1983_Intersil_Data_Book 1983 Intersil Data Book

User Manual: 1983_Intersil_Data_Book

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TABLE OF CONTENTS
G EN ERAL I N FORMATION/CROSS REFERENCES

DISCRETES
DIGITAL

ANALOG SWITCHES AND MULTIPLEXERS
DATA ACQUISITION

D

II
BJ
lEI

II

LINEAR
TIMERS, COUNTERS, AND DISPLAY DRIVERS

Ii]

CONSUMER CIRCUITS

iii

APPEN DICES/PHYSICAL DIMENSIONS

I:)

PRICE: $15.00 (U.S.A.)

ENGINEERING SOLUTIONS ON .A CHIP
FROM INTERSIL
Product offerings described in this data book reflect Intersil's commitment to industry leadership as a producer of advanced low-power analog and digital semiconductor components and data acquisition systems.
These components are fabricated using a wide variety of process technologies and are
intended to provide state-of-the-art performance and maximum cost effectiveness.
Product areas in which Intersil demonstrates its innovative approach to providing
engineering solutions on a chip include:
• FIELD EFFECT AND DUAL MATCHED BIPOLAR TRANSISTORS

A complete line of high-performance junction FETs, dual JFETs, MOSFETs and mat-'
ched dual bipolar devices.
• DIGITAL

Very low-power CMOS ROMs and EPROMs, as well as high-speed HMOS ROMs;
CMOS microprocessors, peripherals and UARTs.
• ANALOG SWITCHES AND MULTIPLEXERS

The industry's broadest offering of highest-performance switches, including a videoRF switch with excellent isolation at 100 MHz, and multiplexers featuring the least error as well as unprecedented input overload protection.
• ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS

3112- and 4112-digit display output (DVM) analog-to-digital converters; 12-, 14- and 16-bit
microprocessor-compatible analog-to-digital converters; and high-speed precision
.
digital-to-analog converters up to 14 bits.
• LINEAR

A new set of low-power devices with unequalled performance-1-J-tV offset voltage op
amps, 4-J-tA quiescent current regulators and supply monitors, 95-per-cent-efficient
voltage converters and 1ppm/oC voltage references; a complete family of CMOS op
amps; and a wide variety of special analog function circuits.
• TIMERS, COUNTERS AND DISPLAY DRIVERS

A wide range of low-power counters, timers and multidigit LED, LCD and vacuum
fluorescent display decoder/drivers, including those with full alphanumeric capability.

Page
Explanation of
Terms, Indices,
and Special
Subsections
A-2

Alphanumeric
Index

A-13

Analog Switch
Cross
Reference

A-21

Data Acquisition
Cross
Reference

A-23

Watch & Clock
Cross
Reference

A-24

Linear Cross
Reference

A-25

A-3

Base Number
Index

A-5

Functional Index

A-7

Obsolete Products
List
A-9
IC Alternate
Source Index

Discrete Cross
Reference

A-10

EXPLANATION OF TERMS, INDICES
AND SPECIAL SUBSECTIONS

m
.

PRODUCTION DATA SHEET
This is a full, final data sheet, and describes a
'. mature product in full production. Although Intersil
reserves the right to make changes in specifications
cOl',1tainedin these data sheets at any time without
notice, such changes are not common and are usual·
Iy lTiinor, generally relating to yield and processing
improvements. These data sheets are not marked;
others are marked preliminary.
PRELIMINARY DATA SHEET
A preliminary data sheet is issued in advance of the
availability of production samples and generally indicates that at the time of printing, the device had
not been fully characterized. In the case of a secondsource part, the specifications are already determined, and a "preliminary" designation indicates the anticipated availability of the device.
ALPHANUMERIC INDEX
This part number index is arranged first by alpha sequence, (ie: ADCxxxx, DGxxx, Gxxx, ICLxxxx, ICMxxxx,
etc.) then by numeric sequence (ie:LM100, LM101A,
LM102, LM105, etc.) and ignoring package/temperature/
pin)number suffixes. The basic numbering sequence,
is sorted by reading the part number characters from
left to right. Reading the left character first (which is
usually an alpha character), then the next character to
the right and so forth.

are organized alphabetically by function. The Func- '
tional Index appears in its entirety in section A,andan
appropriate subindex appears at the beginning of each
major product section.
CROSS-REFERENCE GUIDES
Two cross-reference guides are provided: one for
Discrete Devices and one for Integrated Circuits.
The Discrete Cross-Reference Guide indicates
whether Intersil can provide the industry-standard
type, or an Intersil preferred part instead.
The IC Alternate Source Cross-Reference Guide lists
competitive manufacturer device types for which Intersil makes pin-for-pin replacements. In the left-hand column, the competitive device part number is organized
alphabetically by manufacturer. The Intersil pin-for-pin
replacement appears in the right hand column.
SELECTOR GUIDES
Selector guide tables appear at the front of each major
product category subsection and provides a quick
reference of key parameters for devices contained in
that section.
DEVICE FUNCTION/PACKAGE CODES
Package dimensions and diagrams explaining device
prefix and suffix codes appear in Appendix .B.
DIE SELECTION CRITER1A
Many of Intersil's semiconductor products are
available in die form. This subsection of Appendix B
contains generalinformation on criteria for transistor
and integrated circuit die selection, including physical
parameters, packaging 'for shipment, assembly, testing
and purchase options.

BASE NUMBER INDEX
If only the basic part number is known, use the Base
Number Index as a locator aid. The Base Number Index is organized in numeric sequence (with alpha
prefixes appearing in bold type and numeric
characters set in medium type). Devices are arranged
in this index according to the numeric value of the
first digit on the left, then the value of the second
digit, then the third, and so on. For example, device
number ICM7218 precedes ICL741, no package/temperature/pin number suffixes are included, but these may
be obtained from the specific product data sheet.
FUNCTION INDEX
This is an index of Intersil device types categorized by
product grouping and function. The first major subsection, DISCRETES, is further subdivided into categories
for JFETs and Special Function devices.
All remaining major subsections (ANALOG SWITCHES/MULTIPLEXERS, DATA ACQUISITION, LINEAR,
TI M ERS/COU NTERS, TI M EKEEPI NG/DTM F,
MEMORIES and' MICROPROCESSORS/PERIPHERALS)

HIGH-RELIABILITY PROCESSING
This subsection of Appendix B defines Intersil's commitment to 100 percent compliance with MIL-STD-883,
MIL-STD-750, MIL-M-38510 and MIL-S-19500 specifica'
tions. It also outlines Intersil's programs for quality
conformance, quality testing and limited use qualification and includes a glossary of military/aerospace HiRei terms.
'

Intersil reserves the right to make changes in circuitry or
speCifications contained herein at any time without notice,
Intersil assumes no responsibility lor the use 01 any circuits
described herei n and makes no representations that they are
free patent i nlri ngement.

LIFE SUPPORT POLICY, INTERSIL'S PRODUCTS ARE NOT AUTHORIZED, NOR WARRANTED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
AND/OR SYSTEMS WITHOUT THE EXPRESS WRIDEN APPROVAL OF INTERSIL, INC,
For the purposes of this policy, critical components in Hfe support systems and/or devices are defined as:

1. A critical component is any component of a life support device or system
whose failure to perform can be reasonably expected to cause the failure of
the life support device or system, or to affect its safety or effectiveness.

2. Ufe support devices or systems are devices or systems which, (a) ar~ intended f.or surgical implant into the body, or (b) support or sustain life, and
whose failure to perform, when prop~rly used in accordance with instructions for use provided in the labe,ling, can be- reasonably expected to
result in a significant injury to the user.

Intersi! cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an Intersi! product. No circuit patent licenses are
implied, Intersi! reserves the right to change the circuitry and specifications without notice at any time,

A-2

ALPHANUMERIC INDEX
TYPE 1#

PAGE

TYPE 1#

PAGE

TYPE 1#

PAGE

TYPE 1#

PAGE

2N2607
2N2608
2N2609
2N3684
2N3685

1-9
1-9
1-9
1-10
1-10

2N5115
2N5116
2N5117
2N5118
2N5119

1-37
1-37
1-39
1-39
1-39

3N173
3N188
3N189
3N190
3N191

1-60
1-61
1-61
1-61
1-61

ICH8500
ICH8510
ICH8515
ICH8520
ICH8530

5-208
5-214
5-222
5-214
5-214

2N3686
2N3687
2N3810
2N3811
2N3821

1-10
1-10
1-11
1-11
1-13

2N5196
2N5197
2N5198
2N5199
2N5397

1-40
1-40
1-40
1-40
1-41

/l-A723
!,A733
/l-A740
/l-A741
/l-A748

ICL 101ALN
ICL108ALN
ICL301ALN
ICL308LN
ICL7104

5-46
5-46
5-46
5-46
4-166

2N3822
2N3823
2N3824
2N3921
2N3922

1-13
1-14
1-15
1-16
1-16

2N5398
2N5432
2N5433
2N5434
2N5452

1-41
1-42
1-42
1-42
1-43

/l-A777
AD503
AD590
AD741K
AD7520

5-49

4-138

ICL7106
ICL7107
ICL7109
ICL7115
ICL7116

4-20
4-20
4-30
4-46
4-59

2N3954
2N3955
2N3956
2N3957
2N3958

1-17
1-17
1-17
1-17
1-17

2N5453
2N5454
2N5457
2N5458A
2N5459

1-43
1-43
1-44
1-44
1-44

AD7521
AD7523
AD7530
AD7531
AD7533

4-138
4-144
4-138
4-138
4-148

ICL7117
ICL7126
ICL7129
ICL7134
ICL7135

4-59
4-67
4-75
4-86
4-98

2N3970
2N3971
2N3972
2N3993
2N3994

1-18
1-18
1-18
1-19
1-19

2N5460
2N5461
2N5462
2N5463
2N5464

1-45
1-45
1-45
1-45
1-45

AD7541
ADC0801
ADC0802
ADC0803
ADC0804

4-152
4-4
4-4
4-4
4-4

ICL7136
ICL7137
ICL7145
ICL7146
ICL741HS

4-108
4-116
4-124
4-132
5-44

2N4044
2N4045
2N4091
2N4092
2N4093

1-20
1-20
1-22
1-22
1-22

2N5465
2N5484
2N5485
2N5486
2N5515

1-45
1-46
1-46
1-46
1-47

D123
D125
D129
DG118
DG123

3-9
3-9
3-13
3-6
3-6

ICL741LN
ICL7605
ICL7606
ICL7611
ICL7612

5-46
5-63
5-63
5-73
5-73

2N4100
2N4117
2N4118
2N4119
2N4220

1-23
1-25
1-25
1-25
1-26

2N5516
2N5517
2N5518
2N5519
2N5520

1-47
1-47
1-47
1-47
1-47

DG125
DG1;39
DG142
DG143
DG144

3-6
3-15
3-15
3-15
3-15

ICL7613
ICL7614
ICL7615
ICL7621
ICL7622

5-73
5-73
5-73
5-73
5-73

2N4221
2N4222
2N4223
2N4224
2N4338

1-26
1-26
1-27
1-27
1-28

2N5521
2N5522
2N5523
2N5524
2N5638

1-47
1-47
1-47
1-47
1-49

DG145
DG146
. DG161
DG162
DG163

3-15
3-15
3-15
3-15
3-15

ICL7631
ICL7632
ICL7641
ICL7642
ICL7650

5-73
5-73
5-73
5-73
5-88

2N4339
2N4340
2N4341
2N4351
2N4391

1-28
1-28
1-28
1-29
1-30

2N5639
2N5640
2N5902
2N5903
2N5904

1-49
1-49
1-50
1-50
1-50

DG164
DG180
DG181
DG182
DG183

3-15
3-19
3-19
3-19
3-19

ICL7652
ICL7660
ICL7663
ICL7664
ICL7665

5-96
5-104
5-111
5-111
5-121

2N4392
2N4393
2N4416
2N4856
2N4857

1-30
1-30
1-31
1-32
1-32

2N5905
2N5906
2N5907
2N5908
2N5909

1-50
1-50
1-50
1-50
1-50

DG184
DG185
DG186
DG187
DG188

3-19
3-19
3-19
3-19
3-19

ICL7667
ICL8001
ICL8007
ICL8008
ICL8013

5-128
5-135
5-139
5-142
5-144

2N4858
2N4859
2N4860
2N4861
2N4867

1-32
1-32
' 1-32
1-32
1-33

2N5911
2N5912
2N6483
2N6484
2N6485

1-51
1-51
1-52
1-52
1-52

DG189
DG190
DG191
DG200
DG201

3-19
3-19
3-19
3-28
3-32

ICL8017
ICL8018A
ICL8019A
ICL8020A
ICL8021

5-151
4-158
4-158
4-158
4-155

2N4868
2N4869
2N4878
2N4879
2N4880

1-33
1-33
1-34
1-34
1-34

3N161
3N163
3N164
3N165
3N166

1-56
1-57
1-57
1-58
1-58

DGM181
DGM182
DGM184
DGM185
DGM187

3-23
3-23
3-23
3-23
3-23

ICL8022
ICL8023
ICL8038
ICL8043
ICL8048

5-155
5-155
5-158
5-167
5-174

2N5018
2N5019
2N5114

1-36
1-36
1-37

3N170
3N171
3N172

1-59
1-59
1-60

DGM188
DGM190
DGM191

3-23
3-23
3-23

ICL8049
ICL8Q52A.
ICL8063

5-174
4-166
5-182

•• Obsolete product, refer to page A-9.

A-3

5-28

,

m

11

ALPHANVMERIC INDEX
TYPE #

PAGE

TYPE #

PAGE

TYPE #

PAGE

TYPE #

PAGE

2·11
2·18
2·21
2·24
1·54

LH2308
LH2310
LH2311
LM100
LM101A

5·55

ICL8068
ICL8069
ICL8075
ICL8076
ICL8077

4·166
5·190
5·192
5·192
5·192

IH5017
IH5018
IH5019
IH5020
IH5021

3·36
3·36
3·36
3·36
3·36

IM6654
IM7332
IM7364
IM82C43
IMF6485

ICL8078
ICL8079
ICL8211
ICL8212
ICM1115

5·192
5·192 .
5·198
5·198
7·19

IH5022
IH5023
IH5024
IH5025
IH5026

3·36
3·36
3·36
3·41
3·41

IT100
IT101
IT120
IT121
IT122

1·64
1·64
1·65
1·65
1·65

LM102
LM105
LM107
LM108
LM110

ICM7038
ICM7045
ICM7050
ICM7051

7·5
7·10
7·19
7·23

ICM7070
ICM7201
ICM7206
ICM7207
ICM7207A

7·27

IH5027
IH5028
IH5029
IH5030
IH5031

3·41
3-41
3·41
3·41
3·41

IT124
IT126
IT127
IT128
IT129

1·66
1·67
1·67
1·67
1·67

LM111
LM114
LM300
LM301A
LM302

7·31
6·3
6·3

ICM7208
ICM7209
ICM7211
ICM7212
ICM7213

6·7
7·39
6·14
6·14
7·42

IH5032
IH5034
IH5035
IH5036
IH5037

3·41
3·41
3·41
3·41
3·41

IT130
1T131
IT132
IT136
IT137

1·68
1·68
1·68
1·69
1·69

LM305
LM307
LM308.
LM310
LM311

ICM7215
ICM7216
ICM7217
ICM7218
ICM7223

7·47
6·24
6·39
6,55
7·53

IH5038
IH5040
IH5041
IH5042
IH5043

3·41
3·48
3·48
3·48
3·48

IT138
IT139
IT1700
IT1750
IT500

1·69
1·69
1·75
1·76
1·71

LM4250
M116
NE536
NE/SE592
NE592·8

7·59
7·67
6·64
6-64
6·72

3·48
3·48
3·48
3·48
3·48

IT501
IT502
IT503
IT504
IT505

1·71
1·71
1·71
1·71
1·71

OP05
OP07
SU536
U1897
U1898

5·8
5·16

ICM7223A
ICM7223VF
ICM7224
ICM7225
ICM7226

IH5044
IH5045
IH5046
IH5047
IH5048

ICM7227
ICM7231
ICM7232
ICM7233
ICM7234

6·39
6·84
6·84
6·84
6·84

IH5049
IH5050
IH5051
IH5052
IH5053

3·48
3·.48
3·48
3·56
3·56

IT550
IT5911
IT5912
ITE4091
ITE4092

1·74
1·51
1·51
1·22
1·22

U1899
U200
U201
U202
U231

1·92
1·85
1·85
1·85
1·86

ICM7235
ICM7236
ICM7240
ICM7241
ICM7242

6·104
6·110
6·116
7·75
6·127

IH5101
IH5108
IH5110
IH5111
IH5112

3·63
5·57
5·57
5·57

ITE4093
ITE4391
ITE4392
ITE4393
ITE4416

1·22
1·30
1·30
1·30
1·31

U232
U233
U234
U235
U257

1·86
1·86
1·86
1·86
1·87

ICM7243
ICM7245
ICM7250
ICM7260
ICM7281

6·133
7·77
6·116
6·116
6·143

IH5113
IH5114
IH5115
IH5140
IH5141

5·57
5·57
5·57
3·71
3·71

J105
J106
J107
J111
J112

1·77
1·77
1·77
1·78
1·78

U304
U305
U306
U308
U309

1-88
1-88
1·88
1·89
1·89

ICM7555
ICM7556
ID100
10101
IGC10000

6·155
6·155
1·62
1·62
2·34

IH5142
IH5143
IH5144
IH5145
IH5200

3·71
3·71
3·71
3·71
3·28

J113
J174
J175
J176
J177

1·78
1·79
1·79
1·79
1·79

U310
U401
U402
U403
U404

1·89
1·90
1·90
1·90
1·90

IH5009
IH5010
IH5011
IH5012
IH5013

3·36
3·36
3·36
3·36
3·36

IH5201
IH5208
IH5341
IH6108
IH6116

3·32
3·79
3·87
3·93
3·99

J201
J202
J203
J204
J308

1·80
1·80
1·80
1·80
1·82

U405
U406
VCR2N
VCR3P
VCR4N

1·90
1·90
1·92
1·92
1·92

IH6201
IH6208
IH6216

3·105
3·109
3·115

1·82
1·82

VCR7N

1·92

IH5014
IH5015
IH5016

3·36
3·36
}·36

IM6402
IM6403
IM6653

2·3
2·3
2·11

J309
J310
LH0042
LH2101A
LH2108
LH2110
LH2111
LH2301A

• 'Obsolete product, refer to page A·9.

A·4

5·55

5·24

1·83

5·24

1·84
5·38
5·41

1·92
1·92

BASE NUMBER INDEX
TYPE #
LH
OP
OP
ADC
ADC
ADC
ADC
ID
IT
'LM
ICL
ID
IT
LM
LM
J

LM
J
J

LM
ICL
LM
LM
J

LM
ICM
J
J

LM

M

DG
IT
IT
IT
D

DG
IT
D

0042
05
07
0801
0802
0803
0804
100
100
100
101ALN
101
101
lOlA
102
105
105
106
107
107
108ALN
108
110
111
111
1115
112
113
114
116
118
120
121
122
123
123
124
125
125
126

DG
IT
IT 127
IT 128

D 129

IT
IT
IT
IT
IT
IT
IT
IT
DG
DG
DG
DG
DG
DG
3N
DG
DG
3N
DG
3N

129
130
131
132
136
137
138
139
139
142
143
144
145
146
161
161
162
163
163
164

PAGE
5·8
5·16
4·4
4·4
4·4
4·4
1·62
1·64
5·46
1·62
1·64
1·77
1·77
1·77
5·46
5·24

..

1·78
'

7·19
1·78
1·78
1·83
1·84
3·6
1·65
1-65
1·65
3·9
3·6
1·66
3·9
3·6
1·67
1·67
1·67
3·13
1·67
1·68
1·68
1·68
1·69
1·69
1·69
1·69
3·15
3·15
3·15
3·15
3·15
3·15
1·56
3·15
3·15
1·57
3·15
1·57

TYPE #
DG 164
3N 165
3N 166
3N 170
IT 1700
3N 171
3N 172
3N 173
J 174
J 175
IT 1750
J 176
J 177
DG 180
DG 181
DGM 181
DG 182
DGM 182
DG 183
DG 184

DGM
DG
DGM
DG
DG
DGM
3N
DG
DGM
3N
DG
U
U
U

184
185
185
186
187
187
188
188
188
189
189
1897
1898
1899
190
190
190
191
191
191

3N
DG
DGM
3N
DG
DGM
VCR 2N
DG 200
U 200

DG 201
J 201

U 201

J 202
U 202
J 203
J 204
LH 2101A
LH 2108
LH 2110
LH 2111
LH 2301A
LH 2308
U 231
LH 2310
LH 2311
U 232
U 233
U 234
U 235

TYPE #

PAGE

U 257

3·15
1·58
1·58
1·59
1·75

2N
2N
2N
VCR
LM
LM
ICL
LM

2607
2608
2609
3P
300
301A
301ALN
302
U 304

1·59
1·60
1·60
1·79
1·79
1·76
1·79
1·79
3·19
3·19
3·23
3·19
3·23
3·19
3·19

LM 305
U 305
U 306

LM 307
ICL 308LN
J 308
LM 308
U 308
J 309
U 308
J 310
LM 310
U 310
LM 311
2N 3684
2N 3685
2N 3686
2N 3687
2N 3810
2N 3811
2N 3821
2N 3822
2N 3823
2N 3824
2N 3921
2N 3922
2N 3954
2N 3955
2N 3956
2N 3957
2N 3958
2N 3970
2N 3971
2N 3972
2N 3993
2N 3994
VCR 4N
U 401
U 402
U 403
U 404
2N 4044
2N 4045
U 405
U 406
2N 4091
ITE 4091
2N 4092
ITE 4092
2N 4093
ITE 4093
2N 4100
2N 4117

3·23
3·19
3·23
3·19
3·19
3·23
1·61
3·19
3·23
1·61
3·19
1·92
1·92
1·92
1·61
3·19
3·23
1·61
3·19
3·23
1·92
3·28
1·85
3·32
1·80
1·85
1·80
1·85
1·80
1·80
5·55

5·55
1·86
1·86
1·86
1·86
1·86

•• Obsolete product, refer to page A·9.

A·5

PAGE
1·87
1·9
1·9
1·9
1·92
5·46
1·88
1·88
1·88
5·46
1·82
5·24
1·89
1·82
1·89
1·82
1·89
1·10
1·10
1·10
1-10
1·11
1·11
1·13
1·13
1-14
1·15
1·16
1·16
1·17
1·17
1·17
1·17
1·17
1-18
1·18
1·18
1·19
1·19
1·92
1·90
1·90
1·90
1·90
1·20
1·20
1·90
1·90
1·22
1·22
1·22
1·22
1·22
1·22
1·23
1·25

tYPE #
2N
2N
2N
2N
2N
2N
2N
LM
2N
2N
2N
2N
2N
2N
ITE
2N
ITE
2N
ITE
2N
ITE
2N
2N
2N
2N
2N
2N
2N
2N
2N
2N
2N
2N
IT
IH
IT
IH
IH
IH
IH
IH
IH
IH
IH
2N
IH
2N
IH
IT
IH
IH
IH
IH
IH
IH
IH
IH
IH
IH
AD
IT

4118
4119
4220
4221
4222
4223
4224
4250
4338
4339
4340
4341
4351
4391
4391
4392
4392
4393
4393
4416
4416
4856
4857
4858
4859
4860
4861
4867
4868
4869
4878
4879
4880
500
5009
501
5010
5011
5012
5013
5014
5015
5016
5017
5018
5018
5019
5019
502
5020
5021
5022
5023
5024
5025
5026
5027
5028
5029
503
503

PAGE
1·25
1·25
1·26
1·26
1·26
1·27
1·27
1·28
1·28
1·28
1·28
1·29
1·30
1·30
1·30
1·30
1·30
1·30
1·31
1·31
1·32
1·32
1·32
1·32
1·32
1·32
1·33
1·33
1·33
1·34
1·34
1·34
1·71
3·36
1·71
3·36
3·36
3·36
3·36
3·36
3·36
3·36
3·36
1·36
3·36
1·36
3·36
1·71
3·36
3·36
3·36
3·36
3·36
3·41
3·41
3·41
3·41
3·41
1·71

PI

It

BASE NUMBER INDEX
TYPE #

PAGE

TYPE #

TYPE #

PAGE

PAGE

TYPE #

PAGE

IH
IH
IH
IH
IH

5030
5031
5032
5034
5035

341
3·41
3·41

2N
2N
2N
2N
2N

5458
5459
5460
5461
.5462

1·44
1·44
1·45
1·45
1·45

ICL
ICL
ICL
ICL
ICL

7109
7115
7116
7117
7126

4·30
4·46
4·59
4·59
4·67

ICM
ICM
ICL
ICL
ICL

7555
7.556
7605
7606
7611

6·143
6·143
5·63
5·63
5·73

IH
IH
IH
IT
IH

5036
5037
5038
504
5040

3·41
3·41
3·41
1-71
3·48

2N
2N
2N
2N
2N

5463
5464
5465
5484
5485

1·45
1·45
1·45
1·46
1·46

ICL
ICL
ICL
ICL
ICL

7129
7134
7135
7136
7137

4·75
4·86
4·98
4·108
4·116

ICL
ICL
ICL
ICL
ICL

7612
7613
7614
7615
7621

5·73
5'73
5·73
5·73
5·73

IH
IH
IH
IH
IH

5041
5042
5043
5044
5045

3·48
3·48
3·48
348
3·48

2N
IT
2N
2N
2N

5486
550
5515
5516
5517

1·46
1·74
1·47
1·47
1·47

ICL
ICL
ICM
ICM
ICM

7145
7146
7201
7206
7207

4·124
4·132
7·31
6·3

ICL
ICL
ICL
ICL
ICL

7622
7631
7632
7641
7642

5·73
5·73
5·73
5·73
5.73

IH
IH
IH
IH
IT

5046
5047
5048
5049
505

3·48
3·48
3·48
3·48
1·71

2N
2N
2N
2N
2N

5518
5519
5520
5521
5522

1·47
1·47
1·47
1·47
1·47

ICM
ICM
ICM
ICM
ICM

7207A
7208
7209
7211
7212

6·3
6·7
7·39
6·14
6·14

ICL
ICL
ICL
ICL
ICL

7650
7652
7660
7663
7664

5·88
5·96
5·104
5·111
5·111

IH
IH
IH
IH
IH

5050
5051
5052
5053
5101

3·48
3·48
3·56
3·56

2N
2N
2N
2N
2N

5523
5524·
5638
5639
5640

1·47
1·47
1·49
1·49
1·49

ICM
ICM
ICM
ICM
ICM

7213
7215
7216
7217
7218

7·42
7·47
6·24
6.39
6·55

ICL
ICL
p.A
ICL
ICL

7665
7667
777
8001
8007

5·121
5·128
5·49
5·135
5·139

IH
IH
IH
IH
IH

5108
5110
5111
5112
5113

3·63
5·57
5·57
5·57
5·57

AD
2N
2N
2N
2N

590
5902
5903
5904
5905

5·28
1·50
1·50
1.50
1·50

ICM
ICM
ICM
ICM
ICM

7223
7223A
7223VF
7224
7225

7·53
7·59
7·67
6·64
6·64

ICL
ICL
ICL
ICL
ICL

8008
8013
8017
8018A
8019A

5·142
5·144
5·151
5:158
5·158

2N
IH
2N
IH
2N

5114
5114
5115
5115
5116

1·37
5·57
1·37
5·57
1·37

.2N
2N
2N
2N
2N

5906
5907
5908
5909
5911

1·50
1·50
1·50
1·50
1·51

ICM
ICM
{"A
ICM
ICM

7226
7227
723
7231
7232

6·72
6·39
6·84
6·84

ICL
ICL
ICL
ICL
ICL

8020A
8021
8022
8023
8038

5·158
5·155
5·155
5·155
5·158

2N
2N
2N
IH
IH

5117
5118
5119
5140
5141

1·39
1·39
1·39
3·71
3·71

IT
2N
IT
NE/SE
NE

5911
5912
5912
592
592·8

1·51
1·51
1·51
5·38
5·41

ICM
ICM
ICM
ICM
ICM

7233
7234
7235
7236
7240

6·84
6-84
6·104
6·110
6·116

ICL
ICL
ICL
ICL
ICL

8043
8048
8049
8052A
8063

5·167
5·174
5·174
4·166
5·182

IH
IH
IH
IH
2N

5142
5143
5144
5145
5196

3·71
3·71
3·71
3·71
1·40

IH
IH
IH
IH
IH

6108
6116
6201
6208
6216

3·93
3·99
3·105
3·109
3·115

ICM
ICM
ICM
ICM
ICM

7241
7242
7243
7245
7250

7·75
6·127
6·133
7·77
6·116

ICL 8068
ICL 8069
ICL
ICL
ICt 8077

4.·166
5·190
5·192
5·192
5·192

2N
2N
2N
IH
IH

5197
5198
5199
5200
5201

1·40
1·40
1·40
3·28 .
3.32

1M
1M
2N
2N
2N

6402
6403
6483
6484
6485

2·3
2·3
1·52
1·52
1·52

ICM
ICM
{"A
1M
1M

7260
7281
733
7332
73.64

6·116
6·143

ICL
ICL
1M
ICL
ICL

8078
8079
82C43
8:111
8212

5·192
5·192
2·24
5·198
5·198

IH
IH
NE
SU
'2N

5208
5341
536
536
5397

3·79
3·87

IMF
1M
1M
VCR
ICM

6485
6653
6654
7N
7038

1·54
2·17
2·17
1·92
7·5

p.A
p.A
ICL
AD
ICL

740
741
741HS
741K
741LN

5·46

ICH
ICH
ICH
ICH
ICH

8500
8510
8515
8520
8530

5·208
5·214
5·222
5·214
5·214

2N
2N
2N
2N
2N

5398
5432
5433
5434
5452

1·41
142
1·42
1·42
1·43

ICM
ICM
ICM
ICM

7045
7050
7051
7070

7·10
7·19
7·23
7·27

p.A
AD
AD
AD
AD

748
7520
7521
7523
7530

4·138
4·138
1-144
4·138

2N 5453
2N 5454
2N 5457

1·43
1·43
1·44

AD 7531
AD 7533
AD 7541

4·138
4.148
4·152

3·41
3·4~

1·41

ICL 7104
ICL 7106
ICL 7107

4'166
4·20
4·20

• 'Obsolete product, refer to page A·9.

A·6

2·18
2·21

5·44

~~~~

IGC 10000

2·28

.
f'

FUNCTIONAL INDEX

DISCRETES
JFET Single
Switches
N·Channel
2N3970·72
2N4091·93
2N4491·93
2N4856·61
2N5432·34
2N5638·40
ITE4091·3
ITE4391·3
J105·V
J111·-t3
U200·2
U1897·99
P-Channel
2N3993/4
2N5018/19
2N5114·16
1T100/1
J174·77

Page
1-18
1·22
1·30
1·32
1·42
1·49
1·22
1·30
1·77
1-78
1·85
1·92
1·19
1·36
1·37
1·64
1·79

JFET Single
Amplifiers
N-Channel
2N3684·87
2N3821 122
2N3823
2N3824
2N4117·19
2N4220·22
2N4223/24
2N4338·41
2N4416
2N4867·69
2N5397/98
2N5457·59
2N5484·86
ITE4416
J201·4
J308·10
U308·10
P-Channel
2N2607·9
2N5460·65
U304·6

1·10
1·13
1·14
1·15
1·25
1·26
1·27
1·28
1·31
1·33
1·41
1·44
1·46
1·31
1·80
1·82
1·89

1·43
1·47
1·50
1·51
1·52
1·54
1·71
1·74
1·51
1·86
1·87
1·90

N·Channel
2N4351
3N170/1
IT1750
M116
P-Channel
3N161
3N163/64
3N172/73
1T1700
Dual P-Channel
3N165/66
3N188·91

Video/RF Switch

Memory

IH5341

,

2·18
2·21
2·11
2·28

Peripherals
IM6402/3
IM82C43

2·3
2·24

1·29
1·59
1·76
1·84

ANALOG
SWITCHES AND
MULTIPLEXERS

1·56
1·57
1·60
1·75

Multiplexers

1·58
1·61

Bipolar Dual
Amplifiers
NPN Devices
2N4044/45
2N4100
2N4878·80
IT120·22
IT124
IT126/29
LM114
PNP Devices
2N3810/11
2N5117·19
IT130·32
IT136·39

DIGITAL
NMOS ROMs
IM7332
IM7364
CMOS EPROMs
IM6653/4
Gate Arrays
IGC10000

MOSFET Switchesl
Amplifiers

1·20
1·23
1·34
1·65
1·66
1·67
1·83
1-11
1·39
1·68
1·69

Special Function
1·9
1·45
1·88

JFET Dual
Amplifiers
N-Channel
2N3921/22
2N3954·58
2N5196·99

2NS452·54
2N5515·24
2N5902·9
2N5911/12
2N6483·85
IMF6485
IT500·5
IT550
IT5911/12
U231·35
U257
U401·6

High Speed Dual Diodes
1,62
10100/1
Voltage Controlled
Resistors
VCR2·7
1·92

IH5108
IH5208
IH6108
IH6116
IH6208
IH6216

3·63
3·79
3·93
3·99
3·109
3·115

DATA
ACQUISITION
AID Converters
DVM Circuits
AOC080H
ICL7106/7
ICL7109
ICL7115
ICL7116/17
ICL7126
ICL7129
ICL7135
tlCL7136
ICL7137
ICL8052A/7104
ICL8068/7104

D/A Converters

Analog Switch
Driversl
Level Trans.lators
0123/125
0129
IH6201

D/A Current
Switches
ICL8018A/19A/20A

Analog Switches
with Drivers
OG 118/123/125
OG139A Family
OG180 Family
OGM181 Family
OG200
OG201
IH5009·24
IH5025·38
IH5040·51
IH5052/3
IH5140·45
IH5200
IH5201

1·16
1·17
1·40
A'7

3·6
3·15
3·19
3·23
3·28
3·32
3·36
3·41
3·48
3·56
3·71
3·28
3·32

4·4
4·20
4·30
4·46
4·59
4·67
4·75
4·98
4·108
4·116
4·166
4·166

tThe ICL7136 is recom·
mended for all applica·
lions which currently
employ the ICL7126.

A07520/21 130/31
A07523
A07533
A07541
ICL7134
ICL7145
ICL7146

3·9
3·13
3·105

3·87

4·138
4·144
4·148
4·152
4·86
4·124
4·132

4·158

LINEAR
Amplifiers
Driver Amplifier for
Power Transistors
5·182
ICL8063
Driver Amplifier for
Actuators, Motors
5·214
ICH8510/20/30
5·222
ICH8515
Instrumentation
Com mutating Auto-Zero
ICL7605/6
5·63
Log-Antilog
ICL8048/49
5·174
Operational,
Chopper Stabilized
ICL7650
5·88
ICL7652
5·96

m

rt.1

FUNCTIONAL INDEX
Operational, FET Input
LH0042
AD503
SU/NE536
p,A740
ICL8007
5·139
ICL8043
5·167
ICH8500
5·208
Operational, General
Purpose

Voltage Reference

Display Drivers

ICL8069
ICL8075·9
ICL8211/12

ICM7211/12
ICM7218
ICM7231·34
ICM7235
ICM7243
ICM7281

p,A723
ICL7663/64

OP~5

5~

OP·07

5·16

LM101/301
LM 107/307
LM 108/308

5·24

,p,A741
ICL741HS
5·44
AD741K
ICL741LN
5·46
, p,A748
5·49
p,A777
LH2101/2301
LH21 08/2308
5·55
IH5101
ICL8008
5·142
Operational, High Speed
ICL8017
5·151
Operational, Low Power
LM4250
**
ICL76XX Series
5·73
ICL8021·23
5·155
Video
p,A733
NE/SE592
5·38
NE592·8
5·41
Voltag~ Followers
LM 102/302
LM110/310

Voltage
Regulators .'
LM105/305

5·135

ICM7223
ICM7223A
ICM7223VF

5·57

Temperature
Sensor

ICM1115
ICM7038
ICM7050
ICM7051
ICM7070
ICM7245

ICM7207/A

7·19
7·5
7·19
7·23
7·27
7·77

Clock Generators
ICM7209
ICM7213

7·39
7·42

Frequency Divider
ICM7241

6·116
6·127
6·155
6·155

7·75

Touch Tone
Encoder
ICM7206

6·7
6·24
6·39
6·64
6·72
6·110

Counter
Timebase
5·28

7·53
7·59
7·67

Analog
Watches/Clocks

Counters
ICM7208
ICM7216
ICM7217/27
ICM7224/25
ICM7226
ICM7236

7,10
7·47

Display
Watches/Clocks

TIMERS,
COUNTERS, AND
DISPLAY
DRIVERS

Sample and Hold

AD590

ICM7045
ICM7215

-Not recommended for
new designs. Use
ICL8211/12 or ICL7665.

ICM7242
ICM7555
ICM7556

6~55

6·84
6·104
6·133
6·143

Stopwatches

Multiplier
ICL8013
5·144
Voltage Converter
5·104
ICL7660
Waveform Generator
5·158
ICL8038
Low Battery Detectors
*ICM7201
5·121
ICL7665
ICL8211/12
5·200
Dual Power MOS Driver
ICL7667
5·128

Comparators

IH5110·15

5·111

Special Function

ICM7240/50/60

6·14

TIMEKEEPING,
DTMF CIRCUITS

LM 100/300

Timers

LH2110/2310

Dual
LH2111/2311
low Power
ICL8001
Precision
LM111/311

5·190
5·192
5·198

6·3

"Obsolete product, refer to page A·9,

A·8

7·31

OBSOLETE PRODUCTS
The products listed below have been designed into circuits in the past, but are no longer likely to be the most economic choice for new designs.
These products are still available for use in existing designs. Data sheets for these products
are available upon request.
'
AM2502/3/4
AM25L02/3/4
DG126A Family
G115/123
G116-19
G125-32
ICL7600101
ICL8052/7101
ICL8052/71 C03
ICL8068/71 C03
ICL8052/53
IH401
IMF5911/12
LD110/111
LD114
MM450/550
MM451/551
MM452/552
MM455/555
VCR5P
LH0042

AD503
SU/NE536
p,A740
LM101/301
LM 107/307
p,A741
AD741K
p,A748
LH2101/2301
IH5101
LM4250
p,A733
LM 102/302
LM110/310
LH2110/2310
LH2111/2311
LM111/311
LM100/300
LM105/305
fJ-A723
ICM7201

A-9

IC ALTERNATIVE SOURCE INDEX

m

AMD

Intersil

AM9232
AM9264
LH2101
LH2301
LH2311
LM10l
LM102
LM105
LM107
LM10B
LMll0
LMlll
LM301
LM302
LM305
LM307
LM308
LM310
LM311
723
733
741
748

IM7332
IM7364
LH2101
LH2301
LH2311
LM10l
LM102
LM105
LM107
LM108
LMll0
LMlll
LM301
LM302
LM305
LM307
LM308
LM310
LM311
r A723
rA733
rA741
rA748

AMI
S68332
S68364

Intarsil
IM7332
-IM7364

Analog Devices

Intersil

AD10l
AD108
AD301
AD308
AD503
AD590
AD741
AD75061COMICHIPS
AD75061MIUCHIPS
AD7506JD
AD7506JDIBB3B
AD7506JN
AD750BKD
AD75OBKDI883B
AD7506KN
AD7506SD
AD7506SD1883B
AD7506TD
AD7506TD1883B
AD75071COMICHIPS
AD75071MIUCHIPS
AD7507JD
AD7507 JDI883B
AD7507JN
AD7507KD
AD7507KDI883B
AD7S07KN
AD7507SD
AD7507SD1883B
AD7507TD
AD7507TD1883B
AD7520JD
AD7502JN
AD7520KD
AD7520KN
AD7520LD
AD7520LN
AD7520SD
AD7520TD
AD7520UD
AD7521JD
AD7521JN
AD7521KD
AD7521KN
AD7S21LD
AD7521LN
AD7521SD
AD7521TD
AD7521UD
AD7523AD
AD7523BD
AD7523CD
AD7523JN
AD7523KN
AD7523LN
AD7523SD
AD7523TD
AD7523UD
6,D7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD
AD7530LN
AD7531JD
AD7531JN

LM10l
LM108
LM301
LM30B
AD503
AD590
r A741
IH6116CID
IH6116MID
IH6116CJI
IH6116JI1883B
IH6116CPI
IH6116CJI
IH6116CJI1883B
IH6116CPI
IH6116MJI
IH6116MJI1883B
IH6116MJI
IH6116MJI1883B
IH6216CID
IH6216MID
IH6216CJI
IH6216CJI1883B
IH6216CPI
IH6216CJI
IH6216CJI1883B
IH6216CPI
IH6216MJI
IH6216MJI1883B
IH6216MJI
IH6216MJI1883B
AD7520JD
AD7520JN
AD7520KD
AD7520KN
AD7520LD
AD7520LN
AD7520SD
AD7520TD
AD7520UD
AD7521JD
AD7521JN
AD7521KD
AD7S21KN
AD7521LD
AD7521LN
AD7521SD
AD752.1TD
AD7521UD
AD7523AD
AD7523BD
AD7523CD
AD7523JN
AD7523KN
AD7523LN
AD7523SD
AD7523TD
AD7523UD
AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD
AD7530LN
AL>7531JD
AD7531JN

AD7531KD
AD7531KN
AD7531LD
AD7531LN
AD7533AD
AD7533BD
AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD
AD7533UD
AD7541AD
AD7541BD
AD7541JN
AD7541 KN
AD7541SD
AD7541TD

AD7531KD
AD7531KN
AD7531LD
AD7531LN
AD7533AD
AD7533BD
AD7533CD
AD7533JN
AD7533KN
AD7533LN
AD7533SD
AD7533TD
AD7533UD
AD7541AD
AD7541BD
AD7541JN
AD7541KN
AD7541SD
AD7541TD

Commodore

I"tarsit

2332
2364

IM7332
IM7364

Datel

Intersi!

AMC-8013
DAC7520
DAC7521
DAC7523
DAC7533
D1IC7541
n-590
WG-8038
VR-8069

ICL8013
AD7520
AD7521
AD7523
AD7533
AD7541
AD590
ICL803B
ICLB069

Eurosil

Intersi!

Ell15
El151

ICMll15A
ICMll15B

Exar

tntarsit

XR2240
XR8038
XRL555
XRL556
XR2242

ICM7240
ICL8038
ICM7555
ICM7556
ICM7242

Fairchild

Intarsil

r A101
rAl02
rA105
rA107
rA108
pAllO
pAlll
rA301
rA302
rA305
rA307
rA308
r A310
rA311
rA723
rA733
rA740
rA741
I,A74B
rA777

LM10l
LM102
LM105
LM107
LM108
LMll0
LMll1
LM301
LM302
LM305
LM307
LM308
LM310
LM311
.A723
.I(~733

rA740
rA741
rA748
ItA???

GI

I"tersil

9332
9364

IM7332
IM7364

GTE

Intarsil

2114
2332
2364

2114
IM7332
IM7364

Harris

InlersH

HA2720
HD6402
H 10-0200-6 .
Hll-0200-2
Hll-0200-4
Hll-0200-5
Hll-0200-8
HI2-0200-2
HI2-0200-4
HI2-0200-5
HI2-0200-8
HI3-0200-5
HI0-0201-6
Hll-0201-2
Hll-0201-4

ICL8021
IM6402
DG200BID
DG200AK
DG200BK
DG200BK
DG200AKI833B
DG200AA
DG200BA
DG200BA
DG200AAI883B
DG200CJ
QG201BID
DG201AK
DG201BK

A·10

Hll-0201-5
Hll-0201-8
HI3-0201-5
HI0-050B-6
Hll-05OB-2
Hll-0508-5
Hll-050B-8
HI3-0508-5
HI0-0508A-6
Hll-050BA-2
Hll-05OBA-5
Hll-0508A-8

DG201BK
DG201AKI883B
DG201CJ
IH610BCID
IH610BMJE
IH610BCJE
IH6108MJEIB83B
IH6108CPE
IH5108CID
IH510BMJE
IH510BIJE
IH510BMJEIBB3B

HI3-0508A-5
HI0-0509-6
Hll-0509-2
Hll·0509-5
Hll-0509-8
HI3-0509-5
HI0-0509A-6
Hll-0509A-2
Hll-0509A-5
Hll-0509A-8

IH5108CPE
IH6208CID
IH620BMJE
IH620BCJE
IH6208MJEI883B
IH6208CPE
IH5208CID
IH5208MJE
IH52081JE
IH5208MJEI883B

HI3-0509A-5
HIO-0506-6
Hll-0506-2
Hll-0506-5
HI 1-0506-8
HI3-0506-5
HI0-0507-6
Hll-0507-2
Hll-0507-5
Hll-0507-8
HI3-0507-5

IH5208CPE
IH6116CID
IH6116MJI
IH6116CJI
IH6116MJI1883B
IH6116CPI
IH6216CID
IH6216MJI
IH6216CJI
IH6216MJIIB83B
IH6216CPI

HI0-5040-6
HI1-5040-2
HI1-5040-5
HI1-5040-B
HI0-5041-6
HI1-5041-2
HI1-5041-5
HI1-5041-8
HI0-5042-6
HI1-5042-2
HI1-5042-5
HI1-5042-8
HI0-5043-6
HI1-5043-2
HI1-5043-5
HI1-5043-8
HI0-5044-6
HI1-5044-2
Hll·5044-5
HI1-5044-B
HI0·5045-6
Hll-S045-2
Hll-S04S-S
HI1-5045-B
HI0-S046-6
HI1-5046-2
Hll-S046-5
HI1-5046-8
HI0-5047-6
Hll-S047-2
HI1-5047-5
HI1-5047-8
HI0-5048-6
HI1-5048-2
HI1-5048-5
HI 1-5048-8
HI0-5049-6
HI1-5049-2
HI 1-5049-5
HI1-5049-8
HI0-S050-6
HI 1-5050-2
Hll-S050-5
HI 1-5050-8
HI0-5051-6
HI1-5051-2
HI1-5051-5
HI1-5051-8
LM10l
LM4250

IH5040CID
IH5040MJE
IH5040CPE
IH5040MJEI883B
IH5041CID
IH5041MJE
IH5041CPE
IH5041 MJEI883B
IH5042CID
IH5042MJE
IH5042CPE
IH5042MJEI883B
IH5043CID
IH5043MJE
IH5043CPE
IH5043MJEI883B
IH044CID
IH5044MJE
IH5044CPE
IHS044MJEI883B
IH504SCID
IHS045MJE
IHS04SCPE
IH5045MJEIB83B
IH5046CID
IH5046MJE
IH5046CPE
IH5046MJEI8B3B
IH5047CID
IH5047MJE
IHS047CPE
IHS047MJEI883B
IH5048CID
IH5048MJE
IH5048CJE,CPC
IH5048MJEI883B
IH5049CID
IH5049MJE
IH5049CJE,CPE
IH5049MJEI883B
IH5050CID
IH5050MJE
IH5050CJE,CPE
IH5050MJEI883B
IH5051CID
IH5051MJE
IH5051CJE,CPE
IH5051 MJEI883B
LM10l
LM4250

MicroPower
Systems

Intersll

MP7520JD
MP7520JN
MP7520KD
MP7520KN
MP7520LD
MP7520LN
MP7520SD
MP7520TD

AD7520JD
AD7520JN
AD7520KD
AD7520KN
AD7520LD
AD7502LN
AD7520SD
AD7520TD

Ie Alternate Source Index (continued)
continued

MP7520UD
MP7521JD
MP7521JN
MP7521KD
MP7521KN
MP7521lD
MP7521lN
MP7521SD
MP7521TD
MP7521UD
MP7523JN
MP7523KN
MP7523lN
MP7530JD
MP7530JN
MP7530KD
MP7530KN
MP7530lD
MP7530lN
MP7531JD
MP7531JN
MP7531KD
MP7531KN
MP7531lD
MP7531lN
MP7533AD
MP7533BD
MP7533CD
MP7533JN
MP7533KN
MP7533lN
MP7533SD
MP7533TD
MP7533UD
MP7621AD
MP7621 BD
MP7621JN
MP7621KN
MP7621SD
MP7621TD

AD7520UD
AD7521JD
AD7521JN
AD7521 KD
AD7521KN
AD7521 lD
AD7521lN
AD7521SD
AD7521TD
AD7521UD
AD7523JN
AD7523KN
AD7523lN
AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530lD
AD7530lN
AD7531JD
AD7531JN
AD7531KD
AD7531KN
AD7531lD
AD7531 IN
AD7533AD
AD7533BD
AD7533CD
AD7533JN
AD7533KN
AD7533lN
AD7533SD
AD7533TO
AD7533UD
AD7541AD
AD7541BD
AD7541JN
AD7541lN
AD7541SD
AD7541TD

Mitsubishi

M58435P

1"lersii
ICMll 15B

Motorola

Intersil

lMl01
lMl05
lMl07
lMllO
lMl11
LM301
lM305
lM307
LM308
LM310
LM311
MCM68332
MCM68364
MC1723
MC1741
MC1748
MHW590

lMl01
lMl05
lMl07
lMll0
lMll1
lM301
lM305
lM307
lM308
lM310
lM311
IM7332
IM7364
I.A 723
.A741
.A748
AD590

Netlonal
Semiconductor

Intarsil

AD7520JD (DAC 1022LCD)
AD7520JN (DAC1022LCNI
AD7520KN (DAC1021LCDI
AD7520KN (DAC1021lCNI
AD7520LD (DAC1020LCD)
AD7520LN (DAC1020LCN)
AD7520SK (DAC1022lDI
AD7520TO (DAC1021LD)
AD7520UD (DAC1020lDI
AD7521JD (DAC1222LCD)
AD7521JN (DAC1222lCN)
AD7521KD (DAC1221LCD)
AD7521KN (DAC1221lCN)
AD7521LD (DAC1220lCD)
AD7521lN (DAC I 220lCNI
AD7521 SD (DAC 1222lD)
AD7521TD (DAC1221lD)
AD7521UD (DAC1220lD)
AD7530JD (DAC1022lCD)
AD7530JN (DAC1022lCN)
AD7530KD (PAC1021 LCD)
AD7530KN (DAC 1021lCN)
AD7530lD (DAC1020LCD)
AD7530lN (DAC 1020LCN)
AD7531JD (DACl222lCD)
AD7531JN (DAC1222lCN)
AD7531KD (DAC1221 LCD)
AD7531KN (DAC1221lCN)
AD7531lD (DAC 1220lCDI

AD7520JD
AD7520KD
AD7520KD
AD7520KN
AD7520lD
AD7520LN
AD7520SD
AD7520TO
AD7520UD
AD7521JD
AD7521JN
AD7521KD
AD7521KN
AD7521lD
AD7521 IN
AD7521SD
AD7521TD
AD7521UD
AD7530JD
AD7530JN
AD7530KD
AD7530KN
AD7530LD
AD7530lN
AD7531JD
AD7531JN
AD7531KD
AD7531 KN
AD7531lD

AD7531lN (DAC1220lCN)
AD7533AD (DAC1022lCDI
AD7533BD (DAClO21lCD)
AD7533CD (DAC1020lCDI
AD7533JN (DAC1022lCN)
AD7533KN (DAC1021lCN)
AD7533lN (DAC1020lCN)
AD7533SD (DAC1022lD)
AD7533TO (DAC1021lC)
AD7533UD (DAC1020lD)
AH0139CD
AH0139D
AH0139D/883
AH0142CD
AH0142D
AH0142D/883
AH0143CD
AH0143D
AH0143DI883
AH0144CD
AH0144D
AH0144D/883
AD0145CD
AH0145D
AH0145D/883
AH0146CD
AH0146D
AH0146D/883
AH0161CD
AH0161D
AH0161D/83
AH0162CD
AH0162D
AH0162D/883B
AH0163CD
AH0163
AH0163D/883
AH0164CD
AH0164D
AH0164D/883
AH5009CN
AH5010CN
AH5011CN
AH5012CN
AN5013CN
AH5014CN
AH5015CN
AH5016CN
AM9709CN
AM97C09CN
AM9710CN
AM97C10CN
AM9711CN
AM97CllCN
AM9712CN
AM97C12CN
DM7555
DM7556
LF11201D
LFl1201D/883
lF11508D
lF11508D/883
LF11509D
IF 11509D/883
lF13201
lH0042
lH2108
LH2110
LH<111
LH2301
lH2308
LH2310
LH2311
LM100
LM101
LM102
lMl05
lMl07
lMl08
LMll0
lM111
lM300
LM301
LM302
lM305
LM307
lM308
LM310
lM311
LM4250
lM723
LM733
LM740
lM741
lM742
MM52132
MM52164
MM74C946

A-11

AD7531lN
AD7533AD
AD7533BD
AD7533CD
AD7533JN
AD7533KN
AD7533lN
AD7533SD
AD7533TD
AD7533UD
DG139BK
DG139AK
DG 139AK/883B
DG142BK
DG142AK
DG142AK/883B
DG143BK
DG143AK
DG143AK/883B
DG144BK
DG144AK
DG144AK/883B
DG145BK
DG145AK
DG145AK/883B
DG146BK
DG146AK
DG 146AK/8838
DG161BK
DG161AK
DG161AK/883B
DG162BK
DG162AK
DG162AK/883B
DG163BK
DG163AK
DG163AK/883B
DG1648K
DG164AK
DG164AK/883B
IH5009CPD
IH5010CPD
IH5011CPE
IH5012CPE
IH5013CPD
IH5014CPD
IH5015CPE
IH5016CPE
IH5009CPD
IH5009CPD
IH50lOCPD
IH5010CPD
IH5011CPE
IH5011CPE
IH5012CPE
IH5012CPE
ICM7555
ICM7556
DG201AK
DG201 AK/883B
IH6108MJE
IH6108MJE/8838
IH6208MJE
IH6208MJE/8838
DG201
LH0042
lH2108
LH2110
lH2111
lH2301
lH2308
LH23lO
LH2311
LM100
LM101
LM102
lMl05
LM107
lM108
lM1lO
lMll1
lM300
lM301
lM302
lM305
LM307
lM308
LM310
lM311
lM4250
.A723
.A733
.A740
.A741
.A748
IM7332
IM7364
ICM7224

NEe

.PD816C
.PD820C
.PD833G
.PDl963C
.PD2332
.PD2364

Intersll
ICM7038B
ICM1115B
ICM7223
ICM7050
IM7332
IM7364

SM5510

Int.rsil
ICM1115B

OKI

Intersll

NPC

MSM503

AD503

Panasonic/Matsushita

Intersil

MN6091
MN6093

ICM7038B
ICM7051A

PhillipsIF.s.lee

Intersll

MB78
MBlO1
M8103
M8105
M8lO7
MB108
M8143
MB144
MB5lO

ICM7245U
ICM72458
ICM7245E
ICM7245U
ICM7245D
ICM7245E
ICM7245A
ICM7245F
ICMl115B

Plessey

Intersil

SC748

.A748

PMI

Intarsil

PM308
SSS741

lM308
.A741

Raytheon

Intarsil

lH2101
lH2301
lH2311
lMl01
lM105
lMl07
lM108
lM301
lM305
lM307
lM308
lM311
RC723
RC733
RC741
RC748
RM723
RM741
RM748

lH2101
lH2301
lH2311
lM101
lMl05
lM107
lM108
lM301
lM305
lM307
lM308
lM311
.A723
.A733
.A741
.A748
.A723
.A741
.A748

RCA

Intarsil

CA101
CA107
CAllI
CA301
CA307
CA308
::A723
CA741
CA748
CD22015E
CPD6402

LM10l
lMl07
lMll1
lM301
lM307
lM308
lM311
.A723
.A741
.A748
ICM7051A
IM6402

Samsong
KS5240U01E
KS5240B01J
KS5240B01H
KS5240810H
KS5240B12H
KS5240B20H

Inlersil
ICM7245U
ICM7245A
ICM7245B
ICM7245D
ICM7245E
ICM7245F

Sonyo

Inlersll

~A311

LC7523

AD7523

Signelies

'olersil

.A723
.A733
.A740
.A741
.A748
lH2101
lH2108
LH2301
lH2308

.A723
.A733
.A740
.A741
.A748
lH2101
lH2108
lH2301
lH2308

I

Ie Alternate Source Index (continued)

~

continued
pAll7

Inter511
pA7ll

SG10l
SG105
SG107
SG108
SGll0
SGlll
SG301
SG305
SG307
SG308
SG311
SG4250
SG723
SG733
SG741
SG748
5G7S20
5G7521
5G7523

LM10l
LM105
LM107
LM108
LMll0
LMlll
l.M301
LM30S
LM307
LM308
LM311
LM42S0
pA723
pA733
pA741
pA748
AD7520
AD7521
AD7523

Siliconix

'"tersil

DF412
DS123AL
DG123AP
DG123BP
DG12SAL
DG125AP
DG125BP
DG139A·L
DG139AP
DG139BP
OG142AL
DG142AP
DG142BP
DG143AL
DG143AP
DG143BP
DG144AL
OG144AP
DG144AP
DG145AL
DG14SAP
OG14SBP
DG146AL
OG146AP
DG146BP
DG161AL
OG161AP
DG161BP
OG162AL
DG162AP
OG162BP
DG163AL
DG163AP
DG163.BP
DG164AL
OG164AP
DG164BP
DG180AA
DG180AL
OG180AP
DG180BA
DG180BP
DG181AA
OG181AL
DG181AP
DG181BA
OG181BP
DG182AA

ICM7211
DG123AL
DG123AK
DG123BK
OG125AL
DG12SAK
DG125BK
OG139AL
DG139AK
DG139BK
DG142AL
DG142AK
DG142BK
OG143AL
DG143AK
DG143BK
DG144AL
DG144AK
DG144BK
DG145AL
DG145AK
CG14SBK
DG146AL
DG146AK
DG146BK
DG161AL
DG161AK
DG161BK
DG162AL
DG162AK
DG162BK
OG163AL
DG163AK
DG163BK
DG164AL
DG164AK
DG164BK
DG180AA
DG180AL
DG180AK
DG180BA
DG180BK
OG181AA
DG181AL
DG181AK
DG181BA
DG181BK
DG182AA
OGM182AA
DG182AL
DGM182AL
DG182AK
OGM182AK
DG182BA
DGM182BA
DG182BK
DGM182BK
OG183AL
DG183AK
OG183BK'
DG184AL
DG184AK
DG184BK
OG185AL
DGM185AL
DG185AK
DGM185AK
DG185BK
DGMi85BK
DG186AA
DG186AL

Silicon General

DG182AL
DG182AP
OG182BA
DG182BP
D,G183AL
DG183AP
DG183BP
OG184AL
DG184AP
DG184BP
DG185AL
OG185AP
DG185BP
DG186AA
DG186Al

DG186AK
DG186BA
DG186BK
DG187AA
DG187AL
DG187AK
DG187BA
DG187BK
DG188AA
DGMl88AA
DG188AL
DG188AK
DG188BA
DGM188BA
DG188BK
DG189AL
DG189AK
DG189BK
DG190AL
DG190AK
DG190BK
DG191AL
DGM191AL
DG191AK
DGM191AK
DG191BK
DGM191BK
DG200AA
DG200AL
DG200AK
DG200BA
DG200BK
DG200CJ
DG201AK
DG201BK
DG201CJ
DGM182AA
DGM182AK
DGM182AK
DGM181BA
DGM181BK
DGM181BK
DGM181CJ
DGM185AK
DGM18SAK
DGM184BK
DGM184BK
OGM184CJ
DGM188AA
DGM188AK
DGM188AK
OGM187BA
OGM187BK
OGM187BK
OGM191AK
OGM191AK
DGM190BK
DGM190BK
DGM190CJ
AD503
IH6116MJI
IH6116CJI
IH6116CPI
IH6216MJI
IH6216CJI
IH6216CPI
IH6108MJE
IH6108CJE
IH6108CPE
IH6208MJE
IH6208CJE
IH6208CPE
D123AL,
0123AK
D123BK
D12SBJ
0125AL
D125AK
D12SBK
D125BJ
D129AL
0129AK
D129BK

DG186AP
DG186BA
DG186BP
DG187AA
DG187AL
DG187AP
DG187BA
DG187BP
DG188AA
DG188AL
DG188AP
DG188BA
DG188BP
DG189AL
DG189AP
DG189BP
DG190AL
DG190AP
DG190BP
DG191AL
DG191AP
DG191BP
DG200AA
DG200AL
DG200AP
DG200BA
DG200BP
DG200CJ
DG201AP
OG201BP
DG201CJ
DG381AA
DG381AK
DG381AP
DG381 BA
DG381BK
DG381 BP
DG381CJ
DG384AK
DG384AP
OG384BK
OG384BP
OG384CJ
OG387AA
OG387AK
OG387AP
DG387BA
OG387BK
DG387BP
OG390AK
DG390AP
DG390BK
DG390BP
DG390CJ
OG503
DG506AR
DGS06BR
DGS06CJ
DG507AR
OG507BR
DG507CJ
DG508AP
DGS08BP
DGS08CJ
DG509AP
DG509BP
DG509CJ
D123AL
D123AP
D123BP
D12SAL
D125AP
D125BP
D129AL
D129AP
D129BP

Sprague

Intersi!

UCN·4112M
UCN-4113M
UHP-503

ICM7051A
ICM7038B
A0503

Synerlek

Intersil
IM7332
IM7364

SY2332
5Y2364

A-12

TI

Intersil

"A723
/.A733
pA741
pA748

}.A723
pA733
I,A741
pA748

,All7

pAll7

LM10l
LM10S
LM107
LMlll
LM301
LM305
LM307
LM311
SN74S188
TL 182CL
TL 182CN
TL 1821L
TL 1821N
TL 182ML
TL185CJ
TL 185CN
TL 1851J
TL 18SIN
Tl:18SMJ
TL 188CL
TL 188CN
TL 1881L
TL1881N
TL 188ML
TL 191CJ
TL 191CN
TL 1911J
TL1911N
TL191MJ
TL503

LM10l
LM10S
LM107
LMlll
LM301
LM305
LM307
LM311
DGM182BA
DGM182BA
DGM182CJ
DGM182BA
DGM182CJ
DGM182AA
IHS045CJE
IHS04SCPE
IHS04SCJE
IHS04SCPE
IHS04SMJE
IHS042CTW
IHS042CF?E
IHS042CTW
IH5042CPE
IHS042MTW
IHS043CJE
IH5043CPE
IHS043CJE
IHS043CPE
IH5043MJE
AD503

Toshiba

Intersil

TC8031 P
TC80S1P
TC8056PA
TC8057P
TMM2114
TMM2332
TMM2364

ICM7038A
ICM7038B
ICM111SB
ICM7038D
2114
IM7332
IM7364

DISCRETE CROSS REFERENCE

ALTERNATE
SOURCE PRODUCT

INTERSIL
EOUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EOUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

1008
100U
102M
1028
103M

2N5458
2N3684
2N5686
2N5457
2N5457

2N2606
2N2607
2N2608
2N2609
2N2609JAN

2N2607
2N2607
2N2608
2N2609
2N2609JAN

2N3331
2N3332
2N3333
2N3334
2N3335

2N5270
2N5268
1T132
IT132

1038
104M
105M
105U
106M

2N5459
2N5458
2N5459
2N4340
2N5485

2N2639
2N2640
2N2641
2N2642
2N2643

1T120

2N3336

IT132

IT122

2N3347

IT122
1T120

2N3348
2N3349
2N3350

IT137
IT138
IT139
1T137

107M
110U
120U
125U
1277A

2N5485
2N3685
2N3686
2N4339
2N3822

2N2644
2N2652
2N2652A
2N2720
2N2721

IT122
IT120

IT120
IT120
IT122

2N3351
2N3352
2N3365
2N3366
2N3367

1T138
1T139
2N4340
2N4338
2N4338

2N3823
2N3824
2N3907
2N3909

2N3823
2N3824
IT120
1T12D
2N2609

1278A
1279A
1280A
1281A
1282A

2N3821
2N3821
2N4224
2N3822
2N4341

2N2722
2N2802
2N2803
2N2804
2N2805

IT120
1T139
IT139
1T139
IT139

2N3368
2N3369
2N3370
2N3376
2N3378

2N4341
2N4339

2N3909A

2N2609

2N3921

2N3921

2N4338
2N2608
2N2608

2N3922
2N3949
2N3950

2N3922

1283A
1284A
1285A
1286A
130U

2N4340
2N4222
2N3821
2N4220
2N3687

2N2806
2N2807
2N2841
2N2842
2N2843

1T139
IT139
2N2607
2N2607
2N2607

2N3380
2N3382
2N3384
2N3386
2N3409

2N2609
2N3994
2N3993
2N5114
IT122

2N3954
2N3954A
2N3955
2N3955A
2N3956

2N3954
2N3954A
2N3955
2N3955A
2N3956

1325A
135U
14T
155U
1714A

2N4222
2N4339
2N4224
2N4416
2N4340

2N2844
2N2903
2N2903A
2N2910
2N2913

2N2607

2N3410

2N3411
2N3423
2N3424
2N3425

1T122
1T122
1T122
IT122
1T122

2N3957
2N3966
2N3967
2N3967A
2N3968

2N3957

1T122
IT120
IT122
IT122

1828
1838
1978
1988
1998

2N4391
2N3823
2N4338
2N4340
2N4341

2N2814
2N2915
2N2915A
2N2916
2N2916A

1T120
IT120
IT120

2N3436
2N3437
2N3438
2N3452
2N3453

2N4341
2N4340
2N4338
2N4220
2N4338

2N3968A
2N3969
2N3969A
2N3970
2N3971

2N3685
2N3686
2N3686
2N3970
2N3971

2000M
2001M
2008
200U
2018

2N3823
2N3823
2N4392
2N3824
2N4391

2N2917
2N2918
2N2919
2N2919A
2N2920

IT122

2N3454

2N4338

2N3972

IT122
1T120
1T120
2N2920

2N3455
2N3456
2N3457
2N3458

2N4340
2N4338
2N4338
2N4341

2N3993
2N3993A
2N3994
2N3994A

2N3972
2N3993
2N3993
2N3994
2N3994

2028
2038
2048
2078A
2079A

2N4392
2N3821
2N3821
2N3955
2N3955

2N2920A
2N2936
2N2937
2N2972
2N2973

2N2920
IT120
1T120
IT122
IT122

2N3459
2N3460
2N3513
2N3514
2N3515

2N4339
2N4338
IT122
IT122
1T122

2N4009
2N4010
2N4011
2N4015
2N4016

IT132
IT132
IT132
IT139
IT137

2080A
2081A
2093M
2094M
2095M

2N3955A
2N3955A
2N3687
2N3686
2N3686

2N2974
2N2975
2N2976
2N2977
2N29?8

IT120
IT120
1T120
IT120
IT120

2N3516
2N3517
2N3521
2N3522
2N3574

IT122
IT122
1T122
IT122
2N2607

2N4017
2N4018
2N4019

2N4020
2N4021

1T139
IT139
IT139
IT139

2098A
2099A
210U
2130U
2132U

2N3954
2N3955A
2N4416
2N5452
2N3955

2N2979
2N2980
2N2981
2N2982
2N3043

IT120
IT121
IT122
IT122
IT121

2N3575
2N3578
2N3587
2N3608
2N3680

2N2607
2N26Q8
1T122
3N1?2
IT120

2N4022
2N4023
2N4024
2N4025
2N4026

IT139
IT137
IT137
1T13?
3N163

2134U
2136U
2138U
2139U
2147U

2N3956
2N3957
2N3958
2N3958
2N3958

2N3044
2N3045
2N3046
2N3047
2N3048

1T122
JT122
1T121
IT122
IT122

2N3684
2N3684A
2N3685
2N3685A
2N3686

2N3684
2N3684
2N3685
2N3685
2N3686

2N4038
2N4039
2N4065
2N4066
2N4067

2N4351
2N4351
3N163
3N166
3N166

2148U
2149U
2318
2328
2338

2N3958
2N3958
2N3954
2N3955
2N3956

2N3049
2N3050
2N3051
2N3052
2N3059

IT139
IT139
IT139
1T129
IT139

2N3686A
2N3687
2N3687A
2N3726
2N3727

2N3686
2N3687
2N3687
IT131
1T130

2N4082
2N4083
2N4084
2N4085
2N4091

2N3954
2N3955
2N3954
2N3955
2N4091

2348
2358
241U
250U
251U

2N3957
2N3958
2N4869
2N4091
2N4392

2N3066
2N3067
2N3068
2N3069
2N3070

2N4340
2N4338
2N4338
2N4341
2N4339

2N3728
2N3729
2N3800
2N3801
2N3802

IT122
IT121
IT132
1T132
IT132

2N4091A
2N4091JAN
2N4091JANTX
2N4091 JANTXV
2N4092

2N4091
2N4091JAN
2N4091JANTX
2N4091JANTXV
2N4092

2N2060
2N2060A
2N20608
2N2223
2N2223A

1T120
11121
1T121
1T122
11121

2N3071
2N3084
2N3085
2N3086
2N3087

2N4338
2N4339
2N4339
2N4339
2N4339

2N3803
2N3804
2N3804A
2N3805
2N3805A

1T132
IT130
1T130A
IT130
IT130A

2N4092A
2N4092JAN
2N4092JANTX
2N4D92JANTXV
2N4093

2N4092
2N4092JAN
2N4092JANTX
2N4092JANTXV
2N4093

2N2386
2N2386A
2N2453
2N2453A
2N2480

2N2608
2N2608
IT122
1T121
IT122

2N3088
2N3088A
2N3089
2N3089A
2N3113

2N4339
2N4339
2N4339
2N4339
2N2607

2N3806
2N3807
2N3808
2N3809
2N3810

IT122
IT122
IT122
1T122
2N3810

2N4093A
2N4093JAN
2N4093JANTX
2N4093JANTXV
2N4100

2N4093
2N4093JAN
2N4093JANTX
2N4093JANTXV
2N4100

2N2480A
2N2497
2N2498
2N2499
2N2500

1T121
2N2608
2N2608
2N2609
2N2608

2N3277
2N3278
2N3328
2N3329
2N3330

2N2606
2N2607
2N5265
2N5267
2N5268

2N3810A
2N3B11
2N3811A
2N3812
2N3813

2N3810A
2N3811
2N3811A
IT132
IT132

2N4117
2N4117A
2N4118
2N4118A
2N4119

2N4117
2N4117A
2N4118
2N4118A
2N4119

IT122

1T120
1T120

1T132

2N3814
2N3815
2N3816
2N3816A
2N3817

IT132
1T132
IT130
1T130A
IT130

2N3817A
2N3819

IT130A
2N54B4
2N260B

2N3820
2N3821
2N3822

2N390B

2N3821
2N3822

IT132 '
IT132

2N4416
2N4221
2N4221

2N3685

1T139

/

"'CONSULT FACTORY

A-13

DISCRETE CROSS REF~RENCE (cont.)

ALTERNATE
SOURCE PROOUCT

INTERSIL
EOUIVALENT

2N4119A
2N4120
2N4139
2N4220
2N4220A

2N4119A
3N163
2N3822
2N4220
2N4220

2N4221
2N4221A
2N4222
2N4222A
2N4223

ALTERNATE
SOURCE PRODUCT

INTERSIL
EOUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EOUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EOUIVALENT

2N5045
2N5046
2N5047
2N5078
2N5090

2N5453
2N5454
2N5454
2N5397
IT122

2N5484
2N5485
2N5486
2N5515
2N5516

2N5484
2N5485
2N5486
2N5515
2N5516

2N6484
2N6485
2N6502
2N6503
2N6550

2N6484
2N6485
1T122
1T122
2N4868A

2N4221
2N4221
2N4222
2N4222
2N4223

2N5103
2N5104
2N5105
2N5114
2NS114JAN

2N4416
2N4416
2N4416
2N5114
2N5114JAN

2N5517
2N5518
2N5519
2N5520
2N5521

2N5517
2N5518
2N5519
2N5520
2N5521

2N6568
28C294
28J11
28J12
28J13

2N5432
1T122
2N2607
2N2607
2N5270

2N4224
2N4267
2N4268
2N4302
2N4303

2N4224
3N163
3N161
2N4302
2N5459

2N5114JANTX,
2N5114JANTXV
2N5115
2N5115JAN
2N5115JANTX

2N5114JANTX
2N5114JANTXV
2N5115
2N5115JAN

2N5522
2N5523
2N5524
2N5545
2N5546

2N5522
2N5523
2N5524
2N3954
2N3955A

28J15

2N2607
2N2607

2N4304
2N4338
2N4339
2N4340
2N4341

2N5458
2N4338
2N4339
2N4340
2N4341

2N5115JANTXV
2N5116
2N5116JAN
2N5116JANTX

2N5116JANTX
2N5116JANTXV

2N5547
2N5549
2N5555
2N5556
2N5557

2N3955
2N4093
J310
2N3685
2N3684

28J50
28J78
28J79
28J80
28K11

2N4342
2N4343
2N4351
2N4352
2N4353

2N5461

2N5117

2N5462

2N5118

2N4351
3N163
3N172

2N5119
2N5120
2N5121

2N5117
2N5118
2N5119
1T131
1T132

2N5558
2N5561
2N5562
2N5563
2N5564

2N3684
U401
U402
U404
1T550

2SK12
28K13
2SK132
28K133
28K134

2N43S0
2N4381
2N4382
2N4391
2N4392

2N5460
2N2609
2N5115
2N4391
2N4392

2N5122
2N5123
2N5124
2N5125
2N5158

1T132
11131
IT132
IT132
2N5434

2N5565
2N5566
2N5592
2N5593
2N5594

IT550
IT550
2N3822
2N3822
2N3822

28K135
28K15
28K17
28K178
28K179

2N4393
2N4416
2N-4416A
2N4417
2N4445

2N4393
2N4416
2N4416A
2N4416
2N5432

2N5159
2N5163
2N5196
2N5197
2N5198

2N5433
2N3822
2N5196
2N5197
2N5198

2N5638
2N5639
2N5640
2N5647
2N5648

2N5638
2N5639
2N5640
2N4117A
2N4117A

2SK18
28K180
28K19
28K23
28K30

ITE4416
2N5459
2N5458

2N4446
2N4447
2N4448
2N4856
2N4856A

2N5434
2N5432
2N5434
2N4856
2N4856

2N5199
2N5245
2N5246
2N5247
2N5248

2N5199
ITE4416
2N5484
2N5486
2N5486

2N5649
2N5653
2N5654
2N5668
2N5669

2N4117A
2N5638
2N5639
2N5484
2N5485

28K32
28K33
2SK34
28K37
28K41

2N3822
2N5397
2N3822
2N5484
2N5459

2N4856JAN
2N4B56JANTX
2N4856JANTXV
2N4857
2N4857A

2N4856JAN
2N4856JANTX
2N4856JANTXV
2N4857
2N4857

2N5254
2N5255
2N5256
2N5257
2N5258

1T132
IT132
IT130
2N5457
2N5458

2N5670
2N5793
2N5794
2N5795
2N5796

2N5486
1T129
1T129
IT139
1T139

2SK42
28K43
28K44
28K46
28K48

2N3822
ITE4092
ITE4416
2N5459
2N3821

2N4857JAN
2N4857JANTX
2N4857JANTXV
2N4858
'2N4858A

2N4857JAN
2N4857JANTX
2N4857JANTXV
2N4858
2N4858

2N5259
2N5265
2N5266
2N5267
2N5268

2N5459
2N2607
2N2607
2N2608
2N2608

2N5797
2N5798
2N5799
2N5800
2N5801

2N2608
2N2608
2N2608
2N2608
2N4393

28K49
28K50
28K54
28K55
28K56

2N5484
ITE4416
2N3822
2N3822
2N5459

2N4858JAN
2N4858JANTX
2N4858JANTXV
2N4859
2N4859A

2N4858JAN
2N4858JANTX
2N4858JANTXV
2N4859
2N4859

2N5269
2N5270
2N5277
2N5278
2N5358

2N2609
2N2609
2N4341
2N4341
2N4220

2N5802
2N5803
2N5843
2N5844
2N5902

2N4393
2N4392
IT130
IT130
2N5902

28K61
28K65
28K66
28K68
28K72

2N5397
J201
2N3821
2N3822
2N5196

2N4859JAN
2N4859JANTX
2N4860
2N4860A
2N4860JAN

2N4856JAN
2N4856JANTX
2N4860
2N4860
2N4857JAN

2N5359 '
2N5360
2N5361
2N5362
2N5363

2N4220
2N4221
2N4221
2N4222
2N4222

2N5903
2N5904
2N5905
2N5906
2N5907

2N5903
2N5904
2N5905
2N5906
2N5907

3G8
3N145
3N146
3N147
3N148

2N3821
3N163
3N163
3N189
3N189

2N4860JANTX
2N4861
2N4861A
2N4861 JAN
2N4861 JANTX

2N485 7 JANTX
2N4861
2N4861
2N4858JAN
2N4858JANTX

2N5364
2N5391
2N5392
2N5393
2N5394

2N4222
2N4867A
2N4868A
2N4869A
2N4869A

2N5908
2N5909
2N5911
2N5912
2N5949

2N5908
2N5909
2N5911
2N5912
2N5486

3N149
3N150
3N151
3N155
3N155A

3N161
3N163
3N190
3N163
3N163

2N4867
2N4867A
2N4868
2N4868A
2N4869

2N4867
2N4867A
2N4868
2N4868A
2N4869

2N5395
2N5396
2N5397
2N5398
2N5432

2N4869A
2N4869A
2N5397
2N5398
2N5432

2N5950
2N5951
2N5952
2N5953
2N6085

2N5486
2N5486
2N5484
2N5484
1T122

3N156
3N156A
3N157
3N157A
3N158

3N163
3N163
3N163
3N163
3N163

2N4869A
2N4878
2N4879
2N4880
2N4937

2N4869A
2N4878
2N4879
2N4880
IT131

2N5433
2N5434
2N5452
2N5453
2N5454

2N5452
2N5453
2N5454

~~§~~~

2N6086
2N6087
2N6088
2N6089
2N6090'

IT122
lT121
1T121
1T122
lT121

3N158A
3N160
3N161
3N163
3N164

3N163
3N161
3N161
3N163
3N164

2N4938
2.:
TL lBBIL
TL 1881N
TL 188ML
TL 191CJ

IH5042CTW
IH5042CPE
IH5042MTW
IH5043CJE

HI1-5046-5

OG509CJ

IHS208CPE

iH5143CJE

G1168P

G116BK

Gl17AL
GllBAL
Gl18AP
Gl19AL

Gl17AL
G118AL
G118AK
Gl19AL

G123AL
G123AP
HI0-0201-S
HI0-0381-S
HI0-0384-S

G123AL
G123AK
OG201CI0
OGM1B1CIO
OGM184CIO

HI1-5047-2
HI1-5047-5
HI1-5047-B

IH504SCJE
IH504SMJEI883B
IH5047MJE
IH5047CJE '
IH5047MJE/8838

HIO-0387-6

HI0-039O-S
HI0-050S-S
HIO-050SA-S
HI0-0507-S

DGM187C/D
OGM19OCIO
IH6116C/D
IH511SCIO
IHS21SCIO

HI1-5049-2
HI1-5049-5
HI1-5049-8
HI1-5050-2
HI1-5050-5

IH5149MJE
IH5149CJE
IH5149MJE/8838
IH5150MJE
IH5150CJE

HI0-0507A-S
HI0-0508-S
HI0-0508A-S
HI0-0509-S
HI0-0509A-6

IH5216CID
IHS108CIO
IH5108CIO
IHS208CIO
IH5208CIO

HI1-5050-8
HI1-5051-2
HI1-5051-5
HI1-5051-8
HI2-0200-2

IH51 50MJEI8838
IH6151MJE
IH5151CJE
IH5151 MJEI883B
oG20oAA

HIO-5040-6
HI0-5041-S
HIo-5042-S
HI0-5043-S
HI0-5044-S

IH5140C/O
IHS141CID

IH5142CIO
IH5143CIO
IH5144CIO

HI2-0200-4
HI2-o2oo-5
HI2-D2oo-8
HI2-03Bl-2
HI2-0381-5

OG200BA
OG2008A
OG200AAIBB3B
OGM1B2AA
DGM181BA

H,10-5045-6
HIo-5046'S
HI0-5047-S
HI0-5049-S
HI0-505O-S

IH5145CIO
IH504SCI0
IH5047CIO
IH5149CIO
IH515OCIO

HI2-o381-8
HI2-o387-2
HI2-o387-5
HI2-o387-8
HI3-o2oo-5

OGM181 AAI8838
OGM188AA
OGM1878A
oGM188AAI8838
OG2ooCJ

HI0-5051-S
HI 1-0200-2
HI 1-0200-4
Hll-02oo-5
Iill-0200-S

IH50S1CJD
OG200AK
OG2ooBK
oG200BK
OG200CIO

HI3-o201-5
HI3-o381-5
HI3-o384-5
H13-039O-5
HI3-05OS-5

OGM184CJ
OGM190CJ
IHSllSCPI

Hll-0200-8
Hll-0201-2
Hll-0201-4
Hll-0201-5
Hll-0201-8

OG200AKIBB3B
OG201AK
OG201BK
OG201BK
OG201AKI883B

HI3-050SA-5
HI3-o507-5
HI3-0507A-5
HI3-050B-5
HI3-050BA-5

IHS108CPE
IH5108CPE

Hll-0381-2
Hll-0381-5
Hll-0381-8
Hll-0384-2
Hll-0384-5

OGM182AK
OGM1B1BK
OGM 182AKI883B
OGM185AK
OGM184BK

HI3-o509-5
HI3-0509A-5
LFl12010
LFl12olO1883
LFl12020,

IH6208CPE
IH5208CPE
OG201AK
OG201AKI8838
IH202MJE

Hll-03B4-B
HI 1-0387-2
HI 1-0387-5
Hll-0387-8
Hll-0390-2

OGM185AKI883B
OGM188AK
OGM187BK
OGM188AKI8838
OGM191AK

LF 1120201883
LFl15080
LFl150901883

IH202MJEI883B
IHSlo8MJE
IH6108MJEI883B
IHS208MJE
IHS208MJEI883B

Hll-0390-5
Hll-0390-8
Hll-050S-2
Hll-05OS-5
Hll-050S-8

OGM1908K
OGM191AKIB83B
IH6116MJI
IHSllSCJI
IH6116MJ1I8838

LF132010
LF13201N
LF132020
LF1350BO
LF13508N

OG201BK
OG201CJ
IH202CJE
IHS108CJE
IHS108CPE

Hll-0506A-2
Hll-0506A-5
Hll-0506A-8
HI1-0507-2
HI1-0507-5 '"

IH5116MJI
IH51161J1
IH511SMJI1883B
IHS21SMJI
IHS21SCJI

LF135090
LF13509N
MM450H
MM451H
MM4520

IHS208CJE
IHS208CPE
MM450H
MM451H
MM452J

Ht1-0507-8
Hll-0507A-2
Hll-0507A-5
Hll'0507A-8
Hll-0508-2

IHS21SMJlI8B3B
IH5216MJI
IH5216IJt
IH521SMJI18838
IHS108MJE

MM452F
MM455H
MM550H
MM551H
MM5520

MM452F
MM455H
MM550H
MM551H
MM552J

Hll-0508-5
,"1-0508-8
Hll-0508A-2
Hll-0508A-5
HI1-050BA-8

IHS108CJE
IH6108MJEI8B3B
IH5rD8MJE
IH51081JE
IH510BMJE/BB38

MM552F
MM555H
SJM181BCC
SJM181BIC
SJM182BCC

MM552F
MM555H
JM38510111101BCC
JM3B51 01111 01 BIC
JM3B510111102BCC

Hll-0509-2
Hll-0509·5
HI1-0509-8
Hll-0509A-2
Hll-0509A-5

IH6208MJE
IH6208CJE
IH6208MJEI8838
IH52081JE

SJM182BIC
SJM184BEC
SJM185BEC
SJM1B78CC
SJM187BIC

JM3851011 110281C
JM3B51 01111 038EC
JM385101111048EC
JM3851OIll105BCC
JM3851 01111 05BIC

Hll-0509A-B
HI1-5040-2
HI1-5040-5
HI1-5040-B
HI1'-5041·2

IH5208MJEI883B
IH5040MJE
IH5040CJE
IH5040MJEI883B
IH5041MJE

SJM188BCC
SJM188BIC
SJM190BEC
SJM191BEC
TL182CL

JM3851011110SBCC
JM38510111106BIC
JM38510111107BEC
JM38510111108BEC
OGM1828A

1~5208MJE

HI1~5046-8

t~mg~gI883,

IH5145CJE
IH5145MJE!8B3B

IH504SMJE

TL 191CN
TL1911J
TL 1911N
TL191MJ

ALTERNATE
SOURCE PRODUCT

INTERSiL
EQUIVALENT
;'

IH5Q42CPE

IH5043CPE
IH5043CJE
IH5043CPE
IH5043MJE

'

,,'

'/

oG201CJ
OGM181CJ

IH5116CPI
IH6216CPI
IH5216CPI

A-22

\

,

.
"*CONSULTFACTORY

DATA ACQUISITION CROSS REFERENCE

ALTERNATE
SOURCE PRODUCT

INTERSIL
EOUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

A07520JO
A07520JN
A07520KO
A07520KN,
A07520LO

A07520JO
AD752!)JN
A07520KO
A07520KN
A07520LO

MP7521LN
MP7521S0
MP7521TD
MP7521UO
MP7523JN

A07521LN
A07521S0
A07521TD
A07521UO
A07523JN

A07520LN
A07520SD
A07520TD
AD7520UD
A07521JO

A07520LN
A07520S0
A07520TD
AD7520UD
A07521JO

MP7523KN
MP7523LN
MP7621AO
MP7621BD
MP7621JN

A07523KN
A07523LN
A07541AO
A075418D
A07541JN

A07521JN
A07521KO
A07521KN
A07521 LO
A07521LN

A07521JN
A07521KD
A07521KN
A07521LO
A07521LN

MP7621KN
MP7621SO
MP7621TD

A07541KN
A07541 SO
A07541TO

A07521S0
A07521TO
A07521UO
A07523AO
A07523BO

A07521SO
AD7521TO
A07521UO
A07523AO
A07523BO

A07523CO
A07523JN
A07523KN
A07523LN
A07523S0

A07523CO
A07523JN
A07523KN
A07523LN
A07523S0

A07523TD
A07523UO
AD7530JO
A07530JN
A07530KO

A07523TD
A07523UO
A07530JD
A07530JN
A07530KO

A07530KN
A07530LO
A07530LN
A07531 JO
A07531JN

A07530KN
A07530LO
A07530LN
A07531JO
A07531JN

A07531KO
A07531KN
A07531LD
A07531LN
A07533AO

A07531KO
A07531KN
A07531 LD
A07531LN
A07533AO

A07533BO
A07533CO
A07533JN
A07533KN
A07533LN

A07533BO
A07533CO
A07533JN
A075B3KN
A07533LN

A07533S0
A07533TD
A07533UO
A07541AO
A07541BO

A07533S0
A07533TD
A07533UO
A07541AO
A07541BO

A07541JN
A07541KN
A07541S0
A07541TO
OAC1020LCO

A07541JN
A07541KN
A07541SO
A07541TD
A07520LO

OAC1020LO
OAC1021LO
OAC1022LCO
OAC1022LO

A07520UO
AD7520KD
A07520TD
A07520JO
A07520S0

OAC121BLCO
OAC121BLCN
OAC121BLCN
OAC1219LCO
OAC1219LCN

A07541BO
A07541KN
A07541LN
A07541AO
A07541JN

OAC1220LCO
DAC1220LO
OAC1221LCO
OAC1221LO
OAC1222LCO

A07521LO
AD7521UD
A07521KO
A07521TO
AD7521JO

OAC1222LO
MP7520JO
MP7520JN
MP7520KO
MP7520KN

A07521S0
A07520JO
A07520JN
A07520KO
A07520KN

MP7520LO
MP752QLN
MP7520S0
MP7520TD
MP7520UO

A07520~O

MP7521JO
MP7521JN
MP7521KO
MP7521KN
MP7521LO

A07521JD
A07521JN
A07521KO
A07521KN
A07521LO

OAC1021 LCD

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

I

A07520LN
A07520S0
A07520TD
A07520UO

'''CONSULT FACTORY

A-23

I

WATCH & CLOCK CROSS REFERENCE

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

C022001H
C022015E
E1115
E1151
E1426

ICM1424C
ICM7051A
ICM1115A
ICM11158
ICM7050U

H043871
H043871
KS5183
KS5240801 H

ICM7050G
ICM7050H
ICM7269
ICM72458

KS5240B01J

ICM7245A

KS5240810H
KS524D812H
KS524082DH
KS5240U01 E
M5001

ICM7245D
ICM7245E
ICM7245F
ICM7245U
ICM7269

M58434P
M58435P
M58436·D01 P
M58437·001 P
M8l01

ICM7038D
ICM11158
ICM7050G
ICM707DL
ICM72458

M8103
M8105
M81D7
M8108
M8143

ICM7245E
ICM7245U
ICM72450
ICM7245E
ICM7245A

Ma144
M8510
M8511

ICM7245F
ICM11158
ICM7050H

MB512

ICM7050H

M8513

ICM7D5DG

M8521
M8522
M8531
M8533
M8541

ITS9068
ITS9D68
ICM7050H
ICM7050H
ICM7052

M8542
M878
MCC14440

ICM7052
ICM7245U
ICM1424C

MCC14483

ICM7210

MJ41

ICM1424C

MJ6
MN6081
MN6082A
MN6083
MN6252

ICM722D
ICM70388
ICM7D38E
ICM7051A
ICM705DG

MSM5001
MSM5011
MSt.;15877

ICM726S
ICM1424C
ICM1424C

81424

ICM1424C

SCL5478
SM5D11
SM5510
SM55308
TC8031P

ICM7268
ICM705DG
ICM11158
ICM7070P
ICM7038A

TCB032P
TCBD51P
TCB052P
TCB056PA
TCB057P

ICM7038F
ICM70388

UCN-4111M

UP01863C
UP0815C
UP0816C

UP0820C
UP0833G

INTERSIL
EQUIVALENT·

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUlVALENT

ALTERNATE
SOURCE PRODUCT

INTEIISIL
EQUIVALENT

,

!CM1424C

SCL54301

UCN·4112M
UCN·4113M
UP01852P
UP01862C

ALTERNATE
SQURtE PRODUCT

ICM7038E

ICM11158
ICM70380
ICM7038C
ICM7051A
ICM70388
ICM7220MFA
ICM7050G
ICM7050
ICM7038E
ICM70388
ICM11158
ICM7223

~

·'·CONSULT FACTORY

A-24

LINEAR CROSS REFERENCE

ALTERNATE
SOURCE PRODUCT

INTERSIL
EQUIVALENT

ALTERNATE
SOURCE PRODUCT

INTERSIL

ALTERNATE

INTERSIL

EQUIVALENT

SOURCE PRODUCT

EQUIVALENT

INTERSIL

EQUIVALENT

UA741

723
733
741
74B
A010l

UA723
UA733
UA741
UA74B
LM10l

MC1741
MC174B
MHWS90
MPSS01D
NES90

UA74B
ADS9D
ICLBD69
ADS90

AD10B
AD301
AD30B
ADS03
ADS32

LM10B
LM301
LM30B
ADS03
AOS32

NES92
DP-OS
DP-07
OP-OB
PM30B

NES92
OP-OS
OP-07
OP·QB
LM30B

ADS34
ADS90
AD741
AM2S02
AM2S03

ADS34
AOS90
UA741
AM2S02
AM2S03

RC723
RC733

UA723
UA733

AM2504

~~~!g~

AM2S04
HA2505
HA2525

CA1Q1

LM101

CA107

RC741

UA741

RC74B
RM723

UA74B
UA723
UA741
UA74B
UA74B

LM107

RM741
RM74B
SC74B
SG101
SG10S

CAlll
CA301
CA307
CA30B
CA311

LMlll
LM301
LM3D7
LM3DB
LM311

SG107
SGlOB
SGll0
SGlll
SG2S02

LM107
LMlOB
LMll0

CA723
CA741
CA74B
DG503
DM2S02

UA723
UA741
UA74B
ADS03
AM2S02

SG2S03
SG301
SG30S

AM2S03
LM301
LM30S

SG307

LM307

SG30B

LM30B

DM2S03
DM2S04
HA2S00
HA2S02
HA250S

AM2S03
AM2S04
HA2S00
HA2S02
HA2S0S

SG311
SG42S0
SG723
SG733
SG741

LM311
LM42S0
UA723
UA733

HA2507
HA2510

HA2S07
HA2S10

UA74B
UA741
SUS36
AOS03
NE592

LM101

LMlOS

LM111

AM2S02

UA741

HA2512

HA2512

HA2S1S
HA2S17

HA2S1S
HA2517

SG74B
SSS741
SUS36
TLS03
TL592

HA2520
HA2522
HA2525
HA2527
HA2600

HA2S20
HA2S22
HA2525
HA2S27
HA2600

TT-S90
UA10l
UA102
UA10S
UA107

AD590
LM10l
LM102
LM105
LM107

HA2602
HA260S

HA2602
HA2605

LM10B
LMll0

HA2607

HA2607

HA2620
HA2622

HA2620
HA2622

UAlOB
UAll0
UA111
UA301
UA302

HA2625
HA2627
HA2720
LH0042
LH2101

HA2625
HA2627
ICLB021
LH0042
LH2101

UA305
UA307
UA30B
UA310
UA311

LM305
LM307
LM30B
LM310
LM311

LH21 DB
LH2110

LH210B
LH2110

UA723
UA733

UA723
UA733

LH2111

LH2111

LH2301
LH230B

LH2301
LH230B

UA740
UA741

UA74B

UA741
UA74B

LH2310
LH2311
LM100
LM10l
LM102

LH2310
LH2311
LM100
LM1Dl
LM102

UA777
UHP-503
VR-B069
WG-B03B
XRB03B

UA777
ADS03
ICLB069
ICLB03B
ICLB03B

LM10S
lM107
LM10B
LMll0
LMlll,

LM105
LM107
LM10B
LMll0
LMlll

LM300
LM301
LM302
LM305
LM307

LM300
LM301
LM302
LM3DS
LM307

LM30B

ALTERNATE
SOURCE PRODUCT

,

LM111

LM301
LM302

UA740

LM30B

LM310

LM310

LM311
LM4250
LM723

LM311
LM42S0
UA723

LM733
LM740
LM741
LM74B
MC1723

UA733
UA740
UA741
,UA74B
UA723 '

nCONSULT FACTORY

A·25

N·Channel
2N3970·72
2N4091·93
2N4391·93
2N4856·61
2N5432·34
2N5638·40
ITE4091·3
ITE4391·3
J105·7
J111·13
U200·2
U1897·99
P·Channel
2N3993/4
2N5018/19
2N5114·16
IT100/1
J174·77

Page
1·18
1·22
1·30
1·32
1·42
1·49
1·22
1·30
1·77
1·78
1·85
1·92
1·19
1·36
1·37
1·64
1·79

JFET Single
Amplifiers
N·Channel
2N3684·87
2N3821/22
2N3823
2N3824
2N4117·19
2N4220·22
2N4223/24
2N4338·41
2N4416
2N4867·69
2N5397/98

1·10
1·13
1·14
1·15
1·25
1·26
1·27
1·28
1·31
1·33
1·41

2N5457·59.
2N5484·86
ITE4416
J201·4
J308·10
U308·10
P·Channel
2N2607·9
2N5460·65
U304·6

JFET Dual
Amplifiers
N·Channel
2N3921/22
2N3954·58
2N5196·99
2N5452·54
2N5515·24
2N5902·9
2N5911/12
2N6483·85
IMF6485
IT500·5
A050 (IT 500)
IT550
IT5911/12
U231·35
U257
U401·6

1·44 3N170/1
1·46 IT1750
1·31 M116
1·80 P·Channel
1·82 3N161
1·89 3N163/64
3N172/73
1·9 IT1700
1·45 Dual P:Channel
1·88 3N165/66
3N188·91

1·58
1·61

Bipolar Dual
Amplifiers
1·16
1·17
1·40
1·43
1·47
1·50
1·51
1·52
1·54
1·71
1·73
1·74
1·51
1·86
1·87
1·90

MOSFET Switchesl
Amplifiers
N·Channel
2N4351

1·56
1·57
1·60
1·75

1·29

NPN Devices
2N4044/45
2N4100
2N4878·80
IT120·22
IT124
IT126/7
LM114
PNP Devices
2N3810/11
2N5117·19
IT130·32
IT136·39

1·20
1·23
1·34
1·65
1·66
1·67
1·83

1·69

Special Function
High Speed Dual Diodes
ID100/1 .
1·62
Voltage Controlled
Resistors
VCR2·7

II

DISCRETE PRODUCT REFERENCE GUIDE
Switches -

Junction FET

Ordering Informalion
Preferred
ParI
Number
Package

Vp
minImax
V

BVGSS
10(Off)
loss
min
max
minimax
pA
V
mA
N-channel: Generally requires driver circuit to translate the popular logic IElVels to voltages required to drive the JFET.
rOS(on)
max
!l

IGSS
max
pA

Ifofal
max
ns

max
pF

50
90
180
65
95

25
25
25
16
16

6.0
6.0
6.0
5.0
5.0

140
55
75
100
34

16
14
14
14
18

5.0
3.5
3.5
3.5
8.0

60
120
34
60
120

18
18
18
18
18

8.0
8.0
8.0
8.0
8.0

41
41
41
24
44

30
30
30
10
10

15.0
15.0
15.0
4.0
4.0

63
65
95
140
55

10
16
16
16
14

75
100
60
60
60

14
14
(70)
(70)
(70)

3.5
3.5
(3.5)
(3.5)
(3.5)

48
48
48

(16)
(16)
(16)

(5.0)
(5.0)
(5.0)

CiSS

erss

max
pF

2N3970
·2N3971
2N3972
2N4091
2N4092

TO-18
TO-18
TO-18
TO-18
TO-18

30
60
100
30
50

-4.0
-2.0
-0.5
-5.0
-2.0

-10.0
-5.0
-3.0
-10.0
-7.0

(- 250)
(-250)
(-250)
-200
- 200

-40
-40
-40
-40
-40

25.0
250
250
200
200

50
25
5
30
15

2N4093
2N4391
2N4392
2N4393
2N4856
2N4857
2N4858
2N4859
2N4860
2N4861

TO-18
TO-18
TO-18
TO-18
TO-18

-1.0
-4.0
-2.0
-0.5
-4.0

-5.0
-10.0
.-5.0
-3.0
-10.0

-200
-100
-100
-100
-250

-40
-40
-40
-40
-40

200
100
100
100
250

8
50
25
5
50

TO-18
TO-18
TO-18
TO-18
TO-18

80
30
60
100
25
40
60
25
40
60

-2.0
-0.8

-6.0
-4.0
-10.0
-6.0
-4.0

-250
- 250
-250
-250
- 250

-40
-40
-30
-30
-30

250
250
250
250
250

2N5432
2N5433.
2N5434
• 2N5638
2N5639

TO-52
TO-52
TO-52
TO-92
TO-92

5
7
10
30
60

-4.0
-3.0
-1.0

-10.0
-9.0
-4.0
-12.0
-8.0

-200
-200
-200
-lnA
-lnA

-25
-25
-25
-30
-30

200
200
200
lnA
lnA

20
8
50
20
8
150
100
30
50
25

2N5640
ITE4091
ITE4092
ITE4093
ITE4391

TO-92
TO-92
TO-92
TO-92
TO-92

100
30
50
80
30

-5.0
-2.0
-1.0
-4.0

-6.0
-10.0
-7.0
-5.0
-10.0

-30
-40
-40
-40
-40

lnA
200
200
200
100

5
30
15
8
50

ITE4392
ITE4393
Jl05
Jl06
Jl07

TO-92
TO-92
TO-92
TO-92
TO-92

60
100
3
6
8

-2.0
-0.5
-4.5
-2.0
-0.5

-5.0
-3.0
-10.0
-6.0
-4.5

-lnA
-200
-200
-200
-100
-100
-100
-3nA
-3nA
-3nA

-40
-40
-25
-25
-25

100
100
3nA
3nA
3nA

25
5
500
200
100

Jlll
Jl12
Jll :i

TO-92
TO-92
TO-92

30
50
100

-3.0
-1.0
-0.5

-10.0
-5.0
-3.0

-lnA
-lnA
-lnA

-35
-35
-35

lnA
lnA
lnA

20
5
2

2N3993
2N3994
2N5114
2N5115
2N5116

TO-72
TO-72
TO-18
TO-18
TO-18

150
300
75
100
150

4.0
1.0
5.0
3.0
1.0

9.5
5,5
10.0
6.0
4.0

1.2nA
1.2nA
500
500
500

25
25
30
30
30

1.2nA
1.2nA
500
500
500

-10.0
-2.0
-30.0
-15.0
-5.0

-90
-60
-25

37
68
102

16
16
25
25
25

4.5
4.5
7.0
7.0
7.0

1T100
IT10l
J174
J175
J176

TO-18
TO-18
TO-92
TO-92
10-92

75
60
85
125
250

2.0
4.0
5.0
3.0
1.0

4.5
10.0
10.0
6.0
4.0

200
200
lnA
lnA
lnA

35
35
30
30
30

100
100
-lnA
-lnA
-lnA

-10.0
-20.0
-20.0
-7.0
-2.0

-100
-60
-25

22
45
70

35
35
(25)
(25)
(25)

12.0
12.0
(8.0)
(8.0)
(8.0)

Jl77
J270
J271
Pl086
Pl087

TO-92
TO-92
TO-92
TO-92
TO-92

300

0.8
0.5
1.5

2.25
2.0
4.5
10.0
5.0

lnA
200
200
2nA
2nA

30
30
30
30
30

-lnA

-1.5
-2.0
--6.0
-10.0
-5.0

~20

90

(25)
32 typo
32 typo
45
45

(8.0)
4.0 typo
4.0 typo
10.0
10.0

~4.0

-2.0
-0.8

150
75
30

150
75
30
100
80
100
80

150
75
30

4.0
5.0
5.0
5.0
3.5 .

P-channel:

75
150

) Approximate Value

1-2

-10nA
-10nA

-15
-50
100
215

Switches and Amplifiers Ordering Information
Preferred
Part
Number
Package

MOSFET

VGSITH)
VGSjOFF)
min max
V

BVGSS
min
V

loss
max
pA

Gfs
min
I'mho

IGSS
max
pA

10
IOION)
minImax
mA

raSION)
max

n

P-Channel Enhancement: Gen. used where max isolation between signal source and logic drive required: sw. "On" resistance varies with signal amptitiude.
3N161
3N163
3N164
3N172
3N173
IT1700

TO-72
TO-72
TO-72
TO-72
TO-72
TO-72

-1.5
-2.0
-2.0
-2.0
-2.0
-2.0

-5.0
-5.0
-5.0
-5.0
-5.0
-5.0

-25
-40
-30
-40
-30
-40

-10nA
-200
-400
-400
-10nA
-200

-100.0
-10.0
-10.0
- 200.0
-500.0
-10.0

3500.0
2000.0
2000.0
(2000.0)
(1000.0)
2000.0

(125)
250
300
250
350
400

-40
- 5
- 3
- 5
- ,5
- 2

- 120 Diode Protected
- 30
- 30
- 30 Diode Protected
- 30 Diode Protected

N-Channel Enhancement: Can switch positive signals directly from TTL logic; gen. requires driver or translator circuit to switch bipolar signals.
2N4351
3N170
3N171
IT1750
M116

TO-72
TO-72
TO-72
TO-72
TO-72

Amplifiers Ordering Information
Preferred
Part
Number
Package

1.0
1.0
1.5
0.5
1.0

5.0
2.0
3.0
3.0
5.0

25
25
25
25
30

10nA
10nA
10nA
10nA
(10nA)

10.0
10.0
10.0
10.0
100.0

1000.0
1000.0
1000.0
3000.0
(1000.0)

300
200
200
50
100

3
10
10
10

100
Diode Protected

N·Channel Junction FET
gfs
min
I'mho

Vp
minImax
V

loss
minImax
mA

-2.0
-1.0
-0.6
-0.3

IGSS
max
pA

BVGSS
min
V

ClSs
max
pF

Crss
max
pF

-5.0
-3.5
-2.0
-1.2
-4.0

-100
-100
-100
-100
-100

-50
-50
-50
-50
-50

4
4
4
4
6

1.2
1.2
1.2
1.2
3.0

140
140
140
140
200

-6.0
-8.0
( -8.0)
-1.8
-1.8

-100
-500
-100
-10
-1

-50
-30
-50
-40
-40

3.0
2.0
3.0
1.5
1.5

200 @ 10Hz

-10
-1
-10
-1
-100

-40
-40
-40
-40
-30

1.5
1.5
1.5
1.5
2.0

-6.0
-8.0
-8.0
-8.0
-1.0

-100
-100
-250
-500
-100

-30
-30
-30
-30
-50

2.0
2.0
2.0
2.0
3.0

-100
-100
-100
-100
-250

-50
-50
-50
-30
-40

7
7
7
4
25

3.0
3.0
3.0
2.0
5.0

65 @ 1kHz
65 @ 1kHz
65 @ 1kHz

en
max
nvl -jHz

2N3684
2N3685
2N3686
2N3687
2N3821

TO-72
TO-72
TO-72
TO-72
TO-72

2000
1500
1000
500
1500

2.5
1.0
0.4
0.1
0.5

7.5
3.0
1.2
0.5
2.5

2N3822
2N3823
2N3824
2N4117
2N4117A

TO-72
TO-72
TO-72
TO-72
TO-72

3000
3500

2.0
4.0

10.0
20.0

70
70

0.03
0.03

0.09
0.09

-0.6
-0.6

2N4118
2N4118A
2N4119
2N4119A
2N4220

TO-72
TO-72
TO-72
TO-72
TO-72

80
80
100
100
1000 .

0.08
0.08
0.2
0.2
0.5

0.24
0.24
0.6
0.6
0.3

-1.0
-1.0
-2.0
-2.0

2N4221
2N4222
2N4223
2N4224
2N4338

TO-72
TO-72
TO-72
TO-72
TO-18

2000
2500
3000
2000
600

2.0
5.0
3.0
2.0
0.2

6.0
15.0
18.0
20.0
0.6

2N4339
2N4340
2N4341
2N4416
2N4867

TO-18
TO-18
TO-18
TO-72
TO-72

800
1300
2000
4500
700

0.5
1.2
3.0
5.0
0.4

1.5
3.6
9.0
15.0
1.2

-0.6
-1.0
-2.0
-0.7

-1.8
-3.0
-6.0
-6.0
-2.0

2N4867A
2N4868
2N4868A
2N4869
2N4869A

TO-72
TO-72
TO-72
TO-72
TO-72

700
1000
1000
1300
1300

0.4
1.0
1.0
2.5
2.5

1.2
3.0
3.0
7.5
7.5

-0.7
-1.0
-1.0
-1.8
-1.8

-2.0
-3.0
-3.0
-5.0
-5.0

-250
-250
-250
-250
-250

-40
-40
-40
-40
-40

25
25
25
25
25

5.0
5.0
5.0
5.0
5.0

5 @ 1kHz
10@1kHz
5 @ 1kHz
10 @ 1kHz
5 @ 1kHz

2N5397
2N5398
2N5457
2N5458
2N5459

TO-72
TO-72
TO-92
TO-92
TO-92

6000
5500
1000
1500
2000

10.0
5.0
1.0
2.0
4.0

30.0
40.0
5.0
9.0
16.0

-1.0
-1.0
-0.1
-1.0
-2.0

-6.0
-6.0
-6.0
-7.0
-8.0

-100
-100
-1nA
-1nA
-1nA

-25
-25
-25
-25
-25

5
5.5
7
7
7

1.2
1.3
3.0
3.0
3.0

3.5dB @ 450MHz

-0.1
-0.1
-0.3

-3.0
-3.0
-6.0
-6.0
-4.0

1-3

•

@
@
@
@
@

100Hz
100Hz
100Hz
100Hz
10Hz

65 @ 1kHz

10@ 1kHz

D

II

Amplifiers Ordering Information
Preferred
Part
Number
Package

N·Channel Junction FET(continued)

\
loss

1.0
4.0
8.0
5.0
0.2

5.0
10.0
20.0
15.0
1.0

Vp
minimax
V
-0.3
-3.0
-0.5
-4.0
-2.0
-6.0
-6.0
-1.5
-0.3

V

Ciss
max
pF

Crss
max
pF

en
max
nv/v'Hz

,-InA
-InA
-InA
-100
_100

-25
-25
-25
-30
-40

5
5
5
4
4

1.0
1.0
1.0
2.0
1.0

120 @ 1kHz
120@lkHz
120 @ 1kHz

5 @ 1kHz
5 @ 1kHz
10@lkHz

2N5484
2N5485
2N5486
ITE4416
J201

TO-92
TO-92 .
TO-92
TO-92
TO-92

gfs
min
I'mho
3000
3500
4000
4500
500

J202
J203
J204
J308
J309

TO-92
TO-92
TO-92
TO-92
TO-92

1000
1500
1500
8000
10,000

0.9
4.0
1.2
12.0
12.0

4.5
20.0
typ.
60.0
30.0

-0.8
-2.0
-0.5
-1.0
-1.0

-4.0
-10.0
-2.0
-6.5
-4.0

-100
-100
-100
-InA
-InA

-40
-40
-25
-25
-25

4
4
4
(8)
(8)

1.0
1.0
1.0
(5.0)
(5.0)

J310
U308
U309
U310

TO-92
TO-52
TO-52
TO-52

8000
10,000
10,000
10,000

24.0
12.0
12.0
24.0

60.0
60.0
30.0
60.0

-2.0
-1.0
-1.0
-2.5

-6.5
-6.0
-4.0
-60

-InA
-150
-150
-150

-25
-25
-25
-25

(8)
7 typ.
7 typ.
7 typ.

(5.0)
4.0 typ.
4.0 typ.
4.0 typ.

10 @ 100Hz typ.
10 @ 100Hz typ.
10 @ 100Hz typ.

IGSS
max
nA

BVGSS
min
V

Ciss
max
pF

Crss
max
pF

en
max
nv/v'Hz

3
10
30

10
17
30

Amplifiers Ordering Information
Preferred
Part
Number
Package
2N2607
2N2608
2N2609
2N5460

TO-18
TO-18
TO-18

2N5461
2N5462
2N5463
2N5464
2N5465
U304
J305
U306

TO-18
TO-18
TO-18

minimax
mA

IGSS
max
pA

. BVGSS
min

5 @ 1kHz

P·Channel Junction FET
gfs
min
I'mho

Vp
minimax
V

loss

minimax
mA

TO-92

330
1000
2500
1000

-0.3
-0.9
-2.0
-1.0

-1.5
-4.5
-10.0
-5.0

TO-92
TO-92
TO-92
TO-92
TO-92

1500
2000
1000
1500
2000

-2.0
-4.0
-1.0
-2.0
-4.0

-9.0
-16.0
-5.0
-9.0
-16.0

-30.0
-15.0
-5.0

-90.0
-60.0
-25.0

1.0
1.0
1.0

4.0
4.0
4.0

0.75

6.0

30
30
30
40

1.0
0.75
1.0
1.8

7.5
9.0
6.0
7.5
9.0

40
40
60
60
60

5.0
3.0
1.0

10.0
6.0
4.0

U·

1-4

.5
.5
.5

30
30
30

27
27
27

400
140
140
115

@ 1kHz
@ 1kHz
@ 1kHz
@ 100Hz

115
115
115
115
115

@ 100Hz
@ 100Hz
@ 100Hz
@ 100Hz
@ 100Hz

J

Differential Amplifiers Preferred
Part
Number

Package

Dual Monolithic N·Channel Junction FET

VGSI-2

AVGS

IG

BVGSS

Vp

max
mV

max
~V/oC

max
pA

min
V

minimax
V

2N3921
2N3922
2N3954
2N3954A
2N3955

TO-71
TO-71
TO-71
TO-71
TO-71

5
5
5
5
10

2N3955A
2N3956
2N3957
2N3958
2N5196

TO-71
TO-71
TO-71
TO-71
TO-71

2N5197
2N5198
2N5199
2N5452
2N5453

loss

gls
minimax

-250
-250
-50
-50
-50

-50
-50
-50
-50
-50

-1.0
-1.0
-1.0

-3.0
-3.0
-4.5
-4.5
-4.5

1500
1500
1000
1000
1000

7500
7500
3000
3000
3000

1.0
1.0
0.5
0.5
0.5

15
15
20
25
5

10
25
10
5
25
15
50
75
100
5

-50
-50
-50
-50
-15

-50
-50
-50
-50
-50

-1.0
-1.0
-1.0
-1,0
-0.7

-'4,5
-4.5
-4,5
-4,5
-4.0

1000
1000
1000
1000
700 @

3000
3000
3000
3000

0.5
0,5
0,5
0,5
0.7

TO-71
TO-71
TO-71
TO-71
TO-71

5
10
15
5
10

10
20
40
5
10

-15
-15
-15
IGSS-l00
IGSS -100

-50
-50
-50
-50
-50

-0.7
-0.7
-0.7
-1.0
-1.0

-4.0
-4.0
-4.0
-4,5
-4,5

700 @ 200~A
700 @ 200~A
700 @ 200~A
1000
4000
1000
4000

2N5454
2N5515
2N5516
2N5517
2N5518

TO-71
TO-71
TO-71
TO-71
TO-71

15
5
5
10
15

25
5
10
20
40

IGSS-l00
-100
-100
-100
-100

-50
-40
-40
-40
-40

-1,0
-0.7
-0.7
-0.7
-0.7

1000
1000
1000
1000
1000

2N5519
2N5520
2N5521
2N5522
2N5523

TO-71
TO-71
TO-71
TO-71
TO-71

15
5
5
10
15

80
5
10
20
40

-100
-100
-100
-100
-100

-40
-40
-40
-40
-40

-0.7
-0.7
-0..7
-0.7
-0.7

-4.5
-4,0
-4.0
-4,0
-4.0
-4,0
-4.0
-4,0
-4.0
-4,0

2N5524
2N5902
2N5903
2N5904
2N5905

TO-71
TO-99
TO-99
TO-99
TO-99

15
5
5
10
15

80
5
10
20
40

-100
-3
-3
-3
-3

-40
-40
-40
-40
-40

2N5906
2N5907
2N5908
2N5909
2N5911

TO-99
TO-99
TO-99
TO-99
TO-99

5
5
10
15
10

-1
-1
-1
-1
-100

-40
-40
-40
-40
-25

-4,0
-4,5
-4,5
-4,5
-4.5
-4,5
-4,5
-4,5
-4,5
-5,0

2N5912
2N6483
2N6484
2N6485
IMF6485

TO-99
TO-71
TO-71
TO-71
TO-71

15
5
10
15
25

5
10
20
40
20
40
5
10
25
40

-0.7
-0,6
-0,6
-0,6
-0.6
-0,6
-0.6
-0.6
-0,6
-1.0

-100
-100
-100
-100
-100

- 25
-50
-50
-50
-50

-1.0
-0.7
-0.7
-0.7
-0.7

IT500
IT501
IT502
IT503
IT504

TO-52
TO-52
TO-52
TO-52
TO-52

5
5
10
15
25

5
10
20
40
100

-5
-5
-5
-5
-5

-50
-50
-50
-50
-50

IT505
IT5911
IT5912
U257
U401

50
10
15
100
5
10
10
15
20
40

200
20
40

-5
-100
-100
IGSS-l00
-15

-50
-25
-25
-25
-50

1 U402
U403
U404
U405
U406

TO-52
TO-71
TO-71
TO-99
TO-71
TO-71
TO-71
TO-71
TO-71
TO-71

-15
-15
-15
-15
-15

-50
-50
-50
-50
-50

-0.7
-0,7
-0.7
-0.7
-0.7
":'0.7
-1,0
-1.0
-1.0
-0.5
-0,5
-0,5
-0.5
-0,5
-0.5

-5,0
-4,0
-4.0
-4.0
-4.0
-4,0
-4.0
-4.0
-4,0
-4,0

U421
U422
U423
U424
U425

TO-99
TO-99
TO-99
TO-99
TO-9g

10
15
25
10
15

10
25
40
10
25

-60
-60
-60
-60
-60

U426

TO-99

25

40

-60

10
10
25
25
40
80

0.1
0.1
0,1
0.5
0.5
0,5

200~A

en
max
nV/yHz

min/max
mA

~mho

10.0
10.0
5.0
5.0
5.0
5,0
5,0
5,0
5,0
7,0

160 @ 100Hz
160 @ 100Hz
160 @ 100Hz
160
160
160
160
20

@ 100Hz
@ 100Hz
@ 100Hz
@100Hz
@ 1kHz

7,0
7.0
7.0
5,0
5,0

20 @ 1kHz
20 @ 1kHz
20 @ 1kHz
20 @ 1kHz
20.@ 1kHz

4000
4000
4000
4000
4000

0.7
0,7
0.7
0.5
0.5
0,5
0.5
0.5
0.5
0.5

5,0
7,5
7,5
7,5
7.5

20
30
30
30
30

1000
1000
1000
1000
1000

4000
4000
4000
4000
4000

0.5
0.5
0,5
0,5
0,5

7,5
7,5
7,5
7.5
7,5

30 @ 10Hz
15 @ 10Hz
15@10Hz
15 @ 10Hz
15@10Hz

1000
70
70
70
70

4000
250
250
250
250

0.5
0.3
0.03
0.03
0,03

7,5
0.5
.05
.05
.05

15@10Hz
200 @ 1kHz
200 @ 1kHz
200 @ 1kHz
200 @ 1kHz

250
250
250
250
5/10 @ 5 mA

0,03
0.03
0,03
0,03
7,0

.05
.05
,05
05
40,0

100@lkHz
100 @ 1kHz
100 @ 1kHz
100 @ 1kHz
20 @ 10kHz

5/10 @ 5 mA

7.0
0.5
0.5
0,5
0,5

40,0
7,5
7,5
7,5
7.5

20
10
10
10
15

@
@
@
@
@

10kHz
10Hz
10Hz
10Hz
10Hz

7,0
7,0
7,0
7,0
7,0

35
35
35
35
35

@
@
@
@
@

10Hz
10Hz
10Hz
10Hz
10Hz

7,0
40,0
40.0
40,0
10.0
10,0
10,0
10,0
10.0
10,0

35
20
20
30
20
20
20
20
20
20

@
@
@
@
@
@
@
@
@
@

10Hz
10kHz
10kHz
10kHz
10Hz
10Hz
10Hz
10Hz
10Hz
10Hz

@ 10Hz
@ 10Hz
@ 10Hz
@ 10Hz
@ 10Hz

70
70
70
70

1000
1000
1000
1000

4000
4000
4000
4000

700
700
700
700
700

1600
1600
1600
1600
1600

700

1600

@ 1kHz
@ 10Hz
@ 10Hz
@ 10Hz
@ 10Hz

-4,0
-5,0
-5,0
-5.0
-2.5
-2,5
-2,5
-2,5
-2,5
-2,5

5000
2000

10000
7000

0.7
0.7
0.7
0.7
0.7
0,7
7.0
7,0
5.0
0,5

2000
2000
2000
2000
2000

7000
7000
7000
7000
7000

0,5
0.5
0.5
0,5
0.5

-0.4
-0,4
-0.4
-0.4
-0.4

-2,0
-2,0
-2,0
-3.0
-3,0

300
300
300
300
300

800
800
800
1000
1000

60-1000~A
60-1000~A
60-1000~A
60-1000~A
60-1000~A

20
20
20
20
20

-0.4

-3,0

300

lobo

60-1000~A

20 @ 10Hz

1-5

5/10 @ 5 mA
5/10 @ 5 mA

0

Differential Amplifiers Ordering Inlormation
Prelerred
Part
Number
Package

D

3N165
3N166
3N188
3Nt89
3N190
3N191

TO-99
TO-99
TO-99
TO-99
TO-99
TO-99

VGS(TH)
minImax
V
-2
-2
-2
-2
-2
-2

Differential Amplifiers Ordering Inlormation
Prelerred
Part
Number
Package
2N4044
2N4045
2N4100
2N4878
2N4879
2N4880

TO-78
TO-78
TO-78
TO-71
TO-71
TO-71

IT120

TO-78 TO-71

IT120A
1T121
1T122
1T124

TO-78 TO-71
TO-78 TO-71
TO-78 TO-71
TO-78

1T126
1T127
IT128
1T129

Dual Monolithic P·Channel MOSFETS
(Enhancement)
,

-5
-5
-5
-5
-5
-5

BVoss
minImax
V

loss
max
pA

IGSS
max
pA

Gfs
min
jtmho

-40
-40
-40
-40
-40
-40

-200
-200
-200
-200
-200
-200

-10
-10
-200
-200
-200
-200

1500
1500
1500
1500
1500
1500

rOS(ON)
max
11

10SION)
min max
mA
-5.0
-5.0
-5.0
-5.0
-5.0
-5.0

-30
-30
-30
-30
-30
-30

300
300
300
300
300
300

Vas 1-2
max
mV
100
100 Zener Protected
Zener Protected
100 Zener Protected

Dual NPN Bipolar Transistors

VBE 1-2
mV
max

.lVBE
jtV/oC
max

hFE '"
Ic= 10jtA
VCE=5V
min

3
5
5
3
5
5

3
10
5
3
5
10

200
80
150
200
150
80

IB 1-2 @
Ic = 10jtA
VCE=5V
nA
max

BVCEO
V
min

ICBO
nA
max

5
25
10
5
10
25

60
45
55
60
55
45

.1
.1
.1
.1
.1
.1

200

Noise
dB
max

11
MHz@lc
min

2
3
3
2
3
3

200
150
150
200
150

1~0 @

lmA
lmA
lmA
lmA
lmA
lmA,

220

lmA

@
@
@
@
@

45

1

2 typo

1
1
1
.1

2 typo
2 typo
2 typo
3

220 @ lmA
180@ lmA
180 @ lmA
100 @ 100~A

@

Cobo
pF
max
0.8
0.8
0.8
0.8
0.8
0.8

Structure
Dielec.
Dielec.
Dielec.
Dielec.
Dielec.
Dielec.

1501.
Isol.
1501.
1501.
1501.
Isol.

Junc. 1501.

200
80
80
1500

2.5
25
25
0.6@
VCE = 1V

45
45
45
2

TO-78 TO-71
TO-78 TO-71
TO-78 TO-71

3
5
10

200
200
150

2.5
5
10

60
60
45

.1
.1
.1

1 typo
1 typo
1 typo

250
250
200

@
@
@

10mA
10mA
10mA

Dielec. 1501.
Dielec. 1501.
Dielec. 1501.

TO-78 TO-71

20

100

20

45

.1

1 typo

150

@

10mA

Dielec. 1501.

1-6

2
2
2
0.8

Jur;c.
Junc.
Junc.
Junc.

3
10
20
15

1
3
5
5

1501.
1501.
1501.
1501.

Differential Amplifiers Ordering Inlormation
Prelerred
. -Pari
Number
Package

VSE 1-2
mV
max

2N5117
2N5118
2N5119
IT130
1T130A

TO-78
TO-78
TO--78
TO-78 TO-71
TO-78 TO-71

IT131
IT132
1T136
IT137
1T138

TO-78
TO-78
TO-78
TO-78
TO-78

IT139

TO-78 TO-71

TO-71
TO-71
TO-71
TO-71
TO-71

Dual PNP Bipolar Transistors
hfE @

IC=10~

AVBE

IC=10~A

~V/oC

VCE=5V

VCE=5V
nA
max

BVCEO
V
min

ICBO
nA
max

Noise
dB
max

It

Cobo

MHz@lc
min

max

Structure

pF

max

,min

3
5
5
2
1

3
5
10
5
3

100
100
50
200
200

10
15
40
5
2.5

45
45
45
-45
-60

.1
.1
.1
1
t

4
4
4
2 typo
2 typo

100 @0.5mA
100 @0.5mA
100 @0.5mA
110@lmA
110@lmA

.8
.8
.8
2
2

Dielec. Isol.
Dielec. Isol.
Dielec. Isol.
Junc. Isol.
Junc. Isol.

5
10
1
2
3

10
20
3
5
10

80
80
150
150
120

10
25
2.5
5
10

-45
-45
-60
-60
-55

1
1
.1
.1
.1

2 typo
2 typo
2 typo
2 typo
2 typo

90 @lmA
90@lmA
150 @10mA
150@10mA
180 @10mA

2
2
4
4

Junc. Isol.
Junc. Isol.
Dielec. Isol.
Dielec. Isol.
Dielec. Isol.

20

70

20

-45

.1

2 typo

100 @10mA

Dielec. Isol.

Specially Items
10-100
10-101

This product is a diode combination used to protect those P-channel MOSFET duals which are not diode protected. Their chief characteristic
is < 1 pA leakage when voltage across them is less than 5 mV. If voltage across diodes is adjusted to OV ± 0.1 mV. leakage is less than
0.01
pA.

VCR2N
VCR3P
VCR4N
The VCR family consists of three terminal variable resistors where the resistance value between two of the terminals is controlled by the
VCR5P
voltage potential applied to the third.
VCR7N
VCR11 N (Dual)

Note: Intersil offers the following military qualified devices:'
N-channel switches
2N4091
2N4092
2N4093
2N4856
2N4857
2N4858

JAN.
JAN.
JAN.
JAN.
JAN.
JAN.

JANTX.
JANTX.
JANTX.
JANTX.
JANTX.
JANTX.

JANTXV
JANTXV
JANTXV
JANTXV
JANTXV
JANTXV

N-channel amplifiers

P-channel switches

P-channel amplifiers

2N3821 JAN. JANTX. JANTXV
2N3823 JAN. JANTX. JANTXV

2N5114 JAN. JANTX. JANTXV
2N5115 JAN, JANTX. JANTXV
2N5116 JAN, JANTX, JANTXV

2N2609 JAN

* JAN processing consists of a sample Group B pulled from the production run

JANTX processing consists of JAN processing plus 100% electrical read and record, and 100% burn-in.
JANTVX processing consists of JANTX processing plus 100% pre-cap visual and on-shore assembly.

1-7

D

II

DISCRETE SELECTOR GUIDE

Recommended Part Number.
Detailed
Application

Audio
Buffer
Differential
Fetlnput Op Amp
High Impedance

Amplifiers High Frequency

low noise

2N4220,
2N3821
low leakage, high 2N4221
gain
good matching &
drift
2N4117A
low leakage

high gain, low

U308

Low Noise

2N5397
2N4338
2N3687
2N4867A

Preamplifier

high gain

2N5397
U310

Video
VHF

high gain, low
capacitance
RF parameters,

UHF

high gfs/Ciss

Commutators '

lowCrss

Sample and Hold
Analog Gates

fast switching,

Switches

Digital
Chopper
Integrator Reset
Gain Control
Amplitude Stability
Attenuators
Protection Signal Clipping
and Clamping
Diodes
Voltage
Control
Resistors

Single
N-Channel
JFET

capacitance
low pinch-of!
voltage
low noise

Low Supply Voltage

Mixers

Important
Parameters

low rOSlon)
low rOSlon), high
loss
high VGSloff)

2N4393
ITE4393
U310
2N5397
J310
2N5484
2N4391
. ITE4391

Single
Single
Dual
Single
Dual
P-Channel N-Channel N-Channel P-Channel P-Channel
JFET
JFET
MOSFET
MOSFET
MOSFET

2N2607
2N5460
2N2609
2N5462

-

1T100
J176
2N5116
2N5114

2N3958
IT505
2N5905
IT505
2N3954
U401
2N5515
2N5905
IT505
U426
2N5912

J176
2N5265
J177
2N5116
J176
2N5116
J176

IT5912
U406
2N3958
2N5519
2N5199
IT550
U406

IT100

IT5912
2N5912
2N6485

IT100
J174
2N5114

3N163
3N164
3N172
IT1700

2N4044 IT130
2N4878
IT120
IT136
3N165

,

-

-

IT1750
2N4351

IT1700
3N163

I

1T126

3N188

3N164

3N170-1
M116

2N3810

-

2N4044 IT130
2N4878
IT120
IT136
IT126
2N3810
IT140

3N172
2N4044
2N4044
2N4878
IT120
IT126

IT1750

IT130
IT130
IT136
2N3810

3N170-1

-

IT1700
3N163

3N165

3N164
3N172

3N188

-

-

-

-

-

-

10100-1

1-8

Dual
PNP
Bipolar

IT5912
2N5912

2N3993-4
1T100-1
IT550
2N5114-6
2N4091-3. 2N5114-6 2N5912
2N4391-3
ITE4391-3 J174-7
IT5912
2N5432-4 1T100-1
J111-3
J105-7
VCR2N
VCR3P
VCR4N
VCR11N
VCR7N

low leakage
current

2N4351
3N170-1
M116
IT1750

Dual
NPN
Bipolar

1T139

2N2607-2N2609
2N2609 JAN
P-Channel JFET
PIN
CONFIGURATION

APPLICATIONS
• Low-level Choppers
• Data Switches
• Commutators

CHIP
TOPOGRAPHY
5510

(lor 2N2607. 8)

TO-18

::;:~'UllR

S'"

. ri'- T
m
IIIl!J
I

011
015

OOl~

003'>

ABSOLUTE MAXIMUM RATINGS

l(

OO.'!,
DOl!> "-

~ '"0" -i

I

0046

(TA = 25° C unless otherwise noted)

0050

Gate-Source Voltage ............................ 30 V
Gate-Drain Voltage .............................. 30 V
Gate Current ................................. 50 mA
Storage Temperature Range. . . . . . . . .. -65° C to +200° C
Operating Temperature Range ....... -55°C to +150°C
Lead Temperature (Soldering, 10 sec( ......... +300°C
Power Dissipation ........................... 300 mW
Derate above 25°C ...................... 2 mWrC

~
M)l f

SuBS TAA T[

ISGAH

D G,C

5503
003'

(lor 2609. 2609 JAN)

003'

I~':;; ,~'."
~

0"0

J_

r-

/'

002'

-

--I

6~:6

NOH

~~~~~~flTE

ORDERING INFORMATION*
WAFER
TO·18
2N2607/W
2N2607
2N2608/W
2N2608
2N2609
2N2609/W
2N2609 JAN

--

DICE
2N2607/D
2N2608/D
2N2609/D

-

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (@ 25°C unless otherwise noted)
2N2607

2N260B

2N2609

Test Conditions

PARAMETER
Min

iGSSR

Max

Min

Max

Min

Max

BVGSS

Gate-Drain Breakdown
Voltage

30

Vp

Gate-Source Pinch-Off

1

3

10

30

nA

V GS = 30 V, VOS = 0

3

10

30

!J.A

V GS = 5 V, VOS = 0, T A = 1500 C

V

1G = 1 !J.A, VOS = 0

V

V DS = -5 V,IO =

OSS

rnA

V OS = - 5 V, V GS = 0

prnho

V OS =-5V,V GS =0,f= 1 kHz

pF

V OS =-5V, VGS~ 1 V.

30
4

1

30
4

1

4

-2

-10

Voltage
Drain Current at Zero Gate

I

Unit

Gate Reverse Current
i

-0.30 -1.50 -0.90 -4.50

Small·Signal Common-Source
Forward Transconductance

Ciss

Common-Sou rce Input
Capacitance

330

1000
10

2500
17

30

f = 140 kHz

V OS =-5V,

3
NF

-1!J.A

Voltage

gf,

dB

Noise Figure

3

1-9

3

V GS = 0,
f = 1 kHz

R G =10Mrl
R

G

=

.002'

lMrl

II

II

.n~n[6

2N3684 .. 2N3687

N·Channel JFET
PIN
CONFIGURATION

FEATURES
• Low Noise
• High Input Impedance
• Low Capacitance

TO-72

APPLICATIONS
• Low Level Choppers
• Data Switches
• Multiplexers
• Low Noise Amplifiers
CHIP
TOPOGRAPHY
5010-

ABSOLUTE MAXIMUM RATINGS
(T A = 25° C unless otherwise noted)

Oil)

~
'~I

:~~fllllR

Gate-Source or Gate-Drain Voltage •............ " -50V
Gate Current ..••............................. 50 mA
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.), ........ +300°C
Power Dissipation ........................... 300 mW
Derate above 25° C .. ,............... 1.7 mW/o C

.{1'.
0025

.0025

~ :6~

0035 X .0035

::.

~
NOTE- SUBSTRATE

IS GATE
.011

01.

·OICE wnH 4 MIL BONDING PADS
AVAILABLE. CONSULT FACTORY
fOR DETAILS.

ORDERING INFORMATION·
TO-72

WAFER

DICE

2N3684
2N3685
2N3686
2N3687

2N3684/W
2N3685/W
2N3686/W
2N3687/W

2N3684/D
2N3685/D
2N3686/D
2N3687/D

'When ordering wafer/dice refer, to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
BVGSS Gate to Source Breakdown Voltage
Vp
Pinch-Off Voltage
Total Gate Leakage Current
IGSS
I TA-150C
lOSS
IY!s!'

Saturation Current, Drain-ta-Source
Forward Transadmittance

Gos

Common Source Out-

put Conductance
Common Source Input
Ciss
9apacitance
Common Source Short
C,ss
Circuit Reverse Transfer Capacitance
'OS(on) On Resistance
NF
Noise 'Figure
,\~

2N3684
MIN
MAX

2N3685
MIN
MAX

2N3686
MIN
MAX

2N3687
MIN
MAX

"50
2.0

-50
1.0

-50
0.6

-50
0.3

2.5
2000

5.0
-0.1
-0.5
7.5
3000

1.0
1500

3.5
-0.1
-0.5
3.0
2500

0.4
1000

2.0
-0.1
-0.5
1.2
2000

0.1
500

V

1.2
-0.1
-0.5
,0.5
1500

J1mhos

nA

VOS = 0, IG = 1.0 ~A
VOS- 20 V, 10 - 0.001 ~A
'VGS - -30 V, VOS - 0

~A

rnA,

50

25

10

5

,umhos

4.0

4.0

4.0

4.0

pF

1.2

1.2

1.2

1.2

pF

600
0.5

800
0.5

1200
0.5

2400
0.5

1-10

TEST CON DITIONS

UNITS

Ohms
dB

VGS - 0, VOS - 20 V

VOS=20V,VGS=0,
! = 1 kHz.

VOS" 0, VGS - 0
100 Hz, RG - 10 M n
NBW = 6 Hz, VOS" 10V
~GS = OV

f

2N3810/A,2N3811/A
Monolithic Dual Matched
PNP Transistor
PIN
CONFIGURATION
TO-78

D

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Emitter-Base Voltage (Note'1) ......... "" ............ -5V
Collector-Base or COllector-Emitter Voltage (Note 1) ... -60V
Collector Current (Note 1) ........................ 50 mA
Storage Temperature Range .............. -65°C to +200°C
Operating Temperature Range ............ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............ +300°C
Power Dissipation .............. .
Derate above 25° C ...... . ..

ONE SIDE
500 mW
2.9 mW/oC

4501

CHIP
TOPOGRAPHY

BOTH SIDES
600 mW
3.4 mW/oC

[MITTER ~

.Q..ol!

0039 ~ .0039
TVP 2 PLACES

BA.SE

EMITTER

COLlf.CTOR

BASE

0035

0030

_OOlO

0040 It ,0040

TVP 2 PLACES

0034

iii45" "'0044
TYP. 2 PLACES

ORDERING INFORMATION*
TO·78
WAFER
r-m3810- 2N3810/W

DICE
2N3810/D

2N38111W

2N3811/D

~1DA
2N3811
2N3811A

ELECTRICAL CHARACTERISTICS

'When ordering wafer/dice refer to Appendix B·23.

TEST CONDITIONS: 25°C Ambient Temperature unless otherwise noted
2N38101A

SYMBOL
BVCBO
BVCEO
~.

BVEBO
leloffl
IE(Off)

hFE

~MAX

PARAMETER
C()Ue~~or-Base B...':E'~C!9wn yolt~

CoUector-Emltter Breakdown
Voltage (Note 2
.Emitter-Base Breakdown Voltage
CoUector Cutoff Current
JTA-+150°C
Emitter Cutoff Current
Static Forward Current
Transfer Ratio! Note 2
ITA = -55°C

VeE!sall

Base-Emitter Saturation Voltage (Note 21

VCElsall

CoUector-Emltter Saturation VOltage'
INote2

hie
hie
h'e
hoe
I hie'

Input Impedance
Forw'ard Current Transfer Ratio
Reverse Voltage Transfer Ratio
Output Admittance
Magnitude of small signal
. current gain

-60
-60
-5

-

2N3811/A
MIN
MAX
-60

V

-60
-5

,10
-10
-20
100
ISO
125
75

450

UNITS

,'0
-10
-20
225
300
250
150

nA
"A
nA

90
0035 II QOJ!i

(

..."'" r. T

---L

0130

0180

~T- • •
,ou,,,;""- _ t
i\

, ~,\'f-.i.
0025.0025

SUBSfAATf.

IS GATE

:i;

O~AIN

1I(l1!;" 0035

lr

fUll A

ORDERING INFORMATION·
WAFER

TO·72

CHIP

2N4117
2N41171W
. ._ - - - - ._2N4117/D
2N4117A
2N4118
- . - - - - - - .1~4111!f~
- - - f -2N4118/W
2N4118A
2N41191W 2N4119tD
2N4119
2N4119A
-

-

-

-

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS 125°C unless otherwise noted)
2N4117
2N4117A
MIN
MAX

PARAMETER
Gate·Source Breakdown Voltage

BVGSS

Gate Reverse Current

IGSSR

Qls
Sis

I A devices

Gate·Source Pinch-Off Voltage
Drain Current at Zero Gate
Voltage INote 11

Ciss
Crss
NOTE: 1.

-1
-25

-0.6

-2.5
-1.8

-1

-3

-2

-6

0.02

0.09

0.08

0.24

0.20

0.60

70

210

80

250

100

330

Common-Source Forward

Transconductance INote 11
Common-Source Forward
Transconductance
Conductance
Common -Source Input
Capacitance
Common-Source Reverse
Transfer Capacitance

-2.5

70

60

UNIT
V

-10

-10
-1
-25

-1
-25

Common-Source Output

gos

2N4119
2N4119A
MIN
MAX
-40

-40

-10

I TA = +100'C I A devices

VGS loffl
IDSS

-40

2N4118
2N4118A
MIN
MAX

-2.5

90
5

10

3

3

3

VGS= -20 V, VDS= 0
nA
V
mA

1.5

Pulse test: Pulse duration of 2 ms used during test.

1-25

1.5

VDS = 10 V, ID = 1 n,ll
VDS· 10 V
VGS= 0
VDS-l0V
f = 1 kHz
VGS = 0, I = 30 MHz
VDS=lOV,VGS=O,
1= 1 kHz

pF

1.5

IG = -1 }lA, VDS= 0

pA

ilmho

3

TEST CONDITIONS

VDS= 10 V, VGS = 0,
f = 1 kHz
VDS=10V,VGS=0,
f = 1 kHz

2N4220·2N4222

N·ChanneIJFET
PIN
CONFIGURATION

FEATURES
• C rss < 2 pF

TO-72

• Moderately High Forward Transconductance

D

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ................. -30V
Gate Current :................................... 10 mA
Storage Temperature Range ............. -65° C to +200° C
Operating Temperature Range ........... -55°C to +150°C
Lead Temperatljre (Soldering, 10 sec.) ........... +300°C
Power Dissipation .............................. 300 mW
Derate above 25°C ..................... 1.7 mW/oC

CHIP TOPOGRAPHY
5010'
0121

""1!fi:
Ji.091l;O5 •. 0025

:om

.0035

~ m~

,"ceo

I
-L
NOTE: SUBSTRA. TE
ISGAT£

.011

-m

·OICE WITH. MIL BONDING PADS

AVAILABLE. CONSULT FACTORV
FOR OETAILS.

ORDERING INFORMATION*
WAFER
2N4220/W
2N4221/W
2N4222/W

TO·72
2N4220
2N4221
2N4222

DICE
2N4220/D
2N4221/D
2N4222/D

'When ordering wafer/dice refer to Appendix 6·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
IGSSR

2N4220
MIN
MAX

2N4221
MIN
MAX

-0.1
-0.1

-0.1
-0.1

Gate Reverse Current

BVGSS
VGS(off)

ITA -150°C
Gate-Source Brej3kdown Voltage
Gate-Source Cutoff Voltage

-30

VGS

Gate-Source Voltage

-0.5

C30

-0.1
-0.1
-30

_._.

-6

4
-2.5

2N4222
MIN
MAX.

-1

-5

-8
-2

-6

TEST CONDITIONS

UNIT
nA
gA

V

VGS= -15 V. VDS = 0
IG - -10pA, VDS - 0
VDS = 15 V, ID - 0.1 nA

V

VOS

IDSS

9fs
iYlsl
gas
Cjss

Saturation Drain Current

(Note 3)
Common-Source Forward
Transconductance (Note 1 j

Common-Source Forward
Transadmfttance
Common-Source Output
Conductance (Note 1 )
Common-Source Input

Capacitance
Common-Source Reverse
C rss
Transfer Capacitance
NOTE 1. Pulse test duratIon 2 ms.

0.5

3

2

6

5

15

1000

4000

2000

5000

2500

6000

750

750

750

rnA

\ 10
10
10

=50 !LA 12N4220)
= 200 pA 12N4;221)
=500 !LA 12N4222)

VDS= 15V, VGS=O

f = 1 kHz
1=100MHz

}Jmho

iO

20

40

6

6

6

2

2

2

VDS= 15V, VGS=O

pF

1-26

= 15V

f = 1 kHz

1=1 MHz

2N4223,2N4224
N·ChanneIJFET
FEATURES
• NF = 3 dB Typical at 200 MHz
! Crss< 2 pF

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-72

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage ........•........ -30V
Gate Current............. ....................... 10 mA
Storage Temperature Range ............• -65°C to +200°C
Operating Temperature Range ........... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........... +300°C
Power Dissipation ......•....................... 300 mW
Derate above 25°C ..•......•........•.. 1.7 mW;oC

s

ORDERING INFORMATION·
TO·72
2N4223
2N4224

WAFER
2N4223/W
2N4224/W

DICE
2N4223/D
2N4224/D

·When ordering wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted I
PARAMETER

2N4223
MIN
MAX

2N4224
MIN
MAX

-0.25
-0.25

-0.5
-0.5

= +1500C

IGSSR

Gate Reverse Current, TA

BVGSS

Gate·Source Breakdown Voltage

VGS(off)

Gate·Source Cutoff Voltage

-30
-0.1

-8

-30
-0.1

UNIT
nA
pA

Gate·Source Voltage

lOSS

Saturation Orain Current (Note 1)

9ts

Common·Source Forward
Transconductance (Note 1)

IG - -10pA, VOS - 0

Ciss
Crss
IVfsl
giss

Common·Source Forward
Transadmittance
Common·Source Input
Conductance (Output Shorted)

Gps

Common·Source Output
Conductance (Input Shorted)
Small Signal Power Gain

NF

Noise Figure

goss

-1.0

-7.0

-1.0

-7.5

3

18

2

20

3000

7000

2000

7500

Common·Source Input
Capacitance (Output Shorted)
Common·Source Reverse
Transfer Capacitance

Note 1: Puis. test, duratIon 2 msec.

mA

VOS = 15V

10 = 0.25 nA (2N4223)
10 = 0.5 nA (2N4224)
10. = 0.3 mA (2N4223)
10 =0.2 mA (2N4224)

VOS=15V,VGS=0
f

I1mho

6

6

VGS= -20 V, VOS=O

-8
V

VGS

TEST CONOITIONS

VOS=15V,VGS=0
f = 1 MHz

pF
2

2
2700

= 1 kHz

1700
800

800

200

200

I1mho
VOS=15V,VGS=0
f = 200 MHz

10
5

dB

1-27

VOS - 15 V, VGS - 0,
Rgen = lkfl

I

2N4338·2N434.1
N·Channel JFET
'

PIN
CONFIGURATION

FEATURES

II

•
•
•
•

.

Exception~ny High Figure of Merit
Radiation Immunity
,
Extremely Low Noise and Capacitance
High Input Impedance

TO-1S

APPLICATIONS
• Low-level Choppers
• Data Switches
• Multiplexers and Low Noise Amplifiers

CHIP
TOPOGRAPHY

,ABSOLUTE MAXIMUM RATINGS

m

(T A = 25° C unless otherwise noted I

5040

Gate-8ource or Gate-Drain Voltage .............. -50V
Gate Current •.....•.................. " . . . . •. 50 mA
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering. 10 sec.) .•..•... +300°C
Power Dissipation ........................... 300 mW
Derate above 25°C .................. 1.7 mW/oC

0121

,~u

•

Sill
002Sl

0035

x

0025

0035

.~.

::::a,u",

T

OT!

IWIj'15
,~
I

~ .::::~

:Non:

011

SUBSTRATE
IS GATE

011)

-DICE WITH 4 Mil BONDING PADS
AVAILABLE. CONSULT FACTORY

FOR DET AI LS.

ORDERING INFORMATION*
TO·18

WAFER

DICE

2N4338
2N4339
2N4340
2N4341

2N43381W
2N4.331l1W
2N4340/W
2N4341/W

2N4338/D
2N4339/0
2N4340/0
2N4341/0

'When orderihg waferJdicerefer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise hOted)
PARAMETER
less

TA -150"C
Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage

'O(off)

Drain Cutoff Current

'OSS

Saturation Drain Current

90,
rOSlon)

Ciss
Crss
NF

2N4339
MAX
MIN

2N4340
MIN
MAX

2N4341
MIN
MAX

-0.1
-0.1

-0.1
0.1

-0.1
-0.1

-0.1
0.1

Gate Reverse Current

BVess
VeS(off)

9f,

2N4338
MIN
MAX

Common-Source Forward
Transconductance
Common-So,urce Output
Conductance
Drain-Source ON Resistance
Common-Source Input
Capacitance
Common-Source Reverse
Transfer Capacitance

Noise Figure

-50
-0.3

1
0.05
(-5)

-50
-0.6

-1.8
0.05
(-5)

02

0.6

0.5

1.5

600

1800

800

2400

-50
-I

1.2
1300

-3
0.05
1-5)
3.6
3000

-50
2

nA
pA

TEST CONDITIONS
Ves ~ -30 V. Vos ~ 0

6
0.07
(-10)

nA
IV)

IG -1 pA, Vos - 0
Vos 15V,IO 0.1 pA
Vos -15V,
VGS~ I )

3

9

mA

VOS~15V.Ves~0

2000

4000
I1mho

VOS~ 15V.Ves~0

5

15

30

60

2500

1700

1500

800

7

7

7

7

3

3

3

3

1

1

1

1

1-28

UNITS

V

f

ohm

VOS

~

1 kHz

O.'os~O

f~

pF

VOS~15V,VGS~0

dB

Vos - 15 V, VGS 0
f
Rgen"" 1 meg, BW,= 200'Hz

~

1 MHz

1 kHz

2N4351

N-ChannelEnhancement
Mode MOS FET

FEATURES
•
•
•
•
•

Low ON Resistance
Low Capacitance
High Gain
High Gate Breakdown Voltage
Low Threshold Voltage

PIN
CONFIGURATION
TO-72

II

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C .unless otherwise noted)
Drain-Source Voltage or Drain-Gate Voltage ....... 25V
Peak Gate-Source Voltage (Note 1) ............. ±125V
Drain Current ................................ 100 mA
Storage TemperallJre Range .......... -65°C to +200°C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
Power Dissipation ........................... 375 mW
Derate above 25°C .................... 3 mW/oC

CHIP
TOPOGRAPHY
1003

i

I
014Q

0180

NOTE

SUBSTRATE
IS800Y

ORDERING INFORMATION*

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
Substrate connected to source.
PARAMETER

MIN

BVoss

Drain~Source

IGSS

Gate Leakage Current

lOSS

Zero·Gate-Voltage Drain Current

VGS(th)

Gate-Source Threshold Voltage

1

'Dlon)

"ON" Drain Current

3

VDSlon)

Drain-Source "ON" Voltage

Breakdown Voltage

rOSlon )

Drain-Source Resistance

IYfsl
Crss

Forward Transfer Admittance

----"'_.,--_._------'"-----

UNITS

10

pA

VGS=±30V,VOS=0

10

nA

VOS = 10 V, VGS = 0

V

25

5

VGS - 10 V, VDS - 10 V
10=2mA,VGS=10V

ohms

VGS= 10V,ID=O,f= 1 kHz

Ilmho

VDS - 10 V, 10 - 2 mA, f - 1 kHz

--

1.3

Input Capacitance

Drain-Substrate Capaci.tance

5.0

td(on)

Turn-On Delay

45

VDS = 0, VGS = 0, f = 140 kHz
pF

5.0

--

Rise Time

65

tdloff)

Turn-Off Delay

60

tf

Fall Time
D.~vice

VOS= 10 V,ID = 10IlA

V

300
1000

Ciss

Note 1.

V

1

Cdlsub)
tr

10 = lOIlA, VGS = 0

mA

Reverse Transfer Capacitance
..

TEST CONDITIONS

MAX

100

must not be tested at ±125V more than once or longer than 300 ms.

1-29

VDS - 10 V, VGS = 0, f - 140 kHz
VDISUB) - 10 V, f - 140 kHz

- -----

flC,Ufll 1

·IOV

I

v,,,

ns
IOV

.'>0'

0-

.'''~

WAVEFORMS

',"1'2",
~

DunCVCU'2

~ "",:~~""~'

1

90":

Vas

SWITCH'NG C'RCUIT

1---'0,.S~

-

'I

' , t

01,

10"
-- - - - - - --.---- - - -

4S,

OVTPUTTO

s.... P.. , ..G

OSCilLOSCOPE

II

ITE4391···ITE43. 93
2N4391· 2N4393

N·ChanneIJFET
FEATURES

PIN
CONFIGURATIONS

< 30 ohms (2N4391)
10(off) < 100 pA

• rds(on)
•

TO-92

TO-18

• Switches :!:10 VAC with :!:15V Supplies
(2N4392, 2N4393)

CHIP
TOPOGRAPHY
5001

ABSOLUTE MAXIMUM RATINGS
ITA'" 25°C unless otherwise noted I
Gate-Source or Gate-Drain Voltage ............ -40V
Gate Current ............................... 50 mA
Storage Temperature Range. . . . . .. _65° C to +200° C
Operating Temperature Range ..... -55°C to +150°C
Lead Temperature (Soldering, 10 seC.1 ...... +300°C

D

TO-18

Power Dissipation
Derate above

TO-92
............. 1.8W ..... 360 mW
25°C ..... 1.7 mW/'C .. 3.0 mW/oC

ORDERING INFORMATION*

'When

TQ.i2

TO·18

ITE 4391

2N4391

2N4391/W 2N4391/D

ITE 4392

2N4392

ITE 4393

2N4393

2N4392/W 2N4392/D
2N4393/W 2N4393/D

orderin~

ELECTRICAL CHARACTERISTICS (25° C unless otherwise noted)
PARAMETER

BVGSS

Gate Reverse Current
TA-150C
Gate-Source Breakdown Voltage

10(011)

Drain Cutoff Current

VGSIf
VGSloffl

Gate-Source Forward Voltage
Gate-Source Cutoff Voltage
Saturation Drain Current
INote 11

IGSS

4391
MAX
-100
-200

4393
MIN
MAX
-100
-200
-40

100

100

100

pA
nA

-2

200
1
-5

200

-4

200
1
-10

-0.5

50

150

25

75

5

-40

ITA = 150°C

lOSS
VOSlon)

Drain Source ON Voltage

'OS (on}
'dslon)
Ciss

~tatic

Crss

td
t,
toll
tl

Drain-Source ON Resistance

Drain-Source ON Resistance

Common-Source Input Capacitance
Cammon·Source Reverse Transfer
Capacitance

Turn-ON Oelay Time
Rise Time
Turn-OFF Oelay Time
Fall Time

"

IG - 1 pA, VOS = 0
VOS= 20V

= -5 V (4393)
= -7 V (4392)
= -12 V (4391)

mA

VOS = 20 V, VGS = 0

V

60

100

60
14

100
14
3.5

3.5

12

pF
15
5
50
30

ns

VGS=O

1'0 - 3 mA (4393)
10 = 6 mA (4392)
10 = 12mA (4391)

VGS-O,lo=lmA
VC;S-O,ID=O
VDS-20V,VGS-0
VGS- -5V
VOS =0
I VGS=-7V
VGS=-12V
VOO = 10 V, VGSlon) - 0
1010n)
4391
12mA
4392
6
4393
3

INPUT PULSE
RISE TIME < 0.5 ns
FALL TIME < 0.5 ns
PULSE DUTY CYCLE 1 %

1-30

VGS
VGS
VGS

30

30
30
14

...

VGS=-20V.VOS=0

IG = 1 mA, VOS - 0
VOS=20V,10= 1 nA

0.4

NOTE:
1. Pulse test required,
pulse width = 300 J.lS, duty cycle" 3%

pA
nA
V

V

0.4

15
5
35
20

TEST CONDITIONS

UNIT

1
-3

0.4

3.5
15
5
20
15

DICE

wafer/dice refer to Appendix 8·23.
.

4392
MAX
MIN
-100
-200
-40

MIN

WAFER

1=1 kHz

1=1 MHz

VGSlofl)
-12 V
-7
-5

SAMPLING SCOPE
RISE TIME 0.4 ns
INPUT RESISTANCE 50!!

ITE4416, 2N44161 A
N·ChanneIJFET
FEATURES

PIN
CONFIGURATIONS

- Low Noise
-Low Feedback Capacitance
- Low Output Capacitance
- High Transconductance
- High Power Gain

TO-72

TO-92

D

ABSOLUTE MAXIMUM RATINGS

S

D

G

(TA = 25° C unless otherwise noted)
Gate-Source or Gate-Drain Voltage
2N4416, ITE4416 ........................ -30V
2N4416A ............................... -35V
Gate Current ............................... 10 mA
Storage Temperature Range
2N4416/2N4416A ............ -65°C to +200°C
ITE4416 .................... -55°C to+125°C
Operating Temperature Range
2N4416/2N4416A ............ -65°C to +200°C
ITE4416 .................... -55°C to +125°C
Lead Temperature (Soldering, 10 sec.) ...... +300°C
Power Dissipation ........................ 300 mW
Derate above 25° C ................ .

CHIP
TOPOGRAPHY
5000

ORDERING INFORMATION·
WAFER
TO·72
DICE

TO·92

2N4416/2N4416A ..... 1.7 mW;oC
ITE4416 ..... 3.0 mW/oC

ITE 4416

-

2N4416/W
2N4416A/W

2N4416
2N4416A

2N4416/0
2N4416A/O

·When ordering wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
MIN

PARAMETER
VGS(f)

Gate- Source Forward Voltage

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

LTA -150°C

e

2N4416/IT~4416

2N4416A
2N4416/1TE4416
2N4416A

VGS(off)

Gate-Source Cutoff Voltage

lOSS
gfs
90S
Crss
Ciss
Coss

Drain Current at Zero Gate Voltage
Common-Source Forward Transconductance
Common-Source Output Conductance
Common-Source Reverse Transfer Capacitance

Common-Source Input Capacitance
Common-Source Output Capacitance
PARAMETER

giS£,
biss
90ss
boss

100 MHz
MIN
MAX

Common-Source Input Conductance
Common-Source Input Susceptance
Common-Source Output
Conductance
Common-'Source Output
Susceptance
Transconductance

Gps
NF

Common-Source Power Gain

Noise Fi9ure

UNIT

1
-0.1
-0.1

V
nA
pA

30
35

TEST CONDITIONS
IG

1 rnA, Vos

0

VGS = -20 V, VDS = 0
IG = -1 !lA, VDS = 0

-6
-2.5
-6
5
15
4500
7500
50
0.8
4
2
400 MHz
MIN
MAX

100
2500

1000
10,000

75

100

1000

4000

Common-Source Forward

9fs

MAX

V
VDS = 15 V, ID = 1 nA
rnA
!lmho
!lmho
pF

f = 1 kHz
VDS=15V,VGS=0

pF
UNIT

pmho

f = 1 MHz
TEST CONDITIONS

VDS=15V,VGS=0

4000
18

10
4

2

1-31

dB

VDS 15 V, ID - 5 mA
VDS - 15 V, ID - 5 mA, RG - 1 KS1

II

.U~DIl

2N4856·2N4861
2N4856·2N4858 JAN,

JTX, JTXY*
N·Channel JFET
FEATURES

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-1a

5001

• Low rOS(on)

• 10 (011)<250 pA

• Switches±10V Signals with ±15V Supplies
(2N4858, 2N4861)

ABSOLUTE MAXIMUM RATINGS

'"

'"

(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage
2N4856-58 ...... . . . . . . . . . . . . . . . . . . .. -40V
2N4859'{;1 . . . . . . . . . .. . . . . . . . . . . . . . .. -30V
Gate Current ........................... 50 mA
Storage Temperature ..•........ -65°C to +200°C
Operating Temperature Range ... -55°C to +150°C
Led Temperature (Soldering. 10 sec.) .... +300°C
Power Dissipation .......................... 1.8W
Derate above 25°C .............. 10 mW/oC

1
o

II

T

012~

OOI~ X 0031

003!l

I - ~~:--I

,0026

ISOURCEI

ORDERING INFORMATION*

t.dd JAN, JTX, JTXV, to basic part number to specify these devices.

ELECTRICAL CHARACTERISTICS

'When ordering wafer/dice refer to Appendix 8·23.

(25° C unless otherwise noted)

BVGSS
IGSSR

Gate-Source
Breakdown Voltage

Gate Reverse Current

MIN
12N4856-58
2N4859-61

10(0111

Drain Cutoff Current ITA _ 150°C

Gate-Source Cutoff Voltage

Drain-Source ON -Voltage

Drain-Source ON Resistance
Common-Source Input Capacitance
Common-Source Reverse Transfer

C rss

Capacitance

td

Turn-ON Delay Time

t,

Rise Time

toft

Turn-OFF Time

NOTE:
1. Pulse test required, pulse\ividth == 100 JJ,S, duty cycle

-250
-500
250
500
-10

50

(Note 11

VOS(onl

C;ss

-4

Saturation Drain Current

'ds.lonl

MAX

-40
-30

TA - 150c C

VGS(off)
lOSS

2N4857,60

2N4856,59

PARAMETER

MIN
-40
-30

2N4858,61

MAX

-2

-250
-500
250
500
_6

20

100

MIN
-40
-30

MAX

TEST CONDITIONS

UNIT
V

IG = -1 MA, VOS = 0

pA
nA
pA
nA
V

VGS - -20 V, VOS - 0
Vr,sc-15V,Vos-0

_0.8

-250
-500
250
500
-4

8

80

rnA

VOS=15V.VGS=0

0.75
(201
25
18

0.50
(101
40
18

0.50
(51
60
18

8

8

8

6

6

10

3

4

10

25

50

10.0

V
(mAl
ohm
pF

ns

VOS= 15V. VGS=-10V
VOS=15V,ln=0.5nA

VGS=O,IO=(

I

VGS-O.IO-O

1- 1 kHz

VOS=O,VGS=-10V

1=1 MHz

464 U (2N4856,59)
VOO= 10V, RL = 953U (2N4857,60)
VGS(onl = 0
1910 U 12N4858,611
VGS(oIW-10V, 10 = 20 mA (2N4856, 91
VGSloIW-6V.10 = 10 mA (2N4857, 601
VGSloffl=-4V.IO = 5 rnA 12N4B58, 611

VDO

~

10%.

~

VDD-VOSIONI

Rl"~'

D

VIN

V

RG'

son

-=

1-32

5

"':"'

'

'
OUT

SAMPLING SCOPE

INPUT PULSE
RISE TIME 0.25 ns
FALL TIME 0.75
PULSE WIDTH 100 ns
PULSE DUTY CYCLE

RISE TIME 0.75 ns
INPUT RESISTANCE 1 M
INPUT CAPACITANCE 2.5 pf

< .10%

2N48671A·2N48691A
N·Channel JFET
FEATURES
• Low Noise Voltage
• Low Leakage
• High Gain

PIN
CONFIGURATION

ABSOLUTE MAXIMUM RATINGS
(TA = 25° C unless otherwise noted I

CHIP
TOPOGRAPHY

5005

TO-72

Gate-Source or Gate-Drain Voltage .............. -40V
Gate Current .................................. 50 mA
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55° C to +150° C
Lead Temperature (Soldering, 10 sec. I • • • • • • • • +300°C
Power Dissipation ........................... 300 mW
Derate above 25°C ................... 1.7 mW/oc
o

ORDERING INFORMATION·
TO·72

DICE

WAFER

2N4867
2N4867/W
2N4867A - 2N4867A/W
2N4868
2N4868/W
2N4868Aiw
2N4868A
2N4869
2N4869/W
2N4869A
2N4869A/W

2N4867/D
2N4867A/D
2N4868/D
2N4868AID
2N4869/D
2N4869A/D

·When ordering wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER

IGSSR
BVGSS
VGS(off)
lOSS

Gate Reverse Current

90S

Crss
Ciss

en

2N4869
2N4869A
MIN
MAX

-0.25

-0.25
-0.25

-0.25

nA

··0.25

J.lA

G

Saturation Drzin Current

(Note 1)

Transconductance (Note 1)
Common-Source Output
Conductance
Common-Source Reverse
Transfer Capacitance
Common-Source Input

Capacitance
Short Circuit Equivalent Input
Noise Voltage

I

A devices

NF

2N4868
2N4868A
MIN
MAX

TA-150C
Gate"Source Breakdown Voltage
-40
Gate-Source Cutoff Voltage
-0.7

Common-Source Forward

9fs

2N4867
2N4867A
MIN
MAX

Spot Noise Figure

-0.25
-2

-40
-1

0.4

1.2

1

700

2000

1000

·3

·-40
-1.8

.. 5

3

2.5

7.5

3000

1300

UNIT

V
mA

TEST CONDITIONS

VGS = -30 V, VOS = 0
IG
1 J.lA. VOS 0
VOS 20 V, 10 1J.1A
VOS=20V,VGS=0

4000
f = 1 kHz

,umho

1.5

4

10

5

5

5

25

25

25

20
10
10

5

20
10
10
5

20
10
10
5

1

1

1

VOS = 20 V. VGS = 0

pF

nV

-..1Hz""

f = 1 MHz

VOS = 10 V,
VGS c 0

1=1 kHz.
dB

VOS-10V.VGS-0
Rgen = 20K, (2N4867 Series)
Rgen

NOTE: 1. Pulse test duration

=

2 ms.

1-33

f = 10 Hz
I - 1KHz
1- 10 Hz

=

5K, (2N4867 A Series)

1=1 kHz

II

,

2N~100,

2N4878,2N4879,2N4880
Dielectrically Isolated Dual
MPN Transistor

II

FEATURES
•
•
•
•
•

PIN
CONFIGURATION

High Gain at Low Current
Low Output Capacitance
Good hFE Match
Tight VBE Tracking
Dielectrically Isolated Matched Pairs for
Differential Amplifiers.

TO-71
TO-78

ABSOLUTE MAXIMUM RATINGS·
(TA = 25°C unless otherwise noted)
Collector-Base or Collector-Emitter Voltage (Note 1)
2N4044, 2N4878 ............................ 60V
2N4100,2N4879 ............................ 55V
2N4045, 2N4880 ................... ,........ 45V
Collector-Collector Voltage ...................... 100V
Emitter-BaseVoltage (Note 2) ..................... 7V
Collector Current (Note 1) ..................... 10 mA
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range; ....... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
TO-71
ONE
BOTH
SIDES
SIDE

Power
Dissipation
300 mW
Derate
above 25°C

..

500 mW

CHIP
TOPOGRAPHY
4000

r

---1

~~'J

T~cgttigg=
:~~ 0030
,o.'!;!
TVP 2 PLACES

019

~

TO-78

TVP, 2 PLAces ,0030 OIA
EMITTER =2
_ 0040

TYP, '2 PLACES 0030 DIA

BASE ,,'

ONE
SIDE

BOTH
SIDES

400 mW

750 mW

.00]0

.0040 M '-0040

BASE ,"2

EMITTER ~1

.0040

ORDERING INFORMATION*

(mW/oCI .... l.7

2.9

2.3

4.3

TO·78

2N4044
2N4045
2N41 00

TO·71

I

WAFER

2N4878 I 2N4044AN
2N4879 J 2N4045AN
2N4880 I 2N4100AN

DICE

2N4044[p
2N4045/D
, 2N4100/D

'When ordering wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
hFE

DC Current Gain

I TA ~ -55°C
VBE(on)

Emitter·Base On Voltage

VCE(sat)

Collector Saturation Voltage

ICBO

Collector Cutoff Current

lEBO

ErnitterCutoff Current

Cobo

Output Capacitance

I TA = 150°C

2N4044
2N4878
MIN MAX

2N4100
·2N4879
MIN MAX

200

150

600

600

2N4045
2N4880
MIN MAX
80

225

175

100

75

50

30

UNIT

TEST CONDITIONS
IC = 10 IlA, VCE = 5V

800

IC = 1.0 rnA, VCE = 5 V
V

IC= 10llA, VCE = 5V

0.7

0.7

0.7

0.35

0.35

0.35

0.1

0.1

0.1"

nA

0.1

0.1

0.1"

0.1
0;8

0.1

0.1

IlA
nA

IC - 0, VEB - 5 V

0.8

0.8

pF

IE =0, VCB = 5 V

1-34

IC = ].0 mA, I B = 0.1 mA
IE =0, VCB=45 V, 30V"

S
.D~DIL

2N40~4%2N~045~2N4100*2N4878,2N4879,2N4880
ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER

2N4044
2N4878
MIN
MAX

2N4100
2N4879
MIN
MAX

2N4045
2N4880
MIN
MAX

UNIT

TEST CONDITIONS

Cte

Emitter Transition
Capacitance

1

1

1

pF

Ic = 0, VEB = 0.5V

CC1,C2

Collector to Collector
Capacitance

0.8

0.8

0.8

pF

Vcc = 0

IC1' C2

Collector to Collector
Leakage Current

5

5

5

pA

Vcc = ± 100V

VCEO(sust)

Collector to Emitter
Sustaining Voltage

60

55

45

V

It

Current Gain Bandwidth
Product

200

150

150

MHz

Ic = 1mA, VCE =.10V

It

Current Gain Bandwidth
Product

20

15

15

MHz

Ic = 10"A, VCE = 10V

NF

Narrow Band Noise Figure

BVCBO
BVEBO

Collector Base Breakdown
Voltage
Emitter Base Breakdown
Voltage

2

3

dB

3

Ic = 1mA, IB = 0

Ic =10"A, VCE = 5V\ I = 1kHz
RG = 10 kohms
BW=200 Hz

60

55

45

V

Ic = 10"A, IE = 0

7

7

7

V

IE = 10"A, Ic = 0

MATCHING CHARACTERISTICS (25°C unless otherwise noted)
Ic = 10"A to 1mA,
VCE = 5V

hFE1/hFE2

DC Current Gain Ratio
(Note 3)

IVBE1,VBE21

Base Emitter Voltage
Differential

3

5

5

mV

Ic = 10"A, VCE = 5V

IIB1·1~1

Base Current
Differential

5

~O

25

nA

Ic = 10"A, VCE = 5V

1L'>(VBE1,VBE2) 1/.1 T

Base Emitter
Voltage Differential
Change with
Temperature

3

5

10

,"V/oC

1L'>(lBl·I~)l/.1T

0.9

Base Current
Differential
Change with
Temperature

1

0.85

1

0.8

1

Ic = 10"A,
VCE = 5V
TA = -ssoC to +125°C

0.3

0.5

1

nA/oC

SMALL SIGNAL CHARACTERISTICS
PARAMETER
hlb
hrb
hIe
hob
hie
hre
hoe

Input Resistance
Voltage Feedback Ratio
Small Signal Current Gain
Output Conductance
Input Resistance
Voltage Feedback Ratio
Output Conductance

TYPICAL
VALUE
28
43
250
60
9.6
42
12

UNIT
ohms
x 10-3
I'mhos
k ohms
x 10 3
"mhos

TEST CONDITIONS
Ic = 1mA, VCB = 5V

Ic = 1mA, VCE = 5V

NOTES:
1. Per tranSistor.
2. The reverse base-emitter voltage must never exceed 7.0 volts and the reverse base-emitter current must never exceed 10 }lamps.

3. The lowest 01 two hFE readings Is taken as hFEt lor purposes of this ratio.

1-35

II

2N5018,2N5019
P-Channel JFET
PIN
CONFIGURATION

FEATURES
• Low Insertion Loss
• No Offset or Error Voltages Generated
by Closed Switch

CHIP
TOPOGRAPHY

TO-18

5508

1--- :;;~~------i

r

B :::~:A:7:~:

00:15

OOJ7

-om' nO-"7

{)()J}

• Analq9 Switches
• Commutators
• Choppers

oQ;o! •

NOTE SUBSTRATE IS GATE

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless othe.rwise noted)
Gate-Drain or Gate-Source Voltage .......... 30V
Gate Current .....................•...... 50 mA
Storage Temperature Range ..... -65°C to +200°C
Operating Temperature Range ... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ... +300°C
Power Dissipation .......... ; ........... 500 mW
Derate above 25° C ............... 3 mW/o C

G

s

ORDERING INFORMATION*
WAFER
2N5018/W
2N5019/W

TO·18
2N5018
2N5019

DICE
2N5018/D
2N5019/D

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (@ 25° C unless otherwise noted)
2NS018

2N5019

PARAMETER

BVGSS

Gate·Source Breakdown Voltage

IGSSR

Gate Reverse Current

10(off)

Drain Culoff Currenl

lOGO

Test Conditions

Unit
Min

Max

30

1 TA -

150'C

Min

Max

30

V

2

2

10

10

-10

-10

2

2

.A
nA

-3

-3

.A

nA

Drain Reverse CUrrent

Gale·Source Culoff Vollage

lOSS

Saturation Drain Current

VOS(on)

Orain·Source ON Voltage

0

I VGS

12 V (2N501 B)
VOS = -15 V, VGS = 7 V (2N5019)

I

VOG = -15 V, IS = 0
ITA

VGS(off)

IG = 1 .A, VOS = 0
VGS - 15 V, VOS

= 150°C

10
10

5.
5

V

VOS-

15V, 10-

I.A

mA

VOS

20 V, VGS

0

VGS

-0.5

-0.5

V

75

150

!J

75

150

45

45

10

10

6 mA (2N5018),'
0,10
10 = -3mA(2N5019)

Static Drain-Source ON
rOS(on)
rds(on)

Resistance
Drain-Source ON Resistance
Common-Source Input

Ciss

C rss

Capacitance

10= -1 mA,VGS=O

VOS= -15V,VGS=O
pF

Common-Source Reverse

1= 1 MHz
VOS = 0, VGS·=.12V(2N5018),
VGS = 7 V (2N5019)

Tr'ansfer Capacitance
Id(on)

Turn·ON Delay Time

15

15

Ir

Rise Time

20

75

IQl.ol1L
II

Turn-OIl Delay Time

15

25

Fall Time

50

100

NOTE 1: Due to symmetrical geometry
these units may be operated
with source and drain leads
interchanged.

I _1 kHz

10 = 0, VGS-O

VIN.Tr
J>1nl
51n

VOO = - 6 V, VGS(on) = 0

ns

2N5018

VGS(oll) 10(on)
12 V
6 mA

2N5019

INPUT PULSE
RISE TIME < 1 ns
7~K FALL TIME <1 ns
PULSE WIDTH 100 ns
5'" REPLETION RATE 1 MHz

UK
SAMPLING
SLOPE

1-36

7V

RL
9100

-3 mA 1.8K!J

SAMPLING SCOPE
RISE TIME 0.4 ns
INPUT RESISTANCE 10 Mil
INPUT CAPACITANCE 1.5 pF

2N5114-2N5116 JAN,
JTX P-Channel JFET

PIN
CONFIGURATION

FEATURES
• Low ON Resistance

TO-Ie

• 10(ofl) < 500 pA

• Switches directly from T2L Logic

GENERAL DESCRIPTION
Ideal for inverting switching or "Virtual Gnd" switching
into inverting input of Op. Amp. No driver is required and
±10 VAC signals can be handled using only +5V logic (T2L
or CMOS).

D

Q,C

CHIP
TOPOGRAPHY

r--- ----.. -1
:~~;~

5508

ABSOLUTE MAXIMUM RATINGS
rTA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage .......... 30V
Gate Current ............................ 50 mA
Storage Temperature Range ..... _65° C to +200° C
Operating Temperature Range ... -55° C to +150° C
Lead Temperature rSoldering, 10 sec.) ... +300°C
Power Dissipation ...................... 500 mW
Derate above 25°C ............... 3 mW/oC

:;~ ~ ::~~

f[.ll!1mru·:~·:::
0

NOTE- SUBSTRATE IS GATE

ORDERING INFORMATION*
T018t
WAFER
DICE
2N5114/D
2N5114
2N5114/W
2N5115/W
2N5115/D
2N5115
2N5116/D
2N5116/W
2N5116
tadd JAN, JTX to basic part number to specify these devices
'When ordering wafer/dice refer to Appendix 6·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER

.

BVGSS

Gate-Source Breakdown Voltage

IGSSR

Gate Reverse Current

IDloff)

Drain Cutoff Current

Vp

Gate-Source Pinch-Off Voltage

IDSS

Drain Current at Zero Gate, Voltage
(No,e 11

VGSSF

Forward Gate-So'urce Voltage

VDS(on)

Drain-Source ON Voltage

rDS(on)

Static Drain-Source ON Resistance
Small-Signal Drain-Source ON
Resistance
IJan TX only
Common-Source Input
Capacitance
IJan TX only

r ds(on)
Ciss
Crss

TA

150"C

2N5114
MIN
MAX
30
500
1.0

2N5115
MIN
MAX
30
500
1.0

2N5116
MIN
MAX
30
500
1.0

-500
-1.0

-500
-1.0

-500
-1.0

pA
I1A

I TA = 150°C

Common-Source Reverse
Transfer Capacitance

UNIT
V
pA
'I1A

5

10

3

6

1

4

V

-30

-9.0

-15

-60

-5

-25

mA

-1

-1

-1

-1.3

-0.8

-0.6

75
75
75
25
25

100
100
100
25
25

150
150
175
25
27

7

7

7

TEST CONDITIONS
IG=IJ1A,VDS=O
VGS=20V,VDS=0
2N5114 = 12 V
VDS = -15 V, VGS = 2N5115 = 7V
2N5116= 5V
VDS- -15V, ID= -1 nA
2N5114 - -18 V
=2N5115=-15V
VGS = 0, VDS
2N5116 = -15 V
IG = -1 mA, VDS = 0

V

n

2N5114 - -15 mA
= 2N5115 = - 7 mA
;1N5116=- 3mA
VGS-0,10--1 mA

VGS = 0, 10

VGS = 0, 10 = 0, f = 1 kHz
VDS = -15 V, VGS = 0, f = 1 MHz

pF

VDS

~

0, VGS

f = 1 MHz

Note 1. Pulse test; duration

= 2 ms,

1-37

2N5114-12V
=2N5115= 7V
2N5116 " &V

o

2N5114 16, JAN JTX

.

...

SWITCHING CHARACTERISTICS (25 C unless otherwise noted)
0

PARAMETER
td
tr
toff
tf

2N5114

2N5115

2N5116

MAX

MAX

MAX

6

10

10
20

6

8

15

30

12
30
19
50

Turn-ON Delay Time
Rise Time
Turn-OFF Delay Time
Fall Time

D

JANTX
2N5114
MAX

JANTX
2N55115
MAX

JAN TX
2N51111
MAX

6

10

10
20

6

8

25
35
29

....!lli!L
ns

(not JAN TX specified)

( Voo
VGG
INPUT

TEST CONDITIONS
Voo
VGG
RL
RG
IO(ON)
VIN

2N5114

2N5115

2N5116

-10V
20V

~6V

-6V

12V

43011
10011
-1SmA

91011
22011
-7mA

8V
2 KII
39011
-3mA

-12V

-7V

Js~
--, ,~"

'-, - f
'

-6V

___

~

It

10%

'"1

f--:

4.0

4.0
3.0

;.>

20

Vas"" D.W
VGS "" 0

l\

1.0
0.'
0.8
0.7
0.6
0.5
10

30

100
reSION) (ohms)

t--o

~

300

1,000

iLvos '"

>

510<

?

-;,

I

3.0

Vos = 20V

Vos "" 0

2.0

V

3

cr-

5Hl

;.

20V

VGS "" 0
(pulsed)

1

SCOPE

:

J..

4.0

1.0
0.9
0.8
0.7
0.6
0.5

SAMPLING

Vp vs g,s
10.0
9.0
8.0
7.0
6.0
50

2.0

7.SK

INPUT CAPACITANCE 1.5 pF ~

Vp vs IDSS

3.0
2.0

v'V"
1.2K

510

10.0
9.0
8.0
7.0
6.0
5.0

5.0

t-RG

r~~~;t~E~?S~~~ce 10 MHz ~

OUTPUT

Vp vs rOS (ON)

'4--

SAMPLING SCOPE-

.---- ·t r 04-

SV

10.0
'.0
8.0
7.0
6.0

>0

~'.2K

;>

O.l/ 10:

OOl~

S

002"

002~

ORDERING INFORMATIONTO·52

WAFER

DICE

2N5432
2N5433
2N5434

2N5432/W
2N5433/W
2N5434/W

2N5432/D
2N5433/D
2N5434/D

·When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
2N5432
MAX
-200
-200
-25
200
200
-4
-10

PARAMETER
IGSSR

MIN

Gate Reverse Current

BVGSS

ITA = 150"C
Gate Source Breakdown Voltage

10(off)

Drain Cutoff Current

lOSS

TA = 150"C
Gate-Source Cutoff Voltage
Saturation Drain Current
(Note 1)

rOS(on)
VOS(on)
rdsJon)

Static Drain-Source ON Resistance
Drain-Source ON Voltage
Drain-Source ON Resistance

Ciss

Common-Source Input Capacitance

VGS(off)

Crss
td
tr
toll
tl

2N5433
MAX
-200
-200
-25
200
200
-9
-3

MIN

2

Common-Source Reverse Transfer

Capacitance
Turn·ON Delay Time
Rise Time
Turn·OFF Oelay Time
Fall Time
~

UNIT
pA
nA
V
pA
nA
V
mA

5
50
5
30

7
70
7
30

10
100
10
30

15.

15

15

4
1

4
1

4
1

NOTE: 1. Pulse test reqUlredJ ,pulsewldth 300 PS, duty cycle

30

100

150

2N5434
MIN
MAX
-200
-200
-25
200
200
-4
-1

6

6

6

30

30

30

ohm
mV
ohm

TEST CONDITIONS
VGS"-15V,VOS"0
IG " -1 /lA, VOS " 0
VOS" 5V, VGS"-10V
VOS"5V,10"3nA
VOS" 15V, VGS"O
VGS" 0,10" 10 mA
I

pF

VOS"O,VGS"-10V

1=1 MHz

ns

VOO - 1.5 V,
VGS(on) "0,
VGS(off)" -12 V,
10(on) " 10 mA

3%.

VDD

V,N ~ALV:::~~~~:~::UT PULS'
RG
50.11

S

RISE TIME 025 ns
FALL TIME 075
PULSE WIDTH 200 ns
PULSE RATE 550 pps

1-42

1 kHz

VGS-O,IO -0

SAMPLING SCOPE
RISE TIME 0.4 ns
INPUT RESISTANCE 10 M
INPUT CAPACITANCE 1.5 pF

145.11 (2N5432)
RL'" 143.11 (2N5433)
140.11 j2N5434)

2N5452·2N5454
Dual Monolithic
N·Channel JFET
FEATURES
•
•
•
•

PIN
CONFIGURATION

Low Offset Voltage
Low Drift
Low Capacitance
Low Output Conductance

CHIP
TOPOGRAPHY

TO-71

GENERAL DESCRIPTION
Matched FET pairs for differential amplifiers. This family
of general purpose FETs is characterized for low and
medium frequency differential amplifier applications
requiring low drift and low offset voltage.

ABSOLUTE MAXIMUM RATINGS
(T A = 25° C unless otherwise noted)
Gate-Source or Gate Drain
Voltage (Note 1) ............................. -50V
Gate Current (Note 1) ......................... 50 mA
Storage Temperature Range .......... -65°C to +200°C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) , ....... +300°C
ONE SIDE

ORDERING INFORMATION·
TO·71

BOTH SIDES

~52

Power Dissipation ............ 250 mW
500 mW
Derate above 25°C ....... 2.9 mW/'C .. 4.3 mW/'C

2N545~

2N5454

DICE

WAFER
2N5452/W
2N5453/W
2N5454/W

2N5452/D
2N54531D
2N54541D

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)

-

PARAMETER

IGSSR
BVGSS
VGS(off)
VGS
VGS(f)
lOSS
9f,
90'
Ciss

Crss
CdQO
en
NF
I DSS 111 OSS2
IVGS1-YGS2)
IlIVGS1- VGS21

9fs1/9fs2
)90,1-90,21

d;J

2N5452
MIN
MAX

2N5453
MAX
MIN

2N5454
MIN
MAX

-100
-200

-100
-200

-100
-200

pA
nA

4.5

V

Gate Reverse Current TA ::: 150 C
Gate-Source Breakdown
Voltage
Gate-Source Cutoff ,Voltage
Gate-Source Voltage
Gate-Source Forward Voltage
Saturation Drain Current
Common-Source Forward

Transconductance
Common-Source Output
Conductance
Common-Source Input
Capacitance
Common-Source Reverse
Transfer Capacitance
Drain-Gate Capacitance
Equivalent Short Circuit
Input Noise Voltage
Common-Source SPOt
Noise Figure
Drain Saturation Current Ratio
Differential Gate-Source
Voltage
Gate-Source Voltage
Differential Change with
Temperature
Transconductance Ratio
UI erent,lal Uutput
Conductance

NOTE: 1. Per tranSistor.

-50
1
.2
0.5
1000
1000

-1

-4.5

-1

-4.L

-V.L

-4.L

-V.L

0.5
1000
1000

2
5.0
3000

0.5
1000
1000

TEST CONOITIONS
VGS=-30V.VOS=O
VDS=O.IG=-l~A

-50

-50
-4.5
2
5,0
3000

UNITS

-4.L

2
5.0
3000

mA
I1mho

3.0
1.0

3.0
1.0

3,0
1.0

4.0

4.0

4.0

1.2

1.2

1.2

1.5

1.5

1.5

20

20

20

v'HZ

0.5

0.5

0.5

dB

VOS 20 V, ID 1 nA
vDS • LV , D • bV~'"
VDS - 0, IG - 1 mA
VDS • 20 V, VGS • U
f
f

VDS=20V,VGS=0
VDS

20V,ID

200

~A

1.kHz
100 MHz

fool kHz

VDS=20V,VGS=0

0.95

0.97

1.0

0,95

1,0

0.95

5.0

10.0

15.0

0.8
1.0

2.0
2.5

1.0
0.25

0.97

1.0
0.25

1-43

0.95 ;

VDG-l0V,IS-0
nV

1.0

0.4
0.5

f'" 1 MHz

pF

VDS=20V,VGS=0
VDS 20 V, VGS
RG= 10Mrl
VDS 20 V, VGS

0

f

= 1 kHz

f

= 100 Hz

0

mV

VDS=20V,

ID=200~A

T = 25°C to _55°C
T-25 Cto+125 C

1.0
0.25

f./mhos

f

= 1 kHz

2N5457~2N545'9

N·ChanneIJFET
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)

D

PIN
CONFIGURATION

Drain-Gate Voltage. ............................. 25V
Drain-Source Voltage .... ,...................... 25V
Continuous Forward Gate Current ............. 10 mA
Storage Temperature Range .......... -65°C to +200°C
Operating Temperature flange ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
Power Dissipation ........................... 300 mW
Derate above 25°C .................. 1.7 rriW/oC

TO-92

o

5

G

CHIP TOPOGRAPHY
5010'

''''iin~i
Ii1lJm

002!>x 0025

am

0035

~ gg~6~

~
NOT[

>Cu"

SUBsrRATE

'S GA Tf

011

on;
·DICE WITH 4 MIL BONDING PADS
AVAILABLE. CONSULT FACTORY
fOR DETAILS.

ORDERING INFORMATION*
TO·92

~457
2N5458
2N5459

WAFER

~- 21':1M57/W
2N5458/W
2N5459/W

DICE
2N54571D
2N54581D
2N54591D

·When ordering wafer/dice refer to Appendix 8-2.3.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
BVGSS

Gate·Source Breakdown Voltage

IGSS

Gate Reverse Current

VGS(off)

Gate·Source Cutoff Voltage

VGS

Gate·Source Voltage

lOSS

Zero·Gate·Voltage Orain
Current

IVlsl

Forward Transler Admittance

IVosl
Ciss
Crss

Output Admittance
I nput Capacitance
Reverse Transler Capacitance

NF

Noise Figure

Pulse test reqUired. PW .;; 630 ms, duty cycle';; 10%

MIN

TYP

c25

-60

.05
2N5457
2N5458
2N5459
2N5457
2N5458
2N5459
2N5457
2N5458
2N5459
2N5457
2N5458
2N5459

-0.5
-1.0
-2.0

1.0
2.0
4.0
1000
1500
2000

2.5
3.5
4.5
3.0
6,0
9.0
3000
4000
4500
10
4.5
1.5

MAX

UNITS
V

-1.0

TEST CONDITIONS
IG ~ -10jJA, VOS = 0
VGS--15V,VOS-O
VGS = -15 V,VOS- 0, TA - 100 C

1- 200

nA

-6.0
-7.0
-8.0

V

VOS = 15 V, 10 = 10.nA

V

VOS = 15 V, 10= 200jJA
VOS = 15 V, 10 = 400jJA

mA

VOS = 15 V, VGS = 0,

VOS-15V,IO~100jJA

5.0
9.0
16
5000
5500
6000
50
7.0
3.0

jJmho

VOS = 15 V, VGS= 0, 1=1 kHz

!1mho
pF
pF

VOS - 15 V, VGS - 0, 1-1 kHz
VOS-15V,VGS-0,i-l MHz
VOS-15V, VGS-O,I-l MHz

3,0

'dB

VOS = 15 V,VGS = 0, RG = 1 MHz
BW=l.Hz;f=l KHz

2N5460-2N5465
P-Channel JFET
PIN
CONFIGURATION
TO-92

D

ABSOLUTE MAXIMUM RATINGS
(TA = 25° C unless otherwise noted)
Drain-Gate or Source-Gate Voltage
2N5460 - 2N5462 .......................................... 40V
2N5463 - 2N5465 .......................................... 60V
Gate Current ................................................ 10 mA
Storage Temperature Range ......................... -65°C to +200°C
Operating Temperature Range ....................... -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ....................... +300°C
Power Dissipation .......................................... 310 mW
Derate above 25°C ................................. 2.8 mW/oC

S

D

G

CHIP
TOPOGRAPHY

II~·;}'·=:·
1 r--- 0170

0025

:~~:~

---I

NOTE'

0025

~~~!~~A TE

ORDERING INFORMATlON*
TO-92
2N5460
2N5461
2N5462
2N5463
2N5464
2N5465

WAFER

DICE

2N54601W
2N54611W
2N54621W
2N54631W
2N54641W
2N5465/W

2N5460/D
2N5461/D
2N5462/0
2N5463/0
2N5464/0
2N5465/0

ELECTRICAL CHARACTERISTICS (250C unless otherwise noted) ·When ordering wafer/dice refer to Appendix
MIN

PARAMETER
BVGSS

Gate·Source Breakdown Voltage

VGSloffi

Gate-Source Cutoff Voltage

'GSSR

lOSS

VGS

9fs

90S
Ciss
Crss
NF
en

2N5460. 2N5461, 2N5462
2N5463, 2N5464, 2N5465
2N5460, 2N5463
2N5461, 2N5464

2N5462,
2N5460,
Gate Reverse Currenr
2N5463.,
2N5460,
TA'100°C 2N5463,
2N5460,
Zero-Gate Voltage Drain Current 2N5461,
2N5462,
2N5460,
2N5461,
Gate-Source Voltage
2N5462,
2N5460,
2N5461,
Forward Transadmittance
2N5462,
Output Admittance
Input Capacitance
Reverse Transfer Capacitance

I

2N5465
2N5461,2N5462
2N5464, 2N5465
2N5461, 2N5462
2N5464, 2N5465
2N5463
2N5464
2N5465
2N5463
2N5464
2N5465
2N5463
2N5464
2N5465

,

TYP

40
60
0.75
1.0
1.8

-1.0
-2,0
-4,0
0.5
0.8
1.5
1000
1500
2000
5.0
1.0
1.0

Common·Source Noise Figure
Equivalent Short-Circuit Input
Noise Voltage

60

1-45

MAX

6.0
7.5
9.0
5.0
5.0
1.0
1.0
-5.0
-9,0
-16
4.0
4.5
6.0
4000
5000
6000
75
7
2,0
2.5
115

UNITS

TEST CONDITIONS

V

IG" 10 pAde, VDS" 0

V

VOS

nA

=

15 Vdc, 10::: 1.0pAdc

Vos ·0

"A

VG<·20V
VGS - 30V
VGS'-WV
VGS - 30'

rnA
Vos

-15V

V

VGS '0
ID -0,1 rnA
In - -0.2 rnA
'D • -0.4 rnA

.umho
,umho

pF
pF
d8
nVI

v'H2

8·23.

VDS' -15V
VGS' OV

f"I,OkHz

,
f"100Hz
BW ·1,0 Hz
RG" 1.0 Mn

2N5484· 2N5486
N·Channel ·JPET
PIN
CONFIGURATION

FEATURES

II

• Up to 400 MHz Operation
• Economy Packaging
• erss < 1.0 pF

TO'92

P
t-

ABSOLUTE MAXIMUM RATINGS
(T A = 25 0 C unless otherwise specified)

D

Drain-Gate Voltage ......•....................... 25V
Source Gate Voltage ............................ , 25V
Drain Current ................................. 30 mA
Forward Gate Current ......................... 10 mA
Storage Temperature Range .......... -65°C to +200°C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering. 10 sec.) ... , .... +300°C
Power Dissipation .......•................... 310 mW
Derate above 25°C ................•. 2.8 mW/oC

S

G

CHIP
TOPOGRAPHY
5000

~F\Jll;l\

T. \
• ---M'.!Q
,:. ~_J...
,,1>
orr
• 0"'1

':'.1..__

~ -~

._.

r

Is,
.

",

mrj '0" 'U","''''
.~(jAH

co.

m" .

I

ORDERING INFORMATION·
TO·92
2N5484
2N5485
2N5486

WAFER
2N5484/W
2N5485/W
2N5486/W

DICE
2N5484/D
2N5485/D
2N5486/D

.

When ordenng wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS
PARAMETER
IGSSA

Gate Reverse Current TA _ 1000C

BVGSS
VGSloll1
lOSS

Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage
Saturation Drain urrent

91s
90S
Relylsl
Re(yos)
Re(Yis)
Ciss
C rss"
Coss

NF

Common-Source Forward

Transconductance

2N5485
MIN
MAX

1.0
-200

1.0
200

-25
-0.3
1.0
3000

-3.0
5.0

-25
-0.5
4.0

4.0
10

6000

3500

7000

2N54~6

MIN

1.0
200
-25
2.0
O.U

4000

60

50

Conductance

oA
V
mA

TEST CONDITIONS
VGS = -20 V, VDS

0

IG--1MA,VOS-0
VOS 15V,IO 10nA
VOS 1:::1 v , VGS lJII'IIote
=0

8000
75
f - 100 MHz

3000

3500

f -

,umhos

75
100

100

1000

1000

5.0

5.0

5.0

1.0

1.0

1.0

2.0

2.0

2.0

2.5
3.0

2.~

2.5

VOS= 15V. VGS=O

100

Noise Figure

4.0
Common-Source Power Gain

6.0
20

UNITS

2500

16
Go'

MAX

f'" 1 kHz

Common-Source Output
Common-Source Forward
TransC"onductance
Common-Source Output
Conductance;
Common-Source Input
Conductance
Common-Source Input
Capacitance
Common-Source Reverse
Transfer Capacitance
Common-Source Output
Capacitance

(25'C unless otherwise noted)

2N5484
MIN
MAX

4.0

25
18
10

30
20

18
10

NOTE: Pulse test reqUired. Pulse Width - 3001'5, duty cycle oS 3%,

1-4€l

30
20

of

400 MHz
iOO MHz
400 MHz
100 MHz

400 MHz

f '" 1 MHz

VOS" 15 V, VGS - 0, RG 1 Mrl
VOS 15V,IO 1 rnA, RG 1 krl
VOS 15V,IO 4 mA"RG 1 krl
dB

I
I
I
I

Vos-15V,ID-lmA
VOS

15 V,IO

4 mA

I

1 kHz

f= 100 MHz

'f - 400 MHz

I

100 MHz

f '" 400 MHz

2N5515·2N5524
Monolithic Dual
N·Channel

JFET
FEATURES
•
•
•
•

PIN
CONFIGURATION

Tight Temperature Tracking
Tight Matching
High Common Mode Rejection
Low Noise

D

TO-71

ABSOLUTE MAXIMUM RATINGS

(T A = 25° C unless otherwise specified)
Gate-Source or Gate-Drain Voltage .............. -40V
G'ate Current (Note 1) ......................... 50 mA
Storage Temperature Range .......... -65°C to +200°C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
ONE SIDE

CHIP
TOPOGRAPHY

BOTH SIDES

Power Dissipation .......... 250 mW ... 500 mW
Derate above 25°C .... 3.8 mW/oC ... 7.7 mW/oC

12N5515-191
6037

12NSS20-241
6019
0,

);;=:

·.023

-:-IG'ljIo-'T G'~r"

S'I!
!
0,

.039

.O~'

~

s',

I

~I

I

.025

~

0,

I

J.

.----j

!II s,~:·.::~
.1,
~ G2

~-L
t

52

TVP, 2 PLACES

.0031

02

:~~. ::~:

TVP. 2 PLACES

ALL BOND PADS ARE 4)( 4 MIL.

ORDERING INFORMATION*
TO·72

WAFER

DICE

2N5515
2N5516
2N5517
2N5518
2N5519
2N5520
2N5521
2N5522
2N5523
2N5524

2N5515/W
2N5516/W
2N5517/W
2N5518/W
2N5519/W

2N55151D
2N5516/D
2N55171D
2N5518/D
2N5519/D

'When ordering wafer/dine refer to Appendix 6·23.

NOTE: Per transistor.

1-47

.0031

.0027)C .0027

TVP.2PLACES

2N5515 thru 2N5524
El..ECTRICALCHARACTERISTICS (25°C unless otherwise noted)
PARAMETER

en

Gate Reverse Current
ITA -150°C
Gate-Source Breakdown Voltage
Gate-Source Pinch-Off Voltage
Drain Current at Zero Gate Voltage (Note 1)
Common-Source Forward Transconductance
(Note 1)
Common-Source Output Conductance
Common-Source Reverse Transfer
Capacitance
Common-Source I nput Capacitance
12N5515-19
.
12N5520-24
Equivalent Input NOise Voltage 12N5515-24

IG

Gate Current

VGS

Gate Source Voltage
Common-Source Forward Transconductance
(Note 1)
Common-Source Output Conductance

IGS.SR
BVGSS
Vp
IDSS

II

MIN

9fs
goss
Crss
Ciss

9fs
goss

PARAMETER
Drain CUrrent Ratio at

'DSSI
IOSS2

4
7.5

1000

4000

TEST CONDITIONS
VGS= -30 V, VDS= 0

IG - -1 JJ.A, VOS - 0

V

vDS

LU

v, ID

I nJ!i

mA
f = 1 kHz

I1mho
VDS = 20 V, VGS = 0

10
5

f = 1 MHz

pF

-0.2

25
30
15
10
100
-100
-3.8

500

1000

I1mho

1

I1mho

f = 10 Hz

nV/YHz

f - 1 kHz
pA
nA
V

VDG = 20 V, ID = 2OOl1A
f = 1 kHz

(25°C unless otherwise noted)

2N5515.20
MAX
MIN

2N5516.21
MAX
MIN

0.95

0.95

Differential Gate Current

1

10

(+125"C)

9fs1

Transconductance Ratio

9f52

(Note 1)

1905s1 - 905s21

Differential Output
Conductance

)VGSI -VGS21
t.IVGSI - VGS21
t.T

1

2N5517.22
MIN
MAX

2N5518,23
MIN
MAX

2N5519,24
MIN
MAX

0.95

0.95

0.90

0.97

1

1

10

10
0.97

1

0.95

1

UNIT

1

TEST CONDITIONS
VOS"20V,VGS"0

Differentia'i Gate·Source
Voltage

Gate-Source Voltage Differentia I Drift (TA = _55°C to
+125°C)
Common Mode Rejection

Ratio (Note 2)

= 20 L0910,,-VDD/t.IVGSI

1

10
0.95

1

10
0.90

nA

VOG" 20 V. 10" 200 ~A
VOG - 20 V. '0 - 200 ~A

1

f'" 1 KHz

0.1

0.1

0.1

0.1

0.1

J.lmho

VOG 20 V. 10 - 200 ~A
f =: 1 KHz

5

5

10

15

15

mV

VOG" 20 V.IO" 200 ~A

5

10

20

40

80

~vtc

VOG" 20 V. 10" 200~A

100

100

90

1. Pulse duration of 28 ms used during test.
2. CMRR

UNITS
pA
nA

Zero Gate Voltage (Note 1)

IIGI -IG21

CMRR

-40
0.7
0.5

ITA = 125°C

MATCHING CHARACTERISTICS

MAX
-250
-250

- VGS2', (t.VDD

= 10V)

1-48

dB

VOO" 10 to 20 V. 10" 200~A

2N5638·2N5640
N·Channel JFET
PIN
CONFIGURATION

FEATURES
• Economy Packaging
• Fast Switching
• Low Drain-Source 'ON' Resistance

CHIP
TOPOGRAPHY

TO-92

5001

00'.

cii1Ji.

fULL IU,DIUS
(DIIIIAINI

I

ABSOLUTE MAXIMUM RATINGS
(TA =

25°C unless otherwise specified)

Drain-Source Voltage ............................ 30V
Drain-Gate Voltage .............................. 30V
Source-Gate Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30V
Forward Gate Current ......................... 10 mA
Storage Temperature Range .......... -65°C to +200°C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering. 10 sec.) ........ +300°C
Power Dissipation ........................... 310 mW
Derate above 25°C .................. 2.8 mW;oC

S

1- =-1

Q

ISOURCE)

'"~

ORDERING INFORMATION*
WAFER
2N5638/W
2N5639/W
2N5640/W

TO·92
2N5638
2N5639
2N5640

DICE
2N5638/D
2N5638/D
2N5640/D

'When ordering wafer/dice refer to Appendix 9·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
2N5638
MAX

PARAMETER

BVGSS

Gate Reverse Breakdown Voltage

IGSSR

Gate Reverse Current

10IofO

Drain Cutoff Current

lOSS

Saturation Drain Current

MIN
-30

TA

100

-30
1.0
-1.0
1.0
1.0

TA - 1000 e
0

2N5639
MIN
MAX

e
50

2N5640
MAX

MIN

-30
1.0
-1.0

-1.0

1.0
1.0

1.0
1.0

1.0

5.0

25

V
nA
"A
nA
"A
mA

VOS(on)

Drain-Source ON Voltage

0.5

0.5

0.5

V

rDS(on)
rds on

Static Drain-Source ON Resistance
Drain-Source ON Resistance

30
30

60
60

100
100

n

Ciss

Common-Source Input
Capacitance

10

10

10

4.0

4.0

4.0

4.0
5.0

6.0
B.O
10
20

B.O
10
15
30

Crss

Common-Source Reverse Transfp.r
Capacitance

td on
t

Turn-On Delay Time

trl

Turn-OFF Delay Time
Fall Time

tf

Rise Time

pF

5.0
10

TEST CONDITIONS

UNIT
IG VGS

0

VOS
VGS
VOS
VGs
10 =
10 _.

- 15 V, VGS- 12 V 12N563BI
c -8 V 12N56391, VGS" -6 V (2N56401
- 20 V, VGS - a (Note 1)
- 0, 10 . 12 mA (2N563BI,
6 mA (2N5639). 10 3 mA (2N5640)
1 mAo VGS - 0

-15 V, VOS

c

0

-;0

VGS'" 0, 10 -

a

f -" 1 kHz

f '" 1 MHz

VGS" -12V,VOS""'O

VOO
n;

lO}1A, VOS - 0

10 V

VGS(on) = 0

VGS(offl c -10 V
RG = 50 n

JOlon)
ID/on) '"
ID(on) '"

12 mA (2N56381
6 mA (2N56391
3 mA 12N56401

NOTE: 1. Pulse test; PW .. 300!,s, duty cycle .. 3.0%.

VDD
= 10 VDC

0.1 jJF

~

TO 50 OHM SCOPE 8

1.0K5t

+---+-----------0 TO 50 OHM SCOPE A
SCOPE
TEKTRONIX 561A
OR EQUIVALENT

1-49

.U~UIL

2N5902·2N5909
Monolithic Dual
N·Channel JFET

FEATURES

II

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-99

6015

• Tight Tracking
• Good Matching

GATES ARE
ISOLATED FROM
SUBSTRATE

ABSOLUTE MAXIMUM RATINGS
(T A = 25° C unless otherwise specified)
Gate-Drain or Gate-Source
Voltage (Note 1) ............................. -40V
Gate Current (Note 1) ..........................10 mA
StorageTemperature Range .......... -65°C to +200°C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
ONE SIDE

Power Dissipation ............. 367 mW
Derate above 25°C ....... 3 mW/'C

ORDERING INFORMATION*

BOTH SIDES
500 mW

4 mW/'C

WAFER

TO·99

DICE

TO·99

WAFER

DICE

2N5908 2N5908/W 2N5908/D

2N5902 2N5902/W 2N5902/D
2N5903
_
. 2N5903/W 2N5903/D

2N5907 2N5907/W 2N5907/D

2N5904 2N5004/W
._- ..2N5904/D
_---,--,.
2N5905 2N5905/W 2N5905/D

2N5908 2N5908/W 2N5908/D
2N5909 2N5905/W 2N5909/D

'When ordering wafer/dice refer to Appendix B-23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
IGSSR

Gate Reverse Current

SVGSS
VGSloffl
VGS

Gate-Source Breakdown Voltage

Gate-Source Cutoff Voltage
Gate Source Voltage

IG

Gate Operating Current

lOSS

Saturation Drain Current
Common-Source Forward

9f,
90,
Ciss

TA - 125"C

TA - 125 C

Transconductance
Common-Source Output Conductance

en
NF

Spot Noise Figure

9f,
90S

70

250

PARAMETER

ilGl- IG21

-IOSS1
-IOSS2
9fsl
91s2
IVGS1-VGS21

50

2N5906·9
MIN
MAX
-2
-5
-40
-4.5
-0.6
-4
-1
-1
30
500
70

5
3

1.5

1.5

150

1

0.2

0.1
1

3
2N5903·7
MAX
MIN

VGS = -20 V. VOS = 0
IG = -1 p.A, VOS = 0
VOS= 10V, 10= 1 nA

V
pA
nA
p.A

VOG =10 V, 10 =30p.A

p.mho

VOS = 10 V, VGS = 0

f = 1 kHz
f = 1 MHz

pF

Jlmho

VOG=10V.10=30.A
f = 1 kHz

p.V

y;Hz"""

VDS = 10 V, VGS =0

dB
2NS904-8
MIN
MAX

2.0
0.2

2.0
0.2

Differential"Gate CUrrent

TEST CONDITIONS

pA
nA

150

SO

1

2N5902·6
MIN MAX

UNIT

250

5
3

Common-Source Input Capacitance

Common-Source Reverse Transfer
Capacitance
Common-Source Forward
Transconductance
Common-Source Output Conductance
Equivalent Short Circuit Input
Noise Voltage

Crss

2N5902·5
MAX
MIN
-5
-10
-40
. -4.5
-0.6
-4
-3
-3
30
500

2N590S-9
MIN MAX

2.0
0.2

Saturation Drain Current Ratio

0.95

1

0.95

1

0.95

Transconductance Ratio

0.97

1

0.97

1

0.95

2.0
0.2

1

0.95

1

0.95

UNIT
nA

1

15

Differential Gate-Source Voltage

5

5

AIVsSl, VGS21
AT

Gate-Source Voltage. Differential
Drift (Measured ,at end points
TA and TSI

.5

10

20

40

5

10

20

40

190,1-90,21

Differential Output Conductance

0.2

0.2

0.2

0.2

1 = 1 kHz

mV

p.vi'c

NOTE 1: Per transistor.

1-50

TEST CONDITIONS
VOG = 10 V,
2N5902-5
10 = 30 p.A,
2N5906·9
TA= 125°C
VOS= 10V, VGS=O

1

10

f-l00Hz
RG = 10 Mn

p.mho

VOG=10V, TA 25 C
TS = 12S'C
IDe 30p.A
TA -55 C
TS = 2SoC
f = 1 kHz

2N5911,2N5912
IT5911, IT5912
Monolithic Dual
N·Channel JFET

FEATURES
• Tight Tracking
• Low Insertion Loss
• Good Matching

CHIP

PIN
CONFIGURATION
TO-99

TO-71

L

r

'mo

j

0160

-,

6022

~1-- -~-Gl gg;~. gg~;

ABSOLUTE MAXIMUM RATINGS

I
0190
0130

(TA = 25°C unless otherwise noted)
Gate-Drain or Gate Source Voltage ........•..... -25V
Gate Current .................................. 50 mA
Storage Temperature Range .......•.. -65°C to +200°C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec. I ....•... +300°C
TO-71

TOPOGRAPHY

~l

2
G,

_1__ _

IJYP lPLACESI
OOJ1 0037
- U 1 0011 ~ 0021
ITVP2PlACESl

Sl

~~~. ~;~
(TVP, 2 PLACfSf

TO-99

ONE SIDE BOTH SIDES

Power Dissipation

300 mW 500 mW
1.7
2.9
Derate above 25°C mW/OC mW/'C

ONE SIDE BOTH SIDES

0,

D,

S,

300 mW 500 mW
3.0
4.0
mW/'C mW/OC

ORDERING INFORMATION·

'When ordering wafer/dice refer to Appendix 8-23.

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted)
MIN

PARAMETER
Gate Reverse Current

IGSSR

BVGSS
VGS(off)
VGS

I TA = 150'C
Gate Reverse Breakdown Voltage
Gate-Source Cutoff Voltage
Gate-Source Voltage

IG

Gate Operating Current

I

TA = 125°C
Saturation Drain Clirrent (Pulsewidth 300/1s,
duty cycle';; 3%)
Common-Source Forward Transconductance
Common-Source Forward Transconductance
Common-Source Output Conductance
Common-Source Output Conductance
Common-Source- I nput Capacitance
Common-Source Reverse Transfer Capacitance

IDSS
9fs
9fs
gas
goss
Ciss
Crss

Ci~cuit

en

Equivalent Short

NF

Spot Noise Figure

~IVGS1-VGS21
~T

9fsl
-9fs2

UNIT

-100
-250

pA
nA

-5
-4
-100
-100

V
pA
nA

VOG=10V,ID=5mA

40

mA

VOS=10V,VGS=OV

7
5000
5000

10,000
10,000
100
150
5
1.2

Input Noise Voltage

20
1

pF

1

10

15

Gate-Source Voltage Differential
Drift (Measured at .end points,
TAandTB)

20

40

Transconductance Ratio

40

0.95

1

1-51

0.95

1

VOG=10V,ID=5mA

f = 1 MHz
f=10kHz
f=10kHz
RG = 100Kn

TEST CONDITIONS
125°C
VOG=10V,ID=5mA
\IDS - 10V, VGS- 0
(Pulsewidth 300 /1S, duty cycle';; 3%)

mV
/1V 1°C

20

f - 1 kHz
f=100MHz
f = 1 kHz
f=100MHz

dB

0.95

Differential Gate-Source Voltage

IG = -l/1A, VOS = 0
VOS=10V,lo=lnA

YRZ

Saturation Drain Current Ratio

0.95

VGS= -15 V, VOS= 0

nV

Differential Gate Current

1

TEST CONDITIONS

/1 mho

IT,2N5911 IT,2N5912
UNIT
MIN MAX MIN MAX
20
20
nA

PARAMETER
IIG1-IG21
IDSSl
I DSS2
IVGS1-V GS21

-25
-1
-0.3

MAX

VOG=10V,ID=5mA

TA = 25°C
TB = 125°C
TA = _55°C
TB = 25°C
f = 1 kHz

o

2N6483.2N6485
Monolithic Low Noise Dual
N·ChanneIJFET
FEATURES

II

•
•
•
•

Ultra Low Noise
HighCMRR
Low Offset
Tight Tracking

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

6019

TO-71
D,

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) ...... -50V
Gate-Gate Voltage .............................. ±50V
Gate Current (Note 1) ......................... 50 mA
Storage Temperature Range .......... -65°C to +200°C
Operating Temperature Range ........ -55° C to +150° C
Lead Temperature (Soldering, 10 sec. I ........ +300°C
ONE SIDE

BOTH SIDES
500 mW
7.7 mW(OC

Power Dissipation ......... 250 mW
Derate above 25°C.: 3.8 mw/oC

ORDERING INFORMATION·
TO·71

WAFER

DICE

2N6483
2N6484
2N6485

2N6483/W
2N6484/W
2N6485/W

2N6483/D
2N6484/D
2N6485/D

·When ordering wafer/dicerefer to Appendix B·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER

SYMBOL

MIN,

MAX

pA

200

"A

'GSS
BV GSS

Gate Source Breakdown Voltage

50

Vp

Gale·Source Pinch Off Voltage

07

4,0

'OSS

Drain Current at Zero Gate Voltage (Note 2)

05

7,5

1000

4000

I

TA ~ 150°C

UNIT

200

Gate Reverse Current

TEST CONOITIONS
v GS

,30 v, VOS

0

0,

lpA,VOS=O

IG =

V

9t,

Common-Source Forward Transconductance

9055

Common-Source Output Conductance

10

Ciss

Common-Source I nput Capacitance

20

Cr55

Common-Source Reverse Transfer Capacitance

3.5

20 V, ID '" 1 nA

VOS
mA

(Note 2)

limho

VOS

20 V, V GS 0 0

0

VOS=20V,VGS=O,f= 1 KHz

pF

VOS'" 20V. VGS" 0, f = 1 MHz

V GO - 20V,I 0 0200 pA,

'G

Gate Current

I

100

pA

100

nA

0.2

3.8

V

500

1500

TA " 150"C

V GS

Gate-Source Voltage

9fs

Common-Source Forward Transconductance

20V,1 0 ' 200pA

VOG

0

VOG

0

20V, '0 ~ 2do pA, t 0 1 KHz

VOG

0

20V, 'Oo200pA

/-ImtlO

90,

en

Common-Source Output Conductance

Equivalent I nput Noise Voltage

NOTES: 1. Per transistor.
2. Pulse test required; pulse width =.2 ms.

I
10

~

1-52

nV/yFfi

VDS'" 20 V. 10:= 200pA. f - 10 Hz
VOS 0 20 V., I 0 ~ 200 pA, I ' 1 KHz

IID~DlL

2N6483 - 2N6485
MATCHING CHARACTERISTICS (@25°C unless otherwise noted)
PARAMETER

SYMBOL
IOSSl

Drain Current Ratio at Zero

IOSS2

Gate Voltage

2N6483
MIN.
MAX.

2N6484
MIN.
MAX.

0.95

0.95

'Differential Gate Current

IIGl -IG21

1

2N6485

1

MIN.

MAX.

0.95

1

10

10

UNIT

CONDITIONS
VOS=20V,VGS=0

INote 21

10

nA

VOG

= 20V, 10 = 200MA

TA = +125°C
gfsl

0.97

Transconductance Ratio

~

ggs2

Differential Output

I gosl - 90s2 I

Conductance

1

f = 1 KHz INote 21
V, 10

= 200 MA,

V, 10

= 200MA

VOG =20V.10

= 200MA

VOG
,pmho

5

10

15

mV

5

10

25

MVi'C

NOTES:

i

Common Mode Rejection
Ratio

100

100

= 20

VOG

= _55°C to +125°C

V OO =10t020V,

dB

90

= 20

f = 1 KHz

TA

CMRR

200 MA,

VOG - 20 V. 10

1

0.1

Gate-Source Voltage Differen
tial Drift

6T

0.95

0.1

Voltage

61 VGSl - VGS21

1

0.1

Differential Gate-Source

I V GS1 - V GS2 1

0.97

10 = 200 MA INote 31

1. These ratings are limiting values above which the serviceability of any individual semiconductor device may be impaired.
2. Pulse duration of 2 ms used during test.
3. CMRR = 20Log 106V DDi61V GSl - V GS21, 16V DO = 10 VI, not included in JEDEC registration

TYPICAL OPERATING CHARACTERISTICS
en vs. FREQUENCY

en vs. FREQUENCY
100

100

-t

!

I-c.t-

'I
~lLJ&2~
I

I

,

I
f--

II

10

.

~ ~VOS'20V .1.
:::::::
)---

Ij

10 = 2OOp.A

II

tl-ill
._-

,.

100

r-

."
10

I

10.

f--

~

-++++--+-+

pI0'2~"At

S==::

1: '0' 400" A- r-

i

~

1

10

WOK

~oo

,.

10.

TYPICAL CAPACITANCE vs. VOS

GATE CURRENT vs. VOG

"14

60

J!

~

40

I

20

to
8.0
6.0
4.0

lit

~.-

,

f--7

'GSS

./

f, H.

;;:
J!

13
12

o

c-

uE 10

f-'

J~.

-1-I

'0 - 200

J" c--

./

L

~200""
10

c;~

.......

11

./

15

eras

I-f-

2.0 r-do.400"" . / ' "
I .•

lOOK

frequency (Hz)

80

"

-

-

frequency (Hz)

100

r-

i 10"00} ,--

t'-' 1=:::0
r'-

. I

I

vos~_TV

r--

I

~
,

1
10

i
'S

-"

I

20

VOG

25

00

30

IVI

2

4 8

8 10 12 14 16 18 20 22 24 26 28 30
VoS(V)

1-53

r-

II

~UlL

.
IMF648S
Monolithic Low Noise Dual
N·ChanneIJFET
GENERAL DESCRIPTION

FEATURES
• Ultra Low Noise
• High CMRR
• Low Offset
• Tight Tracking

This N-Channel Junction FET is characterized for ultra
low noise applications requiring tightly controlled and specified noise parameters at 10 Hz and 1000 Hz, Tight matching specifications make this device ideal as the input
stage for low frequency differential instrumentation am·
plifiers.

I

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-71

6019

'ABSOLUTE MAXIMUM RATINGS
(TA = .25°C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) ...... -50V
Gate-Gate Voltage .............................. ±50V
Gate Current (Note 1) ...........•............. 50 mA
Storage Temperature Range .......... -65°C to +200°C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering. 10 sec.) ..••.... +300°C
ONE SIDE

BOTH SIDES

Power Dissipation ......... 250 mW
500 mW
Derate above 25° C .... 3.B mW/O C . . . .. 7.7 mW/o C

ORDERING INFORMATION·

'When ordering wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER

SYMBOL

MIN.

MAX.

UNIT

·200

pA

-200

nA

IGSS

Gate Reverse Current

BVGSS

Gate-Source Breakdown Voltage

-50

Vp

Gate-Source Pinch·Off Voltage

-OJ

-4.0

lOSS

Drain Current at Zero Gate Voltege
(Note 2)

0.5

7.5

mA

1000

4000

j..Imho

9fs

I TA

= 150°C

Common-8ource Forward Transconductance
(Note 2)

V

9055

Common-Source Output Conductance

10

Ciss

Common-Source I nput Capacitance

20

·C'55

Common-Source Reverse Transfer Capacitance

3.5

IG"

Gate Current

,
ITA

= 150°C

V GS

Gate-Source Voltage

9ts

Common-Source F Of ward Transconductance

90S

Common·Source Output

en

Equivalent Input Noise Voltage

pA
nA

0.2

·3.8

V

1500

J.l.mho

1

NOT ES :

1. Per transistor.

2. Pulse test required; pulse width = 2 ms.

1-54

V OS "20V,V GS "O,t" 1 KHz

VOS" 20V,

VGS~O,

t" 1 MHz

V DS " 20 V, VGS" 0, t" 1 MHz

·100

15

VOS"20V,VGS"0

VDS" 20 V, VGS" O,t" 1 KHz
pF

-100

10

IG " -1 ~A. V DS ' 0
VDS" 20V.I D " 1 ~A

500

Conducta_~ce

TEST CONDITIONS
VGS" -30 V, VOS" 0,

VGD." 20 V, ID" 200MA,

V DG

~

20 V, I D "200MA

VDG" 20V, ID" 200MA. t" 1 KHl
V DG "20 V. ID "200MA

nV/,jRl

VDS " 20 V, ID" 200~A. f" 10 Hz
V DS -20V. ID' 200MA, tel KHl

IMF6485
MATCHING CHARACTERISTICS

(@

25° C unless otherwise noted)

PARAMETER

SYMBOL

Drain Current Ratio at Zero Gate Voltage

I DSS1

MIN.

MAX.

0.95

1

UNIT

CONDITIONS

V DS = 20 V, V GS = 0 (Note 21

I DSS2

I

IIG1 - IG2

Differential Gate Current

10

V DG = 20 V, ID = 200 !,A

nA

T A = +125' C

Transconductance Ratio

9ts1

0.95

V DG = 20 V, ID = 200 !,A,

1

f

99S 2

I

90s1 - 90s2

I

Differential Output Conductance

0.1

V GS1 - V Gs2 1

L1IVGS1 - V Gs2 1

Differential Gate-Source Voltage

25

Gate-Source Voltage Differential Drift

40

,Nt C V CG = 20 V, ID = 200 !,A
T A = _55°C to +125° C

90

Common Mode Rejection Ratio

= 1 KHz

V DG = 20 V, ID = 200 !,A

mV

LIT
CMRR

V DG = 20 V, ID = 200!,A,

,umho

f

I

= 1 KHz (Note 21

V DD = 10 to 20 V,

dB

I D = 200 pA (Note 31

NOTES: 1. These ratings are limiting values above which the serviceability of any individual semiconductor device may be Impaired.

2. Pulse duration of 2 ms used during test.
3. CMRR

= 20Lo910LlVDD!LlIVGS1

- V GS2 1, (LlV DD

= 10 VI

TYPicAL OPERATING CHARACTERISTICS
en vs. FREQUENCY

en vs. FREQUENCY
100

100

II
10 - 2OOp.A

~

~

:s,.

II
10

10

20

v

ID = 200)..1

:;:::~

--

r- ~

I

1

3F:::

100

10K

lK

lOOK

100

10

15
14

60

13

-- It

10
8.0
6.0
4.0

2.0
1.0

~

II

20

7

IG~

~"400"A~

E
u

I--"

10

lOOK

c;:.. r-

I,

12
11
10

0;'
'0 = 2 !>O, A

r-

/'

15

Cru

C-

%-OOPA

o

10K

TYPICAL CAPACITANCE vs. VDS

GATE CURRENT vs. VDG
80

40

lK

frequency (Hl)

100

~

10 ",400/JA

1

10

frequencv (Hz)

!

-1001'1 1

10

I - ;:::-VOS:15V

~ :::s.d- V DS

I II

V D S"'20V

20

25

VOG (V)

o

30

1-55

o

L..'4 to

2

I
8 10 12 14 16 18 20 22 24 26 28 30
Vos (V)

I

rJn~nlb

3N161
Diode ProtectedP-Channel
Enhancement Mode MOSFET

FEATURES

II

PIN
CONFIGURATION

• Channel Cut Off with' Zero Gate Voltage
•. Square-LaVi Transfer Characteristic Reduces
Distortion .
• Independent Substrate Connection Provides
Flexibilty in Biasing
• Internally Connected Diode Protects Gate from
Damage due to Overvoltage

TO-72

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain-Source or Drain-Gate Voltage ............... 40V
Drain Current ................................. 50 mA
Gate Forward Current ........................ 10 JJA
Gate Reverse Current ........................... 1 mA
Storage Temperature ............... -65°C to +200°C
Operating Temperature .............. -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
Power Dissipation ........................... 375 mW
Derate above 25°C .................. 3.0 mW/oC

C

G S

D

CHIP
TOPOGRAPHY

1507

o

ORDERING INFORMATION·
DICE

3N1611D

ELECTRICAL CHARACTERISTICS

·When ordering wafer/dice refer to Appendix 8·23.
(25°C unless otherwise noted)

PARAMETER
IGSSF

BVGSS

MIN

Forward Gate-Ter.minal Current
ITA - +100°C
Forward Gate-Source Breakdown Voltage

TYP

MAX

-100
1
-25

UNIT
pA
nA
V

-10
-10

lOSS

Zero-Gate-Voltage Drain Current

VGS(th)

Gate-Source Threshold Voltage

-1.5

-5

VGS

Gate'Source Voltage

-4.5

-8

10(on)

On-State Drain Current

-40

-120

IVfsi

Small-Signal Common-Source
Forward Transfer Admittance

3500

6500

IVosi

Small-Signal Co mmon-Source
Output Admittance

Ciss

Common-Source Short-Circuit
:
Input Capacitance

10

Crss

Common-Source Short-Circuit
Reverse Transfer Capacitance

4

nA
J.1A
V
mA

TEST CONDITIONS
VGS

~

-25 V,

IG -0.1 mA,

VOS~

VOS

~

0

0,

VOS--15V,VGS-0
VOS ~ -25 V, VGS ~ 0
Vos ~ -15V, 10 ~ -10 J.1A
VOS ~ -15 V, 10 ~ -8 mA
VOS

~

-15 V, VGS

~

-15V

f

J.1mho

~

1 kHz

250
VOS~-15V,10~-8mA

pF

1-56

f~

1 MHz

3N163,3N164
P-Channel Enhancement
Mode MOS FEY

FEATURES
Very High Input Impedance
High Gate Breakdown
Fast Switching
Low Capacitance
ABSOLUTE MAXIMUM RATINGS (Note 1)
(TA = 25°C unless otherwise noted)

•
•
•
•

PIN
CONFIGURATION

CHIP
TOPOGRAPHY
1503

TO-72

f----- ~ ----I

Drain-Source or Drain-Gate Voltage
3N163 .................................... . 40V
3N164 .................................... . 30V
Static Gate-Source Voltage
3N163 ................................... '. ±40V
3N164 .................................... ±30V
Transient Gate-Source Voltage (Note 2)
........ ±125V
Drain Current ................................. 50 mA
Storage Temperature ................ -65° C to +200° C
Operating Temperature .............. -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ,......... +300°C
Power Dissipation ........................... 375 mW
Derate above +25° C .................. 3.0 mW;o C

G

ORDERING INFORMATION*
WAFER
DICE
TO·72
3N163/D
3N164/D

3N163/W
3N164/W

3N163
3N164

NOTES:
1, See handling precautions on 3N170 data sheet.
2. Devices must not be tested at ±125V more than once,
nor for longer than 300 ms,

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (@25°C and VBS = 0 unless noted)
Symbol

3N163

Parameter

MIN

IGSSR

Gate Reverse Leakage Current

IGSSF

Gate Forward Current

BVoss

Drain-Source Breakdown Voltage

BV SDS

Source Drain Breakdown Voltage

3N164

MAX

MIN

MAX

pA

-30
-40

VGS = -40V (3N1631
VGS = -30V (3N164)

10

=

-lOpA, V GS

0

-30

v

Threshold Voltage

-20

-5.0

-2.0

-5.0

Threshold Voltage

-2.0

-50

-2.0

-50

Voe

Gate Source Voltage

-3.0

-65

-3.0

-6.5

_ ...a,SmA
Voe - -15V. ID

loss

Zero Gate Voltage Drain Current

200

400

Source Dram Current

400

800

rOS(on)

Dram·Source on Resistance

250

300

On Drain Current

-5.0

Forward Transconductance

2000

-30,0
4000

-3.0
1000

-30,J

250

Vas - -15V, V GS
Veo

ohms
mA

25

2.5

07

07

Output Cdpacitance Input Shorted

30

3.0

25°C

15V, V GS

0

0

VDe

V GS .., -20V, 10

·100 J.1A

Vos -' -15V, V GS

-10V

VOS" -15V, 10

-10 mA, f

1 KH.1

250

Input Capacitance - Output Sh9rted

(@

·lOjJA

-15V,lo

4000

Reverse Transfer Capacitance

SWITCHING CHARACTERISTICS

VOS - V GS , 10" ·10)JA

pA

jJmhos

Output Admitt:mce

Coss

TEST CONDITIONS

10

10

-10
-10
,-------~----~--~----~--~
\ TA"'+125°C
-25
-25

Isos

9fs

UNITS

pF

Vas

-15V, 10

~

-10 mA, f

~

1 MHl

and V BS ~ 01

Turn-On Delay Time

12

12

V oo "--15V

Rise Time

24

24

IOlonl

Turn-Off Time

50

50

SWITCHING TIME CIRCUIT

-10 mA

SWITCHING WAVEFORM

VDD

" ]:vo",
_ _ _- ' 10%

50nL]

toft

1·57

.1

II

3N165,3N166
Dual P-Channel
Enhancement Mode
MOS FET

FEATURES

PIN
CONFIGURATION

• Very High Impedance
• High Gate Breakdown
• Low Capacitance

/)EVICE
SCHEMATIC

L
'~WL..'

TO-99

j

o

c ~

ABSOLUTE MAXIMUM RATINGS (Note 1)
(TA = 25°C unless otherwise specified)
Drain-Source or Drain-Gate Voltage (Note 2)
3N165 ..................................... 40V
3N166 ..................................... 30V
Transient Gate-Source Voltage (Note 3) .......... ±125
Gate-Gate Voltage .............................. ±80V
Drain Current (Note 2) ........................ 50 rnA
Storage Temperature ....... ; ........ -65°C to +200°C
Operating Temperature .............. -55°C to +150°C
Lead Temperature (Soldering. 10 sec.) ........ +300°C
Power Dissipation
One Side .............................. 300 mW
Both Sides ......... '................... 525 mW
Total Derating above 25°C ............. 4.2 mW/oC

•

2506

'0 -.u •

0,

0,

4

CHIP
TOPOGRAPHY

t·~~
.0330

002r,
-OO3!J

NOH' AA 1£
SURST

IS BOD v
----1'

,~vp
:~~~;,vp

0,

-

,

f"
GATE 'J-/"
GAfE 1

~~~~

&!29

s/o

,0230

u___L
1,

___

,L ROOY

S D'

ORDERING INFORMATION·

TO-99
3N165
3Nl66

WAFER
3N16S/W
3N166/W

DICE
3N165/D
3Nl661D

'When ordering wafer/dice refer 10 AppendiX S-23.
ELECTRICAL CHARACTERISTICS (@ 2SoC and Vas =0 unless notes)
PARAMETER
IGSSR
IGSSF
loSS
150S
10(on)
VGS(lh)
VGS(lh)
rDS(on)
gfs
gos
Clss
Crss
Coss
RE(Yfs)

MIN

Gate Reverse Leakage Current
Gate Forward Leakage Current
ITA= +125°C
Drain to Source Leakage Current
Source to Drain Leakage Current
On Drain Current
Gate Source Threshold Voltage
Gate Source Threshold Voltage
Drain Source ON Resistance
Forward Transconductance
Output Admittance
Input CapaCitance
Reverse Transfer CapaCitance
Output CapaCitance
Common Source Forward Transconductance

MATCHING CHARACTERISTICS

-S

-2
-2
1500

MAX
10
-10
-25
-200
-400
-30
-S
-S
300
3000
300
3.0
0:7
3.0

1200

TEST CONDITIONS

UNITS

VGS = 40V
pA

VGS = -40V
-20V
-20, VOS = 0
-1SV, VGS = -10V
-1SV, 10 = -10"A
VGS, 10 =' -10"A
-20V, 10 - -1oo"A

ohms

VOS =
Vso=
VOS =
VOS VOS =
VGS =

"mhos

VOS = -1SV, 10 =

mA
V

~

lOrnA, f = 1kHz

pF

VDS = -1SV; 10 = -10mA, f = 1MHz

"mhos

VOS = -15V, 10 = -10mA, f = 100MH

3N165

PARAMETER
Yfs1 /Yfs2 Forward Transconductance Ratio
VGSl-2 Gate-Source Threshold Voltage
Differential

MIN

MAX

0.90

1.0
100

TEST CONDITIONS

mV

VOS = -lSV, 10 = -1500!LA, f = 1KHz
VOS = -1SV, 10 = - SOO"A

100

Ll.VGS1-2 Gate Source Threshold Voltage
Differential Change with Temperature
Ll.T

/-IV/oC

100
Nole 1: See handling precautions on 3N170 data sheet.
Nole 2: Per transistor,
'

UNITS

1·58

VOS = -1SV, 10 = - 500"A
TA = -55°C to +25,oC

Nole 3: Devices must not be tested at ±125V more than once. nor for
longer than 300 ms,

.D~DIl

3N170,3N171
N·Channel Enhancement
Mode MOS FET

FEATURES
•
•
•
•

PIN
CONFIGURATION

Low Switching Voltages
Fast Switching Times
Low Drain-Source Resistance
Low Reverse Transfer Capacitance

HANDLING PRECAUTIONS
MOS field·effect transistors have extremely high in·

put resistance and can be damaged by the accumulation of excess static charge. Tq avoid
possible damage to the device while wiring.
testing. or in actual operation. follow the procedures ()utlined below.

TO-72

I. To avoid the build·up 01 Sialic charge, Ihe leads 01
the devices should remain shorted together with a
metal ring except when being tested or used.

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain-Gate Voltage ............... ±35V
Drain-Source Voltage ............... 25V
Gate-Source Voltage ............. ±35V
Drain Current ................... 30 mA
Storage Temperature
Range ............. -65°C to +200°C
Operating Temperature
Range ............. -55°C to +150°C
Lead Temperature
(Soldering. 10 sec.) ........... +300°C
Power Dissipation .............. 300 mW
I Derate above 25°C ..... 1.7 mW/oC

2. Avoid unnecessary handling. Pick up devices by
the case instead of the leads.
3. Do not insert or remove devices from circuits with

the power on as transient voltages may cause pe'r.
manant damage to the devices.

CHIP
TOPOGRAPHY

ORDERING INFORMATION·
WAFER
TO·72
DICE

1003

3N170
3N171

3N1701W
3N1701W

3N170/D
3N170/D

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted) Substrate connectored to source.

PARAMETER

MIN

BVDSS

Drain-Source Breakdown Voltage

IGSS

Gate Leakage CurrentlTA = 1250C

'DSS

Zero-Gate-Voltage Drain Current

MAX

25

V
10
100

ITA = 125°C
VGS(th)

Gate-Source Thresholdi
Voltage

I

UNITS

pA

TEST CONDITIONS
'D= lO IlA,VGS=O
VGS - -35 V, VDS - 0

10

nA

1.0

}1A
V

V DS = 10 V, I D = 10}1A

3N170

1.0

2.0

3N171

1.5

3.0

VDS=10V,VGS=0

'D(on)

"ON" Drain Current

mA

VGS=10V,VDS=10V

VDS(on)

Drain-Source "ON" Voltage

2.0

V

'D-10mA,VGs-l0V

rds(on)

Drain-Source ON Resistance

200

0

VGS = 10 V, ID = 0, f = 1.0 kHz

IYls I

Forward Transfer Admittance

10

}1mhos

1000

Crss

Reverse Transfer Capacitance

1.3

Ciss

Input Capacitance

5.0

Cd (sub)

Drain-Substrate Capacitance

5.0

td(on)

Turn-On Delay ,Time

3.0

tr

Rise Time

10

td(off)

Turn-Off Delay Time

3_0

tf

Fall Time

15

1-59

pF

VDS = 10 V, 'D = 2.0 mA,
f = 1.0 kHz
VDS = 0, VGS = 0, f = 1.0 MHz
VDS = 10 V, VGS = 0, f = 1.0 MHz
VD(SUB) = 10 V, f = 1.0 MHz

ns

VDD = 10 V, 'D(on) = 10 mA,

VGS(on) = 10 V, VGS(off) = 0,
RG = 50 {)

D

3N172,.3Ni·'S
Diode Protected
P·Channel Enhancement
ModeMOS FET
FEATURES

II

• High Input Impedance
• Diode Protected Gate

PIN
CONFIGURATION

ABSOLUTE MAXIMUM RATINGS

DEVICE
SCHEMATIC

TO-72

(TA = 25°C unless otherwise noted)
Drain-Source or Drain-Gate Voltage
3N172 ..................................... 40V
3N173 ..................................... 30V
Drain Current ................................. 50 mA
Gate Forward Current ........................ 10}.LA
Gate Reverse Current '........................... 1 mA
Storage Temperature ............... -65°C to +200°C
Operating Temperature .............. -55°C to +150°C
Lead Temperature (Solderi ng, 10 sec.) ........ +300° C
Power Dissipation ........................... 375 mW
Derate above 25°C .................. 3.0 mW/oC

,

~:
.
CHIP
TOPOGRAPHY

NOH

1503Z

SUISTRATt:
lS800V

ORDERING INFORMATION*
WAFER
TO·72
DICE
3N172
3N173

3N172/W
3N173/W

3N172/D
3N173/D

'When ordering wafer/dice refer to Appendix 8-23.

ELECTRICAL CHARACTERISTICS (@25°C and Ves = 0 unless noted)
3N173

3Nl72

UNITS

PARAMETER
MIN
"GSSR

MAX

MIN

-500

-200

Gate Reverse Current

I TA = +125 C

-1.0

-0.5

O

_125

-30

BVoss

Gate Breakdown Voltage

-40

BVoss

Drain-Source Breakdown Voltage

~40

-30

BV SDS

Source-Drain Breakdown Voltage

-40

-30

VGS1th )

Threshold Voltage

TEST CONDITIONS

MAX
pA

V GS = -20V

jJ.A
10=-10jJ.A

-125

10 = -10jJ.A
V

Is = -10jJ.A, V o • =0

-2.0

-5.0

-2.0

-5.0

Vos = V GS , 10 = -10jJ.A

-2.0

-5.0

-2.0

-5.0

Vos = -15V, 10 = -10jJ.A

-3,0

-6.5

-2.5

Gate Source Voltage

loss

Zero Gate Voltage Drain Current

-0.4

-10

'50S

Zero Gate Voltage Source Current

-0.4

-10

'OS(on)

Drain Source On Resistance

'D(on)

On Drain Current

250
-5.0

-30

1·60

-5.0

Vos = -15V, 10 =-500jJ.A

-6.5

V GS

nA

Vos = -15V, VGS = 0
Vso = -15V, VDe = 0, VGO = 0

350

ohms

-30'

rnA

V GS = -20V,lo = -1001lA
Vos = -15V, V GS = -10V

3N188·3N191
Dual P·Channel
Enhancement Mode MOSFET
FEATURES
•
•
•
•

Very High Input Impedance
High Gate Breakdown 3N190-3N191
Zener Protected gate 3N188-3N189
Low Capacitance

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-99

2506

I

ABSOLUTE MAXIMUM RATINGS
(T A = 25° C unless otherwise noted)
Drain-Source or Drain-Gate Voltage (Note 11
3N188. 3N189 ............................... 40V
3N190.3N191 .............................. 30V
Transient Gate-Source Voltage (Notes 1 and 21 .. ±125V
Gate-Gate Voltagae ............................ ±80V
Drain Current (Note 11 ......................... 50 mA
Storage Temperature ................ -65°C to +200°C
Operating Temperature .............. -55°C to +150°C
Lead Temperature (Soldering. 10 sec. 1 ........ +300°C
Power Dissipation
One Side .............................. 300 mW
Both Sides ............................ 525 mW
Total Derating above 25°C ............ 4.2 mWfOC

c

0,

D,

s,

NOTE: Bodv is connected to case.

ORDERING INFORMATION·
WAFER

TO·99

DICE

---

-

3N188
3N189
3N190
3N191

3N190/W

3N190/D

3N191/W

3N1911D

'When ordering wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS (25° C and

0 unless otherwise noted)

VBS =

3N188
3N189
MIN

PARAMETER
'GSSR

Gate Reverse Current

IGSSF

Gate Forward Current

BVOSS
BVSOS

Drain-Source Breakdown Voltage

ITA' '2SoC

Source-Drain Breakdown Voltage

VGSlthl Threshold Voltage
VGS

Gate Source Voltage
Zero Gate Voltage Drain Current

rnS{nn\

Source Drain Current
Drain-Source on esistance

'O(onl

On Drain Current

9fs
Yo.

-200

25

Ciss

Crss
Coss

-5.0

- 3.0

SWITCHING CHARACTERISTJCS (@25°Cand
Turn On Delay Time

Rise Time

toff

Turn Off Time

5.0
'500

4000

300
4.5

300
4,5

',5
3.0

'.0
3.0

VBS =

MAX
'5
30

VGS' -40V
10.uA

IS -10}.LA, VSO 0
VOS--'5V,IO -'0 "A
VOS VGS.IO--'O"A
Vos -'5V 10 - -500 "A

V

ohms

VOS -'5V
V SD
'5V, VOB
VOS--20V.10

mA

VOS

pA

- '5V, VGS

0

'U-'OV
U"

,umhos

f = 1kHz
VOS'-'5V,10'-5mA

pF

f'1MHz

UNITS

TEST CONDITIONS
V OO --15V, 10 --SmA

ns

R G - R L ' 1.4 kn

VBS =
MIN

0 unless noted) 3N188 and 3N190 .
MAX

0.85

UNITS

Yfs1/ Y fs2

Forward Transconductance Ratio

vGS'·2
Il GS1·2

\.;Jate ;)Curee

'uu

mV

uate ::::.ource hreshold voltage ui erent,ls Lhange
with Temperature{Note 4)

'00

"vrc

IlVGS1·2

Gate Source Threshold Voltage Differential Change
with Temperature(Note 4)

100

-:;::r-

40V

50

MATCHING CHARACTERISTICS (@ 25°C and

--;;;r-

pA

=

0 unless noted)

MIN
tdlan)

6.5
-200
-400
.uu
-30.0

-~u.O

4000

-5.0
-5.0

-3.0

200
400
.uu

TEST CONDITIONS
VGS

10 -

-2.0
-2.0

-5.0
-6.5

Output Admittance
Input Capacitance Output Shorted
Reverse Transfer Capacitance
Output Capacitance Input Shorted

tr

UNITS

-40
-40

-40
40
- 2.0

'500

MAX

-200

-5.0

Forward Transconductance(Note 3)

MIN

10
-10

··2.0
lOSS
IsoS

3Nl90
3N191

MAX

resnolo va tage UI erentls

'.0

"vrc

V OS ' -15V. 10 ' -500 "A, f"
Vos -'5V, 10 - -500 "A
V DS --'5V,1 0 --500"A,
T"" -55°C to + 25~C
Vos - -'5V, 10- 500"A
T

= +25°C to

kHz

+125°C

NOTES:
1. Per transistor

2. Approximately doubles for every 10°C increase in TA.

1·61

3. Pulse test duration = 300 !'sec; duty cycle'; 3"...
4. Measured at end points, TA and TB.

I

·U~DlL
FEATURES
• IR

= 0.1 pA (typical)

• BVR> 30V
• C rss = 0.75 pF (typical)

PIN
CONFIGURATIONS

GENERAL DESCRIPTION

TO-71
TO-78

The 10100 and 10101 are monolithic dual diodes intended
for use in applications requiring extremely low leakage
currents. Applications include interstage coupling with
reverse isolation, signal clipping and clamping and protec:
tion of ultra low leakage FET differential dual and opera·
tional aml?'ifiers.

ABSOLUTE MAXIMUM RATINGS
(T A = 25° C. unless otherwise noted)
Diode Reverse Voltage ........................... 30V
Diode to Diode Voltage ......................... ±50V
Forward Current. ............................... 20 mA
Reverse Current ............•..........•...... 100 p.A
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55° C to +150° C
Lead Temperature (Solde~ing. 10 sec.) ........ +300°C
Power Dissipation ............................ 300 mW
Derate above 25°C ................... 1.7.mW/oC

'These leads must not be tied together nor
connected to the circuit in any way.

CHIP
TOPOGRAPHY

'[jm'_
l.

.021

,-

:11

025

-..I

I

4000

CATHODE 111
112 00300030

.

0'15

TYP 2 PLACES

~
01'

'.

~

,0040' ~ .0'040

ANODE 112
TVP,;2 PLACES .0030' DIAMETER

"

0'0'40

ANODE 111

ORDERING INFORMATION*

·When ordering wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS

(@ 25°C unless otherwise noted)

PARAMETER

MIN.

VF

Forward Voltage Drop

0.8

BV R

Reverse Breakdown Voltage

30

'R

Reverse Leakage Current

IIR -I R I
1
.2
Crss

10100, 10101
TYP.
MAX.
1.1

0.1
2.0

ITA = 125°C
Differential Leakage .Current
Total Reverse CapaCitance

0.75
1-62

UNITS

TEST CONDITIONS

V

'F = lOrnA

V

'R

pA

VR = 1 V

nA
pA

V R =10V

3
1

pF

V R =lOV,f= 1 MHz

10
10

., 1 p.A

ID100, ID101
TYPICAL CHARACTERISTICS OF 10100/10101

REVERSE CURRENT vs. VOLTAGE

CAPACITANCE

12

1.0

11

0.9

10

;r

.s-

0.8

~

"-

9

Co

0.7
8

.!!'

r--I - -

II
r--

0.6

7
6

0.5

/'

5

0.4

/'

4
2

o

vs. VOLTAGE

./""

... -o

5

y

10

/'V

/'

V

0.3
0.2
0.1

15

20

5

30

25

FORWARD CURRENT vs. VOLTAGE
100 rnA
10 rnA

~~~~~!'-rll'l==r?t~:-'

~ +-+--t--t---t-t---j----r--~ l;f-: ----

r-r--+-_u.

1 rnA

~-+~~+-+-r--+~-t-~+'--~
___
II
=h±=

:-'-.0=-'---'--'----'1.4
100 nA 0=--'---"--"--'-LlO.=-5-'--'---'--.1--1

1-63

10

15

20

25

30

I

IT100,IT101
P-Channel JFET
FEATURES
• Interfaces Directly w/T2L Logic Elements
• rOS(on) < 7S0 for SV Logic Drive
• 10(ofl)

PIN
CONFIGURATION
TOc18

< 100 pA

GENERAL DESCRIPTION
This P·channel JFET has been designed to directly interface
with T2L logic, thus eliminating the need for costly drivers,
in analog gate circuitry. Bipolar inputs of ±15 V can be
switched. The FET is OFF for hi level inputs (+5 V or
+15 V) and ON for low level inputs « 0.5 V for IT100;<
1.5 V for IT101.

ABSOLUTE MAXIMUM RATINGS

CHIP
TOPOGRAPHY

(TA = 25°C unless otherwise noted)
Gate-Source Voltage ............................ 35V
Gate-Drain Voltage .............................. 35V
Gate Current .................................. 50mA
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
Power Oissipation ........................... 300 mW
Oerateabove25°C ................ 1.7mW/oC

5514
(SOURCE)

FULL RADIUS
(DRAIN)

...Q.Q.lli
,0015

I
I

c--------------'-J--

IL --'*~~1
SU~STRATE
NOTE.

IS GATE.

ORDERING INFORMATION·
TO·18

WAFER

DICE

IT100
IHOl

IT100/W
IT10l/W

IT100/0
IT101/D

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER
lOSS

Drain Current

Vp

Pinch Off Voltage

MIN

1T100
MAX

-10
2

IT10l
MIN
MAX

mA

-20
4.5

4

UNIT

10

TEST CONDITIONS
VGS = 0, VOS =-15 V
10 = 1 nA, VOS =-15 V

V

BVGSS

Gate·Sou rce Breakdown Voltage

IGSSR

Gate Reverse Current

gfs

Transconductance

gas

Output Conductance

1

1

10(off)

Orain (OFF) Leakage

-100

-100

pA

VOS=-10V,VGS=15V

rOS(on)

Orain·Source "ON" Resistance

75

60

n

VGS = 0, VOS =-0.1 V

Ciss

Input Capacitance

35

35

Crss

Reverse Transfer Capacitance

12

12

35

35
200

8

IG = 1 f.l.A, VOS = 0
200

pA

VGS = 20 V, VOS = 0

mmho

VGS = 0, VOS =-15 V

8

1·6.4

VOG =-20 V, VGS = 0
pF

VOG

~-10

V, IS = 0

IT120·IT122
Monolithic Dual
NPN Transistor

FEATURES
High hFE at Low Current
Low Output Capacitance
Good Matching
Tight VBE Tracking

PIN
CONFIGURATION

•
•
•
•

TO-71
TO-7S

D

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Collector-Base Voltage (Note 1) .................. 45V
Collector-Emitter Voltage (Note 1) ................ 45V
Emitter Base Voltage (Notes 1 and 2) .............. 7V
Collector Current (Note 1) ..................... 50 mA
Collector-Collector Voltage ....................... 60V
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55° C to +150° C
Lead Temperature (Soldering, 10 sec) ......... +300°C

Power
Dissipation
Derate Above

TO-71
ONE
BOTH
SIDE
SIDES
400 mW
750 mW

CHIP
TOPOGRAPHY
4003

TO-7S
ONE
BOTH
SIDE
SIDES
500
mW
300 mW

II--:C;:;'O:;-;LL:;E;:CT;;;O:;R-';'~'±.;;-;;::;;i-C-O-LL-'-CT-O-R ISOLATION :~~" :~~
~

::2 TVP. 2 PLACES

1

02 70

.::: "

_

-L_-.-.-,,-.,-L-!--'!-4-1 ':~

25°C ........ 1.7 mW/oC 2.9 mwrc 2.3 mW/oC 4.3 mW/oC

:~~

BASE ::2 TYP. 2 PLACES
DIAMETER

EMITTER::2 :0040
TYP, 2 PLACES .0030 DIAMETER

EMITTER #1

ORDERING INFORMATION*
TO·78
IT120
IT121
IT122

ELECTRICAL CHARACTERISTICS
1T120A
MIN MAX

1T120
MIN MAX

1T121
MIN MAX

1T122
MIN MAX

UNIT

200

80

80

IC" 10MA, VCE" 5.0 V

225

225

100

100

Ic" 1.0 rnA, VCE" 5.0 V

DC Current Gain

VBEIONI

Emitter-Base On Voltage

0.7

0.7

0.7

0.7

VCEISATI

Collector Saturation Voltage

0.5

0.5

0.5

0.5

'-CBO

Collector Cutoff Current

1.0

1.0

1.0

1.0

nA

10

10

10

10

MA

lEBO

Emitter Cutoff Current

1.0

1.0

1.0

1.0

nA

Cobo
Cte

Output Capacitance

2.0

2.0

2.0

2.0

Emitter Transition Capacitance

2.5

2.5

2.5

2.5

CC1' C2

Collector to Collector Capacitance

4.0

4.0

4.0

4.0

IC1' C2
VCEOISUSTI

Collector to Collector Leakage Current

10

10

10

10

75

1 TA" +150°C

Collector to Emitter Sustaining Voltage

GBW

Current Gain
Bandwidth Product

IVBE -VBE21

Base Emitter Voltage Differential

IIB1-IB21

Base Current Differential

c:'(VBE1 - VBE~ Base-Emitter Voltage Differential
Change with Temperature

TEST CONDITIONS

200
hFE

ITA"-We

DICE
IT120/0
1T121/0
ITl22/0

'When ordering wafer/dice refer to Appendix B·23.

(25° C unless otherwise noted I
PARAMETER

WAFER
IT120/W
1T121/W
1T122/w

TO·71
IT120·T071
IT121·T071
IT122·T071

30

30

75

Ie" 10 MA, VCE" 5.0 V

V

pF

45

45

V

10
220

10
220

7
180

7
180

MHz

1

2

3

5

mV

2.5

5

25

25

nA

10

20

IC"0.VEB"5.0V

f

MVtC

VCC-±60V
IC - 1.0 mA, I B - a
IC" 10 MA. VCE " 5 V
IC,l rnA, VCE "5 V
IC" 10 MA. VCE" 5.0 V
TA "" _55°C to +125°C
IC~ 10llA, V CE " 5.0 V

NOTES: 1. Per transistor.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 10 JJ.A.

1·65

=

IC" 0, VEB " 0.5 V 11 MHz
VCC" 0

nA

45

5

IE"0,VCB"45V

IE"0,VCB"5.0vl

45

3

IC" 0.5 rnA. IB" 0.05 rnA

IT124
Monolithic Dual
Super-Beta NPN Transistor
PIN
CONFIGURATION

FEATURES

D

•
•
•
•

CHIP
TOPOGRAPHY
4003Y

TO-78

Very High Gain
Low Output Capacitance
Tight VBE Matching
High GBW

.000S

.0045

:0035 • ~003s

"

t.:;:;:::;;:;;;;;:::::t::::t... -r~:;:;;::;;;;~:i:iiiilii=~--:::~ISOLATION
COLLECTOR =1
COLLECTOR
::2 TYP, 2 Pl ACES
.0045 ,01)45

,-O..lJg

0270

L-

ABSOLUtE MAXIMUM RATINGS

.003S II .-Ocijs

"

BASE :;2 TYP 2 PLACES

•••-,-"-':1'-""--'","",, ~~

(TA = 25° C unless otherwise noted)
Collector-Base Voltage (Note 1) ................... 2V
Collector-Emitter Voltage (Note 1) ................. 2V
Emitter-Base Voltage (Notes 1 and 2) .............. 7V
Collector-Current (Note 1) ..................... 10 mA
Collector-Collector Voltage ...................... 100V
Storage Temperature Range ... , ...... -65° C to +200° C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec) ......... +300° C

DIAMETER

- EMITTER;:2 ,0040
TYP 2 PLACES

:0030

EMITTER =1

OIAMFTER

ORDERING INFORMATION·

TO-78
ONE
BOTH
SIDE

SIDES

Power Dissipation ................ 300 mW
500 mW
Derate above 25° C ............ 1.7 mWr C 4.3 mWr C
·When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS
SYMBOL

@ 25°C (unless otherwise noted)

PARAMETER

MIN

DC Current Gain

hFE

lEBO
Cabo
Cte
CC1 C2
IC1C2

I TA = -55° C
Emitter-Base "ON" Voltage
Collector Saturation Voltage
Collector Cutoff Current
ITA=+150°C
Emitter Cutoff Current
Output Capacitance
Emitter Transition Capacitance.
Collector to Collector Capacitance
Collector to Collector Leakage Current

GBW

Current Gain Bandwidth Product

NF

Narrow Band Noise Figure'

VBE(ON)
VCE(SAT)
ICBO

BVcso
BVESO (Note 2)
VCEOISUST)

SYMBOL
IVBE1-VBE21
LlIIVBE1-VBE2l1/ Ll T
IIB1-ls21

CONDITIONS

UNITS

Ic = 1",A, VCE = 1V
Ic = 1O",A, Vc~ = 1V
0.7
0.5
100
100
100
0.8
1.0
0.8
250

10
100

V
pA
nA
pA
pF

2
7
2

Ic - 1mA, Is - 0.1mA
IE = 0, VCB = 1V
Ic = 0, VEB = 5V
IE = 0, VCB = 1V I _
Ic = 0, VEB _ 0.5Vl f -1 MHz

a

pA
MHz

3

Collector-Base Breakdown Voltage
. Emitter-Base Breakdown Voltage
Collector-Emitter Sustaining Voltage

MATCHING CHARACTERISTICS @

MAX

1500
1500
600

dB

V

Vcc Vcc - ±50V
Ic - 1O",A, VCE - 1V
Ic = 100",A, VCE = 1V
Ic = 1O",A. VCE = 3V,
f = 1 KHz, RG = 10 Kohms,
BW = 200 Hz
Ic = 1O",A, IE =
IE - 1O",A, Ic Ic - 1mA, Is -

a
a
a

25°C (unless otherwise noted)

PARAMETER
Base Emitter Voltage Differential
Base Emitter VOltag'e Differential
Change with Temperature
Base Current Differential

TYP

MAX

UNITS

2
5

5
15

mV

",vrc

.6

nA

CONDITIONS
Ic = 1O",A, VCE = 1V
Ic - 1O",A, VCE - 1V
T = -55°C to +125°C
Tc

= 1O",A,

VCE == 1V

NOTES:
1. Per transistor.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and the r'everse base-to-emitter current must never exceed 101'A,

1-66

FEATURES
•
•
•
•
•

High Gain at Low Current
Low Output Capacitance
Tight 18 Match
Tight V 8E Tracking
Dielectric Isolated Matched Pairs for Differential
Amplifiers

IT126·IT129
Monolithic Dual NPN
Transistor
CHIP
TOPOGRAPHY

PIN
CONFIGURATION
TO-78

TO-71

4001

ABSOLUTE MAXIMUM RATINGS
(TA = 25° C unless otherwise specified)

EMITTER
0029 ,0029
0039" .0039

Collector-Base Voltage (Note 1)
IT126,IT127 ............................... 60V
IT128 ..................................... 55V
IT129 ..................................... 45V
Collector-Emitter Voltage (Note 1)
IT126, IT127 ............................... 60V
IT128 ..................................... 55V
IT129 ..................................... 45V
Emitter-Base Voltage (Notes 1 and 2) ............. 7.0V
Collector Current (Note 1) .................... 100 mA
Collector-COllector Voltage ....................... 70V
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55° C to +150° C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
Power Dissipation
Total Dissipation at 25°C
Cast Temperafure
Derating Factor

T071
One Side Both Sides

TVP, 2 PLACES

BASE
0030
.0040

EMITTEA

JIC

,0030
.0040

TYP. 2 PLACES

BASE

0035 ,0034
0045· 0044

C,

TVP 2 PLACES

ORDERING INFORMATION*

T078
One Side 80th Sides

0.3 Watt
0.5 Watt
0.4 Watt
0.75 Watt
1.7 mW/oC 2.9 mwrc 2.5 mwrc 4.3 mwrc

T078

TO·71

WAFER

DICE

1T126

IT126·T071

IT126/D

1T127
1T128

1T127·T071
IT128·T071

1T129

IT129·T071

IT126/W
IT127/W
IT128/W
1T128/W

IT127/D
IT128/D
IT128/D

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
1T126
PARAMETER

MIN

MIN

800

200

15(1

II

hFE

200

DC Current Gain

I

IT129

150

UNITS

COND(TIONS

MIN

800

100

IC = 1.0 rnA. V CE = 5V

IC=10~A.VCE=5V

70

100
800

MAX

MAX

230

170

115

IC - 10 rnA. VCE = 5V

100

100

75

50

IC - 50 rnA, VCE = 5V

75

75

60

40

Collector Cutoff Current

I TA = +150'C

IC - 1 rnA, VCE = 5V
IC - 10 rnA, VCE = 5V

.9

.9

.9

.9

1.0

1.0

1.0

1.0

.3

.3

.3

.3

IC - 10 rnA, IB - 1 rnA

1.0

1.0

1.0

1.0

Ie = 50 rnA, IB = 5 rnA

0.1

0.1

0.1

0.1*

nA

0.1

0.1

0.1

0.1'

IlA

Collector Saturation Voltage

ICBO

MIN

150

Emitter·Base On Voltage

VCE(sat!

MAX

230

TA:: _55°C

VBE(on!

1T128

1T127

MAX

V

IC - 50 rnA, VCE - 5V

IE = 0, VCB = 45V, 30V'

lEBO

Emitter Cutoff Current

0.1

0.1

0.1

0.1

nA

IC '0, VEB

Cobo

Output Capacitance

3

3

3

3

pF

IE = 0, VCB - 20V

BVC,C 2

Collector to Collector Breakdown
Voltage

VCEO(sust!

Collector to Emitter Sustaining
Voltage

60

60

55

45

BVCBO

Collector Base Breakdown Voltage

60

60

55

45

IC= 10~A,IE =0

BVEBO

Emitter Base Breakdowrl Voltage

7

7

7

7

IE= lO~A,IC=O

±

100

± 100

±

100

±

100

IC = ±1
V

5V

~A

IC = 1 rnA, IB = 0

MATCHING CHARACTERISTICS
IVBE, . VBE 21 Base Emitter Voltage Differential

1

Base Emitter Voltage Differential

3

%

.1(IV BE
VBE21)

L'.T

IIBl - IB2!

2

3

5

5

10

20

mV

~v!'e

Change with Temperature
Base Current Differential

IC = 1 ma , V CE = 5V
IC = 1 rnA, VCE = 5V
TA = -55'e to +125'C

2.5

5

10

20

nA

IC = lO~A, VCE = 5V

.25

.5

1.0

2.0

IlA

IC = 1 rnA, VCE = 5V

NOTES:
1. Per transistor.
2. The reverse base-to-emitter voltage must never exceed 7.0 volts and
the reverse base-to-emitter current must never exceed 10,u Amps.

1-67

II

IT130·IT132
Monolithic Dual PNP
Transistor
PIN
CONFIGURATIONS

FEATURES
• High hFE at Low Current

TO-71'
TO-78

• Low Output Capacitance
• . Tight Ie Match

I

• Tight VeE Tracking

ABSOLUTE MAXIMUM RATINGS·
(TA= 25°Cunless otherwise specified
Collector-Base Voltage (Note 1) .••......•.•....•. 45V
Collector-Emitter Voltage) Note 1) .....••......•.. 45V
Emitter Base Voltage (Notes 1 and 2) .............. 7V
Collector Current (Note 1) ..•••.•.............. 50 mA
ColleQtor-Goliector Voltage ................•....•. 60V
Storage Temperature Range .......... -65° C tei +200° C
Operating Temperature Range ..•••.•. -55°C to +150°C
Lead Temperature (Soldering. 10 sec) ..•..•... +300°C

CHIP
TOPOGRAPHY

TO-78
TO-71
ONE
BOTH
ONE
BOTH
Power
SIDE
SIDES
SIDE
SIDES
Dissipation .••.• 400 mW
750 mW
300 mW
500 mW
2.3 mW/oC 4.3 mW;oC 1.7 mW;oC 4.3 mW/'C

4503

-r-;C;;;O~":;EC~T:;;OR;.-;.,;:I:• •i=iitl---:-C"ISOlAtION
.0045 k&Q§
COL.L.ECTOR
.0035 .0035
.2UO

#2 TVP. 2 PLACES

.0210

.0045
.0035

I

~---'A-SE-.,_Lh~~-'

.0045

Jt

.0035

BASE #2 TYP. 2 PLACES

: : - DIAMETER

~~~~J~~A~~'S ~

EMITTER #1

DIAMETER

ORDERING INFORMATION*
TO·78

WAFER

TO·71·

DICE

1T130A· T071 - IT130A/W - IT130A/D
IT130/W
IT130/D
IT130·T071
. IT1:jliWtiT131/D~
IT131·T071
-_."_.
.-.- IT132·T071 - - IT132;\!i -- '1T132/D

1T130A
IT130
1T131
IT132

----~,-.---.----

---~----.

------~----.-

"--,-

__

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICALCHARACTERISTICS(25°C unless otherwise noted)

.

'.

1T130A
MIN MAX

IT130
MIN MAX

1T131
MIN MAX

IT132
MIN MAX

200

200

225
ITA = _55°C 75

225
75

80
100

80
100

PARAMETER

hFE

DC Curre.nt Gain

VBE10N)

Emitter-Base On Voltage

VCEISATI

Collector Saturation Voltage

ICBO

Collector Cutoff Current

lEBO

Emitter Cutoff Current

Cob

Output Capacitance

Cte

Emitter Transition Capacitance

2.0
2.5

CC1-Co

Collector to Collector Capacitance

4.0

IC1-C;2
VCEO(SUST)

Collector to Collector Leakage Current

GBW
IVBE1-VBE21
IiBl-IS21

0.7
0.5
-1.0

ITA - +150°C

-10
-1.0

30
0.7
0.5

-1.0

-1.0

-10
-1.0
2.0

-10
-1.0
2.0
2.5
4.0
10

2.5
4.0
10

10

Collector to, Emitter Sustaining Voltage

-45

-45

-45

Current Gain
Bandwidth Product

5
110

5
110

4
90

Base Emitter V.oltage Differential
Base Cur'rent Differential
Base-Emitter Voltage Differential

Ll.IVBE1-VBE2V"T Chan'ge with Temperature

IC= 10pA, VCE =5.0V
0.7
0.5
-1.0

nA

-10
-1.0

pA
nA

IC = 10 pA, VCE = 5.0 V
IC = 0.5 mA, IB = 0.05 mA

V

2.0

IE=0,VCB=45V
<,

IC - 0, VEB - 5.0 V
IE - 0, VCB - 5.0 V
~-

2.5
4.0

pF

IC=0,VEB=0.5V

10

nA

VCC" 0
VCC - ±60 V
IC - 1.0 mA, IB = 0

-45
4
90

V
MHz

1

2

3

5

25

5
25

mV

2.5
3

5

10

20

pV/'C

.'

nA

IC=lOpA,VCE-5V
I C = 1 mA, VCE - 5 V
IC = 10pA, VCE - 5.0 V
IC

10 pA, VCE - 5.0 V

TA = -55'C to +125°C
IC = lOIlA, VCE = 5.0 V

NOTES:
1. Per transistor.
2. The reverse base-to-emitter voltage must never exceed 7 .OV, and the reverse base-to-emitter current must never exceed 10 JJA.

1-68

.'

IC-l0pA, VCE -5.0V
IC - 1.0 mA, VCE - 5.0 V

30

0.7
0.5

TEST CONDITIONS

UNIT

IT136-IT139
Monolithic Dual PNP
Transistor
FEATURES
•
•
•
•
•

High Gain at Low Current
Low Output Capacitance
Tight IB Match
Tight VBE Tracking
Dielectrically Isolated Matched Pairs for Differential
&
Amplifiers

PIN
CONFIGURATION

II

TO-71
TO-78

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Collector-Base Voltage (Note 1)
IT136, IT137 ...............................
IT138 .....................................
IT139 .....................................
Collector-Emitter Voltage (Note 1 )
IT136, IT137 ...............................
IT138 .....................................
m~

.....................................

60V
55V
45V
4501

60V
55V

CHIP
TOPOGRAPHY

~

Emitter-Base Voltage (Notes 1 and 2) ............... 7V
Collector Current (Note 1) .................... 100 mA
Collector-Collector Voltage ....................... 70V
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -5,5°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C

EMITTER _0029

BASE ,0030
.0040
COLLECTOR

EMITTER

0035

BASE

ONE

BOTH
SIDES

BOTH

SIDE

SIDES

.0030
_0040

7i044

TYP 2 PLACES

Power Dissipation .. . . . . . . . . . . . . .. 0.4 Watt
0.75 Watt
Derate above 25°C .......... 2.3 mwrc 4.3 mwrc
T071

ONE

:>:

TYP 2 PLACES

.0034

:0045)(

T078
SIDE

0029

0039 )( .0039
TYP, 2 PLACES

ORDERING INFORMATION·
t-IT136

TO·71

WAFER

DICE

IT136-T071

IT136/W

IT136/D

IT137

IT137-T071

IT137/W

IT137/D

IT138

IT138-T071

IT138/W

IT138/D

IT139

IT139-T071

IT1391W

IT139/D

TO·78

Power Dissipation ............... 0.3 Watt
0.5 Watt
Derate above 25°C .......... 1.7 mW/'C 2.9 mW/'C

·When ordering wafer/dice refer to Appendix B-23.

1-69

II

IT136 - IT139
ELECTRICAL CHARACTERISTICS

(@

25°C unless otherwise noted)

1T136
PARAMETER

MIN

1T137

MAX

MIN

150
150
hFE

DC Current Gain

VCE(sati

ICBO

150

MIN

MAX

70

100
800

100

UNITS

MAX

IC" 10 ilA. VCE" 5V

70

800

CONOITIONS

800

IC" 1.0 mAo V CE " 5V

125

125

80

50

IC" 10 mAo V CE " 5V

65

60

40

25

IC" 50 mAo VCE " 5V

75

75

60

40

ITA' 55'C
VBE(on)

MIN

150
800

1T139

IT138

MAX

IC - 10 mAo VCE - 5V

.9

.9

.9

1.0

1.0

1.0

1.0

.3

.3

.3

.3

.6

.6

.6

.6

0.1

0.1

0.1

0.1"

nA

).1

0.1

0.1

0.1*

p.A

Collector Saturation Voltage

Collector Cutoff Current

IC'l mAo VCE • 5V

.9

Emitter - Base On V,)ltage

1TA' +150'C

V

IC· lmA • I B··lmA
IC"10mA.IS"1 mA

lEBO

Emitter Cutoff Current

0.1

0.1

0.1

0.1

nA

Cobo

Output Capacitance

3

3

3

3

pF

PARAMETERS

1T136
I

MIN

IT138

IT137

MAX

MIN

MAX

MIN

MAX

1T139
MIN

IC' 50 mAo VCE" 5V

MAX

UNITS

IE

= O,VCB = 45\1, 30V'

IC - O. VES - 5V
IE"0,VCB'20V. 1·1 MHz
CONDITIONS

BVC,C2

Collector to Collector Breakdown
Voltage

VCEO(sust)

Collector to Emitter Sustaining

60

60

55

45

BVCBO

Collector Base Breakdown Voltage

60

60

55

45

IC"10/lA.IE"0

BVEBO

Emitter Base Breakdown Voltage

7

7

7

7

IE" lO/lA, IC'O

1T137

1T138

IT139

Voltage

PARAMETERS

±

lQO

IT136
MIN

MAX

MIN

± 100

± 100

± 100

MAX

MIN

MAX

MIN

IC' ±1 /lA
V

MAX

IVBE, - VSE 2 1

Base Emitter. Voltage Differential

1

2

3

5

c.1(VsE, - VBE 2 )Ii"T

Base Emitter Voltage Differential

3

5

10

20

UNITS
mV
p.vtc

Change with Temperature
IIB1 -1821

Base Current Differential

IC' 1 mAo IS • 0

COND,ITIONS
IC'l ma.VCE"5V
IC"

mAo VCE" 5V

TA" -55'C to +125'C
2.5

5

10

20

nA

IC"'0p.A,VCE"5V

.25

.5

1.0

2.0

/lA

IC-1 mA.VCE-5V

NOTES. 1. Per transistor.
2. The reverse base-to-em"itter voltage must never exceed 7.0 volts and the reverse base-to-emitter current must never exceed 10,uA

1-70

IT500·IT505
Monolithic Dual
Cascoded
N·ChanneIJFET
FEATURES

GENERAL DESCRIPTION

• CMRR > 120 dB
• IG < 5pA @ 50VOG
• C rss < 0.5 pF
• 90S > .025 /imhos

A low noise, low leakage FET that employs a cascade
structure to accomplish very low IG at high voltage levels,.
while giving high transconductance and very high common.
mode rejection ratio.

ABSOLUTE MAXIMUM RATINGS

L.........- - - - -.....+--CASE

ITA = 25°C unless otherwise specified)
Drain-Source and Drain-Gate
Voltages (Note 1) ................................ 60V
Drain Current (Note 1) ........................... 50 mA
Gate-Gate Voltage ................................. ±60V
Storage Temperature ................... -65°C to +200°C
Operating Temperature ................. -55° C to +150° C
Lead Temperature (Soldering, 10 sec.) ........... +300°C
Power Dissipation ............
Derate above 25° C ......

ONE SIDE

BOTH SIDES

250 mW
3.8 mwr C

7.7 mW/ o C

PIN
CONFIGURATION
TO-71

low prollle

500 mW

CHIP
TOPOGRAPHY
(Note 2)
6028

DRAIN'

.003)( .003
BODY

.003DIA.
SOURCE'
.033)( .003

GATE'
.003 x .003

GATE 2

003 x .003
DRAIN 2

SOURCE 2

003

II.

.003

ORDERING INFORMATION*
TO-78
IT500
IT501
IT502
IT503
IT504
IT505
NOTE 1. Per transistor.
NOTE 2. Due to the non-symmetrical. structure of these devices, the
drain and source ARE NOT interchangeable.

WAFER
IT500/W
IT501/W
IT502/W
IT503/W
IT504/W
IT505/W

DICE
IT500/o
IT501/o
IT502/o
IT503/o
IT504/D
IT505/o

·When ordering wafer/dice refer to Appendix 8-23.

1-71

1

II

.•O~OI6

IT500 ·IT505
ELECTRICAL CHARACTERISTICS (@25°C unless
Characteristics

Symbol

Min

IGSSR

Gate Reverse Current ITA _ 125'C

BVGSS

Gate·Source Breakdown Voltage

-60

VGS (olf)

Gate·Source Cutoll Voltage

-0.7

VGS

Gate·Source Voltage

IG

Gate Operating Curren 1TA = 125'C
Common-Source Forward

Transconductance (Note 1

r

nA

-4

V

5

pA

-5

nA

7

rnA

1000

4000

700

1600

Common-Source Output

Ciss

Spot Noise Figure

-en

Equivalent Input Noise Voltage

Characteristics

10SSl
IOSS2
gfSl/gfs2

6 VGS1·VGS2
6T

1= 1 MHz
VOS = 20V, VGS = 0
1= 100Hz,
RG = 10 Ml!

dB

1= 10 Hz
1-1 kHz

/lV

0.035
0.010

VHZ

IT500
IT502
IT504
IT501
IT503
IT505
Min Max Min Max Min Max Min Max Min Max Min Max
5

5

5

5

10

0.95

1

0.95

1

0.95

1

0.95

1

0.9

1

0.85

1

Transconductance
Ratio (Note 1)

0.97

1

0.97

1

0.95

1

0.95

1

0.90

1

0.85

1

5

5

10

15

25

50

5

10

20

40

100

200

Test Conditions

Unit

15

Saturation Drain
Current Ratio
(Note 1)

Dillerential Gate·
Source Voltage
Gate·Source Dif·
ferential Voltage
Change with
Temp.' (Note 2)

VGS1·VGS2

= V G2 - 10V

V G1

pF

0.5

Dillerential Gate
Current

IG1.IG2

VOS = 20V, 10 = 200/lA
pF

0.5

Capacitance (Note 3)

NF

Symbol

f = 1 kHz
VOS = 20V ,VGS = 0

7

Common-Source Reverse
T~ansler

= 20V, VGS = 0

VOG = 20V, 10 = 200/lA

3.5

Capacitance

Cr55

VOS = 20V, VGS = 0

/lrnho

0.025

Common-Source Input

VOG = 50V, 10 = 200 /lA

VOS

1

Conductance
Gate to Gate Capacitance

Cg192

VOS- 20V, 10 -1 nA

3.8

Conductance

gos

Test Conditions
VGS = -20V, VOS = 0
IG = -·l/lA, VOS = 0

Common-Source Output

90s

Unit
pA

-5

0.7

Common-Source Forward
Transconductance (Note 1)

gls

Max
-100

0.2

Saturation Drain Current (Note 1)

lOSS
gls

otherwise specified)

=

VOG
20V,
10
200 ~A

nA

10

20

100

40

f

Common Mode
Rejection Ratio

120

120

120

120

= 25'C
= 125'C

=

dB

120

VOG
20V TA
10
200~ Te
TA
Te

=

200

120

= 1 kHz

mV

\

C MRR ""

= OV

VOS = 20V, VGS

~V/'C

5

+ 125'C

=

6 VOO

55'C

= 2S'C
= 10V, 10 = 200 ~A

•• C MRR = 20 log'0 6Voo/6 [ Vg" . V g,21. 6voo. 101· 20V
NOTES: 1. Pulse test requireO. pulsewidth '" 300 JiS. duty cycle ~3%.
3. With case guarded Crss is typically < 0,15 pF.

2. Measured at end points. T A and T S.

TYPICAL PERFORMANCE CURVES

;t

~ 2.5

5

I

....

~

10'" JOO.uA
TA=25"C

4

I

>-

-

~ 2.0

=>

:;; 3

~
~
w

.... 1

-

/

/

./

~
I

9

TYPICAL CAPACITANCE VS,
GATE·SOURCE VOL TAGE

OUTPUT
CHARACTERISTICS

GATE LEAKAGE

zo

30
40
50
60
VDG - DRAIN·GATE VOLTAGE - VOLTS

10

a~ 1.5
w
u

0:

~ 10
Z

~ 0.5

o
I

£> 0

r

y.

r

r

VGS=
VGS

E

.Iov
O.2V

>- 2.0

~

=-a.4V

0:
'0:

=> 1.'
u

a.BV

=

Vas"

1.2V
1.4V
1.6V

i\

=> 1.0
~

i!i
Q

10

-

DRAIN TO SOURCE VOLTAGE

~

~
<5

\

C( 0.5

f=

0
0

-0.5

"

-1.0

-1.5

6
4

C;"

fo
-2.0

-2.5

VGS - GATE SOURCE VOLTAGE - VOLTS

1-72

I

w

z

I--

I

Vos" lOV
f=1.0MHz

itI •

'\

l!!

VGS "'-1.0V
Vas
Vas=

I

I

r---

VGS = a.BV
VGS'"

10

2.'

~

VGS

o

-2

c,~

-8
-10
-4
' VGS - GATE·SOURCE VOLTAGE - VOLTS

A050
Using the
IT500 Family to
Improve the
Input Bias Current of
BIFET OPAMPS
INTRODUCTION
The LF156 family of BIFET OPAMPS is very popular because
of the combination of high slew rate (typically 12V/J.ls @ unity
gain) and moderate offset voltage (about 2mV). Input bias
current, however, varies directly with input voltage, rising from
30pA @ VIN = -10V, to 50 pA @ VIN = OV, and finally to 80pA @
VIN = +10V. This can be improved markedly by using one of
the IT500 series to drive the inputs of the LF156.

The IT500, like the others in its family, is a dual cascoded nchannel JFET pair, featuring a typical input bias current of
<1 pA with inputs ranging from -15V to +15V; actual IG is
guaranteed to be less than 5pA @ VDG = 50V.
Figure 1 shows an IT500 being used to drive the inputs of an
LF156. This greatly reduces the input bias current, and in no
way affects the already superior slew rate; the offset voltage is
not significantly degraded because of the excellent matching
of the IT500.

+15V

+INPUT

-15V

FIGURE 1. INPUT DRIVE CIRCUIT USING IT500

The constant current source can be designed with any
transistor pair having a high beta @ Ie = 400J.lA. See Figure 2.

+15V

An added bonus of the IT500 is its CMRR > 100dB, compared
to the LF156 CMRR of 85dB.

7Sk.l1

(ldeally73kn)
400p.A

This configuration is ideal for electrometer circuits, with good
measurement accuracy down to 10pA of input current « 10%
error with 10pA of input current). A 10M.o glass feedback
resistor connected between the -INPUT and OPAMP OUTPUT
does the trick. Other possible applications include sample and
hold amplifiers, instrumentation amplifiers, etc.
Although this application note has dealt solely with the
LF156, all present day BIFET OPAMPS exhibit the same ISlAS
vs. VIN dependancy, and all will benefit from using the IT500
as a preamplifier.

-15V

FIGURE 2. CONSTANT CURRENT SOURCE

1-73

D

II

IT559

DualN·ChannelJFET
FEATURES
- Specified Matching Characteristics
-High Gain
- Low "ON" Resistance

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-?1

6033

ABSOLUTE MAXIMUM RATINGS
(25°C Unless otherwise noted)
Gate-Drain or Gate-Source Voltage ................. -40V
Gate Current .................................... 50 mA
Gate-Gate Voltage ................................ ±80V
Storage Temperature Range ............ -65°C to +200°C
Operating Temperature Range .......... -55° C to +150° C
Lead Temperature (Soldering, 10 sec.) .. , ........ +30QoC
One Side
Both Sides
Power Dissipation ...............
325mW
650mW
Derate above 25° C ........... 2.2mwr C 3.3mwr C

ELECTRICAL CHARACTERISTICS '
TEST CONDITIONS- (25°C unless otherwise
SYMBOL

gfs

Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage
Gate-Source Voltage
Saturation Drain Current (Note 1)
Static Drain Source ON Resistance
Common-Source Forward
Transconductance (Note 1)
Common-Source Output Conductance
Common-Source Reverse
Transfer Capacitance

gos
C,ss

en

WAFER

DICE

IT550

IT550/W

IT55O/D

TEST CONDITIONS

MIN.

MAX.

UNIT

-100
- 200

pA
mA

-3
1.0
30
100
12,500

V

VGS = -20V,Vos = 0

I
IG = -1~A, VOS = 0
VOS - 15V, 10 = 1nA
VOS = OV, IG - 2mA
VOS = 15V, VGS = 0
10=1mA,VGS=0

-40
-0.5
5
f = 1'kHz
f = 100MHz
f = 1kHz

VOG = 15V, 10 = 2mA

7500
7000

mA
Il
~mho

45

f = 1MHz

3
pF

Common-Source Input Capacitance
Spot Noise Figure
Equivalent Short Circuit
Input Noise Voltage

Ciss
NF

TO·71

noted)

PARAMETERS

I TA == 150·C

BVGSS
VGS(off)
VGS(f)
loss
rOS(on)

ORDERING INFORMATION·

'When ordering wafer/dice refer to Appendix B-23.

Gate-Reverse Current

IGSSR

$,

12
1.0
50

f = 10Hz, Rg = 1M
f = 10Hz

dB
nV

/Hz
IT560

SYMBOL

PARAMETERS

IOSS1
IOSS2

Saturation Drain Current
Ratio (Notes 1 and 2)

I VGS1- VGS2 I

Differential Gate-Source
Voltage

.0. I VGS1-VGS2I

Gate.-Source Voltage
Differential Drift (Note 3)

aT

-gls1
gls2

Transconductance Ratio
(Notes 1 and 2)

CONDITIONS
VOS = 15V, VGS = 0

MIN.

MAX.

0.95

1

-

50

mV

100

~V/"C

1

-

VOS = 15V, 10 = 2mA

UNIT

(TA = -55°C to +125"C)

VOS = 15V, 10 = 2mA

f '" 1kHz

0.90

2. Assumes smaller value in numerator
3. Measured at end pOints TA and T B

NOTES:
1. Pulse test required; pulse width 30()l's, duty cycle:5 3%.

1-74

IID~D~

IT1700
P-Channel Enhancement
Mode MOSFET

FEATURES
•
•
•
•
•

Low ON-Resistance
High Gain
Low Noise Voltage
High Input Impedance
Low Leakage

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-72

1503

II

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain-Source and Gate-Source Voltage ...... -40 V
Peak Gate-Source Voltage (Note 1) ......... ±125 V
Drain Current ............................. 50 mA
Storage Temperature ............ -65° C to +200° C
Operating Temperature Range ... -55 0 C to +150 0 C
Lead Temperature (Soldering, 10 sec) ..... +300°C
Power Dissipation ....................... 375 mW
Derate above 25° C .................. 3 mW/o C

C

G S

0

ORDERING INFORMATION·

·When ordering waler/dice reler to Appendix B·23.

ELECTRICAL CHARACTERISTICS

(25°C unless otherwise noted), VBS = 0 unless otherwise noted.

PARAMETER

MIN

MAX

UNITS

TEST CONDITIONS

V

VGS - 0, ID - -10/lA

V

VGS - 0, I D - -10 /lA

BVOSS

Drain to Source Breakdown Voltage

-40

BVSOS

Source to Drain Breakdown Voltage

-40

IGSS

Gate Leakage Current

IDSS

Drain to Source Leakage Current

200

pA

IDSS (150 a C)

Drain to Source Leakage Current

0.4

/lA

ISDS
ISOS (150 a C)

Source to Drain Leakage Current

400

pA

0.8

/lA

VGS(th)

Gate Threshold Voltage

rDS lonl

Static Drain to Source "on" Resistance
Drain to Source "on" Current

lOS (on)

(See note 2)

Source to Drain Leakage Current
-2

V

400

ohms
mA

4000

/lmhos

VOS - -15 V, ID ~ -10 mA
f ~ 1 kHz
VOS = -15V, 10 = -10 mA
f = 1 MHz

9fs

Forward Transconductance
Common Source

Ciss

Small Signal, Short Circuit, Common
Source, Input Capacitance

5

pF

Crss

Small Signal, Short Circuit, Common

1.2

pF

,

VGS~-10V, VOS~O

3.5

Small Signal, Short Circuit, Common

VDG

~

-15 V, 10

I

~

0

= 1 MHz

VDS~-15V,

pF

Source, Output Capacitance

·lb V

VGS--l0V,VDS

f

Source, Reverse Transfer Capacitance
Coss

VGS ~ VDS, 10 ~ -10 /lA

-5

2

2000

VGS ~ 0-, VOS ~ -20 V

~

10--10mA

1 MHz

NOTES: 1. Oevice must not be tested at ± 125V more than once nor longer than 300 ms.
2. Actual gate current is immeasurable. Package suppliers are required to guarantee a package leakage of

<

10 pA. External package

leakage is the dominant mode which is sensitive to both transient and storage environment, which cannot be guaranteed.

1·75

.

.D~D[L

IT1750

N·ChannelEnhancement
Mode MOSFET

D

FEATURES
• Low ON Resistance
• Low Cdg
• High Gain
• Low Threshold Voltage

PIN
CONFIGURATION
TO-72

ABSOLUTE MAXIMUM RATINGS
ITA = 25°C unless otherwise noted)
Drain-Source and Gate-Source Voltage ............ 25V
Peak Gate-Source Voltage (Note 1) ............... ±125V
Drain Current .............•................... 100 mA
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55° C to +150° C
Lead Temperature (Soldering, 10 sec.) ......... +300°C
Power Dissipation ............................ 375 mW
Derate above 25° C ....................... 3 mW/o C

CHIP
TOPOGRAPHY
1003

,
014(/

0180

I
NOH

SUBSTRATE

tseoov

ORDERING INFORMATION*

·When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS IT A = 25°'C, Body connected to Source and VBS = 0 unless otherwise noted)
VGS(th)
lOSS

PARAMETER
Gate to Source Threshold Voltage
Drain Leakage Current

MIN
0.50

TVP
' 1.5
0.1
See note 2.

MAX
3.0
10

UNITS
V
nA

50

V
ohms
rnA

rOS(onJ
10(on)

Gate Leakage Current
Drain Breakdown Voltage
Drain To Source on Resistance
Drain Current

Vis

Forward Transadmittance

Ciss

Total Gate Input Capacitance

5.0

6.0

pF

Cdg

Gate to Drain Capacitance

1.3

1.6

pF

L~
BVOSS

25
10

25
50

3,000

Ilmhos

TEST CONDITIONS
VDS -' VGS, 10 - 10 IlA
VOS = 10 V,.VGS= 0
10 = 101lA, VGS = 0
VGS = 20 V
VOS= VGS = 10 V
VOS = 10 V, 10 = 10 rnA,
I =1 KHz
10 = 10 rnA, VOS = 10 V,
'I = 1 MHz
VOG = 10 V, f = 1 MHz

NOTES:

1. Devices must not be tested at ± 125V more than once nor longer than 300 ms.
2. Actual gate current is immeasurable. Package suppliers are required to guarantee a package leakage of < 10pA.
External package leakage is the dominant mode which is sensitive to both transient and storage environment, which

cannot be guaranteed.

1·76

J105·J107
N·ChanneIJFET
PIN
CONFIGURATION

D

TO-92

FEATURES
• Low r DS(on)

APPLICATIONS

• Analog Switches
• Choppers
• Commutators

S

D

0

ABSOLUTE MAXIMUM RATINGS
(TA == 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ...... -25V
Gate Current .......................... 50 mA
Storage Temperature Range ,. -65° C to +200 0 C
Operating Temperature Range -55 0 C to +150° C
Lead Temperature (Soldering, 10 sec.l .•. +300°C
Power Dissipation ........ ,.......... 360 mW
Derate above 25° C .......... 3.3 mW/ o C

ORDERING INFORMATION*

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25·C unless otherwise noted
J10S
PARAMETER
IGSS

Gate-Reverse Current (Note 1)

VGS(off)

Gate-Source Cutoff Voltage

BVGSS

Gale-50urce Breakdown Vollage

lOSS

Oraln Saturation Current (Note 2)

MIN

TYP

·When ordering wafer/dice refer to Appendix B·23.
J106

MAX

MIN

TYP

-3
-4.5

TO·92 only
TO·92 only
TO·92 only

J105
J106
J107

-10

J107
MAX

MIN

TYP

-6

-2

MAX
-3

-3
-0.5

25

25

-25

500

200

100

UNIT TEST CONDITIONS
nA

-4.5

VOS=OV. VGS= -15V
VOS=5V. 10=1 ,A

V

VOS-OV,IG-

I,A

mA VOS=15V, VGS-OV

1000ff)

Drain Cutoff Current (Note 1)

3

3

3

nA

rOS(on)

Orain source ON Resistance

3

6

8

0

Cdg(Off)

Drain Gate OFF capacitance

35

35

35

Csg(off)

Source Gate OFf Capacitance

35

35

35

Drain Gate plus Source Gate

160

160

160

VOS = 5V. VGS = -10V
VOS"O.IV, VGS-OV
VOS=OV. VGS= -10V
f=l MHz

Cdg(on)

+
Csg(on)

ON Capacitance

Id(On)

Turn On Delay Time

15

15

15

Ir

Rise Time

20

20

20

Id(Off)

Turn Off Delay Time

15

15

15

If

Fall Time

20

20

20

NOTES: 1. Approximately doubles for every 10·C increase in TA.
2. Pulse test duration =300,.s; duty cycles3%.

1·77

pF

ns

VOS=VGS=OV

Switching Time Test
Jl05
1.5V
VOO
VGS(o!!)
-12V
500
RL

Conditions
Jl06 Jl07
1.5V 1.5V
-7V -5V
501l
500

D

J111·J113
,N·Channe."FI;T

FEATURES
•
•
•
•

Low Cost
Automated Insertion Package
Low Insertion Loss
No Offset or Error Voltage Generated by Closed
Switch
Purely Resistive
High Isolation Resistance from Driver
• Fast Switching
• Short Sample and Hold Aperture Time

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-92

5001
00'. 'Ull "ADIUS

IDm,tDtIt"I~'

APPLICATIONS
• Analog Switches
• Choppers
• Commutators

D

S

f- ..2.!!.-1
.10

0

ISOURCf I

ORDERING INFORMATION·

ABSOLUTE MAXIMUM RATINGS
(TA = 25 0 C unless otherwise noted)

Gate-Drain or Gate-Source Voltage ••....•.•...•• -35V
Gate Current ...•...........•••.....••......... 50 mA
Storage Temperature Range •........• -65 0 C to +200° C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) .......• +300°C
Power Dissipation .•....•••.•.•..•.....••...• 310 mW
Derate Above 25° C ....•••.....•...•• 2.8 mW/o C

TO·92

WAFER

DICE

J111
J1t2
J113

J111/W

J111/D
J112/D
J113/D

J112/W
J113/W

·When ordering wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted

IGSSR
VGS(ofl)
BVc;ss
loss
IO(off)
rOS(on)
Cdg(ofl)
Csg(off)
Cd~(On)

Csg(on)
td(on)
tr
td(Ofl)
tl

PARAMETERS
Gate Reverse Current (Note 1)
Gate Source Cutoff Voltage
Gate Source Breakdown Voltage
Drain Saturation Current (Note 2)
Drain Cutoff Current (Note 1)
Drain Source ON Resistance
Drain Gate OFF Capacitance
Source Gate OFF Capacitance
Drain Gate Plus Source Gate
ON Capacitance
Turn On Delay Time
Rise Time
Turn Off Delay Time
Fall Time

J.111
J112
J113
MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT
-1
-1
-1
nA
-10
-3
-1
-5 -0.5
·3
V
-35
-35
-35
20
2
mA
5
1
nA
1
1
30
100
fl
50
5
5
5
5
5
5
pF
28
28
28
7
6
20
15

7
6
20
15

NOTES:
1. Approximately doubles for every 10°C increase in TA.
2. Pulse Test duration 3001's; duty cycle ::s 3%.

1-78

7
6
20
15

ns

TEST CONDITIONS
Vos OV, VGS- 15V
Vos- 5V, 10 - 11'A
Vos - OV, IG- 11'A
Vos 15V, VGS' OV
10V
Vos 5V,VGS
Vos - 0.1V,VGS -OV
VOS = OV, VGS = -10V
Vos:-- VGS - 0

f= 1 MHz

Switching Time Test Conditions
J111
J112 J113
10V
10V
10V
VOO
-7V
-5V
VGS(off) -12V
0.8kfl 1.6kfl 3.2kfl
RL

J174-J177
P-Channel JFET
PIN
CONFIGURATION

FEATURES
• Low Insertion Loss
• No Offset or Error Generated by Closed
Switch
Purely Resistive
High Isolation Resistance from Driver
• Short Sample and Hold Aperture Time
• Fast Switching

CHIP
TOPOGRAPHY (Note 1)
5508

TO-92

q
OOJI

noT! •

NOTE SUBSTRATE IS GATE

o

APPLICATIONS
• Analog Switches
• Choppers
• Commutators

G

S

ORDERING INFORMATION*
TO·92
J17X

I
I

WAFER
J17X/W

I
I

DICE
J17XID

I
I

'When ordering wafer/dice refer to Appendix 8-23.

ABSOLUTE MAXIMUM RATINGS I,TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage (Note 1) ................................. 30V
Gate Current ........................................................... 50 mA
Storage Temperature Range ................................... -65 c C to +200 c C
Operating Temperature Range ................................. -55 c C to +150 c C
Lead Temperature (Soldering, 10 sec.) .................................... 300 c C
Power Dissipation .................................................... 350 mW
Derate above 25 c C ........................................... 3.5 mW/cC

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25 C unless otherwise noted
C

J174

J175

J176

Jl77

PARAMETERS
MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT
TEST CONDITIONS
1
Gate Reverse Current
1
1
nA
1
VDS - O. VGS- 20V
IGSSR
(Nate 21
5
3
1
4
0.8
2.25
VOS --15V, 10 ~-10nA
VGS{off) Gate-Source Cutoff
10
6
Voltage
V
Gate-Source Breakdown 30
BVGSS
30
30
30
Vos - 0, IG - 1MA
Voltage
Saturation Drain Current
-100 -7
1.5
loss
20
60 -2
25
20
mA VOS - -15V, VGS - 0
INote 31
-1
-1
-1
Drain Cutoff Current
IO(off)
nA
1
VOS - -15V, VGS -10V
INote 21
Drain-Source ON
85
125
250
300
II
rOS(an)
VGS - 0, Vos - -{I. IV
Resistance
Drain-Gate OFF
Cdg(off)
5.5
5.5
5.5
5.5
Capacitance
Vos ~ 0, VGS ~ 10V
Source-Gate OFF
5.5
5.5
5.5
5.5
Csg(off)
Capacitance
pF
f ~ 1 MHz
Drain-Gate Plus Source
Cdg(on)
VDS ~ VGS ~ 0
Gate ON Capacitance
40
40
40
40
+
Csg(on}
td(on)

Turn On Delay Time

2

5

15

20

Ie
td(off)
tf

Rise Time
Turn Off Delay Time
Fall Time

5
5
10

10
10
20

20
15
20

25
20
25

NOTES:
1. Geometry is symmetrical. Units may be operated with source and drain leads interchanged.
2. Approximately doubles for every 10°C increase in TA.
3. Pulse test duration -300j.ls; duty cycle::::: 3%.

1·79

ns

Switching Time Test Conditions
J174 J175 J176 JI77
10V -f;V -f;V -f;V
Voo
8V
6V
3V
VGS(off) 12V
560!! 12K! 5.6K!! 10K!!
RL
OV
OV
OV
OV
VGS(on)

II

U~Ull

J201·J204
N·ChanneIJFET

FEATURES
• High Input Impedance
• Low IGSS

PIN
CONFIGURA TlON

CHIP
TOPOGRAPHY

TO-92

5010'

:::=:::FULL R.

0(2)

r----f-f,

sell

ABSOLUTE MAXIMUM RATINGS

(TA == 25°C unless otherwise noted)

~-+--+-.'--'-

Gate-Source or Gate-Drain Voltage ...... -40V
Gate Current .......................... 50 mA
Storage Temperature Range .. -65° C to +200° C
Operating Temperature Range -55°C to +150°C
Lead Temperature (Soldering. 10 sec.) ... +300° C
Power Dissipation ................... 360 mW
Derate above 25° C ........... 3.3mW/o C

o

5

I

G

:::::= x: : : : :

NOTE: SUBSTRATE IS GAT!

..-

.004I{.1111)
.0050(.12701
.01'(.27"
.015(.111) -

I

ORDERING INFORMATION·
WAFER
J201/W
J202/W
J203/W
J204/W

TO·92

J201
J202
J203
J204

DICE

J2011D
J2021D
J203/D
J204/D

'DICE WITH 4 MIL BONDING PADS
AVAILABLE. CONSULT FACTORY
FOR DETAILS.

ELECTRICAL CHARACTERISTICS

·When ordering wafer/dice refer to Appendix B·23.

TEST CONDITIONS: 25°C unless otherwise noted
J201
PARAMETERS

lass

MIN

TVP

J202
MAX

MIN

TVP

-100

Gate Reverse Current

J203
MAX

MIN

TVP

-100

J2Q4
MAX

MIN

TVP

-100

MAX

UNIT

-100

pA

TEST CONDITIONS

Vos::;:O, VGS: -lOV

(Note 2)
VGS(off)

Gate·Source Cutoff

-1.5

-0.3

-0.8

-4.0

-10,0

-2.0

-05

-2.0

Voltage
BVGSS

Gate·Source Breakdown

VOs=20V,IO=10nA

v

-.40

-40

-25

-40

VOS=O, IG= -l~A

Voltage

'OSS

Saturation Drain Current

0.2

1.0

0.9

4.5

4.0

20

1.2

mA

VOS=20V, VGS=O

-35

pA

VOG=2,OV, 'O=200flA

(Note 3)

'G
9fs

Gate Current (Note 1)
LOommon·t)ource Forward

-3.5

-3.5

1,500'

1,000

500

-3.5

1500

Transconductance(Note 2)
90S

Common Source Output

1

35

10

2.5

4

4

4

4

1

1

1

1

5

5

5

10

j.lmho

f=1 kHz
VOS=20V, VGS=O

Conductance

elas

Common-Source Input
Capacitance

Grss

Common-Source Reverse

pF

1=1 MHz

Transfer Capacitance

in

Equivalent Short-Circuit

nV VOS=10V, VGS=O

-/Hz

Input Noise Voltage

NOTES: 1. Approximately doubles for every 10·C increase in TA.
2. Pulse test duration = 2ms.

1·80

f=l kHz

J201·J204

II

J204
PARAMETERS

MIN

TYP

Gate Reverse Current
IGSS
S
T
A
T
I
C

(Note 2)
Gate-Source Cutoff

VGS(off)

Voltage
Gate-Source Breakdown

BV GSS

Voltage
Saturation Drain Current

loss

(Note 3)
Gate Current (Note 1)

IG

Common-Source Forward
gfs

Transconductance (Note 2)

0

y

Common Source Output
gos

Conductance

N

A
M
I
C

Common-Source Input

C iss

Capacitance
Common-Source Reverse

C rss

Transfer Capacitance
Equivalent Short-Circuit

en

Input Noise Voltage

-0.5

MAX

UNIT

-100

pA

VOS = 0, VGS = -20V

-2.0

V

VOS = 20V, 10 = 10nA

-25

TEST CONDITIONS

Vos = 0, IG

= - "A
=0

1.2

rnA

VOS = 20V, VGS

-3.5

pA

VOG = 20V, 10 200"A

1500
f=1kHz

"mho
2.5
VOS = 20V, VGS = 0

4
pF

f= 1MHz

1
10

f>-

1-81

nV

-Hz

VOS = 10V, VGS = 0

f= 1kHz

II

J308·J310

N·ChanneIJFET
FEATURES
•
•
•
•
•

PIN
CONFIGURATION

Industry Standard Part in Low Cost Plastic Package
High Power Gain
Low Noise
Dynamic Range Greater than 100 dB
Easily Matched to 75[1 Input

CHIP
TOPOGRAPHY

TO-92

r-'

6;;6- - -I

-----r
o

'

5021

APPLICATIONS
• VHF/UHF Amplifiers
• Oscillators
• Mixers

o

OOJ~

T'r'P

OOJ~

001~ x aa2~

)PlAUS

G

ABSOLUTE MAXIMUM RATINGS
(T A = 25° C unless otherwise noted)
Drain-Gate Voltage ............................. -25V
Drain-Source Voltage ........................... -25V
Continuous Forward Gate Current ............. -10 mA
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature ,Soldering. 10 seC.i ........ +300°C
Power Dissipation ........................... 300 mW
Derate above 25° C .................. 1.7 mWr C

ORDERING INFORMATION*

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25°C unless otherwise noted
PARAMETER
BVGSS Gate-Source Breakdown
Voltage
Gate Reverse .Current
IGSSR
TA
VGS{off)

loss
VGS(fI
gls
gos
gIg
gog
Cgd
Cgs
en

Re{Vfs)
Re(Vlg)
Re{Vis)
Re(vos)
Gpg
NF
Gpg
NF

Gate-Source Cutoff
Voltage
Saturation Drain
Current (Note 1)
Gate-Source Forward
Voltage
Common-Source Forward
Transconductance
Common-Source
Output Conductance
Common-Gate Forward
Transconductance
Common Gate Output
Conductance
Gate-Drain
Capacitance
Gate-Source
Capacitance
Equivalent Short-Circuit
Input Noise Voltage
Common-Source Forward
Transconductance
Common-Gate Input
Conductance
Common-Source Input
Conductance
Common-Source Output
Conductance
Common-Gate Power
Gain at Noise Match
'Noise Figure
Common-Gate Power
Gain at. Noise Match
Noise Figure

MIN
25

J308
TYP

MAX

MIN
25

J309
TYP

MAX

MIN
25

J310
TYP

MAX

UNIT
V

TEST CONDITIONS
lpA. Vos a

IG

1.0

1.0
1.0
-<3.5

1.0

1.0
1.0
4.0

2.0

1.0
1.0
-<3.5

nA
pA
V

VGS - 15V,
Vos ~ 0
VOS -10V, 10 - lnA

12

60

12

30

24

60

mA

Vos - 10V, VGS - 0

1.0

V

Vos - 0, IG - 1 mA

18,00C

.'

125'C

.'

1.0

1.0

20,000 10,000

8,000

20,000 8,000

200
13,000

_.

1S()

200

200
13,000

12,000

-

150

150

.;.-

pmhos

1.8

2.5

1.8

2.5

1.8

2.5

4.3

5.0

4.3

5.0

4.3

5.0

10

10

10

12

12

12

14

14

14

0.4

0.4

0.4

0.15

0.15

0.15

16

16

16

1.5
11

1.5
11

1.5
11

2.7

2.7

VoS

pF

Vos
VGS

nV

Vos

.,fHZ

~

10V,

10 ~ 10mA

~
~

0,
-10V
10V,

10 ~ 10 mA

f

~

1 kHz

f

~

1 MHz

f

~

100 Hz

,
mmho
f~

Vos
10

i

2.7

NOTE: 1. Pulse test PW 300 pS, duty cycle <: 3%.

1-82

~

105 MHz

10V,
10mA

~

dB

~~ 450 MHz

LM114/H,LM114A/AH
Monolithic Dual NPN
Transistor
GENERAL DESCRIPTION

FEATURES

These devices contain a pair of junction - isolated NPN transistors fabricated on a single silicon substrate. This monolithic
structure makes possible extremely tight parameter matching
at low cost. Further, advanced processing techniques yield
exceptionally high current gains at low collector currents,
virtual elimination of "popcorn noise," low leakages and
improved long-term stability.

•
•
•
•
•
•

Low offset voltage
Low drift
High current gain
Tight beta match
High breakdown voltage
Matching guaranteed over a OV to 45V collector-base voltage range

•

CMRR > 100 dB

Although designed primarily for high breakdown voltage and
exceptional DC characteristics, these transistors have surprisingly good high-frequency performance. The gain-bandwidth
product is 300M Hz with 1mA collector current and 5V collector- base voltage and 22M Hz with 1OJ.lA collector current.
Typical collector-base capacitance is only 1.6 pF at 5V.

PIN ,
CONFIGURATION

4003

r--~~--1

023;1;1

0:2 TYP 2 PLACES
.9_Q4....§ _OQ4_~

:0210

I

Collector-Base Voltage (1) .............................. 45V
Collector-Emitter Voltage (1) ............................ 45V
Collector-Collector Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 45V
Emitter-Base Voltage (1) ................................. 6V
Collector Current (1) ................................. 20mA
Storage Temperature Range ............... _65° C to +200° C
Operating Temperature Range ............. -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ............... +300°C
Power Dissipation .................................. 800mW
Derate above 25° C ............................... 14mW/o C

003S •. 0035
BASE "'2 TVP 2 PLACES

~~

8ASE =1-.

DIAMETER

-- EMITTER:;2

EMITTER :<1

TVP 2 PLACES

.

0040

0030
DIAMETER

ORDERING INFORMATION*
WAFER
DICE
lO·71
lO·78
LM114
LM114H LM114/W LM1141D
LM114A LM114AH

(Note 2)

·When ordering wafer/dice refer to Appendix B·23.

MAXIMUM LIMITS
LMl14, H
LMl14A, AH

PARAMETER

m~·~1

-rC;;;:~;~;~~'~-'_-ISOLATION
I •
COLLECTOR

25°C unless otherwise noted)

ELECTRICAL CHARACTERISTICS

CHIP
TOPOGRAPHY

TO-71
TO-78

ABSOLUTE MAXIMUM RATINGS
(TA =

II

UNITS

CONDITIONS

Offset Voltage

0.5

2.0

mV

1.A '" Ie '" 100.A

Offset Current

2.0
0.5

10

nA

Ie = 1O.A
Ie - 1.A

Bias Current

20

40

nA

Ie
Ie

= 10.A
= 1~

OV

:$

3.0
Offset Voltage Change

0.2

1.5

mV

Offset Current Change

1.0

4.0

nA

Offset Voltage Drift

2.0

10

.V/·C

Offset Current

12

50

Bias Current

60

150

nA

12S·C

10
10

50
50

pA
nA

12S·C

50
50

200
200

pA
nA

300

pA

12SoC

100'
100

300

nA

Ves s VMAX, Ie

-------

=

10ltA

I
-55·C '" TA ", + 125", Ie

Coliector·Base Leakage Current

I

TA

~

Collector-Emitter Leakage
Current

I

TA

~

Collector-Collector Leakage
Current

I

TA

~

Vee

= VMAX

VeE

= VMAX, VEe = OV

Vee

= VMAX

= 10.A

Note 1: Per transistor.

Note 2: These specifications apply for T A
30V.

=

+25° C and OV

<;

VeB

<;

VMAX, unless otherwise specified. For the LM114 and LM114A, VMAX

1-83

=

M116
Diode Protected
N-ChannelEnhancement
Mode MOS
, FliT
FEATURES

II

• Low IGSS
• Integrated Zener Clamp for Gate Protection

PIN
CONFIGURATION

DEVICE
SCHEMATIC
1

tL:

TO-72

ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
Drain to Source Voltage. . . . . . . . . . . . . . . . . . . . . . . . .. 30V
Gate to Drain Voltage ................. '.' . . . . . . . .. 30V
Drain Current ................................. 50 mA
Gate Zener Current .......................... ±0.1 mA
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
Power Dissipation ........................... 300 mW
Derate above 25°C ...............•. 2.2 mW/oC

4

CHIP
TOPOGRAPHY
1003

IIIOH: SU8STRAH
IS QOOY

ORDERING INFORMATION*

'When ordering wafer/dice refer to Appendix 8·23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
PARAMETER

MIN

r---wo

rOS(onl

Drain Source ON Resistance

VGS(th)
BVDSS

Gate Threshold Voltage
Drain-Source Breakdown Voltage

30

BVSDS

Source-Drain Breakdown Voltage

30

BVGBS

Gate-Body Breakdown Voltage
Drain Cutoff Current

30

ID(OFF)
IS(OFF)
IGSS
Cgs
Cgd
Cdb
Ciss

Ml16
MAX
100

1

Source Cutoff Current
Gate-Body Leakage
Gate-Source
Gate-Drain Capacitance
Drain-Body Capacitance

UNITS

TEST CONDITIONS

n

VGS- 20 V, ID - lOOIJA, VBS-O
VGS = 10 V, ID - 100 /lA, VBS - 0
VGS - VDS, ID - 10 /lA, VBS - 0

V

ID = 1 /lA. VGS, = V~=O

5

IS = 1 /lA, VGJ2 = VB..o. = 0
60
10
10

nA

100
2.5

pA

VGS ~ 20 V,VDS- VBS - 0
VGB- VDB - VSB - 0, f - 1 MHz
Body Guarded

pF

VGB - 0, VDB -- 10 V, f

VSD = 20 V, VGD= VBD = 0

2.5
7

Input Capacitance

10

1-84

IG = 10/lA, VSB= VDB= 0
VDS= 20 V, VGS= V~ = 0

1 MHz

VGB - 0, VDB - 10 V, VBS - 0
f = 1 MHz

U200·U202

N·ChanneIJFET
PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-IS

FEATURES
• Low Insertion Loss
• Good OFF Isolation
APPLICATIONS
• Analog Switches
• Commutators
• Choppers

ORDERING INFORMATION·
TO·18

WAFER

DICE

U200
U201
U202

U200/W
U201/W
U202/W

U200/D
U201/D
U2021D

·When ordering wafer/dice refer \0 Appendix B-23.

ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ........................................ -30V
Gate Current ........................................................... 50 mA
Storage Temperature Range ................................. ,. -65° C to +200° C
Operating Temperature Range ................................. -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) .................................. +300°C
Total Device Dissipation ................................................. 1.BW
Derate above 25°C ............................................ 10 mW;oC

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)

Min

IGSS

Gate Reverse Current

U201

U200

Parameter

U202
Unit

Max

Min

Max

Min

-1

-1

-1

nA

-1

-1

-1

jJ.A

VGSS = 20 V, VOS = 0

I TF 150°C

BVGSS

Gate-Source Breakdown Voltage

-30

-30

-30

VGS(off)

Gate-Source Cutoff Voltage

-0.5

-3 -1.5

-5 -3.5

10(off)

Drain Cutoff Current

lOSS

Saturation Drain Current (Note 1)

rds(on)

Drain-Source ON Resistance

1

I TA= 150°C

Common-Source Input
Ciss
C rss

Capacitance (Note 1)

1

1
3

25

75

V

-10
1

1
15

30

IG = 1jJ.A, VOS = 0
VOS = 20 V, 10 = 10 nA

nA

1

jJ.A

150

mA

VOS = 20 V, VGS = 0

75

50 ohm

VGS = 0, 10 = 0

30

30

30

VOS = 20 V, VGS = 0

8

NOTE 1: Pulse test required, pulsewidth = 300 jJ.sec, duty cycle ,,3%.

1-85

8

f = 1 kHz

f = 1 MHz

pF

8

.-

VOS=10V,VGS= -12V

150

Common Source Reverse Transfer
Capacitance

Test Conditions

Max

VOS=O,VGS= -12V

.

....

~ U,~.··
·,D~unIb
~
IN.I Ul5~

U231·U235
Monolithic Dual'N·ChanneIJFET
PIN
CONFIGURATION

FEATURES
• Good Matching Characteristics

CHIP
TOPOGRAPHY
6037

r-'OZl,~

~

APPLICATIONS

II

• Differential Amplifiers
• Low and Maximum Frequency Amplifiers

5'11]-.
-._~
I.
,;~' -_~l

.017

ABSOLUTE MAXIMUM RATINGS

(T A = 25° C unless otherwise noted)
Gate-Source or Gate-Drain Voltage (Note 1) •..... -50V
Gate Current (Note 1) .........•............... 50 mA
Storage Temperature Range .•........ -65° C to +200° C
Operating Temperature Range ......•. -55° C to +150° C
Load Temperature (Soldering, 10 sec.) ., ...... +300°C
Power Dissipation ........................... 300 mW
Derate above 25°C .................. 1.7mWfOC

D,

G,
ALL BONO PADS ARE 4

ELECTRICAL CHARACTERISTICS
Parameter

Min

Gate Reverse Current

ITA

Max
-100

Unit
pA

-{i00

nA

-4.5
-4.0
-50

V

Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage
Gate-Source Voltage

I~

Gate Operating Current

loss

Saturation Drain Current I Note 21

gts

Common-Source Forward Transconductance INote 11

9ts
90S
90S
Ciss

Common-Source
Common-Source
Common-Source
Common-Source

erss

Common-Source Reverse Transfer Capacitance

2

en

Equivalent Short Circuit Input Noise Voltage

80

.-50
-0.5
-0.3

ITA

= 125°C
0.5
1000
1000
600

Forward Transconductance INote 11
Output Capacitance
Output Conductance
Input Capacitance

-250
5.0
3000

1600
35
10
6

Differential Gate Current
Saturation Drain Current
Match (Note 21
Differential Gate-Source
Voltage

~IVGS1-VGS21

Gate-Source Voltage
Differential Drift (Note 3)

~T

,

(gtsl-9Is21
~
Igosl-90s21

Transconductance Match
(Note 2)
Differential Output
Conductance

= -30V, Vos = a

IG - l"A, Vos - a
Vos ~ 20V, 10 - 1 nA

pA

VOG - 20V, 10 - 200"A

nA
rnA

Vos

= 20V, VGS = 0

Vos

= 20V, VGS = 0

f - 1 kHz
"mho

f = 100 MHz
VOG = 20V, 10 = 200"A
f = 1 kHz
VoS - 20V, VGS- 0
VOG - 20V, 10 - 200"A

pF
nV

IG1-IG21
IIOSS1-losS21
10SS1
1VGS1-VGS2 I

Test Conditions
VGS

= 150°C

BVGSS
VGS(ottl
VGS

Matching C"aracteristics

4 MIL.

'When ordering wafer/dice refer to Appendix B-23.

TEST CONDITIONS: 25°C unless otherwise noted.

IGSSR

I(

ORDERING INFORMATION*

f= 1 MHz
Vos = 20V, VGS

=0

v'Hz'

U231
Max
10
5

U232
Max
10
5

U233
Max
10
5

U234
Max
10
10

5

10

15

20

25

10

25

50

75

100

10

3

25
5

50
5

75
10

100
15

%

5

5

5

5

5

"mho

U235
Max
Unit
10
' nA
15
%

f= 100 Hz

Test Conditions
VOG = 20V, 10 = 200"AT125° C
Vos - 20V, VGS = 0

mV

"V;oC

TA = 25°C
TB = 125°C
TA =-55°C
VOG = 20V, 10 = 200"A TB = 25°C
f

NOTES:
, 1. Per transistor.
2. Pulse test required, pulse width = 300 ;"s, duty cycle :'0 3%.
3. Measured at end paints, TA and Ta.

1-86

= 1 kHz

U257
Monolithic Dual
N·ChanneIJFET
FEATURES
• 9fs > 5000 !Lmho from DC to 100 MHz

PIN
CONFIGURATION

• Matched VGS, 9fs and 90S

TO-99

CHIP
TOPOGRAPHY
6022

D

ABSOLUTE MAXIMUM RATINGS
(T A = 25° C unless otherwise noted)
Gate-Drain or Gate-Source Voltage (Note 1) ...... -25V
Gate Current (Note 1 i ......................... 50 mA
Storage Temperature Range .......... -65° C to +200° C
Operating Temperature Range ........ -55°C to +150°C
Lead Temperature (Soldering, 10 sec.) ........ +300°C
ONE SIDE
Power Dissipation. . . . . . . . . . . . .. 250 mW

0,

0,

$,

BOTH SIDES
500 mW

Derate above 25° C ......... 3.8 mW/ o C

7.7 mW/o C

ORDERING INFORMATION·

'When ordering wafer/dice refer to Appendix B·23.

ELECTRICAL CHARACTERISTICS !25°C unless otherwise noted)
PARAMETER
IGSSR

Gate Reverse Current

BVGSS
VGS(oftl

Gate·Source Breakdown Voltage
Gate·Source Cutoff Voltage
Saturation Drain Current INote 2)

lOSS
9ls
9ls
gas
go 55
Ciss
Crss
en
10SSl
IOSS2
IVGS1- VGS21
9lsl
9ls2
Igosl-gos21

MIN
~

TA - 150"C
-25
-1
5
5000
5000

Common-Source Forward Transconductance

Common-Source Forward Transconductance
Common-Source Output Conductance
Common-Source Output Conductance

Common-Source Input Capacitance
Common-Source Reverse Transfer Capacitance

MAX
-100
-250
-5
40
10,000
10,000
150
150
5
1.2

UNIT
pA
nA

V
mA

I1 mho

pF

TEST CONDITIONS

VGS=15V.VOS=0
IG = -1 !LA, VOS = 0
VOS - 10 V, 10 - 1 nA
VOS-l0V, VGS-O
VOS-l0V,10-5mA
VOG-l0V,10-5mA
VOS-l0V,10-5mA
VOG=10V,10=5mA

1- 1 kHz
1-100 MHz
1- 1 kHz
l-l00MHz
1= 1 MHz

nV

Equivalent Input Noise Voltage

30

Drain Current Ratio at Zero Gate Voltage' INote 2)

0.85

Differential Gate-Source Voltage

100

Transconductance Ratio

0.85

Differential Output Conductance

1. Per'transistor.

2. Pulse test required, pulse width = 3001'5, duty cycle';;; 3%.

1-87

1= 10 kHz
VOS = 10 V, VGS = 0

mV

1
20

NOTES:

~

1

VOG=10V,10=5mA
I1mho

1= 1 kHz

II

U304·U306

P·ChanneIJFET
PIN
CONFIGURATION

FEATURES
• Low ON Resistance
10(011) <500 pA
I . Switches directly from T2L Logic (U306)

TO-IB

•

APPLICATIONS
• Analog Switches'
• Commutators
.. Choppers

o

CHIP
TOPOGRAPHY (Note 1)

ABSOLUTE MAXIMUM RATINGS
(TA =

G,C

25°C unless otherwise noted)

01'1'48~

--

Gate-Drain or Gate-Source Voltage (Note 1) .......... 30V
Gate Current .. '" ................................ 50 mA
Storage Temperature Range ..••........ -65° C to +200° C
Operating Temperature Range .......... -55° C to +150° C
Lead Temperature (Soldering. 10 sec.) ............ 300°C
Power Dissipation ...........•........•........ 350 mW
Derate above 25°G ....•.............. 2.8 mW/oC

023'5841--

'I

5508

I'

"'1'," • I I
OOJ510808~~145'r7)
I
002fi~0635j[)

I'

I

~I

s

1/

0" , " " " ,
,

I
I

003!J,oa89!

::;;, ::1::
I

0031l0939i

0027: Ob851
NOH

SUBSl RA H IS GA

r~

ORDERING INFORMATION·
TO·18

DICE

WAFER

~-"U<-"3""04,,---+---,U,<,3,,,,O.:::c4/~W__
U3041D
~-"Uo.:3o=.05=--+---,U=3JJ2.'!'L_ _ __ U3051D

U306

ELECTRICAL CHARACTERISTICS

I

IGSSR

Gate Reverse Current

BVGSS
VGS(Ofl)

TA=150°C
Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage

U304
Min Max
500

U305
Min Max
500

U306
Min Max Unit
500 pA

Drain-Source ON Voltage

IDSS

Saturation Drain Current (Note 2)

ID(oll)

Drain Cutoff Current

rDS(on)
rds(on)
Ciss

TA = 150°C
Static Drain-Source ON Resistance
Drain-Source ON Resistance
Common-Source Input Capacitance

erss

td(on)

I

Test Conditions
VGS = 20V, VDS =

1.0

1.0
30
5

10

30
3

6

1.0
30
1

"A
IG 1 "A, VDS
15V,ID
VDS

4
V

VDS(on)

-1.3
30

90
--500

-IVGsl-VGs21
.:>T

25

Gate-Source Cutoff
Voltage
Gate-Source
Voltage lonl
Saturation Drain Current
(Note 31

Operationg

ItA

Gate Current (Note 2)
Gate-Gate Breakdown
Voltage
Common-Source Forward
Transconductance( Note 31
Common-Source Output
Conductance
Common-Source Forward
Transconductance
Common-Source Output
Conductance
Common-Source Input
CapaCitance
Common-Source Reverse
Transfer CapaCitance
Equivalent Short-Circuit
Input Noise Voltage
Common-Mode Rejection
Ratio (Note 41

Differential Gate-Source
Vbltage
Gate-Source Vottage Differentiat Drift (Note 5)

'When ordering wafer/dice refer to Appendix

U401
U402
U403
U404
U405
U406
Min Ma. Min Ma. Min Ma. Min Ma. Min Ma. Min Ma.
50
50
50
-50
-50
-50

Gate-Source Breakdown
Voltage
Gate Reverse Current
(Note 2)

5

2,5

25
,5

10,0 0,5
-15
-10

125°C
±50

2,5

25
,5

10,0 0,5
15
10

±50

2,5

25
,5

2,3

2,3

2,3
0,5

©7.:. -c~J

0,

ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: 25° unless otherwise noted,
Parameters

,

2,5

25
,5

2,3

2,5

25
,5

2,3

Unit
V
pA

2,5
2,3

8·23.

Test Conditions
Vos - 0, IG - -lpA
Vos - 0, VGS- 30V
Vos - 15V, 10 - 1 nA

V

VOG - 15V, 10 - 200pA

10,0 0,5

10,0 0,5

10,0 0,5

10,0

mA

Vos

-15
10

-15
10

-15
10

-15
10

pA
nA
V

VOG - 15V,
10 ~ 200pA
Vos - 0, VGS - 0, IG - ±1pA

±50

±50

±50

±50

~

10V, VGS

~

0

2000 7000 2000 7000 2000 7000 2000 7000 2000 7000 2000 7000
20

20

20

20

20

1000 1600 1000 1600 1000 1600 1000 1600 1000 1600 1000 1600
2,0

,

2,0

2,0

2,0

2,0

8,0

8,0

8,0

8,0

8,0

3,0

3,0

3,0

3,0

3,0

3,0

20

20

20

20
95

20
95

95

~

10V,
0

90

pF

1 kHz

f

~

1 kHz

f

~

1 MHz

nV

dB

Vos 15V,
f ~ 10 Hz
VGS ~ 0
VOG - 10,to 20V, 10 - 200pA

mV

VOG - 10V, 10 - 200pA

5

10

10

15

20

40

10

25

25

40

80 "V/oC VOG
10V,
10 ~ 200pA

1

,WDD
5, CMRR = 2010910 [ t;, IVGS,-VGS2iJ' t;,VDD = 10 V,

1-90

~

VOG ~ 15V,
10 ~ 200pA

10

NOTES:
1, Per transistor.
2, Approximately doubles for every 10° C increase in TA,
3, Pulse test duration = 300 ILsec; duty cycle oS 3%,
4,Measured at end points, TA and Ta.

f

/lmho

VHz

95

~

2,0

8,0

20

Vos
VGS

20

TA -55°C,
TB ~ +25°C,
10 ~ 200pA
Tc ~ +125°C

U1897·U1899

N·ChanneIJFET
FEATURES

• Low Insertion Loss
• No Error or Offset Voltage Generated
by Closed Switch

PIN
CONFIGURATION

CHIP
TOPOGRAPHY

TO-92

5001

II

APPLICATIONS

Analog Switches, Choppers
ABSOLUTE MAXIMUM RATINGS
(TA

= 25°C unless otherwise noted)

Gate-Drain or Gate-Source Voltage ..•... -40V
Forward Gate Current ................. 10 mA
Storage Temperature Range .. -65° C to +200° C
Operating Temperature Range .. -55°C to +150°C
Lead Temperature (Soldering, 10 sec) ... +300° C
Power Dissipation ................... 350 mW
Derate above 25° C .......... 3.5 mW/o C

S

D

G

ORDERING INFORMATION*
TO-92
U1897
U1898
U1899

ELECTRICAL CHARACTERISTICS

TO-92-18

WAFER

DICE

U1897-18
U1898-18

U1897/W
U1898/W
U1899/W

U1897/D
U1898/D

U1899-18

U1899/D

TEST CONDITIONS: 25°C unless otherwise noted
'When ordering wafer/dice refer to Appendix 8-23.
U1897
U1898
U1899
MIN MAX MIN MAX MIN MAX UNIT
TEST CONDITIONS
-40
-4C
-40
V
IG= -l~A, YoS=O
-400
-400
-400
YGS= -20V, VOS=O
200
200
200
VOG=20V,IS-0
200
200
200 pA VSG 2OV,10=0
200
~UIJ
VoS-20V, YGS= 12V (U1897)
10
10
10 nA VGS= -8V (U1898) VGS= -6Y (U1899)
5.0
10
2.0 -7.0 -1.0 -5.0
V
VOS-20V, 10-1 na
30
15
8.0
mA VOS 20V, YGS-O

IGSSR
lOGO
ISGO

PARAMETERS
Gate·Source Breakdown Voltage
Gate Reverse Current
Drain-Gate Leakage Current
Source-Gate Leakage Current

lo(off)

Drain Cutoff Current

VGS(off)
OSS

Gate·Source Cutoff Voltage
:saturallon ura n Current
(Note 1)

VoS{on)

oraln·Source ON Voltage

0.2

0.2

0.2

Y

VGS=O,10=6.6mA (U1897)
'0 = 4.0mA (U1896) 10 = 2.5mA (U1899)

roS(on)

Static Oral n·Source ON
Resistance
oraln·Gate Capacitance
Source·Gate Capacitance
Common·Source Input
Capacitance

30

50

80

0

10-~mA, YGS-O

5
5
16

5
5
16

5
5
16

BVGSS

ICdg
Csg
ICiss
Crss
td(on)
tr

toff

1 TA=85'C

.

Common·Source Reverse
Transfer Capacitance
Turn ON Delay Time
Rise Time

Turn OFF Time

"00

VoG-2OV,IS-0
VSG = 20V,. 10=0
pF

f=l MHz
VoS=20V, YGS=O

3.5

3.5

3.5

15
10

15
20

20
40

60

40

80

Switching Time Test Conditions
ns
VOO
YGS(on)
VGS(off)
RL
lo(on)

NOTE: 1. Pulse test pulsewldth =3OO,..s; duty cycle<3%

1-91

U1897
3V
0

U1898
3V
0

U1899
3V
0

-12V
425n
B.6mA

-8V
770n
4mA

-6Y
1120n
2.5mA

I.,'

VCA2N/3P/4N/7N

VoltageCont~olled

Resistors
APPLICATIONS

'. · Small Signal Attenuators

CHIP
TOPOGRAPHY

• Filters
• Amplifier Gain Control
• Oscillator Amplitude Control

.

001~

5001

:I

---- -r-' .

ABSOLUTE MAXIMUM RATINGS

CONFIGURATIONS
PI.

I P.6~~~~el\

(N_6~~~2nel)

~

_

l----~::-I

,c,,,
5508

"E.' •

°92~

0017

0025

I(

:~:

VCR7N

5007

'0015

T

•

::S~RATf.

•

ISCAff

~~~ II =~~

::~ FUll R

fSOuRCE I

-]

011'.

.

j:::;;

501014N).....
..

~lltl1l~r"~

.~:::.
I [

00"

01

0025

003&11,0035

r--~j~ll-

VCR4N

:;~:

1_

~:

r-

r. JjO.u.l80'

-rSOURCE 1

: - -_ _

G

-M1311.

-J..
0061

o~,

mI

. -__D_e_ra_t_e_a_b_ov_e_2_5_0_C-,-'_'._._._
.._._._
. ..;..._2_m_W_I_0_C_ _ _--'

TO-18

00ll INOTf ,SUBSHIATEISGATE

1.
)

"'.~

"..

----j'

_--j 00II _

0011510RA''''I,

(TA = 25°C unless otherwise noted)
Gate-Drain or Gate-Source Voltage ....... 15V
Gate Current .......................... 10 mA
Storage Temperature Range .. -65° C to +200° C
Operating Temperature Range· ·-55° C to +150° C
Lead Temperature (Soldering, 10 sec.) ... +300° C
Power Dissipation •.................. ·.300 mW

=-h

VCR2N
fULL RADIUS

0027

."

II.!J
In.. l=

O"'x, ' "
O

111135 .00,.

FUll R

~

-

.

~..

'.'::~

.

,NOH: -SUBSTRA.TE
IS GATE

011

0"iS

NOTE' SUBSTRATE 15 GATE

ORDERING INFORMATION*
TO·18
VCR2N
VCR4N

D

G

s

TO·72

VCR3P
VCR7N

WAFER
VCR2N/W
VCR4N/W
VCR3P/W
VCR7N/W

DICE
VCR2N/D
VCR4N/D
VCR3P/D
VCR7N/D

'When ordering wafer/dice refer to Appendix 8',23.

ELECTRICAL CHARACTERISTICS (25°C unless otherwise noted)
N-Channel VCR FETs

S lass
T'
A BVGSS
T VaS(off)
rds(on)
D Cdgo
y Csoo

16

Parameter
Gate Reverse Current
Gate.-Source Breakdown Voltage
Gate-Sourc~' Cutoff Voltage
Drain Source ON Resistance
Drain-Gate Capacitance
Source-Gate Capacitance

VCR2N
Min Max
-5
-15
-7
-3.5
20
60
7.5
7.5

VCR4N
VCR7N
Min Max Min Max Unit
Test Conditions
-0.1 nA Vas - -15V, Vos - 0
-0.2
-15
-15
IG - -lilA, Vos - 0
V
-7
-5
-3.5
-2.5
10 - lilA, Vos -1~
, - 1 kHz
200 600 4,000 8,000 n Vas - 0,10 - 0
3
1.5 pF Vao - ~10V, Is - 0 , = 1 MHz
3
1.5
Vas - -10V,lo - 0

P-Channel VCR FETs
S
T

A

T
I

C
D

y

IGSS
BVass
VaS(off)
rds(on)
Cdgo
Csgo

Parameter
Gate Reverse Current
Gate-Source Breakdown Voltage
Gate-Source Cutoff Voltage
Drain-Source ON Resistance
Drain-Gate CapaCitance
Source-Gate Capacitance

VCR3P
20
15
3.5
7
70
200
6
6

1·92

Unit
nA
V
f1

pF

Vas
IG 10 Vas
VGO
Vas

'Test Conditions
- 15V, Vos - 0
lilA, Vos - 0
-lilA, Vos - -1OY
f - 1 kHz
- 0,10 - 0
- 10V, Is- 0
f = 1 MHz
- 10V, 10 - 0

VCR2N/3P/4N/7N
JFETS AS VOLTAGE CONTROLLED RESISTORS
The voltage controlled resistor is a junction field effect tran·
sistor whose drain to source ON resistance is controlled by
gate to source voltage.
The gate control terminal is high impedance thereby allow·
ing negligible control current. The gate voltage is zero for
minimum resistance, and increases as the gate voltage ap·
proaches the pinch·off voltage.
This VCR is intended for use on applications using low level
AC signals. Figure 1 shows the output characteristics, with
an enlarged graph of VDS = 0 for AC signals with no DC
component. Operation is in the first and third quadrants; the
device will operate In the first quadrant only If a constant
current is applied to the drain and the Input signal level Is
kept low.

Figure 1 also shows that certain combinations of gate con·
trol voltage and signal levels will cause resistance modula·
tion. This distortion may be improved by introducing local
feedback as shown in figure 2 for best frequency response
and impedance levels; eliminating the feedback capacitor
will require the gate control voltage to be double for the
same ON resistance. The resistor values should be equal,
and about 100kO.
Best gate control voltage for best linearity is up to about
O.8VPK; ON resistance increases rapidly beyond this point.

30

VGS =

20

VGS

OV

= -2V

VGS = -4V

10

VGS = -6V
vGS = -8V

3
//

/

v HI---h'-~~~~ v
/

/

/

5

6

9

10

JFET OUTPUT CHARACTERISTICS

//

mA
VDS

8

VDS·VOLTS

JFET OUTPUT CHARACTERISTICS
ENLARGED AROUND

7

/

//
/

4

=0

FIGURE 1

R

R
GATE CONTROL

FIGURE 2

1·93

C

II

perigherals

Memory
Page
NMOS ROMs
IM7332
IM7364

2·18
2·21

IM64 2/3
82C43

Gate Arrays
IGC10000

CMOS EPROMs
IM6653/4

2·11

2·3
2·24

2·28

DIGITAL
ROMs
Organization

Max Access Time Insl

4096 x 8
IM7332

300

8192 x 8
IM7364

350

Temp Range'

No. Pins

PIckage'

80

24

J.P

C

150

24

J.P

C

100

MaximAl

EPROMs
Organization
1024 x 4
IM6653
IM6653A
512 x 8
IM6654
IM6654A

Max Access
Time Insl

Vee
IVI

Icc Max ImAI
Operating

Icc Max I"AI
Standby

No. Pins

550
300

5
10

'6
12

140
140

24
24

I.M
I.M

550
300

5
10

6
12

140
140

24
24

I.M
I.M

Package'

Temp Range

PERIPHERAL
IM8048 Peripheral
IM82C43 - CMOS 110 Expander

'Package and Temperature Key
F-Flatpack I
C-Commercial, O'C to '70'C
I-Industrial. -40'C to +85'C
J--Ceramic Dual In-Line
P-Plastic Dual In-Line
M-Military. -55'C to +125"C
D-Ceramic Side Brazed (Not Recommended for High Volume)

UARTS
Part Number
IM6402
IM6402A
IM6402-1

Max.
Clock
Frequency

XTAl
Frequency

1.0 MHz
4.0 MHz

V Supply

ICC Max.

5.0
4-11

1.2 mA
9.0 mA
1.9 mA
3.7 mA
13.0 mA
5.5 mA

IM6403

2.0 MHz
2.46 MHz

IM6403A
IM6403-1

6.0 MHz
3.58 MHz

3.58 MHz

5.0
5. 0
4-11
5.0

Part Number

Oelay

Input Nand
Gate Equivalent

Cells

Vce

IGC10408
IGC10756
IGCl1500

6 ns
6 ns
6 ns
6 ns

34

3-9V

2.46 MHz
6.0 MHz

GATE ARRAYS

IGC12001

408
756

I/O

44
62

1500
2001

70

2-2

3-9V
3·9V
3·9V

IM6402/1M6403
Universal Asynchronous
Receiver Transmitter
(UART)
FEATURES

GENERAL DESCRIPTION

•

Low Power -

•

Operation Up to 4MHz Clock (lM6402A)

•

Programmable Word Length. Stop Bits and Parity

•

Automatic Data Formatting and Status Generation

•

Compatible with Industry Standard UART's
(IM6402)

•

On-Chip Oscillator with External Crystal
(IM6403)

•

Operating Voltage IM6402-1 103-1: 5V
IM6402A/03A: 4-11 V
IM6402l03: 5V

PIN CONFIGURATION
Vee

transmissio. n,. parity, and stop bits. The transmitter converts
parallel data into serial form and automatically adds start,
parity, and stop bits.
The data word length can be 5, 6, 7 or 8 bits. Parity may be odd
or even, and parity checking and generation can be inhibited.
The stop bits may be one or two (or one and one-half when
transmitting 5 bit code). Serial data format is shown in
Figure 6.
The IM6402 and IM6403 can be used in a wide range of
applications including modems, printers, peripherals and
remote data acquisition systems. CMOS/LSI technology
permits clock frequencies up to 4.0MHz (250K Baud), an
improvement of 10 to 1 over previous PMOS UART designs.
Power requirements, by comparison, are reduced from
670mW to 10mW. Status logic increases flexibility and
simplifies the user interface.

(outline dwg DL, PL)

,.
EPE
CLSl
CLS2
SBS

2
GND
RRD
RBR8
RBR7
RBR6
RBR5
RBR4
ABR3
RBR2
RBAl
PE

The IM6402 and IM6403 are CMOS/LSI UART's for
interfacing computers or microprocessors to asynchronous
serial data channels. The receiver converts serial start, data,
parity and stop bits to parallel data verifying proper code

Less Than 1 OmW Typ. at 2MHz

5
6

TABLE 1

PIN

CRL
TBRS

9
11
12

13

FE

27

DE
SED

26
25
2.
23

"fBRL

22
21

TBRE""
MR

ORR

2

TBR7
TBR6
TBR5
TBR4
TBR3
TBR2

10

17

IM6402 IM6403 w/XTAL
N/C

RRC

Tri-State
22 Tri-State
40
19

TRC

Divide Control

Divide Control

XTAL

External Clock Input
Always Active
Always Active

Always Active
Always Active
XTAL

The IM6402 differs from the IM6403 in the use of five device
pins as indicated in Table 1 and Figure 1.

IM6403 w!EXT CLOCK

ORDERING INFORMATION

GNo

TBRl
TRD
TRE

*500 Table 1

FUNCTIONAL BLOCK DIAGRAM

l

TRE r - - - - - - - - - - - - - - - - - - - - - -

* TBRE I

-+-I
TRC --+-

TBAl

TRANSMITTER

TIMING

CO~~~Ol

L STOP
t

I

PtoR~TcY

ORDER CODE

IM8402·1/03·1

IM8402A103A

IM8402I03

PLASTIC PKG

IM6402·1/03·1IPL

IM6402/03·AIPL

IM6402/03-IPL

CERAMIC PKG

IM6402·1/03-1IDL

IM6402l03·AIDL

IM6402/031DL

MILITARY TEMP.

IM6402-1I03·1MDL

IM6402/03·AMDL

MILITARY TEMP.
WITH B83B

IM6402·1I03·1
MDU883B

IM6402/03-AMDU
8838

I

-T~8~S~l-i-!-t-i -!-t- i':.'~R.!Jl~l_ - - l

H TRANSMITTER BUFFER REGISTER
I ; TRANSMITTER+ REGISTER

I
I
START
I
t t l

t

I

_1 ~ : ;:i;~______~______! ! ! ! =!:!'!i i li~ ~M:U:l,T:'P_lEeX:E:R~ !.!.!.!.!.:!=I;-!-! .:III-:~
I

gc;~
CAL

CONTROL

MRT

REGISTER

t

I

RRC ~I RECEIVER
TIMING
DAR ----!--'
II
COANNToROl
* DR

SFo

I
L,_

I TAO
I ~~~

•

I II
I

STOP

PARITY

LOGIC

LOGIC

,<,,",,~

--oE r - - - - -

I

MULTIPLEXER

I I

t

RECEIVER BUFFER REGISTER

I
-U- THREE STATE_,...Ly,...Ly,...Ly,...Ly,...Ly
,...Ly,...Ly,...Ly

I

I
I

---FEt----PE"f - ~U~:f:(MSBif_f-T-f-+-f__r-rABR1(LSB) __

* These outputs are three state (lM6402) or always active (lM6403)

2-3

RRI

START
lOGIC

I

RECEIVER REGISTER

PI

II
I
Ii
...J

RRo

2

IM6402.11M6403
I M6402/1 M6403
ABSOLUTE MAXIMUM RATINGS
Oper;;lting Temperature
IM6402/03 ...... . . . . . . . . . . . . . . . .. . .. -40°C to +85°C
Storage Temperature ................... -65°C to 150°C
Operating Voltage ......................... 4.0V to 7.0V
Supply Voltage .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. +8.0V
Voltage On Any Input or Output Pin .. -0.3V to Vee +0.3V

NOTE: Stresses above those listed under "Absolute

Maxim~m

Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure
to absolute' maximum rating conditions for extended periods
may -cause device failures.

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee =5.0 ± 10%, TA = -40°C to +85°C

II

SYMBOL

MIN

CONDITIONS

VIH

I nput Voltage High

2

Vil

Input Voltage Low

3

IlL

Input Leakagei 1 J

4

VOH

Output Voltage High

IOH = -0.2mA

~' ~.

Output Voltage Low

IOl =1.6mA

IOlK

Output Leakage

GN D"VOUT"V CC

7

ICC

Power Supply Current Standby

8

ICC

Power Supply Current IM6402 Dynamic

fe

ferystal

5

I

PARAMETER

1

TYP

MAX

-5.0

GND"VIN"VCC

0.8'

V

5.0

/-!A
V

2.4

-5.0
1.0

VIN=GNO or VCC

UNITS
V

VCC-2.0

= 500 KHz

0.45

V

5.0

/-!A

800

/-!A

1.2

mA

3.7

mA

9

ICC

Power Supply Current IM6403 Dynamic

10

CIN

Input Capacitance[ 1]

7.0

8.0

pF

11

Co

OutputCapaeitance[ 1]

8.0

10.0

pF

TYP

MAX

UNITS

= 2.46MHz

NOTE 1: Except IM6403 XTAl mput pms Il.e. pms 17 and 40).
NOTE 2: VCC=5V, TA=25°e.

A.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 5.0V ± 10%, Cl = 50pF, TA = -40°C to +85°C
PARAMETER

SYMBOL
1

fe

Clock Frequency IM6402

2

ferystal

Crystal Frequency I M6403

3

tpw

Pulse Widths CRl, ORR, TBRL

4

tmr

Pulse Width MR

5

Ids

Input Data

6

tdh

Input Data Hold Time

7

ten

Output Enable Time

RRC

PIN 17

.--

Set~p

MIN

CONDITIONS

D.C.

See Tim ing Diagrams

Time

IFigures 2,3,4)

MHz

2.46

MHz

225

50

ns

600

200

ns

75

20

ns

90

40

ns

,

80

\
1

RECEIVER ~EGISTER
16X CLOCK

1.0

190

ns

RECEIVER REGISTER
16X CLOCK

I

J

PIN 40

TRANSMITTER REGISTER,'

TRe

16X CLOCK

TRANSMITTER REGISTER
16X CLOCK

I

/

N/e

DR

PIN 2

N/c

PIN 19

IM6402

I

,

DIVIDE CONTROL
PIN 2
L'" DIVIDE BY 2048 --'-"41--~------------_.....J

,

H '" DIVIDE BY 16

I
\

PIN 19
DR

\

}

\

PIN 22
TBRE

SFD

PIN 22

BUFFERS ARE 3-STATE \
\
WHEN SFD "" HIGH
\
\
\

PIN 16

'--

BUFFERS ARE
ALWAYS ACTIVE

IM6403

TBRE

PIN 16

\

SFD

\

FIGURE 1. Functional Difference Between IM6402 and IM6403 UART (6403 has On-Chip 4/11 Stage Divider)

as baud rate generators. For example, a color TV crystal at
3.579545MHz results in a baud rate of 109.2Hz for an easy
teletype interface (Figure 10). A 9600 baud interface may be
implemented using a 2.4576MHzcrystalwith the divider setto
divide by'16.

The IM6403 differs from,the IM6402 on three Inputs (RRC,
TRC, pin 2) ,as shovyn in FigureL Two outputs (TBRE, DR) are
not three-state as on the IM6402, but are always active. The
on-chip divider and oscillator allow an inexpensive crystal to
be used as a timing source rather than additional circuitry such
2-4

IM6402/IM6403
IM6402A1IM6403A
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Industrial IM6402AI/03AI
Military IM6402AM/03AM

............
..........

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These 'are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may calise device failures.

-40°C to +85°C
-55°C to +125°C

Storage Temperature ....••............•

-65°C to 150°C

Operating Voltage •.•.•.•.•••.•.........•• 4.0V to 11.0V
Supply Voltage

• . . . . . . . . . . . • . . • . . . . . . . • . . . . . • ..

Voltage On Any Input or Output Pin

••

+12.0V

-O.3V to Vee +O.3V

D.C. CHARACTERISTICS
TEST CONDITIONS:

Vee

=4 OV to

11.0V, TA

= Industrial or Military

PARAMETER

SYMBOL
1

V,H

Input Voltage High

2

V,L

I nput Voltage Low

CONDITIONS

Typ2

MIN

MAX

UNITS

20% Vee

v

1.0

/.IA

V

70% Vee

3

I,L

Input Leakage[l]

GND<;V,N<;Vee

4

VOH

Output Voltage High

IOH

5

VOL

Output Voltage Low

IOL -OmA

6

IOLK

Output Leakage

GND<;VOUT<;Vee

~

OmA

7

ICC

Power Supply Current Standby

V'N~GND or VCC

8

ICC

Power Supply Current IM6402A Dynamic

Ic =4MHz
I crystal = 3.58M Hz

-1.0

V

Vee-0.01
GND+O.Ol

V

1.0

-1.0
5.0

/.IA

500

/.IA

9.0

mA

13.0

mA

9

ICC

Power Supply Current fM6403A Dynamic

10

C'N

Input Capacitance[ll

7.0

8.0

pF

11

Co

Output Capacitance[ 1]

8.0

10.0

pF

Typ2

MAX

UNITS

4.0

MHz

6.0

MHz

NOTE 1: Except IM6403. XTAL input pins (i.e. pins 17 and 40).
NOTE 2: VCC~5V, TA~25°C.

A.C. CHARACTERISTICS
TEST CONDITIONS:

VCC

SYMBOL

= 1 O.OV ± 5%,

CL

=50pF, T A = Industrial or Military
CONDITIONS

PARAMETER

fc

Clock Frequency IM6402A

2

tcrystal

Crystal Frequency IM6403A

3

tpw

Pulse Widths CRL, DRR, TBRL

4

tmr

Pulse Width MR

5

tdS

Input Oat,a Setup Time

6

tdh

I nput Data Hold Time

7

ten

Output Enable Time

MIN
D.C.

1

100

40

ns

See Timing Diagrams

400

200

ns

(Figures 2,3,41

40

0

ns

30

30

ns

40

70

ns

TIMING DIAGRAMS
CLS1, ClS2,

sas, PI, EPE

SFD OR RAD

II""""--.,...-~

\J

STATUS OR

VALID

_R_BR_l_'_RB_R_8__~______-J~I,-__
DA_T_A__

r

FIGURE 2. Data tnput Cycle

FtGURE 3. Control Register Load Cycle

2-5

ten

-

FIGURE 4. Status Flag Enable Time
or Data Output Enable Time

IM6402/1M6403
IM6402-1/IM6403-1
ABSOLUTE MAXIMUM RATINGS
Operating Temperature
Industrial IM6402-11!03-11. . . . . . . . . .. ~40oC to +85°C
Military IM6402-1 M/03-1 M .. . . . . . . . .. -55°C to +125°C
Storage Temperature ................... -65°C to+15QoC
Operating Voltage ...........••.•.......... 4.0V to 7.0V
Supply Voltage ............................... , .. +8.0V
Voltage On Any Input or Output Pin .. -0.3V to Vcc +0.3V

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and funct,ional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specificatiori is not implied. Exposure
to absolute maximum rating conditions for extended periods
may cause device failures.

D.C. CHARACTERISTICS
TEST CONDITIONS: Vee = 5.0
SYMBOL

± 10%, TA =

Industrial or Military

PARAMETER

CONDITIONS

1

VIH

Input Voltage High

2

VIL

I nput Voltage Low

3

IlL

Input Leakagel' I

GND<:;VIN<:;VCC

4

VOH

Output Voltage High

IOH=·0.2mA

5

VOL

Output Voltage Low

IOL = 2.0mA

MIN

Typ2

MAX

VCC c2.0

6

IOLK

Output Leakage

7

ICC

Power Supply Current Standby

VIN~GND or VCC

8

ICC

Power Supply Current IM6402 Dynamic

fc = 2MHz
fcrystal = 3.58MHz

. GND<:;VOUT<:;VCC •

UNITS
V

-1.0

0.8

V

1.0

/J.A

0.45

'V

1.0

/J.A

V

2.4

-1.0
1.0

100

/J.A

1.9

mA

9

ICC

Power Supply Current IM6403 Dynamic

5.5

mA

10

CIN

Input Capacitancel' I

7.0

8.0

pF

11

Co

Output Capacitancel' I

8.0

10.0

pF

Typ2

MAX

UNITS

2.0

MHz

3.58

MHz

NOTE 1: Except IM6403 XTAL input pins (i.e. pins 17 and 40).
NOTE2: VCC=5V, TA = 25°C.

A.C. CHARACTERISTICS
TEST CONDITIONS: Vee
SYMBOL

= 5.0V -+

10%, CL = 50pF, TA = Industrial or Military

PARAMETER

CONDITIONS

1

Ic

Clock Frequency IM6402

2

fcrystal

Crystal Frequency IM6403

3

Ipw

Pulse Widths CRL, ORR, TBRL

4

Imr

Pulse Width MR

See Timing Diagrams

5

Ids

I nput Data Setup Time

(Figures 2,3,4)

6

Idh

Input Data Hold Time

7

len

Output Enable Time

MIN
D.C.
150

50

ns

400

200

ns

50

20

ns

60

40
80

2,6
)

ns
160

ns

IM6402/IM6403
IM6403 FUNCTIONAL PIN DEFINITION

Vee

(Continued)
GND

CLS2

RRD

PIN

SBS

RBR8

SYMBOL

DESCRIPTION

RBR7
RBR6
RBR5

14

FE

A high level on FRAMING ERROR indio
cates the first stop bit was invalid. FE will
stay active untilthe next valid character's
stop bit is received.

15

OE

A high level on OVERRUN ERROR indicates the data received flag was not
cleared before the last character was
transferred to the receiver buffer register.
The Error is reset at the next character's
§!2.E. bit if ORR has been performed (i.e.,
ORR: active low).

16

SFD

A high level on STATUS FLAGS DISABLE
forces the outputs PE, FE, OE, DR7TBRE*
to a high impedance state. See Block
Diagram and Figure 4.

R8R4
ABR3

10

RBR2

RBRl

"

12

TBR4

PE

13

28 _ T B R 3
TBA2

FE

0'

TBR1

SFD

TRO
TR'

liRl\

TBAl

• DR

TBRE ..

RRI

MR

-Ot FFERS BETWEEN IM6402 AND IM6403.

FIGURE 5. Pin Configuration

*IM6402 only.

IM6403 FUNCTIONAL PIN DEFINITION
PIN

DESCRIPTION

SYMBOL

17

IM6402-RRC The RECEIVER REGISTER CLOCK is 16X
IM6403-XTAl the receiver data rate.
or EXT ClK IN

18

A low level on DATA RECEIVED RESET
clears the data received output (DR), to a
low level.

Positive Power Supply

2

IM6402-N/C
No Connection
IM6403·Control Divide Control
High: 24 (16) Divider
low: 211 (2048) Divider

3

GND

Ground

4

RRD

A high level on RECEIVER REGISTER
DISABLE forces the receiver holding
register outputs RBR 1-RBR8 to a high im·
pedance state.

5

RBR8

The contents of the RECEIVER BUFFER
REGISTER appear on these three-state
outputs. Word formats less than 8 char·
acters are right iustified to RBR1.

6

RBR7

See Pin 5 -

RBR8

7

RBR6

See Pin 5 -

RBR8

8

RBR5

See Pin 5 -

RBR8

9

RBR4

See Pin 5 -

RBR8

10

RBR3

See Pin 5 -

RBR8

11

RBR2

See Pin 5 -

RBR8

12

RBR1

See Pin 5 -

RBR8

13

PE

19

DR

A high level on DATA RECEIVED indicates
a character has been received and transferred to the receiver buffer register.

20

RRI

Serial data on RECEIVER REGISTER
INPUT is clocked into the receiver
register.

21

MR

A high level on MASTER RESET (MR)
clears PE, FE, OE, DR, TRE and sets TBRE,
TRO high. less than 18 clocks after MR
goes low, TRE returns high. MR does not
clear the receiver buffer register, and is
required after power-up.

22

TBRE

A high level on TRANSMITIER BUFFER
REGISTER EMPTY indicates the transmitter buffer register has transferred its
data to the transmitter register and is
ready for new data.
A low level on TRANSMITIER BUFFER
REGISTER lOAD transfers data from in·
puts TBR1-TBR8 into the transmitter
buffer register. A low to high transition
on TBRl requests data transfer to the
transmitter register. If the transmitter
register is busy, transfer is automatically
delayed so that the two characters are
transmitted end to end. See Figure 2.

23

A high level on PARITY ERROR indicates
that the received parity does not match
parity programmed by control bits. The
output is active until parity matches on a
succeeding character. When parity is
inhibited, this output is low.

2-7

24

TRE

A high levelon TRANSMITIER REGISTER
EMPTY indicates com~leted transmission
of a character including stop bits.

25

TRO

Character data, start data and stop bits
appear serially at the TRANSMITIER
REGISTER OUTPUT.

1!1

.D~DI6

IM6402/1M6403
IM6403 FUNCTIONAL PIN DEFINITION

IM6403 FUNCTIONAL PIN DEFINITION

(Continued)

(Continued)

PIN

SyMBOL

26

TBR'l ':

DESCRIPTION

PIN

SYMBOL

DESCRIPTION

Character data is loaded into the TRANSMITTER BUFFER REGISTER via inputs
TBR1-TBR8. For character formats less
than 8-bits, the TBR8, 7, and 6 Inputs are
ignored corresponding to the programmed word length.

35

PI*

A high level on PARITY INHIBIT inhibits
parity generation, parity checking and
forces PE output low.

36

SBS*

A high level on STOP BIT SELECT selects
1.5 stop bits for a 5 character format and 2
stop bits for other lengths.

37

CLS2*

These inputs program the CHARACTER
LENGTH SELECTED. (CLSl low CLS210w
5-bits) lCLSl high CLS210w6-bits)(CLSl
low CLS2 high 7-bits) (CLSl high CLS2
high 8-bits)

38

CLS1*

See Pin 37 - CLS2

39

EPE*

When PI is low, a high level on EVEN
PARITY ENABLE generates and checks
even parity. A low level selects odd parity.

40

IM6402-TRC
IM6403-XTAL
or GND

The TRANSMITTER REGISTER CLOCK is
16X the transmit data rate.

27

TBR2

See Pin 26 -

28

TBR3

See Pin 26 - TBRl

29

TBR4

See Pin 26 - TBRl

30

TBR5

See Pin 26 -

31

TBR6

See Pin 26.- TBRl

32

TBR7

See Pin 26 - TBRl

33

TBR8

See Pin 26 - TBRl

34

CRL

A high level on CONTROL REGISTER
LOAD loads the control register. See
Figure 3.

TBRl

TBRl

'See Table 2 (Conlrol Word Funclion)

TABLE 2. Control Word Function
CLS2
L
L
L
L
L
L
L
L
L
L
L
L
H,
H
H
H
H
H
H
H
H
H
H
H

CONTROL WORD
CLSl
PI
EPE
L
L
L
L
L
L
L
L
H
L
L
H
L
H
X
L
H
X
H
L
L
H
L
L
H
L
H
H
L
H
H
H
X
H
H
X
L
L
L
L
L
L
L
L
H
L
L
H
L
H
X
L
H
X
H
L
L
L
H
L
H
H
L
H
L
H
H
H
X
H
H
X

SBS
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H

x = Don'l Care
2·8

DATA BITS

PARITY BIT

STOP BIT(SI

5
5
5
5
5
5
6
6
6
6
6
6
7
7

ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED
ODD
ODD
EVEN
EVEN
DISABLED
DISABLED

1
1.5
1
1.5
1
1.5
1
2

1
7
7
7
8
8
8
8
8
8

1

2
1

2
1
2
1
2
1
2
1
2
1
2
1
2

IM6402/1M6403
TRANSMITTER OPERATION

BEGINNING OF FIRST STOPBIT

The transmitter section accepts parallel data, formats it and
transmits it in serial form (Figure 6) on the TROutput
terminal.
';TARTBIT~ I

5-8 DATA BITS

1,11/2 OR 2 STOP BITS

I

~

I

RR I

DATA

4h

1+-71/2 CLOCK CYCLES

I

RBR1-B,Q E, PE

DRR

~. ~ILS~BI~~~~~IM-SBrl·~\fl~Ll~_C=-

DR

~PARITY

~U
I

FE

*IF ENABLED

~

A

1---,

CLOCK

CYCLE

FIGURE 6. Serial Data Format
FIGURE 8. Receiver Timing (Not to Scale)

Transmitter timing is shown in Figure 7. ® Data is loaded into
the transmitter buffer register from the inputs TBRl through
TBR8 by a logic low on the TBRload input. Valid data must be
present at least tos prior to and tOH following the rising edge of
TBRL If words less than 8 bits are used, only the least
significant bits are used. The character is right justified into
the least significant bit, TBR1. ® The rising edge of TBRl
clears TBREmpty. 0 to 1 clock cycles later, data is transferred to
the trar:1smitter register, TREmpty is cleared and transmission
starts. TBREmpty is resetto a logic high. Output data is clocked
by TRClock; which is 16 times the data rate.©A second pulse
on TBRload loads data into the transmitter buffer register.
Data transfer to the transmitter register is delayed until
transmission of the current character is complete.@Data is
automatically transferred to the transmitter register and
transmission of that character begins.

2

START BIT DETECTION
The receiver uses a 16X clock for timing (see Figure 9.) The
start bit ® could have occurred as much as one clock cycle
before it was detected, as indicated by the shaded portion. The
center of the start bit is defined as clock count 7'1,. If the
receiver clock is a symmetrical square wave, the center of the
start bit will be located within ±1 /2 clock cycle, ±1 /32 bit or
±3.125%. The receiver begins searching forthe next start bit at
the center of the first stop bit.
CLOCK

RRI INPUT

-rn
I. I.

START

COUNT71/2
'-DEFINED
CENTER OF
START BIT

7'/2 CLOCK CYCLES----+!
81/2 CLOCK CYCLES ~

FIGURE 9. Start Bit Timing

TYPICAL APPLICATION

TBRE

Microprocessor systems, which are inherently parallel in
nature, often require an asynchronous serial interface. This
function can be performed easily with the IM6402/03 UART.
Figure 10 shows how the IM6403 can be interfaced to an
IM6100 microcomputer system with the aid of an IM6101
Programmable Interface Element (PIE). The PIE interprets
Input/Output transfer (lOT) instructions from the processor
and generates read and write pulses to the UART. The SENSE
lines on the PIE are also employed to allow the processor to
detect UART status. In particular, the processor must know
when the Receive Buffer Register has accumulated a
character (DR active), and when the Transmit Buffer Register
can accept another character to be transmitted.

TRE

TRO

A

c

o

' \ END OF
LAST
STOP BIT

FIGURE 7. Transmitter Timing (Nollo Scale)

RECEIVER OPERATION
Data is received in serial form at the RI input. When no data is
being received, RI input must remain high. The data is clocked
by the RRClock, which is 16 times the data rate. Receiver
timing is shown in Figure 8.

In this example the characters to be received or transmitted
will be eight bits long (ClS 1 and 2: both HIGH) and transmitted
with no parity (PI:HIGH) and two stop bits (SBS:HIGH). Since
these control bits will not be changed during operation,
Control Register load (CRl) can be tied high. Remember, since
the IM6402/03 is a CMOS device, all unused inputs should be
committed.

®A

low level on DR Reset clears the DReady line. @ During
the first stop bit, data is transferred from the receiver register
to the RBRegister. If the word is less than 8 bits, the unused
most significant bits will be a logic low. The output character is
right justified to the least significant bit RBRl . A logic high on
OError indicates an overrun which occurs when DReady has
not been cleared before the present character was transferred
to the RBRegister. A logic high on PError indicates a parity
error. © 112 clock cycle later, DReady issetto a logic high and
FError is evaluated. A logic high on FError indicates an invalid
stop bit was received. The receiver will not begin searching for
the next start bit until a stop bit is received.

The baud rate at which the transmitter and receiver will
operate is determined by the external crystal and DIVIDE
CONTROL pin on the IM6403. The internal divider can be setto
reduce the crystal frequency by either 16 (PIN 2:HIGH) or 2048
(PIN 2:l0W) times. The frequency out of the internal divider
should be 16 times the desired baud rate. To generate 110
baud, this example will use a 3.579545MHz color TV crystal

2-9

IM6402/1M6403
and DIVIDE CONTROL set low. The IM6402 may use different
receive (RRe) and transmit (TRe) clock rates, but requires an
external clock generator.
To ensure consistent and correct operation, the IM6402/03
must be reset after power-up. The Master Reset (MR) pin is
active high, and can be driven reliably from a Schmitt trigger
inverter and R-C delay. In this example, the IM61 00 is reset
through still another inverter. The Schmitt trigger between the
processor and R-C network is needed to assure that a slow
rising capacitor voltage does not re-trigger RESET. A long reset
pulse after power-up ("<"lOOms) is required by the processor to
assure that the on-board crystal oscillator has sufficient time
to start.
The IM6402 supports the processor's bi-directional data bus
quite easily by tying the TBR and RBR buses together. A read
command from the processor will enable the RECEIVER
BUFFER REGISTER onto the bus by using the RECEIVER
REGISTER DISABLE (RRD) pin. A write command from the
processor clocks data from the bus into the TRANSMIITER
BUFFER REGISTER using TBRL. Figure 10 shows a NAND gate
driving 'i'BRC from the WRITE2 pin on the PIE. This gate is used
to generate a rising edge to i'EiRL at the point where data is

stable on the bus, and to hold TBRL high until the UART
actually transfers the data to it's internal buffer. If TBRl were
allowed to return low before TBRE went high, the intended
output data would be overwritten, since the TBF,! is a
transparent latch.
Although not shown in this example, the error flags (PE, FE,
OE) could be readbythe processor, using the other READ line
from the PIE. Since an IM6403 is used, TBRE and DR are not
affected by the STATUS FLAGS DISABLE pin, thus, the three
error flags can l1e tied to the data bus and gated by connecting'
SFD to READ2.
If parity is not inhibited, a parity error will cause the PE pin to go
high until the h.ext valid character is received.
A framing error is generated when an expected stop bit is not
received. FE will stay high after the error until the next
complete character's stop bit is received.
The overrun error flag is set· if a received character is
transferred to the RECEIVER BUFFER REGISTER when the
previous character has not been read. The OE pin will stay high
until the next received stop bit after a ORR ,is performed.

r-----~-------------------~~~-~-~~t_-~~~+5V

DXo·DXl1 b - - - - - - - - - - " ' , . . . - - - - - . . . , . - - - - - - - - - - ,

IM61001
MICROPROCESSOR

INTGNT

..--------1

LXMAR

1--------1

DEVSELb------~

XTC

1--------1

C11-------I
C2 ......- - - - - - I

--.-----1

SKP ......

INT

FIGURE 10. 110 Baud Seriallnlerlace lor IM6100 System

2-10

IM665311M6654
4096 Bit CMOS
UV Erasable PROM
GENERAL DESCRIPTION

FEATURES
•

Organization -

•
•

Low Power High Speed
- 300ns 10V Access Time for IM6653/54 AI
- 450ns 5V Access Time for IM6653/54-11
Single + 5V supply operation
UV erasable
Synchronous operation for low power
dissipation
Three-state outputs and chip select for easy
system expansion
Full - 55°C to + 125°C MIL range devicesIM6653/54 M, IM6653A/64A M

•
•
•
•
•

The Intersil IM6653 and IM6654 are fully decoded 4096 bit
CMOS electrically programmable ROMs (EPROMs)
fabricated with Intersil's advanced CMOS processing
technology. In all static states these devices exhibit the
microwatt power dissipation typical of CMOS. Inputs and
three-state outputs are TTL. compatible and allow for ~irect
interface with common sy~tem bus structures. On-chip address registers and chip select functions simplify system
interfacing requirements.

IM6653: 1024 x 4
IM6654: 512 x 8
770p.W Maximum Standby

The IM6653 and IM6654 are specifically designed for program development applications where rapid turn-around
for program changes is required. The devices may be erased by exposing their transparent lids to ultra-violet light,
and then re-programmed.

BLOCK DIAGRAM

PIN CONFIGURATION
(outline dwg JG/W)
PROGRAM
VOOf

64 x 64
ARRAY

A7

Vee

As

As

As

Ag

A.

S

01

A3

E1

••
••
••
•

A2
A1

Voo
PROGRAM

Au

03

04 OR
08

I-

:;:)

BI-

03

g-

O2
O2

t

01

S

ORDERING INFORMATION

A7

Vee

As

Aa

As

E2

A.

S
E1

SELECTIONITEMPERATURE RANGE
24 PIN
PACKAGE
CERDIP
JG
( FRIT SEAL)

STO 5V
IJG

INDUSTRIAL
MILITARY
HI SPEED 5V STD 10V STO 5V STD 10V
-11 JG
AIJG
MJG
AMJG

A1

Voo
PROGRAM
07
Oa
05

O.
03

2-11

fa

IM665311M6654
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
Voo ............................................................ +8.0V
Vee=Voo ....................................................... +8.0V
Input or Output Voltage Supplied ...................... GND - 0.3V to Voo + 0.3V
Storage Temperature Range ............................... - 65·C to + 150·C
Operating Range
Temperature
Industrial ............................................ ~40·C to +85·C
Military ............................................. -55·C to + 125·C
Voltage
6653/54 I, -11 ................................................ 4.5 - 5.5
6653/54 M .................................................... 4.5 - 5.5
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to tlJe device. These are stress ratings only, and functional operation of the device at
tl1ese or any other conditions above those indicated in the operational sections of the specifica·
tions Is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

DC CHARACTERISTICS
TEST CONDITIONS: Vee = Voo = 5V ± 10%, TA = Operating Temperature Range
IM6653/541, ·11,M
PARAMETER

SYMBOL

CONDITIONS

MIN

VIH
VIH
Vil

El ,S
Address Pins

Voo-2.0
2.7

II
Vo H2
VOHl
VOL2

GNDsVINSV OO

-1.0

10UT=0
IOH= -0.2mA

Vee- 0.01
2.4

Logical "1" Input Voltage
Logical "0" Input Voltage
Input Leakage
Logical "1" Output Voltage
Logical "1" Output Voltage
Logical "0" Output Voltage
Logical "0" Output Voltage
Output Leakage
Standby Supply Current

VOll
IOlK
looss
Icc

Operating Supply Current
Input Capacitance
Output Capacitance

looop
CI
Co

IOUT=O
IOl=2.0mA
GNDsVosVee

-1.0

VIN =V oo
VIN =V oo
f= 1 MHz
Note 1
Note 1

MAX

UNITS
V

0.8
1.0

p.A

GND+0.01
0.45
1.0
100
40
6
7.0
10.0

V

p.A
mA
pF

Note 1: These parameters guaranteed but not 100% tested.

AC CHARACTERISTICS
TEST CONDITIONS: Vee = Voo = 5V ± 10%, Cl =50pf, TA = Operating Temperature Range

PARAMETER
Access Time From El
Output Enable Time
Output Disable Time
Ej Pulse Width (Positive)
E1 Pulse Width (Negative)
Address Setup Time
Address Hold Time
Chip Enable Setup Time (6654)
Chip Enable Hold Time (6654)

SYMBOL

IM6653154·11
MIN MAX
450
110
110

TE1 LQV
TSLQV
TE1HQZ
TE1HE1L
TE1LE1H
TAVE 1L

j,

TE 1LAX
TE2VE 1L
TE1LE2X

IM6653/54I
MIN MAX

130
450
0
80
0
80

2·12

IIM6653154 M
MIN MAX

150

140
150
550
0
100
0
100

UNITS

600
150

550
140
150
600
0
100
0
100

ns

IM6653A/IM6654A
ABSOLUTE MAXIMUM RATINGS
Supply Voltages
voo ....................................................................+11.0V
Vee = Voo .............................................................. + 11.0V
Input or Output Voltage Supplied .........-.................GND - 0.3V to Voo + 0.3V
Storage Temperature Range .................................... - 65·C to + 150·C
Operating Range
Temperature
Industrial .................................................. - 40·C to + 85·C
Military.................................................... - 55·C to + 125·C
Voltage
6653/54 AI, AM ................................................... 4.5 to 10.5V
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.

DC CHARACTERISTICS
TEST CONDITIONS: Vee = Voo = 4.5V to 10.5V, TA = Operational Temperature Range

PARAMETER
Logical "1" Input Voltage
Logical "0" Input Voltage
Input Leakage
Logical "1" Output Voltage
Logical "0" Output Voltage
Output Leakage
Standby Supply Current
Operating Supply Current
Input Capacitance
Output Capacitance

IM6653/54AI, AM
MAX
MIN

SYMBOL

CONDITIONS

VIH
VIH
Vil

E1,S
Address Pins

II
VO H

GNDsVIWsVoo

-1.0

10UT=0
10UT=0
GNDsVosVcc
V1N=VOO
VIN=VOO
f=1 MHz
Note 1
Note 1

Vee- 0.01

VOL
10lK
IOOSB
Icc
looop
CI
Co

Voo-2.0
Voo-2.0

UNITS
V

0.8
1.0
GND+0.01
1.0
100
40
12

-1.0

7.0
10.0

pA
V
,.A
rnA
pF

Note 1: These parameters guaranteed but not 100% tested.

AC CHARACTERISTICS
TEST CON DITIONS: Vee = Voo = 10V ± 5%, Cl = 50pf, TA = Operating Temperature Range
IM6653/54 AI
PARAMETER
Access Time From El
Output Enable Time
Output Disable Time
El Pulse Width (Positive)
El Pulse Width (Negative)
Address Setup Time
Address Hold Time
Chip Enable Setup Time (6654)
Chip Enable Hold Time (6654)

SYMBOL
TE 1LQV
TSLQV
TE 1HQZ
TEl HElL
TE1LE1H
TAVE 1L
TEl LAX
TE2 VE 1L
TE 1LE2X

MIN

125
300
0
60
0
60

2-13

MAX
300
60
60

IM6653/54 AM
MIN

125
350
0
60
0
60

MAX
350
70
70

UNITS

ns

IM665311M6654
PIN ASSIGNMENTS
PIN

SYMBOL

ACTIVE
LEVEL

1-8,23
9-11,13-17

AO-A7.Aa
0 0-0 7

-

Address Li61es
Data Outlines, 6654

00-0 3
GND
Program

-

Data Outlines, 6653

-

Programming pulse input

Voo
E1
S

-

Chip V+ supply, normally tied to Vee
Strobe line, latches both address lines and, for 6654, Chip enable E2
Chip select line, must be low for valid data out

A9
E2

-

Additional address line for 6653

L

Vee

-

Chip enable line, latched by Chip enable E1 on 6654
Output buffer + V Supply

12
18
19
20
21
22
24

L
L

DESCRIPTION

READ MODE OPERATION

READ CYCLE TIMING

In a typical READ operation address lines and chip enable
E2 'are latched by the falling edge of chip enable E1 (T = 0).
Valid data appears at the outputs one access time (TELOV)
later, provided level-sensitive chip select line S is low
(T; 3). Data remains valid until either E1 or S returns to a
high level (T = 4). Olltputs are then forced to a high-Z state.
Address lines and E2 must be valid one setup time before
(TAVEL), and one hold time after (TELAX), the falling edge
of E1 starting the read cycle. Before becoming valid,.O output lines become active (T = 2). The Q output lines return to
a high-Z state one output disable time (TE1HOZ) after any
rising edge on E1 or S.
The program line remains high throughout the READ cycle.
Q OUTPUTS-----------,:"'-C

PROGR:~ ---r---r----;;-----!---.;--..!....;-.-""'T"'~

~~~--~--~-~~-~~~-~~---

Chip enable line E1 must remain high one minimum.
positive pulse width (TEHEL) before the next cycle can
begin.

*Ag IM6653 only, E2 IM6654 only

FUNCTION TABLE
TIME
REF

INPUTS
E1

E2'

S

H

X

X

0

~

L
X
X
X
X
X

X
X
L
L

-1
1

L

2
3

L
L

4

JI

5

H

L
X

A
X
V
X
X
X
X
X

.

OUTPUTS

NOTES

Q

Z
Z
Z
A
V

DEVICE INACTIVE
CYCLE BEGINS; ADDRESSES, E2 LATCHED'
INTERNAL OPERATIONS ONLY
OUTPUTS ACTIVE UNDER CONTROL OF E1, S
OUTPUTS VALID AFTER ACCESS TIME
READ COMPLETE
CYCLE ENDS (SAME AS -1)

V
Z

2,14

IM6653nM6654
READ AND PROGRAM CYCLES
E,
ADDRESS.

E2

DATA
5V _ __

PROGRAM

~~-

OV

t

VPAOG

-'1_

-40V _ _ _ _ _ _ _ _ _ _ _

s ____________________--J/

\~

_____________

1_.- - - - - REAO-----_.I_.----PROGRAM--__
.,I_._ _ _ _ REAO _ _ __

DC CHARACTERISTICS FOR PROGRAMMING OPERATION
TEST CONDITIONS: Vcc=Voo=5V±5%, TA=25°C
PARAMETER
Program Pin Load Current
Programming Pulse Amplitude

SYMBOL

Vcc Current
Voo Current
Address Input High Voltage
Address Input Low Voltage
Data Input High Voltage
Data Input Low Voltage

Icc

CONDITIONS

IpROG
VPROG

MIN
38

100

VIHA

Voo-2.0

VILA
VIH
VIL

Voo-2.0

TYP

MAx

80
40

100
42

UNITS
mA

0.1
40

5
100

mA

0.8

V

V

0.8

AC CHARACTERISTICS FOR PROGRAMMING OPERATION
TEST CONDITIONS: Vcc=Voo=5V±5%, TA=25°
PARAMETER
Program Pulse Width
Program Pulse Duty Cycle
Data Setup Time
Data Hold Time
Strobe Pulse Width
Address Setup Time
Address Hold Time
Access Time

SYMBOL
TPLPH

CONDITIONS
t rise = tfall = 51's

TDVPL
TPHDX

MIN
18

TYP
20

MAX
22
75%

9
9
150
0
100

TE1HE1L
TAVE1L
TE1LE 1X
TE1LQV

UNITS
ms

I'S

ns
1000

PROGRAM MODE OPERATION
latched by the downward edge on the strobe line (El ). During valid DA-rn IN time, the PROGRAM pin is pulsed from
Voo to - 40V. This pulse initiates the programming of the
device to the levels set on the data outputs. Duty cycle
limitations are specified from chip heat dissipation considerations. PULSE RISE AND FALL TIMES MUST NOT BE
FASTER THAN 51'S.

Initially, all 4096 bits of the EPROM are in the logic one
(output high) state. Selective programming of proper bit
locations to "O"s is performed electrically.
In the PROGRAM mode for all EPROMs, Vcc and Voo are
tied together to a + 5V operating supply. High logic levels
at all of the appropriate chip inputs and outputs must be
set at Voo - 2V minimum. Low .logic levels must be set at
GND + .8V maximum. Addressing of the desired location in
PROGRAM mode is done as in the READ mode. Address
and data lines are set at the desired logic levels, and PROGRAM and chip select (S) pins are set high. The address is

Intelligent programmer equipment with successive
READ/PROGRAMIVERIFY sequences, such as the Intersil
6920 CMOS EPROM programmer, is recommended.

2-15

IM666311M6664
PROGRAMMING SYSTEM CHARACTERISTICS

ERASING PROCEDURE

1. During programming the power supply should be
capable of limiting peak instantaneous current to
100mA.

The IM6653/54 are erased by exposure to high intensity
short-wave ultraviolet light at a wavelength of 2537 A. The
recommended integrated dose (l.e.,UV intensity x exposur~ time) is10W ~ec/cm2. The lamps. should be used
without short-wave filters, and the IM6653/54 to be erased
should be placed about one inch away from the lamp
tubes. For best results it is recommendEild that the device
remain inactive for 5 minutes after erasure, before
reprogramming.

2. The programming, pin is driven from VDD to - 40 volts
(± 2V) by pulses of 20 milliseconds duration. These
pulses should be applied in the sequence shown in the
flow chart. Pulse rise and fall times of 10 microseconds
are recommended. Note that any individual location
may be programmed at any time.

III
_

3.' Addresses and data should be presented to the device
within the recommended setup/hold time and high/low
logic level margins. Both "A" (10V) and non "A"
EPROMs are programmed at Vee, voo of 5V ±5%.
4. Programming is to be done at room temperature.

The erasing effect of UV light is cummulative. Care should
be taken to protect EPROMs from exposure to direct
sunlight or florescent lamps radiating UV light in the
2000A to 4000A range.

PROGRAMMING FLOW CHART

2-16

IM885311M8854
IM6653 CMOS EPROMS AS EXTERNAL PROGRAM MEMORY WITH THE IM80C35
+ 5V

GND

b26Lo
Vee Voo Vss

20pF

F

2

o~OSC1
I-~

P10

OSC2

P16

~

1+

r¥.-

P11 ~
P13~
P14~
P15~
P17

. - - RESET

+fnT

-¥.-

-#

~

1

1ttF

Vcc -.... EA

P20 21

P21

IM80C35

P22
P23

r.2~2_ _ _ _ _ _ _ _ _---1 ::

f¥.-

t-#-

P24~
P25~
P26
P27

t-¥.-

ALE

1"

~I

"g

~

GND

~

Vee Voo

~------~::

0,

r--

Ao
A,
A,
A,
A4

17

As

DB6 18

A,

087

A7

19

WR iffi

~

1>

i:

IM6653
IK x 4
EPROM

IM6653
IK x 4
EPROM

1---+++l---1 Ao
I-----++_++_---l
I-----++_++_---l
I-----++_++_---l
I--_ _ _~_++_--I
I-------.-+_++_--I
I-------+..+_--I
I--_ _ _ _ _
~--I

A,
A,
A,
A,
A,
A,
A,

S E1

S

1,---'91_:251_"018_ _ _ _ _~1+-[_ _ _ _----11

IM6653 CMOS EPROMS AS PROGRAM MEMORY WITH THE IM6100
+5

+5

GND

GND S,

Vee

Wr

-00

+5

GND

+

+

r==:
~

IM65x61

256 x 4

Ao

Vee GND

-

OSC IN

'~ 05C OUT

Vee voo;g GND
0,
0
:
00
~

"

DXo >OX,

1>

IM65x61

256 x 4

Vi E 5,

i:
m

'"
....

A,

IM65x61

256 x 4

RAM
Ao

Vi E 5,

A.

g

EPROM

1

Ao

+5 GND

D~DDLso

J

Vee voo;g GND

r;::: ~,

E, 5

1I

~

A, ' IM6653
1K x 4
EPROM

A,

IM6653
1K x 4
EPROM

Ao

Ao

E, 5

I I

CD4515B
STR
$2

t

GND-oo 0,
GND-oo 04 INH 815

) ADDITIONAL MEMORY ENABLE

1

2-17

g

00

S,f-

' - - 0,

+ f n Gr

i:

IM6653
1K x 4

I

GND

Vee voo;g GND
-=~,
00
"
1>

i:

DX 11

'--

+5

m~

~

fn

IM6l00

....

GND

+5

20pf

"

GND 5,

I

4

x

Vee

XTC

MH

i:

Ao

GND

!h

RAM

E 5,

W

20pf

,~

A,

+5

-;:::: 0,
00

00

RAM

-=

GND 5,

~,

0,
A,

GND

~h

~h
Vee

n-

;g GND

r----Ioo
r - - - - - 0,
~ 0,
r - - 0,

, - - - - 0,

fl!!.

DBS

~

.-------l 0 0
.-----1 0 ,

DBO ~~
DB11-7.:--------'4+--I
DB2 14
DB3 15
084 16

."

Vee Voo

+f-nT

i:

E1 5

11

E1

1

(4096 X

IM7332
32,768 Bit
8) HMOS ROM

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•
•

The IM7332 is a 32,768 bit read-only memory (ROM)
organized 4096 words by 8 bits. The device Is fabricated using Intersil's HMOS technology to minimize cell area and optimize circuit performance.

High Speed - 300ns Maximum access time
Completely static - no clock required
Single + 5V supply
Fully TTL Compatible
Two programmable Chip Selects
Three-state outputs
Industry standard 24 lead pinout

Inputs and three-state outputs are TIL compatible and
allow for direct interfacing to common bus structures. Two
chip select Inputs which are programmable to either active
high or active low, facilitate ease of memory expansion.
The IM7332 operates over 5V ±5% at 75mA with an access
time of 3OOns.

LOGICAL BLOCK DIAGRAM

PIN
CONFIGURATION

LOGIC SYMBOL

A3

S1/~ S2i~

A4

vec

AS

128 x 256

ROW
DECODER

A6

vce

MEMORY
ARRAY

AO

, A6

A8

A1

AS

A9

A2

A6

A4

A9

A3

S,/8,
S,/8,

A2
Al

Al0
All

A7

GND

A6

Q6

A7
A8

Q5

A9

Q4

Al0

Q3

All

Q7

QO

A3
A4
A5

Ql
Q2
IM7332

Q3
Q4
Q5
Q6
Q7

GND

-=(outline dwgs JG, PG)

51 /51

S",5,

L..C.C...::..:..c=:...:.-=---.-J
07

06

05

04

03

02

01

00

ORDERING INFORMATION

,PIN NAMES

PART NUMBER

PACKAGE

TEMP. RANGE

IM7332CPG
IM7332 CJG

24 Pin PLASTIC
24 Pin CERDIP

O·C to + 70·C
O·C to + 70·C

2-18

AO - All
QO- Q7
Sl IS1, S2/S2

ADDRESS INPUTS
DATA OUTPUTS
PROGRAMMABLE CHIP SELECTS

IM7332
ABSOLUTE MAXIMUM RATINGS
8upply Voltage. . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. + 7.0V
Voltage on Any Pin Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
Commercial Operating Temperature Range ..................... O·C to + 70·C
8torageTemperature .................................... -65·Cto +150·C
Power Dissipation .................................................... 1W

NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent
damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions above those indicated in the operational sections of the specifications is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

TESTCONDITIONS:VCC = 5V± 5%,TA = O·Cto

+ 70·C
LIMITS

DESCRIPTION

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Input High Voltage

VIH

2.0

Input Low Voltage

-0.5

VCC
0.8

V

VIL

Input Leakage Current

IILK

-10

10

",A

VIN

= OV to 5.25V

lOUT - -4OOIlA
Output High Voltage

VOH

81/81 = 82/82 = 2.0V/0.8V

2.4
V

lOUT =2.1mA
Output Low Voltage
Output Leakage Current

VOL

81/51 = 82/52 = 2.0V/0.8V

IOlK

VOUT = OV to 5.25V
81/81 = 82/82 = 0.8V/2.0V
TA

Icc

VIN = 5.25V, 81/81 = 82/82 =
2.0V/0.8V

Input CapaCitance

CUll

Vec =5.0V, VIN

COUT

-10

10

",A

75

mA

= 0 ·C, Data Out Open

Operating 8upply Current

Output CapaCitance

0.4

= 2.0V

VCC = 5.0V, VOUT = 2.0V

NOTE: 1. Typical values are measured at Vee = 5.0V and TA = +25°C.
2. Capacitance values are sampled, not 100% tested.

2·19

7
10

pF

IM7332
AC CHARACTERISTICS
DESCRIPTION

SYMBOL

7332-45
Address Access Time
7:3:32
Chip Select to Low Impedance
Chip Select Delay
Chip Deselect Delay
Output Hold Time

I

JEDEC SYMBOL

taa
tlz
teo
tdf
toh

TAVQV
TSVQX
TSVQV
TSXQZ
TAXQX

MIN

TYP

MAX

UNIT

450
300
20
100
100

ns

20

-------------------------------------------------------------READ CYCLE TIMING

~~_______~_L~ID~------~>f~--~---------

Qo -

Q7 -------------'-~

Vee
.AC TEST CONDITIONS
Vcc ...................................... 5V±5%
TA .................................... O°C to 70°C
Input rise and fall times ............ 20ns (10% to 90%)
Input and output reference level. . . . . . . . . . . . . . . . .. 1.5V

2.0kD

DOUT

0--.----...
I

100PF (INCLUDES SCOPE AND
.
JIG CAPACITANCE)

OUTPUT LOAD CIRCUIT

2·20

IM7364
65,536 BIT
(8192 X 8) HMOS ROM
FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•
•

The IM7364 is a 65,536 bit read-only memory (ROM)
organized 8192 words by 8 bits. The device is fabricated using Intersil's HMOS technology to minimize cell area and
optimize circuit performance.

High Speed - 350ns Maximum access time
Completely static - no clock required
Single + 5V supply
Fully TTL Compatible
Two Programmable Chip Select
Three·state outputs
Industry standard 24 lead pinout

Inputs and three-state outputs are TIL compatible and
allow for direct interfacing to common bus structures. A
chip select input, which is programmable to either active
high or active low, facilitates ease of memory expansion.
The IM7364 operates over 5V ± 5% at 90mA with an access time of 350ns.

LOGICAL BLOCK DIAGRAM

LOGIC SYMBOL

PIN
CONFIGURATION

A3
A4
A5
A6
A7

vee

A7
A6

A8

A8
A9

A9
A12

A3
A2
Al
AO
00

Ao-----i2
Al

vcc

SIS

256 X 256
MEMORY
ARRAY

ROW
DECODER

Al0
All
07
06
05·

---------1
02
GND

A2-----i2
Al0------j

AO
Al

A2
A3
A4
AS
A6
A7
AS
A9
Al0
All
A12

IM7364

00
01
02
03
04
05
06
07

GND

A11-------j

(outline dwgs JG, PG)
SIS

07

06

05

04

03

02

01

00

ORDERING INFORMATION

PIN NAMES

PART NUMBER

PACKAGE

TEMP. RANGE

IM7364CPG
IM7364 CJG

24 Pin PLASTIC
24 Pin CERDIP

o·C to + 70·C
O·C to + 70·C

Ao - A12
00 - 07
SIS

2-21

ADDRESS INPUTS
DATA OUTPUTS
PROGRAMMABLE CHIP SELECT

2

IM7364·
ABSOLUTE MAXIMUM RATINGS

Supply Voltage ................................................... + 7.0V
Voltage on Any Pin Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.5V to + 7.0V
Commercial Operating Temperature Range ..................... O·C to + 70'C
Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. -65'C to + 150'C
Power Dissipation. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . . . . . . .. 1W
NOTE: Stresses abo~e those listed under "Absolute Maximum Ratings" may cause. perma·
nent damage to the device. These .are stress ratings only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rating conditions for extend·
ed periods may affect device reliability.

DC CHARACTERISTICS
TEST CONDITIONS: Vee

= 5V± 5%,TA = O'Cto + 70'C
LIMITS

DESCRIPTION

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Input High Voltage

VIH

2;0

Input Low Voltage

-0.5

Vee
O.B

V

Vil

Input Leakage Current

IllK

-10

10

/LA

= OVto 5.25V
= -400J.lA
sis = 2.0V/0.BV
lOUT = 2.1mA
SIS = 2.0V/0.BV
VOUT = OV to 5.25V
SIS = O.BV 12.0V
TA = O·C, Data Out Open
VIN = 5.25V, SIS = 2.0V/0.BV
Vee = 5.0V, VIN = 2.0V
Vee = 5.0V, VOUT ,; 2.0V
VIN

lOUT

Output High Voltage

VOH

Output Low Voltage

VOL

Output Leakage Current

IOlK

Operating Supply Current
Input Capacitance

CIN

Output Capacitance

lee
COUT

NOTE: 1. Typical values are measured at Vee = 5.0V and TA = +25'e.
2. Capacitance values are sampled, not 100% tested.

2-22

2.4

V
0.4

-10

10

/LA

90
7

mA

10

pF

IM7364
AC CHARACTERISTICS

DESCRIPTION

Address
Access Time

SYMBOL

JEDEC SYMBOL

MIN

MAX

TYP

450
350

7364-45
7364
Chip Select to Low Impedance

taa

TAVQV

tlz

TSVQX

Chip Select Delay

teo

TSVQV

120

Chip Deselect Delay
Output Hold Time

tdf
toh

TSXQZ

120

TAXQX

UNIT

20
ns

20

-------------------------------------------------------------READ CYCLE TIMING

~_________VA_L_ID________~~~------------SIS

00 - 07

--------------41

AC TEST CONDITIONS

Vee

Vee""" ... " ............................... 5V±5%
TA .................................... O°C to 70°C

2.0kO

Input rise and fall times" " ..... " " " ". 20ns (10% to 90%)
Input and output reference level. . . . . . . . . . . . . . . . .. 1.5V

OUTPUT LOAD CIRCUIT

2-23

m

IM82C43
CMOS Input/Output
Expander
FEATURES

DESCRIPTION

• 80~8/41 compatible I/O expander

The Intersil IM82C43 is a CMOS input/output expander
equivalent to the NMOS 8243. It is designed to provide
110 expansion forthe CMOS IM80C48 and NMOS 8048
families of single-chip microcomputers.

• CMOS pin-for-pin replacement for standard
NMOS 8243
• Low power dissipation - maximum 25mW active
• Four 4-bit I/O ports in 24-pin DIP

The 24-pin IM82C43 provides four 4-bit bidirectional 110
ports: 8048/41 instructions control bidirectional transfers
between the 82C43 and the 8048 family microcomputers,
and can execute logical AND/OR operations directly on
the data contained in the 82C43 ports.

• Logical AND/OR directly to ports
• Highbutput drive
• Single +5V supply

LOGICAL BLOCK DIAGRAM

PIN CONFIGURATION

PORT4

P50

Vee

P40

P51

P41

P52

P42

P53

P43

P60
P61
P62
P63

PORTS

~73

Pr72
PORT 2

P71
P70

PORTS

(outline drawings JG, PG)

ORDERING INFORMATION

PROG

PORT 7

2-24

IIO~OIl

IM82C43
ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Operating Temperature .......... ; .. 0° C to +70° C
Storage Temperature ........... -65° C to +150° C
Voltage on Any Pin
With Respect to Ground .. Ground -0.5V to Vee +0.5V
Power Dissipation ........................... 1 W

D.C. AND OPERATING CHARACTERISTICS TA
PARAMETER

'=

SYMBOL

Input Low Voltage

VIL

Input High Voltage

VIH

O°C to 70°C, Vee

'=

5V ±10%

CONDITIONS

TYP.

MIN.
-0.5

Output Low Voltage ports 4-7
VOL
Output High Voltage Ports 4-7

VOH

Vee =4.5

2.0

Vee+0.5

Vee = 5.5

2.4

Vee+0.5

IOL = 10mA

0.4

IOL= 20mA

0.8

Output Voltage Port 2

VOH2

IOH = 3.2mA

0.4

IOH = 1.6mA

2.8

IILK

VIN = Vee to OV

-10

Supply Current

Icc

WRITE mode,
All outputs open,
tk = 700ns

Standby Current

leesB

Sum of all ICL from 16 Outputs

410L

PARAMETER

'=

mA
10

iJ. A

5.0

mA

VIN = 0 or Vee, CS = Vcc,
All outputs open

100

iJ. A

5 mA each pin average

80

mA

1.6

5V ±10%

SYMBOL

CONDITIONS

MIN.

80 pF Load

100

Code Valid Before PROG

ta

Code Valid After PROG

tb

20 pF Load

60

Data Valid Before PROG

te

80 pF Load

140
20

Data Valid After PROG

td

20 pF Load

Floating After PROG

th

20 pF Load

PROG Negative Pulse Width

tk

CS Valid BeforelAfter PROG

tes

Ports 4-7 Valid After PROG

tpo

Ports 4-7 Valid BeforelAfter PROG

tip

Port 2 Valid After PROG

tacc

Designator
PROG

7

FUNCTIONAL DESCRIPTION

Chip select input. When HIGH, it disables PROG, thus inhibiting change in
output or internal status.

P20-P23

8-11

Four bit bidirectional port carrying
address and control bits on the falling
edge of PROG and I/O data on the
rising edge of PROG.

P40-P43
P50-P53
P60-P63
P70-P73

2-5
1,21-23

Four bit bidirectional I/O ports. May be
configured for input, tri-state output
(READ mode) or latched output. Data
on pins P20-23 may be directly written,
ANDed, or ORed with previous data.

12

Circuit ground potential

24

+5 volt supply.

650

The IM82C43 has four 4cbit 1/0 ports, which are
addressed as Ports 4 thru 7 by the processor. The
following operations may be performed on these ports:

Function

Vcc

ns

700

80 pF Load

Strobe input. The falling edge of PROG
implies valid address and control information on P20-P23, while the rising edge
implies valid data on P20-P23.

GND

150

0

6

13-16

UNITS

50
100 pF Load

iSS

17-20

0

MAX.

700

FUNCTIONAL PIN DESCRIPTION
Pin
Number

V

2.8

Input Leakage Ports 4-7, Port 2, CS, PROG

A.C. CHARACTERISTICS TA = O°C to 70°C, Vee

UNITS

0.8

10L = 1.6mA

Output Low Voltage Port 2

MAX.

2·25

• Transfer accumulator to port (write)
• Transfer port to accumulator \read)
• AND accumulator to port
• OR accumulator to port
All communication between the microcomputer and
the 82C43 occurs over Port 2 (P20-P23) with timing
provided by an output pulse on the PROG pin of the
processor. Each data transfer consists of two 4-bit
nibbles:
• The first contains the port address and command
to the 82C43. This is latched from Port 2 during
the high-to-Iow transition of PROG and is
encoded as shown in the table on page 3.
• The second contains the four bits of data
associated with the instruction. The low-to-high
transition of PROG indicates the presence of data.

IM82C43
input mode (read). The first read of a port, following a
mode change from write to read should be ignored; all
following reads are valid. This is to allow the external
driver on th.e port to settle after the first read instruction
removes the low impedance drive from the 82C43 output. A read of any port will leave that port in a high
impedance state.

Port Address And Command Format
P23

P22

0
0

0

1
1

0

INSTRUCTION
CODE

1
1

P21

P20

0
0

0

1
1

0

Read
Write
ORlO
ANlD

1
1

ADDRESS
CODE
Port
Port
Port
Port

4
5
6
7

1/0 Expansion
The use of a single 82C43 with an 8048 or 8021 is
shown in figure 1. If more ports are required, more
82C43s can be added as shown in figure 2. Here, the
upper nibble of port 2 is used to select one of the
82C43s. Two lines could have been decoded but that
would require additional hardware. Assuming that the
leftmost 82C43 chip select is connected to P24, the
instructions to select and de-select would be:

Write Modes

2

The device has three write modes. MOVD P,A directly
writes new data into the selected port with old data
being lost; ORlD P,A ORs the new data with the old
data and writes it to the port; and ANlD P,A ANQs new
data with old data and writes it to the selected port.
After the designated operation is performed, the data
is latched and directed to the port. The old data
remains latched until the new data is written by the
rising edge of PROG.

MOV A, #OEFH
OUTl P2, A

P24 =0
Enable 82C43

MOV A, #OFFH
OUTl P2, A

Disable All
Send It

Read Mode
The device has one read mode. The command and port
address are latched from port 2 on the high-to-Iow
transition of the PROG pin. As soon as the read
operation and port address are decoded, the
designated port .output buffers are dil:jabled and the
input b'uffers enabled. The read operation is .terminated by the low-to-high transition of the PROG pin.
The port selected is switched to the high impedance
state while port 2 is returned to the input mode.
Normally a port will be in an output mode (write) or

Power On Initialization
Initial applicaiton of power to the device forces ports 4,
5, 6, and 7 to the high impedance state. Port 2 will be in
an input state if PROG or CS are high when power is
applied. The first high-to-Iow transition of PROG causes
the device to exit the power-on mode. The power-on
sequence is initiated if Vee drops below one volt.

WAVEFORMS
PROG

PORT 2
(WRITE
OPERATIONS)

FLOAT

..

cc~

...
OUTPUT

PORT 2
(REAO
OPERATION)

VALID.

PORTS 4·7

PREVIOUS OUTPUT VALID

PORTS 4·7

INPUT VALID,

AC TEST CONDITIONS:
VjH '" 2.BV
INPUT RISE AND FALL TIMES: 5ns (10 TO 90%)
INPUT AND OUTPUT TIMING VOLTAGE REFERENCE LEVELS: O.BV AND 2.0V

2·26

~

th~

X' - - - - - -

IM82C43
OUTPUT EXPANDER TIMING

TYPICAL APPLICATIONS

BITS 3,2

EXPANDER INTERFACE

PROG

fl

P20-P23

cs
P,

PROG

PROG

P5

8021

OR

P6

,

P7

,

82C43

8048

,

P20·P23

DATA IN

P2

A

,
,

~

--<

/

X

ADDRESS (4-BITS)

I/O

>

"'} "'AD

01_

)
DATA (4-BITS)

'WRITE

10

OR

1\

AND

BITS 1,0

0]
01
10

PORT
ADDRESS

"

Note:
The 82C43 does not have the same quasi-bidirectional port structure
as P1/P2 of the 8048. When a "1" is written to P4-7 of the 82C43 it is
a "hard 1" (low Impedance to +SVI which cannot be pulled low by an
external device. All 4 bits of any port can be switched from output
mode to input mode by executing a dummy read which leaves the
port in a high impedance (no pullup or pulldownl state.

I/O

I/O

I/O

Figure 1

USING MULTIPLE 82C43s
P27

PORT 1
8048

PORT 2

PROG~----------------~------------------~-----------------4------------------~

Figure 2

2-27

ThelGC10000
Series
CMOS Gate Arrays
FEATURES

•
•
•

•

GENERAL DESCRIPTION
An IGC10000 Gate Array is a matrix of identical cells,
each containing 3 uncommitted N-P transistor pairs.
Large numbers of identical arrays are prefabricated
and stockpiled. A particular circuit is constructed from
a prefabricated array by specifying the interconnections among the transistors within and between cells
on the final metal layer. Because all except the final
metal layer are .prefabricated, the cost advantages of
mass production can be realized even for low-volume
applications. In addition, prefabrication provides a saving in both design and manufacturing time; in some
cases customers can receive prototype chips in as few
as 6 weeks after initiation of the project.

Complexity from 408 to 15M
Equivalent 2-input Gates
Mature Silicon Gate CMOS Technology
-Low development cost
-3_3 to 9V nominal power supply range
±10%
- Fu"CMOS temperature range: - 55°C to
+ 125°C
- Resistance to latch-up
and electrostatic discharge
Extensive Macro Cell Library
-Numerous combinational and sequential
macros
-Facilitates 7400 and 4000-based
. designs
...., TTL or CMOS compatible 1/0 .
-Analog capability

In most cases IGC10QOO gate arrays are processed
with one mask step (a customized metal mask along
with a standardized contact mask). For some analog
applications or where more routing flexibility is needed, users have the option of programming the contact
mask in addition to the metal mask.

Fu"y Integrated CAD Software Support
-Highly efficient auto-routing capability
-Layout fully verified against input logic
-Accurate post-layout simulation with
calculated RC delays
-Automatic test code conversion

THE IGC10000 FAMILY OF GATE ARRAYS
Figure 1 shows a structural representation of an
IGC10000 Gate Array. Each rectangle in the body of
the matrix represents an array cell; the rectangles

Figure 1. Gate Array Configuration
(408) 996·5000 TWX: 910·338·0171

INTER5IL, INC., 10710 N. TANTAU AVE., CUPERTINO, CA 95014
Printed in U.S.A. ©Copyright 1980, Intersil, Inc., All Rights Reserved.

2-28

IGC10000
along each of the four sides of the chip represent I/O
cells. Table 1 lists the members of the IGC10000 Gate
Array family with their capacities and cell counts.

of the crossunder strips make the vertical interconnections within the array. The top and bottom
polysilicon strips (called feed-throughs) are used for
feeding horizontal connections through the array cell
beneath the power and ground buses.

Table 1. The IGC10000 Gate Array Family
Part No.

Equivalent
2·lnput Gates

Number of
Array Cells

Bonding Pads
and I/O Cells

IGC10408

408

272

34

IGC10756

756

504

44

IGC11500

1500

1000

62

Figure 3 shows the circuit diagram for the array cell.
Small hollow circles represent possible connection
points; Vss and VDD metal strips are shown as dotted
lines.

TECHNOLOGY

Vss

Voo

IGC10000 gate arrays are fabricated using Intersil's
high performance selectively oxidized 4-micron
silicon gate CMOS process with single-layer metal interconnect. Wafers are processed using state-of-theart processing technology with these features:
•
•
•
•
•
•
•

Positive photoresist
1-1 scanning projection lithography
Polysilicon, nitride and silicon dioxide plasma
etching
Ion implantation for source/drain doping and
threshold adjustment
Sputter metal deposition
Industry standard oxidation and diffusion
techniques
Nitride and polysilicon Low Pressure
Chemical Vapor Deposition (LPCVD)

ARRAY CELLS
An array cell, shown in topographical form in Figure
2, consists of three complementary transistor pairs
and five strips of polysilicon (called crossunder
strips) for making horizontal interconnections among
array cells. Power (VDD) and ground (Vss) buses run
vertically as shown. Metal strips (not shown) on top

n·Channel

p·Channel

Figure 3. Schematic Diagram of the Array Cell

Feed·Th'·OUllhS--

Pcily.i1icon
,Crolsunder
Strips

Figure 2. Topography of the Array Cell
2·29

IGC10000'
itO CELLS
I/O cells are used to interface the array with external
circuitry. Each I/O cell consists of an array of transistors of varying sizes, and allows construction of
normal digital I/O interface circuits as well as analog
circuitry of simple to moderate complexity.

Designers implement their circuits by selecting and
interconnecting the macros in the Macro Library,
listed in,Table 2.
Vss

y

... ...
2

Voo

-

I/O cells have. these features:
•

Protection against electrostatic discharge (ESD)

•

Logic level translation (CMOS-to-TTL and TTL-toCMOS)

B ....-H--+---

I·: ;:'::f!;,~:':::~~~:;:::::g 1;:p:~,::a~',:"'O'
The output drive capability of a single output buffer is
. one TTL load. Applications that require add.itional
. drive capability can be handled by using multiple 1(0
cells in parallel. (In a typical application, not all
available I/O cells are needed for external connections; unused cells will thus usually be available to
provide added driv~ capability where needed.)

AO-H-~-~---------T~ro

3

4

•••

MACROS
A macro is a physical implementation of a functional
,block and is realized by interconnections among trans,lstors in one or more array cells. For example, the
NOR function is constructed by connecting two
p-channel transistors in series to VDD and two
n-channel transistors in parallel to Vss, as shown in
the topographical and schematic diagrams, Figures 4
and 5.

Figure 5. Schematic Diagram for the 2-lnput NOR

A

B

Figure.4_ Interconnect Pattern for. the 2-lnput NOR

IGC10000
Table 2. IGC10000 MACRO Library
IGC10000 Combinational Macros
Type

Description

NOR/NAND

2·input
3-input
4-input
2-input
3-input
4-input

NAND
NAND
NAND
NOR
NOR
NOR

XOR/XNOR

2-input XOR
2-input XNOR

Adder

One-bit full adder

Buffers and Inverters

1Xinverter
2X inverter
3X inverter
4X inverter

Multifunction

2-1 AND-OR invert
2-2-2 AND-OR invert
3-2 AND-OR invert
2-1 OR-AND invert

Multiplexer

2 to 1 multiplexer

Schmitt Trigger

Schmitt Trigger

Transmission Gate

Buffered transmission gate
Unbuffered transmission gate

Tristate Control

Tristate control

IGC10000 Sequential Macros

D Flip-Flops

JK Flip-Flops
T Flip-Flops
. Latches

Counters

D flip-flop with reset
D flip-flop with set
D flip-flop with set and reset
Divide by 2 flip-flop w/jam load and
reset
Divide by 2 flip-flop w/reset
D flip-flop w/jam load and reset
D flip-flop shift register with reset
JK flip-flop with reset
JK flip-flop with set
T flip-flop with reset
latch
latch w/single input control
latch with reset
latch w/reset and single input
control
D latch w/transmission gate on output

D
D
D
D

Down counter with reset
Down counter w/jam load and reset
Up counter with reset
Up counter w/jam load and reset
Up/down counter with reset
Up/down counter w/jam load and reset

2-31

Set

Reset

Jam Load

Yes
Yes

Yes

-

-

-

-

Yes
Yes
Yes
Yes
Yes
Yes

Yes

-

-

Yes

-

-

-

Yes

-

Yes

-

Yes
Yes
Yes
Yes
Yes
Yes

-

-

-

-

Yes

-

Yes

Yes

-

Yes

-

Yes

IGC10000
Table 2. IGC10000 MACRO Library (continued)
IGC10000 Digital I/O Cell Macros
Type

Description

Bidirectional

Tristate output/unbuffered input
Tristate output/inverting TTL input buffer

Feedthrough

Input feedthrough

Internal Buffer

Inverting internal buffer
lriternal tristate buffer·

Input Buffer

Non-inverting TTL input buffer
Non-inverting CMOS input buffer with pull-up options

Output Buffer

Open drain output buffer
Non-inverting TTL output buffer
Inverting TTL output buffer
Tristate output buffer
Symmetrical drive output buffer

IGC10000 Analog I/O Cell Macros
The list below represents a sample of custom macros developed for specific analog applications. Consult your Intersil Representative for suitability to your design.
Analog Transmission Gate
Auto Null Comparator
Comparator
COlT!pensated Op Amp
Crystal Oscillator
Current Multiplier
Current Reference
Op Amp
Power-on Reset
RC Oscillator
Schmitt Trigger

COMPUTER AIDED DESIGN SOFTWARE
TOOLS
The IGC10000 family is supported by a proprietary
computer aided design (CAD) system developed at
·the General Electric Microelectronics Center. The
system provides CAD tools for logic simulation, accurate prediction of circuit speed performance,
automated design of interconnect circuitry, electrical
and design rule checking., post-layout simulation using RC delays extracted from the layout, and
automatic conversion of simulation test pattern files
into tester format.

puter. Once the user has entered the circuit's interconnect information .into the computer, this information,is
converted into a common database accessed by all
other parts of the software through the CADEXEC.
Logic Simulation: Users have access to the TEGAS
logi.c simulator. For pre-layout logic (functional)
verification, customers may perform TEGAS simulation using our Unit Delay Macro Library database; for
design verification (pre-layout tiilling analysis), .
calculated delays based on fanout are used in conjunction with Best, Typical, and Worst Case libraries,
. whose parameters are described in Table 3.

The CAD tools are integrated under a supervisory program called the CADEXEC (for CAD Executive) that
runs on a Digital Equipment Corporation VAX com2-32

IGC10000
Post-layout simulation: A specialized circuit
simulator has been developed at the General Electric
Microelectronics Center to compute the delays of the
RC-interconnect nets from the topology of the network after performing layout. The RC Delay extraction software uses a full transient analysis for each
net; delays are based on resistance as well as
capaCitance of the interconnection nets. The software calculates delays as a function both of load
switching voltage and driver output impedance and
handles loops, bidirectional drivers, and multiple
drivers on the net.

Table 3. Best, Typical, and Worst Case Parameters
Parameter
Voltage (V)
Temperature (0C)
Process

Best

Typical

Worst

5.5

5.0

4.5

0

27

70

Best

Typical

Worst

Routing: The SILICA layout system uses a proprietary
automatic router developed at the General Electric
Microelectronics Center. The SILICA router has consistently performed with higher completion rate and
lower CPU time than other commercially available
routers; in addition, the router improves the overall
performance of the circuit by selecting paths that
produce the smallest delay. Like many routers, the
SILICA router has a Critical Net feature that
minimizes polysilicon and total net length by routing
the critical net first. Unique to the SILICA router is
the Super Critical Net feature, which prohibits the
use of polysilicon gates in a specified net.

After the RC delay information is extracted, the
CADEXEC system inserts the delays into the network
database for post-layout TEGAS simulation and
critical path analysis, thus providing an additional opportunity for refining the layout prior to PG tape
generation.
Tester Tape Generation: Test program conversion
software automatically translates the customer's
final TEGAS simulation output file into a test vector
pattern file to be used in testing the finished device.

Electrical and Design Rule Checking: SILICA DRC
(Design Rule Checker) performs electrical and design
rule checking in minutes instead of hours and extracts geometric data from the layout for input into
the RC delay extraction software.

PACKAGING
Five types of packages are available for the IGC10000
gate arrays. Dual inline packages are available in
plastic (Plastic DIP), ceramic (CerDIP) and multilayer
ceramic (Side Brazed DIP); lead less chip carriers and
pin grid arrays are provided in" multilayer ceramic.
Table 4 presents recommended package types for
each pin count and array size.

Manual editing: In rare instances manual layout
editing may be done on one of our CALMA workstations. CALMA output is fed into SILICA DRC for convenient verification of electrical integrity.

Table 4. Recommended Package Types
Number
of
Pins
8
14
16
18
20
24

28

40

Plastic
DIP
408
408
408
408
408
756
1500
408
756
1500
408
756
1500

CerDIP

Side
Brazed
DIP

408
408
408
408
408
756
1500
408
756
1500
408
756
1500

408
408
408
408
408
408
756
1500
408
756
1500
408
756
1500

Leadless
Chip
Carrier

Pin
Grid
Array

756
1500

44
756
1500

48

1500
1500

52
68
2-33

1500

II

IGC10000
DEVELOPMENT
An overview of the gate array development process is
shown in the flow chart of Figure 6. During Phase 1
(Design Translation), most of the responsibility lies
with the customer; during Phase 3 (Fabrication), with
Intersil. In Phase 2 (Design Implementation), most of
the activities are performed by Intersil, but require

customerinteracti'on and approval. Figure 6
delineates the responsibilities of the customer and of
Intersil. For more information, contact either your
local Intersil representative, or Semicustom
Marketing at the General .Electric Microelectronics
Center, Research Triangle Park, NC, telephone
919-549-3607.

CUSTOME.R
CREATE SCHEMATIC DIAGRAM;
DEFINE PRELIMINARY TEST VECTORS;
VERIFY CORRECT FUNCTIONALITY

PHASE 1
DESIGN
TRANSLATION

CU~TOMER/INTERSIL

TRANSLATE TO IGC10000 CMOS MACROS;
ENCODE IN TEGAS;
PERFORM PRE·LAYOUT SIMULATION

INTERSIL
PERFORM PRELIMINARY PLACEMENT ON ARRAY;
RECOMMEND SCHEMATIC CHANGES
WHERE REQUIRED

PHASE 2
DESIGN IMPLEMENTATION

CALCULATE INTERCONNECTION·RELATED DELAYS; . .PERFORM POST·LAYOUT TEGA$ SIMULATION

CUSTOMER
PROVIDE COMPLETE TEST VECTORS

INTERSIL
CREATE PATTERN GENERATOR TAPE

PHASE 3
{FABRICATE MASKS AND WAFERS; PERFORM WAFER PROBE;
FABRICATION
ASSEMBLE PACKAGES; TEST; SHIP PROTOTYPES

Figure 6. Simplified Flowchart for Gate Array Development

__

IGC10000
OPERATING CHARACTERISTICS 1
Absolute Maximum Ratings 2 (Referenced to Vss)
Parameter

Symbol

Limits

Units

VDD

- 0.5 to + 10.0

V

Input Voltage

VI

- 0.5 to VDD + 0.5

V

DC Input Current

II

±10

mA

Operating Ambient Temperature Range

TA

-55to +125

DC

Storage Temperature Range (Ceramic)

TSTG

-65 to + 150

DC

Storag'e Temperature Range (Plastic)

TSTG

-40 to + 125

DC

DC Supply Voltage

NOTE 1: Stress ratings only. Functional operation of the device at these or any conditions beyond those indicated as Recom·
mended Operating Conditions is not implied.
NOTE 2: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
DC Supply Voltage
Typical Operating Frequency
Operating Ambient Temperature Range

1

Symbol

Limits

Units

VDD

3.3 ± 0.3V to 9.0 ± 0.9V

V

fCK

8.0

MHz

TA

- 55 to + 125

DC

NOTE 1: IGC10000 gate array macros are currently characterized between 0 and 70 DC.

AC CHARACTERISTICS
Specified for nominal processing
Calculated for a fanout of 1.

5V,27"C.

Parameter

Typical Delay (ns)

Array Cell Macros
2-input NAND
2-input NOR
4-input NAND
4-input NOR
1X inverter
4X inverter
2-1 AND-OR invert
D flip-flop with reset
Schmitt trigger
Up counter with reset

D to Output
D to Output
D to Output
D to Output
D to Output
D to Output
D to Output
CK to Output
Input to Output
CK to Output

6
6
8
18
5
4
9
9
18
11

I/O Cell Macros
Input feedthrough
Non-inverting Input Buffer
Non-inverting Output Buffer

Pad to Output
Pad to Output
D to Pad

2-35

1
9
10 (15 pF)
19 (50 pF)

IGC10000
DC CHARACTERISTICS
Voo = 5V ± 10%
Limits 1
O°C
Min.
Max.

Parameter

Condition

2

Quiescent Device
Current

VI= Voo or
VSS

VOL

Low Level Output
Voltage

Ilol:51l'A

VOH

High Level Output
Voltage

Ilol:51l'A

VIL

Low Level Input
Voltage

CMOS
1/0 Macro

VIH

High Level Input
Voltage

CMOS
1/0 Macro

VIL

Low Level Input
Voltage

TTL
1/0 Macro

VIH

High Level Input
Voltage

TTL
1/0 Macro

2.0

2.0

Vo=O.4V

1.8

1.8

VO=2.5V

3.8

VO= 4.6V

Vo=2.5V

Symbol
100

3

IOL

IOH

3

Min.

25°C.
Typ.
Max.

70°C
Min.

0.3

0.05

Voo
- 0.05 .

0.05

Voo
-0.05

Units

100

I'A

0.05

V

V

Voo
- 0.05

1.5

3.5

Max.

1.5

3.5

1.5

V

3.5

0.8

0.8

V

0.8

V

2.0

V

3.6

1.6

rnA

3.8

7.6

3.4

rnA

0.3

0.3

0.6

0.25

rnA

1.8

1.8

3.6

1.6

rnA

Output Low 4
(Sink Current)

Output High
(Source Current)

liN

Input Leakage
Current

VIN=Oor
VOO

± 0.1

±.001

±0.1

± 1.0

itA

IOZ

Tristate Output
Leakage Current

VO= 0 or
Voo

1:

1.0

±.001

± 1.0

±10

wA

CIN

Input Capacitance

Any Input

5.0

pF

NOTES:
1, IGC10000 gate arrays are designed to perform under conditions up to 125°C. Umits reflect temperature range at which the
macro library is characterized.
2. Any internal oscillators disabled.
3. Results depend on specific output macro used.
4. There may be limitations on maximum current when many outputs are simultaneously low ..

2·36

Multiplexers
IH5108
IH5208
IH6108
IH6116
IH6208
IH6216

Page
3-63
3-79
3-93
3-99
3-109
3-115

Analog Switch
Drivers/Level
Translators
0123/125
0129
IH6201

3-9
3-13
3-105

Analog Switches
with Drivers
OG118/123/125
OG139A Family
OG180 Family
OGM181 Family
OG200
OG201
IH5009-24
IH5025-38
IH5040-51
IH5052/3
IH5140-45
IH5200
IH5201

3-6
3-15
3-19
3-23
3-28
3-32
3-36
3-41
3-48
3-56
3-71
3-28
3-32

Video/RF Switch
IH5341

3-87

Analog Switch
>

OG2001201
1t:t52OO15201
Mon~lIthic CMOS

Low Leakage and
Low Quiescent Current

IH5CMO Family

IH5140 FamUy

Monolithic CMOS
driver
combination

Monolithic CMOS
driver gate
combination

g."

drlver-gate
combination

Low rOS(on)

High Speed

OGM181 Famliy
Monolithic CMOS
replacement for
OG180 Family

OGI80 family
Blpolar/MOS driver
with N·JFET .gate

OG126 Family
Bipolar driver with
N·JFET gate

F.......

F••tUrN

F_ture.

Future.

Features

F••tures

1. 002001201 Industry standard

1. Very tow quiescent
current resulting In
very low power
consumption

1. High speed switching
2. Low quiescent
current resulting
in low power
consumption
3. Low leakage
resulting In low
error term
4. Lower cost than the
comparable speed
00180 family
5. Can switch signals
almost to the
supply ralis

1. Drops Into DGI80 family
sockets. Meets or
exceeds all specs
2. Lower cost than DGI80
3. Lower leakages and
power consumption
than DGI80

1. Low rOS(on)

1. Low roS(on)
2. Only switch with
true chip enable
plo
3. Moderate leakage
4. Draw high quiescent
currents

Not••

No...

Not..

Not••

Notes

1. TIL, DTL, CMOS, and
PMOS compatible
2. 5040 through 5047
have 750 f08(on) max
@2S"C
3. IH5048 thru IH5051 have
350 rDS(on) max
@2S"C

1. TIL and CMOS

1. TIL, OTL, RTL and CMOS
compatible
2. OGM181, 184, 187, and 190
have 300 max foS(on)
3. oGM182, 185, 168, and 191
have 750 max roS(on)

1. OTl, TTL, RTl
compaUble
2. OGI80, 183, 185 and
189 have 100 max
on resistance but
have higher
leakage than others
in the family
3. DG181, 184, 187
and 190 have 300

oG133, 134, }
141,151,
Dual SPST
152
OG126, 129, }
140, 153, . Dual oPST

2. IH52OOI5201 have

tar ,uperlor specs
3. IH5201DG201 have"
Individually controllable SPST
switches
.t. IH52OO1OG200 have 2
individually controUable SPST
switches

2. low cost
3. Good speed with
moderate 'OS(on)
and leakage
... Over voltage protection

to :t25V
5. Can switch up to
:;t 13V signals with
± ISV supplies

-

1. TIL, OTL, CMOS and PMOS
compatible
2.

~:

}

Dual SPST

~:;

}

Quad SPST

IH5040
IH5041/5048
IH5042/SOSO
IH5043/5051
IH5044
IH504515049
IH5048
IH5047
I H5052/5053

IH200
IH201/202

SPST
Dual SPST
SPOT
Dual SPOT

DPST
ouat oPSl
oPOT
4PST
Quad SPST
Dual SPST
Quad SPST

compatible
2. Pin compatible
with the more
popular members
of the 00180
family
IHSI40
IHS141
IH5142
IHS143
IH5144
IH5145

SPST
Dual SPST
SPOT
Dual SPOT
OPST
Dual oPST

OGM18112
oGMI84/5
OGMI8718
oGMI90/1

Dual SPST
oualoPST
SPOT
Dual SPOT

2. As fast as the
IH5140 Family
3. Moderate leakage
4. Draw high quiescent
currents

max 'oS(on)
4. oGI82, 165, 188
and 191 have 750
max 'oS(on)
oGI8011I2, Dual SPST
OG1831415, Dual DPST
OGI861718, SPOT
OGI89190ll, Dual SPOT

154
OG143, 144, } Differential
~~' 161,
Input, SPOT
OG139, 142, } Differential
145, 163,
Input,
164
oPOT
IH5001I2
IH5003·7

SPST
OuafSPST

Selector Guide
Low Chilli_
Injection

IH181 Family

Vld_o/RF Switch

For swltch.s who••
outputs go Into the
In••rtlng Input
olin Op Amp

For switching
posltl.. ligna Is
only

IH5341 FamJJy

IH5009

IH5025

CMOS driver and

series shunt

Varafet gate

vldeo/AF switch

Virtual ground
switch

Positive signal
switch

Output of a switch must
go Into the virtual
ground point of an

Can switch positive
signals only unlass

F•• tu....

F•• ture.

1. lowest charge
InJeclion

1. rOS(on) < 75(1, flat from
DC to 100 MHz « 3dB)

2. Almost as last as

2.
3.
4.
5.

IH5140 and DGI80
Femmes
3. Very low quiescent

"OFF" Isolation> BOdB @10 MHz
Cross coupling Isolation >6QdB @10MHz
+ I -5V to + 1-15V power supply range
High speed swllching

current resulting

in low power
consumption

4. Ultra low leakage

Not••

Not ••

1. TIL, HTL, CMOS

1. TIL, DTl, ATL and CMOS compatible
2. IH5J41 Dual SPST

and PMOS compatible
2. Pin for pin compatible
with OG100 family
IH1811182 Dual SPST
IHl841185 Dual DPST
IH1871188 SPDT
IHl901191 Dual SPOT

Op Amp (unless signal

a translalor driver

Is used

Is ...J
Il..
Il..

VJ
UJ

~

All
circuits

0

Il..

l!l
Z

-::c

VJ

UJ

u :2:
l-

~

VJ

f::

All
circuits

IOION)

tION)

0.3

/lS

t(OFF)

1

/lS

=

=

0

-10V

One Channel (ON)

All Channels (OFF)

See Switching Times

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the MOS-FET switch for the given test condition.

3-7

DG11811231125
TYPICAL CHARACTERISTICS
liN vs VIN
DG123
1.8

<
oS

VR = 0
V- = -20V

SWITCHING TIMEI'
TEMPERATURE

I

1100

I

;;;900

1.4

'~::gN

.s

w
tr:

-55'C I I I'J

::;; 700

:>
<.>

J~

....z
a:

..,
....:>
z

J

VI

UJ

0.6

....<.>

~

1/ /

0:2

/
o

0.2

0.4

/
0.6

V+ = 10V
COUT "" 30pF
p = -20V

300
100

tOFF'

O.S

--

-50

V ,N -INPUT VOlTAGE (VI

IS - ~fmA :

~,

L

'"

II

ros vs Vo or Vs
lK

VR' 0
V-· -20V

;::
z
:E 500

11'1

v,

tON

o

V

IQ

./

125'_

/c

25'-

~, *"-55'
.......

100

v+ = 10V
V- - -20V
vp = -20V

r--.,-r-..

~

25

75/

10
-10

125

TEMPERATURE ('CI

o

+10

Vo OR V, (VI

APPLICATION TIPS
The recommended resistor values for interfacing RTL, DTL, and T2 L Logic are shown in

Fisur~s

1 and 2.

AlL
DTl931.948
949,961,963

TTL 5414
TTl900QSERIES
SUHL

Figure 1. DG118 and OG125
I nterfoce

,F igure 2

OG 123
Interface

Enable Control
TheVR and VL terminals can be used as either a Strobe or an Enable control. The requirements for sinking current at VR
or sourcing current at VLare: IL(ON) x No. of channels used, for DG118 and DG125, and IR(ON) x No. of channels used, for
the DG123 devices. The voltage at V L must be greater than the voltage at VIN by at least + 4V.

SWITCHING TIMES
OG123

s,
OGI1J

JOpF

Dl:TPUT

1-""

DG118,125
OuTPUT

DG118,125

.,:}~~---+J(

OUTPUT

30"

3-8

.U~U[6

D123/D125
a·Channel FET Switch Drivers

FEATURES

GENERAL DESCRIPTION

• Provides DC level shifting between low-level
Logic and MOS-FET or J-FET switches

The D123 and 0125 monolithic bi-polar drivers convert
low-level positive signals (0 & +5V) to the high level positive
and negative voltages necessary to drive FET switches. One
.lead can be used to provide an enabling capability.

• External Collector Pull-ups required
• Direct interface with Gl16. Gl17. Gl19. Gl15.
and G123 MOS-FET switches

SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD)
0123

0125

v,

,
,

ENABLE (Vd

,

v.

,
v"

,
v"

ORDERING INFORMATION
D123

L:
A

.

L

Package
K - 14-Pin CERDIP
L - 14-Pin Flat Pack
P - 14-Pin Hermetic DIP (Special Order Only)

Temperature Range
A - Military (_55°C to +125°C)
B - Industrial (-20°C to +85°C)
' - - - - - - - - Device Chip Type

3·9

D123/125
ABSOLUTE MAXIMUM RATINGS
Input-to-Emitter Voltage (V IN - Vee)
Output-to-Emitter Voltage (Vo- Vee)
Logic Supply-to-Emitter Voltage (V L - Vee)
Input-to-Reference Voltage (V IN - V R )
Input-to-Logic Supply Voltage (V IN - Vd
Reference-to-Emitter Voltage (V R - Vee)
Maximum Dissipation (Note)
Current (any pin)

33V
33V
27V
2V
+6V
31V
750mW
30mA

_65°C to +150°C
_55°C to +125°C
300°C

Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec)

NOTE: Dissipation rating assumes device is mounted with all leads
welded or soldered to printed circuit board in ambient
temperature of 70°C. Derate 10 mWfC for higher ambient

temperature.

Stresses above those listed under Absolute Maximum Ratings ·may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ELECTRICAL CHARACTERISTICS
Test conditions unless otherwise specified are as follows: VEE; -20V, V L
supply measurements based on specified input conditions.

PARAMETER
M

N

~

f-

0

::J

"2

-

Ll')

N

IINIOFF)

;

4.5V, lOUT; 0, V R

;

MAX LIMIT

CONDITIONS

-55°C

25°C

125°C

UNITS

1

1

100

pA

V'NION)

1.3

1

I'NIOFF)

1

1

IINION)

O. Output and power

V IN

;

O.4V

V

liN; 1 mA

20

pA

V'N ;4.1V

-0.7

mA

V IN ; 0.5V

10

pA

V OUT ; +10V

0.8

~

-0.7

-0.7

IOUTIOFF)

0.1

0.1

VOUTION)

-19.7

-19.7

-19.5

V

lOUT; 1 mA

VOUTION)

-19.2

-19.2

-19.0

V

lOUT; 4 mA

IRION)II)

0.5

0.5

0.5

N

I R IOFF)12)

1

1

150

0

IEEION)11)

1

1

1

mA

lEE IOFF) (2)

2

2

200

pA

I LION) II)

2

2

0
f-

~

::J

"-

Ll')M

f-

I

NN

::J
0

55
M

>...J

""::J

U)

c::
UJ

:i:

Ll')

0
"-

N

1

1

leEION)11)

2

2

IEeIOFF)12)

2

2

100

pA

mA
pA

lOUT; 0 for
ON measurements.
V OUT ; +10V for
OFF measurements.

~

0

~U)

J:UJ

U2
f-§:f-

1.9
200

mA
pA

tl on )

250

ns

lOUT; 1 mA COUT (3)

0

tloff) (4)

800

ns

(See Switching Times)

~
Ll')

tlon)

250

ns

.loUT; 4 mA COUT (3)

t loff) (5)

600

ns

(See Switching Times)

M

l'J

U)

ILIOFF)12)

1.9

mA

N

~

N
~

0

NOTES: (1)
(2)
(3)
(4)
(5)

One channel ON, 5 channels OFF.
All channels OFF.
Add 30 ns per pF for 1 mA and .add 8 ns per pF for 4mA for additional capacitive loading.
For Dual-In-Line package add 120 ns to tloft).
For Dual-In-Line package add 30 ns to tloff)'

3·10

;

10 pF

;

10 pF

D123/125
SWITCHING TIMES
0123

.>0-+--0,

V oo ,

,,,

JL

+10V---...".

o

I.
I,

< 10ns
< 10",

0125

-20V---.,,+-Cf

fl

1,<10,"
I, < 10ni

Circuit Diagrams

TYPICAL CHARACTERISTICS

SWITCHING TIMES VS
TEMPERATURE 0123 AND
0125 (SEE NOTES 4 AND 51

toff(delayl VS IIN(PEAKI
0123

~

"z
:;

1.6

o

1.5

"

1.3

"'~
:;;;
a:

1100

1.8

.-

1.7

./

/'

L

1.4

/

V

~ 1.2

~_:

1.1

1.0

/

V

~ 900

t-

"'~

700

"iz

500

I-

VR = 0

Vee=- -20V
v+ '" 10V

(J

I-

0< COUT '"' 1000pF
0< lOUT <.4mA

~

.....
too

0.6

1.4

I

"'a:a:

125°C

::>

0.5

,--;~

25°C ~+--J

(J

I-

0.6

:>

V

0.2

/
0.2

0.4

(delay)

400
0

25

75

125

-75

0.3

liN'" 1 rnA (0123)
V," = 0.5V (0125)
V R '" 0
V l '" 4.5V
VEe'" -20V Vee'" lOV

1---,---+--+----1

0.8

V," - INPUT VOLTAGE (VI

-25

25

75

125

TEMPERATURE (OC)

IOUT(OFFI VS
TEMPERATURE
0123AN00125

,.---r--..---,---,

10'

1

.2,

10'

./

10'

S!
10

/

/
0.6

•

........

600

I

0.21----+-

I

z

0.4

.;

55°C

::>

~

~

z

"'Y
tOff

.........

z
2

VSAT VS TEMPERATURE
0123 AND 0125

_~R "'0
VEE '" -20V

z

~

.."

=0

lOUT

.s

TEMPERATURE (OC)

1.8

0-

i,...-'

I-"
-50

(rnA)

liN VS VIN 0123

E

I

;; 800

t O If(4mAY

~::=O_2DV-

"""- r---.

V

100
liN WEAK)

I-

.....-

TA. '" 26°C

1

<1

......r

~

300

liN = lOrnA

toff (1 rnA)

COUT '" 1 OpF

-

1000

I
I

VR:; 0
Vee'" -20V
V+,= 10V

VIN(ON) VS
TEMPERATURE 0123

o'----'----'~--'----'
-75
-25
25
75
125
TEMPERATURE (OC)

3·11

1

25

45

65

85

105

TEMPERATURE (OCI

125

D123/125
APPLICATION TIPS
Interfacing the 0123 and 0125
In order to meet all the specifications on this data sheet, certain requirements must be met by the drive circuitry.
The 0125 can be turned ON easily, but care must be exercised to insure turn-off. Keeping V L - V IN S OAV is a must to
insure turn-off. To accomplish this a shunt resistor must be added to supply the leakage current (ICES) for OTL devices.
Since ICES = 50 JJA, a OAV 10.05 mA = 8k or less should be used. For T2 L devices using a 2k resister will insure turn·off
with up to 200 jJA of leakage current.

VII *_20Y

Using the ENABLE Control
Device pins VA or V L , can be used to enable the 0123 or 0125 drivers. For the 0123the enabling driver must sink
IA(ON)X no. of channels used. For the 0125, IL(ON) X no. of channels used must be sourced with a voltage at least +4V
greater than V IN.

APPLICATIONS
Using INTERSI L'S MOS-FET SWITCH Gl17 with either the 0123 or 0125 drivers provides a reliable means of providing
up to 5 channels with a series block for multiplexing applications.

5-Channel Multiplexer

3·12

IID~D~

D129
4·Channel MOS FEY Switch
Driver with Decode

GENERAL DESCRIPTION

FEATURES

The 0129 is a 4-channel driver with binary decode input_ It
has been designed to provide the DC level-shifting required
to interface low-level logic outputs (0_7 to 2.2V) to fieldeffect transistor inputs (up to 50V peak-to-peak)_ For a 5V
input logic supply. the V- terminal can be set at any voltage between -5V and -30V_ The output transistor is capable of sinking 10mA and will stand-off up to 50V above Vin the off-state_

• Quad Three-Input Gates Decode Binary Counter to Four
Lines

•

Inputs Compatible with Low Power TTL and DTL.
'F = 200/-lA Max

The ON state of the driller is controlled by a logic "1"
(open) on all three input logic lines. while the OFF state of
the" driver is achieved by pulling anyone of the three inputs
to a logic "0" (ground)_

• Output Current Sinking Capability 10mA

•

External Pull-Up Elements Required

The 4-channel driver is internally connected such that each
one can be controlled independently or decoded from a
binary counter_

• Compatible with G 115 and G 123 Series Multichannel
MOS FET Switches which include Current-Limiter PullUp FETs

SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DO, FD-2, JD)
v+

,.

v+

IN,

13

IN,

GUT l

36"

2.6K

INPUTS

DUT 2

IN3
IN.
INS
IN6

OUT 3

OUT 4

IN,

(EACH DRIVER)
GND

V-

ORDERING INFORMATION
0129

L:
A

K

PaCkage
K - 14-pin CERDIP
L - 14-pin Flat Pak
P - 14-pin Ceramic DIP (Special Order Only)

Temperature Range
A - _55°C to +125°C
B - _20°C to +85°C

' - - - - - - - - - Device Chip Type

3-13

3

D129
ABSOLUTE MAXIMUM RATINGS
Note:

'vo - V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50V
GND - V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33V
v+ - GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
VIN - GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6V
Current (any terminal) . . . . . . . . . . . . . . . . . . . . . . 30mA
Storage Temperature. . . . . . . . . . . . . .. _65°C to +150°C
Operating Temperature . . . . . . . . . . . . . _55°C to +125°C
Power Dissipation (note) . . . . . . . . . . . . . . . . . . . 750mW
Lead Temperature (SolderinQ. 10 sec) . . . . . . . . . . . . 300°C

Dissipation rating assumes device mounted with all leads welded

or soldered to pc board in ambient temperature of 70 ce. Derate 10mW/oC
fo: III~ner ambient termperatures.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or
any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to abso·
lute maximum rating conditions for extended periods may
affect device reliability.

ELECTRICAL CHARACTERISTICS Test conditions unless otherwise specified V- = -20V, V+ = 5V
PARAMETER

0

VOL

U VOL
T 10H
I
*
I INH
N
IINL

.

T
I ton
M
E toff

CONDITIONS

I
I VIN = 2.2V, V+ = 4.5V

Output Voltage, Low

10= lOrnA

Output Voltage, Low

10= lmA

Output Current, High
Input Current
Input Voltage High

VO= 10V, V IN = 0.7V
V IN 5 V Input Under I est,
VIN=O All Other In puts

Input Current,
Input Voltage Low

VIN

Turn-ON Time

= 0,

V+

,

0.1

0.1

20

0.2

0.2

0.25

0.25

5

1

1

5

-250

-200

-160

-250

-225

-200

Logic Supply Current

V- = -20V

~ .I EE

Negative Supply Current

V+ = 5.5V

0.25

0.3

1.0

1.5
- 2.25

-2

One Channel "ON"

Logic Supply Current

10

3
All V IN = 0,

-10

All Channels "OFF"

0.75

!J.A

1

mA

+10V

IN "==t=r--'~~-+-~-oOUT

r

tf= lOOns
1r = lOOns
t pw " lJJs
f=100KHz

IN

+;:~Ov

=1-.

..

'

+10V - - - - _ _ , .
OUT
OV ~---_
_l,

.20V _ _ _ _.....::.,::..7V~-'f,.:9::;0%:::......_ _ _ ___'

3·14

mA

-25

SWITCHING TIME AND TEST CIRCUIT

3.

!J.s

3.3

* Per gate Input

+ 5V

!J.A

!J.A

= 5.5V

Turn-OFF Time
Negative Supply Current

UNIT

V

-19.8 -19.8 -19.75

See Switching Time Test Circuit

S lEE
U
P
P IL

IL

MAX LIMITS
01291
D129M
_55°C 25°C 125°C - 20°C 25°C 85°C
-19.25 -19.25 -19
~19.3 -19.3 -19

.D~DIb DG139, DD~\":1

:..~c:a~~~

Drivers with Differentially Driven
FET Switches
FEATURES

GENERAL DESCRIPTION

• Each channel complete-interfaces with most integrated logic

Each package contains a monolithic driver with differential
input and 2 or 4 discrete F ET switches. The driver may be
treated as a special purpose differential amplifier which
controls the conduction state of the FET switches. The
differential output of the driver sets the switches in opposition, one pair open and the other pair closed. All switches
may be opened by applying a positive control signal to the
V R terminal.

• Low OFF power dissipation, 1 mW
• Switches analog signals up to 20 volts peak-to-peak
• Low rOS(ON), 10 ohms max on DG145and DG146

SCHEMATIC AND LOGIC DIAGRAMS (Outline Dwgs DD, FD-2, JD)
SPOT
OG143IrOSION)
OG144(rOSION)
OG146(rOS(ONI
OG1611rOSIONI
OG1621rOSIONI

=

=
=
=
=

DPDT
8011.1
3011.1
10n)
1511.1
5011.1

v+

OG139IrOSION)
OG142IrOSION)
OG145(rOSION)
OG163(rOSION)
OG164IrOSION)

11

=
=
=
=
=

3011.1
80m
10m
1511.1
5011.1

11

11

v+

,sw,

i>--t--------<>-,~-i_<>

1.?-4+_ _ _ _ _~""-+-<>~ SW 3

~t------...".,~-H3SW2
i>--t-------~---i_<>sw.

v12

v12

ORDERING INFORMATION
DG139

L=
A

K

.

Package
K - 14-pin CERDIP
L - 14-pin Flat Pack
P - 14-pin Ceramic DIP ISpecial Order Only)
Temperature Range

A - Military _55°C to +125°C
B - Industrial _20°C to +85°C
L -_ _ _ _ _ _ _ _ _ _

Device Type

3·15

.O~DIl

D0139, D0142 -I)G146,D0161i~D0164
ABSOLUTE MAXIMUM RATINGS··
V+.,. V.,. '.' ...... 36V
Vs - V30V
v+ - Vs
30V
Vs - Vo ....... ±22V
VR - V- ........ 21V
Power Dissipation (Note)
Current (any terminal)

"11V
·14V
±6V
±6V
±6V
750mW
. . . . 30mA

Storage Temperature
. . . . . . . . . . -65 to +150°C
Operating Temperature . . . . . . . . . . . . . -55 to +125°C
. Lead Temperature (soldering, 10 sec) ........ 300°C

V+ - VR ...•.
V+ - V IN1 orVIN2
VIN1 -VIN2
VIN1 - VR .
VIN2 - VR .

NOTE: Dissipation rating assumes device is mounted with all leads

welded or soldered to printed circuit board in ambient
temperature below 70°C~ For higher temperature, derate at
rate of 10 mW(C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are ·stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ELECTRICAL CHARACTERISTICS
Applied voltages for all tests: DG139, DG142, DG143, DG144, DG145, DG146(V+ = 12V, V- = -laV, VR = 0,
VIN2 = 2.5V) and DG161, DG162, DG163, DG164 (V+ = 15V, V- = -15V, V R = 0, VIN2 = 2.5V).lnputtestcondition
that guarantees FET switch ON or OFF as specified is used for output specifications.

SYMBOL

INOTEI

N

TYPE

UNITS

-55
Input Voltage-On

2.9 min

V''NtOFFI

Input Voltage-Off

1."

IV. - V131

Oifferential Volt.

0.5 min
All CHewts

Input Current

'IN2(ONI
'IN1tOFFI

Drain-Source On R'''sunce

W
I

T

0
U
T
U

T

10(ONI

p

W

E

L
y

Orive Leakage Current

'OIOFFI

Or.in Leakage Current

1010NI"" 'SIONI

Drive Leakage Current

'S(OFFI

Source Leakage Curren!

IOIOFFI

Drain Lelk. Current

'OIONI + 'S(ON)

Drive leakage Current

'StOFF)

Source leakage Current

IDIOHI

Drain L..bge Current

+ 'S(ONI

0.5 min

2.0 min
0 .•

TEST CONDITIONS

O.Smlfl

Voll~

AtPin 9 and 13 See Figure 1 and 2. Pg. 4
Se~

Volh

AI Pm 9 and 13

VolTS

See NOle I. Pg. 4

60

60

"A

V",.I1

3 ov

60

60

"A

V 1,"2

l,QV

0.1

01

"A

V,,,",

20V

01

01

"A

V''''2

30V

80

80

150

..

30

30

60

"

OG145
OG146

10

10

20

DG161
DG163

15

15

30

DG162
OG164

50

50

100

"
"
"

FIgure 1 and 2, Pg. 4

VO'" tOY, IS'" -IOmA

DG139

DG142
OG143
OG144
OG145
OG146

OG161
OG163

Drive Leak. Current

VO'" IOV, IS'" -lOrnA

Vo

7,5V, Is

V,

-10 rnA

100

nA

Vo

100

nA

V, . IOV, Vo . -IOV

100

oA

Vo

lOV, Vs - -lOY

100

oA

VD

V, ~ -10\1

~lOV

10

1000

oA

V,

lOY, Vo

-lOY

10

1000

oA

VD

IOV, Vs

-lOV

500

nA

V D -Vs--75V

10

1000

nA

V,

10

1000

oA

Vo

2

500

oA

Vo

200

oA

V,

200

oA

V"

OG162
OG164

ISIOFF}

Source Leakage Current

'OIOFFI

Dr.in Leak... Current

'HON}

Positive Power Supply
Drain Current

4.0

mA

1:lION}

Negative Power Supply
Drain Current

-2.0

mA

IRION}

Reference Power Supply
Drain Current

-2.0

mA

'HOFF}

Positive Power Supply
Leakage Current

25

.A

':leoF .. }

Negative Power Supply
Leakage Current

-25

.A

IACOFF}

Reference Power Supply
Leakage Current

-25

.A

R

U
p.

'SION)

Source Leakage Current

'OIONI

0

+

'StOFF)

1.0

OG139
OGT44

OG143

'OSIONt

2.5 min

125

0

120

Input leakage Current
OG142

25

0

120

11I'0I2(OFf)

C
H

0

V'NIONI

IINHONI

U

.

ABSOLUTE MAX. LIMIT
CHAR'ACTERISTIC

7,5V, Vo ' -7 5V

-7.SV

7 5V. Vs
~

<

Vs

-7.5V

7.5V, V D

~

-7.-5V

7,5V. Vs

~

:...7,5V

V IN1 ' 3V

All Circuits

NOTE: (OFF) and (ON) subscript natation refers to the conduction state,of Ihe FET switch for the given test.

3-16

V IN1

o

2V

V IN ,

=

V IN2

O.SV

DG139, DG142 -

DG146, DG161

DG164

ELECTRICAL CHARACTERISTICS PER CHANNEL (cont.)
ABSOLUTE MAX. LIMIT

SYMBOL

TYPE

CHARACTERISTIC

(NOTEI

toN

OG139,DG142
OG143,OG144
OG162,DG164

Turn-On Time

126°

"'

See Below

OG139,DG142

0.7

D.•

DG139,OG142
DG143,DG144

"'

I .•

"'

00162,OG164

toFF

Turn-Off Time

I

T
C

H
I
N
G

2.°
0.8

DG143.0G144
DG162,OG164

S
W

TEST CONDITIONS

UNITS

_56°C

toN

Turn·On Time

toFF

Turn·Off Time

OG139,OG142
OG143,DG144
OG162,OG164

0.8

OGI45,DG,46
DGI6.,OGI63

1.0

DG145,OG146
DG161,OG163

O.S

00145,00146
DG161,OG163

2.S

OG145,DG146

1.2

"'
"'
"'

0 .•

See e,low

"'

1.25

DGI6',DGI63

See Below

1.•

See Below

"'

P

0
W

PON

E

P OFF

ON Driver Power

175

mW

Both Inputs V 1N ' 2.5V

1

mW

Both Inputs V IN

All Circuits

Of F Dri ... er Power

R

NOTE: (OFF) and (ON) subscript notation refers to the conduction state of the FET switch for the given test.

SWITCHING TIMES (25°C)
DG139, 142, 143, 144, 145, 146

..

\/, ,
1,' 0

"

SW 1&2

DG161, 162, 163, 164
v,~,

1. < 0.
t. < 0

1~.

,o,~.

sw

SW 1&2
OUTPUT
V.--l011

OUTPUT
II,,-,OV

SW3.4
V.·-l011

t,"O

1~.

I &2

OUTPUT
11.-1511

5W1.2
OuTPUT

SW3ll.4
OUTPUT
11.-1011

OUTPUT

~'~'o 1~.

I~.
I~.

\1,,-·1511

"
v+

1/+. 15C \1-

'1211 1/-'-1811

OFF MODEL

z

~15V

OFF MODEL
5pF (0(;161. 163,1
l1pfIOTfleRSI

'"'""tp'"''
1.7"f

''''''''.

•

LOpF

ON MODEL

ON MODEL

3·17

Ip,o'"

-

10V

II

.D~Dl6

DG139,DG142- DG146, DG16,1- DG164
FIGURE 1

FIGURE 2

A80LUTE VOLTAGE I
LEVELS FOR SWITCHING
WITHONE SIDE OPEN AND
OTHER SIDE SWITCHED AT

VOLTAGE ATPIN 13
NECeSSARv TO SWITCH
WHEN 81"5 AT-PIN 9 IS
+2.5V AT 2SoC

25~C

o

o

4

V'N (Pin 13)

VIN (Pins90r 13)

NOTE1: An example of Absolute Minimum Differential Voltage, IV. - V 1,1, is when V. = 3V and VI 3 = 2.5V, the V. side of the switch is
ON and the VI' side of the switch is OFF at 25°C. Conversely, when V. = 2V and VI' = 2.5V, the V. side of the switch is OFF and
the VI. side of the switch is ON at 25°C.

TYPICAL CHARACTERISTICS

(per channel)

OG139, 142,144,145,146
V I N1 THRESHOLD

vs TEMPERATURE

'OSION) vs TEMPERATURE

IOIOFFI vs TEMPERATURE

100

~
if.l.~

~w 1 &2AAE
if/,

Vh

ON_

I uG142. 143

ifh

-f-

IC.(;

'SW1& IAF'EO~ ~

o

"f1T

-75 -50 -25

0

25 50

1000

i'l'.& ~

"'"

lJ-+-

10

10:

75 100 125

100

I - OG139,144
OG145,146

.....

10
a

EXCEPT
OG145,146

.E

1
-75 -50-25

TEMPERATURE (C)

~§ ~

~ ~ OG145.146

~

-

0.1
0

25

50

75 100125

25

45

65

85

105

125

TEMPERATURE lOCI

OG161, 162,163,164
VINl THRESHOLD

vs TEMPERATURE

ROSIONI vs TEMPERATURE

ISIOFF) vs TEMPERATURE
1000

100
OG162,164

.;.
100

./
i-- IOG161,163

~

;;:

10

==

OG161,163

V

9

.E

o~--------~~~--~

-75 -50 -25

0

25 50

75 100 125

TEMPERATURE 1°C)

1
-75 -50 -25 0

OG162,164

0.1
25

50

75 100 125

TEMPERATURE lOCI

3-18

25

45

65

85

105

TEMPERATURE lOCI

125

DG180·191
High·Speed Driver With
Junction FET Switches

FEATURES

GENERAL. DESCRIPTION

• Constant ON-resistance for signals to ±1 OV (DG182,
185, 188, 191), to ±7.5V (all devices)
• ±15V power supplies
• <2nA leakage from signal channel In both ON and
OFF states
• TTL, DTL, RTL direct drive compatibility
• lon, loll <150ns, break-before-make action
• Cross-talk and open switch Isolation >50dB at
10MHz (7511 load)

The DG180 thru DG191 series of analog gates consists of 2
or 4 N-channel junction-type field-effect transistors (J-FET)
designed to function as electronic switches. Level-shifting
drivers enable low-level inputs (0.8 to 2V) to control the ONOFF state of each switch. The driver is designed to provide a
turn-off speed which is faster than turn-on speed, so that
break-before-make action is achieved when switching from
one channel to another. In the ON state, each switch
conducts current equally well in both directions. In the OFF
condition, the switches will block voltages up to 20V peak-topeak. Switch-OFF input-output feedthrough is >50dB down
at 10MHz, because of the low output impedance of the FETgate driving circuit.

SCHEMATIC DIAGRAM (Typical Channel)
ONE AND TWO CHANNEL SPOT AND SPST
CIRCUIT CONFIGURATION

TWO CHANNEL DPST CIRCUIT CONFIGURATION

V+

VL

V+

VL

IN

IN

S
D

II
II
GND v-

DG186/187/188 SHOWN

GND

~

_____-4._ _ _ _--'
DG183/184/185 SHOWN

v-

ORDERING INFORMATION
PART
NUMBER
DG180
DG181
DG182
DG183
DG184
DG185
DG186
DG187
DG188
DG189
DG190
DG191

DG

rOS(on)

TYPE
Dual SPST
DualSPST
DualSPST
Dual DPST
Dual DPST
Dual DPST
SPDT
SPDT
SPDT
Dual SPDT
Dual SPDT
Dual SPDT

(MAX)
10
30
75
10
30
75
10
30
75
10
30
75

181

x

Y

-L

L--_ _ _ _

P·ACKAGE
A· 11).PIN METAL CAN
L· 14-PIN FLAT PACK
p. CERAMIC DIP (Special Order Only)
K· CERDIP
TEMPERATURE
A· MILITARY -SS'C TO +12S'C
B - INDU5TRIAL-20'C TO +85'C

' - - - - - - - - - DEVICE TYPE
L--_ _ _ _ _ _ _ _

3-19

DRIVER

3

DG180·191
MAXIMUM RATINGS
V+-V- .............. 36V
V+·Vo .......•........ 33V
Vo-V- ............... 33V
VoNs ............. ±22V
VL'V- ............... 36V
Lead Temperature (Soldering.

Current (S or 0) See Note 3 ..................... 200mA
Storage Temperature ......... : ...... "':S5'Cto +150'C
Operating Temperature ..........•... ~55'C to + 125'C
Power Dissipation' ................ 450 (TW). 750 (FLAl).
B25(DIP)mW

VL-V IN •.••.•.....••... BV
VL-GND .............. BV
VlwGND .............. BV
GND·V- ............. 27V
GND·V IN .•............20V
10 sec) ........... 300'C

*Device meunted with all leads welded er seldered to. PC beard.
Derate 6mW/'C (TW); 10mW/'C (FLAT); llmW/'C (DIP) abeve
75'C.
Stresses abeve these listed under Abselute Maximum Ratings may cause permanent damage to. the device. These are stress ratings enly. and
functienal eperatien ef the device at these er any ether cenditiens abeve these indicated in the eperatienal sectiens eJ the specificatiens is net
implied. Expesure to. abso.lute maximum rating cenditiens fer extended perieds may affect device reliability.

.

.

ELECTRICAL CHARACTERISTICS (V+ = +15V V- = -15V VL =5V Unless Noted)
ASER1E~

PARAMETER

DEVICE
OG181, 182, 184, 185
187, 188, 190., 191
IOG18D, 183, 186, 1891

-1;5'C

OG182, 185, 188, 191

S

+125'C

-20'C

10.0.

B SERIES
+25'C
5

+85'C

UNITS

10.0.

H

IO(oft)

=

110.1

110.0.0.1

1151

13001

V- = -20V, VIN

="OFF"

1
110.1

10.0.

100
130.01

nA

Vs ~ 7.5V, Vo.
Y,N ~ "OFF"

-7.5V

1100.01

5
1151

1

10.0.

5

10.0.

nA

Vs ~ 10V, Vo.
Y,N ~ "OFF"

W
I
T
C

TEST CONDITIONS
INole 1)
Vs :"lDV, V o. -lDV, V+

nA

OG181, 184, 187, 190.
IOG18D, 183, 186, 1891

IS{offj

+25'C
1

I
N

=10V, Vo. = -10V, V+ =10V

1

100

5

10.0.

1100.01

1151

130.01

OG181, 184, 187, 190
IOG180, 183, 186, 1891

1
110.1

10.0.

100
1300.1

nA

1100.01

5
1151

Vs - 7.5V, Vo. - -7.5V
Y,N ~ "OFF"

1

10.0.

5

10.0.

nA

Vs

Vs
nA

OG18D, 181,183,184
186, 187, 189, 190.

-2

-200

DG182, 185, 188, 191

-2
-250.

-20.0.
-250.

10.

20.

IINL

ALL

hNH

ALL
lDn Switches

ton
D
N
A
M
I
C

toff

COloffl
Co on) + Cs on
OFF Isolation

1-

P
P
L

y

lDn Switches
3Dn and 75n Switches

CS(off)

1+

S
U

3Dn Switches
75n Switches

y

OG181, 182,184,185,
187, 188, 190., 191
IOG18D, 183, 186,1891

-250.

-250.

-10.

-200

-10.
-250.
10.

30.0.
150.

350.
180.

250.
250.
130.

30.0.
300.
150.

9 typical 121 typicall
6 typical 117 typicall
14 typical 117 typical I
Typically >50dB at 10MHz ISee Note 21

DG180, 181, 182, 189
190,191

1.5

1.5

OG183, 184, 185

0.1

0.1

OG186, 187, 188

0.8

V-

~

~

0.8

OG180, 181, 182,189,

-5.0

-5.0

OG183, 184, 185

-4.0

-4.0

OG186, 187, 188

-3.0.

-3.0

4.5

4.5

-20V, Y,N

lDV, Vo.
"OFF"

~

"OFF"

~-lDV

~

nA

Vo. - Vs - -7.5V, Y,N

-200

nA

Vo.

~

Vs

-250.

~A

Y,N

~

DV

20.

~A

Y,N

=5V

ns

See switching time test circuit

pF

Vs
Vo.
Vo.
RL

~

~

-lDV, Y,N

~

"ON"
"ON"

-1;V, 10. ~ 0., ,~ lMHz
+5V, Is - 0.,' lMHz
Vs 0,·' lMHz
750, CL 3pF

190.,191

IL

OG180, 181, 182, 183,
184, 185, 189,190., 191

IGNo.

ALL

1+

OG180, 181, 182, 189,
190,191

OG186 187 188

1-

-lDV

1101

VIN~

+ 18(on)

~

OG181, 182, 184, 185
187, 188, 190., 191
IOG18D, 183, 186, 1891

OG182, 185, 188, 191
ID(on)

~

=10V

3.2

3.2

-2.0

-2.0.

1.5

1.5

OG183, 184, 185

3.0.

3.0.

OG186 187 188

0.8

0.8

OGl80, 181, 182, 189,
190,191

-5.0

-5.0

OG183, 184, 185

-5.5

-5.5

OGl86, 187, 188

-3.0.

-3.0

4.5

4.5

IL

OGl80, 181, 182, 183,
184 185, 189, 190., 191

IGNo.

ALL

OG186, 187, 188

3.2
-2.0

Y,N

~

5V

Y,N

~

OV

rnA

3.2

-2.0.

..
" OFF " Test Cendltlens .

Note 1. See SWitching State Diagrams fer VIN " ON " and VIN
Note 2: Off Iselatien typically >55dB at lMHz fer DG180, 183, 188, 189.
Note 3: Saturatien Drain Current fer DG 180, 183, 186, 189 enly, typically 300mA (2msec Pulse Duratien). Maximum Current en all ether devices
.
(any terminal) 30mA.

3-20

DG1:80·191
ELECTRICAL CHARACTERISTICS (CONT'D)
MAXIMUM RESISTANCES (rOS(ON) MAX)

DEYICE
NUMBER
OG180
OG181
OG182
OG183
OGl84
OG185
OG186
OG187
OG1B8
OG189
OGl90
OG191

MILITARY TEMPERATURE
+125°C
-55°C
+25°C
10
10
20
30
30
60
75
75
100
10
10
20
30
30
60
75
75
150
10
10
20
30
30
60
75
75
150
10
10
20
30
30
60
75
75
150

-20°C
15
50
100
15
50
100
15
50
100
15
50
100

INDUSTRIAL
TEMPERATURE
+25°C
+85°C
15
25
50
75
100
150
15
25
50
75
100
150
15
25
50
75
100
150
15
25
50
50
100
150

CONDITIONS (Note 1)
Y+ =15Y, Y- = -15Y, YL =5Y

. UNITS

Vo = -7.5V
Vo = -7.5V
Vo = -10V
Vo = -7.5V
Vo = -7.5V
Vo = -10V
Vo = -7.5V
Vo = -7.5V
Vo = -10V
Vo = -7.5V
Vo = -7.5V
Vo = -10V

n
n
n
n
n
n
n
n
n
n
!l

n

Is

= -10mA

VIN

= "ON"

APPLICATION. HINT (for design only): Normally the minimum sigDal handling capability of the DG180 through DG191 family is 20V peak-topeak for the 751l switches and 15V peak·to-peak for the lOll and 301l switches (refer ID and Is tests above). For other Analog Signals, the
following guidelines can be used: proper switch turn-off requires that V- "VANALOG(peak) -Vp where Vp = 7.SV for the lOll and 301l switches
and Vp = S.OV for 7SIl switches e.g., -10V minimum (-peak) analog signal and a 751l switch (Yp = SV), requires that V-" -10V
-SV= -lSV.

SWITCHING TIME TEST CIRCUIT

switching time test circuit. Vo is the steady state output with
switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edge of output waveform.

Switch output waveform shown for Vs = constant with logic
input waveform as shown. Note that Vs may be + or - as per

LOGIC INPUT FOR "OFF" TO "ON" CONDITION
LOGIC 3V
INPUT
tr <10ns

(OG180/181/182

SHOWN)

1.SV

SWITCH S,
INPUT o-+----<:r

tl <10ns

SWITCH
OUTPUT

--+-~~-

__~---oVo

I30

CL

SWITCH
OUTPUT
Vo

=

Vs RL

(REPEAT TEST FOR
ALL CHANNELS)

+~~S(ONI

Vo == Vs RL +

DUAL SPST

DUAL DPST

SPDT

DUAL SPDT

DG180/181/182

DG183/184/185

DG1861187/188

DG189/190/191

TEST CONDITIONS

TEST CONDITIONS
VIN
VIN
VIN
VIN

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0Y

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0Y

TEST CONDITIONS
DG106/107/100
Channel
"ON" - 2.0V
Channel
"ON" = 0.8V
Channel
"OFF" = 2.0V
"OFF" = O.BV
Channel

SWITCH STATES ARE
FOR LOGIC "1" INPUT

3-21

PF

~~s(on)

TEST CONDITIONS
DG109/1901191

1
2
2
1

= 2.0Y

VIN
VIN
VIN
VIN

"ON" - 2.0V
"ON" = O.BV
"OFF" = 2.0V
"OFF" = O.BV

Channels
Channels
Channels
Channels

1&2
3 &4
3 &4
1 &2

SWITCH STATES ARE
FOR LOGIC "1" INPUT = 2.0Y

Bl

00180-191
I PIN CONFIGURATIONS AND SWITCHING STATE DIAGRAM (See previous page for logic input)
I
!

'

DUAL SPST (DG180, 181, 182)

Metal Can Package

Flat Package

CERDIP'

,

1.

r;;:=====::J

YL

52

NC

NC

NC

NC

y+

(OUTLINE DWG FD·2)

(OUTLINE DWG TO·100)

(OUTLINE DWG JD)

DUAL DPST (DG183, 184, 185)
Flat Package
54

c:::====::::;;:?

CERDIP'

r;:=====::J
14

53
03

v-

v+
YL c:::::=======:J"

r======~GND
(OUTLINE DWG JE)

(OUTLINE DWG FD·2)

SPOT (DG186, 187, 188)
Metal Can Package

CERDIP'

Flat Package
14

YL

NC

NC

NC

NC

0,

02

5,

52

IN

NC

v+

Y-

GND

YL

(OUTLINE DWG FD·2)

(OUTLINE DWG TO·100)

(OUTLINE DWG JD)

DUAL SPOT (DG189, 190, 191)
CERDIP'

Flat Package

5.C===:;::;:J

r;;:=====::J
14

53

IN1

v+
VL c : = = = = : J

r======:::J GND

(OUTLINE DWG FD·2)

'Side braize ceramic package available
as special order only. Consult factory.

3·22

(OUTLINE DWG JE)

DGM181·191
High-Speed
CMOS Analog Switches

GENERAL DESCRIPTION

FEATURES
• Pin and Function Replacement for OG181 Family
• Mee\s or exceeds all OG181 family specifications
with monolithic reliabillity
• Low power consumption
• 1nA leakage from signal channel in both ON and
OFF states
• TTL, OTL, RTL direct drive capability
• ton, toft < 150ns, break·before·make action
• Crosstalk and open load switch Isolation> 50dB at
10MHz (750 load)

The DGM181 family of CMOS monolithic switches utilizes
Intersil's latch·free junction isolated processing to combine
the speed of the hybrid DG181 family with the reliability and
low power consumption of a monolithic CMOS construc·
tion. These devices, therefore, are an ideal replacement for
the DG181 family.
The DGM181 family has a high state threshold of 2.4V;
devices which have a threshold of 2.0V (the DG181 speci·
fication) can be selected and are available as the DGMS
series - see ordering information.
Both series meet or exceed ali other specifications of the
DG181 family.
No quiescent power Is dissipated in either the ON or OFF
state of the switch. Maximum power supply current is 10",A
from any supply, and typical quiescent currents are in the
10nA range. OFF leakages are guaranteed to be less than
200pA at 25 ·C.

SCHEMATIC DIAGRAM (Typical Channel)
r---~-------r----~------~V+

dt

"c ...

S

V. OF DGM182

ORDERING INFORMATION
TYPE
DualSPST

Dual DPST

SPOT

Dual SPOT

STANDARD
PART
NUMBER
DGM181BX
DGM182AX
DGM182BX
DGM184BX
DGM185AX
DGM185BX
DGM187BX
DGM188AX
DGM188BX
DGM190BX
DGM191AX
DGM191BX

SELECTED
PART
NUMBER
DGMS181BX
DGMS182AX
DGMS182BX
DGMS184BX
DGMS185AX
DGMS185BX
DGMS187BX
DGMS188AX
DGMS188BX
DGMS190BX
DGMS191AX
DGMS191BX

DGM

S

181

A

A

l,~~,

rOS(on)

MAX
AT 25°C
50
50
75
50
50
75
50
50
75
50
50
75

A· 10·PIN METAL CAN
L • 14-PIN FLAT PACK
K • CERAMIC DIP
J. EPOXY DIP

' - - - - TEMPERATURE RANGE
A • MILITARY - 55 °C TO

+ 125 °C

B· INDUSTRIAL -20'C TO +8S'C

L -_ _ _ _ DEVICE TYPE
L-_ _ _ _ _ _ _ _ OPTION'

CMOS ANALOG DRIVER

3·23

3

DGM181·191
MAXIMUM RATINGS
Storage Temperature .......... , . . .. - 65'C to + 150'C
V+-V- .... "...... 36V
VL-VIN ............ 30V
Operating Temperature. .. . . . . . . . . .. - 55'C to + 125'C
V + -Vo ............ 33V
VL -VGNO ........... 20V
Power Dissipation' ............... 450 (TW). 750 (FLAl),
Vo-V - ............ 33V
VIN-VGNO .......... 20V
825 (DIP) mW
Vo-Vs ........... ±22V
GND-V- ......... 27V
VL -v - ............ 36V
GND-VIN ......... , 20V
'Device mounted with all leads welded or soldered to PC board.
Current (Any Terminal) ......................... 30mA
Derate BmW/'C (TW); 10mW/'C (FLAT); llmW/'C (DIP) above 75'C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated In the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAl. CHARACTERISTICS (v+
PARAMETER
l5(off)
S

OGMI82, 185, 188, 191

W
I
T
C
H

DEVICE
OGMI81, 184, 187, 190

ssoC

=+15V, v- = -15V, VL=5V, unless noted)
A SERIES
+25°C

+12SoC

0.2

50

OGMI82, 185, 188, 191

nA

Vs=10V, Vo- -10V
VIN = "OFF"

2.0

100

nA

VS=7.5V, Vo= -7.5V
VIN="OFF"

0.5

50

nA

Vs-l0V, VO- -10V
VIN="OFF"

5.0

100

nA

Vo-VS=

7.5V, VIN="ON"

2.0
10

50

nA

Vo=Vs=

10V, VIN - "ON"

20

10

20

,..A
,..A

VIN=OV

20

ns

See switching time test circuit

ALL
ALL
OGMI81, 184, 187, 190

1.0

y

Y

50

50
20

IINH

S
U
P
P
L

0.5

0.5
1.0

IINL

ton
tolf
C5(of~

CO(off)
CO(on) + C5(on)
OFF Isolation
1+

TEST CONDITIONS
"(Note 1)
Vs=7.5V, Vo- -7.5V
VIN =; "OFF"

50

I

C

UNITS
nA

0.2

N

I

+8SoC
100

OGMI81, 184, 187, 190
OGMI82, 185, 188, 191

N
A
M

BSERIES
+2Soc
2.0

OGMI81, 184, 187, 190

1000ff)

1000n) + l5(on)

0

-20°C

OGMI82, 185, 188, 191

250

ALL
OGMI81, 182, 184, 185,
187, 188, 190, 191

130

.

VIN=5V

180
300
150

5pF typical
6pF typical
11 pF typical
Typically >50dB at 10MHz

pF

ALL

10

100

100

I

ALL

10

100

100

IL

ALL

10

100

100

IGNO
1+

ALL

10

100

100

ALL

10

100

100

I

ALL

10

100

100

IL

ALL

10

100

100

IGND

ALL

10

100

100

Vs- -5V, 10=0, f=IMHz
Vo- -I'5V,ls-0, f_1MHz
Vo=Vs=O, f-1MHz
AL-750, CL-3pF
VIN=5V

,..A
VIN=OV

NOTE 1: See SWltchmg State Diagrams for VIN " ON " and VIN " OFF " Test Conditions.

ELECTRICAL CHARACTERISTICS
\

MAXIMUM RESISTANCES (roS(oN) MAX)

\

\
I
DEVICE
NUMBER
DGM181
DGM182
DGM184
DGM185
DGM187
DGM188
DGM190
DGM191

MILITARY TEMPERATURE
55'C
+25'C
+ 125'C
50

50

75

50

50

75

50

50

75

50

50

75

INDUSTRIAL
TEMPERATURE
-20°C
+25'C
+85'C
50
50
75
75
75
100
50
50
75
75
100
75
75
50
50
75
75
100
50
75
50
75
75
100

UNITS

11
11
11
11
11
11
11
11

CONDITIONS (Note 1)
V+ = 15V, V- = -15V, VL=5V
Vo=-7.5V
VO=-10V
Vo= -7.5V
Vo= -10V
IS= -10mA
Vo= -7.5V
VIN="ON"
Vo= -10V
Vo=-7.5V
VO= -10V

APPLICATION COMMENT: The charge Injection In these switches is of opposite polarity to that of the .standard DGl80 family, but con·
siderably smaller.

3·24

IID~DlL

DGM181·191
SWITCHING TIME TEST CIRCUIT

switching time test circuit. Vo is the steady state output with
switch on. Feedthrough via gate capacitance may result in
spikes at leading and trailing edQe of output waveform.

=

Switch output waveform shown for Vs constant with lOgic
input waveform as shown. Note that Vs may be + or - as per

LOGIC INPUT FOR "OFF" TO "ON" CONDITION (DG180/181/182 SHOWN)
LOGIC
INPUT
tr< 10n8
t,< 10n8

3V

VS--In~::-::i;:::===t=:::::,~­

SWITCH
INPUT
SWITCH
OUTPUT

0

.sWITCH
INPUT

Sl

I

---I~--I

t - - - - - i - ton

t - - - - t - toll

SWITCH
OUTPUT
--~~U--'----~~----UVO

VO=VS

RL
RL +rOS(ON)

(REPEAT TEST FOR
-15V ALL CHANNELS)

SWITCH STATES

OUALSPST

DUAL OPST

SPOT

DUAL SPOT

DGM1811182

DGM1841185

DGM1871188

DGM1901191

TEST CONDITIONS

TEST CONDITIONS

TEST CONDITIONS

TEST CONDITIONS

DGM187/188

DGM190/191
V1N"ON" 2.4V+ Channels 1 & 2
V1N"ON" O.SV
Channels 3 & 4
V1N"OFF" 2.4V+ Channels 3 & 4
V1N"OFF"
O.SV Channellll & 2

V1N"ON" = 2.4V+
V1N"ON" O.SV
V1N"OFF" 2.4V+
V1N"OFF"
O.SV

=
=
=

t

FOR SELECTED DEVICES, LOGIC "1" INPUT

= 2.0V
3·25

Channell
Channel 2
Channel 2
Channell

=
=
=
=

DGM181.191
PIN CONFIGURATIONS & SWITCHING STATE DIAGRAM
DUAL SPST (DGM181, 182)
Metal Can Package

Flat Package (FD·2)

Dual·ln·Line Package

5,

Yl

(OUTLINE DWG TO·100)

SWITCH STATES ARE FOR LOGIC "1" INPUT

(OUTLINE DWGS DD, PD)

DUAL DPST (DGM184, 185)
Flat Package

(OUTLINE DWG FD·2)

Dual·ln·Line Package

SWITCH STATES ARE FOR LOGIC "1" INPUT

(OUTLINE DWGS DE, PEl

SPDT (DGM187, 188)
Flat Package (I'D·2)

Metal Can Package
NC

c::====:::;:?

Dual·ln-Line Package

G======~NC
NC

NC

NC
Yl

y+

(OUTLINE DWG TO·100)

SWITCH STATES ARE FOR LOGIC "1" INPUT

DUAL SPDT (DGM190, 191)
Flat Package

Dual-In-Line Package

SWITCH STATES ARE FOR LOGIC ,"1" INPUT
(OUTLINE DWG FD·2j

3.26

(OUTLINE DWGS DE, PEl

DGM181-191

.'.

CHIP TOPOGRAPHIES

CONSULT
FACTORY

DGM186

DGM181/182
91x53

DGM185
91x76

DGM191
91x76

NOTE: BACKSIDE OF CHIP IS COMMON TO

3-27

v+.

B

DG200/lH5200
CMOS Dual SPST
Analog Switch••

FEATURES

GENERAl. DESCRIPTlON

• Switches Greater Than 28Vpp Signals With ± 15V
Supplies
• Break·Before-Make Switching toll 250 nsec, ton
700nsec Typical
• T2L, OTL, CMOS, PMOS Compatible
• Non-Latching With Supply Tum-Off
• Complete Monolithic Construction
• Industry Standard (OG200)
Improved Performance Version (IH5200)

The DG200IlR5200 solid state analog gates are dElsigned using an Improved, high voltage CMOS monolithic technology.
They provide ease-of-use and performance advantages not
previously available from SOlid. state switches. Destructive
latch-up of soJidstate analog gates Ms been eliminated by
INTERslL's CMOS technology:

SCHEMATIC DIAGRAM (% DG20011H5200)

The DG200is completely spec and pin-out compatible with
the industry standard device. while the IH5200 offers
significantly enhanced speCifications with respect to ON
and OFF leakage currents, switching times, and supply cur·
rent.

PIN CONFIGURATIONS
CERDIP '.EPOXY
DUAL·IN·LlNE PACKAGE

METAL CAN PACKAGE

(outline dwgs JO. PO)
Y

(outline dwg TO-lOO)
+ (SUBSTRATE AND CASE)

NC

v+
1

(SUBSTRATE)

11 NC

s.
GATE
PROTECTION
RESISTOR
INPUT

TOP VIEW

ORDERING INFORMATION

INDUSTRY IMPROVED
STANDARD
SPEC
PART
DEVICE
DG200AA
DG200AK
DG200AL
DG200BA
DG200BK
DG200BL
DG200CJ

PACKAGE

(outline dwg FO-2)
IN2

IH5200MlW 10·Pln
-55 to +125·C
Metal Can
IH5200MJD 14-Pln CERDIP -55 to +125·C
IH5200MFD 14-Pln Flat Pak -55 to +125·C
IH5200llW 10-Pln
-25 to +85·C
Metal. Can
IH5200IJD 14·Pln CERDIP -25 to .+85·C
IH5200IFD 14-Pln Flat Pak -25 to +85·C
IH5200CPD 14-Pln
Epoxy DIP

FLAT PACKAGE

TEMPERATURE
RANGE

0 to + 70·C

c::=f~$.~"~~:::J IN1

He

NC

rS~BSTRATE)

OND
NC

'Nle

7
•
TOPYIEW
SWITCH STATES ARE FOR LOGIC
"1" INPUT (POSITIYE LOGIC)

,.D~Dlb

D0200/lH5200
ABSOLUTE MAXIMUM RATINGS
v+-v- ................,.................... <33V

Current (Any Terminal) ................ , ...... >30mA

V+-Vo

<30V

Storage Temperature .............. -65·C to +150·C

Vo-V- ..................................... <30V

Operating Temperature. . . . . . . . . . . .. -5S·C to + 125·C

Vo-Vs .................................... < :±22V

Power Dissipation .......................... 450mW

VIN-GND .................................... <20V

(All Leads Soldered to a P.C. Board.) Derate 6mW/'C Above 75'C.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions above those Indicated In the operational sections of the specifica·
tlons Is not Implied, Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DG200
ELECTRICAL CHARACTERISTICS (@25·C,
PER CHANNEL
SYMBOL

CHARACTERISTIC

-SS·C

IIN(ON)

Input Logic Current
Input Logic Current
Drain-Source On
Resistance
Channel-to-Channel
rOS(On) Match

1
1
70

irNIOFF)
rOSlon)
rOS{on)

lD(oN)
+ IS{ON)
ton

Min. Analog Signal
Handling Capability
Switch OFF Leakage
Current
Switch OFF Leakage
Current
Switch ON Leakage
Current
Switch "ON" Time

toff

~INJ.)

VANALOG
IOIOFF)
IS(OFF)

OIRR

v+ = +15V, V- = -15V)

MINJMAX. LIMITS
COMMERCIAUINDUSTRIAL
MILITARY
+2S'C +12S'C 0/-2S'C +2S'C + 70 'CI +8S 'C
1
1
70

1
1
100

1
1
80

,.A
,.A

1
1
100

11
'I

25
(typ)

30
(typ)

11

±15

±15

V

2

2

100

5

5

100

nA

2

2

100

5

5

100

nA

2

2

200

10

10

200

nA

1.0

1.0

~s

Switch "OFF" Time

0.5

0.5

~s

Charge Injection
Min. Off Isolation
Rejection Ratio

15
54

20
50

mV

1000
1000
+ Power Supply
2000
Quiescent Current
- Power Supply
1000
1000
2000
IV2
Quiescent Current
Min. Channel to
CCRR
54
Chan net Cross
Coupling Rejection
Ratio
Note 1: These parameters are not tested In production.
IV1

1
1
80

TEST
UNITS CONDITIONS

f=lMHz, RL= 10011,
CLs5pF
See Fig. C, (Note 1)
VIN =OV or
VIN=5V

1000

2000

,.A

1000

1000

2000

~A

3-29

VANALOG = -14V to
+14V
VANALOG = -14V to
+14V
Vo=Vs= -14V to
+14V
RL - 1kll, VANALOG
= -10V to +10V
See Fig. A
RL = 1kll, VANALOG
= -10V to +10V
See Fig. A
See Fig. B

dB

1000

50

VIN =0.8V
VIN =2.4V
Is = lOrnA
VANALOG = ± 10V

dB

One Channel Off
(Note 1)

D02001lH5200
TEST CIRCUITS
Figure B

Figure A

ANALJOG !::UT
3V

ovIL o---Q--t>-- LOGIC

'NPUT

h
1-=

oyIL

10pF

'

3V

~~ o---Q--t>--

YOUT

,

Figure C

r-1-""

ANALOG INPUT

-

10,OOOpF

1kn

B1

510
LOGIC INPUT

(NO~_

~VOUT

-=

I

.-=

1'000

IH5200
ELECTRICAL CHARACTERISTICS (@25·C, V +
PER CHANNEL

MILITARY

SYMBOL

CHARACTERISTIC

-55·C

+25"C

11t;(ON)

Input Logic Current
Input Logic Current

1
1
70

1
1
70

I'N(OFF)
rD5(on)

Drain·Source On
Resistance

=+ 15V, V - = -15V,VREF open)

MIN./MAX. LIMITS

~

COMMERCIAUINDUSTRIAL
+.125"C O/-2S"C

+2S"C

1
1

1
1

1
1

1
1

I'A

100

80

80

100

0

25
(typ)
±15

rD5(on)

Channel·to·Channel
rOs(On) Match

VANALOG

IO(ON)
+ IS(ON)

Min. Analog Signal
Handling Capability
Switch OFF Leakage
Current
Switch OFF Leakage
Current
Switch ON Leakage
Current

ton

Switch "ON" Time

0.7

toft

Switch "OFF" Time

Q('NJ.)
OIRR

Charge Injection
Min. Off Isolation
Rejection Ratio

IV1

+ Power Supply
Quiescent Current

250

200

150

300

250

IV2

- Power Supply
Quiescent Current

10

10

100

10

10

10(oFF)
IS(OFF)

TEST

+70"C/+8S"C UNITS CONDITIONS

30
(typ)
±15

pA

V'N=O.8V
V'N =2.4V
15 = lOrnA
VANALOG = ±10V

0
V

0.2

0.2

50

1

1

50

nA

VANALOG.= -14V to
+1.4V

0.2

0.2

50

1

1

50

nA

VANALOG = -14V to
+14V

0.5

0.5

100

1

1

100

nA

Vo =Vs =·-14Vto
+14V

O.B

1'5

RL = 1kO, VANALOG
= -10V to +10V
See Fig. A

0.25

0.4

1'5

RL = 1kfl, VANALOG
= -10V to +10V
See Fig. A

5
54

10
50

mV
dB

See Fig. B
f-1MHz, RL-l000,
CL$5pF
See Fig. C, (Note 1)

200

pA

V'N=OVor
V'N=5V

100

pA

54
Min. Channel to
Channel Cross
Coupling Rejection
Ratio
Note 1: These parameters are not tested In production.

50

CCRR

3·30

dB

One Channel Off
(Note 1)

DG2001lH5200
TYPICAL CHARACTERISTICS
rOS(on) vs Vo and
Temperature
en

100

~~

50

~

"
~ Q.
~

o ~
~

"z
i~
eo

rOS(on) vs Vo and Power
Supply Voltage

~aaE~v~'~"~5V~
Y---15V

-t

i

CHIP TOPOGRAPHY

12S'C

25' C

K'H-pf~~"t-Pi

"'-V+",.15V,Y-",-15V

-SS'C

0

~Gnnjj±~

-15 -10 - 5
Yo -

0

5

10

B-Y+",.12\',Y-",-12V
C - y+ '" +10V, y- '" -10V

o

15

O-Y+",+8V,V-",-8'"

-15 -10 - 5

DRAIN VOLTAGE (VOLTS)

YO -

0

5

10

15

DRAIN VOL lAGE (VOLTS)

1"_ d,'.°_
,' . . . . • 1S(01l) or 10(011)
vs Temperature"

1000n) vs Temperature"

~i

~~11

B'

... ~

:»11:

I

~~

--_ .. ---

1

'~-

.~.

11:

UW

~~

0.1

' ,

..

§~

~

"r-

&:!:

0.01

25

4S
T -

85

85

105

..

125

TEMPERATURE ('C)

-

~

NOTE: Backside of chip of common to V+.
25

45
T -

65

85

105

125

TEMPERATURE ('C)

APPLICATIONS

Using the VREF Terminal

The DG200 has an internal voltage divider setting the
TTL threshold on the input control lines for + 15V on
V +. The schematic is shown here, with nominal
resistor values, giving approximately 2.4V on the VREF
pin. As the TTL input signal goes from + O.8V to + 2.4V,
01 and 02 switch states to turn the switch ON and OFF.

V+
Supply

(V)
+ 15
+ 12
+10
+9
+8
+7

If the power supply voltage is less than + 15V, then a
resistor needs to be added between V + and the VREF
pin, to restore + 2.4V at VREF . The table shows the value
of this resistor for various supply voltages, to maintain
TTL compatibility. If CMOS logic levels on a + 5V supply are being used, the threshold shifts are less critical,
but a separate column of suitable values is given in the
table. For logic swings of - 5V to + 5V, no resistor is
needed.

.

TTL
Resistor
(kO)

CMOS
Resistor
(kO)

-

-

100
51

-

(34)

34

(27)
18

27
18

V'(+15V)

31k~ JR."

In general, the "low" logiC level should be < O.8V to prevent 01 and 02 from both being ON together (this will
cause incorrect switch function). With open collector
logic, and a low value of pull-up resistor, the 10gic"low"
level can be aboveO.8V.ln this case, INTERSILcan supply parts with thresholds> 1.5V, allowing the user to
define the "low" as <1.5V (consult factory). The VREF
pOint should be set at least 2.6V above this "low" state,
or to > 4.1 V. An external resistor of 27kO between V +
and V REF is required, for a + 15V supply.

VR'F

F'-+t t--;--o6kO

GATE
PROTECTION
INPUT RESISTOR

3-31

J

B1

/

DG201JIH5201
Quad SPST
CMOS Analog Switches

FEATURES
~
• SWitches Greater Than 28V~-p Signals With ± 15V
Supplies
• Break·Before·Make Switching toff =.25Ons8c, ton =
Typically 500nsec
'
• TTL, OTL, CMOS, PMOS Compatible
• Non·Latchlng With Supply Turn·Off
• Complete Monolithic Construction
• Industry Standard (OG201)
1
• Improved Performance Version IH5201

GENERAL DESCRIPTION
The DG201/1H5201 solid-state analog gates are designed using an improved, high-voltage CMOS monolithic technology.
They provide ease-of-use and performance advantages not
previously available from solid-state switches. Destructive
latch-up of solid-state analog gates has been eliminated by
INTERSIL's CMOS technology.
The DG201 is completely spec and pin-out compatible with
the industry standard device, while the IH5201 offers
significantly enhanced specifications with respect to ON
and OFF leakage currents, switching times, and supply current.

SCHEMATIC DIAGRAM (% DG201/1H5201)

CHIP TOPOGRAPHY
D3

IN3

IN.

D4

NOTE: BacksIde of chip common to V +.

ORDERING INFORMATION

PIN CONFIGURATION

(outllnedwgsJE, PE)

DUAL-IN-LlNE PACKAGE
INDUSTRY
STANDARD
PART

IMPROVED
SPEC
DEVICE

DG201AK
DG201BK

IH5201MJE
IH52011JE

DG201CJ

IH520lCPE

PACKAGE
16-Pin CERDIP
16-Pin CERDIP
16-Pin
Plastic DIP

TEMPERATURE
RANGE
-55'C to +125'C
-20'C to +65'C
O'C to +70'C

SWITCH OPEN FOR LOGIC "1" INPUT

3-32

DG201/1H5201
ABSOLUTE MAXIMUM RATINGS
v+-v- ....................................
v+-vo .....................................
Vo-V- .....................................
Vo-Vs .................................... <
VREF-V - ...................................
VREF-VIN ....................................
VREF-GND ..................................
VIN-GND ........ " ..........................

<33V
<30Y
<30V
± 22V
<33V
<30V
<20V
<20V

Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . ..
Storage Temperature .............. -65·C to
Operating Temperature. . . . . . . . . . . .. -55·C to
Power Dissipation ..........................
Derate 6mW/·C Above 70·C

<30mA
+150·C
+ 125·C
450mW

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operatlor. of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

BJ

OG201
ELECTRICAL CHARACTERISTICS (@25·C, v+
PER CHANNEL
SYMBOL

CHARACTERISTIC

IIN(ON)
hN(OFF)
rOS(ON)

lo(oN)
+ls(oN)
ton

Input Logic Current
Input Logic Current
Drain-Source On
Resistance
Channel to Channel
rOS(ON) Match
Analog Signal
Handling Capability
Switch OFF Leakage
Current
Switch OFF Leakage
Current
Switch On Leakage
Current
Switch "ON" Time

toff

Switch "OFF" Time

Q(INJ.)
OIRR

Charge Injection

10'

+ Power Supply
Quiescent Current
- Power Supply
Quiescent Current
Min. Channel to
Channel Cross
Coupling Rejection
Ratio

rOS(ON)
VANALOG
lD{oFF)
lS(oFF)

= +15V, V- = -15V)

MIN./MAX. LIMITS
MILITARY
+2S·C
+12S·C

-SS·C
1
1
80

1
1
80

1
1
125

O·C
1
1
100

COMMERCIAL
+2S·C
+70·C
1
1
100

1
1
125

UNITS
~
~

25
(typ)

30
(tyP)

°
°

±15

±15

V

CCRR

1

100

5

5

100

nA

VANALOG = -14V to
+14V

1

1

100

5

5

100

nA

2

2

200

5

5

200

nA

VANALOG = -14V to
+14V
Vo=Vs= ±14V

Min. Off Isolation
Rejection Ratio

1.0

1.0

~s

RL -lkO, VANALOG
= -10V to +10V
See Fig. A

0.5

0.5

~s

15
54

20
50

mV
dB

RL = 1kO, VANALOG
= -10V to +10V
See Fig. A
See Fig. B
f=lMHz, RL= 1000,
CLs5pF
See Fig. C, (Note 1)

2000

1000

2000

2000

1000

2000

~

2000

1000

2000

2000

1000

2000

~

Note 1: These parameters not tested

VIN =0.8V
VIN =2.4V
Is-l0mA
VANALOG = ± 10V

1

"

10

TEST
CONDITIONS

54

In

50

production.

3-33

dB

VIN =OV or 5V

One Channel Off
(Note 1)

·.O~OIL

DQ201/1H5201
TEST CIRCUITS
Ftgure A

Figure B

ANALJOG !~:UT
3V

OV~ o---Q--t>- LOGIC

INPUT

hJ

OV~
3V

~:~~ o---Q--t>-

Your

.

'O,f

-=

r1-'"

Figure C

ANALOG INPUT

-

1O.000,F

'kll

)11
VP'@'MC

LOGIC INPUT

.

(NO~_

~

J

.

-=

.

':"

~vo",

1'oon

IH5201
ELECTRICAL CHARACTERISTICS (@25°C, v+ = +15V, V- = -15V)
PER CHANNEL
SYMBOL
hN(ON)
I'N(oFF)
rOS(ON)
rOS(ON)
VANALOG
lD(oFF)/
lS(oFF)
ID(ON)
+ lS(oN)
ton

CHARACTERISTIC
Input Logic Current
Input Logic Current
Drain·Source On
Resistance
Channel to Channel
roS(oN) Match
Analog Signal
Handling Capability
Switch OFF Leakage
Current
Switch ON Leakage
Current
Switch "ON" Time

toff

Switch "OFF" Time

Q(INJ.)
OIRR

Charge Injection
Min. 011 Isolation
Rejection Ratio

10-

+ Power Supply
QUiescent Current
;.,. Power Supply
Quiescent Current
Min. Channel to
Channel Cross
Coupling Rejection
Ratio

10
CCRR

MINJMAX. LIMITS
MILITARY
COMMERCIAL
O·C
-55·C
+25·C +125·C
+25·C
+70·C
1
1
1
1
1
1
1
1
1
1
1
1
75
75
100
100
100
125

UNITS

p.A
p.A
Il

25
(typ)

30
(typ)

Il

±15

±15

V

TEST
CONDITIONS
V'N=0.8V
V'N=2.4V
Is-10mA
VANALOG = ± 10V

0.2

0.2

50

1

1

50

nA

VANALOG= -14V to
+14V

0.5

0.5

100

1

1

100

nA

Vo=Vs=.±14V

0.5

0.75

,,5

0.25

0.3

,,5

5
54

10
50

mV
dB

See Fig. B
1= 1MHz, RL -1001l,
CLs5pF
See Fig. C, (Note 1)
Y,N =OV to 5V

1000

750

600

1500

1000

1000

p.A

10

10

100

'20

20

200

p.A

50

54

Note 1: These parameters not tested in production.

3-34

dB

RL = 1kll, VANALOG
= -10V to +10V
See Fig. A
RL - 1kll, VANALOG
=-10Vto +10V
See Fig. A

One Channel Off
(Note 1)

5Hl

DG20111H5201
TYPICAL CHARACTERISTICS

w_

li! ~
:::>%
lilB
-w

V+=+15V
V-=-15V

100

55"C

o

-15 -10 -5

=sA

I-

I-=~F:

r-

o r-

0

10

A
B
c
0

_
-

+15V, V - = -15V
+12V, V- = -12V
+10V, v- -10V
+8V, v- -8V

v+
v+
v+
v+

=
=

'-15 -10 - 5

15

VD -

VD - DRAIN VOLTAGE (VOLTS)

C

~

C

25" C t-::P"~

50

~a:

~Z
eo

L

125"C rl--t;:

Zo

;;;:Z
:§~
~ji

D

11

0

5

10

15

DRAIN VOLTAGE (VOLTS)

10 _ _

.s
........
WZ

f"

ZW

za:

j!!g;

'2;:io.l.1Ilt

00

I~

1

§~.....

L

z

o

0.01

'-:-L....l:---'---::':-"--::'::-...'-:..l..-L-:-'
25

45

65

85

105

1

125

45

T - TEMPERATURE ("C)

65

85

105

125

T - TEMPERATURE ("C)

APPLICATIONS

Using the VREF Terminal

The DG201 has an internal voltage divider setting the
TTL threshold on the input control lines for + 15V on
V +. The schematic is shown here, with nominal
resistor values, giving approximately 2.4V on the V REF
pin. As theTTL input signal goes from + O.BV to +2.4V,
01 and 02 switch states to turn the switch ON and OFF.
If the power supply voltage is less than + 15V, then a
resistor needs to be added between V + and the V REF
pin, to restore + 2.4V at VREF. The table shows the. value
of this resistor for various supply voltages, to maintain
TTL compatibility. If CMOS logic levels on a + 5V supply are being used, the threshold shifts are less critical,
but a separate column of suitable values is given in the
table. For logic swings of - 5V to + 5V, no resistor is
needed.
In general, the "low" logic level should be < O.BV to prevent 01 and 02 from both being ON together (this will
cause incorrect switch function). With open collector
logic, and a low value of pull-up resistor, the logic "low"
level can beaboveO.BV.ln this case, INTERSILcan supply parts with thresholds > 1.5V, allowing the user to
define the "low" as < 1.5V (consult factory). The VREF
pOint should be set at least 2.6V above this "low" state,
or to > 4.1V. An external resistor of 27kO between V +
and V REF is required, for a + 15V supply.

3-35

V+
Supply
(V)

+15
+12
+10
+9
+8
+7

TTL
Resistor

CMOS
Resistor

(kll)

(kO)

-

-

100
51

-

(34)

34

(27)
18

27
18

V+(+15V)

GATE
PROTECTION
INPUT RESISTOR

IH5009 - IH5024
Virtual Ground
Analog Switches
FEATURES

GENERAL DESCRIPTION

• Switches Analog Signals up to 20 Volts Peak·to·
Peak

The IH5009 series of analog switches were designed to fill
the need for an easy-to-use, inexpensive switch for both Industrial and military applications. Although low cost is a
primary design objective, performance and versatility have
not been sacrificed.

• Each Channel Complete - Interfaces with Most
Integrated Logic
• Switching Speeds Less than 0.5",8

Each package contains up to four channels of analog
gating and is designed to eliminate the need for an external driver. The odd numbered devices are designed to be
driven directly from T2L open collector logic (15 volts)
while the even numbered devices are driven directly from
low level T2L logic (5 volts). Each channel simulates a
SPOT switch. SPST switch action is obtained by leaving
the diode cathode unconnected; for SPOT action, the
cathodashould be grounded (OV). The parts are intended
for high performance multiplexing and commutating
usage. A logic "O"turns the channel ON and a logic "1"
turns the channel OFF.

• IO(OFF) Less than 500pA Typical at 70'C
• Effective rds(ON) - 50 to 500
Commercial and Military Temperature Range
Operation

III.
. •
1:1

PIN CONNECTIONS
IH5011 (rOS(ON):51000) (OUTLINE)
IH5012 (rOS(ON):51500) \o~~~,SJE
16 PIN DIP

IH5009 (rOS(ON) :51000) (OUTLINE)
IH5010 (rOS(ON):51500) oc?~g,SJO
14 PIN DIP

o-+--~---;.if

2

IH5015 (rOS(ON):51000) ~OUTLlNE)
IH5016 (rOS(ON):51500)
O~~~,SJE
16 PIN DIP

2

7

&.-------+--0.

IH5013 (rOS(ON)',1000)
IH5014 (rOS(ON):51500)
14 PIN DIP

OUTLINE)

OWGS
PE, JE

~O,

6 o-+--~-.j.ifl

7

IH5017 (rOS(ON):51000) (OUTLINE)
IH5018 (rOS(ON):51500) oJl~~sJO
8 PIN DIP
, ,

IH5019 (rOs(oN):51000)
IH5020 (rOS(ON) :51500)
8 PIN DIP

10

IH5021 (rOS(ON):51000)
IH5022 (roS(oN):51500)
8 PIN DIP

(

(OUTLINE')
OWGS
~O, PA, JO

IH5023 (rOS(ON):51000) (OUTLINE)
IH5024 (roS(ON):51500)
OWGS
8 PIN DIP
DE, PA

I:,;.,
(Note: Numbers in brackets refer to CEROIP packages.) .

3-36

OUTLINE)
( OWGS
DE, PA. JE

.D~DIb

IH5009- IH5024

Operating Temperature
5009C Series, , , , , , , , , , , , , , ' , , .. , , , , , , " 0 'C to + 70 'c
5009M Series, , , , , , .. , , , .... , , .. , " - 55 'c to + 125 'c
Lead Temperature (Soldering, 10 sec) ""',""" ,300'C

ABSOLUTE MAXIMUM RATINGS
Positive Analog Signal Voltage"",,"""""""" 30V
Negative Analog Signal Voltage" " " " " , " " " " -15V
Diode Current"","""""""""""" ""',' 10mA
Power Dissipation (Note) , , ' , , ' , , , , , , , , , " , , , , , " 500mW
Storage Temperature ...... , .... , '.... - 65 'c to + 150 'c
Lead Temperature (Soldering, 10 sec)"""""", 300'C

NOTE: Dissipation rating assumes device is mounted with all leads welded
or soldered to printed circuit board in ambient temperature below
75°C. For higher temperature, derate at rate of 5mWf °c.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and funotional operation of the device at these or any other conditions above those .indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (per channel)
SPECIFICATION LIMIT
SYMBOL
(Not. 11

CHARACTERISTIC

CONDITIONS

- ss·c (MI
O·C (C)

(Note 2)

MINIMAX

TEST

TYPE

(Not. 4)

+12S"C 1M)
+ lOGe (e)

25°C

TVP.

MINIMAX

UNITS

MINIMAX

"N(ON)

Input Current-ON

All

V'N=OV,IO=2mA

0,1

01

0,1

100

pA

IIN(OFF)

Input Current·OFF

5V Logic Ckts

VIN"" +4.SV, VA= ± IOV

0.2

.04

0.1

10

nA

15V LogiC Ckts

04

0.2

10

nA

"N(OFF)

Input Current·OFF

VIN'" +11V, VA= ±10V

0.2

V,NION)

Channel Control Voltage·ON

fN LogiC Ckts

See Figure 5, Nole 3

0.5

05

0.5

V

V'NIONi

Channel Control Voltage-ON

15V Logie Ckts

See Figure 6, Note 3

1.5

1.5

1.5

V
V

I/IN(OFF)

Channel Control yoltage-OFF

5V Logic Ckts

See Figure 5, Note 3

4'.5

4.5

4.5

V'NIOFF)

Channel Control .;voltage-OFF

15V Logic Ckts

See Figure 6, Note 3

11.0

11.0

11.0

IOIOFFI

Leakage Current·OFF

5V Logic Ckts

V'N=+4.5V,VA=±10V

0.2

IO(OFF)

Leakage Current·OFF

15V Logic Ckts

VIN = + 11V, VA = ± 10V

'OION)

Leakage Current·ON

5V Logic Ckts

VIN=OV,ls=1mA

IOION)

Leakage Current·ON

15V Logic Ckts

'OION)

Leakage Current·ON

'O(ON)

Leakage Current-ON

foS(ON)

Drain-Source ON·Resistance

roS(ON)

Orain.Source ON.Resist'ance

~on)1

Turn-ON Time

All

See Figures 3 & 4

I(off)

Turn-OFF Time

All

5ee Figures 3 & 4

300

500

CT

Cross Talt(

All

t = 100Hz

120

-

V

02

0,2

0.2

.02

1.0

0.30

VtN=OV,IS=lmA

0,5

0.10

5V Logic Ckts

VIN=OV,IS=2mA

1.0

1.0

10

pA

15V Logie Ckts

VIN = OV, IS = 2mA

2.0

2.0

1000

nA

5V Logic Ckts
15V Logic Ckts

10 = 2mA, VIN =0.5V

10 = 2mA, VIN = 1.5V

150
100

10

nA

0.2

10

nA

1,0

1000 1M)

0.5

500 1M)
l00lc)

nA

200,e)

90

150

385 1M)

60

100

250 1M)
160lCl

150

500

nA

n

240 (C)

n
ns
ns
dB

NOTE 1: (OFF) and (ON) subscrlpl nOlaUon refers 10 Ihe conducllon slale of Ihe FET switch for Ihe given lesl,
NOTE 2: Refer to Figure 2 for definition of lerms,

NOTE 3: VIN(ON) and V1N(OFF) are test conditions guaranteed by the tests of respectively r05(ON) and ID(OFF)'
NOTE 4: "5V logic CKTS" applies 10 even-numbered devices,

"15V LOQlc CKTS" applies to odd-numbered devices.

ORDERING INFORMATION

I

IH50XX

,

L
M

DE

LPACKAGE

CHANNELS

LOGIC
LEVEL

IH5009

4

+15

JD,DD,PO'

IH5Q10

4

+ 5

JO,DO,PD

IH5011

4

+15

JE,OE,PE

IH5012

4

+ 5

JE,DE,PE

IH5013

3

+15

JD,DD,PO

IH5014

3

+ 5

JO,DD,PD

IH5015

3

+15

JE,DE,PE

"iH5016

3

+ 5

JE,DE,PE

IH5017

2

+15

JO,DD,PA

IH5018

2

+ 5

JD,DD,PA

IH5019

2

+15

JE,DE,PA

IH5020

2

+ 5

JE,OE,PA

BASIC
PART NUMBER

4
~~

PE
DO
DE
JD
JE

=1::~:~ ~~~~~:g ~:~
-

IS· PIN
14·PIN
16-PIN
14-PIN
IS-PIN

PLASTIC DIP
CERAMIC DIP (Special Order Only)
CERAMIC DIP ISpecl.' Order Only)
CERDIP
CEROIP

TEMPERATURE RANGE
M=MtUTARY(-55°Cto +125°C)
C = COMMERCIAL (DOC to + 70°C)

BASIC PART NUMBER

~-

1

+15

JD,DD,PA

IH5022

1

+ 5

JD,DO,PA

)H5023

1

'+15

JE,DE,PA

~5024

1

+ 5

JE,OE,PA

NOTE: Mit-Temperature range (_55°C to
ceramic packages only.

3-37

PACKAGES

+ 125°C) avaIlable

IH5009 - IH5024
TYPICAL ELECTRICAL CHARACTERISTICS (per channel)

1,1000

ID~OFF)

'OIONI VS.ISAT 25'C

-

III

I

ffi
a:
100

~

~

~
!
EJ

~OO.5

Is

V

I

~

Y;--

1.0
1.5
2.0
2.5
II - SOURCE CURRENT (rnA)

a~

100

~

10

'5
75
TEMPERATURE C C)

.9

ill
o

V'

~ 1.2

~

Q

1-1l -I -

~
0:

v

OF FREQUENCY

,

-120

-110

.~

~o

5

0.6

o

25
50
75
TEMPERATURE ( C)

100

10 kn

-,
'\

I'\.

~ -90

/'

~ 1.0

~O.8

CROSSTALK AS A FUNCTION

-130

~-100

~

100

CROSSTALK MEASUREMENT CIRCUIT

ROS!ONt VS. TEMPERATURE
(NORMALIZED TO 25' C VALUE)

V 1.4

vs. nMPERATURE

.!~ lDDkg~~~~~~~~

~I

ia

'OION) VS. TEMPERATURE

=::

Your

I'\.

-60

'"

-50

-.0
-3.

10

100

lK

10K

lOOK

V ,N

1M
+5V (5010 ETC)

FREQUENCY (Hz)

+ 15V (500D eTC)

DEVICE SCHEMATICS AND PIN CONNECTIONS
FOUR CHANNEL
IH5009 (rOSION):5 100!!)
IH5010 (rosION):5150!!)
14 PIN DIP

THREE CHANNEL

IH5011 (rOSION1 :5 100!!)
IH5012 (rOSIONI:5 150!!)
16 PIN DIP

IH5013 (rOSION1 :5 100U)
IH5014 (rOSIONI:5 150U)
14 PIN DIP

3..-u--'"

IT
IT
6

IH5015 ('osiONI :5100U)
IH5016 ('OSIONI:5150!!)
16 PIN DIP

t.

J"

6.---v-o S

S

t5 ' b7',

r--4--o11

IT.

1'.---v-0 9
1,2 ~'0

10

IT
SINGLE CHANNEL

TWO CHANNEL
IH5017 (rosION):5100!!)
IH5018 (rOSIONI:5 150!!)
8 PIN DIP

IH5019 (rOSION1 :5 10012)
IH5020 (rOSIONI:5 15012)
8 PIN DIP

30--;---u--0 1
t. !,

IH5021 (rOSIONI :5100U)
IH502:? (rOSIONI :515012)
8 PIN DIP

IH5023 (rOSION) :5100U)
IH5024 ('osION):5150U)
8 PIN DIP

'~.

3TT
., '

3

6~S

t5

b7
3·38

1

•

IH5009 -

IH5024

THEORY OF OPERATION
The signals seen at the drain of a junction FET type
analog switch can be arbitrarily divided into two
categories; those which are less than ± 200mV, and
those which are greater than± 200mV. The former
category includes all those circuits where switching
is performed at the virtual ground pOint of an op-amp,
and it is primarily towards these applications that
the IH5009 family of circuits is directed.

Clearly, the gain error caused by the switch is dependent on the match between the FETs rather than the
absolute value of the FET on-resistance. For the
standard product, all the FETs in a given package are
guaranteed to match within 50!!. Selections down to
5!! are available however. Contact factory for details.
Since the absolute value of rOSION) is guaranteed only
to be less than 100!1 or 150!!, a substantial improvement in gain accuracy can be obtained by using the
compensating FET.

By limiting the analog signal at the switching point
to ± 200mV, no external driver is required and the
need for additional power supplies is eliminated.

DEFINITION OF TERMS

Devices are available with both common drains and
with uncommitted drains.
Those devices which feature common drains have
another FET in addition to the channel switches. This
FET, which has gate and source connected such that
VGS 0, is intended to compensate for the on·
resistance of the switch. When placed in series with
the feedback resistor (Figure 1) the gain is given by

=

10k!l + rOSION) (compensator)

GAIN

10k!l + ros (switch)

Figure 2,

NOISE IMMUNITY
The advantage of SPDT switching is high noise immunity when the series elements is OFF. For example,
if a ± 10V analog input is being switched by T2L open
collector logic, the series switch is OFF when the
logic level is at + 15 volts. At this time. the diode con·
ducts and holds the source at approximately + 0.7
volts with an AC impedance to ground of 25 ohms.
Thus random noise superimposed on the + 10 volt
analog input will not falsely trigger the FET since the
noise voltage will be shunted to ground.
When switching a negative voltage, the input further
increases the OFF voltage beyond pinch-off, so there
is no danger of the FET turning on.

Figure 1. Use of Compensation FET

SWITCHING CHARACTERISTICS
VA

= ~

VA

lOV

+15V

~
S

"IN
PW=S,IU

OUTPUT
VA"10V

,

~

EOUT (CL .. 10 pFI

G

VIN

0

":"

15Vr-----_,,
7.5V

+ sv

ovSL

0

":'

'r 

"

tOfF

tON

II

FET "ON" FOR VIN -.: 1.5V

FET "OFF" FOR VIN

II
14.0V
+15V

ov.rl.
Figure 1

Figure 2

+5V

vou~OSCOPE

rn

PROBE (lOX)

'::'

I'O,OOOP'

lOOn

Your
TO SCOPE PROBE

(lOX)

~: ~~::

+15V

OVn.

,=

•

@

1 Kn

+15V

1 KC

Figure 4

Figure 3

3·43

II

IH5025 -

IH5038

DEVICE SCHEMATICS

FOUR CHANNEL
IH5025 (rOS{ON) S 1000)
IH5026 (rOs(oN)s1501J)
14 PIN DIP

THREE CHANNEL
IH5029 (rOS(ON) S 1000)
I H5030 (rOS(ON) S 1500)
14 PIN DIP

IH5027 (rOS(ON) S 1000)
·IH5028 (rOS(ON)s1500)
16 PIN DIP

IH5031 (rOS(ON) S 1000)
IH5032 (rOs(oN)sl501l)
16 PIN DIP

11

11

10

10
13

12

14

SINGLE CHANNEL

TWO CHANNEL
IH5033 (rOs(oN)s1000)
IH5034 (rOS(ON)s1500)
8 PIN DIP

4(4)
5(11)

IH5035 (rOS(ON) S 1000)
IH5036 (rOs(oN)s1501J)
8 PIN DIP

""n~
(2)2

6(12)

8(14)

4(4)

""H'' '
7(15)

5(13)

Numbers In parentheses indicate CERAMIC PACKAGE LAYOUT

3·44

IH5037 (ros(oN)s1000)
IH5038 (rOS(ON) S 1500)
8 PIN DIP

~n'"
3(3)

1(1)

IH5025 -

.D~DJL

IH5038

THEORY OF OPERATION
The IH5025 series differs from the IH5009 series In that
they may be driven by floating outputs. This family Is
generally used when operating Into the-non-inverting Input
of an operational amplifier, while the IH5009 series Is used
In operations where the output feeds into the inverting (virtual ground) Input.

put, 1.1V of margin exists for turn-bff. When the IH5025 is
used with 5V TTL logic, a maximum of + 1V can be switched.
The gate of each FET has been brought out so that a
"referral resistor" can be placed between gate and source.
This is used to minimize charge injection effects. The connection is shown below:

The IH5025 model is a basic charge area switching device,
In that proper gating action depends upon the capacity vs.
voltage relationship for the diode junctions. This C vs. V,
when Integrated, produces total charge Q. It is Q total which
is switched between the series diode and the gate to
source and gate to drain junctions. The charge area (C vs. V)
for the diode has been chosen to be a minimum of four (4)
times the area of the gate to source junction, thus providing
adequate safety margins to insure proper switching action.
If normal logical voltage levels of ground to + 15V (open
collector TTL) are used, only signals which are between OV
and + 10V can be switched. The pinch-off range of the
P-Channel FET has been selected between 2.0V and 3.9V;
thus with + 15V at the logical input, and a + 10V signal in-

FROM

TTL OUTPUT

For switching levels> + 10V, the + 15V power supply must
be increased so that there is a minimum of 5V of difference
between supply and signal. For example, to switch + 15V
level, + 20V TTL supply is required. Up to + 20V levels can
be gated.

LOGIC INTERFACE CIRCUITS
When operating with TTL logic it is necessary to use pull-up resistors as shown in Figures 6 and 7. This ensures the
necessary positive voltages for proper gating action.

r- -- ------, '5V

r - - - - - -,

I

I
I
I

I
I

+15V

I
I
I
I

I
I

I

I

I
I
I

I

I

I

_

L.5~T":' G~T~

____ ...J

~"--TT.':..G~E

I

_":" I

____ -.J

Figure 5. Interfacing with + 5V Logic

Figure 6. Interfacing with +15V
Open Collector Logic

3-45

3

IH5025-- IH5038
APPLICATIONS

r--------~-.,.25V

I

SIGNAL

I

OV TO +2OV

INPUT

I

VANAlOG

0- lOV

IREXT

ilz KG
ITO

110 K!l.'

I

.3v

1

OV.r'1..

1

+15V

I

ov.r1.

1

I
I

k.o':..T~~!!,_::'

____ J

+15V

ov.n..
Figure 7. Multiplexer from
Positive Output
Transducers

Figure 8. Sample and Hold Switch

Figure 9. Switching up to +20V
Signals with T2L Logic

r----- - -- --'+15V
1

I

I

I

I

jREXT

I

I(1KS!
TO

I

I
I
I

110Knl

I

+15V

¢SHIFT' 1.0@10Hz
"SHIFT O.16@100Hz

lJov

.3V

ov..r-L

I

_

L!5y"Tll

~li.

":"

_____ ..J

+3V

OV

+3V

~~_-,."O","V_ _->r:-;-::J_l
ms-''--__ J~~u~OGlC
TTL

+15V

OUTPUT

__ .l0t1l1rtfl0rfIlHI\...U_ _ _ _ _--'A'ttIr.tffttJr.~ltftr_- ~~v OP. AMP.

Iflfv Vw l [ v VVV

NOTE: TO SWITCH !10 VAC (20"",,): (1) INCA EASE
(2) INCREASE TTL SUPPLY FROM +15V TO +26V.

~5V

-SV OUTPUT

SUPPLY TO .10V.

Figure 10. Swltching~ Bipolar Signals with T2L Logic

3-46

UP TO +20V
VOUT ~v

IH5025 - IH5038
APPLICATIONS (Cont.)
'1OV SIGNAL
INPUT

r---------,+15V

+3V

I

OV~;~;UT

I

I

+3V

ov.fI..

JL
+16V

2N2907
TYPE OR
2N3638

I
I

INPUT

OV

GATE
STROBE

I

T2L

+15V~T'L
OUTPUT

10KU

I

I
I

GATE
STROBE

-15V

~

+10V

I

~V2.T~A.!!!_-_ _ :....J
ADVANTAGES OVER FIGURE NO. 10 METHOD
A. DC LEVELS OF uP TO ! lOV CAN BE SWITCHED, AS WELL AS
AC SIGNALS UP TO 100 KC; NO. 10 METHOD SWITCKES aNL V

AC RANGE OF 10 Hl TO 10 kHl.
B. CKT IS NOW BREAK BEFORE MAKE

VOUT

-10V

DISAOVANTAGES:
A. PNP CKT DRAWS 3 mA, WHEN ON; THUS ~DDS 3 rnA X 30V '" 90 mW
POWEROIss.
8, toN TIME WILL BE CONSIDERABl V SLOWED OOWN FROM 100 ns
(BEFORE IN FIGURE NO. 10) TO 1 • 2 ~s NOW.

Figure 11. Switching Bipolar Signals with T2L Logic (Alternate Method)

2.

2"

2"

LSD

13
10K

5K

2N3638
TVPE

+3V
5K

ov

SID!!

T2L INPUT
+15V

T2L
OUTPUT

+15V

T'L

r - - - - - - j + 1 5 V OUTPUT

+3V

o~
T'L

INPUT

I

I

I

I

I
I

I
I

I

I

I

I

r ---- - -

1+15V

I
I

-lOV

LADDER
VOLTAGE

I
I
I

I

LOGIC

I
I..!!'!..!.T~A!!.

I INPUT
I (V ,N '
I
_ _ I Figure 12.
..:. _ ~ ..J

o

A
FROM CONTROL

LOO",

Using the IH5028 as a Dual SPOT to Drive
Ladder Networks for Bipolar Switching (up to ± 10V)

i.e. CHANNEL B. C. D. INPUTS ,- +15V;
CHANNEL A INPUT = OV
SIGNAL OUTPUT
Rf + RA X SIGNAL INPUT

NOTE:

"A

WHEN SWITCHING 1+1 OR I-I SIGNAL INPUTS,A SCHEME
SIMILAR TO FIGURES 10 OR l' SHOULD BE USED.

Figure 13. Gain Control with High Input Impedance

3·47

,

IH5040·IH5051 Family
High Level CMOS
Analog Gates
GENERAL DESCRIPTION

FEATURES
• Switches Greater Than 20Vpp Signals With ±15V Supplies
• Qu iescent Current Less Than l/JA
• Overvoltage Protection to ±25V
• Break-Before-Make Switching toft 200 nsec, ton 300 nsec
Typical
• T2L, DTL, CMOS, PMOS Compatible
• Non-Latching With Supply Turn-Off
• Low rDS(on) - 35,Q
• New DPDT & 4PST Configurations
• Complete Monolithic Construction
IH5040through IH5047

FUNCTIONAL DIAGRAM

. The IH5040 family of solid state analog gates are designed
using an improved, high voltage CMOS monolithic technology. These devices provide ease-of-use and performance advantages not previously available from solid state
switches. This improved CMOS technology provides input
overvoltage capability to ±25 volts without damage to the
device, and destructive latch-up of solid state analog gates
has been eliminated . Early CMOS gates were destroyed when
power supplies were remo~ed with an input signal present.
ThelH5040 CMOS technology has eliminated this serious
systems problem.
Key performance advantages' of the 5040 series are TTL
compatibility and ultra low-power operation. The quiescent current requirement .is less than l/JA. Also designed
into the 5040 is guaranteed Break-Before-Make switching,
which is accomplished by extending the ton time (300 nsec
TYP.) so that it exceeds toff time (200 nsec TYP.). This
insures that an ON channel will be. turned OFF before an
OFF channel can turn ON . This eliminates the need for external logic required to avoid channel to channel shorting
during switching.
Many of the 5040 series improve upon and are pin-for-pin
and electrical replacements for other solid state switches.

FUNCTIONAL DESCRIPTION
INTERSIL
PART NO.
IH5040
I Hs041
I HS042
I HS043
I HS044
I HS04S
IH5046
IH5047
IHS04~ Dual
IHS049 Dual
I HSOSO
IHSOSI Dual

7

v-

FIGURE 1. TYPICAL DRIVER. GATE - IH5042

TYPE
SPST
Dual SPST
SPOT
Dual SPOT
OPST
Dual OPST
OPOT
4PST
SPST
DPST
SPDT
SPOT

rOS(on)
7SI1
7SI1
7SI1
7SI1
7SI1
7Sl1
7SI1
7SI1
3SI1
3SI1
3SI1
3SI1

PIN/FUNCTIONAL
EaUIVALENT
(Note 1)

OG 188AA/BA
OG 191 AP/BP
OG 185AP/BP

DG 184AP/BP
DG 187AA/BA
OG 190AP/BP

ORDERING INFORMATION
IH5040 M

NOTE 1. See Switqhing State diagrams for applicable package
equivalency.

JE
Package

.
[

.

Pin andfunctional equivalent monolithic versions of the OG181,
DG182, DG187 and DG188 are available. See data sheet for
this and also IH181 tolHl91.

. ~~_; ~6~:.~~e~~:i~a~'P (Special Order Only)
JE - 16-Pin CEROIP

PE - l6·Pin Plastic DIP
TW - TO·l00 Metal Can (lH504l/2. IH5044.
IH5048. IH50.50 Only)
Temperature Range
M - Military _55°C to +12S C
Q

C - Commercial

oOe to +7-)h
1O,F

I "'"

VOUT

Il
i~p';;i

o-D-t>-lC
I

"n

1O.00M

m
V

("'IMC
""
"'v

LOGIC INPUT

IN~ __

VOUT

-

51!!
'

-=-::-

l---oVOUT

1'00,"

NOTE 1: Some channels are turned on by high "'" logic inputs and other channels are turned on by low "0" inputs; however O.8V to 2.4V
describes the min. range for switching properly. Refer to logic diagrams to see absolute valu~ of logic input required to produce

"ON" or "OFF" state.

3-49

IH5040·IH5051 Family
TYPICAL ELECTRICAL CHARACTERISTICS (Per Channe'l)
100

1=

160

~ Monolithic

I

!- Hybrid

80

140

+12~QC..;..

60

-

+25°C

~

~

J5°C

40

F-

--

II-

-j;.C
I
0

~

~

--

5

7.5 -7.5

80

"~V

60

±15V

20

15V SUPPLIES

@:!:

--

l

"1",

40

--~~--IS= lmA

2.5

MOllolithk:
; ; HYbrid

100

§

~

+25"C

-10 -5 -2.5

t;

120

------ -~tO:c ?-

---

20

CHARGE INJECTION V5 V ANALOG
(SEE FIG. B) C L = 10,OOOpF

rOS(on) vs
POWER SUPPL Y VOLTAGE

rOS(on) vs VANALOG SIGNAL

10

VAN.~LOG {VI

I-""

g

~

E. 25
hl 20~~~--+--+--~~~--~
Z
<5

~

I

±lfV

0

2.5

5

7.5

r-1--t--r-1--t--r-+--i

15~~~__+--+__~~~__~

_.J,.- ---- -- ~r= =

-10 -7.5 -5 -2.5

30

>

10

10

~::t:t::E:TI
Ii::::±::::
----

-10 -7.5 -5 -2,5

0

2.5

VANALOG ~VI

VANALOG {VI

FIGURE 0
CROSS COUPLING
REJECTION vs FREQUENCY
120

100

~

~:-

1-. I

f'i-..r-.

!
80

I
60

I

I
!

I

,

i

I

I

!

;

I

I'h-

i

1

~~'20L~G
10

100

I
10k

lOOk

I

I

I

I

1

:

I

I

I -=
'- -r-+-_-...,

I

JL~

~~~~~~~

•

v~~O:::;PI

lk

\

~

i

40

20

I

g~~NNEL~_;r:llVOUT
J

lOon

I

L-'---~1J

51n

lOon

1M

FIGURE E

FREOUENCY (Hz)

OFF ISOLATION vs FREQUENCY

51ft

OFF STATE

~

OEPENOSONPART~-

t--o,',VOUT
1'oon '

1Hz

10Hz 100Hz

lk

10k

lOOk

1M

FIGURE F

FREQUENCY (Hz)

POWER SUPPLY QUIESCENT CURRENT
"" LOGIC FREQUENCY RATE

1 1000
S

ll:

iil

100

~

0
~

r

>~
>-

10

~

~

5
!?
10

100

1k

10k

lOOk

lOGIC FREQUENCY@tO%DUTYCYCLE (Hz)

FIGUREG

3-50

5

7.5

10

IH5040"IH5051 Family
SWITCHING STATE DIAGRAMS
SWITCH STATES
ARE FOR LOGIC "I" INPUT

SPST

IHS040 ('OS(on)

< 7Sn)

(OUTLINE DWG
FD·2)

(OUTLINE DWGS
DE, JE, PEl

(OUTLINE DWG TO·l00)

.o~nlL.

IH5040·IH5051 Family
SWITCHING STATE DIAGRAMS (Cont.>
SWITCH STATES
ARE FOR LOGIC "I" INPUT

FLAT PACKAGE (FD·2)

v,

s,

D,

S,

D,

S3
S,

v'

v'

v,

OPOT
IH5046 ('OS (ON) <7511)

TO·l00

DIP (DE) PACKAGE

S
I
_J

5,

D,

S,

D,

D3
D,

S3

D3

s,

D,

5,

D,

01

s,

0,

S,

D,

S,

D,

GN'D

4PST
IH5047 ('OS (ON) <7511)

v,

?"

v·

?,

;-v

S,

s,

;v °2

S3

II

4-v 0 3

s,

.......

6"

_J

-v D,

6"

GND

v,

DUAL SPST
IH5048 ('OS (ON) <3511)

v,
s,

S,

D,

'"

v,

S,

D,

'"
'N,

-,

'"

v'

v'

D,

v'

,

S,

D,

'N,

",

S,

D,

,

S,

D,

GND

(OGl84 EQUIVALENT)
v,

DUAL DPST
IH5049 ('OS (ON) <3511)

v,
5,
53

",5,

"

1):1

'"
",
"
5,

D,
D,

5,

,,'

S,

D,

0,

'"

D,
'"

v,

SPOT
IH5050 ('OS (ON) <3511)

v,

v'

v'

(DG187 EQUIVALENT!

v'

v,

v'

5,

D,

S,

D,

5,

D,

S,

D,

(DG190 EQUIVALENT)
v,

v,.

DUAL SPOT
IH5051 ('OS (ON) <3511)
s,
S,

v'

D,
D3

S,

D,

53

D3

D,

'"5,

D,

S,

D.

'"

'"

'N,
S,
5,

5,

D,

5,

D,

GNq

GND

GND

3-52

v'

IH5040·IH5051 Family
APPLICATIONS
IMPROVEO SAMPLE & HOLD
USING IH5043

OUTPUT

ANALOG

INPUT

+3V = '> SAMPl E MODE
OV ~ , HOLD MOOE

IH5043

USING THE CMOS SWITCH TO DRIVE
AN R/2R LADDER NETWORK 12 LEGS)

LOGIC
STROBE

EXAMPLE: If -V ANALOG' -'OVDC and +V ANALOG' +,OVDC
then Ladder Legs are switched between .:t10VDC. depending upon state
of Logic Strobe.

.sL.
T2c
LOGIC
STROBE

2R

DIGITALLY TUNED
LOW POWER ACTIVE FILTER
100kl2

Constant gain, constant Q, variable frequency filter which

provides simultaneous Lowpass, Bandpass, and Highpass
outputs. With the component values shown, center frequency
will be 235Hz and 23.5Hz for high and low logic inputs
respectively, Q = 100, and Gain = 100.
f n :; Center Frequency == - ' 21TRC

3-53

IH5040·IH5051 Family
THEORY OF OPERATION

A. FLOATING BODY CMOS STRUCTURE

-15V

In a cor~lVentional C·MOS structure. the body of the "n"
channel device is tied to the negative supply, thus forming
a reverse biased diode between the drain/source and the
body (Fig. J). Under certain conditions this diode can
become forward biased; for example. if the supplies are off
(at ground) and a negative input is applied to the drain.
This can have serious consequences for two reasons. Firstly,
the diode has no current limiting and if excessive current
flows, the circuit may be permanently damaged. Secondly,
this diode forms part of a parasitic SCR in the conventional
C·MOS structure. Forward biasing the diode causes the
SCR to turn on. giving rise to a "Iatch·up" condition.
Intersil's improved C·MOS process incorporates an addi·
tional diode in series with the body (Fig. K). The cathode
of this diode is then tied to V+, thus effectively floating
the body. The. inclusion of this diode not only blocks the
excessive current path. but also prevents the SCR from
turning on.

P MATERIAL
ANALOG
SIGNAL
INPUT

0-----,

,-----0

VOUT

FIGURE J

D,

B. OVERVOLTAGE PROTECTION
,-----0

The floating body construction inherently provides over·
voltage protection. In the conventional C·MOS process, the
body of all N·channel FETs is tied to the most negative
power supply and the body of all P·channel devices to the
most positive supply (i. e .. ±15V). Thus, for an overvoltage
spike of> ±15V, a forward bias condition exists between
drain and body of the MOSFET. For example, in Fig. J if
the analog signal input is more negative than -15V. the
drain to body of the N·channel FET is forward biased and
destruction of the device can result. Now by floating the
body. using diode 01, the drain to body of the MOSFET is
still forward biased, but 01 is reversed biased so no current
flows (up to the breakdown of 01 which is;;;' 40V). Thus.
negative excursions of the analog signal can go up to a
maximum of -25V. When the signal goes positive (;;;' +15V,
01 is forward biased, but now the drain to body junction
is reversed for the N·channel FET; this allows the signal to
go to a maximum of +25V with no appreciable current
flow. While the explanation above has been restricted to
N·channel devices, the same applies to P·channel FETs and
the construction is as shown in Fig. L. Fig. L describes an
output stage showing the paralleling of an Nand P channel
to linearize the rDS(ONI With signal input. The presence
o~ diodes 01 and 02 effectively floats the bodies and
provides over voltage protection to amaximum of ±25V.

VOUT

FIGURE K

v+

ANALOG
SIGNAL O---

~

------;.-1

r

I

v+ ;;.

ov ;.. v-

5V
:>-15V

LOGIC INTERFACING
·5V

IN

T'l.r-l..

LOGIC

'5VVl

~

V·

10k!!

1

·15V OR >Vee IV. TERMINAlf

g

·IH5052/I'H5053
CMOS Analog Gates
FEATURES

technology provides input overvoltage capability to ± 25
volts without damage to the device, and the destructive
latch-up 01 solid state analog gates has been eliminated.
Early CMOS. gates were destroyed· when power supplies
were removed with an inp!!t signal. present. The INTERSIL
CMOS technology has eliminated this serious systems
problem. Key performance advantages are TIL compatible
and ultra low-power operation. The quiescent current requirement is less than 10pA. Also designed Into the
IH5052/3 is guaranteed Break-Belore-Make switching. This
Is logically accomplished by extending the tON time
(400nsec TYP.) such that it exceeds tOFF time (200nsec
TYP.). This insures that an ON channel will be turned OFF
belore an OFF channel can turn ON and eliminates the
need llir external logic required to avoid chanrrel to channel shorting during switching. The IH5052 is deSigned to
have switch closure with Logic "0" (0.8V or less) and the
IH5053 is designed to close switches with a Logical "1"
/2.4V or more).

• Switches Greater Than 20Vpp Signals With ±15V
Supplies
• Quiescent Current Less Than 10pA
• Overvoltage Protection to ± 25V
• Break-Before-Make Switching toll 100nsec, ton
250nsec Typical
• T2L, DTL, CMOS, PMOS Compatible
• Non-Latching With Supply Turn-Off
• IH5052 4 Normally Closed Switches
• IH5053 4 Normally Open Switches

GENERAL DESCRIPTION
The IH5052/3 solid state analog gates are designed using
an improved, high voltage CMOS technology. This provides
ease-of-use and performance advantages not previously
available Irom solid state switches. This Improved CMOS

FUNCTIONAL DIAGRAM

PIN CONFIGURATIONS
OUTLINE DWGS
DE,JE
DUAL-IN-LINE PACKAGE

1

S;

y+
3 (SUBSTRATE)

SWITCH STATES ARE
FDA LOGIC "1" IN'UT

y

ORDERING INFORMATION
IH505X

C

1

JE

T

Package

JE = t6-Pln CERDIP
DE = til-Pin Ceramic DIP (Special Order Only)

Temperature Range
M-Military
C=Commerclal
L -_ _ _ _ _ _ _ _ _ _ BaSic Part Number

3-56

IH5052/1H5053
MAXIMUM RATINGS

V+-V- .....................................
V+-Vo ......................................
Vo-V- . .. . . . .. .. .. .. . . . . .. . . .... .. . .. . .. .. ..
Vo-Vs .................................... <
VL-V- ......................................
VL-VIN ......................................
VL-GND ....................................
VIN-GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

CurrenHAnyTerminaH ........................... <30mA
Storage Temperature .................. --65°Cto+150°C
Operating Temperature ..•............. --55° C to +125° C
Power Dissipation .............................. 450mW
(All Leads Soldered to a P.C. Board)
Derate 6 mW/·C Above 70·C
Lead Temperature (Soldering, 10 sec) .............. 3oo·C

<33V
<30V
<30V
± 22V
<33V
<30V
<20V
<20V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (@25°C, V+ = +15V, V- = -15V, VL= +5V, GND=OV)
MIN.lMAX. LIMITS

PER CHANNEL

MILITARY

SYMBOL CHARACTERISTIC

COMMERCIAL

TEST CONDITIONS

-55·c

+2S·C

+12S·C

0

+25·C

+70·c

UNITS

IIN(ONI

Input Logic Current

1

1

1

1

1

1

~A

IIN(OFF)

Input Logic Current

1

1

1

1

1

1

~A

'DS(ON)

Drain-Source On
Resistance

75

75

100

SO

SO

100

0

~DS(ON)

Channel to Channel
ROS(ONI Match
Min. Analog Signal
Handling Capability

VANAlOG

25
(typ)

30
(typ)

0

±11

±10

V

10(OFFI

Switch OFF Leakage
Current

1

1

100

10(ONI
+IS(ONI

Switch On Leakage
Current

2

2

200

tON

Switch "ON" Time

500

tOFF

Switch "OFF" Time

250

Q(INJ.I
OIRR

Charge Injection
Min. Off Isolation
Rejection RatiO

1+

+ Power Supply
Quiescent Curent

1-

- Power Supply
Quiescent Current

10

10

100

10

IVl

+5V Supply
Quiescent Current

10

10

100

10

IOND

Gnd Supply
Quiescent Current

10

10

100

10

10

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

Y,N - 2.4VIIH50531-0.SV IIH50521
Y,N - 0.8V IIH50531-2.4V IIH50521
IS = lOrnA, Vanalog = 10V to
+tOV

5

5

100

nA

VANALOG

10V to +10V

10

10

100

nA

Vo - Vs - -10V to +10V

500

ns

RL -lkO. Vinal, =
+ 10V See Fig.

250

ns

RL - 1kO, Vanal ,
+ 10V See Fig.

15

20

mV

See Fig. B

54

50

dB

f - 1 MHz, Rl - 1000, Cl" 5pF

r
10V to
-10V to

See Fig. C (Note 1)
10

10

100

10

100

~A

10

100

~A

10

100

~A

100

~A

10

54

50

V+=+15V,V
with GNO

=-15V,VL-+5V

One Channel Off; Any Other
Channel Switches as per Fig. E
(Note 1)

dB

fl!0te1: Not tested In production.

TEST CIRCUITS
FIG. A

FIG.B

"NAlJOO ~:'PUT

ov.fl.~-

h

.
LJ;:;C~
'. . J":'
INPUT

VOUT

'lin

.vn~_~
~!.
3·57

(N0?D-l>-_

LOGIC INPUT

VOUT

'. _' J

V"@'MC

T2L

1L -

T'L

LOGIC
INPUT

m

FIG.C
ANALOG INPUT

.".

S10

-=.".

t--

VOUT

1'oon

IH505211HS053
TYPICAL ELECTRICAL CHARACTERISTICS (Per Channel)
ros(ON)VI
POWER SUPPLY VOLTAGE

ros(ON) VI VANALOG SIGNAL

.

100

1&0

••
s: ••

....

+1JSOC

~

+25°C

~

t= I-

- Soc

0: . .

-

"
,

..

12.

S

:2

•• I-- f--

&0

....... f-'

±10

CHARGE INJECTION va VANALOG
(SEE FIG. B) CL = 10.0~pF

-

3St-t-+-t--t-I-t-+--!

I 3.r-i--r-t--t-;--t-;~

I--'

+12
+15

~

I--

c5

••

2.
•

-10 -7.5

---5 -2.5

0

2.5

5

7.5

10

VANA.LOG (V)

-10 -7.5 -5

20

t-+--t---t--t-'--t--t--i---i

15 r-i--r-t--t-;--t-;~

2.

Is=o1mA
@ +15V SUPP IES

25

-2.5

0

2.5

5

7.5

': tl~EEE:t!J

10

-10 -7.5 -5

-2.5

YANALOG (V)

0

2.5

5

7.5

VA.NA.LOG (V)

FIGURE D

iJ

,-------,
J~ ITII
CHANNEL~-I.~!
r-....J -:;:-":".
I

CROSS COUPLING
REJECTION VB FREQUENCY

120

I'r--.

100
iii'
~

OFF

"r-.

8.

I
I
I

r--I'

= &0
!!.
~ ••
0

0:

I
I

I'
PL LEVELS

2.

•

ceRR = 201,.00
1

10

100

y~~~~~~~)

1k

10k

100k

.IL..

SWITCHED
. CHANNEL

1M

I··

I
I
I

YOUT

100n

L":"·
---,

'-;---f"----,.---,

L-----1

~-I
J

2Ypp

loon

@1Me

510

FIGURE E

FREQUENCY (Hz)

OFF ISOLATION VB FREQUENCY
-120

"'"I'

-100

iii'

-11.

~

~
2
~

;;0

2Vpp
@1MC

~.

VOUT

100n
OIRR ,;, 20100
1Hz

10Hz 100Hz

1k

v~~~o!::::)
10k

100k

1M

FI.GURE F

FREQUENCY (Hz)

POWER SUPPLY QUIESCENT CURRENT
VB LOGIC FREQUENCY RATE
C 1000
.3

~

:>
,

/

100

+

0:

~

,.

ffi

~

~

/

V

Vi "

0:

0

'"

51(1

I'r-- ,...

-2.

..

.

V
1

V"

10

100

1k

10k

lOOk

LOGIC FREQUENCY @ 10010 DUTV CYCLE (HI:)

FIGURE G

3-58

10

IH5052/IH5053
THEORY OF OPERATION

A. Floating Body CMOS Structure
In a conventional C-MOS structure, the body of the "n"
channel device is tied to the negative supply, thus forming a
reverse biased diode between the drain/source and the body
(Fig. H). Under certain conditions this diode can become
forward biased; for example, if the supplies are off (at
ground) and a negative input is applied to the drain. Thiscan
have serious consequences for two reasons. Firstly, the
diode has no current limiting and if excessive current flows,
the circuit may be permanently damaged. Secondly, this
diode forms part of a parasitic SCR in the conventional
C-MOS structure. Forward biasing the diode causes the SCR
to turn on, giving rise to a "latch-up" condition.

-15V

P·MATERIAL
ANALOG
SIGNAL
INPUT

Your
D

I

Rl

FIGURE H

Intersil's improved C-MOS process incorporates an additional diode in series with the body (Fig. I). The cathode of
this diode is then tied to V+, thus effectively floating the
body. The inclusion of this diode not only blocks the excessive current path, but also prevents the SCR from turning on.

+15Y
(11+)

D,

B. Overvoltage Protection

FLOATING BODY

The floating body construction inherently provides overvoltage protection. In the conventional C-MOS process, the
body of all N-channel FETs is tied to the most negative power
supply and the body of all P-channel devices to the most
positive supply (i.e., ±15V). Thus, for an overvoltage spike of
> ±15V, a forward bias condition exists between drain and
body of the MOSFET. For example, in Fig. H if the analog
signal input is more negative than -15V, the drain to body of
the N-channel FET is forward biased and destruction of the
device can result. Now by floating the body, using diode 01,
the drain to body of the MOSFET is still forward biased, but
01 is reversed biased so no current flows (up to the
breakdown of 01 which is:::: 40Vl. Thus, negative excursions
of the analog signal can go up to a maxirT,um of - 25V.
When the signal goes positive (2: + 15V, 01 Is forward bi·
ased, but now the drain to body junction is reversed for the
N·channel FET; this allows the signal to go to a maximum
of + 25V with no appreciable current flow. While the ex·
planation above has been restricted to N·channel devices,
the same applies to P·channel FETs and the construction
is as shown in Fig. J. Fig. J describes an output stage
showing the paralleling of an Nand P·channel to linearize
the ros(on) with signal input. The presence of diodes 01 and
02 effectively floats the bodies and provides overvoltage
protection to a maximum of ± 25V.

ANALOG
SIGNAL
INPUT

C>-----,

r----'-_---,

Rl

v+
FIGURE J

3·59

r - -.....-'Y+ >SV
OY>V- > -15V

APPLICATIONS

PROGRAMMABLE GAIN NON-INVERTING AMPLIFIER WITH SELECTABLE INPUTS

VIN30--m----O"1

18kH

VIN40---,+----O"1

Uk

n

2kJl

100kn
100B

......
100Jl

-15Y

+5V

ACTIVE LOW PASS FILTER WITH DIGITALLY SELECTED BREAK FREQUENCY

3·61

IH5052/IH5053
APPLICATIONS (Continued)
4-CHANNEL SEQUENCING MUX
SEQUENCER

DECODER

ANALOG SWITCH

(2 BIT BINARY COUNTER)

S,
VIN1

J

MUX
SE~UENCE
RATE

J-K

Q!::..;t-i-f-..,
D,

FLIP

o-J---q

FLOP
YIN2

RESET <>-H_ _- . . J

D:!
S,

J J-K Oi-;,;-\--'-IH+'4-----r-o Your
35pF

VS1 = -5V

Figure 3. ton and toll Switching Test

ton and toll OF LOGIC
INPUT s10ns

I

+3V

I

Ao,A1,A~

~O_V_ _ _....I---4"S---L_ _ _.::S.::EQ.::UENCED

VOUT

10Kn

Figure 4. Break·Before-Make Delay Test

3-65

II

IHS108
DETAILED DESCRIPTION
(a) OVERVDLTAGE WITH MUX POWER OFF

The IH5108, like allintersil's multiplexers, contains a set of
CMOS switches forming the channels, and driver and
decoder circuitry to control which channel turns ON, if any.
In addition, the IH5108 contains an internal regulator which
provides a fully TTL compatible ENable input that is identical
in operation to the Address inputs. This does away with the
special treatment that many multiplexer enable inputs require for proper logic swings. This identical circuit treatment
of the ENable and Address lines also helps ensure theextension of break-befora-make switching to wider multiplexer
systems (see applications section).

-25V
OVERVOLTAGE
N·CHANNEL
MOSFET
ISTURNEDON
BECAUSE VGS = + 25V

----'--'r

--

/1

P·CHANNEL
MOSFET IS OFF

+25V FORCED
ON COMMON
OUTPUT

Q,

S

0

--

G

To""

.1
,..

~~T~=~AL
CIRCUITRY

N·CHANNEL
MOSFET IS OFF

(b) OVERVOLTAGE WITH MUX POWER ON

Another, and more important, difference lies in the switching
channel. Previous devices have used parallel n- and
p-channel MOSFET switches, and while this scheme yields
reasonably good ON resistance characteristics and allows
the switching of rail-to-rail input Signals, it also has a number
of drawbacks. The sources and drains of the switch transistors will conduct to the substrate if the input goes outside
th'e supply railS, and even careful use of diodes cannot avoid
channel-to-output and channel-to-channel coupling in cases
of input overrange. The IH5108 uses a novel series
arrangement of the p- and n-channelswitches (Figure 5) combined with a dielectrically isolated process to obviate these
problems.

-15V

SIGNAL
INPUT

+15V

11

-15V

+15V

-15V

+25V FORCED
ON COMMON
OUTPUT
LINE BY

-25V
OVERVOLTAGE

N.CHANNEL MOSFET
IS.TURNED ON
BECAUSEVGs= +10V

/1
.

1~~'i ~~g~I~~~

N·CHANNEL
MOSFET IS OFF
-15VFROM +15VFROM P.CHANNEL
DRIVERS
DRIVERS MOSFETIS OFF

Figure 6. Overvoltage Protection

-15V

COMMON
OUTPUT

r+--4--+--o 0

S 0--'-'--,

T

-15V FROM + 15V FROM
DRIVER
DRIVER

Figure 5. Series Connection of Channel Switches

Within the normal analog signal band, the inherent variation
of switch ON resistance will balance out almost as well as
the customary parallel configuration, but as the analog
signal approaches either supply rail, even for an ON channel,
either the p- or the n-channel will become a source follower,
disconnecting the channel (Figure 6). Thus protection is
provided to any input or output channel against overvoltage
on any (or several) input or output channels even in the
absence of multiplexer supply voltages, and applies up to the
breakdown voltage of the respective switches, drawing only
leakage currents. Figure 7 shows a more detailed schematic
of the channel switches, including the back-gate driver
devices which ensure optimum channel ON resistances and
breakdown voltage under the various conditions.
Under some circumstances, if the logic inputs are present
but the multiplexer supplies are not, the circuit will use the
logic inputs as a sort of phantom supply; this could result in
an output up to that logic level. To prevent this from occurring, simply ensure that the ENable pin is LOW any time the
multiplexer supply voltages are missing (Figure 8).

-15V

-15V

FROM
DECODER

+15V

Figure 7. Detailed Channel Switch Schematic
+15V

l00pF

Figure 8. Protection Against Logic Input

3-66

IH5108
MAXIMUM SIGNAL HANDLING CAPABILITY
Figure 10 shows the input/output characteristics of an ON
channel, illustrating the inherent limiting action of the series
switch connection (see Detailed Description), while Figure 11
gives the ON resistance variation with temperature.

The IH510S is designed to handle signals in the ± 10V range,
with a typical rOS(On) of 6000; it can successfully handle
signals up to ± 13V, however, rOS(On) will increase to about
1.SK. Beyond ± 13V the device approaches an open circuit,
and thus ± 12V is about the practical limit, see Figure 9.

rOS(on)

t
2Kn
1.5Kr!

lKn

soon
-VSO~RCE ...._..L_...L.,.-...L,.-...L_-1._......l___.-.J,.-_'-_L-_..L-_..L._...L._-,L_-c'c,.--1.,.-_ + VSOURCE

-14V

-12V

-10V

-8V

-6V

Figure 9. rDS(on)

-4V

VB

-2V

OV

2V

4V

6V

8V

10V

12V

14V

Signa' Output Voltage @ TA = + 25'C

+VOUT

16
14
12
10
VOUT

-VIN+--+-1~+-+-+-f--+-+-+-I-+-+...;!'~I-++-t-~+-+-1-~+-+-1_
-24 -22 -20-18 -16 -14 -12 -10 -8 -6 -4 -2

4

6

8

W

a

-4
-6
-8
-10
-12
-14
-16

-Your

Figure 10. MUX Output Voltage vs Input Voltage
Channel 1 Shown; All Channels Similar

3·67

M

ffi

ffl

20

~

~

+VIN

.O~OIL.

IH5108
rDS(on)

300n

2000

Vsupp=

::t15V
VIN = %:10V

loon

-SS·c

25°C

7S·C

TEMPERATURE

Figure 11. Typical rOS(on) vs Temperature

USING THE IH5108 WITH SUPPLIES OTHER
THAN ±15V
20000

18000

The IH5108 will operate successfully with supply voltages
from ± 5V to ± 15V; rOS(on) increases as supply voltage
decreases, see Figure 12. leakage currents, however,
decrease with a lowering of supply voltage, and therefore the
error term product of rOS(on) and leakage current remains
reasonably constant. rOS(On) also decreases as signal levels
decrease. For high system accuracy [acceptable levels of
ros(on)l the maximum input signal should be 3V less than the
supply voltages. The logic levels will remain TTL compatible.

16000

FOR

~

14000
12000
10000

±2V5IGNAL5

6000

+10V5IGNAL

6000

-10VSIGNAL

4000

200n
:OV

±:5V

:t:10V

=15V

Figure 12. rDS(On) VB Supply Voltages

IH5108 APPLICATIONS INFORMATION
-ISV

DECODE TRUTH TABLE

EN

.,..1

IHS108

Ao
A,

5.

5,

+ISV

-ISV

A2
VOUT

A,
TTL OR
CM05
INVERTER

.,..

IHS108

EN
5,.

A3

A2

Al

Ao

ON SWITCH

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1

81
82
83
84
85
86
87
88
89
810
811
812
813
814
815

5,

Flgure13. 1 of 16 channel multiplexer using two IH5108s.
Overvoltage protection Is maintained between all
channels, as Is break·before·make switching.

3·68

0
1
0
1
0
1

~16

IID~Dll

IH5108
IH5108 APPLICATIONS INFORMATION

(Continued)

---t>o-

VL
+5V

TTLICMOS INVERTER

:jJcr-

+15V

Au 0---.----1

TTLICMOS NOR GATE

A'C>--Ht--1
S,

D,

I
I

-'
-,

I
I

0,

S,

VOUT

IH5053

S,

0,

I

-'

,

IN.

I

O.

S.

-15V

DECODE TRUTH TABLE

DECODE TRUTH TABLE

A. A3 A, A, Ao ON SWITCH

A, A3 A, A, Ao ON SWITCH

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

81
82
83
84
85
86
87
88
89
810
811
812
813
814
815
816

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
1

Figure 14. 1 of 32 multiplexer using 4 IH5108s and an IH5053 as a
submultlplexer. Note that the IH5053 is protected
against overvoltages by the IH5108s. Submultlplexlng
reduces output leakage and capacitance.

3-69

817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832

IH5108
APPLICATION NOTES
Further information may be found in:
A003 "Understanding and Applying the Analog Switch," by

A020 "A Cookbook Approach to High Speed Data Acquisi·

Dave Fullagar
A006 "A New CMOS Analog Gate Technology," by Dave
Fullagar

R009 "Reduce CMOS Multiplexer Troubles Through Proper

tion and Microprocessor Interfacing," by Ed Slieger .
Device Selection," by Diok Wilenken

CHIP TOPOGRAPHY

v-

\

"

0.111 in
(2.82) mm

3·70

IH5140 Family
High Level CMOS
Analog Gates
FEATURES

GENERAL DESCRIPTION

•

The IHS140 Family of CMOS monolithic switches utilizes Intersil's latch-free junction isolated processing to
build the fastest switches now available. These switches
can be toggled at a rate of greater than 1 MHz with super
fast ton times (80ns typical) and faster toff times (SOns
typical), guaranteeing break before make switching.
This family of switches therefore combines the speed
of the hybrid FET DG 180 Family with the reliability and
low power consumption of a monolithic CMOS construction.

•

Super fast break before make switching
ton 80ns typ, toll 50ns typ (SPST switches)
Power supply currents less than 1j.1A

• OFF leakages less than 100pA @ 25°C
guaranteed
• Non-latching with supply turn-off
•
•

Single monolithic CMOS chip
Plug-in replacements for IH5040 family and part of
the DG180 family to upgrade speed and leakage

•
•

Greater than 1MHz toggle rate
Switches greater than 20Vp-p signals with
±15V supplies
T2L, CMOS direct compatibility

•

OFF leakages are guaranteed to be less than 100pA at
2SOC. No quiescent power is disSipated in either the ON .
or the OFF state of the switch. Maximum power supply
current is 1j.1A from any supply and typical quiescent
currents are in the 10nA range which makes these
devices ideal for portable equipment and military
applications.
The IHS140 Family is completely compatible with TTL
(SVl logic, TTL open collector logic and CMOS logic
gates. It is pin compatible with Intersil's IHS040 Family
and part of the DG180/190 FamilY as ShOwn In the
switching state diagrams.

ORDERING INFORMATION
Order
Part Number
IH514D MJE
IH514D CJE
IH514D CPE
IH514D MFO
IH5141 MJE
IH5141 CJE
IH5141 CPE
IH5141 MFO
IH5141 CTW
IH5141 MTW
IH5142 MJE
IH5142 CJE
IH5142 CPE
IH5142 MFO
IH5142 CTW
IH5142 MTW
IH5143 MJE
IH5143 CJE
IH5143 CPE
IH5143 MFO
IH5144 MJE
IH5144 CJE
IH5144 CPE
IH5144 MFD
IH5144 CTW
IH5144 MTW
IH5145 MJE
IH5145 CJE
IH5145 CPE
IH5145 MFO

Function
SPST
SPST
SPST
SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
Dual SPST
SPOT
SPOT
SPOT
SPOT
SPOT
SPOT
Dual SPOT
Dual SPOT
Dual SPOT
Dual SPOT
DPST
DPST
DPST
DPST
DPST
DPST
DualDPST
Dual DPST
Dual DPST
Dual DPST

Package
16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO-lOa
TO-IDD
16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO-l0D
TO-100
16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
16 Pin CERDI P
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack
TO-l00
TO-l00
16 Pin CERDIP
16 Pin CERDIP
16 Pin Plastic DIP
14 Pin Flat Pack

FUNCTIONAL DIAGRAM
Temperature
Range
-WC to 125"C
O"C to 70"C
O"C to 70"C
-55" C to 125" C
-55"C to 125"C
O"C to 70"C
O"C to 70"C
-55" C to 125" C
O"C to 70"C
_55" C to 125" C
-55" C to 125" C
O"C to 70"C
O"Ct070·C
-55" C to 125" C
O"C to 70"C
_55" C to 125" C
-55" C to 125" C
D"C to 7D"C
D"C to 7D"C
-WC to 125"C
-55" C to 125" C
D"C to WC
D"C to 7D"C
-55· C to 125" C
D"C to 7D"C
-55"C to 125"C
-55"C to 125"C
D"C to 7D"C
D"C to 7D"C
-55"C to 125"C

v'

FIGURE 1. Typical Driver/Gate -

Note:
1. Ceramic (side braze) devices also available; consult factory.
2. Mil temp range parts also available with MIL-STD-883 processing.

3·71

IH5142

3

IH5140.IH5145" Family
ABSOl.UTE MAXIMUM RATINGS

V~V'V~VD

c;urrent (AhyTerminal) ............ < 30 mA
Storage Temperature ...... -65°C to +150 0 e
Operating Temperature .... -55°C to +125°e
Power Dissipation .................• 450 mW
(All Leads Soldered to a p.e. Board)
Derate 6 mW;oe Above 70°C
Lead Temperature (~Oldering 1Usec.) .. 30Qoe

VD-VVD-VS
VL-VVL-VIN
VL
VIN

<33V
<30V
<30V
<±22V
<33V
<30V
<20V
<20V

NOTE:

Stresses above those listed under
Absolute Maximum Ratings may cause
permanent damage to the device.
These are stress ratings only, and functional operation of the device at the,se
or any other conditions above those
indicated in the operational sections of
the specifications is not implied. Exposure to absolute maximum rati,ng conditions for extended periods may affect
device reliability.

I

eLECTRICAL CHARACTERISTICS (@25°e, V+

=+15V, V- =-15V,VL =+5V)

MIN.!MAX. LIMITS

PER CHANNEL
MILITARY

IB

COMMERCIAL

SYMBOL

CHARACTERiStiC

-55·C

+25·C

+125°C

0

+25·C

+70·C

IINH

Input Logic Current

1

1

1

1

1

1

I'A

VIN = 2.4 V Ne>te 1

IINL

Input Logic Current

1

1

1

1

1

1

I'A

VIN= 0.8 V' Note 1

rOS(on)

Drain-Source On
Resistance

50

50

75

75

75

100

0

ArOS(On)

Channel to Channel
rOS(On) Match

25
(typ)

30
(typ)

0

VANALOG

Min. Analog Signal
Handling Capability

±11

±10

V

10(Off)+

Switch OFF Leakage

0.1

0.1

20

0.5

0.5

20

15(011)

Current

0.1

0.1

20

0.5

0.5

20

Switch On Leakage

0.2

. 0.2

40

1

1

40

10(on)+

UNITS TEST CONDITIONS

nA

Is = -10 rnA
VANALOG = -10 V to +10 V

Vo = +10 V, Vs = -10 V
Vo = -10V, Vs = +10 V

nA

Vo = Vs = -10 V to +10 V

IS(on)

Current

ton

Switch "ON" Time

toff

Switch "OFF" Time

Q(INJ)

Charge Injection

100

150

pC

See Fig. 4, Note 2

OIAR

Min. Off Isolation
Rejection Ratio

54

50

dB

f = 1 MHz, RL = 1000, CL 5 5 pF
See Fig. 5, Note 2

1+

+ Power Supply
Quiescent Current

1.0

1.0

10.0

10

10

100

I'A

1-

- Power Supply
Quiescent Current

1.0

1.0

10.0

10

10

100

I'A

IL

+5 V Supply
Quiescent Current

1.0

1.0

10.0

10

10

100

I'A

IGNO

Gnd Supply
Quiescent Current

1.0

CCRR

Min. Channel to
Channel Cross
Coupling Rejection
Ratio

See switching time specifications and timing diagrams.

V+ = +15 V. V- = -15 V,
VL= +5 V

See Fig. 6
1.0

10.0

10

54

10

50

100

I'A

dB

One Channel Off; Any Other
Channel Switches
See Fig. 7, Note 2

Note:. 1. Some channels are turned on by high (1) logic inputs and other channels are turned on by low (0) inputs; howeverO.8V to
2.4V describes the min. range for switching properly. Refer to logic diag'ams to find logical value of logic input required
to produce ON or OFF state.
2. Charge injection, OFF isolation, and Channel to Channel isolation are only sample tested in production.

3·721

IH5140·IH5145 Family
90

100

80

§

70

0

60

0

---

!

~

50

40

""'-30

20

+10

-

+8

""'

90

IH~141 D~TA

"""-:--

0

r-- r--

+125°C

-

-55'C

+6

+4

0

"

25'C

-2

+2

-6

-4

-8

0

--

20
+10

-10

r-- .....

+8

VB.

sulPPLI ES

~

-

/
TA '" +25"C

IH5141 DATA

_t---!!0V' +5V SUPpJES

i--

-

±15V, +5V SUlPLIES

+4

+6

-2

+2

-4

-6

-8

-10

ANALOG SIGNAL VOLTAGE (VI

ANALOG SIGNAL VOLTAGE (VI

FIGURE 2. rOS(on)

± 5V, 1+5V

........

Temp., @ ±15V, +5V Supplies.

FIGURE 3. rOS(on) vs. Power Supplies.

'3V

~

+10
15

--1,,,1-

14 -1SV

".::lg

+5

-120

~====1====1----t----I---l

FoM 5
4

I

~~-r--1--+----+-- ~

.::l'"

~

+100

•

-5

~

i!

'>

c

tVINJECT

+VINJECT~

NOTE:

-10 b---r---1~-+----+---+----+--

~V

-100

-40b-----

-VINJeCT~
-VINJECT

ffi

-=1

• ..L:-j
~ c

-201---C = 1IJF

SOCKET ON COPPER GROUND PLANE JIG

-10

+10
ANALOG SIGNAL VOLTAGE (V)

FREQUENCY (Hz)

FIGURE 4. Charge Injection vs. Analog Signal.

FIGURE 5. "OFF" Isolation vs. Frequency.

2.8 r--,--r.,.-,rrrrrr--.,..-,--rrrT"T"l,---r,-rr""TTTl

2,61-----------if---------1---------------j
-120

2,4f-------t-------t---------j

2,21---------+-

1.

:"ill
VOUT

-100

iii

:!!
~

r-T--j

9

z<
><

....fI..SL..+3V
""----,

~

OV

'5>0

STROBE INPUT

COAX

(OFF CHANNEL)

S1!1

-80

~

~

-60

5

-40

-20

IL ';;O.06mA FROM 1,1.1' to DC

100

0
100

1000

PERIOD OF PULSE REPETITION RATE (/ls)

FIGURE 6. Power Supply Currents vs. Logic
Strobe Rate.

,

0

p '" 400n,

T -

2
3

lK

C

~
10K

lOOK

FREQUENCY (Hz)

FIGURE 7. Channel to Channel Cross Coupling
Rejection vs. Frequency.

3·73

1M

10M

IH5140·IH5145 Family
SWITCHING TIME SPECIFICATIONS
(ton, toft are maximum specifications and ton-toft is minimum specifications)
MILITARY
Part
Number

Symbol

Characteristics
Switch "ON" time
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belore-make

ton
tott
IH51405141

ton-toff

ton
toft

ton-tofl
ton
toft
ton-toft

IH51425143

ton
toft
t,n-toft
ton
toft
ton
toft
ton-toft
ton
toft

5145

+25°C
100
75
10
150
125
10

I

Switch "ON" time
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belore-make
Switch "ON" time
Switch "OFF" time
Break-belore-make

ton-toft

IH5144-

-55°C

ton-toff

ton
toft
ton-toft

COMMERCIAL
+125°C

DoC

+25°C
150
125
5
175
150
5

+70°C

ton

15

o

~

IfF
VOUTB

13

~

12
11.
Q
~

®

-=-

I~ IN'914

OV

.
T 2l
+15V,---, INPUT

------I
+lDV

OV

L..::.::...::.

+15V

I

-11--

1Kn

Figure 8

300
150
5

ns

Figure 9

Your

LOGIC INPUT

I

VOUT

--1~

ton

toft

FIGURE 8.

FIGURE 9.

I~
VOUTA

tan

toff

I +10V

I

I

90%

I

I

i
I

+15V

10pF

10%

I I

~INPVT
I
I

II
II

I I

FIGURE 10.

FIGURE 11.

3·74

3

-r0
- -10VL.®

II

I

1

2

lKf2

I I VOUTAORB

} -_ _..J +15V

Figure 10

ns

II

II

10pF

ns

250
150
5

,I

-10V

Figure 9

175
125
10
200
125
10

I

I

ns

Figure 11

r

OV I I

Figure 8

ns

r----l

~

ns

5

II

I

I+15V

Figure 9

300
150
.5

:

I

ns

300
150
5
250
150

toft

ov I

Figure 8

.200
125
10
175
125
10
200
125
10

~NPUT~I
I J +10V It

14 -15V

(3)

ns

250
150
5

!-- ---I r---

--I

+15V

Test·
Conditions

175
125
10

NOTE: SWITCHING TIMES ARE MEASURED@ 90% PTS.

16 "0V

Units

IH5140-IH5145 Family
TYPICAL SWITCHING WAVEFORMS

VERT. ~ SV/DIV.
HORIZ. ~ 100ns/DIV.

SCALE:

TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 8)

-55°C

,---

+25 0 C

TTL OPEN COLLECTOR LOGIC DRIVE (Corresponds to Figure 9)

-_:II
...~~
.. ~

VA

=

-1_-

+lDV

1-

.

I~
VA=~10V

.•

I' i i Iii
' iIIii

.....

.. :II
.

'-

+125°C

.J

n ll
LLIl
OGle

ill..

II
_55°C

=r=:r~r_-..

~-

VA

=

+10V

~

VA

=

-lOY

'"""
:-

.~

,

tI

--

.. TTL1LOIi
GICII':II _.:II
+25°C

1111

TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 11)

II

'-,-

III= +10V
VA

II II

1111

+125"C

_.

TTL OPEN COLLECTOR LOGIC DRIVE
(Corresponds to Figure 10)

V Ag +l0V

!

TTL LOGIC

IJij

..•
..

l.

1111

VA -- lOV

VA = -1OV

1111

~

I~

+25°C

0

TTL Lodle

l

+25 0 C

3-75

~

.D~UIl

IH5140-IH5145' Family
APPLICATION NOTE
To maximize switching speed on the IH5140family use
TTL open collector logic (15V with a 1kO or I.ess collector resistor). This configuration will result in(SPST)
ton and toll times of 80ns and 50ns, for signals between
-10V and +10V. The SPOT and OPST switches are
approximately 30ns slower in both ton and toll with the
same drive configuration. 15V CMOS logic levElls.can
be used (OV to +15V), but propagation delays in the
CMOS logic will slow down the switching (typical
50ns -100ns delays).

3

When driving the IH5140 Family from either+5VTTLor
CMOS logic, sW,itching times run 20ns slower than if
they were driven from +15V logic levels . Thustoni.s
about 105ns, and toff 75ns for SPST switches, and 135ns
and 105ns (ton, totf) for SPOT or OPST switches. The low
level drive can be made as fast as the high level drive if
±5V strobe levels are used instead of the usual OV-+3.0V
drive. Pin 13 is taken to -5V instead of the usual GND and
strobe input is taken from +5V to -5V levels as shown in
Figure 12.
The typical channel of the IH5140 family consists of both
P and N-channel MOS-FETs. The N-channel MOS~FET
uses a "Body Puller" FET to drive the body to -15V(±15V
supplies) to get good breakdown voltages when the
switch is in the off state (See Fig. 13). This "Body Puller"
FET also allows the N-channel body to electrically float
when the .switch is in the on state producing a fairly
constant Ros(ON) with different signal voltages. While
this "Body Puller" FET improves switch performance,it
can cause a problem when analog input signals are
present (negative .signals only) and power supplies are
off. This fault condition is shown in Figure 14.
Current will flow from·-10V analog voltage through the
drain to body junction of 01, then through the drain to
body junction of 03 to GNO. This means that there is
10V across two forward-biased silicon diodes and current will go to whatever value the input signal source is
capable of supplying. If the analog input signal is
derived from the same supplies as the switch this fault
condition cannot occur. Turning off the supplies would
turn off the analog signal at the same time.
This fault situation can also be eliminated by placing a
diode in series with the negative supply line (pin 14) as
shown in Figure 15. Now when the power supplies are
off and a negative input signal is present this diode is
reverse biased and no current can flow.

ANALOG OUT

~

16 ANALOG IN (CHANNEL AI

+5V

o

r-l.

CD

~

®
ANALOG OUT

,

'

INPUT

o
0

STROBE
9

ANALOG IN (CHANNEL BI

FIGURE 12.

'15V FROM
DRIVERS

-15V

FIGURE 13.

/

~

GND WHEN POWER
SUPPLIES ARE OFF

'"
FIGURE.14.

1N914
OR EOUIVALENT
I)-_~_--I"'---",

FIGURE 15.

3-76

CMOS

LlEVEL

-15V

IH5140·IH5145 Family
APPLICATIONS

..JL
T2L
LOGIC
STROBE

OUTPUT

ANALOG
INPUT

..JL
T2L

LOGIC
STROBE

IH5143

+3V =

OV =

ETC. ,f-tv-~-'-"M.---< ETC.

> SAMPLE MODE

> HOLD MODE
-v ANALOG = -10VDC and +V ANALOG'" +10VOC
then Ladder Legs are switched between ~ loyoe, depending upon state
of Logic Strobe.

EXAMPLE: If

FIGURE 17. Using the CMOS Switch to Drive an R/2R •
Ladder Network (2 Legs)
•

FIGURE 16. Improved Sample and Hold Using IH5143

lOOk!!

100kH

I,

68k~!

CONSTANT GAIN, CONSTANT a, VARIABLE FREQUENCY FILTER WHICH
PROVIDES SIMUl TANEOUS lOWPASS, BANDPASS, AND HIGHPASS

OUTPUTS. WITH THE COMPONENT VALUES SHOWN, CENTER FREQUENCY
WILL BE 235Hz AND 23.5Hz FOR HIGH AND lOW LOGIC INPUTS
RESPECTIVELY. a"" 100, AND GAIN::; 100.
1
fn "" CENTER FREQUENCY =

bRc

FIGURE 18. Digitally Tuned Low Power Active Filter.

3·77

lIo~nll.

IH5140-IH5145 Family
SWITCHING STATE DIAGRAMS
FLATPACK fFD-21

SWITCH STATES ARE FOR LOGIC "l"INPUT
DIP (JE. PEl
FLATPACK (FD-2)

DIP (JE, PEl

Vl

s'o-i----<:_'+-<: D,

s, 0.:.+-----0.,.-.+<> D,

,.,
,.,

I
I
I

<>'-'H::>--I>--,

s,o-:.t:;::::=::::;r<> "

"'10

13

S, o-'-I-'--""'....,....,'-<>_~1
,.,

'N,
'N,

~-f....jJ.-I>-

,.,

14

DUAL SPST
IH5141 (rOS(on) < 75,1l)

SPST
IH5140 (rOS(on) < 75,1l)
FLATPACK (FD-2)

TO-l00

V'

TO-100
(DG188 EQUIVALENT)

DIP (JE, PEl

,

S, 0-4---0-"-"+-0 D,
" o-t---O--i. ~i-<> "

S,

D,

"

"

DIP (JE, PEl
(DG191 EQUIVALENT)

FLATPACK (FD-2)

s,

o,

S,

D,

S,

D,
D,

D,
D,

,.,
,.,

,.,
'.,

S,

.."

o,
D,

G.,
DUAL SPOT
IH5143 (rOS(on) < 75,1l)

SPOT
IH5142 (rOS(on)< 75 ,Il)
FLATPACK (FD-2)

DIP tJE, PEl

TO-100

FLATPACK (FD-2)

DIP (JE, PEl
(DG185 EQUIVALENT)

v'

s, o--t----o-'i"-t--o.,

s, o-t---o-T"'i-<> D,

s,

s,

"D,

s,

D,

'N,
'Ns,,
OPST
IH5144 (rOS(on)< 75,1l)

DUAL OPST
IH5145 (rOS(on) < 75,1l)

3-78

D,

·D~DIl

IH5208
4·Channel Differential
Fault Protected
CMOS Analog Multiplexer

FEATURES

GENERAL DESCRIPTION

• Ultra low leakage-IO(off)5100pA
• Power supply quiescent current less than 1p.A
• ± 13V analog signal range
• No SCR latchup
• Break-before-make switching
• TTL and CMOS compatible strobe control
• Pin compatible with HI509, DG509 and AD7509
• All channels OFF (1ILK5100nA) when power OFF, for
analog signals up to ± 25V
• Any channel turns OFF (1ILK5100nA) if input exceeds
supply ralls by up to ± 25V_ Throughput always
< ± 14V (± 15V supplies)
• TTL and CMOS compatible binary Address and
ENable inputs

The IH5208 Is a dlelectrlcally Isolated CMOS monolithic
analog multiplexer, designed as a plug-In replacement forthe
DG509 and similar devices, but adding fault protection to the
standard performance_ A unique serial MOSFET switch ensures that an OFF channel will remain OFF when the Input
exceeds the supply rails by up to ± 25V, even with the supply
voltage at zero. Further, an ON channel will be limited to a
throughput of about 1.5V less than the supply ralls, thus
affording protection to any following circuitry such as op
amps, D/A converters, etc. Cross talk onto "good" channels
Is also prevented.
A binary 2-bit address code together with the ENable input
allows selection of any channel pair or none at all. These 3
inputs are all TTL compatible for easy logic interface; the
ENable input also facilitates MUX expansion and cascading.

DECODE TRUTH TABLE

FUNCTIONAL DIAGRAM

•. ~
S2'~

S3a~

S4.~

'D.

''If'

A,

Ao

EN

ON
SWITCH
PAIR

X
0
0
1
1

X
0
1
0
1

0
1
1
1
1

NONE
la,lb
2a,2b
3a,3b
4a,4b

Ao,Alo EN
Logic "1" = VAH '" 2.4V
Logic "0" = VAL :sO.8V

Stb~
S3b~

PIN CONFIGURATION

5.tb~

l

ADDRESS DECODE

10F4

~

J

Ao
EN

! i

(outline dwg JE, PEl

~ r;-v-~ Al
~
~ GND
~

~

~ S1b

82.

~
~

IDJ S2b

Sq

7

@,.
~S4b

D.

8

YSt8

"I

2 LINE BINARY ADDRESS INPUTS
(OO)ANDEN='
ABOYE EXAMPLE SHOWS CHANNELS " AND lb ON

t:!l

TOPYIEW

ORDERING INFORMATION
PART NUMBER
IH5208MJE
IH5208IJE
IH5208CPE

TEMPERATURE RANGE

PACKAGE

+ 125'C
- 20'C to + 8S'C

16 pin CERDIP
16 pin CERDIP
16 pin plastic DIP

- 55'C to

O'C to 70'C

3-79

Y+

Db

3

IH520,8

,/

ABSOLUTE MAXIMUM RATI~GS
VIN(A,EN)toGround ....................... -15V, +15V
VsorVotoV+ ........................, ..... + 25V, -40V
. VsorVotoV- ........................... -25V, +40V
v+ to Ground .............•.. ; •... ,.......... ; .. ; .. 16V
v':':" toGround ................................ : -16V
Current (Any Terminal) ................ ,........... 20mA

Operating Temperature ................... - 55 to 125'C
Storage Temperature ..................... - 65 to 150'C
Power Dissipaton (Package)" .................. 1200mW
• All leads soldered or welded to PC board. Derate 10mWI"C above
70'C.

Stresses above those listed under Absolute Maximum'Ralings in~y'cause permanent damage to the device. These"are stres;s ratings on,ly,. and functional operali,on of the device al these or any otherconditl9ns above,those indicated in the operational sections of thespeclflcationsJs not implied. Exposurato absolute max,
imum ralinQ conditions for extended periods may.. affeGt device reliability.
.
.

ELECTRICAL CHARACTERISTICS V + = 15V, V ~

CHARACTERISTIC

NO
MAX LIMITS
M SUFFIX
MEASURED TESTS TYP
IIC SUFFIX
UNIT
TERMINAL PER 2S'C
20'CI
8S'CI
-5S'C
2S'C
12S'C
2S'C
TEMP
O'C
70'C
Sto 0

rOS(on)

8
8

S

700
500

900
900

900
900

1200
1200

1200

1200

1200

1200

10

5

W lHOS(on)
I
T
C
H

=: -15V, V EN = 2.4V. unless otherwise specified.

.

1800
1800

10

TESrCONDITIONS

Sequence each
switch on.'
VAL -0.8V.
VAH=2.4V

!l

Vo=10V.
Is= -1.0mA
Vo= -10V
Is = -.1.0mA

%

ArOS{on):= rOS(on)max-rDS(6n~min'

Vs:;::: ± 10V

rOS(on)avg.

IS(OII)

S

10 (011)

0

10(on)

0

8
8
1
1
8

0.002
0.002
0.03
0.03
0.1

0.05
0.05
0.1
0.1
0.2

50
50
100
100
100

0.1
0.1
0.2
0.2
0.4

50
50
100
100
100

8

0.1

0.2

100

0.4

100

8

1

100

1000

50

5000

nA

Vs= 10V, Vo= -10V
Vs= -lOV, Vo=10V
Vo -l0V, Vs= 10V
Vo - -10V, Vs"-10V

VEN=O

VS(AII) - Vo -10V

Sequence each

VS(AII)=VO= -10V

VAL =0.8V, VAH = 2.4V

switch on

F Is with Power OFF
A
U
L IS(oll) with
T Overvoltage (Note 1)
I
N

IEN(on) IA(On)
or
IEN(oft) IA(Oft)

0
Y
N
A
M
I
C

S

P

50

V+ =V- =OV, Vs= ±25V,
VEN = Vo =OV, Ao, A" A2 =OV or 5V
nA

S

8

1

2000

AO' A" A2,
or
EN

4

.01

-10 •

4

.01

10
1

SOOO

5000

5000

0.3

t open

0

0.2

ton(EN)

0

0.6

toll(EN)

0

ton-toff Break-

0

-30

-10

-30

30

10

30

VA=2.4VorOV
"A

0

8

VA = 15VorOV
See Figure 1
See Figure 2

1.5

0.4

1

50

25

10

""

See Figure 3

ns

VEN = + 5V, AO' A,., A2 Strobed
VIN = ± 10V, Figure4

VEN =0, RL = 200!l, C L = 3pF, Vs = 3 VRMS,
1=500 KHz

Before·Make
Delay Settling
Time
"OFF" Isolation

Supply
Current

I

+

I -

I

Vs = ± 25V,Vo = + 10V Sequence each

switch

ttransition

CS(OII)
IliO(off)
IliOS(oft)

u

S

0

60

dB

S
0
utoS

5
25
1

pF

V+
V

1
1

500
500

900
900

750
750

600
600

1000
1000

Note 1. Readings taken 400ms after the overvoltage occurs.

3-80

Vs=O
'.'
Vo:O
Vs-O, VO~O
All VA, VEN = 0 or 5V

"A

VEN=OV,
1=140KHz'
to 1 MHz

I

IH5208
+15V

D,

v+

51'

3.0V

S"

1.4V

S3,

O.8V

S••
S,b

~----S1b(on)

VS1b

VS4b

PROBE IMPEDANCE
-ISV

Rp~1MO

Cp:=;30pF

Figure 1. ttran. Switching Test
+15V

r---..l--,.~~=--..-o -2V

+3.0V

SWITCHOUTP:~ a +~~-:I%t
_r-.::

L..-__..,..J--o!'---r-o VOUT

VOUT

-t~E~

open

_

~

O.SVo

3SpF

,

,

Vo
Vs

Figure 2. t opan (Break·Before·Make) Switching Test

+15V

VEN

-sv

Ir AND tts100ns

OV
O.lVa
SWITCH OUTPUT

Your

Your
VEN

3SpF

Vo
-SV

Figure 3. ton and toll Switching Test

ton and toll OF LOGIC
INPUT510ns

I

+3V

I

~,~
~O';'V_ _ _...J--4"S--L_ _ _.::S.::EQ.::UENCED

,,
BREAK· BEFORE

I:

MAKEDElAY-~IJ ~

:V

VOUT

VOUT2

II
~

,:
-,

INPUT
'--+10V

W
~"

BREAK·BEFORE
I I
__ , 1_I_N,PUT
Ov
MAKEDElAY-, I.._ _ _---'~. .

Figure 4. Break·Before·Make Delay Test

3-81

IID~DlL

IH5208'

I

DETAILED DESCRIPTION
The IH5208, like all Intersil's multiplexers, contains a set of
CMOS switches forming the channels, and driver and
decoder circuitry to control which channel turns ON, if any. In
addition, the IH5208 conta'ins an internal regulator which provides a fully TTL compatible ENable input that is identical in
operation to the Address inputs. This does away with the
special treatments that many multiplexer enable inputs require for proper logic swings. This identical circuit treatment
of the ENable and Address lines also helps ensure the extension of break-before-make switching to wider multiplexer
systems (see applications section).

II

(a) OVERVOLTAGE WITH MUX POWER OFF

-25V
OVERVOLTAGE

--

• P·CHANNEL
MOSFET IS OFF

SIGNAL
INPUT

+15V

I 1

N·CHANNEL
MOSFET IS OFF

'::"

(b) OVERVOLTAGE WITH MUX POWER ON

Another, and more important, difference lies in the switching
channel. Previous devices have used parallel n- and
p-channel MOSFET switches, and while this. scheme yields
reasonably good ON resistance characteristics and allows
the switching of rail-to-rail input signals, it also has a number
of drawbacks. The sources and drains of the switch transistors will conduct to the substrate if the inpout goes out·
side the supply rails, and even careful use of diodes cannot
avoid channel-to·output and channel-to-channel coupling in
cases of input overrange. The 'IH5208 uses a novel series
arrangement of the p- and n-channel switches (Figure 5) com·
bined with the dielectrically isolated process to obviate these
problems.

-15V

1

-

0'"
G

5

S

N·CHANNEL M O S F E T - r / 1D
IS TURNED ON
BECAUSE VGS = + 25V

+25V FORCED
ON COMMON
OUTPUT
LINE BY
EXTERNAL
CIRCUITRY

-15V

-15V

+15V

-25V
OVERVOLTAGE

/ 11

'-....

'-..

~~

+25VFORCED
ON COMMON
OUTPUT
LINE BY
EXTERNAL,

1 CIRCUITRY
N·CHANNEL MOSFET
.~
N·CHANNEL
15 TURNED O N '
'.
MOSFET IS OFF
BECAUSEVos=+10V
-15VFROM +15VFROM P.CHANNEL
DRIYERS
DRIVERS MOSFET IS OFF
Figure 6. Overvoltage Protection

-15V

COMMON
OUTPUT

r+-..+-+--o 0

S 0--<1>--,

T

-15V FROM + 15V FROM
DRIVER
DRIVER

Figure 5. Series Connection of Channel Switches

Within the normal analog signal band, the inherent variation
of switch ON resistance will balance out almost as well as
the customary parallel configuration, but as the analog
signal approaches either supply rail, even for an ON channel,
either the p- or the n·channel will become a source follower,
disconnecting the channel (Figure 6). Thus protection is
provided to any input or output channel ag~inst overvoltage
on any (or several) input or output channels even in the
absence of multiplexer supply voltages, and applies up to the
breakdown voltage of the respective switches, drawing only
leakage currents. Figure 7 shows a more detailed schematic
of the channel switches, including the back-gate driver
devices which ensure optimum channel ON resistances and
breakdown voltage under the various conditions.
Under some circumstances, if the logic inputs are present
but the multiplexer supplies are not, the circuit will use the
logic inputs as a sort of phantom supply; this could result in
an output up to that logic level. To prevent this from occur·
ring, simply ensure that the ENable pin is LOW any time the
multiplexer supply voltages are missing (Figure 8).

3-82

-15V

-15V

FROM
DECODER

+15V

Figure 7. Detailed Channel Switch Schematic
+15V

100pF

Figure 6. Protection Against Logic Input

IH5208
MAXIMUM SIGNAL HANDLING CAPABILITY
The IH520B is designed to handle signals in the ± 10V range,
with a typical rOS(on) of 6000; it can successfully 'handle
signals up to ± 13V, however, rOS(on) will Increase to about
1.BK. Beyond ± 13V the device approaches an open circuit,
and thus ± 12V is about the practical limit, see Figure 9.

Figure 10 shows the Input/output characteristics of an ON
channel, illustrating the Inherent limiting action of the series
switch connection (see Detailed Description), while Figure 11
gives the ON resistance variation with temperature.

roS(on)

t
2Kn

1,sKn

1Kn

soon

-VSOURCE

+--_1.l.4Vc:--_.l.
12""V-_.l.10-V-_.l.8V.,.--_.l.6V.,.--_.l.4V.,.--_.l.2V"'--0="V:-:--2="V--4="V:-:--6="V:-:--8="V:-:--:1~OV"'--:1~2V"'--:14'":-V:-:--+ +VSOUACE

Figure 9. rOS(on) vs Signal Input Voltage @ TA

=+ 25°C

+VOUT

16
14
12

10
Your

Your

-VIN+--+-+--iI--+-+-+-+-I--+-+-+-+-7IO:-+-++-+--i-+-++-+-+-f--+-+ +VIN
-24 -22 -20-18 -16 -14 -12 -10 -8 -6 -4 -2
-4
-6

-8

-10
-12

-14
-16
-Your

Figure 10. MUX Output Voltage VB Input Voltage
Channel 1 Shown; All Channels Similar

3-83

B

.O~OIl

~

IH5208
rOS(on)

looon

600n
soon

4DOn
300n
2000

Vsupp = ±15V
VIN = ±10V

1000

-25°C

2SQ C

7SQ C

TEMPERATURE

II .

Figure 11. Typical rDS(on) vs Temperature

:I THAN
USING THE IH5208 WITH SUPPLIES OTHER
::!:15V

'DS(on)

TA = ... 2SQ C

20000
lBOOO

The IH5208 will operate successfully with supply voltages
from ± 5V to ± 15V; rOS(on) increases as supply voltage
decreases, see Figure 12. Leakage currents, however,
decrease with a lowering of supply voltage, and therefore the
error term product of rOS(on) and leakage current remains
reasonably constant. rOS(on) also decreases as signal levels
decrease. For high system accuracy [acceptable levels of
ros(on)l the maximum input signal should be 3V less than the
supply voltages. The logic thresholds will remain TTL
compatible.

lBOOO

~
FOR

l4DOn
12000

lDOOO

±2VSIGNALS

8000

+10VSIGNAL

BOOO

-10VSIGNAL

4000
2000
±OV

±5V

±15V

::t10V

Figure 12. rDS(on) vs Supply Voltages

IH5208 APPLICATIONS INFORMATION
+5V

+15V

-15V

+15V
AO<>--.......- l

A,o-......t-+--j

VOUTa

DECODE TRUTH TABLE

IH5208

EN

TTUCMOS
INVERTER

1"--++-1I---60dB @ 10MHz
Cross coupling isolation > 60dB @ 10M Hz
Directly compatible with TTL, CMOS
Wide operating power supply range
Power supply current< 1J.LA
"Break-belore-Make" switching
Fast switching (80ns/150ns typ)

Construction of remote and portable video equipment with
extended battery life is facilitated by the extremely low
current requirements. Switching speeds are typical
ton 150ns and toff 80ns, and guaranteed "Break·beforeMake" switching.

=

Switch "ON" resistance is typically 400-500 with± 15V
power supplies, increasing to typically 1750 for ± 5V supplies. The devices are available in TO-100 and 14-pin epoxy
DIP packages.

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

o to

IH5341CPD
IH53411TW
IH5341MTW

=

+ 70°C
- 20°C to + 85'C
-55°C to +125°C

14·Pln DIP
TO·100
TO·100

FUNCTIONAL DIAGRAM

PIN CONFIGURATIONS

PD

TO·l00

Circuit 01 Switch Channel
SWITCH ~I/~
SOURCE
(
C>--O SWITCH
DRAIN
(IN)
(OUn

,

L ___ J
I

CONTROL~o­
IN~
DRIVER
TRANSLATOR

V·

~
OND

TOPYIEW

Note: Only one side shown.
TOP VIEW

3-87

3

IH5341.
ABSOLUTE MAXIMUM RATINGS
SupplyV~ltagesV+ andV~

Storage Temperature ................ , - 65'C to + 160'C
Power Dissipation ............................ 250mW
Derate above 25'C @ . . . . . . . . • . . . . . . . . . . . . . 7.5mW/·C
LogicControlVoltage ........................ V+ toVVoltage on Pin 10 ............................ V + to VLea(Hemperature(soldering,10seconds) .......... 300'C

'" , •................ ±17V
Current in any Terminal ......................... 50mA
Analog Input Voltage ........................ V + to VOperating Temperature
(MVersion) ...................... -55'Cto +125'C
(I Version) ........................ - 20'C to +85'C
(C Version) ............................ 0 to + 70'C

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect-device reNability.

DC ELECTRICAL CHARACTERISTICS v+
PARAMETER
Supply Voltage
Ranges
Positive Supply
Logic Supply
Negative Supply
Switch "ON"
Resistance
(Note 4)
Switch "ON"
Resistance

SYMBOL

V+
VL
V-

Switch "ON"
Leakage

(Note 3)

TYP

M GRADE DEVICE
-55'C
+2S'C
+ 12S'C

4.5> 16
4.5>V+
-4> -16

5 to 15
5 toV+
-5 to -15
75

Vo -5Vto +5V
rdS(on)

Is = lOrnA, V'N = 2.4V
Vo -15V to + 15V

rdS(on)

V+=V L =5V, V'N=3V
V-=5V, Vo= ±5V

On Resistance
Match
Switch "OFF"
Leakage
(Notes 2 and 4)

CONDITIONS

= + 15V, VL = + 5V,V- = -15V, TA = 25'C unless otherwise specified.

Is=10mA, Vo= ±5V
ID(Of~

75

IIC GRADE DEVICE
+2S'C

+"'7~~

-20fO'C

5 to 15
5 toV+
-5to -15
100

75

75

V
100

125

125

175

150

150

175

250

250

350

300

300

350

0.1

0.1

20

0.5

0.5

20

I8(Of~

0.2

0.2

50

1.0

1.0

100

1000n)

Vo = + 5V or - 5V

0.3

0.3

50

1.0

1.0

40

+

V'N =2.4V
Vo= +14Vto -14V

0.5

0.5

100

1.0

1.0

100

1

1

10

l5(on)

nA

Input Logic
Current

I'N

V'N>2.4V or frequency where 20 log
I.e., from DC to f = 40MHz, 20 log

V

OUT
v;;;-

VOUT

changes by + 3dB

V;; '" -

4dB;

when this ratio reaches - 1dB, the frequency causing this is
rdslon)3dB frequency.
VIN = 225mVrms @ f = 10MHz -100MHz
VOUT

v;;;- =

750 (load)
750 + rdslon)

Note: Only one side shown. Other acts, identically.
Figure 4. rdslAC) Pole Frequency Test Circuit

3·89

141 mVrms t icall @ f = 10MHz
225mVrms yp
y
,

IH5341
TYPICAL CHARACTERISTICS

rds(on) vs Analog Input Voltage
with :t: 15V Power Supplies
70

60

PIN 3- + 15V, PIN 7=
PIN 10= +5V
TA=25°C

!

50

;;!

40

.... ~

V

V

100

180

15V

PIN 3=PIN 10- +5V
PIN 7= -5V
160 TA=25°C
I--I--

7

If

§

I

J

-15 -10 -5 0
5
10 15
ANALOG INPUT VOLTAGE LEVEL (V)

40

0
0

30
0.1

10

100

FREQUENCY (MHz)

Switch rdo(on) Change with
Frequency (Expressed In
VoItaga Divider Terms with a 750
Lolid (See Figure 4)
-3.3

TA=25°C

TA= + 25°C

-3.4
~

80

a:
a:

r\

50

90

:s

70

a:
a: 60
(5

CCRR (Cross Coupling
Rejection) vs Frequency
(See Figure 3)

iii'

"

so
iii'

:s

80
-5
0
+5
ANALOG INPUT VOLTAGE LEVEL (V)

30

TA= +25°C

I-

90

~

V
V

100

100

OIRR (OFF Isolation Rejection)
vs Frequency (See Figure 2)

rds(on) vs Analog Input Level with
:t: 5V Power Supplies

~ -3.5

52

70

!c
a:

'\

60

-3.6

_ 3.7 r- .

I -3.8

50

!--

~

40

-3.9

30

-4.0
0.1

1
10
FREQUENCY (MHz)

100

0.1

1

10

100

FREQUENCY (MHz)

DETAILED DESCRIPTION

APPLICATIONS

As can be seen in the Functional Diagram, the switch cir·
cuitry is of the so-called "T" configuration, where a shunt
switch is closed when the switch is open. This provides much
better isolation bE;ltween the input and the output than does
the single seri.es switch, especially at high frequencies, and
the result is excellent performance in the Video and RF
region compared to conventional Analog Switches.

Charge COlTlpen$ation Techniques
Charge injection results from the Signals out of the level
transla.tion 'circuit being coupled through the gate-channel
and gate-source/drain capacitances to the switch inputs and
outputs_ This feedthrough is particularly troublesome in
Sampie-and-Hold or Track-and-Hold applications, as it
causes a Sample (Track) to Hold offset. The IH5341 devices
have a typical injected charge of 3OpC-50pC (corresponding
to 30mV-50mV in a 1000pF capacitor), at VS/D of about OV.

The input level shifting circuit is similar to that of the IH5140
Series of Analog Switches, and gives very high speed and
guaranteed "Break-before-Make" action, with negligible
static power consumption and TTL compatibility.

3-90

IH5341
This Sample (Track) to Hold offset can be compensated by
bringing in a signal equal in magnitude but of the opposite
polarity. The circuit of Figure 5 accomplishes this charge in·
jection compensation by using one side of the device as a
S & H (T & H) switch, and the other side as a generator of a
compensating signal. The 1k potentiometer allows the user
to adjust the net injeCted charge to exactly zero for any
analog voltage in the - 5V to + 5V range.

750

+ 15V -.JV\/Y-""f---...,

Your .-------=.p,

ANALOG
INPUT

Since the individual parts are very consistent in their charge
injection, it is possible to replace the potentiometer with a
pair of fixed resistors, and achieve less than 5mV error for all
devices without adjustment.
An alternative arrangement, using a standard TTL inverter to
generate the required inversion, is shown in Figure 6. The
capacitor needs to be increased, and becomes the only
method of adjustment. A fixed value of 22pF is good for
analog values referred to ground, while 35pF is optimum for
AC coupled Signals referred to - 5V as shown in the figure.
The choice of - 5V is based on the virtual disappearance at
this analog level of the transient component of switching
. charge injection. This combination will lead to a virtually
"glitch-free" switch.

CHOLD

..-.-+3V

1000PFT

.....J

Lov

TTL IN (STROBE) ,

• Adjust pot for OmVp·p step @ VOUT with
no analog (AC) signal present
Figure 5. Charge Injection Compensation

+5V

VOUT

DC BIAS
VOLTAGE Q-.JV\/Y-.,
-5V

=

'--..J I-+.-""""-f'"

ANALOG
INPUTr(

1.F

22pF-35pF

T

CHOLD

1000PF

+ 3V

ov

:r--L
TTL
CONTROL IN

Figure 6. Alternative Compensation Circuit

Overvoltage Spike Protection

1N914

+15V -1.........- - - - - ,

If sustained operation with no supplies but with analog
signals applied is possible, it is recommended that diodes
(such as 1N914) be inserted in series with the supply lines to
the IH5341. Such conditions can occur if these signals come
from a separate power supply or another location, for example. The diodes will be reverse biased under this type of
operation, preventing heavy currents from flowing from the
analog source through the IH5341.
The same method of protection will provide over ± 25V overvoltage protection on the analog inputs when the supplies
are present. The schematic for this connectio'n is shown in
Figure 7.

1N914 .".

..-.....~--15V

Figure 7. Overvoltage Protection Circuit

3-91

B

IH6341
EQUIVALENT SCHEMATIC DIAGRAM (1/2 of actual circuit on chip shown)
+15V

-15V

~O----;--O

TTL

1 1000

CHIP TOPOGRAPHY
VL

''''

0.098 In
(2.49)mm

v·

0.093 In
(2.36)mm

,I

3·92

SWITCH

IH6108
a·Channel CMOS
Analog Multiplexer
FEATURES

GENERAL DESCRIPTION

• Ultra Low Leakage - 10(off) :S 100pA
• rOS(on) < 400 oh~s over full signal and temperature
range
• Power supply quiescent current less than 100J.LA
• ±14V analog signal range
• No SeR latch up
• Break·before·make switching
• Binary Address control (3 Address inputs control 8
channels)
• TTL and CMOS compatible strobe control
• Pin compatible with DG508, HI·508 & AD7508

The IH610B is a CMOS monolithic, one ·01 B multiplexer. The
part is a plug-in replacement for the DG50B. Three line binary
decoding is used so that the B channels can be controlled by
3 Address inputs; additionally a fourth input is provided to
use as a system enable. When the ENable input is high (5V)
the channels are sequenced by the 31ine Address inputs, and
when low (OV) all channels are off. The 3 Address inputs are
controlled by TTL logic or CMOS logic elements, a "0" corresponding to any voltage greater than 2.4V. Note that the
ENable input (EN) must be taken to 5V to enable the system
and less than O.BV to disable the system.

FUNCTIONAL DIAGRAM

DECODE TRUTH TABLE

St·~

A2

At

Ao

EN

ON SWITCH

x

x

x

0
1
1
1
1
1
1
1
1

NONE
1
2

a
a

a

0

0

0

1
1

1
0
1

1
1
1
1

a
a

a

52~
S3~

Logic "1"
Logic

0

EN
SWITCH

1

= VAH 2: 2.4V

"a" = VAL S O.BV

Your

S5~

1

a

1
1

Ao. At. A2

S4~

a

3
4
5
6
7

B
VENH 2: 4:5V

PIN CONFIGURATION
56

--

57~

AoII .--..
• ...,
EN [I

Sa~

I

V-I:!
ADDRESS DECODE
10F8

!

~

I

,

'!IDAt

IID A2
EiGND

5t [I

~v+

Sz[I

irn 55

53 [[

1lI56

IT

il]J57

olI

;ID Sa

54

EN (ENABLE INPUT)

3 LINE BINARY ADDRESS INPUTS
(1 0 1)ANDEN@5V
ABOVE EXAMPLE SHOWS CHANNEL 6 TURNED ON

ORDERING INFORMATION
Ceramic package available as
special order only (IH610BMOE/COE)

PART NUMBER
IH610BMJE

TEMPERATURE RANGE

PACKAGE

-55°C to +125°C

16 pin CEROIP

IH610BCJE

O°C to 70°C

16 pin CERDIP

IH610BCPE

DOC to 7DoC

16 pin plastic OIP

3-93

B

IMei0S
ABSOLUTE MAXIMUM .RATINGS
VIN (A,

EN)

Vs or VD to

Current (Analog Source or Drain) . . • • • • • • . . • • . . . •. 20 mA

to Ground ...................... -15V to 15V

v· .......... , ......... ;.. . .. . . .. . ..

Operating Temperature

0, -32V

Storage Temperature

••••••••••••••••••

-55 to 125°C

•••••••••••••••••••.

~5 to 150°C

Vsor VD to V- ••••••••••••• : •••••••••••••••••••• 0,32V

Lead Temp (Soldering, 10 sec) ... .' .••...•....••.. 300·C

V+to Ground

Power Dissipation (Package)* .••••••••••••••••

•••••••••••••••••••••••••••.•••••••••

V- to Ground ••••••••••••••••••••••••••••••••••••

16V

1200

mW

-16V

*Allieads soldered or welded to PC board. Derate 10 mWfOC above
Current (Any Terminal) .......................... 30 mA
70°C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and functional operation of
the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS v+

--15V, v- -

S to D

rOS(ON)

8
8

S ~rDS(ON)

180
150

300
300

300
300

400
400

-

350
350

350
350

TEST CONDITIONS
UNI

I

450
450

Vo = 10V. Is = -1.0mA Sequence each switch on
Vo - 10V, Is- 1.0mA I VAL - 0.8V, VAH, - 2.4V

0

%

20

.arDS(on)

W
I
T ISIOFF)
C
H 1010FF)

S

0
0

10 ON

I IANION) or IAlon)
N IANIOFF) IAloff)

p
U IA
T

Inputs
AoAt
Az
EN

topen
on(EN)

oftiEN)
"OFF" Isolation

0.002
0.002
0.03
0.03
0.1
0.1
.01
.01

0.05
0.05
0.1
0.1
0.2
0.2
-10
10

50
50
100
100
'100
100
-30
30

0.1
0.1
0.2
0.2
0.4
0.4
-10
10

, 50
50
100
100
100
100
-30
30

-10
-10
1

-30
-30

-10
-10

-30
-30

D
D

0.3
0.2
0.6
0.4

roS(on)avg.

10V
Vs -10V. Vo
Vs = -10V, Vo = 10V
nA Vo - 10V, Vs - -10V
Vo - -10V, Vs - 10V
Vs All = Vo = 10V
VSAII -Vo--l0V
VA - 2.4V or OV
VA-15VorOV

0

60

1.5
1

MS

VEN
VEN
See
See
See

VEN =

Vs =±10V

a

Sequence each switch on
VAL = 0.8V, VAH = 2.4V

= 5V
-0
Fig. 1
Fig. 2
Fig. 3

All VA = 0 (Address pins)

J

VEN - 0, RL - 2000, CL - 3pF, Vs - 3 VRMS,

dB

f = 500 kHz

S
D

les(off)

,Cd(ott)

5
25

DtoS

COSlott)

pF

1

Vs =0
Vo = a
Vs = 0, Vo

S Supply
~ Current

+

V+

1

40

200

1000

-

2

100

1000

+

V
V+

1

Standby
y Current

1

1

100

1000

-

V

1

1

100

1000

r

rOS(on)max - roS(on)mln

=

MA
3
1

0
0

ttransition

D
V
N
A
M
I
C

1'.0. At or Az

8
8
1
1
8
8
3
3

,

-

-15V, VEN - +5V (Note 1) Ground-OV unless otherwise specified

NO
MAX LIMITS
CHARACTERISTIC MEASURED TESTS TVP
TERMINAL
PER
M
SUFFIX
25°C
C SUFFIX
TEMP
-55°C 25°C 125°C O°C
25°C 70'C

VEN ~ OV. f
1 MHz
~

~

140 kHz to

a

VEN = 5V
AIIVA =00r5V

MA
VEN =

a

. NOTE 1: See Enable Input Strobing l.,evels, Section 1.
3V

VA
tr <

lOOns

It < lOOns

0.8V-ji---50%---\:-ttrans(8-1)

- - -.... +10V
Your
VSl

VS8

= +10V
~

-10V

ttrans(l-B)

r--..,..=;,;-9;ll;V~_.jI-l0V "
~S80N~

~SI0N~

f---J.~=+:+9~v;--11+10V
ttrans(l-B)

Your

Vs, = -10V
VS8 = +10V
PROBE IMPEDANCE
Rp ~IMO
Cp 530pF

_ _ _...I-10V

-9V
ttrans(8-1)

Figure 1. I'ransi'ion Switching Test

3-94

J--S80N--.

IH61 08
3V
+15V

~A<100n.J

r--"'-~~..-1>------C-2V

tf < l00n8

O.SV

IH6l0S

\'---~O'8V

VOUT~VS~1-~--~2V~---------------~-

L..,...--...,....J-g-T'.._..oJ-::
Your
35pF

S10N

Figure 2. topen I Break-Before-Makel Switching Test

VEN

If < lOOns
If < lOOns

+15V

O.SV

r------~l-~S~I----~ VS1
S2 THRU SS

IH610S

Your

OV

OUT

L""'--""T"J--=<~r-=-"1~ Your
35pF

VEN

Figure 3. ton and toff SWitching Test

IH6108 APPLICATION INFORMATION

I. ENable Input Strobing Levels
The ENable input on the IH610B requires a minimum of + 4.5V
to trigger to the "1" state and a maximum of + O.BV to trigger
to the "0" state. If the ENable input is being driven from TTL

logic, a pull-up resistor of 1k to 3kO is required from the gate
output to + 5V supply. (See Figure 4)

14 +5V lKn

DM7404N
TTL LOGIC

+3V

11

cl""L

Your

Figure 4. ENable Input Strobing from TTL Logic

3-95

.o~n(l

IH61 08
IH6108 APPLICATION INFORMATION

(Continued)

When the EN input is driven from CMOS logic, no pullup is necessary, see Fig. 5.

+5V

B1
Figure 5. ENable Input Driven from CMOS Logic

The supply voltage of the CD4009 affects the switching speed of the IH61 08; the same 'is true for TTL supply voltage levels. The
chart below shows the effect, on tlrans for a supply varying from +4.5V to +5.5V.

CMOS OR TTL SUPPLY VOLTAGE
+4.5V
+4.75V
+5.00V
+5.25V
+5.50V

The throughput rate can theret'ore be maximized by using a

TYPICAL tlrans @ 25°C
400ns
300ns
250ns
200ns
175ns

+ 5V to + 5.5V supply for the ENable Strobe Logic,

The examples shown in Figures 4 and 5 deal with ENable strobing III(hen expansion to more than eight channels is required; in
these cases the EN terminal acts as a fourth address input. If eight channels or less are being multiplexed, the EN terminal can
be directly connected. to + 5V logic supply to enable the IH6108 at all times.

3-96

IH61 08
IH6108 APPLICATION INFORMATION

(Continued)

II. Using the IH6108 with supplies other than
±15V
.
The IH6108 can be used with power supplies ranging from
±6V to ±16V. The switch rOS(on) will increase as the supply
voltages decrease, however the multiplexer error term (the
product of leakage times rOS(on)) will remain approximately
constant since leakage decreases as the supply voltages are
reduced.

voltage in order to define a binary "1" state. For the case
shown in Figure 6 the EN voltage is 11.3V which means that
logic high atAOand A1 is=+8.8V(logic low continues to be=
O.8V). In this configuration the IH6108 cannot be driven by
TTL<+5V) or CMOS <+5V) logic. It can bedriven by TTL open
collector logic or CMOS logic with +12V supplies.

Caution must be taken to ensure that the enable (EN) voltage
is at least O.7V below V + at all times. If this is not done the
Address .input strobing levels will not function properly. This
may be achieved quite simply by connecting EN (pin 2) to V +
(pin 13) via a silicon diode as shown in Figure 6. When using
this type:of configuration, a further requirement must be met·
the strobe levels at AO and A1 must be within 2.5V of the EN

If the logic and the IH6108 have common supplies, the EN pin
should again be connected to the supply through a silicon
diode. In this case, tyingEN to the logic supply directly will
not work since it violates the O.7V differential voltage
required between V+ and EN. (See Figure 7) A 1/LF capaCitor
can be placed across the diode to minimize switching
glitches.

Figure 6. IH6108 Connection Diagram for less than ±15V Supply Operation.

3-97

I

IH81 08
IH6108 APPLICATION INFORMATION

(Continued)

lN914 OR ANY SILICON DIODE
I
I

.0

I

I

L._~!,"_.J

Figure 7. IH6108 Connection Diagram with ENable Input Strobing for less ,than ±15V Supply Operation.

III. Peak-to-Peak Signal Handling Capability

The\electrical specifications of the IH6l08 are guaranteed
for ±10V signals. but the specifications have very minor
changes for ±14V signals. The notable changes are slightly
lower rOS(on) and slightly higher leakages.

The IH6l08 can handle input signals up to ±14V (actually
-15V to +14.3V because ofthe input protection diode) when
using ±15V supplies.

3·98

IH6116
i6·Channel
CMOS Analog Multiplexer
FEATURES

GENERAL DESCRIPTION

• Pin compatible with DG506, HI-506 & AD7506
• Ultra Low Leakage - 10(off) :s; 100pA
• ±11 analog signal range
• rOS(on) <700 ohms over full signal and temperature
range
• Break·before·make switching
• TTL and CMOS compatible Address control
• Binary Address control (4 Address inputs control 16
channels)
• Two tier submultiplexing to facilitate expandability
• Power supply quiescent current less than 100MA
• No SCR latch up

The IH6116 is a CMOS monolithic, one of 16 multiplexer. The
part is a plug·in replacement for the DG506. Four line binary
decoding is used so that the 16 channels can be controlled by
4 Address inputs; additionally a fifth input is provided to use
as system enable. When the ENable input is high (5V) the
channels are sequenced by the 4 line,Address inputs, and
when low (OV), all channels are off. The 4 Address inputs are
controlled by TTL logic or CMOS logic elements with a "0"
corresponding to any voltage less than 0.8V and a "1" cor·
responding to any voltage greater than 3.0V. Note that the
ENable input must be taken to 5V to enable the system and
less than 0.8V to disable the system.

DECODE TRUTH TABLE

FUNCTIONAL DIAGRAM
s,~O-­

S2~0--

S3~O--n

S5~b

S6~
S7~

.

'<>---

S6~

"<>---

59

~VOUT(D)

5,,~o----J
S,,~<>--­

S,,~<>---

5n~<>---

5'4~<>---

5'5~<>---~

/>.2

/>.1

Ao

x

x

x

x

0
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
0
1
0
0
1
0
1
0
1
1
0
0
1
1
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
1
0
1
1
1
0
1
1
1
1
Logic "1" = VAH '" 3.0V
LOQic "0" = VAL 50.8V

I

s'~O--I

/>.3

EN

PIN CONFIGURATION

5,,~<>---

V+:~ ~ Wi
DIVou,)
~ y-

TO DECODE LOGIC
CONTROLLING BOTH
TIERS OF MUXING

Ne :I
Ne 3

26 S8

514 6

25
2456
23 55

513

22 54

5161
515 ~5

I

ADDRESS DECODE
1 of 16

ON SWITCH

NONE
0
1
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
1
9
10
1
11
1
1
12
13
1
14
1
1
15
16
1
VENH '" 4.5V

I

ENABLE
1 of 4

I

812

57

1

~

21 S3

G~ ~:'~

~; ~

NC 13

4 LINE BINARY ADDRESS INPUTS
(0 0 0 1) AND EN (it! 5V
ABOVE EXAMPLE,SHOWS CHANNEL 9 TURNED ON

Aa

16 Al

14

15

A2

TOP VIEW
Y+COMMON TO SUBSTRATE

ORDERING INFORMATION
Ceramic package available as
special order only (I H6116MOIICOI)

PART NUMBER
IH6116MJI
IH6116CJI
IH6116CPI

TEMPERATURE RANGE
-55°C to +125°C
O°C to 70°C
O°C to 70°C

3-99

PACKAGE
28 pin CERDIP
28 pin CERDIP
28 pin Plastic DIP

B1

IH6116
ABSOLUTE MAXIMUM RATINGS

Currenl (Analog Source or Drain) . . . . . . . . . . . . . . . .. 20 mA
OperalingTemperalure .............•..•..• -S51012SoC
SlorageTemperalure ...................... -6510 150°C
Lead Temperature (Soldering, 10 sees) .. ' .......... 300'C
Power Dissipalion (Package)' ................... 1200 mW
'All leads soldered or welded to PC board. Derate 10 mW/oC above
70·C.

Y,N (A, EN) 10 Ground ........•............... -15Vl015V
Vs or Vo 10 V+ ....... ~ . . • . . . . • . . • . . . . . . . . . . • . .. 0, -32V
Vs 'or Vo 10 V- .••..............................• 0, 32V
V+ 10 Ground .......•..•.......•..•....•.......... 16\1
V- 10 Ground •............•....••..•.....•....... -16V
Currenl(AnyTerminaD ........................... 30mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional,operatj,on of
the device at these or any other conditions above those indicated,in the operational seotions of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

v+ = 15V v- = -15V VEN = + 5V (Note 1) Ground = OV unless otherwise specified

NO

CHARACTERISTIC

I----:c:-===:----.----::===---i

16
16

Sto 0

rOSION)

TEST CO,NDITIONS

MAX LIMITS
MEASURED TESTS TYP
UNIT
TERMINAL PER
25'C r_--,M-S-U-FF-I,X---+---.C-S-U-F-F-'Xr--~
TEMP
-55'C
25'C
125'C
O'C
25'C
70'C

480
300

s arOS(ON)
w

600
600

600
600

650
650

700
700

650
650

750
750

o

Vo
Vo

= 10V. Is = -10mAjSequence each switch on
-10V, Is 10mA I VAL
O,BV. VAH
3V

%.L\.r

20

DS(on)

=

ros(on)max - rOS(on)mln Vs
ros(on)avg.

= ±10V

I r-----------+--------+~1~6--t70~.0~1~----+-~0~.1~+-~5~0--r-----r-70.~2--r-750~~---r.V~s---1~0~V~,~V-o----~1~OV~r---------------1

~
1:i

I

S

IS(OFF)
IOlOFF)

0

IO(ON)

o

16
1
1
16
16
4
4

IA(on) or

N IAloft)
P
U ',0.

IT

0.01
0.1
0.1
0,1
0,1
.01
.01

EN

o

topen

o
o

y

tEN(on)

o

ttrans

50
100
100
100
100
30

0.2
0.4
0.4
0.4
0.4
10
10

50
100
100
100
100
30
30

-10
10

-30
-30

-10
10

-30
30

-30

nA

0,2
O.B
0.3
60

Vs - -10V, Vo - 10V
Vo - 10V, Vs -10V
Vo - 10V, Vs - 10V
VSIAII) - Vo - 10V
VSIAII) Vo
10V
VA 3,OV"
VA 15V'",

VEN = 0
Sequence each switch on
VAL O,BV, VAH 3V

VEN = 5V
All VA;' 0
r.V~EN'---:O:'----""1...l

Q,6

o
o

N tEN(o")
A "OF~" Isolation

0.1
0.2
0.2
0,2
0.2
10
10

1.5
1

!'S

See Fig, 1
See Fig. 2
See Fig, 3

dB :VEN

0, RL

2000, CL

3pF, Vs

3 VRMS,

M~~~------+---,,---t-----t~~r----t-----t-----t-----t__---r----i----r.f~=~5~0~0~k~H~Z------.---------------4

I C.(OFF)
C Cd(OFF)

5
40

S
0

pF

Vs - 0
Vo - ()

VEN = O.'f
MHz

= 140 kHz to

1-_____-:-_-11
Cd.IOFF)

0 to S

1

Vs = 0, Vo = 0

5;

~ ~~~~~t

+
~+
~
~~~
~~~~
P~~~--~~~~--+-~-+~-+----~~-r----I-----r~~r-~
standby
+
V+
1
1
100
1000

VEN = 5V

Y Current

VEN

r

-

V

1

1

100

NOTE 1: See Section V. Enable Input Strobing Levels.

1000

11

<:

lOOns

=0

3V

VA
I, <: lOOns

. O.8Y

--:Ir--

50%

----t--

ttranS(16-1j

---,+10V
S1

S.

Your

S3

VS1 "" +10V
YS16 == -10Y

s.

SS
S6
S7
S8
S9
S10

ttrans(t-1Sl

il"=;;;;.;-1I;::V:"'''''''-!I-10V

S11

r-- S10N --1

S1'
S13
S1.
S1S
S16

o

<'

Rp 5V is necessary for the driver to work properly.

e

GENERAL DESCRIPTION
The IH6201 is a CMOS, Monolithic, Dual Voltage Translator;
it takes the low level TTL or CMOS logic level and converts
them to higher levels (i.e. to ±15V swings), This translator is
typically used in making solid state switches, or analog
gates.

BLOCK DIAGRAM
+5V

SCHEMATIC DIAGRAM (ONE CHANNEL)

DRIVER

+5V

OUTPUT

DRIVER
OUTPUT

'1

'2

8,

-=-

82

PIN CONFIGURA TlON

01 1 •
2

01
82 5
82 •

---....----',

DRIVER
OUTPUT

8

OUTLINE DWGS
DE,je:-~-

ORDERING INFORMATION
PART NUMBER
'IH6201CDE
'IH6201MDE
IH6201CJE
IH6201MJE
IH6201CPE
'Special Order Only

TEMPERATURE RANGE
O°C to 70°C
-55°C - +125°C
O°C to 70°C
-55°C to 125°C
O°C to 70°C

3-105

Ii

<

IH6201
ABSOLUTE MAXIMUM RATINGS
V+to V- .....................•.......................
V+ ..................................................
V- ..................................................
V+ to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

35V
35V
35V
40V

Operating Temperature. . . . . . . . . . . . . .. - 55·C to + 125·C
Storage Temperature ................. - 65·C to + 150·C
Lead Temperature (Soldering 10 sec) ............... 300·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ELECTRICAL SPECIFICATIONS v+ = +15V, v- = -15V, VL
ITEM
e or ij driver output swing

=

+5V

IH6201CDE
IH6201MDE
-25°C +25°C +85°C -55°C +25~C +125°C UNITS
28
28
Vpp
28
28
28
28

CONDITIONS
+3V
fig. 28
VIN=OV.rL.

VIN strobe level ("1 ") for
proper translation

e ~ 14V

3.0

3.0

3.0

2.4

2.4

2.4

Vo.c.

VIN strobe level ("0") for
proper translation

e ~ -14V

0.4

0.4

0.4

0.8

0.8

0.8

Vo.c.

= OV or +5V

1

1

1

1

1

1

p.A

ton time

vlN=ovA CL = 30pf
switching turn-on time
fig. 28

400

400

400

300

300

300

nS

toft time

vlN=ovA CL = 30pf
switching turn-off time
fig. 28

300

300

300

200

200

200

nS

liN input strobe current draw
(for OV - 5V range)

0" ~ -14V

O"~ 14V

VIN

1+ (V+) power supply
quiescent current

VIN = OV or +5V

100

100

100

100

100

100

p.A

1- (V-) power supply
quiescent current

VIN

= OV or +5V

100

100

100

100

100

100

p.A

IL (VL) power supply
quiescent current

VIN = OV or +5V

100

100

100

100

100

100

p.A

APPLICATIONS
SIGNAL INPUT

I. INPUT DRIVE CAPABILITY
The strobe input lines are designed to be driven from TTL
logic levels; this means 0.8V - 2.4V levels max. and min.
respectively. For those users who require 0.8V to 2.0V
operation, a pull-up resistor is recommended from the TTL
output to +5V line. This resistor is not critical and can be in
the 1kfl to 10kfl range.

+3V

T2L INPUT

SWITCH
OUTPUT

RL

When using 4000 series CMOS logic, the input strobe is
connected direct to the 4000 series gate output and no pull
up resistors, or any other interface, is necessary.
When the input strobe voltage level goes below Gnd (i.e. to
-15V) circuit is unaffected as long as V+ to VIN does not
exceed absolute maximum rating.

II. OUTPUT DRIVE CAPABILITY
The translator output is designed to drive the Intersil IH401
family of Varafets; these are N-channel J-FETS with built-in
driver diodes. Driver diodes are necessary to isolate the
signal source from the driver/translator output; this prevents
forward biasing between the signal input and the +Vcc
supply. The IH6201 will drive any J-FET provided some sort
of isolation is added i.e..

JL

----I

Figure 1

You will notice in Figure 1 that a "referral" resistor has been
added from 2N4391 gate to its source. This resistor is needed
to compensate for inadequate charge area curve for isolation
diode (i.e. if C vs. V plotfordiode:s 2 [C vs. V plotfor output JFET] switch won;t .function; then adding this resistor
overcomes this condition. The "referral" resistor is normally
in the 100kH to 1MOrange and is not too critical.

III. MAKING A COMPLETE SOLID STATE SWITCH
THAT CAN HANDLE 20Vpp SIGNALS
The limitation on signal handling capability comes from the
output gating device. When a J-FET is used, it's the pinch-off
of the J-FET acting with the V- supply that does the

3·106

IH6201
APPLICATIONS, CONTINUED
limiting. In fact max. signal handling capability = 2 (Vp +
(V-)) Vpp where Vp = pinch-off voltage of J-FET chosen.
i.e. Vp = 7V, V- = -15V :. max. signal handling = 2 (7V +
H5V)) Vpp = 2(7V-15)pp=2(-8Vpp)=16Vpp. Obviously to
get 2: 20Vpp, Vp 2: 5V with V- =-15V. Another simple way to
get 20Vpp with Vp = 7V, is to increase V- to -17V. In fact
using V+ = +12V or +15V and setting V- = -18V allows
one to switch 20Vpp with any member of IH401 family. The

advantage of using the Vp = 7V pinch-off (along with
unsymmetrical supplies) over the Vp = 5V pinch-off (and
±15V supplies) is that you will have a much lower ROS(ON)
resistance for the Vp= 7V feUi.e. forthe 2N4391 fet
rOS(ON) '" 220, rOS(ON) '" 350)
Vp =7V
V p =5V

The IH6201 is a dual translator, each containing 4 CMOS FETs. The schematic of one-half IH6201, driving one-fourth of an
IH401, is shown in Figure 2A.
3V

OV

t----

'----l
I
I
I

I

4", -----J

I
I
I

S

I

L~A~~T_J
+15V

OV

+15Y

-15V~
I
I
I

I

I

+15V

I

-U-

-15
+15

-15V

OV

-15V
TRANSLATOR

Figure 2B

Figure 2A
NOTE:

Each translator output has a

e and ii output. e is just the inverse of ii.

A very useful feature of this system is that one-half of an IH6201 and one-half of an IH401 can combine to make a SPOT switch,
or an IH6201 plus an IH401 can make a dual SPOT analog switch. (See III.)

I. Dual SPST Analog Switch

II. DPDT Analog Switch

NOTE: Either switch is turned on when strobe input goes high.

3-107

IH6201
APPLICATIONS, CONTINUED
III. Dual SPOT

IV. Dual DPST

IH6208
4·Channel Differential
CMOS Analog Multiplexer
FEATURES

GENERAL DESCRIPTION

• Ultra low leakage - 10(011) :::; 100pA
• rOS(on) < 400 ohms over full signal and temperature
range
• Power supply quiescent current less than 100~A
• ±14Vanalog signal range
• No. SCR latch up
• Break·before·make switching
• Binary Address control (2 Address inputs control 2
out of 8 channels)
• TTL and CMOS compatible Address contr:ol
• Pin compatible with HI509, DG509 & AD7509

The IH620B is a monolithic 2 of B CMOS multiplexer. The part
is a plug·in replacement for the OG509. Two line binary decoding is used so that the B channels can be controlled in pairs
by the binary inputs; additionally a third input is provided to
use as a system enable. When the ENable input is high (5V)
the channels are sequenced by the 2 line binary inputs, and
when low (OV) all channels are off. The 2 Address inputs are
controlled by TTL logic or CMOS logic elements with a "0"
corresponding to any voltage less than O.BV and a "1" corresponding to any voltage greater than 2.4V. Note that the
ENable input must be taken to 5V to enable the system, and
less than O.BV to disable the system.

FUNCTIONAL DIAGRAM

DECODE TRUTH TABLE

51.

52'~
r--

S3a~

54.~O---

EN5WITCH
I
I
I
I
I
I
I
I
I

Slb

Ao

EN

ON
SWITCH
PAIR

X

X

0
0
1
1

0
1
0
1

0
1
1
1
1

NONE
la, lb
2a,2b
3a,3b
4a,4b

0,

Ao, Al

02

LOGIC "1"
LOGIC "0"

52b~
r--

53b~

Al

Ao fI
EN I]

ADDRESS DECODE
10F4

!

VENH 2: 4.5V

PIN CONFIGURATION

S4b~O---

I

= VAH 2: 2.4V
= VAL:5 O.BV

~

v- []

I

51.

EN

2 LINE BINARY ADDRESS INPUTS
(0 O)ANDEN=5V(EN="1"FOR +5V,"0"FOROV,
ABOVE EXAMPLE SHOWS CHANNELS 1. & lb ON.

11

.......,.• -

IiID

A1

Illl GNO
IBI v+
!llJ 51b

S2. [[

IIil S2b

53.

IJ:

[ll) S3b

54.

IT

0,

IJ:

~ S4b

fil 02

ORDERING INFORMATION
Ceramic package available as
special order only (lH6208MDE/COE)

PART NUMBER

TEMPERATURE RANGE

IH6208MJE

-55°C to +125°C

PACKAGE

IH6208CJE

O°C to 70°C

16 pin CERDIP
16 pi.n CERDIP

IH6208CPE

O°C to 70°C

16 pin Plastic DIP

3-109

B

•

.D~nl1.

IH6208
ABSOLUTE MAXIMUM RATINGS
l1iN(A,

EN)

Current(AnaloQSourceorDraifl) ••...•........... 20mA

to Ground ......................... -15V, V1

Operating Temperature

Vs or Vo to V+ •••••••••••••.••••••••••••••••••• 0, -32V
Vsor Vo to V- • ,......... : ......... ; ........ ; .... 0, 32V
V+ to Ground .......... : ..........................

..................

-55 to 125°C

Storage Temperature .................... -65 to 150°C
Lead Temp (Soldering,10 sec) . . • . . . . . . . . . . . . . . . . . 300°C

16V

Power Dissipation (Package)* .................

1200 mW

• All leads soldered or welded to PC board. Derate 10 mWfO C above
70°C.

V- to Ground .................................... -16V
Current (Any Terminal) ••••• '..••.•.•••••••••.•••. 30 mA

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of

the device at these or any other conditjons, above those indicated in the operational sections of the specif,ications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability. '

ELECTRICAL CHARACTERISTICS

V+; 15V, V- ; -15V, VEN ;

+ 5V (Note 1), Ground; OV,

NO
CHARACTERISTIC MEASURED TESTS TYP
MAX LIMITS
TERMINAL
PER
M SUFFIX
C SUFFIX
25'C
TEMP
-55'C 25'C 125'C O'C
25'C 70'C
Sto 0

rosloNI

8
8

180
150

300
300

300
300

400
400

350
350

350
350

450
450

20

S droSIONI

TEST CONDITIONS
UNIT

J

0

Vo = 10V, 1';= -1.0.rnA Sequence each switch on
Vo - -10V, Is - -1.0 m~VAL =0.8V, VAH =2.4V

%

aros(on)

=

W
I
T ISIOFFI
C
H 1010FFI

S

0
0

lOON
I IAlonl
N IAlofll
P
U IA
T
tapen
teN(an)
tEN(aff)

"OFF" Isolation

EN
0
0
0
0
0

2
1
0.3
0.2
0.6
0.4
60

S

C'loffl
Cdloffl

50
50
50
50
50
50
30
30

0.1
0.1,
0.2
0.2
0.4
0.4
10
10

100
100
100
100
30
30

-10
-10
1

-30
-30

-10
-10

-30
-30

50
~O

1.5
1

nA

~s

dB

U Current

P
P Standby
,Current

5
12

0

pF

+

o to S
·V+

1

40

200

Cds(off)

Y

0.05
0.05
0.1
0.1
0.2
0.2'
-10
10

Y§.. 10V Vo -10V
Vs - -10V, Vo - 10V
Vo - 10V, Vs - -lOY
Vo - -10V. Vs - 10V
VSIAII -Vo - 10V
V§lAIII- Vo- 10V
VA 2.4V or OV
VA-15VorOV

Vs = ±10V

VEN = 0

SeqlJence each switch on
VAL =0.8V, VAH =2.4V

VEN
VEN
See
See
See

AIIVA=O
-.l(Address Pins)

= 5V
- 0
Fig. 1
Fig. 2
Fig. 3

VEN = 0, RL = 2000, CL = 3 pF. Vs = 3 VRMS,
f = 500 kHz

S Supply

L

0.002
0.002
0.03
0.03
0.1
0.1
.01
.01

ros(on)max ..:.. rOS(on)min
rDS(on)avg.

~A

AO, A1

ttrans

0
Y
N
A
M
I
C

8
8
2
2
8
8
2
2

unless otherwise specified.

1

Vs =0
Vo - 0

VEN = 0, f = 140 kHz to
1 MHz

Vs = O. Vo = 0
1000

-

V-

1

2

100

1000

+

V+

1

1

100

1000

-

V-

1

1

10.0

1000

VEN = 5V
~A

All VA=O or 5V
VEN =0

NOTE 1: See SeclJon I. Enable Input Strobing Levels.

SWITCHING INFORMATION
3,OV
1.4V

S1.

O.8V

52.
53a
54.
51b
52b
53b

At

Ao

':'

54b

10V

IH6208

EN

PROBE IMPEDANCE
,Rp 2:: 1MO
CP:5 30pF

Figure 1. itran. Switching Test

3-110

IH6208
SWITCHING INFORMATION (Continued)
+15V

r---'-l-~~~--<>-2V

l ..,___.,....t~!l:::-r:VOUT
35pF

Figure 2. lopen I Break-Before-Make I Switching Test

+5V

1,80 I, $1:.':.

J------~------~"'

_____

+15V

tEN(Off)

OV
O.IYa

1---+-"""I"-+-----t---t"7'--Al

r----..-,~~S~I~b~-----O-5V

SWITCH OUTPUT

Your
(SEE FIG. 3)

35pF
O.9Va
Va
_5V

Figure 3. Ion and loff Switching Test

IH6208 APPLICATION INFORMATION

I. ENable Input Strobing Levels
The ENable input on the IH620B requires a minimum of
+ 4.5V to trigger it into the "1" state and a maximum of
+ O.BV to trigger it into the "0" state. If the ENable input is

14 +5V

being driven from TTL logic, a pull-up resistor of 1k to 3kfl is
required from the gate output to + 5V supply. (See Figure 4).

lK

DM7404N
TTL LOGIC
+3V
11~

Figure 4. ENable Input Strobing from TTL Lagic

3-111

IH6208
IH6208 APPLICATION INFORMATION

(Continued)

When the EN input is driven from CMOS logic, no pullup is necessary. (See Fig. 5)
+5V

Figure 5. CMOS Logie Driving ENable Pin.

The supply voltage of the CD4009 affects the switching speed of the IH6208; the same is true for TTL supply voltage levels. The
chart below shows the effect on ttrans for a supply varying from +4.5V to +5.5V.

CMOS OR TTL SUPPLY
+4.5V
+4.75V
+5.0V
+5.25V
+5.50V

TYPICAL Ilrans @ 25°C
400ns
300ns
250ns
200ns
175ns

The throughput rate can therefore be maximized by using a + 5V to + 5.5V supply for the ENable Strobe Logic.

The'examples shown in Figures 4 and 5 deal with ENable strobing when expansion to more than four differential channels is
required; in these cases the EN terminal acts as a third address input. If four channel pairs or less are being multiplexed, the
EN terminal can be directly connected to + 5V to enable the IH6208 at all times.

3-112

IH6208
IH6208 APPLICATION INFORMATION (Continued)

II. Using the IH6208 with supplies other than

±15V

The IH620B can be used with power supplies ranging from
±6V to ±16V. The switch ros(on) will increase as the supply
voltages decrease, however the multiplexer error term (the
product of leakage times rOS(on)) will remain approximately
constant since leakage decreases as the supply voltages are
reduced.

2.5V of the EN voltage in order to define a binary "1" state.
For the case shown in Figure 6the EN voltage is 11.3V, which
means that logic high at AO and A1 is = +B.BV (logic low
continues to be = O.BVI. In this configuration the IH620B
cannot be driven by TTL (+5V) or CMOS (+5V) logic.ltcan be
driven by TTL open collector logic or CMOS logic with +12V
supplies.

Caution must be taken to ensure that the enable (EN) voltage
is at least O.7V below V + at all times. If this is not done the
Address input strobing levels will not function properly. This
may be achieved quite simply by connecting EN (pin 2) to V +
(pin 14) via a silicon diode as shown in Figure 6. A further
requirement must be met when using this type of
configuration; the strobe levels at AO and A1 must be within

If the logic and the IH6208 have common supplies, the EN pin
should again be connected to the supply through a silicon
diode. In this case, tying EN to the logic supply directly will
not work since it violates the O.7V differential voltage
required between V+ and EN (See Figure 7). A 11'F capacitor
can be placed across the diode to minimize switching
glitches.

1N914

+12V

• _,a ro",",

,,~,1

A CHANNELS
COMMON DRAIN OUTPUT

= D.

1

I'"' ' '

' -_ _ _ _ _-1

9 02

,,,,cr "mn

= B CHANNEL DRAIN OUTPUT
(COMMON)

Figure 6. IH6208 Connection Diagram for less than ±15V Supply Operation.

3·113

I.

IH6208
IH6208 APPLICATION INFORMATION

(Continued)

1N914
I
I

...

..

I
I

_~!""_..J

EN

161-+-+--~-------------j

Figure 7. IH6208 Connection Diagram with ENable Input Strobing for less than ± 15V Supply Operation.

III. Peak-Io-Peak Signal Handling Capabilily
The IH6208 can handle input signals up to ±14V (actually
-15V to +14.3V because of the input protection diode) when
using ±15V supplies .•

3-114

The electrical specifications of the IH6208 are guaranteed
for ±10V signals, but the specifications have very minor
changes for ±14V signals. The notable changes are slightly
lower roS(on) and slightly higher leakages.

IH6216
a-Channel Differential
CMOS Analog Multiplexer
FEATURES

GENERAL DESCRIPTION

• Pin compatible with H1507, DG507 & AD7507
• ± 11V analog signal range
• rDS(on) < 700 ohms over. full signal and temperature
range
• Break-before-make switching
• TTL and CMOS compatible Address control
• Binary Address control (3 Address inputs control 2
out of 16 channels)
• Two tier submultiplexing to facilitate expandability
• Power supply quiescent current less than 100ILA
• No SCR latch up
• Very .Iow leakage ID(off) :5 100pA

The IH6216 is a CMOS monolithic 2 of 16 multiplexer. The part
is a plug-in replacement for the DG507. Three line binary
decoding is used so that the 16 channels can be controlled in
pairs by the binary inputs; additionally a fourth input is provided to use as a system enable. When the ENable input is
high (5V) the channels are sequenced by the 3 line binary inputs, and when low (OV) all channels are off. The 3 Address inputs are controlled by TTL logic or CMOS logic elements with
a "0" corresponding to any voltage less than O.8V and a "1"
corresponding to any voltage greater than 3.0V. Note that the
ENable input must be taken to 5V to enable the system and
less than O.8V to disable the system.

FUNCTIONAL DIAGRAM

DECODE TRUTH TABLE

51. 0--+<>--

A2

Al

AD

EN

SWITCH
PAIR

X
0
0
0
0
1
1
1
1

X
0
0
1
1
0
0
1
1

X
0
1
0
1
0
1
0
1

0
1
1
1
1
1
1
1
1

NONE
1
2

ON
52. 0--'"0-53.

o--"o--~

54. 0--"0--

S5.~~

5 •• 0--'"
57a

~<>--r, _ D,

0--"

• 0---1

58. 0--'"

Slb~:¥p:=L
S2b~
S3b0--'"

U

4
5
6
7
8

LOGIC "1" = VAH > 3V VENH > 4.5V
LOGIC "0" = VAL < O.BV

.D2

S4bo--'"
55b 0--"<>,--

3

PIN CONFIGURATION

S6b 0--"0-S7b 0--'"0--

V~~~"D'

S8b 0--'"0---

:~~
S8b~~5
S7b

TO DECODe lOGIC
CONTROLLING BOTH
TIERS OF MUXING

I

::::

ADDRESS OECODE

1 OF 8

~ ~

l, E~

I

ENABLE

1 OF 2

S4b~

I

:::~

S1b~

G:~~
(ENABLE INPUT)

NC14

~~
~ 57.
56a

f24

~::
21 S3a

:::
18 EN

17

Ao

~::

TOP VIEW
Y+ COMMON TO SUBSTRATE

3 LINE BINARY ADDRESS INPUTS
(0 0 0)ANDEN=5V
ABOVE EXAMPLE SHOWS CHANNELS ,. & lb ON.

ORDERING INFORMATION
Ceramic package available as
special order only (IH6216MDI/CDI)

PART NUMBER
IH6216MJI
IH6216CJI
IH6216CPI

TEMPERATURE RANGE

3-115

PACKAGE
28 pin CERDIP
28 pin CERDIP
28 pin Plastic DIP

I

IH6216
ABSOLUTE MAXIMUM RATINGS
VIN (A, EN) to Ground .......................... -15V, V1
Vsor Vo. to V· ..•.... " ........ : .......•........ 0, -32V
Vs ·or Vo to V- .. ,............................... 0, 32V
V+ to Ground ... '.................................. 16V
V- to Ground .................................... -16V
Current(AnyTerminaD ........................... 30mA
Current(Analog Source or Drain) ............... ~ •. 20mA

Operating Temperature .................... -55t0125°C
Storage Temperature ...................... -65t0150°C
Power Dissipation (Package)' .................. 1200mW
Lead Temperature (Soldering 10 sec) .............. 300'C
'AII leads soldered or welded to PC board. Derate 10 mW/oC above
70°C

Stresses above those listed under Absolute Maximum Ratings may cause permanentdamag9 to the device, These are stress ratings only, and functional operation of

the device at these or any other conditions abQve those indicated in the operational sections of the specifications is not implied: Exposure to ~bsolutemaximum
rating conditions for extended periods may affect device reliability,
'

ELECTRICAL CHARACTERISTICS y+ = 15Y, Y-

= -15Y,V EN = .j. 5Y (Note 1), Ground =OV, unless otherwise specified.

NO
CHARACTERISTIC

MEASURED TESTS

TYP

TERMINAL

2S°C

PER
TEMP

D

S to 0

rOS(ON)

16
16

480
300

S .lrOSION)

MAX LIMITS

--55°C

25°C

125°C

O°C

25°C

70°C

600
600

600
600

700
700

650
650

650
650

750
750

%

20

I

S

H 1010FF)

0
0

1010N)
I 'IA{onIO r
N IAloft)

Ao A,
A2 As

P
U IA
T

EN

ttrans

o
Y
N

topen
ton(EN)
toff(EN)

A "OFF" Isolation
M C
I
'
C Cdloff)

16
16
2
2
16
16

0.Q1
0.01
0.1
0.1
0.1
0.1

3
3

.01
.01

0
0
0
0
0

0.6
0.2
0.8
0.3
60 .

S

5
20

o to S

Cd,

+

P
P Standby
y Current

L

-

+

V'
V
V'
V

50
50
100
100
100
100
30
30

-10
-10

-30
-30

0.2
0.2

OA
0.4

OA
0.4
-10

50
50
100
100
100
100

10

30
30

-10
-10

-30
-30

Vo = -10V. IS = 10mA VAL =O.BV, VAH "'3V
..\

_ rOS(on)max - rOS(on)min
rOS(on) rDS{on}avg

Vs = 10V. Vo = -10V
Vs ~ -10V, Vo = 10V
nA Vo - 10V, Vs - -10V
Vo - -10V. Vs - 10V

Vs= ±10V

VEN = 0
Sequence each swltch on

VSIAII) - Vo - 10V
VSIAIII- Vo '" 10V

VAL =O.BV. VAH =3V

VA 3.0V
VA - 15V
MA

3
1

0

S Supply
U Current

0.1
0.1
0.2
0.2
0.2
0.2
10
10

I
I

Vo =' 10V, Is = -10mA Sequence each switch on

n

W

T IS OFF
C

TEST CONDITIONS

UNIT
C SUFFIX

M SUFFIX

1
1
1
1

1
55
2
1
1

1
1.5
1

MS

dB

pF

All VA = 0

VEN = 5V
VEN - 0
See Fig. 1
See Fig. 2
SeeFig.3
200!!, CL

VEN 0, RL
f ~ 500 kHz
Vs - 0
Vo - 0

3 pF. Vs

3 VRMS,

VEN = O.f = 140 kHz to
1 MHz

Vs - O. Vo - 0
1000
1000
1000
1000

200
100
100
100

VEN = 5V
AIIVA=00r3V

MA
VEN = 0

NOTE 1: See Section V. Enable Input Strobing Levels.

SWITCHING INFORMATION
3.0V

1.4V
0.8V

1---""'1

A2
A,
Ao

VA
':'

':'

EN

v-. 02

VOUT

"

Rp 4.~

O.9VSBb
VS8b

"

;~: Cp
I

~ --:!:- ;R08E IMPEDANCE
••

3-116

Rp;::: 1M!)
Cp 5: 30pF

.O~DIl

IH6216
SWITCHING INFORMATION

(Continued)

t15V

51.
'-2V

SWITCH OUTPUT
vo
(SEE FIG. 2)

~~4'

~:l

A2

fit

A

vs

52.

THRU

S7.

-::-

58.
YOUT

n

D2

v,

35pF

Figure 2
+15V

S1.
O.1Vo

ALL OTHERS

A,

-5V

SWITCH OUTPUT

Vo
(SEE FIG. 3)

YOUT

D2
35pF

O.9Vo

Vo
Vs

Figure 3

IH6216 APPLICATIONS
I. 2 out of 32 channel multiplexer using 2 IH6216s
-15V

+15V

1
Ao
A1
A2

1

L.
TTL'/CM
INVERT E~5

-

IH6216
EN

I.:.

58~ ~'b-

--

s;~

+15V

-15V

1

1

~

1-

~VOUT1

~

VOUT2

t---

~

IH6216
EN

1-------1 1-------1
59.

516.

59b

516b

'1

-TTL gate must have puUup to drive EN input

Figure 4
DECODE TRUTH TABLE
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Ao
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ON SWITCH
81a
82a
83a
84a
85a
86a
87a
88a
89a
810a
811a
812a
813a
814a
815a
816a

DECODE TRUTH TABLE
A3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

VOUTI

3·117

A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

Al
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

Ao
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

ON SWITCH
Slb
S2b
S3b
S4b
85b
86b
S7b
88b
89b
810b
Sllb
S12b
S13b
S14b
S15b
S16b

VOUT2

Bl

IID~DIl

IH821.6
IH6216 APPLICAnONS (Continued)
II. 2 out of 32 channel multiplexer using 2 IH6216s; with an IH5043 for submultiplexing

Ao

+5V

-15V

+15V

+15V

<>---t---I

Al<>--~+-l

IH6216

A, o-----

VL = +5Vj

•

51

b

53

~

~

"-

.....

b

IH6216

I

";7

~9.

516~

51;~ ~9b

pIH5043

IN1

I

-

J..~

1

54

I

~

b

53

-I I'

'l-

-I

S17b

S24b

+1SV

-lSV

J

1

'---

IH6216

- -

-;3;~ ~;5;;- -

- -

-;3;~

Bl

02

1

04

-15V!

Vee = +15Vr
D1

I

IH5043

~ W3
I
I

_J

IN1
IN2

~

VEE =

-:Ii:

-l

•
b

EN

~;; -

VL = +svf

IH6216

S248

11178

W3

I
I

1
1

52

51

EN

VOUT1

-l

,

•

>--

I

1:

0,

-~

VAl
-lSV
1

+l SV

-r>

I~

EN

I

i

I

IN2

•

Vee = +15V

I
52

1.-.;: .

54

1

~
VAl

D2

VOUT2

--J.

VEE = -15V!

TTL/"CMOS" INVERTER

TTL/CMOS NOR GATE
(TTL gate must have resistor
pullup to drive EN)

Figure 6

IV. General note on expandability of IH6216
The IH6216 is a two tier multiplexer where 8 pairs of input
channels are routed to a pair of outputs in blocks of 4. Each
block of 4 input channels is routed to one common output
channel, and thus the submultiplexed system looks like 4
blocks of 4 inputs routed to 4 different outputs with the 4
outputs tied in pairs. Thus 20 switches are needed to handle

the 16 channels of information. The advantages of this are
lower output capacity and leakage than would be possible
using a system with all 8 channels tied to one common
output. Also the expandability into 2 out of 32,64,128, etc. is
facilitated. Figures 4, 5, and 6 show how the IH6216 is
expanded.

3·119

IH6216

3

Figure 4 shows a 2 of 32 multiplexer using 2 IH6216s. Since
the 6216 is itself a 2 tier MUX, the system as shown is
basically a 2 tier system. Corresponding output pOints of
each of the 6216 are connected together, and the ENable input strobe is used as the A3 input. Since each output (pins 2
and 28) corresponds to an "ON" FETand an "OFF" FET, the
overall system looks like 1 "ON" FET and 3 "OFF" FETs for
each of the Vout1 and Vout2 outputs. Thus the output leakage
will be 1 10(on) plus 3 10(oft)s or about 0.4 nA at room
temperature. Thruput speed will be typically 0.8ILs for ton and
0.3jLs for toft, with thruput channel resistance in the .s000
area.
Figure 5 shows the 2 of 32 MUX of Figure 4, with a third tier of
submultiplexing added to further reduce leakage and output
capacity. The IH5043 has typical ON resistance of 500 (max.
is 150> so it only increases thruput channel resistance from
the 500 ohms of Figure 4 to about 550 ohms for Figure 5.
Thruput channel speed is a little slower by about 0.5ILs for
both ON and OFF time, and output leakage is about 0.2 nA.
Figure 6 shows a 2 of 64 MUX using 3 tier MUXing (similar to
Figure 5>' The Intersil IH5043 is used ·for the third tier of
MUXing. Each Vout point will see 3 OFF channels and 1 ON
channel at any time, so that the typical leakages will be about
0.4 nA. Thruput charme1 resistance will be in the 5500 area
and thruput switching speeds will be about 1.3ILs for ON time
and 0.8ILs for OFF time.
The IH5043 was chosen as the third tier of the MUX because
it will switch the same AC signals as the IH6216 (typically
plus and minus 15V) and uses break before make switching.
Also power supply quiescent currents are typically 1-,2p.A so
NOTE:

that no excessive system power is generated. Note that the
logic of the 5043 is such that it can be tied directly to the
I;::Nable input (as shown in the figures) with no extra logic
being required.
V. Enable Input strobing levels
The ENable input acts as an enabling or disabling pin for
the IH6216 when used as a 2 out of 16 channel MUX, however
when expanding the MUX to more than 16 channels, the EN
pin acts as another address input. Figures 4 and 5 show the
EN pin used as the A3 input:
For the system to function properly the EN input (pin 18)
must go to 5V ±5%for the high state and less than O.8Vforthe
low state. When using TTL logic, a pull-up of 1kO or less
resistor should be used to pull the output voltage up to 5V.
When using CMOS logic, the high state goes up to the power
supply so no pull-up is required.
If used on high voltage logic supplies, EN should be at least
0.7V below V + at all times. See IH6208 data sheet for details.

APPLICATION NOTES
Further information may be found in:
AOO3 "Understanding and Applying the Analog Switch," by
Dave Fullagar
A006 "A New CMOS Analog Gate Technology," by Dave
Fullagar
A020 "A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing," by Ed Slieger
ROO9 "Reduce CMOS Multiplexer Troubles Through Proper
Device Selection," by Dick Wilenken

This multiplexer does not require external resistors and/or diodes to eliminate what is commonly known as a latch up or SCR action.
Because of this fact, the rOSION) of the switch is maintained at specified values.

3-120

AID Convertersl
DVM Circuits
ADC0801-4
ICL7106/7
ICL7109
ICL7115
ICL7116/17
t ICL7126
ICL7129
ICL7135
ICL7136
ICL7137
ICL8052A/7104
ICL8068/7104

D/A Converters
Page
4-4
4-20
4-30
4-46
4-59
4-67
4-75
4-98
4-108
4-116
4-166
4-166

ICL7134
ICL7145
ICL7146
AD7520/21 130/31
AD7523
AD7533
AD7541

4-86
4-124
4-132
4-138
4-144
4-148
4-152

D/A Current
Switches
ICL8018A/19A/20A

4-158

tThe ICL7136 is recommended for all applications which currently
employ the ICL7126.

DATA ACQUISITION

Integrating Analog-to-Digital Converters for Display
Maximum Electrical Specification at 25°C unless otherwise noted.
Model

tCL7136

ICL7137

tCL7135

ICL71Z9

ICL7106/1CL7116

ICL7107/1CL7117

Resolution

±3Y, Digit

±3Y, Digit

±4Y, Digit

±4Y, Digit

±3Y, Digit

±3'/z Digit

Zero Input Reading
Ratiometric Reading
VI~ ,: V~EF
Ro lover rror,

± 1 Count
±O.OOO
±1.000
± 1 Counl
± 1 Count

± 1 Count
±O.OOO
±1.000
± 1 Count
± 1 Count

± 1 Count
±O.OOO
±1.000
±1 Count
±t Count

± 1 Count
±O.OOO
±0.9997
±3 Counts
±1 Count

± i Count
±O.OOO
±1.000
± 1 Count
± 1 Count

± 1 Count
±O.OOO
±1.000
± 1 Count
± 1 Count

Stability
Otfs,et vs.
Temperature
Gain vs.
Temperature

lp.V ICC

lp.V/oC

lp.V/oC

lp.V/oC

lp.V/oC

lp.V/oC

5 ppm/oC

5 ppm/oC

5 ppm/oC

5 ppm/oC

5 ppm/oC

5 ppm/oC

Conversion
Time

0.1 10 3
conv/sec

0.1 to 3
conv/sec

0.1 to 15
conY/sec

0.1 to 6
conv/sec

0.1 to 15
conv/sec

0.1 to 15
conv/sec

Analog Input
Voltage Range
Impedance
Leakage Current
Noise (weak-to-peak)

± 200mV to ± 2V
10"!)
2pA
15p.V typo

± 200mV to ± 2V
10"!)
2pA
15p.V typo

±2V
10"!)
3pA
15p.V typo

± 200mV to ± 2V
10"!)
lpA
7p.V typo

± 200mV to ± 2V
1O"!)
2pA
15~V typo

± 200mV to ± 2V
10"!)
3pA
15~V typo

Decimal Points
Continuity
Hold, Range Select

Display Hold (7116)

Display Hold (7117)

4y, Digit Triplexed
LCD Display Drive
w/Decimal Paints,
Low Battery and
Continuity Indicators

Direct
7 Segment
LCD Display
AC:4.5V
Down tram V+

Direct
7 Segment
LED DiSplay
Comm Anode
DTl/TTL/CMOS

+9V
1.8mA
40 pin DIP

+9V
1.8mA
40 pin DIP

±5V
1.8mA
40 pin DIP

Accuracy
~on-Linearity

I

Digital Input

.Digital Outputs
Format
Logic level
Power Supply
Voltage
Current
Package

Direct 7 Segment
LCD Display

Direct 7 Segment
LCD Display

Multiplex
BCD

AC:4.5V
Down from V+

AC:4.5V
Down from V+

TTL/CMOS

±5V

±5V
1.8mA
28 pin DIP

+9V
100~A

200~A

40 pin DIP

40 pin DIP

"AlSO available lDll011111114 (no! nlCommellOOd 101 _lIISigns), and ICl7126 (nlCommel108d use ICl7.136).

Integrating Analog-to-Digital Converters for Data Acquisition
Type

Single Chip

Model
Resolution
Accuracy

Two Chip Syllem"""

ICl7t09

Microprocellor
Compatible
Output

±12-Blt Binary

±14-Bit

±16-Bit

±1 Count

:t 1 Count

Yes

Yes

Yes

Noise ITypical1
Input Current
Input Vottage
Range

Programmable'
1 Latched parallel
3 state Binary
2 Controlled 2-8 Bit Byte for ICL7104-12/14
3-8 Bit Byte lor ICL7104-16

Controlled
2-8 bit bytes

Control lines
Conversion
Time
UART Compatible

ICl805ZA/8068
ICl71 04-16

j:.1 Count

Programmable
1 Latched parallel
3 state Binary
"

ICL8052A/8068
ICl7104-14

Run/Hold. Busy. Byte Enables. Mode. Load. Send Enable. Out 01 Range
tOms

BOrns

330ms

Yes

Yes

Yes

10pA
t400mV to
+4.1V

,

30pA 18052)

30pA ' 18052)

+100mV to
+10V

~200mV

"""ICL80S2/8068 and ICL80S3 ~an be combined as analog portion 01 dual-slope AID converter under ,.p control.

for.P8tformance characteristiCS,

I

4-2

10

-lOV

See ICL8052/8068 and ICL 7104-16

Digital·to·Analog Converters·
Maximum Electrical Specification at 25°C unless otherwise noted.
Model

ICL7134U/B

7145

7146

A07523

A07533

A07520 17530)

A07520 17531)

Resoluriol.1

14 bit

16 bil

12 bit

8 bit

10 bit

10 bit

12 bit

Accuracy

J/K/L

J/K

Linearity
Zero Offset
Full Scale Reading

0,01/0.006/0.003"10 0006/0.003%

J/K
0.01%
120 p,V

J/K/L
0,2%/0.1%/0.05%
50 p.A
1,5% max

J/K/L
J/K/L
J/K/L
0.2%/0.1 %/0.05% 0.02%/0_01 %/0.05% 0.2%/0.1 %/0.5%
200 nA
200 nA (300 nA)
200 nA (300 nA)
1,4%
03% typ
0.3% typ

AD7541
12 bit

J/K/L
0,02%1001%10,01%
50 nA

10 nA

10 rnV

0,003%

0.04/0.02%

Temperature
linearity vs

5 ppm/DC

1 ppm/DC typ

5 ppm/"C typ

10 ppm/oC

10 ppm/DC

10 ppm/DC

10 ppm/DC

10 ppm/DC

Temperature

1 ppm/DC

1 ppm/DC typ

1 ppm/DC typ

2 ppm/DC

2 ppm/DC

2 ppm/DC

2 ppmJoC

2 ppm/DC

O.g p,s typ

fSR

0.04/0.02%

fSR

0.3%

Stability
Gain vs

Setting Time
3.,

10.

150 ns

600 ns typ

500 ns typ

500 ns typ

1.,

Input Code
Logic Compatibility
option

OTL/TTl/CMOS

OTliTTl/CMOS

OlL/TTL/CMOS

OTLITTl/CMOS

Binary (U)
2's Complement (8)

Binary or
2's Complement

Binary
Offset Binary

OTl/TTL/CMOS
Binary

2's Complement

OTl/TTl/CMOS
Binary
Offset Binary

Ollse! Binary

OlL/TTL/CMOS
Binary
Offset Binary

Oll/TTl/CMOS
Binary
QlIse! Binary

Power Supply
Voltage
Current

4,5 to S.SV
1.2mA

+610 +16V
100 p,A

+5 to +15V
2mA

+510 +15V
2mA

+510 +15V

2mA

2mA

+5 to +16V
2mA

Package

28 pin DIP

28 pin DIP

16 pin DIP

16 pin DIP

16 pin DIP

18 pin DIP

18 pin DIP

To 1/2 L~B

+3.5 to +6.0V

±4.S to S.SV
5mA
28 pin DIP

*R2R ladder Multiplying Type

~s~u~c~c_e_s_s_iv_e__A~p~p_ro~x~i~m~a~t~io~n_A__n_a_lo~9~.t~O~.D~ig~i_ta_I_C_O_n_v_e_r_te_r_s__________________________________-----l1li]
Model

ADC08D1·4

ICL7115

Resolution

8 bit

14 bit binary

Accuracy

± V.I'/2/V2/1 LSB

± '/2 LSB

Microprocessor
Compatible

Yes

Yes

Output

Programmable:
1. Latched parallel 3'
state Binary

Programmable:
1. Two latched bytes

2. One 8 bit byte

2. 15 bit parallel

Control Lines

CS,

RD,

WR

CS, RD, WR, AO, BUS

Conversion
Time

1001'S

4Ol's

UART Compatible

Yes

No

Input Voltage
Range

5V span

0- 5V

Quad Current Switches ICLS01S/S019/S020
High speed precision current switches for use in current summing OIA converters. Can be purchased indiVidually or In matched sets With accuracies of 0.01%
(ICL8DI8). 0.1'/, IICL8019). or 10% (ICL8020)
.

Sample and Hold

..

..

TJP'

(Vp-pl

(~s)

(mV)

(mV)

Drill
R.le (mV/sec)

)H5110
IH5111
)H5112
IH5113
IH5114
IH5115

:<:7.5
:<:10
:<:7.5
:<:10
:<:7.5
,,10

6
6
6
6
6
6

5
5
5
5
5
5

40
40
10
10
5
5

5
5
5
5
5
5

Vanalog

··CSTO ~ 0.01

tacq

Vlnlect

Yo,

~F

Monolithic Voltage Converter-The ICL7660
range of + 1, 5V throuQh + 10V, May be cascaded tor higher negative outp~t voltages, paralleled for greater output current. used
as a positive voltage multlpher. or any combrnatlon of the above. TYPical supply current IS 170 I'A, and output source resistance IS 551l at TA = 25'C and 10 = 20 mA

Converts ~ositive Yoltage ,in~o negative over ~

4·3

ADC0801-ADC0804
a·Bit Microprocessor
Compatible AID Converters
FEATURES

GENERAL DESCRIPTION

• MOS·4S and MCS·SO/S5 bus compatible-no inter·
facing logic required
• Conversion time < 100its
• Easy interface to all microprocessors
• Will operate "stand alone"
• Differential analog voltage inputs
• Works with bandgap voltage references
• TTL compatible inputs and outputs
• On·chip clock generator
• OV to 5V analog voltage input range (single +5V
supply)
No zero·adjust required

The ADC0801 family are CMOS 8·bit successive approximation A/D converters which use a modified potentiometric
ladder, and are designed to operate with the 8080A control
bus via three·state outputs. These converters appear to the
processor as memory locations or I/O ports, hence no interfacing logic is required.
The differential analog voltage input has good commonmode-rejection, and permits offsetting the analog zero-input·
voltage value. In addition, the voltage reference input can be
adjusted to allow encoding any smaller analog voltage span
to the full g bits of resolution.
The ADC0801 family is available in the industry standard 20
pin CERDIP package.

PIN CONFIGURATION

TYPICAL APPLICATION

cs

v+

RD

ClKR

WR

11
12
13
14
15
16
17
18

INTR
DB,
DBs
DBs

ClKIN
AID

DB.
DB,
DB,
DB,
DBo

VJN(+)

\ljNI-)

6

l

DIFF
INPUTS

r·

BIT
OVERRESOLUTION
ANY DESIRED
ANALOG INPUT
VOLTAGE RANGE

AGND
VREFI2

DGND

":"

TOP VIEW

(Outline dwg. JP)

ORDERING INFORMATION

PART

ERROR

TEMPERATURE
RANGE

PACKAGE

ORDER
NUMBER

O·C to + 70·C
- 40·C to + 85·C
55·C to + 125·C
O·C to 70·C
- 40·C to + 85·C
- 55·C to + 125·C

20 pin CERDIP
20 pin CERDIP
20 pin CERDIP

ADC0801LCN
ADC0801LCD
ADC0801LD

20 pin CERDIP
20 pin CERDIP
20 pin CERDIP

ADC0802LCN
ADC0802LCD
ADC0802LD

± 1/2 bit adjusted full-scale

O·C to + 70·C
-,40·C to + 85·C
55·C to + 125·C

20 pin CERDIP
20 pin CERDIP
20 pin CERDIP

ADC0803LCN
ADC0803LCD
A DC0803LD

± 1 bit no adjust

O·C to + 70·C
- 40·C to + 85·C

20 pin CERDIP
20 pin CERDIP

ADC0804LCN
ADC0804LCD

ADC0801

± 114 bit adjusted fulI·scale

ADC0802

± 1/2 bit no adjust

A DC0803

ADC0804

+

4·4

ADC0801-ADC0804
ABSOLUTE MAXIMUM RATINGS

OPERATING RATINGS

Supply Voltage .................................. 6.5V
Voltage at Any Input ................ - 0.3V to(V+ + 0.3V)
Storage Temperature Range ............ - 65·C to +150·C
Package Dissipation atTA + 25·C .............. 875 mW
Lead Temperature (Soldering, 10 seconds) .......... 300·C

Temperature Range
ADC0801f02f03LD .................. -55·Cto +125·C
ADC0801f02f03f04LCD ............... - 40·C to +85·C
ADC0801f02f03f04LCN .................. O·C to + 70·e

=

Supply Voltage Range ...................... 4.5V to 6.3V

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

SYSTEM ELECTRICAL CHARACTERISTICS (Notes 1 and 7)
Converter Specifications: y+ = 5Y, YREF /2 = 2.500Y, TMIN sTA S TMAX and fClK = 640kHz unless otherwise stated.

PARAMETER

TEST CONDITIONS

MIN

TYP

UNIT

MAX

ADC0801:
Total Adjusted Error

With Full Scale Adjust

±1/4

LSB

ADC0802:
Total Unadjusted Error

Completely Unadjusted

± 1/2

LSB

ADC0803:
Total Adjusted Error

With Full Scale Adjust

±1/2

LSB

ADC0804:
Total Unadjusted Error

Completely Unadjusted

±1

LSB

YREF /2 Input Resistance

Input Resistance at Pin 9

Analog Input Yoltage Range

(Note 2)

DC Common· Mode Rejection

Over Analog Input Yoltage Range

±1/16

±1/8

LSB

Power Supply Sensitivity

Y + = 5Y ± 10% Over Allowed
Input Yoltage Range

±1/16

± 118

LSB

1.0

1.3

kfl
Y++0.05

GND - 0.05

Y

AC ELECTRICAL CHARACTERISTICS
Timing SpeCifications: y+ = 5Y and TA = + 25°C unless otherwise stated.

PARAMETER
Clock Frequency

SYMBOL
fClK

Clock Periods per Conversion (Note 4)

tconv

Conversion Rate In Free·Running Mode

CR

TEST CONDITIONS
V+ = 6Y (Note 3)
y+ =5Y

MIN

TYP

MAX

UNIT

100
100

640
640

1280
800

kHz
kHz

66

73

iNTR tied to WR with

8888

convls

CS = OY, fClK = 640kHz
Width of WR Input (Start Pulse Width)

tW(WR)1

CS = OY (Note 5)

Access Time (Delay from Falling Edge of
AD to Output Data Yalid)

tacc

Cl = 100 pF (Use Bus Driver IC
for Larger Cd

135

200

ns

3·State Control (Delay from Rising Edge
of AD to Hi·Z State)

t'h, tOh

Cl = 10 pF, Rl = 10k
(See 3·State Test Circuits)

125

250

ns

Delay fro~lling Edge of WR to
Reset of I NTR

tWI, tRI

300

450

ns

Input Capacitance of Logic
Control Inputs

CIN

5

7.5

pF

3·State Output Capacitance (Data Buffers)

COUT

5

7.5

pF

4-5

100

ns

ADC0801-ADC0804
DC ELECTRICAL CHARACTERISTICS
Digital Levels and DC Specifications: V+ = 5Voc and TMIN
PARAMETER

SYMBOL

S

T~ s TMAX, unless otherwise noted.

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V+

V

0.8

V

CONTROL INPUTS (Note 6)
logical "I," Input Voltage
(Except Pin 4 ClK IN)

V,NH

V+ = 5.25V

2.0

logical "0" Input Voltage
(Except Pin 4 ClK IN)

V,NL

V+ '" 4.75V

ClK IN (Pin 4) Positive Going
Threshold Voltage

v,h

2..7

3.1

3.5

V

ClK IN (Pin 4) Negative Going
Threshold Voltage

VCLK

1.5

1.8

2.1

V

ClK IN (Pin 4) Hysteresis

VH

0.6

1.3

2.0

V

0.005

1

~A

(VdLK) - (VCLK)
logical "1" Input Current
(All Inputs)

I'NH'

Y,N = 5V

logical "0" Input Current
(All Inputs)

I'NLO

Y,N =OV

Supply Current (Includes
ladder Current)

1+

fClK = 640kHz,
TA = +25'CandCS=HI

logical "0" Output Voltage

VOL

10= 1.6mA
V+ '" 4.75V

logical "1" Output Voltage

VOH

10= -36OI,A
V+ =4.75V

3-State Disabled Output
leakage (All Data Buffers)

ILo

VOUT = OV
VOUT =5V

-1

~A

-0.005
1.3

2.5

mA

0.4

V

DATA OUTPUTS AND INTR

Output Short Circuit Current
ISOURCE
ISINK

V

2.4

~A

-3
3

TA = +25'C
VOUT Short to Gnd
VOUT Short to V+

• 4.5
9.0

6
16

~A

mA
mA

Note 1: All voltages are measured with respect to GND, unless otherwise specified. The separate AGND point should always be wired to
the DGND, being careful to avoid ground loops.
Note 2: For V,N1 _) '" V,N1 +) the digital output code will be 0000 0000. Two on·chip diodes are tied to each analog input (see Block Diagram)
which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the V+ supply. Be
careful, during testing at low V+ levels (4.5V), as high level analog inputs (5V) can cause this input diode to conduct-especially at elevated
temperatures, and cause errors for analog inputs near full·scale.As long as the analog Y,N does not exceed the supply voltage by more
than 50mV, the output code will be correct. To achieve an absolute OV to 5V input voltage range will therefore require a minimum supply
voltage of 4.950V over temperature variations, initial tolerance and loading.
Note 3: With V+ '" 6V, the digital logic interfaces are no longer TTL compatible.
Note 4: With an asynchronous start pulse, up to 8 clock periods may be required before the internal clock phases are proper to start the
conversion process.
Note 5: The CS input is assumed to bracket the WR strobe input so that timing is dependent on the WR pulse width. An arbitrarily wide
pulse width will hold the converter in a reset mode and the start'of conversion is initiated by the low to high transition of theWA' pulse(see
Timing Diagrams).
Note 6: ClK IN (pin 4) is the input of a Schmitt trigger circuit and is therefore specified separately.
Note 7: None of these AIDs requires a zero-adjust. However, if an all zero code is desired for an analog input'other than O.OV, or if a narrow
• full·scale span exists (for example: 0.5V to 4.0V full·scale) the V,N (_) input can be adjusted to achieve this. See Zero Error below.

4-6

.D~D[6

ADC0801-ADC0804
TYPICAL PERFORMANCE CHARACTERISTICS

~

1.8

- 55°C" TA "

C!l

~
is

""

1/

1.6

500

+ 125°C

1.7

>

:1o

Delay From Failing Edge of
RD to Output Data Valid
vs load CapaCitance

logic Input Threshold Voltage
vs Supply Voltage

400
iii

~
::t:
....

!511.
l!i

S:!
C!l

9

1.5

./

S

~ 300
....
w

::t:

~

C

200
1.4

100

1.3
4.75
5.00
5.25
4.50
5.50
V+ -SUPPLY VOLTAGE (V)

o

200

ClK IN Schmitt Trip levels
vs Supply Voltage
~ 3.5
w

1

;:!

I

C!l

....

3.1

~

c 2.7
....
o
::t:

[3

Vr+

.....

1000

t-

l!i

'"~

f-

Vr-

~~I~~~?\

I

1.5
4.50

4.75
5.00
5.25
5.50
V+ -SUPPLY VOLTAGE (V)

Ellect of Unadjusted
011 set Error
16

iii

III


LL

V+ -4.5V

'f-

14 ~



11.

....
::>

0

'"

_

1.6

!Z

1.5

g

fCLK = 640kHz
v l+ I=~.~V

w

.,...

::>

ISOURCE



~

100 '---'-..J....Ju..J..LW---'u.......L...J.l.......J.II
10
100
1000
CLOCK CAPACITOR (pF)

1

Full·Scale Error vs fCLK

4

,

\

\

1.9

:::!.
a:
0
a:
a:
w
w
....

1000

R = 50k M1fttt1I\--t\-t++t+1tl

2.3

a:

::t:

800

~~!t!~~~~~1
~
\. R 10k

+ 125°C

- 55°C" TA "

600

fCLK vs Clock Capacitor

~

....

400

LOAD CAPACITANCE (pF)

~

75 100 125

TA-AMBIENTTEMPERATURE(OC)

1.1

1.0
-50 -25 0

V+

=~.civ

=4.~V

25

50

75 100 125

TA-AMBIENT TEMPERATURE (OC)

4·7

II

ADC0801-ADcoa04
3·STATE TEST CIRCUITS AND WAVEFORMS
10h'

10h

CL = 10pF

\

gf
v+

V+

RD

DATA
OUTPUTS

O~:: ----=CI-::;,h

~

2.4V;---t'".h:=-Ril

ok

Ril CS
_

GND---·~--·

tr =20ns

\

v+

..

":" ":" T

O.8V

DATA
OUTPUT
DATA
OUTPUTS

Cl

V+~

I

VOI~
tr=20ns

TIMING DIAGRAMS
Slarl Conversion

~"""~:,

~ t:,.1

"BUSY"

1
STATUS OF THE
CONVERTER _ _ _ _ _ _ _ _ _ _ _I~.~-~-----'~'N~O~T~B~U~S~Y'J'

- - - 1 TO 8 x 1/fClK

--~I __·~INTERNAL Tc --~

DATA IS VALID IN
OUTPUT LATCHES

(LAST DATA WAS READ)

\-I~ED
~N~~'!,OT.
-1/2tClK

OUIPUI Enable and ResellNTR

DATA
OUTPUTS-- -

-

-

--

Nole: All timing is measured from the 50% voltage points.

Ioh

.D~DIb

ADC0801-ADC0804
UNDERSTANDING AID ERROR SPECS
A perfect AID transfer characteristic (staircase waveform) is
shown in Figure 1a. The horizontal scale is analog input
voltage and the particular pOints labeled are in steps of 1 LSB
(19.53mV with 2.5V tied to the VREFI2 pi n). The digital output
codes which correspond to these inputs are shown as D -1,
D, and D + 1. For the perfect AID, not only will center·value
(A -1, A, A + 1, ...) analog inputs produce the correct output
digital codes, but also each riser (the transitions between ad·
jacent output codes) will be located ±112 LSB away from
each center-value. As shown, the risers are ideal and have no
width. Correct digital output codes will be provided for a
range of analog input voltages which extend ± 112 LSB from
the ideal center·values. Each tread (the rangepf analog input
voltage which provides the same digital output code) is
therefore 1 LSB wide.

In other words, if we apply an analog input equal to the
center·value ± 114 LSB, the AID will produce the correct
digital code. The maximum range of the position of the code
transition is indicated by the horizontal arrow and it is
guaranteed to be no more than 112 LSB.
The error curve of Figure 1c shows the worst case transfer
function for the ADC0802. Here the specification guarantees
that if we apply an analog input equal to the LSB analog
voltage center·value, the AID will produce the correct digital
code.

Figure 1b shows the worst case transfer function for the
ADC0801. All center-valued inputs are guaranteed to produce
the correct output codes and the adjacent risers are guaranteed to be no closer to the center·value points than ± 114 LSB.

Next to each transfer function is shown the corresponding er·
ror plot. Notice that the error includes the quantization uncer·
tainty of the AID. For example, the error at point 1 of Figure 1a
is + 112 LSB because the digital code appeared 112 LSB in ad·
vance of the center·value of the tread. The error plots always
have a constant negative slope and the abrupt upside steps
are always 1 LSB in magnitude, unless the device has missing codes.

Transfer Function

Error Plot
+ 1 LSB 1 - - - - - - +112 LSB

0+1

a:
oa:
a:
w

S'""'i6
I

,I
3i4
I
I

o

,
,

0-1

_3

1--++--l-"H-'<-l---1-,--_L _J ____

I

-1/2 LSB

,

4

,I
A-1

A

,

r

QUANT.

J

ERROR

6

,
,

- 1 LSB '--_...l...._L----L_..A-1
A A+1
ANALOG INPUT (VIN)

A+1

ANALOG INPUT IV'N)

a) Accuracy = ± 0 LSB; A Perfect AID
Transfer Function

Error Plot
+1 LSB

1----------

+ 314 LSB
+1'2 LSB
0+1

a:
oa:

ffi

o

-112 LSB

0-1

- 3/4 LSB
-1 LSB '--_...L.._'---'-_,-

A-1

A

A-1

A+1

ANALOG INPUT (VIN)

A

A+1

ANALOG INPUT(VIN)

b) Accuracy = ± 1/4 LSB

Transfer Function

Error Plot
+ 1 LSB 1 - - - - - - - , - - - -

0+1

'-.~ -1 ::::;

a:

oa:

o

ffi

1----+-\--+-+-'7,

4 -1- --._-

0-1

,

-1 LSB
A-1

A

I
'--_..L_~--l.

A-1

A+1

ANALOG INPUT IV'N)

c) Accuracy = ± 1/2 LSB

Figure 1. Clarifying the Error Specs of an AID Converter

4-9

A

__

A+1

ANALOG INPUT IV'N)

.D~DIL

ADC0801-ADC0804
FUNCTIONAL DESCRIPTION
A functional diagram of the ADC0801 series of AID converters is shown in Figure 2. All of the package pinouts are
shown and the major logic control paths are drawn in heavierweight lines. The device operates on the successive approximation principle (see A016 and A020 for a more detailed
description of this principle). Analog switches are closed sequentially by successive-approximation logic until the
analog differential input voltage [V IN(+)- VIN (_)] matches a
voltage derived from a tapped resistor string across the
reference voltage. The most significant bit is tested first and
after 8 comparisons (64 clock cycles), an 8-bit binary code
(11111111 = full-scale) is transferred to an output latch.

the shift-register stages are reset, and the INTR output will be
set high. As long as the CS input and WR input remain low,
the AID will remain in a reset state. Conversion will start from
1 to 8 clock periods after at least one of these inputs makes a
low· to-high transition. After the requisite number of clock
pulses to complete the conversion, the INTR pin will make a
high-to-Iow transition. This can be used to interrupt a processor, or otherwise signal the availability of a new conversion. A RD operation (with CS low) will clear the INTR line
high again. The device may be operated in the free-running
mode by connecting INTR to the WR input with CS O. To ensure start-up under all possible conditions, an external WR
pulse is required during the first power·up cycle. A conversion-in-process can be interrupted by issuing a second start
command.

=

The normal operation proceeds as follows. On the high-tolow transition of the WRinput, the internal SAR latches and
RD

II

.-

2

READ

--

"1" = RESET SHIFT REGISTER
"0" = BUSY AND RESET STATE

CS 1
WRO..;:3------0

INPUT PROTECTION
FOR All lOGIC INPUTS

ClK R

INPUT

19

ClKA

G1

·~lKIN ~LK
GEN

_~ 4

~ f.:

~

ClK OSC

~

10
'J1GND

'-<>\
--I

ClK

CIRCUITS
BV=30V

RESET-

*
VIN(+)
VIN(-)

DFF1
Q

~------------------.'~
ClKB~

~

,

I~.--''---'-D''''

START
'" ~SLON

~

a·BIT
. SHIFT
REGISTER
..)--IFRESET="O"
RI~--1'RESET

I~

AGND

~
~:J

TO INTERNAL

I START FIF I

ClKS

.-____ _

0

V+ ~20
(VREF)

VR EFI2

RESET

SUCCESSIVE
lADDER
I~~~~~------~
APPROX
AND
REGISTER
DECODER
AND lATCH

•

9

DAC
VOUT

8
v+

1

,

1Css" ~-r~
Q
~--~~

-ClKA~

6~~~~+r--~ I
V

'~~ ~~

II+-+I+I+I+-

I~

3·STATE

""6 7'~"~ '~'~"~ 6'50

'--:""':D:-'
DFF2
Q

XFER

~G2

-SET

~

~

\ 11 12 13 14.15 16 17 18 I
-uEONV. COMPL.
DIGITAL OUTPUTS
3.STATE CONTROL
~
- a x 111
"1" = OUTPUT ENABLE '--_ _ _ _-'--_ _ _ _ _ _ _-'

II

Figure 2. Block Diagram of ADC0801-ADC0804

4-10

I

INTR FIF

I

ADC0801-ADC0804
Digital Details

The time interval between sampling V1N (+) and V1NH is 4'/2
clock periods. The maximum error voltage due to this slight
time difference between the input voltage samples is given
by:

The converter is started by having CS and WR simultaneously low. This sets the start flip-flop (F/F) and the resulting "1"
level resets the 8-bit shift register, resets the Interrupt (IN:rR)
F/F and inputs a "1" to the D flip-flop, DFF1, which is at the input end of the 8-bit shift register. Internal clock signals then
transfer this "1" to the Q output of DFF1. The AND gate, G1,
co.mbines this "1" output with a clock signal to provide a
reset signal to the start F/F.lf the set signal is no longer present (either WR or CS is a "1"), the start F/F is reset and the
8-bit shift register then can have the "1" clocked in, which
starts the conversion process. If the set signal were to still be
present, this reset pulse would have no effect (both outputs
of the start F/F would be at a "1" level) and the 8-bit shift
register would continue to be held in the reset mode. This
allows for asynchronous or wide CS and WR signals.

t.Ve(MAX)=(V p) (21rfem)

(~),
fCLK

where:
t.Ve is the error voltage due to sampling delay
Vp is the peak value of the common-mode voltage
fern is the common-mode frequency
For example, with a 60Hz common-mode frequency, fern' and
a 640kHz AID clock, f CLK, keeping this error to 1/4 LSB
(-5mV) would allow a common-mode voltage, Vp, given by:

After the "1" is clocked through the 8-bit shift register(which
completes the SAR operation) it appears as the input to
DFF2. As soon as this "1" is output from the shift register, the
AN D gate, G2, causes the new digital word to transfer to the
3-state output latches. When DFF2 is subsequently clocked,
the Q output makes a high-to-Iow transition which causes
the INTR F/F to set. An inverting buffer then supplies the INTR
output signal.

Vp= [t.Ve(MAX)(fclIJl
(21rfem) (4.5)
or
Vp

When data is to be read, the combination of both CS and RD
being low will cause the INTR F/F to be reset and the 3-state
output latches will be enabled to provide the 8-bit digital
outputs.

Digital Control Inputs
The digital control inputs (CS, RD, and WR) meet standard
T2L logic voltage levels. These signals are essentially
equivalent to the standard AID Start and Output Enable control Signals, and are active low to allow an easy interface to
microprocessor control busses. For non-microprocessor
based applications, the CS input (pin 1) can be grounded and
the standard AID Start function obtained by an active low
pulse at the WR input (pin 3). The Output Enable function is
achieved by an active low pulse at the RD input (pin 2).

Analog Operation
The analog comparisons are performed by a capacitive
charge summing circuit. Three capacitors (with precise
ratioed values) share a common node with the input to an
auto-zeroed comparator. The input capaCitor is switched between V1N(+) and V1N(_), while two ratioed reference capacitors are switched between taps on the reference voltage
divider string. The net charge corresponds to the weighted
difference between the input and the current total value set
by the successive approximation register. A correction is
made to offset the comparison by 1/2 LSB (see Figure 1a).

= (5 x 10 -3) (640 x 103 ) '" 1.9V
(6.28) (60) (4.5)

The allowed range of analog input voltages usually places
more severe restrictions on input common-mode voltage
levels than this.
An analog input voltage with a reduced span and a relatively
large zero offset can be easily handled by making use of the
differential input (see Reference Voltage Span Adjust).

Analog Input Current
The internal switching action causes displacement currents
to flow at the analog inputs. The voltage on the on-chip
capacitance to ground is switched through the analog differential input voltage, resulting in proportional currents
entering the V1N(+) input and leaving the V1N (_) input. These
current transients occur at the leading edge of the internal
clocks. They rapidly decay and do not inherently cause errors
as the on-chip comparator is strobed at the end of the clock
period.

Input Bypass CapaCitors
Bypass capaCitors at the inputs will average these charges
and cause a DC current to flow through the output resistances of the analog signal sources. This charge pumping action is worse for continuous conversions with the V1N (+) input
voltage at full-scale. For a 640kHz clock frequency with the
V1N (+) input at 5V, this DC cur(ent is at a maximum of approximately 5p.A. Therefore, bypass capaCitors should not be
used at the analog inputs or the VREFI2 pin for high resistance
sources (> 1kO). If input bypass capacitors are necessary for
noise filtering and high source resistance is desirable to
minimize capacitor size, the effects of the voltage drop
across this input resistance, due to the average value of the
input current, can be compensated by a full-scale adjustment
while the given source resistor and input bypass capacitor
are both in place. This is possible because the average value
of the input current is a precise linear function of the differential input voltage at a constant conversion rate.

Analog Differential Voltage Inputs and
Common-Mode Rejection
This AID gains considerable applications flexibility from the
analog differential voltage input. The V1N (_) input (pin 7) can
be used to automatically subtract a fixed voltage value from
the input reading (tare correction). This is also useful in
4mA-20mA current loop conversion. In addition, commonmode noise can be reduced by use of the differential input.

4-11

4

.D~DIl

ADC0801-ADC0804
Input Source Resistance
Large values. of source resistance where an input bypass
capacitor is not used, will not cause errors since the input
currents settle out prior to the comparison time. If a low-pass
filter is required in the system, use a low-value series resistor
(:51kn) for a passive RC section or add an opamp RC active
low-pass filter. For low-source-resistance applications,
(:5)kn), a O.1I'F bypass capacitor at the inputs will minimize
EMI due to the series lead inductance of a long wire. A 100n
series resistor can be used to isolate this capacitor (both the
Rand C are placed outside the feedback loop) from the output of an op amp, if used.

Stray Pickup
The leads to the analog inputs (pins 6 and 7) should be kept as
short as possible to minimize stray signal pickup (EM I). Both
EMI and undesired digital-clock coupling to these inputs can
cause system errors. The source resistance for these inputs
should, in general, be kept below 5kn. Largervalues of source
resistance can cause undesired signal pickup. Input bypass
capacitors, placed from the analog inputs to ground, will
eliminate this pickup but can create analog scale errors as
these capacitors will average the transient input sWitc.hing
currents of the AID (see Analog Input Current). This scale er,ror depends on both a large source resistance and the use of
an input bypass capacitor. This error can be compensated by
a full-scale adjustment of the AID (see Full-Scale Adjustment) with the source resistance and input bypass capacitor
in place, and the deSired conversion rate.

allows for a pseudo-ratiometric voltage reference using, for
the V + supply, a 5V reference voltage. Alternatively, a voltage
less than 2.5V can be applied to the VREF/2 input. The internal
gain to the VREF/2 input is 2 to allow this factor of 2 reduction
in the reference voltage.
Such an adjusted reference voltage can accommodate a
reduced span or dynamic voltage range of the analog input
voltage. If the analog input voltage were to range from O.5V to
3.5V, instead of OV to 5V, the span would be 3V. With O.5V applied to the VIN (_) pin to absorb the offset, the reference
voltage can be made equal to 1/2 of the 3V span or 1.5V. The
AID now will encode the VIN (+) signal from O.5V to 3.5V with
the O.5V input corresponding to zero and the 3.5V input corresponding to full-scale. The full 8 bits of resolution are
therefore applied over this reduced analog input voltage
range. The requisite connections are shown in Figure 4. For
expanded scale inputs, the circu.its of Figures 5 and 6 can be
used.
VREF
(5V)

lI.
~..

TO

>-.....VVIrl~VREF/2
FS>"'~_-I

ADJ.

TO

>"'f-+--::Z;;:E=RO=S-;:H:;IF;;:T~V;;:O:;-LT=A;-;G:;;E:----"" VIN( -)

Reference Voltage Span Adjust
For maximum application flexibility, these AIDs have been
designed to accommodate a 5V, 2.5V or an adjusted voltage
reference. ThiS has been achieved in the design of the IC as
shown in Figure 3.

Figure 4. Olfsettingthe Zero of the ADC0801 and
Performing an Input Range (Span) Adjustment

Notice that the reference voltage for the IC is either 1/2 of the
voltage which is applied to the V+ supply pin, or is equal to
the voltage which is externally forced at the VREF/2 pin. This

,

V+ (VREF)
VIN
:t10V

2R
6 VIN(+)

~~}R

II DECODE

~}-

.l

7

J

9

V+

~+

ADC0801ADC0804

2R

R
VREF/2

......,

R

20

5V
(VREF)

~

f10

VIN(-)

~

DIGITAL
CIRCUITS

Figure 5. Handling ±10V Analog Input Range

-1

5V

ANALOG
CIRCUITS

,..--...,------.,-0 (VREF)

.1

R
VIN o--""Rf\r....._6,VIN(+)
:t5V

V+ 20

ADC0801ADC0804
VIN(-)

AGND 8

*

DGND 10

n'7

Figure 6. Handling ±5V Analog Input Range

Figure 3. The VREFERENCE Design on the IC

4-12

ADC0801-ADC0804
Reference Accuracy Requirements

Full·Scale Adjust

The converter can be operated in a pseudo-ratiometric mode
or an absolute mode. In ratiometric converter applications,
the magnitude of the reference voltage is a factor in both the
output of the source transducer and the output of the AID
converter and therefore cancels out in the final digital output
code. In absolute conversion applications, both the initial
value and the temperature stability of the reference voltage
are important accuracy factors in the operation of the AID
converter. ForV REF/2 voltages of 2.5V nominal value, initial errors of ± 10mV will cause conversion errors of ± 1 lSB due to
the gain of 2 of the VRE~2 input. In reduced span appli'cations, the initial value and the stability of the VREF/2 input
voltage become even more important. For example, if the
span is reduced to 2.5V, the analog input lSB voltage value is
correspondingly reduced from 20mV (5V span) to 10mV and
1 lSB at the V REF/2 input becomes 5mV. As can be seen, this
reduces the allowed initial tolerance of the reference voltage
and requires correspondingly less absolute change with
temperature variations. Note that spans smaller than 2.5V
place even tighter requirements on the initial accuracy and
stability of the reference source.

The full-scale adjustment can be made by applying adifferential input voltage which is 1'12 lSB down from the desired
analog fUll-scale voltage range and then adjusting the
magnitude of the VRE~2 input (pin 9) for a digital output code
which is just changing from 11111110 to 11111111. When offsetting the zero and using a span-adjusted VREF/2 voltage,
the full-scale adjustment is made by inputting VM1N to the
V1N (_) Input of the AID and applying a voltage to the V1N(+) input which is given by:
V1N(+) fs adl. = VMAX -1.5 [(VMAX-VMIN)] ,
256
where:
VMAX =the high end of the analog input range
and
VM1N = the low end (the offset zero) of the analog range.
(Both are ground referenced.)

Clocking Option
The clock for the AID can be derived from an external source
such as the CPU clock or an external RC can be added to provide self-clocking. The ClK IN (pin 4) makes use of a Schmitt
trigger as shown in Figure 7.

In general, the reference voltage will require an initial adjustment. Errors due to an improper value of reference voltage appear as full-scale errors in the AID transfer function. IC
voltage regulators may be used for references if the ambient
temperature changes are not excessive.

Zero Error
The zero of the AID does not require adjustment. If the
minimum analog input voltage value, V1N(MIN)' is not ground, a
zero offset can be done. The converter can be made to output
00000000 digital code forthis minimum input voltage by biasing the AID V1N(_) input at this V1N(MIN) value (see Applications
section). This utilizes the differential mode operation
of the AID.
The zero error of the AID converter relates to the location of
the first riser of the transfer function and can be measured by
grounding the V1N (_) input and applying a small magnitude
positive voltage to the V1N(+) input. Zero error is the difference between the actual DC input voltage which is
necessary to. just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal 1/2 lSB value
(1/2 lSB =9.BmV for VREF/2 =2.500V).

Heavy capacitive or DC loading of the ClocK R pin should be
avoided as this will disturb normal converter operation.
loads less than 50pF, such as driving up to 7 AID cO",Ierter
clock inputs from a single ClK R pin of 1 converter, are allowed. For larger clock line loading, a CMOS or low powerT 2l
buffer or PNP input logic should be used to minimize the
loading on the ClK R pin (do not use a standard T2 l buffer).

Restart During a Conversion
If the AID is restarted (CS and WR go low and return high) during a conversion, the converter is reset and a new conversion
is started. The output data latch is not updated if the conversion in progress is not completed. The data from the previous
conversion remain in this latch.

Continuous Conversions
In this application, the CS input is grounded and the WR input
is tied to the INTR output. This WR and INTR node should be
momentarily forced to logic low follOWing a power-up cycle to
insure circuit operation. See Figure B for details.

ADC0801ADC0804

ClK R
19

1

R

ClK t-------:-I>---i
IN

4

>(>-~~ClK

Figure 7. Self· Clocking the AID

4·13

'eLKS; 1.1 RC
Rs;10kO

II
~

ADC0801-ADC0804

...-....._ _ _ _------''\I10'';jk''v---------..,5V (ORVREF)*
...-.......-<>-1-1CS
'--0--:2:-1 RD

...--+__.....-C~3,WR

~_~~o--4~CLKIN
'--o-"';!,INTR
7 VIN(+)
o--<>---'8~VIN( -)

ADC0801ADC0804

DATA
OUTPUTS

",--~~o--9-1AGND

10 VREF/2
DGND

Figure 8. Free·Running Connection

Driving the Data Bus

Wiring and Hook·Up Precautions

This CMOS AID, like MOS microprocessors and memories,
will require a bus driver when the total capacitance of the
data bus gets large. Other circuitry, which is tied to the data
bus, will add to the total capacitive loading, even in 3-state
(high-impedance mode). Backplane bussing also .greatly
adds to the stray capacitance of the data bus.

Standard digital wire·wrap sockets are not satisfactory for
breadboarding this AID converter. Sockets on PC boards can
be used. All logic signal wires and leads should be grouped
and kept as far away as possible from the analog signal
leads. Exposed leads to the analog inputs can cause
undesired digital noise and hum pickup; therefore, shielded
leads may be necessary in many applications.

There are some alternatives available to the designer to handle this problem. Basically, the capacitive loading of the data
bus slows down the response time, even though DC specifications are still met. For systems operating with a relatively
slow CPU clock frequency, more time is available in which to
establish proper logic levels on the bus. and therefore higher
capacitive loads can be driven (see Typical Performance
Characteristics).
At higher CPU clock frequencies time can be extended for I/O
reads (and/or writes) by inserting wait states (8080) or using
.
clock-extending circuits (6800).
Finally, if time is short and capacitive loading is high, external bus drivers must be used. These can be 3-state buffers
(low power Schottky is recommended, such as the 74LS240
series) or special higher-drive-current products which are
designed as bus drivers. High-current bipolar bus drivers with
PNP inputs are recommended.

. Power Supplies
Noise spikes on the V+ supply line can cause conversion errors as the comparator will respond to this noise. A lowinductance tantalum filter capacitor should be used close to
the converter V+ pin and values of 11'F or greater are recommended.1f an unregulated voltage is available in the system,
a se'parate 5V voltage regulator for the converter (and other
analog circuitry) will greatly reduce digital noise on the V+
supply. An ICL7663 can be used to regulate such a supply
from an input as low as 5.2V.

A single-point analog ground should be used which is
separate from the logic ground pOints. The power supply
bypass capacitor and the self-clocking capacitor (if used)
should both be returned to digital ground. Any VRE~2 bypass
capacitors, analog input filter capacitors, or input signal
shielding should be returned to the analog ground point. A
test for proper grounding is to measure the zero error of the
AID converter. Zero errors in excess of 1/4 LSB can usually be
traced to improper board layout and wiring (see Zero Error for
measurement). Further information can be found in A018.

TESTING TH E AID CONVERTER
There are many degrees of complexity associated with
testing an AID converter. One of the simplest tests is to apply
a known analog input voltage to the converter and use LEDs
to display the resulting digital output code as shown in
Figure 9.
For ease of testing, the VREF/2 (pin 9) should be supplied with
2.560V and a V+ supply voltage of 5.12V should be used. This
provides an LSB value of 20mV.
If a full-scale adjustment is to be made, an analog input
voltage of 5.090V (5.120 -1 Yo LSB) should be applied to the
V1N(+) pin with the V1N (_) pin grounded. The value of the VREF/2
input voltage should be adjusted until the digital output code
is just changing from 1111 1110 to 1111 1111. This value of
VREF/2 should then be used for all the tests.

4-14

ADC0801-ADC0804
10kO
150pF

;J;
3

18

N.O.

"AA~

17

16

6

VIN(+)

ADC0801ADC0804

15
5V

O.l~F

14

2.560V
VREF/2

-=-

O.l~FJ

8

13

9

12

10

11
1.3kll
(8)

DGND

LEOs
(8)

Figure 9. Basic Tester for the AID

8·BIT
AID UNDER
TEST

R
,....---...., DIGITAL
OUTPUT
AID UNDER
TEST

R
ANALOG
INPUT

"B"

R

"A"

"c"
100R

':"

R
Figure 11. Basic "Digital" AID Tester

Figure 10. AID Tester with Analog Error Output. This circuit can be used
to generate "error plots" of Figure 1.

The digital-output LED display can be decoded by dividing
the 8 bits into 2 hex characters, one with the 4 mostsignificant bits (MS) and one with the 4 least-significant bits
(LS). The output is then interpreted as a sum of fractions
times the full-scale voltage:

For example, for an output LED display of 1011 0110, the MS
character is hex B (decimal 11) and the LS character is hex
(and decimal) 6, so

6)

11
VOUT= ( 16+ 256

MS
LS)
VOUT= ( 16+ 256
(5.12)V.

(5.12) = 3.64V.

Figures 10 and 11 show more sophisticated test circuits_
4-15

ADC0801-ADC0804
APPLICATIONS
Interfacing MCS·48, and MCS·80/85 Processors
This converter has been designed to directly interface with
an MCS·80/85 microprocessor or system. The 3·state output
capability of the AID eliminates the need for a peripheral in·
terface device, although address decoding is still required to
generate the appropriate CS for the converter. The AID can be
mapped into memory space (using standard memory·
address decoding forCS and the MEMR and MEMW strobes)
or it can be controlled as an I/O device by using the I/O Rand
I/O W strobes and decoding the address bits AO - A7 (or ad·

dress bitsAB - A15, since they will contain the same8·bit ad·
dress information) to obtain the CS input. Using the I/O space
provides 256 additional addresses and may allow a simpler
S·bit address decoder, but the data can only be input to the ac·
cumulator. To make use of the additional memory reference
instructions, the AID should be mapped into. memory space.
See A020 for more discussion of memory·mapped vs I/O·
mapped interfaces. An example of an AID in I/O space is
shown in Figure 12.

INT(14)

v
...

I/O WR(27)'

110 RD (25)'

10k

1

2-

?

~
5
6

.i

ANALOG
INPUTS

-

ti
7

150
1-.....

P

IT -

9

V+
19
ClK R
18
(lSB) DBa
17
DBl
16
DB2
ADC080115
ADC0804
DB3
14
DB4
13
DBs
12
DB6
11
(MSB) DB7

VIN(+)
VIN(-)
AGND

~

VREF/2
.10 DGND

th
I

Ts
~ T4
T3
r - T2
~ Tl
~ To

-

~101' F
DBa (13)'
DBl (16)'
DB2 (11)'
DB3 (9)'
DB4 (5)*
DBs (18)'
DB6 (20)*
DB7 (7)'

5V

J
~

~5V

'-/

CS
RD
WR
ClKIN
INTR

OUT

Y
T
v+

8131
BUS
COMPARATOR

Bs
B4
B3
B2
Bl
Ba

1

1

th
*Note: Pin numbers for 8228 system controller: others are 8080A

Figure 12. ADC0801 to 8080A CPU Interlace

4·16

AD15 (36)
AD14 (39)
AD13 (38)
AD12 (37)
ADll (40)
AD10 (1)

ADC0801-ADC0804
The standard control-bus signals of the 8080 (CS, RD and
WR) can be directly wired to the digital control inputs of the
AID, since the bus timing requirements, to allow both starting
the converter, and outputting the data onto the data bus, are
met. A bus driver should be used for larger microprocessor
systems where the data bus leaves the PC board andlor must
drive capacitive loads larger than 100pF.
It is useful to note that in systems where the AID converter is
1 of 8 or fewer I/O-mapped devices, no address-decoding circuitry is necessary. Each of the 8 address bits (AO to A7) can
be directly used as CS inputs, one for each I/O device.

Interfacing the Z·80 and 8085
The Z-80 and 8085 control busses are slightly different from
that of the 8080. General RD and WR strobes are provided and
separate memory request, MREO, and I/O request, lORa,
signals have to be combined with the generalized strobes to
provide the appropriate signals. An advantage of operating
the AID in I/O space with the Z-80 is that the CPU will
automatically insert one wait state (the RD and WR strobes
are extended one clock period) to allow more time for the I/O
devices to respond. Logic to map the AID in I/O space is
shown in Figure 13. By using MREQ in place of i5'RQ, a
memory-mapped configuration results.
Additional I/O advantages exist as software DMA routines
are available and use can be made of the output data transfer
which exists on the upper 8 address lines (A8 to A15) during
I/O input instructions. For example, MUX channel selection
for the AID can be accomplished with this operating mode.
The 8085 also provides a generalized RD and WR strobe, with
an 101M line to distinguish I/O and memory requests. The circuit of Figure 13 can again be used, with 101M in place of
lORa for a memory-mapped interface, and an extra inverter
(or the logic equivalent) to provide iO/M for an I/O-mapped
connection.

Interfacing 6800 Microprocessor Derivatives
(6502, etc.)
The control bus for the 6800 microprocessor derivatives does
not u,se the AD and WR strobe signals. Instead it employs a
single RiW line and additional timing, if needed, can be derived from theq,2 clock. All I/O devices are memory-mapped
in the 6800 system, and a special signal, VMA, indicates that
the current address is valid. Figure 14 shows an interface
schematic where the AID is memory-mapped in the 6800
system. For simpliCity, the CS decoding is shown using 1/2
DM8092. Note that in many 6800 systems, an already decoded 4/5 line is brought out to the common bus at pin 21. This
can be tied directly to the CS pin of the AID, provided that no
other devices are addressed at HEX ADDR: 4XXX or 5XXX.
In Figure 15 the ADC0801 series is interfaced to the MC6800
microprocessor through (the arbitrarily chosen) Port B of the
MC6820 or MC6821 Peripheral Interface Adapter (PIA). Here
the CS pin of the AID is grounded since the PIA is already
memory-mapped in the MC6800 system and no CS decoding
is necessary. Also notice that the AID output data lines are connected to the microprocessor bus under program control
through the PIA and therefore the AID RD pin can be
grounded.

APPLICATION NOTES
Some applications bulletins that may ,be found useful are
Iisted here:
A016 "Selecting AID Converters," by Dave Fullagar.
A018 "Do's and Dont's of Applying AID Converters," by
Peter Bradshaw and Skip Osgood.
A020 "A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing," by Ed Sliger.
A030 "The ICL7104-A Binary Output AID Converter for
Microprocessors," by Peter Bradshaw.
R005 "Interfacing Data Converters & Microprocessors,"
by Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

WR3

ADC0801ADC0804

WR~--OI._~

74C32
Figure 13. Mapping the AID as an I/O device lor use with the Z-80 CPU

4-17

4

ADC0801·-ADC0804
IRQ (4)*[D)**

.A

RlW (34) (6)

10k

...

~101'F

'-./

-

1

'"

CS·

V+ 20

"19-

~ RD
WR
~
4

eLKIN

5

INTR

6

ANALOG "
INPUTS

~=~
-o-~
10

T-

[ABC]

5V(8) 123

Do (33) [31)
Dl (32) (29)

DB2 16

ADC0801ADC0804

D2 (31) [K)

DB3 15

D3 (30) [H)

VIN(-)

DB4 14

D4 (29) (32)

AGND

DB5 13
DB 12
6 11
(MSB) DB7

Ds (28) [30)

VIN(+)

7

150pF/

CLK R .,--(LSB) DBo 18
DBl 17

VREF/2
DGND

De (27) ilJ
D7 (26)

iJi

n7 -:.:
1

A12 (22) [34]

2

.r- 3
liz D~~ 4

A13 (23)[N)

6

A14 (24)(M)

"

A15 (25) (33)

5

VMA (5) (F)

* Note 1: Numbers in parentheses refer to MC6800 CPU pinout.
*'Note 2: Numbers or letters in brackets refer to standard MC6800 system common bus code.
Figure 14. ADC0801 to MC6800 CPU Interface

18
19

CBl
CB2

10k
......

"'''''''

1
2

~ ~
4
5
6
ANALOG
INPUTS "

7

-

8

150pF - -

T

~~~

9

'-./

CS

RD

V+
CLKR

WR

(LSB) DBo

CLKIN
INTR
VIN(+)
VIN(-)
AGND

<>fa DGND

VREF/2

DB1
ADC0801ADC0804

MC6820
(MCS6520)

~5V
19
18

10

17

11

16

12

15

13

14

14

13
DB5
12
DBs
11
(MSB) DB7

15

DB2
DB3
DB4

Figure 15. ADC0801 to MC6820 PIA Interface

4·18

16
17

PBo
PB1
PB2
PB3
PB4
PBs
PBs
PB7

PIA

ADC0801-ADC0804
CHIP TOPOGRAPHY

1--------

0.093In

(2.36) mm

--------_1

DBo (LSB)

DBl
IliN(+)

DB2

0.101 in
(2.Sn mm

IliN(-)

DB3
AGND

DB4

4·19

I

ICL7106/7107
31f2-Digit Single Chip
AID Converter
FEATURES

GENERAL DESCRIPTION

• Guaranteed zero reading for o volts input on aU
scales.
• True polarity at zero for precise nuU detection.
• 1 pA typical input current.
• True differential input and reference.
• Direct display drive - no external components
required. - LCD ICL7106
- LED ICL7107
• Low noise - less than 15/lV pop.
• On-chip clock and reference.
• Low power dissipation - typically less than 10mW.
• No additional active circuits required.

0°

The Intersi! ICL7106 and 7107 are high performance, low
power 3%-digit AID converters containing all the necessary
active devices on a single CMOS I.C. Included are sevensegment decoders, display drivers, reference, and a clock_
The 7106 is designed to interface with a liquid crystal display
(LCD) and inCludes a backplane drive; the 7107 will directly
drive an instrument-size light emitting diode (LED) display_
The 7106 and 7107 bring together an unprecedented
combination of high accuracy, versatility, and true economy.
High accuracy like a\Jto-zero to less than 10/,V. zero drift of
less than 1/,V/oC, input bias current of 10 pA max., and rollover error of lesstnan ohe count. The versatility of true differential input and reference is useful in all systems, but gives
the designer an uncommon advantage when measuring load
cells, strain gauges and other bridge-type transducers. And
finally the true .economy of single power supply operation
• (7106), enabling. a high performance panel meter to be built
with the addition of only 7 passive components and a display.

E.a, ..lIoo Kit ...IIa.le.

+'N -

IN

+ ,.-------~--_+__t__1I!;1 >--R,
24KJI

,

R;
1MII

,.

t.KJI

)

INTERSIl7106

~

:

1M!!

INTERSIL 7107

HHHHH HH1'1 "I H1'1 H1-11'1 • 1<11·1 ~II~

j cl

~DI'P""

_ .-

1 _'000
,

ICL7106 with Liquid Crystal Display

ICL7107 with LED Display

PIN CON FIGURA',:,T~IO;;,,;N~~-nt-.

ORDERING INFORMATION
Part
7106
7106
7106
7107
7107
7107
7106 Kit
7107 Kit

Package
Temp_ Range
40 pin ceramic DIP
O'C to + 70'C
40 pin plastic DIP
O'C to +70'C
40 pin CERDIP
O'C to + 70'C
40 pin CERDIP
O'C to + 70'C
40 pit] ceramic DIP
O'C to + 70'C
40 pin plastic DIP
O'C to + 70'C
Evaluation kits contain IC, display, circuit
board, passive components and hardware.

1 I, 1

Order Part #
ICL7106CDL
ICL7106CPL
ICL7106CJL
ICL7107CJL
ICL7107CDL
ICL7107CPL
ICL7106EV/Kit
ICL7107EV/Kit

iii"

!::

~

1

~;E2
C~S3

Bn: 4
A1 C 5

F~S6

;~~g~g~

38~OSC3
37 ~ TEST,
3.

::! REF I.,

352~EFLO

C 7 JC17106 (LCD) 34 ~~ te:~REF
~~ ~: ICL7107 (LED):: g;~;tmN
_ { C2 C 10
31
IN HI

--

G1

~
w

B~~

to

A~~
F~~

11
12
13

30 ~IN LO
29 B~/Z
28t;1BUFF

,.

25

_ ~:§~:
B~~

.;: (

~

-

F~~ 17

E3l: 18

:g~ ~~~

(1000)
(MINUS)

4·20

'-'

~~~~T

~G2 (TENS)

24t::C')'"
23BA3 g

~~ t::J ~~/cf'NO
(7106) (1101)

ICL11 06/1CL71 07
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
ICL7106, V + to V - . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15V
ICL7107,V+toGND .......................... +6V
ICL7107,V-toGND .......................... -9V
Analog Input Voltage (either input) (Note 1). . . . . .. V + to VReference Input Voltage (either input) .......... V + to VClock Input
, ICL7106 .................... , . . . . . . . . .. TEST to V +
ICL7107 ............................... GND to V +

Power Dissipation (Note 2)
Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . .. 1000mW
Plastic Package .......................... , 800mW
Operating Temperature . . . . . . . . . . . . . . . . .. O°C to + 70°C
Storage Temperature. . . . . . . . . . . . . . .. - 65·C to + 160·C
Lead Temperature (Soldering, 60 sec) ............. 300·C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of
the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

Nota 1: Input voltages may exceed the supply voltages provided the input current is limited to ±100~.
Nota 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

ELECTRICAL CHARACTERISTICS INote 3)
MIN

TYP

MAX

UNITS

-000.0

±OOO.O

+000.0

Digital Reading

VIN = VREF
VREF = 100mV

999

999/1000

1000

Digital Reading

Rollover Error IDifference in
reading for equal positive and
negative reading near Full Scale)

-VIN = +VIN '" 200.0mV

-1

±.2

+1

Counts

linearity (Max. deviation from
best straight line fitl

Full scale = 200mV
or full scale = 2.000V

-1

±.2

+1

Counts

Common Mode Rejection Ratio
(Note 4)

VCM = ±1 V, VIN = OV.
Full Scale = 200.0mV

50

p.V/v

Noise {Pk-Pk value not exceeded
95% of time)

VIN =OV
Full Scale = 200.0mV

15

p.V

CHARACTERISTICS

CONDITIONS

Zero Input Reading

VIN = O.OV
Full Scale = 200.0mV

Ratiometric Reading

Leakage Current

I Input

VIN = 0

Zero Reading Drift

VIN =0
0° < TA < 70°C

Scale Factor Temperature
Coefficient

VIN = 199.0mV
0° < TA < 70°C
(Ext. Ref. Oppm/oC)

V + Supply Current (Does not
include LED current for 7107)
V Supply Current (7107 only)

VIN = 0

Analog Common Voltage (With
respect to Pos. Supply)

25kfl between Common &
Pos. Supply

Temp. Coeff. of Analog Common
(With respect to Pos. Supply)

25kfl between Common &
Pos. Supply
V+ to V =9V

7106 ONLY
Pk-Pk Segment Drive Voltage,
Pk-Pk Backplane Drive Voltage
(Note 5)
7107 ONLY
Segment Sinking Current
IExcept Pin 19)
(Pin 19 only)

V+ = 5.0V
Segment voltage = 3V

2.4

1

10

0.2

1

pA
p.V/oC

1

5

ppm/DC

0.8

1.8

mA

0.6

1.8

mA

2.8

3.2

V
ppm/DC

80

6

V

4

5

5

8.0

mA

10

16

mA

Note 3: Unless otherwise noted. specifications apply to both the 7106 and 7107 at TA = 25· C. fclock = 48kHz. 7106 is tested in the circuit of Figure
1.7107 is tested in the circuit of Figure 2.
Nota 4: Refer to "Differential Input" discussion.
Note 5: Back plane drive is in phase with segment drive for 'off' segment, 180· out of phase for 'on' segment. Frequency is 20 times conversion
rate. Average DC component is less than 50mV,

4-21

ICL7106/ICL7107
TEST CIRCUITS
IN

IN

+ -

+ -

Figure 1: 7106

Figure 2: 7107

DETAILED DESCRIPTION
ANALOG SECTION

I

Figure 3 shows the Block Diagram of the Analog Sectioh for
the ICL7106 and 7107. Each measurement cycle is divided

into three phases. They are (1) auto·zero (A-Z), (2) signal inte·
grate (INT) and (3) de·integrate (DE).

CAEF

REF HI

CREF+

r-----1

3.

3.

,REF LO

35

33

: v+
I
I

1
I

10j.l8

I
I

C>-....---_TO DIGITAL SECTION

1 31

INHI~~-{~~---4--~r---~----~
I

INT

I

1
1

A/Z

I

'32

COMMON~~----~--~~~~--~

INPUT

I

INLO~'~30~~~____-4__~__________~~________________~
l________________________
iNT
L
_
y-

LOW

~-------------------------------------

Figure 3: Analog Section of 710617107

1. Auto-zero phase
During auto-zero three things happen. First, input high
and low are disconnected from the pins and internally
shorted to analog COMMON. Second, the reference
capacitor is charged to the reference voltage. Third, a
feedback loop is closed around the system to charge the
auto-zero capacitor CAZ to compensate for offset
voltages in the buffer amplifier, integrator, and
comparator. Since the comparator is included in the loop,
the A-Z accuracy is limited only by the noise of the
system. In any case, the offset referred to the input is less
than 10!'V.

IN LO for a fixed time. This differential voltage can be
within a wide common mode range; within one volt of
either supply. If, on the other hand, the input signal has
no return with respect to the converter power supply, IN
LO can be lied to analog COMMON to establish the
correct common-mode voltage. At the end of this phase,
the polarity of the integrated signal is determined.
3. De-Integrate phase
The final phase is de-integrate, or reference integrate.
Input low is internally connected to analog COMMON and
input high is connected across the previously charged
reference capacitor. Circuitry within the chip ensures
that the capacitor will be connected with the correct
polarity to cause the integrator output to return to zero.
The time required for the output to return to zero is
proportional to the input signal. Specifically the digital
reading displayed is 1000 (~I.

2. Signal Integrate phase
During signal integrate, the auto-zero loop is opened, the
internal short is removed, and the internal input high and
low are connected to the external pins. The converter
then integrates the differential voltage between IN HI and

4·22

ICL71 06/1CL7107
Differential Input

these problems are of course eliminated if an external
reference is used.

The input can accept differential voltages anywhere within
the common mode range of the input amplifier; or
specifically from 0.5 volts below the positive supply to 1.0
volt above the negative supply. In this range the system has a
CMRR of 86 dB typical. However, since the integrator also
swings with the common mode voltage, care must be
exercised to assure the integrator output does not saturate.
A worst case condition would be a large positive commonmode voltage with a near full-scale negative differential input
voltage. The negative input signal drives the integrator
pO,sitive when most of its swing has been used up by the
positive common mode voltage. For these critical applications the integrator swing can be reduced to less than the
recommended 2V full scale swing with little loss of accuracy.
The integrator output can swing within 0.3 volts of either
supply without loss of linearity. See A032 for a discussion
of the effects of stray capacitance.

The 7106, with its negligible dissipation, suffers from none
of these problems. In either case, an external reference can
easily be added, as shown in Fig. 4.
v+
v'

COMMON

(b)

(-)

Differential Reference

Figure 4: Using an External Reference

The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the
reference capacitor losing or gaining charge to stray
capacity on its nodes. If there is a large common mode
voltage, the reference capacitor can gain charge (increase
voltage) when called up to de-integrate a positive signal but
lose charge (decrease voltage) when called up to deintegrate
a negative input signal. This difference in reference for (+) or
(-) input voltage will give a roll-over error. However, by
selecting the reference capacitor large enough in
comparison to the stray capacitance, this error can be held to
less than 0,5 count for the worst case condition. (See
Component Value Selection.)

Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from .
analog COMMON, a common mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same point, thus removing the common mode voltage
from the converter.. The same holds true for the reference
voltage. If reference can be conveniently referenced to
analog COMMON, it should be since this removes the common mode voltage from the reference system.

Analog COMMON

Within the IC, analog COMMON is tied to an N channel FET
that can sink 30mA or more of current to hold the voltage 2.8
volts below the positive supply (when a load is trying to pull
the common line positive). However, there is only 10p.A of
source current, so COMMON may easily be tied to a more
negative voltage thus over-riding the internal reference.

This pin is included primarily to set the common mode
voltage for battery operation (7106) or for any system where
the input signals are floating with respect to the power
supply. The COMMON pin sets a voltage that is approximately
2.8 volts more negative than the positive supply. This is
selected to give a minimum end-of-life battery voltage of
about 6V. However, the analog COMMON has some of the
attributes of a reference voltage. When the total supply
voltage is large enough to cause the zener to regulate (>7V),
the COMMON voltage will have a low voltage coefficient
L001%1%),low output impedance ("'150), and a temperature
coefficient typically less than 80ppm/o C.

TEST
The TEST pin serves two functions. On the 7106 it is coupled
to the internally generated digital supply through a 5000
resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other presentation the user may want to include on the
LCD display. Figures 5 and 6 show such an application. No
more than a lmA load should be applied.

The limitations of the on-chip reference should also be
recognized, however. With the 7107, the internal heating
which results from the LED drivers can cause some
degradation in performance. Due to their higher thermal
resistance, plastic parts are poorer in this respect than
ceramic. The combination of reference Temperature
Coefficient (TC), internal chip dissipation, and package
thermal resistance can increase noise near full scale from 25
p.V to 80p.Vp-p. Also the linearity in going from a high
dissipation count such as 1000 (20 segments on) to a low
dissipation count such as 1111 (8 segments on) can suffer by
a count or more. Devices with a positive TC reference may
require several counts to pull out of an overload condition.
This is because overload is a low dissipation mode, with the
three least significant digits blanked. Similarly, units with a
negative TC may cycle between overload and a nonoverload count as the die alternately heats and cools. All

v+
1M!l

7106
INTERSIL

TO LCD
DECIMAL POINT

IT1750

~---o~~~i~LANE
Figure 5: Simple Inverter for Fixed Decimal Point

4-23

~

ICL7106/1CL7107
DIGITAL SECTION

y+

y'

BP •

~-D+l
D-+D-+-'

I

710G

DE'CIMAL [
POINT
SELECT

I

t
I

t

L

TOLeD
DeCIMAL
POINTS

I

:D+
I

L

I

C04030
L
__..J

L__

TEST

' -_ _ _ _ _- - - - 1 \GND

Figure 6: Exclusive 'OR' Gate for Decimal Point Drive

The second function is a "lamp test". When TEST is pulled
high (to v+) all segments will be turned on and the display
should read -1888. The TEST pin will sink about 10mA under
these conditions.

Caution: on the 7106, in the lamp test mode, the segments
have a constant DC voltage (no square-wave) and may burn
the LCD display if left in this mode for several minutes.

Figures 7 and 8 show the di'gital section for the 7106 and
7107, respectively. In the 7106, an internal digital ground is
generated from a 6 volt Zener diode and a large P channel
source· follower. This supply is made stiff to absorb the
relative large capacitive currents when the back plane (BP)
voltage is switched. The BP frequency is the clock frequency
divided by 800. For three readings/second this is a 60 Hz
square wave with a nominal amplitude of 5 volts. The
segments are driven at the same frequency and amplitude
and are in phase with BP when OFF, but out of phase when
ON.' In all cases negligible DC voltage exists across the
segments.
Figure 8 is the Digital Section of the 7107. It is identical to the
7106 exclilpt that the regulated supply and back plane drive
have been eliminated and the segment drive has been
increased from 2 to 8 mA, typical for instrument size
common anode LED displays. Since the 1000 output (pin 19)
must sink current from two LED segments, it has twice the
drive capability or 16mA.
In both devices, the polarity indication is "on" for negative
analog inputs. If IN LO andlN HI are reversed, this indication
can be reversed also, if desired.
.

DISPLAY FONT

O:.?3'-:S:51:3'3

---------------------------------"'.--c·--f-------·+l--!+1+~---~HH_II__I---·~~-I-H-tC

TVPICAL SEGMENT OUTPUT

--4-----~--_4----~~~~--------------~------_+--~~~TEST

asc 1

osc 2

Figure 7: Digital Section 7106

4-24

ICL7106/1CL7107
DISPLAY FONT

,.

0.:'::3 '- :56-::::9

"

,-,
,-,
,-, ,-,

- -

TYPICAL SEGMENT OUTPUT

37

TEST
I

500 II

I
21

I

DIGITAL

-+____~--~~~~.-_-_-_-_-_-_-_~_-_-_-_--_-_-_-_-_-_-_-_-_--_-_-_-_~_-_--_-_~~ GROUND

L -__

osc 1

csc 3

CSC 2

Figure 8: Digital Section 7107

System Timing

40kHz 12.5 readings/second) will reject both 50 and 60 Hz
lalso 400 and 440 Hz).

Figure 9 shows the clocking arrangement used in the 7106
and 7107. Three basic clocking arrangements can be used:

COMPONENT VALUE SELECTION

1. An ·external oscillator connected to pin 40.

1. Integrating Resistor

2. A crystal between pins 39 and 40.

Both the buffer amplifier and the integrator have a class A
output stage with lOOltA of quiescent current. They can
supply 20ltA of drive current with negligible non-linearity.
The integrating resistor should be large enough to remain
in this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 volt full scale, 470KO is
near optimum and similarly a 47KO for a 200.0 mV scale.

3. An R-C oscillator using all three pins.
I

7106/7107

I
I
I
I
I

I

I
I

TO

I
I

COUNTER I

I

I

I

I

I

I

I
L
_______ _

40

2·3M{l

---------

I

39

---------

~

________ J

2. Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up
will not saturate the integrator swing lapprox. 0.3 volt
from either supply). In the 7106 or the 7107, when the
analog COMMON is used as a reference, a nominal ±2
volt full scale integrator swing is fine. Forthe 7107 with ±5
volt supplies and analog COMMON tied to supply ground,
a ±3.5 to ±4 volt swing is nominal. For three readings/
second 148kHz clockl nominal values for CINT are 0.22ltF
and O.IOltF, respectively. Of course, if different oscillator
frequencies are used, these values should be changed in
inverse proportion to maintain the same output swing.

EXTERNAL
OSCILLATOR

TEST (7106)
or GND (7107)

Figure 9: Clock Circuits

The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate 11000
counts), reference de-integrate 10 to 2000 counts) and autozero 11000 to 3000 counts). For signals less than full scale,
auto-zero gets the unused portion of reference deintegrate.
This makes a complete measure cycle of 4,000 116,000 clock
pulses) independent of input voltage. For three readings/.
second, an oscillator frequency of 48kHz would be used.

An additional requirement of the integrating capacitor is
it have low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for
this application, polypropylene capacitors give
undetectable errors at reasonable cost.

To achieve maximum rejection of 60 Hz pickup, the signal
integrate cycle should be a multiple of 60 Hz. Oscillator
frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz,
40kHz, 33 % k Hz, etc. should be selected. For 50Hz
rejection, Oscillator frequencies of 200kHz, 100kHz,
66 2/3 kHz, 50kHz, 40kHz, etc .. would be suitable. Note that

3. Auto-Zero Capacitor
The size of the auto-zero capacitor has some influence on
the noise of the system. For 200 mVfuil scale where noise

4·25

ICL71 06/ICL71 07
and weighing systems with a variable tare are examples.
This offset reading can be conveniently generated by
connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage
between COMMON and IN LO.

is very important. a 0.47l'Fcapacitor is recommended. On
the 2 volt scale. a 0.047l'Fcapacitor increases the speed
of recovery from overload and is adequate for noise on
this scale.

4. Reference Capacitor

7. 7107· Power Supplies

A O.lI'F capacitor gives good results in most applications.
However. where a large common mode voltage exists (Le.
the REF LO pin is not at analog COMMON) anct a 200mV
scale is used. a larger value is required to prevent rollover error. Generally 1.0 I'F will hold the roll-over error to
0.5 count in this instance.

The 7107 is designed to work from ±5V supplies.
However. if a negative supply is not available. it can be
generated from the clock output with 2 diodes. 2
capacitors, and an inexpensive I.C. Figure 10 shows this
application. See ICL7660 data sheet for an alternative.

5. Oscillator Components
For all ranges of frequency a l OOKn resistor is
recommended and the capacitor is selected from the
equation f = ~. For 48kHz clock (3 readings/second). C
= 100pF.

6. Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus. for the 200.0mV and
2.000 volt scale. Vref should equal 100.0 mVand 1.000 volt.
respectively. However. in many applications where the
AID is connected to a transducer. there
exist a scale
factor other than unity between the input voltage and the
digital reading. For instance. in a weighing system. the
designer might like to have a full scale reading when the
voltage from the transducer is 0.682V. Instead of dividing
the input down to 200.0 mV. the designer should use the
input voltage directly and select VREF = .341V. Suitable
values for integrating resistor and capacitor would be
120Kn and 0.22I'F. This makes the system slightly
quieter and also avoids a divider network on the input.
The 7107 with ±5V supplies can accept input signals up
to ±4V. Another advantage of this sytem occurs when a
digital reading of zero is desired for VIN ¥ O. Temperature

will

Figure 10: Generating Negative Supply from +Sv
In fact. in selected applications no negative supply is
required. The conditions to use a single +5V supply are:
1. The input signal can be referenced to the center of the
common mode range of the converter.
2. The signal is les.s than ±.1.5 volts.
3. An external reference is used.

TYPICAL APPLICATIONS
The 7106 and 7107 may be used in a wide variety of
configurations. The circuits which follow show some of the

7106

possibilities. and serve to illustrate the exceptional versatility of these AID converters.

To pin 1
40

7107

To pin 1
40

OSCl

lOOK!!

100Ktl
OSC 2
osc 3 D - - - 1 I - - - '

Set YRH'" 100,OmY

TEST

0------./
1Kn

REF HI

10DpF

SetYREF'" 100.OinV

,/

n--"'----.

22KIl
1 Mil

47Kn

:

47KIl

9V

n-__----'0=.22,,""'F- - - - + - - - - < - 5 V

O.22pF

,,
,

--------- ----

TO BACK PLANE

------~

Figure 12: 7107 using the internal reference. Values shown are for
200.0 mV full scale, 3 readings per second. IN LO may be tied to
either COMMON for inputs floating with respect to supplies, orGND
for single ended inputs. (See discussion under Analog COMMON.)

Figure 11: 7106 using the internal reference. Values shown are for
200.0 mV full scale. 3 readings per second. floating supply voltage
(9V battery).

4·26

ICL7106/1CL7107
TYPICAL APPLICATIONS (Contd.)
7107

[]------~~~vv~~~V-~--Q'5V

6.8V

[]------~~------------_+__o~v

Figure 13:7107 with an external band-gap reference 11.2V type). IN
LO is tied to COMMON, thus establishing the correct common mode
voltage. If COMMON is 'not shorted to GND, the input voltage may
float with respect to the power supply and COMMON acts as a preregulator for the reference. If COMMON is shorted to GND, the input
is single ended Ireferred to supply ground) and the pre-regulator is
over-ridden.
7106/7107
'-./

Figure 14: 7107 with Zener diode reference. Since low T.C. zeners
have breakdown voltages - 6.8V, diode must be placed across the
total supply 110V). As in the case of Figure 12, IN LO may be tied to
either COMMON or GND.

To pin 1

TEST

REF HI
REF LO
C REF
C REF

~

'-./

lOOK!!

po.,..

24Kn
1MJl

:;:.Olj. REF IN
SEND 27
RUN/HOLD26
BUF OSC OUT 25
24kU
OSC SEl24 I--GND
OSC OUT 23
OSC IN 22 ~ 3.5795 MHz
MODE 21
TY CRYSTAL
20~

+

...

~b

r--';'~t:,: q,.-

+

y+

·R'NT = 20kn FOR 0.2Y REF
=200kU FOR 2.0V REF

(OUTLINE DWGS DL. JL. PL)

ORDERING INFORMATION
Part
7109
7109
7109
7109

Temp. Range
-SS'C to t125'C
-20'C to +8S'C
-20'C to t85'C
O'C to 70'C

40·Pin
40·Pin
40·Pin
40·Pin

Package
Ceramic DIP
Ceramic DIP
CERDIP
Plastic DIP

Order Number
ICL7109MDL
ICL7109IDL
ICL71091JL
ICL7109CPL

4·30

ICL7109
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (GND to v+) ...................................... +6.2V
Negative Supply Voltage (GND to V-I ....................................... -9V
Analog Input Voltage (Lo or Hi! (Note 1) ................................ V+ to VReference Input Voltage (Lo or Hi) (Note 1) ............................. V+ to VDigital Input Voltage
V+ + 0.3V
(Pins 2-27) (Note 2) ................................................. GND - 0.3V
Power Dissipation (Note 3)
Ceramic Package .............................................. 1W @ +B5°C
Plastic Package ............................................ 500mW @ +70°C
Operating Temperature
Ceramic Package (MOll ............................... -55°C S TA S +125°C
(lOll ................................. -25°C S TA S +B5°C
Plastic Package
(CPLI ................................... O°C S TA S +lO°C
Storage Temperature .................................... -55°C S TA S +125°C
Lead Temperature (soldering, 60 sec.) ................................... +300°C
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devices. This is a stress
rating only and functional operation of the devices at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TABLE I OPERATING CHARACTERISTICS
All parameters with V+ = +5V, VTest circuit as shown on page 1.

= -5V,

GNO

= OV, TA = 25°C,

unless otherwise indicated.

ANALOG SECTION

PARAMETER

SYMBOL

CONDITIONS

Zero Input Reading

VIN = O.OV
Full Scale = 409.6mW

Ratiometric Reading

VIN = VREF
VREF = 204.BmV

Non-Linearity (Max deviation
from best straight line fit)

Full Scale = 409.6mV to 4.096V
O\ler full operating temperature
range.
Full Scale = 409.6mV to 4.096V
Overfull operating temperature
range.

Roll-over Error (difference
in reading for equal pos. and
neg. inputs near full scale)
Common Mode Rejection Ratio

CMRR

Input Common Mode Range

VCMR

Noise (p-p value not
exceeded 9S% of time)
Leakage current at Input

en
IILK

MAX

UNITS

+00008

Octal
Reading

3777s

37778
40008

40008

Octal
Reading

-1

±.2

+1

Counts

-1

±.2

+1

Counts

Input Hi, Input Lo, Common

15

,

= OV

VIN

V+-1.0

V-+1.S

VIN = 0 All devices 25°C
ICL7109CPL O°C S TA S +loac
ICL710910C -2SoC S TA S +B5°C
ICL7109MDL -SsoC < TA S +125°C
VIN = 40B.9mV = > 7770s
reading
Ext. Ref. 0 ppm/oC

jJ.V/v

SO

VIN = OV
Full Scale - 409.6mV

Zero Reading Drift

V
jJ.V

1
20
100
2

10
100
250
5

0.2

1

pA
pA
pA
nA
jJ.V;oC

1

5

ppmrC

700

1500

jJ.A

700

1S00

jJ.A

-2.S

-3.2

,+

Supply Curr.ent V+ to V-

Isupp

Ref Out Voltage

VREF

Ref Out Temp. Coefficient
Input Common Mode Range

TYP
±OOOOs

VCM ±1V VIN = OV
Full Scale = 409.6mV

Scale Factor Temperature
Coefficient
Supply Current V+ to
GND

MIN
-{JOOOs

VIN = 0, Crystal Osc.
3.5SMHz test circuit
Pins 2-21, 25, 26, 27, 29, open
Referred to V+, 25kll
between V+ and REF OUT
25kll between V+ and REF OUT

VCM

IN HI, IN

La,

COMMON

4-31

-2.4

SO
V+ -0.5
to
V+ -1.0
V- +1.5
V- +1.0

V
ppmrC
V

'ICL7109
DIGITAL SECTION
PARAMETER
Output High Voltage

SYMBOL
VOH

Output Low Voltage

VOL

CONDITIONS
lOUT - 100}LA
Pins 2-16, 18, 19,20

MIN
3.5

lOUT = 1.6mA

Output Leakage Current

Pins 3-16 high impedance

Control I/O Pullup
Current

Pins 18, 19,20 VOUT = V+ -3V
MODE input at GND

Control I/O Loading

HBEN Pin 19 tBEN Pin 18

Input High Voltage

VIH

Pins 18-21, 26, 27
referred to GND

Input Low Voltage

Vil

Pins 18-21, 26, 27
referred to GND

TYP
4.3

MAX

0.2

0.4

V

±.01

±1

}LA

5

UNITS
V

}LA
50

2.5

pF
V

1

V

Input Pull-up Current

Pins 26, 27 VOUT = V+ -3V

5

}LA

Input Pull-up Current

Pins 17, 24 VOUT = V+ -3V

25

}LA

Input Pull-down Current

Pin 21

VOUT = GND +3V

Oscillator Output
Current

High
Low

OOH
OOl

VOUT = 2.5V
VOUT - 2.5V

Buffered Oscillator
Output Current

High
Low

BOOH
BOOl
tw

VOUT = 2.SV
VOUT - 2.SV

MODE Input Pulse Width

5

}LA

1
1.5

mA
mA

2
S

mA
mA
ns

SO

Nole 1:
Nole 2:

Input voltages may exceed the supply voltages provided the mput current IS limited to ±lOOI'A
Due to the SCR structure inherent in the process used to fabricate these devices, connecting any digital inputs or outputs to voltages
greater than V+ or less than GND may cause destructive device latch up. Forthis reason it is recommended that no inputs from sources
other than the same power supply be applied to the ICL7109 before its powersupply is established, and that in multiple supply systems
the supply to the ICL7109 be activated first.
Note 3: This limit refers to that of the package and will not be obtained during normal operation.
+5Y- 1 Y+
2 OSC CONTROL
GND-J: 3 GND
+5V- 4 RRD
5·12
RBR1·.

--

13 PE
14 FE
150E
+5Y- 18 SFD

SERiAL

20 RRI

SERiAL

25 TRO

IN!'UT

OUTPUT

y+ 40 r--+5Y
REF IN - 39
---GND
REF CAP" 38
EXTERNAL
REF CAP + 37 ~1"F
REFERENCE
REF IN + 36
+
1Mil
19 HBEN
IN HI 35
~ INPUT
IN LO 34 ~
GND
COM 33
3·8
INlJI.:1S",F
B9·BI2,POL,OR
INT32
AZ
AZ 31
9·18
.33
8
Bl·B8
BUF30
REF OUT 29 tRINT 20kll 0.2Y REF
+5Y- 17 TEST
Y-28 r~V
llLiE'1i
200k1l2Y REF
21 MODE
RUN/HOLD 28 r+5Y OR OPEN
20~
OSC sEL 24 t- GND
27 SEND
OSCOUT 23
OSC IN 2 2 1 1 ] 3.58 MHz
CRYSTAL
FOR LOWEST POWER CONSUMPTION,
ICL7109
TBA1 TaRI INPUTS SHOULD HAVE OOk I
PULLUP RESISTORS TO oS,
CMOS AID CONVERTER

TRC40 rOSC IN 17
EPE 39
CLS138 s+5Y
¢l'iS237
SBS38
PI 35 t- GND
CRL 34 t-+5Y
28·33
TBR,..
TRE 24 tORR 18
DR 19
TBRL 23
TBRE 22
MR 21 t-GND

IM6403
CMOS UART

GND- 1 GND
25 BUF OSC OUT
2 STATUS

-

-

It

, ,

Figure lA. Typical Connection Diagram UART Interface - To transmit latest r~sult, send any word to UART

+5Y

2
XTALI
1 TO

+5V
GND
+5Y

4 ·1iEftT

r44c0~YV-+r----------;REEiF~I~N~3i9~--------~~~--GND

~7G~E~T

555
8 iRT
GND

+5V
+5V
+5V
GND

7 EA

9 PSEN
11 ALE
25 PROG
28 VDD
39 TL
40 YCC
20 aND

g: ~ ~

I"F

~m~~~h

~i~I~M~I~1~~:++ INPUT

REF IN + 36
I :L~ ~: ~

aWli
+5V

:::

t------------'---------------------i28 RUN/H(i(!j
t-------------------------~----~2STATUS

t-------------~----------------~I.LBEN

t--------~------------__t19

12·19
DBO·DB7
ROl0

87_

HftN

COM 33 t-==~""""C",.~N~M
. INT 32 t:~~;:::!E~
AZ 31 tBUF 30 r--""""="'--JV'W--'
REF OUT 29
R,N' 20kll 0.2Y REF.
Y-28
2OOk1l2Y REF.
SEND 27
BUF OSC OUT, 25
OSC SEL 24
GND
OSC OUT 23 t-----::l
OSC IN 22
MODE 21

ICL7109
CMOS AID CONYERTER

Figure 1B: Typical Connection Diagram Parallel Interface With MCS·48 Microcomputer

4;32

ICL7109
TABLE 2 - Pin Assignment and Function Description
PIN
1
2

SYMBOL

GND
STATUS

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

POL
OR
B12
Bll
Bl0
89
88
87
B6
85
B4
B3
B2
81
TEST

18

LBEN

19

20

HBEN

CE/LOAD

DESCRIPTION
Digital Ground. OV. Ground return for all
digital logiC
Output High during integrate and deintegrate until data is latched.
Output Low when analog section is in
Auto-Zero configuration.
Polarity - H I for Positive Input.
Overrange - HI if Overranged.
Bit 12 IMos~S1!n~c~!J?r~_
Bit 11
All
81t 10
three
Bit 9
state
Bit 8
output
81t 7 HI ~ true
data
Bit 6
bits
Bit 5
Bit 4
81t 3
Bit 2
- - --:-.---:-81t 1 ILeast Significant Bltl
Input High - Normal Operation.
Input Low - Forces all bit outputs high.
Note: This Input is used for test purposes
only. Tie high if not used.
Low 8yte Enable - With Mode IPin 21110w.
and CE/LOAD IPIn 201 low. taking this pin
low activates low ord.er byte outputs 81-88.

PIN
21

22
23
24

25
26

27

- With Mode IPin 211 high. this pin servesas
a low byte flag output used In handshake
mode. See Figures 7. 8. 9.
High Byte Enable - With Mode IPIn 21110w.
and CE/LOAD IPIn 20) low. taking thiS pin
low activates high order byte outputs 89B12. POL. OR.

28
29
30
31
32
33

- With Mode IPln 211 high. thiS pin serves as
a high byte flag output used In handshake
mode. See Figures 7. 8. 9.
Chip Enable Load - With Mode IPIn 2111ow.
CEILOAD serves as a master output enable.
When high. BI-812. POL. OR outputs are
disabled.

34
35
36
37
38
39
40

- With Mode IPIn 211 high. thiS pin servesas
a load strobe used In handshake mode.
See Figures 7. 8. 9.

SYMBOL
MODE

DESCRIPTION
Input Low - Direct output mode where
CEILOAO (Pin 201. H8EN (Pin 191 and
L8EN (Pin 181 act as inputs directly
controlling byte outputs.
Input Pulsed High - Causes Immediate
entry into handshake mode and output of
data as in Figure 9.
Input High - Enables CEILOAD (Pin 201.
H8EN IPin 191. and 03EN (Pin 181 as ('utputs. handshake mode will be entered and
data output as In Figures 7 and 8 at converSion completion.
OSCillator Input
OSCIN
OSC OUT
Oscillator Output
Oscillator Select - Input high configures
OSC SEL
OSC IN. OSC OUT. 8UF OSC OUT as RC
oscillator - clock will be same phase and
duty cycle as BUF OSC OUT.
- Input low configures OSC IN. OSC OUT
for crystal oscillator - clock frequency will
be 1/58 of frequency at 8UF OSC OUT.
BUF OSC OUT Buffered Oscillator Output
RUN/HOLD
Input High - Conversions continuously
performed every 8192 clock pulses.
Input Low - Conversion in progress completed. converter will stop in Auto-Zero 7
counts before integrate.
SEND
Input - Used in handshake mode to indicate
ability of an external device to accept data.
Connect to + 5V if not used.
Analog Negative Supply - Nominally -5V
V
with respect to GND (Pin 11.
REF OUT
Reference Voltage Output - Nominally 2.8V
down from V' (Pin 401.
8UFFER
Buffer Amplifier Output
AUTO-ZERO
Auto-Zero Node - Inside foil of CAl
INTEGRATOR Integrator Output - Outside foil of C'NT
COMMON
Analog Common - System is Auto-Zeroed
to COMMON
Differential Input Low Side
INPUT La
Differential Input High Side
INPUT HI
Differential Reference Input Positive
REF IN'
Reference Capacitor POSitive
REF CAP'
REF CAP
Reference Capacitor Negative
REF IN
Differential Reference Input Negative
V'
Positive Supply Voltage - Nominally +5V
With respect 10 GND (Pin 11.

Note:.A11 digital levels are positive true.

DETAILED DESCRIPTION
Analog Section

the buffer amplifier, integrator, and comparator. Since
the comparator is included in the loop, the AZ accuracy
is limited only by the noise of the system. In any case, the
offset referred to the input is less than 10!'V.

Figure 2 shows the equivalent circuit of the Analog Section
of the ICL7109. When the RUN/FmI!5 input is left open or
con(lected to V+, the circuit will perform conversions at a rate
determined by the clock frequency (8192 clock periods per
cyclel. Each measurement cycle is divided into three phases
as shown in Figure 3. They are (1) Auto-Zero (AZ), (2) Signal
Integrate IINTI and (31 Deintegrate (DE).

2. Signal Integrate Phase
During Signal integrate the auto·zero loop is opened, the
internal short is removed and the internal input high and
low are connected to the external pins. The converter
then integrates the differential voltage between IN HI and
IN LO for a fixed time of 2048 clock periods. Note that
this differential voltage can be within the common mode
range of the inputs. At the end of this phase, the polarity
of the integrated signal is determined.

1. Auto·Zero Phase
During auto·zero three things happen. First, input high
and low are disconnected from their pins and internally
shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feed·
back loop is closed around the system to charge the autozero capacitor CAZ to compensate for offset voltages in

4·33

ICL7109
RJNT

CAEF

,-:-I

REF CAP

+

REF IN

+

REF IN-

BUFFER

I
I
I

INPUT HIGH

 portion of the conversion cycle (See Figure 3), In
this mode of operation, the conversion cycle will be
performed in 8192 clock periods, regardless of the resulting
value.
If RUN/HOLD goes low at any time during Deintegrate
(Phase III> after the zero crossing has occurred, the circuit
will immediately terminate Deintegrate and jump to AutoZero. This feature can be used to eliminate the. time spent in
Deintegrate after the zero-crossing. If RUN/HOLD stays or
goes low, the converter will ensure minimum Auto-Zero
time, and then wait in Auto-Zero until the RUN/HOLD input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the STaTuS output will
go high) seven clock periods after the high level is detected at
RUN/HOLD. See Figure 5 for details.

I

LOW ORDER
BYTE OUTPUTS-

BBBBBBBBBBBB

12 11 10 9

8

7

6

5

4

3

2

17

1

-----1
18

I LBEN

1--_--...+-1;;;9;-
-_+_+-____
LATCH

~ I--+-F';";;;='--L-~

im$mmmmmmm

STATUS
OUTPUT

STATUS OUTPUT __
UNCHANGED IN
UART MODE

~

POSITIVE TRANSITION CAUSES

~~~~ ~~~~Y~~6~ ~

I!m$m~mmmm!ii mm$m~mmmmm mm$.~
--+-+--------< >--+-t-----~ --+--1

INTERNAL UART
MODE oN~O""R:::M,--_--,

SEND~

INPUT

>--+-t----

l

/'
/

SEND

SEND
SENSED

/

___

TERMINATES
UART MODE

SENSED~

~

'1iij!lim_lli_i!_

-----'.~ i----f---rr---- I---t-i,. 1-_L
HIGH

~~~! - _________ .; 1-----i~

__

D_AT_A_VA_L_.;ID

LBEN-~-~-_u----

~-r~
'-------<

LOW~;;!

__________

~ ~-----------~ 1- _ _

. . '" DON'T CARE

- - - '" THREE-STATE HIGH IMPEDANCE

_1_ = THREE-STATE WITH PULLUP

Figure 9: Handshake Triggered By Mode

4-39

DATA VALID

II

ICL7109
internal clock high to low edge, the high order byte outputs
are disabled, and one-half internal clock later, the HBEN
output returns high. At the same time, the CE/LOAD and
LBEN outputs go low, and the low order byte outputs
become active. Similarly, when the CE/LOAD returns high at
the end of one clock period, the low order data is clocked into
the UART Transmitter Buffer Register, and TBREagain goes
low. When TBRE returns to a high it will be sensed on the
nexjJCL7109 internal clock high to low edge, disabling the
data outputs. One-half internal clock later, the handshake
mode will be cleared, and the CE/LOAD, HBEN, and LBEN
terminals return high and stay active (as long as MODE stays
high).
.

II

With the MODE input remaining high as in these examples,
the converter will output the results of every conversion
except those completed during a handshake operation. By
triggering the converter into handshake mode with a low to
high edge on the MODE input, handshake output sequences
may be performed on demand. Figure 9 shows a handshake
output sequence triggered by such an edge. In addition, the
SEND input is shown as being low when the converter enters
handshake mode. In this case, the whole output sequence is
controlled by the SEND input, and the sequence for the first
(high order) byte is similar to the sequence for the second
byte. This diagram also shows the' output sequence taking
longer than a conversion cycle. Note that the converter still
makes conversions, with the STATUS output and
RUN/HOLD input functioning normally. The only difference
is that new data: will not be latched when in handshake mode,
and is therefore lost.

v+-_---_CLOCK

24

-fc;;c
i
SEL
GND

osc
IN

o

OSC
OUT

BUFFERED

osc

OUT

CRYSTAL

Figure 11: Crystal Oscillator
oscillator will operate with most crystals in the 1 to 5MHz
range with no external components. Taking the OSCILLATOR
SELECT input low also inserts a fixed 758 divider circuit
between the BUFFERED OSCILLATOR OUTPUT and the
internal clock. Using an inexpensive 3.58MHz TV crystal, this
division ratio provides an integration time given by:
58
'
T = (2048 clock periods) X C.58MHZ) = 33.18ms
This time is very close to two 60Hz periods or 33.33ms. The
error is less than one percent, which will give better than
40dB 60Hz rejection. The converter will operate reliably at
conversion rates of up to 30 per second, which corresponds
to a clock frequency of 245.8kHz.
If at any time the oscillator is to be overdriven, the overdriving signal should be applied althe OSCILLATOR INPUT,
and the OSCILLATOR OUTPUT should be left open. The
internal clock will be of the same frequency, duty cycle, and
phase as the input signal when OSCILLATOR SELECT is left
open. When OSCILLATOR SELECT is at GND, the clock will
be a factor of 58 below the input frequency.

Oscillator
The ICL7109 is provided with a versatile three terminal
oscillatpr to generate the internal clock. The oscillator may
be overdriven, or may be operated as an RC or crystal
oscillator. The OSCILLATOR SELECT input changes the
internal configuration of the oscillator to optimize it for RC
or crystal operation.

When using the ICL7109with the IM6403 UART, it ispossible
to use one 3.58MHz crystal for both devices. The BUFFERED
OSCILLATOR OUTPUT of the ICL7109 may be used to drive
the OSCILLATOR INPUT of the UART, saving the need fora
second crystal. However, the BUFFERED OSCILLATOR
OUTPUT does not have a great deal of drive, and when driving more than one slave device, external buffering should be
used.
Test Input
When the TEST input is taken to a level halfway between V+
and GND, ,the counter output latches are enabled, allowing
the counter contents to be examined anytime.
When the TEST input is connected to GND, the counter
outputs are all forced into the high state, and the internal
clock is disable,(j. When the input returns to the 1/2 (V+ -GND)
voltage (or to V+) and one clock is applied, all the counter
outputs will be clocked to the low state. This allows easy
testing of the counter and its outputs.

When the OSCILLATOR SELECT input is high or left open
(the input is provided with a pullup resistor), the oscillator is
configured for RC operation, and the internal clock will be
of ,the same frequency and phase as the signal at the
BUFFERED OSCILLATOR OUTPUT. The resistor and
capacitor should be connected as in Figure 10. The circuit
will oscillate at a frequency given by f
0.45/RC. A 100kO
resistor is recommended for useful ranges of frequency. For
optimum 60Hz line rejection, the capacitor value should be
chosen such that 2048 clock periods is close to an integral
multiple of the 60Hz period (but not less than 50pF).

=

INTERFACING

-r
24

SEL

v+

OR OPEN

22

23

25

osc

osc

IN

'OUT

BUFFERED
OSC
OUT

Direct Mode
Figure 12 shows some of the combinations of chip enable
and byte enable control signals which may be used when
interfacing the ICL7109 to parallel data lines. The CE/LOAD
input may be tied low, allowing either byte to be controlled
by its own enable as in Figure 12A. Figure 12B shows a
configuration where the two byte enables are connected
together. In this configuration, the CE/LOAD serves as a
chip enable, and the HBEN and LBEN may be connected to
GND or serve as a second chip enable. The 14 data outputs
will all be enabled simultaneously. Fiigure 12C shows the
HBEN and LBEN as flag inputs, and CE/LOAD as a master
enable, which could be the READ strobe available from most
microprocessors.

----

R

C
lose

~

.45/RC

Figure 10: RC OscillatOr
WhEln the OSCILLATOR SELECT input is Iowa feedback device and output and input capacitors are added to the
oscillator. In this configuration, as shown in Figure 11, the
4-40

ICL7109
A.

GND-.....- - - ,

GND

B.

c.

GND

MODE
69-612
POL, OR

69·612
POL, OR
61-612
POL, OR

14
61-68

61·68
ANALOG
IN

ICL7109

HBEN

ICL7109

ANALOG
IN

RUN/HOLD .......- - CONVERT
L6EN

RUN/HOLD

CHIP

CONTROL

ICL7109

ANALOG
IN

RUN/HOLD .......- - CONVERT

CONVERT

S~~~C~~ - - 4 - - - - - '

6YTE FLAGS

Figure 12: Direct Mode Chip and Byte Enable Combinations
access the data. This application also shows the RUN/HOLD
input being used to initiate conversions under software
control.

Figure 13 shows an approach to interfacing severallCL7109s
to a bus, ganging the HBEN and LBEN signals to several
converters together, and using the CE/LOAD inputs
(perhaps decoded from an address) to select the desired
converter.

A similar interface to Motorola MC6800 or MOS Technology
MCS650X systems is shown in Figure 16. The high to low
transition of the STATUS output generates an interrupt via
the Control Register B CB1 line. Note that CB2 controls the
RUN/HOLD pin through Control Register B, allowing
software-controlled initiation of conversions in this system
also.

Some practical circuits utilizing the parallel three-state
output capabilities of the ICL7109 are shown in Figures 14
through 19. Figure 14 shows a straightforward application to
the Intel MCS-48, -80 and -85 systems via an 8255PPI, where
the ICL7109 data outputs are active at all times. The I/O ports
of an 8155 may be used in the same way. This interface can
be used in a read-anytime mode, although a read performed
while the data latches are being updated will lead to
scrambled data. This will occur very rarely, in the proportion
of setupcskew times to conversion time. One way to
overcome this is to read the STATUS output as well, and if it
is high, read the data again after a delay of more than 1/2
converter clock period. If STATUS is now low, the.second
reading is correct, and if it is still high, the first reading is
correct. Alternatively, this timing problem is completely
avoided by using a read-after-update sequence, as shown in
Figure 15. Here the high to low transition of the STATUS
output drives an interrupt to the microprocessor causing ilia
CONVERTER
SELECT

Figure 17 shows an interface to the Intersil IM6100 CMOS
microprocessor family using the IM6101 PIE to control the
data transfers. Here the data is read by the microprocessor in
an 8-bit and a 6-bit word, directly from the ICL7109 to the
microprocessor data bus. Again, the high to low transition of
the STATUS output generates an interrupt leading to a
software routine controlling the two read operations. As
before, the RUN/HOLD input to the ICL7109 is shown as
being under software control.
The three-state output capability of the ICL7109 allows
direct interfacing to most microprocessor busses. Examples
of this are shown in Figures 1, 18 and 19. It is necessary to
CONVERTER
SELECT

CONVERTER
SELECT

8-61T BUS

GND

GND

GND
MODE

MODE

CE/LOAD
69-B12
POL, OR

MODE

CE/LOAD

ICL7109

ICL7109

ICL7109
61-B8

B1-B8
ANALOG
IN

61-68

RUN/HOLD 1---1-- +5V

BYTE SELECT FLAGS

8

ANALOG
IN

ANALOG
IN
RUN/HOLDI----+5V

CE/LOAD
B9-B12
POL, OR

B9-B12
POL, OR

<

Figure 13: Three-stating Several 7109's to a Small Bus

4-41

RUN/HOLD

+5V

4

ICL7109
carefolly consider the system timing in this type of interface,
to be sure that requirements for setup and hold times, and
minimum pulse widths are met. Note also the drive limitations on long busses, Generally this type of interface is only
favored if the memory periphllral address density is low so

that simple address decoding can be used, Interrupt
handling can also require many additional components, and
usin\l an interface device will usually simplify the system in
this case,

.(

ADDRESS BUS

~

CONTROL BUS

~l

I I

I I

(
GND

J

~J

I

MODE

CE/LOAD

RD

B9-B12
POL, OR

6

WR

11

11

1J

11 11 11

DATA BUS

t}
D7-DO

PAs-PAo

AO-Al

J
j

I I

J

cs

y

--

RUN/HOLD 1---+5V
ICL7109

~

Bl-B8

PB7-PBa

8255
(MODE 0)

8008,8080,
8085,8048 ETC

y
STATUS

IN

GND

8

HBEN

LBEN

1

I

r-SEETEXT -

PCs

Figure 14: Full-time Parallel Interface to MCS-48, -80, -85 Microcomputer Systems

(

ADDRESS BUS

>

CONTROL BUS

j

IJ

JJ

(
GND

!

I

MODE

CE/LOAD
B9-B12
POL, OR

JJ

DATA BUS

1; tJ 1;
RD

6

WR

D7-DO

AO-Al

~~

I I

JJ

1J tl

lJ

CS

PAs-PAo
y

RUN/HOLD

8

Pc.

ICL7109

~

Bl-B8
STATUS

IN

8

--:\1

--

"

GND

HBEN

LBEN

j

I

J

STBA Y

l"F

8255

8008,8080,
8085, 8048 ETC

PB7-PBa

pc,

10k!!
PC.

INTRA

INTR

+5V
SEE TEXT

Figure 15: Full-time Parallel Interface to MCS-48, -80, -85 Microcomputers With Interrupt

4-42

~

j

ICL7109
GND
MODE
B9-B12
POL, OR r - - - - - - /

PAO-S
CRBI--llR-Oll

ICL7109
Bl-B8

MC680X
OR
MCS650X

PBO-7
MC6820

ANALOG
IN

ST ATUS ~--------..J CBl
RUN/HOLD 1---------; CB2

GND--~--~--~

ADDRESS
BUS

DATA
BUS

CONTROL
BUS

Figure 16: Fuil·time Parailel Interface to MC680X or MCS650X Microprocessors
12-BIT DATA BUS

GND

MODE
B9-B12
POL, OR
IM6100
CMOS

IM6101
CMOS
PIE

ICL7109

"p

Bl·B8
ANALOG
IN

STATUS

SENSE 1

RUN/HOLD

WRITE (OR FLAG)

CONTROL BUS

Figure 17: ICl7l09-IM6l00 Interface Using IM6l0l PIE

ICL7109

8008,8080,8085
Bl-B8

ANALOG
IN
CE/LOAD 1-----------'
*MEMR or lOR
for 8080/8228 System

GND

+SV

Figure 18: Direct Interface - ICl7l09 to 808018085

4-43

II

ICL7109 ,
GNP

B9-B12
POL, OR

MC680X

B1-B8

OR
MCS650X

ANALOG
IN

HBEN~--------------~
74C42
LBEN~--------------~

ADDRESS
BUS

DATA
BUS

CONTROL
BUS

Figure 19: Direct ICL7109 - MC680X Bus Interface
Handshake Mode

separately, the data from every conversion (provided the
data access takes less time than a conversion) will be
sequenced in two bytes into the system.

The handshake mode allows ready interface with a wide
variety of external devices. For instance, external latches
may be clocked by the rising edge of CE/LOAD, and the byte
enables may be used as byte identification flags or as load
enables.
Figure 20 shows a handshake interface to Intel microprocessors again using an 8255PPI. The handshake operation with
the 8255 is controlled by inverting its Input Buffer Full nBF)
flag to drive the SEND input to the ICL7109, and using the
CE/LOAD to drive the 8255 strobe. The internal control
register of the PPI should be set in MODE 1 for the port used.
If the 7109 is in handshake mode and the 82551BF flag is low,
the next word will be strobed into the port. The strobe will
cause IBF to go high (SEND goes low), which will keep the
enabled byte outputs active. The PPI will generate an
interrupt which when executed will result in the data being
read. When the byte is read, the IBF will be reset low, which
causes the ICL7109 to sequence into the next byte. This
figure shows the MODE input to the ICL7109 connected to a
control line on the PPI. If this output is left high, or tied high

If this output is made to go from low to high, the output
sequence can be obtained on demand, and the interrupt may
be used to reset the MODE bit. Note that the RUN/HOLD
input to the ICL7109 may also be driven by a bit of the 8255 so
that conversions may be obtained on command under
software control. Note that one port of the 8255 is not used,
and can service another peripheral device. The same
arrangement can also be used with the 8155.
Figure 21 shows a similar arrangement with the MC6800 or
MCS650X 'microprocessors, except that both MODE and
RUN/HOLD are tied high to save port outputs.
The handshake mode is particularly convenient for directly
interfacing to industry standard UARTs (such as the Intersil
IM6402/6403 or Western Digital TR1602) providing a
minimum component count means of serially transmitting
converted data. A typical UART connection is shown on
page 3. In this circuit, any word received by the UART causes

(

ADDRESS BUS

(

CONTROL BUS

I I
I I

I I

C.

~J

RD
B9-B12
POL, OR
ICL7109
B1-B8

9

IN

CE/LOAD

6

~

\

'1-1
STBA

{:c ~J
07-00

AO-A1

I I

II

~J ~}

II

cs

PA7-PAo

pc,

RUN/HOLD

~ pc,

MODE

pc,

SEND

WR

DATA BUS

lr

8008,8080,
8085, 8048 ETC

8255
(MODE 1)

PCs

PC3

INTR

Figure 20: Handshake Interface - ICL7109 to MCS-48, -80, 85

4-44

(
(
(

ICL7109
+5V-.------,

CRA 1--100.011

ICL7109

MC6S00
OR
MCS650X

MC6S20

ANALOG
IN

ADDRESS
BUS

Figure 21! Handshake Interface the UART DR (Data Ready) output to go high. This drives the
MODE input to the ICL7109 high, triggering the ICL7109 into
handshake mode. The high order byte is output to the UART
first, and when the UART has transferred the data to the
Transmitter Register, TBRE (SEND) goes high and the
second byte is output. When TBRE (SEND) goes high again,
LBEN will go high, driving the UART ORR (Data Ready Reset)
which will signal the end of the transfe'r ,of data from the
ICL7109 to the UART.

CONTROL
BUS

The applications of the ICL7109 are not limited to those
shown here, The purpose of these examples is to provide a
starting point for users to develop useful systems, and to
show some of the variety of interfaces and uses of the
ICL7109. Many of the ideas suggested here may be used in
combination; in particular the uses of the STATUS,
RUN/HOLD, and MODE signals may be mixed,

Figure 22 shows an' eXtension of the one converter - one
UART sGheme of the Typical Connection to several
ICL7109s with one UART, In this circuit, the word received
by the UART (available at the RBR outputs when DR is high)

SERIAL OUTPUT

if

IM6403 CMOS UART

~

TBRL

ORR

TBRE

.----J
!

DATA
BUS

ICL7109 to MC6800, MCS650X
is used to select which converter will handshake with the
UART. With no external components, this scheme will allow
up to eight ICL7109sto interface with one UART. Using a few
more components to decode the received word will allow up
to 256 converters to be accessed on one serial line.

SERIAL INPUT
TB{l1·TBRS

RBR1·RBRS

11

Ir
(

S·BIT DATA BUS

. 7V),
the COMMON voltage will have a low voltage coefficient
1.001%1%), low output impedance (~15fl), and a temperature
coefficient typically less than 80ppmfO C.

set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same point, thus removing the common mode voltage
from the converter.

COMMON

7116f7117

COMMON

v(a)

(b)

Figure 4: USing an External Reference

Within the IC, analog COMMON is tied to an N channel FET
that can sink 30m A or more of current to hold the voltage 2.8
volts below the positive supply (when a load is trying to pull
the common line positive). However, there is only 10p.A of
source current, so COMMON may easily be tied to a more
negative voltage thus over-riding the internal reference.

TEST
The TEST pin serves two functions. On the 7116 it is coupled
to the internally generated digital supply through a soon
resistor. Thus it can be used as the negative supply for
externally generated segment drivers such as decimal points
or any other presentation the user may wantto include on the
LCD display. Figures 5 and 6 show such an application. No
more than almA load should be applied.
V+

7116

The limitations of the on-chip reference should also be
recognized, however. With the 7117, the internal heating
which results from' the LED drivers can cause some
degradation in performance. Due to their higher thermal
resistance, plastic parts are poorer in this respect than
ceramic. The combination of reference Temperature
Coefficient (TC), internal chip dissipation, and package
thermal'resistance can increase noise near full scale from 25
p.V to 80 p.Vpk-pk. Also the linearity in going from a high
dissipation count such as 1000 (20 segments on) to a low
dissipation count such asllll (8 segments on) can suffer by
a count or more. Devices with a positive TC reference may
require several counts to pull out of an overload condition.
This is because overload is a low dissipation mode, with the
three least. significant digits blanked. Similarly, units with a
negative TC may cycle between overload and a nonoverload count as the die alternately heats and cools. All
these problems are of course eliminated if an external
reference is used.

TOlCO
DECIMAL POINT

Figure 5: Simple Inverter for Fixed Decimal Point
,--

V+

7116

V+
--1

gt.i 1~ c'i~ L

BP'I-DE-CIMA-L[---..---+-\:
POINT
SELECT

I

~,

1--/

j

POINTS

:D+
,

L-_...-_..J

v+

,

I

CD4030

DP ON,
L__
GROUND ~ DP OFF.
~

I

__--'

\GND

Figure 6; Exclusive 'OR' Gate for Decimal Point Drive

The 7116, with its negligible dissipation, suffers from none of
these problems. In either case, an external reference can
easily be added, as shown in Fig. 4.

The second function is a "lamp test". When TEST is pulled to
high (to V+) all segments will be turned on and the display
should read - 1888. [Caution: on the 7116, in the lamp test
mode, the segments have a constant DC voltage (no squarewave) and will burn the LCD display if left in this mode for
several minutes.)

. Analog COMMON is also the voltage that input low returns
to during auto-zero and de-integrate. If IN LO is different
from analog COMMON, a common mode voltage exists in
the system and is taken care of by the excellent CMRR of
the converter. However, in some applications IN LO will be

4-62

ICL7116/1CL7117
to 8 mA, typical for instrument size common anode LED
displays. Since the 1000 output Ipin 19) must sink current
from two LED segments, it has twice the drive capability or 16

DIGITAL SECTION
Figures 7 and 8 show the digital section for the 7116 and
7117, respectively. In the 7116, an internal digital ground is
generated from a 6 volt Zener diode and a large P channel
source follower. This supply is made stiff to absorb the
relative large capacitive currents when the back plane (BP)
voltage is switched. The BPfrequency is the clock frequency
divided by 800. For three readings/second this is a 60 Hz
square wave with a nominal amplitude of 5 volts. The
segments are driven at the same frequency and amplitude
and are in phase with BP when OFF, but out of phase when
ON. In all cases negligible DC voltage exists across the
segments.

mAo
In both devices the polarity indicator is ON for negative
analog inputs. This can be reversed by Simply reversing IN
LO and IN HI.

HOLD Reading Input
The HLDR input will prevent the latch from being updated
when this input is at a logic "HI". The chip will continue to
make A/D conversions, however, the results will not be
updated to the internal latches until this input goes low. This
input can be left open or connected to TEST (7116) or
GROUND (7117) to continuously update the display. This
input is CMOS compatible, and has a70k typical resistance
to either TEST (7116) or GROUND (7117).

Figure 8 is the Digital Section of the 7117. It is identical
except the reQulated supply and back plane drive have been
eliminated and the segment drive has been increased from 2

DISPLAY FONT
,-, , -, :;
L'

I

C

_,

'-:5:5::::9

-------------------------.------------.---+--.----i~~~+~----~+~+i~~---·i4++~+1----~~~·=~i

TYPICAL SEGMENT OUTPUT

aSCl

OSC 2

esc 3

Figure 7: Digital Section 7116

4-63

ICL7116/ICL7117

.1-'-

,. -,

DISPLAY FONT

,.

.O~OI6

,.-:-,.

-

el-"
d

---------,I
I
I

I

I
I
I
I
I

TYPICAL SEGMENT OUTPUT

I

--~~------~_4r-----------~----+_~r__+------------~v+

37
500

n

TEST
I
I

'---___+-----+----t-,.,----------------'F.===----~---21~1 DIGITAL
1 _____________

I

..J

GROUND

HLDR

osc 2

aSCl

asc 3

Figure 8: Digital Section 7117

System Timing

Figure 9 shows the clocking arrangement used in the 7116.
and 7117. Three basic clocking arrangements can be. used:
2. A crystal between pins 39 and 40.

Both the buffer amplifier and the integrator have a class A
output stage with 100!,A of quiescent current. They can
supply 20!,A of drive current with negligible non-linearity.
The integrating resistor should be large enough to remain
in this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 volt full scale, 470k!l is
near optimum and similarly a 47kO for a 200.0 mV scale.

3. An R-C oscillator using all three pins.
7116/7117

I

I
I
I

,
I
I

TO
:
COUNTERI

I

I

I
I

I

I
I

L________

I

2-3Mn
'!!'________

'!."_______ _

COMPONENT VALUE SELECTION
1. Integrating Resistor

1. An external oscillator connected to pin 40.

I

40kHz (2.5 readings/second) will reject both 50 and 60 Hz
(also 400 and 440 Hz).

I

3! ________ J

2. Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up
will not saturate the integrator swing (approx. 0.3 volt
from either supply). In the 7116 or the 7117, when the
analog COMMON is used as a reference,a nominal ±2volt
full scale integrator swing is fine. Forthe 7117 with ±5 volt
supplies and analog common tied to supply ground, a
±3.5 to ±4 volt swing is nominal. For three readings/
second (48kHz clock), nominal values for C'NT are 0.22
and 0.10!,F,respectively. Of course, if different oscillator
frequencies are used, these values should be changed in
inverse proportion to maintain the same output swing.

EXTERNAL
OSCILLATOR
TEST (7116)

or OND (7117)

Figure 9: Clock Circuits

The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are signal integrate (1000
counts), reference de-integrate (Q to 2000 counts) and autozero (1000 to 3000 counts). For signals less than full *ale,
auto-zero gets the unused portion of reference deintegrate.
This makes a complete measure cycle of 4,000 (16,000 clock
pulses) independent of input voltage. For three readings/
second, an oscillator frequency of 48kHz would be used.

An additional requirement of the integrating capacitor is
it have low dielectric absorption to prevent roll-over
errors. While other types of capacitors are adequate for
this application, polypropylene capacitors give
undetectable errors at reasonable cost.

To achieve maximum rejection of 60 Hz pickup, the signal
integrate cycle should be a multiple of 60 Hz. Oscillator
frequencies of. 240kH;:, 120kHz, 80kH;:, 60kHz, 48kHz,
40kH;:, 33 '/3 k Hz, etc. should' be selected. For 50Hz
rejection, Oscillator frequencies of 200kHz, 100kHz,
66 2/3 kHz, 50kHz, 40kH;:, etc. would be suitable. Note that

3. Auto-Zero Capacitor
The si;:e oflhe auto-zero capacitor has some influence on
the noise olthe system. For 200 mVfull scale where noise

4-64

ICL7116/ICL7117
for Y,N *0. Temperature and weighing systems with a
variable tare are examples. This offset reading can be
conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or
fixed) offset voltage between COMMON and IN LO.

is very important, a 0.471'F capacitor is recommended. On
the 2 volt scale, a 0.0471'F capacitor increases the speed
of recovery from overload and is adequate for noise on
this scale.

7. 7117 Power Supplies

4. Reference Capacitor

The 7117 is designed to work from ±5 volt supplies.
However, if a negative supply is not available, it can be
generated from the clock output with 2 diodes, 2
capacitors, and an inexpensive I.C. Figure 10 shows this
application. See ICL7660 data sheet for an alternative.

A 0.1 I'F capacitor gives good results in most applications.
If rollover errors occur a larger value, up to 1.01'F may be
required.

S. Oscillator Components
For all rangf''' of frequency a 100kD resistor is
recommendE!!! ~nd the capacitor is selected from the
equation f =~. For 48kHz clock (3 readings/second), C
= 100pF.

6. Reference Voltage
The analog input required to generate full-scale output
(2000 counts) is: Y,N = 2VREF. Thus, for the 200.0 mV and
2.000 volt scale, VREF should equal 100.0 mV and 1.000
volt, respectively. However, in many applications where
the AID is connected to a transducer, there will exist a
scale factor other than unity between the input voltage
and the digital reading. For Instance, in a weighing system, the designer might like to have a full scale reading
when the voltage from the transducer is 0.682V. Instead
of dividing the input down to 2oo.0mV, the designer
should use the input voltage directly and select VREF =
.341V. Suitable values for integrating resistor and
capacitor would be 120kO and 0.22JLF. This makes the
system slightly quieter and also avoids a divider network
on the input. The 7117 with ± 5 volts supplies can accept
input signals up to ± 4 volts. Another advantage of this
system occurs when a digital reading of zero is desired

Figure 10: Generating Negative Supply from +5v
In fact, in selected applications no negative supply is
required. The conditions to use a single +5V supply are:

°

1. The input signal can be referenced to the center of the
common mode range of the converter.
2. The signal is less than ±1.5 volts.
3. An external reference is used.

TYPICAL APPLICATIONS
The 7116 and 7117 may be used in a wide variety of configurations. The circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these A/D converters.

7116
'-'

OSC1
PSC2
ose 3

.

7117
Set VREF

e REF
C REF

pO.1~F

1Kn

COMMON

AlZ

au"'"
INT
VG,
C3
A3
G3

ap

R-

=.01~F
O.47~F

-AA'A 47KHj,
,22iJ F

Set VREF = lOG.OmY

1~F'

/
,I

REF HI

V+

22Kn

C REF
C REF

1 Mil

1= ~ I=:

lOOK!}
"V

~~~~=

A',

l-

40

osc 2

=100,OmV

/

100·PF

TEST
REF HI

v+

'-' csc 1

100KO

F-

~O.'"F{

COMMON

+

-

,'A

,

INHI

IN

IN LQ

-

~

!-:

+
IN

47Kn

.22#F

,

G,
C3

) TO DISPLAY

'"

G3
GND

~ TO BACK PLANE
21

1 Mil

=.Ol"F

'.':

Vc

) TO DISPLAY

·5'

22Kn

O.47 /-t F

A/Z
BUFF
INT

..:. 9V

1Kn

21

-5V

,
,

----------- --------"

Figure 12: 7117 using the internal reference. Values shown are for
200.0 mV full scale, 3 readings per second. IN LO may be tied to
either COMMON for inputs floating with respect to supplies, or GND
for single ended inputs. (See discussion under Analog Common.!

Figure 11: 7116 using the internal reference. Values shown are for
200.0 mV full scale, 3 readings per second, floating supply voltage
(9V battery).

4-65

ICL7116/1CL7117
7116/7117

7117

40

OSC 1

'-../

OSC

'-../

100K"

2 LQ-J---+J\JV\.----o Sol VREF = I.OOOV

~~~~ ~

REF HI

V+

~ ::~

100pF

2SKn

COMMON D---~

V+
C REF
C REF
COMMON
IN HI

24KO

1Mn

+

I~~D----+-~_.~. O~I"~F~~V----ol
AlZ

B~:~ D _ _--IV.I-=-.----'
V_[}___~
.. ·2~2"~F_ _ _ _ _ _ _ __o~

BUFF
INT

~: ~

:r--

PO.1/J

~

1TO DISPLAY

BP/GND

/
..A.

A',

1Kn

,;~KI;f"~K~
"-".2V (ICL ....)
1M!!

+5V

+
IN

:::;: .OI,uF

-

O.47}.tF
..A.

A

47Knj
.22j.1F

G2
Co
Ao
Go
GND

I

Sel VREF"" 1DO.OmY

100pF

v-

I

GJ

lOOK!!

.V'

lNA~~ :::::!

U_·0_4~7"-F1t---;:";;;OK;;""'l

G2

40

TEST
REF HI

/

D--h-----,
~.
r--'\J'\/'v----'VV\r-+--<>V+
PO.1}.tF

asc 1
asc 2
osc 3

} TO

DISPL~Y

21

21

Figure 13: 7116/7117: Recommended component values for 2.000V
full scale.

Figure 14: 7117 operated from single +5V supply. An external
reference must be used in this application, since the voltage between
V' and V-- is insufficient for correct operation of the internal
reference .

.-------9 V+

7117

7116

REF HI

Silicon NPN
MPS 3704 or
similar

D------.......,J-.,.

v- 0---="--<>

,,

!

TO DISPLAY

TO BACK PLANE

Figure 16: 7116 used as a digital centigrade thermometer. A silicon
diode-connected transistor has a temperature coefficient of about
--2mV/' C. Calibration is achieved by placing the sensing transistor
in ice water and adjusting the zeroing potentiometer for a 000.0
reading. The sensor should then be placed in bailing water and the
scale-factor potentiometer adjusted for 100.0 reading.

Figure 15: 7117 measuring ratiometric values of Quad Load Cell. The
resistor values within the bridge are determined by the desired
sensitivity.

APPLICATION NOTES
A016"Selecting AID Converters," by David Fullagar.
A017"The Integrating AID Converter," by Lee Evans.
A018"Do's and Don'ts of Applying AID Converters,"
by Peter Bradshaw and Skip Osgood.
A019"4Y,-Digit Panel Meter Demonstratorllnstrumentation Boards," by Michael Dufort.
A023"Low Cost Digital Panel Meter Designs;" by
David Fullagar and Michael Dufort.
A032"Understanding the Auto-Zero and Common-Mode
Behavior of the ICL7106/7/9 Family," by Peter
Bradshaw.
A046"Building a Battery-Operated Auto Ranging DVM
with the ICL7106," by Larry Goff.
A047"Games People Play with Intersil's AID Converters,"
edited by Peter Bradshaw.
A052"Tips for Using Single-Chip 3Y,-Digit AID Converters," by Dan Watson.

4·66

ICL7126
Single-Chip 31J2-Digit
Low-Power AID Converter
GENERAL DESCRIPTION

FEATURES
o
o

o
o
o
o
o

o
o
o
o
o

The Intersil ICL7126 is a high performance, very low power
3'12-digit AID converter. All the necessary active devices are
contained on a single CMOS IC, including seven segment
decoders, display drivers, reference, and clock. The 7126 is
designed to interface with a liquid crystal display (LCD) and
includes a backplane drive. The supply current is 100,..A,
ideally suited for 9V battery operation.
The 7126 brings together an unprecedented combination of
high accuracy, versatility, and true economy. High accuracy,
like auto-zero to less than 1O,..V, zero drift of less than
l,..Vl o C, input bias current of 10pA max., and rollover error
of less than one count. The versatility of true differential
input and reference is useful in all systems, but gives the
designer an uncommon advantage when measuring load
cells, strain gauges and other bridge-type transducers. And
finally the true economy of single power supply operation
allows a high performance panel meter to be built with the
addition of only 7 passive components and a display.
The ICL7126 can be used as a plug-in replacement for the
ICL7106 in a wide variety of applications, changing only the
passive components.

Guaranteed zero reading for 0 Volts Input on all scales
True polarity at zero for precise null detection
1pA typical Input current
True differential Input and reference
Direct LCD display drive - no external components
required
Pin compatible with the ICL7106
Low noise - less than 15~V pop
On-chip clock and reference
Low power dissipation guaranteed less than 1mW
No additional active circuits required
Evaluation Kit available (ICL7126EV/KIT)
8,000 hours typical 9 Volt battery life

PIN CONFIGURATION
OSC 1
OSC2
OSC 3
TEST
REF HI
REF LO

01
IN

+ -

iii
!::

~

-

R,
240KJl

_
~

Cl
81

1

Al
Fl

G1

C+REF

El
02
C2

COMMON

j

C-REF

IN HI
INLO

82

~ ~

~FF

E2

INT

_ { 03

v-

.;

G2 (TENS)

83

~ ~

~l~
G3 ~

(MI:U~~'-IoI_ _ _ _ _oIoII...

8P

(1000) A84

ORDERING INFORMATION

Part
Temp. Range
7126
O·C to +70·C
7126
O·C 10 +70·C
7126
O·Cto +70·C
7126 Kit
ICL7128wlih Liquid Crystal Display

4-67

Package
40-Pln Ceramic DIP
4O-Pin Plastic DIP
40-Pin CERDIP
Evaluation Kits

Order Number
ICL7126CDL
ICL7126CPL
ICL7126CJL
ICL7126EV/KIT

4

.D~D(6

ICL7126
A8S0LUTE MAXIMUM RATINGS

Power Dissipation (Note 2)
Ceramic Package ............................ , .. 1000mW
Plastic Package .................................. SOOmW
Operating Temperature .................... O°C to +70°C
Storage Temperature ................... -65°C to +160°C
Lead Temperature (Soldering, 60 sec) .............. 300°C

Supply Voltage (v+ to V-) ........................... 15V
Analog Input Voltage (either input) (Note 1) ..... V+ to VReference Input Voltage (either input) .......... V+ to VClock Input .................................. TEST to V+

Note 1: Input voltages may exceed the supply voltages provided the input current is limited to ±100!,A.
Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit'board.
'COMMENT: Stress"s above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devices. This is a stress
rating only and functional operation of the devices at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (Note 3)

TYP

MAX

UNITS

-000.0

±OOO.O

+000.0

Dig.ital Reading

999

999/1000

1000

Digital Reading

-VIN = +VIN ~ 200.0mV

-1

±0.2

+1

Counts

Linearity (Max. deviation from
best straight line fit)

Full scale = 200mV
or full scale = 2.000V

-1

±0.2

+1

Counts

Common Mode Rejection Ratio
(Note 4)

VCM = ±1V, VIN = OV.
Full Scale = 200.0mV

50

/lV/V

Noise (Pk - Pk value not exceeded
95% of time)

VIN =OV
Full Scale = 200.0mV

15

/lV

CHARACTERISTICS
Zero Input Reading

CONDITIONS
VIN =O.OV
Full Scale = 200.0mV

Ratiometric Reading

VIN =VREF
VREF= 100mV

Rollover Error (Difference in
reading for equal positive and
negative reading near Full Scale)

MIN

1

10

pA

0.2

1

fJ.V!°C

1

5

ppm/oC

50

100

fJ.A

2.S

3.2

V

Leakage Current@ Input

VIN =OV

Zero Reading Drift

VIN=O
orc < TA < 70°C

Scale Factor Temperature
Coefficient

VIN = 199.0mV
0°C

Ib>

Figure 4: Using an External Reference
output impedance ("'1,50), and a temperature coefficient
typically less than BOppm/o C.
The limitations of the on-chip refer.ence should also be
recognized, however. The reference temperature coefficient
. (TC) can cause some deg'radation in performance. Temperature changes of2 toBOC, typical for instruments, can
give a scale factor error of a count or more. Also the common
voltage will have a poor voltage coefficient when the total
supply voltage is less than that which will cause the zener
to regulate «7V). These problems are eliminated if an
external reference is used, as shown in Figure 4.
Analog COMMON is also used as the input low return dur-'
ing auto-zero and de-integrate. If IN LO is different from
analog COMMON, a common mode voltage exists in the
system and is taken care of by the excellent CMRR of the
converter. However, in some applications IN LO will be set
at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied
to the same paint, thus removing the common mode voltage
from the converter. The same holds true for the reference
voltage. If reference can be conveniently referenced to
analog COMMON, it should be since this removes the common mode voltage .from the reference system.

Analog COMMON
This pin is included primarily to set the common mode
voltage for battery operation or for any system where the
input signals are floating with respect to the power supply.
The COMMON pin sets a voltage that is approximately 2.B
Volts more negative than the positive supply. This is selected
to give a minimum end-of-life battery voltage of about 6V.
However, the analog COMMON has some of the attributes of
a reference voltage. When the total supply voltage is large
enough to cause the zener to regulate «7V), the COMMON
voltage will have a low voltage coefficient (0.001%1%), low

Within the IC, analog COMMON is tied to an N channel FET
that can sink 100/lA or more of current to hold the voltage
2.B Volts below the positive supply (when a load is trying to
pull the common line positive). However, there is only 1/lA
of source current, so COMMON may easily be tied to a more
negative voltage thus over-riding the internal reference.

Test

generated segment drivers such as decimal points or any
other presentation the user may want to include on the LCD
display. Figures 5 and 6 show such an application. No more
than a 1mA load should be applied.

The TEST pin serves two functions. It is coupled to the
internally generated digital supply through a 5000 resistor.
Thus it can be used as the negative supply for externally
y+

y+

7126

TO LCD
DECIMAL-POINT

'-----0

BP'r----_<-\

7126

~~~;~LANE

Figure 5: Simple Inverter for Fixed Decimal Point

Figure 6: Exclusive "OR' Gate for Decimal Point Drive

4-70

ICL7126
,
I
I

The second function is a "lamp test." When TEST is pulled
high (to v+) all segments will be turned on and the display
should read - 1888. The TEST pin will sink about 10mA
under these conditions.

II

Caution: In the lamp test mode, the segments have a
constant D-C voltage (no square-wave) and may burn the
LCD display if left in this mode for extended periods.

I
IL _____ _

TO
COUNTERr

I
I
I

I

I

I
I

I
~

I
_____________ .JI

DIGITAL SECTION
TEST

Figure 7 shows the digital section for the 7126. An internal
digital ground is generated from a 6 Volt Zener diode and a
large P channel source follower. This supply is made stiff
to absorb the relative large capacitive currents when the
back plane (BP) voltage is switched. The BP frequency is
the clock frequency divided by 800. For three readings/second
this is a 60 Hz square wave with a nominal amplitude of
5 Volts. The segments are driven at the same frequency and
amplitude and are in phase with BP when OFF, but out of
phase when ON. In all cases negligible DC voltage exists
across the segments. The polarity indication is "ON" for
negative analog inputs. If IN LO and IN HI are reversed, this
indication can be reversed also. if desired.

Figure 8: Clock Circuits

System Timing
Figure 8 shows the clocking arrangement used in the 7126.
Three basic clocking arrangements can be used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An R-C oscillator using all three pins.
The oscillator frequency is divided by four before it clocks
the decade counters. It is then further divided to form the
three convert-cycle phases. These are siQnal integrate (1000

DISPLAY FONT

OJ,?3'-:SS ::39

---r----~---+----~---1--~--~~~~--~------~--~VV~TEST

*Three Inverters.
One inverter shown for clarity.
--------~......---=.:"G)v-

OSC1

Figure.7: Digital Section

4-71

ICL7126
counts), reference de-integrate (0 to 2000 counts) and autozero (1000 to 3000 counts). For signals less than full scale,
auto-zero gets the unused portion of reference deintegrate.
This makes a complete measure cycle of 4,000(16,000 clock
pulses) independent of input voltage. For three readings!
second, an oscillator frequency of 48kHz would be used.

3. Aut\l-Zero Capacitor

The size of the auto-zero capacitor has some influence
on the noise of the system. For 200mV full scale where
noise is very important, a 0.32jlF capacitor is recommended. On the 2 Volt scale, a 0.033jlF capacitor
increases the speed of recovery from overload and is
adequate for noise on this scale.

To achieve maximum rejection of 60 Hz pickup, the signal
integrate cycle should be a multiple of 60 Hz. Oscillator
frequencies of 60kHz, 48kHz, 40kHz, 33-1/3kHz, etc. should
be selected. For 50Hz rejection, oscillator frequencies of 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that
40kHz (2.5 readings/second) will reject both 50 and 60Hz
(also 400 and 440Hz)'

4. Reference Capacitor

A OJ jlF capacitor gives good results in most applications
However, where a large common mode voltage exists
(i.e., the REF LO pin is not analog COMMON) and a
200mV scale is used, a larger value is required to prevent
roll-over error. Generally 1.0jlF wi II hold the foil-over
error to 0.5 count in this instance.

COMPONENT VALUE SELECTION
1. Integrating Resistor

III

5. Oscillator Components

Both the buffer amplifier and the integrator have a class A
output stage with 6jlA 01 quiescent current. They can
supply -1jlA of drive current with negligible non-linearity.
The integrating resistor should be large enough to remain
in this very linear region over the input voltage range, but
small enough that undue leakage requirements are not
placed on the PC board. For 2 Volt full scale, 1.8MO is
near optimum and similarly 180kO for a 200.0mV scale.

For all ranges of frequency a 50pF capacitor is recommended and the resistor is selected from the approximate
equation f - ~. For 48kHz clock (3 readings/second),
R = 180kO.
6. Reference Voltage

2. Integrating Capacitor

The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up
will not saturate the integrator swing (approx. 0.3 Volt·
from either supply). When the analog COtl(1MON is used
as a reference, a nominal ±2. Volt full scale integrator
swing is fine. For three readings/second (48kHz clock)
nominal values for CINT are 0.047jlF, for 1/sec (16kHz)
0.15jlF. Of course, if different oscillator frequencies are
used, these values should be changed in inverse proportion to maintain the same output swing.
The integrating capacitor should have low dielectric
absorption to prevent roll-over errors. While other types
may be adequate for this application, polypropylene
capacitors give undetectable' errors at reasonable cost.
At three readings/sec., a 7500 resistor should be placed in
series with the integrating capacitor, to compensate for
comparator delay. See App. Note A017 for a description of
the need and effects of this resistor.

The analog input required to generate full-scale output
(2000 counts) is: VIN = 2VREF. Thus, for the 200.0mV and
2.000 Volt scale, VREF should equal 100.0mV and 1.000
Volt, respectively. However, in many applications where
the A/D is connected to a transducer, there will exist a
scale factor other than unity between the input voltage
and the digital reading. For instance, in a weighing
system, the designer might like to have a full scale reading when the voltage from the transducer is 0.682V.
Instead of dividing the input down to 200.0mV, the
designer should use the input voltage directly and select
VREF = 0.341V. A suitable value for integrating resistor
would be 330kO. This makes the system slightly quieter
and also avoids the necessity of a divider network on the
input. Another advantage of this system occurs when a
digital reading of zero is desired for VIN"", O. Temperature
and weighting systems with a variable tare are examples.
This offset reading can be conveniently generated by
connecting the voltage transducer between IN HI and
COMMON and the variable (or fixed) offset voltage
between COMMON and IN LO.

TYPICAL APPLICATIONS
The 7126 may be used in a wide variety of configurations.
The circuits which follow show some of the possibilities,
'-/

,

osc 1
TEST

To pin 1 -

40

~~~!F

--'\/\

/
,A

PO.1~F

-A.

10KH

220KO
1M!!

IN HI

+

:;:.01~F

0.33/-IN

[J_ _~7~50~n~~0~.0~47~"~F_ _ _ _ _~V_

U - - = - - - - - - - - - -......~-5V

Figure 11: Recommended component values for 2.000V full scale, 3
readings per second. For 1 reading per second, delete 750n resistor,
change C'NT, Rose to values of Fig. 10.

Figure 12: 7126 with Zener diode reference. Since low T.C. zeners
have breakdown voltages - 6.SV, diode must be placed across the
total supply (10V). As in the case of Figure 11, IN La may be tied to
COMMON.
-,T~o~p~ln"----------~V'

40
OSCl
OSC2

Set Yref '" lOO.OmY

OSC3~---U----

/

SOpF

TEST

REF HI

TEST

SOpF

+5V

REF LO
C REF
C REF

COMMON
IN HI
IN LO

IN

.Ol/-tF
O.33J.1F

AlZ
BUFF

lBOKn

}TD

DISPLAY':"

--....:::!!!~2f,-=-_TO BACK PLANE

Figure 13: 7126 operated from single +5V supply. An external
reference must be used in this application, since the voltage between
V+and V- is insufficient for correct operation olthe internal reference.

Figure 14: 7126 measuring ratiometric values of Quad Load Cell.
The resistor values within the bridge are determined by the desired
sensitivity.

Scale factor adjust

0--=-./

lMn

lOOKn

Silicon NPN
MPS 3704 or
similar

D-:::;;:::~==!-\:;:;470;.;-KIoise (p.p Value not
Exceeding 95% of Time)

Y'N = OV
200mV Scale

(V

Y'N =OV

1.0
Counts
dB
(v+) - 0,5

)+ 1,5
7,0

V

MV

Input Leakage Current

Y'N = OV, Pin 32, 33

1

10

pA

Scale Factor Tempco

Y'N = 199mV
O·C < TA < + 70·C
External VREF = Oppm/·C

2

5

ppm/·C

COMMON Voltage

V+ to Pin 28

3.2

3,5

COMMON Sink Current
COMMON Source Current

aCommon = + 0,1 V
aCommon = - 0,1 V

DGND Voltage

V+ to Pin 36

2,8

0.6
12
4,5

5,3

V

mA
MA
5,8

V

V+toV-=9V

DGND Sink Current

aDGND= +0,5V

Supply Voltage Range

V+ to V

Supply Current Excluding

V+ to V

1,2
6

=9V

mA

9

14

V

1,0

1.4

mA

120

360

kHz

COMMON Current
Clock Frequency
Display Multiplex Rate

ICLK = 120kHz

100

Hz

VOISP Resistance

VoisP to V+

50

kll

4·76

ICL7129
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS

(Continued) V + to

v- =9V, VAEF =1.00V. TA = + 25"C, ICLK = 120kHz, unless otherwise noted.
MIN

TYP

MAX

UNIT

V + to V-

6.3

7.2

7.7

V

CONTINUITY Comparator

VOUT Pin 27 = HI

100

200

Threshold Voltages

VOUT Pin 27 = LO

Pull·Down Current

Pins 37, 38. 39

"Weak Output'· Current

Pin 20, 21

3/3

Sink, Source

Pin 27 Sink/Source

3/9

Low Battery Flag

CONDITIONS

Activation Voltage

200

400

2

10

Pin 22 Source Current

40

Pin 22 Sink Current

3

~A

.r.r,r,Q

-'.0.0.0.0
.

r --- -

-

BACKPLANE
DRIVES
~

ANNUNCIATOR
DRIVE

-+-HH-- - - ,

~-+-+-+-HH-+-+"""'~

I

OSC1

VDISP

OSC2

OSC3

CONTROL LOGIC

L

-4---

RANGE OH CONT

V+

V-

DGND

------OR
DP4

UR
DP3

DP2

Figure 1. Simplified Block Diagram of ICL7129 Digital Section

4·77

~A

I,A

LOW BATTERY CONTINUITY

SEGMENT DRIVES

mV

I

ICL7129
Table I. Pin Assignments and Functions
PIN
I
2
3
4
5

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

21

22

NAME
OSCI
OSC3
ANNUNCIATOR
DRIVE

FUNCTION
Input to first clock inverter.
Output of second clock inverter.
Backplane squarewave output for driv·
ing annunciators.

B,. C" CONT

Output
OutPUt
Output
Output
Output
Output
Output
Output

A"G"D,
F" E" DP,
B2, C 2, LO BATT
A 2, G2, D2
F2, E2 , DP2
B3, C3, MINUS
A 3, G3, D3
F3, E3, DP3
B4 , C4, BCs
A 4 , D4 , G4
F4 , E4 , DP4
BP3
BP2
BPI
Y01SP
DP4 10R

DP31UR

LATCHIHOLD

to
to
to
to
to
to
to
to

display
display
display
display
display
display
display
display

PIN

segments.
segments.
segments.
segments.
segments.
segments.
segments.
segments.

Output to display segments.
Output to display segments.
Output to display segments.
Output to display segments.
Backplane #3 output to display.
Backplane #2 output to display.
Backplane #1 output to display.
Negative rail for display drivers.
INPUT: When HI, turns on most signifi·
cant decimal point.
OUTPUT: Pulled HI when result count
exceeds ± 19,999.
INPUT: Second most significant
decimal paint on when HI.
OUTPUT: Pulled HI when result count
is less than ±'I,OOO.
INPUT: When floating, AiD converter
operates in the free·run mode. When
pulled HI, the last displayed reading is
held. When pulled LO, the result
counter contents are shown increment·
ing during the de'integrate phase of
cycle.
OUTPUT: Negative going edge occurs
when the data latches are updated.
Can be used for converter status
signal.

NAME

23

V-

24

y+

FUNCTION
Negative power supply terminal.
Positive power supply terminal, and "
positive rail for display drivers.

25

INTIN

Input to integrator amplifier.

26

INTOUT

Output of integrator amplifier.

27

CONTINUITY

INPUT: When LO, continuity flag on !tie
display is. off. When HI, continuity flag
is on.
OUTPUT: HI when voltage between in·
puts is less than + 200m V, LO when
voltage between inputs is more than
+200mY.

28

COMMON

Sets common·mode voltage of 3,2V
below y+ for DE, lOX, etc. Can be used
as pre·regulator for external reference.

29

CREF +

Positive side of external reference
capacitor,

30

C REF

Negative side of external reference
capaCitor.

-

31

BUFFER

32

IN LO

Output of buffer amplifier.
Negative input voltage terminal.

33

.IN HI

Positive input voltage terminaL

34

REF HI

Positive reference voltage input
terminaL

35

REF LO

Negative reference voltage input
terminal.

36

DGND

Ground reference for digital section,

37

RANGE

3~A

38

DP2

Internal 3~A pull·down. When HI,
decimal point 2 will be on.

39

DP,

Internal3~A pull·down, When HI,
decimal point 1 will be on.

40

OSC2

Output of first clock inverter. Input of
second clock inverter.

pull·down for 200mY scale. Pulled
HIGH externally for 2Y scale.

DETAILED OPERATION DESCRIPTION
Intersil'slCL7129 is a uniquely designed single-chip AID converter. It features a new "successive integration" technique
to achieve 10!'V resolution on a 200mV full-scale range. To
achieve this resolution a 10:1 improvement in noise perform·
ance over previous monolithic CMOS AID converters was
accomplished.' Previous integrating converters used an ex·
ternal capacitor to store an offset correction voltage. This
technique worked well but greatly increased the equivalent
noiSe bandwidth of the converter. The ICL7129 removes this
source of error (noise) by not using, an auto-zero capacitor.
Offsets are instead cancelled using 'digital techniques. Savings in external parts cost are realized as well as improved
noise performance and elimination of asource eleoVomagnetic and electrostatic pick·up.
The overall block diagram of the ICL7129 is shown in Figure 1.
The heart of this AID converter is the sequence counterl
decoder whi!;h drives the control logic and keeps track of the
many separate phases required for each conversion cycle.

The sequence counter is constantly running and is a sepa·
rate counter from the upldown results counter which is activated only when the integrator is de-integrating. At the end
of a conversion the data remaining in the results counter is
latched, decoded and multiplexed to the liquid crystal
display.
The analog section block diagram shown in Figure 2 includes
all of the analog switches used to configure the voltage
sources and amplifiers in the different phases of the cycle.
The input and reference switching schemes are very similar
to those in other less accurate integrating AID converters.
, There are 5 basic configurations used in the full conversion
cycle. Figure 3 illustrates a typical waveform on the in·
tegrator output. INT, INTI' and INT2 all refer to the signal
integrate phase where the input voltage is applied to the
integrator amplifier via the buffer amplifier. In this phase, the
integrator ramps over a fixed period of time in a direction opposite to the polarity of the input voltage.

4-78

ICL7129

RiNT

,-

REF HI

REFLO

I
I
I
I
I

TO DIGITAL
SECTION
ZI. X10

COMMONQ-----------~

REST

INLO¢---tO--t--~~--t-~~~~

COMMONo-------t--~~

INL06--~~~~_+---~---~~----------

to DISPLAY
CONTINUITY O--------------~-----.... DRIVER
(NOT LATCHED)

Figure 8. "Instant Continuity" Comparator and Output' Structure

4·81

ICL7129
DISPLAY CONFIGURATION

ANNUNCIATOR DRIVE

The ICL7129 is designed to drive a triplexed liquid crystal
display. This type of. display has three backplanes and is
driven in a multiplexed format similar to the ICM7231 display
driver family. The specific display format is shown in Figure 9.
Notice that the polarity sign, decimal. points, "LOW BAT·
TERY", and "CONTINUITY" annunciators are directly driven
by the ICL7129; The individual segments and annunciators
are addressed ina manner similar to row·column addressing.
Each backplane (row) is connected to one·third of the total
numberof segments. BP1 has all F, A, and B segments of the
four least significant digits. BP2has all of the C, E, .and G
segments. BP3 has all D segments, decimal points, and an·
n,unciators. The segment lines (columns) are connected in
groups 6f three bringing all segments of the display out on
just 12 lines.

A special display driver output is provided on the ICL7129
which is intended to drive various kinds of annunciators on
custom multiplexed liquid crystal displays. The ANNUN·
CIATOR DRIVE output (pin 3) is a squarewave signal running
at the bac\_-4>--.:.:

ICL7129

ICL7129
36

36 DGND

75k

DGND

18k

~

____-4____________--+23

'--______--+23

V-

V-

Figure 12. Two Methods for Temperature Compensating the
Liquid Crystal Display

DISPLAY TEMPERATURE COMPENSATION

COMPONENT SELECTION

For most applications an adequate display can be obtained
by connecting V01SP (pin 19) to DGND (pin 36). In applications
where a wide temperature range is encountered, the voltage
drive levels for some trlplexed liquid crystal displays may
need to vary with temperature in order to maintain good
display contrast and viewing angle. The amount of tempera·
ture compensation will depend upon the type of liquid crystal
used. Display manufacturers can supply the temperature
compensation requirements for ,their displays. Figure 12
shows two circuits that can be adjusted to give a temperature
compensation of '" + 10mVI"C between V+ and V01SP. The
diode between DGND and VoisP should have a low turn·on
voltage to assure that no forward current is injected on the
chip if VOISP is more negative than DGND.

There are only three passive components around the ICL7129
that need special consideration in selection, They are the
reference capacitor, integrator resistor, and integrator
capacitor. There is no auto·zero capacitor like that found in
earlier integrating AID converter designs.

The integrating resistor is selected high enough to assure
good current linearity from the buffer amplifier and integrator
and low enough that PC board leakage is not a problem. A
value of 150k should be optimum for most applications. The
integrator capacitor is selected to give an optimum inte·
grator swing at full·scale, A large integrator swing will reduce
the effect of noise sources in the comparator but will affect

4·83

ICL7129
rollover error if the swing gets too close to the positive rail
("'0.7V). This gives an optimum swing of ",2.5V at full-scale.
For 150k integrating resistor and 2 conversions per second
the value is O.1D!,F. For different conversion rates, the value
will change in inverse proportion. A second requirement for
good linearity is that the capacitor (lavel()w diel.ectric absorption. Polypropylene caps give good'~erformance at a
reasonable price. Finally the foil side of the cap should be
connected to the integrator output to shield against pick-up.

It is important to notice that in Figure 14, digital ground of the
ICL7129 (DGND pin 36) is not directly connected to power supply ground. DGND is set internally to approximately 5V less
than the V + terminal and is not intended to be used as a
power input pin. It may be used as the ground reference for
external logic, as shown. in Figure 5 and 6. In Figure 5, DGND
is used as the negative supply rail for external logic provided
that the supply current for the external logic does not cause
excessive loading onDGND. The DGND output can be buffered as shown in Figure 6.. Here, the logic supply current is
shunted away from the ICLi129 keeping the load on DGND
low. This treatment of the. DGND output is necessary to insure compatibility When the external logic is used to inter·
face directly with the logic inputs and outputs of the ICL7129.

The only requirement for the reference cap is that it be low
leakage. In order to reduce the effects of stray capacitance, a
1.0!,F value is recommended.

CLOCK OSCILLATOR
The ICL7129 achieves its digital range changing by integrating the input signal for 1000 clock pulses (2,000 oscillator
cycles) on the 2V scale and 10,000 clock pulses on the 200mV
scale. To achieve complete rejection of 60Hz on both scales,
an oscillator frequency of 120kHz is required, giving two conversions per second.

+5V

24

V~EFHI 34

In low resolution applications, where the converter uses only
3% digits and 100!'V resolution, an R-C type oscillator is adequate. In this application a C of 51pF is recommended and
the resistor value selected from fosc=0.45/RC. However,
when the converter is used to its full potential (4 % digits and
10!'V resolution) a crystal oscillator is recommended to prevent the noise from increasing as the input signal is increased
due to frequency jitter of the R-C oscillator. Both R-C and
crystal oscillator circuits are shown in Figure 13.

~

~;~: ICL~~:
36

DGND

ICL8069

LO 35
28

COM

IN HI ..,3:=.3_.-'-"""""'_0 +

..,.

VIN

O.1.F

v-

IN LOc:3:=.2_t-_ _ _O
r

23

I
I
ICL7129

I

___

-lI

-5V

2

Figure 14. Powering the ICL7129 from + 5V and - 5V Power
Supplies

I
I
ICL7129 I
I
___ -l

. When a battery voltage between .3.SV and 7V is desired for
operation, a voltage doubling circuit should be used to bring
the voltage on the ICL7129 up to a level within the power supply voltage range. This operating mode is shown in Figure 15,

24

Figure 13. RC and Crystal Oscillator Circuits

POWERING THE ICL7129

v+
+
:

REF 34
HI

REF LO 35

3.8VT06V

The ICL7129 may be operated asa battery powered hand-held
instrument or integrated into larger systems that. have more
sophisticated power supplies. Figures 14, 15, and 16 show
various powering modes that may be used with the ICL7129.

36 DGND

COM 28

ICL7129
33
IN HI

F"--+-_"""'I\r---Q +

The standard battery connection using a 9V battery is shown
on the front page of this data sheet.

ICL7880

The power connection for systems with + 5V and - 5V supplies available. is shown in Figure 14. Notice that measurements are with respect to ground. COMMON is I)ot connected to INPUT LO but is used only as a pre-regulator for the
external voltage reference.

V-

IN 32
LO

23

Figure 15. Powering the ICL7129 from a 3.8V to 6V Battery

4-84

VIN

ICL7129
as a reference voltage for applications where ambient temperature variations are expected to be minimal. When the
ICL7129 is used in most environments, other voltage references should be considered. The diagram on the front page
of this data sheet shows the ICL80691.2V band-gap voltage
source used as the reference for the ICL7129 and the COMMON output as its pre-regulator. The reference voltage for the
ICL7129 is set to 1.000V for both 2V and 200mV full-scale
operation.

Again measurements are made with respect to COMMON
since the entire system is floating. Voltage doubling Is accomplished by using an ICL7660 CMOS voltage converter
and two Inexpensive electrolytic capacitors. The same principle applies in Figure 16 where the ICL7129 is being used in a
system with only a single + 5V . power supply. Here
measurements are made with respect to power supply
ground.
A single polarity power supply can be used to power the
ICL7129 in applications where battery operation is not appropriate or convenient only if the power supply is isolated
from system ground. Measurements must be made with
respect to COMMON or some other voltage within its input
common-mode range.

Figures 17 and 18 show two other methods for generating
precision references that are compatible with the ICL7129.
Both reference voltage and input voltage are connected to
power supply ground. The use of a .6.2V reference diode is
shown in Figure 18. The voltage drop across R1 ~ 2.8V to
minimize rollover error caused by stray capacitance charging
or discharging the reference capacitor. The reference voltage
in this case is taken with respect to V + and is adjusted with
the trim potentiometer connected to REF LO (pin 35).

VOLTAGE REFERENCES
The COMMON output of the ICL7129 has a temperature coefficient of ± 80ppm/oC typically. This voltage is only suitable

+5Vo-------~--~-----------.--------_.

24

V+

ICL8069

O.l"F
36

ICL7129

8

33

+
3

ICL7680

10"F

4

+
Y,N

32

V23

"::"

Figure 16. Powering the ICL7129 from a Single Polarity Power Supply

v·

v·
15

24
REFHI

COM
IN HI
INLO
23

24

~~

ICL7129
REFLO

16

,,-!

35

REF HI 34

REFERENCE

t....-.2.

REF LO 35

4

~

ICL7129

7

33
32

J.

6.2V

=*

+

IN HI r3c:.3__________+ __~-'lN..---<>+

v, N

Y,N

INLOr3=2----------+--~------_o
23

V-

V-

Figure 17. Using a Heated-Substrate 1.000V Reference with the
ICL7129

Figure 18. Using a 6.2V Reference Diode with the ICL7129

4·85

ICL7134
14·81t p.P·Compatible
Multiplying D/A Converter

FEATURES

GENERAL DESCRIPTION

• 14·blt linearity (0.003% FSR)
• No gain adjustment necessary
• Mlcroprocessor·compatlble with double buffered
Inputs
• Bipolar application requires no extra adjustments
or external resistors
• Output current settllng·tlme 3!dJ max (0.9!dJ typ)
• Low linearity and gain temperature coefficients
• Low power dissipation
• Full four·quadrant multiplication

The ICL7134 combines'a four·quadrant multiplying DAC
using thin film reSistors and CMOS circuitry with an on-chip
PROM-controlled correction circuit to achieve true 14-bit
linearity without laser trimming.

O.

Microprocessor bus interfacing is eased by standard
memory WRite cycle timing and control signal use. Two input
buffer registers are separately loaded with the Bleast significant bits (LS register) and the 6 most significant bits (MS
register). Their contents are then transferred to the 14-blt
DAC register, which controls the output switches. The DAC
register can also be loaded directly from the data inputs, in
which case the registers are transparent.

FuI' .......................,...

The ICL7134 is supplied in two versions. The ICL7134U is programmed for unipolar operation while the ICL7134B is programmed for bipolar applications. The VREF input to the most
significant bit of the DAC is separated from the reference input to the remainder of the ladder. For unipolar use, the two
reference inputs are tied together, while for bipolar operation,
the polarity of the MSB reference is reversed, giving the DAC
a true 2's complement input transfer function. Two resistors
which facilitate the reference Inversion are included on the
chip, so only an external op-amp is needed. The PROM Is
coded to correct for errors in these resistors as well as the inversion o·f the MSB.

PIN CONFIGURATION

ORDERING INFORMATION

NON-LINEARITY

'

TEMPERATURE RANGE
O'C to + 70'C

- 2S'C to + 8S'C

- SS'C to + 12S'C

ICL7134BJCJI
ICL7134BKCJI
ICL7134BLCJI

ICL7134BJIJI
ICL7134BKIJI
ICL7134BLlJI

ICL7134BJMJI
ICL7134BKMJ I
ICL7134BLMJI

ICL7134UJCJI
ICL7134UKCJI
ICL7134ULCJI

ICL7134UJIJI
ICL7134UKIJI
ICL7134ULlJI

ICL7134UJMJI
ICL7134UKMJI
ICL7134ULMJI

Bipolar Versions
0.01 % (12-bit)
0.006% (13-bit)
0.003% (14-bit)
Unipolar Versions
0.01 % (12·bit)
0.006% (13-bit)
0.003% (14-bit)

Package: 28·pin CERDIP only

(outline dwg JI)

4:86

ICL7134
ABSOLUTE MAXIMUM RATINGS (Note 1)
SupplyVoltage(V+ toDGND) ............. -0.3Vt07.5V

Storage Temperature Range ........... - 65'C to + 150'C

± 25V

10UT,AGNDF,AGNDs ..................... -O.1VtoV+

Power Dissipation (Note 2) ................... ,. 500mW
Derate Linearly Above 70'C @ 10mW/'C

Currentin AGND s , AGND F ....................... 25mA

Lead Temperature (Soldering, 10 seconds) .......... 300'C

V AFL , V AFM , R,Ny, RFB to DGND ................. "

An, Dn, WR, CS, PROG .............. -0.3VtoV+ +0.3V
Operating Temperature Range
ICL7134XXC .......................... O'C to + 70'C
ICL7134XXI ....................... -20'Cto + 85'C
ICL7134XXM ..................... -55'Cto+125'C

Note 1: All voltages with respect to DGND.
Not. 2: Assumes all leads soldered or welded to printed circuit
board.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS (v+

= 5V, VREF =10V, TA = + 25'C unless otherwise specified.)
LIMITS

PARAMETER

SYMBOL

UNIT

TEST CONDITIONS
MIN

Resolution
Non·Linearity

TYP

Bits

14

J

Test Figure 1
(Notes 1 and 2)

K

L
Non·Linearity Temperature Coefficient
Gain Error

1

Operating Temperature Range

J

Test Figure 1
(Notes 1 and 2)

K
L

2

Gain Error Temperature Coefficient
Monotonicity

IOlK

Power Supply Rejection

PSRR

ICL7134U
ICL7134B

VAEF = ± 10V, 2kHz Sinewave

ZAEF

VAFl = VRFM (Unipolar Mode)

Output Capacitance

COUT

DAC Register = All O's
DAC Register _ All l's

Output Noise

Equivalent Johnson Res.

Low State Input

V'Nl

Operating Temperature Range

V'NH

Operating Temperature Range

ppm/'C
% FSR
% FSR
% FSR

8

ppm/'C
Bits
Bits
Bits

Ilin

elin

Supply Voltage Range

V+

50
100

ppmiV

0.9

3

~s

250
500

Functional Operation

Supply Current

,+

(Excluding Ladder)

~Vp·p

10

4.0
160
235

k!l
0.8

V

1.0

~A

V

2.4

pF

15

1000 Hours, + 125'C (Note 3)

Note 1: Full·Scale Range (FSR) is 10V for unipolar mode, 20V (±10V) for bipolar mode.
Note 2: Using internal feedback and reference inverting resistors.
Note 3: Guaranteed by design, not 100% tested in production.

4·87

k!l
pF

7

(Note 3)

nA

1

O,;;V'N ,;;V+

Logic Input Capacitance

Long Term Stabil ity

2
0.020
0.012
0.006

50

TA = +25'C,dV+ = ±10%
Operating Temperature Range

Reference Input Resistance

Logic Input Current

% FSR
% FSR
% FSR

10

TA = +25'C
Operating Temperature Range

Output Current Settling Time

High State Input

0.010
0.006
0.003

14
14
14

J
K
L

lOUT Leakage Current

Feedthrough Error

MAX

3.5
0.06
10

6.0

V

0.5

mA
ppml-Jmonth

ICL7134
AC CHARACTERISTICS (v+

=5V, see Timing Diagram)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN

TYP

MAX

Address-WRite Set-Up Time (Min)

tAws

100

Address-WRite Hold Time (Min)

t AWh

0

Chip Select-WRite Set-Up Time (Min)

tcws

0

Chip Select-WRite Hold Time (Min)

tCWh

0

WRite Pulse Width Low (Min)

tWR

200

Data-WRite Set-Up Time (Min)

tows

200

Data-WRite Hold Time (Min)

tOWh

0

UNIT

ns

DEFINITION OF TERMS
NONLINEARITY: Error contributed by deviation of the PAC
transfer function from a straight line function between endpOints. Normaily expressed as a percentage of fuil scale
range. For a multiplying PAC, this should hold true over the
entire V REF range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2 - n) (V REF). A
bipolar converter of n bits has a resolution of [2 - (n
[VREFI.
Resolution in no way implies linearity.

-11

SETTLING TIME: Time required for the output function of the
PAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to fuil-scale.
Timing Diagram

GAIN: Ratio of the PAC's operational amplifier output voltage to the nominal input voltage value.
FEEDTHROUGH ERROR: Error caused by capacitive coupling from V REF to output with ail switches OFF.

Table 1. Pin Assignment and Funcli.on Description
PIN

SYMBOL

1

CS

2

WR

3
4
5
6
7
8
9
10
11
12
13
14
15
16

Do
01
O2
03
04
05
06
07
08
09
010
0 11
0 12
0 13

DESCRIPTION
Chip SelecUaclive low).
Enables register write.
WRite, (active lOW). Wrl~s In
register. Equivalent to CS.
Least significant.
BltO
Bit 1
Blt2
Bit 3
Bit 4
Input
Bit 5
Data
Blt6
Bits
Bit 7
(High = True)
Bit 8
Bit.9
Bit 10
Bit 11
Bit 12
Bit 13 MostslQriiiicanC -

-------

PiN

SYMBOL

17

PROG

18
19

VRFL
RINV

20
21

VRFM
RFB

22
23

DGND
AGND F

24

AGNDs

25
26
27
28

lOUT
V+

4·88

A1
Ao

DESCRIPTiON
Used for programming only. Tie to
+ 5V for normal operation.
VREF for lower bits.
Summing node for reference inverting
amplifier.
VREF for MSB only (bipolar).
Feedback resistor for voltage output
applications.
Digital GrouND return.
Analog GrouND force line. Use to
carry current from internal Analog
GrouND connections. Tied internally
toAGND s·
Analog GrouND sense line. Reference
point for external circuitry. Pin should
carry minimal current; tied internally
to AGND F.
Current output pin.
Positive supply voltage.
Address 1 I ·
.
.
Control register lines
AddressO .

I

ICL7134
TEST CIRCUITS (Unipolar operation shown)
VREF

+5V

BITl (MSB)

RFB

013

lOUT

14·81T
BINARY
COUNTER

ICL7134U

I BIT
"
(LSB)

AGNDs

10kn
0.001"'/0

Do

lMU

Os

..JUl..

LINEARITY

CLOCK

ERROR
)(100

VREF

8111
(MSB)

10""
0,001%

16-81T
REFERENCE
OAe

Figure 1. Non·Linearity

UNGROUNDED
SINE WAVE
GENERATOR

SOOkO

40Hz 2Vp'p
SkU

0.01%
VREF + 10V
(ADJUST FOR -----,._--""1""---1---~w..----,._-

...._j

VERROR == avoc)

VERROR

V+

+5V

x 100
SkO

013

0.01%
ICL7134U

BIT 0 (LSB)

Do

cs

ViR

DGNO

Ao

A1

Figure 2. Power Supply Rejection

VREF

=20Vp·p 2kHz

+5V

+5V

SINE WAVE

VREF +10Y
PROG

v+

R,.I----------,
ICL7134
+-!==;:-;::1~IDo

CS

WR

lOUT
AGNDs
AGND,

DONO AI]

VRFL VRFM

+ ~~ ::rL..fU'"L
DIGITAL INPUT

81T 13 (MSB)

v+

PROG ~ 100m'!l1...l:\... ~S:'LLOSCOPE

013

--1,,---+1
,-!;==~IO.

A1

Figure 3. Feedthrough Error

Figure 4. Output Current Settling Time

4·89

I

ICL7134
FUNCTIONAL DIAGRAM
VRFL

VRFM
RINV

F

R
2R

R

2R

R

R
2R

2R

RF.

F

2R

2R

----~--~-+--~~-1----------_+--4-L-------+_~~--1---~-oIOUT
----~--~-*----~~----------~----~------._~------~~_oAGN~

AGNDF
C·DAC

.-------+-----------------~+--I'DECODE

PROM

-

-

-

-

--oPROG

MSB
14·BIT DAC REGISTER

1---------0 A,
REGISTER

.-----------1-++++_1-----1 Af~~~~

Ao

CS
1---------0 WR

Do • • • • • •

Os • • • •

07

013

Figura 5. ICL7134 Functional Diagram

DETAILED DESCRIPTION
The ICL7134 consists of a 14-bit primary DAC, two PROM controlled correction DACs, input buffer registers, and
microprocessor interface logic (Figure 5). The 14-bit primary
DAC is an R-2R thin film resistor ladder with N-channel MOS
SPOT current steering switches. Precise balancing of the
switch resistances, and all other resistances in the ladder,
results in excellent temperature stability.

found to degrade the time stability of thin film resistors at the
14-blt level.

.Analog Section
The ICL7134 inherently provides both unipolar and bipolar
operation. The bipolar application circuit (Figure 6) requires
one additional op-amp but no external resistors. The two onchip resistors, RINVl and RINV2, together with the op-amp,
form a voltage inverter which drives the MSB reference terminal, VRFMI to - VREF, where VREF Is the voltage applied at
the less significant bits' reference terminal, VRFL. This
reverses the weight of the MSB, and gives the DAC a 2's complement transfer function. The op-amp and reference con·
nection to VRFM and VRFL can be reversed, without affecting
linearity, but a small gain error will be introduced. For
unipolar operation the VRFM and VRFL terminals are both tied
to VREF, and the RINV pin is left unconnected.

True 14-bit linearity is achieved by programming a floating
polysilicon gate PROM array which controls two correction
DAC circuits. A 6-bit gain correction DAC, or G-DAC, diverts
up to 2% of the feedback resistor's current to Analog
GrouND and reduces the gain error to less than 1 LSB, or
0.006%. The 5 most significant outputs of the DAC register
address a 31-word PROM array that controls a 12-bit linearity
correction DAC, or C-DAC. For every combination of the
primary DAC's 5 most signifitant bits, a different C-DAC
code is selected. This allows correction of superposition
errors, caused by bit interaction on the primary resistor ladder's current output bus and by voltage non-linearity In the
feedback resistor. Superposition errors cannot be corrected
by any method which corrects individual bits only, such as
laser trimming. Since the PROM programming occurs in
packaged form, it corrects for resistor shifts caused by the
thermal stresses of packaging. These packaging shifts limit
the accuracy that can be achieved using wafer level correction methods such as laser trimming, which has also been

Since the PROM correction codes required are different for
bipolar and unipolar operation, the ICL7134 is available in
two different versions; the ICL7134U, which is corrected for
unipolar operation, and the ICL7134B, which is programmed
for bipolar application. The feedback resistance is also different in the two versions, and Is switched under PROM control from 'R' in the unipolar device to '2R' in the bipolar part.
These feedback resistors have a dummy (always ON) switch
in series to compensate for the effect of the ladder switches.
This greatly improves the gain temperature coefficient and
the power supply rejection of the device.

4·90

ICL7134
APPLICATIONS

Digital Section
Two levels of input buffer registers allow loading of data from
an S-bit or 16-blt data bus. The An and A1 pins select one of
four operations: 1) load the LS-buffer register with the data at
Inputs Do to 0 7; 2) load the MS-buffer register with the data at
inputs 08 to 0 13; 3) load the OAC register with the contents of
the MS and LS-buffer registers and 4) load the OAC register
directly from the data input pins (see Table 2). The CS and
WR pins must be low to allow data transfers to occur. When
direct loading Is selected (CS, WR, An and A1 low) the registers are transparent, and the data input pins control the OAC
output directly. The other modes of operation allow double
buffered loading of the OAC from an S-bit bus.

General Recommendations
Ground Loops
Careful consideration must be given to ground loops in any
14-blt accuracy system. The current into the analog ground
point inside the chip varies significantly with the input code
value, and the inevitable resistances between this point and
any external connection point can lead to significant voltage
drop errors. For this reason, two separate leads are brought
out from this point on the IC, the AGNOF and AGNOs pins.
The varying current should be absorbed through the AGN OF
pin, and the AGNOs pin will then accurately reflect the
voltage on the internal current summing paint, as shown in
Figure 7. Thus output signals should be referenced to the
sense pin AGNOs , as shown in the various application
circuits.

These input data pins are also used to program the PROM
under control olthe PROG pin. This Is done in manufacturing,
and for normal read-only use the PROG pin should be tied to

V+ (+5V).
Table 2. Data Loading Controls
CONTROL liP
CS
WR
A1

Ao
X
X

X
X

X

1.

X

0
0
1

0
1
0

0
0
0

0
0
0

1

1

0

0

1

ICL7134 OPERATION

Operational Amplifier Selection
To maintain static accuracy, the lOUT potential must be exactIy equal to the AGNO s potential. Thus output amplifier selection is critical, in particular low input bias current (less than
2nA) low offset voltage drift (depending on the temperature
rang~) and low offset voltage (less than 25,N) are advisable if
the highest accuracy is needed. Maintaining a low input offset over a OV to 10V range also requires that the output amplifier has a high open loop gain (AVOl> 400k for effective input
offset less than 25,N).

No operation, device not selected.
Load a/l registers from data bus.
Load LS register from data bus.
Load MS register from data bus.
Load DAC register from MS and LS
register.

Note: Data is latched on LO-HI transition of either WR or

Cs.

VREF

VREF I N - - - - - - - ,

RFB

~'---~LEA!":D:-O lOUT
RESISTANCE

~~~~~~~~~

+----;:::======'1 ~ ~aNO

TO
REST Of
LADDER

LEAD

OF ANALOG

RESISTANCE

\

AGND,

TRUE ANALOG
LEAD
GROUND POINT RESISTANCE

Figure 6. Bipolar Operation, with Inverted VREF to MSB

Figure 7. Eliminating Ground Loops

4-91

SYSTEM

II
~

ICL7134
(

The reference inverting amplifier used in tjlebipolar modecir·
cuit'must also be selected carefully. If 14·bit accuracy is
desired without adjustment, Iqw input bias current(less than
1nA), low offset voltage (less than 50ILV), and high gain
(greater than 400k) are ,recommended. If a fixed reference
voltage is used, the gain requirement can be relaxed. For
highest accuracy (better than 13 bits), an additional op·amp
maybe needed to correct for IR drop on the Analog GrouND
line (op·amp A2 in Figure 9). This op·amp should be selected
for low bias current (less than 2nA) and low offset voltage
(less than 50ILV).

necessary with certain high speed amplifiers. F6r applica·
tions where the output reference ground point is .e!!tablished
somewhere other than at the DAC, the circuit of Figure 9 can
be used. Here, op-amp A2 removes the slight errordueto,lR
vOltage drop between the. internal Analog GrouND nOde and
the external ground ,connection. For 13-bitor lower accuracy,
omit A2 and connect AGNDF and AGNDs directly to ground
through as Iowa resistance as possible.
Table 3. Code Table-Unjpolar Binary Operation

The op·amp requirements can be readily met by use of an
ICL7650 chopper stabilized device. For faster settling time,
an HA?6XX can be u~ed with an ICL7650 providing automatic
offset null (see A053 for details).
'
The output amplifier's non·invertinginput should be tied
directly to AGNDs.A bias current compensation resistor is of
limited use since the output impedance at the summing node
depends on the code being converted in an unpredictable
way. If gain adjustment is required, low tempco (approxi·
mately 50ppml"C) resistors or trim·pots should be selected.
Power Supplies

DIGIT12

ViR
Do-7

DATA BUS

Ao

Figure 14. MCS·650X and MC·680X Families'
Interface to ICL7134

A,

Figure 15. ICL7134 to IM6100 Interface Using IM6101 PIE

ICL7134

OPTIONAL
GATE
(SEETEXn

Figure 16. Avoiding Digital Feedthrough
In an MCS·48 to ICL7134 Interface

INTERSIL
IMSOC48
INTEL
8080
S085
ETC.

ANALOG~
CIRCUIT

L..of

Figure 17. ICL7134 to MCS·48, ·80, ·85 Interface with Low Feedthrough

4-95

II

.O~OIl

ICL7134
Successive Approximation AID Converters
Figure 18 shows an ICL7134B-based circuit for a bipolar input
high speed AID converter, using two AM25L03s to form a
14-bit successive approximation register. The comparator is
a two-stage circuit with an HA2605 front-end amplifier, used
to reduce settling time problems at the summing node (see
A020). Careful offset-nulling of this amplifier is needed, and if
wide temperature range operation is desired, an auto-null circuitusing an ICL7650 is probably advisable (see A053), The
clock, using two Schmitt trigger TTL gates, runs ala slower
rateIor the first 8 bits, where settling-time is most critical,

-[;?* ~5V

than for the last 6 bits, The short-cycle line is shown tied to
the 15th bit; if fewer bits are required, it can be moved up accordingly. The circuit will free-run ifthe HOLD/RUN input is
held low,but will stop after completing a conversion ifthe pin
is high at that time, A low-going puise will restart it. The
STATUS output indicates when the device is operating, and
the falling edge indicates the availability of new data. A
unipolar version may be constructed by tying the MSB (0, 31
on an tCL7134U to'pin 14 on the first AM25L03; deleting the
reference inversion amplifier A4, and tying VRFM to VRFL,

- Y,N +

+15V

~2

7a
'27
>-"'-

19

20
24
CS DGND VRl R/NV VRM AGNDs

WR
Ao
A,

n'7

....

As

1'18

..... HP2800

t>,-

-=

+

22

.....

39kll

... HP2800

2~nrf

+5V

23
21
25
PROG V + AGNDF RFS lOUT

ICL7134B
LSB
8 7 6 5 4 3

MSB
16 1S 1413 12 11 10 9

*~
~"l?
HA260S

+

-1SV

LSBL _

+5V

OUT.

LM311

,+

~
lN827A

+5

-15V

~-

~r

lMIi
1300

>---

~-=:
>--O'MSB

-lSV

15 13 12 11 6 5 4 3

+5V~

F

07 Q6.

•

•

•

14 13 12 11 6 S 4L

.00 CC 2,.......!.

AM25L03

S

0

10

2k!l

Q7 • • • • • Q1

CP 9,.....~ CP 0

7

5100

e:-

7

...

AM25L03

S
10

.......

CC
2

r!L-+5V

~

lN4146

\uJ '''''''jj, .
k'
'
~
H;;800

l000pF

-u=-

HOLD/iiUliI r..

ff

r

HP2800

~4
.W

220!1

·1'l00PF

7

STATUS

Figure 18_ Successive Approximation AID Converter

4-96

B(N+',

SHORT
CYCLE
LINE

v
6800

ICL7134
PC BOARD LAYOUT

A016 "Do's and DonI's of Applying AID Converters," by

Great care should be taken In the board layout to minimize
ground loop and similar "hidden resistor" problems, as well
as to minimize digital signal feedthrough. A suitable layout
for the Immediate vicinity of the ICL7134 is shown in
Figure 19, and may be used as a guide.

Peter Bradshaw and Skip Osgood.

A020 "A Cookbook Approach to High Speed Data Acquisi·
tion and Microprocessor Interfacing," by Ed Sliger.

A021 "Power AID Converters Using the ICH8510," by Dick
Wilenken.

A030 "The ICL7104-A Binary Output AID Converter for

APPLICATION NOTES

Microprocessors," by Peter Bradshaw.

Some applications bulletins that may be found useful are
listed here:
A016 "Selecting AID Converters," by Dave Fullagar.
A017 "The Integrating AID Converter," by Lee Evans.

ROO5 "Interfacing Data Converters & Microprocessors," by
Peter Bradshaw et ai, Electronics, Dec. 9, 1976.
Most of these are available in the Intersil Data Acquisition
Handbook, together with other material.

J

(a) Printed Circuit Side of Card (Single Sided Board)

(b) Top Side with Component Placement

Figure 19. Printed Circuit Board layout (Bipolar Circuit, see Figure 10)

4·97

ICL7135
precision 41/2 Digit Single Chip
A/D Converter

FEATURES

GENERAL DESCRIPTION

• Accuracy guaranteed t~ ±1 count over entire
±20,OOO counts· (2.0000 volts full scale)
• Guaranteed zero reading for 0 volts Input
• 1 pA typical Input current
• True differential Input
• True polarity at zero count for precise null detection
• Single reference v~ltage required
• Over-range and under-range signals available for
auto-ranging capability
• All outputs TTL compatible
• Blinking display gives visual Indication of overrange
.SIX auxiliary InP
. uts/outputs are available for
Interfacing to UARTs, microprocessors or other
complex clrcullry
.
• Multiplexed BCD output versatility

The Intersil ICL7135 precision AID converter, with its
multiplexed BCD output and. digit drivers, combines dualslope conversion reliability with ±1 in 20,000 count accuracy
and is ideally suited for the visual display DVM/DPM market.
The 2.0000V full scale capability, auto-zero and auto-polarity
are combined with true ratiometric operation, almost ideal
differential linearity and true differential input. All necessary
active devices are contained on a single CMOS I.C., with the
exception of display drivers, reference, and a clock.
The Intersil ICL7135 brings together an unprecedented
combination of high accuracy, versatility, and true economy.
High accuracy like auto-zero to less than 10/-lV, zero drift of
less than 1p.V/oC, input bias current of 10 pA max., and
rollover error of less than one count. The versatility of
multiplexed BCD outputs is increased by the addition of
several pins which allow it to operate in.more sophisticated
systems. These include STROBE, OVER RANGE, UNDERRANGE, RUN/HOLD and BUSY lines, making it possible to
interface the circuit to a microprocessor or UART.

a·
,...
•

SET VREF

VAEF IN

100kn

'<>----i41
1i2

1.000V-5V

I

ANALOG'~
GND

.

tnl
lOOkn

a---:::..

SIGNAL
INPUT '

'"

28

Tr

1.0~F

~
1 .~~
·100k~F~
8
~

O.l.F

>C*
fc¥.r1ii

+5VO--~

J

ICL7135

D-I,-{ 'i

1

Ts

~

100kfl

120kHz

~

F.

*G.47~F27h ~
I

r:> ~LOCK

~~D
Ts~h
~I~

~ DISPI.!'Y.-==-

~=~~:

TRANSISTORS

g gl

6

~I---'
~I---'
iiiI---'

~I---'
~

F,i

SEVEN
SEG.·
DECODE

-

ICL7135 with LED Display

ORDERING INFORMATION

PIN CONFIGURATION
v- ~

REFERENCE
ANALOG COMMON

Part

Package

Temp. Range Order Part #

EVI
KIT

Evaluation Kit
(PC Board,
active, passive
components)

[!

INTOUT ~
AZIN 5

7135 28'Pin CERDIP
O°C to +70°C ICL7135CJI
7135 28-Pin Plastic DIP O°C to +70°C ICL7135CPI
ICL135EVI
KIT

INHI

v+

·(MSD)D5

~
11

~

(LSB)Bl ~
B2 14

4·98

dwgs JI, PI)
UNDERRANGE
OVERRANGE
STROBE

25 R/H

BUFF_O~ ~
REF.CAP.- ~
REF. CAP. + ~
INLO 9

i
I

(Outlin~

ICL7135

DIGITAL GND
POL

~ CLOCK IN

~ BUSY
~ (LSD)Dl

~ D2
~ D3

m
17 D4

(MSB)BS
15 B4

ICL7135
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 2)
Ceramic Package .......................... 1000 mW
Plastic Package •........................... 800 mW
Operating Temperature ..•............... O°C to +70°C
Storage Temperature ................ -6SoC to +160°C
Lead Temperature (Soldering, 10 sec) ............ 300°C

Supply Voltage V+ ................................ +6V

V- ............................... -9V
Analog Input Voltage (either input) (Note 1) ..... V+ to VReference Input Voltage (either input) .......... V+ to VClock Input ................................. Gnd to V+

Note 1: Input voltages may exceed the supply voltages provided the input current. is limited to +lOOIlA.
Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devices. This is a stress
rating only and functional operation of the devices at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ICL7135 ELECTRICAL CHARACTERISTICS (Note 1)

v+ =

+ SV, V- = -SV, TA=2SoC, Clock Frequency Set for 3 Reading/Sec

A
N
A
L

0
G

(Note 1)
(Note 2)

INPUTS

0
I
G
I
T
A

L

CHARACTERISTICS
Zero Input Reading
Ratiometric Reading (2)
Linearity over ± Full Scale
(error of reading from
best straight line)
Differential Linearity
(difference between worse
case step of adjacent counts
and ideal step)
Rollover error (Difference in
reading for equal positive &
negative voltage near full scale)
Noise (P-P value not
exceeded 9S% of time)

MIN
-{l.0000

TYP
±O.OOOO

MAX
+0.0000

+0.9998

+0.9999

+ 1.0000

-2V ::; VIN ::; +2V

O.S

1

-2V ::; VIN ::; +2V

.01

= 2V

O.S

1

1S
1
O.S

10
2

jJ.V
pA
jJ.V;oC

2

S

ppm;oC

0.8
0.1
10
0.40

CONDITIONS
VIN = O.OV
Full Scale = 2.000V
VIN:; VREF
Full Scale = 2.000V

-VIN :; +VIN
en

VIN = OV
Full scale = 2.000V

Leakage Current at Input
Zero Reading Drift

IILK

VIN - OV
VIN = OV
0°::; TA::; 70°C

Scale Factor Temperature
Coefficient (3)

TC

VIN = +2V
0::; TA::; 70°C
(ext. ref. 0 ppm/DC)

-Clock In, Run/Hold, See Fig. 2

0

All Outputs

U
T
P
U
T
S
S
U
P
P
L
Y

Bl, B2, B4, B8
01, 02, D3, D4, Ds

Clock

SYMBOL

BUSY, STROBE,
OVER-RANGE, UNDER-RANGE
POLARITY
+SV Supply Range
-SV Supply Range
+SV Supply Current
-SV Supply Current
Power Dissipation Capacitance
Clock Freq. (Note 4)
. .

2.8

LSB

VINH
VINL
hNL
hNH
VOL
VOH

VIN =0
VIN = +SV
IOL = 1.6ma
IOH =-1mA

2.4

2.2
1.6
0.02
0.1
0.2S
4.2

VOH

IOH = -10jJ.A

4.9

4.99

+4
-3

+S
-S

+6
-8

1.1
0.8

3.0
3.0

V+
V
I
I
Cpo

fc = 0
fc = 0

DC

2000

Digital
Count
Error

V
mA
jJ.A
V
V
V

40

vs. Clock Freq

UNITS
Digital
Reading
Digital
Reading
Digital
Count
Error

1200

V
V
mA

pF
kHz

Note 1: Tested In 4-1/2 digit (20,000 count) CirCUit shown In Fig. 1, clock frequency 120kHz.
Note 2: Tested with a low dielectric absorption integrating capacitor. See Component Selection Section.
Note 3: The temperature range can be extended to +70°C and beyond as long as the auto-zero and reference capacitors are increased to
absorb the higher leakage of the ICL7135.
Note 4: This specification relates to the clock frequency range over whioh the ICL7135 will correctly perform its various functions. See "Max
Clock Frequency" below for limitations on the clock frequency range in a system.

4-99

IID~DlL

ICL7135
TEST CIRCUIT

r-------~~------~------ ~

CLOCK
IN
120kHz

'-----..+------DIG GND

Figure 2: 7135 Digital Logic Input

Figure 1: 7135 Test Circuit

DETAILED DESCRIPTION
Analog Section

I

Figure 3 shows the Block Diagram of the Analog Section for
the ICL7135. Each measurement cycle is divided into four
phases. They are (1) auto-zero (A-Z), (2) signal integrate
-____~

-ll~D~3

________~~____-t~

~""D2_____........

>--_ _t-....

~~-~r-~

Figure 6: Timing Diagram for Outputs

4-102

ICL7135
Auto·Zero and Reference Capacitor
The size of the auto·zero capacitor has some influence on
the noise of the system, a large capacitor giving less noise.
The reference capacitor should be large enough such that
stray capacitance to ground from its nodes is negligible.
The dielectric absorption of the reference cap and auto·zero
cap are only important at power·on or when the circuit is
recovering from an overload. Thus, smaller or cheaper caps
can be used here if accurate readings are not required for
the first few seconds of recovery.

To achieve maximum rejection of 60Hz pickup, the Signal integrate cycle should be a multiple of 60Hz. Oscillator fre·
quencies of 300kHz, 200kHz, 150kHz, 120kHz, 100kHz,
40kHz, 33%kHz, etc. should be selected. For 50Hz rejection,
oscillator frequencies of 250kHz, 166%kHz, 125kHz,
100kHz, etc. would be suitable. Note that 100kHz (2.5
readings/second) will reject both 50 and 60Hz.
The clock used should be free from significant phase or frequency jitter. Several suitable low·cost OSCillators are
shown in the Applications section. The multiplexed output
means that if the display takes significant current from the
logic supply, the clock should have good PSRR.

Reference Voltage
The analog input required to generate a fu"·sca'e output is
VIN =2 VREF.
The stability of the reference voltage is a major factor in the
overall absolute accuracy of the converter. For this reason, it
is recommended that a high quality reference be used where
high·accuracy absolute measurements are being made.
Rollover Resistor and Diode
A small rollover error occurs in the 7135, but this can be
easily corrected by adding a diode and resistor in series be·
tween the INTegrator OUTput and analog COMMON or
ground. The value shown in the schematics is optimum for
the recommended conditions, but if integrator swing or
clock frequency is modified adjustment may be needed. The
diode can be any silicon diode, such as a 1N914. These com·
ponents can be eliminated if rollover error is not important,
and may be altered in value to correct other (small) sources
of rollover as needed.
Mall. Clock Frequency
The maximum conversion rate of most dual·slope AID con·
verters is limited by the frequency response of the com·
parator. The comparator in this circuit follows the integrator
ramp with a 3JLs delay, and at a clock frequency of 160kHz
(6JLs period) half of the first reference integrate clock period
is lost in delay. This means that the meter reading will
change from 0 to 1 with a 50JLV input, 1 to 2 with 150JLV, 2 to 3
at 250JLV, etc. This transition at mid·point is considered
desirable by most users; however, if the clock frequency is
increased appreciably above 160kHz, the instrument will
flash "1" on noise peaks even when the input is shorted.
For many·dedicated applications where the input signal is
always of one polarity, the delay of the comparator need not
be a limitation. Since the non·linearity and noise do not in·
crease substantially with frequency, clock rates of up to
-1 MHz may be used. For a fixed clock frequency, the extra
. count or counts caused by comparator delay will be a con·
stant and can be subtracted out digitally.
The clock frequency may be extended above 160kHz without
this error, however, by using a low value resistor in series
with the integrating capacitor. The effect of the resistor is to
introduce a small pedestal voltage on to the integrator out·
put at the beginning of the reference integrate phase. By
careful selection of the ratio between this resistor and the
integrating resistor (a few tens of ohms in the recommended
circuit), the comparator delay can be compensated and the
maximum clock frequency extended by approximately a fac·
tor of 3. At higher frequencies, ringing and second order
breaks will cause significant nonlinearities in the first few
counts of the instrument· see Appli.cation Note A017.
The minimum clock frequency is established by leakage on
the auto-zero and reference caps. With most devices, measurement cycles as long as 10 seconds give no measurable
leakage error.

Zero·Crossing Flip·Flop
The flip·flop interrogates the data once every clock pulse
after the transients of the previous clock pulse and half·clock
pulse have died down. False zero-crossings caused by clock
pulses are not recognized. Of course, the flip·flop delays the
true zero·crossing by up to one count in every instance, and
if a correction were not made, the display would always be
one count too high. Therefore, the counter is disabled for one
clock pulse at the beginning of phase 3. This one-count delay
compensates for the delay of the zero-crossing flip-flop, and
allows the correct number to be latched into the display.
Similarly, a one-count delay. at the beginning of phase 1 gives
an overload display of 0000 instead of 0001. No delay occurs
during phase 2, so that true ratiometric readings result.

EVALUATING THE ERROR SOURCES
Errors from the "ideal" cycle are caused by:
1. Capacitor droop due to leakage.
2. Capacitor voltage change due to charge "suck-out" (the
reverse of charge injection) when the switches turn off.
3. Non·linearity of buffer and integrator.
4. High-frequency limitations of buffer, integrator. and
comparator.
5. Integrating capacitor non-linearity (dielectric absorption.)
6. Charge lost by CREF in charging Cstray.
7. Charge lost by CAZ and CINT to charge Cstray.
Each of these errors is analyzed for its error contribution to
the converter in application notes listed on the back page,
specifically A017 and A032.

NOISE
The peak·to·peak noise around zero is approximately 151'V
(pk-to·pk value not exceeded 95% of the time). Near full
scale, this value increases to approximately 30I'V, Much ,of
the noise originates in the auto·zero loop, and is proportional
to the ratiO' of the input signal to the reference .

ANALOG AND DIGITAL GROUNDS
Extreme care must be taken to avoid ground loops in the
layout of ICL7135 circuits, especially in high-sensitivity circuits. It is most important that return currents from digital
loads are not fed into the analog ground line.

POWER SUPPLIES
The 7135 is designed to work from ± 5V supplies. However,
in selected applications no negative supply is required. The
conditions to use a single + 5V supply are:
1. The input signal can be referenced to the center of the
common mode range of the converter.
2. The signal is less than ± 1.5 volts.
See "differential input" for a discussion of the effects this
will have on the integrator swing without loss of linearity.

4·103

4

ICL7135
TYPICAL APPLICATIONS
The circuits which follow show some oqhe wide variety,of
possibilities, and serve to illustrate the exceptional versatility
of this AID converter.
Figure 7 shows the complete circuit for a 4 cl/2 digit (±2.000V)
full scale) AID with LED readout using the ICL806f1 as a 1.2V
temperature compensated voltage reference. It uses the
band-gap principal to achieve ex.cellent stability and low
noise at reverse currents down to 50MA. The circuit also
shows a typical R-C input filter. Depending on the
application, the time-constant of this filter can be made
faster, slower, or the filter deleted completely. The 1/2 digit

LED is driven. from the 7 segment decoder, with a zero
reading blanked by connecting a 05 signal to RBI input of
the de.coder. The 2-gate clock circuit should use CMOS
gates to maintain good power supply rejection.
Figure 8 is similar except the output drives a multiplexed
common cathode LED Display with the 7-Common Emitter
Transistor Array, for the digit driver transistors, making a
lower component count possible. Botli versions of the
complete circuit will give a blinking display as. a visual
indication of overrange. A clock oscillator circuit using the
ICM7555 CMOS timer is shown.

+5V

~~~~~~~~~-------------o+5V

a.8kl!
ICL8069

7447

1

ANALOG-:-t-~:Jl~~~

b

GND

B1
B2
B4
B8

d

•t
9

III

ICL7135

47k

02 19

03 18
04 17

MSBB8f.1~a~--------~----~------------~------------~~
B4 15

C

RCNETWORK

Jose = .45/RC
·For tlner resolution on scale facto'r adjust. use a 10 lum pol or a sm.all pot In series with a

filed rell,tor.

Figure 7: 4-1/2 Digit A-D Converter with a multiplexed common anode LED display

rn--~--~""'--..J·,

Figure 8: Driving multiplexed common cathode LED displays

4-104

ICL7135
A suitable circuit for driving a plasma-type display is shown
in Fig. 9. The high voltage anode driver buffer is made by
Dionics. The 3 AND gates and caps driving 'BI' are needed
for interdigit blanking of multiple-digit display elements, and
can be omitted if not needed. The 2.5k & 3k resistors set the
current levels in the display. A similar arrangement can be
used with Nixie@ tubes.
The popular LCD displays can be interfaced to the O/Pof the
ICL7135 with suitable display drivers, such as the ICM7211A
as shown in Figure 11. A standard CMOS 4000 series LCD
driver circuit is used for displaying the 1/2 digit, the polarity,
®,

and an 'overrange' flag. A similar circuit can be used with the
ICL7212A LED driver and the ICM7235A vacuum fluorescent
driver with appropriate arrangements made for the 'extra'
outputs. Of course, another full driver circuit could be
ganged to the one shown if required. This would be useful if
additional annunciators were needed. The Figure shows the
complete circuit for a 4-1/2 digit 1±2.000V) A/D.
Figure 10 shows a more complicated circuit for driving LCD
displays. Here the data is latched into the ICM7211 by the
STROBE signal and 'Overrange' is indicated by blanking
the 4 full digits.

Nixie is a registered trademark of Burroughs Corporation.

23 pal
2001
1902

3202

1803

3303

17 04

3404

16 B8

30 B3

15 B4

29 B2

14 B2

28 B1

13 B1

27 BO

II

1205
26 STROBE

ICM7211A

27 OR

ICL7135

Figure 9: ICL7135 Plasma Display Circuit

4-1/2 DIGIT lCO DISPLAY

REF
VOLTAGE

+5V

==~
.?

-5V-Q V-

ICL7135

i2 REF
~ ~~:'~8N

~~~5~1
~ INT OUT
=r= 27ll
O·~I·F ~
AZIN
-

100kll

~

1.F~~
-~ 8

lOOk!!
INP Q:T

"1.0.F ~
6 BUF OUT

I

100kll
_

r-i=i

'* I

O.lj.LF

Figure 10: LCD Display with Digit Blanking on Overrange

~

RC1
RC2
INPUT lO

INPUT HI
+5V-~ v+

fc~::
r1ii

B2

UR

~

OR 27

;=

STROBE
R/H 25

124
pal ~
CLOCK ~
BUSY ~r01 ~
02 ~

DIG. GNO

03
04
B8
B4

l_fUUU
IfU U U

1111
11161514125 3
C04054A

~I

78131110926

Jill

28 SEGMENTS 01-0

B

'BACKPLANE

I
120kC ~ 3 READINGS/SEC
CLOCK IN
5 BP

ICM7211A

31 01
3202

F,i

3303

~

34 04

~

2.3.4 I 6-26
37-40 ~

30 B3

~

OPTI aNAL
CAPAC ITOR

29 B2
28 B1

OSC 36

35 V- .

ov
Figure 11: Driving LCD Displays

4-105

---Lr - - - +5V
22-10OpF

27 BO

V+l
+5V

,ICL7135
TYPICAL APPLICATIONS (Con.d.)
A problem sometimes encountered with both LED & plasmatype display driving is that of clock source supply line
variations. Since the supply is shared with the display, any
variation in voltage due to the display reading may cause
clock supply voltage modulation. When in overrange the
display alternates between a blank display and the 0000
overrange indication. This shift occurs during the reference
integrate phase of conversion causing a low display reading
just after overrange recovery. Both of the above circuits have
considerable current flowing in the digital supply from
drivers, etc. A clock source using Intersil's LM311 voltage
comparator in positive feedback mode (Figure 12) could
minimize any clock frequency shift problem.
The 7135 is designed to work from ±5 volt supplies. However,

,--,.----

Vour

1

10"F

Figure 12: LM311 Clock Source

Figure 13: Generating Negative Supply from +5V

SERIAL OUTPUT
TO RECEIVING UART

t

I

TRO

RRI

t

DR

-

c- EPE
2

3

4

.

5

6

7

8'

lY 2V 3Y

.

TBR

,

1

TBRl

TBRl

TBR

,

UART
IM8402/3

EPE

ORR

IM6402/3

TRO

,

1

2

3

4

5

6

7

8

04

03

02

01

Bl

B2

B4

B.

74C157
lA 2A 3A

N C - Os

STROBE

D4 03 02 01 81 82 84 88

L-

OS

ICL7135

RUN/HOLD ---<> +5V

POL

...

1rl
....
III

ENABLE

~

lB 2B 3B

I I I

-

ICL7135

-

P 0 U
0 V N
l E 0
R ~
'---

RU~~~ ~
BUSY

,

"100pf

\

\

\

= -5V

Figure 14: ICL7135 to UART Interface

+5V
10K

Figure 15: Complex ICL7135 to UART Interface

L-~~~~~-L------~REAOI

Bl B2 B4 B. :; ~
l E

ICL7135

R
R

IM6101

IM6100

STROBE ~----ISENSE 1

RUN/iiOi])~----IWRITE

1

Figure 16: 1M6100 to ICL7135 Interface

4-106

9 of 10

.D~DIb

ICL7135
1V

PAO

EN

1V

PA1
PA2
PA3

PA1
MC680X
OR
MCS6S0X

PA2
PA3

8255
(MODE 1)

Mc6820

03
0,

PAO

PA4
PAS
PA6
PA7

03
04

Figure 17: ICL7135 to MC6800, MCS650X Interface

INTERSIL
IM80C48
INTEL
8080
8085,
ETC.

PA4
PAS
PAS
PA7

Figure 18: ICL7135 to MCS-4S, -80, 85 Interface

transmit sequence. A quad 2 input multiplexer is used to
superimpose polarity, over-range, and under-range onto the
Ds word since in this instan<;:e it is known that B2 = B4 = Bs =

O.
For correct operation it is important that the UART clock be
fast enough that each word is transmitted before the next
STROBE pulse arrives. Parity is locked into the UART at load
. time but does not change in this connection during an output
stream.

APPLICATION NOTES
A016 "Selecting AID Converters," by David Fullagar
A017 "The Integrating AID Converters," by Lee Evans
A018 "Do's and Don'ts of Applying AID Converters," by
Peter Bradshaw and Skip Osgood
A019 "4-112 Digit Panel Meter Demonstrator/lnstrumentation Boards," by Michael Dufort
A023 "Low Cost Digital Panel Meter Designs," by David
Fullagar and Michael Dufort

Circuits to interface the ICL7135 directly with three popular
microprocessors are shown in Figures 16, 17 and 18. The
main differences in the circuits are thatthe IM6100with its 12
bit word capability can accept polarity, over-range, under-I
range, 4 bits of BCD and 5 digits simultaneously where the
"...
8080/8048 and the MC6800 groups with 8 bit words need to
•
have polarity, over-range and under-range multiplexed onto
the Digit 5 word - as in the UART circuit. In each case the
microprocessor can instruct the AID when to begin a
measurement and when to hold this measurement.

A028 "Building an Auto-Ranging DMM USing the
8052A/7103A AID Converter Pair," by Larry Goff
A030 "The ICL7104 " A Binary Output AID Converter for
Microprocessors", by Peter Bradshaw
A032 "Understanding the Auto-Zero and Common Mode
Performance of the ICL7106 Family", by Peter
Bradshaw
R005 "Interfacing Data Converters & Microprocessors," by
Peter Bradshaw et ai, Electronics, Dec. 9, 1976

4·107

ICL7136
3 1/2-Digit
Low Power AID Converter

II

FEATURES

GENERAL DESCRIPTION

• First-reading recovery from overrange gives
immediate "OHMS" measurement
• Guaranteed zero reading for OV input
• True polarity at zero for precise null detection
• 1pA typical input current
• True differential input and reference
• Direct LCD display drive - no external components
required
• Pin compatible with the ICL7106, ICL7126
• Lownoise-15I1Vp-p without hysteresis or
overrange hangover
• On-chip clock and reference
• low power dissipation, guaranteed less than
1mW - gives 8,000 hours typical 9V battery life
• No additional active circuits required
• Evaluation Kit available (ICL7136EVlKit)

The Inter::lil ICL7136 is a high performance, very low power
31f2-digit AID converter. All. the necessary active devices are
contained on a single CMOS IC, including seven-segment
decoders, display drivers, reference, and c.lock. The 7136 is
designed to interface with a liquid crystal display (LCD) and
includes a backplane drive. The supply current is under
100uA, ideally suited for 9V battery operation.
The 7136 brings together an unprecedented combination of
high accuracy, versatility, and true economy. High accuracy,
like auto-zero to less than 10,..V, zero drift of less than 1,..V/oC,
input bias current of 10pA max., and rollover error of less than
one count. The versatility of true differential input and
reference is useful in all. systems, but gives the designer an
uncommon advantage when measuring load cells, strain
gauges and other bridge-type transducers. And finaUy the
true economy of single power supply operation allows a high
performance panel meter to be built with the addition of only
7 passive components and a display.
The ICL7136 is an improved version of the ICL7126,
eliminating the overrange hangover and hysteresis effects,
and should be used in its.place in all. applications. It can also
be used as a plug-in replacement for the ICL7106 in a wide
variety of applications, changing only the passive
components.

ORDERING INFORMATION
PART

PACKAGE

7136
7136
7136
7136 Kit

4D'pin CERDIP
4D·pin Ceramic DIP
4D·pin PlasticDIP
Evaluation Kits

TEMPERATURE
RANGE

ORDER PART
NUMBER

D'C to + 7D'C
D'C to + 70'C
D'C to + 70'C

ICL7136CJL
ICL7136CDL
ICL7136CPL
ICL7136EVlKIT
DISPLAY

PIN CONFIGURATION (Outline dwgs_ DL, JL PL)
V'

rft-"""'!...,.-.....hOS

C1

01

OSC2

1~~

~:;/

~ { i~

:~~6
:~FF

Vi
!::

~
.....

A1
F1
G1
E1
02

!; ~~

-; I

-,,n:' n: n:,

.

I-+-_---'IM.---I-O +

I--+--':::+:=--'---+--O

REF HI
REF LO
C+REF
C-REF
COMMON

E2

INT

~

~~
~

~~ (TENS)
C

--

E3

A~l§

(1000) AB4
G3
(MI:U~~""'''-_ _ _''''''''f-'BP

!!.

DISPLAY

ICL7136 with Liquid Crystal Display

4-108

IN

ICL7136
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (V + to V -) .... ' .................... 15V
Analog Input Voltage(either input)(Note 1) ...... V + to VReference Input Voltage (either input) .......... V + to VClock Input .............................. TEST to V +

Power Dissipation (Note2)
Ceramic Package .......................... 1000mW
Plastic Package ............................ 800mW
Operating Temperature ................... O·C to + 70·C
Storage Temperature ................. -65·Cto +160·C
Lead Temperature (soldering, 60 sec) ............... 300·C

Note 1: Input voltages may exceed the supply voltages, provided the input current is limited to ± 100I'A.
Note 2: Dissipation rating assumes device is mounted with all leads soldered to printed circuit board.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specitica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (Note 3, 7)
PARAMETER

CONDITIONS

UNITS

MIN

TYP

MAX

-000.0

±OOO.O

+000.0

Digital Reading

1000

Digital Reading

Zero Input Reading

Vm=O.OV
Full·Scale = 200.0mV

Ratiometric Reading

VIN = VREF , VREF = 100mV

999

RolI·Over Error (Difference in
reading for equal positive and
negative reading near full·scale)

- VIN = + VIN =: 200.0mV

-1

±0.2

+1

Counts

Linearity (Max. deviation from
best straight line fit)

Full·Scale = 200mV
or Full·Scale = 2.000V

-1

±0.02

+1

Counts

Common·Mode Rejection Ratio
(Note 4)

VCM = ±1V, VIN=OV
Full·Scale = 200.0mV

50

I'V/v

Noise (Pk·Pk value not exceeded
95% of time)

VIN = OV, Full·Scale = 200.0mV

15

I'V

Leakage Current

Input

=: OV

999/1000

1

10

pA

0.2

1

I'V/'C

VIN = 199.0mV, O'C 7V), the COMMON voltage will
have a low voltage coefficient (0.001 %1%), low output im·
pedance (::: 35!J), and a temperature coefficient typically less
than 80ppm/ o C.

v+

ICl7136

1M"

TO LCD
DECIMAL POINT
INTERSIL
1T1750
TO LCD
BACKPLANE

Figure 5. Simple Inverter for Fixed Decimal Point

The second function is a "lamp test:' When TEST is pulled
high (to V +) all segments will be turned on and the display
should read -1888. The TEST pin will sink about 10mA under
these conditions.

The limitations of the on·chip reference should also be
recognized, however, The reference templilrature coefficient
(TC) can cause some degradation in performance. Tempera·
ture changes of 2°C t08°C, typical for instruments, can give a
scale factor error of a count or more. Also, the COMMON
voltage will have a poor voltage coefficient when the total

Caution: In the lamp test mode, the segments have a con·
stant DC voltage (no square·wave). This may burn the LCD
display if maintained for extended periods.

4·111

II
~

ICL7136
y•

•• 1----....-+--\

lCL7138

TOlCD

DECIMAL
POINT

DECIMAL

L

POINTS

SELECT

oJ

TEST

Figure 8. Exclusive "OR" Gate for Decimal Point Drive

Figure 8. Clock Circuits

DETAILED DESCRIPTION-Digital Section

SYSTEM TIMING

Figure 7 shows the digital section for the 7136. An internal
digital ground is generated from a 6V Zener diode and a large
P channel source follower. This supply is made stiff to absorb
the relatively large capacitive currents when the backplane
(BP) voltage is switched. The BP frequency is the clock fre·
quency divided by 800. For three readings/secpnd this is a
6OH;zsquare·wave with a nominal amplitude of 5V. The
segments are driven at the same frequency and amplitude
and are in phase with BP when OFF, but out of phase when
ON. In all cases negligible DC voltage exists across the
segments. The polarity indication is "ON" for negative
analog inputs. If IN La and IN HI are reversed, this indication
can be reversed also, if desired.

Figure 8 shows the clock oscillator provided in the 7136.
Three basic clocking arrangements can be used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An RC oscillator using all three pins.
The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the four
convert·cycle phases. These are signal integrate (1000
counts), reference de·integrate (0 counts to 2000 counts),
zero integrator (11 counts to 140 counts *) and auto·zero
(910 counts to 2900 counts). For signals less than full·scale,
auto·zero gets the unused portion of reference de·integrate

* After an overranged conversion of more than 2060 counts, the
zero integrator phase will last 740 counts, and auto·zero will last
260 counts.

DISPLAY FONT

o ,:3'-:';S-:

*Three inverters.
One Inverter shown for clarity.

OSC1

OSC2

Figure 7. Digital Section

4·112

ICL7136
Reference Voltage

and zero integrator. This makes a complete measure cycle of
4000 (16,000 clock pulses) independent of input voltage. For
three readings/second, an oscillator frequency of 48kHz
would be used.

The analog input required to generate full-scale output (2000
counts) is: VIN = 2V REF . Thus, for the 200.0mV and 2.000V
scale, VREF should equal 100.0mV and 1.000V, respectively.
However, in many applications where the AID is connected to
a transducer, there will exist a scale factor other than unity
between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have
a full-scale reading when the voltage from the transducer is
0.682V. Instead of dividing the input down to 200.0mV, the
designer should use the input voltage directly and select
VREF = 0.341V. A suitable value for the integrating resistor
would be 330kO. This makes the system slightly quieter and
also avoids the necessity of a divider network on the input.
Another advantage of this system occurs when a digital
reading of zero is desired for VIN*O. Temperature
and weighing systems with a variable tare are examples. This
offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON
and the variable (or fixed) offset voltage between COMMON.
and IN LO.

To achieve maximum rejection of 60Hz pickup, the signal in·
tegrate cycle should be a multiple of the 60Hz period.
Oscillator frequencies of 60kHz, 48kHz, 40kHz, 33 Va kHz, etc.
should be selected. For 50Hz rejection, oscillator frequen·
cies of 662flkHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings/second) will reject both 50Hz and
60Hz (also 400Hz and 440Hz). See also A052.

COMPONENT VALUE SELECTION (See also A052)
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 6",A of quiescent current. They can supply
-1",A of drive current with negligible non-linearity. The in·
tegrating resistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full·scale, 1.8MO is near optimum, and
similarly 180kD for a 200.0mV scale.

TYPICAL APPLICATIONS
The 7136 may be used in a wide variety of config~r~~i?ns. The
circuits which follow show some of the pOSSibilities, and
serve to illustrate the exceptional versatility of these
A/D converters.

Integrating Capacitor
The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build·up will
not saturate the integrator swing (approx. 0.3V from either
supply). When the analog COMMON is used as a reference, a
nominal ± 2V full·scale integrator swing is fine. For three
readings/second (48kHz clock) nominal values for CINT
are O.047",F, for 1 reading/second (16kHz) 0.15",F. Of course, if
different oscillator frequencies are used, these values should
be changed in inverse propo~tion to maintain the same
output swing.
The integrating capacitor should have low dielectric absorption to prevent roll·over errors. While other types may be ade·
quate for this application, polypropylene capacitors give
undetectable errors at reasonable cost.

Auto-Zero Capacitor
Figure 9. 7136 Using the Internal Reference. Values shown are
for 200.0mV full·scale, 3 readings/sec, floating supply voltage
(9V battery).

The size of the auto·zero capacitor has some influence on the
noise of the system. For 200mV full·scale where noise il:! very
important, a 0.47",F capacitor is recommended. The 21 phase
allows a largeauto·zero capacitor to be used without causing
the hysteresis or overrange hangover problems that can occur with the ICL7126 or ICL7106 (see A032).

Reference Capacitor
A 0.1",F capacitor gives good results in most applications.
However, where a large common·mode voltage exists (i.e., the
REF LO pin is not at analog COMMON) and a 200mV scale is
used, a larger value is required to prevent roll·over error.
Generally, 1.0",F will hold the roll·over error to 0.5 count in this
instance.

Oscillator Components
For all ranges of frequency a 50pF capacitor is recommended
and the resistor is selected from the approximate equation
f - 0.45/RC. For 48kHz clock (3 readings/second), R =180kO,
for 16kHz, R = 560kO.

Figure. 10. 7136 with an External Band·Gap Reference (1.2V Type).
IN LO is tied to COMMON, thus establishing the correct common·
mode voltage. COMMON acts as a pre·regulator for the reference.
Values shown are for 1 reading/sec.

4-113

II
~.

ICL7136
TYPICAL APPLICATIONS (Continued)
'-'

To pin 1
40

aSCi

'-'

.00k0

OSC2

REF HI
REFLO
C REF
C REF

/

SOpF

TEST

Ft=:5=o.'"F

1Mn

INHI

IPO.01/,f

C REF

IN

.., ~

-5V

0,
C,

}TODISPLAY

G,

}ODISPLAV

G,

I - - - TO BACKPLANE

8P

2.

EJ..--.,:..

TO BACKPLANE

2'

Figure 11. Recommended Component Velues for 2.000V Full·
Scale, 3 Readings/Sec. For 1 reading/sec, change C,NT , Rose to
values of Figure 10.

Figure 12. 7136 with Zener Diode Relerence. Since low TC zeners
have breakdown voltages -6.8V, diode must be placed across the
total supply (10V). As In the case of Figure 11, IN LO may be tied to
COMMON.
~T~.~PI~n~.~------------------~V+

To pin 1
40

40

OSC 1

OSC1

OSC2LJ--~VV~--~

OSC2LJ---J~Ar---'

OSC3[)------II----~

TEST

-

'80kG

BUFF
INT
V-

0.047",F

5V

+

.O.01~F

0.33 F

A·Z

C,

II

/1Mn 'oj .....V
1MH

IN HI
INLO

IN

1.8M!l

..,

Do.'"FI

.m:'O

COMMON

+

O.10/olF

G,

BP

\.;1

REF HI
,REF LO

24OkO

CAEF

COMMON
INLO
A,z
BUFF
INT
V-

Set Yre' '" 100.OmV

50pF

TEST

V+

250kO

,A", .A

OSC2
QBe3

Set Yref = 1.000V

ose3

To pin 1
40

OSC1

set Vref '" 10D.OmY

OSC 3 D - - - - - I l r - - - - '
TEST

50pF

/

SOpF

"1'3=======:::,-

REF HI [)------~-."
REF LO [)------,-~J\I\I\,"""'N..,.."VV\,..._O+5V
C REF
27kG

REF
REF LO[
CREF
CREF

C REF

COMMON

COMMONO------~

IN HI [)-------+----:~=,!VV\r_--------+------'
INT

IN~()!~~{Xr_----+----_+.2=.--------~
L ____________ - - - - - - - - - - - - - - - - - - - v-

Figure 3. Analog Section of 7137

4-118

3 of 8

ICL7137
4. Zero Integrator Phase
regulate « 7V). These problems are eliminated if an external
reference is used, as shown in Figure 4.

The final phase is zero integrator. First, input low is shorted
to analog COMMON. Second, the reference capacitor is
charged to the reference voltage. Finally, a feedback loop is
closed around the system to input high to cause the inte·
grator output to return to zero. Under normal conditions, this
phase lasts for between 11 to 140 clock pulses, but after a
"heavy" overrange conversion, it is extended to 740 clock
pulses.

v+

v+
v+

V+ REF

HI
6.8 VOLT
ZENER

1.2 VOLT
REFERENCE
(INTERSIL ICL8069)

ICL7137

ICL7137

DIFFERENTIAL INPUT

REF LO
COMMON

The input can accept differential voltages anywhere within
the common-mode range of the input amplifier; or specifically from 0.5V below the positive supply to lOV above the negative supply. In this range the system has a CMRR of 90dB
typical. However, since the integrator also swings with the
common-mode voltage, care must be exercised to assure the
integrator output does not saturate. A worst case condition
would be a large positive common-mode voltage with a near
full-scale negative differential input voltage. The negative
input signal drives the integrator positive when most of its
swing has been used up by the positive common-mode voltage. For these critical applications the integrator swing can
be reduced to less than the recommended 2V full-scale swing
with little loss of accuracy. The integrator output can swing
within 0.3V of either supply without loss of linearity.

v(b)

(a)

Figure 4. Using an External Reference

Analog COMMON is also used as the input low return during
auto-zero and de-integrate. If IN LO is different from analog
COMMON, a common-mode voltage exists in the system and
is taken care of by the excellent CMRR of the converter.
However, in some applications IN LO will be set at a fixed
known voltage (power supply common for instance). In this
application, analog COMMON should be tied to the same
point, thus removing the common-mode voltage from the
converter. The same holds true for the reference voltage.
If the reference can be conveniently referred to analog
COMMON, it should be since this removes the commonmode voltage from the reference system.

DIFFERENTIAL REFERENCE
The reference voltage can be generated anywhere within the
power supply voltage of the converter. The main source of
common·mode error is a roll·over voltage caused by the reference capacitance losing or gaining charge to stray capacity
on its nodes. If there is a large common-mode voltage, the
reference capacitor can gain charge (increase voltage) when
called up to de-integrate a positive signal but lose charge
(decrease voltage) when called up to de-integrate a negative
input signal. This difference in reference for (+) or (-) input
voltage will give a roll-over error. However, by selecting the
reference capacitor large enough in comparison to the stray
capacitance, this error can be held to less than 0.5 count for
the worst case condition (see Component Value Selection).

Within the IC, analog COMMON is tied to an N channel FET
which can sink 100l'A or more of current to hold the voltage
3.0V below the positive supply (when a load is trying to pull
the common line positive). However, there is only 11'A of
source current, so COMMON may easily be tied to a more
negative voltage, thus overriding the internal reference.
TEST
The TEST pin is coupled to the internal digital supply through
a 500n resistor, and functions as a "lamp test' When TEST is
pulled high (to V +) all segments will be turned on and the
display should read -1888. The TEST pin will sink about
10mA under these conditions.

ANALOG COMMON

DETAILED DESCRIPTION-Digital Section

This pin is included primarily to set the common-mode
voltage for battery operation or for any system where the input signals are floating with respect to the power supply. The
COMMON pin sets a voltage that is approximately 3.0V more
negative than the positive supply. This is selected to give a
minimum end-of-life battery voltage of about 6V. However,
analog COMMON has some of the attributes of a reference
voltage. When the total supply voltage is large enough to
cause the zener to regulate (> 7V), the COMMON voltage will
have a low voltage coefficient (0.001 %1%), low output impedance (::: 35n), and a temperature coefficient typically less
than 80ppm/oC.

Figure 5 shows the digital section for the 7137. The segments
are driven at 8mA, suitable for instrument size common
anode LED displays. Since the 1000 output (pin 19) must sink
current from two LED segments, it has twice the drive
capability or 16 mAo The polarity indication is "ON" for
negative analog inputs. If IN LO and IN HI are reversed, this
indication can be reversed also, if desired.
Figure 6 shows a method of increasing the output drive current, using four DM7407 Hex Buffers. Each buffer is capable
of sinking 40mA.

The limitations of the on-chip reference should also be
recognized, however_ The reference temperature coefficient
(TC) can cause some degradation in performance. Temperature changes of 2°C to 8°C, typical for instruments, can give a
scale factor error of a count or more. Also, the COMMON
voltage will have a poor voltage coefficient when the total
supply voltage is less than that which will cause the zener to

4-119

SYSTEM TIMING
Figure 7 shows the clock oscillator provided in the 7137.
Three basic clocking arrangements can be used:
1. An external oscillator connected to pin 40.
2. A crystal between pins 39 and 40.
3. An RC oscillator using all three pins.

I]
"...
•

ICL7137
DISPLAY FONT

,.

-: ::: '3

u"

"

,-,1-'- ,-,1-'- ',."'I~'.•
d

---------,

I

I
I

I

I
I
I
I
I

TYPICAL SEGMENT OUTPUT

I
I

-----+--------~~----------_+----~_+--~--~------~v+
37

TEST
I

SOO

II

n

I

~---+~~~---+~~-------------------~-----------~------------------~------~~~~ ~~~~~~
'Three inverters.
One inverter shown for clarity.

esc 1

OSC2

OSC 3

Figure 5. Digital Section

1300
1300

L

oJ

1300

~

SEG~~NTSi
I
I

Figure 6. Display Buffering for Increned Drive Current

Figure 7. Clock Circuits

The oscillator frequency is divided by four before it clocks the
decade counters. It is then further divided to form the four
convert·cycle phases. These are signal integrate (1000
counts), reference de·integrate (0 counts to 2000 counts),
zero integrator (11 counts to 140 counts') andauto·zero
(910 counts to 2900 counts). For signals less than full·scale,
auto·zero gets the unused portion of reference de·integrate
and zero integrator. This makes a complete measure cycle of
4000 (16,000 clock pulses) independent of input voltage. For
three readings/second, an oscillator frequency of 48kHz
would be used.

should be selected.. For 50Hz rejection, oscillator frequen·
c.ies of 662fJkHz, 50kHz, 40kHz, etc. would be suitable. Note
that 40kHz (2.5 readings/second) will reject both 50Hz and
60Hz (also 400Hz and 440Hz). See also A052.

To achieve maximum rejection of 60Hz pickup, the signal in·
tegrate cycle should be a multiple of the 60Hz period.
Oscillator frequencies of 60kHz, 48kHz, 40kHz, 33 V, kHz, etc.
• After an overranged conversion of more than 2060 counts. the
zero integrator phase will last 740 counts. and auto·zero will last
260 counts.

COMPONENT VALUE SELECTION (See also A052)
Integrating Resistor
Both the buffer amplifier and the integrator have a class A
output stage with 6p.A of quiescent current. They can supply
-1p.A of drive current with negligible non·linearity. The in·
tegratingresistor should be large enough to remain in this
very linear region over the input voltage range, but small
enough that undue leakage requirements are not placed on
the PC board. For 2V full·scale, 1.8MO is near optimum, and
similarly 180kO for a 200.0mV scale.

4-120

ICL7137
Integrating Capacitor

TYPICAL APPLICATIONS

The integrating capacitor should be selected to give the
maximum voltage swing that ensures tolerance build-up will
not saturate the integrator swing (approx. 0.3V from either
supply). When the analog COMMON is used as a reference, a
nominal ± 2V full-scale integrator swing is fine. For three
readings/second (48kHz clock) nominal values for C INT
are 0.047/,F, for 1 reading/second (16kHz) 0.15/,F. Of course, if
different oscillator frequencies are used, these values should
be changed in inverse proportion to maintain the same
output swing.

The 7137 may be used in a wide variety of configurations. The
circuits which follow show some of the possibilities, and
serve to illustrate the exceptional versatility of these
AID converters.
TOPlnl~

Set Vrel - lOO.OmY

0-----.'

/

D---t-.J\!V'v--V'vv----.---<>+5v
220kfl
1M!!

The integrating capacitor should have low dielectric absorption to prevent roll-over errors. While other types may be adequate for this application, polypropylene capacitors give
undetectable errors at reasonable cost.

D---'--;!;oO".01U,F-/V'vv---<>IN

D~~------;----<>-5v

Auto·Zero Capacitor
_ _~i?,~~-------------oov

The size of the auto-zero capacitor has some influence on the
noise of the system. For 200mV full-scale where noise is very
important, a 0.47/,F capacitor is recommended. The ZI phase
allows a large auto-zero capacitor to be used without causing
the hysteresis or overrange hangover problems that can occur with the ICL7107 or ICL7117 (see A032).

Figure 8. 7137 U,Sing the Internal Reference. Values shown are for
200.0mV full·scale, 3 readings/sec. IN LO may be tied to either
COMMON for inputs floating with respect to supplies, or GND for
single ended, inputs. (See discussion under Analog COMMON.)
To pin 1

40

Reference Capacitor

OSC 1

560kn

osc 2

Set Vrel

OSC 3
TEST

A O.l/,F capacitor gives good results in most applications.
However, where a large common-mode voltage exists (i.e., the
REF LO pin is not at analog COMMON) and a 200mV scale is
used, a larger value is required to prevent roll-over error.
Generally, 1.0/,F will hold the roll-over error to 0.5 count in this
instance.

50pF

20k!)

REF HI

,.
200kn

100.0mV

27kn

v+

REF 1..0
C REF

C REF

COMMON
IN HI
IN LO

180kn

BUFF

Oscillator Components

INT

For all ranges of frequency a50pF capaQitor is recommenqed
and the resistor is selected from the approximate equation
f - 0.45/RC. For 48kHz clock (3 readings/second), R = 180kf!,
while for 16kHz (1 reading/sec), R 560kf!.

IN

O.OlILF
O.47j.!F

A·Z

O.15iJF

v-

}TO DISPLAY

_ _~~21--------------------<>OV

=

Figure 9. 7137 with an External Band·Gap Reference (1.2V Type). IN
LO is tied to COMMON, thus establishing the correct commonmode voltage. COMMON acts as a pre·regulator for the reference.
Values shown are for 1 reading/sec,

Reference Voltage
The analog input required to generate full-scale output (2000
counts) is: V IN 2V REF . Thus, for the 200.0mV and 2.000V
scale, V REF should equal 100.0mV and 1.000V, respectively.
However, in many applications where the A/D is connected to
a transducer, there will exist a scale factor other than unity
between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have
a full-scale reading when the voltage from the iransducer is
0.682V. Instead of dividing the input down to 200.0mV, the
designer should use the input voltage directly and select
V REF 0.341V. A suitable value for the integrating resistor
would be 330kf!. This makes the system slightly quieter and
also avoids the necessity of a divider network on the input.
Another advantage of this system occurs when a digital
reading of zero is desired for VIN';cO. Temperature
andweighing systems with a variable tare are examples. This
offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON
and the variable (or fixed) offset voltage between COMMON
and IN LO.

=

'-'

To pin 1
40

OSC 1

180kn

asc 2
asc 3

Set Vrel '-- 1.OOOV

,.

50~F

TEST
REF HI

REF LO
C REF
C REF
COMMON
IN HI
IN 1..0

=

==S=0.l/Jf

240kn
1Ml)

':;:O.OlI'F

8UA~! 1=
lNT

250kn

h.

~;8
A, bl
C~

G:~g

IN

O.4711F

~.,l,8M"j
O.047/-lF

v-

}TO DISPLAY

ov

21

Figure 10. Recommended Component Values for 2.000V Full·
Scale, 3 Readings/Sec. For 1 reading/sec, change CINT, Rose to
values of Figure 9.

4·121

II
~

ICL7137
TYPICAL APPLICATIONS (Continued)

.

To pin 1
~

40

~:~~F

To pin 1
40
~

REF HI
REF LO

10k!l

po."Fl·

COMMON
IN HI
IN LO

ase3

\~

SOpf

CREF
C REF

OSC2

Set Vret '" 100.0mV

OSC3
TEST

INT

v-

C REF

e REF

IN

A·Z

180kn

BUFF

INT
Y

5V

.~

+5V

1MJ!
~O.01p.F

R

.

IN

0.47/1F..JL

.

180kn

G,

C,

'"

Yr.' '" 100.OmV

2OkO..a..Ll00kllJ 27kO
~ ".2V (ICL8069)

PO.l.

COMMON
INHI
INLO

+

A'
0,
GNP

/

REF HI

Il.

.

A·Z

Set

REF LO

'5V

/,Mll'j ~6.8 V
1MU

BUFF

.
50pF

TEST

-.-T 0 •Ol lif
0.47p.F

osc 1

C,
AJ
G,
GNP

}TO PISPLAV

.,

ov

}TOOISPLAV

.,

ov

Figure 12. 7137 Operated from Single + 5V Supply. An external
reference must be used in this applipation, since the voltage
between V + and V - is insufficient for correct operation of the in·
ternal reference.

Figure 11. 7137 with Zener Diode Reference. Since low TC zeners
have breakdown voltages - 6.BV, diode must be placed across the
total supply (10V). As in the case of Figure 9, IN LO may be tied to
COMMON.

-'T~o~Pi~n"---------------------?Y'
QSel
OSC2

40

OSC3[J-----iI----J
TEST
SOpF
REF HI [ J - - - - - - - - - - - - - ,

REF LO [ J - - - - - - - -______
C REF
C REF

COMMON
IN HI [ J - - - - - - - - - . . :
IN

~.~ E5=;R';N,;=fl~0.I47';:'"F:~----'

BUFF

iNT [J----:::III---J

}TO DISPLAV

Figure 13. Measuring Ratiometric Values of Quad Load Cell. The
resistor values within the bridge are determined by the desired
sensitivity.

v'

+5V

40
Y+
01

Cl
81
Al
Fl
Gl

ICl7137

.,

To .
logic

v+

Vee
VPTAT

ICl8073/4

12K!!

VIN HI

VREF

_'gCJll
I __1._1

VREF HI

VZERO

VINLO

D.
C2
8.

OSCl

ose2
OSC3
TEST
AEfHI

REFlO
CREF
CAEF
COMMON
INHI
INLO
AlZ
BUFF

INT

vVREF LO

GND

ov

vFigure 14. Basic Digital Thermometer. Both the ICLB073 (0C) and
ICL8074 (OF) contain all necessary offset and reference (scalefactor) voltages to allow a direct·reading thermometer to be con·
structed without the need for external adjustments. Component
values for 200mV full-scale should be used with the ICLB073, and
(ideally) 170mV full-scale for the ICLB074.

Figure 15. Circuit for developing Underrange and Overrange
signals from outputs. The LM339 is required to ensure logic com·
patibility with heavy display loading.
'Values depend 011 clock frequency. See Figures 8, 9 and 10.

4-122

ICL7137
TYPICAL APPLICATIONS (Continued)
~~~p~ln~I'-----------~----~----S-C'-I'-I'-CI-O'-'-dIU-'-'--------------------~+5V
OSC1

40

(Yr.' '" 100mV lor AC to AMS)
180kO

OSC 2

10.u F

~~~~ o.---.5;n.OP'"FIt----'

REF HI

0.----------.

REF LO O------~-'Vv_;,-'VIIV---'
C REF
IOkO
220kO
C REF
COMMON 0 - - - - '
IN HI

0--------------+--------'

IN~~~~O.4~~~F~~~~~--~----_r+-r_~Ar;r~~~~--+:~~~----t_--'
BUFF

180kU

O.22 .. F

21

Figure 16. AC to DC Converter with 7137

APPLICATION NOTES

7137 EVALUATION KITS

A016 "Selecting AID Converters;' by David Fullagar.
A017 "The Integrating AID Converter;' by Lee Evans.
A018 "Do's and Dont's of Applying AID Converters;' by Peter
Bradshaw and Skip Osgood.
A019 "4 Vz·Digit Panel Meter Demonstratorllnstrumentation
Boards;' by Michael Dufort.
A023"Low Cost Digital Panel Meter Designs;' by David
Fullagar and Michael Dufort.
A032"Understanding the Auto·Zero and Common·Mode
Behavior of the ICL7106/7/9 Family;' by Peter Bradshaw.
A046"Building a Battery·Operated Auto Ranging DVM with
the ICL7106;' by Larry Goff.
A047"Games People Play with Intersil's AID Converters;'
edited by Peter Bradshaw.
A052"Tips for Using Single·Chip 3Vz·Digit AID Converters;'
by Dan Watson.

After purchasing a sample of the 7137, the majority of users
will want to build a simple voltmeter. The parts can then be
evaluated against the data sheet specifications, and tried
out in the intended application.

4-123

To facilitate evaluation of this
unique circuit, Intersil is of·
fering a kit which contains all
the necessary components to
build a 3Vz·digit panel meter.
With the ICL7137EV/Kit, an
engineer or technician can
have the system "up and run·
ning" in about half an hour.
The kit contains a circuit
board, LED display, passive
components, and miscella·
neous hardware.

II

ICL7145
16.. Bit IlP.. Compatible
Multiplying D/A Converter

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•

The ICL7145 combines a four·quadrant multiplying DAC us·
ing thin film resistors and CMOS circuitry with an on·chip
PROM·controlled correction circuit to achieve 0.003%
linearity without laser trimming.

16·bit resolution
High Iinearity-0.003% FSR
Microprocessor compatible with buffered inputs
Bipolar application requires no external resistors
Output current settling time 3"s max (1.0"s typ)
Low linearity and gain temperature coefficients
(1ppm/OC typ)
• Low power dissipation
• F~II four·quadrant multiplication
• Full temperature range operation

,Microprocessor bus interfacing is eased by standard
memory WRite cycle timing and control signal use. The input
buffer register is loaded with the 16·bit input, and directly
controls the output switches. The register is transparent if
WR and CS are held low.
The ICL7145 is designed and programmed for bipolar opera·
tion. There is an offset resistor to the output with a reference
input which should be connected to - VREF , giving the DAC a
true.2's complement input transfer function. Two extra
resistors to facilitate the reference inversion are included on
th,e chip, so that only an external op amp is needed:

II
ORDERING INFORMATION
NON·LlNEARITY .

0.,.0.0.6%
0..0.03%

PIN CONFIGURATION

TEMPERATURE RANGE
O°C TO

+ 70°C L

ICL7145JCJI
ICL7145KCJI

I
I

- 25°C TO + 85°C
ICL7145JIJI
ICL7145KIJI

Package: 28·pin CERDIP only

CHIP TOPOGRAPHY
D11

D.o

D. D8

D7 D.

D5 D.

mm

4·124

(outline dwg JI)

ICL7145
ABSOLUTE MAXIMUM RATINGS

(Note 1)

Supply Voltage V + to DGND ............... - O.3V to 7.5V

Storage Temperature ................. - 65°C to + .150°C
Power Dissipation (Note 2) ..................... 500mW
derate above 70°C@ 10mW/oC
Lead Temperature(soldering, 10seconds) .......... 300°C

VREF,RoFS,R'NV,RFBtoDGND ................... ±25V
Currentin AGND F, AGND s ....................... 25mA
DN, WR, CS, PROG, lOUT,
AGNDF,AGND s .................. -O.3VtoV+ +O.3V
Operating Temperature
ICL7145C ............................ O°Cto + 70°C
ICL71451 .......................... -25°Cto +85°C

Note 1: All voltages with respect to DGND.
Note 2: Assumes all leads soldered or welded to printed circuit
board.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS

v+ = + 5V, VREF = + 5V, TA = + 25°C unless otherwise specified.
LIMITS

PARAMETER

SYMBOL

CONDITIONS

UNIT
MIN

I
I

J

(Notes 3 and 4)

K

0.003

(Notes 3 and 4)

Non-Linearity Temperature Coefficient

Operating Temperature Range

l
I

Bits
0.006

Differential Non-Linearity

Gain Error

MAX

16

Resolution
Non·Linearity

TYP

J

0.003

% FSR

1

ppmrC
0.04

(Notes 3 and 4)

K

% FSR

0.02

% FSR
ppm/oC

Gain Error Temperature Coefficient

Operating Temperature Range

Zero Output Offset

TA = +25°C
Operating Temperature Range

10

PSRR

TA = + 25°C, V+ =5v ±10%

1

20

1

3

~s

ZREF

VREF

6

kO

COUT

DN=AIIOs
DN =AI11s

Power Supply Rejection Ratio

Voz

1
10

Output Current Settling Time
Reference Input Resistance
Output CapaCitance

Output Noise

3
110

Low State Input

V,N,

Operating Temperature Range

High State Input

V,Nh

Operating Temperature Range

IUN

o ::s;

ppmlV

pF

260

Equivalent Johnson Resistance

mV

kO

7
0.8

V
Logic Input Current

V1N ::s; V+

Logic Input CapaCitance

CUN

Supply Voltage Range

v+

Functional Operation

Supply Current

1+

Excluding Ladder

2.4
-1.0

1.0

~A

pF

15
4.5
0.5

5.5

V

1.2

mA

Note 3: Full·Scale Range (FSR) is 10V (± 5V).
Note 4: Using internal feedback and reference inverting resistors.

AC ELECTRICAL CHARACTERISTICS v+
PARAMETER

SYMBOL

Chip Select-WRite Set·Up Time

tcws

Chip Select·WRite Hold Time

=

+ 5V, TA =

+ 25°C, see Timing Diagram.

CONDITIONS

MIN

TYP

MAX

tCWh

a
a

Write Pulse Width Low

tiNA

200

Data-WRite Set·Up Time

tows

200

Data·WRite Hold Time

tOWh

0

4-125

UNIT

ns

ICL7145

Timing Diagram

DEFINITION OF TERMS
Table 1. Pin Assignment and Function Description

PIN
1

NAME

DESCRIPTION

Do
D,

Bit 0

2
3

D2

Bit 2

4

Do
D4

Bit 3
Bit 4

D5

Bit 5

D6
D,

Bit 6

DB
Dg

Bit 8

5
6
7
8

9
10
11
12
13

D,o

Bit 1

Bit 7
Bit 9
Bit 10
Bit 11

14

D"
0'2
, D'3

15

D'4

Bit 14

16

D'5
PROG

Bit 15

17
18

Least Significant Bit
-----------

NON·LlNEARITY: Error contributed by deviation of the DAC

transfer function from a best straight line function. Normally
expressed as a percentage of full·scale range. For a multiply·
ing DAC, this should hold true over the entireV REF range.
RESOLUTION: Value of the LSB. For example, a unipolar con·
verter with n bits has a resolution of (2 - n) (V REF ). A bipolar
converter of n bits has a resolution of [2 -(n -1)] [VRE,,].Resolu·
tion in no way implies linearity.
SETTLING TIME: Time required for the output function of the
DAC to settle to within 1/2 LSB for a given digital input

Input
Data
Bits
(High = True)

stimulus, i.e., 0 to full·scale.
GAIN: Ratio of the DAC's operational amplifier output volt·

age to the nominal input voltage value.

DETAILED DESCRIPTION

Bit 12
Bit 13

----------Most Significant Bit

Used for programming only. Tie to + 5V
for normal operation.

.19

VAEF
R,NV

Summing node for inverting amplifier.

20

ROFS

Bipolar offset resistor, to - VAEF.

21

RFB

Feedback resistor for voltage output
applications.
Digital GrouND return.

VAEF input to ladder.

22

DGND

23

AGNDF

Analog GrouND force line. Use to carry
current from internal Analog GrouN D
connections. Tiedlinternally to AGNDs .

24

AGNDs

Analog GrouND sense line. Reference
point for external circuitry. Pin should
carry minimal current. Tied internally io
AGNDF.

25
26

lOUT
V+

Current output pin.
Positive supply voltage.

27

CS

Chip Select (active low). Enables writing
to reg ister.

28

WR

WRite (active low). Writes into register.
Equivalent to CS.

The ICL7145 consists of a 16·bit primary DAC, PROM
controlled correction DACs, the input buffer registers, and
the microprocessor interface logic. The 16·bit primary DAC is
an R·2R thin film resistor ladder with N·channel MaS SPDT
current steering switches. Preci.se balancing of the switch
reSistances, and all other resistors in the ladder, results in ex,
cellent temperature stability.
The high linearity is achieved by programming a floating
polysilicon gate PROM array which controls the correction
DAC. The most significant bits of the DAC register address
the PROM array, whose outputs control a 12·bit linearity cor·
rection DAC. Thus for every combination of the primary
DAC's most significant bits a different C·DAC code is
selected, allowing correction of superposition errors caused
by bit interaction on the primary ladder's current bus and by
voltage non-linearity in the feedback resistor. Superposition
errors cannot be corrected by any method that corrects in·
dividual bits only, such as laser trimming. Since the PROM
programming occurs in packaged form, it corrects for
resistor shifts caused by the thermal stresses of packaging,
unlike wafer·level trimming methods. Since the thin film
reSistors do not suffer laser trimming stresses, no degrada·
tion of time·stability results.
Also controlled by the onboard PROM, the 6·bit G·DAC
reduces gain error to less than 0.02% FSR by diverting to
analog ground up to 2% of the c.urrent fI()wing in RFB.

4,126

ICL7145
VREF

R

R

R

ROFS

RoNV

R

RFB

2R

2R

2R

~rt--~~------~r-~~+-~~-+--~+-----------~--~---r~~~UT
L-~----4-~---+--------~---+-*----+-~---+------~~-t------~~-oAGN~

AGNIlF

C·DAC

r-----~-------JH'DECODE

PROM

--------{)PRoG

~~--~--~~~~==--~---=~l-----------------o~
~-r'-~~~~~~~~~~-r~~~------------------oWR
08·

•

•

•

•

• 015

Figure 1. ICL7145 Functional Diagram

APPLICATIONS

The input circuits of some high speed op amps will sink large
currents to their negative supply during power up and power
down. The Schottky diode at lOUT limits any negative going
transients to less than - O.4V, avoiding the SCR latch-up
which could result if significant current was injected into the
parasitic diode between lOUT and V - of the ICL7145. This
diode is not needed when using the ICL7650 ultra low Vas op
amp.

Bipolar Operation
The circuit configuration for the normal bipolar mode opera·
tion of the ICL7145 is shown in Figure 2. The 2's complement
input and positive and negative reference voltage values
allow full four·quadrant multiplication. Amplifier A3, together
with the internal resistors R1NV1 and R1NV2 , forms a simple
voltage inverter circuit to generate - VREF forthe ROFS offset
input pin. This will give the nominal "digital input code/ana·
log output value" relationship of Table 2.

Offset Adjustment
1. Connect all data inputs and WR and CS to DGND.
2. Adjust the offset zero-adjust of the operational amplifier
A 2 , if used, for < ± 50/LV atAGND s.
3. Set data to 0000 .... 000 (all low). Adjust the offset zeroadjust of output operational amplifier AI for < ± 50/LV at
lOUT. VOUT will be offset from OV by the bipolar zero error of
±10mV.

Table 2. Code Table- Bipolar Operation
DIGITALIN PUT

o
o

ANALOG OUTPUT

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

0 0 0 0 0

o

0 0 0 0

0 0 0 0 0 0 0 0

o0

0

o0 o0
o0 o0

- VREF (112'5 )

0

0

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1

o

1

000 0

0 0 0 0000000

o

o0 o

- VREF (1 _1/2 15 )

1

1

0 0 0 0 0 0 0 0 0 0

VREF (1/2'5 )

The bipolar zero error may be trimmed out by adjusting the
offset of A 3. The bipolar zero error can be as large as 10mV,
but has a typical tempco of only 10/LV/oC.

VREF (1 _112'5)
VREF

Amplifier AI is the output amplifier. An additional amplifierA 2
may be used to force AGND F if the ground reference point is
established elsewhere than at the DAC, as in Figure 3.
A feedback compensation capacitor, C F, improves the settling time by reducing ringing. This capacitor is normally in
the 10pF-40pF range, depending on layout and the output
amplifier selected. If C F is too small, ringing or oscillation
can occur when using an op amp with a high gain-bandwidth.
If C F is too large, the response of the output amplifier will be
overdamped and will settle slowly. Figure 6 shows the effect
ofC F·

4·127

Gain Adjustment
In many systems, gain adjustment will not be needed since
the gain of the ICL7145 is accurate to within 0.02% FSR.
When system gain must be adjusted, the low gain error limits
the required adjustment range to only slightly more than the
initial accuracy error of the reference. This is desirable since
external gain trims degrade the gain temperature coefficient
of a monolithic DAC. This degradation in the gain tempco
comes about because, although the internal resistors track
each other closely, they have a temperature coefficient of
resistance of approximately - 250ppm/oC.

ICL7145

VREF IN

16
15.

0

18

19

20

VREF
RINV1

RINV
RINV2

RoFS

V+
21

D'S(MSB)

RFB

D14
lOUT

DATA
INPUTS

25

ICL7145

o

1.

+5V 17

I

AGNDS~~----~~-------------L

Do(LSB)
PROG

AGNDF

Figure 2. Bipolar Operation, Four·Quadrant

VREF IN

16

D,S (MSB)

15

RFB

21

D14
lOUT

DATA
INPUTS

25

ICL7145

I -

AGNDs

24

/

(
\
Do (LSB)
+5V

17

\ - AGNDF

23

DGND 22

Figure 3. Operation with Forced Ground

4·128

VOUT

ICL7145
ladder switches. While this simplifies interfacing in nonmicroprocessor systems it may cause additional glitches in
some microprocessor systems. These small glitches will
occur if WR goes low before data is valid. Data must be valid
at the time WR goes low to avoid these additional glitches.

To increase VOUT , connect a series resistor of 2000 or less
between the A1 'output and the RFB terminal (pin 21). To
decrease VOUT , connect a resistor of 1000 or less between the
reference voltage and the VREF terminal (pin 18). These
resistor values result in a minimum of 1% FSR gain trim and
add about 3ppm/'C gain tempco. If only a small gain trim
range is needed, the resistor values should be reduced in
order to preserve the excellent 1ppm/'C gain tempco.

All digital interfaces can suffer from capacitive coupling between the digital lines and the analog section. There·are two
general precautions that will reduce the capacitive coupling
problem: 1) reduce stray capacitance between digital lines
and analog lines; and 2) reduce the number of transitions on
the digital inputs. Careful board layout and shielding can
minimize the capacitive coupling (see Figure 5, PCB layout).
The activity on the digital input lines can be reduced by using
external latches or Peripheral interface ICs between the microprocessor bus and the ICL7145. This will reduce the
number of tranSitions on the digital data and control lines of
the ICL7145, and thereby reduce the amount of digital noise
coupled into the sensitive analog sections.

Digital Interface
The ICL7145 has a 16-bit latch onboard and can interface
directly to a 16-bit data bus. Use external latches or peripheral ICs to interface to an 8-bit data bus, as shown in Figure 4.
To ensure that the data is written into the onboard latch, the
data must be valid 200ns before the rising edge of WR. The
on board latch is transparent, meaning that if WR and CS are
tied low, the input data is directly applied to the internal R-2R

2 LINE TO 4 LINE DECODER

WR

ICL7145

Figure 4. Interlace to 8-Bit Microprocessor

0"

00

,,0

--=---------

MSB

DIGITAL

INPUT
DATA

L~8

1

Printed Circuit Side of Card (Single' Sided Board)
Figure 5b_ Top Side with Component Placement

Figure 5a_ Printed Circuit Board Layout

4-129

ICL7145
Operational Amplifier Selection
The input offset voltage, input current, gain, and bandwidth
of the op amps used' affect the circuit performance. Since the
output impedance of lOUT varies with Hie digital input code,
A1'S input current will cause a code·dependent error at VOUT,
degrading the linearity. The input bias current should be
significantly less than 1 LSB current, which is about 10nA. In
a similar manner, any offset voltage in A1 will also cause
linearity errors. The offset voltage of the output amplifier
should be significantly less than 1 LSB, which is 1531'V.

ICL7650 or ICL7652 can be. used for A 1.Since thelCL7650f52
offset voltage is less than 51'V, no offset trimming is needed.
To get a full5V swing, ± 7.5V supplies should be used for the
ICL7650f52. Figures 6 and 7 show typical performance.
Amplifier A 3, which is used to generate the inverted
reference, needs only to have a stable offset and to be able to
drive a 3kO load. Since this is strictly a DC amplifier, the low
noise ICL7652 is an ideal choice. Any variation in the offset.
voltage of A3 will result in a drift in the bipolar zero, but will
not affect the linearity of the ICL7145.

The voltage output settling time is highly dependent on the
slew rate and gain·bandwidth of A 1, so for high speed opera·
tion a high speed op amp such as the HA2600 is recommend·
ed. For applications where high speed is not required, the

Amplifier A2 , used to generate a high quality ground, also
needs a low offset and the ability to sink about 2mA.

_t_
-t2v/DIV

VOLTAGE

OUTPUT

_t
5VIDIV

Figure 6. Voltage Output Settling with HA2525·5 Output Amplifier

Upper 50mV of a 10V Step

Figure 7. Voltage Output Settling with LF356 Output Amplifier

4·130

ICL7145
Ground Loops
Careful consideration must be given to ground loops in any
high accuracy system. The current into the analog ground
point inside the chip varies significantly with the input code
value, and the inevitable resistances between this point and
any external connection point can lead to significant voltage
drop errors. For this reason, two separate leads are brought
out from this point on the IC, AGND s and AGND F . The varying
current should be absorbed through the AGND F pin, and the
AGND s pin will then accurately reflect the voltage on the in·
ternal current summing point, as shown in Figure 8. Output
signals should ideally be referenced to the sense pin AGND s ,
as shown in the application circuits.

VREF

TRUE OIP NODE

::.:-.::.....----'I.--{) lOUT
LEAD
RESISTANCE

Multiplying Mode Performance

While the ICL7145 can perform full four·quadrant multiplica·
tion, full 0.003% linearity is guaranteed only at VREF + 5V.
This is because the voltage coefficient of resistance of the
R·2R ladder and the feedback resistor are significant at the
14· or 16·bit level. This effect is most significant at higher
voltages, and adds errors on the order of 0.01 % for a ± 10V
full·scale. While the ICL7145 is tested and specified for
VREF = + 5V, the R·2R ladder has the same voltage across it
when VREF
5V. Therefore, voltage coefficients do not add
any error with a - 5V VREF •

=

~;~~~~~~

AGNDS

•___________.///">-\===---'1.-0-+ OF ANALOG
~

I,

RES~~~NCE

SYSTEM

~GNO

\

AGNDF

TRUE ANALOG
LEAD
GROUND POINT RESISTANCE

=-

Figure 8. Eliminating Ground Loops

4·131

-::-

"~ii' ICL 7146

Complete
x~~(:J'!'~"
12·Bit Processor
"\"c:,,,,(7Compatible CMOS 'DAC
GENERAL DESCRIPTION

FEATURES
•

Low Impedance Voltage Output

•

Double·Buffered Processor Interface

•

Easy·To·Use Bipolar Offset

•

Multiplying Capability

•

On·Chip Trimmed Reference

•

7pSec Settling Time

•

No External Gain or Offset Adjustment
Required

0:

Low Power Dissipation 50mW
No Critical External Components

ORDERING INFORMATION
Part Number

Linearity

ICL7146LCJI
ICL7146L1JI
ICL7146KCJI
ICL7146KIJI
ICL7146JCJI
ICL7146JIJI

0.Q1%
0.02%
0.05%

Temperature
Range

o to

Package

+ 70·C

The ICL7146 is the first of a series of complete 12·Bit
CMOS DAC's. These DAC's feature all of the needed
support circuitry to interface to processors and give a
voltage output. Contained on the chip are two levels
of latches for double buffers, a trimmed reference, a
latch controller, and an output buffer amplifier. All
devices are accurately trimmed for both gain and off·
set so that no external trimming is required.
CMOS circuitry is used to keep the power dissipation
low, and with all devices contained on a single chip,
significant board size reductions, are possible. As an
alternative to this, many more analog channels could
be added to a board and still decrease power con·
sumption. Intersil's patented autostabilized op amp
construction eliminates drifts in the zero offset and
provides a fast (7 jtsec) settling time.

-40·Cto+85·C

o to

+ 70·C

- 40·C to + 85·C

o to

CERDIP

+ 70·C

- 40·C to + 8S·C

Processor interface is double-buffered with all 12-bits
being brought out. The first level of latches is divided
into 4 and 8 bit bytes with a 12 bit wide second buffer.
Data can be directly entered into any of the three buffers or the buffers can be operated separately.

BLOCK DIAGRAM
v-

AGNO

PIN CONFIGURATION

ROS

VOUT

CEXTA
'----oCEXTB

ALE

CS A1
WR AO

07 05 03 01
06 04 02 DO

4-132

ICL7148
Absolute Maximum Ratings (Note 1)
REFIN, RFB, ROS ......................... ± 25V
V+ ...................................... 6.2V
V- .................................... -9.0V
REFOUT, VOUT, CEXT,
AGND .................. V- -0.3VtoV+ + 0.3V
Digital Inputs .......... V + + 0.3V to DGND - 0.3V
Storage Temperature Range ..... - 65·C to + 150·C

Streses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
NOTE 1: All Voltages with Respect to DGND

Operating Characteristics

v + = 5V, V - = - 5V, Vref = 4.00V, TA = 25·C,
Parameter

Symbol

RL

= 20K, CL = 50pF

Test Conditions

Min_

Limits
Typ.

Max.

Unit

.05
.02
.01

% FSR
% FSR
% FSR

Bits

12

Resolution
Non Linearity J
K
L
Differential Linearity

LSB
± 3/4
± 1/2
± 1/2

J
K
L

Guaranteed Monotonic

±2
±1
±1

Gain Error

0.1

0.2

% FSR

Unipolar Zero Error

60

120

!-'V

0.025

0.05

% FSR

± 0.001

0.005

% FSRI
% V+
% FSRI
% V+

Bipolar Zero Code Error

RFB Connected to VOUT
Ros Connected to
-VREF

Positive Power Supply
Rejection Ratio

V+ = 4.5 to 5.5V
External Reference

Negative Power Supply
Rejection Ratio

V- = -4.5 to -5.5V
External Reference

0

± 0.001

Voltage Setting Time (Note 1)

To 1/2 LSB

7

10

!-,s

Feedthrough Error

VREF = BV p.p,
10 KHz Sine Wave

1

mV pop

Reference Input Resistance

- 55·C to 125·C

Internal Reference Voltage

5

10

20

KO.

-4.04

-4.00

-3.96

V

25

50

PPM of
FSR per
·C

Internal Reference Tempco

Positive Supply Voltage Range

V+

Functional Operation,
Internal or External
Reference

4.5

5.0

5.5

V

Negative Supply Voltage
Range

V-

Functional Operation,
External Reference

-4.5

-5.0

-7.5

V

Functional Operation,
Internal Reference

-4.75

-5.0

-7.5

V

Output Voltage Range

RFB con~ected to VOUT

Output Drive Current

±4
±2

4-133

V
mA

.D~Dll

ICL7146
Operating Characteristics (continued)

v+

= SV,

v-

= - SV, Vref = 4.00V, TA = 2S·C, RL = 20K, CL = SOpF

Parameter

,.

Symbol

Output Amp Bandwidth

.

Test Conditions

Min.

Slew Rate
Output Impedance

@D.C.

Reference Input Range
(Note 2)

For design use.
Linearity Guar. @4.0V

Limits
Typ.

Max.

Unit

2

MHz

2.S

V/I'.5

n

.02
±10

V

0.8

V

Logic Input Current

1

{tA

Logic Input Capacitance
(Note 1)

8

pF

4.0

S.O

mA

4.0

S.O

mA

SO

mW

Logic Low

VINL

Logic High

VINH

Positive Supply Current

±2.0

V

2.4

Inputs = OV or SV

Negative Supply Current
Power Dissipation

Input Code = S.OV
V+ =5.0V, V- = -5.0V

Gain Error Tempco

Internal Ref
External Ref

±30
-12

PPM of
FSR
·C

DIGITAL SWITCHING CHARACTERISTICS
Address WR Set-up Time

TAWS

100

nS

Address WR Hold Time

TAWH

0

nS

CS WR Set-up Time

TCWS

0

nS

CS WR Hold Time

TCWH

0

nS

Write Pulse Width

TWR

200

nS

Data Set-up Time

TOS

200

nS

Data Hold Time

TDH

0

nS

ALE Pulse Width

TLL

200

nS

Address-ALE Set-up Time

TAL

60

nS

Address-ALE Hol,d Time

TLA

40

nS

CS-ALE Set-up Time

TCL

30

nS

CS~ALE

TLC

SO

nS

TWL

0

nS

Hold Time

WR Trailing Edge to ALE

NOTE 1: Guaranteed by design, not 100% tested in production,
NOTE 2: External Op Amp Required for Vout > ± 4.0V

DETAILED DESCRIPTION
The ICL7146 is a monolithic 12-bit processor compatible CMOS DAC. It is a complete DAC containing a
DAC, a group of latches, a reference, digital control
circuitry and an op amp.

DAC. CMOS switches and low tempco thin film
resistors provide a stable output current proportional
to the input digital code. Two matched and trimmed
resistors are provided at the output for current to
voltage conversion and for offset generation in
bipolar operation.

A wide range of applications can be implemented
with the ICL7146 laser trimmed 12-bit multiplying

An on-chip precision auto-stabilized operational
amplifier is provided for current to voltage conver-

4-134

ICL7146
TIMING DIAGRAMS AND TRUTH TABLES
Non-Multiplexed Bus
TRUTH TABLE (ALE tied to V +)
TIMING DIAGRAM

CONTROL INPUTS
A1 AO CS WR
X
X
1
X
X
1
X
X

I-T,,--\-+TO•
0 1.0 0

OPERATION
No Operation Device Not
Selected

0

0

0

0

LOpd All Registers From
Data Bus

0

1

0

0

Load LSB Register From
Data Bus'

1

0

0

0

Load MSB Register From
Data Bus'

1

1

0

0

Load DAC Register From
LSB & MSB Register

DATA VAlIOI!?"?""""'''''''''''''''''''''''

TIMING FOR NON·MUL TlPLEXED ADDRESS BUS

'Data is latched on low to high transition of WR or cs.

Multiplexed Bus
TRUTH TABLE (ALE is latch control input; CS, AO &
A 1 are latched outputs)
TIMING DIAGRAM

CONTROL INPUTS
CS WR
1
X
1
X

OPERATION

A1

AO

X
X

X
X

0

0

0

0

Load All Registers From
Data Bus

0

1

0

0

Load LSB Register From
Data Bus

1

0

0

0

Load MSB Register From
Data Bus

1

1

0

0

Load DAC Register From
LSB & MSB Register

No Operation Device Not
Selected

TIMING FOR MULTIPLEXED ADDRESS BUS

sion. The auto zeroing technique utilized guarantees
extremely low offset and low gain drift over
temperature. Two inexpensive capacitors are required for the internal auto zero circuitry. Th op amp
has been left open loop for flexibility. The loop can be
closed by connecting Ros and Rfb to VOUT for full
scale voltages less than ± 4 volts. An external
amplifier can be closed in the loop for applications requiring larger output swing or current. An inexpensive buffer amplifier with no special input
characteristics can be used without any system
degradation. No external offset trimming is required
due to the auto zeroing circuitry.
A zener reference that can be trimmed for both out·
put voltage and temperature drift is provided. This
reference is capable of driving an extra load of 200!-,A
above the current required for the DAC ladder. This
allows the reference to be used for other devices iri
the system when required.
Latches on the chip are set up in two levels, the first
level connects to the data bus and is internally ar-

ranged as three groups of four latches each. The
decoding circuitry is designed so that the user may
address either the lower eight bits or the upper four
bits. This allows the user to hard wire the 4 MSB's
directly to the 4LSB's for easy interface to eight bit
processors. Or the DAC can be wired directly to a 12
bit or larger data bus. Following the two input latches
is another latch that is 12 bits wide. This makes the
ICL7146 double-buffered. By double buffering the in·
put of the DAC it is possible to interface the DAC to
an eight bit data bus and prevent the DAC from hav·
ing a major output glitch as the digital code changes.
With a single level of latches, say a 4 bit latch and an
8 bit latch connected to an 8 bit data bus the following would occur if an attempt was made to generate a
ramp. As the input code was incremented from
OOOHEX to OFFHEX an even stair case output would
occur. But to change the code to 100HEX the processor would either have to change to code to 000
and then to 100, or first to 1FF and then to 100. In the
first case the output would go to zero for a full processor cycle. And in the second case it would double

4-135

n
III

.U~UlL

ICL7146
its output value. Neither ofthese conditions are acceptable in a wide variety of applications. Hence the
need for double buffering.

Buffer control is handled by a decoder to ease processor interface requirements. Operation of the
decoder is shown in the truth table.

TYPICAL APPLICATIONS
Bipolar Output

TYPICAL APPLICATIONS
Unipolar Output

Offset Binary Code Table
Binary Number In
DAC Register
MSB
LSB
1111

1111

Code Table

1111

+ VREF

(2047)
2048

1000 0000 0001

+ VREF

(_1_)
2048

1000 0000 0000

OV

0111

1111

- VREF

0000 0000 0000

- VREF

1111

Binary Number In
DAC. Register
MSB
LSB

Analog Output, VOUT

1111

1111

1000 0000 0000
0000 0000 0001

CO~8)

e048 )

0000 0000 0001

- VREF

e

095 )
4096

C048)
= -1/2 VREF
4096
-VREF (_1)
4096
- VREF

OV

2048

+ 4V UNIPOLAR QUTPUT:

± 4V BIPOLAR OUTPUT:

..: [ i

1111

Analog Output, VOUT

;~ L.;.,r-T~_I_C. ;.L:_1_46";C"i"':':'A-.Jr/- _-.J. . ovgJ;:~TE
...

":' -4V

+sv

-sv

+sv

-5V

NOTE 1: Al should be selected or trimmed for low
offset voltage; Rl & R2 are 10KO reSistors
trimmed to a matching of 0.1 % or better.

+ 10V UNIPOLAR OUTPUT:

± 10V BIPOLAR OUTPUT:

(EXT)

NOTE 1: Al should be selected or trimmed for low
offset voltage; Rl & R2 are 10KO resi stors
trimmed to a matching of 0.1 % or better.

NOTE 1: A2 needs not to have a low offset voltage but it
must be fast (>8MHz) to insure stability.

NOTE 2: A2 needs not to have a low offset voltage but it
must be fast (>8MHz) to insure stability.

4-136

ICL7146
TYPICAL APPLICATIONS (Continued)

CHIP TOPOGRAPHY
04 05 06 07 Os 09 010011

R,

R,

YAf':FIN

=

VRr;FOUT (1

+ ~)
10k 5%

Ao
A1
ALE

USING INTERNAL REF FOR V REF >4V

4-137

AD7520.17530
AD7521 17531
10 & 12 Bit Monolithic
Multiplying DI A Converters
FEATURES

II..

GENERAL DESCRIPTION

• AD7520/ AD7530: 10 Bit Resolution; 8, 9 and 10 Bit
Linearity
• AD7521/ AD7531: 12 Bit Resolution; 8, 9 and 10 Bit
Linearity
• Low Power Dissipation: 20 mW (Max)
• Low Nonlinearity Tempco: 2 PPM of FSR/o C (Max)
• Current Settling Time: 500 n. to 0.05% of FSR
• Supply Voltage Range: +5V to +15V
• DTL/rTL/CMOS Compatible
• Full Input Static Protection
• 883B Processed Versions Available

The AD7520/AD7530 and AD7521/AD7531 are monolithic,
high accuracy, low cost 10-bit and 12-bit resolution,
multiplying digital-to-analog converters (cAC)'
INTERSIL thin-film on CMOS processing gives up to 10bit accuracy with DTLlTTLICMOS compatible operation.
Digital inputs are fully protected against static discharge
by diodes to ground and positive supply.
Typical applications include digital/analog interfacing,
multiplication and division, programmable power
supplies, CRT character generation, digitally controlled
gain circuits, integrators and attenuators, etc.
The AD7530and AD7531 are identical to the AD7520 and
AD7521, respectively, with the exception of output

r-____________________________________________T-____
Ie_a_k_ag_e__c_u_rr_e_n_t_a_nd
__f_ee_d_t_h_ro_u_9_h__
sp_e_c_if_ic_a_t_io_n_s_.____-,

FUNCTIONAL DIAGRAM
10Kn

VREF

10Kn

CHIP TOPOGRAPHY

10KO

10KH

SPOT
NMOS

IOUT2

SWITCHES

'-+--4+---4-i---~--..,.---<> loun
RFEE08ACK

(Switches shown for Digital Inputs "High")
(Resistor values are nominal)

PACKAGE IDENTIFICATION
AD7520

Suffix D: Cerdlp package
Suffix N: Plastic DIP package

PIN CONFIGURATION (Outline dwgs DE, PEl
TOPYIEW·

J N

AD7520 (AD7530)

1 11==:=:.

OND

3

BIT 1 (MSS)

4

13 BIT 10 (LSB)

ORDERING INFORMATION
Nonlinearity
0.2% IS-Bill

0.1% 19-13ill

0.05% 110-Bill

O'C 10 +70

BIT3 8

Temperature Range
-25' C 10 +85' C -55'C10 +125'C

AD7520JN
AD7530JN
AD7521JN
AD7531JN

AD7520JD
AD7530JD
AD7521JD
AD7531JD

AD7520SD

AD7520KN
AD7530KN
AD7521KN
AD7531KN

AD7520KD
AD7530KD
AD7521KD
AD7531KD

AD7520TD

AD7520LN
AD7530LN
AD7521LN
AD7531LN

AD7520LD
AD7530LD
AD7521LD
AD7531LD

AD7520UD

81T4

AD7S21 (AD7S31)

AD7521SD

GND 3
BIT 1 (MSB)

AD7521TD

BIT4 7

AD7521UD

4-138

1

BIT 12 (LSB)

AD7520/7530/7521 17531
ABSOLUTE MAXIMUM RATINGS (TA = 25° C unless otherwise noted)
Operating Temperatures
Y+ ............................................ +17Y
IN,KN,LNYersions ..................... 0°Cto+70°C
YAEF ......................................... ±25Y
JD,KD,LDYersions .................... -25°Cto85°C
Digital Input Yoltage Range .............. y+ to GND
SO, TO, UD Versions ................. -55°Cto+125°C
Output Yoltage Compliance ........... -100mY to Y·
Power Dissipation (package)
Storage Temperature .................. -65°Cto+150°C
up to +75°C .............................. 450 mW
derate above +75°C @ .................. 6 mW/oC
CAUTION: 1) The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy
electrostatic fields. Keep unused units in' conductive foam at all times.

2) Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and Rtb.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and fUnctional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

SPECIFICATIONS (Y+
PARAMETER
DC ACCURACY INote 1)
Resolution
Nonlinearity

= +15Y, YREF= +10Y, TA=25°C unless otherwise specified)

J
S
K
T
L
U

Nonlinearity Tempco
Gain Error INote 2)
Gain Error Tempco INote 2)
Output Leakage Current
leither output)
Power Supply Rejection
ACACCURACY
Output Current Settling
Time
Feedthrough Error
REFERENQE INPUT
Input Resistance INote 3)
ANALOG OUTPUT
Voltage Compliance
Iboth outputs)
Output Capacitance

Output Noise
Iboth outputs)
DIGITAL INPUTS
Low State Threshold
High State Threshold
Input Current
Ilow to high state)
Input Coding
POWER REQUIREMENTS
Power Supply Voltage Range

1+
Total Power Dissipation
lincluding the ladder)
NOTES:

AD7520
(AD7530)

AD7521
(AD7531)

10

12

UNITS

LIMIT

TEST CONDITIONS

FIG.

0.2 IS-Bit)

Bits
% of FSR

Max

S, T. U: over -55° C to =125° C

1

0.1 (9-Bit)

% of FSR

Max

0.05 110-Bit)

% of FSR

Max

2
0.3
10
200
(300)

PPM of FSR/o C
% of FSR
PPM of FSR/oC
nA

Max
Typ
Max
Max

±0.005

% of FSR/%

Typ

500

nS

Typ

To 0.05% of FSR IAII digital
inputs low to high and high to
low)

6

10

mV pp

Max

YREF = 20Y pp, 100kHz
150kHz) All digital inputs low

5

5k
10k
20k

n

Min
Typ
Max

~
-10V"VREF" = 10V

~

-10V"YREF" +10Y
Over the specified temperature
range
2

All digital inputs high.
IOUT1 at ground.

See absolute max. ratings
tOUT1 120
IOUT2 37
loun 37
IOUT2 120
Equivalent to 10kn
Johnson noise

pF
pF
pF
pF

0.8
2.4
1

V
V
p.A

Typ
Typ
Typ
Typ
Typ

Max
Min
Typ

All digital inputs high

4

All digital inputs low

4
3

Over the specified temp range

See Tables 1 & 2 on pages 4
and 5

Binary/Offset Binary

+5 to +15
5
2

V
nA
mA

20

mW

1. Full scale range IFSR) is 10V for unipolar and ±10V for bipolar modes.
2. Using internal feedback reSistor. RFEEDBACK.
3. Ladder and feedback resistor Tempco is approximately -150ppmfoC.

4-139

Typ
Max
Typ

All digital inputs at GND
All digital inputs high or low

IE

AD7520/7530/7521/7531
TEST CIRCUITS
NOTE: The following test circuits apply for the AD7520. Similar circuits can be used for the AD7530, AD7521 and AD7531.
VREF

1081T

,,
,

BINARY
COUNTER

• BIT 10
(lSB)

UNGROUNDED
SINE WAVE
GENERATOR
40Hz 2V p-p

AD7520

13
10K .01%

soak'

HOY
1 MEG

JU1
CLOCK

10K .01%

BIT 10
(LSB)

Figure 1. Non linearity

Figure 2. Power Supply Rejection

+11V (ADJUST FOR VOUT = OY)

+15V
1k

NC

+15

f '" 1kHz

,.,.

BW'" 1Hz

~'T 1 (MSB)

aUAN
TECH
MODEL
1340
WAVE
ANALYZER

15

100 mVp-p
1MHz

Figure 4. Output Capacitance

-'-15V

+15V

.;:V,"''''--_-,

51:' 1% SETTLING (1 mY)

EXTRAPOLATE

'"*..-.....,.,4~

14

8t: 0.03% SETTLING

t""rlse time

BIT 1 (MSS) 415

~=:J:

+~~ nIl..rt
DIGITAL INPUT

13

,.

13

+10 V

BIT 1 (MSB)

NC

A07520

Figure 3. Noise
VREF = 20 V p-p 130 kHz SINE WAVE

4'5

VOUT

OSCILLOSCOPE

5
AD7520

1

~"'iLSi;t':3
-;~..1
BIT '9 (LSe)

BIT 10 (lSe

GND

Figure 5. Feedthrough Error

Figure 6. Output Current SettlingTir'ne

DEFINITION OF TERMS
GAIN: Ratio of the DAC's operational amplifier output
voltage to the nominal input voltage value.

NONLINEARITY: Error contributed by .deviation of the
DAC transfer function from a best straight line function.
Normally expressed asa percentage of full scale range.
For a multiplying DAC, this should hold true over the
entire VREF range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREFI. A
bipolar converter of n bits has a resolution of [2-(n-l)]
[VREF]. Resolution in no way implies linearity.
SETTLING TIME: Time required forthe output function of
the DAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to Full Scale.

FEEDTHROUGH ERROR: Error caused by capacitive
coupling from VREF to outputwith all switches OFF.
OUTPUT CAPACITANCE: Capacityfromloun and IOUT2
terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears
on loun terminal with all digital inputs LOW or on IOUT2
terminal when all inputs are HIGH.

4-140

.D~D[l

AD7520/7530/7521 17531
GENERAL CIRCUIT INFORMATION
The AD7520 (AD7530l and AD7521 (AD7531) are
monolithic, multiplying D/A converters.Highly stable thin
film R-2R resistor ladder network and NMOS SPDT
switches form the basis of the converter circuit, CMOS
level shifters permit low power DTLlTTLICMOS
compatible operation. An external voltage or current
reference and an operational amplifier are all that is
required for most voltage output applications.

Converter errors are further reduced by using separate
metal interconnections between the major bits and the
outputs. Use of high threshold switches reduces the offset
. (leakage) errors to a negligible level.
The level shifter circuits are comprised of three inverters
with a positive feedback from the output of the second to
the first, (Figure 81. This configuration results in DTLI
TTLICMOS compatible operation over the full military
temperature range. With the ladder SPDT switches driven
by the level shifter, each switch is binarily weighted for an
ON resistance proportional to the respective ladder leg
current. This assures a constant voltage drop across each
switch, creating equipotential terminations for the 2R
ladder resistors and highly accurate leg currents.

A simplified equivalent circuit of the DAC is shown in
Figure 7. The NMOS SPDT switches steer the ladder leg
currents between loun and IOUT2busses which must be
held either at ground or virtual ground potential. This
configuration maintains a constant current in each ladder
leg independent of the input code.
10K!}

VREF

10K!}

10Kn

10K!}

v+-----~-~---~--~-

(15/17)

SPDT

NMOS

SWITCHES

IOUT2 (2)

4---4+--.....i-----<~--4_._---o loun

(1)

DTLlTTL/CMOS
INPUT

RFEEOBACK

(16/18)

(Switches shown for Digital Inputs "High")
Figure 7.7520/7521 Functional Diagram

Figure 8. CMOS Switch

APPLICATIONS

2. Adjust the offset zero adjust trimpot of the output
operational amplifier for OV ±1 mV at VOUT.
Gain Adjustment

UNIPOLAR BINARY OPERATION
The circuit configuration for operating the AD7520
(AD7530) and AD7521 (AD7531) in unipolar mode is
shown in Figure 9. With positive and negative VREF values
the circuit is capable of 2-Quadrant multiplication. The
"Digital Input Code/Analog Output Value" table for
unipolar mode is given in Table 1.

1. Connect all AD7520 (AD7530) or AD7521 (AD7531)
digital inputs to V + .
2. Monitor VOUT for a -VREF (1·2- n)reading. (n=10 for
AD7520 (AD7530) and n =12 for AD7521 (AD7531)).
3. To decrease VOUT, connect a series resistor (0 to 500
ohms) between the reference voltage and the VREF ter·
minal.
4. To increase VOUT , connect a series resistor (0 to 500)
ohms) in the lOUT, amplifier feedback loop.

+15V
VREF - - - - ,

BIT 1 (MS8)

DIGITAL

:

INPUT

;

1S

11~i"R.::.F::::EE",DB=AC::::'_ _ __

CODE TABLE -

13

:B~'T~'O;;(~LS;;B~)1!!.....;._3
GND

Figure 9. Unipolar Binary Operation
(2-Quadrant Multiplication)

Zero Offset Adjustment

TABLE 1
UNIPOLAR BINARY OPERATION

DIGITAL INPUT

ANALOG OUTPUT

1111111111

-VREF (1 - 2- n )

1000000001

-VREF (1/2

1000000000

-VREF /

0111111111

-VREF (1/2 - 2- n )

0000000001

-VREF (2

0000000000

0

+ 2- n )

2
-n)

2. n = 10 for 7520, 7530
n = 12 for 7521,7531

1. Connect all digital inputs to GND.

4·141

AD7520/7530/7521/7531
(APPLICATIONS, Conrd.)

Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Connect all digital inputs to "Logic 1".
3. Adjust IOUT2 amplifier offset zero adjust trimpot for OV
±1 mV at IOUT2 amplifier output.
4. Connect MSB (Bit 1) to "Logic l"and all other bits to
"Logic 0".
5. Adjust IOUT1 amplifier offset zero adjust trimpot forOV
±1 mV at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+;
2. MonitorVouT for a -VREF (1-2-(n-1» volts reading. (n=
10 for AD7520 and AD7530, and n = 12 for AD7521 and
AD7531).
3. To increase VOUT, connect a series resistor of up to
500n between VOUT and Rfb.
4. To decrease VOUT, connect a series resistor of up to
500n between the reference voltage and the VREF
terminal.

BIPOLAR (OFFSET BINARY) OPERATION
The ci~cuit configuration for operating the AD7520
(AD7530) or AD752,1 (AD7531) in the bipolar mode is given
in Figure 10. Using offset binary digital input codes and
positive and negative reference voltage values 4Quadrant multiplication can be realized; The "Digital
Input Code/Analog Output Value" table for bipolar mode
is given in Table 2.
+15
YREF

R3

---_1--I-,-------\M,.-----...,
10 MEGOHM

BIT 1 (MSS)

DIGITAL
INPUT

15

I
:

"

, 16 RFEEOBACK

AD7520

13
BIT 10 (LSB)

Figure 10. Bipolar Operation
14-Quadant Multiplication)

TABLE 2
CODE TABLE - BIPOLAR IOFFSET BINARY) OPERATION

A "Logic 1" input at any digital input forces the
corresponding ladder switch to steer the bit current to
IOUT1 bus. A "Logic 0" input forces the bit current to IOUT2
bus. For any code the IOUT1 and IOUT2 bus currents are
complements of one another. The current amplifier at
IOUT2 changes the polarity of IOUT2 current and the
transconductance amplifier at IOUT1 output sums the two
currents. This configuration doubles the output range but
halves the resolution of the DAC. The difference current
resulting at zero offset binary code, (MSB = "Logic 1", All
other bits = "Logie 0"), is corrected by using an external
resistor, (10 Megohm), from VREF to IOUT2.
POWER DAC DESIGN USING AD7520

BIT

SWITCHES

{

ANALOG OUTPUT
-VREF (1 - 2-(n-1»

1000000001

-VFiEF (2-(n-1»

1000000000

0

011111111'1

VREF (2-(n 1»

0000000001

VREF (1 - 2-(n 1»

0000000000
NOTE:1.LSB-2 (n-1)VREF

,.
15

-

DIGITAL INPUT
1111111111

VREF
2. n - 10 for 7520 and 7521
n = 1'2 for 7530 and 7531

30Kn
VREF (±10Y)
+15V

LSB}
,

10K,n

:~ITCHES
'

YOUT

lDOpI

7.SKn

Figure 11. The Basic Power DAC
A typical power DAC designed for 8 bit accuracy and 10
An important note on the AD7520/101A interface
bit resolution is shown in Figure 11. An INTERSIL IH8510
concerns the connection of pin 1 of the DAC and pin 2 of
power amplifier (1 Amp continuous output at l1pto ±25 V)
the lOlA. Since this pOint is the slimming junction of an
is driven by the AD7520.
amplifier with an AC gain of 50,000 or better. stray
A Slimming amplifier between the AD7520and the IH8510
capaCitance should be minimized; otherwise instabilities
is used to separate the gain block containing the AD7520
and poor noise performance will result. Note that the
on-chip resistors from the power amplifier gain stage
output of the lOlA is fed into an inverting amplifier with a
whose gain is set only by the external resistors. This
gain of -3, which can be easily changed to a non-inverting
configuration. (For more information see:INTERSI L
approach minimizes drift since the resistor pairs will track
properly. Otherwise the AD7520 can be directly
Application Bulletin A021-Power D/A 'Converters Using
connected tothe IH8510, by l1sing a 25 Vreferenceforthe
The IH8510 by Dick Wilenken.>
DAC.

4·142

.O~OIL.

AD7520/7530/7521/7531
(APPLICATIONS, Cont'd.)
ANALOG/DIGITAL DIVISION

This is division of an analog variable (VIN) by a digital word.
With all bits off, the amplifier saturates to its bound, since
division by zero isn't defined. With the LSB (Bit-10l ON,
the gain is 1023. With all bits ON, the gain is 1 (±1 LSBl.

With the AD7520 connected in its normal multiplying
configuration as shown in figure 15, the transfer function
is
Va = -VIN (A1

21

+

A2
22

+

A3
23

+ ...

An)
2n

+1SV

where the coefficients Ax assume a value of 1 for an ON bit
and 0 for an OFF bit.
By connecting the DAC in the feedback of an operational
amplifier, as shown in Figure 12, the transfer function
becomes

81T-1 (MSB)

15

::;:::::::::1"

'"

16

VIN

DIGITAL:
INPUT 1

Your

~B;'r'T:::;-10o;(;;LS;;;B~1.!!..-.;......!I

Figure 12. Analog/Digital Divider

For further information on the use of this device, see the following Application Bulletins:
A016
A018
A020
A021
R005

"Selecting AID Converters," by David Fullagar
"Do's and Don'ts of Applying AID Converters," by Peter Bradshaw and Skip Osgood
"A Cookbook Approach to High-Speed Data Acquisition and Microprocessor InterfaCing" by Ed Sliger
"Power DIA Converters Using the IH8510," by Dick Wilenken
"Interfacing Data Converters & Microprocessors," by Peter Bradshaw et aI., ElectroniCS, Dec. 9, 1976

4-143

II

AD7523
8 Bit Monolithic
Multiplying DI A Converters
FEATURES

GENERAL OESCRIPTION

•
•
•
•
•
•
•
•
•

The Intersil AD7523 is a monolithic, low cost, high
performance, 10 bit accurate, multiplying digital-to-analog
converter (DAC), in a 16-pin DIP.
Intersil's thin-film resistors on CMOS circuitry provide 8-bit
resolution (8, 9 and 10-bit accuracy), with DTL/TTL/CMOS
compatible operation.
Intersil AD7523's accurate four quadrant multiplication, full
military temperature range operation, full input protection
from damage due to static discharge by clamps to V+ and
GND and very low power dissipation make it a very versatile
converter.
Low noise audio gain control, motor speed control, digitally
controlled gain and attenuators are a few of the wide number
of applications of the 7523.

8,9 and 10 bit linearity
Low gain and linearity Tempcos
Full temperature range operation
Full input static protection
DTLITTL/CMOS compatible
+5 to +15 volts supply range
Fast settling time: 100 nS
Four q4adrant multiplication
8838 Processed versions available

__

III

r--F-U-N-C-T-IO-N-A-L-O-IA-G-R-A-M--------....--P-IN-C-O-N-F-IG-U-R-A-T-I-O-N---------..,

OUT1

0:: ~ ~

,
I

J,
MSB
(4)

I
I

~

BIT2
(5)

RFEEDBACK

~ VREFIN
~v+

[1
GND~

OUT2

BIT 1 (MSB)

[!

~

NC

BIT2

IT

~

NC

~

BIT 8 (LSB)

BIT 4

[I
[2

~

BIT 7

BIT 5

IT

I

I

&

BIT 3

BIT3

(6)

AD7S23

t!J

BIT 6

TOP VIEW

(Switches shown for Digital Inputs "High")

OUTLINE DRAWINGS
DE,PE

ORDERING INFORMATION

1LT

Temperature Range
,
Nonlinearity O°C to +70°C _20°C to+8S"C -55°C to +125°C
0.2%
(8 Bit)
AD7523AD
AD7523JN
AD7523SD
0.1%
(9 Bit)
AD7523KN
AD7523BD
AD7523TD
0.05%
(10 Bit)
AD7523LN
AD7523CD
AD7523UD

D

D - 18·Pln CERDIP DIP
N -l~·Pln PI..11c DIP
Nonlln••rlty and Temperature Range
J, K, L - Commercial

O'C 10 +70"C

A,B,C - Induetrlal
-20"C 10 +85"C
S,T,U -

MII"ary

- 55"C 10 +125"C
'--_ _ _ _ _ _ _ _ _ a •• le Part Number

4·144

AD7523
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
V+ .............................................. +17V
VREF •·· ... · ....•.............•................... ±25V
Digital Input Voltage Range. . . . . . . . . . . . . . . . .. -0.3 to VDD
Output Voltage Compliance ................. -0,3 to VDD
Power Dissipation (package)
Plastic
upto+70°C .................................. 670mW
deratesabove+70°Cby .................... 8.3mW/oC

Ceramic
up to 75° C ................................... 450mW
derates above 75° C by ....................... 6mW/o C
Operating Temperatures
IN, KN, LN Versions., .... , .. , ......... ,. 0°Cto+70°C
AD, BO, CO Versions ............... ,., -25°Cto+85°C
SO, TO, UO Versions .. , ... , .... , .... -55°Cto+125°C
Storage Temperature ..... ,."" ,., .. 435°Cto+150°C
Lead Temperature Isoldering, 10 seconds) .... ,' +300° C

CAUTION: 1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy
electrostatic fields. Keep unused units in conductive foam at all times.
2. Do not apply voltages higher than VDD and lower than GND to any terminal except YAEF + RFB.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied, Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

SPECIFICATIONS (V +

= + 15V, VREF = + 10V unless otherwise specified)
+25°C

,- TA
MIN-MAX

UNITS

LIMIT

8
±0.2

8
±0.2

Bits
% of FSR

Min
Max
Max

-10VSVREFS +10V

Max

VOUT1

% of FSR

Max

Digital inputs high.

PPM of FSR/o C
PPM of FSR/o C

Max
Max
Max

-10V VREF + 10V

TA
PARAMETER
DC ACCURACY INote 11
Resolution
Nonlinearity (Note 21

I

I
I

(±1/2 LSBI
(±1/4 LSBI
(±1/8 LSBI

Monotonicity

±0.1
±0.1
±0.05
±0.05
Guaranteed

Gain Error INote 21

±1.5

±1.8

% of FSR
% of FSR

Nonlinearity Tempco (Note 2 and 31
Gain Error Tempco (Note 2 and 31
Output Leakage Current leither outputl

±50

±200

nA

AC ACCURACY (Note 31
Power Supply Rejection INote 21

0.02

0.03

% of FSR/%

Output Current Settling Time
Feedthrough Error

150
±1/2

200
±1

nS
LSB

REFERENCE INPUT
Input Resistance (Pin 151
Temperature Coefficient INote 31
ANALOG OUTPUT INote 31
Voltage Compliance INote 41
Output CapaCitance

High State Threshold (V,NH)
Input Current Iper inputl
Input Coding
Input Capacitance (Note 31

5K

II

20K

ppm/oC

~500

Max
Max
Max

COUT1

100
30
30
100

pF
pF
pF
pF

Max
Max
Max
Max

0.8
2.4
±1
Binary/Offset Binary
4

V
V

Max
Min

p.A

Max

pF

Max

NOTES:

Voun - VOUT2 - 0

=

V+
14.0t015.0V
To 0.2% of FSR, RL

= 1O0ll

=

'V AEF
20V pp, 200KHz sine wave. All
digital inputs low.

+5 to +16
100

V
p.A

All digital inputs high. loun at ground.
Both outputs.
See maximum ratings.
All digital inputs high IVINHI
All digital inputs low IVINU

Guarantees DTL/TTL and CMOS 10.5
max, 14.5 mini levels
Y,N - OV or +15V
See Tables 1 & 2
Accuracy is tested and guaranteed at

POWER REQUIREMENTS
Power Supply Voltage Range
1+

=VOUT2 =OV

Min
Max
Max

-100mV to V+
COUT2
Coun
COUT2

DIGITAL INPUTS
Low State Threshold (V ,NL )

2
10

TEST CONDITIONS

1. Full scale range (FSRI is 10V for unipolar and .±10V for bipolar modes.
2. Using internal feedback resistor, RFEEDBACK.
3•. Guaranteed by design; not subject to test.
4. Accuracy not guaranteed unless outputs at ground potential.

4-145

V+
Max

= + 15V, only,

All digital inputs low or high.

Specifications subject to
change without notice.

.D~OIL

AD7523
DIGITAL INPUT
MSB
LSB

APPLICATIONS
UNIPOLAR OPERATION
±10V
VREF

11111111

NOTES:
1. R1 AND R2 USED ONLY IF GAIN
ADJUSTMENT IS REQUIRED.
2. CR1 PROTECTS AD7523 AGAINST
NEGATIVE TRANSIENTS.

+15V

R1
2k

ANALOG OUTPUT

-VREF
.",

R21k

Your

10000001

-VREF

(129)
256

10000000

",VREF

C28)
256

01111111

-VREF

C27)
256

00000001

-VREF'

00000000

-VREF

Note: 1 LSB = (2- 8 ) (VREF)=

Figure 1. Unipolar Binary Operation (2-Quadrant Multiplication)

( 255)
256

(2~6)

(2~6)
(2~6)

= _ VREF
2

=0

(VREF)

Table 1. Unipolar Binary Code Table

BIPOLAR OPERATION
::10V

-t-15V

VAEF

DIGITAL INPUT
MSB
LSB

R45k

R21k

11111111

-VREF

C27)
128

R35k

10000001

-VREF

(1~8)

R71Mll
R610k

ANALOG OUTPUT

CR2

NOTES:
3. R5-R7 USED TO ADJUST Vour = OV AT
INPUT CODE 10000000.
1. R3!R4 MATCH 0.1% OR BETTER.
2. R1, R2 USED ONLY IF GAIN
4. CR1 & CR2 PROTECT AD7523 AGAINST
NEGATIVE TRANSIENTS.
ADJUSTMENT IS REQUIRED.

10000000

0

01111111

+VREF

00000001

+VREF

C27 )

00000000

+VREF

(128)
128

Note: 1LSB = (2-7 ) (VREF) =

(1~8)

(1~8)
128

(VREF)

Table 2. Bipolar (Offset Binary) Code Table

Figure 2. Bipolar (4-Quadrant) Operation

POWER DAe DESIGN USING AD7523
16~-----------------------,

15
14
4 INTERSIL 13
AD7523 12 -

~:

VAEF (±10Y)
+15V
NC
NC

}

O.68ll

10Kll

YOUT

:~ITCHES
100pl
-35Y

O.68ll

7.5Kll

Figure 3. The Basic Power DAC

A typical power DAC designed for 10 bit accuracy and 8 bit
resolution is shown in Figure 3. INTERSIL IH8510 power
amplifier (1 Amp continuous output with up to +25V) is driven
by the AD7523.

chip resistors from the power amplifier gain stage whose
gain Is set only by the external resistors. This approach
minimizes drift since the resistor pairs wi" track properly.
Otherwise AD7523 can be directly connected to the IH8510,
by using a 25 volts.referencefor the DAC.

A summing amplifier between the AD7523 and the IH8510 is
used to separate the gain block containing the AD7520 on-

4-146

IID~DIl

AD7523
APPLICATIONS (continued)
DIVIDER (DIGITALLY CONTROLLED GAIN)

MODIFIED SCALE FACTOR AND OFFSET
VREF

+15V

VOUT

= - VIN/o

WHERE:
0= alT1 +~+ ... ~
21

22

R,

alT 1
15 14 16
1
DIGITAL Msa 4
!,~~UT
Lsa
AD7523

!

28

255)

( 0<0<
- 256
>-..o--oVOUT
+.

Vour = VREF

[(R'~R') - (R~:OR2~ WHERE:

0 = al;' 1+ al;,2 + ... al;' 8
( 0<0<,255)
- - 256

DEFINITION OF TERMS
NONLINEARITY: Error contributed by deviation of the DAC
transfer function from a best straight line function. Normally
expressed as a percentage of full scale range. For a
multiplying DAC, this should hold true over the entire VREF
range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2- n) (VREFl. A bipolar
converter of n bits has a resolution of [2-(n-1)][VREFJ.
Resolution in no way implies linearity.
SETTLING TIME: Time required f~r the output function of
the DAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to Full Scale.

GAIN: Ratio of the DAC's operational amplifier output
voltage to the nominal input voltage value.
FEEDTHROUGH ERROR: Error caused by capacitive
coupling from VREF to output with all switches OFF.
OUTPUT CAPACITANCE: Capacity from IOUT1 and IOUT2
terminals t6 ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
loun terminal with all digital inputs LOW or on IOUT2
terminal when all inputs are HIGH.

For further informatiQn.on the use of this device, see the following Application Bulletins:

A016
A018
A020
A021
R005

"Selecting AID Converters," by David Fullagar
"Do's and Don'ts of Applying AID Converters," by Peter Bradshaw and Skip Osgood
"A Cookbook Approach to High-Speed Data Acquisition and Microprocessor Interfacing" by Ed Sliger
"Power D/A Converters Using the IH8510," by Dick Wilenken
"Interfacing Data Converters & Microprocessors," by Peter Bradshaw et aI., Electronics, Dec. 9, 1976

4-147

Af)7533
10 Bit Monolithic
Multiplying DI A Converters
FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•
•
•
•
•
•
•

The Inters/l AD7533 is a low cost, monolithic 10-bit, fourquadrant multiplying digital-to-analog converter (DAC)'
Intersil's thin-film resistors on CMOS circuitry provide 10, 9
and 8 bit accuracy, full temperature range operation, +5V to
+15V power range, full input protection from damage due to
static discharge by clamps to V+ and ground and very low
power dissipation.
Pin and function equivalent to Industry Standard AD7520,
the AD7533 is,recommended as a lower cost alternative for
old or new 10-bit DAC designs.
Application of AD7533 includes programmable gain
amplifiers, digitally controlled attenuators, function
generators and control systems.

Lowest cost 10-bit DAC
8,9 and 10 bit linearity
Low gain and linearity Tempcos
Full temperature range operation
Full input static protection
DTL/TTL/CMOS direct interface
+5 to +15 volts supply range
Low power dissipation
Fast settling time
Four quadrant multiplication
Direct AD7520 equivalent
8838 Processed versions available

II ~--..,-------.-----FUNCTIONAL DIAGRAM

10Kn

V:REFIN

10Kn

10K!!

PIN CONFIGURATION

10K!!

(15)
20Kn

20Kn

20Kn

20Kn

SPOT
NMOS
SWITCHES

20Kn

IOUT2(2)
IOUTl (1)
I
I

6

BIT2
(5)

I

I

RFEEDBACK

,\
BIT3
(6)

(16)

(Switches shown for Digital Inputs "High")

(Outline dwg DE, PEl

ORDERING INFORMATION

PACKAGE IDENTIFICATION
AD7S33

D

Temperature Range
Nonlinearity DOC to +7D o C -20°C 10+8S'C -5S o C 10 +125°C
±O.2%
(S-bitl
±O.l%
(9-bitl
±O.O5%
(10-bit)

AD7533JN

AD7533AD

AD7533SD

AD7533KN

AD7533BD

AD7533TD

AD7533LN

AD7533CD

AD7533UD

LPACKAGE
D - 18-PIN CERDIP DIP
N - 18·PIN PLASTIC DIP

'-------

~~:~~~~':~ ::~GE
J,K,L - COMMERCIAL O"C TO + 70"C
A,B - INDUSTRIAL -20"C TO +8S"C
S,T - MILITARY -5S"C TO +12S"C

'--_ _ _ _ _ _ _ _ _ BASIC PART NUMBER

4-148

AD7533
ABSOLUTE MAXIMUM RATINGS
(TA = 25° C unless otherwise· noted)

Plastic
up to 70° C ................................... 670mW
derates above 70° C by ..................... 8.3mW/o C
Operating Temperatures
IN, KN, LN Versions ..................... 0°Cto+70°C
AD, BD, CD Versions .................. -25°Cto+85°C
SO, TO, UD Versions ................ -55°Cto+125°C
Storage Temperature ................ -65°Cto+150°C
Lead Temperature (soldering, 10seconds) ...... +300° C

V+ ........................................ -{).3V,+17V
VREF ...............••••...........•.............. ±25V

Oigitallnput Voltage Range ................... -{).3V to V+
Output Voltage Compliance .................... -{).3 to V+
Power Dissipation (package)
Ceramic
upto+75°C .................................. 450mW
derates above +75° C by ...................... 6mW/o C

CAUTION: 1. The digital control inputs are zener protected; however, permanent damage may occur on unconnected units under high energy
electrostatic fields. Keep unused units in conductive foam at all times.
2. Do not apply voltages lower than ground or higher than V+ to any pin except VREF and RFB.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

SPECIFICATIONS .tv+ = +15V, VREF= +10V, VOUT1 =VOUT2=O unless otherwise specified.)
PARAMETER
DQ ACCURACY INote 11
Resolution
Nonlinearity INote 21

Gain Error INote 2 and 51
Output Leakage Current leither outputl
ACACCURACY
Power Supply Rejection INote 2 and 31
Output Current Settling Time
Feedthrough Error INote 31
REFERENCE INPUT
Input Resistance IPin 151
Temperature Coefficient
ANALOG OUTPUT
Voltage Compliance INote 41
Output Capacitance INote 31

,
DIGITAL INPUTS
Low State Threshold IVINLI
High State Threshold IVINHI
Input Current lliNI
Input Coding
Input Capacitance INote 31
POWER REQUIREMENTS
Voo
Power Supply Voltage Range
1+

TA
+25°C

TA
MIN·MAX

UNITS

LIMIT

10
±0.2
±0.1
+0.05
+1.4
+50

10
±0.2
±0.1
+0.05
+1.5
+200

Bits
% of FSR
% of FSR
% of FSR
%of FS
nA

Min
Max
Max
Max
Max
Max

0.005
600
INote 61
±0.05

0.008

% of FSR/%

800
INote 31
±0.1

nS

Max
Max

% FSR

Max

n
ppm/oC

Min
Max
Typ

5K
20K
-300

COUT1
COUT2
COUT1
COUT2

-100mV to V+
100
35
35
100

pF
pF
pF
pF

Max
Max
Max
Max

0.8
2.4

V
V

±1
Binary/Offset Binary
5

IJ.A

Max
Min
Max

pF

Max

+15 ±10%
+5 to +16
2
100
150

V
V
mA
p.A

I

TEST CONDITIONS

-10V:sVREF:S +10V
Voun = VOUT2 = OV
Digital Inputs = VINH
VREF - ±10V
V+

= 14.0 to 17.0V

To 0.05% of FSR, RL

= lOOn

VREF = ±10V, 100kHz sine wave.
Digital inputs low.
All digital inputs high.
Both outputs.
See maximum ratings.
All digital inputs high IVINHI
All digital inputs low IVINLI

VIN = OV and V+
See Tables 1 & 2

Rated Accuracy
Max
Max

Digital Inputs - VINL to VINH
Digital Inputs - OV or V+

NOTES: 1. Full scale range IFSRI is 10V for unipolar and ±10V for bipolar modes.
Specifications subject to
2. Using internal feedback resistor, RFEEOBACK.
change without notice.
3. Guaranteed by design; not subject to test.
4. Accuracy not guaranteed unless outputs at ground potential.
5. Full scale IFSI = - IVREFI • 11023/10241
6. Sample tested to ensure specification compliance.
7. 100% screened to MIL·ST[)'883, method 5004, para. 3.1.1. through·3.1.12 for class B device. Final electrical tests are: Nonlinearity,
Gain Error, Output Leakage Current, VINH, VINL, liN and 1+ @ +25°C and +125°C (SO, TO, UO) or +.25'C and +85°C (AD, BO, CD).

4·149

AD7533
GENERAL CIRCUIT INFORMATION
I

The Intersil AD7533 is a 10 bit, monolithic, multiplying D/A
converter. Highly stable thin film R-2R resistor ladder
network and NMOS DPDT switches form the basis of the
converter circuit. CMOS level shifters provide low power
DTUTTUCMOS compatible operation. An external voltage
or current reference and an operational amplifier are all that
is required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in Figure
1. The NMOS DPDT switches steer the ladder leg currents
between IOUT1 and IOUT2 busses which must be held at
ground potential. This configuration maintains a constant
current in each ladder leg independent of the input code.
10K!}

'lREFIN

10K!}

10K!}

The level shifter circuits are comprised of three inverters with
a positive feedback from the output of the seCond to the first,
(Figure 2). This configuration results in DTUTTUCMOS
compatible operation over the full military temperature
range. With the ladder DPDT switches driven by the level
shifter, each switch is binarily weighted for an "ON"
resistance proportional to the respective ladder leg current.
This assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder
resistors resulting in accurate leg currents.
v+-----~-~---~--~--

10K!!
6

(lS)

TO LADDER

20Kn

SPOT
10UT2 (2)
NMOS
SWITCHES 4----4>+---4-.;----......----4......--,--<> loun (1)

I

I

!

MSB
(4)

DTLlTTLICMOS

I

~

;,

BIT2
(S)

INPUT

RFEEDBACK

(16)

BIT3
(6)

IOUT2

lOUT'

(Switches shown for Digital Inputs "High")
Figure 1

Figure 2

A,PPLICATIONS

BIPOLAR OPERATION
(4-QUADRANT MULTIPLICATION)

UNIPOLAR OPERATION
(2-QUADRANT MULTIPUCATION)

ANI~~~~ ±tOV

v+

BIPOLAR

ANI~~~~

±10V

v+

R21k
R21k
R4 Sk

A3 5k

VOUT

A71Mll
A610k

NOTES:
1. Rl AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. SCHOTTKY DIODE CRl (HPS082·2811 OR EQUIV) PROTECTS
TERMINAL AGAINST NEGATIVE TRANSIENTS.

7

oun

Figure 3. Unipolar Binary Operation (2-Quadrant Multiplication)
DIGITAL INPUT
MSB
LSB
1111111111

as

1000000001

-VAEF

1000000000

-VAEF

0111111111

-VREF

0000000001

-VAEF

0000000000

-VREF

=

-VREF

NOMINAL ANALOG OUTPUT
(VOUT

as shown in Figure 4)

1111111111

-VAEF

(.§.!1.)
512

1000000001

-VREF

(5~2 )

(- 513)

To24

tTo24

512 )

-

VAEF

2""

1000000000

(511 )
1024

(,0~4)
(,~24) ~ 0

0111111111

+VAEF

0000000001

+VREF

0000000000

+VREF

(

5~2)

(.§.!1.)
512
(.?,g)
512

NOTES:
1. Nominal Full Scale Range for the circuit of Figure 4 is given by

(~)

1024
2. Nominal LSB magnitude for the circuit of Figure 3 is given by
LSB

Bipolar Operation 14-Quadrant Multiplication)

DIGITAL INPUT
MSB
LSB

( 1023)
1024

NOTES:
1. Nominal Ful.1 Scale for the circuit of/Figure 3 is given by
FS

Figure 4.

shown in Figure 31

-VR,EF

-=

NOTES:
t. R3/R4 MATCH O.OS% OR BETTER.
2. Rl, R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
3. SCHOTTKY DIODES CRl AND CR2 (HPS082·2811 OR EQUIV)
AND OUT2 TERMINALS FROM NEGATIVE
PROTECT
TRANSIENTS

oun

NOMINAL ANALOG OUTPUT
(VOUT

CR2

FSR

= VREF ( 1023)
512

2. Nominal LSB magnitude for the circuit of Figure 4 is given by

= VAEF LO~4)

.LSB= VREF

(5~2)

Table 2. Bipolar (Offset Binary) Code Table

Table 1. Unipolar Binary Code

4·150

AD7533

.

POWER DAC DESIGN USING AD7533
15
14
4 INTERSIL 13
AD7523 12

{

BIT
-SWITCHES

7

11
10

VRE' (±10V)
+15V
NC
NC
}

0.68ll

10Kll

VOUT

BIT
SWITCHES

8
100pl
-35V

0.S8!!

7.5Kn

30pF
-15V

Figure 5. The Basic Power DAC

A typical power DAC designed for 8 bit accuracy and 10 bit
resolution is shown in Figure 5. INTERSIL IH8510 power
amplifier (1 Amp continuous output with upto+25V) is driven
by the AD7533.
A summing amplifier between the AD7533 and the IH8510 is
used to separate the gain block containing the AD7533 onchip resistors from the power amplifier gain stage whose
gain is set only by the external resistors. This approach

minimizes drift since the resistor pairs will track properly.
Otherwise AD7533 can be directly connected to the IH8510,
by using a 25 volts reference for the DAC. Notice that the
output of the 101A is fed into an inverting amplifier with a
gain of -3, which can be easily changed to a non-inverting
configuration. (For more information write for: INTERSIL
Application Bulletin A021-Power D/A Converters Using The
IH8510 by Dick Wilenken.l

10-BIT AND SIGN MULTIPLYING DAC

PROGRAMMABLE FUNCTION GENERATOR
CALIBRATE
10k

±10V
BIPOLAR
ANALOG INPUT

Ftf

v+

SQUARE
WAVE

VAEF

10k

10k

y
~ N (8R~Ct)

.,!:

I

~ ~--------------------~
iii

Rt ~ 10k!!
0< N s (1 - 2-tO)

TRIANGULAR
WAVE

INPUT SIGNAL WARNING
Because of the input protection diodes on the logic inputs, it is important that .no voltage greater than 4V outside the logic
supply rails be applied to these inputs at any time, including power-up and other transients. To do so could cause destructive
SCR latch-up.

4·151

AD7S41
12 Bit Monolithic
Multiplying DI A Converte...

I

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•
•
•
•
•
•

The Intersi! AD7541 is a monolithic, low cost, high
performance, 12-bit accurate, multiplying digital-to-analog
converter (DAC).
Intersil's. wafer level laser-trimmed thin-film resistors on
CMOS circuitry provide true 12-bit linearity with DTLlTTLI
CMOS compatible operation.
Special tabbed-resistor geometries (improving time
stability), full .input protection from damage due to static
discharge by diode clamps to V+ and ground, large IOUT1
and IOUT2 bus lines (improving superposition errors) are
some of the features offered by Intersi! AD7541.
Pin compatible with AD7521, this new DAC provides
accurate four quadrant multiplication over the full military
temperature range.

12 bit linearity (0.01%)
Pretrimmed gain
Low gain and linearity Tempcos
Full temperature range operation
Full Input static protection
DTLITTL/CMOS compatible
+5 to +15 volts supply range
Low power dissipation (20m,).\')
Current settling time: 1J.Ls to 0.01% of FSR
Four quadrant multiplication
8838 Processed versions available

FUNCTIONAL DIAGRAM

10Kn

VREF IN

10KD

PIN CONFIGURATION

10KD

10Kn

"

(17)

..Kn

2.Kn>

2OK!l

l

SPOT

I

NMOS
SWITCHES

I
I

I
I

b
MSB
(4)

r'h r'h
I

I

I

I

I

I

...

Bin
(5)

•

BIT3

'vv

2.Kn>

2QKn

r r
1

TOPYIEW

1,

2.Kn

-=

1

Icun

IT •

IOUT2

[1

(3)

BIT 1 (~SB)

[!

81T2

IT

a'IT3

[!

IOUT2 (2)

10K!!
RFEEOBACK

(18)

(6)

~ RF~EOBACK

~ VREF,IN

\~v+

ONOe!

~'OUr'(1)

....

-AD7541

~ iIlT 12 (LSB)

~BIT11
~BIT10

SIT 4

IT

~BIT9

BIT 5

[!

tTIl BITa

BITO

[9

1101 BIT7

(Switches shown for Digital Inputs "High")
(Oull!ne dwg DN, PN)
\

ORDERING INFORMATION
~~

Temperature Range
Nonlinearity O°C to +70°C -20·C to +85··C -55°C to +125°C
0.02%
(11-bitl
AD7541JN
AD7541AD
AD7541SD
0.01%
(12-bitl
AD7541KN
AD7541BD
AD7541TD
0.01%
(12-bitl
AD7541LN
Guaranteed
Monotonic

-

-

T

D

~

PACKAGE
D - II-PIN CERDIP DIP
N - II-PIN PLASTIC DIP
NONLINEARITY AND
TEMPERATURE RANGE
J,K,L - COMMERCIAL O·C TO +70·C
A,B - INDUSTRIAL -20·C TO +B6·C
S,T,- MILITARY -55·C TO +125·C
BASIC PART NUMBER

4·152

AD7541
ABSOLUTE MAXIMUM RATINGS
(TA = 25°C unless otherwise noted)
V+ ............................................... +17V
VREF ............................................ ±25V
Digital Input Voltage Range .................. V+ to GND
Output Voltage Compliance .............. -100mV to V+
Power Dissipation (package)
upto+75°C .................................. 450mW
deratesabove+75°Cby ...................... 6mW/oC
CAUTION

Operating Temperatures
IN,KN,LNVersions ..................... O°Cto+70°C
AD,BDVersions ..................... -20'Cto +85'C
SD, TDVersions ..................... -55°Cto+125°C
Storage Temperature ................ --65°Cto+150°C

1. The digital control inputs are zener protected; however, permanent damage may occur on unconnecled units under high energy
electrostatic fields. Keep unused units in conductive foam at all times.
2. Do not apply voltages higher than VDD or less than GND potential on any terminal except VREF and Rfb.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended period may affect device reliability.

SPECIFICATIONS (V+ = +15V, VREF= +10V, TA =25'C unless otherwise specified)
PARAMETER
DC ACCURACY (Note 11
Resolution
Nonlinearity INote 21

S
T

J
K
L

Gain Error INote 21
Output Leakage Current (either outputl
AC ACCURACY (Note 31
Power Supply Rejection (Note 21
Output Current Settling Time
Feedthrough Error

12

12

±0.020
±0.024
±0.010
±0.012
±0.010
±0.012
Guaranteed Monotonic
+0.3
+0.4
±50

DIGITAL INPUTS
Low State Threshold (VINU
High State Threshold (VINHI
Input Current
Input Coding
Input Capacitance (Note 3)
POWER REQUIREMENTS
Power Supply Voltage Range
1+
Total Power Dissipation (including the
ladder)

TEST CONDITIONS

UNITS

LIMIT

Bits
% of FSR
% of FSR
% of FSR

Min
Max
Max
Max

-10V'S VREF 'S +10V
VOUT1 ~ VOUT2 ~ OV
-10V'S VREF 'S +10V

% of FSR

Max

±200

nA

Max

±0.02

% of FSR/%

Max
Max
Max

1
1

I'S
mV pp

5K
10K
20K

n

Min
Typ
Max

-100mV to V+
COUT1
'COUT2
COUT1
COUT2

Output Noise (both outputs)

NOTES: 1.
2.
3.
4.

TA
MIN-MAX

±0.01

REFERENCE INPUT
Input Resistance
ANALOG OUTPUT
Voltage Compliance (Note 41
Output Capacitance (Note 31

TA
+25°C

200
60
60
200
Equivalent to 10Kn
Johnson noise

pF
pF
pF
pF

0.6
2.4
±1

V
V
I'A

Binary/Offset Binary
6

pF

+5 to +16
2
20

V
mA
mW

Max
Max
Max
Max
Typ

Max
Min
Max

VOUT1
V+

~

~

VOUT2

~

FIG.

1

0

14.5 to 15.5V

To 0.01% of FSR
VREF - 20V pp, 10kHz. All
digital inputs low.

2
6
5

All digital inputs high.
IOUT1 at ground.
Both outputs.
See maximum ratings.
All digital inputs high IVINHI

4

All digital inputs low (VINLI

4
3

VIN - 0 or V+
See Tables 1& 2 on pages 4 and 5.

Full scale range (FSR) is 10V for unipolar and ±10V for bipolar modes.
Using internal feedback resistor, RFEEDBACK.
Guaranteed by design; not subject to test.
Accuracy not guaranteed unless outputs at ground potential.

4-153

Max
Accuracy is not guaranteed
over this range
Max
Typ

All digital inputs high or low

Specifications subject to
change without notice.

AD7541
TEST CIRCUITS

12 BIT

BINARY
COUNTER

UNGROUNDED

,,,

SIN~WAVE

A07541

ISIT12

(LSB)

GENERATOR
40Hz 2V p-p

15

10K .01%

500K

+10 V
YREF~.----.....
(ADJUST

--+--.JovV\r--""---<'"

1 MEG

IUl

FOR

CLOCK

,t

B
="T='=(::M:::;SB:::)r.
=OV.DC/f

VERROA

10K .OWn

BIT 12

(LSB)

Figure 1. Nonlinearity

I

,Figure 2. Power Supply Rejection

+11V (ADJUST FOR VOUT'= OV)

,.

+15V
Ne
F = 1kHz
BW

=1Hz
BIT 1 (MSB) 417

QUAN
TECH
MODEL

5

+15

,.,.

He

1340
WAVE
ANALYZER

100 mVp-p
1MHz

Figure 3. Noise

+15V

+15V

VREF '" 20V p-p 10kHz SINE WAVE

BIT 1 (MSS)

Figure 4. Output Capacitance

+10 V.:.:VR.:=-':...F- - - ,
17

,.

BIT 1 (MSS) 417

h==::I;

~= I"1JlJ1.
DIGITAL INPUT

15

3t: 5% SETTLING

,"*_~,.:,EXTAAPOLATE 9t: 0.01% SETTLING

Your

I

5 AD7541

1

'BIT
-i'T-miLsEijI!;'
5:""'f-...!I
12 (LSB)

BIT 12 (LSS)

GHD

Figure 5. Feedthrough Error

Figure 6. Output Current Settling Time

DEFINITION OF TERMS
NONLINEARITY: Error contributed by deviation of the DAC
transfer function from a best straight line function. Normally
expressed as a percentage of full scale range. For a
multiplying DAC, this should hold true over the entire VREF
range.
RESOLUTION: Value of the LSB. For example, a unipolar
converter with n bits has a resolution of (2-n ) (VREF). A bipolar
converter of n bits has a resolution of [2-(n-l)] [VREF].
Resolution in no way implies linearity.
SETTLING TIME: Time required for the output function of
the DAC to settle to within 1/2 LSB for a given digital input
stimulus, i.e., 0 to Full Scale.

GAIN: Ratio of the DAC's operational amplifier output
voltage to the nominal input voltage value.
FEEDTHROUGH ERROR: Error caused by capacitive
coupling from VREF to output with all switches OFF.
OUTPUT CAPACITANCE: Capacity from loun and IOUT2
terminals to ground.
OUTPUT LEAKAGE CURRENT: Current which appears on
IOUTl terminal with all digital inputs LOW or on IOUT2
terminal when all inputs are HIGH.

4-154

AD7541
GENERAL CIRCUIT INFORMATION
The Intersil AD7541 is a 12 bit, monolithic, multiplying D/A
converter. Highly stable thin film R-2R resistor ladder
network and NMOS DPDT switches form the basis of the
converter circuit. CMOS level shifters provide low power
DTLlTTLlCMOS compatible operation. An external voltage
or current reference and an operational amplifier are all that
is required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in Figure
7. The NMOS DPDT switches steer the ladder leg currents
between IOUT1 and IOUT2 busses which must be held at
ground potential. This configuration maintains a constant
current in each ladder leg independent of the input code.
Converter errors are further eliminated by using wider metal
interconnections between the major bits and the outputs.
Use of high threshold switches reduces the offset (leakage)
errors to a negligible level.

VREF IN

10Kn

10K!!

10Kil

Each circuit is laser-trimmed, at the wafer level, to better than
12 bits linearity. For the first four bits of the ladder, special
trim-tabbed geometries are used to keep the body of the
resistors, carrying the majority of the output current,
undisturbed. The resultant time stability of the trimmed
circuits is comparable to that of untrimmed units.
The level shifter circuits are comprised of three inverters with
a positive feedback from the output of the second to the first
(Figure 8). This configuration results in DTL/TTLICMOS
compatible operation over the full military temperature
range. With the ladder DPDT switches driven by the level
shifter, each switch is binarily weighted for an "ON"
resistance proportional to the respective ladder leg current.
This assures a constant voltage drop across each switch,
creating equipotential terminations. for the 2R ladder
resistors, resulting in accurate leg currents.

10Kn

(17)

SPOT

NMOS
SWITCHES

IOUT2 (2)

L+--++--......---~--4---oloUT1

(1)

AFEED6ACK

(18)

(Switches shown for Digital Inputs "High")
Figure 7. AD7541 Functional Diagram

Figure 8. CMOS Switch

APPLICATIONS
General Recommendations
Static performance of the AD7541 depends on lauT1 and
lauT2 (pin 1 and pin 2) potentials being exactly equal to GND
(pin 3).

Ground-loops must be avoided by taking all pins going to
GND to a common point, using separate connections.

The output amplifier should be selected to have a low input
bias current (typically less than 75nA), and a low drift
(depending on the temperature range). The voltage offset of
the amplifier should be nulled (typically less than ±200/LV).
The bias current compensation resistor in the amplifier's
non-inverting input can cause a variable offset. Noninverting input should be connected to GND with a low
resistance wire.

4-155

The V+ (pin 18) power supply should have a low noise level
and shOuld not have any transients exceeding + 17 volts.
Unused digital inputs must be connected to GND or Voo for
proper operation.
A high value resistor (-1 MO) can be used to prevent static
charge accumulation, wh.en the inputs are open-circuited for
any reason.
When gain adjustment is required, low tempco (approximately 50ppm/o C) resistors or trim-pots should be selected.

AD7541
APPLICATIONS, Continued
UNIPOLAR BINARY OPERATION
The circuit configuration for operating the AD7541 in
unipolar mode is shown in Figure 9. With positive and
negative VREF values the circuit is capable of2-Quadrant
multiplication. The "Digital Input Code/Analog Output
Value" table for unipolar mode is given in Table 1. Schottky
diode (HP 5082-2811 or equivalent) prevents IOUT1 from
negative excursions which could damage the device. This
precaution is only necessary with certain high speed
ampliffers.

Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output operational amplifier for OV±0.5mV (max) at VOUT.
Gain Adjustment
1. Connect all digital inputs to VDD.
2. Monitor VOUT for a -VREF (1 - 1/212) reading.
3. To increase VOUT, connect a series resistor, (Q to 500
ohms), in the IOUT1 amplifier feedback loop.
4. To decrease VOUT, connect a series resistor, (Q to 500
ohms), between the reference voltage and the VREF
terminal.
TABLE 1

+15V

Cede Table - Unipelar Binary Operatien

VREF - - - - ,

BIT 1 (MSB)

17

::;==':1'
DIGITAL
INPUT

16

DIGITAL INPUT
111111111111
100000000001
100000000000
011111.111111
000000000001
000000000000

RFEED8ACK

1·F=::::.:...----,

:
:
YOUT

BIT 12 (LSS)

BIPOLAR (OFFSET BINARY) OPERATION
The circuit configuration for operating the AD7541 in the
bipolar mode is given in Figure 10. Using offset binary digital
input codes and positive and negative reference voltage
values Four-Quadrant multiplication can be realized. The
"Digital Input Code/Analog Output Value" table for bipolar
mode is given in Table 2.
+15Y

VREF

BIT 1 (MSB)

I
I
I
I
I
DIGITAL:

,

,.

17

16

YOUT

ANALOG OUTPUT
-VREF (1 - 1/2121
-VREF (1/2 + 1/212)
-VREF/2
-VREF (1/2 - 11212)
-VREF (1/212)
0

Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Set R4 to zero.
3. Connect all digital inputs to "Logic 1".
4. Adjust IOUT2 amplifier offset zero adjust trimpot for OV
±0.1mVat IOUT2 amplifier output.
5. Connect a short circuit across R2.
6. Connect all digital inputs to "Logic 0".
7. Adjust IOUT2 amplifier offset zero adjust trimpot for OV
±0.1 mV at IOUll amplifier output.
8. Remove short circuit across R2,
9. Connect MSB (Bit 1) to "Logic 1" and all other bits to
"Logic 0".
10. Adjust R4 for OV ±0.2mV at VOUT.

AD7541

INPUT I

I
I
I
I
I
I

BIT 12 (lSB)

,.

R'

soon
GNO
'::'

':'

'::'

Note: R1 and R2 sheuld be 0.01%, lew-TCR resisters.
Figure 10. Bipelar Operatien (4-Quadrant Multiplicatien)

Gain Adjustment
1. Connect all digital inputs to VDD.
2. Monitor VOUT for a -VREF (1 - 1/211) volts reading.
3. To increase VOUT. connect a series resistor, (0 to 500
ohms), in the IOUT1 amplifier feedback loop.
4. To decrease VOUT, connect a series resistor, (0 to 500
ohms), between the reference voltage and the VREF
terminal.

A "Logic 1"input at any digital input forces the corresponding ladder switch to steer the bit current to IOUT1 bus.
A "Logic 0" input forces the bit current to IOUT2 bus. For any
code the IOUT1 and IOUT2 bus currents are complemepts of
one another. The current amplifier at IOUT2 changes the
polarity of IOUT2 current and the transconductance
amplifier at IOUT1 output sums the two currents. This configuration doubles the output range but halves the resolution
of the DAC. The difference current resulting at zero offset
binary code, (MSB = "Logic 1", All other bits = "Logic 0"), is
corrected by. using an external resistive divider, from'
VREF to IOUT2.

TABLE 2

Cede Table - Bipolar (Offset Binary) Operatien
DIGITAL INPUT
111111111111
100000000001
100000000000
011111111111
00000000Q001
000000000000

4-156

ANALOG OUTPUT
-VREF (1 - 1/211)
-VREF (1/211)
0
VREF (1/211)
..
VREF(l ~ 1/211)
VREF

.D~OIl

AD7541
+15V
YREF +10V

17

BIT 1 (MSB)

BIT 2

0---"',

5
5V/DIV
VOUT

BIT 12 (LSB) <>-'--~1'~5--i~:I

Figure 11. General DAC Circuit with Compensation
Capacitor, Cc.

1

J

1

'"

II

,'"

Figure 14. AD7541 Response with: A = Intersil 2520

DYNAMIC PERFORMANCE
The dynamic performance of the DAC, also depends on the
output amplifier selection. For low speed or static applications, AC specifications of the amplifier are not very critical.
For high-speed applications slew-rate, settling-time, openloop gain and gain/phase-margin specifications of the
amplifier should be selected for the desired performance.

20 a/DIV

"

II

\

5Y/DIV

-

The output impedance of the AD7541 looking into 10UT1,
varies between 10kn (RFeedback alone) and 5kn (RFeedback in
parallel with the ladder resistancel.
Figure 12. AD7541 Response with: A

Similarly the output capacitance varies between the
minimum and the maximum values depending on the input
code. These variations necessitate the use of compensation
capacitors, when high speed amplifiers are used.

= Intersil 741HS

A capacitor in parallel with the feedback resistor provides the
necessary phase compensation to critically damp the
output.

1 a/DIY

"

1,\

A small capacitor connected to the compensation pin of the
amplifier may be required for unstable situations causing
oscillations. Careful PC board layout, minimizing parasitic
capacitances, is also vital.

\

5V/DIV

I

IJ

f\

11, I

\

II

~

1\

Three typical circuits and the resultant waveforms are shown
in Figures 11 to 14. A low-cost general purpose (Intersil
741 HS), a low-cost high-speed Ontersil 2515) and a highspeed fast-settling (Intersil 25201 amplifier cover the
principal application areas.

. r- r-IFigure 13. AD7541 Response with: A = Intersil 2515
Cc = 15pF

INPUT SIGNAL WARNING

Because of the input protection diodes on the logic inputs, it is important that no voltage greater than 4V outside
the logic supply rails be applied to these inputs at any time, including power-up and other transients. To do so
could cause destructive SeR latch-up.

4-157

ICLS01SA/S019A/S020A
Quad Current Switch for
D/ A Conversion

FEATURES

GENERAL DESCRIPTION

• TTL Compatible: LOW-0.8V

Digital Threshold Control
Programmable Voltage Source
Meter Drive
X-Y Plotters

The Intersil ICL8018A family are high speed precIsion
current switches for use in current summing digital-to~
analog converters. They consistof four logically controlled
current switches and a reference device on a Single
monolithic silicon chip. The reference transistor, combined
with preciSion resistors and an external source, determines
the magnitude of the currents to be summed. By weighting
the currents in proportion to the binary. bit which controls
them, the total output current will be proportional to the
binary number represented by the input logic levels.
The performance and economy of this family make them
ideal for use in digital-to-analog converters for industrial
process control and instrumentation systems.

SCHEMATIC DIAGRAM

PIN DIAGRAM

HIGH-2.0V
,.
•
•
•

12 Bit Accuracy
40 nsec, Switching Speed
Wide Power Supply Range
Low Temperature Coefficient

APPLICATIONS:
• DfA-AID Converters
•
•
•
•

III
EQUIVALENT CIRCUIT

y+

MSB 2
LOGIC { BIT2
INPUTS BIT 3

LOGIC INPUTS
_ _ _- ,

r -_ _

BIT 4
5

~A~

BIT 3
4

BIT 2
3

BIT 1
2

y+
1

BIT4
COMPENSATION f E
TRANSISTOR c

L

012

9

6

::::}TO
PRECISION
BIT 3 RESISTORS
BIT4
BASE LINE

OUTLINE

DWGS
JD,PD

ORDERING INFORMATION
REFERENCE
TRANSISTOR

ACCURACY
Individual Devices
.01%
0.1%
1.0%
Matched Sets·
.01%
0.1%
1.0%

lOUT

BASE

6
10
11
12
13
EMITTER ,_BI_T_4__B_IT_3-'v~B_IT_2__
BI_T~1}
TO PRECISION RESISTORS
SDk
40k
20k
10k

MILITARY
TEMP RANGE
CERDIP

COMMERCIAL
TEMP RANGE
PLASTIC DIP

ICL8018AMJD
ICL8019AMJD
ICL8020AMJD

ICL8018ACPD
ICL8019ACPD
ICL8020ACPD

ICL8018AMXJD
ICL8019AMXJD
ICL8020AMXJD

ICL8018ACXPD
ICL8019ACXPD
ICL8020ACXPD

'NOTE: Units ordered in equal quantities will be matched such
that the Vbe'S of the 8019 will be within ±10mVof the 8018 compensating transistvr, and the Vbe'S of the 8020 will be within
±50mV. The ICL8018 - X matched sets consist of one 8018, one.
8019, and one 8020. TheaOl9-Xconlainsone8019andone8020,
. while the 8020 - X contains two 8020's. Units shipped as matched
sets will be marked with a unique set number.

4-158

ICLB01SA/S019A/S020A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .......................................................... ±20V
Logic Input Voltage ..................................... . ........... -2V to V+
Output Voltage ............................................... VSASELINE to + 20V
VSASELINE ........................................................... V - to +5V
Storage Temperature ......................................... -65° C to +150° C
Operating Temperature ICLB01BAM
ICLB019AM ........................... -55°C to +125°C
ICLB020AM
ICLB01BAC
ICLB019AC ............................... 0° C to +70° C
ICLB010AC
Lead Temperature (soldering 10sec) ..................................... 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
PARAMETER
Absolute Error
ICLB01BA
ICLB019A
ICLB020A
Error Temperature Coefficient
ICLB01BA
ICLB019A
ICLB020A

(4.5V:S V+:s 20V, V-

CONDITIONS

= -15V,

MIN

Supply Voltage Range
V+
VSupply Current (Vsupp
1+
1-

V @ pin 6

TYP

±2
±2
±2

Switching Time To Turn On LSB
Output Current (Nominall
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4 (LSB)

Logic Input Current
"0"
"1" !into device)
Power Supply Rejection
V+
V-

= 25°C,

VINHI = 5.0V
VINLO = O.OV

Settling Time To ± 1/2 LSB, RL = 1kO
8 BIT
12 BIT

Zero Output Current
Output Voltage Range
Input Coding-Complimentary Binary
(See Truth Table)
Logic Input Voltage
"0" (Switch ON)
"1" (Switch OFF)

TA

VIN

= 5.0V

= -5V)
MAX

UNITS

±.01
±0.1
±1

%

±5
±25
±50

ppm/DC

100
200

ns

40

ns

1.0
0.5
0.25
0.125
10

mA

VBASELINE +1V

50
+10

nA
V

O.B

V

-2
0.1

mA
p.A

2.IOUT <400nA
2.0
VIN
VIN

= OV
= 5V

-1.0
0.01

%N

.005
.0005
4.5
-10

5
-15

20
-20

V

7
1

10
3

mA

= ±20V)

4·159

ICLS018A/8019A/8020A
BASIC D/A THEORY

10.0 volts the maximum output would be

The majority of digital to analog converters contain the·
elements shown in Figure 1. The heart of the 01 A converter is
the logic controlled switching network, whose output is an
analog current or voltage proportional to the digital number
on the logic inputs. The magnitude of the analog output is
determined by the reference supply and the array of
precision resistors, see fig. 2. If the switching network has a
current output, often a transconductance amplifier is used to
provide a voltage output.
LOGIC INPUTS

REFERENCE

SWITCHING NETWORK

RESISTOR ARRAY

Figure 1: Elements of a D/A Converter

Nominal
Output
Current (mA)
1.875
1.750
1.625
1.500
1.375
1.250
1.125
1.000
0.825
0.750
0.625
0.500
0.375
0.250
0.125
0.000

Logic Input
0000
o () 0 1
001 0
001 1
o1 0 0
o10 1
o1 10
o1 1 1
1 0 0 0
1 0 0 1
101 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

Figure 2: Truth Table

:~:~x 10V. Sinc~

the numbers are extremely close for high resolution systems,
the terms are often used interchangeably.
The accuracy of a 01 A converter is generally taken to mean
the largest error of any output level from its nominal value.
The accuracy or absolute error is often expressed as a
percentage of the full scale output.
Linearity relates the maximum error in terms of the deviation
from the best straight line drawn through all the possible
output levels. Linearity is related to accuracy by the scale
factor and output offset. If the scale factor is exactly the
nominal value and offset is adjusted to zero, then accuracy
and linearity are identical. Linearity is usually specified as
being within ±1/2 LSB of the best straight line.
Another desirable property of O/A converter is that it be
monotonic. This simply implies that each successive output
level is greater than the preceding one. A possible worst case
condition would be '.when the output changes from most
significant bit (MSB) OFF, all other bits ON to the next level
which has the MSB ON and all other bits OFF, e.g., 10000 ...
to 01111.
In applications where a quad current switch drives a
transconductance amplifier (current to voltage converter),
transient response is almost exclusively determined by the
output amplifier itself. Where the quad output current drives
a resistor to ground, switching time and. settling time are
useful parameters.
Switching time is the familiar 10% to 90% rise time type of
measurement. Low capacitance scope probes must be used
to avoid masking the high speeds that current source
switching affords. The settling time is the elapsed time
between the application of a fast input pulse and the time at
which the output voltage has settled to or approached its
final value within a specified limit of accuracy. This limit of
accuracy should be commensurate with the r'lsolution of the
OAC to be used.
Typically, the settling time specification describes row soon
after an input pulse the output can be relied upon as accurate
to within ±1/2 LSB of an N bit converter. Since the 8018A
family has been desiged with all the collectors of the current
switching transistors tied together, the output capacitance is
constant. The transient response is, therefore, a simple
exponential relationship, and from this the settling time can
be calculated and related to the measured rise time as shown
in Figure 3.

DEFINITION OF TERMS
The resolution of a 01 A converter refers to the number of
logic inputs used to control the analog output. For example,
a 01 A converter using two quad current sources would be an
8 bit converter. If three quads were used, a 12 bit converter
would be formed. Resolution is often stated in terms of one
part in, e.g., 256 since the number of controlling bits is
related to total number of identifiable levels by the power of
2. The four bit quad has sixteen different levels (see Truth
Table) each output corresponding to a particular logic input
word.
Note that maximum output of the quad switch is 1 + 1/2+ 114
+ 1/8 = 1-718 = 1.875 rnA. If this series of bits were continued
as.1/16 + 1/32 + 1/64 ... .. 112 (n-l), the maximumoutput limit
would approach 2.0 rnA. This limiting value is called full scale
output. The maximum output is always less than the full
scale output by one least significant bit, LSB. For a twelve bit
system (reSolution 1 part in 4096) with a full scale output of

±1/2 LSB Error
Number of
Number of
Bits of
Resolution % Full Scale Time Constants Rise Times
.2 %
6.2
2.8
8
10
.05%
7.6
3.4
4.2
12
.01%
9.2
Rise Time (10%-90%) = 2.2 RL Celf
Figure 3: Settling Time vs. Rise Time Resistor Load

CIRCUIT OPERATION
An example of a practical circuit for the ICL8018A quad
qurrent switch is shown in Figure 4. The circuit can be
analyzed in two sections; the first generates very accurate
. currents and the second causes these c·urrents to be
switched according to input logic signals. A reference
current of 1251'A is generated by a stable reference supply
and a precision resistor. An op-amp with low offset voltage

4-160

ICLS018A/8019A/8020A
LOGIC INPUTS
r-------~A~-------,

BIT 4
5

BIT 3
4

BIT 2
3

- - ---

BIT 1
2

v+

VREF

RS

L

IREF

VOUT

IN914

Rs
10
SDk

SDk

11

12

13

40k

20k

10k

14

Figure 4: Typical Circuil

and low input bias current, such as the ICL8008, is used in
conjunction with the internal reference transistor, 06, to
force the voltage on the common base line, so that the
collector current of 06 is equal to the reference current. The
emitter current of 06 will be the sum of the reference current
and a small base current causing a drop of slightly greater
than 10 volts across the 80k resistor in the emitter of 06.
Since this resistor is connected to -15V, this puts the emitter
of 06 at nearly -5V and the common base line at one VSE
more positive at -4.35V typically.
Also connected to the common base line are the switched
current source transistors Of through 010. The emitters of
these transistors are also connected through weighted
precision resistors to -15V and their collector currents
summed at pin 8. Since all these transistors, 06 through 010,
are deSigned to have equal emitter-base voltages, it follows
that all the emitter resistors will have equal voltage drops
across them. It is this constant voltage and the preCision
resistors at the emitter that determine the exact value of
switched output current. The emitter resistor of 07 is equal to
that of 06, therefore, Ois collector current will be IREF or
1251'A. 08 has 40k in the emitter so that its collector current
will be twice IREF or 250I'A. In the same way, the 20k and 10k
in the emitters of 09 and 010 contribute.5 mA and 1 mA to the
total collector current.
The reference transistor and four current switching
transistors are designed for equal emitter current density by
making the number of emitters proportional to the current
switched.
The remaining circuitry provides switching signals from the
logiC inputs. In the switch ON mode, zener diodes D5
through D8, connected to the emitter of. each current switch
transistor 07 thru 010, are reverse biased allowing the
transistors to operate, producing preciSion currents
summed in the collectors. The transistors are turned off by
4-161

raising the voltage on the zeners high enough to turn on the
zeners and raise the emitters of the switching transistor. This
reverse biases the emitter base diode thereby shutting off
that transistor's collector current.
The analog output current can be used to drive one load
directly, (1 kfl to ground for FS = 1.875V for examplel or can
be used to drive a transconductance amplifier to give largel
output voltages.

EXPANDING THE QUAD SWITCH
While there are few requirements for only 4 bit D to A
converters, the 8018A is readily expanded to 8 and 12 bits
with the addition of other quads and resistor dividers as
shown in Figure 5.
To maintain the progression of binary weighted bit currents,
the current output of the first quad drives the input of the
transconductance amplifier directly, while a resistor divider
network divides the output current of the second quad by 16
and the output current of the third by 256.
e.g., ITotal= 1 x(1 +1/2+1/4+1/81+1/16(1 +1/2+1/4+1/81
+ 11256 (1 + 1/2 + 1/4+ 1/8)= 1 + 1/2 + 1/4+ 1/8+
1/16 + 1/32 + 1/64 + 1/128 + 1/256 + 1/512 +
1/1024 + 1/2048.
Note that each current switch is operating at the same high
speed current levels so that standard 10k, 20k, 40k and 80k
resistor networks can be used. Another advantage of this
technique is that since the current outputs of the second and
third quad are attenuated, so are the errors they contribute.
This allows the use of less accurate switches and resistor
networks in these positions; hence, the three accuracy
grades of .01 %, 0.1 %, and 1% for the 8018A, 8019A and
8020A, respectively. It should be noted that only the
reference transistor on the most significant quad is
required to set up the voltage on the common base line
joining the three sets of switching transistors (Pin 9>'

ICLS018A/8019A/8020A
ANALOG
VOLTAGE OUT

VREF

LOGIC ,INPUTS

LIREF
8019A
(0.1'1,)

8020A
(1.0%)

Figure 5: Expanding the Quad Switch

th!,! external zener will dominate the temperature
dependence of this scheme, however using a temperature
compensated zener minimizes this problem. Since as is
operating at a higher current density than the other
switching transistors, the temperature matching of VBE'S is
not optimum, but should be adequate for a simple 8 or 10 bit
converter.
The 8018A series is tested for accuracy with 10V reference
voltage across the precision resistors, implying use of a 10
volt zener. Using a different ,external zener voltage will only
slightly degrade accuracy if the zener voltage is above 5 or 6
volts.
When using other than 10 volt reference, the effects on logic
thresholds should also be noted (see logic levelS below). Full
scale adjustment can be made at the output amplifier.

GENERATING REFERENCE CURRENTS ZENER REFERENCE
As mentioned above, the 8018A switches cu~rents
determined by a constant voltage across the external
precision resistors in the emitter of each switch. There are
several ways of generating this constant voltage. One of the
simplest is shown in Figure 6. Here an external zenerdiode is
driven by the same current source line used to bias internal
Zener 011.
BIT 4
5

BIT 3'
4

BIT 2
3

BIT 1
2

v+
012

PNP REFERENCE

,...,--!-_-+-..---+__+ __+--+--<;8 IOUT
'-c>-it:--""'-1E::-="-t+-=-f+-=-+-t--="-=-f---'- - - - TO
OTHER
QUADS

Another simple reference scheme is shown in Figure 7. Here
an external PNP transistor is used to buffer a resistor divider.
In this case, the -15 volt supply is used as a reference.
Holding the V- supply COnstant is not too difficult since the
8018A is essentially a constant current load. In this scheme,
the internal compensation transistor is not necessary, since
the VBE matching is provided by the emitter-base junction of
the external transistor. A small pot in series with the divider
facilitates full scale output adjustment. A capacitor from
base to collector of the external PNP will lower output
impedance and minimize transient effects.

FULL COMPENSATION REFERENCE
10k

~isv

Figure 6: Simple Zener Reference

The zener current wi,II' be typically 1 mA per quad. The
compensation transistor as is connected as a diode in series
with tne external zener. The VBE of this transistor will
approximately match the VBE'S of the current switching
transistors, thereby forcing the external zener voltage across
each of the external resisto,rs. Thetemperature coefficient of

For high accuracy, low drift applications, the reference
scheme of Figure 4, offers excellent performance. In this circuit, a high gain op-amp compares two currents. The first is a
reference, current generated in Rs by the temperature compensated zener and the virtual ground at the non-inverting opamp input. The second is the collector current of the
reference transistor as, provided on the quad switch. The
output of the op-amp, drives the base of 06 keeping its
collector current exactly equal to the reference current.
Since the switching transistor's emitter current densities are
equal and since the precision resistors are proportional, all
of the switched collector currents will have the proper value.

4-162

.D~DIl.

ICLB01SA/S019A/S020A
BIT 4

BIT 3

BIT 2

BIT 1

y+

5

4

3

2

1
D12

a

r--I-.--t-......-t-~--t----t---t----<>IOUT
--TO
OTHER
QUADS
012

10k

10

11

12

aOk

40k

20k

13

14

10k

-15Y

Figure 7: PNP Reference

+15Y

3&0

OUTPUT OFFSET
ADJUST
10M

~f

2k

5k

10k

-15Y

I

30PF

Rn:
14.0625k
R14
lk

51k

1000pF

R9

R4

R3

R2

R1

aOk

aOk

40k

20k

10k

Y-

Rs

R7

R6

Rs

aOk

40k

20k

10k

Y-

R13

R12

Rl1

RlO

&Ok

40k

20k

10k

-15Y
NOTE: ALL RESISTORS RATIO TO R1
UNLESS OTHERWISE NOTED.

TOLERANCE TABLE
10k
0.1% ABS
0.0122'10
20k
40k
0.0244'10
&Ok
0.0488%
0.096'10
10k

R.

20k
40k
eOk
eOk

R10
R11

20k

R6
R7
Rs

10k

Figure 8

4·163

0.195%
0.391%
0.781%
0.1%
0.5% ABS
RATIO TO R10 1%

40k
aOk
lk
937.50
14.062Sk
14.0625k

RATIO TO Rl0 1%
RATIO TO R10 1'10
l%ABS
l%ABS
RATIO TO R15 1%
RATIOTOR'40.1%

v-

ICLS018A/8019A/8020A
The op-amp feedback loop using the intemal reference
transistor will maintain proper currents in spite of VSE drift,
beta drift, resistor drift and changes in V-.Using this circuit,
temperature drifts of 2 ppm/oC are typical. A discrete diode
connected as shown will keep Q6' from saturating and
prevent latch up if V- is disconnected.
In any reference scheme, it is advisable to capacitively
decouple the common base line to minimize transient
effects. A capacitor, .001!'F to .1!,F from Pin 9 to analog
ground is usually sufficient.

IMPROVED ACCURACY
As a final note on the subject of setting up reference levels, it
should be pOinted out that the largest contributor of error is
the mismatch of VSE'S of the current switching transistors.
That is,' if all the VSE'S were identical, then all precision
resistors would have exactly the same reference voltage
across them. A one millivolt mismatch compared with ten
volt reference across the precision resistors will cause a .01 %
error. While decreasing the reference voltage will decrease
the accuracy, the voltage can be increased to achieve better
than .01% accuracies. The voltage across the emitter
resistors can be doubled or tripled with a proportional
increase in resistor values resulting in improved absolute
accuracy as well as improved temperature drift performance.
This technique has been used successfully to implement up
to 16 bit 01 A converters.

PRACTICAL D/A CONVERTERS
The complete circuit for a high performance 12 bit D/A
converter is shown in Figure B. This circuit uses the "full
compensation reference" described above to set the base
line drive at the proper level, the temperature compensated
zener is stabilized using an op-amp as a regulated supply,
and the circuit provides a very stable, preCise voltage
reference for the D/A converter. The 16:1 and 256:1 resistor
divider values are shown for a straight binary system; for a
binary coded decimal system the dividers would be 10:1 and
100:1 (BCD is frequently encountered in building programmable voltage·sources).
The analog output current of the B01BA current switches is
converted to an output voltage using the B017 as shown. The
output amplifier must have low input bias current (small
compared with the LSB current), low offset voltage and offset
voltage drift, high slew rate and fast settling time. The input
compensatioh shown helps improve pulse response by
providing a finite impedance at high frequencies for a point
that is virtual grouhd at DC.
An alternative bias scheme is shown in Fi\lure 9. In this case,
the bias at the common base line is fixed by inverting op-amp
A4, the gain of which is adjusted to give -5.0 volts at the
emitter of the reference transistor. With the bias at the common base line fixed, the regular circuit of A1 uses the internal
reference transistor and drives the bus connecting all the
precision resistors. This isolates the precision resistors from
V- fluctuations. Zener 03 and constant current source Q1
keep the regulating BOOB op-amp in mid-range. There are
several alternative bias schemes depending on power
supplies available. If -20 volts is used for V-, the bottom of
the precision resistorwill be at-15 and operation will be the
same as the standard circuit. If only -15V is available for Vthe gain of the output transcondUctance amplifier can be
increased by 30% to allow use of a smaller switching currents
with 7 volts across the precision resistors. .

MULTIPLYING DAC
The circuit of Figure 9 is also convenient to use as a one
quadrant multiplying D/A converter. In a multiplying DAC,
the analog output is proportional to the product of a digital
number and an analog signal. The digital number drives the
logic inputs, while the analog signal replaces the constant
reference voltage, and produces a current to set up the
regulating BOOB op-amp. To vary the magnitude of currents
being switched, the voltage across all the 10k, 20k, 40k and
BOk resistors must be modulated according to the analog
input. An analog input of 0 to +10 volts and an BOk resistor at
the input to the BOOB will fulfill this requirement.

CALIBRATING THE 12 BIT D/A CONVERTER
1. With all logic inputs high (ones) adjust the output amplifier
offset for zero volts out.
2. Put in the word 0000 1111 1111 (Quad 1 maximum output
Quad 2 and 3 off) and adjust full scale pot for Vo of 15/16
(10V) where full scale output is to be 10 volts.
3. Put in the word 1111 0000 1111 and trim the Quad 2 divider
for Vo of 15/256 (10V). This adjustment compensates for
VSE mismatches between quads although matched sets
are available (see data sheet).
4. Put in the word 11111111 0000 and trim the Quad 3 divider
for Vo of 15/4096 (10V).
5. Finally, with all bits ON (all O's) readjust the full scale
factor pot for
Vo = 4095/4096 (10V)

SYSTEM INTERFACE REQUIREMENTS
Using the B01BA series in practical circuits requires
consideration of the following interface requirements.
Logic Levels: The B01BA is designed to be compatible with
TTL, DTL and RTL logic drive systems. The one constraint
imposed on the external voltage levels is that the emitters of
the conducting current switch transistors be in the vicinity of
-5V; this will be the same as the voltage on Pin 6 if the
reference transistor is used. When using other than -5V at
Pin 6, the direct bearing on logic threshold should be
considered.
Power Supplies: One advantage of the ICLB01BA is its
tolerance of a wide range of supply Voltage. The positive
supply voltage need only be large enough (greater than
+4.5V) to keep Q11 out of saturation, and the negative supply
needs to be rnore negative than -10V to ensure constant
current operation of Q12. The maximum supply voltage of
±20V is dictated by transistor breakdown voltages. It is often
convenient to use ±15V supplies in systems with op-amps
and other I.C.'s. These suppli.es tend to be better regulated
and free from high current transients found on supplies used
to power TTL Logic. As with any high speed circuit, attention
to layout and adequate power supply decoupling will
minimize switching effects.
Ground: High resolution D/A, e.g., 12 bits require fairly large
logic drive currents. The change from all bits ON to all bits
OFF is a considerable change in supply current being
returned to ground. Because of this, it is usually advisable to
maintain separate ground pOints for the analog and digital
, sections.
Resistors: Each quad current switch requires a set of
matched resistors scaled proportional to their binary
currents as R, 2R, 4R and BR. For a 10V resistor voltage drop
and "2 mA" full scale output current, resistor values of 1Ok,
20k, 40k and BOk are convenient. Other resistor values can be
used, for example, to iricrease total output current. The
4·164

ICLS018A/8019A/8020A
individual switched currents can be increased up to 100% of
their nominal values. The overall accuracy of the complete
01 A converter depends on the accuracy of the reference, the
accuracy of the quad current switch and tolerance of resistor
matching. Because of the binary progression of switched
currents, the tolerance of 80k/1 Ok match can be twice that of
the 40k/10k which, in turn, can be twice the tolerance of the
20k/10k ratio and still have equal output current errors. The
current dividers between quads allows. use of less well
matched sets of resistors further along in the O/A just as it
allows use of .01%, 0.1%, and 1% accurate quad current
switches. There are several manufacturers producing the
complete precision resistor networks required to implement
up to 12 bit O/A converters. Contact Intersil for additional
information. '
360

'Resistor Ladder Networks are manufactured by the
following companies:
Micro Networks Corporation
5 Barbara Lane
Worcester, Massachusetts 01604
Tel. (617) 756-4635
Allen-Bradley Company
1201 S. Second Street
Milwaukee, Wisconsin 53204
Tel. (414) 671-2000
Hycomp, Inc.
146 Main Street
Maynard, Massachusetts 01754
Tel. (617) 897-4578

+15V

2k

+15V

20k

~>--'V°'vUT,\P~U~Tt-0_F_F_SE~Tt-_-*--l

f

ADJUST
10M

5k

EOUT

10k
-15V

130P~

~':'~~Mi

VREF

MULTIPLYING
o TO 10V

3.9k

14.0625k

13k

14.0625k

lk
80k

937.5

-4.35V

49k

MULTIPLY
DAC

FI

lOO0P

Figure 9

-20V

For further information see the following Applications Bulletins.
A016 "Selecting AID Converters" by Dave Fullagar.
A018 "Do's and Don'ts of Applying AID Converters'" by Peter Bradshaw and Skip Osgood.
A020 "A Cookbook Approach to High Speed Data Acquisition and Microprocessor Interfacing" by Ed Sliger.

4-165

ICLS052/1CL7104
and ICLS068/1CL71 04
16/14/12 Bit Binary A/D
.Converter Pairs for ~Processors
FEATURES

GENERAL DESCRIPTION

• 16 bit binary three-state latched outputs plus
polarity and overrange. Also 14 and 12 bit versions.
• Ideally suited for interface .to UARTs,
microprocessors, or other complex circuitry.
• Conversion on demand or continuously.
• Handshake byte-serial transmission synchronouslt
or on demand.
• Guaranteed 'zero reading for zero volts input.
.• True polarity at zero count for precise null detection.
• Single reference voltage for true ratio metric
operation.
• Onboard clock and reference.
• Auto-Zero; Auto-Polarity
• Accuracy guaranteed to 1 count.
• All outputs .TTL compatible.
• ±10V analog input range
• Status signal available for external sync, A/Z in
preamp, etc.

The ICL7104, combined with the ICL8052 or ICLS06S, forms
a member of Intersil's high \, performance AID converter
family. The 16-bit version, the ICL7104-16, performs the
analog switching and digital function for a 16-bit binary AID
converter, with full three-state output, UART handshake
capability, and other outputs for a wide range of output
interfacing. The ICL7014-14 and ICL7104-12 are 14 and 12bit versions. The analog section, as with all Intersil's
integrating converters, provides fully precise Auto-Zero,
Auto-Polarity (including ±O null indication), single referenc(>
operation, very high input impedance, true input integration
over a constant period for maximum EMI rejection, fully
ratiometric operation, over-range indication, and a medium
quality built-in reference. The chip pair also offers optional
input buffer gain for high sensitivity applications, a built-in
clock oscillator, and output signals for providing an external
Auto-Zero capability in preconditioning circuitry, synchronizing external multiplexers, etc.

PIN CONFIGURATIONS
/-~-__-flj441 ~J~GRATOR
COMP
OUT
12 :~T~GRATOR

REF
CAP
REF
PASS

11

:~I~~GRATOR

BUFFER
OUT

REF
OUT
REF
SUPPLY

v..

V..

v..

DIG GND
STTS
POL.
O.R.
BIT 16
BIT 15
BIT 14
BIT 13
BIT 12
BIT 11
BIT 10
BIT 9
BIT8
BIT1
BIT6
BIT5
BIT4
BIT 3
BIT 2

DIG GND
STTS
POL
O.R.
BIT 14
BIT 13
BIT 12
ICL7104
BIT 11
·16
BIT 10
BIT9
N.C.
N.C.
BIT8
BIT7
BIT6
SITS
BIT4
BIT 3
BIT2

,

(OUTLINE DWGS DD,JD,PD)

DIGGND
STTS
POL
O.R.
BIT 12
BIT 11
BIT 10
BIT9
N.C.
N.C.
N.C.
N.C.
BIT 8
BIT 7
BIT 6
11

v~

,

COMP IN
REFCAP 1
VREF
AZ

ANALOG GND
REFCAP 2
BUF IN
ANALOG liP

v+

CElLO
SEN
R/H
MODE
CLOCK 2
CLOCK 1

11
12
13
14
15
16

BIT5
BIT4
BIT 3
BIT2

'"

NOTE
LBEN
BIT 1

r.;;;r:;;or::;;;-:;,-,

(OUTLINE DWGS DL,JL,PL)

ORDERING INFORMATION
Part
805~

8052
8052A
8052A
8066
B06BA

Packag~

Temp. Range
O'C
O'C
O'C
O'C
O'C
O'C

10
10
10
10
to
10

70'C
70'C
70'C
70'C
70'C
70'C

14·Pin
14·Pin
14·Pin
14·Pin
14·Pin
14·Pin

Plaslic DIP
Ceramic DIP
Plaslic DIP
Ceramic DIP
CERDIP
CERDIP

Order Number
ICL8052CPD
ICL8052CDD
ICL8052ACPD
ICL8052ACDD
ICLB068CJD
ICL8068ACJD

4·166

Part

Temp. Range

710412·811
710412·8il
710412·8il
710414·811
710414·8il
710414·811
710416·8il
710416·8il
710416·8il

O'C 10 70'C
O'C 10 70'C
O'C 10 70'C
O'C 10 70'C
O'C 10 70'C
O'C 1070'C
O'C 10 70'C
O'C 10 70'C
O'C 10 70'C

Package
40·Pin
40·Pin
40·Pln
40·Pin
40·Pin
40·Pin
40·Pin
40·Pin
40·Pln

CERDIP
PlaSlic DIP
Ceramic DIP
CERDIP
PlaSlic DIP
Ceramic DIP
CERDIP
Plastic DI P
Ceramic DIP

Order Number
ICL7104·12CJL
ICL7104·12CPL
ICL7104·12CDL
ICL7104·1.4CJL
ICL7104·14CPL
ICL7104·14CDL
ICL7104·16CJL
ICL7104·16CPL
ICL7104·16CDL

8052/7104 8068/7104
ABSOLUTE MAXIMUM RATINGS
Power Dissipation 1 ............................. 500mW
Storage Temperature .................. --65°Cto+150°C

8052, 8068

7104

Supply Voltage ................................... ±18V
Differential Input Voltage(8068) ................... ±30V
(8052) .................... ±6V
Input Voltage2 ................................... ±15V
Output Short Circuit Duration,
All Outputs 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
Operating Temperature .................... 0° C to +70° C
Lead Temperature (Soldering, 10 Sec.) ............ 300°C

V+ Supply (GND to V+) ............................ 12V
V++ to V- .......................................... 32V
Positive Supply Voltage (GND to V++) .............. 17V
Negative Supply Voltage (GND to V-I ............... 17V
Analog I~,put Voltage (Pin 32-39)4 .............. V+ to VDigital Input Voltage ........................... V++0.3V
(Pins 2-30)5 ................................ GND -o.3V

Notes:
1: Dissipation rating assumes device is mounted with all leads welded or soldered to printed circuit board in ambient temperature below +70° C.
For higher temperatures, derate 1OmW/o C.
2: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
3: Short circuit may be to ground or either supply. Rating applies to +70°C ambient temperature.
4: Input voltages may exceed the supply VOltages provided the input current is limited to ±100"A.
5: Connecting any digital inputs or outputs to voltages greater than V+ or less than GND may cause destructive device latchup. Forthis reason
it is recommended that no inputs from sources not on the same power supply be applied to the ICL7104 before its power supply is
established.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the devices. This is a stress rating only and functional operation of
the devices at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

7104 ELECTRICAL CHARACTERISTICS
CHARACTERISTICS

(v+

= +5V, V++ = +15V,

V-

= -15V,

Ta

= 25°C)

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

CLOCK 1
COMP IN (Note 1)

hN
liN

Vin -- +5V to OV
Yin OV to +5V

±2
10

±7'
±0.001

±30
+10

~A

Inputs
with Pulldown

MODE

IIH
IlL

Vin
Vin

+5V
OV

+1
10

+5
±0.01

+30
+10

~A

Inputs
with
Pullups

SEN, R/H
LBEN, iiillbl';j,
HBEN, CE/LD

IIH
hL

Yin - +5V
Vin OV

10
30

±0.01
5

+10
1

~A

Input High Voltage

All Digital Inputs

V,H

2.5

2.0

-

V

Input Low Voltage

All Digital Inputs

V,L

1.5

1.0

V

Digital
Outputs
Three-Stated
On

~13 EN

VOL
VOH
VOH

10L - 1.6 rnA
lO~A
10H
240~A
10H

.4

2.4

.27
4.5
3.5

V
V
V

10

±.001

+10

~A

.3
3.3
0.5
4.5
.27
3.5

.4

V
V
V
V
V
V

Clock Input

Comparator liP

.

I

(Note 2)

MB EN 116 only}
} (Note 3)
HB EN
CE/LD

BIT n, POL. OR

10L

0'5 Vout:> V+

Non-Three-State
Digital
Output

ST"!:S

VOL
VOH
VOL
VOH
VOL
VC)H

10L - 3.2 rnA
10H -400~A
10L -- 320~A
320~A
10H
10L 1.6 rnA

CLOCK 2
CLOCK 3 1-12, -14 ONLY}
Switch 1
Switches 2,3
Switches 4,5,6,7,8,9
Switch Leakage

IOH -

320~A

2.4

2.4

-

rDS(on)
rOS(on)
rOS(on)
IO(oft)

Clock

Clock Freq. (Note 41

Supply
Currents

+5V Supply Current
All outputs high impedance
+15V Supply Current
15V Supply Current

1+

Freq. - 200 kHz

1++
I

Freq.
Freq.

Supply Voltage
Range

Logic Supply
Positive Supply
Negative Supply

V+
V++
V

Note 5

Note
Note
Note
Note
Note

~A
~A

BIT n, POL, OR

Digital
Outputs
Three-Stated Off

Switch

-

~A

-

25k
4k
2k
15

DC

200

400

kHz

200

600

~A

.3
25

1.0
200

mA

+11.0
+16.0
10.0

V
V
V

200 kHz
200 kHz
4.0
+10.0
16.0

1: This spec applies when not In Auto-Zero phase.
2: Apply only when these pins are inputs, i.e., the mode pin is low. and the 7104 is not in handshake mode.
3: Apply only when these pins are outputs, i.e., the mode pin is high or the 7104 is in handshake mode.
4: Clock circuit shown in Figs. 10 and 11.
5: V+ must not be more positive than V++.

4-167

.4

20k
10k

II
!l
!l
pA

~A

II

8052/7104 8068/7104
8068 ELECTRICAL CHARACTERISTICS

(Vsupp = -+15V unless otherwise specified)

8068

I

SYMBOL

Ay
SR
GBW
Isc

Input Offset Voltage
Input Current (either input) (Note 1)
Common-Mode Rejection Ratio
Non-Linear Component of CommonMode Rejection Ratio (Note 21
Large Signal Voltage Gain
Slew Rate
Unity Gain Bandwidth
Output Short-Circuit Current

AYOL·
+VO
Vo

Small-signal Voltage Gain
Positive Output Voltage Swing
Negative Output Voltage Swing

Vos

liN
CMRR

CONDITIONS I MIN I TYP I
EACH OPERATIONAL AMPLIFIER

CHARACTERISTICS

VCM -OV
VCM -OV
VCM - ±10V

70

VCM =±2V
RL - 50k!}

20,000

20
175
90

MAX

I
I

\

806SA
MIN

I

TYP

I

20
80
90

65
250
70

110

MAX

UNITS

65
150

mV
pA
dB

110
20,000

6
2
5

..

VN
6
2
5

10

VII'S

MHz
mA

10

COMPARATOR AMPLIFIER

I RL - 30k!}

I

I
I

I

+12
-2.0

I
I

4000
+13
-2.6

I

I

I
I

+12
2.0

I
I

+13
2.6

I

I

I
I

1
I

VN
V
V

VOLTAGE REFERENCE

II

Vo
Ro
TC
Vsupp
Isupp

Output Voltage
Output Resistance
Temperature Coefficient
Supply Voltage Range
Supply Current Total

1.75
5
50

1.5
,

±10

8052 ELECTRICAL CHARACTERISTICS

Vos

liN
CMRR

Av
SR
GBW
Isc

1.60

±16
14

±10

8052

Input Offset Voltage
Input Current (either input) (Note 11
Common~Mode RejectiOn Ratio
Non-Linear Component of CommonMode Rejection Ratio (Note 21
Large Signal Voltage Gain
Slew Rate
Unity Gain Bandwidth
Output Short-Circuit Current

8

±16
14

V
ohms
ppm/oC
V
mA

MAX

I
I UNITS

VCM -OV
VCM -OV
VCM -±10V

7.0

VCM = ±2V
RL - 10k!}

20,000

8052A

I

CONDITIONS I MIN I TYP I MAX
EACH OPERATIONAL AMPLIFIER

CHARACTERISTICS

1.90

1.75
5
40

(Vsupp = ±15V unless otherwise specified)
I

SYMBOL

2.0

20
5
90

I

MIN

I

TYP

I

20
2
90

75
50
70

110

mV
pA
dB

75
10

110

.

20,000
6
1
20

6
1
20

100

VN
VII'S

MHz
mA

100

COMPARATOR AMPLIFIER

AYOL
+VO
Vo

I Small-signal Voltage Gain
I Positive Output Voltage Swing
Negative Output Voltage Swing

I'RL- 30k!}
I

+12
2.0

I

4000
+13
2.6

I
I

I
I

I

I

+12
2.0

I
I

I

+13
2.6

I
I

I

I

VN
V
V

VOLTAGE REFERENCE

Vo
Ro
TC
Vsupp
Isupp

Output Voltage
Output Resistance
Temperature Coefficient
Supply Voltage Range
Supply Current Total

1.5

,1.75
5
50

±10
6

Note 1:

2.0

1.80

±16
12

±10

1.75
5
40
6

1.90

±16
12

V
ohms
ppmfOC
V
rnA

The input bias currents are junction leakage currents which approximately double for every 10° C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal
operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. TJ =TA +OjA Pd
,where OjA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
Note 2: This is the only component that causes error in dual-slope converter.

4-168

8052/7104 8068/7104
SYSTEM ELECTRICAL CHARACTERISTICS: 8068/7104
(V++ = +15V, V+ = +5V, v_ = -15V Clock Frequency = 200KHz

Zero :rnput Reading

CONDITIONS
Yin "'"

O.DV

Full Scale
Ratio~etric

Reading (1)

4.000V

~

4.000V

Yin - VRef

Full Scale
linearity over ± Full Scale
(error of reading from
best straight linel

~

MIN
-.000
7FF

Noise (P-P value not
exceeded 95% of time)
Leakage Current at Input (2)
Zero Reading Drift

±.OOO

MAX
+.000

MIN
-0.0000

800

801

1FFF

TYP

Reading

0.2

-4V S Vin s:; +4V

Differential, Linearity
(difference between worse
-4V S Yin S +4V
case step of adjacent counts
and ideal step

Rollover error (Difference in
reading for equal positive &
negative voltage near full
scale)

TYP

8068A17104-16
MAX
UNITS
TYP
MAX
MIN
±O.OOOO +0.0000 -0.0000 ±O.OOOO +0.0000 Hexadecimal
Reading
8001
Hexadecimal
2000
2001
7FFF
8000

8068A17104-14

8068A17104-12
CHARACTERISTICS

1

0.5

.01

-Yin == +Vin "" 4V

1

0.5

.01

1

.01

LSB

LSB

0.2

1

0.5

1

0.5

1

3
200
1

265
5

2
100
0.5

165
2

2
100
0.5

165
2

2

5

2

5

2

5

LSB

Yin - OV

Full scale

~

4.000V

OV
Yin = OV
Yin =

~V

pA
~VI'C

DOC -;; TA S 70°C
Scale Factor Temperature (3) Vin - +4V
Coefficient
0"TA,,50°C

ppm/oC

(ext. ref. 0 ppmfOCI

SYSTEM ELECTRICAL CHARACTERISTICS: 8052/7104
(V++ = +15V, v+ = +5V, v_ = -15V Clock Frequency = 200KHz
CHARACTERISTICS
Zero Input Reading

CONDITIONS
Vin - O,OV

Full Scale
Ratio,metrjc Reading (3),

Differential Linearity
(difference between worse
-4V:S Vin :$ +4V
case step of adjacent counts
and ideal step)
Roliover error (Difference in
reading for equal positive &
negative voltage near full
scale)
Nojse (P-P value nQt
exceeded 95% of time)

-Vin

-= +Vin

800

801

1FFF

2000

2001

7FFF

8000

8001

"" 4V

Hexadecimal

Reading

4.000V

-4V::; Vin ::; +4V

UNITS
Hexadecimal

Reading
7FF

~

8052A/71 04-14
8052A17104-16
MAX
MIN
TYP
MIN
TYP
MAX
-0.0000 ±O.OOOO +0.0000 -0.0000 ±O.OOOO +0.0000

4.000V

Yin - VAef

Full Scale
Linearity over ± Full Scale
(error of reading from
best straight line)

~

8052/7104-12
MIN
TYP
MAX
-.000
±.OOO
+.000

0.2

1

.01

0.2

0.5

1

.01

1

0.5

20
50
30
1

3

0.5

1

.01

LSB

LSB

1

0.5

1

80
5

30
20
0.5

30
2

30
20
0.5

30
2

15

2

5

2

5

LSB

Vin - OV

Full scale
Leakage Current at Input (2)

Vin - OV

Zero Reading Drift

Vin - OV

~

4.000V

~V

pA
~vrc

Q°:STA:S70°C
Scale Factor Temperature
Coefficient

Vin - +4V

O:s TA:S 70°C

ppm/oC

(ext. ref. 0 ppmr CI

Note 1:
Note 2:

Note 3:

Tested with low dielectric absorption integrating capacitor.
The input bias currents are junction leakage currents which approximately double for every 10° C increase in the junction temperature, TJ. Due to limited production test time, the input bias currents are measured with junctions at ambient temperature. In normal
operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, Pd. T J = TA +BjA Pd
where BjA is the thermal resistance from junction to ambient. A heat sink can be used to reduce temperature rise.
The temperature range can be extended to 70° C and beyond if the Auto-Zero and Reference capacitors are increased to absorb the
high temperature leakage of the 8068. See note 2 above.

4-169

II

8052/7104· 8068/7104

OR

OR

POL

POL

Mal

a052AI
8068A

a052A1
a068A

7104

Mal

7104

~18

UI

LSI
1052A1
aoaBA

7104
-16
CONTROL

CONTROL

: --t= or CHIP SELECT 2

'------+--+--~-

8052A1
a068A

II

7104

Full 18 Bit Three State Output
UI'----I

CONTROL

Various Combinations of Byte Disables

AC CHARACTERISTICS (V++ = +15V. V+ = +5V. V- = -15V)
CElLO
As INPUT

AliEN
AS INPUT

MIrniI
AS INPUT

LlIEN
AS INPUT
HIGH BYTE
DATA
tdac

~~~~t~ BYTE

-----------,...---------------< ~:z.~ }--------

LOW BYTE
ENABLE
-------

~ HIGH IMPEDANCE

TABLE 1: Direct Mode Timing Requirements (NQte: Not tested in production)
SYMBOL
lb••
Idab
t dhb
toea

tdac
t dhc

tewn

DESCRIPTION
XBEN Min. Pulse Width
Data Access Time
from XBEN
Data Hold Time
from XBEN
CElLO Min. Pulse Width
Data Access Time
from CElLO
Data Hold Time
from CE/LD
CLOCK 1 High Time

MIN
400

450

1250

4·170

TYP

MAX

UNITS

300

300

400

200
350

250

350

450

280

350

1000

ns

.D~Dll

8052/7104 8068/7104
TABLE 2: Handshake Timing Requirements

NAME
tmw
tsm
tme
tmb

DESCRIPTION
MODE Pulse (minimum)
MODE pin set-up time
MODE pin high to low Z CEILD high delay
MODE pin high to XBEN low Z (high) delay
CLOCK 1 high to CEILD low delay
CLOCK 1 high to CEILD high delay
CLOCK 1 high to XBEN low delay
CLOCK 1 high to XBEN high delay
CLOCK 1 high to data enabled delay
CLOCK 1 low to data disabled delay
Send ENable set-up time
CLOCK 1 high to XBEN disabled delay
CLOCK 1 high to CEILDdisabled delay
CLOCK 1 High Time

!cel
!ceh
!cbl
!cbh
tedh
tedl
tss
tebz
!cez
tewh

MIN

TYP

1250

20
-150
200
200
700
600
900
700
1100
1100
-350
2000
2000
1000

MAX

UNITS

ns

II
H

CL,OCK 1 (PIN 25)

L
EITHER:
MODE PIN
OR:

j ---.--"",

INTERNAL LATCH
PULSE IF MOOE "HI".

INTERNAL MODE

---.------~,,---------I
~-----IGNORED

. ---- -----------._ .

UART
NORM----~--~~~~

SEN
(EXTERNAL SIGNAL)

O/R,POLOl-14

BITS 1-5

..

__

----_4----~----~-----+---- .~J.~·--~-- ~(::::~DA~T~A~V~A~LI§D~,S~T~A~B~t:::>~--~---4--~--THREE-STATE _

HANDSHAKE MODE TRIGGERED BY -----OR---14, -12 BIT VERSION SHOWN

-16 HAS EXTRA (MBEN) PHASE

Timing Relationships In Handshake Mode

4-171

THREE-STATE W PULLUP

~

8052/7104 8068/7104
TABLE 3: Pin Assignment and Function Description
PIN
1

2

STTS

4

POL

5

OR

6

BIT 16
BIT 14
BIT 12
BIT 15
BIT 13
BIT 11

8

9

10

11

12

13

14
15
16
17
18
19
20
21
22

BIT 14
BIT 12
BIT 10
BIT
BIT
BIT
BIT
BIT
nc

13
11
9
12
10

BIT 11
BIT9
nc
BIT 10
nc
nc
BIT9
nc
nc
BIT8
BIT7
BIT6

24

HBEN

DESCRIPTION

PIN
25

Positive Supply Voltage
Nominally +15V
Digital Ground .OV, ground
return
STaTuS output .HI during
Inte\lrate and Deintegrate
until data is latched .LO
when analog section is in
Auto-Zero configuration.
POLarity. Three-state output. HI for positive input.
OverRange. Three-state
output.
-16
-14
-12
-16
-14
-12
-16
-14
-12
-16
-14
-12
-16
-14
-12
-16
-14
-12
-16
-14
-12
-16
-14
-12

BIT !?
BIT4
BIT 3
BIT 2
BIT 1
LBEN

MBEN
23

OPTION

GND

3

7

II

SYMBOL
VI++I

(Mosi significant bitl

26
27

SYMBOL
CLOCK1
CLOCK2
MODE

DESCRIPTION
Clock input. External clock or oscillator.
Clock output. Crystal orRC oscillator.

Input LO;Direct output mode where
[Em'ii act as
inputs directly controlling byte outputs.
If pulsed HI causes immediate entry into
handshake mode (see Figure 91.
If HI, enables CEILD, HBEN, MBEN, and
LBEN as outputs. Handshake mode
will be entered and data output as in
Figures 7 & 8 at conversion completion.
Run/Hold; Input HI-conversions continuously performed every 217 1-161
215 1-141 or 213 1-121 clock pulses.
Input LO :onversion in progress
complet&J, converter will stop in
Auto-Zero 7 counts before·inputintegrate.
Send-ENable: Input controls timing
of byte transmission in handshake
mode. HI indicates·'send'.
Chip-Enable/LoaD. With MODE (pin 271
LO, CEIID serves as a master output
enable; when HI, the bit outputs and
POL, OR are disabled. With MODE HI,
pin serves as a LoaD strobe (-ve
gOingl used in handshake mode. See
Figures 7 & 8.
Positive Logic Supply Voltage.
Nominally +!1V.
ANalog INput. High side.
BUFfer INput to analog chip
(ICL8052 or ICL80681
REFerence CAPacitor (negative sidel
ANalog GrouND. Input low side and
reference low side.
Auto-Zero node.
Voltage REFerence input Ipositive sidel
REFerence. CAPacitor (positive sidel
COMParator INput from 8052/8068
Negative SupplyVoltage. Nominally-15V.

CE/ITi, HBEN, Ml3Ei\l, and

28

RIH

29

SEN

30

CEILD

31

V(+I

32
33

AN.IN
BUF IN

34
35

REFCAP2
AN.GND.

36
37
38
39
40

A-Z
VREF
REFCAP1
COMP-IN
VH

j

---~

Data Bits, Three-state
outputs. See Table 4 for
format of ENables and
bytes.
HIGH = true

-------

-16
-14
-12

HBEN

-16

CLOCK3

-14
-12

Least significant bit
Low Byte ENable. If not in
handshake mode (see pin 271
when LO (with CEIID, pin
301 activates low-order
byte outputs, BITS 1-8
When in handshake mode
(see pin 271, serves ,as a
lOW-byte flag output. See
Figures 8, 9 and 10.
Mid Byte ENable. Activates
BITS 9-16, see LBEN (pin 221

CElLO
1104·16 POL CIR 816 815 814 813 812 811 810 89

7104·14
7104-12

High Byte ENable. Activates
BITS 9-14, POL, OR, see
LBEN (pin 221
High Byte ENable.
Activates POL, OR, see
LBEN (pin 221.
RC oscillator pin. Can be
used as clock output.

POL O/R 814 813 812 811 810 89
POL O/R
812 811 810 89

88

87

86

85

84

88

B7

88

B7

83

82

B1

86

85

86

85

84

83

82

81

84

83

82

81

TABLE 4: Three-State Byte Formats and ENable Pins.

4·172

8052/7104

8068/7104

Fig. 1 shows the functional block diagram of the operating system. For a detailed explanation, refer to fig. 2 below.
+15V

AINT

-aUF IN

aUF OUT

-JNT IN
• NB 16 bit

version shown;
14 and 12 bit
versions differ
In pinout here.

23

MBEN'

I

CONTROL LOGIC

R/H

Figure 1: B052A IB06BAI/7104 16/14/12 Bit AID Converter Functional Block Diagram

DETAILED DESCRIPTION
Analog Section
Figure 2 shows the equivalent Circuit of the Analog Section
of both the ICL7104/8052 and the ICL7104/8068 in the 3
different phases of operation. If the Run/Hold pin is left open
or tied to V+, the system will perform conversions at a rate

determined by the clock frequency: 131,072 for -16; 32,368
for -14; and 8092 for - 12 clock periods per cycle (see Figure
conversion timing!.

a

D
ZERO
CROSSING
FF

CL

POL

CL

Figure 2A: Phase I Auto-Zero

1. Auto-Zero Phase I Fig. 2A
During Auto-Zero, the input of the buffer is shorted to
analog ground thru switch 2, and switch 1 closes a loop
around the integrator and comparator. The purpose of

the loop is to charge the Auto-Zero capacitor until the
integrator output no longer changes with time. Also,
switches 4 and 9 recharge the reference capacitor to VREF.

4·173

8052/7104 8068/7104
AN
liP

o

0

ZERO
CROSSING
FF

CL

POL

CL

Figure 28: Phase II Integrate Input

2. Input Integrate Phase" Fig. 2B
During input integrate the Auto-Zero loop is opened and
the analog input is connected to the buffer input thru
switch 3. (The reference capacitor is still being charged to
VREF during this timeJ If the input signal is zero, the buffer,
integrator and comparator will see the same voltage that
existed in the previous state (Auto-Zero). rhus the

integrator output will not change but will remain
stationary during the entire Input Integrate cycle. If V!N is
not equal to zero, an unbalanced condition exists
compared to the Auto-Zero phase, and the integrator will
generate a ramp whose slope is proportional to VIN. At the
end of this phase, the sign ot the ramp is latched into the
polaritv F/F.

Ba

o

Q
ZERO
CROSSING
FF

21

97"::'

CL

~VREF

_"::'+

POL

CAEF

Figure 2C: Phase III

Deintegrate Phase III Fig. 2C & D
During the Deintegrate phase, the switch drive logic uses the
output of the polarity F/F in determining whether to close
switches 6 and 9 or 7 and 8. If the input signal was positive,
switches 7 and 8 are closed and a voltage which is VREF more
negative than during Auto-Zero is impressed on the buffer
input. Negative inputs will cause +VREF to be applied to the
buffer input via switches 6 and 9. Thus, the reference
capacitor generates the equivalent of a (+) reference or a H
reference from the single reference voltage with negligible

error. The reference voltage returns the output of the
integrator to the zero-crossing pOint established in Phase I.
The time, or number of counts, required to do this is proportional to the input vOltage. Since the Deintegrate phase can
be twice as long as the Input integrate phase, the input
voltage required to give a full scale reading = 2VREF.
Note: Once a zero crossing is detected, the system
automatically reverts to Auto-Zero phase for the leftover
Deintegrate time (unless Run/Hold is manipulated, see Run/
Hold Input in detailed description, digital section).

o

t(
B

6

9

7

-

+

CL

+ Deintegrate

Q
ZERO
CROSSING
FF

CL

~VREF

POL

CREF

Figure 20: Phase III - Deintegrate

CL

8052/7104 8068/7104
Buffer Gain

At the end of the auto-zero interval, the instantaneous noise
voltage on the auto-zero capacitor is stored, and subtracts
from the input voltage while adding to the reference voltage
during the next cycle. The result is that this noise voltage
effectively is somewhat greater than the input noise voltage
of the buffer itself during integration. By introducing some
voltage gain into the buffer, the effect of the auto-zero noise
(referred to the input) can be reduced to the level of the
inherent buffer noise. This generally occurs with a buffer
gain of between 3 and 10. Further increase in buffer gain
merely increases the total offset to be handled by the autozero loop, and reduces the available buffer and integrator
swings, without improving the noise performance of the
system. The circuit recommended for dOing this with the
ICl8068/1Cl7104 is shown in Figure 4. With careful layout,
the circuit shown can achieve effective input noise voltages
on the order of 1-2/,V, allowing full 16-bit use with full scale
inputs of as low as 150mV. Note that !I.l this level, thermoelectric EMFs between PC boards, IC pins, etc., due to local
temperature changes can be very troublesome. For further
discussion, see App. Note A030.

-15V

+15V

rtll

16

B

7

1

TO ICL7104

Figure 4: Adding Buffer Gain to ICL8D68

Table 5: Typical Component Values

V++ = +15V V+ = 5V V- = -15V Clock Freq = 200 kHz
ICLS052/S06S with
ICL7104-16
Full scale VIN
200
800
4000
Buffer Gain
10
1
1
100
RINT
43
200
.33
.33
.33
CINT
1.0
1.0
1.0
CAZ
Cret
10
1.0
1.0
100
400
VREF
2000
Resolution
3.1
12
61

ICL7104-14
100
4000
1
10
180
47
0.1
0.1
1.0
1.0
10
1.0
50
2000
6.1
244

ICL8052 vs ICL8068
The ICl8052 offers significantly lower input leakage
currents than the ICl8068, and may be found preferable in
systems with high input impedances. However, the ICl8068
has substantially lower nOise voltage, and for systems where
system noise is a limiting factor, particularly in low signal
level conditions, will give better performance.

4-1.75

ICL7104-12
50
4000
1
10
200
27
.022
.022
.47
.47
4.7
4.7
200
25
980
12

UNITS
mV

kO
/,F
/,F
/,F
mV
/'V

.O~OIl

8052/7104 8068/7104
POLARITY
D~TECTED

ZERO CROSSING
OCCURS

I

I
I ......

1/

I

ZERO CROSSING
/DETECTED·
I

INTEGRATOR
OUTPUT

t....-

INTERNAL CLOCK

n.r ~ Jl[lJl..fl.. N'lIlJ1r ~

I

I·~

r--AZ PHASE I - + I N T PHASE

INTERNAL LATCH

I

II!

I

I

4;2

DEINT PHASE

1

1
I

l i n

I

I

1

I

1

1

STATUS OUTPUT 1

I

I

I
I

I
'I

-16
-14
-12

Phase I
32768
8192
2048

COUNTS
Phase II
32768
8192
2048

I

I

~AFTER

NUMBER OF COUNTS TO ZERO CROSSING!
PROPORTIONAL TO V,N

III~AZ­

I
I

ZERO CROSSING,
ANALOGSECTION WILL
BEIN AUTOZERO
CONFIGURATION

Phase III
65536
16384
4096

Figure 3: Conversion Timing

II

COMPONENT VALUE SELECTION
For optimum performance of the analog section, care must
be taken in the selection of values forthe integrator capacitor
and resistor, auto-zero capacitor, reference voltage, and
conversion rate, These values must be chosen to suit the
particular application.
Integrating Resistor
The integrating resistor is determined by the full scale input
voltage and the output current of the buffer used to charge
the integrator capacitor. This current should be small
compared to the output short circuit current such that
thermal effects are kept to a minimum and linearity is not
affected. Values of 5 to 40 p.A give good results with a
nominal of 20 p.A. The exact value may be chosen by
RINT =

full scale voltage'
20p.A

'Note: If gain is used in the buffer amplifier then RINT =

(Buffer gain) (full scale voltage)
20p.A

Integrating Capacitor
The product of integrating resistor and capacitor is selected
to give 9 volt swing for full scale inputs. This is a compromise
between possibly saturating the integrator (at +14 volts) due
to tolerance build-up between the resistor, capacitor and
clock and the errors a lower voltage swing could induce due
to offsets referred to the output. of the comparator. In
general, the value of CINT is give by
32768 for -16

C
INT

=

~(8192 for -14 X clock period)

]

X (20p.A)
(2048for-12
Integrator output voltage swing

A very important characteristic of the integrating capacitor is
that it have low dielectric absorption to prevent roll-over or
ratiometric errors. A good test for dielectric absorption is to
use the capacitor with the input tied to the reference.

This ratiometric condi.tion should read half scale (100 ... 0001
and any deviation is ~robably due to dielectric absorption.
Polypropylene capacitors give undetectable errors at
reasonable cost. Polystyrene and polycarbonate capacitors
may also be used in less critical applications.

Auto-Zero and Reference Capacit~r
The size of the auto-zero capacitor has some influence on
the noise of the system, a large capacitor giving less noise.
The reference capacitor should be large enough such that
stray capacitance to ground from its nodes is negligible.
Note: When gain is used in the bufferamplifier the reference
capacitor should be substantially larger than the auto-zero
capacitor. As a rule of thumb, the reference capacitor should
be approximately the gain times the value of the auto-zero
capacitor. The dielectric absorption of the reference cap and
auto-zero cap are only important at power-on or when the
circuit is recovering from an . overload .. Thus, smaller or
cheaper caps can be used here if accurate readings are not
required for the first few seconds of recovery.

Reference Voltage
The analog input required to generate a full scale output is
VIN = 2 VREF.
The stability of the reference voltage is a major factor in
the overall absolute accuracy of the converter. The
resolution of the ICL7104 at 16 bits is one part in 65536, or
15.26ppm. Thus, if the reference has a temperature
coefficient of 50ppm/o C (on board reference) a temperature
change of 1/3°C will introduce a one-bit absolute error. For
this reason, it is recommended that an external high quality
reference be used where the ambient temperature is not
controlled or where high-accuracy absolute measurements
are being made.

4·176

8052/7104 8068/7104
DETAILED DESCRIPTION

Run/Hold Input

Digital Section

'When the Run/Hold input is connected to V+ or left open (this
input has a pullup resistor to ensure a high level when the pin
is left openl,'the circuit will continuously perform conversion
cycles, updating the output l(ltches at the end of every
Deintegrate (Phase 1111 portion of the conversion cycle (See
Figure 31. (See under "Handshake Mode" for exception.! In
this mode of operation, the conversion cycle will be
performed in 131,072 for 7104-16, 32768 for 7104-14 and
8192 for 7104-2 clock periods, regardless of the resulting
value.
If Run/Hold goes low at any time during Deintegrate (Phase
III) after the zero crossing has occurred, the circuit will
immediately terminate Deintegrate and jump to Auto-Zero.
This feature can be used to eliminate the time spent in
Deintegrate after the zero-crossing. If Run/Hold stays or
goes low, the converter will ensure a minimum Auto-Zero
time, and then wait in Auto-Zero until the Run/Hold input
goes high. The converter will begin the Integrate (Phase II)
portion of the next conversion (and the'STaTuS output will
go highl seven clock periods after the high level is detected at
Run/Hold. See Figure 6 for details.
Using the Run/Hold input in this manner allows an easy
"convert on demand" interface to be used. The converter
may be held at idle in Auto-Zero with Run/Hold low. When
Run/Hold goes high the conversion is started, and when the
STaTuS output goes low the new data is valid (or transferred
to the UART - see Handshake Model. Run/Hold may now go
low terminating Deintegrate and ensuring a minimum AutoZero time before stopping to wait for the next conversion.
Alternately, Run/Hold can be used to minimize conversion
time by ensuring that it goes low during Deintegrate, after
zero crossing, and goes high after the hold point is reached.
The required activity on the Run/Hold input can be provided
by connecting it to the CLOCK3 (-12, -141,CLOCK2 (-16)
Output. In this mode the conversion time is dependent on the
input value measured. Also refer to Intersil Application
Bulletin A030 for a discussion of the effects this will have on
Auto-Zero performance.

The digital section includes the clock oscillator circuit, a 16,
14 or 12 bit binary counter with output latches and TTLcompatible three-state output drivers, polarity, over-range
and control logic and UART handshake logic, as shown in
the Block Diagram Figure 5" (16 bit version shown).
Throughout this description, logic levels will be referred to
as "low" or "high". The actual logic levels are defined under
"ICL7104 Electrical Characteristics". For minimum power
consumption, all inputs should swing from GND (low) to V+
(high). Inputs driven from TTL gates should have 3-Skn
pullup resistors added for maximum noise immunity.

MODE Input
The MODE input is used to control the output mode of the
converter. When the MODE pin is connected to GND or left
open (this input is provided with a pulldown resistor to
ensure a low level when the pin is left open), the converter is
in its "Direct" output mode, where the output data is directly
accessible under the control of the chip and byte enable
inputs. When the MODE input is pulsed high, the converter
enters the UART handshake mode and outputs the data in
three bytes for the 7104-16 or two bytes for the 7104-14 and
7104-12, then returns to "direct" mode. When the MODE
input is left high, the converter will output data in the
handshake mode at the end of every conversion cycle. (See
section entitled "Handshake Mode" for further details).

STaTuS Output
During a conversion cycle, the ST~TuS output goes high at
the beginning of Input Integrate (Phase II), and goes low
one-half clock period after new data from the conversion has
been stored in the output latches. See Figure 3 for details of
this timing. This signal may be used as a "data valid" flag
(data never changes while STaTuS is low)to drive interrupts,
or for monitoring the status of the converter.

CElLO
B9

BS

B7

B6

LBEN
85 84

83

82

81

7104~14

7104-12

I

I

r....J"-...~~UlJUI

COMP OUT
.. TO AZ
ANALOG ( INT
SECTION DEINT(,-)
DEINT(-)

I

I
2.L ___ J
STaTuS

RIA

CLOCK CLOCK

1

2

CLOCK

3

Figure 5: Dig ital Section

4-177

MODE

SEND

I

CElLO

8052/7104 8068/7104
OPTION
MIN
MAX
DEINT TERMINATED,
AT Z,ERO CROSSING'\.

INTEClRATOR
OUTPUT

-

INTERNAL CLOCK

V,., n

~

~TION -.J"\.1

n n

n n n n n n

-12
1785
2041

-14
-16
7161 28
8185 32761

I
,

.....NT

I

~
n '"' h ,., ,.,

STATIC IN
I HOLD STATE

: !I ,

n..---1

UUUL.,"'UUUL.lL.lL.,~LII~UUL.,,.J'1
INTERNAL LATCH _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
I

STaTuS OUTPUT
RUN/HOLD INPUT

n

I

PHASE I

I

,.---.,..7 COUNTS-----:"---

~
I
I

L ____
___ _
--------7L-_-_-_-_-_-_-':",_____________"" _---"""""lrI

~_-!

Figure 8: Run/Hold Operation
If the Run/Hold input goes low and stays low during AutoZero (Phase I), the converter will simply stop at the end of
Auto-Zero and wait for Run/Hold to go high. As above,
Integrate (Phase II) begins seven clock periods after the high
Ieve lis detected.

input low will allow the outputs of that byte to become active
(three-stated onl. This allows a variety of parallel data accessing techniques to be used. The timing requirements forthese
outputs are shown under AC Characteristics and Table 1.

Direct Mode

It should be' noted' that these control inputs are
asynchronous with respect to the converter clock - the data
may be accessed at any time. Thus it is possible to access the
data while it is being updated, which could lead to scrambled
data. Synchronizing the access of data with the conversion
cycle by monitoring the STaTuS output will prevent this.
Data,is never updated while STaTuS is low. Also note the
potential bus conflict described under "Initial Clear Circuitry".

When the MODE pin is lellata low level, the data outputs[bits
1 through 8 low order byte, see Table 4 for format of middle
(-16) and high order bytes]are accessible under control of the
byte and chip ENable terminals as inputs. These ENable
inputs are all active low, and are provided with pullup
resistors to ensure an inactive high level when left open.
When the chip ENable input is low,taking a byte ENable
ZERO-CROSSING
'\J/OCCURS

INTEGRATOR
OUTPUT

INTERNAL
CLOCK

1'\ ~ERO-CROSSING

'"

~uence Ineerted here.

DETECTED

~ r- ~~ t -

I--~ ~rL-

I

INTERNAL
LATCH
STATUS
OUTPUT
MODE
INPUT

MODE HIGH ACTIVATES
CE7[ljJ\f),

HIIEIii, IliEN

~
1ll

INTERNAL UART
MODE NORM
SEN
INPUT

0:::::::::::::

SEN
f-'SENSE~

.--::::::::

f--

SEN
SENSED _______

•I\
I\,

1
HIGH BYTE
DATA

---------

1\

../

I\,

/

IN HA:8fHEfK~'X,~~~
DISABLES OUTPUTS C'E7[])

'/

-r--

DATA VALID

r-

1--------- ___

----------- r-- 1--------

--

.JI----:m:~~~

/

I'-~--~"'"

~--

... -

~ ------

~- ... -

1/

1\
LOW BYTE
DATA

J

TERMINATES
UARTMODE

-- -------- --- ------

DATA VALID

v----

\..
"

LOW BYTE
DATA

-----------------------------------_

~ DON'T CARE

- - - - ~ THREE-STATE HIGH IMPEOANCE

Figure 7: Handshake With SEN Held Positive

4-178

DATA VALID

~--~---I

-~-~ THREE-STATE WITH PULLUP

8052/7104 8068/7104
Handshake Mode
The handshake output mode is provided as an alternative
means of interfacing the ICL7104 to digital systems, where
the AID converter becomes active in controlling the flow of
data instead of passively responding to chip and byte ENable
inputs. This mode is specifically designed to allow a direct
interface between the ICL7104 and industry-standard
UARTs (such as the IntersilCMOS UARTs,IM6402/3) with no
external logic required. When triggered into the handshake
mode, the ICL7104 provides all the control and flag signals
necessary to sequence the three (lCL7106-16) or two
(lCL7104-14, -12) bytes of data into the UART and initiate
their transmiSSion in serial form. This greatly eases the task
and reduces the cost of designing remote data acquisition
stations using serial data transmission to minimize the
number of lines to the central controlling processor.
Entry into the handshake mode will occur if either of two
conditions are fulfilled; first, if new data is latChed (i.e. a
conversion is completed) while MODE pin (pin 27) is high, in
which case entry occurs at the end of the latch cycle; or
secondly, if the MODE pin goes from low to high, when entry
will occur immediately (if new data is being latched, entry is
delayed to the end of the latch cycle). While in the handshake
mode, data latching is inhibited, and the MODE pin is
ignored. (Note thaI conversion cycles will continue in the
normal manner). This allows versatile initiation of handshake
operation without danger of false data generation; if the
MODE pin is held high, every conversion (other than those
completed during handshake operations) will start a new

handshake operation, while if the MODE pin is pulsed high,
handshake operations can be obtained "on demand."
When the converter enters the handshake mode, or when the
MODE input is high, the chip and byte ENable terminals
become TTL-compatible outputs which provide the control
signals for the output cycle. The Send ENable pin (SEN) ipin
29) is used as an indication. of the ability of the external
device to receive data. The condition of the line is sensed
once every clock pulse, and if it is high, the next (or firs!) byte
is enabled on the next rising CLOCK 1 (pin 25) clock edge,
the corresponding byte ENable line goes low, and the Chip
ENablelLoaD line (pin 30) (CElLO) goes low for one full clock
pulse only, returning high.
On the next falling CLOCK 1 clock pulse edge, if SEN remains
,high, or after it goes high again, the byte output lineswill be
put in the high impedance state (or three-stated off). One half
pulse later, the byte ENable pin will be cleared high, and
(unless finished) the CEILD and the next byte ENable pin will
go low. This will continue until all three (2 in the case of 12
and 14 bit devices) bytes have been sent. The bytes are
individually put into the low impedance state i.e.: threestated on during most of the time thattheir byte ENable pin is
(active) low. When receipt of the last byte has bee';'
acknowledged by a high SEN, the handshake mode will be
cleared, re-enabling data latching from conversions, and
recognizing the condition of the MODE pin again. The byte
and chip ENable will be three-stated off, if MODE is low, but
held h'igh by tlieir (weak) pullups. These timing relationships
are illustrated in Figure 7, 8, and 9, and Table 2.

ZERO·CROSSING
INTEGRATOR
OUTPUT

----''F\=--r~~RO'OCRIOS'SING

INTERNAL
CLOCK
INTERNAL
LATCH _ _ _ _- "
STATUS
OUTPUT

-------1

MODE------~
INPUT
INTERNAL UART

MODE~N~OR~M~_ _ _~

SEN INPUT
(UART
TBRE)

:E7Ui OUTPUT
(UARTTBRL)

.maEmm~-r---7
ill

------+-0\

HIGH DATA
BYTE - - - - - -

-.-t'-1C=~~~~I~~::)

MIDDLE,BYTE _ _ _ _ _ _ _ _
DATA

-----~"..-

------.. ~-+-~~t:::)

-----;~--

LOW BYTE
DATA - - - - - -

•

= DONTCARE

- - - = THREE·STATE HIGH IMPEDANCE

t=lgure 8: Handshake - Typical UART Interface Timing

4·179

II
~

8052/7104 8068/7104
The data outputs are paralleled into the eight Transmitter
Buffer Register inputs.
Assuming the UART Transmitter Buffer Register is empty,
the SEN input will' be high when the handshake mode is
entered after new data is stored. The CEILD arid HBEN
terminalswill go low after SEN is sensed, and the high order
byte outputs become active. When CElLO goes highat the
end of one clock period, the high order byte data is clocked
into the UART Transmitter Buffer Register.The UART TBRE
output will now go low, which halts the output cycle with the
RBENoutput low, and the high order byte outputs active.
When the UART has transferred the data to the Transmitter
Register and cleared the Transmitter Buffer Register, the
TBRE returns high. On the next ICL7104 internal clock high
to low edge, the high order byte outputs are disabled, and
one-half internal clock later, the HBEN output returns high.
At the same time, the CElLO and MBEN(6) or LBEN
outputs go low, and the corresponding byte outputs become
active. Similarly, when the CElLO returns high at the end of
one clock period, the enabled data is clocked into the UART
Transmitter Buffer Register, and TBRE again goes low.
When TBRE returns to a high it will be sensed on the next
ICL7104 internal clock high to low edge, disabling the data
outputs. For the 16 bit device, the sequence is repeated for
LBEN. One-half internal clock later, the handshake mode
will be cleared, and the chip and byte ENable terminals
return high and stay active (as long .as MODE stays highl.
With the MODE input remaining high as in these examples,
the converter will output the results of every conversion

Figure 7 shows the sequence of the output cycle with SEN
held high. The handshake mode (Internal MODE high) is
entered after the data latch pulse (since MODE remains high
the CElLO, LBEN, MBEN and HBENterminals are active as
outputs). The high level at the SEN input is sensed on the
same high to low internal clock edge. Onthenext lowto high
internal clock edge, the CElLO and the HBEN outputs
assume a low level and the high-order byte (POL and OR, and
except for -16, Bis 9-14) outputs are enabled. The CElLO
output remains low for one full internal clock period only, the
data outputs remain active for 1-1/2 internal clock periods,
and the high byte ENable remains low for two clock periods.
Thus the CElLO output low level or low to high edge may be
used as a synchronizing signal to ensure valid data, and the
byte 8iiable as an output may be used as a byte identifica-,
tion flag. With SEN remaining high the converter completes
the output cycle using CElLO, MBEN and LBEN while the
remaining byte outputs (see Table 4) are activated. The
handshake mode is terminated when all bytes are sent (3 for16, 2 for -14, -12l.
Figure 8 shows an .output sequence where the SENinput is
used to delay portions of the sequence, or handshake, to
ensure correct data transfer. This timing diagram shows the
relationships that occur using an industry-standard
IM6402/3 CMOS UART to interface to serial data channels.
In this interface, the SEN input to the ICL7104 is driven by
the TBRE (Transmitter Buffer Register Empty) output of the
UART, and the C1:/[]j terminal of the ICL7104 drives the
TBRL (Transmitter Buffer Register Load) input to the UART.

ZERO CROSSING DETECTED

INTERNAL~'.
CLOCK
r~
INTERNAL
LATCH

r-u-L~0~.r ....... ~
UART MODE

STATUS
OUTPUT
POSITIVE TRANSITION CAUSES
MODE ENTRY INTO
INPUT UART MODE

SEN
INPUT

_____

r--

HBEN _ _ _ _ _

r--

HIGH ~~~ _ _ _ _ .,- _ _ _ ....

MBEN _ _ _ _ _

MIDDLE ~Z~~

r--

... -------.,

~

... - --

~

r\

I\,

If
DATA VAL,It:: ~

--

------~~--

-

.....

~~

...

------o(~--

-- ------;/0 .._-

fo---u..._~.

'If
DATA VAl:O--

>-

------,~--

-

.•

~ DON'T CARE

~--

-- ------.;~-- .. -------0(
- - -

~

THREE-STATE HIGH IMPEDANCE

Figure 9: Handshake Triggered By Mode

4-180

/0---

--

..i._~_

,-J--"'-'

r\
LOW ~~~ ... _ _ _ _ _ _ _ ~

... ~.

~"' ~-

\.
~--

r_

J::,

- ~,

~~~~_ _~

ASO~;~~~

STATUS OUTPUT
UNAFFECTED BY
UART MODE

DEINT
PHASE III

DATAVA~C ~.

----

-"'-~ TH,REE-STATE WITH

PULLUP

8052/7104 8068/7104
except those completed during a handshake operation. By
triggering the converter into handshake mode with a low to
high edge on the MODE input, handshake output sequences
may be performed on demand. Figure 11 shows a handshake
output sequence triggered by such an edge. In addition, the
SEN input is shown as being low when the converter enters
handshake mode. In this case, the whole output sequence is
controlled by the SEN input, and the sequence for the first
(high order) byte is similar to the sequence for the other
bytes. This diagram also shows the output sequence taking
longer than a conversion cycle. Note that the converter still
makes conversions, with the STaTuS output and Run/Hold
input functioning normally. The only difference is that new
data will not be latched when in handshake mode, and is
therefore lost.

As a result of pin count limitations, the ICL7104-16 has only
CLOCK 1 and CLOCK 2 available, and cannot be used as an
RC oscillator. The internal clock will correspond to the
inverse of the signal on CLOCK 2. Figure 11 shows a crystal
oscillator circuit, which can be used with all 7104 versions. If
an external clock is to be used, it should be applied to
CLOCK 1. The internal clock will correspond to the signal
applied to this pin.

Initial Clear Circuitry
The internal logic of the 7104 is supplied by an internal
regulator between V++ and Digital Ground. The regulator
includes a low-voltage detector that will clear various
registers. This is intended to ensure that on initial power-up,
the control logic comes up in Auto-Zero, with the 2nd, 3rd, and
4th MSB bits cleared, and the "mode" FF cleared (i.e. in
"direct" model. This, however, will also clear these registers
if the supply voltage "glitches" to a low enough value.
Additionally, if the supply voltage comes up too fast, this
clear pulse may be too narrow for reliable clearing. In
general, this is not a problem, but if the UART internal
"MODE" FF should come up set, the byte and chip ENable
lines will become active outputs. In many systems this could
lead to buss conflicts, especially in non-handshake systems.
In any case, SEN should be high (held high for nonhandshake systems) to ensure that the MODE FF will be
cleared as fast-as possible (see Fig. 7 for timingl. For these
and other reasons, adequate supply bypass is
recommended.

Oscillator
The ICL7104-14 and -12 are provided with a versatile three
terminal oscillator to generate the internal clock. The
oscillator may be overdriven, or may be operated as an RC or
crystal oscillator.
Figure 10 shows the oscillator configured for RC operation.
The internal clock will be of the same frequency and phase as
the voltage on the CLOCK 3 pin. The resistor and capacitor
should be connected as shown. The circuit will oscillate at a
frequency given by f = .45/RC. A 50-100kfl resistor is
recommended for useful ranges of frequency .. For optimum
60Hz line rejection, the capacitor value should be chosen
such that 32768 1-16), 8192 (-14), 2048 (-12) clock periods is
close to an integral multiple of the 60Hz period.

25
CLOCK
1

24

26
CLOCK
2

CLOCK
3
R

lose

~

c

.45/RC

Figure 10: RC Oscillator
Note that CLOCK 3 has the same output drive as the bit outputs.

Figure 1.1: Crystal Oscillator

POWER SUPPLY SEQUENCING
Because of the nature olthe CMOS process used to fabricate
the ICL7104, and the multiple power supplies used, there are
certain conditions of these supplies under which a disabling
and potentially damaging SCR action can occur. All of these
conditions involve the V+ supply (nom. +5V) being more
positive than the V++ supply. If there is any possibility of this
occuring during start-up, shut down, under transient
conditions during operation, or when inserting a PC board
into a "hot" socket, etc., a diode should be placed between V+
and V++ to prevent it. A germanium or Schottky rectifier
diode would be best, but in most cases a silicon rectifier
diode is adequate.

ANALOG AND DIGITAL GROUNDS
Extreme care must be taken to avoid ground loops in the
layout of 8068 or 805217104 circuits, especially in 16-bit and
high sensitivity circuits. It is most important that return
currents from digital loads are not fed into the analog ground
line. A recommended connection sequence for the ground
lines is shown in Figure 12.

APPLICATIONS INFORMATION
Some applications bulletins that may be found useful are
listed here:
A016 "Selecting AID Converters", by Dave Fullagar
A017 "The Integrating AID Converter", by Lee Evans
A018 "Do's and DonI's of Applying AID Converters", by
Peter Bradshaw and Skip Osgood
A025 "Building a Remote Data Logging Station", by Peter
Bradshaw
A030 "The ICL7104 - A Binary Output AID Converter for
Microprocessors", by Peter Bradshaw
R005 "InterfaCing Data Converters & Microprocessors", by
Peter Bradshaw et ai, Electronics, Dec. 9, 1976.

I

~

8052/7104 8068/7104
BUF
OUT

rl't-r- --'VV'v- liP
Y,N

--1

'6~~ER

EXTERNAL
REFERENCE
(IF USED)
ICL8052
PIN 5
AN GND

ICL7104
PIN 35
ANGND

+15V

1 1

8068 PIN 2
COMP

It"

DIGITAL
LOGIC

K

DIGGND
ICL7104
PIN 2

-15V

I

BOARD
EDGEI

I

I

~
T
T
T

...n.

DEVICE PIN

+5V SUPPLY BYPASS CAPACITOR(S)

Figure 12: Grounding Sequence

4-182

$)

/SUPPLY
RETURN

Driver Amplifier for
Power Transistors Page
ICL8063
5-182
Driver Amplifier for
Actuators, Motors
ICH851 0/20/30
5-214
ICH8515
5-222
Instrumentation
Com mutating Auto-Zero
ICL7605/6
5-63
Log-Antilog
ICL8048/49
5-174
Operational
Chopper Stabilized
ICL7650
5-88
ICL7652
5-96
Operational, FET Input
LH0042
AD503
SU/NE536
/l-A740
ICL8007
5-139
ICL8043
5-167
ICH8500
5-208
Operational, General
Purpose
OP-05
5-8
OP-07
5-16
LM101/301A
LM107/307
LM108/308
5-24
/l-A741
ICL741HS
5-44
AD741K
ICL741LN
5-46
/l-A748
5-49
/l-A777

..

LH2101/2301
5-55
LH21 08/2308
IH5101
5-142
ICL8008
Operational, High Speed
ICL8017
5-151
Operational, Low Power
LM4250
ICL76XX Series
5-73
5-155
ICL8021-23
Video
/l-A733
NE/SE592
5-38
NE592-8
5-41
Voltage Followers
LM 102/302
LM110/310
LH2110/2310

..

Comparators
Dual
LH2111/2311
Low Power
ICL8001
Precision
LM111/311

Voltage Reference
ICL8069
ICL8075-9
ICL8211/12

5-190
5-192
5-198

Voltage Regulators
LM 100/300
LM105/305
/l-A723
ICL7663/4

5-111

Special Function
Multiplier
ICL8013
5-144
Voltage Converter
ICL7660
5-104
Waveform Generator
ICL8038
5-158
Low Battery Detectors
ICM7201
5-121
ICL7665
ICL8211/12
5-198
Power Mos Driver
5-128
ICL7667

..

5-135

Sample and Hold
IH5110-15

5-57

Temperature
Sensor

•• Not appearing in this
catalog. Contact local
sales representative for
specific product
5-28
information.

AD590

LINEAR
Operational Amplifiers - General. Purpose
Type

Description

lOB
10BLN

Low Level, Uncompensated
Guaranteed Noise lOB

30B
30BLN

Ib
(nA)

vos
(mV)

GBW (typ) Isupp
(MHz)
(mA)

AYOL
(v/V)

2.0
2.0

50,000
50,000

Low Level, Uncompensated
Guaranteed Noise 308

2.0
2.0
7.5
7.5

7.0
7.0

777
777C

General Purpose Comparator
General Purpose Comparator

0.7
0.7

BOOBM
BOOBC

Low Bias Current, Compensated
Low Bias Current, Compensated

5.0
6.0

LH2108
LH2108A
LH2308
LH2308A

Dual
Dual
Dual
Dual

2.0
0.5
7.5
0.5

Super
Super
Super
Super

Beta
Beta
Beta
Beta

TA
(OC)

Packages'

Remarks

-55, +125
-55, +125

J, F, T
T

7CnV/.,jHZ@10Hz

0.6
0.6

25.000
25,000

1.0
1.0
1.0
1.0

25
25

150,000
150,000

O.B
O.B

2.5
2.5

-55, +125
0, +70

P, T
P, T

10
25

20,000
20,000

1.0
1.0

2.B
2.B

-55, +125
0, +70

J, T
J, P, T

3.0
25,000
3.0 . 40,000
10
15,000
10
60,000

1.0
1.0
1.0
1.0

0.4
0.4
0.4
0.4

..,.55 to +125
-55to+125
oto +70
oto +70

,

O.B
O.B

F, J, P, T

0, +70
0: +70

r

Operational Amplifiers - Low Power Programmable
Type

11

Description

Vos
(mV)

Ib
(nA)

AYOL
(V/V)

GBW
(MHz)

Isupp
(,.A)

@ Iset
(pA)

@V.
(V)

70nV/.,jHZ@10Hz

n

Build to Order

TA
(OC)

Packages'

B021M
B021C

Programmable, Compensated
Programmable, Compensated

3.0
6.0

20
30

50,000
50,000

0.27
0.27

40
50

30
30

+6.0
+6.0

-55to +125
0, +70

J, T
T

8022M
B022C

OualB021M
Dual8021C

3.0
6.0

20
30

50,000
50,000

0.27
0.27

40
50

30
30

+6.0
+6.0

-55to +125
0, +70

J, F
J, P

8023M Triple B021M
8023C Triple B021C

3.0
6.0

20
30

50,000
50;000

0.27
0.27

40
50

30
30

+6.0
+6.0

- 55 to +125
oto +70

J
J, P

7611
7612
7613

2.0
2.0
2.0

0.001
0.001
0.001

100,000
100,000
100,000

1.4
1.4
1.4

20
20
20

C,I,M
C,I,M
C,I,M

T, P
T, P
T, P

5.0
5.0

0.001
0.001

100,000
100,000

1.4
1.4

60
60

C,I,M
C,I,M

0', P
D, P

7631
7632

CMOS
CMOS, Extended CMVR
CMOS, Input Protected
to ±200V
CMOS, Triple
CMOS, Triple, Uncompensated

Operational Amplifiers - CMOS
Type
7611
7612

Description

Compensation

Single, Selectable 10
Internal
Single, Selectable 10
Internal
Extended CMVR
7613 Single, Selectable 10
Internal
Input Protected to ± 200V
7614 Single, Fixed 10
External
7615 Single, Fixed 10
External
Input Protected
7621 Dual, Fixed 10
Internal
7622 Dual, Fixed 10
Internal
7631 Triple, Selectable 10
Internal
7632 Triple, Selectable 10
None
7641 Quad. Fixed 10
Internal
7642 Quad, Fixed 10
Internal
7650 Chopper Stabilized
Internal

Output Swing

Input CMR

Packages'

0"5at Null

Vos Selection

los

18

Yes
Yes

2,5,15mV
2,5, 15mV

0.5pA
0.5pA

lpA
lpA

Vsupp -100mV Vs upp-l00mV
VsuPp + 300mV Vsupp-l00mV

P, T
P, T

Yes

2,5,15mV

0.5pA

lpA

Vsupp-l00mV

Vsupp-l00mV

P, T

Yes
Yes

2,5, 15mV
2,5,15mV

0.5pA
0.5pA

lpA
lpA

Vsupp -100mV
VsuPP"-100mV

Vsupp -100mV
Vsupp -100mV

P, T
P, T

No
Yes
No
No
No
No

2,5, 15mV
2,5,15mV
5,10,20mV
5.10.20mV
5,10.20mV
5. 10, 20mV
O.OlmV

MpA
0,5pA
0.5pA
0.5pA
0.5pA
a.5pA

lpA
lpA
lpA
lpA
lpA
lpA
10pA

Vsupp-l00mV
Vsupp-l00mV
Vsupp-l00mV
Vsupp-l00mV
Vsupp-l00mV
Vsupp-l00mV
Vsupp-l00mV

Vsupp-l00mV
Vsupp -100mV
Vsupp -100mV
Vsupp-l00mV
Vsupp-l00mV
Vsupp -100mV

P,T
p, J
P, J
'P, J
P. J
p. J
P, T

'Package Key: O-Solder lid side brazed ceramic dual-in-line. F-Ceramic flat package. J-Glass frit seal ceramic duaHn:line. P-Plastic dual-in-line.
T-Metal can.

5·2

Operational Amplifiers - FET Input (also see Operational Amplifier, CMOS)

Type

Vos
(mV)

Description

Ib
(pA)

Slew
AVoL GBW (typ) Rate Isupp
(V/V)
(MHz) (V/I's) (mA)

TA
(OC)

Packages·

Remarks

T

B007M
B007AM
B007C
B007AC

General Purpose, Compensated
8007M, Low Ib
General Purpose, Compensated
8007C, Low Ib

20
30
50
30

20
1.0
50
10

50,000
20,000
20,000
20,000

1.0
1.0
1.0
1.0

6
2.5
6
2.5

5.2
6
6
6

-55, +125
-55, +125
0, + 70
0,4-70

B043M
B043C

Dual8007M
Dua18007C

20
50

20
50

50,000
20,000

1.0
1.0

6.0
6.0

6
6.8

-,55, +125
-55, +125

J, P

B500
B500A

MOSFET Input, Compensated
MOSFET Input, Super Low Ib

50
50

0.1
0.01

20,000
20,000

0.7
0.7

0.5
0.5

2.7
2.7

-25, +85
-25, +B5

T
T

T
T
T

All BI FET amplifiers
offer low noisesee data sheets

Operational Amplifiers - High Performance

Type

Description

Vos
(mV)

Ib
(pA)

AVoL
(V/V)

GBW
(MHz)

Slew
Rate
(VII's)

Isupp
(mA)

TA
(OC)

Packages·

B017M
B017C

High Speed, Inverting
High Speed. Inverting

5.0
7.0

200
200

25,000
25,000

10
10

130
130

7.0
B.O

-55, +125
0, + 70

T, F
T, F

OP-05
OP-07

Low Bias, Low Drift
Ultra Stable

0.07
0.025

700
300

500,000
500,000

0.6
0.6

0.2
0.17

4.0
4.0

-55, +125
-55, +125

T, J
T, J

Operational Amplifiers-High Slew Rate
Type

B017M
BOlle

OelCrlptlon
High speed. inverting
High speed Inverting

(mV)

Ib
(pA)

(V/V)

5.0

200

7.0

200

25.000
25.000

Yos

saw

AVOL

(MHz)

10
10

SlIW

11111

Isupp

(V/.S)

(mA)

130
130

70
B.O

T.
('C)

-55· 125
0·70

Plckagl,"

T.F
T.F

·Package Key: D-Solder lid side brazed ceramic dual-in-line. F-Ceramic flat package. J-Glass frit seal ceramic dual-in-line. P-Plastic dual-in-line.
T-Metal can.

5·3

Precision Operational Amplifiers, Vsupp = :t 2V to

:t 8V

Slew
Type
ICl7650C
ICl76501
ICL7652

Description
Chopper Stabilized
Chopper Stabilized
Chopper Stabilized

Vos
("V)

4Vos
("V/OC)

:tl
:tl
:tl

:t 0.01
:t 0.01
:to.7

4Vos
("V/yaar)

Av
(dB min)

Rata
Rate (VIpS)

IBIAS

(pA)

Packages·

TA
(OC)

100nV/~month

126
126
120

2.5
2.5
0.5

+1.5
+1.5
+1.5

J, p, T
J, p, T
J, P, T

oto +70
-25to +85
-20to +85

100nV/~month
100nV/~month

Precision Instrumentation Amplifiers, Vsupp = :t 2V to
Type
ICL7605C
ICl76051
ICL7605M
ICL7606C
ICl76061
ICl7606M

:t 5V, Isupp

Description

Vos
("V)

4Vos
("V/OC)

4Vos
("V/y,ar)

Ay
(dB min)

Compensated
Compensated
Compensated
Uncompensated
Uncompensated
Uncompensated

:t2
:t2
±2
:t2
±2
:t2

:t 0.01
:t 0.01
±0.05
:t 0.01
:t 0.01
:t 0.05

0.5
0.5
0.5
0.5
0.5
0.5

90
90
90
90
90
90

=1.7mA
TA
(OC)

Packagas·
J, P
J, P
J, P
J, P
J, P
J,.P

Oto +70
-25to +85
-55to +125
Oto +70
-25to +85
-55to +125

Precision Voltage References
Type
ICL8069

ICl8075-9

Description
. low Voltage Reference

The ICL8069 is a 1.2V temperature compensated voltage reference. It uses the bandgap principle to achieve excellent stability and low noise at reverse currents down to
50pA.

Ultra Precision Temperature The ICl8075-9 is a family of precision laser-trimmed voltage references that incorStabilized Voltage References porate a substrate heater to produce extremely low overall voltage temperature coefficients. The series of devices Is produced so that exact voltages are available for the
most popular AID and D/A converters. This avoids the necessity to perform adjustments In most cases, and reduces the problems with trim range and temperature
coefficient loss in all others.

Video Amplifiers
Type

Description

NE/SE592 Gain Selectable Video Amp
NE592-8
Gain Selectable Video Amp

Gains (typ)
(V/V)
400,100, 10
400, 100, 10

Bandwidths (typ)
(MHz)
40, 90
40

e.
"V(rms)

Output
Offset (V)

Isupp
(mA)

12
12

0.75
0.75

10
10

TA
(OC)
O. +70/-55, +125
0, + 70

Packages·
J.T
P

'Package Key: D-Solder lid side brazed ceramic dual-in-line. F-Ceramic flat package. J-Glass frit seal ceramic dual-in-line. P-Plastic dual-in-line.
T-Metal can.

5-4

Comparators
Type

Description

8001M
BOOIC

vos
(mV)

Ib
(nA)

Av
(V/mV)

tpl!
(ns)(typ)

3
5

100
250

15
15

250
250

Low Power Comparator
Low Power Comparator

Isupp
(rnA)

VOL
(V)

IOl
(rnA)

2
2

0.5
0.4

2

Vos
(mV)

Ib
(nA)

AVOl
(v/V)

TA .,
(OC)

heDg"·

-55, +125
0, +70

T
T

Notes: tpd measured for 100mV step with 5mVoverdrive.
Isupp measured for Vsupp + ± 15V.

Power Amplifiers
Type

Description

ICH8510M Hybrid Power Amplifier
ICH85101 Hybrid Power Amplifier
Hybrid Power Amplifier
ICH85151
ICH8515M Hybrid Power Amplifier
ICH8520M Hybrid Power Amplifier
ICH85201 Hybrid Power Amplifier
ICH8530M Hybrid Power Amplifier
ICH85301
ICL8063C
ICL8063M

Use

Servo
and
Actuator

Hybrid Power Amplifier
Power
Monolithic Power Amplifier
Transistors
Monolithic Power Amplifier

Note 1: Specifications apply at ± 30V supplies.
Note 2: All units packaged in 8 lead TO-3 can.

Output
Output
Current (A) Swing (V)

Slew Quiescent
Rate
Isupp
(VI,..)
(rnA)

1.0
1.0
1.25
1.5
2.0
2.0
2.7

±26
±26
±12
±12
±26
±26
±25

3.0
6.0
6.0
3.0
3.0
6.0
3.0

250
500
500
250
250
500
250

100,000
100,000
100,000
100,000
100,000
100,000
tOO,OOO

0.5
0.5
0.5
0.5
0.5
0.5
0.5

40
50
80
70
40
50
40

2.7
2.0
2.0

±25
±27
±27

6.0
50
75

500

100,000
6
6

0.5

50
250
300

TA
(OC)
-55, +125
-25, +85
- 20°C - + 85°C
-55°C - +125°C
-55, +125
-25, +85
-55, +125
-25, +85
0, +70
-55, +125

Note 3: Fully protected against inductive current flow.
Note 4: Externally setlable output current limiting.

'Package Key: D-Solder lid side brazed ceramic dual-in-line. F-Ceramic flat package. J-Glass Irit seal ceramic dual-in-line. P-Plastic dual-in-line.
T-Metal can.

5·5

Ii

Special Function Circuits
Type

Accuracy

Description

Temperature transducer-output linear at 1~/oK
AD590
ICL7667C Dual Power MOS Driver
ICL7667M Dual Power MOS Driver
8013AM
Four quadrant multiplier. Output proportional to algebraic products
8013BM
of two input signals. Features ±0.5% accuracy: internal op amp
8013CM
for level shift, division and square root functions: full ± 10V
8013AC
input! output range: 1MHz bandwidth.
8013BC
8013CC
8038AM
8038AC
8038BM

Simultaneous Sine, Square, and Triangle wave outputs T2L compatible to 28V over frequency range from O.OIHz to 1.0MHz.
Low distortion « 1%): high linearity (0.1%): low frequency drift
with temperature (50ppm/ oC max): variable duty cycle (2%-98%).

8038BC

I

± 1"C

±0.5%
±1.0%
±2.0%
±0.5%
±1.0%
±2.0%

. Vsuw
(V)
40 to 30
22
22
±15
±15
±15
±15
±15
±15

TA
(OC)
-55 to +150
0, +70
- 55, + 125
-'-55, +125
-55, +125
-55, +125
0, +70
0, +70
0, +70

Packages·
F, H
J, P, T
J, T
T
T
T
T
T
T

1.5%
1.5%
3.0%

±5to ±15
±5to ±15
±5to ±15

3.0%

±5to ±15

0, +70

5.0%

± 5 to ± 15

0, +70

P

-55, +125
0, +70
-55, +125

P

8038CC

External frequency modulation.

8048BC
8048CC

Log amp 1V/decade (Adjustable). 120dB range.
with current input. Error referred to output.

±30mV
±60mV

±15
±15

0, +70
0, +70

J, P
J, P

8049BC

Antilog amplifier adjustab:J scale factor.

±10mV

±15

0, +70

J, P

8049CC

Error referred to input.

±30mV

±15

0, +70

J, P

8211M
8211C
8212M
8212C

Micropower voltage detector lindicator Ivoltage regulator I
programmable zener. Contains 1.15V micropower reference
plus comparator and hysteresis output. Main output
inverting (8212) or non-inverting (8211).

2 to 30
2 to 30
2 to 30
2 to 30

-55,
0,
-55,
0,

+125
+70
+125
+70

T
P, T
T
P, T

Note: All parameters are specified at Vsupp = ± 15V and TA = + 25"C unless otherwise noted.
'Package Key: D-Solder lid side brazed ceramic dual-in-line. F-Ceramic flat package. J-Glass frit seal ceramic dual-in-line. P-Plastic dual-in-line.
T-Metal can.

5·6

CMOS Power Supply Circuits
Type

Description

+1.5V to

ICL7660

Voltage Converter

The ICL7660 performs the complete supply voltage conversion from positive to negative for an input range of
+ IO.OV, resulting in complementary output voltages of -1.5V to --IO.OV.

ICL7663
ICL7664

Positive Regulator
Negative Regulator

The ICL7663 (positive) and ICL7664 (negative) series regulators are low-power, high-efficiency devices which accept
inputs from I. 6V to 16V and provide adjustable outputs over the same range at currents up to 40mA. Operating current is
typically less than 40~, regardless of load.

ICL7665

Programmable
Micropower
Voltage Detector

The ICL7665 contains two individually programmable voltage detectors on asingle chip. Requiring only - 3~ for operation, the device is intended for battery-operated systems and instruments which require high or low voltage warnings,
sellable trip points, or fault monitoring and correction.

B

5·7

OP-05
Low Bias Low Drift
Operational Amplifier
FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•
•
•
•

The OP-05 series of monolithic operational amplifiers
combines high performance in low signal level applications
with the flexibility of a fully protected, internally compensated op amp. OP-05 characteristics include low offset
voltage and bias current and high gain, input impedance,
CMRR and PSRR.

Low noise (0.6ILV, 0.1 Hz-10Hz)
Low drift with time and temperature
Low Vos (0.15mV max)
High CMRR, PSRR
High AVOL (300k min)
High Rdiff (>30MD)
High RCM
Internally compensated
Industry standard (741) pin configuration

The OP-05 is a plug-in replacement for 725, 108A and unnulled 741 devices, allowing instant performance improvement
without redesign. It is an excellent choice for a wide variety
of applications including strain gauge and thermocouple
i.lridges, high gain active filters, buffers, integrators, and
sample and hold amplifiers.

SIMPLIFIED SCHEMATIC

PIN CONFIGURATIONS

v+o---·--.---~~----~----~--~--~~-.--~~---+--.-~

(outline dwgs JA, PAl

OUTPUT

NON·

A,

INVERTING
INPUT

0"
0"

INVERTING
INPUT

A.

v-

ORDERING INFORMATION
TEMPERATURE
RANGE

PART

.

OP·05
OP·05
OP·05
OP·05A
OP·05A
OP·05C
OP·05C
OP·05C
OP·05E
OP·05E
OP·05E

-

55'C to + 125'C
55'C to + 125'C
55'C to + 125'C
55'C to + 125'C
O'C to + 70'C
O'C to + 70'C
O'C to + 70'C
O'C to + 70'C
O'C to + 70'C
O'C to + 70'C

(outline dwg JD)

PACKAGE

ORDER #

dice
14'pin CERDIP
TO·99
14·pin CERDIP
TO·99
8·pin MiniDIP
14·pin CERDIP
TO·99
8·pin MiniDIP
14·pin CERDIP
TO·99

OP·05/D
OP·05Y·
OP·05J
OP·05AY·
OP·05AJ
OP·05CP
OP·05CY·

Not directly Interchangeable with LM108A

5-8

OP·05CJ
Op·05EP
Op·05EY·
OP·05EJ

V- (CASE)

(outline dwg TV)

OP-05
ABSOLUTE MAXIMUM RATINGS
Notel: Maximum package power dissipationvs ambient temperature.

Supply Voltage ................................ ± 22V
Internal Power Dissipation (Note 1) .............. 500mW
Differential Input Voltage ..........
. ......... ± 30V
Input Voltage (Note 2) ........................... ± 22V
Output Short Circuit Duration ................. Indefinite
Storage Temperature Range. . . . . .
- 65'C to + 150'C
Operating Temperature Range
OP-05A,OP·05 .................... - 55'C to + 125'C
OP·05E, OP-05C ....................... O'C to + 70'C
Lead Temperature (Soldering, 10 seconds) .......... 300'C

Package Type

Derate Above Maximum
Maximum Rated
Ambient Temperature Ambient Temperature

TO-99 (J)

BO'C

7.1mW/'C

Dual·ln-Une (Y)

100'C

10.0mW/'C

MiniDIP (P)

36'C

5.6mW/'C

Note 2: For supply voltages less than ± 22V, the absolute maxi·
mum input voltage is equal to the supply voltage.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS These specifications apply for Vs =

PARAMETER

SYMBOL

Input Offset Voltage

Vas

Long Term Input Offset

t:Noslt>t

TEST CONDITIONS

MIN

(Note 1)

± ISV, TA = + 2SoC, unless otherwise noted.

OP-OSA
TYP
0.07

MAX
0.15

0.2

1.0

MIN

OP·05
TYP

MAX

0.2

0.5

mV

0.2

1.0

~V/mo

UNITS

Voltage Stability

Input Offset Current
Input Bias Current

los
ISlAS

0.7

2.0

1.0

2.B

nA

±0.7

±2.0

± 1.0

±3.0

nA
~Vp·p

nVI..jHz.

Input Noise Voltage

enp.p

0.1 Hz to 10Hz (Note 2)

0.35

0.6

0.35

0.6

Input Noise Voltage
Density

en

10 = 10Hz (Note 2)
10= 100Hz (Note 2)
10 = 1000Hz (Note 2)

10.3
10.0
9.6

lB.O

10.3
10.0
9.6

lB.O

Input Noise Current

i np.p

0.1 Hz to 10Hz (Note 2)

in

10 = 10Hz (Note 2)
10 = 100Hz (Note 2)
fa = 1000Hz (Note 2)

Input Noise Current
Density

Input Resistance·
Differential Mode
Common-Mode

Rdill
RCM

Input Common· Mode

CMVR

30

13.0
11.0

13.0
11.0

14

30

14

30

pAp·p

0.32
0.14
0.12

O.BO

0.32
0.14
0.12

0.80
0.23
0.17

pA/..jHz.

0.23
0.17

20

BO

200

MO
GO

60
200

±13.5

±14.0

±13.5

±14.0

V

114

126

114

126

dB

Voltage Range

Common· Mode

CMRR

CMVR = ± 13.5V

Power Supply Rej. Ratio

PSRR

VsuPP = ± 3V to ± 18V

100

110

100

110

dB

Large Signal Voltage

AVOL

RL"= 2kO, Vo = ± 10V
RL"= 5000, Va = ± 0.5V,
Vs = ± 3V

300
150

500
500

200
150

500
500

VlmV

±Vo

RL"=10kO
RL"= 2kO
RL"= lkO

± 12.5
±12.0
± 10.5

± 13.0
±12.8
± 12.0

±12.5
± 12.0
± 10.5

±13.0
±12.8
± 12.0

Rejection Ratio

Gain
Maximum Output
Voltage Swing

V

Slew Rate

SR

RL"= 2kO (Note 2)

0.1

0.17

0.1

0.17

VI~s

Closed Loop Bandwidth

BW

Av = +1.0 (Note 2)

0.4

0.6

0.4

0.6

MHz

Open Loop Output Res.

Ro

Vo=O, 10 =0

60

Power Consumption

Pd
Vsupp = ±3V

90
4

Rp= 20kO

4

Olfset Adjustment Range

5-9

60
120
6

90
4

4

0
120
6

mW
mV

OP·05
OPERATING CHARACTERISTICS (Continued)
These specifications apply for Vs = ± 15V, TA

PARAMETER

SYMBOL

Inpui Offset Voltage

Vas

Long Term Input Offset

"Vos/"t

= + 25°C, unless otherwise noted.

TEST CONDITIONS

OP·OSE
MIN

(Note 1)

MAX

0.5

OP·OSC
TYP
0.3

1.3

mV

1.5

0.4

2.0

~V/mo

TYP

MAX

0.2
0.3

MIN

UNITS

Voltage Stability
Input Offset Current

los

Input Bias Current

ISlAS

Input Noise Voltage

1.2

3.8

1.8

6.0

nA

± 1.2

±4.0

± 1.8

±7.0

'nA

enp.p

0.1 Hz to 10Hz (Note 2)

0.35

0.6

0.38

0.65

~Vp·p

Input Noise Voltage
Density

en

fo
fa
fa

=10Hz (Note 2)
=100Hz (Note 2)
=1000Hz (Note 2)

10.3
10.0
9.6

18.0
13.0
11.0

10.5
10.2
9.8

20.0

nV/-./Hz

Input Noise Current

i np •p

0.1 Hz to 10Hz (Note 2)

in

fa = 10Hz (Note 2)
fa = 100Hz (Note 2)

Input Noise Current
Density

fa
Input Resistance·
Differential Mode
Common· Mode

=1000Hz (Note 2)
15

Rdiff
RCM

Input Common·Mode
Voltage Range

CMVR

Common· Mode
Rejection Ratio

CMRR

Power Supply Rejection
Ratio

13.5
11.5

14

30

15

35

pAp·p

0.32
0.14
0.12

0.80
0.23
0.17

0.35
0.15

0.90
0.27

pA/-./Hz

0.13

0.18

50
160

8

33
120

Mil
Gil

±13.5

±14.0

±13.0

±14.0

V

CMVR = ± 13.5V

110

123

100

120

dB

PSRR

Vsupp = ± 3V to ± 18V

94

107

90

104

dB

Large Signal Voltage
Gain

AVOL

RL2:2kll, Vo= ± 10V
RL2:5001l, Vo= ±0.5V
Vs=±3V

200

500
500

120
100

400
400

V/mV

150

Maximum Output
Voltage Swing

±Vo

±12.5

±13.0

±12.0

±12.0
±10.5

±12.8
±12.0

±11.5

±13.0
±12.8

Slew Rate

SR

RL 2: 2kll (Note 2)

0.1

0.17

0.1

0.17

V/~s

Closed Loop Bandwidth

BW

AVCL = +1.0 (Note 2)

0.4

0.6

0.4

0.6

MHz

Open Loop Output

Ro

Vo=O,lo=O

60

60

Il

Vsupp = ± 3V

90
4

RL2:10kll
RL2:2kll
RL2: lkll

V

±12.0

Resistance
Power Consumption

Pd

Offset Adjustment Range

4

Rp =20kll

120

95

150

6

4

8

4

mW
mV

,
Notel: Long term input offset voltage stability refers to the average trend lineof Vas vs time overextended periods after the first 30 days
of operation. Excluding the initial hourof operation, the change in Vos during the first 30 operating days is typically 25~V. Parameter is not
100% tested; 90% of units meet this specification.
Note 2: Parameter is not 100% tested; 90% of units meet this specification.

5·10

.D~DIl

OP-05
OPERATING CHARACTERISTICS (Coniinued)
These specifications apply for Vs = ± 15V, - 55·C" TAs + 12S·C, unless otherwise noted.

PARAMETER

SYMBOL

Input Offset Voltage

Vas

Input Offset Voltage Drift
Without External Trim
With External Trim

aVos/aT

Input Offset Current

TEST CONDITIONS

MIN

MAX
0.24

0.3

0.3
0.2

0.9
0.5

0.7
0.3

' 2.0

1.0

4.0

1.8

5.6

nA

50

pA/'C

los
alas/aT

Input Bias Current

ISlAS

Input Bias Current Drift

aiSIAs/aT

Input Common·Mode
Voltage Range

CMVR

Common·Mode Rej. Ratio

CMRR

CMVR= ±13.0

Power Supply Rej. Ratio

PSRR

Vsupp = ± 3V to ± 18V

Large Signal Voltage Gain Avo~

RL", 2kfl, Va = ± 10V

Output Voltage Swing

RL",2kfl

±Vo

(Average Tested)

5
±1.0

(Average Tested)

8

SYMBOL

Input Offset Voltage

Vas

Input Offset Voltage Drift
Without External Trim
With External Trim

aVos/aT

Input Clffset Current

los

Input Offset Current Drift

alas/aT

Input Bias Current

ISlAS

Input Bias Current Drift

alSIASlaT

Input Common·Mode
Voltage Range

CMVR

Common·Mode Rej. Ratio

CMRR

Power Supply Rej .. Ratio

PSRR

TEST CONDITIONS

mV

±6.0

25

13

50

123

94

106

200
±12.0

MIN

nA
pAl'C

±13.5

V

110

123

dB

94

106

dB

400

150

400

V

±12.6

±12.0

±12.6

V

± 1SV, O·CsTAs + IO·C, unless otherwise noted.

OP·OSE
TYP
0.25

MAX
0.6

MIN

Op·OSC
TYP
0.35

MAX
1.6

UNITS
mV
~V/'C

0.7
0.2

2.0
0.6
(Note 2)

1.2
0.4

4.5
1.5
(Note 2)

1.4

5.3

2.0

8.0

nA

8

35

12

50

pAl'C

±1.5

±5.5

±2.2

±9.0

13

35

18

50

± 13.0

±13.5

CMVR= ±13.0

107

123

Vsupp = ± 3V to ± 18V

90

104

RL",2kfl

8

"110

(Average Tested)

RL", 2kfl, Va = ± 10V

±Vo

UNITS

1.0

±2.0

±13.0

(Average Tested)

Large Signal Voltage Gain AVOL

25

±13.5

Rp = 20kfl
(Average Tested)

Output Voltage Swing

MAX
0.7

±4.0

± 13.0

OPERATING CHARACTERISTICS These specifications apply for Vs =

PARAMETER

MIN

~V/'C

Rp = 20kfl
(Average Tested)

Input Offset Current DriH

OP·05
TYP

OP·OSA
TYP
0.10

±13.0

V

97

120

dB

86

100

dB
V/mV

180

450

100

400

±12.6

±11.0

±12.6

5-11

pAl'C

±13.5

±12.0

Note 2: Parameter is not 100% tested; 90% of units meet this specification.

nA

V

.O~OIb

OP·05
TYPICAL PERFORMANCE CURVES
Trimmed Offset Voltage
vs Temperature
30

u.$'

03
"'w
::>CJ 20

.~~

,..0
.... >
::>>-'w
0",

10

"' ......
"':"0

1.0
Vos TRIMMED TO < 5.V AT25'C NULLING POT = 20kG
r-+-CD OP·OSA

1

i--'c-- 12l

@ OP·05C

I-- (j)

I\,

I2l

";:!

,\

I~

>-

I2l

0

50

-

-50

TEMPERATURE ('C)

-

::;;
;::

r-

I;:
-

-16

WEEK

,..

MO
M' 0

I
30

POWER SUPPLIES TURNED

4 ~~t~T'~=RO. Vos s100.V

"~

TEMPERATURE ('C)

TIME (MONTHS)

Offset Voltage Change
Due to l'tIerma I Shock

, Trimmed Offset Voltage
Drift as a Function 01
Trimming Potentiometer
(Rp) Si~e and Vos

z':i
~~

tu

II

:i5 tu~

-2

~ -4~B;B±ffiiEEf~tBiB±m±fffl

:r u

6 ...

0.001 0.01 0.1 1.0 10 100 1k 10k

10

$'

E
a:0>-

~~

,..;!;
::;;0
::>>::;;0

1.0

Vos NULLED TO

o

~,5~V ~T ,25~C I

70 0 e

=

W

~:i1

~

...~
~
,..

'l=l=+ITV;-;';;s1i"l
IVs= ot15V

>- ~ 25
:>

'"

o 1 2 3 4 5 6 7 8 9 10 1112

100

50

6

I M~N I D~Y I

$'
3

0.2.VIMO.
TREND LINE

g...,,2

Offset Voltage Drift
with Time
10
SEC

0.3.VlMO.
TREND LINE

12

w

to

I I

Vs= ot15V

16

~
:r

L I

Rs=50G

100

r-

l=

Op·05A- -

w

......'"
0
0.01

-50

OP·05 ~.....l-r
~!- ror·05E-1

>

CD

" ,

I-

-' 0.1
0

IW

\

OP·05C-::- -;-

.sw

~{$L~

@

(4J

$'

irt-

OP·05E

f--~@ OP·05

I--

Typical Offset Voltage
Stability vs Time

Untrimmed Offset
Voltage vs Temperature

20

THERMAL SHOCK
d"RESPONSE BAND

lr-

15

~=1J~t:~:t*~~~
10 H-fI--¥+-H-+++--H-l
O ...oI-

Vs= :t1_SV

Vs= ot15V

W

a;

a:

::>

• • •

"1'---

a:

L.:...~"","~'=""";'

1.0

OP·05C

-

~JE- ./
':::::: t:-;;:.,:.

TRIMMED
0.1 ace TO 70 0 e

0.01
0.1

100

Z

~~1'0~
,~~
~§
~

10

MATCHED
SOURCE RESISTANCE (kG)

Input Offset Current
vs Temperature

UNTRIMMED
O'CTO 70'C

w;!;

1.0

MATCHED
SOURCE RESISTANCE (kG)

Input Bias Current
vs Temperature

Maximum Error vs
Source Resistance

t5;:

0.01 l....J....LJ.illllL.....l-LllllJJL-LLWlll
1.0
10
0.1
100

MATCHED
SOURCE RESISTANCE (kQ)

100

./

OP·05A

_ _-=..J..U.wJ

10

OP·05

-50

0

50

TEMPERATURE ('C)

5-12

U

tu
~

.........

o

>-

~

;!;
100

c

u.

o
-50

:---

0

I-~~IOP.05E'-

P

OP.Q5 ...... I-"'"

OPi05~
50

TEMPERATURE ('C)

100,

flD~DlL

OP-05
TYPICAL PERFORMANCE CURVES (Continued)

OP·05 low Frequency Noise
1000

~o~

NOISE OF SOURCE
RESISTORS
INCLUDED

t--

100

>.

EXCLUDED

0;

~Rs

Vs- :!:15V
10
100
FREQUENCY (Hz)

1 SEC/em

Frequency
:!;

110

iii'
:!!. 100
a:
a: 90

PSRR

op·osc

op·OSC

120

10

100

lk

"-

iii' 100

10k

z

z

g

40

c

20

TA =25°C

Z

~

/

$

20

0..

16

~

12

~

100 lk 10k lOOk 1M 10M
FREQUENCY (Hz)

:;;

::;;

~

1

20
40
60
TOTAL SUPPLY VOLTAGE,
V+ TOV-,(V)

5

0
0.01

0.001

NEGATIVE
SWING

~ ct

20

~ffi

10

-30

~"'

-10

10

LOAD RESISTOR TO GROUND (kO)

1-'7

,...::1:T
",'.0V,
'" 2nA (OP·OSA)
'" anA (OP·OS)
'" 7nA (OP·OSC)

-~
-30 -20 -10

0

~z
~~
c:..,

o ~~

!
IVOIFFI

-10
-20

-20

V

I-a:
a:
a:
w:;,

i~

5·13

1.0

Vs:::: ±15V
TA = 25°C .

>0

1.0

0.1

FREQUENCY (MHz)

~§.

o
0.1

:::20

\

30

IIIII

V'
i/

±1S

Input Bias Current vs
Differential
Input Voltage

20 Op·os
TA = 25°C
POSITIVE
Vs= ±15V
15 VIN - +10m v I--SWING

10

±10

Op·o5
Vs= ±15V
TA = 25°C

g
0..
I-

:;,

W

o

24

:;,

:;,

~
o

;:!:5

I-

I-

10

28

~

Output Power YS load

C!J

~

Z

~
0..

::1W

.......
10

2:

a

Maximum Undistorted
Output vs Frequency

YS

Op·os
TA 25°C

0100

~

....... r-..,

POWER SUPPLY VOLTAGE (V)

-20
10 100 lk 10k lOOk 1M 10M

Power Consumption
Power Supply

o

10k

"'-

FREQUENCY (Hz)

~
ei

lk

OP·OS
Vs=:t15V

""- ~

60

§o

-20
-40
0.1

2i
a:

100

100

iii' 80
:!!.

0..

1'\.

I

10

Closed loop Response
for Various
Gain Configurations

C!J

1'\.

1000

1.0

FREQUENCY (Hz)

;;:

60

W
0..

o

--

./

0..

§ 400
o

50
0.1

lOOk

op·os
Vs= :t15V
TA = 25°C

; . 80

40

C!J

op·os

6~

Open loop Frequency
Response

20

~

z

70

FREQUENCY (Hz)

~

Op·os

~ 200

60
1.0

9z

100

TA=25°C

;;: 600

0..

70

~

1000

:;;E 800

(/)

~

80

I
I

100

iii'
:!!. 90
a:
a: 80

op·os

0

TA=2 5°C

c

1.0
10
BANDWIDTH (kHz)

Open Loop Gain YS
Power Supply Voltage

Frequency

110

I1111

:;;

YS

0.1
0.1

1000

120

lSV

iAlir

1.0

TA -25°C
1

Vs-

V

(/)

::;;
a:

0

op·os

1

130

'"'

0

(/)

~

0..

120

TA - + 25°C

:;;Z

10 r-

Zc
1-:;,

;!:

YS

Op·os
Vs +15V

W

W N

(/)::1:

CMRR

10

~RS1- RS2 =200kOTHERMAL

....

W

C!J

I'

Input Wideband Noise YS
Bandwidth (0.1 Hz to
Frequency Indicated)

Input Spot Noise Voltage
YS Frequency

10

20

Iisl

10
20

W
30

DIFFERENTIAL INPUT VOLTAGE (V)

~z

_"0

~=i

OP·05
TEST CIRCUITS

son
vo
Vos=~
4000

v-

Offset Voltage Test Circuit

Figure 1. Offset Nulling Circuit

r------o~+3V TO

loon

+ BV

OUT

1000

2.4MO

2.5MO
INPUT REFERRED NOISE =

.10Hz FILTER

~,SO ~"" 200nV/cm

25,000

25,000

v+

Low Frequency Noise Test Circuit

Figure 2. Auto·Nulling Circuit for OP·05

APPLICATIONS
OP·05 Series devices may be fitted directly to 725 and
108/108A' Series sockets with or without removal of external
compensation components. Additionally, OP·05 may be fit·
ted to unnulled 741 Series sockets; however, if conventional
741 nulling circuitry is in use, it should be modified or reo
moved to enable proper OP·05 operation (see Figure 1). The
OP·05 provides stable operation with load capacitances up
to 500pF and ± 10V swings; larger capacitances should be
decoupled with a 50n decoupling resistor. The designer is
cautioned that stray thermoelectric voltages generated by
dissimilar metals at the contacts to the input terminals can
prevent realization of the drift performance indicated. Best
operation will be obtained when both input contacts are
maintained at the same temperature, preferably close to the
temperature of the device's package.
-fl15V

Figure 2 shows how it is possible to combine the low noise
and output drive capability of the OP·05 with the low offset
and drift of the ICL7650 chopper stabilized op·amp to yield a
circuit which has a Vos of less than 5",V (typically 1",V),
temperature drift of t

(Note 2)

0.2

1.0

0.2

1.0

~V/mo

Voltage Stability
Input Offset Current

los

Input Bias Current

IBIAS

.Input Noise Voltage

enp.p

0.1 Hz to 10Hz (Note 3)

0.35

0.6

0.35

0.6

I'Vp·p

en

to = 10Hz (Note 3)
to = 100Hz (Note 3)

10.3

18.0

10.3

nV/,jHz

10.0
9.6

13.0
11.0

10.0
9.6

18.0
13.0
11.0

Input Noise Voltage
Density

to = 1000Hz (Note 3)
Input Noise Current
Input Noise Current
Density

i np. p

0.1 Hz to 10Hz (Note 3)

in

to - 10Hz (Note 3)
to = 100Hz (Note 3)
to = 1000Hz (Note 3)

0.3

2.0

0.4

2.B

nA

±0.7

±2.0

± 1.0

±3.0

nA

14

30

14

30

pAp-p

0.32
0.14

O.BO
0.23
0.17

0.32
0.14
0.12

O.BO
0.23
0.17

pA/..jHz

0.12

Input Resistance
Differential Mode
Common·Mode

30

Rdiff
ReM

80

20

200

60

MD

200

GD

Input Common-Mode
Voltage Range

CMVR

±13.0

±14.0

±13.0

±14.0

V

Common-Mode

CMRR

CMVR = ± 13.0V

110

126

110

126

dB

Power Supply Rej. Ratio

PSRR

Vsupp = ± 3V to ± 1BV

100

110

100

110

dB

Large Signal Voltage
Gain

AvoL

RL", 2kD, Va = ± 10V
RL", 500D, Va = ± 0.5V,

300

500

200

500

V/mV

150

500

150

500

±12.5
±12.0
±10.5

± 13.0
±12.B
±12.0

± 12.5

±13.0
± 12.B

Rejection Ratio

Vsupp = ± 3V
Maximum Output

±Vo.

Voltage Swing

RL", 10kn
RL",2kn
RL", 1kn

±12.0
±10.5

V

±12.0

Slew Rate

SR

RL", 2kn (Note 3)

0.1

0.17

0.1

0.17

VII'S

Closed Loop Bandwidth

BW

Av = + 1.0 (Note 3)

0.4

0.6

0.4

0.6

MHz

Open Loop Output Res.

Ro

Vo=O,lo=O

Power Consumption

Pd

60

Vsupp = ± 3V
Offset Adjustment Range

Rp = 20kn

D

120

75

120

4

6

4

6

±4

5-17

60

75

±4

mW
mV

OP·07
OPERATING CHARACTERISTICS (Continued)
These specifications apply for Vsupp = ~ 15V, TA = + 25°C, unless otherwise no led.

PARAMETER

SYMBOL

TEST CONDITIONS

OP·07C

OP·07E
TYP

MAX

MIN

OP·07D

TYP

MAX

MIN

UNITS

TYP

MAX

Input Offsel Voltage

Vos

(Note t)

30

75

60

150

60

150

,V

Long Term Input Offset

AVOS 1M

(Note 2)

0.3

1.5

0.4

2.0

0.5

3.0

!lV/m,o

6.0

nA

MIN

Voltage Stability
Input Offset Current

los

Input Bias Current

I BIAS

Input Noise Voltage

enp.p

Input Noise Voltage

en

0.5

3.B

O.B

6.0

O.B

± 1.2

±4.0

± 1.8

±7.0

±2.0

0.1 Hz to 10Hz (Note 3)

0.35

0.6

fo.~

10.3
10.0
9.6
14

10Hz (Note 3)

fo ~ 100Hz (Note 3)

Den~ity

fo

~

1000Hz (Note 3)

12

nA

0.3B

0.65

,Vp·p

nV/..jHz

:t

0.3B

0.65

1B.0

10.5

20.0

10.5

20.0

13.0

10.2

13.5

10.2

13.5

11.0

9.B

11.5

9.B

11.5

30

15

35

15

Input Noise Current

i nD. p

0.1Hz to 10Hz (Note 3)

35

pAp·p

Input Noise Current
Density

in

fo = 10Hz (Note 3)

0.32

0.80

0.35

0.90

0.35

0.90

pA/..jHz

fo ~ 100Hz (Note 3)

0.14

0.23

0.15

0.27

0.15

0.27

fo ~ 1000Hz (Note 3)

0.12

0.17

0.13

0.18

0.13

0.18

Input Resistance
Differential Mode

Rdiff

Common·Mode

RCM

Input Common·Mode

15

50

8

160

33

7

120

±13.Q

31

Mil

120

Gil

±13.0

±14.0

±13.0

±14.0

106

123

100

120

94

110

dB

94

107

90

104

90

104

dB

200

500

120.

400

120

400

V1mV

150

500

100

400

-

-

RL;?:: 10kn
RL;?:: 2kO

±12.5

±13.0

±12.0

±13.0

±12.0

±12.B

±11.5

±12.B

RL2::1kn

±10.5

±12.0

-

±12.0

CMVR

± 14.0

V

Voltage Range

Common· Mode

II

~

CMRR

CMVR

PSRR

Vsupp

AVOL

RL~2kO,

± 13.0V

Rejection Ratio
Power Supply Rejection

= ± 3V to

± l8V

Ratio
Large Signal Voltage

Vo = ± lOV

RL" 5000, Vo ~ ± 0.5V,

Gain

Vsupp;:: ± 3V

Maximum Output

±Va

Voltage Swing

Slew. Rate

SR

RL" 2kll (Note 3)

Closed Loop Bandwidth

BW

AVOL ~

+ 1.0 (Note 3)

Open Loop Output

Ro

Vo~O,

10=0

±12.0
±11.5

V

±13.0
±12.B

-

-

0.1

0.17

0.1

0.17

0.1

0.17

VI,s

0.4

0.6

0.4

0.6

0.4

0.6

MHz

60

Il

60

60

Resistance
Power Consumption

Pd

Vsupp - ± 3V
Offset Adjustment Range

Rp~

20kll

75

120

BO

150

BO

150

4

6

4

8

4

B

±4

±4

±4

mW
mV

Note 1: Input offset voltage measurements are performed by automated test equipment approximately 0.5 seconds after application of
power. Additionally, OP-07A offset voltage is measured 5 minutes after power supply application at - 55'C, + 25'C and + 125'C.
Note 2: Long term input offset voltage stability refers to the average trend line of Vos vs time over extended periods after the first 30 days of
operation. Excluding the initial hour of operation, the change in Vos during the first 30 operating days is typically 25~V. Pa.rameter is not
100% tested; 90% of units meet this specification.
Nole 3: Parameter is not 100% tested; at least 90% of units meet this specification.

5-18

IIO~OIl

OP~07
OPERATING CHARACTERISTICS (Continued)
These specifications apply for Vsupp = :!: 15V, - 55°C:5TA:5

PARAMETER

+ 125°C, unless otherwise noted.

SYMBOL

TEST CONDITIONS

Input Offset Voltage

Vas

INote 1)

Input Offset Voltage Drift

AVoslAT

(Average Tested)

Without External Trim
With External Trim

MIN

OP·07A
TYP

MAX

25

60

los

Input 0ffset Current Drift

AloslAT

Input Bias Current

(Average Tested)

'Al s1AS /.1.T

Input Common-Mode

CMVR

MAX

60

200

UNITS
"V

0.2
0.2

0.6
0.6

0.3
0.3

1.3

0.8

4.0

1.2

5.6

nA

5

25

8

50

pAI"C

±to

'SIAS

Input Bias Current Drift

OP·07
TYP

.VI"C

Rp = 20kn (Note 3)

Input Offset Current

MIN

(Average Tested)

1.3

±4.0

±2.0

±6.0

25

13

50

8
± 13.0

±13.5

±13.0

nA
pAI"C

±13.5

V
dB

Voltage Range
Common·Mode Rej. Ratio

CMRR

CMVR= ± 13.0

106

123

106

123

Power Supply Rej. Ratio

PSRR

Vsupp = ± 3V to ± 18V

94

106

94

106

dB

Large Signal Voltage Gain

AVOl

RL~2kO,

200

400

150

400

VlmV

Output Voltage Swing

±Va

RL;?: 2kO

±12.0

±12.6

±12.0

±12.6

Vo= ±10V

V

OPERATING CHARACTERISTICS
These specifications apply for Vsupp = ± 15V, ODC:5 TA :5

PARAMETER

SYMBOL

TEST CONDITIONS

Input Offset Voltage

Vas

(Note 1)

Input Offset Voltage Drift

::,vosl:; T

(Average Tested)

Without External Trim
With External Trim

+ 70°C, unless otherwise noted.

MIN

OP·07E
TYP

MAX

45

130

MIN

OP·07C
TYP

MAX

85

250

MIN

OP·07D
TYP

MAX

85

250

"V

(Note~)

"VI"C

(Note 3)

Rp = 20kn

0.7

0.3
0.3

1.3
1.3

0.5
0.4

0.9

5.3

1.6

8.0

1.6

8.0

nA

8

35

12

50

12

50

pAI"C

±1.5

±5.5

±2.2

±9.0

±3.0

±14

13

35

18

50

18

50

1.8
1.6

0.7

(Note 3)
Input Offset Current

los

Input Offset Current Drift

.1.los/,j,T

Input Bias Current

'SIAS

Input Bias Current Drift

~IBIAS/,l T

Input Common-Mode

CMVR

(Average Tested) IN ate 3)

(Average Tested) (Note 3)
± 13.0

UNITS

± 13.5

±13.0

±13.5

2.5
2.5

(Note 3)

±13.0

nA
pAI"C

± 13.5

V
dB

Voltage Range
Common-Mode Rej. Ratio

CMRR

CMVR= ± 13.0

103

123

97

120

94

106.

Power Supply Rej. Ratio

PSRR

Vsupp

90

104

86

100

86

100

dB

Large Signal Voltage Gain

AVOL

= ± 3V to ± 18V
RL 2!2kn, Vo = ± 10V

180

450

100

400

100

400

VlmV

Output Voltage Swing

±Vo

RL 2!2kn

±12.0

±12.6

±11.0

±12.6

±11.0

±12.6

V

Note 1: Input offset voltage"measurements are performed by automated test equipment approximately 0.5 seconds after application of
power. Additionally, OP·07A offset voltage is measured 5 minutes after power supply application at - 55°C, + 25°C and + 125°C.
Note 2: Long term input offset voltage stability refers to the average trend line of Vas vs time over extended periods after the first 30 days of
operation. Excluding the initial hour of operation, the change in Vas during the first 30 operating days is typically 25~V. Parameter is not
100% tested; 90% of units meet this specification.
Note 3: Parameter is not 100% tested; 'at least 90% of units meet this specification.

5-19

I

OP-07
TYPICAL PERFORMANCE CURVES
Untrimmed Offset
Voltage vs Temperature

Trimmed Offset Voltage
vs Temperature

Typical Offset Voltage
Stability vs Time

85

Iii

...0~

VS=±1SV
R=1000 - --j

75

~~

50

...0

25

....

...

:r

ff±:=

I- k:- -

OP.07E

!i

OP·07_

~

-50

50

0

5...

Offset Voltage Change
Due to Thermal Shock

Warm·Up Drill

Iii

......
0-

OP·07
Vs=±15V I -

800

II)

~:;
zeo

600

o.w

C!l
0.

9 400

!~

~

k-

wO

..

eo>
z

z

~ 200

:r

o

-50

50

"

100

20 40 60 80
TIME(SECONDS)

TEMPERATURE ('C)

Maximum Error vs
Source Resistance
W

W

0.8

0: ...

0::>

"'0.

"'Z 0.4
w:1;0

,,'"
:I;
x

..
:I;

1.0

TA=25"C
Vs= ±1SV

o

Gl
®

t::i>

w

a:.§, 0.6
0: ...

0"

cr:
2: 0.4
w-

:I;

0
10

100

Input Bias Current
vs Temperature
Vs= ±15V

~

OP·07A

o

0.1

z

...::>
0.

~

~IC

~ ~7E
OP·07

f-

t::;
./

OP·07A

-50

o~
o 1

0
50
100
TEMPERATURE ('C)

w

/

10

ffi

1.0

~~
0:-

0.8

ffi~

0.6

O"CsTs70°C
Vs= ±15V

/

0 ....

":I;

OP·07C

....

~

0.2

lIE

2.5

tzw

2.0

""
Iii

1.5

...0~
...
";!;
0.

1.0

°t

0.5

30
....

~!~

I
1

~~

OP.07

1

~ l\. ~7E

0j.071'

- 50

50

5-20

1.0
10
100
MATCHED OR UNMATCHED
SOURCE RESISTANCE (kO)

20

l

-30

Vs= :t15V

TA = 2S"C

10

..._w
w"
>"
~~ -10
",

0:",

1/

T

TEMPERATURE ('C)

0.1

./

Input Bias Current vs-··
Differential Input Voltage

V~=l'SJ
07

.-"

OP·07E

o

100

I

/J

:1;0 0.4

Input Offset Current
vs Temperature

..

"';IOP.07
OP·07A

1.2

0.

MATCHED OR UNMATCHED
SOURCE RESISTANCE (kO)

0:
0:

" r---

1.0

.5-

w
a:
a:

"
.,"~

OP·07E

0:

VI
V

OP·07

0.2

MATCHED OR UNMATCHED
SOURCE RESISTANCE (kO)

i...

-

"'0.

0.2

1.0

I!~P.(J7C

10

Maximum Error vs
Source Resistance

VS=J;15V

0.8

~g

0.1

TA=2S'C
Vs= ±15V

15

TIME AFTER POWER SUPPLY
TURN·ON (MINUTES)

- 55°C:s T $ 125°C

W

0:
0:

OP·07A
OP·07
@ OP·07E
@ OP·07C

o:§. 0.6

100

20

Maximum Error vs
Source Resistance

1.0
0

...w>-

2 3 4 5 6 7 8 9 10 1112

25

;;-

0:
0:

o1

TIME (MONTHS)

1000

II

~

12

-50
50
100
TEMPERATURE ('C)

Open Loop Gain vs
Temperature

~

0.2.VlMO.
TREND LINE

-16

100

TEMPERATURE ('C)

z

- 4

~ -8

OP·07A

II)

!

0.3,VIMO.
TREND LINE

12

:I;

;::

::oW

... eo
~~
~g

16

;;;

..;:.
w

OP·07C~

100

~

1:1)

-20

~~

I

1T IVolFFI s1.0V, IIBI
s 2nA (OP·07 A)
s3nA(OP.(J7)
s 7nA (OP·07C)

- 30
-30 -20 -10

10

20

30

30

DIFFERENTIAL INPUT VOLTAGE (V)

.D~D[b

OP-07
TYPICAL PERFORMANCE CURVES (Continued)

Input Wideband Noise vs
Bandwidth (0.1 Hz to
Frequency Indicated)

Total Input Noise Voltage
vs Frequency

OP·07 Low Frequency Noise

10

OP·07
Vs= ;1:15V

W

~~

TA - 25°C

~

>,

o~
z

WN

(/):z:
is x
z>

,/
1.0

(/)

~

I-S

:::>

'"

0.

!!;

0.1
0.1
1 SEC(cm

FREQUENCY (Hz)

1.0
10
BANDWIDTH (kHz)

CMRR vs Frequency

PSRR vs Frequency

Open Loop Gain vs
Power Supply Voltage

130

110

o

OP·07C

OP·07

'"'"

90

(/)

90

,

OP·07C

70

z

60

o

60

50
0.1

120

iii 100

~

100

1k

10k

100k

~ 200

~

10

100

100

iii
~

z


0

0100

~O

~g

OZ

:z:W

25

0. 0

I-

TA= + 25 C Q

r-...

(/)'"

1-'"
:::>:::>

1/

10

20

.....;;

(!)~ ::::

:::>

~0.

0

1
LOAD RESISTOR TO GROUND (kOi

\

>

W

10

16

FREQUENCY (MHz)

~

'"

1.0

Vs= ±15V
TA =25°C

20

FREQUENCY (Hz)

1000

V

OP·07

0.

FREQUENCY (Hz)

NEGATIVE
SWING

28
24

I-

-20

I1111
TA=25°C
POSITIVE
Vs= :t15V
VIN=±10mV-S~

±20

:::>

-40

OP·07

:t1S

Maximum Undistorted
Output vs Frequency

o

0

0.1 1

:!:10

~ 12

.......

g

-20

~

:Ii0.
~

TA =25°C

"-

±s

POWER SUPPLY VOLTAGE (V)

OP·07
Vs= ±15V

80
60

"0

40
20

1.0

Closed Loop Response
lor Various
Gain Configurations

OP·07
Vs= :!:15V
TA =25°C

80

~
FREQUENCY (Hz)

ifi0.
o

400

70

10

......

0.

I

Open Loop
Frequency Response

g;
9

"
S

80

0.

FREOUENCY (Hz)

i

z
Ci 600

OP·07

80

1.0

TA = 25°C

E 800
~

I
I

100
~

OP·07

;;-

110

iii

11111

1000

TA=25°C

iAlirc

iii
:E. 100

'"~

120

Vs- ::t15V

120

100

o

15

20

40

TOTAL SUPPLY VOLTAGE.
v+ TO V- (V)

5-21

60

o
TIME FROM OUTPUT BEING
SHORTED (MINUTES)

OP·07
TEST CIRCUITS
20Qkfl

50n
Vo

Vos=~

4000

v-

Offset Voltage Test Circuit

Figure 1. Offset Nulling Circuit

.---,---.....,-0 ~+3V TO + 8V
+15V

OUT

3.3ka

OUTPUT

2.4MO
-15V
2.SMn
INPUT REFERRED NOISE

".,10Hz FILTER

= ~,so 5mV/cm
25.000

s;

200nVlcrn

25.000

v+

Low Frequency Noise Test Circuit

Figure 2. Auto·Nulling Circuit forOP·07

APPLICATIONS
Figure 2 shows how it is possible to combine the low noise
and output drive capability of the OP·07 with the low offset
and drift of the ICL7650 chopper stabilized op·amp to yield a
circuit which has a Vos of less than 5JLV (typically 1JLV),
temperature drift of < O.D1ItV/·C, long term drift of less than
1JLV per year and input noise voltage of 10nV/-jRZ, while at
the same time driving loads of up to 2kn.

OP·07 series devices may be inserted directly in 725 and
108/108A * series sockets with or without removal of external
compensation components. Additionally, the OP·07 may be
fitted to unnulled 741 series sockets; however, if conventional
741 nulling circuitry is in use,. it should be modified or reo
moved to enable proper OP·07 operation (see Figure 1). The
OP·07 provides stable operation with load capacitances up
to 500pF arid ± 10V swings; larger capacitances should be
decoupled with a 50f4 decoupling resistor. The designer is
cautioned that stray thermoelectric voltages generated by
dissimilar metals at the contacts to the input terminals can
prevent realization of the drift performance indicated. Best
operation will be obtained when both input contacts are
maintained at the same temperature, preferably close to the
temperature of the device's package .
• except "Y" package

The exceptional input characteristics of the OP·07 are used
to advantage in Figure 3 with the ICL7134B 14·bit monolithic
DAC. Both the reference inversion amplifier, A 3, and the out·
put amplifier, A 1, require offset voltages and input currents of
around 251N and 2nA respectively, to maintain the required
accuracy.

VREF IN - - - - . ,
18
VRFL
RINVl

19

20

RtNV
RINV2

VRFM

V+

21

0---..!4 013 (MSB)

RFB 1---.....- - - - -

~D12
I

lOUT ;'=~""'-'---t

DATA
INPUTS

ICl71348

!
I

I
I

VOUT

I

0--1----2. Do (LSB)
+5V 17

PROG
WA

C-S

t2 t1

At

t27

Figure 3. OP·07s.Used·for Reference Inversion and Voltage Output with ICL7134B DAC

5·22

OP-07
CHIP TOPOGRAPHY
v;

O/N

Iill
OIP

+

0.062 in

+IN

.I"

---_.j

I

5-23

LM108/A, LM308/A
Low Level Operational Amplifiers

FEATURES

GEN.eRAL DESCRIPTION

•
•
•
•
•
•

Thase differential input, precision amplifiers provide low input
currents andojfset voltages competitive with FET and chopper
stabilized amplifiers. They feature low power consumption over
a supply v,oltage range of >2V to ±20V. The amplifiers may be
frequency,compensated with a single external capacitor. The
LM 108A and I,M308A are high performance selections from the
1081308 amplifier family .

Input Bias Current - 2 nA max to 7 nA max
Input Offset Current - 0.2 nA max to 1 nAmax
Input OffsetVoltage -0.5 mV max t07.5 mV max
6. Vos/6.T - 5 p'vrc to 30 p'vrC
6.los/6.T - 2.5 pArC to 10 pArC
Pin for Pin Replacement for 101A!301A

8

PIN CONFIGURATIONS

FREQ caMP A
-IN

I

FREO caMP B

+IN

vOUT
NC

V

(outline dwg PAl

NON INVERTING

INPUT

TOP VIEW

(outline dwg JD)
FREQ. COMP, B

V'

NC

caMP

GUARD

caMP

-IN

V+

+IN

OUT

v-

GUARD

TOP VIEW

(outline dwg F8-1)

(outline dwg TV)

ORDERING INFORMATION
Part
number

TO-99
Can

8 pin
MiniDIP

LM108A
L"1308A

LM108AH"
LM308AH

LM308AN

LM108
LM308

LM108H"
LM308H

LM308N

-

-

14 pin
CERDIP

10 pin
Flalpak

Dic"

LM108AJ
LM308AJ

LM108AF
LM30BAF

LM108ND
LM308ND

LM10BJ
LM30BJ

LM108F
LM308F

LM108/D
LM308!D

"If 8838 proceSSing is desired add 18838 10 order number,

5-24

LM108/A, LM308/A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
l08,l08A
308,30M
Internal Power Dissipation (Note 1)
Metal Can (T0·99
DIP
Differential Input Current (Note 2)
Input Voltage (Note 3)

ct18V

SOOmW
SOOmW
ctl0mA
ct15V

ELECTRICAL CHARACTERISTICS
PARAMETER

Output Short·Circuit Duration
Indefinite
Operating Temperature Range
-55°C to +125°C
l08,l08A
O°C to +70°C
308,308A
Storage Temperature R~nge
-65°C to + 150°C
300°C
Lead Temperature (Soldering, 60 sec.)

ct20V

(T A ~ 25°C unless otherwise specified)

308

CONOIHONS
MIN

(Note 4)

108

308A

TYP

MAX

MIN

TYP

MAX

MIN

TYP

lDBA
MAX

MIN

TYP

UNITS
MAX

Input Offset Voltage

20

7.S

0.3

O.S

07

2.0

0.3

Input Offset Current

02

1.0

0.2

1.0

OOS

0.2

O.OS 0.2

nA

Input BIas Current

1.5

7

1.5

7

0.8

20

0.8

2.0

nA

Input ReSistance
Supply Current

Large Signal
Voltage Gain

10

40

10

40

30

Vs;:; ±20V

0.3

Vs:= .t15V
Vs = ±15V, V OUT '" ±10V

R L ;> 10 kll

70

0.3

25

0.8

300

0.3

80

30
0.6

0.5

MD

70
0.3

0.6

0.8

300

50

80

300

mV

mA
mA

V/mV

300

THE FOLLOWING SPECIFICATIONS APPLY OVER THE OPERATING TEMPERATURE RANGES

Input Offset Voltage

10

Input Offset Current

1.5

0.73

3.0

1.0

mV

1.5

0.4

0.4

nA

1.0

S.O

jJvte

O.S

2.5

pAte

Average Temperature
CoeffiCient of Input

6.0

30

1.0

2

10

2.0

3.0

5.0

15

Offset Voltage

Average Temperature
Coefficient of Input

0.5

10

2.S

Offset Current
Input Bias Current

10

Large Signal
Voltage Gain

Vs = ±15V, VOU1-::: !10V
RL? 10k!)

Input Voltage Range

Vs = ±15V

15

3.0

10
60

±13.5

25

±13.S

3.0
40
± 13.5

±13.5

nA
V/mV
V

Common Mode
Rejection RatiO

80

100

96

110

85

100

96

110

dB

SuppiV Voltage

80

96

96

110

80

96

96

110

dB

± 13

±14

±13

±14

13

±14

±13

·±14

Rejection RatiO
Output Voltage Swmg

Vs " ±15V, RL " 10 kSl

Supply Current

TA

0

+12S"e, Vs" ±20V

!

0.15

0.4

NOTE 1: Derate Metal Can package at 6.8 mwtC for operation at ambient temperatures abolle 75°C and Ihe Oual In·Line package al
9 mW/"C for operation at ambient temperatures above 9S"C
NOTE 2: The inputs are shunted With back-la-back diodes for over-voltage protection. Therefore, e)(ceSSlve current Will flow it a differential
input voltage In excess of lV is applied between the Inputs unless some limiting resistance is used
NOTE 3: For supply voltages less than! 15V, the mall.lmum Input lIoltage

15

equal to the supply voltage

NOTE 4: Unless otherwise specified, these specifications apply for supply voltages from ~5V to ~20V for th.1OB, and 108A and
:': SV to :t 15V tor the 308 and 308A

5·25

0.1'5

V
0.4

rnA

.U~UIL

LM108/A, LM308/A
TYPICAL PERFORMANCE CURVES
INPUT CURRENTS
2.0

1.5

11.0
....
ffi

0.5

3JI3~A~IAL
r---! I'r--.,.
108AIl08 Ir-

i'--

"" otJ-

~O.\5
0.10

1.0

-55-35-15 5 25 45 6585105125
TEMPERATURE I'CI

> 10

t7

t;;

o
....

-55

C<~A< 125'C

O°C

< TA <

1M

70'C
100M

10M

POWER SUPPLY REJECTION

~

~ i--"

~_ 1.0

z

100A

<1. < 125'C

='08II08A. -55'C

r-

zw

-3081308k
-'
~ 01
1M
:;
lOOk

8

INPUT RESISTANCE lUI

O'C

< T. <

7O'C
100M

10M

INPUT RESISTANCE lUI

VOLTAGE GAIN

INPUT NOISE VOLTAGE

120

r

1- 30

I-

l-

i2

108A

I- 3081308A.

lOOk

308-

o

If'

,,

kdl~1

"-

~ 1081l08A.

o

100AI\08

r--

~

r.r..-

10

~

":;«

f"/.

I-'

w

t;:

w

30~A

I

308

MAXIMUM OFFSET ERROR

E100

I

1-108

a:
oa:
a:

3081308A OFFSET

:>

I

P
~100

r-?-

a:
""j>
a: 0.25
u
.... 0.20
:>

:>

MAXIMUM DRIFT ERROR
lk

1000

_100
=

60

'--,

~

0

~

is
z

cr: 40

::;

DJ

it

Rs::: 1M

~ 100
Rs = lOOk

....
~

20

As::: 0

40

;<:

:>

'"

-20

I

10
100

lk

10k

lOOk

1M

10

10M

100

OUTPUT SWING

r-

~

t'-.

........

Vs

.....

10

""

\

5

Qac-i+-II

TA '"
I
I

:>

o

T1rell

600

120

_ 500

100

«

.;!

iii

~400

z

~ 80

~

w

1."-

cr:

~

306

w

~200

....

HIt

-'

it

0

>

:>
'" 100

--

§

10

10'

u

~ 12

~ 10'

z

w

z

~
....
:>
....Q.:>

~

"

;: 10°

ii:....

100

lk

10k

lOOk

FREQUENCY IHzl

1M

10M

:+(

f------tC"

10

100

Ik

,

'r-

z

4
2

:;i!

-2

~w

8
C, '" 3 pF

~

ft

C"=13

i\

I-

10k

lOOk

~ -4
> -6

FREQUENCY IHzl

5-26

-8
-10
1M

)

INPUT

0yTP~T

1

I

o

",.....

f- Ir- '-

~

!\

!7

1\

T. - 25'C

I
I
o

Vs=:!:15V

C, = 30pF
40

o

10k lOOk 1M 10M

8

~ 6
<:!

Ik

~

45

10

T A'" 25°C
V s =±15V

:!!

80
TIME

120
I~sl

:3
w

C,' 30 pFF~

GAIN
PHASE ___

135i
<:!

~

100 pF

VOLTAGE FOLLOWER
PU LSE R.ESPONSE

L---L_...J.._...L._.:..Vs~=-=-"~5,,:,V---l
10

"

f-- _C,=3pF.

180

90

~

LARGE SIGNAL
FREQUENCY RESPONSE

lOUT'" ±1 mA

10-2

" ..

#

I-

'/V

20

15

......C,= 30 pF ~

FREQUENCY IHzl

o

5 10·' 1--++-+-+-

......

c,,' 100 p~'\

SUPPLY VOLTAGE I'VI

<:!

w

""

20
0

OUTPUT CURRENT ('mAl

16

C, = 3 pF_

-20

0

CLOSEO LOOP
OUTPUTIMPEDENCE

"" '"

60

~ 40

u

I
T. = 2 h l

:>

20

:!:15V

T. = 70'C

'"....

:=

T. = 125'C

1

~

:--...

15

OPEN LOOP
FREQUENCY RESPONSE

SUPPLY CURRENT

.\
<:!
Z

10

SUPPLY VOLTAGE I'VI

FREOUENCY IHzl

FREQUENCY IHzl

15

90
lOOk

10k

Ik

160

i1:

LM10S/A, LM30S/A
GUARDING
Extra care must be taken in the assembly of printed circuit
boards to take full advantage of the low input currents of
the 108 amplifier. Boards must be thoroughly cleaned with
TCE or alcohol and blown dry with compressed air. After
cleaning, the boards should be coated with epoxy or
silicone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble at 125°C, particularly since the
input pins are adjacent to pins that are at supply potentials.
This leakage can be significantly reduced by using guarding
to lower the voltage difference between the inputs and
adjacent metal runs. Input guarding of the 8·lead TO·99

package is accomplished by using a .10·lead pin circle, with
the leads of the device formed so that the holes adjacent
to the inputs are empty when it is inserted in the board. The
guard, which is a conductive ring surrounding the inputs,
is connected to a low impedance point that is at approxi·
mately the same voltage at the inputs. Leakage currents
from high·voltage pins are then absorbed by the guard.
The pin configuration of the dual in·line package is designed
to facilitate guarding, since the pins adjacent to the inputs
are not used (this is different from the standard 741 and
lOlA pin configuration).

FREQUENCY COMPENSATION CIRCUITS
ALTERNATE CIRCUIT, IMPROVES REJECTION OF
POWER SUPPL Y NOISE BY A FACTOR OF TEN.

STANDARD CIRCUIT

R,

R,

OUTPUT

OUTPUT

NON

NON-I NVE ~~!~~ D--'V\R'tv-_-l

INVE~~~~~ D---.R",''v-_-;

I

c,
Co' 30 pF

5-27

C,
1°OPF

AD590
Temperature Transduc.r
in which conventional electrical temperature sensors are
currently employed. The inherent low cost of a monolithic
integrated circuit combined with the elimination of support
circuitry makes the AD590 an attractive alternative for many
temperature measurement situations. Linearization circuitry, precision voltage amplifiers, resistance-measuring
circuitry and cold-junction compensation are not needed in
applying the AD590. In the simplest application, a resistor, a
power source and any voltmeter can be used to measure
temperature.

FEATURES
•
•
•
•

Linear current output: 1 p,AJOK
Wide range: - 55°C to +150°C
Two-terminal device: Voltage in/current out
Laser trimmed to ±O.5°C calibration accuracy

(AD590M)
•
•
•
•

Excellent linearity: ± O.5°C over full range (AD590M)
Wide power supply range: + 4V to + 30V
Se.nsor isolation from case
Low cost

In addition to temperature measurement, applications include temperature compensation or correction of discrete
components, and biasing proportional to absolute temperature. The AD590 is available in chip form making it suitable
for hytirid circuits and fast temperature measurements in
protected environments.

GENERAL DESCRIPTION
The AD590 is an integrated-circuit temperature transducer
which produces an output current proportional to absolute
temperature. The device acts as a high impedance constant
current regulator, passing 1J
0

298.2

I-

:::>
CL

I-

218

:::>

0

/

V

/
VouT-1mVfOK

lkO

218°K 298.2°K 423°K
(-55°C) (+25°C) (+I50°C)
TEMPERATURE

Figure 6. Simple connection. Output is proportional to absolute
temperature.
+15V

v+

(AODI1'IONAL
SENSORS)

R
333.30
0.1%

i0ka
0.1%

(FOR 3 SENSORS)

Figure 8. Average·temperature sensing scheme. The sum of the
AD590 currents appears across R, which is chosen by
the formula

Figure 7. Lowest·temperature sensing scheme. Available cur·
rent is that of the "coldest" sensor.

R= 10kll ,

n
n being the number of sensors.

+15V

-,
I
I ~~:~i~T
I

AD590

.J
R,

R2
IC(8069
1.23V
R3

Figure 9. Single·setpoint temperature controller. The AD590 pro·
duces a temperature·dependent voltage "cross R (C is
for filtering noise). Setting R2 produces a scale·zero
voltage. For the Celsius scale, make R = 1kll and
VZERO = 0.273 volts. For Fahrenheit, R = 1.Bkll and
VZERO = 0.460 volts.

5-34

AD590
TYPICAL APPLICATIONS (Cont'd)
COLUMN
SELECT

+15V

ENABLE

ROW
SELECT

+15V

ENABLE

~

R
(OPTIONAL)

IH6108
a-CHANNEL MUX

5

5 1

IH6108
a·cHANNEL
MUX

12 4

11

10 6

R
(OPTIONAL)

.".

AD590 (64)

10kn
0.1%

I

Your

j

Figure 10. Multiplexing sensors. If shorted sensors are possible, a series resistor in series with
the D line will limit the current (shown as R, above: only one is needed). A six-bit
digital word will select one of 64 sensors.

,--"""1......- - - - - - - - - < l

+15V

1kn
ZERO SET

44.2kO

v+
(8Vmin)

V118kn
10kn

0.1%

-,
100n

10kn

20kn

FULL·SCALE
ADJUST

2.7315V

_I

Figure 11. Centigrade thermometer (O·C-l00·C). The ultra·low
bias current of the ICl7611 allows the use of largevalue gain-resistors, keeping meter-current error under
1/2%, and therefore saving the expense of an extra
meter·driving amplifier.

Figure 12. Differential thermometer. The 50kll pot trims offsets in
the devices whether internal or external, so it can be
used to set the size of the difference interval. This also
makes it useful for liquid·level detection (where there
will be a measurable temperature difference).

5-35

AD590
TYPICAL APPLICATIONS (Cont'd)
v+

r+

",A/'K

I

L

----------,
____ ___ _
+--__-.__

I
'I SEEBECK

---._~-'--+_C>__l_C::::O::E::.F:..:FI:::;:CIENT = 40,NloK

t

R,

Tc=

40.211

t

=

V,

401! V/oK

10.98mV

I

I

TYPEK

v+

Figure 13. Cold·junction compensation lor type K thermocouple.
The reference junction(s) should be in close thermal
contact with the AD590 case. V + must be at least 4V,
while ICLS069 current should be set at 1 mA-2 mAo
Calibration does not require shorting or removal of the
thermocouple: set R, for V2 = 10.9SmV. If very precise
measurements are needed, adjust R2 to the exact
Seebeck coefficient for the thermocouple used
(measured or from table) note V" and set R, to buck out
this voltage (I.e., set V2 = V,). For other thermocouple
types, adjust values to the appropriate Seebeck
coefficient.

VOUT

1

V2 = 10.98 40.21/

I

R,
45211/

500pA

+

Figure 14. Simplest thermometer, Meter displays current output
directly in degrees Kelvin. Using the AD590M, sensor
output is within ± 1.7 degrees over the entire range, and
less than ± 1 degree over the greater part of it.

v+

R
R,

R,

R2

R3

R4

Rs

1°F 9.00 4.02 2.0 12.4 10.0 0
loe 5.00 4.02 2.0 5.11 5.0 11.S

R,

5
R

E Rn = 2Sk!l (nominal)'

R,

1
All values in k!l

R4

The ICL7106 has a Y'N span of ± 2.0V, and a VCM range of (V + - 0.5)
Volts to (V - + 1) Volts; R is scaled to bring each range within VCM
while not exceeding Y,N' VAEF for both scales is 500mV. Maximum
reading on the Celsius range is 199.9'C, limited by the (short·term)
maximum allowable sensor temperature. Maximum reading on the
Fahrenheit range is 199.9'F (93.3'C), limited by the number of
display digits. See also note below.

Rs
COMMON
IN La
ADS90

vFigure 15. Basic digital thermometer, Celsius and Fahrenheit scales

5·36

AD590
y.

V'

7.5kO
2.28kO

1.235V

ZERO SkO
ADJ 1.000V

REFLO

SkO
SCALE
ADJ
15kO

121kO

ICL8069
REF HI

SkU

/

7.SkO
SCALE REF
ADJ
HI
/
REFLO

ICL7108
1kO.O.1%

lSkO

4020

28.1kO

COM

ICL7106
COM

INHI

INHI
INLO

1.00kO
ADS90

v-

y-

Figure 17. Basic digital thermometer, Kelvin scale with zero ad·
just. This circuit allows "zero adjustment" as well as
slope adjustment. The ICL8069 brings the input within
the common· mode range, while the 5kll pots trim any
offset at 218'K ( - 55'C), and set scale factor.

Figure 16. Basic digital thermometer, Kelvin scale. The Kelvin
scale version reads from 0 to 1999'K theoretically, and
from 223'K to 473'K actually. The 2.26kll resistor brings
the input within the ICL7106 VCM range: 2 general·
purpose silicon diodes or an LED may be substituted.

Note on Figure 15, Figure 16 and Figure 17: Since all 3 scales have narrow VIN spans, some optimization of ICL7106 components can be made
to lower noise and preserve CMR. The table below shows the suggested values. Similar scaling can be used with the ICL7126/36.
Scale

VIN Range (V)

RINT(kll)

CAbF)

K

0.223 to 0.473

220

0.47

C

- 0.25 to

220

0.1

220

0.1

F

- 0.29 to

+ 1.0
+ 0.996

For all:
CREF = 0.11'F

Cosc= 100pF

C INT = 0.221'F

5·37

Rose = 100kll

I:
II

NE/SE592
Video Amplifier

FEATURES

DESCRIPTION

•
•
•
•
•

The NE/SE592 is a monolithic, two stage, differential output,
wideband video amplifier which offers fixed gains of 100 and
400 without external components and adjustable gains from
o to 400 with one extermi.1 resistor. The input stage has been
designed so that with the addition of a few external reactive
elements between the gain select terminals, the circuit can
function as a high pass, low pass, or b<;lnd pass filter. This
feature makes the circuit ideal for use as a video or pulse
amplifier in communications, magnetic memories, display,
video recorder systems, and floppy disc head amplifiers. The
NE/SE592 is a pin-for-pin replacement for the p.A733 in most
applications.

120MHz bandwidth
Adjustable gains fromO to 400
Adjustable pass band
No frequency compensation required
Wave shaping with minimal external components

ORDERING INFORMATION

PART
TYPE

TEMP
RANGE

SE592

- 55·C to
+ l25·C
O·C to
+70·C

NE592

PIN CONFIGURATIONS
l4·Pin 01 P Package
(JO, PO Package)

l4·Pin
Plastic

PACKAGE
l4·Pin
CEROIP

10·Pin
TO·l00

INPUT 1

-

SE592F

SE592H

NC

NE592N

NE592F

NE592H

G2A GAIN SELECT

EQUIVALENT CIRCUIT (resistor values

nominal only)

r-----~-----.----~~--~._------._--_+--~v·

2.4k

2.4k

TOP VIEW

10k

10·Pin TO-l00 Package
(H Package)
G2A GAIN

SELECT

+-----+------+--jf-------f-----............""-i-----+---oOUTPUT 1

L.------l---------'l.fVw-l---.......---OOUTPUT 2

vTOP VIEW

400

L-----~-----+--------~--------~~--_+--_ov-

Note: Pin 5 connected to case

NEISE592
ABSOLUTE MAXIMUM RATINGS
(TA = + 25'C unless otherwise specified)

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . ..
Common-Mode Input Voltage ....................
Output Current. .............................. ,

± BV

± 5V
± 6V
10mA

Operating Temperature Range
SE592 .......................... - 55'Cto + 125'C
NE592 ............................. O·Cto + 70·C
Storage Temperature Range .......... -65'Cto + 150'C
Power Dissipation ........................... 500mW

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any othec conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
TA = + 25·C. Vs = '" SV. VCM = 0 unless otherwise specified. Recommended operating supply voltages Vs = '" S.OV

PARAMETER
Differential Voltage Gain

SYMBOL

NE592

SE592

MIN

TYP

MAX

MIN

TYP

MAX

250
80

400
100

600
120

300
90

400
100

500
110

RL = 2kO. VOUT = 3Vp·p

40

40

Gain 2 (Note 2)

90

90

VOUT = 1Vp-p

10.5
4.5

6.0

Input Bias Current

, C'N

Gain 2

IBIAS
en
LlV,N

BW = 1kHz to 10MHz

VCM ± 1V. F < 100kHz
VCM±1V. F=5MHz

kO

30
2.0

pF

0.4

5.0

0.4

3:0

9.0

30

9.0

20

12

12

~A
~A
~Vrms

± 1.0

60

60

86

V

dB

86
60

60

PSRR

Gain 2 (Note 2)

50

LlVs = ± 0.5V

70

50

dB

70

Voos

Gain 2 (Note 2)

Output Voltage Swing Differential

20

CMRR

Gain 2 (Note 2)

Output Common-Mode Voltage

ns
10

4.0

30

'" 1.0

Gain 2 (Note 2)

Output Offset Voltage

7.5

2.0

los

Input Voltage Range

Supply Voltage Rejection Ratio

6.0

4.0
10

Input NOise Voltage

Common-Mode Rejection Ratio

10

ns
10

R'N

Gain 2 (Note 2)

Input Offset Current

10.5
4.5

7.5

VOUT = 1Vp-p

Gain 2 (Note 2)

Input Capacitance (Note 2)

12

td

Gain 1 (Note 1)

Input Resistance
Gain 1 (Note 1)

MHz

tr

Gain 2 (Note 2)
Propagation Delay

VIV

BW

Gain 1 (Note 1)

Rise Time
Gain 1 (Note 1)

UNIT

AvoL

Gain 1 (Note 1)
Gain 2 (Note 2)
Bandwidth

TEST CONDITIONS

RL =
VOCM
±Vo

Output Resistance

Ro

Power Supply Current

1+

00

0.35

0.75
3.4

RL = co

2.4

2.9

RL =2kO

3.0

4.0
20

RL =

18

00

Note 1: Gain select pins G'A and G'B connected together.
Note 2: Gain select pins G2A and G2B connected together.

5·39

24

V

0.35

0.75

2.4

2.9

3.4

3.0

4.0

V

20

0

18

24

V

rnA

NE/SE592
TYPICAL APPLICATIONS

Filter Networks

Basic Configuration (see note)

FILTER
TYPE

Z NETWORK
R

L

~

LOW PASS

1.4 X 10'
--L--

HIGH PASS

1.4x10'
--R--

BAND PASS

1.4x10'
--L--

C

V;

~~
~C~

Vo (s) TRANSFER
-VI (s) FUNCTION

[S+1R/CJ

[5+ ~/RCJ

J
J

~S2 + R/Lss + 1/LC

L

~

BAND REJECT

1.4x10' [2 S2+1/LC·
R
s +1/LC+s/RC

Note: In the networks above, the R value used is assumed to include the internal 2re of
approximately 320.

Disc/Tape Phase Modulated Readback Systems

Differentiation with ,",igh .
Common·Mode Noise Rejection

+5V
+6V

Q

1

___ ~ ___ .J

AMPLITUDE:
FREQUENCY:

1
READ HEAD

.,..1

DIFFERENTIATORIAMPLIFIER

ZERO CROSSING DETECTOR

For frequency F,« 1/2 7r (32)C
•

dVi

Vo'" 1.4 x 10 C-:ciT

5·40

NE592·8
Video Amplifier

FEATURES

DESCRIPTION

•
•
•
•
•

The NE59Z-8 is a monolithic,'two stage, differential output,
wideband video amplifier which offers a fixed gain of 400
without external components and adjustable gains from 0 to
400 with one external resistor. The input stage has been
designed so that with the addition of a few external reactive
elements between the gain select terminals, the circuit can
function as a high pass, low pass, or band pass filter. This
feature makes the circuit ideal for use as a video or pulse
amplifier in communications, magnetic memories, display,
video recorder systems, and floppy disc head amplifiers. The
NE592-8 is a pin-for-pin replacement for the "A733 in most
applications.

120MHz bandwidth
Adjustable gains from 0 to 400
Adjustable pass band
No frequency compensation required
Wave shaping with minimal external components

ORDE.RING INFORMATION

PIN CONFIGURATION

(outline dwg PAl

INPUT 1 1

PART
TYPE

TEMP
RANGE

PACKAGE

NE592

O°C to+ 70°C

NE592N-8

G'A GAIN SELECT

7 G'B GAIN SELECT

2

OUTPUT 1 4

EQUIVALENT CIRCUIT (resistor values

5 OUTPUT 2

nominal only)

r-----~----~------~----~------_.----~--ov+

2.4k

2. 4k

10k

~-----r-----1--+------1------~vv~----4---00UTPUTI

'------+-------'w..-t-----+-__o OUTPUT 2

400

L---~~--~~--~--+_--------~--~__ov-

NESa!.a
ABSOLUTE MAXIMUM RATINGS
(TA = + 25·C unless otherwise specified)

SupplyVoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
. Differential Input Voltage. . . . . . . . . . . . . . . . . . . . . . ..
Common· Mode Input Voltage ....................
Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

Operating Temperature Range ............ O·C to + 70·C
StorageTemperatureRange .......... -65·Cto + 150·C
Power Dissipation ........................... 500mW

± 8V
± 5V

± 6V
10mA

I

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC ELECTRICAL CHARACTERISTICS
TA = + 25·C. Vs = ± 6V. VCM = 0 unless otherwise specified. Recommended operating supply voltages Vs = ± 6.0V

PARAMETER

Differential Voltage Gain
Gain 1 (Note 1)

SYMBOL

RL = 2kll, VOUT = 3Vp·p "
BW

Rise Time
Gain 1 (Note 1)

t,

Propagation Delay
Gain 1 (Note 1)

td

Input Resistance
Gain 1 (Note 1)

RIN

Input Capacitance

CIN

Input Bias Current
Input Noise Voltage
Input Voltage Range

MIN

NE592·8
TYP

MAX

250

400

600

MHz

VOUT = 1Vp·p

10.5

ns

VOUT = 1Vp·p

7.5

ns

4.0

kll

2.0

pF

los

0.4

5.0

IBIAS

9.0

30

en

BW = 1kHz to 10MHz

± 1.0

Il.VIN
VcM ±1V, F<100kHz
VCM ± 1V, F = 5MHz

60

50

Supply Voltage Rejection Ratio

PSRR

Il.Vs=±0.5V

Output Offset Voltage

Voos

RL

Output Common· Mode Voltage

VOCM

RL =

±Vo

Ro

Power Supply Current

1+

RL = 2kll

86
60

00

Note 1: Gain select pins G'Aand G'B connected together.

5-42

V
dB

70

dB
0.75

V

2.4

2.9

3.4

V

3.0

4.0

V

20
RL =

p.A

0.35

=,00

00

p.A

p.Vrms

12

CMRR

Output Resistance

V/V

40

Common· Mode Rejection Ratio

Output Voltage Swing Differential

UNIT

AVOL

Bandwidth
Gain 1 (Note 1)

Input Offset Current

TEST CONDITIONS

18

Il

24

mA

NE592·8
TYPICAL APPLICATIONS
Filter Networks
Basic Configuration (see note)

R

V; (s) FUNCTION

L

~

V;

Vo (s) TRANSFER

FILTER
TYPE

Z NETWORK

LOW PASS

1.4x10' [_1_J
L
s + R/L

C

~j-----<>

~C~

~

[_S_J

HIGH PASS

1.4x10'
R

BAND PASS

1.4X10' [
--L--

BAND REJECT

1.4x10'
R

_.-

s+1/RC

S2
[2

J

s
+ R/L s + 1/LC

J

S2+1/LC
s +1/LC+s/RC

Note: In the networks above, the R value used is assumed to include the internal 2r. of
approximately 32n.

Differentiation with High
Common-Mode Noise Rejection

Disc/Tape Phase Modulated Readback Systems

+5V

a

I
AMPLITUDE:
FREQUENCY:

---~---~
READ HEAD

DIFFERENTIATORIAMPLIFIER

ZERO CROSSING DETECTOR

For frequency F, «112
4

dVi

Vo =1.4x10 C dT

5-43

7r

(32)C

ICL74~HS

High Speed 741
Operational Amplifier
FEATURES
• Pin For Pin and Electrically Equivalent tOj.LA741
• Guaranteed Slew Rate - O.7V/.usMin.

• Large Common-Mode Input Range
• Guaranteed Drift Characteristics

• Low Cost
• Short Circuit Protection

•
•

No Lat<;h Up
Internal Frequency Compensation

ABSOLUTE MAXIMUM RATINGS

GENERAL DESCRIPTION
I

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Power Dissipation (Note 1) . . . . . . . . . . . . . . . . . . 500mW
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . ±30V
Input Volta,ge (Note 2) . . . . . . . . . . . . . . . . . . . . . . . ±15V
Operating Ternperature Range . . . . . . . . . . . . O°C to +70°C
Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Lead Temperature (Soldering at 60 sec.) . . . . . . . . . . 300°C
Output Short-Circuit Duration (Note 3) ... , ..... Indefinite

The 741 HS high slew rate version of the 741 general
purpose operational amplifier is intended for applications
where slew rate performance greater than 0.3V/J,Lsec is
required. Typical applications are oscillators, active filters,
sample and hold and other large signal applications. This
device has a guaranteed minimum slew rate of O. 7V IJ.l.sec
and is identical and equivalent to the standard 741 opera·
tional amplifier. It will fill the application void between the
741 and lOlA type amplifiers (slew rate ~ 0.3V/J.l.sec) and
the more costly high·speed amplifiers (slew rate ~ 30V/J.l.sec).

NOTE 1: The ma)(imum junction temperature of the 741 HS is
150° C, while that of the 741 CHS is 100° C. For operating
at elevated temperatures devices in the TO-5 package must
be derated based on a thermal resistance of 150°C/W,
junction to ambient or 45° CIW, junction to case .. For the
flat package, the derating is based on thermal resistance
of 185° C/W when mounted on a 1/16-inch-thick epo)(y

HIGH-SPEED 141 OPERATIONAL AMPLIFIER

GIl

~lass board with ten O.03~inch-wide. 2..ounce copper con-

E

u

:;
Ln

ductors. The thermal resistance of th'e dual-in-line package
is 100° CIW, junction to ambient.
NOTE 2: For supply voltages less than ± 15V, the absolute ma)(imum input voltage is equal to the supply voltage.
T A = 25° C unless otherwise specified.
.
NOTE 3: Short circuit may be to ground or either supply.

741H:;

741 STD
5J.LS/cm

---

Stresses above those listed under Absolute Maxjmum
Ratings may cause permanent damage to the device.
These are stress ratjngs only, and functional operation
of the device at these or any other conditions above
those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

ORDERING INFORMATION
8 Pin
Plastic DIP

14 Pin
CERDIP

TO-99
Can

ICL741CHSPA

ICL741MHSJD

ICL741CHSTY
ICL741MHSTY

PIN CONFIGURATIONS
NOTE: AVAILABLE
IN COMMERCIAL
TEMP RANGE ONLY

"

NOTE: AVAILABLE
IN MILITARY
TEMP RANGE ONLY

NC

NC

y+

INPUT

, BALANCE

INVERTING
INPUT

INPUT

OUTPUT

V-

BALANCE

V(outline dwg PAl

(outline dwg JD)

q-44

(outline dwg TY)

ICL741t1S
ELECTRICAL CHARACTERISTICS
CONDITIONS

PARAMETER

MIN

= 2S'C, RS ~ 50kn
TA = 2S'C
TA = 2S'C
T A = 2S'C
TA = 2S'C, Vs = ,15V
TA = 2S'C, Vs = ,lSV
VOUT = ±10V, RL ~ 2kn

Input Offset Voltage

TA

Input Offset Current
Input Bias Current
Input Resistance
SUpply Cur,"nt
Large Signal Voltage Gain
Input Offset Voltage

RS~50kn

Slew Rate

VOUT = ±10V, RL ~ 2kn
CL = 50pF

Input Offset Current

TA

0.3

741MHS
TYP

MAX

6.0

1.0

S.O

mV

20

200

20

200

nA

200

SOO

200

500

741CHS
TYP

MAX

2

25

Large Signal Voltage Gain

Vs = ±15V, VOUT
RL ~ 2kn

= ±10V

Output Voltage Swing

VS=±15V,

RL
RL

= 10kn
= 2kn

0.7

±12
±10

RS~

Supply Voltage Rejection Ratio

RS

~

mV

300

500

nA

0.8

1.5

!J.A
VlmV

±12
±10

±14
±13

V
V
V

±12

±12

mA

V/!J.sec

1.0

25
±14
±13

n,l\

V/mV

160
6

0.7

1.0

15

= ±15V

Vs

2.8

7.5

= 25°C

Input Voltage Range

50

UNITS

Mn

1.0
1.7

2.8

160

Input Bias Current

Common Mode Rejection Ratio

0.3

2.0
1.7

MIN

50kn

70

90

70

90

dB

50kn

77

96

77

96

dB

DEFINITION OF TERMS
SLEW RA TE: A measure of the large signal capability of
amplifier output to follow the amplifier input. Slew
Rate = 211" BW Large Signal VO.Peak·
SUPPL Y CURRENT: The current required from the power
supply to operate the amplifier with .no load and the output
at zero.

INPUT OFFSET VOL TAGE: That voltage which must be
applied between the input terminals through two equal
resistances to obtain zero output voltage.
INPUT OFFSET CURRENT: The diffl!rence in the currents
into the two input terminals when the output is at zero.
INPUT VOL TAGE RANGE: The range of voltages on the
input terminals for which the offset specifications apply.
The average of the two input

OUTPUT VOL TAGE SWING: The peak output voltage
swing, referred to zero, that can be obtained without dipping.

COMMON MODE REJECTION RA TlO: The ratio of the
input voltage range to the peak·to·peak change in input
offset voltage over this range.

LARGE-SIGNAL VOLTAGE GAIN: The ratio of the output voltag~ swing to the change in input voltage required to
drive the output from zero to this voltage.

INPUT RESISTANCE: The ratio of the change in input
voltage to the change in input current on either input with
the other grounded.

POWER SUPPL Y REJECTION: The ratio of the change in
input offset voltage to the change in power supply voltages
producing it.

INPUT BIAS CURRENT:
currents.

TEST CIRCUITS
FAST VOLTAGE
FOLLOWER

TRANSIENT RESPONSE
TEST CIRCUIT

o

VOUT

Power Bandwidth: 1.5kHz
Slew Rate: lVI"s

5·45

.n~UlL

ICL741LN, ICL741CLN, ICL101ALN
ICL301 ALN, ICL 1 08LN, ICL308LN
Low Noise
Operational Amplifiers

FEATURES

GENERAL DESCRIPTION

• Guaranteed Noise Specifications

These low noise amplifiers are suitable for all applications
where low level signals are encountered. The three impor'
tant noise parameters, input referred voltage noise, input
referred current noise, and popcorn noise, are all 100%
screened and guaranteed .

• Complete Electrical Specifications

. PIN CONFIGURATIONS
7411741C

101A/301A

108/308
FR~aUfNC'1'

COMP

II

(outline dwg TV)
NOTE: PIN 4 CONNECTED TO CASE.

(outline dwg TV)
NOTE: PIN 4 CONNECTED TO CASE.

741

lOlA

741

COMP~~i:i,~~

:I

INVERllNG INPUT

3

NON-INVERTING"
INPUT

NON INVERTING
INPUT

, ,

(outline dwg FB·l)

(outline dwg TV)
NOTE: PIN 4 CONNECTED TO CASE.

(outline dwg FB)

(outline dwg JD)

301A

741C

lOlA

(outline dwg PAl

(outline dwg JD)

5·46

(outline dwg PAl

CL 741 LN, ICL 741 CLN, ICL 101 ALN, ICL301 ALN, ICL 1 08LN, ICL308LN
GUARANTEED NOISE SPECIFICATIONS (T A ~ 25°C)

Input Referred Voltage

NOis~

@ 10 Hz (Max)

Input Referred Current

741

741C

lOlA

301A

108

308

UNITS

50

50

50

50

70

70

nV/y'"H;

0.4

Noise @ 10 Hz (Max)
Popcorn Noise Transition
Amplitude tor Rs
lOOk (Max)

0.4

25

0.7

25

0.7

25

0.2

25

25

0.2

pM/Hz

25

)J.V

0

For other electrical specifications see standard data sheets.
741 INPUT REFERRED
VOL TAGE NOISE

101A/301A INPUT REFERRED
VOLTAGE NOISE
100

100

~>

"

-.S.

.

~

MAX

w

<:J

108/308 INPUT REFERRED
VOLTAGE NOISE

"

-l

..

100

w

TYP

t::;

-'

0

0

w

Vl

!!1

0

0

z

..

~

10

t::;

TYP
10

>

w

Z

MAX

~

0

>

>

"-

l

TYP

<:J

10

l-

~

MAX

I'-...

w

V>

0
Z

1
100

10

10k

lk

lOOk

10

~
0:
0:

w
a:
a:
::>
u
w

::>

u

w

TYP

Vl

0.1

a:
a:

I

om

TYP

u

-- -

100

lk

10k

100

FREQUENCY (Hzl

Vl

lk

10k

lOOk

741LN
741C·LN
741LN
741C·LN

TEMPERATURE
RANGE

ORDER
NUMBER

MIL
COM
MIL

TO·99
T099
14 lead DIP

-55"C to t125"C
O°C to + 70 0 e
_55°C to + 125"C

ICL741LNTY
ICL741 CLNTY
ICL741LNJD

FLAT PACK

-5S')C to ~ 125"C

101ALN

COM
MIL
MIL

T099

-55"C to t12S"C

301ALN
101ALN
301ALN

COM
MIL
COM

TO 99
14 Lead DIP
8 Lead DIP

-55"C

t12S'C
lOoe

ICL301ALNTY
ICL101AlNJD
ICL301AlNPA

10IALN
108·LN
308·LN

MIL
MIL
COM

FLAT PACK
TO·99
TO·99

-55"C to f-125°C
-55"C to +125"C
O°C to t 70'-'C

ICll 01 AlNFB
ICll08LNTY
ICL308LNTY

8 Lead DIP

5-47

O°C to

O"C to
to

o"e to

t

t

"i--.

100

lk

10k

FREQUENCY (Hz)

PACKAGE

741·LN

"MAX

'k
10

ORDERING INFORMATION

TYPE

TYP

Z

FREQUENCY (Hz)

PART
NUMBER

~.

w

0.01
10

lOOk

r\.

0

0.01
10

0.1

::>

Z

Z

a;

_.

I----

Vl

I-

"'MAX

0

0

lOOk

~

.!

",

IZ

MAX 1===

10k

10B/308 INPUT REFERRED
CURRENT NOISE

"

~

1''',

Ik

1.0

~«

"-

0.1

100

F REOUENCY 1Hz)

1.0

1.0

a;

10

101A/301A INPUT REFERRED
CURRENT NOISE

741 INPUT REFERRED
CURRENT NOISE

I-

lOOk

10k

FREQUENCY (Hz)

FREQUENCY (Hzl

-1

lk

100

70

0

e

lO°C

t

ICL741CLNPA
ICL741LNFB
ICL101ALNTY

lOOk

IID~D[L
ICL741LN, ICL741CLN,ICL101ALN, ICL301ALN,ICL108LN, ICL308LN
NOISE IN OPERATIONAL AMPLIFIERS
VOLTAGE NOISE: The noise due to the equivalent input
voltage generator is measured using the 'eircu it shown in
Figure 1. It is expressed in nV/y'RZ.
CURRENT NOISE: The noise due to the equivalent input
current generator is measured using the circuit in Figure 2.
It is ex pressed in pA/$z. Popcorn noise cannot be effectively screened using this test due to its erratic nature and
very low frequency.

FIGURE ,.

POPCORN NOISE: Popcorn noise, sometimes referred to
as burst noise, is a low frequency noise phenomenon in
which the output 'of the amplifier appears to jump erratically between two or more stable states. It is most notice-able when operating at high source impedances and is
expressed as a· trans,ition amplit~de, in /lV, for a given
source resistance. The test circuit of Figure 3 is used.

The noise of an amplifier may be expressed in terms of an
input referred voltage generator (en) and an input referred
current generator (in), see Figure 4. The total noise of an
amplifier in a typical application contains contributions
from both these generators, together with a contribution
from the source resistance. The total mean square noise
for a bandwidth of 1 Hz is given by:

FIGURE 2.

o
F IQURE 3.

II

I'll
,,> II!.
liff7lf2

(1 )

Since both en and in are frequency dependent, the total
mean square noise for a given bandwidth llf= f2 - f, is
given by:
FIGURE 4.

(2)

With most amplifiers, the voltage noise term dominates for
low source impedances. The current noise term is dominant
at higher source impedances.
To specify operational amplifier noise performance one of
two methods is used. One is to specify the total input
referred noise for a given bandwidth and source impedance. This is defined as eT from equation 1 above. The test
circuit in Figure 5 is used. The typical broadband noise of
the 741 and lOlA type amplifier is shown in Figure 5.
The second method is to guarantee specific. valyes of en
and in (in equation 2) at various frequencies. A Noise
Analyzer is used for this measurement (Figure 3). The
values of en and in (for llf = 1 Hz) are measured at 10 Hz,
100 Hz, 1 kHz, 10 kHz and 100 kHz, The recorded values
may be plotted graphically, as shown on page 1. The noise
information obtained from these measurements is considerably more general than that obtained from the first method,
since the noise for any source impedance and bandwidth.
may be calculated from equation 2. (Graphical integration
can determine the area under each curve.)

FIGURE 5.

741/101A BROADBAND
NOISE FOR VARIOUS
BANDWIDTHS

~ 100

I IIII

~

ill
6
z

~

10

=

Ir

i

t:::'"

H)--l00 kHz

~

10-10 kHz

10-1 kHz

~

Ii'
.:
-'
0{

~

0.1
100

lk

10k

SOURCE RESISTANCE

FIGURE 6.

lOOk

n

J.l.A777
Precision Operational Amplifier

FEATURES

GENERAL DESCRIPTION

• Low offset voltage 'and offset current

The /LA77? is a monolithic Precision Operational
Amplifier. It is an excellent choice when performance
versus cost trade-offs are possible between super beta
or FET input operational amplifiers and low cost general purpose operational amplifiers. Low offset and
bias currents improve system accuracy when used in
applications such as long term integrators, sample and
hold circuits and high source impedance summing
amplifiers. Even though the input bias current is extremely low, the /LA77? maintains full ±30V differential
voltage range. High common mode input voltage
range, latch-up protection, short circuit protection and
simple frequency compensation make the device versatile and easily used.

• Low offset voltage and current drift
• Low input bias current
• Low input noise voltage
• Large common mode and differential voltage ranges

ABSOLUTE MAXIMUM RATINGS
Supply Voltage " " " " " , ......... '..... ± 22V
Internal Power Dissipation (Note 1)
Metal Can ........................... 500mW
Differential Input Voltage ...... , ....... , . .. ± 30V
Input Voltage (Note 2) .. . . . . . . . . . . . . . . . . . .. ± 15V
Storage Temperature Range. . . . .. - 65°C to + 150°C
OperatingTemperature Range(HC) , . . . . .. O°C to ?O°C
(HM) .. - 55°C to + 125°C
Lead Temperature (Soldering, 10s) ........... 300°C
....................................... 260°C
Output Short Circuit Duration (Note 3) ..... Indefinite

PIN CONFIGURATION
8-LEAD METAL CAN
(TOP VIEW)

Note 1: Rating applies to ambient temperatures up to lO°C. Above
lOoC ambient derate linearly at 6.3mW/oC for Metal Can,
8.3mWrC for the DIP, and 5.6mW/oC for the Mini DIP.
Note 2. For supply voltages less than ±15V, the absolute maximum
input voltage is equal to the supply voltage.
Note 3. Short Circuit may be to ground or either supply. Rating
applies to +125°C case temperature or +l5°C ambient
temperature for ISET ,; 30",A.

v(outline dwg TV)

ORDERING INFORMATION

5·49

__
_

p,A7"
ELECTRICAL CHARACTERI$TICSFOR p.A777 . (~s =±15V, TA =25°C, Cc =30pF unless otherwise specified)

PARAMETERS

CONDITIONS

MIN

TYP

Rs ~ 50kO
Input Offset Voltage
0.7
Input Offset Current
0.7
,
Input Bias .Current
25
Input Resistance
1.0
2.0
Input Capacitance
3.0
Offset Voltage Adjustment Range
±25
Large Signal Voltage Gain
RL :::: 2kO, VOUT - ±10V
25,000
250,000
Output Resistance
100
Output Short Circuit Current
±25
Supply Current
1.9
Power Consumption
60
Transient Response
Rise Time VIN = 20mV,Cc =30pF
0.3
(Voltage Follower,
RL = 2kO, CL ~ 100pF
Gain of 1)
Overshoot
5.0
Slew Rate
RL:::: 2kO
0.5
(Voltage Follower, Gain of 1)
Transient Response
Rise Time VIN = 20m V, Cc =3.5pF
0.3
(Voltage Follower,
RL = 2kO, CL ~ 100pF
Overshoot
Gain of 10)
5.0
Slew Rate
RL ~ 2kO, Cc =3.5pF
5.5
(Voltage Follower, Gain of 10)
The following specifications apply over operating temperature range.
Input Offset Voltage
Rs ~ 50kO
0.8
Average Input Offset Voltage Drift Rs ~ 50kO
4.0
I n put Offset Current
25°C ~ TA ~ +70°C
0.01
Average Input Offset Current Drift
O°C ~ TA ~ +25°C
0.02
Input Bias Current
Input Voltage Range
±12
±13
Common Mode Rejection Ratio As ~ 50kO
70
95
Supply Voltage Rejection Ratio
Rs ~ 50kO
15
Large Signal Voltage Gain
RL ;::: 2kO, VOUT - ±10V
15,000
RL? 10kO
+12
+14
Output Voltage Swing
RL? 2kO
+10
+13
Power Consumption
60

MAX

UNITS

5.0
20.0
100

mV
nA
nA
MO
pF
mV
VIV
fl
mA
mA
mW

2.8
85

p's
%
Vlp.S
p's
%
V/p.s
5.0
30

40
10.3
0.6
200

V

150

COMPo OFFSET NULL

COMPo

r-------~--~----~--4_~-.------------~v+

5-50

dB
p.VIV
VIV
V
V

100

EQUIVALENT CIRCUIT
INVERTING INPUT

mV
p.VloC
nA
nAloC
nAloC
nA

mW

J.LA777
TYPICAL PERFORMANCE CURVES

OPEN LOOP VOLTAGE
GAIN AS A FUNCTION
OF SUPPLY VOLTAGE
120

>

TA '" 2SOC

~ 1'0

"z

"

,."o

I

1

10

15

20

100

--I--

~+-:=--=-r=

2

'"

f-

"r---r--

1
20

20

80

TA '" 25°C

I

~ 1.2
~ 1.0

"w 0.8

"
"
,.Ii'

r-- ,-f-

E 70
I

-

--1

00.4
f-

"~ 0.2
o
5

10

--t--

15

20

SUPPLY VOLTAGE - ±V

Vs '" .±:15V

>

=00

I

""

i'-r--

2

20

28
Vs
TA

~

24

::"
"'"o

20

60

TEMPERATURE _

OUTPUT SHORT-CIRCUIT
CURRENT AS A FUNCTION
OF AMBIENT
TEMPERATURE

100

°c

.

~

-~

140

80

+15V
2S"C

/

-t--+-1/

~ 12

'"
~

E
I

f-

30

1"-

ffi

'"
""'"
:;
"'"
U

25

8
0.1

0.2

0.5

1.0

2.0

f-

f-

a:

I

'" "-

20

15
10

-60

1

60
100
-20
20
TI:MPERATURE _ DC

10

INPUT NOISE VOLTAGE
AND CURRENT AS A
FUNCTION OF FREQUENCY

0

ili

5.0

LOAD RESISTANCE - kn

Vs = ±15V

:"

j---

16

35

"

100

°c

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
LOAD RESISTANCE

f-

i'--

"0 50
"
~'" 40

60

40

TEMPERATURE _

j

-20

I

0, 1

20

'-

30
-60

1- -- -- -

°c

t--- RL

60

iil

I

~ 0.6

++-

"-

0

t;;

f-

..-f-"

"- 0, 2r- -r-

POWER CONSUMPTION AS
A FUNCTION OF AMBIENT
TEMPERATURE

1,6

~ 1.4

r--r-- f-

2.0

40

60
TEMPERATURE _

INPUT OFFSET, CURRENT
AS A FUNCTION OF
SUPPLY VOLTAGE

I

m1.0
'"~ 0.5

;;;

10
15
SUPPLY VOLTAGE - tV

10

w 5.0

""
~

10

5

->-lSV

Vs

g

BIAS

-f-

""'"

5

30

VS - "5~:-I=-:t-t-- -

~

1

20
SUPPLY VOLTAGE - tV

INPUT RESISTANCE AS
A FUNCTION OF
AMBIENT TEMPERATURE

500 F.=~C;=FFFFFF'I

~

I
I

ill

"

INPUT CURRENT AS
A FUNCTION OF
AMBIENT TEMPERATURE

~

I

Vf<"!

/'

"o~

SUPPLY VOLTAGE - 'V

'"

~

":/ 12 1--+-t-

I

0
5

J--t1

E

I
w 14

7

../f

POWER CONSUMPTION AS
A FUNCTION OF SUPPLY
VOLTAGE
100

:;: 16 r---r-.----;

---

-;7

I

~

SUPPLY VOLTAGE - .rV

3: 50

/

1

"o

------

5

t J---

f-

~ 100 , - -,

~

~<

32

~

f..---

I

40

I

RL = 2k!1

I,

INPUT COMMON MODE
VOLTAGE RANGE AS A
FUNCTION OF SUPPLY
VOLTAGE

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
SUPPLY VOLTAGE

140

FREOUENCY - Hz

5-51

II

J.LA777
TYPICAL PERFORMANCE CURVES

OPEN LOOP .vOLTAGE GAIN
AS A FUNCTION OF
FREQUENCY

OPEN LOOP PHASE
RESPONSE AS A
FUNCTION OF FREQUENCY
o~~,--,-,-~~~,

'20
Vs '" ±1SV

e-.:+---

'00

I··,···.:

!g 80
z
;;' 60

"" .'
""""

Rl '" 2kS1

w

q

I"",··". \

>

.....

-20

iE

-'50f-+-+---+-+---+-i-'\\--j

-'80f-+--1-+--+-+--+--I

\

102 103 104 105 106 107

10

-210,'-_,LO-'O-'-o,C-,L
03;-,04"-;--'' '05;-,-'-oO.,---J,o"

FREQUENCY· Hz

~

VS =i15V
TA ::25°C
~l ::: 100kQ

32

I-

~

o
~

\Cc- 3pF

"
~

:1

Ii

16

II

'\-

~

II

'il

24

:::>

CC =.30pF

8

ii

I II
I II

0

"i- LL
'Ok

'k

lOOk

'OM

'M

FREQUENCY - Hz

COMPENSATION
CAPACITANCE AS A
FUNCTION OF CLOSED
LOOP .vOLTAGE GAIN

'20

., '00 r---"f""'f"-<+--~

'00

c--+-c--+-t-

!g 80

80

z

z

;;' 60

;;' 60

" 40
""~
0 20

w

w

20

>

>

10

100 lk 10k lOOk 1M 10M
FREQUENCY· Hz

CLOSED LOOP VOLTAGE GAIN - dB

COMMON MODE REJECTION
RATIO AS A FUNCTION OF
FREQUENCY

INPUT OFFSET .vOLTAGE
DRIFT AS A FUNCTION
OF TIME

FREQUENCY· Hz

INPUT RESISTANCE,
OUTPUT RESISTANCE,
AND INPUT CAPACITANCE
AS A FUNCTION OF FREQUENCY
100M
!

'OM

~

lk
100

a:

,
,

,

-

10k

ffi

,

A'N

TC 'N

'is" lOOk
l;;

i

: I

'M

U)

.~

"~

40

FREQUENCY RESPONSE
FOR .vARIOUS
CLOSED·LOOP GAINS

'20r--'-r--r-r--r-'-~

"
""...
<5

~

FREQUENCY· Hz

OPEN LOOP .vOLTAGE GAIN
AS A FUNCTION OF
FREQUENCY FOR .vARIOUS
GAIN/COMPENSATION OPTIONS

"

±15~

~

Cc =30pF

~ -120

r··"",. ~

0

Vs =

I :: AL~;~?i~"'''''''i-'''''-'''-+---1

Rl =12knf--------Cc "',3pF

...,...~. ~

" 40 -Cc '30pF
""~
20

= 2k.Q

~c '3pF ~ ~~: ~~ C

-30"\1

son

~

~~L

'\

TA :: +25"C
AS'"

OUTPUT .vOLTAGE SWING
AS A FUNCTION OF
FREQUENCY

U
. :

100

90

;:

"'-

a: 80

"z
0

70
50

0
0

30

I

Vs
TA

, -if! ii'

'0

=

±15V
25°C

'M

lk
10k
lOOk
FREQUENCY· Hz

"z
""
0
0

u

>

7100

Vs "" ±15V

TA = 2SQ C
Cc :: 30pF

w

~
o
I-

ii:

20
'0
lk

_

Vs • 1'20V

-----:- TA "" 125°C

,.

10k lOOk 1M 10M

40

~
~
w

:'l"

5

20

TRANSIENT RESPONSE
TEST CIRCUIT

.

TREND LlNEt-----

r

I

/

,
.

I

0

200

0

400

600

800

1000

TIME-HAS.

FREOUENCY • Hz

.vOLTAGE FOLLOWER
TRANSIENT RESPONSE
(GAIN OF 1)

_+_ '

--

~ 60
o

'\
100

---

I-

'\

10

80

>

'\

;: 60

~

I

a: 40
w

IAO~T'

'00

~
0

.vOLTAGE FOLLOWER
LARGE SIGNAL
PULSE RESPONSE

28
24

>

20

~ 16

90%

...
...~ 12
5 8

I

V,N

I

I--

i---

Vs = ±15V

~2,%1-- r--6~: ~~~;
RISE1TtME

.5

r-~~: ~~~PF

1.0 1.5
TIME -,uS

2.0

-'0 '--1-'.--'---1- .!--'---,-'-lC-L.J
o

2.5

10 20 30 40 50 60 70 80 90
TIME-,u.s

5·52

IlA777
TYPICAL PERFORMANCE CURVES
STABILIZATION TIME OF INPUT OFF-SET
VOLTAGE FROM POWER TURN-ON

THERMAL RESPONSE OF INPUT OFFSET VOLTAGE
TO STEP CHANGE OF CASE TEMPERATURE
2.,5 C:12S.C

TA '" 25'C

0

Vs '"

m

15V

O~

>~ ~ -10

0

:.--~

z
TA '" 25 CHH-++++-H
~ 5.0 HHlf7l--I--HH-I-++-l-l
Vs '" 15V

Rl'" "'"

~

>~2.5

~

o

-2.5

\

~-t+-I-~-+-I--I-++~

'-'-"--'--'---'--'-L..JLJ.~..L-'

o

1.0

2.0

3.0

4.0

5.0

6.0

RESPONSE TIME· ps

VOLTAGE OFFSET
NULL CIRCUIT

GAIN TEST CIRCUIT

50n VIN
DC INPUT
L'_10V FDA Vs

'=

t

15V)

TOLERANCE OF ALL
UNMARKED RESISTORS
IS 1%

SUGGESTED

ALTERNATE

5-53

tJ.A777
TYPICAL APPLICATIONS
BIAS COMPENSATED LONG TIME INTEGRATOR

SAMPLE AND HOLD

V+

30pF
*ADJUST R3 FOR MINIMUM INTEGRATOR DRIFT

CAPACITANCE MULTIPLIER

AMPLIFIER FOR CAPA

"ANCE TRANSDUCERS

LOW'FREOUENCY CUTOFF Rl X C1

BILATERAL CURRENT SOURCE

HIGH SLEW RATE POWER AMPLIFIER

r---~-<>+15V

INPUT

INPUT

L---+--<>-15V

±100V COMMON MODE RANGE
INSTRUMENTATION AMPLIFIER

INSTRUMENTATION AMPLIFIER WITH
HIGH COMMON MODE REJECTION

~ == ~ for best CMRR
R7

R4

R3"" R4

Rl ""

13 6 '"

10R 3

R,

Gain =

As

5·54

LH21 08/2308
Dual Super Beta
OpAmp
FEATURES

GENERAL DESCRIPTION

• Low offset current - 50 pA
• Low offset voltage - 0.7 mY
• Low offset voltage - LH2108A: 0.3 mY
LH2108:
0.7 mY
• Wide input voltage range - ±15Y
• Wide operating supply range - ±3Y to ±20Y

The LH2108A1LH2308A and LH2108/LH2308 series of dual
operational amplifiers consist of two LM108A or LM108 type
op amps in a single hermetic package. Featuring all the same
performance characteristics of the single device, these duals
also offer closer thermal tracking. lower weight, and reduced
insertion cost.
The LH21 08A/LH21 08 is specified for operation over the
-55°C to +125°C military temperature range, and the
LH2308A/LH2308 is specified for operation from 0° C to
+70°C.
PIN. CONFIGURATION

CONNECTION DIAGRAM
V+

'4
2

INV
INPUT

BALANCE
OUTPUT
COMPENSATION

'6

OUTPUT
OUTCOMP...

3

NON-INV
INPUT

BAL/COMPENSATlON
BALICOMP A

6

IN~~~ 0-----1

V-

~---'-<:l

'0

-IN..,

+IN. .

BALANCE
OUTPUT

,---":'::"0 COMPENSATION

"">--=-0

V-

OUTPUT

SAL,

,---...:.'.:...'0 BAL/COMPENSATION
V+

'--_ _-.-.:9:....0

OUTs

(outline dwg DEI

ORDER NUMBER LH2108AD,
LH2408AD, LH2108D,
ORLH2408D

AUXILIARY CIRCUITS
ALTERNATE*
FREQUENCY COMPENSATION

STANDARD
COMPENSATION CIRCUIT

FEEDFORWARD
COMPENSATION

-vIN-'lN_ _--~v-..f'v_--

VOUT

VOUT

VOUT
+VIN'''''''''-A..''--..J

Cf>~
-- R,+R2
Co = 30 pF
Cf

*Improves rejec!ion
df power supply
noise by a factor

C,
'50 pF

of ten.

5·55

L",21 08/2308
ABSOLUTE MAXIMUM RATINGS
Supply Voltage· ........................................................... ±20V
Power Dissipation (Note 1) ............................................ 500 mW
Differential Input Current (Note 2) ...................................... ±10mA
Input Voltage (Note 3) ..............................................•... :. ±15V
Output Short Circuit Duration ............................•......... Continuous
Operating Temperature Range
LH2108A/LH2108 ......................................... -55°C to +125°C
LH2308A/LH2408 ............................................ 0° C to +70° C
Storage Temperature Range ................................... -65°C to +150°C
Lead Temperature (Soldering, 10 sec) .................................... 300°C

ELECTRICAL CHARACTERISTICS Each side (Note 4)
LIMITS
PARAMETER
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Supply Current
Large Signal Voltage Gain
Input Offset Voltage
Average Temperature Coefficient
of Input Offset Voltage
Input Offset Current
Average Temperature Coefficient
of Input Offset Current
Input Bias Current
Supply Current
Large Signal Voltage Gain
Output Voltage Swing
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
PARAMETER
Input Offset Voltage
Input Offset Current
Input Bias Current
Input Resistance
Supply Current
Large Signal Voltage Gain
Input Offset Voltage
Average Temperature Coefficient
of Input Offset Voltage
Input Offset Current
Average Temperature Coefficient
of Input Offset Current
Input Bias Current
Supply Current
Large Signal Voltage Gain
Output Voltage Swing
Input Voltage Range
Common Mode Rejection Ratio
Supply Volt<;lge Rejection Ratio

CONDITIONS
TA = 25°C
TA- 25°C
TA-25°C
TA - 25°C
TA - 25°C
TA - 25°C Vs - ±15V
VOUT = ±10V, RL ~ 10 kO

TA Vs RL>
Vs Vs -

+125°C
±15V, VOUT - ±10V
10 kO
±15V; RL - 10 kO
±15V

CONDITIONS
TA=25°C
TA - 25°C
TA - 25°C
TA - 25°C
TA - 25°C
TA - 25°C Vs - ±15V
VOUT = ±10V, RL ~ 10 kO

TA Vs RL>
Vs Vs -

+125°C
±15V, VOUT - ±10V
10 kO
±15V, RL - 10 kO
±15V

LH2108
2.0
0.2
2.0
30
0.6
50

LH2308
7.5
1.0
1.0
10
0.8
25

MO Min
mA Max
V/mV Min

3.0
15

10
30

mVMax
I'NloC Max

0.4
2.5

1.5
10

nA Max
pA/oC Max

3.0
0.4
25

10

-

nA Max
mA Max
V/mV Min

±13
±13.5
85
80

±13
±14
80
80

15

LIMITS
LH2108A
LH2308A
0.5
0.5
0.2
1.0
2.0
7.0
10
30
0.6
0.8
80
80

UNITS
mVMax
nAMax

V Min
dB Min

UNITS
mV Max
nA Max
MO Min
mA Max
V/mV Min

1.0
5

0.73
5

mV Max
/lV/oC Max

0.4
2.5

1.5
10

nA Max
pA/oC Max

3.0
0.4
40

10
60

nA Max
mA Max
V/mV Min

±13
±13.5
96
96

±13
±14
96
96

-

V Min
dB Min

Note 1: The maximum junction temperature of the LH210S1A is 150° C, and that ofthe LH230S/A isS5° C. The thermal resistance olthe packages
is 100° CIW, junction to ambient.
Note 2: The inputs are shunted with back-to-back diodes for overvoltage protection. Therefore, excessive current will flow if a differential input
voltage in excess of IV is applied between the inputs unless some limiting rElSistanceiis used.
Note 3: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
Note 4: These specifications apply for ±5V $ Vs $ ±20V and -55° CoOTA $125° C, unless otherwise specified, and the LH230SA/LH2308for ±5V $
Vs $ 15Vand O°C $ TA $ 70°C,

5-56

IH5110 - IH5115
General Purpose Sample & Hold

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•
•

Each of the 5110 family is a complete Sample and Hold
circuit, (except for sampling capacitor) including input buffer
amplifier, output buffer amplifier and CMOS logic switching.
The devices are designed to operate from ±15V and +5V
supplies. The input logic is designed to "Sample" and "Hold"
from standard TTL logic levels.

Low cost
Military and industrial temperature ranges
±10V input voltage range
O.SmV/sec drift typical @ Cs = 0.01!1F
TTL, DTL and CMOS compatible
Short circuit protected
Input offset voltage adjustable to < 100!1V using a
20k potentiometer
• 0.1% guaranteed sample accuracy with 10V signals
and Cs = 0.01!1F
• Sample to hold offset is SmV max

The design is such that the input and output buffering is
performed by only one operational amplifier, by switching
the sampling capacitor from the output back to input.
Switches 0" 02, and 03 (see Fig. 1) accomplish this
switching. In the sampling mode 0, and 03 are shorted and
02 is open; thus the op. amp. charges up the sampling
capacitor. In the hold mode 0, and 03 are open and 02 is
shorted; thus the sampling cap. is switched back to the noninverting input of the op. amp.
This structure provides a very accurate d.c. gain of 1 with
very fast settling times (i.e. 5I-'s); additionally the design has
internal feedback to cancel charge injection effects (sample
to hold offsets). 0, and 02 are driven 180 degrees out of
phase to accomplish this charge nulling.

SCHEMATIC DIAGRAM

S&H
OUTPUT

16

4

AOD
EXTERNALLY

1

CSAMPLE

1000

r 0 01 f.'F

FIGURE 1

ORDERING INFORMATION
IH5110

M

PIN CONFIGURATION

JE

~

Package
JE=16 pin CERDIP
DE= 16 pin ceramic DIP (special order only)

Temperature Range
M=Military (-55°C to +125°C)
I =Industrial (--20°C to +85"'C)

(outline dwg DE, JE)
Device Chip Type

5-57

(I
I

.D~DIL

IH5110 -IH5115
ABSO.LUTE MAXIMUM RATINGS

Supply Voltages ...................................•....................... ±16V
Power Dissipation ... , ...•............................................... 500mW
Operating Temperature ........................................... -25° C to 85° C
,
-55°C to 125°C
Storage Temperature Range.................................... -65°Cto 150°C
Lead Temperature (Soldering, 10 sec) ..................................... 300·C

ELECTRICAL CHARACTERISTICS
SYMBOL

(Pin 7

= 5V,

Pin 8

= GND,

IH5111, 5113, 5115

UNITS

120

200

ns

35
6
6

25
4
4

35
6
6

,.,s

4
4

2.5
5
10

0.3
0.5
2.0

2.5
5
10

mY/sec

See fig. 2

0.3
0.5
2.0

Charge Injection or Sample to Hold Offsets
Cs = 0.1,.,F
Cs = O.Q1,.,F
Cs = 0.001,.,F
See Note 1 & fig. 3

<1
<1
12

5
5
25

<1
<1
12

5
5
25

mV~-p

Switching Transients'or Spikes
(Duration Less than 2,.,5)
Cs = 0.1,.,F
Cs = 0.01,.,F
Cs = 0.001,.,F
See fig. 3

0.1
0.1
0.2

0.5
0.5
0.5

0.1
0.1
0.2

0.5
0.5
0.5

Vp

5

mVp- p

Aperature Time
Acquisition Time for Max Analog Voltage Step
Cs = 0.1,.,F (0.1% AccurJ
Cs = 0.01,.,F (0.1% Accur.)
Cs = 0.001,.,F (0.1% AccurJ
.See fig. 4
Drtft Rate
Cs = 0.1,.,F
Cs = O.Q1,.,F
Cs = 0.001,.,F

Vcouple

A.C. Feedthrough Coupled to Output

Vollset

D.C. Offset When in
Sample Mode (Trimmable
to Om V With Ext. 20kO
Potentiometer
See fig. 2

TYP

MAX

120
25

40
40
10
5
5
100

1±1SV

Plus or Minus 15V Supply
Quiescent Current

3.4
0.3

Isv

5V Supply Quiescent Current
D.C. Input Voltage Range

VA.C. range

A.C. Input Voltage Range
See Note 2& fig. 5

mV

10

Input Impedance in Hold or Sample
Mode (f:5 10Hz)

Vanalog

MIN

5
5110
5111
5112
5113
5114
5115

Rin

..

Note 3

200

Close

Istrobe

= 15V, TA = 25°C)

MAX

tacq.

Vswitch

11

TYP

MIN

Vinject

= -15V, Pin

IH5110, 5112, 5114

CHARACTERI.STIC

Vdrift

Pin 9

6

3.4

10

0.3

±7.5

6
1(1

0.1

10

mA
A

±10
V

20

15

TTL Logic Strobe Input Current in
Either Hold or Sample Mode

Megll

100

0.1

10

,.,A

NOTES: 1. Offset voltage of op. amp. must be adjusted to OmV (using 20kfl potentiometer) before charge injection is measured.
2. The A.C. input voltage range differs from the D.C. input voltage range. All versions will handle any analog input within the range of
plus 10V to minus 10V; however the IH5110, 5112, 5114 has the added restriction that the peak to peak swing should be less than
15Vp- p i.e. ±7.5 Vae.
3. All of the electrical characteristics specs, are guaranteed with Cs = O.01I'F in series with 100fl as per Fig. 2, Cs = O.1I'F &
Cs = O.001I-'F are for design aid only.
4. If supplies are reduced to ± 12VDC, analog signal range will be reduced to ± 7Vp·p.

5·58

IH5110 -

IH5115

APPLICATIONS INFORMATION
I. Typical Connection Diagram

ANALOG
INPUT

N.C.

,.

S & H OUTPUT

N.C.

15

N.C.

>-====-=-----1
·NOTE 2
O.01I1F

10011

~""""'VV\r-l
t-3V

•V

-=-

--I'"'"1-

1.

IH5110
THRU
IH5115

20k

N.C .

12

'5V

,.

11

TTL LOGIC STROBE

_

13

15V
OFFSET
POTENTIOMETER

-r15V
N.C.

15V

NOTES: 1. To trim output offset to OmV. set strobe input to sample mode 13VI. set analog input to GND. adjust potentiometer until S & H output
IS OmV.
2. Use a low diele( .
.hsorption capacitor such as polystyrene.

SAMPLE MODE occurs when logic input is greater than 2.4V.
HOLD MODE occurs when logic input is less than O.BV.
FIGURE 2

II. Charge Injection (sample to hold offset) measurement circuit; also switching transients test circuit.

N.C.

1.

N.C.

15

TO 10 . SCOPE
PROBE

N.C.

1.
O.OlI'F

100il

L--1

15V

2.k

_ _ OFFSET
POTENTIOMETER

13
N.C.

12

·3V
.V

~

11

,.

·5V

,15V

N.C.

15V

Adjust offset to OmV before testing for charge injection. See note 1.

CHARGE INJECTION

SWITCHING TRANSIENTS

5V/DIV.
VA .,-- GND
LOGIC INPUT ~
Cs - O.01jlF

. . . , - ~3V

......J

L-

UPPER TRACE =
OV

SV/D,V.

II~ +3Y

'

.....J

L--

VA ""GND
LOGIC INPUT'"

OV

Cs '" 0.011-'$

LOWER TRACE'" 5mV/DIV.
TIME lOps/em

FIGURE 3

5-59

~-"'3V

--I

L..-

. - - , - +3Y

UPPER TRACE =
OV

--.J

L--

LOWER TRACE = SOOmY/DIY.
TIME"" lOlls/em

OV

IH5110 . IH5115
III. Typical Circuit for measurement of A.C. signal handling capability.
ACQUISITION TIME

1.

N.C.
+10Y

OY

N.C.

~ANALOG

PROBE
2

STEP INPUT

O.01MF

+3V

15

N.C.

"

10011

..c-I

OUTPUT
TO 10 x seOP,E

20k -15V
_
OFFSET
POTENTIOMETER

13
N.C.

12

11

+15V

+5V

10

N.C.

TTL lOGIC IN

":15Y
SViDIV.

-=-

,

VA ==

.s-c

+10V

,

UPPER TRAC~
"

~-+10V

,

=....J ' L..-

OY

OV

SViDIV.

LO~ER

LOGIC INPUT"" +3V
Cs "" O.01j.(F

, - - - - " \ - +1DY

TRACE ==

-J

~ OY

TIME"" 5/-ls/cm

NOTE: The acquisition time is actually a settling time spec. since the reading is only taken when the output has settled within 1% of its final
value. The 61'S spec. IIH5111, 5113 & 5115 is the worst reading of the ton or toff settling time shown above. The above test can be
performed with a 0 to +7.5V or 0 to -7.5V step for the IH5110, 5112, 5114.

FIGURE 4

IV. Typical Circuit for measurement of A.C. peak to peak signal handling capability.

N.C.
N.C.
A.c.

SIGNAL GENERATOR
~
f =- 1kHz

OUTPUT
TO 10 x SCOPE
PROBE

15

N.C.

ANALOG IN FROM

O.01J1F

A.C, PEAK TO PEAK

1.
3

100!!

20k
_

r-1,..........,vv·v--t

-15V
OFFseT
POTENTIOMETER

N.C.

-5V

11

+15V

10

N.C.
-15V

TYP.IH5111

To test this parameter, increase the amplitude of the signal
generator until the output starts to distort (it will always show
up on the positive excursion of the sine wave first); then back
off until all distortion is gone. The resultant peak to peak
swing must be greater than 15Vpp for the IH5110, 5112, 5114
and greater than 20Vpp for the IH5111, 5113, 5.115.

UPPER TRACE

LOGIC INPUT == +3V
Cs = O.01j.1F f = kHz

FIGURE 5

5-6'0

=

~ ov

UPPER &
LOWER TRACE == lOY/DIY.
TIME'" a.Sma/em

IH5110 -

IH5115

V. Application Tips:
If you are undecided as to which sample and hold to use
within the family, the following will give you a pretty good
idea of the outstanding differences between the six models.
First, determine the voltage range you need to sample and
hold.
The even numbered parts are designed to switch smaller a.c.
signal amplitudes with the goal being to minimize the charge
injection effects (sample to hold offsets)' This charge
injection error is shown in Fig. 3. Once, the voltage offset is
zeroed, the 5110 has typical error amplitudes of 1 to 2mVp-p
(corresponds to 10pc to 20pc of charge). Thus one could
sample very low level d.c. Signals with extremeaccuracy.lf
very low level a.c. signals are being sampled, voltage offset potentiometer can be adjusted for a zero charge injection effect. Once the potentiometer has been adjusted,
there will be a zero error going from sample to hold; however there will be a d.c. error caused by adjusting the potentiometer for zero charge injection and not for zero
voltage offset. In general, this d.c. error will be in the area
of 2mV to 5mV.
The odd numbered parts are primarily designed to handle
any input in the plus or minus 10V range, regardless of
whether it is a.c. or d.c.; to obtain this, the charge injection is
abo'ut a factor of 2 higher than the even numbered parts.
The use of Varafet switching elements similar to Intersil's
IH401/401A leads to a trade-off between AC signal swing
and charge injection.
After the voltage range and charge injection requirements
have been determined, all that remains is to determine the
input offset voltage the system can tolerate. By using the
higher numbered parts, it is possible to eliminate the offset potentiometer if system accuracy will allow 5mV (5114,
5115) or 10mV (5112, 5113) due to the low input offset
voltage on these devices.
The drift rate is specified at 10mV/sec. Max. for all models:
this corresponds to approximately 1~OpA total leakage into a
O.D1f.lF sampling capaCitor (Cs). While the 10mV/sec. is the
Max. encountered, a more typical reading is less than

1mV/sec. (true for any input between -10V and +10V); thus
the IH5110 family is ideal for applications requiring very low
drift or droop rates.
The aperture time is spec'd at 200ns Max. for all models, but a
more typical value is 150ns; this is basically the off time of
switch Q,. The way this aperture time affects system
accuracy is shown below:
Assume the input signal to the Sample and Hold is an a.c.
signal of peak amplitude A (peak to peak swing is 2A) and
frequency 2rrf =w, then Vinput =Aeiwt then dVIdt = Aejwt. This
means the slope of input signal = dV/dt; this slope is a
maximum at t (time) = 0, this maximum value is wA (in
amplitude). (j.e') input frequency is 10kc, therefore dV/dt =
wA = 6.28 x 104 X 1OV = 6.3 x 105V Isec.A = 1OV, then slope or
dV/dt = 0.63V/p.s. Now if we wish error to be a Max. of say 1%
of full scale 10V, we see that 100mV (1%/aperture time =
0.63V/f.ls. Solving this equation we see that aperture time
must be 160ns or less to get 1% holding accuracy. Since our
aperture time is 150ns typical, we have 1% accuracy in
holding 10kHz varying signals; for signal frequencies 1kHz
and less, Max. error is 0.1%. The simple interpretation of just
how the off time of the switch causes this system error is due
to the fact a finite time is required for the switch to react to a
hold command; this reaction time manifests itself with a
system voltage error because the time varying input signal is
changing to a new value before the switch has actually
turned off. (i.e,) in the above example off = 10kHz and A =
10V, suppose we gave the hold command (thru TTL logic) att
= 0 (a.c. signal goes thru zero pI.) At this point we have
calculated the slope to be a Max. and equal to 0.63V/f.ls. If
there were no aperture time error, we would read OV at output
of Sample and Hold; however because of finite time for
switch to respond to hold command, 150ns passes before
switch goes off. During this 150ns, the input signal has gone
to 100mV above or below OV, thus the stored value of signal
will be 100mV and that is the reading at the output of the
Sample and Hold. If the input frequency were 1kHz, the
"error voltage" would be 10mV.

5-61

'&
"~

IH5110 -

IH5115

VI. Connection for Hi-Speed Sample and Hold with following typical performance: wlCs = 0.001
a. 2f.J.s settling time (acquisition time) to 1% accuracy
b. 25mV charge injection amplitude
c. 10mV/sec drift rate
HI-SPEED SAMPLE AND HOLD

,.

N.C.

+10V

N.C.

.~,..-

L:.-. STEP INPUT

-1"'1'O;:1~ANALUG

ov-.:J

2

15

OUTPUT
TO 10 x SCOPE
PROBE

N.C.

1.
O.001,'-'F

510n

20k -15V

r-!''''''-V'VV--I

-

OFFSET
POTENTIOMETER

12

N.C.

TTL LOGIC IN

13

+3V

+5V

11

+15V

10

N.C.
-15V

5V/DIV.

"":'"

UPPER TRACE'"""'

VA =

..J""L

LOGIC INPUT = +3V
Cs == O.001J,lF

-HOV

L..- ov

+10V

OV

SViDIV.

LOWER TRACE ==

_ r - - \ , . - +10V

--J
TIME

[I

". . . -

---I

'-=

'-- OV

51's/em

NOTE: Typical times lor the Sample and Hold to acquire the input are 2"s for turn on (output) goes to +10V and 3"s lor turn ofl (output goes
down to OV). As a general note, all the electri.cal specifications are guaranteed with a sampling capacitor equal to 0.01,,1. As the above
application (Fig. 6) shows, other values 01 sampling capacitors can be used but the best combinations of S & H specs may not result
with values other than 0.01"F. The only advantage 01 using a 0.001"F for Cs is the acquisition timeis 2"s typical instead of 5"s typical
(with 0.01 "F; however the drift rate would be worse and charge injection would be affected). To minimize drift rate, use a 0.1 "F capacitor;
this should produce a 0.1 mY/sec rate 01 change and a charge injection amplitude 01 0.2mVp-p. Of course the acquisition time will be
slowed down to the 25~sarea. Also use a 0.1~s system lor slow speed changes (i.e., input frequency is less than 1kHz. The series
resistor should be about 100n·200n to stabilize the system.
FIGURE 6

DEFINITION OF TERMS
Aperture Time: The time it takes to switch from sample mode
to hold mode and the actual opening of switch.
Charge InJection: The amount of charge coupled across ~he
switch with no input voltage.
Drift Rate: The amount of drift of output voltage at a rate
caused by current flow through the storage capacitor.

~
 OUTPUT

#2

--

-INPUT

I
1

CAZ
OP
AMP
OUTPUT
ANALOG
SWITCH
SECTION

rl
:l-"
Y

+2 OR -;-32
DIVIDER NETWORK

jR

t

5-64

r

STABILIZED
POWER
SUPPLY

I

LEVEL
TRANSLATORS

(DIVISION RATIO)

tJ

LEVEL
TRANSLATORS

,-2

II

!-

ICL7605/1CL7606
OPERATING CHARACTERISTICS
Test Conditions: V+ = +5 volts, V- = -5 volts, TA'= +25°C, DR pin connected to V+ IteoM= 160Hz, teOMl = 80Hz)'
Cl =C2=C3=C4 = 1"F, Test Circuit 1 unless otherwise specified,

PARAMETER
Input Offset Voltage

SYMBOL
Vos

Average Input Offset
~Vos/~T
Voltage Temperature
Coefficient
Long Term Input
~Vos/~t
Offset Voltage Stability
Common Mode Input Range
CMVR
Common Mode Re4ection Ratio CMRR

MIN

CONDITIONS
Rs S 1k!!

Low Bias Selti ng
Med Bias Selting
High Bias Setting
MIL version over temp.
Med Bias Setting
Low or Med Bias Settings -55° C > TA > +25° C
+25°C > TA > +85°C
+25°C> TA > +125°C
Low or Med Bias Settings

±2
±2
±7
0.01
0.01
0.05
0.5

PSRR
ISlAS

Equivalent Input Noise
Voltage peak-to-peak

enp~p

Equivalent Input
Noise Voltage
Voltage Gain

Maximum Output
Voltage Swing

Band Width of Input
Voltage Translator
Nominal Commutation
Frequency
Nominal Input Converter
Commutation Frequency
Bias Voltage to define
Current Modes
Bias (Pin 81 Input Current
Division Ratio Input
Current
DR Voltage to define
Oscillator division ratio
Effective Impedance of
Voltage Translator
Analog Switches
Supply Current

Operating Supply
Voltage Range

GBW

Any bias setting, fe
160Hz
IIncludes charge injection currentsl
Low Bias Mode
Band Width
Med Bias Mode
0.1 to 10Hz
High Bias Mode
Band Width
0.1 to 1.0Hz
All Bias Modes
RL - 100k!!
Low Bias Setting
Med Bias Setting
High Bias Setting
RL - 1M!!
RL = lOOk!!
Positive Swing
RL = 10k!!
Neqative Swinq
All Bias Modes
C3 - C4 - 1!-'F

fCOM

Cose - OpF

feoMl

Cose - OpF

VSA
VSM
VSL
ISlAS
lOR

Low Bias Setting
Med Bias Setting
High Bias Setting

VORH
VORL

Internal oscillator division ratio 32
Internal oscillator division ratio 2

en
Av

±VO

DR
DR
DR
DR

Connected
Connected
Connected
Connected

to
to
to
to

90
90
80

V'-V

±5
+20
0.2
0.2
0.2

+5.3

dB
dB
dB
nA

1.5

4.0
4.0
5.0

I'V
I'V
I'V

1.7
105
105
100
±4.9
±4.8

I'V
dB
dB
dB
V
V
V
V
Hz.

-4.5

V -{)3
V-+1.4
V--{)3

160
2560
80
1280
V+
GND
V-

V++0.3
V' -1.4
V-+0.3

±30
±30

V+ -8.0S VOR S V+ +0.3 volt
V' -{)3
V+-8

V++0.3
V+ -1.4
30

High Bias Setting
Med Bias Setting
Low Bias Setting
High Bias Setting
Med or Low Bias Setting

5·65

7
1.7
0.6
5
4

I'V
I'V
I'V
I'V
!-'V;oC
!-'V;oC
!-'V;oC
!-'V/Year

100
104
110
0.15

10
V'
GND
V'
GND

UNIT

V
dB

+4.4

RAS
Isupp

MAX

94

5.3
Cosc - 0, DR connected to V', C3 - C4 -- 1!-,F
Cosc=1I'F,DR connected to GND, C3 = C4 = 11'F
Cosc=1I'F,DR connected to GND, C3 = C4 = 1Ol'F

Power Supply Rejection Ratio
-INPUT Bias Current

VALUE
TYP

Hz
Hz
Hz
Hz
V
V
V
pA
pA
V
V
k!!

15
5
1.5
10
10

mA
mA
mA
V
V

ICL760S/ICL7606
INPUT OFFSET VOLTAGE AND
PK-TO-PK NOISE VOLTAGE AS A
FUNCTION OF SUPPLY VOLTAGES

INPUT OFFSET VOLTAGE AS A
FUNCTION OF, AMBIENT TEMPERATURE

NEGATIVE POWER SUPPLY VOLTAGE
-11.5
-5.5
-4.5
-3.5
-2.5
-7.5

>

+10

TE~T CI~CUIT 11

"-

~
g

TA = 25°C

C, ~ C, ~ lMF
fcOM = 1,60 Hz

+8

III

~ -4.0

+6

~

~ +2

/

....

~

0

if>

-2

il!:
~

:s
~
Z

./

/

OFFSET VOLTAGE

:lJ
IL

I

20

'eoM = 160 Hz

.... -3.0

.... +4

"

>

~

"

10

III

~

-25
0
25
50
75
100 125
TA' AMBIENT TEMPERATURE· °C

-==

12.5 W

-10
!!: If
IL

10.0

g

7.5

:t

0
~ ....

TA - 25°C
Av ~ 1000
Rs <; lkll
C, ~ O.lMF

I--

c,.

'. V+~+5V\ \ V-~-5V/
OFFSET

VOhl~

r-rd""'" ~
r-

p.p
NOISE

II
MED

~Ai

V

\

I""""

l.- BI~t
HIGH

20.0 ~
17.5

Q,

.

~
15.0g

LOW
BIAS

7.5

HIGH BIAS

5.0

....

~

2.5

,,;

2.5

INPUT CURRENT AS A FUNCTION
OF COMMUTATION FREQUENCY

'! -500
0",

,,!Z -400

II

ZIII

;::a: -350
a: a:
~a-300
il!: ....

INiB NON INVERTING
INPUT CURRENT

iS~ -250

";';; -200

\ /

l~-150
.a:

)'

~~-100

-50

o

i-"':

--

I

if

TA ~ 25°C
IV+,V-I ~ 10 VOLTS

/

I
I

I
'I

I

II

I

Rs::;: 1kO

W

C" C, ~ 1.0MF
IV+I ~ IV-I

5z tu-4
g

teOM = 160 Hz

....
-'

/v

If
~ ~-3

Q.

5.0 ~

100
lk
10k
fcOM' COMMUTATION FREQUENCY· Hz

a: • -450

0
0
lk
10k
10
100
leOM' COMMUTATION FREQUENCY· Hz

COMMON MODE REJECTION RATIO
AS A FUNCTION OF THE INPUT
DIFFERENTIAL TO SINGLE ENDED
VOLTAGE CONVERTER
CAPACITORS

III
30~

1000

~

:t

.)ol.v&
''''''.! ~.:~~rl'AS

J~OLTAGIE

~

10.0 x:

~V

'[\"
~

Av

~-5

w

12.5

TA = 25°C

j

I,)

~'NV~T'NG
INPUT CURRENT

10
100
1000
feoM' COMMUTATION FREQUENCY· Hz

~
,,;

~

~-2
~
if>

~-

..
o

20

105

8!g 100
iSg

V

OZ

a: ....
w

,,;

14

o

16

MAXIMUM OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT LOAD RESISTANCE

J..r-

r

/

V

8n
0.1

"

1/
1.0
10.0
C3, C4 - VOLTAGE CONVERTER
, CAPACITOR VALUES - MF

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

-

...-:'

~i+3

gffi+ l

/

./

.... 0

~6

0

~~ ~Jo Hz

1/

>+4

~S+2

160 Hz

...J..r"

./

/

I;:: 90

5 ::

';;OtsE'Vt';-AGE

+5

95

:E
0 oa: 85

f c =40Hz

. / !'to ~

i-"

:t a:~

10~

./

V

1S~ 00
N

.u-

TA - +25 0
V'·V- ~ 10V
C, ~ C, ~ lMF

:EI

5 :E«
:Ea:
Z

,8
10
12
6
SUPPLY VOLTAGE

2

I

"

-

1

o

25g
III

/ ' , " , BIAS

TA = 25°C

TA ~ 25°C
,..IV+,V-I ~ 10V
RL CQNNECTED TO GND_

NO LOADNO INPUT

./

-

.... w
50
-1

.:-~ -2

~$a: -3

'\

-4
-5
100

....... ......
lk
10k,
RL' LOAD RESISTANCE

5·66

lOOk

~
0

il!: -5

35~

-7

~ ~;)

N

:::>

INPUT OFFSET VOLTAGE AND
PK-TO·PK NOISE AS A FUNCTION
OF SUPPLY VOLTAGE (V+-V-)
>

,

-20

II>

W

~

+2.5
+3.5
+4.5
+5.5
+6.5
+7.5
• POSITIVE POWER SUPPLY VOLTAGE

INPUT .OFFSET VOLTAGE AND
PK-TO-PK NOISE VOLTAGE AS A
FUNCTION OF COMMUTATION
FREQUENCY (Cl, C2 = 0.1 f'F)

>

5 >....

z

-50

«

15.0 ~
0

-'

~

t--- t-_N~lrE~~'A.!!~,,;;;

if>

17.5 ~

!:i "
;! -15

g
Z

-2.0

-;- -1.0

20.0 ~

-20

"-

III 0

15

-4

il!:

>
W

Av ~ 1000
Rs::; 1kH
C" C, ~ 1.0MF
IV+, V-I ~ 10 VOLTS

~
o
>

INPUT OFFSET VOLTAGE AND
PK-TO-PK NOISE VOLTAGE AS A
FUNCTION OF COMMUTATION
FREQUENCY (Cl, C2 = 1f'F)

o

2

--

./
MED BIAS
LO BIAS

I

4
6
8
10
12
14
16
IV+,V-I' SUPPLY VOLTAGE· VOLTS

ICL7605/1CL7606
SUPPL Y CURRENT AS A
FUNCTION OF TEMPERATURE

f--L

i--

..:

£

HI ~'AS

E

....
ffi
a:

i'- :--..

5

a

V+-V- = 10 VOLTS
NO LOAD
NO INPUT

a:

4

>
....
0..

--

0..

:l

2

IJ)

MED BIAS
LO BIAS

o

-50

OSCILLATOR FREQUENCY AS A FUNCTION
OF EXTERNAL CAPACITIVE LOADING

u

"-

"I
w
is -10

f".-

ow

/"I

IJ)

For Case

...
a:
a:

-

w -20
a:

I

t:
....

I

!5 -30

~

:::! 100

u

-

t----..

-r--

10

1
10
100
1000
Case - OSCILLATOR CAPACITANCE - pF

FREQUENCY RESPONSE OF THE 10 Hz LOW
PASS FILTER USED TO MEASURE NOISE
(TEST CIRCUIT 2).

II
w

IJ)

Z -10

"

IIR~

1 AZ -DIFF IN 18
3C4
4C4
5 C2
6C2
7 V-

+DIFF IN 17
C316
C315
C114
C,13

~
~
~

:l

....

~.

10
100
1,000
f - FREQUENCY - Hz

r------4 2 -IN

w

:-20
c

~t "-

I

>
..:

t-T~=125ld

IJ)

~'ALIASINGt-

I -50

~

o

o0..

~ -40

..:

I

0 pF

IJ)

j "-f~!,D=B~:i Hz

w

~

5

~

IJ)

1

fo~e '., ~.2 kkz

1k

TA - +25°C
(V'-V-) = 5 VOLTS
Cl'::= C2 = C3 = C4 = 1~F

0..

TA = 25'C
5 < IV+-V 1< 10 VOLTS=
~

zw

:l

-25
0
25
50
75
100 125
TA - AMBIENT TEMPERATURE 'C

CD

L' L

>

AMPLITUDE RESPONSE OF THE INPUT
DIFFERENTIAL TO SINGLE ENDED VOLTAGE CONVERTER

-liD

10k

~-30

"

~

F'I

ci' -40

"

10,000

2

~

3 45
10
20304050
I - FREQUENCY - Hz

100

GND OR VOLTAGE
BETWEEN
(V' +0.3) AND
(V- -{l.3) VOLT
'MF

DR 12

+5V

8 BIAS
OSC"
9 OUTPUT V+ 10

+5V

t-'"V'-f\r-<>_-_ OUTPUT
1M
VOUT

lK

VOLTAGE GAIN = 1000

TEST CIRCUIT 1: USE TO MEASURE:
(VOUT)
a) INPUT OFFSET VOLTAGE 1000
b)
c)
d)
e)

INPUT EQUIV NOISE VOLTAGE
SUPPLY CURRENT
CMRR
PSRR

TEST CIRCUIT 2: DC to 10Hz (1Hz) unity Gain Low Pass Filter

5-67

ICL7605/1CL7606
DETAILED DESCRIPTION
CAZ Instrumentation Amp Overview

CAZ Op Amp Section

The CAl instrumentation amplifier operates on principles
which are very different from those of the conventional three
op amp designs, which must use ultra-precise trimmed
resistor networks in order to achieve acceptable accuracy:
An important advantageofthe ICL7605/1CL7606 CAl instrumentation amp is the provision for self-compensation for
internal error voltages, whether they are derived from
steady-state conditions, temperature, supply voltage fluctuations, or are variable over a long term,
The CAl instrumentation amplifier is constructed with
monolithic CMOS technology, and consists of three distinct
sections, two analog and one digital. The two analog
sections - a differential to single-ended voltage converter,
and a CAl op amp - have on-chip analog switches to
steer the input signal. The analog switches are driven from a
self-contained digital section which consists of an RC
oscillator, a programmable divider, and associated voltage
translators. A functional layout of the ICL7605/1CL7606 is
shown in Figure 1,

Operation of the CAl amp section of the ICL7605/1CL7606
instrumentation amplifier is best illustrated by referring to
Figure 2. The basic amplifier configuration, represented by
the large triangles, has one more input than does a regular op
amp - the Al, or auto-zero terminal. Thevoltage on the Al
input is that level at which each of the internal op amps will be
auto-zeroed, In Mode A, op amp #2 is connected in a unity
gain mode through on-Chip analog switches, It charges
external capaCitor C2 to a voltage equal to the DC input offset
voltage of the amplifier plus the instantaneous lowfrequency noise voltage, A, short time later, the analog
switches reconnect theon-chip op amps to the configuration
shown in Mode B, In this mode, op amp #2 has capacitor C2
(which is charged to a voltage equal to the offset and noise
voltage of op amp #2) connected in series to its non-inverting
(+) input in such a manner as to null out the input offset and
noise voltages of the amplifier. While one of the on-chip op
amps is processing the input signal, the second op amp is in
an ,auto-zero mode, charging a capacitor to a voltage equal
to its equivalent DC and low frequency error voltage, The onchip amplifiers are connected and reconnected at a rate
deSignated as the commutation frequency (fCOM), so that at
all times one or the other of the on-chip op amps is
processing the input Signal, while the voltages on capacitors
Cl and C2 are being updated to compensate for variables
such as low frequency nOise voltage and input offset voltage
changes due to temperature, drift or supply voltages effects.

-OIFF IN

-l
I
I OUTPUT

I
I
I
AZ -INPUT

Compared to the standard bipolar or FET input op amps, the
CAl amp scheme demonstrates a number of important
advantages:
* Effective input offset voltages can be reduced from 1000
to 10,000 times without trimming,
* Long-term offset voltage drift phenomena can be
compensated and dramatically reduced.
* Thermal effects can be compensated for over a wide
operating temperature range. Reductions can be as much as
100 times or better,
* Supply voltage sensitivity is reduced.
CMOS processing is ideally suited to implement the CAl
amp structure, The digital section is easily fabricated, and

Figure 1: Simplified Block Diagram

, The ICL7605/1CL7606 have approximately constant equivalent input noise voltage, CMRR, PSRR, input offset voltage
and drift values independent of the gain configuration. By
comparison, hybrid-type modules which use the traditional
three op amp configuration have relatively poor
performance at low gain (1 to 100) with improved
performance above a gain of 100.
The only major limitation of the ICL7605/1CL7606 is its lowfrequency operation (10 to 20 Hz maximum), However in
many applications speed is not the most important
parameter.

'--_ _ _ _~..:O:=UTPUT

;.--_ _ _--.:~O!!:!.UTPUT

Figure 2: Diagrammatic representation of the 2 half cycles of operation of the CAZ OP AMP,

5-68

ICL7605/1CL7606

C,---t---------+---------1

c, ---+-+------.
OUTPUT

I~:UTATION
I

INPUT
FROMFIG4
AZ

~

RF
(100kll)

CL

C[

-INPUT - - - - - - - - - - - - - '

~ '-FfiEQUENCY)

Figure 3: Schematic of analog switches connecting each internal OP AMP to its inputs and output.

the transmission gates (analog switches) which connect the
on-chip op amps can be constructed for minimum charge
injection and the widest operating voltage range. The analog
section, which includes the on-chip op amps, contributes
performance figures which aresimilarto bipolar or FET input
designs. CMOS structure provides the CAZ amp with openloop gains of greater than 100 dB, typical input offset
voltages of ±5 mV, and ultra-low leakage currents, typically 1
pA.

DIFFERENTIAl-TO-SINGlE-ENDED
UNITY GAIN VOLTAGE CONVERTER
An idealized schematic of a voltage converter block is shown
in Figure 4. The mode of operation is quite simple, involving
two capacitors and eight switches. The switches are
arranged so that four are open and four are closed. The four
conducting switches connect one of the capacitors across
the differential input, and the other from a ground or
reference voltage to the input of the CAZ instrumentation
amp. The output signal of this configuration is shown in
Figure 5, where the voltage steps equal the differential
voltage (VA-VB) at commutation times a, b, c, etc. The output
waveform thus represents all information contained in the
input signal from DC up to the commutation frequency,
commutation and noise voltages are added. Sampling theory
states that to preserve the integrity of the information to be
processed, at least two samples must be taken within a
period (1/f) of the highest frequency of the signal being

The CMOS transmission gates connect the on-chip op amps
to external input and output terminals, as shown in Figure 3.
Here, one op amp and its associated analog switches are
required to connect each on-chip op amp, so that atany time
three switches are open and three switches are closed. Each
analog switch consists of a P-channel transistor in parallel
with an N··channel transistor.

+DIFF IN o--+--~

,-

(54
~---+--INPUT

OF AMPLIFIER

, - - - - - . - - G N D OR REFERENCE VOLTAGE

55

56
-DIFF IN

<>-----t--1

MODE
5,
52
53
54
A
CLOSED OPEN CLOSED OPEN
OPEN CLOSED OPEN CLOSED
B

56

The frequency at which modes A & B are cycled is
known as the INPUT COMMUTATION FREQUENCY

5.

Figure 4: Sohematic of the differential to single ended voltage converter

5·69

57

5.

OPEN CLOSED OPEN
CLOSED OPEN CLOSED

Ii
@III

ICL7605I ICL7606

OUTPUT
VOLTAGE

sampled, Consequently this scheme preserves information
up to the commutation frequency, Above the commutation
frequency, the input signal is transferred to a lower
frequency, This phenomenon is known as aliasing, Although
the output responds above the commutation frequency, the
frequencies of the output responses have been aliased down
to frequencies below the commutation frequency,
The voltage converter is fabricated with CMOS analog
switches, which contain a parallel combination of P-channel
and N-channel transistors, The switches have finite ON
impedances of 30k!1, plus parasitic capacitances to the
substrate, Because of the Charge injection effects which
appear at both the switches and the output of the voltage
converter, the values of capacitors Co and Co must be about
1",F to preserve signal translation accuracies to 0,01%, The
1",F capacitors, coupled with the 30k!1 equivalent
impedance of the switches, produce a low-pass filter
response from the voltage converter which is approximately
3dBat10Hz,
'

GND OR
REFERENCE

! - - - - i VOLTAGE
INPUT COMMUTATION
PERIOD (1/fCOM1)

Figure 5: Input to Output Voltage waveforms from the differential to
single ended voltage converter. For additional information, see
frequency characteristics in Amplitude Response of the Input
Differential'to single ended voltage converter graph on page 5,

APPLICATIONS
USING THE ICL7605/ICL7606 TO BUILD A DIGITAL READOUT TORQUE WRENCH
that, given a certain strain gauge bridge with a defined
pressure voltage sensitivity, a value of gain for the ICL7605/
ICL7606 instrumentation CAl amp be selected along with an
appropriate value for the reference voltage, The gain should
be set so that at full scale the output will swing about 0,5V,
The reference voltage required is about one-half the
maximum output swing, or approximately 0,25V,

A typical application for the ICL7605/ICL7606 is in a strain
gauge system, such as the digital readout torque wrench
circuit shown in Figure 6, In this application, the CAl instrumentation' amplifier is used as a preamplifier, taking the
differential voltage of the bridge and converting this voltage
to a single-ended voltage reference to ground, The signal is
then amplified by the CAl instrumentation amplifier and
applied to the input of a 3~1/2 digit dual-slope NO converter
chip for LCD panel meter display, The NO converter device
used in this instance is the Intersil ICL7106,
In the digital readout torque wrench circuit, the reference
voltage for the ICL7106 is derived from the stimulus applied
to the strain gauge, to utilize the ratiometric capabilities of
the NO, In order to set the full-scale reading, it is required

In this type of system, only one adjustment is required, Either
the amplifier gain or the reference voltage must be varied for
full-scale adjustment. Total current consumption of all circuitry, less the current through the strain gauge bridge, is
typically 2 mA. The accuracy is limited only by resistor ratios
and the transducer.

OSC 140

asc 2 39

100k

osc 338
TEST,3?
1

AZ

IN 18

REF HI36

+DlFF IN17

REF LO 35
C REF 34
C REF 33
COMM 32

~DIFF

.------/2 -IN
3 C4

;g~

C316

ICL7606 g~~:

6 C2

C,13

10

V-

DR12

11

7

a BIAS
OSC11
9 OUTPUT
V" 10

v'

1Mil
10kn

r

O,1 MF

Rl

Av

13
14
15
16
17
18

=

Rl + R2
-R-,-

1.5 Hz
LOW PASS
FILTER

= 101

TIMES

BUFF 28
,22MF
INTH

v-

ICL7106

26
25
24

19

23
22

20

21

--=
20

LCD DISPLAY

Figure 6: 3-1/2 Digit Digital Readout Torque Wrench

5-70

IN HI3l
IN LOlo .47jJ.F
AZ 29

v-

ICL7605I ICL760e
Output Loading (Capacitive)

SOME HElPFUL HINTS
Testing the ICL760S/ICL7606
CAZ Instrumentation Amplifier
Test Circuits #1 and #2 provide convenient means of
measuring most of the important electrical parameters of the
CAl instrumentation amp. The output signal can be viewed
on an oscilloscope after being fed through a low-pass filter. It
is recommended that for most applications, a low-pass filter
of about 1.0 to 1.S Hz be used to reduce the peak-to-peak
noise to about the same level as the input offset voltage.
The output low-pass filter must be of a high-input impedance
type-Inot simply a capacitor across the feedback resistor R2)
at about 100kO and 1.01'F so thatthe output dynamic loading
on the CAl instrumentation is about 100kO.

Bias Control
The on-chip op amps consume over 90% of the power
required by the ICL760S/ICL7606 instrumentation op amp.
For this reason, the internal op amps have externallyprogrammable bias levels. These levels are set by
connecting the BIAS terminal to either V:, GND, or V~ for
LOW, MED or HIGH BIAS levels, respectively. The difference
between each bias setting isabout a factor of 3, allowing a 9:1
ratio of power supply versus bias setting. This current
programmability provides the user with a choice of device
power dissipation levels, slew rates (the higher the slew rate,
the better the recovery from commutation spikes), and offset
errors due to "IR" voltage drops and thermoelectric effects
(the higher the power dissipation, the higher the input offset
error). In most cases, the medium bias (MED BIAS) setting
will be found to be the best choice.

In many applications, it is desirable to include a low-pass
filter at the output of the CAl instrumentation op amp to
reduce high-frequency noise outside the desired signal
passband. An obvious solution when using a conventional
op amp would be to place a capacitor across the external
feedback resistor and thus produce a low-pass filter.
However, with the CAl op amp concept this is not possible
because of the nature of the commutation spikes. These
voltage spikes exhibit a low-impedance characteristic in the
direction of the auto-zero voltage and a high-impedance
characteristic on the recovery edge, as shown in Figure 7. It
can be seen that the effect of a large load capacitor produces
an area error in the output waveform, and hence an effective
gain error. The output low-pass filter must be of a highimpedance type to avoid these area errors. Forexample, a 1.S
Hz filter will require a 100kn resistor and a 1.0!,F capacitor.
or a 1 Mil resistor and an 0.1!,F capacitor.

Oscillator and Digital Circuitry Considerations
The oscillator has been designed to run free at about S.2 kHz
when the OSC terminal is open circuit. If the full divider
network is used, this will result in a nominal commutation
frequency of approximately 160 Hz. The commutation
frequency is that frequency at which the on-chip op amps are
switched between the Signal processing and the auto-zero
modes. A 160 Hz commutation frequency represents the
best compromise between input offset voltage and low
frequency noise. Other commutation frequencies may provide
optimization of some parameters, but always at the expense
of others.
The oscillator has a very high output impedance, so that a
load of only a few picofarads on the OSC terminal will cause
a significant shift in frequency. It is therefore recommended
that if the natural oscillator frequency is desired IS.2 kHz) the
terminal remains open circuit. In other instances, it may be
desirable to synchronize the oscillator with an external clock
source, or to run it at another frequency. The ICL760S1
ICL7606 CAl amp provides two degrees of flexibility in this
respect. First, the DR Idivision ratio) terminal allows a choice
of either dividing the oscillator by 32 (DR terminal to V+) or by
2 (DR terminal to GND) to obtain the commutation
frequency. Second, the oscillator may have its frequency
lowered by the addition of an external capacitor connected
or system GND
between the OSC terminal and the
terminals. For situations which require that the commutation
frequency be synchronized with a master clock, (Figure 8)
the OSC terminal may be driven from TTL logic (with
resistive pull-up) or by CMOS logic, provided that the V+
supply (with respect to ground) is +SV (±10%) an.d the logic
driver also operates from a similar voltage supply. The

Output Loading (Resistive)
With a 10kO load, the output voltage swing can vary across
nearly the entire supply voltage range, and the device can be
used with loads as low as 2kO.
However, with loads of less than SOkO, the on-chip op amps
will begin to exhibit the characteristics of transconductance
amplifiers, since their respective output impedances are
nearly SOkO each. Thus the open-loop gain is 20 dB less with
a 2kO load than it would be with a 20kO load. Therefore, for
high gain configurations requiring high accuracy, an output
load of 100kO or more is suggested.
There is another consideration in applying the CAl instrumentation op amps which must not be overlooked, and that
is trye additional power dissipation of the chip which will
result from a large output voltage swing into a low reSistance
load. This added power dissipation can affect the initial input
offset voltages under certain conditions.

,r

OUTPUT

INPUT
AC

GND

RSOURCE

WAVEFORMS

OUTPUT
VOLTAGE

Figure 7: Effect of a load capacitor on output voltage waveforms.

5-71

m
.
,

ICL7605 I ICL7606

TTL
OR
CMOS
LOGIC

22kll

USE RL FOR TTL LOGIC
(NOT NEEDED FOR CMOS)

Figure 8: ICL7605 being clocked from external logic, into the
oscillator terminal.

reason for this requirement is that the logic section
Cincluding the oscillator) operates from an internal
--5V supply, referenced to V+ supply, which is not accessible
externally.

Thermoelectric Effects
The ultimate limitations to ultra-high-sensitivity DC
amplifiers are due to thermoelectric, Peltier, or thermocouple effects in electrical junctions consisting of
various metals (alloys, silicon, etc.) Unless all junctions are at
precisely the same temperature, small thermoelectric
voltages will be produced, generally about 0.1I'V/oC.
However, these voltages can be several tens of microvolts
per 0 C for certain thermocouple materials.
In order to realize the extremely low offset voltages which the
CAZop amp can produce, it is necessary to take precautions
to avoid temperature gradients. All components should be
enclosed to eliminate air movement across device surfaces.
In addition, the supply voltages and power dissipation
should be kept to a minimum by use of the MED BIAS setting.
Employ a high impedance load and keep well away trom
equipment which dissipates heat.
Component Selection
The four capacitors (C1 thru C4) should each be about 1.0I'F.
These are relatively large values for non-electrolytic
capacitors, but since the voltages stored on them change
significantly, problems of dielectric absorption, charge
bleed-off and the like are as significant as they would be for
integrating dual-slope AID converter applications. Polypropylene are the best forC3 and C4, though Mylar may be
adequate for C1 and C2.
Excellent results have been obtained for commercial
temperature ranges using several of the less-expensive,
smaller-size capaCitors, since the absolute values of the
capaCitors are not critical. Even polarized electrolytiC
capaCitors rated at 1.01'F and 50V have been used successfully at room temperature, although no recommendations
are made concerning the use of such capacitors.
Commutation Voltage Transient Effects
Although in most respects the CAZ instrumentation
amplifier resembles a conventional op amp, its principal
applications will be in very low level, low-frequency preamplifiers limited to DC through 10 Hz. The is due to the
finite switching transients which occur at both the input and

5·72

output terminals because of commutation effects. These
transients have a frequency spectrum beginning at the
commutation frequency, and including all of the higher
harmonics of the commutation frequency. Assuming 'thatthe
commutation frequency is higher than the highest in~band
frequency, then the commutation transients can be filtered
out with a low-pass filter.
The input commutation transients arise when each of the onchip op amps experiences a shift in voltage which is equal to
the input offset voltages (about 5-10mV), usually occurring
during the transitipn between the signal processing mode
and the auto-zero mode. Since the input capacitances of the
on-chip op amps are typically in the 10 pF range, and since it
is desirable to reduce the effective inputoffset voltage about
10,000 times, the offset voltage auto-zero capaCitors C1 ahd
C2 must have values of at least 10,000 x 10 pF, or 0.1I'Feach.
The charge that is injected into the input of each op amp
when being switched into the signal processing mode
produces a rapidly-decaying voltage spike at the input, plus
an equivalent DC input bias current averaged over a full
cycle. This bias current is directly proportional to the
commutation frequency, and in most instances will greatly
exceed the inherent leakage currents of the input analog
switches, which are typically 1.0pA at an ambient
temperature of 25° C.
The output waveform in Test Circuit #1 (with no input signal!
is shown in Figure 9. Note that the equivalent noise voltage is
amplified 1000 times, and that due to the slew rate of the onchip op amps, the input transients of approximately 7 mV are
not amplified by 1000.
~6

,--- m
OUTPUT
VOLTAGE
GND

s----l
DIFF,ERENTIAL TOSINGLEENpED
-I /COVERTER TRANSIENTS

T~

~
III
2rvl,~lNNI,lvV!lv.Iy'Nv"WN' IMvYNN,'f/r
III

L3
,m

s--l"
CAZ OP'AMP
'I
TRANSIENTS

TIME-

Figure 9: Output waveform from Test Circuit 1.

Layout Considerations
Care should be exercised in positioning components on the
PC board, particularly the capacitors C1, C2, C3 and C4, all of
which must be shielded from the OSC terminal. Also,
parasitic PC board leakage capacitances associated With
these four capaCitors should be kept as low as possible to
minimize charge injection effects.

ICL761X/

762X/763X/764X

Low Power CMOSTM
Operational Amplifiers
FEATURES
• Wide operating voltage range ±1.0V to ±av
• High input impedance - 1012 0
• Programmable power consumption - as low as
20/1W
• Input current lower than BIFETs - typ 1pA
• Available as singles, duals, triples, and quads
• Output voltage swing ranges to within millivolts of
V- to V+
• Low power replacement for many standard op amps
• Compensated and uncompensated versions

APPLICATIONS
• Portable instruments
• Meter amplifiers
• Telephone headsets
• Medical instruments
• Hearing aid/microphone • High impedance buffers
amplifiers
A numberof special options are available. They include:
• Single, dual, triple, and quad configurations
• Internally compensated and uncompensated
versions
• Inputs protected to ±200V (ICL7613/15)
• Input common mode voltage range greater than
supply rails (ICL7612)
Note: See page 2 for table of options.

SCHEMATIC
STAGE

10
SETTING
STAGE

I

I

INPUT

OUTPUT
STAGE

I

r---~----~-'--~~~----~---~--~--~--oV'

CD
OFFSET

+
'0

"NPUT

6.3V

>-------~

V

P9

'

-----'4". . ----

v-

cC"~~PF0

D

-INPUT

TABLE OF JUMPERS
lel-7611
tCL·7612
lel·7613
ICl-7614
ICl·7615
ICl-7621
ICL·7622
ICL-7631
ICL·7632
ICL·7641
ICl·7642

R F, H
B. F, H

B, F. H
C, D. E
C, D, E

c.
c.

E
E

S, F, H
B, F, H
c. G

A. E

vO·--i4.....-----<. IO/COMP ®

NOTES;
1. HIGH VALUE THIN FILM RESISTORS ARE PRESENT ONLY ON
ICL·7613 AND 7615. FOR ALL OTHER DEVICES, THEY ARE
REPLACED BY DIRECT CONNECTIONS.

2. OFFSET NULLING PINS ARE NOT AVAILABLE ON TRIPLE
(lCL·763X) AND QUAD (ICL-764X) VERSIONS.
3.10 AND COMP TERMINALS AA,E METAL MASK OPTIONS OF THE
SAME BONDING PAP; ONLY ONE OF THESE FUNCTIONS IS
AVAILABLE IN A GIVEN DEVICE.
4. FOR INTERNAllY COMPENSATED VERSIONS ONLY THIS
CAPACITOR IS ABSENT FOR ALL OTHER DEVICES

5·73

OUTPUT

ICL761X/762X/763X/764X
GENERAL DESCRIPTION

Of particular significance is the extremely low (1 pAl
input current, input noise current of .01 pAl 1Hz, and
1012{1 input impedance. These features optimize
performance in very high source impedance applications.

The ICL761X1762X/763X1764X series is a family of
monolithic CMOS op amps. These amplifiers provide
the designer with high performance operation at low
supply voltages and selectable quiescent currents,
and are an ideal design tool when ultra low input
current and low power drain are essential.

The inputs are internally protected and require no
special handling procedures. Outputs are fully protected against shorts to ground or to either supply.

The basic amplifier will operate at supply voltages
ranging from ±1.0V to ±8V, and may be operated from
a single Lithium cell.

AC performance is excellent, with a slew rate of
1.6V/J.ls, and unity gain bandwidth 011 MHz at 10=
1 mAo

A unique quiescent current programming pin allows
setting of standby current to 1 mA, 100 J.lA, or 10 J.lA,
with no external. components. This results in power
drain as low as 20 J.lW. Output swings range to within a
few millivolts of the supply voltages.

Because of the low power dissipation, operating
temperatures and drift are quite low. Applications
utilizing these features may include stable instruments, extended life designs, or high density packages.

SELECTION GUIDE

BASIC TYPE

ORDER SUFFIX

BASIC TVPE
TO-99
OFFSET
NULL CAPABILITY
V = VES
N=NO

IQSETTING
L = 10!,A FIX ED
M = 100!,A FI XED
H = lmA FIXE D
P= PROGRAM MABLE

a

W

f-

a wf- >a~
-,w
-,wu
-,f- f-U -,f-w

w8 u'" wu~
Z
OW

a:
>
::<
U
a
w
a
Z
w
fX
w

MINI PLASTIC CERAMIC
DIP(1)
DIP DIP!1!

'b

U
10
N

'0

+
,9

+
,9

+
,9

U

U
10

u

....

'b

"'

u

....
U

'b

u

'b
....

+
,9

U

'b

u

'b
....
+
,9

U

0

U

'~"'
+
,9

U

'"'"'

DIE

u

'b
....
+

,9

U

0

0 P

~

VOS SELECTION
A=2mV
B=5mV
C = 10mV
D = 15mV
Ii = 211'mV

SINGLE

DUAL

7611 7614 7613

7615

VIP VIM VIP

VIM

7622
IvlM
[3j

TEMP. RANGE
C = O°C TO 70°C
M = -55'C TO +125°C

TRIPLE

High IQ
PACKAGE CODE
TV - TO-99, 8 PIN
PA - PLASTIC 8 PIN MINI DIP
PD - 14 PIN PLASTIC
PE - 16 PIN PLASTIC
JD - 14 PIN CERDIP
JE - 16 PIN CERDIP

7631 7632
Nip Nip

QUAD

QUAD
LowlQ

OCtD

--

1458 PINOUT INIM

747 PINOUT

--

ACTV AMTV ACPA
BCTV BMTV BCPA
DCTV
OCPA

7621

DUAL

7612 ACTV AMTV ACPA
BCTV BMTV BCPA
V IP
DCPA
DCTV

I~~
7642

Pre

OCtD
ACPD
BCPD
DCPD

ACJD AMJD·
BCJD BMJD
OCJD - - DCtD

BCPE
CCPE
ECPE

BCJE BMJE
CCJE CMJE
ECJE
ECtD

BCPD
CCPD
ECPD

BCJD BMJD
CCJD CMJD
ECPD - - ECtD

BCPD
CCPD
ECPD

BCJD BMJD
CCJD CMJD
Ec::JD - - EC/D

--

NOTES: 1. Duals and quads are available in 14 pin DIP packages, triples in 16 pin only.

2. Ordering code must consist of basic device and order suffix, e.g., ICL7611BCPA.
3. ICL7632 is not compensatable. Recommended for use in high gain circuits only.

5-74

U

'"'~
+
,9

U
10

"'

ICL761X/762X/763X/764X
PIN CONFIGURATIONS
DEVICE

ICL7611XCPA
ICL7611XCTV
ICL7611XMTV
ICL7612XCPA
ICL7612XCTV
ICL7612XMTV
ICL7613XCPA
ICL7613XCTV
ICL7613XMTV

DESCRIPTION

I nternal compensation, plus
offset null capability
and external I Q control.

PIN ASSIGNMENTS
TO·99 (TOP VIEW)
(outline dwg TV)

8 PIN DIP (TOP VIEW)
(outline dwg PAl

10 SET

·Pin 7 connected to case.

ICL7614XCPA
ICL7614XCTV
ICL7614XMTV
ICL7615XCPA
ICL7615XCTV
ICL7615XMTV

Fixed IQ (100,uA), external

compensation, and offset

TO·99 (TOP VIEW)
(outline dwg TV)

8 PIN DIP (TOP VIEW)
(outline dwg PAl

null capability.
COMP

COMP

OFFSET

-IN

v,

+IN

OUT

v-

OFFSET

v

* Pin 7 connected to case.

ICL7621XCPA
ICL7621XCTV
ICL7621XMTV

Dual op amps with internal
compensation; I Q fixed
at 100,uA

TO·99 (TOP VIEW)

8 PIN DIP (TOP VI EW)
(outline dwg PAl

(outline dwg TV)

v+

v+ OUT. -IN. +IN.

Pin compatible with
Texas Inst. TL082
Motorola MC1458
Raytheon RC4558

OUT. -IN. +IN.

v* Pin 8 connected to case,
ICL7622XCPD

14 PIN DIP (TOP VIEW)
(outline dwgs JO, PO)

Dual op amps with internal

compensation and offset
null capability; IQ fixed
at 100,uA

OFFSET. v+ OUT.

Pin compatible with
Texas I nst. TL083
Fairchild ,uA747

N/C

OUT.

14

Note: Pins 9 and 13 are internally connected.

5-75

v+

OFFSET.

v-

ICL781X/782X/783X/784X
PIN CONFIGURATIONS (Cont.)
DEVICE
ICL7631XCPE
ICL7632XCPE

DESCRIPTION
Triple op amps with internal
compensation (lCL7631) and
no compensation (lCL7632).
Adiustable I Q
Same pin configuration as
ICL8023.

PIN ASSIGNMENTS
16 PIN DIP (TOP VIEW)
(outline dwgs JE. PEl
loe

lOA

SET

V+

OUTA

+INa

-IN.

-INA

+IN.a.

OUT.

v+

SET

16

•
NC

lac

-INc

+INc

SET

Note: Pins 5 and 15 are internally connected.

ICL7641XCPD
ICl7642XCPD

14 PIN DIP (TOP VI EW)
(outline dwg JO. PO)

Quad op amps with internal
compensation.
10 fixed at 1mA (lCL7641)
10 fixed at 10jlA (lC L 7642)
Pin compatible with
Texas Instr. TL084
National LM324
Harris HA4741

aUTo

-INo

+IN D

v-

+INc

-INc

OUTe

14

IIiIII ~________~____________

:_~_~

C -_ _ _ _ _ _L -____________

__
-_IN_'__
+I_N'___
V_+__
+_IN_'_-_IN_.__O_U_T.____________

~

GENERAL INFORMATION
STATIC PROTECTION

These current settings change only very slightly over
the entire supply voltage range. The ICL 7611/12/13
and ICL7631/32 have an external 10 control terminal,
permitting user selection of each amplifiers' quiescent
current. (The ICL7614/15, 7621/22, and 7641/42 have
fixed 10 settings - refer to selector guide for details.)
To set the 10 of programmable versions, connect the
10 terminal as follows:
10 = 10J.lA - 10 pin to V+
10 = 100J.lA -10 pin to ground. If this is not possible,
any voltage from V+-0.8 to V- +0.8 can be used.
10 = 1rnA - 10 pin to V-

All devices are static protected by the use of input
diodes. However, strong static fields should be avoided,
as it is possible forthe strong fields to cause degraded
diode junction characteristics, which may result in
increased input leakage currents.
LATCHUP AVOIDANCE
Junction-isolated CMOS circuits employ configurations which produce a parasitic 4-layer (p-n-p-n)
structure. The 4-layer structure has characteristics
similar to an SCR, and under certain circumstances
may be triggered into a low impedance state resulting
in excessive supply current. To avoid this condition, no
voltage greater than 0.3V beyond the supply rails may
be applied to any pin. (An exception to this rule
concerns the inputs of the ICL7613 and ICL7615,
which are protected to ±200V.) In general, the op amp
supplies must be established simultaneously with, or
before any input signals are applied. If this is' not
pOSSible, the drive circuits must limit input current flow
to 2 rnA to prevent latchup.

NOTE: The negative output current available is a
function of the quiescent current setting. For maximum p-p ouputvoltage swings into low impedilnce
loads, 10 of 1 rnA should be selected.
OUTPUT STAGE AND LOAD
DRIVING CONSIDERATIONS
Each amplifiers' quiescent current flows primarily in
the output stage. This is approximately 70% of the 10
settings. This allows output swings to almost the
supply rails for output loads of 1M, 100K, and 10K,
using the output stage in a highly linear class A mode.
In this mode, crossover distortion is avoided and the
voltage gain is maximized. However, the output stage
can also be operated in Class AB, which can supply

CHOOSING THE PROPER 10
Each device in the ICL76XX family has a similar 10
set-up scheme, which allows the amplifier to be set to
nominal quiescent currents of 10 J.lA, 100 J.lA or 1 rnA.
5·76

ICL761X/762X/763X/764X
higher output currents. (See graphs under Typical
Operating Characteristics). During the transition from
Class A to Class B operation, the output transfer
characteristic is non-linear and the voltage gain
decreases.

HIGH VOLTAGE INPUT PROTECTION

A special featu re of the output stage is that it
approximates a transconductance amplifier, and its
gain is directly proportional to load impedance.
Approximately the same open loop gains are obtained
at each of the I Qsettings if corresponding loads of 10K,
100K, and 1M are used.

The ICL7613 and 76.15 include on-chip thin film
resisitors and clamping diodes which allow voltages of
up to ±200 to be applied to either input for an indefinite
time without device failure. These devices will be
useful where high common mode voltages, differential
mode voltages, or high transients may be experienced.
Such conditions may be found when interfacing
separate systems with separate supplies. Unity gain
stability is somewhat degraded with capacitive loads
because of the high value of input resistors.

INPUT OFFSET NULLING

EXTENDED COMMON MODE INPUT RANGE

For those models provided with OFFSET NULLING
pins, nulling may be achieved by connecting a 25K pot
between the OFFSET terminals with the wiper connected to V+. At quiescent currents of 1 rnA and 100 p.A,
the nulling range provided is adequate for all Vas
selections; however with IQ= 10 p.A, nulling may not be
possible with higher values of Vas.
FREQUENCY COMPENSATION

The ICL7612 incorporates additional processing which
allows the input CMVR to exceed each power supply
rail by 0.1 volt for applications where V supp 2: ±1.5V.
For those applications where V supp::O ±1.5V, the input
CMVR is limited in the positive direction, but may
exceed the negative supply rail by 0.1 volt in the
negative direction (eg. for V supp = ±1.0V, the input
CMVR would be + 0.6 volts to -1.1 volts).

Ttl:! IC'.7611/12/13, 7621/22, 7631, 7641/42 are

OPERATIONATVsupp = ±1.0VOLTS

internally compensated, and are stable for closed loop
gains as low as unity for capacitive loads up to 100pF

Operation at V supp = ±1.0V is guaranteed at I Q= 10J.LA
only. This applies to these devices with selectable I Q,
and those'devices are set internally to I Q ~~ 10p.A (i .e.,
ICL7611 ,7612,7613,7631,7632,7642).

The ICL7614 and 15 are externally compensated by
connecting a capacitor between the COMP and OUT
pins. A 39pF capacitor is required for unity gain
compensation; for greater than unity gain applications,
increased bandwidth and slew rate can be obtained by
reducing the value of the compensating capacitor.

Output swings to within a few millivolts of the supply
rails are achievable for R L2: 1 Megn. Guaranteed input
CMVR is ±0.6V minimum and typically -t-0.9V to -0.7 at
V supp= ±1.0V. For applications where greater common
mode range is desirable, refer to description of
ICL7612 above.

Since the gm of the first stage is proportional to .jjQ,
greatest compensation is required when I Q= 1rnA. The
ICL7632 is not compensated internally, nor can it be
compensated externally. The device is stable when
used as follows:

The user is cautioned that, due to extremely high input
impedances, care must be exercised in layout,
construction, board cleanliness, and supply filtering to
avoid hum and noise pickup.

IQ of 1 rnA for gains 2: 20
IQ of 100 J.LA for gains 2: 10
IQ of 10 p.A for gains 2: 5

ABSOLUTE MAXIMUM RATINGS

1

Total Supply Voltage V+ to V- ...............'..... 18V
Input Voltage ...................... V+ +0.3 to V- -0.3V
Input Voltage ICL7613/15 Only .... V T +200 to V- -200V
Differential Input Voltage i2 ...
±IIV T +0.3, - IV- -0.31IV
Differential Input Voltage,2,
ICL7613/15 Only ........
± IIV T +200, - IV- - 200,IV
Duration of Output Short Circuitl 3 , . . . . . . . . . . . Unlimited
Continuous Power Dissipation @ 25° C
Above 25° C
derate as follows:
TO-99
250mW
2mWfOC
8 Lead Minidip
2mWfOC
250mW
14 Lead Plastic
375mW
3mWfOC
4mW/oC
14 Lead Cerdip
500mW
3mW/oC
375mW
16 Lead Plastic
4mW/oC
16 Lead Cerdip
500mW
Storage Temperature Range .......... -55°C to +150°C

5-77

Operating Temperature Range
M Series ........................... -55° C to +125° C
C Series .............................. O°C to +70°C
Lead Temperature ,Soldering. 10 sec, ........... 300°C
Notes'
1. Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only. and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2. Long term offset voltage stability will be degraded Ii large
input differential voltages are applied for long periods of
time.
3. The outputs may be shorted to ground or to either supply.
for VsuPP oS10V. Care must be taken to insure that the diSSIpation rating is not exceeded.

.D~DIL

ICL761 X/762X
ELECTRICAL CHARACTERISTICS

VSUPP = -+5 OV TA =

25°C

unless otherwise specified

76XXA
PARAMETER

SYMBOL

Input Offset Voltage

Vas

CONDITIONS

Rs';100KO. TA=25'C

2
3

TMIN$TA:::;TMAX

Temperature Coefficient of Vas

.lVos/.H

Rs';100.KO

10

Input Offset Current

los

TA=25'C
.lTA=CI2
.lTA=M2

0.5

TA=25'C
.lTA=C
.HA=M

1.0

Input Bias Current

IBIAS

Common Mode voltage Range
I Except ICL7612,

VeMA

Extended Common Mode Voltage
Range IICL7612 Only,

VCMP

Large Signal Voltage Gain

0.5

50
400
4000

1.0

0.5

50
400
4000

1.0

±5.3
+5.3
-5.1
+5.3
-4.5

+5.3

+5.3

+5.3
-5.1
+5.3
-4.5

+5.3
·51
+5.3
-4.5

(1) 10 = 10"A, RL = lMn
±4.9
TA = 25'C
±4.B
.lTA = C
± 4.7
.lTA = M

±4.9
±4.8
±4.7

±4.9
±4.8
± 4.7

'0 = 100"A. RL = lOOk!!
TA = 25'C
.lTA = C
.lTA = M

4.5

±4.9
±4.8
±4.5

±4.9
±4.B
:t 4.5

(1) 10 = 1mA, RL = 10k!!
± 4.5
TA = 25'C
± 4.3
.lTA = C
±4.0
.lTA =.M

±4.5
±4.3
±4.0

±4.5
±4.3
±4.0

± 4.9
± 4.8
:t

mV

MV/'C

25
30
300
800

la=10~A

30
300
800

pA

50
400
4000

pA

±4.4
±4.2
±3.7

V

V

V

Vo=±4.0V, RL =1 Mn

AVDL

GBW

TA::::250C

86
80
74

104

80
75
68

104

80
75
68

104

.lTA=C
.lTA=M
Vo=±4.0V. RL=100kn
la=100MA, TA=25' C,
.lTA=C
.lTA=M

86
80
74

102

80
75
68

102

80
75
68

102

80
76
72

83

76
72
68

83

I

Vo=±4.0V, RL=10kn
la=lmA', TA=25'C
.lTA=C
.lTA=M

I

la=10MA'
IQ=100MA

1,

lo=1mA

76
72
68

0.044
0.48
1.4

1

RIN'
CMRR

PSRR

83

0.044
0.48
1.4

1012

Input Resistance
Common Mode Rejection Ratio

Power Supply Rejection Ratio

15
30
300
800

±4.4
±4.2
±3.7

la=10/-LA

Unity Gain Bandwidth

15
20

5
7

±4.4
±4.2
±3.7

la=100MA

VOUT

76XXD

la-10MA'
la=100MA
io=1mA 1

la=lmA
Output Voltage Swing

76XXB

MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP. MAX. UNITS

dB

0.044
0.48
1.4

MHz

1012

n

Rs';100Kn, la-l0MA '
Rs';100Kil, la=lOOMA
Rs';100Kn, la=l mA '

76
76
66

96
91
87

70
70
60

96
91
87

70
70
60

96
91
87

dB

Rs-S100Kil, la=10MA'
Rs-Sl00Kil, la=100MA
Rs-S100Kn, la=1mA'

BO
80
70

94
86

80
80
70

94
86

80
80
70

94
86
77

dB

1012

77

77

Input Referred Noise Voltage

en

Rs=100n, f=1 KHz

100

100

100

nV!/ Hz

Input Referred Noise Current

In

Rs=100n, f=l KHz

0.01

0.01

0.01

pAIjHZ

Supply Current

Isupp

No Signal, No Load
la=10MA'
la=100MA
la=lmA'

0.01
0.1
1.0

(Per Amplifier)

Channel Separation

VO,IV02

Slew Rate ill

SR

Rise Time 13i

tr

Overshoot Factorl 31

Note: 1. ICl7611, 7612, 7613 only.

2. C
M

0.01
0.1
1.0

0.02
0.25
2.5

0.01
0.1
1.0

0.02
0.25
2.5

mA

AVOL -100

120

120

120

dB

AvaL =1, CL =100pF,
V,N = 8V p- p
la=10MAI'I, RL=lMn
la=100MA, RL=100KO
la=1mAi', RL=10KO

0.016
0.16
1.6

0.016
0.16
1.6

0.016
0.16
1.6

V/MS

VIN=50mV, CL=100pF
la=10MA,", RL=1MO
la=100MA, RL=100KI1
la=1mAi'" RL=10Kn

20
2
0.9

20
2

20
2
0.9

MS

0. 9

VIN-50mV, CL -1 OOpF
la=10MA['I, RL=lMI1
la=100MA, RL=100Kil
la=lmAI'_, RL=10KO

40

5
10
40

5
10
40

= Commercial
=

0.02
0.25
2.5

5
10

Temperature Range: D'C to +7DoC
Milita.ry Temperature Range: -55° C to +125' C

5-78

%

3. ICl7614/15; 39pF from pin 6 to pin 8

ICL761 X/762X
ELECTRICAL CHARACTERISTICS

Vsupp =±1.0V. 10 = 1O/LA. TA = 25°C. unless otherwise specified.
Specs apply to ICL7611/7612/7613 only.

76XXA
PARAMETER

SYMBOL

Input Offset Voltage

Vos

CONDITIONS

MIN.

TYP.

Rs~100Kn.TA=25DC

"Vosl :'T

Input Offset Current

loS

Input Bias Current

IBIAS

MIN

I TYP.

2
3

TMIN~TA~TMAX

Temperature Coefficient of Vos

76XXB
MAX.

Rs~100Kn

10

TA=25 DC
:lTA=C

0.5

TA=25 DC
:'TA=C

1.0

MAX

UNITS

5
7

mV
,tV/DC

15
30
300

0.5

50
500

1.0

30
300

pA

50
500

pA

Common Mode Voltage Range
(Except ICL7612)

VCMA

±O .6

±O .6

V

Extended Common Mode Voltage
Range (ICL7612 Only)

VCMA

+0.6
to
-1.1

+0.6
to
-1.1

V

Output Voltage Swing

Vour

Large Signal Voltage Gain

AYOL

RL=lMn. TA=25 DC
:'TA=C

±0.98
±0.96

±0.98
±0.96

V

Vo=±O.lV. RL=lMn
TA=25 DC
"TA=C

90
80

90
80

dB
MHz

Unity Gain Bandwidth

GBW

0.044

0.044

Input Resistance

RIN

1012

1012

n

Common Mode Rejection Ratio

CMRR

80

80

dB

Power Supply Rejection Ratio

PSRR

Input Referred Noise Voltage

en

Rs~100Kn
Rs~100Kn

80

80

dB

Rs=100n. f=l KHz

100

100

nVV'Hz

Input Referred Noise Current

in

Rs=100n. f=l KHz

0.01

Supply Current
(Per Amplifier)

Isupp

No Signal. No Load

6

Slew Rate

SR

AYOL=l. CL=100pF.
VIN=0.2Vp-p
RL=lMn

0.016

0.016

VII's

Rise Time

tr

VIN=50mV. CL=100pF
RL=lMn

20

20

p.s

VIN=50mV. CL=100pF
RL=lMn

5

5

%

Overshoot Factor

0.Q1
15

6

Note: C = Commercial Temperature Range(ODC to +70 DC); M = Military Temperature Range (-55°C to +125°C).

pAV'Hz
15

p.A

763X/764X
ELECTRiCAL CHARACTERISTICS Vsupp= +5
- OV

TA

= 25°C unless otherwise specified
76XXC

76XXB
PARAMETER

SYMBOL

Input Offset Voltage

Vos

CONDITIONS
AsSl00KII. TA-25'C

~Vos/.H

Input Offset Current

los

AsSl00KII

15

TA-25'C

0.5

~TJ\~C

TA-25'C

ISlAS

1.0

~TA~C
~TA~M

Common Mode Voltage Aange

Output Voltage Swing

VeMA

VOUT

la- l 0"A'

la~100"AI31
lo::::1mAl2i

(1) la _,O"A, AL _1 Mil
TA ~25'C
C.TA=C
C.TA=M
10 = 100"A, AL = 100kll
TA =25'C
C.TA=C
c.TA=M

(3)

(2)10 = lmA, AL = 10kll
TA = 25'C
C.TA=C
c.TA=M
Large Signal Voltage Gain

AVOL

Vo=±4.0V, AL=lMII'll
la~10"A 1 , TA=25' C
.HA=C
~TA~M

Vo=±4.0V. AL =100k1l 131
la~100"A, TA~25' C
~T.=C
~TA=M

Vo=±4.0V. AL =10kll l21
10=1 mA 1 , TA=25° C
~TA=C

~TA"'M

Unity Gain Bandwidth

GBW

Input Resistance

AIN

Common Mode Rejection Ratio

CMAA

Power Supply Aejection Aatio

PSAA

la~10"A

20
25

20

~TA~M

Inp'ut Bias Current

10
15

5
7

TMIN-

:Ea;

-10

a;

100J.lA

102

::J

r--

U

>

~

::J

10

'"

-50

16

-

-25

+25

+50

+75

FREE-AIR TEMPERATURE

Vsupp

:=

-25

0

+25

+50

10f--+--+--+--4-~+-~k-~

t-- I--

~........

.........

75

65
-75

-50

-25

o

+25

+50

w

~
~

..........

o'"z

400

300

>-

~
~

200

>-

.....

+75 +100 +125

FREE·AIR TEMPERATURE -

C

~

<{

100

>

§

II
,I

w

..............

70

1

500

>

........
.........

I--

90

~ 85

""
z
""

r--~~=10~ r--..

~;'::r--,-r- i'.........

"
8

80

o

10

TA '" +25'C
3V ,:;;; Vsupp .;;; l6V

75

-50

0

>

,

16

10

i i!

100

•· .... ·,o=100~

"

\

.....
t- t-

FREQUENCY - Hz

10K

r100K

vsupp '"

o

100

I
lK

,

Ji. ""\
\
I

"t2V

l\

,,

!,

\

~'''''

10K

+25"C

I
- IQ =lmA
--*1 0 =10,uA

I_-::c~ p.'......

lK

5·82

I,~
- ,5V

I I

+75 +100 +

TA

""\

1\

vsCP;--= ' \

I
........

+50

fi

,8V

1\

1

+25

~~

14

vs: p-

~

I

-25

PEAK-TO-PEAK OUTPUT VOLTAG
AS A FUNCTION OF FREQUENC't

12

1

I

!
I!\I
i II
I
I\.i
II

i"-.

FREE--AIR TEMPERATURE _oC

EQUIVALENT INPUT NOISE VOLTAGE
AS A FUNCTION OF FREQUENCY

I

"""-

..........

~""OIlA
80

-

-

10 - 100pA

I-- ~A

95

-75

:;;

+12!

Vsupp = 10V

70

~ 600

95

100

FREQUENCY - Hz

Vsupp "" lOV

+100

o

C

100

=1, rnA

105

I

..
o
;::
~
z

102

POWER SUPPLY REJECTION
RATIO AS A FUNCTION OF
FREE-AIR TEMPERATURE
10

.,

+75 +100 +125

FREE-AIR TEMPERATURE -

85

~~r;6~~J~5

I
-50

+75

COMMON MODE REJECTIOP
RATIO AS A FUNCTION
OF FREE-AIR TE .... PERATURE

~

I--

Your '" 8 VOLTS

+50

FREE-AIR TEMPERATURE -,°C

o
;::

~

+25

-25

_oc

10'f--+--+~rl-~~-+--~~

10 VOL TS

./

0.1
-50

+100 +125

~ :::::::-

1

./

1.0

~

RL "" 10K~2
'o"'lmA

I

90

~

IQ '" 100pA

RL'" lr.'lil_ r--

1

/

'"
>-

r---; :::::::: ~'O=10"A

10

10

u

iii

107 r-~-~---T---'--~-"---'
Vsupp :: l6V
TA "" +25°C
106 f - - + - - + - - + - - + Cc '"

1
-75

0:
::J

'"

LARGE SIGNAL DIFFERENTIAL
VOLTAGE GAIN AND PHASE SHIFT
AS A FUNCTION OF FREQUENCY

I

-

J

:Ea;

--

-/0 - lOIlA

1000

Rl := 1OOKr~
10'" 100pA _

/

100

1

LARGE SIGNAL DIFFERENTIAL
VOLTAGE GAIN AS A FUNCTION
OF FREE-AIR TEMPERATURE

/

V'
V- - -SVOLTS

>-

SUPPLY VOL TAGE - VOL TS

100

'""

10'

1
10

~5 VO~TS

F=
r--

NO LOAD

-

1

I

f
o

1000

)-v-~'0v6LTS

I
-'0"" 1 rnA

~

INPUT BIAS CURRENT AS A
FUNCTION OF TEMPERATURE

~\

••...... ~ ~

lOOK

FREQUENCY - Hz

1M

1011

ICL761X/762X/763X/764X
TYPICAL PERFORMANCE CHARACTERISTICS
MAXIMUM PEAK- TO-PEAK
OUTPUT VOLTAGE AS A
FUNCTION OF FREQUENCY
>
I

16
Vsupp = 10V
10'" lmA

14

t-

>

I Ii,

12

MAXIMUM PEAK-TO-PEAK
VOLTAGE AS A FUNCTION OF
FREE-AIR TEMPERATURE

MAXIMUM PEAK-TO-PEAK
OUTPUT VOLTAGE AS A
FUNCTION OF SUPPLY VOLTAGE
16r---r---r--'--~---'---r--,

14

i---j------t---i- t----t----,V-----i

10

1------1---+--+

!
10

['.;

lY

TA '" 55 C

I

\ 1,\

i\r-.;

TA = +125C----' ~

I I

o

1\
I
~~ J

lOOK

10K

'E"

TA =+25C

10M

FREOUENCY _. Hz

SUPPL y VOLTAGE - VOLTS

MAXIMUM OUTPUT/SOURCE
CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

MAXIMUM OUTPUT
SINK CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

40

I-

a:
a:
::J
u

0

IV

w

U

a:

::J

g

0

I;;
~

::J

o

10

IV

"
::J

"X

,1

"'"

10 '" lmA

1M

I

~

Vsupp '" 10 VOL TS
O~~--~--~~~~~~~~~
-75 -50 -25
0
+25 +50 +75 +100 +125

'

I

L'

/

V

v

" '~_-I
E
I

i:j
a:
a:

::J

"'"

12

10

14

16

10'" , I11A

Vsupp

>
I
w

\

/

>

!oUTPUT

I-

"

~

"0

"
"i.:
2

INPUT

l-

-4

/

25 C

10"'"

mA

C::=
10

---

V

~

"'

10'" lmA-=

o

10

12

~

14

o

16

I

0.1

1.0

10

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

>

>

+25 C

w

w

"~"
0

>

>

I-

l-

::J

i.:

~

I-

o

0

::J

::J

"

"
"i.:

2

2

"
l-

-2

l-

i.:

!;

!;

-4
-6

10
TIME -,us

12
TIME -

5-83

iJS

100

LOAD RESISTANCE - K!.!

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

""~
o

I

!;

-6

-

t-

V

TA

l\.

= 10 VOL TS

=

II

:

10V
10K:!
lOOpF

\

TA

100ilA

SUPPLY VOLTAGE - VOLTS

\

-2

I

RL
CL

=

t----

10

1\

"X

0

0

1.0

0

'"

i

:

r-- t----- ~ ~IO

::J

VOLTAGE FOLLOWER LARGE
SIGNAL PULSE RESPONSE

""~

""'

2

SUPPLY VOLTAGE - VOLTS

'"~

0.1

l-

i.:
I-

v· - v14

10 - 10j.lA

12

"u
"
in

.-

16

I

r----lt-

I-

°c

MAXIMUM PEAK-TO-PEAK OUTPUT
VOLTAGE AS A FUNCTION OF
LOAD RESISTANCE
>

0.0

V

I

FREE·AIR TEMPERATURE _

TIME -

f.lS

ICL761X/762X
APPLICATIONS
Note that in no case is 10 shown. The value of 10 must
be chosen by the designer with rega'rd to fre.quency
response and power dissipation.
SIMPLE FOLLOWER*

PRECISETRIANGLE/SQUARE WAVE GENERATOR
Since the output range swings exactly from rail to rail,
frequency and duty cycle are virtually independent of
power supply variations.

V,N------I

.>---p-----1r------ VOUT

DUTY CYCLE
680kn
WAVEFORM GENERATOR

AVERAGING AC TO DC CONVERTER FOR AID
CONVERTERS SUCH AS ICL7106, 7107, 7109, 7116,
7117.
LEVEL DETECTOR*
1M

*By using the ICL7612 in these applications, the circuits will follow rail to rail inputs.

20k

2.2M

TO

I

SUCCEEDING

+5

V,N

INPUT
STAGE

+5

>---t---,.-j

'---j-+-VOL'

.>-----r----

VOUT

TO CMOS OR
LPTTllOGIC

lOOk ~-.,--I

COMMON

1M

MEDICAL INSTRUMENT PREAMP
PHOTOCURRENTINTEGRATOR
Low leakage currents allow integration times up to
several hours.

Note that AVOL = 2S; single Ni-cad battery operation.
Input current (from sensors connected to patient)
limited to < SIJ.A under fault conditions.
1M
lOOk, 1%

'"F+

50Ok,l%

lOOk

INPUT

Vou'r

50k

VOUT

lM,l%
V+

-=

lOOk
10Ok,l%
IM

5·84

lM,l%
V-

ICL761X/762X/763X/764X
FIFTH ORDER CHEBYSHEV MULTIPLE FEEDBACK LOW PASS FILTER
The low bias currents permit high resistance and low
capacitance values to be used to achieve low
frequency cutoff. fe = 10Hz, AVOL = 4, Passband ripple
= 0.1 dB.
O.2.uF

lOOk

680k

51k

INPUT

1M

O.lpF

OUTPUT
1M

*Note that sma!1 capacitors (25-50pFI may be needed for stability in some cases.
SECOND ORDER BIQUAD BANDPASS FILTER

Vas NULL CIRCUIT

Note that 10 on each amplifier may be different.
AVOL= 10, Q = 100, f 0 = 100Hz.

16k

16k

>----VOUT

V,N

1.6M

160k

160k

r--+-VOUT

BURN-IN AND LIFE TEST CIRCUIT

UNITY GAIN FREQUENCY COMPENSATION

+8V

TA '" +125'C

>---1>--"""'--r-

1.Sk
V,N

:------1

"FOR ICL7614!15
NOTES:
1. FOR DEVICES WITH EXTERNAL COMPENSATION,
USE 33pF.
2. FOR DEVICES WITH PROGRAMMABLE STANDBY
CURRENT, CONNECT 10 PIN TO V- (to " 'rnA
MODE).

5-85

I'00PF

V OUT

RL '" 10k FOR 10 '" 1rnA
lOOk FOR 10 '" lQOpA
1M FOR 10 '" lOIJA

ICL761X/762X/763X/764X
CHIP TOPOGRAPHY

BIAS/COMP

OFFSET
-INPUT

761X

.076 IN.
(1.93 MM)

OFFSET.

.077 IN.
(1.95 MM)

-IN.
+IN.
OFFSET.

OFFSET.

762X

5-86

ICL761X/762X/763X/764X
CHIP TOPOGRAPHY (Cant.)

1 4 - - - - - - - .084 IN. _ _ _ _ _~~I
(2.13 MM)

OUT.
+IN.
-IN •

.079 IN.
(2.00 MM)

lac SET

OUTc
-INc

+INc

763X
.080 IN.

~-----(2.03 MM) - - - - - . !

-INc OUTc OUT. -IN,
+INc

+IN •

.086 IN.
(2.18MM)

-INo
-IN.

aUTo OUT. -IN.

764X

5-87

+IN.

ICL7850
Chopper Stabilized
Operational Amp'lifier
FEATURES
• Extremely low input offset voltage - 1p.Vover
temperature range
.
• Low long-term and temperature drifts of input
offset voltage
• Low DC input bias current - 10pA
• Extremely high gain, CMRR andPSRR
min 120dB
• High slew rate - 2.SV/p.s
• Wide bandwidth - 2MHz
• Internally compensated for unity-gain operation
• Very low intermodulation effects (open loop phase
shift < 10° @ chopper frequency)
• Clamp circuit to avoid overload recovery problems
and allow comparator use
• Extremely low chopping spikes at input and
output

GENERAL DESCRIPTION
The ICL76:50 chopper-stabilized amplifier isa highperformance device which offers exceptionally low offset voltage and input-bias parameters, combined with
excellent bandwidth and speed characteristics. Intersil's unique CMOS approach to chopper-stabilized
amplifier design yields a versatile precision component which can replace more expensive hybrid or
modular parts, while at the same time out-performing
them and other monolithic devices.

The chopper amplifier achieves its low offset by comparing the inverting and non-inverting input voltages in
a nulling amplifier, nulled by alternate clock phases.
Two external capacitors are required to store the cotrecting potentials on the two amplifier nulling inputs;
these are the only external components necessary.
The clock Oscillator and all the other control circuitry
is entirely self-contained, however the 14-pin version
includes a provision for the use of an external clock, if
required for a particular application. In addition, the
ICL7650 is internally compensated for unity-gain
operation.
ORDERING INFORMATION
TEMP RANGE
O· ·70·C
O· . 70·C

PART
ICL 7650 CPA
ICL 7650 CPO
ICL 7650 CTV

O· . 70·C

PACKAGE
B·Pin Plastic
14·Pin Plastic
a·Pin TO·99
a·Pin Cerdip

ICL 7650 IJA

-20·C· B5·C

ICL 7650 IJO
ICL 7650 lTV

- 20·C· B5·C
-20·C· B5·C
- 55·C . 125·C

14·Pin Cerdip

- 55·C • 125·C

a·Pin TO·99
B·Pin Plastic

ICL 7650 MJO
ICL 7650 MTV
ICL 7650 CPA·1
ICL 7650 CTV·1

O· ·70·C
O· . 70·C

ICL 7650 IJO·1

-20·C· B5·C

ICL 7650 ITV·1
ICL 7650 MTV·1

-20·C· B5·C
- 55·C· 125·C

a·Pin TO·99
14·Pin Cerdip

B·Pin TO·99
a·Pin Cerdip
B·Pin TO·99
a·Pin TO·99

NOTE: By uSing the ICl 7650·1 verSions and connecting CRETN. betler nOise
performance can be attained.

PIN CONFIGURATION
INTlrnBA
EXT elK IN
OSC.
':
CLKOUT'

CEXTB

C

INTER~:~-f
+ IN

o--

>

.....
..

~ +6

w

~

~
o

~
I-

w

>

+4

en

Iii

~ -2r--t--t--t--t--t---1

10K

= 1000;

= 10KIl

II

""

I

lK

OUTPUT WITH ZERO INPUT; GAIN
BALANCED SOURCE IMPEDANCE

'5.

+3r---,---,---,---,---,--,

100

CHOPPING FREQUENCY (CLOCK·OUT) Hz

INPUT OFFSET VOLTAGE
CHOPPING FREQUENCY

w

E

20

::0

0

::0

20

0

u.
u.
0+2

l:>

::§!=a

~!~
gl~

o

!;
...
!

-3 L-_'----'_-1._-L,----'-_...J
10

12

14

TOTAL SUPPLY VOLTAGE - VOLTS

16

i
BROADBAND

8:IE

14

TOTAL SUPPLY VOLTAGE - VOLTS

100

,.......

0

25

-25

AMBIENT TEMPERATURE -

IL

Z 1
o

:IE

:----

r-- r-- ~

-30

-SO

VOLTS

COMMON·MODE INPUT·VOLTAGE RANGE
.. SUPPLY VOLTAGE

~:

~

~

~J

:IE
:::; 7
w

!il

I

r-

-10

~ -20

10

-

.......
::E

TOTAL SUPPLY VOLTAG,E -

I--

L

!;

t:::::-:

1l!i

4

--

V-

<>

1

o

-+-

::0

::0

.>

r--

II:

I

i:l

......~

I

./

I

.i5

/'"

16

o

10

r
100

1K

10K

CHOPPING FREQUENCY (CLOCK·OUn Hz

5-90

2

4

6

TIME· ms

7

8

9

ICL7650
OPEN LOOP GAIN AND PHASE SHIFT
vs. FREQUENCY

OPEN LOOP GAIN AND PHASE SHIFT
vs. FREQUENCY

160

160

140

~

:c

50
120

70

80

Z

...0

w

z

lil

:cCl

tL

60

=

~

0.01

...0

100

....

60

...

60

0

l'\.

-

t-----

100

lK

10K lOOK

0.01

!:i

... /;,

w

CLOCK OUT
LOW

Cl

c

0

!:i
0

>

....
.......=>
=>
0

/

-1

II

-2

'I

en

....
....

If

w

\

+1

\

Cl

c
....

....

CLOCK OUT
HIGH

0

130

.'-

10K lOOK

....
.......=>
=>

1.5

CLOCK OUT
LOW

CLOCK OUT ----"'_\
HIGH

>

0

0.5

90
110

+2

0

>

ro

lK

0

VOLTAGE FOLLOWER LARGE SIGNAL
PULSE RESPONSE'

.......

+2

> +1

""

100

-

70 Cl
W

FREQUENCY Hz

VOLTAGE FOLLOWER LARGE SIGNAL
PULSE RESPONSE'

0

10

0.1

"-

h

1

10

W

\

./

-1

~

\\'-

-2

o

2.5

TIME· .S

0.5

~

1

1.5

TIME· .S

• THE TWO ~IFFERENT RESPONSES CORRESPOND
TO THE TWO PHASES OF THE CLOCK.

P·CHANNEL CLAMP CURRENT
vo. OUTPUT VOLTAGE

N·CHANNEL CLAMP CURRENT
vo. OUTPUT VOLTAGE.
l00.A

l00,A

10~

....

....
z
WW
za:
za:

c=>
:z:U

v-

10,A

1~

....

z

l00nA

I

za:

Z=>

C (.)

10nA

:t ....~

InA

:z: ...

u'"
'lE

InA
Zc
....
U l00pA

1,A

i&I~ 100nA

10nA

/

(.) l00pA

. r---

10pA

.-

lpA
+0.8

+0.6

+0.4

+0.2

r---

10pA

r--- 1/
I

lpA

o

-0.8

OUTPUT VOLTAGE AV-

-0.6

-0.4

-0.2

OUTPUT VOLTAGE AV+

5·91

en
W
a:

'-

FREQUENCY Hz

en

V

40 _RL = 10K
CE[XT = [1.0.

=

0.1

50

A

Z

w

130~

RL
10K
CEXT
O.l.F

[\.

120

0

en
110w
en
c

w

40

...
OJ

0

90

....

f3
a:

~ 100

0
0

,

140

III

o

Ii:
~

en
W
en
c

...:z:

.O~OIl..

ICL7650

the capacitive circuitry. The outside foil, where
available, should be connected to CRETN (or V-).

TEST CIRCUIT
R2

OUTPUT CLAMP
The OUTPUT CLAMP pin allows reduction of the
overload recovery time inherent with chopper-stabilized amplifiers. When tied to the inverting input pin, or
summing junction, a current path between this pOint
and the OUTPUT pin occurs just before the device output saturates. Thus uncontrolled input differential inputs are avoided, together with the consequent charge
build-up on the correction-storage capacitors. The output swing is slightly reduced.
CLOCK

:>.....- - - OUTPUT

O.1I'F EACH

DETAILED DESCRIPTION
AMPLIFIER

II

The block diagram shows the major elements of the
ICl7650. There are two amplifiers, the main amplifier,
and the nulling amplifier; both have offset-null capability. The main amplifier is connected full-time from the
input to the output, while the nulling amplifier, under
the control of the chopping frequency oscillator and
clock circuit, alternately nulls itself and the main
amplifier. The nulling connections, which are MOSFET
back gates, are inherently high impedance, and two external capacitors provide the required storage of the
nu. lIing potentials and the necessary nulling-loop time
constants. The nulling arrangement operates over the
full common-mode and power-supply ranges, and is
also independent of th.e output level, thus giving exceptionally high CMRR, PSRR, and AVOl.
Careful balancing of the input switches, and the inherent balance of the input circuit, minimizes chopper
frequency charge injection at the input terminals, and
also the feed forward-type injection into thecompensation capacitor, which is the main cause of output
spikes in this type of circuit.

The ICl7650 has an internal oscillator giving a chopping frequency of 200 Hz, available at the CLOCK OUT
pin on the 14-pin devices. Provision has also been
made for the use of an external clock in these parts.
The INT/EXT pin has an internal pull"up and may be left
open for normal operation, but to utilize an external
clock this pin must be tied to V- to disable the internal clock. The external clock signal may then be applied to the EXT. CLOCK IN pin. At low frequencies, the
duty cycle of the external clock is not critical, since an
internal divide-by-two provides the desired 50% switching duty cycle. However, since the capacitors are
charged only when· EXT ClK IN is HIGH, a 50-80%
positive duty cycle is favored for frequencies above
500Hz to ensure that any transients have time to settle
before the capacitors are turned OFF. The external
clock should. swing between V+ and GROUND for
pOwer supplies up to ±6V, and between V+ and V+
-6V for higher supply Voltages. Note that a signal of
about 400Hz will be present at the EXT ClK IN pin with
INT/EXT high or open. This is the internal clock signal
before the divider.
In those applications where a strobe signal is
available, an alternate approach to avoid capacitor
misbalancing during overload can be used. If a strobe
signal is connected to EXT ClK IN so that it is low during the time that the overload signal is applied to the
amplifier, neither capacitor will be charged. Since the
leakage at the capacitor pins is quite low at room
temperature, the typical amplifier will drift less than
10JLV/sec, and relatively long measurements can be
made with little change in offset.

INTERMODULATION
Previous chopper-stabilized amplifiers have suffered
from intermodulation effects between the chopper frequency and input signals. These arise because the
finite AC gain of the amplifier necessitates a small AC
signal at the input. This is seen by the zeroing circuit
as an error signal, which is chopped and fed back, thus
injecting sum and difference frequencies and causing
disturbances to the gain and phase vs. frequency
BRIEF APPLICATION NOTES
characteristics near the chopping frequency. These effects are sustantially reduced in the ICl7650 by
COMPONENT SELECTION
feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current, in '. The two required capacitors, CEXTA and CEXTB, have
optimlJm values depending on the clock or chopping
such a way as to cancel that portion of the input signal
frequency. For the preset internal clock, the correct
due to finite AC gain. Since that is the major error conv.alue is 0.1JLF, and to maintain the same relationship
tribution to the ICl7650, the intermodulation and
between the chopping frequency and the nulling time
gain/phase disturbances are held to very low values,
constant this value should be scaled approximately in
and can generally be ignored.
proportion if an external clock is used. A high-quality
CAPACITOR CONNECTION
film-type capacitor such as mylar is p'referred,
although a ceramic or other lower-grade capacitor may
The null-storage .capacitors should be connected to
the CEXTA and CEXTB pins, with a common connection
prove suitable in many applications. For quickest seUlto the CRETN pin (in the case of 14-pin devices) or the
ing on initial turn-on, low dielectric absorbtion capaciV- pin (in the case of the 8-pin devices). This oonnec- tors (such as poly propylene) should be used. With
ceramic capacitors, several seconds may be . required
tion should be made directly by either a separate wire
or PC trace to avoid injecting load current IR drops into to settle to 1JLV.
5-92.

ICL7650
temperature, thermoelectric voltages typically around
STATIC PROTECTION
0.11lV/oC, but up to tens of IlV/oC for some materials,
All device pins are static-protected by the use of input
will be generated. In order to realize the extremely low
diodes. However, strong static fields and discharges
offset voltages that the chopper amplifier can provide,
should be avoided, as they can cause degraded diode
junction characteristics, which may result in increased it is essential to take special precautions to avoid
temperature gradients. All components should be
input-leakage currents.
'enclosed to eliminate air movement, especially that
caused by power-dissipating elements in the system.
LATCH·UP AVOIDANCE
Low thermoelectric-coefficient connections should be
Junction·isolated cMOS circuits inherently include a used where possible and power supply voltages and
parasitic 4-layer (p-n-p-n) structure which has power dissipation should !;Ie kept to a minimum. Highcharacteristics similar to an SCA. Under certain cir- impedance loads are preferable, and good separation
cumstances this junction may be triggered into a low- from surrounding heat-dissipating elements is
impedance state, resulting in excessive supply cur- advisable.
rent. To avoid this condition, no voltage greater than
0.3V beyond the supply rails should be applied to any
pin. In general, the amplifier supplies must be GUARDING
established either at the same time or before any input Extra care must be taken in the assembly of printed cirsignals are applied. If this is not possible, the drive cir- cuit boards to take full advantage of the low input curcuits must limit input current flow to under 1mA to rents of the ICL7650. Boards must be thoroughly
avoid latchup, even under fault conditions.
cleaned with TCE or alCOhol and blown dry with compressed air. After cleaning, the boards should be
coated with epoxy or silicone rubber to prevent
OUTPUT STAGE/LOAD DRIVING
contamination.
The output circuit is a high-impedance stage (approximately 18kO), and therefore, with loads less than this Even with properly cleaned and coated boards,
the chopper amplifier behaves in some ways like a leakage currents may cause trouble, particularly since
transconductance amplifier whose open-loop gain is the input pins are adjacent to pins that are at supply
proportional to load resistance. For example, the open- potentials. This leakage can be significantly reduced
loop gain will be 17dB lower with a 1kO load than with a by using guarding to lower the voltage difference be10kO load. If the amplifier is used strictly for DC, this tween the inputs and adjacent metal runs. Input guarlower gain is of little consequence, since the DC gain ding of the 8-lead TO-99 package is accomplished by
is typically greater than 120dB even with a 1KO load. using a 10-lead pin circle, with the leads of the device
However, for wideband applications, the best frequen- formed so that the holes adjacent to the inputs are
cy response wll1 be achieved with a load resistor of empty when it is inserted in the board. The guard,
10K or higher. This will result in a smooth 6dB/octave which is a conductive ring surrounding the inputs, is
response from 0.1 Hz to 2M Hz, with phase shifts of less connected to a low impedance pOint that is at approxthan 10 ° in the transition region where the main imately the same voltage as the inputs. Leakage currents from high-voltage pins are then absorbed by the
amplifier takes over from the null amplifier.
guard.

THERMO·ELECTRIC EFFECTS
The ultimate limitations to ultra-high precIsion DC
amplifiers are the thermo-electric or Peltier effects
arising in thermocouple junctions of dissimilar metals,
alloys, silicon, etc .. Unless all junctions are at the same

The pin configuration of the 14-pin dual in-line package
is designed to facilitate guarding, since the pins adjacent to the inputs are not used (this is different from
the standard 741 and 101A pin configuration, but corresponds to that of the LM108).

CONNECTION OF INPUT GUARDS

R1
R2
INPUT ~W¥--r--"'Wv---,

OUTPUT

~

EXTERNAL
CAPACITORS

3-

INPUT

v+
OUTPUT

OUTPUT

+

EXTERNAL
CAPACITORS
NOTE:

~ SHOULD BE LOW
R1

+

R2

IMPEDANCE FOR
OPTIMUM GUARDING

·USE R3 TO COMPENSATE FOR LARGE
SOURCE RESISTANCES, OR FOR CLAMP
OPERATION (.88 FIG. 2)

INVERTING AMPLIFIER

FOLLOWER

7v-. : 4~2'
~ ...
.
!>:'"

<0

GUARD

~

BOTTOM VIEW
BOARD LAYOUT FOR INPUT
GUARDING WITH TO-lJ9
PACKAGE

NON-INVERTING AMPLIFIER

5-93

0

OUTPUT,
'181

I

.D~DR.

ICL7650
PIN COMPATIBILITY
The. basic pinout of the 8-pin device corresponds, where
possible, to that of the industry,standard 8-pin devices,
the LM741, LM10t, etc. The null-storing external
capacitors are connected to pins 1 and 8, usually used
for offset null or compensation capacitors, or simply
not connected. The output-clamp pin (5) is similarly used. In the case of the OP-05 and OP-07 devices, the replacement of the offset-null pot, connected between
pins 1 and 8 and V+ , by two capacitors from those pins
to V-, will provide easy compatibility. As for the LM108,
replacement the compensation capacitor between pins
1 and 8 by the two capacitors to V- is all that is
necessary. The same operation, with the removal of any
connection to pin 5, will suffice for the LM101, I'A748,
and similar parts.
The 14-pin device pinout corresponds most closely to
that of the LM108 device, owing to the provision of
"NC" pins for guarding between the input and all other
pins. Since this device does not use any of the extra
pins, and has no provision for offset-nulling, but requires a compensation capacitor, some changes will
be required in layout to convert to the ICL7650.
TYPICAL APPLICATIONS
Clearly the applications of the ICL7650 will mirror
those of other op. amps. Thus, anywhere that the performance of a circuit can be significantly improved by
a reduction of input-offset voltage and bias current, the
ICL7650 is the logical choice. Basic non-inverting and
inverting amplifier circuits are shown in" Figs. 2 and 3.
Both circuits can use the output clamping circuit to
enhance the overload recovery performance. The only
limitations on the replacement of other op. amps by'

the ICL7650 are the supply voltage (± 8V max.) and the
output drive capability (10kO load for full swing). Even
these limitations can be overcome using a simple
booster circuit, as shown in Fig. 4, to enable the full
output capabilities of the LM741 (or any other standard
device) to be combined with the input capabilities of
the ICL7650. The pair form a composite device, so loop
gain stability, when the feedback network is added
should be watched carefully.
'
Fig. 5 shows the use of the clamp circuit to advantage
in a zero-offset comparator. The usual problems in using a chopper stabilized amplifier in this application
are avoided, since the clamp circuit forces the inverting input to follow the input signal. The threshold input must tolerate the output clamp current '" VIN/R
without disturbing other. portions of the system.
Normal logarithmic amplifiers are limited in dynamic
range in the voltage-input mode by their input-offset
voltage. The built-in temperature compensation and
convenience features of the ICL8048 can be extended
to a voltage-input dynamic range of close to 6 decades
by using the ICL7650 to offset-null the ICL8048, as
shown in Fig. 6. The same concept can also be used
with such devices as the HA2500 or HA2600 families of
op amps. to add very low offset voltage capability to
their very high slew rates and bandwidths. Note that
these circuits will also have their DC gains, CMRR, and
PSRR enhanced.
Mixing the ICL7650 with Circuits operating at ±15V
supplies requires the provision of a lower voltage.
Although this can be met fairly easily, a highly efficient
voltage divider can be built using the ICL7660 voltage
converter circuit 'backwards'. A suitable connection is
shown in Fig. 7.

INPUT " > - - - - - - - - - l
INPUT">-----"Mr~-I

>---o--+- OUTPUT

>-........--_OUTPUT

R,

R,

R3 + (R, I/R2I ~ 100kO
FOR FULL CLAMP EFFECT

NOTE: R,lfR2 1NDICATES THE
PARALLEL COMBINATION
OF R, AND R2

(R11IR2)

~

loa

FOR FULL CLAMP EFF'£CT

FIG. 3 INVERTING AMPLIFIER WITH (OPTIONAL)
CLAMP

FIG. 2 NON INVERTING AMPLIFIER WITH
(OPTIONAL) CLAMP
+7.5V

OUT

y,N>----~-I
>----yOUT

10k

FIG. 4 USING 741 TO BOOST OUTPUT DRIVE
CAPABILITY

FIG. 5 LOW OFFSET COMPARATOR

5-94

ICL7850
TYPICAL APPLICATIONS (Continued)

I

Ro

I

".,,_J

.1 OUTPUT

(LOW T.e.)

.. _,J. ...

10kf1

FIG. 7 SPLITTING + l5V WITH ICL7660.
SAME FOR -15V. >95% EFF.

FIG. 6 ICLS04S OFFSET NULLED BY ICL7650

FOR FURTHER APPLICATIONS ASSISTANCE, SEE A053 AND R017

v-

+IN

-IN
CEXTA
CEXTB

INT/EXT
EXT ClK IN

0.061"

OUTPUT
CLAMP

INT ClK OUT
OUTPUT

v+

......1--------0.082"-----~..
~1

5·95

ICL7652
Chopper-Stabilized
Operational Amplifier

respect to time and temperature. It is similar to INTERSIL's
ICL765D but offers improved noise performance and a wider
common-mode input voltage range. The bandwidth and slew
rate are reduced slightly.

FEATURES
• Extremely low input offset voltage-1/N over temperature range
• Ultra low long·term and temperature drifts of input
offset voltage (100nV/vmonth, 10nV/oC)
• Low DC input bias current-15pA
• Extremely high gain, CMRR and PSRR-min 110dB
• Low input noise voltage-O.2/LVp,p (DC-1 Hz)
• Internally compensated for unity·gain operation
• Very low intermodulation effects (open·loop phase
shift < 2°@chopper frequency)
• Clamp circuit to avoid overload recovery problems
and allow comparator use
• Extremely low chopping spikes at input and output

IJ
.

INTERSIL's unique CMOS chopper-stabilized amplifier circuitry is user-transparent, virtually eliminating the traditional
chopper amplifier problems of intermodulation effects, chop·
ping spikes, and overrange lock-up.
The chopper amplifier achieves its low offset by comparing
the inverting and non-inverting input voltages in a nulling
amplifier, nulled by alternate clock phases. Two external
capacitors are required to store the correcting potentials on
the two amplifier nulling inputs; these are the only external
components necessary.

GENERAL DESCRIPTION
The ICL7652 chopper-stabilized amplifier offers exceptionally low input offset voltage and is e)Vos

Input Bias Current
(Doubles every 10·C above
about 60·C)

ISlAS

TT""

Input Offset Current

los

Input Resistance

RIN

= + 25·C, Test Circuit (unless otherwise specified)
LIMITS
MIN

TYP
±O.?
± 1.0

Operating Temperature
Range (Note 1)
TA = + 25·C
O·C< TA < + 70·C
-20·C
Ii;

0

8

8

10

12

14 16

5

~

4

3

III

6

-

!I.!

z

4

-

0

Co

6.

2

r\.

N

:l:

60%

2
70%

10

012345678
EACH SUPPLY VOLTAGE (+ AND-)

6

10Hz p.p Noise Voltage Voltage
vs Chopping Frequency

~

o

0'--"--.1.--'---'--'--'--'---'

4

Input Offset Voltage vs
Chopping Frequency .

tJ>

II.
II.

---

I--

2

:I!

75 100 125

CI

:I!
:I!

8

50

TOTAL SUPPLY VOLTAGE (V)

10

71-+-+--+-+-1-+'--1>"'..1
6 I-+-+--+-+~.

III

z
o

25

AMBIENT TEMPERATURE (OC)

Common·Mode Input Voltage
Range vs Supply Voltage

~

I'-. r-....

~-30

o
6
8 10 12 14 16
TOTAL SUPPLY VOLTAGE (V)

-

0

i-20

4

o

2

:I!

o

..-

/

V

0-10

::::l

tJ>

Q

4

::::l

l - t--

I

~

II

6

~

III

"....

III

!Z

~

111111\
80%
100

-

o

1k

10k

10

CHOPPING FREQUENCY (CLOCK OUT)

100

-

1k

10k

CHOPPING FREQUENCY (CLOCK OUT)

% parameter is EXT elK in duty cycle

Broadband Noise Balanced
Source Impedance = 1kll
Gain =1000
CEXT = 0.11'F

Clock Ripple Referred to tl}e
Input vs Temperature

Broadband Noise Balanced
Source Impedance = 1kll
Gain=1000
CEXT = 1.01'F

1000

:;;-

CEXT

~ 100

......

0.1~F-

e

..J

ii2

....::::l

...!:;;!l;

...;!l;

5

e +5

0

III

0

~ -5

III
II.
II.
III

-5

Q

10

~

'"

Q

II:

II:

9o

CEXT

Co

1~F

BROADB~ND NOISE ~

Q.

o
25

I
50

Av

-1

000

75

III

II:

II:

~

~

I
100

125

TEMPERATURE (OC)

150

2

3

4

5

TIME (ms)

5-98

6

7

8

2345678
TIME (ms)

ICL7652
TYPICAL OPERATING CHARACTERISTICS (Continued)

Voltage Follower Large Signal
Pulse Response'

~

2

w

Voltage Follower Large Signal
Pulse Response'
3

C~OC~ ~ ~
OUT
LOW

Ilf

~

>

:>

Il.
I-

-1

>

-2

\ 1"\

II-

:>

0

-2

r-

- 2 0

2

4

6

TIME

8 10 12 14

- 2 0

(~s)

2

:Eo

z

g
g

~

100
80

IpH~SE I I

4

8

40

o

20

I
RL= 10k

Il.

.t"i
6

~

i'\.

0.1

~-

i'\.

I

o
10 12 14

70

" i'\. -.... 1\

60

FREQUENCY (Hz)

'The two different responses correspond to the two phases of the clock.

N·Channel Clamp Current
Output Voltage

P·Channel Clamp Current ys
Output Voltage

YS

I-

100~A

l:!

10~A

~

l~A

:>

:3

10nA

:3U

• ....1

lnA

....I

100pA

z

I-

zw

-

100~A

a::
a::

,

:i!J:

W

Z

 m,."

0

~p

-1

~
~

~
~

-2

I-

:> -3

Il.

~

4

6
8
10 12 14 16
TOTAL SUPPLY VOLTAGE (V)

~

m

III
J:

90

~

110

~

Cl

::m"

10 100 lk 10k lOOk 1M

TIME(~s)

."

J:

50

I'\. MARGIN = 60·

....I

i\~'G1

30

I

Il.

CLOCK
f.---OUT
I-- -

-3

-3

I'\.

iii'120

OUT

,

0

:> -1
Il.

I

:>

0

0

~ ~~H

I-

I-- l\LOW

~

II/cLocK

0

C!J

w

C!J

0

t-

f-

140

~LO~K

~

Open· Loop Gain and Phase
Shilt YS Frequency

ICL7652
DETAILED DESCRIPTION
Amplifier

Clock

The Block Diagram shows the major elements of the ICl7652.
There are two amplifiers, the main amplifier, and the nulling
amplifier; both have offset-null capability. The main amplifier
is connected full-time from the input to the output, while the
nulling amplifier, under the control of the chopping frequency
oscillator and clock circuit, alternately nulls itself and the
main amplifier. The nulling connections, which are MOSFET
back gates, are inherently high-impedance, and two external
capacitors provide the required storage of the nulling potentials and the necessary nulling-loop time constants. The nulling arrangement operates over the full common-mode and
power supply ranges, and is also independent of the output
level, thus giving exceptionally high CMRR, PSRR, and A VOL'

The ICl7652 has an internal oscillator, giving a chopping frequency of 400Hz, available at the CLOCK OUT pin on the
14-pin devices. Provision has also been made for the use of
an external clock in these parts. The INT/EXT pin has an internal pull-up and may be left open for normal operation, but to
utilize an external clock this pin must be tied to V - to disable
the internal clock. The external clock signal may then be applied to the EXT ClOCK"IN pin. An internal divide-by-two provides the desired 50% input switching duty cycle. Since the
capaCitors are charged only when EXT CLOCK IN is high, a
50%-80% positive duty cycle is recommended, especially
for higher frequencies. The external clock can swing between
V+ and.V -. The logic threshold will be at about 2.5V below
V+. Note also that a signal of about 800Hz, with a 70% duty
cycle, will be present at the EXT CLOCK IN pin with INT/EXT
high or open. This is the internal clock signal before the
divider.

Careful balancing of the input switches, together with the inherent balance of the input circuit, minimizes chopper frequency charge injection at the input terminals, and also the
feedforward-type injection into the compensation capacitor,
which is the main cause of output spikes in this type of
circuit.

Intermodulation
Previous chopper-stabilized amplifiers have suffered from
intermodulation effects between the chopper frequency and
input Signals. These arise because the finite AC gain of the
amplifier necessitates a small AC signal at the input. This is
seen by the zeroing circuit as an error Signal, which is
chopped and fed back, thus injecting sum and difference frequencies and causing disturbances to the gain and phase vs
frequency characteristics near the chopping frequency.
These effects are substantially redu<;ed in the ICl7652 by
feeding the nulling circuit with a dynamic current, corresponding to the compensation capacitor current, in such a
way as to cancel that portion of the input signal due to finite
AC gain. Sincelhat is the major error contribution to the
ICl7652, the intermodulation and gain/phase disturbances
are held to very low values, and can generally be ignored.

Capacitor Connection
The null-storage capacitors should be connected to the
CEXTA and CEXTB pins, with a common connection to the
C RETN pin (in the case of 14-pin devices) or the V - pin (in the
case of 8-pin devices). This connection should be made directly by either a separate wire or PC trace to avoid injecting
load current I R drops into the capacitive circuitry. The outside
foil, where available, sho\lld be connected to CRETN (or V -).

In those applications where a strobe signal is available, an
alternate approach to avoid capaCitor misbalancing during
overload can be used. If a strobe signal is connected to EXT
ClK IN so that it is low during the time that the overload
signal is applied to the amplifier, neither capacitor will be
charged. Since the leakage at the capacitor pins is quite low
at room temperature, the typical amplifier will drift less than
10pV/sec, and relatively long measurements can be made
with little change in offset.

BRIEF APPLICATION NOTES
Component Selection
The required capaCitors, CEXTA and CEXTB , are normally in the
range of 0.1pF to 1.01'F. A 1.01'F capacitor should be used in
broad bandwidth circuits if minimum clock ripple noise is desired. For limited bandwidth applications where clock ripple
is filtered out, USing a 0.11'F capaCitor results in slightly lower
offset voltage. A high-quality film-type capacitor such as
mylar is preferred, although a ceramic or other lower-grade
capaCitor may prove suitable in many applications. For
quickest settling on initial turn-on, low dielectric absorption
capacitors (such as poly-propylene) should be used. With
ceramic capacitors, several seconds may be required to
.settle to 11'V.

Static Protection

Output Clamp

All device pins are static-protected by the use of input diodes.
However, strong static fields and discharges should be
avoided, as they can cause degraded diode junction characteristics which may result in increased input-leakage
currents.

The OUTPUT CLAMP pin allows reduction of the overload
recovery time inherent with chopper-stabilized amplifiers.
When tied to the inverting input pin, or summing junction, a
current path between this pOint and the OUTPUT pin occurs
just before the device output saturates. Thus uncontrolled input d.ifferential inputs are avoided, together with the consequent charge build-up on the correction-storage capacitors.
The output swing is slightly reduced.

Junction-isolated CMOS circuits inherently include a parasitic 4-layer (p-n-p-n) structure which has characteristics similar to an SCA. Under certain circumstances this junction
may be trigerred into a low-impedance state, resulting in ex,
cessive supply current. To avoid this condition no voltaae

5-100

Latch·Up Avoidance

ICL7652
greater than 0.3V beyond the supply rails should be applied to
any pin. In general, the amplifier supplies must be estab·
IIshed either at the same time or before any input signals are
applied. If this is not possible, the drive circuits must limit input current flow to under 1mA to avoid latch-up, even under
fault conditions.

enclosed to eliminate air movement, especially that caused
by power-dissipating elements in the system. Low thermo·
electric·coefficient connections should be used where possible and power supply voltages and power dissipation
should be kept to a minimum. High·impedance loads are
preferable, and good separation from surrounding heatdissipating elements is advisable.

Output Stage/Load Driving
Guarding

The output circuit is a high-impedance stage (approximately
18kO), and therefore, with loads less than this the chopper
amplifier behaves in some ways like a transconductance
amplifier whose open· loop gain is proportional to load resistance. For example, the open·loop gain will be 17dB lower
with a 1kO load than with a 10kO load. If the amplifier is used
strictly for DC, this lower gain is of little consequence, since
the DC gain is typically greater than 120dB even with a 1kO
load. However, for wideband applications, the best frequency
response will be achieved with a load resistor of 10kO or
higher. This will result in a smooth 6dB/octave response from
0.1 Hz to 2MHz, with phase shifts of less than 2· in the transition region where the main amplifier takes over from the null
amplifier.

Extra care must be taken in the assembly of printed circuit
boards to take full advantage of the low input currents of the
ICL7652. Boards must be thoroughly cleaned with TCE or
alcohol and blown dry with compressed air. After cleaning,
the boards should be coated with epoxy or silicone rubber to
prevent contamination.
Even with properly cleaned and coated boards, leakage currents may cause trouble, particularly since the input pins are
adjacent to pins that are at supply potentials. This leakage
can be Significantly reduced by using guarding to lower the
voltage difference between the inputs and adjacent metal
runs. Input guarding of the 8 lead TO-99 package is accomplished by using a 10 lead pin circle, with the leads of the
device formed so that the holes adjacent to the inputs are
empty when it is inserted in the board. The guard, which is a
conductive ring surrounding the inputs, is connected to a
low·impedance point that is at approximately the same voltage as the inputs. Leakage currents from high·voltage pins
are then absorbed by the guard.

Thermo-Electric Effects
The ultimate limitations to ultra-high precision DC amplifiers
are the thermo-electric or Peltier effects arising in thermocouple junctions of dissimilar metals, alloys, silicon, etc.
Unless all junctions are at the same temperature, thermoelectric voltages typically around 0.1pV/·C, but up to tens of
pV/·C for some materials, will be generated. In order to realize
the extremely low offset voltages that the chopper amplifier
can provide, it is essential to take special precautions to
avoid temperature gradients. All components should be

The pin configuration of the 14·pin dual-in-line package is
designed to facilitate guarding, since the pins adjacent to the
inputs are not used (this is different from the standard 741
and 101A pin configuration, but corresponds to that of the
LM108).

CONNECTION OF INPUT GUARDS
INPUT

Q-.JV\I'v-_--.JV\I'v----,

OUTPUT

OUTPUT

Follower

Inverting Amplifier

EXTERNAL
CAPACITORS

v+

R3'

()

~7 8 l '

OUTPUT _ _

.

EXTERNAL~4~2~

OUTPUT

CAPACITORS . ~

R1 R2
Note: R1 + R2

v-

......

Should be low
impedance for
optimum guarding
Non·lnverting Amplifier

(0.'>

".. ~~

GUARD

~

BonOMVIEW

Board Layout lor Input
Guarding with,'TO·99 Package

'Use R3 to compensate for large source resistances, or for clamp operation (see Figure 2)

5-101

Ii

ICL7652
PIN COMPATIBILITY
The basic pinout of the 8-pin device corresponds, where
possible, to that of the industry-standard 8-pin devices, the
LM741, LM101, etc. The null-storing external capacitors are
connected to pins 1 and 8, usually used for offset-null or compensation capacitors, or simply not connected. The outputclamp pin (5) is similarly used. In the case of the OP-05 and
OP-07 devices, the replacement of the offset-null pot, connected between pins 1 and 8 and V +, by two capacitors from
those pins to V-, will provide easy compatibility. As for the
LM108, replacement of the compensation capacitor b.etween
pins 1 and 8 by the two capacitors to V - is all that is
necessary. The same operation, with the removal of any connection to pin 5, will suffice for the LM101, I'A748, and similar
parts.

clamping circuit to enhance the overload recovery performance. The only limitations on the replacement of otheropamps by the ICL7652 are the supply vo!tage (± 8V max) and
the output drive capability (10kO load for full swing). Even
these limitations can be overcome using a simple booster circuit, as shown in Figure 4, to enable the full outputcapabilities of the LM741 (or any other standard device) to be combined with the inpulcapabilities of the ICL7652. The pair form
a composite device, so loop gain stability, when the feedback
network is added, should b.e watched carefully.
Figure 5 shows the use of the clamp circuit to advantage in a
zero-offset comparator. The usual problems in using a
chopper-stabilized amplifier in this application are avoided,
since the clamp circuit forces the inverting input to follOW the
input Signal. The threshold input must tolerate the output
clamp current ~ V,N/R without disturbing other portions of
the system.

The 14-pin device pinout corresponds most closely to that of
the LM108 device, owing to the provision of "NC" pins for
guarding between th61 input and all other pins. Since this
device does not use any of the extra pins, and has no provision for offset-nulling, but requires a compensation capacitor, some changes will be required in layout to convert to the
ICL7652.

It is pOSsible to use the ICL7652 to offset-null such high slew
rate and bandwidth amplif.iers as the HA2500 and HA2600
series, as shown in Figure6. The same basic idea can be used
with .Iow-noise bipolar devices, such as the OP-05, and also
with the ICL8048 logarithmic amplifier, to achieve a voltageinput dynamic range of close to 6 decades. Note that these
circuits will also have their DC gains, CMRR and PSRR enhanced. More details on these and other ideas are explained
in application note A053.

TYPICAL APPLICATIONS
Clearly the applications of the ICL7652 wil! mirror those of
o'.her op-amps. Thus, anywhere that the performance of a circuit can be Significantly improved by a reduction of inputoffset voltage and bias current, the ICL7652 is the logical
choice. Basic non-inverting and inverting amplifier circuits
are shown in Figures 2 and 3. Both circuits can use the output

Mixing the ICL7652 with circuits operating at ± 15V supplies
requires the provision of a lower voltage. Although this can
be done fairly easily, a highly efficient voltage divider can be
built using the ICL7660 voltage converter circuit "backwards".
A suitable connection is shown in Figure 7.

INPUT
INPUT )-J\II;'Ir-+--l
OUTPUT
OUTPUT

Note: R,I1R2 indicates the
parallel combination
of R, and R2

R3+(R1I1 R2)2100kll
FOR FULL CLAMP EFFECT

(R1 I1R2)2100kO

FOR FULL CLAMP EFFECT

Figure 3. Inverting Amplifier with (Optional) Clamp

Figure 2. Non·lnverting Amplifier with (Optional) Clamp

+7.5\1

VOUT

OUT

'----+_v.--< VTH
200knTO 2Mn

Figure 4. Using 741 to Boost Output Drive
Capability

Figure 5. Low Offset Comparator

5-102

Figure 6. HA2500 or 2600 Offset· Nulled
by ICL7652

ICL7652
TYPICAL APPLICATIONS (Continued)

CHIP TOPOGRAPHY

I" v-

0.100 in
(2.540) mm
+IN

-IN
CeXTA

1---<+15V
10,llF

CeXTS

1-_-.+7.5V
10,uF

I--+-.ov

0.096 in
(2.440)mm

INT/EXT
EXT elK IN

Figure 7. Splitting + 15V with ICL7660 at > 95% efficiency.
Same for -15V.
For further applications assistance, see A053 and R017

OUTPUT
CLAMP

INTClKOUT

~------~~~--~.--~

5·103

ICL7660
Monolithic MAXCMOS™
Voltage Converter

GENERAL DESCRIPTION

FEATURES
• Simple Conversion of +5V Logic Supply to ±5V
Supplies
• Simple Voltage Multiplication (VOUT = (-,-)nVIN)
• 99.9% Typical Open Circuit Voltage Conversion
Efficiency
• 98% Typical Power Efficiency
• Wide Operating Voltage Range 1.5V to 10.0V
• Easy to use - Requires only 2 External NonCritical Passive Components

APPLICATIONS
•
•
•
•

On Board Negative Supply for up to 64 Dynamic RAMs.
Localized !,"Processor (8080 type) Negative Supplies
Inexpensive Negative Supplies
Data Acquisition Systems

PIN CONFIGURATIONS

v+ (and CASE)

The Intersil ICL7660 is a monolithic MAXCMOSTM power
supply circuit which offers unique performance advantages
over previously available devices. The ICL7660 performs the
complete supply voltage conversion from positive to
negative for an input range of +1.5V to +10.0V, resulting in
complementary output voltages of -1.5 to -10.0V with the
addition of only 2 non-critical external capacitors needed for
the charge pump and charge reservoir functions. Note that
an additional diode is required for VSUPPL Y >6.5V.
Contained on chip are a series DC power supply regulator,
RC oscillator, voltage level translator, four output power
MaS switches, and a unique logic element which senses the
most negative voltage in the device and ensures that the
output N-channel switches are not forward biased. This
assures latch-up free operation.
The oscillator, when unloaded, oscillates at a nominal
frequency of 10kHz for an input supply voltage of 5.0 volts.
This frequency can be lowered by the addition of an external
capacitor to the "osc" terminal, or the oscillator may be
overdriven by an external clock.
The "LV" terminal may be tied to GROUND to bypass the
internal series regulator and improve low voltage (LV)
operation. At medium to high voltages (+3.5 to +10.0 volts),
the LV pin is left floating to prevent device latch up.

(outline dwg PAl

(outline dwg TV)

ORDERING INFORMATION
PART NUMBER
ICL7660CTV
ICL7660CPA
ICL7660MTV
ICL7660/D

TEMP. RANGE

PACKAGE
TO-99
8 PIN MINI DIP
TO-99
DICE

Typical applications for the ICL7660 will be data acquisition
and microprocessor based systems where there is a +5 volt
supply available for the digital functions and an additional-5
volt supply is required for the analog functions. The ICL7660
is also ideally suited for providing low current, -c5V body bias
supply for dynamic RAMs.

BLOCK DIAGRAM
r-------------~------------~------~-------------------ov+

,..-------------------0 CAP +

Your

osc

LV

=
5-104

ICL7660
ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................................. 10.5V
LV and OSC Input Voltage
(Note 1) ................ -0.3V to (V+ +0.3V) for V+ < 5.5V
(V+ -5.5V) to (V+ +0.3V) for V+ > 5.5V
Current into LV (Note 1) ............ 20p.A forV+> 3.5V
Output Short Duration I, VSUPPL Y S 5.5V) .... Continuous
Power Dissipation (Note 2)
ICL?660CTV .......... . . . . . . . . . . . . . . . . . . . . .. 500mW
ICL7660CPA ................................ 300mW
ICL7660MTV ............................ : ... 500mW

Operating Temperature Range
ICL7660M .......................... -55°C to +125°C
'ICL7660C .............................. O°C to 70°C
Storage Temperature Range ........... -65° C to 150° C
Lead Temperature
(Soldering, 10 sec.) ............ , ................ 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS
SYMBOL

PARAMETER

1+

Supply Current

V+Hl

Supply Voltage Range - Hi
(Ox out of circuit) (Note 3)

V' = 5V. TA = 25°C. Case = O. Test Circuit Figure 1 (unless otherwise Ilpecified)

LIMITS
TYP. MAX.

MIN.

170

UNIT

TEST CONDITIONS
RL =.,

p.A

3.0

500
6.5

3.0
1.5

5.0
3.5

V

-55°C S TA S 125°C. RL = 10kfl. LV Open
MIN:S TA S MAX. RL = 10kfl. LV to GROUND

O°C S TA S 70°C. RL = 10kfl. LV Open

V
V

V+L1

Supply Voltage Range - La
(Ox out of circuit)

V+H2

Supply Voltage Range - Hi
(Ox in circuit)

3.0

10.0

V

MIN S TA s MAX. RL = 10kfl. LV Open

V+L2

Supply Voltage Range - Lo
(Ox in circuit)

1.5

3.5

V

MIN

100
120

fl

lOUT = 20mA. T A = 25° C

fl

lOUT =20mA. -20°C:S TA S +70°C
lOUT = 20mA. -o5°C s TA s +125°e (Note 3)

55

Output Source Resistance

ROUT

fose
PEf

Oscillator Frequency
Power Efficiency

VOUT Ef

Voltage Conversion Efficiency

Zose

Oscillator Impedance

TA

s

MAX. RL = 10kfl. LV to GROUND

150

fl

300

fl

V+ = 2V. lOUT = 3mA. LV to GROUND
-20°C s TA s +70 0 e

400

fl

V+ = 2V. lOUT = 3mA. LV to GROUND. -o5°e s
TA s +125°C. Ox in circuit (Note 3)

kHz
%
%
Mfl
kfl

10
95
97

s

98
99.9
1.0
100

RL = 5kfl
RL =.,
V+ = 2 Volts
V

= 5 Volts

Notes: 1. Connecting any input terminal to voltages greater than V+ or less than GROUND may cause destructive latch up. It is recommended
that no inputs from sources operating from external supplies be applied prior to "power up" of the ICl7660.
2. Derate linearly above 50°C by 5.SmW/oC.
3. ICl7660M only.

TYPICAL PERFORMANCE CHARACTERISTICS
OPERATING VOLTAGE AS A
FUNCTION OF TEMPERATURE

(Circuit of Figure 1)

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE

S 10K

iA

w

o
z

~25ob=

OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF TEMPERATURE

§: 350
z0(
t;

~

~1000
w
a:

250

;;;
~ 200
~

w

oa:

!5

~

~ 100 ~
~

:J
~ 100

o

I"'--.

§

"-

~

o

10

o

1

2
3
5
6
SUPPLY VOLTAGE (v+)

5-105

lOUT = 1 mA

~ 300

150

50 I"""

o

-

-50" -25"

...-

/

/>::~+2V

...v+

~

5V

0" +25°' +50" +75"+100" +125"
TEMPERATURE (OC)

ICL7660
FREQUENCY OF OSCILLATION
AS A FUNCTION OF
EXTERNAL OSC. CAPACITANCE

POWER CONVERSION EFFICIENCY AS A
FUNCTION OF OSC. FREQUENCY

ll00

~ 98

o'"
it"'
z

lOUT

lOUT

~_

~

-

I
-15mA

8

lK

~ 100
~
o

10K

o

100

1000

"'-,
t'-....

8
6
-50 -25

-3

!: 100 ,.......
t

~

90
80

r--...

Note that the curves on the right
include in the supply current that current fed directly into the load I RL I from
V+ I see Figure 11. Thus, approximately half the supply current goes
directly to the positive side of the load,
and the other half, through the
ICL7660, to the negative side of the
load. Ideally, VOUT ~ 2 VIN, Is ~ 2 IL, so
V,N • Is ~ VOUT • IL.

SLOPE 55D
20 30 40 50 60 70
LOAD CURRENT lL(mA)

80

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT
+2

TA ~ +2h::
Y+=·2Y

'" +1

~

40

Z

30

8

NOTE 4.

\

\
\

\'

ffi
...~

./

0_1

-2

........

V

/

V

20
30
40
50
LOAD CURRENT IL (rnA)

~

...'"

70 I- TA = +25·C

o

50

y+ = +2.0Y

60

Z

30

8

20

--

.........

/

.....

/

/

Cosc~

~YOUT
LY

c,-

~------~(2~.:1:~·~~------~
Figure 2: Chip Topography

5·106

7J

10.0

~

m

~

..e

OmA
1.5
3.0 4.5 6.0
7.5
LOAD CURRENT IL (rnA)

RL

NOTES: 1. For large value of Casc (>1000pF) the values of C,
and C2 should be increased to 100!,F.
2. Ox is required for supply voltages greater than 6.5V
@ -55° ,,; TA ,,; +70°C; refer to perjormance curves
for additional information.
Figure 1: ICL7660 Test Circuit

1 2.0

V

1

*

!iin

4.0

I

Ox

~

14.0

2,()

I

T
r*
, ....
,

16.0

V

------l

-

~

8.0 3'
6.0 ~
_

Is V+

I
I

o

il

~

r--------~~_o(+5Y)

I
I

60

20.0 '"
c:
18.0

y+

CI
10IJF _

"+

303'
~
TA = +25 c C - 20 Z
10 ~
Y+i+ 5Y

!: 100
> 90 ri---...
.............
!iw 80

o

023456
LOAD CURRENT IL (rnA)

40

I-

10

11:

........ ~ --s;.rPEI15O[

g
5lIn

50 ~

\

/

iii
a: 40
~

~

60

\

/

/

20
10

70

SUPPLY CURRENT POWER CONVERSION
EFFICIENCY AS A FUNCTION OF
LOAD CURRENT

Z

0

"

80 ~

"\

/

60

ffi

>

100 '"
90 ~

r

~

/~

~ 50

1/
10

.........

0 +25 +50 +75 +100 +125
TEMPERATURE-(OC)

SUPPLY CURRENT & POWER CONVERSION
EFFICIENCY AS A FUNCTION OF
LOAD CURRENT

/
V

~

'\

Cosc (pi)

II

-So

>

\r-..

y+ = +5Y

~

10K

j.;

1

-4

o

~

0

\

... 70

...>~ -10
...
:> -2
o

12

ffi
Q

'"~

~

::!...
y+ - 5Y

10 ~AIII+2r?
10
1.0

:

125 b

0
riA =
Y· = +5Y

14

a:

OUTPUT VOLTAGE AS A
FUNCTION OF OUTPUT CURRENT
5

~

a

...

+,+5Y

18

!2
o

> 16

1\

:>

84

lK
OSC. FREQUENCY lose (Hz)

~

\

51a:

86

82
80
100

l:

""

.!2

..........

92

a;

~

= 1 mA-r--.

94

20

N

g

98

Q 90
II)

8a:

;foK

T = +2S o y

UNLOADED OSCILLATOR FREQUENCY
AS A FUNCTION OF
TEMPERATURE

9.0

ICL7660
THEORETICAL POWER EFFICIENCY
CONSIDERATIONS

CIRCUIT DESCRIPTION
The ICL7660 contains all the necessary circuitry to complete
a voltage doubler, with the exception of 2 external capacitors
which may be inexpensive 10/lF polarized electrolytic
capacitors. The mode of operation of the device may be best
understood by considering Figure 3, which shows an
idealized voltage doubler. Capacitor C1 is charged to a
voltage, V+, for the half cycle when switches S1 and S3 are
closed. (Note: Switches S2 and S4 are open during this half
cycle.) During the second half cycle of operation, switches
S2 and S4 are closed, with S1 and S3 open, thereby shifting
capacitor C1 negatively by V+ volts. Charge is then
transferred from C1 to C2 such that the voltage on C2 is
exactly V+, assuming ideal switches and no load on C2. The
ICL7660 approaches this ideal situation more closely than
existing non-mechanical circuits.
In the ICL7660, the 4 switches in Figure 3 are MOS power
switches; S1 is a P-channel device and S2, S3 & S4 are Nchannel devices. The main difficulty with this approach is
that in integrating the switches, the substrates of S3 & S4
must always remain reverse biased with respect to their
sources, but not so much as to degrade their "ON"
resistances. In addition, at circuit startup, and under output
short circuit conditions (VOUT = V+), the output voltage must
be sensed and the substrate bias adjusted accordingly.
Failure to accomplish this would result in high power losses
and probable device latchup.

S1

In theory a voltage multiplier can approach 100% efficiency if
certain conditions are met:
A The drive circuitry consumes minimal power
B The output switches have extremely low ON resistance
and virtually no offset.
C The impedances of the pump and reservoir capacitors
are negligible at the pump frequency.
The ICL7660 approaches these conditions for negative
voltage multiplication if large values of C1 and C2 are used.
ENERGY IS LOST ONLY IN THE TRANSFER OF CHARGE
BETWEEN CAPACITORS IF A CHANGE IN VOLTAGE
OCCURS. The energy lost is defined by:
E = 1/2 C1 (V1 2 - V22)
where V1 and V2 are the voltages on C1 during the pump and
transfer cycles. If the impedances of C1 and C2 are relatively
high at the pump frequency (refer to Fig. 3) compared to the
value of RL. there will be a substantial difference in the
vOltages V1 and V2. Therefore it is not only desirable to make
C2 as large as possible to eliminate output voltage ripple, but
also to employ a correspondingly large value for C1 in order
to achieve maximum efficiency of operation.

DO'S AND DON'TS
1 Do not exceed maximum supply voltages.
2 Do not connect LV terminal to GROUND for supply
voltages greater than 3.5 volts.
3 Do not short circuit the output to V+ supply for supply
voltages above 5.5 volts for extended periods, however,
transient conditions including startup are okay.
4 When using polarized capacitors, the + terminal of C1
must be connected to pin 2 of the ICL7660 and the +
terminal of C2 must be connected to GROUND.
5 Add diode Ox as shown in Fig. 1 for hi-voltage, elevated
temperature applications.

52

VIN~~
I
I
I
I
I

C1

I
I
I

I
I

I
I

I
S31

I

_

+J -': ;
C2

S41~

.

CONSIDERATIONS FOR HI VOLTAGE &
ELEVATED TEMPERATURE

JlJlJL

Figure 3. Idealized Voltage Doubler

This problem is eliminated in the ICL7660 by a logic network
which senses the output voltage (VOUT) together with the
level translators and switches the substrates or S3 & 54 to the
correct level to maintain necessary reverse bias.
The voltage regulator portion of the ICL7660 is an integral
part of the anti-latch up circuitry, however it's inherent
voltage drop can degrade operation at low voltages.
Therefore, to improve low voltage operation the "LV" pin
should be connected to GROUND, disabling the regulator.
For supply voltages greater than 3.5 volts the LV terminal
must be left open to insure latchup proof operation, and
prevent device damage.

The ICL7660 will operate efficiently over its specified
temperature range with only 2 external passive components
(storage & pump capacitors), provided the operating supply
voltage does not exceed 6.5 volts at +70° C and 5.0 volts at
+125°C. Exceeding these maximums at the temperatures
indicated may result in destructive latch-up of the ICL7660.
(Ref: Graph "Operating Voltage Vs. Temperature")
Operation at supply voltages of up to 10.0 volts over the full
temperature range without danger of latch-up can be
achieved by adding a general purpose diode in series with
the ICL7660 output, as shown by "Ox" in the circuit
diagrams. The effect of this diode on overall circuit performance is the reduction of output voltage by one diode
drop (approximately 0.6 volts).

5·107

5

.D~Do:'

ICL7660
TYPICAL. APPLICATIONS
1. Simple Negative Voltage Converter
The majority of applications will undoubtedly utilize the
ICL7660 for generation of negative supply voltages. Figure4
snows typical connections to provide a negative supply
wl'\ere a positive supply is available. A similar scheme may be
employed for supply voltages anywhere in the operating
range of +1.5V to +10.0 volts, keeping in mind, that pin 6 (LV)
is tied to the supply negative (GNDl only for supply voltages
below 3.5 volts, and .that diode Dx must be included for
proper operation at higher voltages and/or elevated
temperatures.

The output characteristics of the circuit in Figure 4 are those
of a nearly ideal voltage source in series with 70 ohms. Thus
for a load current of -10mA and a supply voltage of +5 volts,
the output voltage will be -4.3 volts. The dynamic output
impedance due to the capacitor impedances is approximately
1/wC where
C=C1=C2
giving

1

we

2rr fosc x 10-5

= 3 ohms

for C = 10ILFand fosc = 5kHz (1/2 of oscillator frequency)
'NOTE: 1. VOUT ~ -nY+ FOR
1.5Y" v+" 6.SV
2. VOUT ~ -n(Y+ -VFDX)
FOR 6.5 " v+ " 10.0Y

--:1:..------<0

+

VOUT·

il0~F

Figure 4: Simple Negative Converter

its own pump capacitor,C1. The resultant output resistance
would be approximately

2. Paralleling Devices
Any number of ICL7660 voltage convertors may be
paralleled to reduCe output resistance. The reservoir
capacitor, C2, serves all devices while each device requires

ROUT (of ICL7660l
n (number of devices)

ROUT =

RL

Figure 5: Paralleling Devices

3_ Cascading Devices

defined by:

The ICL7660 may be cascaded as shown to produce larger
negative multiplication of the initial supply voltage, however,
due to the finite efficiency of each device, the practical limit
is 10 devices for light loads. The output voltage is

VOUT = -n (VIN),
where n is an integer representing the number of devices
cascaded. The resulting output resistance would be
approximately the weighted sum of the individual ICL7660
RouT values;

V+

Ox

r"*....,
c>---r-o
L __ ..J

.b..ftC

::tO~F
=

'NOTE: 1. YOUT ~ --nv+ FOR
I.SY s v+" 6.SY
2. VOUT = -n (V+;YFDX) FOR
6.5Y " v+ " 10.0V

Figure 6: Cascading Devices for Increased Output Voltage

5-108

VOUT'

ICL7660
4. Changing the ICL7660 Oscillator Frequency
It may be desirable in some applications, due to noise or
other considerations, to increase the oscillator frequency.
This is achieved by overdriving the oscillator from an external
clock, as shown in Figure 7. In order to prevent possible
device latchup, a 1kO resistor must be used in series with the
clock output. In the situation where the designer has generated the external clock frequency using TTL logic, the addition of a 10kO pullup resistor to Y+ supply is required. Note
that the pump frequency with external clocking, as with
internal clocking, will be 1/2 of the clock frequency. Output
transitions occur on the positive-going edge of the clock.

It is also possible to increase the conversion efficiency of the
ICL7660 at low load levels by lowering the oscillator frequency. This reduces the switching losses, and is achieved
by connecting an additional capacitor, Cos e , as shown in
Figure 8. However, lowering the oscillator frequency will
cause an undesirable increase in the impedance of the pump
(C,) and reservoir (C,) capacitors; this is overcome by increasing the values of C, and C2 by the same factor that the
frequency has been reduced. For example, the addition of a
100pF capacitor between pin 7 (Osc) and Y+ will lower the
oscillator frequency to 1kHz from its nominal frequency of
10kHz (a multiple of 10), and thereby necessitate a corresponding increase in the value of C, and C, (from 10!,-F to
100!,-F).

v+

Cose

>---..----0

Vour

lC2

1
Figure 7: External Clocking

Figure 8: Lowering Oscillator Frequency

5. Positive Voltage Multiplication

6. Combined

The ICL7660 may be employed to achieve positive voltage
multiplication using the circuit shown in Figure 9. In this
application, the pump inverter switches of the ICL7660 are
used to charge C1 to a voltage level of y+ - YF (where y+ is the
supply voltage and VF is the forward voltage drop of diode
01l. On the transfer cycle, the voltage on C1 plus the supply
voltage (y+) is applied through diode' 02 to capacitor C2. The
voltage thus created on C2 becomes (2Y+) - (2VF) or twice the
supply voltage minus the combined forward voltage dropsof
diodes 01 and 02.
The source impedance of the output (Your) will depend on
the output current, but for y+ = 5 volts and an output current
of 10mA it will be approximately 60 ohms.

Negative Voltage Conversion and
Positive Supply Multiplication
Figure 10 combines the functions shown in Figures 4and 9 to
provide negative voltage conversion and positive voltage
multiplication simultaneously. This approach would be, for
example, suitable for generating +9 volts and -5 volts from an
existing +5 volt supply. In this instance capacitors C1 and C3
perform the pump and reservoir functions respectively for
the generation of the negative voltage, while capacitors C2
and C4 are pump and reservoir respectively for the multiplied
positive voltage. There is a penalty in this configuration
which combines both functions, however, in that the source
impedances of the generated supplies will be somewhat
higher due to the finite impedance of the common charge
pump driver at pin 2 of the device.

y+

y+

VOUT = -(nVIN-VFDX)

YOUT =

(2Y+) - (2VF)
+-~-..--o

J;C3
0,

c,

NOTE:
0, & 02 CAN BE ANY
SUITABLE DIODE

Figure 9: Positive Voltage Multiplier

-

Your ~ (2Y+)(YFD. HYFD')

Figure 10: Combined Negative Converter and Positive Multiplier
5-109

ICL7660
ICL7660's output does not respond instantaneously to a
change in input, but only after the switching delay. The clr·
cuit shown supplies enough delay to accommodate the
7660, while maintaining adequate feedback. An increase In
pump and storage capacitors is desirable, and the values
shown provides an output impedance of less than 50 to a
load of 10mA.

7. Voltage Splitting
The bidirectional characteri$tics can also be used to spilt a
higher supply in half, as shown in Figure 11. The combined
load will be evenly shared between the two sides .. Once
again, a high valve resistor to the LV pin ensures start·up.
Because the switches share the load in parallel, the output
impedance is much lower than in the standard circuits, and
higher currents can be drawn from the device. By USing
this Circuit, and then the circuit of Figure 6, + 15V can be
cO!1verted (via + 7.5, and - 7.5) to a nominal -15V, though
with rather high series resistance (- 2500).

SOk

+8V

SII<

.-~--------.---~--------------.-v+

SOk

lOOk

RLl

v+ - vVOUT = - 2 -

".Cl808.
VOl
L-~------

I

__+-__________________ +-v-

lOOk

Figure 11: Splitting a Supply in Half.

2SOk
VOLTAGE
ADJUST

I.

lOO.~

Figure 12: Regulating the Output Voltage

+ 5V

LOGIC SUPPLY

,.

T~l

DATA
INPUT

12

11

r-:!.f---oOJ..._~~~---oRS;~~:t,!A

,--+..!:'5!fCH>-.J
IHS142
13

14

+5V

- 5V

rI
n
I L..--I L-

Figure 13:.RS232 Levels from a Single 5V Supply

8. Regulated Negative Voltage Supply
In some cases, the output impedance of the ICL7660 can be
a problem, particularly if the load current varies substantially. The circuit of Figure 12 can be used to overcome this by
controlling the input voltage, via an ICL7611 low-power
CMOS op amp, in such a way as to maintain a nearly constant output voltage. Direct feedback is inadvisable, since the

5-110

OTHER APPLICATIONS
Further. information on the operation and use of the ICL7660
may be found in A051 "Principals and Applications of the
ICL7660 CMOS Voltage Converter" by Peter Bradshaw and
Dave Bingham.

ICL7663/7664
CMOS Programmable
Micropower Voltage Regulators
FEATURES

GENERAL DESCRIPTION

• Ideal for battery·operated systems: less than 4/-1A
typical current drain
• Will handle Input voltages from 1.6V to 16V
• Very low input·output differential voltage
• 1.3V bandgap voltage reference
• Up to 40mA output current
• Output shutdown via current·llmit sensing or exter·
nal logic signal
• Output voltages programmable from 1.3V to 16V
• Output voltages with programmable negative tem·
perature coefficients (ICL7663 only)

The ICL7663 (positive) and ICL7664 (negative) series
regulators are low·power,high·efficiency devices which
accept inputs from 1.6V to 16V and provide adjustable outputs over the same range at currents up to 40mA. Operating
current is typically less than 4p.A, regardless of load.
Output current sensing and remote shutdown are available
on both devices, thereby providing protection for the
regulators and the circuits they power. A unique feature, on
the ICL7663 only, is a negative temperature coefficient output. This can be used, for example, to efficiently tatlor the
voltage applied to a multiplexed LCD through the driver (e.g.,
ICM7231/213/4) so as to extend the display operating temperature range many times.
The ICL7663 and ICL7664 are available in either an S-pin
plastic minidip package or a TO-99 can.

r-P-IN--C-O-N-F-I-G-U-R-A-T-I-O-N-S--(o-ut-lIn-e-dw-g-SP-A-.T-V-)---------------------------------------------,1Ii!
ICL1884 Negative Regulator

ICL1883 Positive Regulator

GROUND

YiN

ORDERING INFORMATION
Positive Regulator
ICL1663CPA
ICL7663CTV
ICL7663/D

O'Cto
O'C to

+ 10'C
+ 70'C

Negative Regulator
B-pin minidip
TO-99

ICL7664CPA
ICL1664CTV

DICE

ICL7664/D

5-111

O'C to
O'C to

+ 70'C
+ 70'C

B-pln minidip
TO·99
DICE

ICL7663/7664
ABSOLUTE MAXIMUM RATINGS, ICL7663 POSITIVE REGULATOR
Input Supply Voltage ............................ + 18V
Any Input or Output Voltage (Note 1)
(GN D -O.3V) to
(Termirials1, 2, 3, 5, 6,7) ................... (V + O.3V)
Output Source Current
(TerminaI2) ................................. 50mA
(TerminaI3) ................................. 25mA

Output Sinking Current (Terminal?) .............. -10mA
Power Dissipation (Note 2)
Minidip ................................... 200mW
TO·99 Can ................................. 300mW

it

Stresses above those listed under "Absolute Maxinium Ratings" may cause permanent damage to the d(Jvice. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure fo absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS V ~ =.9V, VOUT = 5V, 'fA =
PARAMETER

Input Voltage
Quiescent Current
Reference Voltage
Temperature Coefficient

Line Regulation
VSET Input Current

SYMBOL

+ 25·C, test circuit unless otherwise specified.

TEST CONDITIONS

VI~

TA = +25·C
20·C",TA", + 70·C

10

{Rl=OO
,}
1·.4V", VOUT:S 8.5V

MIN

LIMITS
TYP
MAX

1.5

16.0

1.6

16.0

VIN = 16V

VI~

' VSET

=9V
1.2

UNIT

V

4.0
3.5

12
10

",A

1.3

1.4

V

Il.VSET
-Il.T

8.5V 0.6
0.4

J

0.2

V- ~~ ~ ~15V- r-

o ~ f"
o 2 4

6 8 10 12 14 16 18 20

5.0
4.5 - f-Tl=
-1--4.0
"'""TA= +25°C
3.5
I-3.0
2.5 ~-TA= + 70°C
2.0
1.5
1.0
0.5

VIN = +9.0V
LlVIN =2V

:i
~

lk

o

I

o

2

4

6

W

8

g

M ffi

5.00
4.75
4.50
4.25

2.0
1.8

~4.00

I

-

VI~= -9V

6.0

~ !::::

-lvIN= -15V
9.0

~

o
lk

5

0.6
0.4
0.2

o

8 10 12 14 16
VIN (V)

5·114

60

80

I

I I

I I
I I

V'~=I-~V
I I

J
II

~~ po-

o

.1.-1

1

y

VIN=-9

-

I----rl

/
/

r-

..... 1-'::

3.0

6.0

j....o

~
V'7 =1- 115V

9.0

12.0

15.0

ICL7664
Quiescent Current as a
Function of Temperature

~

6

40

IOUT2 (mA)

~

4

.......
..............

I
20

O.S

-1.4V"VOUT"VVoun AN D VOUT2
CONNECTED TOGETHER

2

V~=I~

1.2
1.0

12.0 15.0

3.5
3.0
~
..:; 2.5
~ 2.0
1.5
1.0
0.5

1\

r1"-"r---

r--..
I--.

TA= + 25°C

loun (mA)

5.0
4.5
4.0

r V+=+9V-

-......L

ICL7664
VOUT2 Input·Output Differential
vs Output Current
2.0

~
">

J

'" - ' I

So.

=1+~5V

........

-=>3.75
........
~ 3.50
3.25
3.00 - 2.75
2.50
-20
0

1.8
1.6
~ 1.4
VIN= -2VI ·1

3.0

vl

TEMPERATURE (OC)

I I I I

o

I

I

~~

(V)

TA= + 25°C

1.6
~ 1.4
;: 1.2
:::>
1.0
~
Il!; 0.8
~ 0.6
0.4
0.2
0

I

5 10 15 20 25 30 35 40 45 50
IoUT2(mA)

I

ICL7664
Quiescent Current as a
Function of Input Voltage

TA= + 25°C
VIN = -9.0V
LlVIN =2.0V

0.1
1.0 10.0 100.0
FREQUENCY (Hz)

III

ICL7663
Quiescent Current as a
Function of Temperature

ICL7664
Voun Input·Output Differential
vs Output Current

ICL7664
Input Power Supply
Rejection Ratio

0.01

o

vi~

ICL.7664
Output Voltage as a
Function of Output Current
-5.000
1111 I n11'
-4.995 1111
TA= + 25°C
-4.990 vlN = -9.0V
-4.985 BOTH OUTPUTS
_-4.980 CONNECTED
~ -4.975 TOGETHER
§; -4.970
-4.965
-4.960
-4.955
-4.950
l~A 10~A 100~A 1.0
10.0 100.0
lOUT (mA)

---

.......,..

'Y

+1
VIN =15V

0.2

o

VI~ =2V

VI~ =9V_

0.4

I I

~20ic

111111111111111111

'"

'" 1.2
!; 1.0
~ 0.8
+~ 0.6 ,.,..~-

loun (mA)

'"

100
90
80
70
iii"
:!:! 60
II:
50
II:
Q.
40
30
20
10

I

ICL7663
Quiescent .Current as a
Function of Input Voltage

111111111111111111

0.1
1.0 10.0 100.0
FREQUENCY (Hz)

"7 ~

J.-1" .....

/

r-

ICL7663
Input Power Supply
Rejection Ratio

i'

II II

1+1 1
VIN =9V

lOUT (mA)

100
90
80
70
iii" 60
:!:!
a: 50
II:
40
Q.
30
20
10
0
0.01

I I I.

I
I

ICL7663
VOUT2 Input· Output Differential
vs Output Current
2.0
1.8
TA= + 25°C
1.6
~ 1.4

5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5

o

rr- r-

-

-20

--

I
I
)

I
I
=

1
I

l-l~V

V- "'""1v

I

V

I
= -2V

1 Jl
II I
0
20
40
60
80
TEMPERATURE (OC)

ICL766317664
TEST CIRCUIT
SENSE 1 - - - - - - - - ,
VOUT2I--~-~-"IV\,-'--,-___{)

Note1: 8, when closed, disables oulput current limiting
Note 2: For ICL7664, exchange VOUT1 and VOUT2 . 8 2 action differs,
as follows:

VOUT1

VTC

(7663 ONLy)

RL

Device

8 2 Open

8 2 Closed

ICL7663

Voun

VOUT2

ICL7664

VOUTl + VOUT2

VOUT1

R2 + R,

Note 3: VOUT

=R;- VSET

ON

Note 4: IQ quiescent current is measured at GND pin by meter M
Note 5: 8 3 when ON, permits normal operation, when OFF, shuts
down both VOUT1 and VOUT2

S,

OFF

1M"

L....-4---~IN\r-___{)1.4V -......---'-0

!-----'".o

VSET

VTC

L . . . . - I - - - - + - - - - - - - - ' - O SHUTDOWN
o-----~~-~-------~GND

Figure 2_ Block Diagram of the ICL7664

Figure 1. Block Diagram 01 the ICL7663

5-115

ICL7663/7664
CMOS devices generally require two precautions: every input
pin must go somewhere, and maximum values of applied
voltages and current limi'ts must be rigorously observed.
Neglecting these precautions may lead to, at the least, incorrect or non-operation, and at worst, destructive device failure.
To avoid the problem of latch up, do not apply inputs to any
pins before supply voltage is applied.
Input Voltages- These regulators accept working inputs of
about 1.4V to 16V. When power is applied, the rate-of-rise of
the input may be hundreds of volts per microsecond. This is
potentially harmful to the regulators, where internal
operating currents are in the nanoampere range. TheO.0471'F
capacitor on the device side of the switch will limit inputs toa
safe level around 2Vll's. Use of this capacitor is suggested in
. all applications. In severe rate-of-rise cases, it may be advisable to use an RC network on the SHutDowN pin to delay
output turn-on. Battery charging surges, transients, and
assorted noise signals should be kept from the regulators by
RC filtering, zener protection, or even fusing.
Output Voltages- The resistor divider R21R1 is used to scale
the reference voltage, VSET , to the desired output using the
formula VOUT =(1 + R21R1) VSET. In the ICL7664, VIN and VSET
are negative, so VOUT will be also. Suitable arrangements of
these resistors, using a potentiometer, enables exact values
for VOUTtO be obtained. Because of the low leakage current of
the VsETterminal, these resistors can betensof megohms for
minimum additional quiescent drain current. However, some
load current is required for proper operation, so for extremely
low-drain applications it is necessary to draw at least 11'A.
This can include the current for R2 and R1.
Output voltages up to nearly the VIN supply may be obtained
at low load currents, while the low limit is the reference
voltage. The minimum input-output differential in each
regulator is obtained using the VOUT1 terminal.
Output Currents- For the ICL7663, low output currents of
less than 5mA are obtained with the least input-output differential from the VOUT1 terminal (connect VOUT2 to VOUT1).
Either output may be used on the ICL7664, with the unused
output connected to VIN. Where higher currents are needed,
use VOUT2 on the ICL7663 (VOUT1 should be left open in this
case) and parallel VO UT1 and VO UT2 on the ICL7664.
High output currents can be obtained only as far as package
dissipation allows. It is strongly recommended that output
current-limit senSing be used in such cases.

Current-Limit Sensing- The on-Chip comparator (C in the
block diagrams) permits shutdown of the regulator output in
the event of excessive current drain. As the test circuits
show, a current-limiting resistor, RCl , is placed in series with
VO UT2, and the SENSE terminal is connected to the load side
of RCl. When the current through RCl is high enough to produce a voltage drop equal to VCl (O.7V for ICL7663, 0.35V for
ICL7664) the voltage feedback is bypassed and the regulator
output will be limited to this current. Therefore, when the
maxil)1um load current (I LOAD) is determined, simply divide
VCl by ILOAD to obtain the value for RCl.
Logic-Controllable Shutdown-When equipment is not
needed continuously (e.g., in remote data-acquisition
systems), it is desirable to eliminate its drain on the system
until it is required. This usually means switches, with their
unreliable contacts. Instead, the ICL7663 and ICL7664 can be
shut down by a logic signal, leaving only 10 (under 41'A) as a
drain on the power source. Since this pin must not be left
open, it should be tied to ground if not needed. A voltage of
less thaI) 0.3V for the ICL7663, and greater than - 0.3V for the
ICL7664 will keep the regulator ON, and a voltage level of
more than 1.4V but less than V ~ for the ICL7663, and less
than -1.4V but not less than V iN for the ICL7664 control will
turn the outputs OFF. If there is a possibility that the control
signal could exceed the regillator input (V or V iN), the current from this Signal should be limited to 100l'A maximum by
a high-value (1 MO) series resistor. This situation may occur
when the logic signal originates from a separately-powered
system from that of the regulator.

if.

Additional Circuit Precautlons- These regulators have poor
rejection of voltage fluctuations from AC sources above 10Hz
or so. To prevent the output from responding (where this
might be a problem), a reservoir capacitor across the load is
advised. The value of this capacitor is chosen so that the
regulated output voltage reaches 90% of its final value in
20ms. From
I_CC.V C-I
(20 x 10- 3) -0022 lOUT
- c.t' - OUT 0.9VOUT - .
VOUT .
In addition, where such a capacitor is used, acurrent-limiting
resistor is also suggested (see "Current·Limit Sensing").
Producing Output Voltages With Negative Temperature
Coefficients- The ICL7663 has an additional output (not
present on the ICL7664) which is 0.9V relative to GN D and has
a tempco of + 2.5mV/oC. By applying this voltage to the
inverting input of amplifier A (i.e., the VSET pin), output
voltages having negative TC may be produced. The TC of the
output voltage is controlled by the R2/R3 ratio (see Figure 3
and its design equations).

EO.1: VOUT = VSET (1 + R2)
R1 + R2
R3 (VSET - VTC)
EO. 2: TCVOUT= - ~ (TCVTc)inmV/oC

>-.....-oVOUT

WHERE: VSET = 1.3V
VTc=O.9V
TCVTC = + 2.SmV/oC

Figure 3. Generating Negative Temperature Coefficients

5-116

ICL766317664
APPLICATIONS
VI~

SENSE
RCL
VOUT1

VSET 1----......

f--O.047.F
Your

VSET

O.047.F

YOUr>
'ICL7664
VOUT21-<~JV'.i/Ir---1~--'~

GND

SHDN

1
1

1

R,

~-'---4r--~

v'N

SENSEt-------'

vOUT = R2+R, VSET

VOUT = R2 + R, VSET

ICL = O.7V
RCL

ICL = O.3SV
RCL

R,

Figure 4. Basic Application of ICL7663 as Positive Regulator with
Current Limit

Figure 5. Basic Application of ICL7664 as Negative Regulatorwith
Current Limit

r---1~------------;t----1v,~

+
:

VOUT

R2

ICL7663 VTC r------

V'N=~_

r

R,

VOUT2

SENSE
ICL7663

RCL

VOUTt-""'i/Ir---1t--1~-<>+5V

GNO

VSET

9V

V+

CAP+ 2
C'

Case

CAP- 4
ICL7660

100pF

+-______~_~-,

GND~3~_ _.-_~_ _ _

R.

V+

C'

0,

1N4148
RCL

L - - - - - - - - - -......-------1V,N,CL766/ouTI-'YII'v---1.......--4r--o-SV 'Values depend on load
SENSE

characteristics

Figure 6. Generating regulated split supplies from a single supply. The oscillation freq!Jency of the ICL7660 is
reduced by the external oscillator capacitor. so that it inverts the battery voltage more efficiently.
+SV
Vlt
VOUT1

LOGIC
SYSTEM, I - PROCESSOR, IETC.

VOUT2

J

V+
1.8MIl
MUX'O LCD DISPLAY

ICL7663
VSET

300kO

ICM7233

VTC
-

GND

2.7MO

1

L

-::,.

---1\,

-V

mmmm

VUISP

GND

1'1

DATA BUS

Figure 7. Driving a Multiplexed LCD Display. The negative temperature coefficient drive voltage
to the displays allows consistent operation over more than 40·C temperature span, as
opposed to about 10·C with a fixed drive voltage. Values based on EPSON LDB·728
display or similar.

5·117

ICL 7663176~4
APPLICATIONS (Continued)

I

1

v+

:!...~Vr

--

L

osc

R1

GND

RADIO
ENABLE

SHUTDOWN

VSET

IN
SEG
OIPS

~~

ICM7223i\
OSC
OUT

PM

V-

SNn

I

I

"

ICL7664
Rse

LCD DISPLAY

VOUT1

222

BBtBB

VOUT2

1

R,
RT

U

REPEAT
SIGNAL

SENSE

VIN

I

I
Figure 8. Once a Day System. This circuit will turn on a regulated supply to a system for one minut "very day, via the SHUTDOWN
pin on the ICL7664, and under control of the ICM7223A Alarm Clock circuit-If the system decid,
needs another one minute activation, pulling the REPEAT line to V+ (GND) during one activation will trigger a subsequent activation after a snooze interval set
by the choice of SN pins (2 mins shown). Alternatively, activation of the Steep timer, without pause, can be achieved. See
ICM7223A data sheet for details.

CHIP TOPOGRAPHIES

I-~~-

---------~~~865~

0.065 in
(1.65)

mm

:m------¥SET

VTC

I

0.065 in
(1.65)mm

SENSE

YOUTZ

ICL7663

ICL7664

5-118

.D~DIL

ICL76638/48 ADDEN DUM TO TH E ICL766314 DATASH Eel
this Addendum to the standard ICL766314 datasheet describes
changes and/or modifications to the DC Operating characteristics applicable to the ICL7663B1ICL7664B devices. The
following table Indicates those limits to which the ICL7663B1
ICL7664B Is tested and/or guaranteed operational.

ICL7663B POSITIVE REGULATOR
ORDERING INFORMATION
Positive Regulator
ICL7664BCPA
ICL7664BCTV
ICL7664BC/D

S·pin MiniDIP
TO·99
DICE

Oto +70"C
Oto +70"C
Oto +70"C

ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage ............................ + 12V
Any Input or Output Voltage (Note 1)
(GND -0.3V)to
(Terminals 1,2,3,5,6,7) .................... (ViN +0.3V)
Output Source Current
(Terminal 2) .................................. 50mA
(Terminal 3) .................................. 25mA

Output Sinking Current (Terminal 7) ............... -10mA
Power Dissipation (Note 2)
MinIDIP ................................... 200mW
TO·99Can ................................. 300mW

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ICL7663B OPERATING CHARACTERISTICS YiN = 9V, VOUT = 5 V, TA = +25°C, test circuit unless otherwise specified.
PARAMETER

SYMBOL

LIMITS

TEST CONDITIONS
MIN

Input Voltage
Quiescent Current
Reference Voltage
Temperature Coefficient
Line Regulation
VSET Input Current
Shutdown Input Current

YiN

TA= +25°C
20°C';; TA ", + 70"C

10

~~l-OO
}
1.4V'" VOUT '" 8.5V

~

AVSET
VSETAVtN

UNITS
MAX

10
10

V

3.5

10

,..A

1.3

1.4

V

8.5V < VIN < 9V

±200

ppm

2V< VIN< 9V

0.03

%N

ISET

±0.01

10

nA

ISHDN

±0.O1

10

nA

Shutdown Input Voltage

VSHDN

Sense Pin Input Current

ISENSE

VSHDNHI: Both VOUT Disabled
VSHDNLO: Both VOUT Enabled

Sense Pin Input Threshold Voltage

VCl

Input-Output Saturation ReSistance
(Note 3)

RSAT

VIN=2V
VIN=9V

Load Regulation

AVOUT
AloUT

AIOUTt = 100,..A @ VOUTt = 5 V
AloUT2 = 10mA @ VOUT2 = 5V

Available Output Current (VOUT2)

IOUT2

VIN=3V
VIN=9V

VTC

Open·Circult Voltage

ITc

Maximum Sink Current

AVTC

1.4
0.3
0.01

VCl = VoUT2 - VSENSE
(Current-Limit Threshold)

Negative-Tempco Output (Note 4)

1.5
1.6

1.2

VSET

INSET

TYP

VOUT= VSET
VOUT=5V

Temperature Coefficient

~

Open Circuit

Minimum Load Current

lL(mln)

(Includes VS ET Divider)

10

nA

0.7

V

200
70

Q

2
1

Q

10
25

mA
0.9

0

V

8

V
2

mA
mVrC

+2.5
1

,..A

Not.t: Connecting any terminal to voltages greater than (YIN +O.3V)or less than (GND -O.3V) may cause destructive device latch·up.1t Is recommended that no
Inputs from sources operating on external power supplies be applied prior to ICl7663B power·up.
, Not. 2: Derate linearly above 5O"C at SmWfOC for mlnldlp and 7.SmWfOC for TO·99 can,
Not. 3: This parameter refers to the saturation resistance of the MOS pass transistor. The minimum Input-output voltage differential at low current (under SmA).
can be determined by multiplying the load current (Including set resistor current, but not quiescent current) by this resistance.
Not. 4: This output has a positive temperature coefficient. Using It In combination with the Inverting Input of the regulator at ¥SET, a negative coefficient results
In the output voltage. See J:lgure 3 for details. Pin will not source current.

5-119

ICL7664B NEGATIVE REGULATOR
ORDERING INFORMATION

ABSOLUTE MAXIMUM RATINGS
Input Supply Voltage .. ; ... ; . . . .. . .. . . . . .. .. -12V
Any Input or Output Voltage (Note 1)
(GND +0.3V) to
(Terminals 1, 2, 3, 5, 6, 7) ............... (VIN -0.3V)
Output Source Current
(Terminal 1, 7) ..........•.............. -25mA
Power Dissipation (Note 2)
MiniDIP .............................. 200mW
TO·99 Can .......................•.... 300mW

Negative Regulator

ICL7664BCPA
ICL7664BCTV

o to +70·C
o to + 70·C

a'pin MiniDIP
TO·gg

ICL7664BC/D

o to +70·C

DICE

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above those indIcated in the operational sections ofthe specific;ations is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ICL76648 OPERATING CHARACTERISTICS VIN =9V, VOUT= -5V, TA= +25°C, test circuit unless otherwise specified.
PARAMETER

SYMBOL

LIMITS

TEST CONDITIONS
MIN

Input Voltage

VIN

Quiescent Current

la

Reference Voltage

VSET

Temperature Coefficient

AVsET

TA = +25°C
O.;;TA .;; +70°C

TYP

,-10
-10

V

3.5

10

,..A

-1.3

-1.4

V

-1.5
-1.6

{Rl -00
}
-1.4V';; VOUT';; -S.5V
-1.2

UNITS
MAX

-S.5V < YiN < -9V

±200

ppm

-2V < VIN

0.03

%N

AT
Line Regulation
VSET Input Current
Shutdown Input Current

AVSET
VSETAVIN

< -9V

ISET

±0.Q1

10

nA

ISHDN

±0.01

10,

nA

Shutdown Input Voltage

VSHDN

Sense Pin Input Current

ISENSE

VSHDNHI: Both VOUT Disabled
VSHDNLO: Both VOUT Enabled

VCl

VCl = VOUT2 - '/sENSE
(Current·Limit Threshold)

Input·Output Saturation Resistance
(Note 3)

RSAT

VIN=2V
VIN =9V

AVOUT
AloUT

Output Current VO UT1 or VO UT2

lOUT

Minimum Load Current
(Includes VSET Divider)

lL(mln)

-1.4
0.01

Sense Pin Input Threshold Voltage

Load Regulation

-0.3

AIOUT! =100,..A @
AloUT= -5V
VIN =3V
ViN=9V

VOUT=VSET
VOUT= -5V

10

V
nA

-0.35

V

150
40

Q

2

Q

-2
-20

mA

1

,..A

NOlel: Connecting any terminal to voltages greaterthan (GND +O.3V)or less than (V IN -O.3V) may cause destructive device latch,up.lt Is recommended that no
inputs from sources operating on external power supplies be applied prior to ICl7664B power·up.
Nole 2: Derate linearly above SO'C at 5mWI"C for mlnldlp and 7.5mWI"C for TO·99 can.
Nole 3: This parameter refers to the saturation resistance of the MOS pass transistor. The minimum Inpul-output voltage differential can be determined by
multiplying the load current (Including set resistor current, but not quiescent current) by this resistance.

5·120

ICL7665
Micropower Under-I
Over-Voltage Detector
FEATURES

GENERAL DESCRIPTION

• Exceptionally low supply current '!~~:A typ)
• Individually programmable upper and lower trip
voltages and hysteresis levels
• Accurate on-chip bandgap reference, used by both
detectors
• Up to 20mA output current sinking ability
• Wide supply voltage range

BLOCK DIAGRAM

The ICL7665 contains two individually programmable voltage
detectors on a single chip. Requiring only - 3p.A for operation, the device is intended for battery-operated systems
and instruments which require high or low voltage warnings,
settable trip points, or fault monitoring and correction.
Typical applications are battery-backup computer memories,
battery-operated medical devices, radiation dosimeters,
pocket pagers, portable calibrators and test instruments,
and charging systems.

PIN CONFIGURATIONS

r-------------------~----~__Ov+

HYST2

SET1 o----+-------r.....
~--------_o

HYST1

1---------_0 OUT2
SET20----+--'-----t,,,
_.--~OUT1

L-------------------~----~__oGND

(outline dwg PAl

Conditions·
VSET1
VSET1
VSET2
VSET2

> 1.3V, OUT1 switch ON
< 1.3V, OUTl switch OFF
> 1.3V, OUT2 switch OFF
< ·1.3V, OUT2 switch ON

HYSTl switch ON
HYSTl switch OFF
HYST2 switch ON
HYST2 switch OFF

V+
(CASE)

• See Operating Characteristics for exact thresholds.

ORDERING INFORMATION
PART NUMBER
ICL7665PA
ICL7665TV
ICL7665/D

TEMPERATURE
RANGE
- 20'C to + 70'C
- 20'C to + 70'C

-

PACKAGE

8 Lead ivliniDIP
8 Lead TO·99
GND

DICE Only

(outline dwg TV)

5-121

ICL7665
ABSOLUTE MAXIMUM RATINGS
Maximum Sink Output Current OUTl and OUT2 ...... 25mA
Maximum Source Output Current
HYSTl andHYST2 .......................... -25mA
Power Dissipation (Note 1) ...................... 200mW
Operating Temperature Range ........... - 20°C to + 70°C
Storage Temperature Range ........... - 55°C to + 125°C

Supply Voltage ........ ' ................ - O.3V to + 18V
Output Voltages OUTl and OUT2
(with respect to GND)(Note2) ........... -O.3V to + 18V
Output Voltages HYSTl and HYST2
(with respect to V + )(Note 2) ............ + O.3V to -18V
Input Voltages SET1 and SET2
(Note 2) ................... (GND - O.3V) to (v+ +O.3V)
Note 1: Derate above +25°C ambient temperature at 4mWI"C.

Note 2: Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to voltages greater
than (V + + 0.3V) or less than (GND - 0.3V) may cause destructive device latchup. For this reason, it is recommended that no inputs from
external sources not operating from the same power supply be applied to the device before its supply is established; and that in multiple
s'upply systems, the supply to thelCL7665 be turned on first. If this is not possible, currents into inputs andlor outputs must be limited to
± 0.5mA and voltages must not exceed those defined above.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to,the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
. tions is not implied. Exposure to absolute maximum rating conditions ior extended periods may affect device reliability.

DC OPERATING CHARACTERISTICS (v+

= 5V, TA = + 25°C, test circuit unless otherwise specified.)
LIMITS

PARAMETER

SYMBOL

UNITS

TEST CONDITIONS
MIN

Operating Supply Voltage

V+

1+

Supply Current

Input Trip Voltage

'TA = + 25°C
- 20°C,; TA ,; + 70°C

AVSET

of VSET

AT

Supply Voltage Sensitivity

AVSET

of VSET1 , VSET2

AVs

Output Leakage Currents

10lK

on OUT and HYST

IHlK

Output Saturation Voltages

2.5

10

V+ =9V

2.6

10

V+ = 15V

2.9

15

1.15

1.3

1.45

1.2

1.3

1.4

0.004

'ioN

VSET = OV or VSET '" 2V

10
-10

V+ =2V, VSET1 =2V, IOUT1=2mA
V+ =5V, VsEn =2V, IOUT1 =2mA
V+ = 15V, VsEn = 2V, IOUT1 = 2mA

200
-100

0.2

0.3

0.06

0.2

VHYST1
VOUT2

V + = 2V, VSET2 = OV, IOUT2 = 2mA

0.2

VOUT2
VOUT2

V+ = 5V, VSET2 = OV, IOUT2 = 2mA

0.15

V+ = 15V, VSET2 =OV, IOUT2=2mA

ISET
AVSET

VSET1

-

VSET2

V+ =2V, VSET2 =2V, I HYST2 = -0.2mA
V+ =5V, VSET2 =2V, IHyST2 = -0.5mA
V+ = 15V, VSET2 = 2V, IHYST2 = - 0.5mA
GND ,; VSET ,; V+
ROUT = 4.7kll, RHysT = 20kll
VouTLO =1% V+, VouTHI =99% V+

-0.15

-0.3

-0.05

-0.15

~0.02

-0.10

V

0.5,
0.3

0.11

0.25

-0.25

-0.8

-0.43

-1.0

-0.35

-0.8

0.01

10

nA

±50

mV

1

ROUT, RHYST = 1Mil

±5

ROUT, RHYST = 1Mil

±1

5·122

nA

0.5

0.1

V + = 2V, VSET1 = 2V, IHYSn = - 0.5mA
V + = 5V, VSET1 = 2V, IHYST1 = - 0.5mA
V + = 15V, VSET1 = 2V, IHysn = - 0.5mA

VHYST2

V

Roun, ROUT2' RH YST1, RHYST2 = 1 Mil

IHlK

VHYST2

p.A

ppmloC

2000

Voun

V

200

-500

VHYST2

Output/Hysteresis Difference

16.0

V + = 15V, TA = 70°C

VHYSn
VHYST1

Difference in Trip Voltages

16.0

1.8

V+ =15V, TA=70°C

Voun

AVSET Input for Complete
Output Change

1.6

10lK

Voun

VSET Input Leakage Current

MAX

GND ,; VSET1 , VSET2 ,; V +
All Outputs Open Circuit
V+ =2V

VSET;
VSET2

Temperature Coefficient

TYP

ICL7665
AC OPERATING CHARACTERISTICS
LIMITS
PARAMETER

SYMBOL

MIN
Output Delay Times

t S01d
t SH1d

Input Going HI

ROUT

tS02d

610

RouT

120
80

= 4. 7kn, CL = 12pF

tH2r

25
30

VSET Switched between 1.0V and 1.6V

t021

60

RouT = 4.7kn, C L = 12pF

tHlI

~s

180

RHYST = 20kn, C L = 12pF

tH21

~s

330

RHYST = 20kn, C L = 12pF

tOll

~s

70
30

VSET Switched between 1.0V and 1.6V

t02r
t H1r

Output Fall Times

1040

= 4.7kn, CL = 12pF
RHYST = 20kn, C L = 12pF

t 01r

~s

120
230

RouT

tS02d
t SH2d
Output Rise Times

= 4.7kn, C L = 12pF

VSET Switched from 1.6V to 1.0V

tSH1d

MAX

80

RHYST = 20kn, CL = 12pF

t S01d

TYP
70

VSET Switched from 1.0V to 1.6V

tSH2d

Input Going LO

UNITS

TEST CONDITIONS

30

SWITCHING WAVEFORMS
.--------,--------------1.6V

INPUT

VSET1. VSET2

L------------------1.0V

------- v+ (SV)
tS01d

OUT1

~------~------~-------GND
t - - - - - - + - - - - I d - + - - - - - - - - - V + (SV)

HYSn

!'-------------GND
I~-----_{f+-------------V+ (SV)

OUT2

1'------------------ GND
lr-----4.H---~----------V+

HYST2

~---------------

TEST CIRCUIT (Switching

(SV)

tH2f

tSH2d

GND

Response)
V+

4.7kn
r----------------t--~----*---~---------------oOUT1

4.7kn

.----+----.---------0 HYSn

~----*---~--~----t_--~-----oOUT2

INPUT
1.6V-n

1.0v------1

L

Hf---......-~-~----t_--+--.....,.-o HYST2

5-123

IID~D16

ICL7665
TYPICAL OPERATING CHARACTERISTICS
OUT1 Saturation Voltage as a
Function of Output Current

E 2:0

Supply Current as a
Function of Suppl.y Voltage

;--,;--..,.--,,::--:-::-::"1

w

CI

~

~ 1.6

o

....
z

o

It:
It:

~ 1.2 I-------'I----I-t--t---+---c.

w

::>

~ O.s I----~~--t-~~

0

It:

::>

~
~

0.4

o

Il.
Il.

1---~----:;;;;""'1::~;;!",~.
4

E 2.0

>
....

S

12

::>

fJ)

16

z

~

6

'--''-1._-'-_-'-_.J.....JL......J -2.0

8 10 12 14 16
HYST1 OUTPUT CURRENT (mA)

HYST2 Output Saturation Voltage
vs HYST2 Output Current
-5.0 -4.0 -3.0 -2.0 -1.0

;---,--r--,-n--.rr--.



1---t--+--tl'--7''-I7'''--'-t-----l

0

f--~~"'f_-+-t---j

Il.
Il.

Il!
::>
o

4

Supply Current as a
Function of Ambient Temperature

1.2 I---t--+++<'

0.4

2

OUT2 Saturation Voltage as a
Function of Output Current

o

::>

I I I

o

SUPPLY VOLTAGE (V+)

1.6

~ o.s

I
I I I

OU11 OI,lTPUT CURRENT (mA)

w

g

-

o

20

CI

~

5.0
4.5 _OV:5 ViET1'IVSjT2:5 V~_
4.0
~
3.5 - I - - r- TA= -20·C
3.0
F-- -TA= +25·C- I-~
2.5
2.0
TA= +70·C
1.5
I I
1.0
0.5

HYST1 Output Saturation Voltage
vs HYST1 Output Current
-20 -16 -12 -s
-4
0
r.:---::-:::-::r-,---,-.".O

4

8

12

16

20

OUT2 OUTPUT CURRENT (mA)

~

::>

fJ)

5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5

r- OVi'

~

V1SETi' VSETi :5 V+ I -

I

~=115V
~:.::;;

vL~v I -

1------1~-t--+-z:I~(---i -1.0 ~

~~

f----j~--j,~~-__t---l -2.0 5 ~

z'"

<0

v+ -2V

A~-i'I--+-+---l -30 0 ~

. ~~,

-iI'-+--+--t------I -4.0

o

'--"--''----'--'--........---' -5.0

-20

0

+20

+40

f,l ....

3

+60

AMBIENT TEMPERATURE (·C)

HYST2 OUTPUT CURRENT (mA)

DESCRIPTION

PRECAUTIONS

As shown in the Block Diagram, the ICL7665 conSists of two
comparators which compare input voltages on the SET1 and
SET2 terminals to an internal 1.3V band-gap reference. The
outputs from the two comparators drive open-drain
N-channel transistors for OUT1 and OUT2, and open-drain
P-channel transistors for HYST1 and HYST2 outputs. Each
section, the Under-Voltage Detector and the Over-Voltage
Detector, is independent of the other, although both use the
internal1.3V reference. The offset voltages of the two comparators will normally be unequal, so VSET1 will generally not
quite equal VSET2•

Junction·isolated CMOS devices like the ICL7665 have an inherent SCR or 4-layer PNPN structure distributed throughout
the die. Under certain circumstances, this can be triggered
into a potentially destructive high-current mode. This latchup
can be triggered by forward-biasing an input or output with
respect to the power supply, or by applying excessive supply
voltages. In very· low-current analog circuits, such as the
ICL7665, this SCRcan also be triggered by applying the input
power supply extremely rapidly ("instantaneously"), e.g.
through a low.impedance battery and an ON/OFF switch with
short lead lengths. The rate-of-rise of the supply voltage can
exceed 100V/"s in such a circuit. A low-impedance capacitor
(e.g. O,05"F disc ceramic) between the V + and GrouND pins
of the ICL7665 can be used to reduce the rate-of-rise of the
supply .voltage in. battery applications. In line-operated
systems, the rate-of-rise of the supply is limited by other considerations,and is normally not a problem.

The input impedances of the SET1 and SET2 pins are extremely high, and for most practical applications can be
ignored. The four outputs are open-drain MOS transistors,
and when ON behave as low resistance switches to their
respective supply rails. This minimizes errors in setting-up
the hysteresis, and maximizes the output flexibility. The
operating currents of the bandgap reference and the comparators are around 100nA each.

If the SET voltages must be applied before the supply voltage

v+, the input current should be limited to less than O.5mA by
appropriate external reSistors, usually required for voltage
setting anyway. A similar precaution should betaken with the
outpu'fsifitis likely that they will be driven by other circuits to
levels'outside the supplies at any time. See M011 for some
other pt~tection ideas.

5·124

ICL7665
APPLICATIONS
VOUT

OFF

V,N

1
v·

Rp2

Rp,

R21.-_+_ OUT1

OUT2 ~
ICL7665

SEn

SET2

Ru
~

00

.l

1

. -

VTR2

VNOM

VTR1

f----DETECTOR 2 + DETECTOR , - -

(b) Transfer Characteristics

(a) Circuit Configuration
Figure 1. Simple Thrashold Detector

Figure 1 shows the simplest connection of the ICL7665 for
threshold detection. From the graph (b), it can be seen that
at low input voltages OUT1 is OFF, Or high, while OUT2 is
ON, or low. As the input rises (e.g. at power-on) toward VNOM
(usually the eventua.1 operating voltage), OUT2 goes high on
reaching VTR2 . If the voltage rises above VNO M as much as
VTR " OUT1 goes low. The equations giving VSET' and VSET2
are, from Figure 1(a):

Since the voltage to trip each comparator is nominally 1.3V,
the value of V1N for each trip point can be found from
VTR ,

=VSET1 (Rl1 + R2,) =1.3 (R"
R"

+ R2,) for detector 1 and
Rll

VTR2 =VSET2 (R'2 + R22)
R'2

=1.3

(R;2 + R22) for detector 2.
R'2

Either detector may be used alone, as well as both together,
in any of the circuits shown here.
When V1N is very close to one of the trip voltages, normal
variations and noise may cause it to wander back and forth
across this level, leading to erratic output ON and OFF condi·

tions. The addition of hysteresis, making the trip points
slightly different for rising and falling inputs, will avoid this
condition.
Figure 2(a) shows how to set up such hysteresis, while Figure
2(b) shows how the hysteresis around each trip point pro·
duces switching action at different pOints depending on
whether V1N is r.iSin g or falling (the arrows indicate directiO. n
of change). The HYST outputs are basically switches which
short out R3, or R32 when VIN is above the resIJective trip
point. Thus if the input voltage rises from a low value, the trip
point will be controlled by R'n, R2n and R3n, until the trip point
is reached. As this value is passed, the detector changes
state, R3n is shorted out, and the trip pOint becomes controlled by only R'n and R2n, a lower value. The input will then
have to fall to this new point to restore the initial comparator
state, but as soon as this occurs, the trip point will be raised
again.
An alternative circuit for obtaining hysteresis is shown in
Figure 3. In this configuration, the HYST pins put the extra
resistor in parallel with the upper setting resistor. The values
of the resistors differ, but the action is essentially the same.
The governing equations are given in Table 1. These ignore
the effects of the resistance of the HYST outputs, but these
can normally be neglected if the resistor values are above
about 100kO.
OWT

V,N

1

I
I R31
I

r- HVST1

,~

I

I

v·

R32
HVST2

,l
R22

r-

I

I

-

,to R21

l'

SET1

ICL7665

SET2

ON

I

~

'III:
~

I

I

I
1

oun

OVER·VOLTAGE
Ru

GND

1

OFF

1

OUT2

UNDER·VOLTAGE

1--+.-7:VL.L.2~VU2

I

'-'"_____+-______--+1

R12
I--DETECTOR 2-----DETECTOR
VNOM

(a) Circuit Configuration

(b) Transfer Characteristics
Figure 2. Threshold Detector with Hysteresis

5-125

V,N

1--L

Ii

ICL7665
APPLICATIONS

(Continued)
V,N

Table 1. Set· Point Equations
a) NO HYSTERESIS
Over·Voltage
+--'VIIIr--; HYST1
+----;SET1

ICL7665

R11+R21
VTRIP = --RXVSET1
11 -

HYST2 1--.lVl.I\r---.
Under·Voltage VTR1P = R12 + R22 X VSET2
R12

SET2i-----+

R11

b) HYSTERESIS PER FIGURE 2A
VU1 =
Over·Voltage

Figure 3. An Alternative Hysteresis Circuit

R11 + R21 + R31

X VSET1

R"

VTR1P

R11+R21
VL1 =--R-,,-XVSET1

.CHIP TOPOGRAPHY
VU2 =
Under·Voltage VTR1P

R'2 + R22 + R32
V
R
X SET2
12

VL2 = R'2 + R22 X VSET2
R'2
c) HYSTERESIS PER FIGURE 3
VU1 = R" + R21 X VS ET1
R"
Ov?r.Voltage

VTR1P

R" +
VL1 =

R21 R31
R21 + R31

X VSET1

R"
VU2 = R'2 + R22 X VSET2
R'2
Under·Voltage VTR1P
VL1 =

R
R22 R32
12+--R22 + R32
R'2

ICL7665

5-126

X VSET2

ICL7665B ADDENDUM TO THE ICL7665 DATASHEET
ORDERING INFORMATION
This Addendum to the standard ICL7665 datasheet describes
changes and/or modifications to the DC Operating characteristics applicable to the ICL7!l65B device. The following table
indicates those limits to which the ICL7665B is tested and/or
guaranteed operational.

PART NUMBER
ICL7665BCPA
ICL7665BCTV
ICL7665BC/D

TEMPERATURE
RANGE

o to
o to
o to

PACKAGE
8 Lead MlnlDIP
8 Lead TO·99
DICE Only

+70·C
+70·C
+70·C

ABSOLUTE MAXIMUM RATINGS, ICL7665B
Supply Voltage ......................... -0.3Vto +12V
Output Voltages OUT1 and OUT2
(with respect to GND)(Note2) ........... -0.3Vto + 12V
Output Voltages HYST1 and HYST2
(with respectto V+)(Note2) ............ +0.3Vto -12V
Input Voltages SET1 and SET2
(Note 2) ................... (GND -0.3V)to(V+ +0.3V)

Maximum Sink Output Current
OUT1 and OUT2 .............................. 25 rnA
Maximum Source Output Current
HYST1 and HYST2 .......................... - 25mA
Power Dissipation(Note 1) ...................... 200mW
Operating Temperature Range ................ 0 to + 70'C
Storage Temperature Range. . . . . . . . . . .. - 55·C.to + 125'C

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above those indicated In the operational sections of the specifications is not
Implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC OPERATING CHARACTERISTICS V+ = 5 V, TA = + 25'C, test circuit unless otherwise specified.
PARAMETER

SYMBOL

TEST CONDITIONS

Operating Supply Voltage

v+

TA= +25'C

Supply Current

1+

GND ~ VSEn , VSET2 ~ V +
All Outputs Open Circuit
V+ =2V
V+ =9V

Input Trip Voltage
Temperature Coefficient
of VSET
Supply Voltage Sensitivity
of VSET1, VSET2
Output Leakage Currents
on OUT and HYST

Output Saturation Voltages

VSET Input Leakage Current
AVSET Input for Complete
Output Change
Difference in Trip Voltages
Output/Hysteresis Difference

O~ TA~+70'C

Roun, ROUT2, RHysn , RHYST2 = 1 MQ

TYP

1.6
1.8

1:15
1.2

VSETI
VSET2
AVSET
AT
AVSET

LIMITS
MIN

MAX

UNITS

10
10

V

2.5
2.6

10
10

iAA

1.3
1.3

1.45
1.4

V

±2oo

pprnrc

0.004

%N

AVs
IOlK
IHlK

VSET = OV or VSET '" 2V

IOlK
IHlK

V+ =9V, TA=70'C
V+ =9V, TA =70'C

VOUTI
Voun
VOUTI

V+ =2V, VSET1 =2V, loun =2mA
V+ =5V, VSET1 =2V, loun =2mA
V+ =9V, VSETI =2V, IOUTI =2mA

VHysn
VHYSTI
VHYSn

V + = 2V, VSET1 = 2V, IHYSn = - 0.5mA
V + = 5V, VSET1 = 2V, IHysn = - 0.5mA
v+ =9V, VSET1 =2V, IHYSTI = -0.5mA

VOUT2
VOUT2
VOUT2

V+ =2V, VSET2 =OV, IOUT2=2mA
V+ =5V, VSET2=OV, IOUT2=2mA
V+ =9V, VSET2 =OV, IOUT2=2mA

VHYST2
VHYST2
VHYST2

V+ =2V, VSET2 =2V, IHyST2 = -0.2mA
V+ =5V, VSET2 =2V, IHYST2= -0.5mA
V+ =9V, VSET2=2V, IHYST2= -0.5mA

ISET
AVSET
VSET1-VSET2

GND ~ VSET ~ V+
ROUT=4.7kQ, RHysT =20kQ
VouT LO=1% V+, VOUTHI=99% V+

10
-10

200
-100

nA

2000

-500
0.2
0.1
0.06

0.5
0.3
0.25

-0.15
-0.05
-0.02

-0.3
-0.15
-0.15

0.2
0.15
0.11

0.5
0.3
0.3

-0.25
-0.43
-0.35

-0.8
-1
-1

0.01

10

V

nA

1
mV

ROUT, RHYST = 1 MQ

±5

ROUT, RHYST = 1 MQ

±1

±50

Notal: Derate above + 25·C ambient temperature at 4mWfC.
Nota 2: Due to the SCR structure Inherent In the CMOS process used to fabricate these devices, connecting anY terminal to voltages greater than 01 + + O.3V)or
less than (GND - O.3V) may cause destructive device latchup. For this reason, Ills recommended Ihal no Inpuls from external sources not operating from Ihe
same power supply be applied to the device before lis supply Is establshed, and that In multlpe supply systems,lhe supply 10 the ICL7665 be turned on first. If
this Is nol possible, currenls Into Inputs andloroutputs must be limited 10 ± O.SmA and voltages must not exceed those defined above.

5-127

D~D[l

ICL7667
1 Power MOS Driver

FEATURES

GENERAL DESCRIPTION

• 1.5A Peak Output Current
• Fast Rise and Fall Times
- 40ns with 1000pF load
• Wide Supply Voltage Range
-Vee =4.5 to 20V
• Low Power Consumption
- 4mW with inputs low
-120mW with inputs high
• nUCMOS Input Compatible Power Driver

The ICl7667 is a dual monolithic high-speed driver designed to convert TTL level signals into high current
outputs at voltages up to 20V. Its high speed and 1.5A
peak current output enable it to drive large capacitive
loads with high slew rates and low propagation delays.
With an output voltage swing only millivolts less than
the supply voltage and a maximum supply voltage of
20V, the ICL7667 is well suited for driving power
MOSFETs in high frequency switching regulators. The
ICl7667's high current (1.5A peak) outputs minimize
power losses in the power MOSFETs by rapidly.charging and discharging the gate capacitances, while the
ICL7667's inputs are TTL compatible and can be directly driven by common switching regulator IC's.

-ROUT=6Q

• Direct Interface with Common Switching
Regulators
• Pin Equivalent to D50026/DS0056

TYPICAL APPLICATIONS
• Switching Power Supplies
• DC/DC Converters
• Motor Controllers

ORDERING INFORMATION
Temperature
Range
- 55·C to

o to
o to

+ 125·C

+ 70·C
+ 70·C

PIN CONFIGURATION

Package

Order
Number

TO-99 Can

ICL7667MTV

8-Pin Cerdip

ICL7667MJA

8-Pin Plastic

ICL7667CPA

8-Pin Cerdip

ICL7667CJA

TO-99 Can

ICL7667CJA

Dice

ICL7667C/D

v+

v(pin configuration for TV and PA packages also on this page)
TOP VIEW
TO·99

(TV)

BLOCK DIAGRAM

N.C. OUT

8

A

v+

2

3
V-

7

6

OUT

B

7

Vee - -.....- - - - . , - - - - ,

t---19>O---1;I00---

OUT

IN-1

1

N.C.

IN

A

TOP VIEW

8-PIN DIP
(PA, JA)

5-128

4

IN

B

[l]O~OIl

ICL7667
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ...................•......... 22V
InputVoltage ................... 22Vto(V- -0.3V)
Peak Output Gurrent . . . . . . . . . . . . . . . . . . . . . . . . 1.5 A
Package Dissipation, TA = 25°G ............. 500mW
Linear Derating Factors
TO·gg
Plastic
Gerdip
6.7mWfG
5.6mWfG
6.7mWfG
above SOOG
above 36"G
above SOOG
Storage Temperature .............. -65°G to + 1SOOG

Lead Temperature (Soldering, 10 seconds) ...... 3QOOG
Operating Temperature Range
G Series ........................... 0 to + 700G
M Series ....................... - 55°G to +125°G

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

DC OPERATING CHARACTERISTICS
Test Conditions: Vee = 4.5to 20V, TA = +25°C unless otherwise noted.

PARAMETER

SYMBOL

Logic 1 Input Voltage

VIH

Logie 0 Input Voltage

VIL

LIMITS

TEST CONDITIONS
MIN

TYP

2.4

2.0

UNITS
MAX

V

1.5

0.8

V

1

,..A

IlL

0< VIN < Vee

-1

0

VOH

No Load

Vee
-0.05

Vee

Output Voltage Low

VOL

No Load

0

0.05

V

Output Resistance

ROUT

VIN =VIL
lOUT = -10mA
Vee=20V

6

20

Q

Output Resistance

ROUT

VIN=VIH
lOUT = 10mA
Vce=20V

6

20

Q

Power Supply Current

Icc

VIN=3V
(both inputs)

4

6

mA

Power Supply Current

Icc

VIN=OV
(both inputs)

150

400

,..A

Input Current
Output Voltage High

V

AC OPERATING CHARACTERISTICS
Test Conditions: Vee = 20 V, TA = + 25°C, unless otherwise noted.

PARAMETER

SYMBOL

LIMITS

TEST CONDITIONS
MIN

UNITS

TYP

MAX

Delay Time

T02

Figure 1

50

75

ns
ns

Delay Time

T02

Figure 2

50

75

Rise Time

TR

Figure 1

25

35

ns

Rise Time

TR

Figure 2

35

50

ns

Fall Time

TF

Figure 1

30

40

ns

Fall Time

TF

Figure 2

40

55

ns

OelayTime

T01

Figure 1

20

35

ns

Delay Time

T01

Figure 2

20

35

ns

5-129

ICL7667
V+ =20V

+5V
INPUT

~O.l~F

"'.4V

---+-t:>C-+---1P---'" OUTPUT

INPUT

20V

INPUT RISE AND
FALL TIMES';10ns

ov

Figure 1.

Test Circuit

V+ =20V

+5V
INPUT
~O.l~F

"'.4V
INPUT

---+-i.><-+-.......W'Y--......-

*"

1011

INPUT RISE AND
FALL TIMES';10ns

OUTPUT

20V

CL=l000pF

OV

Figure 2.

Test Circuit

TYPICAL CHARACTERISTICS
T01. T02 vs Temperature

Rise and Fall Times vs CL

TR. TF vs Temperature

100

..100
c::

V

I

LL
.....

a:

I

90

r!

CL=lnF , _
IIcC=20V

70

T02 __

50
40

30

i FA2t.
I· -r

20

--

100

11'F

0
-55

lOI'F

ICC vs CL

c(

10

e
I

o

--

TR~/ ~

30

c::

20

~

V

CL=lnF
IIcC=20V

T0110

0

+25

CL WITH 10Q SERIES RESISTANCE
VCC=20V

30

.

.--'

~

40

10

1

10

80

60

./

TRISE

.... 10

V

/

50

JJ/

I---""

$;
3.0

1
loopF 100pF

V

70

0

+25

70

+125

·C

·C

ICC vs Frequency

No Load ICC vs Frequency

V

-

~V'

20kHz

100

100
c(

c(

E

E

I

I 10

10

0

0

$;

$;

lDOI'A '--_ _-L._ _ _..l-_ _.....I
lnF

0
-55

+125

10nF

CL with 10Q SERIES RESISTANCE
VCC=20V

10k

lOOk

1M

FREQUENCY

5·130

10 meg

CL= 10pF
100l'A '--_ _....J._ _ _..l-_ _.....I
10k

lOOk

1M

FREQUENCY

10meg

.O~OIl.

ICL7667
TYPICAL CHARACTERISTICS

(Cont'd)

Delay and Fall Times vs
50
40
til

I'

30

~

w

~

i=

Vee

Rise and Fall Times vs

Vee

50

40

I' 30 ~ .............
til

...........

20

~
10

TF

-

T01

/

TR =T02

w

~

.....

i= 20
eL= 1nF

CL=lnF
10

o

o
5

10

20

15

5

Vee

15

10

20

Vee

DETAILED DESCRIPTION
The ICL7667 is a dual high-power CMOS inverter whose inputs
respond to TTL levels while the outputs can swing as high as
20V. Its 1.5A peak output current enables it to rapidly charge
and discharge the gate capacitance of power MOSFETs,
minimizing the switching losses in switch mode power supplies. Since the output stage is CMOS, the output will swing to
within millivolts of both ground and Vce, without any external
parts or extra power supplies as required by the DS0026/56
family. Although most specifications are at Vee 20V, the
propagation delays and specifications are almost independent of Vee.

=

In addition to power MOS drivers, the ICL7667 is well suited for
other applications such as bus, control signal, and clock
drivers on large memory of microprocessor boards, where the
load capacitance is large and low propagation delays are required. Other potential applications include peripheral power
drivers and charge pump voltage inverters.

INPUT STAGE
The input stage is a large N-channel FET with a P-channel
constant-current source. This circuit has a threshold of about
1.5 V, relatively independent of the Vec voltage. This means
that the inputs will be directly compatible with TTL over the entire 4.5-20V Vee range. Being CMOS, the inputs draw less than
l,..A of current over the entire input voltage range of ground to
Vee. The quiescent current or no load supply current of the
ICL7667 is affected by the input voltage, going to nearly zero
when the inputs are at the 0 logic level and rising to 6mA maximum when both inputs are the 1 logic level. A small amount of
hysteresis, about 50-100mV at the input, is generated by
positive feedback around the second stage.

OUTPUT STAGE
The ICL7667 output is a high-power CMOS inverter, swinging
between ground and Vee. At Vee = 20V, the output impedance
of the inverter is typically 6Q, with a peak current output of
typically 1.5A. It is this high peak current capability that
enables the ICL7667 to drive a 1000pF load with a rise time of
only 40ns. Because the output stage impedance is very low, up
to 300mA will flow through the series N- and P-channel output
devices (from Vee to ground) during output transitions. This
"crowbar" current is a significant portion of the internal power

5-131

dissipation of the ICL7667 at high frequencies. It can be
minimized by keeping the rise and fall times of the input to the
ICL7667 below 1,..S.

APPLICATION NOTES
Although the ICL7667 is simply a dual level-shifting inverter,
there are several areas to which careful attention must be paid.

GROUNDING
Since the input and the high current output current paths both
include the ground pin, it is very important to minimize any
common impedance in the ground return. Since the ICL7667 is
an inverter, any common impedance will be negative feedback,
degrading the delay, rise and fall times. Use a ground plane if
possible, or use separate ground returns for the input and output circuits. To minimize any common inductance in the
ground return, separate the input and output circuit ground
returns as close to the ICL7667 as is possible.

BYPASSING
The rapid charging and discharging of the load capacitance requires very high current spikes from the power supplies. A
parallel combination of capacitors that has a low impedance
over a wide frequency range should be used. A 4.7,..F capacitor
in parallel with a low inductanceO.1,..F capacitor is usually sufficient bypassing.

OUTPUT DAMPING
Ringing is a common problem in any circuit with very fast rise
or fall times. Such ringing will be aggravated by long inductive
lines with capacitive loads. Techniques to reduce ringing include:
1) Reduce inductance by making printed circuit board traces
as short as possible.
2) Reduce inductance by using a ground plane or by closely
coupling the output lines to their return paths.
3) Use a 10 to 30Q resistor in series with the output of the
ICL7667. Although this reduces ringing, it will also slightly increase the rise and fall times.
4) Use good bypassing techniques to prevent ringing caused
by supply voltage ringing.

.D~DIl.

ICL7667

POWER MOS DRIVER CIRCUITS
POWER DISSIPATION

POWER MOS DRIVER REQUIREMENTS

The power dissipation of the ICL7667 has three main components:

Because it has very high peak current output, the ICL7667 excels at driving the gate of power MOS devices. The high current output is important since it minimizes the time the power
MOS device is in the linear region. Figure 3 is a typical curve of
charge vs. gate voltage for a power MOSFET. The flat region is
caused by the Miller capacitance, where the drain-to-gate
capacitance is multiplied by the voltage gain of the FET. This
increase in capacitance occurs while the power MOSFET is in
the linear region and is dissipating significant amounts of
power. The very high current output of the ICL7667 is able to
rapidly overcome this high capacitance and quickly turns the
MOSFET fully on or off.

1) Input inverter current
2) Output stage crowbar current
3) Output stage 12R power
The sum of the above must stay within the specified limits for
reliable operation.
As noted above, the input inverter current is input voltage
dependent, with an Icc of O.2mA maximum with a logic 0 input and 6mA maximum with a logic 1 input.
The output stage crowbar current is the currElnt that flows
through the series N- and P-channel devices that form the output. This current, about 300mA, occurs only during output transitions. Caution: The inputs should never be allowed to remain
between V1L and VIH since this could leave the output stage in a
high current mode, rapidly leading to destruction of the device.
If only one of the drivers is being used, be sure to tie the unused
input to a ground. NEVER leave an input floating. To reduce the
average power dissipation in the output stage due to transitions, the input signal rise time should be less than 1J.ts. The
average supply current drawn by the output stage is frequency
dependent, as can be seen in Icc vs. Frequency graph in the
Typical Characteristics Graphs.
The output stage 12R power dissipation is nothing more than
the product of the output current times the voltage drop across
the output device. In addition to the current drawn by any
resistive load, there will be an output current due to the charging and discharging of the load capacitance. In most high frequency circuits the current used to charge and discharge
capacitance dominates, and the power dissipation is approximately
PAC=CVcc 2F

18
16

IO=IA

14

III 12

680pF/ V'

I'

8
~ 6

>

'/

4
2

o
-2

Figure 3.

2

4

6

8

ro n

M

~ ~ ~

MOSFET Gate Dynamic Characteristics

DIRECT DRIVE OF MOSFETs
Figure 4 shows interfaces between the ICL7667 and typical
switching regulator ICs. Note that unlike the OS0026, the
ICL7667 does not need a dropping resistor and speed-up
capacitor between it and the regulator IC. The ICL7667, with
its high slew rate and high voltage drive can directly drive the
gate of the MOSFET. The 1527 IC is the same as the 1525 IC,
except that the outputs are inverted. This inversion is needed
since ICL7667 is an inverting buffer.
+165 VOC

t--t--O--+--'~.,I-~
1-+-1:>0-11-..... ~ IVN8400
GNO

<

Figure 4a_

+15

Direct Drive of MOSFET Gates

5-132

Ve30 pF
I

QG - NANO COULOMOS

In cases where the load is a power MOSFET and the gate drive
requirements are described in terms of gate charge, the
ICL7667 power dissipation will be

Figure 4b.

r,(voo= :r>v

I
o

+18

Where QG = Charge required to switch the gate, in
Coulombs.
F = Frequency

4oci=

/212pF

Where C = Load Capacitance
F = Frequency

PAC=QGVCCF

II

V ~75V

VI

5 10

r

'II
voo=/
sov ~/

IVN6000

vDirect Drive of MOSFET Gates

ICL7667
TRANSFORMER COUPLED DRIVEOF MOSFETs

BUFFERED DRIVERS FOR MULTIPLE MOSFETs

Transformers are often used for isolation between the logic
and control section and the power section of a switching
regulator. The high output drive capability of the ICL7667
enables it to directly drive such transformers. Figure 5 shows a
typical transformer coupled drive circuit. PWM ICs with either
active high or active low outputs can be used in this circuit,
since any inversion required can be obtained by reversing the
windings on the secondaries.

In very high power applications which use a ~roup of
MOSFETs in parallel, the input capacitance may be very large
and it can be difficult to charge and discharge quickly. Figure 6
shows a circuit which works very well with very large capac·
itance loads. When the input of the driver is zero, 01 is held in
conduction by the lower half of the ICl7667 and 02 is clamped
off by 01. When the input goes positive, 01 is turned off and a
current pulse is applied to the gate of 02 by the upper half of
the ICl7667 through the transformer, T1. After about 20ns, T1
saturates and 02 is held on by its own Cgs and the bootstrap
circuit of C1, 01 and R1. This bootstrap circuit may not be
needed at frequencies greater than 10kHz since the· input
capacitance of 02 discharges slowly.

In this circuit, the transformer is driven with a symmetrical
waveform, so the secondary voltage outputs are determined
only by the turns ratio and the power supply voltage to the
ICL7667. If the transformer drive is not symmetrical, the
voltage output will be affected by the duty cycle, being highest
for low duty cycles.
+18

_ - - - - - - +165V

SG1524

OV
V.ICL7667

EB

,!,

470

Figure 5.

J. ---.. .~-~--

Transformer Coupled Drive

v+

v+

IL

c)'5V
INPUT FROM
PWMIC

V.
ICL7667

T1-IS THREE TURNS 30 BIFILAR ON A
FERRITE BEAD.

Figure 6.

Very High·Speed Driver

5·133

-185V

IC,,7661
I

OTHER APPLICATIONS
RELAY AND LAMP DRIVERS
The ICL7667 is suitable for converting low power TIL or CMOS
signals to high current, high voltage outputs for relays, lamps
and other loads. Unlike many other level translator/driver ICs,
the ICL7667 will both source and sink current. The continuous
output current is limited to 200mA by the 12R power dissipation in the output FETs.

CHARGE PUMP OR VOLTAGE INVERTERS AND DOUBLERS
The low output impedance and wide Vee range of the ICL7667
make it well suited for charge pump circuits. Figure 7 shows a
typical charge pump voltage inverter circuit and a typical performance curve. A common use of this circuit is to provide a
low current negative supply for analog circuitry or RS232
drivers. With an input voltage of +15V, this circuit will deliver
20mA at -12.6V. By increasing the size of the capaCitors, the
current capability can be increased and the voltage loss
decreased. The practical range of the input frequency is 500Hz
to 250kHz. As the frequency goes up, the charge pump capacitors can be made smaller, but the internal losses in the
lCL7667 will rise, reducing the Circuit efficiency.

Figure 8,a voltage doubler, is very similar in both circuitry and
performance. A potential use of Figure 8 would be to supply
the higher voltage needed for EEPROM or EPROM programming.

CLOCK DRIVER
Some microprocessors (such as the 68XX and 65XX families)
use a clock signal to the various LSI peripherals of the family.
The ICL7667's combination of low propagation delay, high current drive capability and wide voltage swing make it attractive
forthis application. Although the ICL7667 is primarily intended
for driving power MOSFET gates at 150r 20 V, the ICL7667 also
works well as a 5V high-speed buffer. Unlike standard 4000
series CMOS, the ICL7667 uses short channel length FETs and
the ICL7667 is only slightly slower at 5 V than at 15 V.

+15

~~~:RHiwAVEIN

TTL LEVELS

I

+15

-1-+~_~_~_+28.5V

*..

V,
ICL7667

10~F

+

147~F

+15
IN4OO1

. If"""'-+""""""_- -13.5V

1·250 ••. "
SQUARE WAVE IN
TTL LEVELS

Figure 8.

>~

Voltage Doubler

CHIP TOPOGRAPHY
Figure 7a.

Voltage Inverter

4
6

SLOPE =60
~

_10k'!.

OUT
A

.... """

III!'K

5

t - 6.= ISUPPLY V8. - VOUT
I-- • I 1~kH~ C~O~K ~AT~
20

40

60

80

100

lOUT-rnA

Figure 7b.

Voltage Inverter

IN A

5·134

IN 8

ICL8001
Precision Comparator

ABSOLUTE MAXIMUM RATINGS

FEATURES
•
•
•
•
•

Low Input Current -:; 250 nA
Low Power Consumption 30 mW
Large Input Voltage Range> ±lOV
Low Offset Voltage Drift 3 "Mvtc
Output Swing Compatible with Bipolar Logic

GENERAL DESCRIPTION
The Intersil 8001 integrated circuit is a monolithic volt
age comparator featuring low input currents, low power
consumption, and 250 ns response time. A versatile output
stage enables the designer to control the output voltage
swing. The use of thin film resistors ensures excellent long
term stability and the device is particularly suitable for
low power space and airborne applications.

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±lBV
Input Voltage (Note 2). . . . . . . . . . . .
. .... ±lBV
Differential Input Voltage. . . . . . . . ..
. . . . . . . . . ±15V
Internal Power Dissipation (Note 1) . . . . . . . . . . . . 500 mW
Peak Output Current . . . . . . . . . . . . . . . . . . . . . . . 15 mA
Storage Temperature Range . . . . . . . . . . . . -65°C to +150°C
Operating Temperature Range
(B001C) . . . . . . . . . . . . . . . . . . . . . . . . . O°C to +70°C
(8001M) . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . 300°C

EQUIVALENT CIRCUIT

SCHEMATIC DIAGRAM
~-_-o OUTPUT

NON-INVERTING

INPUT
9V
INVERTING
INPUT

O~T

v-

GND

NULL

PIN CONFIGURATION
NON-INVERTING

INPUT

TOP VIEW

(outline dwg TO-l00)
NOTE: Pin 5 connected to case.

r=

ORDERING INFORMATION
8001

'!.i-

L = C Pock'ge
L - TZ
TO 100
Temperature Range
C - Commercial (O°C to t70°C)
M - MiIitary (_55°C to + 125°C)

De . . lce ChIp Type

I"or notes and additional electrical characteristics, see next page.

5-135

ICL8001
ELECTRICAL CHARACTERISTICS

(V++ = 15V, V+

5V, V- = :-15V unless otherwise specified)

...

PARAMETER

CONDITIoNS

MIN

8001M
TYP

MAX

MIN

8001C
TYP

MAX

UNITS

The following specifications apply for
T A • +25°C:
Rs~ 10kf!

Input Offset Voltage

0.5

1.0

3.0

5.0

2

20

10

50

Input Bias Current

40

100

50

250

Input Resistance

10

Input Offset Current

V OUT

Power Consumption

= 2.5V

30

30

nA
nA
M~!

10
60.

mV

60

mW

The following specifications apply for
-55°C:<;; TA :<;; +125°C (B001M)
O°C:<;; T A :<;; +70°C (B001C)
Rs~ 10kf!

Input Offset Voltage

4.0

Average Temperature Coefficient

2.0

6.0
3.0

20

30

mV
jJ.vtc

of Input Offset Voltage
7

Input Offset Current

100

15

250

Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio

100

35

35

Average Temperature Coefficient
of Input Offset Current

300

±12

±10

±12

V

70

90

70

90

dB

300

300

Differential Input Voltage Range

±15

± 15

Positive Output Level

15,000
Ma~

Negative Output Level

(Note 3)

V+·+15V

nA

±10

Supply Voltage Rejection Ratio

Vol tage Gai n

nA
pAtC

7.0

500

250

V
V/V

9.0
200

250

Response Time (Note 4)

60,000

7.0

9.0
200

At 2 rnA Sink Current

15,000

60,000

jJ.VIV

V
400

mV
ns

NOTE 1: Rating applies for ambient temperatures to +70oC.
NOTE 2: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
NOTE 3: Positive output level can be adjusted below 9V by changing V+. See circuit.
NOTE 4: The response time specified is for a 100 mV input step with 5 mV overdrive.
NOTE 5: Input bias current is independent of V-.

CIRCUIT NOTES:
.f15V

'+sv

OUTPUT LEVEL COMPATIBLE
WITH TTL, DTL, ETC.

VOLTAGE OFFSET
NULL CI RCUIT

NOTE: As with all high gain comparators, care must be taken to avoid feedback between output and input. Where possible, hysteresis
should be used to provide a small deadband.

5-136

ICL8001
TYPICAL PERFORMANCE CURVES

INPUT BIAS CURRENT

INPUT BIAS CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE
100

1 80
§

70

~

60

13

50

~

I'.

~

i'
........

--

I-

~

;(

80

I- 40

.E

z

w

70

a:
a:
::>
u

60

U)

40

a:
a: 30
::>

(J

50

'"

iii

I-

f- r-

,.--

w

...0~

30

I-

-60

-20

+20

+60

+100

..

o

0

+140

5

6

7

8

-60

9 10 11 12 13 14 15

POWER CONSUMPTION
AS A FUNCTION OF
AMBIENT TEMPERATURE

COMMON MODE RANGE
AS A FUNCTION OF
SUPPLY VOLTAGE

~

~

V-~-15V

z
o

,13

w

-.::::: I-

640
u
a:
w

~ 20

- - t-

t-

til

-20

+20

+60

o

'/

~
w

r

.'1

I
I
':'-;-+125°C

~'

'"..:

I-

-'

-I--- f--~

0

>

I-

~

+25°C

::>

I

I-

0

~~

1-":
::>10-'
0

>

/

"

-40

o

..

0

13

/

V

V

15

11

4

RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES

~

2

'.1

+40

INPUT VOLTAGE IVI

+100

~

-100

>

!olv.t+-

-5 mV, -2 mV

Il!
'>E

+100

o

!.0.-

mV ••.......

E

;

I
-20 mV ~11

0

.... -

~0

10

I +2 mV
f-+-+--1II-"\'~~~-I+;~:~ : : : :
1--t-+--+--'.J~.+10

15

13

V·

;;

t:

IA

o
-100

10

'>

,L -I

I

/

in

RESPONSE TIME FOR
VARIOUS INPUT
OVERDRIVES

- ..jJ

>

SUPPLY VOLTAGE IVI

VOLTAGE TRANSFER
CHARACTE RISTI CS
I
·-55'C_

w

;::

11

+140

TEMPERATURE lOCI

10

::>
0

I
I I

'/

u

+100

::>

I-

--r::EGATIVE LIMIT

7

:;;
:;;

IL
-60

l- II

A

:;;

15

13

..

POSITIVE LIMIT

o
o

I-

+140

~

'"
a: 11

f-

+100

15

~
<:J
z

z

Sl

+60

POSITIVE OUTPUT SWING
AS A FUNCTION OF V+

<:J

60

+20

TEMPERATURE lOCI

15

E BO

-20

POSITIVE SUPPLY V H

V" '" +15V
V· '" +5V

r-.....

~

TEMPERATURE lOCI

~

~ ......

::> 10

10

'"

o

20

I-

~ 20

20
10

z

90

z

w

r-.....

50

100

I-

40
30

Qj

V++ INOTE 51

,

,

90

INPUT OFFSET CURRENT
AS A FUNCTION OF
AMBIENT TEMPERATURE

AS A FUNCTION OF

t- ~ +100

~~
o

0

- ~ -100

200

400
TIME Insl

5-137

600

800

o

>

o

200

400
TIME (ns)

600

800

ICL80()1
CIRCUIT AND APPLICATION NOTES
INPUT

>-1>---0. OUTPUT
OUTPUT

R 1 - Rs for minimum

Vos end drift.
VflEf

SIMPL.E VOL. TAGE· L.EVEL. OETECTOR

COMPARATOR WITH HYSTERESIS

+5V

SET

UG::i~o---~

»-......- 0 a
OUTPUT

INPUT

II

SET L~~Wo--_~

USE OF EXTERNAL NAND GATES TO PROVIDE
OUTPUT STORAGE

CONNECTION TO PROVIDE L.OGICAL. OR OF
TWO COMPARATOR OUTPUTS

ANALOG
INPUT

A TO D CONVERTER

WINDOW DETECTOR

5·138

ICL8007
FET Input
Operational Amplifier
GENERAL DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

The I ntersil 8007 integrated circuit is a low input current
FET input operational amplifier. The 8007A is selected for
4 pA max input current.

Supply Voltage
I nternal Power Dissipation (Note 1)
Differential I nput Voltage
Input Voltage (Note 2)
Storage Temperature Range
Operating Temperature Range

±18V
500mW
±30V
±15V
-65°Cto +150°C

8007M,8007AM
8007C, 8007 AC
Lead Temperature (Soldering, 10 sec.)
Output Short-Circuit Duration (Note 3)

-55°C to +125°C
O°C to +70°C
300°C
Indefinite

The devices are designed for use in very high input imped·
ance applications. Because of their high slew rate, high
common mode voltage range and absence of "latch-up",
they are ideal for use as a voltage follower.

NOTES:

The Intersil 8007 and 8007A are short circuit protected.
They require no external components for frequency compensation because the internal 6 dB/roil-off i.nsures stability
in closed loop applications. A unique bootstrap circuit
insures unusually good common mode rejection for an FET
input amp and prevents large input currents as seen in some
amplifiers at high common mode voltage.

1. Rating applies for case temperatures to 12SoC; derate linearly at

6.5 mW/oC for ambient temperatures above +75°C.
2. For supply voltages Jess than ±15V, the absolute maximum input
voltage is equal to the supply voltage,

3. Short circuit may be to ground or either supply. Rating applies

to + 12SoC case temperature or +7SoC ambient temperature.

EQUIVALENT CIRCUIT

TRANSIENT RESPONSE
TEST CIRCUIT

r-~--------~--------~----~--ov'

OUTPUT

PIN CONFIGURATION (outline dwg TV, TY)"

ORDERING INFORMATION

Part
Number

"v,TOP VI{W,

ICL8007C
ICL8007AC
ICL8007M
ICL8007AM

Temperature
Range
O°C to +70'C
55°C to + 125°C

dice

To-99
Can

ICL8007C/D
ICL8007AC/D
ICL8007M/D
ICL8007AM/D

ICL8007CTY
ICL8007ACTV
ICL8007MTY
ICL8007AMTV'

• Add 1883B to order number if 883B processing is desired.

"ICLaOO?M/C pin 4 connected to case (TY package)
ICLaOO? AM/C, pin a connected to case (TV package)

5-139

ICL8007
,

ELECTRICAL CHARACTERISTICS (V s = ±15V unless otherwise specified)
'
;

I

CHARACTERisTICS

8007M

CONDITIONS

8007 AM & 8007AC

8007C

TYP

MIN

MAX

MIN

TYP

MAX

20
0,5

50

3.0

50

MIN

TYP

MAX

15

30

UNITS

The following speciftcaticms apply for T A" 2S"C:

Input Off"'t Voltage
Input Ofhet Current

Rs';: 100 kf!

Input Current (either input)
Input Resistance
Input Capacitance

10
0,5

20

2,0
10·

20

RL 2 2 k!l, VOUT = ±10V

0.5
10·

10·
2,0

2.0

Large Signal Voltage Gain

0;2

50,000

pA
4,0

pA
M!l
pF

2.0

20,000

mV

20,000

V/V

Output Resistance

75

75

75

!l

Output Short-Circuit Current

25

25

25

mA

Supply Current

3.4

5.2

102

Power Consumption

Slew Rate
Unity Gain Bandwidth
Transient Response (Unity Gain)
Risetime

3.4

180

6.0

6.0

1.0

1.0

102
2.5

6.0
180

6.0

mA
mW
VII'S
MHz

1.0

CL ';: 100 pF, RL = 2 k!l

Overshoot
The following specifications applV for

6,0

3.4
102

156

oCe $. TA, $. +70"C

300

300

300

ns

10

10

10

%

t8001C and 8007ACI, -5S"C ~ T A ~ +12SQ C (8007M and 8007AM):

Input Voltage Range

±1O

±12

±10

±12

±10

±12

V

70

90
70

70

90

86

95

dB

Common Mode Rejection Ratio

Supply Voltage Rejection Ratio
Large Signal Voltage Gain

70

300

25,000

600

70

15,000

200

15,000

Output Voltage Swing

RL21Ok!l

±12

±14

±12

±14

±12

±14

±10

±13

±10

±13

±10

±13

I nput Current (either input)

RL 2 2 k!l
TA = +125°C
TA = +70oC

2.0

V

1.0
50

Average Temperature Coefficient
of Input Offset Voltage

30
75

75

/JV/V
V/V
V

50

nA
pA
/JV/oC

tYPICAL PERFORMANCE CURVES
OPEN LOOP
VOLTAGE GAIN
10'
10'

z

""
w

10'
10'

>

10

0

i"\.

10'

".......


...

~

\

-4

~

VsuI>P = ±15V
T. = 25°C

"~
Z

'+r++

...:>
......

"~


,!OUTPUT

0 1 2 3

40

V>

f I

INPUT

0

0

10k lOOk 1M 10M

FREQUENCY 1Hz)

0

ii:....
:>

~
\

1

~

w

"

I
I
I

8

TA=+2SoC

1

OUTPUT VOLTAGE SWING AS
A FUNCTION OF FREQUENCY

VOL TAGE FOLLOWER LARGE·
SIGNAL PULSE RESPONSE

g

16
8

0
lk

10k

lOOk

1M

FREQUENCY IHzl

10M

ICLa007

INPUT CURRENT AS A
FUNCTION OF TEMPERATURE

TRANSIENT RESPONSE

OUTPUT SWING AS A FUNCTION
OF SUPPLY VOL TAGE

28

20
T A" 25"C

24

AL '" :;> kf1:

20

0;
~
>-

ii'>-

90',.

16

~

I

12
--

::0

0

10'\

w

----{

::0

U
>-

VS"'!1SV

__11_

~

1.5

2.0

'">-::0

107

10

/

POSITIVE SWING./

>-

/

::0

./

./V
/"

/

0-

V

0

10

j/

V

NEGATIVE SWING

N

~

1.0
TIME

./

ii'z

RISE TIME T A " 25'C
R, " 2 kll
C l "'100pF

15

§i;

a:
a:

I
I

'I--

10 3

~
<.:J
z

2.5

<:

1

::;

o

40

60

80

100

120

10

140

15

20

SUPPLY VOLTAGE I'VI

TEMPERATURE I'CI

z

OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF

./
20

a:

(.us~

SUPPL Y VOLTAGE

INPUT VOL TAGE RANGE AS
A FUNCTION OF SUPPLY VOLTAGE

0;

~

QUIESCENT SUPPLY CURRENT
AS A FUNCTION OF SUPPLY
VOLTAGE

20

w
<.:J

2:
z

I

~

15

Z

;;'

<:
a:

~ 10~

C;
<:
>-

o

g

POSITIVE /...

0-

o

2S":C

/

/

...-

VNEGATIVE

/ /
V

...

W

=

A/

10

a>

z

TA

ii'
;!;

-~

10'
10

15

10

20

SUPPLY VOLTAGE I'vi

15

20

QUIESCENT SUPPLY CURRENT
AS A FUNCTION OF TEMPERATURE

INPUT VOL TAGE NOISE AS
A FUNCTION OF FREQUENCY

-;;; 1000

HI'

E

'3
w

Ii

::;.

--

r- r-

- -r-

w
<.:J

..:

>-'

As

0

> 10'

....

w

= 1 Mn

8a:

Rs" 50n

w
u.
w

...a:

25

65

TEMPERATURE I'CI

105 •

10

100

1k

10k

FREOUENCY IHzl

For additional information, see Application Bulletin A005 ..

5·141

10.0

~

>-

./

"

./

I-'

10
BANDWIDTH
0.1 Hz TO 1

i.:z

III I I
-15

f-- BANDWIDTH
f--" 10 Hz TO 100 kHz

a:

z

-55

100

'"6z

10'

'"6
o

20

WIDEBAND NOISE AS A FUNCTION
OF SOURCE RESISTANCE

Vs'" +15V

OS

15

10

SUPPLY VOLTAGE I!VI

SUPPLY VOLTAGE I'VI

ktz===

01
lOOk

100

1k

10k

lOOk

1M

10M 100M

SOURCE RESISTANCE Inl

ICL8008
Low Input Current
Operational Amplifier
FEATURES

GENERAL DESCRIPTION

•
•
•
•
•
•

The 8008 is a high performance monolithic operational
amplifier with very low input currents. his intended for
a wide range of analog appliCations. High common mode
voltage range and absence of "latch-up" tendencies make
the 8008 ideal for use as a voltage follower. The high gain
and wide range of operating voltages provide superior performance in integrator, summing amplifier, and general
feedback applications. The 8008 is short-circuit protected,
has the. same pin configuration as the popular 741 operational amplifier, and requires no external components for
frequency compensation. The internal 6 dB/octave roll-off
insures stabii'ity in closed loop applications.

Low Input Current
No Frequency Compensation Required
Offset Voltage Null Capability
Large Common-Mode and Differential Voltage Ranges
Low Power Consumption
No Latch up

SCHEMATIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Internal Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage (Note 2)
Voltage between Offset Null and VStorage Temperature Range
Operating Temperature Range
8008M
8008C
Lead Temperature (Soldering, 60 sec.)
Output Short-Circuit Duration (Note 3)

PIN CONFIGURATIONS

e
TO-5

OF~~~~

I

I

,,0'" "'VE~TJN(;
I~PuT

V'

~

1

3

•

~

±30V
±15V
±0.5V
-65°C to +150°C
_55°C to +125°C
O°C to +70°C
300°C
Indefinite

Plastic DIP

:<

'NVf~~~~~

±18V
500mW

o'::~:O"'
,,.PUT

OUTPUT

''''UT

.;

,-

OuTPuT

OfFS:r

..va

(outline dwg TV)
NOTE: Pin 4 CONNECTED TO CASE

V

e~~~H

NOTE 1: Rating applies for case temperatures to 125°C; derate
linearly at 6.5 mWrC for ambient temperatures above
+75°C.
NOTE 2: For supply voltages less than ±15V, the absolute maximum input voltage is equal to the supply voltage.
NOTE 3: Short circuit may be to ground or either supply. Rating
applies to +125°C case temperature or +75°C ambient
temperature.

(outline dwg PAl

ORDERING INFORMATION
ICL8008

M

TV

1

Package:
TV-TO-99 metal can
PA-a Pin Plastic DIP (Available
only at Commercial Temperature
Range) 10 Dice
Temperature Range:
M-Military -55°C to +125°C
r, -Commercial O°C to + 70°C
Device Type

5-142

ICL8008
ELECTRICAL CHARACTERISTICS
CHARACTERISTICS

= ±15V

unless otherwise specified)

CONDITIONS

The following specifications apply for TA

Input Offset Voltage
Input Offset Current
Inpu.t Bias Current
Input Resistance
Input Capacitance
Offset Voltage Adjustment Range
Large-Signal Voltage Gain
Output Resistance
Output Short-Circuit Current
Supply Current
Power Consumption
Transient Response (unity gain)
Risetime
Overshoot
Slew Rate (unity gain)

(V s

SOOSM
TYP

MIN

MAX

MIN

SOOSC
TYP

= 25°C:

As':;:

RL

~

MAX

UNITS

-

10 kfl

1.0
1.0
2
25
5
1.5
±15
20,000 200,000
75
25
1.7
50

2 kfl, V OUT = ±10V

V ,N = 20 mV, RL
C L ':;:100pF

=

5
5
10

2.S
S5

1.0
2.0
5
25
5
1.5
±15
20,000 200,000
75
25
1.7
50

6.0
20
25

2.S
85

mV
nA
nA
Mfl
pF
mV
VN
fl
mA
mA
mW

2 kfl,
0.3
5.0
0.5

RL ~ 2 kfl

0.3
5.0
0.5

IlS
%

V/lls

The following specifications apply for O°C -< TA -< +70°C IBOOBC). -SSoC -< T A -< + 12SoC IBOOBM):

Input Offset Voltage
Input Offset Voltage Average
Temperature Coefficient
Input Offset Current

Rs':;: 10kfl

1.5

Rs':;: 10kfl

7

6

±10
70

±12
90
30

Rs':;: 10 kfl
Rs':;: 10 kfl
RL~ 2 kfl, V OUT = ±10V 15,000
±12
R L ?:10kfl
±10
RL?: 2kfl

7.5

30

30

nA

50

50

nA

±12
70
150
15,000
±12
±10

±14
±13

mV

Ilvtc

15

Input Bias Current
Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing

1.5

±13
90
30

V
dB
IlVN
VN
V
V

150

±14
±13

TYPICAL PERFORMANCE CURVES
OPEN LOOP VOLTAGE
GAIN AS A FUNCTION
OF SUPPLY VOLTAGE

OPEN LOOP VOLTAGE
GAIN AS A FUNCTION
OF FREOUENCY

Hf
10'

z

;(

"
"..:~
w

0

>

10"

10"

II

T. - 25°C

Vs = ±15V _

~

10"

"-

10'

z

"~

lk

-

w

"-

10- 1

100

=

10'

....

c5

"'"'"[\

10k lOOk 1M 10M

FREOUENCY 1Hz)

>

24

20

;(

10

10

5 x 10'

T. = 25°C

TRANSIENT RESPONSE
28

5)(

5'>

16

~

12

....

90%

I

I

::J

10"

o

o

-r

V s ::±15V

t- RISE TIME T.R, - 2 kllC

t-10%

_

0

25

=

C,

= 100

1.5

2.0

pF

10"

10

20

15

SUPPL Y VOLTAGE ltV)

CIRCUIT NOTES:
TRANSIENT RESPONSE
TEST CIRCUIT

VOLTAGE OFFSET
NULL C( RCUIT

5-143

1.0

TIME

(~s)

2.5

ICLS013
Four Quadrant Analog Multiplier

FEATURES

GENERAL DESCRIPTION

•
•
•
•
•

The ICL8013 is a four quadrant analog multiplier whose
output is proportional to the algebraic product of two input
signals. Feedback around an internal op-amp provides level
shifting and can be used to generate division and square root
functions. A Simple arrangement of potentiometers may be
used to trim gain accuracy, offset voltage and feedthrough
performance. The high accuracy, wide bandwidth, and
increased versatility of the ICL8013 makes it ideal for all
multiplier applications in control and instrumentation
systems. Applications include RMS measuring equipment,
frequency doublers, balanced modulators and
demodulators, function generators, and systems process
controls.

Accuracy of ±O.5% ("An version)
Full ±10V I/O voltage range
1 MHz bandwidth
Uses standard ±15V supplies
Built in op amp provides level shifting, division and
square root functions.

BLOCK DIAGRAM (MULTIPLIER)

X,N
Xos

VOLTAGE TO CURRENT
CONVERTER AND
SIGNAL COMPRESSION

OUTPUT

Y,N
Yos

PIN CONFIGURATION

ORDERING INFORMATION
TEMPERATURE MULTIPLICATION ORDER PART
NUMBER
TYPE
RANGE
ERROR
ICL8013AM TZ
ICL8013AM -55'C to +125°C
±.5%}
±1% MAX
ICL8013BM TZ
ICL8013BM -55°C to +125°C
+2%
ICL8013CM TZ
ICL8013CM -55°C to +125°C
ICL8013AC TZ
ICL8013AC
O°Cto +70°C
±.5'10}
ICL8013BC TZ
ICL8013BC
O°.C to +70°C
±1'10 MAX
+2%
ICL8013CC TZ
ICL8013CC
O°C to +70°C
DICE

O°C to +70°C

±2'10 TYP

ICL8013C/O

Yos

v·
TOP VIEW

(outline dwg

5-.144

TO-100)

.D~DIL

ICLS013
o

ABSOLUTE MAXIMUM RATINGS
Supply Voltage .................................. ±18V
Power Dissipation (Note 1) .................... 500 mW

Input Voltages (X, V, Z, XO, Va, Zo) .....•..•..... Vsupp
Lead Temperature (soldering, 10 sec) ....•....... 300°C
Storage Temperature Range ....•.....• --tl5°C to +150°C

NOTE 1: Derate at 6.B mW/o C for operation at ambient temperature above 75 0 C.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of'lhe device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

"

ELECTRICAL CHARACTERISTICS
(Unless otherwise specified TA

= 25°C

PARAMETER
Multiplier Function
Multiplication Error

Vsupp

= +15V
-

CONDITIONS

Gain and Offset Potentiometers Externally Trimmed)
ICL8013C
ICL8013A
ICL8013B
MIN TYP MAX MIN TYP MAX MIN TYP MAX
XY
XY
XY
.5
10Z

Divider Function
Division Error
Feedthrough
Nonlinearity
X Input
Y Input
Frequency Response
Small Signal Bandwidth (-3dB)
Full Power Bandwidth
Slew Rate
1% Amplitude Error
1% Vector Error
(0.50 Phase Shiftl
Settling Time
(to ±2% of Final Value)
Overload Recovery
(to ±2% of Final Value)
Output Noise

10

10

10
-10 < X < 10
-10 VOUT = OV
Y-

In Figure 48, notice that with VIN = 0 any variation in the ratio
of biasing current sources will produce a common mode
voltage across the load resistors. The differential output
voltage will remain zero. In Figure 4C we apply a differential
input voltage with unbalanced current sources. If IE1 is twice
IE2, the gain of differential pair 01 and 02 is twice the gain of
pair 03 and 04. Therefore, the change in cross coupled
collector currents will be unequal and a differential output
voltage will result. 8y replacing the separate biasing current
sources with the voltage to current converter of Figure 3 we
have a balanced multiplier circuit capable of four quadrant
operation (Figure 51.

Figure 5: Typical Four Quadrant Multiplier-Modulator
Figure 3 showed a current source formed by relying on the
matching characteristics of a diode and the emitter base
junction of a transistor. Extension of this idea to a differential
circuit is shown in Fig. 6A. In a differential pair, the input
yoltage splits the biasing current in a logarithmic ratio. (The
usual assumption of linearity is useful only for small signals,)
Since the input to the differential pair in Figure 6A is the

XOIEI

(I - X) IE

I

1(1-

X) ID

v+

~I +.;

RL

1/2 i;= 2..l

~ 1/2 IE + ~

Figure 6A: Current Gain Cell

v+

Figure 4C: Input Signal with Unbalanced Current Sources,
Differential Output Voltage

This circuit of Fig. 5 still has the problem that the input
voltage VIN must be small to keep the differential amplifier in
the linear region. To be able to handle large signals, we need
an amplitude compression circuit.

5-147

y-

Figure 68: Voltage Gain with Signal Compression

ICLa013
difference in voltage across the two diodes, which in turn is
proportional to the log of the ratio of drive currents, it follows
that the ratio of diode currents and the ratio of collector
currents are linearly related and independentofamplitude.1f
we combine this circuit with the voltage to current converter
of Fig. 3, we have Fig. 68. The output of the differential
amplifier is now proportional to the input voltage over a large
dynamic range, thereby improving linearity while minimizing
drift and noise factors.

The complete schematic is shown in Figure 7. The
differential pair 03 and 04 form a voltage to current
converter whose output is compressed in collector diodes
01 and 02. These diodes drive the balanced cross-coupled
differential amplifier 07/08 014/015. The gain of these
amplifiers is modulated by the voltage to current converter
09 and 010. Transistors 05,06,0", and 012 are constant
current sources which bias the voltage to current converter.
The output amplifier comprises transistors 016 through 027-

Z,N
R33

Zos
R30

R28

OUTPUT
R29

Yos
Xos

Figure 7: ICL8013 Schematic

MULTIPLICATION
In the standard multiplier connection, the Z terminal is
connected to the op amp output. All of the modulator output
current thus flows through the feedback resistor R27 and
produces a proportional output voltage.

EOUT =

x
y

Figure 8A: Multiplier Block Diagram

x1•0y

MULTIPLIER Trimming Procedure
1. Set XIN = YIN = OV and adjust Zos for zero Output.
2. Apply a ±10V low frequency (~100Hz) sweep (sine or
triangle) to YIN with XIN = OV, and adjust Xos for minimum
output.
3. Apply the sweep signal of Step 2 to XIN with YIN = OV and
adjust Yos for minimum Output.
4. Readjust Zos as in Step 1, if necessary.
5. With XIN = 10.0V DC and the sweep signal of Step 2
applied to YIN, adjust the Gain potentiometerforOutput=
YIN. This is easily accomplished with a differential scope
plug-in (A + B) by inverting one signal and adjusting Gain
control for (Output - YIN) = Zero.

DIVISION

X,N o-----"i

YIN~
Sk

7.Sk

If the Z terminal is used as an input, and the output of the opamp connected to the Y input, the device functions as a
divider. Since the input to the op-amp is at virtual ground,
and requires negligible bias current, the overall fee:dback
forces the modulator output current to equal the current
produced by Z.
Therefore 10 =

Xos YosZos

x.y = ~ =

Since Y = EOUT, EOUT =
Figure 8B: Actual Circuit Gonnection

5-148

10Z

1~Z

ICLS013
Note that when connected as a divider, the X input must be a
negative voltage to maintain overall negative feedback.

z
7.SkO

Figure lOB: Actual Circuit Connection

SQUARE ROOT
Tying the X and Y inputs together and using overall feedback
from the Op Amp results in the square root function. The
output of the modulator is again forced to equal the current
produced by the Z input.

Figure 9A: Division Block Diagram
Xos Yas Zos

7 10
X'N

9

(0 TO - lOY) 6

10 =

X-Y = ( - EOUT)2 = 10Z

Z'No----~

EOUT = -

y'lOZ

The output is a negative voltage which maintains overall
negative feedback. A diode in series with the Op Amp output
prevents the latchup that would otherwise occur for negative
input voltages.

7.Sk

Figure 9B: Actual Circuit Connection

z

DIVIDER Trimming Procedure

1. Set trimming potentiometers at mid-scale by adjusting
voltage on pins 7,9 and 10 (Xos, Yos, Zos) for zero volts.
2. With ZIN = OV, trim Zos to hold the Output constant, as XIN
is varied from -10V through -1V.
3. With ZIN = OV and XIN =-10.0V adjust Yos for zero Output
voltage.
4. With ZIN = XIN (and/or ZIN = -XIN) adjust Xos for minimum
worst-case variation of Output, as XIN is varied from -10V
to -1V.
5. Repeat Steps 2 and 3 if Step 4 required a large initial
adjustment.
6. With ZIN = XIN (and/or ZIN = -XIN) adjust the gain control
until the output is the closest average around +10.0V
HOV for ZIN = -XIN) as XIN is varied from -10V to -3V.

Figure llA: Square Root Block Diagram

IN4148

OUTPUT = - y10Z

L-----------------__
?5k
GAIN
7.5k

SQUARING
The squaring function is achieved by simply multiplying with
the two inputs tied together. The squaring circuit may also be
used as the basis for a frequency doubler since cos 2 w = 1/2
(cos 2w + 1).

Figure llB: Actual Circuit Connection

z
SQUARE ROOT Trimming Procedure
1. Connect the ICL8013 in the Divider configuration.
2. Adjust Zos, Yos, Xos, and Gain using Steps 1 through 6 of
Divider Trimming Procedure.
.

x

3. Convert to the Square Root configuration by connecting
XIN to the Output and inserting a diode between Pin 4 and
the Output node ..
4. With ZIN = OV adjust Zos for zero Output voltage.

Figure lOA: Squarer Block Diagram

5-149

ICLS013
VARIABLE GAIN AMPLIFIER

z 3r---,

, Most applications for thelCL8013 are strai.ght forward
variations of the simple arithmetic functions described
above. Although the circuit description frequently disguises
the fact, it has al ready been shown that the frequency
doubler is nothing more than a squaring circuit. Similarly the
variable gain amplifier is nothing more than a multiplier, with
the input signal applied at the X input and the control voltage
applied at the Y input.

~~~A~; ~05k

: 7

YOLTAGE

Xos Yas Zos

7Sk

Figure 12: Variable Gain Amplifier

TYPICAL APPLICATIONS
POTENTIOMETERS FOR
TRIMMING OFFSET AND FEEDTHROUGH

MULTIPLICATION

y+
X,N<>----=-J

Zoso--

20k

SQUARE ROOT
DIVISION
Xos Vas Zos
(0 TO _ lOY)

7 10

9

X,N

IN4148

OUTPUT ~ - .j1ilz

Z,No----...l

GAIN

5k

7.5k

7.5k

TYPICAL PERFORMANCE CURVES
AMPLITUDE AND PHASE AS
A FUNCTION OF FREQUENCY

FEEDTHROUGH AS A
FUNCTION OF FREQUENCY

NONLINEARITY AS A
FUNCTION OF FREQUENCY

w
....
,...

iii'

:!!.
w

c

~ 10

~

I
I
I\~

~4
S.

]'I~

~

\~

15

~

ilJ

:;
..: 20

I

25
lk

10k

lOOk

1M

FREQUENCY (Hz)

-50
10M

~

100

-10 nTTT"TiTTT"TiTTT"TiT1i1

....
....
~

~

a

10

IL

o

~

HtH-t-ttH-t-ttH-t-ttH-1

-30

:::l

x- I

~

z
:::;
z
oz

-20

.1

~ ~o HtH-t-ttH-~~~tH-1

PUT

~

Y -INPUT

--50

w

~ -50~~~~tt~tt~
-70

100

lk

10k

FREQUENCY (Hz)

DEFINITION OF TERMS
Multipfication/Division Error: This is the basic accuracy
specification. It includes terms due to linearity, gain, and
offset errors, and is expressed as a percentage of the full
scale output.
Feedthrough: With either input at zero, the output of an ideal
multiplier should be zero. regardless of the signal applied to

5-150

lOOk

t:t!jit:t::jt:l:l:t:tll.I.L.J.j,UU

lk

10k

lOOk

1M

10M

FREQUENCY (Hz)

the other input. The output seen in a non-ideal multiplier is
known as the feedthrough.
Nonlinearity: The maximum deviation from the best straight
line constructed through the output data, expressed as a
percentage of full scale. One input is held constant a~'d the
other sw.ept through its nOminal range, The nonlinearity is
the component of the total multiplication/division error
which cannot be trimmed out.

ICL8017
High Speed
Inverting Amplifier
FEATURES

APPLICATIONS

• 130 VljJ.s Slew Rate
• Fast Settling Time
• 50 nA Input Current
• 10 MHz Bandwidth
• Simple Frequency Compensation
• Short Circuit Protection

•
•
•
•
•
•
•

High Speed Inverting Amplifier
DIA Converter
AID Converter
Pulse Amplifier
Active Filter
Sample and Hold Circuit
Peak Detector

GENERAL DESCRIPTION
The 8017 integrated circuit is a high speed inverting
.itmplifier combining excellent input characteristics with
wide bandwidth and high slew rate. Frequency compensa·
tion is achieved with the minimum number of external
components. The high slew rate and fast settling time
ensure exceptional performance in high speed data acquisi·
tion circuits. Full power bandwidth of 2 MHz makes the
8017 amplifier suitable for all applications where large
amplitude, high frequency signals are encountered.

VOLTAGE OFFSET NULL CIRCUIT
+'5\1

TOK[)

The 8017 is available in the military version, 8017M, with a
temperature range from _55°C to +125°C and in the commercial version, 8017C, from O°C to + 70°C.

SCHEMATIC DIAGRAM

1000
"OUT

10Kn

-1SV

PIN CONFIGURATION
FEEOFORWARD

,.:~~.... o

.

"'~":f:~ ~"'i':fM

V·
TOP VIEW

(outline dwg TO·l00)

11

ORDERING INFORMATION

leLB017 M

TW

L .....ge: TW - TO·l00 metal can
Temperature Range

M - Military (-55°C to +125°C)

C - Commercial (DoC to JOOe)
,

Device Chip Type

5-151

ICL 8017
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Power Dissipation (Note 1)
Differential Input Voltage
Input Voltage (Note 2)
Operating Temperature Range
ICLB017M
ICLB017C
Storage Temperature Range
Lead Temperature (60 sees)

±lBV
500mW
±30V
±15V
-55°C to +125°C
O°C to +70°C
-65°C to +150°C
300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation ofthe device atthese or any other conditions above those indicated in the operational sections ofthe specifications is not
'
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS (V s ; ±15V)

PARAMETER

CONDITIONS

MIN

S017M
TYP

MAX

MIN

S017C
TYP

MAX

UNITS

The following specifications apply for T A; 2SoC:

Input Offset Voltage

2.0

I nput Current

50

Input Noise Voltage (rms)

10 Hzto 1 MHz

Large Signal Voltage Gain

R L ;2kn

5.0

2.0

200

50
20

20
25

7.0
200

1000

25

mV
nA
p.V

1000

V/mV

Output Resistance

75

75

n

Output Short-Circuit Current

25

25

mA

Supply Current

V OUT

;

OV

Power Consumption

V OUT

;

OV

Slew Rate

Rsw; 20 kn

130

130

V/p.s

Unity Gain Bandwidth (Note 3)

Rsw; 20 kn

10

10

MHz

Transient Response (Note 3)

Unity Gain, Rsw ; 20 kn
30

30

ns

5

5

%

1.0

1.0

p.s

3.5

3.5

p.s

5.0
150

Risetime
Overshoot
Settling Time (0.1 %) (Note 3)
(.01%) (Note 3)

Unity Gain, Rsw; 20 k~

7.0

5.0
150'

210

B.O
240

mA
mW

The following specifications apply for O°C 5: TA ~ +70°C (8017CI, -SSoC S TA ~ +12SoC (8017MI:

Input Offset Voltage
Average Temperature
Coefficient of Input
Offset Vo Itage

7.5

6.0

I nput Current

500
-55°C::; T A::; +125°e
oOe::; T A::; + 700 e

10

RL

Supply Current

V OUT

;

2 kn

15

15

±10

±10
300

;

OV

9.0

mV
nA
p.V/"C
p.V/"C

10

Large Signal Voltage Gain
Output Voltage Swing
Supply Voltage Rejection Ratio

500

VlmV
V
300
9.0

p.VIV
mA

NOTE 1: The ma.imum junction temperature of the 8017M is 150° C, while that of the 8017C is 100' C. For operating at elevated tempera·
tures the package must be derated based on Ii thermal resistance of 150'C/W, junction to ambient, or 4SoC/W, junction to case.
Above 100'C it may be necessary to use a heatsink with the 8017M to avoid ..ceeding the maximum chip temperature,
NOTE 2: For supply voltages less than ± 15V, the absolute maximum'input voltage is equal, to the supply vol.tage.

NQTE 3: Circuit and compensation as in Figure 1.

5·152

.D~DlL

ICL 8017
TYPICAL PERFORMANCE CURVES*
INPUT lllAS CURRENT AS A
FUNCTION OF TEMPERATURE
120

!...

~

a;
a;

...
...iii

40

z

20

,..,

~

E

...z

80
60

"1'0..

v

50

w
a;

...... t-.....

V>

~

l00k~_

6.0

100

=>
<.)

OPTIMUM VALUE OFRBW
AS A FUNCTION OF CLOSED
LOOP GAIN (SEE FIG. 11

SUPPLY CURRENT AS A
FUNCTION OF TEMPERATURE

./

a:
=>
u

.

~

~

V

S
~
a;

10k

:;

lk

=>

ii:0"

4.0

i;l

~~II~III~III

100 _ _

3.0
-75 -SO -25

0

25

50

75 100 125

~

Raw
60

w

40

.g

20

..J

0

>

" ,"-

0

~

g

=! 20 kn

I

u
lk

10k

;;
E

40

~

30

t;

20

o

10M

1M

TAo"

~

24

Z

...
V>

...~

:::>

0

...0::''"i

...
'"

~

10

kn

T. = 25'C
R." • 20 kil

7.5
5.0

~

.....5...

-2.5
-S.O

l

INPUT

2.5

=>

J
J

,
I

\
\
\
INPUT

-7.5
-10

lOOk

32
28

20

\

10

100M

.1

z

~

<.::>

w

20

<.::>

16

~

...

.g
..~
0

>

12

0

8

I10

.3

.4

.5

.1

0

100

FREQUENCY IMHzl

110
100
90
80
70
60
50
40
30

I
~

BW

'/ a

10
20
30
40

1'- .1

50
60

RBw=20k~

20
10

a
-10
10k

70
80
90

UH-"

I II

IIII
lOOk

1M

.3

.4

.5

FREQUENCY CHARACTER·
ISTICS AS A FUNCTION OF
TEMPERATURE
-20
-10

~11I=d_\111

:-".

.2
TIME I~sl

OPEN-LOOP FREQUENCY
RESPONSE

~

25°C

Rew '"' 20 kn
AL - 5 kn

0

.2
TIME (ps)

OUTPUT VOLTAGE SWING
AS A FUNCTION OF
FREQUENCY

~

=

\
\

FREOUENCY IHzl

<.::>

UNITY GAIN LARGE
SIGNAL PULSE RESPONSE

OUTPUT

50

~

Raw'" '1 H2
Raw

CLOSED LOOP GAIN

OUTPUT

Raw'"

......

Rew

1000

100

10

75 100 125

T A ~ 25 D C

60

au

I
on
.I

<.::>
<.::>

I
=

50

UNITY GAIN TRANSIENT
RESPONSE
70

80

~

z

25

TEMPERATURE lOCI

FREQUENCY RESPONSE
FOR VARIOUS CLOSED
LOOP GAINS

iii

a

-75 -50 -25

TEMPERATURE lOCI

10M

100M

FREQUENCY IHzl

1.6
14

"'0

I

~
V>

:t;
~

-<

c:

~

~

w

...'3
>
w
>

...

:3w
a;

0.6

I-+-+-+--t---t-t--+-;

0.4 L-..L.-'---J_-'--'---'-_L-...J
-75 -50 -25 0 25 50 75 100 125
TEMPERATURE Iocr

*S017C only guaranteed for O°C ~ TA::; +70°C

DEFINITION OF TERMS
Input Offset Voltage:

Voltage which must be applied to
input terminal to obtain zero output voltage.

Input Current: Current into input terminal when at ground
potential.

Large Signal Voltage Gain: The ratio of maximum output
swing with load to the required change in input drive
voltage.
Slew Rate: The maximum rate of change of output voltage
in response to a large amplitude input pulse.

5-153

Unity Gain Bandwidth: The frequency at which the small
signal gain is 3 dB below its low frequency value.
Transient Response: The 10% to 90% closed loop stepfunction response of the amplifier under small signal
conditions.
Settling Time:

The elapsed time between the application
of a fast input pulse and the time at which th\l output has
settled to its final value within a specified limit of accuracy.

ICL 8017
APPLICATIONS INFORMATION
Figure 1. 'I nverting Voltage Amplifier

v'
R,

IIlF~
R,.

v,"
V OUf

C,
100pF

GAIN

R$

R,

IX
lOX
l00X

10kn
lDkn
1kn

10kn
l00kn
100kn

Row

20kn

2 kn
shon

BAND·

SLEW

WIDTH

RATE

10MHz
6MHz
800 kHz

130 VIps
100 V/1J5

50 VIIJ~

0047 ;.oF

,.F
NOTE:

J

ff no bandwidth control resistor (Raw) is connected between pins 3 and 4, the amplifier is unconditionally stable for
normal feedback configurations. ,Some improvement in frequency performance can be realized by setting Raw = 20 kSl;
the amplifier will still be unconditionally stable. However, for optimum frequency response, Raw should be selected from
the curve on page 3,' based on the closed loop gain of the circuit. Additional control of the bandwidth/stability trade-off is
possible by bypassing Rt with a low value capacitor. It is not necessary to alter the value of
C2 or C3'

e,.

Figure 2. Current Summing Amplifier

v'

01'1{. SETTLING TIME' 1 ~WC
01% SETTLING TIME· J j.lWC

v-

NOTE: The analog output current of thd 8018 Series D/A current ,switches can be converted to voltage using the 8017 as shQwn. Input
compenAtion of approximately 10 kn and 30 pF helps improve settling time.

F igur. 4. Isolation of Capacitive 'Loads

Figure 3. Settling Time Measurement

10K
10K

>-",-0'0

5K
LOW CAPACIT ANCE
SCOPE PROBE

F0717

NOTE: Excess phase shift caused by heavy capacitive
loading (above 200 to 300 pF) can cause stability
problems. Bv providing the amplifier with a mini·
mum real load impedance (510), these diffi·
cu Ities can be overcome. Note that at high out·
put currents, maximum voltage swing will be
reduced.

NOTE: Settling time is measured by creating a dummy
summing junction and observing the error voltage
waveform on a scope. The function is clamped
with' high speed diodes to avoid overdriving the
scope preamp.

5·154

ICL8021-ICL8023
Low Power
Operational Amplifiers

FEATURES
•
•
•
•
•
•
•

avos = 3 mV max (adjustable to zero).
:±:1V to ±18V Power Supply Operation.
Power Consumption - 20 jJ.W @ ± 1V.
Input Bias Current - 30 nA max.
Internal Compensation.
Pin-For-Pin Compatible With 741.
Short Circuit Protected.

GENERAL DESCRIPTION
The Intersil8021 integrated circuH is a low power operational
amplifier specifically designed for applications requiring very
low standby power consumption over a wide range of supply
voltages. The electrical characteristics of the 8021 can be tailored to a particular application by adjusting an external resistor, RSfT ' which controls the quiescent current. This is advantageous because 10 can be made independent of the supply
voltages: it can be setto an extremely low value where power
is critical, or to a larger value for high slew rate or wideband
applications.

ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . .
Differential Input Voltage (Note 1) . . .
Common Mode I nput Voltage (Note 1)
Output Short Circuit Duration
Power Dissipation (Note 21 ..
Operating Temperature Range

±18V
±15V
±15V
. Indefinite

Other features of the 8021 include low input current that remains constant with temperature, low noise, high input impedance, internal compensation and pin-far-pin compatibility with the 741 .

. .300 mW

-55° C to + 125° C
. . .O°C to +700 C
-65° C to + 1 50° C
Storage Temperature Range . .
Lead Temperature (Soldering, 10 sec) . . . . . . +3000 C
8021 M . . . . . . . . .
8021C . . . . . . . . . .

The Intersil8022 (8023) consists of two (three) low power operational amplifiers in a single 14-pin DIP. Each amplifier is
identical to an 8021 low powerop amp, and has separate connections for adjusting its electrical characteristics by means
of an external resistor, RSfT , which controls the quiescent current of that amplifier.

NOTE 1: For supply voltages less than ±15V, the absolute maximum
input voltage is equal to the supply voltage.
NOTE 2: Rating applies for case temperatures to +125'C; derate
linearly at 5.6 mW/oC for ambient temperatures above
+ 95'C.

SCHEMATIC DIAGRAM

PIN CONFIGURATIONS

BALD'las
-BAL
2

7

v+

+IN

3

8

OUT

V-'

v(outline dwg TY)

(outline dwg PAl

NOTE: Pin 4 connected to case.

VOLTAGE OFFSET NULL CIRCUIT
(outline dwg JD, PD)

'l

ORDERING INFORMATION
C

Basic
Part Number

8021--5ingle
8022~u.1

TY

LP~c~~eT0-99
PA- 8
Minidip

Metal Can

8021 only

~g::= ~: ~:~ ~~:~PDIP

8022 only

~~ ;~ ~:~~I:~tDIP

8023 only

pin

(outline dwg JE, PEl

8023-Triple
Temperature
C':""" Commercial - COC to 70"C
M- Military -55'C 10 + 125'C

5-155

ET

~IN

ICL8021-ICL8023
ELECTRICAL CHARACTERISTICS (V s = ±6V, IQ '= 30 IlA, unless otherwise specified.)
8021M

CONDITIONS

CHARACTERISTICS

MIN

8021C

TYP

MAX

MIN

TYP

MAX

UNITS

The following specifications apply for T A = 2SoC:

Input Offset Voltage

2

Rs <::: 100 kn

Input Bias Current

Input Voltage Range

= ±15V

Vs

Common Mode Rejection Ratio· Rs <::: 10kn
Supply Voltage Rejection Ratio

Rs <:::10kr2

Output Resistance

Open Loop

Output Voltage Swing

RL ~ 20 kn, Vs
RL ~ 10 kr2, Vs

20

V OUT

3

10

±12

±13

V

70

80

70

80

dB

150

±12
±11

=0

±12
±11

Input Offset Voltage

<

0.16

+70'C (8021C) -55'C

<

Input Bias Current

4.0

R s <:::10kr2

Average Temperature
Coefficient of Input
Offset Current

= 10 kr2

RL ~ 10 kr2

"'.A

100~A

470k12

150 kH

15

,

3

3.3 MH

Ll Mn

330kH

100 k!1

,

6

75MH

27MH

7501<\1

220kH

,

9

13Mn

4MH

1 3 M~~

35Qk\l

~

12

18Mn

5.6MH

1.5MH

510 kH

~

15

22Mn

7.SMn

22 MH

6201<.12

1.7

0.8

pAtC

50

200

50

200

V/mV

±10

±13

±10

±13

V

QUIESCENT CURRENT
SETTING RESISTOR
(PIN 8 TO v-I

'0

10~A

~I'o "30"A
' 0 ' l00 .. A

1 M!~

la. :300"A
100

k~,

0

;

4

6

8

10 12 14

SUPPLY VOLTAGE (-V)

5-156

nA
/1vtc

10 MU

15

nA

50

5

3OO\pA

~

mV

15

5

QU.IESCENT CURRENT
SETTING RESISTOR
(PIN 8 TO V-I
1O~A

7.5

1.5

32

QUIESCENT CURRENT ADJUSTMENT

1.SMH

IlS
%

2.0

11

10

RL

kHz

+125'C (S021M)

1.0

Large Signal Voltage Gain

V/Ils

1.3
10

2.0

Rs <::: 10 kr2

Output Voltage Swing

Il W

= 20 mV

I nput Offset Current

Average Temperature
Coefficient of Input
Offset Voltage

mA
600

270

1.3
10

The following specifications apply for :O'C ~ TA

V
V

360

210

IlVIV

kS2

±14
±13
±13

480

0.16

RL = 20 kr2, V IN

150

2

±14
±13

360

Mn

30

2

RL = 20 kr2, V IN = 20 mV

Transient Response (Unity
Gain)
Risetime
Overshoot

nA

10

Slew Rate (Unity Gain)
Unity Gain Bandwidth

nA

30

±13

±13

Power Consumption

Vs
~

7

mV

10

3

30

= ±15V
= ±15V

6
.7

±12

Output Short-Circuit Current

,

2

7.5

5

Input Resistance

II

3
.5

I nput Offset Current

16 18

ICL8021-ICL8023
TYPICAL PERFORMANCE CURVES* (T A ~ +25°C, Vs ~ ±6V, IQ ~ 30 pA, unless otherwise specified.)
DIFFERENTIAL INPUT
IMPEDANCE VS
QUIESCENT CURRENT

INPUT BIAS CURRENT VS
AMBIENT TEMPERATURE

INPUT BIAS CURRENT
VS QUIESCENT CURRENT

!'00 mmrm_

~l00m_

100

i,0~1111

~

t-

lo ~ 100 j.lA

f-

~

~ log~ltll

1010310,1

~

f-

~

z

~ ~

tt-...

10'" lOj.lA

~

~

III

1

-60

140

100

60

-20 0 20

50

30

Ci

TEMPERATURE I'CI

QUIESCENT CURRENT (j.lA)

FREQUENCY RESPONSE
VS QUIESCENT CURRENT

SLEW RATE VS
QUIESCENT CURRENT

100

300

QUIESCENT CURRENT I",AI

PHASE MARGIN VS
QUIESCENT CURRENT
Rl

I
~
I

./

~

"

400

~

300

~

200

~

~

20 kH

500

<.?

90

z

L--~

~ 75
<
, 60

/'

~

V

./
45

30

~ 100

o
30

100

10

300

OPEN· LOOP FREQUENCY
RESPONSE

~
z

CO

_ R , - 50

50

~

kf~

<
>

R, -5k"_~

~

10

l"'V,

12

£

~

10

::5

R,

30

16

;

20Id·~',==

1111111

60
50
40

"w>

30

6z

20

E::
t--::

~

~

,

t---

1

50

100

FREQUENCY (Hz)

:S. T A::;'

100 ",A

..... 10

10 = 30"A:::r

1111111
1111111

10
10

SUPPLY VOLTAGE IVI

.. Ie L8021 C guaranteed only for 0° C

1001(')"A~

10 '

..!o

30"A
= 10j.lA

lo=lO#'A-i

!
'3

EQUIVALENT INPUT NOISE
CURRENT VS FREdUENCY
1

I

H4

~

/

300

QUIESCENT CURRENT (.. AI

EQUIVALENT INPUT NOISE
VOLTAGE VS FREQUENCY

lL

~

I I

TIME ("sec)

OUTPUT VOLTAGE SWING
VS SUPPLY VOLTAGE
30

~

0:
TIME

lOOk

10

1

V," '6V

~

~=RISE

f

'15V

~

z

40

FREOUENCY IHzl

Z

MAXIMUM LOAD VS
QUIESCENT CURRENT

~

"

<.?

300

100

QUIESCENT CURRENT (j,JA)

TRANSIENT RESPONSE

z

]

30

10

80

~
~

300

100

<.?

<

100

120

~
~

30

QUIESCENT CURRENT (;.tAl

OUIESCENT CURRENT IliA)

+ 70° C

5·157

111111

1

500

lk

10

50

100

FREQUENCY 1Hz)

500

11<.

ICL8038
Precision Waveform
Generator/Voltage
Controlled Oscillator
FEATURES

GENERAL DESCRIPTION

• Low frequency drift with temperature - 50ppm/o C
• Simultaneous sine, square, and triangle wave
outputs
• Low distortion - 1% (sine wave output)
• High linearity - 0.1% (triangle wave output)
• Wide operating frequency range - 0.001 Hz to
0.3MHz
• Variable duty cycle - 2% to 98%
• High level outputs - TTL to 28V
• Easy to use - just a handful of external components
required

The ICL8038 Waveform Generator is a monolithic integrated
circuit capable of prbducing high accuracy sine, square,
triangular, sawtooth and pulse waveforms with a minimum of
external components. The frequency(or repetition rate) can
be selected externally from .001 Hz to more than 300kHz
using either resistors or capacitors, and frequency
modulation and sweeping can be accomplished with an
external voltage. The ICL8038 is fabricated with advanced
monolithic technology, using Schottky-barrier diodes and
thin film resistors, and the output is stable over a wide range
of temperatl,lre and supply variations. These devices may be
interfaced with phase locked loop circuitry to reduce
temperature drift to less than 50ppm/o C.

PIN CONFIGURATION (outline dwg JD)

BLOCK DIAGRAM

CURREN:~
SOUR~~
'V'v
jI

6

COMPARATOR~
#1

10

)21

COMPARATOR
#2

'.

C:F

f

'~':o/
I Y
r--

SOURCE
#2

v+

BUFFER

FLIP-FLOP

SINE WAVE
OUT

[I

TRIANGLE
OUT

[I

DUTY
CYCLE
FREQUENCY
ADJUST

r---V-or GND
11

{~

I[I
5

v+

II

FM
BIAS

[I7

~ NC

ii!I SINE WAVE
ICL8038

A~JUST

!!J V-OR GND
~ TIMING

10 CAPACITOR

:!l SQUARE WAVE
OUT
:!l FM SWEEP
INPUT

SINE
CONVERTER

BUFFER

~JUl..

II ~ ~ NC

SINE WAVE
ADJUST

~

3

'V'v

2'\J\J

ORDERING INFORMATION
TYPE
8038 CC
8038BC
8038 AC
8038 BM
8038 AM

TEMPERATURE RANGE
O°C to +70°C
O°C to +70°C
O°C to +70°C
-55°C to +125°C
-55°C to +125°C

STABILITY
250ppm/oC typ
150ppm/oC max
80ppm/oC max
150ppm/oC max
80ppm/·C max

5-158

PACKAGE
CERDIP
CERDIP
CERDIP
CERDIP
CERDIP

ORDER PART NUMBER
ICL8038 CC JD
ICL8038 BC JD
ICL8038 AC JD
ICL8038 BM JD
ICL8038 AM JD

ICLS038
MAXIMUM RATINGS
Supply Voltage .............................................. ±18V or 36V Total
Power Dissipation ''' ..................................................... 750mW
Input Voltage (any pin) ......................... Not To Exceed Supply Voltages
Input Current (Pins 4 and 5) .............................................. 25m A
Output Sink Current (Pins 3 and 9) ........................................ 25m A
Storage Temperature Range ................................... -B5°C to +125°C
Operating Temperature Range:
8038AM, 8038BM ........................................... -55° C to +125° C
8038AC, 8038BC, 8038CC ...................................... O°C to +70°C
Lead Temperature (Soldering, 10 sec,) ................................... 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections ofthespecifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

NOTE 1: Derate ceramic package at 12.5mW/oC for ambient temperatures above 100°C.

ELECTRICAL CHARACTERISTICS
(Vsupp

= ±10V or +20V,

TA

= 25°C,

RL

= 10kO, Test Circuit

SYMBOL
GENERAL CHARACTERISTICS
MIN
Vsupp Supply Voltage Operating Range
V+
SinQle Supply
+10
V+, V
±5
Dual Supplies
Isupp
Supply Current IVsupp +10V)121
8038AM, 8038BM
8038AC, 8038BC, 8038CC
FREQUENCY CHARACTERISTICS lall waveforms)
fmax
Maximum Frequency of Oscillation 100,000
Sweep Frequency of FM
fsweep
Swee FM Range '31
FM Linearity 10:1 Ratio
df/dT
Frequency Drift With Temperature l51
+ 25°C to + 70°C (+ 125°C)
O°C ( - 40°C) to + 25°C
M/dV
Frequency Drift With Supply Voltage
lOver Supply Voltage Range)
Recommended Programming
Resistors IRA and RB)
1000
OUTPUT CHARACTERISTICS
Square-Wave
Leakage Current IV9 = 30V)
10lK
Saturation Voltage IISINK 2mA)
VSAT
Rise Time IRl - 4.7kOl
tr
Fall Time IRl - 4.7kOl
tf
Duty Cycle Adjust
2
Triangle/Sawtooth/Ramp
Amplitude IRTRI = 100kOl
0.30
Linearity
Output Impedance IIOUT - 5mA)
ZOUT
Sine-Wave
Amplitude IRslNE = 100kO)
0.2
THO IRs - 1MOll41
THO Adjusted IUse Fig. 8bl

NOTE
NOTE
NOTE
NOTE

2:
3:
4:
5:

8038CC
TYP

12

Unless Otherwise Specified)

MAX

MIN

8038BC(BM)
TYP
MAX

MIN

8038AC(AM)
TYP
MAX

+30
±15

+10
±5

30
±15

+10
±5

30
±15

V
V

15
20

mA
mA

12
12

20

15
20

100,000
10
35:1
0.5

1000

1
0.5

98
0.33
0.1
200

5

2

1
0.4

98

0.30

0.33
0.05
200

0.2

0.22
1.5
1.0

3

RA and Rs currents not included.
Vsupp = 20V; RA and RB = 10kO, f '" 9kHz; Can be extended to 1000.1. See Figures 13 and 14.
82kO connected between pins 11 and 12, Triangle Duty Cycle set at 50%. IUse RA and RBJ
Fig. 2, pins 7 and 8 connected, Vsupp = ±10V. See Fig. 6c for T.C. vs Vsupp.

5-159

1000

0.2
180
40
2

1M

0

1
0.4

Jl.A
V
ns
ns
%

98

0.30

0.33
0.05
200

0.2

0.22
1.0
0.8

ppm/oC
%/Vsupp

0.05
1M

0.2
180
40

%

80
120

0.05
1M

0.22
2.0
1.5

10
35:1
0.2
150
200

0.05

Hz
kHz

100,000
10
35:1
0.2

250
250

0.2
180
40

12
12

UNITS

xVsupp
%
0

1.5

xVsupp
%
%

ICLS038
TEST CONDITIONS
PARAMETER
Supply Current
Maximum Frequency of Oscillation
Sweep FM Range 111
Frequency Drift with Temperature
Frequency Drift with Supply Voltagel~
Output Amplitude: Sine
Triangle
Leakage Current (Offl 131
Saturation Voltage (on)(31
Rise and Fall Times
Duty Cycle Adjust: MAX
MIN
Triangle Waveform Linearity
Total Harmonic Distortion

RA

RB

RL

C1

SW1

MEASURE

10kfl
lkfl
10k!l
10k!l
10k!l
10k!l
10k!l
10k!l
10kl1
10kfl
50k!l
-25k!l
10k!l
10k!l

10kll
lk!l
10k!l
10k!l
10k!l
10k!l
10k!l
10k!l
10k!l
10k!l
-1.6kn
50k!l
10kn
10kfl

10kll
4.7kll
10kll
10k!l
10kfl
10k!l
10k!l

3.3nF
100pf
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF
3.3nF

Closed
Closed
Open
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed
Closed

Current into Pin 6
Frequency at Pin 9
Frequency at Pin 9
Frequency at Pin 9
Frequency. at Pin 9
Pk-Pk output at Pin 2
Pk-Pk output at Pin 3
CJrrent into Pin 9
Output (low) at Pin 9
Waveform at Pin 9
Waveform at Pin 9
Waveform at Pin 9
Waveform at Pin 3
Waveform at Pin 2

10k!l
4.7k!l
10k!l
10k!l
10kfl
10kn

NOTE 1: The hi and 10 frequencies can be obtained by connecting pin 8 to pin 7 (fhil and then connecting pin 8 to pin 6 (flo I. Otherwise apply
Sweep Voltage at pin 8 (2/3 Vsupp +2V10"; VSWEEP 0"; Vsupp where Vsupp is the total supply voltage. In Fig. 2, pin 8 should vary
between 5.3V and 10V with respect to ground.
NOTE 2: 10V 0"; V+ 0"; 30V, or ±5V 0"; Vsupp 0"; ±15V.
NOTE 3: Oscillation can be halted by forcing pin 10 to +5 volts or -5 volts.

DEFINITION OF TERMS:

TEST CIRCUIT

Supply Voltage (Vsupp). The total supply voltage from V+ to VSupply Current. The supply current required from the power supply
to operate the device, excluding load currents and the currents
th rough HAsnd RB.
.
Frequency Range. The frequency range at the square wave output
through which circuit operation is guaranteed.

RA
10k

Sweep FM Range. The ratio of maximum frequency to minimum
frequency which can be obtained by applying a sweep voltage to pin
R For correct operation, the sweep voltage should be within the

SW,

.

~~

Rs
10k

N.C.

(2/3 Vsupp + 2V) < VSWEEP < Vsupp

ICL8038

FM Linearity: The percentag"l d"lviation from the best-fit straight line
on the control voltage versus output frequency curve.
Output Amplitude. The. peak-to-peak signal amplitude appearing at
the outputs.

11

10

Saturation Voltage. The output voltage at the collector of Q23 when
this tran$istor is turned on. It is measured for a sink current of 2mA.

C,
3300pF

Rise and Fall Times. The time required for the square wave output to
change from 10% to 90%, or 90% to 10%. of its final value.
Triangle Waveform Linearity. The percentage deviation from the
best-fit straight line on the rising and falling triangle wavefo~m.
Total Harmonic Distortion. The total harmonic distortion at the sinewave output.

TYPICAL PERFORMANCE CHARACTERI~TICS
20

v

l;

I

~ 15
a:
~

10

5

~
5

10

15

N

20

25

SUPPLY VOLTAGE

30

~0.99

~1.02

I

w

u.
0 1.00
w

T1T

/,7. V

f;11.02
g1.01

r>-

o

~

1 V ~V

1.03
>-

w

-

I

-

a:
u.

......

I!l

-~,

30V
0 1.00 - [--:lOV
l'OV
~O.99

:;

:;

00.98

00.98

'

~~
1"1;v

a:

a:

z

1°V

"ljll.O1

z

>=
10

15

20

25

SUPPLY VOLTAGE

5-160

30

~

-50 -25 0 25

75

TEMPERATURE'C

125

.ICLS038
THEORY OF OPERATION (see block diagram,
first page)
An external capacitor C is charged and discharged by two
current sources. Current source #2 is switched on and off by
a flip-flop, while current source #1 is on continuously.
Assuming that the flip-flop is in a state such that current
source #2 is off, and the capacitor is charged with a current I,
the voltage acrpss the capacitor rises linearily with time.
When this voltage reaches the level of comparator #1 (set at
2/3 of the supply voltage), the flip-flop is triggered, changes
states, and releases current source #2. This current source
normally carries a current 21, thus the capacitor is
discharged with a net-current I and the voltage across it
drops linearly with time. When it has reached the level of
comparator #2 (set at 1/3 of the supply voltage), the flip-flop
is triggered into its original state and the cycle starts again.

Four waveforms are readily obtainable from this basic
generator circuit. With the current sources set at I and 21
respectively, the charge and discharge times are equal. Thus
a triangle waveform is created across the capacitor and the
flip-flop produces a square-wave. Both waveforms are fed to
buffer stages and are available at pins 3 and 9.
The levels of the current sources can, however, be selected
over a wide range with two external resistors. Therefore, with
the two currents set at values different from I and 21, an
asymmetrical sawtooth appears at terminal 3 and pulses with
a duty cycle from less than 1% to greater than 99% are
available at terminal 9.
The sine-wave is created by feeding the triangle-wave into a
non-linear network (sine-converter). This network provides a
decreasing shunt-impedance as the potential of the triangle
moves toward the two extremes.

Performance of the Square-Wave Output
200

11..4

RISE TIME
I

150

l - I-

~

100

I .. ~

I

12f\C~~

....
o
>
z

I
I

o

o

25iC 1/~

~

125'C

~~

1"1

--~

o
o

ro

/

v: vv
~ p.. vt,c
~
25'C

~

125'C

o

I

1

a:
~ 0.5

FALL TIME

50

1-1-

i

CI
~ 1.5

25:'C~ jIi'" -55'C

k: ~

r----

w

AK

LOAD RESISTANCE-kll

10

4
LOAD CURRENT -mA

Performance of Triangle-Wave Output
10

w 1.2

~
.....

g

1.1

0-

o 2

4 6 8 10 12 14 16 18 20
LOAD CURRENT-mA

~

)

0.1

--_.-

0.7
0.6
10Hz 100Hz 1kHz 10kHz100kHz1MHz
FREQUENCY

0.01
10Hz 100Hz 1kHz 10kHz 100kHz 1MHz
FREQUENCY

Performance of Sine-Wave Output

w 1.1

12

~

...5 1.0
0-

=>

o
o

~

O. 9

~
~

::

:::;
a:

II

10

o

>

It

--l- t-- -I-

~ 0.8

a:

e-I-

I

o

;t::Ii

I

---

l-

I - -I--

~ 1.0

5 0.9

.~-

II

I-

~

1\

lA

o
~

g

6

!!!

4

o

VI

~TEDI

AFJ~~

o

10Hz 100Hz 1kHz 10kHz 100kHz 1MHz
FREQUENCY

rl

ED~ l- I-

10Hz 100Hz 1kHz 10kHz 100kHz 1MHz
FREQUENCY

5-161

ICLS038

~

r'\

/

"- /

"-

V

1"-./

"-/

"

'"

'/

/ ~

/" ~

v '\

1"-

r\

....V

'/

V

1\

~/

'V V"

"

r\

~

V

,

'V "

....

Square-Wave Duty Cycle - 50"10

/

""...r\

......

....

...

Square-Wave Duty Cycle - 80"10
Phase Relationship of Waveforms

WAVEFORM TIMING

With two separate timing resistors, the frequency is given by

The symmetry of all waveforms can be adjusted with the
external timing resistors. Two possible ways to accomplish
this are shown in Figure 1. Best results are obtained by
keeping the timing resistors RA and Rs. separate (al. RA
controls the rising portion of the triangle and sine-wave and
the 1 state of the square-wave.
The magnitude of the triangle-waveform is set at 1/3 Vsupp;
therefore the rising portion of the triangle is,

f=_1_ =
t1+12

f=

CX1/3V+

5

Rs

5

E.
3

RA

(e)

(b)

RB

RL

lkll

RL

RL

RB

RA

J111.

"Iv
'\IV

ICL8038 '

C

12

v+

v+

v+

11

(for Figure 1a)

Neither time nor frequency are dependent on supply voltage,
even though none 01 the voltages are regulated inside the
integrated circuit. This is due to the fact that both currents
and thresholds are direct, linear functions of the supply
voltage and thus their effects cancel.
To minimize sine-wave distortion the 82kO reSistor between
pins 11 and 12is best made variable. With this arrangement
distortion of less than 1% is achievable. To reduce this even
further, two potentiometers can be connected as shown in
Figure 2; this configuration allows a typical reducti.on of
sine-wave distortion close to 0.5%.

X RARsC
2 RA - Rs

(8)

10

~.~

1 = 0.15
RC

Thus a 50% duty cycle is achieved when RA = Rs.
If the duty.cycle is to be varied over a small range about 50%
only, the connection shown in Figure 1b is slightly more
convenient. If no adjustment of the duty cycle is desired,
terminals 4and 5 can be shorted together, as shown in Figure
1c. This connection, however, causes an inherently larger
variation of the duty-cycle, frequency, etc.

RA

2RA-Rs

If a Single timing resistor is used (Figure 1c only), the
frequency is

The falling portion of the triangle and sine-wave and the 0
state of the square-wave is:

~ x Vsupp _ J.. x VsuPP

3

or, if RA = Rs = R

t - CxV _ CX1/3XV+xRA _ 5
1I
115 X V+
- "3 RA X C

cxV
t2 = -1- =

1

~RAC(1+~)

82k

9

ICL8038
10

11

J111.

9

'\Iv

"IV
12 2

'\IV

10

11

C

C
V-orGND

V-'orGND

Figure 1: Possible Connections for the External Timing Resistors.

5·162

nn

12 2

'\IV

82k
V-orGND

ICLS038
V

.l
1kll
RA

RB

RL
~

7

4

5

6

ICL8038

8

10

::c

11

12

1

I

9

---+-o.n.n..

3

r-------o '\I"v

2

r-------o '\IV

....
:. 10

100kll
10 Okll
10k

V-orGND

FREQUENCY MODULATION AND SWEEPING
The frequency of the waveform generator is a direct function
of the DC voltage at terminal 8 (measured from V+). By
altering this voltage, frequency modulation is performed.
For small deviations (e.g. ±10%) the modulating signal can be
applied directly to pin 8, merely providing DC decoupling
with a capacitor as shown in Figure 3a. An external resistor
between pins 7 and 8 is not necessary, but it can be used to
increase input impedance from about 8kO (pins 7 and 8
connected together), to about (R + 8kO)'
For larger FM deviations or for frequency sweeping, the
modulating signal is applied between the positive supply
voltage and pin 8 (Figure 3b). In this way the entire bias for
the current sources is created by the modulating signal, and
a very large (e.g. 1000:1) sweep range is created (f = 0 at
Vsweep = 0), Care must be taken, however, to regulate the
supply voltage; in this configuration the charge current is no
longer a function of the supply voltage (yet the trigger
thresholds still are) and thus the frequency becomes
dependent on the supply voltage. The potential on Pin 8 may
be swept down from V+ by (1/3 Vsupp - 2V).

Figure 2: Connection to Achieve Minimum Sine-Wave Distortion.

SELECTING RA, Rs AND C
For any given output frequency, there is a wide range of RC
combinations that will work, however certain constraintsare
placed upon the magnitude of the charging current for
optimum performance. At the low end, currents of less than
1/lA are undesirable because circuit leakages will contribute
significant errors at high temperatures. At higher currents (I
> 5mA), transistor betas and saturation voltages will
contribute increasingly larger errors. Optimum performance
will, therefore, be obtained with charging currents of 1O/lA to
1mAo If pins 7 and 8 are shorted together, the magnitude of
the charging current due to RA can be calculated from:

A similar calculation holds for RB.
The capacitor value should be chosen at the upper end of its
possible range.

v+
SWJEEP

RA

VOL TAGE

WAVEFORM OUT LEVEL CONTROL AND
POWER SUPPLIES

4

The waveform generator can be operated either from a single
power-supply (10 to 30 Volts) or a dual power-supply (±5 to
±15 Volts). With a single power-supply the average levels of
the triangle and sine-wave are at exactly one-half of the
supply voltage, while the square-wave alternates between V+
and ground. A split power supply has the advantage that all
waveforms move symmetrically about ground.
The square-wave output is not committed. A load resistor
can be connected to a different power-supply, as long as the
applied voltage remains within the breakdown capability of
the waveform generator (30V)' In this way, the square-wave
output can be made TTL compatible (load resistor
connected to +5Volts) while the waveform generator itself is
powered from a much highe~ voltage.

RB

5

RL

6

ICL8038

>-8

10

::c

11

9

f-+---o

31-----<>

12

21-----<>

81k
V-orGND

Figure 3: Connections for Frequency Modulation (a) and Sweep (b)

5-163

.D~DIL

ICLS038

r--------,--------------------~----~+15V

APPLICATIONS
RA

v+

>

<

RA

RB

15k

RB

~

7

4

5

6

2 ~MPLITUDE

;.

ICL8038

;~~

ICL8038

8

t.....

IN914

20k

10.

11

2
IN914

10

t-~~~~STROBE

4.7k

11

C
'-----<

=F

lOOk

C

-15V

.".

Figure 4: Sine Wave Output Buffer Amplifiers.
The sine wave output has a relatively high output impedance
(1 kO Typ). The circuit of Figure 4 provides buffering, gain and
amplitude adjustment. A simple op amp follower could also be
used.

.

Figure 5: Strobe-Tone Burst Generator.
With a dual supply voltage the external capacitor on Pin 10 can be
shorted to ground to halt the 8038 oscillation. Figure 5 shows a
FET switch, diode AN Oed with an input strobe signal to allow the
output to always start on the same slope.
+1 ov

~'IN457
-"

OFF
V +15V (+10V)
ON -15V ~-10V)

DUTY
CYCLE
lk"

-r: .1~F

<

• 4.7k

? Uk

l,5k

r----<
5

10k
FREQUENCY

ICL8038

8

10
20k

6

4

~

~15MI.

9~

.nn.

3~

11

12

*.oo47"F

I.

21---<>

'\A

~DISTORTI ON
lOOk

-10 V

Figure 6: Variable Audio Oscillator, 20Hz to 20kHz.
To obtain a 1000:1 Sweep Range on the 8038 the voltage across external resistors RA and Rs must decrease to nearly zero. This requires thatthe
highest voltage on control Pin 8 exceed the vo!tage at the top of RA and Rs by a few hundred millivolts.
The Circuit of Figure 6 achieves this by using a diode to lower the effective supply voltage on the 8038. The large resistor on pin 5 helps reduce
duty cycle variations with sweep.
HIGH
FREQUENCY
SYMMETRY

lN753A
(6.2V)

lOOk!!

10k!!
4.7k!!

lk!!

1M!!

lOOk!!
LOW
FREQUENCY
SYMMETRY
SINE-WAVE
OUTPUT

ICL8038

lk!!

FUNCTION GENERATOR

"-

3

+
11

10

12

50"F
15V
lOOk!!

3,900pF
L-----~----

__

,

SINE-WAVE
DISTORTION

~----~--

___________4----------____

~~-15V

Figure .7: Linear Voltage Controlled Osciilator
The linearity of input sweep voltage versus output frequency can be significantly improved by using an op amp as shown in Figure 7.
5-1~4
.

ICLS038
USE IN PHASE-LOCKED LOOPS
Second, the DC output level of the amplifier must be made compatible to the DC level required at the FM input of the waveform
generator (pin 8, 0.8 x V+l. The simplest solution here is to provide a voltage divider to V+ (R 1, R2 as shown) ifthe ampl ifier has a
lower output level, or to ground if its level is higher. Thedivider
can be made part of the low-pass filter.
This application not only provides for a free-running
frequency with very low temperature drift, but it also has the
unique feature of producing a large reconstituted sinewave
signal with a frequency identical to that at the input.
For further information, see Intersil Application Bulletin
A013, "Everything You Always Wanted to Know About The
8038."

Its high frequency stability makes the ICL8038 an ideal
building block for a phase-locked loop. In this application
the remaining functional blocks, the phase-detector and the
amplifier, can be formed by a number of available IC's (e.g.
MC 4344, NE 562, HA 2800, HA 2820>.
In order to match these building blocks to each other, two
steps must be taken. First, two different supply voltages are
used and the square wave output is returned to the supply of
the phase detector. This assures that the VCO input voltage
will not exceed the capabilities of the phase detector. If a
smaller VCO signal is required, a simple resistive voltage
divider is connected between pin '9 of the waveform
generator and the VCO input of the phase-detector.

v++

~

Rl

4
FMBIAS
0--7

v+

~

SQUARE
WAVE
OUT 9

~
INPUT

DUTY
CYCLE
/. FREQUENCY/,
ADJUST

~~

VCO
IN
0--

PHASE DETECTOR

~

AMPLIFIER

DEMODULATED
FM

1

FM
SWEEP
INPUT

R2

~
LOW-PASS
FILTER

~

5

.

6
3

f---- 2k!1, Vau! = ±10V 50,000
Output Resistance
Ro
75
Output Short-Circuit Current
Isc
25
Isupp"
Supply Current ITotall
4.5
Pd
Power Consumption
135
SR
Slew Rate
6.0
GBW
Unity Gain Bandwidth
1.0
Transient Response IUnity Gain) CL < 100pF, RL = 2k!1
tr
Risetime
300
Overshoot
10

I

I
MAX.

I

MIN.

20

I

8043C
TYP.
20
0.5
3.0
106
2.0

20

I

I

MAX.
50
50

20,000
75
25
4.5
135
6.0
1.0

6
180

6.8
204

I

UNITS
mV
pA
pA
M!1
pF
V/v
!1
mA
mA
mW
V/p.s
MHz

300
10

ns

±12
90
70

V
dB
p.V/v
V/v
V
V
mV
nA
pA
p.V/oC

%

The following specifications apply for O°C < TA < +70'C 18043C), --55°C < TA < +125'C 18043M):

Av
±Vo

Input Voltage Range
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Large Signal Voltage Gain
Output Voltage Swing

Vos
liN

Input Offset Voltage
Input Current leither input)

tlVosliH

Average Temperature Coefficient
of Input Offset Voltage

tlVIN
CMRR
PSRR

±10
70
25,000
±12
±10

RL > 10k!1
RL > 2k!1
TA
TA

= +125°C
= +70°C

±12
90
70
±14
±13
15
2.0

±10
70
300
15,000
±12
±10
30
15
75

5·168

600

±14
±13
30

60

50

175
75

ICLS043
TYPICAL PERFORMANCE CURVES
OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
FREQUENCY
10'
105
Z

~

10'

>
...:>

'"
,.';"
UJ
0-

0-

10k

lOOk

1M

10M

0123456789

FREQUENCY (Hz)

TIME ("s)

INPUT CURRENT AS A
FUNCTION OF TEMPERATURE

OUTPUT SWING AS A FUNCTION
OF SUPPLY VOLTAGE
20

~ 104

20r-~~~~-+--~--4-~
90%

;

16r---+-/~r-~r-~~~---4

~

12~--~~/~--~--~--~~

~ 10 3
~

...<>

RISE-t--- VSUpp = ±15V

iJ:= TIME

TA

~ 25°C

I

.5

CL ~ 100pF

1.0
1.5
TIME (~s)

2.0

2.5

oZ

~

25°C
2kll

20

UJ

"'z"

z

r--- r--- K j G A T E r j - t--

60
80
100 120
TEMPERATURE (0C)

140

±5
±10
±15
SUPPLY VOLTAGE

"'~"
0
...>

10 5

g
zUJ
0o

10

r---

Vs = ±15V

--r--. r--.

§.

UJ
IX
IX

UJ
IX
IX
~

<>

±15

±5

±20

- t--

l - +-

+-t-"

i""""

<>
~

00-

1il

±10

±15

INPUT VOLTAGE NOISE AS
A FUNCTION OF FREQUENCY

:I!

r--. r--.

~

UJ
II>

z
RS

1 Mil

-

102

w

TEMPERATURE eC)

10

100
lk
10k
FREQUENCY (Hz)

5-169

~

BANDWIDTH
- 0.1 Hz TO 1 kHz

1.0

J

~ 0.1
lOOk

100

L

f'

~

~

IIII

o
105

UJ
IX

IX

i5
z
65

~ 10.0
Z

~

Rs - SOil

UJ
II>

25,

r-- ~~~~~'fci~oo kHz V

i5

UJ

§?

~

±20

1000

.::, 100
103

"~

±15

WIDEBAND NOISE AS A FUNCTION
OF SOURCE RESISTANCE

I>

">

II>

-15

±10

SUPPLY VOLTAGE

104

-

±5

±20

SUPPLY VOLTAGE

i

-55

~

~

2
±10

±5

TOTAL QUIESCENT SUPPLY CURRENT
AS A FUNCTION OF TEMPERATURE

...Z

...Z

V

SUPPLY VOLTAGE

:<

V 1.Ce~ATIVE

~125OC

§.

lLV

VV

~

0-

;!;

o

:<

JL V

t--POSITIVE

±20

QUIESCENT SUPPLY CURRENT
AS A FUNCTION OF SUPPLY
VOLTAGE
TA

ILv

15

IX
UJ

104

40

V

.L ~

~

~

[

/. V

0

.L

.,

1

L

/

POllTIVE SWING

.L ~

20
TA
RL

o

10

INPUT VOLTAGE RANGE AS
A FUNCTION OF SUPPLY VOLTAGE

10'

0-

II>

r---

~

/

UJ
N

IX

15

0-

C

OPEN LOOP VOLTAGE GAIN
AS A FUNCTION OF
SUPPLY VOLTAGE

~

/

~ 10

I--f--f---t- RL ~ 2kll

~
z

"li
...
...

IX

;!;

/! I

TA'~25~C
TL ~ 2kr

...Z@J

~ 102

t-- 10C

t-

-8

'" o
lk

<>

o

OU~pJT

UJ
0-

lOOk 1M 10M

TRANSIENT RESPONSE

~

II

\

-4

-

INPUT

Ii

0

FREQUENCY (Hz)

:;-

,

1\

..J

6

[\

TA~25'C

-

"...'"
0

Ii

16

Vsupp = ±15V

~

,

24

~

o

VOLTAGE FOLLOWER LARGESIGNAL PULSE RESPONSE

~~~p~ ~ '±~~~
TA
RL

...

0

>

i"

40

II>

~

..J

~

VSUlpp '=
TA ~ +2fi'C

"'-['\..

UJ

OUTPUT VOLTAGE SWING AS
A FUNCTION OF FREQUENCY

lk

10k

lOOk

1M

10M 100M

SOURCE RESISTANCE (Il)

ICLS043
CHANNEL SEPARATION
Channel separation or crosstalk is measured using the circuit of Figure 1. One amplifier is driven so that its output swings ±1 OV;
the signal amplitude seen in the other amplifier (referred to the input) is then measured. Typical performance is shown in Figure

2.
Channel Separation = 20 log (VOUT(A'\
VIN(S)J

CHANNEL SEPARATION
11 0

Ih~12rC

100

RL

RL
R

~
~J) r\

~

10k

t\
60

~

50
100

Figure 1

lk
10k
lOOk
FREQUENCY (Hz)

1M

Figure 2

Following this nulling operation, A1 is used as a normal
amplifier while the voltage necessary to zero its offset
voltage is stored on the integrator comprised of A2 and C1.

APPLICATIONS
Applications for any dual amplifier fall into two categories.
There are those which use the two-in-one package concept
simply to save circuit-board space and cost, but more
interesting are those circuits where the two sides of the dual
are used to complement one another in a subsystem
application. The circuits which follow have been selected on
this basis.

The advantage of this circuit is that it allows chopper
amplifier performance to be achieved at one-tenth the cost.
The only limitation is that during the offset nulling mode, Al
is disconnected from the input. However, in most data
acquisition systems, many inputs are scanned sequentially.
It is fairly simple to synchronize the offset nulling operation
so that it does not occur when that particular amplifier is
being "looked at". For the component values shown in Figure
3, and assuming a total leakage of 50pA at the inverting input
of A2, the offset voltage referred to the input of A1 will drift
away from zero at only 40INlsec. Thus, the offset nulling
information stored on C1 can be "refreshed" relatively
infrequently. The measured offset voltage of A1 during the
amplification mode was 11/N; offset voltage drift with
temperature was less than O.1INloC.

AUTOMATIC OFFSET SUPPRESSION
CIRCUIT
The circuit shown in Figure 3 uses one amplifier (Al) as a
normal gain stage, while the other (A2) forms part of an offset
voltage zeroing loop. There are two modes of operation
which occur sequentially; first, an offset null correction
mode during which the offset voltage of A1 is nulled out.

+5V

130kll

16

lkll

130kll

LOGIC
INPUT

10kll

~________-L~______~/

Figure 3A.

/

/

* SWl, SW"

& SW3 ARE ALL PART OF
A SINGLE IH5043 CMOS ANALOG
SWITCH CONNECTED AS SHOWN
IN FIGURE 38

(

5·170

Figure 3B.

+15V

ICLS043
STAIRCASE GENERATOR
The circuit shown in Figure 4 is a high input impedance
version of the so-called "diode pump" or staircase generator.
Note that charge transfer takes place at the negative-going
edge of the input-signal.
The most common application for staircase generators is in
low cost counters. By resetting the capacitor when the
output reaches a predetermined level, the circuit may be
made to count reliably up to a maximum of about 10. A
straightforward circuit using a LM311 for the level detector,
and a CMOS analog gate to discharge the capacitor, is
shown in Figure 5. An important property of this type of

counter is the ease with which the count can be changed; it is
only necessary to change the voltage at which the
comparator trips. A low cost A-D converter can also be
designed using the same principle since the digital count
between reset periods is directly proportional to the analog
voltage used as a reference for the comparator.
A considerable amount of hysteresis is used in the
comparator shown in Figure 5. This ensures that the
capacitor is completely discharged during the reset period.
In a more sophisticated circuit, a dual comparator "window
detector" could. be used, the lower trip point set close to
ground to assure complete discharge. The upper trip point
could then be adjusted independently to determinethepulse
count.

r

if10100
LOW LEAKAGE
DIODE PAIR

-

F

-

~~

__ I/'
VOUT
}

(2V/DIV)

fJ
-I-

-

I-

- - - - HORIZONTAL

~

VIN
}

(SV/DIV)

SOmS/DIV

Figure 4

IH5042

1kil

1/ ~
100kil

10100
LOW LEAKAGE
DIODE PAIR

---

--

l.r.:' ~

I""""

~

~

~

Your VREF

Figure 5

5-171

.". ~

--- -- --- ,.-- --- 10-1---10--HORIZONTAL

10kil

VOUT

~

200mS/DIV

}

(SV/DIV)

Y,N
}

(SV/DIV)

1:1
l1li

ICLS043
SAMPLE & HOLD CIRCUIT

Actual sample and hold waveforms are shown in Figure 7B.
The center waveform is the analog input, a ramp moving at
about 67V/ms, the lower waveform is the logic input to the
sample & hold; a logic "1" initiates the sample mode. The
upper waveform is the output, displaced by about 1 scope
division (2V) from the input to avoid superimposing traces.
The hold mode, during which the output remains constant, is
clearly visible. At the beginning of a sample period, the
output takes about 81lsec to catch up with the input, after
which it tracks until the next hold period.

Two important properties of the 8043 are used to advantage
in this circuit. The low input bias currents give rise to slow
output decay rates ("droop") in the hold mode, while the high
slew rate (6V/IlS) improves the tracking speed and the
response time of the circuit. See Figure 6.
The ability of the circuit to track fast moving inputs is shown
in Figure 7A. The upper waveform is the input (10V/div), the
lower waveform the output (5V1div). The logic input is high.

+15V
-15V

10
OUTPUT
ANALOG
INPUT

1

-15V

10.000 pF
POLYSTYRENE

12 +5V

11 +15V

10

+3V ~ > SAMPLE MODE
OV ~ > HOLD MODE

IH5043

Figure 6

.....
~

,......",

...........

A.

~I

r

\

.1

......... ~
~

t\r.
r-....

~

~

r--

TOP: INPUT (10VlDIV)
BOTTOM: OUTPUT (5V/DIV)
HORIZONTAL: 10"s/DIV

TOP: 2V1DIV
CENTER: 2VIDIV
BOTTOM: 10VlDIV
HORIZONTAL: 10"s/DIV

Figure 7A

Figure 7B

5·172

..........

......... 1'-0..

ICLS043
INSTRUMENTATION AMPLIFIER
A dual FET input operational amplifier is an attractive
component around which to build an instrumentation
amplifier because of the high input resistance. The circuit
shown in Figure 8 uses the popular triple op-amp approach.
The output amplifier is a High Speed 741 (741 HS, slew rate
guaranteed 20. 7VI p.s) so as to utilize the high slew rate of the
8043 to the maximum extent. Input resistance of the circuit
(either input, regardless of gain configuration) is in excess of
1012 ohms.
For the component values shown, the overall amplifier gain
is 200 (front end gain

= 2Rl + R2,
R2

back end gain,

= R6/R4l.

Common mode rejection is largely determined by the
matching between R4 and R5, and R6 and R7. In applications
where offset nulling is required, a single potentiometer can
be connected as shown in Figure 9.
Another popular circuit is given in Figure 10. In this case the
gain is 1 + Rl/R2, and the CMRR determined by the match
between Rl and R4, R2 and R3.
For more information on FET input operational amplifiers,
see Intersil Application Bulletin A005 "The 8007: A High
Performance FET -input Operational Amplifier."

Figure 8

Figure 9

CHIP TOPOGRAPHY

.087"
- - - - - - " ' ( 2 . 2 1 mm""")------tI~~1

f o.
l ..

2

16
r-l'!!!!!!~r-1. 15

.087"
(2.21 mm)

4

13

Figure 10

12

5-173

ICL8048/8049
Monolithic Log Amplifierl
Monolithic Antilog Amplifier

FEATURES
• 1/2% Full Scale Accuracy
• Temperature Compensated O°C to +70°C
• Scale Factor 1V /Decade, Adjustable
• 120dB Dynamic Current Range (8048)
• 60dB Dynamic VoJtage Range (8048 & 8049)
• Dual FET-Input Op-Amps

GENERAL DESCRIPTION
The 8048 is a monolithic logarithmic amplifier capable of
handling six decades of current input, or three decades of
voltage input_ It is fully temperature compensated and is
nominally designed to provide 1 volt of output for each
deCade change of input_ For increased flexibility, the scale
factor, reference current and offset voltage are externally
adjustable_
The 8049 is the antilogarithmic counterpart of the 8048; it
nominally generates one decade of output voltage for each
1 volt change at the input.

PIN CONFIGURATION

SCHEMATIC DIAGRAM (8048)
V REF

>--'lNv--Q

(outline dwgs JE, PEl

I'

REF

16

VOUT

1D

GNDo--+--~

GROUND

I

NO CONNECTION

3

14

Al OFFSET NULL

4

13

A2 OFFSET NULL

Al OFFSET NULL

5

12

A2 OFFSET NUll

9

NO CONNECTION

Al OUTPUT

7

NO CONNECTION

8

NO CONNECTION

15
GAIN

Al OUTPUT

SCHEMATIC DIAGRAM (8049)

A2 INPUT

14

16
.\,I'.;I'LI1

I

AI OFFSH NUll

4

GAIN
13

A2 OFFSET NULL

12

A'} OFFSET NULL

9

NO CONNECTION

1D

Your

15
GROUND
A 1 OUTPUT

5-174

AIOUTPUl

1

NO CQNNrCTION

!l

ICL8048/8049
ABSOLUTE MAXIMUM RATINGS (8048)

See note under 8049 Absolute Maximum Ratings.

Supply Voltage. . . . . . •

Operating Temperature Range.

· . .O°C to +70°C

IIN( Input Current). . . . • . . • . . .

. .2mA

±18V

Output Short Circuit Duration . . . .

· . . . . Indefinite

IREF (Reference Current). . . • . . .
Voltage between Offset Null and V+ .

. .2mA
. ±0.5V

--65° C to +125° C
Storage Temperature Range . . . . . .
Lead Temperature (Soldering, 60 sec.) . · . . . . . . 300°C

Power Dissipation. . . . • • . . . . . .

. 750mW

OPERATING CHARACTERISTICS (8048)
Vs

= ±15V,

TA

= 25°C,

IREF

= lmA,

scale factor adjusted for IV/decade unless otherwise specified.
8048BC

PARAMETER

CONDITION

MIN.

TYP.

8048CC
MAX.

MIN.

TYP.

MAX.

UNITS

Dynamic Range
liN (lnA-lmA)
VIN (10mV-l0V)

RIN = 10k!l

120

120

60

60

dB
dB

Error, % of Full Scale

TA = 25°C, liN = InA to lmA

.20

0.5

.25

1.0

%

Error, % of Full Scale

T A = O°C to +70°C,

.60

1.25

.80

2.5

%

liN = 1 nA to 1 mA
Error, Absolute Value

TA = 25°C, 'IN= InA to lmA

12

30

14

60

mV

Error, Absolute Value

T A = O°C to +70°C,

36

75

50

150

mV

IIN= lnAto lmA
Temperature Coefficient of VOUT

liN = 1 nA to 1 mA

0.8

Power Supply Rejection Ratio

Referred to Output

2.5

Offset Voltage (AI & A2)

Before Nulling

15

Wideband Noise

At Output, for II N = lOO"A

250

Output Voltage Swing

RL

= 10k!l

RL = 2k!l

±14

±10

±13

200

150

200

mW

5

6.7

5

6.7

mA

g

.21-0.--+-+-

;:

"~
~

" f----+-"-lo_---t-+

~

~

-2 -,.,---

INPUT CURRENT (AMPS)

INPUT VOLTAGE

MAXIMUM ERROR VOLTAGE
AT THE OUTPUT AS A
FUNCTION OF INPUT CURRENT

MAXIMUM ERROR VOLTAGE
AT THE OUTPUT AS A
FUNCTION OF INPUT VOLTAGE

150

(O°c

200

I I

125

Jll 1
\

100

75

,.

o

10 9

10 8

10 7

I

I

10 6

10-5

INPUT CURRENT (AMPS)

8048

50

8048 Be (2S"C)

25
10-4

10-3

k" - r-

---11-

1k -

1---

I---+-+~ll-- I--

100

I

1--+----1r -+---r-

f-

-

-+-

SMALL SIGNAL VOLTAGE GAIN
AS A FUNCTION OF INPUT
VOLTAGE FOR RS = 10 k!l
434

V~~~A~~k~~IN

o
lOmV

lIVIN

I

1'-1'I

III I I

1

lV

5-175

V/v

--

10

W.B~t;;t
l00mV

e

VTN-

~ .4~~~

cc (25~C)

INPUT VOLT AGE

loglO

= 6VOUT"

100

1'-

alll.JJftt

1\

75

8048 CC (2S 3 C)

-

V

III I I I I

8048 Be (DOC to 70 oe)

50

10k 1--+--+-+-

1000

8048 CC (O°c to 70°C\

125

I I

100

150

-..__1-'=

--

INPUT CURRENT lAMPS)

R'N " 10"!

to 10°CI

IREF"'mA

~-t---

-3

8048 CC

SMALL SIGNAL BANDWIDTH
AS A FUNCTION OF INPUT
CURRENT

'3

175

V

150

o

I I

V

±12

~

175

mV
"V(RMS

±14

o
>

~

50

±13

TRANSFER FUNCTION FOR
VOLTAGE INPUTS

"~

200

15
250

±12

Supply Current

TRANSFER FUNCTION
FOR CURRENT INPUTS

25

±10

Power Consumption

mVI"C
mV/V

0.8
2.5

lOV

lmV

t
10rnV

l00mV

INPUT VOLTAGE

1"lV

10V

.D~DIL

ICL804818049
ABSOLUTE MAXIMUM RATINGS (8049)
Supply Voltage . . . . . . .
Y,N (Input Voltage) . . . . . . . . .
'REF (Reference Current) . . . . . .
Voltage between Offset Null and V+
Power Dissipation . . . . . . . . . . .

±18V
±15V

.
.
.
.

. 2mA

. ±O.5V
. 150mW

Operating Temperature Range.
Output Short Circuit Ouration
Storage Temperature Range ..
Lead Temperature (Soldering, 60 sec.) .

· ..O°C to +70°C
· . . . . Indefin ite
4i5°C to +150°C
· . . . . . . 300°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliabilitY.

OPERATING CHARACTERISTICS(8049)
Vs

= ±15V, T A = 25° C,

I REF

= 1 mA,

scale factor adjusted for 1 decade (out) per volt (in), unless otherwise specified.

PARAMETER

CONDITION

Dynamic Range (VOUT)

VOUT = 10mV to 10V

Error, Absolute Value

TA = 25°C. OV$V,N $3V

Error, .a.bsolute Value

TA = O°C to +70°C,

MIN.

8049BC
TYP. MAX.

MIN.

8049CC
TYP. MAX.

60

60

UNITS
dB

3

10

5

25

mV

20

75

30

150

mV

OV$V,N$3V
Temperature Coefficient, Referred to Y,N

Y,N = 3V

Power Supply Rejection Ratio

Referred to Input, for

0.38

0.55

mVrC

2.0

2.0

I"V!V

Y,N =OV
Offset Voltage (A1 & A2)

Before Nulling

15

Wideband Noise

Referred to I nput, for

26

Output Voltage Swing

RL=10k!1

±12

±14

RL=2k!1

±10

±13

25

15

.50

mV

26

I"V(RMS)

±12

±14

V

±10

±13

Y,N = OV

Power Consumption

200

150

200

mW

5

6.7

5

6.7

mA

Supply Current

MAXIMUM ERROR VOLTAGE
REFERRED TO THE INPUT AS A
FUNCTION OF Y,N

TRANSFER FUNCTION
(VOUT AS A FUNCTION OF Y,N)
10r--r-'~~~--r-'-~--'

'0' f-+-I--+-"9-~=
'0 3 '---'--'---'--'-......1---'--'-.......

.001 '---'---'---'--'--''---'--'--''
-4

-3

-2

-1

... 1

INPUT VOLTAGE

+2

+3

o

+4

(V~

INPUT VOL rAGE (VI

SMALL SIGNAL BANDWIDTH
AS A FUNCTION OF
INPUT VOLTAGE

SMALL SIGNAL VOLTAGE GAIN
AS A FUNCTION OF
INPUT VOLTAGE
'RU

lmA

f--- ---1--+-+--/

-23~

-'0 f--"'...L...J

o
INPUT VOLTAGE IV)

INPUT VOLTAGE (VI

. 5·176

V

150

ICL8048/8049
THEORY OF OPERATION
The 8048 relies for its operation on the well·known expo·
nential relationship between the collector cuuent and the
base·emitter voltage of a transistor:

carefully designed to provide the necessary compensation.
Resistor R2 is external and should be a low T.C. type; it
should have a nominal value of 1 kn to provide 1 volt/
decade, and must have an adjustment range of ±20% to
allow for production variations in the absolute value of R 1.

(1 )

For base·emitter voltages greater than 100mV, Eq. (1)
becomes
qVBE/
IC ~ IS e
/kT

(2)

From Eq. (2), it can be' shown that for two identical
transistors operating at different collector currents, the
VBE difference ([WBE) is given by:

~ -2.303 x kqT log 10 [rC1/IC2]

OFFSET AND SCALE FACTOR ADJUSTMENT·
A log amp, unlike an op-amp, cannot be offset adjusted by
simply grounding the input. This is because the log of zero
approaches minus infinity; reducing the input current to
zero starves 01 of collector current and open the feedback
loop around A1. Instead, it is necessary to zero the offset
voltage of A1 and A2 separately, and then to adjust the
scale factor. Referring to Fig. 1, this is done as follows:

Referring to Fig. 1, it is clear that the potential at the
collector of 02 is equal to the t.VBE between 01 and 02.
The output voltage is t.VBE multiplied by the gain of A2:

1) Temporarily connect a 10kn resistor (RO) between
pins 2 and 7. With no input voltage, adjust R4 until
the output of A1 (pin 7) is zero. Remove RO.
Note that for a current input, this adjustment is not
necessary since the offset voltage of A1 does not
cause any error for current·source inputs.

~ -2.303(R~2+ R2)(k:) log 10 CINIJREF}4)

2) Set liN ~ IREF ~ 1mA. Adjust R5 such that the
output of A2 (pin 10) is zero.

t.VBE

VOUT

(3)

The expression 2.303 x kT has a numerical value of 59mV
q

at 25°C; thus in order to generate 1 volt/decade at the
output, the ratio (R1 + R2)!R2 is chosen to be 16.9. For
this scale factor to hold constant as a function of tempera·
ture, the (R1 + R2)/R2 term must have a 1/T characteristic
to compensate for kT /q.
In the 8048 this is achieved by making R1 a thin film
resistor, deposited on the monolithic chip. It has a nominal
value of 15.9kn at 25° C, and its temperature coefficient is

3) Set liN ~ 11lA, IREF ~ 1mA. Adjust R2 for
VOUT ~ 3 volts (for a 1 volt/decade scale factor)
or 6 volts (for a 2 volt/decade scale factor).
Step #3 determines the scale factor. Setting liN ~ 11lA
optimizes the scale factor adjustment over a fairly wide
dynamic range, from 1mA to 1nA. Clearly, if the 8048 is to
be used for inputs which only span the range 100llA to
1mA, it would be better to set liN ~ 100llA in Step #3.
Similarly, adjustment for other scale factors would require
different II Nand VOUT values.
·See A053 for an automatic offset nulling circuit.

FIGURE'. ICL8048 OFFSET AND SCALE FACTOR ADJUSTMENT

5·177

ICL8048/8049
THEORY OF OPERATION

For voltage references equation 7 becomes

The 8049 relies on the same logarithmic properties of the
transistor as the 8048. The input voltage forces a specific
L'1VBE between 01 and 02 (Fig. 2). This VBE difference
is converted into a difference of col.lector currents by the
transistor pair. The equation governing the behavior of the
transistor pair is derived from (2) on Page 3 and is as follows:
ICV =
[qL'1VBE/ ]
/ IC 2 exp
/kT ,

VOUT = VREF x ROUT exp r~ x q V,N ]
RREF
URI + R2
kT

OFFSET AND SCALE FACTOR ADJUSTMENT*
As with the log amplifier, the antilog amplifier requires
three adjustments. The first step is to null out the offset
voltage of A2. This is accomplished by reverse biasing the
base·emitter of 02. A2 then operates as a unity gain buffer
with a grounded input. The second step forces V,N = 0;
the output is adjusted for VOUT = 10V. This step essentially "anchors" one point on the transfer function. The
third step applies a specific input and adjusts the output to
the correct voltage. This sets the scale factor. Referring to
Fig. 2, the exact procedure for 1 decade/volt is as follows:

(5)

When numerical values for q/kT are put into this equation,
it is found that a L'1VBE of 59mV (at 25°C) is required to
change the collector current ratio by a factor of ten. But
for ease of application, it is desirable that a 1 volt change
at the input generate a tenfold change at the output. The
required input attenuation is achieved by the network comprising Rl and R2. In order that scale factors other than
one decade per volt may be selected, R2 is external to the
chip. It should have a value of lkU, adjustable ±20%, for
one decade per volt. Rl is a thin film resistor deposited on
the monolithic chip; its temperature characteristics are
chosen to compensate the temperature dependence of
equation 5, as explained on Page 3.

1) Connect the input (pin #16) to +15V.
This
reverse biases the base·emitter of 02. Adjust R7
for VOUT = OV. Disconnect the input from +15V.
2) Connect the input to Ground.
Adjust R4 for
VOUT = 10V. Disconnect the input from Ground.
3) Connect the input to a precise 2V supply and adjust
R2 for VOUT = 100mV.

The overall transfer function is as follows:
IOUT/
[-R2
qVINl
/IREF = exp ~Rl + R2) x ~J
Substituting VOUT

_

=

(6)

lOUT x ROUT gives:

r

-R2
qVINl
VOUT - ROUT IREF exp ~Rl + R2) xi(TJ

(7)

The procedure outlined above optimizes the performance
over a 3 decade range at the output (i. e., VOUT front
10mV to 10V). For a more limited range of output
voltages, for example 1 Vto 10V, it would be better to
use a precise 1 volt supply and adjust for VOUT = IV.
For other scale factors and/or starting points, different
values for R2 and RREF will be needed, but the same basic
procedure applies.
*See A053 for an automatic offset nulling circuit.

v'

(8)

VREF
(+15VI

",

2kf!

FIGURE 2. ICL8049 OFFSET AND SCALE FACTOR ADJUSTMENT

5-178

ICL8048/8049
APPLICATIONS INFORMATION
Scale Factor Adjustment
The scale factor adjustment procedures outlined on Page 3
(8048) and Page 5 (8049) are primarily directed towards
setting up 1 volt (l:.VOUT) per decade (l:.IIN or l:.VIN) for
the log amp, or one decade (l:.VOUT) per volt (l:.VIN) for
the antilog amp.
This corresponds to K = 1 in the respective transfer func·
tions:
Log Amp: VOUT = -K log 10

[II~REFJ

Frequency Compensation
Although the op-amps in both the 8048 and the 8049 are
compensated for unity gain, some additional frequency
compensation is required. This is because the log transistors
in the feedback loop add to the loop gain. In the 8048,
150 pF should be connected between Pins 2 and 7 (Fig. 1).
In the 8049, 200 pF between Pins 3 and} is recommended
(Fig. 2).
Error Analysis
Performing a meaningful error analysis of a circuit con·
taining log and antilog amplifiers is more complex than
dealing with a similar circuit involving only op-amps. In
this data sheet every effort has been made to simplify the
analysis task, without in any way compromising the validity
of the resu Ita nt nu mbers.

(9)

Antilog Amp: VOUT = ROUT IREF 10 -VUYK (10)
By adjusting R2 (Fig. 1 and Fig. 2) the scale factor "K" in
equation 9 and 10 can be varied. The effect of changing K
is shown graphically in Fig. 3 for the log amp, and Fig. 4
for the antilog amp. The nominal value of R2 required to
give a specific value of K can be determined from equation
11. It should be remembered that R 1 has a ±20% tolerance
in absolute value, so that allowance shall be made for ad·
justing the nominal value of R2 by ±20%.

R2

=

941
(K-.059)

(11)

n

EFFECT OF VARYING UK·· ON
THE LOG AMPLIFIER
12

I'\.

10

IREF"'lmA

'\.
........

-

........

The key difference in making error calculations in log/
antilog amps, compared with op-amps, is that the gain of
the former is a function of the input signal 'level. Thus, it
is necessary, when referring errors from output to input, or
vice versa, to check the input voltage level, then determine
the gain of the circuit by referring to the graphs given on
Pages 2 and 4.
The various error terms in the log amplifier, the 8048, are
Referred To the Output (RTO) of the device. The error
terms in the antilog amplifier, the 8049, are Referred To
the Input (RTI) of the device. The errors are expressed
in this way because in the majority of systems a number
of log amps interface with an antilog amp, as. shown
in Fig. 5.

~

k.1'\.
r- ~ "-r- :::::: ~
........

-2
10-1010-9 10-8

1O~7

ERROR DUE TO A {ATO)

10-6 10-5 10-4 10-3

INPUT CURRENT (AMPS)

FIGURE 3

EFFECT OF VARYING UK'· ON
THE ANTILOG AMPLIFIER

FIGURE 5

It is very straIghtforward to estimate the system error at
node (A) by taking the square root of the sum·of·the
squares of the errors of each contributing block.
INPUT VOLTAGE (V)

Total Error ;. .Jx2 + y2 + z2

FIGURE 4

5-179

at (A)

m

.D~OIL

ICL804818049
If required, this error can be referred to the system output
through the voltage gain of the anti.log circuit, using tl)e
voltage gain plot on Page 4.
. .
The numerical values of x, y, and z in the above equation
are obtained from th" maximum error voltage plots given
on Pages 2 and 4. For example, with the 8048BC, the
maximum error at the output is 30mV at 25°C. This
means that the measured output will be within 30mV of
the theoretical transfer function, provided the unit has
been adjusted per the procedures on Page 3. Fig. 6 illustrates this point.
To determine the maximum error over the operating temperature range, the 0 to 70° C absolute error values given
in the table of electrical characteristics should be used. For
intermediate temperatures, assume a linear increase in the
error between the 25°C value and the 70°C value.
For the antilog amplifier, the only difference is that the
error refers to the input, i. e., the horizontal axis. It will
be noticed that the maximum error voltage of the 8049,
over the temperature range, is strongly dependent on the
input voltage. This is because the output amplifier, A2,
has an· .offset voltage drift which is directly transmitted to
the output. When this error is referred to the input, it must
be divided by the voltage gain, which is input voltage
dependent. At VIN = 3V, for example, errors at the
output are multiplied by 1/.023 (= 43.5) when referred
to the input.
It is important to note that both the B048 and the 8049
require positive values of IREF' and the input (8048) or
output (8049) currents (or voltages) respectively must
also be positive. Application of negative liN to the 8048
or negative IREF to either circuit will cause malfunction,
and if maintained for long periods, would lead to device
degradation. Some protection can be provided by placing a diode between pin 7 and ground.

SETTING UP THE REFERENCE CURRENT
In both the 8048 and the 8049 the input current reference
pin (lREF) is not a true virtual ground. For the 8048, a
fraction of the output voltage is seen on Pin 16 (Fig. 1).
This does not constitute an appreciable error provided
VREF is much greater than this voltage. A 10V or 15V
reference satisfies this condition. For the 8049, a fraction
of the input voltage appears on Pin 3 (Fig. 2), placing a
similar restraint on the value of VREF.
Alternatively, I R EF can be provided from a true current
source; One method of implementing such a current source
is shown in Fig. 7.

LOG OF RATIO CIRCUIT, DIVISION
The 8048 may be used to generate the log of a ratio by
modulating the IREF input. The transfer function remains
the same, as defined by equation 9:
(9)

VOUT = -K 10910 [II%EF]

Clearly it is possible to perform division using just one
8048, followed by an 8049.
For multiplication, it is
generally necessary to use two log amps, summing their
outputs into an antilog amp.
To avoid the problems caused by the IREF input not being
a true virtual ground (discussed in tl)e previous section), the
circuit of Fig. 7 is again recommended if the IREF input
is to be modulated.

APPLICATION NOTES
For further applications assistance. see
A007 "The ICL8048/8049 Monolithic Log-Antilog Amplifiers", by Ray Hendry

TRANSFER FUNCTION FOR
CURRENT INPUTS

+15V

VREF!

+15V

J

R,

10------1
2N2219

1Dka

-8 L......I.--'_.J--l.._L-...!--I
10-10 10-9 to-8 10-1 10-6 10-5 10-4 10-3
INPUT CURRENT (AMPS)

Actual output will lie
within shaded area for
8048 BC at 25° C

FIGURE 6

( TO PIN 16 ON 8048)
TO PIN 30N8049

FIGURE 7

5-180

ICL804818049
DEFINITION OF TERMS
In the definitions which follow, it will be noted that the
various error terms are referred to the output of the log

amp, and to the input of the antilog amp. The reason for
this is explained on Page 6.

DYNAMIC RANGE The dynamic range of the 8048 refers
to the range of input voltages or currents over which the
device is guaranteed to operate. For the 8049 the dynamic
range refers to the range of output voltages over which the
device is guaranteed to operate.

TEMPERATURE COEFFICIENT OF VOUT OR V/N For
the 8048 the temperature coefficient refers to the drift
with temperature ~f VOUT for a constant input current.

ERROR, ABSOLUTE VALUE The absolute error is a
measure of the deviation from the theoretical transfer function, after performing the offset and scale factor adjustments as outlined on Pages 3 (8048) or 5 (8049). It is
expressed in mV and referred to the linear axis of the
transfer function plot. Thus, in the case of the 8048, it is
a measure of the deviation from the theoretical output
voltage for a given input current or voltage. For the 8049
it is a measure of the deviation from the theoretical input
voltage required to generate a specific output volta!je.

The absolute error specification is guaranteed over the
dynamic range.
ERROR, % OF FULL SCALE The error as a percentage of
full scale can be obtained from the following relationship:

For the 8049 it is the temperature drift of the input voltage
required to hold constant value of VOUT.

a

POWER SUPPL Y REJECTION RATIO The ratio of the
voltage change in the linear axis of the transfer function
(VOUT for the 8048, VIN for the 8049) to the change·
in the supply voltage, assuming that the log axis is held
constant.
WIOEBAND NOISE For the 8048, this is the noise occurring at the output under the specified conditions. In the
case of the 8049, the noise is referred to the input.
SCALE FACTOR For the log amp, the scale factor (K) is
the voltage change at the output for a decade 0. e. 10:1)
change at the input. For the antilog amp, the scale factor
is the voltage change required at the input to cause a one
decade change at the output. See equations 9 and 10.

,m. .

100 x Error, absolute value
Full Scale Output Voltage
__
--_-_-_-_-_-_-_c_-_-_-_-_-_-_-_-_-___________________________________________________

E_r _o_r_'~_O_O_f_F_U_I _s_c_a_le_=

___

ORDERING
INFORMATION
r
TYPE
8048 BC
8048 BC
8048 CC
8048 CC
8049 BC
8049 BC
8049 CC
8049CC

PACKAGE
16 Pin
16 Pin
16 Pin
16 Pin
16 Pin
16 Pin
16 Pin
16 Pin

CERDIP
Plastic DIP
CERDIP
Plastic DIP
CERDIP
Plastic DIP
CERDIP
Plastic DIP

MAX. ABSOLUTE
ERROR. (25°C)

TEMPERATURE RANGE
O°C
O°C
O°C
O°C
O°C
O°C
O°C
O°C

30mV
30mV
60ll)V
60mV
10mV
10mV
25mV
25mV

5-181

to
to
to
to
to
to
to
to

+70°C
+70°C
+70°C
+70°C
+70°C
+70°C
+70°C
+70°C

ORDER PART NUMBER
ICL 8048 BC
ICL 8048 BC
ICL 8048 CC
ICL 8048 CC
ICL 8049 BC
ICL 8049 BC
ICL 8049 CC
ICL 8049 CC

JE
PE
JE
PE
JE
PE
JE
PE

ICLS063
Power Transistor Driver-Amplifier

FEATURES:
• Converts ±12VOutputs from Op Amps and other
linear functions to ±30V levels
• When used In conjunction with general-purpose
op amps and external complementary power
transistors, system can deliver> 50 Watts to
external loads
• Has built-in Safe Area Protection and short-circuit
protection
• Produces 25mA quiescent current in power amp
configuration while delivering ±2 Amps output
current
• Has built in±13V Regulators to power op amps or
other external functions
500kO, input imped-.---------~~:

+

10,Ooo,.F
_*@50WVDC

Figure 16: Hi Fi Amplifier

-'-16

1----

---~,i

RL ""..,

+12

~\~

"L'1011
cc.o~\

\

\\

,

,

,.0---------------;

~\i\

+4

"L-10n
\
cc • 1000pF ----..\

\

\

\

-2

i

100

1k

10k

100k

1M

f-(Hz)

10k
-3DY

OUT VS. Frequency For Typicat Circuit Shown
Figure 17: Typical Performance Curve of EV
IN

5-188

'

.n~nlb

ICL8063

r----.~r_--~--~r_--~--------~~13
+30Y

500k

'" ~

400k

300k

\

to
z

200k

100Hz

VIN - VA

~

lOOk

1kHz

R,

lOOk X VA

ZIN= - - - - -

\

10kHz
100kHz
f-(Hz)

1M

10M

-30V

Figure 18: Typical Performance Curve of Input Impedance Versus Frequency for Typical Circuit Shown

CHIP TOPOGRAPHY

Note: Intersil offers a hybrid power amplifiersimilartothat
shown in fig. 9. See ICH8510/8520/8530 data sheet for
details.

ICLS069 Series
Low Voltage Reference

FEATURES

GENERAL DESCRIPTION

- Temperature Coefficient guaranteed to 10 ppmfO C
max.
- Low Bias Current ... 50",A min
- Low Dynamic Impedance
-Low Reverse Voltage
-,Low Cost

The ICL8069 is a 1.2V temperature compensated voltage
reference. It uses the band~gap principle to achieve excellent
stability and low noise at reverse currents down to 50",A.
Applications include analog-to-digital converters, digital-toanalog converters, threshold detectors, and voltage
regulators. Its low power consumption makes it especially
suitable for battery operated equipment.

TYPICAL CONNECTION DIAGRAMS

+5V

+ 15V
2.2ktl

ICL8069
- - -.......- - - + 5 V

r---.

v+

15kn
1.8kU

10kn

r-----

*
l
. . i>-_--<1~......-<>J
: ICL8069 1

4.7"F"

+10Yout

10kn

1kn

REF HI

.:::j

---0

YOUT

*See Note 1

la) Simple Reference 11.2 volts or less)

ICL7107

1'.4~

ICL8069

Ibl Buffered IOV Reference 'using a
single supply.

ORDERING INFORMATION

COMMON
REF LO

Ic) Double regulated I OOmV reference
for ICL7107 one-chip DPM circuit.

PIN CONFIGURATION
TO-52

Max. Temp. CoeH.
of VREF
O.OOI%I·C
O.OO25%I"C
O.OO5%I"C
O.OO5%I·C
O.OI%I·C
O.OI%I·C

Temp. Range
O·C to +70·C
O·C to +70·C
D·C to +70·C
-55·C to +125·C
O·C to +70·C
-55·C to +125·C

Order PIN
TO-92

TO-92

Order PIN
TO~2

ICL8069ACSQ
ICL8069BCSQ
ICL8069CCSQ
ICL8069CMSQ
ICL8069DCSQ
ICL8069DMSQ

ICL8069CCZR

-

ICL8069DCZR

-

PACKAGE DIMENSIONS
.~~1_!l·209-0.2"

(S.3Ot-5.S631

~~~_I'O."'l!-O.l59

(4.521-4.151)'1

SEATING

-r
Tffr
0 0 O--l_i l (~2~

PLANEp_1 III
!

,:::

OjJ1:~:.O"

(0.401-0,4131

TO-92

il\3.601-4.039\
I~.

TO-52

5-190

CHIP TOPOGRAPHY
V+

ICLS069 Series
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the

Reverse Voltage ............................. See Note 2
Forward Current .................................. 10mA
Reverse Current .................................. 10mA
Power Dissipation . Limited by max forward/reverse current
Storage Temperature ................... --u5° C to+150° C
Operating Temperature
ICL8069C .............................. 0°Cto+70°C
ICL8069M .......................... -55°Cto+125°C
Lead Temperature (Soldering, 10Sec) ............ : 300°C

ELECTRICAL CHARACTERISTICS

operation sections of this specification is not implied.

Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

(@ 25°C unless otherwise noted)

CHARACTERISTICS

CONDITIONS

MIN

TYP

MAX

UNITS

Reverse breakdown
Voltage

IR = 500ilA

1.20

1.23

1.25

V

Reverse breakdown
Voltage change

50l'A

Reverse dynamic Impedance

~

IR ,; SmA

IR = 5Ol'A
IR = 500ilA

15

20

mV

1
1

2
2

n

1

Forward Voltage Drop

IF = 500ilA

.7

RMS Noise Voltage

10Hz ~ f ~ 10kHz
IR = 500ilA

5

!

Breakdown voltage
Temperature coefficient:
ICL8069A
ICL8069B
ICL8069C
ICL8069D

I," 500,A

TA = operating
temperature range
(Note 3)

Reverse Current Range

V
I'V

.050

.001
.0025
.005
.01

%/oC

5

mA

TYPICAL PERFORMANCE CHARACTERISTICS
REVERSE VOLTAGE AS A
FUNCTION OF CURRENT

VOLTAGE CHANGE AS A
FUNCTION OF REVERSE CURRENT

REVERSE VOLTAGE AS
A FUNCTION OF TEMPERATURE

lamA

14

1.245

'R ' ."~A
=

1.240

...~

".

//

+125"C

~

-,

10,uA

l00,uA

1m...

REVERSE CURRENT

....
.

.,.."::::::::::

~~25OC,

+'[7l;(.•. y ~F

:0
:0

./

.2

.4

.6

.•

1.0

REYERSE VOLTAGE (V)

1.225

f""""

.-

0

/'

10mA

1.235

!j
0 1.230
>

-55"C /

1.220
1.215
1.2

1.4

--50

-25
0
+25 +50 +75 +100 +125
TEMPERATURE (OC)

Not ••:
1) If circuit strays in excess of 200pF are anticipated, a 4.7"F shunt capacitor will ensure stability under all operating conditions.
21 In normal use, the reverse voltage cannot exceed the reference voltage. However when plugging units into a powered-up test fixture. an
instantaneous voltage equal to the compliance of the test circuit will be seen. This should not exceed 20V.
3) For the military par), measurements are made at 25° e, --55° e, and +125° e. The unit is then classified asa function of the worst case T.e. from
25° e to -55° e, or 25° e to +125° e.

5-191

ICL8075-9
,;,_cision Temperature
. fflzed Voltage References

The series of devices is produced by adjusting basic parts
with various metal masks so that exact voltages are available
for the mo!!t popular AID and D/Aconverters. This avoids the
necessity to perform adjustments in most cases, and
reduces the problems with trim range and temperature coef·
ficient loss iri all. others.

FEATURES

• Laser-trimmed to precise voltage
• Extremely low temperature coefficient
(typ< 1ppm/OC)
• Short-circuit protected
• Thermally isolated die for minimum power
consumption
.
• Separate heater supply for good noise rejection,
application flexibility
• Wide range of end-use oriented output voltages
• Wide operating voltage range on both reference
and heater
• Heater control system operates correctly at low
voltage, avoiding thermal latch up problems

II
.

..

This series is divided into two basic groups, those with out·
puts less than the band·gap voltage (ICL8075/6), and those
with higher outputs (ICL8077/8/9). The nominal reference
voltage (cardinal value) is coded in the second part of the
number, with two digits and a "D" for a decimal value or a "8"
for a binary value, at the decimal point location.
Each device is packaged in a standard 8·pin TO·99 package,
but the die is mounted on an insulating ceramic substrate to
ensure a high thermal resistance from the die to the case.
This usuaUy undesirable condition is beneficial in this case,
since it reduces the power consumption of the heater as far
as possible, and .facilitates maintaining the die temperature
at about 85·C, even in cold ambient conditions.

GENERAL DESCRIPTION
The ICL8075-9 are a family of precision laser·trimmed vol~·
age references that incorporate a substrate heater to pro·
duce extremely IQw overall. voltage temperature coefficients.

PIN CONFIGURATION

ORDERING INFORMATION
PART
NUMBER

VOLTAGE

ICL8075·001

0.10

ICL8076-100

1.00

ICL8076-1DOJCTV

ICL8077-205

2.50

ICL8077-205JCTV ICL8077·205:"CTV

0.4% (S·Bln

(outline dwg TV)

0.03% (12·Btn

ICL8075·001 JCTV ICL8075·0D1LCTV
ICL8076·1DOLCTV

ICL8077·2B5

2.56

ICL8077-2B5JCTV ICL8077-2B5LCTV

ICL8078-500

5.00

ICL8078-5DOJCTV ICL8078·500LCTV

I CL8078·5 B 1

5.12

ICL8078-5B1 JCTV

ICL8078-5B1LCTV

v,-

ICL8079-100

10.00

ICL8079-10DJCTV

ICL8079-10DLCTV

IClS07S/6

ICL8079·10B

10.24

ICL8079·10BJCTV

ICL8079-10BLCTV

IClS077lS/9
TO·99

BLOCK DIAGRAMS
.------~-O~+

.....-ov,+

.-----~-

.--------e-- 1.2)

Heater Supply

V+
2

MIN

TYP

MAX

UNIT

3.2

30

VOUT + 2
8

30
30

V

0.1
0.02

0.4
0.03

%

Absolute Accuracy of VOUT

Heater Settled

Line Regulation

V, + to V, - = 15V to 30V

0.002

0.005

%N

load Regulation of VOUT
(ICl8077l8/9 Only)

lOUT = OmA to 5mA

0.03

0.05

%/mA

40
40

mA

J Grade
l Grade

Short·Circuit Limits
VOUT (ICL8075/6)
(lCl8077/8/9)
VBG (ICl8075/6)
(ICl8077l8/9)

1
20
20
1

Isc
(Note 1)

Output Drive Capabi lity
VOUT
VBG

ICL8077/8/9 Only (Note 2)
ICL8075/6 Only

Maximum Heater Current

IHTR

Supply Current
Reference Section
Heater Section

1+
2

5
0

,

(+
Device Warmed Up (Still Air)

10

7

mA

90

130

mA

250
15

450
20

mA

Temperature Coefficient of VOUT

V2 +>8V, -55·C-.....

-t:+

v,4

H~---R-E-FE--EN-C....E > - - - - - '

DETAILED DESCRIPTION
The ICL8075-9 family consists of two semi-independent circuits within one die. One of these is a band-gap reference circuit with several possible mask options, each of which can
be laser-trimmed to a specific value of output voltage. The circuit configuration depends on whether this voltage is less
than or greater than the actual band-gap voltage (1,25V) itself.
The laser-trimming is also used to reduce as far as possible
the intrinsic temperature coefficient of the basic band-gap
circuil. For devices whose output is lower than 1.2V, the bandgap voltage is divided by a pair of resistors to provide the
required output, with the ratio of these resistors being ad,
justed to achieve the desired result. The higher output
devices divide down the output of the internal amplifier to
the band-gap value, again adjusting the resistor ratio to the
requisite value.

and compares it to the voltage drop across a string of diodes.
The result of the comparison is used to drive a pair of large
heater transistor/resistor elements. The inherent feedback of
this combination causes the die to be heated until the diode
drop matches the band-gap-derived reference level, thus
ensuring an almost constant temperature on the die. Care
has been taken in the die layout to ensure that the large currents and temperature gradients associated with the heater
do not degrade the accuracy and consistency of the bandgap reference output of the other section. Also, the die has
been mounted on a thermally isolating substrate to reduce
the required heater power and the temperature gradients
across the die_ The result is that the reference circuit sees
only about 11100 of the ambient temperature change, allowing a 1ppm/oC temperature coefficient to be achieved in
monolithic fprm.

The other section of the circuit is a constant temperature
. heater system, which takes another band-gap type voltage

5·194

ICL8075-9
The coexistence of two circuits on one die has some implications, however. The high currents that flow in the heater section need to be isolated from the reference section, so
separate supply pins are provided for the two sections.
Although these are fairly independent, there is only one
substrate for the die, which must be attached to one of the
supplies, and therefore restrict the "freedom" of the other. In
the ICL8075 family, the substrate is tied to the negative terminal of the heater supply (V2 -), and the negative supply of
the reference section (the V1 - pin) must not be allowed to be
negative with respect to this point.
The heater will take some time to heat the die up to its
operating temperature. During this time, the output voltage
will change at a rate determined by the intrinsic temperature
coefficient of the reference, leading to some appreciable
"warm-up" drift. The time required for this drift is given as the
settling time for the heater, although the heater dissipation

settling time is substantially longer, owing to the longer
thermal time constants of the package. Further, the choice of
the die operating temperature leads to some compromises
also. Clearly, the higher the operating temperature, the more
power needed to sustain it at any given ambient temperature,
and also the poorer the reliability of the device. On the other
hand, if too Iowa temperature is chosen, the point at which
temperature stabilization breaks down will be within the
desirable operating range, leading to a degraded temperature coefficient. The ICL8075 family is laser-trimmed to
stabilize at about + 85'C, so that the temperature coefficient
break point is outside the commercial and industrial
temperature ranges.
The trim pads on the ICL8075/6 and ICLB077/B/9 can be used
to adjust the output voltage, in either direction, to finer precision than is available in the part itself. Figures 1 and 2 show
two methods of adjustment, suitable for either type of device.

T
+
-

>-_--t-----_+YSG

T1
ICL8075/6

VSG

ICL80nl8/9

T2

Y1-

V1-

Figure 1. Fine Trim Circuit

Y1+

T
YSG

+

YREF

T1

T1

ICL8075/6

ICL8077/8/9

T2

VaG

T2

YREF

•
~~
V1-

Y1-

Figure 2_ Alternative Trim Circuit

5-195

ICL8075-9
APPLICATIONS
There are many possible applications of reference circuits, of
course. One typical use is in AID converters, such as the
4 %-digit integrating converter shown in Figure 3. This
schematic is roughly that of the ICL7135EV/Kit evaluation kit,
on which provision has been made to accept an ICL8076-1 DO
as a 1.000V reference. The PC board includes space for a
potentiometer for fine adjustment of the voltage, since the
accuracy of the ICL7135 is higher than that of the best grade
of ICL8076.

Another common requirement is for references .for D/A converters, such as the ICL7134 shown in Figure 4. This device
offers 14-bit accuracy, without laser-irimming, by the expedient of using a CMOS PROM on the die to correct for the errors of the analog section. The circuit shown is that. with a
bipolar output, using a chopper-stabilized op amp, the
ICL7650, to achieve high accuracy without adjustments and
at low cost. A "binary" type of reference here will lead to a
decimal value for the LSB; thus a 10.24V reference gives an
LSB of 1/16mV.
4-112 DIGIT LCD DISPLAY

BACKPLANE

f _ - - - - - + - H - - - < 6~~~~~J READINGS/SEC
L-_ _ _ _ _ _ _ _--~5.p

03 18

34
04 1 7 t - - - - - - + - + - - - - - - - -_ _ _ _,.,D.

ICM7211A

Ba 1 6 f _ - - - - - + - + - - - - - - - - - - - - " " l 3 0 .,

2,3,4,

~15f_-----+-+_-----------~~ ~

37-40

28 .,

ose 3!,..,

6~26,

.. J. ..

~:~~~~~R

.. T" 22pF-100pF
+5V

OV

Figure 3. 4 V. -Digit AID Converter

+8V
TO'+15V

DATA
INPUTS

+5V 17

Figure 4_ 14-Bit D/A Converter Without Adjustments

5-196

+5V

ICL8075-9
APPLICATIONS (Continued)
Other applications are in accurate power supply circuits,
such as that shown in Figure 5, which uses an ICH8530 power
amplifier and a standard AD7541 DAC to set the output value.

Up to 3A at up to ± 30V can be controlled by this circuit, with
errors well under 0.1 %. The circuit is based on the same prin'
ciple as Figure 4, but with a power output buffer.
16

5
VREF ..,1'7
'14 - - - - - ,
+15V 13

~~~s;: LSB
6
+15V

T1VBG T2
VI'
ICL8079·10B
VREF
V2+

12}

11
:0

7

BIT
SWITCHES

8

100pF

3Ok!l

10k!l

7.5k!l

Figure 5. Accurate Power Supply Circuit

5·197

.U~DIL

ICL8211,ICL8212
Programmable Voltage Reference

FEATURES

GENERAL DESCRIPTION

• High accuracy voltage sensing and generation:
internal reference 1.15 volts typical
• Low sensitivity to supply voltage and temperature
variations
• Wide supply voltage range: Typ. 1.8 to 30 volts
• Essentially constant supply current over full supply
voltage range
• Easy to set hysteresis voltage range
• Defined output current limit - ICL8211
High output current capability - ICL8212

The Intersil ICL8211/12 are micropower bipolar monolithic
integrated circuits intended primarily for precise voltage
detection .and gel:leration. These circuits consist of an
accurate voltage reference, a comparator and a pair of
output buffer/drivers.
Specifically, the ICL8211 provides a 7mA current limited
output sink when the voltage applied to the 'THRESHOLD'
terminal is less than 1.15 volts (the internal referencel. The
ICL8212 requires a voltage in excess of 1.15 volts to switch its
output on (no current limitl. Soth devices have a low current
output (HYSTERESIS) which is switched on for input
voltages in excess of 1.15V. The HYSTERESIS output may be
used to provide positive and noise free output switching
using a simple feedback network.
Applications include:
1. Low voltage sensor/indicator
2. High voltage sensor/indicator
3. Non volatile out-of-voltage range sensor/indicator
4. Programmable voltage reference or zener diode
5. Series or shunt power supply regulator
6. Fixed value constant current source

PIN CONFIGURATION

SCHEMATIC DIAGRAM
HYSTERESIS

N/C

RS

4.Skil

-+-__-=2-<> HYST

L-_ _

GROUND

(outline dwg PAl

loutline dwg TV)

ORDERING INFORMATION
Part Number
ICL8211CPA
ICL8211CTY
ICL8211MTY
ICL8212CPA
ICL8212CTY
ICL8212MTY
ICL8211D
ICL8212D

Tel11J)erature Ranae
o to +70°C
o to +70°C
-55° to +125° C
o to 70°C
o to 70°C
-55 to +125°C
Dice only
Dice only

THRESHOLD

Packaae
8 lead Mini DIP
TO-99 Can
TO-99 Can
8 lead Mini DIP
TO-99 Can
TO-99 Can

x

<~ R6

~> 100kn
x

- - - - ICL8211 option
x x x x ICL8212 option

5·198

ICL8211/ICL8212
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage ............................................... -{l.S to +30 volts
Output Voltage ............................................... -{l.S to +30 volts
Hysteresis Voltage ............................................ +o.s to,-10 volts
Threshold Input Voltage ................ +30 to -S volts with respect to GROUND
and +0 to -30 volts with respect to V+
Current into Any Terminal .............................................. ±30mA
Power Dissipation (Note 1 & 2) ..................... ,................... 300mW
Operating Temperature Range ICL8211M/1~M ................. -SsoC to +125°C
Operating Temperature Range ICL8211C/1':1C .............. , ....... , 0 to +70°C
Storage Temperature Range .. ,., .............................. -6SoC to +lS0°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device, These are stress ratings only. and
functional operation of the device at these or any other conditions a:bove those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE 1: Rating applies for case temperatures to 125°C to ICL8211MTY/12MTY products. Derate linearly at -10mW;oC for ambient
temperatures above 100°C.
NOTE 2: Derate linearly above 50°C by -10mW;oC for ICL8211C/12C products. The threshold input voltage may exceed +7 volts for short
periods of time. However for continuous operation this voltage must be maintained at a value less than 7 volts.

TYPICAL OPERATING CHARACTERISTICS (v+ = SV, TA =2SOC unless otherwise specified)
PARAMETER
Supply Cu rrent

1+

Threshold Trip Voltage

VTH

Threshold Voltage Disparity
Between Output & Hysteresis
Output
Guaranteed Operating Supply
Voltage Range

VTHP

Typical Operating Supply
Voltage Range
Threshold Voltage
Temperature Coefficient
Variation of Threshold Voltage
with Supply Voltage
Threshold Input Current
Output Leakage Current

Output Saturation Voltage
Max Available Output Current

CONDITIONS

SYMBOL

2.0 < V+ < 30
VT = 1.3V
VT = 0.9V
lOUT = 4mA V+ = 5V
V+ = 2V
VOUT = 2V
V+ = 30V

"

VSupp

--{)5°C to +125°C
+25°C
+125°C
--{)5°C

VsuPP

lOUT - 4mA
VOUT = 2V
t> V+ - 10% at V+ = 5V

t>VTH/t>T

t>VTH/t>V+

VTH = 1.15V
VTH = 1.00V
VOUT = 30V
VOUT = 30V
VOUT = 5V
VOUT = 5V
lOUT = 4mA

ITH
IOlK

VSAT
IOH

Hysteresis Sat Voltage

VHYS (max)

Max Available Hysteresis Current

IHYS (max)

ICL821
TYP
22
140
1.15
1.145
1.165
-8.0

IHYST - -7p.A VTH - 1.3V
measured with respect to V+
VTH - 1.3V

40
250
1.19
1.19
1.20

50
10
1.00
1.00
1.05

30
30
30
30
30
30

2.0
2.2
2.8
1.8
1.4
2.5

ICL8212
TYP
MAX
110
20
1.15
1.145
1.165
-0.5

p.A
p.A
V
V
V
mV

30
30
30
30
30
30
+200

1.0

1.0

mV

250

100
5

250

10
1
0.17

1
0.4

7.0

12

0.17
4

15
0.1
-0.1
-15

UNITS

250
40
1.19
1.19
1.20

10

= 1.0V
= 1.3V
=1.0V
= 1.3V
= 1.0V
= 1.3V

(Note 3 & 4) VTH = 1.0V
VOUT = 5V
VTH = 1.3V
--{)5°C:5 TA :5125°C VTH = 1.0V
V+ - 10V VTH - 1.OV
VHYST = V-

MIN

+200

100
5
VTH
VTH
VTH
VTH
VTH
VTH

MAX

V
V
V
V
V
V
ppm/oC

2.0
2.2
2.8
1.8
1.4
2.5

+25°C

o to +70°C

IlHYS

10
50
0.98
0.98
1.00

lOUT - 4 mA VOUT - 2V
IHYST = 7p.A VHYST = 3V

;

Hysteresis Leakage Current

MIN

-21

15
12

35

-0.1

-0.2
-15

0.4
mA

-21

nA
nA
p.A
p.A
p.A
p.A
V
V

0,1

mA
mA
p.A

-0.2

V
p.A

NOTE 3: The maximum output current of the ICL8211 is limited by design to 15ma under any operating conditions. The output voltage maybe
sustained at any voltage up to +30 as long as the maximum power dissipation of the device is not exceeded.
NOTE 4: The maximum output current of the ICL8212 is not defined, and systems using the ICL8212 must therefore ensure that the output
current does not exceed 30ma and that the maximum power dissipation of the device is not exceeded.

5-199

.O~OlL

IC.L.8211/IC.L8212
TYPICAL OPERATING CHARACTERISTICS

H·YSTERESIS
OUTPUT SATURATION CURRENT
AS A FUNCTION OF TEMPERATURE

THRESHOLD INPUT CURRENT AS A
FUNCTION OF THRESHOLD VOLTAGE

~

10,000
TA 25'C
V' 10V
1,000

-

V'= 5V
VTli ":' 1.2V

Z-5

-1l:LSJ11

100

0

I-

~r IcLs21 ~- -,

w

a:
a:

Characteristics
common 10 bolh
the ICL8211 and
Ihe ICL8212

='

--- -

4,(~~ j.5V Jith I
,respect to V+ supply)

I-

::>-20

5

it

1/

VHY'S

::>-10

o

0-25

I/)

~-30
a:

I
10
0,0 1,1 1:151.2 2.0 3.0 6.0 8.010.0
THRESHOLD VOLTAGE - VTH
(IRREGULAR SCALE)

r--

ICLr11 I'ICLr12

r--

w

Iii
~

-40 -20

0 +20 +40 +60 +80.
TEMPERATURE 'C

Characteristics ICL8211
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

SUPPLY CURRENT AS A
FUNCTION OF THRESHOLD VOLTAGE

150

r- r---.

= 0.9V,i±
1125 ~VTH
TA=d5'C I
I
15100
OUTPUTS lPEN CIRCUIT
I-

.a

~

75
50

~

75

o
....

50

.

ICLt211

i:::>

1/)25

o

10
20
SUPPLY VOLTAGE

I

I

o

TA=25'C
V+ =5V

'

-5

Va = 0.5V
VHYS = V' - 0.25V

ICLf211

I I
HYSTERESIS

I-J

OU+P~ ~ ~UTPUT

I
I H
I
I

J

11-8~V

a:

13
I-

-15~

~

-20 0

II>

u;

::!
-30~

-25

1.12 1.13 1.14 1.15 1.16 1.17 1.18
THRESHOLD VOLTAGE

~

OUTPUT SATURATION CURRENT AS
A FUNCTION OF TEMPERATURE

50

~

25

IV-

~ 251--t-~,-~-t---t--t
I/)

-55 -25

1.0 1.1 1.15 1.2 2.0 4.0
THRESHOLD VOLTAGE - VTH
(IRREGULAR SCALE)

I-

15
a:
!5o

7

r

,/

1.18

~ 1.15 ~.-4''-+-I-~'''-+--t
9 1.14 I - - t - - t - r r - - t - - - t - - t

t-lol= ~~a~ va! 1V I I I I
Cl1.17 t-IH[S 117iA, VHYS = (V' -2) V

w

~

OUTPU~

Q

....

~1.15

a:

!3a:

~

JJ

gl.16

o

!-'"

j!: 1.13

. / f'HYS
OUTPU""-

,.!,!~.

.l'3'ft~

1.13
-55 -25 +5 +35 +65 +95 +125
TEMPERATURE' C

OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

1

0

.......

r~

w

~

-10

VT = 1.144V

I-

JlllL

~ -20

~11.18VI

5 -25


0-15

........... r-...

2 3 45
10 20304050100
SUPPLY VOLTAGE

HYSTERESIS OUTPUT CURRENT
AS A FUNCTION OF
. HYSTERESIS OUTPUT VOLTAGE
~ -5

I-

VjL

V" L

j!:1.14

ICJ211

---

+5 -1-35 +65 +95 +125
TEMPERATURE' C

THRESHOLD VOLTAGE
TO TURN OUTPUTS "JUST ON"
AS A FUNCTION OF SUPPLY VOLTAGE

~

I -

~-t~~~t--r-~~

Q.

I-

- 10

~ 75~-t-+-1--r-t--t

o

THRESHOLD VOLTAGE
TO TURN OUTPUTS "JUST ON"
AS A FUNCTION OF TEMPERATURE

~
15a:

rT:=+==t==+:::T"l

,.:. 100

::>

0.0

30

OUTPUT SATURATION CURRENTS
AS A FUNCTION OF
THRESHOLD VOLTAGE
12

,L82J1-

I/)

'VTH '" \.3V

150

~ 125
Z

::!a:
::>

t.

I

CIRCUIT

• 100

a:
a:

TA= 25'C
V'=5V

~OUTPUTS OPEN

SUPPLY CURRENT AS A FUNCTION
OF TEMPERATURE

~ -10.00

-1.00
-0.10
-0.10
HYSTERESIS OUTPUT VOLTAGE

5·200

ICL8211/ICL8212
TYPICAL OPERATING CHARACTERISTICS
Characteristics ICL8212

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

SUPPLY CURRENT AS A
FUNCTION OF THRESHOLD VOLTAGE
150

150

< 125
.;;
!zw 100
a::
~

o

~

00-

~

75

TA

~

:.

-

... 100

1 - - - ICLr21- -

~ 75

I

'VTH

I

50
25

1.3V

I

zw

t--

B

ICJ212

..J

I I

II)

~ 25

a:: 75
a::

:::l

0

>- 50

..J

00:::l

0
-55 -25

0.0 1.0 1.1 1.15 1.2 2.0 4.0
THRESHOLD VOLTAGE - VTH
(IRREGULAR SCALE)

THRESHOLD VOLTAGE
TO TURN OUTPUTS "JUST ON"
AS A FUNCTION OF TEMPERATURE
1.17
w

TA
V'

r-

~ 25
~

0

t

I

~1.16 r -

IHYS = -7p.A, VHYS

>

ffi1.15

a::

v

~

!

g.

~

0.6 r-....,-"'T-~=_..,.-., 30
~05
~

L

9
01.15

~OTH

l:

'1

r-

L82

w

r-

~1.14 TA

...

40 r-:!""'"~~T'T1IT"""T'/M1iT1

~30~++tr-rtrtH-f-f-H~

~

OUTPttE
HYSTERESIS
..l.
25° C OUTPUT
I
I

:~~; : ~;:~, V~HUyTS =: 1(~~ _ 2) V-

1.13

+5 +35 +65 +95 +125
TEMPERATURE °c

OUTPUT CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

..

~

II)

V

1.14
-55 -25

ICL8212
~ 1.17

gl.16

/V

l:

1.14 1.15 1.16 1.17 1.18 1.19
THRESHOLD VOLTAGE

~

,,/'

o

i=

1.18

;=

+5 +35 +65 +95 +125
TEMPERATURE °c

THRESHOLD VOLTAGE
TO TURN OUTPUTS "JUST ON"
AS A FUNCTION OF SUPPLY VOLTAGE

I

5V
10 = 1 ma, Vo = SV

c
..J

OUTPUT SATURATION VOLTAGE
AND CURRENT AS A
FUNCTION OF TEMPERATURE

25

II)

30

OUTPUT SATURATION CURRENTS
AS A FUNCTION OF
THRESHOLD VOLTAGE

V' ~5V
OUTPUTS OPEN CIRCUIT

.!..

zw

II

0-

150

<
.:;; 125
.:. 100

/
I

>- 50

VTH - O.9V

/

10
20
SUPPLY VOLTAGE

TA 25°C
I
I
I
V' ~ 5V
OUTPUj OPEN CI~Tr-=

<
.3:125

25°C

r-OUTP~TS 0tEN f'RCU'T-

SUPPLY CURRENT AS A FUNCTION
OF TEMPERATURE

1

2 345
10 20304050 100
SUPPLY VOLTAGE

HYSTERESIS OUTPUT CURRENT
AS A FUNCTION OF
HYSTERESIS OUTPUT VOLTAGE

1:;:- -50 I"[~~±~~~;'E~~~A~~r~~~
z

a

zw

il!-10 1:::~-+--;-""!ifFHt-tt-H--t
a::
Be15 1-H-t-j--j--tlr-t-t-rt-tt-t-r-1

C2 0.3

0

§ 20 ~++thr.-t--+ttt-t-Htt-t

~-20t-trrt~-*~t-+-iTtT-;

~ 0.2

·10 a:

i!i 0.4 h''-I--+'--'+--b-Lt--i 20
;::

z

~

~

~

~ 0.1

§

tn

0
-55 -25

0

~~

I-

+5 +35 +65 +95 +125 :.I
TEMPERATUREoC
0

a::

o
~

~ 10~tj~-r-+ttt-t-titt-t

o

0.1

~-25

o

~-30t-tr~-t-tH-t-~i++t-i

ffi -35 t-tr~-t-ttt
Iii -40 ........................................................
1.0
10.0 30.0 100.0
OUTPUT VOLTAGE

CIRCUIT DESCRIPTION
The ICL8211 and ICL8212 use standard linear bipolar
integrated circuit technology with high value thin film
resistors which define extremely low value currents.
Components 01 th ru 010 and Rl, R2 and R3 set up an
accurate voltage reference of 1.15 volts. This reference
voltage is close to the value of the bandgap voltage for silicon
and is highly stable with respect to both temperature and

5-201

;;: -10.00
-1.00
-G.l0
-G.Ol
HYSTERESIS OUTPUT VOLTAGE

supply voltage. The deviation from the bandgap voltage is
necessary due to the negative temperature coefficient of the
thin film resistors (-5000 ppm per °CI.
Components 02 thru 09 and R2 make up a constant current
source; 02 and 03 are identical and form a current mirror. 08
has 7 times the emitter area of Og, and due to the current
mirror, the collector currents of 08 and Ogare forced to be
equal and it can be shown that the collector current in 08 and

ICL8211/ICL8212
09 is

1. GENERAl.: INFORMATION
Ie (Oa or 09) = _1_ X

R2

THRESHOLD INPUT CONSIDERATIONS

!I.. in 7

Although any voltage between -5V and V+ may be applied to
the THRESHOLD terminal, it is recommended that the
THRESHOLD voltage does not exceed about +6 volts since
above that voltage the threshold input current increases
sharply. Also, prolonged operation above this voltage will
lead to degradation of device characteristics.

q

or approximately 1J.!A at 25°C
Where k = Soltzman's constant
q = charge on an electron
and T = absolute temperature in 0 K

Transistors 05, 06, and 07 assure th.at the VeE of 03,04, and
09 remain constant with supply voltage va~iations. This
ensures a constant current supply free from variations.

INPUT
VOLTAGE
(RECDMMENDED RANGE
+5 VOLTS)

V·
-j;

(V' MUST
EQUAL DR
EXCEED 1.8
VDLTS)

TO.

VTH o - - - j - - j

The base current of 01 prqvides sufficient start up current for
the constant current source; there being two stable states for
this type of circuit - either ON as defined above, or OFF if no
start up current is provided. Leakage current in the
transistors is not sufficient in itself to guarantee reliable
startup.

I

Vo

+-------4---0 VHYST

L02

04 is matched to 03 and 02; 010 is matched to 09. Thus the Ie
and VBE of 010 are identical to thai of 09 or 08. To generate
the bandgap voltage, it is necessary to sum a voltage equal to
the base emitter voltage of 09 to a voltage proportional to the
difference of the base emitter voltages of two transistors 08
and 09 operating at two current densitieS.

INPUT
VOLTAGE

VTH

which provides

R3

R2

R3 X kT
q

R2

in 7

I

VOl

' ':ffvffvft". o~~.
v'

Thus 1.15 = VBE (09 or 010) +

RL1

o~

rI
rI
rll~L8211/12AND
-.J L---J L---..J ~UTPUT

I I

I I

I I ICL8211 ONLY

r-----l r
L.J

r--1

V -,
OV
L.J

L.J

DUTPUT
ICL8212DNLY

= 12 (approx.l

Figure 1: Voltage Level Detection

The total supply current consumed by the voltage reference
section is approximately 6J.!A at room temperature. A voltage
at the THRESHOLD input is compared to the reference 1.15
volts by the comparator consisting of transistors 011 thru
017. The outputs from the comparator are limited to two
diode drops less than V+ or approximately 1.1 volts. Thus the
base current into the hysteresis outP!Jt transistor is limited to
about 500nA and the collector current of 019 to. 100J.!A.
In the case of the ICL8211, 021 is proportioned to have 70
times the emitter area of 020 thereby limiting the output
current to approximaely 7mA, whereas for the ICL8212
almost all the collector current of 019 is available for base
drive to 021, resulting in a maximum available collector
current of the order of 30mA.lt is advisable to externally limit
this current to 25mA or less.

The outputs change states with an input THRESHOLD
voltage of approximately 1.15 volts. Input and output
waveforms are shown in Figure 1 for a Simple 1.15 volt level
detector.
The HYSTERESIS output is a low current output and is
intended primarily for input threshold voltage hysteresis
applications. If this output is used for other applications it is
suggested that output currents be limited to 10J.!A or less.
The regular OUTPUT's from either the ICL8211 or.ICL8212
may be used to drive most of the common logic families such
as TTL or C-MOS using a single pullup resistor. There is a
guaranteed TTL fanout of 2 for the ICL8211 and 4 for the
ICL8212.
V·

VTH

APPLICATIONS
The ICL8211 and ICL8212 are similar in many respects,
especially with regard' to the setup o.f the input trip
conditions and hysteresis circuitry. The folloWing
discussion describes both devices, and where differences
occur they are clearly noted.

5·202

C·MOS OR
TTL GATES

Figure 2: Output Logic Interface

ICL8211/1CL8212
A principal application of the ICL8211 is voltage level
detection, and for that reason the OUTPUT current has been
limited to typically 7mA to permit direct drive of an LED
connected to the positive supply without a series current
limiting resistor.

INPUT
VOLTAGE

On the other hand the ICL8212 is intended for applications
such as programmable zener references, and voltage
regulators where outpui currents well in excess of 7mA are
desirable. Therefore, the output of the ICL8212 is not current
limited, and if the output is used to drive an LED, a series
current limiting resistor must be used.

a) Range of input voltage greater than +1.15 volts.
Input voltage to change the output states
= (R1 + R2)

In most applications an input resistor divider network may be
used to generate the 1.15V required for VTH. For -high
accuracy, currents as large as 50MA may be used, however
for those applications where current limiting may be
desirable, (such as when operating from a battery) currents
as low as 6MA may be considered without a great loss of
accuracy. 6MA represents a practical minimum, since it is
about this level where the device's own input current
becomes a significant percentage of that flowing in the
divider network.

X 1.15 volts
MAY BE ANY STABLE VOLTAGE
REFERENCE GREATER
VAEF (+ve) THAN 1.15 VOLTS

INPUT

b) Range of input voltage less than +1.15 volts.
I nput voltage to change the output states
IR1 + R2) X 1.15
R2 VREF
R1

. v-~~------------~

R1

Figure 4: Input Resistor Network Setup Procedures
For supply voltage level detection applications the input
reSistor network is connected across the supply terminals as
shown in Figure 5.

Figure 3: Input Resistor Network Considerations

r-------------~--~v"

Case 1. High accuracy required, current in resistor network
unimportant Set I = 50MA for VTH = 1.15 volts :. R1 20k ohms.

INPUT VOLTAGE
OR SUPPLY VOLTAGE

Case 2. Good accuracy required, current in resistor network
important Set I = 7.5MA forVTH = 1.15 volts:· R1150k ohms.

L------------+~Vo

Figure 5: Combined Input and Supply Voltages
Conditions for correct operation of OUTPUT (terminal #4).
1. ICL8211
1.8V::: V+::: 30V
2. ICL8212
0::: V+::: 30V

SETUP PROCEDURES FOR VOLTAGE
LEVEL DETECTION

Case 2. Use of the HYSTERESIS function

Case 1. Simple voltage detection - no hysteresis
Unless an input voltage of approximately 1.15 volts is to be
detected, resistor networks will be used to divide or multiply
the unknown voltage to be sensed. Figure 4 shows
procedures on how to set up resistor networks to detect
INPUT VOLTAGES of any magnitude and polarity.

The disadvantage of the simple detection circuits is that
there is a small but finite input range where the outputs are
neither totally 'ON' nor totally 'OFF'. The principle behind
hysteresis is to provide positive feedback to the input trip
point such that there is a voltage difference between the
input voltage necessary to turn the butputs ON and OFF.

5-203

I

ICL8211/1CL8212
The advantage of hysteresis is especially apparent in
electrically noisy environments where simple but positive
voltage detection is required. Hysteresis circuitry, however,
is not limited to applications requiring better noise
performance but may be expanded into highly complex
systems with multiple voltage level detection and memory
applications - refer to specific applications section.
There are two simple methods to apply hysteresis to a circuit
for use in supply voltage level detection. These are shown in
Figure 6.
r-------~-----.~v'

Circuit (a) requires that the full current flowing in the resistor
network be sourced by the HYSTERESIS output whereas for
circuit (b) the current to be sourced by the HYSTERESIS
output will be a function of the ratio of the two trip pOints and
their values. For low values of hysteresis circuit (b) is to be
preferred due to the offset voltage of the hysteresis output
transistor.
A third way to obtain hysteresis (lCL8211 only) is to connect
a resistor between the OUTPUT and the THRESHOLD
terminals thereby reducing the total external resistance
between the THRESHOLD and GROUND when the
OUTPUT is switched on.

3. PRACTICAL APPLICATIONS
a) Low Voltage Battery Indicator

~----------_+~vo

150kn

a) Low trip voltage
VTR1 = CRl

"Ra OPTIONAL

+ R:: X 1.15 + 0.1J volts

Figure 7: Low Voltage Battery Indicator

High trip voltage
VTR2 =

(R1 + R2 + R3)
_ _~_ _ X 1.15 volts
R1

r----------------.~v'

This application is particularly suitable for portable or
remote operated equipment which requires an indication of
a depleted or discharged battery. The quiescent current
taken by the system will be typically 35/LA which will increase
to 7mA when the lamp is turned on. R3 will provide hysteresis
if required.
b) INon-Volatilel Low Voltage Detector
~--------------~~--~v'

Ra
L------------r~VO

RL

b) Low trip voltage
VTR1 = [RORS
(Ro + Rs)

+ Rpl

JX

1

Rp

L------------+......~OUTPUT

X 1.15 volts

High trip voltage
VTR2 =

(Rp

+ Ro)

s

X 1.15 volts

Rp

'" OFF

~

Q,

s
~
o

'" OFF

~

S:l

--rr--

~
o

~
ON

~

0
ON

--,

1----

::
IVTR1

'VTR2

OFF~

9

Figure 8: Low Voltage Detector and Memory

S:2

SUPPLY VOLTAGE

Figure 6: Two alternative voltage. detection circuits employing

hysteresis to provide pairs of well defined trip voltages.

In this application the high trip voltage VTR2 is set to be above
the norma.1 supply voltage range. On power up the initial
condition is A. On momentarily closing switch S1 the
. operating point changes to B and will remain at B until the

5-204

ICL8211/ICL8212
supply voltage drops below VTR1, at which time the output
will revert to condition A. Note that state A is always retained
if the supply voltage is reduced below VTR1 (even to zero
volts) and then raised back to VNOM.
c) (Non-volatile) Power Supply Malfunction Recorder
In many systems a transient or an extended abnormal (or
absence of a) supply voltage will cause a system failure. This
failure may take the form of information lost in a volatile
semiconductor memory stack, a loss of time in a timer or
even possible irreversible damage to components if a supply
voltage exceeds a certain value.
It is, therefore, necessary to be able to detect and store the
fact that an out-ol-operatlng range supply voltage condition
has occurred, even in the case where a supply voltage may
have dropped to zero. Upon power up to the normal
operating voltage this record must have been retained and
easily interrogated. This could be important in the case of a
transient power failure due to a faulty component or
intermittent power supply, open circuit, etc., where direct
observation of the failure is difficult.

the supply voltage that will result in the output of the ICL8211
changing from the ON state to the OFF state. This may be
achieved only by shorting out R3 for values of supply voltage
between V1 and V2.
d) Constant Current Sources
The ICL8212 may be used as a constant current source of
value of approximately 25/lA by connecting the
THRESHOLD terminal to GROUND. Similarly the ICL8211
will provide a 130/lA constant current source. The equivalent
parallel resistance is in the tens of megohms over the supply
voltage range of 2 to 30 volts. These constant current
sources may be used to provide biasing for various circuitry
including differential amplifiers and comparators. See
Typical Operating Characteristics for complete information.

A simple circuit to record an out of range voltage excursion
may be constructed using an ICL8211, an ICL8212 plusa few
resistors. This circuit will operate to 30 volts without
exceeding the maximum ratings of the I.C. 'so The two voltage
limits defining the in range supply voltage may be set to any
value between 2.0 and 30 volts.

I
I

~
~

2S"A (ICL8212)
130"A (ICL8211)

r--------------.~~------------------~~v·

Figure 11: Constant Current Source Applications
e) Zener or Precision Voltage Reference
TA

lWYV'

w
CJ

~ 4

g3
a:

w

Figure 9: Schematic of Recorder

ifi

2

N

OUTPUT ICL8211
ICL8212 DISCONNECTED
I

OUTPUT ICL8212

a

OUTPUT ICL8211
AS PER FIGURE 9

~ 2S'C ill

0,01

....:tIs

~

t-~t~

ICL SOak ~R
8212
VTHt-150k
OUT

jj-t...l.ll.

2

R1

1 'I
+

w

- 5.u F

N

~

I 1111 I Ilil

0.1
1.0
10
SUPPLY CURRENT - I (rna)

100

VNOM

OFF

-

Figure 12: Programmable Zener or Voltage Reference

ON
SUPPLY VOLTAGE

SUPPL Y VOLTAGE

The ICL8212 may be used to simulate a zener diode by
connecting the OUTPUT terminal to the Vz output and using
a resistor network connected to the THRESHOLD terminai
to program the zener voltage
(V zener = (R, + R2) X 1.15 volts),

SUPPL Y VOLTAGE

Figure 10: Output States' of the ICL8211 and ICL8212 as a
Function of the Supply Voltage

Rl
Referring to Figure 9, the ICL8212 is used to detect a voltage,
V2, which is the upper voltage limit to the operating voltage
range. The ICL8211 detects the lower voltage limit of the
operating voltage range, V1. Hysteresis is used with the
ICL8211 so that the output can be stable in either state over
the operating voltage range V1 to V2 by making V3- the upper
trip point of,the ICL8211 much higher in voltage than V2.
The output of the ICL8212 is used to force the output of the
CL8211 into the ON state above V2. Thus there is no value of

5-205

Since there is no internal compensation in the ICL8212it is
necessary to use a large capacitor across the output to
prevent oscillation.
Zener voltages from 2 to 30 volts may be programmed and
typical impedance values between 300/lA and 25mA will
range from 4 to 7n. The knee is sharper and occurs at a
significantly lower current than other similar devices
available.

ICL8211/ICL8212
f) Precision Voltage Regulators
v·o---------'~-

v·o-_------..-~...,

_____
r------

:

R3

I.-"'y"'v"'v-

V·<>-.......- - - - - - -.......~-...,

~

Vour

R2:, R,

x 1.15 VOLTS

r-----R3

Figure 13: Simple Voltage Regulator

,

, L_/V'y"v'

The ICL8212 may be used as the contrallerfor a highly stable
series voltage regulator. The output voltage is simply
programmed, using a resistor divider network Rl and R2.
Two capacitors Cl and C2 are required to ensure stability
since the ICL8212 is uncompensated internally.
This regulator may be used with lower input voltages than
most other commercially available regulators and also
consumes less power for a given output control current than
any commercial regulator. Applications would therefore
include battery operated equipment especially those
operating at low voltages.

Figure 14: High Voltage Dump Circuits

g) Frequency limit detectors
Simple frequency limit detectors providing a GO/NO-GO
output for use with varying amplitude input signals may be
conveniently implemented with the ICL8211/12. In the
application shown, the first ICL8212 is used as a zero
crossing detector. The output circuit consisting of R3, R4 and
C2 results in a slow output positive ramp. The negative range
is much faster than the positive range. R5 and R6 provide
hysteresis so that under all circumstances the secon9
ICL8212 is turned on for sufficienttime to discharge C3. The
time constant of R7 C3 is much greater than R4 C2.
Depending upon the desired output polarities for low and
high input frequencies, either an ICL8211 or an ICL8212 may
be used as the output driver.

f) High supply voltage dump circuit
In many circuit applications it is desirable to remove the
power supp'ly in the case of high voltage overload. For
circuits consuming less than 5mA this may be achieved
using an ICL8211 driving the load directly. For higher load
currents it is necessary to use an external pnp transistor or
darlington pair driven by the dutput of the ICL8211. Resistors
R1 and R2 set up the disconnect voltage and R3 provides
optional voltage hystereSis if so ?esired.

v'o-~--------_~------------------~~r-----------~--'

C,

Ra

INPUT~H-~~-l

L------~~*-~OUTPUT

TIME CONSTANT R3 C, ~ R4 C, os R7 C3
VARY R, FOR OPTION ZERO CROSSING DETECTION
VARY R4 TO SET DETECTION FREQUENCY

INPUT

----j'NDETERMINATE
BELOW 10

-_._i'-----'\------,r--~

1.15V

A

1.15V
B

--cl.-Irt---===="'J.o.H'=--

....

OFF
~

~5
~d
....

-+++-------+1+--

g

ON

r

~
(

10

Figure 15: Frequency Limit Detector

5·206

-

,,
,
FREQUENCY-

ON W

~

~

OFF 0

ICL8211 IICL8212
This circuit is sensitive to supply voltage variations and
should be used with a stabilized power supply. At very low
frequencies the output will switch at the input frequency.
h) Switch bounce filter
Single pole single throw (SPST) switches are less costly and
more available than single pole double throw (SPDT)
switches. SPST switches range from push button and slide
types to calculator keyboards. A major problem with the use
of switches is the mechanical bounce of the elctrical
contacts on closure. Contact bounce times can range from a
fraction of a millisecond to several tens of milliseconds
depending upon the switch type. During this contact bounce
time the switch may make and break contact several times.
The circuit shown in Figure 16 provides a rapid charge up of
C1 to close to the positive supply voltage (V+) on a switch
closure and a corresponding slow discharge of C1 on a
switch break. By proportioning the time constant of R1 C1 to
approximately the manufacturer's bounce time the output as
terminal #4 of the ICL8211/12 will be a single transition of
state per desired switch closure.

RL

For further applications, see A027 "Power Supply Design
using the ICL8211 and ICL8212" by D. Watson.

CUSTOM OPTIONS
The ICL8211/12 have been designed with more on chip
components than are used, in anticipation of more dedicated
high volume system usage. The trigger voltage and
hysteresis resistor network IS Integrated on chip but not
connected. Consult the factory for more information on
custom options.

CHIP TOPOGRAPHY

~ 0.038

SWITCH OUTPU OUTPUT
I L8212
I L
CLOSED
HI
LO
OPEN
LO
HI

1-

(0.965)

----.J
-I

DIE IS PASSIVATED WITH A DEPOSITED OXIDE. BONDING
PAD OXIDE WINDOWS ARE 3.6 x 3.6 MILS SQUARE.

L------------+~~vo

Figure 16: Switch Bounce Filter

j) Low voltage power disconnector
There are some classes of circuits that require the power
supply to be disconnected if the power supply voltage falls
below a certain value. As an example, the National LM199
precision reference has an on chip heater which
malfunctions with supply voltages below 9 volts causing an
excessive device temperature. The ICL8212 may be used to
detect a power supply voltage of 9 volts and turn the power
supply off to the LM199 heater section below that voltage.

Figure 17: Low Voltage Power Supply Disconnect

5-207

ICH8500/A
Ultra Low Bias Current
Operational Amplifier
FEATURES

GENERAL DESCRIPTION

• Input diode protection
• Input bias current less than 0.01 pA at all
operating temperatures
• No frequency compensation required
• Offset voltage null capability
• Short circuit protection
• Low power consumption

The ICM8500 and ICH8500A are hybrid circuits
designed for ultra low input bias current operational
amplifier applications. They are ideally suited for
analog and electrometer applications wherehigh input
resistance and low input current are of prime
importance.
Functionally, they are pin for pin identical to the
popular 741 monolithic amplifier. These amplifiers are
unconditionally stable anq the input offset voltage can
be adjusted to zero with an external20k potentiometer.
The input bias current for the inverting and noninverting inputs is 0.1 pA maximum for the ICH8500,
and 0.01 pA maximum for the ICH8500A and are
constant over the operating temperature range of
-25 0 C to +85 0 C.

APPLICATIONS
•
•
•
•
•
•
•

Femto Ammeter
Electrometers
Long time integrators
Flame detectors
pH meter
Proximity detector
Sample and Hold Circuits

Pin 8 is connected to the case. This permits the
designer to operate the case at any desired potential,
the key to achieving the ultra low input currents
associated with these two amplifiers. Forcing the case
to the same potential as the inputs eliminates current
flow between the case and the input pins, and leakage
currents that may have otherwise existed between any
of the other pins and the inputs are intercepted by the
case.

SCHEMATIC DIAGRAM
v'

ORDERING INFORMATION
ICH

8500A

TV

~L: .

PACKAGE
TV~ TO-99

metal can

.

DEVICE TYPE
INTERSIL HYBRID
CIRCUIT

NON-INVERTING
INPUT

100pF

OFFSET

NULL

12K

PIN CONFIGURATION
1K

1K

[NVE~~~~~
OFFSET
NULL

12K

5-208

2

(outiinedwgTV)

ICH8500/A
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ............................ ±18V
Internal Power Dissipation l11 .••.•••••.••• 500 mW
Differential Voltage ........................ ±0.5V
Storage Temperature ........... -65°C to +150°C
Operating Temperature .......... -25°C to +85°C
Lead Temperature (Soldering 10 sec) ...... 300°C
Output Short Circuit Duration .......... Indefinite

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of thedevicesat
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

Note: 1. Rating applies for ambient temperature to +70°C.

ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified, Vsupp = ±15V)
ICH8500
CHARACTERISTICS

SYMBOL

Input Leakage Current
(Inverting and Non-Inverting)
Input Offset Voltage
Offset Voltage Adjustment Range
Change in Input Offset
Voltage Over Temperature

Output Voltage Swing
Common Mode Voltage Range
Large Signal Voltage Gain
Feedback Capacitance
Long Term Input Offset
Voltage Stability

TYP.

ICH8500A
MAX

MIN

TYP

0.1

hLK

MAX

UNITS

0.01

pA

TEST
CONDITIONS
Case at same
potential as inputs

Vos

50

50

mV

±Vos

±50

±50

mV

20kfl Potentiometer

±5.0
±5.0

mV
mV

+25 to +85°C
-25 to +25°C

dB

±5 volts common
mode voltage

IlVos I

Common Mode Rejection Ratio

MIN

IlT

CMRR

60

75

60

75

±Vo

±11

±11

V

CMVR

±10

±10

V

AVOL

20,000

105

20,000

±3.0

IlVos/ Ilt

-

105

0.1

Cfb

RL 2: 10kfl

0.1

pF

Case guarded

±3.0

mV

At 25°C

Slew Rate

SR

0.5

0.5

V/JJ-s

Input Capacitance

CIN

0.7

0.7

pF

Case guarded

Input Capacitance

CIN

1.5

1.5

pF

Case grounded

RL 2: 2kfl

CIRCUIT NOTES
VOLTAGE OFFSET
NULL CIRCUIT

LOW LEVEL CURRENT MEASURING CIRCUIT

VOLTAGE FOLLOWER

OUTPUT
Vo '" 1 VOLT/pA
'" 10 12 , IJN

CASE
GUARD

NOTE: Adjust input offset voltage to OV ± 10!'V"before measuring leakage.

5·209

.O~OlL

ICH8500/A
TYPICAL PERFORMANCE CURVES

OPEN LOOP VOLTAGE
GAIN vs. FREQUENCY
106

I

"'" '"

10'

~
~

;>;

10 3
10'

10

85

I

no

75

i

r-~

~

.11I

rl VB
-10
+2 SOC';:;; T A

70

I

1

1

•• - • • . .

65

I..IM!"r

~ +85°~-""""

-15
10

100

1k

10k

lOOk

60

1M

8

9

FREQUENCY (Hl)

10

11

12

13

14

15

16

10

8

SUPPLY VOLTAGE (fVI

INPUT OFFSET VOLTAGE
vs. SUPPLY VOLTAGE

~

l'

f.--

;::. I--'
'5 VOLT COMMON
MODE VOL TAGE

,12

13

14

15

16

SUPPLY VOLTAGE I'VI

±POWER SUPPLY REJECTION
RATIO vs. SUPPLY VOLTAGE

OUTPUT VOLTAGE SWING
vs. SUPPLY VOLTAGE
15
T

90~-r~-+--T-!-+-r--r-1
80 ~-r~~=-+~_1

~~

1

--

I

-5

-

80

\tJI\\

~~~

'5

'" '"

COMMON MODE REJECTION
RATIO vs. SUPPLY VOLTAGE

'15

I

VSUpp - '15V
TA ~ +2S"C

10 5

Z

INPUT VOLTAGE RANGE
vs. SUPPLY VOLTAGE

~. ,,'5· C

,l

~~

,0'

10

rT

~

y

~
"
~'v<'

--

708~~~10~~11--1~12--'~3~lL4~1-5-J'6

__~~__~~__~~
10 11
12
13
14 15
16

4~~~

8

SUPPLY VOLTAGE (tV)

±QUIESCENT SUPPLY
CURRENT vs. SUPPLY VOLTAGE

2.0

500

1.5

-.; P--~;;;C: t:::::: V

~

0.5

o

......-:

---

r--

.-

r-- 1-- 1---

-

-

-

14

15

i
8

10

11

12

13

SUPPLY VOLTAGE (±V)

200

g

100

>;

16

"

10

14

15

16

50

E
z

0

40

"~

30

t

\
o

13

60

~5!" \00'"

300

~

12

POWER CONSUMPTION
vs. SUPPLY VOLTAGE

1 !\
:!:

11

SUPPLY VOLTAGE ('VI

400

~"sc;:,oC

10

10

8

INPUT REFERRED
NOISE VOLTAGE

3.0
2.5

o

SUPPLY VOLTAGE (±VI

,
10,0

8

".,
oc

i

~
lk

FREQUENCY (Hz)

5-210

10k

lOOk

20
10

o

i#r
"
~ ~<'

?P
8

~

10

11

~c

","'0

12

13

-:/

r-- f-'--

14

SUPPLY VOLTAGE (±V)

15

16

ICH8500/A
APPLICATIONS
The Pico Ammeter
A very sensitive pico ammeter can be constructed with
the ICH8500. The basic circuit (illustrated in Figure i)
employs the amplifier in the inverting or current
summing mode.

circuit is approximately the product of the feedback
capacitance Cfb times the feedback resistor Rfb. For
instance, the time constant of the circuit in Figure 1 is 1
sec if Cfb = 1 pF. Thus, it takes approximately 5 sec (5
time constants) for the circuit to stabilize to within 1%
of its final outpat voltage after a step function of input
current has been applied. Cfb of less than 0.2 to 0.3 pF
can be achieved with proper circuit layout. A practical
pico ammeter circuit is illustrated in Figure 2.

Care must be taken to eliminate any stray currents
from flowing into the current summing node. This can
be accomplished by forcing all points surrounding the
input to the same potential as the input. In this case the
potential of the input is at virtual ground, or OV,
therefore, the case of the device is grounded to
intercept any stray leakage currents that may
otherwise exist between the ±15V input terminals and
the inverting input summing junctions. Feedback
capacitance' should be kept to a minimum in order to
maximize the response time of the circuit to step
function input currents. The time constant of the

The internal diodes CR1 and CR2 together with
external resistor R1 protect the input stage of the
amplifier from voltage transients. The two diodes
contribute no error currents, since under normal
operating conditions there is no voltage across them.
"Feedback capacitance is the capacitance between the output and
the inverting input terminal of the amplifier.

Afb-l012Q

CURRENT
SOURCE

>-------'"---- OUTPUT
CURRENT/

VI) = -liN Rib

SUMMING
NODE

'" -1 VOL T/pA

Figure 1. Basic Pica Ammeter Circuit

+15V

R,
lMn

INPUT

>------4--..J.,j'Y¥----<>---...,...-------t
~---<>--....- - - - - OUTPUT

CRl

Vo '" -liN x 10 '2 n

=-tVOLT/pA
INTERNAL

DIODES

20HZ

-15V

Figure 2. Pica Ammeter Circuit

5-211

II

ICH8500lA
Sample and Hold Circuit (Figure 3)
The basic principle of this circuit is to rapidly charge a
capacitor CSTO to a voltage equal to an input signal.
The input signal is then electrically disconnected from
the capacitor with the charge still remaining on CSTO.
Since CSTO is in the negative feedback loop of the
operational amplifier, the output voltage of the
amplifier is equal to the voltage across the capacitor.
Ideally, the voltage acrossCSTO will remain constant,
thus the output of the amplifier will also be constant,
however, the voltage across CSTO will decay at a rate
proportional to the current being injected or taken out
of the current summing node of the amplifier. This
current can come from four sources: leakaqe
resistance of CSTO, leakage current due to the solid
state switch SW2, currents-due to high resistance paths
on the circuit fixture, 'and most important, bias current
of the operational amplifier. If the ICH8500A operational amplifier is employed, this bias current is almost
non-existant «0.01 pAl. Note that the voltages on the
source, drain ane! gate of switch SW2 are zero or near
zero when the circuit is in the hold mode. Careful construction will eliminate stray resistance paths and
capacitor resistance can be eliminated if a quality
capacitor is selected. The net result is a quality sample
and hold circuit.

As an example, suppose the leakage current due to all
sources flowing into the current summing node of the
sample and hold circuit is 1OOpA. The rate of change of
the voltage across the 0.011lF storage capacitor is then
10mV/sec. In contrast, if an operational amplifier
which exhibited an input bias current of 1 nA were
employed, the rate of change of the voltage across
CSTO would be 0.1 V/sec. An error build up such as this
could not be tolerated in most applications.
Wave forms illustrating the operation of the sample and
hold circuit are shown in Figure 4.

The Gated Integrator
The circuit in Figure 3 can double as an integrator. In
this application the input voltage is applied to the
integrator input terminal. The time constant of the
circuit is the product of R1 and CSTO. Because of the
low leakage current associated with the ICH8500 and
ICH8500A, very large values of R1 (Up to 1012 ohms)
can be employed; this permits the use of small values of
integrating capaCitor (CSTO) in applications that
require long time delays. Waveforms for the integrator
circuit are illustrated in Figure 5.

RIb CAN BE REDUCED TO 10K
IF CIRCUIT 15 EMPLOYED AS
AN INTEGRATOR

RIb

l00kn
0.01%
INPUT TERMINAL
IF CIRCUIT
IS EMPLOYED
AS AN INTEGRATOR
VIN -" 0 TO :tl0V

CHARGE
STORAGE

CAPACITOR
CSTO

/

O.01-..F
SW2
IT1700
INPUT TERMINAL
IF CIRCUIT
IS EMPLOYED
AS A SAMPLE AND
HOLD CI RCUIT
VIN =OTO tl0V

B

100kU
0.01%

B

>--=-o--~- OUTPUT

1T1700

t15V

V2 ~--"\II5k",n_-o -15V
lQkn

CNULL

_15V

lpF

20k!2
D.C.
ZERO

v,

V'Nr---t::
SAMPLE

1T1700

PULSE OR

CAPACITOR
DISCHARGE
PULSE

+--______________--'

ADJUST CNULL TO ELIMINATE
ANY OUTPUT OFFSET VOLTAGE
DUE TO CHARGE INJECTION
FROM SW2

15kU

-=

-15V

Figure 3. Sample and Hojd Circuit or Integrator Circuit

5-212

.D~DIl

ICH8500/A
WAVEFORMS

"

VIN

'5V
0

r---,

+5V

"

b,

V,

"5V~

bl
-15V

0---,
-15V

I

V3

,IIII

"
h'

OPEN

I

:~SEO

~i-=---­

OUTPUT

"

V3

I,

I

II

II

~SAMPLEW'NDOW

0, --------

CL~
i~SED
I
OPEN

STATE OF
SW1
STATE OF
SW2

OPEN

INPUT TO +16V - - - - - - - - - , \ .
S&H
0 _______
"'
_ _ _ _ _ __

OP. AMP.

I

-15V

I--CLOSED--I
STATE OF
SW2

I

+15V~1
dI

II

II
~-OPEN

CLOSED

V2 -15: ~
I

+15V~1
:
-15V

"

,I

~
' ....--....11

V2

STATE OF
SW1

TIME _ _

+15V

-tSV

d,

,. ...... , . . ", .. ". .

~

--I

TIME ___

OPEN

,1-

!--CLOSED--j
t

OPEN

"'---SAMPLE WINDOW

gl

INTE~~:Z~I~
INPUT

0 -------------lOY

+6V -

o _L..._ _ _

~~

_ _ _ _ _ _ _ __

Figure 5. Gated Integrator Waveforms

Figure 4. Sample and Hold Circuit Waveforms

5·213

ICH851 0/8520/8530
Power Amplifierl
Motor & Actuator Driver

III

KEY FEATURES:

DESCRIPTION:

• pelivers up to 2.7 amps @ 24·28V DC
(30V supplies)
• Protected against inductive kick back with internal
power limiting
• Programmable current limiting (short circuit protection)
• Package is electrically isolated (allowing easy heat
sinking)
• DC gain> 100dB
• 20mA typical standy quiescent current
• Popular 8 pin TO-3 package
• Internal frequency compensation
• Can drive up to 0.1 horsepower motors.

The ICH8510/8520/8530 is a family of hybrid power
amplifiers that have been specifically designed to drive
linear and rotary actuators, electronic valves, push·pull
solenoids. and DC & AC motors.
There are three models available for up to +30V power
supply operation: 2.7 amps @ 24 volt output levels, 2 amps
@ 24V and 1 amp @ 24V. All amplifiers are protected
against shorts to ground by the addition of 2 external pro·
tection resistors. For a devi(Jperating at lower voltages,
see the ICH8515.
The design uses a conventional 741 operational amplifier,
a special monolithic driver chip (BL8063), NPN & PNP
power transistors, and internal frequency compensating
capacitors. The chips are mounted on a beryllium oxide
substrate for optimum heat transfer to the metal package;
this substrate provides electrical isolation between
amplifiers and metal package.
The I.C. power driver chip has built·in regulators to drive
the 741 @ typically ±13V supply voltages.

SCHEMATIC DIAGRAM

v+

7

H~---JIIV\r--+-<>RSC+

6

-=

t----t-::-:---<>VOUT

H-_ _+,,1IV\r-..-<>5 RSC-

ORDERING INFORMATION

PIN CONFIGURATION

ICH8510MKA

I I~ '~:,... ro-,~"

(outline dwg KA)

(TOP VIEW)

Temperature Range
M~Military -55°C to +125"C
I ~Industrial -20"C to +85"C
Basic Part Number
8510 ~ 1A output
8520 ~2A output
8530 ~2. 7A output

v-

5·214

Rsc

ICH851 0/8520/8530
ABSOLUTE MAXIMUM RATINGS @TA=25°C
Supply Voltage .......................................................... ±32V
Power Dissipation, Safe Operating Area ............................. See Curves
Differential Input Voltage ................................................. ±30V
Input Voltage .................................................... ±15V (Note 1)
Peak Output Current ....................................... See Curves (Note 2)
Output Short Circuit Duration (to ground) ................... Continuous (Note 2)
Operating Temperature Range M .............................. -55°C - +125°C
I .............................. -20°C - +85°C
Storage Temperature Range ................................... -65°C to +150°C
Lead Temperature (Soldering, 10 seconds) ............................... 300°C
Max Case Temperature ................................................. 150°C
Note 1: Rating applies to supply voltages of ±15V. For lower supply voltages, VINMAX = VsuPP.
Note 2: Ratings apply as long as package dissipation is not exceeded. Device must be mounted on heat sink, see Figures 8 and

12.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL SPECIFICATIONS TA = +25"C. VSUPP = ±30V (unless otherwise stated)
ICH85101
DESCRIPTION

SYMBOL

CONDITIONS

Input Offset Voltage
Change with
Power Dissipation

~Vos/~Pd

Mid. on Wakefield
403 Heat Sink

Input Offset Voltage

Vos

As, 10 k!!
Pd < 1W

Input Bias Current

IBIAS

As • 10k!!
Pd< 1W

Input Offset Current

los

As" 10 k!!
Pd<1W

Large Signal
Voltage Gain

AVOL

Input Voltage Range

VeMA
CMRA

Common Mode
Rejection Ratio

MIN.

AL -20!!

MAX.

4

-6

ICH85201

ICH8510M
MIN.

MAX.

MIN.

-3

-6

+3

500

250

200

100

ICH8530M

ICH85301

MAX.

MIN.

MAX

2

4

2

+6

ICH8520M
MIN.

MAX.

-3

+6

+3

MIN.

4

-6

+6

-3

MAX.

UNITS

2

mV/W

+3

mV

500

250

500

250

nA

200

100

200

100

nA

100

100

100

100

-10

-10

-10

-10

100

100

dB

Vo '>2/3 Vsupp

As

~

10 k!!

+10

70

+10

70

+10

+10

70

70

-10

+10

70

-10

+10

V

70

dB

Power Supply
Rejection Ratio

PSAR

Rs ~ 10 k!!

77

77

77

77

77

77

dB

Slew Rate

SA

CL-3 pF, Av - 1
AL ~ 10!!

0.5

0.5

0.5

0.5

0.5

0.5

VI'S

±26V

±26V

2.0

2.0

Vo >- 2/3 Vsupp
Output Voltage Swing
Output Current (3)

VOMAX

IMAX

AL

~

20!!

(RL=30n)

(RL~30n)

Av == 10

±·26V

+26V

AL - B!!

1.0

1.0

±25V

±25V

V
A

2,7

2.7

Av = 10
Power Supply
Quiescent Current

10

RL == 'x
V!N '= OV

100

125

125

100

125

100

mA

Note 3: See ~igure #9 if Power Supplies are less than::!:: 30V

ELECTRICAL SPECIFICATIONS (continued) TA = ":55"C. to +125"C.(M) or TA = -20°C. to +85°C.(I)
Input Offset Voltage

Vos

Pd < 1W

Input Bias Current

IBIAS

Pd < 1W

Input Offset Current

los

Large Signal
Voltage Gain

AVOL

~

MV

750

1500

750

nA

500

200

500

200

500

200

+9

90

+10

90

+9

+10

90

90

90

nA
dB

=2/3 Vsupp

Output Voltage Swing

VOMAX

AL

AIIJA

Without
Heat Sink

Thermal Resistance
Junction to Case

RflJC

Thermal Resistance
Junction to Ambient

RHJA
Vsupp

+9

1500

-9

-9

-9

750

+10

-10

-10

1500
90

AL == 200
~Vo

Thermal ReSistance
junction to Ambient

Supply Voltage Range

-10

20n, Av

~

10

+24

Mtd. on Wakefield
403 Heat Sink

±lB

+24

+24

+24

V

±24

:.t24

40

40

40

40

40

40

'C/W

2.5

2.5

2.5

2.5

2.5

2.5

'C/W

(Typ.)
4.0

(Typ.)
4.0

±30

:.t18

±30

5-215

(Typ.)
4.0
±1B

±30

(Typ.)
4.0

(Typ.)
4.0

±18

±30

±1B

±30

(Typ.)
4.0

±18

±30

'C/W
V

ICH851 0/8520/8530
How To Set The Externally Programmable,
Current Limiting Resistors:
The maximum output current is set by the addition of two
external resistors, R sc and Rsc. Because of the current
power limiting circuitry, the maximum output current is
available only when Va is close to either power supply. As
Vo moves away from Vsupp, the maximum output current
decreases in proportion to output voltage. The curve below
shows maximum output current versus output voltage.

~.'I.""'.".
~.,
..
~
~
.

Inductive Load
(Note catch diode)

Capacitive Load
VSl"lpp = :!030V
Tc = 25"C

lOUT (Amp.)
3

Thus the limiting circuitry protects the 'load and avoids
needless damage to the driver during abnormal conditions.
For any 24-28VDC motor/actuator, the Rsc resistors must be
calculated to get proper power delivered to the motor (up to a
maximum of 2.7A) and Vsupp set at ±30V. For lower supply and/
or output voltages. the maximum output current will follow graphs
of Figures 1 and 5,

Rsc "O.4fl, 5W

NOTE ON AMPLIFIER POWER DISSIPATION
The steady state power dissipation lim it is given by

p _
D-

TJ(MAX) - TA
ROJC + ROCH + ROHA

where
TJ =
TA=
ROJc=

} - - - - , ; VOUl

Rsc

Figure 1: Maximum Output Current for Given Rsc
In general, for a given Va, Isc limit, and case temperature
Tc, Rsc can be calculated from the equation below for Va
positive, lOUT positive.
Rsc = (20. 6Vo)* +680-2.2 (Tc-25'C)
ISC(LlMIT)
*For Vo negative, replace this term with 10.3 (Vo-1.2)
For example, for 10 = 1.5A @Vo = 25V and Tc = 25'C,
Rsc = 1195 = 0.797
1500

Maximum junction temperature
Ambient temperature
Thermal resistance from transistor junction to
case of package
RHCH=
Thermal resistance from case to heat sink
RHHA=
Thermal resistance from heat sink to ambient air
And since
TJ =
200'C ior silicon transistors
RHJC '"
2.0C/WATT for a steel bottom TO-3 package with
die attachment to beryllia substrate to header
RHCH=
.045°C/W for 1 mirthi.ckness of Wakefield type 120
thermal joint compound
.09°C/W for 2 mil thickness of type 120
.13° C/W for 3 mil thickness of type 120
.17°C/W for 4 mil thickness for type 120
.21°C/W for 5 mil thickness of type 120
.24°C/W for 6 mil thickness of type 120
ROHA=
The choice of heat sink that a user selects depends
upon the amount of·room available to mount the
heat sink. A sample calculation follows: by
choosing a Wakefield 403 heat sink, with free air,
natural convection (no fan). ROHA '" 2.0°C/W.
Using 4 mil jOint compound,

Therefore for this application, Rsc = .820 (closest standard
value)

PD =

When 0.820 is used, Isc @ Vo = OV will be reduced
to about lA. Except for small changes in the "±VO(max)
limit" area, the effects of changing Rsc on the lOUT vs Your
characteristics can be determined by merely changing the
lOUT scale on Fig. 1 to correspond to the new value. Changes
in Tc move the limit curve bodily up and down.
This internal power limiting circuitry however does not at all
restrict the normal use of the driver. For any normal load, the
static load line will be similar to that shown in Figure 1.
Clearly, as Va decreases, the 10 requirement falls also,
more steeply than the 10 available. For reactive loads, the
dynamic load lines are more complex. Two typical operating
point loci are sketched here:

200'C - T A
2.0' + 0.17".+ 2.0

or@TA=25'C.
200°C -25°C = 42W
4.17"C/W
and @ TA = 125°C.'
200°C -125'C
4.17°C/W

18W

From Fig. 2 the worst case. steady state power dissipation for an
IH8520 (Rsc = 0.620) is about 30W and l8W respectively. Thus
this heat sink is adequate.

5-216

.O~OI1.

ICH851 0/8520/8530
TYPICAL PERFORMANCE CURVES

For ICH 8520, multiply
lCH 8530

lOUT by 0.67

Rsc - 0.6!1

lOUT

3.0A

TeAsE 125°C
Vee
• 30V

For ICH 8510, multiply

lour by 0.33
Rsc 1.2n

2.0

Source Current
only is shown.
Sink Current
is identical with

Reversed Scales.
Derate Linearly
Between Curves
with Temp.

0.'

__~~;-~-r-r~-r-r-r-r-r~-'
-30

·25

-20

-15

·10

10

·5

15

20

25

30V YOUT

-30

-25

·20

·15

·10

10

-5

15

20

25

30

Figure 2: Safe Operating Area; lOUT vs VOUT vs Tc

10K

Voffset(mv)

,.
10
}--~'-'>--1 VOUT

10n

10

15

20

25

30 Pkg. Power Diss. (W)

'Set switch on Vin to gel desired Power Oiss., then

switch to Gnd.10 read offset (VOUT -" 11 x Vollset)

Figure 3: Input Offset Voltage vs Power Dissipation
Input Impedance (Mn)

RI

30t-R_I_O~(~Un~"~'~G=a;=n)~_ _ _ __

20t-R~I_··~'~K~!l_ _ _ _ _ ___

RI

10KJl

1 0 1 - - - - - - -_
RI

=

__..

100Kfl

10Hz

100Hz

1KHz

10KHz

Freq.

Figure 4: Input Impedance vs Gain vs Frequency
Quiescent current Irom •
either +Vee or -Vee (ma)

80

lK

20

25

30

35

·they are approx. equal

Power Supply Voltages
±Vee IVOL TSI

Figure 5: Quiescent Current

YS

5·217

Power Supply Voltage

Your

ICH851 0/8520/8530
TYPICAL PERFORMANCE CURVES, CONTINUED.
YOUT power band width VOUT : ' 67% Vee

Rf
100KHz

10KHz

IK
1KHz
Vin@1

} - - - - - . -...... VOUT

Ion

I.

100

Closed loop gain

Gain

Figure 6: Large Signal Power Band Width

Closed loop Gain

Rf
I.O+-----~

RI

CL .' SOOQpl

99Kn

Cl
10

f

100pl

+-R::fC-:9C:K"'n---.a..~
IK

RI

eo

on

10Hz

Vin@f

100Hz

1KHz

10KHz 100KHz

Ireq(Hz)

Figure 7: Small Signal Frequency Response

'MAX AMPS
Tc=25"C
Rsc "" O.39{l

Max. Output Current (Amps) @ VOUT = ±24Y
IMAX

3.0

=

3.'

[(1200mV)+(2.2 mY)(25°C~Tc)J
As,c.

2.5
2.5
2.0

2.0
1.5
1.5
I.'

1.0

0.5

0.5

'--t--+--+---+--+-+-<~ ± Vee Volts

w55 ·25

+25

+50

+75 +100 +125
Case Temp. eTc) (0 C)

±S

Figure 8: Maximum Output Current
vs. Case Temperature

:tID

:t15

±20·

±25

:!:30

Figure 9: Maximum Output Current
vs. VSUPP

5-218

.
ICH851 0/8520/8530
BRIEF APPLICATION NOTES
The maximum input voltage range, for Vsupp <±15V, is substantially less than the available output voltage swing.
Thus non-inverting amplifiers, as in Figure 10, should
always be set up with a gain greater than about 2.5, (with
±30V supplies), so that the full output swing is available
without hazard to the input. At first sight, it would seem
that no restrictions would apply to inverting amplifiers,
since the inputs are virtual ground and ground. However,
under fault (output short-circuited) or high slew
conditions. the input can be substantially removed from
ground. Thus for inverting amplifiers with gains less than
about 5, some protection should be provided at this input.
A suitable resistor from the input to ground will provide
protection, but also increases the effect of input offset
voltage at the output. A pair of diodes, as shown in Figure
12, has no effect on normal operation, but gives excellent
protection.

Power dissipation is another important parameter to
consider. The current protection circuit protects the
device against short circuits to ground, (but only for
transients to the opposite supply) provided the device has
adequate heat sink. A curve of power dissipation vs Vo
under short circuit conditions is given in Figure 12. The
limiting circuit is more closely dependent on case
temperature than (output transistor) junction
temperatures. Although these operating conditions are
unlikely to be attained in actual use, they do represent the
limiting case a heat sink must cope with. For fully safe
design, the anticipated range of Vo values that could
occur, (steady state, including faults) should be examined
for the highest power dissipation, and the device provided
with a heat sink that will keep the junction temperature
below 200°C and the case temperature below 150°C with
the worst case ambient temperature expected.

'1"

I

V'N

Source direction shown

Ri

Pdiss

-- -.
.--'

For sink, reverse VOUT s.:.a~r---- --+-_40_W_ _ .-- TA

Av '-' RHR!

/
............. -;ranslenls only

RI

30

'---... .......

20

,/

10

/,/

Figure 10:
Non-Inverting Amplifier

'Vou, 30V

Figure 11:
Inverting Amplifier

25V

20V

15V

10V

5V

25"C

0

5V

10V

15V

20V

25V

30V . Va"

Figure 12: Power Dissipation under Short Circuit Conditions

TYPICAL APPLICATIONS
II. Obtaining Up To 5 Amps Output Current Capability By
Paralleling Amplifiers

I. Actuator Driving Circuit (24-28 VDC rated)

10.

9.

130V

t

30V

01

"

Actuator

/Pfston
VIN

V'N

VOUT

10K

"

Figure 13: Power Amp Driving Actuator

The gain of the circuit is set to +10, so a V ,N = +2.4V will
produce a +24V output (and deliver up to 2.7 amps output
current). To reverse the piston travel, invert V'N to -2.4V and
VOUT will go to -24V. Diodes 01 and 02 absorb the inductive
kick of the motor during transients (turn-on or turn-off); their
breakdown should exceed 60V.

Figure 14: Paralleling Power Amps for Increased Current
Capability
This paralleling procedure can be repeated to get any desired
output current. However, care must be taken to provide sufficient load to avoid the amplifiers pulling against each other.

5-219

III

III

ICH851 0/8520/8530
III. Drlvl",g A 48VDC Motor
9K

+30Y

!Imax
48VDC Motor

Overcurrent ~rotection
Circuit

--------l

AVIN - -+2.4V
will deliver output
ot 48V

I

I

I

aero .. motor

I
I
I
I
I
I
I
I

1K

I

}----<~-+--1Lr--_-_·_-_.-1 ______

I

J

*For current protecllon R1 '" O.7Y

Imax
+30Y

Figure 15: Power Amp Driving 48 VDC Motor
IV. Precise Rate Control of an Electronic Valve
; There are two methods to get very fine control of the opening
of an orifice driven by an electronic valve.
1. Keep the voltage constant, i.e., 24VDC or 12VDC,
and vary the time the voltage is applied, i.e., if it
takes five seconds to completely open an orifice
at 24VDC, then applying 24V for only 2'/2 seconds
opens it only 50%.

2. Simply vary the DC driving voltage to valve. Most valves
obtain full opening as an inverse of applied voltage, i.e.,
valves open 100% in five seconds at 24VDCand in 10
seconds at 12VDC.
A circuit to perlorm the second method is shown below;
the advantage of this is that digit switches can precisely
set driving voltage to 0.2% accuracy (8-bit DAC), thereby
controlling the rate at which the valve opens.

II
.
..

10K

+5V ref

electronic valve

Figure 16: Digitally Controlled Electronic Value
V. The circuit presented in Fig. 16 is also an excellent way to
get a precise power supply voltage; in fact, it is possible to

build a precision variable power supply using a BCD coded
DAC with BCD Thurnbwheel switches.

4K
... 15V

I

+30V-- +35V
unregulated input
lIof bits depends
upon desired accuracy
~F\",/\,~~

+5V ref.

digit switChes

1

-30V--3SV unregulated input

. (4K + 1K) x digital' # set bV Sws. and can deliver up to 3 amps.

VOUT =.:!::5V

~1K-

Figure 17: Digitaliy Programmable Power Supply

5·220

20

21

22

1

1

1

1
0
0
1
1
Etc.

1
1
1
0
0

1
0
0
0
0

23
1

1
0
0

24
1
1
1
1
0
0

25
1
1
0
0
0
0

26
1
1
0
0
0

0

27

o BIT

1

1
0
1
0
1
0

1
1
1
0
0

YOU!
+25VDC
-25VDC
+15VDC
-15VDC
+0.098VDC
-0.098VDC

The power supply can be set to ±.0.1VDC.

IIlD~DIL

ICH851 0/8520/8530
VI.

processor (local) or C.P.U.program the D/A converter.
Then total, pre-programmable, electronic control of an
actuator, electronic valve, motor, etc., is obtained. This
would be used in conjunction with a transducer/multiplex
system for electronic monitoring and control of any electromechanical· function.

There is great power available in the sUb-systems shown in
IV and V; there the 0/ A converter is shown being set
manually (via digitswitches) to get a precise analog output
(binary # x full scale voltage), then the driver amplifier
multiplies this voltage to produce the final output voltage. It
seems obvious that the next logical step is to let a micro-

MUX = INTERSIL IH5060 (1/16) or IH5070 (2/16)
S/H ISAMPLE & HOLD) = INTERSIL IH5111
DIA CONVERTER = INTERSIL 7520 or INTERSIL 7105
POWER AMP = IH8510 11 AMP) or IH8520 12 AMP) or
IH8530 (2.7 AMP)
AID CONVERTER = ICL805217103 or ICL8052/7104
J1 COMPUTER = IM6100 family:

ELECTRONIC CONTROL SYSTEM:

TO AID STROBE eNTRL

____________________________________________________
T_O_D_IA_C_O_NV_E_RT_E_R___________________________________

~

1:.1

HEAT SINK INFORMATION
Heat sinks are available from Intersi!. Order part number 290305 1$10.00 ea.l with a ROHA = 1.3°C/watt. A convenient

mating connector is also available. Order part number 290306 1$4.5'0 ea.).

NOTE: This product contains 8eryllia. If ~sed in an application where the package integrity may be breached and the internal parts crushed or
machined, avoid inhalation of the dust.

APPLICATION NOTES
For Futher Applications Assistance, See:
A021 "Power D/A Converters Using The ICH8510/20/30," by Dick Wilenken
A026 "DC Servo Motor Systems Using The ICH8510/20/30," by Ken McAllister
A029 "Power Op Amp Heat Sink Kit." by Skip Osgood

5-221

II

ICH8515
Power Amplifier
Motor & Actuator Driver
KEY FEATURES:

DESCRIPTION:

• Delivers up to 1.5 amps @ +12VDC (±15VDC
supplies)
• Protected against inductive kick back by internal
power limiting
• Programmable current limiting (short circuit
protection)
• Package is electrically isolated (allowing easy heat
sinking)
• DC gain> 100dB
• Popular 8 pin TO-3 package
• Internal frequency compensation
• Can drive up to 0.033 horsepower motors
• Pin equivalent to ICH8510/20/30 family

The ICH8515 is a hybrid power amplifier specifically
designed to drive linear and rotary actuators, electronic
valves, push'pull solenoids, and DC & AC motors.
The design uses a conventional 741 operational amplifier, a
special monolithic driver chip (BL80631, NPN & PNP power
transistors, and an internal frequency compensating
capacitor. The chips are mounted on a beryllium oxide
substrate, for optimum heat transfer to the metal package;
this substrate provides electrical isolation between
the amplifier and the metal package.
The 8515 has special SOA (safe operating areal circuitry
which allows it to withstand a direct short to ground or to
either supply indefinitely. It has been designed to operate
with ±12 or ±15VDC supplies and will deliver typically .1.5
to1.8A @13Vout using +15V supplies.
Internal frequency compensation provides stability down to
unity gain (either inverting or noninverting) even when using
inductive loads.

SCHEMATIC DIAGRAMr-------,_ _ _--.-_ _

~--t__-______1>-----r___ov·

7
Ho---.....J'W'\r-+-oRSC'

6

-=

~-'---~---oVOUT

r....__-+"1/V'V-~5 RSC

PIN CONFIGURATION (OUTLINE DWG. KA)

ORDERING INFORMATION

(TOP VIEW)

DEVICE
ICH8515MKA
ICH85151KA

TEMPERATURE
-55°C to +125°C
- 20°C to + 85°C

OUTPUT
1.5A
1.25A

v-

5·222

Rsc

ICH8515
ABSOLUTE MAXIMUM RATINGS @ TA

= 2S0C

Supply Voltage ................................................. , ........ ±lSV
Power Dissipation, Safe Operating Area ............................. See Curves
Differential Input Voltage ................................................. ±30V
Input Voltage .................................................... ±lSV (Note 1)
Peak Output Current ....................................... See Curves (Note 2)
Output Short Circuit Duration (to ground) ................... Continuous (Note 2)
Operating Temperature Range M .............................. -SsoC - +12SoC
I .............................. -20°C - +SsoC
Storage Temperature Range ................................... -6SoC to +lS0°C
Lead Temperature (Soldering, 10 seconds) ............................... 300°C
Max Case Temperature ................................................. lS0°C
Note 1: Rating applies to supply voltages of ±15V. For lower supply voltages, V,NMAX = Vsupp.
Note 2: Rating applies as long as package dissipation is not exceeded for heat sink attached.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS TA

+2S'C. Vsupp = ::':lSV (unless otherwise stated)

=

ICH85151
MIN.

TYP.

ICH8515M

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

Input Offset Voltage
Change with
Power Dissipation

~Vos/~Pd

Mtd. on Wakefield
403 Heat Sink

Input Offset Voltage

Vos

Rs,,; 10kH, Pd < lW

Input Bias Current

ISlAS

Rs,,; 10kH, Pd < lW

SOO

2S0

nA

Input Offset Current

los

Rs,,; 10kH, Pd < lW

200

100

nA

Large Signal Voltage Gain

AVOL

RL = lOn,
Vo > 2/3 Vsupp

MAX.

TYP.

MAX.

UNITS

2

mV/W

3

mV

4

-6

1

6

-3

100

0.7

dB

100

-10

-10

Input Voltage Range

VCMR

Common Mode
Rejection Ratio

CMRR

Rs

10kn

70

70

dB

Power Supply
Rejection Ratio

PSRR

Rs = 10kn

77.

77

dB

Slew Rate

SR

CL
RL
Vo

=
=

05

O.S

V/J1.s

=

30pF, Av = 1,
10n
'3 2/3 Vsupp

Output Voltage Swing

VOMAX

RL

=

lOn, Av

Output Current

IMAX

RL

=

SH, Av = 10

Power Supply
Quiescent Current

10

RL =

ex,

=

Input Offset Voltage

Vos

Pdo-

""""

1

1

-~

'\

GATING OUTPUT

~

A

'"

~l

LEl
STORE

RESET 14

ORDERING INFORMATION
PACKAGE
14·Pin DIP
DICE
EV/Kit"
14·Pin DIP
DICE
EVIKit"

~l

()

"v

L:,.

~

ICM7207A

.

~
v

'C

12

PART
ICM7207

~

+10

~~

MULTIPLEX
OUTPUT

J'

I
I

-;.2 5

Id'i

PIN CONFIGURATION
ORDER NUMBER
ICM7207IPD
ICM7207/D
ICM7207EVIKit
ICM7207AIPD
ICM7207AID
ICM7207AEVIKit

Temperature Range on packaged parts is - 20'C to + 85'C
'These EV/Kits contain just the IC and the corresponding crystal. The ICM7207A is
also used in the 4V,-Digit CounterlDriver kits, the ICM7224 EV/Kit, ICM7225
EV/Kit, and ICM7236 EV/Kit, which include severallCs, a crystal, PC board, and
some passive components.

6-3

N/CC~PRST
snjC

2

N/CC

3

GROUNOC

4

OSCOUTL

5

OSCINL

6

9

N/CC

7

8 PN/C

13 PGATINGOUT

12 PMUXOUT
leM 7207

IAI

11
10

b

RANGE CONTROL

pv+
PN/C

(outline dwg PO)

OJ

ICM7207/A
I

ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings refer to values
which if \ exceeded may permanently
change or destroy the device. Stresses
above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only. and functional operation of the device
at these or any other conditions above
those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods· may affect
device reliability.

Supply Voltage ........................................................ 6.0V
Input Voltages ........................... Equal to or less than supply voltage
Output Voltages (7207) ..... Not more positive than +6V with respect to GRQUND
(7207A) ................•...................... V+ toVOutput Currents ...................................................... 2SmA
Power Dissipation @ 2SoC Note 1 .................................. , 200mW
Operating Temperature Range " " " , . " " " " . " " " , . , .. ". -20°Cto+8SoC
Storage Temperature Range.,., ... ,',." ... ,", .. ".,., .... -S5°C to +12SoC
NOTE 1: Derate by 2mWfOC above 25°C.

TYPICAL OPERATING CHARACTERISTICS

=

TEST CONDITIONS: fosc 6.5536MHz(7207), 5.24288MHz(7207 A), V+
specified
PARAMETER
Operating Voltage Range
Supply Current
Output on Resistances

SYMBOL
V+
1+
rds(on)

Output Leakage Cu rrents
(Output Resistance
Terminals 12,13,14)
Input Pulldown Current
Input Noise Immunity
Oscillator Frequency Range
Oscillator Stability
Oscillator Feedback
Resistance

= SV, TA = 2SoC, test'circuit unless otherwise

CONDITIONS
-20°C to +8SoC
All outputs open circuit
Output current - SmA
All outputs
All outputs (STORE only)
Output current = SOIJA. 7207A
only
Terminal 11 connected to V+

IOlK
(ROUT)
Ipd

.

.

MIN.
4

TYP.

MAX.
S.S
1000
120

260
SO

SO

UNIT
V
J1-A
0

SO
33K

JJ-A

200

",A
% supply voltage
MHz
ppmN

0

2S
2

10
Note 2
CIN = COUT = 22pF
0.2
1.0
Quartz crystal open circuit
3
MO
Note 3
..
NOTE 2: Dynamic dividers are used 10 the mltlal stages of the divider cham. These dividers have a lower frequency of operation
determined by transistor sizes. threshold voltages and leakage currents.
NOTE 3: The feedback resistor has a' non-linear value determined by the oscillator instantaneous input and output voltage
voltages and. the supply voltage.
tose
fSlAS
rose

OUTPUT SATURATION RESISTANCES
AS A FUNCTION OF SUPPLY VOLTAGE

SUPPLY CURRENT AS A FUNCTION
OF QSCILLATOR FREQUENCY

w

300

TA = 2SoC

250

v+ '" 5V
Medium Qualitv Quartz Crvstals

c:(

~

1/ ;

~

~ 200~~-~-+::r-'12MHz
I

""

~

"\.

~

.,
~~~

COUT'" 10pF

150 f--+-=-+-;
\ C'N'" 10pF
a::
... \"1 6.5 MHz
"
~
.. '\
COUT"'lOpF
.
(,,) 100 -L r3.3MHZ CIN = lOPF---f-

~

a

~~NU! ;2:~F

so

2 MHz
COUT 22pF
CIN '" 22pF

=

~o

i~=

0

100

TA=25C'f
RL=lKn

80~~-~-~-~-4-~

t'-...

I

~
01"

§

.

,

~:---+-=

t--I

40

IOUTPUT 2 ~ _ _

- .

I OUTPUT'.

~

~

I

10
OSCILLATOR FREOUENCV MHz

'20'---'-1-'-1-'---'--""""'--'

l;i

-1tI'

GATING OUT

MUX oUiPUT

i

j

20fc----+---+

0~3-J--~~--5L-~-~

12

SUPPLY VOLTAGE

OSCILLATOR STABILITY AS A FUNCTION
OF SUPPLY VOLTAGE

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
600

~

+0.5

TA = 2S0C

P""r='-"i'-"-+""-"""+---;!~-d

I

50o fos6 = 6.S MHz
COUT = 22pF
CIN" 22pF I

I

> 0.0

400

...
::i

iii

~ -0.5 ~--+-7'''1-~!'I--+--4-~

I
,

300

~

e
j

~

-1.0

200

f--:l-'7<'-t

I

-'.5 b"--'f--I--+--~-4-~
-2.0

'00 ,./

o

'----""--L--'--L---I--:

3

3

6-4 ,

/'

v

i

V

4
5
SUPPLY VOLTAGE '

V

ICM7207/A
Crystal Frequency = 6.5536 (5.24288) MHz

OUTPUT TIMING WAVEFORMS 7207 (7207A)

I

1

1

1.6kHz

or 781ps)

JUl----rrD----nrL

MULT'PLEXQUTPUT

I.

GATING OUTPUT

°1625/J$ (1.28kHz

~

20 or 200 ms
----~2000r2000mS)

.

-

·1

I

----~-10orl00(1000rl000)mS

.----Lj
.----~

provides a 50% duty cycle signal whose period depends upon
whether the RANGE CONTROL terminal isconnectedtoV+ or
GROUND (open circuit).

Referring to the test circuit, the crystal oscil,lator frequency is
divided by 212 to provide both the multiplex frequency and
generate the output pulse widths. The GATING OUTPUT

TEST CIRCUIT
CRYSTAL PARAMETERS
CIN "" COUT "" 22pF

II

ICM7207
f = 6.5536MHz
Rs = 40Q
Cl "" 15 mpF
Co c 3.5 pF

ICM7207A
f = 5.24288MHz

As < 7S,n
Co ="F
eM = 12mpF
CL = 12pF

~v+

DI--------J

+
C'N

SWITCHES 81, ~. 83. 84 OPEN CIRCUIT fOR SUPPLY CURRENT MEASUREMENT.
SWITCH 85 OPEN CIRCUIT FOR SLOW GATING PERIOD.

t SWITCHES 82. 83. 84 and SDk RESISTORS ARE NOT NEEDED WHEN USING THE ICM7207A.

6·5

ICM7207/A
APPLICATION NOTES
OSCILLATOR CONSIDERATIONS

The ICM7207/A uses dynamic frequency counters in the initial divider sections. Dynamic frequency counters are faster
and consume les,s power than static dividers but suffer from
the disadvantage that there is a minimum operating frequency at a given supply voltage.

The oscillator con.sists of a CMOS inverter with a non-linear
resistor connected between the input and output terminals
to provide biasing. Oscillator stabilities of approximately 0.1
ppm per 0.1 volt change are achievable at a supply voltage of
5 volts, using low cost crystals. The crystal specifications are
shown in the TEST CIRCUIT.
It is recommended that the crystal load capacitance (CLl be
no greater than 15pF for a crystal having a series resistance
equal to or less than 750, otherwise the output amplitude of
the oscillator may be too low to drive the divider reliably.
If a very high quality oscillator is desired, it is recommended
that a quartz crystal be used having a tight tuning tolerance
±10 ppm, a low series resistance (less than 25m, a low
,motional capacitance of 5mpF and a load capacitance of
20pF. The fixed capacitor CIN should be 39pF and the
oscillator tuning capacitor should range between approximately 8 and 60pF.
Use of a high quality crystal will result in typical oscillator
stabilities of 0.05 ppm per 0.1 volt change of supply voltage.

QUARTZ CRYSTAL MANUFACTURERS
The following list of possible suppliers is intended to be of
assistance in putting a design into production. It should not
be interpreted as a comprehensive list of suppliers, nor does
it constitute an endorsement by Intersi!.
a) CTS Knights, Sandwich, Illinois, (815) 786-8411
b) Motorola Inc., Franklin Park, IllinoiS (312) 451-1000
c) Sentry Manufacturing Co., Chickasaw, Oklahoma
(405) 224-6780
d) Tyco Filters Division, Phoenix, Arizona (602) 272-7945
e) M-Tron Inds., Yankton, South Dakota (605) 665-9321
f) Saronix, Palo Alto, California (415) 856-6900

FREQUENCY LIMITATIONS

CHIP TOPOGRAPHY

The ICM7207/A uses dynamic frequency counters in the
initial divider sections. Dynamic frequency counters are faster and consume less power than static dividers but suffer
from the disadvantage that there is a minimum operating
frequency at a given supply voltage.
5
4

SUPPLY
VOLTAGE 3

WINDOW

10KHz

100KHz
lMHz
FREQUENCY

10MHz

For example, if instead of 6.5MHz, a 1MHz oscillator is
required, it is recommended that the supply voltage be
reduced to between 2 and 2.5 volts. This may be realized by
using a series resistor in series with the 5V positive supply
line plus a decoupling capacitor. The quartz crystal
parameters, etc., will determine the value of this resistor.
NOTE: Except for the output open drain n-channel transistors no other terminal is permitted to exceed the supply
voltage limits.

Chip may be die attached using conventional

eut9Ctic or epoxy procedures. Wire bonding may be
either aluminum ultrasonic or gold compression.

PRACTICAL FREQUENCY COUNTER
A complete frequency counter using the ICM7207/A together
with the ICM7208 Frequency Counter is described in the
ICM7208 data sheet.
A complete frequency counter using the ICM7207/A together
with the ICM7208 Frequency Counter is descr.ibed in the
ICM7208 data sheet, and app note A015. Other frequency
c::lunters using the ICM7207/A can be constructed using the
ICM7224, ICM7225, and ICM7236, for LCD, LED and VF
displays. The latter are available as EV/Kits also.

6-6

·U~U[b

ICM7208
CMOS
7 Decade Counter

FEATURES

DESCRIPTION

•
•
•
•

Low operating power dissipation < 10mW
Low quiescent power dissipation < SmW
Counts and displays 7 decades
Wide operating supply voltage range
2V'S V+ 'S 6V
Drives directly 7 decade multiplexed common
cathode LED display
Internal store capability
Internal inhibit to counter input
Test speedup point
All terminals protected against static discharge

The ICM7208 is a fully integrated seven decade counterdecoder-driver and is manufactured using Intersil's low
voltage metal gate C-MOS process.

ORDERING INFORMATION

PIN CONFIGURATION

•
•
•
•
•

ORDER
PART NUMBER

TEMPERATURE
RANGE

28 LEAD
PACKAGE

ICM7208IPI

-20 0 C to +85 0 C

PLASTIC

Specifically the ICM7208 provides the following on chip
functions: a 7 decade counter, multiplexer, 7 segment
decoder, digit & segment driver, plus additional logic for
display blanking, reset, input inhibit, and display on/off.
For unit counter applications the only additional
components are a 7 digit common cathode display, 3
resistors and a capacitor to generate the multiplex frequency
reference, and the control switches.
The ICM7208 is intended to operate over a supply voltage of
2 to 6 volts as a medium speed counter, or over a more
restricted voltage range for high frequency applications.
As a frequency counter it is recommended that the ICM7208
be used in conjunction with the ICM7207 Oscillator
Controller, which provides a stable HF oscillator, and output
signal gating.

(OUTLINE DRAWING PI)

ORDER DICE BY FOLLOWING PART NUMBER:
ICM7208D

CHIP TOPOGRAPHY
MUX

ICM720B

SEG.g
TEST 2
SEG.a

SEG.b

MUX 3
0.134"
(3.4mm)

SEG.d

I
SEG.e
GROUND

SEG.c
RST

COUNT ENABLE
COUNT IN

6·7

.D~DI1.

ICM7208
ABSOLUTE MAXIMUM RATINGS

Power Dissipation (Note 1) ....................................•••.......•. 1 W
Supply voltage (Note 2) ..........•.........•.•........•..................... 6V
Output digit drive current INote 3) .... ;................................. lS0mA
Output segment drive current ..........•................................ 30 rnA
Input voltage range (any input terminal) (Note 2) ... Not to exceed the supply voltage
Operating temperature range .............................•..... -20·C to +8S·C
Storage temperature range ..................•................. -5S·C to +12SoC
Lead temperature (soldering, 10 seconds) •...........•...........•...•... 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in Iheoperatlonal sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

TYPICAL OPERATION CHARACTERISTICS
TEST CONDITIONS: (V+ = 5V, T A = 25°C, TEST CIRCUIT, display off, unless otherwise specified)
TYP

MAX

Quiescent Current

10

All controls plus terminal 19 connected to
V+ No multiplex oscillator

30

300

Quiescent Current

10

All control inputs plus terminal 19 connected
to V+ except STORE which is connected

70

350

Operating Supply
Current

1+

Operating Supply

1+

fin = 2MHz
fin :S 2M Hz

PARAMETER

SYMBOL

CONDITIONS

MIN

UNITS

/LA

to GROUND
210

All inputs connected to V+ , RC multiplexer

SOO

osc operating fin < 2SKHz
700

Current
Supply Voltage Range

V+

Digit Driver On Resistance

rDIG

Digit Driver Leakage

IDIG

3.S
4

S.S

V

12

n

SOO

/LA

Current
Segment Driver

rSEG

40

n

On Resistance
Segment Driver

sao

ISLK

/LA

Leakage. Current
Pullup Resistance of RESET
or STORE Inputs

Rp

COUNTER INPUT Resistance

RIN

COUNTER INPUT Hysteresis
Voltage

VHIN

100

400
kn

Terminal 12 either at V+ or GROUND

100
2S

SO

mV

NOTE 1: This value of power dissipation refers to that of the package and will not be obtained under normal operating conditions.
NOTE 2: The supply voltage must be applied before or at the same time as any input voltage. This poses no problems with asingle power supply
system. If a multiple power supply system is used, it is mandatory that the supply for the ICM7208 is switched on before the other
supplies otherwise the device may be permanently damaged.
NOTE 3: The output digit drive current must be limited to 150mA or less under steady state conditions.(Shortterm transients up to 250mA will
not damage the device.1 Therefore, depending upon the LED display and the supply voltage to be Used it may be necessary to include
additional segment series resistors to limit the digit currents.

6·8.

.O~O(6

ICM7208
TYPICAL PERFORMANCE CHARACTERISTICS

SEGMENT OUTPUT CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE

MAXIMUM COUNTER INPUT FREQUENCY
AS A FUNCTION OF SUPPLY VOLTAGE
TA

i

lI:
.§

30.0

~ 250C
1

'E"

7.0

I-

>

zw

6.0

::l

aw

...a:

/

5.0

I::l
0-

l;
lI:
::l

3.0

)(

/

'"

lI:

2.0

o

1.0

a:
a:

::l
U

>
....
0-

0::l

20.0

Z
w

10.0

lI:

"
w

'"

2.0
3.0
4.0
SUPPLY VOLTAGE

5.0

/

5.0

..... /

6.0

1.0

V

V

/
II

15.0

0

I-

/

I
I

J

2.0
3.0
4.0
SUPPLY VOLTAGE

5.0

300

600

~ J50C

L

I

25kHz
RC oscillator 1.5kHz

fiN

=;

'",.

/

150

100
50

./'

IZ

400

::l
U

300

w
a:
a:

/

>
....
0-

0::l

'"

2.0
3.0
4.0
SUPPLY YOLTAGE

a
b

/

T~ ll2~od

V

1.6kHz RC MUX OSC
200
100

I II

I II

lLWEJEJJ~~
MUX INPUT Ti ii

~

o

t.o

TEST CIRCUIT

V

/

6.0

500

V

200

 50pSec.

-COUNTER RESET

EXTERNAL FREQUENCY TO BE MEASURED

COUNTER INPUT

Figure 3: Frequency Counter Input Waveforms

6. Period Counter
For this application, as opposed to the frequency counter,
the gating and the input signal to be measured are reversed
to the frequency counter. The input period is multiplied by
two to produce a single polarity signal 150%duty cycle) equal
to the input period, which is used to gate into the counter the
frequency reference 11 MHz in this casel. Figure 5 shows a

COUNT ENABLE INPUT

block schematic of the input waveform generator. The 1MHz
frequency reference is generated by the ICM7209 Clock
Generator using an 8MHz oscillator frequency and internally
dividing this frequency by 8. Alternatively, a 1MHz signal
could be applied directly to COUNTER INPUT. Waveforms
are shown in Figure 4.

~X2TERNAL FREQUENCYI

_ STORE GENERATED BY THE POSITIVE
EDGE OF THE ENAillINPUT

STORE INPUT

RESET INPUT

=U-RESET

COUNTER INPUT

INPUT IS

~

1MHz

Figure 4: Period Counter Input Waveforms

INPUT

-----------1

I----~------

1------

ENAiiLE INPU)

RESET INPUT

'-----~------- STORE INPUT

1 MHz

1------------ COUNTER INPUT

Figure 5: Period Counter Input Generatpr

6·13

DJ

ICM7211 (LCD)
ICM7212 (LED)
Four Digit CMOS
Display Decoder/Drivers
ICM7211 (LCD) FEATURES

DESCRIPTION

• Four digit non·multiplexed 7 segment LCD display
outputs with backplane driver
• Complete onboard RC oscillator to generate back·
plane Irequency
• Backplane input/output allows simple
synchronization 01 slave·device segment outputs
to a master backplane signal
• ICM7211 devices provide separate Digit Select
inputs to accept multiplexed BCD input (Pinout
and lunctionally compatible with Siliconlx DF411)
• ICM7211M devices provide data and digit select
code input latches controlled by Chip Select in·
puts to provide a direct high speed processor
interlace
• ICM7211 decodes binary hexadecimal;
ICM7211A decodes binary to Code B (0-9, dash, E,
H, L, P, blank)
,

The ICM7211 (LCD) and ICM7212 (LED) devices constitute a
family of non-multiplexed four-digit seven-segment CMOS
display decoder-drivers.
The ICM7211 devices are configured to drive conventional
LCD displays by providing a complete RC oscillator, divider
chain, backplane driver, and 28 segment outputs. These
outputs provide the zero d.c. component signals necessary
for long display life.
The ICM7212 devices are configured to drive common-anode
LED displays, providing 28 current-controlled low leakage
open-drain n-channel outputs_ These devices provide a
BRighTness input, which may be used at normal logic levels
as a display enable, or with a potentiometer as a continuous
disp'lay brightness control.
Both the LCD and LED devices are available with two input
configurations_ The basic devices provide four data-Bit inputs and four Digit Select inputs_ This configuration is
suitable for interfacing with multiplexed BCD or binary output devices, such as the ICM7217, ICM7226 and ICL71C03_
The microprocessor interface (suffix M) devices provide data
input latches and Digit Select code latches under control of
high·speed Chip Select inputs_ These devices simplify the
task of implementing a cost-effective alphanumeric sevensegment display for microprocessor systems, without requiring extensive ROM or CPU time for decoding and display
updating .
The standard devices will provide two different decoder configurations.·The basic device will decode the four bit binary
input into a seven-segment alphanumeric hexadecimal output. The "A" versions will provide the "Code B" output code,
i.e., 0-9, dash, E, H, L, P, blank_ Either device will correctly
decode true BCD to seven-segment decimal outputs.
Devices in the ICM7211/7212 family are packaged in a
standard 40 pin plastic dual-in-line package and all inputs
are fully protected against static discharge.

ICM7212 (LED) FEATURES
• 28 current-limited segment outputs provide 4-digit
non-multiplexed direct LED drive at > SmA per
segment.
• Brightness input allows direct control of LED
segment current with a single potentiometer. Can
function digitally as a display enable.
• ICM7212M and ICM7212A devices provide same
input configuration and output decoding options as
the ICM7211.

PIN CONFIGURATIONS

(OUTLINE DRAWING PL)

4Q] 01

"

39

01
C1

G',3
Fl : 4
BP 'S:

G1

38 B1

A2 ~

A2'S

"

.

B2: 7
C2
02 '~
E2
G2
F2 I;';
A3
B3
C3

""
"

""

3
F1 [_~
BP 5

f4' 04

7211
7211A

33' OJ

!

~l ~~
3~

~7.

eo

26, F4
25 G4
E4

G318

~

04

F3,'_'!:

2.2_ C4

A4 20

Inputs

~:~ :~ I ~~:ts

,.

E3

I Select

B3'

:1J

03 "'6

DI9 1t

82 ~J
C2 ~)
02 ~
E2 10
02,11
F2

"12

7211M
7211AM

A1

Chip Select 2
33 Chip Select 1
32 Digit Selel:' Code Bil 2

"

31 ,Digit Select Code Bill
30 B3,

""

""

2\

A. ~o

F1;4
BRT --5
A2
B2 .7
C2
02 ]
E2 _~o
G2 ,j

:~J :~ I Data Inputs
27
2S

2i&~

"

01

2i

C.

Gl,3

36 Oscillator
35 GNO

A3
B3
C3
0'
• 3 .17
G3 "'-8

"
"
""

4Q] 01

.

F2

A3 "
B' i.
C3
03 "16

"

BO

"

G.
E4

E3.~

23 D.
22 C.

G3

"

F3 19
A4 20

B4

6·14

Fl;4
BRT _.5=

., ,

•

B2 7
C2 ~~
02 ~
E2 ,~O
G2

7212
7212A

~:~ :~ I ~~:ts
~1.. BO

~

.."

"Cl D.
22_ C.

i,-

B'

F2

A3
B3
C3
03
'3
G3

"

7212M
7212AM

"
"
"

"2

"
"17
"'!

A. 20

21~ 84

.D~DIl

ICM7211/ICM7212
ABSOLUTE MAXIMUM RATINGS

Power Dissipation (Note 1) ...................................... O.S W @ 70°C
Supply Voltage ... , ....................................................... 6.SV
Input Voltage (Any
Terminal) (Note 2) ................................... : V+ +0.3V, GROUND --{).3V
Operating Temperature Range .................................. -20°C to +70°C
Storage Temperature Range ................................... -SsoC to +125°C
Lead Temperature (Soldering 10 sec.! .................................... 300°C
NOTE 1: This limit refers to that of the package and will not be realized during normal operation.
NOTE 2: Due to the SCR structure inherent in the CMOS process, connecting any. terminal to
voltages greater than V+ or less than GROUND may cause destructive device latch up.
For this reason, it is recommended that no inputs from external sources not operating on
the same power supply be applied to the device before its supply is established, and that
in multiple supply systems, the supply to the ICM7211/ICM7212 be turned on first.

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS
TEST CONDITIONS: All parameters measured with V+ = 5V unless otherwise specified.
ICM7211 CHARACTERISTICS (LCD)
PARAMETER
Operating Supply Voltage Range
Operating Current
Oscillator Input Current
Segment Rise/Fall Time
Backplane Rise/Fall Time
Oscillator Frequency
Backplane Frequency

UNIT
V

TYP
S
10
±2
O.S
I.S
19
1S0

MAX
6
SO
±10

MIN

TYP

MAX

UNIT

4

S
10

6
SO

V
iJ. A

200
±0.01
8

±1

mA
iJ. A
mA

TYP

MAX

UNIT

MIN
3

SYMBOL CONDITIONS
Vsupp
Test Circuit, Display blank
lop
Pin 36
losci
CL - 200pF
trfs
C L = 5000pF
trfb
Pin 36 Floating
fasc
Pin 36 Floating
fbp

iJ. A
iJ.S
kHz
Hz

ICM7212 CHARACTERISTICS (COMMON ANODE LED)
PARAMETER
Operating Supply Voltage Range
Operating Current
Display Off
Operating Current
Segment Leakage Current
Segment On Current

SYMBOL CONDITIONS
VsuPP
lop
lop
ISLK
ISEG

Pin S (Brightness),
Pins 27-34 - GROUND
Pin S at V , Display all 8's
Segment Off
Segment On, Va - +3V

._--_.

S

INPUT CHARACTERISTICS
PARAMETER
SYMBOL CONDITIONS
Logical "1" input voltage
V,H
Logical "0" input voltage
V,L
Input leakage current
Pins 27-34
IILK
Pins 27-34
Input capacitance
C,N
BP/Brightness input leakage
Measured at Pin S with Pin 36 at GND
ISPLK
BP/Brightness input capacitance
All Devices
CSPI
AC CHARACTERISTICS - MULTIPLEXED INPUT CONFIGURATION
Digit Select Active Pulse Width
Refer to Timing Diagrams
tsa
Data Setup Time
tds
Data Hold Time
tdh
Inter-Digit Select Time
t,ds
AC CHARACTERISTICS - MICROPROCESSOR INTERFACE
Chip Select Active Pulse Width
ksa
other Chip Select either held active, or
both driven together
Data Setup Time
tds
Data Hold Time
tdh
Inter-Chip Select Time
tics

6-15

MIN
3

±.01
S
±.01
200
1

2
±1
±1

V
iJ.A
pF
iJ. A
pF
iJ.s

sao
200
2

ns
iJ.s

200
100
10
2

ns
0
iJ.S

ICM7211/ICM7212
TYPICAL CHARACTERISTICS
ICM7211 BACKPLANE FREQUENCY
AS A FUNCTION OF SUPPLY VOLTAGE

ICM7211 OPERATING SUPPLY CURRENT
AS A FUNCTION OF SUPPLY VOLTAGE
30

180

J/

f- LbD D~VICJS
TA=25"C

I

:?_D DEVICES, TEST CIRCUIT

25 t- DISPLAY BI..ANK

Y

150

PIN 36 OPEN

J

I

20
,TA

1/
=i20 C')I
O

120

,/1-'

1/v.;

10

V

V
,,

V '/
TA=25°V

COSC=O

/
I

V.I

(PIN 36 OPEN) _

/
"

.,,- V
. / VCOSC=22PF

.,,- V

60

:/ ~

, ~ ~ ~TA=700C

.'

-

30

,", V

.'

Cosc= 220pF

o
4
y+ (VOLTS)

1

4
y+ (VOLTS)

ICM7212 LED SEGMENT CURRENT
AS A FUNCTION OF OUTPUT VOLTAGE

" PI~ Ai.·
TA = 25°C
•

-i--"V·=8V

/V
/

10

/

l/
I/ /

rt/

/'

-

v+ =5V

l-

y+

=4V

!J

,II
0 0

3
Vo (VOLTS)

ICM7212 LED SEGMENT CURRENT
AS A FUNCTION OF
BRIGHTNESS CONTROL VOLTAGE
12
SJGMEINT

I- TA=2S"C

ICM7212 OPERATING POWER (LED DISPLAY)
AS A FUNCTION OF SUPPLY VOLTAGE

O~TPU~ AT ~ 3V I

1800

/

I-

I

10

1500

V

LJD

DE~'CE~

I

I

I

I

DISPLAY ALL EIGHTS
LED FORWARD VOLTAGE DROP
VFLEO=1.7V

/

PINSATY+

TA=25"C

1/

1200

V

J

V

900

V
1/

V

600

............

/
/

300

V

"

/
o

V
o

2

3

•

4

VOLTAGE ON BRT PIN 5 (VOllS)

V+ (VOLTS)

6-16

ICM7211/ICM7212
BLOCK DIAGRAMS
ICM7211 (A)
0'

03

SEGMENT OUTPUTS

SEGMENT OUTPUTS

02
SEGMENT OUTPUTS

01
SEGMENT OUTPUTS

OIGITl~~~~====~~_~

SELECT

INPUTS

OSCILLATOR
16KHz
FREERUNNING

OSCilLATOR
INPUT

ICM7212 (A)
0'

03

SEGMENT OUTPUTS

SEGMENT OUTPUTS

02
SEGMENT OUTPUTS

01
SEGMENT OUTPUTS

BRIGHTNESS

DIGIT!
INPUTS

SELECT

===============================================================~________________J

6-17

ICM7211/1CM7212

0'
SEGMENT OUTPUTS

ICM7211(A)M
D.
SEGMENT OUTPUTS

02

01

SEGMENT OUTPUTS

SEGMENT OUTPUTS

DATA
INPUTS

2-81T
DIGIT SELECT
CODE INPUT

CHIP SELECT 1
OSCILLATOR

CHIP SELECT 2

16KHz
FREERUNNING

OSCILLATOR

INPUT

m

ICM7212(A)M
0'

D.

02

01

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

BRIGHTNESS

DATA
INPUTS

2-BIT
DIGIT SELECT
CODe INPUT

CHiPSELE'CT1
CHIP SELECT 2

6-18

ICM7211/ICM7212
INPUT DEFINITIONS
In this table, V+ and GROUND are considered to be normal operating input logic levels. Actual input low and high levels are
specified under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.

INPUT
BO

B1
B2
B3
OSC
(LCD Devices Only)

TERMINAL CONDITION
27
V+ = Logical One
GND = Logical Zero
V+ = Logical One
GND = Logical Zero
28
V+ - Logical One
GND = Logical Zero
29
V+ = Logical One
30
GNO = Logical Zero
36
Floating or with ex·
ternal capacitor to V+
GROUND

ICM7211/1CM7212
MULTIPLEXED-BINARY INPUT CONFIGURATION
INPUT
TERMINAL CONDITION
01
31
V+ = Active
D2
32
GNO = Inactive
D3
33
D4

FUNCTION
Ones (Least Significant)
Twos

Eights (Most significant)
Oscillator input
Disables BP output devices, allowing segments to be synced to an
external signal input at the BP terminal (Pin 5)

FUNCTION
D1 (Least significant) Digit Select
D2 Digit Select
D3 Digit Select
D4 (Most significant) Digit Select

34

ICM7211 M/ICM7212M
MICROPROCESSOR INTERFACE INPUT CONFIGURATION
INPUT DESCRIPTION
TERMINAL CONDITION
D81 Digit Select
31
Code Bit 1 (LSB)
V+ = Logical One
DS2 Digit Select
GND = Logical Zero
32
Code Bit 2 (MSB)
CS1
CS2

Chip Select 1
Chip Select 2

33
34

Data Input Bits

Fours

FUNCTION
DS1 & DS2 serve as a two bit Digit Select Code Input
OS2, DS1 = 00 selects 04
OS2, DS1 = 01 selects D3
DS2, DS1 = 10 selects D2
DS2, DS1 = 11 selects D1
When both CS1 and CS2 are taken low, the data at the Data
and Digit Select code inputs are written into the input latches.
On the rising edge of either Chip Select, the data is decoded
and written into the output latches.

V+ - Inactive
GND = Active

TEST CIRCUIT
+

5Y

-

IIII t - - - - ' - - - - ,

-':~M~2::):~~
!g;
5 SP

esc

36

GND 35

EACH SEGMENT

TO BACKPLANE

Y+(MICROPROCESSOR)

DIGIT ICHIP

WITH ZOOpF
CAPACITOR

u

SELECT

32

INPUT

31

DATA! 28~~

VERSIONS
GND(MUL TIPLEXED)

INPUTS

::.rU 1

'-,,20:::...._ _........

u·----------- J

6·19

'VERSIONS
y+

.O~OI6

ICM7211/ICM7212
OSCILLATOR
FREQUENCY
DIGIT SELECT

nr 1fUl.Jlr 1IUlJ
I
I
1--I
_

1JUl.JlJ'

_ _......_-I~128CYCLES_1

DN-1

BACKPLANE

INPUT IOUTPUT

DIGIT SELECT
ON

f--64 CYCLES

OFF SEGMENTS

ON SEOWIENTS

Figure 1: Multiplexed Input Timing Diagram

L-L-

64 CYCLES---!

'--_.....IrDisplay Waveforms

large capacitive loads with short (1-2/,5) rise and fall times.
The maximum frequency for a backplane signal should be
about 150Hz although this may be too fast for optimum
display response at lower display temperatures, depending
on the display used.

cs.
(CS2)

CS2
(CS1)

The onboard oscillator is designed to free run at approximately 19KHz at microampere power levels. The oscillator
frequency is divided by 128 to provide the b<;lckplane frequency, which will be approximately 150Hz with the oscillator
free-running; the oscillator frequency may be reduced by connecting an external capacitor between the OSCillator terminaland V+.

DATA AND
DIGIT SELECT

CODe

~ ~DONTCARE
Figure 2: Microprocessor Interface Input Timing Diagram

The oscillator may also be overdriven if desired, although
care must be taken to ensure that the backplane driver is not
disabled during the negative portion of the overdriving Signal
(which could cause a d.c. component to the display). This
can be done by driving the OSCillator input between the
positive supply and a level out o.f. the range where the
backplane disable is sensed (about one fifth of the supply
voltage above GrouND). Another technique for overdriving
the oscillator (with a signal swinging the full supply) is to
skew the duty cycle of the overdriving Signal such that the
negative portion has a duration shorter than about one
microsecond. The backplane disable sensing circuit will not
respond to signals of this duration.

DESCRIPTION OF OPERATION
LCD DEVICES
The LCD devices in the family (lCM7211, 7211A, 7211M,
7211 AM) provide outputs suitable for driving conventional
four-digit by seven-segment LCD displays, including 28
individual segment drivers, backplane driver, and a selfcontained oscillator and divider chain to generate the
backplane frequency.
The segment and backplane drivers each consist of a CMOS
inverter, with the n- and p-channel devices ratioed to provide
identical on resistances, and thus equal rise and fall times.
This eliminates any dc component, which could 'arise from
differing rise and fall times, and ensures maximum display
life.
The backplane output devices can be disabled by
connecting the OSCillator input (pin 36) to GrouND. This
allows the 28 segment outputs to be synchronized directly to
a signal input. at the BP terminal (pin 51. In this manner,
several slave devices may be cascaded to the backplane
output of one master device, or the backplane may be
derived from an external source. This allows the use of
displays with characters in multiples of four and a single
backplane. A slave device represents a load of approximately
200pF (comparable to one additional segment), thus the
limitation of the number of devices that can be slaved to
one master device backplane driver is the additional load
represented by the larger backplane of displays of more than
four digits; and the effect of that loart on the backplane rise
and fall times. A good rule of thumb to observe in order to
minimize power consumption is to keep the rise and fall
times less than about 5 microseconds. The backplane output
driver should handle the backplane to a display of 16 onehalf-inch characters (rise and fall times not exceeding 51's. ie,
3 slave devices and the display backplane driven by a fourth
master device). It is recommended that if more than four
devices are to be slaved together, that the backplane signal
be derived externally and all the ICM7211 devices be slaved
to it. This external signal should be capable of driving very

LED DEVICES
The LED devices in the family (ICM7212, 7212A, 7212M,
7212AM) provide outputs suitable for directly driving fourdigit by seven-segment common-anode LED displays,
including 28 individual segment drivers, each consisting of a
low-leakage, current-controlled, open-drain n-channel
transistor.
The drain current of these transistors can be controlled by
varying the voltage at the BRighTness input (pin 5). The
voltage at this pin is transferred to the gates of the output
devices for "on" segments, and thus directly modulates the
transistor's "on" resistance. A brightness control can be
easily implemented with a single potentiometer controlling
the voltage at pin 5, connected as in Fig (31. The
potentiometer should be a high value (100Kfl to 1MflJ to
minimize 12R power consumption, which can be significant
when the display is off.
The BRighTness input may also be operated digitally as a
display enable; when high, the display is fully on, and low
fully off. The display brightness may also be controlled by
varying the duty cycle of a signal swinging between the two
voltages at the BRighTness input.
Note that the LED devices have two connections for
GrouND; both of these pins should be connected. The

6-20

ICM7211/1CM7212
A select code of 00 writes into 04, OS2 =0, OS1 =1 writes into
03, OS2 = 1, OS1 = 0 writes into 02, and 11 writes into 01. The
timing relationships for inputting data are shown in Fig (2),
and the chip select pulse widths and data setup and hold
times are specified under Operating Characteristics.

double connection is necessary to minimize effects of bond
wire resistance with the large total display currents possible.
When operating LED devices at higher temperatures and/or
higher supply voltages, the device power dissipation may
need to be reduced to prevent excessive chip temperatures.
The maximum power dissipation is 1 watt at 25°C, derated
linearly above 35°C to 500mW at 70°C H5mW/oC above
35°Cl. Power dissipation for the device is given by:
P = (V+-VFLED) (lSEG) (nSEG)
where VFLED is the LED forward voltage drop, ISEG is
segment current, and nSEG is the number of "on" segments.
It is recommended that if the device is to be operated at
elevated temperatures the segment current be limited by use
of the BRighTness input to keep power dissipation within the
limits described above.
--~_--

Table 1: Output Codes

B3

B2

B1

BO

HEXADECIMAL
ICM7211(M)
ICM7212(M)

o

0

0

0

'-'

,-,
'-',

,?

I:'

BINARY

V+(LED ANODES)

BRIGHTNESS

PIN 5

Figure 3: Brightness control

INPUT CONFIGURATIONS AND OUTPUT CODES
The standard devices in the ICM7211/12 family accept a
four-bit true binary (ie, positive level = logical one) input at
pins 27 thru 30, least significant bit at pin 27 ascending to the
most significant bit at pin 30. The ICM7211, ICM7211 M,
ICM7212, and ICM7212M devices decode this binary input
into a seven-segment alphanumeric hexadecimal output,
while the ICM7211A, ICM7211AM, ICM7212A, and
ICM7212AM decode the binary input into the same sevensegment output as in the ICM7218 "Code B", ie 0-9, dash, E.
H, L, P, blank. These codes are shown explicitly in Table 1.
Either decoder option will correctly decode true BCD to a
seven-segment decimal output.
These devices are actually mask-programmable to provide
any 16 combinations of the seven segment outputs decoded
from the four input bits. For larger quantity orders, (10K pcs.
minimum) custom decoder options can be arranged.
Contact the factory for details.
The ICM7211, ICM7211A, ICM7212, and ICM7212A devices
are designed to accept multiplexed binary or BCD input.
These devices provide four separate digit lines (least
significant digit at pin 31 ascending to most significant digit
at pin 34), each of which when taken to a positive level
decodes and stores in the output latches of its respective
digit the character corresponding to the data at the input
port, pins 27 through 30. More than one digit select may be
activated simultaneously (which will write the same
character into all selected digits), although the timing
requirements shown in Fig (1) and under Operating Characteristics for data setup, hold, and inter-digit select times
must be met to ensure correct output.
The ICM7211M, ICM7211AM, ICM7212M, and ICM7212AM
devices are intended to accept data from a data bus under
processor control.
In these devices, the four data input bits and the two-bit digit
select code (DS1 pin 31, DS2 pin 32) are written into input
buffer latches when both chip select inputs (CS1 pin 33, CS2
pin 34) are taken low. On the rising edge of either chip select
input, the content of the data input latches is decoded and
stored in the output latches of the digit selected by the
content~ of the digit select code latches.

000

1

o

0

1

0

o

0

1

1

CODE B
ICM7211A(M)
ICM7212A(M)

,-,

o

1

0

0

o
o
o

1

0

1

'-.J

1

1

0

1

1

1

1

0

0

0

1

0

0

1

1

0

1

0

1

0

1

1

1

0

0

1

1

0

1

1

1

1

0

1

1

1

1

::;

~,

,-'-,,

1

,

:

-'

'-:
'--

'-'
-,

-,,

,

,-,

:::

o

,-,

CI

~,

,CI,

-'

b
,-

E
,,
,1

'- ,

o

,
'-

!-

(BLANK)

t='

SEGMENT ASSIGNMENT

APPLICATIONS
1. Ganged ICM7211's Driving 8-Digit LCD Display.
0706051040302

BCO/B,NARy_-*_L+.W...+--,======:jf-H"ti+-..J
DATA

OIGIT\~~~-§~

SELECTS

04
03

02

01-------------------~

6-21

ICM7211/1CM7212
2. 4 1/2 Digit LCD DPM with Digit Blanking on Overrange.

3101
D2 26

3202

D3p2~-t==~:>----~------------1-~

33 D3

2,3,4

D4f2:!j4i-'-1:=t::==:C)-+---------t--1

3404

37-40

88 23

30 B!J

ICL71C03A 84 ~2~=tf~~~!~±=======j=j
r---Cci.o.1
1
B2~1

81 20

100kn
INPUT

ICM7211A

DS

2982

6~26

OPTIONAL
CAPACITOR

OSC 36

--u---

+5V

22-100pF

2891
2780

1.'r--+~~~~~~=;

STiiOiE 18'r--~---'

I
I

I

ov

+5V
+5V

I

L- _ _ _ _ _ .J

'" 120kHZ

T

300pF

OV

3600

+15V: ANALOG POSITIVE VOLTAGE
DIGITAL POSITIVE VOLTAGE (v+)
OV: DIGITAL GROUND VOLTAGE
-15V: ANALOG NEGATIVE VOLTAGE

+ 5V:

ANALOGGND

NOTE: See also ICLS052/1CLS06S/lCL71C03 and ICL7135 Data Sheets for similar
circuits with fewer features.

6-22

ICM7211/ICM7212
3, 8048/8748/IM80C48 Microprocessor Interface,
8-DIGIT
LCD DISPLAY

B B B B B B B BJ

y+ +5V

.h~
2.

2•

vee YOO vss

~~

~~

P1D 27

'2. XTALl

3 XTAL2

r----

ICM7211M
HIGH ORDER DIGITS

28
2.
3.
31
32

~ 35

-=

1/0

_

-(

r

~£L

,~

SEGMENTS 6-26
DATA

BP 5

37-40

36osc~-h~~'D3~2 C3~'

c;:

5 BP

ICM7211M
LOW ORDER DIGITS

U.'

6-26 SEGMENTS

OATA 37 -40

v'

m;ioo03~' D3~2 ~ C3~2

NC

Y' 't'SV

h~

4 RESET

• SS

3.
37
P2738

1 T.

22 A9

2 CE
NC

I

PAO 24

12 ADO

2.
2.
27
28
2.
3.

13 AD1

PA731

1 PROG

14

14 AD2

"

15 AD3
16
17
18
19

VW ijp

I

+ 5V

PBO 32
33

A04
A05
AD6
AD7

34
3'
3.
37
38

• iOli

pa739

1010W

9RC
11 ALE

8355/8755 NOT NECESSARY
TO leM72l1 INTERFACE

'EA should go to

for

BO(C) 35 deVices.

ORDER PART NUMBER

LED
DISPLAY

ICM7211 IPL
ICM7211A IPL
ICM7211M IPL
ICM7211AM IPL
ICM72121PL
ICM7212A IPL
ICM7212M IPL
ICM7212AM IPL

OUTPUT CODE
HEXADECIMAL
CODEB
HEXADECIMAL
CODE B
HEXADECIMAL
CODE B
HEXADECIMAL
CODEB

Evaluation Kits are also available. Order ICM7211 EVIKit or ICM7212 EV/Kit.

6-23

835518755
ROMIEPROM
WITH 110
EXPANDER

7

3

-==

I
He

ORDERING INFORMATION

LCD
DISPLAY

2.

I/O

18
DB719

I I

•

YDDVSS

4 RESET

"
17f---

A,~E PSfN PW G

vee

23 Al0

13

fNT

4.

21 AI

DBO 12

NPUT{ 39 T1
6

r-- y+ t5V
~

33
P17 34

IMBOC48 P2. 21
8048
22
~ 7 EA-Ito
8748
~!
I'COMPUTER 3.

-==
-

1
3.

OSC 36

INPUT CONFIGUR.ATIONS
MULTIPLEXED 4-BIT
MICROPROCESSOR INTERFACE
MULTIPLEXED 4-BIT
MICROPROCESSOR INTERFACE

•I

Ne

ICM7216A/B/C/D
10 MHz Universall
Freque~cy Counters
FEATURES

GENERAL DESCRIPTION

ALL.VERSIONS:

The ICM7216A and 8 are fully integrated Universal
Counters with LED display drivers, They combine a
high frequency oscillator, a decade timebase counter,
an 8-decade data counter and latches, a 7-segment
decoder, digit multiplexers and 8 segment and 8 digit
drivers which directly drive l1\rge multiplexed LED displays. The counter inputs have a maximum frequency
of 10 MHz in frequency and unit counter modes and 2
MHz in the other modes. 80th inputs are digital inputs.
In many applications, amplification and level shifting
will be required to obtain proper digital signals for
these inputs.

• Functions as a frequency counter.
Measures frequencies from DC to 10 MHz
• Four internal gate times:
0.01 sec, 0.1 sec, 1 sec, 10 sec'ln frequency
counter mode
• Output directly drives digits and
segments of large multiplexed LED displays.
Common anode and common cathode versions
• Single nominal 5V supply required
• Stable high frequency oscillator, uses either
1 MHz or 10 MHz crystal

The ICM7216A and 8 can function as a frequency
counter, period counter, frequency ratio (fA/fs)
counter, time interval counter or as a, totalizing
counter. The counter uses either a 10 MHz or 1 MHz
quartz crystal timebase. For period and time interval,
the 10MHz timebase gives a 0,1 J,tsec resolution. In
period average and time interval average, the
resolution can be in the nanosecond range. In the
frequency mode, the user can select accumUlation
times of 0.01 sec, 0.1 sec, 1 sec and 10 sec. With a 10 sec
accumulation time, the frequency can be displayed to a
resolution of 0,1 Hz in the least significant digit. There
is 0.2 seconds between measurements in all ranges.

• Internally generated decimal points,
interdlglt blanking, leading zero blanking
and overflow indication
• Display Off mode turns off display and puts
chip into low power mode

m·

• Hold and Reset inputs for additional flexibility
ICM7216A AND B

•.

Functions also as a period counter,
unit counter, frequency ratio counter or time
interval counter

The ICM7216C and D function as frequency counters
only, as described above.
All versions of the ICM7216 incorporate leading zero
blanking, Frequency is displayed in kHz. In the
iCM7216A and 8, time is displayed in J,tsec. The display
is multiplexed at 500Hz with a 12.2% duty cycle for
each digit. The ICM7216A and C are designed for
common anode display with typical peak segment currents of 25mA. The ICM72168 and D are designed for
common cathode displays with typical peak segment
currents of 12mA. In the display off mode, both digit
and segment drivers are turned off, enabling the display to be used for other functions.

• 1 cycle, 10 cycles, 100 cycles, 1000 cycles In
period, frequency ratio and time interval modes
• Measures period from 0.5J,ts to 10s
ICM7216C AND 0
• Decimal pOint and leading zero blanking may be
externally selected

ORDERING INFORMATION
Universal Counter; Common Anode LED
Universal Counter; Common Cathode LED
Frequency Counter; Common Anode LED
Frequency Counter; Common Cathode LED
Evaluation Kit:
Use ICM7226 EV/Kii

ICM 7216 A IJI
ICM 721~ B IPI
ICM 7216 C ,IJI
ICM 7216 0 IPI

I

Type

IL

Package

{JI - 28 pin CERDIP
PI _ 28 pin PLASTIC DIP

Temperature Range -20 0 C to +85 0 C

6·24

ICM7216
PIN CONFIGURATIONS (outline dwgs JI, PI)
CONTROL INPUT
INPUT B
FUNCTION INPUT

DECIMAL POINT OUTPUT
SEG E OUTPUT

INPUT A

CONTROL INPUT

HOLD INPUT

asc OUTPUT
asc INPUT
EXT asc INPUT

INPUT A

INPUT B

HOLD INPUT

FUNCTION INPUT

asc OUTPUT

DIG! T 3 OUTPUT

csc INPUl
EXT esc INPUT

DIGIT 1 OUTPUT

SEG G OUTPUT

DIGIT 1 OUTPUT

DIGIT 2 OUTPUT

DECIMAL POINT OUTPUT

SEG A OUTPUT

DIGIT 2 OUTPUT

DIGIT 4 OUTPUT

SEG G OUTPUT

GND

DIGIT 3 OUTPUT

GND

seG E OUTPUT

SEG 0 OUTPUT

DIGIT 4 OUTPUT

DIGIT 5 OUTPUT

SEG A OUTPUT

SEG B OUTPUT

DIGIT 5 OUTPUT

DIGIT 6 OUTPUT

seG 0 OUTPUT

SEG C OUTPUT

v+

DIGIT 7 OUTPUT

v+

01 GI T 6 OUTPUT

DIGIT 8 OUTPUT

SEG BOUTPUT

DIGIT 7 OUTPUT

RESET INPUT

seGe OUTPUT

DIGIT 8 OUTPUT

RANGE INPUT

SEG F OUTPUT

RESET INPUT

CONTROL INPUT

iN

INPUT A

CONTROL INPUT

INPUT A

PROGRESS

HOLD INPUT

MEASUREMENT IN PROGRESS

DECIMAL POINT OUTPUT

ose OUTPUT

DIGIT 1 OUTPUT

OSCOUTPUT

OSC INPUT

DIGIT 3 OUTPUT

ose INPUT

SEG G OUTPUT

EXT OSC INPUT

DIGIT 2 OUTPUT

EXT OSC INPUT

SEG A OUTPUT

OIGIT 1 OUTPUT

DIGIT 4 OUTPUT

DECIMAL POINT OUTPUT

GND

DIGIT 2 OUTPUT

GND

SEO G OUTPUT

SEG D OUTPUT

DIGIT 3 OUTPUT

DIGIT 5 OUTPUT

SEG E OUTPUT

SEG BOUTPUT

DIGIT 4 OUTPUT

DIGIT 6 OUTPUT

SEG

A OUTPUT

e OUlPUT

OIGIT 5 OUTPUT

DIGIT 7 OUTPUT

SEG

o OUTPUT

v+

DIGIT 8 OUTPUT

MEASUREMENT

SEG E OUTPUT

SEG

seG F OUTPUT

HOLD INPUT

v+

RESET INPUT

DIGIT 6 OUTPUT

RESET INPUT

SEG B OUTPUT

EX. D.P. INPUT

DIGIT 7 OUTPUT

EX. D.P. INPUT

SEa C OUTPUT

RANGE INPUT

,)IGIT 8 OUTPUT

RANGE INPUT

SEa F OUTPUT

EVALUATION KIT
The ICM7226 Universal Counter System has all of the
features of the ICM7216 plus a number of additional
features. The ICM7226 Evaluation Kit consists of the
ICM7226AIJL (Common Anode LED Display), a 10M Hz
quartz crystal, eight 7 segment 0.3" LED's, P.C. board,
reSistors, capacitors, diodes, switches, socket: everything needed to quickly assemble a functioning
ICM7226 Universal Counter System.

ABSOLUTE MAXIMUM RATINGS
Maximum Supply Voltage. . . . . . . . . . . . . . . . . .. 6.5V
Maximum Digit Output Current . . . . . . . . . . .. 400mA
Maximum Segment Output Current. ......... 60mA
Voltage On Any Input or
Output Terminai[1] . . . . . . . . .. V + + 0.3V to - 0.3V
Maximum Power Dissipation at
70°C .................... 1.0W(ICM7216A&C)
0.5W (ICM72168 & D)
Lead Temperature (Soldering, 10 sec) .... . . .. 300°C
Maximum Operating Temperature
Range. . . . . . . . . . . . . . . . . . . . .. - 20°C to + 85°C
Maximum Storage Temperature
Range .. .. .. .. .. .. .. .. .. ... - 55°C to + 125°C

Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Note:
1. The ICM7216 may be triggered into a destructive latchup mode if either Input signals are applied before the power supply is applied or if
input or outputs are forced to voltages exceeding V + to GND by more than 0.3 volts.

6-25

ICM7218
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: V+ = 5.0V, Test Circuit, TA = 25°C, unless otherwise specified.
PARAMETER

MIN.

TYP.

MAX.

UNITS

2

5

mA

6.0

V

SYMBOL

CONDITION

1+

Display Off, Unused Inputs to GND

V+

-20°C < TA < +85°C, INPUT A,
INPUT B Frequency at f max

4.75

-20° C < T A < +85° C
4.75 < V+ s; 6.0V, Figure 1,
Function = Frequency, Ratio, Unit
Counter
Function = Period, Time Interval

10
2.5

MHz
MHz

'20°C < TA < +85°C
4.75 < V+ s; 6.0V,
Figure 2

2.5

MHz

-20°C < TA < +85°C
4.75 < V+ s; 6.0V,
Figure 3

250

ns

ICM7216A/B
Operating Supply Current
Supply Voltage Range
Maximum Frequency
INPUT A.Pin 28

Maximum Frequency
INPUT B, Pin 2

fA(max)

f8(max)

Minimum Separation
INPUT A to INPUT B
Time Interval Function
Maximum Osc. Freq. and Ext.
Osc. Frequency

fose

Minimum Ext. Osc. Freq.

fose

Oscillator Transconductance

gm

V+ =4.75V, TA = +85'C

Multiplex Frequency

fmux

lose

Time Between Measurements
Input Voltages:
Pins 2,13,25,27,28
Input Low Voltage
Input High Voltage
Input Resistance to V+
Pins 13,24
Input Leakage
Pin 27,28,2
Minimum Input Rate
of Change

-20°C < TA < +85°C
4.75 < V+ s; 6.0V

MHz

10

kHz

100

",mhos

2000

= 10MHz

500

Hz

fose = 10MHz

200

ms

-20°C < TA < +85°C

R'N

IrLK
dV,N/dt

V
V

1.0

VINL
VINH

3.5
Y,N = V+ -1.0V

100

400

kll
20

"
Supplies Well Bypassed

",A

15

mV/",s

ICM7216A
Digit Driver:
Pins 15,16,17,19,20,21,22,23
High Output Current
Low Output Current

IOH
IOL

VOUT = V+ - 2.0V
VOUT = + 1.0V

-140

-180
+0.3

mA
mA

SEGment Driver:
Pins 4,5,6,7,9,10,11,12
Low Output Current
High Output Current

IOL
IOH

Your = + 1.5V
VOUT = v+ - 2.5V

20

35
-100

mA
iJ. A

Multiplex Inputs:
Pins 1.3,14
Input Low Voltage
Input High Voltage
Input Resistance to GROUND

V,NL
VINH
RIN

VIN = +1.0V

Digit Driver:
Pins 4,5,6,7,9,10,11,12
Low Output Current
High Output Current

IOL
IOH

VOUT=+ 1.3V
VOUT = V+ - 2.5V

50

SEGment Driver:
Pins 15,16,17,19,20,21,22,23
High Output Current
Leakage Current

IOH
ISLK

VOUT = V+- 2.0V
VOUT = V+- 2.5V

-10

Multiplex Inputs:
Pins 1,3,14
In'put Low Voltage
Input High Voltage
Input Resistance to V+

V,NL
V,NH
RIN

0.8
2.0
50

100

V
V
k!l

75
'100

mA
",A

ICM72168

V+ 0.8
200

V+ -

VIN = V+ -

1.0V

6-26

mA
",A

10

360

2.0

V
V
k!l

.D~DlL

ICM7216
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS: V+

= 5.0V,

PARAMETER

Test Circuit, TA

SYMBOL

= 25° C,

unless otherwise specified.

CONDITION

MIN.

TYP

MAX.

UNITS

2

5

mA

6.0

V

ICM7216C/D
Operating Supply Current

1+

Supply Voltage Range
Maximum Frequency
INPUT A, Pin 28
Maximum Osc. Freq and Ext.
Osc. Frequency
Minimum Ext. Osc.

~rE:q.

Display 011, Unused Inputs to GND
-20'C

B

1

10

102

103

104

105

106

107

108

TIME INTERVAL ([.Is)

The segment and digit outputs in ICM7216's are not directly
compatible with either TTL or CMOS logic when driving LEOs.
Therefore, level shifting with discrete transistors may be
required to use these outputs as logic signals.

FIGURE 9. Maximum Accuracy of Time Interval
Measurement Due to Limitations of
Quantization Errors
6-33

.O~OlL

ICM7216
CIRCUIT APPLICATIONS

The ICM7216 has been designed for use in a wide range of
Universal and Frequency counters. In many cases,
prescalers will be required to reduce the input frequencies to
under 10 MHz. Because INPUT A and INPUT B are digital
inputs, additional circuitry is often required for input buffering,
amplification, hysterisis, and level shifting to obtain a good
digital signal.
The ICM7216A or B can be used as a minimum component
complete Universal Counter as shown in Figure 11. This circuit
can use input frequencies up to 10 MHzat INPUT Aand 2 MHz
at INPUT B.lfthe signal at INPUT A hasa very low duty cycle it
may be necessary to use a 74121 monostable multivibrator or
similar circuit to stretch the input pulse width to be able to
guarantee that it is at least 50ns in duration.
To measure frequencies up to 40 MHz the circuit of Figure 12
can be used. To obtain the correct measured value, it is necessary to divide the oscillator frequency by four as well as the
input frequency. In doing this the time between measurements
is also lengthened to 800 ms and the display multiplex rate is
decreased to 125 Hz.

FIGURE 10. Maximum Accuracy for Frequency RatIo
Measurement Due to Limitation of
.
Quantization Errors

v+

V'
10k,Q

DISPLAY DISPLAY
~~~
BLANK
TEST ENABLE

39pF
TVP.

10MHz
CRYSTAL

28
27
26

3
FREQUENCY
PERIOD
FREQUENCY RATIO

0,
Os
02

0,
02

UNIT COUNTER

10
11

12
13
14

DIGIT

0,

25
EXT
24 I-----------------------------------------------+-~o~
INPUT
23
D.P.
G
SEC.
CYCLES
ICM 22
10kn
0, 0.Q1 -'-.07216B 21
02
0.1
10.0
20
A
03 1.0
100,0

4

10kQ 03

TIME INTERVAL

DRIVERS

Os
IN914'S

04 10.0
lK
19
0
18 I--+--~----------------------------~========~+----ov+
17
16
SEGMENT DRIVERS
15

I

I

ICOMMON CATHODE LED DISPLAY I

BBBBBBBB

9
dp

0,

LED
OVERFLOW

L-__~~------~~------~~--~--~~----~~~------~~-------4---------4-----------4--~INDICATOR

FIGURE 11. 10MHz Universal Counter

6·34

ICM7216'

EXT

v'

ase

DISPLAY DISPLAY
OFF
TEST

EN
39pF
TVP.
100kQ

lQOpF ~
22MSl
Os

2.5 MHz
CRYSTAL

dp

1-------+.--+--------iD

lN914'S

EXT

__------------------------------~----------------------------~osc

INPUT

'---____~---O'g2~__~---~
____

~

10kn

D3

COMMON ANODE LED DISPLAY!

D4

BBBBBBBB
D,

FIGURE 12. 40MHz Frequency Counter

If the input frequency is prescaled by ten, then the oscillator
can remain at 10 or 1 MHz, but the decimal point must be
moved one digit to the right. Figure 13 shows a frequency
counter with a .;- 10 prescaler and an ICM7216C. Since there
is no external decimal point control with the ICM7216A or 8,
the decimal point may be controlled externally with additional
drivers as shown in Figure 14. Alternatively, if separate
anodes are available for the decimal pOints, they can be
wired up to the adjacent digit anodes. Note that there can be
one zero' to the left of the decimal point since the internal
leading zero blanking cannot be changed. In Figure 15 additional logic has been added to count the input directly in
period mode for maximum accuracy. In Figures 13 through 15,
INPUT A comes from Q c of the prescalerrather than Q D to ob·
tain an input duty cycle of 40%.

6·35

ICM7218
EXT.

DECIMAL
PT. ENABLE

'OOpF

*

EXT.

asc.

BLANK

DISPLAY

DISPLAY

TEST

39pF (TYP.)

10MHz

dp

0,

08

CRYSTAL

lN914'S

BBBBBBBB
0,

FIGURE 13. 100MHz Frequency Counter

DI

v+ v+

-=

3kn

dp

ICM
7216A

2'
20
'9
'8
'1
'6
'5

O.1~F

39pF

E@

3kn

28
21
26
25
24
23
22

DISPLAY
TEST

'Oka

TYP.
100kn

~

22Mn

lN914

01

0,
0,
03
04
Os

v+
Os

RANGE

07

0'0----+

08

10k.Q

10kn

FREQ,
PERIOD

COMMON ANODE LED DISPLAY

FREO. RATIO

02

LED
OVERfLOW

INDICATOR

rv

I

04

, 400

BBBBBBBB.
, 07

0,

FIGURE 14. 100MHz Multifunction Counter

6·36

ICM7216

3K~2

v+
v+

v+
10kn

-:

39pF
TYP.

IHOLDI
lQOkH

~

22Mn

D,
D,
D3
D4

lkn

D5

v+
D6

10kS2

07

RANGE

DB

0,

DEC. PT.

I

COMMON ANODE LED DISPLAY

I

0,

10k!2

lkn

04

I

04
40n

BBBBBBBB.
0,

LED OVERFLOW
INDICATOR

FIGURE 15. 100MHz Frequency, 2M Hz Period Counter

OSCILLATOR CONSIDERATIONS

The required Qm should not exceed 50% of the Qm specified
for the ICM7216 to insure reliable startup. The OSCillator IN·
PUT and OUTPUT pins each contribute about 5pF to Cin and
Couto For maximum stability of frequencY,Cin and Cout
should be approximately twice the specified crystal static
capacitance.
In cases where non decade prescalers are used It may oe
desirable to use a crystal which is neither 10 MHz or 1 MHz.
In that case both the multiplex rate and time between
measurements will be different. The multiplex rate is f mux
f
f
~ for 10 MHz mode and f mux ~ for the 1 MHz
2 X 10 3
2 x 10 4

The oscillator is a high gain complementary FET inverter. An
external resistor of 10MO to 22MO should be connected
between the OSCillator INPUT and OUTPUT to provide biasing. The oscillator is designed to work with a parallel resonant
10 MHz quartz crystal with a static capacitance of 22pF and a
series resistance of less than 35 ohms.

=

For a specific crystal and load capacitance, the required gm
can be calculated as follows:

=

CO) 2
gm = w 2 Cin Cout Rs ( 1+
CinCout
)
CL
(
where CL = Cin+Cout

.
x 106 . th e
mode. The time
between measuremen t 5 .15 2
~ In
10 MHz mode and 2 ~ 10 5 in the 1 MHz mode.

Co = Crystal Static Capacitance
Rs = Crystal Series Resistance
Cin = Input Capacitance
Cout = Output Capacitance
w = 2 ITf

osc

The crystal and oscillator components should be located as
close to the chip as practical to minimize pickup from other
signals. Coupling from the EXTERNAL OSCILLATOR INPUT
to the OSCILLATOR OUTPUT or INPUT can cause undesirable shifts in oscillator frequency.
6-37

ICM7216
20

F~EOUENCY

c~y

IA 1m,,)
UNIT
FREOUENCY RATIO MODES

15

~

10

fA (max) f8 (max) PERIOD,
TIME INTERVAL MODES

-

5

TA

--

=2S

Q

C

0

V' (VOLTS)

'A(ma.). 'a(ma.) as a Function 9'

v+

FIGURE 16. Typical Operating Characteristics

CHIP TOPOGRAPHIES

EXT

asc INPUT
esc INPUT

SEGb

OSC OUTPUT
SEG c
SEGf

RANGE INPUT

HOLD INPUT

INPUT A

AE'S"ETINPUT

CONTROL INPUT

INPUT B
Os

0,
FUNCTION INPUT

ICM7216B
ICM7216A

...::>

I!:::>
0

cEij

~
EXT OSC INPUT 1iiII=""'~
esc INPUT

ww

'"''

EXT DSC INPUT
osc INPUT

;.
seGb

osc OUTPUT

OSC OUTPUT

SEG c
SEGf

0,
0,

RANGE INPUT
EXT D.P. INPUT

HOLD INPUT

RANGE INPUT

HOLD INPUT

EXT D.P. INPUT

INPUT A

INPUT A

RESET INPUT

CONTROL INPUT
MEASUR·EMENT IN
PROGRESS

R'ESET INPUT

CONTROL INPUT
MEASUREMENT IN
PROGRESS

SEGI

Os

0,

SEGc

58

N

o:t

o c

ICM7216D

ICM7216C

6·38

0 In
ZO

'"

if

ICM7217 Series
ICM7227 Series
4-Digit CMOS
Up/Down Counter/
Display Driver
These circuits provide multiplexed 7 segment LED display
outputs, with common anode or common cathode configurations available. Digit and segment drivers are provided
to directly drive displays of up to .8" character height
(common anode) at a 25% duty cycle. The frequency of the
onboard multiplex oscillator may be controlled with a single
capacitor, or the oscillator may be allowed to free run.
Leading zeroes can be blanked. The data appearing at the 7
segment and BCD outputs is latched; the content of the
counter is transferred into the latches under external control
by means of the Store pin.

FEATURES
• Four decade, presettable up-down counter with
parallel zero detect
• Settable register with contents continuously
compared to counter
• Directly drives multiplexed 7 segment common
anode or common cathode LED displays
• On-board multiplex scan oscillator
• Schmitt trigger on count input
• TTL compatible BCD I/O port, carry/borrow, equal,
and zero outputs
• Display blank control for lower power operation;
quiescent power dissipation < SmW
• All terminals fully protected against static discharge
• Single SV supply operation

The ICM7217/7227 (common anode) and ICM7217 A17227 A
(common cathode) versions are decade counters, providing a
maximum count of 9999, while the ICM7217B, 72278
(common anode) and ICM7217C/7227C (common cathode)
are intended for timing purposes, providing a maximum
count of 5959.

DESCRIPTION

These circuits provide 3 main outputs; a CARRY IBORROW
output, which allows for direct cascading of counters, a
ZERO output, whicH indicates when the count is zero, and an
EQUAL output, which indicates when the count is equal to
the value contained in the register. Data is multiplexed to and
from the device by means of a three-state BCD 1/0 port. The
CARRY/BORROW, E'QUAi:., Z'E'RO outputs, and the BCD
port will each drive one standard TTL load.

The ICM7217 and ICM7227 are four digit, presettable up/
down counters, each with an onboard presettable register
continuously compared to the counter. The ICM7217
versions are intended for use in hardwired applications
where thumbwheel switches are used for loading data, and
simple SPOT switches are used for chip control. The
ICM7227 versions are for use in processor-based systems,
where presetting and control functions are performed under
processor control.

To permit operation in noisy environments and to prevent
multiple triggering with slowly changing inputs, the count
input is provided with a Schmitt trigger.

PIN CONFIGURATIONS (outline dwgs JI, PI)

Input frequency is guaranteed to 2 MHz, although the device
will typically run with fin as high as 5 MHz. Counting and
comparing (EQUAL output) will typically run 750 kHz maximum.

CARRY/SORROW

mill
I!OlJAL

BCD I/O 1'. 7

COUNT INPUT
STORE

ORDERING INFORMATION

,

COMMON ANODE
Display Option

Common
Common
Common
Common
Common
Common
Common
Common

SEGI

BCD 1108's
BCD 1/0 4'8
BCD 1101's
COUNT INPUT

BCD 1108's
BCC 1104's
BCD 1102's

7

o

SEG g
DISPLAY CONT.

COMMON CATHODE

6-39

Anode
Cathode
Anode
Cathode
Anode
Cathode
Anode
Cathode

Count Option
Max Count

28-LEAD
Package

Order
Part Number

Decade/9999
Decade/9999
Timer/5959
Timer/5959
Decad e/9999
Decade/9999
Timer/5959
Timer/5959

CERDIP
PLASTIC
CERDIP
I PLASTIC
CERDIP
PLASTIC
CERDIP
PLASTIC

ICM72171JI
ICM7217AIPI
ICM7217BIJI
ICM7217CIPI
ICM72271JI
ICM7227AIPI
ICM722-'BIJI
ICM7227CIPI

6

ICM7'217/.7227
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (commoll anode/Cerdip) ..... 1W Note 1
Power Dissipation (common cathode/Plastic) ... 0.5W Note 1
Supply Voltage V+ - V- ................................ 6V
Input Voltage
(any terminal) ....•....... V+ +0.3V, Ground -0.3V Note 2
Operating temperature range. , ............. _20° C to +85°C
Storage temperature range ............... _55° C to +125° C

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

OPERATING CHARACTERISTICS

v+ =

5V +10% TA = 25°C Test Circuit Display Diode Drop 1 7V unless otherwise specified
PARAMETER
SYMBOL
CONDITIONS
,+
Supply current
Display Off, LC, DC, UP/ON,
(72171
(Lowest power model
ST, RS, BCD I/O Floating or at V+ (Note 3)

Supply current
(Lowest power model

,+

Display off (Note 3)

TYP

MAX

350

500

"A

300

500

"A

S.5

mA
mA
V

(72271

Supply current
OPERATING

lop

Supply Voltage

V+

Digit Driver output
current

IDIG

Common anode, VOUT

SEGment driver
output curreni
Digit Driver
output current

ISEG

SEGment driver
output current
ST, RS, UP/DN input
pullup current

MIN

Common Anode, Display On, all "8's"
Common Cathode, Display On, all "8's"

UNITS

175
85
4.5

200
100

140

200

mA
peak

Common anode, VOUT = +1.3V

-25

-40

IDIG

Common cathode, VOUT = +1.3V

-7S

-100

mA
peak
mA
peak

ISEG

Common cathode VOUT = V+ -2V

10

12.S

mA
peak

Ip

VOUT = V+ -2V (See Note 3)

5

25

J.lA

100

kll

= V+

-2.0V

5

3 level input impedance

Z,N

BCD I/O input
high voltage

VSIH

BCD I/O input
low voltage

VSIL

BCD I/O input
pullup current

Ispu

ICM7217 common cathode Y,N = V+ -2V (Note 31

5

25

J.lA

BCD I/O input
pulldown current
BCD I/O. CARRY/BORROW,
ZERO, EQUAL Outputs
output high current
BCD 1/0, CARRY/BORROW,
ZERO, EQUAL Outputs
output low current

ISPD

ICM7217 common anode Y,N = +1.3V (Note 31

5

25

"A

ISOH

VOH = V+ -1.SV

100

"A

ISOL

VOL = +O.4V

-2

mA

Count input frequency
(Guaranteed)

fin

V+ = SV

Count input threshold

VTH

V+ = SV

2

V

Count input hysteresis

VHYS

V+ = SV

0.5

V

Display scan
oscillator frequency

Ids

Free-running (SCAN terminal open circuitl

2.5

kHz

Operating Temperature
Range

TA

Indu.strial temperature range

ICM7217
ICM7217
ICM7227
ICM7217
ICM7217
ICM7227

common anode (Note 41 (V+ =5.0V)
common cathode (Note 41
with SOpF effective load
common anode (Note 41 (V+ =5.0V)
common cathode (Note 41
with SOpF effective load

± 10%, -20°C 60",A A 1Ok!1 pull-up resistor to V+ on the
EQUAL or ZERO outputs is recommended for highest speed
operation, and on the CARRY/BORROW output when it is
being used for cascading.

OUTPUTS
The CARRY/BORROW output is a positive going pulse
occurring typically 500ns after the positive going edge of the
COUNT INPUT. It occurs when the counter is clocked from
9999 to 0000 when counting up and from 0000 to 9999 when
counting down. This output allows direct cascading of
counters.
The EQUAL output assumes a negative level when the contents of the counter and register are equal.
6·42

ICM7217/7227
MUX TYP MAX

SYMBOL DESCRIPTION
tucs
tUCh
tCUh
tCUI
tCB
tBw
tCEI
tCZI

UP/DOWN setup time (min)
UP/DOWN hold time (min)
COUNT pulse high (min)
COUNT pulse low (min)
COUNT to CARRY/
BORROW delay
CARRY/BORROW pulse
width
COUNT to EQUAL delay
COUNT to ZERO delay

UNITS

300
0
100 250
100 250
750

ns

100
500
300

Figure 5: ICM7217/27 COUNT and Output Timing
The Digit and SEGment drivers provide a decoded 7 segment
display system, capable of directly driving common anode
LED displays at typical peak currents of 40mA/seg. This
corresponds to average currents of 10mA/seg at a 25%
multiplex duty cycle. For the common cathode versions, peak
segment currents are 12.5mA, corresponding to average
segment currents of 3.1 mA. Figure 4 shows the multiplex
timing, while Figure 5 shows the Output Timing. Figures 6
through 9 show the output characteristics of the Digit and

300

80

l:~""""

ICM7217
ICM7217B
ICM7227
ICM7227B

80
TA '"' 25 C

60

200

IX\lOO\ IQ'I

se1

~~

se,

~ ~-

"

~

'\c

I

SC1,SC2lATCHES RESET
REGISTER WRITE CYCLE (Sel,Se2

1,0)

.-

-

IlDh

BCD IIC

~

~~

.{ se1

DATA OUTPUT CYCLE (Sel,Se2 '" 0,1)

se,
B~p

1,1)

(COUNTER WRITE CYCLE IS SIMILAR: sel, se2

~ ~
hOa-

~

-

I

I/Q

OUTPUT

- r-

r-

tTDf

--= DON'T CARE

*: CONTROL WORD INPUTS

Figure 13: ICM7227 I/O Timing (see Table 4)

CONTROL OF ICM7227 VERSIONS
The ICM7227 series has been designed to permit mi.:roprocessor control of the inputs. BCD inputs and outputs are
active high.

At the end of a data transfer operation, on the positive going
transition of the fourth DT pulse, the SC1 and SC2 control
latches will automatically reset, terminating the data transfer
and reconnecting the multiplex counter clock to the oscillator.
In the ICM7227 versions, the multiplex oscillator is always freerunning, except during a data transfer operation when it is
disabled.

In these versions, the STORE, UP/DOWN, SC1 and SC2 (Select
Code bits 1 and 2) pins form a four-bit control word input. A
negative-going pulse on the CWS (Control Word Strobe) pin
writes the data on these pins into four internal control latches,
and resets the multiplex counter in preparation for sequencing
a data transfer operation. The select code 00 is reserved for
changing the state of the Store and/or Up/Down latches
without initiating a data transfer. Writing a one into the Store
latch sets the latch and causes the data in the counter to be
transferred into the output latches, while writing a zero resets
the latches causing them to retain data and not be updated.
Similarly, writing a one into the Up/'DOwii 'atch causes the
counter to count up and writing a zero causes the counter to
count down. The state of the Store and Up/Down latches may
also be changed with a non-zero select code.

Fig. 13 shows the timing of data transfers initiated with a 11
select code (writing into the register) and a 01 select code
(reading out of the output latches). Typical times during which
data must be valid at the control word and BCD I/O ports are
indicated in Table 4.

Table 4: ICM7227 I/O Timing Requirements

Writing a nonzero select code initiates a data transfer
operation. Writing select code of 01 (SC1, SC2) indicates that
the data in the output latches will be active and enables the
BCD I/O port to output the data. Writing a select code of 11
indicates that the register will be preset, and a 10 indicates that
the counter will be preset.

SYMBOL DESCRIPTION
tcws
tiCs

tDrw

tscs
tSCh

When a nonzero select code is read, the clock of the four-state
multiplex counter is switched to the DATA TRANSFER pin.
Negative-going pulses at this pin then sequence a digit-bydigit data transfer, either outputting data or presetting the
counter or register as determined by the select code. The
output drivers of the BCD I/O port will be enabled only while
Dr is low during a data transfer initiated with a 01 select code.
The sequence of digits will be D4-D3-D2-D1, i.e. when outputting, the data from 04 will be valid during the first DT pulse,
then 03 will be valid during the second pulse, etc. When presetting, the data for 04 must be valid at the positive-going
transition (trailing edge) of the first DT pulse, the data for 03
must be valid during the second DT pulse, etc.

tlDs

t.Dh
troacc
tTOf

6-47

Control Word Strobe Width
(min)
Internal Control Set-up (min)
DATA TRANSFER pulse
width (min)
Contralto Strobe setu p (mi n)
Control to Strobe hold (min)
Input Data setup (min)
Input Data hold (min)
Output Data access
Output Transfer to Data float

MIN TYP MAX

UNITS

275

ns

2.5
300

300
300
300
300
300
300

3

I's
ns
ns
ns
ns
ns
ns
ns

.D~D(6

ICM7217/7227
APPLICATIONS
FIXED DECIMAL POINT

DRIVING LARGER DISPLAYS

In the common anode versions, a fixed decimal point may be
activated by connecting the b.p. segment lead from the
appropriate digit (with separate digit displays) through a 39!l
series resistor to Ground. With common cathode devices,
the D.P. segment lead should be connected through a 75!l
series resistor to V+.

For displays requiring more current than the ICL721717227
can provide, the circuits of Figure 15 can be used.

y+
ICM7217/B
ICM7227/B

To force the device to display leading zeroes after a fixed
decimal pOint, use a bipolar transistor and base resistor in a
configuration like that shown below with the resistor connected to the digit output driving th~ D.P. for left hand D.P.
displays, and to the next least signifi~ant digit output for right
hand D.P. display. See Figure 9 for a similarly operating
multi-digit connection.

(leM 7217 Ale)
(leM 7227 Ale)

4
DIGIT (SEG)

SEG (DIGIT)

-------1>-------y.

DISPLAY

CONTROL

Dn~B

DIGIT LINE

- - -

On
DIGIT
LINE

~

-I

ICM7217 Ale

GND

COMMON ANODE

COMMON CATHODE

Figure 14: Forcing Leading Zero Display

Figure 15: Driving High Current Displays

LCD DISPLAY INTERFACE (Figure 16)
The 10-20kO resistors on the switch BCD lines serve to isolate the switches during BCD output.

The low-power operation of the ICM7217 makes an LCD
interface desirable. The Intersil ICM7211 4 digit BCD to LCD
display driver easily interfaces to the ICM7217. Total system
power consumption is less than 5mW. System timing margins
can be improved by using capacitance to ground to slow down
the BCD lines. A similar circuit can be used to drive Vacuum
Fluorescent displays, with the ICM7235.

m

y+

=

y+ '" 5

5Y

L

..,.,.,..
LCD DISPLAY

04

37~4Q

•• ,.,.,•• r
28 SEGMENTS
AND BACKPLANE

-+

~
03

ICM7211

D.
01

~

34

--~-

33
3•
31
4
5
6
1

DB3 30

I

DB2 29
DBl 28
DBO

27

8,s
4',
2'.
1'.

~ ~

DC ~

ICM7217
IJI
COUNT 8
STORE 9
UP/DN 10
RESET 14

~110 ~

'4

y+

.A

~~ t.~

y y

110-' ~

-'~ ..

A -' ~ -' ~

~

~

Q

10-2DkH

Figure 16: LCD Display Interface (with Thumbwheel Switches)

6-48

••

01~

02

f26

g!~

1---

ICM7217/7227
UNIT COUNTER WITH BCD OUTPUTIFigure 17)

CARRY
ZERO

The simplest application of the ICM7217 is a 4 digit unit
counter. All that is required is an ICM7217, a power supply
and a 4 digit display. Add a momentary switch for reset, an
SPOT center-off switch to blank the display or view leading
zeroes, and one more SPOT switch for up/down control.
Using an ICM7217 A and a common-cathode calculator-type
display, results in the least expensive digital counter/display
system available.

BCD
OUTPUT

i'
'

COUNT INPUT 8

ICM
7217A

STORE

Figure 17: Unit Counter

INEXPENSIVE FREQUENCY COUNTER/
TACHOMETER (Figure 18)

300-500l's. The positive waveform time is given by twp = 0.693
(RA + RBI C while the negative waveform is given by tNn = 0.693
RBC. The s'ystem is calibrated by using a 5Mn potentiometer
for RA as a "coarse" control and a 1k potentiometer for RB as a
"fine" control. C040106B's are used as a monostable multivibrator and reset time delay.

This circuit uses the low power ICM7555 (CMOS 5551 to generate the gating, STORE and RESET signals. To provide the
gating signal, the timer is configured as an astable multivibrator, usi!1g RA, RB and C to provide an output that is positive for
approximately one second and negative for approximately

V+ ~ 5 VOLTS

3K

10K

24

9 __
v+

~~~---------1STORE

.047
ICM7217

lk

~_ _ _ _ _-18 COUNT
r':':';~---!--!-l_~

CV

14 RESET
GNO
20
GNO
INVERTERS: C040106B
NANOS: C04011B

COUNT INPUT 0 - - - - - - - - - - - '

r------

GATE

3OO

I

/--+50",
STORE

U

"S

'I'

I

1 SEC

( f

)I

f<

U

(f

"

RESET

Figure 18: Inexpensive Frequency Counter
6-49

ICM7217/7227
TAPE RECORDER POSITION INDICATORI
CONTROLLER (Figure 19)

the register can be set with the stop point and the EQUAL
output used to stop the recorder either on fast forward,. play
or rewind.

This circuit shows an application which uses the up/down
counting feature of the ICM7217 to keep track of tape
pOSition. This circuit is representative of the many
applications of' up/down counting in monitoring dimensional position. For example, an ICM7227 as a peripheral to a
processor can monitor the pOSition of a lathe bed or
digitizing head, transfer the data to the processor, drive
interrupts to the processor using the EQUAL or ZERO outputs, and serve as a numerical display for the processor.

To make the recorder stop before the tape comes free of the
reel on rewind, a leader should be used. Resetting the
counter at the starting point of the tape, a few feet from the
end of the leader, allows the ZERO output to be used to stop
the recorder on rewind, leaving the leader on the reel.
The 1M!1 resistor and .0047 /IF capacitor on the COUNT
INPUT provide a time constant of about 5ms to debounce the
reel switch. The Schmitt trigger on the COUNT INPUT of the
ICM7217 squares up the signal before applying it to the
counter. This technique may be used to debounce,switchclosure inputs in other applications.

In the tape recorder application, the LOAD REGISTER,
EQUAL ilnd ZERO outputs are used to control the r.ecorder
To make the recorder stop at a particular point on the tape,

LOGIC TO GENERATE

COMMON-CATHODE
LED DISPLAY

RECORDE;R CONTROL
SIGNALS

)

REEL SWITCH
CLOSED ONCE/REV

~~~~~====~~
4 DIGITS

Figure 19: Recorder Indicator

PRECISION ELAPSED TIME/COUNTDOWN
TIMER (Figure 20)

COUNTER terminal and Ground. This resistor pulls the
LOAD COUNTER input low when not loading, thereby inhibiting the BCD output drivers. This resistor should be eliminated and SW4 replaced with an SPOT center-off switch if the
BCD outputs are to be used. This technique may be used on
any 3-level input. The 1OOk pullup resistor on the count input
is used to ensure proper logic voltage swing from the
ICM7213. For a less expensive (and less accurate) timebase,
an ICM7555 timer may be used in a configuration like that
shown in Figure 18 to generate a 1Hz reference.

This circuit uses an ICM7213 preciSion one minute/one
·second timebase generator using a 4.1943 MHz crystal for
generating pulses counted by an ICM7217B. The thumbwheel switches allow a starting time to be entered into the
counter for a preset-countdown type timer, and allow the
register to be set for compare functions. For instance, to
make a 24-hour clock with BCD output the register can be
preset with 2400 and the EQUAL output used to reset the
counter. Note the 10k resistor connected between the LOAD

--I
EaUAL
ZERO

TO LOGIC GENERATING
SIGNALS FOR CONTROL OF
EXTERNAL EQUIPMENT

lOOK
STOP
14
13

leM 12
721311
10
9

SW1

RUN HRS/MIN

v+
(4 VOL T5 MAX)

4.1943 MHz
CRYSTAL

As < 750

v+ LOAD SET PT.
DISPLAY OFF

v+ PRESET
RESET

Figure 20: Precision Timer

6-50

\

.D~DIL

ICM7217/7227
MICROPROCESSOR INTERFACE-ICM7227
(Figure 21)

r-D'l
,.

OXQ-11

LXMAR
DEVSEL
INTGNT
IM610D

XTC

_P

C1
C,
SKP
INTREQ

~~

v+

~

f--I

"

a:-,)-o

CIUZ ...

:1""")(

~~!

III

u3~

li:

".

SENSE2

:!'mi

SENSE3

EQUAL

7i

+.

IM6l01
PIE

READ1
WRITE1
DXO-l1

CARRY/SORROW

SENSE1

- --

:::J

)--

1/4CD:""081

FLAG1ljQ;

WRITE2

BCD 1/0
ST ,U/D,SC1 ,SC2

4 DIGITS

1

-v+ID
U
U U

LED

DT

ICM7227

cws

ul

0 U
U

_v-

COUNT

J

DISPLAY

7 SEGMENTS

1/4 CD4081
COUNT

Figure 21: IM6100

This circuit shows the hardware necessary to interface the
ICM7227 to an IntersillM6100 CMOS microprocessor. Using
an IM6101 Parallel Interface Element (PIE) allows the
addition of one or more ICM7227 devices as generalized
peripherals to any IM6100 system, using a minimum of
external components.

The ICM7227 can perform many "accessory" functions that
are inefficient or impossible for the processor to perform. For
example, by adding a timebase such as an ICM7213, and
using an ICM7227C or 0, an inexpensive real-time clock/display, directly accessible by the processor, can be
constructed.

A similar configuration may be used with the MC6800 using
the corresponding PIE, while an 8255 can be used to
interface 8080 based systems.

6-51

D]
•

ICM721717227
8-DIGIT UP/DOWNCOUNTER (Figure 22)
This circuit shows how to cascade counters and retain
correct leading zero blanking. The NAND gate detects
whether a digit is active since one of the two segments or 6
is active on any unblanked number. The flip flop is clocked
by the least significant digit of the high order counter, and if
this digit is not blanked, the Q output of the flip flop goes high
and turns on the NPN transistor, thereby inhibiting leading
zero blanking on the low order counter.

It is possible to use separate thumbwheel switches for
presetting, but since the devices load data with the oscillator
free-running, the multiplexing of the two devi'ces is difficult
to synchronize. This presents no problems with the ICM7227
devices, since the two devices are operated as peripherals to
a processor.

a

[

'-,i ,-,

C/ C/

CQMMON-ANODE

,LED D,,'SPLAYS

- -'-'-L"
.../, '
L, '-'

, ,-, ,-, ,-,

C/,

~----

,I.....I '-' '-' '-'

COUNT INPUT

.~C;~;!!!~cl':~,g~pgU~l:,T:::-S_-+-II1\:r,2;:5.2i2.iH~DIGITS
HIGH ORDER DIGITS
4 4-7 tell' 24
0\+

CARRY/BORROW

4
DIGITS

25-28

7217

Figure 22: 8 Digit Up/Down Counter

-~--~-----~--,----------~-V+~5V
22pF

10kO

RESET 14

INPUT

Figure 23: Precision Frequency Counter (-1MHz Maximuml

6·52

7
SEGMENTS

ICM7217/7227
PRECISION FREQUENCY COUNTER/
TACHOMETER (Figure 23)
This circuit is a simple implementation of a four digit
frequency counter, using an ICM7207 A to provide the one
second gating window and the STORE and RESET signals. In
this configuration, the display reads hertz directly. With Pin 11
of the ICM7027A connected to V+, the gating time will be 0.1
second; this will display tens of hertz as the least significant
digit. For shorter gating times, an ICM7207 may be used (with a
6.5536 MHz crystal), giving a 0.01 second gating with Pin 11
connected to V+, and a 0.1 second gating with Pin 11 open.

number of holes drilled around i.ts edge to interrupt the light
from an LED to a photo-dector. For faster updating, use 0.1
second gating, and multiply the rotational frequency by 600.
For more "intelligent" instrumentation, the ICM7227 interfaced
to a microprocessor may be more convenient (see Figure 21 ).
For example, an ICM7207 A can be used with two ICM7227's to
provide an 8 digit, 2MHz frequency counter. Since the
ICM7207 A gating output has a 50% duty cycle, there is 1
second for the processor to respond to an interrupt, generated
by the negative going edge of this signal while it iflhibits the
count. The processor can respond to the interrupt using ROM
based subroutines, tostore the data, reset the counter, and
read the data into main memory. To add simultaneous period
display, the processor inverts the data and an ICM7218 Universal Display Driver stores and displays it.

To implement a four digit tachometer, the ICM7207A with
one second gating should be used. To get the display to read
directly in RPM, the rotational frequency of the object to be
measured must be multiplied by 60. This can be done electronically using a phase-locked loop, or mechanically by
using a disc rotating with the object with the appropriate

AUTO-TARE SYSTEM
This circuit uses the count-up and count-down functions of
the ICM7217, controlled via the EQUAL and ZERO outputs,
to count in SYNC with an ICL7109 AID Converter. By
RESETing the ICM7217 on a "tare" value conversion, and
STORE-ing the result of a true value conversion, an auto-

matic tare subtraction occurs in the result.
The ICM7217 stays in step with the ICL7019 by counting up
and down between 0 and 4095, for 8192 total counts, the same
number as the ICL7109 cycle. See A047for more details.

~
400mV
FULL SCALE
INPUT

~

°c

Q

~

......,~

~'~

,f

2 STATUS
3 POL

4 OR
S 812
6811
7810
BB9
g BB
10B7
1186
1285

1384
1483
1582
16 B1
17 TEST
18LBEN
19HBEN
[

v'

20CE/LOAO

REF IN·

40 !----SV

REF IN + 36
IN HI 35

P1MF

t:====t-t1_~'0K

IN La 34
COMMON
33
O.lJ.1F
INT 32 L---.J I 0.22 F
AZ31!
lIF"'"--t
aUF 30
REF OUT 29
47K
lOOK
Y-28
SEND 27 !--+5V

1-----:-'VVIr---'

4 DIGIT COMMON ANODE
LED DISPLAY

1'~._# LJ nl CI 1_
b F " I L/I 11_1

.. ,.

"":F-

5,'I"'N4_'_4B_ _ _'V'_ _ _ _

....:F--

DO 28

2 ZERO

0127

~

3 iR.iOA[

D226~

YHH---I

4 BCD 8

03251--

'---t--<"--t--I

5 BCD 4

l-....

6BCD2

------

7 BCD 1

v'

~-------t 9 STORE

'---;J------I10 UP/DOWN

241-~-+-'5V

DISP. CONT. 23
ICM7217

-::!:-

,~

1 CARRY/BORROW

S COUNT

1---...,

1----:7'7"----,

MINU~E~G~N~.,.-l....L.-'T'"""I..L..-,I-L-.,.-I....

'---I-H-+-+-+-+--I

t-

f=~~i~:7-1
II,

ICL7109

Q

.. ,.

f-

lOOK

391---+--1,

R~~FC~~:~:

DC 5 Q

±

Q

lGND

+5V

n

~

G22l--f-4
821l--f-4
V- 20

I---::

E19l--=-=--4
' 5 V - - ! t - - - 11 lOAD REG.
F1Sl---4
10!-,F
12 LOAD CTR.
17l---4
13 SCAN
16l---4
~-rr~--t.~14~R~ES!,!;Er.T_ _ _ _ _-"~1~5J---....J

L-.J 1100 FI
IIF"'-P- - - ,
OOSS~~~~~I-_ _r"I/'00",Krl

RUN/HOLD 26
BUFOSC OUT 25

OSCIN221---J---'
MODE 21 r-+5V

'--------------------------'

TARE

Figure 24: Auto-Tare System for AID Converter

6·53

ICM7217/7227
CHIP TOPOGRAPHY

BCD I/O 4
BCD I/O 2

I

O.
3.378

BCD I/O 1
COUNT I/P
STORE ISTORE)

in.

mm

0.133 in.
3.378 mm

BCD I/O 1
COUNT I/P
STORE ISTORE)

LO REG/i!ff ISCI)

LO REG/Off ISCII

ICM7217/B (ICM7227/B)

ICM7217A1C (ICM7227A/C)

6-54

ICM7218 Series
CMOS Universal 8 Digit
LED Driver System

FEATURES

The ICM7218A and ICM7218B are intended to be used
primarily in microprocessor systems, Data is read directly
from the 1/0 bus line from the microprocessor, 2 Control
lines (Write, and Mode) define chip select, which reads either
4 bits of control information (Data Coming, Shutdown,
Decode, Hexa or Code B Decoding) or 8 bits of Display Input
Data, Display Input Data (8 words, 8 bits each) is
automatically sequenced into the memory on successive
positive going Write pulses. Data may be displayed either
directly or decoded in Hexadecimal or Code B formats, The
ICM7218A drives a common anode display while the
ICM7218B drives a common cathode display, (See Block
Diagram 1)

• Total circuit integration on chip includes:
a) Digit and segment drivers
b) All multiplex scan circuitry
c) 8X8 static memory
d) 7 segment Hexadecimal and Code B decoders
• Output drive suitable for large LED displays
• Both common anode and common cathode LED
drive versions
• Single 5 volt supply required
• Data retention to 2 volts supply
• Shutdown feature - turns off display and puts chip
into very low power dissipation mode
'
• Pin selectable choice of 2 seven segment decodersHexa or Code B - or no decode
• Microprocessor compatible
• Serial and random access versions
• Decimal point drive on each digit

The ICM7218C and ICM7218D feature 2 lines for control
information (Write, Three Level Input; Hexa, Code B,
Shutdown), 4 lines for Input Data and 3 lines for Data
Addressing of each of eight data memory locations,
Data is written into memory by setting up a Data Address
memory location, defining 4 lines of Input Data and then
strobe the Write line low, The Three Level Control Input is
independent of the Write instruction. Only Hexadecimal and
Code B decoding are available for the Display Outputs, The
ICM7218C drives a common anode display, the ICM7218D a
common cathode display, (See Block Diagram 2)

GENERAL DESCRIPTION
The ICM7218 series of universal LED driver systems provide,
in a single package, all the circuitry necessary to interface
most common microprocessors or digital systems and
an LED display, Included on chip is an 8x8 static memory
array providing storage for the displayed information, 2
types of 7 segment decoders, all the multiplex scan circuitry
and the high power digit and segment drivers,

The ICM7218E provides 4 separate lines for control
information (Write, Hexa-Code B, Decode, Shutdown), 8
lines for input data, and 3 lines for digit address, Data is
written into the memory by setting up a Data Address
memory location, defining 8 lines of Input Data, and then
strobe the Write line low, Control information is on separate
lines and is independent of the Write instruction, Data may
be displayed either directly or decoded in Hexadecimal or
Code B formats, The ICM7218E drives a common anode
display. (See Block Diagram 3)

ORDERING INFORMATION
Order
Part Number
ICM7218A IJI
Serial Access
ICM7218B IPI
Random Access ICM7218C IJI
ICM7218D IPI
ICM7218E IDL

Typical
App.

Display
Option
Common
Common
Common
Common
Common

Anode
Cathode
Anode
Cathode
Anode

Package
28 Lead CERDIP
28 Lead Plastic
28 Lead CERDIP
28 Lead Plastic
40 Lead Ceramic

PIN CONFIGURATION

(OUTLINE DRAWING JI)

ICM7218A
COMMON ANODE

CHIP TOPOGRAPHY ICM7218A

Seg C 1
Seg e 2
Seg b 3

Mode

D"P" 4
106 (!-lEXA/CODE B)LS
105 (-DECODE) 6
107 (DATA COMING) -7
WRITE[s
MOOE[9
104 (SHUTDOWN)L.!£
1011_1
IOO!""i"2
102 t~-3

wrrre

103r1~

04

07
.102 inch
2.59 mm
06

03

107 (Data Coming)

SEGI

-"'="""=""'==......==~

TOP VIEW

105 (ilecode)

t40te: Pins 5, 6, 7, 10 are under control

106 (Hexa/coaeB)

SEGd SeGg GND seGc
SEGb
SEG.
SEGe
DECIMAL

I~~ _ _ ,137 inch

'--_---I

l.?;OIGIT 5
~~l DIGIT 2
"i5)OIGIT 1

of Mode pin 9. See page 6-60.

POINT

See page 6·57 for other device configurations.

3.46mm

6·55

D]
.

•

.D~DI1.

ICM7218 SERIES
ABSOLUTE MAXIMUM RATINGS

Supply Voltage ...............................•.............................. 6V
Digit Output Current ...............................................•..... 300mA
Segment Output Current .................................................. 50mA
InputVoltage(anyterminall .................................. V"'+0.3V to V--o.3V
NOTE 1
Power Dissipation (28 Pin CERDIP) ................................ 1 W NOTE 2
Power Dissipation (28 Pin Plastic) ................................ 0.5 W NOTE 2
Power Dissipation (40 Pin Ceramic) ................................ 1 W NOTE 2
Operating Temperature Range ..•................................. -20°C to +85°C
StoraQe Temperature Range ..................................... -55° C to +125° C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE 1: Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater
than V+ or less than GROUND may cause destructive device latchup. For this reason it is recommended that no inputs from sources
operating on a different power supply be applied to the device before its own supply is established, and when using multiple supply
systems the supply to the ICM7218 should be turned on first.
NOTE 2: These limits refer to the package and will not be obtained during normal operation. Derate above 50°C by 25mW per °C.

SYSTEM ELECTRICAL CHARACTERISTICS v+ = 5V ±10%;
PARAMETER
Operating Voltage
Quiescent Supply Current
Operating Supply Current
Digit Drive Current
Digit Leakage Current
Peak Segment Drive Current
Segment Leakage Current
Display Scan Rate
Three Level Input
Logical "1" Input Voltage
Floating Input
Logical "0" Input Voltage
Three Level Input Impedance
Logical "1" Input Voltage
Logical "0" Input Voltage
Write Pulse Width (Negative)
Write Pulse Width (Positive)
Write Pulse Width (Negative)
Write Pulse Width (Positive)
Mode Hold Time
Mode Pulse Width
Data Set Up Time
Data Hold Time
Digit Address Set Up Time
Digit Address Hold Time
Data Input Impedance

SYMBOL

TA

= 25°C, Test Circuit,

CONDITIONS

V+

10
lop
IDIG

Power Down Mode
Shutdown (Note 3)
Decoder On, Outpl!'\s Open Ckt
No Decode, Outputs Open Ckt
Common Anode You! - V+ -2.0
Common Cathode Vout = V- +1V

Display Diode Drop 1.7V

MIN
4
2
6
250
200
-170
50

TYP

20
-10

25

10

ID'LK
ISEG

MAX
6
6
300
950
450

100
Common Anode Vout = V- +1.5V
Common Cathode Vout = V+ -2.0V

ISLK

50
250

fMUX

Per Digit

VINH
VINF
VINL

Hexidecimal ICM7218C,D IPin 9)
Code B ICM7218C, 0 (Pin 9)
Shutdown ICM7218C, 0 (Pin 9)

ZIN
VIH
VIL
tw
tiN
tw
tiN

Note 3

250
250

V
V
V
kf1
V
V
ns
ns
ns
ns

150

ns

4.0
2.0

3.0
1.75
100

3.5
.8

\7218C, 0, E

' tmh

7218A,B

tm

7218A, B

Ids
tdh
tdas
tdah

ICM7218C, D, E
ICM7218C, D, E

ZIN

5-10 pF Gate Capacitance

400
400

550
550
400
400

\7218A, B

:

500
500

--

ns
ns
ns
ns
ns

25
500
100

.

UNITS
V
V
jJ.A
jJ.A
jJ.A
mA
mA
jJ.A
mA
mA
jJ.A
Hz

1010

Ohms

NOTE 3: In the ICM7218C ano D Irandom access versions) the Hexa/Code B/Shutdown Input IPin 91 has internal biasing resistors to hold it at
y. /2 when Pin 9 is open circuited These resistors consume power and result in a Quiescent Supply Current 1101 of typically 50~A,The
ICM7218A, B, and E devices do not have these biasing resistors and thus are not subject to this condition,

6-56

ICM7218 SERIES
BLOCK DIAGRAMS
ICM7218E

ICM7218C,ICM7218D

ICM7218A,ICM7218B

HEXADECIMALI

coDe B

100·103
HEXADECIMALI
107
CODe B/
DATA

iiiiJTDOiiiN

INPUT

WRITE

DAD-CA2
DIGIT
ADDRESS

0)
PIN CONFIGURATIONS (See page 6·65 for ICM7218A)
ICM7218C (OUTLINE DRAWING JI)

ICM7218B* (OUTLINE DRAWING PI)
COMMON CATHODE

OlGIT41
DIGIT 6 2
DIGIT3 :I
0lGIT1 4
106 (HEXA/~) 5
105 (DEC"OIl!) 6
107 (DATA COMING) 7
WRITE 8
MODE 9

GOMMON ANODE

Seg C 1
Seg e 2:
Seg b 3
D.P. 4
DAD (DIGIT ADDRESS 0) 5
DA1 (DIGIT ADDRESS 1) 6
107 (INPUT DJi.) 7

WRITE 8
20 DIGIT 4
19 y+
18 DIGIT 8
17 DIGIT 5
16 DIGIT 2
15010lT1

HEXA/CODE a/SHUTDOWN 9
CA2 (DIGIT ADDRESS 2) 10

104 (SHUTDOWN) 10

10111

TOP VIEW

TOP VIEW

*Note: Pins 5, 6, 7, 10 are under control

ICM7218E (OUTLINE DRAWING DL)

of Mode pin 9. See page 6·60.

COMMON ANODE

ICM7218D (OUTLINE DRAWING PI)
COMMON CATHODE
28
27
26
25
24
23

GROUND
DIGIT 7
DIGIT 5
DIGIT 2
DIGIT 8
Seg 9
22 Seg t
21 Seg e
20 Seg C

19 v+
18 Sag d
17 Seg b
16 Seg a
1S D.P.

TOP VIEW

6·57

ICM7218 SERIES
INPUT DEFINITIONS ICM7218A and B
INPUT
WRITE

TERMINAL
8

MODE

9

ID4SHUTDOWN

10

105 (DECODE/No Decode)

6

MODE
High

106 (HEXAdecimal/CODE B)
107 (DATA COMINGControl Word)
Input Data

5
7

MODE
Low

100-107*

High
Low
High
Low
High
Low
High

FUNCTION
Input Not Loaded Into Memory
Input Loaded Into Memory
Load Control Word on Write Pulse
Load Input Data on Write Pulse
Normal Operation
Shut90wn (Oscillator, Dec6der, and Displays
Disabled)
No Decode
Decode
Hexadecimal Decoding
Code B Decoding
Data Coming
}
Control Word
No Data Coming
Loads "One" (Note 2)

Low

Loads "Zero" (Note 2)

VOLTAGE
High
Low
High
Low
High
Low

11,12,13,
14,5,6
10,7

...

'100-103 ~ Don't care when writing control word
104-107 ~ Don't care when writing Hex/Code B
(The display blanks on ICM7218A/B versions when writing in Datal

INPUT DEFINITIONS ICM7218C and D
INPUT
WRITE
Three Level Input (Note 1)

OJ

High
Low
High

FUNCTION
Inputs Not Loaded Into Memory
Inputs Loaded Into Memory
Hexadecimal Decode
Code B Decode
Shutdown (Oscillator, Decoder and Displays
Disabled)
Loads "Ones"
Loads "Zeros"
Loads "O,"!!lS" (Note 2)

7

Low

Loads "Zeros" (Note 2)

TERMINAL
9

VOLTAGE
High
Low
High
Low

TERMINAL
8
9

Digit Address
DA2 (MSB)-DAO (LSB)
Input Data 103 (MSB) - 100
107

VOLTAGE
High
LoW
High
Floating
Low

.
= Data

= D.P.

10,6,5
14,13,11,12

INPUT DEFINITIONS ICM7218E
INPUT
WRITE
SHUTDOWN

10

Digit Address (0,1,2)
DAO-DA2
DECODE/No Decode
HEXAdecimal/CODE B
Input Data

13,14,12
33
32
16,17,18,19
6
7,11,8

100-107

High
Low
High
Low
High
Low
High

FUNCTION
Input Latches Not Updated
Input Latches Updated
Normal Operation
Shutdown (Oscillator, Decoder and Displays
Disabled)
Loads "Ones"
Loads "Zeros"
No Decode
Decode
Code B Decoding
Hexadecimal Decoding
Loads "Ones" (Note 2)

Low

Loads "Zeros" (Note 2)

NOTE 1 In the ICM7218C and ICM7218D versions, Hexadecimal, Code B anu .,,,utdown are controlled with a three level input on Pin 9. Pulling
Pin 9 high decodes Hexadecimal. Floating Pin 9 decodes Code B and pulling Pin 9 low puts the ICM7218 in a Shutdown mode.
NOTE 2 In the No Decode fofmat, "Ones" represents "on" segments for all inputs except for the Decimal Point, where "Zero" represents "on"

segments, (i.e.

segme~ts

are positive true, decimal point is negative truel.
6-58

ICM7218 SERIES
INTERNAL CSC.
OUTPUT

~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

02

~~IT--.L-A-NK------------------------------~---------------------

.,

r___lL___________________________________
____________________
_______________________

01

~r__l~

07
EXTERNAL

__________________________

o.

~r___l~

_________________

06

________________________________

04

____________________________________

0'

____________________________

~r__l~

___________

~r__l~

_____

----------~r---

Figure 1: Multiplex Timing

.

SHUTDOWN
SHUTDOWN performs several functions: it puts the device
into a very low dissipation mode (typically 10!-,A at V+ = 5)',
turns off both the digit and segment drivers, stops the multiplex sca.n. oscillator (thisistheonlywaythescanoscillatorcan
be disabled). However, it is still possible to input data to the
memory during shutdown - only the output and read sections
of the device are disabled.

'/-:-Ib

./--/-

_._ eo.p.

Figure 2: Segment Assignments

Powerdown
In a Shutdown Mode, the supply voltage may be reduced to 2
volts without data being lost in memory. However, data
should not be written into memory if the supply voltage is
less than 4 volts.

DECODE/No Decode
For the ICM7218A/B/E products, there are 3 input data
formats possible; either direct segment and decimal pOint
information (8 bits per digit) or 2 Binary codes plus decimal
point (5 bits per digitI. The 7 segment decoder on chip may be
disabled if direct segment information is inputted.

Output Drive
The common anode output drive is approximately 200 mA
per digit at a 12% duty cycle. With 5 segments being driven,
this is equal to about 40mA per segment peak drive or 5mA
average drive. The common cathode drive is approximately
one half that ofthe common anode drive. If high impedance
LED displays are used, the d rive will be correspond i ng Iy less.

In the No Decode format, the inputs directly control the
outputs as follows:
Input Data:

107 106 105 104 103 102 101 100

Output Segments:

D.P. a b c

e

g

f

d

Inter Digit Blanking
A blankir,g time of approximately lOllS occurs between digit
strobes to ensure that segment information is correct before
the next digit drive thereby avoiding ghosting.

In this format, "Ones" represents on segments for all inputs
except for the Decimal Point, where "zero' represents on
segments.
HEXAdecimal or CODE B Decoding
For all products, a choice of either HEXA or Code B decoding
may be made, HEXA decoding provides 7 segment numeric
plus six alpha characters while Code B provides a negative
sign (-i, a blank (for leading zero blanking), certain useful
alpha characters and all numeric formats.
The four bit binary code is set up on inouts 103-100.

Leading Zero Blanking
This may be programmed into chip memory in the nodecode operation (each segment programmed for a zero for
the blanked digits) or by using the 16th state (binary 151 with
the Code B decoder.

BinaryCode 0 1 2 3 4 5 6 7 8 91011 12131415

,-, ,, ,:

Hexa Code u
Code B

-'-'

'-:

,- -,,
c..J CI

:::

,-, , ::' ::; , ,- ,- ..,, CI
'-' , '- -' '-' J 0::;
'-'

'-J
..J
0.:>
..J

'..J

I,

,- , ,- ,b '- 0 c ,-

- ,-c :i '-,

:=1 IBlank)
6-59

Driving Larger Displays
If a higher average drive current per digit is required, it is
possible to parallel connect digit drives together. For
example, by paralleling pairs of digit drives together to drive
a 4 digit display 10 mA average segment drive can be
obtained.

a
~

•

ICM7218 SERIES
APPLICATIONS, continued

ignored. It is not possible to change one individual digit
without refreshing the data for all the other digits, (This can,
however, be achieved with the ICM7218C/D/E where the
digits are individually addressedJ

Power Dissipation Considerations
Assuming common anode drive at V'-= 5volts and all digits
on with an average of 5 segments driven per digit, the
average current would be approximately 200mA. Assuming a
1.8 volt drop across the LED display, there will be a 3.2 volt
drop across the ICM7218. The device power dissipation will,
therefore, be 640mW rising to about 900mW for all '8"s
displayed. Caution: Position device in system such that air
can flow freely to provide maximum cooling. The common
cathode dissipation Is approximately one half that of the
common anode dissipation.

Random Access Input Drive Considerations
(ICM7218C/D/E)
Control instructions are provided to the ICM7218C/D by a
Single, three level input terminal (Pin 9), which operates
independently of the WRITE pulse. The ICM7218E control
instructions are also independent but are on three separate
pins (10, 32, 33>Data can be written into memory on the ICM7218C/D/E by
setting up a 3 bit binary code (one of eight) on the digit
address inputs (which define the digit where the data is to be
written into the memory) and apply a negative going WRITE
pulse. For example, it is possible to change only digit 7
without refreshing the data for all the other digits. (However,
this cannot be achieved with the ICM7218A/BJ

Serial Input Drive Considerations (ICM7218A/B)
The control instructions are read from the input bus lines if
MODE is high and WRITE low. The instructions occur on 4
lines and are- Decode/no Decode, type of Decode (if desired).
SHUTDOWN/no Shutdown and DATA COMING/not Coming. After the control instructions have been read (with Data
Coming instruction) display data can be written into memory
with each following negative going pulse of WRITE, MODE
being low. After all 8 words or digit memory locations have
been written, additional transitions of the state of WRITE are

Supply Capacitor
A 0.1j.LF capacitor is recommended between V+ and
GROUND to bypass multiplex noise.

SWITCHING WAVEFORMS ICM7218

~=:-;;===i;=~~~==~~-

MODE

INPUT DATA

DIGIT ADDRESS

7218A,8 ONLY

~~I~~,
~

7218C,D,E ONLY

~

1 = CONTROL WORD·
0= DATA WORD
'" DON'T CARE

YlIUTE '" LEVEL SENSITIVE, NOT EDGE SENSITIVE
~KEEP

MODE FROZEN THROUGHOUT
8 DATA· WORD WRITE SeQUENCE,

Figure 3

CHIP ADDRESS SEQUENCE ICM7218Aand B'
MOO'

.Jl,---..,--.~

_ _ _ _ _fL
DON'TeARE

(08)

(01)

CONTROL WORD
TYPE OF DECODER? 106
DECODE/NO DECODE? 105
SHUTDOWN? 104
DATA COMING 107

\
CONTROL WORD
TYPE OF DECODER? 106
DECODE/NO DECODE11DS
SHUTDOWN? 104
DATA NOT COMING 107

Figure 4

CHIP ADDRESS SEQUENCE EXAMPLE ICM7218C/D/E

~
DON'T CARE

DECODE·NO DECODE,
SH'iJfi5"OWN AND HEXADECIMAL-CODE BARE
INDEPENDENT OF THE WRITE PULSE
(ICM7218C/D/E ONLY) AND MAY BE CHANGED
ANYTIME BY APPLYING THE APPROPRIATE INPUT
LOGIC STATE.

Figure 5

6·60

ICM7218 SERIES
TEST CIRCUITS
TEST CIRCUIT 1

~r.v-~
,
"

~'26

3

~
HEXA-CODE 8/106 5

25

~

is

DECODE/IDS
DATA COMING/ID7 7
1
,
MODE ~
SHUTOOWN/ID4 10

ICM7218A

"
"
"
@,l¥

101 11

,

-!-+

\

)

)

~

~
17

\\\~

16

me

v+

-:-SV

O.1.uF

T-

v08 07

06 05

04 D3

02 01

'-W~ili_~L~O.j

1d-

:==-

'-i.jH.j,I-l.1
U. '-~ U. U. U. U.
U. U. ~b

COMMON ANODE
DISPLAY

D.P.

TEST CIRCUIT 2

~r.V-w-~-t--_ _-----,

~

r__;===================~DI~G~ITjA~D~~~RE~S~S~O~:
DIGIT ADDRESS 1 6
107 (D.P.)

1

~~~6--r----------------1r-1-~

~'®5==t=========~---24

ICM7218D

WRITh 8
HEXAICODE B/SHUTDOWN 9
DIGIT ADDRESS 2 10

~23

F,ji.

"
"
"

19

101 11

17

16
15

-:-+

v+

T-

v-

I"

fllil

f

08 07

06 05

04

D3

02 01

~ lululr ilolr~rlululo'

-=-SV

~

I'_'·IU·ICI·IU·IU·IU·IU·IU...

~.P.

COMMD~~P~:~HODE

TYPICAL CHARACTERISTICS
COMMON ANODE
SEG. DRIVER
ISEG vs. VOUT
AT 25°C

COMMON ANODE
SEG. DRIVER
ISEG. VS. VOUT

COMMON ANODE
DIGIT DRIVER
IDIG VS. (V+ -VOUT)

300 r-----,-----..,--""7,l'"

80r-----,-----~_.,20~·C~,,~

y

.-

~30r-----,,~~-t-----1

.-S

$

.il

200

0

'DO

,s~~~+-----_t----~

VOUl (VOLTS)

Your (VOLTS)

6-61

ICM7218 SERIES
TYPICAL CHARACTERISTICS, CONTINUED
COMMON CATHODE
DIGIT DRIVER
IOIG VS.

COMMON CATHODE
SEG. DRIVER

Vour

AT 25°C

ISEG

COMMON CATHODE
DIGIT DRIVER

va. (V+ -Vour)

IOIG VB. Vour
'011 ......--r----r-~-,

200 , - - - - - - , - - - - - , - - - - - ,

1
§

100 r--~~~-+--~
10

f------,--j-+---il--:--:-l.

y+ -Your (VOLTS)

Your (YOLTS)

Your (VOLTS)

APPLICATION EXAMPLES
8 DIGIT MICROPROCESSOR DISPLAY
APPLICATION
The display interface (ICM7218) is shown with an MCS-48
family microprocessor. The 8 bit data bus DBO/DB7-IDO/ID7
transfers control and data information to the 7218 display
interface on successive WRITE pulses. When MODE is high a
control word is transferred. MODE low allows data transfer on
a WRITE pulse. Eight memory address locations in the 8 x 8
static memory are automatically sequenced on each succes-

,

r

, I I I

'-'.

L/.
l

r

sive WRITE pulse. After eight WRITE pulses have occurred,
further pul5es are ignored and the display interface returns
to normal display operation· until a new control word is
transferred. See Figure 4. This also allows writing to other
peripheral .devices without disturbing the ICM7218 AlB.
,Oecoding of the stored data in memory is defined by the
control word and may be decoded in Hexadecimal, Code B,
or No-Decode formats.

I

,

,

,-, '-' 1-'I
L/. ,_'. L/. _. ,_'. I ,.

,-,
'-'
1

1

I ,
J

,~

J

T~~2.Io

Vee
II

"::l::

D
.. T

•
3

"

..

•

II

7

VDD

Vss

l.

Vss

J.

I

XTAL2

~

8 DIGITS

tM-

RESET

EA

P20 ~
P.,
P•• ~
P23 ~
P•• 3S
P2S
P2.
P.7

IM80C3S
IM80C48
8048
8050
8748
ETC.

?

ICM7218A18

~

fe-

9 MODE

12 100

DBO 12

11 101

DBl 14

~

GND

Voo

Ne....! !is

-[~
.2!

+sv

P10
P11
P1.
P13
P1.
P1S 3.
P1.
P17

XTAL1

~.

INPUT

j

J

T1

DB2
DB3
DB4
DBS

15
16
11
18

jjjj'

~:~

19

TO

ALE PSEN PROG WR

r' ,"

,25

['0

13 102
14 103
10, 104

• IDS

5 106
7 107

WIt

lID

J

,.

·Figure 6: 8 Digit Microproqessor Display

6·62

.,

8S,?GMENTS

ICM7218 SERIES
16 DIGIT MICROPROCESSOR DISPLAY
APPLICATION
Both ICM7218's are addressed simultaneously with a 3 bit
word, OA2-0AO.

Oecimal point information (from the processor, P26-P27) is
supplied to the ICM7218 on bus lines 1D7 to both devices.

Oisplay data from the MCS-48 1/0 bus (OB7-0BO) is
transferred to both ICM7218 (103-100) simultaneously,
4 bits + 4 bits on WRITE enable.

Choice of decoding is available in either Hexadecimal or
Code-B format by hardwiring or decoding to a Three Level
format on Pin 9 of the ICM7218.

Oisplay digits from both ICM7218's are interleaved to allow
adjacent pairs of digits to be loaded sequentially on a single 8
bit data bus, ie 00 01, 02 03, 04 05, etc ..

Multiplexing is asynchronous with respect to the microprocessor and is completely performed by the ICM7218.

I

8

: :.1: 1.1: 1.\/ :'\11.\: :.\: :.\: :.\: :.\: 1.\11. I_I.
I " \'L/.'.\',_'.'.\'L/.'\'L/.'\
01.

015

013

014

012

011

010

08

D.

07

06

OS

D.

03

02

1

01
8

8

+SV!.1.

+5Vho--. GND!:
40

Vee
2

":::!::

~3

•

II

"

20

V5S

RESET

f!!-

~

EA
"::"

NC-! SO

P20
P21
P22
P23
P2.
P'S
P'.
P'7

IM80C35
IM80C48
8048
8050
8748
ETC.

4~
37
38

,.

TO
3"
-.:,; T1

~

fN'f
ALE PSEN PROG WR

I" I"

125

1"

: DAO

10

g:~

DIGITS

-

DIGITS

-

SEGMENTS

-

SEGMENTS

-

S

ICM7218C/D

•

10

DAO
DA1
DA'

ICM7218C/D

~

12
DBO
13
DB1
DB2
1S
DB3
DB. ~
H
DBS
DB.
DB7 .!L

t~

,...!

21
22
23

28

Vss

l

XTAL2

V-I

V+I,
1.

8

28

VDD

27
P10
P"
P12
P13 ~
P1.
32
P1S
P16
P17 l L

XTAL1

7

INPUT

26

VDD

GNDI:

7

7 107 (DEC. PT.)

12

~~ 100
13 101
14 102
103

-:=:=tt"13

Vi- ---1 THREE

v+.-!

LEVEL

WA

liD

r

18

107 (DEC. PT.)

100
1D1
10'
103

THREE
LEVEL

-

WR

r

Figure 7: 16 Digit Display

NO DECODE APPLICATION
The ICM7218 can be used as a microprocessor based LEO
status panel driver. The microprocessor selected control
word would include "No Decode" and "Oata Coming". The
computer then outputs word oriented "Ones" and "Zeroes"
to indicate on-off states. This data is read into the ICM7218
which in turn directly drives appropriate discrete LEOs. LEO
indicators can be red or green (8 "segments" x 8 digits = 64
dots + 2 per red orgreen=32channels). With red, yellow and
green, 21 channels can be accommodated.

Additional ICM7218's may be bussed and addressed (see
Figures 6 and 7) to expand the status panel capacity. Note per
figure 4 that after.the ICM7218A/B has been read in its data (8
WRITE pulses), it ignores additional information on the data
lines. A new control word must be received before the next
write sequence can be accommodated. Consequently, by
address decoding and WRITE pulse enabling, numerous
ICM7218's can be bussed together to allow alarge numberof
indicator channels.
6·63

ICM7224 (LCD)
ICM7225 (LED)
4 Y2-Digit CounterI

DecoderI Drivers
FEATURES
• High frequency counting-guaranteed 15MHz,
typically 25M Hz at 5V
• Low power operation-less than 100l'W quiescent
• STORE and RESET inputs permit operation as
frequency or period counter
• True COUNT INHIBIT disables first counter stage
• CARRY output for cascading four-digit blocks
• Schmitt-trigger on the COUNT input allows
operation in noisy environments or with slowly
changing inputs
• Leading Zero Blanking INput and OUTput for
correct leading zero blanking with cascaded
devices
• LCD devices provide complete onboard oscillator
and divider chain to generate backplane
frequency, or backplane driver may be disabled
allowing segments to be slaved to a master
backplane signal
• LED devices provide BRighTness input which can
function digitally as a display enable or with a
single potentiometer as a continuous display
brightness control

GENERAL DESCRIPTION
The ICM7224 and ICM7225 devices constitute a family of
high-performance CMOS 4 1f2-digit counters, including
decoders, output latches, display drivers, count inhibit,
leading zero blanking, and reset circuitry.
The counter section provides direct static counting, guaranteed, from DC to 15 MHz, using a 5V ±10% supply over the
operating temperature range. At normal ambient temperatures, the devices will typically count up to 25 MHz. The
COUNT input is provided with a Schmitt trigger to allow
operation in noisy environments and correct counting with
slowly changing inputs. These devices also provide count
inhibit, store and reset circuitry, which allow a direct interface with the ICM7207!A to implement a low cost, low power
frequency counter with a minimum component count.
These devices also incorporate several features intended to
simplify cascading four-digit blocks. The CARRY output
allows the counter to be cascaded, while the Leading Zero
Blanking INput and OUTput allows correct Leading Zero
Blanking between four-decade blocks. The BackPlane driver
of the LCD devices'may be disabled, allowing the segments
to.be slaved to another backplane signal, necessary when us·
ing an eight or twelve di.git, single backplane display. In LED
systems, the BRighTness input to several ICM7225 devices
may be ganged to one potentiometer.
The ICM7224!ICM7225 family are packaged in a standard
40-pin dual-in-line plastic package.

TYPICAL APPLICATION (UNIT COUNTER)

PIN CONFIGURATION (outline dwg PL)

COUNT 32
COUNT INHIBIT 31 ...--_....P"'AU'"'S'"E-
..J
(BLANK)

6-69

ICM7224/1CM7225
APPLICATIONS
1. Two-Hour Precision Timer

4V,·DIGIT LCD DISPLAY

0
IBBS
__ l · U

GND35~~-------+-,

~34

5 BP

RESET 33
COUNT32~--~~~~

COUNT INHIBIT 31
LZB OUT 30
LZBIN 29
CARRY2S
'----------------12,3,4
Z9 SEGMENTS
6-27
'-----------------oi 37-40

ICM7224A

2. Eight-Digit Precision Frequency Counter
LOW ORDER DIGITS

HIGH ORDER DIGITS

OOOOfOOOO
- Ll
Ll Ll LIlLI Ll Ll Ll
I
J

OVERFLOW 1

m

I

I I I

I I

I

I

I

I

II

2.
ICM7224
HIGH ORDER DIGITS
MASTER BACKPLANE
LZ LZ
BI 80

CY

II

Ei

27 2. 29 30 31

21

I

I

I I

III

+

I

I

CNT

AS Sf GND

CSC

32 33 34 35 36

I

SEGMENTS

rtll1, f-

5
BP

'j

4 SEGMENTS

r~ BACKPLANE

6 •

SEGMENTS 3
4
15
SEGMENTS
SEGMENTS

6 SEGMENTS

8 DIGIT LCD DISPLAY
WITH OVERFLOW

I I

SEGMENTS

I

I I

I I

I I

I I II

I I

-hsEGiE~

5
BP

2.

ICM722'
LOW ORDER DIGITS
MASTER BACKPLANE

LZ LZ

CY

4.

1111 L" I__

I I

BI BO

Ci

27 28 29 30 31

21

I

I I

III

CNT

AS Sf GND asc

32 33 34 35 36

III

III

I I

~

~~~fr.HG CiE':tSJ~L~~~~~ '1'

v

+ ~13...fiV

_

-

13

3
4

12 SWITCH OPEN 1 SEC GATING
11 ~$WITCHCLOSEDO.1-SECGATING
,.

5

-7

CIN

.....

2

-1D'F · ·1111"'::".........-.-

; ::COUT

.,..

l:'1'-"1'4

10kn

8-

ICM7207A

....

1/4 CD4069C

Cour=22pF
~,~" ~
~,

INPUT'
,SIGNAL INPUT
SIGNAL
CONDITIQNING
(PRESCALER
lEVEL SHIFTING)

'0 == S.24288MHz
Rs <; 75!l
Cs == O.015pF
Cp == 3.5pF

6-70

II

ICM7224/1CM7225
CHIP TOPOGRAPHIES

BP

BRT

A2

A2

GNO
STORE
RESET

B2
C2

0.115 in

B2

COUNT

COUNT

C2
02

COUNT INHIBIT
LZB OUT

E2

LZBIN

02

COUNT INHIBIT
LZB OUT

E2

LZBIN

0.115 in

CARRY

~lmm ~

L.<.::==========OM.J [:'::'

~

3 03 E3 G3 F3 A4 B4 C4 04 E4

ICM7224

0.102 in - - - - - - 1
2.59 mm

ICM7225

a

6·71

'ICM7226A1B
10MHz Universal Counter
System for LED Displays
FEATURES
• CMOS design for very low power
• Output drivers directly drive both digits and
segments of large 8 digit LED displays. Both
common anode and common cathode versions
are available
• Measures frequencies from DC to 10M Hz; periods
from O,S/LS to 10s
• Stable high frequency oscillator uses either 1MHz
or 10MHz crystal
• Control signals available for external systems
operation
• Multiplexed BCD outputs
APPLICATIONS
• Frequency Counter
• Period Counter
• Unit Counter
• Frequency Ratio Counter
• Time Interval Counter

ORDERING INFORMATION
DISPLAY

,

DEVICE

ORDER
NUMBER

PACKAGE

CERDIP
ICM7226AIJL
DICE
ICM7226AID
Plastic
ICM7226BIPL
Common Cathode ICM7226B
DICE
ICM7226BID
tJOTE: An evaluation kit is available for these devices - order
ICM7226AEV/KIT.
Common Anode·

ICM7226A

GENERAL DESCRIPTION
The ICM7226 is a fully integrated Universal Counter and LED
display driver. It combines a high frequency oscillator, a
decade timebase counter, an 8 decade data counter and
latches, a 7 segment decoder, digit multiplexer, and segment
and digit drivers which can directly drive large LED displays.
The counter inputs accept a maximum frequer;lcy of 10MHz
in frequency and unit counter modes a,nd 2MHz in the other
modes. Both inputs are digital inputs. In many applications,
amplification and level shifting will be reqUired to obtain
proper digital signals for these inputs.
The ICM7226 can function as a frequency counter, period
counter, frequency ratio (fi>Jfs'! counter, time interval counter
or a totalizing counter. The devices require either a 10MHz or
1MHz crystal timebase, or if desired an external timebase
can also be used. For period and time interval, the 10MHz
timebase gives a 0.1/lsec resolution. In period average and
time interval average, the resolution can be in the nano·
second range. In the frequency mode, the user can select
accumulation time of 10ms, 100ms, 1s and 10s. With a 10s
accumulation time, the frequency can be ,displayed to a
resolution of 0.1 Hz. There is a 0.2s interval between
measurements in all ranges. Control signals are provided to
enable gating and storing of prescaler data.
Leading zero blanking has been incorporated with frequency
display in kHz and time in /ls. The display is multiplexed at a
500Hz rate with a 12.2% duty cycle for each digit. The
ICM7226A is designed for common anode display with typi·
cal peak segment currents of 25mA, and the ICM7226B is
designed for commpn cathode displays with typical seg·
ment currents of 12mA. In the display off mode, both digit
drivers & segment drivers are ttirned off, allowing the display
to be used for other functions.

PIN CONFIGURATION (outline dwgs JL, PL)
CONTROL IN

M""'EA"S""'INnp"'Ri>O"'G"'R.'i~"'~!'o~

CONTROL IN
BIN
MEAS IN PROGRESS
FUNCTION
STORE
BCD 4
BCD8
D1

" A IN
3

FUNCTION 4
STORE
BCD 4
BCD 8
DP
SEG e 9
SEG 9 10
SEG a 11
GROUND 12
SEG d 13
SEG b 14
SEGC15
SEG f 16
BCD 2 "
BCD 1 "
Ii5"l'IN 19
EXT DP IN 20

::

~8W OSC OUT

NC'
OSC OUT
OSC IN
NC'
33 EXT OSC IN
:i2' RST OUT
31 EXT RANGE
30 01
29 D2
31
36

35
34

ICM7226A

28

03
02

23

.......

.. ~--

22
21

D7
D8
RANGE

'For maximum frequency
stability, connect to V+ or GROUND

6·72

36

OSC OUT
OSC IN
NC*
EXT OSC IN
RST OUT
EXT RANGE
DP OUT
SEG 9
SEG e
SEG a
SEG d

34

8

33
32
31
30
29

9
10

28
27

26

16

BCD 2 17
BCD 1 "
ASTIN 19
EXT OP IN 20

06

A IN
HOLD
BUFF OSC OUT

7

0411

08

40
39
38
37
35

GROUND 12
05 13
D6 14
D7 15

03

27 D4
26D5
25 V+

24

2

...

~--

Ne·

ICM7226A/B
ABSOLUTE MA'XIMUM RATINGS
Maximum Supply Voltage .............................................. 6.5V
Maximum Digit Output Current ........................................ 400mA
Maximum Segment Output Current ..................................... 60mA
'Voltage on any Input or
OutputTerminal(Notel) ............................ NottoexceedV+ orGND
by more than 0.3V
Maximum Power Dissipation at 70 0 (Note 2)
ICM7226A ........................................................ 1.0W
ICM7226B ........................................................ 0.5W
Maximum Operating Temperature Range ....................... - 20°C to + 85°C
Maximum Storage Temperature Range ........................ - 55°C to + 125°C
Lead Temperature (soldering, 10seconds) ................................ 300°C

e

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability .
• Note 1: Destructive latchup may occur if input signals are applied before the power supply is
established or if inputs or outputs are forced to voltages exceeding V+ or GROUND by
O.3V.
Note 2: Assumes all leads soldered or welded to PC board and free air flow.

ELECTRICAL CHARACTERISTICS
v+= S.OV, Test Circuit,

TEST CONDITIONS:
PARAMETER
Operating Supply

SYMBOL CONDITION

I~p

Current
Supply Voltage Range

Maximum Guaranteed
Frequency
Input A, Pin 40

Maximum Frequency
Input B, Pin 2
Minimum Separation
Input A to Input B
Time Interval Function
Maximum osc. freq. and ext. osc.
freq. (minimum ext. osc. freqJ
Oscillator Transconductance
Multiplex Frequency

MIN

TYp

MAX

UNITS

2

5

mA

6.0

V

Display Off
'Unused inputs to GROUND

Vsupp

fA(max)

fS(max)

fose
gm
f mux

Time Between Measurements
Minimum Input Rate of Charge

TA = 2SoC, unless otherwise specified.

dVin/dt

-20°C < TA < 85°C
Input A, Input B
Frequency at fMAX

4.75

-20° C < T A < 85° C
4.75V < V+ < 6.0V Figure 1
Function = Frequency,
Ratio, Unit Counter
Function = Period, Time Interval
-20°C < TA < 85°C
4.75V < V+ < 6.0V
Figure 2

10
2.5

-20°C < TA < 85°C
4.75V < V+ < 6.0V
Figure 3
-20°C < TA < 85°C
4.75V < V+ < 6.0V

14

MHz

2.5

ns

250

(0.1 )

V+ = 4.75V
TA = +85°C

10

MHz

2000

Il S

500
200

fose = 10 MHz
fose - 10 MHz
Inputs A, B

15

Hz
ms
mV/~s

SEGMENT IDENTIFICATION AND DISPLAY FONT
LED overflow indicator connections:
Overflow will be indicated on the decimal point output of
digit 8.

ICM7226A
ICM7226B
6-73

CATHODE

ANODE

d.p.
DB

DB
d.p.

ICM7226A/B
ELECTRICAL CHARACTERISTICS (Continued)
TEST CONDITIONS: V+ = 5.0V, test circuit, TA = 25° C, unless otherwise specified.
MIN

SYMBOL CONDITION
PARAMETER
INPUT VOL TAG~S
PINS 2,19,33,39,40,35
-20°C < TA < +70 P C
input low voltage
V,L
input high voltage
V,H
hLK
PIN 2. 39, 40 INPUT LEAKAGE, A, B
I npul resistance to V·
V,N = V· -1.0V.
PINS 19,33
RIN
r-:-Input resistance to GROUND
V,N =+1.0V
PIN 31
RIN
Output Current
PINS 3,5,6,7,17,18,32,38
VOL = +OAV
IOL
PINS 5,6,7,17,18,32
IOH
VOH + 2.4V
PINS 3,38
VOH=V+~.8V
IOH

TYP

MAX

1.0

V
3.5
20

100

400

50

100

"A

.kll

400
100
265

=

UNITS

"A
"A

ICM1226A
PINS 22,23,24,26,27,28,29,30
DIGIT DRIVER
high output current
low outP(Jt current
SEGMENT DRIVER
'-'I~S 8,9,10,11,13,14,15,16
low output current
high output current
MUL TIPLEX INPUTS
PINS 1,4,20,21
input low voltage
input high voltage
input resistance 10 GROUND

IOH
IOL

Vo = V+ -2.0V
Vo - +1.0V

150

mA

180
~.3

"

1m
IOH

Vo = +1,5V
Vo = V+ -1.0V

V,L
V,H
RIN

V,N = +1.0V

IOL
IOH

Vo = +1.0V
Vo - V+ -2.5V

IOH
IL

Vo = V+ -2.0V
Vo - GROUND

25

mA
iJ. A

35
100

0.8
_.

2.0
50

V

100

kfl

75
100

iJ. A

ICM7226B
DIGIT DRIVER
PINS 8,9,10,11,13,14,15,16
low output current
high output current
SEGMENT DRIVER
PINS 22,23,24,26,27,28,29,30.
high output current
leakage current
MUL TIPLEX INPUTS
PINS 1,4,20,21
input low voltage
input high voltage
input resistance to V·

V,L
V,H
RIN

1----;:;:-

V,N

~

V· --1.0V

50

mA

10
15
---- - ----10

V ~.8
200

-360

V·
-2.0
--~~

mA
iJ. A

V
kfl

EVALUATION KIT
An evaluation kit is available for the ICM7226. It includes all the components necessary to assemble and evaluate a
universal frequency/period counter based on the ICM7226. With the help of this kit, an engineer or technician can
have the ICM7226 "up-and-running" in less than an hour. Specifically, the kit contains an ICM7226AIJL, a 10MHz
quartz crystal, eight each 7-segment 0.3" LEOs, PC board, resistors, capacitors, diodes, switches and IC socket.
Order Number ICM7226AEV/Kit.

6-74

ICM7226A/B
BLOCK DIAGRAM

-

-L
EXT

asc

INPUT

asc INPUT

asc OUTPUT

0------1

~~ S~~~CT

__

OECODERI_.-J'I.-_-I

O~:~~:S _--------------------'~;.«'-

10~ .J~HZ
I,

104 OR

r:::;-

d:O~NTROl
LOGIC i----<> RANGE INPUT

REFERENCE
COU~~ER

RANGE INPUT

r--~------+-_+_+_+-'
,------_+----1
~--+_I_I+-rrl--t___::.--+-;CONTROL
CONTROL
,------+-+-------'
1
LOGIC 1 - - - - < > INPUT

8~~~E~~~

~tNPuTo--~~~-----~_I----------'

~

.--JEN

MAIN

~

RESE~I

L,.

INPUT A

II-1I~c~O=u~N~T~EA~o~v-ErA~Fl~o~wJl-+-+-+--+~i
0----.-+-1 cONTROLt_III1j-____
LOGIC
CL
108

INPUT B

o--t-i-t-l

414 14 14 1414 14 4

L

8

DATA LATCHES

t-+---"I---J-.l-I~~~PUT

~

o

CONTROL

'------ lOGIC

r---

-

STOREr

L...-....,

a

~~_+---ICl

1------------<>

,.t_ .

r---

~

D.P.
LOGIC

DECODER
& LZB
LOGIC

_____ ~

EXT. C.P
INPUT

SEG
8

SEGMENT

4

BCD

~ DRIVERS I_-!!f--<> OUTPUTS (8)
'

MAIN

FF

FN

FUNTJ~~~ o-___-IC~~:~~LI----I---+---+---------+---+-'

OUTPUT o-----oC-......&:::1-________1_1--'

OUTPUTS (4)

V

.

MEAS IN PROG

HOLD INPUT

4

RESET
OUTPUT

SfOAE
OUTPUT

0------='---------'

TEST CIRCUIT

CONTROL INPUT

v+ '-- s.ov

STORE OUTPUT

10kll
D1

t.,

BCD C OUTPUT
BCD 0 OUTPUT
dp

...r:;---t--{!II

ICM7226A

"

CRYSTAL SPECS. =
Fa
10.00 MHz

33

Co

"

""

Rs

22pf
lSI!

DENOTES
BUS WITH
6 CONDUCTORS

BCD B OUTPUT
BCD A OUTPUT

===!==HB

LED OVERFLOW INDICATOR CONNECTIONS
OVERFLOW WILL BE INDICATED ON THE
DECIMAL POINT OUTPUT OF DIGIT 7
ICM7226A
ICM72268

6-75

d.p.

D,

0,
d.p.

m

ICM7226A/B
COUNTED

~TRANSITIONS

This can be easily accomplished with the following
circuit: (Figure 3b).

50 ns MIN

4.5V.,.-----__,.
INPUT A
SIGNAL A

O.5,V
50 ns MIN

FIGURE 1. Waveform for Guaranteed Minimum fA(max)
Function = Frequency, Frequency Ratio, Unit Counter.
_MEASURED _ _
INTERVAL

INPUT A OR
INPUT B

4.5V

~_ _ _-I~ INPUT A

SIGNAL B

I

V'

v+

v+

N.o.~~_IPrR)'M",E_1-W1-+'_50-lk~>-""'-I~

v+

O.5V

lOOk

lN914

FIGURE 2. Waveform for Guaranteed Minimum fe(max)
and fA(max) for Function = Period and Time Interval.

O.15pF

T'

TIME INTERVAL MEASUREMENT

Type

The ICM7226A/B can be used to accurately measure
the time interval between two events. With a 10 MHz
time-base crystal, the time between the two events
can be as long as ten seconds. Accurate resolution in
time interval measurement is 100ns.

C040498 Inverting Buffer
CD4070B Exclusive-OR

FIGURE 3b. Priming Circuit, Signal A&B High or Low.

The feature operates with Channel A going low at the
start of the event to be measured, followed by Channel
B going low at the end of the event.

Following the priming procedure (when in single event
or 1 cycle range input) the device is ready to measure
one (only) event.

When in the time intervlll mode and measuring a
single event, the ICM7226A/B must first be "primed"
priorto measuring the event of interest. This is done by
first generating a negative going edge on Channel A
followed by a negative going edge on Channel B to
start the "measurement interval." The inputs are then
primed ready for the measurement. Positive going
edges on A and B, before or after the priming, will be
needed to restore the original condition.

- =p

20pF

When timing repetitive signals, it is not necessary to
"prime" the ICM7226A/B as the first alternating signal
states automatically prime the device. See Figure 3a.
During any time interval measurement cycle, the
ICM7226A/B requires 200ms following B going low to
update all internal logic. A new measurement cycle
will not take place until completion of this internal
update time.

H4om •
L..J

STORE

30 TO 40ms

"

J.--+

n

RESET _ _..:-_ _ _ _..I

I

GOms

FUNCTION:
TIME INTERVAL

L _ _:...._ _4

H-40ms

~19~~g~~gms - - - - I - - - P R I M I N G ----I_----MEASUREMENT INTERVAL ----~-I-~

MEASUREMENT
~

INPUT A

...J.~I'lllllfI

INPUT B

I

--l

250ns MIN.
MEASURED
INTERVAL

I

I--

IFIRS"

NOTE: IF RANGE IS SET TO 1 EVENT, FIRST AND LAST MEASURED INTERVAL WILL COINCIDE.

FIGURE 3a. Waveforms for Time Interval Measurement (Others are similar. without priming phase)
6-76

--.j
I-MEASURED
INTERVAL
(LAST)

.D~DIL

ICM7226A/B

Display Off - To enable the display off mode it is necessary to
tie 0 4 to the CONTROL input and have the HOLD input at V +.
The chip will remain in this mode until HOLD is switched low.
While in the display off mode, the segment and digit driver
outputs are open and the oscillator continues to run (with a
typical supply current of 1.5mA with a 10MHz crystal) but no
measurements are made. In addition, signals applied to the
multiplexed inputs have no effect. A new measurement is in·
itiated after the HOLD input goes low. (This mode does not
operate when functioning as a unit counter.)

APPLICATION NOTES
GENERAL
INPUTSA& B
The signal to be measured is applied to INPUT A in frequency
period, unit counter, frequency ratio and time interval modes.
The other input signal to be measured is applied to INPUT B
in frequency ratio and time interval. fA should be higher than
fs during frequency ratio.
Both inputs are digital inputs with a typical switching
threshold of 2.0V at V + 5.0V and input impedance of 250kfl.
For optimum performance, the peak to peak input signal
should be at least 50% of the supply voltage and cente~ed
about the switching voltage. When these inputs are being
driven from TTL logic, it is desirable to use a pullup resistor.
The circuit counts high to low transitions at both inputs.
Note: The amplitude of the input should not exceed the supply by
more than 0.3V otherwise, the circuit may be damaged.

=

1MHz Select - The 1MHz select mode allows use of a 1MHz
crystal with the same digit multiplex rate and time between
measurements as a 10MHz crystal. The internal decimal
point is also shifted one digit to the right' in period and time in·
terval, since the least significant digit will be in 11's incre· .
ments rather than 0.1I's.
External Oscillator Enable - In this mode, the EXTernal
OSCillator INput is used, rather than the on·chip oscillator,
for the Timebase and Main Counter inputs in period and time
interval modes. The on·chip oscillator will continue to func·
tion when the external oscillator is selected, but have no
effect on circuit operation. The external oscillator input fre·
quency must be greater than 100kHz or the chip will reset
itself and enable the on·chip oscillator. Connect external
oscillator to both OSC IN (pin 35) and EXT OSC IN (pin 33), or
provide crystal for "default" oscillation, to avoid hang·up
problems.

MULTIPLEXED INPUTS
The FUNCTION, RANGE, CONTROL and EXTERNAL
DECIMAL POINT inputs are time multiplexed to select the
input function desired. This is achieved by connecting the ap·
propriate digit driver output to the inputs. The input function,
range and control inputs must be stable during the last half of
each digit output, (typically 125I'sec). The multiplex inputs
are active high for the common anode ICM7226A, and active
low for the common cathode ICM7226B.
Noise on the multiplex inputs can cause improper operation.
This is particularly true when the unit counter mode of opera·
tion is selected, since changes in voltage on the digit drivers
can be capacitively coupled through the LED diodes to the
multiplex inputs. For maximum noise immunity, a 10kfl
resistor should be placedin series with the multiplex iriputs
as shown in the application notes.

External Decimal Point Enable - When external decimal
point is enabled, a decimal pOint will be displayed whenever
the digit driver connected to the EXTERNAL DECIMAL POINT
pin is active. Leading Zero Blanking will be disabled for all
digits following the decimal point.

Table 1 shows the functions selected by each digit for these
inputs.

Test Mode - This is a special mode used only in high speed
production testing, and serves no other purpose.

TABLE 1. Multiplexed Input Control
FUNCTION INPUT
PIN 4

RANGE INPUT
PIN 21

PIN 31
CONTROL INPUT
PIN 1

EXTERNAL DECIMAL
POINT INPUT, PIN 20

RANGE INPUT

DIGIT
FUNCTION
Frequency
01
Period
Os
Frequency Ratio
02
Time Interval
05
Unit Counter
04
Oscillator Frequency
03
0.01 Sec/1 Cycle
01
0.1 Sec/l0 Cycles
02
1 Sec/l00 Cycles
03
10 Sec/1 k Cycles
04
Enable External Range
05
Input
Blank Display
D4&Hold
Display Test
Os
lMHz Select
02
External Oscillator Enable
01
External Decimal Point
Enable
03
Test
05
Decimal Point is Output for Same Digit
That is Connected to This Input

The range input selects whether the measurement is made
for 1, 10, 100 or 1000 counts of the reference counter, or if the
EXTernal RANGE INput determines the measurement time.
In all functional modes except unit counter, a change in the
RANGE input will stop the measurement in progress, without
updating the display, and initiate a new measurement. This
prevents an erroneous first reading after the RANGE input is
changed.

FUNCTION INPUT
Six functions can be selected. They are: Frequency, Period,
Time Interval, Unit Counter, Frequency Ratio and Oscillator
Frequency.
These functions select which signal is counted into the main
counter and which Signal is counted by the reference counter,
as shown in Table 2. In time interval, a flip flop is set first by a
1-0 transition at INPUT A and then reset by a 1-0 transition
at INPUT B. The oscillator is gated into the Main Counter duro
ing the time the flip flop is set. A change in the FUNCTION in·
put will stop the measurement in progress without updating
the displa{and then initiate a new measurement. This
prevents an erroneous first reading after the FUNCTION
input is changed. If the main counter overflows, an overflow
indication is output on the Decimal Point Output dUring Os.

CONTROL INPUTS
Display Test - All segments are enabled continuously, giving
a display of all 8's with decimal points. The display will be
blanked if display off is selected at the same time.

6-77

Dl
•

ICM7226A/B
TABLE 2. Input Routing
DESCRIPTION
Frequency (fAI

BCD Outputs - The BCD representation o/each digit output
is available at the BCD outputs; see Table 3 for TruthTable.

REFERENCE
COUNTER
100Hz IOsciliator +
105 or 1041
Input A
Input B
Osc OFF Gate
Not Applicable
100Hz IOsc : 105 or

MAIN COUNTER
Input A

Period ItAI
Oscillator
Ratio (fA/fBI
Input A
Time Interval IA-BI Osc ON Gate
Unit CounterlCount AI Input A
Osc. Freq. (foscl
Oscillator

The positive going (lCM7226A - Common Anodel or negative
going (ICM7226B - Common Cathode) digit drivers lag the
BCD data by 2 to 6 microseconds; the leading edge of the
digit drive signal should be used to externally latch the BCD
data. Each BCD output will drive one low powl;lr Schottky TTL
load and when interfacing low power Schottky TTliatches, it
is necesl'ary to use 1kll pull down resistors on the TTL inputs
for optimum results. The display is multiplexed from MSD to
LSD. Leading zero blanking has no effect on the BCD outputs.

1041

EXTERNAL DECIMAL POINT INPUT
TABLE 3 Truth Table BCD Outputs

When the external decimal point· is. selected, this input is
active. Any olthe digits, except 0 8 , can be connected to thi:;
point. 0 8 s.hould not be used since it will override the overflow
output and leading zeros will remain unblanked after the
decimal pOint.

NUMBER

r-Te-I

EXT RANGE
INPUT

Figure 4: External Range Input to End of Measurement in Progress.
MEASUREMENT' IN PROGRESS, STORE AND RESET
Outputs - These Outputs are provided to facilitate external in.
terfacing. Figure 5 shows the relationship between these
signals during the time between measurements. All three
outputs can drive a low power Schottky TTL load. The
MEASUREMENT IN PROGRESS output can directly drive one
ECl load, if the ECl device is powered from the. same power
supply as the ICM7226.

)

30'T040ms,

RESET OUT

t

l---+
·-U
I

2ooms-_1

~I

_____

1

1
1

0

0

0

6
7
8

1

9

1

0
0

~1l

40m ,

r---+

0

0

0
1
1
1
1

1

0

1

1
1

0

0
0

0

1
1

The ICM7226A is designed to drive common anode LED
displays at a peak current of 2SmA/segment, using displays
with VF = 1.8V at 25mA. The average DC current will be
greater than 3mA under these conditions. The ICM7226B is
deSigned to drive common cathode displays at a peak current
of 1SmA/segment, using displays with VF = 1.8V at 1SmA.
Resistors can be added in series with the segment drivers to
limit the display current, if required. Figures 6, 7, 8 and 9
show the digit and 'segment currents as a function of output
voltage for common anode and common cathode drivers.

L--..,

TO

0

0
0

DISPLAY CONSIDERATIONS

--,

'1---190

0

0
0
0
0
0
0
0

The display is multiplexed at a SOOHz rate with a digit time of
2441'S, and an interdigit blanking time of 61'S to prevent
ghosting between digits. The decimal point and leading zero
blanking have been implemented for right hand decimal
point displays; zeros following the decimal pOint will not be
blanked. leading zero blanking will also be disabled if the
Main Counter overflows. The internal decimal point control
displays frequency in kHz and time in j.lS.

LrL

____~I

BCD 1
PIN 18
0

BUFFered OSCillator OUTput - The BUFFered OSCillator
OUTput has been provided to enable use of the on chip
oscillator Signal without loading the oscillator itself. This
output will drive one low power Schott"y TTL load. Care
should be taken to minimize capacitivl;lloading on this pin.

EXTernal RANGE Input- The EXTernal RANGE Input is used
to select other ranges than those provided on the chip.
Figure 4 shows the relationship between MEASurement IN
PROGRESS and EXTernal RANGE Input.

M.EASUREMENT
IN PROGRESS

BCD2 .
PIN 17

1

3
4
5

RESET Input - The RESET Inpu~ resets the main counter,
stops any measurement in progress, and enables the main
counter latches, resulting in an all zero output. A capacitor to
ground will prevent any hang·ups on power·up.

MEAS.
iN PFrnGRm

BCD 4
PIN 6

0

2

HOLD Input - Except in the unit counter.mode, when the
HOLD Input is at V +, any measurement in progress (before
STORE goes low) is stopped, the main counter is reset and
the chip is held ready to initiate a new measurement as soon
as HOLD goes low. The latches which hold the main counter
data are not updated, so the last compll;lte measurement is
displayed. In unit counter mode when HOLD Input is at V +,
the counter is not stopped or reset, but the display is frozen at
that instantaneous value. When HOLD goes low the count
continues from the new value in the counter.

REFERENCE
COUNTER
CLOCK

BCDS
PIN 7

300

,.-----,---.--...7>1

200

1--------1--'-+F-----I

100 I-+-~I__H.H---!
6Dms

--------~~rlr~---­
r-+4if~s

1
2
Y+ - Vo (VOLTS)

Figure 5: RESET OUT, STORE, and MEASUREMENT IN
PROGRESS Outputs Between Measurements.

. Figure 6: ICM7226A Typical IDIG vs. V+-Vo ·4.5 :s V+
6·78

:s 6.0V

ICM7226A/B
80r-----.-----~~--~

-20°C " ,

'y

,

2
VO(VOLTS)

Yo (VOL 15)

(.1

(bl

In addition, there is a quantization error inherent in any digital
measurement of ± 1 count. Clearly this error is reduced by
displaying more digits. In the frequency mode, maximum ac~
curacy is obtained with high frequency inputs, and in period
mode maximum accuracy is obtained with low frequency in·
puts. As can be seen in Figure 10, the least accuracy will be
obtained at 10kHz. In time interval measurements there is a
maximum error of 1 count per interval. As a result there is the
same inherent accuracy in all ranges, as shown in Figure 11.
In frequency ratio measurement more accuracy can be ob·
tained by averaging over more cycles of INPUT B as shown in
Figure 12.

Figure 7: ICM7226A Typical ISEG vs. Vo

1 CYCLE

~

2

I----+--'!.:~:-"I~"'-lf---F~

~~

3

f--t-+-"i-.-"!d~~7f7i

~:::)iLt5

4

IL+-+-+-)!el€~*:-1

a:
200r-----,------r--r-~

200 ...-----....- - - - - , - - - - - ,

/---+---\->'\--::;;0-'-1

150 I---+-~-:.I'''=-=i

150

!100t---~~-_r--'_I
~

t-'k--'k~~.--t-+--F..t

~~

~~~~U1~~~~NT

103 CYCLES

FREQUENCY

o

1 SEC

.1

1

MEASUREMENT

__L-~-L~ '0 SEC

10 100 103 10 4 lOS, 106 107
FREQUENCY (Hz)

Figure 10: Maximum Accuracy· of Frequency and Period Measurements Due to Limitations of Quantization Errors.

Yo (VOLTS)

Va (YOLTS)

Figure 8: ICM7226B Typical

IDIG VS.

Vo

1'\

1'\

30

MAXIMUM TIME INTERVAL
FOR 103 INTERVALS

./

1'\

V

1'\ ~

MAXIMUM TIME INTERVAL
FOR 100 INTERVALS

V

"

V

,/

;<

PERIOD

102 CYCLES

i ~ :~+-+~~q~~~~ :~:~::c )
~~~~~

,

)

10 CYCLES

MAXIMUM TIME INTERVAL
FOR 10 INTEJ:tVALS

1'\1/

20

.s
0

1

10

1,\

10 100 103 104 105 106 107 10&
TIME INTERVAL (M5EC)

l

Figure 11: Maximum Accuracy of Time Interval Measurement Due
to Limitations of Quantization Errors.
vt-VOUT (VOLTS)

Figure 9: ICM7226B Typical ISEG vs. (V+-Vol 4.5V :5 V+ :5 6.0V

To increase the light output from the displays, V+ may be
increased to 6.0V, however care should be taken to see that
maximum power and current ratings are not exceeded.
The SEGment and Digit outputs in both the 7226A and Bare
not directly compatible with either TTL or CMOS logic.
Therefore, level shifting with discrete transistors may be
required to use these outputs as logic signals. External latch·
ing should be done on the leading edge of the digit signal.

1'\

/

, CYCLE

1'\I"
V"./
1"'\ 1""-.
./
100
V
I"I"11'\
V
""-. 1'\1'\ IX
V 103
1'\1'\1'\ IX
1'\1'\1'\ IX
I'\; 1'\1'\1,\

" '"

1

10

10 CYCLES

RANGE

CYCLES

(CYCLES OF B)

CYCLES

102 103 104 105 106 107 108

IA/IB

Figure 12: Maximum Accuracy for Frequency Ratio Measurement
Due to Limitations of Quantization Errors.

ACCURACY

CIRCUIT APPLICATIONS

In a Universal Counter, crystal drift and quantization errors
cause errors. I n frequency, period and time interval modes,
a signal derived from the oscillator is used either in the
Reference Counter or Main Counter, and in these modes, an
error in the oscillator frequency will cause an identical error
in the measurement. For instance, an oscillator temperature
coefficient of 20ppm/oC will cause a measurement error of
20ppm/oC.

The ICM7226 has been designed as a complete stand alone
Universal Counter, or used with prescalers and other circuitry
in a variety of applications. Since A IN and B IN are digital inputs, additional circuitry will be required in many applications.
for input buffering, amplification. hysteresis. and level shifting
to obtain the required digital voltages. For many applications
an FET source follower can be used for input buffering. and
an ECl 10116line receiver can be used for amplification and

ICM7226A/B
between measurements is lengthened to BOOms and the
display IT)ultiplex rate is decreased to 125Hz.

hysteresis to obtain high impedance input, sensitivity and
bandwidth. However, cost and complexity of this cfrcuitry
can vary widely, depending upon the sensitivity and
bandwidth required. When TTL prescalers or input buffers
are used, pull up resistors to V+ should be used to obtain
optimal voltage swing at A IN andB IN.
If prescalers aren't required, the ICM7226 can be used to
implement a minimum component Universal counter as
shown in figure 13.
For input frequencies up to 40MHz, the circuit shown in
figure 14 can be used to implement a frequency and period
counter. To obtain the correct value when measuring
frequency and period, it is necessary to divide the 10MHz
oscillator frequency down to 2.5MHz. In doing this the time

If the input frequency is prescaledby ten, the oscillator fre·
quency can remain at either 10MHz or 1MHz, but the decimal
point must be moved. Figure 15 shows use of a .;. 10
prescaler in frequency counter mode. Additional logic has
been added to enable the 7226 to count the input directly in
period mode for maxi.mum accuracy. Note that A IN comes
from Q c rather than QQ, to obtain an input duty cycle of 40%.
If an output with a duty cycle not near 50% must be used then
it may be necessary to use a 74121 monostable multivibrator
or similar circuit to stretch the input pulse to guarantee a
50ns minimum pulse width.

10kll

~+------------,

TYPICAL.
CRYSTAL PARAMETERS

Cl - 22pF
R5

35!)

'------------<> EXT OSC IN

m
Figure 13: 10MHz Universal Counter

I<>-____

DISPLAY DISPLAY

OFF

TEST

10lln

EKT
OSC

.,,

8.

10k ••

0,

0,

Notes: 11 If a!2.5MHz crystal is used, diode 01 and I.,C.'s 1 and 2 can be eliminated.
Figure 14: 40MHzFrequency, Period Counter

6·80

~

A IN

.D~DIb

ICM7226A/B
Figure 16 shows the use of a CD4016 analog multiplexer to
multiplex the digital outputs back to the FUNCTION Input.
Since the CD4016 is a digitally controlled analog transmission gate, no level shifting of the digit output is required.
CD4051's or CD4052's could also be used to select the
proper inputs for the multiplexed input on the ICM7226from
2 or 3 bit digital inputs. These analog multiplexers may also

be used in systems in which the mode of operation is
controlled by a microprocessor rather than directly from
front panel switches. TTL multiplexers such as the 74153 or
74251 may also be used, but some additional circuitry will be
required to convert the digit output to TTL compatible logic
levels.

10k

INPUT

~

39pF

DIODES: 'IN914

INPUT

lOki!

Figure 15: 100MHz Multi Function Counter

v'

DISPLAY DISPLAY
39pF
OFF
TEST
10k!1
»--tt-~~--'\NV------------...------.--,

v'
10k!!

INPUT

v'
10k ~!

10MHz

39pF TYP

"

25

0,

o
RESET

INPUT~

Figure 16: 100MHz Frequency Period Counter

6·81

ICM7226A/B

II

The circuit shown in figure 17 can be used in any of the
circuit applications shown to implement a single measurement mode. of operation. This circuit uses the STORE output
to put the ICM7226 into a hold mode. The HOLD input can
also be used to reduce the time between measurements. The
circuit shown in figure 18 puts a short pulse into the HOLD
input a short time after STORE goes low. A new measurement will be initiated at the end of the pulse on the HOLD
Input. This circuit reduces the time between measurements
to less than 40ms from 200ms; use of the circuit shown in
Figure 18 on the circuit shown in Figure 14 will reduce the
time between measurements from 1600ms to 800ms.

For a specific crystal and load capacitance, therequired gm
can be calculated as follows:
gm = w 2 CINCOUT Rs

(1+ g~) 2

C
( CinCout )
h
were L = Cin+Cout
Co =
Rs =
Cin =
Cout =
w =

Crystal static capacitance
Crystal Series Resistance
Input Capacitance
Output Capacitance
2 rrf

The required gm should not exceed 50% of the gm specified
for the ICM7226to insure reliable startup. The oscillator in·
put and output pins each contribute about 4pF to CIN and
COUT . For maximum freqL1cy stability, CIN and COUT
should be approximately twice the specified crystal load
capacitance.

HOLD
INPUT

In cases where nondecade prescalers are used, it may be
desirable to use a crystal which is neither 10MHz nor 1MHz.
In this case both the multiplex rate and the time between
measurements will be different. The multiplex rate is

OPEN
SINGLE MEAS MODE ENABLED
CLOSED - INITIATE NEW MEASUREMENT
CLOSED -- HOLD INPUT

Figure 17: Single Measurement Circuit for Use With ICM7226

I mux

.
lose
=-fose
- - for. 10M Hz mode and
f mux = - - - - for the

2x10 4

2x10 3

1MHz mode. The time between 'measurements is 2 ~ 10 6 in

100k!!

ose

th~ 10MHz mode and 2 ~ 10

HOLD INPUT

5

in the 1MHz mode. The buffered

ose

oscillator output should be used as an oscillator test point or
to drive additional logic; this output will drive one low power
Schottky TTL load. When the bulfered oscillator output is
used to drive CMOS or the external oscillator input, a 10k!l
resistor should be added from the buffered oscillator output
to V+.

"o;l{°

"0" ••

Figure 18: Circuit for Reducing Time Between Measure,ments

The crystal and oscillator components should be located as
close to the chip as practical to minimize pickup from other
signals. In particular, coupling from the BUFfered OSCillator
OUTput and EXTernal OSCillator INput to the OSCillator
OUTput or OSCillator INput can cause undesirable shifts in
oscillator frequency. To minimize this coupling, pins 34 and
37 should be connected to V+ or GROUND and these two
signals should be kept away from the oscillator circuit.
4

TYPICAL LCD DISPLAY

5

v' (VOLTS) I
IAMAX, tSMAX AS FUNCTION OF Y+

Figure 19: Typical Operating Characteristics
Figure 20 shows the iCM7226 being interfaced to LCD dis·
plays, by using its BCD outputs and 8 digit lines to drive 2
ICM7211 display drivers. The iCM7226 EVIKit may easily be
interfaced to 21CM7211 EVIKits in this way. A similar arrange·
ment can be used for driving vacuum fluorescent displays
with the ICM7235.

OSCILLATOR CONSIDERATIONS
The oscillator is a high gain complementary FET inverter. An
external resistor of 10M!l or 22M!l should be connected bet·
ween the oscillator input and output to provide biasing. The
oscillator is designed to work with a parallel resonant
10MHz quartz crystal with a load capacita~ce of 22pF and a
series resistance of less than 35!l. Among suitable crystals
is the 10MHz CTS KNIGHTS ISI·002.

ICM7226A

Figure 20: 10MHz Universal Counter Sy&tem with LCD Display
6·82

ICM7228A/B
CHIP TOPOGRAPHIES

EXT

RANGE
EXT D.P. IN

0.157 In
(3.9ae)mm

RESET IN

BCo,
BCo,
SEQ,

SEQ,

ICM7226A
EXT

SEQ,

SEQ,

RANGE
EXT C.P.IN
RESET IN

BCO,
BCo,

Do

ICM7226B

6·83

Dl

ICM7231/32/33/34
Display Decoder/Drivers
for Triplexed Liquid
Crystal Displays
FEATURES
The family is designed to interlace to modern hIgh
"performance, microproces'sors and microcomputers
, and ease system requirements for RO'M space and
CPU timE! needed to service a display.
The ICM7231 drives displays with 8 seven-segment
digits with ,two independent annunciators per digit,
accepting Six data bits and three digit address bits from
paralleL inputs controlled by a chip select input. The
data bits are subdivided into four binary code bits and
two annunciator control bits. The ICM7232 drives 10
seven-segment digits with two independent annunciators per digit. To write into the display, six bits of data
and four bits of digit address are clocked serially into a
shift register, then decoded and written to the display.

• ICM7231: Drives 8 digits of 7 segments with two
Independent annunciators per digit. Address and
dat.input In parallel format.
• ICM7232: Drives 10 digits of 7 segments with two
independent annunciators per digit. Address and
data'input In serial format.
'
• ICM7233: Drives 4 characters of 18 segments.
Address and data input in parallel fo:rmat.
• ICM7234: Drives 5 characters of 18 segments.
Address and data input in serial format.
• Chips provide all signals required tb drive rows
and columns of trlplexed LCD display.
• Display voltage independent of power
supply, allows user control of display operating
voltage and temperature compensation if desired.
• On-Chip oscillator provides all display tlmlng~
• Total power consumption typically 200/lW,
maximum 500/lW at 5V.
• Low-power shutdown mode retains data with 5/lW
typical power consumption at 5V, 1/lW at 2V.
• Direct interfacing to high-speed microprocessors
and microcomputers.

The ICM7233 has a parallel input structure similar to
the ICM7231, but the decoding and the outputs are
organized to drive four 18-segment alphanumeric
characters. The six data bits represent a 6-bit ASCII
code.
The ICM7234 uses a serial input structure like that of
the ICM7232, and drives five 18-segment characters.
Again, the input bits represent a 6-bit ASCII code.
Input levels are TTL compatible, and the DATA
ACCEPTED output on the serial input devices will
drive one LSTTL load. The intermediate voltage levels
necessary to drive the display properly are generated
by an on-chip resistor string, and the output of a totally
self-contained on-chip oscillator is used to generate all
display timing. All devices in this family have been
fabricatedusinglntersil's MAXCMOS® process and all
inputs are protected against static discharge. Devices
are packaged in a 40 pin plastic DIP.

GENERAL DESCRIPTION
The ICM7231/7234 family of integrated circuits are
designed to generate the voltage levels and switching
waveforms required to drive triplexed liquid-crystal
displays. These chips also include input buffer and
digit address decoding circuitry and contain a maskprogrammed ROM allowing six bits of input data to be
decoded into 64 independent combinations of the
output segments of the selected digit.

DATA CLOCK

Ci

V·

INPUT
VOISP

VDUS'
COM1

A1

COM1

DATA ACCEPTED
OUTPUT
COM3
12

GND

,v

lOY 6Y

DATA ACCEPTED

AO

OUTPUT

12

D5

tv

D4

12
,V
,X

,w

9X 7Z

22
AN2

,V

AN'

'U

1U

2Z

2Z

3V

2V

2V

3X

BZ

3X

BZ

BX

2X

4W

2X

42

7X

4Z

7X

9Z

2W

4X

2W

4V

n"

4V

7Y 9Y

2V

2V

4X

7Z 9X

2U

2U

4X

5Z

3Z

3Z

5V

5v

3V

3Y

5X

5X

3X

3X

52

6·84

v'
WlITff INPUT

3

,X

ZV

INPUT
VDISP

COM3

lOX 6Z

8D3
8D2

COM2

DATA CLOCK

ICM7231/32/33/34
OPTION TABLE AND ORDERING INFORMATION
ORDER PART"
NUMBER

ANNUNCIATOR
LOCATIONS

OUTPUT CODE

INPUT

OUTPUT

Parallel Entry
4 bit Data
2 bit Annunciators
3 bit Address

8 Digits
plus
16 Annur.ciRtors

ICM7231AFIPL
ICM7231BFIPL
ICM7231CFIPL

Hexadecimal

ICM7232AFIPL

Hexadecimal

Both AnnunCiators

Serial Entry

10 Digits

ICM7232BFIPL

Code B

on COM3

ICM7232CRIPL

Code B

4 bit Data
2 bit Annunciators
4 bit Address

plus
20 Annunciators

Both Annunciators

"on COM3

Code B
Code B

ICM7233AFIPL

1 Annunciator COM1
1 Annunciator COM3

1 Annunciator COM1
1 Annunciator COM3

64 Character

No Independent

Paraliel Entry

Four

(ASCII(

Annunciators

6 bit (ASCII(

Characters

Data

18 Segment

(Half width numbers)
ICM7233BFIPL

2 bit Address

64 Character

No Independent
Annunciators

(ASCII(

6 bit (ASCII(

18 Segment

Data
3 bit Address

(Full width numbers)
ICM7234AFIPL

64 Character

No Independent
Annunciators

(ASCII (

Parallel Entry

Five

6 bit IASCII(

Characters

Data
2 bit Address

18 Segment

(Half width numbers)
ICM7234BFIPL

Four
Characters

Serial Entry

64 C.haracter

No t ndependent
Annunciators

(ASCII(

Serial Entry

Five
Characters

6 bit (ASCII(

18 Segment
(Full width numbers)

Data
3 bit Address

·Olce versions also available! ICM7231AF/D, ICM7233AF/O, etc. \ Introductory parts may be available only
suffix to IJL if necessary

In

CEADIP package. Change

ABSOLUTE MAXIMUM RATINGS
Power Dissipation l11 ............... O.S W @ 70 0 e
Supply Voltage (V+) ............. ,............ 6.S V
Input Voltagel 2 1 ................... -0.3:S VIN :S 6.S
Display Voltagel 2 1 ............. -0.3:S VDISP :S +0.3
Operating Temperature Range ..... -20 0 e to +8Soe
Storage Temperature Range ..... -ssoe to +12Soe

NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any olher conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum' rating conditions for
extended periods may affect device reliability.

Notes:
1. This limit refers to that of the package and will not be obtained during normal operation.
2. Due 10 the SeR structure inherent in these devices, connecting any display terminal or the display vOltage terminal to a voltage outside

the powersupply to the chip may cause destructive device latchup. Thedigilal inputs should never be connected to a voltage less than-0.3 volts below ground, but may be connected to voltages above V+ but not more than 6.5 volts above GND.

ELECTRICAL CHARACTERISTICS v+ = SV ±1 0%, T A = -20° e to +8So e unless otherwise specified
PARAMETER

SYMBOL

Power Supply Voltage

V+

CONDITIONS/DESCRIPTION

Data Retention
Supply Voltage

V+

Guaranteed Retention at 2V

Logic Supply Current

1+

Current from V+ to Ground excluding
Display. VOISP = 2V

TYP

MAX

UNITS

4.5

>4

5.5

V

2

1.6
30
1

Shutdown Total Current Is

VOISP Pin 2 Open

Display Voltage Range

VOISP

Ground 0; VOISP 0; V+

Display Voltage Setup
Current

IOISP

VOISP = 2V Current from V+ to
VOISP On-Chip

Display Voltage Setup
Resistor Value

ROlsP

One of Three Identical Resistors
in String

DC Component of
Display Signals

MIN

0
15
40

(Sample Test only)

Display Frame Rate

fOlsP

See Figure 2

Input Low Level

VIL

Input High Level

VIH

ICM7231, ICM7233
Pins 30-35, 37-39, 1

Input Leakage

ilLK

Input Capacitance

CIN

Output Low Level
VOL
Output High Level
VOH
Operating Temperature Top
Range

60

V
100

JJ.A

10

JJ.A

V+

V

25

JJ.A

75

kG

1/4

1

% (V+ - VOISP)

90

120

Hz

0.8

V

1

JJ.A

2.0

V
0.1

ICM7232, ICM7234
Pins 1, 38, 39

pF

5

Pin 37, ICM7232, ICM7234, 10L
V+ = 4.5V, 10H = -500JJ.A
Industrial Range

6·85

= lmA,

0.4
4,1
-20

+85

V
V
°C

Dl

AC CHARACTERISTICS V+=5V±10%,-20°CsTAS +85°C
PARALLEL INPUT (ICM7231, ICM7233) See Figure 12
PARAMETER
Chip Select
Pulse Width

SYMBOL

MIN

TYP

tes

CONDITIONS/DESCRIPTION

500

350

Address/Data
Setup Time

Ids

200

Add ress/Data
Hold Time

tdh

a

Inter-Chip
Select Time

tics

3

MAX

UNITS
ns
ns

-20

ns
I's

SERIAL INPUT (ICM7232, ICM7234) See Figures 15, 16, 17
PARAMETER

SYMBOL

Data Clock
Low Time

tel

350

ns

Data Clock
High Time

tel

350

ns

Data Setup Time
Data Hold Time

tds

200

tdh
twp

0

-20

500

350

Write Pulse 10
Clock at
Initialization

twll

1.5

Data Accepted
Low Output Delay
Data Accepted
High Output Delay

tadl

200

400

ns

tadh

1.5

3

I'S

Write Delay After
Last Clock

tews

Write Pulse
Width

CONDITIONS/DESCRIPTION

MIN

TYP

MAX

UNITS

ns
ns
ns
I's

350

ns

TERMINAL DEFINITIONS
ICM7231 PARALLEL INPUT NUMERIC DISPLAY
TERMINAL

PIN
NO.

AN1
AN2

30
31

BOO
BD1
BD2
BD3

32
33
34
35
37
38
39
1

AO
A1
A2
CS

DESCRIPTION
Annunciator 1 Control Bit
Annunciator 2 Control Bit
Least Significant}

4 Bit Binary
Data Inputs

Most Significant
Least Significant}

3 Bit Digit
Address Inputs
Most Significant
Data Input Strobe/Chip Select
(Note 3)

FUNCTION
High = ON
Low = OFF

See Table 3

Input
Data
(See Table 1)

HIGH = Logical One (1)
LOW = Logical Zero (0)
Input
Address
(See Table 2)
Trailing (Positive going)
edge latches data, causes data
input to be decoded and sent out
to addressed digit

Note:
3. CS has a special "mid-level" sense circuit that establishes a test mode if it is held near 3V (or several msec. Inadvertent Jriggering of
this mode can be avoided by pulling it high when inactive. or ensuring frequent activity.

6-86

ICM7231/32/33/34
ICM7233 PARALLEL INPUT ALPHA DISPLAY
TERMINAL

_._--- -

PIN
NO.

DESCRIPTION

t

DO
01
D2
D3
D4
05

30
31
32
33
34
35

L,,,' SigoiLl,,",

AO
A1

37
38

Least Significant} Address Inputs
Most Significant

CS1
CS2

39
1

Chip Select Inputs
(Note 3)

1--._-----"

6 Bit IASCII)
Data Inputs

FUNCTION
Input
Data
See
T'able 4

HIGH = Logical One (1)
LOW = Logical Zero (0)

Most Significant _
Input Add,
See Table 5
Both inputs LOW load data into
input Iqtches, Rising edge of
either input causes data to be
latched, decoded and sent out to
addressed character.

, Note:
3 CS1 has a special "mid-level" sense circuit that establishes a test mode if it is held near 3V for several msec. Inadvertent triggering of this
mode can be avoided either by pulling it high when inactive, or ensuring frequent activity,

ICM7232 and ICM7234 SERIAL DATA AND ADDRESS INPUT
---,---_.

TERMINAL

PIN
NO.

Data Input

38

Data

WRITE Input

39

Decode, Output, and Reset Strobe

-"

Data Clock
Input

1

DESCRIPTION

FUNCTION

+ Address Shift Register Input

Data Shift Register and Control
Logic Clock

Positive going edge advances
data in shift register,
ICM7232: Eleventh edge resets
shift register and control logic,
ICM7234: Tenth edge resets shift
register and control logic,

Handshake Output

Output LOW when correct number
of bits entered into shift
register; ICM7232 8, 9 or 10 bits
ICM72349 bits

DESCRIPTION

FUNCTION

Negative end of on-chip resistor
string used to generate intermediate
voltage levels for display,
Shutdown Input.

Display voltage control. When
open lor less than 1V from V+)
chip is shutdown; oscillator stops,
all display pins to V+

C---'----

DATA
ACCEPTED
Output

37

HIGH = Logical One (1)
LOW = Logical Zero (0)
When DATA ACCEPTED Output
is LOW, positive going edge of WRITE
causes data in shift register to
be decoded and sent to addressed
digit, then shift register and
control logic to be reset.
When DATA ACCEPTED Output
is HIGH, positive going edge of
WRITE triggers reset only,

ALL DEVICES
TERMINAL
Display
Voltage VDISP

L-,

--

PIN
NO.
2

Common
Line Driver
Outputs

3,4,5

Segment
Line Driver
Outputs
Vt
GND

6·29
6·35
40
36

Drive display commons, or rows.

IOn ICM7231/33)
(On ICM7232/34)

Drive display segments, or
columns,

Chip Positive Supplv
Chip Ground

6·87

ICM7231/32/33/34
TRIPLEXING (1/3 MULTIPLEXING)
LIQUID CRYSTAL DISPLAYS
Figure 1 shows the connection diagram for a typical
7-segment display font with two annunciators such as
would be used with an'ICM7231 or ICM7232 numeric
display driver. Figure 2 shows the voltage waveforms of
the common lines and one segment line, chosen for
this example to be the "Y" segment line. This line
intersects with COM1 to form the "a" segment, COM2
to form the "g" segment and COM3 to form the "d"
segment. Figure 2 also shows the waveform of the "Y"
segment line for four different ON/OFF combinations
of the "a", "g" and "d" segments. Each intersection
(segment or annunicator) acts as a capacitance from
segment line to common line, shown schematically in
Figure 3. Figure 4 shows the voltage across the "g"
segment for the same four combinations of ON/OFF
segments in Figure 2.
The degree of polarization of the liquid crystal material
and thus the contrast of any intersection depends on
the RMS voltage across the intersection capacitance.
Note from Figure 4 that the RMS OFF voltage is always
Vp/3 and that the RMS ON voltage is always 1.92 Vp/3.

DJ

<

I

-

-

I .i I

¢,

-

-

-

-

-

-

-

-

- -

-

•

-

-

-

I ., I

¢;

-

-

-

-

-

-

V'
VH

-

-

-

VL

- VOISP

I I I I I I I

COM 2if=1----;...::;-J.- --;.;,~~:
I- - ..I--.J. -

I I I I I I I

, ON CHIP
RESISTOR STRING

-- --- ----------b~ISP

V'I

-"15Kfl

I I I I I I --v
I,
----------

VH

~75Kfl

v,

-

'SEGME;~
,.dOFF

-

-

-

-

-

-

-

-

-

-

-

-

-75Kfl

VOISP

I I I I I I I,

-8- ---tl_________ C~'SP
-

-

-

-

VOISP

~H

-

TYPICAL
SEGMENT LINE
WAVEFORMS
(SEGMENT
LINE "y")

--

J - - ____-_ -~~~ISP

I I I I I I I

ALLON

l-=-=-=-=--t-----~-----~~
t
- ' _ ' - -_ _ _ _ _
&_

-, -

-

-

-

VOISP

NOTE: ifJl. r/>2. ¢3 - COMMON HIGH WITH RESPECT TO SEGMENT.

rf;{,

1>i. ¢;i -

COMMON LOW WITH RESPECT TO SEGMENT.

COM 1 ACTIVE DURING 4'1 ANDr/>l'
COM 2 ACTIVE DURING 3 AND rl>J'

Figure 2. Display Voltage Waveforms

x

v

f

z _______ SEGMENT
LINES

I

I

I
I
I

I
I
I
I

I

I
I
I
IC

I

b

COM 1

COM 2

I
, I
I
I
I
I

LH
COM 3

I
I
I
I

-

I
I
: RH

I

RH
COMMON LINE CONNECTION

Figure 1. Connection Diagrams for Typical 7-Segment Displays

Figure 3. Display Schematic

6·88

PIN 2

INPUT

I I I I I I I
~~~~ ~-------F -~~

v

SEGMENT LINE CONNECTION

WAVEFORMS

COM3]-------p - -- ----~~:

All members of the ICM7231/ICM7234 family use an
internal resistor string of three equal value resistors to
generate the voltages used to drive the display. One end
of the string is connected on the chip to V+ and the other
end (user input) is available at pin 2 (VDISP) on each
chip. This allows the display voltage input (VDISP) to be
optimized forthe particular liquid crystal material used.
Remember that Vp = V+ - VDISP and should be three
times the threshold voltage of the liquid crystal material used. Also it isvery important that pin 2 never be
driven below ground. This can cause device latchup
and destruction of the chip.

LH

COMMON LINE

v,

L

- - - - - - - - -1-..J - - - VOISP

For a 1/3 multiplexed LCD, the ratio of RMS ON to OFF
voltages is fixed at 1.92, achieving adequate display
contrast with this ratio of applied RMS voltage makes
some demands on the liquid crystal material used.
Figure 5 shows the curve of contrast versus applied
RMS voltage for a liquid crystal material tailored for VP
= 3.1V, a typical value for 1/3-multiplexed displays in
calculators. Notethat the RMS OFF voltage Vp/3 = 1V is
just below the "threshold" voltage where contrast
begins to increase. This places the RMS ON voltage at
2.1V, which provides about 85% contrast when viewed
straight on.

x

.2
-------,-r
COM 1D
L:::t
I ., I

ICM7231/32/33/34
Vg'" VB - VCOM 2 (DIFFERENCE BETWEEN SEGMENT
LINE b AND COM 2 VOLTAGES)

I
. -

91

I

0,

I

<13

I

9"

-

-

-

-

-

-

-

I

I

0,'

-

-

03'

-

I

-

Vp "" V+ - VOISP

-

-Cff_

'IT - n.L _LJ _ L.l _

ALL OFF -

-

-

-

-

-

-

-

-

-

-

0

-

-

g,d

-

-

'O~~ - -

-

-

-

-

-

-

-

-

-

-

SEGMENT PEAK TO
PEAK VOLTAGE
VRMS =

Yf

VRMS =

~

= VRMS OFF

-' - -Vp

I I I I I I I

- -

"" COMMON AND

+Vp

-

-

+Vp

-I _____ EO

=VRMSOFF

APPLIED VOLTAGE (VRMS)

Figure 5. Contrast vs, Applied RMS Voltage
6

r- --r-r-+_1I 1I II

5e----

VOLTAGE CONTRAST RATIO ""

V RMS ON ==
VRMS OFF

Iff "" 1.92

13

-

-

'-- -

-

r-

NOTE: 01.92,03 - COMMON HIGH WITH RESPECT TO SEGMENT.

1

~E~K

V6LTAGE
FOR 90% CONTRAST-I-

o

-10

r-

--

II I i1--tJ.
1 I
r-PEAK VOLTAGE

FOR 10% CONTRAST

I

()1, ()2, 93 - COMMON LOW WITH RESPECT TO SEGMENT.
COM 1 ACTIVE DURING ',)1 AND <,:,,'

-

~ri

10

rll

I

I I I I
I 20I I 30I

40

50

COM 2 ACTIVE DURING <)2 AND ()2'
AMBIENT TEMPERATURE (OC)
COM 3 ACTIVE DURING ,'3 AND

,~3'

Figure 6. Temperature Dependence of LC Threshold
Figure 4. Voltage Waveforms on Segment g (Vg)

A more important effect of temperature is the variation
of threshold voltage. For typical liquid crystal materials
suitable for multiplexing, the peak voltage has a temperature coefficient of -7 to -14 mV/o C. This means that as
temperature rises, the threshold voltage goes down.
Assuming a fixed value for Vp, when the threshold voltage drops below Vp/3 OFF segments begin to be visible. Figure 6 shows the temperature dependence of
peak voltage for the same liquid crystal material of
Figure 5.

TEMPERATURE EFFECTS AND
TEMPERATURE COMPENSATION
The performance of the IC material is affected by
temperature in two ways. The response time of the
display to changes in applied RMS voltage gets longer
as the display temperature drops. At very low
temperatures (-2DOC) some displays may take several
seconds to change to a new character after the new
information appears at the outputs. However, for most
applications above DOC this will not be a problem with
available multiplexed LCD materials, and for lowtemperature applications, high-speed liquid crystal
materials are available, One high temperature effect to
consider deals with plastic materials used to make the
polarizer. Some polarizers become soft at high
temperatures and permanently lose their polarizing
ability, thereby seriously degrading display contrast.
Some displays also use sealing materials unsuitable
for high temperature use. Thus, when specifying dis. plays the following must be kept in mind: liquid crystal
material, polarizer, and seal materials.

For applications where the display temperature does
not vary widely, Vp may be set at a fixed voltage chosen
to make the RMS OFF voltage, Vp/3, just below the
threshold voltage at the highest temperature expected.
This will prevent OFF segments turning ON at high
temperature (this at the cost of reduced contrast for ON
segments at low temperatures).
For applications where the display temperature may
vary to wider extremes, the display voltage VDISP (and
thus Vp) may require temperature compensation to
maintain sufficient contrast without OFF segments
becoming visible.
6-89

ICM7231 132/33/34
DISPLAY VOLTAGE AND
TEMPERATURE COMPENSATION
OPEN

These circuits allow control of the display peak voltage
by bringing the bottom of the voltage divider resistor
string out at pin 2. The simplest means for generating a
display voltage suitable to a particular display is to connect a potentiometer from pin 2 to GND as shown in
Figure 7. A potentiometer with a maximum value of
200 k!l should give sufficient range of adjustment to suit
most displays. This method for generating display voltage should be used only in applications where the
temperature of the chip and display won't vary more
than ±5° C (±9° F), as the resistors on the chip have a
positive temperature coefficient, which will tend to
increase the display peak voltage with an increase in
temperature. The display voltage also depends on the
power supply voltage, leading to tighter tolerances for
wider temperature ranges.

.•

40

+

36

.,:-

-::leM

72317234

Figure 7 Simple Display Voltage Adjustment

v'

Figure 8(a) shows another method of setting up a display voltage using five silicon diodes in series. These
diodes, 1N914 or equivalent, will each have a forward
drop of approximately 0.65V, with approximately 20!lA
flowing through them at room temperature. Thus, 5
diodes will give 3.25V, suitable for a 3V display using the
material properties shown in Figures 5 and 6. For higher
voltage displays, more diodes may be added. This circuit provides reasonable temperature compensation, as
each diode has a negative temperature coeffici.ent of
-2 mV/oC; five in series gives -10 mV/oC,not far from
optimum for the material described.

[8

2 VOISP

200kS?

lN914

401---+5

2 VOISP

DIODES

361----,
leM

72317234,

40kil

Figure 8(a) String of Diodes

The disadvantage of the diodes in series is that only
integral multiples of the diode voltage can be achieved.
The diode voltage multiplier circuit shown in Figure 8(b)
allows finE'-tuning the display voltage by means of the
. potentiometer; it likewise provides temperature compensation since the temperature coefficient of the
transistor base-emitter junction (about -2 mV/o C) is also
multiplied. The transistor should have a beta of at least
100 with a collector current of 10 !lAo The inexpensive
2N2222 shown in the figure is a suitable device.

v'
40

2 VOISP

36
200kn
POTENTIOMETER'

For battery operation, where the display voltage is generally the same as the battery voltage (usually 3-4.5V),
the chip may be operated at the display voltage, with
VDISP connected to GND. The inputs. of the chip are
designed such that they may be driven above V+ without
damaging the chip. This allows, for example, the .chip
and display to operate at a regulated 3V, and a microprocessor driving its inputs to operate with a less well
controlled 5V supply. (The inputs should not be driven
more than 6.5V above GND under any circumstances.)
This also allows temperature compensation with the
ICL7663, as shown in Figure 9. This circuit allows independent adjustment of both voltage and temperature
compensation.

2N2222

leM

72317234

40kn

Figure 8(b) Transistor-Multiplier
Figure 8 Diode-based Temperature Compensation
+5V

1 -_-;=:::1,-...,

0-

VI~

v+

VOUT1

VOUT2

1.8Mfl

ICL7663

VSETr-----..
300kO

Vrc

ICM7233

Figure 9 Flexible Temperature Compensation

6-90

+5

ICM7231 132/33/34
DESCRIPTION OF OPERATION
PARALLEL INPUT OF DATA
AND ADDRESS (ICM7231, ICM7233)

The rising edge of the Chip Select also triggers an onchip pulse which enables the address decoder and
latches the decoded data into the addressed digit!
character outputs. The timing requirements for the
parallel input devices are shown in Figure 12, with the
values for setup, hold, and pulse width times shown in
AC Characteristics on page 3. Note that there is a
minimum time between Chip Select pulses; this is to
allow sufficient time for the on-chip enable pulse to
decay, and ensures that new data doesn't appear at the
decoder inputs before the decoded data is written to the
outputs.

The parallel input structure of the ICM7231 and
ICM7233 devices is organized to allow simple, direct
interfacing to all microprocessors, see block diagrams
Figures 10 and 11. In the ICM7231, address and data
bits are written into the input latches on the rising edge
of the Chip Select input. In the ICM7233, the two Chip
Selects are equivalent; when both are low, the latches
are transparent and the data is latched on the rising
edge of either Chip Select.

08

07

06

X Y Z

X Y Z

X Y Z

DO

05

X Y

Z

X Y Z

02

03
X

Y

Z

X Y Z

x

0'
Y Z

SEGMENT

LINE
DRIVERS
3WIDE

OUTPUT
LATCHES
9WIOE

VH

g~~~!~

VL

VOLTAGE
LEVEL
GENERATOR

VOISP

H+---'---PIN 2 (INPUT)

COM 1

COMMON
LINE

DRIVER

S

I
DATA INPUTS

Figure 10. iCM7231 Block Diagram

6-91

COM 2

COM 3

ICM7231/32/33/34

CHAR 4

CHAR 3

CHAR 2

CHAR 1

UVWXYZ

UVWXYZ

UVWXYZ

UVWXYZ

SEGMENT

LINE
V'

DRIVERS
6WIDE

ON CHIP

OUTPUT
LATCHES
18 WIDE

VH

DISPLAY
VOLTAGE

lEVEL
GENERATOR

18

18

~H_-- g g

*+
/

N /'
0 ~ /

M J

DIGIT
SELECTED

ICM
7234
ONLY

A2

Al

AO

0

0

0

01

0

0

1

02

0

1

0

03

0

1

1

04

1

0

0

05

1

0

1

NONE

1

1

0

NONE

1

1

1

NONE

/

ADDRESS
DECODING
(lCM7233/34)

'~

?

DATA DECODING
6 " BIT ASCIl-18 SEGMENT
IICM7233/34)

TYPICAL APPLICATIONS

[I
8M8
MICROCOMPuTER

v'

v'
'I vee
40

Voo'l

26

o-f

20P~

~}
g
I

20 Vss

P10 27

20SCI

I

I
'1734

30Se2

200T

-----1ffr-

P20
4 RESET

V'-

P 26,37

sss

P2738

1 TO

DBO 12
I
I
BUS:
I
I
DB719

-=INPUTS{= 39T1

aM

11
ALE

23
24

v'

~,
~

t-

1-_

~T~

2N2222

1
t/OPDRT

GND

~~~-

~~

7 EA

TEMPE RATURE
COMPE NSATION

27

27

I

6MHzD

---l

~

0
40

v'

36GND
DO

I/O PORT 2

3-29

2
VOISP

ICM7233A

-------05 AO A 1 CS2 CS1

30 ~------~·35 3738 39 1

v'
GND

40

v+

36GND

2
VDISP

ICM7233A

00--------05 AOA1CS2CS1
30 - - - - - - - - 35 37 38 39 1

J

1

3-2.

j

1

200kr/.
VDISP

AOJ.

}~ro

EXTER NAL
MEMO AYAND
OTHER PERIPHERALS

9 26 108

J. II

1-1PSEN

.

liD

'PULL-UP RECOMMENDED ON CSi. SEE NOTE 3.

V·

lMn

Figure 21, 8048/1M80C48 Microcomputer with 8 Character 16 Segment ASCII Tr~x Liquid Crystal Display. The two bit ch'aracter address
is merged with the data and written to the display driver under the control of the WR line. Port lines are used to either select the target
driver. or deselect all of them for other bus operations.

6,98

ICM7231/32/33/34

IT ~~TF F~C;

MC8802
MICROPROCESSOR

39 EXTAL Vee 36

sa

OCMHz

RE 36

v'

v'- oov'

v'

3-29
2
DISPLAY VOISP

-

00 iiESE't

30-35 37 36 39

-

8NMI

'Okll _

DATA
BUS

3MR

26-33

-

7BA

TI!!I'
4

ADD 9-20
BUS 22-26
E37

RiW
34

I

~

11 - , -]

I

-3 -31
:

Ie:

VMA

5

I

GND

Do-o.t

8

I

2

Ag,

,

A,

A,

-

ICM7233BIPL

Do-o.ts

2
AO,
A'

'8
I

'8

27

27

~A~:DADD ef2 CS,

2 HALT

T r-L L_

v'

27

2N2222

VDISP
ADJ.
200k1l

ICM7233AlPl

38XTAL

~

Iv'

27

8
Vee

V..

T IL_
_ -L

_

TEMPERATURE
COMPENSATION

'I

~
1,21
~

I

-L

WITH RAM

29 V:
ADDRESS
2'-28
PORT

L---

J~ISPLAV
8

7

A3

ICM7233BIPL

e

D.-ot

2

Ag,
A,

f-t
A.

ICM7233BIPl

Do-ot~~,
A'

2

,

-

AS

401<<2

-=-

}'TOOTH ER
PARTS OF
SYSTEM

I 2-5, '8,30-33, 36-00 ~7'LSOO

U
Om

,

-

V·
'Mil
STORAGEENABlE

(SEE NOTE 3)

OTHER I/O

8-'5 CP,35 I===}CONTROL
DATA CP,34

m'8 ~}

20E

CIQ'9

8CSO
7 RiW C
'7
36 Vss
IRQ

I

-b

COUNTERITIMER

Me....... _

ROM I/O TIMER

Figure '22. MC6802 Microprocessor with 16 Character 16 Segment ASCII liquid Crystal Display. The peripheral device provides ROM and
Timer functions in addition to port line control of the display bank, Individual character locations are addressed via the address bus, Note
that VMA is not decoded on these lines, which could cause problems with the TST instruction,

6-99

ICM7231132/33/34

~,*,~m~I~/~~
Iii
l ILJ ~ IZIS ILJ~ ILJ Iii

II

I

ir

I

ICM7233

-

eS2

Cs1

ICM7233

A,

AO

-

Do-DS

-es,

eS2

I

Ao

A,

00-05

6

.A
~.

6

+5V

TO Os ON
EPROM

{

rl

750kn

+ .

,k

8 x100kn
MC14049B

V+

''--

~ Re

2

O.'"F*

4
leM 7240

F

OR

.....
..... .....
.....

8

RESET

GND

to.

..... .....

.....

'6

+ 5 V - TRIG

CD40498

32

64
'28

I
A5
A6
A7
AS

I
A4

AJ

A2

A,

Ao

00-00

IM6654

06

~

Ei

-

.,r-

F

,

Re
ICM7240

if
c: c: c:

TB I/O

2

~ ~~ ~

4

+ 5 V - TRIG
RESET

,

GND

Figure 23. EPROM-Coded Message System. This circuit cycles through a message coded in the EPROM, pausing at the end of each
line, or whenever coded on Q6.

6-100

.O~OIL

ICM7231/32/33/34
~

~

I FREO. RATIO I

FREQUENCY

I

B• C••
~I

ClORDCICI

C.. D. L•• Lt. D. LI.
OVER
RANGE

800-3

ICM7231CF

AN2 AN1

Ao

CS

A,

A,

BCO
OP

INPUT A

+5V

FUNCTION

ICM7226A

INPUTB-

10K
C04532

GS

Figure 24. 10 MHz Frequency/Period Pointer with LCD Display. The annunciators show function and the decimal points indicate the
range of the current operation. The system can be efficiently battery operated.

08

07

06

04

05

03

CICIDRCIC'

LI •• LI •• Lt •• L•• YLI •• LI.

01

02

.Lt.

ICM7231AF/BF
TOP VIEW

Figure 25. "Forward" Pin Orientation and Display Connections.

6-101

[I

COM 1
COM 2
COM 3

m

ICM7231 132/33/34
010

D9

08

07

06

05

I FORWARD I

t::.

t::.

6.

D4

03

I STOP I

02

01

'B BI
!WAIT!

(][]

DO
C' ··B ·C'
D _. _.
O.
D. . L'.L.
L'. D.

COM 1
COM 2
COM 3

PCB TRACES UNDER PACKAGE

II!iIII ________________________________

F_ig_u_r_e_2_6_,_'_'R_e_v_e_rs_e_"_p_i_n_o_r_ie_n_t_at_io_n__a_n_d_D_i_s_p_la_y_c_o_n_n_e_c_t_io_n_s_______________________________

CHARACTER

CHARACTER

CHARACTER

CHARACTER

4

3

2

1

v
X

ICM7233AFiO

W
V

U

lCO

01 E MOUNTS UNDER LCD

TOP VIEW IBOTH DIE AND lCD)

Figure 21- "Forward" Die. Pad Orientation and Typical Triplex Alphanumeric Display Connections

6·102

0

S;;::<~2<~;:;;<

1-, "~" "" --

N

3Z

COM2
COM 1

3Y

VDlSP

3X

...,3:M
3V

Co>

3"

--t
COM 3

4X

2"

~

!

4Y

V·

52

o

COM2
COM 1

5Y

~

6l

~

Sy

...

6X

~!='

OS
v'

4Y

~

"W

I

AD

GND _ _ _

GND

CIO«>=»====
N
-< X ~ ~ g ~ ~ B

.p..p..,I:oOCCClCO

::ii!:

<

c:

<=>

...

N

....

.,1:0

U\

....

~~

I

7X

~

W

"::t "W

3~

7Y

AD

4X

::D
l>

~

3 ?

1Z

4l

"
C>

0

I <

VDISP

5X

-n

"0-I I:

N

NX<
=X
=
_ XN
_
_C
N

~

~~~~~~~~~

II
=

I
=

IF'

ICM7235
.Four Digit
Non-Multiplexed Vacuum
Fluorescent Display
Decoder/Drivers
FEATURES

DESCRIPTION

• 28 high voltage segment drivers provide four
7-segment digits

The ICM7235 family of display driver circuits provides the
user with a single chip interface between digital logic or
microprocessors to non-multiplexed 7-segment vacuum
fluorescent displays.

• Multiplexed BCD input(7235)

The chips provide 28 high voltage open drain P-channel
transistor outputs organized as four 7-segment digits.
The devices are available with two input configurations. The
basic devices provide four data-bit inputs and four digit
select inputs. This configuration is suitable for interfacing
with multiplexed BCD or binary output devices, such as
the Intersi! ICM7217, ICM7226 and ICL7135. The
microprocessor interface devices (suffix M) provide data
input latches and digit select code latches under control of
high-speed chip select inputs. These devices simplify the
task of implementing a cost-effective alphanumeric
7-segment display for microprocessor systems, without requiring extensive ROM or CPU time for decoding and
display updating.

• High speed processor interface (7235M)
• 7-segment hex (O-g, A-F) or Code-B (O-g, dash, E,
H, L, P, blank) output versions available
• Display blanking input
• All devices fabricated using high density
MAX-CMOSTM LSI technology for very low-power,
high-performance operation
• All inputs fully protected against static discharge

PIN CONFIGURATIONS (outline dwg PL)

The standard devices available will provide two different
decoder configurations. The basic device will decode the
four bit binary input into a seven-segment alphanumeric
hexadecimal output (0-9, A-F). The "A" versions provide the
same output code as the ICM7218 Code "B" (0-9, dash, E, H,
L, P, blank). Either device will correctly decode true BCD to
seven-segment decimal outputs.

V+l~40Dl
El

2

DISPLAY ON/OFF

~

37 At

5

36 Ground

35 y+

.2 •

~~~
02
E2
G2
F2
AJ

•
10
11
12
13

.,

39 C1

~:rf
ICM

7235135A

5534 DS3
D54f Digit
32 DS2 Select

92 O.ta
3D2829 .'f
81 Inputs

~!m

21 80

D3 16

25 G4
24 E4

23 04
22 C4

F3 19
A4 20

21 84

v+r,-~

40 01

ORDERING INFORMATION
~ Cl
38 81

El 2
Gl ,
F1 4
DISPLAVOJiIOFF 5

37 At

36 Ground

Order Part Number

Output Code

Input Configuration

ICM72351PL

Hexadecimal

Multiplexed 4-6it

I

ICM7235A IPL

Code 6

Multiplexed 4-6it

3D 83 }

ICM7235M IPL

Hexadecimal

Microprocessor Interface

ill 80

ICM7235AM IPL

Code 6

Microprocessor Interface

'2 •

35

.2
C2
02

~

~~m
F2 12
A3 13

~~ ~
03 16
E3 17

~~ ~
A4 20

The ordering information shows the four standard devices of
the ICM7235 family and their markings, which serve as part
numbers for ordering purposes.

26 F4

~~m

7
8
•

All devices in the ICM7235 family are packaged in a standard
40-pin plastic dual-in-line package.

~ OS1 Inputs

ICM
7235M/35AM

:-J
v+

!~ ~:!
fg

82
28 81
26
25
24
23
22
21

F4
G4
E4
04
C4
84

CHIP SELECT INPUTS

DIGIT SELECT CODE BITS

DATA INPUTS

An Evaluation Kit is available for this part.
Order number ICM7235 EV/Kit.

6-104

ICM7235
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 1) .............. 0.5 W @ + 70°C
Supply Voltage (v+ -Ground) .................. 6.5 Volts
Input Voltage (Note 2) .......... V+ +0.3V. Ground -0.3V

Output Voltage (Note 3) . . . . . . . . .. . . . . . . . . . . .. V+ - 35V
Operating Temperature Range. . . . . . . . .
-20°C to +85°C
Storage Temperature Range. . . . . . . . .. -55°C to +125°C

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifica·
tions is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS
All parameters measured with V+

=5V, T A =25°C

PARAMETER

SYMBOL

Operating Supply Voltage Range

VsuPP
1+

Supply Current

1+

Supply Current
Segment OFF Output Voltage
Segment OFF Leakage Current
Segment ON Current

CONDITIONS

VSEG

MIN

TYP

MAX

UNIT

4

5

6

V

10

50

pA

100

mA
V •

Measured V+ to Ground
Test circuit; display blank or OFF
Measured V + to Display
ISLK = 1OI'A

30

I LS

VSEG = V+ -30V

ISEG

VSEG=V+ -2V

1.5

2.5

CONDITIONS

MIN

TYP

0.1

10

!

pA
mA

INPUT CHARACTERISTICS
PARAMETER

SYMBOL

Logical "1" Input Voltage

V,H

Referred to Ground

Logical "0" Input Voltage

V,L

Referred to Ground

I'LK
C'N

Pins 27-34

Input Leakage Current
Input Capacitance
ON/OFF Input Leakage
AC CHARACTERISTICS -

Pins 27-34

UNIT

V
±0.1

1.5

V

±1

pA
pF

5

I'LK(ON/OFF) All Devices
C'N(ON/OFF All Devices

ON/OFF Input Capacitance

MAX

3

±0.1
200

±1

pA
pF

MULTIPLEXERD INPUT CONFIGURATION

Digit Select Active Pulse Width

tsa

1

I's

Data Setup Time

tds

500

ns

Data Hold Time

tdh

200

ns

2

I's

200

ns

Inter-Digit Select Time
AC CHARACTERISTICS -

Refer to Timing Diagrams

tids
MICROPROCESSOR INTERFACE

Chip Select Active Pulse Width

tcsa

Other Chip Select either held active,
or both driven together

Data Setup Time

tdsm

100

Data Hold Time

tdhm

10

Inter-Chip Select Time

tics

2

ns
0

ns

!'5

NOTE 1. ThiS limit refers to that of the package and Will not be realized dUring normal operation.
NOTE 2: Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any input terminal to a
voltage in excess of V+ or ground may cause destructive device latch-up. For this reason, it is recommended that inputs from external sources operating on a different power supply be applied only after the device's own power supply has been established,
and that on multiple supply systems the supply to the ICM7235 be turned on first.
NOTE 3: This value refers to the display outputs only.

6-105

II

tCM7235
INPUT DEFINITIONS
In this table, V+ and ground are considered to be normal operating input logic levels. Actual input low and high levels are
specified under Operating Characteristics. For lowest power consumption, input signals should swing over the full supply.
INPUT

TERMINAL

CONDITION

FUNCTION
Ones (Least Significant)

BO

27

V+ = Logical One
Ground = Logical Zero

B1

28

v+ = Logical One
Twos
Ground = Logical Zero

B2

29

V+ = Logical One
Fours
Ground = Logical Zero

30

v+ = Logical One
Ground = Logical Zero

1-"'

63

Data Input Bits

"--C--

Eights (Most Significant)

V+ =OFF,
Ground =ON

5

ON/OFF

--

Display ON/OFF Input

ICM7235, ICM7235A
MULTIPLEXED·BINARY INPUT CONFIGURATION
INPUT

TERMINAL

D1

31

D2

32

D3

FUNCTION

CONDITION

D1 (Least Significant) Digit Select

=

33

,---_.,-

D2 Digit Select

V+ Active
Ground = Inactive

,~.-~.---.-----

..- - - - - -

D3 Digit Select
.----~'--'.-.~'-.--~"

D4

34

...- - : - -

, D4 (Most Significant) Digit Select

ICM7235M, ICM7235AM
MICROPROCESSOR INTERFACE INPUT CONFIGURATION

....-->.,,,-

",""~,.~-,,"~

INPUT

DESCRIPTION

TERMINAL

CONDITION

FUNCTION
~-",""""""",,,,","=

DS1

Digit Select
Code Bit 1 (LSB)

31

DS2

Digit Select
Code Bit 2 (MSB)

32 - -

CS1

Chip Select 1

33

CS2

Chip Select 2

34

DS2 & DS1 serve as a
DS2, OS'I = 00 selects
DS2, OS1 = 01 selects
DS2, OS1 = 10 s.elects
DS2, OS1 = 11 selects

V+ = Logical One
Ground = Logical
Zero

two·bit Digit Select Code Input
04
03
D2
01
---------~----.-~'---

When both CS1 and CS2 are taken to ground, the data at
the Oata and Digit Select code inputs are written into the
input latches. On the rising edge of either Chip Select, the
data is decoded and written into the output latches,

V+ = Inactive
Ground Active

=

ICM7235 TYPICAL DC VACUUM FLUORESCENT DISPLAY CONNECTION
OPEN·DRAIN HIGH·vat TAGE P·CHANNEL TRANSISTOR OUTPUTS

10·30V
TYP

DEPENDING
ON
DISPLAY

t-l-~--"+i.-.,.;f~3>5
~l\t--~~~~"l--T
-=-=-

+

+'

4·6V

_

ICM7235
/

' - - - GROUND

36

YL~G

"1
L __
_

abc

d

€

f

9

V

1.5·2.5V
DEPENDING ON
' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,__D~IS_P_LA_Y_._~ __

6·106

/

. . '4:-

---~--- -.~

~---;:jlll-::---'-

NEG. Electronics, Inc.
Models FIP4F8S and FIP5F8S

Ll-/GRID
DIRECTLY HEATED

_ ~ __ ~ _~ _~_ ~ _'- _____ ~
1_/~~I~::'E~~VCE:~Hp~DE

~

VACUUM FLUORESCENT DISPLAYS (4 DIGIT)

PHOSPHOR·COATED
ANODES

DC FILAMENT
DISPLAY

:

.D~DIL

ICM7235
ICM7235/35A

D.

OJ

02

01

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

SEGMENT OUTPUTS

DISPLAY
6tiiIO~F

DATA
INPUTS

DIGIT
SELECT
INPUTS

ICM7235M/35AM

D'

SEGMENT OUTPUTS

0'

SEGMENT OUTPUTS

02

01

SEGMENT OUTPUTS

SEGMENT OUTPUTS

OISPLAY

ONIOFF

DATA
INPUTS

2-81T
DIGIT SELECT
CODE INPUT

CHIP SELECT 1
CHIP SELECT 2

6,107

ICM7235
Characteristics for data setup, hold, and interdigit select times must be met to ensure correct
output.
The ICM7235M and AM devices are intended to
accept data from a data bus under processor
control.
In these devices, the four data input bits and the
2-bit Digit Select code (DS1 pin 31, DS2 pin 32) are
written Into in~buffer latches when both Chip
Select inputs (CS1 pin 33, CS2 pin 34) are taken to
ground. On the rising edge of either Chip Select
input, the content of the data input latches is
decoded and stored in the output latches of the
digit selected by the contents of the select code
latches. A select code of 00 writes into 04, 01
writes into 03, 10 writes into 02 and 11 writes into
01. The timing relationships for inputting data
are shown in Figure 3, and the chip select pulse
widths and data setup and hold times are specified under Operating Characteristics.

CIRCUIT DESCRIPTION
Each device in the ICM7235 family provides
signals for directly driving the anode terminals
of a four-digit, 7-segment non-multiplexed vacuum
fluorescent display. The outputs are taken from
the drains of high-voltage, low-leakage P-channel
FETs, each capable of withstanding> -35V with
respect to V+. In addition, the inclusion of an
ON/OFF input allows the user to disable all segments by connecting pin 5 to V+; this same in·
put may also be used as a brightness control by
applying a signal swinging between V+ and
ground and varying its duty cycle.
The ICM7235 may also be used to drive nonmultiplexed common cathode LED displays by
connecting each segment output to its cor·
responding display input, and tying the common
cathode to ground. Using a power supply of 5V
and an LED with a forward drop of 1.7V results in
an "ON" segment current of about 3mA, enough
to provide sufficient brightness for displays of
up to 0.3" character height.
Note that these devices have two V+ terminals;
each should be connected to the positive supply
voltage. This double connection is necessary to
minimize the effects of bond wire resistance,
which could be a problem due to the high
display currents.

m

TEST CIRCUIT
5V

v+

Input Configurations and Output Codes
The standard devices in the ICM7235 family ac·
cept a four-bit true binary (i.e., positive level
logical one) input at pins 27 through 30, least
significant bit at pin 27 ascending to the most
significant bit at pin 30. The ICM7235 and
ICM7235M decode this binary input into a 7segment alphanumeric hexadecimal output,
while the ICM7235A and ICM7235AM decode the
binary input into the same 7-segment output as
the ICM7218 "Code B," i.e., O-g, dash, E, H, L, P.
blanK. I nese coaes are shown explicitly in Table 1
Either decoder option will correctly decode true
BCD to a 7·segment decimal output.
These devices are actually mask-programmable
to provide any 16 combinations of the 7-segment
outputs decoded from the four input bits. For
larger quantity orders, (10Kpcs. minimum)
custom decoder options can be arranged. Contact your Intersil Sales Office for details.
The ICM7235 and ICM7235A devices are intended
to accept multiplexed binary or BCD output.
These devices provide four separate Digit lines
(least significant digit at pin 31 ascending to
most Significant digit at pin 34), each of which
when taken to· a positive level decodes and
stores in the output latches of its respective
digit the character corresponding to the data at
the input port, pins 27 through 30. More than one
Digit select may be activated simultaneously
(which will write the same character into all
selected diQits), although the timing requirementsshown in Figure 2 and under Operating

SEGMENTS OFF

V

Ground = SEGMENTS ON

36

V· 35
34

=

V

DIGIT.ICHIP { 33
SELECT
INPUTS

32

MICROPROCESSOR
VERSIONS

Ground MUL TtPlEXED VERSIONS

"

30
DATA {
INPUTS

29
28

27

20

21

TYPICAL OUTPUT CHARACTERISTICS
-12

-10

·8

-6

-4
0

~

V+

4V

V+

4.SV

-='=

v?r

I--

r-

v~ I - r-

~B
6-108

""'"

~

VI/J.
~...-) VI...
..t.'lll

--

I--

L71

[L/

f-

-

,/

t'!"".

--'L,
2

I

3

4

/

5

8

lOUT

mA

ICM7235
Table 1: Output Codes
DIGIT SELECT

B1

BO

a
a
a
a
a
a
a
a

a
a
a
a

a
a

a

1..'

1

a

1

1

1

a

1

a
a

1

1

a

1

1

1

-,,

,-=,
3
'-',
5
:3-,
,

1

a
a

a

S

'-'0;>

1

a

1

a
a
a
a

1

1

1

1

a

1

1

a
a

1

1

1

a

1

1

1

1

1
1
DATA AND
DIGIT SELECT
CODE

1m

=

DON'T CARE

Figure 3. Microprocessor Interface Input Timing Diagram

SEGMENT ASSIGNMENT

6·109

'-',

B2

ON

Figure 2. Multiplexed Input Timing Diagram

,-,
,,
,?

B3

BINARY

DIGIT SELECT

CODE B
ICM1235A
ICM1235AM

HEXADECIMAL
ICM1235
ICM1235M

DN-l

1

1

1

1

::

'-',
'~

:;
CJ
..J

oJ

",

,0'-,

,-,

,

,=.

..J

-

:,

E

0

,
'-,;:.

,-

(BLANKI

::,-

I

ICM723e
41f2-Digit Counter
With Vacuum Fluorescent
Static Display Drivers
FEATURES

DESCRIPTION

• High frequency counting-guaranteed 15M Hz,
typically 25MHz at 5V
• Low power operation-less than 100/LW quiescent
• Direct 4112 -digit seven-segment display drive for
non-multiplexed Vacuum Fluorescent displays
• STORE and RESET inputs permit operation as
frequency or period counter
• True COUNT INHIBIT disables first counter stage
• CARRY output for cascading four-digit blocks
• Schmitt-trigger on COUNT input allows operation
in noisy environments or with slowly changing
inputs
I
• Leading Zero Blanking INput and OUTput for
correct leading zero blanking with cascaded
devices
• All inputs fully protected against static discharge-no special handling precautions
necessary
• Devices fabricated using MAXCMOS™ process
for high-performance, low power operation

The ICM7236 and ICM7236A devices are high-performance
CMOS 4 Y.-digit counters, including decoders, output
latches, count inhibit, reset, and leading zero blanking circuitry, and twenty-nine high-voltage open drain P-channel
transistor outputs suitable for driving non-multiplexed
(static) vacuum fluorescent displays.
The ICM7236 is a decade counter, providing a maximum
count of 19999, while the ICM7236A is intended for timing
purposes, providing a maximum count of 15959.
The counter section of the two devices in the ICM7236 family
provides direct static counting from DC to 15MHz guaranteed (with a 5V ± 10% supply) over the operating temperature range. At normal room temperatures, the device will
typically count up to 25M Hz. The COUNT input is provided
with a Schmitt trigger to allow operation in noisy environments and correct counting with slowly changing inputs. These devices also provide count inhibit, stofe and
reset circuitry which allows a direct interface with the
ICM7207 devices to implement a low cost, low power frequency counter with a minimum component count.
These devices also incorporate features intended to simplify
cascading in four-digit blocks. The CARRY output allows the
counter to be cascaded, while the Leading Zero Blanking
INput and OUTput allow correct leading zero blanking
between four-decade blocks.

II

The ICM7236 and ICM7236A are packaged in a standard
40-pin dual-in-line plastic package.

PIN CONFIGURATION (outline dwg PL)
v+
E1
G1
F1 4
ON/OFF
A2
B2
C2

01
C1
B1

ORDER PART NUMBER

A1
GROUND

ICM7236AI PL

ICM7236IPL
ICM7236 EVIKIT

v+
STORE
RESET
COUNT
COUNT INHIBIT
LZB OUT
LZB IN
CARRY
1/2·DIGIT
F4

leM

7236/36A
E2
G2
F2
A3
B3
C3
03
E3
G3
F3
A4 20

ORDERING INFORMATION

21

G4
E4
04
C4
B4

6-110

COUNT OPTION

19999
15959
(Evaluation Kit)

ICM7238
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (Note 1) .............. 0.5 W @ + 70·C
Supply Voltage (V+) . . . . . . . . . . . . . . . . . . . . . . . . . . .. 6.5 V
Display Voltage (Note 3) ..................... V+ -35V
Operating Temperature Range. . . . . . . . .
-20°C to +85°C
Storage Temperature Range. . . . . . . . .. -55·C to + 125·C
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS
(All parameters measured with V+ = 5V unless otherwise indicated.)
PARAMETER

MIN

TYP

MAX

3

5

6

V

Test circuit, Display blank

10

50

pA

Output OFF, V = V+ -30V

0.1

Input Pullup Currents

IOlK
Ip

Input High Voltage

V1H

Pins 29,31, 33, 34

Input Low Voltage

V1L

Pins 29, 31, 33, 34

COUNT Input Threshold

VCT

2

V

COUNT Input Hysteresis

VCH

0.5

V

Operating Supply Voltage Range
Operating Current
Display Voltage
Display Output Leakage

SYMBOL

VsuPP
lop

CONDITIONS

V+

V01SP
Pins 29, 31, 33, 34

V=V+ -3V

Output High Current

10H

CARRY (Pin 28), LZB OUT (Pin 30)
VOUT= V + - 3V.

Output Low Current

10L

CARRY (Pin 28), LZB OUT (Pin 30)
VOUT= +3V_

Count Frequency

fcoun!

STORE, RESET Minimum Pulse Width

ts, tw

4.5Vinary
counting or timing, whereas the ICM7250 is optimized for
decimal counting or timing. The ICM7260 is specifically
designed for time delays in seconds, minutes and hours.
All three devices use open drain output transistors, thereby allowing wireAND-ing. Manual programming is easily
accomplished by the use of standard thumbwheel
switches or hardwired connections. The ICM7240/50/60
are packaged in 16 pin CERDIP packages.

• Select output count from
1RC to 255RC (ICM7240)
1RC to 99RC (ICM7250)
1RC to 59RC (ICM7260)
• Monostable or astable operation
• Low supply current: 115/-tA@ 5 volts
• Wide supply voltage range: 2-16 volts
• Cascadeable

GENERAL DESCRIPTION
The ICM7240/50/60 is a family of CMOS Timer/Counter
circuits intended to replace Intersil's ICL 8240/50/60
and the 2240 in most applications. Together with the
ICM7555/56 (CMOS versions of the SE/NE 555/6), they
provide a complete line of RC oscillators/timers/

Applications include programmable timing, long delay
generation, cascadeable counters, programmable
counters, low frequency oscillators, and sequence
timing.

cooot." offedog low", 'opply COH.ot,. wid., ,"pply

PIN CONFIGURATION

ORDERING INFORMATION

(OUTLINE DRAWING JE)

ICM7240, 7250, 7260
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

ICM7240lJE

-20· C to +85· C

16 Lead CERDIP

ICM7250lJE

-20·C to +85·C

16 Lead CERDIP

ICM7260IJE

-20· C to +85· C

16 Lead CERDIP

ICM7240/D

Dice Only

ICM7250/D

Dice Only

ICM7260/D

Dice Only

7250/60
1
1',

2
4
8

10's 1 ' :0

80'

7240

--;-[~PV'
~[
2
4[

2
3

15
14

8[

4

13

16 [

5

12

P
P

RC
MOD·

32[ 6

11 pTRIGGER

64 [

10

7

128[ 8

"'7260 OPEN CIRCUIT

6-116

p:-N/C (7240)
.......CARRY OUT (7250/60)
TB I/O

P
P

HESET

.bGNO

ICM7240/S0/60
ABSOLUTE MAXIMUM RATINGS

NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions above {hose indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for
extended periods may.affect device reliability.

Supply Voltage ............................... 18V
Input Voltage l11
Terminals 10,11,12,13,14 ............. GND -0.3V to
V++0.3V
Maximum continuous output
current (each output) ...................... 50 mA
Power Dissipation 121 ••••••••••••••••••••••• 200 mW
Operating Temperature Range ...... -20°C to +85°C
Storage Temperature Range ...... -55°C to +125°C
NOTES:
1. Due to the SCR structure inherent in the CMOS process, connecting
any terminal to voltages greater than V+ or less than GROUND may
cause destructive device latchup. For this reason, it is recommended
that no inputs from external sources not operating on the same
supply be applied to the device before its supply is established, and
that in multiple supply systems, the supply to the ICM7240/50/60 be
turned on first.
2. Derate at -2 mW;o C above 25° C.

BLOCK DIAGRAM
ICM7240/50/60

MOD'~2-----------------'

RC O--~----------.--~

13

8 STAGE BINARY

OR BCD COUNTER

GND

TB I/O

OUTPUT

1--------8

14

6-117

OUTPUT

OUTPUT

15

ICM7240150/60
ELECTRICAL CHARACTERISTICS
Each of the three devices utilizes an .identical timebase,
control flip-flops, and basic counters, with the outputs
consisting of open drain n-channel transistors. Only the
ICM7250/60 have CARRY outputs.
Test Conditions: Test circuit, V+= 5V, TA = +25°C, R = 10Kfl, C = O.1J.LF, unless otherwise specified.
PARAMETER

SYMBOL

Guaranteed Supply Voltage

V+

Supply Current

1+

CONDITIONS

MIN

300

700

jJ.A

120

500

Il A

TB Inhibited, RC Connected to GND

125

(Exclusive of RC Drift)

Time Base Output Voltage

VOTS

ISOURCE
ISINK

OJ

= 1 mA
= 3,2 mA

Time Base Output
Leakage Current

ITSLK

RC

Mod Voltage Level

VMOD

= 5V
V+ = 15V
v+ = 5V
v+ = 15V
V+ = 5V
V+ = 15V
V+ = 2V }
V+ = 5V

Max Count Toggle Rate
7240

VRST

ft

V
jJ.A

Operating, R = 10K!}, C = 0.1jJ.F
Operating, R = 1M!}, C = 0.11lF

.:,f/':'T

Reset Input Voltage

UNITS

16
125

RC Oscillator Frequency
Temperature Drift

VTRIG

MAX

Reset

Timing Accuracy

Trigger Input Voltage

TYP

2

3,5

Il A

5

%

250

ppm/oC

4,2
0,25

= Ground

V
0,6

V

25

jJ.A

3,5

V+

V

11,0

V

1,6

2,0

V

3,5

4,5

V

1,3

2,0

V

2,7

4,0

CounterlDivider Mode

V+ = 15V

2

'

V
MHz

1
6

MHz

13

MHz

5

MHz

50% Duty Cycle Input with Peak to
Peak Voltages Equal to V+ and GND
Max Counter Toggle Rate
7250, 7260

ft

V+ = 5V
(Counter/Divider Model

Max Count Toggle Rate
7240, 7250, 7260

ft

Programmed Timer -

Output Saturation Voltage

VSAT

Output Leakage Current
MIN Timing Capacitor
Timing Resistor Range

10LK
Ct
Rt

All Outputs except TB Output
V+ = 5V, lOUT = 3.2 mA
V+ = 5V, per Output
V+~

5,5V

V+~

16V

1,5

Divider Mode
0.22

10
1K
1K

100

KHz

0.4

V

1

Il A

22M
22M

pF
!}
!}

TEST CIRCUIT
v'
51-A= AC RUN
B = T. B. INPUT RUN

10K
10K

S2-A = INACTIVE
B = TRIGGER

S3-A = INACTIVE
B = RESET

10K
NOTE: 81-8 INHIBITS THE TIMEBASE SECTION, ALLOWING
TERMINAL 14 TO BECOME THE COUNTER INPUT.
* * TERMINAL 15 IS CARRY OUTPUT FOR 7250/60 DEVICES.
* TERMINALS IS OPEN CIRCUIT FOR 7260.

10K
10K
10K
10K
10K

6·118

ICM7240/S0/60
TYPICAL PERFORMANCE CHARACTERISTICS
RECOMMENDED RANGE
OF TIMING COMPONENT VALUES
FOR ACCURATE TIMING

SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
260
240
220
200

TA ""_20°C

c-

1

-- ----;,....- 1
'BO -_ .._- -- t--

:5a:

/

f-

'60 -

a:

'40

"
~

'20

::>

Ol

100M

=f-~-±1- --f---.- T.7 ~
~- --c---

Q

'OM

,M

D

TA - +75°C

I
1
I

'V

o 1
o

:I:

1.-1--

rI/

60
40
20

TA -

// / '

BO

'""

./

l"""+25 G

."",."

1 :rV

-

'00

I

J

I
1
I

RESET MODE

I

I

10

12

14

16

SUPPLY VOL T AGE (V)

TIMING CAPACITOR, C (/-IF)

TIMEBASE FREE RUNNING FREQUENCY
AS A FUNCTION OF RAND C

MINIMUM TRIGGER PULSE WIDTH
AS A FUNCTION OF TRIGGER AMPLITUDE
1500
1400
1300

1200

P-~-

r-r·-·
r--

,

1-

1100

1000

~-L~-i

-+-

:-1""--, t
-

c

m-=+--

-- 900 t-BOO ._-700 t-600
v+ ., 16~ _ _ _
500
400
V' - 5\1
300
\ \,1 _~_~I--200
.,....
1 1
'00 v+ "" 2V
1 '-...L_ c-b--J---c
o I
9 '0

-=

1

---=-=

-1- -l-i--

TIME BASE FREQUENCY (Hz)

TRIGGER AMPLITUDE (VOL lS)

NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE
AS A FUNCTION OF TEMPERATURE

MINIMUM RESET PULSE WIDTH
AS A FUNCTION OF RESET AMPLITUDE
'500 ,--Trr-,-TT--,----,-T·-,-~_.__,
'400-, 300 - -- -- - - 1--- 1200

1100

--11+++-++-+-+---

+10·°1. -..

-01-..L- ----

+8.0f----

TA "" 2S"C

-tt+-f--I+-- --1--. - -- .-

-

1000 f-1It+-+l--:V:t'-~-=5V:':-+-+-+-+-1
900-BOOI__II+_+-oI'1-+-_+
-+-+_+--j
700
/
/)

+

~ 2~---1--t--+-_+___1

600c---~LT-~I--+-~-I__+__+___1~

-+-f--+--+-·--

500 c---+t-_+7't'co,-_-o,CC
6V

;~~

- t<

-4.0

__

f--+-f--+--l--+-

-B.O

100-

o
a

-

-6.0

200 - - \ -1'.:+--+--+--+-+--+---1

-i_._

-10.G
5

<

6

7

9

2

'0

'0
SUPPl y VOLTAGE (VI

RESET AMPLITUDE (VOLTS)

6-119

18

20

.D~DIL

ICM7240/50/60
TYPICAL PERFORMANCE CHARACTERISTICS
NORMALIZED FREQUENCY
STABILITY IN THE ASTABLE MODE
AS A FUNCTION OF SUPPLY VOLTAGE
+5

~

+4

~

+3

~

~

o
>
u

_

R=10~"~

-1

-2

--

,-

~

-4

Z

-5

~

TA '" +25"C

""""

==

RC CONNECTED
rOGROUND
_

r=::
~

'I

1M

1
1
5V<

I

10M

~:C '" O.1.uF

-3

~

I

C=0.1"~"'" "...

+1

@

o

100M

I
I

1l::Ji

«

....

+2

if
fa
j

MAXIMUM DIVIDER FREQUENCY
vs. SUPPLY VOLTAGE"

-

lOOK r-

*g6R~~~~:/~7~T6~~'~~L~S_
~F
r-- NO PROGRAMMING CONNECTIONS

v+ < 15V

-

~

t

-25

+25

+50

10K

o

+75

TEMPERATURE (OCJ

2

4

6

8

10

12

14

16

18

20

SUPPLY VOLTAGE (V)

OUTPUT SATURATION CURRENT AS A
FUNCTION OF OUTPUT SATURATION VOLTAGE

DISCHARGE OUTPUT CURRENT AS A FUNCTION
OF DISCHARGE OUTPUT VOLTAGE

10
DISCHARGE SATURATION VOL lAGE (V)

OUTPUT SATURATION VOLTAGE (V)

DESCRIPTION OF PIN FUNCTIONS
COUNTER OUTPUTS (pINS 1 THROUGH 8)
Each binary counter output is a buffered "open-drain"
type. At reset condition, all the counter outputs are at a
high, or non-conducting state. After a trigger input or
when using the internal timebase, the outputs change
state (see timing diagram, Figure 1). If an external
clock input is used, the trigger input must overlap at
least the first falling edge of the clock. The counter
. outputs can be used individually, or can be connected
together in a wired-AND configuration, as described in
the Programming section.

RESET AND TRIGGER INPUTS (PINS 10 AND 11)
The circuits are reset or triggered by positive going
control pulses applied to pins 10 and 11, and once
triggered they ignore additional trigger inputs until
either the timing cycle is completed or a reset signal is
applied. If both reset and trigger are applied simultaneouslytrigger overrides reset. Minimum input pulse
widths are shown in the typical performance characteristics. Note that all devices feature power ON reset.
MODULATION AND SYNC INPUT (pIN 12)

GROUND (PIN 9)

The period t of the time base oscillator can be modulated by applying a DC voltage to this terminal. The
time base oscillator can be synchronized to an external
clock by applying a sync pulse to pin 12.

This isthe return or most negative supply pin. It should
have a very low impedance as the capacitor discharge
and other sWitched currents could create transients.
6·120

ICM7240/S0/60
pulse is applied to pin 10. When the circuit is at reset,
both the time base and the counter sections are disabled and all the counter outputs are at a HIGH or OFF
state. The carrry-out is also HIGH.
In most timing applications, one or more of the counter
outputs are connected back to the reset terminal; the
circuit will start timing when a trigger is applied and
will automatically reset itself to complete the timing
cycle when a programmed count is completed. If none
of the counter outputs are connected back to the reset
terminal (switch Sl open), the circuit operates in its
astable, or free-running mode, after initial triggering.

TIMEBASE INPUT/OUTPUT PIN (TERMINAL 14)
While this pin can be used as either a time base input or
output terminal, it should only be used as an input
terminal if terminal 13 (RC) is connected to GND.
If the counter is to be externally driven, care should be
taken to ensure that fall times are fast (see Operating
Limits section).
Under no conditions is a 300pF capacitor on this terminal useful and should be removed if a 7240/50/60 is
used to replace an 8240/50/60 or 2240.
CARRY OUTPUT (TERMINAL 15, ICM7250/60 ONLY)

PROGRAMMING CAPABILITY

This pin will go HI for the last 10 counts of a 59 or 99
count, and can be used to drive another 7250 or 7260
counter stage while still using all the counter outputs
of the first. Thus, by cascading several 7250's a large
BCD countdown can be achieved.

The counter outputs, pins 1 through 8, are open-drain
N-channel FETs, and can be shorted together to a
common pull-up resistor to form a "wired-AND" connection. The combined output will be LOW as long as
anyone of the outputs is low. Each output is capable of
sinking ..,5 mAo In this manner, the time delays associated with each counter output can be summed by
simply shorting them together to a common output.
For example, if only pin 6 is connected to the output
and the rest left open, the total duration of the timing
cycle (monostable mode) to would be 32t for a 7240
and 20t for a 7250/60. Similarly, if pins 1, 5, and 6 were
shorted to the output bus, the total time delay would be
to.=(1 +16+32)tforthe72400r(1 +10+20)tforthe
7250/60. Thus, by selecting the number of counter
terminals connected to the output bus, the timing
cycle can be programmed from:

The basic timing diagrams for the ICM7240/50/60 are
shown in Figure 1. Assuming that the device is in the
RESET mode, which occurs on powerup or after a
positive signal on the RESET terminal (if TRIGGER is
low), a positive edge on the trigger input signal will
initiate normal operation. The discharge transistor
turns on, discharging the timing capacitor C, and all
the flip-flops in the counter chain change states.
Note that for straight binary counting the outputs are
symmetrical; that is, a 50% duty cycle HI-LO. This is
not the case when using BCD counting. See Figure 3.

J1

___________

-

I I I I I I I I I I II

TIMEBASE OUTPUT
(TERMINAL 14)

Lf"l..JULrLnr ~I

2t

11::; to::; 255t (7240)
1t::;to::; 99t(7250)
11::; to::; 59t (7260)

TRIGGER INPUT
(TERMINAL 11)

Note that for the 7250 and 7260, invalid count states
(BCD values ~ 10) will not be recognized and the counter will not stop.
The 7240/50/60 can be configured to initiate a controlled timing cycle upon power up, and also .reset
internally; see figure 2. Applications for this could
include lawn watering sprinkler timing, pump operation, etc.

"2 OUTPUT (TERMINAL 1)

~
"-

15"
"Sl
il:

@

..

N

::;

'oa:"
z

+3

10M

0

~C-C

j....-"'"'"

--

~

I
I

3

lOOK
..-

5V< V+" 15V

I
+50

+25

~-

l - t--l - t--- 1--1-- -

4
5
-25

~

II

1M

= O}~F

~

-+TA = +25°C
_
RC CONNECTED == =
TO GROUND
_

~ i"'"

C'0.1"~'"

+1

2

I
f--

R'10Jn~
_

2

1

100M

I
I

+4

+

MAXIMUM DIVIDER FREQUENCY
vs. SUPPLY VOLTAGE

10K

o

+75

TEMPERATURE (OC)

2

4

6

8

10

12

14

16

18

20

SUPPLY VOLTAGE (V)

DISCHARGE OUTPUT CURRENT AS A FUNCTION
OF DISCHARGE OUTPUT VOLTAGE

OUTPUT SATURATION CURRENT AS A •
FUNCTION OF OUTPUT SATURATION VOLTAGE

;;-

.s
!;;
~

_ 10 f=----.-

,,-

--+-~-~

a:

""
"

I

Z

V+ =2V

'"

I

r-l::

w

.."
a:

:I:

bl
Ci

I

I

'I'

O. ~O':-1--"-..L-'-.u.....:0:":.1c-'-L....LJ.J.LL-.-L..L-'-JJ..UU
10

,\

0.1

DISCHARGE SATURATION VOLTAGE (V)

10

OUTPUT SATURATION VOLTAGE (V)

APPLICATIONS

is a very slow ramp triangular, sine wave, etc., it will be
necessary to "square up" the waveform; this can be
done by using two CMOS inverters in series, operating
from the same supply voltage as the ICM7242.
The ICM7242 is a non-programmable timer whose
principal applications will be very low frequency oscillators and long range timers; it makes a much better
low frequency oscillator/timer than a 555 or ICM7555,
because of the on-chip 8-bit counter. Also, devices can
be cascaded to produce extremely low frequency
signals.

GENERAL CONSIDERATIONS
Shorting the RC terminal or output terminals to V+ may
exceed dissipation ratings and/or maximum DC current limits (especially at high supply voltages).
OPERATING LIMITS
There is a limitation of 50pF maximum loading on the
TB I/O terminal if the timebase is being used to drive
the counter section. If higher value loading is used, the
counter sections may miscount.
For greatest accuracy, use timing component values
shown in the graph under typical performance charac- .
teristics. For highest frequency operation it will be
desirable to use very low values' for the capacitor;
accuracy will decrease for oscillator frequencies in
excess of 200 KHz.
When driving the counter section from an external
clock. the optimum drive waveform is a square wave
with an amplitude equal to supply voltage. If the clock

TA' +25"C

Because outputs will not be AND'd, output inverters
are used instead of open drain N-channel transistors,
and the external resistors used for the 2242 will not be
required for the ICM7242. The ICM7242 will, however,
plug into a socket for the 2242 having these resistors.
The timing diagram for the ICM7242 is shown in Figure
1. Assuming that the device is in the RESET mode,
which occurs on powerup or after a positive signal on
the RESETterminal (if TRIGGERis low), a positive edge

6-130

ICM7242
on the trigger input signal will initiate normal operation.
The discharge transistor turns on, discharging the
timing capacitor C, and all the flip-flops in the counter
chain change states. Thus, the outputs on terminals 2
and 3 change from highto low states. After 128 negative
timebase edges, the +28 output returns to the high state.

1-.____________-

Jl

I I I I II I I I I II

OUTPUT

-,---{::J

TRIGGER
INPUT
(TERMINAL
6)

TIMEBASE OUTPUT
(TERMINAL 8)

TRIGGER

~

~---""

---- +20UTPUT (TERMINAL 2)

1I11111

T8 OUTPUT

~~~
i---128RC

I.

""1-----1

128RC---I

J1f1='

TERMINAL 6

TERMINALS

-+ 128(256 OUTPUT
(TEAMINAl3) (ASTABLE
OR "FREE RUN" MODE)

OUTPUT

~t

TERMINAL 3

.;. 128/256 OUTPUT
(TERMINAL 3) (MONOSTABLE
OR "ONE SHOT" MODEj

1----,28 RC---j

Figure 1. Timing Diagrams of Outpllt Waveforms for the ICM7242.
(Compare with Figure 5)

To use the a-bit counter without the timebase, terminal
7 (RC) should be connected to ground and the outputs
taken from terminals 2 and 3.

Figure 4. Monostable Operation

COMPARING THE ICM7242 WITH THE 2242
ICM7242
a.
b.
c.
d.

e.
f.

g.
Figure 2. Using the ICM7242 as a Ripple Counter (Divider)

The ICM7242 may be used for a very low frequency
square wave reference. For this application the timing
components are more convenient than those that would
be required by a 555 timer. For very low frequencies,
devices may be cascaded (see Figure 3).

h.

2242

4-15V
2-16V
Operating Voltage
Commercial Temp.
Range
-20° C to +75° C 0° C to +75° C
Supply Current
V+ = 5V
7 mA Max.
0.7 mA Max.
Pullup Resistors
Yes
TB Output
No
Yes
+2 Output
No
Yes
No
+256 Output
Toggle Rate
3.0 MHz
0.5 MHz
Resistor to Inhibit
Yes
Oscillator
No
Resistor in Series
with Reset for
Yes
No
Monostable Operation
Capacitor TB
Terminal for
No
Sometimes
HF Operation

By selection of Rand C , a wide variety of sequence
timing can be realized. A typical flow chart for a machine
tool controller could be as follows:
reM 7242

leM 7242

leM 7240

leM 7242

~r-t-'I----TI-t'I;-----------'---'~
WAIT
5 SEC.

Figure 3. Low Frequency Reference (Oscillator)

For monostable operation the +28 output is connected
to the RESET terminal. A positive edge on TRIGGER
initiates the cycle (NOTE: TRIGGER overrides RESET).
The ICM7242 is superior in all respects to the 2242
except for initial accuracy and oscillator stability. This is
primarily due to the fact that high value p-resistors have
been used on thelCM7242 to provide the comparator
timing pOints.

ENABLE
10 SEC.

WAIT
5 SEC.

COUNT
TO 185

ENABLE
5 SEC.

Figure 5.

By cascading devices, use of low cost CMOS AND/ OR
gates and appropriate RC delays between stages, numerous sequential control variations can be obtained.
Typical applications include injection molding machine
controllers, phonograph record production machines,
automatic sequencers (no metal contacts or moving
parts), milling machine controllers, process timers, autoatic lubrication systems, etc.
6-131

ICM7242
SEQUENCE TIMING
• Electro-pneumatic Drivers
• Multi-operation (Serial or Parallel controlling)

• Process Control
• Machine Automation

SEQUENCE TIMER:

y'

y'

y'

y'

PUSH S1 TO START SEQUENCE:

----j
TRIGGER

I---

MUST BE SHORTER THAN "ON timeA ..

~•
'

_______________________________

~

128RC

----li-______________________

OUT.UTA'I

,

_..jI______~I-.---128RC---~·1_I--------OUTPUTB-

OUTPUTe"

CUTPUTD*

I

'I

I

I

I

!-128RC-j

-~-----_r--------_,

~-----------

~I

---------+.-----------.+

--7

1--128RC

-.- - - - "

1

---l

I

1

1

-ONt;meA_

ONt;me. .

Figure 6.

CHIP TOPOGRAPHY (.068" x .069")
RC

RESET

.;.128/256

OUT

+128/256
OUT

6·132

.

ONthriOC+-ONt;meD---!

• SELECT RCVALUESTO
DESIRED "ON time"
FOR EACH ICM7242

ICM7243
a·Character 14.116·Segment
Alphanumeric LED Display Driver
FEATURES
• 14· and 16·segment fonts with decimal point
• Mask programmable for other font·sets up to 64
characters
• Microprocessor compatible
• Directly drives small common cathode displays
• Cascadable without additional hardware
• Standby feature turns display off; puts chip in low
power mode
• Serial entry or random entry of data into display
• Single + 5V operation
• Character and segment drivers, all MUX scan cir·
cuitry, 8 x 6 static memory and 64·character ASCII
font generator included on·chip

GENERAL DESCRIPTION

Six-bit ASCII data to be displayed is written into the memory
directly from the microprocessor data bus. Data location
depends upon the selection of either Serial (MODE =1) or
Random (MODE = 0). In the Serial Access mode the first entry
is stored in the lowest location and displayed in the "leftmost" character position. Each subsequent entry is automatically stored in the next higher location and displayed to the
immediate "right" of the previous entry. A DISPlay FULL
signal is provided after a entries; this signal can be used for
cascading. A CLeaR pin is provided to clear the memory and
reset the location counter. The Random Access mode allows
the processor to select the memory address and display digit
for each input word.
The character multiplex scan runs whenever data is not being
entered. It scans the memory and CHARacter drivers, and
ensures that the decoding from memory to display is done in
the proper sequence. Intercharacter blanking is provided to
avoid display ghosting.

The ICM7243 is an a-character alphanumeric display driver
and controller which provides all the circuitry required to inORDERING INFORMATION
terface a microprocessor or digital system to a 14- or
16-segment display. It is primarily intended for use in
Part
Display
Order
microprocessor systems, where it off loads the processor
Number
Segments
Package
Number
ICM7243A
16 + d.p.
40 Pin CERDIP ICM7243AIJL
and minimizes hardware and software overhead. Incorporated on-chip are a 64-character ASCII decoder, an a x 6
ICM7243B
14 d
40 Pin CERDIP ICM7243BIJL
memory, the high power character and segment drivers, and
+ .p.
~th~e~m~u~lt~iP~I~e:x~s~c~a~n~C~ir~c~u~it~ry~.__________________________~==IC=M=7=2=4=3=B=E=W=K=IT~===K=it=W=i=th=D=i=S~P=1a~Y==~=IC=M=7=2=4=3B==E~=I=K=IT~

PIN CONFIGURATIONS

6·133

6

ICM7243
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ................................... 6V
CHARacter Output Current ...................... 300mA
SEGment Output Current ..... , .................. 30mA
InputVoltage(AnyTerminal) .......... (V+ +O.3V)tO -O.3V

Power Dissipation ................................ 1W
Operating Temperature Range ........... -20°C to +85°C
Storage Temperature Range ............ -55°C to + 125°C

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS
SYMBOL

PARAMETER

Supply Voltage

V+

Operating Supply Current

1+ OP

Quiescent Supply Current

I0 +

Input High Voltage

VIH

Input Low Voltage

VIL

MIN
4.75

LIMITS
TYP
5.0

=5.25V, 10 Segments ON, All 8 Characters
V + =5.25V, OSCIOFF Pin < lV
V+

MAX
5.25

UNIT

V

180
30

mA

250

~A

2

V
0.8

liN

V + =5.25V, V1H =5V
V1L=OV

CHARacter Drive Current

ICHAR

Y+

CHARacter Leakage Current

ICHLK

Input Current

D1

TEST CONDITIONS

V

+1

,

~A

-1

=5V, VOUT= l\V

140

190

mA

14

19

mA

~A

SEGment Drive Current

V+=5V, VouT =2.5V

ISEG

SEGment Leakage Current

ISLK

DISPlay FULL Output Low

VOL

IOL = 1.6mA

DISPlay FULL Output High

VOH

IIH

Display Scan Rate

Ids

0.01

~A

0.4

= 100~A

V

2.4

Y

400

Hz

AC CHARACTERISTICS (Drive levels O.4V and 2.4V, timing measured at 0.8V and 2.0V)

!

PARAMETER

SYMBOL

TEST CON DITIONS

MIN

TYP

WR, CLeaR Pulse Width Low

tWPI

250

WR, CLeaR Pulse Width High

tWPh

250

Data Hold Time

tDh

0

Data Setup Time

tDs

250

150

Address, SEN, MODE Hold Time

tAh

125

80

MAX

UNIT

-20
ns

.~

Address, SEN, MODE Setup Time

tAs

-20

CS, CS Setup Time

tCs

0

Pulse Transition Time

tt

100

CAPACITANCE
SYMBOL

TEST

MIN

TYP

MAX

UNIT

CIN

Input Capacitance

pF

Co

Output Capacitance

pF

6-134

ICM7243
TYPICAL PERFORMANCE CURVES
SEGment Current vs Output Voltage

CHARacter Current vs Output Voltage

30

I __ r-v+

50Q

V+ =5.:~_

=5.5V

.V~5.0V

e:-

,~.5V

10

.~.

I

j .

#

100

"':;. Vi;oV
.5r~
.'

I
SEGment Voltage (V)

CHARacter Voltage (V)

ICM7243A/B DISPLAY FONT, SEGMENT ASSIGNMENTS Note: Some display manufacturers use different designations
for some of the segments. Check data sheets carefully.

0

Os. D.

0

1
1

RB C11 Er- GH IJ I-< LM N 0
lP Q R 5T UV W;x: YZ [ \ J /'
0
11£ 9]% jJ' < > *+ /
1[2] 12 3Y S5 18 9
,7
L
I

/

/

R B C11 Er- G H ILl I-< LM N 0
lP Q R 5T U VW Xy Z +\ 01 7"
I
0
/
":±! 9]~ Z' < > *+
1[2] 12 3Lf S 51 89
L.= ~7

0

0[lJ

os. D4

0[lJ

0

1

/

1

-

I

03 0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

03 0

0

0

0

o

'0

0

0

1

1

1

1

1

1

1

02 0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

02 0

0

0

0

1

1

1

1

0

0

0

0

1

1

1

1

0, 0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0, 0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

DO 0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Do 0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

NOTE: Slgments a and d appear 8S 2 segments each. but both halves are driven together.

ICM7243A
16·Segment Character Font with Decimal Point

ICM7243B
14-Segment Character Font with Decimal Point

CS _ _.....J'I
V+

SEGMENT
DRIVER

VLEO= 1.6V
RTYPICAl = 100n

DISPLAY

~-- ~~I

ADDREsst,
SEN·, MODE

____

. SEGMENT LEOs
rOS(on)-4n

WRITE

-=

t'---I I

oh : I------'----.t
_

DATA~

VALID

·SERIAL ACCESS ONLY
tRANDOM ACCESS ONLY

Segment and Character Drivers Output Circuit

Data Entry Timing

~

I

.D~OIl"

ICM7243
PIN DESCRIPTIONS, ICM7243A (B)
SIGNAL

PIN

FUNCTION

SIGNAL

10-15

Six·Bit ASCII Data input pins
(8-13)
(active high).
16
Chip Select for decoding
(14-16) from I'P address bus, etc.
17
WRite pulse input pin (active
low). For an active high write
pulse, CS can be used, and
WR can be used as (;'S.
Selects data entry MODE.
31
High selects Serial Access
(SA) mode where first entry is
displayed in "leftmost" char·
acter and subsequent en·
tries appear to the "right".
Low selects the Random Ac·
, cess (RA) mode where data
is displayed on the character
addressed via Ao-A2 Ad·
dress pins.
30
In RA mode it is the LSB of
the character Address. In SA
mode it is used for cascad·
ing display driver/controllers
for displays of more than 8
characters (active high en·
abies driver controller).

Do-Os
CS,CS
WR

MODE

Ao/SEN

PIN

FUNCTION

A,/CLeaR

29

A2/DISPlay FULL

28

OSC/OFF

27

In RA mode this is the sec·
ond bit of the address. In SA
mode, a low input will CLeaR
the Serial Address Counter,
the Data Memory and the
display.
In RA mode this is the MSB
of the Address. In SA mode,
the output goes high after
eight entries, indicating DIS·
Play FULL.
OSCillator input pin. Adding
capacitance to V + will
lower the internal oscillator
frequency. An external oscil·
lator is also applied to this
pin. A low puts the display
controller/driver into a qui·
escent mode, shutting OFF
the display and oscillator
but retaining data stored in
memory.
SEGment driver o~tputs.

SEGa-SEGm, D.P.
CHARacter 1-8

2-9 (7),
32-40
18-21,
23-26

CHARacter driver outputs.

BLOCK DIAGRAM
DATA INPUT

64)( 17*
ROM

Do.,

SEGMENT
DRIVERS

SEGMENT OUTPUTS
SEGx

CHARN
CHARACTER OUTPUTS

Ao/SEN_

SEL

SEL

"ICM7243AHASONLYONECSAND
NO CS.ICM7243B HAS 15 SEGMENTS
ADDRESS
MULTIPLEXER
AND
DECODER

A,/DISP FULL .........

INTER·CHARACTER BLANKING

6·136

ICM7243
DETAILED DESCRIPTION OF OPERATION

es. These pins are immediately functionally ANDed,
so all actions described as occurring on an edge of WR, with
CS and CS enabled, will occur on the equivalent (last) en·
abling or (first) disabling edge of any of these inputs. The
delays from CS pins are slightly (about 5nsecs) greater than
from WR or CS due to the additional inverter required on the
former.

WR,~,

will not affect device operation. This allows use of a
multiplexed 6·bit bus controlling both address and data, with
timing controlled by WR.
Serial Access Mode. If the internal latch is set for Serial Ac·
cess (SA), (MODE latched high), the Serial ENable input on
SEN will be latched on the falling edge of WR (or its equiva·
lent). The CLR input is asynchronous, and will force·clear the
Serial Address Counter to address 000 (CHARacter 1), and
set all Data Memory contents to 100000 (blank) at any time.
The DISPlay FULL output is always active in SA mode also,
and indicates the overflow status of the Serial Address
Counter. If this output is low, and SEN is (latched as) high, the
contents of the Counter will be used to establish the Data
Memory location for the Data input. The Counter is then incremented on the rising edge of WR.lf SEN is low, or DISPlay
FULL is high, no action will occur. This allows easy "daisychaining" of display drivers for multiple character displays in
a Serial Access mode.

MODE. The MODE pin input is latched on the falling edge of

\iiit! (or its equivalent, see above). The location in Data Mem·
ory where incoming data will be placed is determined either
from the Address pins or the Serial Address Counter, under
control of this latch, which also controls the function of
Ao/SEN, A 1 /CLR, and A2/DISPlay FULL.
Random Access Mode. When the internal mode latch is set
for Random Access (RA) (MODE latched low), the Address in·
put on Ao, A 1 , and A2 will be latched by the falling edge of WR
(or its equivalent). Subsequent changes on the Address lines

TEST CIRCUIT (ICM7243A SHOWN)
17
SEGMENTS

r----I--/SlZI-IS/Zl-IS/Zl-IS/Zl-IS/ZI-/S/Z/-/SIZI-/S/71
IZ1SI IZ1SI IZISI IZISI IZISI 1&1 IZISJ ILISI
3

CHAR 1

8

8 CHARACTERS
SEGMENTS

1-----'---'--1---<>._

0_--- v +

.......---.:::--- DISPLAY FULL OUTPUT

I-....:..::=~~=--+

'---<0----0 NC (FOR SA MODE)

6-137

ICM7.243.
clears the pre-divider and Multiplex Counter. This puts the circuit in a low-power-dissipation passive condition in which all
outputs are effectively open circuits, except for parasitic
diodes to the supply lines. Thus a display connected to the
output may be driven by another circuit (including another
ICM7243) without driver conflicts.

Changing Modes. Care must be exercised in any application
involving changing from one mode to another. The change
will occur only on a falling edge of WR (or its equivalent).
When changing mode from Serial Access to Random Access,
note that A2IDISPIay FULL will be an output until iNR has
faUen low, and an Address drive here could cause a conflict.
When changing from Random Access to Serial Access,
A 1/CLR should be high to avoid inadvertent clearing of the
Data. Memory and Serial Address Gounter. DISPlay FULL will
become active immediately after the falling edge of WR.

Display Output. The address output of the Multiplex Counter
is multiplexed into the address input of the Data Memory, except during lAm operations (in Serial Access mode, with
SEN high and DISPlay FULL low), to control display operations. The address decoder also drives the CHARacter outputs, except during the inter-character blanking interval
(nominally about5I'sec). Each CHARacter output lasts
nominally about 300l'sec, and is repeated nominally every
2.5msec, i.e., at a 400Hz rate (times are based on internal
oscillator without external capacitor).

Data Entry. The input Data is latched on the rising edge of WR
(or its equivalent) and then stored in the Data Memory 10'
cation determined as described above. The six Data bits can
be multiplexed with the Address information on the same
lines in Random Access mode. Timing is controlled by the
WR input.
OSC/OFF. The device includes a one·pin relaxation oscillator
with an internal capacitor and a nominal frequency of
200kHz. By adding external capacitance to V + at the
OSC/OFF pin, this frequency can be reduced as far as de·
sired. Alternatively, an external signal can be injected on this
pin. The oscillator (or external) frequency is pre-divided by64,
and then further divided by 8 in the Multiplex Counter, to drive
the CHARacter strobe lines (see Display Output). An intercharacter blanking signal is derived from the pre-divider. An
additional comparator on the OSC/OFF input detects a level
lower than the relaxation oscillator's range, and blanks the
display, disables the DISPlay FULL output (if active), and

III

The 6 bits read from the Data Memory are decoded in the
ROM to the 17 (15 for ICM7243B) segment signals, which
drive t~e SEGment outputs. Both CHARacter and SEGment
outputs are disabled during WR operations (with SEN high
and DISPlay FULL low for Serial Access mode). The outputs
may also be disabled by pulling OSC/OFF low.
The decode pattern from 6 bits to 17 (15) segments is done by
a ROM pattern according to the ASCII font shown. Custom
decode patterns can be arranged, within these limitations, by
consultation with the factory.

APPLICATIONS
8 CHARACTER LED DISPLAY

,_,-J_
*'Il-t
CLR

r~-5

DATA
BUS

8 CHARACTER

..

TI

TI\JTt~~C;
~,
-~-

.... 1-- "

LED DISPLAY

II-~/I-lcJL-i~3

8

8

.'

I--

"

CHAR
SEG
DISP FULL

+5V __
SEN
+5V __ MODE
WR

--

CHARACTER LED DISPLAY

,

T~-iE
8

1

8

-

LC.LR

CHAR >--SEG r--DISP FULL f , - - - I
+5v
v+ ~+5V
,

~.

SEN
+5V __ MODE
V++-+5V _ _ WR

cs

GND/~

6

r

~-5

cs

GND~
/

6

----

.

CLR

CHAR t-SEG
DISP FULL

-

SEN
MODE
WR
~-5

V+ _+5V
CS

GND

-

6

-

WR.(CS)
CS. (WR)
FIRST 8 CHARACTERS

SECOND 8 CHARACTERS

--

"17 for ICM7243A. 15 for ICM7243B
Figure 1. Multicharacter Display using Serial Access Mode

6-138

nth 8 CHARACTERS

+;;.,

ICM7243
APPLICATIONS

~

(Continued)

RBR8
RBR7

RRI

ETC.

IM6403
UART
RBR1_S
DR

ORR
+5V
OUT

V+
TR

20k

ICL7555
DELAY

ETC.

TH

200pF

1SJZJ 1SJZJ /S/Zl 1SJZJ /S/Zl 1SJZJ /S/Zl 1SJZJ /SJZI/S/Zl /SI7/1SJZJ /SlZ//S/Zl /S/Zl /SIZl
0S1/ZlS./ /ZlS./ /ZlS./ 0S10S1/ZlS./ 0S1/ZlS./ 1ZlS./ IZ1SII~//ZlS./ IZlSI/ZlS./ /ZlS./
Figure 2. Driving Two Rows of Characters from a Serial Input. UART converts data stream to parallel bytes. Bit 7 of each word sets which row
data will be entered into. Bit a will blank and reset whole display if low. Each MODE pin should be tied high. ICM7243A can also be
used, with inverter on RBR7 for one row.

1

ICM7243A/B
CS A2 A1Ao 05-0 WR

I

P22
IM80C35
IM80C48
8048,
8050,
ETC.

P21
P20

1

I~

1

ICM7243A1B

.1

CS A2 Al Ao 05-0 WR

..,;~

I

J

-D>

ICM7243A/B

.1

CS A2 Al Ao 05-0 WR

1

I"';~

ICM7243A/B

I

CS A2 Al Ao 05-0 WR

~I

1.-<" ';::>.

OB7
OBs
OBs-o

6-BIT BUS

WR

I
Figure 3. Random Access 32·Character Display in MCS·48 system. One port line controls A2 , Other two are CS lines. a·bit data bus drives 6
data and 2 address lines. MODE should be GrouNDed on each part.

6·139

APPLICATIONS

II

(Continued)

-i:
n

....
~

•
W

T§
oXe

IM6100

0:S f-

/

~

/

~

/

/

/

I...-""""T'"_,..--....J

~ TI
V

"' .. '"

-\ oxo····· ox"

1-----,-----,-1

I

T

I

OXo

CONTROL BUS

/ /

/

•
~

/

/

OX3
OX3

~

/
cs

IM6101

CS

05~0

A2-0

I

ITT.

TI

IT

IT

... ...

... ... ...

... ...

( ICS
S

( Ics
S

( Ics
S

TilT

..........~• ..,L,;
"''''L..J.....J....I._...J........,
( Ics
S

cs

CS A2-0

ICM7243B
WRITE 1

h
I

WR SEQ

I

05-0

ICM7243B

CHAR

WR

WR

I

ISIZ/ISIZI Kl711SiZ/ 1SIZ11SiZ//SlZII\iZ1 •
1&lIZlSi/ZlSiIZISJ IZISI/ZlSiI&lIZISJ

WR

WR

WR SEQ

CHAR

i

•

• fIlfIIfIIfIIfIIfIIFilfII

Figure 4. A 48-Character Random Access Display. 12·bit bus split into 6 bits data, 3 bits address within chip, and 3 bits chip address. Inverting
one 01 these chip address lines allows selection 01 one 01 6 chips without decode, using CSand CS lineson ICM7243B. Standard 1'01-8
decoder can select 64·character array using ICM7243A/B. WRITE 2 can be used I,or another row in either case.

II

I
=
F

ICM7243
APPLICATIONS (Continued)

+5V

+5V

I
I

+5V

+5V

+5V

I

I
I

1.4 AMP PEAK

I

1k

I
I

I
100ll :

100ll

I

I

140 (l00mA PEAK)

ICM7243

IV

tel

ICM7243

:3OOll
I
I

I

I1J

I

(l00mA PEAK)

":" GND

GND ":"

(5b.) Common Anode Displays

(Sa.) Common Cathode Displays

Figure 5. Driving Large Displays. The circuits of Figures 5a and 5b can be used to drive

0,5" or larger alphanumeric displays, either common cathode (5a) or com·
mon anode (5b).

COMPONENT SELECTION
Displays suitable for use with the ICM7243 may be obtained
from the following manufacturers; among others:
Hewlett Packard Components, Palo Alto, California
(415) 857-6620 (part #HDSP6508, HDSP6300)
General Instruments Inc., Palo Alto, California
(415) 493-0400 (part #MAN2815)

6-141

Texas Instruments Inc" Dallas, Texas
(214) 995-6611 (part #HDSP6508)
A.N.D., Burlingame, California
(415) 347-9916 (part #AND370R)
lEE Inc., Van Nuys, California
(213) 787-0311 (part #LR3784R)

m

ICM7243
CHIP TOPOGRAPHIES

SEGdl

D.P.

D.P.

SeGh

SEGh

SEGal

SeGd
SEGj

SEGj

SEG/!2

SeG/!
MODE

MODE

Do

D,
D,

D,
AoISEN

"olSEN

D,

D,

A,IClR

Al/ClR

D,

D,

A2/DISP

FUlL---.fl~J~ __

D.

(3.861)mm

D,

A21DISP FULL

D.

JI~J~
(3.861Jmm

D,

OSC/OFF

CHAR 8 CHAR 7 CHAR 6 CHAR 5 GNO CHAR 4 CHAR 3 CHAR 2

!

I-

0.139 in

(3.531)-m';'

ICM7243A

_0-,-1_3_9 in
(3.S31)mm

ICM7243B

II

6-142

::HAR 1

I

-1

I

ICM7281
LCD Column Driver
FEATURES

TYPICAL APPLICATIONS

•

LCD Dot Matrix Column Driver

•

•

40 High Voltage LCD Column Drive
Outputs For Up to 8 SxN Characters per IC

Column Drivers for Dot Matrix Alpha·
numeric Displays using ICM7280 Row Driver

•

Rowand Column Drivers for LCD Dot
Matrix Graphics Displays

•

Segment Driver for LCD Bargraphs and
Annunciators

•

Serial Input I/O Expander

•

Easy Interface
-Serial Input Shift Register
With parallel latch and carry outputs

•

Directly Compatible with ICM7280 Row Driver
-Up to 10 ICM7281's can be driven by an
ICM7280 with no external components

•

Low Resistance Outputs
-Can drive both columns and rows of
LCD graphics displays

•

Will Drive 1.SV Threshold LCDs with Only
Single SV Supply
-Can drive up to 4.SV threshold LCDs with
1SV VOISP

PIN CONFIGURATIONS
(Outline dwg. PL)

GENERAL DESCRIPTION
The ICM7281 LCD Dot Matrix Column Driver is
designed to convert a serial data stream into drive
signals for a multiplexed dot matrix LCD. Easily
cascadable, up to 10 ICM7281 's can be driven by one
ICM7280 Intelligent Row Driver to make an 80
character dot matrix display. The ICM7281 also
serves as both a Row Driver and Column Driver in
LCD dot matrix graphics displays. The low output
resistance and the 15V drive capability make it well
suited for graphics displays with up to 256 x 256 dots
(with 10pF/dot capacitance).

ICM
7281

The ICM7281 consists of a 40 bit shift register, a 40
bit latch and 40 level·shifters/drivers. The 4 display
drive voltages are generated externally, usually by a
Row Driver. A serial data interface is used to
minimize the number of pins needed for digital inter·
facing. Two data Carry Outputs are included for
cascading several ICM7281 's to drive large LCD
displays.

ORDERING INFORMATION
No. Of Columns

Package

Order Number

30

40 Pin Plastic

ICM72811PL

40

Dice

ICM7281liD

40

52·64 Pin Plastic
Flatpack

-

PACKAGE

6·143

ICM7281
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Vec - Vss) ................... 6V
Display Voltage (Vce - VOISP) ................ 18V
Input Voltage (Note 1) .... Vec + 0.3V to VSS - 0.3V
Power Dissipation (Note 2) ......... 0.3W @

+ 85°C

Operating Temperature Range .... - 20°C to + 85°C

.

Storage Temperature Range ..... - 65°C to + 150°C
V2, V3· ............................ VOISP to Vcc

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. These are stress ratings only and functional
operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended
periods may affect device reliability.
NOTE 1: Oue to theSCR structure inherent in any junction
isolated CMOS device, connecting an input to any
voltage greater than Vee or less than ground may
cause destructive device latch·up. If the input
voltage can exceed the recommended range, the
input should be limited to less than 1 rnA to avoid
latch-up.
NOTE 2: This limit refers to that of the package and will not
occur during normal operation.

OPERATING CHARACTERISTICS
(Vcc = 5V ± 10%, VOISP= -10V, V2 = 1/3 (VCC-VOISP)· V3 = 2/3 (Vcc - VDlSP), VSS = OV,
TA = - 20 to + 85°C) Unless otherwise specified.

Parameter

Symbol

Operating Supply
Range

Vsupp

Display Voltage

VOISP

Conditions

Min.

Typ.

Max.

Units

VSS =:= OV

4.5

5.0

5.5

V

Vcc = 5V,
V OISP < (V2, V3) < VCC

-10

Vcc

V

10
1000

uA

SUPPLY CHARACTERISTICS

Supply Current
Quiescent
Dynamic

.1
450

Icc
Icc

FCLK = 0
FCLK = 500KHz

Logic 1 Input
Range

V,H

DATA INPUT, DATA LATCH,
CLOCK and DISPLAY CONTROL

0. 7V cc

Vcc

V

Logic 0 Input
Voltage

V,L

DATA INPUT, DATA LATCH,
CLOCK and DISPLAY CONTROL

0

0.3VCC

V

Input Current

liN

DATA INPUT, DATA LATCH,
CLOCK and DISPLAY CONTROL
O--j'::---f------I

1------ ••• -------I

DISPLAY 1----1
CONTROL
VOFF
CKT.

1----- ••• ------I
1------'- •••

--------1

DISPLAY
CONTROL
COLUMN 1
OUTPUT

COL 40

COL2

ICM7281 COLUMN DRIVER BLOCK DIAGRAM

6-146

COLUMN 40
DATA OUTPUT

ICM7281
DETAILED DESCRIPTION

This input is used as one of the two control inputs to
the 1 of 4 analog multiplexer that drives each column
output.

Data Interface
To reduce the pincount, the data interface is serial.
The data on DATA INPUT is shifted into the shift
register with each falling edge of CLOCK. The data in
the shift register is also shifted one bit with each failing edge of CLOCK. The data in the 20th and 40th
registers is available as COL 20 OUTPUT and COL 40
OUTPUT on the ICM7281 dice. The packaged part has
only one CARRY OUTPUT, which is the 30th column.
These outputs are normally used as the DATA INPUT
for an adjacent ICM7281.

Figure 1 shows a typical interface between an array
of ICM7281's and the ICM7280 Intelligent Row Driver.
The Column Driver also readily interfaces with
microprocessors, as shown in the block diagram of a
graphics display, Figure 2.

LCD Interface
The ICM7281 uses a modified Alt and Pleshko
multiplexing scheme, in which the Column Driver
uses 4 voltages: Vee, V2, V3, and VDISP. These drive
voltages are generated externally, usually by the
ICM7280 Intelligent Row Driver. Each column output
is driven by an analog multiplexer. The truth table and
a schematic of this multiplexer are shown in Figure 3.
The column data is the data that is serially loaded into the shift (egister, then parallel loaded into the data
latch. The DISPLAY CONTROL signal, generated by
the ICM7280 Row Driver, tells the ICM7281 which half
of the mux cycle is occuring.

The DATA LATCH input is used to transfer data from
the shift register to the 40 bit latch, which consists of
40 negative edge-triggered D flip-flops. The data in
the shift register is stored by the falling edge of
DATA LATCH and this latched data will be held until
the next falling edge of DATA LATCH.
The DISPLAY CONTROL pin is used to convey
multiplex timing information to the Column Drivers.

ICM
7280

ROW
DRIVE
RI·10

LCD DISPLAY
7·10 ROWS, UP TO 480 COLUMNS

10

ALE

,t. 7 ..

.. ,t. 8 ..

TO
MICROPROCESSOR

to

to

AO·6
00·7
S ClK

RD
WR

to

Dour
DATA
CS
lATCH
DISPLAY
CONTROL
V2
V3

+5

Vee

VDlSP
VSS

ClK
DATA IN cOl
DATA
40
lATCH
DISPLAY
CONTROL
V2
V3
VDlSP
ICM7281
#1

),

-----

f40
ClK
DATA INc~l
DATA
lATCH
DISPLAY
CONTROL
V2
V3
V 01SP
ICM7281
#2

I
V 01SP
GENERATOR

Figure 1. Alphanumeric LeO Display System

6-147

to

• •••
r--r--f----

r--r--r--r---

••••

ClK
DATA IN
DATA
lATCH
DISPLAY
CONTROL
V2
V3
V01SP
ICM7281
#12

ICM7281
Vee ROW/COL

DIl'PLAY VOLTAGES ROW

3
ICM7281
24/40

~SUPPLY

64 x 64 DOT
LCD DISPLAY

"*

ICM7281
DC DATA DL

1

24/40

40

ICM7281
DC

ICM7281

~SUPPLY
2

ROWD'i~~TROrL;;..._ _ _...,
1
1

VOIS P ROW/COL

LATCH
DATA IN
GRAPHICS

Dcl~----~~~~~~~~ CONTROLLER

1 12

3

3

DISPLAY
VOLTAGES
COLUMN

DISPLAY VOLTAGES ROW

SUPPLY

DISPLAY
VOLTAGES
COLUMN

DATA

DATA INPUT

Dl

DATA LATCH

CHIP

12

SUPPLY

Figure 2. ICM7281 Column Driver Used in a Graphics Application

C,

R

~ 2K~

•

COL 1 DATA

I
V2

»--.. .o

V3

>

R

~

L---- COL 1 DATA

•

A

20011
0

·C

R

V

01SP

Vec

DISPLAY
CONTROL

»----~O

>

R

~

~ 2K~ N
I

COL "N"

L---- COL "N" DATA

B

20011

0

•

I
I
I

>- ___ ...J

TRUTH TABLE
COLUMN DATA
o
1

DISPLAY
CONTROL 0 ~-=--+-=;:':::"-I

~40

R ~ 2K!1

I
I

•

COL 40

L - - - - COL 40 DATA
COLUMN OUTPUT MULTIPLEXER AND TRUTH TABLE

Figure 3. Column Output Multiplexer and Truth Table

ICM7281
calculated values for common multiplex ratios are
shown in table 1. Table II shows the optimum
voltages for V1 to V5 for different multiplex ratios.

LCD MULTIPLEXING
Multiplexing Schemes
The goal in LCD multiplexing is to increase the
number of segments a given number of column lines
can drive, while not unacceptably degrading the
viewability of the LCD display. Increasing the number
of rows driven by a column decreases the ratio between the voltage across an ON segment and the
voltage across an OFF segment. This ON/OFF
voltage ratio is critical since the contrast of an LCD
segment is determined by the RMS voltage across
that segment. Figure 4 shows a typical curve of RMS
voltage vs. contrast. For an acceptable display, the
RMS OFF voltage must be below the 10% contrast
point and the RMS ON voltage must be above the
50% contrast point. The RMS on voltages for different multiplex ratios are also shown in figure 4.
Note that as the number of rows or backplanes goes
up, the RMS on voltage decreases.

Temperature Effects and Temperature
Compensation of V OISP
The performance of LCD fluids is affected by
temperature in two ways. The response time of the
display to changes in applied RMS voltage gets
longer as the display temperature drops. At very low
temperatures some displays may take several
seconds to change to a new character after the new·
information appears at the LCD driver outputs.
However, for most applications above O°C this will
not be a problem, and for low temperature applications, high-speed liquid crystal materials are
available. High temperature operation is generally
limited by long term degradation of the polarizer and
the sealing materials above 70°C or 85°C.

The ICM7281 can drive either columns or rows using
the modified Alt and Pleshko waveforms as shown in
figure 5. The ON/OFF voltage ratio formula and the
~

100
Itil


;:::

N = 2
N=3 V=3.29
N=4 V=2.94

20
0
4.0

6.0

DRIVE VOLTAGE VRMS

Figure 4.

Table 1. OPTIMUM MULTIPLEX DRIVE
Rows

VON/OFF

4

1.73

4

3

7

1.488

4.74

3.27

8

1.447

4.97·

3.37

9

1.414

5.20

3.46

10

1.387

5.41

3.56

12

1.346

5.81

3.74

14

1.315

6.18

3.917

6.532

4.08

8.817

5.19

16

1.290

32

1.196

64

1.134

Alt and Pleshko
Vcc-V DisplaylVT

12.01

6-149

ICM7280/lCM7281
Vcc-V DisplaylVT

6.804

ICM7281
MODIFIED ALT & PLESHKO

~IT51T 61 T11 T21 T 31

To I T11T 21T31T
V5 -

V4 V3 ROW 2 V2-

I

I

R~W ~~

3xSDISPLAY

1 2 345
COLUMN

V1 VO-

WITH
Vo = 0
V1 =V{3
V2 = 2 V{3
V3=VOI- V{3
V4 = VOl
V5
VOISPLAY

V5 -

V4 V3 COL 2 V2 -

=

V1 VO-

= VOl + Vp

V5 -

V4 .,..
COL 3

~~:=
V1

WHERE: K =

-

Vo-

-IN + 1
-IN-1

V TH = THRESHOLD VOLTAGE OF LCD

(V,"+V{3) Vo: (V,,-V{3)V{3Vo -

V{3(Va- V {3) -

DJ

Va (V,,+VtJ) ROW 1 WRT COL 3
(Va+ V {3) I
I
I
V,,-

(V,,-V,j) -

VrJVo -

V(3(V,,-VjJ) -

V,,(V,,+V;J) -

I

I

:t
I

VON_
VOF F-

I

l-

I

I

I

I

(M+1)2 + (N-1)
(M-1)2 + (N-1)

FOR OPTIMUM CONTRAST M =

Figure 5.

6·150

.fN N ,,4

ICM7281
Table II. Optimum Drive Voltages
N

V1

V2

V3

V4

V5

ON/OFF
VOLTAGE
RATIO

4

1.000

2.000

1.000

2.000

3.000

1.732

5

0.951

1.902

1.176

2.127

3.078

1.618

6

0.919

1.838

1.332

2.252

3.171

1.543
1.488

7

0.897

1.793

1.476

2.372

3.269

8

0.879

1.759

1.608

2.488

3.367

1.447

9

0.866

1.732

1.732

2.598

3.464

1.414

10

0.855

1.710

1.849

2.704

3.559

1.387
1.365

11

0.846

1.692

1.960

2.806

3.652

12

0.838

1.677

2.066

2.904

3.743

1.346

16

0.816

1.633

2.449

3.266

4.082

1.291

20

0.802

1.605

2.786

3.589

4.391

1.255

24

0.793

1.585

3.090

3.883

4.676

1.23

30

0.782

1.564

3.502

4.284

5.066

1.203

32

0.779

1.559

3.629

4.409

5.188

1.196

40

0.771

1.541

4.103

4.874

5.645

1.173

48

0.764

1.529

4.332

5.296

6.061

1.156

54

0.761

1.522

4.830

5.590

6.351

1.147

64

0.756

1.512

5.292

6.047

6.803

1.134

The temperature effect most important in the 0·70°C
range is the variation of threshold voltage with
temperature. For typical liquid crystal materials, the
threshold voltage, VTHRESH, has temperature coefficient of - 7 to - 14mV/oC. Since the VOISP is 3.27
times VTHRESH (for 7 row multiplex, see Table 1), the
VOISP has a tempco of about - 25 to - 50 mV/oC,
depending on LCD fluid tempco. As can be seen in
Figure 4, for optimum viewability and contrast ratio,
the driving voltage must be accurately matched to
the LCD threshold voltage. If a significant variation is
temperature is expected, a method of adjusting the
VOISP must be provided. Figure 6 uses the ICL7663
voltage regulator to independently set VOISP and the
tempco of VOISP. The Vbe multiplier circuit of Figure
7 can be used with some displays. Since the Vbe
multiplier's voltage and tempco cannot be independently adjusted, the Vbe multiplier is, suitable
. only for use over a limited temperature range or with
a display whose V01S P tempco matches the Vbe
multiplier tempco.
With the fluids now available for 32 and 64 multiplex
operation it is quite common to have a "Contrast" adjustment accessible to the user. This "Cont~ast" adjustment varies the VOISP to compensate for both
temperature variations and for variations in the viewing angle.

Multiplex Rate and Maximum Drive
Capability
The minimum multiplex rate is determined by the
response time of the LCD. To avoid flicker, the mux
rate should be above 30Hz. The maximum multiplex
rate is determined by power dissipation limits and the
drive capability of the ICM7281.
The drive capability of the ICM7281 indirectly sets the
upper limit of the mux rate. The absolute maximum
limit of DC voltage across an LCD is usually specified
as 50mV. As the multiplex rate increases, any asymmetry in the rise and fall times will cause a DC offset,
in addition to any offset caused by V2 and V3 not being exactly symmetrical with respect to VOISP and
Vee. The ICM7281 was designed to have equal rise
and fall times, as well as low resistance drivers which
make the rise and fall times short. This allows the
ICM7281 to drive over 2000pF at mux rate of 100Hz.
Normally an LCD dot matrix display will have less
than 1000pF capacitance per 40 columns (each
ICM7281 drive 40 columns).

6-151

ICM7281
v+

UNREGULATED

,.

TO SYSTEM REGULATOR

T
V+IN SENSE

VOUT = 1.3 ( 1

+~)

+

~(0.4)

VOUT1

h

VOUT2

r-

>--<1_ VCC ICM1280/81

V4 1CM7280
R2

ICL
7663

V31CM7281

TCVOUT = -~( TCVTC) mV/'C
VSET

~a.

TCVTC = + 2.5mV/'C
VTC

V2 1CM7281

SHUT
DOWN GND

R1

,

V 1 1CM7280

VOISP FROM
ICM 7280 VOLTAGE
INVERTER OUTPUT ....
OR ICL7660

....

"">-.-4-

Figure 6. V DISP Generator

V+

DJ

VCC

V4
R1

V3

V2

R2
V1

V 01SP

V(VCC-VOISP)

~

.6V x ( 1 +

~)

Figure 7. VSE Multiplier

6·152

V01SP ICM1280/81

ICM7281
POWER DISSIPATION
The power dissipation of a display system driven by
the ICM7281 has several components:
1) Quiescent or DC power dissipation of the ICM7281
2) Dynamic or AC power dissipation of the ICM7281
3) Power consumed in driving the LCD display.

This process is repeated for each phase of the
multiplex cycle. The ICL7663 provides a temperature
compensated VDISP to the ICM7280 voltage divider,
which generates the other voltage needed to drive the
LCD display. For further details refer to the ICM7280
Intelligent LCD Row Driver data sheet.

LCD Graphics Display
ICM7281 Power Dissipation
The quiescent current of the ICM7281 is very low,
typically less than 1/LA, and can generally be ignored.
The dynamic current is proportional to the clock frequency, with a typical value of 1.0 mA per MHz. This
means that at a 500 KHz clock the dynamic current
will be 0;5 mAo

LCD Display Drive Dissipation
Since the LCD has very low leakage currents, most of
the power used to drive the LCD is used to charge
and discharge the LCD capacitance. The power is
PLeD
Where:

= C V2 FEFF

PLeD is the power dissipated in driving the
display
C is the display capacitance
V is Voltage across the display

In this circuit,' ICM7281's are used to drive both the
rows and columns of the LCD dot matrix. An external
controller is used to generate the row and column
data that is serially transferred into the ICM7281 'So
The display drive voltages are generated in a resistor
divider network, with the ICL7663 providing the
temperature compensated VDISP. The optimum
voltages for V1 through V5 can be calculated using
the equations of figure 5. Optimum voltages for common multiplex ratios are shown in Table II.
The LCD shown in Figure 2 is a 32 row display, divided into two sections of 16 rows to increase the
ON/OFF RMS voltage ratio, thereby improving the
contrast of the display. As LCD fluids improve it will
become practical to use 32 or 64 row multiplexing,
reducing the number of column drivers by a factor of
2 or 4.
As the number of rows increases, the VDISP required
by the ICM7281's modified Alt and Pleshko multiplex
scheme increases less than the VDISP required by a

F is the effective multiplex frequency
The effective multiplex frequency ranges from FMUX
to N x FMUX, where FMUX is the multiplex rate and N
is the number of rows. The actual effective multiplex
frequency is dependent on which characters or bit
pattern is being displayed and is typically about N/3 x
FMUX

Low Power Shutdown
If the data clock is stopped and the voltages across
the LCD are not changing, the power consumption
will drop to the 5 to 50 microwatt range. Set VDISP, V2
and V3 equal to Vee to prevent permanent damage to
the LCD display by a DC bias. An easy way to shutdown the display voltages is to use the SHUTDOWN
pin of an ICL7663, as shown in Figure 6.

APPLICATIONS
Alphanumeric Display Using ICM7280
Intelligent Row Driver
The ICM7280 Intelligent Row Driver is specifically
designed to drive multiple ICM7281 LCD Column
Drivers. Figure 1 shows a typical 80 character display.
The ICM7280 anp ICM7281's will drive either 7, 8, 9 or
10 row displays, with the characters having either 5 or
6 columns. The Row Driver receives ASCII data, converts that data to bit-by-bit column data for the
ICM7281 's and serially shifts data into the ICM7281 'so

cl,,,,c All aod Ple,hko m,lllple, ,cheme, Fo' e>am·

Ii

pie: a 64 row display with a 1.45V threshold would require + 5V and - 12.4V supplies using standard Alt
and Pleshko multiplexing. The ICM7281 would require only + 5V and - 4.9V to ddve this same display·
with 64 row multiplexing. This means that the
negative voltage could easily be generated using a
charge pump such as the ICL7660 or the onboard
charge pump of the ICM7280.

Serial Input 110 Expander
In addition to driving LCD's, the ICM7281 can be used
as an I/O expander as shown in Figure 8. In this case,
the data can be serially entered into the ICM7281
shift register using the 80C51 serial port. The 80C51
then transfers the data to the output latch by pulsing
the DATA LATCH input with an I/O port line. Note that
multiple ICM7281's can be cascaded to get more than
30 output lines. This cascading does not require any
additional logic since the ICM7281 CARRY OUTPUTs
are used.
DISPLAY CONTROL is tied to V + so that the data on
the column outputs is the same as the data that was
entered. If DISPLAY CONTROL is grounded, the column outputs will be inverted data. With V3 grounded,
the logic level at the column outputs will be CMOS
compatible, swinging from ground to V + . The output
resistance of the column outputs is about 2K ohms.

6-153

.~

ICM7281
. P3.2
OR ~------~-------------.-----~----------.~------------~
OTHER 1/0 LINE

8051 P3.1

t-------------+----....---..."..------------+----.....-'-"'-----------------+-----.-------~

OR

80C51
P3.0 ~----I DATA

DL

+5V

CLK

CARRVt-------I

ICM 7281

+5V

+5V

Figure 8. Serial I/O

PACKAGE OUTLINES

~xpander

7281

All dimensions given In inches and (millimeters).

....

..
."
:s". " :s..
" S" ""
0:

z

"

[
]
r-"""1
F2.G40151.8201~
0.180

II

1411641
MAX

£ -r\
L"~j

-,
tfi\n::~~

JL~l

0.080 (1.524)
,

tci.02O (.51)

0.018

---I!!

~

-

~ TYP,

0.020 (0.608)

0.100

""c~

:::>
0

>-

i!!

....

:::>

I

0

:::>

·0

...
..

0

....

0.025

TO
NEXT

ICM7281

~

~
'" > !Ilc
> ~ >

"

" ""
0

~ ~
.... ....

~

0

0

""

COL2

COL 39

COL3

COL 38

COL4

COL 37

COL 5

COL 36

COL 6

COL 35

COL 7

COL 34

COL8

COL 33

COL 9

COL 32

COL 10

COL 31

COL 11

COL 30

COL 12

COL 29

0.180
14.11641

0.001 10.0211

COL 13

COL 28

MIN.

0880

COL 14

COL 27

(2.540)

(16.184)
MAX.

..

g: ;1;

~
~
....
.... .... .... .... .... .... .... ....
....
0 0 0 0 0 0 0 0 5 0 5 0
0
0 0
0 0
~

40 LEAD PLASTIC (Pl)

~ ~

" ""

:! \!!

"

lQ

!!l

"""

...
..

:::>
:::>
0

....0~
0

DIE

CHIP TOPOGRAPHY

6·154

IID~D~

ICM7555/7556
CMOS
General Purpose Timers

FEATURES

GENERAL DESCRIPTION

• Exact equivalent In most cases for SE/NE555/
556 or the 355.
• Low Supply Current 80llA Typ. (ICM755S)
160llA Typ. (ICM7556)
• Extremely low trigger, threshold and reset
currents - 20pA Typical
• High speed operation - 500 kHz guaranteed
• Wide operation supply voltage range guaranteed
2 to 18 volts
• Normal Reset function - No crowbarrlng of
supply during output transitIon.
• Can be used with big her Impedance timing elements
than regular 555/6 for longer RC time constants.
• Timing from microseconds through hours
• Operates In both astable and monostable modes
• Adjustable duty cycle
• High output source/sink driver can drive
TTUCMOS
• Typical temperature stability of 0.005% per ° C at
25°C
• Outputs have very low offsets, HI and LO

The ICM7555/6 are CMOS RC timers providing significantly
improved performance over the standard SElNE555/6 and 355
timers, while at the same time being direct replacements for
those devices in most applications. Improved parameters
include low supply current, wide operating supply voltage
range, low THRESHOLD, TFjIGGER and RESET currents, no
crowbarring of the supply current during output transitions,
higher frequency performance and no requirement to decouple CONTROL VOLT AG E for stable operation.

APPLICATIONS
•
•
•
•
•
•
•

Specifically, the ICM7555/6 are stable controllers capable of
producing accurate time delays or frequencies. The ICM7556
is a dual ICM7555, with the two timers operating independently of each other, sharing only V+ and GND. In the one
shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. For astable
operation as an OSCillator, the free running frequency and the
duty cycle are both accurately controlled by two external
resistors and one capacitor. Unlike the regular bipolar 555/6
devices, the CONTROL VOLTAGE terminal need not be
decoupled with a capacitor. The circuits are triggered and
reset on hilling (negative) waveforms, and the output inverter
can source or sink currents large enough to drive TTL loads,
or provide minim~1 offsets to drive CMOS loads.

PIN CONFIGURATIONS (Top View)

Precision Timing
Pulse Generation
Sequential Timing
Time Delay Generation
Pulse Width Modulation
Pulse Position Modulation
Missing Pulse Detector

y+

.x.J..\!

}!J

GND
TRIGGeR

AND

~

OUTPUT

CASE
DISCHARGE

~~~ ~.
JJ.. ;g~::gi

THRESHOLD

~

-~
RESET

(OUTLINE DRAWING TV)
~

~~.
ORDERING INFORMATION

TRIGGER

2

OUTPUT

3

RESET

11

-

ICM7555

~V'
~
7

DISCHARGE

THRESHOLD

5

~g~l:8i

(OUTLINE DRAWING PAl
ORDER
TEMPERATURE
PART NUMBER
RANGE
ICM75551PA
ICM75551TV
ICM7555MTV
ICM7556IPD
ICM7556MJD
ICM7555/0
ICM7556/0

-20 to +85°C
-20 to +85°C
-55 to +1,25°C·
-20 to +85°C
-55 to +125·C·

PACKAGE
OISCHARGE
THRESHOLD

8 Lead MiniDlp
To-99 Can
TO-99 Can
14 Lead PlastiC DIP
14 Lead CERDIP

1

~

9
or

~g~i:gi
iiffi'f.
OUTPUT

TiiiGGeii
aND

DICE
DICE

~7

~
ICM7556

I

v'
13 DISCHARGE

~
11

THRESHOLD

;g~1:8t

~ iiEsii'

~8 ~
TRIGGER

(OUTLINE DRAWING JD, PO)

• Add J883B to order number If 883B processing Is desired.

6·155

.D~UIl

ICM7555/lCM1556
ABSOLUTE MAXIMUM RATINGS

(NOTE 1 I

1-

Supply Voltage ............................... +18 Volts
Input Voltage Trigger
Control Voltage Threshold ..... ::; V+ + O.3Vto ~ V- --:c 0.3V
Reset
Output Current .....................•............ 100mA
Power Dissipation,2[
ICM7556 ................. 300mW
ICM7555 ................. 200mW

NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

Operating Temperature Range 12i
ICM75551PA ••.•....... .-20° C to +85° C
ICM75551TV .............-20°C to +85°C
ICM75561PD ........... .-20° C to +85° C
ICM7555MTV ......... -55°Cto+125°C
ICM7556MJD ......... -55°C to +125°C
Storage Temperature .................. '-65°C to +150° C
Lead Temperature (Soldering 60 Seconds) ........ +300° C

QPERATING CHARACTERISTICS

(TA = 25°C, V+ = +2 to +15 Voits unless other specified)
VALUE

PARAMETER

SVMBOL

Supply Voltage

V+

Supply Currentl 3[

1+

Timing Error
Initial Accuracy

Drift with Temperature

Drift with Supply Voltage
Threshold Voltage
VTH
Trigger Voltage
VTRIG
Trigger Current
ITRIG

Threshold Current

ITH

Reset Current

IRST

Reset Voltage

VRST

Control Voltage Lead
Output Voltage Drop

Vcv
Vo

TEST CONDITIONS

--20°C"; TA"; +70°(::
-55°C"; TA"; +125°C
V+= 2V
ICM7555
V+ = 16V
V+ = 2V
ICM7556
V+ = 16V
5V"; V+,,; 15V
RA, Rs = lk to lOOk,
C=O.lIJ. F
Note 4
V+= 5V
Note 4
V+ = 10V
V+ = 15V
V+ = 5V

t,

Fall Time of Output
Guaranteed Max Osc Freq

tf
fma:oc.

0.63
0.29

V+ = 5V
V+ - 16V
V+ = 5V
V+ = 2V
V+ ···16V
V+= 5V
V+ = 2V
VRESET = Ground

V+ = 16V
V+= 5V
V+= 2V

V+ = 16V
V+= 2V
Output Lo

RL = 10Mfl
RL = 10Mfl
Astable Operation

V+= 5V
V+ - 16V
V+= 5V
V+ = 16V
V+= 5V
CL = 10pF
CL = 10pF

TVI'

MAX

UNITS

16
16

V
V

SO
120
120
240

200
300
400
600

IJ.A
IJ.A
IJ.A
IJ.A

2.0
50
75
100
1.0
0.66
0.33
50
10
1
50
10
1
100
20
2
0.7
0.7
0.66
0.1
0.15
17.6
4.5

5.0

2
3

V+ = 5V

Output Hi
Rise Time of Output

MIN

0.4
0.4
0.S2
ISINK - 3.2mA
ISINK = 3.2mA
ISOURCE = 1.0mA
ISOURCE = 1.0mA
V+=5V
V+=5V

17.25
4.0
35
35
500

40
40

%

ppmloC

3.0
0.S7
0.34

1.0
1.0
0.67
0.4
0.4

75
75

%N
V+
V+
pA
pA
pA
pA
pA
pA
pA
pA
pA
V
V
v+
V
V
V
V
ns
ns
kHz

NOTES:
1. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal toa voltage greaterthan V+
+0.3V or less than Y--·-1J.3V may cause destructive latch up.
For this reasan it is recommended that no·inputs from external sources not
operating from the same power supply be applied to the device before its power sUpply is established.
I n multiple systems, the supply of the
ICM7555/6 must be turned on first.
2. Junction temperatures should not exceed 135°C and the power dissipation must be limited to 20mW at 125°C. Below 125°C power.
dissipation may be increased to 300mWat 25°C. Derating factor is approximately 3mW/oC (75561 or 2mW/oC (755SI.
3. The supply current value is essentially independent of the i'Fii'G'G'EFf, THRESHOLD and RESET,voltages.
4. Parameter is not 100% tested, Majority of all units meet this specification.

6-156

ICM7555/ICM7556
TYPICAL CHARACTERISTICS

.

MINIMUM PULSE WIDTH
REQUIRED FOR TRIGGERING

"
""

r.

1
fA

i'1000
-

g. .

l-

e..

:r

"i...

7. .

~ .00

I

500

rr- -

~-

:>

Z
i

y' ,2V

200

v - 'v ;;;:::::::

'00

C

180

3eO

~

160

320

-

~ 100

f----

~

,-

20

a.
a.

~

_.- r--

30

60
40
20

40

~

i

.9

ffi,

... 10.0

"II!

.!!iz

I

Ui

§.

ffi

1

V'

c-

2V -

~

"":>

.

'.0

0.01

0.'
1.0
OUTPUT LOW VOLTAGE VOL

·2

U

ffi

:>

0

I--

:l:

2

1---

ffiN

4

~

.
::;

~

6

Z

e

o

f--f---

0.'

"-

l

--+

:/

e-

'0.6

-0.3

ffi

-0.2

ii

-0.1

".

"r

D

~

,I-""

v .o,ev/

/

/

in
t.O

V

<
:r
~

0.'

1.0

1

1

I

l

'0.

''''(1

' - ~ ~I
"

, p'0.'

TA

~'.

~

'1J

v-

2D"e-

r-- --

."

200

If

'00

o

10

20

30

40

T'iiiG"GE'R PULSE (% V')

TIME DELAY IN THE MONOSTABLE
MODE AS A FUNCTION OF RA AND C

1,\
1\

V
V V

100J.lF

10J,lF

~'%'--V

'.'

10nF

'n'
lOOpF

M
10M

tOpF

, p'

v

V,ii>*",;" V
./
V
V~
''~-."
" ~
/'V v
R,

100nF

100 lk
10k lOOk 1M
FREQUENCV (Hz)

6-157

,

,m'

:-.......

I"

TA'" 25"C

10mF

1

I'\.
'\:
."',,1\
\ \ \

1

100mF

~;",

10

!J

TA '" +70"C

1.0F

25'C

10pF

1

LOWEST VOLTAGE lEVEL OF

N

100 pF

10.0

Y' "'- 5Y

TA '" +25"C

10.0

FREE RUNNING FREQUENCY AS A
FUNCTION OF RA, Rs and C
TA

1.0

0

0.1

0.01

0.1

a.

-

10nF

Tao

400
300

;:
<

y' '" 2V

100nF

-60

/'

/

500

0

V

w

~

.......... ..........

120
+40
TEMPERATURE ~c

I
>

, "'.' , , ~
, '00°", ,
, ~/
,
'n'

Z

600

:l...

'm' ~ ..,--....I~' ' J.B)
I
l00';.tF

0

y""-2Y

PROPAGATION DELAY
AS A FUNCTION OF
VOLTAGE LEVEL OF TRIGGER PULSE

Z

10j,lF

e:

~ ~"'5V -

OUTPUT LOW VOLTAGE VOL

DISCHARGE LOW VOLTAGE VOL

·0.4

/

0

SUPPLY VOLTAGE (YOLTS)

·0.1

/

/ /

1.0

V
0.'0.01

10.0

C

100.0

l"v,L

u

,;'

~

10mF

N

-

l-

~

Z

;: ·0.8

-0.5

#

IJ.

tz 10.0 I-~
:>
~

"u

1.0F

>

-,

1

To\ - 70"C

2

U;

2S C

~ 10.0

100mF

~

,
V ~,J-

:

f---

-1.0

u

'00

J.-tTl

0.1
1.0
OUTPUT lOW VOLTAGe VOL

T,

Z

',0.9

...:>Z

i

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

DISCHARGE OUTPUT CURRENT
AS A FUNCTION OF
DISCHARGE OU1PUT VOLTAGE

~

0

-10.0 en

-

V' --18V

20

/

0.'
0.01

§.

~_ -I :0:1"

10.0

...

u

"o:>

'"

o

0-

R, R, tOM!!
C
100pF
~'
-1-' c~fRB 'Okl! \
1.0

r,-;

0

Z

.~

18

v· -, 2V-

~

~

~:>

100

L/' /'IA~
JJr/' / ' V V
II /' V V
1
1

10

IA'

""

~

a:

"a

:>

10.0

NORMALIZED FREQUENCY STABILITY
IN THE ASTABLE MODE AS A
FUNCTION OF TEMPERATURE
0

16

I" /

V'

2.5~C

1/ i\

~o
>

12 14

1 1

25"C

V-

'00
6

L

5V

1.0

V

iiI-

a.

NORMALIZED FREQUENCY STABILITY
IN THE ASTABLE MODE AS A
FUNCTION OF SUPPLY VOLTAGE
T,

>

40

:>

0'

'20

I-

:>

o

~

10

u

0-

-

:>

~

8

c-

in

--

6

_1~11I, II
/

Z

/

~

r~'

10.0

0-

V

1/
1.0

V'

I"

'/

i
4

~-' J_v',ev

.9

1--4
;1_' -

u

...

"":>
u

eo

1--2

2
g

'60

S

v· ~ 2VI"""

~

+--

~/

-

r-

0-

II

~

~

i

200 Z

t2S¢C

f-- ~'7~'C

-

~.,

//

TA '" 25°C

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
'00

20~ht
tt4~ L
.
v
=,i~
n,I,vh~-17 -

240

OUTPUT VOLTAGE REFERENCED TO V'
·1 0
0'
-001

10

SUPPL y VOLTAGE (VOLTS)

OUTPUT SINK CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE
T,

TA" "20°C

y

,...... T,

l-

LOWEST VOLTAGE LEVEL OF TiiiG'GiRPULSE (%Y")

'00

V

'-"

;-

80

U

>

- r--

1--

2eo

-r:: -

120

I-

.

- r--

-f--r-

10

400

~ 14C

/
If)

~~

200

"g

D

1---

300

I

'8

_.

_.-

I-- - -

.. 4"
e- -V
ii

II

. 25°C

OUTPUT SOURCE CURRENT AS A
FUNCTION OF OUTPUT VOLTAGE

SUPPL Y CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

100
;.IS

1

10

m. m.

TIME DELAY

100
ml

,;"
,;"
,;"
/'
,;"

.

,.

.

!;

o

ICM7555/lCM7556
v·

APPLICATION NOTES
GENERAL
The1CM7555/6 devices are, in most instances, direct replacements for t~e N~SE 555/6 devices. Howeyer, it is possible to
effect economies in the external component count using the
ICM7555/6. Because the bipolar555/6 devices produce large
crowbar currents in the output driver, it is necessary to decouple the power sUPPI'y lines with a good capacitor close to the
device. The 7555/6 devices produce no such transients. See
Figure 2.

10K

OUTPUT

<>-<..----jl---!

500
TA == 25°C

40 0

.'7" .
.i

300

Figure 3: Astable Operation

A

MONOSTABLE OPERATION

\lSEINE555

~

II:

~ 200

U

~ 10~

"

-~'CM7555I56

200

400
TIME·

n.

• 00

•••

Figure 2. Supply Current Transient Compared with a
Standard Bipolar 555 During an Output Transition

In this moae of operation, the timer functions as a one-shot.
Initially the external capacitor (C) is held discharged by a
transistor inside the timer. Upon application of a negative
TRIGGER pulse to pin 2, the internal flip flop is set which
releases the short circuit across the external capacitor and
drives the OUTPUT high. The voltage across the capacitor
now increase,s exponentially with a time constant t = RAC.
When the voltage across the capacitor equals 2/3 V+, the
comparator resets the flip flop, which in-turn discharges the
capaCitor rapidly and also drives the OUTPUT to its low
state. TRIGGER must return to a high state before the OUTPUT can return to a low state.
'
v'

The ICM7555/6 produces supply current spikes of only 2-3
mA instead of 300-400 mA and supply decoupling is
normally not necessary. Secondly, in most instances, the
CONTROL VOLTAGE decoupling capacitors are not
• required since the input impedance of the CMOS
, comparators on chip are very high. Thus, for many applications 2 capaCitors can be saved using an ICM7555, and 3
capacitors with an ICM7556.

t '" O.69RC

R,

6'

SL

OUTPUT

L-REsET'

6~~:~RHO:LD
5 VQlJ~GE
I
I

OPTIONAl.~
V':s 18V

CAPACITOR

I.

"*

POWER SUPPLY CONSIDERATIONS
Although the supply current consumed by the ICM7555/6
devices is very low, the total system supply can be high
unless the timing components are high impedance.
Therefore, usp high values for R and low values for C in
Figures 3 and 4.

OUTPUT DRIVE CAPABILITY
The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTL. As
such, if driving CMOS, the output swing at all supply
voltages will equal the supply voltage. At a supply voltage of
4.5 volts or more the ICM7555/6 will drive at least 2 standard
TTL loads.

Figure 4: Monostable Operation

CONTROL VOLTAGE
The CONTROL VOLTAGE terminal permits the two trip
voltages for the THRESHOLD and TRIGGER internal
comparators to be controlled. This provides the possibility of
oscillation frequency modulation in the astable mode or
even inhibition of oscillation, depending on the applied
voltage. In the monostable mode, delay times can be
changed by varying the applied voltage to the CONTROL
VOLTAGE pin.

RESET
The RESET terminal is designed to have essentially the same
trip voltage as the standard bipolar 555/6, i.e. 0.6 to 0.7 volts. At
all supply voltages it represents an extremely high input impedance. The mode of operation of the RESET function is, however, much improved over the standard bipolar 555/6 in that it
controls only the internal flipflop. which in turn controls simul~
taneously the state of the OUTPUT and DISCHARGE pins.
This avoids the multiple threshold problems sometimes encountered vyith slow falling edges in the bipolar devices.

ASTABLE OPERATION
The circuit can be connected to trigger itself and free run as a
multivibrator, see Figure 3. The output swings from rail to rail,
and is a true 50% duty cycle square wave. (Trip points and
output swings are symmetrical). Less than a 1% frequency
variation is obsE/rved, over a voltage range of +5 to +15V.
1
f=l.4RC

6-158

ICM7555/1CM7556
EQUIVALENT CIRCUIT
v'

THRESHOLD
o~-r---I

CONTROL
VOLTAGE
OUTPUT

r.ND

BLOCK DIAGRAM
v'

,
OUTPUT
DRIVERS

THqESHQLD
6~----+--I

5

<>c---,----+
CONTROL

P-M»......I>>-<> OUTPUT

VOL TAGE

OJ

COMPARATOR

This block diaQram reduces the circuitry down to its simplest equivalent components,
Tie'down unused inputs.
R = 100kn, ± 20% typ.

TRUTH TABLE

THRESHOLD
VOLTAGE

TRIGGER
VOLTAGE

DON'T CARE

DON'T CARE

LOW

>2/3(Vt)
VTH <2/3

>1/3(V+)
VTR > 1/3
<1/3(Vt)

HIGH
LOW
HIGH STABLE
HIGH
HIGH

DON'T CARE

RESET OUTPUT
LOW

NOTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD,

6-159

DISCHARGE
SWITCH
ON
ON
STABLE
OFF

ICM7555/1CM7556
CHIP TOPOGRAPHIES
ICM7555
CONTROL
VOLTAGE

1

ICM7558
GND

RESET OUTPUT
\
./

~ ••

3

t

TH"ESHOLD'.~
DISCHARGE 7
r.

.040"

1

y' 8

1("'11"

4 RESET

RESET 10

CONTROl"
VOLTAGE

2 ;RIGGER

(1.02mm)

OUTPUT 9

.050"
(t.27mm)

3 CONTROL

VOLTAGE

1 GND

~(1'~~)~

THRESHOLD 12

2 THRESHOLD

IDISC~A"GE
13

"
...: ,

(1.7mm)

DJ

6-160

D~I

Stopwatches
ICM7045
ICM7215

Clock Generators
Page
7-10
7-47

ICM7209
ICM7213

7-39
7-42

Frequency Divider
Display
Watches/Clocks
ICM7223
ICM7223A
ICM7223VF

ICM7241
7-53
7-59
7-67

Touch Tone
Encoder
ICM7206

Analog
Watches/Clocks
ICM1115
ICM7038
ICM7050
ICM7051
ICM7070
ICM7245

7-19
7-5
7-19
7-23
7-27
7-77

7-75

7-31

TIMEKEEPING, DTMF CIRCUITS

Watches
Typical Current
___
pa_rt_N_u_m_be_r__~________________________________~C_lrc_u_it_O_es_cr~ip_ti_on_____________________________________~_t.55VOC
ICM7245B/0/E/F
ICM7245U

Analog quartl watch/clock CirCUIt. ICM7245B/D/E/F for bipolar stepper motors. ICM7245U for unipolar.
stepper motors. Ultra high accuracy 0.1 ppm

Notes: Allintersil watch circuits are designed for use with a 32.768Hz quartz crystal, All provide a rapid advance setung

Watch cirCUits are normally sold in .die form. The ICM7245B/O/E/F and ICM7245U are available in eilher an 8 pin plastic DIP or mini-flalpack as well as dice.
Allinlersil watch cirCUits have a fixed on-chip oscillator capaCitor. The above circuits show lypical current at 155 Volts LCD units in doubler mode.

Dual Tone (Touch Tone) Encoders
Part Number

Circuit OelcrlptlOft

Package

Crystal Frequency

Output

ICM7206

Touch-tone encoder: requires Single contact per key

16-Pm DIP

3.57954 MHz

2-of-8 sine wave for tone dialing

ICM7206A

Touch-tone encoder: requires one contact per key
with common line connected to • supply.

16-Pm DIP

3.57954 MHz

2-of-8 sine wave for tone dialing

ICM7206B

Touch-tone encoder: requires 2 contacts per key
with common line connected to negative supply:
OSCillator enabled when key is pressed.

16-Pin DIP

357954 MHz

2-of-8 sine wave for tone dialing

ICM7206C

Touch-tone encoder requires single contact per
key: oscillator enabled only when key is
depressed. Disable line tied to V-

16-Pin DIP

3.57954 MHz

2-of-8 sine wave for tone dialing

ICM7206D

Touch tone encoder: requires single contact
per key: oscillator enabled only when key is
depressed. DISABLE line tied to V + .

16-Pin DIP

3.57954 MHz

2-of-8 sine wave for tone dialing

Clock and Timing Signal Generators
ICM7209

High-frequency clock-generator for 5-voit systems

8-Pin DIP

to 10 MHz

Crystal frequency. plus

ICM7213

Oscillator and frequency divider

14-Pin DIP (plastic)

to 10 MHz

Ipps. Ippm. 10 Hz. composite

7·2

8 divider stage

Clocks
Typical
Operaling
Part Num._b_l_r__________________C_ir_cu_II_O_e_sc_r..:.ip_tlO_n. ______._ _ _ _ _ _ _ _ _ _ _ _-V-ol-ta;;..ge----packagl
ICMI115
ICMI115A
ICM1115B

Analog Quartz clock CIrcuit with simple alarm For bipolar stepper motors: 1 Hz square wave output fose =4.19MHz
Analog Quartz clock circuit with simple alarm For bipolar stepper motors. 1 Hz square wave output fose = 4 19MHz
Analog Quartz clock circuit with simple alarm For bipolar stepper motors: I Hz square wave output fose = 4.19MHz

t5V

8 pin DIP

ICM7038A
ICM7038B

Analog Quarlz clock CIrculi with simple alarm. For synchronous mOI~rs
Analog Quartz clock circuli with simple alarm. For synchronous molors

30V
t5V

8 pin DIP

ICM7050

Analog Quartz clock circuli with complex alarm. For bipolar stepper motors 47 ms pulse width.
1Hz ratefos e =4.19MHz

15V

8 pin DIP

ICM7051A
ICM7051B

Analog quartz clock circuit for automollVe applications-synchronous motors. 64 Hz square wave
Analog quartz clock CIrCUli for automotive applications-bipolar stepper motors
31 ms pulse width. 1Hz rate

12.0V

8 Pin DIP

ICM7070L

Analog Quartz clock circuit with complex alarm For bipolar stepper motors, 31 ms pulse width
@ 0.5 Hz fose = 32 kHz

1.5

8 pin DIP

ICM7223
ICM7223D

4 DI91t LCD Alarm Clock with Snooze
•
Drrect drive Crrcket alarm 24 hour format by bond option For 32.768 kHz Quartz crystal

15V

40 pm DIP

- ICM7223A

4 Digit LCD Clock RadIO CIrCUit With Sleep Timer. Snooze and Alarm. Low ballery indIcator
RadIO Enable. For 32.768 kHz Quartz crystal

9.0V

40 pin DIP

120V

40 pin DIP

ICM7223VF

4 Digit Vacuum Fluorescent Clock RadIO/Auto Clock.crrcult With Sleep Timer. Alarm. Snoole
and RadiO Eeable For 32.768 kHz Quartz crystal

8 pin DIP

Notes: All Analog clock crrcults are deSigned for use With a 4 19 MHz Quartz crystal. WIth the exception of the ICM7223 serres which uses a 32 768 kHz crystal
Clock Circuits are normally purchased in package form: each IS also available as dice
All Analog clock circuits are mask programmable for oscillator frequency output frequency and pulse Width. and alarm frequency_ Consult the factory for
details

Stopwatch~s
Part Number

Circuit Description

Cry st. I
Frequency

Paokage

ICM7045

8 DIgit 4 Function LED stopwatch circuit Features Hours Minutes Seconds 100ths Provides Time Out. Taylor
Spilt and Rally modes Drrect drive for LEOs May be used as 24-hour clock

655 MHz

28 pin DIP

ICM7215

6 Digit 4 Function LED stopwatch errcult. Features MInutes Seconds.l00ths PrOVides Trrne out Taylor and
Spilt modes Drrect drive for LEOs

3.28 MHz

24 pin DIP

NOles' All sfopwatches may be purchased as an Evaluation Kit lEV KIT) whICh Includes the Ie and the appropriate Quartz crystal All operate at 25 10 4.5 volts. and
source 15 mA Clirrent to the segments of the LEOs

7·3

CMOS
OSCILLATOR/DIVIDER/DRIVERS
SELECTION GUIDE
(Includes circuits used in quartz analog clock and watch applications)

PRODUCT
NUMBER

MASK
VARIANT

CRYSTAL
FREQUENCY

MOTOR
DRIVE
OUTPUT

OUTPUT PULSE
CHARACTERISTICS
ALARM
NOMINAL
Width
Freq.
FREQUENCY VOLTAGE
(pulses
(V)
(ms)
per sec)
(Hz)

(MHz)

PACKAGE[4j

(IlA)

iCM7Q38A

4.19

Synchronous

7.8

1

64

512

3.0

90

S-pin DIP

iCM7038B

4.19

Synchronous

7.8 1

64

512

1.5

40

8-pin DIP

ICM7213

4.19

Multiple

3.0

100

14-pin DIP

{

7.8
31.2
125

1~

}024+16t2
1 per min.

4.19

Unipolar

15.6

j

1024

1.5

40

8-pin DIP

4.19

Bipolar

46.9

0.5

2048+8+1

1.5

40

8-pin DIP

4.19

Bipolar

64

4.S-13.S

500

8-pin DIP

4.19

Bipolar

31.2

O.S

4.5-13.S

SOO

S-pin DIP

I CM7070Ll21

32 kHz

Bipolar

31.2

0.5

1.S

3

8-pin DIP

ICM724SAI 21

32 kHz

Bipolar

9.7

0.5

1.S

0.4

8-pin DIP

ICM724SBI21

32 kHz

Bipolar

7.8

0.5

0.4

8-pin DIP

ICM7245DI 21

32 kHz

Bipolar

7.8

1 per 10 sec

0.4

S-pin DIP

ICM724SEI21

32 kHz

Bipolar

7.8

1 per 12 sec

1.S

0.4

S-pin DIP

ICM7245FI21

32 kHz

Bipolar

7.8

1 per 20 sec

1.5

0.4

S-pin DIP

ICM7.24SU121

32 kHz

Unipolar

1.5

0.4

S-pin DIP

ICM7050A

ITS9044-1

ICM7050
ICM7051A
ICM7051 B

g

TYPICAL
CURRENT

ITS9042-1

7.8 111

ICM1115A

4.19

Bipolar

3.9
1
_.,---0.5
1000 111

ICM111SB

4.19

Bipolar

looo11i

All Intersil analog quartz products are mask programmable. Options include:
• Crystal frequency! 32 kHz, 1 MHz, etc.;
• Pulse width 1500 msec to 3.9 msec,
• Pulse frequency: 64 Hz to O.S Hz 1
• Alarm frequency 164 Hz to 4096 Hz, including complex,
• Motor drive characteristics
• Oscillator characteristics, including fixed capacitors IICM70S0

7-4

0.5

2048+8+1

1.5
----_._-_._---1.5

---------

64

1.S

80

8-pin DIP

64

1.5

40

S-pin DIP

Notes: 11 i Square Wave.
121 Includes a fixed value capacitor on
oscillator input.
131 Includes snooze.
141 Allintersil analog quartz products may be
ordered in die form.

ICM7038 Family
CMOS Analog Quartz
Clock Circuit
Synchronous Motor Applications
FEATURES

GENERAL DESCRIPTION

• Battery operation: 1.2 to 3.6V devices

The ICM7038 family of synchronous motor drivers is
designed to operate from a 1.5V battery, and performs
the functions of oscillator, frequency divider and out·
put driver. In addition a power driver is tapped off from
the thirteenth divider for US!l as an alarm driver.

• Very low power: 3OJ-tA typical (1.5V parts)
• High output current drive: 1 mA minimum
• Zero output bridge DC component (50% duty cycle
square wave)
• All inputs fully protected precautions required

Specifically the ICM7038 family uses an inverter oscillator
having all biasing components on chip. Binary dividers per·
mit frequency division from 4 MHz down to 64 Hz. The out·
put from the divider network drives a bridge output circuit
which provides a 50% duty cycle AC square wave having vir·
tually zero DC component for driving a synchronous single
phase motor. The total output drivers saturation is typically
200 ohms providing efficient operation of synchronous
motors. The alarm output will drive a transducer (piezoelec·
tric or speaker).

no special handling

• Wide operating temperature range: -20"C to

+ 70"C

TABLE OF OPTIONS
The ICM7038 may be modified with alternative metal
masks to provide any number of binary divider stages
up to a maximum of 19 and supply voltages from 1.2 V
to over 3.6V together with various output options. Con·
suit your Intersil representative or the factory for fur·
ther information. The alarm output can be tapped off
from any of the latter divider stages.
(See table for standard options).

Part
Number

Binary
Dividers

Nominal
Output
Frequency

Nominal
Supply
Voltage

ICM7038A
ICM7038B

18
18

84 Hz
84 Hz

3.0V

ORDERING INFORMATION

PIN CONFIGURATION
(OUTLINE DRAWING PAl

~~Blh;'
L PACKAGE

r-v-- ~OSCIN

v+[[.

~ ose OUT

v- [ [
OUT, [ [
OUT 2

[£

~

NC

~

ALARM OUT

(PA'" 8 PIN PLASTIC DIP)

.

I" TEMPERATURE RANGE
INDUSTRIAL:
-20 to +70"C
ELECTRICAL OPTION

TOP VIEW

'-------- TYPE

PIN liS DESIGNATED BY EITHER A DOT OR A NOTCH.
ORDER DEVICES BY FOLLOWING PART NUMBERICM70388 I PA

7·5

1.SV

ICM7038 Family
ABSOLUTE MAXIMUM RATINGS

TEST CIRCOIT

Power Dissipation Output Short Circuit(1) .... 300mW
Supply Voltage:
ICM7038A ............................... 5V
ICM70388 ................ , .............. 3V
Output Voltage (2) ...................... V- to V+
Input Voltage (2) ....................... y- to V+
Storage Temperature ............ -30·C to +125·C
Operating Temperature ........... -20·Cto +70·C

QUARTZ CRYSTAL PARAMETERS
f = 4,194,304 Hz
RS= 35n

v+

Cm =10mpF

OR V-

Co = 3.5 pF

~g~F

NOMINAL
VALUE

SINGLE PHASE
64H,

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of thedevicesat
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended period~ may cause device failures.

SYNCHRONOUS
MOTOR

512 Hz
50% DUTY CYCLE
SIMULATED ALARM LOAD

NOTES:
1. This value of power dissipation refers to that of the package and will not be obtained under normal operating conditions.
2. Except for instantaneous static discharges all terminals may exceed the supply voltage (2.0V max) by ±O.S volt provided that the
currents in these terminals are limited to 2mA each.

OPERATING CHARACTERISTICS
(V + = 3.0Y (ICM7038A) or 1.5Y (ICM7038B), fo~c = 4,194,304 Hz, test circuit 1, T A = 25'C, unless otherwise specifed.

Parameter

Symbol

Supply Current
Guaranteed Operating Yoltage Range
Total Output Saturation Resistance
Alarm Output Saturation Resistance

iii

1+
y+

7038B/D/EIG
7038A1C/F
Min. Typ. Max. Min. Typ. Max. Unit

Conditions

90
-20'C

RSAT
RAL

Oscillator Stability

fSTAB

Oscillator Start·Up Time

tSTART

:s

to

:s

70'C

2.2

p + n Output Transistors,
lOUT 0.5mA

=
lOUT = 1mA

Over y+ range
CIN
V+

v+

~:

J

512 Hz

v+
05

~

AlARM~
OUT

v+~
Q1

OUT 1 3

v-

vALL ZENER DIODES HAVE TYPICAL
BREAKDOWN VOLTAGES OF 7 VOLTS

02

64

7-6

P

'

N

H~

30
1.2

60

pA

1.8

V

230

400

200

700

0

200

400

300

SOO

0

1
1.0

v+

v-

3.6

1

= COUT = 15pF
= min.

SCHEMAT'CD'AGRAM ('CM7.'•• )

v+

150

ppm
1.0

sec

ICM7038A
TYPICAL OPERATING CHARACTERISTICS (ICM7038A)

MINIMUM OPERATING SUPPLY VOLTAGE
VS. TEMPERATURE

OSCILLATOR STABILITY VS.
SUPPLY VOLTAGE

z

e

Vi

'2
TA '" 23°C

f-

\,0;10 0F

~

c;

\
\-..l--'5i15

~

-

C'''J/Cc,'

0

>-

~

E

U

~ ci.

"

""'"

o_
UJ

~

a:

0
0

of

~
w

,....~

CJ

<:

30/30 PF

l

0

f-

j
1

Sl0

1

3

2

=15/15pF

~

,,~,

0

f"'4.194MHz

4
II

>

J'

;;:

:;:

5

a'="

fos = 4.194 MHz

4

SUPPL Y VOLTAGE (V oo

f-

RANGEl
OPERATION

20

0

2

a'="
>

1

~

0

;;;

5

oJ

3 f-

Vssl

+40

'20

+60

'80

TEMPERATURE (OC)

OUTPUT CURRENT VS.

OUTPUT SATURATION VOLTAGE

SUPPLY CURRENT VS.
SUPPLY VOLTAGE

-4

I
~ 400

;{

RL • ""

-

~

~

1-1100

c-0

z

w

~ 120

y

11 MHz

8MHz.r:;VV

V-2 MHIZ-

4MH~262kHz
1

2

>::> 80
a.
f-

"

0

1

3

.s

18

~
a:

14

f-

"
U

16
12

f-

10

i?
f-

8

"0w
CJ

0

'"'"

6
4
2

}...
Voo

r--+-- 1'""-i"\V
l\.
I-~

Nv

r--t:--. I'Z~
0

1

2

m

40

20

2V~

r---4V

p- ¥ V

\
1,\

-<

~

0

V

1,\

3

z

'3

~~

10 ;(

.s
f-

3Vf-'" ~

1,\

1'\

0

:xl

I - - 2V

Vss '" 5V

i'\

§5

4V3V

IA ~123'IC

I'"'

r....

()

-18

ALARM OUTPUT CURRENT (SOURCE)
VS. OUTPUT SATURATION VOLTAGE

BRIDGE OUTPUT CURRENT VS.
BRIDGE OUTPUT VOLTAGE

20

c:
-<

"-<

I

J::::==

0

-12 c:

OUTPUT SATURATION VOLTAGE

V,,)

SUPPLY VOLTAGE (V oo


U

a:

.
:>
u

'~'~ ~'0PF

-'

..

.

ffia:

./

60

40

-2

.§

l/

>

t:>

:<

,/

Q

.Ez

./

-,

~

:>
Q

~

-6 ~------~~~~-------+------~

;.......---

20

_8L-____

cO

1.2

1.8

1.S

~

______-L______L-____

-2

~

.-1

SUPPL Y VOL TAGE

ALARM OUTPUT SATURATION VOLTAGE

OSCILLATOR STABILITY VS. SUPPLY VOLTAGE
CRYSTAL PARAMETERS
PER TEST CI.RCUIT PAGE 2

1oS

CIN/COUT"" 10Pf/307

':i

.
...
Ii
>

::;
iii

a

V

./

30/10

. 0

-1

-2

-

~

15pF/15pf

/'"

3Opf/l0pF

1.8

1.5

1.3

SUPPL Y VOL T AGE

BRIDqE OUTPUT CURRENT VS.
BRIDGE OUTPUT VOLTAGE

MINIMUM OPERATING SUPPLY VOLTAGE
VS. TEMPERATURE
3.0

-

TA = 25°C

r--... .........

f '"

"VOD

=

1.65V

.

~

I'-. r-..... "\
vIDO=

1.5V

I--i-r-VOD'" 1.2V

i I

o

o

-.........

~. 194,301 Hz

2.0

~

>

[\. \

-'

, ,

t

a

1\ 1\

'" 1"\

--

a
>

1.0

,

f\ 1\
[\\

1.0

o

-40

2.0

-20

'20

+40

TEMPERATURE lOCI

BRIDGE OUTPUT VOL rAGE

7·8

+60

'80

ICM7038 Family
APPLICATION NOTES

feedback resistor is provided on chip, which has a
maximum value at start up. Oscillator tuning should be
done at'the oscillator output.

GENERAL DESCRIPTION
The ICM7038 Family has been designed primarily for
quartz clock and timer applications using oscillator
frequencies between 2.0 and 10 MHz. The design
objectives were exceptional oscillator frequency
stability, very low power, wide supply voltage range
and wide temperature range. The oscillator contains all
components except the tuning components and quartz
crystal. Three outputs are provided. The two principal
outputs are intended to be used to drive a single phase
synchronous motor in a bridge configuration. As such,
because of the matching of the transistors in the two
outputs, the output DC component is extremely small.
Stepper motors may also be used by placing a
capacitor in series with the motor and using either a
single output or the bridge output.

The following expressions can be used to arrive at a
crystal specification:
Tuning Range
III

Cm
C - CINCOUT
L - CIN+COUT
= 2(Co + CLI
gm required for startup

f

gm =

0---1

CINCOUT Rs (1 +

~~ ) 2

Rs
f
af

= series resistance of the crystal
= frequency of the crystal
= frequency shift from series resonance
frequency
Co = sta1ic capacitance of the crystal
CIN =-input capacitance
COUT = output capacitance
CL
= load capacitance
Cm = motional capacitance
0)
= 217'f

Voo
DR

0)2

DR

Vss

The resulting gm should not exceed 50 ILmhos
Alternatively outputs 3 and 4 may be used to drive TTL
logic directly for timer applications.
The alarm output is taken from the output of the
thirteenth divider and can source 1 mA at a low
saturation voltage.

2VMAX

The ICM7038 may be used as a straight
driving directly into the oscillator output
with a low impedance square wave drive.
may be used over the frequency range 1
MHz.

divider by
(pin no. 7)
As such it
MHz to 10

OSCILLATOR CONSIDERATIONS
The oscillator of the ICM7038 is designed to operate
with crystals having a load capacitance of.10 to 12 pF.
This allows nominal capacitor values of 15/15 pF or
20/20 pF. Increasing the load capacitance of the crystal
requires larger oscillator device sizes, which causes
the supply current to increase. Modifications to the
oscillator can be made on a custom basis. The tuning
range can be increased by using crystals with lower
load capacitances, however, the stability may decrease
somewhat. This can be counteracted by reducing the
motional capacitance of the crystal. A non-linear

7-9

ICM7045

CMOS Precision
Decade Timers
FEATURES
• Total integration: includes oscillator, divider,
decoder driver on chip
• Wide operating supply range: 2.5V s V + s 4.5V
• Low operating power consumption:
0.9 mW @ 3.6V supply with display off
• High output current drive: .18 mA peak curr~nt
per segment with 12.5% duty cycle.
• Leading zero suppression: timer stopwatch
applications
• Fractional second suppression: 24·hour clock
application
• Short duration short circuit protection on all
inputs and outputs at 3.6V supply
• Versatility of applications: precision timer,
4 mode stopwatch, 24·hour clock
• Uses 6,5536 MHz quartz crystal for high
accuracy

.GENERAL DESCRIPTION
The ICM7045 is a fully integrated precision decade timer
fabricated using Intersil's low voltage metal gate C·MOS
technology. The oscillator, frequency divider, multiplexer,
decoder, segment and .digit output buffers are all included
on,chip. The circuits are designed to interface directly with
fully multiplexed a·digit 7·segment common cathode LED
displays. The normal supply voltage is 3.6V, equivalent to a
stack of three nickel cadmium batteries.
This circuit is designed for use as a digital timer,
4·function stopwatch and 24 hour clock; the only external
components required are the display, batteries, 6.5536
MHz crystal, turning capacitor and 4 switches.
The ICM7045 divides the oscillator frequency in sixteen
binary stages to a frequency of 100 Hz; some of these
intermediate outputs are used to generate the multiplex
waveforms at a 12.5% duty cycle/800 Hz rate. The 100 Hz
signal is then processed in the counters and multiplexed
in the decoders.

-- r---------,---------,
_

BLOCK DIAGRAM

PIN CONFIGURATION (outline dwg DI)

,8 SEG a

v+
SEGd '

a LINES

8 LiNes

7 LINES

26

SEG,

GROUND .,

76

CATH 5

CATH 3 c

,., CATH 6

CATH 4

b

73

TEST POINT

7

22

CATH 7

8,

" CATH 8(7045)

9

20

OSC OUT

10

19

OSC IN

1 & 2 ADVANCE
CATH 1 (MSD)
START/STOP

ZENER DIODE HAS TYPICAL BREAKDOWN VOLTAGE OF 5.6V

CATH 2

ORDERING INFORMATION
ICM7045

I

I

I

DI

DISPLAY"
STANDARD
SPLIT

Package

L- Temperature
''''" ",,'"Range
Doe

RALLY

I = Industrial - 20 'C to + 65 'C

Type
Order Dice by Following Part Number -

ICM7045/D

7·10

" .DIGITS 3 & 4 ADVANCE

SEG e "

" SEG g

12

17

13

16

SEGb
RESET

14

15

SEG c

ICM7045
ABSOLUTE MAXIMUM RATINGS
Power Dissipation (1) ................................................... 1W
Supply Voltage ..................................................... + 5.5V
Input Voltage ................ Equal to, but never in excess of the supply voltages
Output Voltage .............. Equal to, but never in excess of the supply voltages
Digit Drive Output Current ....................................... 150mAJdigit
storage Temperatures .................................... - 55"C to + 125"C
Operating Temperatures ................................... - 20"C to + 85"C
Lead Temperature (Soldering, 10 sec) .................................. 300"C
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation of the device at
these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Note 1: This value of power dissipatiqn refers to that of the package and will not be obtained
under normal operating conditions.

TYPICAL OPERATING CHARACTERISTICS
TEST CONDITIONS: V + = 3.6V, TA = 25"C Parameters listed are absolute value
PARAMETER

Supply Current

SYMBOL

1+

Operating Voltage

V+

Segment Current Drive

ISEG

MIN

TYP

MAX

UNITS

2000

7 Segments Lit

70

180
105

",A
mA

VF = 1.8V
2 Segments Lit

28

42

VF=1.8V
- 20"C
....I

1

8

700

w

a:
a: 500

1/

I

10

800

...z~

IL

7 SEGMENTS LIT

1

12

UJ

r:....

i

14

::E

TA=25°C
DISPLAY OFF

900

/

L
If

1

16

UJ

f"'-..-

TA=25°C
LED FORWARD
VOLTAGE DROP
OF 1.8V AT 15mA

22

w
a:
a:

I I I I I
2 SEGMENTS LIT

1000

26
24

.s...<"
z

SUPPLY CURRENT
. VS.
SUPPLY VOLTAGE

0

3.0

LED SEGMENT VOLTAGE DROP

3.5

4.0

4.5

5.0

2.5

3.5

3.0

4.0

4.5

5.0

SUPPLY VOLTAGE

SUPPLY VOLTAGE

OSCILLATOR STABILITY VS. SUPPLY VOLTAGE FOR 3 DIFFERENT QUARTZ CRYSTALS

z

z

..

o +4.0

~
~Q

;;;

UJ
Q

>

~

~ - 4.0 I'---t---ir-

w
:;:)

~

-8.0

LL

Z

w

'"
S

RS:::::470
Co = 3.3pF

- 8.0

LL -12.0

12.0'----'_......1._--'-_--'-_-'---'
2.0
3.0
4.0
5.0
SUPPLY VOLTAGE

'--r---'---Z-~----"7!

~ + 8.0 f---t---t--,--,---jf-----j

!;i

Z

a:

[

I + 8.0 1----t---=--:':~'------'.r7'''-i

UJ

'"
S

g;

o + 4.0 i--'-------r----,,""""'IO;;!-""'-1

~~~~"~~~ ~~

~

+ 12.0

E

!;i+.

~

,---,r----rr-r--------,

+ 12.0

E + 12.0 ,---,----r-"'TA-=""2""5o"'C.------,
c.
I
f = 3.64089 MHz
~ + 8.0
QUARTZ RS = 330 -~. z
CRYSTAL CO=4.1pF
o 40 PARAMETERS. CM = 18mp"

3.0
4.0
SUPPLY VOLTAGE

2.0

-8.0

a:

'--_ _~_~__
C~M_=._1_0_m_p~F

LL

5.0

-12.0
2.0

TA=25°C
f = 2.184533MHz
QUARTZ
RS = 800
CRYSTAL
Co = 5.1pF
PARAMETERS
CM = 10mpF

ICM7045
10THS

Quartz Crystal Parameters
f = 6.5536 MHz
Rs=400
C1 =15mpF
Co =3.5pF

10QTHS

CI CI CI CI
CI CI CI CI

T'~T

r-r-:c--r-~t++-I+[
p.l-{j,h,~ tw-W
dot
I L-Z>·
~
T-v-

~

+j

J>26§J-i-W

4

NC

I

25

-r--t-i----r-

'-+-----li15

r

c

l.

,

iW-"

CTUNING

~_ ~ BCM7045' ~
iII~D----t+-+---' I D

STAR=T/:::ST=O::tP:~~~~=~~10

J

19

6.5536 MHz"

DISPLAY

NO~R"'M"'AL-L

~E~~~_~TIALr--m
~ r--ill

N.C. ==
y'-'O-"PE::-N-<
N.C. '" NORMALLY CLOSED

NOTE:

RALLY

ID--

-[j]

tTANDARO

I

~

Ill"u-------r~·

ill-----

~T:::O:-P:::VIE:::W:-'

'Cl
~

RESET

Specify quartz crystal to have nominal frequency value
when tuned by a total parallel capacitance value of 12
pF or less.
Figure 1: Four Stopwatch Modes

7·12

3.0
4.0
SUPPLY VOLTAGE

5.0

ICM7045
FUNCTIONAL OPERATION

3. Showing 00 in the two least significant digits.
4. Turning on the display if it was previously turned off

STOPWATCHITIMER OPERATION
The display of just two zeros in the two least significant
digits gives the complete assurance that the stopwatch is
"ready to go".

The control inputs used in the complete stopwatch ap·
plication are: (refer to fig. 1)
START/STOP
DISPLAY

SPLIT
RALLY

RESET
STANDARD

START/STOP and DISPLAY are designed for connection to
single pole double throw switches to insure operation free
of contact bou nce.

STANDARD MODE
In the STANDARD mode, after a reset has taken place,
START/STOP is activated at time to. The clock and display
are moving simultaneously. A second activation of
START/STOP stops the clock and holds the display at time.
ttotal' This completes an event. For timing a second event
there are two options. One is to activate START/STOP at
the start of the second event. This will momentarily reset
the counter and display so that the timing of the second
event proceeds from zero. Another activation of
START/STOP stops the counter and display at time ttotal to
end the second event. The other option is to activate
RESET after the first event is over. Then the second event
proceeeds similarly to the first event. As is clear from this
description, RESET can be used at any time to reset the
stopwatch, including when' a timing is in. progress. The
DISPLAY input can be activated to turn the display off and
on. If the display is off when RESET is activated, it will
reset and turn on. Turning off the display for timing long
events will result in a very substantial power .saving.

The switch connected to RESET can be normally open
single pole single throw. STANDARD, SPLIT and RALLY
are control pOints with internal pull down resistors to
V - .These are designed to be connected to a rotary
function switch which will connect no more than one of
these pOints to Y+. If STANDARD (SPLIT, RALLY) is
connected to Y + the stopwatch is said to be in the
STANDARD (SPLIT, RALLY) mode. If all three are left open,
the stopwatch is in the SEQUENTIAL mode.

RESET FUNCTION
When the stopwatch is turned on, the RESET will normally
be activated. This puts the stopwatch in a ready condition
by:
1. Resetting all circuitry
2. Blanking seconds, minutes, hours

PAUSE

to

to EVENT NO.1 ttotal

i-----r'~1

• i-----r'--I

EVENT NO.2 Itotal

• t-- ....

MANUAL
RESET

START/STOP

START/STOP

t

START/STOP

,

START/STOP

•
RESETS

STARTS
COUNTER

HOLDS
DISPLAY

(AUTOMATICALLY)
MOMENTARILY

HOLDS
DISPLAY

t

COUNTERS

t

BLANKS
6 MOST

DISPLAY
FOLLOWS
COUNTER

t

RESETS COUNTERS

t

STARTS
COUNTERS

SIG~:~:~:NT

,

t

BL.NKS

TURNS ON
DISPLAY

DISPLAY
FOLLOWS
COUNTER

PAUSE

to EVENT NO.1 Itotal

~~I.·
MANUAL
RESET

t

,,

t

RESETS
COUNTERS

'1

START/STOP

START/STOP

START
COUNTER

HOLDS
COUNTER

t

to

,·--f----r---I
MANUAL
RESET

t

,

RESETS
COUNTERS

BLANKS

BLANKS

TURNS ON
DISPLAY

7·13

EVENT NO.2

ttolal

• f-- •.•.

START/STOP

START/STOP

STARTS
COUNTER

HOLDS
COUNTER

t

t

ICM7045
SEQUENTIAL MODE
to the sum of the n times read Clljt:

The sequential mode of the stopwatch is designed for timing events consisting of more than one leg (such as relays,
multilap races, etc.). After the initial reset the START/STOP
is activated at to to start the event. A second activation of
START/STOP at time t, stops the display and allows t, to
be read out, while the clock resets and starts counting
again instantaneously. At time t2 an activation cif
START/STOP enters t2 (the time of leg 2) into the display.
This sequence can continue indefinitely. Assuming the
total event has n legs, the total elapsed time is then equal

If it is desired to see the moving clock after a time has
been recorded, the DISPLAY switch can be activated to
release the display hold and catch up with the moving
clock. The display cannot be turned off in the sequential
mode. RESET can be activated at anytime to reset clock·
and display.
-I

-_~--_ _ _ _

} - - - - - - - - - - EOVENT

~,"US_E~-+-_ _L_EG_N_O_.,_ _tf(_ _L_E_G_NO_._2~o_t~r-<--------I • • • ~NO. n
START/STOP

MANUAL

RE;ET

t

REseT

I

HOLDS

ADVANCES

START/STOP

t

I

ADVANCES

DISPLAY

ANO

ANO

I

I

HOlDS

HOLDS

DISPLAY

DISPLAY

DISPLAY

COUNTER

t

'S
UNINTERRUPTED

fOLLOWS

DISPLAY

START/STOP

STARTS
COUNTER

COUNTERS

BLANK

STAR¥STOP

COUNTER

t

COUNTER

COUNTER

'S

'S

UNINTERRUPTED

UNINTERUPTED

.

lEG NO.2::::t2 -t,

SPLIT MODE
with the total elapsed time from to to t2 showing. Finally, at
time tnthe total elapsed time of the event is entered in the
display. The timeof one leg of the event can be obtained by
subtraction. The display can be synchronized to the
counter (catch-up function) at any time by activating the
display switch. To reset the timer, activate reset. The
display cannot be turned off in the SPLIT mode.

The split mode is another mode for timing multi leg events.
In contrast to the sequential mode, the timing in the split
mode is cumulative. From a reset· condition, the
START/STOP switch is activated at to to start the counter
and display. running. A second activation at t, stops the
display and allows t, to be read out while counter continues timing. A third activation at t2 advances the display

,'"' J'"" .

."-I"-LE-G-NO-.-'-" ,:VENT

.

~~

MANUAL
RESET

.

LEGNO.N

• i----r'r<----Io •

0

0..1..

~'~I

START/STOP

START/STOP

START/STOP

START/STOP

STARTS
COUNTER

HOLDS
DISPLAY

ADVANCES

ADVANCES

1

t

RESETS
COUNTERS

I

I

DISPLAY
FOLLOWS
COUNTER

BLANKS
DISPLAY

t

AND

AND

HOLDS
DISPLAY

HOLDS
DISPLAY

•

RESETS
COUNTER

t

I

RESETS
COUNTERS

STARTS
COUNTER

RESETS
COUNTER

1

I

~ -ARTS
COUNTER

STARTS
COUNTER

RALLY MODE
during long timing intervals. At time t1 a START/STOP
pulse stops counter and display. From here on each leg
time is added to the total by a START/STOP pulse at the
beginning of the leg and at the end. The individual leg
times are determined by subtraction. The display can be
turned on and off with the display switch.

The rally mode is designed for timing of events with interruptions. Consider an n leg event where the legs may be
separated by intervals which should not be timed. The rally
mode starts with a RESET. At time to the stopwatch is
started by activating START/STOP. After this point the
RESET function is disabled to prevent accidental resets

'.

-----EVENT

I

.,

p~~~~__ ___

r---r~

1 MANUAL

lEG NO.1

I

I,

PA~~I

,------.-~.

---------~O_II
t

LEG NO.2

.12

t
PAUSE·2

, r--r---I o

START/STOP

START/STOP

START/STOP

START/STOP

START/STOP

t

STARTS
COUNTER

COUNTER

COUNTER
CONTINUES

COUNTER
HOLDS

COUNTER
CONTINUES

t

F~~~~~S

BLANK
DISP

COUNTER

RESET
ONLY

C~~S~~;R

Itotol (EVENT) '" In

t
t

'.1

~IOLDS

t

H~~:;S

t

t

~~~r~::s
COUNTER

t

t

D~~~~Y

t

t

DISPLAY
FOLLOWS
COUNTER

LEG NO.n=tn-In+l

LEG NO.,1 '" 11 - 10

7-14

C~NO.
0 0,---.-

"

~
START/STOP

t

COUNTER
HOLDS

I

DISP
HOLDS

ICM7045
CLOCK OPERATION
The control inputs used in a possible 24·hour clock (ton·
figuration are (refer to fig. 2):

1.

If clock is not running when power is applied
activate START/STOP switch.
2. Depress MINUTES ADVANCE switch to obtain
correct minutes setting, one minute count per
activation.
3. Depress HOURS ADVANCE switch to obtain correct
HOURS setting, one hour count per activation ..
It is possible to set the clock more accurately or to correct
small time errors by using START/STOP in combination
with MINUTES ADVANCE. If the clock is, for instance, 20
seconds slow, activate the MINUTES ADVANCE once, then
activate the START/STOP, wait 40 seconds and activate
the START/STOP again. If the clock is 20 seconds fast, the
START/STOP switch should be activated to stop the clock,
then after 20 seconds activated again to restart the clock.
Other clock configurations are possible (see Application
Notes).

START/STOP
MINUTES ADVANCE
HOURS ADVANCE
RALLY
START/STOP,
MINUTES
ADVANCE
and
HOURS
ADVANCE are designed for connection to single pole
double throw switches; this assures contact bounce
elimination on these inputs. To avoid an additional switch
for the DISPLAY input, the RALLY input should be
connected to V+ through a 20k resistor and to V- through
a O.011'F capacitor. These components insure that the
display is on when power is applied to the circuit. The most
convenient setting procedure is:

H10

8

H1

S10

M1

M10

S1

8

'l7"lb l-I l-I I-I I-I I-I
°l7"'/c
l ...7 l-I II II l-'
,g
II
b

c
,---0

,---d

rTl 'Tl

,.-f

~
k-

12:~~ J
~
~

L.--{I

POWER
SUPPLY

~

.J

'T

~

-fS

$

7lJ--

r;;-

L.r

HOURS
ADVANCE

r;ICM7045

r;;~

U
20 k

START/STOP

!J
20

~
r;;-

~N.C.

:ill

~

IN.C.

MINUTES!
ADVANCE
CTUN1NG

-J9

S.553SMHz

JE
:IT!-

[iI

~
~

OI
14

TOP VIEW

N.C. = NORMALLY CLOSED

Figure 2: Clock Mode

APPLICATION NOTES
The ICM7045 have been designed with versatility of ap·
plications in the digital timer/stopwatch/24·hour clock field
as the major objective. The simplicity of operating modes
allow for an extremely practical, easy to use stopwatch, at

the same time permit the design of a variety of Simple
lapse timer, stopwatch and clock circuits; a few of these
will be shown and discussed briefly here.

7·15

ICM7045
TIMER CIRCUIT I

TIMER CIRCUIT III

This simple circuit (display connections not shown) allows
interval timing up to 24 hours with a resolution of 0.01
second. I;ach interval is timed by one start and one stop
pulse on the start/stop line. The start pulse for the next
interval to be timed automatically resets the timer.
Leading zero suppression is automatic.

This circuit allows interval timing with a single pulse on
the start/stop line. Each pulse enters the time elapsed
since the previous pulse into the display, resets the timer
and starts the timer for the next interval.

v+ o-------+-~1J
v+G-------~----DJ

TOP VIEW

TOP VIEW

g

CLOCK CIRCUIT I
The standard clock circuit is shown and described in fig. 2.
The clock accuracy with a stable voltage supply will depend mostly on the temperature and aging characteristics
of the crystal.

TIMER CIRCUIT II

The power supply can be modified to give battery standby
power.

This circuit allows cumulative timing of intervals. Each interval is timed by one start and one stop pulse on the
start/stop line. Each subsequent interval timed adds to the
total line displayed. The reset switch allows the timer to be
reset to zero to start another sequence of intervals. Note
that the time between the end of one interval and the start
of the reset is not recorded nor added to the total.

V~P>-------I-----"" TO v+

=

3.6V

1
v+ 0-------+--1

The standby circuit should be designed to provide the
specified minimum voltage to the ICM7045.

OTHER CLOCK CIRCUITS
The basic clock circuit can be modified for various special
applications. If it is desired to turn the display on and off,
then connect the display input to an additional SPDT
switch, while omitting the capacitor/resistor combination
on the STANDARD Input.
This input can then be wired directly to V+. This 24-hour
clock version might be applicable to vehicles, boats, etc.
where a battery is available. to supply the display off clock
current, while the display can be turned on with the ignition. Another possible configuration would connect a
special circuit to the DISPLAY input which generates a
double pulse about 3 seconds apart:

N.O.
1161_--<_~ RESET

1
7-16

ICM7045
V'

100k

TO DISPLAY INPUT

This means depressing the switch will turn on the clock's
display for 3 seconds. This allows design of a battery
operated "on demand" digital 24-clock.

STOPWATCH EXTERNAL SYNC CIRCUIT
If the stopwatch is connected as shown in fig.1, a few additional components will allow external synchronization of
the stopwatch in any mode:

v+

10k
ICM70451A
PIN 9

2.2k

V,N

2.2k

I
I

- - - - - - - - - - - - - - - _ .....

NOTE:

Be sure to minimize the distance between the transistor
and the ICM7045 to prevent noise from being generated
along this connection. Noise spikes absolutely must not
exceed the supply voltages.

The external sync signal source must supply a positive
pulse to activate the START/STOP input. The minimum
voltage of this pulse is about 1.2V in the circuit as shown,
but the triggering level can be changed by modifying the
input resistor ratio. The output impedance of the external
sync signal source should be no greater than 4k ohms.

7-17

ICM7045
OSCILLATOR CONSIDERATIONS
The oscillator is a high gain complementary MOS inverter
with on-chip feedba,ck resistors and an on-chip fixed input
capacitor of 22pF. For the 6.5536 MHz crystal needed for
normal timing using the ICM7045, it is suggested that the
nominal load capacitance be kept under 12pF to keep total
loading on the oscillator to a reasonable level. The actual
trimmer range and the nominal l.cad capacitance needed
will have to be determined from the total stray capacitance
of the particular circuit (including ICM7045 with package,
PC board, etc.) and the tuning tolerance of the chosen
crystal.
The series resistance of the crystal should also be kept to
a low value (typically less than 50 ohms) to achieve
adequate low voltage operation.
Oscillator tune up can be most easily performed using a
pull-up resistor of 10k ohms on the fractional seconds
digit, using period average tune for 1.25ms (800Hz).

CHIP TOPOGRAPHY
CATH 8

ADV

7-18

ICM7050
ICM1115
Quartz Clock Circuits
Bipolar Stepper Motor Applications
FEATURES
•
•
•
•

Single battery operation
Very low current - typically 40llA at 4.19MHz
Reset or stop function, inhibited during output
Extremely low output saturation resistance:
less than 100 ohms
• Complex direct drive alarm: 1Hz + 8Hz + 2048Hz
• Custom options available

ORDERING INFORMATION
DEVICE
MOTOR OUTPUT
ICM7050
47ms@0.5 Hz
ICM1115

0.5 Hz Square Wave

ALARM OUTPUT
Complex
64 Hz Tone

Note: These devices require a crystal frequency of 4.19 MHz.
Consult ICM7070 data sheet for 32.768 kHz devices.

'See PART NUMBER CHANGES below.

BLOCK DIAGRAM'

GENERAL DESCRIPTION
The ICM7050/lCM1115 are single battery analog quartz
clock circuits intended for use with bipolar stepper
motors and fabricated using Intersil's low voltage metal
gate CMOS process. The circuits consist of a divider
chain, output gating, output buffers and an oscillator
which, when using the specified 4.19MHz crystal and
capacitors, provides excellent stability. The high frequency portion of the divider chain consists of dynamic
dividers, while the remainder are static. The dynamic
dividers feature low power consumption and operating
voltage, but limit low frequency operation. The 223
divider chain is tapped at the 211, 2 19, and 222 points to
provide a complex alarm of 1Hz, 8Hz, and 2048Hz driving an output inverter. Several standard motor drive
waveforms are available, and the lar!:je output inverters
provide the low impedance necessary to drive the
motor. A reset inhibit function is provided so that if the
RESET occurs during an output pulse, resetting will not
take place until the pulse is completed. RESET may also
be used as a stop for synchronization to a time signal or
tester. Motor drive will continue 1 sec. after RESET is
released.
PIN CONFIGURATION (outline dwg PA)

TOP VIEW
ALARM
OUT
2

6 f--++---«~--r
COMPLEX
ALARM
LOGIC

Hz

ORDERING INFORMATION
ICM7070

PA

216

OUT
1

v+mr
v~~

2048

T

'LI- - - -

L -_ _ _ _ _ _

1Hz

8Hz

M~~~~Y 1-----,,22:.:.3-1

:::k~~:.ine Drawing
Temperature Range:

Industrial-20°C to '-70 c e

LI_ _ _ _ _ _ _ _ _ _ Type

LOGIC

Order Oevices by Following Part Number -

CUSTOM OPTIONS
The ICM7050 input and output configurations may be customized for:
•
•

On-chip oscillator capacitance up to 20 pF at OSC IN or OSC OUT
Output pulse frequency from 0.5 Hz to 64 Hz I standard crystal
freq.,

• Output pulse width from 0.98 msec to 50% duty cycle
• Alarm output up to three binary frequencies from 1 Hz to 2048 Hz
Consult factory for mask programming charge and minimum order
requirements.

7·19

ICM70S0lPA
ICM1115AIPA
ICM1115BIPA

IC.M7050nCM 1115
ABSOLUTE MAXIMUM RATINGS
Power Dissipation Output Short Circuit (Note 1) ......................... 300mW
Supply Voltage ............................................................. 3V
Output Voltage (Note 2) ................ ,.................... Equal to but never
Input Voltage (Note~) ............................. exceeding the supply voltage
Storage Temperature ......................................... -30°C to +125°C
Operating Temperature .........• , ............................. -20°C to +70°C
Lead Temperature (soldering, lOs) ..•.•.................................. 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions above those indicated i,n the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

NOTE 1: This value of power dissipation' refers to that of the package and will not normally be obtained under normal operating conditions.
NOTE 2: Due to the inherent SCR structure of junction isolated CMOS devices, the circuit can be put in a latchup mode if large currents are
injected into device inputs or outputs. For this reason special care should be taken in a system with multiple power supplies to prevent
voltages being applied to inputs and/or outputs before power is applied. If only inputs are affected, latchup can also be prevented by
limiting the current into the input terminal to less ihan 1mA.

ELECTRICAL CHARACTERISTICS
(V+ = 1.5V, fosc = 4,194,304Hz test circuit, TA = 25°C, unless otherwise specified)
PARAMETER
Supply Current(Note 3) except ICM1115A

SYMBOL
1+

ICM1115A Only
Operating Voltage

V+

Total Output Saturation Resistance

ROUT

Alarm Saturation Resistance

RAL(on)

CONDITIONS

MIN

No Load
-20°C < TA < 70°C
IL

P,IL=1mA

Oscillator Stability

fstab

Oscillator Start-up Time

tstart

V+ = 1.2V

Oscillator Transconductance (Note 3)

gm

MAX

UNITS

40

p.A

80

60
120
1.8

V

70

100

400
100'

700

n
n
n

1.2

= 4mA

N, IL = 2mA
1.2 :S V+ :S 1.6

TYP

400

ppm

1
1.0
75
150
75

ICM7050
ICM1115A
. ICMll15B

200
400
200

sec
p.mho

Two options are available with the ICM1115. The ICM1115B is designed to be used with crystals whose load capacitance is 12 pF or less.
Using input and output capacitors of 15 to 20 pF, this device will provide stable operation at very low supply current. For applications with
larger load capacitance (15 to 20 pFI, the ICM1115A ensures that an increased oscillator current is available to guarantee startup and
operation over the voltage range. Using input and output capacitors of 30 to 40 pF, the ICM1115A will offer good stability at a supply
current approximately twice, that of the 19M1115B.

TYPICAL APPLICATION (also TEST CIRCUIT)
CLOCK CIRCUIT

~v~----~vC'f11f'.~~---1I~----~

15pF

15pF

1.5V -L
lCM7050
ICM1115

TO
ALARM

t---------~~r-~---TRANSDUCER

i
L.

v· "~>---+---I
RESET/STOP
Quartz: Crystal Parameters

(Iort.st

I - 4.194.304 Hz
Rs =- 45 ohms
CIN =:= 10mpF
COUl "" 4pF

only)
MOTOR

OR'

DRIVER
Notes:
RESET/STOP' If pin 4 is not
used, it should be tied to V-.

OUTPUT FREQUENCIES Crystal frequencies from 1 to 10 MHz
may be used to obtain different
output frequencies. See Oscilla-

(75!! for test "I)

tor Considerations for suita'ble
crystal parameters

7·20

ICM7050llCM1115
TYPICAL OPERATION CHARACTERISTICS

OSCILLATOR STABILITY vs. SUPPLY VOLTAGE

SUPPLY CURRENT vs SUPPLY VOLTAGE
140~--r---~--~---r--~--~----'

Crystal Parameters
Per "Clock Circuit" _'

1201--1--

C,nlCoot ~ 10PF I 3 Y
30pFll0pF

f..--

./'" V

lJ P FI15PF

/

30pFll0pF

~ [---

~.~2--~--~--~1.~5--~--~--~~~

1.2

1.5
SUPPLY VOLTAGE

SUPPL Y VOLTAGE

1.8

ALARM OUTPUT CURRENT vs SATURATION VOLTAGE

OUTPUT CURRENT vs OUTPUT LOAD VOLTAGE

P CHANNEL SATURATION VOLTAGE

1.5

I

1.5

1.0

N CHANNEL SATURATION VOLTAGE

OUTPUT LOAD VOLTAGE

OUTPUT WAVEFORMS (ICM7050)
RESET DURING OUTPUT PULSE*

NORMAL OPERATION

_I C

OUT1U

t

2 se;:.c=====:!.I
___._.

!

OUT 2

OUT1LJ"1

1_ _ 1 sec

-U

OUT 2

:1

U

1.1

I

ALARM

RESET

n • 47 msec for ICM7050

~ ~l_s_._c==~___I,--____

.'II~WDI

ALARM

I~~m

OUTPUT WAVEFORMS (ICM1115)
NORMAL OPERATION

OUT 1
OUT 2
ALARM

"I

_J

I

2 sec
1 sec

DIW~

~I

~OO~~

RESET*

~

OUTl

I

r-

OUT 2

---.I !

~nl

RESET
ALARM

"Shown during OUTput 1; exchange OUTput 1 and OUTput 2 for opposite case.

7-21

I

~~I----------~
~I

,-- --I
1 sec

I~~I

.O~OlL

·ICM'7050IlCM 1115
APPLICATION NOTES

OSCILLATOR TUNING METHODS

OSCILLATOR CONSIDERATIONS

When tuning the oscillator two methods can be used. The first
method would be to monitor the output pulse at either OUT 1
or OUT2 with a counter set to measure the period. The
oscillator trimmer would then be adjusted for a reading of
2.000000 sees. A second method would be to put the device in
the reset, mode by pulling the RESET pin to V+ and then
monitor the ALARM output with a counter set to measure
average period. The ALARM output is a continuous 2048Hz
when in the reset mode, which gives a period of 488.28125/ls.

The oscillator of the ICM7050 has been designed to operate
with crystals having a load capacitance of 10 to 12pF. This
allows nominal capacitor values of 15/15pF or 20/20pF.
Increasing the load capacitance of the crystal requires larger
oscillator device sizes, which causes the supply current to
increase. Modifications to the oscillator can be made on a
custom basis. The tuning range can be increased by using
crystals with lower load capacitances, however the stability
may decrease somewhat. This can be counteracted by
reducing the motional capacitance of the crystal. A nonlinear feedback resistor having a maximum value at start
up is provided on chip. Oscillator tuning should be done at
the OSCillator OUTput.
The following expressions can be used to arrive at a crystal
specification:
Tuning Range
~f

Cm

f

21Co + Cl)

Cl

=

+

g~) 2

The trimmer capacitor used for tuning should be connected
to the OSCillator OUTput. Otherwise, if tuned at the input,the
stability will vary with tuning, and the current drain may
become excessive when the input capacitance is much less
than the output capacitance. Refer to the Supply Current vs.
Supply Voltage and Oscillator Stability vs. Supply Voltage
characteristic curves on the preceding page.

TEST MODE OPERATION
Pulling the RESET/TEST input to -7V switches thedevice into
the test mode to speedup automatic testing. When in the test
mode the output rate is increased 16 times, from 1Hz to 16Hz,
with a corresponding reduction in pulse width. The ALARM
output changes to a composite waveform of 16Hz and 128Hz.
The circuit can be reset while in the test mode by shorting the
ALARM output to V-.

CinCout
Cin + Cout

gm required for startup
gm =

002

CmCoutRs

(1

Rs = series resistance of the crystal
f = frequency of the crystal
~f = frequency shift from series resonance frequency
Co = static capacitance of the crystal
Cin = input capacitance
Cout = output capacHancp
Cm = motional capacitance
w = 21Tf
The resulting gm should not exceed 50/lmhos.

ALARM CONSIDERATIONS
The ALARM output inverter is large enough to directly drive
transducers requiring up to 2mA of current. If more current is
needed, a PNP buffer should be used'. A slight flutuation in the
supply current of O.5/lA to 1.0/lA will be seen; this is a result of
2048Hz driving the relatively large gate cjlpacitance of the
alarm output transistors.
'See Intersil Application Bulletin A031 for details.

1iiI--------------------~------------C-H-I-P-T-O~P-O-G-R-A-P-H-Y-----------------OUT2

.068 In .
.173mm

v+~_

_----.;~36~n.;, ____.1

7·22

RESET

TEST

ICM7051

CMOS Auto
Clock Circuit
FEATURES
• Wide operating supply voltage and temperature
ranges
• Excellent oscillator stability
• Short circuit protected bridge output with low ON
resistance
• Oscillator feedback resistor on-chip
• All inputs fully protected
• Nominal 12.6 volt zener on chip
• 64Hz output for synchronous motor applications
(ICM7051A)
• 1 Hz output with 31.2 ms output pulse width for
stepper motor applications (ICM7051B)
• Typical power dissipation < 4 mW at 12 volts

GENERAL DESCRIPTION
The ICM7051 AlB is an auto clock circuit fabricated
using Intersil's standard metal gate CMOS process.

Included on-chip are the oscillator, dividers, output
drivers and over-voltage protection circuitry. The oscillator of the ICM7051A/B has the feedback component
on-chip, and when used with the specified crystal
parameters will give excellent stability. The binary dividers of the ICM7051 allow division from 4.19MHz and
drive a bridge output which provides an alternating
31.2ms output pulse at 1Hz for the ICM7051 B (O.5Hz
each side) or a 64Hz square wave output for the
ICM7051A. The bridge output consists of two large
inverters with the output ON resistance of the Nand P
channel devices together being less than 100 ohms with
VBATT equal to 13.5 volts and load current equal to
10mA.
The ICM7051 series contains an on-chip zener which,
when used with an external resistor and capacitor, will
provide protection against over-voltage transients that
may occur in an automobile environment.

SCHEMATIC DIAGRAM

7

v-

PIN CONFIGURATION (outline dwg PAl

ORDERING INFORMATION
ICM7051A
ICM7051B

TT
I

PA

"c"ce
PA= 8 PIN

MINI DIP

TEMPERATURE RANGE
-20' C to +85' C
' - - - - - - - - TYPE
Order dice by following part numbers: ICM7501A/D, ICM7051 BID
Note: The ICM7051A was formerly known as ITS 9042-1.

" ICM7051
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VSATT, •..•.••. -12 to +25V (Note 1)
see TEST CIRCUIT) ................ -0.5 to +13.5V
Output Voltage and T.P. Input ........ Not to exceed
supply voltage
Storage Temperature ............. -40°C to +125°C
Operating Temperature ............ -20°C to +85°C
Lead Temperature (Soldering, 10 sec) ........ 300°C
Power Dissipation (Note 2) ................ 0.5 Watt
Latch up holding current (Note 3) ... .. .. ... 100mA

Stresses above those listed under "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect devic~ reliability.

Note 1: Stress duration not to exceed 2 min.
Note 2: This value of power dissipation refers to that of the package and will not be nOrmally obtained under normal operating condiUons.
Note 3: A destructive latch up mode is possible if an input or output is forward biased with respect to either the positive or negative supplies. The
ICM7051 has an absolute maximum latch up holding current of 100mA. This means the device, when operated at ambient temperature, will
return to its normal operating state after an inadvertant input transient, if the supply cutrent is limited to less than the absolute maximum
latch up holding current of the device.
.

OPERATING CHARACTERISTICS
VBATT = 13.5V, TA = 25°C, fosc = 4.194304MHz, Rl= 1.2 kn, unless otherwise specified
LIMITS
PARAMETER

SYMBOL
1+

Supply Current

TEST CONDITIONS
No Load

l

VBATT

Output Resistance (n+p)

ROUT

Zener Voltage

Vz

TA - 25°C

4.5

-20°C S TA S +85°C

7.0

UNIT
mA

>3.5

7
1
22

17

10 = 10mA

100

V+-SV, la-SmA

130
11

Iz=5mA

fSTAB

6VS V+S Vz

Oscillator Start Up Time

tSTART

6VS V+S Vz

Output Leakage Current

10lK
gm

MAX.

V+ = 7.0V

OSCillator Stability

Oscillator Transconductance

TYP,

VBATT - 13.5V

I

Supply Voltage Range (Note 4)

MIN.

All Outputs
V+:O::6.0V
25

n

14

V

2

ppm

1

sec

100

IlA

250

V+,:o:: 3.0V

V

Ilmho

100

Note 4: In Test Circuit only. V+ should not exceed vz.

TEST CIRCUIT

TYPICAL AUTO CLOCK

TRIM

Quartz Crystal Parameters

Rs

:0

lOon

em'" 0.012 pF
Co = 5 pF
f ::: 4.194,304 Hz

1-1

1'1
V'

300n

o-'V\f\r"--12..l
30GI!

1.2kn

MOTOR

7-24

ICM7051
TYPICAL OPERATING CHARACTERISTICS
Output Current as

Supply Current as
a Function of Supply Voltage

a Function of Load Voltage

30

300

TA
~ 25

~

3

250

i'-.

~ 20
~

~

1"'-

G 15

II

200

1

VSATT '" 13.SV

'\
I\.

~

co

010

II

150

'\.

~

co

I----

V

TA" 25 C

t"--r-.,

~

V

25 C

/

100

I

TEST
"CIRCUIT

I

I

\
10

/

50

I
4
6
8
SUPPLY VOLTAGE V+

12

LOAD VOLTAGE

Oscillator Stability as
a Function of Supply Voltage

10

12

Zener Voltage as
a Function of Temperature
13.2

+1.0

TA'" 25 C

IZ'" SmA

13.0

V

12.8

/
/
~

,/

Cin = c~r

~

IPF I - -

12.6

'/

c~~0T- l -

-1.0

10

12

14

16

,./

12.4

..,.

..,. ..,.V

V
,/

I

e-12.2

18

20

40

60

80

100

TEMPERA:rURE C

SUPPl Y VOL TAGE

OUTPUT WAVEFORMS
ICM7051A

The ICM7051 uses a TEST point to facilitate testing.
This pin has an on-chip pulldown resistor, and for normal operation is at V-. Connecting this pin to V+ will
give a 32 times speed-up of the outputs.

OUT'LJLF

1-~ Hz_I
OUT2~

50% DUTY CYCLE

CUSTOM VERSIONS
The ICM7051 may be modified with alternative metal
masks to provide a different number of dividers, various
pulse widths, increased oscillator transistors or optional
V zener pad for use with an external zener diode. The
ICM7051 can be adapted for use with different synchronous motors as well as a variety of stepping motors.
Consult factory for details.

OUT 1

OUT 2 - - - - - - - - - - - - - - - ,

Lf
7-25

ICM7051
APPLICATION NOTES
OSCILLATOR CONSIDERATIONS
The oscillator of the ICM7051 has been designed to operate
with crystals having a load capacitance of 10 to 12pF. This
allows nominal capacitor values of 15/15pF or 20/20pF.
Increasing the load capacitance of the crystal requires larger
oscillator device sizes, which causes the supply current to
increase. Modifications to the oscillator can be made on a
custom basis. The tuning range can be increased by using
crystals with lower load capacitances, however the stability
may decrease somewhat. This can be counteracted by
reducing the motional capacitance of the crystal. A nonlinear feedback resistor having a maximum value at start
up is provided on chip.

The follwing expressions can be used to arrive at a crystal
specification:
Tuning Range
~f

f

CinCout'
Cin

+ Cout

Rs = series resistance of the crystal
f = frequency of the crystal
.~f =, frequency shift from series resonance frequency
Co = static capacitance of the crystal
Cin = input capacitance
Cout = output capacitance
Cm = motional capacitance
w = 21Tf

To tune the oscillator, the best method is to monitor the
output pulse at either OUT1 or OUT2 with a counter set to
measure the period. The oscillator trimmer is then adjusted for
a reading of 15.625 msec for the ICM7051A, or 2.0000 secs for
the ICM7051 B. Note that different output frequencies can be
obtained by varying the crystal frequency over a range of
1 to 10MHz. In particular, a 60Hz output will result if a
3.93216MHz crystal is used with the ICM7051A.

The resulting gm should not exceed about 1/2 the value
of the oscillator at the relevant supply voltage.

CHIP TYPOGRAPHY

1--------·1~O~~---------.j
OUTl

OSCIN

TEST

+ CII

gm required for startup

The trimmer capacitor used for tuning should be connected
to the OSCillator OUTput. Otherwise, if tuned at the input, the
stability will vary with tuning, and the current drain may
become excessive when the input capacitance is much less
than the output capacitance. Refer to the Supply Current vs.
Supply Voltage and Oscillator Stability vs. Supply Voltage
characteristic curves on the preceding page.

OUT2

Cm
2(Co

v-

7·26

.D~DIl

ICM7070L
Quartz Clock Circuits
Bipolar Stepper
Motor Applications
GENERAL DESCRIPTION

FEATURES
• Single battery operation
• Very low curr.ent - typically 3 /lA
• Reset or stop function, inhibited during output
• Extremely low output saturation resistance: less than
100 ohms
• Complex direct drive alarm: 1Hz + 8Hz + 2048Hz
• On chip oscillator input capacitor
• Custom options available
DEVICE

MOTOR OUTPUT

ICM7070L

31ms@0.5 Hz

The ICM7070 is a single battery analog quartz clock
circuits intended for use with bipolar stepper motors
and fabricated using Intersil's low voltage metal gate
CMOS process. The circuit consists of a divider chain,
control gating, output buffers and an oscillator which,
when using the specified 32 kHz crystal and capacitors,
will provide excellent stability. The 2 15 divider chain is
tapped at the 2 15, 2 12, and 24 points to provide a complex alarm of 1 Hz, 8Hz, and 2048Hz driving an output
inverter. Several standard motor drive waveforms are
available, and the large output inverters provide the low
impedance necessary to drive me motor. A reset inhibit
function is provided so that if the RESET occurs during
a (non-square wave) output pulse, resetting will not take
place until the pulse is completed. RESET may also be
used as a stop for synchronization to a time signal or
tester. Output will begin 1 sec. after RESET goes low
again, and in the correct sequence.

Note: These devices require a crystal frequency of 32.768 kHz. Consult
ICM7050 family data sheet for 4.19 MHz devices.

PIN CONFIGURATION (outline dwg PA)

BLOCK DIAGRAM
OSC f t B U F F E R
IN

+24

g~~

RES~~~EST

TEST

I~~~:~

RESET

RESET/STO~
TEST

ALARM

rv+

7 T
,--

41--+-+---1

SPEEDUpL
GATE I

~

y+
Y-

LOGIC

OUT 1

IT ~ :!I OSC IN
IT ICM7070 21 OSC OUT
[I

)]

ALARM

14

51

OUT 2

RESET ISTOP
TEST
L.:.

m-[i6iJ---+--l---o(~::1----{
___""'"
.
COM~LEX

..::J
TO~

ALARM
LOGIC

YIEW

OUT
1

Y+l
Y- 2

ORDERING INFORMATION

8Hz
......."'-......

1Hz

. RESET
MEMORY 1 - - - - \
LOGIC

1~~O~'1
T

CUSTOM OPTIONS

Temperature Range:
Industrial-20°C to +70°C

The ICM7070 input and output configurations may be customized
for:
• On-chip oscillator capacitance up to 20pF at OSC IN orOSC
OUT
• Output pulse frequency from 0.5 Hz to 64 Hz (standard crystal
freq.1
• Output pulse width from 0.98 ms to 50% duty cycle
• Alarm output up to three binary frequencies from 1 Hz to 2048 Hz
Consult factory for mask programming charge and minimum order

Option
'-------------Type

requirements.

7-27

Package
See Outline Drawing

,

ICM7070L
ABSOLUTE MAXIMUM RATINGS
Power Dissipation Output Short Circuit (Note 1) ......................... 300mW
Supply VOltage ............................................................. 3V
Output Voltage (Note 2) ..................................... Equal to' but never
Input Voltage (Note 2) ............................. exceeding the supply voltage
Storage Temperature ......................................... -30° C to +125° C
Operating Temperature ........................................ -20°C to +70°C
Lead Temperature (soldering. 10s) ....................................... 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only. and
functional operation of the' device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditipns for .extended periods may affect device reliability.
NOTE 1: This value of power'dissipation refers to that of the package and will not normally be obtained under normal operating conditions.
NOTE 2: Due to the inherent SCRstructure of junction isolated CMOS devices, the circuit can be put in a latchup mode if large currents are
inj~cted into device inputs or outputs. For this reason special care should be taken in a system with multiple power supplies to prevent
voltages being applied to inputs and/or outputs before power is applied. If only inputs are affected. latchup can also be prevented by
limiting the current into the input terminal to less than 1mAo
.

ELECTRICAL CHARACTERISTICS
(V+ = 1.5V. fose = 32.768 Hz test circuit. TA = 25°C, unless otherwise specified)
PARAMETER
Supply Current
Operating Voltage
Total Output Saturation Resistance
Alarm Saturation Resistance

SYMBOL
1+
V+
ROUT
RAL(on)

,
Oscillator Stability
Oscillator Start-up Time
Oscillator Input Capacitance

Istab
tstart
CIN
gm

Oscillator Transconductance

CONDITIONS
No Load
-20° C < TA < + 70° C
IL = 4mA
P.IL=1mA
N, IL = 2mA
1.25 V+ 5,1.6
V+ = 1.2V

MIN

TYP
3

1.2
70
400
100
1
16
2

20
7

MAX
6
1.8
100
700
400
1.0
24

TYPICAL APPLICATION
CLOCK CIRCUIT

NOTES:
1.5V

1-----..--- ALARM
v+~r--4-~
RESET/STOP

Quartz Crystal Parameters
f 32,768 Hz
R s 20K ohms
0:..

CIN"" 10mpF
Caul"" 4pF

MOTOR

, 7-28

RESET/STOP; If pin 4 is not used, it
should be tied to vOUTPUT FREQUENCIES: Crystal
frequencies from 20 to 100 kHz may be
used to obtain different output
frequencies. See Oscillator
Considerations for suitable crystal
parameters.

UNITS
jJA
V

n
n

n
ppm
sec
pF
I'mho

ICM7070L
TYPICAL OPERATION CHARACTERISTICS
OSCILLATOR STABILITY vs. SUPPLY VOLTAGE

SUPPLY CURRENT vs SUPPLY VOLTAGE
4.5

r--,.--...,...-....,..---,--r--,.--"

'4r--,.---,--r--,--r--,.--,
COUT '"

CRYSTAL PARAMETERS
PER "CLOCK CIRCUIT"

10 pF

4.0

<'
.3
>-

~

3.5

3.0

a:

:>

()

~
~

,.0,L.2-....I.-....J--,~.5~....J--'---,.L..B---'
SUPPL y VOLT AGE

SUPPL y VOLT AGE

ALARM OUTPUT CURRENT vs SATURATION VOLTAGE

OUTPUT CURRENT vs OUTPUT LOAD VOLTAGE

P CHANNEL SATURATION VOLTAGE
1.5

30

!

~

..........

"'" "'"

I

:S.~ =1 ,8V
"-. v+ =1.5V"-

i'-.

...........

'\

- ""

+ =1.2V

"'"

.......

o
o

~

1.0

'\.
"\

\ \
1.5

1.0

1.5

N CHANNEL SATURATION VOLTAGE

OUTPUT LOAD VOLTAGE

OUTPUT WAVEFORMS (ICM7070L)
RESET DURING OUTPUT PULSE'

NORMAL OPERATION
OUT 1
OUT 2

--, I

J-I

_I

G . 2 S msec (L)

2 se,~c====::::::ll
__44~77msec (P)
1sec_U

OUT1L!'1
I

,

1-·

OUT2

ALARM

RESET

ALARM

7-29'

11
. -1---------,

U
Ii--' .ec--_I
I

.lllIm~UU

~W~I

ICM7070L
APPLICATION NOTES

OSCILLATOR TUNING METHODS

OSCILLATOR CONSIDERATIONS

When tuning the oscillator two methods can be used. The
first method would be to monitor the output pulse at either
OUT 1 or OUT 2 with a counter set to measure the period.
The oscillator trimmer would then be adjusted for a reading
of 2.000000 secs. A second method would be to put the
device in the reset mode by pulling the RESET pin to V jand then monitor the ALARM output with a counter set to
measure average p'eriOd. The ALARM output is a continuous
2048Hz when in the reset mode, which gives a period of
488.28125J.'s.

The oscillator of the ICM7070 has been designed to operate
with crystals having a load capacitance of 10 to 12pF. This
allows nominal capacitor values of 15pF or 20pF. Increasing
the load capacitance of the crystal requires larger oscillator
device sizes, which causes the supply current to increase.
Modifications to the oscillator can be made on a custom basis.
The tuning range can be increased by using crystals with
lower load capacitances, however the stability may decrease
somewhat. This can be counteracted by reducing the motional
capacitance of the crystal. A non-linear feedback resistor
having a maximum value at start up is provided on chip.
Oscillator tuning should be done at the oscillator output.
The following expressions can be used to arrive at a crystal
specification:
Tuning Range

M

f

Cm
= 21C o + Cl)

Cl =

CinCout
Cin + Cout

gm required for startup
gm =

w2

CinCoutRs

(1

+

~)2

Rs = series resistance of the crystal
f = frequency of the crystal
.
~f = frequency shift from series resonance frequency
Co = static capacitance of the crystal
Cin = input capacitance
Cout = output capacitance
em = motional capacitance
w = 2rrf
The resulting gm should not exceed 20 J.'mhos.

The trimmer capacitor used for tuning should be connected
to the OSCillator OUTput. Otherwise, if turied at the input,
the stability will vary with tuning, and the current drain may
become excessive when the input capacitance is much less
than the output capacitance. Refer to the Supply Current vs.
the Supply Voltage and Oscillator Stability vs. Supply
Voltage characteristic curves on the preceding page.

TEST MODE OPERATION
Pulling the RESETITEST input to -7V switches the device into
the lesl mode to speed up automatic testing. When in the lest
mode the output rate is increased 4 times, from 0.5Hz to 2Hz,
with a corresponding reduction in pulse width. The ALARM
output changes to a composite waveform of 4Hz and 32Hz.
The circuit can be reset while in the lesl mode by shorting the
ALARM output to V-.

ALARM CONSIDERATIONS
The ALARM output inverter is large enough to directly drive
transducers requiring up to 2mA of current. If more current is
needed, a PNP buffer should be used'. A slight fluctuation in
the supply current of 0.5J.'A to 1.0J.'A will be seen; this is a result
of the 2048Hz drive to the relatively large gate capacitance of
• the alarm output transistors.

IiiiII ____________________~__________________________·~S~e~e~ln~te~r~si_IA~p~p~li~ca~t~io_n_B~u-"-ffi-in-A-o-3-1-fo-r~d~e-ta-ils-.----------~CHIP TOPOGRAPHY

ICM7206
CMOS Touch
TonEfEncoder
-3dBV into a 900 ohm termination. The skew between the
high and low groups is typically 2.5 dB without low pass
filtering.

FEATURES
• L.ow cost system with minimum component count
• Fully integrated oscillator uses 3.S8 MHz color TV
crystal
• High current bipolar output driver
• Low output harmonic distortion
• Wide operating supply voltage range: 3 to 6 volts
• Uses inexpensive single contact per key
calculator type keyboard (ICM7206/C/D)
• Extremely low power -S S.SmW with a S.SV supply
• Single and dual tone capabilities
• Multiple key lockout
• Disable output: provides output switch function
whenever a key is pressed
• Custom options available

The 7206 uses either a 3 x 4 or 4 x 4 single contact keyboard;
the oscillator will run whenever the power is applied, and the
DISABLE output consists of a p-channel open drain FET
whose source is connected to V+.
The 7206A can also use a 3 x 4 or 4 x 4 keyboard, but requires
a double contact type with the common line tied to V+. The
oscillator will be on whenever power is applied; the DISABLE
output consists of a p-channel open drain FET; its' source is
can nected to V+.
The 7206B requires a 4 x 4 double contact keyboard with the
common line tied to V-. The oscillator will be on only during
the time that a ROW is enabled, and the DISABLE output
consists of an n-channel open drain FET with its' source tied
to V-.
The 7206C uses either a 3 x 4 or 4 x 4 sing Ie contact keyboard;
the oscillator will be on only during the time that a key is
depressed. The DISABLE output consists of an n-channel
open drain FETwith its source tied to V-.
The 72060 uses a single contact 3 x 4 or 4 x 4 keyboard. The
oscillator will be on only during the time that a key is
depressed. DISABLE output consists of a p-channel open
drain FET with its source tied to V+

GENERAL DESCRIPTION
The Intersil ICM72061 A/B/C/D are 2-of-8 sine wave tone
encoders for use in telephone dialing systems. Each circuit
contains a high frequency oscillator, two separate programmable .dividers, a D/A converter, and a high level output
driver.
The reference frequency is generated from a fully integrated
oscillator requiring only a 3.58 MHz color TV crystal. This
frequency is divided by 8 and is then gated into two divide by
N counters (possible division ratios 1 through 128) which
provide the correct division ratios for the upper and lower
band of frequencies. The outputs from these two divide by N
counters are further divided by 8 to provide the time
sequencing for a 4 voltage level synthesis of each sinewave.
Both sinewaves are added and buffered to a high current
output driver, with provisions made for up to two external
capacitors for low pass filtering, if desired. Typically, the
total output harmonic distortion is 20% with no L.P. filtering.
and it may be reduced to typically less than 5% with filtering.
The output drive level of the tone pairs will be approximately

-~-+----ov+

14pF

P,

asc IN

0--+--1 f-----+--+--TO·B

asc OUT ()-_ _ _ _ _ _ _'-_--.J

ICM7206 Oscillator

PIN CONFIGURATION
LP,
lP2
ROW 1
ROW 2

C

c::
c::
c::

C
ROW 4 C
DISABLE C
, v- C
ROW 3

,.
2

(OUTLINE DRAWING PEl

16P
P
15

3

14

4

13

5

ICM
7206/A/B/C/D
12

6

11

7

10

8

9

P
P
P
P
P
P

v+
OUTPUT

ORDERING INFORMATION
PART
TEMPERATURE
RANGE
NUMBER
ICM7206JPE
ICM7206A .JPE
ICM7206B JPE
ICM7206C JPE
ICM7206D JPE
ICM7206/D
ICM7206A/D
ICM7206B/D
ICM7206CID
ICM7206DID

COll
Cal 2
COl3
COl4
OSCOUT
OSC IN

Pin 1 is designated either by a dot or a notch.

7-31

-40 0
_40 0
_40 0
-40 0
-40 0
_40 0
_40 0
-40 0
-40 0

_'10

C to +85 0 C
C to +85 0 C
C to +85 0 C
C to +85 0 C
C to +85 0 C
C to +85 0 C
C to +85 0 C
C to +85 0 C
C to +85 0 C
0 C to +85 0 C

PACKAGE
Plastic
Plastic
Plastic
Plastic
Plastic
DICE
DICE
DICE
DICE
DICE

.O~OI6

ICM7206 Family
ABSOLUTE MAXIMUM RATINGS (Note 1)

Output Volt. Iterm. 15). Not more pos. than +5V with respect to V+,
nor more neg. than -1.0 with respect t6 VOutput Current (terminal 15) ............................. 25mA
Power Dissipation .................................... 300mW
Operating Temperature Range ................. -40"C to +85'C
Storage Temperature Range .................. -55° C to +125' C

Supply Voltage (Note 2) .................................. 6.0V
Supply Current V- (terminal 8) ........................... 25mA
Supply Current V+ (terminal 16) .......................... 40mA
Disable Output Volt. (term. 7) .• Not more pos. than V+ nor more
neg. than -f>V with respect to V+

NOTE 1.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device, at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

NOTE 2.

The ICM7206 family has a zener diode connected between V+ and V- having a breakdown voltage between 6.2 and 7.0 volts. If the
currents into terminals 8 and 16 are limited to 25 and 40mA maximum respectivj3ly, the supply voltage may be increased above 6 volts
to zener voltage. With no such current limiting, the supply voltage must not exceed 6 volts.

TYPICAL OPERATING CHARACTERISTICS
TEST CONDITIONS:

V+= 5.5V, Test Circuit, TA = 25°C unless otherwise specified.

PARAMETER
Supply Current
Guaranteed Operating Supply Voltage Range
INote31
Peak to Peak Output Voltage
RMS Output Voltage

SYMBOL

Rl disconnected

VOP

_40° C

VOUT

l

MIN. TYP. MAX. UNITS

CONDITIONS

1+

450 1000

c:: T A c:: +85° C

3.0

I

Zo

Total Output Harmonic Distortion

THDl

Rl

I
I

= lkfl

Operating
Quiescent

3.0

dB

90
25

200

fl
Kfl

20

25

2.3
1.0

10
10
4.6

Total Output Harmonic Distortion

THD2

Maximum Output Voltage Level

VOH

Minimum Output Voltage Level

VOL

RL =lkll

0.5

Keyboard Input Pullup Resistors
Keyboard Input Capacitance
Guaranteed Oscillator Frequency Range
(Note 41
Guaranteed Oscillator Frequency Range
System Startup Time on Application of Power

R'N
C,N

Terminals 3,4,5,6,11,12,13,14
Terminals 3,4,5,6,11,12,13,14

35

fose

3 c:: I V+ - V-I

2.0

4.5

2.0

7

ton

4VC::JY+ - V-I c:: 6V
ICM7206, ICM7206A

System Startup Time on Application of Power
and Key Depressed Simultaneously
DISABLE Output Saturation Resistance
(ONSTATEI
DISABLE Output Leakage
(OFFSTATEI

100

See Logic Table for Input Conditions
Current =4mA

10lK

See Logic Table for Input Conditions

OSCillator Load Capacitance

Case

Guaranteed Output Frequency Tolerance

fa

Oscillator Startup Time ICM7206B, C, D

tstart

Measured between terminals 9 & 10,
nq supply voltage applied to circuit
-40° C c:: T A c:: 85° C
Any output frequency
Crystal tolerance ±60ppm
Crystal load capacitance CL = 30pF
V+-3V INote5)

150
5

%

V
Kfl
pF
MHz

10

ICM7206B, ICM7206C, ICM7206D
RD

mV

2.5

Either Hi or Low Bands
No Low Pass Filtering
RL = lkfl, C, = .002}J.F I fOUT = 697Hz
C2 =0.02}J.F
I fOUT - 1633Hz
Rl-lkfl

c:: 6V

V

655

Rl = 1 kfl, C" C2 disconnected

Output Impedance

6.0

C" C2 disconnected - Low Band
0.90 1.15 1.45
Rl - 1 kfl, no filtering - High Band
1.10 1.40 1.70
480
Rl = 1 kfl,fOUT = 697Hz
C2 Only
C, to C2
480
Nofiltering
490
490
Rl = 1 kfl, fOUT = 1633Hz
C,
580
C, tOC2
Nofiltering

Skew Between High and Low Band
Output Voltages

}J.A

7
330

ms

700

n

10

p.A

7

pF

NOTE 3:

±0.75

%

7

ms

Operation above 6 volts must employ supply current Ilmltmg. Refer to 'ABSOLUTE MAXIMUM RATINGS' and the Application Notes
for further information.
.
NOTE 4: The ICM7206 family uses dynamic high frequency circuitry in the initial 23divider resulting in low power dissipation and excellent performance over a restricted frequency range. Thus, for reliable operation with a 6 volt supply an oscillator frequency of not less than
2MHz must be used.
'
NOTE 5: After row input is enable<;!.

t
7-32

ICM7206 Family
TRUTH TABLE

7
8
9
10
11

ROWS (1)
ACTIVATED
0
1
1
2 or 3
2 or 3
1
4
0
1
2 or 3
4

12
13

2 or 3 or 4
4

liNE
1
2
3
4
5

6

COlS (2) ACTIVATED
0
1
2 or 3 (incl. col #4)
1
2 or 3 (excl. col #3)
4 or 3 (must excl. col #4)
1
1 or 2 or 3 or 4
0
0
0
4
2 or 3 or 4

OUTPUT
(TERMINAL #15)
Off
frow + feol
frow
feol
D.C. Level
frow , 50% Duty Cycle
feol, 50% Duty Cycle
Off
902Hz + frow
902Hz
902Hz, 50% Duty
Cycle
D.C. Level
D.C. Level

DISABLE
(TERMINAL #7)
Off
On
On
On
On
-trow, 50% Duty Cycle
feol, 50% Duty Cycle
Off
On
On
902Hz, 50% Duty
Cycle
Indeterminate
Indeterminate

COMMENTS
Quiescent State
Dual Tone
Single Tone
Single Tone
No Tone
frow Test
teal Test
n/a'
n/a'
n/a'
n/a'
Multiple Key Lockout
Multiple Key Lockout

'n/a - not applicable to telephone calling.
Nole 1:

Rows are activated lorthe ICM720S/C byeonnecting toa negativesupply voltage with respectto V+ (terminal1SI at least 33% olthe value
01 the supply voltage (V+'-V-I. For the lCM7206A rows (and columnsl are activated by connecting to a positive supply voltage with
respect to V- (terminal 81 at least 33% 01 the value 01 the supply voltage (V+-V-I. The rows and columns 01 the ICM720S8 are activated
by connecting to a negative supply Voltage.
Columns IICM720S1 are activated by being connected to a positive supply voltage with respect to V- (terminal 81 at least 33% 01 the
value 01 the supply voltage (V+-V-1.

Nole 2:

COMMENTS
All combinations of row and column activations are given in
the truth table. Lines 1 thru 7 and 12,13 represent conditions
obtainable with a matrix keyboard. Lines 8thru 11 are given
only for completeness and are not pertinent to telephone
dialing.
Lines 6 and 7 show conditions for generating 50% duty cycle
full amplitude signals useful for rapid testing of the row and
column frequencies on automatic test equipment. In all other
cases, output frequencies on terminal 15 are single or dual4
level synthesized sine waves.

A 'DC LEVEL' on terminal 15 may be any voltage level
between approximately 1.2 and 4.3 volts with respect to V(terminal 8) for a 5.5 volt supply voltage.
The impedance of the OUTPUT (terminal 15) is approximately 20K ohms in the OFF state. The 'DISABLE OUT-OUT ON
and OFF conditions are defined in the TYPICAL
OPERATING CHARACTERISTICS.

SCHEMATIC DIAGRAM
v+ 0>----+(.....- - 0 v·

osc
OSCILLATO

LOW BAND

"-23
SEOUENCER

eN

~

6.4V

OSC
LP 1

DUAL
DTOA
CONVERTER

23

4 X ROWS

HIGH BAND

LP 2

OUTPUT
BUFFER
DRIVER

OUTPUT

DISABLE
LOGIC
DRIVER

DISABLE

-'-23
SEQUENCER

-,-N

CONTROL
LOGIC

4 X COLUMNS

7·33

ICM7206 Family
TEST CIRCUIT (single contact keyboard devices shown)

ROW 1

OUTPUT
14
RL

RoW2

4

13
7206/C/O
12
-5.5V
11

ROW 3

10

RoW4

CoLl

COL 2

CoL3

oUARTZ CRYSTAL PARAMETERS
f
" 3.579,545 Hz
RS .;:;; 100 n
eM:=: 200 mpF
CO" 4.5 pF
CL "30 pF

-5.5V

CoL4

TYPICAL OPERATING CHARACTERISTICS

TOTAL HARMONIC DISTORTION
AS A FUNCTION OF LOAD
RESISTANCE

SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE
100

TA"~5'C

16r------,-------,-------,

I

I

OUTPUT OPEN CIRCUIT

«.
S

I

10

II

t-

i:irr:

~

1.0

u

~

a.

~

o. 1

f

/"

-

--

0.0 1
lK

OSCILLATOR FREQUENCY
DEVIATION AS A FUNCTION
OF SUPPLY VOLTAGE

PEAK TO PEAK OUTPUT
VOLTAGE AS A FUNCTION
OF SUPPLY VOLTAGE

TA" 25 C
CRYSTAL PARAMETERS:
f
" 3,579,545 Hz
RS "45<1
eM'" 20 mpF
Co "4.5 pF

"[ +1.0

-"
2
+0.5

a>
rr:

o

~ -0.5
..J

~

lOOK

LOAD RESISTANCE (n)

,

+1.5

~

10K

SUPPL Y VOL T AGE

/"

-1.0
-1.5

1

V

1.75

I'-c.

tJ

:

1.25

~

1.0

...J

V

o
>.

~ 0.75

/

/

,~

V ,,
V

HIGV
BAND

/

tt-

.f

RL"560n
NO FILTERING

,

'o" 0.5

,

I

TA"1 25,c
1.5

~LoW
BAND

V
4

SUPPLY VOLTAGE

SUPPLY VOLTAGE

.r7-34

.O~OIl

ICM7206 Family
STANDARD TELEPHONE
1

---

COL 1

KEYBOARD

COL 2

KEY

-

COL 3

ROW 2

ROW3

ROW4

I·

FULL KEYBOARD

HI BAND
FREQ. Hz

697
697
697
770
770
770
852
852
852
941
941
941
697
770
852
941

1209
1336
1477
1209
1336
1477
1209
1336
1477
1209
1336
1477
1633
1633
1633
1633

1
2
3
4
5
6
7
8
9

COL4

D 8 8 D
[] 8 8 G
D 8 8 []
D ~ [J G

ROW 1

LOW BAND
FREQ. Hz

.

0
#
A

B

C

·1

0

FIGURE 1: Keyboard Frequencies

2.414'

~
L HI

BAND
SIGNAL

NO LOW PASS FILTERING
C, AND C2 REMOVED

T

APPROX.

HIGH AND LOW

2.6Vp-p

~~~~~~~gJ ES

-

j

APPROX 12V
REFERRED TO V-

FIGURE 2

Figure 2 shows individual currents of a low band and high band frequency pair
into the summing node A (see Figure 3) and the resultant voltage waveform.

DESIRED
FREQUENCY
Hz

ACTUAL
FREQUENCY
Hz

FREQUENCY
DEVIATION

697
770
852
941
1209
1336
1477
1633

699.13
766.17
847.43
947.97
1215.88
1331.68
1471.85
1645.01

+0.30
-D.50
-D.54
+0.74
+0.57
-D.32
-D.35
+0.74

%

7-35

DIVIDE BY N
RATIO

80
73
66
59
46
42
38
34

ICM7206 Family
APPLICATION NOTES
1. Device Description
The ICM7206 family is manufactured with a standard metal
gate C-MOS technology having proven reliability and
excellent reproducability resulting in extremely high yields.
The techniques. used in the design have been developed over
many years and are characterized by wide operating supply
voltage ranges and low power dissipation.
To minimize chip size, all diffusions used to define sourcedrain regions and field regions are butted up together. This
results in approximately 6.3 volt zener breakdown between
the supply terminals, and between all components on chip.
As a consequence, the usual C-MOS static charge problems
and handling problems are not experienced with the
ICM7206.

The control logic block recognizes signals on the row and
column inputs that are only a small fraction of the supply
voltage, thereby permitting the use of a simple matrix single
contact per key keyboard, rather than the more usual two
contacts per key type having a common line. The row and
column pullup resistors are equal in value and connected to
the opposite supply terminals· (ICM7206/C only; for the
ICM7206A all pullup resistors are connected to the Vterminal and for the ICM7206S they are tied to the V+.
Therefore, connecting a row input to a column input
generates a voltage on those inputs which is one half of the
supply voltage.
The ICM7206 family employs a unique but extremely
simple digital to analog (0 to A) converter. This 0 to A
converter produces a 4 level synthesized sine wave having an
intrinsic total harmonic distortion level of approximately
20%. Figure 3 shows a single channel 0 to A converter. The
current sources 02 and 03 are proportioned in the ratio of

The oscillator consists of a medium size C-MOS inverter
having on chip a feedback resistor and two capacitors of
14pF each, one at the oscillator input and the other at the
oscillator output. The oscillator is followed by a dynamic +23
circuit which divides the oscillator frequency to 447,443Hz.
This is applied to two programmable dividers each capable
of division ratios of any integer between 1 and 128, and each
counter is controlled by a ROM. The outputs from the programmable counters drive sequencers (divide by 8) which
generate the eight time slots necessary to synthesize the 4level sine waves.

1:1.414. During time slots 1 and 8 both Sl and S2 are off,
during time slots 2 and 7 only Sl is on, during time slots 3 and
6 only S2 is on, and during time slots 4 and 5 both Sl and S2
are on. The resultant currents are summed at node A,
buffered by 04 and further buffered by R3, R4 and 05. Switch
S3 allows the output to go into a high impedance mode under
quiescent conditions.
Node A is the ~ommon summing pOint for both the high and
.Iow band frequencies although this is not shown in Figure 3.

r---------------~--~--------------~--ov+

,------+--{) LP 2

The synthesized sine wave has negligible even harmonic
distortion and very low values of third and fifth harmonic
distortion thereby minimizing the filtering problems
necessary to reduce the total harmonic distortion to well
below the 10% level required for touch tone telephone
encoding. Figure 4 shows the low pass filter characteristic of
the output buffer for Cl = 0.00221'F and C2 = 0.022I'F. A small
peak of O.4dS occurs at 1100Hz with sharp attention (12dS
per octave) above 2500Hz. This type of active filter produces
a sharper and more desirable knee characteristic than would
two simple cascaded RC networks.

A

"0--4--0 OUT

~~VY--~--------OLPl

~

__

~

_____-+___

~

______________--oV-

-\

+5

V+

11
I

iii

TIME----

:!!

z -5
0
;::: -10

2131451617181
I


zw -15

........

....::>

..
0

-20

TA=25 c C

\

v+
VII\! 13K

-25

13K

1·0022"FI

"Fl

.022j.JF

-30
'.

-35
100

--

\.
\

,

VOUl
1K

1\

\

vlK

10K

100K

FREOUENCY (Hz)
OUTPUT WAVEFORM

FIGURE 3: 0 to A Converter

FIGURE 4:Frequency Attentuation

and Output Buffer

Characteristics of the Output

7-36

Bl~ffer

ICM7206 Family
2. Latchup Considerations
Most junction isolated C-MOS integrated circuits, especially
those of moderate or high complexity, exhibit latchup phenomena whereby they can be triggered into an uncontrollable low impedance mode between the supply terminals.
This can be due to gross forward biasing of inputs or outputs
(with respect to the supply terminals), high voltage supply
transients, or more rarely by exceptional fast rate of rise of
supply voltages.

output going more than 1 volt negative with respect to the
negative supply V- and the circuit operates over the supply
voltage range from 3.5 volts to 15 volts on the device side of
the bridge rectifier. Transients as high as 100 volts will not
cause system failure, although the encoder will not operate
correctly under these conditions. Correct operation will
resume immediately after the transient is removed.
The output vOltage of the synthesized sine wave is almost
directly proportional to the supply voltage (V+-V-) and will
increase with increase of suPpJy voltage until zener breakdown occurs (approximately 6.3 volts between terminals 8
and 16) after which the output voltage remains constant.

The ICM7206 family is no exception, and precautions must
be taken to limit the supply current to those values shown in
the ABSOLUTE MAXIMUM RATINGS. For an example, do
not use a 6 volt very low impedance supply source in an
electrically extremely noisy environment unless a 500 ohm
current limiting resistor is included in series with the Vterminal. For normal telephone encoding applications no
problems are envisioned, even with low impedance
transients of 100 volts or more, if circuitry similar to that
shown in the next section is used.

4. Portable Tone Generator
The ICM7206A/B require a two contact key keyboard with
the common line connected to the positive supply (neg for
ICM7206B) (terminal 16). A simple diode matrix may be used
with this keyboard to provide power to the system whenever
a key is depressed, thus avoiding the need for an on/off
switch. In Figure 6 the tone generator is shown using a 9
volt battery. However, if instead, a 6 volt battery is used, the
diode D4 is not required. It is recommended that a 470 ohm
resistor still be included in series with a negative (positive)
supply to prevent accidental triggering of latchup.

3. Typical Application (Telephone Handset)
A typical encoder for telephone handsets is shown in Figure
5. This encoder uses a single contact per key keyboard and
provides all other switching functions electronically. The
diode connected between terminals 8 and 15 prevents the

, -_ _---j ,Q022pF

G)

R6
5.1K

® 0

® ® ®
(J) ® ®

0

R4
lK

@ 0)

4 X3 MATRIX
KEYBOARD
(ONE CONTACT
PER KEY)
R2
2.7K

R3
680

!

~L,

~l

Rl
2.2K

NOTE: If dual contact keyboard is used, common should be left floating.
FIGURE 5: Telephone Handset Touch Tone Encoder

7·37

ICM7206 Family


....
 ............................ , ....... 300°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to
the device. These are stress ratings only, and functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.
NOTE 1: The fCM7213 like most C-MOS devices, may enter a destructive latchup mode if an input
or output voltage is applied in excess of those defined and there is no supply current
limiting.
NOTE 2: Derate linearly power rating of 200mW at 25° C to 50mW at 70° C.

OPERATING CHARACTERISTICS
TEST CONDITIONS: V+ = 3.0V, lose = 4.194304 MHz, Test Circuit, TA = 25°C unless otherwise specified
PARAMETER
Supply Current
Guaranteed Operating Supply

SYMBOL

CONDITIONS

MIN

1+
VOP

-20°C < TA < 85°C

TYP

MAX

UNITS

100

140

}J.A

4

2

V

Voltage Range

= 6 Volts
= 2.5mA

10

/J A

120

200

n

Inhibit terminal connected to V+

10

40

Test pOint terminal connected

10

40

10

40

Output Leakage Current

IOLK

Any output, VOUT

Output Sat. Resistance

ROUT

Any output, IOLK

Inhit;>it Input Current
Test Point Input Current

Ii
ITP

}J.A

to V+
Width Input Current

Iw

Width terminal connected to V+

Oscillator gm

gm

V+

Oscillator Frequency Range (Note 3)

lose

Oscillator Stability
Oscillator Start Time

-fSTAB
ts

= 2V

umho

100
1

10

2V < V+ < 4V

1.0

= 3.0 volts

0.1

V+ = 2.0 volts

0.2

V+

MHz
ppm
sec

NOTE 3: The ICM7213 uses dynamic dividers for high frequency division. As with any dynamic system, information is stored on very
small nodal capacitances instead of latches (static system), therefore there is a lower frequency of operation. Dynamic dividers
are used to improve the high frequency performance while at the same time significantly decreasing power consumption. At
low supply voltages, operation at less than 1MHz is possible. See application notes.

7-43

.D~DIl

ICM7213
SUPPLY CURRENT AS A
FUNCTION OF TEMPERATURE
130
<120
::!.

I
1- 110
zw

::!.

~ 25r--+--+--t__+--4--1

I 250

I

C

9
z

!!!

200

I-

~100

'\,

::l

r-- f-

>
...I

......~
iil

80

::l

'" 70
-40 -20

0

+20

+40 +60 +80

TEMPERATURE _ °c

Z

:;

o-

./

o
/'

w!!:.
IE:"" -0.5
u.
(.IE
fOSC=4.19MHz
::lZ

1=
5 f+*--+--+--+--4--1
::l
o
o 0.1 0.2 0.3 0.4 0.5 0.6

0 '------L.__L----'-__-'---l.__...1
5.0
3.0
4.0
2.0
SUPPLY VOLTAGE V+ - V-

z
o

za.
wa.

(.I

I-

::l

OSCILLATOR STABILITY
AS A FUNCTION
OF DEVICE TEMPERATURE

~

201--+--/-1-

w

IE:
IE:
::l

~1501--r--~-T~~-+--~
IE:
a100r--+~~~--+--+--1

/

........

(.I 90

8:

30r--r--r-~--~-'--~

<300r--r--'-~--~-'~~

I I

VSUpp=3V
CIN = COUT = 30 pFfOSC':' 4.19 MHz

\

OUTPUT CURRENT AS A
FUNCTION OF OUTPUT
SATURATION VOLTAGE

SUPPLY CURRENT AS A
FUNCTION OF SUPPLY VOLTAGE

-1.0

V

<
:;:

-J-

w
C

>

(.IE

iii !l:

...",..-

5~

0

r--Tc::;;i!>oC"",,-+---+-:;',£-f--1

~$-1
u. +

SUPPLY VOLTAGE

r

7·44

ICM7213
OUTPUT DEFINITIONS
TABLE I.
INPUT STATES·
INHIBIT
WIDTH

TEST
L

L

L

L

L

L

16Hz
. +216

1024 + 16 + 2Hz
(+212+216+221) composite

1Hz.7.8mS
+222

+ (2 24 X 3 x 5)

16Hz
+216

1024 + 16 + 2Hz
(+212+216+221) composite

1Hz.7.8mS

1160Hz. 125ms

+ 222

16Hz
+216

1024 + 16Hz
(+212+216) composite

H
-----

-"----

PIN 2
OUT 3

L

H

--~

PIN 13
OUT 2

H

H

L

PIN 12
OUT 1

16Hz
+216

-~~--

1024

OFF

+ 16Hz

r~ (+212+216)

PIN 14
OUT 4
1160Hz. 1 Sec.

OFF

OFF

SEE

composite

WAVEFORMS

---~

H

L

L

ON

4096 + 1024Hz
(+210+212) composite

2048Hz
+211

34.133Hz. 50% D.C.
+(213 x 5 x 3)

H

L

H

ON

4096

+ 1024Hz

2048Hz
+211

34.133Hz. 50% D.C.
+(213 x 5 x 3)

(+210+212) composite
H

H

L

ON

1024Hz
+212

ON

OFF

H

H

H

ON

1024Hz
+212

ON

OFF

NOTE: When TEST and RESET are connected to ground. or left open. all outputs except for OUT 3 and OUT 4 have a 50% duty cycle.

OUTPUT WAVEFORMS

--I

,_

1--16 Hz

• •••

••••••••

OUT2

1024 Hz

2Hz--------~·1

I

EFFECT OF INHIBIT INPUT TEST connected to ground or left open.

~~------------I

INHIBIT

I
I

OUT 3
CASE

1\ OUT 4

I

~-u-

LJ

I
I
I
I

I

OUT3
CASE 21

COI:C~~~~~

OUT 4

WITH INHIBIT!

~

I
I

<7.8ms-l~r-7~.8~m-s-----f

I

:
I

I

U

!

I
I

~-----'uri--i- - - - - 1

(EFFECT OF
WIOTH
ON OUT 41

~-7.8m.

-------~II
OUT 3

CASE 3

0.75 - 1.0 SEC r
1- 59.75 to
I
60 SECS.

OUT 4

WIOTH

I

u

IL+I_ _oJ
I

:
I

n L..----f

I

CASE 4
(EFFECT OF
WIDTH
ONOUT4)

!

I

OUT3

I

OUT 4 .

I

~~----~U~II--------~

u

I....-!-I_ _ _....
WIDTH

-------~-~-iL--__f

All time scales are arbitrary. and in the case of OUT 3 only the
pulses coinciding with the negative edge of OUT 4 are

shown. Where time intervals are relevant they are clearly
shown.

7-45

ICM7213
APPLICATIONS
2. Logic Family Compatability
Pull up resistors will generally be required to interface
with other logic families. These resistors m\.lst be connected between the various outputs and the positive power
supply.

1. Supply Voltage Considerations
The ICM7213 may be used to provide various precision
outputs with frequencies from 2048Hz to 1160Hz using a
4,194,304Hz quartz oscillator, and other output frequencies may be obtained using other quartz crystal frequencies. Since the ICM7213 uses dynamic high frequency
dividers for the initial frequency division there are limitations on the supply voltage range depending on the
oscillator frequency. If, for example, a low frequency
quartz crystal is selected, the supply voltage should be
selected in the center of the operating window, or
approximately 1.7 volts.

3, Oscillator Considerations
The oscillator COnsists of a C-MOS inverter and a feedback resistor whose value is dependent on the voltage at
the oscillator input and output terminals and the supply
voltage. Oscillator stabilities of approximatelyO.l ppm per
0.1 volt variation are achievable with a nominal supply
voltage of 5 volts and a single voltage dropping resistor.
The crystal specifications are shown in the TEST
CIRCUIT.
It is recommended that the crystal load capacitance (CLl
be no g'reater than 22pF for a crystal having a series resistance equal to or less than 75 ohms, otherwise the output
amplitude of the oscillator may be too low to drive the
divider reliably.
If a very highquality oscillator is desired, it is recommended that a quartz crystal be used having a tight tuning
tolerance ±10ppm, a low series resistance (less than 25
ohms), a low motional capacitance of 5mpF and a load
capacitance of 20pF. The fixed capacitor CIN should be
30pF and the oscillator ·tuning capacitor should range
between approximately 16 and 60pF.
Use of a high quality crystal will result in typical stabilities
of 0.05ppm per 0.1 volt change of supply voltage.

5
OPERATING
WINDOW

4
SUPPLY
VOLTAGE

1

3

2

1-----10KHz

100KH

1MHz

10MHz

FIGURE 1: Window of Correct Operation

The supply voltage to the ICM7213 may be derived from a
high voltage supply by using a simple resistor divider (if
power is of no concern), by using a series resistor for
minimum current consumption, or by means of a
regulator.

CBYPASS 0.01 M F
11
EXAMPLE:
f~ 4.2 MHz
~-~BV ,,;; V";; 12V (10 nom.)
I, ""100MA
R2
12 ""1 mA
R2 ""3K OHMS
12
R1 ""6.BK OHMS
~_~-'

4. Control Inputs
The TEST input inhibits the 218 output and applies the 29
output to the 221 divider, thereby permitting a speedup of
the testing of the +60 section by a factor of 2048 times.
This also results in alternative output frequencies (see
table).
The WIDTH input may be used to change the pulse width
of OUT 4 from 125ms to 1 sec, or to change the state of
OUT 4 from ON to OFF during INHIBIT.

CHIP TOPOGRAPHY
OUT OUT
2
1 TEST V+

OUT
4

R3
11 ~_ _-,
CBYPASS
0.01MF

..

EXAMPLE:
fOSC = 4.2 MHz
BV ,,;; V ,,;; 12V (10V nom)
11 ~ 100MA
R3 = (10- 3 ) K OHMS
10- 4
""68K OHMS

0.063"
1.6mm

WIDTH

FIGURE 2: Biasing Schemes with High Voltage Supplies

7·46

ICM7215
6-Digit 4-Function
LED Stopwatch Circuit
FEATURES

GENERAL DESCRIPTION

• Four functions: start/stop/reset, split, taylor, time
out
• Six digit display: ranges up to 59 minutes 59.99
seconds
• High LED drive current: 13mA peak per segment at
16.7% duty cycle with 4.0 volt supply
• Requires only three low cost SPST switches without
loss of accuracy: start/stop, reset, display unlock
• Chip enable pin turns off both segment and digit
outputs; can be used for multiple circuits driving one
display
• Low battery indicator
• Digit blanking on seconds and minutes
• Wide operating range: 2.0 to 5.0 volts
• 1KHz multiplex rate prevents flickering display
• Can be used easily in four different single function
stopwatches or two two-function stopwatches:
start/stop/reset with time-out, split with taylor. The
component count for a three- or four-function stopwatch will be slightly greater.
• Retrofit to ICM7205 for split and/or taylor
applications

The ICM7215 is a fully integrated six digit LED stopwatch
circuit fabricated with Intersil's low threshold metal gate
CMOS process. The circuit interfaces directly with a six
digit/seven segment common cathode LED display. The low
battery indicator can be connected to the decimal point
anode or to a separate LED. The only components required
for a cOmplete stopwatch are the display, three SPST
switches, a 3.2768MHz crystal, a trimming capacitor, three
AA batteries and an on-off switch. For a two function stopwatch, or to add a display off feature, one additional slide
switch is required. The circuit divides the oscillator frequency by 215 to obtain 100Hz, which is fed to the fractional
seconds, seconds and minutes counters, while an intermediate frequency is used to obtain the 1/6 duty cycle
1.07KHz multiplex waveforms. The blanking logic provides
leading zero blanking for seconds and minutes independently of the clock. The ICM7215 is packaged in a 24-lead
plastic DIP.

PIN CONFIGURATION

BLOCK DIAGRAM

(OUTLINE DRAWING PG)

6 OUTPUTS

OSC OUT
LBI ANODE

MULTIPLEX
GENERATOR

V'
Seg c

7 OUTPUTS
1 INPUT

~
BATT.

ORDERING INFORMATION
Order devices by following part number ICM7215 I PG
Order dice by following part number
ICM7215/D

7·47

MODE
RESET

Seg e

DISPLAY UNLOCK

Seg d

10ths

Seg g

100ths

Seg b

V·-

Seg f

CHIP ENABLE

510
1 OUTPUT

TEST
START/STOP

Seg a

51
4 INPUTS >-----1

OSCIN

M10
Ml

ICM7215
ABSOLUTE MAXIMUM RATINGS
Supply Voltage ...................................................'....... 5.5 V
Power Dissipation (Note 1) .... ; ......................................... 0.75 W
Operating Temperature ........................................ -20°C to +70°C
Storage Temperature ......................................... -55°C to +125°C
Input and Output Voltage ....... equal to but never exceeding the supply voltage
Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions above those indicated in the operational
sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

OPERATING CHARACTERISTICS:
TEST CONDITIONS: TA = +25° C, stopwatch circuit, V+ = 4.0V unless otherwise specified.
PARAMETER
Supply Voltage

-20°C

Supply Current

SYM
V+
1+

Segment Current

ISEG

5 seg ments lit

CONDITIONS
~ TA < +70°C

MIN

TYP

2.0

Display off

Peak

0.6

MAX
5.0
1,5

UNITS
V
mA

1.8 Volts across display

9.0

13.2

Average

2.2

Switch Actuation Current

Isw

Switch Actuation Cu rrent
Digit Leakage Current

IOLK

Segment Leakage Current

ISLK

All inputs except chip enable

20

50

Chip enable

50

200

= 2.0V
VSEG = 2.0V
VOIG

I'A

50
100

Low Battery Indicator

7

Trigger Voltage

VLBI

LBI Output Current
Oscillator Stability
Oscillator Transconductance

ILBI
fSTAB
gm

Oscillator Input Capacitance

Cosel

2.2

= 2.0V, VLBI = 1.6V
= 2.0V to V+ - 5.0V
V+ = 2.0V

2.8

V+
V+

V

2.0

mA

6

PPM

30

I'mho
pF

120
24

36

NOTE 1: The output devices on the ICM7215 have very low impedance characteristics, especially the digit cathode drivers. l/these devices are
shorted to a low impedance power supply, the current could be as high as 300mA. This will not damage the device momentarily, but if
the short circuit condition is not removed immediately probable device failure will occur.
------~-

STOPWATCH CIRCUIT

1::: ~ r@ab
7 _

d

6 ....... ee

5 ....... a
4 -c
2 -

de
II'

D.P.Ml0

t
14

COMMON CATHODE DISPLAY

B. B. B. B. B.
Ml

S10

t

t

13

v+

12

SI

10th.

11t

t
18

100th.

t

17

v+

QUARTZ CRYSTAL
PARAMETERS
f = 3.2768MHz
RS = son
CM = 23mpF

ROTARY SWITCH WITH
TWO DECKS GANGED TOGETHER

co = 14pF
CL

= ISpF

SWITCH TRUTH TABLE
MODE
START/STOP/RESET
SPLIT
TAYLOR
TIME-OUT
N.O. NORMALLY OPEN
_ _ TO DISPLAY

7.-48

SWITCH MODE DISPLAY
pos.
(21)
(19)
1
FLOAT FLOAT
2
V+
UNLOCK
3
v- UN~OCK
4
FLOAT
v-

.O~Oll

ICM7215
TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT VS VOLTAGE

SEGMENT CURRENT VS SUPPLY VOLTAGE

~

'"

TA = +25°C

§.

/

~ 0.6

III

a
>~

IL

:J

0.4
0.2

UI

V

~ 15

5

~ 0

4.0

./

V

IL

5.0

2.0

SUPPLY VOLTAGE (V+)

/

g

/

III

2.7

~

"'-

"",-

g~ 2.5

V

..........

II:

~ 2.3
~

ii:

I- 2.1

3.0

5.0

~ 2.9

....

V
./
2.0

4.0

LOW BATTERY INDICATOR (LBI)
TRIGGER VOLTAGE VS TEMPERATURE

I

TA = +25°C
COUT = 22pF

V

3.0

SUPPL Y VOLTAGE (V+)

OSC. STABILITYVSSUPPLYVOLTAGE
I

V

L

V

::IE

~

ll!
II!

3.0

/

//

:J

o
I- 10
a'j.

0.0
2.0

I

III

v/

V

I

§. 20 TA = +25°C
IW(LED) = 1.8V
Z

/

II:
II:

r-r

;;;

0.8 DISPLAY OFF

4.0

iii
....

5.0

-10

SUPPLY VOLTAGE (V+)

0

10

'" "
50

30

TEMPERATURE ("C)

FUNCTIONAL OPERATION

START/STOP/RESET MODE

Turning on the stopwatch will bring up the reset state with
the fractional seconds displaying 00 and the other digits
blanked. This display always indicates that the stopwatch is
ready to go.
The display can be turned off in any mode by connecting the
chip enable input to V+.

When the mode input is floating and the display input is floating or connected to V+ the circuit is in the start/stop/reset
mode.

,-,,-,

L"_'
RESET

::;-;,'-'_,
cc

,-, I I '"

U::'

CLOCK AND
DISPLAY COUNTING
PRESS
START/STOP
ONCE

li/l

'-

-'0

UU

DISPLAY STOPS
PRESS
START/STOP
ONCE

RESET
PRESS
START/STOP
ONCE

one minute. The range of the stopwatch is 59 minutes 59.99
seconds, and if an event exceeds one hour, the number of
hours must be remembered by the user. Leading zeroes are
not blanked after one hour.

.D~UIl

ICM7215
TAYLOR OR SEQUENTIAL MODE
When the mode input is connected to V-, the stopwatch is in
the taylor or sequential mode.

,-,,-,

In I , I

eU I

LILt
RESET

I I

DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING

CLOCK AND
DISPLAY COUNTING

,,-

tC .J.J

I

DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING

PRESS
PRESS
PRESS
PRESS
DISPLAY
START/STOP
START/STOP
START/STOP
UNLOCK
ONCE
ONCE
ONCE
ONCE
- - - - 20.47 sec.---_·~---12.35 sec.---_~----42.79 s e c . - - - -

I I I /II

,-; "
'-' '-'

C -; '0

CLOCK AND
DISPLAY COUNTING

DISPLAY STOPS
CLOCK RESETS
AND STARTS COUNTING

PRESS
START/STOP
ONCE

RESET

PRESS
RESET

Each split time is measured from zero in the taylor mode; Le.,
after stopping the watch, the counters reset momentarily and
start counting the nElxt interval. The time displayed is that
elapsed since the last activation of start/stop. The display is

stationary after the first interval unless the display unlock is
used to show the running clock. Reset can be used at any
time.

SPLIT MODE
When the mode input is connected to V+ the stopwatch is in
the split mode.

,-,n

"',11
, (:r

'_'LI

-/1-' " ,

CLI -, ,

,I

RESET

CLOCK AND
DISPLAY COUNTING

DISPLAY STOPS
CLOCK CONTINUES COUNTING

PRESS
PRESS
START/STOP
START/STOP
ONCE
ONCE
_ · 2 0 . 4 7 s e c . - - - . _ - - - 12.35

uC ,,-,

'/

I _, II::'

CLOCK AND
DISPLAY COUNTING

PRESS
START/STOP
ONCE
sec._·~._----

, I:J,,- (),-

PRESS
DISPLAY
UNLOCK
ONCE

42.79 s e c . - - - -

"n

UU

LI'

DISPLAY STOPS
CLOCK CONTINUES COUNTING
PRESS
START/STOP
ONCE

DISPLAY STOPS
CLOCK CONTINUES COUNTING

RESET

PRESS
RESET

The split mode differs from the taylor in that the lap times are
cumulative in the split mode. The counters do not reset or
stop after the first start until' reset is activated. Time

displayed is the cumulative time elapsed since the firststart
after reset. Display unlock can be used to let the display
'catch up' with the clock, and reset can be used at any time.

7·50

ICM7215
TIME OUT MODE
When the mode input is floating and the display input is tied
to V-, the stopwatch is in the time-out mode.

,-,,-,

:J'-' U -;

'-'LI

L'-'
CLOCK AND
DISPLAY COUNTING

RESET

PRESS
START/STOP
ONCE

I I I

PRESS
START/STOP
ONCE

I

I

DISPLAY STOPS
CLOCK STOPS

PRESS
START/STOP
ONCE
20.47 sec. _ _ TIME O U T - - 22.32 sec.

/II

11"

C -; '0

'-' '-'

CLOCK AND
DISPLAY COUNTING

PRESS
START/STOP
ONCE

DISPLAY STOPS
CLOCK STOPS

RESET
PRESS
RESET

be used at any time. The display unlock button is bypassed in
this mode.

In the time-out mode the clock and display alternately start
and stop with activations of the start/stop switch. Reset can

APPLICATION NOTES
LOW BATTERY INDICATOR

SWITCH CHARACTERISTICS

The on-chip low battery indicator is intended for use with a
small LED or the decimal points on a standard LED display.
The output is the drain of a p-channel transistor two-thirds
the size of the segment drivers, and designed to provide a
trigger voltage of approximately 2.5 volts at room
temperature. Normal AA type batteries will provide many
hours of accurate timekeeping after the indicator comes on,
however the wide voltage spread between the LSI voltage
and minimum operating voltage is required to guarantee low
battery indication under worst case conditions.

The ICM7215 is designed for use with SPST switches
throughout. On the display unlock and reset inputs the
characteristics of the switches are unimportant, since the
circuit responds to a logic level held for any length of time
however short. Switch bounce on these inputs does not need
to be specified. The start/stop input, however, responds to
an edge and so requires a switch with less than 15ms of
switch bounce. The bounce protection circuitry has been
specifically designed to let the circuit respond to the first
edge of the signal, so as to preserve the full accuracy of the
system.

CHIP ENABLE
The chip enable input is used to disable both segment and
digit drivers without affecting any of the functions of the
device. When the chip enable input is floating or connected
to V-, the display is enabled, and when the tied to V+ the
display is turned off. One example of the many possible uses
of this feature is driving one display from two ICM7215
devices, one in the split mode and the other in the taylor
mode. The circuit below indicates how the user can obtain
lap and cuml!'ifative readings of the same event.

LATCHUP CONSIDERATIONS
Due to the inherent structure of junction isolated CMOS
devices, the circuit can be put in a latchup mode if large
currents are injected into device inputs or outputs. For this
. reason special care should be taken in a system with multiple
power supplies to prevent voltages being applied to inputs
and/or outputs before power is applied to the 7215. If only
inputs are affected, latchup can also be prevented by limiting
the current into the input terminal to less than 1mA.

DISPLAY
TO DISPLAY

ICM7215
SPLIT

TO DISPLAY

1 1----.--+--1
15 24 1----+---1

~----~~

ICM7215
24 TAYLOR
15

~~----~

TAYLOR SPLIT
ALL OTHER SWITCHES COMMON TO BOTH DEVICES

7-51

7

ICM7215
OSCILLATOR DESIGN

OSCILLATOR TUNING

The oscillator of the ICM7215 includes all components on
chip except the 3.2768 MHz crystal and the trimming
capacitor. The oscillator input capacitance has a nominal
value of 30pF, and the circuit is designed to work with a
crystal with a load capacitance of approximately 15pF. If the
crystal has characteristics as shown on page 3, an 8-40pF
trimming capacitor will be adequate for a tuning tolerance of
±30PPM on the crystal. If the crystal's static capacitance is
significantly lower, a narrower trimming range may be
selected.
After deciding on a crystal and a nominal load capacitance,
take the worst case values of Cin, Cout and Rs and calculate
the gm required by:

Tuning can be accomplished by using the 10th or 100th
seconds with the device reset. The frequency on the cathode
should be tuned to 1066.(>67 Hz, which is equivalent to a
period of 937.5 microseconds. Note that a frequency counter
cannot be connected directly to the oscillator because of
possible loading.

gm = w2 Cin Cout Rs

{ 1 + Co (Cin + Cout)}
Cin Cout

2

Co = static capacitance
Rs = series resistance
Cin = input capacitance
Cout = output capacitance
w
= 211" x crystal frequency
The resulting gm should be less than half the gm specified for
the device. If it is not, a lower value of crystal series
resistance and/or load capacitance should be specified.

TEST POINT
The test pOint input is used for high speed testing of the
device. When the input is pulsed low, a latch is set which
.speeds up counting by a factor of 32; each pulse on the test
point rapidly advances both minutes and seconds in a
parallel mode. To accurately rapid advance the signal
applied to the test pOint must be free of switch bounce. The
circuit is taken out of the test mode by using either reset or
startJsto~

REPLACING THE ICM.7205 WITH THE ICM7215
The ICM7215 is designed to be compatible with circuits
using the ICM7205. If the 7205 is used only in the split mode
no changes are required. If the 7205 is used in the taylor
mode and the split taylor input (pin 21) is left open, a jumper
from pin 21 to v- must be added when converting to the 7215.
A jumper may also be needed if the 7205 is used with a split!
taylor switch. Once the jumper has been added the board
can be used with either device.

CHIP TOPOGRAPHY
START!
STOP
MODE

sege

I

RESET

eega

DISPLAY
UNLOCK

sege
115 mils
(2.921)

10th.

segd
100th.

segg

v-

segb

CHIP
ENABLE

segl
Sl

S10

Ml

Ml0

 ......1 - - - - - - 1 0 6 mils -----..,,.~I
(2.6921

PAD SIZE 5 x 5 mil.
(0.127 x 0.127)

7-52

ICM7223
4.Digit LCD Clock
Circuit with
Snooze Alarm
FEATURES

GENERAL DESCRIPTION

• 3-1/2 or 4 digit display with AM/PM and alarm flags

The ICM7223 is a fully integrated 4-digit LCD clock
circuit with 24 hour alarm and 8 minute snooze timer.
For high accuracy and low power consumption a
32.768 KHz quartz watch crystal is used as the time
base, and the number of external components has
been reduced to a minimum.
The time keeping and alarm time counters are split
during setting, allowing hours and minutes to be set
independently, each ata 2 Hz rate. A 'time hold' mode is
entered when setting minutes; seconds are automatically reset to zero. The clock starts when the RUN
mode is entered, thereby permitting synchronization
of the clock to the nearest second. Seconds are not
displayed.

• 12/24 hour user selectable formats
• Direct alarm drive @ 3V pop, with complex (cricket)
alarm tone

• 8 minute snooze (Dice programmable from 2 to 14
minutes in two minute increments)
• Single battery operation (1.5V)
• Low current - 6 }.LA maximum
• On-chip fixed oscillator input capacitor
• 32 kHz oscillator requires only quartz crystal and
trimming capacitor
• Voltage tripler for large displays

The ICM7223 is fabricated using Intersil's low
threshold metal gate CMOS process for minimum cost
and long battery life.

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

ICM7223IPL

-20°C to +70°C

40 Pin Plastic DIP

ICM7223D/D

-20°C to +70°C

DICE

BLOCK DIAGRAM

PIN CONFIGURATION
(OUTLINE DRAWING PL)

osc IN

Vi CAP 3 CAP 2 CAP 1

DSC OUT

Bl+C1(C1)
F2

Vi
25pF

1
SET AND DISPLAY
CONTROL

lOGIC

HRS.lMIN.
ADVANCE

BP

'2
02

HRS/MINS ADV

AL 2

12/24

92

asc IN
asc OUT
v'

A2

BACKPLANE + 26 SEGMENTS

~v+

6v,

V'

G3

AL 2

'3

AL 1

A3+ 03

AL 1

RUN/SET

C2

'3
ALARM OFF
TEST

AM (B1)

G2

COLON

12/240--+--+---;

PM(+~~ ++~11)

C3

ALOFF~

SNOOZE

B3

Vi

'4
G4

CAP2

CAPJ

E4

CAP,

04

A4

C4

B4

PARENTHESES AND BOLD TYPE INDICATE
24 HOUR OPERATION
SNOOZE

(-1.5V)

7-53

D

ICM7223
ABSOLUTE MAXIMUM RATINGS
Storage Temperature ........... -55° C to +125° C
Operating Temperature .......... -10°C to +60°C
Power Dissipation)1) ...................... 100 mW
Supply Voltage)2)
V+-V1' ., ................................. 2.0V
V+-V3 ................................... 5.5V
Input Voltage (Osc. In, Test,
Set, Display) .................... V- ,,; VIN ,,; V+
Output Voltage (Osc. Out, 512) .•... Vi""; VOUT ,,; V+
(All Other Pins) ................... Vi,,; VOUT"; V+

NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devic.es at
these or any other conditions above those indicated in the
operation sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

OPERATING CHARACTERISTICS
TEST CONDITIONS: V+-V- = 1.55V, voltage tripler ~onnected, TA = 25° C, Test Circuit,
unless otherwise specified, voltages and currents are shown as absolute values.
SYMBOL

PARAMETER
Supply Voltage

V+

Supply Current

1+

Tripier Output Voltage

MIN.

TYP.

1.2
4

Display Disconnected

V3

13 = 0.0 p.A

4.2

13 = 1.0 p.A

4.1

Segment Drive Current

ISEG

VSAT = 0.2V (Both Directions)

5

Backplane Drive Current

IBP

VSAT = D.1V (Both Directions)

20

Switch Actuation Current

Isw

Vsw = V+ or Vsw = V3

Alarm Saturation Resistance

MAX.

UNITS

1.8

Volts

6

p.A
V

p.A
p.A
3

5

p.A

P-CH at 1 mA

P-CH

350

500

N-CH at 0.5 mA

N-CH

1500

1800

RAL(ON)

Oscillator Stability

ISTAB

V = OV, 1.2DV S V+ S 1.55V,
COUT = 25 pF

Oscillator Input Current l31

losci

'OSC IN' Connected to V+
'OSC OUT' Open Circuit

PPM

0.2

p.A

CIN

20

25

Oscillator Transconductance

gm

10

15

ICM7223 is, fully short cirCuit protected on all inputs and
outputs. However, if by forward biasing an input or output the
device is put into a latchup condition, power dissipation must be
limited to 100 mW to prevent destruction of the device.
2. The ICM7223 is intended for use with two power supplies, one of
which is derived from an external battery V, and the other is
generated internally by the voltage multip)ier iV'3 The common
point of the two supplies is the most positive, V+. If desired the

n

2

Oscillator Input Capacitance

R ~o~~~
_

CONDITIONS
V- =.,OV -10°C < TA < 60°C

30

pF
p.mho

circuit can be supplied with an external V3 by disconnecting the
multiplier capacitors, or \fJ and V, can be tied together (for a 1.5
volt display for instance).
3. The integrated oscillator biasing components have a nonlinear
characteristic depending on the instantaneous values of the input
and output voltages of the oscillator and the supply. Under
oscillator startup conditions this component has a maximum
value.

TYPICAL APPLICATION
26 LINES TO DISPLAY
TIME SET
DISPLAY OUTPUTS

0---0

v'

0---0

V3

RUN"" FLOAT

RUN/SET

CRYSTAL

[=:::J

HRSAOVANCE
0 - - - 0 v'

OSCOUT
ICM7223

MIN ADVANCE

O---OV3

5-35pF

v'

SNOOZE
SNOOZE

o - - - - - f 12/24 HR
FLOAT = 12HR
=24HR

v+

ALl

AL2

CAP 1

CAP 2

CAP 3

v'

I---c:r 0 - - - 0 v'

At OFF

NOTE: ALL CONTROL INPUTS HAVE
INTERNAL PULL DOWNS TO Vi"
CRYSTAL PARAMETERS:
f = 32,768 Hz
CL = 10pF
eM = 2.5mpF

As

=

20KH

ALARM
TRANSDUCER
(4kHz)

1.5V

T o05pF
bv,

7·54

ALARM OFF
0--0 V'

ICM7223
TYPICAL PERFORMANCE CHARACTERISTICS
OSCILLATOR STABILITY VS. SUPPLY VOLTAGE

SUPPLY CURRENT VS. SUPPLY VOLTAGE

l

z
0
;::

+2

~

+1

«

f - - - 1----

e----

0

>-

u

/'

~
=>

I

d
w

fE

-1

a:
0

~

t-

j

2.0

1.0

----

V

V

l7

V
-- -

-2

U

~.-L_-'-

1.2

__L - - ' - _ - " .
1.5

'"0
1.8

1.2

2.0

1.5

1.8

SUPPLY VOLTAGE (VOLTSI

SUPPL Y VOLT AGE {VOL TSI

ALARM DRIVER OUTPUT CURRENT
VS. OUTPUT VOLTAGE

VOLTAGE MULTIPLIER OUTPUT VOLTAGE
VS. OUTPUT CURRENT

P CHANNEL OUTPUT VOLTAGE

4.5

I

!

1

j-

1
TRIPLEI1

v+

I
1.55V

--- - 1---,--- -

t:::J
CL
t-

=>

o

--'
w
Z

z

«
:I:

u
Z

N CHANNEL OUTPUT
VOLTAGE {VOLTSI

OUTPUT CURRENT IH {MAl

NORMAL CLOCK OPERATION
r::-::-_-::-'7"---"A;:;LA.,RM
RUN
MODE

Pi :t!n n
fC+UU
COLON FLASHES

AT 1 Hz RATE

FLAG

In normal operation, hours and minutes are displayed
with the colon flashing at a 1 Hz rate. An AM and a PM
indicator flag is provided in the 12 hour mode, while in
the 24 hour mode, the pads used for the AM/PM flags
are utilized to drive the segments which produce the
numeral "2" in the tens of hours digit. The alarm 'flag
will be on if the alarm is enabled, and off if the alarm is
not enabled; (Alarm Off input at V+\.

7-55

.D~DI6

ICM7223
TIME SETTING
PM
TIME
SET

COLON STILL FLASHING
NO CHANGE IN DISPLAY

HRSADVANCE
AT 2 Hz RATE
COLON STILL FLASHING

MIN. ADVANCE AT 2 Hz
COLON STOPS FLASH ING
SECONDS RESET TO ZERO
TIME HOLD MODE

COUNTERS START RUNNING
COLON STARTS FLASHING

NOTE: When the HRS/MIN Advance input is activated
there will be a pause of less than one second before the
counters start advancing at a 2 Hz rate.

TIME SETTING
To set the time, the RUN/SET switch is placed in the
Time Set position, and the HRS/MIN advance input is
used to advance the hours or minutes. The seconds are
reset to zero and counting is stopped whenever the
minutes are set. The clock will start when the RUN/SET
switch is put back into the RUN position, and while in
the RUN position, inputs from the HRS/MIN advance
switch are disabled to prevent accidental setting.

After 8 minutes the alarm will again sound, and will
continue for 2 minutes and stop unless ALARM OFF is
used or another Snooze cycle is activated. The Snooze
may be repeated as many times as desired.

NOTE: In die form, all the SNOOZE input pads are
available, allowing the manufacturer or user to select
snooze times from 2 to 14 minutes in 2 minute steps.
These pads are identified as SN 1, SN2 and SN3. See
the following table for the selection of Snooze times:

ALARM OPERATION

INPUT CODE (1 = V+)
SN3
SN2
SN1

II

The alarm comparat6r provides a 24 hour alarm in both
12 and 24 hour modes. When the time of day and alarm
times are equal, the alarm outputs are enableci,
providing that the ALARM OFF input is at V1; If the
ALARM OFF input is at V+, the alarm outputs will not be
enabled. The alarm outputs provide a push-pull, or
bridge, configuration for direct drive of a piezoelectric
transducer, and if increased drive (loudness) is
desired, a coil and external NPN transistor may be
used. The external transistor should be driven by the
ALARM 1 output. The coil DC resistance should be
1000 or greater,to limit the peak currentto less than
13 mAo

SNOOZE
TIME

0

0

0

None

0

0

1

2 minutes

0

1

0

4 minutes

0

1

1

6 minutes

1

0

0

8 minutes

1

0

1

10 minutes

1

1

0

12 minutes

1

1

1

14 minutes

ALARM SETTING

ALARM SET
COLON NOT
FLASHING

The alarm signal is a complex waveform that generates
the Intersil Cricket sound. The alarm output will
automatically stop after one minute unless either the
ALARM OFF or the SNOOZE input is used. The alarm
transducer should be selected to provide maximum
output (loudness) at 4 kHz, that is, it should be
resonant at 4 kHz.

atool

HRS ADVANCE
AT 2 Hz RATE

MIN.
ADVANCE

MIN. ADVANCE

AT 2 Hz RATE

SNOOZE OPERATION
A momentary closure of the SNOOZE switch to V+ will
silence the alarm and start the snooze timer. The
Snooze input must be activated during the one minute
the alarm is sounding in order to start a Snooze cycle.

The alarm time is set by switching to' Alarm Set, then
using the HRS/MIN ADVANCE input to set hours and
minutes. The alarm time is displayed only when the
RUN/SET switch is in the Alarm· Set position.

7·56

,

ICM7223
SNOOZE OPERATION
r----------------------------2t~~~~S----------------------------,

BMIN.

PRESS
SNOOZE
BUTTON
ONCE

LATER

PRESS
L----_ _ _ _ _

~~~~6~

2MIN.
LATER

ALARM
SOUNDS

----'

ALARM
DISABLED

ALARM
OFF

ONCE

NOTE: IF ALARM OFF IS LEFT AT V+ THE ALARM WILL NOT SOUND 24 HOURS LATER.

APPLICATION NOTES
ALARM DRIVE
The ICM7223 alarm output transistors are capable of
directly driving a piezoelectric ceramic transducer at ~
volts peak-to-peak. Any transducer that does not
require more than 1 mA of peak current may also be
used. The transducer should generate maximum
output at 4 kHz. If a louder sound is desired, buffering
(using an NPN transistor and 5 mho coil) or sound
enhancement techniques such as a resonant cavity or
diaphragm will be required. See Application Bulletin
A031 for details.

volt supply. The oscillator is of the inverter type with a
nonlinear feedback resistor included on chip, which
has a maximum resistance under startup conditions.
The nominal load capacitance of the crystal should be
less than 15 pF, typically 12 pF. In specifying the
crystal, the motional capacitance, series resistance
and tuning tolerance have to be compatible with the
characteristics of the circuit to insure startup and
operation over a wide voltage range under worst case
conditions.
The following expressions can be used to arrive at a
crystal specification:
Tuning range

TEST MODE
The high speed test mode for automatic testing is
entered by pulling the ALARM OFF/TEST Input to.-7
volts referenced to Vi"". In this state the HRS/MIN
ADVANCE input will advance the appropriate counters
at the rate that the input is toggled. The colon will
appear to stop flashing as it is changing state more
rapidly than the display can respond. In the run mode
the minutes will change at a 4.27 Hz rate, as the clock
has been speeded up by a factor of 256 Hz. The
backpl.ane frequency will be 512 Hz. The voltage tripler
drive frequencies remain the same as in normal modes.
ALARM AND DISPLAY TEST
If the ALARM OFF and SNOOZE buttons are pushed
simultaneously, all segments of the display will be
turned on and the alarm will sound, while none of the
time counter contents are disturbed.
VOLTAGE MULTIPLIER
The ICM7223 voltage multiplier may be utilized only in
a tripler configuration; only four pins, and three
external capacitors are requi red. The con nection of the
capacitors differs from that used in standard watch
circuit type voltage multiplers, therefore close
attention should be paid to substrate design to ensure
the proper connection of the capacitors.
OSCILLATOR
The oscillator of the ICM7223 is designed for low
frequency operation at very low currents from a 1.55

-.1f

T

Cm
. CL = CIN COUT
2 I Co + CLI '
CIN + COUT

gm required for startup
gm = 4rr2f2 CIN COUT Rs ( 1

CO)2
+ CL

where
Rs
f
Llf

= Series Resistance of Crystal
= Frequency of the Crystal
= Frequency Shift from Series Resonance
Frequency
Co = Static Capacitance of Crystal
CIN = Input Capacitance
COUT= Output Capacitance
CL
= Load Capacitance of Crystal
C m = Motional Capacitance of Crystal

The gm required for startup calculated should not
exceed 50% of the gm guaranteed for the device.
POWER UP RESET
An on chip circuit is provided thatwill reset all counters
and flip-flops to a known state when power is first
applied. The alarm and timekeeping counters will be
reset to 1:00 am in the 12 hr. mode and 0:00 in the 24 hr.
mode. This function is not tested during automatic
testing, as it does not affect normal circuit operation.
7·57

ICM7223
DISPLAY

D

:

r-------------------------~

: [%)fM]

:'~C'D
[Jt) rrB f fIT]
fft(
B'8 + BCB' D
B=
a'i
:

MOTOROLA MLC406
BECKMAN ' 737·01
LADCOR
LAO-OOl
HAMLIN
TIME¥:
COCKROFT

~~~.

3411
T1001
CII202

F1

:

B1

E1

,C1

I~
L
_____

C

0

P

F
1

G
\

F2

E
1

D
1

~

B2

F3

,B3

F4

B4

~
.~
~
___________________
6

C B A F G E
1112222

, ,,

C

B

A

L

F G
33

E
J

D
3

C
3

B

A

f

G

E

DeB

A

334444444

, c, a_,,
"

DISPLAY FONT
NUMBERS

f

COCKROFT CII201

A~D·BD~

M

LI C·_I DZZ2

CHIP TOPOGRAPHY
ICM7223

,.7 ( 3 . 7 3 ) - - _
I •• (3.5611---t

80 (2.032)

•• (1.",6)--=

2. (0.5',')--""

CHIP DIMENSIONS: 116 x 147 mils (2.95 x 3.73 mm)

7·58

Z

B

...

E

, ,

:

I

~

ICM7223A
3·1/2 Digit
LCD BaHery Operated
Clock Circuit With Snooze
and Sleep Timers
FEATURES

timers. For high accuracy and low power consumption
a 32.768 kHz quartz watch crystal is used as the time
base, while the number of external components has
been reduced to a minimum. This circuit is intended
for use in 9V clock-radio systems where both the clock
and the radio operate from the same battery.
The time keeping and alarm time counters are split
during setting, allowing hours and minutes to be set
independently, each at a 2 Hz rate. A 'time hold' mode
is entered when setting minutes; seconds are
automatically reset to zero. The clock starts when the
RUN mode is entered; this permits synchronization of
the clock to the nearest second. Seconds are not
displayed.
The alarm employs a snooze timer that may be programmed from 2 to 14 minutes in two minute
increments; the sleep timer may be set from 8 to 56
minutes in 8 minute increments. The alarm outputs
consist of a complex (cricket) alarm tone to directly
drive a speaker of piezoelectric transducer, and a radio
enable output which allows control of a clock radio.
Low battery voltage is indicated by the display flashing
at a 1 Hz rate whenever the battery voltage falls below
about 5.6V.
The ICM7223A is fabricated using Intersil's low
threshold metal gate CMOS process for minimum cost
and long battery life. Current drain at 9 volts is typically
15J.1A with a maximum of 25J.1A.

• Single 9V transistor battery operation
• 3-1/2 digit display with AM/PM, SLEEP and
ALARM flags
• Direct alarm drive with complex (cricket) alarm tone
• Programmable snooze
• Programmable sleep timer with RADIO ENABLE
OUTPUT
•
•
•
•
•

Wide operating voltage range - 4 to 15 volts
Low current - 15J.1A @ 9V
On-chip fixed oscillator Input capacitor
Uses standard 32.768 KHz crystal
Low battery Indicator (display flashes at 1 Hz)

• Display and alarm test

ORDERING INFORMATION
PART
NUMBER

TEMPERATURE
RANGE

PACKAGE

ICM7223AIPL

-20' C to +85' C

40 Pin Plastic DIP

ICM7223A/D

-20' C to +85' C

DICE

GENERAL DESCRIPTION
The ICM7223A is a fully integrated 3-1/2 digit LCD
clock circuit with 24 hour alarm, and sleep and snooze

IiFJ

r-------~--------,.
OSCIN
OSCOUT
BLOCK
DIAGRAM

25PF

J

DIVIDER CHAIN

c~-t--rL_-~-:- :-~-~-~-~-:-~-J1~:"c1~-,-,

-Ij-SE-T-AN-O-O-'S-PL-A-yl---o RUN/SET
CONTROL

1 Hz

LOGIC

1----iU ~~~.:I~E

r--'----ii-----ID
,.,~----,u

L,_--.__S;;::~-O

26 SEGMENTS

v+
(GNDI

v-

V~REG -1.SV

(-9V)

TO -2.0V

7·59

SN 3

SN 2

SN 1

ALARM OFF

~
RADIO

ENAB LE
AL OUT

ICM7223A
PIN CONFIGURATION (outline dwg PL)
81 +C1

PM

F2

AM

G2

ALARM FLAG

E2

BP

02

HRS/MINS ADV

C2

RUN/SET

B2

VREG

A2

osc

COLON

IN

OSCOUT

F3

V+IGNOI

G3

V-

E3

RADIO ENABLE

A3+03

ABSOLUTE MAXIMUM RATINGS
Storage Temperature ............. -55°C to +125°C
Operating Temperature ............. -20°C to +85°C
Power E>issipation l11 ••••••••••••••••••••••• 500 mW
Supply Voltage ................................ 18V
Input Voltage
(OSC IN, SN1, SN2, SN3) ..... -2V ::;VIN::; V+ + 0.3V
(RUN/SET, HRS/MIN ADV,
AL OFFITEST) ...... V- - 0.3V ::; VIN ::; V+ + 0.3V
Output Voltage
(OSC OUT) .................... -2V::; Your::; v+
(AL OUT, RADIO ENABLE,
All Segment Drivers) ........... V-::; Your ::; V+

ALOUT

C3

ALOFF/TEST

B3

SNOOZE 3

F4

SNOOZE 2

G4

SNOOZE 1

E4

SLEEP FLAG

04

A4

C4

B4

NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress rati ngs only, and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect devi,ce reliability.

NOTE: CONSULT FACTORV IF 24 HOUR TIME
DISPLAY IS DESIRED.

OPERATING CHARACTERISTICS
All testing at 25°C; All numbers stated in absolute value; V+ = 9V unless otherwise specified.

PARAMETER
Supply Voltage Range
Timekeeping Accurate
Supply Current

II

SYMBOL

TEST CONDITIONS

V+
1+

Oscillator Input CurrenH3)

IOSCI

Oscillator Input Capacitance
Oscillator Transconductance
Oscillator Stability

CIN
gm
fSTAB

Alarm Saturation Resistance

RAL(on)

Segment Drive Current
BaCkplane Drive Current

ISEG
IBP

Switch Actuation Current

ISW

MIN.

LIMITS
TYP.

4
V+ =9V
'OSC IN' Connected to V+
'osc our Open Circuit

15

UNIT

18

V

25

pA

0.2
20
10

5V:s VSUPPLY s,15V
P-ch at 10mA
N-ch at 10 mA
VSAT = 0.2V (Both Directions)
VSAT = 0.1V (Both Directions)
Vsw=V+
Vsw = V-

MAX.

pA

25
15

30

pF
Itmho

0.7
220
100

1.0
300
150

ppm

5
20
10
10

30
30

{}
{}

itA
itA
itA
pA

NOTES: 1. This value of power dissipation is that of the package and will not be obtained under normal operating conditions.

7-60

ICM7223A
TYPICAL CLOCK RADIO APPLICATION
BP
26 DISPLAY OUTPUTS

CRYSTAL PARAMETERS:
F'" 32,768 Hz

CL=lOpF
eM '" 2.5 mpF
Rs=20k~~

esc IN
CRYSTAL

RUN/SET I-_~-+_---.J

0

r--~t=----~---I OSC OUT
ICM7223A

5 - 30pF

~-----j 1-----1
O.47J.lF

VR'G
Al. OFF

AL'6~~
SN3

SN2

I-_-+__-<>',,>--_~

SNl
SLEEP

....L..

10----+

TO RADIO

vt

I
I
I
....L..

SUPPLY

~---O
O---~
(DPST PUSH BUTTON)

SNOOZE/SLEEP
PROGRAMMING

SNOOZE

....L..

'-----0 <>----1
(SPST PUSH BUTTON)

SUPPLY CURRENT VB. SUPPLY VOLTAGE

OSCILLATOR STABILITY VB. SUPPLY VOLTAGE
5

50
45

0

40

'1,
I-

iii0:

35

0:

25

"~

20

~

::>

15

'"

10

::>

o

o. 5

I-- DISPLAY OFF; ALL INPUTS FLOATING-

30

~,

V,/
I-

o

0

-

-

~

I/

-0. 5

-,.0
-,.5

V
8

10

12

14

16

18

V
I--

i"----

10

'2

REF

,.

'4

SUPPLY VOLTAGE - V

20

SUPPLY VOLTAGE - V

VOLTAGE REGULATOR OUTPUT
SUPPLY VOLTAGE

ALARM DRIVER OUTPUT CURRENT
VB. OUTPUT VOLTAGE

VB.

P-CHANNEL OUTPUT VOLTAGE - V

-2.0

r-~'·~'T·~1r4_'T2---.J'TO~.~~.~---.J;-~00

~

~

~ -1.9

·Y- """
9V

i

V

10
I
~r:=:.j::7
r+--4-~+-~~~~~~

1-4--+-1--+--+~~~~-+-20

I-

I-

J

I

v

C-f -1~V VF-I-.../",,+-,

o

12v

-+-f-+---.J 40

,- ".

+----1-+--+--+-- 60

N CH

50

..1~l.",~:±::j-t= 15V

I:::::

o -

f;;;;; "", - I - -

--

: W~-++--+_9+Vi--i_f---I---1--_
-l.B

o

8

10

12

14

16

18

00

20

2

4

6

10

12 14

16

18

N- CHANNEL OUTPUT VOLTAGE - V

SUPPLY VOLTAGE - V

7-61

ICM7223A
ALARM OPERATION

NORMAL CLOCK OPERATION
In normal operation hours and minutes are displayed with
the colon flashing at a 1 Hz rate. AM and PM indicators are
provided. The alarm flag will be on if the ALARM OFF input
is at V·, and off with the ALARM OFF input at V+.
Time is displayed in a 12 hour format with AM/PM
annunciators.

The alarm comparator provides a 24 hour alarm by taking
into account AM and PM. When thetime of day and alarm
times agree, and the ALARM OFF input is floating, the
ALARM and RADIO ENABLE outputs are activated; the
alarm sounds and the RADIO ENABLE line goes to V+
Momentarily tying the ALARM OFF input to V+ will silence
both the alarm and the radio. The alarm will automatically
shut off after one minute if ALARM OFF is not used; the
RADIO ENABLE will stay HIGH until either the ALARM
OFF or SNOOZE inputs are used. The SNOOZE input
must be applied within one minute in order to begin a
snooze,cycle.

RUN
MODE
COLON FLASHES
AT 1 Hz RATE

TIME SETTING
To set the time, the RUN/SET switch is placed in the
Time Set position, and the HRS/MIN advance input is
used to advance the hours or minutes. The seconds are
reset to zero and counting is stopped whenever the
minutes are set. The clock will start when the RUN/SET
switch is put back into the RUN position, and while in
the RUN position, inputs from the HRS/MIN advance
switch are disabled to prevent accidental setting.

~+n

TIME
SET

PM

n I---"=~

C +U U

PM

ALARM SETTING
ALARM seT

,+n
D
It U

L.-_~-=-=:...J
HRS ADVANCE
AT 2 Hz RATE

COLON FLASHING
NO CHANGE IN DISPLAY

HRS ADVANCE
AT 2 Hz RATE

COLON STilL FLASHING

MIN.
ADVANCE

COUNTERS START RUNNING
COLON STARTS FLASHING

MIN. ADVANCE
AT 2 Hz RATE

The alarm time is set by switching to Alarm Set, then
~sing the HRS/MIN ADVANCE input to set hours and
minutes. The alarm time 'is displayed only when the
RUN/SET switch is in the Alarm Set position.

SNOOZE OPERATION

MIN. ADVANCE AT 2 Hz
COLON STOP.S FLASHING
SECONDS RESET TO ZERO
TIME HOLD MODE

To begin a snooze cycle, the SNOOZE input must be
momentarily shorted to V+ during the one minute that
the alarm is sounding or the RADIO ENABLE line is
high. When this is done the alarm will be silenced and
the snooze timer started; the alarm will sound again after
the selected snooze time. Unless the ALARM OFF input
is used, the alarm will automatically shut off after two

NOTE: When the HRS/MIN Advance input is activated
there will be a pause of less than one second before the
counters start advancing at a 2 Hz rate.

SNOOZE OPERATION
r -____________________________ ~~~~:S----------------------------~

'----- ~~~~6~ -----'
1X

NOTE: IF ALARM OFF IS lEfT AT

v+ THE

ALARM WILL NOT SOUND 241iOURS LATER.

7-62

ALARM
OFF

ICM7223A
SLEEP TIMER OPERATION

minutes. The RADIO ENABLE will remain on until the
ALARM OFF line is activated, however, a second snooze
cycle can be initiated with the SNOOZE switch. This can
only be done if the SNOOZE is activated while the alarm
is sounding.

TIME seT

The snooze times are programmable in 7 steps from 2 to
14 minutes. Programming is accomplished with binary
coding on the three SNOOZE inputs, as shown in the
following table:
INPUT CODE (1

=

V')

SNOOZE
TIME

SN2

SN1

0

0

0

None

None

0

0

1

2 minutes

8 minutes

0

1

0

4 minutes

16 minutes

0

1

1

6 minutes

24 minutes

1

0

0

8 minutes

32 minutes

1

0

1

10 minutes

40 minutes

1

1

0

12 minutes

48 minutes

1

1

1

14 minutes

56 minutes

PM

•

SNOOZE
BUTTON

The sleep timer may be activated at any time except
during a snooze cycle or when the alarm is sounding.
The sleep timer is started by setting the RUN/SET
switch in the SET position and momentarily activating
the SNOOZE switch. Sleep times are programmed with
the snooze inputs; see table on previous page.
Another method for sleep timer activation is to use a
single DPST pushbutton switch, with one pole connected to the RUN/SET switch and the other to the
common side of the SNOOZE programming switch. The
other side of the switches is tied to V+. (See typical
application, page 3). This method allows the use of a
"dedicated" sleep button, which may be recessed to
prevent accidental activation.

SLEEP
TIME

SN3

When the sleep timer is activated the RADIO ENABLE
output is set high to turn on a radio and the sleep flag
appears on the display. At the end of the programmed
sleep time the RADIO ENABLE output is returned to Vand the sleep flag disappears.

HRS
OFF
MINUTES
ADVANCE / 1~\ ADVANCE

ZZZ

BE',tBB

8 TO 56
MINUTES

(SIMULTANEOUS
PUSH)

r-r,-v-:J
rr-

r'

>-

RUN

-

I--

TIME /

3 POSITION SWITCHES

ALARM

~.~

I--

rr27 UNES
TO DISPLAY

I-I-I-I--

34

I-- N.C.

D

1

1
5-3~F

+J-

-1

---

ICM7223A

rr-

OFF

RADIO
__~ ON

9 VOLTS

ALARM
TRAfSDUCER

I--

IO~

ALARM

r-

OFF

.-'L.

I-I--

rr-

I---I--

I--

Q

ALARM

~-b.::!~'\
)

SLEEP

..:r..,- -...:r:...

~II

I

~

)

WAKE-UP
SELECT

rADIO

10K

D

jr-...
~

TYPICAL CHIP CURRENT
IS 1SJ.lA W ITH DISPLAY

'I 'I

SNOOZE AND SLEEP
PROGRAMMING----<:
THE PROGRAMMING SWITCH CAN BE AN
8 POSITION BINARY SLIDE SWITCH OR AN
OCTAL THUMBWHEEL TYPE

~ ~

SNOOZE

....:::r:...

ICM7223A 12HR LCD SNOOZE ALARM CLOCK RADIO CIRCUIT WITH SLEEP TIMER.
(9 volt single battery operation)

7-63

I

+
RADIO

.O~OIL

ICM7223A
LOW BATTERY INDICATION
The ICM7223A is provided with a completely
integrated low battery indicator. When the supply
voltage drops below about 5.6V the display will begin
flashing at a 1 Hz rate. Actual trigger points vary from
chip to chip, but will usually be in the range of 5.2V to
6V. Time keeping will not be affected.
CHIP RESET
Power up reset is not provided on the 7223A, as interaction between the V+ and V- inputs and the voltage
regulator in noisy environments could cause spurious
resetting. Resetting the circuit to a known state, 1:00
AM, can be accomplished by momentarily connecting
the ALARM OUT output to V+; this can be done with a
NO SPST switch. This same method may be employed
to clear the 7223A in the event that it powers up in an
illegal state. The switch should be made accessible to
the user fOr use when changing batteries.
TEST MODE OPERATION
This mode, provided for high speed automatic testing, is
entered by shorting ALARM OFF to V-. The minutes will
then advance at a 4.27 Hz rate and setting can be
accomplished by the application of a digital input to the
hrs - mins advance input. The counter will then advance
once per pulse. Note that in the test mode there is no
debounce protection on.the HRS/MINS ADVANCE
input.
ALARM AND DISPLAY TEST
If the ALARM OFF and SNOOZE buttons are pushed
simultaneously, all segments of the display will be
turned on and the alarm will sound, while none of the
time counter contents are disturbed.
OSCILLATOR
The oscillator of the ICM7223A is designed for low
frequency operation at very low currents from a 9 volt
supply. The oscillator is of the inverter type with a
nonlinear feedback resistor included on chip, which
has a maximum resistance under startup conditions.
The nominal load capacitance of the crystal should be
less than 15 pF, typically 12 pF. In specifying the crystal, the mommal capacitance, series resistance and
tuning tolerance have to be compatible with the characteristics of the circuit to insure startup and o')')ration
over a wide voltage range under worst case cunJitions.

where
Rs
f
M
Co
CIN
COUT
CL
Cm

=
=

=
=
=

Series Resistance of Crystal
Frequency of the Crystal
Frequency Shift from Series Resonance
Frequency
Static Capacitance of Crystal
Input Capacitance
Output Capacitance
Load Capacitance of Crystal
Motional Capacitance of Crystal

The (calculated) gm required for startup should not
exceed 50% of the gm guaranteed for the device.
ALARM DRIVE
The ICM7223A will directly drive any suitable audio
transducer (piezoelectric
ceramic, or magnetic
speaker) with a peak frequency response of 4 kHz with
v+ = 9V and a peak current 01 10 mAo The volume
should be more than adequate; no buffering should be
required.
POWER SUPPLY CONSIDERATIONS
The ICM7223A contains an on-chip CMOS voltage
regulator which operates all timing and counting logic
Circuitry at about 1.8 to 2.0V below V+. This provides
low current operation over a voltage range of 4-15V
and also improves oscillator stability. The LCD
maximum operating voltage willbe the limiting factor
in most cases, therefore the supply voltage will rarely
exceed 12V.
For applications which involve power supplies with
high noise levels or transients, it will be necessary to
provide supply filtering. The voltage regulator output
(V-REG) should be decoupled to V+ with a 0.22/LF to
0.47/LF capacitor, and the V+ and V- lines should be
low-pass-filtered using a 300n resistor and 100/LF capacitor. Note that a zener diode in parallel with the filter
cap will limit voltage spikes to 15V, and should be
included if the common "24V survival" required for
automotive use is desired.

300n

The following expressions can be used to arrive at a
crystal specification:
Tuning range
~ =
f

Cm
•
2 (Co + CLI'

C _
.L -

,5V

~

CIN COUT
CIN + COUT

gm required for startup
gm = 417"212 CINCOUT

Rs

(1 + ~~)

7-64

_ _ _ _ _ _~~_ _4 -_ _ _ _ _ _-OV-

IID~Dll

ICM7223A
DISPLAY

r----------I
I

LAD-DOl
3411
nODl
Cll202

~~~

8~ 8~ f 8~ 8~
Fl

I
I
I
I
I

MLC406
737-01

D

~fM]

I
I
I
MOTOROLA
BECKMAN
LAOCOR
HAMLIN
TIMEX
COCKROFT

--------.-~-----,

Bl

F2

82

F3

F4

B3

84

~

~

~

0

I
I
I
I
I

o8BBf e8 BB
~

C§D

I
~
~
~
~
L
_______
_________________

C

I
I

P

F

G

E

0

1111

C

II

A

f

11122

,

0

C

iii

A

Z

2

)

2

2

L

F

G

33

DISPLAY FONT
NUMBERS

COCKROFT CII201

7-65

foe

II

ill' F

J

3

34444444

3

J

G

E

0

C

II

A

Z

B
E

, ,
l

I

I
I
I

~

ICM7223A
CHIP TOPOGRAPHY
ICM7223A
.3
+

20

40

60

80

100 112

(0.508) (1.016) (1.524) (2.032) (2.54)(2.84)

CHIP DIMENSIONS: 112 x 143 mils (2.84 x 3.63 mm)

7-66

ICM7223VF
3·1/2 Digit Vacuum
Fluorescent Clock Circuit
With Snooze Timer
and Sleep Timer
FEATURES
• 3-1/2 digit display with AM/PM, sleep timer, and

GENERAL DESCRIPTION
The ICM7223VF is a fully integrated 3-1/2 digit Vacuum
Fluorescent clock circuit with 24 hour alarm, and sleep
and snooze timers. For high accuracy and low power
consumption a 32.768 kHz quartz watch crystal is used
as the time base, while the number of external components has been reduced to a minimum. The vacuum
fluorescent display outputs are static, or nonmultiplexed, thereby eliminating radio frequency interference (RFI).
.

alarm flags
• Direct alarm drive with complex (cricket) alarm tone
plus radio enable for clock radio applications
• 8 minute repeatable programmable snooze
• Programmable sleep timer
• Wide operating voltage range • Low current -

4 to 15 volts

12/LA @ 12V with display off

The time keeping and alarm time counters are split
during setting, allowing hours and minutes to be set
independently, each at a 2 Hz rate. A 'time hold' mode is
entered when setting minutes; seconds are automatically reset to zero. The clock starts when the RUN mode
is entered; this permits synchronization of the clock to
the nearest second. Seconds are not displayed.

• On-chip fixed oscillator input capacitor
• Uses standard 32.768 kHz crystal
• Display control blanks display for auto and travel
clock applications

ORDERING INFORMATION

Pari
Number

Temperature
Range

Package

ICM7223VFIPL

-20 0 C to +85 0 C

40 Pin Plastic DIP

ICM7223VF/D

-20 0 C to +85 0 C

Dice

The alarm employs a snooze timer that may be programmed from 2 to 14 minutes in two minute increments;
the sleep timer may be set from 8 to 56 minutes in 8
minute increments. The alarm outputs consist of a complex (cricket) alarm tone to directly drive a speaker or
piezoelectric transducer and a radio enable output which
allows control of a clock radio.
The ICM7223VF is fabricated using Intersil slow
threshold metal gate CMOS process for minimum cost
and long battery life. Current drain at 12 volts is
typically 12/LA with a maximum of 25/LA (display off).
•

r--OSCIN - - - - - - - - - - - - . I I I
BLOCK
DIAGRAM

OSCOUT

25pF

J

c::~~-{r-:.~::~~~~~:::-:.l~~~1~~dr-SE-T-A-NO-OI-SP-lA-yl---o
CONTROL

12/24

[}--~-'::=l==-~

1 Hz

RUN/SET

1-----1D ~~~·~~~E

LOGIC

r----l----O ALARM OFF
TEST

ALARM
CONTROL
LOGIC

1--11:»---10 ~~~~~E

L._-.__J--P--o

26 SEGMENTS OPEN
DRAIN P-CH OUTPUTS

v+

v-

(GNOI

(-12VI

SN3

7-67

SN2

SN1

AL OUT

ICM7223VF
ABSOLUTE MAXIMUM .RATINGS

PIN CONFIGURATION (OUTLINEDRAWINGPL)
B1 +Cl

PM

F2

AM

G2

ALARM FLAG

E2

DISPLAY CONTROL

02

HRS/MINS ADV

C2

RUN/SET

B2

VREG

A2

osc IN

COLON

OSCOUT

F3

V+(GNO)

G3

V'

E3

RADIO ENABLE

A3+03

Storage Temperature ............. -55°C to +125°C
Operating Temperature ............. -20°C to +85°C
Power Dissipation l11 ••••••••••••••••••••••• 500 mW
Supply Voltage (V+ - V-) ...................... 18V
Input Voltage
(OSC IN. SN1. SN2, SN3) ..... -2V:5 VIN:5 V+ + 0.3V
(RUN/SET. HRS/MIN ADV.
.
AL OFFITEST) ...... V- - 0.3V :5 VIN :5 V+ + 0.3V
Output Voltage
.
OSC OUT . .. . .. . .. . . .. . . .. . .. -2V:5 VOUT :5 V+
AL OUT, RADIO ENABLE ....... V - :S VOUT :S V +
All Segment Drivers ........ V+- 35V :S VOUT :S V +

ALOUT

C3

AL OFF/TEST

B3

SNOOZE 3

F4

SNOOZE 2

G4

SNOOZE 1

E4

SLEEP FLAG

04

A4

C4

B4

NOTE: CONSULT FACTORY IF 24 HOUR
DISPLAY IS DESIRED.

NOTE: Stresses above those listed under Absolute Maximum
Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

TIM~

OPERATING CHARACTERISTICS All testing at 25°C; All numbers stated in absolute value
LIMITS
PARAMETER
Supply Voltage Range
Timekeeping Accurate

SYMBOL
V+

Supply Current
Supply Current Display ON!21

1+

Segment Output
Saturation Resistance

RSEG

Oscillator Input
Capacitance

CIN

Osciliator'Stability
Alarm Saturation Resistance
Switch Actuation Current

TEST CONDITIONS

MIN.

TYP.

4
Display OFF V+ - V' =12V
V+ -.~ 12\1. Display"
Test. NEC LD8164
los = 1mA P-ch

12

V

MAX.

UNIT

15

V

25

20

p.A
mA

3
1000

1500

!1

25

30

pF

ISTAB

_.
5V $ VSUPPLY $ 15V

0.7

1.0

ppm

RAL(on)

P-ch at 10mA

220

300

!1

N-ch at 10mA

100

150

!1

. '!sw = V+

10

30

p.A

Vsw=V

10

30

p.A

Isw

NOTES: 1. This value of power dissipation is that of the package and will not be obtained under normal operating conditions.
2. Chip current plus display anode current only; does not include display filament or grid currents.

7·68

ICM7223VF
TYPICAL CLOCK RADIO APPLICATION
26 DISPLAY OUTPUTS

CRYSTAL PARAMETERS:
F '" 32,768 Hz
Cl'=10pF
eM '" 2.5 mpF
Rs "" 20 kS2

, - - - - ; ase IN

CRYSTAL

RUN/SET t---~-t----'

0

,----"I-F-----<>----I

OSC OUT
[GM 7223 VF

5 - 30pF

+------1 f - - - - - I

DISPLAY

c~~~~~~ f-_-+_--'O:::N;..,,"(,..:O;::Fc-F_ ....

VREG

O.47/lF

ALOFF

AL'6~~
SN3

SN2

r--+----O-"(>-----1

SN1
SLEEP

.......
10------.

TO RADIO
v t SUPPLY

I
I

.......0----+
I

,----0

(OPST PUSH BUTTON)

SNOOZE/SLEEP
PROGRAMMING

SNOOZE

.......0-----+

L-_-<>

(SPST PUSH BUTTON)

SUPPLY CURRENT

VS.

SUPPLY VOLTAGE

OSCILLATOR STABILlTYvs. SUPPLY VOLTAGE
I_

50
45

i

40

"i
I

...

fii
a:
a:

""
~
~

35

0_

~

30
DISPLAY OFF; ALL INPUTS FLOATING

2.
20

,

I.
10

,/f"

,/

'"

+-

2

4

8

10

12

14

16

18

----

-- - -

r----- - -

~
-0_ 5

.......... V
I" REF

--

-1_ 0

100

•

I

~

I
I

•

I_ 0

-1_ 5

20

10

SUPPL V VOLTAGE - V

12

14

16

SUPPLYVOLTAGE-V

ALARM DRIVER OUTPUT CURRENT
VS. OUTPUT VOLTAGE
SEGMENT DRIVER OUTPUT CURRENT
VS. DRAIN VOLTAGE

P·CHANNEL OUTPUT VOLTAGE - V

10

1

1

1

1

I---I--- !--P.CH VSUPPLV '" 12V

-,...- I -

/v

/

'"E

...I

V
1

0

I

~

\

"G

V
o

2

4

6

8

10

12

14

16

18

20

P·CHANNEL SEGMENT OUTPUT VOLTAGE - V

N- CHANNEL OUTPUT VOL TAGE - V

7-69

NORMAL CLOCK OPERATION

SNOOZE OPERATION

In normal operation hours and minutes are displayed with
the colon flashing at a 1 Hz rate. AM and PM indicators are
provided. The alarm flag will be on if the ALARM OFF input
is floating, and off with the ALARM OFF input at V+.
Time is displayed in a 12 hour format with AM/PM
annunciators.
RUN MODE

To begin a snooze cycle, the SNOOZE input must be
momentarily shorted to V+ during the one minute that
the alarm is sounding or the RADIO ENABLE line is
high. When this is done the alarm will be silenced and
the snooze timer started; the alarm will sound again after
the selected snooze time. Unlessthe ALARM OFF input
is used, the alarm will automatically shut off after two
minutes. The RADIO ENABLE will remain on until the
ALARM OFF line is activated, however, a second snooze
cycle can be initiated with the SNOOZE switch. This can
only be done if the SNOOZE is activated while the alarm
is sounding.

ALARM
FLAG

A;,

~+

nn

PM' C +U U
COLON FLASHES
AT 1 Hz RATE

ALARM OPERATION

The snooze times are programmable in 7 steps from 2 to
14 minutes. Programming is accomplished with binary
coding on the three SNOOZE inputs, as shown in the
following table:

The alarm comparator provides a 24 hour alarm by taking
into account AM and PM. When the time of day and alarm
times agree, and the ALARM OFF input is floating, the
ALARM and RADIO ENABLE outputs are activated; the
alarm sounds and the RADIO ENABLE line goes to V+.
Momentarily tying the ALARM OFF input to V+ will silence
both the alarm and the radio. The alarm will automatically
shut off after one minute if the ALARM OFF is not used; the
RADIO ENABLE will stay HIGH until either the ALARM
OFF or SNOOZE inputs are used. The SNOOZE input
must be applied within one minute in order to begin a
snooze cycle.

INPUT CODE (1

ALARM SETTING
ALARM SET

= V')

SLEEP
TIME

SNOOZE
TIME

SN3

SN2

SN1

0

0

0

None

None

0

0

1

2 minutes

8 minutes

0

1

0

4 minutes

16 minutes

0

1

1

6 minutes

24 minutes

1

0

0

8 minutes

32 minutes

1

0

1

10 minutes

40 minutes

1

1

0

12 minutes

48 minutes

1

1

1

14 minutes

56 minutes

SLEEP OPERATION

HRS ADVANCE
AT 2 Hz RATE

The sleep timer may be activated at any time except
during a snooze cycle or when the alarm is sounding.
The sleep timer is started by setting the RUN/SET
switch in the SET position and momentarily activating
the SNOOZE switch. Sleep times are programmed with
the snooze inputs; see table on previous page.
Another method for sleep timer activation is to use a
single DPST pushbutton switch, with one pole connected to the RUN/SET.switch and the other to the
common side of the SNOOZE programming switch. The
other side of the switches is tied to V+. (See typical
application, page 3). This method allows the use of a
"dedicated" sleep button, which may be recessed to
prevent accidental activation.

MIN. ADVANCE
AT 2 Hz RATE

The alarm time is set by switching to Alarm Set, then
using the HRS/MIN ADVANCE input to set hours and
minutes. Th.e alarm time is displayed only when the
RUN/SET switch is in the Alarm Set position.
SNOOZE OPERATION

r----------------------------21~~~~s----------------------------,

NOTE: IF ALARM OFF IS LEFT AT v+ THE'
ALARM WILL NOT SOUND 2'~HOURS LATER.

'--~--- ~~W6~
lX

7-70

----'

ALARM

OFF

IID~DI1.

ICM7223VF

minutes are set. The clock will start when the RUN/SET
switch is put back into the RUN position, and while in
the RUN position, inputs from the HRS/MIN advance
switch are disabled to prevent accidental setting.

When the sleep timer is activated the RADIO ENABLE
output is set high to turn on a radio. At end of the
programmed sleep time the RADIO ENABLE output is
returned to V-.

NOTE: When the HRS/MIN Advance input is activated
there will be a pause of less than one second before the
counters start advancing at a 2 Hz rate.

TIME SET

8-56 MINUTES

SNOOZE

DISPLAY
The ICM7223VF is designed for use only with 12V
direct drive (non-multiplexed) 3% digit vacuum(fluorescent displays such as the NEC LD8164 or equivalent.
(But see "LED Display Driving" under DESIGN
CONSI DERATIONS.)

ALARM OFF

TIME SETTING

DESIGN CONSIDERATIONS

To set the time, the RUN/SET switch is placed in the
Time Set position, and the HRS/MIN advance input is
used to advance the hours or minutes. The seconds are
reset to zero and counting is stopped whenever the

DISPLAY CONTROL
This input allows the display to be blanked (turned off)
when low current operation is desirable, such as when
an auto clock is being used with the engine turned off.
For normal operation connect DISPLAY CONTROL to
V+; to turn off display allow the input to float. A SPST
switch can be used for those times when it is desired to
turn on the display with the engine off.

nn
l +UU
+

TIME
SET

PM
COLON STILL FLASHING
NO CHANGE IN DISPLAY

HRS ADVANCE
AT 2 Hz RATE
COLON STILL FLASHING

-L

DISPLA Y CONTROL - - 0 0 - -

MIN.

v+

ADVANCE

PM
COUNTERS START RUNNING
COLON STARTS FLASHING

1:56

MIN. ADVANCE AT 2 Hz
COLON STOPS FLASHING
SECONDS RESET TO ZERO
TIME HOLD MODE

300n

15V

ZENER

12V
AUTO
BATTERY

AUTO

DISPLAY

IGNITION
SWITCH

CONTROL

100l-'F

r - -------- -- -

v+

-- -- --- ---- ,

I ICM7223 VF

7.5 kfl

I
I

DISPLAY
BRIGHTNESS
CONTROL

I
I_CHIP

I
I

BRIGHT

_____ .1

DIM
(1/2 BRIGHTNESS}
APPROX.

..------- SEGMENT ANODES

~~--~-+--+-~--~--+-~

' - -_ _ _ _-=G"'RI.=.D+_ _

_

_

_

_

_

_

_

_

_

_

_

_

_

_

V.F. DISPLAY
NEC LDS164

___________ FILAMENT
SUPPl Y
SOmA _ _

FILAMENT

NOTE: ONLY ONE DIGIT
SHOWN CONNECTED

62$1 lW
6.8V

ZENER

ICM7223VF VACUUM FLUORESCENT DISPLAY CONNECTION EXAMPLE; AUTO CLOCK APPLICATION

7-71

ICM7223VF
-lED DISPLAY DRIVE
It is possible to drive high efficiency common cathode
LED displays with the 7223VF as long as the total display
current does not exceed 1OOmA (or 4mA per segment).
as excessive on-chip heating may occur. Operation is
not guaranteed for extended periods. since the package power dissipation limits are likely to be exceeded.
When driving LED displays with the 7223VF. use of the
DISPLAY CONTROL as a "time demand" is highly
recommended.
CHIP RESET
Power up reset is neit provided onthe 7223VF. as interaction between the V+ and V- inputs and the voltage
regulator in noisy environments could cause spurious
resetting. Resetting the circuit to a known state. 1:00
AM. can be accomplished by momentarily connecting
the ALARM OUT output to V+; this can be done with a
NO SPST switch. This same method may be employed
to clear the 7223VF in the event that it powers up in an
illegal state.

7

TEST MODE OPERATION
This mode. provided for high speed automatic testing. is
entered by shorting ALARM OFF to V-. The minutes will
then advance at a 4.27 Hz rate and setting can be
accomplished by the application of a digital input to the
hrs - mins advance input. The counter will then advance
once per pulse. Note that in the test mode there is no
debounce protection on the HRS/MINS ADVANCE
input.
ALARM AND DISPLAY TEST
If the ALARM OFF and SNOOZE buttons are pushed
simultaneously. all segments of the display will be
turned on and the alarm will sound. while none of the
time counter contents are disturbed.
OSCILLATOR
The oscillator of the ICM7223VF is designed for low
frequency operation at very low currents from a 12 volt
supply. The oscillator is of the inverter type with a
nonlinear feedback resistor included on chip. which
has a maximum resistance under startup conditions.
The nominal load capacitance of the crystal should be
less than 15 pF. typically 12 pF. In specifying the crystal. the motional capacitance. series resistance and
tuning tolerance have to be compatible with the characteristics of the circuit to insure startup and OPeration
over a wide voltage range under worst case conditions.

The following expressions can be used to arrive at a
crystal specification:
Tuning range
~ =
f

Cm
•
2 (CO + CLI'

C _
L -

gm required for startup
I

gni =

41T212 GIN GOUT

Rs

CIN COUT
GIN + GOUT
2

(1 + ~~)

where
Rs
f
al

Series Resistance of Crystal
Frequency of the Crystal
Frequency Shift from Series Resonance
Frequency
Co
= Static Capacitance of Crystal
CIN = Input Capacitance
COUT = Output Capacitance
CL
= Load Capacitance of Crystal
Cm = Motional Capacitance of Crystal

The (calculated) gm required for startup should not
exceed 50% of the gm guaranteed for the device.
ALARM DRIVE
The ICM7223VF will directly drive any suitable audio
transducer (piezoelectric ceramic. or magnetic
speaker) with a peak frequency response of 4 kHz with
V+ = 12V and a peak current of 10 mA. The volume
should be more than adequate; no buffering should be
required.
.
POWER SUPPLY CONSIDERATIONS
The ICM7223VF contains an on-Chip CMOS voltage
regulator which operates all timing and counting logic
circuitry at about 1.8 to 2.0V below V+. This provides
low current operation over a voltage range of 4-15V
and also improves oscillator stability.
For applications which involve power supplies with
high noise levels or transients. it will be necessary to
provide supply filtering. The voltage regulator output
(V-REG) should be decoupled to V+ with a 0.22,uF to
0.47,uF capacitor. and the V+ and V- lines should be
low-pass-filtered using a 3000 resistor and 100,uF capacitor. Note that a zener diode in parallel with the filter
cap will limit voltage spikes to 15V. and should be
included if the common "24V survival" required for
automotive use is desired.

7·72

ICM7223VF
TYPICAL CLOCK RADIO APPLICATION

ICM7223 VF
TYPICAL AUTO CLOCK/RADIO
APPLICATION

12V
POWER
SUPPLY

3300
ZENER ( .. 15V

+--_ _ _f_'III---4+" -

bRADIO

I~

r-<>-- - -

I AL SET

I

"r

CRYSTAL

-

35

NPN

30

PM
INDIG.

I

TRANSDUCER

ON
RADIO /

I OFF
RADIO

25

21

ICM7223 VF

6.BV'::i~

10

-

-

-

20

15

-

I

--

PM

I I

I

G

G •. F

R
I
D

1

1

I

I
A
1

F
2

A
2

B

2

G

C

R

0

I
D

0

F
3

L

A
3
D
3

r--

A
4

B

G

3

F
4

4

R
I
0

G
4

E
4

0
4

C
4

B

N

G

F
I
L

R
I
0

E
1

D
1

C
1

G
2

E
2

I I

BRIGHT

DIM

6

0
2

C
2

G
3

E
3

C
3

G
R
I
0

II

DISPLAY BRIGHTNESS

'y

20k.Q

7-73

TOV+

DISP

CONT

NEe LD8164 V.F. DISPLAY

.n

NPN

i ~~> I jf ~r--02E_~

f- -

B20n

1W

A

Q

DJ~~

6Bn

-,--0--- OFF

~O+~-~!-~--Q-P-+-!.TI-M-:-:-:-T~_+~-+~-L~AR-M-'--~D
1

-+_____
MIN
ADV

_____
r

0

F
I
L

ICM7223VF
TYPICAL DISPLAY (FIP5E15S)
Other displays (by NEG):
FIP 588S
LD 8196
LD 8164

_
t
"-_JVlIv-_ _ _-.,-_ _ _- '
loon

OUT

ZENER DIODE HAS TYPICAL
BREAKDOWN VOLTAGE OF 6.3 VOLTS.

TYPICAL CONNECTION

PIN CONFIGURATION (outline dwg PA)

OSC IN

v-

OSC OUT

Ne

32kHz OUT
COUT

NC

22pF
NOMINAL
VALUE

NC
TOP VIEW

V'
PIN 1 IS DESIGNATED BY EITHER A DOT OR A NOTCH.

32kHz
OUTPUT

f""4,194,304Hz
As = 35&1

ORDERING INFORMATION

eM'" 10mpF
CO"" 3.5pF

Order devices by following part number: ICM7241

Cl. '" 12pF

7-75

ICM7241
TYPICAL OPERATING CHARACTERISTICS
V+

= 1.5V,

fosc

= 4,194,304

Hz, TA

= 25°C,

Parameter

unless otherwise specified. All numbers in absolute values.
Symbol

Conditions

Supply Current

1+

Guaranteed Operating Voltage Range

V+

-20°C S to S 70°C

P-Ch Output Saturation Resistance

RSAT

lOUT

Min.

= .5mA
lOUT = .5mA

RSAT

Oscillator Stability

fSTAB

1.2V < V+ < 1.6V
CIN = COUT = 15pF

Oscillator Start-Up Time

tstart

V+

Ratings may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device
at these orany other conditions above those indicated in the

Max.

Unit

40

70

/J- A

1.2

N-Ch Output Saturation Resistance

NOTE: Stresses above those listed under' Absolute Maximum

Typ.

1.8

V

680

2

kO

240

1

1

= 1.2V

1.0

SUPPLY CURRENT vs. SUPPLY VOLTAGE

OSCILLATOR STABILITY vs. SUPPLY VOLTAGE
CRYSTAL PARAMETERS
AS SPECIFIED ON PAGE 1.

CRY-STAL PARAMETERS
ASSPECIFIEDONPAGE 1

120

100

f-

a;

""::>
<.J

~
~

1

80

60

40

20

o

---

1.2

l--

1.3

1.4

1.5

.

--

f'-.-- r--

~
CIN '" COUT = 22pF

1.6

1

i'--

-2

1,7

sec

operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

140

1

kO
ppm

1.2

1.8

SUPPL V VOLTAGE (V)

1.3

1.4

1.5

1.6

1.7

SUPPLY VOLTAGE (V)

OUTPUT CURRENT (SOURCE) vs.
OUTPUT SATURATION VOLTAGE

30~-----+------~------r------1

20

OUTPUT SATURATION VOL rAGE (V)

7-76

1.8

ICM7245
Quartz Analog
Watch Circuit
FEATURES

GENERAL DESCRIPTION

• Very low current consumption: 0.4f.LA at
1.55 volt typical

The ICM7245 is a very low current, low voltage
microcircuit for use in analog watches, It consists of an
oscillator, dividers, logic and drivers necessary to
provide either bipolar or unipolar drive for minimumcomponent count watches, The oscillator is extremely
stable over wide ranges of voltage and temperature,
and thus combines high accuracy with low system
power. The ICM7245 is fabricated using Intersil's low
threshold metal-gate CMOS process,

• 32 kHz oscillator requires only quartz crystal
and trimming capacitor
• Bipolar stepper drive with low output ON resistance:
200 ohms maximum (7245 A/B/O/E/F)

The inverter oscillator contains all components onchip except for the tuning capacitor and quartz crystal.
The binary divider consists of 15 stages, the last 5 of
which may be reset. If a reset (stop) occurs during an
output pulse, the duration of the pulse is not affected,
When the reset is released, the first output occurs
approximately 1 second later. For the bipolar version,
memory reset logic is included to make sure the first
pulse after a "stop" occurs on the opposite output from
the one just before the "stop",

• Unipolar stepper drive with very low output ON
resistance: 50 ohms maximum (7245U)
• Extremely accurate: oscillator stability
typically 0.1 ppm
• STOP function for easy time synchronization
• TEST input for'highspeed testing

The bipolar bridge output consists of two large
inverters, normally high, The output ON resistance of
the P and N channel devices in series is 200.0 maximum
@ 1 mA, In unipolar operation, the output is made up of
a single normally high inverter, The ON resistance of
the N-channel device is 50.0 maximum @ 3 mA.

• Wide temperature range: -20°C to +70°C
• On chip fixed oscillator capacitor: 20pF ±20%

TABLE OF OPTIONS
Device
Number
ICM7245A
ICM7245B
ICM7245D

Blpolar/
Unipolar

Pulse
Width
(ms)

Pulse
Frequency

Oscillator
Capacitor

B

9,7

1Hz

COUT

B
B

7,8
7,8

1Hz
0,1Hz
(1 pulse/
10 seconds)

PIN CONFIGURATION
v'
MOTOR 2

C,N

ICM7245E

B

7,8

ICM7245F

B

7,8

0,05Hz
(1 pulse/
20 seconds)

C,N

ICM7245U

U

3,9

1Hz

C,N

C,N

,...----..

8

L2

OSCDUT

7

I ase IN

ICM7245

COUT

0,0833Hz
(1 pulse/
12 seconds)

...--1

(OUTLINE DRAWING BA)

MOTOR 1

I

3

6

I TEST

STOP

I

4

5

I

ORDERING INFORMATION

T
ICM7245 U

BA

1

_

'
_ ' ---------

PACKAGE
BA=8PINFLATPACK

~2EO~~·TRoA!0~;c
ELECTRICAL OPTION

DEVICE TYPE

ORDER DICE BY FOLLOWING PART NUMBER:
ICM7245A/D

LSELECT OPTION

7-77

B

ICM7245
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent device failure. These are
stress ratings only and functional operation of the devices at
these or any other conditions above those indicated in the

Storage Temperature ........... -40°C to +125°C
Operating Temperature .... ,.;.... -20°C to +70°C
Power Dissipation (Note 1) ................ 25 mW
Supply Voltage (V+ - V-) .............. 3.0 volts
Lead Temperature (Soldering, 10 sec) ..... 300°C
Input Voltages ...........

operation sections of this specification is not implied.

Exposure to absolute maximum rating conditions for
extended periods may cause device failures.

V- -0.3 < VIN < v+ +0.3

Note 1.:. This value of power dissipation refers to that of the package and will not normally be obtained under normal operating conditions.

TYPICAL OPERATING CHARACTERISTICS
V+ -

V-

= 1.55V,

fosc

= 32,768 Hz,

= 25°C"

circuit in Figure 1, TA

unless otherwise stated.

Numbers are in absolute values.

PARAMETER

SYMBOL

1+

Supply Current

TEST CONDITIONS

MIN.

TYP.
0.4

No Load

MAX. UNITS
0.8

pA

Operating Voltage

V+- V-

O°C < TA < 50°C

1.2

Oscillator Transconductance

gm

Start-up

15

Oscillator CapaCitance

Cose

STOP I nput Current

ISTOP

TEST Input Current

ITEST

10

Oscillator Stability

"A
ppm

Supply Current During Stop

fSTAS
1+

'STOP'Connected to V+

1.0

"A

Output Saturation Resistance

Ro

Bipolar (N-CH.

200

Output Saturation Resistance P-CH

RO-p

Unipolar IL

Output Saturation Resistance N-CH

RO-N

Unipolar IL

n
n
n

16

!:J.(V+-V

20

) = 0.6V

+ P~CH)

=3
=3

1.8

V

24

"mho
pF

0.3

"A

0.1
IL

= 1 mA

mA

200

mA

50

TYPICAL WATCH CIRCUIT

!
1

/

5-25 pF

=D
2

00.0"9

CRYSTAL
PARAMETERS

8

7

f

T

leM
72458

3

-:;
STOP

4

5

Figure 1.

7·78

= 32768 Hz

CL = 10 pF
CM = 2.5 mpF
Rs = 20Kn

32768 Hz
CRYSTAL

r-

l,55V

ICM7245
WAVEFORMS
(ICM7245U)

(ICM7245B)
I \-',-----.~
MOTOR1U

1 '5Ec1

r-r ld-

MOTOR1/MOTOR~\
STOP

---1

1-'5EC-1

~

u..-----l

MOTOR 2

-1i--

r

3 9m
,
.

STOP

•

78m ,

-----'

.

\ - ' SEC

TYPICAL OPERATING CHARACTERISTICS
SUPPLY CURRENT AS
A FUNCTION OF SUPPLY VOLTAGE

BRIDGE OUTPUT CURRENT
AS A FUNCTION OF LOAD VOLTAGE

1.6

6
TA

1.4

,,1 25oC

-

RL "'" 60S!
GOUT" 20 pF

(TA '" 25°C)

1.2

1
f-

~

a:
a:

12

0--""""

1.0

::l

.8

~

.6

8

"

--

V+-V-=1,BV

"""

""
-- '"""\ \
I

Vt

.4

-

......

V- "" 1.2V

~

-.........

.2

o

o
1.2

1.4

1.6

1.8

2.0

r--

~1.55V

6

::l

'"

J-r-

14

o

.4

SUPPLY VOLTAGE (VOLTS)

.8

~

1.2

1.6

BRIDGE LOAD VOLTAGE (VOLTS)

OSCILLATOR STABILITY AS
A FUNCTION OF SUPPLY VOLTAGE
.3

f------+---+----+-----j

.2

f------+---+----+----'----j

a:

_.1

f----+---+----+------1

~

-.21-----+---+-----+-----1

TA '" 25°C
GOUT'" 20 pF

~

1.2

1.4

1.6

1.8

SUPPl Y VOL TAGE (VOLTS)

7-79

2.0

2.0

ICM7245
APPLICATION NOTES

where

OSCILLATOR
The oscillator of the ICM7245 is designed for low
frequency operation at very low current from a 1.55 volt
supply. The oscillator is of the inverter type, using a
non-linear feedback resistor having maximum resistance under start-up conditions. The nominal load
capacitance of the crystal should be less than 12 pF,
with a preferred range of 7-10 pF. In specifying the
crystal, the motional capacitance, series resistance
and tuning tolerance must be compatible with the
characteristics of the circuit to insure start-up and
operation over a wide voltage range under worst case
conditions.

Rs
f

= Series Resistance of Crystal
= Frequency of the Crystal
= Frequency Shift from Series Resonance

Co
CIN
COUT
Cl
Cm

= Static Capacitance of Crystal

The following expressions can be used to arrive at a
crystal specification:
Tuning Range
~f =

f

Cm
. C _ CIN COUT
2(Co + Cl)' l - CIN + COUT

gm required for start-up
gm = 471'2f2 CIN COUT Rs ( 1 +

g~

r

~f

. Frequency
= Input Capacitance
= Output Capacitance
= Load Capacitance
= MotiQnal Capacitance of Crystal

The gm required for start-up calculated should not
exceed 50% of the gm guaranteed for the device.
TEST POINT
The TEST input, when connected to V-, causes the
ICM72458/U to speed-up the outputs by 16 times. On
long period output versions (12, 20, 60 sec) t~e speedup factor will be larger. This allows easy testmg of the
finished watch module. The pulse width is not affected
by the speed-up of the pulse frequency.
CUSTOM VERSIONS
The ICM7245 may be modified with alternative metal
masks to provide different number of dividers, various
pulse widths, and different output configurations.
In addition, MOS capacitors .on-chip up to a total of
50 pF may be connected to either the input and/or the
output of the oscillator. Consult your Intersil
representative or the factory for further information.

CHIP TOPOGRAPHY

DIE SIZE = 62.5 x 62.5 MilS (1.58 x 1.58 mm)
BOND PAD SIZE = 5x5 MilS (.127 x .127 mm)

7-80

Packaging Dimensions
Thermal Resistance
High Reliability Processing
Application Note Summary
EValuation (EV) Kit Information.
Chip Ordering Information
Intersil Part Numbering System
Sales Offices, Distributors, and Representatives

8-11
8-12
8-20

PACKAGE OUTLINES

All dimensions givE1nin inches and (millimeters).

--(~:::~:~~)
0178-0191
(4:521-4:.51) ....... ' - 1

(::!!:. MAX

0.188-0.210
(4.775-5.334)

SEATlNG~.LA.NEn

I
-t
PLANE

f

-

LLffiS
,!:f~ ~ 0

SEATING

oJ

MAX

J

0.500

:'=:'~~)-11'"

(~.~:)A MAX

t:i:)

eOTH ENDS

~AMAX
(13.335)

BOTTOM VIEW

TO·3

TO·18

I-(~::::~::~)-[
I...'

IQi

_,_

0.315-0.335"1

(8.001-8.509) i

0.2"~0.260 I
I I

(8.098-8.604)

0.178-0.191 ~,_I 0.142-0.159
(4.521-4.151)
'(3.601-4.031)

I'

t .-,-

O.209~O.219

(5.309-5.563)

I

-L

SEATING

SEAT'NG
PLANE

PLANE1J=~~-···l

I!:~::)

0.045

'~F)~~~

MAX

non
:

(~::~::~:~:) _11.-

I

~
(12.70)

0.016-0.019 ...11...
(O.406~ ~

0.500
(12.70)
MIN

(4.826-5.334)

TO·52 (SQ·, SR)

'sa denotes a two lead package; center lead miSSing.

TO·39

-"------r

0.209-0.219
(5.309-5.563)

0.120

i1rnii

0.470-0.500

MAX

0.178-0.191 _ , 0.188-0.210
(4.521-4.851) -:
~ ~.~~~::.5.334)

I

0.250-0.340

I_I

=:J:~kJ
:r.;:
-=--__ !
0....-0.075

j

(24.333

24.435)

___ ..i._

I

I

I!:::

+

~ 0.021-0.034

(O.711-0.114)
0.158-0.112
_

SEATINGPI~Iln
-t
~t

I
I

MAX

aa aaa ___
Ii

0.016-0.019 __ 1_
(0.406-0.483)

...!:!!!=!!!L

~r (1 •.•:'.~4.111)
(3.....

0.'10-0:210)

0.142-0.152
(3.101-....1)

(4.12t-5.334)

TO·71

TO·66
B·2

0.500
(12.70)
' MIN

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

1--- (:::::::!:)
I
0.181-0.210

_ _ _ _ _ 0.209-0.219
~

(5.309-5.563)
0.142-0.159
(3.607-4.039)

_ _I

(4.521-4.851)
SEATING PLAHE

0.ne-O.1"

(4.521-4.11,) II~I

I~:~:)

00 n00

MAX

(~:~::~:~~) -+11__

SEATINGiLAHE

1

:£-aool
II
•.

O.~

MAX
0.011-0.01' __ _
(0.401-0.413)

(12.70)

TO·71 LOW PROFILE (UT)

I_

DI"

-Ii (:!!~::::.

J;. to....
-.

"f '~o;.l1 ~~ ~ ~~

-

,
,
)
Q
-0 00t

0.175-0.185
(4.«5-4.699)

DIA

(4.1.,-4. •

500
(12.70)
MIN

TO·72 (US)

I" :::-::: '~l

o.,.._o.rlL~I_

~5.334)

inJ
--L~

!_-J:=,~_~t

SEATING
PLANE

LEADS FIT INTO

-ll---,~::::~:::)

0.016-0.019

D~A~~:·~~lp)

I

I

I

I

I

I

(15.088)

J-...I

0.045-0.055 ....
(0.143-1.397)
--I
1

0.085-0,095

~

0.045-0.055
..... (0.143-1.397)

R~O'045_0'055

(2'15·~'::'~EI ,",'4.-,.397)
(3.43)
MIN

_
0.175-0.205
(4.45-5.21)

0.003-0.013
(0.076-0.330) F.

TO·92 (ZR)

TO·78

.370-.335

TO·99 (TV)

TO·99 (TV)
8-3

TO·100 (TW, TX)

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

0.395-0.405
(10.033-10.287)

0.139-0.147
(3.531-3.7~)

0.4IO-o.sao

(~

0.025

1.21

130.734)
REF

(0.635)

.+--":'::=~

;:::::::}

.r-

RAD

0.015-0.075

(1,15~~.105-.
CHAMBER

(1.524)

2 PLACES

jf
.
I

REF

.....-•.'.. ~II~1-1-0,0.015-0.185-

(2.413-2.117)
0.021
(G.iii) REF NOTE 2

I

1-

,

0.012-0.025
(0.305-0.835) ---

(2.413-2."7)

(~:::=::!!~) -J

170-•. , . .
4-(4.311-4.121)
~
(0.413-0• •

(::::=::=--

TO·202

TO·220

0.205-0.115

I. 1...'-....) . I

r:

-~_~._."~.

~ (i.l7-2.41)

0.270-0.210:

T

:

I

(....- ••10)

I 0.176-0.115
1(4.445-4• •

~ I

'000

0.4011-0.413)
~

DIA HOLE (TYP)

~g

-t

0:115-0.175
LEADS FIT INTO ~

0.114

II

I
(15.0II)

--L

::::~~ -I .....r-I.-

+

(3.43)
MIN

0.005

0.003-0.013
(0.078-0.330) R

(0.13

0.175-0.206
(4A5-5.21)

MIN_~1
1-..-=-=.. ~:I~
~ ~5~3:
200

(12.69)

(5.08)

13.5£' •.

12)

r

~ ~:~~)

2 LEAD CERAMIC (DH)

U

0.210 ± 0.006

15.33> •. '2)

L
l

0.050 ± 0.002

-------+- 0.401 (10.338) _

~~,~~J

.~'~3~

.

MAX

1'.27' .(6)
0.115 (2.921)

0.070 ~

-r~TIITr

0.015, t 0.002
(0.38 ± 0.06)

~=======}t
r---r t

(1,27:1:0.12)

[[]]

l~~:: :::;)~

lL-~§:~]==-=:~~f
~

..

~ O~OO:O~5

TO·237 (AR)

0.14O:t 0.005

_12.•• ~~:=)

~\=~v~/~55r;z:;z:;z;:z;z~z~z:;z~~~j~:n~~:=·~:

_1,.'43-"'87)

~

. o.s••

+

.....-.....

O'085_0'OH~(o'143~~~'056

12.'..-2.4'3)

I:I·:

0.017 ± 0.002

10:",..-.....

-t-~..!1Q 12.794) _

0.006± 0.001

_,~

0090(2.286)

(1.70:1:0.01)

I_II

~.~~! :g.~::

8 LEAD FLATPACK (SA)

..

0200 (S OS)

'-i===~:~=~==~=:~=24=:~)~'lr~~~I'
o.o~ 0200 j5 08)

--,-.::D.::'2=5-,,13,,1,,-75:::)~__

- -

~:~'~

(O.381)

1---1

8 LEAD CERAMIC (DA)
8-4

=
1

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

0.710
(11.5I)

r-I

0.344-0.314 MAX DI....
(1.74-1.25)

~ -4(12.1'-12.7)

~~0.Gl6-1J.100

=c=l...*SEATING PLANE

(1.02)

TVp_l~

(2.11-2.54,

0.1 ..-0.111 .....D
(4.22-4.47)

8 LEAD CERDIP (JA)

O~ b

.

8 LEAD TO·3 CAN (KA)

D.3l0± 0.005
(1.874 ± 0.127)

~H(1.651)
(9.652 ± 0.254)

I

r---'r
10_5tj_·'_~~
~'~======~~i===~
~

~

I

0 130 ± 0 002

~

090 (2 286)

023(584)

I

014 ( 356)

I635 ±0050 1

_ -r

__

~-.!

~

0.125 MIN

I

I

L,===-=='=

0015103.'1

------1, -

a DOS (02D3)

L

0.325 ± 0.025
(8.255 ± 0.635)

I

_ _ 11 _ _
1

=r

RE'l

-L
-I--"--~ ~~
0.017.0.002
TV.

0.320 (8128)

0.280 17.112' [

1

0.070 (1.778)
0.040 (1.016)

0.550

I
_0.710 (18.034) MAX_

0.110 f2.794)
0.090 (2.286) -

0.006 (0.152)
0.004 (0.102)

10 LEAD FLATPACK (FB)

8 LEAD PLASTIC (PA)

[I:::::]]

0.040 (1.016)

=~i=~[~ 0.020 (0.508)

1§""0"".2,,,,20;::1:::5:::.588=1

(3.175)!.------J

,070 (1.718)
~

0.240 (6.096)

1

______

____

0.200 (5 OB)

MAX

~==:

t

t

O.023~
0.014 (0.356)

14 LEA,D CERAMIC (DO)

14 LEAD FLATPACK (FD·1)

8·5

0.385

------, i

PACKAGE OUTLINES

All dimensions given in inches and (millimeters).

n

0.266 10.673)

r

0.250 (if.'635)

I~~~~~~~~
~~:::fJ:
'~D'780
MAX ~
)

0.055 (0.139)
0.045 (0.114)

119.• ,2)

$$$ : $$$~~t
L
[

1

I~~

~D.Dl.~

~!
====d;=~~ee;;::::=='
c-=-,

0.240 16.096

0.060 (1.524)
0.015 (0":"381'

0.1.014.572)
0.140
(3.556)

~

f!!3r

0.010 (0.254)

L

0.007 10.177)
0.004 (0.101'

0.07. 10.198)
0.065 (O.16S)

14 LEAD FLATPACK (FD·2)

14 LEAD CERDIP (JD)

[I:::::]]
0.115 (2.921)
O.OGO (1.524)

~

g: ~

O'810 (20.574) MAX___
~

l111.!!l-.

0.030 (0.762)

I-1-

r

J

0200 (5081
MAX

L-~IHmrJ~II ~!.M!l.,
~'=~'-1.JJ:j
l
t
D~'5 II
~_ 0.090 12.286i

O.11Q

14 LEAD PLASTIC (PO)

-+-

u, 0.126 (3.175)
(0.381) ~
I
=.)1
_I-- if.Oi'i
0.023 (0.5841
.. IH7·.366'22ID81 t---------.-J
iO:35iI 00..3220
r7.366)

16 LEAD CERAMIC (DE)

:':'.~~ +_~12~) MAX--::---1-(7.3661
MAX

I

0.019,10.483)
JO.D1S (0.381'

~~====ilro-·-11=i§~, f
=~===IL._J.~===;:;=;;

1+------+1
I

I

t

~ ,I~!~~AX
t

0.280 (7.112)
0.245 (6.223)

I

0.055 (1.391)
0.045 (1,143)
,
0.040 (l.Ot6)

I

dr°,020tO.50S1

~L~==D.=D06=ID=.'=52"')==:::o§§D.§D.§D§'2§.D§:3~=)~=F=~i
0,003 {O,6j6j

0.040 (1.016)

16 LEAD FLATP,ACK(FE·1)

16 LEAD FLATPACK(FE·2)
8-6

r------~I

PACKAGE OUTLINES

,.
0....

All dimensions given in inches and (millimeters).

t. .

31

[~~ ~ ~ ~ ~] ~:~!:~~~~;rl:1

iIJOii (l7.i011

~

.1

0.660 122.3621
0.966 12'.5111

nnnn

L

, ,

~

TVP.~

0,200 MAX 15.080)

II

,J LJ II
I I

,,
,
hl~~.-I

,

0.100 (2.S.) _I

0.78011'.8121 MAX

-I-

0,976 (24.7861

[

I

9~.19_ (;:!:~9~)

0.090 /2.286)

[::::::j1 :~~}
.23515 ....1
.215 (5.461)

.770 (19.558) MAX -

1,J
,' ,II

.110/2.794)
.09i:i (2.286)

F

TB-

..!§Q (4.064)

.008 (:203)

.023 (.584)
.015 (.381'

OOi~~I~i~1

Q.;Q2~

I

I

0.400 (10,16)

L O .• ,0123.114IMAXi

[[~:

JJ

0.110~ II

==

T. "

==

-------i l:i.330 (8-:-382) . . -

'

0.200 15.081

~ ~AjX

.400 (10.161
.330 (8.382)

11-~~It~~1
t t

~

T

~l--

0.115/2.921l
0,060 (1.524)

,100 12.540)

.060 (1.5241
.045 (1.143)

0.008

:~ - ! :g~~j:!

(!-\.584)
0.015 (0.381)

0.030 /0.762)

0.015

0:l:lmn'
~ ~fflt_J_--

IlL ~L I ~ ''''~''L

~'

J'l

~1'~

16 LEAD CERDIP (JE)

.160 MAX

~E~

I

=+_.

~
0.070 IJ.778)

16 LEAD (.6 x .7) CERAMIC (IE)

~

"

L

I .1

I
I
O.O'5(OL~" _-.i,.-._Q-14._5?})
~
0.140 (3.556)

E ~122'098I~

0.060 (1.524)

0.01510.3811

0.060 (1,524) 0.008 (0.203)

0.02510.6351',

0.200 (5.08)
0.125 (3.175)

I

~

0.023 (0.584)
0.014 (0.356)

.18 LEAD CERAMIC (ON)

16 LEAD PLASTIC (PE)

[~~~~~~~j
f..----

0.900 (22.860) MAX

~

0.060 (1.524)

O'*~u
~
-i !-0.110 ~ 0.070 (1.778)
0,090 (2.286) 0.030 (0.762)

0.20015.08)

Q.125 (3.T75i

-If-0.023 (0,584)
0.015 (0.381)

18 LEAD CERDIP (IN)

18 LEAD FLATPACK (FN)

B·7

I

I

0.320 (8.128) ___
0.290 (7.366)

PACKAGE OUTLINES

All dimensions given in inches and (millimeters)

[:::::] :.::::] F
~ 0.950 (24.13) MAX

=-::.t

(4.064)

f

]C]I

0060

- -: :. --T
~,
... ~ -''''

0.015 (0.3811

.

.

*

L

O.110~O.070l1..:ZZID.

O.022~

0.090 (2.286) 0.030 (0.762)

0.018 (0.457)

[~~~~~~]

.160 MAX

0.060 11.5241

-"'

.100(2.540)

~

r+L

(1524)~f.--l'02~(26'035IMAX
--I !

0015 (03811

--'--

---.--!

r

I

~ -

0 200 .!§..!l!l.
0125 (3175)

-

0110 (2794) 0070(1778)
0090 (2286) 0030 (oiS2l

.330 (8.382)

~~"-I

0180 (4572)

~) I/--~-'I

II

.0151.381)

.400 {lO.161

-:: r
0.320
0.290

I~

....,..\1'
"-"
~

0015
0 ooa

1' Ig~gM

-11-

0023(0584)
00)5 (0381)

I

----. 0400 !.!Q..Jm __
0330 (8382)

20 LEAD CERDIP (JP)

18 LEAD PLASTIC (PN)

·
C
1- - --

l

--~..

~:~

~I

0.410~r
0.390 (9.906)

-,g:~g=r

r,·10(27.941 MAX---jO.180

(4~~11

~~..
~ ~,~'"
~ L . Jl "
0.12513.1751

:j:mmL

!!
. I

r

0,1'0 (2.794)
0.090 (2.286)

0.010 (1.178)
0.030 (0.162)

~ 1 290 1327661 MAX

C~
=~

380 (96621

350191441

1_'2001~.:IMAx_1

..

19

EiTiTIiTT- -ITi1ilTI3I.~

:~~~ ~

"

! !

II
-.......110 (2.794)
;D9CH2.286)

- .090 (2.286)
:075 (1.9051

MAX

I

J

LO.510112....

0,023 (0.584)
0.015 (0.3811

0.44Ot11.176)

~
O.110~!

II ,470 (11.938)

.410 (10.414)

'r-

0.200 (5 08)
MAX

~
I·
0030(o76211~~"

0070 (1778)

0.115~

II
_/--'

1

O.023~
0.D14 (0.356)

22 LEAD. PLASTIC (PF)

I--

0570 (14 478)

:=M-:-.
~I-lClL==;=;=:Jl
..

0.060 (1.524)

.023 (.58421
.015 (.38101

14-

[06201157481 __

__

.~

6I
0 = r 1 ,.
im

I '

1.008 10.20321 I

. . . .- -.

=-=!

[ ==]

410 (10 414)

+Cllm~~LIL
'751~.4~1 ~~
I

O.OO8!Q.203)

22 LEAD CERDIP (JF)

22 LEAD CERAMIC (OF)

~ Ii ~~

I

I
~

Ii
0.200 (5.08)

0.008 (0.203)

. J .

!'

I

0.125(3.175)
0.060 ~
.0.025 (0.635)

1_

ro.59O

24 LEAD CERAMIC (OG)
B-8

0.015 10.3811 __ '--

0.620(15.148'_.--.1
(14.986)

I

PACKAGE OUTLINES

0.380 (9.652)
0.300 (7.62)

I

o.75O (19.051

All dimensions given in inches and (millimeters).

MINl

r(~AXl
r-.

D..

O.280(7.',Zl
0.245 (6223)

L

n

I

0.019 (0.483)

if.Of5 (0.381)

=c===+

l-0.430.
- r (10.9221
.
0.360 (9.1441

w

,,.

I-

100

iii
w
a:

80

CJ
Z

1 nA

Dice supplied in die form do not require cleaning prior to
assembly. Dice supplied in wafer form should be cleaned
after scribing and breaking. Freon TF in a vapor degreaser
is the preferred cleaning method. However, an alternative is
to boil the die in TCE for five minutes with a rinse in isopropyl alcohol for 1-2 minutes.

VGS(th)
rDS(on)
lOSS & lOSS
Qfs

0-20V @> 10 p.A

DIE ATTACH:
'The die attach operation should be done under a gaseous
nitrogen ambient atmosphere to prevent oxidation. A preform should be used if the mounting surface has less than
50 microinches of gold and the die should be handled on
the edges with tweezers. Die attach temperature should be
between 3850 C and 4000 C with eutectic visible on three
sides of the die after attachment.

IDloff ), ISloft), 'GSS
V GSl - V GS2 IDuals)

n

min. @ V GS

=0

IV GS

= 30 MOSFETs)

10,000 IJ.MHOS max. @ 10 ';;; 10 rnA
100pA min.
10rnV min.

Electrical testing is guaranteed to a 10% LTPD. AC parameters such as capacitance and switching time cannot be
tested in wafer or dice form.

STANDARD DIE CARRIER PACKAGE
•

Easy to handle, store and inventory.

•

100% electrically probed dice with electrical rejects removed.

•

100% visually sorted with mechanical and visual rejects
removed.

•

Easy visual inspection - dice in carriers, geometry side
up.

BONDING:
Thermocompression gold bailor aluminum ultrasonic bonding may be used. The gold ball should be about 3 times the
diameter of the gold wire. The ball should cover the bonding pad, but not excessively, or it may short out surrounding
metallization. l-mil aluminum wire may be used on most
dice, but should not be used if the assembled unit will be
plastic encapsulated.

20

100 rnA max.

•

Individual compartment for each die.

•

Carriers usuable in customer production area.

•

Carrier may be storage container for unused dice.

HANDLING OF DICE:

•

All dice shown in this catalog are passivated devices and Intersil warrants that they will meet or exceed published specifications when handled with the following precautions:

Carriers hold 25, 100, or 400 dice, depending on die size
and quantity ordered.

•

Part numbers shown in this catalog are for carrier packaging.

•

Dice should be stored in a dry inert-gas atmosphere.

•

Dice should be assembled using normal semiconductor
techniques.

•

Dice should be attached in a gaseous nitrogen spray at a
temperature less than 4300 C.

COMPARTMENTED
TRAY

DICE

ELECTRICAL TEST LIMITATIONS
DUAL BIPOLAR TRANSISTORS
LV CEO

100V max. @ ,;;; 1 rnA

BV CBO
BV EBO

190V max. @ >1 p.A

hFE

';;;1000@ >10 p.A

V CE(sat)

>10 mV @';;;1O rnA

I CBO

>100 pA @ ';;;100V

\' i3El- V BE2
181 -I B2

>2 nA

"

100V max. @';;;1O rnA

>1 mV @ >10p.A

B-24

CLEAR AMBER COVER
. / WITH ANTI-STATIC
I PLASTIC FILM

DIE & WAFER ORDERING INFORMATION

OPTIONAL VIAL PACKAGE

ELECTRICAL TEST CAPABILITY

•

100% electrically probed dice with rejects inked but included in vial. Bulk shipment.

•

10% extra good dice included (no charge) to cover possible breakage and/or visual rejects.

As an example of how to use the capability chart to see
what Intersil actually guarantees and tests for, on a 100%
basis, compare the 2N4391 in a TO-18 package to the
2N4391 delivered as a chip.

•

Preferred for production quantities.

•
•

Electrical Test Spec.

Lower cost.
For vial package - replace "0" in catalog number with
"V", e.g.: 2N4416/0 (2N4416 dice in carrier) becomes
2N4416/V (2N4416 dice in vial).

100 pA max.

BV GSS

40V min.

40V min,

10(offl @ 25C

100 pA max,

100 pA max,

1V max,

See note 1

V GS(oftl or V p

4V to 10V

4V to 10V

lOSS

50 to 150 rnA

50 to 100 rnA
O.4V max.

VOS(on)

O.4V max,

rOS(o,n)
Ciss

30n max.

30n max.

14pF max,

Guaranteed by Design

C rss

3,5 pF max,

Guaranteed by Design

td

15n5 max.

Guaranteed by Design

t,

5ns max.

Guaranteed by Design

toft

20n5 max.

Guaranteed by Design

tf

15 ns max.

Guaranteed by Design

NOTE 1:

•

This parameter is very dependent upon quality of metallization surface to which chip is attached.

100% electrically probed - rejects inked.

•

10% extra good dice included (no charge) to cover possible br~akage and/or visual rejects.

•

Preferred for production quantities.

•

Lowest cost.

SUMMARY
Of the 14 items specified for the package part, only 7 can
be tested and guaranteed in die form. It is to be noted that
those specifications which cannot be tested in die form can
be sample tested in package form as an indicator of lot performance. Many of the tests, however, such as capacitance
tests, are design parameters.

• Wafer is supplied unscribed.
•

2N439l Chip

100 pA max.

V GS(forward)

OPTIONAL WAFER PACKAGE

2N439l in a TO-1S

I GSS @25C

For wafer package - replace "0" i.n catalog number with
"W", e.g.: 2N4416/0 (2N4416 dice in carrier) becomes
2N4416/W (2N4416 dice in wafer).

The above electrical testing is guaranteed to a 10% LTPO,
However, there are occasions where customer requirements
cannot be satisfied by wafer sort testing alone. While the
previously described tests will be done on a 100% basis, Intersil recognizes the need for additional testing to obtain
confidence that a particular customer's needs can be met
with a reasonably high yield, Toward this end Intersil has
instituted a dice sampling plan which is two-fold. First,
random samples of the dice are packaged and tested to assure adherence to the electrical specification. When required, wafers are identified and wafer identity is tied to
the samples. This tests both the electrical character of the
die and its ability to perform electrically after going through
the high temperature dice attachment stage. Second, more
severe testing can be performed on the packaged devices
per individual customer needs. When testing is required
other than that called out in the data sheet, Intersil issues
an ITS number to describe the part, Examples of tighter
testing which can be performed on packaged samples is
shown as follows:

FOAM
MYLAR

FILTER PAPER

NOTE:
Intersil reserves the right to improve device geometries and
manufacturing processes as required. These improvements
may result in slight geometry changes. However, they will
not affect the electrical limits, basic pad layouts or maximum die sizes in·this catalog.
B-25

m
•
•

DIE & WAFER ORDERING INFORMATION
FET & DUAL FET PAIRS
1. Leakages to 1 pA (I GSS)
2. ros lonl to as low as 4 ohms
3. 10 loffl to 10 pA

TRANSISTOR PAIRS
1. Leakages to as low as 1 pA
2. Beta with collector current up to 50 mA and as lowas 100 n,

4. loss to 1 amp (pulsed)

3. fT up to 500 MHz with collector currents in the range of
10 /1A to 10 mA

5. 9fs to 10,000 pmho

4. Noise measurements as low as 5nV/y'HZ from 10Hz to 100k

6. 90S to 1 pmho

5. A(VBE1-VBE2)/AT to 10pV;oC to an LTPD of 20%

7. en noise to 5 n V /y'HZ at frequencies of 10Hz to 100 Hz
8. CMRR to 100 dB

VISUAL INSPECTION

9. A(V GS1-V GS2)/AT down to 1'OpV/"C to an LTPD of 20%

Individual chips are 100% inspected to MIL-STD-750,
Method 2072 or, as an option, MIL-STD-883, Level B.
Inspection is done to an L TPD of 20%. As an option, Intersil offers S.E.M. capability on all wafers.

10.9m match to 5%
11. loss match to 5%

B-26

DIE & WAFER ORDERING INFORMATION

CMOS INTEGRATED CIRCUIT CHIPS

INTRODUCTION
In addition to discrete device chips, Intersil also offers a full
line of metal gate CMOS integrated circuits in die form. Die
sales, however, present some unique problems. In many
cases, chips cannot be guaranteed to the same electrical
specifications as can the packaged parts. This is because
leakage, noise, AC parameters and temperature testing cannot be guaranteed to the same degree of accuracy for dice
as for packaged devices.

•

Each die surface is protected by planar passivation and
additional surface glassivation except for bonding pads
and scribe lines. The surface passivation is removed from
the bonding pad areas by an HF etchant; bonding pads
may appear discolored at low magnification due to surface roughness of the aluminum caused by the etchant.

•

Dice are 100% inspected to electrical specifications, then
visually inspected according to MI L·STD·883, Method
2010.2, Condition B, with modifications reflecting CMOS
requirements.

•

Bonding pad dimensions are 4.0 x 4.0 mils minimum.

GENERAL PHYSICAL INFORMATION

•

Storage temperature is _40°C to +150°C.

• Chips are available with precise length and width dimensions, ± 2 mils in either dimension.

•

• Operating temperature is -20°C to + 70°C.
Guaranteed AQL Levels:
Visual
2.0%
Functional electrical testing 1.0%
Parametric DC testing
4.0%
Untested parameters
10.0%

• Chip thickness is 15 mils ± 1 mil.
•

Bonding pad and interconnect material is aluminum, 10K
to 15K Athick.

CMOS INTEGRATED CIRCUIT CHIP PROCESSING FLOW CHART

WAFER
PROCESSING

1------VISUAL
INSPECTION

+

+

QC
ELECTRICAL
INSPECTION

CARRIER
LOADING

..1

t

t

WAFER
CLASSIFICATION
& ALLOCATION

SCRIBE
&
FRACTURE

. PACKING
&
SHIPPING

+

X

100%
CLEAN

100%
ELECTRICAL
PROBE

l

rl
'---

+
100%
VISUAL

i
QC
VISUAL

I

B-27

QC sample
assembled for
special testing
when required

DIE & WAFER ORDERING INFORMATION
RECOMMENDED DICE ASSEMBLY PROCEDURES

STANDARD DIE CARR.IER PACKAGE
•

Easy to handle, store and inventory.

CLEANING

•

100% electrically probed with electrical rejects removed.

Dice supplied in die form do not require cleaning prior to
assembly. However, if cleaning is desired, dice should be
subjected to freon TF in a vapor degreaser and then vapor~
dried.

•

100% visually sorted with mechanical and visual rejects
removed.

•

Easy visual inspection - dice are in carriers, geometry
side up.

RECOMMENDED HANDLING

•

Individual compartment for each die.

Intersil recommends that dice be stored in the vacuumsealed plastic bags which hold the dice carriers. Once removed from the sealed bags, the di.ce should be stored in a
dry, inert-gas atmosphere.

•

Carriersusable'in customer production area.

Extreme care should be used when handling dice. Both
electrical and visual damage can occur as the result of an
unclean environment or harsh handling techniques.

•

• Carrier may be used as storage contained. for unused dice.
• Carriers hold 25, 100 or 400 dice, depending.on die size
and quantity ordered.
Packaging of integrated circuit dice in carriers is identical to illustration shown earlier for discrete device, except that IC chips are not available in vial packs or in
wafer form.

DIE ATTACH

The die attach operation should be done under a gaseous
nitrogen ambient atmosphere to prevent oxidization. If a
eutectic die attach is used, it is recommended that a 98%
gold/2% silicon preform be. used at a die attach temperature between 385°C and 435°C. If an epoxy die attach is
used, the epoxy cure temperature should not exceed 150°C.
If hermetic packages are used, epoxy die attach should be
carried out with caution so that there will be no "outgassing"
of the epoxy.

CHANGES

Intersil reserves the right
manufacturing processes
these improvements may
they will not affect dice
maximum die sizes.

in improve device geometries and
without prior notice. Although
result in slight geometry changes,
electrical limits, pad layouts, or

USER RESPONSIBILITY
BONDING

Written notification of any non-conformance by Intersil of
Intersil's dice specifications must be made within 75 days of
the shipment date ofthe die to the user. Intersil assumes no
responsibility forthe dice after 75 days or after further user
processing such as, but not limited to, chip mounting or wire
bonding.

Thermocompression gold ball or aluminum ultrasonic bonding may be used. The wire should be 99.99% pure gold and
the aluminum wire should be 99% aluminum/1% silicon.
In either case, it is recommended that 1.0 mil wire be used
for normal power circuits.

8·28'

PART NUMBERING SYSTEM

LINEAR:

Examples of Intersil Part Numbers

BASIC

ELECTRICAL
OPTION
TEMP

ICH8500

A

ICL8038

C

PIN

T

V

C

P

0

ICLB03BCC PO

M

0

E

IH5040MDE

C

IH5040

ICL 8038
ORDER #

PKG

ICH8500ACTV

illl

C C P D

~---

ON ALL INTERSIL IC PART NUMBERS. THE LAST
THREE LETTERS ARE TEMPERATURE, PACKAGE,
AND NUMBER OF PINS, RESPECTIVELY.

~----~-------

Number of Pins
Package
Temperature Range:
M - -55°C to +125°C
I - -20°C to + 85°C
C O°C to + 70°C
Electrical Option
Device Chip Type
Intersil Linear Circuit

HYBRIDS:
PACKAGE:

A
8
C
D

E
F
H

J
K
L
P
S
T

U
V
Z
IW
ID
NUMBER OF PINS:

A
8
C
D

E
F
G
H
I

J
K
L
M
N

TO-237
Plastic flat-pack
TO·220
Ceramic dual·in·line
Small TO-8
Ceramic flat·pack
TO·66
16 pin (.6 x .7 pin spacing)
hermetic hybrid dip
Cerdip dual-in·line
TO·3
Leadless, ceramic
Plastic dual·in·line
TO-52
TO·5 type (also TO-78, TO·99,
TO-100)
TO-72 type (also TO-18, TO·71)
TO-39
TO-92
Wafer
Dice
8
10
12
14
16
22
24
42
28
32
35
40
48
18

P
Q

R
S
T

U
V

DG 126 A L

- - -t=t

~-----~-------

IH 5043 B M F 0

--E~
l.:==

Number of Pins
Package
Temperature Range:
M - -55°C to +125°C
C 0° C to + 70° C
Electrical Option
' - - - - - - - Device Chip Type
.....,.-------Intersil Hybrid/Analog Gate

20
2
3
4
6
7
8 (0.200" pin circle,
isolated case)

WATCH AND CLOCK:

---lli=L
leM 7045 A I P I

W

10 (0.230" pin circle,
isolated case)

Y

8 (0.200" pin circle,
case to pin 4)
10 (0.230" pin circle,
case to pin 5)

Z

Package:
A - Metal Can
K - Cerdip
L - Flat pack
P - Ceramic
Temperature Range:
A - -55°C to +125°C
B - -20°C to + 85°C
C O°C to + 70°C
Device Chip Type
Device Family
DG - Drivers
o - Drivers
G - Multi-channel FET

8-29

Number of Pins

Package
Temperature Range:
M - -55°C to +125°C
I - -20°C to + 70°C
C 0" C to + 70° C
.....,.---- Electrical Option
' - - - - - - Device Chip Type
'-----~-- Intersil Watch and Clock Circuit

m

PART NUMBERS AND ORDERING INFORMATION
MOSMEMORY:

C/MOS MEMORY:
1M 6 5 08 A -1 MOE

-ill,
Tl
L
~---

'----'-----'-------

'-------'---------

1M 7 114..!::...
Number of Pins
Package
Temperature
M - -55'C to +125'C
I - -20·C to + 85·C
C O°C to + 75°C
Improved Speed, Reduced Current (optional)
Operating Voltage (optional)
Specific Chip Type
General Type
1 - Processing Elements
3 - Read Only Memories (ROM)
4 - Interface Elements
5 - Random Access Memories (RAM)
6 - Programmable Read Only Memory (PROM)
C/MOS Process
Intersi! Memory CirCUit

m.

1:1

B~30

3..

C J N

tC~

~---

L-_ _ _ _ _
L-_ _ _ _ _ _
L._ _ _ _ _ _ _ _
L._ _ _---,_ _ _ _ _

Number of Pins
Package
Temperature Range
M - _55°C to +125'C
I - -20'C to + 85·C
C O'C to + 75'C
Speed Selection
Power Selection
Device Chip Type'
MOS Process
Intersil Memory

DOMESTIC SALES OFFICES
CALIFORNIA

ILLINOIS

MINNESOTA

1272 Forgewood Avenue
Sunnyvale, California 94089
Tel: (408) 996·5285
TWX: 910·339·9260

85 W. Algonquin Rd., Suite #380
Arlington Heights, IL 60005
Tel: (312) 364·6670
TWX: 910·687·3782

6550 York Avenue, South. Suite #416
Minneapolis. Minnesota 55435

20969 Ventura Blvd., Suite 6
Woodland Hills, CA 91364
Tel: (213) 887·7363
TWX: 910·494·2104

MASSACHUSETTS

NEW JERSEY

2 Militia Drive, Suite 12
Lexington, Massachusetts 02173

560 Sylvan Avenue
Englewood Cliffs. New Jersey 07632

FLORIDA

Tel: (617) 861·6220
TWX: 710·326·0887

GE Intersil
700 W. Hillsboro Blvd., Bldg. 4
Suite 207
Deerfield Beach, FL 33441
Tel: (305) 429·0440

9-31

Tel: (612) 925·1844
TWX, 910·576·2780

Tel: (201) 567·5585
TWX, 710·991·9730

.D~DlL

DOMESTIC SALES REPRESENTATIVES
ARIZONA

INDIANA

NEW YORK (cont.)

eSA Electronics

Giesting Associates
4407 DeRome Drive

S·J Associates

LD Electronics

Fort Wayne, IN 46815
Tel: (219)486-1912

148-05 Archer Ave_ '
Jamaica, NY 11435
Tel: (212)291-3232
TWX: 710-582-2635

East 12607 Gulhrie Dr_
Spokane, WA 99216
Tel: (509) 922-4883

Giesting Associates
5825 Somers Drive
Indianapolis. IN 46227
Tel: (317)263-0005

NORTH CAROLINA

727·E2 ArcadIa Circle. NW

Huntsville. AL 3580t
Tel: (205)533-2444
TWX: 810-726-2170

ARIZONA
Shefler-Kahn

2017 N. 7th 51.
PhoenIX. AZ 85006
Tel: (602)257-9015
TWX: 910-951-0659

CALIFORNIA
ADDEM S.D.

LD Electronics

CSR E)ectronics
5880 Faringdon Place

Los Altos. CA 94022-3968 .
Tel: (415)962-0660
TWX: 910·370-6005

Interstate Marketin'g Assoc.
P.O. Box 487
Woodland Hills. CA 91365
Tel: (213)883-7606
TWX: 910·494-1239

COLORADO
Thorson Rocky Mountain. Inc.
7076 S. Alton Way
Bldg. D
Englewood. CO 80112
Tel: (303) 779-0666
TWX: 910-935-0117

CONNECTICUT

Raleigh, NC 27609
Tel: (919)878-9200
TWX: 510-928-1845

Severna Pk. MD 21146
Tel: (301)544-4100
TWX: 710-867-6405

OHIO

D_ Dolin Sales Co_
131 W_ Layton Ave_
Milwaukee, WI 53207
Tel: (414)482-1111
TWX: 910-262-1139

Giesting & Associates
7712 Hamilton Avenue

CANADA

MASSACHUSETTS

Cincinnati, OH 45231
Tel: (513)521-8800
TLX: 214-283

COM-SALE
Waltham_ MA 02154
Tel: (617)890-0011
TWX: 710-324-7708

Giesting & Associates

8843 Washington Colony Dr.
Daylon, DH 45459
Tel: (513)293-4044

MICHIGAN

Walling lord. CT 06492
Tel: (203)269-7964
TWX 910-324-7708

FLORIDA
EIR. Inc.
1 76 Jaffa Drive

Fern Park, FL 32730-0057
Tel: (305)830-9600
TWX: 810-853-9213
EIA. Inc
6541 Harbour Road

N_ Lauderdale, FL 33068
Tel: (305)975-8712

6455Southgrove
Mentor, DH 44060
Tel: (216)946-3407

5654 Wendzel Dr.
Colma_ MI 49038
Tel: (616)468-4200
Giesting & Associates

OKLAHOMA

22765 Heslip Dr. #103
Novi, MI 48050
Tel: (313)348-3811

Bonser:Philhower Sales

6644 South Victor
Tulsa, OK 74136
Tel: (918)496-3236

MINNESOTA

LD Electronics

P.O. Box 626
Beaverton, OR 97075

NEW HAMPSHIRE

Tel: (503)649-8556
(503) 649-6177
TWX: 910-467-8713

COM-SALE
102 Maple 51.
Manchester, NH 03103
Tel: (603)668-1440

Giesting & Associates

NEW JERSEY

471 Walnut Slreet
Pittsburgh, PA 15238
Tel: (412)963-0727

PENNSYLVANIA

Comlek, Inc.
Plaza Office Center
Suite 404 East
Route 73 and Fellowship Rd.

TEXAS
Bonser-Philhower Sales

Mt. Laurel, NJ 08054
Tel: (609)235-8505
TWX: 710-897-0150

NEW MEXICO

GSR Electronics
1530 Dunwoody Village Pkwy.

Shefier-Kahn

689 West Renner Road
SuiteC
Richardson, TX 75080
Tel: (214)234-8438
TWX: 910-867-4752
Bonser-Philhower Sales

SUite 110
Tel: (404)396-3720
TWX: 810-751-0337

11700 Southwest Freeway
Suite 110
Houston, TX 77031
Tel: (713)531-4144

10200 Menaul NE
Albuquerque, NM 87112
Tel: (505)296-0749

Bonser-Philhower Sales

NEW YORK

8200 Mopac, Suite 120
Austin, TX 78759
Tel: (512)346-9186

ILLINOIS
Ossmann Component Sales
D. Dolin Sales Co.

6232 N. Pulaski Rd_
Chicago_ IL 60646
Tel: (312)286-6200
TWX: 910-221-5018

7528 Bath Rd_

~~~~~:t~~a18ntario
Tel: (416)671-2225
(416)671-8111
P_O. Box 15766
Station F
Ottawa, Ontario

Canada, K2C 357
Tel: (613) 593-8873
Gidden·Morton Assoc., Inc.

605 Rue Filiatautt
51. Laurent, Quebec
Canada H4L 3V3
Tel: (514)747-1770
Woodberry Electronic Sales LTD_

OREGON

PSI
7732 West 78th Street
Minneapolis, MN 55435
Tel: (612)944-8545
TWX: 910-576-3483

GEORGIA

Gidden-Morton Assoc., Inc.

Gidden-Morton
Giesting & Associates

Giesting & Associates

COM-SALE
633 Williams Road

WISCONSIN

Suite 2

New Era Sales, Inc.
678 Ritchie Hwy.

60 Hickory Drive
Elrepco Inc.
4962 EI Camino Real. Suite 217

7410 771h Ave_, S_E_
Snohomish, WA 98290
Tel: (206)568-0511

MARYLAND

923 Daisey Ave.

Carlsbad. CA 92008
Tet: (619)695-2050
TWX: 910·335-1272

WASHINGTON

Corp.
280 Metro Perk
Rochester, NY 14623
Tel: (716)424-4460
TWX: 510-253-7685

UTAH
Thorson Rocky Mountain, Inc.

Bank of Utah, Suite A
2309 S_ Redwood Rd_
West Valley City, UT 84119
Tel: (801)973-7969
TWX: 910-925-5826

Ossmann Component Sales
Corp.

t54 Pickard Bldg_
Syracuse, NY 13211

Tel: (315)455-6611
TWX: 710-541-1522

8·32

Discovery Park

107A-3700 Gilmore Way
Burnaby, B_C_
Canada V5G 4Ml
Tel: (604)430-3302
TLX: 04356595

.O~OIb
INTERSIL FRANCHISED DISTRIBUTORS
ALABAMA

CALIFORNIA (con!.)

CONNECTICUT (con!.)

ILLINOIS (con!.)

Hamilton/Avnel Electronics
4692 CommerCial Drive

Kierulif Electronics

Kierulff Electronics

2585 Commerce Way

165 Northplains Rd.

Huntsville. AL 35805
Tel 1205) 837·7210

~~~ ~~~~j~S5~3~~0040

Wallingford, CT 06492
Tel: (203) 265·1115

Schweber Electronics
904 Cambridge Drive
Elk Grove Village, IL 60007

Schweber Electronics
25 Wiggins Ave.
Bedford, MA 01730

Tel: (312) 364·3774
TWX: 910·222·3453

Tel: (617) 275·5100
TWX: 710·326-0268

TWX: 910·580·3106

Schweber Electronics
2227 Drake Ave. SW
Suite 14
Huntsville. AL 35605
Tel: (205) 882-2200

ARIZONA
Arrow Electronics
2127 West 5th Place
Tempe. AZ 85281

Kierutfl Electronics
3969 East 8ayshore Rd.
Palo Alto, CA 94303
Tel: (415) 968-6292
TWX: 910-379·6430

Kierulff Electronics
14101 Franklin Ave.
Tustin, CA 92680

Schweber Electronics
Finance Drive
Commerce Industrial Park
Danbury, CT 06810
Tel: (203) 792·3742
TWX: 710·456-9405

FLORIDA
Arrow Electronics

INDIANA

MICHIGAN

Advent Electronics
8446 Moller Rd.
Indianapolis, IN 46268
Tel: (3171872-4910
TWX: 810·341-3228

Arrow Electronics
3801 Varsity Dr.
Ann Arbor, MI48104

Arrow Electronics
2718 Rand Road
Indianapolis, IN 46241

Arrow Electronics
3510 Roge~ Chaffee Blvd.
Grand Rapids, MI 49508

Tel: (317) 243·9353
TWX: 810·341·3119

Tel: (616) 243·0912

Tel: 1602) 968·4800

Tel: (714) 731-5711
TWX: 910·595·2599

Hamilton/Avnet Electronics
505 S. Madison Dr.
Tempe. AZ 85381

Schweber Electronics
17822 Gillette Ave.
Irvine, CA 92714

Tel: (305) 776-7790
TWX: 510-955-9456

Tel (602) 275·7851
Tel: (602) 894·9600

Tel: (714) 863-9953
TWX: 910-595-1720

Arrow Electronics
50 Woodlake Dr. West

Hamilton/Avnet Electronics
485 Gradle Dr.
Carmel, Indianna 46032

Bldg. B.

Schweber Electronics
1771 Tribune Rd.
Suite B
Sacramento, CA 95815

Tel: (317) 844-9333

Tel: (305) 725·1480
TWX: 510·959·6337

Klerulff Electronics
4134 E. Wood St
Phoenix'. AZ 85040
Tel: (602) 243·4101

Tel: (916) 929-9732

TWX 910·9511550

Schweber Electronics
3110 Patrick. Henry Dr.
Santa Clara, CA 95050

1001 NW 62nd SI.

Suite 108
Ft. lauderdale, FL 33309

Palm Bay, FL 32905

Hamilton/Avnet Electronics
6801 NW 151h Way
Ft. Lauderdale, FL 33309

MASSACHUSETTS (con!.)

IOWA
Advent Electronics
682 58th Avenue Courth S.W.
Cedar Rapids, IA 52404

Tel: (313) 971·8220
TWX: 810-

Hamilton/Avnet Electronics
32487 Schoolcraft Road
Livonia, MI 48150
Schweber Electronics
12060 Hub
Livonia, MI 46150
Tel: (313) 525·8100
TWX: 810-242·2983

MINNESOTA

Tel: (305) 979·2900

Tel: (319) 363-0221
TWX: 910·525·1377

Tel: (408) 748-4700
TWX: 910-338-0296

Hamilton/Avnet Electronics
3197 Tech Drive North
St. PeterSburg, FL 33702

Arrow Electronics
1930 St. Andrews Dr., N.E.
Cedar Rapids, IA 52402

Wyle Distribution Group
8155 N. 24th Ave
Phoenix. AZ 85021

Wy!e Distribution Group
3000 Bowers Ave
Santa Clara, CA 95051

Tel: (8131576-3930

Tel: (3191373-7230

Kierulff Electronics

Tel (602) 249·2232
TWX: 910·951-4282

Tel: (4081727·2500
TWX: 910-338·0296

Schweber Electronics
5720 N. Park Place N.E.
Cedar Rapids, IA 52402

CALIFORNIA

Wyle Distribution Gro'up
124 Maryland St.
EI Segundo, CA 90245

Te): (305) 955·9601
TWX: 510·955·9801

KANSAS

Tel: (213) 322-8100

TWX: 910·348·7140

Kierulff Electronics
3247 Tech Or.
St. Petersburg, FL 33702

Hamilton/Avnet Electronics
9219 Quivira Road
Overland Park, KS 66215

Wyle Distribution Group
17872 Cowan Ave.
Irvine, CA 92714

Tel: (813) 576·1966
TWX: 810-863-5625

Tel: (714) 641-1600
TWX: 910-595·1572

Schweber Electronics
181 Whooping Loop
Altamonte Springs, FL 32701

10300 W. 103rd

Arrow Electronics
2380 Schuetz Rd.
St. Louis, MO 63416

SuiteM'103
Overland Park, KS 66214

Tel: (314) 567-6688
TWX: 910·764-0682

Wyle Distribution Group
9525 Chesapeake Dr.
San Diego, CA 92123
Tel: (714) 565·9171

Tel: (305) 331-7555

Tel: (913) 492-2922

Schweber Electronics
11049 N. 23rd onve
Phoenix, AZ 85062
Tel' (602) 997·4874

4125 Sorrento Valley Blvd
San Diego, CA 92121
Tel: (612) 453·9005
TWX: 910·335·1515

Anthem Electronics
1.74 Component Dr.
San Jose, CA 95131
Tel: 14081946·8000
TWX: 910·338·2038

Arrow ElectroniCS
4029 Westly Place
SUite 113
Newport BeaCh. CA 92660
Tel. (714)851·8961
TWX 910·595·2860

Arrow ElectroniCS
521 Weddel Ave
Sunnyvale. CA 94086

TWX: 910-335-1590

Wyle Military
18910 Teller Ave.
Irvine, CA 92715
Tel: (714) 851-9953
TWX 910-595-2642

Tel 1408) 745·6600

Arrow Electronics
9511 Rldgehaven CI.
San Diego. CA 92123
Tel 1619) 565·4800
TWX 910·335·1195

Arrow Electronics
19748 Dearborn 51.
Chatsworth, CA 91"311
,eI1213) 701·7500
TWX 910·483-2086

Avnet Electronics
350 McCormick Avenue
Cost Mesa, CA 92626
Hamitton Elect-ro Sales
10950 Washington Blvd
Culver City, CA 90230
Tel: (213) 558·2121

Hamilton Electro Sales
Orange County
3170 Pullman Street
Costa Mesa, CA 92626
Tel: (714) 641·4100
Hamilton/Avnet
4545 Viewridge Avenue
San Diego. CA 92123
Sales: (714) 571·7510
Admin: (714) 571·7500
Hamilton/Avnet Electronics
1175 Bordeaux Drive
Sunnyvale, CA 94086
Tel:

(40~)

743·3355

COLORADO
Belllndus!ries
8155 W. 48th Ave.
Wheatridge, CO 80033
Tel: (303) 424·1985
TWX: 910·938·0393

4850 N. Stale Rd. *7

Suite E
Ft. Lauderdale, FL 33319

Schweber Electronics
2830 N. 28th Terrace
HOllywood, FL 33020

Hamilton/Avnet Electronics
10300 Bren Rd.
Minnetonka, MA 55435
Tel: (513) 433-0610

Kierulff Electronics
7667 Cahill Road
Edina, MN 55435
Tel: (612) 941-7500
TWX: 910-576·2721

MISSOURI

Hamilton/Avnet Electronics
13743 Shoreline Court
Earth City, MO 63045
Tel: (314) 344·1200

Tel: (305) 921-0301
TWX: 510·954·0304

GEORGIA

Tel: (301) 247-5200
TWX: 710-236·9005

Arrow Electronics
2979 Pacific Dr.
Norcross, GA 30071

Columbia, MD 2104

LCOMP

2211 River Front Dr.
Kansas City, M064120

Hamilton/Avnet Electronics

Tel: (404) 449-8252

Bait. Sales: 501-995-3500

Wash. Sales: 301·621·5410

Hamilton/Avnet Electronics
5825 D. Peachtree Corners East
Norcross, GA 30092

Kierulff Electronics
202 Azar Court
Baltimore, MD 21227

Schweber Electronics
303 Research Drive
Norcross, GA 30092
Tel: (404) 962-3405
TWX: 810-766·1592

Kierulff Electronics
7060 S. Tucson Way
Englewood, CO 80112

ILLINOIS
Arrow Electronics
200 Algonquin
Schaumburg, lL 60195

Wyle Laboratories
451 E. 124th Ave.
Thornton, CO 80241

Tel: (312) 397·34~0
TWX: 910·291-3544

Tel: (303) 457·9953
TWX: 910-931·2626

Hamilton/Avne! Electronics
1130 Throndale Ave.
Bensonville, FL 60106
Tel: (312) 860·7700

Kierulff Electronics
1530 Landmeier Rd.
Elk Grove Village, lL 60007

Tel: (203) 265-7741
TWX: 710·476-0162

Tel: (312) 640-0200
TWX: 910-222-0351

Hamilton/Avnet Electronics
Commerce Indu·strial Park
Commerce Drive
Danbury, CT 06810

Newark ElectroniCS
500 North Pulaski Road
Chicago, IL 60624
Tel: (312) 638·4411

8-33

2550 Harley Dr.
TWX: 910-762-0632

Tel: (816) 221·2400
TWX: 910-771·3148

Tel: (301) 247-5020
TWX: 710-234-1971

Schweber Electronics
502 Earth City Expwy.
Suite 1#203

Schweber Electronics
9218 Gaither Rd.
Gaithersdurg, MD

NEW HAMPSHIRE

Tel: (301) 840-5900
TWX: 710-828-9749

MASSACHUSETTS
Arrow Electronics
Arrow Drive
Woburn, MA 01801
Tel: (617) 933-8130
TWX: 710·393-6770

Gerber Electronics
128 Carnegie Row
Norwood, MA 02062

Earth Cily, MO 63045
Tel: (314) 739-0526

One Perimeter Road
.''''''''''00310~
ManChester, NH

~~~~~~b~~~~~~
Schweber Electronics
Bedford Farms
Bldg. 2

Kitton & SOUUI River Rd.
Manchester, NH 03102
Tel: (603) 625-2250
TWX: 710-220·7572

NEW JERSEY

Hamilton/Avnet Electronics
50 Tower Office Park
WOburn, MA 01801

Arrow Electronics
6000 Uncoln Drive East
Ezesham, NJ 08053

Tel: (617) 273-7500

Kierulff Electronics
13 Forturn Or.
Billerica, MA 01821

lEI

Tel: (609) 596·8000
TWX: 710-897-0829

Arrow Electronics
2 Industrial Road
Fairfield, NJ 07006
Tel: (201) 575-5300
TWX: 710-734-4403

•.

. •

Tel: (6171769-6000
TWX: 710·336-1987

Tel: (617) 667-8331
TWX: 710·390-1449

Tel: (203) 797-2800

LCOMP

~e~~~~~~ 2~;~~~b6 MO 63043

6822 Oak Hall

TWX: 810·757·4213

Admin: (303) 779·9998
Sales: (303) 740-1000

Arrow ElectroniCS
12 Beaumont Rd.
Wallingford,· CT 06492

MARYLAND

Tel: (612) 830·1800

Arrow ElectroniCS
4801 Benson Ave.
Baltimore, MO 21227

Tel: (404) 447-7507

CONNECTICUT

Te.l: (913) 888-8900

Schweber Electronics

Hamilton Avnet Electronics
8765 E. Orchard Road
Suite .708
Englewood, CO 80111

Tel: (303) 371-6500

Tel: (319) 373·1417

Arrow Electronics
5230 W. 73rd Street
Edina, MA 55435

INTERSIL FRANCHISED DISTRIBUTORS
NEW JERSEY (cont.)

NORTH CAROLINA

PENNSYLVANIA

UTAH (cont.)

CANADA (cont.)

HamiltonfAvnet ElectroniCS
1 Keystone Ave.
Bldg. #36
Cherry HiH, N.J. 06003
Tel: (609) 424·0100

Arrow Electronics
3117 Poplarwood Court
P.O. Box 95163 Suite 123
Raleigh, NC 27625
Tel: (919) 876·3132
TWX: 510·928·1856

Arrow Electronics
650 Seco Rd.
Monroeville, PA 15146
Tel: (412) 856·7000
TWX: 710·797·3894

Wyle Distribution Group
1959 S. 4130 West. Unit B
Salt Lake City. UT 84104
Tet: (BOt) 974·9953

RAE. Ind. Elect. ltd' ,
3455 Gardner Ct
Burnaby. British Columbia
Canada V5G 4J7
Tel: 1604) 291·8866
TWX: 610929·3005

Hamilton/Avne! Eh~clronics
10 Industrial Rd.
Fairfield,07006
Tel: (201) 575·3490
(201) 575·3390

Schweber Electronics
18 Madison
Fairfield, NJ 07006 .
Tel: (201) 227·7880

NEW MEXICO
Alliance Electronics
11030 Cochiti S.E.

Arrow Electronics
938 Burke St.
Winston-Salem, NC 27102
Tel: (919) 725·8711
TWX: 510·928·0590
Hamilton/Avnet ElectroniCs
2803 Industrial Drive
Raleigh, NC 27609
Schweber electronics
1 Commerce Center
5285 North Blvd.
Ral'eigh, NC 27604
Tel: (919) 876·0000

Schweber Electronics
Prudential Business Campus
231 Gibraltal Road
Horsham, PA 19044
Tel: (215) 441·0600
Schweber Electronics
1000 RIDC Plaza Suite #203
Pittsburg, PA 15238
Tel: (412) 782-1600

TEXAS

Albuquerque, NM 87123
Tel: (505) 292·3360
TWX: 910·989·1151

OHIO

Arrow Electronics
t0125 Metropolitan Orive
Austin, TX 78758
Tel: (512) 835·4180
TWX: 910·874·1348

Arrow Electronics
2460 Alamo Avenue, S.E.
Albuquerque, NM 87106
Tel: (505) 243·4566
TWX: 910·989·1679

Arrow Electronics
7620 McEwen Road
Centerville, OH 45459
Tel: (513) 435·5563
TWX: 810·427·9409

Arrow Electronics
13715 Gamma Rd.
Dallas, TX 75234
Tel: (214) 386·7500
TWX: 910·860·5377

8ellindustries
11728 Linn, NE

Hamilton/Avnet Electronics
4588 Emery Industrial Parkway
Cleveland, OH 44128
Tel: (216) 831·3500

Arrow Electronics
10700 Corporate Dr.
Stafford, TX 77477
Tel: (713) 491·4100
TWX: 910·880·4439

Albuquerque, NM 87123
Tel: (505) 292·2700
TWX: 910·989·0625

Hamilton/Avne! Electronics
2524 Baylor S.E.
Albuquerque, NM 87106
Tel: (505) 765·1500

NEW YORK
Arrow Electronics
25 Hub St.
Mel.vilie. NY 11747
Tel: (516) 391-1609
Arrow Electronics
20 Oser Ave.
Hauppauge, NY 11787
Tel: (516) 231-1000
TWX: 510·227·66231
Arrow Electronics
3000 South Winton Rd.
Rochester, NY 14623
Tel: (716) 275·0300
HamiltonfAvnet Electronics
16 Corporate Circle
East Syracuse, NY 13057
Tel: (315) 437·2641
Hamilton/Avnet Electronics
5 Hub Drive
Melville, NY 11746
Tel: (516) 454·6060
Hamilton/Avnet Electronics
333 Metro Park
Rochester, NY 14623
Tel: (716) 475·9130
Pioneer/Harvey Electronics
640 Fairport Park
Fairport, NY 14450
Tel: (716) 381-7070
TWX: 510·253·7001
Pioneer/Harvey Electronics
1806 Vestal Parkway East
Vestal, NY 13850
Tel: (607) 748·8211
TWX: 510·252·0893
Schweber Electronics
Jericho Turnpike
Westbury, NY 11590
Tel: (607) 748·8211
TWX: 510·222·3660
Schweber Electronics
4 Townline Circle
Rochester, NY 14623
Tel: (716) 424·2222
Summit Distributors Inc.
916 Main st.
Buffalo, NY 14202
Tel: (716) 887·2800
TWX: 710·522·1692

Hamitton/Avnet Electronics
954 Senate Drive
Dayton, OH 45459
Tel: (513) 433·0610
Kierultf Electron'ics
23060 Miles Rd.
Bedford Heights, OH 44128
Tel: (216) 587-6558
TWX: 810·427·22821

Hamilton/Avnet Electronics
2401 Rutland Dr.
Austin, TX 78757
Tel: (512) 837·8911
Hamilton/Avnet Electronics
8750 West park Dr.
Houston, TX 77063
Tel: (713) 780·1771

Schweber Electronics
23060 Miles Rd.
Bedford Heights, OH 44128
Tel: (216) 587·6558
TWX: 810·427·2282

HamiltonlAvnet Electronics
2111 West Walnut Hill Lane
Irving, TX 75062
Tel: (214) 659·4111

Schweber Electronics
7865 Paragon Road
Suite 210
Centerville, OH 45459
Tel: (513) 439·1800

Kierulff Electronics
3007 Longhorn Blvd.
Suite 105
Austin, TX 78758
Tel: (512) 835·2090
TWX: 910·873·1359

OKLAHOMA
Arrow Electronics
4719 S. Memorial
Tulsa, OK 74145
Tel: (918) 665·7700
Kierulff Electronics
12318 E. 670th SI:
Tulsa;OK 74145
Tel: 1918) 252·7535
TWX: 910·845·2150
Schweber Electronics
4815 S. Sheridan Road
Suite #109
Tulsa, OK 74145
Tel: (918) 622·0000

OREGON
Hamilton/Avnet Electronics
6024 SW. Jean Rd.
Bldg. C, Suite 10
Lake Oswego, OR 97034
Tel: (503) 635·8157
Kierulff Electronics
14273 N.W. Science Park Dr.
Portland,. OR 97229
Tel: (503) 641·9150
TWX: 910·467·8753
Moore Elect. Inc.
15824 S.W. Upper Boones
Ferry Rd.
Lake Oswego, OR 97034
Tel: (503) 641·3131
TWX: 910·455·8183
Wyle Distribution
5289 N.E. Elam Young Pkwy.
Bldg. Eloo
Hillsboro, OR 97123
Tel: (503) 640·6000
TWX: 910·460·2203

WASHINGTON
Hami!tonlAvnel Electronics
14212 N.E. 21st St.
Bellvue, WA 98005
Tel: (206) 643·3950
Kierulff Electronics
1053 Andover Park East
Tukwilla. WA 98188
Tel: (206) 575·4420
TWX: 910·444·2034
Wyle Distribution Group
1750 132nd Ave .. NE
Bellevue, WA 98005
Tel: (206) 453·8300
TWX: 910·443·2526

WISCONSIN
Arrow Electronics
430 W. Rawson Ave.
Oak Creek. WI 53154
Tel: (414) 764·6600
TWX: 910·2621193
HamiltonfAvnet Electronics
2975 Moorland Rd.
New Berlin, WI 53151
Tel: (414) 784·4510
Kierulfl Electronics
2236 W. Bluemound Rd.
Waukesha, WI 53186
Tel: (414) 784·8160
TWX: 910·265·3653
Schweber Electronics
150 Sunnyslope Road
Suite 120
Brookfield, WI 53005
Tel: (414) 784·9020

CANADA
Canadian GE-ECO
189 Dufferin St.
• Toronto. OntariO
Canada M6K 1Y9
Tel: (418) 530·2700
TLX: 06·23238

Kierulfl Electronics
9610 Skillman Ave.
Dallas, TX 75243
Tel: (214) 343·2400
TWX: 910·861·2150

Cardinal Industrial Electronics
P.O. Box 12000
Edmonton. Alberta
Canada T5J 2P4
Tel: (403) 483·6266
TLX: 037·2372

Kierulff Electronics
10415 Landsbury Dr.
Houston, TX 77099
Tel: (713) 530·7030
TWX: 910·880·4057

Cardinal Industrial Electronics
10,5920 11th Street SE
Calgary, Alberta
Canada T2H 2M4
Tel: (403) 259·6817

Schweber Electronics
11 t W. Anderson Lane
Suite 209
Austin, TX 78752
Tel: (512) 458·8253

CESCO Elect. Ltd.
66 Colonnade Rd.
Nepean,Ont.
Canada K2E 7K7
Tel: (613) 226·6903

Schweber Electronics
4202 Beltway
Dallas, TX 75234
Tel: (214)·661·5010
TWX: 910·860·5493

CESCO Elect. Ltd.
4050 Jean Talon St. W
Montreal, Quebec
Canada H4P 1W1
Tel: (514) 735·5511
TWX: 610·421-3302

Schweber Electronics
10625 Richmond Ave.
Suite 1#100
Houston, TX 77042
Tel: (713) 784·3600
TWX: 910·881·4036

UTAH
Bell Industries
3639 West 2150 South
Salt Lake City, UT 84120
Tel: (801) 973·6913
TWX: 910·925·4072
HamiltonfAvnet Electronics
1585 West 2199 South
Salt Lake City. UT 84119
(801) 972-2900

8-34

CESCO Elect. Ltd
24 Martin Ross Ave.
Downsview. Ontario
Canada M3J 2K9
Tel: (416l661·0220
TLK 06·218213
CESCO Elect. Ltd.
,909Boul. Charest Quest
Quebec City. Quebec

~:tUf8?~M1f,

TLX: 051·3388

Electro Sonic
1100'Gordon Saker Rd.
Willowdale. Ontario
Canada M2H SB2
Tel: (4161499·1555
TLX: 065·25295

RAE. Ind. Elect. Ltd
11680 170lh st.
Edmonton, Alberta
Canada. T5S lJ7
Tel: (403) 451·4001
TLX: 037·2653
Zentronics
3300·14 Ave N.E.
Calgary. Alberta
Canada T2A 6J4
Tel: (403) 272·1021
Zentronics
8 Tilbury Court
Brampton. Ontario
Canada L5T3T4
Tel: (416) 451·9600
TLX: 06·97678
Zenlronics
564/10 Weber St. N

Waterloo, Ontario
Canada N2L 4C6
Tel: 1519) 884·5700
Zentronics
505 Locke Street
St. Laurent. Quebec
Canada. H4T lX7
Tel: (514) 735·5361
TLX: 05·827535
Zentronics
141 Catherine SI.
Ottawa. Ontario
Canada K2P 1C3
Tel: 1613) 238·64 t1
TLX 053·3636
Zentronics
108·11400 Bridgeport Road
Richmond. Be
Canada V6X 1T2
Tel: 1604) 273·5575
Zentronics
590 Berry Street

~~~~~ae~3~~~~oba
Tel: (204) 775·8661

INTERNATIONAL SALES OFFICES
U.S. AND CANADIAN
CORPORATE HEADQUARTERS

NORTHERN EUROPEAN
HEADQUARTERS

SOUTHERN EUROPEAN
HEADQUARTERS

IntersiI, Inc.

InterSil Datel(U.K.) Ltd.
Belgrave House

Intersil, Inc,
217, Bureaux de la Col line
Bat. D (2 EME ETAGE)
92213 Saint-Cloud Cedex

10710 N. Tantau Avenue
Cupertino, California 95014
Tel; (408) 996·5000
TWX; 910·338·2014

Basing View
Basingstoke, Hants., RG21 2YS
England
Tel; 0256·57361
TLX; 858041 INTRSL G

France
Tel: (1) 60258.98
TLX, INTEDAT 204280F

CENTRAL EUROPEAN
HEADQUARTERS

FAR EAST HDQTRS.
HONG KONG

FAR EAST HDQTRS.
JAPAN

Intersil Datel GmbH

Intersil Datel KK
Suyama Building
1-1-1 Ebisu Minami
Shibuya-Ku
Tokyo 150
Japan
Tel; (03) 793·1031
TLX; 2468205 (DACADC J)

Bavariaring 8, Concordiahau5

InterSii Datel Hong Kong Ltd.
Room 1603

8000 Muenchen 2

Perfect Commercial Bldg.

West Germany

20 Austin Ave., Tsimshatsui

Tel; 891530741
TLX; 5212855 IDl D

Kowloon, Hong Kong
Tel; 3·7214286·7
TLX; 39979 I NTDL HX

(

8·35

I!O~Dll
INTERNATIONAL DISTRIBUTORS
AUSTRALIA

INDIA

NETHERLANDS

TAIWAN

R&D Electronics Ply. Ltd.
P.O. Box 206
Burwood, Victoria 3125
Australia
Tel: 288-823218262
TLX: RADET AA 33288

Zenith Electronics
541, Panchratna
Mama Parmanand Marg.
Bombay 400 004
India
Tel: 384214
TLX: 011·3152 ZENITH

Auriema Nederland B.V.
Doornakkersweg' 26
5642 MP Eindhoven
Netherlands, Holland
Tel: 040-816565
TLX, 51992 AURI NL

Galaxy Far East Corp.
Room 4, 2nd F!. No. 312
Sec. 4 Chung Hsaio East Rd.
P.O. Box 36-12 Taipei
Taiwan, A.O.C.
Te" (02) 7811895-7
Cable: GALAXYER
TLX: 26110 GALAXYER

R&D Electronics Pty. Ltd.
133 Alexander S1.
P.O. Box 57
Crows Nest NSW 2065
Sydney, Australia
Tel: 439-5488
TLX, SECCO AA25468

AUSTRIA
Transistor Vertriebsges m.b.H.
AUhofstrasse 41 A
A-1130 Vienna
Austria
Tel, (02 22) 82 94 51182 94 04
TLX: 133738 TVGWN A

BELGIUM
Simac ElectroniCS SPRL
Rue Du Progres 52, Boite 3
8-1000 Brussels
Belgium
Tel: 02-2192453
TLX, 23662 SIME-IP-B

DENMARK
E.V. Johanssen Elektronik A-S
15, Titangade
DK-2200 Copenhagen N
Denmark

Tel: 45·1·839022
TLX, 16522 EVICAS OK

FINLAND
Nabla Elektroniikka Oy
P.O. Box 3
SF-021Ql Espoo 10
Finland
Tel: 90-46 28 29
TLX, 124270 NABLA SF

FRANCE
Tekelec-Airtronic
B.P. No.2
Cite des Bruyeres
Rue Carle-Vernel
92310 Sevres
France
Tel, (1) 534.75.35
TLX, TKLEC A 204552F
C.C.I:
Zone Induslrielle
5, Rue Marcelin Berthelot
92160 Antony
France
Tel, (1) 666.21.82
TLK 203881 F
C.C.!.
67, Rue Bataille
69008 Lyon
France

HONG KONG
Conmos Products Ltd.
11th Fir., Hay·Nien Building
#1 Tai Yip St.
Kwun Tong, Kowloon
Hong Kong
Tel: 3·7560103·8
TLX: 85448 CMOS HX
Electrocon Products, Ltd.
Rm. 603, 6th Floor
Perfect Commercial Bldg.
20 Austin Avenue, Tsimshatsui
Kowloon
Hong Kong
Tel: 3·687214·6
TLX, 39916 EPLET HX

INDIA-U.S. OFFICE
Fegu Electronics
2584 Wyandotte St.
Mountain View, California 94043
U.S_A.
Tel: (415) 961·2380
TLX, 176572 FEGU ELEC MNTV

ISRAEL
Vectronics Ltd.
60 Medinat Hayehudim St.
P.O. Box 2024
Herzlia B 46120
Israel
Tel' (052) 56070156071
TLX: 342579 VECQ IL

ITALY
Metroelettronica
Viale Girene, 18
20135 Milano
Italy
Tel: 546.26.41/546.59.41
TLX, 312168 METRON I
TLX, 315802 METRON I
Metroelettronica
Via G. Lorenzini, 12
00137 Roma. Italy
Tel: 827.28.41
Metroelettronica
Via Beaumont. 15
10138 Torino, Italy
Te!: 54.64.36
Eledra 3S S.P.A.
Viale Elvezia, 18
20154 Milano
Italy
Tel' (2) 349 751
TLX, 332 332

JAPAN
Intern ix, Inc.
Shinjuku Hamada Bldg. (7th Floor)
7-4-7 Nishi Shinjuku
Shinjuku-Ku
Tokyo 160,
Japan
Tel, (03) 369-1101
TLX: INTERNIX J26733
Internix, Inc.
Arai Bldg.
5·3·36 Tokiwagi
Uedashi, Nagano 386
Japan
Tel: (0268) 25-1610
Intern ix, Inc.
Takahashi Bldg. (Nishikan)
4·4-13 Nishi-tenma, Kita-ku
Osaka 530
Japan
Tel: 06·364·5971

KOREA
Duksung Trading Co.
Room 301 Jinwon Bldg.
507·30 Sinrim 4-00ng
Gwanak·Ku, Seoul
Republic of Korea
Tel: 856·9764
TLX: DUKSUNG K23459

NEW ZEALAND
Delphi Industries Ltd.
27 Ben Lomond Crescent
Pakuranga, Auckland
New Zealand
Tel: 563-259
TLK DELPHIC NZ21992

NORWAY
Hans H. Schive A/S
P.O. Box 15 .
Holmengt,28
N·1360 Nesbru
Norway
Tel, (02) 78.51_60
TLX, 19124 SKIVE N

PORTUGAL
Decada Espectral
Equipamentos de Electronica
e Cientificos, SARL
Av. Bombeiros Voluntarios, Lote 1028
Mirafiores/Alges
1495 Usboa
Portugal
Tel: 2-103420
TLK 15515 ESPEC P

SOUTH AFRICA
Electronic Bldg. Elements Pty. Ltd.
P.O. Box 4609
Pretoria 0001
Republic of South Africa
Tel: 46-922117
TLX: 30181 SA

SOUTH AMERICAU.S. OFFICE
lntectra
2629 Terminal Blvd.
Mountain View, California 94043
U.S.A.
Tel, (415) 967-8818
TLX: 345-545 INTECTRA MNTV

SPAIN

THAILAND
Science, Engineering, & Education Co., Ltd.
800/43·45 Asoke-Dindang Rd.
Samsennai, Huaykwang
Bangkok 10400
Thailand
Tel: 245-0390 or 245·9216
TLX: TH 81023 TVS

TURKEY
Turkelek Elektronik Ltd
Hatay Sokak #8
Ankara, Turkey
TeJ: 189483
TLX: 42 120 TRKL TR

UNITED KINGDOM
Farnel Electronic Components Ltd.
Canal Road
Leeds. LS12 2TU
England
Tel, (0532) 636311
TLX: 55147 FEC G
Hawke Elect. Ltd.
Amotex House
45, Hanworth Rd.
Sunbury on Thames
Middx
Tel, (01979) 7799
TLX, 923592
Quarndon Electronics
Semiconductor Ltd.
Slack Lane
Derby DE3 3ED
England
Tel' (0332) 32651
TLk 37163 QRNDON G
Macro-Marketing Ltd.
Burnham Lane
Slough, Berks SL 1 6LN
England
Tel: (06286) 4422
TLX: 847945 MACRO G

Amitron
CILoeches, 6 . Bajo D
Madrid 8
Spain
Te" (01) 246.58.63
TLX, 45550

Tranchant Electronics Ltd.
Tranchant House
53 Ormside Way
Redhill, Surrey RH1 2LS
England
Tel: (0737) 69217
TWX, 8953230 TRELEC G

SWEDEN

WEST GERMANY

Svensk Teleimport AB
Box 5071
S-162 05 ValHngby
Sweden
Tel,08-890265
TLX, 15372 PANTEL S

Spezial-Electronic KG
Hermann·Unggstr. 16
8000 Muenchen 2
West Germany
Tel: 89/530387
TLX: 5212176 SPEZ D

SWITZERLAND

Spezial-Electronic KG
Kreuzbreite 14
3062 Bueckeburg
West Germany
Tel, 05722 2030
TLX, 971624 SPEZ D

Laser & Electronic Equipment
Eierbrechtstrasse 47
8053 Zurich
Switzerland
Tel: 01 553330
TLX, 52124 LASEQ CH
Laser & Electronic Equipment
1227 Carouge - G~neve
Bureau Suisse Romande
1227 Carouge-Geneve
Switzerland
Tel: 022 425 677
TLX; 421 343

8·36

Spezial-Electronic KG
Magdeburgerstrasse 15
7090 Ellwangen
West Germany
Tel, (07961) 4047
TLX: 74712 SPEZ D
Spezial-Electronic KG
Hanauer Str. 4
6360 Friedberg
West Germany
Tel: 06031/4634
TLX: 4184025 SPEZ D

EXPLANATION OF TERMS, INDICES
AND SPECIAL SUBSECTIONS
PRODUCTION DATA SHEET
This is a full, final data sheet, and describes a
mature product in full production. Although Intersil
reserves the right to make changes in specifications
contained in these data sheets at any time without
notice, such changes are not common and are usual·
Iy minor, generally relating to yield and processing
improvements. These data sheets are not marked;
others are marked preliminary.
PRELIMINARY DATA SHEET
A preliminary data sheet is issued in advance of the
availability of production samples and generally in·
dicates that at the time of printing, the device had not
been fully characterized. In the case of a second·
source part, the specifications are already determined,
and a "preliminary" designation indicates the an·
ticipated availability of the device.
ALPHANUMERIC INDEX
This part number index is arranged first by alpha sequence, (ie: ADCxxxx, DGxxx, Gxxx, ICLxxxx, ICMxxxx,
etc.) then by numeric sequence (ie: LM100, LM101A,
LM102, LM105, etc.) and ignoring package/temperature/
pin number suffixes. The basic numbering sequence,
is sorted by reading the part number characters from
left to right. Reading the left character first (which is
usually an alpha character), then the next character to
the right and so forth.
BASE NUMBER INDEX
If only the basic part number is known, use the Base
Number Index as a locator aid. The Base Number Index is organized in numeric sequence (with alpha
prefixes appearing in bold type and numeric
characters set in medium type). Devices are arranged
in this index according to the numeric value of the
first digit on the left, then the value of the second
digit, then the third, and so on. For example, device
number ICM7218 precedes ICL741, no package/temperature/pin number suffixes are included, but these may
be obtained from the specific product data sheet.
FUNCTION INDEX
This is an index of Intersil device types categorized by
product grouping and function. The first major subsection, DISCRETES, is further subdivided into categories
for JFETs and Special Function devices.
All remaining major subsections (ANALOG SWITCHES/MULTIPLEXERS, DATA ACQUISITION, LINEAR,
TIMERS/COUNTERS, TIMEKEEPING/DTMF,
MEMORIES and MICROPROCESSORS/PERIPHERALS)

are organized alphabetically by function. The Functional Index appears in its entirety in section A, and an
appropriate subindex appears at the beginning of each
major product section.
CROSS-REFERENCE GUIDES
Two cross-reference guides are provided: one for
Discrete Devices and one for Integrated Circuits.
The Discrete Cross-Reference Guide indicates
whether Intersil can provide the industry-standard
type, or an Intersil preferred part instead.
The IC Alternate Source Cross-Reference Guide lists
competitive manufacturer device types for which Intersil makes pin-for-pin replacements. In the left-hand column, the competitive device part number is organized
alphabetically by manufacturer. The Intersil pin-for-pin
replacement appears in the right hand column.
SELECTOR GUIDES
Selectorguide tables appear at the front of each major
product category subsection and provides a quick
reference of key parameters for devices contained in
that section.
DEVICE FUNCTION/PACKAGE CODES
Package dimensions and diagrams explaining device
prefix and suffix codes appear in Appendix B.
DIE SELECTION CRITERIA
Many of Intersil's semiconductor products are
available in die form. This subsection of Appendix B
contains general information on 'criteria for transistor
and integrated circuit die selection, including physical
parameters, packaging for shipment, assembly, testing
and purchase options.
HIGH-RELIABILITY PROCESSING
This subsection of Appendix B defines Intersil's commitment to 100 percent compli~nce with MIL-STD-883,
MIL-STD-750, MIL-M-38510 and MIL-S-19500 specifications. It also outlines Intersil's programs for quality
conformance, quality testing and limited use qualification and includes a glossary of military/aerospace HiRei terms.

Intersil reserves the right to make changes in circuitry or
specifications contained herein at any time without notice.
Intersil assumes no responsibility for the use of any circuits
described herein and makes no representations that they are
free patent i nfri ngement.

LIFE SUPPORT POLlCY.INTERSIL·S PRODUCTS ARE NOT AUTHORIZED, NOR WARRANTED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES
AND/OR SYSTEMSWITHOUT,JHE EXPRESS WRITIEN APPROVALOF INTERSIL, INC.

For the purposes of this policy, critical components in life support systems and/or devices are defined as:

1. A critical component is any component of a life support device or system
whose failure to perform can be reasonably expected to cause the failure of
the life support device or system, or to affect its safety or effectiveness.

2. Life support devices or systems are devices or systems which, (a) are in·
tended for surgical implant into the body, or (b) support or sustai,n life, and
whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to
result in a significant injury to the user.

Intersil cannot assume responsibility for use of any circuitry described other than circuitry entirely embodied in an Intersil product. No circuit patent licenses are
implied. Intersll reserves the right to change the circuitry and specifications without notice at any time.

m

TABLE OF CONTENTS

GENERAL INFORMATION/CROSS REFERENCES

D
II

II
II

III
II
_

DISCRETES
DIGITAL
ANALOG SWITCHES AND MULTIPLEXERS
DATA ACQUISITION
LINEAR
TIMERS, COUNTERS, AND DISPLAY DRIVERS
CONSUMER CIRCUITS

I:) APPENDICES/PHYSICAL DIMENSIONS
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:08:13 11:06:30-08:00
Modify Date                     : 2017:08:13 11:51:13-07:00
Metadata Date                   : 2017:08:13 11:51:13-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:e7c4610e-99a7-0e41-be9f-2e15855a2c99
Instance ID                     : uuid:b14173f2-e2b4-6047-a7f1-00ba4d9c35e3
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 968
EXIF Metadata provided by EXIF.tools

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