1983_Memory_Component_Handbook 1983 Memory Component Handbook
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LITERATURE
1983 will be a year of transition for Intel's catalog program. In order to better serve you, our
customers, we are reorganizing many of our catalogs to more completely reflect product groups.
In addition to the new product line handbooks listed below, an INTEL PRODUCT GUIDE (Order No.
210846) will be available free of charge in March. This GUIDE will contain a listing of Intel's complete
product line along with information on quality/reliability, packaging and ordering,customer training
classes and product services.
Consult the Intel Literature Guide (no charge, Order No. 210620) for a complete listing of Intel
literature. Literature is presently available in other forms for those handbooks that will not be
published until later in the year. Write or call the Intel Literature Department, 3065 Bowers Avenue,
Santa Clara, CA 95051, (800) 538-1876, or (800) 672-1833 (California only).
HANDBOOKS
Memory Components Handbook (Order No. 210830)
Contains all application notes, article reprints, data sheets and other design
information on RAMs, DRAMs, EPROMs, E2 PROMs, Bubble Memories.
Microcontroller Handbook (Available in May)
Contains all application notes, article reprints, data sheets, and other user information
on the MCS-48, MCS-51 (8-bit) and the new MCS-96 (16-bit) product families.
Military Handbook (Order No. 210461)
Contains complete data sheets on all military products.
Microprocessor and Peripherals Handbook (Order No. 210844)
Contains data sheets on all microprocessors and peripherals. (Individual User
Manuals are also available on the 8085, 8086, 8088, 186, 286, etc.)
Development Systems Handbook (Available in April)
Contains data sheets on development systems and supporting software.
OEM Systems Handbook (Available in May)
Contains all application notes, article reprints and data sheets for OEM boards
and systems.
Software Handbook (Available in May)
Contains software product overview as well as data sheets for all Intel software.
Quality/R,liability Standards Handbook (Available in April)
MEMORY COMPONENT
HANDBOOK
1983
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear in this document nor does it make a commitment to update the information contained herein.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
BXp, CREDIT, i, ICE, 12 1CE, ICS, iDBp, iDIS, iLBX, i m , iMMX,
Insite, INTEL, intel, Intelevision, Intellec, inteligent IdentifierT. ,
intelBOS, inteligent Programming T. , Intellink, iOSP, iPDS,
iRMS, iSBC, iSBX, iSDM, iSXM, Library Manager, MCS,
Megachassis, Micromainframe, MULTI BUS, Multichannel T •
Plug-A-Bubble, MULTI MODULE, PROMPT, Ripplemode,
RMX/80, RUPI, System 2000, and UPI, and the combination of
ICE, iCS, iRMX, iSBC, MCS, or UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of
Mohawk Data Sciences Corporation.
* MULTI BUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
literature Department
3065 Bowers Avenue
Santa Clara, CA 95051
©INTEL CORPORATION. 1982
Table of Contents
Alphanumeric Index ........ ',' . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
v
CHAPTER 1
Memory Overview ......... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
CHAPTER 2
Intel Memory Technologies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-1
CHAPTER 3
RAMs (Random Access Memories)
APPLICATION NOTES
AP-74 High Speed Memory System Design Using 2147H . . . . . . . . . . . . . . . . . . . . . . . . .
AP-131 Intel 2164A 64K Dynamic RAM Device Description .........................
AP-132 Designing Memory Systems with the 8K x 8 iRAM (2186/87) . . . . . . . . . . . . . . . ..
AP-133 DeSigning Memory Systems for Microprocessors Using the Intel 2164A
and 2118 Dynamic RAMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-97 A Interfacing Dynamic RAMs to iAPX 86, 88 Systems ..................... , ..
AP-141 8203/8206/2164A Memory Design ......................................
AP-46 Error Detecting and Correcting Codes Part I ..............................
AP-73 ECC #2 Memory Systems Reliability with ECC ............................
ARTICLE REPRINTS
AR-189 Keep Memory Design Simple Yet Cull Single-Bit Errors ...................
AR-197 Better Processor Performance Via Global Memory (2164A) ..................
DATA SHEETS
2114A, 1024 x 4-Bit Static RAM ..............................................
2115N2125A Family, High Speed 1K x 1-Bit Static RAM ..........................
2115H/2125H Family, High Speed 1K x 1-Bit Static RAM ..........................
2118 Family 16,384 x 1-Bit Dynamic RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2141, 4096 x 1-Bit Static RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2147H High Speed 4096 x 1-Bit Static RAM .....................................
2148H, 1024 x 4-Bit Static RAM ..............................................
2149H, 1024 x 4-Bit Static RAM ..............................................
2164A Family 65,536 x 1-Bit Dynamic RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2186, 8192 x 8-Bit Integrated RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
8203 64K DynamiC RAM Controller ...........................................
8206 Error Detection and Correction Unit .......................................
8207 Advanced Dynamic RAM Controller ......................................
RAM Family Express Data Sheet ................................ : . . . . . . . . . . ..
3-1
3-22
3-40
3-70
3-110
3-146
3-151
3-164
3-209
3-217
3-224
3-228
3-233
3-238
3-249
3-255
3-259
3-263
3-267
3-281
3-288
3-303
3-322
3-348
CHAPTER 4
EPROMs (Erasable Programmable Read Only Memories)
APPLICATION NOTES
AP-151 The Inteligent Programming™ Algorithm Fast Programming
for Intel EPROMs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DATA SHEETS
2716, 16K (2K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2732A, 32K (4K x 8)UV Erasable PROM .......................................... "
2764, 64K (8K x 8) UV Erasable PROM ........................................... "
27128, 128K (16K x 8) UV Erasable PROM. .. ...... .. ... ... .. . ........... ... .. .. . ...
27256, 256K (32K x 8) UV Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Express Data Sheet ............................. : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iii
4-1
4-5
4-12
4-19
4-29
4-39
4-40
CHAPTER 5
E2PROMs (Electrically Erasable Programmable Read Only Memories)
1982-1983 Designer's Guide to E2PROM Products ..............................
5-1
APPLICATION NOTES
AP-100 Reliability Aspects of a Floating Gate E2PROM . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-16
AP-136 A MULTIBUS®-Compatible 2816' E2PROM Memory Board Description. . . . . . .. 5-23
AP-148 2817 Using the 2817 Intelligent E2 PROM............................... 5-67
ARTICLE REPRINTS
AR-11916-K EE-PROM Relies On Tunneling For Byte-Erasable Program Storage...... 5-74
AR-174 Hardware a Software Download Techniques with 2816 .............. '.' . .. 5-80
AR-230 ROMs That Erase One Byte at a Time .................................. 5-85
DATA SHEETS
2815, 16K (2K x 8) Electrically Erasable PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-90
2816, 16K (2K x 8) Electrically Erasable PROM ................................. 5-103
2816A, 16K (2K x 8) Electrically Erasable PROM ................................ 5-116
2817, 16K (2K x 8) Electrically Erasable PROM ................................. 5-128
CHAPTER 6
Bubble Memory
Magnetic Bubble Primer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APPLICATION NOTES
AP-119 Microprocessor Interface for the BPK 72 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
AP-127 Powerfail Considerations for Magnetic Bubble Memories. . . . . . . . . . . . . . . ..
AP-150 8085 to BPK 72 Interface ......... " .. , , , . , , ... , , ' , .. , .. , ' ... , . , ' . , . , , ..
ARTICLE REPRINTS
AR-243 Thin-film Detectors X-ray Lithography Deliver 4-Mbit Bubble Chip .. , , , ..... , '.
AR-250 Bubble Chip Packs 4 Mbits Into 1-Mbit Space, . , , , , , , . , , , . , , , , , , , , ..... ,
DATA SHEETS
BPK 72 Bubble Storage Prototype Kit ,:" ... ,.,', .... ,", .. , .. ,',.".,.,",.,'
BPK 70 1 Megabit Bubble Storage Subsystem " " , ... , .... , ... ,',., ... , .. , ... ,'
7110, 1 Megabit Bubble Memory Family ., ... , .. ,., .... " .. " ...... " . , " " " "
7220-1, Bubble Memory Controller, .. , .. , .... , . , , , .. , . , , .. , , , ..... , ......... "
7230, Current Pulse Generator for Bubble Memories ........... , ... , . , , ... , ' , , , "
7242, Dual Formatter/Sense Amplifier for Bubble Memories. , .. , ... , . , , , , , , ... , .. ,.
7250, Coil Pre-Driver for Bubble Memories " ... , ... ,",.','.' .. , .. ,"', ........
7254, Quad VMOS Drive Transistors for Bubble Memories. , , . , . , , . , . , .. , , , , . . . . . ..
7114, 4-Megabit Bubble Memory ... ',"",.,"",., ... ,', .. "., .. ,.,., ... ,....
6-1
6-15
6-64
6-86
6-158
6-160
6-169
6-172
6-176
6-184
6-199
6-204
6-216
6-220
6-223
CHAPTER 7
Packaging Information . ... ' , ' .. , " , . , . , , . , .. , , .,. , ' .,. , .... ' .. , ,. , . , .. , . , .... "'" , , , .. , '. , . 7-1
iv
Alphanumeric Index
2114,1024 x 4-Bit Static RAM ...................................................................... 3-224
2115A/2125A Family, High Speed 1K x 1-Bit Static RAM ............................................. 3-228
2115H/2125H Family, High Speed 1K x 1-Bit Static RAM.... .................. ..........
. .... 3-233
2118 Family 16,384 x 1-Bit Dynamic Ram....... .... .................................. ..... .. 3-70,3-238
2141,4096 x 1-Bit Static RAM .......................................................................... 3-249
2147H High Speed 4096 x 1-Bit Static RAM.................... ..
. .................... , ........ 3-1, 3-255
2148H High Speed 1024 x 4-Bit Static RAM. ......... ........ .. .......
. .......... ...... . .3-259
2149H High Speed 1024 x 4-Bit Static RAM ................... , ............ , .......................... 3-263
2164A 65,536 x 1-Bit Dynamic RAM .............................................. 3-22, 3-70,,3-146, 3-217, 3-267
2186,8192 x 8-Bit Integrated RAM ................................................................ 3-40, 3-281
27128, 128K (16K x 8) UV Erasable PROM ........................................................... 4-29
2716, 16K (2K x 8) UV Erasable PROM ................................................................... 4-5
27256, 256K (32K x 8) UV Erasable PROM ............................... . . . . . . . . .. .
. . . .. . .. 4-39
2732A, 32K (4K x 8) UV Erasable PROM ................................. : ............................. 4-12
2764, 64K (8K x 8) UV Erasable PROM ..................................................... _............... 4-19
2815, 16K (2K x 8) Electrically Erasable PROM ............................................................ 5-90
2816, 16K (2K x 8) Electrically Erasable PROM ......................................... 5-16, 5-23, 5-80, 5-103
2816A, 16K (2K x 8) Electrically Erasable PROM..... . ................................................ 5-116
2817, 16K (4K x 8) Electrically Erasable PROM.........................
. .................. 5-67,5-128
7110,1 Megabit Bubble Memory Family .............................................................. 6-176
7114, 4-Megabit Bubble Memory ................................................................. :6-223
7220-1, Bubble Memory Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ............ 6-64,6-86,6-184
7230, Current Pulse Generator for Bubble Memories. . . . . . . . . . . . . . . . . . . . . . . .. . ......................... 6-199
7242, Dual Formatter/Sense Amplifier for Bubble Memories.... . .... ......
. .................. 6-204
7250, Coil Pre-driver for Bubble Memories.. .. .... ... ... ... ..... .......... .
. .................. 6-216
7254, Quad VMOS Drive Transistors for Bubble Memories ........................................ 6-220
8085 Microprocessor. "'.. . .................................................. .............. ........ . .. 6-86
8202A Dynamic RAM Controller ...................................................................... 3-110
8203 64K Dynamic RAM Controller ...................................................... 3-110, 3-146, 3-288
8206 !=rror Detection and Correction Unit .................................................. 3-146, 3-209,3-303
8207 Advanced Dynamic RAM Controller........................... .... .....
. ..... , ............ 3-322
BPK 70, 1 Megabit Bubble Storage Subsystem. . . .. .. ............. ................. .............. ..6-172
BPK 72, Bubble Storage Prototype Kit .......................................................... 6-15,6-169
iAPX-8616-Bit HMOS Microprocessor ................................................................ 3-110
iAPX-88 8-Bit HMOS Microprocessor .................................................................... 3-110
v
PREFACE
This handbook has been prepared to provide a comprehensive grouping of
technical literature covering Intel's memory products, with special emphasis
on microprocessor applications. In addition, a brief summary of current
memory technologies and basic segmentation of product lines is provided.
Memory Overview
1
CHAPTER I: MEMORY OVERVIEW
Joe Altnether
MEMORY BACKGROUND
AND DEVELOPMENT
store important data on a non-volatile medium before
the power goes down.
Only ten years ago MOS LSI memories were little more
than laboratory curiosities. Any engineer brave enough
to design with semiconductor memories had a simple
choice of which memory type to use. The 2102 Static
RAM for ease of use or the 1103 Dynamic RAM for low
power were the only two devices available. Since then,
the memory market has come a long way, the types of
memory devices have'proliferated, and more than 3,000
different memory devices are now available. Consequently, the designer has a lot to choose from but the
choice is more difficult, and therefore, effective memory
selection is based on matching memory characteristics
to the application.
Despite their volatility, RAMs have become very popular, and an industry was born that primarily fed computer
systems' insatiable appetites for higher bit capacities
and faster acc,ess speeds.
RAM Types
Two basic RAM types have evolved since 1970. Dynamic
RAMs are noted for high capacity, moderate speeds
and low power consumption. Their memory cells are
basically charge-storage capacitors with driver transistors. The presence or absence of charge in a capacitor is interpreted by the RAM's sense line as a logical
1 or 0, Because of the charge's natural tendency to distribute itself into a lower energy-state configuration,
however, dynamic RAMs require periodic charge refreshing to maintain data storage,
Memory devices can be divided into two main categories: volatile and non-volatile. Volatile memories retain their data only as long as power is applied. In a great
many applications this limitation presents no problem.
The generic term random access memory (RAM) has
come to be almost synonymous with a volatile memory
in which there is a constant rewriting of stored data.
Traditionally, this requirement has meant that system
designers had to implement added circuitry to handle
dynamic RAM subsystem ref~esh. And at certain times,
refresh procedures made the RAM unavailable for writing or reading; the memory's control circuitry had to arbitrate access. However, there are now two available
alternatives that largely offset this disadvantage. For
relatively small memories in microprocessor environments, the integrated RAM or iRAM provides all
of the complex refresh circuitry on chip, thus, greatly
simplifying the system design. For larger storage requirements, LSI dynamic memory controllers reduce
the refresh requirement to a minimal design by offering a monolithic controller solution.
In other situations, however, it is imperative that a nonvolatile device be used because it retains its data
whether or not power is applied. An example of this requirement would be retaining data during a power
failure. (Tape an'd disk storage are also non-volatile
memories but are not included within the scope of this
book which confines itself to solid-state technologies in
an IC form factor.)
Thus, when considering memory devices, it's helpful to
see how the memory in computer systems is segmented
by applications and then look at the state-of-the-art in
these cases.
Where users are less:concerned with space and cost
than with speed and reduced complexity, the second
RAM type - static RAMs - generally prove best.
Unlike their dynamic counterparts, static RAMs store
ones and zeros using traditional flip-flop logic-gate con-'
figurations. They are faster and require no refresh. A
user simply addresses the static RAM, and after a very
brief delay, obtains the bit stored in that location, Static
devices are also simpler to desigh with than dynamic
RAMs, but the static cell's complexity puts these non- ,
volatile chips far behind dynamics in bit capacity per
square mil of silicon.
Read/Write Memory
First examine read/write memory (RAM), which permits
the access of stored memory (reading) and the ability
to alter the stored data (writing).
Before the advent of solid-state read/write memory,
active data (data being processed) was stored and retrieved from non-volatile core memory (a magneticstorage technology). Solid-state RAMs solved the size
and power consumption problems associated with core,
but added the element of volatility. Because RAMs lose
their memory when you turn off their power, you must
leave systems on all the time, add battery backup or
The iRAM
There is a way, however, to gain the static RAM's
design-in simplicity but with the dynamiC RAM's higher
1-1
MEMORY OVERVIEW
capacity and other advantages. An integrated RAM or
iRAM integrates a dynamic RAM and its control and
refresh circuitry on one substrate, creating a chip that
has dynamic RAM density characteristics, but looks like
a static RAM to users. You simply address it and collect
your data without worrying about refresh and arbitration.
The first ROMs contained cell arrays in which the sequence of ones and zeros was established by a metal ization interconnect mask step during fabrication. Thus,
users had to supply a ROM vendor with an interconnect
program so the vendor could complete the mask and
build the ROMs. Set-up charges were quite high - in
fact, even prohibitive unless users planned for large
volumes of the same ROM.
Before iRAM's introduction, users who built memory
blocks smaller than 8K bytes typically used static
RAMs because the device's higher price was offset by
the support-circuit simplicity. On the other hand, users
building blocks larger than 64K bytes usually opted for
dynamic RAMs because density and power considerations began to take precedence over circuit complexity issues.
To offset this high set-up charge, manufactu'rers developed a user-programmable ROM (or PROM). The first
such devices used fusible links that could be melted or
"burned" with a special programmer system.
Once burned, a PROM was just like a ROM. If the burn
program was faulty, the chip had to be discarded. But,
PROMs furnished a more cost-effective way to develop
program memory or firmware for low-volume purposes
than did ROMs.
For the application area between these two limits, decisions had to depend on less straightforward tradeoffs.
But iRAMs could meet this middle area's needs (See
Figure 1).
Read-Only Memory
As one alternative to fusable-link programming, Intel
pioneered an erasable MOS-technologyPROM (termed
an EPROM) that used charge-storage programming. It
came in a standard ceramic DIP package but had a window that permitted die exposure to light. When the chip
was exposed to ultraviolet light, high energy photons
could collide with the EPROM's electrons and scatter
them at random, thus erasing the memory.
Another memory class, read-only memory (ROM), is
similar to RAM in that a computer addresses it and then
retrieves data stored at that address. However, ROM includes no mechanism for altering the data stored at that
address - hence, the term read only.
ROM is basically used for storing information that isn't
subject to change - at least not frequently. Unlike
RAM, when system power goes down, ROM retains its
contents.
The EPROM was obviously not intended for use in
read/write applications, but it proved very useful in
research and development for prototypes, where the
need to alter the program several times is quite common. Indeed, the EPROM market consisted almost exclusively of development labs. As the fabrication process became mature, however, and volumes increased,
EPROM's lower prices made them attractive even for
medium-volume production-system applications.
ROM devices became very popular with the advent of
microprocessors. Most early microprocessor applications were dedicated systems; the system's program
was fixed and stored in ROM. Manipulated data could
vary and was therefore stored in RAM. This application
split caused ROM to be commonly called program
storage, and RAM, data storage.
8K
16K
SYSTEM RAM BLOCK SIZE (BYTES)
Figure 1. System Cost Graph
1-2
64K
.".
MEMORY OVERVIEW
During a read operation, the chips use conventional + 5
Volt power.
Another ROM technology advance occurred in 1980
with the introduction of Intel's 2816- a 16K ROM that's
user programmable and electrically erasable. Thus, instead of removing it from its host system and placing it
under ultraviolet light to erase its program, the 2816 can
be reprogrammed in iis socket. Moreover, single bits or
entire bytes can be erased in one operation instead of
erasing the entire chip.
Bubble MemQry
A very different device type, bubble memory was once
considered the technology that would obsolete RAM
components. This view failed to consider the inherent
features and benefits·of each technology. There is no
question that RAMs have staked out a read/write applications area that is vast. Nevertheless, their volatility
presents severe problems in more than a few applications. Remote systems, for example, might be unable
to accept a memory that is subject to being wiped out
should a power failure occur.
Such E2 PROMs (for electrically erasable programmable ROM) are opening up new applications. In pointof-sale terminals, for example, each terminal connects
to a central computer but each can also handle moderate amounts of local processing. An E2PROM can store
discount information to be automatically figured in during a sales transaction. Should the discount change, the
central computer can update each terminal via telephone
lines by reprogramming that portion of the E2PROM
(Figure 2).
Bubble memories use a magnetic storage technique,
roughly similar to the core memory concept but on a
much smaller size and power-consumption scale. They
are non-volatile and physically rugged. Thus, their first
clear applications target has been in severe-environment
and remote system sites. Portable terminals represent
another applications area in which bubbles provide unique
benefits.
In digital instrumentation, an instrument could become
self-calibrating using an E2PROM. Should the instrument's calibration drift outside specification limits, the
system could employ a built-in diagnostic to reprogram
a parametric setting in an E2PROM and bring the
calibration back within limits.
Considering bubble products, Intel's latest design provides 1,048,576 bits of data storage via a defect-tolerant
technique that makes use of 1,310,720 total bits (Figure
3). Internally, the product consists of 256 storage loops'
of 4,086 bits each. Coupled with available control
devices, this single chip can implement a 128K byte
memory subsystem.
E2PROMs contain floating-gate tunnel-oxide (Flotox)
-cell structure. Based on electron tunneling through a
thin (less than 200 Angstroms) layer of silicon dioxide,
these cells permit writing and erasing with 21 Volt pulses.
,....-------""1
10 DIGIT
UNIVERSAL
PRODUCT
UNIT
PRICE
CODE
KEYBOARD
CODE
SCANNER
TO INVENTORY
RECORD
Figure 2_ Typical E2PROM Application
1-3
PRODUCl
DESCRIPTION
(15 bytes)
I
MEMORY OVERVIEW
~----------------,
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
TO
8080
8085
8088
8086
I
7220.,
BUBBLE
MEMORY
CONTROLLER
(BMC)
TO
ADDITIONAL
BPK70'.
Figure 3. Intel Model 7110 Bubble Memory
memory. Each of these factors plays a important role in
the final selection process.
SEGMENTATION OF MEMORY DEVICES
Besides the particular characteristics of each device
that has been discussed, there are a number of other
factors to consider when choosing a memory product,
such as cost, power consumption, performance, memory architecture and organization, and size of the
Performance
Generally, the term performance relates to how fast the
device can operate in a given system environment. This
1-4
MEMORY OVERVIEW
parameter is usually rated in terms of the access time.
Fast SRAMs can provide access times as fast 20 ns,
while the fastest DRAM cannot go much beyond the 100
ns mark. A bipolar PROM has an access time of 35 ns.
RAM and PROM access is usually controlled by a signal
most often referred to as Chip Select (CS). CS often appears in device specifications. In discussing access
times, it is important to remember that in SRAMs and
PROMs, the access time equals the cycle time of the
system whereas in DRAMs, the access time is always
less than the cycle time.
cations, the use of devices made by the CMOS technology have a distinct advantage over the NMOS products. CMOS devices offer power savings of several
magnitudes over NMOS. Non-volatile devices such as
E2PROMs are usually independent of power problems
in these applications.
Power consumption also depends upon the organization of the device in the system. Organization usually
refers to the width of the memory word. At the time of
their inception, memory devices were organized as
nK x 1 bits. Today, they are available in various configurations such as 4Kx 1, 16Kx 1, 64Kx 1, 1Kx 4, 2Kx 8,
etc. As the device width increases, fewer devices are required to configure a given memory word - although
the total number of bits remains constant. The wider
organization can provide significant savings in power
consumption, because a fewer number of devices are
required to be powered up for access to a given memory
word. In addition, the board layout design is simpler due
to fewer traces and better layout advantages. The wider
width is of particular advantage in microprocessors and
bit-slice processors because most microprocessors are
organized in 8-bit or 16-bit architectures. A memo~y chip
configured in the nKx8 organization can confer a definite
advantage - especially in universal site applications.
All non-volatile memories other than bubble memories
are organized nKx8 for this very reason.
Cost
There are many ramifications to consider when evaluating cost. Cost can be spread over factors such as
design-in time, cost per device, cost per bit, size of
memory, power consumption, etc.
Cost of design time is directly proportional to design
complexity. For example, SRAMs generally require less
design-in time than DRAMs because there is no refresh
circuitry to consider. Conversely, the DRAM provides
the lowest cost per bit because of its higher packing
density.
Memory Size
Memory size is generally specified in the number of
bytes (a byte is a group of eight bits). The memory size
of a system is usually segmented depending upon the
general equipment category. Computer mainframes
and most of today's minicomputers use blocks of RAM
substantially beyond 64K bytes - usually in the hundreds of thousands of bytes. For this size of memory,
the DRAM has a significantly lower cost per bit. The additional costs of providin.g the refresh and timing circuitry are spread over many bits.
Types of Memories
The first step to narrowing down your choice is to cletermine the type of memory you are designing - data
store or program store. After this has been done, the
.
next step is to prioritize the following factors:
Performance
Power Consumption
Density
Cost
The microprocessor user generally requires memory
sizes ranging from 2K bytes up to 64K bytes. In memories of this size, the universal site concept allows maximum flexibility in memory design.
Global Memory
Generally, a global memory is greater than 64K bytes
and serves as a main memory for a microprocessor
system. Here, the use of dynamic RAMs for read/write
memory is dictated to provide the highest density and
lowest cost per bit. The cost of providing refresh circuitry
for the dynamic RAMs is spread over a large number of
memory bits, thus minimizing the cost impact. Bubbles
would also be an excellent choice for global memory
where high performance is not required. In addition,
bubbles offer low cost per bit and non-volatility.
Power Consumption
Power consumption is important because the total
power required for a system directly affects overall cost.
Higher power consumption requires bigger power supplies, more cooling, and reduced device density per
board - all affecting cost and reliability. All things considered, the usual goal is to minimize power. Many
memories now provide automatic power;down. With today's emphasis on saving energy and" reducing cost,
the memories that provide these features will gain an increasingly larger share of the ",arket.
Local Memory
Local memories are usually less than 64K bytes and
reside in the proximity of the processor itself - usually
on the same PC board. Two types of memories are
In some applications, extremely low power consumption
is required, such as battery operation. For these appli-
1-5
intJ
MEMORY OVERVIEW
often used in local memory applications: RAMs and
E2PROMs/EPROMs. These devices all offer universal
.
site compatibility and density upgrade.
vices have on chip address latches. Yet with respect to
the system, one device operates synchronously and the
other asynchronously.
Synchronous and Asynchronous Memories
Therefore, in considering memory devices or systems,
that operate within a specified cycle time, Intel defines
a synchronous memory as one that responds in a prediptable and sequential fashion, always providing data
within the same time frame from the clock input"This
allows a system designer to take advantage of the
predictable access time and maximize his system performance by reducing or eliminating WAIT states.
Historically, there have been several definitions of convenience when describing synchr.onous~and asynchronous memory devices. The, question of which
definition is the more appropriate boils down to a
philosophical decision, and depends on whetl1er the
definition is narrowed to component operating parameters or expanded to system operating parameters.
One popular and accepted definition defines the two
types of memories by relying on the most apparent difference. The synchronous memory possesses an internal address register which latches the current device
address, but the asynchronous device lacks this capability. The logic of this definition is easy to follow: Register
transfer or sequentjallogic is considered synchronous
because it is clocked by a common periodic signal the system clock. Memories with internal address registers are also internally sequential logic arrays clocked
by a signal, common throughout the memory system,
and are, therefore, synchronous.
By the foregoing definition, asynchronous memories
would require the device address be held valid on the
bus throughout the memory cycle. Static RAMs fall into this category. In contrast, synchronous memories require the address to be valid only for a very short period
of time just before, during, and just after the arrival of
the address register clock. DRAMs and clocked static
RAMs fall into this category.
Intel defines an asynchronous memory as one that
(within the framework of the memory cycle specifications) does not output data in a predictable and repeatable time frame with respect to system timing. This is
generally true of DRAM systems, where a refresh cycle,
which occurs randomly skewed to the balance of the
system timing, may be in progress at the time of a
memory cycle request by the CPU. In this case, provision must be made to re-synchronize the system to the
memory - usually with a READY signal. The 2186
iRAMs fit into this' category, while the 2187 iRAMs are
considered synchronous devices.
These definitions are somewhat broader in scope than
those chosen in the past; however, as systems become
implemented in silicon, a more global definition is required to encompass those former systems that are now
silicon devices.
SUMMARY
Table 1 provides a summary of the various memory
devices that have been discussed.
With the introduction of the 2186 and 2187 iRAMs, the
preceding definition no longer fits, because both de-
Table 1. Segmentation of Memory Devices
Operating
From
Read Speed
Slow
Fast
Mass
Boot
Monitor
Buffer
Bubbles
Disk
EPROM
EPROM
Bytewide
Diagnostics E"/EPROM!
RAM
Operating
System
E"/EPROM!
APP/PGM/
RAM
Data Store
Bubbles
Write Speed
Fast
Slow
Down
Load
Bubbles
Disk
N/A
N/A
,N/A
N/A
Bytewide Bubbles
N/A
Bytewlde
E"PROM
N/A
N/A
Bytewlde
E"PROM
Xl
Small
Size
Large
Bubbles
Disk
NJA
N/A
N/A
All"
All
All
Bubbles
'Disk
Bubbles
'Disk
Bubbles
'Disk
Bubbles
All
AlP
All
Xl
All
Xl
Removable
(Archive)
System
Level
Bubbles
Disk
Add on RAM
Bubbles
N/A
N/A
Add in RAM
Bubbles
N/A
Xl
Bubbles
Disk
Bubbles
Disk
Bubbles
Disk
Add in/
Add on RAM
Add in/
Add on RAM
'Down Loaded From Add on/Add in Bubbles
"E"/EPROM Bytewides
'X 1 Dram Bubbles Disk
1-6
Memory Technologies
2
CHAPTER 2: INTEL MEMORY TECHNOLOGIES
Larry Brigham, Jr.
Most of this handbook is devoted to techniques and information to help you design and implement semiconductor memory in your application or system. In this section, however, the memory chip itself will be examined
and the processing technology required to turn a bare
slice of silicon into high performance memory devices
is described. The discussion has been limited to the
basics of MOS (Metal Oxide Semiconductor) technologies as they are'responsible for the overwhelming majority of memory devices manufactured at Intel.
nologies are similar, but use n·type dopants (normally
phosphorus or arsenic) to make n-channel transistors
in p-type silicon substrates. N-channel is so named
because the channel is comprised of negatively charged
carriers. CMOS or Complementary MOS technologies
combine both p-channel and n-channel devices on the
same silicon. Either p- or n-type silicon substrates can
be used, however, deep areas of the opposite doping
type (called wells) must be defined to allow fabrication
of the complementary transistor type.
There are three major MOS technology families PMOS, NMOS, and CMOS (Figure 1). They refer to the
channel type of the MOS transistors made with the
technology. PMOS technologies implement p-channel
transistors by diffusing p-type dopants (usually Boron)
into an n-type silicon substrate to form the source and
drain. P-channel is so named because the channel is
comprised of positively charged carriers. NMOS tech-
Most of the early semiconductor memory devices, like
Intel's pioneering 1103 dynamic RAM and 1702 EPROM
were made with PMOS technologies. As higher speeds
and greater densities were needed, most new devices
were implemented with NMOS. This was due to the inherently higher speed of n-channel charge carriers
(electrons) in silicon along with improved process
margins. The majority of MOS memory devices in pro-
GATE
GATE
F.O.
PMOS
NMOS
P-CHANNEL
DEVICE
N-CHANNEL
DEVICE
GATE
F.O.
.'
P-SUBSTRATE
CMOS
Figure 1. MOS Process Cross-sections
2-1
MEMORY TECHNOLOGIES
duction today are fabricated with NMOS technologies.
CMOS technology has begun to see widespread commercial use in memory devices. It allows for very low
power devices and these have been used for battery
operated or battery back-up applications. Historically,
CMOS has been slower than any NMOS device. Recently, however, CMOS technology has been improved
to produce higher speed devices. Up to now, the extra
cost processing required to make both transistor types
has kept CMOS memories limited to those areas where
tM technology's special characteristics would justify the
extra cost. In the future, the learning curve for high performance CMOS costs will make a larger and larger
number of memory devices practical in CMOS.
nitride and oxide was etched away, providing areas
doped strongly p-type that will electrically separate active areas. After implanting, the wafers are oxidized
again and this time a thick oxide is grown. The oxide
only grows in the etched areas due to silicon nitride's
properties as an oxidation barrier. When the oxide is
grown, some of the silicon substrate is consumed and
this gives a physical as well as electrical isolation for adjacent devices as can be seen in Figure 3.
NITRIDE
In the following section, the basic fabrication sequence
for an HMOS circuit will be described. HMOS is a high
performance n-channel MOS process developed by
Intel for 5 Volt single supply circuits. HMOS, along with
its evolutionary counterparts HMOS II and HMOS III,
CHMOS and CHMOS II (and their variants), comprise
the process family responsible for most of the memory
components produced by Intel today.
The MOS IC fabrication process begins with a slfce (or
wafer) of single crystal silicon. Typically, it's 100 or 125
millimeter in diameter, about a half millimeter thick, and
uniformly doped p-type. The wafer is then oxidized in a
furnace at around 1OOO°C to grow a thin layer of silicon
dioxide (Si02) on the surface. Silicon nitride is then
deposited on the oxidized wafer in a gas phase chemical reactor. The wafer is now ready to receive the first
pattern of what is to become a many layered complex
circuit. The pattern is etched into the silicon nitride using
a process known as photolithography,. which will be
described in a later section. This first pattern (Figure 2)
defines the boundaries of the active regions of the IC,
where transistors, capacitors, diffu~ed resistors, and
first level interconnects will be made.
r -_ _ _ ETCHED _ _ _-.
AREAS
\
NITRIDE~
~ \
FIELD
ox
P-SUBSTRATE
Fi~ure
,
3. Post Field Oxidation
Having fulfilled its purpose, the remaining silicon nitride
layer is removed. A light oxide etch follows taking with
it the underlying first oxide but leaving the thick (field)
oxide.
Now that the areas for active transistors have been defined and isolated, the transistor types needed can be
determined. The wafer is again patterned and then if
special characteristics (such as depletion mode operation) are required, it is implanted with dopant atoms. The
energy and dose at which the dopant atoms are implanted determines much of the transistor's characteristics. The type of the dopant provides for depletion
mode (n-type) or enhancement mode (p-type) operation.
The transistor types defined, the gate oxide of the active transistors are grown in a high temperature furnace.
Special care must be taken to prevent contamination or
inclusion of defects in the oxide and to ensure uniform .
consistent thickness. This is important to provide precise, reliable device characteristics. The gate oxide layer
is then masked and holes are etched to provide for direct
gate to diffusion ("buried") contacts where needed.
OXIDE"/
P-SUBSTRATE
Figure 2. First Mask
The patterned and etched wafer is then implanted with
additional boron atoms acceJerate\l at high energy. The
boron will only reach the 'silicon substrate where the
The wafers are now deposited with a layer of gate
material. This is typically poly crystaline silicon ("poly")
which is deposited in a gas phase chemical reactor
similar to that used for silicon nitride. The poly is then
doped (usually with phosphorus) to bring the sheet resistance down to 10-20 ohms/square. 'This layer is also
used for circuit interconnects and if a lower resistance
is required, a refractory metallpolysilicon composite or
refractory metal silicide can be used instead. The gate
layer is then patterned to define the actual transistor
gates and interconnect paths (Figure 4).
2-2 '
MEMORY TECHNOLOGIES
At this point the circuit is fully operational, however, the
top metal layer is very soft and easily damaged by
handling. The device is also susceptible to contamination or attack from moisture. To prevent this the wafers
are sealed with a passivation layer of silicon nitride or
a silicon and phosphorus oxide composite. Patterning
is done for the last time opening up windows only over
the bond pads where external connections will be made.
POLYSILICON
P-SUBSTRATE
P+
This completes basic fabrication sequence for a single
poly layer process. Double poly processes such as
those used for high density Dynamic RAMs, EPROMs,
and E2PROMs follow the same general process flow
with the addition of gate, poly deposition, doping, and
interlayer dielectric process modules required for the
additional poly layer (Figure 7). These steps are performed right after the active areas have been defined
(Figure 3) providing the capacitor or floating gate
storage nodes on those devices.
Figure 4. Post Gate Mask
The wafer is next diffused with n-type dopant (typically
arsenic or phosphorus) to fprm the source and drain
junctions. The transistor gate material acts as a barrier
to the dopant providing an undiffused channel selfaligned to the two junctions. The wafer is then oxidized
to seal the junctions from contamination with a layer of
5i02 (Figure 5).
+ VG
SECOND-LEVEL
POLYSILICON
FIELD
OXIDE
Figure 5. Post Oxidation
P-SUBSTRATE
EPROM CELL
A thick layer glass is then deposited over the wafer to
provide for insulation and sufficiently low capacitance
between the underlying layers and the metal interconnect signals. (The lower the capacitance, the higher the
inherent speed of the device.) The glass layer is then
patterned with contact holes and placed in a high
temperature furnace. This furnace step smooths the
glass sul'face and rounds the contact edges to provide
uniform metal coverage. Metal (usually aluminum or
aluminum/silicon) is then deposited on the wafer and the
interconnElct patterns and external bonding pads are
defined and etched (Figure 6). The wafers then receive
a low temperature (approximately 500°C) alloy that insures good ohmic contact between the AI and diffusion
or poly.
SECOND-LEVEL
POLYSILICON
TUNNEL
oI-t---i-I."'-'Y OXIDE
E2PROM CELL
Figure 7. Double Poly Structure
After fabrication is complete, the wafers are sent for
testing. Each circuit is tested individually under conditions designed to determine which circuits will operate
properly both at low temperature and at conditions
found in actual operation. Circuits that fail these tests
are inked to distinguish them from good circuits. From
here the wafers are sent for assembly where they are
sawed into individual circuits with a paper-thin diamond
blade. The inked circuits are then separated out and the
good circuits are sent on for packaging.
Figure 6. Completed Circuit (without passivation)
2-3
intJ
MEMORY TECHNOLOGIES
Packages fall into two categories - hermetic and nonhermetic. Hermetic packages are Cerdip, where two
ceramic halves are sealed with a glass fritt, or ceramic
with soldered metal lids. An example of hermetic
package assembly is shown in Table 1. Non-hermetic
packages are molded plastics.
frame placed on top. This sets the lead frame in glass
attached to the base. The die is then attached and
bonded to the leads. Finally the lid is placed on the
package and it is inserted in a seal furnace where the
glass on the two halves melt together Il!aking a hermetic
package.
The cer!3.mic package has two parts, the base, which
has the leads and die (or circuit) cavity, and the metal
lid. The base is placed on a heater block and a metal
alloy preform is inserted. The die is placed on top of the
preform which bonds it to the package. Once attached,
wires are bonded to the circuit and then connected to
, the leads. Finally the package is placed in a dry inert atmosphere and the lid is soldered on.
In a plastic package, the key component is the lead
frame. The die is attached to a pad on the lead frame
and bonded out to the leads with gold wires. The frame
then goes to an injection molding machine and the
package is formed around the lead frame. After mold
the excess plastic is removed and the leads trimmed.
After assembly, the individual circuits are retested at an
elevated operating temperature to assure critical operating parameters and separated according to speed and
power consumption into individual specification groups.
The cerdip package consists of a base, lead frame, and
lid. The base is placed on a heater block and the lead
Table 1. 2164A Hermetic Package Assembly
Flow
Process/Materials
Typical Item
Frequency
Criteria
Wafer
Die saw, wafer break
Die wash and plate
Die visual inspection
--0
Passivation, metal
QA gate
Die attach
(Process monitor)
0/76, LTPD = 5%
Wet out
4 x/operator/shift
0/11 LTPD=20%
Orientation, lead
dressing, etc.
4 x/operator/
machine/shift
All previous items
every lot
11129, LTPD=3%
Cap align, glass
integrity, moisture
4 x/furnace/shift
01)5, LTPD = 15%
lOx to mil std.
883 condo C
1/11, LTPD = 20%
100% of devices
Post die attach v!sual
Wire bond
(Process monitor)
Post bond inspection
--0
QA gate
100% devices
c
Seal and Mark
(Process monitor)
Temp cycle
1. __
2. __
f-o
100% of die
Every lot
Hermeticity check
(Process monitor)
F/G leak
100% devices
Lead Trim
(Process monitor)
Burrs, etc. (visual)
Fine leak
4 x/station/shift
2 x/station/shift
External visual
Solder voids, cap
alignment, etc.
100% devices
QA gate
All previous items
All lots
Class test
(Process monitor)
Run standards
(good and reject)
Calibrate every
system using
"autover" program
Every 48 hrs.
Mark and Pack
Final QA
1. Units for assembly reliability monitor.
(See attached)
2. Units for product reliability monitor.
2-4
0/15, LTPD=15%
1/129, LTPD=3%
1/129, LTPD=3%
MEMORY TECHNOLOGIES
The finished circuits are marked and then readied for
shipment.
critical for high resolution. The wafer is baked at a low
temperature to solidify the resist into gel. It is then exposed with a machine that aligns a mask with the new
pattern on it to a previously defined layer. The photoresist will replicate this pattern on the wafer.
The basic process flow described above may make'
VLSI device fabrication sound straightforward, however,
there are actually hundreds of individual operations that
must be performed correctly to complete a working circuit. It usually takes well over two months to complete
all these operations and the many tests and measurements involved throughout the manufacturing process.
Many of these details are responsible for ensuring the
performance, quality, and reliability you expect from
Intel products. The following sections will dispuss the
technology underlying each of the major process
elements mentioned in the basic process flow.
Negative working resists ar.e polymerized by the light,
anp the unexposed resist can be rinsed off with solvents. Positive working resists use photosenSitive
polymerization inhibitors that allow a chemically reactive developer to remove the exposed areas. The positive resists require much tighter control of exposure and
development but yield higher resolution patterns than
negative resistance systems.
The wafer is now ready to have its pattern etched. The
etch procedure is specialized for each layer to be
etched. Wet chemical etchants such as hydrofluoric
acid for silicon oxide or phosphoric acid for aluminum
are often used for this. The need for smaller features
and tighter control of etched dimensions is increasing
the use of plasma etching in fabrication. Here a·reactor is run with a partial vacuum into which etchant gases
are introduced and an electrical field is applied. This
yields a reactive plasma which etches the required
layer.
PHOTOLITHOGRAPHY
The photo or masking technology is the most important
part of the manufacturing flow if for .no other reason than
the number of times it is applied to each wafer. The
manufacturing process gets more complex in order to
make smaller and higher performance circuits. As this
happens the number of masking steps increases, the
features get smaller, and the tolerance required becomes
tighter. This is largely because the minimum size of
individual pattern elements determine the size of the
whole circuit, effecting its cost and limiting its potential
complexity. Early MOS IC's used minimum geometries
(lines or spaces) of 8-10 microns (1 micron=10- 6 meter
'" 1/25,000 inch). The n-channel processes of the mid
1970's brought this down to approximately 5 microns,
and today minimum geometries are less than 2 microns
in production. This dramatic reduction in feature size
was achieved using the newer high resolution photo
resists and optimizing their processing to match improved optical printing systems.
A second major factor in determining the size of the circuit is the registration or overlay error. This is how accurately one pattern can be aligned to'a previous one.
Design rules require that space be left in all directions
according to the overlay error so that unrelated patterns
do not overlap or interfere with one another. As the error
space increases the circuit size increases.dramatically.
Only a few years ago standard alignment tolerances
were 20 ± 2 microns; now advanced Intel processes
have reduced this dramatically due mostly to the use of
advanced 'projection and step and repeat exposure
equipme~t.
The wafer that is ready for patterning must go through
many individual steps before that pattern is complete.
First the wafer is baked to remove moisture from its surface and is then treated with chemicals that ensure"good
resist adh~sion. The thick photoresist liquid is then applied and the wafer is spun flat to give a uniform coating,
The wafer is now ready for the next process step. Its
single journey through the masking process required
the careful engineering of mechanics, optics, organiC
chemistry, inorganic chemistry, plasma chemistry,
physics, and electronics.
DIFFUSION
The picture of clean room garbed operators tending furnace tubes glowing cherry red is the one most often
associated with IC fabrication. These furnace operations are referred to collectively as diffusion because
they employ the principle of solid state diffusion of matter to accomplish their results. In MOS proceSSing, there
are three main types of diffusiQn operations: predeps,
drives, and oxidations.
Predeposition, or "predep," is an operation where a
dopant is introduced into the furnace from a solid, liquid,
or gaseous source and at the furnace temperature
(usually 900-1200°C) a saturated solution is formed at
the silicon surface. The temperature ofthe furnace, the
. dopant atom, and rate of introduction are all engineered
to give a specific dose of the dopant on the wafer. Once
this is completed the wafer is given a drive cycle where
the dopant left at the surface by the predep is driven into
the wafer by high temperatures. These are generally at
different temperatures than the predeps and are designed to give the required junction depth and concentration profile.
2-5
MEMORY TECHNOLOGIES
OXidation, the third category, is used at many steps of
the process as was shown in the process flow. The temperature and oxidizing ambient can range from 800 tb
1200°C and from pure oxygen to mixtures of oxygen
and other gases to steam depending on the type of oxide required. Gate oxides require high dielectric breakdown strength for thin layers (between .01 and .1 micron)
and very tight control over thickness (typically ± .005
micron or less than ± 1/5,000,000 inch), while isolation
oxides need to be quite thick and because of this their
dielectric breakdown strength per unit thickness is much
less important.
vacuum and are accomplished by vaporizing the metal
with a high energy electron beam and redepositing it on
the wafer or by sputtering it from a target to the wafer
under an electric field.
Chemical vapor deposition can be done at atmospheric
pressure or under a moderate vacuum. This type of
deposition is performed when chemical gases react at
the wafer surface and deposit a solid film of the reaction product. These reactors, unlike their general industrial 'counterparts, must be controlled on a microscale to provide exact chemical and physical properties
for thin films such as silicon dioxide, silicon nitride, and
polysilicon.
The properties of the diffused junctions and oxides are
key to the performance and reliability of the finished
device so the diffusion operations must be extremely
well controlled for accuracy, consistency and purity.
The fabrication of modern memory devices is a long,
complex process where each step must be monitored,
measured and verified. Developing a totally new
manufacturing process for each new product or even
product line takes a long time and involves significant
risk. Because of this, Intel has developed process
families, such as HMOS, on which a wide variety of
devices can be made. These families are scalable so
that circuits need not be totally redesigned to meet your
needs for higher performance. 1 They are evolutionary
(HMOS I, HMOS II, HMOS III, CHMOS) so that development time of new processes and products can be reduced without compromising Intel's commitment to consistency, quality, and reliability.
ION IMPLANT
Intel's high performance products require such high accuracy and repeatability of dopant control that even the
high degree of control provided by diffusion operations
is inadequate .. However, this limitation has been overcome by replacing critical predeps with ion implantation.
In ion implantation, ionized dopant atoms are accelerated by an electric field and implanted directly into the
wafer. The acceleration potential determines the depth
to which the dopant is implanted.
The manufacture of today's MOS memory devices requires a tremendous variety of technologies and manufacturing techniques, many more than could be mentioned
here. Each requires a team of experts to design, optimize, control and maintain it. All these people and thousands of others involved in engineering, design, testing
and production stand,behind Intel's products.
The charged ions can be counted electrically during implantation giving very tight control over dose. The ion
implanters used to perform this are a combination of
high vacuum system, ion source, mass spectrometer,
linear accelerator, ultra high resolution current integrator, and ion beam scanner. You can see that this important technique requires a host of sophisticated technologies to support it.
Because of these extensive requirements, most manufacturers have not been able to realize their needs for
custom circuits on high performance, high reliability processes. To address this Intel's expertise in this area is
now available to industry-through the silicon foundry.
Intel supplies design rules and support to design and
debug circuits. This includes access to Intel's n-well
CHMOS technology. Users of the foundry can now
benefit from advanced technology without developing
processes and IC manufacturing capability themselves.
THIN FILMS
Thin film depositions make up most of the features on
the completed circuit. They include the silicon nitride for
defining isolation, polysilicon for the gate and interconnections, the glass for interlayer dielectric, metal for interconnection and external connections, and passivation layers. Thin film depositions are done by two main
methods: physical deposition and chemical vapor deposition. Physical depOSition is most common for depositin'g metal. Physical depositions are performed in a
1 R. Pashley, K. Kokkonen, ·E. Boleky, R. Jecmen, S. Liu. and W.
Owen, "H·MOS Scales Traditional Devices to Higher Performance
Level," Electronics, August 18, 1977.
2-6
Random Access Memories
3
APPLICATION
NOTE
AP-74
March, 1980
INTEL CORPORATION. 1980
3-1
AP-74
INTRODUCTION
function of channel length <£) and doping
concentration (CB ), thus channel shortening can
be compensated by increasing the doping
The Intel® 2147H is a 4096-word by I-bit Random
Access Memory, fabricated using Intel's reliable
HMOS II technology. HMOS II, the second
generation HMOS, is Intel's high performance nchannel silicon gate technology, making simple,
high speed memory systems a reality. The purpose
of this application note is to describe the 2147H
operation and discuss design criteria for high
speed memory systems.
.-L Ir--.--------i
TO,
J
1
c.
- L~
__x.-,_
_1'0 I-PERFORMANCE FACTORS
GAIN al/(Tox1)
• HIGH DEVICE GAIN
• LOW DIFFUSION CAPACITANCE
• LOW MILLER CAPACITANCE
LOW BODY EFFECT
TECHNOLOGY
CpaXJ
I.
When Intel introduced the HMOS 2147, MOS
static RAM performance took a quantum leap by
combining scaling, internal substrate bias
generation, and automatic powerdown. As a
result, the 2147 has an access time of 55ns, density
of 4096 bits, and power consumption of .99W
active and .165W standby.
The high performance of the 2147 is further
enhanced by the 2147H using HMOS II, a scaled
HMOS process increasing the speed at the same
power level which involves more than scaling
dimensions.
Figure 1 shows the cross section of an HMOS
device and lists the~ parameters of scaling, one of
which is high device gain. The slew rate of an
amplifier or device is proportional to the gain.
Because faster switching speeds occur with high
gain, the gain is maximized for high speed. Device
gain is inversely proportional to the oxide
thickness (Tox) and device length (i,),
consequently, scaling these dimensions increases
the gain ..
Another factor which influences performance is
unwanted capacitance which appears in two
forms· - diffusion and Miller. Diffusion
capacitance is directly proportional to the
diffusion depth (Xi) into the silicon, thus-Xi must
be reduced. Miller capacitance, the same phenomenon that occurs in the macro world of discrete
devices, is proportional to the overlap length of the
gate and the source (i, D)' Capacitance on the input
shunts the high frequency portion of the input
signal' so that the device can only respond to low
frequencies. Secondly, capacitance from the drain
to the gate forms a feedback path creating arJ.
integrator or low pass filter which degrades the
high frequency performance. This effect is
minimized by reducingi D •
One of 'the limits on scaling is punch through
voltage, which occurs when the field strength is
too high, causing current to flow when the device
is "turned off'. Punch through voltage is a
em aiD
6.VT a
vee Tox
LIMITS
• PUNCH THROUGH VOLTAGE
• THRESHOLD VOLTAGE
RESULT
• DECREASE t, TaX, X" ie
• INCREASE Cs
f
~ CHANNEL LENGTH
Tax ~ OXIDE THICKNESS
X,
~ DIFFUSION DEPTH
10 ~ GATE OVERLAP
Cs ~ CONCENTRATION
Figure 1. HMOS Scaling
concentration. This has the additional advantage
of balancing the threshold voltage which was
decreased by scaling the oxide thickness for gain.
Comparison
Comparing scaling theory to HMOS II scaling in
Table I, note'that HMOS II agrees with scaling
theory except for the supply voltage. It is left
constant at +5V to maintain TTL compatibility.
Had the voltage been scaled, the power would
have been reduced by l/K3 rather than 11K, but
the device would not have been TTL compatible.
Table I. Scaling
Dimensions
Substrate Doping
Voltage
Device Current
Capacitance AIT
Time Delay VCII
Power Dissipation VI
Power Delay Product
Theory
11K
K
11K
11K
11K
11K
11K'
11K'
HMOS II
11K
K
1
1
11K
11K
1
11K
THE DEVICE
The 2147I:J is TIL compatible, operates from a
single +5 volt SUp~y, and is easy to use.
Figure 2 shows the pin configuration and the logic
symbol. The 2147H is compatible with the 2147
allowing easy system upgrade. Contained in an
industry standard 18-pin dual in-line package the
2147H is organized as 4096 words of 1 bit. To
access each of these words, twelve address lines
are required. In addition, there are two control
signals: CS, which activates the RAM; and WE,
I
3-2
I
AP-74
®
which controls the write function. Separate data
input and output are available. Logical operation
of the 2147H is shown in the truth table. The
output is in the high impedance or three-state
mode unless the RAM is being read. Power
consumption switches from standby to active
under control of CS.
~Vcc
~GND
®
MEMORY ARFIAY
64 ROWS
64 COLUMNS
o
4096 x 1 BIT
2147H
PIN CONFIGURATION
..,,,
.
..
Dour
PIN NAMES
lOGIC SYMBOL
.All ADDRESS INPUTS
WRITE ENABLE
ill!:
B
V c POWER I'" SVj
GND GROUND
CHIP SELECT
DIf1, are the key to low standby power.
Forming an AND function with the active devices,
the upper transistors are turned off when the
·2147H is not active, minimizing power·
consumption. Without them, at least one stage of
these cascaded amplifiers would always be
consuming, power.
+,---+--11-4---1-----'
ADDRESS
Figure 4. Address Buffer.
For both the 2147 and the 2147H, access is delayed
until the address buffers are activated by chip
selection. In the standard 2147, priming during
deselection compensates for this delay by
speeding up the access elsewhere in the circuitry.
For short deselect times, however, full compensation does not oceur because priming is incomplete.
The result is a pushout in tAcs for short deselect
times.
The signal <1>1, and its inverse ii, are generated
from CS. They are part of an innovative design not
found in the earlier 2147. Their function is to minimize the effects at short deselect times on the Chip
Select access time, tACS.
3-3
AP-,4
In the 2147H, the address buffers are controlled by
<1>1, which is shaped as shown in Figure 5. <1>1 activates rapidly for fast select time. Howilver, <1>1
deactivates slowly, keeping the address buffers
active during short deselect times to speed access.
As shown in Figure 6, this design innovation keeps
t",cs pushout to less than 1, ns.
I
d
~ I
Figure 7 shows the standard six-transistor cell.
Configured as a bi-stableflip-flop, the memory cell
uses two transistors for loads and two for active
devices so that the data is stored twice as true and
compliment. The two remaining transistors
enable data onto the internal I/O bus. Unlike the
periphery, the cell is not po~ered down during
deselect time to sustain data indefinitely.
CHIP
I DESELECTED
I r------"\
The 2147H has an internal bias generator. Bias
voltage allows the use of high resistivity substrate
by adjusting the threshold voltages. In addition, it
reduces the effect of bulk silicon capacitance. As a
result, performance is enhanced. Bias voltage is
generated by capacitively coupling the output of a
ring oscillator to a charge pump connected to the
substrate. Internally generated bias permits the
2147H to operate from a single +5 volt supply,
maintaining TTL compatibility.
'
CHIP
SELECTED
I
I
I
I
I
I
SLOW
DESELECT
I
I
I
2147H SUBSTRATE BIAS GENERATOR
I
I
CMAAGE
I
I
J
I
POMP
I
I
~f-I--rf--'~"-'--',,,\,,,,
FAST
SELECT
it. . . ___
Figure 5. CS Buffer Sigual.
Vc(.=5S11
Figure s. 2147H Substrate Bias Generator
DEVICE OPERATION
READ MODE
With power applied and CS at greater than 2V, the
2147H is in the standby mode, drawing less than
30mA. Activating CS begins access of the cell as
defined by the state of the addresses. Data is
transferred from the cell to the output buffer.
Because the cell is static, the read operation is nondestructive. Device access and current are shown
in Figure 9. Maximum access relative to 'the
leading edge of CS is 35 ns for a 2147H-1. Without
clocks, data is valid as long as address and control
are maintained.
Figure 6. CS Acce •• V •. Deselect Time
WRITE MODE
Data is modified when the write enable WE is
activated during a cycle. At tnis time, data present
at the input is duplicated in the cell specified by
the address. Data is latched into the cell on the
trailing edge of WE, requiring that setup and hold
times relative to this edge be maintained.
Figure 7. 2147H Memory Cell
3-4
AP-74
Two modes of operation are allowed in a write
cycle, as shown in Figure 10. In the first mode, the
write cycle is controlled by WE, while in the other
cycle, the cycle is controlled by CS. In a, WE
controlled cycle, CS is held active while addresses
change and the WE signal is pulsed to establish
memory cycles. In the CS controlled cycle, WE is
maintained active while addresses again change
and CS changes state to define cycle length. This
flexible operation eases the use and makes the
2147H applicable to a wide variety of system
designs.
5...
5...
20nS
ADDRESS
INPUT
CHIP SELECT
DATA
OUTPUT
SUPPL Y ,CURRENT
1100 mAlcm)
Figure 9. 2147H Access and Power Photo
WAVEFORMS
, WRITE CYCLE #1 (WE CONTROLLED)
---'we
ADDRESS
~-------:---.ew
CSll
I~
II
--
tAW---
1--- - - - tAs-~_-j
IIII
-'w,-
'w'
\\
*
DATA IN
tOH_
'DW
J
DATA IN VALID
________________=-1
CE~,
:)o-....:=~=;:;::-,--«......----'ow
f----tWl
HIGH IM.EDAN,
DATA OUT
-----
DATA UNDEFINED
WRITE CYCLE #2 {CS CONTROLLED)
'we
---..
ADDRESS
--
-
'cw
'AS
~
'AW
-'w,-
-'wP
IIIIIIII
\ \ \ \ \ \'\ \ \-\
i
DATA IN
'ow
·DH·
DATA IN VALID
__. ,. _____________=1
-
-'wz
DATA OUT
DATA UNDEFINED
HIGH IMPEDANCE
----~----.....- - -
:)
....
Note' 1 If CS goes high simuitaneousiy with WE high. the output remains In a high Impedance state
Figure 10. Write Cycle Modes of Operation
3-5
AP-74
EFFECT OF POWER DOWN AT
THE SYSTEM LEVEL
active or being accessed. For a system with power
down, the average current of a device in the
system is the sum of total active current and the
total standby current divided by the number of
devices in the system. For an Xl memory such as
the 2147H, the number of active devices in most
systems will be equal to the number of bits/word,
m. Therefore, the number of devices in standby is
the difference between Nand M. lAVE is expressed
mathematically:
Power consumed by a -memory system is the
product of the number of devices, the voltage
applied, and the aver~$e current:
Equation 1
P = NVIAvE
P = Power
N = Number of devices
V = Voltage applied
lAvE = Average current/device
where:
Equation 2
Without power down, the average current is
approximately the operating current. System
power increases linearily with the number of
devices. With power down, power consumption
increases in proportion to the standby current
with increasing number of memory devices.
Curves in Figure 11 illustrate the difference which
results from the majority of devices being in
standby with a very small portion ofthe devices
lAVE= mIAcT+ (N-m) ISB
N
m = Number of active devices
IAcT = Active current
ISB = Standby current
where:
The graph of Figure 12 shows the relation between
average device current and memory size for
automatic power down. For large memories the
average device current approaches the standby
current. Total system power usage, P, is calculated
by substituting Equation 2 into Equation 1.
P = V[mIAcT + (N-m) ISB]
Comparison of power consumption of a system
with and without power down illustrates the
power savings. Assume a 64K by 18-bit memory
constructed with 4KX1 devices. Active current of
one device is 180mA and standby current is 30rnA.
Duty cycle is assumed to be 100% and voltage is 5
volts. The number of devices in the system is:
EFFECT OF POWER DOWN
AT THE SYSTEM LEVEL
N = 64K words x 18 bits/word
4K bit/device
WITH POWER DOWN
N =288 devices
WITHOUT POWER DOWN:
MEMORY sIze
Figure 11. Effect of Power Down at the System
'"
P NPD
=
288 devices x 5 volts x 180 mAl device
P NPD = 259.2 watts
WITH POWER DOWN:
With power down only 18 devices are active - 18
bits/word - and 270 are in standby.
PwPD = 5 volts [18 devices (180rnAldevice) +
270 devices (30 rnA/device)]
PWPD = 56.7 watts
The system with power down devices uses only
22% of the power required by a non-powerdown
memory system.
Isa ----------------------
..
,
r.tEMORYSIZE
Figure 12. Average Current as a Function of ~emory Size
3-6
AP-74
POWER-ON
ARRAY CHARACTERISTICS
When power is applied, two events occur that must
be considered: substrate bias start up and TTL
instability. Without the bias generator functioning (Vee less than 1.0 volts), the depletion mode
transistors within the device draw larger than
normal current flow. When the bias generator
begins operation (Vee greater than 1.0 volts), the
threshold of these transistors is shifted, decreasing the current flow. The effect on the device
power-on current is shown in Figure 13.
For Vee values greater than 1.0 v., total device
current is a function ,of both the substrate bias
start-up characteristic and TTL stability. During
power-on, the TTL circuits are attempting to
operate under conditions which violate their
specifications; consequently the CS sign,als can be
indeterminent. One or several may be low,
activating one or more banks of memory. The
combined effects of this and the substrate bias
start-up characteristic can exceed the power
supply rating. The V-I characteristic of a power
supply with fold back reduces the supply voltage
in this situation, inhibiting circuit operation. In
addition, the TTL drivers may not J!.e able to
supply the current to keep the CS signals
deactivated.
One of several design techniques available to
eliminate the power-on problem is power supply
sequencing. Memory supply voltage and TTL
supply voltage are separated, allowing the TTL
supply to be activated first. When all the CS
signals have stabilized at 2.0V or greater, the
memory supply is activated. In this mode the
memory ~ower-on current follows the curve
marked CS =Vee in Figure 13.
If power sequencing is not practical, an equally
effective method is to connect the CS signal to Vee
through a 1Kn resistor. Although this does not
guarantee a 2.0V CS input; emperical studies
indicate that the effect is the same.
When two or more RAMs are combined, an array
is formed. Arrays and their characteristics are
controlled by the printed circuit card which is the
next most important component after the memory
device itself. In addition to physically locating the
RAMs, the p.c. board must route power and
signals to and from the RAMs.
GRIDDING
A power distribution network must provide
required voltage, which from the 214 7H data sheet
is 5.0 volts ±10% to all the RAMs. A printed circuit
trace, being an extremely low DC resistance,
should easily route +5v DC to all devices. But as
the RAMs are operating, micro circuits within the
RAMs are switching micro currents on and off,
creating- high frequency current transients on the
distribution network. Because the transients are
high frequency, the'network no longer appears as
a "pure" low resistance element but as a transmission line. The RAMs and the lumped equivalent circuits of the transmission line are drawn in
Figure 14. Each RAM is separated by a small
section of transmission line both on the +voltage
and the -voltage. Associated with the transmission lines is a voltage attenuation factor. In
terms of AC circuits, the voltage across the
inductor is the change in current - switching
transient - multiplied by the inductance.
:~
. ::I9:--"
O~----···~-1
I
Figure 14. Equivalent Circuit for Distrihution
Assuming all RAMs act similarly, the first
inductor will see N current transients and the
inductor at RAM B sees N-1 transients. The total
differential is:
".
N
AV=
g
I
n
40
n L din
dt
=1
That voltage tolerance of ±1O% could easily be
exceeded with excursions of ±1 volt not uncommon.
Measures must be taken to prevent this. The
characteristic impedance of a transmission line is
shown in Figure 15A.
VccCYOLTSJ
Figure 13.' 2147H Power Up Characteristic
3-7
AP-74
:ll: ill!
Connecting two transmission lines in parallel will
halve the characteristic impedance. The. result is
shown in Figure 15B.
LO
A
-'OL-r-'-
I
Zo
Lo
INDUCTANCE/UNIT LENGTH
Co
CAPACITANCE/UNIT LENGTH
I
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:
J ~: ~-LO
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Lo
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~--------
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2
Lo
Co
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:
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lut
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:
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Figure 16. Gridding Plan
Figure 15. Transmission Line Characteristic Imped~ce
Paralleling N traces will reduce the impedance to
Zo/N. Extrapolation of this concept to its limit
will result in an infinite number of parallel traces
such that they are physically touching, forming
an extremely wide, low impedance trace, called a
plane. Distribution of power (+ voltage) and
ground (- voltage) via separate planes provides the
best distribution.
P.C. boards with planes are manufactured as
multi-layer boards sandwiching the power and
ground planes internally. Characteristics of a
multilayer board can be cost effectively
approximated by gridding the power and ground
distribution. Gridding surrounds each device with
a ring of power and ground distribution forming
many parallel paths with a corresponding
reduction of impedance. Gridding is easily
accomplished by placing horizontal traces of
power (and ground) on one side of the pc board and
vertical traces on the other, connected by plated
through holes to form a grid.
Viewed from the top of the p.c. board, the gridding
as in Figure 16 surrounds each device. Pseudogridding techniques such as serpentine or
interdigitated distribution, as in Figure 17, are not
effective because there are no parallel paths to
minimize the impedance.
INTERDIGITATED
Figure 17. Pseudo-Gridding Techniques
for the 2147H is accomplished by placing a 0.1 !-If
ceramic capacitor at every other device as shown
in Figure 18. Bulk decoupling is included on the
board to filter low frequency noise in the system
power distribution. One tantalum capacitor of 22
to 47 Jlf per 16 devices provides sufficient energy
storage. By distributing these capacitors, around
the board several small currents exist rather than
o~e large current flowing everywhere. Smaller
voltage differentials - voltage is proportional to
current - are experienced and the voltage remains
in the specified operating range. Figure 19
demonstrates the difference with and without
gridding.
DECOUPLING
One final aspect of power/ground' distribution
must be considered - decoupling.
TERMINATION
Decoupling provides localized charge to minimize
instantaneous voltage changes on the power .grid
.due to current changes. These transient current
changes are local and high frequency as devices
are selected and deselected. Adequate decoupling
Similar reasoning is applied to the a.c. signals:
address, control, and data. While they are not
gridded or decoupled, they must be kept short and
terminated. Similar to the power trace, the signal
3-8
AP-74
~
~
DDD
D D0
DD0
000
0
0
•
ce
~
~
•
~
III
a:
• • •
~
~
c
III
III
~
w
0
0
•
a:
c
•
C
LC
~~-----o
UNDERSHOOT
. Di
D
Array
SERIES TERMINATION
~
4L 2
<
D
[>0>------
I
LC
OVERSHOOT
A".,
....
PARALLEL TERMINATION
=
Fignre 23. Series and Parallel Termination
III
R'
I
4L2
LC
CRITICALLY DAMPED
Fil'll"e 21. Three Cases of Equation Solution
Series termination uses one resistor and consumes
little power. Current through the resistor creates a
voltage differential shifting the levels of input
v.oltage to the devices slightly. This shift is usually
insignificant because the 2147H has an eJitremely
high input impedance.
Termination could also be accomplished by a
parallel termination as shown in Figure 23.
3-10
AP-74
Parallel termination has the advantage of faster
rise and fall times but the disadvantage of higher
power consumption ·and increased board space
usage.
A
SYSTEM DELAYS
RAMs are connected to the system through an
interface, comprised of address, data and control
signals. Inherent in the interface is propagation
delay. Added to the RAM access time, propagation
delay lengthens system access time and hence system cycle time. Expressed as an equation:
where:
tsa
Figure 24A.
tsa =tela + f;pd
=system access time
t... = device access time
tpd = propagation delay
Device access is a fixed value, guaranteed by the
data sheet. System efficiency then, is a function of
system access and can be expressed as:
Eff= tda/taa
where: Eff =System Efficiency
This can be reduced by substitution for tsa to:
Eff =1~(1 + tpd/tda)
System efficiency is maximized when
propagation delay is minimized. With sub 100 ns
access RAMs, efficiency can be reduced to 40-60%
because delay through the signal paths is
significant when compared to RAM access. Three
factors contribute to the delay: logic delay,
capacitive loading, and transit time.
o
1
2
3
4
5
I I
6
8
I
I I
9
10
tn.)
TTL GATES
800 504, 610. 520
SOl, 511
1--n,"",,",,,,,1
I-"-t'~~m~
Figure 24B. Skew
10
LOGIC DELAY
The delay through a logic element is the time
required for the output to switch with respect to the
input. Actual delay times vary. Maximum TTL
delays are specified in catalogs, while minimum
delays are calculated as one-half of the typical
specification. As an example, a gate with a typical
delay of 6 ns has a minimum delay of 3 ns.
A signal propagating through two logically identical paths but constructed from different integrated circuits will have two different propagation
times. For example, in Figure 24A one path has
minimum delays while the other has maximum
delays. Path A-B has a delay of 3.5 ns while A-Bi
has a delay of 11 ns. The time difference between
these two signals is skew, which will be important
later in the system design. Figure 24B shows skew
values for several TTL devices.
OL-____
W
~
~
______- L_ _ _ _
~
~
____
100
~
1~
CAPACITIVE LOAOING (pF)
TIME DELAY OF A TYPICAL SCHOTTKY TTL GATE
CAPACITIVE LOADING
Figure 25. Capacitive Loading
Delay time is also affected by the capacitive load
on the device. Typical delay as a function of capacitive load is shown in Figure 25. TTL data sheets
specify the delay for a particular capacitive load
(typically 15pF or 50 pF). Loads greater than specified will slow the device; similarly, loads less
than specified will speed up the device.
3-11
AP-74
"see" all the load capacitance simultaneously, it is
distributed along the trace at the devices.
A value of 0.05 ns/ft is a linear approximation of
the function in Figure 25 and is used in the calculations. Loading effect is calculated by subtracting
the actual load from the specified load. This difference is multiplied by 0.05 ns/pF and the result
algebraically subtracted from the specified delay.
As an example, a device has a 4 ns delay driving 50
pF, but the actual load is 25 pF. Then,
Substituting into the equation:
tpl = VL(C + CO
where: tpl = Modified delay
CL =Load capacitance
50 pF specified
-25 pF actual
25 pF difference
25 pF x 0.05 ns/pF = 1.25 ns
4 ns
specified
-1.25ns difference
2.75 ns actual delay
A device specified at 4 ns while driving 50 pF will
have a delay of only 2.75 ns when driving 25 pF.
Conversely, the same device driving 75 pF would
have a propagation time of 5.25 ns.
Algebraically:
tpl = LC(I + CL /C)
tpl = VIii VI + CLiC
and
tpl = tp VI + CLiC
Emperically, tp is 1.8 ns/ft for G-lO epoxy and C is
1.5 pF lin. For a 5-in. trace and a 40 pF load, the
delay is calculated to be 4.5 ns. Because this is
worst case, an approximated 2 ns/ft can be used.
In the following sections, however, the equation
will be used. Total delay is the summation of all
the delays. Adding the device access, TTL delays
and the trace delays result in the system access.
V
---
TRANSIT TIME
BOARD LAYOUT
Signal transit time, the time required for the signal to travel down theP.C. trace, must also be considered. As was shown in Figure 19, these traces
are transmission lines. Classical transmission
line theory can be used to calculate the delay:
tp =
The preceding section discussed the effects of
trace length and capacitive loading. Proper board
layout minimizes these effects.
As shown in Figure 26, address and control lines
are split into a right- and left-hand configuration
with these signals driving horizontally. This
configuration. minimizes propagation delay.
Splitting the data lines is not necessary, as the
data loads are not as great nor are their traces as
long as address and control lines. Cpntrol and
timing fills the remaining space.
Two benefits are derived from this layout. First,
.JfE
t p = Travel Time
L = Inductance/unit length of trace
C = Capacitance/unit length of trace
The capacitance term in the equation is modified
to include the sum of the trace capacitance and the
device capacitance. This equation approximates
in the worst case direction; a signal will never
where:
RI~
LEFT
MEMORY
ARRAY
.-
MEMORY
ARRAY
LEFT
ADDRESS
ANO CS
DRIVERS
I
't
I
I
I
IJ
-
I
.
CONTROL
II
DATA
BUFFER
l
I
TIMING
I
I
CARD EDGE CONNECTOR
Figure 26. Board Layout
3-12
AP-74
~1~.~______________~80~n~S________________-+•.I'.'-_______
~
X,-_-+I__
I
START CYCLE
(REO)
I
-L-
'r---
---,
L--..J
M"~~
DATA OUT
Figure 27. System Timing
TIMING
GEN
r
12
ADDRESS
LATCH
16
ADDRESS
BUS
~
1.66/ .....
~
DATA
BUS
CRITICAL PATH
Figure 28. System Block Diagram
the address and control lines are perpendicular to
the data lines which minimizes crosstalk. Second,
troubleshooting is simplified.· A failing row of
devices indicates a defective address or control
driver; whereas a failing column indicates a faulty
data driver.
control signals are coincident with the start of the
cycle. Access is not yet specified because it is
affected by device access and the unknown
propagation delay. Access will be determined in
the design.
Figure 28 illustrates the elements of the system in
block diagram form. Addresses are buffered and
latched at the input to the printed circuit card.
Once through the latch, the addresses split to
perform three functions: board selection, chip
select (CS) generation, and RAM addressing.
Highest order addresses decode the board select,
which enables all of the board logic including CS.
Next higher order addresses decode CS, while the
lowest order addresses select the individual RAM
cell. Data enters the board from the bidirectional
bus through a buffer/latch, while output data
returns to the bidirectional bus via buffers. Only
two cont~ol signals - cycle request (MEMREQ)
and write (WR) control the activity on the board.
SYSTEM DESIGN
Using previously discussed rules and guidelines,
the design of a typical high speed memory will be
reviewed to illustrate these techniques.
Configuration ofthe system is a series of identical
memory cards containing 16K words of 16 bits.
Timing and control logic is contained on each
board. System timing requires an 80 ns cycle as
shown in Figure 27. Cycle operation begins when
data and control signals arrive at the board. In
this design, addresses are shifted 30 ns to be valid
before the start of the cycle so that address, data,
and control arrive at the memory device at the
same time for maximum performance. Data and
Figure 29 illustrates the levelsofthe delay in the
3-13
AP-74
CRITICAL PATH
,I
1
ADDRESS
BOARD
SELECTION
+
J
CHIP
SELECT
I
i
-!
CONTROL
DATA
1
MEMORY
I
+
1
1
Figure 29. Worst Ca,e Delay Path
system. Data and control have only one level. But
examine the address path, it has three levels.
Addresses are decoded to activate the logic on the
board, select the row of RAM to be accessed and
finally locate the specific memory cell. C8 is in this
address path and is crucial for access; without it
RAM access cannot begin. But this path has the
most levels of decoding with associated
propagation delays. Consequently, the address
path to C8 is the critical patll- and has the greatest
effect on system delay and hence must be
minimized.
Examination of the system begins with the C8
portion of the critical path, followed by addresses,
data path, and finally timing and control.
allows addresses to pass independent of any clock.
Delay time is measured from the signal rather
than a clock. The Intel® 3404 is a high speed, 6-bit
latch operating in a flow-through mode with 12 ns
delay. This is acceptable but a faster latch can be
fashioned using a 2-to-1line multiplexer, either a
748157 or a 748158. The slower of the two is the
748157 with 7.5 ns delay. Although the 748158 is
faster with 6 ns delay, it requires an extra inverter
in the feedback path as shown in Figure 30. Between the 748157 and the 748158 latches, the trade
off is speed against board space and power. Individual designers will choose to optimize their
designs.
'
74S04
CRITICAL ,PATH ,
Analysis of the critical path begins with the
address latch. The first decision to be made is to
the latch type. Latches can be divided into two
types: clocked and flow-through. Clocked latches
capture the data on the leading or trailing edge of
the clock. Associated with the clock is data set-up
or hold-time that must be included in the delay
time. Accuracy of the clock affects the transit time
of the signal because any skew in the clock adds to
the delay time. As an example, a typical 748173
latch has a data set-up time of 5 ns and a
maximum propagation delay time from the clock
of 17 ns. Total delay time is 22 ns, excluding any
clock skew.
Flow-through latches have an enable rather than
clock. The enable opens the address window and
INPUT
OUTPUT
------t--r-'"
'14 OF 745158
tpo INPUT·OUTPUT
tPD LATCH·OUTPUT
Figure 30. Fast Latch
3-14
MIN
2 ns
4 ns
MAX
6 ns
12 ns
AP-74
In either case, care must be exercised in
constructing the latch. Output data must be fed
back to the input having the shortest internal path
- the A input. If the latch is constructed with the
output strapped to the B input, the input could be
deselected and the feedback loop not yet selected
because of the delay through the internal inverter.
In this situation data would be lost. Additional
delay through the external inverter (74S04) aids in
preventing data loss. Inverting add1:esses has no
system effect - except that it's faster than the
non-inverting latch. During a write cycle, data
will be stored at the compliment of the system
address. When this data is to be retrieved, the
same address will be complimented, fetching the
correct word.
a true input, defining the output from the Board
Select decoder.
In the Board Select decoder, the high order adresses are matched to hard-wired logic levels
generated with switches for flexibility. Changing
a switch setting shifts the 16K range of the board.
Comparison of the switch setting and the address
can be accomplished with an exclusive-OR, a
. 74S86. N ANDing all the exclusive-OR outputs will
generate a Board Select signal. Unfortunately,
this signal is active-low, requiring an additional
inverter as in Figure 32A, and it also consumes
22.5 ns to decode. An MSI solution to board
selection is a 4-bit comparator - 74S85 - which
MAX PROP DELAY::; 11.5
The remaining elements in the critical path to be
designed are board selection and CS decoding. To
minimize the CS, decode path, the easiest method
is to work backwards from CS. In this manner input signals to a stage are determined and the
output from the preceding stage is defined. This
saves inserting an inverter at the cost of 5 ns to
generate the proper input to a stage.
+Vcc
os
r--- 6(
Y
r-Y"
1 ....
....
~
Starting with the CS driver, the design analyzes
several approaches to select the fastest one. With
four rows of devices, there are four CS signals to be
generated. A 2-to-4line decoder like the 74S 138 is a
possible solution. It is compact, but has two
detriments: long propagation delay and
insufficient drive capability. propagation delay
from enable is 11 ns. Enable is driven by board
selection which arrives later than the binary
inputs. Splitting the RAMs into two 4x8 arrays
eases the drive requirement but the demultiplexer
must still drive eight devices at 5 pF each - or 40
pF total- which adds 1.75 ns to the delay. More
importantly, signal drive is required to switch
cleanly and maintain levels in spite of crosstalk
and reflections. A 74S240 buffer will solve this but
in the process consumes an additional 9 ns.
1
- F\.
I
........
':;;4
1
~
--
BRD
SEL
S40
Figure 31.
CS Decode
~
~
~
AN_'
A second and preferred approach is to use a discrete decoder to decode and drive the CS signals.
Four input NAND buffers - 74S40 - fulfill this
function. Addresses A12 and A13 are inverted via
74S04, providing true and compliment signals to
the buffer for decoding. As shown in Figure 31, the
delay is 11.5 ns. Propagation delay for the 74S40 is
specified into a 50 pF load, eliminating the
additional loading delay. Left and right driversCSXL and CSXR - are in the same package to
minimize skew between left and right bytes of
data. All of the decoders are enabled by Board
Select to prevent rows of devices on several boards
fro~ being simultaneously active. Board Select is
~
3-15
-
'S86
l- =~~~:~~ ~:t:~ ,~::!2.~6!';:~:'~~: I
SKEW = 15.25
Figure 32A.
'5260
'504
+ 2 = 3.5.0
I
+ 6 =,11 ns
SKEW 7.5 ns
Figure 32B. Board Select
=
MIN PROP DELAY
1.5
MAX PROP DELAY = 5
I
.01
AP-74
, consumes less board area and propagation delay
is improved at 16.5 ns.
The best solution is attained by inverting the high
order addresses to generate true and compliment
'signals. the appropriate signal is connected into a
74S260, 5·input NOR. With an active-high output,
maximum delay is 11 ns as in Figure 32B.
Critical path timing is the sum of the latch, Board
Select, and CS delay times. In this example, latch
delay is 6 ns, Board Select is 11 ns and CS decode is
11.5 nS for a total of 28.5 ns. One additional delay
- trace delay - must be included for a complete
,solution. Each 74S40 drives eight MOS inputs
having 5 pF/device for a load of 40 pF. Trace
capacitance is calculated on 5 in. of trace. At 1.5
pF/in., trace capacitance is 7.5 pF. Trace delay
calculated from equation 3 is 1.9 ns.
tpl = 1.8 ns x 5 in.
40 pF
ft
12 in.lft
1 + 7.5 pF
tpl = 1.9 ns
Total worst case maximum critical path delay has
been calculated to be 30A ns (28.5 ns + 1.9 ns). With
the addresses shifted in time by an amount equal
to the worst case delay, device and system cycle
start are coincident. Start of system access and
device access differ only 0.4 ns when the addresses
are shifted 30 ns. From the system cycle start,
access is stretched by 0.4 ns as shown in Figure 33.
Thus, with a 35 ns 2147H-1, data is valid at the
output of the device 35.4 ns after the start of the
cycle.
J
From address change, the maximum delay in the
critical path is 30.4 ns while the minimum is 10.9
ns. The difference between these two times is skew
and will be important in later calculations.
ADDRESSES
Lower order addresses (Ao-All) arrive at the devices earlier than CS because they are not
decoded. Consequently, the address drivers do not
have a critical speed requirement. Once through
the 6 ns latch, addresses have 24 nsto arrive at the
devices.
While speed is not the primary prerequisite, drive
capability is. Address drivers are located in the
center ofthe board, dividing the array into two sections of 32 devices each. F9r the moment, assume
one driver drives 32 devices as in Figure 34A. Each
device is rated at 5 pF linput, resulting in a load of
160 pF. In addition, there are four 5-in. traces one for each row. twenty inches oftrace equates to
30 pF. total capacitive load is 190 pF. A 74S04 is
specified at 5 ns delay into 15 pF. The increased
capacitive load is 175 pF, which at 0.05 ns/pF increases the delay by 8.75 ns. Under these conditions the worst cast driver relay is 5 ns pI us 8.75 ns,
totalling 13.75 ns. It is 10 ns earlier than the 24 ns
available.
LO
AODRESS
\ \
-
S
----M
-EMREQ
10.9n5
\
30 4ns-------..
30n5
Figure 33.
·1
CS Decode Time
The minimum delay also must be calculated. With
addresses valid prior to the start of the cycle, CS
decoding can start in the previous cycle. If it
occurs too soon, the previous cycle will not be
properly completed. Minimum delay time is the
sum of the minimum propagation delays plus
capacitive loading delay plus trace delay.
Capacitive loading delay is less than 0.4 ns and
ignored. Minimum delay through the TTL is 9 ns,
and added to trace delay results in a total of 10.9
ns.
Figure 34A. Address Driver
The first impression is that this is sufficient, but
the effect of crosstalk must be considered. For
example, as shown in Figure 35, each trace has
inductance, and parallel traces take on the
3-16
AP-74
can sink 20 rnA, inducing a transient in an
adjacent trace. If the adjacent signal is switching
to a one level, only 400 IlA of a source current from
the driver is available. The induced current will
generate a negative spike, driving the signal at a
one leval negative. Additional time ofl 0 to 15 ns is
required to recover and re-establish a stable one
level. This may prevent stable address at the start
of the cycle. Recall:
.
dv
dv
l=CTt ordt=C T
characteristics of transformers. When a signal
switches from a one level to a zero level, its driver
LO
where: i = instantaneous current
C = capacitance
dv = voltage time rate of change
dt
LO
The term dv/ dt can be maximized by increasing i
or decreasing C. Current can be doubled by using a
driver like a 748240, but it draws 150mA supply
current. In a large system the increased power is a
disadvantage because it requires a larger power
supply and additional cooling.
A better alternative is to reduce the capacitance,
which results in a corresponding increase in dv / dt
for quick recovery. 8plitting the loads to 16 devices
reduces the capacitance and allows a low power
driver, like a 74804, to be used, as in Figure 34B.
This has the double effect of decreased propagation delay and providing sharp rise and fall times.
Now, there are only 10 in. oftrace or 15 pF load and
16 devices, representing 80 pF for a total of 95 pF.
Again, the 804 delaY' is 5 nil'into 15 pF, but the
stretched delay due to 80 pF is only 4.0 ns for a
total of 9.0 ns. Stable addresses are guaranteed at
the start of the cycle.
Figure 34B. Address Drivers
LO
Figure 35. Cross Talk
DATA PATH
x
ADDRESS
SLOW ell FAST
Next in line for analysis is the data path.
Reference to the system block diagram shows that
the data is latched into the board on a write cycle
and buffered out during a read cycle. Data latches
are constructed from 748158 quad two-input
multiplexers. Because the data bus is
bidirectional, 748240 three-state drivers are used
for output buffers.
All that remains to complete the board access computation is the calculation of the output propagation delay. Output delay of the active RAM is
caused by the capacitance loading of its own output plus the three idle RAMs, the input
capacitance of the 748240 bus driver and trace
capacitance. Output capacitance ofthe 2147Hs is
6 pF/device for a subtotal of 24 pF; input
capacitance of the 748240 is 3 'pF and trace
capacitance of a 5-in. trace is 7.5 pF. total load
r--
CS
"
FAST ADDR
X
---
,-Figure36A.
SLOW~$
~
X ===
_+-_______
FAST CS _
AODR
~
--1. .
~------J/~--r_-
Figure 36B. Rl!:ce Condition Between Address and WE
3-17
AP-74
Figure 36B shows the proper operation controlled
with timing.
Finally, the data output buffers, controlled by
timing signals, are enabled only during a read
cycle while the board is selected preventing bus
contention with two or more boards in the system.
More importantly, timing' disables the output
pri()r to the start of the next cycle, allowing input
data to be stabilized on the bidirectional data bus
in preparation for a write cycle.
capacitance is 34.5 pF, and access time of the
2147H is specified driving a 30 pF load. Calculated
loading is close enough to the specified loading to
eliminate any significant effect on the access
calculations. Had there been a difference, the
effect would have been included in the calculation.
As previously calculated, transit time of the trace
is 1.6 ns. Adding this to the 7 ns delay through the
748240 bus driver results in an 8.6 ns output
propagation delay from the RAM output to. the
bus.
Total access is 35.4 ns plus 8.6 ns output delay for a
total access of 44 ns. The efficiency of this system
is:
TIMING GENERATION
Having discussed the philosophy of timing and
control, we can now focus on the specifics of
address latching, write pulse generation and
output-enable timing. To perform these functions
timing can be generated from one of three sources:
clock and shift register, monostable
multivibrator, or delay line.
35
Eff = 44 or 80%
TIMING AND CONTROL
Timing and control gating regulates activity on
the board to guarantee operation in an orderly
fashion. This gating latches addresses, controls
the write pulse width and enables the three-state
bus drivers. In addition, accurately generated
timing compensates for skew effects.
In anticipation ofthe next cycle, the latch must be
opened f()r the new address. When the current
cycle has completed 50 ns, the latches are again
opened. The next cycle might not begin 30 ns after
the latch is opened beca.use the system may skip
one or more memory cycles. Therefore, a signal
from the next active cycle must close the latch. In
operation, a buffered Memory Request signal
latches the addresses.
The write pulse is controlled to guarantee set-up
and hold times for data and address and to
prevent an overlap of C8 and write enable from
different cycles. To understand the consequences,
consider the following example.
Assume two memory banks, one has a minimum
CS and the other has a maximum delay path in
CS, and both have a minimum address delay.
Assume that WE is a level generated from a write
command as shown in Figure 36A. The'operation
under examination is a write cycle into the bank
with fast C8 followed by a read cycle into the bank
with slow CS.
Both the write cycle and the read cycle have device
specification violations. In the write cyCle, the addresses change prior to CS and WE becoming
inactive; that new address location may be written
into. In the read cycle, the address change is
correct but WE is. still active and the fast CS
begins too soon, performing a non-existent write
cycle. Clearly, controlling the width of WE will
solve the problems.
CLOCKED SHIFT REGISTER
A clocked shift register circuit is shown in Figure
37 consisting of a D-type flip flop and an 8-bit shift
register.
~---'MEM~L-_________
I
CLK~
Q
U
-I
1--
LATENCY
Figure 37. D Flip-Flop and Shift Register
On the leading edge ofMEMREQ, the Q output of
the D flip flop is clocked to a one state, enabling a
"one" to be propagated through the shift register.
The one is clocked into the first stage of the shift
register on the first clock edge after the A and B
inputs are "ones". After the clock, the output QA
goes true which subsequently clears the D flip flop,
clocking zeros into the register to create a pulse
one clock period wide.
The accuracy and repeatability depends primarily'
on the accuracy and stability of the clock. Crystal
clocks can be built with +0.005% tolerance and less
than a 1% variation due to temperature.
An inherent difficulty is the synchronization of
Memory Request and the clock. At times there will
be a latency of one clock cycle between Memory
Request and the actual start of the cycle when
Memory Request becomes active just after the
clock edge. Assuming an 80 ns cycle and 20 ns
clock, the latency can be 20 ns or 25% of a cycle
stretching both access and cycle accordingly. A
second difficulty of this circuit is caused by the
asynchronous nature ofthe clock and the Memory
Request. The request becomes active just prior to
3-18
AP-74
the clock and the set-up time of the latch is
violated, the output QA "hangs" in a quasi-digital
state and could double or produce an invalid pulse
width; this and the latency hinder effective use in
high speed design.
MONOSTABLE MUL TIVIBRATOR
The second possible timing generator is a series of
monostable multivibrators, using a device such as
the AMD Am 26S02 multivibrator. It has a
maximum delay from input to output of 20 ns and
an approximate minimum of6 ns. However, with a
delay of20 ns, the monostable multivibrator offers
no advantage over the clocked generator. Having
a minimum pulse width of 28 ns, the one-shot
offers no improvement over the 50 MHz clock, but
in fact the performance is worse because it is more
temperature and voltage sensitive. The pulse
width is dependent on the RC network composed
of resistors and capacitors that are temperature
sensitive. Consequently, repeatability leaves
something to be desired.
generators. The leading edge travels down the
delay lines. When the edge reaches the 25 ns tap,
the output is inverted and fed back to the R input of
the R-S flip flop, shaping the pulse to width to 25
ns. Twenty-five nanoseconds was chosen to match
as close as possible the write pulse width. A 25 ns
pulse limits the Memory Request signal width to
less than 25 ns to insure proper operation.
Otherwise, the R-S flip flop will not clear until
Memory Request return,s to a one level. As the
pulse travels down the delay lines, it acquires
additional skew of ±1 ns per delay line package for
a total of 6 ns overall. Figure 38 shows several
timing pulses and the uncertainty of each edge calculated by worst case timing analysis. The
remaining problem is selection of timing edges to
operate the device_ Now that the timing chain is
completely defined, specific details of the address
latch, write pulse and output enable can be
completed.
ADDRESS LATCH TIMING
An R-S flip flop activated by. MEMREQ latches
the addresses. A second signal which we will now
calculate is used to open the latch. This signal has
two boundaries. If the latch opens too late, the
access of the cycle will be extended; if it opens too
soon, the current cycle will be aborted. Skew
through the R-S flip flop is 1.75 ns to 5.5 ns and
skew in the latch from enable to output is 4 ns to 12
ns for a total skew of 6 to 17.5 ns. With this skew
added to the 30 ns address set-up time, the latch
opening signal must be valid at 36 ns best case or
DELAY LINE
The third and best choice is a delay line. This
design uses STTLDM-406 delay lines from EC2
with tapped outputs at 5 ns increments. In
operation, Memory Request activates an R-S flip
flop fabricated from cross coupled NAND gates.
The output of this circuit starts the memOry cycle.
Consequently, the cycle starts 5 ns after Memory
Request compared to 20 ns for the other two timing
I
T60
T10
TO
TSO
TO
I
I
I
I
I
==::::x:::=
ADDRESS
MEMREa~
eLK
-D
TAP 35
TAP40
TAP 45
TAP 50
TAP 55
TAP 65
TAP 70
Figure 38. Timing Chain
3-19
AP-74
47.5 ns worst case prior to the start of the memory
cycle. Each cycle is 80 ns long, therefore, the latch
opening signal must begin 44 ns or 32.5 ns,
respectively, in the preceding cycle. From the
delay line timing diagram, ,T35 will satisfy the
worst case requirements for opening the latch and
T 25 best case. In production, each board is tuned
by selecting T25, T30, or T35 to open the latch,
guaranteeing it opens between 35 and 30 ns prior
to the start of the cycle.
to 8 ns. Subtracting 8 ns from 50 ns sets the
termination of the write timing edge at 42 ns.
Using the inversion ofT25 will end the write pulse
at 43 ns with 7 ns to spare.
Data set-up time is guaranteed because data is
valid 6 ns (the worst case delay through the latch)
after the start of MEMREQ.
'
OUTPUT ENABLE TIMING
There is a 5.5 ns delay through the address driver
providing minimum device cycle of 50 ns. As a
result the earliest data can disappear from the bus
is at 54 ns because of delay through the output circuit. To select the timing tap for the output enable,
the skew of the enable circuit is subtracted from
the system access time.
WRITE PULSE TIMING
The next timing to be calculated is the write pulse.
Figure 39 shows the three parameters which
define the write pulse timing: data set-up time,
write pulse width and write recovery time. Data
set-up is assured by having data valid through
the entire cycle.
t
Subtracting the 28 ns skew of the buffer enable circuit from the 44 ns access time pfthe system shows
that the latest the timing edge can occur is 16 ns,
which is satisfied by edge TlO. The trailing edge,
however, ends at 37 ns and with minimum propagation delays the bus would become three-stated
at 44 ns, coincident with data becoming valid.
ORing T20 with TlO will guarantee the output is
valid until 54 ns, minimum. Selecting a timing gap
between T35 and T50, depending on the
propagation delay in the enable circuit, disables
the output at 70 ns, allowing input data to be valid
for 10 ns prior to start of cycle. The complete
schematic is shown in Figure 40.
WR
ADDRESS
-------------------------+'I~-----
DATA
t DH
Figure 39. WE Constraints
SUMMARY
Placement of WE in the cycle is controlled by
address change to comply with tWR- From
previous calculations the earliest addresses can
change is 50 ns, which defines the end ofthe WE
signal. Our calculations begin at the device and
work back to the timing edge. Eight devices
constitute a 40 pF load and a 74S40 is specified for
a 50 pF load, reducing delay by 0.5 ns when
driving 40 pF. Trace delay and 74S40 delay is 3.5
The 2147H is an easy-to-use, high speed RAM. The
problems in a memory system design are the result
of inherent limitations in interfacing. Largest of
these is skew, which the designer must strive to
minimize. In this example, skew consumed 45 ns
of an 80 ns cycle while device access time was
extended by only 10 ns, resulting in an 80%
efficiency.
3-20
.
:.
v
.---
AOD
I
I
I
A3
--l>
....
SO.
•
--'-
Ij
I
I
I
I
I
I
I
SO,
~
~
5158
~
.----
A.
I
I
I
A7
A8
SO,
•
5158
-
I
I
I
A11
i
A12C
I I
I I
t
I
A15~
5158
I
I
I
:
f...-------.-J
r--S04
'A17D-
•
5158
130
........
~
....
L...-
I
I
V
-L
....
....
MOO
524
MO'_
W:i
-
~
Wi
~
Wo
M08_
-J-
52'
M015_
"-----r
CA11RU
MIO~
r - '-1
CS2R
~
CA11LU
r----.
CA11ll
.----
CS3R
r--'
CA11RL
MI2_
5158
MI7_
So.
,-CSOR
~
'-
:
CS1L
....
~~
V
5260 WR
so.
BOARD ENABLE
c>-r--- rc>C>C>-
5157
r-
•
;04
i~
BOX
ClK
CS3l
~
h
$158
i-
CS2l
P-'
: t...::
,--Ml15 _
FI--"
'"JBH'" . I ,, 111'
TSO
WE
1'11J
5
,'~
MEMiiEO
MEMREQ~ L . . . - r-
Figure 40. 16K X l6-Bit High Speed Static Memory
I- -
MI8_ f -
CSOl
P--'
l-
•
CS1R
'---
1>'
-
-
M07_
--l..J
WE
1>'
--t>
W3
--l..J
.....
:1~
toL-..!:_
Do---
--l..J
I
cf}-
A16
CAOll
TO
~I .
I
·r----.J
I
~
no
T20
-t:
......
I
540
CAORL
Tis
....
i ----i
Cf
"
";;
...-L'
.....
'KO
....
~
..""..
•
5158
'--
N
CAOlU
CAQLU
TO
25 ns DELAY LINES
STTLO m 406
160
I , , '1
APPLICATION
NOTE
Ap·131
March 1982
© Intel Corporation, 1982
3·22
intJ
AP·131
16-bit address words onto eight address input pins. The
two 8-bit address words are latched into the 2164A by
the two TTL level clocks: Row Address Strobe (ill)
and Column Address Strobe (CAS). Noncritical timing
requirements allow the use of the multiplexing technique while maintaining high performance.
1. INTRODUCTION
The Intel@ 2164A is'a high performance, 65,536-word by
I-bit dynamic RAM, fabricated on Intel's advanced,
HMOS-D III technology. The 2164A also incorporates
redundant elements to improve reliability and yield.
Packaged in the industry standard 16-pin DIP configuration, the 2164A is designed to operate with a single
+ 5V power supply with ± 10010 tolerances. Pin 1 is left
as a no-connect (N/C) to allow for future system upgrade to 256K devices. The use of a single transistor cell
and advanced dynamic RAM circuitry enables the
2164A to achieve high speed at low power dissipation.
Data is stored in a single transistor dynamic storage cell.
Refreshing is required for data retention and is accomplished automatically by performing a memory cycle
(read, write or refresh) on the 128 combinations of RAo
through RAt; (row addresses) during a 2-ms period. Address input A7 is a "don't care" during refresh cycles.
The 2164A: is the first commercially available dynamic
RAM to be manufactured using redundant elements and
also features single + 5V operation, low input levels
allowing -2V overshoot, a wide tRCD timing window,
low power dissipation, and pinout compatibility with
future system upgrades. These features make the 2164A
easy and desirable to use.
3. DEVICE OPERATION
3.1 Addressing
A block diagram of the 2164A is shown in Figure 2. The
storage cells are divided into four 16,384-bit memory arrays. The arrays are arranged in a 128-row by 128column matrix. Each array has 128 sense amplifiers connected to folded bit lines.
2. DEVICE DESCRIPTION
The 2164A is the next generation high density dynamic
RAM from the 2118 +5V, 16K RAM. Pin 1 N/C provides for future system upgrade of 64K to 256K sockets.
The 2164A pin configuration and logic symbols are
shown in Figure 1.
figure 3 depicts a bit map of the 2164A and also shows
the Boolean equations necessary to enable sequential
addressing of the 16 required address bits (Ao-AlS).
There is no requirement on the user to sequentially address the 2164A; the bit map and Boolean equations are
shown for information only.
Sixteen bits are required to address each of the 65,536
data bits. This is accomplished by multiplexing the
PIN
CONFIGURATION
BLOCK DIAGRAM
LOGIC
SYMBOL
128. 128 CELL
MEMORY ARRAV
.,
.,
A6
1~~~28
DECODERS
12f1.12&CELL
MEMORY ARRAY
Doy '
'"
'"
or
m
ROW ADDRESS STROBE
Figures 1 & 2. Intel' 2164A Pin Assignments and Block Diagram
3-23
_VDD
Ap·131
INPUT
ADDRESS
TOPOLOGICAL
ADDRESS
o
,
2164A
NlC 1
18 Vss
SPA~E
,
SPARE
COLrMNS
[5!]
COLrMNS
cccccccc
"AA"""""
7 6 5 4 2 , 0
~
on
O,gOOOOl
~
lUl000Ql
00100001
11100001
I 10 ~ 0 ~ 1
o
10010001
"
1 0 1 1 ~ 0 0 1
001'0001
11110D01
10001Qn1
00001001
~
~~
~ ~j
~~Qw.~ w
Ao
;f
5
In
"
"
""
"
14 DOUT
~~
~(J~
In
RAS 4
~
..
.1
:IDECODER
,.
Z
;f
,,,"
12 A,
In
::
"
6
spIRE
COLUMNS
VDD
~
MSB.
splRE
1
.
1o A,
"
"
""
"
"
"
""
COLUMNS
9
8
A,
2164A
ADDRESS
PIN
PROGRAMMED
ADDRESS
ROW
ROW ADDRESS
SCRAMBLING
RAO
RAI
RA2
RA3
RA4
RA5
RA6
RAT
NOTE: Bit Map can be determined
from Address Map equations.
COLUMN
CAO
CAl
CA2
CA3
CA4
CA5
CA6
CAT
AOR
AIR
A2R
A3R
A4R
A5R
00'01001
11101001
, D
~
1 10 0 1
00011001
0101,001
10111001
00111001
111"001
000001 0
~
A6R
COLUMN ADDRESS
SCRAMBLING·
01100101
D0010101
tl010101
,~
01110101
11001101
0100"01
10101101
01101101
10011101
.
01111101
10000011
00000011
11000011
01000011
10100011
00'00011
11100011
01100011
100'0011
..
..
."
.
'"
,.'"
"010011
0.010011
'01100"
00110011
01110011
'000.011
0000.011
'"
m
,.
Acii
$
D,N
'"
'"
.
'"
'"
'"
"'"
'""
.
COLUMN
ADDRESSES
'"
'"
"'"
'"
'"
'"
'"
m
011010"
00011011
'0"1011
001110.,
'000011'
00000'"
0100011,
'0'00'"
00100111
00010111
11010111
,M
'"
.'"'"
01001011
10101011
W
ACT
AC6
AC5
AC4
AC3
AC2
ACI
on
'"
'"
"'"
~
90',a101
11'101Gl
0'011101
10111101
"
ATR
OU10Dl01
1'100101
.
.
AIR
A2R
ATR
ATR
ATR
ATR
ATR
(j)
(j)
(j)
(j)
(j)
(j)
(j)
INTERNAL DATA_AOR ~ A7C
TOPOLOGICAL
ADDRESS
.,001001
01001001
1Ql010g,
11000101
""
""
"
"
0
A.
'"
00010001
1
·lSB
DECIMAL
EQUIVALENT
10000001
00000001
1111011.
011'0'"
1000'11'
00001111
11001111
0'0011"
'"
" .
'"
'"
'"
'"
n'
,,''"
11101111
0110111'
011'""
'"
'"
"'"
1111""'''111"","",,,,,
, 1 1 , , 1 , • 1 , 2 2 2 2 2 2 2 2 2 2 I 3 J a 3 3 l 3 l 3. 4 4" •• 4 4 4 5 5 5 5 ~ 5 5 5 S ~ 6 6 8 6 6 6 8 6 6 6 11 7 1 111111! 8 8 U 8 I! 8 I 8 9 ~ 9 9 999 9 9 ~ 0 0 0 0 0 0 0 0 a 0 1 1 1 , , , 1 , , , 222 2 2 2 • 2
0, ~ 34 581890 1:1 ~. 5 61890 1 2 34 S 6 1890' 2 34, 6 18 90,. J 4 5618 ~o 1 2 3458' 890' 23 458 1a 90 1 2 345 6 1 890 1 2 J . 51 1890 1 2 345 6 r ~9 0, ~3 4 0 6 7 890 1234" 6 7 e 9 0 t ~ J 4 ~ 61
INPUT
ADDRESS
DECIMAL
EQUIVALENT
66 B 6 7 1 ti & r 1 1 1 7 7 7 1 8 e 9 8 I 8 e 8 9 8 9 9 9 9 9 9 9 ~
4" 7e 0 1962 3 5.89 76 0 1 3 2 6 7 54 a
0 4 5 32 6 n
g.
~
9 1 1 1 • 1 1 , 1 1 1 1 , , 1 1 • , 1 1 , 1 1 , 1 1 tIl 0 1
8~~~~~~~~~: ~ ~~~; ~ ~ ~~! ~ ~ ~ ~~; ~ ~
j
2 6 ? , 489 1 1 1 " T 1 1 1 1 2 2 2 2 ~ 2 2 2 j 3 2 2 J 3 3 3 3 3 3 J 4 4 •• 4 • 444 4 5 5 5 5 5 , 5 5 5 556 6 6
1045326' ~ 8 23' O. 5 7"0' 9.2 J5 459' 8Q' 3 28' 5 4891
45 3 2 8 7 982 3,
..
°
~---ROW
°
ADDRESSES
C835
Figure 3. Intel® 2164A Bit Map
3·24
AP·131
ROWADDRESSES--------------------------------------------------------------------;~~
TOPOLOGICAL'
ADDRESS
11111111111111111111111111111111111111111111.111111111"'1"1111111111111111111111111111111111111111111"111111,111111",\\1"""'''7
000000000000000000000000000000000000000000000000000000000000000011111111111111111111111111111""'1111111111"'11111111111111111RAII
111\1111"\1111111111,1'1",,,,100000000000000000000000000000000"1"'11111111111111111111111111000000000000OQOOOOOOOQOOOOQaOOOORM
11111111111"'11000000000000000011\11111111111110000000000000000"""111111111100000000000000001111,,111111'11100000000000000001'1....
111111110000000011111'1100000000111"'11000000001111111100000000'""",00000000"1"'1'00000000"""1100000000II",11'00Q00000FlA3
""0000,11100001,110000,1"0000,1110000'1,,0000,1110000111100001"'0000111,000011,10000,1,,0000111'0000',110000111!000011110000RA2
001,1,0000,,1'00001,'1'00001,',0000111100001"'00001111000011"0000111'0000"110000",10000,,,100001"10000''I'QOOOll1'OOOO.,1'00RAl
01100110011001100110011001100110011001100110011001100110011001100.,001100"0011001,0011001,00,1001100,,001100110011Q011001100110RAO
1111\ , 1 1 1 11 11 1 11 1 1 1 1 1 1 1 1 11 I 11 I 1 1 1 11 11 111 1 11 1 1 1 , 1 , I , 1 1 1 1 1 1 111 111 1 2 ~ 2 2 2 2 2 2 2, Z. 2 2 2.2 •• 222.2.22 • • • • • 2 •• 2 • • • • • 222.2222.222122111 1 1111
8 6' i 8 8 8 & 6 6 6 8 I 1 I 1111111 6 668 6 6 ti 6 6 6 5 5 ~ 5 J 5 5 5 •• 5 5 , • • • • ' " 3 3 3 3 3 3 3 3 J J 2 2 5 5 6 5 56. 4 4 4. 4 4 4 •• 3 3 3 3 J 3 3 3 2 2 3 3 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 9 8 • 8 ~ 9. t
'110815' 0 1 3 2 19 7 6 2 3 S 40 1 9 8 4 5 16 2 3 1 0 6 1 9 B 4 5 3 2 8 9 1 0 e 1 5 4 0 1 3 2 B 9 7 ~ 2 3 S 401962354019 B. S 7 ti 2 J 1 0 6 1 9 8 4 5 3 2 8 9 1 0 6 1 5 401 328918235' 0 1 9 6.51623106198.532
INPUT
ADDRESS
DECIMAL
EQUIVALENT
INPUT
ADDRESS
TOPOLOGICAL
ADDRESS
,,.
,,,
..
'"
'"
'"
ccccc
AAAAA
43210
00000
00000
00000
00000
00000
10000
10000
10000
10000
10000
10000
01000
01000
,~
'"
'",
'"
.
...
'"
'"
'"
,,,...
'"
COLUMN
ADDRESSES
01000
01000
,.000
11000
11000
11000
11000
00100
00100
00100
00100
00100
10100
10100
10'00
10100
10100
".
:::
'"
".
'"
'"
'"
.,,.
m
.,'"
~
'"
'"
'"
'"
'"
'"
".
".
".".
m
,.'"'"
m
'"'"
".'"
~
'"
'"
".
..
.
'"
·
·"'"'"
·'"'"
·,...'"
·",.'"
DATA MAP EQUATION
INTERNAL DATA = DATA IN <±lIAOR <±l A7C)
,
AOR
A7C
INTERNAL
DATA
DATA IN
(0,.)
'"
"'"
".
".
I!!!! ".
,.
11100
11100
11100
00010
00010
00010
00010
00010
10010
10010
10010
10010
01010
01010
01010
01010
11010
00110
m
'"
DECIMAL
EQUIVALENT
00110
00110
10110
10110
2164A
N/C
1
.
'"
.'"
.'",.
'"
'"
".
.
,.",.
.'",
SPARE
COLr MNS
~
1 5 CAS
-LSB
14
ffi0
.."
DOUT
0
~
"".
".
16 Vss
SPARE
COL1 MNS
~
r-""
5
A2
6
~
1 3 A,
~
~ Of
en %Z~
1 2 A,
0
~t---
::!~
~~DEc"'d8'fR
~~~
~5%
spIRE
COLUMNS
Voo
~~
~
MSB.
3EJ
SlRE
COLUMNS
11A"
1o A,
8
9
A,
"
10110
10110
01110
011'0
01110
01110
""0
11110
•.
,..
"'"
,
"
.
ca36
Figure 3. Intel® 2164A Bit Map (continued)
3-25
Ap·131
(Figure 5b). The bit sense line is precharged to Voo
when RAS is high (Figure 5c). During an active cycle,
the row select line goes high, and the charge is redistributed (shared) with' the bit sense line (Figure 5d).
The sense amplifier detects the level from the cell and
then reinstates full levels into the data cell via a capacitive bit line restore circuit. At the end of the active cycle, the row select line goes low, trapping the data level
charge on the stored cell.
3.2 Active Cycles
m
When
is activated, 512 cells are simultaneously
sensed. A sense amplifier automatically restores the
data. When CAS goes active, Column Addresses CAoC~ choose one of 128 column decoders. CA7 and RA7
gate data sensed from the sense amplifiers onto one of
the two separate differential I/O lines. One I/O pair is
then gated into the Data Out buffer and valid data appears at DOUT'
3.5 Data Sensing
Because of independent RAS and 00 circuitry, successive CAS data cycles can be implemented for transferring blocks of data to and from memory at the maximum rate - without reapplying the RAS clock. This
procedure is called Page Mode operation and is described in more detail in Section 4.6. If no CAS operation takes place during the active RAS cycle, a refreshonly operation occurs: RAS-only refresh.
The 2164A sense amplifier compares a stored level to a
reference level (Vss) in a special, non-addressable storage cell called a dummy cell.
V D• STORAGE
PLATE
I~~~
3.3 Storage Cell
The basic storage cell is shown in Figure 4. Note that the
2164A uses two dummy cells on each bit line to help
compensate for alignment effects. Data is stored in
single-transistor dynamic RAM cells. Each cell consists
of a single transistor and a storage capacitor. A cell is accessed by the occurrence of row select (RAS) clocks
Ao-A7 into the address pins, followed by column select
(CAS) multiplexing As-AJS into the address pins.
ROW
SELECT
,
I
ROW SELECT
GATE
•
~~
) '
•
I
BIT/SENSE'
LINE
L-.J
: --r-LJ---') -,t""_.,-_.,-._""._,-.,..._....
I
I
b)
' ...
C
_
CIRCUIT DIAGRAM OF BASIC
STORAGE CELL
_-_.!
CROSS SECTION OF BASIC
STORAGE CELL
"
BASIC CELL DURING
PRE.CHARGE
-,,...-,:--::--,--:--:--=::--.::-=r- BASIC CELL IS ROW SELECTED
-~_--H_ _;-"""""r---r--\' BIT
'LINE
~=~~~iSTOR ~
d)
L··
- • 0 - . • 01
-------'-!....!.J
e)
\ ...e~!,e!.'!! ~!.e
!!\:tIItJ
L:!:!J
CHARGE IN CELL REDISTRIBUTED
WITHBITLINE
CELL CHARGE IS RESTORED
ROW SELECT GATE IS DESELECTED
63 STORAGE CELLS AND
'2 DUMMY CELLS
STORAGE
NODE
I
VDD 0-0------<->------\1
.---l.-
I
\-')_-4----<>--...----\
Figure 5. Sensing
Figure 6 depicts a simplified schematic of the 2164A
sense amplifier. The sense amp contains a pair of crosscoupled transistors (Ql and Q2), two isolation transistors (Q3 and Q4), and a common node which goes low
with SAS (Sense Amp Strobe) and activates the sense
amp. The bit-sense lines (BSL and BSL) run parallel out
from the sense amp in a folded bit line approach. Each
bit line contains 64 data cells and two dummy cells. The
double dummy cell arrangement helps limit the effect of
mask alignment on sensing margins by having a dummy
cell oriented in the same direction as the data cells.
Figure 4. Storage Cell
3.4 Charge Storage in Data Cell
,
\
Data is stored in the 2164A memory cells as one of the
two discrete voltage levels in the storage <;apacitor - a
high (Voo) and a low (Vss). These levels are sensed by
the sense amplifiers and are transmit~ed to the output
buffer. Sensing of stored levels is destructiv!,:, so
automatic restoration (rewriting or refreshing) must
also occur.
The folded bit line approach has several advantages,
one of which minimizes the effect 'of interbit line substrate noise and I/O coupling by providing common
mode noise rejection. This sense amp arrangement uses
metal bit lines and polysilicon word lines.
The charge storage sensing mechanism for a stored low
is described in Figure 5. The Vou storage plate creates a
potential well at the storage node. For a stored low, the
charge is stored in the cell relative to the storage plate
3-26
inter
Ap·131
ROW
SELECT LINE
BSL
BIT LINE RESTORE
BIT LINE RESTORE
V
o
DUMMY
SELECT
LINE
• FROM BIT LINE
ISOLATION CLOCK
PLATE
Figure 6. Sense Amp
To eliminate sensing problems, a three-step sensing
(Figure 7) is employed in the generation of Sense Amp
Strobe clock (SAS). Device A is triggered by the sense
strobe clock. This device pulls do)Vn slowly and when
fed back, triggers the two gates D and E. When SAS is
low enough, device B turns on, pulling the SAS line
lower and at a later time, device C pulls §AS down hard.
If sensing occurs too quickly, the sense amp becomes
sensitive to capacitive imbalance and sensing errors
might happen. This design elim'inates excessively fast
sensing which can occur when two sense strobe clocks
are being used.
precharge, the row select and dummy select lines are at
Vss, isolating the cells from the bit lines. When RAS
goes low, the precharge clock goes low, ending the precharge period.
3.7 Data Sensing Operation
The row select and dummy select gating are arranged so
the selected data and dummy cells are on alternate bit
lines of the sense amp (Figure 6). The row select and
dummy select lines go high simultaneously, resulting in
concurrent charge redistribution on the bit lines. The·
relationship between the word select lines and the effect
of concurrent charge redistribution on the bit lines is
shown in Figure 8. An approximate 250 mV differential
results from this charge redistribution.
WORD SELECT LINES (DUMMY AND DATA)
j/
_...1'"_
SENSE
STROBE .....
CLOCK
TIME (ns)
voot~--_~~~~~R~~~
-'~
Figure 7. Intel® 2164A Sense Amp Clocks
DUMMY BIS LINE
............. _
3.6 Precharge
I
.. _ _ _ _ _ _ _
--
f 250 mV
~50mv
DATA BIS LINE (STORED LOW)
--==--:-
Vss L _ _ _ _ _ _ _ _ _ _ _ _ _
A precharge period is required after any active cycle to
ready the memory device for the next cycle. This occurs'
while RAS is high. The bit lines are precharged to VDD,
while the dummy cells are precharged to Vss. During
TIME (ns)
BIT LINES DURING CHARGE REDISTRIBUTION
Figure 8. Sensing Voltage Waveforms
3·27
Ap·131
After charge redistribution, the sense amp is activated.
The sense amp amplifies the differences in the resultant
voltages on the bit lines. The line with the lower voltage
potential is driven to Vss. The other line remains at a
relatively high level, as shown in Figure 9.
lines. The I/O is a pair of opposite polarity data lines
(110 and I/O) which are connected to the Data Input
(DIN) and Data Output (DOUT) buffers. Data is differentially placed on the 110 lines during read operation
and multiplexed to the final I/O lines. During a write
cycle, data is differentially placed on the final I/O lines
from DIN and decoded onto the internal 110 lines.
Stored levels are determined by CA, column and RAo
row exclusive-ORed product and then exclusive-ORed
again with DIN (Figure 3). Stored levels are decoded
during DOUT operation and have no effect on device
use.
VDD~==::::;~",::",:-:",:-:...:-=-,:-:",,:~
RESTORING
STORED HIGH
I~
SENSE AMP
::;
ACTIVATION
~
v•• -
-
-
I
I
RESTORING STORED lOW
t-
3.9 Address Latches
TIME (n8)
The 8-bit row and column address words are latched
into'internal address buffer registers by RAS and CAs.
RAS strobes in the seven low-order addresses (Ao-A,)
both to select the appropriate data select and dummy
select lines and to begin the timing which enables the
sense amps. ~ strobes in the eight high-order addresses (Ag-AlS) to select one of the column decoders
and enable I/O operation.
Figure 9. BIUSense Line Voltage
The bit line boost circuitry is shown in Figure 10. During sense operations, the boost capacitors are isolated.
After sensing, the bit line with a "0" has the capacitor
turned off (Vas"'O) and, conversely, the bit line with a
"1" has the capacitor turned on. The boost clock will
turn on and boost the I-level up above VDD , giving
maximum charge stored in the cell.
BSL---'------'
BSL-------'
BIT LINE
BOOST
ISOLATION
CLOCK
Figure 12 shows a simplified 2l64A address buffer. As
tRwo min and tcwo>tcwo min). A
RAS-only refresh cycle or a CAS-only cycle will have no
effect on DOUT which will remain in the Hi-Z state.
DOUT remains valid from access time until CAS goes
high. Holding CAS low and taking RAS high will not
affect the state of the DOUT. The DOUT remains valid
following a valid Read cycle regardless of the number of
subsequent RAS-only cycles performed on the device up
to the tCAS max limit. These secondary RAS cycles are
RAS-only refresh cycles to the 2164A.
RAS and CAS have minimum pulse widths as specified
in the 2164A Data Sheet. These minimum pulse widths
and cycle times must be maintained for proper device
operation and data integrity. A cycle, once begun, must
be within specification.
.
Figure 16 briefly summarizes the various active cycles
which are discussed in paragraphs 4.1 through 4.6.
4.1 Read Cycle
A Read cycle is performed by maintaining WE high during a RAS/CAS operation. The output pin of a selected
device remains in a high impedance state until valid data
appears at the output within the specified access time.
3.12 Power·On
Device access time, tACC, is the longer of two calculated
intervals:
An initial pause of 500 /1S is required after the application of the Voo supply, followed by a minimum of eight
(S) initialization cycles (any combination of cycles containing a RAS clock such as RAS-only refresh) prior to
normal operation. Eight initialization cycles are required
after extended periods of bias (greater than 2 ms) without clocks. The Voo current (Ioo) requirement of the
2164A during power on is, however, dependent upon the
input levels of RAS and CAS and the rise time of V00 as
shown in Figure 15.
Eq. (1) tACC=tRAC or
Eq. (2) tACC = tRCO + tCAc
Access time from RAS (tRAd, and access time from
CAS (tcAd, are device parameters. Row to column address strobe delay time, tRCO, is a system-dependent
timing parameter. For example, substituting the device
parameters of the 2164A-20 yields:
Eq. (3) tACC = tRAC = 200 ns for 35 nS:5 tRCO:5 80 ns
Eq. (4) tACC = tRCO + tCAC =tRCO + 120 ns for
tRCO>SO ns
Note that if 35 nS:5tRC0:5S0 ns, device access time is
determined by equation 3 and is equal to tRAC. If
tRCO> SO ns, access time is determined by equation 4.
This 45 ns interval (shown in the tRCO inequality in
equation 3), in which the falling edge of CAS can occur
without affecting access time, allows for system timing
skew in the generation of CAS. This allowance for tRCO
skew is designed in at the device level to allow the fastest
access times to be utilized in practical system designs.
~ 5
~
w
II:
4
1-----11-------1---1---1
g
3 1-----I1---c71-~-~
t
2/--/+--+ CAS=I Voo -
~
1
~
/'
AJ:S=VOD
/-+-1/---1---1---1
.L/
50
100
TIME
150
"'~)
TIME ",s)
4.2 Write Cycles
Figure 15. Typical 100 vs. Voo During Power Up
4.2.1 EARLY WRITE CYCLE
If RAS = Vss during power on, the device may go into
An early write cycle is performed by bringing WE low
before CAS. DIN is written into the selected bit. DOUT
remains in the Hi-Z state.
an active cycle and Ioo would show spikes similar to
those shown for the RAS/CAS timings. It is recommended that
and CAS track with Voo during
power on or held at a valid Vm.
m
4.2.2 LATE WRITE CYCLE
4. DATA CYCLES/TIMING
A late write cycle happens after RAS and CAS go low.
During a late write cycle, tRWO and tcwo (RAS and
CAS delays to Write Enable) minimum timings are not
met. Since there is no guarantee that DOUT will remain
in a Hi-Z state, the condition of DOUT is indeterminate.
A memory cycle begins with a negative transition of
Both the RAS and CAS clocks are TTL compatible. The 2164A input buffers convert the TTL level signals to MOS levels inside the device.
m.
3·30
Ap·131
4.3 Read-Modify-Write Cycle
(Delayed Write)
4.4 CAS· Only Cycle
A CAS-only cycle has no effect on the 2164A. The
2164A remains in the lowest power, standby condition.
A Read-Modify-Write (R-M-W) cycle is performed by
bringing WE low after RAS and CAS are low. Here,
tRWD and tcWD minimum timings are satisfied. DOUT
has had time to become valid and is now latched by CAS
remaining low. As WE goes low, a write begins, transferring the data from DIN to the cell as DOUT remains
active with the previous data.
4.5 Refresh Cycle
A cycle at each of 128 row addresses will refresh all storage cells. Any memory cycle - Read, Write (Early
Write, Delayed Write, R-M-W) or RAS-only - refreshes the bits selected by the row address combinations of Ao through At;. Both 32K halves are refreshed,
as the state of A7 is irrelevant during refresh.
In any type of Write cycle, DIN must be valid at or
before the falling edge of WE or CAS, whichever is
latest.
"EARLY"
- - R E A D CYCLE-- - - WRITE CYClE-- --RAS ONLY CYClE--
DOUT
-+-----{
--CAS ONLY CYCLE---READIMODtFY/WRITE C y C L E - - - -
LATE WRITE
OOUT-~--------r---~V~AL~ID~F~R~O~M~R~EA~D~~----~~~~~J
I - - - - - - H I D O E N REFRESH C Y C l E - - - - - - j
_ _ READ CYCLE
OOUT
WE
Dour
- - R A S ONLY CYCLE-_
VALID
-~--------~
-+------{
VALID
r--"t--------t---\'::~~~~~
Figure 16. Intel® 2164A Operation of Data Output for Various Active Cycles
3-31
intJ
Ap·131
set. This is done by maintaining RAS low while successive 00 cycles are performed:
4.5.1 READ CYCLE REFRESH
Since A7 is' irrelevant for refresh addressing, a row refreshes 512 cells. The 256 cells in Ii specific row addressed (Ao-~, A7) are refreshed as are another 256
cells in the row Ao-~, A7. Therefore, addressing a bit
in a row refreshes the 256 cells associated with that row
(Ao-A7)' For refresh purposes, row Ao-~ and Ai is
also addressed as another 256 cells. Therefore, successive reads of the 128 row combinations of Ao-~ refreshes the entire array of the 2164A ..
Page Mode operation allows a maximum data transfer
rate as RAS addresses are maintained internally and do
not have to be reapplied. During this op~ration, Read,
Write and R-M-W cycles are possible. Following the
entry cycle into Page Mode operation, access is teAC dependent. The Page Mode cycle is dependent upon CAS
pulse width (teAS) and the CAS precharge period
. (tCPN)'
This refresh mode is useful only when the memory system consists of a single row of devices. When used with
more than one row of devices, output bus contention
will result.
5. SYSTEM DESIGN CONSIDERATIONS
Calculating total 2164A power consumption is a simple
task. To illustrate the method of calculating power, an
example system organized as 256K words by 16 bits is
assumed.
4.5.2 WRITE CYCLE REFRESH
A Write cycle will perform a refresh. However, the
selected cell will be modified to DIN. This may cause a
change of state of selected cell, while the other 511 cells
are refreshed.
'
The first step is to compute the total 2164A current by
summing the three individual Voo 2164A ·supply currents: (I) operating current (1 0 00)' (2) standby current
(Ioos), and (3) refresh current (IOOR)' The total2164A
power consumption equals the 2164A current multiplied
by the maximum supply voltage (Voo). Total system
power consumption is determined by adding the support
circuitry power requirements to the total2164A power.
For an Early Write refresh cycle, there will be no output
bus contention since the output remains in the Hi-Z
state. Bus contention will result for Delayed Write or
R-M-W refresh cycles involving more than one row of
devices.
Examples of these calculations, along with a power/bit
determination, are presented in following sections.
4.5.3 RAS·ONL Y REFRESH
5.1 Power Calculations
A cycle with i l l active refreshes the 2164A. This is the
recommended refresh mode, especially when the memory system consists of multiple rows of memory devices.
The DOUT'S may be wired-ORed with no bus contention
when RAS-only refresh cycles are performed on all rows
of devices concurrently. The 2164A DOUT will remain in
three-state.
.
5.1.1 OPERATING CURRENT (1000)
Active operating current is determined by the following
equation:
Eq. (I) Iooo=(loD2+IoOLO)K
Where:
4.5.4 HIDDEN RAS·ONLY REFRESH
10DO=the operating Voo supply current.
K = the number of active devices (selected
at one time by both RAS and CAS).
The 2164A is designed for "hidden" refresh operation.
Hidden refresh accomplishes a refresh cycle following a
read cycle without disturbing the DOUT ' Once valid,
DOUT is controlled solely by CAs. After a Read cycle,
CAS is held low while RAS goes high for precharge. A
RAS-only cycle is then performed and DOUT remains
valid. However, for operation in this mode, CAS must
be decoded along with RAS for the Read and Write
cycles. CAS cannot be driven as a common clock to the
entire array since it would cause devices being only refreshed to interpret this operation as a RAS/CAS cycle.
100LO = the 2164A output load current (output
leakage current plus the load devices
input current). For example, if four
devices are dot ORed on the output
line, the output leakage current is the
sum of the input current (lIN) for the
load plus the three leakage currents
(ILO) for the three devices standby.
5.1.2 STANDBY CURRENT (Ioos)
4.6 Page Mode Operation
Standby current is determined by the following eQuation:
Page Mode operation allows additional columns of the
selected device to be accessed at a common row address
Eq. (2) loos= 10Dl xM
3·32
intJ
Where:
Ap·131
K= 16 devices active at one time
M = N-K devices in standby
=64-16
=48
1001 = the Voo supply current.
M = the number of inactive devices (not
selected by RAS; receiving CAS-only
cycles).
Referring to the Intel 2164A Data Sheet l and the Intel
8282 Data Sheet2, we obtain the following values:
5.1.3 REFRESH CURRENT (IOOR)
Refresh current is determined by the following equation:
1001 = 5 rnA, 2164A-20
10D2 = 45 rnA, 2164A-20, tRC = 330 ms
1003 = 40 rnA, 2164A-20, tREF = 2 ms
lLO = 10 /lA, 2164A-20
lIN = 200 /lA, 8282
Eq. (3) 100R = (l0D3 X N) (tRC/tREF) (128)
Where: 10D3 = the V00 supply current, RAS-only
cycle.
N = the total number of devices in the system.
To calculate 10DO:
tRC = the refresh cycle time.
Eq. (I) 1000 = (10D2 + 100LO)K
= (45 mA+ [3(10 /lA)+ 200 /lA])16
=723.68 rnA
tREF = the time between refresh cycles.
Since 10D3 is not a full-time current, the- fraction tRC
over tREF represents the duty cycle for one address.
There are 128 row addresses active in generating refresh,
so the duty cycle is multiplied by 128.
To calculate loos:
Eq. (2) loos = (loOl)M
=(5 rnA)48
=240 rnA
Cycle time has a downward scaling effect on the average
operating current according to the following equation:
Eq. (5)
100AVE = [ looi x
To calculate 100R:
(tR~~~~:~:;:ng)
+ [ 1001 X 1 - (
Eq. (3) 100R = (10D3 XN)(tRC/tREF)(128)
) ]
= (40 rnA x 64) 330 ns (128)
2ms
tR~~~~:~:;:ng) )]
At minimum cycle time,
tRC (spec)
(
.)
tRc operatmg
=(2560 mA)(.021)
=53.76 rnA
I,
To calculate total power:
so that worst case 100AVE = 10D2' but as the cycle time
increases, 100AVE approaches the standby current,
becoming 6.3 rnA @ 10,000 ns cycle time. Figure 5 in the
2164A data sheet depicts this scaling effect.
Eq. (4) Power = (1000+ Ioos + 100R) Voo(max)
=5.5V (723.7 mA+24O rnA
+53.8 rnA)
= 5.59 watts
5.1.4 TOTAL 2164A POWER
The power/bit is equal to:
Total 2164A power equals the sum of the three currents
multiplied by the worst case supply_voltage. This is expressed by the following equation:
Power/Bit = (Total2164A Power/Number of Devices)
(Bits per Device)
= 5.59(64 x 65,536)
Eq. (4) Power = (1000 + loos + 100R) Voo(max)
= 1.33 /lwaUs/bit
5.1.5 EXAMPLE POWER CALCULATIONS
5.2 Board Layout
Assume that we have a 256K word by 16-bit memory
system using the 2164A-20 at minimum cycle time.
Thus, the f()llowing parameters apply:
An important consideration in system design is the circuit board layout. A proper layout results in minimum
board area while yielding wider power supply and tim-
N = 64 devices in system
3-33
inter
Ap·131
ing operating margins for increased reliability and easier
manufacturability. The key areas of consideration are:
1.
2.
3.
4.
5.
19). This provides maximum decoupling and minimum
crosstalk between signal traces.
Ground (Vss) and power (Voo) gridding
Power and ground planes
Memory array/controlline routing
Control logic centralization
Power supply decoupling
5.2.1 GROUND AND POWER GRIDDING
Ground and power gridding can contribute to excess
noise and voltage drops if not properly structured. An
example of an unacceptable method is presented in
Figure 17. This type of layout results in accumulated
transient noise and voltage drops for the device located
at the end of each trace (path).
~I
\ I
\ I
I
\ I
\ I
\ !~
I
\ I
\ I
\ I
~
~
I
2164A
,
\
I
I
I
2164A
~
\
2164A
~
-
•
TWO SIDED CARD
•
MAIHGROUND 8US OR INTERCONNECTION TO nL
CONTAOL, ADDRESS. DATA BUFFERS
-
VERTICAL TRACES ON COMPONENT SIDE
HORIZONTAL TRACES ON SOLDER SIDE
Figure 18. Recommended Power Distribution Gridding
RECOMMENDED
NOT RECOMMENDED
Figure 17. Unacceptable Power Distribution
Transient effects can be minimized by adding extra circuit board traces in parallel to reduce interconnection
inductance (Figure 18).
Figure 19. Recommended Voids for Multilayer
PC Boards
5.2.2 POWER AND GROUND PLANE
5.2.3 MEMORY ARRAY/CONTROL LINE
ROUTING
A better alternative to power and ground gridding is
power and ground planes. Although this requires two
additional inner layers to the P,C board, noise and supply voltage fluctuations are greatly reduced. If power
and ground planes are used, gridding is optional but
typically used for increased reliability of power and
ground connections and further reduction of electromagnetic noise.
Address lines should be kept as short and direct as possible. The lone serpentine line shown in Figure 20 is to
be avoided since the devices furthest away from the
driver will receive a valid address at a later time than the
closer ones. A better way to route address lines is in a
comb-like fashion from a central location as shown in
Figure 21. Routing control and address signals together
from a centralized board area will also minimize skew.
It is preferable on power I ground planes to use circular
voids for device pins rather than slotted voids (Figure
3-34
inter
Ap·131
5.2.5 POWER SUPPLY DECOUPLING
For best results, decoupling capacitors are placed on the
memory array board at each memory location (Figure
22). High frequency 0.1 I'F ceramic capacitors are the
recommended type, especially for four or more rows of
devices. In this arrangement, noise is minimized because
of the low impedance across the circuit board traces.
Typical VDO noise levels for this arrangement are less
than 300 mY.
ADDRESS LINE LAYOUT
8 DEVICES
A large tantalum capacitor (typically one 100 I'F per 64
devices) is required at the circuit board edge connector
power input pins to recharge the 0.1 ",F capacitors between memory cycles.
ADDRESS
DRIVER
TOTAL LENGTH OF LINE
20
To calculate decoupling requirements, one considers the
current switching of devices from standby to active currents. This involves IA = IOD2 - IOD! (active cycle) and
IR = IOD3 - IOD! (refresh cycle). One can then assume
some tB bulk decoupling response time with only one
refresh during tB and minimum cycle time tc. As a further example, assume only 114 of the devices are active
at anyone time. The amount of charge (Q) requiring
decoupling is:
Figure 20. Unacceptable Address Line Routing
(Serpentine)
1
ADDRESS LINE LAYOUT
8 DEVICES
Q = IR tc + "4 IA (tB - te).
This charge can then be used to calculate the appropriate decoupling capacitance per device. Using
Coulomb's law, Q=CV, and knowing Q, one picks an
acceptable t. V ( < 400 m V) for noise on the VDO lines.
The capacitance required is given by C = QI t.V. It is important to recognize that C is determined by the current
changes in the devices. Minimum cycle time is used for
calculating purposes. Lengthening the cycle time will
not affect decoupling.
6. THERMAL CHARACTERISTICS
Figure 21. Recommended Address Line Routing
Thermal Characteristics are useful when designing for
thermal systems, 'or for any applicat20n where the temperature may go to extremes.
5.2.4 CONTROL LOGIC CENTRALIZATION
Memory control logic should be strategically located in
a centralized board position to reduce trace lengths to
the memory array. Long trace lines are prone to ringing
and capacitive coupling which can cause false triggering
of timing circuits. Short lines minimize this condition
and also result in less system skew.
The operating ambient temperature ranges ,for the
2164A are guaranteed with transverse airflow that exceeds 200 linear feet per minute.
Typical thermal resistance values of the cerdip package
at maximum temperature are:
A practical memory array layout is shown in Figure 22.
Typically, thi's 'pattern and its "mirror image" are
placed on each side of the memory control logic for a
practical memory board design.
OJA (@200 fpm air flow) =47 °C/W
0jc (still air) = 22 °C/W
3-35
Ap·131
DECOUPLING
CAPACITOR
D",~=.
DOUT'" •
NOTE 1 FUTURE ADDRESS EXPANSION
NOTE MEMORY DEVICE SPACING IS 0 425"
TRACES ARE 50 Mil
Figure 22. 2164A Memory Array PC Board Layout
7. DESCRIPTION OF REDUNDANT
CIRCUITS
.
spare rows and four spare columns were chosen for the
2164A.
The Intel 2164A is the first commercially produced
RAM to incorporate redundant elements into the design. Redundancy allows bit-efficient use of silicon by
maximizing bits/wafer start. By overstressing and
eliminating weak oxide at sort, prior to fusing in redun·
dant elements, long term oxide failures can be greatly
reduced. Redundancy makes possible the use of larger
die sizes allowing better use of existing fab equipment,
and a more conservative layout to utilize larger cell
(storage) areas.
The address of a faulty element is programmed into the
spare element by electrically opening polysilicon fuses
during wafer probe. The basic circuit block diagram for
a spare row is shown in Figure 23. The key logic node
for the spare row is marked by an (A) on the diagram.
When the spare row is not in use, node (A) is held permanently low by transistor (T) whose gate is held high
by the spare row enable block. When the spare row is to
·be used, a fuse is opened within the spare row enable
block and the pulldown gate is brought to ground so
that the programming elements are enabled. Under control of a fuse, either address true or address complement
is transmitted through each programming element.
Thus, by blowing the proper fuses, the address of a faulty row in the array: is programmed into the spare row.
In choosing how redundant elements should be organized, single bits, blocks of bits and spare rows and columns were examined. For maximum efficiency, four
3·36
Ap·131
Figure 24 shows the basic configuration of a programming element. V0 and Vop are special high voltage supplies used only during programming. They are brought
on-chip by extra pads probed at wafer sort. These pads
are not bonded out to the package but instead, Vo is
grounded and Vop is tied to Voo by on-chip transistors.
No inadvertent programming can occur at the package
level because PI cannot turn on and current through the
fuse is limited by the transistor connecting Vop and
x,
x.
t
x.
t
ADDRESS
BUFFER
x. x.
...
x,
Voo. To blow the fuse, the programming address is
brought low, which raises the gate of the programming
transistor P to a high voltage. A high current flows
through the fuse and it opens. When programming is
complete, V0 is brought to ground. If the fuse has been
blown, current through depletion transistor 01 pulls
node (B) to ground and transfer gate T2 passes Xi onto
Xpi. If the fuse has not been blown, node (B) stays near
Vop and Xi is transferred onto Xpi.
t
x,
...
X.
x.
SUPPLY
I
vOLTAGE
I I
PROGRAMMIN G
ELEMEN T
...
Xpo
4~ ...
•
I
I
...
x.'
x••
4~ ...
Y~
SPARE NOR DECODER
SPARE ROW
ENABLE
CLK~C @
0
.
- 2164A tRAe vs Vee
NORMAL
DECODER
INPUTS
1
The concept of using redundancy for yield enhancement
is well-established. Initially researched by IBM in 1964,
Intel has now implemented this concept with the introduction of the 2164A. It is expected that others will follow this lead, and that by the mid-1980's, redundancy
will be standard in all memory devices.
Figure 25. Deselecting a Faulty Element
As mentioned previously, the repair of faulty elements
is done during wafer probing. As they come out of fabrication, all spare elements are disabled, allowing full
testing of the normal array. Bits are tested not only for
hard failures, but also for latent oxide or silicon defects
through stressing. The location of any bad bit is stored
in the tester's memory. This information is then processed to determine the optimum usage of the spare elements. Then, the spare elements are programmed into
their proper logical locations. Finally, the die is tested
once more to assure that repair has occurred as planned.
8. SUMMARY
The Intel 2164A, made possible by Intel's HMOS-D III
technology, introduces a new generation of denser
dynamic RAM devices, featuring redundancy, + 5V-only
TTL-compatible operation, high performance, low
power and ease of use. Additional system level design
information can be found in Intel Applications Note
AP-74, "High Speed Memory System Design Using the
2147H," and AP-133, "Designing Memory Systems For
Microprocessors Using the Intel 2164A and 2118
Dynamic Rams."
The dice are then assembled as usual. Rigorous class
testing is performed to guarantee that the devices meet
3·38
Ap·131
ADDENDUM
again checked for their performance to specifications.
Many devices are simultaneously evaluated whether in a
memory system test environment or in an actual system
manufactured by the user. Problems can also occur
from improper gridding or decoupling on the memory
card itself. With the complicated signal paths in a
memory system, and the difference between vendor
specifications, careful attention must be given to timing
and skews not to exceed data sheet values. Errors from
timing can result in bus contention or can cause many
devices to fail test. Of course, with dynamic RAMs, arbitration between access and refresh modes must be reliable to guarantee the refresh specifications of the RAM.
A typical user qualification program of memory devices
fits into two categories: device-level qualification and
system-level qualification. Occasionally during these
programs, failures occur that are not related to the
device under evaluation.
At the component level, devices are tested individually
for performance to specifications. These tests are usually accomplished with the use of sophisticated software-driven memory testers and environmental handlers. Due to the complexity of the test setup, several problem areas arise. Often testing (software) errors cause
failures. Omission of dummy cycles or violation of
refresh specifications makes failures invalid. Many
times the device under test is remote from the test deck
of the system. This can cause excessive power supply
noise at the end of the cables. Timing skews, glitches 'on
clock lines and 110 levels at the device are complicated
by testing at the end of long cables. Output loading is
also critical for the device to perform to specifications.
These problems can be avoided with careful preparation. However, if problems do arise during qualification, don't hesitate to call your local field applications
engineer or sales office.
REFERENCES
1. Intel® 2164A Data Sheet, March 1982.
During system-level qualification, the problems encountered are significantly different. Here the devices are
3-39
inter
APPLICATION
NOTE
AP·132
June 1982
© INTEL CORPORATION, 1982
Order Number: 210443-001
3-40
inter
Ap·132
the component count and overhead costs, both in design
and implementation.
1 INTRODUCTION
1.1 RAM Overview
Conversely, static RAMs need very little external control
circuitry and they interface easily to most microprocessors. An SRAM has no refresh requirement and usually
has all of its control signals generated directly by the
system microprocessor. A disadvantage of the SRAM is
its high cell complexity. A typical static RAM cell requires four to six transistors - resulting in a lower cell
density and higher manufacturing cost/bit than DRAMs.
Matching the correct RAM to microprocessors is fundamental to effective product design. Understanding the
advantages and disadvantages of each device type
enables a microprocessor system designer to choose the
best product for his particular design objective.
Two basic types of semiconductor random access
memories (RAMs) are in use at present: static RAMs
(SRAMs) and dynamic RAMs (DRAMs). Where large
amounts of memory at the lowest cost per bit is required,
such as main computer memory, the dynamic RAM
holds a commanding position. The extra costs of
refresh, timing and arbitration overhead are spread over
a very large amount of memory. The static RAM,
however, provides a better solution for relatively small
memory systems where high performance or simple
system design is desired.
A new type of RAM has now been developed that combines the best features of the SRAM and DRAM and is
called the iRAM (integrated RAM). An iRAM is an--entire dynamic RAM system integrated onto a single
silicon chip, including the memory array, refresh logic,
arbitration, and control logic. This new implementation
combines the cost, power and density advantages of a
DRAM with the ease of use of a static RAM. Because all
of the DRAM control logic is internal, the memory
system can operate. autonomously, controlling its own
refresh and arbitration. This greatly simplifies
microprocessor interfacing and minimizes additional
TTL hardware support. Proper refresh is guaranteed
and overall system performance improved.
A major advantage of dynamic RAMs is low memory
component cost. A DRAM uses a simple one-transistor,
one-capacitor cell for binary storage. This simple design
achieves high integration density and low cost. When a
DRAM cell is not being written, read or refreshed, it
consumes almost no current. At any given time, the majority of the cells in a DRAM array will be in this conditiOI~ - yielding low overall power consumption.
1.2 iRAM Concept Background
With the advent of VLSI technology and 64K RAM densities, it became possible to further integrate and
simplify memory system design. LSI memory controllers
integrate all of these components into a single device
(such as Intel's 8202A and 8203 dynamic DRAM controllers). Figure 1 shows the major elements of such a
dynamic RAM controller.
One disadvantage of DRAMs are their extensive control
and interface requirements., The DRAM control circuitry must generate signals such as RAS and CAS, provide refresh cycles, and handle ar~itration. This adds to
~
t\
TIMER
I--
IV
~
--V
V
t\
TIMING
GENERATOR
V
MEMORY
CONTROL
SIGNALS
ARBITER
REFRESH
ADDRESS
COUNTER
~7
J\
V
>
MUX
J\
ADDRESS FROM CPU
V
Figure 1. Memory Control BlOck Diagram
3-41
t\
MEMORY
) ADDRESSES
V
AP·132
Figure 2 shows a simple miCroprocessor memory system
implemented with three major blocks: the CPU, the
memory array, and a memory controller. An example of
this configuration is a system comp~ising an 8088 CPU,
and 8203 DRAM controller and a 2}.64A memory array.
To advance this configuration to a higher level of integration would require a decision on whether to place
the memory control inside the CPU or within the
memory itself.
-.?-
CPU
~
['rlI
MEMORY
CONTROL
~
f'rlI
MEMORY
....
A sensible alternative is to integrate the memory controller circuits into the memory - completely freeing the
CPU of this task. While this approach places an additional burden on the device designer, it greatly simplifies
the task of the system designer by eliminating the design
problems associtated with refresh and timing. This permits a very simple interface to the CPU and yet provides
guaranteed refresh, optimized timing, and minimal
hardware support requirements.
A microprocessor integrates all the components of a central processing unit into one device. An iRAM integrates
all the components of a dynamic RAM memory system
into a single device. This is unlike the pseudostatic or
quasi-static RAM devices which only incorporate a portion of the refresh circuitry onto the memory chip and
still require much control from the CPU. The integration used in the iRAM includes the refresh timer, refresh
address control and counter, address multiplexing, and
memory cycle arbitration as well as an 8-bit wide
memory array. Figure 3 is a pictorial representation of
this concept.
Figure 2. Separate Memory Control
1.3 Memory System Size and
Cost Constraints
Memory control incorporated within the CPU requires
CPU participation in all memory references - just to
preserve refresh. This includes DMA (direct memory access) which normally doesn't require or permit CPU intervention; Also, the CPU must run continuously.
Single stepping, hold operations, extended WAIT states
and the special block data move instructions of some
microprocessors must all be carefully avoided to
preserve refresh and maintain data integrity of the
memory system. While these constraints can be acommodated with careful design, the added overhead does
limit the full CPU processing capabilities and overall
system performance.
Integrated RAMs are primarily intended for use in
microprocessor memories usually less than or approximately equal to 64K bytes, while standard DRAMs with
a separate controller are more cost effective in larger
memories. The relative costs of systems designed with
various device family types are shown in Figure 4. A
range is shown for each alternative to represent the
change in cost over time. Thus, the 2Kx8 SRAM is a
good choice for very small memory systems of less than
8K bytes while DRAMs provide a clear advantage in the
region beyond 64K bytes. In the region between 8K and
Figure 3. iRAM/Microprocessor Comparison
3-42
Ap·132
ularly useful in development of microprocessor systems
in which the hardware design of the memory site may be
completed early in the design cycle before the RAMI
ROM mix has been specified. For example, a RAM
might be initially used to store microprocessor instruction code during the development and testing of the system software. This allows code to be run and debugged
at full system speed. Initial prototypes and small production runs can place EPROMs in the same sockets,
while full scale production may change to PROMs or
ROMs. The universal site flexibility also allows an easy
upgrade path to next generation (higher density) devices.
64K, however, standard DRAMs are usualy not as cost
effective because of the overhead involved in the design
and cost of the hardware for the controller. Based on
these comparisons, iRAMs have a clear advantage for
anything other than very small or very large memory
systems.
2K
4K
A key feature of the universal memory site is the two-line
bus control with separate CE and OE to prevent bus contention in a system. This convention offers a distinct
advantage over devices with only one-line control.
(Eliminating the effects of bus contention is extremely
important and not always easy due to its subleties.
Generally, the current and voltage spiking on the power
supply rails presents the major problem because this
type of noise can lead to a whole host of problems including invalid data, false triggering, race conditions,
and reflections, to name a few.)
8K
16K
64K
SYSTEM ~AM BLOCK SIZE (BYTES)
Figure 4. System Cost Graph
1.4 Byte·wide Universal Memory Site
1.4.1 ONE·L1NE CONTROL
The byte-wide universal memory site concept allows a
system designer to create one or more memory sites that
can accommodate several types of x8 memories, including RAMs, ROMs, EPROMs, and E2PROMs. The
universal site is depicted in Figure 5. Though based on a
28-pin site, the universal site also supports 24-pin
devices. For this site to be truly universal, it should cont\lin provisions for memory densities that have not yet
been developed.
With one-line control devices (Figure 7), bus contention
OCcurs when two devices simultaneously occupy a bus
(when CE of one device goes inactive simultaneously
with another devices' CE going active). This is the usual
situation when chip selects are generated from a
decoder. The contention occurs because it takes more
time for the output of the deselected device to turn off
(switch to high impedence) than the short output buffer
turn-on time of the selected device. Because the data
lines are wire-ORed to a common data bus, any data bits
of opposite polarity will cause bus contention (Figure 8).
Figure 6 shows various memory classes and how they
conform to the universal site. The universal site is partic-
28~ycc
SEE TABLE ~ 1
27QWE
26 ~ ~EE TABLE
25 As
24EA,
A1'12
:: ~ !
A,
A~ ~
5
6
A~ ~
7
23e~11
22Qoe
:: [:
21~~o
2oE.CE
19QIIO
I~& ~ :~
:~~::g
:;g i:~
16E"O
15pl/O
GND [14
,
PIN FUNCTIONS
PIN
FUNCTION
SYSTEM HIGH VOLTAGE, TYPICALLY V"
OR REFRESH FOR INTEGRATED RAMS
26 Vee FOR 24 PIN DEVICES,
1
A13 FOR 128K EPROMS
'M'
Figure 5. Byte·Wide Universal Memory Site
3·43
Ap·132
EPROM
A,
Vee
A,
A"
A,
Vee
Vpp
Vee
Vee
PGM
PGM
NC
A13
Vee
A"
A,
A"
A13
A,
A.
A,
As
A.
As
As
Vpp
As
As
As
A.
As
A.
A.
A"
A"
A"
A"
DE
A,
OEIVpp
DE
DE
A.
A,
A"
A,
A"
CE
CE
A,
CE
1107
1107
1107
1I0a
Ao
1100
1105
1/0 1
1/°5
"°4
1/0 2
1/0 4
A.
A,
A,
A"
A,
A,
CE
A,
CE
Ao
1100
110 1
1/07
1106
Ao
1100
1101
1105
1/0 1
1105
1/0 2
1/0 4
1102
GND
110 4
1103
GND
2K
X
A"
A"
A,
liDs
1/06
110 1
EPROM
110 1
110 3
1/0 3
1/03
4K)( 8
EPROM
8
1105
1/0 4
8K)( 8
EPROM
A.
DE
1/06
110 3
GND
16K )(8
32K)( 8
EPROM
EPROM
STATIC RAM
E'PROM
A.
iRAM
NC
Vee
RDY
WE
Vee
Vee
WE
A,
Vee
A,
Vee
NC
WE
NC
,A,
A.
A.
A.
A.
A.
A.
As
A.
Vpp
As
A.
A,
NC
As
As
As
As
WE
DE
A"
A"
A"
DE
A.
A,
DE
DE
DE
A,
A"
A,
A"
A,
CE
A,
CE
Ao
1/07
Ao
1100
1106
1/0 1
1/05
1100
110 1
A"
A"
CE
CE
1/0 7
1107
1107
I/0a
1106
1106
1105
1105
A"
CE
1106
110 1
1105
A,
1'°1
1105
110 2
1/0 4
1/0 2
110 4
1/0 4
1/04
110 4
GND
110 3
GND
1/0 3
110 3
110 3
1/0 3
8K)( 8
SRAM
2K)( 8
2K)( 8
E2PROM
STATIC RAM
8K )(8
8K )(8
IRAM
IRAM
FigureS. Intel's Line of Universal Products
_TACC_
ADDRESSES
I\.
TDECODE
!-TACC_
ADDRESS 1
TeE---+-
TDECODEi-
V
COMMON
DATA BUS
OUTPUTS 1
ACTIVE
DATA 1 VALID
OUTPUTS 1
DESELECTING
OUTPUTS 2
ACTIVE
XXXXX
DATA 2 VALID
BUS
CONTENTION _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~c...:.~~~~"'-l..------
l-o~~~~~P-I
Figure 7. One·line Control
3-44
inter
AP·132
any given processor. All devices inserted in the path, demultiplexers, transceivers, decoders, etc., must be compensated for by a higher speed memory.
Vee
ON
2 DEVICE DESCRIPTION
OFF
2.1 Overview
f-
ON
OFF
DEVICE 2
DEVICE 1
GND
TO
DATA BUS
GND
Figure 8. Bus Contention
1.4.2 TWO·LlNE CONTROL
Similar to one-line control, two-line control logic allows
the CE of one device to go inactive simultaneously with
another going active. However, the timing diagram in
Figure 9 shows that no bus contention occurs because
the OE of the selected device is not enabled until the outputs of the deselected device have switched off the bus.
The use of an independent output enable is the best way ,
to eliminate bus contention in the system. The use of
non-integrated output buffers cannot achieve the same
result; they can only confine bus contention to a memory card or memory section of it large card. In addition,
as processor speeds increase, greater demands are placed
on memory performance and the use of external nonintegrated output buffers places still more constraints on
memory system performance. In thi~ context, the time
between addresses out and data in is a fixed interval for
The 2186 and 2187 iRAMs are 5-volt only, dynamic
RAM 8K x 8 systems integrated on a single chip (Figure
10). The memory devices have been designed for easy
use with microcontrollers, multiplexed addressldata bus
microprocessors, and processors with separate address
and data paths. These memories are referred to as integrated RAMs or "iRAMs" because they contain refresh
timing and control logic. The 2186/87 iRAMs include
the following major features:
• Easy to use on-chip self-refresh, including:
- Internal refresh timer
- Refresh address counter
- High speed arbiter (2186 only)
- Refresh address multiplexer
- Complete internal timing control
• External refresh control option (2187 only)
• Microprocessor handshake signal (2186 only)
• Outputs drive two low power Schottky TTL
loads and 100 pF
The 2186/87 iRAMs are fabricated using an N-channel
double layer polysilicon gate process with depletion
loads. The fGur-quadrant memory array is built with
conventional one transistor DRAM cells, polysilicon
word lines and folded metal bit lines. Each of the four
quadrants contains 128 rows and columns. In addition,
four redundant columns and four redundant rows are
provided. Two pairs of 1/0 lines from each of the quad-
ADDRESSES
COMMON
oeiiilii
DATA BUS - - -_ _ _ _ _ _
~
\.'---NO OVERLAP
Figure 9. Two·line Control
'3·45
AP·132
rants provide a total of eight bits to the data bus. An active restore circuit boosts the bit lines back to a full Vee
level after every read or refresh cycle. Boosted word
lines and column select lines are used to write a full Vee
level into the memory cells. Wide internal operating
margins provide a high degree of reliability.
Intel's byte-wide universal memory site (Section 1.4).
Pin 1 (labeled "CNTRL") is the only external difference
between the 2186 and 2187. On the 2186, Pin 1 is a ROY
output - a signal to the system indicating memory
status. Pin 1 on the 2187 is a "refresh" strobe (REFEN),
an input signal for external refresh requests.
2.2 Device Pinout
Pins 2 thru 10,21, and 23 thru 25 are the 12 address inputs required to select each of the 8192 bytes. Pins 11
through 13 and 15 through 19 are the eight bits ofthe bidirectional data bus.
The pinout of the 2186 and 2187 is shown in Figure 11.
The industry standard 28-pin package conforms to
Figure 10. 2186 Die Photo
3·4E?
intJ
Ap·132
Pin 27 is the write pulse input strobe (WE) for data store
during Write cycles. Pin 20 is Chip Enable (CE), which
latches addresses and begins the internal memory cycle.
Pin 22 is Output Enable (OE), normally connected to a
CPU REAO (RO) line. OE enables the iRAM output
buffers during a Read cycle.
capability as it has been designed for use in synchronous
applications.
Pin 1 on the 2186 is the ROY output which serves as the
handshake signal (required in asynchronous systems)
and is usually bussed to the ROY input circuit of the processor. The ROY output is an open drain device, requiring a 510 ohm pull-up resistor which allows "wire-OR"
connections of other device ROY outputs without the
need for extra gates.
The 2187 receives external refresh requests via Pin 1
(REFEN). This input must be strobed 128 times within 2
milliseconds to perserve refresh in the dynamic RAM array. The 2187 iRAM is designed for use in synchronous
systems where the user wants control of the refresh
cycles. Hence, the designer must provide refresh requests to the iRAM. The 2187 has neither a ROY signal
nor any access cycle deferment and because it has no
built-in arbitration capabilities, the user must also
guarantee that access cycles are not requested during
refresh cycles.
Figure 11. 2186187 Pinout
Refresh addresses are generated internally in both
devices by an onboard refresh address counter. In addition, both devices have an internal refresh timer which,
for the 2187, pecomes active in a power-down mode.
2.3 Internal Description
2.3.1 ASYNCHRONOUS AND SYNCHRONOUS
REFRESH
2.3.2 FUNCTIONAL BLOCK DIAGRAM
The 2186 iRAM contains automatic internal refresh circuitry making it an ideal choice for asynchronous applications. The 2187 does not have the internal arbitration
Figure 12 shows a functional block diagram
iRAM.
REFRESH
REQUEST
SEQUENCER
AND
CE>-A~C-C~ES~S~R~E~Q~UE~S-T---'------~r-------~~
ARBITER
ACCESS
COMMAND
OE>-------~----------~
WE>-------------------~
• ROY OUTPUT ONLY ON 2186
R'EF'EN INPUT ONLY ON 2187
Figure 12. iRAM Block Diagram
3-47
BUSY
ROY *
0
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Ap·132
2.3.2.1 Refresh Timer
3 DEVICE DESCRIPTION
The refresh timer requests refresh cycles as required.
The refresh timer has been designed to track with temperature and process variations. The design optimizes
the rate at which refreshes occur while still guaranteeing
data integrity.
All timing signals used throughout this document are
denoted by various alpha character strings to indicate
certain basic conditions or parameters. Understanding
signal name derivation will enable the reader to arrive at
a correct interpretation of any signal name encountered.
Figure 13 illustrates the meaning of various letters used
in a signal name.
2.3.2.2 Sequencer and Arbiter Circuits
The sequencer and arbiter circuits accept refresh requests
from the refresh timer and memory cycle requests from
the CE input. The internal refresh command and the external memory accesses are asynchronous and either
may occur at any time with respect to the other. If one
does occur while the other is in progress, the request is
queued and the cycle performed after the existing cycle
has'completed. If a refresh cycle is already in progress at
the time an access request occurs, the RDY signal on pin
1 is pulled to VOL informing the system that the access
cycle is being deferred. In this instance, the normal cycle
will be delayed until after the refresh cycle has been completed. RDY will remain low until shortly before valid
data becomes available, after which the cycle is completed in a normal manner. The internal high speed arbiter resolves any conflict wherein an internal refresh
command and an external access occur simultaneously.
This circuit also generates the RDY handshake signal in
the 2186. The sequencer/arbiter circuit also decides
which type of memory cycle is to occur and controls the
operation.
ll. r
SIGNAL TERMINOLOGY
CONDITION
H - HIGH
L _ LOW
V - VALID
X -INVALID
CYCLE TYPE (OPTIONAL)
R - REFRESH
F - FALSE
TELQXR
.\
L - - SIGNAL OF INTEREST
E - ENABLE (CHIP)
.
REFERENCE
E _ ENABLE (CHIP)
~= ~
,
G-DE
w- WE
~ ~~~:ESS
=
R-
READY (ROY)
A - ADDRESS
Q- DATA
R - READY (ROY)
Fjgure 'I 3. Timing Signal Terminology
Each control signal is given a one-letter designer; i.e.,
CE is represented by E, OE by G, etc. Each of these letters is followed by another letter describing the state of
the foregoing. In addition, a timing descriptor may have
a letter added to the end to describe a 'special case. For
example, TELGL is the time from CE low to OE low,
while TEHELF is the time from CE high to the next CE
low during a false memory cycle; TELQVR is the time
from CE low to data valid for a not ready condition.
2.3.2.3 Address Buffers and Refresh Address
Counter
External addresses Ao-A 12 are directed to internal row
and column address buffers to generate internal byte addresses. Refresh addresses are generated by an internal
refresh address counter and are multiplexed internally
with the external row addresses.
The 2186 and 2187 are edge-triggered devices that recognize a timing edge as a signal to start an operation.
Because of this, CE must be allowed to make only one
transition per cycle, otherwise the device cycle time
(TELEL) will be violated. The 2186 and 2187 latch all
external addresses on the leading edge of CEo Data is
latched into the device on the leading edge of WE as opposed to the trailing edge write requirement which is
common among static RAMs.
2.3.2.4 Data Buffers
Controlled by signals from the read/write data control
circuit, the three-state bidirectional data buffers receive
or transmit eight data bits.
2.3.2.5 ,Read, Write Data Control
The 2186 provides· four major types of cycles: read,
write, false memory, and refresh.
The read/write data control circuit controls and directs
the flow of data between the 8K x 8 DRAM memory array and the data buffers.
Two major modes of operation exist for both read and
write cycles; CE pulsed mode and CE long mode. For
pulsed mode CE operation, the low CE time (TELEH)
must be less than or equal to TELGL(TELWL)max +
TGLEH(TWLEH)min, while long CE mode requires a
longer CEo (For more detailed timing information, consult the 2186 and 2187 data sheets.)
2.3.2.6 Cycle Terminator and Precharge
The cycle terminator and precharge circuits ensure proper
termination of all memory cycles and precharge the dyn'lmic circuitry in preparation for the next cycle.
3·48
AP·132
3.1 Read Cycle
will become valid and remain so for as long as OE is active, independent of CEo
A read cycle (Figure 14) is initiated by both CE and OE
going low during the same cycle. Depending on the low
time of CE, either a pulsed or long CE mode will occur.
Refresh cycle is in progress
If a refresh cycle is in progress at the time CE goes low,
the read cycle will be delayed (deferred read cycle) until
after the refresh cycle has completed. In this event, the
2186 will respond very quickly with a RDY low output
(TELRL). After the refresh cycle is completed, the read
cycle wiil commence and data will be available at a given
time after RDY returns high (TRHQV). As was the case
with the non-deferred read cycle, TELGL must be met
or an FMC will occur.
1----TElEl-----t
3.1.2 LONG CE MODE READ
OE
WE --~-~+--+--------~~-----
For long CE, a read cycle mode is initiated on the falling
edge of CEo Similarly to pulsed mode CE, both deferred
and non-deferred write cycles may occur where a deferred cycle causes RDY to be pulled low.
ADDRESS _ _ _
-J~_---I
110
In the long CE mode of operation, CE must be held low
for a given period of time after BE goes low (TGLEH).
Violation of this specification will cause an FMC to occur. At a given time after OE goes low, valid data will
become and remain available throughout the duration
of BE's active period, independent of CEo
--------t--::=:-:t=~~=j
READ
Note that deferred access cycles are not allowed for the
2187.
OE
----+--i
WE
---+---+-------,---------+---
RDY
110
3.2 Write Cycle
--+--.
A write cycle (Figure 15) occurs when both CE and WE
go low during the same cycle. As is the case for the read
cycle, either a pulsed or a long CE mode can occur.
--t-----------(
3.2.1 PULSED MODE
CE WRITE
In the pulsed mode, a CE write cycle is initiated on the
falling edge of CEo At this time, a refresh cycle mayor
may not be in progress. '
DEFERRED READ
For pulsed mode, a CE read cycle is initiated on the falling edge of CE at which time either a refresh is or is not
in progress.
Refresh cycle not in progress
With a refresh cycle not in progress, the memory cycle
can immediately commence (non7deferred write cycle).
After the falling edge of CE, WE must go low within a
specified period of time. If this latter condition is not
met, a false memory cycle (FMC) will occur (see Section
3.3). On the falling edge of WE, data is latched into the
device. \
Refresh cycle not in progress
With a refresh cycle not in progress, the memory cycle
can immediately commence (non-deferred read cycle).
After the falling edge of CE, OE must go low within a
specified period of time (TELGL). If this latter condition is not met, a false memory cycle (FMC) will occur
(see Section 3.3). At some point after OE goes low, data
If a refresh cycle i~ i~ progress at the time CE goes low,
the write cycle will be delayed (defem~d write cycle) until
after the refresh cycle has completed. In this event, RDY
is brought low and held there until the refresh cycle has
completed. Note that data is still latched into the 2186 on
the falling edge of WE.
Figure 14. Read Cycle Timing
3.1.1 PULSED MODE
CE READ
Refresh cycle is in progress
3-49
intJ
AP·132
Note that the CE high time (TEHELF) required after an
FMC is somewhat longer than the corresponding period
required for a read or write cycle (TEHEL).
I----TELEL----+i
As is the case with a read or write cycle, FMC cycles can
be deferred. RDY response time (TELRL) and recovery
time (TRHEL) are the same as for the read and write
cycles.
CE
~ ----4+-----4r----~~-
WE
ADDRESS
TAVErl
- I
<
'--
l-----.J
rr
mAX
~
~
CE
TDVWL -+j'ilt:;±--T-W-LD-X---
oe-----+r-------------
~f--------
1/0
<
WRITE
\+----TELELR -..,.--~
ADDRESS
~-~r-~H----------+---
CE
WE
--4--l
oe----f----+------If----
READY --......;.--""\
WE----f----:--+---------_ TELRL 1--0+--/
..... TWLDX
I/O~
ROY
DEFERRED WRITE
-----f-""\
DEFERRED FMC
Figure 15. Write Cycle Timing
3.2.2 LONG
Figure 16. False Memory Cycle Timing
CE MODE WRITE
3.4 Refresh Modes
A long mode CE write cycle is initiated on the falling
edge of CE. As is the case for a pulsed mode CE, both
deferred and non-deferred write cycles may occur with
RDY being pulled low in the deferred cycle.
Both the 2186 and 2187 can be refreshed by reading or
writing all 128 rows (Ao through A 6) within a two millisecond period. Several specific modes of refresh operation exist for each part as outlined below.
For the long CE mode of operation, CE must be held
low for a given period of time after WE goes low
(TWLEH). Violation of this specification will cause an
FMC to occur. On the falling edge of WE, data is latched
into the device.
3.4.1 2186 AUTOMATIC INTERNAL REFRESH
Refresh is totally automatic and requires no external
control. In addition, the refresh address is computed internally and does not ha:-----------------~------------~
Figure 18. Interface Circuit No.1
3-52
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A simple, one-gate alternative to the preceding example
along with the appropriate timings is shown in Figure
23. This cross-coupled NAND arrangement operates in
much the same way as the CE generation circuit presented earlier, acting to synchronize the WR pulse with
the clock. This circuit will provide for both leading and
trailing edge writes.
Either circuit will provide all of the interface needed for
a 5 MHz 8086 or 8088 max mode system, because
MWTC can be used to provide both leading and trailing
edge writes. For a min mode system, the circuit in Figure
21 can be used to provide a leading edge write, and the
circuit in Figure 22 can be used to provide both a leading
and trailing edge write.
WR"----;
5 SPECIFIC APPLICATION EXAMPLES
ol----"WE
This section describes some typical memory interface
designs using three types of CPUs: an 8-bit microcontroller, an 8-bit microprocessor, and a I6-bit microprocessor. Design examples are included for both the 2186
and the 2187.
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5.1 8·Bit Microcontroller
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Figure 24 shows a two-chip microcomputer system using
the 875118051. This system features 4K bytes of
EPROM/PROM and 8K bytes of data storage using the
2186 iRAM. Interface to the multiplexed bus is simplified because the 2186 latches addresses from its external
bus on the falling edge of CE, eliminating the need for
latches. In this configuration, the ALE output from the
microcontroller is gated with P2.7, and used to generate
CE of the 2186. The gating of ALE with P2.7 is important for the following reasons: when the 8051 does any
type of memory operation, it outputs ALE onto its external bus. This includes internal program memory
fetches, in which the ALE cycle time (Figure 25) is only
half of what it would be for an external data memory
fetch. During these "short" cycles, ALE must be inhibited from generating a CE to the 2186, or else the
2186 cycle time with WAIT specification (TELELR)
would be violated. To carry this out, P2.7 is initially set
to a "1" which is done automatically upon RESET. This
"1" will be present on the output during all times except
external data memory fetches from addresses below
8000H, at which time P2.7 will go low, allowing ALE to
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DATA ------'--1,..---''------'--'+-(WRITE)" _ _ _ _ _--'"---,..,-_ _ _.,...,...-'-_ _
WE
--------I-i
Figure 22. leading and Trailing Edge Write
1_ ---1
200
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WE
Figure 23. Simplified Write Enable Circuitry
3-54
inter
AP·132
the 8051 are tied directly to the WE and OE inputs to the
iRAM. Data to be written is guaranteed to be valid
before the leading edge of WR for the 8051. This provides the leading edge write needed by the 2186/87.
provide a CE to the 2186. After completion of the external data memory fetch, P2.7 will revert to its preset
value of "I".
RDY
Although a RDY input does not exist for the 8051, a
2186 can still be used for data memory. At 8 MHz the
8051 does not require data back from the data memory
until 800 ns after the trailing edge of ALE. The 2186-25
specifies worst case access time at 675 ns from the trailing edge of CE, which in this system, corresponds to
ALE. Even if the 2186 is just starting a refresh' cycle
when the 8051 requests an access, it will still have time to
complete the refresh cycle, and access valid data by the
time the 8051 requires it. Note that during RESET, CE is
kept high to satisfy the power-up requirements of the
2186.
N.C.
8051
8751
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WE
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The access time required of program memory is somewhat faster than that needed for data memory. Because
of this, the 2186 cannot be used in an asynchronous refresh mode as program memory for a full speed system.
However, operation could be guaranteed if the system
clock were slowed down.
Vee
Figure 24. Asynchronous 8051 System
The synchronous 2187 iRAM can be used as program
storage for an 8051 running at 10 MHz by utilizing a
method known as clock stretching. The circuitry, as
shown in Figure 26, allows the 8051 clock to be stopped
in a high state whenever the 2187 requires a refresh cycle.
This stretched period is performed at the beginning of a
cycle while ALE is high.
Note that a pull-up resistor is used to ensure that P2.7
will return to a "1" before the next trailing edge of
ALE. Timings on the ALE are specified so that all CErelated parameters on the 2186 are guaranteed, including address setup (TAVEL) and hold times (TELAX),
and CE high time (TEHEL). The RD and WR outputs of
1--220-••f-o.I---------1500----;:===::::.~1
ALE -----'I
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2
--------~~--------------------------~-------8 MHz
805112186
Figure 25. Asynchronous 8051 System Timing
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plished by allowing either PSEN or Ri5 to enable the
2187 for a READ. Thus, it is possible to create a intermixed data and instruction field.
Operation of the clock stretching circuitry is straightforward'(Figure 27). Under normal operation, U2 acts as a
frequency divider for the clock. U3 and U4 count clock
pulses, and when a full count occurs, a refresh cycle request is issued (RFRQ). This request sets UlA. On the
next high transition of ALE, this request is clocked into
UIB, where it causes REFEN to become active. A
refresh cycle within the 2187 begins at this time.
5.2 8088/2186 8-Bit Microprocessor
Design Example
An example of an 808812186 iRAM design is shown in
Figure 28. The 8088 is connected in a straightforward
manner to the 2186 iRAM array. The low order addresses
are latched from the multiplexed address/data bus of the
CPU by ALE and are connected to the array. The CPU
RD provides
for the iRAMs While the MWTC from
the 8288 bus controller serves as the WE for the memory. A stable chip select is generated by circuitry enclosed within the dashed lines. This circuit runs without
WAIT states at 5 MHz using the 250 ns 2186-25.
At the same time that REFEN becomes active, U5 is released from a clear state to start counting clocks, acting
as an interval timer to allow time for the refresh cycle to
occur.
ern
On the first high transition of the system clock after U 1B
is set, U2 will be preset, maintaining the already high
state of the clock. This high level is maintained until U5
has counted 10 clock cycles, at which point it acts to
reset the clock stretching circuitry and allow the clock to
return to a toggling condition.
5.3 8086/2186 16·Bit Microprocessor
Design Example
The clock stretching circuitry used in this system could be
utilized to a greater extent than just handling iRAM
refresh cycles. For example, it might be useful for some
type of DMA operation, or for use with slow peripherals.
Also note that no address latches are needed with this
system. To satisfy the power-up requirements of the 2187,
REFEN must be held low for 100 IIsec after Vee is within
its specified vaiue. This is accomplished by driving REFEN
low during RESET.
The 5 MHz min mode system shown in Figures 29 and 30
depicts a typical interface of 2186 iRAMs with an 8086
16-bit microprocessor. With this arrangement, up to
128K words can be addressed.
To guarantee a stable CE, the first interface circuit described in Section 4 is used. The output of this dual J-K
flip-flop arrangement is used to enable the 8205 CE decoder.
In a typical operation, a down-loader program would
reside onboard the 8051 in PROM. This program would
write program instructions into data memory. These instructions could then be "fetched" out of the same
memory which would now be acting as program storage.
This overlaying of program and data store is accom-
T4
T5
A False Memory Cycle (FMC) is generated by this circuit
during byte write cycles because both devices in the
16-bit word receive CE, but only one device (or, byte)
receives a WE. The other device enters an FMC without
any consequences at the system level.
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-
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(WRITE)
_92-/
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1-
10
I
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-
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191--
WE - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ,
r---
~------------~I
Figure 30. 8086 Min Mode System Timing
If an 8086 max mode system is to be used, the WE delay
circuitry is not needed. In this case, the normal WR provided by the 8288 bus controller meets the leading edge
write requirement. A diagram is shown in Figure 31.
Note that a D-type flip-flop is used to latch 52. This is
important, because during certain 8086 operations, such
as execution of a software HALT, 52 is not guaranteed
to remain valid up to the trailing edge of ALE. To overcome this, S2 is latched on the leading edge of ALE, as
done here.
video priority table. This programmable table permits
up to 16 colors (out of 256 possible) per display frame. It
also assigns priority. For example, a red disk crosses a
green on the display. Does the red cross in front of the
green disc, the green in front of the red, or does the area
of the overlap become yellow? The priority encoding
assigns answers to these questions.
By industry standards, this 256 x 256 pixel display has
low-end to medium display resolution. For those unfamiliar with the capabilities at this level, visit a local video
game parlor and examine some of the dazzling displays
on the state-of-the-art video games such as Williams
Electronics Defender. Advanced machines such as this
are only beginning to approach this display density.
5.4 Graphics Example
All of the applications examples presented thus far are
non-specific; that is, all demonstrate how to connect the
iRAMs to various microprocessors in the most general
terms without regard to the total application. The design
that follows shows the 218612187 iRAM in a specific application: a color graphics display memory.
The iRAM used in this example is the synchronous 2187.
Due to the sequential addressing scheme of video displays, video memory typically requires no additional circuitry for refresh. The 2187 is no exception, and in this
design the REFEN pin is tied high. The sequential scanning by the video address generator automatically refreshes the internal array of the iRAM.
In this example (Figure 32), the color display resolution
is 65,536 (256 x 256 pixels) x 4 bits. The four bits select
the color of the pixel by addressing a color lookup and
3·60
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inter
Ap·132
and vertical blanking (retrace) periods permits the real
time screen update required in an animated display.
Figure 32 is a simplified diagram. A detailed analysis of
the circuit and timing will not be discussed. Briefly, the
circuit functions as follows:
CPU addresses A14 and A1s are decoded to generate one
of four iRAM chip selects so that the (assumed 8-bit)
CPU can read or write information to the individual
memory planes (iRAMs). These chip selects are gated so
that all four iRAMs can be simultaneously enabled by
the Vcs signal from the video timing circuitry. A similar
circuit (not shown) would allow OE for the iRAMs to be
generated by either the CPU or the video timing generator. The iRAM addresses are generated by multiplexing
the CpU addresses with video timing addresses. The
32-bit output from the iRAMs is loaded into four 8-bit
shift registers and are serially shifted out as four bits of
video information used to address the color lookup
table. The four lines (Vidl-Vi~) are multiplexed with
CPU addresses AU-A3 to create the actual addresses of
the lookup table. Comprised of two 2148H RAMs, the
eight data lines of the lookup table are directed to three
digital-to-analog converters for generating 16 of256 different display colors.
5.5 External Refresh Systems
5.5.1 BURST REFRESH
Figure 33 shows an example of a burst mode refresh controller. Timings for this system are shown in Figure 34.
To ensure data integrity for a 2187, REFEN must be
strobed at least 128 times in each 2 ms period. After each
high-to-low transition of REFEN, one cycle time must
be allowed before REFEN (or CE) again becomes active.
The system shown in Figure 33 accomplishes refresh by
interrupting the processor once each 1.63 ms (200 ns
clock period divided by 8192). Upon acknowledgment
of this interrupt, TEST is driven high, allowing REFEN
to be generated once every three clock cycles. 'i'EST is
also routed back to the TEST pin of the 8086 to indicate
that a burst is in progress. The 8086 samples the state of
the TEST pin and loops in an idle state until the TEST
goes low. This is accomplished using the WAIT instruction.
Due to the byte-wide organization of the iRAMs, there is
plenty of time between video read cycles to allow CPU
access to the memory. With a pixel rate of 6 MHz, the
byte-wide iRAM has a video read rate of 6/8 MHz or
once every 1.33 microseconds. Only 350 ns of this time is
needed for a video read cycle. The balance of the time
(approximately Il'sec) can be used by the CPU to access
the memory. This interieavihg of CPU cycles with video
timing cycles, combined with allowing the CPU unrestricted access to the memory during both horizontal
TVI'Q 4-bit counters are used to count the REFEN pulses.
After 128 pulses, the count goes high. On the next rising
edge of the system clock, TEST is reset to a zero, blo~k
ing any further REFEN pulses, clearing the counters,
and signaling to the processor that the burst is complete.
, Note that one non-access cycle should be inserted after
TEST is set low to ensure that sufficient time has been
allowed for the last refresh cycle to complete.
15 Mhz
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Figure 33. Burst Refresh Circuit
3-63
AP·132
Figure 34. Burst Refresh Timing
nature of bank selection used (AO:Al decoding), more
than a couple of consecutive accesses to anyone bank
are highly unlikely.
5.5.2 SYNC REFRESH SYSTEM
The system in Figure 35 represents one way in which synchronous refresh could be employed using the 2187. In
this configuration, memory is divided into four banks,
selected via the two least significant addresses. To ensure
data integrity, each of the four banks must receive 128
REFEN pulses every 2 ms. In this system if anyone bank
is accessed, each of the other three banks receives a refresh pulse. Minimum cycle time cannot quite be attained
because the cycle time for the refresh cycle is the same as
that for an access cycle, and the fact that a one-gate
delay exists between CE to one device and the REFEN to
the others. At least 16 ns must be added to the minimum
cycle time of 425 ns. This number is derived by taking
the propagation delay difference between a "fast"
74155 and a "slow" 74155, and adding the maximum
delay through a 74S11. This gives the CE to REFEN
delay time. This extra delay is not really critical in most
systems; the minimum cycle time for a 5 MHz 8086 is
800 ns.
.
One caution to note,. however, has to do with powerdown refresh. If Ri'lFEN is kept low for longer than one
timer period, the timer will begin to time out. In this
event, a period of time (RFHEL) must be allowed before
CE can go low again after REFEN returns high. This is
to ensure, that if a timer initiated refresh cycle started
just as REFEN returned to a high state, it will have time
to complete before an access cycle is started.
6 SYSTEM CONCEPTS
6.1 System Reliability
New applications for microprocessor systems appear
almost every day. They appear in microwave ovens, automobiles, word processors, home computers, video
games, vending machines, lighting controls, medical
equipment, etc. The list goes on and on. Failures on
these systems cover equally broad ranges: acute annoyance (such as losing your last quarter to the coffee machine), financial loss (a double debit is added to your
bank statement by an electric teller machine), and life
threatening system failures (the electronic carburator
control on your car fails, opening the throttle wide
open).
With the circuitry described, data integrity would be
jeopardized ifone bank were accessed consecutively too
many times, since the accessed bank would receive no
REFEN pulses. Assu~ing a 500 ns cycle time, one bank
would have to be accessed at least 30 consecutive times
to jeopardize data. This is the worst case. In actual operatJon, consecutive accesses to one bank could be many
more than this, as long as operation during any 2 ms period provides 128 REF'EN pulses to all banks. Due to the
3·64
Ap·132
In many applications, reliability is important enough to
be designed into the system. The computer memory system is one of the system components for which reliability is important. Also it is one of the few system elements
which can be easily designed to enhance its reliability.
Since memory system reliability is inversely proportional
to the number of devices in the system, a system of a
given size should be designed with as few components as
possible. For example, a 32K byte system could be designed with sixteen 16K 2118 DRAMs. The system
MTBF (Mean Time Between Failures - the "up" time
of a system) could be calculated from the combined device soft and hard error rates (See Intel Application Note
AP-73 "Eee #2 Memory System Reliability With
Eee" for a model to calculate system MTBF's). The
point is that, whatever the calculated system MTBF, the
2186 will be several times more reliable in a system due
to the lower device count.
A few example calculations are tabulated in Table 1.
Essentially what is shown is what the maximum acceptable
device soft error rate is for a specified system MTBF. For
example, if a design using 8K x 8 RAMs requires a
memory system MTBF for two years, and the system size
is 16K bytes, then the design allows a device with a soft
error rate of 3. I ll7o/IK-hrs. The 2186/87 soft error rate
goal is more than an order of magnitude better than that!
From the chart it can be seen that a 64K byte extra-reliable
memory system with a 10 year MTBF requires a device
with a soft error rate or O.IS%/IK-hrs. Clearly the
2186/87 family ofiRAMs is reliable over the entire spectrum of typical application memory sizes.
DUAL
2TO 4
74155
DECODER
ENABLE
Figure 35. Synchronous Refresh Scheme
Table 1. 2186/87 SER Data
No. of
Syst.
Rows
No.
of
Dev.'
Maximum Allowable SER (%/K·Hrs.)
Sys.
Size
Eft.
Cycle
Time"
1 Yr. MTBF
(8800 Hrs.)
2Yrs. MTBF
(17600 Hrs.)
5 Yrs. MTBF
(44000 Hrs.)
10Yrs. MTBF
(88000 Hrs.)
Ll2
1
1
8K
7.00
11.34
5.66
2.25
2
2
16K
9.66
6.23
3.10
1.22
.60
3
3
24K
11.06
4.29
2.13
.84
.41
4
4
32K
11.93
3.27
1.62
.64
.31
8
8
64K
11.52
1.67
.82
.31
.15
* All times in microseconds
System has a 7~sec device cycle time.
Hard error rate = O.02"7o/1K-Hrs.
3-65
AP·132
6.2 Circuit Design Considerations
Skew is defined as simply the difference between the
maximum and minimum propagation delays through
devices in a parallel path. Figure 36 is a simple example.
Best case propagation of signal A is 6 nanoseconds versus worst case delay of signal B which is 16 nanoseconds.
This condition equates to 10 nanoseconds of skew
(Figure 37) which adds directly to system access or cycle
time. The worst case number of 16 ns would be used for
timing analysis in this type of delay calculation;
however, often the best case is the most important. For
example, as in Figure 38, the skew of concern deals with
the best case arrival of a write pulse versus worst case ar~
rival of data to a memory device.
Integrating components into systems requires a keen
awareness of basic concepts on the part of the designer.
Techniques for designing optimal performance memory
systems have been thoroughly covered in other literature. Two useful documents that cover these procedures
are AP-74 "High Speed Memory System Design Using
the 2147H" and AP-133 entitled "Designing Memory
Systems for Microprocessors Using the Intel 2164A and
2118 Dynamic RAMs. "There are essentially three areas
of major concern in a memory system design:
• Timing delay calculations in the critical path
(worst case timing analysis)
• Memory circuit trace layout
• Power distribution and decoupling
SKEW-DIFFERENCE BETWEEN MAXIMUM AND
MINIMUM PROPAGATION DELAY THROUGH
DEVICES IN A PARALLEL PATH.
The following sections summarize these techniques as
they apply to the 2186 and 2187 iRAMs.
6.2.1 DELAY CALCULATIONS
SIGNAL
All memory designs require a timing analysis to ensure
proper operation and compatibility of the memory and
the processor. Timing skews, capacitive delays and
propagation delays all have to be accounted for in a ,
proper analysis. Propagation delay design rules for TTL
are furnished in the manufacturer's data book. The
maximum delay is the data book maximum and the
typical delay (usually useless for design) is the data book
typical. Intel has determined in work with TTL device
manufacturers that the minimum propagation delay is
Y2 the data book typical value.
Ons
SIGNAL "A"
SIGNAL "iii"
(DELAYED)
SIGNAL "8"
4ns
8ns
12"5
"A"---------"-...~------ ~~ ________
,DELAY MIN DELAY MAX -
DELAY MIN DELAY MAX -
2 ns
5 ns
2 ns
6 ns
16"5
20n6
*
PATH "A" DEVICES
OPERATING AT
MIN.
I
~+i-----------
PATH "8" DEVICES
OPERATING AT
MAX.
,I
~
1,'
I
,
~
~
SKEW:
SIGNAL "A" SIGNAL "B"
=
= MAX - MIN 16 ns - 6 ns
TO -= 10 ns ISKEWI
ADDS DIRECTLY TO SYSTEM ACCESS/CYCLE TIME
Figure 37. Skew Timing
3-66
2 ns
S ns
~
ns
5 ns
Figure 36. Skew
1;:=_________
6 ns (MIN)
"A"
"B"
~OElAYED
________
SIGNAL ,,~.
(DELAYED)
•
2 ns
6 ns
SIGNAl"B,,~SIGNAl
16 ns (MAX)---j,
SKEW
2 ns
5 ns
~~_ _ _ _ _ _ _ _ _ _ __
--!
SIGNAL
~DELAYED
AP·132
capacitance, use the following standard derating factors:
Schottky TTL =0.05 ns/pF
Low Power Schottky TTL=O.I ns/pF
Standard TTL=0.75 ns/pF
WE TO DATA SKEWS PROHIBIT USE OF COMMANDS
DIRECTLY FROM 8088 PROCESSOR
CASE 1 -
DATA NOT VALID AT WRITE
~VALID
WORST CASE DA: FROM 8088
BEST CASE CAS/WE FROM 8203
Add up all of the capacitance connected to a driver, including the circuit-printed trace capacitance of 2 pF per
inch, subtract out the manufacturer's capacitance drive
specification, (typically 15 pF) then multiply this capacitance by the derating factor for the driver. This net result
is the additional delay due to capacitance. The equation
is:
~_
+-_
_
r:tDS
CASE 2 BEST CASE
NOT ENOUGH TIME TO WRITE
CAS FJlOM 8203
WORST CASE COMMAND
FROM 8088 (MWTC) ,
Dc = (ECIO + ECPCB - CSPEclTD
where: Dc
ECIO
= delay due to capacitance
= sum of all input/output connections
attached to driver
ECPCB = 2 pF x number of inches of circuit
trace attached to driver
CSPEC = specified drive capacitance of driver
TD
= capacitive derating factor
Figure 38. Worst Cas~ Timing
Unbalanced capacitive loading on address or control
line drivers also contribute to skew. Capacitance contributes to risetime degradation on these signals. The unbalanced loading causes differing rise times as shown in
Figure 39. The different rise times reach a logic threshhold at different times, contributing to skew. In all of
these examples, skew contributes to'the overall delay,
and the goal of the designer is to minimize these skews.
A few simple rules will help to achieve this in 2186/87
memory system design:
• Select logic gates for minimum delay per function
• Place parallel paths in the same package (device to
device skew is much less within same package - 0.5
ns max for STTL)
• Balance the output loading of device drivers to
equalize capacitive delays.
6.2.2 TRACE LAYOUT
Address lines need to be kept as short and direct as possible. Route address lines in a comb-like fashion from a
central location. Routing control and address signals
together from a centralized board area will also
minimize skew.
Allow for proper termination of all address and control
lines because these circuit traces are actually transmissiOli lines. A series resistor close to the driver is the
recommended termination technique. Thirty-three ohms
is a good typical value, although actual values are usually determined empirically. Figure 40 shows P.C.B. artwork that embodies these rules as well as proper power
and ground gridding with decoupling as described in the
following section.
SCHOTTKY TTL CAPACATIVE LOADING EFFECTS
6.2.3 POWER SUPPLY DISTRIBUTION
AND DJ:C,OUPLING
TTL INPUT
LOAD
CAPACITANCE
10
20
Ground and power busses can contribute to excess noise
, and voltage drops if not properly structured. The power
and ground network do not appear as a pure low
resistance element but rather as a transmission line,
because the current transients created by the RAMs are
high frequency in nature.
Transient effects can be minimized by adding extra circuit board traces in parallel to reduce interconnection inductance. Extrapolation of this concept to its limits will
result in an infinite number of parallel traces, or an extremely wide low impedance trace, called a plane. Arranging power and ground voltages by plane provides
the best distribution; however, correct gridding can cost
effectively approximate the benefits of planar distribu-
30
Figure 39. Capacitive Loading Effects
As previously stated, capacitance contributes to signal
dsetime degradation. To determine the delay due to
3-67
Ap·132
tion by surrounding each device with a ring of power and
ground traces (Figure 40).
generation is significant and must be dealt with during
design.
Consider two aspects of the memory device that contribute to power system noise: the active/standby power
modes of the RAMs, and the drive requirements of the
data 110 buffers. In a typical microprocessor-based
system, address space is divided into blocks of RAM,
ROM/EPROM, and 110. When the microprocessor is
not accessing a given RAM, the RAM is usually deselected and in a power standby mode. When a previously
unselected RAM is selected, a large current surge is experienced. Because the connections supplying power to
the device will involve resistance and inductance, a
voltage variation will occur in association with the current surge in accordance with the equation:
V = Ri + Ldildt,
where V = instantaneous voltage,
L = inductance,
R = resistance,
= instantaneous current
and
Another factor that contributes to current surges are the
drive requirements of the memory devices data 110 buffers. Consider first an 110 buffer outputting a logic one.
To accomplish this, the buffer must supply a current to
charge the capacitance of the line that it's driving to a
logic one level. This operation places a higher current requirement than normal on the Vee bus. Conversely, if
the 110 buffer is outputting a logic zero, it must discharge all of the capacitance on the line to ground. This
produces a current surge to the ground bus, possibly
raising the local Vss potential above ground during the
transient.
The solution to this problem is to use a solid plane Vee
and ground bus on a P ;C. board or use a proper power
and ground grid combined with adequate decoupling.
Adequate decoupling is also important in circuit design
to minimize transient effects on the power supply
system. For best results with the 2186/87, decoupling
capacitors are placed on the memory array board at
every device location (Figure 40). High frequency 0.1 /tF
Because a RAM may be selected and deselected hundreds of thousands of times a second, the transient noise
Vee
GND
Figure 40. Example of Power and Ground Gridding
3·68
Ap·132
ceramic capacitors are the recommended type. Also included should be a large bulk decoupling capacitor in the
50 to loo,.F range, placed where power is supplied to the
memory system grid. In this arrangement, each memory
is effectively decoupled and the noise is minimized
because of the low impedance across the circuit board
traces.
of DRAM density, power consumption, and price
without the added cost of designing the refresh control
circuitry. The 2186 and 2187 are the premier members of
this new byte-wide product family, designed for flexible
operation in virtually any microprocessor memory
system. By comforming to Intel's universal memory site
concept, these iRAMs are compatible with a wide variety
of byte-wide memory devices including SRAMs,
EPROMs, and E2PROMs.
7 SUMMARY
In sum"mary, Intel provides another innovative memory
product, the 2186/87 iRAMs - basic building blocks
for microprocessor memory solutions.
Intel's iRAMs provide a new approach to memory
design that allows the system designer to take advantage
3·69
APPUCATION
NOTE
Ap·133
April 1982
© INTEL CORPORATION, 1982
Order Number: 210431-()01
3-70
PREFACE
This application note has been developed to provide the memory system designer
with a detailed description of microprocessor memory system design using Intel
Dynamic RAMs, the 16K 2118, 64K 2164A, and the 8203 Dynamic RAM Controller.
The 8086 bus interface to memory components is described and three major examples are presented and analyzed - ranging from simple to complex: the simple
solution, the 5 MHz No-WAIT State and the 10 MHz No-WAIT State systems. To
assist the designer, complete logic schematics, timing diagrams and system design
considerations are also included in this application note.
3-71
AP·133
Unfortunately, the simple cell has a drawback: the
capacitor is not a pure element and it has leakage. If left
alone, leakage current would cause the loss of data. The
solution is to refresh the charge periodically. A refresh'
cycle reads the data before it degrades too far aJ;ld then
rewrites the data back into the cell. RAM organization is
tailored to aid the refresh function. AIl an example, the
Intel® 2164A 64K RAM is organized internally as four
16K RAM arrays, each comprised of 128 rows by 128
columns. Consequently the row address accesses 128
columns in each of the four quadrants. However, let's
concern ourselves with only one quadrant. Prior to
selection, the bit sense line was charged to a high
voltage. Via selection of the word line (row addresses)
128 bits are transferred onto their respective bit lines.
Electrons will migrate from the cell onto the bit line
destroying the stored charge. Each one of the 128 bit
lines has a separate sense amplifier associated with it.
Charge on the bit line is sensed, amplified and returned
to the cell. Each time the RAM clocks in a row address,
one row of the memory is refreshed. Sequencing through
all the row addresses within 2 ms will keep the memory
refreshed.
1 INTRODUCTION
Matching the correct RAM to microprocessor application requirements is fundamental to effective product
design. A good understanding of the advantages and disadvantages of each technological approach and device
type will enable a memory system designer to best.
choose the product that provides the optimal benefit for
his particular design objective.
Two basic types of random access memories (RAMs)
have existed since the inception of MOS memories: static
RAMs (SRAMs) and dynamic RAMs (DRAMs). Where
highest performance and simplest system design is
desired, the static RAM can provide the optimum solution for smaller memory systems. However, the dynamic
RAM holds a commanding position where large
amounts of memory and the lowest cost per bit are the
major criteria.'
The major attributes of dynamic RAMs are low power
and low cost - a direct result of the simplicity of the
storage cell. This is achieved through the use of a single
transistor and a capacitor to store a single data bit
(Figure 1).
In spite of the advantages of minimal cost per bit and
low power, the dynamic RAM has often been shunned in
microprocessor systems. Up until now, dynamic RAMs
have required a good deal of complicated circuitry to
support the refresh requirements, and associated timing
and interfacing needs. Circuitry for arbitration of
simultaneous data and refresh requests, for example,
has posed significant design problems. These requirements all add to the component count and system
overhead costs, both in design and implementation.
BIT SENS;,;;E;..;L;;;,IN;,;;E_-T_ __
ROW, SELECT
TRANSISTOR
(WORD LINE)
-!
~
l
.
STORAGE·
CAPACITOR
The development of the Intel family of dynamic RAM
controllers has brought a new level of design simplicity
to dynamic RAM memory systems. These new devices
include the solutions to the problems of arbitration, timing, and address multiplexing associated with dynamic
RAMs.
Figure 1. Dynamic RAM Memory Cell
The absence or presence of charge stored in the capacitor equates to a one or a zero respectively. The capacitor
is in series with the transistor eliminating the need for a
continuous current flow to store data. In addition, the
input buffers, the output driver and all the circuitry in
the RAM have been designed to operate in a sequentially
clocked mode, thus consuming power only when being
accessed. The net result is low, power consumption.
Also, a single transistor dynamic cell as compared to a
four or six-transistor cell of a static RAM, occupies less
die area. This results in more die per wafer.
This application note describes two basic memory
systems employing the use of the Intel® 2164A and 2118
dynamic RAMs in conjunction with the Intel® 8203 Dynamic RAM Controller and the Intel 2164A, 64K dynamic RAM with a hig~ speed TTL controller.
1.1 2118 16K RAM
Becaus~ the manufacturing cost of a wafer is fixed, more
'The Intel 2118 is a high performance 16,384 word by 1
bit dynamic RAM, fabricated on Intel's n-channel
HMOS technology. The Intel 2118 is packaged in the industry standard 16-pinDIP configuration, and only requires a single + 5V power supply. (with ± 100/0
tolerances) and ground for operation, i.e., VDD ( + 5V)
and Vss (GND). The substrate bias voltage, usually
die per wafer translate into lower cost. For example,
assume a wafer costs $250 to manufacture. Yielding 250
die per wafer means each die costs one aollar. But, if only
125 die are yielded, the cost per die is two dollars. The
rationale of the quest for smaller die size is obvious; the
simple dynamic memory cell fulfills this quest.
3·72
Ap·133
designated VBB, is internally produced by a back bias
generator. The single + 5V power supply and reduced
HMOS geometries result in lower power dissipation and
higher performance.
operate with a single + 5V power supply with ± 10117.
tolerences. Pin 1 is left as a no-connect (N/C) to allow
for future system upgrade to 256K devices. The use of a
single transistor cell and advanced dynamic RAM circuitry enables the 2164A to achieve high speed at low
power dissipation.
1.1.1 2118 DEVICE DESCRIPTION
The 2118 pin configuration and performance ratings are
shown in Figure 2. Note that pins 1 and 9 are N/C (noconnects). This allows for future expansion up to 256K
bits in the same device (package). For a rigorous device
description, refer to AP-75, "Application of the Intel
2118 16K Dynamic RAM."
1.2.1 2164A DEVICE DESCRIPTION
The 21MA is the next generation high density dynamic
RAM from the 2118 +5V, 16K RAM. The 2164A pin
configuration and performance ratings are shown in
Figure 3. For a detailed device description, refer to
AP-131, "Intel 2164A 64K Dynamic RAM Device Description. "
NIC
D,N
WE
3
Do
RAS
4
As
A3
A.
Vss
CAS
AD
A2
At
V DD
Access Time (ns)
Cycle Time (ns)
Operattng Current (mA)
Standby Current (mA)
As
A7
Access Time (ns)
Cycle Time (ns)
Operating Current (rnA)
Standby Current (rnA)
Figure 2. Intel® 2118 Pinout
Figure 3. Intel® 2164A I'inout
1.2.2 2118 ADDRESSING
Fourteen addresses are required to access each of the
16,384 data bits. This is accomplished by multiplexing
the addresses onto seven address input, pins. The two
7-bit address words are sequentially latched into the 2118
by the two TTL level clocks: Row Address Strobe (RAS)
and Column Address Strobe (CAS). Noncritical timing
requirements allow the use of the multiplexing technique
while maintaining high performance. For example, a
wide t RCD window (RAS to CAs delay) allows relaxation of the timing sequence for RAS, address change,
and CAS while still permitting a fast t RAC (Row Access
Time).
1.2.2 2164A ADDRESSING
Sixteen address lines are required to access each of the
65,536 data bits. This is accomplished by multiplexing
the 16-bit address words onto eight address input pins.
The two 8-bit address words are latched into the 2164A
by the two TTL level clocks: Row Address Strobe (RAS)
and Column Address Strobe (CAS). Noncritical timing
requirements allow the use of the multiplexing technique
while maintaining high performance.
Data is stored in a single transistor dynamic storage cell.
Refreshing is required for data retention and is accomplished automatically by performing a memory cycle
(read, write or refresh) on the 128 combinations of Ao
through A6 (row addresses) during a 2 ms period. Address input A7 is a "don't care" during refresh cycles.
Thus, designing a system for 256 cycle refresh at 4 ms in
a distributed mode automatically provides 128 cycle
refresh at 2 ms and a more universal system design.
Data is stored in a single transistor dynamic storage cell.
Refreshing is required for data retention and is accomplished automatically by performing a memory cycle (read, write or refresh) at all row addresses every 2
milliseconds.
1.2 2164A 64K RAM
The Intel 2164A is a high performance 65,536 word by
1 bit dynamic RAM, fabricated on Intel's advanced
HMOS-D III technology. The 2164A also incorporates
redundant elements. Packaged in the industry standard
16-pin DIP configuration, the 2164A is 'designed to
1.3 Compatibility of the 2118
and the 2164A
In 2118 memory systems designed for upgradability, it is
now possible to take advantage of the direct upgrade
3·73
AP·133
path to the 2164A. The common pinout and similarities
in A.C. and D.C. operating characteristics of most
systems make this upgrade easy and straightforward. A
simple jumper change to bring the additional multiplexed address into the memory array, a check for proper decoupling, and the replacement of the 211S's with
2164A's usually completes the job. In the two sections
that follow, both device and system level compatibility
issues are examined, key parameters are compared, and
implications discussed. A data sheet for each device
should be handy to aid in understanding the following
material.
2164A exceed those of the 21IS-15, as well as those timings specific to the read and refresh cycles. Noteworthy
are the t RWL (write command to RAS lead time) and
tCWL (write command to CAS lead time) specifications
of the 2164A. These are 60 ns less than those of the 211S,
allowing more flexibility in timing generation of the
write cycle. One other improvement is tpc (page mode
read or write cycle) which is 125 ns. This parameter
allows, for the first time, a two-fold performance advantage for page mode called extended page mode. This is
offered as an option to read or write an entire page (row)
of data during a single RAS cycle. By providing a fast
tpc and long RAS pulse width (tRPMZ), the 2164A-15
S6493 permits high-speed transfers of large blocks of
data, such as required in bit-mapped graphics applications.
1.3.1 DEVICE COMPATIBILITY
Both the 211S and 2164A are packaged in the industry
standard 16-pin DIP. Observation of the device's pinout
configurations shows that the only difference is the additional multiplexed address address input on pin 9 of the
2164A. This extra input is required to address the additional memory within. Notice the N/C (no connect) on
pin 1 of the 2164A. This allows for another direct upgrade path to the 256K DRAM device, with pin I used as
the next address input. The first and most obvious
specifications to compare are the speed and cycle times.
Clearly, when discussing compatibility and upgradability the same speed devices must be examined. A glance at
the respective data sheets shows that the 211S-15 and the
2164A-15 are the current devices available that are speed
and cycle time compatible, and further discussion will
center on these two specific device types.
There are a few of the 2164A timing specifications
however, that exceed those of the 211S. These are:
tCAC (access from CAS) = S5 ns, 5 ns greater
than 211S
tRAH (row address hold time) = 20 ns, 5 ns greater
than 211S
t CAH (col address hold time) = 25 ns, 5 ns greater
than 211S
tRCD (RAS to CAS delay time) = 30 to 65 ns,
versus the 211S, 25 to 70 ns
Usually only the t RAH specification has significance in
system applications. This and all other system level compatibility issues are discussed in the following section.
1.3.1.1 D.C. and Operati~g Characteristics
1.3.2 SYSTEM LEVEL COMPATIBILITY
Both the 2164A and the 211S function in the same temperature environment (0-70°C) with a single 5 volt
± IOlIlo power supply. All signal input voltage level
specifications are identical. The input load currents and
the output leakage currents are also the same. The
operating currents (IDOl, IDDZ, IDD3, IDD4) of the
2164A are greater than the 211S because of the increased
density of the 2164A. One other parametric difference
worth pointing out is the maximum capacitive load of
the control lines on the 2164A. The maximum specification is S pF on the RAS and CAS lines, each respectively
1 pF greater than the 211S.
1.3.1.2 A.C. Characteristics
/
When designing a new system, the current (IDD) requirements of the 2164A do not present any particular
problems. Simply proceed with the normal power requirement analysis, and specify the power supply accordingly. (A method for determining memory system
power requirements is detailed in Intel application note
AP-131 titled: Intel 2164A 64K Dynamic RAM Device
Description.) In a system being upgraded with 2164A
devices, check the new power supply reqirements against
the current power supply specifications to insure compatibility. Worth pointing out is the fact that in a 211S
system arranged as 64K by 16-bit word (32 devices) the
power/bit of the 211S-15 is 2.6 microwatts/bit (see
AP-75, pp. ll-12). Replacing the 211S's with 2164A
DRAMS creates a 256K by 16-bit word (again, 32
devices) and the power per bit is 1.33 microwatts/bit (see
AP-13I, pp. 11-12).The quadrupling in memory size
does not quadruple power supply requirements.
--
As mentioned above, the tRAC (access time from RAS)
spec of the 2164A-15 is a perfect match to the 211S-15.
Generally, the other A.C. timing specs of the 2164A
meet or exceed those of the 211S. Both the read and
write cycle times (tRd of the 2164A-15 are 60 ns less
than the 211S. The read-modify-writecycle of the 2164A
runs 130 ns faster than the 211S. All parameters in the
write cycle (reference 2164A data sheet page 3) of the
For a 64K by 16-bit to 256K by 16-bit conversion, the
additional power required is 2.S9 watts. (5.59 watts for
the 2164A system - 2.7 watts for the 211S system). On
3-74
AP·133
system and A is the device failure rate. This equation
(MTBF = lInA) says that system reliability is inversely
proportional to the number of devices in the system.
Therefore, a 1 Megabyte system (or any given system
size) built with 2164A devices is four times more reliable
as one built with 2118s.
the other hand, to build a 64K by 16-bit system with
2118 requires 2.7 watts versus only 1.4 watts for the
2164A, meaning that for a given system size, there is a
significant system power system savings by implementing the design with the 2164A.
The difference in current (I DD) specifications leads to
another system consideration, that of decoupling. The
larger current transients generated as a dynamic RAM
internally powers up as a response to rdresh cycles or active cycles requires decoupling to keep noise off the
power grid and to prevent a transitory local voltage drop
across devices. Specifics of calculating local and bulk
decoupling requirements are presented in Section 6.3.4,
but in general Intel recommends .1 JtF high frequency
ceramic capacitors for every 2164A device, and 100 JtF
bulk decoupling for every 32 devices.
In summary, when upgrading a system to 64K devices,
increase the decoupling, check the power supply, and
tweak the timing only if necessary, then enjoy the improved system reliability. When engineering a new
design, become familiar with and be aware of the specification differences between the 2118 and the 2164A.
2 MICROPROCESSOR SYSTEM
To effectively design a microcomputer memory, an
understanding of both the RAM and the microprocessor
is necessary. Since Intel microprocessors have been welldocumented in other publications, this applications note
will mainly focus upon operation during bus cycles as
related to the memory interface.
In comparison to the 2118, the ill, CAS lines of the
2164A RAM have 1 pF additional load. This seems trivial on a device level, but in a system the extra capacitance
adds approximately .1 ns/pF propagation delay (assuming low power Schottky drivers) to the overall system access path. With 16 devices per driver, this extra load
adds up to a measurable increase in propagation delay.
Determining additional delay due to capacitance is
standard engineering practice in a new design. When
upgrading a current memory system with 2164A
DRAMs, the additional delay also has to be considered.
Refer to section 6.2 for the formula to determine if the
additional loading is a concern in any specific application.
2.1 iAPX 86 Bus Operation
The iAPX 86 bus is divided into two parts: control bus
and time-multiplexed address data bus. The bus is the
microprocessor's only avenue for dialog with the
system. The processor communicates with poth the
memory and 110 via the bus. As a result, it must
necessarily differentiate between a memory cycle and an
1/0 cycle. In the minimum mode, this differentation is
accomplished with the signal Mira which remains valid
during the 'entire cycle. Therefore, this signal need not be
latched. In the maximum mode, the processor commits
to a bus cycle by means of three status bits transmitted to
the bus controller which generates the control signals ..
Of the four timing specifications where the 2164A-15 exceeds the 2118-15 usually only tRAR specification is of
concern. If, however, the system being upgraded is CAS
access limited rather than
access, then check the
timing to determine if the extra 5 ns on t CAC will require
system re-tuning. The column address hold specification
(tCAR) needs also be checked in this case. In the majority of DRAM systems, the access speed of importance is
tRAc, the RAS access time. When optimizing a memory
system to achieve the design's fastest access time, set the
t RCD spec to a value less than t RCD maximum. In these
high performance systems, be sure that the tighter 5 ns in
the 2164A tRCD spec window doesn't push out the
system access time by that amount, or if it does, that It
still conforms to the system timing requirements.
m
The bus cycle is divided into four times, referred to as
t-states, independent of the mode. Duration of this
t-time (tcLcd is the reciprocal of the clock frequency into the microprocessor. During each of these states, a
distinct suboperation occurs. In t 1, the address becomes
valid and the system is informed of the type of bus cycle,
memory or 1/0. In addition, a clock called ALE (Address Latch Enable) is generated to enable the system to
latch the address. This is required because the address
will disappear in anticipation of data on the bus. Intended to strobe a flow-through latch, ALE becomes active after the address is valid and deactivated prior to the
address becoming invalid. At the end of t2, the Ready
input is sampled. If it is low, the processor will "idle,"
repeating the t3 state ulltil the Ready line is high, allowing the memory or 110 to synchronize with the
microprocessor. In t3, the read or write operation commences and the high order status bits become valid.
Reliablity qualification data for the 2164A and 2118 are
identical with projections of less than .1 %/IK-hrs for
soft errors caused by ex particles and less than
.02%/IK-hrs for hard failures. This leads to a distinct
system reliability advantage of the 2164A over the 2118.
System reliability is qualified as MTBF (mean time between failure). This is the "up-time" of the system and is
defined as lInA where n is the number of devices in the
3-75
inter
Ap·133
Finally in t4, the machine cycle is terminated; input data
is latched into the processor in a read cycle or in a write
cycle output data disappears. The relationship of the
signals for minimum and maximum modes are shown in
Figures 4 and 5. Exact timing relationships will be
developed throughout the text. The design problem involves making the microprocessor signals intelligible to
the dynamic RAM.
MN/MX ..... Vee
r-----Wer------+-
M/iO
RD~-----+
...
The timing analysis is to be given with a read cycle for
the minimum mode configuration of Figure 6. Unlike
static RAMs which access from whenever every input
signal is stable, dynamic RAMs begin a cycle on a clock
edge after addresses are stable. This will introduce a certain amount of delay in the logic path. The exact amount
depends on the complexity of the memory controller.
Two paths to access will be considered: first, the control
signal to data input and second, address stable to data
input. In the read cycle there are four control signals;
MilO used to differentiate memory and 1/0 cycles, RD
used to control the output enable, DT iR: and DEN are
controls for data flow. Of these only M/ffi is a concern
to the memory design. Without WAIT states, no cycle
can be longer than four clock periods.
COMMAND BUS
----,,
,,
~1MEQABYTE
!----V
ADDRESS BUS
,
.
.,
I
16·B'T
DATA BUS
Figure 6. Minimum Mode Operation
T,
T,
T,
T,
CLK
eLK·
BHE
A16·A19
MliO
BHE
ALE
A16A19
ADO-1S
ALE
ADO
AD15
DTIA
Ri5
--+--"
!=lEAD
CYCLE
MRDC
DTIR
DEN
--+----l-\,
+-__+---J
DEN _ _
ADO·15
WRITE
CYCLE
1:::
+-__+---J
DEN _ _
-f-_J
AMWC
--+--""::="'+-..,.1
MWTC
--+---+----1---,.
WR -+------h.1
Figure 4. 8086 Bus Timing - Minimum Mode and Figure 5. 8086 Bus Timing - Maximum Mode
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Ap·133
Referring to Figure 5, the following is obtained:
Using this equation and the results from Table 1, tACC
can be calculated.
MEMCY:54 tCLCL
MilO is stable tCHCTV from the previous clock high
time tCHCL, but;
tCHcL
=
Table 2. tACC Calculations -
5 MHz
1/3tCLCL + 2
3tCLCL (ns)
IADDR(ns)
IDVCL(ns)
IIVOV(ns)
For the 5 MHz clock, tCLcL = 200 ns
solving for tCHCL,
tCHCL = 68 ns
But tCHCTV is 110 ns.
IACC(ns)
ALE(STB)
5 MHz
*
"--
-----
Figure 7. 828218283 Latch Timing
5 MHz
tCLAv(ns)
IIVOV (ns)
Flow Thru (ns)
110
=
= +- 22
132
=
tCLLH (ns)
=
tSHOV(ns)
=
Latch Delay (ns) =
Min Mode
8 MHz
+ 22
-
80
+40
120
82
= 110
= -110
= - - 22
IDS (ns)
= - 22
10 MHz
8 MHz
70
- 70
- 22
- 22
50
- 50
- 22
-
- 22
tDS
=
tCVCTC - (tCLDV + t1vOV)
10 MHz
Froin the calculations in Table 3, the leading edge of the
write pulse must be delayed in. the minimum mode.
These calculations will be used later.
50
+ 22
-
60
ICVCTV(ns)
ICLDV(ns)
IIVOV (ns)
Min Mode
During a write cycle, access is not the issue, but the write
pulse width, the data setup and hold time with respect to
the write pulse are of concern. The pulse width is simply
tWLWH, while data set-up time must be calculated from
a clock edge. Dynamic RAMs latch input data on the
falling edge of the write ena.ble pulse, so the calculation
is critical. Data is valid tCLDV plus the buffer delay
t\VOV in t2 while the write pulse begins tCVCTV in t2'
Worst case condition is a skew such that tCLDV is a maximum delay while tCVCTV has a minimum delay.
-{~t+--_-TIV----'OV--~\-'
Table 1. Address Latch Delays -
90
Table 3. Data Setup Time -
- TSHOV- -
OUTPUTS
10 MHz
375
600
Table 3 shows the system access time from stable address
to input data required. This time is the summation of the
RAM access time plus the control logic delay time.
Address calculations must include the buffer delay
(Figure 7). Stable addresses from the processor are
available tCLAv into the cycle and ALE is active tCLLH
into the cycle (Table 1). Addresses are on the bus tCLAV
plus t\VOV (latch delay) or tCLLH plus tSHOV (buffer
delay from strobe). The worst case number (tADDR) is
the greater of these two numbers.
INPUTS
=
8 MHz
300
80
5
+ 20
+ 22
+ 22
184 -184 132 -132 107 -107
416
243
193
=
= 132
= + 30
= + - 22
SUBTOTAL (ns) =
As a result, MilO is a stable worst case 32 ns after the
start of a memory cycle. For an 8086-2, tCLCL is 125 ns
and tCHCTV is 60 ns. Similarly, MilO is stable 17 ns
after the start of the cycle.
Min Mode
72
50
+ 40
90
Having examined the major timing parameters of the
minimum mode configuration, let's now check the maximum mode timings.
40
+40
-
80
In the maximum mode configuration of Figure 8, the
system has another component - an 8288 bus controller
- which generates ALE and the read and write control
signals. In this configuration a memory read cycle is not
committed until tCLML into t2 whereas in the minimum
mode operation, the information was known in t I. In
this respect, a maximum mode system access cycle is less
than'3t CLCL.
Flow through delay is the limiting factor of the 5 MHz
system, whereas delay from the latch strobe (ALE) is the
limiting factor in the fastest processors. Finally, data
must be inputted tDVCL plus t\VOV to the data buffer
prior to the fourth t-state. Access from stable addresses
is:
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Ap·133
Table 5. tAcc Calculations 5 MHz
GND
51
52
52
MWTC
COMMAND BUS
DEN
tACC(ns)
1 MEGABYTE
ADDRESS BUS
8 MHz
10 MHz
600
375
=
72
82
= 132
5
+ 20
= + 30
+ 22
+ 22
= + 22
SUBTOTAL (ns) = 184 -184 124 -124
99
300
3tCLCdns)
tADDR (ns)
tDVCL (ns)
tIVOV (ns)
8288
SO
51
Max Mode
=
-
-
416
251
-
-
99
201
Access from the read command (MRDC) must also be
determined. MRDC is valid tCLML from t2, causing access (tCA) from MRDC to be:
tCA
=
2tCLCL - tCLML - (tDVCL + tIvOV)
Using, this equation, Table 6 shows the access calculations.
l6·BIT
DATA BUS
Table 6. Access From Memory Read Command
5 MHz
2tCLCL (ns)
tCLML(ns)
tDVCL (ns)
tIVOV (ns)
400
=
35
35
=
+ 20
= + 30
+ 22
= + 22
SUB TOTAL (ns) =
77
87 - 87
313
tCA (ns)
=
Figure 8. 8086 Maximum Mode Operation
To determine address delay, we will, again, examine the
data flow path and the delay from the latch opening.
The greater of these two numbers is the worst case time
delay (tADDR)'
Flow-thru Delay = tCLAV + tIVOV
Latch Delay = tCLLH + tSHOV
Using these equations and previous data, Table 4 shows
how Flow-thru Delay can be calculated.
Table 4. Flow·through Delay 5 MHz
tCLAv(ns)
=
tIvOv(ns)
=
Flow Thru Delay =
IS
tCLLH(ns)
=
tSHov(ns)
= +40
Delay from ALE =
55
10 MHz
50
+ 22
-
60
+ 22
82
72
IS
IS
+40
-55
+40
55
10 MHz
250
200
35
5
+ 22
- 77
62 - 62
173
138
Access from the memory read command (MRDC) is
much more stringent than address access. Consequently
both access paths must be consideed in system design.
The write cycle has the same limitation as access from
memory read command. Memory write is identified by
Mw'fC having the same timing as the memory read
command. Address timing is the same for both the read
and write cycles. The write pulse, twp is generated by
MW"fC with a pulse width of one clock cycle plus maximum tCLML plus the minimum overlap into the next cycle (t CLMH)'
Max Mode
8 MHz
110
+ 22
132
8 MHz
twp = tCLCL + tCLML - tCLMH
For the 5 MHz, 8 MHz, and 10 MHz system, twp is
calculated as shown in Table 7.
Table 7. twp Calculations -
In each case in Table 4, the limiting delay is f1ow-thrutime. Access time from address can now be determined.
Again, data must be valid tDVCL plus the input buffer
delay (tIVOV) before the end of t3. For maximum mode
access from the address valid time is:
5 MHz
125
10 MHz
100
=
35
35
35
=
- 10
- 10
= - 10
SUBTOTAL (ns) =
25 - 25
25 - 25
25 - 25
twp(ns)
175
, 75
100
=
tCLCL,(ns)
tCLML (ns)
tCLMH (ns)
tACC = 3tCLcL - tADDR - (tDvCL + tIVOV)
Using this equation and previous data (Table 4), Table 5
shows how tACC can be calculated.
3-78
200
Max Mode
8 MHz
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Ap·133
Data setup time (tos) to the leading edge of the write
pulse occurs approximately one tCLCL time later. From
tCLCL, the maximum tOVCL plus the minimum tCLML
must be subtracted:
+
tos = tCLCL - (tCLDv
lOW ORDER
ADDREssr;s~
tCLML)
Now tos can be computed as shown in Table 8 by using
data from previous calculations and the data sheet.
Table 8. Data Setup (tos) Calculations Max Mode
ICLov(ns)
=
=
ICLML(ns)
=
lOS (ns)
=
ICLCL(ns)
5 MHz
8 MHz
200
12S
100
-1l0
-60
- 50
-
-
-
-
10
80
-
10
SS
10 MHz
-
10
40
Using MWTC as the write pulse allows sufficient data
set-up time for the dynamic RAMs. These, then, are the
basic timing equations for the system of Figures 6 and 8.
They are general in that timing requirements for different clock frequencies (Le., 9 MHz) can be calculated
using them. Armed with these equations, the designer
can now shape the control and address signal in the time
domain with a memory controller to meet the dynamic
RAM requirements.
'20 TTL PACKAGES REOUIRED TO IMPLEMENT REFRESH/CONTROL
Figure 9. Refresh Timing and Control
Block Diagram
Consequently, a large delay is injected every 2 ms. On
the other hand, distributed refresh steals a single cycle,
128 times periodically throughout the 2 ms. Evenly distributed, a refresh cycle occurs once every 15 microseconds. Again assume a 350 ns refresh cycle, and our 5
MHz system need only inject two WAIT states (worst
case) each time. Thus distributed refresh is preferable in
almost all microprocessor systems.
In addition to converting address, MRDC and MWTC
into RAS, CAS, WE, etc., to satisfy both the processor
and memory, another task called refresh must be performed by the memory controller.
Performing the interface translation, providing refresh
and controlling the signal timing to the RAM requires a
controller that consists of six elements as shown in
Figure 9. Of these, the most basic is the oscillator
because it fulfills two functions: providing a time base
for refresh interval timing and establishing precise times
for RAS; CAS, etc., to the RAM. The operating frequency must be high enough to provide sufficient increments between timing signals. The relationship of
timing signals will be multiple periods of the clock frequency. In addition, the oscillator drives a countdown
or divide by N circuit to measure the ttme between refresh cycles. Refresh can be either burst or distributed.
In the burst mode, a refresh request would occur once
every two milliseconds to meet the dynamic RAMs'
needs. For a 16K or 64K RAM with 128 refresh cycle requirement, all 128 refresh cycles would be performed
consecutively. A disadvantage of this method is that the
memory is "out of service" for a long period of time.
Assume a 350 ns cycle time, then the time required to
perform refresh is 350 ns multiplied by 128 cycles or 44.8
microseconds operating with a 5 MHz 8086; this
translates to 224 consecutive WAIT states.
Guaranteeing that all 128 refresh addresses are exercised
is the task of the refresh address counter. It consists of
an eight-stage binary counter. After the refresh cycle has
been completed, the counter is advanced one count. Incrementing after refresh eliminates any concern regarding
address settling or setup time as the counter outputs are
changing. This would be a concern if the counter were
incremented as the refresh cycle started.
Because the counter cycles through all 128 addresses
every 2 milliseconds, it isn't required to be in a specific.
state after power on, Le., it need not start at address 0
after power on.
Next is the arbiter - which can be the bane of every
memory design. Deciding whether a memory cycle is an
access cycle or a refresh cycle is the function of the arbiter. Refresh requests are derived from the oscillator
which operates asynchronously with the system clock.
The arbiter will grant the request when a refresh request
is made and no memory cycle is occuring or pending. If
3-79
Ap·133
an access cycle is in progress, the arbiter must inhibit the
refresh cycle until the current cycle is completed. The
same logic process occurs if a refresh cycle is in progress
'and access is requested. This sequence flows smoothly
most of the time. The difficulty arises when refresh and
access are requested simultaneously. In every arbiter
there exists an infinitely small but very real time period
when the arbiter cannot make a decision, much less the
correct one. Consider the arbiter in Figure 10 - a simple
cross-coupled NAND or an R-S flip-flop.
Effective solutions have reduced performance to maximize reliability. One such method is a two stage clocked
flip-flop per Figure 12.
'
HAS MULTIPLE STAGES
(MASTER/SLAVE APPROACH)
a
~
If both requests are made simultaneously, both would be
0
......£.
.
MASTER
SLAVE
granted - an impossibility!
t>
~
~
REFRESH GRANT
MEM CYCLE GRANT
-
t>
FLlp·FLOPS HAVE HIGH GAIN/HIGH POWER/HIGH SPI;:ED
MASTER HAS SCHMIDT TRIGGER INPUTS
MASTER/SLAVE HAVE DIFFERENT THRESHOLDS
FLlp·FLOP D·INPUT IS INTEGRATED TO FILTER GLITCHES
CROSS COUPLING (POSITIVE FEEDBACK) IS USED
DATA LOCKOUT ON D·INPUT IS USED
Figure 12. 8203 Arbitration Logic
Figure 10. Arbiter Cross·coupled NAN D Gates
In this configuration arbitration is performed at the seccond stage so that even if the first stage "hangs" all will
be settled by the clocking of the second stage.
Another arbiter frequently used is a D-type flip-flop as
in Figure 11. Here arbitration is attempted between the
clock and the D input. Violating the setup or hold time
with respect to the clock can cause the output to enter a
quasi-stable state of non-TTL levels for as long as 75 ns.
This timing is too long for many high performance
systems.
The timing and control section is the core of the controller. Under its guidance, addresses are switched for multiplexing. RAS, CAS, WEare produced and sequenced in
a fashion understandable by the RAMs. One other fea-
-QOUTPUT
DATAOTYPE
LATCH
CLOCK--
'i
DATA
·tSETUPCLOCK
tHOLD ________
aUASI STABLE STATE
./'
aOUTPUT
-tPROP
"" I
VIOLATING & SETUP
OR tHOLD
tpROP*
'CAN BE UP TO 75
"sec FOR A 74574
A941
Figure 11. D·type F/F Arbitration
3·80
Ap·133
ture required is a handshake signal with the processor to
indicate whether or not the memory is ready to be accessed. This is usually implemented with a System Acknowledge (SACK) (an early signal in the cycle) which
indicates a receipt by the controller of a memory access
request, or by a Transfer Acknowledge (XACK, a signal
occuring later in the memory cycle), indicating the valid
memory data is available.
dynamic RAM controller for microprocessor systems
and expansion memories. All of the system control
signals are provided to operate and refresh the 2117,
2118 and 2164A dynamic RAMs. To accomplish this,
the 8203 provides the following features:
• Directly addresses one-half megabyte of 2164A
(with external drivers)
• Provides address multipexing and RAS, CAS, WE
strobes
• Provides a refresh timer and an 8-bit refresh address counter
• Refresh may be internally selected for automatic
refresh in a distributed fashion
• Refresh may be externally requested to provide for
synchronous or transparent refresh
• Compatible with Intel 8080A, 8085A, iAPX 88
and iAPX 86 families of microprocessors
• Provides system acknowledge and transfer acknowledge signals
• Allows asynchronous memory and refresh cycle requests
• Provisions for external clock or crystal oscillator
The final piece of the memory controller is the address
mUltiplexers and buffers to drive the memory addresses.
During the normal memory cycle the parallel addresses
from the bus must be reduced by one half through time
multiplexing. In addition refresh addresses must be applied to the array through this same address path. Buffers are shown to drive the capacitance of the array with
signals having sharp rise and fall times.
Figure 9 also shows the quantity of TTL packages required to implement such a controller. Twenty TTL
packages are usually required for a controller.
To design a controller with discrete TTL components
can take several man months of design effort. Typically,
four weeks for design, two weeks for timing analysis,
four weeks to build and debug prototypes, six weeks for
circuit board layout, and another four weeks to add additional features or to tweak the original design. Obviously, the Intel 8203 DRAM controller is a desirable
alternative.
A block diagram of the 8203 is given in Figure 13 which
illustrates how these features are integrated.
2.2.1 OSCILLATOR
The Intel 8203 generates its timing from an internal shift
register which is crystal controlled. This method provides highly accurate control of the timing required for
dynamic RAMs. This method is sllperior to a monostable mulitvibrator approach where transients and unitto-unit timing accuracies are difficult to control.
2.2 8203 Dynamic RAM Memory
Controller
The Intel 8203 is a Schottky bipolar de,vice housed in a
40-pin dual in-line package. It provides a complete
TIMING
GENERATOR
REFRESH
COUNTER
ARBITER
REFRQ/ALE - - - -....--+1
X,/CLK""
Figure 13. 8203 Dynamic RAM Controller Block Diagram
3·81
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Ap·133
2.2.2 ARBITER
The arbiter resolves all conflicts between any cycles that
are requested simultaneously. These cycles can be
generated from one of four places:
1.
2.
3.
4.
Read Cycle Request - ROISI input
Write Cycle Request - Wi input
External Refresh Request - REFRQ/ALE
Internal Refresh Request - (refresh timer shown in
Figure 13)
If a refresh cycle is in progress and a read or write cycle is
requested, the requesting device receives a "not ready"
until the present cycle is completed. After completion of
the present refresh cycle a response from the 8203 called
System Acknowledge, or SACK, will notify the requesting device of availability for use. If a read or write request occurs simultaneously with a refresh request, the
read or write cycle will be performed first, then the refresh cycle. Read and write cycle requests cannot occur
simultaneously during normal operation. If the 8203 is
deselected, only an internal or external refresh cycle request will be accepted. Once sel,ected, it vyill continue
with the present memory cycle if one is being performed.
(Hence the chip select input is called protected chip
select, PCS, because the current cycle is always completed regardless of any other pending request.)
The outputs from the multiplexer are inverted from the
address inputs. This is immaterial to the dynamic RAM
array and does not require inversion for proper system
operation.
2.2.5 TIMING AND CONTROL
The timing and control logic allows either a read, write
or refresh cycle to occur. After any read or write cycle
request, SACK (System ACKnowledge) goes active if
the cycle was not requested during a refresh cycle. If it
was, SACK is delayed until XACK, thereby requesting
WAIT states from the cycle requester.
Figure 14 is a diagram of the 8203 pinout. Table 9 lists
the pin numbers, the symbols, and the function of each
pin when the 8203 is configured for the 64K option.
The 8203 has two ways of providing dynamic RAM
refresh:
1. Internal (failsafe) refresh
2. External refresh
m
Both types of 8203 refresh cycles activate all of the
outputs, while CAS, WE, SACK, and XACK remain inactive.
2.2.3 REFRESH TIMER AND COUNTER
The' refresh timer is a counter that increments on each
pulse from the clock input until it reaches a preset
number causing an internal refresh request to occur.
Note that this causes the refresh rate to be 8203 clock cycle dependent. External refresh requests will cause the
refresh timer to reset, but will not disable it.
The internal address counter contains the address that
will be used during the next refresh cycle. The counter is
incremented after each refresh, counting up to 256
before resetting to zero after all RAM addresses have
been refreshed. All current generation Intel DRAMs require a 128-cycle refresh, hence, the most significant bit
is ignored. However, this extra bit allows use of 256 cycle 4 ms refresh devices without changing the current
memory system design.
Figure 14. 8203 Pinout
2.2.6 REFRESH CYCLES
Internal refresh is generated by the on-chip refresh
timer. The timer uses the 8203 clock to ensure that
refresh of all rows of the dynamic RAM occurs every 2
milliseconds. If REFRQ is inactive, the refresh timer will
request a refresh cycle every 10-16 microseconds.
2.2.4 MULTIPLEXER
The multiplexer is controlled by the timing and control
logic. It presents to the address bus one ofthe following:
1. The contents of the refresh counter when there is a
refresh cycle
2. ALo_6 on a RAS pulse
3. AH o_6 'on a CAS pulse
External refresh is requested via the REFRQ input (pin
34). External refresh control is not available when the
Advanced-Read mc;>de is selected. External refresh requests are latehed, then synchronized to the 8203 clock.
3-82
Ap·133
Table 9. Pin Description (64K Option)
Symbol
Pin No.
Type
Name and Function
ALo
ALI
AL2
AL3
AL4
ALs
AL6
AL7
6
8
10
12
14
16
18
24
Input
Input
Input
Input
Input
Input
Input
Input
Address Low: CPU address inputs used to generate memory row address.
AHo
AHI
AH2
AH3
AH4
AHs
AH6
AH7
5
4
3
2
I
39
38
25
Input
Input
Input
Input
Input
Input
Input
Input
Address High: CPU address inputs used to generate memory column address.
BO
26
Input
Bank Select Input: Used to gate the appropriate RASo-RAS 1 output for a
memory cycle.
PCS
33
Input
,
Protected Chip Select: Used to enable the memory read and write inputs. Once a
cycle is started, it will not abort even if pes goes inactive before cycle completion.
WR
31
Input
Memory Write Request
RD
32
Input
Memory Read Request
REFRQ
34
Input
External Refresh Request
OUTo
OUT I
OUT2
OUT3
OUT4
OUTs
OUT6
OUT7
7
9
II
13
15
17
19
23
Output
Output
Output
Output
Output
Output
Output
Output
WE
28
Output
Write Enable: Drives the write enable inputs of the dynamic RAM array.
Output of the Multiplexer: These outputs are designed to drive the addresses of
the dynamic RAM array. (Note that the OUTO_7 pins do not require inverters or
drivers for proper orientation.)
CAS
27
Output
Column Address Strobe: This output is used to latch the column address into the
dynamic RAM array.
RAS o
RAS I
21
22
Output
Output
Row Address Strobe: Used to latch the row address into bank of dynamic RAMs,
selected by the 8203 Bank Select Pin (Bo).
XACK
29
Output
Transfer Acknowledge: This output is a strobe indicating valid data during a read
cycle or data written during a write cycle. 'XA'CK can be used to latch valid data
from the RAM array.
SACK
30
Output
System Acknowledge: This output indicates the beginning of a memory access
cycle. It can be used as an advanced transfer acknowledge to eliminate WAIT
states. (Note: if a memory access request is made during a refresh cycle, SACK is
delayed until XACK in the memory access cycle.)
X O/OP2
36
Input
Crystal Inputs: These inputs are desiliBed for a quartz crystal to control the frequency of the oscillator. Xl/CLK becomes a TTL input for an external clock if
X/OP is tied to Vee.
3-83
AP·133
The arbiter will allow the refresh request to start a
refresh cycle only if the 8203 is not in a cycle.
The user can select the desired Read request configuration via the BlIOPl hardware strapping'option on pin
25.
Internally, if a memory request and a refresh request
reach the arbiter at the same time, the 8203 will honor
the refresh request first. However, the external refresh
synchronization takes longer than the memory request
synchronization so, relative to the 8203 input signals, a
simultaneous memory request and external refresh re, quest will result in the memory request being honored
first. This 8203 characteristic can be used to "hide"
refresh cycles during system operation. A circuit simiIiar
to Figure 15 can be used to decode the CPU's instruction
fetch status to generate an external refresh request. The
refresh request is latched while the 8203 performs the instruction fetch: the refresh cycle will start immediately
after the memory cycle is completed, even if the RD input has not gone inactive. If the CPU's instruction
decode time is long enough, the 8203 can complete the
refresh cycle before the next memory request is generated.
Normal Reads are requested by activating the Ri5 input,
and keeping it active until the 8203 responds with an
XACi( pulse. The RD input can go inactive as soon as
the command hold time (tCHS) is met.
Advanced Read cycles are requested by pulsing ALE
while SI is active; if SI is inactive (low) ALE is ignored.
Advanced Read timing is simiIiar to Normal Read timing, except the faIling edge of ALE is used as the cycle
start reference.
If a read cycle is requested while a refresh cycle is in progress, then the 8203 will set the internal delayed-SACK
latch. When the Read cycle is eventually started, the
8203 will delay the active SACK transition until XACK
goes active. This delay was designed to compensate for
the CPU's READY setup and hold times. The delayedSACK latch is cleared after every READ cycle.
Based on system requirements, either S'ACK or XACK
can be used to generate the CPU READY signal. XACK
will normally be used; if the CPU can tolerate an advanced READY, then SACK can be used. If S'ACK arrives too early to provide the appropriate number of
WAIT states, then either XACK or a delayed form of
SACK should be used.
~~----REFRa
a~~~
.. _
WR--------------WR
Figure 15. Hidden Refresh Generator
After each refresh cycle, the 8203 increments the refresh
counter, reloads the refresh timer, and clears the external refresh latch. If the external refresh request is held
active, the latch will be set again, and another refresh cycle will be generated. If, however, a memory request is
pending, it will be honored before the second refresh request. Th'is feature prevents refresh from locking out the
memory request.
2.2.8 WRITE CYCLES
Write cycles are similiar to Normal Read cycles, except
for the WE output. WE is held inactive for Read cycles,
, but goes active for Write cycles. All 8203 Write cycles
are "early write" cycles; WE goes active before CAS
goes active by an amount of time sufficient to keep the
dynamic RAM output buffers turned off.
For a more detailed analysis of the 8203, refer to Application Note AP-97A, entitled "Interfacing Dynamic
RAMs to iAPX 86/88 Systems Using the Intel 8202A
and 8203."
Certain system configurations require complete external
refresh control. If external refresh is requested faster
than the minimum internal refresh timer (tREF) then, in
effect, all refresh cycles will be caused by the external
refresh request, and the internal refresh timer will never
generate a refresh request.
3 SIMPLE SOLUTION
An example of the ease of interfacing DRAMs to microprocessors with the 8203 is shown in Figure 16. This is an
example of the 8203 and 2118's or 2164A's configured as
local memory to a min mode iAPX 88 System. The CPU's
local bus is demultiplexed by an 8283 which latches the.
addresses and presents them to the 8203. Notice the lack
of TTL support circuitry. The only additional components are a latch for the dynamic RAM output data
and a OR gate to steer the WE signal on byte writes. The
8203 handles all the interfage requirements of the
2.2.7 READ CYCLES
The 8203 can accept two different types of memory
Read requests:
1. Normal Read, via the Ri5 input
2. Advanced Read, using the SI and ALE inputs
3-84
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Ap·133
ity of the 16 bit 8086 to perform byte operations requires
two gates (shown on the diagram of Figure 17 between
the 8203 and the 2164A array) to steer the write pulse
output from the 8203 to either the high or low byte or
both bytes as directed by AO and BHE (Byte High
Enable).
DRAM array, rendering a very simple solution to a
dynamic memory design.
Figure 17 is an 8203/2164A memory system configured
as a global resource to a max-mode iAPX 86 microprocessor system. Although there are several more TTL
components involved, the buffers and transceivers are a
requirement for proper system bus interface design. In
terms of controlling the memory, the 8203 and 2164A interface is as simple as in the previous example. The abil-
These examples balance ease of use and design throughput time with performance. The designs shown typically
require one to two WAIT states. With one WAIT state,
Figure 16. 8203/2118 Local Memory System
MUlTlBUS®
TYPE
SYSTEM
BUS
Figure 17. 8203/2164A Global Memory System
3-85
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Ap·133
processor performance is reduced to 91.7010, and with
two WAIT states it drops to 83.7010. This may be acceptable in many applications, but where it is not, a modest
additional design effort can yield zero WAIT states.
not a simple task in minimum mode operation because
the iAPX 86 processor produces the RD and WR signals
in a fIxed relationship after ALE occurs. However,
operating in a max-mode, the iAPX 86 outputs three
status bits (SO, Si, 82) which occur ahead of the ALE
signal. (Refer to the timing diagram shown in Figure 18.)
With proper logic circuitry, these status bits can be used
to initiate the advanced signals required.
4 5 MHz NO·WAIT STATE SYSTEMf
4.1 Circuit Description
The following discussion describes a 5 MHz no-WAIT
state 'microprocessor memory system designed for optimum performance. Figure 19 shows an iAPX 86 maximum mode system modified for zero WAIT states. The
circuitry added to the system previously described is enclosed in the dashed lines. The 8205 decodes the three
status bits (80, Si, 82) and outputs an advanced read or
write signal at pin 13 or 14, respectively. These signals
flow through the corresponding 748158 (a 2: 1 mux con-
The DRAM/8203 microprocessor memory system discussed up to this point met all of our design criteria except one"':" optimum performance. In minimum mode
operation, inherent delays in the system Ri5 and WR
commands resulted in a READY signal that was too late
to avoid processor WAIT states. Attaining zero WAIT
states requires minimizing these delays by transmitting
advanced read (RD) or write (WR) commands. This is
T,
T,
TCL'J---,
LK
T,
}_~ I-TCL,cLl ~':-,
TCH.CH.!..I
VCL...) ITCCAv.
o",os,
~ t-JI~ ' L - . )
X
~
X
1 - ITCHSV
-
TCLSH_
s;s;:"iU (EXCEPT HALn
A"
..
:~L~~H,,:
ALE (82. OUTPU
n
_TC' :AV
,
_
A"A"
I:: -
I·
::b
TA~
~
I_T~1VLC
'1~ ~,,\\\\\\\~
1__ TCLF 'x
1
IVHSH-
Y.
I
1
'AD, Ao,
~
_TCHRYX
,-
-V
DATA IN
FLOAT
TCLRH
"....
.1 ~
\
TCLML-
HI5C OR'R5e
-
--
.I~
TCHDTL-
[
.r--
0
82880UTPUTS
,-
TCHDX-
I
TA :RL_
SEE NOTES 6, 8
-
\
,[
DrI~
--'
-TCHLL
READY(8088INPU
AD, A 0,
'"U,'"
"B,
~
TCLAV_
fC..
-
LAX
I
n
READ CYCLE
X
A,,~
see NOTES (
ADYfl284INPU
~n-
VC':r--'I
TCLMH-
\
TCVNV-
I~
I
i-
~
u-
"
DEN
I,
{
TCVNX-
I=-
Figure 18. 8086 Bus Timing - Maximum Mode System (usin'J 8288)
3·86
inter
Ap·133
- used in place of XACK because it occurs sooner) is
returned to the 8284A which provides a synchronous
ready signal to the iAPX 86. The advanced memory
write command, A'MWC, clocked to provide appropriate timing with CAS, is ORed with WE to obtain
the WR for the 2118's. The S2 status bit is latched by the
74S158 on the trailing edge of ALE.
figured as a high speed flow through latch) and are latched
on the falling edge of ALE from the 8288. Latch outputs
(ADV WRC and ADV RDC) are connected to the 8203
WR and RD inputs. The two latches are cleared by
clocking 'the trailing edge of either the memory read
command (MRDC) or memory write command (MWTC)
through a 74S74 flip·flop. System acknowledge (SACK
)1
I~
I~
~
o
,I
~I~
g~
Ii
u ___ -,
J
"
s
o
Figure 19. 5 MHz No·WAIT State Microprocessor Memory System
3·87
inter
Ap·133
latest PCS is generated by decoding CPU addresses and
arrives within 133 ns. The SAcK signal is then returned
within 127 ns from PCS. The buffered SACK is used as
the READY signal to the iAPX 86, resulting in zero
WAIT states (except when the 8203 is performing a
refresh cycle). The maximum PCS to CAS delay is
shown to be 245 ns. Also accounted for is the maximum
access time from CAS to data valid of 80 ns and a propagation delay of 45 ns for valid oata to reach the processor.
4.2 Analysis and Description of
System Timing
Read cycle worst case analysis is shown in Figure 20
which only considers the maximum time delays. The
four processor t states are indicated by t I through t4. To
accomplish zero WAIT states, valid data must reach the
iAPX 86 by the end of t3 minus 30 ns. The latest read
data arrives at the iAPX 86 (next to the last waveform)
within this time frame. Timing relationships are as
follows: '
In the write cycle, the relationship between data and WE
at the memory and the relationship between the leading·
edge of WE and the trailing edge of CAS (tewd must be
The ADV RDC flows through the 74S158 latch and
reaches the 8203 within 6 ns after the rise of ALE. The
I
T,
T,
200ns
TCLCl-CLOCK
LATEST
ALE
LATEST ADV ROC
AT 8203
LATEsrPCs
AT 8203
LATESrSAcK
FROM 8203
READY INPUT
(BUFFERED SACK)
T08284A
TR1VCH"'35ns~
NECESSARY ASYNCHRONOUS
- { READY SETUP AT 8284A TO
GUARANTEE NO WAIT STATE
_TACK::10ns
PCS TO CAs DELAY
AT 8203 (MAX)
TeAC
::80n8FOR
SLOWEST 2118
MAX~~~~:~~~~--4------------------------iI~_DA_T_AV_A_Ll_DO_U_T_OF_2_"_.__~-JII~_
PROP DELAY 70 ns
LATEST READ DATA
READ DATA
ARRIVAL AT 8086 -f-,,--------------=------------I]'----;:M:::Us::::T'"=.;-":E~O FOR NO
1--___________ 570ns __________--'---Jr-W~A~IT~S::;TA:.!T=ES~·___
D~~ :~~~~~LV-Ai~~~~ -...:..------------:--------------------{['-:-V_A_Ll_DD_A_TA_A_TC_P_U_
rTDVCl
READ CYCLE WORST CASE ANALYSIS
8086 IN MAX MODE AT 5 MHz
8203 AT 25 MHz
·CRITICAl TIMING FOR ZERO WAtT STATES
Figure 20. Read Cycle Timing Analysis (5 MHz)
3·88
AP·133
preserved. Since DRAMs write data on the leading edge
of the write pulse, data must be valid before the fall of
WE. Timing analysis of the skew of the normal memory
write command (MWTC) to valid data shows that worse
case, it is possible to have data, arrive after the falling
edge of WE (case 1 of Figure 21). Using the other write
pulse available from 8288 bus controller, the advanced
memory write command (AMWC), led to the problem
depicted in Figure 21, case 2, violation of the DRAM
specification tCWL. From these observations, the need
for the clocked AMWC pulse becomes apparent. By
delaying the AMWC pulse until the next rising edge of
the system clock and then gating this signal with the WR
output from the 8203, a "best-fit" write pulse is created
that meets all timing requirements.
generation and arrival of timing signals to the memory.
Since the controller is CAS access (tcAd limited, the
tCAC spec of the 2118 and the 2164A must be compared
for the read cycle. tCAC on the 2164A-15 is 85 ns, 5 ns
greater than the 2118. This means that valid data will arrive at the 8086 processor 5 ns later, for the worse case,
using the 64K device. The read cycle timing analysis
shows this is still well within the 570 ns requirement of
the 8086. During the write cycle, two parameters were of
concern in the 5 MHz system:
tDS (data set-up before CAS)
, tCWL (leading edge of write to trailing edge of CAS)
Since the tDS spec is the same for both devices (0 ns), the
original timing analysis for this parameter is still valid
and the 2164A fits. The tCWL spec for the 2164A-15 is
40 ns. This is 60 ns less than the 2118-15, so that
substituting the 2164A actually relieves a tight timing
spot in this design. The additional delay added to control line paths due to larger input capacitances of the
2164A is accounted for in the 8203 specification (the
8203 is specified to directly drive four rows of 2118's,
only two rows of 2164A's for this reason). After adding
decoupling to meet the 2164A-15 requirements, the
2164A memory system is up and running, doubling
memory size and reducing device count by one-half.
WE TO DATA SKEWS PROHIBIT USE OF COMMANDS
DIRECTLY FROM 8086 PROCESSOR
CASE 1 -
DATA NOT, VALID AT WRITE
~VAL1D
WORST CASE DA: FROM 8086
BEST CASE CAS/WE FROM 8203
-----"'t_+-_
_
~tDS
CASE 2 -
NOT ENOUGH TIME TO WRITE
BEST CASE CAS FROM 8203
4.4 System Reliability
WORST CASE COMMAND
FROM 8086 (MWTC)
The majority of microcomputer systems are designed into applications where system failure ranges from irritating (such as a vending machine failure) to a financial
loss (such as a double debit from an electronic teller
machine). While these are not life threatening failures,
reliability is important enough to be designed into the
system.
Figure 21. Write Cycle Problems
Figure 22 depicts the worst case analysis of the write cycle. The timing relationships are similar to those for the
read cycle with a few exceptions. The advanced write
commimd, ADV WRC, flows through 74S158 and is
latched by the fall of ALE. The earliest CAS occurs 145
ns after the PCS. Valid data is output from the CPU
within 210 ns and re'aches the memory 35 ns later. The
advanced memory write command, AMWC, and associated progation delays must satisfy the tCWL requirement
of the 2118's which starts at the beginning of the AMWC
pulse and terminates with the end of CAS. The write
enable, WE, from the 8203, is ANDed with AMWC to
obtain the WR for memory.
A memory system is one of the system components for
which reliability is important. Also it is one of the few
system elements which can be easily altered to enhance
its reliability. The inclusion of some additional hardware allows the CPU to keep check on the integrity of
the data in memory. Figure 23 represents a five TTL chip
solution that, when added to the 5 MHz design example,
allows error detection in the memory.
Because the 16-bit 8086 has the ability to do selective
high or low byte writes in addition to full word operations, parity needs to be generated and checked on the
byte level. This requires two extra memory devices per
row to store the parity bits of the high and low bytes.
4.3 Comj)atibility of the 2118 and 2164A
The 5 MHz no-WAIT state system was designed with the
2118-15 DRAM. By following the guide lines in section
1.3 and examining tight timing areas specific to this application, it can be shown that the system is expandable
and works equally well by using two rows of 2164A-15
parts in place of four rows of 2118-15 parts. The 8203,
when configured in the 64K mode, guarantees ptoper
Parity is generated by exclusive ORing all the data bits in
each byte (accomplished by the 74S280) which results in
a parity bit. This parity oit is the encoding bit of each
byte. Because there are eight data bits, the parity bit Cis:
C = b l G)b2 ...... b 7 G1 b s where b = value in the bit
positions.
3-89
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Ap·133
8086 CLOCK
ALE
133na
LATEST PCS AT 8203
127 ns
SACK FROM 8203
READY INPUT
(BUFFERED SlreRi
AT"""
---t----+---'
MIN ROY SETUP
AT 8284A,., 35 ns
tec
ICASMIN _ _
145n8
200ns
EARLIEST CAS
FROM DELAY
310n8-----1
LATEST VALID DATA
FROMCPU _ _ _ _ _ _ _ _ _ _ _ _'I~____~r_-----------'~-22
LATEST VALID DATA
ARRIVAL AT 2118
ns
PROP DELAY
VALID DATA AT MEMORY
--------------'1\.--~f_------------'
M'~=45n.
EARLIESTWlf
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FOR 2118
FROM 8203
EARLIEST
CLO~~~~S=
-------------lI
,----
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, 8086 IN MAX MODE AT 5 MHz
8203 AT 25 MHz CLOCK
EARLIESTClOCKED~
+ PROP DELAYS""YiR AT 2118
--------------+.
TDSMIN = 8 ns WORST CASE"
WRITE CYCLE WORST CASE ANAL VSIS
~
I--I.....I~---TDH
100nsTCWLMIN
'CRITICAL TIMING FOR ZERO WAIT STATES
Figure 22. Write Cycle Timing Analysis
iNTA~-"""-
PWRup·RESET
Figure 23. Parity Checker/Generator
3·90
AP·133
The parity bit combines with the bits from the original
data byte to form the encoded half-word (9-bit byte).
Encoded words always have either "odd" parity, which
is an odd number of Is (an odd weight) or "even" parity
which is an even number of Is (an even weight). Odd and
even parity are never intermixed, so tlJ.at the encoded
words have either odd or even parity - never both.
Using the encoded word "010" one possible double bit
erro,r (DBE) is:
I 1I
L- Parity
Checking parity:
C=I(j;)I=1
When the encoded word is fetched" the parity bits are
removed from the word and saved. Two new parity bits
are generated from each byte. Comparing these new
parity bits with the stored parity bit determines if a single
bit error has occurred in either byte.
The transmitted parity and the regenerated parity agree.
Therefore the technique of parity can detect only an odd
number of errors.
In the circuit of Figure 23, parity is generated and checked
in the same devices - the 74S280 pair. Should a parity
error occur in either the high or low byte (or both) the error flip-flop is set, causing an interrupt to the 8086 to occur. When the 8086 responds with INTA (interrupt acknowledge) the flip-flop is reset. INTA also enables the
74S244 which gates the interrupt number onto the data
bus. The interrupt request signal to the CPU indicates a
memory error has occurred. The nature of the interrupt
procedure is heavily dependent on the user application,
but typically ranges from retry or recovery routines to
simply turning on the parity error light and proceeding.
Consider the two bit data word whose value is "01".
Exclusive-NORing the two data: bits generates a parity
bit which causes the encoded word to have odd parity:
C=O(j;)1
c=o
The encoded word becomes:
Generated Parity Bit
Data
01
o
Assume that an error occurs and the value of the word
becomes "110." Stripping off the parity bit and
generating a new parity bit:
transmitted parity = 0
transmitted word = 11
One other software consideration for this circuit is the
requirement to initialize all the memory to a known
state. This initialization is needed to properly encode all
the memory to even parity. This is typically done upon
power-up by writing zeros into all memory locations
prior to program storage.
New parity of transmitted word = I (j;) 1 = I; generated parity oF transmitted parity.
In summary, single bit parity will detect the majority of
errors, but cannot be used to correct errors. Using parity
introduces a measure of confidence in the system.
Should a single bit error occur, it will be detected.
Note that the error could have occurred in the parity bit
and the final result would have been the same. An error
in the encoding bit as well as in the data bits can be
detected.
For a detailed treatment of error detection and also
techniques for error correcting, refer to Intel application
notes AP-46, "Error Detecting and Correcting Codes
Part #1," and Application Note AP-73 , "ECC #2
Memory System R~liability ~ith Err~r Correction."
Although parity detects the error, no correction is possible. This is because each valid word can generate the
same error state. Illustration of this is shown in Table
10.
Table 10. Possible Errors
Possible Correct Word
with Parity
Single Bit
Error
00 I
1 1 I
o1 1
o1 1
010
01 1
4.5 Alternatives to '8203 Refresh
Control Designs
There are essentially four choices available when selecting a technique for refresh control circuitry. These are:
Separate controller
CPU Hardware Control
CPU Software Control
Circuitry Internal to the RAM
Each of the errors is identical to the others and reconstruction of the original word is impossible.
Figure 24 is an implementation of a separate controller
design. This is a typical non-LSI version that requires II
TTL packages, an 8282A octal latch, a 3242 address
multiplexer/refresh counter, two bidirectional bus
drivers, an 8212 octal latch and two active delay lines.
Parity fails to detect an even number of errors occurring
in the word. If a double bit error occurs, no error is
detected because two bits have changed state, causing
the weight of the word to remain the same.
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Nothing is gained by using discrete packages where a
LSI device can be designed in. The plethora of TTL does
require a larger engineering effort exemplified by the circuit complexity and timing analysis for this circuit
(Figure 25). In terms of performance, the extra engineering effort can be fruitless - the CPU in this example is
forced into the HOLD condition every time a refresh cycle occurs, even 'if the memory is not being accessed.
This waiting period lasts 1.23 microseconds for every
refresh cycle performed. Contrast this with the 8203 circuit which runs without WAIT states (unless a refresh
cycle is in progress when the CPU requests a memory access, in which case one WAIT state is inserted). The advantages of using the 8203 should be obvious by now.
usage of such a system however, precluding this type of
design in many applications.
To cite a few disadvantages:
• CPU must run continuously - no single step,
HOLD, or extended WAIT states
• Multiprocessor operation is difficult
• CPU must always participate in memory operations
CPU software control of refresh is another alternative.
This approach increases software development and
maintenance costs and may not be offset by the very low
or no hardware overhead for refresh. One method requires real-time analysis of all modules and possible
directions of the program, with branch-to-refresh instructions included in all paths so that a refresh procedure is executed at least every 2 ms. An option on this
technique requires a single interrupt time, which, when it
times out, interrupts the CPU, causing it to revert to the
burst refresh software routine.
Additional hardware closely coupled to the CPU timing
refresh for the microprocessor operation is one alternative to 8203 design. Some implementations include the
extra hardware within the microprocessor; rendering a
low cost, simple design. Wide restrictions govern the
"
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ENDI
END BURSTREF;
1* MAIN *1
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CALL BURSTREF;
ENDI
END REFRSH;
Figure 26. PlM·86/ASM·86 Burst Refresh, Sheet 2 of 2
3"95
intJ
AP·133
F = Frame rate of 60 Hz
R = Number of pixel clock times allowed for
horizontal retrace time = 160 (Usually
empirically determined. This number establishes the width of the margins on the
left and right sides of the CRT display.)
One last technique for refresh control exists that doesn't
fit into any of the above catagories and is worth bringing
to light. Its use is heavily application dependent, hence
has the most severe limitations, but if it meets the design
requirements, its the most cost effective of all. The
memory must be configured so that all row addresses
will be strobed within 2 ms. Figure 27 is a block diagram
of an application where this is possible since successive
memory access addresses are predictable and defined.
The circuit depicts a simpified graphics terminal display
memory interface. Assuming a requirement of a
512x512 display resolution, the memory array is arranged as two rows of eight 2118 devices. During each
read cycle, one byte is loaded from the memory into the
shift register and is serially clocked out as video. A single
RAS is common to the array and 00 is decoded to each
row. This configuration simultaneously refreshes one
row while reading data from the other row. A disadvantage of this arrangement is additional power supply and
decoupling requirements, since one row is always making a transition to active current (~I A) while the other
draws refresh cycle current (~IR)' Refer to Section 6.3.4
on decoupling for calculations. The following is determined:
Memory ,Cycle Rate = Byte read rate of the memory
=2.68 MHz
21.450 MHz
Meye (Hz) =
8
= 2.68 MHz
pixel rate
pixels/byte
1
Tcye = 2.68 MHz = 373 ns/cycle
The 2118-15 meets this Tcye cycle time requirement.
Since the memory array is sequentially addressed, the
memory is automatically refreshed every 128 consecutive cycles.
Checking refresh timings: 128 cycles x 373 ns/cycle =
47.74 microseconds between total refresh for each
device, easily within the 2 ms specification.
Pixel Clock (Hz) = (N + R) • L • F = 21.450 MHz
where N = Number of displayed dots per line = 512
L = Number of horizontal lines per frame
= 532 (512 visible lines + 20 line times allowed for vertical retrace)
The worst case refresh occurs during vertical retrace
time when:
retrace time = 31.3 microseconds/line x 20 lines =
627 microseconds
rllll-]
OSC
PIXEL CLOCK
I
VIDEO
MEMREQ
-
-f---
RASTER
TIMING
AND
VIDEO
CONTROL
VIDEO ADRS BUS
R~ADY
!-HZ BLANK
C/V
!-VBLANK
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MEMORY
ARRAY
=>
2 ROWS 2118
CPU
ADDRESS
BUS
SHIFT
REG.
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RAS
CPUNIDEO BUS SELECT
CAS,
CAS,
' - - - ROW/COL
TIMING OENERATOR
Figure 27. Graphics Terminal Memory
3·96
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VIDEO
Ap·133
worst case refresh rate = 627 microseconds + 47.7
microseconds = 674.7 microseconds, still well within
the 2 ms specification.
and data hold time of a flip-flop arbiter. This is a major
problem in purely asynchronous designs.
5.2 System Block Diagram
Writing is performed during horizontal or vertical retrace. More efficient designs would interleave memory,
eliminating the processor being in WAIT mode until the
memory is open. Here, and in some other limited applications, refresh can occur automatically by design,
and with no software or hardware overhead.
Figure 30 is a block diagram of the basic functions required for this system; refresh interval timer, refresh address counter, arbiter synchronization, address multiplexingand timing generation. Included also in the
diagram are the memory and CPU status decoders, data
latches and transceivers, bus control and clock generation.
5 10 MHz NO·WAIT STATE SYSTEM
The function of the refresh interval timer is to place requests for refresh cycles, distributed in approximately 15
microsecond intervals, so that each row of the memory
devices receives a refresh within 2 milliseconds. This
timer is comprised of two four-bit synchronous binary
counters and two flip-flops. The timer circuits divide the
10 MHz system clock by 150, then latches the count
carry bit to hold until recognized, through the arbiter,
by the refresh latch.
For fast high performance microprocessors such as the
10 MHz 8086, an LSI controller for dynamic RAM interfacing is unacceptable, due to the requirement for
WAIT states and resultant impact on performance.
Until faster LSI controllers appear, discrete controller
designs are required. In the example that follows, high
performance design techniques are coupled with Intel
high performance RAMs to yield a to MHz no-WAIT
state 808612164A system.
The key requirements are:
ALE to data in:
READY response:
2164A tRAC
The refresh address counter generates the refresh addresses that are submitted to the address multiplexer
during a refresh cycle. The counter is incremented once
at the end of each refresh cycle to update the refresh address. The outputs are wire-ORed to the microprocessor
address bus and are active only during a refresh cycle, at
which time the current count is presented to the address
multiplexer as the refresh address.
219 ns
89 ns
150 ns
The solution and implementation that follows, configures the 8086-1 in max-mode, incorporates a synchronous arbiter while providing a quasi-synchronous
refresh (refresh that is synchronous to the system clock,
but not to the microprocessor).
Timing generation for the memory array proauces the
control signals for the address multiplexer and the gating
signals that provide for the properly timed arrival to the
memory of RAS, CAs, and addresses. In this design example, it is essentially a delay circuit with variable taps
to permit fine tuning of the memory inputs so as to allow
no-WAIT states by the microprocessor for a memory cycle. The strobe used to latch valid data from the memory
is also provided by the timing generator.
5.1 System Refresh
Rather than being constrained to the design configurations of purely synchronous or asynchronous refresh arbitration, a quasi-synchronous scheme was chosen taking advantage of the benefits of both, and avoiding
some of the drawbacks of implementing either one exclusively. Synchronizing the refresh arbitration to the
system clock ensures that its operations are inherently
and closely coupled to CPU operation and allowing
critical· timing edges to always be predicted through
worst case analysis. However, unlike totally synchronous systems, if the CPU in this example were to
enter a HOLD, HALT, or otherwise stopped state,
refresh cycles would continue to keep valid data in the
memory, independent of the CPU operation. Also, synchronization of refresh requests to the system clock
make the task of the arbiter very easy. Memory cycle requests and refresh cycle requests never occur at the same
time (Figures 28 and 29, timing analysis). As a result,
there is no chance that a random cycle request can arrive
in a narrow time window that would violate data setup
The 2164A dynamic RAM requirement of multiplexed
row and column addresses is met by the address
multiplexer. Here, the proper selection and transmission
of row/refresh or column addresses is accomplished by
contrJll of the select line timing generation circuit.
In this design (Figure 31), arbitration is easily performed, i.e., once a cycle type is latched into its respective flip-flop (refresh latch or memory access latch) its
request is presented to the input of an AND gate that will
allow the request to pass through if a request of the other
type is not currently in execution. Once the request
passes the AND gate, the hardware is committed to a cycle of the requesting type and blocks any subsequent request until the current cycle is complete.
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For example, suppose the CPU status decoder indicates
a memory cycle is pending and there is no refresh cycle in
progress. The status decoder outputs a bit indicating this
condition to the memory access latch and is latched on
the falling edge of ALE (address latch enable). After
propagating through the latch, this latched memory access bit is presented to the input of AND gate B (where it
will carry through the gate initiating a memory cycle,
since there is no refresh cycle in progress) and its complement to AND gate A where it will block a refresh request
from propagating through until the memory cycle is
complete. As another example, assume that a refresh cycle is pending. The refresh timer times out, latches its
output signal into the refresh request latch which subsequently presents this latched refresh request to the input
of AND gate A. Here the signal is either held up or passed through depending upon the current CPU status.
Assuming that there is no memory cycle in progress or
that one has just ended, the AND gate passes the refresh
request through to the refresh cycle latch, committing
the hardware to initiate a refresh cycle and blocking any
memory request that may occur until the end of the
refresh cycle.
The sole purpose of the CPU status decode block is to
inform the arbiter (as soon as possible) as to whether or
not the pending machine cycle is going to be a memory
cycle.
The bus controller provides the memory write command
(MWTC) and is steered to a high and/or low byte write
by AO and BHE in the byte control block. Address latch
enable (ALE) used for latching valid addresses off the
multiplexed bus, data enable (DEN) used to enable the
data transceivers, and data transmit/receive (DT /R)
used to control the direction of the data transceivers, are
all provided by the bus control block.
5.3 Schematic
Refer to the logic schematic (Figure 31) and to the block
diagram in Figure 30, during the following discussion involving the conversion of logic blocks to TTL logic.
The refresh interval timer is comprised of devices P2 and
P4, two 74LSI63 four-bit synchronous binary counters,
and one FIF from P14, a 74S74 flip-flop. The counters
are cascaded and free-running, being incremented by the
system clocks so as to output a refresh request pulse
every 15 microseconds. This pulse is stored by P27 FIF,
the refresh request latch, which is part of the arbiter.
The refresh counter is a pair of AM25LS2569 three-state
binary up/down counters (located at P17 and P18) that
sequence from 0 to 28-1 (255) and then roll over to start
again. The MSB (most significant bit) of the counter is
unused. With the devices' clock input tied to their OE,
the counters are automatically incremented at the end of
a refresh cycle when the outputs are switched off the address bus by OE going high. This sets up the count to the
next refresh address.
Memory address multiplexing is comprised of a pair of
74S158 quad 2:1 multiplexers (PI9, P20). Inverted data
output devices were selected because of their shorter
propagation delay. The arrival of addresses to the
memory is one of the tight timing constraints for zero
WAIT states. The select line is controlled by the timing
generator during a memory read or write cycle and is
used to switch from row to column addresses at the appropriate time. During a refresh cycle, the select line
does not change; thus, only the refresh addresses, which
are wire-ORed to the row addresses are presented to the
memory array.
The arbiter in this system is designed with two 74S74
FIFs, one from Pll and the other from P27, and two
gates: a 74S11 AND gate at P25 and a 74S00 NAND gate
at P22. As previously discussed, the arbiter makes the
decision of whether to run a memory R/W cycle or a
refresh cycle, then commits the hardware to initiate the
cycle decided upon. Classically a difficult choice, the
task is greatly simplified by the quasi-synchronous
nature of this design. Memory and refresh cycle requests
never occur at or near the same time and the worst case
data setup and hold times at each F /F are easily predicttable and are designed to avoid violations of these
specifications. The relatively simple nature of this arbitration circuit is demonstrated by the small device
count and simplicity of the method involved.
The refresh sync and ready sync blocks generate several
control signals for a number of functions that must exeecute to carry a refresh cycle to its natural end, all in
synchronization with the system clock. The first signals
generated are address disable - used to switch the CPU
address latches into a high impedance state, and access
block - used to block a memory cycle request at AND
gate B. On the next rising clock edge a control signal is
output that will switch the refresh address counters onto
the address bus and enable a string of shift registers that
comprise the ready sync to start shifting the READY bit
through. Then, on the next rising edge of the clock, the
refresh cycle latch is cleared, and finally on the falling
edge of the clock the refresh signal is output from the
ready sync block which is used by the RAS select block
to enable all the RAS lines at once, simultaneously performing refresh on all four memory rows.
The status decode block is implemented with two NAND
gates from 74S00 at 1>26 and one NAND gate from P22.
Low power Schottky devices were required because of
the limited (2 rnA) drive capability of the 8086 status
3-102
inter
Ap·133
lines. Through observation of the truth table fQr the status
bits SO-S2 on the schematic and the following logic, it is
apparent that NAND gate P26, pin 6 goes low during
memory read, memory write, or instruction fetch cycles.
This active low memory cycle status bit is latched into the
access latch on the trailing edge of the clocked ALE (from
S74 F IF at PI I) and informs the arbiter that this memory
cycle is in progress. For any other type of CPU cycle,
device P26, pin 6 is high, which enables NAND gate P22,
.pin 5 to allow the next rising edge of the clock to preset
the memory access latch, indicating to the arbiter that this
is not a memory cycle.
speed microprocessor memory requirement, fulfilling
the needs at all performance levels. In particular, the
2164A DRAMs used in this 10 MHz design easily conform to the rigid requirements of this high performance
system.
6 HIGH PERFORMANCE SYSTEM
DESIGN CONSIDERATIONS
Designing a high performance, high speed memory
system requires consideration of the following areas:
1. Skew
2. Propagation Delay
3. General Circuit Design Techniques
4. Worst-case timing analysis
The bus control block functions are executed with an
Intel 8288 bus controller. In this circuit, ALE, DT IR,
DEN and MWTC are all generated at P5 from system
clock and CPU status bits inputs. The MWTC is used
for the write pulse to the memory array, being directed
to the higher or low byte by the pair of 74S32 gates at
P24 which comprised the U/L WE byte control block.
ALE is transmitted to Pl1latch control (ENG) input of
the 74S373 three-state address latches P6-P8, thus latching valid addresses from the multiplexed CPU bus.
DT/R and DEN are wired to pins I and 19 respectively
of the pair of 8-bit 74LS245 data transceivers at P9 and
PIO, with DT/R controlling the direction of data flow
through the devices and DEN used to enable the device
output drivers in the direction selected by DT IR.
6.1 Skew
Skew is the difference between maximum and minimun
propagation delay through devices in a parallel path.
For example, refer to Figure 32. Here signal A and signal
B propagate through the same number and types Of
gates, each transversing a parallel path. For both signals
the total mimimum delay is 6 ns and the total maximum
delay is 16 ns. However, diagramming the worst case
(Figure 33), the skew between these signals can be as
much as 10 ns. This time (skew) adds directly to the
system accessl cycle time.
Timing generation for memory array related signals are
all derived from a STTLDM-595* active delay line at
P28. Activated only during a memory cycle via a single
input from the arbiter, this one pulse is delayed 25 ns to
become the ACCESS ENABLE signal (the source of
RAS), 50 ns to enable the flow through memory data
latches, 60 ns before switching the address multiplexer
and finally delayed 75 ns before becoming the source of
CAS.
Capacitive loading of the STTL drivers will cause rise
time degradation in the memory array, and will contribute to skew, caused by heavily loaded versus lightly
loaded sigmlls. Figure 34 displays the effects of
capacitive loading of the Schottky TTL. Obviously skew
needs to be minimized.
The ACCESS ENABLE line is connected to P5 of the
74S138 three-to-eight decoder located at P15. Configured as a two-to-four decoder by grounding the
C-input and placing high order addresses AI7 and AI8
on the A and B inputs, PIS selects which of the four
memory rows will receive a RAS signal. Once a proper
output is selected, the ACCESS ENABLE signal is
directed through the 74S138 to the correct row after being buffered through a 74S08 at P29. Note that one input of all the gates at P29 RAS buffers are connected
together to the refresh signal. This allows simultaneous
strobing of all memory RAS during a refresh cycle.
SKEW-DIFFERENCE BETWEEN MAXIMUM AND
MINIMUM PROPAGATION DELAY THROUGH
DEVICES IN A PARALLEL PATH.
SIGNAL "A"- _____ ~ SIGNAL "A"
~DELAYED
DELAY MIN -
2 ns
DELAY MAX -
~
ns
2 ns
6 ns
2 ns
S ns
SIGNAL"S" ___ ~SIGNAL "ii"
~DELAYED
It is evident from the examples presented that the Intel
2118 and 2164A high performance DRAMs match any /
DELAY MIN DELAY MAX -
2 ns
5 ns
2 ns
6 ns
2 ns
S ns
Figure 32. Skew - Variations Between MaxiMin
Propagation Delay
• Available from EC2, San Luis.Obispo, California
3·103
Ap·133
Ons
SIGNAL "A"
4ns
8ns
12ns
16ns
20ns
~_ _ _ _ _ _ _ _ _ _ _ _ __
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6 ns (MIN)
I
PATH "At! DEVICES
. OPERATING AT
MIN.
SIGNAL "A"
(DELAYED) - - - -........ ,
SIGNAL "8"
~-+l----------16 ns ( M A X ) = = t - - - - -
SIGNAL "8"
(DELAYED)
PATH "8" DEVICES
OPERATING AT
MAX.
!
1
~
SKEW
~,
SKEW:
=MAX-MIN=16ns-6ns
SIGNAL "A" - TO -= 10 ns l ISKEWI
SIGNAL "8"
•
ADDS DIRECTLY TO SYSTEM ACCESS/CYCLE TIME
Figure 33. Skew - Adds Directly to System Access/Cycle Time
• Drive address and clocks from a common area on
the P.C.B, to avoid circuit board trace skew due to
unequal lengths of signal distribution (Figure 35).
• Localize the timing generation
SCHOTTKY TTL CAPACATIVE LOADING EFFECTS
74500 SERIES
NO TERMINATION
4.0
TTL INPUT
TTL INPUT
o~
3.0
LOAD
CAPACITANCE
2.0
·····100 PF
- - - 200 PF
-300PF
6.2 Propagation Delay
Propagation delay must be determined in the critical
paths to guarantee the design goals of circuit optimization and maximum performance. The following rules
are generally used to determine propagation delay'
through the TTL devices:
>
1.0
• t prop MAX = Data Book maximum
• t prop Typical = Data Book typical
• t prop MIN = Y2 Data'Book typical
0.0 '--_-'-_---'_ _-'-_-'--.-J'--_-'-_--'_-----'
1Q
10
20
30
0
20
30
NS
Capacitive loads add to the propagation delays specified
in the data books~ The additional delay can be calculated
in the following manner:
Figure 34. Schottky TTL Capacitive
Loading Effects
• Additional Delay = .Dc X (C]oall - Cspec), where
C]oad
sum of all input capacitance plus PCB
traces ("" 2 pF/in),
specified capacitance of the driver, and
C spec
the derating factor for the driver logic
Dc
family
Schottky TTL = 0.5 ns/pF
Low power Schottky TTL
= ,1 ns/pF
High current Schottky TTL
= .25 ns/pF
TTL = .75 ns/pF
The goal to minimize skew is achieved by observing the
following guidelines:
• Select logi~ gates for minimum delay per function
• Place parallel paths in the same package (Device to
device skew within the same package = .5 ns max
for STTL, 2.0 ns max for high. current drivers, i.e.,
74S240.)
• Balance the output loading to equalize the
capacitive delays
• Use delay lines with tight t prop and'trise tolerances
(± 1 ns)
3·104
Ap·133
LEFT
ADDRESS
DRIVERS
112 OF
MEMORY
ARRAY
I
DATA BUFFER
RIGHT
ADDRESS
DRIVERS
112 OF
MEMORY
ARRAY
I
I
DATA BUFFER
I
CONTROL
&
TIMING
I
I
CARD EDGE CONNECTOR
Figure 35. Memory Board Layout
6.3 Circuit Design Techniques
Optimum circuit design demands attention to the
physical details of a 2164A memory system. A properly
produced layout will minimize board area while yielding
wider operating margins on timing and power supply requirements. The key areas of consideration are:
I. Ground and power gridding
2. Memory array/control line trace routing
3. Control logic centralization
4. Power supply decoupling
RA:"~RAM
-=-
B
N
'--<~--
I
I
Figure 36. Equivalent Circuit for Distribution
6.3.1 GROUND AND POWER GRIDDING
LO
The power and ground network do not appear as a pure
low resistance element, but rather as a transmission line
because the current transients created by the RAMs are
high frequency in nature. The RAMs are the lumped
equivalent circuits of the power and ground transmission lines are shown in Figure 36.
The characteristic impedance of a transmission line is
shown in Figure 37 A. By connecting two transmission
lines in parallel, the characteristic impedence is halved..
The result is shown in Figure 37B.
(Al
~Lo
3-105
Co
=
INDUCTANCE/UNIT LENGTH
Co
= CAPACITANCE/UNIT LENGTH
Zo
=
J ~:
~
(B)~
I
I
Transient effects can be minimized by adding extra circuit board traces in parallel to reduce interconnection inductance.
I
Zo
Lo
Co
Figure 37. Transmission Line Characteristic
Impedance
AP·133
Extrapolati<>n of this concept to its limit will result in an
infinite number of parallel traces, or an extremely wide
low impedance trace, called a plane. Distribution of
power and ground voltages by plane provides the best
distribution, however correct gridding can effectively
approximate the benefits of planar distribution by surrounding each device with a ring of power and ground
(Figure 38).
I
2164A
~
I
~
I
~
I
2164A
6.3.2 MEMORY ARRAY/CONTROL
LINE ROUTING
Address lines need to be kept as short and direct as possible. The lone serpentine line depicted in Figure 40 should
be avoided, since the devices farthest away from the
driver will receive a valid address at a later time than the
closer ones. A better way to route address lines is in a
comb like fashion from a central location as depicted in
Figure 41. Routing control and address signals together
from a centralized board area will also minimize skew.
~
ADDRESS LINE LAYOUT
8 DEVICES
I
~
I
\ I
I
2164A .
~
I
\ I
I
~
•
_5
I
~
I
~
\ I
\
~
I
2164A
~
ADDRESS
TWO SIDED CARD
-
•
I
DRIVER
VERTICAL TRACES ON COMPONENT SIDE
HORIZONTAL TRACES ON SOLDER SIDE
TOTAL lENGTH OF LINE - 20'
MAINQROUND BUS OR INTERCONNECTION TO TTL
CONTROL. ADDRESS. DATA BUFFERS
Figure 40. Unacceptable Address Line
Routing (Serpentine)
Figure 38_ Recommended Power Distribution
- Gridding
Improper ground and power gridding can contribute to
excess noise and voltage drops if not properly structured. An example of an unacceptable method is
presented in Figure 39. This type of layout promotes accumulated transient noise and voltage drops for the
device lqcated at the end of each trace (path).
ADDRESS LINE LAYOUT
8 DEVICES
ADDRESS
/ DRIVER
Figure 41. Recommended Address Line Routing
Allow for proper termination of all address and control
lines, since a P.C.B. trace becomes a transmission line
when:
2tpd ~ tr or tf
where: tp = propagation delay down the line
t r = rise time
t f = fall time
Figure 39. Unacceptable Power Distribution
3-106
AP·133
The maximum unloaded line lengths not displaying
transmission line characteristics are listed in Table 11.
The values assume propagation delay of 0 = 1.7 ns/ft.
Table 11. Transmission Characteristics
Logic
Family
Rise
Time
Fall
Time
54174L
54174
54H/74H
54LS174LS
54S174S
10K ECL
100KECL
14 - IS ns
6 - 9 ns
4- 6 ns
4- 6 ns
I.S - 2.S ns
1.5 - 2.2 ns
0.5 - 1.1 ns
4 - 6 ns
4 - 6 ns
2 - 3 ns
2 - 3 ns
1.6 - 2.6 ns
1.5 - 2.3 ns
0.5 - 1.1 ns
Max.
Length
14.1
14.1
7.0
7.0
5.6
5.3
I.S
inches
inches
inches
inches
inches
inches
inches
The maximum length of a loaded transmission line is:
Co
2Co
where CD = Capacitive load/unit length
and Co = Capacitance/unit length
6.3.3 CONTROL LOGIC CENTRALIZATION
Memory control logic should be strategically located in a
centralized board position to reduce trace lengths to the
memory array (Figure 35).
Long trace lines are prone to ringing and capacitive
coupling, which can cause false triggering of timing circuits. Short lines minimize this condition and also result
in less system skew.
A practical memory array layout is presented in Figure
42. Typically" this pattern and its "mirror image" are
placed on each side of the memory control logic for a
practical memory board design.
6.3.4 POWER SUPPLY DECOUPLING
For best results with the 2164A, decoupling capacitors
are placed on the memory array board at every device
location (Figure 42). High frequency 0.1 p,F ceramic
capacitors are the recommended type. In this arrangement each memory is effectively decoupled and the noise
is minimized because of the low impedence across the
DECOUPLING
CAPACITOR
Dour= •
NOTE 1 FUTURE ADDRESS EXPANSION
NOTE MEMORY DEVICE SPACING IS 0 425"
TRACES ARE
so MIL
Figure 42. 2164A Memory Array P.C. Board Layo~t
3·107
AP·133
circuit board traces. Typical Voo noise levels for this array are less than JOO mY.
A large tantalum capacitor (typically one 100 /IF per 32
devices) is required for the 2164A at the circuit board
edge connector power input pins to recharge the 0.1 /IF
capacitors between memory cycles.
Decoupling is of considerable importance in circuit
design in order to lI1inimize transient effects on the
power supply system. In order to determine the values
for proper decoupling capacitors, the required amount
of charge storage for a capacitor must first be determined in the following manner:
Q = AIAT
where: Q = charge in coulombs
AI = change in current is amperes
AT = change in time is seconds
and: AV = Q/C
where: AV = voltage change in volts
and C = capacitance in farads
Assuming the following system parameters:
5 rnA to 55 rnA current switch for regular cycle
5 rnA to 45 rnA current switch for refresh cycle
1 microsecond bulk decoupling response time
260 ns cycle time
,v. of devices selected (one of four rows)
An example calculation proceeds as follows:
Q = (45-5 rnA) (.3 /lsec) + V. (55-5) rnA (.7 /lsec)
Q = 20.75 nanocoulombs
Bulk decoupling requirements are determined in a similar way:
Assuming the following:
50 flSec power supply response time
15.6 flsec refresh rate
Thre~ refresh cycles/50 flsec period
IOD standby=5.77 rnA
I
00
STDBY = 45 rnA (.3 flsec) + 5 rnA (15.3 /lsec)
15.6 flsec
=5.77 rnA
An example calculation with V. devices active proceeds
as shown:
Q = [50- (3) (.3)] flsec X49.23 rnA (V.) =604 nC
~~ =6.0 flF device
i'f V=I00 mV then C= :
if V =500 mV then C= : : ~~ = 1.2 flF device
The data shown in Table 12 defines the decoupling requirements of2164A-15 and 2118-15 dynamic RAMs for
a 300 ns cycle time over various device selections for a
given percentage.
Cycle time has a downward scaling effect on the average
operating current according to the following equation:
IooAVE =
[1
CR~~~~:~:~ing») ]
002 x
, [
if VOD is restricted to 100 mV (20/0) then
+ IDDl
nC
F/'
C = 20.8
100 mV = .21 /l DeVice
(
X
1-
tRC (spec)
)]
tRC (operating)
tRC (spec)
At minimu!ll cycle time, --.,--..,.-- 1,
tRC (operating)
if Voo is allowed to 500 mV (10%) then
20.8 nC
.
c= 500 mV = .042 flF/Devlce
so that worst case IOOAVE =ioD2' but as the cycle time
increases, IOO AVE approaches the standby current,
Table 12. Decoupling Chart
% Selected
Devices
AVoo=2%
AVoo=10%
Co
Ca
Co
Ca
100
0.47
24.0
300 ns
0.11
4.8
50
0.29
12.0
300 ns
0.059
2.4
2164A-15
2118-15
Cycle
Time
25
0.21
. 6.0
300 ns
0.042
1.2
12.5
0.16
3.0
300 ns
0.033
0.6
100
0.19
9.2
300 ns
0.D38
1.84
50
0.10
4.6
300 ns
0.019
0.92
25
0.064
2.3
300 ns
0.013
0:46
12.5
0.048
1.15
300 ns
0.01
0.3
3-108
}
0.1 flfd/device will work if l4
devices are active at one time .
+ 100 flfd every 32 devices.
}
+ 27 flF every
32 devices (assuming l4 of devices active)
0.1 flF /2 devices
Ap·133
becoming 6.3 mA @ 10,000 ns cycle time. Figure 5 in the
2164A data sheet depicts this scaling effect. Be sure to
use the correct IDD value based on specific worst case
cycle time when computing specific decoupling requirements.
6.4 Timing Analysis the Worst Case
Determining
Once the control logic is designed, worst case system
delays must be determined to guarantee proper circuit
operation. There are two ways to perform these calculations:
1. A statistical worst case analysis (or the Monte Carlo
method) which assumes that aU devices probably
won't be in their worst case condition at the same
time.
It is determined by the following formula:
STATISTICAL WORST CASE
=..jE(A)2 + (B)2 + (C)2 MAX STTL DELAYS
+ TYPICAL STTL DELAYS
+ .jE (A)2 + (B)2 + (C)2 SKEW DELAYS
+E DELAYS DUE TO CAPACITIVE LOADING
+ MAXIMUM DELAY ACCESSING MEMORY
DEVICE
WHERE (A), (B) OR (C) = MAX-TYP OR TYP-MIN
In summary, the following rules and guidelines apply to
worst case analysis:
I. All propagation delays are from the industry TTL
books.
Max = Data book maximum
Typ = Data book typical
Min = Yz Data Book Typical
2. Skew device to device in same package = 0.5 ns Max
for Schottky TTL and 2 ns for 74S24O.
3. STTLDM-595 is a special delay line with active outputs. Propagation delay = ± '1 ns per tap (Le., 75 ±
1 ns). (10 MHz system.)
4. Capacitive loads add 0.5 ns/pF to propagation delays specified in device spec (Le., 74S04 is specified at
5.0 ns Max @ 15 pF. At 25 Pf propagation 4elay is
5.5 ns) Schottky TTL input capacitance is 3 pF. PCB
traces are 2 pF/inch.
5. PCB etch delay adds little or no skew to array address/control timing signals. It adds 4 ns, however,
in the overall access time'data path.
6. Timing components are immediately adjacent tb
each other, making PCB etch delays in delay timing
chain negligible (exception is timing tap used to ter'
minate delay line bitch).
7. SUMMARY
2. A true worst case analysis, using specified maximum
and minimum delays for peripheral circuits plus all
delays due to capacitive loading from device inputs
and distributive capacitance in PC board etched con
ductors. The following formula appears here:
The Intel 2164A and 2118 DRAMs meet all microprocessor system requirements, offering high density,
speed, low power and ease of use. Follow th~ syste~
design guidelines presented to create a harmoIUous microprocessor memory design.
WORST CASE
= E MAX STTL DELAYS + SKEW DELAYS
(pERIPHERAL DEVICES)
+ E DELAYS DUE TO CAPACITIVE LOADING
(INPUTS + P.C.B. TRACES)
+ MAXIMUM DELAY ACCESSING MEMORY
DEVICE (T RAC OR T CAd
Since the statistical approach can be justified only in
large systems with hundreds or thousands of compotients, the timing calculations used in all of the
previous examples are based on a true worst case
analysis. Capacitive delay is formulated from the equations in Section 6.1.2.
8. REFERENCES
Application of the Intel 2118 16K Dynamic
RAM
, AP-131 2164A 64K Dynamic RAM Device Description
AP-92A Interfacing, Dynamic RAMs to iAPX 86/88
Systems Using the Intel 8202A and 8203
Brror Detecting and Correcting Codes Part #1
AP-46
AP-73
BCC #2 Memory System Reliability with Brror
Correction
AP-75
3·109
APPLICATION
NOTE
Ap·97A
April 1982
3-1'10
ORDER NUMBER' 210398·001
AP·97A
Table 1. Comparison of Intel Static and
Dynamic RAMs Introduced during 1981
INTRODUCTION
The designer of a microprocessor-based system has two
basic types of devices available to implement a random
access read/write memory - static or dynamic RAM.
Dynamic RAMs offer many advantages. First, dynamic
RAMs have four times the density (number of bits per
device) of static RAMs, and are packaged in a 16-pin
DIP package, as opposed to the 20-pin or larger DIPs
used by static RAMs; this allows four times as many
bytes of memory to be put on a board, or alternatively,
a given amount of memory takes much less board space.
Second, the cost per bit of dynamic RAMs is roughly
one-fourth that of statics. Third, static RAMs use about
one-sixth the power of static RAMs, so power supplies
may be smaller and less expensive. These advantages are
summarized in Table 1.
2164·15
(Dynamic)
Density
(No. of bits)
No. of pins
Access time (ns)
Cycle time (ns)
Active power (rna)
Standby power (rna)
Approx. cost per bit
(millicents/bit)
300
60
5
45
16K
20
70
70
125
40
250
In addition, dynamic RAMs may not always be able to
transfer data as fast as high-performance
microprocessors require; wait states must be generated
in this case. The circuitry required to perform these
functions takes up board space, costs money, and consumes power, and so detracts from the advantages that
make dynamic RAMs so appealing. Obviously, the
amount of support circuitry should be minimized.
On the other hand, dynamic RAMS require complex
support functions which static RAMs don't, including
•
•
•
•
64K
16
150
2167·70
(Static)
address multiplexing
timing of addresses and control strobes
refreshing, to prevent loss of data
arbitration, to decide when refresh cycles will be
performed.
The Intel 8202A and 8203 are LSI dynamic RAM controller components. Either of these 4O-pin devices alone
does all of the support functions required by dynamic
RAMs. This results in a minimum of board space, cost,
and power consumption, allowing maximum advantage
from the use of dynamic RAMs.
LOG2lCOSTl
CONTROLLER
CS LOGIC
4K
8K
16K
32K
64K
128K
LOG2lRAM SIZE] (K BYTES)
Figure 1. Implemented Cost of Static vs. Dynamic RAM
3-111
AFN: 02200A
AP·97A
Figure 1 shows the relative cost of static and dynamic
RAM, including support circuitry, as a function of
memory size, using the Intel 8202A or 8203. For any
memory larger than 16KBytes, the dynamic RAM is less
expensive. Since the cost of the dynamic RAM controller is relatively independent of memory size, the cost
advantge for dynamic RAM increase's with increasing
memory size.
This Application Note will describe the techniques of interfacing a dynamic RAM memory to an iAPX-86 or
iAPX-88 system using either the 8202A or 8203 dynamic
RAM controller. Various configurations of the 8086
and 8088 microprocessors, and those timings which they
satisfy, are described. The Note concludes with examples of particular system implementations.
DYNAMIC RAMS
This section gives a brief introduction, to the interfacing
requirements for Dynamic RAMs. Later sections will
describe the operation of the Intel 8202A and 8203
Dynamic RAM Controllers.
Device Description
The pinout of two popular families of dynamic RAMs,
the Intel 2118 and 2164A, are shown in Figure 2. The
2118 is a 16,384 word by I-bit dynamic MOS RAM. The
2164 is a 65,536 word ,by I-bit dynamic MOS RAM.
Both, parts operate from a single + 5v supply with a
± 100/0 tolerance, and both use the industry standard
, 16-lead pinout.
Addressing
Each bit of a dynamic RAM is individually addressable.
Thus, a 2164A, which contains 216 (or 65,536) bits of information, requires 16-bit addresses; similarly, the
2118, which contains 214(or 16,384) bits, requires 14-bit
addresses.
In order to reduce the number of address pins required
(and thus reduce device cost), dynamic RAMs timemultiplex addresses in two halves over the same pins.
Thus a 2164A needs only 8 address pins to receive 16-bit
addresses, and the 2118 needs only 7 for its 14-bit addresses. The first address is called the row address, and
the second is called the column address. The row address is latched internal to the RAM by the falling edge
of the RAS (Row Address Strobe) control input; the column address is latched by the falling edge of the CAS
(Column Address Strobe) control input. This operation
is illustrated in Figure 3.
Dynamic RAMS may be visual1ized as a twodimensional array of single-bit storage cells arra!1ged
across the surface of the RAM's die. In the case of the
2164A, this array would consist of 28 (or 256) rows and
28 (or 256) columns, for a total of 216 (or 65,526) total
bit cells (Figure 4). This is the source of the "row address" and "column address" terlhinology. Bear in
mind that any given RAM may not be physically implemented as described here; for instance, the 2164A actually contains four' arrays, each one 27 rows by 27
columns.
The two parts are pinout-compatible with the exception
of the 2164 having one extra address inpJlt (A7, pin 9);
this pin is a no-connect in the 2118. Both parts are also
compatible with the next generation of 256K dynamic
RAMs (262,144 word by I-bit), which will use pin 1
(presently a no-connect on both the 2118 and 2164A) for
the required one extra address input (As). This makes it
possible to use a single printed circuit board layout with
any of these three types of RAM.
v,,
CAS
Dour
V••
DIN
CAS
WE
Dour
_As
DIN
WE
As
RAS
A3
A4
As
Ao
Ac
A3
A2
Al
A4
As
RAS
Ao
A2
Al
A741
Voo
Voo
v.,
CAS
Dour
As
A3
A4
As
A7
Figure 2. Dynamic RAM Pinout Compatibility
3-112
AFN.02200A
AP·97A
ADDRESS
COLUMN
Figure 3. Dynamic RAM Addressing
COLUMNS
ROWS
°H
OH
1H
2H
3H
1H
100 H
101H
102H
103 H
2H
200 H
201H
~ 202H
3H
300 H
301H
302H
4H
400H
401H
402H
5H
SOOH
501H
502H
FDOO H
FIJU1H
-.-.....
FEOO H
FE01H
FE02H \
FFOO H
FF01 H
FF02H
203~
I..
"{lHI
FEH
FFH
\1
IFEH
IFFH
19
/
303 (
403~
50y
2FEH
2FFH
\3FEH
3FFH
-=--
""'\
BIT CELL ADDRESS
P
~
~H
nFDFEH
II FEFEH
1\
/1 FFFEH
Figure 4. Bit Cell
-
FCFF H
FDFFH
FEFFH
FFFFH
"Array"
CAS or WE, whichever occurs last. If WE goes active
before CAS (the usual case, called an "early write"),
write data is'latched by the falling edge of CAS. If WE
goes active after CAS (called a "late write"), data is latched by the falling edge of WE (see Figure 5).
Memory Cycles
In this Application Note, we will discuss three types of
memory cycles - read, write, and RAS-only refresh.
Dymanic RAMs may perform other types of cycles as
well; these are described in the dynamic RAM's data
sheet.
Late writes are useful in some systems where it is desired
to start the memory cycle as quickly as possible, to maximize performance" but the CPU cannot get the write
data to the dynamic RAMs quickly enough to be latched
by CAS. By delaying WE, 'more time is allowed for
write data to arrive at the dynamic RAMs.
Whether data is read or written during a memory cycle
is determined by the RAM's WE control input. Data is
written only when WE is active.
.
During a read cycle, the CAS input has a second function, other than latching the column address. CAS also
enables the RAM data output (pin 14) when active,
assuming RAS is also active. Otherwise, the data output
is 3-stated. This allows mUltiple dynamic RAMs to have
their data outputs tied in common. '
During write cycle~, data on the RAM data input pin is
latched internally to the RAM by the falling edge of
3·113
Note that when "late write" is performed, CAS goes active while WE is still inactive; this indicates a read cycle,
so the RAM enables its data output. So, if "late write"
cycles are performed by a system, the RAM data inputs
and data outputs must be electically isolated from each
other to prevent contention. If no "late writes" are performed, the RAM data inputs and data outputs may be
tied together at the RAM to reduce the number of board
traces.
'
AFN' 02200A
AP·97A
\~------'/
.
r---
[\
lOS
IOH
~
~
DOUT
VALID
K
---------------------------<:~________
:>--------------
IN_D_ET_E_R_M_IN_A_T_E___________
B. "LATE WRITE"
\
-WE
~
>-
IOH
VALID
~
DOUT --------:------.-------------------------------------...:-----------------------A. "EARLY WRITE"
Figure 5. Dynamic RAM Write Cycles
Access Times
Each dynamic RAM has two different access times
quoted for it - access time from RAS active (tRAd and
access time from CAS active (tcAd; these are illustrated
in Figure 6. How do you know which to use? This
depends on the timings of your RAM controller. First,
the worst case delay from the memory read command
active to RAS active (tcIV and CAS active (ted must be
determined. Then the read data access time is the larger
of the tCR(Controller) + tRAdRAM) or tcdController)
+ tCAdRAM). An alternative· way to determine
whether to use tRAC or tCAC is to look at the dynamic
RAM parameter for RAS active to CAS active delay,
tRCD. tRcnmax is a calculated value, and is shown on
dynamic RAM data sheets as a reference point 9nly. If
the delay from RAS to CAS is less than or equal to
tRComax, then tRAC is the limiting access time parameter; if, on the other hand, the delay from RAS to
CAS is. greater than tRComax, then tCAC is the limiting
parameter. tRComax is not an operating limit, and this
spec may be exceeded without affecting operation of the
RAM. tRCrftlin, on the other hand, is an operating
limit, and.Jhe RAM will not operate properly if this spec
is violated.
3-114
AFN 02200A
Ap·97A
\
Dour
Figure 6. Dynamic RAM Access Times
Refresh
Unfortunately, if left for very long, the charge will leak
out of the capacitor, and the data will be lost. To prevent this, each bit-cell must be periodically read, the
~harge on the capacitor amplified, and the capacitor
recharged to its initial state. The circuitry which does
this amplification of charge is called a "sense amp".
This must be done for every bit-cell every 2 ms or less to
prevent loss of data.
One unique requirement of dynamic RAMs is that they
be refreshed in order to retain data. To see why this is
so, we must look briefly at how a dynamic RAM is
implemented.
Dynamic RAMs achieve their high density and low cost
mostly because of the very simple bit-storage cell they
use, which consists only of one transistor and a
capacitor. The capacitor stores one bit as the presence
(or absence) of charge. This capacitor is selectively accessed for reading and writing by enabling its associated
transistor (see Figure 7).
Each column in a dynamic RAM has its own sense amp,
so refresh can be performed on an entire row at a time.
Thus, for the 2118, it is only necessary to refresh each of
its 128 rows every 2 ms. Each row must be addressed via
the RAM's address inputs to be refreshed. To simplify
ONE COLUMN
~
}
ONE
ROW
BIT SELECT
LINES
(FROM ROW
ADDRESS
DECODER)
T
v+
T
v+
'----v------'
BIT SENSE LINES
(TO SENSE AMPS)
Figure 7. Dynamic RAM Cell
3-115
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ADDRESS
RAS
X
X
ROW
\
/
DON'T CARE
DOUT
Figure 8. RAS·only Refresh
refresh, the 2164A is implemented in such a way that its
refresh requirements are identical to the 2118; 128 rows
every 2 ms. Some other 64K RAMs require 256 row
refresh every 4 ms.
microseconds for 128 rows) no read or write cycles can
be performed. This severely limits the worst case
response time to interrupts and makes this approach unsuitable for many sy~tems.
Refresh can be performed by a special cycle called a
RAS-only refresh, shown in Figure 8. Only a row address is sent; that row is refreshed. No column address is
sent, and no data is read or written during this cycle. Intel dynamic RAM controllers use this technique.
As long as every row of the RAM is refreshed every 2
ms, the distribution of individual refresh cycles is unimportant. Distributed refresh takes advantage of this fact
by performing a single refresh cycle every 2 ms/128, or
about every 15 microseconds. In this way, the refresh requirements of the RAM are satisfied, but the longest
time that read and write cycles are delayed because of
refresh is minimized. Those few dynamic RAMs which
use 256 row refresh allow 4 ms for the refresh to be completed, so the distributed refresh period is still 15
microseconds.
Any read, write, or read-modify-write cycle also
refreshes the row addressed. This fact may be used to
refresh the dynamic RAM without doing any special
refresh cycles. Unfortunately, in general you cannot be
sure that every row of every dynamic RAM in a system
will be read from or written to every 2 ms, so refresh
cannot be guaranteed by this method alone, except in
special applications.
A third technique for· refresh is called hidden refresh.
This method is not popular in microprocessor systems,
so it is not described here, but more information is
available in the dynamic RAM's data sheet.
Three techniques for timing when refresh cycles are performed are in common use: burst refresh, distributed
refresh, and transparent refresh ..
Burst refresh means waiting almost 2 ms from the last
time refresh was performed, then refreshing the entire
memory with a "burst" of 128 refresh cycles. This
method has the inherent disadvantage that during the
time refresh is being performed (more than 40
The third technique is called transparent (or "hidden"
or "syncronous") refresh. This takes advantage of the
fact that many microprocessors wait a fixed length of
time after fetching the first opcode of an instruction to
decode it. This time is necessary to determine what to do
next (i.e. fetch more opcode bytes, fetch operands,
operate on internal registers, etc.); this time may be
longer than the time required for a RAM refresh cycle.
If the status outputs of the CPU can be examined to
determine which memory cycles are opcode fetches, a
refresh cycle may be performed immediately afterward
(Figure 9). In this way, refresh cycles will never interfere
with read or write cycles, and so appear "transparent"
to the microprocessor.
Transparent refresh has the disadvantage that if the
microprocessor ever stops fetching opcodes for very
3-116
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INSTRUCTION
DECODE TIME
r-----~~~----~
h
FETCH
OPCODE
FETCH
OPERAND
A. NO REFRESH CYCLES
INSTRUCTION
DECODE TIME
~
I
1"---------,
I
I
I
f
TIME
•
EXECUTION
TIME DEGRADED
THIS AMOUNT
I
I
REFRESH
I
I
CYCLE
I
I
IL _________ JI
FETCH
OPCODE
I
FETCH
OPERAND
FETCH
OPERAND
FETCH
OPERAND
•
TIME
B. REFRESH INTERFERES WITH OPERAND FETCH
INSTRUCTION
DECODE TIME
~
'---F-ET-C-H-"';
OPCODE
r--~~;:E~~--l
I
I
CYCLE
L__________ .J
Ir--FE-T-C-H--'
OPERAND
FETCH
OPERAND
I
•
TIME
C. TRANSPARENT REFRESH
Figure 9. Transparent Refresh
ternal refresh request input (REFRQ) allows the
microprocessor's status to be decoded to generate a
refresh cycle for transparent refresh. If, for whatever
reason, no external REFRQ is generated for 15
microseconds, the internally generated refresh will take
over, so memory integrity will be guaranteed.
long, due to a HOLD, extended DMA transfers, or
when under hardware emulation, no refresh cycles will
occur and RAM data will be lost. This puts restrictions
on the system design. Also, high speed microprocessors
do not allow silfficient time between opcode fetches and
susequent bus cycles for a complete RAM refresh cycle
to be performed, so they must wait for the refresh cycle
to complete before they can do a subsequent bus cycle.
These microprocessors cannot use transparent refresh to
any advantage. Transparent refresh is useful for
microprocessors like the Intel 8085 operating at low
clock frequencies.
Arbitration
Because RAMs cannot do a read or write cycle and a
refresh cycle at the same time, some form of arbitration
must be provided to determine when refresh cycles will
be performed.
The 8086 and 8088, however, prefetch opcodes into a
queue which is several bytes long. This prefetching is independent of the actual decoding and execution of the
opcodes, and there is no time at which it can pe
guaranteed that the 8086 or 8088 will not request a
memory cycle. So transparent refresh is not applicable
to these microprocessors.
Arbitration may be done by the microprocessor or by
the dynamic RAM controller. Microprocessor arbitration may be implemented as follows:
The 8202A and 8203 perform distributed and/or
transparent refresh. Each device has an internal timer
which automatically generates a distributed refresh cycle every 15.6 microseconds or less. In addition, an ex3-117
A counter, running from the microprocessor's clock, is
used to time the period between refresh cycles. At terminal ~ount, the arbitration logic asserts the bus request
signal to prevent the microprocessor from performing
any more memory cycles. When the microprocessor
responds with a bus grant, the arbitration logic
generates a refresh cycle (or cycles, if burst refresh is
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used). After refresh is complete, the arbitration logic
releases the bus. This method has several disadvantages:
First, time is wasted in exchanging bus control, which
would not be required if the RAM controller did arbitration. Second, while refresh is being performed, all
bus activity is stopped; for instance, even if the
microprocessor is executing out of ROM at the time, it
must stop until refresh is over. Third, bursts of DMA
transfers must be kept very short, as refresh cannot be
performed while DMA is in progress.
before it can complete the read or write cycle. This
means that from when the microprocessor activates the
read or write signal, the time until the cycle can be completed can vary over a range of roughly 200 to 700 ns.
Because of this, an acknowledge signal from the
dynamic RAM controller is required to tell the
microprocessor the memory cycle it requested is complete. This signal goes to the microprocessor's READY
logic.
Memory Organization
Some microprocessors, such as the Zilog Z-80, generate
refresh cycles themselves after instruction fetches. This
removes the need for external arbitration logic,'but still
has several disadvantages: First, DMA bursts still must
be kept short to allbw the CPU to do refresh. Second,
this method adds to the complexity of the microprocessor, without removing the need for the RAM controller which is still required to do address multiplexing
and RAS, CAS and WE timing. Microprocessor refresh
can cause problems of RAM compatibility; for instance,
the Z-80 only outputs a 7-bit refresh address, which
means some 64K RAMs which use 256 row refresh cannot be used with the Z-80. Also, since the Z-80 refresh
cycle is fixed length (no wait states), faster speed selections of the Z-80 are not compatible with slower
dynamic RAMs. Third, systems employing 'multiprocessing or DMA are harder to implement, because of
the difficulty in insuring the microprocessor will be able
to perform refresh.
a
It is preferable to have arbitration performed by the
dynamic RAM controller itself. This method avoids all
the problems described above, but introduces a complication. If the microprocessor issues a read or write
command while the dynamic RAM is in the middle of a
refresh cycle, the RAM controller must make the
microprocessor wait until it is done with the refresh
INTEL DYNAMIC RAM CONTROLLERS
The Intel 8202A and 8203 Dynamic RAM Controllers
each provide all the interface logic needed to use
dynamic RAMs in microprocessor systems, in a single
chip. Either the 8202A or 8203 allow a dynamic RAM
memory to be implemented using a minium of components, board space, and power, and in less design
time than any other approach.
As each dynamic RAM operates on only one bit at a
time, multiple RAMs must be operated in parallel to
operate on a word at a time. RAMs operated in this way
are called a bank of RAM. A bank consists of as many
RAMs as there are bits in the memory word. When used
in this way, all address and control lines are tied to all
RAMs in the bank.
A single bank of RAM will provide 64K words of
memory in the case of the 2I64A, or 16K words in the
case of the 2118. To provide more memory words,
multiple banks of RAM are used. In this case, all address, CAS, and WE lines are tied to all RAMs, but each
bank of RAM has its own RAS. Each bank knows
whether it is being addressed during' a read or write
operation by whether or not its RAS input was activated
- if not, then all other inputs are ignored during that
cycle.
Data outputs for RAMs in corresponding bit positions
in each of the banks may be tied in common, since they
are 3-state outputs; even though CAS is connected to all
banks of RAM, only that bank whose RAS is active will
enable its data outputs in response to CAS going active.
Data inputs for RAMs in corresponding bit positions in
each of the banks are also tied in common.
and 16K dynamic RAMs, including the Intel 2I04A,
2117, and 2118. The pinout and simplified logic
diagram of the 8202A are shown in Figures 10 and 11.
The following sections will describe each of these controllers in detail.
8202A
FUNCTIONAL DE~CRIPTION
The 8202A provides total dynamic RAM control for 4K
,3-118
The 8202A is always in one of the following states:
IDLE
b) TEST cycle
c) REFRESH cycle
d) READ cycle
e) WRITE cycle
a)
The 8202A is normally in the idle state. Whenever a cycle is requested, the 8202A will leave the idle state to
perform the desireq cycle; if no cycle requests are pending, the 8202A will return to the idle state. A refresh
cycle request may originate internally' or externally to
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AH4
AH3
AH2
AH,
AHo
ALo
'OUTo
AL,
OUT,
AL2
OUT2
AL3
OUT3
AL4
OUT4
ALs
OUTs
ALslOP3
OU T6
GND
Vee
AHS
AH6
X,/ClK
XoIOP2
N.C.
REFRQ ALE
PCS
Rii S1
WR
SACK
XACK
WE
CAS
RAS3
B,/OP,
Bo
RAS2
RAS,
RASo
Figure 10. 8202A Pinout
the 8202A; 'all other requests come only from outside
the 8202A.
'
A test cycle is requested by activating the RD and WR
inputs simultaneously, independent of PCS (Protected
Chip Select). The test cycle will reset the refresh address
counter to zero and perform a write cycle. A test cycle
should not be allowed to occur in normal system operation, as it interferes with normal RAM refresh.
by activating the REFRQ input to the 8202A; this input
is latched on the next 8202A clock. If no refresh cycles
are requested for a period of about 13 microseconds, the
8202A will generate one internally. By refreshing one
row every 15.6 microseconds or sooner, all 128 rows will
be refreshed every 2 ms. Because refresh requests are
generated by the 8202A itself, memory integrity is insured, even if the rest of the system should halt operation for an extended period of time.
The arbiter logic will allow the refresh cycle to take
place only if there is not another cycle in progress at the
time.
A read cycle may be requested by activating the RD input, with PCS (Protected Chip Select) active. In the Advanced Read mode, a read cycle is requested if the
microprocessor's SI status line is high at the falling edge
of ALE (Address Latch Enable) and PCS is active. If a
dynamic RAM cycle is terminated prematurely, data
loss may result. The 8202A chip select is "protected" in
that once a memory cycle is started, it will go to completion, even if the 8202A becomes de-selected.
A write cycle may be requested by activating the WR input, with PCS active; this is the same for the normal and
Advanced Read modes.
BLOCK DIAGRAM
Let's look at the detailed block diagram in Figure 12 to
see how the 8202A satisfies the interface requirements
of the dynamic RAM.
A refresh cycle performs a RAS-only refresh cycle of the
next lower consecutive row address after the one
previously refreshed. A refresh cycle may be requested
A H O·6
ALO·6
Address Multiplexing
Address multiplexing is achieved by a 3-to-1 multiplexer
---------v
=::r====:;--=--=Y
REFRQ/ALE
RD/Sl
WR
pcs
TIMING
GENERATOR
B.l0P,
Bo
RASo
RAS,
RAS2
RAS3
CAS
WE
SACK
XACK
Figure 11. 8202A Simplified Block Diagram
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AHO·6
Alo·6
OUTO·6
Bo
B,
REF RIC
XoIOP2
TEST MODE
RASo
RAS,
RAS2
RAS3
ClK
W~,~~~
START
RDISl
GEN'R
(SHIFT
REG. &
lOGIC)
RAS
RIC
CAS
CAS
WE
WE
SACK
COMMAND
DECODER
EOC
SACK
XACK
XACK
OPl
Figure 12. 8202A Detailed Block Diagram
internal to the 8202A; the three inputs are the row address (ALo_6)' column address (AHo_6), and refresh row
address (generated internally). When the 8202A is in the
Idle state, the multiplexer selects the row address, so it is
prepared to start a memory cycle. If a refresh cycle is requested either internally or externally, the address
multiplexer will select the refresh row address long
enough before RAS goes active to satisfy the RAM's
tASR parameter.
To minimize propagation delays, the 8202A address
outputs (OUTO_6) are inverted from the address inputs.
~---FROM
OUTo·6
ALo·6
This has no effect on RAM operation; inverters are not
needed on the address outputs.
Doing this multiplexing internally mmlmlzes timing
skews between the address, RAS, and CAS, and allows
higher performance than would otherwise be possible.
Refresh Counter
The next row to _be refreshed is determined by the
refresh counter, which is implemented as a 7-bit ripplecarry counter. During each refresh cycle, the counter is
MICROPROCESSOR ADDRESS BUS
REF. ADDR.-l
REF. ADDR.
Alo·6
RAS
Figure 13. Detailed 8202A Refresh Cycle
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incremented by one in preparation for the next refresh
cycle (a refresh cycle is shown in detail in Figure 13).
When the 8202A enters TEST mode, the refresh counter
is cleared. This feature is useful for automatic testing of
the refresh counter function. Because the address outputs are inverted, the first refresh address after clearing
the counter in test mode is 7FH, and the addresses
decrease for subsequent refresh cycles.
RAS Decoding
Which bank of RAM is selected for a memory cycle is
determined by the RAS decoder from the BO-I inputs,
which normally come from the microprocessor address
bus. The 8202A Timing Generator produces an internal
RAS pulse which strobes the RAS decoder, generating
the appropriate external RAS pulse. The BO_I inputs are
not latched, so they must be held valid for the length of
the memory cycle. During a refresh cycle, all the RAS
outputs are activated, refreshing all banks at once.
Oscillator
The 8202A operates from a single reference clock with a
frequency between 18.432 MHz and 25 MHz; this clock
is used by the synchronization, arbitration, and timing
generation logic. This clock may be generated by an onboard crystal oscillator, or by an external TTLcompatible clock source. When using the internal
oscillator (available only on part number D8202A-l or
Xo 36
X, 37
8202A
a. CRYSTAL MODE
Command Decoder
The command decoder takes the commands from the
bus and generates internal memory request (MEMR),
and TEST signals.
The 8202A has two bus interface modes: the "normal"
mode, and the "Advanced Read" mode. In the normal
mode, the 8202A interfaces to the usual bus RD and
WR signals.
In the Advanced Read mode, ihe 8202A interfaces to
the Intel microprocessor bus signals ALE, SI, and WR.
Sl must be high on the falling edge of ALE for read
cycles, and WR must be low for write cycles (write
cycles are the same as for normal read mode). The
8085A SI may be used directly by the 8202A; the 8086
and 8088 SI must be inverted. ALE and WR must be
qualified by pes.
The Advanced Read mode is useful for reducing read
data access time, and thus wait states. This mode is used
mainly with 8085A systems.
If both RD and WR are active at once (regardless of the
state of peS), the internal TEST signal is generated. and
the 8202A performs a test cycle as described above. One
or both of RD and WR should have pull-up resistors to
prevent the 8202A from inadvertantly being put into test
mode, as the RD and WR signals are 3-stated by the
microprocessor when RESET or HOLD are active.
Since the test mode resets the refresh address counter,
the refresh sequence will be interrupted, and data loss
may result.
Refresh Timer and REFRQ
12 v
±10%
1 K.f\.
± 5%
D8202A-3), a fundamental-mode crystal is attached to
pins 36 and 37 (Xo and XI), as shown in Figure 14. The
external TTL clock option is selected by pulling pin 36
(OP2) to + 12v through IK ohm resistor, and attaching
the clock input to pin 37 (eLK).
The 8202A contains a counter, operated from the internal clock to time the period from the last refresh cycle.
When the counter times out, an internal refresh request
is generated. This refresh period is proportional to the
8202A's clock period, and varies from 10.56 to 15.625
microseconds. Even at the lowest refresh rate, all the
rows of the dynamic RAM will be refreshed every 2 ms.
8202A
~
ClK 37
The 8202A has an option of reducing the refresh rate by
a factor of two, for use with 4K RAMS. These RAMs
have only 64 rows to refresh every 2 ms, so need refresh
cycles only half as often. This option is selected by pull-
b. EXTERNAL CLOCK MODE
Figure 14. 8202A Clock Options
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ing pin 18 (AL6/0P3) to + 12v through a 5.1K ohm
resistor. This pin normally serves as the high-order row
address input for the address multiplexer, but it is no
longer needed for this function, as 4K RAMs have one
less address input.
A refresh cycle may also be requested externally by activating the REFRQ input. This input is latched, so it
only needs to be held active a maximum of 20 ns. If the
8202A is currently executing a memory cycle, it will
complete that cycle, and then perform the refresh cycle.
The internal and external refresh requests are 0 Red
together before going to, the arbiter.
The REFRQ input cannot be used in the Advanced
Read mode, as the REFRQ pin is used for ALE in this
mode.
REFRQ is most often used to implement transparent
refresh, as explained in the section Dynamic
RAMS - Refresh. This technique is not useful in iAPX
86 and iAPX 88 systems, so REFRQ is normally tied to
ground.
The refresh timer is reset as soon as a refresh cycle is
started (whether it was requested internally or externally). The time between refresh cycle (tREF) is measured
from when the first cycle is started, not when it was requested, which occurs sometime earlier. Of course,
tREFmin does not apply if REFRQ is used - you may
externally request refresh cycles as often as you wish.
the 8202A's internal clock. Assuming the 8202A is initially in an idle state, one full clock period after the synchronizers sample the state of the MEMREQ and
REFREQ signals, the arbiter examines the REFR and
MEMR outputs of the synchronizers. If MEMR is active, the arbiter will activate START to begin the
memory cycle (either read or write) on that clock. If
REFR is active (regardless of the state of MEMR), the
arbiter will activate START and REF to begin a refresh
cycle on that clock. Once the cycle is complete, the Cycle Timing Generator will generate an end-of-cycle
(EOC) signal to clear the arbiter and allow it to respond
to any new or pending requests on the next clock.
Once a memory cycle is started, it cannot be stopped,
regardless of the state of the RD/Sl, WR, ALE, or PCS
inputs. This is necessary, as ending a dynamic RAM
cycle prematurely may cause loss of data. Note,
however, that the RAM WE output is directly gated by
the WR input, so if WR is removed prematurely, the
RAM WE pulse-width spec (twp) may be violated, causing a memory failure.
What happens if a memory request and refresh request
occur simultaneously? ,
If the 8202A is in the idle state, the memory request
will be honored first.
If the 8202A is not in the idle state (a memory or
refresh cycle is in progress) then the memory cycle
will lose priority and the refresh cycle will be honored
first.
Arbiter
This is the hardest section of a dynamic RAM controller
to implement. If a read or write arrives at the same time
as a refresh request, the arbiter must decide which one
to service first. Also, if a read, write, or refresh request
arrives when another cycle is already in progress, the arbiter must delay starting the new cycle until the current
cycle is complete.
Both of the internal signals REFR (refresh request) and
MEMR (memory cycle request) are synchronized by
D-type master-slave flip-flops before reaching the arbiter. these circuits have been optimized to resolve a
valid logic state in as short a time as possible. Of course,
with any synchronizer, there is a probability that it will
fail - not be able to settle in one logic state or the other
in the allowed amount of time, resulting in a memory
failure - but the 8202A has been designed to have less
than one system memory failure every three years,
based on operation in the worst case system timing
environments.
Both synchronizers and the arbiter are operated from
\
Remember, if the 8202A is performing a cycle, the arbiter doesn't arbitrate again until the end of that cycle.
So the memory and refresh cycles are "simultaneous" if
they both happen early enough to reach the arbiter
before it finishes the current cycle. This arbitration arrangement gives memory cycles priority over refresh
cycles, but insures that a refresh cycle will be delayed at
most one RAM cycle.
Refresh Lock·Out
As a result of the 8202A operation, transparent refresh
circuits like the one shown in Figure 15 should not be
used. This circuit uses the RD input, with some qualifying logic, to activate REFRQ whenever the microprocessor does an opcode fetch. This circuit will work fine,
as long as the 8202A never has to generate an internal
refresh request, which is unlikely (if nothing else, the
system R~SET pulse is probably long enough that the
8202A will throw in a couple of refreshes while the
microprocessor is reset). If the 8202A ever does generate
its own refresh, there is a probability that the
microprocessor will try to fetch an opcode while the
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AFN: 02200A
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refresh is still in progress. If that happens, the 8202A
will finish the refresh, see both the RD and REFRQ inputs active, honor the REFRQ first, and start a second
refresh. In the meantime, the microprocessor is sitting
in wait states, waiting for the 8202A to complete the op'code fetch. When the 8202A finishes the second refresh,
it will see both RD and REFRQ active again, and will
start a third refresh, etc. The system "locks up" with
the microprocessor sitting in wait states ad infinitum,
and the 8202A doing one refresh cycle after another.
When the cycle is complete, the Cycle Timing Generator
sends an end-of-cycle (EOC) pulse to the arbiter to
enable it to respond to new or pending cycle requests.
Minimum and maximum values for the 8202A
parameters tCR (Command to RAS active delay) and tcc
(Command to CAS active delay) differ by one 8202A
clock period. This is because the commands (RD, WR,
. ALE) must be synchronized to the 8202A's clock; this
introduces a ± one clock period (tp) uncertainty due to
the fact that the command mayor may not be sampled
on the first clock after it goes active, depending on the
set-up time. If RD or ALE and WR are synchronous to
the 8202A's clock, and the set-up time (tsd is met, the
smaller number of clock periods will apply.
808SA
All .8202A output timings are specified for the
capacitive loading in the data sheet. Typical output
characteristics are shown in the data sheet for capacitive
loads ranging from 0 to 660 pF, these can be used to
calculate the effect of different loads· than those
specified in the data sheet on output timings. All address, RAS, CAS, and WE drivers are identical, so these
characteristic curves apply to all outputs.
Figure 15. Improper Transparent
Refresh Generation
To prevent this from happening, the transparent refresh
circuit should be modified as shown in Figure 16. In this
circuit, REFRQ cannot be activated until the opcode
fetch is already in progress, as indicated by SACK being
active (remember, SACK is never active during a
refresh). If the microprocessor tries to do an opcode
fetch while the 8202A is doing a refresh, REFRQ will
not be active; the 8202A will finish the refresh and see
only RD active, and will start the opcode fetch; only
then will REFRQ be activated.
5,
So
808SA
RD
Because refresh cycles are performed asynchronously to
the microprocessor's operation (except during
transparent refresh), the microprocessor cannot know
when it activates RD or WR if a refresh cycle is in progress, and therefore, it can't know how long it will take
to complete the memory cycle.
This added consideration requires an acknowledge or
"handshake" signal from the 8202A to tell the
microprocessor when it may complete the memory
cycle. This acknowledge would be used to generate the
microprocessor's READY input - the microprocessor
will sit in wait states until the 8202A acknowledges the
memory cycle. Two signals are generated for this purpose by the 8202A; they are called system acknowledge
(SACK) and transfer acknowledge (XACK). They serve
the same purpose but differ in timing.
8202A
.--..
C4
SACK AND XACK
REFRQ
SACK
-
RD
Figure 16. Generating Transparent
Refresh For 8085A Systems
XACK is a Multibus-compatible signal, and is not activated until the read or write cycle has been completed
by the RAMs. In a microprocessor system, however,
there is a considerable delay from when the 8202A
acknowledges the memory cycle until the microprocessor actually terminates the cycle. This delay is due
to the time required to combine this acknowledge with
other sources of READY in the system, synchronize
READY to the microprocessor's clock, sample the state
of READY, and respond to an active READY signal.
As a result, more wait states than necessary may actual-
Cycle Timing Generator
The Cycle Timing Generator consists of a travellingones shift register and combinational logic required to
generate all the RAM control signals and SACK and
XACK. All timings are generated from the 8202A's internal clock; no external delay lines are ever needed. The
timing of these signals relative to CLK is illustrated in
Figure 17.
3-123
AFN' 02200A
·1
2
0
4
ClK
RD
WR
ALE
PCS
ADDRESS
....,..ct>
ROW
COlUMN-
ROW
RAS
N
CAS
READ CYCLE
WE
SACK
WRITE CYCLE
DELAYED SACK
-----------1-.------------------------------------------------------------------,
\
NORMAL SACK
XACK
(EOC)
,.
"
;<:
~
Figure 17. 8202A Timing Relative To elK
Ap·97A
8202A memory cycle will have SACK delayed, even if
that cycle was not actually delayed due to a refresh cycle
in progress. The delayed SACK flip-flop will be reset at
the end of that cycle, and the 8202A will return to normal SACK operation. The same thing happens in Advanced Read mode if SI is high at the f~ling edge of .
ALE during a refresh cycle, once again regardless of the
state of PCS.
ly be generated by using XACK. SACK is activated
earlier in the cycle to improve performance of
microprocessors by compensating for the delays in the
microprocessor responding to XACK, and thus
eliminating unneeded wait states which might be
generated as a result of XACK timing. The system
designer may use one or the other acknowledge signal,
or use both in different parts of the system, at his
option.
8203
SACK and XACK are activated by the Cycle Timing
Generator, but they can be de-activated only by the
microprocessor removing its RD or WR request, or by
activating ALE when in the advanced read mode. As the
SACK and XACK signals are used to generate READY
for the microprocessor, this is necessary to give the
microprocessor as much time as it needs to respond to
its READY input.
The 8203 is an extension of the 8202A architecture
which allows the use of 64K dynamic RAMs. It is pinout
compatible with the 8Z02A and shares identical A.C.
and D.C. parameters with that part. The description of
the 8202A applies to this part also, with the modifications below.
ENHANCEMEt-ITS
Delayed SACK Mode
SACK may be activated at one of two different times in
tiJe memory cycle; the earlier case is called "normal
SACK" and the later is called "delayed SACK" (Figure
18). Delayed SACK occurs if the memory request was
received by the 8202A while it was doing a refresh cycle.
In this case, the memory cycle will be delayed some
length of time while the refresh cycle completes; SACK
is delayed to ensure the microprocessor will generate
enough wait states. This is a concern mostly for read
cycles.
Because of the way the delayed SACK mode is implemented in the 8202A, if the RD or WR input is activated while a refresh cycle is in progress, regardless of
whether or not the 8202A is chip-selected, the internal
delayed SACK mode flip-flop will be set. The next
\
I.
Supports 16K or 64K dynamic RAMs. 4K RAM
It).ode, selected by pulling AL6I'OP3 (pin 18) to
+ 12v, is not supported.
2.
Allows a single board design to use either 16K
or 64K RAMs, without changing the controller,
and only making between two and four jumper
changes to reconfigure the board.
3.
May operate from external TTL clock without
the + 12v pull-up which the 8202A requires (a
+ 5v or + 12v pull-up may be used).
The pinout of the 8203 is shown in Figure 19. This
pinout is identical to the 8202A, with the exception of
the five highlighted pins. The fanction of these is
described below. The simplified block diagram is similar
to the 8202A's, in Figure 11.
DELAYED SACK
-------------~~::L-::-------------\
\~I
Figure 18. Delayed SACK Mode
3-125
AFN 02200A
Ap·97A
8io2A's pins are already used, this is clearly a challenge
- some functionality must be sacrificed to gain 64K
RAM support. The 8203 reduces the maximum number
of banks supported from four to two for 64K RAMs.
AH4
AHS
AH2
AHI
AHo
Pin 35 (16K/64K) is used to tell the 8203 whether it is being used to control 16K RAMs or 64K RAMs. When
tied to )Icc or left unconnected, the 8203 operates in the
16K RAM mode; in this mode all the remaining pins
function identically to the 8202A. When tied to ground,
it operates in the 64K RAM mode, and pins 23 through
26 change function to enable the 8203 to support 64K
RAMs. Pin 35 (16K/64K) contains an internal pull-up
-when unconnected, this input is high, and the 8203
operates identically to the 8202A. This maintains pinout
compatibility with the 8202A, in which pin 35 is a noconnect, so the 8203 may be used in 8202A sockets with
no board modifications.
ALO
OUTo
ALI
OUTI
AL2
0U'I'2
AL3
OUTs
AL4
OUT4
ALS
OUTS
ALe
OUTe
XACK
WE
CAS
RASs(Bo)
Bl(AH7)
Bo(AL7)
RAS2COU'I'n
RASI
v •• ~;;..._......;;:..r RASo
When the 8203 is in the 64K RAM mode, four pins
change function, as shown in Table 2. The pins change
function in this particular way to allow laying out a
board to use either 16K or 64K RAMs with a minimum
of jumpers, as shown in Figure 20. This figure shows the
8203 with two banks of RAM. Banks 0 and 1 may be
either 16K RAMs or 64K RAMs; banks 2 and 3 may only be 16K RAMs, as the 8203 supports two banks of 64K
RAM. For clarity, only those connections which are important in illustrating the 8203 jumper options are
shown .
Fig. 19 8203 Pinout
16K Mode and 64K Mode
The gOal of the 8203 is to provide a pin- and timingcompatible upgrade of the 8202A for use with 64K
RAMs. The difficulty in doing this is that 64K RAMs require an additional address input compared to 16K
RAMs, and thus the 8203 needs three more pins (one
more RAM address output, and two more inputs to its
internal address multiplexer). Since all but one of the
....
Ao·A13
ALo-&
ALo·&
RASo 21
A14
24 BoCAL7)
AIS
25 Bl (AH7)
J1
CS (32K WORDS) ~
CS (64K WORDS) -0
f! (128K WORDS)
---:8
J5
1-=
Ale
...:g
RASI 22
2118
(2164)
RAS2 23
(OUT7)
9 N.C. (A7)
RASa(Bo)
J4 33
~ PCS
BANK 0
~
8203
~
4 RAS
'--.1
16Kt64K
RAS
2118
(2164)
J8
~
16K RAM JUMPER OPTION
J1·J4 (32K WORDS)
J1·J2 (64K WORDS)
~
BANK 1
N.C. (A7)
TO RAS OF BANK 2
(2118 ONLY)
L....... TO RAS OF BANK 3
(2118 ONLy)
64K RAM JUMPER OPTION
J2·J4 (64K WORDS)
J3·J4 (128K WORDS)
J5-J6
J7.J8
/
figure 20. 8203 Jumper Options
3-126
AFN:022OOA
AP·97A
Table 2. 16K/64K Mode Selection
Pin #
23
24
25
26
64K Function
16K Function
RAS2
Bank Select (BO)
Bank Select (B I)
RAS3
Address Output (OUT7)
Address Input (AL7)
Address Input (AH7)
Bank Select (BO)
Jumpers Jl·J4 may be used to chip select the 8203 over
various address ranges. For example, if two banks of
16K RAMs are replaced with two banks of 64K RAMs,
the address space controlled by the 8203 increases from
32K words to 128K words. If four banks of 16K RAMs
are replaced with one bank of 64K RAMs, no chip select
jumpers are needed.
In the 64K RAM mode, pins 24 and 25 (Bo(AL7) and
B1(AH7» change function from bank select inputs to
address inputs for the 64K RAM. Since the bank select
inputs normally come from the address bus anyway, no
jumper changes are required here. The bank select function moves to pin 26 (RAS 3(BO»; since only two bank of
64K RAM is supported, only one bank select input is
needed in this mode, not two. Jumpers J6 and 17 are
shorted in the 64K RAM mode to connect pin 26 (Bo) to
the address bus. In the 16K RAM mode, these jumpers
must be disconnected, as pin 26 junctions as the RAS 3
output; in the 64K RAM mode, this bank is not populated, so RAS3 is not needed.
Pin 23 serves two functions: in the 16K RAM mode it is
tJ;1e RAS output for bank 2 (RAS2l, in the 64K RAM
mode is the high order RAM address output (OUT7),
which goes to pin 9 of the 64K RAMs. This requires no
jumpers as when using 16K RAMs, pin 9 is a noconnect, and when using 64K RAMs, bank 2 is
depopulated, so RAS2 is not used.
This arrangement allows converting a board from 16K
RAMs to 64K RAMs with no change to the controller
and changing a maximum of three jumpers.
+ 5v External Clock Option
Just"as with the 8202A, the user has the option of an external TTL clock instead of the internal crystal
oscillator as the timing reference for the 8203; unlike the
8202A, he does not need to tie pin 36 (Xol0P2) to + 12v
to select this option-this pin may be tjed to either + 5v
or + 12v. If pin 36 is tied to + 12v, a lK ohm (± 5OJo)
series resistor must be used, just as for the 8202A. If pin
36 is tied to + 5v, it must be tied directly to pin 40 (V cc)
with no series resistor. This is because pin 36 must be
within one Schottky diode voltage drop (roughly 0.5v)
of pin 40 to select the external TTL clock option; a
series resistor may cause too great a voltage drop for the
external clock option to be selected. For the same
reason, the trace from pin 36 to 40 should be kept as
short as practical.
Test Cycle
An 8203 test cycle is requested by activating the RD.
WR, and PCS inputs simultaneously. By comparison,
an 8202A test cycle requires activating only the RD and
WR inputs simultaneously, independent of PCS. Like
the 8202A, and 8203 test cycle resets the address counter
to zero and performs a write cycle.
AHO-6 - - - - - - - - - , /
REFRQIALE
RDIS1
TIMING
81.0P1_....._ _ _ _ _ _ _00iGENERATOR
80-------------001
RASO
RAS1
RAS,
RAS3
CAS _
WE
SACK
XACK
16KI64K:-------"
Figure 21. 8203 Simplified Block Diagram
3-127
AFN-.02200A
Ap·97A
it to support RAMs which u;e either the 128-row
or 256-row refresh schemes. Regardless of which
type of RAM is used, the refresh counter cycles
through 256 rows every 4 ms. RAMs which use
128-row re-fresh treat the eighth address bit as it
"don't care" during refresh, so they see the
equivalent of 128-row refresh every 2 ms. In
either case the rate of internally-generated
refresh cycles is the same-at least one every
15.6 microseconds.
BLOCK DIAGRAM
A simplified block diagram of the 8203 is shown in
Figure 21. It is identical to the 8202A except for the
following differences:
1. The 3: 1 address multiplexer is 8 bits wide, instead
of 7 bits wide, to support the addressing
requirements of the 64K RAM.
2.
The refresh address counter is 8 bits. This allows
INTEL iAPX·86 AND iAPX·88
Device Descriptions
The iAPX;-86 and iAPX-88 are advanced 16-bit
microprocessor families, based on the 8086 and 8088
microprocessors, respectively. While both have a similar
architecture and are software compatible, the 8086
transfers data over a 16-bit bus, while the 8088 uses an
8-bit data bus (but has a 16-bit internal bus).
Min and Max Modes
In order to support the widest possible range of applications, the 8086 and 8088 can operate in one of two
modes, called minimum and maximum modes. This
allows the user to define certain processor pins to
"tailor" the 8086 or 8088 to the intended system. These
modes are selected by· strapping the MN/MX
(minimum/maximum) input pin to Vee or ground.
In the minimum mode, the microprocessor supports
small, single-processor systems using a minimum of
components. In this mode, the 8086 or 8088 itself
generates all the required bus control signals (Figure
22).
In the maximum mode, the microprocessor supports
larger, higher performance, or multiprocessing systems.
In this mode, the 8086 or 8088 generates status outputs
which are decoded by the Intel 8288 Bus Controller to
provide an extensive set of bus control signals, and
Multibus compatibility (Figure 23). This allows higher
performance RAM operation because the memory read
and write commands are generated more quickly than is
possible in the minimum mode. The maximum mode is
the one most often used in iAPX-86 and iAPX-88
systems.
AO
MIlO
READY
GEN'R
CPU
A 16·19
ADo·15
8284A
ClK
8086
ALE
8282
ft-----'''-
8203
lATCH
DRAM
CONTROL
5TIT o 7
RAM
ARRAY
BHE
ClK
TO
TOCPU
READY
lOGIC
Figure 22. 8086 Minimum Mode
3·128
AFN 02200A
Ap·97A
READY
8284A
ClK
GEN'R
ClK
TO CPU
READY
lOGIC
Figure 23. 8086 Maximum Mode
control signal using the min or max mode in the normal
configuration.
Alternate Configuration
The Alternate Configuration is not an operating mode
of the 8086 or 8088 per se, but uses TTL logic along with
the status outputs of the microprocesor to generate the
RAM read and/or write control signals (Figure 24). The
alternate configuration may be used with the
microprocessor in either minimum or maximum mode.
This configuration is advantageous because it activates
the memory read and write signals even earlier than the
maximum mode, leading to higher performance. It is
possible to generate either the RAM read or write signal
using this configuration, and generate the other RAM
Each of the three system configurations may be used
with buffers on the address, data, or control bus for increased electrical drive capability.
Performance
VS.
Wait States
Before starting a discussion of timing analyses, it's
worthwhile to look at the effect of wait states on the
iAPX-86 and iAPX-88.
Vee
ClK
8284A {
CLOCKED AMWC
8086
8088
{STATUS
(50·2)
ADVWR
TO
8202AI
8203
ALE
8288
AMWC
ADVRD
1
MRDC
Figure 24. Alternate Configuration LogiC
3-129
AFN 02200A
Ap·97A
For most microprocessors, the effect of, say, one wait
state on execution times is straightforward. If a bus
cycle normally is three clocks long, adding a wait state
to every bus cycle will make all bus cycles four clocks,
decreasing performance by 33010. This is multiplied by
the percentage of time that the microprocesor is doing
bus cycles (some instructions take a long time to execute, so the microprocessor skips a few bus cycles).
which don't use an instruction queue. The effect of wait
states on 8086 execution time compared to the Motorola
68000 and Zilog Z8000 for a typical mix of software is
summarized in Table 3.[1]
Table 3. Effects of Wait States on Execution Time
Execution Time Increase
Over 0 Wait State
Execution Time
The effect of wait states on the iAPX-86 and iAPX-88 is
not so straightforward, however.
The 8086 and 8088 microprocessors consist of two processing units: the execution unit (EU) executes instructions, and the bus interface unit (BIU) fetches instructions, reads operands, and writes results. During
periods when the EU is busy executing instructions, the
BIU "looks ahead" and fetches more instructions from
the next consecutive addresses in memory; these are
stored in an internal queue. This queue is four bytes
long for the 8088 and six bytes long for the 8086; under
most conditions, the BIU can supply the next instructions without having to perform a memory cycle. Only
when the program doesn't proceed serially (e. g. a Jump
or Call instruction) does the EU have to wait for the
next instruction to be fetched from memory. Otherwise,
the instruction fetch time "disappears" as it is proceeding in parallel with execution of previously fetched
instructions. The EU then has to wait for the BIU only
when it needs to read operands from memory or write
results to memory. As a result, the 8086 and 8088 are
less sensitive to wait states than other microprocessors
Processor
1 Wait
State
2 Wait
States
3 Wait
iAPX 86/10 (measured)
Z8000 (computed)
68000 (computed)
8.3"7.
\9.1"70
15.9"70
\6.3"70
38.2"70
31.9%
26.3"70
57.3"70
47.8%
The BIU can fetch instructions faster than the EU can
execute them, so wait states only affect pefformance to
the extent that they make the EU wait for the transfer of
operands and results. How much this affects program
execution time is a function of the software; programs
that contain many complex instructions like multiplies
and divides and register operations are slowed down less
than programs that contain primarily simple instructions. The effect of wait states on the 8086 and 8088 is
always less than on other microprocessors which don't
use an instruction queue.
[1]
From J6-Bit Microprocessor Benchmark Report:
iAPX-86, Z80OO, and 68000, pub!. by Intel Corp.
1980
Ao
8086
States
H-+-I----io-jPCS 8203 WE
8282
74532
WE
(LOW
BYTE)
A1S-19
AD01S
52.51,50
READY
Figure 25. 8086 Max Mode System
3-130
AFN' 02200A
Ap·97A
:;;:~t------~t---:--~~~-
~~~-
\
RAS
IRSH
~IRCD-
I
ICAS
V
CAS
_IASR-
)
!-IRAH-
_IASC-'
_ICAH-
COLUMN
ROW
K
Figure 26. Memory Compatibility Timing
Table 4. Memory Compatibility Timings
Timing Analysis
(all parameters are minimums)
This section will look at two specific system configurations to show how the 8203 timing requirements are
satisfied by the 8086. Methods of determining the worst
case number of wait states for the various configurations are also given.
Symbol
tASC
tASR
teAH
teAS
tRAH
tRCD[l)
tRSH
The timings of the 8202A and 8203 are identical; only
the 8203 is referred to for the remainder of this note, but
all comments apply equally to the 8202A. All timings
are worst case over the range of T A = 0 - 70"C and
Vee = + 5v ± 10% for the test conditions given in the
devices' data sheets.
Parameter
Column Address Set-Up Time
Row Address Set-Up Time
Column Address Hold Time
CAS Pulse Width
Row Address Hold Time
RAS to CAS Delay Time
RAS Hold Time from CAS
.
Value
tp-30
1p·30
51p·30
51p'1O
Ip-IO
21p-40
51p·30
[l)tRComin = tRAHmin + tAscmin = 2p - 40
This parameter is the minimum RAS active to CAS
active delay.
Example 1. 8086 Max
Mode System (5 MHz)
These timings are all a function of the 8203's clock
period (tp); they may be adjusted to be compatible with
slower dynamic RAMs by slowing the 8203's clock (increasing lp). The frequency of the 8203's clock may be
varied from 18.432 MHz to 25 MHz; for best performance, the 8203 should be operated at the highest possible frequency compatible with the chosen dynamic
RAM. In most cases, tRAH or tCAS will be the frequency
limiting parameter, but the 8203 can operate at its maximum frequency with most dynamic RAMs available.
This example (Figure 25) is representative of a typical
medium-size microprocesor system. Example I requires
one wait state (worst case) for memory cycles. Example
2 also uses an 8086 in Max mode at 5 MHz, b\)t uses externallogic to reduce the number of wait states to zero
for both read and write cycles.
DYNAMIC RAM INTERFACE
tASR applies only to refresh cycles. When the 8203 is in
the Idle state (not performing any memory or refresh
cycles) the address multiplexer allows the ALo_7 inputs
(the RAM row address) to propagate through to the
8203 OUTO_7 pins, which are connected to the RAM address pins. So in read or write cycles, the row address
will propagate directly from the address bus to the
First, look at the timing requirements of the dynamic
RAM to .ensure they are satisfied by the 8203. Memory
compatibility timings are shown in the 8203 data sheet
(Figure 26). Seven 8203 timings are given, not counting
tAD, which will be discussed in the next section. These
timings are summarized in Table 4.
3·131
AFN 02200A
AP·97A
RAM; the row address set-up time in this case is determined by the microprocessor's timing (see the next section). At the beginning of a refresh cycle, the 8203 has
to switch its internal multiplexer to direct the refresh
row address to the RAMs before activating RAS; the
tASR parameter in Table 4 refers to this case only.
Assume the Intel 2164A-20 RAM (200 ns access time) is
used. Equations l(a)-(h) show that this RAM is compatible at the 8203's maximum operating frequency of
25 MHz (lp = 11(25 MHz) = 40 ns). This frequency
will be used for now; once the rest of the system timings
are calculated, the minimum 8203 frequency which will
provide the same system performance can also be determined.
(a)
(b)
(c)
(d)
tASC
tASR
tCAH
tCAS
(e) tRAH
(f) tRCD[I]
(g) tRP
(h) tRSH
[I]
tp - 30
tp - 30
5tp - 30
5t p - 10
tp - 10
2tp - 40
4tp - 30
5tp - 30
10 (Equation 1.)
10
170
190
30
40
130
170
May be calculated as
tRcnIDin = tRAHmin + tAscmin = 2tp - 40
ADDRESS SET·UP AND HOLD TIME MARGINS
The microprocessor must put the memory address on
the address bus early enough in the memory cycle for it
to pass through the 8203 and meet the row address setup time to RAS (tASR> requirement' of the dynamic
RAM (Figure 27). Since the address propagates directly
through the 8203, this set-up time is a function of how
long the microprocessor holds the address on the bus
before activating the RD or WR command, the address
delay through the 8203 (tAnIDax), and how long the
8203 waits before activating RAS (tcRmin). This is
shown in Figure 28, and calculated in Equation 2. This
and all following equations show timing margins; a
positive result indicates extra margin, a zero result says
the parameter is just met, and a negative result indicates
it is not met for worst-case condWons.
Row Address Set-Up Time Margin
(Equation 2.)
CPU Address to RD Delay + RAS
Active Delay - Address Delays
TCLCL(5MHz) + TCLML min (8288) +
tCRmin(8203) - [Greater of
TCLA Vmax(8086) + TIVOVmax (8282) or
TCLLHmax(8288) + TSHOVmax(8282)] tAnIDax(8203) - tASR(2164A-20)
200 + 10 + [40 + 30] [Greater of (110 + 30) or (15 + 45)] - 40 - 0
100
74532
WE
8086
(LOW
BYTE)
Figure 27. Address Set·Up and Hold Time Margins
3-132
AFN' 02200A
T1
CLK(8284A)
T2
~
1\
\
i'--
1\
\
_TCLAV_
\V
BHE\(8086)
AO·19
JI\
BHE. Ao 19VALID
_TCLLH_
/
ALE(8288)
/
-
TIVOV
TSHOV
ADDRESS BUS
\/
/\
VALID
-IAD-
}
OUT 0.7(8203)
=Ao·7(2164.20)
VALID
I--IASR-
\
MRDC \(8288)
AMWC
\
1\
RAS(8203)
_TCLML
Figure 28. Address Set·up Time Margin
ICR-
T2
CLK(8284A)
T3
\
\
\
T4
T1
\
\
\
~
'\
'\
\
\
TW
'L-
~
/
ALE(8288)
/
~
ADDRESS BUS
~
MRDS 1(8288)
AMWC
\V
VALID
/~
,
\
\
RAS(8203)
I.
CAS(8203)
tee
.
i
tRSH
'1
"I
/
Figure 29. Address Hold Time Margin
AP·97A
READ DATA ACCESS TIME MARGIN
Similarly, the microptocessor must maintain the
memory addresS long enough to satisfy the column address hold time (teAR> of the RAM; the 8203 TAomin
parameter should be used for this calculation.
Read data access times determine how many wait states
are required for read cycles. Remember that dynamic
RAMs have two access time parameters, RAS access
tilJle (tRAd and CAS access time (teAd. Either one may
be the limiting factor in determining RAM access time,
as explained in the section Dynamic RAM - Access
Times, above. Here tCAC is the limiting factor, as
More importantly, the 8203 bank select (Bo-I) inputs are
also not latched; these are used directly to decode which
ill output is activated during read or write cycles, so
these inputs must be held valid until RAS goes inactive.
Since BO_I are usually taken directly from the address
bus, this determines the address hold time required of
the system (Figure 29). These are easily satisfied by the
8086 as shown by Equation 3. N represents the number
of wait states. This equation can be tried with various
values for N (starting with 0 and increasing) until the
equation is satisfied, or it can be set equal to zero
(meaning no excess margin remains) and solved for N
directly; the fractional value for N that results must be
rounded up to get the worst-case number of wait states
to satisfy this particular parameter. No wait states are
required to meet address hold times.
This timing is shown in Figures 30 and 31, and is
calculated in Equation 4. In this system, one wait state is
required to satisfy the read data access time requirements of the system; the margin is -50 ns, which is
too large a difference to be made up by using a faster
RAM.
Address Hold Time Margin (N "" 0)
(Equation 3.)
CPU Address Hold Time, from
RD Active - RAS Inactive Delays
(3 + N)TCLCL(5MHz) +
TCLLHmin(8288)[I) + TSHOVmin(8282)TCLMLmax(8288) - tccmas(8203) tRSHffiax(8203)[2)
3(200) + 2 + 10 - 35 - [4(40) + 85) [5(40) + 30)
102
[I)
Not specified - use 2 ns
(2) Not specified in 8203 data sheet;
tRsHmax(8203) = 5tp + 30
AO
8086
74532
WE
8282
(lOW
BYTE)
A16-19 1A-...--AJ A
ADo-1SI'IW""'IIIIr--YI
fi8284
~
RAM
5TB
ClK
01100
52. $1. SO 1---il1IIII---v1
............................4t-~ClK
DOUT
8286
OE
T
DON
Figure 30. Read Data Access Time Margin
3-135
AFN: 02200A
T2
T3
TW
T4
CLK(8284A)
MRDC(8288)
tcc
CAS(8203)
~
Co)
m
DouT(2164·20)
VALID
DATA BUS
------------
VALID
""":t"'"
-----~'-----------------4
Figure 31. Read Data Access Time Margin
VALID
;>------------------
AP·97A
Read Data Access
(Equation 4.)
Time Margin (N = 0)
CPU RD Active to Data Valid Delay CAS Active Delay - Data Delays
(2 + N)TCLCL(5MHz) - TCLMLmax(8288)
tccmax(8203) - tCAcmax(2164A-20) tpmax(74S373)[I] - TIVOVmax(8286) TDVCLmin(8086)
2(200) - 35 - [4(40) + 85] - 11030[1] - 30 - 30
- 80 => I wait state needed (N = I)
WRITE DATA SET·UP AND HOLD TIME MARGINS
In write cycles, the write data must
I.
reach the dynamic RAMs long enough before
CAS to meet the RAM's data set-up time
parameter, tos (Figures 32 and 33), and
2.
be held long enough after CAS to meet the
RAM's data hold time parameter (tolV (Figures
32 and 34.)
Data set-up time margin is calculated in Equation 5, and
data hold time margin is given in Equation 6. Again,
these are margins, so a positive number indicates that
system timing requirements are met for worst-case timings. Data hold time is a function of the number of 8086
wait states, represented as N, as is the read data access
time margin. No wait states are required to meet this
parameter.
Write Data Set-Up Time Margin
(Equation 5.)
CPU WR Active to Data Valid Delay +
CAS Delay - Data Delay
TCLMLmin(8288) + tccmin(8203) TCLDVmax(8086) - TIVOVmax(8286) tosrnin(2164A-20)
10 + [3(40) + 25] - 110 - 30 - 0
15 '
Write Data Hold Time
(Equation 6.)
Margin (N = 0)
CPU Data Hold Time, from AMWC
Active + Data Delays - CAS Active Delay
(2 + N)TCLCL(5MHz) + TCLCHrnin(8284A)
+ TCHDXmin(8086) + TIVOVmin(8286)
- TCLMLmax(8288) - tccmax(8203) tOHmin(2164A-20)
2(200) + [;)(200) - 15] + 10
+ 5 - 35 - [4(40) + 85] - 45
308
[I] tp(74S373) is the greater of tPHL (from data) or
tpLH (from data) and is compensated for Vee and
temperature variations, and is derated for a
300pF load (T.1. spec is at 15pF).
tp(74S373) = 13ns + 0.05ns/ pF(300 - 15)pF
+ 2.75ns = 30ns.
Where 13ns is T.1. spec value
0.05ns/ pF is derating factor
for excess capacitive load
(300 - 15) is excess capacitive
load 2.75 is compensation for
T A and Vee variation
Ao
8086
74S32
WE
8282
(LOW
BYTE)
A'6·'9 lA......_-"-1 A
ADO.'51"11''''''!I--v1
WE
--f---J ~~~
STB
S2.S;.So~-II-~~~::-ii~~-_.J
RAM
01100
1----+H>-aI ,
READY
.....- - - - -.....D-...CLK
8286
OE
T
Figure 32. Write Data Set-Up and Hold Time Margins
3-137
AFN' 02200A
Ap·97A
11
CLK(8284A)
T2
\
\
1\
1\
TCLML
"
AMWC(8288)
\
tcc
\
CAS(8203)
_TCLDV_
ADo.,s(8086)
'V
ADDRESS
DATA
/1\
tOS---'
I-TIVOV
DATA BUS=
DIN(2164A·20)
I------------------------------
\V
/1\
VALID
Figure 33. Write Data Set·Up Time Margin
refresh cycle is in progress, how near it is to completion.
SACK is sampled by the 8284A Clock Generator Chip's
RDYI or RDY2 input. The 8284A can be programmed to treat these inputs as either synchronous or asynchronous inputs by tying its ASYNC input (pin 15)
either high or low, respectively. SACK must be treated
as asynchronous unless it has been synchronized to the
microprocessor's clock with an external flip-flop.
SACK SET·UP TIME MARGIN
As explained earlier, SACK (and XACK) are "handshaking" signals used to tell the microprocessor when it
may terminate the bus cycle in progress. Thus, SACK
timing determines how many wait states will be
generated, as opposed to how many wait states are'actually required for proper operation, which is determined by the read data access time for read cycles and by
the write data hold time for write cycles. If SACK
causes more wait states than are required, there is a performance penalty, but the system operates; if too few
wait states are generated, the system will not function.
SACK and XACK serve the same function; they differ
only in timing. XACK is Multibus compatible, and is
activated only when the read data is actually on the bus
(in a read cycle) or when the write data has been latched
into the RAM (in a write cycle). SACK is activated
earlier in the memory cycle than XACK to compensate
for delays in the microprocessor responding to this
signal to terminate the cycle. Use of SACK is normally
preferable, as it results in the fewest possible wait states
being generated. But in some systems, 'SACK will not
generate a sufficient number of wait states, so XACK or
a delayed form of SACK must be used. Note that the
number of wait states generated by SACK and XACK
will vary, depending on whether a refresh cycle is in progress when the memory cycle was requested, and if
SACK set-up time is shown in Figures 35 and 36, and is
calculated in Equation 7. This equation indicates that,
at worst case, one wait state will be generated (n = 1).
This satisfies the requirements of the system, namely
one wait state for reads and zero (or more) wait states
for writes.
SACK Set-Up Time Margin (N = 0)
(Equation 7.)
RD or WR Active to SACK Active Delay
(N)TCLCL(5MHz) + tpLHmin(7404)[II TCLMLmax(8288) - tCAmax(8203)
- tsumin(74S74)
.
o + 1 - 35 - [2(40) + 47] - 3
-164=> 1 wait state wi! be generated (N = 1)
3·138
We have only looked at "worst case" SACK set-up time
so far, to determine the maximum number of wait states
that will be generated (assuming no delays due to a
refresh cycle in progress). We should look at "best
[II Not specified - use 1 ns.
AFN 02200A
T2
CLK(8284A)
T3
~
T4
\
\
\
\
/
\
\
r-..
/
~
AMWC(8288)
\
\
tcc
CAS(8203)
\
»
"tI
TCHDX
ADo-ts(8086)
\
./
DATA VALID
!--TCVNX
~
»
..
\
DEN(8288)
f\--I-TEL?~
-TIVOV
DATA BUS
~
VALID
tOH
Figure 34. Write Data Hold Time Margin
intJ
AP·97A
Ao
8086
74532
8282
CPU
A'6.'9 )/1-----"-1
ADo·,s
RAM
01100
Figure 35. SACK Set·Up Time Margin
T3
T2
TW
CLK(8284A)
MRDC 1(8288)
AMWC
5ACK(8203)
CLK(74574)
Q(74S74)~
RDY1(8284A)
READY(8284A,8086)
Figure 36. SACK Set·Up Time Margin
3·140
AFN 02200A
Ap·97A
case" SACK timing also, to make sure enough wait
states are always generated. Note that in Figure 35,
SACK goes through an external 74S74 flip-flop; this
samples SACK on-half clock cycle earlier than the
8284A does (on the same clock edge that activates
MRDC or AMWC), effectively reducing SACK set-up
time by one-half clock period. This guarantees the prope~ number of wait state will be generated for "best
case" SACK timing. Adding this flip-flop does not increase the worst case number of wait states generated by
SACK.
In the case where a memory cycle is requested while a
refresh cycle is in progress, the memory cycle will be
delayed by a variable amount of time, depending on
how near the refresh cycle is to completion. This delay
may be as long as one full memory cycle if the refresh
was just starting; this time is about 650 ns, depending on
the 8203's clock frequency. SACK set-up, read data setup, and write data h'old times to the microprocessor's
clock are not the same as in the usual case where there is
no refresh interference. In this case, SACK is delayed
until the read or write cycle has been completed by the
RAM, so that there is no possibility of terminating the
cycle too soon.
RAM DATA OUT HOLD TIME MARGIN
The 8203 CAS output is only held valid for a fixed
length of time during a read cycle, after that the RAM
data outputs are 3-stated. This time is not long enough
to allow the 8086 to read the data from the bus, so the
data must be latched externally. This latch should be a
transparent type and should be strobed by XACK from
the 8203. Because the minimum time from XACK active
to CAS inactive is only IOns, a latch with a data hold
time requirement of 10 ns or less (such as a 74S373)
should be used (see Equation 9).
RAM Data Out Hold Time Margin,
(Equation 9.)
from XACK Active
tAcKmin(8203) + tOFFmin(2164A - 20)
- tHmin(74S373)[l]
10 + 0 - 10
o
OTHER CALCULATIONS
PCS SET-UP TIME MARGIN
The 8203's RD, WR, and ALE inputs must be qualified
by PCS in order to perform a memory cycle. If the PCS
active set-up time parameter (tpcs) is violated, the
memory cycle will be delayed. In this case all maximum
delays normally measured from command (tCR, tec,
tCN will be measured instead from PCS active and will
be increased by tpcs (20 ns). Minimum tCR, tcc, tCA
delays remain the same, but are measured from command or PCS whichever goes active later. If tpcs is
violated, care must be taken that PCS does not glitch
low while RD, WR, or ALE is active, erroneously triggering a memory cycle. tpcs is not violated in this
system, however (Equation 8).
PCS Set-Up Time Margin
(Equation 8.)
CPU Address Valid to Command Active
Delay - PCS Decode Time
TCLCL(5MHz) + TCLMLmin(8288) [Greater of TCLAVmax(8086) +
TIVOVmax(8282) or TCLLHmax(8288) +
TSHOVmax(8282)]
- tpffiax(8205) -tpcsmin(8203)
200 + 10 - [Greater of (110 + 30) or
(15 + 45)] - 18 - 20
32
3-141
Equations 3, 4, 6 and 7 may be solved directly for N,
where N is the number of wait states, to find how many
wait states are required at a given frequency. Alternatively, a number may be substituted for N and these
equations solved for the 8086's clock period, TCLCL,
to find the maximum microprocessor frequency possible
with N wait states. Note that the clock high and low
times (TCHCL and TCLCH)are also a function of'
TCLCL. Be sure to use the proper speed sele~tion of the
8086 in this calculation, as various A.C. parameters are
different and the result may be different for different
speed selections of the 8086, even at the same frequency.
Be sure to check the other equations at this frequency to
make sure they are OK, too.
Finally, for given values of TCLCL and N, Equations 3,
4, 6, and 7 may be checked to find the lowest 8203 clock
frequency which will allow the same system performance, if it is desired to operate at some frequency
other than the 25 MHz we assumed.
CONCLUSION
This design will operate with, at ~orst case, one wait
state (except for refresh) at microprocessor frequencies
up to 6 MHz, using slow' (200 ns access time) dynamic
RAMs. At 6 MHz, it is limited by a lack of SACK set-up
[1]
A 74S373 must be used to meet this timing requirement. Even though worst case margin is 0 ns,
this is not a critical timing, as valid data will hold
on the latch inputs for a considerable time after
the RAM outputs 3-state.
AFN' 02200A
Ap·97A
delayed so long that there is no longer enough data hold
time, measured from when WE goes active; or that the
WE active to CAS inactive delay spec or the RAM
(tRWU is violated. None of the control signals from the
8086 or 8288 bus controller satisfy both of these timing
constraints, so such a signal is generated, by flip-flop
AI1.1, which serves to delay AMWC from the bus controller by an amount of time equal to TCLCH (the low
time of the 8086's clock). Al 1.1 is also preset by AIO.1
at the end of the memory cycle. The Q output of AI1.1
is ANDed with WE from the 8203 by A14.1 to form a
delayed RAM WE. As in the previous example, this
signal is then ANDed with BHE and AO to form the
WE for the high and low bytes of RAM, respectively.
time. At 5 MHz, the 8203 can be operated at any clock
frequency from 18.432 MHz to 25 MHz, still with only
one wait state.
Example 2. 8086 Alternate
,Configuration System (5 MHz)
Figure 37 shows another 8086 Max mode system at 5
MHz, but this time using the Alternate Configuration,
which allows it to operate with no wait states (except for
refresh).
The system in the previous example was limited by
SACK set-up time. SACK set-ug time can be improved
by sampling SACK later; this has been done by changing
the clock edge used to sample SACK, allowing roughly
V, clock period longer. SACK set-up time (and read data
access time and write data hold time) margin can also be
improved by activating the RD or WR inputs of the 8203
earlier in the 8086's bus cycle; this is the purpose of the
extra logic in Figure 37 (I.C.s A8 - All). These generate
advanced RD and WR signals timed from the faIling
edge of ALE, which occurs roughly Yl clock period
sooner than the MRDc and AMWC are generated by the
8288 Bus Controller. Altogether, these changes allow
about one 8086 clock period more set-up time for SACK.
A total of four packages (three 14-pin and one 16-pin)
of TTL logic are required.
The dynamic RAM interface timings are identical to the
last example (Equations I (a)-(h»; 2164A-20 RAMs will
be used again.
ADDRESS SET-UP .AND HOLD TIME MARGINS
Let's look at this logic in more detail. An Intel 8205
(A8) is used to decode the 8086's status outputs SO-2. An
opcode fetch, memory read, or memory write decode to
8205 outputs 4, 5, and 6, respectively. These outputs go
to the D inputs of two 74S74 flip-flops. The Q output of
flip-flop AIO.2 is an advanced memory read signal and
the Q output of AI1.2 is an advanced memory write
signal. As shown in Figure 37, the 8203 is not activated
for opcode fetches, but it can be if 8205 outputs 4 and 5
are ORed with the unused 74S00 gate (A9.4) and the Q
output of AIO.2 used instead of Q. Both flip-flops are
clocked by the faIling edge of ALE to generate the advanced commands. Flip-flop AIO.1 is clocked by the
trailing edge of either AMWC (Advanced Memory
Write Command) or MRDC (Memory Read Command)
from the 8288 bus controller (A6), indicating that the
8086 has completed the memory cycle. AIO.1, in turn,
presets both the AIO.2 and All.2 flip-flops to terminate
the advanced memory read and write signals to the
8202A. AIO.1 is then preset to its initial state by ALE
going active at the start of the next bus cycle.
Because RAM write cycles are started very early in the
8086's bus cycle using this logic, the 8203 will activate
CAS to the RAMs (latching write data) before the data
is valid from the 8086. This requires delaying WE to the
RAMs and performing a "late write" (explained earlier
under Dynamic RAMs) in order to allow more time for
the write data to arrive. But the WE signal must not be
Address set-up and hold time margins are given in
Equations 10 and II, respectively. An 8086-2
microprocessor has been used instead of the standard
8086, as this speed-selected part gives better address setup to RD or WR times, which this design needs since it
uses advanced RD and WR commands.
(Equation 10.)
Row Address Set-Up Time Margin[l]
CPU Address to Adv. RD Delay
+ RAS Delay - Address Delays
TCLCHmin(8284A) + TCHLLmin(8288)[2]
+ tPLHmin(74S00) [3] + tpHLmin(74S74)[2]
+ tCRmin(8203) - [Greater of
TCLAVmax(8086 - 2) + TIVOVmax(8282)
or TCLLHmax(8288) + TSHOVmax(8282)]
- tAomax(8203) - tAsRmin(2164A-20)
[V,(200) - 15] + 2 + 1 + 2 + [(40) + 30]
- [Greater of (60 + 30) or (15 + 45)] - 40 - 0
63
Read or write cycles only. Eq. Ib gives this timing
for refresh cycles.
[2) Not specified - use 2 ns.
[3] Not specified - use Ins.
[I]
3-142
AFN' 02200A
AP·97A
Address Hold Time Margin (N = 0)
(Equation 11.)
CPU Address Hold Time from Adv. RD
Active - RAS Inactive Delays
(3+ N)TCLCL(5MHz) + TCHCLmin(8284A)
+ TCLLHmin (8288)
+ TSHOVmin(8282) - TCLMLmax(8288)
- tccmax(8203) - tRsHmax(8203)
(3)200 + [\.1(200) + 2) + 2 + 5 - 35
- [4(40) + 85) - [5(40) + 20)
175
READ DATA ACCESS TIME MARGIN
Read data access time margin is shown in Equation 12;
no wait states are required for read cycles, even with 200
ns access time RAMs.
Read Data Access Time
(Equation 12.)
Margin (N = 0)
Adv. RD to Data Valid Delay - CAS Delay
- Read Data Delays
(2+N)TCLCL(5MHz) + TCHCLmin(8284A)
- TCHLLmax(8288) - tpLHmax(74SOO)
- tpHLmax(74S74) - tccmax(8203)
- tCAcmax(2164A-20) - tplllax(74S373)
- TIVOVmax(8286) - TDVCLmin(8086-2)
(2)200 + [\.1(200) + 2) - 15 - 5 - 10
- [4(40) + 85) - 110 - 30 - 30 - 20
3
WRITE DATA SET-UP AND HOLD TIME MARGINS
Write data set-up and hold times are shown in Equations 13 and 14, respectively. No wait states are required
during write cycles. Note that write data set-up has been
guaranteed by delaying WE from the 8203 with clocked
AMWC from the bus controller and performing "late
write" cycles; write data set-up time would not be
satisfied otherwise. Equation 15 verifies that WE has
not been delayed. too long to meet the RAM's WE active
to RAS inactive s~t-up time (tRWU. The RAM's WE active to CAS inactive set-up time (tcwu is also satisfied,
since CAS does not go inactive until at least 20 ns after
Write Data Hold Time
(Equation 14.)
Margin (N = 0)
CPU Data Hold Time from Clocked AMWC
+ Data Delays - WE Delays
(2 + N)TCLCL(5MHz)
TCHDXmin(8086-2) + TIVOVmin(8286) - tpHLmax(74S74) - (2)tpHIJIlax(74S32)
- tDHmin(2164A-20)
(2)200 + 10 + 5 - 10 - (2)7 - 45
346
WE Active Set-Up Time Margin
(Equation 15.)
to RAS Inactive
TCHLLmin(8284A)[I) + tpLHmin(74SOO)[2)
+ tccmin(8203) + tRsHmin(8203)
- tSKEw(74S74)[3) -(2)tpHLmax(74S32)
- tRwLmin(2164A-20) - TCLCL(5MHz)
2 + 1 + [3(40) + 25) + [5(40) - 30)
-2-(2)7-50-200
52
SACK SET-UP TIME MARGIN
Equation 16 shows that SACK set-up time is satisfied;
no wait states will be generated for read or write cycles
(except for refresh).
SACK Set-Up Time Margin (N = 0)
(Equation 16.)
(1 + N)TCLCL(5MHz) - TCHLLmax(8288)
- tpLHmax(74SOO) - tpHLffiax(74S74)
- tcAmax(8203) - tsumin(74S74)
200 - 35 - 5 - 10 [2(40) + 47) - 3
20
RAS.,
Write Data Set-Up Time Margin
(Equation 13.)
CPU Data to ClockeQ AMWC Set-Up
+ WE Delays - Data Delays
TCLCHmin(8284A) + tpHLmin(74S74)[I)
+ (2)tpHLmin(74S32)[I)
- TCLDVml\X(8086-2) - TIVOVmax(8286)
- tDgmin(2164A-20)
[1'3(200) - 15) + 2 + (2)2 - 60 - 30 - 0
34
3-143
[I) Not specified - use 2 ns.
(2) Not specified - use 1 ns.
(3) tSKEw(74S74) is max. skew betweentpHdQ output, from CLK) of iwo Q outputs in
same package - use = 2 ns.
AFN:022OOA
A16-19
A'8 '9
A12
~~------A-D~D~R~E~S~S~B~U~S--------~------------~~~,IA02
00
15
ADo·,s
A1
8284A
ASYNC
'T
>z
OW
a:
74S13~
A2
8086·2
0
"z
i
Figure 37. 8086 Alternate Configuration System
WE
RAM
2164A
·20
DIN
Ap·97A
PCS Set·Up Time Margin
(Equation 17.)
CPU Address Valid to Adv. RD or Adv.
WR Delay - PCS Decode Time
TCLCHmin(8284A) + TCHLLmin(8288)[I]
+ tpLHmin(74S00) + tpHLmin(74S74)[1]
- TCLAVmax(8086-2) - TIVOVmax(8282)
- tpmax(74S138[3] - tpcsmin(8203)
[%(200) - 15] + 2 + 1 + 2 - 60 - 30 - 12 - 20
1
PCS SET·UP TIME MARGIN
PCS set-up time for the 8203 (tpcS> is satisfied, but not
with as much margin in the last example (Figure 17).
[I] Not specified - use 2 ns.
[2] Not specified - use 1 ns.
[3] Must use 74S138 to maintain PCS Set-Up
Time Margin.
This is because the RD and WR commands are activated
earlier in the microprocessor's bus cycle, leaving less
time to decode PCS from the address bus.
CONCLUSION
This design will operate with a guaranteed zero wait
states up to 5 MHz using slow (200 ns access time)
RAMs. At this frequency, it is limited by both read and
write data set-up times, and to a lesser extent, by SACK
set-up time. Using faster RAMs will not raise the maximum frequency, as write data and SACK set-up times
are not affected by the RAM speed. The 8203 operating
frequency must be 25 MHz.
This design can be used (with some modifications) to
allow one wait state performance up to 8086 clock frequency of 8 MHz.
3-145
AFN 02200A
inter
APPLICATION
NOTE
AP·141
October 1981
3.146
order number:210315.001
AP-141
ABSTRACT
DESIGN
This Application Note shows an error corrected
dynamic RAM memory design using the 8203 64K
Dynamic RAM Controller, 8206 Error Detection and
Correction Unit and 150 ns 64K Dynamic RAMs with a
minimum of additional logic.
Figure I shows a memory design using the 8206 with
Intel's 8203 64K Dynamic RAM Controller and 150 ns
64K Dynamic RAMs. As few as three additional ICs
complete the memory control function (Figure 2).
The goals of this design are to:
1. Control 128K words x 16 bits (256 KB) of 64K
dynamic RAM.
2. Support 150 ns dynamic RAMs.
3. Write corrected data back into dynamic RAM when
errors are detected during read operations.
4. To use a minimum of additional logic.
It is not the goal of this design to:
I. Provide the maximum possible performance.
2. Provide features like error logging, automatic error
scrubbing and dynamic RAM initialization on
power-up, or diagnostics, although these features
can be added.
h
V
h
Bo AH AL OUT ~ A7·Ao
• •
HIGH
RD
RASO
V RAS BYTE
WR 8203 RAS1
RAS RAM
(16)
CS
CAS
-+< ~~S 2164A
XACK
01
DO
.-< ;:>-.
Ao
BHE
LOW
-<: RAS BYTE
-<:
RAM
RAS (16)
--.
1
10ET
82B86 A'I'
SYSTEM DATA BUS
Figure 1. 8203/8206 Memory System
3·147
AFN02114A
AP-141
-In order to do read-modify-writes in one cycle, the
dynamic RAM's CAS strobe must be active long enough
for the 8206 to access data from the dynamic RAM, correct it, and write the corrected data back into the
dynamic RAM. CAS active time is an 8203 spec (teAs),
and is dependent on the 8203's clock frequency. The
clock frequency and dynamic RAM must be chosen to
satisfy Equation 1.
R/W is generated by delaying CAS from the 8203 with a
TTL-buffered delay line. This allows the 8206 sufficient
time to generate the syndrome; this deiliy, tDELAY j,
must satisfy Equation 2.
(Eq.2)
Dynamic
RAM
tDELAY 1 ~
(Eq. 1)
Dynamic
RAM
8203
tCAsmin 2:
tCAC
5(54)-10 2:
85
260
2:
251
8206
8206
Dynamic Dynamic
RAM
RAM
+ TDVQV + TQVQV +tos +
+ 67 +
59
+ 0 +
tCWL
The 8203 itself performs normal reads and writes. In
order to perform read-modify-writes, all that is needed
is to change the timing of the WE signal. In thi's design,
WE is generated by the interface logic in Figure 2-the
8203 WE output is not used. All other dynamic RAM
'control signals come from the 8203. A 20-ohm damping
resistor is used to reduce ringing of the WE signal. These
resistors are included on-chip for all 8203 outputs.
150
2:
85
+
150
2:
119
'"
After R/W goes low, sufficient time is allowed for the
8206 to generate corrected check bits, then the interface
logic activates WE to write both corrected data and
check bits into dynamic RAM. WE is generated by
delaying CAS from the 8203 with the same delay line
DEL!~LLINE
50 100 150 200 250
'--____...2""0,.0_ WE
I
BMo
BHE~------------~-r--~-J
CS-+---'I:><>--'
RAM
R/W ] ARRAY
Ao
SYSTEM {
ADDRESS
BUS
DEL~~~~
34
In the event that an uncorrectable error is detected, the
8206 will force the Correctable Error (CE) flag low; this
may be used as an interrupt to the CPU to halt execution and/or perform an error service routine. In this
case the 8206 outputs data and check bits just as they
were read, so that the data in the dynamic RAM is left
unaltered, and may be inspected later.
The interface logic generates the R/W input to the 8206.
This signal is high for read cycles and low for write
cycles. During a read-modify-write cycle, R/W is first
high, then low. The falling edge of R/W tells the 8206 to
latch its syndrome bit& internally and generate corrected
check bits to be written to dynamic RAM. Corrected
data is already available from the DO pins. No control
signals at all are required to generate corrected data.
C A S - IN
8206
+ TDVRL
The 8206 uses multiplexed pins to output first the syndrome word and then check bits. This same R/W signal
may be used to latch the syndrome word externally for
error logging. The 8206 also supplies two useful error
signals. ERROR signals the presence of an error in the
data or check bits. CE tells if the error is correctable
(single bit in error) or uncorrectable (multiple bits in
error).
40
..
8203
(CAC
~~~TROL
BM1
-]
gYST~M '--------------------~---:T::: ~~~TROL
C NT:U; {
WR
iW """T_-<.tl-.-"
Figure 2. Interface Logic
3-148
AFN02114A
inter
AP·141
A7.AOJ<:
X
ROW
COLUMN
X
\ ~----------------~/
m
\ '---------------/
CAS
00- -
-
-
-
-
-
-
<
)-
VALID
X
01
VALID
X,,--_
Figure 3. Single·Cycle Read·Modify-Write
whole word plus check bits into dynamic RAM. A byte
write is implemented as a Read-Modify-Write.
used to generate R/W. This delay, tDELAY 2, must be
long enough to allow the 8206 to generate valid check
bits, but not so long that the tCWL spec of the RAM is
violated. This is expressed by Equation 3.
Why bother with error correction on the old word? Suppose a bit error had occurred in the half of the old word
not to be changed. This old byte would bl; combined
with the new byte, and new check bits would be generated for the whole word, including the bit in error. So
the bit error now becomes "legitimate"; no error will be
detected when this word is read, and the system will
crash. You can see why it is important to eliminate this
bit error before new check bits are generated. Byte
writes are difficult with most EDC chips, but easy with
the 8206.
(Eq.3)
8206
tDELAY I
150
8203
+ TRVSV ~
+
42
,;
192
,;
tDELAY 2 :::; tcAsmin -
200
,;
260
200
,;
220
Dynamic
RAM
tC~VL
40
Unlike other EDC chips, errors in both data and check
bits are automatically corrected, without programming
the chip to a special mode.
Since the 8203 terminates CAS to the dynamic RAMs a
fixed length of time after the start of a memory cycle, a
latch is usually needed to maintain data on the bus until
the 8086 completes the read cycle. This is conveniently
done by connecting XACK from the 8203 to the STB in. put of the 8206. This latches the read data and check
bits using the 8206's internal latches.
Referring again to Figure 2, the 8206 byte mark inputs
(BMo, BMI), are generated from AO and BHE, n:spectively, of the 8086's address bus, to tell the 8206 which
byte is being written. The 8206 performs error correction on the entire word to be modified, but tri-states its
DO/WDI pins for the byte to be written; this byte is.
provided from the data bus by enabling the corresponding 8286 transceiver. The 8206 then generates check
bits for the new word.
The 8086, like all 16-bit microprocessors, is capable of
reading and writipg single byte data to memory. Since
the Hamming code works only on entire words, if you
want to write one byte of the word, you have to read the
entire word to be modified, do error correction on it,
merge the new byte into the old word inside the 8206,
generate check bits for the new word, and write the
During a read cycle, BMo and BM I are forced inactive,
i.e., the 8206 outputs both bytes even if 8086 is only
reading one. This is done since all cycles are implemented as read-modify-writes, so both bytes of data
(plus check bits) must be present at the dynamic RAM
data input pins to be rewritten during the second pha,se
of the read-modify-write. Only those bytes actually be-
3-149
AFNO~114A
intJ
AP·141
ing read by the 8086 are driven on the data bus by enabling the corresponding 8286 transceiver.
The output enables of the 8286 transceivers (OEBO,
OEBI) are qualified by the 8086 RD, WR commands
and the 8203 CS. This serves two purposes:
1. It prevents data bus contention during read cycles.
2. It prevents cOlltention between the transceivers and
the 8206 DO pins at the beginning of a write cycle.
CONCLUSION
Thanks to the use of a 68-pin package, the 8206 Error
Detection and Correction Unit is able to implement an
architecture with separate 16 pin input and output
busses. The resulting simplification of control requirements allows error correction to be easily added to an •
8203 memory subsystem with a minimal amount of
interface logic.
3-150
AFN02114A
APPLICATION
NOTE
© Intel Corporation, 1979-
3-151
Ap·46
9800752
INTRODUCTION
Complex electronic systems require the utmost in reliability. Especially when the storage and retrieval of
critical data demands faultless operation, the system
designer must strive for the highest reliability possible.
Extra effort must be expended to achieve this high
reliability. Fortunately, not all systems must operate with
these ultra reliability requirements.
1.000.000
100 YRS
0.01%/1000
HR
100.000
10YRS
The majority of systems operate in an area where system
failure ranges from irritating, such as a video game
failure, to a financial loss, such as a misprinted check.
While these failures are not hazardous, reliability is
important enough to be designed into the system.
10.000
1 YR
0
...
...:Ii
::I:
III
1,000
1 MONTH
A memory system is one of the system components for
which reliability is important. Also, it is one of the few
system components which can be altered to greatly'
enhance its reliability. The purpose of this report is to
examine different methods of error encoding, especially
Error Correction Codes (ECC), to increase the reliability
of the memory system.
lWK
100
NUMBER OF DEVICES
SYSTEM RELIABILITY
Individual device reliability is the foundation of memory
system reliability. Reliability is expressed as mean time
between failures. The mean time between failures
(MTBF) of a system is a function of the number of
devices and the device failure rate. Failure rate of the
memory device can be obtained from the reliability
report on the specific device. MTBF of the device is:
To
I
=;:-
and MTBF of the system is approximately:
To
and dividing by the size of the RAM. To illustrate,
assume a I megaword memory system with a word width
of 32 bits, implemented with Intela:
[2]
where Ts = MTBF of the system
D = number of devices in the system
As the number of devices required to construct a system
becomes larger, the system MTBF becomes smaller.
A plot of system MTBF as a function of the number of
memory devices 4s shown in Figure I for different failure
rates. Included for reference are the failure rates of the
Intel® 2104A 4Kx I RAM and the Intel® 2Jl7 16Kx I
RAM. Using RAMs which are organized one bit wide,
the amount of devices required for a system is 'calculated
by multiplying the number of words by the word length
3-152
Equation 2 showed that system MTBF is increased when
fewer devices are used. A one megaword memory having
32 bit wide words can be constructed with Intel 2117 16K
RAMs. In this case one fourth as many devices are
required - 2048 devices. From Equation 2, the expected
MTBF should be four times as large - 2668 hours. It is
not. The failure rate from Figure I for this system is 2000
hours. Different device failure rates account for this
difference. The failure rate of the 16K is not yet equal to
that of the 4K. Memory device reliability is a function of
time as shown in Figure 2. Reliability improvement often
is a result of increased experience in manufacturing and
testing. In time, the failure rate of the 16K will reach that
of the 4K and one fourth as many devices will result in a
system MTBF approximately four times better.
One measure of a code is its efficiency. Efficiency is the
ratio of the number of bits in the encoded word to the
number of bits of data:
0.2
~
0.1
~iB 0.01
II: 0.01
~g 0.07
... " 0.08
0.05
Substituting N = M + K:
E --
~I
~l 0.04
..
M.±!.
M
[4J
where E = efficiency
0.03
All of the data are contained in the M bits. The K bits
contain no data, only validity checks. To maximize the
amount of data in the encoded word, the number of K
bits must be minimized. Examination of Equation 4
shows that the minimum value of K is zero. With K equal
to zero, the efficiency is unity. Efficiency is maximized,
but the word has no encoding bits. Therefore, it has no
capability to detect an error.
0.02
'72
'73
'74
'75
'78
'77
'78
'78
'80
YEAR
Fllure 2. Device FaUure Rate ... Funellon of Time.
As an example, consider a two bit word. It can assume 22
or 4 states, which are:
The failure rate of a system without error correction will
follow a similar curve over time. Indeed, in very large
systems built with large numbers of devices, the system
failure rate may be intolerable, even with very reasonable
device failure rates. To increase the system reliability
beyond the device reliability, redundancy coding techniques have been developed for detecting and correcting
errors.
State 1
State 2
State 3
State 4
All possible states have beeJ1 used as data; consequently
any error will cause the error state to be identical to a
valid data state.
Redundancy codes add bits to the data word to provide a
validity check on the entire word. These additional bits,
used to detect whether or not an error has occurred, are
called encoding bits. With M data bits and K encoding
bits, the encoded word width is N bits. Shown in Figure 3
is the form of the encoded word.
N
I
1111····1 III 1····11
L--M---'
11
Fllure 4. AU Slain of a Two-BII Word
REDUNDANCY CODES
i
00
01
10
The mechanics of the encoding bits create encoded words
such that every valid encoded word has a !'et of error
words which differ from all valid encoded words. When
an error occurs, an error word is formed and this word is
recognized as containing invalid data.
By adding one K bit to the two bit word error detectior
becomes possible. The value of the K bit will be such that
the encoded word has an odd number of ONES. As will
be explained later, this technique is "odd" parity.
L-.-K---'
The sum of the ONES in a word is the weight of the
word. Parity operates by differentiating between odd and
even weights. The encoded word will always have an odd
weight as a result of having an odd number of ONES.
Flaure 3. Encoded Word Form
Mathematically, N is related to M and K by:
N = M+K
[3J
If a single bit error occurs, one bit in the encoded word
will change state and the word will have an even weight.
Then in this example, all encoded states with an even
weight - an even number of ones - are error states.
where N = number of bits in the encoded word
M = number of data bits
K = number of encoding bits
Exactly how K is related to M, and the number of
required K bits depends on several factors which Will be
described later.
The value of the encoding bit or parity bit is found by
counting the number of ones - calculating the weight and setting the value of K to make the weight of the
encoded word odd. Referring to Figure 4, State 1 was 00,
3·153
the weight of this word is 0, so K is set to I and the weight
of the encoded word is odd. State 2 is 01, the weight is
odd already, so K is set to O. The weight of State 3 is
identical to that of State 2 so K is again set to O. Finally,
State 4 has an even weight (I + 1 = 2), thus K is 1. The
encoded states of the two bit data word are listed in
Figure 5.
Data
Encoding Bit
State I
00
State 2
State 3
State 4
OJ
I
0
0
10
II
M
State B
State D
K
To illustrate the error detection, Figure 6a lists all states
of the encoded data word and all possible single bit
errors. Because the encoded word is 3 bits long, there are
only 3 possible single bit errors for each encoded state.
MK
Figure 7. Bit Difference.
These two states have two bit positions which differ. This
difference is defined as distance and these two states have
State I
State 2
State J
State 4
C
001
010
100
III
Error States
000
000
000
011
101
011
110
101
110
011
101
110
PARITY
Figure 6.. All Possible Single-Bit Errors
Notice that every error state has an even weight, while the
valid encoded states have odd weights.
Converting all the values of these states to decimal
equivalents makes the errors more obvious as shown in
Figure 6b.
Error States
I
2
4
0
0
3
5
3
6
5
6
II::J
Figure 8. Minimum Distance of a Two-Bit Word
~-~-
0
00
01::J}
10::1
Distance of I
D
Encoded States
Valid States
(0)
A minimum distance of two between encoded states is
required for error detection. A re-examination of a word
with no encoding bits shows that the states have a
minimum distance of I (see Figure 8) .. No error detection
is possible because any single bit error will result in a
valid word.
Flgur. 5. Code Bits for All Possible States of a Two-Bit Word
II
I
a distance of two. Distance, then, is the number of bits
that differ between two words. The encoded words have
a minimum distance of two. Longer encoded words may
have distances greater than two but never less than two if
error detection is desired. The error states have a
minimum distance of one from their valid encoded state.
N
A
(0)
l!J I l!J
A minimum distance of two code is implemented with
Parity. Refer to previous section for an explanation.
Parity is generated by exclusive-ORing all the data bits in
the word, which results in a parity bit. This parity bit is
the K encoding bit of the word. If the word contains M
data bits, the parity bit is:
C
where C
b
7
3
5
6
Flgur. 6b. Decimal Representation of Errors
No error state is the same as any valid encoded state.
Identical error states ~an be found in several columns.
The fact that some error states are identical prevents
identification of the bit in error, and hence correction is
impossible. Importantly though, error detection has
occurred.
Figure 6a demonstrates another property of codes. Every
error state differs from its valid encoded state by one bit,
whereas each of the encoded states differs from the
others by two bits. Examine the encoded states labeled B
and D in Figure 6a and shown in Figure 7.
blED b2 ED b3 ED ... ED bm
parity bit
value in the bit position
The parity bit combines with the original data bits to
form the encoded word as shown in Figure 9. Encoded
words always have either "odd"~ parity, which is an odd
number of Is (an odd weight) or "even" parity which is
an even number of Is (an even weight). Odd and even
parity are never intermixed, so that the encoded words all
have either odd or even parity - never both.
When the encoded word is fetched, the parity bit is
removed from the word and saved. A new parity bit is
generated from the M bits. Comparing this new parity bit
with the stored parity bit determines if a, single bit error
has occurred.
3-154
Figure 9. Encoded Word Form
Consider the two bit data word whose value is "01."
Exclusive-NORing the two data bits generates a parity bit
which causes the encoded word to have odd parity:
C
=
0
Ell
I
C=O
ERROR CORRECTION
The encoded word becomes:
M
o
Classical texts on error coding contain proofs showing
that a minimum distance of three between encoded words
is necessary to correct errors. While this fact does not
describe the code, it does give an indication of the form
of the code.
'
K
L
In summary, single bit parity will detect the majority of
errors, but cannot be used to correct errors. Using parity
int~oduces a measure of confidence in the system. Should
a single bit error occur, it will be detected.
0
parity
LSB of data
Assume that an error occurs and the value of the word
becomes "110." Stripping off the parity bit and
generating a new parity bit:
transmitted parity
o
transmitted word
II
new parity of transmitted word = reI = 1
Correcting errors is not as difficult as it first appears. AS"
a result of a paper published by R. W. Hamming on error
correction the most widely used type of code is the
"Hamming" code. Using the same technique as parity,
Hamming code generates K encoding bits and appends
them to the M data bits. As shown in Figure II, this N bit
word is stored in memory.
III· .. ·····III[JIJ
generated parity"* transmitted parity
Note that the error could have occurred in the parity bit
and the final result would have been the same. An error
in the encoding bit as well as in the data bits can be
detected.
Although parity detects the error, no correction is
possible. This is because each valid word can generate the
same error state. Illustration of this is shown in Figure
10.
Correct Word
with Parity
001
I I I
oI 0
Possible
Single Bit
Error
oI
oI
oI
I
I"
I
Figure 10. Possible Errors
'----M---~'
Figure 11. Encoded Word Form
Thus far the mechanism is similar to parity. The only
difference is the number of K bits and how they relate to
the M data bits.
\
When the word is read from memory, a new set of code
bits (K ') is generated from the M' data bits and
compared to the fetched K encoding bits. Comparison is
done by exciusive-ORing as shown in Figure 12. Like
parity the result of the comparison - called the
syndrome word -.-:. contains information to determine if
an error has occurred. Unlike parity, the syndrome word
also contains information to indicate which bit is in error.,
Each of the errors is identical to the others and
reconstruction of the original word is impossible.
Parity fails to detect an even number of errors occurring
in the word. If a double bit error occurs, no error is
detected because two bits have changed state, causing the
weight of the word to remain the same.
Using the encoded wor'd "010" one possible double bit
error (DBE) is:
1 I
L-parity
Checking parity:
'-K----'
'------N --------'
~
ITIIO K
ITIIOK'
ITIIO
Syndrome
Figure 12. Syndrome Generation
The syndrome word is therefore K bits wide. The
syndrome word has a range of 2K values between 0 and
2K - I. One of these values, usually zero, is used to
indicate that no error was detected, leaving 2K - I values
to indicate which of the N bits was in error. Each of
these 2K - I values can be used to uniquely describe a bit
in 'error . The range of K must be equal to or greater than
N. Mathematically, the formula is:
The transmitted parity and the regenerated parity agree.
Therefore the technique of parity can det-ect only an odd
number of errors.
3-155
2K_I
~
N
but N
=
M+K
~
M+ K
and 2K - I
(5)
CODE DEVELOPMENT
Equation 5 gives the number of K bits needed to correct a
single bit error in a word containing M data bits. Ranges
of M for various values of K are calculated and listed in
Table I.
Single Corl'Kl/
Single Detect
Single Correct!
.. M<
<;M<
K
4
12
27
58
121
II
26
57
120
245
Contained in the syndrome word is sufficient information to specify which bit is in error. After decoding this
information, error correction is accomplished by
inverting the bit in error. All bits, including the encoding
bits - called check bits - are identified by their
positions in the word.
Double Del«r
4
II
26
57
10
Bit N
25
56
119
Bit 3 Bit 2 Bit I
I· ... ·1
L-______ N______
Tablet.
Range of M for Single Corfecl/Single Detect or Double Detect Codes
for Values of K
~
Figure 14. Positional Representalion of Blls In the Word
To detect and correct a single bit error "in a 16 bit data
word, five encoding bits must be used. As a result, the
total number of bits in the encoded word is 21 bits.
Efficiencies of single detect - parity - and single
detect! single correct codes as a function of the number of
data bits are shown in Figure 13. For large values of M,
the efficiency of single detect! correct is approximately
equal to that of the single detect code - parity.
Bits in the N bit word are organized as shown in Figure
14. Bit numbers shown in decimal form are converted to
binary numbers. From equation 5, this binary number
will be K bits wide. In Figure 15 is an example using a 16
bit data word. Because there are 16 data bits, M equals
16, K equals 5 and N equals 21. Shown in Figure 15 the
word is binary equivalent of the position. Notice that
where the M and the K bits are located is not yet
specified.
-OO\OO ..... -"O ... ..,.Mf"!-O O\~ .....
NN _ _ _ _ _ _ _ _ _ _
\Q ...
~f""IN_
N
Bit
Position
Value
101010101010101010101
001100110011001100110
110000111100001111000
000000111111110000000
II I I I 1000000000000000
2° LSB
2'
22
23
24 MSB
~~~~~~~~~~~~~~~~~~~~~
Figure 15. Binary Value of Bit Position.
E
=M,P
The syndrome word is the difference between the fetched
check bits and the regenerated check bits. Identification
of the bit in error by the syndrome word is provided by
the binary value of the bit position. The syndrome word
is generated by exclusive-DRing the fetched check bits
with the regenerated check bits. Any new check bits that
differ from the old check bits will set I s in the syndrome
word. To identify bit 3 as a bit in error, the syndrome
word will be 00011, which is the binary value of the bit
position. Weight is determined only by the Is in the bit
position chart in Figure 15, so they are replaced with an
X and the Os are deleted. The result is shown in Figure 16.
_00-.00 ..... -..0 ... ..,.1")"'1_0
N N - - - - - - - - - - O \ O O .....
\Q~..,.I")N_
~~~~~~~~~~~~~~~~~~~~~
1
10
20
30
40
50
60
N
1
x x x x x x x x x x x
xx xx xx xx xx
xxxx
xx
xxxx
xxxxxxxx
xxxxxx
70
DATA BtTs/WORD
Figure 13. Code Efficiency vs Data Word Size
CI
C2
C4
C8
CI6
Figure 16. Relationship of Data Bits and Check Bits.
3-156
The simplest mechanism to calculate the check bits is
shown in Figure 18. The data word is aligned on the
chart. Because weight and hence parity are affected only
by "Is," only columns containing "Is" are circled for
identification. The check bits are the result of odd parity
generated on the rows. For example, the CI row has three
"Xs" circled; therefore CI is 0 to kj:ep the row parity
odd. In this example, all other rows contain an even
number of circled "Xs;" therefore the remaining check
bits are "Is." These check bits are incorporated into the
data word, forming the encoded word. Performing this
function, the 21 bit encoded word is:
Check bit function is now defined by equating the check
bits to the powers of 2 in the binary positions. Each check
bit will operate on every bit position that has an X in the
row shown in Figure 16. Five bit positions - 1,2,4,8,
and 16 - have only one X in their columns. The corresponding check bits are in these respective locations.
Check bit CI is stored in Bit Position I, C2 is stored in
Bit Position 2, and C4, C8, and CI6 are stored in
positions 4, 8, and 16 respectively. Because each of these
positions has one X in the column, the check bits are
independent of one another. If a check bit fails, the
syndrome word will contain a single "1." A data bit
failure will be identified by two or more "Is" in the
syndrome word.
CI6
0101 0
The data bits are filled in the positions between the check
bits. The least significant bit (LSB) of data is located in
position 3.
1 000 0011 I
CI6
C8
o
o
•
= M2$M3$M4$MS$M9$MIO$MII$MI6$MI6
How the Hamming code corrects an error is best shown
with an example. In this example, a data word will be
assu111ed, check bits will be generated, an error will be
forced, new check bits will be generated, and the
syndrome word will be formed. Assuming the 16-bit data
word
Check bits are generated by overlaying the data word on
the Hamming Chart of Figure 16 and performing an odd
parity calculation on the bits matching the "Xs."
II
10
9
8
7
6
19
18
17
16
4
5
3
C8
CI6
20
I New check bits
o
Old check bits
o 0
While this "straight" Hamming code is simple, implementing it in hardware does present some problems.
First, the number of bits exclusive-ORed to generate
parity is not equal for all check bits. In the preceding
example, the number of bits to be checked ranges from
10 to S. The propagation delay of a 10 input exclusiveOR is much longer than that of a S input exclusive-OR.
.The system must wait for the longest propagation delay
path, which slows the system. Equalizing the number of
bits checked will optimize the speed of the encoders.
0101 0000 0011 1001
21
0
The result is 00111, indicating that bit position 7- data
bit 3 - is in error. Bit position of the error is indicated
directly by the syndrome word.
= MI2$MI3$MI4$MIS$MI6
12
0
CI6 C8 C4 C2 CI
CS = MS$M6$M7$MS$M9$MIO$MII
13
o
When the new check bits are exclusive-ORcil with the old
check bits, the syndrome word is formed:
C2 = MI$M3$M4$M6$M7$MIO$MII$MI3$MI4
14
C2 CI
CI6 C8 C4 C2 CI
CI = MI$M2$M4$MS$M7$M9$MII$MI2$MI4$MI6
IS
C4
A new set of check bits is generated on the error word as
shown in Figure 18 and is:
Parity check on the specified bits is used to generate the
check bits. Each check bit is the result of exclusive-ORing
the data bits marked with an "X" in Figure 18. Check
bits are generated by these logic equations:
,16
o
I
1 000 0011 I OPO I
0101 0
When the check bits are generated for storage, bits I, 2,
4, 8, and 16 are omitted from the generation circuitry
because they do not yet exist, being the result of
generation.
CI6
100
C2 CI
Forcing an error with bit position 7 - data bit 4:
Data Bit 2 is stored in position S - position 4 is a check
bit. Figure 17 shows the positions of data bits and check
bits for sixteen bits of data.
C4
C4
C8
IS
14
13
12
II
10
9
8
7
6
I
2
,
5
C4
4
Data Bits
C2 CI
3
Figure 17. Data and Check Bit Positions in the Encoded Word.
3-157
2
I
Check BIts
PosItion
16-
15
X
14
X
X
X
13
X
12
CI6
X
X
X
X
X
X
10
II
X
X
C8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
C4
X
X
X
X
X
X
X
C2
CI
CI
X
X
X
X
C2
C4
X
X
X
C8
CI6
X
Figure 18a. Ha",mlng Chart.
Bit Position 21 20
Data Bit 16 15
19
14
18
13
17 16 15
12 CI6 II
14
10
13
9
12
II
10
9
~
C8
4
2
4
C4
I
W",","~; f r ~: >~ ~ ~ ~:: ~
Ww""",W
~~ ~~
:
;:;
~ ~ ~~ ~
,
I
;
~
C2 CI
CI 0
C2
C4
C8 I
CI6 I
o
I
CI
C2
C4
C8
CI6
~
:
I
0
0
I
Figure 18b. Check Bit Generation.
Secondly, two bits in error can cause a correct bit to be
indicated as being in error. For example, if check bits CI
and C2 failed, data bit I would be flagged as a bit in
error.
detectable as a douple bit error by performing a parity
check on the syndrome word. If two data bits fail, again
the syndrome word has an even weight - a detectable
error.
Because of these two difficulties, the Error Correction
Code (ECC) most commonly used is a "modified"
Hamming code is most widely used which will detect
double bit errors and correct single bit errors.
Adding one additional check bit to the correction check
bits provides the capability to detect double bit errors.
The number of encoding or check bits required to detect
double bit errors and correct single bit errors is:
2N -
1
2M~~
SINGLE BIT CORRECT /
DOUBLE BIT DETECT CODES
Substituting M + K for N:
Modern algebra can be used to prove that a minimum
distance of four is required between encoded words to
detect two errors or correct a single bit error. An excellent
text on this subject is Error Correcting Codes by Peterson
and Weldon.
One possible double bit error is tWQ check bits. Using
straight Hamming code, the circuit would "correct" the
wrong bit. Double error detection techniques - modified
Hamming codes - prevent this by separating the
encoded words by a minimum distance of fpur. As a
result each data bit is protected 'by a minimum of three
check bits, so that the syndrome word always has an odd
weight. Therefore, even weight syndrome words cannot
be used. When two check bits fail, the syndrome word
has two "Is" or an even weight. Even weight is
2K-l;;. M+K
(6)
Equation 6 is similar to equation 5, which describes single
bit correct and detect except for the left side of the
inequality, which shows one additional encoding bit is
required. For single bit detect and correct the left side of
the inequality was 2K. Table I also lists the ranges of M
for values of K, for a direct comparison to single bit
detect and single bit correct codes.
3-158
Figure 13 includes the efficiency curve for single bit
correct/double bit detect (SBC/DBD) codes for vlllues of
M. As would be expected, beclluse of the additional
encQding bit the efficiency is slightly lower. For large
values of M, the efficiency of this code approaches unity
like the two other curves.
Syndrome words for the SBC/DBD code are developed
like the straight Hamming code, except that syndrome
words do not map directly to bit positions. The syndrome
word has an odd weight and does not increment like
straight Hamming code. In addition, implementation
considerations can impose constraints. For example, the
74S280 parity generator is a nine input device. If a check
bit is generated from ten bits, extra hardware is required.
Empirical methods can be used to form the syndrome
words. All possible states of the encoding bits are listed
and those with an even weight are stricken from the list.
Again like Hamming code, states'which have a weight of
one are used for syndrome words for check bits. For a
sixteen bit data word, six check bits are required. Figure
19 lists the possible states of syndrome words for a 16 bit
data word.
C6 C5 C4 C3 Cl Cl
100
I 0
0
I
000
I
0
0
I
I 0 0
0
0
I
0
0 0
I
0
o
o
o
o
o
o
o
I
0
o
o
o
o
0
0
0
o
0
0
0
0
0
0
0
0
I
o
o
o
o
0
0
0
0
0
I
0
I
I
0
0
0
0
0
0
0
0
I
I
0
0
0
0
0
0
I
0
0
0
0
0
0
0
0
I
0
0
0
0
0
0
0
0
Figure 19. Possible Syndrome Words
In Figure 19 only twenty syndrome words for data bits
are listed, because the possible words with a weight of 5
were eliminated so that every data bit w:>uld have only
three bits protecting it. This simplifies the hardware
implementation. If there are more than 20 data bits,states with a weight of 5 n,lust be used. All states listed in
Figure 19 are valid syndrome words, so that the problem
becomes one of selecting the optimum set of syndrome
words. To minimize circuit propagation delay the
number of data bits checked by each encoding bit should
be as close as possible to all the others.
The syndrome words can be mapped to any bit position,
providing that identical code generations are done at
storage and retrieval times. Syndrome word mapping
may be arranged to solve system design problems. For
example. in byte oriented systems the lower order
syndrome bits are identical, so that the circuit design may
be simplified by using these syndromes to determine
which bit is in error, and the higher order syndromes to
determine which byte is in error. Double bit detect/single
bit correct code is implemented in hardware as a straight
Hamming code would be.
DESIGN EXAMPLE
To illustrate code development, the design example uses
single bit correct/double bit detect code on a 16 bit data
word. In addition to the memory, the ECC system has
five components: write check bit generator, read check
bit generator, syndrome generator, syndrome decoder,
and bit correction. Connected together as shown in
Figure 20, these components comprise the basic system.
Features can be added to the system to enhance its
performance. Some systems includ~ error logs as a
feature. Because the address of the error and the errors
are known, the address and the syndrome word are saved
in a non-volatile memory. At maintenance time this error
log is read and the indicated defective devices are
replaced. Being a basic design, this example does not
include an error log.
Write check bits are generated when data are written into
the memory, while read check bits are generated when
data are read from the memory. Off-the-shelf TTL is
used to implement the design. Check bits are generated
by performing parity on a set of data bits, so that this
function is performed by 74S280 9-bit parity generators.
One parity generator for each check bit is required.
Because the read and write check bit generations are the
same, the circuits are similar. One minor difference
should be noted. In, this example, the check bit will be
formed from parity bn eight data bits. The 74S280 parity
generator has nine inputs; therefore, the write check bit
generator will have the extra input grounded while the
read generator has as an input the fetched check bit.
Developed directly in the read check bit generator is the
syndrome bit, which saves one level of gating. Figure 21
shows the identical results of generating the syndrome bit
by exclusive-ORing the fetched check bit with the
regenerated check bit and forming the syndrome bit in
the read check bit generator.
Implementing the syndrome generator word in this way
reduces the circuit propagation delay by approximately
10 nanoseconds. This implementation imposes a
restriction on the code to be used - the check bit must be
formed from no more than eight data bits.
3-159
r'-
,16
. DATA OUT
DO(X)
BUS
16
B(X)
CORRECTOR
DECODER
, 16
DATA IN
16
DI(X)
READ
CHECK BIT
GENERATOR
DATA OUT
~
SYNDROME
GENERATOR
MEMORY
WRITE
CHECK BIT
GENERATOR
~
MD(X)
16
I
'S(X) { 6
6
..",6
CHECK BITS
OUT
~
,
C(X)
Figure 20. Block Diagram of ECC System.
S280
DATA BITS
FETCHED CHECK BIT""""\~
FOR CHECK BIT
GENERATION
REGENERATED -/L/"'SvNDROME
CHECK BIT
S86
BIT
1000
FETCHED
CHECK BIT
SYNDROME
BIT
Figure 21. Syndrome Bit Generation.
While there are twenty possibilities for syndrome words,
only 16 are needed. Each row contains ten "Is" and each
column contains three "Is." Four columns are
eliminated but in a way that each row contains eight
"Is." When the columns are matched to data bits, the
"Is" i,n each row define inputs to the 745280 parity
generators for the given check bit. Eliminating the two
columns from each end results in sixteen columns with
each row having eight "Is." These remaining sixteen
columns which match the data bits are rearranged in
Figure 23 for convenience of printed circuit board layout
and assigned to the data bits. The syndrome words for
check bits are also shown for complete code
development.
Figure 19 listed the possible syndrome words for a 16 bit
data word. These are relisted in Figure 22 with the
syndrome words for the check bits and the zeros deleted.
CI
C2
C3
C4
C5
C6
II
I I
II I
I
I I
I
II
I
I I
I
I I
I I
II I
II I
II I
II II
II I I II
I I I I I II I I I
Figure 22. Possible Syndrome Words with Three Check Bits.
Data Bit
MI6 MIS MI4 MI3 MI2 Mil MIO M9 M8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
M6 M5
X
X
X
X
X
X
X
Cl
X
X
X
X
X
M2 MI
X
X
X
X
M4 M3
X
X
X
X
X
M7
X
X
X
C2
C3
C4
C5
C6
CI
C2
X
C3
X
X
C4
X
X
C5
X
X
,X
Figure 23.
3·160
X
X
X
X
X
C6
With this information the check bit generators can be
designed. Figure 24 depicts write check bit generators
while Figure 25 depicts read check bit generators.
M02 •
M03 •0 1 8 I EVEN
M
M04 :
SlI
M05 • 5280
M06 •
rooo
M07 •
M08 :
56
C6
I
Double bit error detection is accomplished by generating
parity on the syndrome bits. Except for the syndrome
word of ()()()()()() - no error - even parity wi\l be the
result of a double bit error. Hardware implementation is
shown in Figure 26. OR-ing the syndrome detects the
zero state, which has even parity and prevents flagging
this state as a double bit error.
M08 •
M09 •0 7 8 IEVEN
M
MOlD :
SlI
MOll
• 5280
:
=g~~
M014
C5
Decoding the syndrome word must be done to invert the
one bit in error. Combinational logic will decode only
those syndrome states which select the one of sixteen bits
for correction. Figure 28 shows the logic of the decoder.
:
I
M05
•
M06 •0 4 8 I EVEN
M
M012
:
"S4
M013 • 5280
:
=g~:
011
M016
A
013
:
C4
016
018
0110
0112
0111
0116
M03 •
M04
'0 2 8 IEVEN
M
M09 :
~
MOll
• 5280
roOD
Cl
:
=g~~
g:~:
M016
C3
•
I
IOOO
53
M02 •
M05 •
I EVEN
MD18
M07 :
~
M09 • 5280
C2
I
:
=g~~
M015
013
014 1 2 [ J
0
019
0111 .
5280
0113
rOOD
g:~~
C3
:
C2
IOOO
52
I
M03 •
M06 •0 1 8 rEVEN
M
MD8 :
~
MD10 • 5280
I
015
016
0I[J4
0112
0113
5280
g:~~
WOO
54
I
5280
012 I B - A
O
015
017
019
5280
0110
rooD
DIU
IOOO
55
=gg :
WOO
MD16
:
51
Cl
I
Figure 25. Read Check Bit Generators
rooD
.
C4
I
017
018
019
0110
0111
0112
Dl13
0114
51
52
53
54
55
56
A
5280
IOOO
A
IOOD~-------------DBE
5280.
rEVEN~::::::;:r==>
----,I
C5
~""H_ _ _
SBE
5280
530. NO ERROR
IODO
C6
Figure 26. Double Error Decoder
Figure 24. "'rite Chf(.'k Bit Generator,
3-161
~::::::)D--0ATA BIT 1
~:::::)D---0ATA BIT 9
~~:::::)D-- DATA BIT 2
M10
---4,D-
810--1
~~:::)D--- DATA BIT 3
DATA BIT 10
M 1 1 - - ; D - - DATA BIT 11
811----J
~:::::)D--- DATA BIT 4
M12
~~::::)D---0ATA BIT 5
M13
--4D----;D---
812---1
B13--j
~:::::)D--- DATA BIT 6
DATA BIT 12
DATA BIT 13
~D- DATA BIT 14
M14
814--J
~;::::)D---DATA BIT 7
M15-4D-OATABIT15
B15~,
~:::::)D--- DATA BIT 8
M16 - - - 4 D - - DATA BIT 16
816
----I
Figure 27.Correction Circuil.
lK
ECC
, -_ _- , I N H ?
MOl
M02
M03
M04
M05
M06
M07
M08
C6
A
M07
M08
M09
M010
MOll
M012
A
~_....._
MO{X)- UNCORRECTED DATA
FROM MEMORY
.......,
5280
1000
5280
1000
M013
M014
C5
M04
MD5
M06
M012
M013
A
54
5280
MD14
1000
M015
M016
C4
M02
M03
M04
M09
MOll
M013
M015
M016
C3
A
MOl
M02
M05
M07
M09
MOlD
M014
M015
C2
A
MOl
M03
M06
M08
M010
MOll
M012
MOle
Cl
53
OBE
5280
1000
52
5280
1000
51
52
sa
A
51
54
55
56
5280
1000
Figure 28. Complete Correction Circuit
3-162
Enabling the correction logic, the decoded B(x) signals
become "high" to invert the output of the 74S86 exclusive-OR circuits. If the B(x) signals are "low" the output
of the correction is the same level as the input. The
correction circuit is shown in Figure 29.
Connecting the five circuits as shown in the block
diagram of Figure 20 completes the error correction
circuitry.
REFERENCES
t. "2107A12107B N-Channel Silicon Gate MOS 4K
RAMs," Reliability Report RR-7, Intel Corporation,
September, 1975.
N-Channel Silicon Gate 1K MOS
RAMs," Reliability Report RR-14, Intel Corporation,
1976.
2. "211512125
3. "2l04A N-Channel Silicon Gate 4K Dynamic RAM,"
Reliability Report RR-15, Intel Corporation, September, 1977.
SUMMARY
An unprotected memory has a system MTBF which is
approximately equal to the device MTBF divided by the
number of devices. Redundancy codes are used to protect
memories. While parity is a redundancy code, it only
indicates that an error has occurred. A "modified"
Hamming code can correct single bit errors and detect
double bit errors, truly enhancing the system MTBF.
This report has laid the foundation of ECC basic
concepts. Building on this foundation, the next report
will address the mathematics for calculating the
enhancement factor of ECC in a system environment.
4. "2116 N-Channel Silicon Gate 161\ Dynamic RAM,"
Reliability Report RR-16, Intel Corporation, August,
1977.
5. R. W. Hamming, "Error Detectihg and Error Correcting Codes," Bell System Technical Journal, Vol. 26
(April 1950), pp. 147 -160.
6. Len Levine and Ware Meyers, "Semiconductor
Memory Reliability with Error Detecting and Correcting Codes," Computer, October, 1976, pp. 43-50.
7. -, "Modern Algebra for Coding,"
Technology, April, 1965, pp. 59-66.
Electro-
8. William W. Peterson and E. J. Weldon Jr., Error
Correcting Codes, MIT Press, Cambridge, Mass.,
1972.
3-163
APPLICATION
NOTE
AP-73
AUGUST. 1980
©
Intel Corporation. 1980
01305A
3-164
AP-73
1.
page and p pages per system. Note that a "page"
is defined as the number of memory words formed
by a minimum set of memory components.
INTRODUCTION
This Application Note explains reliability analysis as applied to a typical memory system. (It follows Intel Application Note AP-46, which reviewed
basic ECC, Error Corrections Code, concepts.)
A number of examples demonstrate techniques to
calculate reliability of a model memory system,
with and 'without ECC - 'emphasizing system
reliability as a function of the number of devices
in a system and the individual device failure
rates.
For example, 16K by 1 RAMs would have a
minimum page size of 16384 words.
Figure 1 represents such a system, with the
horizontal axis corresponding to parallel, addressaccessed data bits and the vertical axis corresponding to the series stacking of words and
pages. This memory structure is used for the
model system.
Since a system with ECC can correct a single bit
failure and detect double bit errors within an accessed word, it has a decided advantage over a
system without ECC. A soft error rate of two or
three times device hard failure rate has significantly less effect on the Mean Time Between
Failures (MTBF) for a system with error correc~ tion. This is quantified as the Enhancement
Factor, EF - the ratio of MTBF for two identical
systems, one with and one without ECC. The
Enhancement Factor can be predicted by the
application of statistical analysis.
3.
3.1 Hard Failures
Hard failures are permanent physical defects,
such as shorts, open leads, micro-cracks, or other
intrinsic flaws. They are classified as single cell
failures, row failures, column failures, combined
row-column failures, half-chip failures and fullchip failures.
The general model presented in this Application
Note numerically predicts the chance of memory
system failures during a specified length of time.
It also provides insights into the relationship of
device failure mechanisms and soft errors to
memory system reliability. Intel® 2117 Dynamic
RAM is used in the example memory system. The
reliability data for distribution of hard fallures
was obtained from the 2117 Reliability Report
(Intel RR-20).
The failure type distribution within a device is a
function of the device design. Typical ratios are
50% single cell failures, 40% row or column
failures, 10% combined failures and less than 0.1 %
half-chip or full-chip failures. (Refer to Figure 4.)
The accumulative independent events are expressed
as a single numeric value for the combined failure
rate of the device (EQ:la). The standard mathematical symbol for device failure rate is the Greek
letter Lambda, A; i.e., A = 0.027%/1000 hrs.
2. MEMORY CONFIGURATION
2.1 Device
System reliability begins with the smallest physical unit, the memory device. Each device can be
considered a system itself, with the smallest functional unit being a single storage cell. Device internal structures have inherent failure mechanisms
affecting individual memory cells.
'The structure of a typical RAM device consists of
two-dimensional coordinate-addressed arrays of
memory cells arranged in rows and columns, such
as the Intel® 2117 Dynamic RAM shown in Figure
2. This device contains 16384 cells arranged in a
128 row by 128 column matrix; each cell is selected
by an encoded 7-bit row and 7-bit column address.
2.2 System
An array of memory devices on one or more circuit boards forms a typical memory 'system. A
system is defined by n bits per -word, x words per
ERROR CLASSIFICATION
The 2117 failure mechanisms illustrated in Figure
3 are fairly representative for today's RAM devices.
These can be categorized as hard failures and
soft errors.
EQ:la Ahrd= Asmgl e+ Arow+ Acolumn+ Arow/col+
Ahalfchlp +Afullchlp
3.2 Soft Errors
In contrast to hard failures, soft errors are characterized as being random in nature, non-recurring,
non-destructive single cell errors.
Traditional soft errors are caused by noisy system
environments, poor system design, or rare combinations of noise, data patterns, and temperature
effects which push the RAM beyond its normal
specified range of operation. This type of soft
error has not been included in the analysis to
follow because it is associated with system level
problems and the rate of failure is difficult to
quantify; in any case it is assumed to be quite
small.
3-165
AP-73
PARALLEL
~ BI~~~~AL---.
n-blts
~
11
C
m
<
n
m
#3 #2 #1
#n
t
SERIES
AXIS
x·words
Z·BOARDS
PER SYSTEM
V-PAGES
PER BOAR D
'-
++++++++
: W?RD:
Figure 1. Memory Configuration
3-166
AP-73
4.
RELIABILITY
Reliability, as used in this application note, is
defined as "the probability that a component will
operate within specified limits, for a given period
of time"l. The definition includes the term "probability", a quantitative measure for chance or
likelihood of occurrence, of a particular form of
event - in this case, operation without failure
within specified limits. In addition to the probabilistic aspect, the reliability definition also involves
length of operational time.
Since reliability is concerned with events which
occur in the time domain, they are classified as
incidental failures, which do not cluster around
any mean life period, but occur at random time
intervals. The exact time of failure cannot be predicted; however, the probability of occurrence or
non-occurrence of a statistical mean in a given
operating frame of time can be analyzed by the
theories of probability. Since exact formulae exist
for predicting the frequency of occurrence of events
following various statistical distributiOIls, the
chance or probability of specified events can be
'
derived..
4.1 Component Reliability
Memory systems are operated where failures
occur randomly due only to chance causes. The
fundamental principles of reliability engineering
predict the failure rate of a group of devices which
will follow the so-called bathtub curve in Figure 6.
The curve is divided into three regions: Infant
Mortality, Random Failures, and Wearout Failures.
All classes of failure mechanisms can be assigned
to these regions.
Figure 2. Random Access Memory Device
Other soft errors are caused by ionizing radiation
of alpha particles changing memory cell charge
in semiconductor substrates with high impedance
nodes. The data bit error is realized during a
memory read to the failing cell. These errors are
purged by rewriting (restoring) the correct data
bit information to the cell. The failure rate for this
type of soft error is stated separately from hard
failures because of its unique properties.
The total device failure rate becomes:
EQ:lb Ad"
= Ahrd + A'ft
The pie graph in Figure 5 depicts the combined
distribution of both hard and soft errors.
Infant Mortality, as the name implies, represents
the early life failures of a device. These failures
are usually associated with one or more manufacturing defects. Memory device failures occurring
as the result of Infant Mortality have been eliminated by corrective actions relating design,
inspection, and test methods.
Wearout failures occur at the end of the device's
useful life and are characterized by a rising
failure rate with time as the device's "wearout"
both physically an«:l electrically. This does not
occur for hundreds of years for integrated circuits.
The Random Failure portion of the curve represents the useful period of device life. As stated,
,memory devices are operated in systems during
this period when failures occur randomly. The
number of failures occurring during any time
interval within the "Random" period is related
only to the total number of memory components
1 Reliability Mathematics - Amst.adter
3-167
AP-73
SINGLE CELL
(1 CELL)
ROW-COLUMN
(258 CELLS)
COLUMN'
ROW
(128 CELLS)
('28 CELLS)
FULL· DEVICE
HALF-DEVICE
(8192 CELLS)
Figure 3. Failure Geometry -
3·168
(18.384 CELLS)
2117 Example
AP-73
COMBINED HARD FAILURE RATE
=0.027%/1000 hr.
50%
SINGLE CELL
1 CELL
ROW-COLUMN
256 CELLS
Figure 4. Failure Distribution - 2117 Example
SOFT ERROR SINGLE CELL RATE HARD ERROR COMBINED RATE TOTAL
operating. If sufficient numbers are operated, and
the measured interval is long enough, failure rate
approaches some relative constant value. For any
given component type, the failure rate value will
depend on operating and external environmental
conditions (voltage, temperature, timing, etc.) and
will be characteristic of this set of conditions.
When the conditions change, the failure rate will
correspondingly change.
For example, if 500 devices are t~sted for 1,500
hours and two failures were observed during the
test interval, then the failure rate is two failures
per 750,000 device-hours or one failure per 375,000
device-hours. For commonality, device failure rates
are' expressed as a percentage value per 1000 devicehours. The above example then becomes .00266
failures per 1000 device-hours or Adev = 0.27% per
1000 hours. This is an overly simplified statement
on determining the device failure rate. Many tests,
designed to stress the devices over operating con·
ditions and margins, are used in the final analysis
for the specification of device failure rates.
0.1% PER 1000 hrs
0.027% PER 1000 hrs
= 0.127%
PER 1000 hrs
HARD ERRORS
50.00;. SINGLE CELL
4.1.1 RELIABILITY FUNCTION R(t)
The Reliability Function, R(t), follows an inverse,
natural logarithmic curve, which expresses the
rate of change for a memory component from an
operational state to a failure or error condition.
The curve is a familiar one to the physical scien·
tists because of its relationship to growth and
decay.
15.6% ROW
28,1% COLUMN
6.2% ROW/COLUMN
21.2%
COMBINED
HARD ERRORS
The general function for reliability is given in
EQ:2 where the exponent (A . t) represents the
device failure "lambda" times the independent
time variable "t". The graph in Figure 7 shows
the shape of the Rfunction curve.
78.7%
SOFT ERROR
SINGLE CELL
EQ:2
R(t) = e- At
Figure 5. Combined Distribution of Failure Type
1,0
RELIABILITY LIFE (BATHTUB) CURVE
:ljR 0,5
w
""
"...
U)
0
0.0
RANDOM
0
time
Log Scale
timet
Figure 6. Reliability Life Curve
Figure 7. R(t) - Reliability Function
3·169
AP-73
For any constant failure rate the value ofreliability depends only on time_ The limits ofthe reliability function R(t) a~e:
R(O) = 1.0 and R(oo) = 0.0
The distribution is a one-parameter type; in that
once the failure rate is established, the reliability
function is completely defined. For high or low
failure rates the general shape of the, curve
remains the same, but is adjusted along the time
axis.
4.2 System Reliability
Just as there is a functional relationship between
the components and the system, there is a functional relationship between component reliability
and system reliability. If a failure in anyone of
the components of a system causes the entire
system to fail, the system is a "Series System"
(Figure 8).
Figure 8. System of Series Components
If all the component devices must fail before the
system fails, the system is a "Parallel System"
(Figure 9).
4.2.1 EQUATION FOR A SERIES SYSTEM
The Reliability ,Function for a series system is the
product of the reliabilities of the individual
components. If "n" components with corresponding failure rate of AI, A2, A3, , , , A'1 operate in
series to form a system then the equation for system reliability is:
EQ:3
R(t)sys = R(t)!, R(th' R(t))-, , ,R(t)ry
where R(t), = e-'>',·t
If each of the n components has the same device
failure rate lambda, then the system reliability
equation reduces to:
EQ:4
R(t)sys = R(t)~
= e -~'>'t
4.2.2 EQUATION FOR A PARALLEL
BINOMIAL SYSTEM
One of the fundamental concepts of reliability
engineering is the Binomial Theorem. The theorem
is used for computing the reliability of complex
redundant systems, where "j" out of "n" units are
required to operate for system success. The binomial distribution expresses the probabilities of
two states of an event, "a" and "b", where the
event is permutated "n" ways. The general form
of the binomial distribution is (a + b)'1, and is
expanded to:
EQ:5
a ~ + l1a~-l'b + 11(1/1)a'1-2'b 2 +
2!
11(1/1)( 1/2)a'1-3'b 3 + ... +b'1
3!
It is applicable to a memory system operating in
parallel; i.e., when there are only two possible
states or results of an event - when a component
of the system either conforms to requirements or
is discrepant.
Figure 9. Parallel System
a system has on' components which operate in
.parallel, but OJ' out of the on' components need to
be functional for the system to operate, then this
system is referred to as a 'I Parallel Binomial
System" (Figure 10).
~ If
}
Figure 10_ Parallel Binomial System
If we assign to one state the function of reliability
- R(t), then the other state is Q(t), the function of
non-reliability, which is the probability of being
inoperative.
'
Recall that R(t) is a unity function, which ranges
from 1.0 to 0.0, as a function of time. Since the
sum of R(t) and Q(t) make up the whole."event",
then EQ:6 defines Q(t). This relationship is also
illustrated in Figure 11.
EQ:6
3-170
R(t)
+ Q(t) =
1 , then Q(t)
= 1-
R(t)
AP-73
By substituting R(t) and Q(t) respectively for a
and b, where R(t) is the probability of a device
being good, Q(t) is the probability of the same
device being defective, and "n" the number of
units in parallel, then:
0,0
10
If there are three components X, Y, and Z, of
which two are operative and one fails, then three
possible combinations exist: X and Yare operational and Z fails, X and Z operational and Y fails,
and Y and Z operational and X fails. The probability of each combination is (RxRyQz) + (RxQyRz)
+ (QxRyRz).
OiT)
PROBABILITY
OF FAILURE
o
R
05
Again, since each combination is mutually exclusive and together they constitute all possible combinations, the probability of two operational devices
and one failure is 3R 2'Q. Similarly, if there are n
component-devices, the probability of all but one
being operative is nR"l . Q. Thus, the second
term of the binomial expansion series is the pro bability of exactly one device failure, and all other
devices being good.
By extending these derivations to cover each succeeding term, we find that the third term is the
probability of exactly two failed components, the
fourth term is the probability of exactly three
failures and so on. There are n + 1 terms in the
expansion, and the last term Q is the probability
all components are inoperative.
0.5
PROBABILITY
OF SUCCESS
AREA = MTBF
00~-----------------L------~~--'0
o
time
T
Figure 11. Ott) = 1 - e -~I
EQ:7
[R
+Q
]11 = 1
Note, for simplicity, all references to (t) for the
reliability and non-reliability functions will not
be indicated, but implied.
It follows that the expansionof[R + Q]lI must also
equal unity example
EQ:8
RlI
+ 7)R1J- 1'Q + 7)(rr l )R1J- 2'Q2 +
2!
7)(rr l )(rr2)R1J- 3'Q3 + ... + Q1J = I
3!
We can next examine the meaning of each term in
the series on the left side of EQ:8. Suppose that
there are "n" identical components of a system, of
which the probability of a component being
operative is R, and that .the probability of its
being inoperative is Q or (1 - R). If there.is only
one component (n = 1), then the probability of its
being not defective is si,mply R.
, The reliability of a group of redundant items
depends not only on the reliability of each individual item and on the number of items in redundant configuration, but also on how many are
required to operate to achieve system success. If
all are required, then the first term of the binomial
series represents system success. In this case
there is really no redundancy. However, if all but
one are required (one failure permitted), then
success is achieved if no failures occur or exactly
one failure occurs within word accessed from a
page of memory. The system reliability is then the
sum of the first two terms of the series.
If two failures are permitted, then the sum of the
first three terms represents the probability of
system success. In general, if r failures are permitted, system success is the sum of the first r + 1
terms.
If there are two components (n = 2), then the
probability of both being operative is R X R = R2;
and if there were three components, then the
probability of all three being good is R3. Consequently, if there are "n" components, the chance
of all "n" units being operative is RlI and the first
term in the series R1J is the probability of all
components being operational.
The general equation then for a binomial system,
permitting one error, which is representative of a
memory system with single bit error correction ECC per accessed word is expressed as:
EQ:9 RT(t) = R1J+ 7)'R1J- 1'Q
Next, suppose there are two components X and Y,
one is operative and one has failed. There are two
ways that this can occur: X is operational and Y
fails, with the probability Rx . Qy; or X fails and Y
is operational, with the probability Qx . Ry. Since
these are mutually exclusive and constitute all
possible combinations of one operative component
and one failure, the total probability is (RxQy) +
(QxRy), or 2RQ.
I st
2nd - binomial terms
Note that the remaining terms of the binomial
expansion represent all combinations of failures
that are greater than one failure, up to and including all components failing. RT(t) is still a unity
function of reliability and has a converse QT(t),
where QT(t) = 1 - RT(t). Thus, QT represents the
3rd through n-th terms of the binomial.
3-171
AP-73
5.
RELIABILITY ANALYSIS USING
PAGE/SYSTEM APPROACH
The analysis of the model system in Figure 1
begins with EQ:2 at the smallest non-redundant
failure level; by using standard rules for series
and parallel reliability, the combination of these
device exponential expressions will yield the system reliability equ\ltion. The method of approach
will be to calculate the reliability of a page of
memory and treat subsequent pages as a series
, system where:
'1
-A·n·t
EQ:ll R(t)PAGE necc = R(t)DEV necc = e
where "n" is the number of components in the
page and Adev is the device combined failure rate.
The reliability for the memory system of "p"
pages is:
EQ:12
EQ:I0 R(t)system= (R(t)pagel P
For clarity, the reliability of power supplies, fans,
backplane connections, TTL support logic, etc.
will not be included. These items can be merged in
the final analysis by the reader as additional
series system equations for each type.
5.1 Memory System Without ECC
The analysis of reliability' of a memory system
"without" any form of ECC is simply the first
term of the binomial equation EQ:9. Since this
term represents reliability of all components in a
page of memory without redundancy, it is equivalent to a "series system" equation (EQ:4). Therefore, the equation for a page of memory without
ECC is:
5.2 Memory System With ECC
The analysis of reliability of a memory system
"with ECC" - (single bit error correction) is more
complex. The fundamental difference between the
two memory systems is that in a non-corrected
system, any error - no matter the type, single cell
failure, row failure, soft error, etc. - is considered
a system failure. In a memory system with ECC, a
system level failure only occurs when more than
one bit has failed in an accessed word.
Thus in the analysis of a System with ECC, we
must deal with the probabilities of each failure
type occurring in random combinations which
align within a word of memory to cause multiple
bit failures as shown in Figure 12.
Memory Page Accessed Word Failure Alignment
Figure 12. Memory Page Accessed Word Failure Alignment
3-172
AP-13
devlcel
0
0
0
0
0
Msz
~l
word·
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
f'
#1
Ar =Adev
-Msz
Mlz • Memory P,age SIz.e
Isz • Failure SI,e
Rpa•• = [R"'r1
il
RELIABILITY
-5
-4
-3
-2
-1
1
RTf
=
4
3
(Rr 4Rf'Qfl
UNIT RELIABILITY
-0
#4
-'~~.Ms,
Rr = e-'f
if
=
Ms,
Is,
Figure 13. Single Failure Type Illustration
For example, consider a single cell hard failure in
one device in a system using 16K RAMs. The
chance of a similar failure in the same cell of a
different device is 1/16384 times the device failure
rate for single cells. For n devices in the data word
the total.chance is n/16384 for a single cell match.
The application of the binomial distribution
(EQ:9) requires further differentiation in the
analysis of the example memory system. EQ:9 is
restricted to one failure mode, in that it typically
assumes a failure renders the whole device inoperative. This is not the case with memory components where each device in itself can be thought
of as a system of memory cells, with the smallest
unit being the single cell.
Multiple devices have multiple failure modes, but
usually when a failure occurs only a portion of the
memory component is inoperative. Therefore, the
application of EQ:9 must represent the unit of
failure and be mutually inclusive with all other
components along the accessed word (parallel axis)
of the memory page.
failure mechanism of type f, which affects fsz
number cells during a failure. The unit failure rate
AI is the ratio of {fsz/Msz l times the device failure
rate Adev. Only that portion of the failure area, the
shaded area in Figure 13, is mutually-inclusive
with the failure when it occurs. Any additional
failures outside the shaded area are mutuallyexclusive, causing no double-bit failures in conjunction with "j:"
The Reliability Function, RT, therefore, represents
only a portion of the memory page as indicated by
the shaded area fsz in Figure 13. If "t' were the
only failure type, then the reliability for the full
page is simply a series equation with RT raised to
the exponent the ratio Msz/fsz.
i,
Derived from the binomial equation EQ:9, the
expression for reliability for a single page of mem·
ory with one bit redundancy - (ECC) -, and only
one failure type "x" is given as:
EQ:13
The example in Figure 13 shows a four device
memory array where each component has a single
3·173
AP-73
devices
0
0
0
0
0
Msz
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-Msz
RpAGE =[R'f,ll,
--- ---
0
-5
Ry,=
Rj,[Ry/\'[R.t; R/-"]'.a.r,
-4
-3
-2
!"
Ry, =Ri,+ RJ,"Or,
4
-1
-0
AI. = Ode.
1
J!!L
Msz
),/2::: Adev
:~!
.i 1 =
XI'
i
X/2
2
'S'2
Rf , =e-'f,
fsz 1
= Ms.
fsz 2
•
Ri, =e-'J,'
Figure 14. Multiple Failure Type Illustration
Now that the binomial equation technique has
been applied to a single failure type, let's expand
the process to cover more than one failure type.
By the process of combining or permutating these
failure types, the Reliability Function can be calculated. Figure 14 shows a four component
system with the probability that two failure types
.Ii or.li can occur in each component. Both failure
types affect fszl and fsz2 number of cells during a
failure, respectively. The calculation begins with
evaluating the probability of (I occuring (EQ:14a)
and merging by a second calculation the probability of failure type f2. (EQ:14b).
~
EQ:14a RT) = Rfl
~
f
EQ:14c
The total reliability for the page in Figure 13b is
given by equation 14d.
Msz
EQ:14d
R(t)page= [RT2J fsz 2
By expanding on this process the equation for a
system of memory components with these failure
types: fl, .li,.f3 is given in EQ:15.
~-I
+ 7)Rfl·Qfl
EQ:14b RT2= Rh[RT)2]
EQ:14c is the unit failure rate equation forfl and
fz in this case.
~-I
+ 7)[RhRfP] ·Qh
EQ:15
NOTE: with Adev representing more than one failure type,fl and.f2, Adev must be proportioned to the
"failure-type-distribution" in determining the
unit faiiure rates Afl and Ah. The term Xfl and
Xh are introduced to quantify the failure type distribution as a percentage. (Ref: EQ:1 and Figure 5).
3·174
We can now formulate a general set of equations
for multiple (fI) failure types in an error corrected
system.
AP-73
5.2.1 EQUATIONS FOR THE MODEL
5.2.2 THE ENHANCEMENT FACTOR
The full model under analysis in this report has
six failure types, as described in the section on
Error Classification. The reliability calculations
for a page of memory must permutate all combinations of these six failure types. It is accomplished
by the set of equations in EQ:16.
5.2.2.1 Mean Time Between Failures
The Mean Time Between FI!-ilures (MTBF) for a
IJlemory system, with or without ECC, is given in
EQ:17. MTBF is calculated by integrating the
system reliability function, R(t).ys, from t = 0 to
infinity.
EQ:16
:-,; £ 1 =
fsz.- ]
fSZ.-l
[ i_
,
fsz.
1 At. = Adev' X.' "MSz
R(t)PAGE ecc = { i _
,-~,
' .. =
" Q, = I - R,
Rs. = R"(Rs.- 1)"
I
RT, = R~'(RT'_I)b+ 1/(RS.)~-I'Q,
r
N
R(t)SYSTEM eee = [R(t)PAGE eee ]Pages
restrictions: RSo = RTo = fszo = 1.
The process begins at the word level with soft
errors and gradually increases the area of evaluation to single cell hard failures, then row or
column failures, combined row/column failures,
half· chip failures, and finally full-chip failures.
00
EQ:17
MTBFsys = !R(t)sys·dt
o
On the average a system will fail once every
MTBFsys hours. The relationship between MTBF
and the R function is shown in Figure 17.
The bottom line conclusions on the effect that errorcorrection has on a given memory system is calculated by comparing the resultant MTBF sy.-eee
projection with the MTBF .ys-necc of a similar system without ECC. The improvement of a memory
system with error correction logic over a comparable system without is expressed by EQ:18 as the
enhancement factor EF.
EF = MTBF aya-ecc
MTBFsys.necc
Illustrated in Figures 15 and 16 are the six iterative steps to merge all combinations of failure
types - fi, ,f2. fl, {4, /s, 16.
The first step calculates the chance of a single
word of the memory page not having more than
one soft error.
EQ:18
The second step calculates the probability of not
having more than one single-cell hard failure and
merges step #1, for a combined result that no more
than one failure caused by either soft error or
single-cell failure has occurred within the single
word analyzed.
The Mean Time To Failure (MTTF) ia similar in
concept to MTBF, but differs in that it represents
the effects of maintenance on an error corrected
memory system. When a maintenance policy is
adopted which allows for the rllplacement of
failed component;s before the system fails, system
failure is postponed (depending on how often the
system is inspected and maintained). With this
policy a memory system fails less frequently than
it does without maintep'ance; it is assured that
every new operating period after inspection starts
with full redundancy restored. The maintained
system Mean Time To Failure thus becomes
greater than MTBFsys:
,The third step calculates for row failures and
'merges with step #2 all combinations of the three
failure types. Using the 2117 example memory
system from Figure 6 to illustrate this point - a
row pr column failure affects 128 memory words
- the combined result from step #2, which analyzed a single word, is raiseq by the exponent 128
as a series equation. The combined result for step
: #3 is the probability of not having a system
failure due to any of the failure types ,fi, ji, /3, in
any given word for a 128-word block.
'
5.2.2.2 Mean Time To Failures
If preventive maintenance is performed at an
arbitrary time T, then EQ:19 expresses mean time
to failure.
I This process continues up to step six, which is the
calculation for all six failure types occuring in all
combinations that would cause a system failure
within the page of memory. The analysis of each
I step therefore raises the results of each previous
step by the exponent i ..
EQ:19
3:-175
T
[R(t)sys-ecc .dt,
MTTF
1 7 R(T) aya-ecc
BINOMIAL
--'-- AXIS
--+-
n-blts
exponent I, ratio
of area's sho.wn:
P
/sz.
I. " /SZs
User Definitions
2117 example
is"
I, " Soft Errors
I. " Single Cell Hard
13 " Row or Col Failures
I. " Combined Row/Col
Is = Half Chip Failures
I. " Total Chip Failures
Isz, " 1
Xi " .787
Isz. " 1
X. " .106
Isz, " 128
tsz. " 255
Iszs " 8192
Isz. " 16384
6,384
t. "
/ sz 5
/sz.
/sz.
/oz,
/sz,
i, " /oz.
i. "
X, " .082
X. " .013
Xs "-0.0
X. " 0.0
l, "
/sz.
/sz,
1
1. " 2
i5 = 32
£4
i3
= 2
=
128
12 = 1
I, = 1
,Moz
=
16384
--1--1--1--1--1---18192
i
RT. "combme[RT,l •
Adev
~
Ahrd + Aslt
++++++++
~qRD:
n
fsz l
Atl = Adev· XI. Msz
R, = e- A,"
, Q, "
Rs, = R,' (Rs,_,
RTI~
1 - R,
_1)1. +
R7.(RTI
}
}i,
">RT.
11(Rs.),,-1. Q1
~~
1st term
2nd term
Figure 15.
3-176
Rsys " [RT. ]"
AP-73
5.2.3 SOFT ERROR SCRUBBING
STEP.l
In the preVious sections on MTBF and MTTF, soft
errors and hard errors were treated the same.
They both accumulated to cause system failure or
were removed at scheduled preventive maintenance (PM) intervals.
STEP.2
STEP l - - - ' - - - ,
STEP.4-----'---,
STEP.. 5 - - - - - - ' - - - - - - , 111+12+13+141
STEP.6-------'---
+ 15 -
RT.S
111+12+13+14+151 + 16 - RT.6
Figure 16.
~
_ _ _ _. , MTBFsys
MTBF
HOURS
(THOUSANOS)
1.0 I-----.~
R
.5
Figure 17.
Figures 18 and 19 show the relationship ofMTTF
to the R functioll. and MTTF to MTBF respectively.
However, soft errors can have their own special
maintenance function. Recall that soft errors can
be purged from a system with ECC by rewriting
(restoring) the correct data bit information to the
failing memory cell. (Provided that no other bit
within the word containing the soft error has
failed.) Thus it is possible for the system to
maintain itself by software, etc. This special
maintenance function of scrubbing soft errors at
predetermined intervals is incorporated into the
system reliability equations by merely resetting
the time parameter t for the soft error portion of
the equations.
Figure 20 shows the relationship' of soft error
scrubbing on MTBF and the system R functions.
~_---~MTBFsys
The enhancement of a memory system with maintenance over a comparable system without ECC
is expresse.d in EQ:20.
=~Mo;:;T~T~F,.--__
EF
EQ:20
MTBF
MTBF sys-ecc
mnt
1.0
"', ,
TSFT
,
Figure 20.
\
R
\
0~
___
0.0
~
__
\
5.2.4 APPLYING THE MODEL EQUATIONS
MTBF' ...... _
__
~
~3L
_ _ _ _ _ ___
The basic set of equations for a model are derived
from EQ:16. The application of these equations is
best suited for implementation on a computer. An
example computer program is available on request.
1_00
(T)
TIME
Figure 18.
Figure 21 illustrates a simplified block diagram of
the model.
T
f R(t).y•• dt
o
OCT)
MTBF - mean lime to failures
R(I) - system rehabillty fUnction
EFeec - enhancement factor
Inputs
equations'
outputs
_______
;-0...._ _ _ __
Figure 21.
LOG/LOG
SCALE
In
The required user inputs are for component parameters - total memory size, number of rows and
columns, hard failure rate, soft error rate, and
P.M. TIME
Figure 19.
3-177
AP-73
failure mode distribution; for system parameters
- memory word size, ECC check bits, number of
pages, interval of time, and soft,error scrub time.
II. Table 3 shows the comparison of six memory
configurations, between two soft error rates.
. Output is a set of discrete values of the reliability
function representing the complete memory sys-,
tem as a function of time.
Table 3. Memory Configurations versus SE Rates·
HARD FAILURE RATE = 0.027% 11000 hrs
The integral functions for MTTF and MTBF are
evaluated by the trapezoidal rule of integration.
EQ:21
Configuration
16-bit word by 1 pg
16-bit word by 128 pg$
32-bit word by 1 pg
32-blt word by 128 pgs
64-bit word by 1 pg
64-bit word by 128 pgs
oc
MTBF=:I =~lk[Rsys
_1+Rsys l'.lTime
I
I
I
where R syso = I
Based on the Intel® 2117 Dynamic Ram, the following three sections - (I, II, III) - compare
various system configurations and failure rate
parameters.
Table 1 shows the comparison of six memory
configurations, ranging from 32~-bytes to 16
Megabytes. The Input parameters used were
those listed in Table 2.
I.
FAILURE RATE ~ ,127% 11000 hrs
configuration
.~,:r.E!F.', ,n.()n,:~,c.~ .~Jrr:~~! .Elc;c;.
16-bit word
16-bit word
32-bit word
32-bit word
64-bit word
64-bit word
by 1 pg
by 128 pgs
by 1 pg
by 128 pgs
by 1 pg
by 128 pgs
49 k hrs
390 hrs
24 k hrs
195 hrs
12 k hrs
98 hrs
1170
95
658
53
355
29
k
k
k
k
k
k
hrs
hrs
hrs
hrs
hrs
hrs
SOFT ERROR
RATE
·S.~Ll(JOg .~r.s
MTBF, acc
575k hrs
44 k hrs
322 k hrs
24 k hrs
173 k hrs
13 k hrs
III. Table 4 shows the comparison of a memory
device with one failure type. The failure types.
compared are devices with a single cell
failure tnodes and full-chip failure modes.
System A has devices with only "single cell"
failure types and System B has only "fullchip" type. All other parameters are identical.
Both system failure rates are 0.027%/1000
hrs.
, Table 1. Memory Configuration versus MTBF
,
SOFT ERROR
RATE
:,?roL~.(JQg..~!".!!.
MTBF, ecc
880 k hrs
70 k hrs
492 k hrs
39 k hrs
265 k hrs
21 k hrs
E.F
Table 4. Single Cell versus Full Chip Failures
24
249
' 27
278
29
299
configuration'
64-bit by 1 page
64-bit by 128 pages
SYSTEM A
With
...... ,!l,i.".!l!.EI,C;,~,IL"
MTBF
8.3 m hrs
730 k hrs
..
SYSTEM B
with
, ... !.lIll~.c~ip' .....
MTBF
103 k hrs
6k hrs
Table 2. Model Input Parameters
5.2.5 DISTRIBUTION
Combined HARD FAILURE RATE = 0,027% 11000 hours
Failure distributions:
single cell
row cells
column cells
row-column cells
half-chip
full-chip
Error correction in a system does not alter or
change the actual occurrence of failures. Failures
still occur at the MTBFnecc period based on the
distribution in Figure 5. (For the example system,
the soft error rate is three times the hard failure
rate - .1% vs .. 027% - which represents a soft
error occurring 78% of the time.)
= 50.0%
= 15.6%
= 28.1%
= 6.3%
= 0.0%
= 0.0%
total 100%
SOFT ERROR F,AILURE RATE = 0.1% 11000 hrs" est.
These results show an enhancement factor of
approximately 27 for a single page of memory
.and over 278 for 128 ,pages.
However, the fact that a multibit failure is required to cause a system failure in a system with
ECC' modifies the failure distribution; soft errors
have much less effect than hard failures on
system performance. Figure 22 demonstrates this
by showing a modified distribution based. on
average cells per failure, the Rate Geometry
Product, RGP.
3-178
AP-73
6.
INDIVIDUAL FAILURE RATE DISTRIBUTION OF A GIVEN TYPE
tiMES THE NUMBER OF CELLS AFFECTED
EQUALS AVERAGE CELLS PER FAILURE
FAILURE TYPE
SOFT ERROR:
SINGLE CELL
HARD ERRORS:
SINGLE CELL
ROW
COLUMN
ROW/COLUMN
% DISTRIBUTION
1
10.6%
1
128
128
256
6.0%
3.4%
1.3%
100%
AVERAGE CEllS
CELLS
78.7%
x
x
x
TO~AL
=
SUMMARY
This Application Note presents step-by:step
procedures for calculating system reliability. In a
system without ECC, a fault of any type can
cause system failure - predominantly types with
the highest failure rates. In a system with ECC,
only multi-bit errors within the same word cause
system failure - predominantly types with the
highest average cell errors as defined by the Rate
Geometry Product. An Enhancement Factor,
comparing a system without ECC to one with
ECC, can be used to determine if error correcting
techniques are advantageous for any specific
memory system.
0.79
0.11
7.93
4.35
3.32
16.5
6% SINGLE
CELLS
DISTRIBUTION BY NUMBER OF AVERAGE CELLS
References
1. Randall C. Cork, "Reliability with Error·Detecting and
Correcting Codes in Semiconductor Memories," Ph.D.
dissertation, Arizona State University, 1975.
Figure 22.
The illustration shows the statistical average cell
failure for each type derived by taking the prodllct
of the component failure rate distribution times
the number of cells affected. For the 2117 example
device, the total average cell failure is 16.2 of
which 11.8 are column and row failures.
Intuitively, it can be seen that row and column
failures are the most predominant, while the least
predominant are soft errors and single cell hard
errors.
3-179
2. Bertram L. Amstadter, Reliability Mathematics Fundamentals; Practices; Procedures, McGraw Hill, N.Y., 1971.
3. Byron L. Newton, Statistics for Business, Science Research
Associates, 1973.
4. Carl· Erik W. Sundberg, member IEEE, "Erasure and Error
Decoding for Semiconductor Memories", IEEE 1978.
5. Peter Elias, "Error Free Coding", MIT.
6. S.K. Wang & K. Lovelace, "Improvement of Memory Reliability by Single-Bit-Error Correction", Texas Instruments
Inc.
AP-73
APPENDIX A
3-180
AP-73
APPENDIX A
EQ:la
Ahrd= Asmgle+ Arow+ Acolumn+ Arow/col+ Ahalfch,p +Afullch,p
EQ:lb
Adev
EQ:2
R(t) = e- . . t
EQ:3
R(t)sys= R(t)rR(th·R(t)r ••• R(th
where R(t), = e- . . ,·t
EQ:4
R(t)sys = R(t)'1 = e -'1 . . t
EQ:5
a'1 + T/a'1-t' b + T/(7)""""I)a'1-2'b 2+ T/(7)""""I)(7)""""2)a1J-3·b 3+ ... +b'1
= Ahrd + Ash
2!
3!
EQ:6
R(t) + Q(t) = 1 • then Q(t) = 1 - R(t)
EQ:7
[R
EQ:8
R'1 + T/R'1-I'Q + T/(7)""""I)R1J-2. Q 2 + T/(7)""""I)(7)""""2)R'1-3. Q 3 + ... + Q'1 = 1
EQ:9
RT(t) = R'1 + T/'RI1- I'Q
1st
2nd - binomial terms
EQ:I0
R(t)system= [R(t)pageJ P
EQ:ll
R(t) PAGE necc -- R(t)'1DEV
- e- . . ·n . t
necc -
EQ:12
R(t)sys necc =[ R(t)PAGEneccl P= [R(t)DEV ('1
+ Q ]'1 = 1
2!
3!
EQ:14a
'1
'1-1
JLx
R(t)PAGEecc= [R(t)x + T/'R(t)x . Q(th
'1
1)-1
RTI = RJI + T/RJI'QJI
EQ:14b
RT2 = RJdRTI2] + T/[Rh'RJP] ·Qfz
EQ:13
I
1)
~I
AI _ A . XI . fszh
2dev
2 MSZ
EQ:l4c
EQ:14d
Msz
R(t)page= [RT2] fsz,
EQ:15
=~
"f
]
[ i - ' ! fsz,_1
fsz l
I Al, = Ade,· X,· MsZ
EQ:16
R(t) PAGE
ecc
={i _
NRI= e
-).t,·, Ql =
t
I _ RI
= R ·(Rs
t>"i1
'1-1
17 •
RTI - R (RTd) + 1) (Rs,) .Q,
.
Rs
I _
I
1
1-
I
R(t)SYSTEMecc = [R(t)PAGEecc]Pages
restrictions: RSo = RTo = fszo = 1.
3·181
}MSZ
fsz
N
AP-73
00
EQ:17
MTBFsys = JR(t)sys·dt
o
EQ:18
EF = MTBF sys·eee
MTBFsys-necc
T
EQ:19
MTTF
EQ:20
EF.
mn!
JR(t)sys-ecc .dt
-=-0-....,-..,_ _
1 . R(T) sys.ece
MTTF
MTBF sys-ecc
00
EQ:21
MTBF=
k'k[R sysI
-1+Rsys
J~Time
,
i =1
'
I
where Rsyso= 1
3·182
AP-73
APPENDIX B
3·183
AP-73
APPENDIX B
INPUTS
UNIT 'AlLURE RATes
Ahflt,
A."
FAILURE DISTRIBUTION
tc.%
TIME INTERVAL
(I)
UNIT MEMORY SIZE
UNIT ROW SIZE
SYSTEM WORD WIDTH
ECC CHECK BITS
'AGES
REL~.ILITY
OUTPUTS
MOOEL
•
•
•
EQUATIONS
•
•
•
•
•
3-184
f-
R(t)SYSTEM FUNCTION
-
MTTF(T) FUNCTION
L..-
MTBF
inter
Ap·73
FORTRAN IV
V02. 04
C###############################################I#I#I#1#
C
#
ECC RELIBILITY MODEL
REV 6B FEB79
#
C
#
#
C
#
INTEL CORP
#
C
MEMORY PRODUCTS DIVISION
#
C
#
APPLICATIONS LAB
#
C
#
ALOHA. OREGON #
C
#
#
C
*"
#
C
#
ERROR CORRECTI ON RELI AB I L ITY
C
#
APPLICATIONS NOTE
I
C
#######################################1###1##
*"
r'
0001
0002
0003
0004
0005
0006
0007
0008
0009
001.0
0011
0012
0013
0014
0015
001(:0017
0018
C
0019
C
0020
0021
0022
OO:.!:3
0024
0025
0026.
0027
0028
0029
0030
0031
003:2
0033
003'1
00:35
0036
0037
0038
IMPLICIT REAL*8 (D.R.S.T.Z)
DIMENSION KM(2).LH(2).KL(4).LQ(4)
BYTE LL(2).LR(2). IBUF(80). ILIST(80)
INTEGER*4 IIPTR.LPTR(13). InBORT, IHELP.LMFLGS(3). IIXFG
COMMON /ECC1/RXZ. RXS. RXR. RXC. RXF. RXE. RXH. RXT,RCNF,SZER. SXX
COMMON /ECC2fRMSZ. RCSZ, RWD, BPG, RZD, RZDD, REC. RZER. RL RTM. RTSF
COMMON /ECC3/IM. ILLM, IULM.RSQ,.JSFLG,EPGX. ISFLG,ST.R.RTH,R2
COMMON /ECC4/ISW,RFF. IPM,RTTF,RZTTL. ICST.RALMT. IDBK.~QFG. lueD
COMMON /ECC5/ISFG. RECL REe2. IEFLG. RZSYS. ILIM. IDFLG. RAVE
COMMON /ECC6/ IT 1 N. ITOUT. I LP
COMMON /ECC7/RZZ, RZS. RZR.RZC,RZF.RZE,RZH.RZT,RZDX
COMMON /ECC8/ECZ, ECS.ECR,ECC. ECF,ECE,ECH,ECT,ECX
COMMON /ECC9/EW,EW1,EW2,RW.RW1,RW2,S,T,TSFT,THRD
COMMON /ECCA/EPG,EBD,EPSZ, ECA. EPX.EPY,EPZ
COMMON IECCC/L IMN. RPRT. RTO, RTPG, RTX. RZDZ. RXX. RSPC!. RSPC2:
DATA KLl" '-, "'* ",., !V, "'*$' I. IABORTFABOR"I, IHELPFHELP'I
DATA KM/'KB', 'MB'/,LL/' " '<'/,LR/' " ')'1
DATA LMFLGS/'SYS', 'MPD', 'MSO'I
1
2:
3
'I
5
6
7
DATA LPTRf'LIST"', "SIZE", 'RATE', "'DIST', 'COMM'-, 'DUMP', 'FLAG',
* 'HXDR', 'CYCL', 'PURG', 'NECC', 'SECC', 'D!CC'I
8
9
10
l.1
12
13
DATA U~/'Q1", "02", 'OX', "OZ"I
DiHA LH/"- -"', "'M-' /, IBEL/1799.l
DATA ITINf5.l, ITOUT.l7/, ILIM.llO.l, IDFLG/l.l, ILP.l61
DATA RXZf. 7874DO.l,RXS/. 50DO.l,RXR.l. 156DO.l,RXC.l. 281DO/,RXE~ 062DO/
DATA RXH/~ ODO/.RXT/O ODO/.RCNF/. 37DO.l.SZER/. 1D-4/
DATA RRXS.l50. DO.l,RRXR/15. 6DO.l.RRXC.l28. 100/,RRXE/6. 200/
DATA RRXH/O. ODOfi. RR'XT /0. 000/. SXX/1. ODO/
DATA RMSz/16384. ODO/,RCSZ/128. ODO/, RWD/64. ODO.l.BPG/128. 01
DATA RZD/O. 0002700.l.RiSE.l0. 00lDO/.REC/-1. 000/. RZER/O. 0001
DATA RRZD.lO. 027DO.l,RRZSE/O. 100/,RRZTTL/0. OOO/.RRZSYS/O.ODO/
DATA RU1. ODO/.RTM/2500. 000/,RTSF.l1000. ODO.l.RAVEf228. ODOI
DATA IM/O/, ILLM/O.l. IULM/30/, RSQ/2. ODO.l, .JSFLG/1/. EPGX/I. 0/
DATA ISFLG.ll.l,ST.lO. ODO/,Rf100. ODO/,RTH/l00000. 000/,R2/2. ODO/
DATA ISW.ll/,RFF.l~ ODO/, IPM/l0/,RTTF/Q OOO/,RZTTX.lO. ODO/
DATA ICST.l2/,RALMT/0. 0IDO/. IDBK.li/, IQFG.ll.l, ruc%.l, ISFG/1/
DATA RECI/8. ODO/,REC2.li5. ODO/, IEFLG.lO/,RZSYX/O. ODO/
DATA ILFG/U,RTMSO/O.ODO/,RZTI:1P/O. ODO/,.JXFG/U
DATA RZS1/0. ODO/,RZS2/Q ODOf,RRZS1.l0. ODO/,RRZS2/0. ODOI
DATA TTMCYLl5. OD:2.1, TMCYL.l5. OD2/' TTRCYL/1. 5D4/, TRCYL/1. 5D41
3-185
inter
FORTRAN IV
Ap·73
V02.04
DATA TREF/7. D3/,RRX1A/66. DO/,RX1A/. 66DO/,RRX1B/33. DO/,RX1B/.33DO/
RPSZ=RZER
'
SLM=RZER
EPG=BPG
0039
'0040
0041
0042
C
C#################### RELIABILITV EQUATIONS ##########################
C
C
R[TJ = N*QT*[ RT* SINGLE CELL TO SOFT ERROR RATIO
~
- 1
COLUMN TO SINGLE CELL RATIO
:::: ROW/COLUMN TO COLUMN RATIO
= HALF CHIP TO ROW/COLUMN RATIO
= TOTAL CHIP TO HALF CHIP RATIO
C
0043
0044
WRITE (ITOUT, 10)
FORMAT (T2, '«« ERROR CORRECTION RELIABILITY »»~,/,
C T4, 'INTEL CORP. MPD/MCO
DJM FEB79',//,
C T4, '·FOR PROGRAM DESCRIPTION ENTER> HELP')
C######################################################################
10
C
C
INPllT PARAMETERS
C
C#######################################################################
C
0045
100
0046.
0047
90
0048 101
0049
0050
0051
0052
0053
0054
CONTINUE
WRITE (ITOUT,90) IBEL
FORMAT (A2, T5, "POI'NTER, INDEX, TIME"
PAGE, BOARD')
FORMAT <1"2, ~** LIST OUTPUT PARAMETERS **~, /,
C T2, '* LOWER, UPPER, SKIP, UNCOND, MAINT, . CONF~)
102
FORMAT (T2, ~** COMPONENT & MEMORY SYSTEM PARAMETERS **~,/,
C T2, '* RAMSIZE., COLSIZE, WORDSIZE, CHECKBITS')
103
FORMAT 0
0092
0094
OO·;>C.
009:3
0099
0100
0101
0102
115
117
READ (ITIN,95) IIPTR, III,RRTM, IRPG, IRBD
FORMAT (A4, lX, I6,Fl0. 2, 15,15)
IPTR=O
DO 94, .J=l, 1:3
IF (IIPTR. EQ. LPTR(J» IPTR=J
CONTINUE
IF ~IIPTR. EQ IABORT) STOP
IF (I I PTR. EG!. I HELP) CALL HELP
IF (IPTR. EQ. 0) GO TO 100
IF (IPTR. LT. 10) GO TO 96
RTM=RRTM
EPG=IRPG
EBD=IRBD
1=1 II
. . . .. DETERMINE WHAT TEST .....
IMM=IPTR-l0
CONTINUE
IDMf=l
IF (IPTR. EQ. b) IDMP=2
IF (IPTR. GE. 11) GO TO 200
GO TO (98, 115), IDMP
CONT I NUE
GO TO (UO, 120, 1:30, 140, 150, 160, 170, 180, 190, 1';>5), IPTR
WRITE (ITOUT, 1(1)
READ (!TIN, 112) ILLM, IULM, ISW, lUCD, J:::;, RCNF
FORMAT (5(I6).Fl0. 8)
. .. DISABLE FUDGE FACTOR ...
RFF=O. 0
IEFLG=O
IF «ILLM. LE. 0). OR. crULM. LE. 0). OR. (JS. LT. 0» IEFLG=l
IF «RCNF. LE. O. 0). OR. (RFF. LT. 0. 0»
IEFU3=2
IF «IUC~ LT. 0). OR. (JS. LT. 0» IEFLG=3
IF (IEFLG. EQ. 0) GO TO 100
WRITE ·(ITOUT. 1(7) IEFLG
WRITE (ITOUT, 117) LPTR(l). ILLM, IULM, ISW, IUCD.JS,RCNF,RFF
FORMAT 0:;::
REI>.' I I I
182
0';>0,1
l..tRITE (ITOI.IT, 182) ,.JXI-'G, REC, EPG, ESD
FORMA'f (T2, '* HEADER) FLG-' , I3.2X. 'CK-'.F4. 0.2X. 'PG-'.
CF4, u,3X. ·8D-',F4. 0)
ou ro '2:00
O?05
1)206
1.9()
020 7
0:;:>0::::
192
f):2'09
1)';:'1.0
O~~c 1. t
n?l:3
O::::t!5
O:~~ 17
O'?1';1
CONT.r NUE
~.JRt I'E (nOUT, 1(6')
READ (IT[N, 192) TTMCYL.TTRCYl.RRX1A.RRX1B
FORMAT (2(F12 OI.2(F8, ~)I
IEFU,-O
IF (e ITMCYL. LE. 0, 0), OR. (lTRCYL. L~ O. 0)1 IEFLG=1
IF (CHRX1A+RRX1B), GT 100. ) IEFLG=2
IF «RF':XH'I LT. O. ). OR. (RRX1.B. L.T. O. » IEFLG'=3
IF (IEFLG NE.O) GO TO ~93
TI"ICYL ~·'1 TMCYL
02·?O
TRCYL.~TTRCYL.
(l"?:2t
02'22
RX1(\=RRXlfVl00
R:f.1.B",·f:i:RX1B/100
02 4::::
(;(1
nJ
100
022 (J
1 ,:~ "::
0225
1':;"4
WRI·fE (IrOUT. 194) TTMCYL..TTRCYL,RRX1A,RRX1S
Ff)HM(~"
(T:2, '1* "';2~(r:12, o~ 1X).2X}2(F8. 4/1.X»
1 'il!5
CUNTINUF..
GO
O·::-~:?(:,
0'2:l7
C
ro
100
PURGEo
[If)
l',q. I NIT'::, 1 ,
~5
3·189
inter
FORTRAN IV
0229
0230
02:31
0232
0233
0234
196
197
198
AP-73
V02. 04
WRITE (ILP, 196) (ILIST(NN),NN=1,72)
FORMAT (T2,72A2)
CONTI NUE
WRITE (ILP, 198)
FORMAT (lHl)
GO TO 100
C
C#################################################~####################
C
C
INITIALIZE PARAMETERS
C
C##############################,":########################################
02:35
02:36
0238
02:39
0240
0241
0242
0243
024A
0246
0247
0248
0249
0251
025:3
0254
200
201
202
208
209
210
C
0255
0256
0257
0258
0259
0260
0261
0262
02e:.3
0264
0265
0266
0267
026',1
0270
0271
0272
027:3
0274
0275
0276
0277
CONTI NUE
IF (IEFLl3. Eel. 0) GO' TO 202
WRITE (ITIN,201) IEFLG
FORMAT (T2. >ERROR COND EX ISTS - ABORT "', 12)
GO TO 100
CONTINUE
SLM:=:·JS*RTM
RE=O. 00
IF CREC. L~ RZER) GO TO 208
RE=REC
GO TO 209
CONTINUE
IF (IMI'1. EGl. 2) RE=RECI
IF (IMM. EG!. 3) RE=REC2
RW"~RWD+RE
CONTINUE
. . . . . .. NAME CHANGES FOR SPEED REASON " S
EW=RW
RW 1 ""RW-1. 0
EW1=RWl
RW2=-RW-2. 0
EW2=RW2
. . .. SOFT ERROR ALGOR I THM BY CYCLE TIMES ....
SMCYL'-"'RMSZ
SMTIM~SMCYL*TMCYL
:::;.RCYL"'SMT I M/TRCYL
SRPG=(EPG*EBDI-l.
::;;ECYL': ( 8MT:t M+ ( :3MT I M*SRPG) ) / ( SMCYL + ( SRCYL *SRPG) )
SNRMLZ=TREF/SECYL
RZDD=(RX1A*RZSE*SNRMLZ)+(RX1B*RZSE)
IF (JXFG. NE. 2) RZOD=RZSE
RZOX'"RID+RZOD
RXZ"~RZDO/RZDX
RXF=RXR+RXC
RRSZ"'RM::;;Z/RC:::;Z
RF8Z=(RC81+RR8Z1/2.0
RESZ=RM8Z/(RCSZ+RR8Z)
RHSZ"'2. (>
RT8Z=1. I)
o27.E:
ECZ=1. I)
ECS=1. 0
027',1
ECR"RR::::Z
3·190
AP·13
-FORTRAN IV
0290
0291
0292
0293
0294
0295
0296
0297
0299
0299
0290
0291
0292
0293
0294
0295
0296
0297
0299
0300
0301
0302
0303
0304
0305
0306
0307
0309
0309
0310
0311
0312
0313
0314
0315
0316
0317
0318
0319
0320
0321
0322
0323
0324
0315
0326
0327
0328
0329
0330
0331
0332
033~
0334
V02.04
ECC=RCSZ
ECF=RFSZ
ECE=(RRSZ+RCSZ)/RRSZ
ECH=RMSZ/«RRSZ+RCSZ)*2.0)
ECT=2. 0
T=RZER
S=RZER
RINC=RTM/RTSF
RMTBF=RZER
RMTTF=RZER
RMNT=RZER
LG==1
IMFLG=l
I SFLG= 1
.JSFLG=1
IXFLG=1
ILFLG=1
RM t L= 1 000000.
IF (RTM. GE. 100000.0) IMFLG=2
RZZ=(~XZ*RZDX)/RMSZ
RZS=(RXS*RZD)/RMSZ
RZR=(RXR*RZD)/RRSZ
RZC=(RXC*RZD)/RCSZ
RZF=(RXF*RZD)/RFSZ
RZE=(~XE*RZD)/RESZ
RZH=(RXH*RZD)/RHSZ
RZT=(RXT*RZD)
RHRD=l. O-RXt
RTMP=(RXS/RMSZ)+('RXF/RFSZ)+(RXE/RESZ)+(RXH/RHSZ)+(RXTIRTSZ)
RAVE=RXZ+«RTMP*RMSZ)*RHRD)+RFF
AZ=RXZ
AS=RHRD*RXS
AF=RHRD*RXF*(RMSZ/RFS2)
AE=RHRD*RXE*(RMSZ/RESZ)
AH=RHRD*RXH*(RMSZ/RHSZ)
AT=RHRD*RXT*(RMSZ/RTSZ)
AXX=AS+AF+AE+AH+AT
BZ=(AZ/(AZ+AXX»*R
BHRD=100. OO-BZ
BS=(AS/AXX)*R
BF=(AF/AXX)*R
BE=(AE/AXX)*R
BH=(AH/AXX)*R
BT=(AT/AXX)*R
RZDZ=RZDX*(RAVE/RMSZ)
ECA=RMSZ/RAVE
RZREV=O. 0
RZTOL=O. 0
RTPM=RTM/IPM
MLD=1. 0
ISFLG=l
RTSED=RTTF
RSPC1=1. 0
RSPC2=2. 0
3-191
intJ
FORTRAN IV
0335
03:36
0337
0:~::38
0340
0341
0342
034:3
0344
0346
0347
0:348
0349
0350
0351.
0:352
0354
0355
0357
211
212
0358
0359
0360
0361
r'
0362
036:3
0364
0:366
21:3
c
0367
0:368
0370
0:372
0373
0374
0375
214
0:~:77
217
216
0378
0380
0:381
0382
0::::84
0::::85
0386
0387
0389
218
219
Ap·73
V02. 04
EPX=(CRMSZ-RPSZI/RMSZI*EPG
EPY=(RPSZ/RMSZI*EPG
EPZ=O. 0
IF (RPSZ. L~ RMSZ) GO TO 211
EP=(RPSZ-RMSZI/RMSZ
EPZ=EP*EPG
EPY~(l. O-EP)*EPG
EPX'=O. 0 .
IF (RPSZ~LE. 2. O*RMSZI GO TO 211
EPX:-::O. 0
EPY=O. 0
EPZ:=O.O
CONTINUE
EP:::;Z=RPSZ
RZTMP"'O. 0
IF (CRTTF. NE. RZER). OR. (IMM. EQ. 1» GO TO 212
RZTMP=RWD*EPG*EBD*«RZD*SXX)+RZDD)
IF (RZTMP. GT. O. 0) RTSED=1.000. O/RZTMP
CONTINUE
RZTTL=O. 0
RZSYS=O. 0
RTM:::;O=O. 0
GO TO (213.214.214).JXFG
NORMAL TTL SYSTEM CALCULATION ..... .
RZTTL=RZTTX
RZSYS-=RZSYX
IF (RZSYS. GT. 0.0) RTMSO=lOOO.O/RZSYS
GO TO 216
MSO MODE RTMSO CALCULATION FOR HEADER ONLY .....
RZTMP=(EBD*RZTTX)+RZSYX
IF (RZTMP. GT. O. 0) RTMSO=1000.0/RZTMP
IF (JXFG. LT. 3) GO TO 216
RZSY:::;=RZTMP
CONTINUE
IMN=l.
IF (RPSZ. GT. RZER) IMN=2
CONTINUE::
IF «III. EQ. 0). OR. (IMM. EQ. 0» GO TO 220
T=III*RINC
S::::T
IF (JS. EQ. 0) GO TO 395
GO TO (218.219). ISFG
S=.JS*RINC
GO TO :395
IF (RTSF. GT. O. 0) S=SLM/RTSF
GO TO :395
C
C######################################################################
r'
0390
0391
C
PRINT HEADER
C
C##############################################'*#######################*
220 WRITE (ILP. 221) (IBUF( IB). IB=1. 72)
221
FORMAT
(T2.72Al./IT2,8(~---------~»
3-192
inter
Ap·73
FORTRAN IV
0392
0393
0394
0395
0397
0398
0399
0400
(1401
0402
04·(13
04(14
0405
040~.
0407
0408
0409
041.0
041.1
041'~~
Ott 1:3
0415
0416
0417
041.8
'.102. 04
QC=RWD*EPG*EBD
RSS=(QC*RMSZJ/8192.
IFLG::-::l
IF (RSS. L.T. 1000.0) GO TO 16
RSS-::RSS/l000. 0
CONTINUE
I ',FlO. 6. 'x / 1000 HRS'./,T2, 'SOFT ERRORS: ',T16,
r:: . H*H··.·120,'·MAJNT -) ',FlO. O,··HRS. ",T45,'RATE -) ',FlO. 6,
r:: '% I 1000 HRS', I,T2. 'ANALYSIS DATA:'. T20, 'PERIOD -)' ~,Fl~ 2,
C . HRS, ". T45, " AVE CELL F?ULURE -Y, F8. 1)
1<.,-100
WRITE:: (ILP, 11)
FORMAl (T2, 'FAILURE TYPE RATIOS:
"5('----------'),/, T2.
It
C ':~TYPE""·' .114, " ~-D1STRIBUT ION-=GEOMETRY=-UNIT. RATE/IK HRS=',
C 'AVE. CELL8~Eec DISTR=EXPS-')
WRITE eILP, 12) RXZ*R,RMSZ.RZZ*R.AZ,BZ.RHRD*R.BHRD.RXS*R,
C RMSZ, RlS*R. AS, BS. Er::S. RXF*R. RFSZ. RZF*R,AF. BF, ECF
FORMAT (1':':;:, 'SOFT ERROR -)[", F7, :3, ',;]/", F7. 0,' = '. E12. 5, 'X, "
L~
C FI1, 3.2X. '[',F6. 2. 'Xl'.I,T3. 'HARD ERRORS -)[',F7. 3, ~X]',
C T65. "'[". F6. 2. ,",;]",,1,
e T3 •. SINGLE CELL -)'.F8. 4.'X 1'.F7. 0,' = ',EIL5, 'X, 'Fl1. 3,2X,
C F~ 2, 'X'.2LF4. 0,/,T3, 'ROW OR COL -)',Fa 4,'X 1',F7. 0,' = "
CELl. 5. ·'X, ··,Fl1. ::::,2X,F6. 2, ",;", 2X, F4. 0)
WRITE (ILP, 17) RXE*R,RESZ, RZE*R, AE, BE. ECE,RXH*R, RHSZ,RZH*R,
C AH,BH,ECH,RXT*R,RTSZ,RZT*R,AT,BT.ECT
17
FORMAT q:3, "COLUMN/ROW -:", F8. 4, ",; /"', F7. 0,' := "
C E12. 5, 'x. ·,Fl1. 3,2X,F6. 2, ·X',2X,F4. 0,/,T3, ;HALF CHIP
-)',
C F8.4.·:'I. .I'.F7 (I," '" .... EI2.5, ':'I.,'·FII :3,2X,F6 2,'i';"',2X,F4.0,/.
C T3. "'TOTAL CHIP ->',FB. 4, 'X 1',F7. 0,'" = "',E12. 5, ':'1.,"',
C F 1. J 3, 2X, F6. 2, ":'1.", 'lX, F4. 0, /)
IF (IMM. NE. 0) 1.30 TO :30::/1)
WRI TE (ILP, :::::30)
380 FORMnr (IHl,T2,8C'--------'»
GO TO 100
390 CONTINUE
1(-,
C$$.$$.$$$$$$$$$$$$$$'$$"'$'$$$."$'$"'$'$'$'$$$$'$$$$$$$'$$$$$$$$$$$
3·193
AP·73
VO:l. 04
EC~UfH
C
ION LOOP
(:
.-.
WRITE CILP. 14) LPTRCIMM+l01.LHCIMFLG)
FORiv1(.YI (1"2.' PERIOD'. Tll. "PMCH: ",1'24. '··RCT]. ". A4i T44 .... MTTF'.
C T52. 'ENHANCEMENT'.l6S.·X - RCT)'.I.T2. '-----'.T8.
C "'C', Ai. •.' HR::::>·. 1'2:3. '·"'FUNCTION:'. T42 •.,.-( HRS ~...... T52.
(: .... FACrOR . ".1'65, . '
Ci.'1'. ,)
0 /119
0420
111
0421
04.22
:39~5
rSF"f"="S
400
THRD"'T
CONTINUE
1"'0
0'17.:3
04'24
04:?!,)
,-'13=1
RENH:::RlER
04 ~:'(:,
r'
1=:t.I:####### tf###################:It##########:W##################### #########
!'":
(".
RELIABILITY
EQl~TIONS
r'
C
CAL.L TEST (JMM)
C
ctt#################################################### #################tI
C.
OUTPUl DATA
r
C
(;##, •• #######ft ••• #.#### ••• ####ft####################### #################tI
0428
0429
04:31
'500
502
0433
04:34
04:35
0436
0437
510
0439
0441
0442.
0444
0445
0447
0448
0449
0450
0451
0452
0454
0455
0456
0458
0460
0462
517
520
522
l"::Ol'fT [NUt::
IF (III. EQ 0) GO TO 510
wRI TE: (I TOUT. 5(2) LPTRC IMM+l0). I. T*RTSF. RTPG
FORMAT (T2. '** '.A4.5t .... I => .... I4.5X.'T => '.FIO. 2. lOX.
C 'R -> .... FIO. 7)
13(1 TO 100
IZFLG:-:(l
f:TIM==T*RTSF
RTMX:::-:RTIM
IF (IMFLG. EQ. 2) RTMX=RTIM/RMIL
IF (I. EQ 0) GO ro 522
RINT"""'(CROLD+RTPG)/2.0>*RTM
IF CISFLG. EQ. 2) RINT~RZER
RMTTF=RMTTF+RINT
IF (1. O-RTPG. LE. SZER) GO TO 517
RMNT"RMTTF/(1.0-RTPG)
GO TO 520
IZFLCi:::::2
ROLD"'RTPG
CONTINUE
IF (C RTPG. LE. RCNF). AND. (LG. EQ. 1») ,-'13=2
~:.LI ::-:KL< I XFCi)
IFU3=O
IF « (I.fISW)*ISW. NE. I). OR. (1. LT. ILLM» IFLCi=l
IF (I. GT. I0LM) IFLCi=l
IF (I. Ea. IUCD) I FLG=O
RI=1
3-194
inter
AP-73
FORTRAN IV
0463
0464
04&,6
0467
0468
0469
0471
0473
0474
0475
047':.
0477
0478
047',1
0480
0482
V02. 04
e l F (1. EGl. 0) GO TO 525
C
IF (RTPG. LE. O. 0) GO TO 525
C
RZREV=(DLOG(l.O/RTPG»/T
RZTOL=«RZTOL*(RI-l.O»+RZREVI/RI
C
525 CONTINUE
IF « 1. NE. 0), AND. (IFLG. EQ. 1» GO TO 550
Ll=LL( .JG)
L2=LR ( ....113 )
RCFD=RTPG*lOQ 00
IF (RT::';ED. GE. 1. 0) RENH=RMNT lRTSED
IF « I :::;FLG+ ...J:::;FLG. EGl. :;::). AND. (I LFG. EG!. 1» GO TO 535
GO TO (5:31, 5:32), I MFLG
531 WRITE (ILP.505) I.RTMX,KLI.RTPG.RMNT.RENH.Ll.RCFO.L2
505 FORMAT (T2. 14.T7.F& 0.A2.T24.F8. 5.T40.F1Q O.T52.F8. O.
C 1"65. Al. F5. 1. "y.". AI)
GO TO 5:35
532 WRITE (ILP.50b) I.RTMX.KLI.RTPG.RMNT.RENH.Ll.RCFD.L2
506 FORMAT (12. I4.T7.F8. 2.A2.F8. 5.T40.F1Q 0.T52.F8. O.
C T65. Ai. F5. 1. ,.~t.". (41)
5::::5 CONT I NUE
IF (J~EQ. 2) LG=2
550 CONTINUE
r'
C***#,",###4t~:\:##*t:"*######*####:It#####,",###1*###t.~###ti:'"''":##jl####1i'jt*1~:,",##,",,",####,",,",####
c
CALCULATE NEXT /T' INTERVAL
0483
0484
04:=:5
0-'+::::6
04::::::
0489
0490
0491
560
!56:;;O
04·92
56'~
049:3
\)494
0495
C
0'1-9'::.
566
04';17
0498
0499
0500
0502
050'~
0506
O:::iO::::
0509
0510I
c
570
GO TO (560.570), ISFG
IXFLG=l
I XFG=.1
IF (JSFLG+ISFLG. LT. 4) GO TO 562
.J:3FLG=1
I:::;FLG=1
CONT I NUE
GO TO (564.566).JSFLG
T·'r+RINC
!:;=S+RINC
1=1+1.
GO TO 56f:::
. . . .. SCRUE: SOFT ERROR:::: ....
S:::RZER
CONTINUE
TSFT'''S
THRD=T
IF « S. GE. (SLM./RTSF) l. AND. (SLM. NE. RZEH I) I XFLG=2
IF (.JSFLG. EQ. 2) I :::;FLG=2
IF tIXFLG. EQ. 2) JSFLG=2
IF « LG. EO. 2). AND. (I8FU3. EQ. 1»
J8FLG=1
IXFG::::I:3FLG
GO TO 580
CONTINUE
. ... SPECIAL MODE AVERAGE SOFT -ERROR RATE
3·195
intJ
FORTRAN IV
O!'.:il1
0~512
051::':
0514
051.5
051.6
574
576
O:::ij, 7
0511:3
I XF13=:3
T"'T+RINC
1"=1+1
GO TO (574.5761. IXFLG
:3:=S+R I NC
GO TO 57::::
:;::;""RZER
I XFU3:=: 1
05l -:;-,
0520
578
0521
O!522
0524
O!:i2~5
05:;'~7
('52'~)
AP·73
V02. 04
580
r·
C
CONTINUE
THRD-::::T
T:::;FT'",::::;
IF (SLM. EQ. RlERJ GO TO 580
TSFT:R1+(SLM/l000. )
IF (& GE. (SLM/RTSF» IXFLG=2
IF (IXFLG. EO. 2) IXFG~4
CONTINUE
END EOU{4TION LOOP ....
C$$$.S"$$S$'$$""$$$"""'$S'$"$$$'$'$$"""'$$$$S$$"'S$$S$S$$S$$$
C
05:30
05:31
05::::2
585
C
IFLG=O
GO TO (585,590). IDFLG
CONTINUE
ITERATE TILL LIST COUNT ....
O~i:3~3
I FU3"'" 1
05:34
05:36
IF (CI. GT~IUlM). OR. IRTPG. LE. RALMT» GO TO 650
GO TO 400
CONTINUE
ITERATE TILL R(T) BELOW LIMIl·
IF «La EQ~l~. OR (ILFLa EQ. 2» GO TO 660
ACCELERATE FAILURE RATE ....
RINC=RINC*IDBK
590
053'7
C
05:38
C
0540
0541
0542
054:3
0544
0546
0547
0549
0550
0551
0552
ILFLG~2
660
,-.
595
600
650
RENH::::O.O
IF (RTPG. GT. RALMT> WRITE (ILP. 595)
IF (RTSED.GT. 1. 0) RENH=RMTTF/RTSED
0553
0554
0556
CONTINUE
IFLG=2
IF (RTPa LE. RALMT) GO TO 650
IFLG=:3
IF (I. LT. IULM*I(:::::T) GO TO 400
WRITE (ILP.5951
FORMAT (T2. ~****~)
CONTINUE·
CONTINUE
r·
C#####################:H::H:##:H::H::H::H:#:H:#:H:######:H:#######:H::H:#### #:H:#########:H:######:
c
THIS IS, IT .....
,~
SYSTEM MTBF
C
C#####:H:##############:H:#######:H:##:H:###########~######### ################-
0558
0559
675
WRITE (ILP.675) I.RTMX.RTPG.RMTTF.RENH
FORMAT (T38. '=MEMORY MTBF=~.4X. ~=EF='.I.T2. 14. T7. F1Q 2.
3-196
Ap·73
FORTRAN IV
V02. 04
C
0560
0561
0562
0563
0564
0565
0566
0567
05t,S
0569
0570
0571
('573
0574
676
677
678
Rr::~VS=RMTTF
RZTMP=O. 0
679
CONTI~UE
IF (RTSED. GT. 0. 0) RENH=RTSYS/RTSED
WRITE (ILP, 680) IFLG. RT8YS, RENH. RZTMP
6::::0 FORMAT (T2, "FIW, IX. 13. T24, ~=SYSTEM MTBF=~.T40,F12. 2,T52,F8, 0,
C fb5.EI2. 5.1. lHl)
GO TO 100
END
0575
0576
FORTRAN IV
0001
0002
0003
RZTOL=1000. /RMTTF
GO TO (676,677,67S),JXFG
RZTMP=RZTOL+RZSYS
RTSYS=1000. O/RZTMP
GO TO 679
RZTMP=RZTOL+RZSYX+
I MF'U C IT REAL *8 ( R)
DATA Rt/l. 0001
.
C##################i######i#iiiiii#iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii#i
C
C
RS (T) FUNCTION
C
0004
0005
0006
C######################i###iiiii##iiii#iii#iiiiiiiiiiiiiiiiiiiiiiiiiiiiii
DRTI=(RI/DEXP(RZX*RT»* '
RfRM2=RN*RQX*",
f' ./. T 17 •..,:> 1. - NUMBER OF MEMORY ROWS PER BOARD ....• /.
C T2. "'BOARD::::;: ...• T12. 4( ........... "'). T50. '··:::DATA TYPE INTEGER:>", /.
C T 1 7 •..,:> 1 - NUMBER OF BOARDS PER MEMORY SYSTEM. ". /)
WRITE (ITOUT.40)
FORMAT (T20.' ** HIT (RETURN) TO CONTINUE **')
READ (ITIN.45) IDUM
FORMAT (A2)
WRITE (ITOUT.50)
FORMAT (/I.T20.' • ADDITIONAL POI~TER PARAMETERS . ' . / / ,
c T2. "POINTER: ...• T12, 4·( ........ , .. "). T50. "'(DATA TYPE LITERAL)", /,
LIST OUTPUT PARAMETERS. ',/,
C T15. 'LIST
MEMORY COMPONENT & SYSTEM PARAMETERS. ',/,
C T15. 'SIZE
r' TIS. 'RATE
COMPONENT & SYSTEM FAILURE RATE& ',/,
f' T15,
f"' Ti5.
0017
0018
0019
0020
C!:'t;;'
._' .. _1
c
"'[lIST
~COMM
COMPONENT FAILURE-TYPE DISTRIBUTION. "', /J
OUTPUT RUN-TIME COMMENT LINE~)
\
WRITE (ITOUT.55)
FORMAT (TI5. 'ABORT EXIT PROGRAM. ',/,
C TIS. 'DUMP
DISPLAY
~ LIST, SIZE, RATE, DIST, COMM ) ' , / ,
C T15. "'PUf':GE PRINT RE!;T OF RUN-TIME OUTPUT BUFFER', //,
r'-' Tl.5. "'FLAG
USE OF TTL & SYSTEM FAILURE RATES,
Q-FLAG", /,
I~
T22, "SYS ::::: TTL. @ BOARD LEVEL, SYSTEM USED WITH MEMORY', /,
C T22. "MPD ::::: TTL N. U., SYSTEM RATE LISTED IN HEADER ONLY', /,
I~
T28, "'SOFT ERROR RATE SPECIAL MPD ALGORITHM - MEM CYCLES', /"
r' T22, ..' MSO
(TTL X BOARDS) + SYSTEM COMB I NED WITH MEMORY"', /,
::::: ONE DIMENSIONAL ARRAY MODEl", /,
C T22, "C!l
SAME AS e!L PLUS SPECIAL TWO DIMENSIONAL FIX"', /,
C T22, 'C!2
C TI0,5('********/).//'/)
RETURN
'
END
END OF PROGRAM
3·202.
inter
Ap·73
SYS /Q1
ECC PROBABILITV PROGRAM
II
INTEL-MPD/MC.
II'
MEMORV SVS: SIZE-)
32.0KB
WORD WIDTH-) 16.+ 6. NO.PAGES-~
1. X 1.
COMPONENT: TOTAL-)
16. +
6.
RAM SIZE-)
16384. COL SIZE-) 128.
SYSTEM DATA:
TTL RATE -) O. OOOOOY./1K-HRS, SYSTEM RATE -) O. 00000Y./1K-HRS
MTBF. NECC -)
49212. 60HRS, MTBF. SVS -)
O. OOHRS
FAILURE DATA:
HARD ERRORS:
PARTIAL -)O.CELLS/PG RATE -)
0.027000Y. / 1000 HRS
SOFT ERRORS:
"*" MAINT -)
O. HRS, RATE -)
O. 100000Y. / 1000 HRS
ANALVSIS DATA:
PERIOD -) 100000.00HRS, AVE CELL FAILURE -)
16.2
FAILURE TVPE RATIOS: -------------------------------------------------=TVPE=
=DISTRIBUTION=GEOMETRV=UNIT.RATE/1K HRS=AVE.CELLS=ECC. DISTR=EXPS=
SOFT ERROR -)[ 78. 740Y.J/ 16384. = 0.61035E-05Y.,
0.787 [ 4. 87Y.J
HARD ERRORS -) [ 21. 260Y. J
[ 95. 13Y.]
SINGLE CELL -) 50.0000Y. / 16384. = 0.82397E-06Y.,
0.106
0.69Y.
1.
ROW' OR COL -) 43.7000Y. /
128. = 0.92180E-04Y.,
11.892
77.36Y. 128.
COLUMN/ROW -) 6.2000y' /
h4. = 0.26156E-04Y.,
3.374
21. 95Y.·
2.
HALF CHIP
-) O. OOOOY. /
2. = O. OOOOOE+OOY.,
O. 000
O. OOY.
32.
TOTAL CHIP -) O.OOOOY. /
1. = O.OOOOOE+OOY.,
0.000
O.OOY.
2.
PERIOD
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PM@T:
<:M- HRS)
0; 00
0.10
O. 20
O. 30
O. 40
O. 50
O. 60
O. 70
O. 80
0.90
1. 00
1. 10
1. 20
1. 30
1. 40
1. 50
1. 60
1. 70
1. 80
1. 90
2. 00
2.10
2. 20
2. 30
2.40'
2. 50
2. 60
2. 70
2. 80
2.90
3. 00
RCTl.SECC
=FlINCTION=
1.00000
O. 99332
O. 97389
O. 94293
O. 90200
O. 85289
O. 79748
O. 73770
0,67537
0.61217
O. 54958
O. 48884
O. 43095
O. 376M
O. 32650
O. 28075
O. 23956
O. 20290
O. 17062
O. 14248
O. 11819
O. 09741
O. 07979
O. 06496
O. 05258
O. 04232
O. 03388
O. 02698
O. 02137
O. 01685
O. 01322
****
3. 00
31
O. 01322
MTTF
HRS )
O.
14922026.
7584078.
5149121.
3939900.
3221005.
2747323.
2413825.
2168007.
1980705.
1834422.'
1718017.
1624061.
1547397.
1484334.
1432149.
1388787.
1352665.
1322533.
1297395.
1276437.
1258993.
1244505.
1232508.
1222606.
1214463.
1207796.
1202358.
1197945:
1194379.
1191512.
<:
ENHANCEMENT
FACTOR
O.
303.
154.
105.
80.
65.
56.
49.
44.
40.
37.
35.
33.
31.
:30.
29.
28.
27.
27.
26.
26.
26.
25.
25.
25.
25.
25.
24.
24.
24.
24.
=MEMORV MTBF=
1175755.35
·=EF=
24.
1175755.35
24.
Y. - R(T)
@T
100. OY.
99. 3Y.
97. 4Y.
94.3,.;
90. 2Y.
85. 3Y.
79. 7Y.
73.
8~1.
67.
61.
55.
48.
5Y.
2Y.
OY.
9X
4:3. 1:'1;
37. n;
<: 32. 6Y.)
28. 1Y.
24. OY.
20.3:'1;
17. lY.
14. 2Y.
11. 8Y.
9. 7Y.
8. OY.
6. 5Y.
5. 3Y.
4.2Y.
3. 4Y.
2. 7Y.
2. lY.
1. 7Y.
1. 8Y.
---------------------------------------------------------------FIN
1
=SYSTEM MTBF=
3·203
O. 85052E-03
intJ
Ap·73
------------------------------------------------------------------------
SVS /Ql
ECC PROBABILITV PROGRAM "INTEL-MPO/MC. "
MEMORV SVS: ,SIZE-)O
4. 1MB
WORD WIDTH-)O 1·6. + 6, NO. PAGES-)O
1. X128.
COMPONENT: TOTAL-)O 2048. +
768.
RAM SIZE-)o
16384. COL SIZE-)O 128.
SVSTEMDATA: TTL RATE -)0 O. OOOOOX/IK-HRS, SYSTEM RATE -)0 O. OOOOOX/IK-HRS
FAILURE DATA: MTBF. NECC -)0
384. 47HRS, MTBF. SVS - ) 0 .
O. OOHRS
HARD ERRORS:
PARTIAL -)0
O. CELLS/PG RATE -)0
O. 027000X / 1000 HRS
SOFT ERRORS:
"*" MAINT -)0
O.HRS, RATE -)0
O. 100000X / 1000 HRS
ANALVSIS DATA:
PERIOD -)0
8000. OOHRS. AVE CELL FAILURE -)0
16. 2
FAILURE TVPE RATIOS: ------~------------------------------------------=TVPE=,
=DISTRIBUTION=GEOMETRV=UNIT. RATE/IK HRS=AVE. CELLS=ECC. DISTR=EXPS=
SOFT ERROR -)o[ 78. 740X]/ 16384. = 0.61035E-05X.
0.787 [ 4. 87XJ
HARD ERRORS -)o[ 21. 260XJ
I
[
95. 13XJ
SINGLE CELL -)0 50.0000X / 16384. = 0.82397E-06X,
0.106
0.69X
1.
ROW OR COL -) 43.7000X /
128. = 0.92180E-04X.
11.892
77.36X 128.
COLUMN/ROW -) 6.2000X /
64.::: 0.26156E-04X,
3.374
21.95r.
2.
HALF CHIP
-)0 O. OOOOX /
2.::: O. OOOOOE+OOX,
O. 000
O. OOX
32.
TOTAL CHIP -) O. 0000r. /
1.::: O. OOOOOE+OOr..
O. 000
O. OOX
2.
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
PM@T:
HRS)O
O.
8000.
16000.
24000.
32000.
40000.
48000.
56000.
64000.
72000.
80000.
88000.
96000.
104000.
112000.
120000.
128000.
136000.
144000.
152000.
160000.
168000.
176000.
184000.
192000.
200000.
208000:
216000.
224000.
232000.
240000.
31
240000.00
PERIOD
----- <: 0
1
2
3
4
5
6
7
8
9
10
11
FIN
1
R[TJ. SECC
=FUNCTION=
1. 00000
O. 99446
O. 97804
O. 95132
O. 91518
O. 87080
0.81955
O. 76294
O. 70256
O. 63998
O. 57670
O. 51411
O. 45341
O. 39562
O. 34153
0.29171
O. 24653
O. 20616
O. 17059
O. 13968
O. 11318
O. 09076
0.07202
O. 05656
O. 04397
O. 03382
O. 02575
O. 01941
0.01448
O. 01069
O. 00782
0.00782'
=SVSTEM MTBF=
ENHANCEMENT
FACTOR
O.
O.
3744.
1439611.
722580.
1879.
1260.
484470.
366101.
952.
295638.
769.
249140.
648.
216349.
563.
192135.
500.
173652.
452.
159190.
414.·
147663.
384.
138346.
360.
130737.
340.
124475.
324.
119297.
310.
115001.
299.
111433.
290.
108471.
282.
106017.
276.
103990.
270.
266.
102322.
263.
100958.
99849.
260.
257.
98954.
256.
98237.
97668.
254.
97220.
253.
252..
96872.
96603.
251.
96397.
251.
=MEMORV MTBF=
=EF=
95643.55
249.
MTTF
< HRS
)0
95643. 55
249.
X - R(T)
@T
100. Or.
99. 4r.
97. 8r.
95. IX
91. 5r.
87. lr.
82. OX
76. 3X
70. 3r.
64. Or.
57. 7r.
51. 4r.
45. 3X
39. 6r.
< 34. 2r.>
29. 2X
24. 7r.
20. 6X
17. lr.
14. OX
11. 3X
9. lr.
7. 2r.
5. 7r.
4. 4r.
3. 4r.
2. 6r.
1. 9r.
1. 4r.
1. lr.
O. 8r.
O. 10455E-Ol
intJ
AP-73
SVS /Q1
ECC PROBABILITV PROGRAM "INTEL-MPD/MC. "
WORD WIDTH-> 32. + 7. NO. PAGES->
1. X 1.
MEMORV SVS: SIZE->
64. OKB
7.
RAM SIZE->
16384. COL SIZE-> 128.
COMPONENT: TOTAL->
32. +
SYSTEM RATE -> 0.00000Y./1K-HRS
SYSTEM DATA:
TTL RATE -> 0.00000Y./1K-HRS,
FAILURE DATA:
MTBF. NECC ->
24606. 30HRS, MTBF. SVS ->
O. OOHRS
HARD ERRORS:
PARTIAL ->
O. CELLS/PG RATE ->
O. 027000Y. / 1000 HRS
SOFT ERRORS:
"*" MAINT ->
O. HRS, RATE ->
O. 100000"~ I" 1000 HRS
ANALVSIS DATA:
PERIOD ->
66000. 'OOHRS, AVE CELL FAILURE ->
16.2
FAILURE TVPE RATIOS:
-------------------------------------------------=TVPE=
=DISTRIBUTION=GEOMETRV=UNIT. RATE/1K HRS=AVE. CELLS=ECC. DISTR=EXPS=
SOFT ERROR ->[ 78. 740Y.J/ 16384.
O. 61035E-05Y.,
O. 787
[
4. 87Y.J
HARD ERRORS ->[ 21. 260Y.J
( 95. 13Y.J
SINGLE CELL -) 50. 00001. / 16384.
ROW OR COL
COLUMN/ROW
HALF CHIP
TOTAL CHIP
PM(H:
PERIOD
<:
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2:3
24
25
26
27
-> 4:3. 7000Y. /
-> 6.. 2000Y. /
-) O. OOOOY. /
-> O. OOOOY. /
- HRS>
O.
66000.
132000.
198000.
264000.
330000.
396000.
462000.
528000.
594000.
660000.
726000.
792000.
858000.
924000.
990000.
1056000.
1122000.
1188000.
1254000.
1320000.
1386000.
1452000.
1518000.
1584000.
1650000.
1716000.
1782000.
28 1782000.00
FIN
1
128.
64.
2.
=
=
=
=
1.
R[T]. SECC
=FUNCTION=
1.00000
O. 99070
O. 96388
0.92173
O. 86699
O. 80276
O. 7:3219
O. 65828
O. 58374
O. 51088
O. 44151
O. 37700
O. 31821
O. 26564
0.21942
O. 17'741
O. 14528
O. 11655
O. 09267
O. 07305
O. 05'712
O. 04431
0.03411
O. 02607
0.01979
O. 01492
0.01118
0.008:32
O. 00832
O. 82397E-061.1
O.
O.
O.
O.
~/2180E-04~1.,
26156E-04Y.,
OOOOOE+OOY.,
OOOOOE+OOY.,
O. 106
11.
3.
O.
O.
892
374
000
000
ENHANCEMENT
MTTF
FACTOR
HRS :>
O.
O.
287.
7066011.
3604737.
146.
100.
2458257.
1890484.
77.
6:3.
1554231.
1333790.
54.
48.
117'7584.
,4:3.
1066829.
981755.
40.
916096.
37.
864581.
35.
82:3686.
3:3.
'::0-:>
790958.
764629.
31.
74:3388.
30.
726238.
:30.
29.
712400.
28.
701259.
28.
692319.
28.
6·85174.
28.
679492.
27.
674998.
27.
671465.
27.
668705.
666562.
27.
664910.
27.
663644.
27.
=MEMORV MTBF=
=EF=
27.
658122. 51
<:
y~.
658122. 51 "
=SVSTEM MTBF=
3-205
27.
O. 69Y.
77.
21.
O.
O.
%
1.
128.
36Y.
2.
95Y.
32.
OOY.
2.
OOY. .
- R(T)
@T
100. o/~
99. 1 ~I.
96. 4Y.
92. 2Y.
86. 7Y.
80. 3Y.
73. 2Y.
65. 8Y.
58. 4Y.
51.1 Y.
44. 2~1.
37. n
<: 31. 8/~:>
26. 6/~
21. n
17.9Y.
14. 5Y.
11. 7/~
9. :3Y.
7. 3Y.
5. 7Y.
4. 4Y.
3. 4Y.
2. oY.
2. o/~
1. 5Y.
1. 1 Y.
O. 8/~
O. 15195E-02
AP·73
SYS /(!1
ECC PROBAB I L I TY PROGRAM "I NTEL -MPD/MC. "
MEMORY SYS: SIZE-)
8. 2MB
WORD WIDTH-) :32. + 7. NO. PAGES-)
1. X128.
COMPONENT: TOTAL-) 4096. +
896.
RAM SIZE-)
1~,:384.
COL SIZE-) 128.
SYSTEM RATE -) O.OOOOOY./ll<-HRS
SYSTEM DATA:
TTL RATE -) O. OOOOO~:Vll<-HRS,
FAILURE DATA:
MTBF. NECC'-)
192. 24HR8, MTBF. SYS -)
O.OOHRS
PARTIAL. -)
O. CEL.LS/PC; RATE -)
O. 027000Y. / 1000 HRS
HARD ERRORS:
SOFT ERRORS:
u .... "
MAINT -)
O. HRS, RATE -:>
o. 100000Y. / 1000 HRS
ANALYSIS DATA:
PERIOD ->
5000.00HRS, AVE CELL FiULURE -)
16.2
FAILURE TYPE RATIOS:
-------------------------------------------------=TYPE'"
=DISTRIBUTION:::GEOMETRY=UNIT. RATE/ll< HRS=AVE. CELLS=ECC. DISTR=EXPS=
SOFT ERROR -)( 78. 740/;]/ 16:384. =
O. 61035E-05/;,
O. 787
[
4. 87'0
HARD ERRORS -> [ 21. 260/;]
[ 95. 13"; J
SINGLE CELL -> 50. 0000:1. .I 16:384.
O. 8239-'E-06Y.,
O. 106
O. 69/;
1.
128. .- O. 92180E-04/;,
11. 8'n
ROW OR COL
-:> 4':;' 7000:1; /
77. :36Y.
128.
'COLUMN/ROW -)- 6. 2000Y. /
64. ==
O. 26156E-04Y.,
3. 374
21. 95Y.
2.
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2.
O. orjOOOE+OO:'l;,
O. 000
O. OOY.
32.
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1.
O. OOOOOE+OOY.,
O. 000
O. OOY.
2.
TOTAL CHIP
-> O. 0000"/; /
.",.
10
11
12
1:3
14
15
16
17
18
19
20
21
22
23
24
25
26
27
PM@T:
HRS)
O.
5000.
10000.
15000.
20000.
25000.
:30000.
:35000.
40000.
45000.
50000.
55000.
60000.
65000.
70000.
75000.
80000.
85000.
90000.
':;'5000.
100000.
105000.
110000.
115000.
120000.
125000.
130000.
135000.
28
135000. 00
PERIOD
<:
0
1
2
.:;.
'-'
4
5
6
7
8
.
~
FIN
1
-
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=FUNCTION=
1. 00000
O. 99306
O. 97257
O. 93'5"40
O. 89494
O. 84095
O. 7794~,
0 .. 7121.:8
O. 64283
O. 57202
O. 50219
O. 4:::14':;'9
O. 37176
0 312:51
O. 2~,090
O. 21425
O. 17:364
O. 13888
O. 1096::::
O. 08542
O. 0656'5"
O. 04987
O. 037:37
O. 027eo5
O. 02019
O. 0145l:,
O. 01037
O. 00729
O. 00729
(
MTTF
HRS
:>
ENHANCEMENT
FiKTOR
O.
:37:36.
1877.
1260.
954.
772.
652.
568.
506.
460.
4'7'':'
394.
:371.
352338.
326.
:316.
308.
:301.
296.
292.
28'7.
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718156.
360766.
242201.
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125:392.
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97356.
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81346.
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678:35.
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57'71:3.
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56116.
55486.
54992.
54609.
54316.
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283.
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-
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99. 3Y.
97. 3Y.
93. 9Y.
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84. 1Y.
77. 9Y.
71. :3Y.
64. 3Y.
57. 2Y.
50. 2Y.
43. 5Y.
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26. lY.
21. 4/;
17.4Y.
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WORD WIDTH-> 64. + 8. NO. PAGES-)
1. X 1.
MEMORV SVS: SIZE-)
128. OKB
8.
RAM SIZE-)
16384. COL SIZE-) 128.
COMPONENT: TOTAL-)
64. +
SYSTEM DATA: TTL RATE -> O.000007./1K-HRS, SYSTEM RATE -) O.OOOOOr..tlK-HRS
FAILURE DATA:
MTBF. NECC -)
12303. 15HRS, MTBF. SVS -)
O. OOHRS
HARD ERRORS:
PARTIAL -)
O. CELLS/PG RATE -)
O. 0270007. / 1000 HRS
SOFT ERRORS:
U*U MAINT
-:>
O. HRS, RATE -)
O. 1000007. / 1000 HRS
ANALVSIS DATA:
PERIOD ->
33000. OOHRS, AVE CELL FAILURE -)
16. 2
FAILURE TVPE RATIOS: -------------------------------------------------=TVPE=
~DISTRIBUTION=GEOMETRV=UNIT. RATE/1K HRS=AVE. CELLS=ECC:DISTR=EXPS=
SOFT ERROR -)[ 78. 740%]/ 16384.
O. 61035E-05Y.,
O. 787 [ 4. 87Y.]
HARD ERRORS ->[ 21. 2607.]
[ 95. 13Y.]
SINGLE CELL -) 50. 00007. / 16384. = o. 82397E-067.,
O. 106
O. 69Y.
1.
ROW OR COL -> 43.70007. /
128. = 0.92180E-04Y.,
11.892
77.367. 128.
COLUMN/ROW -> 6. 2000Y. /
64. = O. 26156E-047.,
3. 374
21. 95Y.
2.
HALF CHIP
-) 0.00007. /
2. = O.OOOOOE+OP7.,
0.000
0.007.
32.
TOTAL CHIP -) O. OOOOY. /
1. = O. OOOOOE+OOY.,
O. 000
O. OOY.
2.
26
27
28
29
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- HRS)
O.
33000.
66000.
99000.
132000.
165000.
198000.
231000.
264000.
297000.
330000.
363000.
396000.
429000.
462000.
495000.
528000.
561000.
594000.
627000.
660000.
693000.
726000.
759000.
792000.
825000.
858000.
891000.
924000.
957000.
30
957000.00
PERIOD
,~
....
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
FIN'
1
R[TJ. SECC
""FUNCTION=
1. 00000
0.99197
O. 96871
O. 93192
0.88376.
O. 82663
O. 76308
O. 69556
O. 62639
O. 55758
O. 49083
O. 42747
O. 36848
O. 31451
O. 26592
O. 22280
O. 18504
O. 15240
O. 12450
O. 10093
0.08120
O. 06487
O. 05146
O. 04056
0.03176
O. 02472
0.01912
O. 01471
0.01125
0.00856
0.00856
MTTF
ENHANCEMENT
FACTOR
HRS >
O.
O.
4092667.
333.
169.
2084463.
1418701.
115.
1088549.
88.
892655.
73.
62.
763911.
673564.
55.
607238.
49.
556949.
45.
42.'
517906.
487054.
40.
462357.
38.
442398.
36.
426159.
35.
412889.'
34.
402018.
33.
393104.
32.
385797.
31.
379818.
31.
374936.
30.
370964.
30.
367744.
30.
3651'47.
30.
363061.
30.
361395.
29.
360071.
29 ..
359025.
29.
358203.
29.
357561.
29.
=MEMORV MTBF=
=EF=
354499. 33
29.
<
=SVSTEM MTBF=
354499. 33
3-207
29.
7. - R(T>
@T
100. OY.
99. 2Y.
96. 9Y.
93.2Y.
88. 4Y.
82. 7Y.
76. 37.
69. 67.
62. 6Y.
55. 8Y.
49. lY.
42. 7Y.
< 36. 87.>
31. 5Y.
26. 6Y.
22. 3Y.
18.5Y.
15. 2Y.
12. 5Y.
10. 17.
8. lY.
6.5Y.
5. lY.
4. 17.
3. 27.
2. 5X
1.9X
1. 5X
1. 17.
0.9X
/0. 28209E-02
AP':73
SYS /Q1
ECC PROBAB I L I TY PROGRAM "I NTEL -MPD/MC. "
MEMORY SY::;: ::::1 ZE-:>
16.4MB
WORD WIDTH-) 64. + 8. NO. PAGES-)
1. X 128.
COMPONENT: TOTAL-:> 8192. +
1024.
RAM SIZE-)16384. COL SIZE-) 128.
SYSTEM DATA:
TTL RATE -:> O.OOOO():'!;/U<-HRS,
SYSTEM RATE -:> O. 00000~/;/1K-HRS
FAILURE DATA:
MTBF. NECC -)
96. 12HRS, MTBF. SYS -)
O. OOHRS
HARD ERRORS:
PARTU~L -)
O. CELLS/PG RATE -)
O. 027000:Y. / 1000 HRS
SOFT ERRORS:
"*" MAINT ->
O. HR:::;.. RATE -}
O. 100000:Y. / 1000 HRS
ANALYSIS DATA:
PERIOD -)
2500. OOHRS, AVE CELL FAILURE ->
16. 2
FAILURE TYPE RATIOS:
-------------------------------------------------=TYPE=
=DISTRIBUTION=GEOMETRY=UNIT. RATE/H:: HRS=AVE. CELLS=ECC. DISTR=EXPS=
SOFT ERROR -).( 7E:. 740:Y.]./ 16:384. -. 0.61035E-05/;,
O. 787
[
4. 87:Y.]
HARD ERRORS -)[ 21. 26.0~1.]
[ 95. 13:Y.]
SINGLE CELL -} 50. O(H)O/; ./ 16384.
O. 82:397E-06/;,
O. 106
O. 69:Y.
1.
ROW OR COL -) 4::::. 7000/;.1
128.
O. 92180E-04/;,
11. 892
77. :36:Y.
128.
COLUMN/ROW -) 6. 2000:Y. .I
64.·- o. 26.156E-04/;,
3. :374
21'. 95:Y.
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12
1:3
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
PM@T:
HRS)
O. M2500.
5000.
7500.
10000.
12500.
15000.
17500.
20000.
22500.
25000.
27500.
:30000.
::::2500.
35000.
37500.
40000.
425€)0.
45000.
47500.
50000.
52500.
55000.
57500.
60000.
62500.
65000.
67500.
70000.
72500.
30
72500. 00
.PERIOD
0
1
2
3
....". -
4
5
6
7
8
9
10
11
FIN
1
R[T]. SECC
=FUNCT I1)N=
I. 00000
O. 99401
O. 'i'7629
O. 94·751
O. 9086'::'
O. 86119
o. :::<)65::::
O. 746.58
O. 682':'/8
O. 61752
O. 55187
O. 48749
O. 4256,6
o. :36741
O. 31350
O. 26445
O. 2205:3
o. 1818::::
O. 14E:22
O. 11947
O.
-(
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3·~8.
28975.
==MEMORY MTBF=
28758. 48
28758. 48
299.
:3041·~.
O.
O.
O.
O.
O.
O. 00748
ENHANCEMENT
FACTOR
O.
4 ',:!-':I'-'
2175.
1459.
110:3.
8';' I.
752.
654.
58 I.
526.
483.
448.
421.
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352.
342.
334.
:327.
321.
316.
313.
310.
307.
306.
304.
303.
302.
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299.
0'~521
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05847
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034::::4
02588
o. 01929
O. 01422
O. 01037
O. 00748
MTTF
HRS )
O.
416.:361.
209042.
140217.
106020.
85676.
72264·.
62816.
55851.
50543.
46400.
4::::106.
4045:3.
:3:3295.
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::::5074.
3:3876.
32888.
32075.
31407.
:30862.
30061.
29774.
29546.
2·~367.
29227.
29120.
2·~0::::7.
==SYSTEM MTBF=
3-208
-
R(T)
@T
100. (n
9~'. 4:Y.
97. 6:Y.
94. 8:Y.
90. 9:'1;
86. 1:Y.
80. 7r.
74. 7r.
68. 3:Y.
61. 8/;
55. 2:Y.
48. 7r.
4'/ 6/;
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31. :3/;
26. 4/;
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1/;
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n;
O. 34772E-Ol
ARTICLE
REPRINT
AR-189
November 1981
Reprinted with permiSSion from ElectrOniC Design September 30 1981 Copyrrght Hayden Publlshmg Co All fights reserved
AFN-02124A
ORDER NUMBER- 210287 001
4
3-209
A new error-correction chip with dual-bus architecture interfaces
easily with dynamic RAMs. Memory-system reliability soars and the
additional parts count is relatively modest.
Keep memory design simple
yet cull single-bit errors
In memory-system design, the demand for greater
reliability is reflected by an increasing interest in
error-detection and correction circuitry. Several
semiconductor manufacturers have recently introduced error-detection and correction chips. They
share a common architecture that features a
multiplexed data bus. But the Intel 8206 errordetection and correction unit (EDCU) is different:
This LSI device, fabricated in HMOS II, allows error
correction to be added to memory systems with
minimal overhead.
A single 8206 handles 8 or 16-bit data widths, and
I,Ip to five 8206's can be cascaded to handle all
multiples of eight bits (up to 80 bits). The 8206
corrects single-bit errors in a maximum of 65 ns for
16-bit systems and typically replaces 20 to 40 ICs, .
depending upon the number of featu.res in the
system.
Common error detection circuits simply recognize
that data has a parity error. Correction. circuits use
the Hamming code as an extension of parity to detect
and give the position of the error, allowing it to be
corrected.
Single-bit correction and
multiple-bit detection is the
typical implementation, reflecting the tradeoff between the probability of errors in a system and the cost
of additional memory. For a
16-bit system, single-bit error correction and doublebit error detection is imM. Bazes, Design Engineer
L. Farrell, Marketing Manager
B. May, Appltcatlons Engineer
M. Mebel, Design Engineer
Intel Corp. 3065 Bowers Ave.
Santa Clara. CA 95051
plemented by using 6 additional check bits, for an
overhead of 37% (Table I). Adding single-bit error
correction to a system improves system reliability
by at least a factor of 24 (Table 2).
Error correction is used extensively in mainframe
and minicomputer design where memory sizes of
several megabytes are common. Here the probability
of error is directly related to the error rate of the
individual RAMs and the number of RAMs in the
system. As the number of RAMs increases, so does
the system error rate.
With today's microprocessors, like the Intel eightbit iAPX 88 and 16-bit iAPX 86 (each can directly
address 1 Mbyte), typical RAM memory sizes are 100
kbytes and climbing. As a result, microprocessor
system designers are looking to add error correction
as simply as possible.
New bus architecture
The 8206 is the first 16-bit EDCU to use separate
input and output data buses, a feature that simplifies
system design, saves board space, and reduces parts
count. The new architecture
is made possible by packaging the 8206 in a JEDEC
type A 68-pin lead less chip
carrier. Figure 1 shows the
8206's functional blocks.
During read cycles, data
'. and check bits enter via the
data input (DI) and check-bit
input (CBI) pins, where they
are optionally latched by
the 8m input. The data tfien
take two parallel paths. The
first path is to the dataoutput (DO/WDI) pins, where
the uncorrected data are
available 32 ns later. The
second path is to the checkSeptember 30. 1981
3-210
Memory Technology: Error-correctiQn chip
bit generator, where check bits generated from the
data are compared with the check bits read from the
memory.
The result of the comparison is the syndrome, a
5-to-8-bit value identifying which bit (if any) was in
error. The syndrome is then decoded to a l-of-16 bit
strobe which is used to "flip" the bit in error
(assuming theCRC'f input is active). Syndrome decoding also tells the 8206 whether to assert the error
flags. The 16 data output pins are enabled on a byte
basis by the liM inputs.
For write cycles, data enter the write data input
(no/wm) pins and goes to the check-bit generator.
The check bits are then written to the check-bit
memory by the check-bit output (SYO/CBO/PPO) pins.
These pins also output the syndrome bits during read
or read-modify-write cycles.
Note that only the 8206's RiW pin is typically used,
for contrdl during a memory cycle. This pin informs
the 8206 whether the cycle is a read (generate new
check bits and compare to those from memory) or
a write (generate new check bits only). During a readmodify-write cycle, a falling edge of R/W tells the
8206 to latch the syndrome bits intllrnally and output
check bits to be written back into memory. The strobe
input (STB) may optionally be used to latch data and
check bits internally.
The 8206's dual-bus architecture saves the additional control lines and the sequencing logic required
":~L
hit
~
16
latc.!'
STe
CBI/SYlo
7
,.
SVO/CBOI
PPOO 7
e
PPIIPOSlNSL+-
e
Check bit
syndrome
partial panty
generator
I'"
4
pos. •
NSLo •
Ue
Data word bits
Check bits
Overhead %
(Ncheck blts/N data
bits)
8
5
62
16
6
37
32
7
22
64
8
12
80
8
10
Table 2. Single-bit error correction Increases
memory reliability a minimum of 24 times.
MTBF
(no error
correction)
'Memory Size
I-
56 Years
64 "
27 "
751 "
28
128 "
14 "
40.5 "
29
108 "
246
5 Mbytes
133.6 Years
16 Days
8 "
6.1 •
278
16 "
4 "
33 "
301
'Based on a IS kblt dynamiC RAM With a failure rate of 0 127% every 1000 hours
Note MTBF, though related to memory Size, also depends on memory organization (e 9 word
Width, number of pages) that IS not detailed In thiS table
2 POSo..
ERROR
fv--+--
CE
r
,..L
It
I
~
I---< CRCT
Syndrome
decoder
and
error
delectlon
r=: sy~~~~me ~
t
24
8 "
.~
~
2 NSLo
Data
correction
'6
~
_~OO/WOIg..I:'
1
..
POS.·H2
GND
SELL
5V
11
v,.
v~
wz
BMo,
1. The '8206's two 16-blt data buses. one for data from the RAM (010-,5) and one for data to the system bUB
(000-'5)' minimize the external control logic required,
EI....'onlc D••lgn • September 30, 1981
MTBF
Improvement
ratios
32 kbytes
Write
partial panty
generator
M/S>--
MTBF
(Single-bit error
correction)
16
Read
partial parity
generator
Check bit
latch
Table 1. Check bits required for slngle-bit
correction, multlple-bit detection.
3-211
by single-bus EDCUs. The principal advantages of
dual-bus architecture can be illustrated by looking
at the three types of memory cycles: reads, writes,
and read-modify-writes.
In a read cycle (Fig. 2), data and check bits are
received from the RAM outputs by the DI and C{lI
pins. New check bits are generated from the data
bits and compared to the check bits read from the
RAM. An error in either the data or the check bits
read from memory means the generated check bits
will not match the read check bits. If an error is
detected, the ERROR flag is activated and the correctable error (CE) flag tells the system if the error is
(or is not) correctable.
With the BM inputs high, the corrected word
appears at the DO pins (if the error was correctable),
or the unmodified word appears (if the error was
uncorrectable). Note that for this correction cycle
there is no control or timing logic required. The 8206's
dual buses isolate the RAM outputs from the EDCU
outputs. Special transceivers that prevent contention
between the uncorrected RAM data and corrected
EDCU data are not needed.
A syndrome word, five to eight bits in length and
containing all necessary information about the existence and location of an error, is provided at the
syndrome output (SYO/CBO/PPO) pins. Error logging
is accomplished by latching the syndrome and the
memory address of the word in error. The syndrome
decoding of Table 3 can be used as a table lookup
by the CPU.
If an error is detected during a read, the read cycle
is extended to a read-modify-write cycle where the
corrected data is rewritten to the same location. This
offers several 'advantages:
• Since soft errors are random, independent processes, the longer a soft error is allowed to remain
in memory, the greater the probability that a second
soft error will occur in the memory word, resulting
in an uncorrectable double-bit error. By writing the
correct data back to RAM, the mean "lifetime" of
soft errors is reduced, greatly reducing the chance
of double-bit errors, and increasing reliability.
• "Error scrubbing" (going through the entire
memory and correcting any soft errors) may be done
as a background software task. For instance, the 8086
microprocessor's load string (LODS) instruction can
consecutively read all addresses in RAM. Any soft
errors will be corrected. Scrl!bbing further increases
system reliability,
• Error logging may be used to detect hard errors.
(A soft error is seen once when the affected word
is read and is then corrected, while a hard error is
seen again and again.) An error logger shows a
consistent pattern if a hard error is present in a
particular word. A system may be configured to
• Uncorrected data
. Uncorrected
check bits
2. The 8206 requires no control logic or timing inputs to
perform read-with-correction cycles.
• Uncorrected data
. Uncorrected
check bits
Corrected data
3. The 8206 can correct both data bits and check bits.
generate an interrupt when the 8206 detects an error.
This last advantage allows the operating system
to re-read the address where the error occurred. If
the same error re-occurs, it is assumed to be a hard '
error, and while the system can continue to function,
maintenance is indicated. The operating system may
mark that page of memory as "bad" until its PC card
3-212
Electronic D••lgn • September 30. 1981.
Memory Technology: Error-correction chip
has been serviced. Alternatively" the memory system
may reconfigure itself and map the bit where the
hard error occurred to a spare dynamic RAM
whenever the affected memory page is accessed.
When a correctable error occurs during a read
cycle (Fig. 3), the system's dynamic RAM controller
(or CPU) examines the 8206 ERROR and CE outputs
to determine if a correctable error occurred. If it did,
the dynamic RAM controller (or CPU) forces R/W
low .. telling the 8206 to latch the generated syndrome
and drive the corrected check bits onto the
SYO/CBO/PPO outputs. The corrected data is already
available on the DO/WDI pins. The dynamic RAM
controller then writes the corrected data and check
bits into memory. Once again the 8206's dual buses
allow this cycle to be implemented without special
bus transceivers.
The 8206 may be used to perform read-modifywrites in one or two RAM cycles. If it is done in two
cycles, the 8206 latches are used to hold the data and
check bits from the read cycle to be used in the
immediately following write cycle.
CPU or dynamic RAM controller, which can then perform one of several optins: lengthen the current cycle
for correction, restart the instruction, perform a
diagnostic routine, or activate the CRCT input to
enable error correction. Even with the ~ pin
WrHe cycle corrections
For a full-word write (Fig. 4) where an entire word
is written to memory, data are written directly to
the RAM. This same data enter the 8206 through the
DO/WDI pins where five to eight check bits are
generated. The check bits are then sent to the RAM
through the SYO/CBO/PPO pins for storage along with
the data word.
.
A byte write (Fig. 5) is implemented as a readmodify-write cyrle. Since the Hamming code works
only on entire words, to,write one byte of the word,
it is necessary to read the entire word to be modified,
perform error correction, merge the new byte into
the old word inside the 8206, generate check bits for
the new word, and write the whole word plus check
bits into RAM.
Error correction on the old word is important.
Suppose a bit error occurs in the half of the old word
that was not changed. This old byte would be
combined with the new byte, and check bits would
be generated for the whole word, including the bit
in error. The bit error now becomes "legitimate"; no
error will be detected when this word is read; and
the system may crash. Obvious'ly, it is important to
eliminate this bit error before new check bits are
generated.
The 8206 may alternatively be used in a "checkonly" mode with the correct (CRCT) pin left inactive.
With the correction facility turned off, the delay of
generating and .decoding the syndromes is avoided,
and the propagation delay from memory outputs to
8206 outputs is significantly shortened. In the event
of an error, the 8206 activates the ERROR nag to the
Electrqnlc 0 ••19n • September 30. 1981
4. The 8206 generates check bits and writes them to memory.
• Uncorrected data
•• Uncorrected
check bits
5. The "new data" byte Is supplied by the CPU, while the
8206 supplies the corrected old byte. The 8206 also generates
new cHeck bits.
3-213
inactive, the 8206 generates and decodes the syndrome bits, so that data may be corrected rapidly
if the CRCT is activated.
Multiple 8206 systems
A single 8206 handles eight or 16 bits of data and
five or six check bits, respectively. Up to five 8206's
can be cascaded for 80-bit data words with eight
check bits. When cascaded, one 8206 operates as a
master, and all others work as slaves (Fig. 6).
As an example, during a read cycle in a 32-bit
system with one master and one slave, the slave
calculates "partial parity" on its portion of the word
and presents it to the master through the partialparity output (SYO/CBO/PPO) pins. The master receives the partial parity at its partial-parity input
(PPIIPOS/NSL) pins and combines the partial parity
from the slave with the parity it calculated from its
own portion of the word to generate the syndrome.
The syndrome is then returned from the master to
the slave for error correction.
The 8206 uses a modified Hamming code which
was optimized for multi-chip EDCU systems. The
code is such that partial parity is computed by all
8206's in parallel. No 8206 requires more time for
logic propagation than any other, hence no single
device becomes a bottleneck in the parity operation.
The 8206 is easy to use with all kinds of dynamic
RAM controllers. Because of its dual-bus architecture, the amount of control logic needed is very small.
Data memory
16 bits
Check bits
7 bits
DI
OJ
DE
32b't~
data
bus
DO
Figure 7a shows a memory design using the 8206 with
Intel's 8203 64-kbit dynamic RAM controller and
2164 64-kbit dynamic RAM. As few as three additional ICs complete the memory control function
(Fig.7b).
For simplicity, all memory cycles are implemented
as single-cycle read-modify-writes (Fig. 8). This cycle
differs from a normal read or write primarily in
when the RAM Write Enable (WE) is activated. In
a normal write cycle, WE is activated early in the
cycle. In a read cycle, WE is inactive.
A read-modify-write cycle consists of two phases.
In the first phase, WE is inactive, and data are read
from the RAM; for the second phase, WE is activated
and the (modified) data is written into the same word
in the RAM. Dynamic RAMs have separate data
input and output pins so that modified data may be
written, even as the original data is being read.
Therefore, data may be read and written in only one
memory cycle.
In order to perform read-modify-writes in one
cycle, the 8203 dynamic RAM's CAS strobe must be
active long enough for the 8206 to access and correct
data from the RAM, and write the corrected data
back into RAM. CAS active time (tCAS ) depends on the
8203's clock frequency. The clock frequency and
dynamic RAM must be chosen to satisfy:
tCAS(~~:) ~ -tCAcRAM
+ TDVQV8°06 +
TQVQV8206 +
tDlAM
+
tCWLRAM
Data memQry
16 bits
DO
DO
01
~
1ij
&
T
DOIWDI
01
SYO/CBOCBl o_6
PP1o- e
PPI, ~
GACT,
Cont,ol {
lines
wi.
STe
A/W
B~e
marks
eMo
{
BM,
L-_
_
*__lDr-.
820£
Master
Ceo,
r-
SYI O- 6 OOIWDI
MiS +r-0-V
r--
8206
slave
NSl,
POSo
POS,
CACT
wz
~ STS
A/W
01
!-il
!-t V
NSLo !-
PPO O_6
MIS
r---
I-
': ':EA': ';A: : OA.:. .-_SE_OC_U. J~ II_"':_-~_:__---.;,Ii-_S_:B_:~-'~~
5V
Error
Signals
6. No additional logic Is required for this 32-blt master-slave system. The slave calculates partial parity on
Its half of the data, and the master determines which of the 32 data bits and 7 check bits is In error.
3-214
Electronic O•• lgn • September 30. 1981
Table 3. Syndrome decoding identifies and corrects
all single-bit errors.
o 0
1 0
2 0
30
Syndrome
bits
7
6
5
4
o
0
0
1
0
0
D
0
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0 -1-0--'-----=0:---:-1----=0:---:-1----=0:---:-1-1
1
1
0
0
1
1
Q
0
1
1
1
1
O.
0
0
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
N
CBO CB1 D CB2 D
D 18 CB3 D D O D
1 2 D
CB4 __D __ J;> _.2 ___ IL_L L_JL_!L_.;! _1J;i .,Q__ ~JL1L.rL
_~_,,1_ 0.. _ _.Q.~._i>____.Q_ .J1.l>
19 __ 12 D
D
8
9 D 10 D D 67
o
0
1
1
D .__ ~____ 1~ __Q_J..?_P__ ~.' 21,=~20--_-:Q=-~66D2223-Do 1 0 0
CB6
D
D
25
D
26
49 ~_~_24 0 27 D D 50
o 1 0 1
D
52
55
D
51
D
D 70 28
D D 65 D 53 54 D
0
D
29
31
D
64
D
D 69 68
D D 32 D 33 34 D
o
1
1
o 1 1 1 __ 30 D D 37 D 38 39 D D 35 71 D 36 D D_.-lL
1
0
0
0
CB7 ._~.1> .~. _Q..~_ 44 D
D
40 41 0 42 D D U
1
0
0
1
D
45
4~__ J>____~_~~24_. 72
D D U D 73 U D
1
0
1
0
D
59
75
D
79
D
D 58 60
D D 56 D U 57 D
0
1
1
63
0
D
62
D
U
U D
D
U U D 61 D 0
U
1
0
0
D
U
U
DUD
D U
76
D DUD U U D
1
1
0
1
78
D
DUD
U
U D
D
U U DUD D U
1
1
1110
U
D
DUDUUDDUUDU.QDU
1111
D
U
UDUDDUUDPUDUUD
~..-!l_-.:t_
N ;:: No error
CBX = Error 10 check bit X (correctable)
X = Error In data bit X (correctable)
AO~~
BHE---.(~
0;:: Double-bit error (detected but not corrected)
U;:: un correctable multi-bit error
-_.....
.......
8203 { CAS
Ao------------~--dl·--~
;J~~:~ ~
bus
------------i
8206
co"trol
I
BM,
BHE---+--------------~+_~~__~
System
control
bus
O~018286
:E6' con"ol
I
RO
WR
(b)
7. The 256-kbyte sys,tem (a) has 32 64-kbyte dynamic RAMs lor data plus 12 dynamic RAMs lor error
correction. The dynamic RAMs are controlled by the 8203 dynamic RAM controller while error correction
control is supplied by the 8206. Interlace logic (b) allows the 8203/8206 system to Implement readmC/dl'y-wrlte cycles by gener;lUng Write Enable (Wl~'>to the RAMs, Read/Wrlte(RiwHo the 8206. and bytecontrol signals.
Electronic Oeolgn • September 30. 1981
3-215
Memory Technology: Error-correction, chip
The 8203 itself performs normal reads and writes.
To perform read-modify-writes, simply change the
timing of the WE signal. In Fig. 7b, WE is generated
by the interface logic-the 8203 WE output is not
used. All other dynamic RAM control signals come
from the 8203. A 20-(1 damping resistor reduces the
WE signal ringing. These damping resistors are
included on-chip for all 8203 outputs.
The interface logic generates the R/W input tothe
8206. This signal is high for read cycles and low for
write cycles. During a read-modify-write cycle, Riw
is first high, then low.
The falling edge of R/W tells the 8206 to latch its
syndrome bits internally and generate corrected
check bits to be written to RAM. Corrected data are
already available from the DO pins. No control
signals at all are required to generate corrected data.
Riw is generated by delaying CAS from the 8203 with
TTL-buffered delay line. This delay (tDELAY 1) must
satisfy:
tOEL'Y 1 :2 teA/AM + TDVRL 8206
The 8206 uses multiplexed pins to output the
syndrome word and then the check bits. The R/W
signal may be used to latch the syndrome word
externally for error logging. The 8206 also supplies
two useful error signals: ERROR indicates an error
is present in the data or check bits; CE tells if the
error is correctable (single bit) or uncorrectable
(multiple bits).
After R/W goes low, sufficient time is allowed for
the 8206 to generate corrected check bits, then the
interface logic activates WE to write both corrected
data and check bits into RAM. WE is generated by
delaying CAS from the 8203 with the same delay line
used to generate R/W. This delay, tDELAY 2' must be
long enough to allow the 8206 to generate valid check
bits, but not so long that the spec of the RAM
(tCWL ) is violated. This is expressed by:
Errors in both data and check bits are automatically
corrected, without special 8206 programming.
Since the 8203 terminates CAS to the" RAMs at a
fixed interval after the start of a memory cycle, a
latch is usually needed to maintain data on the bus
until the 8086 completes the read cycle. This is
conveniently done by connecting XACK from the 8203
to the STB input of the 8206, latching the read data
and check bits inside the 8206.
The 8086, like allI6-bit CPUs, is capable of reading
and writing single-byte data to memory. As just
explained, the Hamming code works only on entire
words, so in byte writes, and new byte and old byte
must be merged, and new check bits written for the
Af-A{)~_ _ _ _ _~==I
RAS
/
\~====;:_--.J;-
CAS _ _ _ _
~
WE
DO
01
----------------<
VaI,d
X
Valid
)-----
:x=
8. In all memory cycles, the row and column
addresses are strobed to the RAMs byiiAs and CiS
Sometime after the data out Is valid, the control logic
In Fig. 7b generates Write Enable(WE)to write the data
back into the RAMs.
composite word. This is difficult with most EDC
chips, but it is easy with the 8206.
Further qualifications on 8206 operation
Referring again to Fig. 7b, the 8206 byte-mark
inputs (liMo. tiM,), are generated from AO and BHE.
respectively (off the 8086's address bus) to tell the
8206 which byte is being written. The 8206 performs
error correction on the entire word to be modified,
but 3-states its DO/WDI pins for the byte to be written;
this byte is provided from the data bus by enabling
the corresponding 8286 transceiver. The' 8206 then
generates check bits for the new word.
During a read cycle, BMo and BM, are forced inactive
(i.e., the 8206 outputs both bytes even if 8086 is only
reaaing one). This is done since all cycles are implemented as read-modify-writes, so both bytes of
data (plus check bits) must be present at the RAM
data in pins to be rewritten during the second phase
of the read-modify-write cycle. Only those bytes
actually being read by the 8086 are driven on the
data bus by enabling the corresponding 8286
transceiver.
The 8286's Output Enables (OEBo• OEBd are
qualified by the 8086's RD, WR commands and the
8203's CS command. This serves two purposes: It
prevents data bus contention during read cycles and
it prevents contention between the transceivers and
the 8206 DO pins at th~ beginning of a write cycle.
Thanks to the use of a 68-pin lead less chip carrier,
the 8206 error detection and correction unit is able
to implement an architecture with separate I6-pin
input and output buses. Thus single-bit error correction may be added to a system with a minimum of
control signals or external 10gic.D
3-216
ARTICLE
REPRINT
, AR-197
JANUARY, 1982
Copynghr by Computer DeSI(Jn Publishing Co C J.nuM'Y, 7982
All Rlfhl$ R"stIIWd, Repnnted by Pwrmsswn
3·217
ORDER NUMBER. 210378
~
~.
c~·~==============================~
.:
I
"
....,Al.EPGIT O. . . . .., " "......
BETTER PROCESSOR
PERFORMANCE VIA
GLOBAL MEMORY
. Wait states are eliminated by joining global and local
memories through five TTL components
by Joseph P. Altnether
A
t least 60'70 of today's designs incorporate
microcomputers, which have become o~e of the
most widespread components in a variety pf electronic equipment ranging from video games to navigational flight computers. Microcomputer$ comprise
several elements. One of the more important of these is
the memory. In early systems (and even in some of
today's low performance microcontrollers), the memory
is interfaced and accessed exactly like any ~ther peripheral. Such an architecture is shown in Fig 1. For this
type of application, data store (random access
memory), control store (electrically programmable read
only memory/read only memory), and input/output
reside on a single bus connected directly to the central
processing unit. This kind of application is usually a
dedicated system performing only one function, such as
,control of a vending machine.
Memory consists of control store and data store. The
former occupies most of the memory and contains
about 16k bytes of program; the latter is small and contains less than 4k bytes. A major design goal is simplicity, which can be best achieved when the components
of control store and data store are compatible. It is
much simpler and certainly more efficient to use the
Joseph P. Altnether is technical marketing manager
for memory products at Intel Corp, Aloha, OR
97005. Before that, he worked as an applications
engineer at Intel and a memory system designer for
nuclear/medical instruments at G. D. Searle. Mr
Altnether has a BSEEfrom St Louis University.
JAIUARY 1S'Z
same set of address
decoders and drivers, as
well as data transceivers,
for both control and
data store. This' is
achieved with common
pinout and functionality
between random access
memory (RAM) and electrically 'programmable
read only memory/read
only memory (EPROM/
ROM). Therefore, the
memory, should be an
8-byte wide. RAM. Several
disadvantages are inherent in such a system: the address
space is limited; and because ail elements-including the
central processing unit (CPU)--:reside on a common bus,
the cpu, as the bus controller, suspends processing to
'
control bus operations.
Enhancing the system
The performance of this system can "be enhanced by
upgrading to a microprocessor and storing a variety of
programs in permanent bulk memory. In this kind of
system, control store consists of a RAM containing up to
64k bytes (Fig 2). This memory is much larger because it
serves a dual function: data store and control store.
Programs to be executed are downloaded via a boot
program residing in EPROM. The system overcomes the
memory addressing space deficit of the previous system
but still retains the disadvantage of having all memory
3-2111
COMPUTER DESISI
8
checking and cQrrection, and direct memory access all
become cost effective.
B
~
If_U'
(I'll
.
... because the global memory is so
large, the RAM used must be as dense
as possible to reduce the number oj
components.,
.
FIg 1 Slngle-bus architecture of dedicated nlicrocontroller.
Though inexpensive, this configuration limits available
address space and requires ,that CPU suspend processing
when controlling bus.
PROGRAM
DATA')IORf
PERMANENT
~IORAGE
BOOI
CPU
Fig 2 Improved performance results when microprocessor
using RAM program storage for up to 64k bytes of data and
control information is used. Disadvantages of common bus
architecture are retained, however.
reside on the CPU bus. For example, throughput efficiency could be improved if it were possible to download other portions of the program into control store
while executing out of control store (dual porting).
High performance in both processing power and
speed is realized in distributed processing systems. In
such a configuration, several processors, together with
their local memories, are distributed throughout the
system. These could be structured like ttie systems
previously described; however, they have an important
distinguishing element-multiple local buses with a
common system or global bus. Fig 3 depicts such a
system. Here, the advantag~s of dual porting, error
Residing on the system bus is a global memory to
which every processor has access. This memory can be
very large-even greater than 1M byte. Consequently, it
could be disk, tape, magnetic bubble, or RAM. If built
with RAMs, the type used would be dynamic RAMs
(DRAMs) for several reasons. First, because the global
memory is so large, the RAM used must be as dense as
possible to reduce the number of components. Lower
component count reduces system cost and increases system reliability, which is inversely proportional to the
number of components in the system. Second, the components should consume minimal power. Even a small
amount of power per device multiplied by hundreds of
devices will require a large power supply. In addition, as
the power requirements increase, so do the cooling requirements, which again add to the overall system cost
and operating cost.
Finally, the RAM must be low cost to be competitive
and provide ample operating margins. DRAMs meet
these requirements quite adequately as they provide the
lowest cost per bit and also consume the lowest power
per bit of RAM devices. Unfortunately, designing with
DRAMs has long been considered esoteric and difficult.
In fact, some designers still believe that DRAMs do not
even work: The first of these beliefs was based on fact in
earlier days, but the second is based on an emotional
REQUEST
ACKNOWLEDGE
~
-
~EfRESH
- - - - ' \ '>V'>HM BU\
------v tNONMU1IIl'IIXIlJ)
Fig J Distributed processing system using several
processors with local memories and common (global) bus
provide high performance. Each processor in system 'has
access to large OM-byte) global memory.'
I -'--,.--,--'
Fig 4 Typical DRAM controller. Oscillator provides timing
and control logic for refresh timer.
3-219
DATA -
o TYPE
f-- Q
to design_ In theory, a D type flipflop could be an arbiter (Fig 5). If refresh request is set asynchronously
with respect to the system clock, a decision on the Q
output can be made. If Q is true, the refresh cycle is
granted; if false, the CPU is given access. Timing relationships of data and clock indicate that normal operation of the flipflop will occur if setup and hold times of
data with respect to the clock are met.
If the; setup or hold times are violated, however, the Q
output is no longer a transistor-transistor logic (TTL)
level I or O. The output becomes an analog signal
floating between TTL levels somewhat like a 3-state output device with the output in a high impedance state.
This condition can persist for as, long as 75 ns, during
OUTPUT
LATCH
CLOCK ~
t.:Y:c.-_-.J
OATA
--=:J
ts[) UP
I--
r---------+----~
CLOCK _ _ _ _ _ _---'11-_ tHOLO _ _ _
QUASI STABLE STATE
QOUT~PU~T============Jt====~~~~~~~==
I-- VlOLATI,~G ~~.Oo I
-_
~CAN
tPROP
••
SETUP
f.---tPROP·~~
BE UP TO 75 os FOR A 74S74
The ... DRAM controller... includes an
arbiter which synchronizes the refresh
and memory cycle requests to
eliminate the arbitration problem ....
Fig 5 Timing diagrams for arbiter circnit show that when
certain conditions exist. output is analog signal floating
between TTL levels I and O. During this 75-ns period, no
decisions can be made and refresh failure occurs.
reaction to a memory that forgets unless it is periodically told to remember. DRAMs do not lose data if they
are properly refreshed. This can be easily accomplished
by a memory interface controller.
Designing a DRAM system
Although it is more difficult to design a DRAM system
than a static RAM (SRAM) system, it is not impossible.
Shown in Fig 4 is a typical DRAM controller. At the heart"
of the controller is an oscillator which provides timing
and control logic for the refresh timer. Because DRAMs
are clocked, they need signals like row address strobe
(RAS) , column address strobe (CAS), and write enable
(WE), which come from the control logic. The refresh
timer will periodically time out, typically every 15 ,,"s, to
request a refresh cycle asynchronously with respect to
CPU memory requests. To decide which request (cPu or
refresh) is granted first, an arbiter circuit is required.
The arbiter is the most complicated controller element
which it is impossible to make a decision. At the system
level this appears as a refresh failure. Lastly, the controller requires multiplexers and drivers for the memory
addresses. The total system is built with 20 TTL components (Fig 4).
Another consideration is design time. About four
weeks are usually required for design, two weeks for
worst-case analysis, six weeks for printed circuit board
layout, four weeks for building and debugging, and
another four weeks for redesigning to add features or
correct errors ,. And this does not include a possible second iteration effort. In any case, the task could consume up to six man-months.
A simpler solution
Intel's dynamic RAM controller, the 8203, is contained in
a single 4O-pin package that incorporates the entire
DRAM controller (Fig 6). It includes an arbiter which
synchronizes the refresh and
memory cycle requests to eliminate
the arbitration problem previously
COLUMN
described. Compatible with the
~s
AHaTOAH7~~~
8080A, s08SA, iAPX88, and iAPX86
family of microprocessors, the
MUX
AID TO AL,
device directly addresses half a
megabyte of memory composed of
MUX
ROW
64k RAMs (eg, the Intel 2164). All the
ADDRESS
refresh functions' are provided:
BO
REFRESH
B, 10 DP ,
timer, 8-bit address counter, and
COUNTER
multiplexers for addresses. Because
i'/RROISt
refresh is usually performed asynPeS ~-..rchronously with the CPU cycles, proTIMING
ARBITER
GENERATOR
vision is made for performing synREFRQ/ALE - - - - - chronous refresh if required. At
times the controller will be providing refresh when the CPU requires
access. Consequently, the CPU must
XO/OPz
be placed in a WAIT mode. This is
Xl/eLK
accomplished with a signal from the
8203 called SACK. In addition, the
signal XACK can be used to clock
Fig /I 4O-pin, 8203 DRAM controller includt!$ arbiter that synchronizes refresh and
memory cycle requests eliminating indecisive condition of Fig 5. Chip directly
data into the latches during a read
addresses O.5M byte.
cycle.
-===-~====:1
3-220
mode, a bus controller such as the
Intel 8288 is required. In this case,
MRDe
the iAPX86 outputs status bits 5. to
OWle
52 that are interpreted by the bus
controller. Commands for read and
write are now generated by the bus
controller. Independent of the
mode, the 8203 and memory interface identically to the micro16
processor.
Ease of use or simplicity of design
have been balanced against performance. The simple system shown
(Fig 7) typically operates with one to
two WAIT states required. For the
minimum mode operation, the read
(RD) and write (WR) commands occur too late in the memory cycle to
allow, the DRAM controller to
Fig 7 Typical global memory interface for microprocessor. Multiplexed
generate a ready signal early enough
address/data bus serves as local bus and demultiplexed address/data bus serves as
to avoid WAIT states. Operation
global bus. Minimum or maximum mode operation is possible.
without WAIT states can be accomTo illustrate the ease of interfacing global memories plished by transmitting advance RD or WR commands to
to the microprocessor, an iAPX86 system using an 8086 is. the memory. This is a non-trivial task in the minimum
shown. The mUltiplexed address/data bus is normally mode because. the iAPX86 produces the RD and WR
thought of as the local bus, and the demultiplexed ad- signals in a fixed relationship after address latch enable
dress and data bus as the global bus. In much larger (ALE) occurs. For maximum mode operation, the iAPX86
systems, it would be possible for the local bus, to be outputs status bit information ahead of ALE. With
demultiplexed immediately at the processor and for proper logic circuitry, these status bits can be decoded
another bus that services the entire system to be the and the information used to initiate the advance RD and
global bus. The system described works on either WR commands.
demultiplexed bus. The iAPX86 can be operated in either
With a small amount of additional logic, it is possible
of two modes, minimum or maximum (Fig 7). In the to combine ease of use of the DRAM controller with high
former mode, the microprocessor generates the read performance. As a result, the iAPX86 can operate at 5
and write commands directly, whereas in the latter MHz and requires no WAIT states unless the memory is
r - - - - - - - - - - - - - - - - - - - - - - - - -- - - - - - - - - - - ,
I
:
I
INTERFACE
CONNECTOR
I
Am
I
8086 CLOCK
RESET IN
~=====;;::;;::;=======:;j00
TO 016
Do TD 016
"MUST BE 145151 CRiTICAL FOR PROPER LATCH OPERATION
TCONN{CTTO VCC THROUGH lk PUUUP
CIRCUITRY REQUIRED fOR ZERO WAH STATES
AOOITION~L
Fig 8 To acbleve S-MHz operation with no WAIT states, additional circuitry (dashed lines)
'
must be added.,
3-221
indicated by T1 through T4. To read
without WAIT states, valid data must
"
200ns
I
reach the processor by the end of T3
TClCL~
minus 30 ns. The latest read data
CLOCK
arrival at the processor does indeed
fall within this time frame. The
memory read cycle begins with ADV
ROC (Fig 9), which is latchC(,i by the
LATEST
ALE
falling edge of ALE. ADV RDC
reach~s the 8203 at 160 ns into the
LATEST AOW ROC
A18203
cycle and begins access. Within SO
u.nsr SACK -1---+----'.1
ns, SAC!, is valid and ANDed with
fROM 8203
"--_-+...::SAC::::''PCS to be returned to the 8284A clock
READY INPUT
as READY. As a result, no WAIT
(BUfFERED SACK)
J1
T0 8l" - I - - - I states are required unless the DRAM
controllc;r is performing a refresh
cycle. The system is CAS access
ADvlliiCro WOELAY - 1 - - - 1 - - - - ,
limited, and as such the ADV RDC to
AT 8103
1--,------.;
CAS c\elay is 225 ns. The S5-ns CAS
----::--:-------:-~t~~~~~tt=·OB$TOffm'"fOR2164
mu~ACCISSWITH _
access time (t CAC) must be added to
SLOWEST 2164
this time. Finally, an additional
LATEST READ DAfA -I--------'--l-,v__:_-45.ns delay through the buffers is
ARRIVAtAT808fi -1_ _ _ _ _ _ _ _ _-'1'_.......'"
includ~d for a total delay time of
OATA MUST BE VAliD AT
510 ns. Access required is 3 T times
CPU", 3 relet - TOVeL -j+:-=-=-=-=-=-==-~"~'.~'========~~~~~
(600 ns) minus 30 ns, or 570 ns. The
system indeed requires no WAIT
·CRiTlCAl TIMING fOR ZERO WAIT STATES
states for operation.
In the write cycle, the relationship
Fig 9 Read cycle worst-case analysis. Processor Tstates TJ through T•. are
between data and WE and the relashown. For read without WAIT states, valid data must reach processor 30 ns
tionship of CAS and WE must be
before end of T3.
gUiUanteed. Data are written into
being refresheq. The circuitry added to the system is . the DRAM on the falling edge of WE. Consequently, data
shown inside the dashed lines in Fig S. The 8205 is a must be valid prior to the falling edge of WE. The skew
3:8 line decoder which monitors the status lines, With of data from the processor and WR from the 8203 is such
the proper combination of status lines S., S" and S" an that it is possible for the data to be valid after the falling
advanced RD command (ADV ROC) or an advanced WR edge of WR. In this event, invalid data would be written
command (ADV WRC) will be output on pin I3 or pin 14, intQ the memory as shown in Fig 100a). In addition,
respectively.
DRAMS have a timing constraint, tCWL' whicll is the
The RD or WR command, whichever is true, is latched overlap between CAS and WE. If CAS were early and
by the corresponding 74S14 on the falling edge of ALE MWTC were late, tCWL would be violated as shown in
from the 8288 bus controller. Latch outputs at pins ~ and Fig 1O(b). 80th of these requirements are satisfied by
·9 (ADV WRC and ADV RDC) are entered into the 8203A WR ANDing AMWC with WR.
and RD inputs directly. The two latches are cleared later
on the trailing edge of either the memory read command
(MROC) or memory write command (MWRC) througQ the
WORSH.A~~ fROM 8086 ~
two 14500 gates. System acknowledge (SA<;:K)-used in
BEST CASE CAS/WE fROM ~201
place of (XJ\CK) because it occurs sooner-is ANlJ!:d
IDS
with protected chip select (pcs) and returned to the
11
(mu)
11
lJ
i_____
(a)
Global memory can be easily built
using only DRAMs and the ...
DRAM controller.
Bm CASE CAS fROM 8201
~
WORST·CASE COMMAND fROM 8086 (MWTC)
tCWl
(b)
8284A, which provides a synchronous ready signal to the
iAPX86. The S, status bit (memory operation) is latched
by the 14S151 on the trailing edge of ALE. The 2: I
multiplexer is configured as a high speed flow-through
latch by feeding the output back into the input. Propagation delay time is only 7.5 os. The advanced memory
write command (AMWC) is ANoed with WE to provide
WE to the DRAMs.
Read cycle worst -case analysis (Fig 9) considers the
maximum time delays. The four processor T states are
Fig 10 Required
WE
delay timing
10
!Demory
Fig II depicts the worst-case timing analysis fOf a
write cycl~, which is similar to that for the read cycle
with a few exceptions. The ADV WRC is latched on the
falling edge of ALE. The earliest that CAS can occur is
105 ns after ADV WRC starts the write cycle. Valid da~a
are output fro!Jl the CPU within 210 ns a!ld reach the
memory 35 ns later. By ANDing the AMWC with WR from
3-222
II
"
13
SOS6CtOCl\
EARlIES'AOVWRC
AtS203
80ns
SACK fROM 8203
READY INPUT
(BUfFEREOSACKj
Ar8m
ROY SETUP
AT 8284 ",60ns
min
TRIVCl
the 8203, WE falls a minimum of 8 ns
after data are stable and valid at the
memory. In addition, this ANDing
guarantees a minimum tCWL' of
100 ns.
Overall system performance is improved by using global as well as
local memories. Global memory can
be easily built using only dynamic
RAMs and the 8203 dynamic RAM
controller. Performance, together
with ease of use, is achieved by adding just five TTL components. The
design of a 5-MHz system that runs
without WAIT states is a good example of this approach.
Acknowledgment
EARLIEST ffi FROM
AOV WiC DELAY
The author would like to thank Bill
Righter and David Chamberlin for
their help in preparing this article.
LAT[ST VAllO OA'A
fROM CPU
LAT£SrVAtIOOATA
ARRIVAt AT 2164
EARlIESTWij
fROM 8203
mm = 45 ns
} ORedTOGHWii
fOR 2164
EARUESTCLOCKEOAMWC
AT 14S32 otf MEMORY CARD
8086 IN ma~ MODE AT S MHl
, 8082 AT 25MH,CtOCK
oj-
High 713
PRO~A~~~~ C~or~l~l~
·CRITICAL TIMING FOR ZERO WAIT SlAns
Fig 11
Worst~ase
Please rate the value Of this article
to you by circling the appropriate
number in the "Editoriql Score
Box" on the Inquiry Card.
timing analysis for write cycle
3-223
Average 714
Low 715
2114A
1()24 X 4 BIT STATIC RAM
I
2114AL·1
2114AL·2
2114AL·3
2114AL·4
2114A·4
2114A·5
100
120
150
200
200
250
40
40
40
40
70
70
Max. Access Time (ns)
I
Max. Current (n1A)
Technology
• HMOS
Low
Power,
High Speed
•
• Identical Cycle and Access Times
• Single +5V Supply ±10%
Directly TTL Compatible: All Inputs
• and
Outputs
Common Data Input and Output Using
• Three-State
Outputs
• High Density 18 Pin Package
•
•
Completely Static Memory - No Clock
or Timing Strobe Required
Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
The Intele 2114A is a 4096-bit static Random Access Memory organized as 1024 words by 4-bits using HMOS, a high performance MOS technology. It uses fully DC stable (static) circuitry throughout, in both the array and the decoding, therefore it
requires no clocks or refreshing to operate. Data access is particularly simple since address setup times are not required. The
data is read out nondestructively and has the same polarity as the input data. Common input/output pins are provided.
The 2114A is designed for memory applications where the high performance and high reliability of HMOS, low cost, large bit
storage, and simple interfacing are important design objectives. The 2114A is placed in an 18-pin package for the highest
possible density.
It is directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate Chip Select (CS) lead allows
eesy salection of an individual package when outputs are or-tied.
PIN CONFIGURATION
..
As
A.
A,
Vee
....
A,
BLOCK DIAGRAM
LOGIC SYMBOL
Ao
A,
110,
A.
A,
IIOz
A.
Ao
Ito,
A,
IIOz
A.
Az
IIOz
A,
110.
A.
Wl
Ao
A, 0
A ®
•0
A.
... (i)@
~vcc
.i!LGNO
ROW
SELECT
MEMORY ARRAY
64 ROWS
64 COLUMNS
A,
A, @
As
110,
110.
WE
PIN NAMES
ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
~
110,-110. DATA INPUT/OUTPUT
Act-A.
WI
o.
V"" POWER I+5VI
GNDGROUND
PIN NUMBERS
INT£L COflPllRA TlON ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBOOIED IN AN INTEL PRODUCT NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED
.,NTEL CORPORATION. 19n. 1979
DECEMBER 1979
3-224
2114A FAMILY
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias .................. -10·C to 80·C
Storage Temperature .....•.............. -65·C to 150·C
Voltage on any Pin
With Respect to Ground .................. -3.5V to +7V
Power Dissipation •. . . . . . . . . . . . . . • . . . . . . . . . . . . . . . .. 1.0W
D.C. Output Current .....••..•...................... 5mA
·COMMENT: Stresses above those listed under "'AbSolute
Maximum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of/he device
at these or any other conditions above those indicatlld in the
operational sections of this specification is not implied. Ex·
posure is not implied. Exposure to abSolute maximum rating
conditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS
TA = O·C to 70·C. Vee = 5V ± 10%. unless otherwise noted.
SYMBOL
PARAMETER
2114AL·1/L·2/L·3/L·4
Min. Typ.111 Max.
2114A·4/·5
Min.
Typ.111
Max.
UNIT
CONDITIONS
~
a to 5.5V
liLt!
I nput Load Current
(All Input Pins)
.01
1
1
/1 A
VIN
IlLOI
1/0 Leakage Current
.1
10
10
Il A
CS = V,"
Vila = 0 to 5.5
Icc
Power Supply Current
25
40
70
mA
Vee ~ max, 1110 ~ 0 mAo
T A = O°C
VIL
Input Low Voltage
0.8
V
-3.0
VIH
Input High Voltage
2.0
10L
Output Low Current
4.0
9.0
10H
Output High Current
-2.0
·2.5
105 121
Output Short Circuit
Current
50
0.8
-3.0
6.0
2.0
6.0
4.0
9.0
-2.0
-2.5
40
40
V
mA
VOL = O.4V
mA
VOH = 2.4V
mA
VouT=GND
NOTE: 1 TYPIcal values are for TA =25°C and Vee::: 5 OV
2 Duration not to exceed 1 second.
LOAD FOR
TOTO
CAPACITANCE
AND
TOTW
+5V
TA = 25·C, f = 1.0 MHz
SYMBOL
CliO
1.8K
TEST
Input/Output CapacItance
MAX
5
UNIT
pF
CONDITIONS
Vila
= OV
Doul
100pF
1K
CIN
NOTE:
Input Capacitance
5
pF
VIN
=OV
ThIS parameter i. paroodlcally sampled and not 100% tested.
-=
Figure 1.
+5V
1.8K
A.C. CONDITIONS OF TEST
Input Pulse Levels .•................................................. 0.8 Volt to 2.0 Volt
Input Rise and Fall rimes ...................................................... 10 nsec
DOUT
5pF
lK
Input and Output Timing Levels ...................................... 0.8 Volts to 2 a Volts.
Output Load ............................................... 1 TTL Gate and C L = 100 pF
3·225
Figure 2.
-=
2114A FAMILY
A.C. CHARACTERISTICS
READ CYCLE
TA = O°C to 70°C, Vee = 5V :!: 10%, unless otherwise noted.
[1)
2114AL·l
Min.
PARAMETER
SYMBOL
100
Read Cycle Time
tRe
Max.
tA
Access Time
teo
Chip Selection to Output Valid
70
Chip Selection to Output Active
tOTO(3)
Output 3-state from DeselecllOn
tOHA
Output Hold from
Address Change
Min.
10
15
Min.
Max.
Min.
Max.
120
150
70
·'70
UNIT
250
ns
85
ns
70
40
ns
50
ns
60
ns
15
15
15
ns
10
10
35
Max.
200
:
10
15
Min.
250
200
,150
10
30
2114A-4/L-4 2114A·5
2114AL-3
Max.
120
100
tcX{3}
2114AL-2
WRITE CYCLE [2)
2114AL-1
Min.
PARAMETER
SYMBOL
2114AL-2
Max.
Min.
Min:
twe
Write Cycle Time
100
120
150
tw
Write Time
75
75
tWR
Write Release Time
0
0
loTW(3)·
Output 3-state from Write
tow
Data to Write Time Overlap
70
70
90
tOH
Data Hold from Write Time
0
0
0
30
2114A.4/L-4 2114A·5
2114AL-3
Mu.
Max.
Min.
Max.
Min.
Max.
UNIT
200
250
ns
90
120
135
ns
0
0
0
35
40
,
ns
50
60
ns
120
135
ns
0
0
ns
NOTES:
1. A Read occurs during the overlap of a low CS and a high WE
2. A Write occurs during the overlap of a low Cs and a low WE tw is measured from the latter of CS or WE gOing low to the earlier of CS or WE gOing high.
3. Measured at ± 500 mV with 1 TTL Gate and C L =500 pF
WAVEFORMS
READ CYCLE@
WRITE CYCLE
T
I--------'oe-------I
1-----'.------1
ADDRESS
'we
-
-.II\.-----------I-...JI'---
ADDRESS
1--";'0-
,\\' l\\'\
UI I IIII IIII II,
'w
®' ~
_ t OT
NOTES:
I.
=1
Dour
I'~
3 ~ high lor a Read Cycle
4 If the CS low tranSition occurs Simultaneously with the WE low
transition. the output buffers remain '" a high Impedance state
5. ~ must be high dUring all address tranSitions
0,.
3-226
II
I
tOH
2114A FAMILY
TYPICAL D.C. AND A.C. CHARACTERISTICS
NORMALIZED ACCESS TIME VS.
AMBIENT TEMPERATURE
NORMALIZED ACCESS TIME VS.
SUPPLY VOLTAGE
12
11
1
10
0
$
•
o
o•
~
08
2
07
~
7
---
~
--
06
6
o5
05
450
475
525
500
o
550
20
40
60
80
, VCC(V)
NORMALIZED POWER SUPPLY CURRENT
VS. AMBIENT TEMPERATURE
NORMAUZED ACCESS TIME VS.
OUTPUT LOAD CAPACITANCE
2
14
,/'
13
1
/'
'12
/
1
13
/'
10
,
09
I
/
------ '----
---
08
:--
07
08
06
07
05
100
150
200
250
300
350
o
20
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE
0
60
30
60
20
0
~
10
~
60
40
o
~
o
o
0
//
/
/
1
VOL
3-227
/
(V)
80
inter
2115A, 2125A FAMILY
HIGH SPEED 1K X 1 BIT STATIC RAM
2115AL,2125AL
2115A,2125A
2115AL·2,2125AL·2
2115A·2, 2125A·2
Max. TAA (n5)
45
45
70
70
Max. Icc (mA)
75
125
75
125
• Pin Compatible To 93415A
(2115A) And 93425A (2125A)
• Fan-Out Of 10 TTL (2115A Family)
-- 16mA Output Sink Current
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
• Uncommitted Collector (2115A)
And Three-State (2125A) Output
• Low Operating Power Dissipation
--Max.0.39mW/Bit (2115AL, 2125AL) • Standard 16-Pin Dual In-Line
Package
• TTL Inputs And Outputs
The Intel® 2115A and 2125A families are high-speed, 1024 words by 1 bit random access memories_ Both open collector
(2115A) and three-state output (2125A) are available_ The 2115A and 2125A use fully DC stable (static) circuitry throughout - in both the array and the decoding and, therefore, require no clocks or refreshing to operate. The data is read out nondestructively and has the same polarity as the input data_
The 2115AL/2125AL at 45 ns maximum access time and the 2115AL-2/2125AL-2 at 70 ns maximum access time are fully
compatible with the industry-produced 1 K bipolar RAMs, yet offer a 50% reduction in power of their bipolar equivalents.
The power dissipation of the 2115AL/2125AL and 2115AL-2/2125AL-2 is 394 mW maximum as compared to 814 mW
maximum of their bipolar equivalents. For systems already designed for 1 K bipolar RAMs, the 2115A/2125A and the
2115A-2/2125A-2 at 45 ns and 70 ns maximum access times, respectively, offer complete compatibility with a 20% reduction
in maximum power dissipation.
The devices are directly TTL compatible in all respects: inputs, outputs, and a single +5V supply. A separate select (CS) lead
allows easy selection of an individual package when outputs are OR-tied.
The 2115A and 2125A families are fabricated with Intel's N-channel MOS Silicon Gate Technology.
PIN CONFIGURATION
LOGIC SYMBOL
cs
cs
vee
Ao
D,.
A,
WE
A,
A,
Ao
-
..
A.
A.
A,
12
13
PIN 16
PIN 8
WRITE
DRIVERS
I AorOAs
CHIPSElECT
ADDRESS INPUTS
["'.
DATA INPUT
DATA OUTPUT
m
,,"UT
WRITE ENABLE
CONTROL
LOCIC
(SEE TRUTH
,-
TASLEI
-
1
ADDRESS
DECODER
Dour
III t t
PIN NAMES
•
11
A,
Vee '"
:-------
SENSE AMPS
AND
I.
"
GNO"
32)(32
ARRAY
1 j
A,
A.
GNO
WORD
DRIVER
"
..
Dour
I.
A,
A,
A.
~N WE
15
..
A,
BLOCK DIAGRAM
ADDRESS
DECODER
I 1111
AO Al A) AJ A4
A~ A(, A] As Ag
CS
WE
-
DIN
(0)0®®
®@l@@@
Ii'
@
@
TRUTH TABLE
INPUTS
CS WE DiN
H
X
X
L
L
L
L
L
H
L
H
X
OUTPUT
OUTPUT
2115A FAMILY 2125A FAMILY
""U,
,,"VT
MODE
,,"UT
HIGH Z
HIGH Z
HIGH Z
NOT SELECTED
WRITE "0"
WRITE "1"
,,"u,
READ
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBOOIED IN AN INTEL PRODUCT NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED
.INTELCORPORATION. 1977. 1979
3.228
NOVEMBER. 1979
2115A, 2125A FAMILY
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . . . . . . . . . . . . . -10°C to +85°C
Storage Temperature . . . . . . . . . . . . . . -65°C to +150°C
All Output or Supply Voltages . . . . . . . . . . -0.5V to +7V
All Input Voltages . . . . . . . . . . . . . . . . . -0.5V to +5.5V
D.C. Output Current . . . . . . . . . . . . . . . . . . . . . 20 mA
*COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
at any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
D.C. CHARACTERISTlCS[1,21
Vcc; 5V ±5%, T A; O°C to 75°C
Symbol
Test
VOL1
2115A Family Output Low Voltage
Min.
Typ.
VOL2
2125A Family Output Low Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
IlL
I nput Low Current
-0.1
IIH
Input High Current
IlcEXI
2115A Family Output Leakage Current
ilOFFI
2125A Family Output Current (High Z)
IOS[31
2125A Family Current Short Circuit
to Ground
VOH
Family Output High Voltage
Icc
Power Supply Current:
ICC1: 2115AL, 2115AL·2, 2125AL,
2125AL·2
Max,
Unit
0.45
V
IOL; 16 mA
0.45
V
IOL; 7 mA
2.1
V
0.8
V
-40
JlA
Vcc
= Max., VIN; O.4V
0.1
40
JlA
Vcc
= Max., VIN,; 4.5V
0.1
100
JlA
Vcc
= Max., VOUT = 4.5V
0.1
50
JlA
Vcc
= Max.,
mA
Vcc
= Max.
V
IOH
= -3.2 mA
-100
2.4
I CC2 : 2115A, 2115A·2, 2125A, 2125A·2
Conditions
60
75
mA
100
125
mA
V OUT = 0.5V/2.4V
All Inputs Grounded, Output
Open,
NOTES:
1. The operating ambient temperature ranges are guaranteed With transverse air flow exceeding 400 Imear feet per mmute and a two minute
warm-up Typical thermal resistance values of the package at maximum temperature are:
eJA
{@ 400 fpM air flowl = 45" C/W
{st,11 airl = 60" C/W
eJC = 2S"C/W
2. TYPical Itmits are at Vee = 5V ITA = +25 0 C, and maximum loading.
eJA
3. Duration of short circuit current should not exceed 1 second.
3-229
2115A, 2125A FAMILY
2115A FAMILY A.C. CHARACTERISTlCS[1,2] vee = 5V ±5%, TA = o°C to 75°C
READ CYCLE
Symbol
2115A Limits 2115AL·2 Limits 2115A·2 Limits
2115AL Limits
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
tACS
Chip Select Time
15
30
15
30
15
30
15
40
ns
tACS
Chip Select r.ecovery Time
10
30
10
30
10
30
10
40
ns
tAA
Address Access Time
30
45
30
45
40
70
40
70
ns
tOH
PrevIous Read Data Valid After
Change of Address
5
5
10
5
10
5
10
ns
10
WRITE CYCLE
Symbol
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
tws
Write Enable Time
tWR
Write Recovery Time
tw
Write Pulse Width
tWSD
10
10
25
25
0
10
30
30
0
10
25
25
0
40
45
0
ns
30
20
30
10
30
15
50
15
Data Set·Up Time Prior to Write
0
-5
5
-5
0
-5
5
-5
ns
tWHD
Data Hold Time After Write
5
0
5
0
5
0
5
0
ns
tWSA
Address
tWHA
Address Hold Time
Set·U~
Tlm@
I
ns
5
0
5
0
5
0
15
0
ns
5
0
5
0
5
0
5
0
ns
twses
Chip Select Set·Up Time
5
0
5
0
5
0
5
0
ns
tWHCS
Chip Select Hold Time
5
0
5
0
5
0
5
0
ns
A.C. TEST CONDITIONS
ALL INPUT PULSES
3TP _:I'_:_,...-------.\:
--.- _ ---__ ---_: ~I\,;_;;';T· .
4SV
90%
-;...-':..::;"":::...._ _
"r;ND
-=- __:
_~
:.--10n$
:_____ 10n$
30pF
(INCLUDING
SCOPE AND
JIG)
READ CYCLE
AOA9 _ _ _
WRITE CYCLE
J~~___________________________
l - tAA
-
r--
~
l-
--jt-
-
~[-
---'.'l_ t w ___
DATA VALID
WE
PROPAGATION DELAY FROM CHIP SELECT
~'C.--..:J 'tWSD
I---
I---
_tWHA,_
_tWSA_
-'w~'--f- 'w,
DATA
UNDEFINED
(ALL ABOVE MEASUREMENTS REFERENCED TO 1 5V)
3-230
'WHO
J
~t~~HCS-
~
2115A,2125A FAMILY
2125 FAMILY A.C. CHARACTERISTICS[1.2)
Vee = 5V ±5%. TA = O°C to 75°C
READ CYCLE
Symbol
2125AL Limits
2125A Limits 2125AL·2 Limits 2125A·2 Limits
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
tAcs
Chip Select Time
15
30
15
30
15
30
15
40
ns
tZRCS
Chip Select to HIGH Z
10
30
10
30
10
30
10
40
ns
tAA
Add ress Access Ti me
30
45
30
45
40
70
40
70
ns
tOH
PrevIous Read Data Valid After
Change of Address
5
5
5
10
10
5
10
10
ns
WRITE CYCLE
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Units
Test
Symbol
tzws
Write Enable to HIGH Z
tWR
Write Recovery Time
tw
Write Pulse Width
tWSD
10
25
10
30
10
0
25
0
30
25
10
25
0
0
40
ns
45
ns
30
20
30
10
30
10
50
15
ns
Data Set·Up Time Prior to Write
0
-5
5
-5
0
-5
5
-5
ns
tWHD
Data Hold Time After Write
5
0
5
0
5
0
5
0
ns
tWSA
Address Set·Up Time
5
0
5
0
5
0
15
0
ns
tWHA
Address Hold Time
5
0
5
0
5
0
ns
Chip Select Set·Up Time
5
0
5
0
0
0
ns
tWHes
Chip Select Hold Time
5
0
5
0
5
5
5
5
0
twses
0
5
0
ns
T.1'-.
A.C. TEST CONDITIONS
ALL INPUT PULSES
45V
~-------.-.-.-,.\"'.;..._~;,;,O%; ;",
Joon
GND -::-
M2115A
600n
-.;
:. -10ns
"oUT--.---....
__
~ __ -10ns
== SCOPE
~~lUDING
AND
JIG)
READ CYCLE
A.A,
WRITE CYCLE
~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
es
-----..
r-
"-
~
Au A,!
l - tAA - - l-
D"
DATA VALID
'w~
.-
WE
PROPAGATION DELAY FROM CHIP SELECT
1W<;O
t"5V
,~
-
~-
_IW'iA ___
I+---~-t-AC-S:'---~-------------
,-.
tWR
IALl ABOVE MEASUREMENTS REFERENC[D TO 15Vl
3·231
.c
.-.-lWHA---"
: . . - - "+- tWHCS - -_____
- 'wscs
DOUT
'WHD
~IGH ~
:
2115A,2125A FAMILY
2125A FAMILY WRITE ENABL.E TO HIGH Z DELAY
5V
WRIT"NA.~ ~
750U
Dour
2125A
5pF
DATA OUTPUT
r--~;H-;
tzws
"0"LEVEL
--"";"==---'lI---''-} 05V
DoUT _ _ _
··';..
...;;L';;.;V.;;'.;;.L_ _~
}
05V
,-__ .!!I~!.
DATA QUTPUT
LOAD'
2125A FAMILY PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z
co
CHIP SELECT
---II
DOUT
r--~I;'-;
-,!_}
0 5V
--"';''':;;''':;;'---.l-}
05V
DATA OUTPUT _ _ _"_O"_L_'V_'_L_ _
"1" LEVEL
DoUT
~ _ _ ~~~
DATA OUTPUT
(ALL tzxxx PARAMETERS ARE MEASUREO AT A DELTA
OF 0 5V FROM THE lOGIC LEVel AND USING LOAD 1 I
2115A/2125A FAMILYCAPACITAI)ICE* Vcc=5V, f= 1 MHz,
SYMBOL
2115A Family
LIMITS
TEST
TYP.
TA = 25°C
2125A Family
LIMITS
MAX.
TYP.
TEST CONDITIONS
UNITS
MAX.
CI
Input Capacitance
3
5
3
5
pF
All Inputs = OV, Output Open
Co
Output Capacitance
5
8
5
8
pF
CS = 5V, All Other Inputs = OV,
Output Open
·This parameter is peroodically sampled
~nd
is not 100% tested.
TYPICAL CHARACTERISTICS
Icc VS. VCC
ICC VS. TEMPERATURE
110
'00
go
i
-
110
2,1'5A.J11.,..k
r--!'25A. 2'2$A·2 -
I--
eo
..
V2115A.2116A.2
- 2125A, 2125A·2
90
1 eo
.li 7.
.
~
'00
1--1---
so
60
ACCESS TIME VS. TEMPERATURE
70
-
I--
•o
W
.li
211SAL.2115AL·2
~
~
20
..t
~
..
TEMPERATURE
re)
eo
m
eo
!
~
70
.
.
o
L
40
30
20
V2116AL.2116AL.2
2126AL. 2126AL·2
I
TA .. 2S"C
o
VccfV)
3-232
2~ 16AL'~' 21'!A.2
--- --~ -
2126AL-2. 2125A 2
,
~
211SAL,2116A
2125AL.2125A
!"-"
i--"
I--
1 1 1
'0
o
...... f-"
.-
o
W
20
~
~
..
TEMPERATURE (OC)
eo
vcc"sv
m ~
inter
2115H, 2125H FAMILY
HIGH SPEED 1K X 1 BIT STATIC RAM
2115H·2,2125H·2
2115H·3,2125H·3
2115H·4,2125H·4
Max. TAA (n5)
20
25
30
35
Max. Icc (mA)
150
125
100
125
2125H·1
I
I
n Technology
• HMOS
Compatible to 93415A (2115H) and
• Pin
93425A (2125H)
Output Sink Current
• 16mA
Low Operating Power Dissipation • .Max.
0.53 mW/Bit (2115H-3, 2125H-3)
Inputs and Outputs
• TTL
• Single +5V Supply
Collector (2115H) and
• Uncommitted
Three-State (2125H) Output
in EXPRESS
• -Available
Standard Temperature Range
-
• Standard 16-Pin Dual In-Line Package
Extended Temperature Range
The .ntel® 2115H and 2125H families are high speed, 1024 words by 1-blt random access memories fabricated with
HMOSII, Intel's advanced N-channel MOS silicon gate technology Both open collector (2115H) and three-state output
(2125H) are available The 2115H and 2125H use fully DC stable (static) circuitry throughout - in both the array and the
decoding and, therefore, require no clocks or refreshing to operate The data is read out non-destructively and has the
'
same polarity as the input data.
HMOS II's advanced technology allows the production of the industry's fastest, low power, 1K static RAMs - offering
access times as low as 20ns
HMOS II allows the production of the 2115H/2125H families, fully compatible with the 1K Bipolar RAMs yet offering
substantial reductions In power dissipation The power diSSipations of 525mW maximum and 656mW maximum
compared to 814mW maximum offer reductions of 19% and 36% respectively,
The devices are directly TTL compatible in all respects Inputs, outputs, and a single +5V supply A separate select (CS)
lead allows easy selection of an individual package when outputs are OR-tied
PIN CONFIGURATION
Os
co
Vee
Ao
0,.
A,
WE
.,
,
Ao
A,
DOUT
A.
GND
As
WE
WORD
DRIVER
r-
A,
'"
GND '"
WRITE
A.
A,
DRIVERS
'0
A,
"
A,
13
1-
-
1
'2
ADDRESS
DECOOER
PIN 16
ADDRESS
DECODER
°OUT
~ A, Al A3 A4
A~ A6 A, As A"
I t 111
-
CS
WE
000®®
0@@@@
~
@ @
-
D'N
TRUTH TABLE
PIN NAMES
"'.
""r
CONTROL
lOGIC
(SEE TRUTH
TABLEI
AND
AS
PIN 8
r----
SENSE AMP'>
t t II t
"TO"
W£
x 32
1 I
.
Vee
32
ARRAY
2
A,
.
A.
0'111
,. ,.
A,
A,
A,
BLOCK DIAGRAM
LOGIC SYMBOL
INPUTS
CHIP5ELECT
ADDRESS INPUTS
WRITE ENABLE
C5 WE 0.,.
H
L
L
L
DATA INPUT
DATA OUTPUT
3·233
X
L
L
H
X
L
H
X
OUTPUT
OUTPUT
2115H FAMILY 212SH FAMJlY
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
""ur
MODE
""ur
""UT
HIGH Z
""ur
NOT SELECTED
WRITE "0"
WRITE "1"
READ
2115H/2125H FAMILY
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias . • . . . . . . . . . . . _10°C to +85°C
Storage Temperature . . . . . . . . . . . . . . _65°C to +150°C
*COMMENT: Stresses above those listed under "Absolute Maximum Ratmgs" may cause permanent damage to the device, This is a
stress rating only and functional operation of the device at these or
at any other conditions above those indicated In the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.
All Output or Supply Voltages . . . . . . . . . . -O.SV to +7V
All Input Voltages. . . . . . . . . . . . . . . .. -1.5V to + 7V
D.C. Output Current . . . . . . . . . . . . . . . . . . . . . 20 mA
D.C. CHARACTERISTICS [1,21
Symbol
Min.
Test
VOL
2115H/25H Family Output Low Voltage
V,H
Input High Voltage
V,L
Input Low Voltage
Typ.
Max.
Unit
0.45
V
0.8
V
Conditions
10L
= 16 mA
V
21
I,L
Input Low Current
-0.1
-40
/iA
Vee
= Max., V,N = O.4V
I'H
Input High Current
01
40
/i A
Vee
= Max., V,N = 4.5V
IlcExl
2115H Family Output Leakage Current
0.1
100
/iA
Vee
= Max., VOUT = 4.5V
Ii0FFI
2125H Family Output Current (High Z)
0.1
50
/iA
Vee
= Max., VOUT = 0.5V/2.4V
los
2125H Family Current Short Circuit
to Ground
125
200
mA
Vee
= Max
VOH
Family Output High Voltage
V
10H
= -5.2
24
mA
Power Supply Current.
Icc,: 2125H-l
Icc
80
150
mA
2115H-2/2125H-2
2115H-4/2125H-4
80
125
mA
le03: 2115H-3/2125H-3
80
100
mA
ICC2:
,.,-
NOTES:
-
.
-
•.
All Inputs Grounded, Output
Open
-
1 The operating ambient temperature ranges are guaranteed with transverse aIr flow exceeding 400 Imear feet per minute
2 TYPlcalltmlts are at Vee = 5V, TA = +25°C, and maxImum loading
3-234
2115H/2125H FAMILY
2115H FAMILY A.C. CHARACTERISTICS
Vee = 5V ±5%. T A = O°C to 75°C
READ CYCLE
Symbol
2115H-3 Limits
Min.
Max.
2115H·2 Limits
Min.
Max.
Test
2115H-4 Limits
Min.
Max.
Unlll
t.cs
Chip Select Time
15
20
20
ns
tACS [1]
Chip Select Recovery Time
20
20
20
ns
tM
Address Access Time
25
30
35
ns
toH
PrevIous Read Data Valid After
Change of Add ress
[1]
0
0
0
ns
WRITE CYCLE
Symbol
Test
Min.
Max.
Min.
Max.
15
Min.
Max.
Units
20
ns
20
ns
tws [1]
Write Enable Time
tWA
Write Recovery Time
0
tw
Write Pulse Width
20
20
25
ns
!wso
Data Set-Up Time Prior to Write
0
0
0
ns
!wHO
Data Hold Time After Write
0
0
0
ns
tWSA
Address Set-Up Time
5
5
5
ns
20
15
0
20
0
!wHA
Address Hold Time
0
0
0
ns
twoes
Chip Select Set-Up Time
5
5
5
ns
tWHCS
Chip Select Hold Time
0
5
5
ns
[1] These specifications are guaranteed by design and not production tested.
A.C. TEST CONDITIONS
ALL INPUT PULSES
Vee
""r -1,--- - -
Vee
3001~
3OV±P-~
t
I
GND "::"
_n
90%
--"',O%"'--_ __
300!!
2115H
1\
_1-+ ____________:_\!'-__
i
l
I
I
I
1
_:
--! :--
: _ 5ns
5ns
DoUT---;,.---4
lOp"
,
(INCLUDING
. SCOPE AND
60Ql!
5pF
~--------------J.
3~ ~-4\--
' - - - 4 JIGI
.--,.-
LOAD FOR ~CS' tws
READ CYCLE
~
1
GNO -:;: - :
-=-
I
i-
90%
I
~
5ns
I
: - 5ns
WRITE CYCLE
~A' ____~~~_________________________
...
AO Ag
1 _ IAA -
'-
l-
-Jl-
~t-
-JDouT
--'0%
--- -- ____ ~-I-~ -_
DATA VALID
...-tw-+
WE
PROPAGATION DELAY FROM CHIP SELECT
~~
IWSO~
r-
twSA
~ iwscs - DouT
DATA
UNDeFINED...
tAll ABOVE MEASUREMENTS REFERENC[D TO 1 5Vl
3-235
:-1
+-tWHA
--
-rI
.
'ws
~~WHCS_
'w.
~
2115H/2125H FAMILY
2125H FAMILY A.C. CHARACTERISTICS
READ CYCLE
Symbol
2125H-1 Limits
2125H-2 Limits
2125H-3 Limits
2125H-4 limits
Max. Min.
Max. Min.
Max. Units
Min.
Max. Min.
Test
Chip Select Time
tAA
Address Access Time
tOH
PrevIous Read Data Valid After
Change of Address
[1)
15
20
25
15
20
20
tAcs
t ZRCS [1J
Chip Select to HIGH Z
0
20
20
35
20
20
30
0
0
0
ns
ns
ns
ns
WRITE CYCLE
Symbol
Test
Min.
tzws '[1J
Write Enable to HIGH Z
tWR
Write Recovery Time
tw
Write Pulse Width
twso
Data Set·Up Time Prior to Write
tWHO
Data Hold Time After Write
tWSA
Address Set·Up Time
tWHA [1J
Address Hold Time
twscs
Chip Select Set·Up Time
tWHCS
Chip Select Hold Time
[1 J These
0
15
0
0
5
0
5
0
..
Max. Min.
15
15
Max. Min.
15
15
0
Max. Min.
20
20
0
20
0
0
5
0
5
0
Max. Units
20
20
0
25
0
0
5
20
0
0
5
0
5
5
ns
ns
ns
ns
ns
ns
0
ns
5
5
ns
ns
specifications are guaranteed by design and not production tested.
A.C. TEST CONDITIONS
ALL INPUT PULSES
e-r---- ------ -------- ----
Vee
-4"';;~,
510.\1
GND
2125H
Dour -~r----~
300C!
-=-
I
I
-1
I
90%
I
-1- -----------l- ~,
..,;_..,;_..,;'.;;0%,,-_ _
r
I
I
I
,---- 5ns
---t
I
I
\ - 5ns
30pF
(INCLUDING
SCOPE AND
JIG)
READ CYCLE
WRITE CYCLE
~A. ______J~~__________________________
cs
----
~
l<-
-
E-
!______ t AA
-i!Dour
-J!-
DATA VALID
--'1"1---~ r
WE
PROPAGATION DELAY FROM CHIP SELECT
'WSD
~
~
-'WSA_ '
-'wscs_
----'WHA_
>/;,Hlo'H
tWR
i~;;
(ALL ABOVE MEASUREMENTS REFERENCED TO 1 5V)
3-236
'WHO
IWHCS_
2115H/2125H FAMILY
2125H FAMILY WRITE ENABLE TO HIGH Z DELAY
5V
WE
WAITE ENABLE
SlOD
DOUT
~
r---;';OH-;
-lI=} 05V
tzws
2125H
OOUT
DATA OUTPUT _ _'..;,'0'..,;'L;;;E.;.;VE;;;L_ _
5.'
"1" lEVEL
DOUT
DATA OUTPUT
-:::-
} 05V
,-__ .!!I~':'
LOAD 1
2125H FAMILY PROPAGATION DELAY FROM CHIP SELECT TO HIGH Z
os
CHIP SELECT
DOUT
t ZRCS
DATA OUTPUT _ _ _
"0_"_LE_V_EL_ _
r--~1~7
--'l_}
OSV
"1" lEVEL
DOUT
DATA OUTPUT
(ALL
tzxxx PARAMETERS ARE MEASURED AT A DELTA
OF 0 5V FROM THE LOGIC LEVEl AND USING LOAD 1 I
2115H/2125H FAMILY CAPACITANCE*
Vcc=5V, f= 1 MHz, TA = 25°C
2115H Family
SYMBOL
2125H Family
LIMITS
TEST
TYP.
LIMITS
MAX.
TYP.
UNITS
TEST CONDITIONS
MAX.
C,
Input Capacitance
3
5
3
5
pF
All Inputs = 0\1, Output Open
Co
Output Capacitance
5
8
5
8
pF
CS = 5V, All Other Inputs = OV,
Output Open
*Thls parameter IS periodically sampled and IS not 100% tested.
3·237
2118 FAMILY
16,384 x 1 BIT DYNAMIC RAM
2118-3
100
235
285
Maximum Access Time (ns)
Read, Write cycle (ns)
Read-Modlfy-Wrlte Cyele (ns)
• Single +5V Supply, ±10% Tolerance
• HMOS Technology
• Low Power: 150 mW Max. Operating
11 mW Max. Standby
• Available in EXPRESS
- Standard Temperature Range
- Extended Temperature Range
2118-4
120
270
320
2118-7
150
320
410
• CAS Controlled Output Is
Three-State, TTL Compatible
• RAS Only Refresh
• 128 Refresh Cycles Required
Every 2ms
• Page Mode and Hidden
Refresh Capability
• Allows Negative Overshoot
VIL min = -2V
The Intel@ 2118 is a 16,384 word by 1-bit Dynamic MOS RAM designed to operate from a single +-SV power supply. The
2118 is fabricated using HMOS - a production proven process for high performance, high reliability, and high storage
density.
The 2118 uses a single transistor dynamic storage cell and advanced dynamic circUitry to achieve high speed with low
power dissipation The circuit design minimizes the current transients typical of dynamic RAM operation These low
current transients contribute to the high noise Immunity of the 2118 In a system environment.
Multiplexing the 14 address bits into the 7 address Input pinS allows-the 2118 to be packaged in the industry standard
16-pin DIP The two 7-bit address words are latched Into the 2118 by the two TTL clocks, Row Address Strobe (RAS) and
Column Address Strobe (CAS). Non-critical timing requirements for RAS and CAS allow use of the address multiplexing
technique while maintaining high performance.
The 2118 three-state output is controlled by CAS, Independent of RAS. After a valid read or read-modify-write cycle, data
IS latched on the output by holding CAS low The data out pin IS returned tothehigh impedance state by returning CASto
a high state. The 2118 hidden refresh feature allows CAS to be held low to maintain latched data while RAS is used to
execute RAS-oniy refresh cycles.
The single transistor storage cell requires refreshing for data retention. Refreshing is accomplished by performing MSonly refresh cycles, hidden refresh cycles, or normal read or write cycles on the 128 address combinations of Ao through
As during a 2ms period. A write cycle will refresh stored data on all bits of the selected row except the bit which is
addre$sed.·
.
PIN
CONFIGURATION
BLOCK DIAGRAM
LOGIC SYMBOL
_VOD
64 II 128 CELL
MEMORY ARRAY
A,
A,
A,
A,
A.
A,
A,
RAS
CAS
-Vs~
D,.
OUTPUT
BUFFER
DouT
DOUT
W'
An As
ADDRESS INPUTS
CAS
COLUMN ADDRESS STROBE
D"
DATA IN
DOUT
DATA
our
WE
WRITE ENABLE
RAe;
ROW ADDRESS STROBE
Voo
POWER
Vss
GROUND
r
5VI
Intel Corporabon assumes no responsibility for the use of any Circuitry other than CIrcuitry embodied '" an Inlel product No other crrcud: patent licenses are Implied
@INTElCORPORATION, 1982
December, 1979
Order Number 1940-001
3·238
2118 FAMILY
ABSOLUTE MAXIMUM RATINGS·
'COMMENT:
AmbientTemperature Under Bias ... -10° C to +80°C
Storage Temperature ............. -65° C to +150° C
Voltage on Any Pin Relative to Vss ............ 7.5V
Data Out Current ............................ 50mA
Power Dissipation ... . . . . . . . . . . . . . . . . . . . . . . .. 1.0W
Stresses above those listed under "Absolute Maximum
Rating" may cause permanent damage to the device. This
IS a stress ratmg only and functIonal operation of the device at these or at any other conditIon above those indicated m the operational sections of thIs specification is
not Implied. Exposure to absolute maximum ratmg conditions for extended periods may affect device reliability.
D.C. AND OPERATING CHARACTERISTICS!1]
= ooe
TA
to 7o o e, Voo
Symbol
= 5V
±10%, Vss
= av,
unless otherwise noted.
Limits
Min. Typ.l21 Max. Unit Test Conditions
Parameter
Notes
IILlI
Input Load Current (any Input)
01
10
/i A
VIN=VSS to Voo
IILOI
Output Leakage Current for
High Impedance State
01
10
/i A
Chip Deselected: CAS at VIH,
Your = 0 to 5.5V
1001
Voo Supply Current, Standby
1.2
2
mA CAS and RAS at VIH
1002
Voo Supply Current, Operating
23
27
mA 2118-3, tRC = tRCMIN
3
21
25
mA 2118-4, tRC = tRCMIN
3
19
23
mA 2118-7, tRC = 1RCMIN
3
16
18
mA 2118-3, tRC = tRCMIN
3
14
16
3
12
14
mA 2118-4, tRC = tRCMIN
mA 2118-7, tRC = tRCMIN
2
4
mA CAS at VIL. RAS at VIH
3
Voo Supply Current·, RAS-Only
Cycle
1003
1005
Voo Supply Current, Standby,
Output Enabled
Vil
Input Low Voltage (all Inputs)
-2.0
08
VIH
Input High Voltage (all Inputs)
2.4
7.0
V
VOL
Output Low Voltage
0.4
V
IOl = 4.2mA
VOH
Output High Voltage
V
IOH = -5mA
24
V
NOTES:
1. All voltages referenced to V55
2. Typical values are for TA = 25°C and nominal supply voltages.
3.
100
is dependent on output loading when the device output
IS
selected Specified
100 MAX IS
measured with the output open.
CAPACITANCE[1]
TA
= 25°e,
.Symbol
VOO
= 5V ±10%,
VSS
= OV,
unless otherwise noted .
Typ.
Max.
Unit
CI1
Address, Data In
Parameter
3
5
pF
CI2
RAS, CAS, WE, Data Out
4
7
pF
NOTES
Capacitance measured with Boonton Meter or effective capacitance calculated from the equation
C = l.lt with .lV equal to 3 volts and power supplies at nominal levels
.lV
3-239
3
2118 FAMILY
A.C. CHARACTERISTICS[1,2,3]
TA = 0 0 C to 70 0 C, VDD = 5V
±1 0%,
V SS = OV, unless otherwise noted.
READ, WRITE, READ-MODIFY-WRITE AND REFRESH CYCLES
2118-3
2118-4
2118-7
Max.
Unit
tRAC
Access Time From RAS
100
120
150
ns
4,5
tCAC
Access Time From CAS
55
65
80
ns
4,5,6
2
ms
Symbol
Para meier
tREF
Time Between Refresh
tRP
RAS Precharge Time
tCPN
tCRP
CAS Precharge Ttmelnon-pagecycles~
CAS to RAS Precharge Time
tRCO
tRSH
Min.
Max.
Min.
Max.
Min.
2
.2
110
120
135
ns
55
0
25
70
0
25
ns
ns
RAS to CAS Delay Time
50
0
25
RAS Hold Time
70
85
105
tCSH
CAS Hold Time
100
120
165
ns
tASR
Row Address Set-Up Time
0
0
0
ns
tRAH
Row Address Hold Time
15
15
15
ns
tASC
Column Address Set-Up Time
0
0
0
ns
tCAH
Column Address Hold Time
15
15
20
ns
tAR
Column Address Hold Time, to RAS
60
70
90
tT
TransitIOn Time IRlse and Fall!
3
50
3
50
3
50
ns
tOFF
Output Buffer Turn Off Delay
0
45
0
50
0
60
ns
45
55
70
ns
Notes
7
ns
ns
8
READ AND REFRESH CYCLES
270
ns
tRC
Random Read Cycle Time
235
tRAS
RAS Pulse Width
115
10000
140
10000
175
10000
tCAS
CAS Pulse Width
55
10000
65
10000
95
10000
tRCS
Read Command Set-Up Time
a
0
0
ns
tRCH
Read Command Hold Time
0
0
0
ns
320
ns
ns
WRITE CYCLE
270
ns
tRC
Random Write Cycle Time
235
tRAS
RAS Pulse Width
115
10000
140
10000
175
320
10000
ns
tCAS
CAS Pulse Width
55
10000
65
10000
95
10000
ns
twcs
Write Command Set-Up Time
0
0
0
ns
tWCH
Write Command Hold Time
25
30
45
ns
tWCR
Write Command Hold Time. to RAS
70
85
115
ns
Write C(ommand Pulse Width
30
65
50
110
ns
tRWL
Write Command to RAS Lead Time
25
60
tCWL
Write Command to CAS Lead Time
45
50
100
ns
tos
Data-In Set-Up Time
0
0
0
ns
tOH
Data-In Hold Time
25
30
45
ns
tOHR
Data-In Hold Time. to RAS
70
85
115
ns
.twP
9
ns
READ-MODIFY-WRITE CYCLE
tRWC
Read-Modlfy-Wrlte Cycle Time
285
tRRw
RMW Cycle RAS Pulse Width
165
10000
320
190
10000
410
265
10000
ns
tCRW
RMW Cycle CAS Pulse Width
105
10000
120
10000
185
10000
ns
tRWO
RAS to WE Delay
100
120
150
ns
9
tcwo
CAS to WE Delay
55
65
80
ns
9
ns
NOTES
7 tRCD Imax ) IS specified as a reference pOint only. IftRCD IS less
than tRCD Imax ) access time IS tRAC. If IACD IS greater than tRCD
(max I access time IS IRCD + tCAC
tT IS measured between VIH (Min) and VIL (max I
Iwcs, Icwo and tRWO are specified as reference pOints only If
twcs <:: twcs (min) Ihe cycle IS an early wntecycleand the data
out pin Will remain high Impedance throughout the entire
cycle 'If tcwo:::: tCWD (min I and IRWO:::: IAWD {min J, Ihecycle IS
a read·modlly-wnle cycle and the data out will contain the data
read from the selected address If neither 01 the above
conditions IS satisfied, the condition of the data oul IS
Indeterminate
All voltages referenced to Vss
Eight cycles are reqUired after power-up or prolonged periods
(greater than 2ms) of FiAS Inactlvlly before proper device
operation IS achieved Any 8 cycles which perform refresh are
adequate for this purpose
A C Characteristics assume IT-=: 5ns
Assume that tACO :5 tRCD Imax I If tRCD IS greater than tACO
(max I then tRAC wl!llOcrease by the amount that tRCD exceeds
tACO 1m ax ~
load'" 2 TTL loads and l00pF
Assumes tRCO <:: tRCD Imax I
3-240
2118 FAMILY
WAVEFORMS
tRe
READCY CLE
1·-tR~
tRAS
v,"
CD 1\.0
RAS
V"
CAS
CD
tASRi- -tRAH-1
~"
~
ADDRESSES
V'L
t RSH
IReD
I
V"
r\\\ \ ~
ADDRESS
/-
v,"
V'L
teAs
V
tAR
tAse
K X
ROW
-tCAH-
K
COLUMN
ADDRESS
J::::-WE
~lePN-1
tCSH
1--;-
(B)teRP - [
v,"
/I
,
H
t RCS
d¥
DOUT
f----tOFF-
HIGH
CD
IMPEDANCE
(4)
t RAS
RAS
v,"
V"
CAS
--r
J
tASRr
V,"
ADDRESSES
V"
~
H·'....
XCi)0
,
tRCD
(i)
- t RAH
-!
,X
t ASC
r\\\
~
ROW
ADDRESS
tCSH
t RSH
\.@
- tCAH- -
K
COLUMN
ADDRESS
t RWl
'oWL
WE
V,"
V"
\.
-twcs----
- - - - - t wcH twp
0
•
1/
tWCR
I--®'DS~
V,"
)
D'N
V"
CD
_ t OH
@---
K
0
tOHR
DOUT
NOTES
Va"
VOL
HIGH
IMPEDANCE
1,2 V IH MIN AND V 1L MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS
3,4 V OH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF Dour
5 tOFF IS MEASURED TO lOUT 4 IIlO I
6 tos AND tOH ARf REFERENCED TO CAS OR
WHICHEVER OCCURS LAST
7 tRCH IS REFERENCED TO THE TRAILING EDGE OF C'AS OR RAS, WHICHEVER OCCURS FIRST
8 tCRP REQUIREMENT IS ONL Y APPLICABLE FOR RAS/CA$ CYCLES PRECEEDED BY A CAS~
ONLY CYCLE {I e, FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS)
m,
3·241
RP
1·_tePN_~1
l'
tCAS
tAR
+
~
DATA OUT
/.
CD 1\0
(B)teRP
CD
VALID
._t'p~
t Re
WRITE CY CLE
V,"
v"
0
~
tCAG
tRAC
va"
VOL
t RCH
2118 FAMILY
WAVEFORMS
READ-MODIFY-WRITE CYCLE
'Rwe
1---·.. -·1
tRRW
,
1
8ICR~-=l
~tRCD
~
1)
r=tstX
~::
ADOREs,,<;ES
.-1\\\\
tRA:~tlAse
IASRt---
)(( 1 I
T.
2)
AD~~~SS
)(
-
1-
!-tCPN---t
"'A.
(2)
.v
.1
'AW','oA"
_ - - ICWL-
;g~~~;;
(2)
tRcst--i
'Rwe
-~'v
lewD
(;IJ'
2)
_IDH"'::--
®
'®'O'l
)(r)) D~tl~N
I 0
X
-
~"'AC~
tRAC
Vo
Vo"
,
DOlll
(3)
HIGH
IMPEDANCE
(4)
VALID
DATA OUT
IOFF
"'t®
RAS-ONL Y REFRESH CYCLE
\--------------.,,----------------1
1 - - - - - -..., - - - - - - - 11
r--...--l
RAs vlH---("~.)~I1)
I:if"
¥o'
V1L
I- tcRPfs)
ADORE'SSES V
IH
A!)
AO'b~~SS
J(
v,,_~~~~~~~-~~----------------------------
DOUT
::-------------~--~IM~~~~~:~NC~E------------------
HIDDEN REFRESH CYCLE
(For Hidden Refresh Operation order 2118-3 56445, 2118-4 56446 or 2118-7 56447)
V,"~~J:-'-t-x±+-f--±7--,-±'---,t-Jr----·
....,±'--,h-.:-----t------
AOo.RESSES
V,,-~f-_t~'=f+_t_-"f;->..---'..,..--'p'------'+----'F_>-----_t------
WE
v,"
-+--"I""
v,, _ _ _
J=:t"''
'A"
NOTES
1.2
3,4
5
6
7
8
-i"';;.~"___________v_AL. .'D:I__~A-T-A----------~i®"
.
V 1H MIN AND V1l MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF INPUT SIGNALS
VOH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOUT
tOFF IS MEASURED TO lOUT" IILO I
"
tos AND tOH ARE REFERENCED TO CAS OR W'E', W~EVER OCCURS LAST
tRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS~ WHICHEVER OCCURS FIRST
tCRP REOUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A 00ONLY CYCLE he. FOR SYSTEMS WHERE CPl'HAS NOT BEEN DECODED WITH RAS)
,3-242
2118 FAMILY
D.C. AND A.C. CHARACTERISTICS, PAGE MODE[7,8,11]
TA = O°C to 70°C, VDD = 5V ±10%, Vss = OV, unless otherwise noted.
For Page Mode Operation order 2118-3 56329. 2118-4 56330. or 2118-7 56331,
2118·3
86329
8ymbol
Parameter
Min.
Max.
2118-4
86330
Min.
Max.
2118·7
86331
Min.
Max.
Unit
tpc
Page Mode Read or Write Cycle
125
145
190
ns
tpCM
Page Mode Read Modify Wrote Cycle
175
ns
CAS Precharge Time. Page Cycle
60
200
70
280
tcp
tRPM
RAS Pulse Width. Page Mode
tCAS
CAS Pulse Width
1004
Voo Supply Current Page Mode.
Minimum tpc. Minimum tCAS
ns
85
115
10000
140
10000
175
10000
ns
55
10000
65
10000
95
10000
ns
15
rnA
. 20
17
Notes
WAVEFORMS
PAGE MODE READ CYCLE
1-----------------tRPM--------·-----i------i
~~-__;:::::::::;,.t===
..do-
_
V.He
RAS
Io---+---tpc --+---+1
_
V. He
CAS
V IL
WE
V'He
VIL _ _
..,..+-_J
V OH
DOUl VOl------------~~
NOTES
1,2 V!H MIN AND V 1L MAX ARE REFERENCE LEVELS FOR\MEASUR1NG TIMING OF INPUT SIGNALS
3,4 V OH MIN AND VOL MAX'ARE REFERENCE lEVELS FOR MEASURING TIMING OF DOUT
5
6
7
8
9
tOFF IS MEASURED'TO lOUT
illO I
tRCH IS REFERENCED TO THE TRAILING EDGE OF CAS OR RAS, WHICHEVER OCCURS FIRST
ALL VOL lAGES REFERENCED TO Vss
AC CHARACTERISTIC ASSUME tT '" 50s
seE THE TYPICAL CHARACTERISTICS SECTION FOR VALUES OF THIS PARAMETER
UNDER AL TERNATE CONOITIO!')lS
10 tCRP REQUIREMENT IS ONLY APPLICABLE FOR RAS/CAS CYCLES PRECEEDED BY A CASONLY CYCLE 11 e, FOR SYSTEMS WHERE CAS HAS NOT BEEN DECODED WITH RAS)
11 ALL PREVIOUSLY SPECIFIED A C AND 0 C CHARACTERISTICS ARE APPLICABLE TO THEIR
RESPECTIVE PAGE MODE DEVICE (, e, 2118 3, S6329 WILL OPERATE AS A 21183)
3-243
-
2118 FAMILY
PAGE MODE
WRITE CYCLE
_
~---------------------------------tRPM--------------------------------~
V 1HC
RAS V,L
ADDRESSES V,H
VIL--~~t-~~Lit-'-~~------f----'~,---~~-----t------,r---£-~t---~~-----;;------------
_
V 1HC
WE
VIL------~---4~~--~F_--------_+~------+_--------~~--;1~------1_----_t-----------
V,H
D,N
VIl ______
~-'~~--------~~----~~--~------~~------~f~~------------~~----------------
PAGE MODE READ-MODIFY-WRITE CYCLE
ADDRESSES
V IH
V"
NOTES
1.2
3,4
5
6
7
8
V 1H MIN AND V 1l MAX ARt: REFERENCE lEVELS FOR MEASURING TIMING OF INPUT SIGNALS
VOH MIN AND VOL MAX ARE REFERENCE LEVELS FOR MEASURING TIMING OF DOUT
tOFF IS MEASURED TO lOUT "'- IILO I
tos AND tOH ARE REFERENCED TO CAS OR WE. WHICHEVER OCCURS LAST
tRCH IS REFERENCED TO THE TRAILING EDGE Of CAS OR RAs, WHICHEVER OCCURS FIRST
!CRP REQUIREMENT IS ONl V APPLICABLE FOR RAS/CAS CYCLES PRECEEOED BY A CASONLY CYCLE he. FOR SYSTEMS WHERE ~HASNOT BEEN DECODED WITH RAS)
3-244
2118 FAMILY
TYPICAL SUPPLY CURRENT WAVEFORMS
RAS ONLY REFRESH
l~~
'DO
40
1\
1\
60
1
1
n
20
I\J
III
l
M
\
'I
i\
1\
:I.......~
l--
100
"
11
1\
(rnA)
200
300
II \
\
11.
II\.
11\1\
~
100
500
400
V M--
)
1'-
II \
'b-...
200
300
TIME (ns)
TIME (ns)
LONG RAS/CAS
: ~',!
M
V1H
V"
111111111
J
11'11111
~
--,-60
100
,,
11.
40
(rnA)
20
J
100
1M
M'
200
M
II
1\
/\
l'
I 11
:--
1\
300
~--~
\
t-- -
I--
400
500
,
\
II \
600
I'.
700
800
900
TIME (ns)
Typical power supply waveforms vs time are shown for
the RAS/CAS timings of Read/Write, Read/Write (Long
RAS/CAS), and RAS-only refresh cycles 100 current
transients at the RAS and CAS edges require adequate
decoupling of these supplies
The effects of cycle time, Voo supply voltage and ambient
3-245
temperature on the 100 current are shown In graphs
Included In the Typical Characteristics Section Each
family of curves for 1001, 10 0 2, and 1003 is related by a
common point at Voo = 5.0V and T A = 25°C for two given
tRAS pulse widths. The tYPical 100 current for a given
condition of cycle time, Voo and T A can be determined by
combining the effects of the appropriate family of curves.
2118 FAMILY
TYPICAL CHARACTERISTICS
GRAPH 2
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS.
AMBIENT TEMPERATURE
GRAPH 1
TYPICAL ACCESS TIME
tRAC (NORMALIZED) VS Voo
12
~
11
~
10
o
~
.:t:
~
~
14
12
'"
~
GRAPH 3
TYPICAL STANDBY CURRENT
1001 VS VOO
09
~
TA=70"C
~
I~
11
10
V
0
J
~
1
08
/
09
/'
V
L
..
~
-
g
12
f-
Z
w
a:
II:
::J
tJ
10
~
~
f--
a.
a. OB
:J
TA
'"I
= DOG
"
.!? 06
OB
Voo = 45V
40
45
50
55
20
60
Voo - SUPPL Y VOLTAGE {VOLTS}
TA -
GRAPH 4
TYPICAL STANDBY CURRENT
14
--
...z
w
10
>08
:J
~
_0
AMBIENT TEMPERATURE
vl"
55V-
~
g
40
iE
t-- r--
a:
a:
~
""-
°
.!?
g
SOV
40
60
BO
20
10
~ ........
200
400
g
40
I-- VDD
I
>~
~
" 50V
g
W
II:
II:
30
tRAS - 500ns
1lsns
_0
---
BOO
600
1l
_
tAG'" 235ns
>-i
a.
20
~
40
45
=235n5
tRAS = 500ns
f RG '" 750n5
50
55
60
VDD - SUPPLY VOLTAGE (VOLTS)
GRAPH 9
TYPICAL RAS ONLY
REFRESH CYCLE
1003 VS. VOO
50
40
f-
~
TA " 251
Voo;;: 50V
I
g
"-
'"I
Z
W
30
20 1----.
40
=750n5
60
10
TA -AMBIENT TEMPERATURE (OC)
........
.......
8
t--
200
_0
1_
tRAS = 115ns
~ = 235n5
400
10
tRAS = 500 ns
tRAS = 500ns
tRAS
o
BO
20
"-
::J
I
tRAS = 500ns
tRC
30
>~
45nsec
Note that If 25nsec :S tRCD:S 45nsec device access time is
determined by equation 3 and IS equal to tRAC. If tRCD >
45nsec access time IS determined by equation 4. This
20nsec interval (shown in the tRCD inequality In equation
3) in which the falling edge of CAS can occur without
affecting access time IS provided to allow for system
timing skew in the generation of CAS.
.
REFRE~H
CYCLES
Each of the 128 rows of the 2118 must be refreshed every 2
milliseconds to maintain data Any mefTlory cycle
Read Cycle
2 Write Cycle (Early Write, Delayed Write or ReadModify-Write)
3 RAS-only Cycle
refreshes the selected row as defined by the low order
(RAS) addresses Any Write cycle, of course, may change
the state of the selected cell. USing a Read, Write, or ReadModify-Write cycle for refresh IS not recommended for
systems which utilize "wire-OR" outputs Since output bus
contention will occur
A RAS-only refresh cycle IS the recommended technique
for most applications to provide fordata retention A RASonly refresh cycle maintains the DOUT In the high
.3·247
2118 FAMILY
ThiS feature allows a refresh cycle to be "hidden" among
data cycles without affecting the data availability
impedance state with a tYPical power reduction of 30%
over a. Read or Wrrte cycle.
RAS/CAS TIMING
RAS and CAS have minimum pulse widths as defined by
tRAS and tCAS respectively. These minimum pulse widths
must be maintained for proper device operation and data
integrity. A cycle, once begun by brrngrng RAS and/or
CAS low must not be ended or aborted prror to fU,lflliing
the minimum clock signal pulse wldth(s) A new cycle can
not begin until the minimum precharge time, tRP, has been
met.
POWER ON
After the application of the Voo supply, or after extended
periods of bias (greater than 2ms) Without clocks, the
deVice must perform a minimum of eight (8) Initialization
cycles (any combination of cycles contarning a RAS clock
such as RAS-only refresh) prror to normal operation.
DATA OUTPUT OPERATION
The Voo current (100) requirement of the 2118 durrng
power on IS, however, dependent upon the Input levels of
RAS and CAS If the rnput levels of these clocks are at VIH
or Voo, whichever IS lower, the 100 requirement per deVice
IS 1001 (100 standby). If the Input levels for these clocks
are lower than V IH or Voo the 100 requirement Will be
greater than 1001, as shown rn Figure 2.
The 2118 Data Output (Dour), which has three-state
capability, is controlled by CAS Durrng CAS high state
(CAS at VIH) the output IS In the high impedance state. The
follOWing table summarizes the Dour state for various
types of cycles.
Intel 2118 Data Output Operation
lor Various Types of Cycles
Type of Cycle
DOUT State
Read Cycle
Data From Addressed
Memory Cell
HI-Z
HI-Z
HI-Z
Data From Addressed
Memory Cell
Indeterminate
Early Wrrte Cycle
RAS-Only Refresh Cycle
CAS-Only Cycle
Read/Modlfy/Wrrte Cycle
Delayed Write Cycle
~.
3
t-----t----t---t-t-
T
"
.£l
HIDDEN REFRESH
An optional feature of the 2118 is that refreSh cycles may
be performed while maintaining valid data at the output
pin. This feature is referred to as Hidden Refresh. Hidden Refresh is performed by holding CAS at VIL and
taking RAS high and after a specified precharge period
(tRP) , executing a "RAS-Only" refresh cycle, but with CAS
held low (see Figure 1.)
RAS
-{
t ""8
MEMORY
CYCLE
CYCLE
/
CAS
DOUT
HIGHZ
<
DATA
Figure 1. Hidden Refresh Cycle.
'}-
Voo
(VOLTS)
Figure 2. Typical IDD VS VDD during power up.
For large systems, this current requirement for 100 could
be substantially more than that for which the system has
been deSigned. A system which has been designed,
assuming the majority of deVices to be operating in the
refresh/standby mode, may produce suffiCient 100
loadrng such that the power supply may current limit. To
assure that the system will not experience such loading
during power on, a puliup resistor for each clock input to
Voo to malntarn the non-selected current level (1001) for
the power supply is recommended.
3·248
inter
2141
4096 X·1 BIT STATIC RAM
2141-2
120
70
20
Max. Access Time (ns)
Max. Active Current (mA)
Max. Standby Current (mA)
2141-3
150
70
20
• ADVANCED HMOS II Technology
• Industry Standard 2147 Pinout
• Completely Static Memory - No Clock
or Timing Strobe Required
• Equal Access and Cycle Times
• Single +5V Supply
2141-4
200
55
12
2141-5
250
55
12
21411.:-3
150
40
5
2141L-4 2141L-5
200
250
40
40
5
5
.' Automatic Power-Down
• Directly TTL Compatible - All Inputs
and Output
• Separate Data Input and Output
• Three-State Output
• High Reliability Plastic or Cerdip Package
The Intel® 2141 is a 4096-bit static Random Access Memory organized as 4096 words by 1-bit using ADVANCED
HMOS II, a high-performance MOS technology. It uses a uniquely innovative design approach which provides the easeof-use features associated with non-clocked static memories and the reduced standby power dissipation associated
with clocked static memories. To the user this means low standby power dissipation without the need for clocks, address setup and hold times, nor reduced data rates due to cycle times that longer than access times.
CS controls the power-down feature. In less than a cycle time after CS goes high - deselecting the 2141 - the part
automatically reduces its power requirements and remains in this low power standby mode as long as CS remains high.
This device feature results in system power savings as great as 85% in larger systems, where the majority of devices are deselected.
The 2141 is placed In an 18-pin package configured with the industry standard pinout. the same as the2147. It is directly TTL
compatible in all respects: inputs. output. and a single +5V supply. The data is read out nondestructively and has the same
polarity as the input data. A data input and a separate three-state output are used.
PIN CONFIGURATION
LOGIC SYMBOL
Ao
Vee
A.
, A,
17
A,
A3
As
A4
A.
As
13
DOUT
,
WE
A,.
12
An
11
D,N
@
A,
A2
A3
A4
As
A. DOUT
A,
As
A.
A,.
An
A.
A2
BLOCK DIAGRAM
Cs
~vcc
-GND
MEMORY ARRAV
64 ROWS
64 COLUMNS
DIN WE CS
(]
DOUT
PIN NAMES
A.-An
WE
CS
D,N
Dour
ADDR ESS INPUTS
WRITE ENABLE
CHIP SELECT
DATA INPUT
DATA OUTPUT
Vee POWER I+5V)
GND GROUND
TRUTH TABLE'
cs
WE
3-249
2141
ABSOLUTE MAXIMUM RATINGS*
'COMMENT: Stresses above those listed under "Absolute
MaxImum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional opera·
tion of the devIce at these or any other conditions above
those indicated in the operational sections of this specifi·
cation is not Implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliabtllty.
TemperatureUnderBias •....•......... -10°Ct085°C
Storage Temperature ............... -65°C to +150° C
Voltage on Any Pin With
Respect to Ground .................... -l.SV to +7V
Power Dissipation ............................. 1.2W
D.C. Output Current ••.•••••••••••..••..•••.•• 20mA
D.C. AND OPERATING CHARACTERISTICS
TA = Oo'c to 70°C,
Vee = +5V±10% unless otherwise noted.
2141L-3/L-4/L-S
2141-2/-3
2141-4/-5
Min. Typ.f11 Max. Min. Typ.l1] Max. Min. Typ.11] Max.
Unit
Conditions
Ilul
Input Load Current
(All Input Pins)
0.01
1.0
001
1.0
001
1.0
/J A
Vee=Max , VIN=
GND to Vce
Ilwl
Output Leakage
Current
01
10
0.1
10
0,1
10
/J A
CS=VIH, Vee=Max.,
VOUT=GND to 4.5V
IcC
Operating Current
45
70
40
55
30
40
rnA
Vee=Max , CS=V'L,
ISB
Standby Current
20
12
5
rnA
Outputs Open
Vee=MIn to Max.,
IpOl'1
Peak Power-On
Current
40
30
18
rnA
VIL
Input Low Voltage
-1.0
V
2.0
Symbol
Parameter
CS=V'H
Vee-GND to Vee Min
CS=Lower of Vee or
-
VIH Min,
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
losl31
Output,Sho;t Circuit
Current
Notes: 1.
2.
,
3.
08
-1.0
08
-1.0
08
6.0
20
60
20
60
V
0.4
V
10L
V
10H = -4.0mA
04
24
0.4
24
24
±275
±275
±275
rnA
= B.OmA
VouT=GND to Vee
Typical limits are at Vee = 5V, TA = +25 0 C, and specified loading
Icc exceeds ISB maximum during power-on, as shown In Graph 7. A pull-up resistor to Vee on the CS input is required to
keep the deVice deselected, otherwise, power-on current approaches Icc active
Duration not to exceed one second.
A.C. TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0 Volts
5 nsec
1.5 Volts
0.8-2.0 Volts
1 TTL Load plus 100pF
CAPACITANCE [4[
TA = 25°C, f = 1.0MHz
Symbol
Parameter
Max. Unit
Conditions
GIN
Input Capacitance
5
pF
VIN = OV
GOUT
Output Capacitance
6
pF
VOUT = OV
Note 4. This parameter
IS
sampled and not 100% tested.
3-250
2141
A.C. CHARACTERISTICS
TA
= OGC to 70·C, Vee = +5V±10%, unless otherwise noted.
READ CYCLE
Parameter
Symbol
2141-2
Max.
Min.
2141-3/L-3
Min.
Max.
2141-4/L-4
Min.
Max.
2141-5/L-5
Min.
Max.
120
150
200
250
Unit
ns
IRc
Read Cycle Time
1M
Address Access Time
120
150
200
250
ns
IAcs1(1)
Chip Select Access Time
.120
150
200
250
ns
250
ns
IAcs2(2)
Chip Select Access Time
tOH
Output Hold from Address Change
10
10
160
10
10
tL.Z 131
Chip Selection to Output in Low Z
30
30
30
30
tHz l31
Chip Deselection to Output in High Z
0
Ipu
Chip Selection to Power U'p Time
0
tPD
Chip Deselection to Power Down Time
130
60
0
60
0
60
200
0
60
ns
60
60
ns
ns
0
0
60
0
ns
60
ns
WAVEFORMS
READ CYCLE NO.1 [4,5J
~r-~~~=-_~=-_~~-_-'A_A~~~~~~~~~~~~l'-1,....-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_*_~~~~~~~~~
>---------------'RC'----------------li:=P?2--'
~ ~
o
60
8n
I+
:,on.
,
80
DESELECT TIME (ns)
FIGURE 3. tACS VS. DESELECT TIME.
~
cs- -
--
I/'"
1'\
\
VIL
-- ~
ICC·
-- -"-
-
The power switching characteristic of the 2141 requires
more careful decoupling than would be required of a
constant power device. It IS recommended that a O.lI'F
ceramic capacitor be used on every other device, with a
221'F to 471'F bulk electrolytic decoupler every 32 devices.
The actual values to be used will depend on board layout,
trace widths and duty cycle. Power supply grldding is
recommended for PC board layout. A very satisfactory
grid can be developed on a two-layer board with vertical
traces on one side and horizontal traces on the other, as
shown in Figure 4.
/
iCC
\
---
J
ISB
!
I
'-
FIGURE 1, icc WAVEFORM.
ICC
Vce _ _.....
_~
a:
w
;:
~
vee
w
u
~0
w
OJ
"~
"iii
a:
>-
'">
'"
ISB
32K
4K 8K '6K
MEMORY SIZE IN WORDS
64K
FIGURE 4. PC LAYOUT.
FIGURE 2. AVERAGE DEVICE DISSIPATION VS.
MEMORY SIZE.
3-254
2147H
HIGH SPEED 4096 x 1 Bit STATIC RAM
Max. Access Time (ns)
Max. Active Current (mA)
Max. Standby Current (mA)
•
•
•
•
•
•
2147H·1
35
180
30
2147H·2
45
180
30
2147H·3
55
180
30
2147H
70
160
20
2147HL
70
140
10
Pinout, Function, and Power Compatible to Industry Standard 2147
•
Direct Performance Upgrade for 2147
•
Automatic Power-Down
HMOS II Technology
Completely Static Memory-No Clock
or Timing Strobe Required
Equal Access and Cycle Times
Single + SV Supply
O.8-2.0V Output Timing Reference
Levels
•
High Density 18-Pin Package
•
Available in EXPRESS
- Standard Temperature Range
..;;.. Extended Temperature Range
•
Separate Data Input and Output
•
Three-State Output
The Intel® 2147H is a 4096-bit static Random Access Memory organized as 4096 words by 1-bit using
HMOS-II, Intel's next generation high-performance MOS technology. It uses a uniquely innovative design
approach which provides the ease-of-use features associated with non-clocked static memories and the
reduced standby power dissipation associated with clocked static memories. To the user this means low
standby power dissipation without the need for clocks, address setup and hold times, nor reduced data
rates due to cycle times that are longer than access times.
es controls the power-down feature. In less than a cycle time after es goes high-deselecting the 2147H
-the part automatically reduc!,!s its power requirements and remains in this low power standby mode as
long as es remains high. This device feature results in system power savings as great as 85% in larger
systems, where the majority of devices are deselected.
The 2147H is placed in an 18-pin package configured with the industry standard 2147 pinout. It is directly
TTL compatible in all respects: inputs, output, and a single + 5V supply. The data is read out nondestructivelyand has the same polarity as the input data. A data input and a separate three-state output are used.
PIN CONFIGURATION
BLOCK DIAGRAM
LOG IC SYMBO L
@
Po"
A,
A,
A2
A,
A.
As
A. DOUT
A7
As
A.
A,.
A"
A.
A2
A,
A.
-Vee
~GND
A,
MEMORY ARRAY
64 ROWS
, 64COlUMNS
DIN WE CS
D,.
@
PIN NAMES
Po"-A,, ADDRESS INPUTS
WRITE ENABLE
CHIP SELECT
DATA INPUT
D,N
DATA OUTPUT
DoUT
WE
cs
Vee POWER (+5VI
GND GROUND
TRUTH TABLE
MODE
NOT SELECTED
WRITE
READ
OUTPUT
HIGH Z
HIGHZ
DoUT
Inlel Corporation assumes no responsibility for the use of any CirCUitry other than Circuitry embodied
Intel Corporation, 1979, 1980
3-255
In
an Intel product No other CirCUit patent licenses are Implied
ApriL 1980
2147H
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ............. -10·Ct08S·C
StorageTemperature ............. -65·Cto +1S0·C
Voltage on Any Pin
With Respect to Ground ............ - 3.SV to + 7V
Power Dissipation ........................... 1.2W
D.C. Output Current ......................... 20 mA
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage
to the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those Indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
D.C. AND OPERATING CHARACTERISTICS[1]
(TA = O·C to 70·C, VCC =
r
Symbol
Parameter
ilLo I
Input Load Current
(All Input Pins)
Output Leakage
lee
Operating Current
III
+ SV
± 10%, unless otherwise noted.)
2147H-1, 2, 3
Min. Typ_ Max.
0.01
10
Min.
2147H
Typ.(2)
0.01
Max.
1.0
IPOI31
2147HL
Typ.[2J Max.
0.01
1.0
Unit
Test Conditions
p.A
Vee = Max.,
V,N =GND to Vee
CS = V,H' Vee = 5.5V
Vour - GND to 4.5V
TA = 25·C I Vee = Max.,
CS=V,L,
TA=O°C
Outputs Open
Vee = Min. to Max.,
CS.V,H
Vee =GND to Vee Mon.,
0.1
50
0.1
50
0·1
50
p.A
120
170
100
150
160
100
135
140
mA
mA
Current
180
ISB
Min.
Standby Current
18
30
12
20
7
10
mA
Peak Power-On
35
70
25
50
15
30
mA
0.8
6.0
0.4
V
V
V
V
CS -= Lower of Vee or V1H Min.
Current
V,L
V,H
VOL
VOH
I
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-3.0
2.0
0.8
6.0
0.4
-3.0
2.0
2.4
0.8
60
0.4
24
-3.0
2.0
24
IOL=8 mA
10H= -4.0 mA
NOTES:
1. The operating ambient temperature range is guaranteed With transverse air flow exceeding 400 linear feet per minute.
2. Typical limits are at Vee =5V, TA = + 25"C, and specified loading.
3. A pull-up resistor to Vee on the CS Input Is required to keep the deVice deselected; otherwise, power-on current approaches Icc active.
Vee
A.C. TEST CONDITIONS
4800
Input Pulse Levels
Input Rise and Fall Times
Input Timing Reference Levels
Output Timing Reference Level (2147H-1)
Output Timing Reference Levels
(2147H, H-2, H-3, HL)
Output Load
GNDt03.0V
Sns
1.SV
1.SV
0.8-2.0V
See Figure 1
Dour - - -.....- - ' -..
30 pF
(INCLUDING
2550
SCOPE AND
JIG)
Figure
1. Output Load
Vee
4800
CAPACITANCE[4] (TA=2S·C, f= 1.0 MHz)
DOUT - - -.....- -. .
Symbol
Parameter
Max. Unit Conditions
CIN
Input Capacitance
S
pF
VIN=OV
COUT
Output Capacitance
6
pF
VOUT= OV
2550
5 pF
NOTE:
4. This parameter
IS
sampled and not 100% tested.
Figure 2. Output Load for tHZ. tLl. twz. tow
3-256
intJ
2147H
A.C. CHARACTERISTICS
Read Cycle
Symbol
(TA= o·c to 70·C, Vcc=
+ 5V
± 10%, unless otherwise noted.)
2147H,
2147H·3
2147H·1
2147H·2
2147HL
Min. Max. Min. Max. Min. Max. Min. Max.
Parameter
tRc l1J
Read Cycle Time
tAA
Address Access Time
35
45
tACS1 18J
tACS2[9J
Chip Select Access Time
35
45
Chip Select Access Time
35
45
35
45
55
70
55
ns
55
70
ns
65
80
ns
Output Hold from Address Change
5
5
5
5
Chip Selection to Output in Low Z
5
5
10
10
tHZ[2,3,7J
Chip Deselection to Output in High Z
0
tpu
Chip Selection to Power Up Time
0
tpD
Chip Deselection to Power Down Time
0
30
0
20
0
30
0
20
ns
70
tOH
t l.Z[2,3, 7J
30
Unit
0
ns
ns
40
ns
30
ns
0
20
ns
WAVEFORMS
Read Cycle No. 114,5)
~. . - - - - * ----------------------------'Re--------------------------~l
ADDRESS
"'.-0-------- 'AA ------------~~I
1-------- 'OH - - - - - - t
OATA OUT
DATA VALID
PREVIOUS DATA VALID
Read Cycle No. 214,6)
~ l1<~==========~-'-A-es~===I=========~~I---------------------------
---------------------------'Re--------------------------~(
'_. __
-------...:.;::::::.==='------(~ X X ),r---------------------------------""'J-:::::~=:--1<-0------- 'cz -----_.
HIGH IMPEDANCE
DATA OUT
Vee
SUPPl V
CURRENT
__
r'-.L.J............
HIGH
DATA VALID
...1 , ....._______________________________
--'
IMPEDANCE
::- -~-""-j.so%---------·r---'-;L
..
NOTES:
1. All Read Cycle timings are referenced from the last valid address to the first transitioning address.
2. At any given temperature and voltage condition, tHZ max. is less than tLl min. both for a given device and from device to device.
3. Transition is measured ± 500 mV from steady state voltage with specified loading in Figure 2.
4. WE is high for Read Cycles.
5. Device is continuously selected, CS = V,L .
6. Addresses valid prior to or coincident with CS transition low.
7. This parameter is sampled and not 100% tested.
8. Chip deselected for greater than 55 ns prior to selection.
9. Chip deselected for a finite time that is less than 55 ns prior to selection. If the deselect time IS 0 ns, the chip is by definition
selected and access occurs according to Read Cycle NO.1. Applies to 2147H, 2147HL, 2147H·3.
3·257
2147H
A.C. CHARACTERISTICS (Continued)
Write Cycle
Symbol
2147H,
2147H·3
2147H·2
2147HL
2147H·1
Min. Max. .Min. Max. Min. Max. Min. Max. . Unit
Parameter
twe[2]
Write Cycle Time
tew
Chip Selection to End of Write
tAW
Address Valid to End of Write
tAS
Address Setup Time
twp
Write Pulse Width
tWA
Write Recovery Time
~o
tow
Data Valid
tOH
twZ[3]
Data Hold Time
Write Enabled to Output in High Z
toW[3]
Output Active from End of Write
WAVEFORMS
Write Cycle No. 1
End of Write
35
35
35
0
20
0
20
10
0
0
45
45
45
0
25
0
25
10
0
0
20
~--~---------
55
45
45
0
25
10
25
10
0
0
25
70
55
55
0
40
15
30
10
0
0
25
ns
ns
ns
ns
ns
ns
ns
ns
35
ns
ns
.."
---.,
AODRESS
~
(WE CONTROLLED)[4]
"''' 'l'i
~
'c.
II
..
'.,----1
'
--'.'~
JIll
1---"',-
\\
t
J.
DATA IN
'oj
---tow
I
DATA IN VAllO
1-----"'.
- - .. ,----I
OATA
OUT-------DA-TA-U-ND-"-'N-ED-----~
=1.-----
'.,
Write Cycle No.2
(CS CONTROLLED~41
H
2149HL
Max.
1.0
001
Output Leakage Current
01
50
Icc
Operating Current
120
180
V'L
Input Low Voltage
-30
2.1
JiLOI
V'H
Input H'gh Voltage
VOL
Output Low Voltage
VOH
Output H'gh Voltage
IOS/3)
Output Short CirCUit Current
Min.
Typ
(2'
001
,
08
-30
60
2.1
Unit
1.0
JlA
Vcc = max, V'N = GND to 5.5V
01
50
JlA
90
125
mA
Vcc = max, CS = V'L.
Outputs Open
08
V
60
V
04
V
±200
mA
24
±150
±200
Test Conditions
CS - V'H' Vcc - 5.5V
VOUT = GND to 5.5V
04
24
Max.
V
±150
10L = 8 mA
10H = -40 mA
VOUT = GND to Vcc
Notes:
1. The operating ambient temperature range 's guaranteed With transverse air flow exceeding 400 linear feet per minute. Typical
thermal res,stance values of the package at maximum temperatures are'
BJA (@ 400 fpM air flow) = 40° C/W
BJA (still air) = 70° C/W
BJC = 25° CIW
2 Typical I,mits are at Vcc = 5V, TA = +25° C, and Load A
3. Duration not to exceed 1 second.
+5V
A.C. TEST CONDITIONS
Input Pulse Levels
5 nsec
+5V
DOUT - - -.....- -. .
30 pF
Input and Output Timing
Reference Levels
Output Lead
4800
GND te 3.0 Velts
Input Rise and Fall Times
1.5 Velts
(INCLUDING
SCOPE AND
JIG)
2550
See Lead A.
4800
D OUT - - - _ - -..
2550
CAPACITANCE 131
Load A.
T" =25·C, f =1.0MHz
Symbol
Parameter
Max.
Unit
Conditions
C'N
Address/Control Capacitance
5
pF
V,N = OV
C,e
Input/Output Capacitance
7
pF
VeuT = OV
Note 3. This parameter is sampled and not 100% tested.
3-264
Load B.
5pF
inial
2149H FAMILY
A.C. CHARACTERISTICS
T A =O·G to '+- 70·G, Vee = + 5V ± 10% unless otherwise noted.
READ CYCLE
2149H-2
Parameter
Symbol
Min.
Max.
Min.
Max.
2149H/HL
Min.
Max.
Unit
tRC
Read Cycle Time
tAA
Address Access Time
45
55
70
ns
Chip Select Access Time
20
25
30
ns
tACS
45
2149H-3
55
70
Telt
Condilions
ns
tOH
Output Hold from Address Change
5
5
5
ns
tlZ
Chip Selection Output
5
5
5
ns
Note 3,4
tHZ
Chip Deselectlon to Output
ns
Note 3, 4
In
Low Z
In
High Z
15
0
0
15
0
15
WAVEFORMS
READ CYCLE No.
11" 21
ADDRESS
DATA OUT
--.It§,_ _
'RC-===~_
-f~
.1
OATA VALID
--------------~~~~~---------------------------
READ CYCLE No. 213)
..
•
'Re
'
ADDRESS
'ill/ VIIIIII
\\\\\\\\\\\\\\\\\\l
tA.CS
'e.
I.
1~'r.=1
DOUT
Noles:
1 WE, IS high for Read Cycles
2 Device IS continuously selected,
CS
= Vil
3 At any given temperature and voltage condition, tHZ max IS less than tlz min both fur a given device and from device to devIce
4 Transition IS measured ±500 mV from high Impedance voltage With Load B ThiS parameter IS sampled and not 100% tested
3-265
inter
2149H FAMILY
A.C. CHARACTERISTICS (continued)
WRITE CYCLE
2149H·2
Parameter
Symbol
Min.
2149H·3
Max.
Min.
2149H/HL
Max.
Min.
Max.
Unit
twe
Write Cycle Time
45
55
70
ns
tew
Chip Selection to End of Write
40
50
65
ns
tAW
Address Valid to End of Write
40
50
65
ns
tAS
Address Setup Time
0
0
0
ns
twp
Write Pulse Width
35.
40
50
ns
5
5
5
ns
20
20
25
ns
0
0
0
ns
Write Recovery Time
, tWR
tow
Data Valid to End of Write
tOH
Data Hold Time
twz
Write Enabled to Output In High Z
0
tow
Output Active from End of Write
0
15
0
20
0
0
0
25
ns
Note 2
ns
Note 2
WAVEFORMS
WRITE CYCLE No. 1 (WE CONTROLLED)
twe
ADDRESS
CS[l]
---tew
~~
fiilPLfL fJ.!J.jjjjfjjjl
.
tAW
i---tAs--j
~tWR-->-
twp
\\
tOH
, t : = tow
,I
)( DATA IN VALID )(
DATA IN
I--tw~,
DATA UNDEFINED
DATA OUT
tow"'j
HIGH IMPEDANCE
I
WRITE CYCLE No.2 (CS CONTROLLED)
twe
ADDRESS
---->
-
A
tew
}
tAW
-tWR-
twp
.\\\ \ \ \ \ \ \ \ \ \\\2
,/11/// / ILLLLLLLLifL
. r.:=.tow-~to~.
DATA IN VALID )(
I
DATA IN
DATAO_U_T-=::::::D=A=T=A=U=N=D=E=F=IN=E=D=====---)==~----~----~~
-
k----twz
HIGH IMPEDANCE
_______________
Note.:
1 If
CS goes high simultaneously with WE high, the output remains In a high Impedance state
2 Transition
15
measured ± 500 mV from high Impedance voltage with Load B ThiS parameter
3·266
IS
Test
Conditions
sampled and not 100% tested
intJ
2164A FAMILY
65,536 )('1 BIT DYNAMIC RAM
2164A·15
2164A·20
150
200
Read, Write Cycle (ns)
260
330
Page Mode Read, Write Cycle (ns)
125
170
Maximum Access Time (ns)
• HMOS·D III technology
• Low capacitance, fully TTL compatible
inputs and outputs
• Single
+ 5V supply,
± 10% tolerance
• 128 refresh cycle/2 ms RAS only
refresh
• Compatible with the 2118
• Extended page mode, read·modify.
write and hidden refresh operation
• Inputs allow a - 2.0V negative
overshoot
• Industry standard 16·pin DIP
• Compatible with Intel's micropro·
cessors and DRAM controllers
The 2164A is a 65,536 word by 1·bit N·channel MOS dynamic Random Access Memory fabricated with Intel's HMOS-O III
technology for high system performance and reliability, The 2i64A design Incorporates high storage cell capacitance,
to provide wide internal device margins for reduced noise sensitivities and more reliable system operation. Moreover,
high storage cell capacitance results in low soft errorrates without the need for a die coat. HMOS-O III process employs
'
the use of redundant elements.
The 2164A is optimized for high speed, high performance applications such as mainframe memory, buffer memory,
microprocessor memory, peripheral storage and graphic terminals. For memory intenSive microprocessor applications
the 2164A Is fully compatible with Intel's DRAM controllers and microprocessors to provide a complete DRAM system,
Multiplexing the 16 address bits into the 8 address Input pins allows the 2164A to achieve high packing density. The 16
pin DIP provides for high system bit densities, and is compatible with widely available automated testing and insertion
equipment. The two a-bit TIL level address segments are latched Into the 2164A by the two TIL clocks, Row Address
Strobe (FIAS) and Column Address Strobe (CAS). Non·critical timing requirements for the RAS and CAS clocks allow the
use of the address multiplexing technique while maintaining high performance,
The non-latched, three state, TIL compatible data output is controlled ~AS, independent of RAS. After a valid read or
read-modify-write cycle, data is held on the data output pin by holding CAS low, The data output is returned to a high impedance state,~eturning CAS to a high state, Hidden refresh capability allows the device to maintain data at the output ~Iding CAS low while RAS is used to execute FIAS-only refresh cycles. Refreshing is accomplished by performing RAS-only cycles, hidden refresh cycles, or normal read or write cycles on the 128 address combinations of
addresses Ao through ~, during a 2 ms period.
BLOCK DIAGRAM
PIN
CONFIGURATION
LOGIC
SYMBOL
10F126
128xt28CELl
'ow
MEMOAVARRAY
"
"
"
"
...
.." ,
AI
AO-A7
ADDRESS lNI>tJTS
en
COLUMN AnDRESS STROBE
OECODERS
128x 128 CELL
MEMORY ARRAY
_ _ VOl)
_IISS
'"
DOUT
'"
...
'o~
on
'"
'§
ROW ADDRESS STROBE
POWER (-+ SV)
GROUND
.,.
""
DATA IN
Intel Corporation assumes no responsibility for the use of any Circuitry other than CirCUitry embodied
© INTEL CORPORATION, 1982
3-267
In
an Intel product No other CIrcUIt patent licenses are Implied
Order Number:
2~ri~5:~
inter
2164A FAMILY
ABSOLUTE MAXIMUM RATINGS·
'COMMENT:
Stresses above those listed under "Absolute Maximum Rating"
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at
any other condition above those indicated In the operational
sections of this specification is not implied. Exposure to abo
solute maximum ratlflg conditions for extended periods may
affect device reliability.
Ambient Temperature
Under Bias .................. -10·C to + 80·C
StorageTemperature .. Cerdip -65·Cto + 150·C
Plastic - 55·C to + 125·C
Voltage on Any Pin except Voo
Relative to Vss .................. - 2.0V to 7.5V
Voltage on Voo Relative to Vss .... -1.0V to 7.5V
Data Out Current ...................... 50 mA
Power Dissipation ................., ..... 1.0W
D.C. AND OPERATING CHARACTERISTICSI1)
TA=O·C to 70·C, Voo=5V± 10%, Vss= OV, unless otherwise noted.
Limits
Symbol
Max.
Unit
Input Load Current (any Input)
10
pA
VIN = VSS to VOO
JlLOi
Output Leakage Current for
High Impedance State
10
p.A
Chip Deselected: CAS at VIH ,
DOUT= 0 to 5.5V
1001
Voo Supply Current, Standby
3
5
mA
CAS and RAS at VIH
42
55
mA
2164A·15, tRC=tRCMIN
3
33
45
mA
2164A·20, tRC=tRCMIN
3
30
45
mA
2164A·15, tRC = tRCMIN
24
40
mA
2164A·20, tRC = tRCMIN
6
mA
CAS at VIL, RAS at VIH
0.8
V
7.0
V
0.4
V
IOL=4.2 mA
5
V
IOH= -5 mA
5
1002
Parameter
Typ.l2)
JlLd
Min.
Voo Supply Current, Operating
1003
Voo Supply Current, RAS·Only
Cycle
1005
Voo Supply Current, Standby
Output Enabled
VIL
Input Low Voltage (all inputs)
-1.0
2.:4
VIH
Input High Voltage (all inputs)
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
Test Conditions
Notes
3
4
NOTES:
1. All voltages referenced to Vss.
2. Typical values are for TA = 25'C and nominal supply voltages.
3. 100 is dependent on output loading when the device output Is selected. Specified 100 MAX is measured with the output open.
4. Specified VIL MIN is for steady state operation. Ouring transitions the inputs may overshoot to - 2.0V for periods not to exceed 20 ns.
5. Test con~itions apply only for O.C. characteristics. A.C. parameters specified with a load equivalent to 2 TTL loads and 100 pF.
CAPACITANCEI1)
NOTES:
1. Capacitance measured with Boonton Meter or effective
capacitance calculated from the equation:
TA=25·C, Voo=5V±10%, Vss= OV,
unless otherwise noted.
Symbol
j)arameter
Typ.
Max.
Unit
C 11
Address, Data In
3
5
pF
C12
WE, qata Out
3
6
pF
C 13
RAS, CAS
4
8
pF
C= IAt
IN
with AV equal to 3 volts and power supplies at nominal
levels.
3·268
2164A FAMILY
A.C. CHARACTERISTICS 11,2,31
TA= O'C to 70·C, voo= 5V ± 10%, Vss= OV, unless otherwise noted.
READ, WRITE, READ·MODIFY·WRITE AND REFRESH CYCLES
2164A·15
Symbol
Parameter
tAAC
Access Time From RAS
tCAC
Access Time From
tAEF
tAP
Time Between Refresh
tCPN
(;AS Precharge Time (non·page cycles)
CAS to RAS Precharge Time
teAP
Min.
~ Precharge Time
100
25
-20
30
85
150
0
20
0
25
90
3
0
(;AS Delay Time
RAS to
tCSi'l
CAS Hold Time
tASA
tAAH
Row Address Set·Up Time
tASC
Column Address Set·Up Time
tCAH
tAA
tT
Column Address Hold Time
Transition time (Rise and Fall)
tOFF
Output Buffer Turn Off Delay
2164A·20
Min.
150
85
2
CAS
tACO
t ASH
Max.
~HoldTime
Row Address Hold Time
Column Address Hold Time to RAS
65
50
30
120
35
-20
35
120
200
0
25
0
30
110
3
0
Max.
Unit
Notes
200
120
2
ns
ns
4,5
5,6
ms
ns
ns
80
ns
ns
7
ns
ns
ns
ns
ns
ns
ns
50
40
ns
8
ns
READ AND REFRESH CYCLES
tAC
Random Read Cycle Time
tAAS
RAS Pulse Width
tCAS
tACS
CAS Pulse Width
Read Command Set·Up Time
tACH
Read Command Hold Time referenced to CAS
Read Command Hold Time referenced to RAS
tARH
260
150
85
0
5
20
10000
10000
330
200
120
0
5
20
ns
10000
10000
ns
ns
ns
ns
ns
9
9
NOTES:
1. All voltages referenced to Vss.
2. An initial pause of 500 ~s is required after power up followed by a minimum of eight (8) initialization cycles (any combination of
cycles containing a RAS clock such as RAS·only refresh). 8 initialization cycles are required after extended periods of bias (greater
than 2 ms) without clocks.
3. A.C. Characteristics assume tT = 5 ns.
4. Assumes that t ACo :5 tACO(max). If tAco is greater than tACO(max) then t AAC will increase by the amount that tACO exceeds tACO(max).
5. Load = 2 TTL loads and 100 pF.
6. Assumes tACO;': tACO(max).
7. tACo(max) is specified as a reference point only. If tRCO is .Iess than tACD(max) access time is t RAC ' If tRco is greater than tRCO(max)
access time is tRCO + t CAC ' tAco(min) = tRAH + t ASC + tT + tT (tT = 5 ns).
8. tT is measured between VIH(min) and Vldmax).
9. Either tRCH or tRRH must be satisfied.
3·269
2164A FAMILY
A.C. CHARACTERISTICS (con't.)
WRITE CYCLE
Symbol
Parameter
t RC
Random Write Cycle Time
tRAS
RAS Pulse Width
tCAS
twcs
CAS Pulse Width
tWCH
t WCR
twp
I RWL
Write Command Hold Time
Write Command Hold Time to RAS
Write Command Pulse Width
Write Command 10 RAS Lead Time
Write Command Set· Up Time
tCWL
Write Command to CAS Lead Time
tos
toH
Data·ln Set·Up Time
toHR
Data·ln Hold Time to RAS
Data·ln Hold Time
2164A·15
Max.
Min.
2164A·20
Min.
Max.
260
150
85
-10 .
30
95
30
40
40
0
30
95
330
200
120
-10
40
120
40
50
50
0
40
120
10000
10000
Unit
Notes
ns
10000
10000
ns
ns
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
READ·MODIFY·WRITE CYCLE
tRWC
Read·Modify·Write Cycle time
tRRW
tCRW
t Rwo
RMW Cycle RAS Pulse Width
tcwo
CAS to WE Delay
280
170
105
125
60
RMW Cycle CAS Pulse Width
RAS to WE Delay
10000
10000
355
225
145
170
90
ns
10000
10000
ns
ns
ns
10
10
ns
NOTES:
10. t wcs , tCWD and t RWD are specified as reference pOints only. If twcs",twcs(min) the cycle is an early write cycle and the data out
pin will remain high impedance throughout the entire cycle. If t CWD '" tcwdmin) and tRWD'" tRWD(min) the cycle is a read·modify·
write cycle and the data out will contain the data read from the selected address. If neither of the above conditions is satisfied,
the condition of the data out is indeterminate.
WAVEFORMS
READ CYCLE
lAC
_ t RP
tRAS
(i)
V'H
RAS
VOL
(f)tcRP-1
V'H
CAS
VOL
---!
/
1\.0
.
~ICPN~I
tCSH
1--;-
tRCD
!
0J
1\\\\0
lASH
tCAS
/
IAR
tASAi-
~H
ADDRESSES
VOL
.~.
- t RAH - ]
ROW
ADDRESS
1- lAse
K )(
_ICAH-
K
COLUMN
ADDRESS
l-t Rcs
WE
V'H
-
cfY
VOL
-
-tRRH
®
r
®
lRCH
\
tCAC
tRAC
VO H
HIGH
VOL
IMPEDANCE
DOUT
- tOFF -
CD
0
3·270
VALID
DATA OUT
®
r=-
2164A FAMILY
WAVEFORMS
WRITE CYCLE
'RC
I-'R'-/
tRAS
V,.
Rn
0'
VIL
III
-
0 1cR'-j
ro
tesH
GJ ~\\' I\~
iX ) -
-tRAH-1
tASRr
)fD®
ADDRESSES
VIL
I
t RSH
tRCD
if
V,H
VIL
v,.
tI
'AR
'C'N~I
I'
~'cAH-
tASC-
ROW
ADDRESS
tCAS
K
COLUMN
ADDRESS
t AWl
V,.
WE
~
V,L
'ewL
-twcs-
_ t WCH -
/
tw,
twCR
I-®'os- I-'o.®-V,.
D'N
K
XG)®
VIL
,
tOHR
"oUT
HIGH
IMPEDANCE
VOH
VOL
READ·MODIFY·WRITE CYCLE
IRwe
1-,..-1
"RW
0)
f)tcRP-J
--fi
'.SRiADDRESSES
~::
1
®
!;--.tRCD
;--
(~)
~'A'
t~~
r--
)((1) AD~~SS J( )[ .:~~~;;
C~
1-i
IRCS
----I
te.w
~~ @
.i!
~"WL-:::!.-I
_t
teA.
CWL
K
tRWD
r-~~
few.
Ci}'Y
®
I-....
®'·'l
)£,)
teAO r:----toAO
vo.
Dour
Vo L
IMPEDANCE
VALID
®
'!J
(4)
HIGH
DATA IN
VAUO
DATA OUT
K
-
tOFF
®
NOTES: 1,2. VIH MIN and VIL MAX are reference levels for measuring timing of input signals.
3,4. VOH MIN and VOL MAX are reference levels for measuring timing of DoUT .
measured to lOUTS IILaI.
5. ,t OFF
6. t DS and tDH are referenced to CAS or WE, whichever occurs last.
.
7. t CRP requirement is only applicable for RASlCAS cycles preceeded by a CAS'only cycle (i.e., for systems where CAS
has not been decoded with FiAS).
8. Either tRCH or tRRH must be satisfied.
is
3·271
inter
2164A FAMILY
WAVEFORMS
RAS·ONLY REFRESH CYCLE
\------------'''--------------1
1 - - - - - " " - - - - - 111
RAs
ADDRESSES
Dour
V'" _ _"""''''''-I
V 1l
(1)
,~
r--"'---='
Jlf
~
~I: _-9
X:~':D~'....:.:A;;;D"O"''i,W;;;ES;:;.S_~l(~--------------------------
-
®
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _....",~:::",,""""---------------~~
IMPEDANCE
VOL
HIDDEN REFRESH CYCLE
ADDRESSES
v,"
V"
WE
v,"
v"
®
Vo"
""
~''''
j,,?!~~---------VA-l-I~!OATA
DOUT
vo,
~;;"
_I.::!!
~,-~-----------'11'------,----_1
NOTES: 1,2.
3,4.
5.
6.
7.
VIH MIN and VIL MAX are reference levels for measuring timing of input s'ignals.
VOH MIN ar.ld VOL MAX are reference levels for measuring timing of DOUT .
tOFF is measured to lOUTS IILOI.
tos and tOH are referenced to CAS or WE, whichever occurs last.
tCAP requirement is only applicable for RASICAS cycles preceeded by a CAS·only cycle (i.e., for systems where CAS
has not been decoded with RAS).
8. Either tACH or tAR~ must be satisfied.
3-272
2164A FAMILY
D.C. AND A.C. CHARACTERISTICS, PAGE MODE [6,7,11]
TA = O°C to 70°C, Voo= 5V ± 10%, VSS = OV, unless otherwise noted.
Symbol
t pc
2164A·15
Min.
Max.
Parameter
125
145
30
Page Mode Read or Write Cycle
Page Mode Read Modify Write
O""AS Precharge Time, Page Cycle
~AS Pulse Width, Page Mode
O""AS Pulse Width
tpCM
tcp
tRPM1
tCAS
170
195
40
Unit
Notes
10000
10000
ns
ns
ns
ns
ns
40
35
mA
8
2164A·15
S6493
Min.
Max.
2164A·20
S6494
Min.
Max.
Unit
Notes
75000
75000
85
Voo Supply Current Page Mode,
Minimum tpc, Minimum tCAS
1004
2164A·20
Min.
Max.
10000
10000
120
EXTENDED PAGE MODE[11,12]
Symbol
Parameter
RAS Pulse Width, Extended Page Mode
tRPM2
ns
WAVEFORMS
PAGE MODE READ CYCLE
1--------------~tRPM----------__.j
_ V 1HC
RAS
JlE
V 1HC
-+_...J
vlL _ _
- ..- - - - - - t R A c
V OH
DOUT
Vrn
('Of
---~
----------~
NOTES: 1,2.
3,4.
5.
6.
7.
8.
9.
'CAcl~ ~
-o-_'O_ff_____
VIH MIN and VIL MAX are reference levels for measuring timing of input signals.
VOH MIN and VOL MAX are reference levels for measuring timing of 00UT'
tOFF IS measured to 10UT:5\I LO \'
All voltages referenced to Vss.
A.C. characteristic assume tT = 5 ns.
See the typical characteristics section for values of this parameter under alternate conditions.
t CAP requirement is only applicable for RAS/CAS cycles preceeded by a CAS'only cycle (i.e., for systems where CAS
has not been decoded with RAS).
10. Either tACH or tRAH must be satisfied.
11. All previously specified A.C. and D.C. characteristics are applicable.
12. For extended page :node operation, order 2164A·15 S6493, 2164A-20 S6494.
3-273
2164A FAMILY
WAVEFORMS
PAGE MODE WRITE CYCLE
ADDRESSES V IH
V'L--~~r-~~~~--~------,r---L~~--~~----+---~~~~tT~~~----~H------------
WE
V 1HC
VIL------;-----tf~~--_t----------_+~------~----------~~--_t~------_+------+_-----------
PAGE MODE READ·MODIFY·WRITE CYCLE
ADORESSFS
Wi'
v,"
v"
v,"
v"
\OH
Dour VOL
NOTES: 1,2.
3,4.
5.
6.
7.
HIGH
IMPEDANCE
V,H MIN and V,L MAX are reference levels for measuring timing of input signals.
VOH MIN and VOL MAX are reference levels for measuring timing of DouT .
tOFF is measured to lOUTS IILOI.
IDS and tDH are referenced to CAS or WE, whichever occurs last.
t CRP requirement is only applicable for RAS/CAS cycles preceeded by a CAS·only cycle (Le., for systems where CAS
has not been decoded with ~).
3-274
inter
2164A FAMILY
TYPICAL SUPPLY CURRENT WAVEFORMS
RAS·ONLY REFRESH
- ::1
CAS
V1H
WE
V1H
VIL
VIL
120
100
1\
80
It
lUI
(mA)
40
I.
200
400
600
I
"
IV
-LJ
.J
800
400
200
1000
TIME (ns)
600
TIME (ns)
LONG RAS/CAS
RAS
CAS
WE
~I
VIL
120
100
80
n
(mA)
'VI
40
Jt
200
400
600
800
1000
1200
1400
1600
1800
TIME (ns)
Typical power supply waveforms vs. time are
shown for the RAS/CAS· timings of Read/Write,
Read/Write (long RAS/CAS), and RAS-only refresh
cycles. IDD current transients at the RAS and CAS
edges require adequate decoupling of these supplies.
The effects of cycle time, VDD supply voltage and
ambient temperature on the IDD current are shown
in graphs included in the Typical.Characteristics
Section. Each family of curves for IDD1, IDD2' and
IDD3 is related by a common point at VDD = 5.0V
and TA = 25·C for tRAS =150 ns and tRC = 260 ns.
The typicallDD current for a given condition of cycle time, VDD and TA, can be determined by combining the effects of the appropriate family of '
curves.
3-275
intJ
2164A FAMILY
TYPICAL CHARACTERISTICS
GRAPH 2
TYPICAL ACCESS TIME
IRAe (NORMALIZED) 's.
AMBIENT TEMPERATURE
GRAPH 1
TYPICAL ACCESS TIME
lRAe (NORMALIZED) .s. V••
GRAPH 3
TYPICAL OUTPUT
SOURCE CURRENT
IOH VB. OUTPUT VOLTAGE VOH
1.2
1.2
......
>"1.1
1.1
~
:;!
"
l1.0
!
:;.
gO.9
~'
100
~ t-....
/
/"'"
!;;60
~
'/
......
TA=~5'C
\
Voo=50V
~
"~40
"" '"
"-
~
Voo =5.DV
0.8
\
1
"U60
w
TA=25°
J
V
~ 20
0.8
j
0.7
4.0
4.5
5.0
5.5
V•• - SUPPLY VOLTAGE IV)
0.7
B.O
o
GRAPH 4
TYPICAL STANDBY CURRENT
1001 VI Voo
40
20
60
80
-
--
1
VOH
GRAPHS
TYPICAL STANDBY CURRENT
1••, .s. AMBIENT TEMPERATURE
GRAPHB
TYPICAL OUTPUT
SINK CURRENT
IOL VI. OUTPUT VOLTAGE VOL
r--- t---
~
1.5
B.O
~ i---
o
20
40
60
60
o
TA - AMBIENT TEMPERATURE ('C)
GRAPH 7
TYPICAL OPERATING CURRENT
IDD2 VI. Voo
/
/
/
o
GRAPHS
TYPICAL OPERATING CURRENT
IOD2 va. lltAc
IRe
1000 n.
1
40
:1
30
TA=J5'C
Voo =5.0V
VOL ,- OUTPUT VOLTAGE (V)
GRAPH 8
TYPICAL OPERATING CURRENT
1••2 .s. AMBIENT TEMPERATURE
50
3
OUTPUT VOLTAGE (V)
I
TA =25°C
45
5.0
5.5
V•• - SUPPLY VOLTAGE IV)
-
100
VoD =5.0Y
1.5
4.0
o
""'- ~
TA - AMBIENT TEMPERATURE ('C)
4.0
4.0
o
500 ns
333 n.
250 ns
50
60
1-
zw
t RC
L280ns
t RC
~330 ns
tHAS =150
n.
Voo= 5.0V
IAC~500 ns
"u
~
~2O
..",
lAC =1000 ns
IRe
~ 1000 ns
!!
.E 10
T=25°C
VDO = 5.DV
o
0
4.0
4.5
5.0
5.5
V•• - SUPPLY VOLTAGE (V)
8.0
o
20
40
60
TA - AMBIENT TEMPERATURE ('C)
3-276
60
O~----~----~----~--~
1
3
o
CYCLE RATE (lilAC) MHz
inter
2164A FAMILY
TYPICAL CHARACTERISTICS
GRAPH 10
TYPICAL RAil-ONLY
REFRESH CURRENT
IDD3 VI. VDD
'1003
GRAPH 12
TYPICAL RAS·ONLY
REFRESH CURRENT
IDD3 vs. 1/tRC
GRAPH 11
TYPICAL O§.ONLY
REFRESH CURRENT
YS. AMBIENT TEMPERATURE
I RC
1000 ftS
50..---,---,---,---,
VDD = 5.0V
oS
40
ffi
i
B
30
8:
20
1----+---1---1----;
/---+-::==--t===:::""".-!-=.:=---l
~
/--""F'----t---"""r=:":='--l
ill,
o L - _ - L_ _
4.0
4,5
~
__
5.0
L-_~
5.5
Voo - SUPPLY VOLTAGE (V)
6.0
:c
:C4O
oS
ns
!Z
AC!33;"S
ex:
u
tAC = 280
B
t
~ 30
~
ill,
J
20
40 _--;---1-----11---""1
~ 30 1_--;---1-----11---;;;;..;
"~
8:
lAC _500 ns
I 1000 ns
IRC
02040
~
TA - AMBIENT TEMPERATURE ('C)
DEVICE DESCRIPTION
The Intel 2164A is produced with HMOS-D III, a
high performance MOS technology which incorporates redundant elements. This process, combined with new circuit design concepts, allows the
2164A to operate from a single + 5V power supply,
eliminating the + 12V and - 5V requirements. Pin
1 is not connected, which allows P.C.B. layout for
future higher density memory generations.
The 2164A is functionally compatible with the
2118, the industry standard 5V-only 16-pin 16K
dynamic RAM. This allows simple upgrade from
16K to 64K density merely by adding one additional multiplexed address line.
RASICAS Timing
RAS and CAS have minimum pulse widths as
defined by tRAS and teAs respectively. These
minimum pulse widths must be maintained for
proper device operation and.2!!a integr!!LA cycle, once begun by bringing RAS and/or CAS low,
must not be ended or aborted prior to fulfilling the
minimum clock Signal pulse width(s). A new cycle
can not begin until the minimum precharge time,
tRP, has been met.
Read Cycle
A Read ~Ie is performed by maintaining Write
Enable (WE) high during a RAS/CAS operation. The
20
1----+---t:.fP""--II----1
ill
a
~101_~~~-1----I1_-""1
10
o
250 ns
oS
ffi
8:
333 ns
T=25°C
VDD =5.0V
tAAS=1 150 ns
:c
500 "8
50
50
~
1
2
3
CYCLE RATE (11IRC) MHz
output pin of a selected device will remain in a
high ,impedance state until valid data appears at
the output at access time.
Write Cycle
A Write cycle is performed by taking WE low during a RAS/CAS operation. Data Input (DIN must be
valid relative to the negative edge of WE or CAS,
whichever transition occurs last.
Refresh Cycles
There are 512 sense amplifiers, each controlling
128 storage cells. Thus, the 2164A is refreshed in
128 cycles. Any com~ination of the seven (7) low
order Row Addresses RAo through RAs, will select
two rows of data cells (256 cells/row). Row address
7 is not critical during a refresh operation and can
be either high or low. Although any cycle, Read,
Write, Read-Modify-Write, or i=iAS-only, wi!! refresh
the memory, the RAS-only cycle is recommended,
since it anows about 20% system power reduction
over the other types of cycles.
Hidden Refresh
A standard feature of the 2164A is that refresh
cycles may be performed while maintaining valid
data at the output pin. This is referred to as Hidden
Refresh. Hidden Refresh is performed by holding
CAS at V1L and taking RAS high and, after a
specified precharge period (tRP), executing a
3-277
inter
2164A FAMILY
"RAS-Only" refresh cycle, but with CAS held low
(see figure below)_
is recommended that RAS and CAS track with Voo
during power on or be held at a valid VIH.
Von RISE TIME", 10/,$
~~~ Cd I
Dour
!\
I \.
I
/
II
----'r-
H1GHZ
(
-=-=---<'-____
D_AT_A_ _ _
'--
This feature allows a refresh cycle to be "hidden"
among data cycles without affecting the data availability. The part will be internally refreshed at the
row addressed at the time of the second RAS. .
10
Von RISE TI!\I1E::: 100"S
I ~~:kP]
/
RiS= Voo
CASr=VOD
20
30
RAS=Voo
CAST Voo
J
40
./
50
TlME(ps)
100
150
200
TlME(ps)
Figure 1_ Typical 100 vs_ Voo During Power Up
Data Output Operation
Page Mode Operaticm
The 2164A Data Output (DOUT), which has threestate capability, is controlled by CAS. During CAS
high state (CAS at VIH), the output is in the high impedance state. The following table summarizes
the DouT state for various types of cycles.
Page Mode operation allows additional columns
of the selected device to be accessed at the common row address set. This is done by maintaining
RAS low while successive CAS cycles are performed.
.
Intel® 2164A Data Output Operation
for Various Types of Cycles
Type of Cycle
~ead
Cycle
Early Write Cycle
RAS-Only Refresh Cycle
CAS-Only Cycle
Read-Modify-Write Cycle
Delayed Write Cycle
DOuTState
Data from Addressed
Memory Cell
Hi-Z
Hi-Z
Hi-Z
Data from Addressed
Memory Cell
Indeterminate
Power On
An initial pause of 500,..s is required after the application of the Voo supply,. followed by a minimum
of eight (8) initialization cycles (any combination
of cycles containing a RAS clock such as RAS-only
refresh). 8 initialization cycles are required after
extended periods of hias (greater than 2 ms) without clocks. The.Voo current (100) requirement of
the 2164A during power on, is however, dependent upon the input levels of RAS and CAS and the
rise time of Voo shown in F!gure 1.
If RAS = Vss during power on, the device may go
into an active cycle and 100 would show spikes
similar to those shown for the RAS/CAS timings. It
Page Mode operation allows a maximum data
transfer rate as Row addresses are maintained internally and do not have to be reapplied. During
this operation, Read, Write and Read-tv'!odify-Write
cycles are possible. Following the entry cycle into
Page Mode operation, access is tCAC dependent.
The Page Mode cycle is dependent upon CAS
pulse width (tCAS) and the CAS precharge period
(tcp)·
.
Extended
P~ge
Mode Operatio!1
An optional feature of the 2164A is extended page
mode operation whicn allows an entire page (row)
of data to be read or written during a single RAS
cycle. By providing a fast tpc and long RAS pulse
width (tRPM2), the 2164A-15 S6493 permits transfers
of large blocks of data, such as required by bitmapped graphic applications.
SYSTEM DESIGN CONSIDERATIONS
Ground and power Gridding
Ground and power gridding can contribute to excess noise and voltage drops. An example of an
unacceptable method is presented in Figure 2.
This type of layout results in accumulated transient noise and voltage drops for the device
located at the end of each trace (path).
3-278
inter
2164A FAMILY
l
5l
j I
I
\ I
\ I
\l
I
~
I
~
I
~
I
~
I
~
I
~
I
I
2164A\
I
2164A
~
2164A
..
\
~
~
2164A
VDO (+sV)
ditional inner layers to the PC board, noise and
supply voltage fluctuations are greatly reduced. If
power and ground planes are used, gridding is optional but typically used for increased reliability of
power and ground connections and further reduction of electromagnetic noise.
It is preferable on power/ground planes to use circular voids for device pins rather than slotted
v91ds (Figure 4). This provides maximum decoupling and minimum crosstalk between signal traces.
V,s (GND)
RECOMMENDED
NOT RECOMMENDED
Figure 2. Unacceptable Power Distribution
Transient effects can be minimized by adding ex·
tra circuit board traces in parallel to reduce inter·
connection inductance (Figure 3).
~
I
~
I
r
~
I
~
ql
I
~
I
~
I
I
I
2164A
2164A
~
I
\ I
~
~
~
I
2164A
Figure 4_ Recommended Voids for Multilayer
PC Boards
~
Power Supply Decoupling
~
I
I
~
2164A
~
• TWO SIDED CARD
- VERTICAL TRACES ON COMPONENT SIDE
- HORIZONTAL TRACES ON SOLDER SIDE
• MAINGROUND BUS OR INTERCONNECTION TO
TTL CONTROL, ADDRESS. DATA BUFFERS
Figure 3. Recommended Power Distribution
- GridC\ing
Power and Ground Plane
A better alternative to pQwer and gridding is power
and ground planes. Although this requires two ad-
For best results, decoupling capacitors are placed
on the memory array board at each memory location (Figure 5). High frequency 0.1 p.F ceramic
capacitors are the recommended type. Noise is
minimized because of the low impedance across
the circuit board traces. Typical VDD noise levels
for this arrangement are less than 300 mY.
A large tantalum capacitor (typically one 100 p.F
per 64 devices) is required at the circuit board
edge connector power input pins to recharge the
0.1 p.F capacitors between memory cycles.
For further details see application note (A.N.) #131,
2164A Dynamic RAM Device Description, or A.N.
#133, Designing Memory Systems for Microprocessor Using the Intel 2164A and 2118 Dynamic
RAMs.
3-279
2164A FAMILY
DECOUPLING
CAPACITOR
NOTE 1 FUTURE ADDRESS EXPANSION
NOTE" MEMORY DEVICE SPACING IS 0 425"
TRACES ARE 50 MIL
Figure 5. 2164A Memory Array PC Board Layout
3·280
2186
8192 x 8 BIT INTEGRATED RAM
• Low-cost, high-volume HMOS
technology
• Simple asynchronous refresh operationi
static RAM compatible
• High density one transistor cell
• 2764 EPROM compatible pin-out
• Single
+ 5V:i: 10% supply
• Two-line bus control
• Proven HMOS reliability
• JEDEC standard 28-pin site
.• Low active current (70 mAl
• Low standby current (20 mAl
The Intel 2186 is a 8192 word by 8-bit integrated random access memory (iRAM) fabricated on Intel's proven
HMOS dynamic RAM technology. Integrated refresh control provides static RAM characteristics at a significantly lower cost. Packaged in the industry standard 28-pin DIP, the 2186 conforms to the industry standard JEDEC 28-pin site. Designs based on 2186 timings can be made fully compatible with EPROMs and
static RAMs.
The 2186 is particularly suited for microprocessor applications and incorporates many requisite system
features including low power dissipation, automatic initialization, extended cycle operation and two-line
bus control to eliminate bus contention.
BLOCK DIAGRAM
ROW
ADDRESS
MULTIPLEXER
PIN NAMES
~A"
OE
WE
11°0.11°7
ROY
Vee
V.s
ADDRESS INPUTS
CHIP ENABLE
OUTPUT ENABLE
WRITE ENABLE
DATA INPUT/OUTPUT
READY
+5V POWER
GROUND
The follOWing are tradema'1<-s of Intel CorporatIOn and may be used only to describe Intel products Intel, CREDIT, Index, Inslte, InteHee, Library Manager, Megachas8ls,
Micromap, MULTI BUS, PROMPT, UPI, ,.Scope, Promware, MeS, ICE, IRMX, ISSC, ,sax, MULTIMODULE and les Intel CorporatIon assumes no responsibility for the use of any
circuitry other than circuitry embodied in an Intel product No other CirCUit patent licenses are implied
© INTEL CORPORATION, 1982
3-281
September 1982
Order Number: 210480-001
inter
2186 FAMILY
-COMMENT: Stresses above those listed under
"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
device reliability.
ABSOLUTE MAXIMlJM RATINGS*
Temperature Under Bias. . . . .. -10·C to + 80·C
Storage Temperature ....... -65·Cto + 150·C
Voltage on Any Pin with
Respect to Ground .......... - 1.0 V to + 7 V
D.C. Continuous Current per Output. . . . .. 10 mA
D.C. Maximum Data Out Current. . . . . . . .. 50 mA
D.C. Power Dissipation ................. 1.0 W
D.C. AND OPERATING CHARACTERISTICS(1)
TA=O·C to + 70·C, VCC= +5V± 10% unless otherwise noted.
Limits
Symbol
III
Mln_
Parameter
Max.
Unit
10
pA
Input Load Current (All Input Pins)
Test Conditions
IILOI
Output Leakage Current
" 10
,PA
ICC
Operating Current
70
mA
Minimum Cycle Time
ISB
Standby Current
20
mA
CE=VIH
VIL
Input Low Voltage
-1.0
0.8
V
VIH
Input High Voltage
2.4
7.0
V
VOL
Output Low Voltage
VOH
Output High Voltage
0.45
2.4
Notes
VIH = VSS to VCC
OE=VIH
2
3
V
IOL=2.1 mA
V
10H= -1.0 mA
4
NOTES:
1. Typical limits are VCC= +5V. TA=25'C.
2. ICC is dependent on output loading when the device output is selected. Specified ICC max. is measured with the output open.
3. Specified Vil min. is for steady state operation. DUring transitions the inputs may overshoot to - 2.0V for periods not to exceed
20 nsec.
4. IOl for ROY is 10 mAo
A.C. TEST CONDITIONS
+5V
Input Pulse and Timing
Reference Levels. . . . . . . . . . . . . .. 0.8V to 2.4V
Input Ris'e and Fall Times .............. 10 nsec
Output Timing Reference Levels .. 0.45V and 2.4V
Output Load .................... See Figure 1
UK
DOUT
---..---+
lK
+5V
l00pF
(INCLUDING
SCOPE AND
JIG)
UK
DOUT - - - . - -...
Figure 1.
CAPACITANCE I51 •
1K
TA=25·C, f= 1.0 MHz
Figure 2.
Symbol
Parameter
Max.
Unit
Conditions
CADD
CliO
CIN
Address Capacitance
110 Capacitance
Control Capacitance
8
14
14
pF
pF
pF
VADD=OV
VI/O=OV
VIN=OV
NOTE: 5. ThIs parameter
IS
characterized and not 100% tested,
3-282
(FOR HIGH IMPEDANCE
MEASUREMENTS ONLy)
5pF
2186 FAMILY
A.C. CHARACTERISTICS
+ 70·C, VCC= + 5V ± 10% unless otherwise noted.
TA= o·c to
READ CYCLE (WE
=VIH)
Symbol
2186·25
Max.
425
Parameter
Min.
TELEL
Cycle Time
TELOV
Access Time from CE
TELELR
Cycle Time with Refresh
TELOVR
Access Time from CE wlRefresh
TGLOV
Access Time from OE
TELEH
CE Pulse Width
40
TEHEL
CE High Time
40
TAVEL
Address Set-Up Time
TELAX
Address Hold Time
TGLEL
OE low to next CE low
TGLGH
OE Pulse Width
250
850
675
65
2186·30
Max.
500
300
1000
800
70
40
40
Min.
2186·35
Max.
600
Min.
Unit
Notes
ns
1
ns
1
ns
2
950
ns
2
75
ns
350
1200
40
ns
40
ns
0
0
0
ns
30
30
30
ns
250
275
65
70
300
75
ns
40
ns
TGHEL
OE high to next CE low
40
TGHOX
OE high to Data Float
10
60
10
60
10
60
ns
3
TELGL
CE low to OE low -
Pulse Mode
0
90
90
0
90
ns
4,5
TGLEH
OE low to CE high -
Long Mode
40
0
40
TELRL
CE low to RDY low
TRLRH
RDY Pulse Width
TRHOV
RDY high to Data Valid
TRHEL
RDY high to nei
ns
4
ns
6
ns
6
ns
ns
inter
2186 FAMILY
A.C. CHARACTERISTICS
T A = O·C to
+ 70 ·C, VCC = + 5V ± 10%
un less otherwise noted.
WRITE CYCLE (OE = VIH)
TELEL
Cycle Time
2186·25
Min. Max.
425
TELELR
Cycle Time with Refresh
850
1000
1200
TELEH
CE Pulse Width
40
40
40
ns
TEHEL
CE High Time
40
40
40
ns
TAVEL
Address Set·Up Time
TELAX
Address Hold Time
TWLEL
WE low to next CE low
TWLWH
Symbol
Parameter
2186·30
Min. Max.
2186·35
Min. Max.
500
600
ns
ns
Unit
a
a
a
ns
30
30
30
ns
250
300
350
ns
WE Pulse Width
40
40
40
ns
TWHEL
WE high to next CE low
40
40
40
ns
TDVWL
Data Set·Up to WE low
a
a
a
ns
40
45
TWLDX
Data Hold from WE low
TELWL
CE low to WE low -
Pulse Mode
a
TWLEH
WE low to CE high -
Long Mode
40
TELRL
CE low to RDY low
TRLRH
RDY Pulse Width
100
100
100
ns
TRHEL
RDY high to next CE low
250
275
350
ns
90
a
50
90
40
50
a
ns
90
40
60
70
ns
4
ns
6
6
WAVEFORMS
---+------. i---;:;~~;::;~=::::+
AD DR
DATA
IN::~J::~~~~~~~~:::=
TDVWL
WRITE CYCLE WITH REFRESH
WE(W)
---t-------.
DATA IN ------«(D.DA;iTrAA:"Vv:;\AuL'DD).)------3·284
4,5
ns
WRITE CYCLE
WE (E"j
Notes
1
2
2186 FAMILY
A.C. CHARACTERISTICS
TA = o·C to
+ 70·C, VCC= + 5V ± 10% unless otherwise noted.
FALSE MEMORY CYCLE (OE and WE =VIH)
Symbol
TELEL
Parameter
Cycle Time
,
2186·25
Min. Max.
425
2186·30
Max.
Min.
500
1000
40
TELELR
Cycle Time with Refresh
TELEH
CE Pulse Width
850
40
TEHELF
CE High Time for F.M.C.
200
250
TAVEL
Address Set·Up Time
0
0
10000
10000
2186·35
Max.
Min.
600
1200
Unit
Notes
1
ns
ns
2
7
275
ns
8
0
ns
40
ns
10000
TELAX
Address Hold Time
TELRL
CE low to ROY low
ns
6
TRLRH
ROY Pulse Width
100
100
100
ns
6
TRHEL
ROY high to next CE low
250
275
350
ns
30
30
30
50
60
ns
70
WAVEFORMS
FALSE MEMORY CYCLE
......---TElEHI---;t:::~~~~
TElAX
ADDR~~_______________________
X====
FALSE MEMORY CYCLE WITH REFRESH
NOTES:
1. TELEL TELGL max
+ TGLEH mm or TELEH> TELWL max + TWLEHmin.
5. For Long Mode TELGL max and TELWL max = 10 ~sec.
6. C RDy .<100 pF and REXT =5101l.
7. False Memory Cycles Only.
8. Note TEHELF > TEHEL.
3·285
2186 FAMILY
FUNCTIONAL DESCRIPTION
The 2186 has three control pins: CE (Chip Enable),
nal access and internal refresh cycle requests. The
internal timer period is specified as 24 JLsec. ± 50%.
OE (Output Enable), and WE (Write Enable). An
open-drain output pin called RDY indicates if refresh is occurring during an access request. ROY
will only respond when the 2186 has been selected
by CE going active low during a refresh cycle.
The 2186 may also be refreshed by performing
Read, Write, or False Memory cycles on all 128
rows (AO through A6) within a two millisecond
period.
Cycles are iflitiated by latching addresses into the
2186 with the leading (falling) edge of CEo When
CE goes active during internal refresh, the RDY pin
is pulled low signaling a delay. RDY remains low
until shortly before both refresh and access (Read/Write) cycles are complete.
EXTENDED
On-chip control circuitry tracks all operations for
nearly transparent refresh. A high-speed on-chip
arbitration circuit prevents conflicts from occurring between refresh and access cycles.
Access Cycles
READ CYCLE
A read cycle is initiated by CE and OE both going
active low during the same cycle. CE may be either
pulsed to initiate a cycle or held active low
throughout the cycle. ~ is a logic level; ~ controls the 2186 data output bus. Access times are
specified from both OE and CEo Data r~mains on
the data bus until OE returns inactive (high) independent of CE. WE may not go active during a
Read cycle.
WRITE CYCLE
A Write cycle is initiated by CE and WE going active low during the same cycle. CE may be a pulse
or a logic level. WE leading edge latches data from
the data pus into the 2186. OE may not go active
during a Write cycle.
FALSE MEMORY CYCLE (FMC)
A False Memory cycle is initiated by CE going active without either OE or WE going active. No
memory cycle will be performed. Note that address set-up and hold times must be observed for
False Memory cycle operation.
Operating Modes
REFRESH OPERATION
Refresh is totally automaticand requires no external stimulas. All refresh functions are controlled
internally.
,A high-speed arbitration circuit will resolve any potential conflict arising between simultaneous exter-
CYC~E
OPERATION
Extended cycle operation is defined as holding OE
or WE valid (low) for indefinite periods. (CE is allowed to return high.) Data will remain valid on the
bus as long as OE is valid. WE latches data on the
leading (falling) edge. Automatic refreshes will
continue to be performed as needed, even while
OE or WE is held low; RDY will not respond during
these extended cycle refreshes.
INITIALIZATION
To guarantee initialization, all control inputs must
be inactive (high) for a 100 microsecond period after
Vce is within specification. No extra cycles are re,
quired before normal operation may begin.
Interfacing Considerations
The 2186 is an edge enabled RAM. Below is an illustration of a simple interface for connecting microprocessors with edge enable memories. A
stable CE clock is necessary to avoid accidentally
selecting the RAM. Generally, stable select signals are desirable in all types of microsystem applications. Most common decoding circuits allow
addresses to flow directly through the decoder
(i.e. decoder permanently "enabled"). This technique may allow false decoder outputs to occur
when addres~es are in transition. This may result
in false CE signals and potentially, invalid memory
requests. A simple gating circuit will inhibit enabling the decoder until addresses are valid at the
decoder inputs.
Another interfacing consideration is the relationship between WE and valid data. The 2186 performs a write operation on the leading edge of WE.
In a minimum mode 8088 or 8086 system, WE occurs before data is valid. The cross-coupled NAND
gate configuration shown below on the WR signal
will preyent this from occurring. This implementation also guarantees valid data on the rising (trailing) edge of WE to maintain compatibility with fully
static RAMs. (For maximum mode 8088 or 8086
operation, the control signal MWTC directly from
the 8288 bus controller serves the same function.)
For a more detailed description of designing iRAM
3-286
2186 FAMILY
systems, refer to Intel App. Note #132 on "Designing Memory Systems with the BK x BiRAM"
the 2186 application, a trace should be run from
pin 1 of each socket location to the ROY input of
either the microprocessor or clock generator.
Also, a provision for a pull-up resistor to Vee is
needed.
Layout Considerations
To ensure compatibility with other 28·pin memory
devices such as EPROMs, several pins require
close examination; specifically, pins number 1, 26
and 27. Following is a discussion of the system
level operation and the design considerations for
.
these pins.
PIN #26
While pin 26 is a No Connect for both the 2186 or
the '2764 EPROM, a trace to pin 26 from Vee will
guarantee compatibility between 24 pin and 28 pin
EPROMs. Pin 26 will carry the additional address
bit required to future higher density memories. For
flexibility, provide a jumper for an address bit
and/or Vee on pin 26.
PIN #1
Pin 1 on all EPROMs is reserved fonhe high voltage programming bias, Vpp. EPROMS are usually
programmed external to the system. Therefore, in
normal system operation, pin 1 is connected to Vee.
PIN #27
Pin 1 on the 2186 is the microprocessor handshake
signal, ROY. The ROY signal may be bussed to the
ROY input of either the, microprocessor or clock
generator. Because ROY is an open drain output,
all 2186 ROY signals may be "wire OR'd" with any
other ROY signals in the system. A 510 ohm pullup resistor is required between ROY and Vee. For·
Pin 27 is labelled WE on the RAM and PGM on the
EPROM. While WE is a system level control signal,
PGM is only used when programming the EPROM
(Vpp at + 21V). PGM may be allowed to toggle during normal EPROM operation (Vpp at + 5V). There·
fore, WE may be bussed to every socket location
with no jeopardy of illegal operation.
IRAM
,------------,
INTERFACE
I
,--------,r-----~J
I
I
I
I
JjD
8068
ALE I--~--r-",
8284A
101M
elK
ROY
RDY
ADo·AD15
Vee
12000
3-287
2186/8088 MIN.MODE
8203
64K DYNAMIC RAM CONTROLLER
• Provides ~II Signals Necessary to
Control 64K (2164) and 16K (2117, 2118)
Dynamic Memories
• Fully Compatible with Intel® 8080A,
~085A, iAPX'88: an,d iAPX 86 Family Microprocessors
.
• Directly Addresses and Driv.es Up to 64
Devices Without External Drivers
• Provides System Acknowledge and Transfer Acknowledge Signals
• Provides Address Multiplexing and
Strobes
• Provides a Refresh Timer and a Refresh
Counter
• Provides Refresh/ Acces~ Arbitration
• Internal Clock Capability with the 8203-1
and the 8203-3
• Refresh Cycles May be internally or Externally Requested (For Transparent Refresh)
'. Internal Series Damping Resistors on
RAS, CAS and WE Outputs
• Available in EXPRESS
-Standard Temperature Range
The Intel® 8203 is a. Dynamic Ram System Controller delligned to provide all signals necessary to use 2164, 2118
or 2117 Dynamic RAMs in microcomputer systems. The 8203 provides multiplexed add~esses ancj address
strobes, refresh logic, refresh/access arbitration. Refresh cycles can be started internally or externally. The
8203-1 and the 8203-3 support Advanced-Read mode and an internal crystal oscillator. The 8203-3 is a ±5%
Vee part.
,
-
_ IS
.......AH,
AH,
AHa
.
....
........
m,
Iifi:=====:::r~
~
~--------~
Oil
...
....
I'IEFAQ/ALE ------~--_t
M •
AL,
M,
AL,
M,
ALa
M,
.....
liii!i
iIU'I',
....
M.
"""
Figure 1. 8203 Block Diagram
Intel Corporation Assumes No Responsibility
@INTELCORPORATION. 1982
Figure 2. Pin Configuration
ior the Use of Any Circuitry Other Than Circuitry Embodied
3-288
In
an Intel
Product No Other CirCUit Patent LtcenS9S are Implied
JULY 1982
ORDER NUMBER: 21044-002
inter
8203
Table 1. Pin Descriptions
Symbol
Pin
No. Type
ALa
ALI
AL2
AL3
AL4'
AL5
AL6
Pin
No. Type Name and Function
Name and Function
Symbol
6
8
10
12
14
18
18
Address Low: CPU address inputs used to generate memory
row address.
RASa
RASI
RAS21
OUT7
RAS3/BO
21
22
23
0
0
0
26
I/O
AHa
AHI
AH2
AH3
AH4
AH5
AH6
5
4
3
2
1
39
38
Address High: CPU address inputs used to generate memory
column address.
XACK
29
0
Transfer Acknowledge: This
output is a strobe indicating valId data during a read cycle or
data wntten dUring a wnte cycle.
XACK can be used to latch valid
data from the RAM array
BO/AL7
Bl /OP l l
AH7
24
25
Bank Select Inputs: Used to
gate the appropriate RAS output
for a memory cycle. Bl/OPl option used to select the Advanced
Read Mode. (Not available in
64K mode.) See Figure 5.
When in 64K RAM Mode, pins 24
and 25 operate as the AL 7 and
AH7 address inputs.
SACK
30
0
PCS
33
System Acknowledge: ThiS
output indicates the beginning of
a memory access cycle It can
be used as an advanced transfer acknowledge to eliminate
wait states (Note: If a memory
access request IS made during a
refresh cycle, SACK is delayed
un"l XACK In the memory access cycle).
I/O
I/O
Oscillator Inputs: These inputs
are deSigned for a quartz crystal
to control the frequency of the
oscillator If XO/OP2 is shorted
to pin 40 (Vec) or if XO/OP2 is
connected to + 12V through a
1Kf! resistor then XII CLK becomes a TTL input for an external clock. (Note: Crystal mode
for the 8203- 1 and the 8203-3
only)
I
Mode Select: This input selects
'16K mode (2117, 2118) or 64K
mode (2164). Pins 23-26
change func"on based on the
mode of operation.
I
Protected Chip Select: Used to
enable the memory read and
write inputs. Once a cycle is
started, it will not abort even if
PCS goes Inactive before cycle
completion.
XO/OP2
Xl /CLK
36
. 37
Row Address Strobe: Used to
latch the Row Address into the
bank of dynamic RAMs, selected by the 8203 Bank Select pins
(BO, B 11 OP 1) In 64K mode,
only RASa and RAS 1 are available; pin 23 operates as OUT7
and pin 26 operates as the BO
bank select input.
WR
31
I
Memory Write Request,
RD/SI
32
I
Memory Read Request: SI
functiqn used in Advanced Read
mode selected by OPI (pin 25).
REFRQI
ALE
34
I
External Refresh Request: ALE
function used in Advanced Read
mode, selected by OP 1 (pin 25)
16K/64K
35
OUTO
OUTI
OUT2
OUT3
OUT4
OUT5
OUT6
7
9
11
13
15
17
19
0
0
0
0
0
0
0
Output of the Multiplexer:
These outputs are designed to
drive the addresses of the Dynamic RAM array. (Note that the
OUTO-7 pins do not require inverters or drivers for proper operation.)
VCC
40
Power Supply: +5V
GND
20
Ground.
WE
28
0
Write Enable: Drives the Write
Enable inputs of the Dynamic
RAM array.
CAS
27
0
Column Address Strobe: This
output is used to latch the Column Address into the Dynamic
RAM array.
Functional Description
The 8203 provides a complete dynamic RAM controller for microprocessor systems as well as\expansion
memory boards, All of the necessary control signals
are providedfor2164, 2118and 2117 dynamic RAMs.
The 8203 has two modes, one for 16K dynam ic RAMs
and one for 64Ks, controlled by pin 35.
3-289
AFN.()2144B
8203
Other Option Selections
I-I
cs=l=
I
I
I
CAS
I:::l
1KU
• 5%
RASQ
XI
":"
68011
+5%
CI!.l,
T
I
-I'
8203~1
or
RAS1
8203-3
RAS2
RASa
":"
Cs·
The 8203 has three strapping options. When OP 1 is selected (16K mode only), pin 32 changes from a RD input to
an S 1 input, and pin 34 changes from a REFRQ input to an
ALE input. See "Refresh Cycles" and "Read Cycles" for
more detail. OP 1 is selected by tying pin 25 to + 1~V
through a 5.1 K ohm resistor on the 8203-1 or 8203-3
only.
WE
Xo
XACK
10pF
FUNDAMENTAL XT Al
When OP2 IS selected, the internal oscillator is disabled
and pin 37 changes from a crystal input (X 1) to a CLK
Input for an external TTL clock. OP2 is selected by shortIng pin 36 (XO IOP2) directly to pin 40 (VCC). No current
limiting resistor should be used OP2 may also be selected
by tYing pin 36 to + 12V through a 1Kf! resistor.
SACK
Figure 3. Crystal Operation for the 8203-1 and
8203-3
All 8203 timing is generated from a single reference clock.
ThiS clock is provided via an external oscillator or an onchip.crystal oscillator. All output signal transitions are synchronous with respect to this clock reference, except for
the trailing edges of the CPU handshake signals SACK and
XACK.
Refresh Timer
The refresh timer is used to monitor the time since the last
refresh cycle occurred. When the appropriate amount of
time has elapsed, the refresh timer will request a refresh
cycle. External refresh requests will reset the refresh
timer.
CPU memory requests normally use the RD and WR inputs. The Advanced-Read mode allows ALE and S 1 to be
used in place of the RD input.
Refresh Counter
The refresh counter is used to sequentially refresh all of
the memory's rows. The 8-bit counter is incremented after
every refresh cycle.
Failsafe refresh is provided via an internal timer which generates refresh requests. Refresh requests can also be
generated via the REFRQ input.
An on-chip synchronizer I arbiter prevents memory and refresh requests from affecting a cycle in progress. The
READ, WRITE, and external REFRESH requests may be
asynchronous to the 8203 clock; on-chip logic will synchronize the requests, and the arbiter will decide if the requests should be delayed, pending completion of a cycle in
progress.
Pin #
16K Function
64K Function
23
24
25
26
RAS2
Bank Select (BO)
Bank Select (B 1)
RAS3
Address Output (OUT7)
Address Input (AL 7)
Addresf\lnput (AH7)
Bank Select (BO)
Figure 4. 16K/64K Mode Selection
16K/64K Option Selection
Outputs
Inputs
Pin 35 is a strap input that controls the two 8203 modes.
Figure 4 shows the four pins that are multiplexed. In 16K
mode (pin 35 tied to VCC or left open), the 8203 has two
Bank Select inputs to select one of four RAS outputs. In
this mode, the 8203 is exactly compatible with the Intel
8202A Dynamic RAM Controller. In 64K mode (pin 35 tied
to GND), there is only one Bank Select input (pin 26) to
selecrthe two RAS outputs. More than two banks of 64K
dynamic RAM's can be used with external logic.
16K
Mode
64K
Mode
RASO RAS1 RAS2 RAS3
B1
BO
a
a
a
a
1
a
1
1
a
1
a
1
-
-
a
-
-
1
1
a
1
·1
1
1
-
a
a
1
1
1
1
1
1
1
1
Figure 5_ Bank Selection
Description
Pin #
Normal Function
B1/0P1 (16Konly)/AH7
25
Bank (RAS) Select
Advanced-Read Mode (see text)
XOIOP2
36
Crystal OSCillator (8203-1 and 8203-3) .
External OSCillator
Option Function
Figure 6_ 8203 Option Selection
3-290
AFN-02144B
intel·
8203
Address Multiplexer
Refresh Cycles
The address multiplexer takes the address inputs and the
refresh counter outputs, and gates thell] onto the address
outputs at the appropriate time., The address outputs, in
conjunction with the RAS and CAS outputs, determine the
address used by the dynamic RAMs for read, write, and
refresh cycles. During the first part of a read or write cy- .
cle, ALO-AL7 are gated to OUTO-OUT7, then AHO-AH7
are gated to the address outputs.
The 8203 has two ways of providing dynamic RAM
refresh:
During a refresh cycle, the refresh counter is gated onto
the address outputs. All refresh cycles are RAS-only refresh (CAS inactive, RAS active).
Both types of 8203 refresh cycles activate all of the RAS
outputs, while CAS, WE, SACK, and XACK remain
inactive.
Internal refresh is generated by the on-Chip refresh timer.
The timer uses the 8203 clock to ensure that refresh of all
rows of the dynamic RAM occurs every 2 milliseconds
(128 cycles) or every 4 milliseconds (256 cycles). If
REFRQ is inactive, the refresh timer will request a refresh
cycle every 10-16 microseconds.
To minimize buffer delay, the .information on the address
outputs is inverted from that on the address inputs.
aUTO-OUT 7 do not need inverters or buffers unless additional drive is required.
Synchronizer / Arbiter
The 8203 has three inputs, REFRQ/ ALE (pin 34), RD (pin
32) and WR (pin 31). The RD and WR inputs allow an external CPU to request a memory read or write cycle, respectively. The REFRQ/ ALE input allows refresh requests
to be requested external to the 8203.
External refresh is requested via the REFRQ input (pin 34).
External refresh control is not available when the Advanced-Read mode IS selected. External refresh requests
are latched, then synchronized to the 8203 clock.
The arbiter will allow the refresh request to start a refresh
cycle only if the 8203 is not in the middle of a cycle.
When the 8203 is in the idle state a simultaneous memory
request and external refresh request will result in the memory request being honored first. This 8203 characteristic
can be used to "hide" refresh cycles during system operation. A circuit similar to Figure 7 can be used to decode
the CPU's instruction fetch status to generate an external
refresh request. The refresh request is latched while the
8203 performs the instruction fetch; the refresh cycle will
start immediately after the memory cycle is completed,
even if the RD input has not gone inactive. If the CPU's
Instruction decode time is long enough, the 8203 can complete the refresh cycle before the next memory request is
generated.
All three of these inputs may be asynchronous with respect to the 8203's clock. The arbiter will resolve conflicts
between refresh and memory requests, for both pending
cycles and cycles in progress. Read and write requests
will be given priority over refresh requests.
System Operation
The 8203 is always in one of the following states:
a)
b)
c)
d)
e)
1) Internal (failsafe) refresh
2) External (hidden) refresh
IDLE
TEST Cycle
REFRESH Cycle
READ Cycle
WRITE Cycle
If the 8203 is not in the idle state then a simultaneous memory request 'and an external refresh request may result in
the refresh request being honored first.
The 8203 is normally in the IDLE state. Whenever one of
the other cycles is requested, the 8203 will leave the IDLE
state to perform the desired cycle. If no other cycles are
pending, the 8203 will return to the IDLE state.
SO~~REFRa
Test Cycle
8085A
The TEST Cycle is used to check operation of several
8203 inte'rnal functions. TEST cycles are requested by activating the PCS, RD and WR inputs. The TEST Cycle will
reset the refresh address counter and perform a WRITE
Cycle. The TEST Cycle should not be used in normal system operation, since it would affect the dynamic RAM refresh.
S1
8203
'--_________
~:;K
or
Figure 7. Hidden Refresh
3-291
AFN-02144B
8203
Write Cycles
Certain system configurations require complete external
refresh requests. If external refresh is requested faster
than the minimum internal refresh timer (tREF), then, in effect, all refresh cycles will be caused by the external refresh request, and the internal refresh timer will never
generate a refresh request.
Write cycles are similiar to Normal Read cycles, except
for the WE output. WE is held inactive for Read cycles, but
goes active for Write cycles. All 8203 Write cycles are
"early-write" cycles; WE goes active before CAS goes active by an amount of time sufficient to keep the dynamic
RAM output buffers turned off.
Read Cycles
The 8203 can accept two different types of memory Read
requests:
General System Considerations
All memory requests (Normal Reads, Advanced Reads,
Writes) are qualified by the PCS input. PCS should be stable, either active or inactive, prior to the leading edge of
RD, WR, or ALE. Systems which use battery backup
should pullup PCS to prevent erroneous memory requests.
1) Normal Read, via the RD input
2) Advanced Read, using the Sl and ALE inputs (16K
mode only)
The user can select the desired Read request configuration via the B 1 / OP 1 hardware strapping option on pin 25.
Pin 25
Pin 32
Pin 34
# RAM banks
Ext Refresh
Normal Read
Advanced Read
Bl input
OPI (+12V)
SI input
ALE input
2 (RAS 2-3)
RD Input
REFRQ Input
4 (RAS 0-3)
Yes
In order to minimize propagation delay, the 8203 uses an
inverting address multiplexer without latches. The system
must provide adequate address setup and hold times to
guarantee RAS and CAS setup and hold times for the
RAM. The tAD AC parameter should be used for this system calculation.
The BO-B 1 inputs are similiar to the address inputs in that
they are not latched. BO and B1 should not be changed
during a memory cycle, since they directly control which
RAS output is activated.
No
Figure 8. 8203 Read Options
The 8203 uses a two-stage synchronizer for the memory
request inputs (RD, WR, ALE), and a separate two stage
synchronizer for the external refresh input (REFRQ). As
with any synchronizer, there is always a finite probability
of metastable states inducing system errors. The 8203
synchronizer was designed to have a system error rate
less than 1 memory cycle every three years based on the
full operating range of the 8203.
Normal Reads are requested by activating the RD input,
and keeping it active until the 8203 responds with an
XACK pulse. The RD input can go inactive as soon as the
command hold time (tCHS) is met.
Advanced Read cycles are requested by pulsing ALE
while S 1 is active; if S 1 is inactive (low) ALE is ignored.
Advanced Read timing is similiar to Normal Read timing,
except the falling edge of ALE is used as the cycle start
reference.
A microprocessor system is concerned when the data is
valid after RD goes low. See Figure 9.ln order to calculate
memory read access times, the dynamic RAM's A_C_
specifications must be examined, especially the RAS-access time (tRAC) and the CAS-access time (tCAC). Most
configurations will be CAS-access limited; i.e., the data
from the RAM will be stable tcc,max (8203) + tCAC
(RAM) after a memory read cycle is started. Be sure to
add any delays (due to buffers, data latches, etc.) to calculate the overall read access time.
If a Read cycle is requested while a refresh cycle is in
progress, then the 8203 will set the internal delayedSACK latch. When the Read cycle is eventually started,
the 8203 will delay the active SACK transition until XACK
goes active, as shown in the AC timing diagrams. This delay was designed to compensate for the CPU's READY
setup and hold times. The delayed-SACK latch is cleared
after every READ cycle.
Based on system requirements, either SACK or XACK can
be used to generate the CPU READY signal. XACK will
normally be used; if the CPU can tolerate an advanced
READY, then SACK can be used, but only if the CPU can
tolerate the amount of advance provided by SACK. If
SACK arrives too early to provide the appropriate number
of WAIT states, then either XACK or a delayed form of
SACK should be used.
3-292
Since the 8203 normally performs "early-write" cycles,
the data must be stable at the RAM data inputs by the time
CAS goes active, including the RAM's data setup time. If
the system does not normally guarantee sufficient write
data setup, you must either delay the WR input signal or
delay the 8203 WE output.
Delaying the WR input will aelay all 8203 timing, including
the READY handshake signals, SACK and XACK, which
AFN-02144B
intel·
8203
RD~
I
~
may increase the number of WAIT states generated by the
CPU.
I
Ii:
G-
If the WE output is externally delayed beyond the CAS active transition, then the RAM will use the falling edge of WE
to strobe the write data into the RAM. This WE transition
should not occur too late during the CAS active transition,
or else the WE to CAS requirements of the RAM will not be
met.
________________ ________J
~I
~---tRLOV
!-:
DATA---------~(
I
I
t..-tRAC---"':
I
I
'\
i
I
tCAe
I
I
0
The RASo-i: CAS, OUTO-7' and WE outputs contain onchip series damping resistors (typically 20m to minimize
overshoot.
'-t
CAS - - - - - - - - - - \
!/
Some dynamic RAMs require more than 2.4V VIH- Noise
immunity may be improved for these RAMs by adding pullup resistors to the 8203's outputs. Intel RAMs do not require pull-up resistors.
Figure g. Read Access Time
2118
DYNAMIC RAM ARRAY
AS-15
ALE
8088
ADO-7
RD
WR
~
ALO-6
OUTO-6
~
AHO-6
-
+
AO-6
80-1
8203
(16K MODE)
~
RD/51
=:
WE
CAS
-
RASa
WR
RAS1~
--c
RAS2
SACK
RAS3
=:::
WE
CAS
RAS
DIN Dour
,--1
-
-
-
WE
CAS
RAS
DIN Dour
T
=:::~
_WE
-
-_
CAS
RAS
DIN DOUl
TT
~
~S;;DATA BUS
DATA
LATCH IN
~
AO-6
DIN Dour
'T I
A
II
1\
D'N
Dour
:Ll
D'N
~
Ll
..1.3
WE
CAS
RAS
Dour
Ll
+
+
AD-6
XACK
=:
D'N
D'N
DOUT
!
D'N
D'N
Dour
1
.I
D'N
D'N
D'N
Dour
1
Dour
Dour
Dour ~UT
1
'J
'--
Figure 10. Typical 8088 System
3-293
AFN-021448
8203
MULTIBUS'
TYPE
SYSTEM
BUS
8284A
8288
READ
MRDe
MWTC
WRITE
8086
BHEN
ADRO
I ADR,
A9 16
1 ADRF
A019
I
OTHER
READY
INPUTS
BHE
00-15
I
I
I
READ
WRITE
~
8286
XCEIVER
I-+-+-----+-.
RAM
32 BITS +
7 CHECK BITS
~
~
-
WE
01
8207
MUX
CLK)---+ eLK
",UX
-
-
PSEN
CE
r-----
IL~
ERROR
DBM
--.I
ADDR
ACKA
RIW
ACKA
-
LI
PSEL
[
ADORA
th
WZ
ADDRB
CMPIPEA
cal DO/CSO
ADRC
C.
RIW
ERL SVOI DIICBI
R/W
CSO
PPI
·5V- 8TB
~
PPO
8206
CReT MASTER
~
wz
8M
-
-5V
8206
SLAVE
WZ
BM
DOIWOI
DOIWDI
Q
II~
BYTE
MARK
ST8
CRef
Q
-"'--
01
SVI
.... ~"-
.....
t~
DECODER
'---
,L.....-
~
L-...
OE
XCVR
r-
OEI
LATC,",
RD
sra
PORT A
PORTS
Figure 5. Dual Port RAM Subsystem with 8206/8207 (32-bit bus)
3-311
AFN-
TEST POINTS
A.C. TESTING LOAD CIRCUIT
V-
<::~
DEVICE
UNOER
TEST
!fe,
RL
TEST POINT
-=
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 08V FOR A lOGIC a
C L INCLUDES JI~ CAPACITANCE
3-314
AFN·020098
inter
8206
A.C. CHARACTERISTICS
(TA = O°C to 70°C, vee = +5V ± 10%, Vss = OV, RL = 22fi, CL = 50 pF;
all times are in nsec.)
8206
Symbol
Parameter
Min.
Max.
8206-8
Min.
Max.
Notes
TRHEV
ERROR Valid from RlWi
25
34
TRHCV
CEVaiid from R/Wi (Single 8206)
44
59
TRHOV
Corrected Data Valid from R/Wi
54
66
1
TRVSV
SYO/CBO/PPOValid from R/W
42
56
1
TDVEV
ERROR Valid from Data/Check Bits In
52
70
TOVCV
CE Valid from Data/Check Bits In
70
94
TDVOV
Corrected Data Valid from Data/Check Bits In
67
90
TOVSV
SYO/PPOValid from Data/Check Bits In
55
74
TBHOV
Corrected Data Access Time
TDXOX
Hold Time from Data/check Bits In
0
TBLOZ
Corrected Data Float Delay
0
TSHIV
STB High to Data/Check Bits In Valid
TIVSL
Data/Check Bits In to STB~ Set-up
TSLIX
Data/Check Bits In from STB~ Hold
43
37
1
0
28
0
38
40
30
5
5
25
30
1
-2
TPVEV
ERROR Valid from Partial Parity In
30
40
TPVOV
Corrected Data (Master) from Partial Parity In
61
76
1
TPVSV
Syndrome/Check Bits Out from Partial Parity In
43
51
1
TSVOV
Corrected Data (Slave) Valid from Syndrome
51
69 -
TSVCV
CE Valid from Syndrome (Slave number 1)
48
65
TOVOV
Check Bits/Partial Parity Out from Wnte Data In
64
80
TRHSX
Check Bits/Partial Parity Out from R/W, WZ Hold
0
0
TRLSX
Syndrome Out from R/W Hold
0
0
TOXOX
Hold Time from Write Data In
TSVRL
1
0
0'
Syndrome Out to R/W~ Set-up
17
22
TOVRL
Data/Check Bits In to R/W Set-up
39
TDVOU
Uncorrected Data Out from Data In
32
43
TTVOV
Corrected Data Out from CRCl!
30
40
TWLOL
WZ~
30
TWHOX
Zero Out from WZi Hold
to Zero Out
0
1
1
46
1
40
0
NOTES:
1. A.e. Test Levels for eso and DO are 2.4V and 0.8V.
2. TSHIV is required to guarantee output delay tll\1lngs' TOVEV, Tovcv, TOVQV, Tovsv. TSHIV + TIVSl guarantees a min STS pulse
width of 35 ns (45 ns for the 8206-8).
..
,
3-315
AFN-02OO9II
8206
WAVEFORMS
READ-16 BIT ONLY
STB7:
!
I:SH'~ I'
N'--+:-----
T'VSL
•
I I!SL'! 1
RtYi_-4'~
1
1
:
1
1
1
1
1
I
I
1
1
~
8M
:~
----T-I--I' I
1
~
f{
I 1' - - - - - - -
~TBHOV-I
1
ri
I 1
I I
1
i'~
~)-!-:- - I
If+-._ _ _--1.I TRHOV
!..--TBlQZ _ _
1
. '
I
--wffiWd . ~ro...
DO-~i
11-.- - - T R V S V
SYO
I"
1
,
TOVSV
./
--+-J:=:I!
!' ~TRHEV::;::;::;::';=;~~
>W///~
ERROR_-+-:
I ..
I
1
TOVEV
1
I
•1
1
VALID
_:
Tovev
x=
x==
_ _ 1
...j........J:
I"
~
1
i .~.
TOVQV
--!
k=
1
./
------+-:-+-'1)@W/$Et
I.
1
'
_,
_~I_I~'~~~~TRH~eV~~~~~_I~_ _ _ _ _ _
CE_---')<7#~/A
3-316
VALID
1
1
AFN-Q2009B
8206
WAVEFORMS (Continued)
READ-MASTER/SLAVE
ft'------
STB;;f
I
:--lTSHIV
,
I
I
, :
I ~
-I'U,
pE ,
R,\II _ _ _
I
I
"~
I
I
' { ' -_ _-tIl_ _
I
!
I-
I
I
1--1
c~: ----<~.--'i--+-i---VAL--iID
I---:TRVSVr---1
::,~~:~:::: -----'~
I
~~~
I
i
I
TSLIX I
~
I
I
I
I--!
TBHOV
8M _ _ _.!-I...J.I....J
I
TIVSL L.....-.l
I
i
I
i
I_TDXOX_I
,
X"---:-
VALID
:
:_TPVOV~
I
I
I
'-TPVSV-j
I
I
_~.....-r-?4"""":"~~//:~~'-T-7jf-+r---VAL-ID-$l}-
DO (MASTER) - - - - - ; - - :
I
SYO(MASTER)-----'XV~M
4L
SYI(SLAVE) -
I
:'
4
VALID
,,-------I
.-----
ra-
I.-TSVOV_:
I
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I
XI
VALID
I-TPVEV.i I
~'~~~TR~HE;~~~~'I~I_____________
ERROR---J~/4:
VALID
I :SVCV.I
I
I
X'--_
,
~I'~~~~~TR~HC~V~~~~'~I~____~~I
A
CE'-----I)0//////0/W
3-317
VALID
X_
AFN-02009B
8206
WAVEFORMS (Continued)
FULL WRITE-16 BIT ONLY
1---
TRVSV
---I
-------------..i
,
R/W
I
1,--_ _ _ _ _-
A
i
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1
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"'K
DATA OUT
1-'
WRITE DATA IN
1
I
,
1
T~
'--Tavav---"I
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I
1--1
,
------S-VN-------~.L~_.L~_L_I:'"__
1
1
___
CB_ _
~X
SVN
FULL WRITE-MASTER/SLAVE
~TRvsv--+-1
r1
I
R/" - - - - - - - - ' {
I~BLa~1
I
I
BM~:
:
I
I
1
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,
I
:
:
I:,
I
DO/WOl
DATA OUT
1
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W
--!.:I___
WR_ITE_D_,,_Al_N
i
,
PPI(MASTER)
I
H..,I_____
I
I
PPO,SLAVE)
1
~TavQv~1
Taxaxl
x=
I
I
)(/5R771
---------T"I
-----'---1
VALID
I
l-SVO/CBO _ _S_VN_ _
'
TRLSX
--I
:.
1
TPVSV
• 1
---J~4
3-318
:
CB
:k=
AFN-02009B
8206
WAVEFORMS (Continued)
READ MODIFY WRITE-16 BIT ONLY
f'f-'
N _____
STa)
II
TS1IVi-,,-----TIVSL----!·I 1--.---TsLlx------t·1
-tt-'
II
I
II
I
RIW
=vr
1
8M
I~-----'I~
1+-1'-"-I----TovRL.---....·I_TRvsv---i
I
1
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I
;
X----VAL-t-IO:
I:
1I
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1
cg:
'{
A:
-----r-:
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I
I__ TBHav---'I
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-----r-I_VA~LIO:
-i-+-:
,
1
1
II
---'-'~L
II!RHSX II
'I
II
-+-_~1
I
I
:
I
.~~~===_TR:::'-av==;1~;:;-1:~:r+1__---=~---To_Xa-X---l_ j- :
1
I I
~1.---TRvsv·----+l·1 M l-TRLSX
I I
Taxa;::
I I
~"""T'"'"":;Z0......-r-Z"""T'"'"":;74.....-i-7-::---'-SVN~""'-'~'---'-~-t>'--CB_ _
SVOICBO -----I....i_____)Q;;r7'"7""(
.
I------TOVSV
I I
1
1
1
1
mL.
~!
1.
.
-: : ,
-::
__
I
I
I,TBL~I
I
I
1
,
I
I
1
I
I
X=
I
.1 I--TOvav_1
3-319
AFN-02009B
inter
8206
WAVEFORMS (Continued)
READ MODIFY WRITE-MASTER/SLAVE
;f
R/W
---'
A
'{
I
1' - - - - - '
I
I
I
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----l
__~>K~-----------r:------~}(~____~i
'I
I
j4--TBHaV _ _ 1
-J:
STB
7]
",-SHI: 14
I
1
01
CBI
TOVSV ------I
I
I
!-TlVSL-!
1
1
~I
1
1'\-+-:
I
1
I
~
t!
.1
TRVSV ----.,
p:~::::::: =*zR~07
I
I
1
I
I
I
I
I
I
I I
II
-----t--t:I
I
1
1
I I
I II
I-+- TSVRL ---+r-TRVSV -+l
!
VALID
1
1
1
I
I
1
1
I
I
iTP~SV-1
1
I
I
I
I
1
I
I
:I ~
i
~~~---~I-----~~
I
I
I
:
VALID
I
I
I
SYN
I ~
X//Ui
L-f
I
I
1
~TaVaV~
I
I
~
I
I
I 1
I I
»-t
iI
j4-7-TPVaV--!
K
~r:WR""IT-"H~:--------t-!
I
Sya/CBa(M~
SYI (SLAVE)
I
j---TBLaz~
I
1
(MASTER)
1
1
--~=:======:i=:1I ==;VA_L-Io====:================::i
I
oO/WOI
I
I
I
CB
KI
I
oO/WOI -t--I- - @ {
(SLAVE)
3-320
VALID
AFN-Q2009B
8206
WAVEFORMS (Continued)
NON-C'ORRECTING READ
CRCT
--------..'1-
)
, ' - -_ _ _---J
I
I
I
:II
I
r
I TTVQV I
lI'
I__ TTVQV_I
I_
TBlQI _,
1
~=============:t=========:i===========:i=~~
I
I
!--TBHQV----l
I
' I
DO/WDI
1=
:
t o o l . - - T D V Q U - -._II
.
I
I
01
CBI
I
I
I
8MJ:
I
-------WA
WRITE ZERO
I
I
I
I
UNCORRECTED
{
iII :
I
I
I
1
I
I
CORRECTED
:I}
UNCORRECTED
I
~
1._
. ---TWlQL---.1
I
1
I
m---------~~~I_____________I~:'-------J;'f------I
1_ TQVQV(l) ~
I
I
I
ITQVQV(2)
I-I
I
1
Do0'l~mJuhWflJ:
~
1
I
I
I~WHQ~ I
I
I
: k7d
I
1
I~I
NOTE:
(1): 16 BIT ONLY
(2): MASTER/SLAVE
3-321
AFN·02009B
inter
8207
ADVANCED DyNAMIC RAM CONTROLLER
• Provides All Signals Necessary to
Control 16K (2118), 64K (2164A) and
256K Dynamic RAMs
• Directly Addresses and Driv,s up to 2
Megabytes without External Drivers
• Supports Intel iAPX 86, 88, 186, and 286
Microprocessors
• Supports Single and Dual-Port
Configurations
• Provides Signals to Directly Control the
8206 Error Detection and Correction Unit
• Automatic RAM Initialization in All
Modes
• Five Programmable Refresh Modes
• Transparent Memory Scrubbing in
ECC Mode
• Data Transfer Acknowledge Signals for
Each Port
• Supports Synchronous or
Asynchronous Operation on Either Port
• +5 Volt Only HMOSII Technology for
High Performance and Low Power
The Intel 8207 Advanced Dynamic RAM Controller (ADRC) is a high-performance, systems-oriented, Dynamic
RAM controller that is designed to easily interface 16K, 64K and 256K Dynamic RAMs to Intel and other
microprocessor Systems. A dual-port interface allows two different busses to independently access memory.
When configured with an 8206 Error Detection and Correction Unit the 8207 supplies the necessary logic for
designing large error-corrected memory arrays. This combination provides automatic memory initialization,and
transparent memory error scrubbing.
ERROR
i\DA
WRA
PCTLA
PlJ\
RFRQ
PDI---1f---'-~
YccYss---+-
eLK---+-
RESET---+-
1-_ _ _ _ _1/ AOo-,
AL08C===~~
AHa 8
'--------,./1
BSO.1C====:~
Figure 1. 82.07 Block Diagram
Intal Corporation AI.umes No ReapORSlblity for the U.e of Any CirCUitry Other Than CirCUitry Embodied In an Intel Product No Other CirCuit Patent licenses are Imphed
(£"NTEL CORPORATION. 1982
'
3-322
A1'RIL 1982
ORDER NUMBER: 210483-001
8207
Table 1. Pin Description
Pin
Type
Name and .Function
LEN
Symbol
1
0
ADDRESS LATCH ENABLE: In two·port configurations, when port A is running with
iAPX 286 Status interface mode, this output replaces the ALE signal from the system
bus controller and generates an address latch enable signal which provides op·
timum setup and hold timing for the 8207.
XAGKA/
AGKA
2
0
TRANSFER ACKNOWLEDGE PORT A/ACKNOWLEDGE PORT A: In non·EGG mode,
this pin is XAGKA and indicates that data on the bus is valid during a read cycle or
that data may be removed from the bus during a write cycle for Port A. XACKA is a
Multibus·compatible signal. In EGG mode, this pin is AGKAwhich can be configured,
depending on the programming of the X program bit, as an XAGK or AAGK strobe.
The SA programming bit determines whether AAGK will be early or late.
XAGKB/
AGKB
3
0
TRANSFER ACKNOWLEDGE PORT B/ACKNOWLEDGE PORT B: In non-EGG mode,
this pin is XAGKB and indicates that data on the bus is valid during a reXd cycle or
that data may be removed from the bus during a write cycle for Port B. AGKB is a
Multibus-compatible signal. In EGG mode, this pin is AGKB which can be configured,
depending on the programming of the X program bit, as an XAGK or AAGK strobe.
The SB programming bit determines whether AAGK will be early or late.
AAGKN
WZ
4
0
ADVANCED ACKNOWLEDGE PORT A/WRITE ZERO: In non-EGG mode, this pin is
AAGKA and indicates that the processor may continue processing and that data will
be available when required. ThiS signal is optimized for the system by programming
the SA program bit for synchronous or asynchronous operation. After a RESET, this
signal will cause the 8206 to force the data to all zeros and generate the appropriate
check bits.
AAGKB/
R/iN
5
0
ADVANCED ACKNOWLEDGE PORT B/READ/WRITE: In non-EGG mode, this pin IS
AAGKB and indicates that the processor may continue processing and that data will
be available when required. ThiS signal IS optimIzed for the system by programming
the SB program bit for synchronous or asynchronous operation. This signal causes
the 8206 EDGU to latch the syndrome and error flags and generate check bits.
DBM
6
0
DISABLE BYTE MARKS: This is an EGG control output signal indicating that a read
or refresh cycle is occurring. This output forces the byte address decoding logic to
enable all 8206 data output buffers. In EGG mode, thiS output is also asserted during
memory initialization and the 8-cycle dynamic RAM wake-up exercise.
ESTB
7
0
ERROR STROBE: In EGG mode, this strobe is activated when an error is detected
and allows'a negative-edge triggered flip-flop to latch the status of the 8206 EDGU
GE for systems with error logging capabilities.
LOGK
8
I
LOCK: ThiS input Instructs the 8207 to lock out the port not being serViced at the time
LOGK was issued.
Vee
9
43
I
I
LOGIC POWER: +5 Volts ± 10%. Supplies Vee for the Internal logic cirCUits.
DRIVER POWER: +5 Volts ± 10%. Supplies Vee for the output drivers.
GE
10
I
CORRECTABLE ERROR: ThiS is an EGG input from the 8206 EDCU which instructs
the 8207 whether a detected error is correctable or not A high Input indicates a
correctable error. A low input inhibits the 8207 from activating WE to write the data
back Into RAM. This should be connected to the GE output of the 8206.
ERROR
11
I
ERROR: This IS an EGC input from the 8206 EDGU and instructs the 8207 that an
error was detected. This pin should be connected to the ERROR output of the 8206.
MUX/
PGLK
12
0
MULTIPLEXER CONTROL/PROGRAMMING CLOCK: Immediately after a RESET
this pin IS used to clock serial programming data Into the PDI pin. In normal two-port
operation, this pin is used to select memory addresses from the appropriate port.
When this signal is high, port A is selected and when it is low, port B is selected. ThiS
signal may change state before the completion of a RAM cycle, butthe RAM address
hold time is satisfied.
PSEL
13
0
PORT SELEC'I": This signal IS used t~ select the appropriate port for data transfer.
PSEN
14
0
PORT SELECT ENABLE: This signal used in conjunction with PSEL provides
contention-free port exchange. When PSEN IS low, PSEL is allowed to change state.
0
WRITE ENABLE: This signal provides the dynamiC RAM array the write enable input
for a write operation.
I
WE
15
3-323
AFN-0221BA
intel'
8207
Table 1, Pin Description (Continued)
Symbol
Pin
Type
Name and Function
FWR
16
I
FULL WRITE: This is an ECC input signal that instructs the 8207, in an ECC configuration, whether the present write cycle is normal RAM write (full write) or a RAM
partial write (read-modify-write) cycle.
RESET
17
I
RESET: This signal causes all internal counters and state flip-fl--
ALE
elK
~~
51
SO
80861
80186
CLR
OE STa
8283
~'T
OE
B1
,.
EXTENDED MEMORY USING STATUS.
STB
8283
LATCH
I--I---
L....-
~
~
OE
~--rJ
STa
OE
8283
LATCH
,.
,.
-
k'
ADDR/DATA
PORT A-SYNCHRONO US;
OE
8283
,v-
lo.
BO
r-
<
I
I
-----t I, f+- I
------~~
I
I
I
I
I -112
f~-----------
i-"=
I
I
------------~I--~)( ~i-------------------I
~f
I
~ '~'---------
NOTES
I,-PSEN DELAY
\,-PSEL DELAY
10-TRANSCEIVER OUTPUT DISABLE TIME
t.-TRANSCEIVER OUTPUT ENABLE TIME
Figure 12. Port Switching Timing for Dual Port Data Bus
3-339
AFN-02218A
8207
Processor Timing
AACK must be used and connected to the SRDY
input of the appropriate bus controller. AACK is issued relative to a point within the RAM cycle and has
no fixed relationship to the processor's request. The
Timing for the 8086,80186, and 80286 processors is
given in Figure 13.ln order to run without wait states,
Tl
T2
T4
T3
elK
so, 51. 52 (8086)
ADDRESS OUT (8283)
\
__
\
\ \
~ij~--I----V-AlID----~X~--
;f
-If
CMD(8288)
DATA IN (8086)
1/
I
_0_~U~_~_
SRDY (8284A)
(A) 8086-80188 TIMING
so,51
\
j~
IL /1
I
I
ADDRESS,M/iO
1\ \
'IIIII/X
i
_ _ _..\.( _ _ _ _ _ _ VALID
_ _ _ _ _ _ _-J "-J...J,.,,<.....L..l..-_ _ _ _ __
-1
CMD(82288)
DMAIN
I
I
( I
dl
:f~:
------------------------~-
=D
SRDY (82284)
(8) 80286 TIMING
t
I-
I
Figure 13. 8086,80186 and 80286 Read Timing
3-340
AFN-02218A
8207
timing is such, however, that the processor will run
without wait states, barring refresh cycles, bank precharge, and RAM accesses from the other port. In
non-ECC fast cycle, fast RAM, non-extended configurations (80286), AACK is issued on the next failing edge of the clock after the edge that issues RAS.
In non-ECC, slow cycle, non-extended, or extended
with fast RAM cycle configurations (8086, 80186),
AACK is issued on the same clock cycle that issues
RAS. Figure 14 illustrates the timing relationship between AAeJ(, the RAM cycle, and the processor cycle
for several different situations.
aborted. In asynchronous operation, PE is required
to be setup to the same clock edge as the internally
synchronized status or commands. Externally, this
allows the internal synchronization delay to be atlded
to the status (or command)-to-PE delay time, thus
allowing for more external decode time than is available in synchronous operation. The minimum sync,hronization delay is the additional amount that 'J5E
must be held valid. If PE is not held valid for the
maximum synchronization delay time, it is possible
that J5E will go invalid prior to the status or command
being synchronized. In such a case the 8207 aborts
the cycle. If a memory cycle intended for the 8207 is
aborted, then no acknowledge (AACK or XACK) is
illsued and the processor locks up in endless wait
states. Figure 15 illustrates the status (command)
timing requirements for synchronous and asynchronous systems. Figures 16 and 17 show a more
detailed hook-up of the 8207 to the 8086 and'80286,
respectively.
Port Enable (P'E'j setup time requirements depend on
whether the associated port is configured for synchronous or asynchronous operation. In synchronous operation, Pi: is required to be setup to the
same clock edge as the status or commands. If J5E is
true (low), a RAM cycle is started; if not, the cycle is
8207CLK
I
~_LlLlDD
1
---JX""___,.JX,,,,'......,{Ir--_'T'YA_L_ID_ _ _....XI........l.(__Vi-~L_ID_ _ __
ADDR OUT _ _ _...,-V... _ _ _
:::::J 1=
-~\'--r""""';\-'-t'I_-L/-J7
-
I
1\
1-
1
1
1
1
RAM DATA
1
1
1
1
I
7
/
1
\""'\-'TI_-J/
1
1W
---{\.W
:
I
\ 1
\......_____/ :
\W
s~......- - _ - ' /
:r~
\'-------i':rj\
\~-----tJII:
1
:
+-'I" -
\I.--_ _
I
.---..------'
< --.+,r-+<""--'<___
I
VA_Ll_D_ _-'-'I--........,..-
VALID
1
1
~~~~a:~~:~
~PORT, REFRESH CYCLE,:-I
OR BANK PRECHARGE'
1
1
~
CYCLE WITHOUT
WAIT STATES
1
-I
(AI 80286 TIMING
Figure 14. 80286 Synchronize Timing
3-341
AF"'-02218A
8207
8207CLK
I
1:.1:-
COMMAND/STATUS
I
PE
I
I
I
I
--l
I
J7
(A) I5E SET·UP AND HOLD TIME REQUIREMENTS FOR SYNCHRONOUS
OPERATION (80286 CMD/STATUS)
8207CLK
COMMAND/STATUS
PE
--------4"""'--
------------~;2~==~
MAX DELAY
MIN HOLD FROM CMD
FROMCMD
(8)
Pi! TIMING REQUIREMENTS FOR ASYNCHRONOUS OPERATION
Figure 15. PE Timing Requirement
Memory Acknowledge
(ACK, AACK, XACK)
In system configurations without error correction,
two memory acknowledge signals per port are supplied by the 8207. They are the Advanced Acknowledge strobe (AACK) and the Transfer Acknowledge
strobe (XACK). The CFS programming bit determines for which processor AACKA and AACKB are
optimized, either 80286 (CFS = 1) or 8086/186 (CFS
= 0), while the SA and SB programming bits optimize
AACK for synchronous operation ("early" AACK) or
asynchronous operation ("late" AACK).
Both the early and late AACK strobes are three
clocks long for CFS = 1 and two clocks long for CFS
= O. The XACK strobe is asserted when data is valid
(for reads) or when data may be removed (for writes)
and meets the Multibus requirements. XACK is
removed asynchronously by the command going inactive. Since in a synchronous operation the 8207
removes read data before late AACK or XACK is
recognized by the CPU, the user must provide for
data latching in the system until the CPU reads th~
data. In synchronous operation, data latching is unnecessary since the 8207 will not remove data until
the CPU has read it.
In ECC-based systems there is one memory acknowledge (ACK) per port and a programming bit associated with each acknowledge. If the X programming
bit is high, the strobe is configured as XACK, while if
the bit is low, the strobe is configured as AACK. As in
non-ECC, the SA and SB programming bits determine whether the AACK strobe is early or late.
Data will always be valid a fixed time after the occurrence of the advanced acknowledge. Table 9 summarizes the various transfer acknowledge options.
3-342
AFti-02218A
inter
8207
8284A
ARDY
READY
ClK
("If:J OTHER ~ INPUTS
+
ClK
8288
DEN
DTIIi
READY
t---
ClK
~-3
CA 0-3
8207
PCTl
AOo_s
RD
WE
WR
Ll
52
1
51
SO
~OE
8088
ADDRI
DATA
r- r-v"
AlCK
ClK
r--
S2 SlSOAlE
r--
8283
;-
~
T~
STB
~
OE
8287
l'
----=>
DI
DO
WE
I
lATCH
'7
....
WE
MEMORY
(LOWER)
=>
-
AHO-sAlO-s
STB
~
MEMORY
(UPPER)
BYTE
MARK
DECODER
J
:D-
-
I
I
{r
DI
DO
I
~
16/
f
lATCH
T
-
'--
STB
OE
16/
8283
f
lATCH
Figure 16. 8086 Hook-up to 8207 Non-ECC Synchronous System-Single Port.
3-343
A~2218A
8207
82284
<'l= I OTHER ACK INPUTS
ii!AliY SRDY
CLK
+
CLK
ALE
82288
DEN
DT/li
READY
-
CLK
==:>
ADDR,
STROBES
M/iOS1SO
CLK
AACK
~I
S1
PCTL
M/iO
~ RD
SO
WR
80286
MEMORY
(UPPER)
8207
WE
.
WE
ADDRIN
DI
DO
'~
"
ADDR
~
~
DATA
MEMORY
(LOWER)
I
f-
WE
DI
I il
DO
I
I
~
STBJ
~
Tq
STB
BYTE
MARK
LATCH
-
r-!!-
OE
16
8283
LATCH
T
STB
'---
'---:-
r-OE
16
8283
LATCH
NOTE
THE BYTE MARK LATCH MAY ALSO BE STROBED WITH LEN
Figure 17. 80288 Hook-up to 8207 Non-ECC Synchrol'!ous System-Single Port.
3-344
AFN-02218A
8207
Table 8. Processor Interface/Acknowledge Summary
CYCLE
FAST
CYCLE
CFS=l
SLOW
CYCLE
CFS=O
PROCESSOR
REQUEST TYPE
SYNC/ASYNC
INTERFACE
ACKNOWLEDGE TYPE
80286
STATUS
SYNC
80286
STATUS
ASYNC
EAACK
LAACK
80286
COMMAND
SYNC
EAAcK
80286
COMMAND
ASYNC
LAACK
8086/80186
STATUS
ASYNC
LAACK
8086/80186
COMMAND
ASYNC
LAACK
MULTIBUS
COMMAND
ASYNC
XACK
8086/80186
STATUS
SYNC
EAACK
8086/80186
STATUS
ASYNC
LAACK
8086/80186
COMMAND
SYNC
EAACK
6086}80186
COMMAND
ASYNC
LAACK
MULTIBUS
COMMAND
ASYNC
XACK
Table 9. Memory Acknowledge Option Summary
Synchronous
Asynchronous
XACK
Fast Cycle
AACK Optimized
for Local 80286
AACK Optimized for
Remote 80286
Multibus Compatible
AACK Optimized
for Local 8086/186
AACK Optimized for
Remote 8086/186
Multibus Compatible
Slow Cycle
Test ModelS
Two special test modes exist in the 8207 to facilitate
testing. Test Mode 1 (non-ECC mode) splits the
refresh address counter into two separate counters
and Test Mode 2 (ECC mode) presets the refresh
address counter to a value slightly less than rollover.
Test Mode 1 splits the address counter into two, and
increments both counters simultaneously with each
refresh address update. By generating external
refresh requests, the tester is able to check for
proper operation of both counters. Once proper individual counter operation has been established, the
8207 must be returned to normal mode and a second
test performed to check that the carry from the fi rst
counter increments the second counter. The outputs
of the counters are presented-on the address out bus
with the same timing as the row and column addresses of a normal scrubbing operation. During
Test Mode 1, memory initialization is inhibited, since
the 8207, by definition, is in non-ECC mode.
Test Mode 2 sets the internal refresh counter to a
value slightly less than rollover. During functional
testing other than that covered in Test Mode 1, the
8207 will normally be set in Test Mode 2. Test Mode 2
eliminates memory initialization in ECC mode. This
allows quick examination of the circuitry which
brings the 8207 out of memory initialization and into
normal operation. Test Mode 2 is also useful for quick
reset response in ECC systems.
PACKAGE
The 8207 is packaged In a 68-pin, lead less JEDEC
type A hermetic chip carrier. Figure 18 illustrates the
package, and Figure 19 is the pinout.
3-345
AFN-02218A
inter
8207
050
H Dn
L_
.800
(20.32)
I
.960
(2438)
(D~::)l
PIN NO. 18
PIN NO 1
~PIN
NO 1 MARK
.130
(3.30)
.960
(24.38)
Figure 18. 8207 JEDEC Type A Package
3-346
AFN-02218A
inter
8207
TOP
§=i~~~~~~~~~~iiii
~~~~~i;~~3~~~"$~
34 A01
33
32
31
30
A02
A03
A04
AD5
29 A06
28 A07
27 A08
PIN NO.1 MARK
BOTTOM
52 AH4
53 AH5
54 AH6
55 AH7
56 AH8
57 PDI
58 RFRQ
59 eLK
60 Vss
61 ImII
62 WIllI
63
J5ElI
64 PCTLB
651mA
66 Wli7<
67
PEA
68 PCTLA
Figure 19. 8207 Pinout Diagram
3-347
inter
RAM FAMILY
EXPRESS
• Standard Temperature Range
• 168 (±8) Hour Burn-In Available
• Extended Temperature Range
-40°C- +85°C Available
• Inspected to 0.1% AQL
The Intel EXPRESS RAM family is a series of random-access memories which have received additional
processing to enhance product operating temperature range and infant mortality. EXPRESS processing is
available for several densities of RAM, allowing the choice of appropriate memory size to match system
applications.
EXPRESS RAM product is available with 168(±8) hour, 125°C dynamic burn-in using Intel's standard bias
configuration. This process exceeds or meets most industry specifications of burn-in.
The standard EXPRESS RAM operating temperature range is O°C to 70 or 75° C. Extended operating temperature range (-40°C to 85°C) EXPRESS product is available. EXPRESS products plus military grade RAMs (-55°C
to 125°C) provide the most complete choice of standard and extended temperature range RAMs available.
like all Intel RAMs, the EXPRESS RAM family is inspected to 0.1% electrical AQl. This may allow the user to
reduce or eliminate incoming inspection testing.
Detailed individual product electrical specifications are available separately in Intel's respective commercial
and industrial grade product data sheets.
'
2114A
2115A, 2125A
os
As
As
Vee
A,
..
A.
Aa
A,
A,
Aa
A,
vee
D,.
....
.."..
A,
As
110,
A,
A,
1/0,
°OUT
A,
1/0,
GND
cs
WE
2125H
..
B
vee
D, •
A,
WE
A,
"
"
..
"
"
DOUl
A,
GND
A,
I/O,
WE
GND
2118
N/C
DIN
v's
CAS
WE
°OUT
RAs
A,
Ao
A,
A,
A,
A,
A,
VDD
2148H,2.149H
2147H
Ao
Vee
A,
A.
A,
A,
A,
A.
A,
A,.
DouT
A"
D,N
N/C
Cs
Pin Configuratiol)
Intel Corporahon Assumes No Reaponsibllty for the Use of Any Circuitry Other Than Circuitry Embodied
@INTELCORPORATION. 19s:!
3-348
In an'lntel Product. No Other Circuli Patent Licenses are Implied
MARCH 1982
ORDER NUMBER: 210347-001
RAM FAMILY
Table 1. RAM Product Family
EXPRESS
Type
Organization
Maximum
Access
(ns)
Power
Supply
Operating
Temperature
eC)
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
OD2114A-4
OP 2114A-4
OD2114A-5
OP 2114A-5
OP 2114A-6
OD2114AL-1
OP 2114AL-1
OD2114AL-2
OP 2114AL-2
OD2114AL-3
OP 2114AL-3
OD2114AL-4
OP 2114AL-4
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
1K
x
x
x
x
x
x
x
x
x
x
x
x
x
4
4
4
4
4
4
4
4
4
4
4
4
4
200
200
250
250
300
100
100
120
120
150
150
200
200
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
5V
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
±10%
LD
LD
LD
LD
1K
1K
1K
1K
x
x
x
x
4
4
4
4
200
250
150
200
5V
5V
5V
5V
±10%
±10%
±10%
±10%
-40
-40
-40
-40
to
to
to
to
TO 2114A-4
TO 2114A-5
TO 2114AL-3
TO 2114AL-4
1K x 4
1K x 4
1K x 4
1K x 4
200
250
150
200
5V
5V
5V
5V
±10%
±10%
±10%
±10%
-40
-40
-40
-40
to 85
to 85
to 85
to 85
OD2115A
OD2115A-2
OD2115AL
OD2115AL-2
1K x
1K x
1K x
1K x
1
1
1
1
45
70
45
70
5V
5V
5V
5V
±5%
±5%
±5%
±5%
OD2125A
OD2125A-2
OD2125AL
OD2125AL-2
1K
1K
1K
1K
x1
x1
x1
x-1
45
70
45
70
5V
5V
5V
5V
±5%
±5%
±5%
±5%
OD2125H-1
OD2125H-2
OD2125H-3
OD2115H-4
1K
1K
1K
1K
x
x
x
x
1
1
1
1
20
25
30
35
5V
5V
5V
5V
±5%
±5%
±5%
±5%
002118-3
002118-4
002118-7
16K x 1
16K x 1
16K x 1
100
120
150
LD 2118-4
LD 2118-7
16K x 1
16K x 1
TD2118-4
TD2118-7
16K x 1
16K x 1
2114A-4
2114A-5
2114AL-3
2114AL-4
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
NONE
NONE
NONE
NONE
168
168
168
168
5V ±10%
5V ±10%
5V ±10%
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 75
o to 70
o to 70
o to 70
120
150
5V ±10%
5V ±10%
-40 to 85
-40 to 85
168
168
120
150
5V ±10%
5V ±10%
-40 to 85
-40 to 85
NONE
NONE
OD2147H
OD2147H-1
OD2147H-2
OD2147H-3
OD2147HL
OD2147HL-3
4K
4K
4K
4K
4K
4K
x
x
x
x
x
x
1
1
1
1
1
1
70
35
45
55
70
55
5V
5V
5V
5V
5V
5V
±10%
±10%
±10%
±10%
±10%
±10%
OD2148H
OD2148H-3
OD2148HL
OD2148HL-3
1K
1K
1K
1K
x4
x4
x4
x4
70
55
70
55
5V
5V
5V
5V
±10%
±10%
±10%
±10%
OD2149H
OD2149H-2
OD2149H-3
OD2149HL
OD2149HL-3
1K
1K
1K
1K
1K
x
x
x
x
x
70
45
55
70
55
5V
5V
5V
5V
5V
10%
10%
10%
10%
10%
4
4
4
4
4
85
85
85
85
Burn-In
125°C
(±8 hours)
3-349
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
168
J68
168
168
168
168
168
168
168
168
AFN'()2163A
inter
RAM FAMILY
p.
+5V
Ps
P,
P4
p.
P,
p.
Po
P '0
P,
P 11
P,
P
GND
P '3
GND
GND
TOLER·
PWR·UP
VOLTAGES
ANCES
SEQ.
CURRENT
DEVICE -
Vee
+5V
±.25V
1
70mA
V"
O.OV
±.5V
V,H
5.0V
±1.0V
SUPPLY
±.25V
"
I
I
U,
"RESET
..
NOISE
LEVELS
- - - 5V
- - - OV
"'
n
7 J.L~
I
"ADD. ADY.
I
I
,I
5V
"MUX
OV
2114/214812149
TIMING DIAGRAM
7 !,-s CYCLE TIME
Figure 1. 2114A, 2148H, 2149H Burn-in Configuration
3·350
AFN·02163A
intJ
RAM FAMILY
P
+5V
"
Po
P
P,
GND
P,
P,
P3
p.
P,
P,
"
Vee
2DDll
1f2watt
P,
GND
2DDll
P,
1J2watt
PWR·UP
SEQ.
CURRENT
NOISE
ANCES
DEVICE
LEVELS
lSI
75mA
TOLER·
SUPPLY
VOLTAGES
Vee
+5V
±.2SV
VIL
D.DV
±.5V
V ,H
5.DV
±l.DV
±.25V
1---
I
I
.---------------,Ui----I
---
5V
DV
~-------------7~s--------------~·11
I
"ADD. AD\!,
~----------------~n~__-I
I
I
5V
I
"MUX
DV
211512125 TIMING DIAGRAM
7 ~s CYCLE TIME
Figure 2. 2115,2125 Burn-in Configuration
3·351
AFN·02163A
RAM FAMILY
OPEN
GND
P14
SP,
SP3
NC
SP,
P6, P'3
po. P7
P3, PlO
P2, P9
P4, P'1
p,. P8
P5. P'2
TOLER· PWR·UP CURRENT NOISE
SUPPLY VOLTAGES ANCES SEQ.
DEVICE LEVELS
Pulses
4-6V
1st
+5V
Vdd
+5V
±.25V
2nd
±.25V
20mA
OPEN
Vdd
"RESET ----------------------_____________________________________________
~
"ADD.ADY. 1-1·---------------131'.;---------------......~1L
500n.
RAS ~~.---41'.-------...il~.~==================~9~.5~1'~.~==================~
..~ Pin 5
.
CAS FI·::=========::j81.i.5~I';.·;==========;.. tl:·===~4:.':.1'~.===::J'~ Pin 17
WE FI.::===========-;10O;:I'.;:==========:"11--~!2.!:.1'~.+1~:"-1.5'1'._ Pin 4
MUX FI;.======~6~.5~1'~.~====~.;lt.~::::::::::::::::7~1'~.~::::::::::::::~
STROBE
I!___________________________________-'r---------------,---,1___
--- 5VOV
I
I
1~·~----------------------------CYbt~~~ME----------------------------~..~1
I
I
~~
2118 TIMING DIAGRAM
Figure 3. 2118 Burn-in Configuration
3·352
AFN·02163A
RAM FAMILY
R
R
+5V
Po
1 Ao
Vee 18
P,
2 A,
As
17
Fs
P,
3 A,
A,
16
P,
P,
4 A,
A,
15
p.
P,
5 A,
A,
14
p.
P,
6 A,
A,o 13
p,.
7 Dour
Al1 12
P ll
8WE
D,N 11
P 12
9GND
CS
GND
200
200
GND
GND
R = 200
10
TO~R-
VOLTAGES
ANCES
PWR·UP
SEQ. '
CURRENT
DEVICE
LEVELS
Vee
+5V
".25V
1
125mA
".25V ~-
Vil
O.OV
".sV
V,H
5.OY
"l.OY
SUPPLY
n ll2W
1
r--------------..., ;-1_--
UI
'R9ETI
I
---
5V
---
OY
1~.~------7~·-------~·1
n
I
·ADD.AIl'l
I
I
~I- - - - -
I
I
I
I
I
:
___ 5Y
I
'MUX : - - - - - - - - - - - - - - - - - , - - - - - - - OY
2147H
TIMING DIAGRAM
7 ~. CYCLE TIME
Figure 4. 2147H Burn-In Configuration
3·353
NOISE
--
EPROMs (Erasable Programmable
Read Only Memories)
4
intJ
APPLICATION
AP-151
NOTE
December 1982
DECEMBER 1982
INTEL CORPORATION, 1982
ORDER NUMBER: 210888·001
4·1
AP-151
INTRODUCTION
Intel high-density EPROMs have become even more cost-effective when used in volume. In addition to reduced inventory cost and code flexibility offered by all EPROMs, Intel now has the inteligent Programming™ Algorithm. This
new technique for programming Intel 2764 and 27128 EPROMs will typically improve the efficiency of programming
equipment and labor by a factor of six, resulting in dramatic cost savings for high-volume EPROM programming
applications. The time required to program a 27128 can be reduced from 14 minutes to an average of 2.50 minutes
using this algorithm.
Since the introduction of the Intel 2716, the time required to program an EPROM cell has remained constant at 45
msec minimum. As EPROM densities doubled with the introduction of each new density, time required for
programming doubled correspondingly. Although the lYz minutes required to program a 2716 was not a burden, 14
minutes for a 128K EPROM'is considerably longer. Of course, there is a cost associated with the labor and equipment
required for programming also. If the time required to program is cut substantially, costs will be decreased also.
THE inteligent Programming™ Algorithm
The algorithm that is now used for most EPROM programming requires a fixed minimum 45 msec write pulse at each
cell. Program margin is insured by manufacturer's testing which screens-out units which do not program within that
time. This testing also guarantees that 45 msec will give adequate long-term reliability.
There is a technique that can be used to verify the level to which an EPROM storage cell has been programmed. The
level of charge storage in the cell can be determined relative to the absolute minimum level required to program the
cell to a detectable level. This is termed program "margin."
EPROM margin checking depends upon the operating characteristics of the storage cell. An erased cell with no
charge on the floating gate has a characteristic similar to an ordinary NMOS 1-V curve (Figure 1). This results in "1"
output from the EPROM. As the cell is programmed, the cell threshold as a function of select gate voltage begins to
increase. Therefore, by externally increasing Vee, which is connected to the select gate, it is possible to determine
cell threshold by observing the Vee value which causes an output to change from a "0" to a "1". As the Vee value
where this occurs exceeds 5 .25Y.the maximum specified operating value, the additional voltage required to change an
output from "0" to "1" corresponds to additional programming margin, which increases reliability.
a
t
NOT
PROGRAMMED
PROGRAMMED
"1"
CURRENT
THROUGH
TRANSISTOR
ICELLI
V T 1 (NOT PROGRAMMMED)
VTo (PROGRAMMED)
SENSE THRESHOLD
VOLTAGE ON GATE OF CELl----..
Figure 1. Storage Cell Threshold Shift
4-2
AP·151
In the case of the inteligent Programming Algorithm, aVec value of 6.0V ± 0.25V has been determined to be the "0"
to "1" transition point~which insures that each individual EPROM cell has adequate programming margin to
guarantee long-term reliability.
DEVICE
FAILED
Figure 2. Intellgent Programming™ Flowchart
4-3
AP·151
Empirical data gathered by Intel show that most bits in Intel EPROMs program in less than S msec and only a small
percentage require a longer time. U sing this information, and the technique for detecting the program margin of bits ,
it is possible to greatly reduce programming time because most require less than 16% (S msec/50 msec) of the time
used in the current algorithm.
The inteligent Programming Algorithm (See Figure 2) programs the cell in a minimum amount of time while
guaranteeing reliability through the "closed loop" technique of checking margin. The inteligent Programming
Algorithm begins by setting Vee to 6.0V to obtain the correct levelfor margin testing. Vpp is set to 21.0V, then the,
address to be programmed is selected. With correct data supplied to the outputs of the device, a 1 msec width
low-going pulse is presented to the program pin, PGM. The outputs are verified to check program margin. If the data
is not verified, the pulse is repeated and data is verified again. This may occur up to 15 times.
Once the byte has been verified, a final overprogramming pulse equivalent to 4 times the combined width of all the
one msec pulses is applied. This helps insure that the cell has received additional programming margin for reliable
operation.
In the unlikely event that the device fails to verify at Vee = 6.0Vafter afull sequence of 15 pulses of 1 msec and one 60
msec pulse, the device would be rejected as a programming failure.
Note that the maximum single pulse width of 60 msec more thim guarantees backward compatibility to all 2764s or
27128s that have been tested previously to the older 50 msec open loop algorithm. Very few bytes within a device may
actually require this amount of programming with the inteligent Programming Algorithm.
CAUTION: The inteligent Programming Algorithm has been developed specifically for Intel EPROMs. Intel cannot
guarantee that EPROMs supplied by other manufacturers can be programmed with adequate reliability when using
this algorithm.
COMMERCIAL PROGRAMMER IMPLEMENTATION
Most commercial programming equipment will be capable of accommodating the inteligent Programming Algorithm
with minor changes to hardware and software. For example, the following manufacturers offer upgrades to their
existing equipment for this algorithm.
Data 110
Model 120A or 121A
Unipak
Unipak II
Mospak
Requires purchase of
Revision D software
Revision 004 software
Revision 1
Revision 003 software
Prolog
M980 Control Unit
PM90S0 module
PA2S-S0 socket adapter
Revision B software
Intel
iUP 200 or 201
Hardware module (Available 1983)
FUTURE TRENDS
As EPROM densities continue to increase and as volumes of usage increase even more, there will be continued need for
fast algorithms to facilitate high-volume programming. The Intel 2764 and 27128 are only the first devices to feature
such an algorithm. Future higher-density EPROMs from Intel will also feature adaptive programming algorithms.
4·4
2716
16K (2K x 8) UV ERASABLE PROM
• Fast Access Time
- 2716-1: 350 ns Max.
- 2716-2: 390 ns Max.
- 2716: 450 ns Max.
- 2716-5: 490 ns Max.
- 2716-6: 650 nS.Max.
• Pin Compatible to Intel 2732A EPROM
• Simple Programming Requirements
- Single Location Programming
- Programs with One 50 ms Pulse
• Inputs and Outputs TTL Compatible
During Read and Program
• Single +5V Power Supply
• Low Power Dissipation
- Active Power: 525 mW Max.
- Standby Power: 132 mW Max.
• Completely Static
The Intel 2716 is a 16,384-bit ultraviolet erasable and electrically programmable read-only memory (EPROM).
The 2716 operates from a single 5-volt power supply, has a static standby mode, and features fast, singleaddress programming. It makes designing with EPROMs fast, easy and economical.
The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with highperformance +5V microprocessors such as Intel's 8085 and 8086. Selected 2716-5s and 2716-6s are also
available for slower speed applications. The 2716 also has a static standby mode which reduces power
consumption without increasing access time. The maximum active power dissipation is 525 mW while the
maximum standby power dissipation is only 1,32 mW, a 75% savings.
The 2716 uses a simple and fast method for programming-a single TTL-level pulse. There is no need for high
voltage pulsing because all programming controls are handled by TTL signals. Programming of any location at
any time-either individually, sequentially or at random is possible with the 2716's single-address programming. Total programming time for all 16,384 bits is only 100 seconds.
A7
A6
As
A.
A3
A2
A,
Ao
Vee
As
Ag
Vpp
OE
DATA OUTPUTS
0 0 -0 7
A,o
~
CE
07
06
00
0,
05
O2
GND
O.
03
YG.cTING
Ao-A" {
ADORESS
INPUTS
PIN NAMES
Ao-A,o
16,384-BIT
CELL MATRIX
ADDRESSES
CE
CHIP ENABLE
OE
OUTPUT ENABLE
0 0 -07
OUTPUTS
Figure 1. Pin Configuration
Figure 2. Block Diagram
Intel Corporation Assumes No Responsibllty for the Use of Any Circuitry Other Than Circuitry Embodied
© INTEL CORPORATION, INC 1982
4-5
In
an Intel Product No Other CirCUit Patent licenses S'fe Imj:!lie~
NOVEMBER 1982
2716
DEVICE OPERATION
a) the lowest possible memory power dissipation,
and
The six modes of operation of the 2716 are listed in.
Table 1. It should be noted that inputs for all modes
are TTL levels. The power supplies required are a
+5V Vcc and a Vpp. The Vpp power supply must be
at 25V during the three programming modes, and
must be at 5V in the other three modes.
b) complete assurance that output bus contention
. will not occur.
To use'these two control lines most efficiently, CE
(pin 18),should be decoded and used as the primary
device selecting function, while OE (pin 20) should
be made a common connection to all devices in the
array and connected to the READ line from the
system control bus. This assures that all deselected
memory devices are in their low-power standby
modes and that the output pins are active only when
data is desired from a particular memory device.
Read Mode
The 2716 has two control functions, both of which
must be ,ogically satisfied in order to obtain data at
the outputs. Chip Enable (CE) is the power control
and should be used for device selection. Output
Enable (OE) is the output control and should be used
to gate data from the output pins, independent of
device selection. Assuming that addresses are stable, address access time (tACC) is equal to the delay
from CE to output (tCE)' Data is available at the outputs tOE after the falling edge of OE, assuming that
CE has been low and addresses have been stable for
at least tACC-tOE'
Programming
Initially, and after each erasu re, all bits of the 2716 are
in the "1" state. Data is introduced by selectively
programming "O's" into the desired bit locations.
Although only "O's" will be programmed, both "l's"
and "O's" can be presented in the data word. The only
way to change a "0" to a "1" is by ultraviolet light
erasure.
Standby Mode
The 2716 is in the programming mode when the Vpp
power supply is at 25Vand OE is atVIH . The data to be
programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and
data inputs are TTL.
The 2716 has a standby mode which reduces the
maximum active power dissipation by 75%, from
525 mW to 132 mW The 2716 is placed in the standby mode by applying a TTL-high signal to the CE input. When in standby mode, the outputs are in a
high impedance state, independent of the OE input.
When the address and data' are stable, a 50 msec,
active-high, TTL program pulse is applied to the
CE input. A pulse must be applied at each address
location to be programmed. You can program any
location at any time-either individually, sequentially, or at random. The program pulse has a maximum
width of 55 msec. The 2716 must not be programmed
with a DC signal applied to the CE input.
Output OR·Tieing
Because 2716s are usually used in larger memory
arrays, Intel has provided a 2-line control function
that accomodates this use of multiple memory connections. The two-line control function allows for:
Table 1. Mode Selection
~
- Mode
CE
(18)
OE
(20)
Vpp
(21)
Vcc
(24)
Outputs
(9-11,13-17)
Read
VIL
-
VIL
+5
+5
DOUT
Output Disable
VIL
VIH
+5
+5
HighZ
Standby
VIH
X
+5
+5
HighZ
Program
Pulsed VIL to VIH
VIH
+25
+5
DIN
+5
DOUT
+5
HighZ
Verify
VIL
VIL
+25
Program Inhibit
VIL
VIH
+25
NOTES: 1. X can be VIL or VIH
4-6
AFN·Q0811B
inter
2716
ABSOLUTE MAXIMUM RATINGS·
·NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the devic,# at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature Under Bias .............. -10·C to +80·C
Storage Temperature ................ -65·C to +125·C
All Input or Output Voltages with
Respect to Ground ................... +6V to -0.3V
Vpp Supply Voltage with Respect
to Ground During Program ......... +26.5V to -0.3V
D.C. AND A.C. OPERATING CONDITIONS DURING READ
2716
2716-1
2716-2
2716-5
2716-6
Temperature Range
0·C-70·C
0·C-70·C
0·C-70·C
0·C-70·C
0·C-70·C
Vee Power Supply[1.21
5V ±5%
5V ±10%
5V±5%
5V ±5%
5V±5%
Vee
Vee
Vee
Vee
Vee
Vpp Power SUPply[21
READ OPERATION
D.C. CHARACTERISTICS
Limits
Symbol
Parameter
Min.
III
Input Load Current
IlO
I
[21
PP1
I
[21
ee1
Output Leakage Current
Vee Current (Standby)
lee2[21
Vee Current (Active)
Vil
Input Low Voltage
-0.1
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Units
Typ.[31
I
Vpp Current
2.4
Test Conditions
,
Max.
10
,..A
VIN = 5.25V
10
,..A
VOUT = 5.25V
5
mA
Vpp = 5.25V
10
25
mA
CE =VIH. OE =Vll
57
100
mA
OE = CE =Vll
0.8
V
Vee+ 1
V
0.45
V
IOl = 2.1 mA
V
IOH = -400,..A
~
A.C. CHARACTERISTICS
Limits (ns)
Symbol
Parameter
2716
I
2716-1
2716-2
2716-5
2716-6
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Test
Conditionst
tACC
Address to Output Delay
450
350
390
450
450
CE = OE =VIL
tCE
CE to Output Delay
450
350
390
490
650
OE = VIL
200
CE =VIL
100
CE = VIL
tOE
[41
Output Enable to Output Delay
tDF[4,61 eE or OE High to Output Float
tOH
Output Hold from Addresses, CE or
OE Whichever Occurred FIrst
120
0
0
100
120
0
0
4-7
100
160
12Q
0
0
100
0
0
100
0
0
CE = OE =VIL
AFN.Q0811B
inter
2716
Programming of multiple 2716s in parallel with the
same data can be easily accomplished due to the
simplicity of the programming requirements. Like
inputs of the paralleled '2716s may be connected
together when they are programmed with the same
data. A high-level TTL pulse applied to the CE input
programs the paralleled 2716s.
ERASURE CHARACTERISTICS
The erasure characteristics of "the 2716 are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain types of fluorescent lamps have wavelengths
in the 3000-4000 A range. Data show that c~mstant
exposure to room-level fluorescent lighting could
erase the typical 2716 in approximately 3 years, while
it would take approximately 1 week to cause erasure
w~en exposed to direct sunlight. If the 2716 is to be
exposed to these types of lighting conditions for
extended periods of time, opaque labels should be
placed over the 2716 window to prevent unintentional erasure.
Program Inhibit
Programming of multiple 2716s in parallel with different data is also easily accomplished. Except for
CE, all like inputs (including OE) of the parallel
2716s may be common. A TTL-level program pulse
applied to a 2716's CE input with Vpp at 25V will program that 2716. A low-level CE input inhibits the
othe~ 2716 from being programmed.
The recommended erasure procedure for the 2716 is
exposure to shortwave ultraviolet light which has a
wavelength of 2537 Angstroms (A). The integrated
dose (Le., UV intensity X exposure time) for erasure
should be a minimum of 15 W-sec/cm 2 . The erasure
time with this dosage is approximately 15 to 20
minutes using an ultraviolet lamp with a 12000
fJ. W/cm 2 power rating. The 2716 should be placed
within 1 inch of the lamp tubes during erasure.
Verify
A verify should be performed on the programmed
bits to determine that they were correctly programmed. The verify may be performed with Vpp at 25'1.
Except during programming and program verify, Vpp
must be at 5'1.
4-8
AFN.()()811B
2716
CAPACITANCE[41 (TA
= 25°C, f = 1 MHz)
T
Parameter
Symbol
yp.[3]
t A.C. TEST CONDITIONS
Test
Max. Units
Conditions
CIN
Input Capacitance
4
6
pF
VIN
COUT
Output Capacitance
8
12
pF
VOUT
= OV
= OV
Output Load
........... 1 TTL gate and
CL = 100 pF
Input Rise and Fall Times ........ ,,;;20 ns
Input Pulse Levels .. , ....... 0.8V to 2.2V
Timing Measurement Reference Level:
Inputs ................... 0.8V and 2V
Outputs ................. 0.8V and 2V
A.C. WAVEFORMS[11
V'H-------,.
ADDRESS
VALID
ADDRESSES
V'L _ _ _ _ _..J
V'H
-------t-......
1-+-----lcE-----o.~1
+-_________
V'H _ _ _ _ _ _ _
I·
{4,61
1>,
I...----o~
IOE
10'
1>'
O~PUT------~H~IG~H~Z~-----*_f_~~~~~
HIGHZ
VALIDOUT'PUT
NOTES:
1. Vce must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected to VCC except during programming. The supply current would then be the sum of ICC and IpPl .
3. Typical values are for TA = 25°C and nominal supply voltages.
4. This parameter is only sampled and is not 100% tested.
5. DE may be delayed up to tACC-tOE after the falling edge of CE without impact on tACC.
6. tOF 's specified from DE or CE, wh,chever occurs first
4·9
AFN·00811B
2716
PROGRAMMING CHARACTERSITICS
D.C. PROGRAMMING CHARACTERISTICS:
Symbol
TA =25°C ±5'C, VCC[1] =5V ±5%, Vpp[1,2] =25V ±1V
Parameter
Min.
Typ.
Max.
Units
Test
Conditions
Y,N = 5.25V/0.45
III
Input Current (for Any Input)
10
p,A
IpP1
Vpp Supply Current
5
mA
CE
IpP2
Vpp Supply Current During
Programming Pulse
30
mA
CE
IcC
VCC Supply Current
100
mA
V,L
Input Low Level
-0.1
0.8
V
V,H
Input High Level
2.0
VCC+ 1
V
= V,L
= V,H
A.C. PROGRAMMING CHARACTERISTICS: TA =25°C ±5'C, VCC[1] =5V ±5%, Vpp[1,2] =25V ±1V
Symbol
Parameter
Min.
Typ.
Max.
Units
tAS
Address Setup Time
2
tOES
OE Setup Time
2
p,s
tos
Data Setup Time
2
p,s
tAH
Address Hold Time
2
p,s
tOEH
OE Hold Time
2
p,s
tOH
Data Hold Time
2
tOFP
Output Enable to Output Float Delay
0
p,s
p,s
ns
CE = V,L
200
ns
CE = V,L
55
ms
200
tOE
Output Enable to Output Delay
tpw
Program Pulse Width
tpRT
Program Pulse Rise Time
5
ns
tpFT
Program Pulse Fall Time
5
ns
• A.C. CONDITIONS
45
Test
Conditions'
50
of:' TEST
Input Rise and Fall Times (10% to 90%) .......... 20 ns
Input Pulse Levels ......................... 0.8 to 2.2V
Input Timing Reference Level .............. 0.8V and ,2V
Output Timing Reference Level. , .......... 0.8V and 2V
NOTES:
1. Vee must be applied simultaneously or beforeVpp and removed simultaneously or after Vpp. The 2716 must not be inserted into
or .removed from a board with Vpp at 25 ± 1V to prevent damage to the device.
2. The maximum allowable voltage which may be applied totheVpp pin during programming is +26\1. Care must be taken when switching
the Vpp supply to prevent overshoot exceeding this 26V maximum specification.
4·10
AFN-00811B
2716
PROGRAMMING WAVEFORMS
PROGRAM
~
VERIFY
'AH
-~~-
H
DATA
K
ADDRESS
(2)
HIGHZ
DATA IN
STABLE
DATADUT
VAUD
V,L
tOFP
(G.20IllJAX)-
'OE
I-
(0.20_
MAX)
/
..
1+-\05
(2) ~-(~~.)
_';5_/
tpAT~
\
'OH
4-
-
k
IOFP
.... (0.20 MAX)
/
.~
\:';H
--
I-+--lpFT
NOTE
1 ALL TIMES SHOWN IN PARENTHESIS ARE MINIMUM TIMES AND ARE. SEC UNLESS OTHERWISE NOTED
2 tOE AND tDFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER
4·11
2732A
32K (4K x 8) UV ERASABLE PROM
• 200 ns (2732A·2) Maximum Access
Time ... HMOS*·E Technology
• Industry Standard Pinout ... JEDEC
Approved
• Compatible with High·Speed 8mHz
iAPX 186... Zero WAIT State
• Two Line Control
• Compatible with 12 MHz 8051 Family
• Low Standby Current...30 mA
Maximum
• ±10% Vcc T~lerance Available
• inteligent Identifier™ Mode
The Intel 2732A is a 5V only, 32,768 bit ultraviolet erasable and electrically programmable read-only-memory
(EPROM). The standard 2732A access time is 250 ns with speed selection (2732A-2) available at 200 ns. The
access time is compatible with high performance microprocessors such as the 8 MHz iAPX 186. In these
systems, the 2732A allows the microprocessor to operate without the addition of WAIT states.
An important 2732A feature is the separate output control, Output Enable (OE), from the Chip Enable control (CE). The OEcontrol eliminates bus contention in microprocessor systems. Intel's Application Note
AP-72 describes the microprocessor system implementation of the OE and CE controls on Intel's
EPROlv!s. AP-72 is available from Intel's Literature Department.
The 2732A has a standby mode which reduces power consumption without increasing access time. The
maximum active current is 125 mA, while the maximum standby current is only 35 mA, a 70% saving. The
standby mode is selected by applying the TTL-high signal to the CE input.
The 2732A is fabricated with HMOS*-E technOlogy, Intel's high-speed N-channel MOS Silicon Gate Technology..
-HMOS
IS
a patented process of Intel Corporation.
PIN NAMES
Ao-Al1
ADDRESSES
CE
CHIP ENABLE
OElVpp
OUTPUT ENABLEI
0 0 -07
OUTPUTS
Vpp
DATA OUTPUTS
vee 0 - - -
00:°7.
OUTPUT BUFFERS
Y·GATING
AO-A11
ADDRESS
INPUTS
32,768·BIT
CELL MATRIX
Figure 2_ Pin Configuration
Figure 1_ Block Diagram
Intel CorporatIon Assum!=ts No Responslb,lty for the Use of Any CirCUitry Other Than CircUItry Embodied 10 an Intel Product No Other CirCUit Patent LIcenses ale Implied
© INTEL CORPORATION, INC 1982
4-12
AFN.Q1545B
intJ
2732A
ERASURE CHARACTERISTICS
Standby Mode
The erasure characteristics of the 2732A are such that
erasure begins to occur upon exposure to light with
wavelengths shorter than approximately 4000 Angstroms
(A). It should be noted that sunlight and certain types of
fluorescent lamps have wavelengths in the 3000-4000A
range. Data show that constant exposure to room level
fluorescent lighting could erase the typical 2732A in ap·
proximately 3 years, while it would take approximately 1
week to cause erasure when exposed to direct sunlight. If
the 2732A is to be exposed to these types of lighting condi·
tions for extended periods of time, opaque labels should
be placed over the 2732A window to prevent unintentional
erasure.
The 2732A has a standby mode which reduces the maximum.active current from 125 mA to 35 mAo The 2732A is
placed in the standby mode by applying a TIL·high signal
to the CE input. When in standby mode, the outputs are in
a high impedance state, independent of the OE input.
Output OR-Tieing
Because EPROMs are usually used in larger memory arrays. Intel has provided a 2 line control function that ac·
commodates this use of multiple memory connection.
The two line control function allows for:
a) the lowest possible memory power dissipation. and
b) complete assurance that output bus contention will
not occur.
The recommended erasure procedure for the 2732A is
exposure to shortwave ultraviolet Iight which has a
wavelength of 2537 Angstroms (A). The integrated dose
(Le., UV intensity X exposure time) for erasure should be
a minimum of 15 W·sec/cm 2. The erasure time with this
dosage is approximately 15 to 20 minutes using an
ultraviolet lamp with 12000"W/cm 2 power rating. The
2732A should be placed within 1 inch of the lamp tubes
during erasure.
To use these two control lines most efficiently, CE (pin 18)
should be decoded and used as the primary device selecting function, while OE (pin 20) should be made a common
connection to all devices in the array and connected to the
READ line from the system control bus. This assure~ that
all deselected memory devices are in their low power
standby mode and that the output pins are active only
when data is desired from a particular memory device.
DEVICE OPERATION
PROGRAMMING
The six modes of operation of the 2732A are listed in Table
1. A single 5V power supply is required in the read mode.
All inputs are TIL levels except for OElV pp during program·
ming and 12Von Ag for~e inteligent Identifier™ mode. In
the program mode the OE/V pp input is pulsed from a TIL
level to 21V.
CAUTION: ExcflfJding 22V on Pin 20 (OENpp) win
PBrmanently damage the 2732A.
Initially, and after each erasure, all bits of the 2732A are
in the "1" state. Data is introduced by selectively pro·
gramming "O's" into the desired bit locations. Although
only "O's" will be programmed, both "1's" and "O's" can
be present in the data word. The only way to change a
"0" to a "1" is by ultraviolet light erasure.
Table 1. Mode Selection
~
MODE
CE
OE/Vpp
(18)
(20)
As
vee
OUTPUTS
(22)
(24)
(9-11.13-17)
Read
V,L
V,L
X
+5
Dour
Output DIsable
VIL
VIH
X
+5
High Z
Standby
V,H
X
X
+5
High Z
Program
V,L
Vpp
X
+5
D,N
Program Inhibit
V,H
Vpp
X
+5
High Z
Inteligent Identifier
VIL
VIL
VH
+5
Code
The 2732A is in the programming mode when the OEiVpp
input is at 21V. It is required that a 0.1 /LF capacitor be
placed across OEiVpp and ground to suppress spurious
voltage transients which may damage the device. The data
to be programmed is applied 8 bits in parallel to the data
output pins. The levels required for the address and data
inputs are TTL.
Notes 1 X can be VIH or VIL
2 VI-\
=
When the address and data are stable. a 50 msec, active
low. TTL program pulse is applied to the CE input. A program pulse must be applied a1 each address location to be
programmed. You can progr.m any location at any time
-either individually, sequentIally, or at random. The program pulse has a maximum ~idth of 55 msec. The 2732A
must not be programmed wit~ a DC signal applied to the
CE input.
'\
120 ±05V
Read Mode
The 2732A has two control functions, both of which must
be logically active in order to obtain data at the outputs.
Chip Enable (CE) is the power control and should be used
for device selection. Output Enable (OE) is the output
control and should be used to gate data from the output
pins, independent of device selection. Assuming that ad·
dresses are stable. address access time (tAcel is equal to
the delay from CE to output (tcEl. Data is available at the
outputs after the falling edge of OE. assuming that CE has
been low and addresses have been stable for at least
tACC-tOE'
Programming of multiple 2732As in parallel with the
same data can be easily accomplished due to the simplicity of the programming requirements. Like inputs of the
paralleled 2732As may be connected together when they
are programmed with the same data. A low level TIL pulse
applied to the CE input programs the paralleled 2732As.
4-13
AFN-01545B
inter
2732A
Program Inhibit
Programming of multiple 2732As in parallel with differ·
ent data is also easily accomplished. Except for CE, all
like inputs (including OE) of the parallel 2732As may be
common. A TTL level program pulse applied to a 2732A's
CE input with OElVpp at 21V will program that 2732A. A
high level CE input inhibits the other 2732As from being
programmed.
Intel will begin manufacturing 2732As during 1982 that will
contain the intellgent Identifier feature. Earlier 'generation
devices will not contain identifier information, and if eras·
ed, will respond with a "one" (VoH) on each data line when
operated in this mode. Programmed, preidentifier mode
. 2732As will respond with the current data contained in
locations 0 and 1 when subjected to the intellgent Iden·
tifier operation.
System Consideration
Verify
The power switching characteristics of HMOS-E EPROMs
require careful decoupling of the devices. The supply current, Icc, has three segments that are of Interest to the
system designer-the standby current level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enable. The
magnitude of these transient current peaks is ,dependent
on the output capacitive loading of the deviqe. The
associated transient voltage peaks can be suppressed by .
complying with Intel's Two-Line Control, as detailed in In·
tel's Application Note, AP·72, and ,by properly selected
decoupling capacitors. It is recommended that a 0.11'F
ceramic capacitor be used on every device between Vee
and GN D. This should be a high frequency capacitor of low
inherent inductance and should be placed as close to the
device as possible. In addition, a 4.71'F bulk electroly1ic
capacitor should be used between Vee and GND for every
eight devices. The bulk capacitor should be loqated near
where the power supply is connected to the array. The pur·
pose of the bulk capacitor is to overcome the voltage
droop caused by the inductive effects of PC board·traces.
A verify (Read) should be performed on the programmed
bits to determine that they were correctly programmed.
The verify is accomplished with OENpp and CE at VIL. Data
should be verified tov after the falling edge of CEo
inteligent IdentifierTM Mode
The inteligent Identifier Mode allows the reading out of a
binary code from an EPROM that will identify its manufac·
turer and type. This mode is intended for use by programm·
ing equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C
± 5°C ambient temperature range.
To activate'this mode, the programming equipment must
force 11.5V to 12.5V on address line A9 (pin 22) of the
2732A. Two identifier bytes may then be sequenced from
the device outputs by toggling address line AO (pin 8) from
VIL to VIH. All other address lines must be held at VIL during
intellgent Identifier Mode.
Byte 0 (AO
VII) represents the manufactur~r code and
byte 1 (AO = VIH) the device identifier code. For the Intel
2732A, these two identifier bytes are given in Table 2. All
identifiers for manufacturer and device codes will possess
odd parity, with the MSB (07) defined as the parity bit.
=
Table 2. 2732A Intellgent Identifier™ Bytes
~.
Idenllfler
Ao
(8)
07
0&
05
04
03
02
0,
00
Hex
(17) ,
(18)
(15)
(14)
(13)
(11)
(10)
(9)
Data
Manufacturer Code
VIL
1
0
0
0
1
0
0
I
89
Device Code
VIH
0
0
0
0
0
0
0
1
01
4-14
AfN-ol545B
2732A
ABSOLUTE MAXIMUM RATINGS*
'NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Temperature Under Bias ............ -10'Cto +80'C
Storage Temperature ............. -65'Cto +125'C
All Input or Output Voltages with
Respect to Ground ................. +6V to - 0.3V
Voltage on Pin 22 with Respect
to Ground ...................... + 13.5V to - 0.3V
Vpp Supply Voltage with Respect to Ground
During Programming .............. +22Vto -0.3V
D.C. AND A.C. OPERATING CONDITIONS DURING READ
2732A/A-2/ A-3/ A-4
I Operating Temperature Range
I Vcc Power Supply
2732A·20/A·25/A·30
0'C-70'C
O'C-70'C
5V ± 5%
5V ± 10%
READ OPERATION
D.C. CHARACTERISTICS·
Symbol
Parameter
Min.
Limits
Typ.l1J
Max.
Units
Conditions
IlL
Input Load Current
10
fAA
VIN = 5.5V
ILO
Output Leakage Current
10
fAA
VOUT = 5.5V
ICC1
Vcc Current (Standby)
35
mA
CE = VIH , OE = VIL
ICC2
Vcc Current (Active)
125
mA
OE=CE=VIL
VIL
Input Low Voltage
-0.1
0.8
V
VIH
Input High Voltage
2.0
Vcc +1
V
VOL
Output Low Voltage
0.45
V
10L = 2.1 mA
VOH
Output High Voltage
V
IOH = -400 /LA
2.4
-
A.C. CHARACTERISTICS
,
Symbol
Parameter
2732A·2
2732A·20
Address to Output Delay
tCE
CE to Output Delay
200
tOE
t [2]
OE to Output Delay
70
tOH
2732A·3
2732A·30
2732A·4
Min. Max. Min. Max. Min. Max. Min. Max. Units
tACC
OF
2732A
2732A·25
OE High to Output Not Driven
0
OutputJ::!.0ld from Addresses,
CE or OE Whichever Occurred
First
0
60
300
450
ns
CE = OE =VIL
250
300
450
ns
OE = VIL
100
150
150
ns
CE = VIL
130
ns
CE =VIL
ns
CE = OE = VIL
250
200
0
0
Test
Conditionst
60
0
0
130
0
0
tA.C. TEST CONDITIONS
Output Load .......•....... 1 TTL gate and CL = 100 pF
Input Rise and Fall Times ...................... '" 20 ns
Input Pulse Levels ....................... 0.45Vto 2.4V
Timing Measurement Reference Level:
Inputs ................................ 0.8 and 2.0V
Outputs .............................. 0.8 and 2.0V
4·15
AFN.()1545B
intJ
2732A
CAPACITANCE [2J (TA = 25°C, 1.= 1 MHz)
Symbol
Parameter
CIN1
Input Capacitance
Except OE/Vpp
CIN2
OE/Vpp Input
Capacitance
COUT
Output Capacitance
Typ.
Max.
4
6
pF
VIN = OV
20
pF
VIN = OV
12
pF
VOUT = OV
8
Unit Conditions
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
, 3V
"=X
20
08
045
>
2.0
TEST POINTS'<
OA
1N914
x-=
33KU
DEVICE
UNDER
TEST
OUT
ICc
-- 100 pF
=
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A lOGIC 1 ANO 0 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND a 8V FOR A LOGIC a
CL
=
100pF
CL INCLUDES JIG CAPACITANCE
A.C. WAVEFORMS
V , H - - - - - -....
ADDRESS
VALID
ADDRESSES
VIL-------'
V,H
--------1-.. . .
ill
V,H
--------1-----....
tCE'---~
OeNpp
V,H
OUTPUT ____________~HI~G~H~Z~_ _ _ _ _ __t~~~~
HIGHZ
V,l
4-16
AFN:O'5458
2732A
PROGRAMMING[4]
D.C. PROGRAMMING CHARACTERISTICS: TA = 25 ± 5°C, Vcc = 5V ± 5%, Vpp = 21V ± 0.5V
Limits
Symbol
Parameter
III
Input Current (All Inputs)
VOL
Output Low Voltage During Verify
V OH
Output High Voltage During Verify
Icc
Vcc Supply Current
V 1L
Input Low Level (All Inputs)
, V 1H
Min.
Ipp
V pp Supply Current
A9 inteligent Identifier Voltage
Max.
Units
10
f'A
0.45
V
IOL=2.1 rnA
V
10H= -400f'A
2.4
85
125
Test Conditions
V1N = V1L or V1H
rnA
-0.1
0.8
V
2.0
V cc + 1
V
30
rnA
11.5
12.5
Input High Level (All Inputs Except OElV pp)
V1D
Typ.
CE=V1L,OE=Vpp
V
A.C. PROGRAMMING CHARACTERISTICS: TA = 25 ± 5°C, Vcc = 5V ± 5%, Vpp = 21V ± 0.5V
Limits
Symbol
Parameter
t AS
Address Setup Time
tOES
Min.
Typ.
Max.
Units
2
f's
OE Setup Time
2
f'S
tDS
Data Setup Time
2
f'S
tAH
Address Hold Time
0
f'S
tOEH
OE Hold Time
2
f's
tDH
Data Hold Time
2
f's
0
130
ns
tDFP
Chip Enable High to Output Not Driven
tDV
Data Valid from ~
tpw
CE Pulse Width During Programming
45
tpRT
<:>t Pulse Rise Time During Programming
50
ns
tVR
Vpp Recovery Time
2
f's
50
Test Conditionst
1
f's
55
ms
CE=V 1L, nt::=V 1L
tA.C. TEST CONDITIONS
Input Rise and Fall Times (10% to 90%) ......... :5 20 ns
Input Pulse Levels ....................... 0.45V to 2.4V
Input Timing Reference Level .......... 0.8V and 2.0V
Output Timing Reference Level ......... Q.8V and 2.0V
NOTES:
1. Typical values are for TA = 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested. Output float is defined as the point where data is no longer driven see timing diagram on page 4-18
3. OE may be delayed up to IACC-IOE after the falling edge of CE without impacting IACC.
4. When programming the 2732A, a 0.1/,F capacitor is required across OEIVpp and ground to suppress spurious voltage
transients whi~h may damage the device.
4·17
AFN-01545B
2732A
PROGRAMMING WAVEFORMS
~----------------PROGRAM---------------~f+-----
V,H
AOORESSES
V,L
HIgh Z
DATA - - - - {
V,L
'ov
[11
Vpp
[
I
cj£lVpp
tOES
[2[
V'H _ _ _ _ _ _ _ _"""'\I
I ~EH
[[21
~
I
NOTES
1 ALL TIMES SHOWN IN [I ARE MINIMUM AND IN .SEC UNLESS OTHERWISE SPECIFIED
2 THE INPUT TI~rNG REFERENCE LEVEL IS 0 BV FOR A VrL AND 2V FOR A V1H
4-18
AFN-01545B
inter
2764
64K (SK x S) UV ERASABLE PROM
• inteligent Programming™ Algorithm
Industry Standard Pinout •.• JEDEC
• Approved
• Low Active Current...100mA Max.
• ±10% Vcc Tolerance Available
200 ns (2764-2) Maximum Access
• Time
••• HMOS*-E Technology
with High·Speed 8mHz
• Compatible
iAPX 186... 2ero WAIT State
• Two Line Control
• Pin Compatible to 27128 EPROM
The Intel 2764 is a SV only, 6S,S36-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The
standard 2764 access time is 2S0 ns with speed selection available at 200 ns. The access time is compatible with highperformance microprocessors such as Intel's 8 mHz iAPX 186. In these systems, the 2764 allows the microprocessor to
operate without the addition of WAIT states. The 2764 is also compatible with the 12 MHz 80S1family.
An important 2764 feature is the separate output control, Output Enable (OE) from the Chip Enable control (CE). The OE
control eliminates bus contention in microprocessor systems. Intel's Application Note AP-72 describes the
microprocessor system implementation of the OE and CE controls on Intel's EPROMs. AP·72 is available from Intel's
Literature Department.
The 2764 has a standby mode which reduces power consumption without increasing access time. The maximum active
current is 100 mA, while the maximum standby current is only 40 mAo The standby mode is selected by applying a TTLhigh signal to the CE input.
± 10% Vee tolerance is available as an alternative to the standard ±S% Vee tolerance for the 2764. This can allow the system
designer more leeway with regard to his power supply requirements and other system parameters.
The 2764 is fabricated with HMOS'-E technology, Intel's high-speed N-channel MOS Silicon Gate Technology.
:l!
~
OATA OUTPUTS
Vee 0-------+
GND_
Vpp_
00-0.,
~
Vpp
vpp
A12
A,
A12
A,
<
~
A,
A,
Y-QATING
85,53I-BIT
CELL MATRIX
A,
A,
A,
A,
O.
0,
0,
Gnd
Gnd
Gnd
Gnd
(27)
(24)
Vpp
I')
Vee
(0)
V,"
X
Vee
Vee
Dour
vee
Vee
Hlghl
""'hZ
IH)
v,
V"
OlilpulD'sable
v"
v,"
S..nd~
V
Program
v"
V,H
Verify
V,
V"
Program Inhibit
V,
X
In1ehgenlldentl'.,
V,
v"
V,H
...
A"
A"
As
As
Ag
A"
DE
A10
Ag
A"
DE
A,.
CE
CE
CE
CE
0,
0,
O.
0,
0,
0,
0,
O.
Os
0,
0,
0,
O.
Os
0,
0,
00
Os
0,
0,
V
""'-
V
X
0......
(11·13,11-
-'11
v,"
,
X
X
V
V
V
X
Vpp
Vee
V,H
X
¥pp
Vee
Dour
X
"'.
PIN NAMES
A.-A"
CE
OE
¥pp
Vee
HI hZ
Vee
Vee
Code
0.-0
Yo
V
D,
PGM
N.C.
In'ellgent
Pr~.mmlnL
As
Figure 2. Pin Configurations
..
1201
X
As
A,
Vpp A"
De OENpp
A10 A,.
A,
O.
0,
0,
Vee
A,
As
0,
0,
Vee
BLOCKS ADJACENT TO THE 2784 PINS
....
X
A,
O.
0,
0,
MODE SELECTION
::;-.::
M"'"'
~
Vee
NOTE INTEL UNIVERSAL SITE .coMPATIBLE EPROM PIN CONFIGURATIONS ARE SI-K)WN IN THE
Figure 1. Block Diagram
Oi
l'ii
~
PGM A14
A,
A,
00
~
~
Vee
As
AS
<
w
~
. .
."" .. . ..""
OUTPUT BUFFERS
co
2764
w
.."" ."" .."" ..""
As
-
~
ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
OUTPUTS
PROGRAM
NO CONNECT
1 X can be VIH or VIL
2 VH = 120V ::t:05V
'HMOS Is a patented process of Intel Corporation
Inlel Corporation Assumes No Responslbllty for the Use of Any Circuitry Other Than Circuitry Embodied In an It'ltel Product No Other Circuit Patent Licenses are Implied
OINTELCORPORATION, 1982
4-19
NOVEMBER 1982
ORDER NUMBER: 210570.Q02
2764
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
~ those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias .............. -10'e to +80'e
Storage Temperature ................ -S5'e to +125'e
All Input or Output Voltages with
Respect to Ground .......•........ + 7.0V to -O.SV
Voltage on Pin 24 with
Respect to Ground ................. + l3.5V to -O.SV
Vpp Supply Voltage with Respect to
Ground During Programming ........ +22V to -O.SV
D.C. AND A.C. OPERATING CONDITIONS DURING READ
Operating Temperature
Range
2764-2
2764
2764-3
2764-4
2764-25
2764-30
2764-45
O'C-70'C
O'C-70'C
O'C-70'C
O'C-70'C
O'C-70'C
0'C-70'C
O'C-70'C
5V:!: 5%
5V:!: 5%
5V:!: 5%
5V:!: 5%
5V :!: 10"/~
5V:!: 10"/0
5V :!: 10"/0
Vee Power Supply 1 .2
Vpp Voltage 2
Vpp = Vee Vpp = Vee Vpp = Vec Vpp = Vee Vpp = Vee Vpp = Vee Vpp = Vee
READ OPERATION
D.C. CHARACTERISTICS
Limits
Symbol
Parameter
Min
TypO
'Max
Unit
III
Input Load Current
10
p.A
Y,N = 5.5V
Conditions
VOUT = 5.5V
ILO
Output Leakage Current
10
p.A
IpPl'
Vpp Current Read
5
rnA
Vpp = 5.5V
ICC1'
Vcc Current Standby
40
rnA
CE = V,H
ICC2'
VCC Current Active
109
rnA
CE = OE = V,L
VIL
Input Low Voltage
-.1
+.8
V
V,H
Input High Voltage
2.0
VCC+ 1
V
VOL
Output Low Voltage
.45
V
10L = 2.1 rnA
VOH
Output High Voltage
V
10H = -400 p.A
70
2.4
A.C. CHARACTERISTICS
2764-2 Limits
Symbol
Parameter
Min
Max
2764-25 &
2764 Limlls
Min
M,IX
2764-30 &
2764-3 Limits
Min
Max
2764-45 &
2764-4 limits
Min
Max
Unit
Test
Conditions
tAee
Address to Output Delay
200
250
300
450
ns
CE=OE=V IL
teE
CE to Output Delay
200
250
300
450
ns
OE=V 1L
OE to Output Delay
75
100
120
150
ns
CE=V 1L
130
ns
CE=V 1L
ns
CE=OE=V IL
tOE
tOF
4
tOH
NOTES: 1
2
3.
4.
OE High to Output Float
0
Output Hold from Addresses.
CE or OE Wh,chever Occurred
First
0
60
0
0
60
0
0
105
0
0
.
Vee must be applied simultaneously or before Vpp and removed SImultaneously or after Vpp •
Vpp may be connected directly to Vee except during programming. The supply current would then be the sum of Icc and Ip",
TYPIcal values are for tA = 25'C and nominal supply voltages
'
This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer
driven - see timing diagram on page 4-21
4-20
AFN-ol647B
inter
2764
CAPACITANCE
Symbol
C'N'
COUT
(T A = 25°C, f = 1 MHz)
Parameter
Typ.'
Max.
Unit
Input Capacitance
4
6
pF
V'N=OV
Output Capacitance
8
12
pF
VOUT=OV
Conditions
A.C. TESTING INPUTfOUTPUT WAVEFORM
...
0.5
=x::>
TEST POINTS
A.C. TESTING LOAD CIRCUIT
..!fL
:.:>e
~'N9"
<
3.3Kil
DEVICE
UNDER
TEST
_ OUT
I-=-
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND 0 "5V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 08V FOR A LOGIC 0
100 pF
CL
CL 100 pF
CL INCLUDES JIG CAPACITANCE
A.C. WAVEFORMS
V,H - - - - - - " ' " \
ADDRESS
VALID
ADDRESSES
V,L------V,H
V,L
--------t-_,.
1'"----------....
--------t-----"'"\
I~..
I__---ICE'-----'
V,H
~-----,ACC..- - - - _ I
V,H
OUTPUT _ _ _ _ _ _ _~HI~G~H~Z~~----_+~~~r<
HIGHZ
V,L
NOTES:
t TYPical values are for TA = 25·C and nominal supply voltages
2 ThiS parameter 's only sampled and,s not tOO"A. tested
3 i5E may be delayed up to tACC - 10, after the falhng edge of CE w,thout ,mpact on !..cc.
4. to. 's spec,f,ed from OE or CE, wh'chever occurs f".t.
4·21
AFN-O'6478
intJ
2764
STANDARD PROGRAMMING
D.C. PROGRAMMING CHARACTERISTICS:
TA
= 25
= 5V
:!:5 e C, Vee
:!:5%, V pp
= 21V
:!:0.5V (see Note 1)
Limits
Symbol
Parameter
Input Current (All Inputs)
Vll
Input Low Level (All Inputs)
VIH
Input Hight Level
VOL
Output Low Voltage During Verify
VOH
Output High Voltage During Verify
ICC2
Vce Supply Current (Program & Verify)
IpP2
Vpp Supply
VID
AS for inteligent Identifier Voltage
Curren~
Max.
Unit
10
p.A
-0.1
O.B
V
2.0
VCC+1
V
0.45 '
Min.
III
2.4
(Program)
A.C. PROGRAMMING CHARACTERISTICS:
TA
11.5
= 25
:!:5'C, Vee
= Vll
V
IOl
V
IOH
= 2.1 mA
= -400 p.A
CE
= Vll = PGM
100
mA
30
mA
12.5
V
= 5V
:!:5%, V pp
Test Conditions
VIN
= 21V
or VIH
:!:0.5V (see Note 1)
Limits
Parameter
Min.
tAO
Address Setup Time
2
toE'
OE Setup Time
2
p's
tos
Data Setup Time
2
p's
tAH
Address Hold Time
O.
p's
tOH
Data Hold Time
2
Output Enable to Output Float Delay
0
Symbol
t OFP
2
tv.
V.P Setup Time
t pw
PGM Pulse Width During Programming
leES
CE Setup Time
tOE
Data Valid from OE
Typ.
Max.
Test Conditions'
p's
p's
130
ns
55
ms
2
45
Unit
p's
50
2
p's
150
ns
• A.C. CONDITIONS OF TEST
Input Rise and Fall Times (10% to SO%).
. .20ns
Input Pulse Levels ..................... 0.45V to 2.4V
Input Timing Reference Level ............ O.BV and 2.0V
Output Timing Reference Level. ; ....... O.BV and 2.0V
NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data
longer driven - see timing diagram on page 4·23
4·22
IS
nO
AFN·01647B
intJ
2764
STANDARD PROGRAMMING WAVEFORMS
'1,.
ADDRESSES
-
)
PROGRAM
VERIFY
ADDRESS STABLE
DATA OUT VALID
I--{ij--
-=l
I
~
DATA IN STABLE
DATA
HIg/IZ
r-[oj
DATA OUT JALID
'(
-
~[2j·
1--121--
C
t DFP
'-r,oMAX'3J
V"
V"
V"
V,.
CE
V"
J
1--12j--
1\
I - ~i--
'1,.
PGM
V"
'1,.
CE
1.
2
3.
4.
~)
--
t~
l45msee ]
f-
f-12i
-1 1+-[0":,'5J"\
'1"
MAX
ALL TIMES SHOWN IN [1 ARE MINIMUM AND IN ,.sEC UNLESS OTHERWISE SPECIFIED.
THE INPUT TIMING REFERENCE LEVEL IS .BV FOR V,L AND 2V FOR A V,H .
tOE AND tDFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER.
WHEN PROGRAMMING THE 2764, A O.I~F CAPACITOR IS REQUIRED ACROSS VPP AND GROUND TO SUPRESS
SPURIOUS VOLTAGE TRANSIENTS WHICH CAN DAMAGE THE DEVICE.
ERASURE CHARACTERISTICS
The erasure characteristics of the 2764 are such that erasure
begins to occur upon exposure to light with wavelengths
shorter than approximately 4000 Angstroms (A). It should be
.noted that sunlight and certain types of fluorescent lamps
have wavelengths in the 3000-4000 A range. Data show that
constant exposure to room level fluorescent lighting could
erase the typical 2764 in approximately3 years, while it would
take approximately 1 week to cause erasure when exposed to
direct sunlight. If the 2764 is to be exposed to these types of
lighting conditions for extended periods of time, opaque
labels should be placed over the 2764 window to prevent
unintentional erasure."
The recommended erasure procedure for the 2764 is exposure to shortwave ultraviolet light which has a wavelength of
4-23
2537 Angstroms (A). The integrated dose (Le., UV intensity x
exposure time) for erasure $hould be a minimum of 15 Wsec/cm 2• The erasure time with this dosage is approximately
15 to 20 minutes using an ultraviolet lamp with a 12000
pW/crr{J- power rating. The 2764 should be placed within 1 Inch
of the lamp tubes during erasure. The maximum Integrated
dose a 2764 can be exposed to without damage is 7258
Wseclcm2 (1 week @ 12000 ,.W/cm~. Exposure of the 2764 to
high Intensity UV light for long periods may cause permanent
damage.
DEVICE OPERATION
The eight modes of operation of the 2764 are listed in Table
1. A single 5V power supply is required In the fead mode.
All Inputs are TIL levels except for Vpp and 12V on A9 for
inteligent Identifier mode.
AfI«)'847B
2764
System Considerations
Table 1. MODE SELECTION
~
(20) (22) (27) (24)
Read
VIL VIL VIH
X
Vee Vee
Output Disable.
Vil VIH VIH
X
VCC VCC
Standby
VIH
X
X
Program
VIL VIH
VIL
Verify
VIL VIL VIH
MODE
Outputs
CE O! PGM Ag Vpp Vee (11-13,15·
(1) (28)
Program InhIbIt
X
VIH X
mtehgent IdentIfIer VIL VIL VIH
mtehgent
Programmmg
VIL VIH VIL
NOTES:
-19)
X
Vee Vee
Vpp Vee
X Vpp Vee
DOUT
HighZ
HlghZ
X
DIN
X
Vpp Vee
DOUT
HlghZ
VH Vee Vee
Code
X
Vpp Vee
DrN
1 X can be VIH or Vil
2 VH=120V",OSV
READ MODE
The 2764 has two control functions, both of which must be
logically active in order to obtain data at the outputs. Chip
Enable (CE) is the power control and should be used for
device selection. Output Enable (OE) is the output control
and should be used to gate data from the output pins, independent of device selection. Assuming that addresses are
stable, the address access time (tACC) is equal to the delay
from CE to output (tcel. Data is available at the outputs
after a delay of tOE from the falling edge of OE, assuming
that ~ has been low and addresses have been stable for at
least tACC':" tOE.
STANDBY MODE
The 2764,has standby mode which reduces the maximum
active current from 100 mA to 40 mAo The 2764 Is placed in
the standby mode by applying a TIl·high signal to the CE
input. When in standby mode, the outputs are in a high im·
pedance state, independent of the OE input.
Outpuf OR·Tieing
Because EPROMs are usually used in larger memory arrays,
Intel has provided 2 control lines which accommodate thiS
multiple. memory connection. The two control lines allow for:
a) the lowest possible memory power dissipation"and
b) complete assurance that output bus'contention will not
occur.
To use these two control lines most efficiently, CE (pin 20)
should be decoded and used as the primary device selecting
function, while OE' (pin 22) should be made a common connection to all devices in the array and connected to the READ
line from the system control bus. This assures that all deselected memory devices are in their low power standby
mode and that the output pins are active only when data is
desired from a particular memory device.
The power switching characteristics of HMOS-E EPROMs
require careful decoupling of the devices. The supply currerit, 'CC, has three segments that are of interest to the system designer - the standby current level, the active current
level, and the transient current peaks that are produced by
the falling and rising edges of Chip Enable. The magnitude of
these transient cu rrent peaks is dependent on the output
capacitive loading of the device. The associated transient
voltage peaks can be suppressed by complying with Intel's
Two·line Control, as detailed in Intel's Application Note, AP72, and by properly selected decoupling capacitors. It is recommended that a 0.1 /LF ceramic capacitor be used on
every device between VCC and GND. This should be a high
frequency capacitor of low inherent inductance and should
be placad as close to the device as possible. In addition, a 4.7
/LF bulk electrolytic capacitor should be used between Vec
and GND for every eight devices. The bulk capacitor should
be located near where the power supply is connected to the
array. The purpose of the bulk capacitor is to overcome the
vpltage droop caused by the inductive effect of PC board·
traces.
PROGRAMMING MODES
CBution: ExfHlding 22V on pin 1 (V,.I w/H
pemIIInBntly
dBmlllIfI thB 2764.
Initially, and after each erasure, all bits of the 2764 are in the
"1" state. Data is introduced by selectively programming "Os"
into the desired bit locations. Although only "Os" will be
programmed, both "1s" and "Os" can be present in the data
vyord. The only way to change a "0" to a "1" is by ultraviolet
light erasure.
The 2764 is in the programming mode when Vpp input is at
21V and CE and PGM are both at TTL low. The data to be
programmed is applied 8 bits in parallel to the data output
pins. The levels required for the address and data inputs
are TTl.
Standard Programming
For programming, CE should be kept TIl·low at all times
while Vpp is kept at 21V. When the address and data are
stable, a 50 msec, active-low, TIL program pulse is applied to
the PGM Input. A program pulse must be applied at each ad·
dress location to be programmed. You can program any loca·
tlon at any time-either individually, sequentially, or at random. The program pulse has a maximum width of
55 msec.
Programming of multiple 2764s in parallel with the same data
can tie easily accomplished due to the simplicity of the programming requirements. like inputs of the paralleled 2764s
may be'connected together when they are programmed with
the same data. A low-level TTL pulse applied to the PGM
input programs the paralleled 2764s.
Program Inhibit
Programming of multiple 2764s in parallel with different data
is also easily accomplished by using the Program inhibit
4·24
AfN.Ol841B
inter
2764
Figure 3. 2764 intellgent Programmlng™ Flowchart
mode. A high-level CE or PGM input inhibits the other 27645
from being programmed. Except for CE, all like Inputs (Including OE) of the parallel 27645 may be common. A TTL lowlevel pulse applied to a 2764 CE and PG"M input with Vpp at
21V will program that 2764.
Verify
A verify should be performed on the programmed bits to
determine that they were correctly programmed. The verify is
performed with CE and OE at VIL, PGM at VIH and Vpp at 21V.
inteligent Programming™ Algorithm
The 2764 inteligent Programming Algorithm allows Intel
27645 to be programmed in a significantly faster time than
the standard 50 msec per·byte programming routine.
Typical programming times for 27645 are on the order of a
minute and a half, which is a five-fold reduction in programming time from the standard method. This fast algorithm
results in the same reliability characteristics as the stan·
dard 50 msec algorithm. A flowctiart of the inteligent Programming Algorithm is shown in Figure 3. This is compatible with the 27128 inteligent Programming Algorithm.
4-25"
AFN-oI647B
2764
With the standard programming method, data is programmed into a selected 2764 location by a single 50 msec,
active-low, TTL pulse applied to the PGM pin. The inte'igent Programming Algorithm utilizes two different
pulse types: initial andoverprogram. The duration of the initial PGM pulse(s) is one millisecond, which will then be
followed by a longer overprogram pulse of length 4X msec.
X is an iteration counter and is equal to the number of the
initial one millisecond pulses applied to a particular 2764
location, before a correct verify occurs. Up to 15 onemillisecond pulses per byte are provided for before the
overprogram pulse is applied.
The entire SBquence of progmm pulses and byte vfHifications is
performf1(/at Vee = 6.0Vand Vpp= 21.0V. When the inte'igent
Programming cycle has been completed, all bytes should be
compared to the original data with Vee = Vpp = 5.0V.
inteligent Programming™ Algorithm
D_C_ PROGRAMMING CHARACTERISTICS: TA
Symbol
Parameter
= 25
±5°C;-Vee
= 6.0V ±O.25V, Vpp = 21V
Limits
Max.
Min.
Unit
III
Input Current (All Inputs)
V,L
Input Low Level (All Inputs)
V,H
Input Hight Level
VOL
Output Low Voltage During Verify
VOH
Output High VoJtage During Verify
lee2
Vee Supply Current (Program & Verify)
100
mA
'pP2
Vpp Supply Current (program)
30
mA
VID
A9 for inteligent Identifier Voltage
12.5
V
A.C. PROGRAMMING CHARACTERISTICS: TA
10
/LA
-0.1
0.8
V
2.0
Vee+ 1
V
0.45
2.4
11.5
= 25
±5°C, Vee
±O.5V (see Note 1)
Test Conditions
Y,N = V,L or V,H
V
IOL
V
IOH
= 2.1 mA
= -400/LA
CE
= V,L = PGM
= 6.0V ±O.25V, Vpp = 21V ±O.5V (see Note1)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
Address Setup Time
2
/LS
tOES
OE Setup Time
2
/LS
tos
Data Setup Time
2
/LS
tAH
Address Hold Time
0
/LS
tOH
Data Hold Time
2
tOF
Output Enable to Output Float Delay
0
tyPS
Vpp Setup Time
2
tyes
Vee Setup Time
tpw
PGM Initial Program Pulse Width
0.95
topw
PGM Overprogram Pulse Width
3.8
teEs
CE Setup Time
tOE
Data Valid from OE
tAS
• A.C. CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) .......... 20 ns
Input Pulse Levels ...................... 0.45V to 2.4V
Input Timing Reference Level ........... 0.8V and 2.0V
Output Timing Reference Level .......... 0.8V and 2.0V
Test Conditions·
/LS
130
ns
/LS
2
/LS
1.0
1.05
ms
(see Note 3)
63
ms
(see Note 2)
2
/LS
150
ns
NOTES:
1. Yee must be applied simultaneously or before Vpp and
removed simultaneously or aiter ypp.
2. The length of the overprogram pulse will vary from 3.8 msec
to 63 msec as a function of the iteration counter value X.
3. Initial Program Pulse width tolerance is 1 msec ± 5%.
4. This parameter is only sampled and is not 100% tested. Out·
put Float is defined as the point where data is
• no longer driven - see timing diagram on page 4-27
4-26
AFN·Ol647B
2764
inteligent Programming™ WAVEFORMS
PROGRAM
----.J
ADDRESSES
VERIFY
ADDRESS STABLE
DATA OUT VALID
~
f.--I'2'J-~
DATA IN STABLE
DATA
1--I'2'J-
---
High Z
C
-I'OJ
DATA OUT JALID
-
1+]'2J-
'OFP
-[013J
MAX
v••
---.I _',21_
v"
Vee ->-1
Vee
Vee
v,"
CE
V"
---.I
-
_'ves-+
121
,
\
-1',]-
V,"
PGM
~
V"
V,"
OE
V"
---
-
'pw
[.9Smsl
topw
[3.8msl
I-
1-
10,11
"\
i-
'0'
_[0151_
MAX
1. ALL TIMES SHOWN IN [J ARE MINIMUM AND IN ~SEC UNLESS OTHERWISE SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS .8V FOR V'L AND 2V FOR A V'H'
3. tOE AND tDFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER.
4. WHEN PROGRAMMING THE 2764, A O.l~F CAPACITOR IS REQUIRED ACROSS Vpp AND GROUND TO SUPRESS
SPURIOUS VOLTAGE TRANSIENTS WHICH CAN DAMAGE THE DEVICE.
4-27
AFN-Ol647B
2764
r
inteligent Identifier™ Mode
The inteligent Identifier Mode allows the reading out of a
binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching
the device to be programmed with its corresponding programming algorithm. This mode is functional in the 25°C
± 5°C ambient temperature range.
Byte 0 (AO = VILl represents the manufacturer code and byte
1 (AO = VIH) the device identifier code. For the Intel 2764,
these two identifier bytes are given in Table 2. All identifiers
for manufacturer and device codes will possess odd parity,
with the MSB (D7) defined as the parity bit.
During 1982, Intel will begin manufacturing 2764s that will
contain the inteligent Identifier feature. Earlier generation
devices will not contain identifier information, and if erased,
will respond with a "one" (VOH) on each data line when
operated in this mode. Programmed, pre-identifier mode
2764s will 'respond with the current data contained in
locations 0 to 1 when subjected to the inteligent Identifier
operation.
To activate this mode, the programming equipment must
force 11.5V to 12.5Von address line A9 (pin 24) of the 2764.
Two identifier bytes may then be sequenced from the device
outputs by toggling address line AO (pin 10) from VIL'to VIH.
All other address lines must be held at VIL during
inteligent Identifier Mode.
Table 2. 2764 inteligent IdentifierTM Bytes
~
Identifier
Ao
07
Os
05
04
03
02
01
00
(10)
(19)
(18)
(17)
(1&)
(15)
(13)
(12)
(11)
Hex
Data
Manufacturer Code
VIL
1
0
0
0
1
0
0
1
89
Device Code
VIH
0
0
0
0
0
0
1
0
02
4-28
AFN·016476
27128
128K (16K x 8) UV ERASABLE PROM
• 250 ns Maximum Access Time ...
HMOS*·E Technology
• Compatible with H igh·Speed 8 MHz
iAPX 186...Zero WAIT State
• Industry Standard Pinout ... JEDEC
Approved
• Two·Line Control
• Pin Compatible to 2764 EPROM
• Low Active Current ... 100 mA Max.
•
± 10% Vee Tolerance Available.
• inteligent Programming™ Algorithm
The Intel 27128 is a 5Vonly, 131 ,072-bit ultraviolet erasable and electrically programmable read-only memory
(EPROM). The standard 27128 access time is 250 ns which is compatible with high-performance microprocessors such as Intel's 8 MHz iAPX 186. In these systems the 27128 allows the microprocessor to operate without
the addition of WAIT states. The 27128 is also compatible with the 12 MHz 8051 family.
An important 27128 feature is the separate output control, Output Enable (DE) from the Chip Enable control
(CE). The OE control eliminates bus contention in microprocessor systems. Intel's Application Note AP-72
describes the microprocessor system implementation of the OE and CE controls on Intel's EPROMs. AP-72 is
available from Intel's Literature Department.
The 27128 has standby mode which reduces the power consumption without increasing access time. The
maximum active current is 100 mA, while the maximum standby current is only 40 mA. The standby mode is
selected by applying a TIL-high signal to the CE input.
±10% Vee tolerance is available as an alternative to the standard ±5% Vee tolerance for the 27128. This can
allow the system designer more leeway with regard to his power supply requirements and other system
parameters.
The 27128 is fabricated with HMOS*-E technology, Intel's high-speed N-channel MOS Silicon Gate Technology.
DATA OUTPUTS
00·07
Vee 0 - - - - GNDO---VppO---
aE
11111111
OUTPUT ENABLE [
CHIPA~~A8LE
PGM
a Ao-A13
ADDRESS
INPUTS
OUTPUT BUFFERS
PROG lOGIC
-==
y
DECODER
----;-
Y GATING
~
=:=:
x
DECODER
131 ,on BIT
CELL MATRIX
-
MODE SELECTION
~
~
CE OE PGM A,9 Ypp Vee
Outputs
(20) (22) (27) (24) (1) (28) (11-13,15-19)
Read
V" V"
V,H
X
Output Disable
V,l V,H
V,H
X VCC Vpp
High Z
High Z
Ve,
Vc,
~
j:!
N
Standby
V,H
X
X
X
Ve
V" V,H
V"
X
Vpp Vee
Verify
V,H
X
Vpp Vee
DIN
Dour
Program Inhibit
V" V"
V,H X
X
X
Vpp Ve
High Z
m1ellgenl tdenltfler
V" V"
V,H
VH
Vee Vee
Code
Inlellgent Programmmg V" V,H
V"
X
Vpp Vee
D,N
..
~
~
27128
~
~
~
..~ ..
~
~
Vpp
Vpp
v"
Vee
Vee
Vee
A12
A,
A6
A5
A,
A,
A,
A,
Ao
00
POM
PGM
A,
A6
A5
A,
A,
A,
A,
Ao
00
A"
A13
A.
A,
0,
0,
00
0,
0,
0,
0,
0,
A"
A,
A,
A5
A,
A,
A,
A1
AO
00
0,
0,
Gnd
Gnd
Gnd
Gnd
A,
A,
Ao
00
0,
NOTE
A,
A6
A5
A,
A,
A,
A,
Ao
A"
Vee
Vee
N.C.
A.
A,
A,
A,
A,
A.
A,
A.
ONO
A"
Vpp
A"
A"
A"
OE
A10
OE
QEJI/pp
DE
DE
AlO
A'0
A '0
AlO
eE
CE
CE
CE
CE
0,
0,
05
0,
0,
0,
0,
0,
06
06
05
05
0,
06
05
0,
0,
0,
0,
0,
0,
06
05
0,
0,
INTEL UNiVERSAL SITE COMPATIBLE EPROM PIN CONFIGURATIONS ARE SHOWN IN THE
BLOCKS ADJACENT TO T HE 27128 PINS
Dour
Program
Vee
..~
A12
A,
A6
A5
A,
A,
Figure 1. Block Diagram
Mode
ill
Fig ure 2. Pin Configurations
PIN NAMES
AO-A13
CE
DE
0-0
NOTES
1 X can be VIH or V1L
PGM
. NC
2 VH-=-120Y"'O.5V
ADDRESSES
CHIP ENABLE
OUTPUT ENABLE
OUTPUTS
PROGRAM
NO CONNECT
'HMOS is a patented process of Intel Corporation.
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied In an Intel Product No Other
':9 INTEL CORPORATION 1982
4-29
CirCUit
Patent Licenses
8le
Implied.
NOVEMBER 1982
ORDER NUMBER, 210224·003
inter
27128
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias .............. -10'C to +80'C
Storage Temperature ................ -65'C to +125'C
All Input or Output Voltages with
Respect to Ground ................. + 7.0V to -0.6V
Voltage on Pin 24 with
Respect to Ground ................. +1.3.5V to -0.6V
Vpp Supply Voltage with Respect to Ground
During Programming ................ +22V to -0.6V
D.C. AND A.C. OPERATING CONDITIONS DURING READ
Operating Temperature
Range
Vee Power Supply 1.2
Vpp Voltage2
27128
27128-3
27128·4
27128-25
27128-30
27128·45
0'C-70'C
0'C-70'C
0'C-70'C
0'C-70'C
0'C-70'C
0'C-70'C
5V ± 5%
5V
0:
5%
5V
0:
5%
5V
5V
5V
Vee Vpp
~
Vee Vpp
~
Vee Vpp
Vpp
~
0:
~
10%
0:
10%
~
Vee Vpp
Vee Vpp
10%
0:
~
Vee
READ OPERATION
D.C. CHARACTERISTICS
Limits
Symbol
Parameter
Min.
Typ.'
Max·
Test
Conditions
Units
/LA
V,N
10
p.A
VOUT
5
rnA
Vpp~55V
15
40
rnA
CE
60
CE ~ OE ~ V"
III
Input Load Current
10
ILo
Output Leakage Current
~
55V
~
55V
I pp,2
Vpp Current Read/Standby
Icell!
Vee Current Standby
Icc/
Vee Current Active
100
rnA
V"
Input Low Voltage
- 1
+.8
V
V,H
Input High Voltage
20
Vee +1
V
VOL
Output Low Voltage
45
V
10L ~ 21 rnA
VOH
Output High Voltage
V
10H ~ -400 fJA
2.4
~
V,H
A.C. CHARACTERISTICS
27128·25 &
27128 Limits
Symbol
Parameter
Min.
Max.
27128-30 &
27128-45 &
27128-3 Limits 27128-4 Limits
Min.
Max.
Min.
Max.
Units
Test
Conditions
t Aee
Address to Output Delay
250
300
450
ns
CE~OE~V
teE
CE to Output Delay
250
300
450
ns
OE~V
tOE
OE to Output Delay
100
120
150
ns
CE~VIL
130
ns
CE~V
ns
CE~OE~V
tOF
4
tOH
OE High to Output Float
0
Output Hold from Addresses.
CE or OE Whichever Occurred
First
0
60
0
0
105
0
0
IL
IL
IL
IL
NOTES:
1 Vee must be applied simultaneously or before Vpp and removed Simultaneously or after Vpp
2. Vpp may be connected directly to Vee except during programming The supply current would then be the sum of lee and IpP1
3 Typical values are for tA ~ 25'C .and nominal supply voltages
4 ThiS parameter IS only sampled and IS not 100% tested Output Float IS defined as the pOint where data IS no longer driven-see
timing diagram on page 4-31
4-30
27128
CAPACITANCE (TA
=
25'C, f
Parameter
=
1 MHz)
Typ.'
Max.
Unit
Conditions
C1N 2
Input Capacitance
4
6
pF
V,N=OV
COUT
Output Capacitance
8
12
pF
Vour=OV
Symbol
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
3.3KH
DEVICE
UNDER
TEST
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A lOGIC 1 AND a 45V FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 20V FOR A LOGIC 1
AND 0 BV FOR A LOGIC 0
1---+----0 OUT
I
c,"
100 pI
C L = 100pF
C L INCLUOES JIG CAPACITANCE
A.C. WAVEFORMS
V,H - - - - - - - ,
ADDRESS
VALID
ADDRESSES
VIL _ _ _ _ _ _ _J
V,H
---------+-'"
V,H
---------+-----'"\
I.----.c.,----,..
t------tAcd3J' - - - - - - - t
OUTPUT _______~H~IG~H~Z~_ _ _ _ _ _~~r1~~
HIGHZ
NOTES:
1. TYPical values are forTA = 25'C and nominal supply voltages.
2. This parameter is only sampled and IS not 100% tested.
3. OE may be delayed Up to tACC-tOE after the falling edge of CE without impact on tACC'
4. tOF is specified from OE or CE, whichever occurs first.
4·31
AFN·02077A
inter
27128
STANDARD PROGRAMMING
D.C. PROGitAMMING CHARACTERISTICS: TA
= 2S ± SoC, Vcc = SV ± S%, Vpp = 21V ± O.SV (see Note 1)
Umlts
Symbol
Min.
Parameter
ILl
Input Current (All Inputs)
VOL
Output Low Voltage During Verify
VOH
Output High Voltage During Verify
VIL
Input Low Level (All Inputs)
Max.
Unit
10
/loA
0.45
V
IoL = 2.1 mA
V
IoH = -400/ioA
2.4
-0.1
0.8
2.0
VCC + 1
V
40
mA
Te.. Conditions
VIN = VIL orVIH
V
VIH
Input High Level
ICC1
VCC Supply Current (Program Inhibit)
ICC2
VCC Supply Current (Program & Verify)
100
mA
IpP2
Vpp Supply Current (Program)
30
mA
CE =VIL = PGM
IpP3
Vpp Supply Current (Verify)
5
mA
CE = VIL PGM = VIH
IpP4
Vpp Supply Current (Program Inhibit)
5
mA
CE =VIH
VIO
Ag Inteligent Identifier Voltage
12.5
V
A.C. PROGRAMMING 'CHARACTERISTICS: TA
11.5
CE =VIH
= 2S ± SoC, Vcc = SV ± S%, Vpp = 21V ± O.SV (see Note 1)
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
I..
Address Setup Time
2
/los
toE.
OE Setup Time'
2
/loS
10 •
Data Setup Time
2
/loS
t..H
Address Hold Time
0
/los
IOH
Data Hold Time
2
t OFP 2
Oulput Enable to Output Float Delay
0
Iv.
V•• Setup Time
2
t.w
PGM Pulse Width During Programming
icEs
CE Setup Time
toE
Data Valid from OE
45
Test Conditions-
/loS
130
ns
/los
50
55
2
ms
/loS
150
ns
·A.C. CONDITIONS OF TEST
Input Rise and Fall Times (10% to 90%) .......... 20 ns
Input Pulse Levels ............. '......... 0.45V to 2.4V
Input Timing Reference Level , .... , ..... 0.8V and 2.0V
Output Timin'g Reference Level .......... 0.8Vand 2.0V
NOTES:
1. Vee must be applied simultaneously Dr before Vpp and removed Simultaneously or after Vpp.
2. This parameter is only sampled and is not 100% tested. Output Float IS defined as the point where data is no longer
driven-see timing diagram on page 4-33
4-32
inter
27128
STANDARD PROGRAMMING WAVEFORMS
i - - - - - - - P A O G R A M - - - - - - i - - - - - VERIFY ~.,.----~
ADDRESSES
DATA
Vpp
Ce
V"
PGM
V"
10'
10151
MAX
0.
V"
NOTES:
1 ALL TIMES SHOWN IN [ J ARE MINIMUM AND IN ~SEC UNLESS OTHERWISE SPECIFIED
2 THE INPUT TIMING REFERENCE LEVEL IS 8V FOR A VIL AND 2V FOR AVIH
3 'OE AND 'DFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER
4 WHEN PROGRAMMING THE 27128. A 0 I~F CAPACITOR IS REQUIRED ACROSS Vpp AND GROUND TO SUPRESS SPURIOUS VOLTAGE TRANSIENTS WHICH CAN
DAMAGE THE DEVICE
ERASURE CHARACTERISTICS
The'erasure characteristics of the 27128 are such
that erasure begins to occur upon exposure to light
with wavelengths shorter than approximately 4000
Angstroms (A). It should be noted that sunlight and
certain types of fluorescent lamps have wavelengths
in the 3000-4000 A range. Data show that constant
exposure to room level fluorescent lighting could
erase the typical 27128 in approximately 3 years,·
while it would take approximately 1 week to cause
erasure when exposed to direct sunlight. If the 27128
is to be exposed to these types of lighting conditions
for extended periods of time, opaque labels should
be placed over the 27128 wihdow to prevent unintentional erasure.
The recommended erasure procedure for the 27128
is exposure to shortwave ultraviolet light which has a
wavelength of 2537 Angstroms (A). The integrated
dose (Le., UV intensity x exposure time) for erasure
should be a minimum of 15 Wsec/cm2 • The erasure
time with this dosage is approximately 15 to 20
minutes using an ultraviolet lamp with a 12000
p.W/cm2 power rating. The 27128 should be placed
within 1 inch of the lamp tubes during erasure. The
maximum integrated dose a 27128 can be exposed
to without damage is 7258 Wsec/cm 2 (1 week @
12000 p.W/cm2j. Exposure of the 27128 to high i~ten
sity UV light for long periods may cause permanent
damage.
DEVICE OPERATION
The eight modes of operation of the 27128 are
listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TIL levels
except for Vpp and 12Von A9 for inteligent Identifier mode.
Table 1. Mode Selection
~
(20) (22)
(27)
(24)
Read·
VIL VIL
VIH
X
Vcc Vcc
Output Disable
VIL VIH
VIH
X
Vcc Vcc HighZ
Mode
CE OE
PGM Ag
vpp vcc Outputs
(11-13,
(1) (28) 15-19)
DOUl
Standby
VIH
X
X
Vec Vce HighZ
Program
VIL VIH, VIL
X
Vpp VCC
DIN
,Verify
VIL VIL
X
Vpp VCC
DOUl
Program InhIbit
VIH
X
X
X
intellgent Identifier
VIL VIL
VIH
VH
Vec Vce
Code
in!ellgent
Programming
VIL VIH
VIL
X
Vpp Vec
OjN
X
VIH
Vpp Vce HlghZ
NOTES:
1 X can be V,H or VIL
2 VH =12 OV ",O,5V
4-33 .
AFN·02077A
27128
transient current peaks is dependent on the output
capacitive loading of the device. The associated
transient voltage peaks can be suppressed by complying with Intel's Two-Line Control, as detailed in
Intel's Application Note, AP-72, and by properly selected decoupling capacitors. It is recommended
that a 0.1 /LF ceramic capacitor be used on every
device between Vcc and GND. This should be a high
frequency capacitor of low inherent inductance and
should be placed as close to the device as possible.
In addition, a 4.7 /LF bulk electrolytic capacitor
should be used between Vcc and GND for every
eight devices. The bulk capacitor should be located
near where the power supply is connected to the
array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effects of PC board traces.
READ MODE
The 27128 has two control functions, both of which
must be logically active'in order to obtain data at the
outputs. Chip Enable (CE) is the power control and
should be used for device selection. Output Enable
(OE) is the output control and should be used to gate
data from the output pins, independent of device
·selection. Assuming that addresses are stable,
the address access time (tACe) is equal to the
delay from CE to output (tCE). Data is available at
the outputs after a delay of tOE from the falling
edge of OE, assuming that CE has been low and
addresses have been stable for at least tACC - tOE.
STANDBY MODE
The 27128 has standby mode which reduces the
maximum active current from 100 mA to 40 mA.·
The 27128 is placed in the standby mode by applying a TTL-high signal to theCE input. When in
standby mode, the outputs are in a high impedance state, independent of the OE input.
PROGRAMMING MODES
Caution: Exceeding 22Von pin 1 (Vpp) will permanently damage the 27128.
Initially, and after each erasure, all bits of the 27128
are in the "1" state. Data is introduced by selectively
programming "Os" into the desired bit locations. Although only "Os" will be programmed, both "1s" and
"Os" can be present in the data word. The only way to
change a "0" to a "1" is by ultraviolet light erasure.
Output OR·Tieing
Because EPROMs are usually used in larger memory
arrays, Intel has provided 2 control lines which accommodate this multiple memory connection. The
two control lines allow for:
The 27128 is in the programming mode when Vpp
input is at 21 Vand CE and PGM are both at TTL low.
The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the
address and data inputs are TTL.
a) the lowest possible memory power dissipation,
and
b) complete assurance that output bus contention
will not occur.
To use these two control lines most efficiently, CE
(pin 20) should be decoded and used as the primary
device selecting function, while OE (pin 22) should
be made a common connect!on to all devices in the
array and connected to the READ line from the system control bus. This assures that all deselected
memory devices are in their low power standby mode
and that the output pins are active only when data is
desired from a particular memory device.
Standard Programming
System ConSiderations
For programming, CE should be kept TTL-low at all
times while Vpp is kept at 21V. When the address and
data are stable, a 50 msec, active-low, TTL program
pulse is applied to the PGM input. A program pulse
must be applied at eacH address location to be programmed. You can program any location at any time
-either individually, sequentially, or at random. The
program' pulse has a maximum width of 55 msec.
The power switching characteristics of HMOS-E
EPROMs require careful decoupling of the devices.
The supply current, Icc, has three segments that are
of interest to the system designer-the standby current level, the active current level, and the transient
current peaks that are produced by the falling and
rising edges of Chip Enable. The magnitude of these
Programming of multiple 27128s in parallel with the
same data can be easily accomplished due to the
simplicity of the programming requirements. Like
inputs of the paralleled 27128s may be connected
together when they are programmed with the same
data. A low-level TTL pulse applied to the PGM input
programs the paralleled 27128s.
4-34
AFN-020nA
27128
Figure 3. 27128 inteligent Programming™ Flowchart
programmed. The verify is performed with CE and
OE at VIL, PGM at VIH and Vpp at 21V.
Program Inhibit
Programming of multiple 27128s in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE or PGM input
inhibits the other 27128s from being programmed.
Except for CE, all like inputs (including OE) of the
parallel 27128s may be common. A TTL low-level
pulse applied to the CE and PGM inputs with Vpp
at 21V will program the selected 27128.
inteligent Programming™Algorithm
The 27128 inteligent Programming Algorithm allows
Intel 27128s to be programmed in a significantly
faster time than the standard 50 msec per byte programming routine. Typical programming times for
27128s are on the order of two minutes, which is a
six-fold reduction in programming time from the
standard method. This fast algorithm, results in the
same reliability characteristics as the standard 50
msec algorithm. A flowchart of the 27128 inteligent
Verify
A verify should be performed on the programmed
bits to determine that they have been correctly
4-35
AFN·02077A
intel·
27128
Programming Algorithm is shown in Figure 3. This is
compatible with the 2764 inteligent Programming
Algorithm.
tion counter and is equal to the number of the initial
one millisecond pulses applied to a pa·rticular 27128
location, before a correct verify occurs. Up to 15
one·millisecond pulses per byte are provided for
before the overprogram pulse is applied.
With the standard programming method, data is programmed into a selected 27128 location by a single
50 msec, active-low, TTL pulse applied to the PGM
pin. The inteligent Programming Algorithm utilizes
two different pulse types: initial and overprogram.
The duration of the initial PGM pulse(s) is one millisecond, which will then be followed by a longer
overprogram pulse of length 4X msec. X is an itera-
The entire sequence of program pulses and byte
verifications is performed at Vee = 6.0Vand Vpp =
21.0V. When the inteligent Programming cycle has
been completed, all bytes should be compared to the
original data with Vcc = Vpp = S.Ov.
inteligent Programming ™Algorithm
D.C. PROGRAMMING CHARACTERISTICS: TA
= 25
= 6.0V
± 5°C, Vee
± 0.2SV, Vpp
Limits
Symbol
Parameter
Min.
Max.
Unit
III
Input Current (All Inputs)
10
liA
VIL
Input Low Level (All Inputs)
-0.1
0.8
V
VIH
Input High Level
2.0
Vee+ 1
V
VOL
Output Low Voltage During Verify
0.45
VOH
Output High Voltage During Verify
ICC2
Vee Supply Current (Program & Verify)
IpP2
VIO
Vpp Supply Current (Program)
2.4
Ag inteligent Identifier Voltage
A.C. PROGRAMMING CHARACTERISTICS: TA
11.5
= 25
± 5°C, Vcc
Test Conditions
(see Note 1)
= VIL or VIH
V
IOL
V
IOH
= 2.1 mA
= - 4OO Ii A
CE
= VIL = PGM
mA
30
mA
12.5
V
± 0.2SV, Vpp
Limits
Symbol
Parameter
Min.
Typ.
Max.
Unit
tAS
Address Setup Time
2
liS
tOES
OE Setup Time
2
lis
tos
Data Setup Time
2
liS
0
liS
tAH
' Address Hold Time
tOH
Data Hold Time
2
tOFP4
Output Enable to Output Float Delay
0
tvps
Vpp Setup Time
2
tvcs
Vee Setup Time
tpw
PGM Inilial Program Pulse Width
0.95
topw
PGM Overprogram Pulse Width
3.8
tCES
CE Setup Time
tOE
Data Valid from OE
± O.SV
VIN
100
= 6.0V
= 21V
= 21V
± O.SV
Test· Conditions'
(see Note 1)
liS
130
ns
liS
2
liS
1.0
1.05
ms
(see Note 3)
63
ms
(see Note 2)
2
liS
150
ns
NOTES:
1 Vcc must be applied simultaneously or before Vpp and
removed simultaneously or after Vpp.
2 The length of the overprogram pulse will vary from 3.8 msec
to 63 msec as a functIOn of the Iteration counter value X.
3 Initial Program Pulse width tolerance is 1 msec ± 5%
4 ThiS parameter IS only sampled as IS not 100% tested
Output Float IS defined as the point where data IS no longer
drrven-see timing diagram on page 4·37
• A.C. CONDITIONS OF TEST
Input RiSe and Fall Times (10% to 90%) ......... 20 ns
Input Pulse Levels
......... O.4SV to 2.4V
Input Timing Reference Level ...... . ... a.8V and 2.aV
Output Timing Reference Level .......... a.BV and 2.aV
4·36
AFN-02077A
intJ
27128
inteligent Programmlng™ WAVEFORMS
RAM
ADDRESSES
~
VERIFY
X-
ADDRESS STABLE
~
-:;~-
DATA
1\
DATA IN STABLE
HIghZ
DATA OUT vlLlD
--.
":~i·
-\~~-
_IAH
[0)
"
J
tOFP
"1-'013
MAX.'
Vpp
Vpp
,--.-I -~&f:--
Vee
Vee + 1
.
:--.-1 -'r:l')S-
Vee
Vee
1\
l--'f2E)S-
\~I
--
-
'PW
[.15mo)
[3~P':')
r-
t-'OES-j
(2)
"\
r-
tOE
-I::!~-
NOTES:
1 ALL TIMES SHOWN IN [ ) ARE MINIMUM AND IN ~SEC UNLESS OTHERWISE SPECIFIED
2 THE INPUT TIMING REFERENCE LEVEL IS 8V FOR AV'L AND 2V FOR AV'H
3 tOE AND IDFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER
4 WHEN PROGRAMMING THE 27128. A 0 1"F CAPACITOR IS REQUIRED ACROSS Vpp AND GROUND TO SUPRESS SPURIOUS VOLTAGE TRANSIENTS WHICH CAN
DAMAGE THE DEVICE
4·37
AFN·02QnA
Byte 0 (AO = Vld represents the manufacturer code
and byte 1 (AO = VIH) the device identifier code. For
the Intel 27128, these two identifier bytes are given in
Table 2. All identifiers for manufacturer and device
codes_ will possess odd parity, with the MSB (07)
defined as the parity bit.
inteligent Identifier™ Mode
The inteligent Identifier Mode allows the reading out
of a binary code from an EPROM that will identify its
manufacturer and type. This mode is intended for
use by programming equipment for the purpose of
automatically matching the device to be programmed with its corresponding programming algorithm.
This mode is functional in the 25°C ± 5°C ambient
temperature range.
Intel will begin manufacturing 27128s during 1982
thEit will contain the inteligent Identifier feature. Earlier generation devices will not contain identifier information, and if erased, will respond with a "one"
(VOH) on each data line when operated in this mode.
Programmed, pre-identifier mode 27128s will
respond with the current data contained in locations
and 1 when subjected to the inteligent Identifier
operation.
To activate this mode, the programming equipment
mustforce 11.5V to 12.5Von address line A9 (pin 24)
of the 27128. Two identifier bytes may then be sequenced from the device outputs by toggling address lineAO (pin 10) from VIL to VIH. All other
address lines must be held at VIL during inteligent
Identifier Mode.
o
Table 2. 27128 inteligent Identifier Bytes
Identifier
~s
Ao
(10)
Manufacturer Code
Device Code
07
(19)
Os
(18)
Os
(17)
04
03
02
01
00
(16)
(15)
(13)
(12)
(11)
Hex
Data
VIL
1
0
0
0
1
0
0
1
89
VIH
1
0
0
0
0
0
1
1
83
4-38
27256
256K (32K x 8) UV ERASABLE PROM
• Software Carrier Capability
• 250 ns Maximum Access Time
• Two-Line Control
• Inteligent Identifier™ Mode
Standard Pinout ... JEDEC
• Industry
Approved
Low Power
• -100
mA max. Active
•
- 40 mA max. Standby
Inteligent Programming™ Algorithm
The Intel 27256 is a 5Vonly, 262,144-b'it ultraviolet Erasabie and Electrically Programmable Read Only Memory
(EPROM). Organized as 32K words by 8 bits, individual bytes are accessed in under 250ns. This is compatible
with high performance microprocessors, such as the Intel 8MHz iAPX 1'86, allowing full speed operation
without the addition of performance-degrading WAIT states.
The 27256 enables implementation of new, advanced systems with firmware intensive architectures. The
combination of the 27256's high density, cost effective EPROM storage, and new advanced microprocessors
having megabit addressing capability provides designers with opportunities to engineer user-friendly, high
reliability, high-performance systems.
The 27256's large storage capability of 32K bytes enables it to function as a high density software carrier. Entire
operating systems, diagnostics, high-level language programs and specialized application software can reside
in a 2725.6 EPROM directly on a system's memory bus. This would permit immediate microprocessor access and
execution of software and eliminate the need for time .consuming disk accesses and downloads.
DATA OUTPUTS
-0 0 -0,
Vcc~
GND~
V-GATING
Ao_A14!
ADDRESS
INPUTS
\
262,144 BIT
CELL MATRIX
CE OE
Ao
(20) (22) (24)
Vpp Vee
(1)
Vpp
Vpp
A12
A,
A12
A,
A,
A,
Vee
A12
A14
A,
A5
A"
As
A.
A,
An
A3
A,
OE
A10
A,
A.
An
OE
A,o
A3
A,
A,
A3
A,
A,
A,
CE
OE
OE
Ao
Ao
00
Ao
0,
0,
0,
0,
Gnd
OE
A,o
0,
0,
0,
05
0,
05
0,
0,
05
0,
GND
03
03
03
00
0,
0,
NOTE INTEL "UNIVERSAL SITE" COMPATIBLE EPROM PIN CONFIGURATIONS
ARE SHOWN IN THE BLOCKS ADJACENT TO THE 27256 PINS
(28) (11-13,15-19)
VIL
X
Vee Vee
DOUT
VIL V,H
X
Vee Vee
HlghZ
Standby
V,H
X
Vee Vee
HlghZ
Intellgent Programming
V,L V,H
X
Vpp Vee
D,N
Verify
V,H V,L
X
Vpp Vee
DOUT
Program Inhibit
V,H V,H
X
Vpp Vee
HlghZ
OE
Intellgent Identifier
V,L
Code
00- 0 7
OUTPUTS
PGM
PROGRAM
N.C.
NO CONNECT
VH Vee Vee
Figure 2. Pin Configurations
PIN NAMES
AO-A'4 ADDRESSES
CHIP ENABLE
CE
NOTES
1 X can be VIH or VIL
~
A.
An
A"
As
".
VIL
2 VH
As
Vee
PGM
A5
Output Disable
V,L
Vee
PGM
N.C.
A5
Read
X
~
Vpp
".
0,
Gnd
OUTPUTS
.
. f:i
27256
;!;
00
0,
Figure 1. Block Diagram
~
...f:i ....
OUTPUT ENABLE
12 OV" 05V
Intel Corporation Assumes No Responslbllty tor the Use of Any Circuitry Other Than CirCUitry Embodied," an Intel Product No Other Circuit Patent Llce'ns8s a'e Implied
© INTEL CORPORATION. 1982
4.39
ORDER
NUM~~~~~:~~7:~
UV ERASABLE PROM FAMILY
EXPRESS
• 0-70°C Temperature Range
Standard
• 168±8 Hour Burn-in Available
• Industry Standard Pinout ... JEDEC
Approved
• Extended Temperature Range
-40°C - +85°C Available
• Inspected To 0.1% AQL
• Two Line Control
The Intel EXPRESS EPROM family is a series of ultraviolet erasable and electrically programmable read only
memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match system
applications. Intel's JEOEC approved 28 pin Universal Memory Socket provides the industry standard upgrade
path to higher density EPROMs.
.
EXPRESS EPROM products are available with 168±8 hour, 125°C dynamic burn-in using Intel's standard bias
configuration (equivalent to MIL-STO-8838). This process exceeds or meets most industry specifications of
burn-in.
The standard EXPRESS EPROM operating temperature range is O°C to 70°C. Extended operating temperature
range (-40°C to 85°C) EXPRESS products are available. EXPRESS products plus military grade EPROMs
(-55°C to 125°C) provide the most complete choice of standard and extended temperature range EPROMs
available.
Like all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1 % electrical AQL. This may allow the user
to reduce or eliminate incoming inspection testing.
'
2764
2716
A7
A'2
Vee
Vee'
Ae
As
As
Ag
Vee
VPP
Vee
PGM
A'2
A7
A'3
N.C.
As
"-
GND
27128
2732A
PGM
As
As
Ae
As
Ae
An
"-
An
A3
OE
A3
A2
A,
Ag
liE
A,o
A10
A,o
CE
As
A,
CE
D7
Cii
D7
As
D7
As
0,;
0,;
06
0,;
05
00
0,
O.
02
O.
Oa
GND
03
05
0,
05
00
0,
O.
0,
o.
0,
Oa
GND
Oa
A10
Cii
D7
05
PIN CONFIGURATION
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than CirCUitry Embodied
© INTEL CORPORATION '982
4-40
In
an Intel Product No Other CircUIt Patent Licenses are Implied
FEBRUARY '982
ORDER NUMBER, 210322-001
intJ
EXPRESS
EPROM Product Family
Operating
Temperature
eC)
Burn-in
125°C
(hr)
5V ± 5%
5V ± 5%
o to 70
o to 70
o to 70
16B±B
16B±B
450
5V ± 5%
-40 to 85
16B±B
2048x8
450
5V ± 5%
-40 to 85
NONE
002732A-2
002732A
002732A-3
002732A-4
4096x8
4096x8
4096x8
4096x8
200
250
300
450
5V
5V
5V
5V
16B±B
16B±B
16B±B
16B±B
002732"-20
002732A-25
002732A-30
4096x8
4096x8
4096x8
200
250
300
5V ± 10%
5V ± 10%
5V ± 10%
o to 70
o to 70
o to 70
o,to 70
o to 70
o to 70
o to 70
16B±B
16B±B
16B±B
L02732A
L02732A-4
4096x8
4096x8
250
450
5V ± 5%
5V ± 5%
-40 to 85
-40 to 85
16B±B
16B±B
L02732A-25
L02732A-45
4096x8
4096x8
250
450
5V ± 10%
5V ± 10%
-40 to 85
-40 to 85
16B±B
16B±B
T02732A
TD2732A-4
4096x8
4096x8
250
450
5V ± 5%
5V ± 5%
-40 to 85
-40 to 85
NONE
NONE
T02732A-25'
TD2732A-45
4096x8
4096x8
250
450
5V ± 10%
5V ± 10%
-40 to 85
-40 to 85
NONE
NONE
002764-2
002764
002764-3
002764-4
8192x8
8192x8
8192x8
8192x8
200
250
300
450
5V
5V
5V
5V
16B±B
16B±B
16B±B
168±B
002764-25
002764-30
002764-45
8192x8
8192x8
8192x8
250
300
450
5V ± 10%
5V ± 10%
5V ± 10%
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
o to 70
L02764
L02764-4
8192x8
8192x8
250
450
5V ± 5%
5V ± 5%
:"'40 to 85
-40 to 85
16B±B
16B±B
L02764-25
L02764-45
8192x8
8192x8
250
450
5V ± 10%
5V ± 10%
-40 to 85
-40 to 85
16B±B
16B±B
TD2764
T02764-4
8192x8
8192x8
250
450
5V ± 5%
5V ± 5%
-40 to 85
-40 to 85
NONE
NONE
TD2764-25
TD2764-45
8192x8
B192x8
250
450
5V ± 10%
5V ± 10%
-'40 to 85
-40 to 85
NONE
NONE
0027128
0027128-3
16384xB
16384x8
250
300
5Y ± 5%
5V ± 5%
o to 70
o to 70
168±B
16B±B
Organization
Maximum
Access
(ns)
Power
Supply
002716-1
2048x8
350
5V:t- 10%
002716-2
002716
2048xB
2048xB
390
450
L02716
2048x8
TD2716
Type
4-41
±
±
±
±
5%
5%
5%
5%
± 5%
± 5%
± 5%
± 5%
168±B
16B±B
16B±B
16B±B
AFN-02139A
intJ
EXPRESS
EPROM Product Family
(Cont.)
Organization
Maximum
Access
(ns)
Power
Supply
0027128-4
16384x8
450
5V ± 5%
16384x8
16384x8
250
450
5V -± 10%
5V ± 10%
o to 70
o to 70
o to 70
168±8
0027128·25
0027128-45
L027128
L027128-4
L027128-45
16384x8
16384x8
16384x8
250
450
450
5V ± 5%
5V ± 5%
5V ± 10%
- 40 to 85
- 40 to 85
- 40 to 85
168±8
168±8
168±8
T027128
T027128-4
T027128-45
16384x8
16384x8
16384x8
250
450
450
5V ± 5%
5V ± 5%
5V ± 10%
- 40 to 85
-40 to 85
- 40 to 85
NONE
NONE
NONE
Type
Operating
Temperature
Burn·in
(OC)
(hr)
0,
V"
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
168±8
168±8
V"
Vee
Vee
0,
125°C
0,
ot=+5V R=lK!l vcc=+sv
Vpp=+5V Vss=GND CE=GND
0E=+5V R=lKn Vcc=+5V
Vss=GND CE=GND
Vee
Vee
0,
0,
0,
0,
0,
0,
0,
0,
Vee
"
0,
0,
0,
0,
0E=+5V
0E=+5V R=lKn Vcc=+5V
Vpp=+5V Vss=GND CE=GND
Vpp=+5V
1'lm=+5V
A""lKO VcC=+5V
VsS=GNO
CE=GND
1'lm=+5V
30,""
Ao~·
r
A, ..J
AN
BINARY SEQUENCE FROM
Ao
to AN
Figure 1. Burn-In Bias and Timing Diagrams
4-42
AFN·02139A
READ OPERATION
D.C. AND A.C. CHARACTERISTICS
Electrical Parameters of EXPRESS EPROM products are identical to standard data sheet parameters except
for:
Limits
Symbol
Parameter
TD2716
LD2716
Min.
TOE
Output Enable to
Output Delay (n5)
toF
Output Enable to
Output Float (n5)
Iccl
Icc2
VCC Standby Current (rnA)
0
Max.
TD2732A
LD2732A
Min.
Max.
TD2764
LD2764
Min.
Max.
TD27128
LD27128
Min.
Test Conditions
Max.
150
CE
= VIL
130
CE
= VIL
CE
= VIH • OE = VIL
= CE = VIL
45
150
VCC Active Current (rnA)
4·43
50
125
50
125
OE
E2 PROMs (Electrically Erasable
Programmable Read Only Memories)
5
..----intel-I!)_ _ _ __
1982-1983
, DESIGNER'S
GUIDE TO
E2PROM
.. PRODUCTS
Dan Pichulo
PPROM Product Line
Manager
Larry Palley
NVMD Marketing
December. 1982
Order Number 210700--002
5·1
INTRODUCTION
In the emerging market for Electrically Erasable PROMS (PPROMS),
there have been many product announcements with a variety of features. Each of these products is not entirely compatible with the others.
This myriad of PPROM choices has created confusion in the industry
about which E2PROM characteristics, features and pinouts are necessary or desirable. The lack of'a defined direction in E2PROM technology,
one which users can rely upon for planning, has created many questions about E2PROM functionality, availability and reliability
This document was prepared to provide general guidelines to the engineers, system designers, managers, and component evaluators about
the directions in PPROM product features and pinouts. It presents a
clear view of the expanding E2PROM technology base, including present products, and a design path to newer devices cbnsistent with
total system memory requirements. Topics discussed are E2PROM
technology, future product trends including features, pinouts, characteristics, standards, cost trends, and applications.
~
______________________
5-2
in~_®
_
(E2PROM) TECHNOLOGY
+VG
SECQNo.LEVEL
POLYSIUCON
pSUBSTRATE
FIGURE 1A. EPROM CELL
In 1971, a revolutionary transistor cell, the EPROM, was created
which provided non-volatile data storage. The cell could be pro- '
grammed like a PROM with high voltage pulses but it could be erased
with ultraviolet light. Data could be read from the EPROM at speeds
that were compatible with microprocessor operations. With its unique
transistor structure, the EPROM opened a new set of microprocessor
applications using dedicated EPROM program storage. The main
advantages were significantly faster code changes and reprogrammability over masked ROMs and fusible link PROMs.
The EPROM transistor cell (Figure 1A) takes advantage of the excellent insulating properties of silicon dioxide to store charge on a gate
isolated within silicon dioxide even when power is not applied. Charge
stored on this '110ating" gate changes the transistor characteristics.
When selected to read data, a transistor with an uncharged floating
gate will conduct current from drain to source. The charged state is
then distinguished from the uncharged state by the fact that, when
selected, the transistor will not conduct current. A logical "0" or "1"
condition is thus represented.
The benefit of the floating gate transistor structure results trom the
ability of the charge to be transported onto or removed from the floating
gate at the user's discretion. In the case of an EPROM, charge is programmed onto the gate with a PROM programmer al1d removed by
exposing the array to ultraviolet light. To program an EPROM, the
device is placed in a programmer that electrically adds charge to
selected gates for programming
FIGURE 1B. E2 PROM CELL
The 1;:2pROM was developed as a further advancement in EPROM
technology. Its storage cell (Figure 1B) takes advantage of the same
EPROM transistor structure to achieve electrical erasabllity. The difference in the cell is the addition of tunnel oxide region above the drain
of the floating gate transistor This thin oxide region allows charge to
move bidirectionally under the influence of an electric field (Figure 1B)
either onto or off of the floating gate By applying a high voltage to the
transistor's !Select gate (VG) and a corresponding low voltage (ground)
to the transistor drain (Vol, charge is induced to pass through the tunnel oxide onto the floating gate. Using the same principle, but reversing
the voltages, charge can be electrically removed from the floating gate.
E2PROM technology offers enormous benefits Since the charge
transport mechanism has very low current requirements, programming
________________________________________ i~-@--5-3
the PPROM cell requires a very modest power source. It is then possible to create, with the low current required, the necessary high voltage programming pulses from the normal system power supplies.
Programming, erasure, and reprogramming can all be accomplished
In-circuit (i.e. in the end application system without a PROM programmer unit or circuit).
One of the major improvements that E'PROMs offer is the ability to
electrically erase and reprogram individual bytes within an array. This
is in contrast to ultraviolet light erasure associated with EPROMs,
which can only erase the entire memory array. Erasure in E'PROMs is
also rapidly accomplished; both byte programming and erasure occur
in 10ms respectively. A total E'PROM chip can also be erased with
one 1Oms electrical pulse in-circuit versus the 3D-minute requirement
of EPROMs in the external environment of ultraviolet light.
Since E'PROM technology evolved from the EPROM, much of the
experience gained from EPROMs also applies to E'PROMs. The same
cost reduction and reliability methodologies of EPROMs can be carried
over and used with E'PROM. The reliability of E'PROMs can also be
verified using the techniques similar to those developed with EPROMs.
With EPROM technology as its base, and the addition of a single select
transistor and the tunnel oxide innovation, E'PROMs have been
developed as versatile non-volatile memories The technology has
advanced to the stage where 16K bit E'PROM devices are in cost
effective volume production. Large E'PROM arrays, including 64K bit
densities, are already in design. As designers become more familiar
with the devices, E'PROMs will continue to add versatility and performance to microcomputer systems.
E2PROM FEATURES: First &
Second Generation Devices
The original 2816 E'PROM, with byte erase capability, became
available in production quantities in early 1981. The 2816 represented the first step in achieving commercial E'PROM reliability. The
viability of the floating gate structure has been tested and proven with
these devices.
To make E'PROM technology readily available to customers and
coincidentally to demonstrate product reliability, the 2816 was designed
as conservatively and usable as possible. It incorporates the important
------------------intel-®~
5-4
basic requirements for an E'PROM-1 Oms write/erase times, single
byte erasability, 10,000 erase/ write cycles per byte, and 250ns read
access speeds.
For many applications, howeyer, additional support components need
to be added. First, an external programming voltage is required. This
usually entails implementation of an on board 5V-to-21 V voltage circuit
such as a DC/ DC converter, or a stepped-down 24 to 21-volt regulator. While relatively simple to implement and low cost, the circuit
requires additional design time and board space.
,
A second part of the supporting design involves the write sequencing
circuitry. The 2816 requires 1Oms to erase or write date, a period much
longer than the typical microprocessor write cycle. The additional
peripheral functions include a counter to time-out the 1Oms write
pulse, latches to hold the data and addresses during the write cycle,
and analog circuitry to correctly shape the programming pulse.
These additional E'PROM interface requirements are now embodied
in a second E'PROM device, the 2817 (Figure 2). To write a byte of
data into the' E'PROM array, a simple microprocessor write cycle is initiated (Figure 3). When the write cycle begins (taking only 100 ns), the
2817 device itself takes over the process of programming the E'PROM
r-----------------~,
Vee
I
I
I
I
I
I
I
I
I
I
I
I
I
l
WE
RDYIBsY=t
I
=====~rf~~
iI
ADDRESS.-i"-------~~~~~
2816
DATA_~-------~~
L _________________
I
I
I
I
I
I
I
E~
FIGURE 2.
2817 INTEGRATES INTERFACE ON CHIP
__________________~________ i~-®__
5-5
arrqy. The 2817 starts by lowering its READY/BUSY output and electrically disconnects itself from the microprocessor system. Since the
2817 contains all the necessary information in on-chip latches, no additional microprocessor support is required. In fact, the microprocessor
is free to perform other system functions during the remainder of the
write cycle.
The byte location to be written js automatically erased, and then programmed. No microprocessor intervention is required as with some
E2PROMs. At the end of the programming cycle, the 2817 uses the
READY/BUSY signal to inform the processor through an interrupt or
polling structure that the byte is written and non-volatilely stored. At
this point, the 2817 re~establishes the electrical continuity of its input
and output lines to be ready for subsequent accesses.
An important feature of the 2817 is the built-in ready/busy line to
identify its status to the associated CPU. This line indicates internal
programming activity by a logical low. After completion of the intemal
programming cycle, the line returns to a logic high. The E' device is
then accessible for reading/or writing by the microprocessor. By tying
the ready/busy signal to a system interrupt as in Figure 3, the CPU requires only one instruction cycle to make E2PROM writing possible. In
effect, the processor can write to the 2817 like a RAM, perform other
system functions and then retum to write the next byte after receiving a
ready interrupt. In this arrangement no polling or time-out counting is required by the processing system. In systems without interrupt capability it is possible to use a single I/O port to poll the ready line.
WITHOUT REAOYI8USY
r--_ _---:;WITHREAOY1SUSV,--_ _- .
2817
EPROM
WITH
INTERNAL
RJr~~i~sy
• READY /iiOSY PROVIDES A POSITIVE FEEDBACK SIGNAL TO THE
MICROPROCESSOR
• ELIMINATES NEED FOR AN EXTERNAL HARDWARE TIMER OR TIME
CONSUMING SOFTWARE TIMING/POLLING LOOPS
FIGURE 3.
__
THE ADVANTAGE OF A READYIBUSY SIGNAL
_________________________________________
5-6
i~-®--~
With alterable memories, data retention is another factor to be considered. Some MNOS technologies suffer from "read disturb" of the
memory cell with increasing usage. Ths means that a device of this
type will become erased if it is read enough times without being reprogrammed. Also, the greater the number of programming cycles applied
to an MNOS device, the sooner a device will lose its programmed data
in this manner. By contrast, the Intel Flotox Process exhibits no read
disturb characteristics. Within the total endurance specification, the
level of usage is independent of the retention capability. The full data
retention specification applies to the Flotox device throughout its
endurance life. From a practical viewpoint, the Ready (Busy signal on
a 2817 also serves as a data retention indicator. During each write
cycle, this signal goes low. The transition to the high state which confirms that programming is complete, also indicates that optimum
retention is assured for the current data.
These advances.in memory device technology make the 2817
E'PROM very simple to use. Not only is the hardware reduced, but
the hardware design task is easier, the software is minimal, and system
speed and efficiency are improved.
5-VOLT ONLY VERSIONS
To make E2PROMs even morl'l convenient for in-system use, product
improvements are planned involving the addition of 5V to 21 V conversion circuitry. Three pieces of on-chip circuitry are needed to advance
the product to the 5V-only stage-a 5V to 21 V pump, a 21 V regulation
circuit, and power sequencing circuitry(Figure 2).
While it is a relatively simple task to build a 5-volt to 21-volt pump circuit
into an E2PROM often overlooked is the importance of the 21 V regulation
circuitry. Because of the tolerances of the E2PROM cell, the internal
21 V programming voltages must be regulated over a large temperature
range. Approaches have been developed to make this circuitry
achievable and cost effective.
Another often overlooked requirement of E2PROM designs is the need
to protect the device from spurious systerh writes to guarantee data
integrity. Since an E'PROM device is most effective when programmed
and erased in-circuit, its inpu1s could be susceptible to random write
pulses during system power transitions. This is especially true when
the part is placed in a system with only 5V operation.
______________________________________~i~-®--5-7
To avoid spurious writes, a 5V-only E'PROM should be designed with
protection circuitry. A 5V-only E'PROM should not respond to system
signalS when the system power supply is below a pre-defined active
level. By designing special lockout circuitry into 5V E'PROM, spurious
writes can be ignored during power transitions.
All three aspects of the 5V-only circuitry discussed here are
planned to upgrade current products and for future E'PROMs.
STANDARDS FOR SYSTEM
IMPLEMENTATION
I
DEOCATED
~"""
I
LATCHES~~TA
S-VOlT
TMSl HAADWAAE OR
SOFT ...... AE
"""
OI1OPSINl)NIVl"RSAl
~"
IlHVEASAL
"''''''
I
AlJTOEAASEBEFORE-WRITE
ON"
ME~VSITE
REAOY/BUSY
FEEDBACK LINE
FIGURE 4.
DUAL LINE FUNCTIONALlTY-16 K
A major hardware design consideration with 2816 E'PROMs has been
the requirement for additional interface circuitry. This requirement has
been significantly minimized with the 2817 and will be essentially eliminated with the 2817 A 5V-only device. With added on-chip programming
capability, the devices have become more intelligent making them
easier to interface and use. In the interim, designers have utilized 2816
and 2815 devices.
Five-Volt only E' devices should develop along dual product lines to provide greater choice to designers to match system specifications and
product goals. To service dedicated designs, a device with minimum
on-chip support (e.g. 2816A) might be selected. In such a design, the
costs of off-chip latches and the write-timing function can often prove
cost effective by allocating their expense over a group of E' devices.
For more universal designs, where ease of interface or enhanced
functionality are important, an enhanced device (e.g. 2817 A) can be
used. The chart in Figure 4 summarizes the main conSiderations for
each type of system design.
Aiding the design engineer has been the consistency of pinouts
across byte-wide memory product lines. E'PROM products have been
designed to fit in the Jedec 28-pin universal memory site. The design
philosophy of the universal 28-pin memory site emphasizes b'oth the
capability to interchange many memory types and to provide groups
of densities within each memory family. Refer to Figure 5.
Extraordinary design flexibility can be implemented with this memory site
concept particularly in the E'PROM family. Future intelligent E'PROM
devices like the current 2817 will be designed to be directly insertable
into a 28-pin site without hardware modifications. Designers can mix
and match E'PROMs with PROMs, ROMs, and RAMs. Also, the density
selections of 28-pin E' devices can be totally upward and downward
compatible. As system requirements change, users can utilize higher
or lower density E'PROM-or other memory components-at various
__________~____________________________ i~-®--~
5-8
densities in the same sockets. Hardware redesign cycles can be minimized or eliminated to implement new features, enhancements, or
changes to systems.
System designers also have the option to provide a universal memory board to be used across a company's product lines. Varying
memory requirements can be met with this single board. Additionally,
manufacturers can benefit from the cost reduction of future density
upgrades as new memory technologies expand. As can be seen in the
28-pin site diagram, E'PROMs sucn as the 2817 A fit directly into
the socket with no extemal hardware requirements. In the E' family,
28-pin E'PROM devices from 4K to 128K are compatible with the
universal site.
ROM
EPROM
e2PROM
NVRAM
.RAM
tRAM
16Klo
16KIO
4Klo
4Kto
8Kto
64K to
256K
256K
12SK
1281(
256K
128K
[e..,
Ne
v~
RDYNpp
NE
.,.
RDY/RFH
I
'14
pGMlA14
WE
WE
PlN27
WE
FIGURE: 5.
UNIVERSAL 28-PIN SITE
WE
The 28-pin site also accommodates 24-pin devices such as the 2816
and 2815 (and their 5V-only versions). This is a result of the consistent
locations of the data, address, and control pins.
In today's designs, E'PROMs form a complementary mix-and-match
non-volatile memory set with EPROMs. Where density and low cost per
bit are prime system considerations, EPROMs will be the principal
memory. When the ability to change the firmware content easily, quickly,
economically or to suit the job-at-hand are important, E'PROMs offer
a significant advantage. EPROMs generally fill the medium and upper
density requirements while E'PROMs fit the lower density needs. For
example, main program code, system kernels and popular application
programs which have been extensively field tested tend to reside in
EPROMs. Embedded firmware in distributed processing architecture
and local area networks which lend themselves to user reconfiguration
and code modifications are prime candidates for E'PROMs. As a point
of perspective, both memories will continue to grow in density per
device but the current EPROM-to-E' density ratio favors the economy
of EPROMs for unchanging code. Over time, the absolute price differences will become smaller and E'PROMs should accerlerate their
penetration into firmware memories.
GENERAL APPLICATIONS
E'PROMs provide capabilities to improve system functionality, producibility, and serviceability in applications spanning many industries.
They provide the designer and manufacturer with the ability to provide
a more flexible, adaptable, reliable, and user friendly system
for customers.
E'PROMs can improve the capabilities of many types of systems in
diverse applications. Typical applications for E'PROMs include:
• Programmable controllers and data loggers require user entered
and alterable programs. These programs contain polling sequences, configured parameters, alarm and set point, and alterable
data tables.
- - - - - - - - - - - - - - i n t e l - ®--5-9
• Robots require remote storage that configures arm axes of movement. Compensation algorithms, calibration constants, as well as
protocols need to be stored and reconfigured over time.
• In data acquisition and communications systems, one must be able
to easily adapt systems to particular customer needs. Protocol
reconfiguration can take place without hardware modifications.
• Smart terminals today often have "soft" keys that require non-volatile
storage for their reuse. Character fonts, screen formats, color setup, baud rates, highlighting attributes and frequently used key-steps
could be stored.
• Firmware, traditionally committed to ROMs, PROMs and EPROMs,
can be readily updated when stored in PPROMs. Both main program code and particularly embedded firmware in distributed
processing systems lend themselves to this application. All of the
conventional write techniques can be employed as with RAMs:
Keyboards, down-load from disk, and telecom links.
• In PABXs, stored program control could be implemented so that
feature updates, polling algorithms, access routings and other program modifications are readily reconfigurable in non-volatile
memory to match each installation and changing conditions.
E2PROMs IN SYSTEM
MAINTENANCE
An area where FPROMs are of great value is the reduction of system
service costs. Since programs can be loaded in FPROMs while they
are in a system, program updates can be achieved without dismantling
hardware or incurring the associated service costs. Programs can be
updated remotely (for example, in the manufacturer's software design
group) and then downloaded to an end user's system via a telephone,
through an I/O port or from a mass storage device via disk or tape
with no travel and service cost incurred. The code would then remain
in FPROMs non-volatilely.
These program changes would save manufacturers the burden of
carrying spare PROM inventories, programming new PROMs, and
sending or replacing them in their installed customer base systems.
Firmware updates resulting from code enhancements, code fixes and
system upgrades would be carried out Simply and efficiently with little
_________________________________________ i~-®--~
5-10
incurred service costs. Additionally, an entire customer base of systems can be quickly updated so that all machines reflect the same
code revision levels. Service technicians would no longer be baffled
when servicing old problems; and record keeping could be greatly
simplified by actually storing revision and service data in a few bytes
of an E'PROM.
E2PROMs IN SYSTEM
MANUFACTURE
FPROMs improve the throughput times required to test systems.
Products with FPROMs are able to Pl3rform extensive self tests on
the assembly line, be reloaded with new test programs, and be configured for individual end users. All of these functions would take place
in one set of built-in E'PROMs. An example test floor set-up is shown
in Figure 6.
. ,
A machine could progress through a series of tl3sts which are individually downloaded into the FPROM memory. Each test program could
be executed independently by the machine with the final test results
verified at the next test station. Since the tests are all internally run, test
equipment would be greatly simplified. Finally, the product could be
customer configured and shipped with its program in E'PROM after a
final download.
FUTURE E2PROM PRODUCTS
Intel currently manufactures two versions of 16K E'PROM in 24-pin
packages and one, the enhanced 2817, in a 28-pin package. The
2816 was the original E'PROM device and has been described. The
2815, a lower cost version of the 2816, IS identical to the 2816 in
operation and characteristics to the 2816 but needs 50ms rather that
10ms programming pulses.
Soon to be released products are 5V-only-versions oi both the 2816/15
and 2817 parts. These products will incorporate all of the associated
5V-only circuitry necessary for reliable operation as described earlier.
These 5V-only devices will be fully compatible with existing non-5V-only
parts for ease of upgrade. The first part to be produced will be the
2816A-a 5V-only version of the standard 2816 which includes the 5V
converter, regulator, and power transition circuitry.
~
_______________________________________ i~_®__~
5-11
t
SH1P
FIGURE 6.
SELF-TESTS WITH E'PROMs IN
PRODUCTION OF COMPUTER EQUIPMENT
The 2816A is designed to be fully compatible with the 2816 interfaces
and support circuitry. It can be placed directly in a 2816 socket with no
hardware changes. The 2816A can, therefore, be programmed at
5V-only levels or at the previous 21 V levels. The 2816A is also provided for customers who must rely on immediate second sources. In a
24-pin package, several announced competitive products would be
compatible.
Intel currently provides a second generation PPROM product in volume
production, the 2817. This part reduces, by over 70%, the peripheral
circuitry which the hardware designer needs with 2816 design. The
2817 is especially cost effective in designs which require small arrays
of E2PROMs containing from one to about eight devices. In larger system arrays, the 2816/2815 tends to be more cost effective, since the
________________-------------------------i~-®--5-12
cost of external system circuits can be prorated over many somewhat
lower cost devices.
In development is the 2817 A, a 5V-only version of the simple to Interface 2817. All of the learning curve aspects of 5V-only E'PROM
technology will be incorporated on this product.
28PIN
+21----,------[]
I
/
"
RDY---'--'---'
REMOVE Te, +21V INSTALL JUMPER
FIGURE 7.
2817 TO 2817 A UPGRADE DESIGN
Additionally, two improvements to the 2817 are planned. These include:
1. An open drain output stage on the ROY IBSY iine so that
several 2817 A ROY IBSY lines can be OR tied together to a single interrupt or port.
2. Relocation of the ROYIBSY line to pin 1 from pin 2 so that
compatibility is assured for 64K E'PROMs with address line 12
on pin 2 consistent with the universal site.
Figure 7 contains a diagram that illustrates how 2817 designs can
easily anticipate 2817 A upgrades.
Intel plans to continue its technology leadership with E2PROM devices
in higher densities. These parts will be produced in the same format
and with the intelligent functions of the 2817 A. By designing FPROMs
in 28-pin board sites now with the 2817 and 2817 A, designers and
users will have the capability to insert future E'PROMs into the
same sockets.
Intel plans to use its E'PROM technological advantage to address
lower density applications requiring 4K bits (512 by1es). These devices
will be competitive with existing CMOS RAM + Battery, EAROM, and
low density EPROM applications. The lower density E'PROMs will be
designed in a 28-pin universal package so that upward compatibility to
2817 A is maintained. By designing today with 2817s, low density
E'PROMs will be compatible as they become available.
The E'PROM market of the future is characterized by products with
easy to deSign interfaces, 5-volt-only operation, and reliable arrays
of many densities. These features will have their primary appeals with
design architects and hardware engineers. Users, however, will have
a somewhat different orientation centered around functionality. Packaging standards which allow a free intermix of memory technologies
will be important to increase design longevity and minimize new design
efforts and turn around times. The user community will focus on data
integrity and retention, minimal system software support and increased
density at cost effective prices. First generation devices will give way
to FPROMs with on-chip support and intelligence. A summary of the
~
_______________________________________ i~_®~~
5-13
on-chip inteliligence of the 2817 appears in Figure 8. Devices such as
the 2817, which represent the culmination of many years of design
experience, will strongly influence the standardization of E2PRelMs for
functionality and pin-out.
EASE-OF-INTERFACE
EASE-OF-USE
• AObRESS LATCHES
• AUTO ERASE-BEFORE-WRITE
• DATA LATCHES
• MINIMUM WRITE TIME EACH BYTE
• WRITE SHAPING CIRCUITRY
• BYTE ADDRESSABLE
• 28-PIN UNIVERSAL SITE
• READY/BUSY FEEDBACK
• FREES PROCESSOR FOR OTHER
FUNCTIONS AFTER INITIATING
EACH WRITE
FIGURE 8.
Ii--JTELLIGENT ON-CHIP FEATURES
2817E2 PROM
E2PROMs RELIABILITY
/
The original Intel E2PROM has been in production for over 2 years.
During that time its reliability has been validated in user applications
and through thousands of hours of test and evaluation. Over 10,000
devices have been analyzed through cyclic erase/write, life and
retention bake tests to ensure performance and functionality.
The 2817 has exhibited even better reliability than the older 2816 in
similar evaluations. This improvement occurs because the 2817's
"intelligent" Internal programming algOrithm limits the programming
level and the consequent stress on the cell after programming.
E2PROMs are conservatively tested for erase/write cycle endurance.
All E2PROMs are shipped to meet a specification requiring at least
10,000 cycles per byte. Over 99% of the bytes, however, have been
found to still function reliably after 100,000 cycles The 10,000 number is the equivalent of changing every byte in the E2PROM array
about 3 times per day for 10 years.
_______________________________________________
5-14
i~-@---~
CONCLUSIONS
This Guide has traced the emergence of PPROM technology and
the development of first and second generation devices It is an evolutionary Intel technology based on the design, development and manufacture of UV-erasable EPROMs with their long and successful history.
As a point of comparison, over 70 man-years of reliability engineering
have been accumulated in the fundamental EPROM technology. Similarly, over lOman-years of reliability and quality assurance have been
devoted to E2PROMs exclusive of design, technical development and
product engineering.
From the many factors that have been considered, reliability, ease-ofinterface and on-chip intelligence have surfaced as the major considerations. The 2817A, 5V-only, intelligent PPROM clearly establishes
the optimum industry standard. It offers Jedec packaging compatibility,
all the necessary Integrated functionality, and total upward and downward density mobility from 4K to 128K-bit capability.
Intel offers a clear design path for users of E2PROMs The 2816 and
2817 can be designed and used in today's systems, and replaced with
the upgrades to 2816A and 2817A PPROMs in the future. Higher
and lower density growth paths are also provided through the 28
pin package.
Intel has the commitment to extend current technological limits and
pave the way for designers to use more advanced E2PROMs In the
future. These devices will Incorporate higher densities, extension of
critical parameters and even greater flexibility.
'-______~___________________________________ i~-@--~
5-15
APPLICATION
NOTE
AP-100
December 1982
Based on presentation at 1981 International Reliabi)ity Physics Symposium, Orlando, Florida, April 7, 1981.
@lntelCorporatlon, 1982
5·16
AP-100
INTRODUCTION
Electrically Erasable Programmable Read Only
Memories (E 2 PROMs) that can be electrically erased
and written one byte at a time are new components
being used in computer systems. The E 2 PROM is particularly attractive in applications requiring field update
of program store memory or non-volatile data capture.
It is only recently that E 2 PROMs which operate via
Fowler-Nordheim tunneling to a floating poly silicon
gate have become available. The E 2 PROM has the data
retention requirements of earlier generations of
PROMs, but also must maintain its field-programmable
characteristics over its device life.
10.2
10-3
10.4
ItO.
10-6
10·7
10·9~----'::-----:----:---:::1O---:'';-'-~
In this paper we shall first review the basic operation of
the Intel 2816 E 2 PROM cell. Intrinsic failure mechanisms which limit the applications of E 2 PROMs will be
examined, and then defect mechanisms will be discussed. Finally lifetest data will be presented to predict
operating failure rates.
Device Operation
The Intel 2816 uses the FLOTOX structure, which has
been discussed in detail in previous literature 1 . Basically, it utilizes an oxide of less than 200A thick between the floating polysilicon gate and the N + region as
shown in Figure 1.
5
Figure 2. Fowl.er-Nordheim Tunneling I-V
Characteristic
During the erase operation, approximately 20V is
applied to the top gate of each cell in the byte while the
drain is kept at ground potential. The electrical field in
the thin oxide region is directed from the floating gate to
the N + region such that electrons tunnel through the
oxide and are stored on the floating gate. This shifts the
cell threshold in the positive direction causing the cell to
shut off current flow and present a logical "1" at its
output (as seen in Figure 3a).
On the other hand, when the cell is written to logic "0" ,
the top gate is pulled down to ground potential and a
high voltage is applied to the drain (with the source end
floating). Electrons are depleted from the floating gate
FIELD
OXIDE
COLUMN 2
ov
SINGLE
CELL,
SELECT
UNE
+21Y
(
SELECT
TRANSISTOR
ELECTRONS CHARGE
ALL ,GATES O)'INE
ERASE!
WRITE
Figure 1. FLOTOX Device Structure Cross Section
LINE
+21V
Both erase and write are accomplished by tunneling the
electrons through thin oxide using the FowlerNordheim mechanism 2 . The I-V characteristic of
Fowler-Nordheim tunneling is shown in Figure 2,
where the current is approximately exponentially dependent on the electric field applied to the oxide.
Figure 3a. Schematic of Memory Cell OPeration
During Erase
5·17
AFN-OI883A
Ap·100
as seen in Figure 3b, and the cell is left with a negative
threshold. Since the interpoly oxide is much thicker
than the' 'tunnel oxide" and the electric field across the
interpoly oxide is much smaller, the erase and write
operations are predominantly controlled by the thill
oxide region.
1~_ _ _
Ec
- - - - - - - EF
Ey
DRAIN
Ec-----'I
EF - - - - - -
Ey
EF • FERMI LEVEL
l>.Y • YOLTAGE DIFFERENCE BETWEEN TOP GATE AND DRAIN
IN WORST CASE READ CONDITION
Figure 4. Band Diagram During Read of
Written Cell
ERASE!
WRITE
UNE
OY
Read Retention
The floating gate structure is known for its excellent
charge retention properties. The reliability of this
structure in the case of the EPROM device has been
reported before3 • The only remaining concern of the
data retentivity of the 2816 is possible charge gain or
loss through the tunnel oxide due to Fowler-Nordheim
tunneling. The maximum electric field is built up across
the tunnel oxide for a written cell, one that has a net
positive charge on the floating gate. In this state the
positive top gate voltage creates an electric field which
adds to the field created by the positive charge on the
floating gate, and there exists the probability that electrons may tunnel to the floating gate and shift the cell
threshold. The band diagram of this condition is shown
in Figure 4. However, the amount of current which may
pass through the thin oxide during read or deselect is
kept low by biasing the top gate of the memory cell at an
internally generated voltage less than Vee. The effect
on the threshold shift of the cell can only be observed
after long-term stress. Under this condition, the accelerated voltage test can be very useful.
THIN
OXIDE
INTERPOLY
OXIDE
SELECT
UNE
+21V
Figure 3b. Schematic of Memory Cell Operation
During Write
.
TOP GATE
SINGLE
CELL,
there is a one-to-one relationship between the VT and
the stress voltage. In other words, we can stress the
device by applying a higher voltage to the top gate such
that the change of the threshold voltage can be measured. The data then will be used to predict the same
characteristics at the much lower normal read voltage.
In Figure 5, the aforementioned simulation and experimental data are shown. The cell was biased at a voltage
4V higher than the normal read condition and the
threshold voltage of the cell was monitored over a
period of a week. A simulation was also generated to
compare with the observed threshold s~ift and to demonstrate the technique we use to predict whethi:lr the
data retention ofthe' cell is accurate. As can be seen in
the Figure 4, even under the accelerated voltage test the
cell VT still will not cross above the sense level after
more than 10 years. Similar data has also been taken by
writing the cell to a more negative initial threshold. In
this case, the shift of the threshold can be observed at a
stress of normal read voltage. Clearly, a IV/IV relationship holds and an extrapolation can be made that
the correct data will be retained for more than 10 years
of continuous read.
.~ r-------------------~~--------_,
e
-------------------SENSELEVEL
SIMULATION
------
~~;::::;~~:::.
ACCELERATED
--
YOLTAGEIV_
-
If we assume Fowler-Nordheim tunneling is the
predominant mechanism governing the movement of
electrons, the threshold shift of the cell will be dependent solely on the voltage between the top gate and the
N+ region. This has been proven to be true in both
simulations and experiments, where we found that
-r-j
ExmAPOLATED
+ 4yl
-
-------
~
-
trr
tell,
llME(SEC)
~
~
__ _
10".
~
1110,,.
~
~
Figure 5. Single Cell Threshold Voltage Shift vs.
Log Time During Read of a Written Cell
5-18
AFN.()l883A
AP-100
Intrinsic Charge Trapping
charges will cause an increase in electric field at the
injection interface, i.e., Si02/Si interface, as shown in
Figure 7b. This will in turn increase the tunneling current to the floating gate, where the amount of stored
electrons is thus increased, causing the erase threshold
to increase. During the erase cycle, however, the polarity of bias voltage across the tunnel oxide will cause the
positive charge at Si02 /Si interface to be neutralized
,through the reverse tunneling mechanism that fonns
these charges. At the same time a new layer of positive
charges is fonned near the anode! 1, !2, i.e., poly/Si02
interface, as shown in Figure 7c. These charges will
then cause the write threshold to increase through the
Isame mechanism as that discussed for the erase
threshold. In addition to positive charge trapping, our
study also shows that there is a uniform distribution of
electron traps throughout the oxide!!' 12. When the cell
is erased or written, electrons are injected through the
oxide and some of them will be captured by these traps,
An ideal feature of a tunneling dielectric is that it should
never remember the number of electrons that passed
through it or the voltage that was previously applied
across the film. Unfortunately, for thermally grown
Si02 there always exists a certain number of electron
and hole traps4-9. When these traps are occupied the
net charging state of the tunnel oxide will be changed
and thus cause the tunneling current across the film to
vary if the applied voltage has remained the same.
Figure 6 plots the threshold voltage of a 2816 cell in
erase (charged) and write (discharged) states as a function of erase/write cycles. The solid line is for a single
cell, while the dashed line is for a typical 2816 array. It is
seen that the threshold window, defined as the difference between the erase and, write threshold, is
slightly increased in the first few E/W cycles and then
saturates and remains almost constant until 104 cycles.
From that point, the window begins to narrow
gradually until around 106 cycles where the window is
collapsed.
Poly
DRAIN
+
+
+
+
f12
~
..
... -- ....
---.... --
.... --
..
-
--~
--<>
A) POSITIVE CHARGE INDUCED AT THE S,02-S, INTERfACE AT THE END
Of THE WRITE OPERATION
L,
~D1SCHARGED STATE
-6
+
+
10
ERASE I WRITE CYCLES
+
Figure 6. Typical Cell and Device Window vs.
Log Cycles
Our study shows that the behavior of the widening and
narrowing of the threshold window can be explained by
charge trapping in tunnel oxide. The window widening
effect is found to be caused by the following
mechanism:
B) BAND DIAGRAM Of SUBSEQUENT ERASE SHOWING LOWERING Of THE
TUNNELING BARRIER BY THE TRAPPED POSITIVE CHARGE
Sl~
Poly
Assume a cell is to be erased following a write cycle.
During the preceding write cycle, the floating gate is
biased negatively relative to the substrate. A layer of
positive charge will be formed, either through the tunneling of holes from Si into Si0 2 or electrons in the
reverse directioq. These positive charges are in general
at 20-30A away from the Si0 2/Si interface, as in Figure'
7a. At the beginning of the erase step, the positive
5-19
+VFG
~
DRAIN
+
+
+
+
-I
C) POSITIVE CHARGE NEAR POL YSILICON-Si02INTERFACE AT THE END
OF THE ERASE OPERATION
'
Figure 7. Threshold Window Widening
AFN·Ol883A
AP-100
causing the build-up of negative charges in the oxide, as
shown in Figure 8. The negative charges will reduce the
electric field at the injection interface, thus decreasing
the tunneling current and causing the threshold window
to narrow. It has been found that the electron traps are
not only preexisting in the oxide but also generated
during the E/W cycles~-12 because of the high field
stress and the accompanying high current flow. The
non-saturated build-up of negative charges, because of
the continuous generation of electrons traps will finally
cause the threshold window to collapse.
Erase/write cycling effects on data retention were studied by comparing 250"C retention before cycling to that
after 10,000 cycles. Figure 9 shows a plot of the cumulative % data retention failure during 500 hours 250"C
retention bake. Data from the Intel 2716 EPROM is
included as a comparison. From this data it is clear that
the retention failure rate closely resembles that of the
Intel 2716 EPROM.
Since the defect charge loss failure mechanism is temperature activated it is simple to construct screens on a
production basis for these types of failures similar to
those used on EPROMs.
BEGINNING OF ERASE
Poly
ing to occur at voltage differences between the floating
gate and the drain that would ordinarily be insufficient
to support tunneling.
DRAIN
VFG
0..::-
-
-
-
'-
-
-
-
+
+
+
+
-
H
-
Figure 8. Negative Charges Trapped Uniformly
Across Tunnel Oxide
• 2816 E2 PROM
, 2816 AFTER 10.000 CY
... 2716 EPROM
Defect Charge Loss
166
I
10y'S
EPROMs have been shown to have excellent data retention3 . In this section we will discuss data retention
studies that have been performed on the Intel 2816
E 2PROM. Since in E 2 PROMs the number of Erase/
Write cycles during the device lifetime is 3 to 4 orders of
magnitude greater than in the EPROM, we will also
need to address the effects of cycling on data retention.
200
I
20yrs
400
SIOY's
SOO HRS(250' C)
TJ=70°C
Figure 9. Intel 2816 Data Retention at 2SO"C,
Percent Fail vs. Time
Accelerated Test Results
As in the case of EPROMs the charge loss from the
floating gate can be described as either intrinsic or
defect-related. We will discuss the defect-related
charge loss since the intrinsic charge loss on a typical
device is identical to the EPROM and has been described before3 .
An E 2PROM has an additional reliability requirement
over standard PROMs. Besides the integrity of data
retention, an E 2 PROM must withstand up to 10,000
erase and write programming pulses per byte. Besides
the previously discussed window closing phenomenon
there are reliability considerations due to high voltage
operation. Dielectric breakdown l3 is a common MOS
failure mechanism, which has been shown to be highly
voltage accelerated. The reliability of the Intel 2816
during erase/write cycles was measured by performing
the full number of erase/write cycles on each byte.
Erase/write cycling was done at 70°C and 25°C with no
difference in observed failure rate between these
temperatures.
Analysis of cells exhibiting defect -related charge loss
shows that the leakage current has an exponential dependence on the potential of the floating gate. This is
different from the EPROM where defect leakage current exhibits a linear (ohmic) dependence on voltage. 3
The exponential dependence is indicative of electron
tunneling. The effect of the defect, then, is the lowering
or narrowing of the thin oxide barrier, allowing tunnel-
5-20
AFN-01883A
AP-100
The results of erase/write cycling are shown in Figure
lOA. The devices under test are completely tested after
2,000, 5,000 and 10,000 total cycles on each byte. The
devices are programmed to several data patterns and
tested to data sheet specifications. In addition, the
deviCes are tested for high temperature data retention.
As can be seen from Figure lOA, the failure rate per
1000 cycles decreases as a function of the number of
cycles, which is typical for defect mechanisms such as
dielectric breakdown. 13 From the time the initial data
was gathered in 1981, recent data (Figure lOA) has
shown the failure rate to have been reduced by a factor
of 2.
~
4.0
~G
.. § 3.0
i1i~
Ii IIC
S~
! if
.,.
2.0
.7%
1.0 ..- _ _ . .
.5%
2K
.2%
5K
10K
E/WCYCLES
A) INSTANTANEOUS PERCENT FAIL VS NUMBER OF EIW CYCLES
Two major types of failures were found: Tunnel oxide
breakdown and oxide breakdown in the row select circuitry. These failures were minimized by using standard
screening techniques for oxide breakdown. Figure lOB
shows the failure mode distribution found during
erase/write cycling of 549 devices.
, - - - - - - 2 5 % OTHER
Tunneling oxide breakdown failures are cells which fail
either to program or to retain data following programming due to conduction through the thin oxide at low
electric fields. In the case of the programming failures,
the breakdown extends all the way through the oxide
layer. The data retention failures exhibit charru.:teristics
similar to those of the defect charge loss failures discussed in the previous section and are probably due to a
partially broken down oxide layer. Further cycling of
this type of retention failure has been found to result in
it becoming a programining failure.
B) FAILURE MECHANISM DISTRIBUTION
Figure 10. EraseJWrite Cycling Results
Table I shows expected failure rates in %/1000 hours at
a 60% upper confidence level based on expected device
life and the average number of cycles per byte. In a
typical system it is expected that ~ome bytes will be
written more often than others, so these failure rates
serve as a guideline.
Table I. Erase/Write Cycling Failure Rate
(per 1000 hours at a 60% UCL)
No. of Cycles
Devite
Life
5 years
10 years
20 years
As can be seen in Table It. acceptable fallure rates are
achieved for the design goal of 10,000 erase/write cycles
per byte. To achieve 10,000 cycles per byte in ten (10)
years, each byte must be altered approximately three
times per day.
2000
.035
.017
.009
5000
.06
.029
.017
10,000
.092
.047
.023
Table II. 125°C Lifetest Results
Cycles 48 Hrs 168 Hrs 500 tirs 1000 Hrs 2000 Hr.
0
0/1422 1/1422a 1/443°
0/429
0/270
10,000 0/336
0/336
0/336
0/150
Total 0/1758 1/1758
1/779
0/579
0/270
As a final verification of device reliability a standard
high temperature lifetest at 125°C was performed on
devices programmed with a checkerboard data pattern.
The lifetest was performed on devices with no additional cycles and devices with 10,000 cycles on each
Failure Analysis:
a) ~ Non-repeatable charge gain, contamination, lev.
b) ~ Input leakage, contamination, lev.
;:'
5-21
AFN-Ol883A
AP-100
Failure rate predictions are mad~ in Table III at a 60%
upper confidence level for both 5SOC and 70°C operation. The .013%/1000 hrs. failure rate at 55°C shows
good reliability comparable to other semiconductor
memories.
byte. As can be seen from the data in Table II standard
MOS failure mechanisms were observed. This data is
significant in that it shows no additional defect mechanisms related to data retention or erase/write cycling of
the Intel 2816 E 2 PROM.
.
Table III. Failure Rate Predictions at a 6(1% U.C.L.
125°C
Device Hrs.
Activation
Energy
Equivalent Hours
Lifetest
Failures
Failure Rate
% per 1000 Hrs.
55°
70°
55°C
7rf
3.2x 106
0.3 eV
2.lx10 7
!.3x107
0
.004
.007
3.2x106
0.6 eV
1.3 x 108
5.3x10 7
0
.001
.002
!.OeV
!.6x 109
3.4x lOB
2
.000
.001
Combined
.005
.010
3.2x 106
SUMMARY
--
5 . M. H. Woods and R. Williams, J. Appl. Phys.,
p 47, 1082, 1976.
This p·aper has discussed a number of E 2 PROM failure
mechanisms for both erase/write cycling and data retention. It has been shown that Fowler-Nordheim tunneling used for programming does not affect data retention. Erase/write cycling has been shown to degrade
device margins by only a small amount and is easily
guardbanded. Erase/write cycling does contribute to a
significant portion of the observed failure rate due to
oxide breakdown under high field operation. Finally, it
has been shown that E 2 PROMs can perform reliably in
applications requiring up to 10,000 erase/write cycles
per byte.
6. W.C.Johnson,IEEETrans.Nuc/.Sci.;p. NS-22,
2144, 1975.
7. D. J. DiMaria, Proceeding of the International Topical Conference on the Physics of Si02 and its
Interfaces, p. 160, 3/78.
8. E. Harari, Appl. Phys. Letter, p. 30,601, 1977.
9. C. S. Jenq, "High Field Generation of Interface
States and Electron Traps in MOS Capacitors,"
Ph.D. dissertation, Princeton Univ., 12/77.
10. C. S. Jenq, W. C. Johnson, "High Field Generation
of Electron Traps in MOS Capacitors," presented
in Semiconductor Interface Specialist Conference,
12/77 .
REFERENCES
11. C. S. Jenq, T. R. Rangarath, C. H. Huang, "Charge
Trapping in Floating Gate Tunnel Oxide"
presented in 1980 Non-Volatile Semiconductor
Memory workshop to be published.
1. W. S. Johnson, et aI, "16-K EE-PROM Relies on
Tunneling for Byte-Eraseab1e Program Storage,"
Electronics, February 28, 1980, p. 113-117.
2. R. Williams, Phys. Rev., Vol. 140, p. 569, 1965.
12. D. R. Young, "Electron Trapping in SiO z",
presented in 1980 Non-Volatile Semiconductor
Memory workshop.
3. R. E. Shiner, J. M. Caywood, B. L. Euzent, "Data
Retention in EPROMs," 1980 Proceedings of the
18th Annual Reliability Physics Symposium,
p. 238-243.
13. D. Crook, "Method of Determining Reliability
Screen for Time Dependent Dielectric Breakdown," 1979 17th Annual Reliability Phy~ics Symposium Proceedings, p. 1-5.
4. E. H. Nicollian, C. N. Berglund, P. F. Schmidt, I.
M. Andrews,J. Appl. Phys., Vol. 42, p. 5654,1971.
5-22
AFN·01883A
APPLICATION
NOTE
AP-136
September 1981
© Intel Corporation, 1981.
5-23
AFN-02067A
AP·136
INTRODUCTION
J1-J8
Interrupt Line Selection
The Intel Special Products Division E2 MuItibus
Memory Board is an excellent example of how to implement the 2816 Electrically Erasable PROM in a multibus system. The board is completely MuItibus
compatible and can be plugged into any existing Intellec
Microcomputer Development System. It can also be
used in a Multil:)us-compatible system with any combination of Intel Single-Board Computer (iSBC)
Modules. The memory board has a capacity of up to
16K bytes of electrically erasable non-volatile memory
storage (8 2816s). The board can be read at microprocessor system speeds (250 ns). Writing to the E2 Board
requires only a single system write cycle. When the
write operation is complete, the E2 Board notifies the
CPU by lowering an Interrupt Line. Individual 2816s
can be erased in a similar manner with one write
operation.
J20
Data Bus Width
The E2 Memory Board can operate with either an 8 or a
16-bit-wide data bus. This is determined by one jumper
and by a 3628A Bipolar PROM used for decoding the
addresses to the MOS PROM Array. The 3628A gives
the board the capability of accommodating combinations of 2816s, 2815s, 2716s, 2732s, 2732As, and 2764s.
The JEDEC pin compatibility ofInteI's MOS EPROMs
allows these devices to be plugged into the same 28-pin
sockets. The 3628A, used as a decoder, allows these
different memory size MOS PROMs to be used in the
same array in various combinations. This enables the
user to mix the devices in the memory array to fit the
system's particular applications. The Multibus card can
be located anywhere within up to one Megabyte of
addressing space. The Vpp supply voltage is generated
on board, and the only voltages needed are the standard
Multibus +5V, + 12V, and -12V power supplies. Finally, the E2 memory system can be powered up and
down repeatedly without losing one byte of its 16K
bytes of data.
INSTALLATION INSTRUCTIONS
Below is a procedure to prepare the E2 memory card for
use. Following the list are detailed instructions for each
step.
Procedure
1. Install the correct shorting plugs on the following
jumper groups:
121-J24
PROM Socket Address Configuration
JWI-JW8
PROM/RAM Selection
2. Vpp Pulse Width Selection
3. Set switches SWI-SW5 according to the MOS
PROM density used.
4. Adjust the Vpp high voltage level.
5. Select the proper XACR delay based on the tACC of
the slowest MOS PROM used.
Board Address Location
The E2 board can be assigned to anyone of the 16
64K byte pages within a one-megabyte address space. If
only 64K of address space,is available, leave, the jumper
pairs J9-J12 open. Otherwise, install the shorting plugs
to select the desired page as shown in the following
chart:
Board Address Selection
X
=
install shorting plug
0= open
As shown in the assembly drawing in Appendix D, 2
pins reside at each jumper location. A shorting plug is
simply inserted at the jumper location for installation.
64K Page
Jl2
64K
64K- I28K
,128K- I92K
I92K- 256K
256K- 320K
320K- 384K
384K- 448K
448K- 5I2K
5I2K- 576K
576K- 640K
640K- 704K
, 704K- 768K
768K- 832K
832K- 896K
896K- 960K
960K-I024K
OK~
0
0
0
0
0
0
0
0
X
X
X
X
X
X
X
X
Jumper
JlO
JlI
J9
0
0
X
X
0
0
X
X
0
0
X
X
0
0
X
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
X
0
0
0
0
X
X
X
X
0
0
0
0
X
X
X
X
J9-J12
Board Address Location
RESET and Chip Erase Functions
J13-J19
RESET and Chip Erase I/O Addresses
The board requires two consecutive I/O addresses to
control the RESET and Chip Erase functions. Doing an
5-24
AFN-02067A
AP·136
I/O write cycle to one or the other address activates the
particular function. The even I/O address selects the
RESET function, an odd I/O address sets the Chip
Erase function.
Jumper
110 Address bit
RESET
Function Chip
Erase Mode
b = address bit
JI8
A6
b
b
J19
A7
b
b
Jumpers J13 through Jl9 determine which two
consecutive I/O addresses are to be used. The following
chart shows the jumper scheme for I/O addressing.
J17
A5
b
b
Jl6
A4
b
b
Jl5
A3
b
b
J14
A2
b
b
J13
Al
b
b
AO
0
I
Once two consecutive I/O addresses for these two
functions are determined, then install shorting plugs on
J13-J19 corresponding to the 1's in the upper 7 bits of
the two I/O addresses.
Structure section for an explanation of the E2 Board
internal data bus structure. Refer to the following
PROM Array Decoder subsection for directions on
setting switches SWI-SW5.
Examples:
PROM/RAM Selection
for OOH = RESET
01H = Chip Erase,
install no shorting plugs
If E2PROMs or EPROMs are used in the MOS PROM
Array, do the following:
r
for 8AH = RESET
8BH = Chip Erase,
put shorting plugs on J13, J15, and J19
Install shorting plugs on the following jumpers:
for 32H = RESET
33H = Chip Erase
put shorting plugs on J13, J16, J17
Leave these jumpers OPEN:
JW1, JW3, and JW8
JW2, JW4, JW5, JW6, and JW7
Vpp PULSE WIDTH SELECTION
Ensure that the correct RC timing components are
installed for the E2 PROM to be used:
Interrupt Line Selection
The E2 Memory Board generates an interrupt upon
completion of a Byte Erase/Write or a Chip Erase
operation. Anyone of the 8 Multibus Interrupt Lines
can be used. To select a given Interrupt Line, install the
shorting plug indicated below:
Interrupt Line
INTO
INT I
INT2
INT3
INT4
INT5
INT6
IN17
E2PROM
R3
C8
2816
2815
10KO
24KO
4.7 /LF
10 /LF
twp
10 ms
50ms
R3 and C8 are located at the top and center of the EZ
board on the left of I.C. HI.
Jumper
Jl
J2
MOS PROM Array Decoder
J3
J4
J5
J6
The Multibus Card can use either an 8-bit or a
16-bit-wide data bus. Jumper J20 should be installed for
16-bit data buses, and left open for 8-bit-wide buses.
(See Figure 1) The Bipolar PROM is used to select the
MOS PROM or MOS PROM pair being addressed. The
Bipolar PROM holds decoding algorithms for 2816s,
2815s, 2716s, 2732s, 2732As, and 2764s. The decoder
also selects one or two devices at a time depending on
whether an 8-bit or a 16-bit data bus is being used. The
Dipswitch at the top of the board determines which
decoding algorithm is to be used. Use Table 1 to choose
the proper switch setting for the MOS PROMs to be
loaded in the Array. The correct shorting plugs must
also be installed on Jumpers J21-J24-see Table 2.
In addition, switches SWI-SW5 must be set so that the
correct MOS PROM(s) are enabled for upper and/or
lower byte operations. Refer to the 16-Bit Data Bus
If it is desired to have devices of different densities in
the Array or if a decoding algorithm other than the one
provided is needed, the spare blocks in the 3628A can
J7
J8
Data Bus Width
5-25
AFN.02067A
AP·136
MOB PROM ARRAY
-
-
LOWER
BYTE
r---
~ CE
CE
Al1lVpp
~~
~~
23
23
~
~ CE
...!!. CE
~~
LAC-
#7
#5
#3
#1
23
23
.___LAC
Vpp~
e---Vpp
3828A
LAO
BHE
BAC
BAD
BAE
BAF
-
-
-
00
AO
Al
01
A2
02
A3
03
A4
04
AS
05
08
07
Cii
23
I
'20
'A1i~
'A1iN,;""
'20 CE
CE
23
A11IVpp
23
23
"'A11#.;"'
'20
CE
'20
CE
UPPER
BYTE
#4
#2
-
-
#6
#8
Figure 1. PROM Array Address Configuration
be programmed with new algorithms. The structure of
the algorithm is .determined by a simple principle. The
output corresponding to the CE of the MaS PROM to
be selected should be a logic 0 for the address range of
that PROM. The selecting addresses areAI2,A13,AI4,
A15 (called BAC-BAF on the schematic), and AO and
BHE. (See section on 16-Bit Data Bus Structure for
infqnnation on the use of AO and BHE.) The smallest
address range is 2K bytes. AddressesAl2-Al5 select a
pair of PROMs while AO/BHE select one or both of the
two PROMs in that pair. Figures 2 through 7 can be used
as examples. (Also see Appendix B.).
Jumpers J21-J24 simply connect address All orVpp to
pin 23 of the 28-pin MaS PROM socket. If a given Array
half (sockets 1-4, for example) is to be loaded with
2816s or 2716s, then Vpp must go to pin 23 (Jumpers 122
and J24). If 4K or 8K byte parts are used, then All must·
be connected to pin 23 (Jumpers J21 and J22).
A few rules must be followed in mixed-density Arrays.
(1) Each socket pair (1 and 2,3 and 4, etc.: see Figure 1)
must contain devices of the same density. (2) Each
Array half (sockets 1-4 and sockets 5-8) can contain
either 4K and 8K pairs, or 2K pairs, but not both.
The decoding algorithms must also take into account
the data bus width. See figures 2 through'Hor examples
of 8-bit data bus algorithms and figures 5 through 7 for
examples of 16-bit data bus algorithms. Note that the
proper shorting plugs must be installed, on Jumpers
J21-J24 according to the device densities used.
If desired, a 3636B can be used instead of a 3628A. The
2K X 8 3636B will allow the encoding of twice as many
decoding algorithms as the lK X 8 3628A.
The blank PROM Decoder charts inAppendix G may be
helpful in planning new decoding algorithms.
5·26
AFN-02067A
AP-136
SYSTEM
ADDRESS
DECODER CIRCUIT INPUTS
AO-15
HEX
BAF
BAE
BAD
BAC
BliEN
LAO
o
BYTe
L
OXXX
H
1 X X X
L
H
" LOW BYTE
HIGH BYTE
=
o "
1
ENABLE
= DISABLE
L
2 X X X
= NO SHORTING PLUG
= SHORTING PLUG INSTALLED
H
3XXX
L
H
4 X X X
L
H
S X X X
L
H
8 BIT DATA BUS
L
6 X X X
H
L
7 X X X
H
sxxx
L
H
9XXX
L
H
LEAVE JUMPER J20 OPEN. (NO SHORTING PLUG)
L
AXXX
H
L
B X X X
INSTALL SHORTING PLUGS
PER THE FOLLOWING TABLE.
H
L
exxx
H
DEVICE DENSITY = 2K BYTES
oxxx
L
E X X X
H
L
F X X X
X=HEX
DIGITS
JUMPERS
H
AS
A3
A4
A2
A1
PROMS1-4
AD
OUTPUTS
ADDRESS INPUTS
5-8
Iml-!B
2KI
0
x
3628A
4KJ8KI
x
I
0
~
X
I J~4 I
I
0
I
Figure 2. 2716 or 2816
Table 1. BIP Decoder Switch Settings
Device
2816/2815/2716
Address Range in Hex
(For Full Array)
OFF
ON
2732/2732A
2764
0OO0-3FFF
8000-BFFF
0OOO-7FFF
OOOO-FFFF
8-Bit
Data Bus
SWI
SW2
SW3
SW4
'SW5
ON
ON
ON
ON
ON
ON
OFF
OFF
ON
ON
OFF
OFF
ON
ON
ON
ON
OFF
ON
ON
ON
l6-Bit
Data Bus
SWI
SW2
SW3
SW4
'SW5
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
ON
ON
ON
ON
OFF
ON
ON
OFF
ON
OFF
ON
ON
= No shorting plug.
=
Install shorting plug.
* Must Be "ON" for 3628A.
5-27
AFN.Q2067A
AP-136
SYSTEM
ADDRESS
AO-15
HEX
DECODER CIRCUIT INPUTS
BAF
BAE
BAD
SAC
BHEN
o
LAO
BYTE
oX XX
L
H
1 X X X
L
H
2 X X X
L
H
3 X X X
L
H
4 X X X
L
H
5 X X X
=
=
=
L
H
=
o "
X
LOW BYTE
HIGH BYTE
ENABLE
DISABLE
NO SHORTING PLUG
"" SHORTING PLUG INSTALLED
L
H
Il-
6XXX
L
H
7XXX
L
H
8 X X X
L
H
8 BIT DATA BUS
LEAVE JUMPER J20 OPEN. (NO SHORTING PLUG)
L
H
A XX X
8XXX
L
H
ex xx
L
H
DXXX
L
H
EXXX
L
H
F X X X
L
H
X=HEX
DIGITS
INSTALL SHORTING PLUGS
PER THE FOLLOWING TABLE:
AS
A3
A4
A2
A1
DEVICE DENSITY = 4K BYTES
JUMPERS
1·4
AO
2K
OUTPUTS
ADDRESS INPUTS
3628A
5·8
Il-rulm
0
x
4K/SKI
x
I
0
~JJ~41
X
I
0
I
Figure 3. 2732 or 2732A
Table 2. MOS PROM Sockets
5-8
1-4
Device Density
J21
J22
J23
J24
2K
0
X
0
X
4Kor8K
X
0
X
0
o = No shorting plug.
X·= Install shorting plug.
5·28
AFN-02067A
AP·136
SYSTEM
ADDRESS
AO-15
HEX
DECODER CIRCUIT INPUTS
BAF
B~E
BAD
BAC
BHEN
CE'S
LAO
0
BYTE
X X
L
H
1 X X X
L
H
2 X X X
L
H
3 X X X
L
H
4 X X X
L
H
5 X X X
L
H
6 X X X
L
H
7 X X X
L
H
8 X X X
L
H
9 X X X
L
H
oX
D.
AXXX
L
H
C X X X
L
H
oX
X X
L
H
E X X X
L
H
F X X X
L
H
AS
A'
A3
A2
ADDRESS INPUTS
3628A
A'
0
X
=
=
ENABLE
=
=
NO SHORTING PWG
SHORTING PLUG INSTALLED
DISABLE
8 BIT DATA BUS
LEAVE JUMPER J20 OPEN (NO SHORTING PLUG)
L
H
BXXX
X=HEX
DIGITS
L = LOW BYTE
H '" HIGH BYTE
INSTALL SHORTING PLUGS
PER THE FOLLOWING TABLE:
DEVICE DENSITY = 8K BYTES
JUMPERS
,.,
PROMS.
AD
OUTPUTS
5·8
(I-illl~
0
X
2K
4K/8K
I
X
I
0
~
X
I J~4 I
I
0
I
Figure 4. 2764
5·29
AFN.()2()67A
AP-136
SYSTEM
ADDRESS
Ao-15
HEX
DECODER CIRCUIT INPUTS
BAF
BAE
BAD
8AC
ii'iiEN
LAO
BYTE
OXXX
W
L
H
1 XX X
W
L
H
2XXX
W
L
H
3XXX
W
L
H
~
LOWBVTE
=
HIGH BYTE
=
=
DISABLE
~
=
ENABLE
NO SHORTING PWG
SHORTING PLUG INSTALLED
W
L
H
DO
1
4XXX
L
H
16 BIT DATA BUS
W
L
H
5XXX
W
6XXX
L
7XXX
W
L
H
H
9XXX
W
L
AXXX
H
BXXX
W
L
H
'1
ex XX
W
L
H
DXXX
W
L
H
W
L
H
W
L
H
EXXX
FXXX
AS
x=
A4
A3
A2
A1
DIGITS
ADDRESS INPUTS
INSTALL SHORTING PLUGS
PER THE FOLLOWING TABLE
DEVICE DENSITY
'=
2K BYTES
JUMPERS
1-4
5-8
x
~
0
X
Im1ru
2KL
4K/8KI
AD
4
HEX
INSTALL SHORTING PLUG AT JUMPER J20.
W
L
H
W
L
H
8XXX
0
x
_1
I
I. J~41
I I
D
3
OUTPUTS
3628A
Figure 5. 2716 or 2816
5-30
AFN-02(]67 A
AP-136
SYSTEM
ADDRESS
AU-IS
HEX
DECODER CIRCUIT INPUTS
BAF
BAE
BAD
BAC
IIii!iii
CE'S
LAO
BYTE
,4
OXXX
W
L
H
lXXX
W
L
H
0
0
2XXX
W
L
H
3XXX
W
L
H
78
ESTAT
72 E8LK:
73,
74 ;
75 ;
76 ; _
.................................._
77;
78;
79 ;
80;
81;
82 ;
7831>
78JF
784ll
7842
7844
TEI1PORARY ST(MlE 5POCE
**-*_.._....__...._****
83;
84;
85 ESTAT:
J)5
S6 E2BUSY:
OS
87 HSGAOO:
J)5
88 SRCAOO:
OS
DS
S9 D£SAOO:
98;
2
1
2
2
2
5-36
AFN-02067A
AP·136
LIlC
(RJ
LII£
SUCE STATEIIENT
91;
92;
7&46 31987E
7849 D388
93 ;
94 INIT:
95
96
97;
98;
99;
1118 ;
7848 3EC3
181 ;
182
784D l2l888
183
7858 21AE78
7853 223988
184
185
186
187
188
189
118
7856 3E7E
7858 DR
785fI FB
785B 218378
185E 224878
7861 COE578
;
;
;
;
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111 ;
112
113
114
115
116
117
118 ;
119
128
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125 ;
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127 ;
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129 IIIINPG:
138 ;
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148 ;
141 ;
142
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143
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144
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145 ;
5-37
(F
DATA STRING
AFN.()2()67A
AP-136
LOC 08J
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146 i
147 i
148 ;
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7879 2190C8
787C 224278
787F 7E
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7891 212778
7894 224878
7897 roE578
789A 9E89
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149 ;
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159
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157
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158
159 ;
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161
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162
163
IIVI
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164
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165
; DATA TRflHSfER IS IN PROGRESS
166 ;
167 ;
168 ;
169 ;
178 ;
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171 ;
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172 ;
173 ;
174 PROCES:
175
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176
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177
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178 ;
179 i
180 ;
181 ;
Ota THE DATA TRffiSFER 15 WflETED THE IFERAT(R
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182 i
181 ;
184;
185 i
186 ;
187 FINISH:
188
LXI . H,FINHSG
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I15GAOO
198
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191 ;
192 ;
191 ;
194 RTISIS:
195
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D, EBI.J(
196
LXI
E 197
au ISIS
198 ;
199 ;
288 ;
5-38
AFN-02067A
AP-136
LOC IJ3J
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7SA5 224878
78A8 CDE578
78AB C39A78
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78C7224278
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If,ERRIISG
282
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283
SIU
284
CALL
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RTISIS
296 ;
287 ;
288 ;
289 ; .............. 111111111 ......
218 ;
. 211;
212 ;
SUIROOTINES
213 ;
214 ;
. 215;
216 ;
217 ;
218 ;
HN TIE E2 IKlRRD HAS CM'LETED ITS BYTE
219 ;
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228 ;
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221 ;
FR(II TJ£ RffI BLOCK IN) WRITTEN TO TI£ I£XT
222 ;
LOCATlOO 00 TIE E2 iQR).
221 ;
224 ;
225 ;
226 ;
227 SRYINT:
228
EI
229 ;
238 ;
SAVE ALL REG'S
231 ;
232
PUSH PSN
m
B
PUSH
234
PUSH
0
235
PUSH H
236
ruT
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; RESET TIE E2 so:IRD
237 ;
238
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DESAOO
219
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248
UlD
241
; om:tT DATA?
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242
JNZ
ERROR
243;
244 ;
YES, aJfTIH
245 ;
H
246
IIIX
247
I'KIY
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IPI
I!FFH
248
249
JZ
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258 ;
251 ;
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253
SIU
254
UlD
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255
IIIX
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5·39
AfN.«!087"
AP-136
LIE
5IlRCE 51ATEIENT
78CE 77
256
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78CF 224478
71>2 C3OfI78'
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; RES11:iE REG'S
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I
259 ;
268 ;
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7tlJ7 323f78
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261;
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262 ;
2631)(1£:
264
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11.8
265
51A
E2aJSY
78I)fI E1
78DB D1
78DC C1
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266 ;
267 REST:
26'8
269
278
271
7IIIlE lE28
IW
IW
IW
01
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272
273
274
275
. 7IIE8 DR
7tIE2 F1
7IlE3 FB
78E4 C9
276
277
278
279
288
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H
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IlRSTR
PSW
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;
;
;
;
281 ;
282 ;
78E5 2fM878
78E8 4E
78E9lEFF
78EB BE
78EC G8
78ED al8II88
7R21
-78F1 C3E878
283 OISIISG:
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284
285 1ISIlP:
286
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287
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288
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291
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292
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291 ;
294 ;
295 ;
296 ;
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C888
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298 RfIIILK:
299 ;
388 ;
381 ;
182 ;
38l
7846
8C888H
OS
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1888H
INIT
Pl8.IC SMnS
EXTERtR. SMnS
CI
E 8888
CO
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E 8888
5·40
BINI)
AP-136
USER 5YIIKlS
eI
E Il8II0
EI!lK A 7838
INIT A 7846
PISG.P A 78E8
SRYINT A 78AE
co
E IlIlIl8
ERRItSG A 78iR
INTI1SK A 8IlFC
OI.RSTR A 98fI)
STRAOO A 8008
ASSEIIIllY C(I1PLETE,
CR
A0Il0I)
ERROR A 78A2
ISIS E 11099
PROC£S A 7889
STXFER A 788l
DE5A)I) A 7844
ESTAT A 783D
LDLP °A 7867
RAI'IBlII' A C89(t
TRttISG A 7883
A 78DA
DOI£
FINISH
I1AItft
RTISIS
A 78D5
A 7891.
A 7864
A 789A
E2SUSY A 783F
FlltISG A 7827
tI5GAOO A 7848
SRCfI)I) A 7842
NO ERRORS
16-BIT DATA BUS STRUCTURI;
The XACK Generator returns the Transfer Acknowledge signal to the Multibus Bus Master after receiving
any memory or 110 command.
The Multibus card can use either an 8-bit or 16-bit data
bus. The PROM Array is organized in pairs of8-bit wide
MOS PROM's to enable the formation of a 16-bit word.
For a 16-bit data bus, the upper byte MOS PROM is
enabled whenever BHE (Byte High Enable) is low. The
lower byte PROM is enabled when AO is low. The upper
and lower PROM's can be enabled and accessed separately as individual bytes or together to form a word.
Accessing data by words takes half the time required to
do byte operations; thus the advantage of 16-bit systems over 8-bit systems.
The bus Address Decoder performs 2 functions:
1. Enabling the E2 Board within its assigned address
block for memory operations.
2. Enabling the RESET function and setting the Chip
Erase Mode whenever the proper 110 addresses are
written to.
The PROM Array Decoder enables the proper MOS
PROM for any given memory address.
HARDWARE DESCRIPTION
The Address and Data Latches hold the Bus address
and data values for the duration of the E2 write and
Chip Erase operations. During read operations, the
Data Buffers transfer the accessed data to the Multibus.
Overview
This discussion assumes an 8-bit data bus is being used
and applies equally to a 16-bit-wide system except that
whenever a byte-wide operation is being described,
two bytes (two MOS PROMs) in parallel are being
affected. '
,
The Vpp and OE Drivers provide the high voltage
pulses required for the byte erase, byte write, and Chip
Erase cycles while the SV to 24V Converters provide
the supply voltage for the Vpp and OE drivers. Tied to
these circuits is the Write Protection Circuitry which
prevents any spurious write cycles from occurring during the system power up and power down transitions.
The E2 Board hardware consists of the following
sections:
1.
2.
3.
4.
S.
6.
7.
8.
DIS/!SG A 78E5
A Il989
A 09IlA
EXIT
LF
REST
Sequencing and Timing
The figures referenced in the following 'subsections are
shown in the Schematic Section.
XACK Generation
Bus Address Decodhlg
PROM Array Decoding
Data and Address Latches and Buffers
Vpp and OE Drivers
SV to 24V Converter
Write Protection Circuitry
Sequencing and Timing
READ OPERATION
When MRDC goes low the RDEN signal also goes low.
, WR Mode is normally high when the E2 Board is not
being accessed and is not performing an operation. WR
Mode also stays high during a Read operation. The
address latches in Figure 12 remain transparent, and
lines BAC-BAF select one of the MOS PROMs in the
PROM Array via the 3628A Bipolar PROM decoder. In
Figure 13 the RDEN signal enables the 8287 transceivers to gate the output data onto the multibus.
RDEN also. causes OE ta go low to read the data out of
the MOS PROMs.
See the block diagram in Figure 8.
A brief description of the function of each circuit block
will be given. The circuit operation will then be discussed in detail in the subsections to follow.
The Sequencing and Timing circuitry generates the signals necessary to do the byte erase, bIte write, chip
erase cycles, and read cycles on the E PROMs.
5·41
AFN-02067A
AP-136
--{
BOARD AND 1/0
ADDRESS DECODE
XiCK GENERATION
I
I
SEQUENCING·
AND
TIMING
~
PROM
ARRAY
DECODE
1
I
ADDRESS
AND DATA
LATCHES
AND BUFFERS
ADDRESSES .-
I
I
-·DATA-·
I
5VTO
24V
CONVERTER
I
I
Vp~ND
DRIVERS
IL
I
PROM
ARRAY
I
1
WRITE
PROTECTION
Figure 8. ~ Board Block Diagram
now shut off (Vpp ON = 1) but the voltage 011 the Vpp
line will take a long time to discharge to 5V. This is due
to the 4.7 uf low-frequency decoupling capacitor, connected from Vpp to ground; the capacitor is needed to
suppress low frequency noise (See Figure 17). In order
to pull the Vpp line down fast, the Vpp Discharge signal
turns on Q8 which discharges the capacitor. When the
third one-shot times out, the Cycle Done One-Shot
starts, which clears the start Erase Cycle FF and forces
CE high (Figure 16 and Figure 10). The rising edge of
Cycle Done sets the Start Write Cycle FF and causes
the 74LS393 counter (Figure 10) to increment from 0 to
1. This starts the one-shot chain again to perform the
byte write cycle. The Data In En signal enables the
latched data onto the input lines. The one-shot chain
then delays, activates Vpp, and discharges the Vpp line.
This time the data byte is written into the selected 2816 '
address location. The 74LS393 counter is incremented
a second time and its QB output lowers one of the
Multibus Interrupt Lines. The CPU RESETS the E2
board with an IOWC command. The WR Mode FF, the
Start Write FF and the 74LS393 counter are cleared,
and the E2 Board is ready for the next operation.
WRITE OPERATION
Refer to Figures 10 and 11 and to the timing diagram in
Figure 9.
When MWTC goes low the BD WR signal also goes low
which sets the WR Mode FE The falling edge of WR
Mode latches the addresses as the falling edge of BD
WR latches the data. The rising edge of BD WR sets the
Start Erase Cycle FF, which in turn starts the one-shot
chain.
'
The first one-shot delays the rising edge ofVpp to provide some set-up time for CEo When the delay one-shot
times out, it triggers the Vpp ON one-shot. This second
one-shot turns on the Vpp driver for approximately
IOms. This is the byte erase cycle. Although the bus data
has been latched, the latch outputs are not yet enabled
by Data In En (Figure 13). The lK pullup resistors on
the LOO-LDl51ines pull the high-impedance latch outputs up to 5V. As a result, the data inputs to the
E 2PROM are all 1's which in turn erase the addressed
data byte. When the Vpp ON one-shot times out, the
Vpp Discharge one-shot is triggered. The Vpp driver is
5-42
AP-136
CHIP ERASE OPERATIO",
The Chip Erase Opel1ltion is quite similar to the byte
erase operation. The differences are:
1. The Chip Eralie FF is set by the Multibus CPU
before initiating the write operation. The Chip Erase
FF is set by doing an 10WC command to the Chip
Erase address.
2. When the write operation begins, the OE signal is
raised to 14.5V (Figure 17). The byte erase cycle
proceeds as before.'
3. At the end of the byte erase cycle the Cycle Done
signal does not set the Start Write Cycle FR Instead,
the Start Write Cycle FF is held in a clear state by the
INH Byte Write signal shown in Figure 10. Cycie
Done increments the 74LS3i}3 counter from 0 t9 1.
The QA output is now used to lower one of the
Interrupt Lines to signal the CPU that the Chip
Erase Operation is complete. When the CPU resets
the E2 Board, the Chip Erase FF is also cleared.
INITIALIZATION
The E2 Board must be RESET after power up. Due to
the write protection circuitry delay period after power
up, the RESET should not be sent until at least 1 second
after the CPU starts running. Once the board is RESET,
.
it is ready for a command.
XACK Generation
(Figure 11) The XACK (Transfer Acknowledge) signal
is driven low after a' delay period determined by the
tACC of the slowest MOS PROM in the PROM Array.
XACK stays low until the Memory or JlO command
goes back high. See the XACK delay subsection.
Bus Addr,ss Deco~,ng
Two sets of aqdresses need to be decoded for the E2
Memory Board: the memory space address for the
PROM Array and the I/O address for Chip prase Mode
and the RESET function. The 74LS85 comparators in
Figure 16, along with Jumpers J9-Jl2 and J13 ...Jl9, are
used to select the desired addresses and generate the
appropriate enabling signals when the selected addresses appear on the Multibus. The board memory
address is determined by' jumpers J9-Jl2. W\ten the
correct memory address is put on the pus, the MEM
EN signal goes low. The INm (INmBIT RAM) signal
is driven low on the Multibus to 'disable any RAM
memory that is occupying the same memory space as
the E2 Board.
When the selected I/O address· appears on the system
bus and IOWC goes low the BD lOW signal goes low
5-43
(Figure 16). If ADRO is low, the RESET function is
activated. If ADRO is high, the Chip Erase FF is set.
MOS PROM Array D~CQder
(Figure 12) Details on how to program the 3628A
Bipolar PROM decoder ar,e given in the Installation
Instructions under PROM Array Decoder. The 3628A
acts as a sophisticated decoder. The address input to the
3628A allows a maximum address range of 64K with a
minimum resol~tion of 2K. The AO and BHEN input
signals enable the 36284 to select the lower byte MOS
PROM, the upper byte MOS PROM, or both in parallel.
The 3628A output lines connj:ct to an 8282 8-bit latch.
The 8282 latches tlte decoder output to provide CE for
the 10ms erase lind write cycles. During read cycles the
8282 simply acts as a buffer for the decoder.
4d~ress and Dat~ L~tches and Buffers
The 8283s and 8282 of Figures 12 and 13 latch the
address and data frow the Multibus when the CPU
issues an MWTC command, These address and data
values stay latched throughout the Write Operation.
The addresses are latched on the falling edge of WR
Mode. The input d~ta from the bus is latched by the
falling edge of WR EN (See Figure 13). For Read
pp~rai:ions the'WR Mode signal stays high. A high on
the 6283 STB inpUt pu~stjlese latches in "transparent"
mode: they act as buffers for the bus addresses. The
8287s in Fiiure 13 act as data output buffers for the
accessed MOS PROM data.
The 8286 is used when the system data bus is 8-bits
wide. This transceiver transfers the data byte from the
LDO-LD710w byte data bus to LD8-LDI5 upper byte
aata bus for write ope~tions. For read operations, the
data byte from the LDS:-LD 15,byte bus is transferred to
the LDO-J.-D7 data byte bus. This byte swapping circuit
is actually adapting tbe 16-bit upper/lower byte structure to' an exihnal8-bit wide data bus. See the section
on l§-b~t Data Bus Structure for more information.
Ypp lI"d OE Drivers
Refer to Figure 17. The Vpp driver provides the 21V
Vpp programming pulse for the 2816. The pulse goes
from 5V to 21V with an exponential rising edge. The OE
driver is used to provide nominal TTL levels for read
and write operations. This driver also provides a 14.5V
level for the Chip Erase cycle.
SV to
~4V
C()nverter
Refer to Applicathms Note AP-103 in the E2PROM
Applications Handbook. (Also Figure 18.)
AFN-02067A
AP-136
Write Protection Circuitry
above. This keeps the Vpp driver disabled until about
SOOtns after Vee reaches SV. About 400ms before Vee
reaches SV, the Write Protect FF in Figure 10 is set by
the Multibus INIT signal. This FF will hold the Vpp ON
one-shot disabled until the CPU RESETS the E2
Memory Board and the Write Protect FE Thus, the
Q4/C30 circuit holds the Vpp driver off until long after
the TTL logic has stabilized and the Write Protect FF
has disabled the Vpp ON one-shot.
The Write Protection circuits are designed to prevent
the TTL control logic from causing an E2 write/erase
cycle to occur during the periods of board power up or
power down. The 747 op-amp in Figure 18 senses when
the board SV supply has dropped below the voltage
level on C41. When this happens, the op-~p disables
the Vpp driver by grounding C38 (Figure 17). This prevents the capacitor from charging up the 21V-it is the
exponential rising voltage on this capacitor which is
used to generate the Vpp programming pulse's rising
edge.
The purpose of the Write Protect Flip Flop is to prevent
the 2816s from being written to by the InteJlec Monitor
Program immediately after power up. The Intellec
Monitor tries to write to every location in its addressable range after power up. This is done to determine
how much RAM is in the system. In a non-Intellec
system the INIT signal is not really needed as long as no
System Write commands' occur other than those
generated by the user.
When the E2 Board is powered up, the rising Vee
voltage begins charging up capacitor C30. Until the
voltage on C30 is high enough to, turn on Q4
(approximately 3.SV), this transistor will hold the vpp
OFF signal low. This is the same signal in Figures 18 and
17 that is used by the power-down circuit described
SCHEMATIC DIAGRAMS
iilW'fC(BDWR)
••
~
~~
START ERASE CYCLE
\ : : '> - - -----+---
"---::::t===:::::
~I
_ [:
----t\.\
---------;J.,jj
INTERRUPT -
__--'
_ _ _ _ _ _ _ _.....,.._, ..
, _ _ _. . -_ _ _..,...._ _ _........,..._ _....
RESET ---------~-.
(FRO.,
CPU)
BDWR
-----10---__;....., ......------
> _ _ - -.....
-
START WRITE CYCLE
CYCLE DONE
V"ON
I ..
-Jf.
___
-.J
,>-----t-----+-----; -+-----{
\~-.--------r_----_r--------r_--------BYTE
ERASE
CYCL~
BYTE
WRiTE
CYCLE
Figure 9. Writ~ Operation: Byte Erase and Byte Write Cycles
5-44
AFN-02067A
AP·136
CHIP
E:~~~
>-____________________--,
r--------~::~::::::::::::::::::::::::::::::WRMODE
WR MODE
IL_-+________
J.._---P~:.;f!-------------CH'P ERASE
DIP SWITCH 1
~>--,--~--~-------,
J1
@~~§
37 INT4
38 INT5
35
'-_--'--
fIim
36 INT7
milN
r------------~r---------------------------m
r---------------~
, - - - - - - - - - -__ v"
DISCHARGE
CYCLE
DONE
Figure 10. Write and Erase Sequencing and Timing
~>---------------,
MEM EN
>------------,
r---------------------.IDWR
r--~i;~--------~~~~77---·BDWR
~t_------------------------------~~Mnrn
lowe 22
L-________________________________________________________
NOTES
1 TO SELECT R7 USE THIS TABLE AND THE ~cc VALUE OF
ALL DIODES ARE 1 N914 UNLESS OTHERWISE NOTED
ALL RESISTORS ARE IN OHMS
THE SLOWEST PROM
(nsJ~8cc
250
350
450
650
~Iowe
XACK DELAY (ns)
R7
250
300
400
500
700
12K
18K
22K
30K
7K
Figure 11. XACK Generator
5·45
AFN-02067A
H
SADR0
11
co
c
ADR1 58
AOlI1 5 5
E4
8283
r--""'"- '
DIO
2 DI1
3 Dl2
4 013
Ii
~
AiiR5 54
6 Dis,
:.a.
ADR6 51
AOR7 5 2
7 Di.
8 D17'
mm
''fl';
"
It
01
.i:0">
III
III
::I
a.
I:
0
1iDlIli 5 0
A1lIiA 4 7
ADl!lI • 8
iimIC 45
AliRE
43
BHEN 27
D02
D03
D04
D05
DD6
,.
,.
17
,I
'I
.7t-!!4 3
V
BECKMAN
784-1-A1'K
5V
RP-4
r - ...,------,
f1.L-
18
2
007 12'
DE
V
BAF
UIiIE
15
~2
BAC
5~2 6 BAD
V 11~2 10
C
...
DI3
014
DIS
016
DI7
STB
BADRO
III
It
19
DOO
DOl 141
~J
...
8a.
•
5
6
7
8
AJOOj 46
'<
It
1
DIO
2011
3 012
~. 9
rn
:....
LAB
LAC
LAD
8283
'V
:II
0
I:
LAA
D4
III
go
16
~ 15
Im5 14
Iro6 13
~ 12
1-"T8,0.
a.
Ii
01:
:7
LAl
LA2
LA3
LA4
LAS
LAO
LA7
LA8
LA9
17,
!!03
5 DI4
53
LAO
llll2
1iDR"3 56
...
DOG 19
IlO'l 18
B4
8 AO
III
p,
Do 9
D 10
7 Al
o A2
5 A3
III
SWl
SW2
DIP$WITCH SW3
Jl Isw.
SW5
~
/
5V
------
r2
-.
Bi~~~~~ :,~ ~M
"
'4rs "i
1M
:".
,
lK:
I
L.---RP,a"--.J
•
3
2
1
23
22
21
I
I
I
I
I lK
I
L_
Kl
3628A
f- ...J
8 '2
3 0 1 5
4
El
'"
A4
A5
AO
A7
A8
A9
CSl
~
O2 '130 314
eo
D,
E4
Os 15
E5
D 18
6 17
D,
E6
E7
RP-S
8
lK
1
CS2 CS3 CS
20
Eli
1'9 1'8 RO
lK
5V
5Y
AP-136
74505
r--1!£?
I
10
I
B3
11 ....
v.a
2
5
74S30
J2
8
BECKMAN 784-1-AIK
1
r ------------,
,..-----li
APS
Ll
1 010
2011
3 012
4 013
5 014
6 DIS
Die
017
2
DOG 19
001
D02
D03
D04
DOS
DOe
D07
5V
11
1_1K
I
I
I
I
L
.....!!!L
~
10
- f - - -- --3
5
6
7
8
18
17
16
15
:4
12
7
3-f
9
4
I
I
J
-
AP3
11
lK
1
5V
Figure 12a. CE Latch
5-47
AFN-02067A
AP-136
DATA IN
EN
=
1
iiim
DAT2
DAT3
~
JW2
!lAf4
tIAT!;
BOWR~
OATS
DAT7
R32
1K
1
2
3
4
5
6
7
8
73
74
71
72
69
70
67
68
19
DOD 18
001
17
002
jjQ3 16
004 15
jjlj5 14
D06 13
12
r
19
18
17
i507
8287
K4
II1i
B1
AO
A1
A2
A3
A4
A5
A6
A7
T
11
B2
16
B3
15
94
14
>---e
LOO
L01
L02
L03
L04
LD5
L06
L07
STB
11
9y
~
JW8
,BOWR
8283
J4
010
011
012
013
014
015
016
017
OE
B5
~ 86
L.-.-..!l i!'I
OE
9'(
1
1
2
3
4
2
3
4
5
6
7
8
6
7
----1
1
1
1
1
1
K3
BeCKMAN
RESISTOR PACK
898-1-R1K
I
J
---
1
5V
RO EN
1K
R30
5V
WRMODE
1 2 3 4 5 6 7 8
F3'
L9HE
LAO
~2
-~"
0
13
65
om 66
DATA 63
DATli 64
DATe 61
DATD 62
DATE 59
OATF 60
8
t t t ~ l: ~
8286
9
~~~~f!f~~g::~
"" ... "''" .. woo
5V
R9
20
8283
H4
010
000
011
001
012
002
003
013
014
D04
015
i505
016
lll!6
017
007
OE STB
11
9'(
19
18
17
16
15
14
13
12
8287
F4
19
AO
18
B1
A1
17 ~
A2
16 ii3
A3
15 B4
A4
14 B5
A5
86
A6
~
<----..E i!'I
A7
OE
T
eo
fiBEiii
~ ~
1K
1
2
3
4
5
6
7
8
rID1i
9
11
-t
J3
41H2~
13_
F2
12
RifErii
LBHE~
1.
11
5
9y
11
1K
1
2
3
4
5
6
7
8
L08
LOO
LOA
LOB
LOC
LOO
LOE
LOF
21----1
15
14
13
12
11
10
9
1
I H3
BeCKMAN
I RESISTOR PACK
I 898-1-R1K
1
r-16I
5V
R30
5V
Figure 13. Data In Latch, Data Out Buffer, and Upper/Lower Byte Transceiver
5·48
AFN-Q2067A
AP-136
,.
CEO
LA1
•
~
~5V
..
CE
Vee
AO
0 0 11
A1
I
A.
7
A3
LA'
LA.
LAO
••
•
•
LA5
LA.
LA7
LA.
LA.
.5
20
LAA
LAB
LAD
..
PROM
•
AS
A7
A.
LD1
0 2 13
LD.
0, 15
LD.
0 4 11
LDO
0 5 17
LD5
0,
LDI
M1
p,
,.,.
LD7
AnNpp
OE PGMVpp
..
,. AO
,
271 ~
22
,
0, 12
1
A.
21
A1.
2
A12
----1!
LO.
'
~
CE
5V
Vee
0."
•
A1
·..
0,
•7 A3
A2
>--
PROM
••
5 ..
0 ..
.
3 .7
.5 . .
0, 15
0. ,.
N1
0,
A.
r--E
17
0, ,.
21 .10
f---!
12
0,13
A12
Or
A11Npp
OE PQMVpp
,.
" 271 ~
0E1
,.
••
).
.. ~
..
CE
Vee
AO
0."
LDO
Of 12
LDI
0,"
LDA
••
0,15
LDB
0. ,.
LDC
L2
0, 17
LDD
A1
·.
A2
7 A3
5 AS
4 ..
PROM
•
....
A7
.5 . .
0,"
0, ,.
21 A10
•
~
5V
A12
LDE
LDF
A11N,p
oe PGM V••
l
E.
·• .,.
,. AO
··..
....
" T27 ~
). .. ~
CE
Vee
11
0,12
7 A3
5 AS
"
PROM
••
• A7
25 . .
J21
J22
0, 15
0. ,.
N2
0,17
21 A10
0,"
A12
0, ,.
.;
5V
A11lVpp
OE PaM V
"T27!
~
sv
A1 1K
Figure 14•. MOS PROM Array
5·49
AfN.02Il87 A
AP-136
~5V
CEO
20
10
LA'
LA2
26
CE
•
V"
AD
00
Al
8
A2
7
A'
6
PROM
A.
5
#
A5
5
A6
A7
25
AS
2.
A.
21
A10
2
A12
A11Np?
LA'
LA.
LA5
LA6
LA7
LA8
,•
LA'
LAA
LAB
LAD
0,
.,
LDO
12
LDl
0, 13
LD2
0, 15
LO'
0, 16
LD.
0, 17
LD5
0,
0,
~
"
"
"
LD6
LD7
OE PGM V pp
L,
"
~
V"
AD
Al
0,"
8
.2
7
A3
6
A.
5 A.
0,13
•
0, 12
PROM
#
0,15
.,
•,
7
A6
A7
25 A8
2.
A9
21 A10
f----1.
f---E-
5V
26
CE
10
r--
22 271
0,
0,
16
17
,.
0,"
A12
0,
A11Npp
OE PGM Vpp
221271 ~
OE
•
~
.l"
26
CE
10 AD
Al
8 A2
7 A3
6 A4
5 A.
V"
•
•,
PROM
LD8
0, 12
LD'
6
0,
A7
13
LOA
0,15
#
.2
25 A8
2' A.
21 A10
A12
~
~
0,"
0,
A6
5V
0,
LOB
16
LDC
17
LDD
\(4 18
0,
A11Npp
LDE
19
LOF
OE PGM Vpp
22127\
7
.l"
CE
10 AO
0,"
0,
6 A.
0,
A.
A6
A7
AS
f---!23
J23
J2'
12
13
PROM
#
8
0, 15
.2
0, '17
24 A9
21 A10
•
~
5V
26
Vee
• Al
8 A2
7 A3
•
•
,
25
.
~
04 16
0,"
A12
0,19
A11Np?
~"
DE
PQM Ypp
22\27IS
5V
R1 lK
Figure 15. MOS PROM Array
6-50
AFN-Q2067A
AP-136
.5V
R10
F3
F3
...-____________---:13=t
12
5V_-.lW'----,
10
9 F2
E
IOic
t-------------------------------;--------------BADRO
AliIfi 58
ADAli 55
AI)ft3
561---------'-1
.--------f-------------- POWER RESET
F3
ADJII 57t-----'9.;>O=----------......4 >O"'-T---""l.:.:.r
DRf
1.~-----=--------------------------~~~t_--------------:J~~~-L-------------RBUrr
L-------------------------------------- BADRO
Figure 16.
Board Addre •• location Selection, RESET and Chip Era.er 1/0 Addre •• Selection
5-51
AFN.()2(J67A
AP-136
24v>---------.---------~~r_--r_------------------------------------~
R21
10K
1N4747A
20V
5V
VppOF~>-----------~------_,
R22
CRll
HP5082-2800
12K
Q7
7407
VppON
>-__~1~~2~-L______~
C3B
+-__
L_________
2N4923
CR.
.OSf.l.F
K2
IN914
R18
-A~----L---------~--~~~~--~---------+--.V,'
47.
Vpp FINE ADJUST
R12
24V
R13
>-----,-----........N'------.---.I'N-----,
2.
R1S
10K
7407
oHIPERASE>-----------------------------9C~-------------------L----------__i
.2
7407
RDEN
WRMODE
>-r:============~'3~H~2)J'~'--------~~~--------------------------------+_----------~OE
12
K2
RS
2K
5V
Figure 17. Vpp and OE Drivers
+12V
5V
+C46
.-____----'__----114.7 "F
CR5
5V
f.i.A747
1K
CR7
R25
5V
045
01"FT
R17
lOOK
CR4
CR3
7.
-12V
80f--L-----------------'
+
4.7 f.l.F
5V
~
C30
C32
H')f=+'-'--.---,-~ 24V
C3.
300pF
R24
R27
1.2K
18K
/
Figure 18. 5V to 23V Converter and Power Up/Power Down Write Protection Circuitry
5·52.
AFN-02067A
AP-136
ASSEMBLY INSTRUCTIONS
7. Install and solder resistors and resistor networks at
the following locations:
1. Install and solder the following Integrated Circuits:
A4
B4
D4
E4
F4
H4
J4
K4
-
74832
748240
8283
8283
8287
8283
8283
8287
A3
B3
C3
D3
E3
F3
J3
-
74S10
74S05
74LS85
74L885
74LS85
74LS04
8286
A2
B2
C2
D2
E2
F2
H2
J2
K2
Al
B1
C1
D1
E1
F1
HI
L1
N4
M4
P4
-
74804
74800
74808
74L874
74L808
74L800
74LS32
74S30
7407
-
9602
PE-21216
74LS393
74LS74
74LS74
9602
9602
8282
-
TL497A
UA747
LM358
~
H3
K3
RPI
RP2
RP3
RP4
RP5
-
898-1-R1K
898-1-R1K
784-1-R1K
784-1-R1K
784-1-RIK
784-1-R1K
784-1-R1K
R6
-
lK
24K
6.2K
10K
24K
1K
R5
R4
R3
R2
R1
R32
RIO
R9
R8
-
R19
-
R31
R30
-
1K
1K
1K
2K
R16
R17
-
4.7K
lOOK
R29
R28
-
33,1/2 W
0.5, 1/2W
R27
R24
R23
R15
R22
R21
R20
R18
R12
R13
R14
R25
-
18K
1.2K
24K
10K
12K
10K
1.2K
47K
2K
12K
1K
1K
-
5K
Mini-potentiometer
1K
lK
2. Install and solder a 24-pin socket at KI.
8. Install and solder capacitors in the following
locations:
3. Install and solder 28-pin socketsatM1, L2, N1, N2,
PI, P2, R1 and R2.
4. Install and solder jumper pin pairs at the following
locations:
Jl
J2
J3
J4
J5
J6
J7
J8
J9
JlO
Jll
Jl2
J13
Jl4
Jl5
Jl6
Jl7
Jl8
Jl9
J20
5. Break in half 4 jumper pairs.
Install and solder one jumper pair at J21. Install and
solder one of the single jumper pins at 122.
C13
C12
Cll
C10
C9
C8
C7
C6
C5
C4
C3
C2
C1
-
0.1 pi
0.1 pi
0.1 pi
0.1 pi
0.33 pi
4.7 pi
20pf
0.1 pi
0.1 pi
0.1 pi
0.1 pi
0.1 pi
0.1 pi
C23
C22
C21
C20
-
0.1
0.1
0.1
0.1
pf
pi
pi
pi
C19
C18
C17
C16
C15
-
C28
C27
C26
C25
C24
-
C37
C49
C36
C35
C34
C33
C48
~
pi
pi
pi
pi
pi
0.1 pi
0.1 pi
0.1 pi
0.1 pi
0.1 pi
0.1 pi
22 pi
0.1 pi
0.1 pi
0.1 pi
0.1 pi
22 pi
0.1
0.1
0.1
0:1
0.1
Install and solder another single jumper pin and one
jumper pair at J23 and 124.
9. Install and solder the following diodes:
Install and solder jumper pairs at JW7, JW3, and
JW2.
CR1
CR2
CR3
CR4
CR5
CR6
Install and solder single jumper pins at JW8, JW4,
JW1, JW6, and JW5.
6. Install and solder the Dipswitch at location JI.
5-53
1N914
1N914
1N914
1N914
1N914
1N914
CR7
CR8
CR9
CR10
CRll
CR12
-
1N914
1N4747A
1N914
1N914
HP5082-2800
1N914
AP-136
10. Install
Ql
Q2
Q3
Q4
Q5
Q6
an~
-
11. Install and solder the following capacitors:
solder the following transistors:
2N2222A
2N3904
2N3904
2N3904
2N3904
2N3553
C40
C47
C45
C39
C43
C38
C32
If hardware is provided or available, mount transis-
tors in the following locations:
Q7
-
-
0.1 pI
0.1 pI
0.1 pI
300 pf
0.1 pI
0.05 pI
0.1 pI
C41
C44
C42
C31
C30
C46
-
4.7 pI
4.7 pI
4.7 pI
22 pI
4.7 pI
4.7 pI
12. Install and solder the 62 ~ RF choke at location L1
(just above the 60-pin edge connector).
2N4923
Solder the leads of Q7 and Q8 to the solder pads on
the board.
5·54
AFN-02067A
AP-136
APPENDIX A
JUMPER LIST
Jl
J2
13
J4
J5
J6
J7
J8
INTO
INTI
INT2
INT3
INT4
INT5
INT6
INT7
J9
JIO
JIl
JI2
(ADRI0)
(ADRll)
(ADRI2)
(ADR13)
JI3
J14
J15
J16
JI7
J18
JI9
(ADRl)
(ADR2)
(ADR3)
(ADR4)
(ADRS)
(ADR6)
(ADR7)
4 bit selection of one of
16 64K pages for board
add~ess
-Note: these ADRs are in HEX
Select I/O address for Chip Erase
Mode (ADR 0=1) and RESET function
(ADR 0=0)
J20 Jumpered for 16-bit wide data bus, Open for 8-bit wide data bus.
NOTE: The proper decoding algorithm for the data bus must be used in
the BIPOLAR PROM decoder-refer to the PROM Array Address
Configuration subsection of the Installation Instructions.
J21 (Select 4KJ8K)
J22 (Select 2K)
MOS PROMs 1-4
123 (Select 4KJ8K)
124 (Select 2K)
.
MOS PROMs 5-8
JWl
JW2
JW3
JW4
JW5
JW6
JW7
JW8
8-bit wide static RAM
5-55
AFN.02067A
AP-136
APPENDIX B
BIP DECODER DATA FORMAT
3628A, 1K X 8, 000-3FFH
Data = alII's at all locations not shown.
o = Switch is on
1 = Switch is off
,
SW4
SW3
SW2
SW1
0
0
0
0
0
0
0
0
0
I
1
0
(Hex)
Address
(Hex)
Data
2
3
6
7
A
B
E
F
FE
FD
FB
F7
EF
DF
BF
7F
42
43
46
47
4A
4B
4E
4F
52
53
56
57
5A
5B
5E
5F
FE
FD
FE
FD
FB
F7
FB
F7
EF
DF
EF
DF
BF
7F
BF
7F
82
83
86
87
SA
8B
8E
8F
FE
FD
FE
FD
FE
FD
FE
FD
FB
F7
FB
F7
FB
F7
FB
F7
EF
DF
EF
DF
EF
DF
EF
DF
BF
7F
92
93
96
97
9A
9B
9E
9F
A2
A3
A6
A7
AA
AB
AE
AF
B2
B3
5-56
Decoding for
2K X 8
(2816, 2815 OR 2716)
8-BIT DATA BUS
4KX 8
(2732, 2732A)
8-BIT DATA BUS
8KX8
(2764)
8-BIT DATA BUS
AFN.()2()67A
AP-136
(Hex)
Address
(Hex)
Data
0
B6
B7
BA
BB
BE
BF
BF
7F
BF
7F
BF
7F
8K x 8
8-BIT OATA BUS
(Continued)
1
CO
Cl
C2
C4
C5
C6
C8
C9
CA
CC
CD
CE
FC
FO
FE
F3
F7
FB
CF
OF
EF
3F
7F
BF
2KX 8
16-BIT OATA BUS
100
101
102
104
105
106
108
109
lOA
IOC
10D
lOE
110
111
112
114
115
116
118
119
llA
11C
lID
lIE
FC
FD
FE
FC
FD
FE
F3
F7
FB
F3
F7
FB
CF
DF
EF
CE
DF
EF
3F
7F
BF
3F
7F
BF
140
141
142
144
145
146
148
149
14A
14C
14D
14E
150
151152
154
155
156
FC
FD
FE
FC
FD
FE
FC
FD
FE
FC
FD
FE
F3
SW4
SW3
SW2
SW1
0
0
1
0
0
1
0
0
1
1
0
0
0
1
Decoding for
(2816, 2815, OR 2716)
;
4KX 8
16-BIT DATA BUS
(2732 OR 2732A)
8KX8
16-BIT DATA BUS
(2764)
F7
FB
F3
F7
FB
5-57
AFN-Q2067A
AP-136
(Hex)
Address
(Hex)
Data
I
158
159
15A
15C
15D
15E
160
161
162
164
165
166
168
169
16A
16C
16D
16E
170
171
172
174
175
176
178
179
17A
17C
17D
17E
F3
F7
FB
F3
F7
FB
CF
DF
EF
CF
DF
EF
CF
DF
EF
CF
DF
EF
3F
7F
BF
3F
7F
BF
3F
7F
BF
3F
7F
BF
8K x 8
16-BIT DATA BUS
(Continued)
0
IA2
IA3
IA6
IA7
IAA
lAB
IAE
IA7
FE
FD
FB
F7
EF
DF
BF
7F
LOCATED AT 8000H
8-BIT DATA BUS
lEO
lEI
lE2
lE4
lE5
lE6
lE8
lE9
lEA
lEC
lED
lEE
FC
FD
FE
F3
F7
FB
CF
DF
EF
3F
7F
BF
LOCATED AT 8000H
l6-BIT DATA BUS
SW4
SW3
SW2
SW1
0
I
0
0
I
I
0
I
I
I
5-58
Decoding for'
(2716. 2816 OR 2815)
(2716. 2816 OR 2815)
AFN-Q2067A
AP-136·
APPENDIXC
PARTS LIST
Table C-1. Integrated Circuits
Qty
Table C-3. Discrete Components
Description
1
4
1
2
3
1
3
3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
3628A-4
8283
8286
8287
74LS85
74LS393
9602
74LS74
74LS08
74S10
74S30
74LS32
74LS04
74LSOO
74S00
74S05
8282
74S08
74S04
74S32
74S240
LM358
TTL Delay Line PE-21216
J.tA747
7407
TL497A
36
TOTAL
Qty
1
1
2
1
1
1
1
2
3
6
1
2
3
1
1
1
34
3
1
1
1
9
Description
.
Cap., 20 pf
Cap., 50 pf
Resistor, 12K
Cap., 0.33 JLf
Cap., 0.05 JLf
Resistor, 47K
Resistor, 6.2K
Resistor, 2K
Resistor, 10K
Cap., 4.7 JLf
Mini-potentiometer, TrimPot
3009p-I-502,5K
Resistor, 1.2K
Resistor, 24K
Resistor, 18K
Resistor, 33, 1I2W
Resistor, 0.5, 1I2W
Cap., 0.1 JLf, 50V, ceramic
Cap., 22 /Lf, 25V
Cap., 300 pf
Resistor, lOOK
Resistor,4.7K
Resistor, lK
Table C-2. Discrete Components
Qty
Description
1
1
4
1
11
1
t
1
1
5
2
1
1
8
29
18
2N3553
2N4923
2N3904
2N2222A
IN914
HP5082-2800
(Schottky Diode)
IN4747A
R.E Choke, 62 /Lh, 475 rna
J. W. Miller 4630
Resistor Network
Beckman 784-1-RIK
Resistor Network
Beckman 898-1-RIK
Dip Switch, CTS 206-8
24-Pin Socket
~
28-Pin Sockets
Header Pins
Shorting Plugs
5-59
AF~7A
01
0,
o
AP·136
APPENDIX E
MULTIBUS PCB DIMENSIONS
0.25 X 45
rI-
0
12.000 REF
)
(2PLACES~
0.109 DIA
-I
11.500 REF
!-0.250REF
o
/.
i_~5,....
(3 HOLES)
5.950
"0.005
COMPONENT SIDE
6.20
6.75 REF
If
0.06 R
(12 PLACES)
I.
--
86-PIN
0.156" cc
6O-PlN
--
01"cc
'11
.1.
6.767:!: 0.005
5-61
Ir
- 0 l-~
':"---n, .
~3.060
.1
~•.st-O.30
4.570
AFN-D2067A
Ap·136
APPENDIX F
MULTIBUSSIGNAL LIST
Pin
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Signal
GND
OND
Vee
Vee
Vee
Vee
VD D
V()()
GND
GND
BCLKJ
INIT/
BPRN/
BPRO/
BUSY/
BREQ/
MRDC/
MWTC/,
IORCI
IOWq
XACKJ
INHlI
AACK/
BHEN/
ADIO/
Function
Pin
Ground
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
Source power +5 VDC
Source Power +12V DC
Ground
Bus Clock
Initialize system
Bus priority in
Bus priority out
Bus busy
Bus request
Memory read command
Memory write commapd
110 read command
110 write command
Transfer acknowledge
Inhibit 1 disable RAM
Advanced 8080
acknowledge
Byte High Enable
AD III
ADI2/
AD 13/
INT6I
INT7/
INT4/
INT5/
INT2I
INT3/
INTO/
INTI/
ADRE/
77
78
79
80
81
82
83
84
85
86
External Interrupt
Level Requests
ADDRESS BUS
5-62
Signal
Function
ADRF/
ADRC/
ADRD/
ADRA!
ADRB/
ADR8/
ADR9/
ADR6/
ADR7/
ADR4/
ADR5/
ADR2/
ADR3/
ADRO/
ADRlI
DATE/
DATF/
DATC/
DATD/
ADDRESS BUS
DATA!
DATB/
DAT8/
DAT9/
DAT6I
DAT7/
DAT4/
DAT5/
DAT2/
DAT3/
DATO/
DATlI
GND
GND
VBB
VBB
Vee
Vee
Vee
Vee
GND
GND
DATA BUS
Ground
Source power -12 VDC
Source power +5V
Ground
AFN.()2()67A
AP-136
APPENDIXG
BLANK DECODER CHARTS
SYSTEM
ADDRESS
AO-15
HEX
OXXX
1 X X X
DECODER CIRCUIT INPUTS
BAF
BAE
0
0
0
0
Bf'D
CE'S
BAC
BHEN
LAO
0
1
1
0
1
L
H
1
1
1
0
1
L
H
0
1
L
H
0
0
7
6
5
4
3
2
1
0
BYTE
2 X X X
0
0
1
0
1
1
3 X X X
'0
0
1
1
1
1
0
1
L
H
4 X X X
0
1
0
0
1
1
0
1
L
H
5 X X X
0
1
0
1
1
1
0
1
L
H
1
1
0
1
L
H
6 X X X
0
1
1
0
7 X X X
0
1
1
1
1
1
0
1
L
H
0
1
L
H
8 X X X
1
0
0
0
1
1
9 X X X
1
0
0
1
1
1
0
1
L
H
A X X X
1
0
1
0
1
1
0
1
L
H
BXXX
1
0
1
1
1
1
0
1
L
H
0
1
L
H
C X X X
1
1
0
0
1
1
o
X X X
1
1
0
1
1
1
0
1
L
H
E X X X
1
1
1
0
1
1
0
1
L
H
FXXX
1
1
1
1
1
1
0
1
L
H
X=HEX
AS
A4
A3
A2
DIGITS
ADDRESS INPUTS
A1
AO
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
L
"'" LOW BYTE
H "" HIGH BYTE
== ENABLE
=
DISABLE
~
NO SHORTING PLUG
=
SHORTING PLUG INSTALLED
8 BIT DATA BUS
LEAVE JUMPER J20 OPEN. (NO SHORTING PLUG)
INSTALL SHORTING PLUGS
PER THE FOLLOWING TABLE
DEVICE DENSITY
=
K BYTES
JUMPERS
PROMS:
1·4
5·8
OUTPUTS
3628A
5-63
AFN.()2()67A
AP-136
SYSTEM
ADDRESS
Ao-15
HEX
OXXX
0
1XXX
0
SAE
0
IjIAD
SAC
0
0
BHEN
LAO
0
1
0
0
0
1
0
2XXX
0
0
0
1
0
0
1
1
0
0
0
1
0
0
1
0
1
0
0
3XXX
4XXX
0
0
0
1
1
1
0
0
1
0
0
0
1
0
1
0
1
0
1
1
0
1
0
0
1
7XXX
0
0
1
1
1
0
1
1
6
5
4
3
2
1
0
BYTE
W
L
H
W
L
H
W
L
H
W
L
H
0
0
1
0
1
W
L
H
8XXX
1
0
0
0
1
0
0
0
1
W
L
H
9XXX
1
0
0
1
0
1
0
0
0
1
W
L
H
AXXX
1
0
1
0
0
1
0
0
0
1
W
L
H
BXXX
1
CXXX
1
0
1
1
1
0
0
0
0
1
0
1
0
0
1
0
0
0
1
0
1
0
0
0
1
0
0
0
OXXx
1
EXXX
1
1
1
0
1
FXXX
1
1
1
1
1
0
1
A5
A4
A3
A2
A1
AO
1
0
1
0
0
W
L
H
ADDRESS INPUTS
o
~
ENABLE
1
-=
DISABLE
~
NO SHORTING PLUG
'= SHORTING PLUG INSTALLED
16 BIT DATA BUS
INSTALL SHORTING PLUG AT JUMPER J20.
INSTALL SHORTING PLUGS
PER THE FOLLOWING TABLE:
DeVICE DENSITY
~
BYTES
W
L
H
W
L
H
W
L
H
W
L
H
1
0
0
0
7
X = HEX
I ITS
OG
LOW BYTE
HIGH BYTE
W
L
H
0
0
1
0
~
==
W
L
H
1
0
L
H
W
L
H
0
0
6XXX
7
0
0
0
0
5XXX
«'S
DECODER CIRCUIT INPUTS
SAF
0
6
0
5
0
0
0
0
4
3
2
1
JUMPERS
PROMS:
1·4
5·8
0
0
OUTPUTS
3628A
5-64
AFN-02067A
AP-136
APPENDIX H
TEST DECODING ALGORITHMS FOR
2K X 8 MOS PROMs AT 8000H
SYSTEM
ADDRESS
AO-15
HEX
oX
X X
CE'S
DECODER CIRCUIT INPUTS
6'
BAF
BAE
BAD
BAC
BiiElii
LAO
0
0
0
0
1
1
0
1
L
H
7
5
4
3
2
1
0
BYTE
1 X X X
0
0
0
1
1
1
•
1
L
H
2 X X X
0
0
1
0
1
1
0
1
L
H
3 X X X
0
0
1
1
1
1
0
1
L
H
4 X X X
0
1
0
0
1
1
0
1
L
H
'0
1
L
H
5 X X X
0
1
0
1
1
1
6 X X X
0
1
1
0
1
1
0
1
L
H
7 X X X
0
1
1
1
1
1
0
1
L
H
8 X X X
1
0
0
0
1
1
0
1
1
1
0
1
0
0
L
H
1
0
0
1
A X X X
1
0
1
0
1
1
0
1
1
1
1
0
1
0
1
L
H
1
0
1
0
1
1
0
0
o XXX
1
1
0
1
1
1
0
1
L
H
E X X X
1
1
1
0
1
1
0
1
L
H
0
1
L
H
AO
X~HEX
1
1
1
1
A5
M
A3
A2
A1
DIGITS
ADDRESS INPUTS
0
7
0
6
ENABLE
~
DISABLE
o
=
NO SHORTING PLUG
X == SHORTING PLUG INSTALLED
8 BIT DATA BUS
LEAVE JUMPER J20 OPEN (NO SHORTING PLUG)
L
H
0
0
CXXX
F X X X
=
L
H
0
0
1
1
1
1
o
1
L
H
0
9 X X X
B XXX
L -:= lOWBVTE
H == HIGH BYTE
0
5
0
4
OUTPUTS
3628A
0
3
0
2
0
1
INSTALL SHORTING PLUGS
PER THi. FOLLOWING TABLE.
DEVICE DENSITY == 2K BYTES
JUMPERS
PROMS
1-4
0
0
5-8
2Kr-~~~-tt-~~~~
4KJ8K
5-65
AFN-02067A
AP-136
SYSTEM
ADDRESS
HEX
-
CE'S
DECODER CIRCUIT INPUTS
AO-1S
BAF
BAE
BAD
BAC
LAO
7
6
S
4
3
2
1
0
BYTE
0
1
0
0
0
1
W
L
H
OXXX
0
0
0
0
0
0
0
1
0
1
0
0
0
1
W
1XXX
0
0
1
0
0
1
0
0
0
1
W
2XXX
W
0
0
1
1
0
1
0
3XXX
0
0
1
L
H
0
0
W
1
0
0
4XXX
0
1
0
0
0
1
0
1
6XXX
0
1
1
0
0
0
W
7XXX
0
1
1
0
1
8XXX
1
0
0
0
9XXX
1
0
0
1
AXXX
1
BXXX
1
CXXX
1
DXXX
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
1
0
0
0
0
1
0
EXXX
FXXX
1
1
AS
X" HEX
DIGITS
1
1
A4,
1
0
0
1
0
0
0
0
0
0
L
H
W
0
0
L
H
W
0
0
L
H
INSTALL SHORTING PLUGS
PER THE FOLLOWING TABLE
0
W
L
H
DEVICE DeNSITY _~ BYTES
0
0
0
W
1
L
H
0
W
0
1
0
0
L
H
1
0
0
1
W
L
H
0
0
W
1
1
1
0
0
1
L
H
A3
A2
AI
AO
ADDRESS INPUTS
3628A
INSTALL SHORTING PLUG AT JUMPER J20.
W
0
0
1
0
1
0
L
H
0
0
0
0
W
0
1
1
0
16 BIT DATA BUS
L
H
1
0
NO SHORTING PLUG
== SHORTING PLUG INSTALLED
L
H
0
1
'" DISABLE
L
H
W
1
" ENABLE
L
H
1
0
0
1
0
5XXX
L
H
L == LOW BYTE
H "" HIGH BYTE
0
7
0
0
6
5
0
4
0
0
0
3
2
1
JUMPERS
PROMS
1·4
5·8
0
0
OUTPUTS
5·66
AFlW2DB7A
inter
APPLICATION
NOTE
Ap·148
November 1982
ORDER NUMBER 210699-001
©lntel Corporation 1982
5-67
i~
Ap·148
A NEW AND REVOLUTIONARY TYPE
OF MEMORY
Writing to the 2817, however, is much easier than writing
to either the 2716 EPROM or the 2816 E 2PROM. Writing
to a 2716 EPROM is accomplished by first erasing the
EPROM completely with ultraviolet light. An EPROM is
then programmed before being placed into its target
system. When writing to a 2816 E 2PROM, the chip is first
erased in circuit by applying a high voltage exponential rise
time programming pulse and placing logical I's on the
data bus. After erasure, the 2816 E 2PROM is tpen programmed with another programming pulse.
The Electrically Erasable PROM (E2 PROM) provides the
system designer with an inexpensive, non-volatile, incircuit alterable memory. The E 2PROM is superior in
reliability to electro-mechanical, non-volatile storage
media such as floppy disks. E 2PROMs can operate in environments of dust particles, vibration, and wide
temperature ranges. The E 2PROM offers additional flexibility over UV EPROMs because of in-circuit alterability.
By contrast, the 2817 is as simple as writing to a RAM:
CE = WE = LOW, OE = HIGH. All the control
signals initiating the write cycle are TTL level. Like a
RAM, the user does not have to erase the memory location before writing to it; the erase-before-write is performed automatically by on-chip intelligence. The input
addresses and data are latched by the WE input. Latches
make the 2817 E 2PROM appear RAM-like to the user
even though the programming time for an E 2PROM cell
is inherently slower than a RAM cell. The oil-chip timer
generates the internal programming pulse using the external timing capacitor. The' ROY /BUSV output goes
low to indicate that a write operation is in progress. The
system CPU can then contil;J.ue its normal processing
work until the 2817's ROY /'iiUSY output goes back
high, at which time another byte write or read operation
can be initiated.
Urilike the previous 2816 E2PROM, the 2817 E 2PROM has
on~hip address/data latches, auto erase-before-write, and
READY/BUSY (ROY/BUSy) output intelligence. These
powerful features, discussed later in more detail, are provided to the user through a high level of on-chip integration.
, Applicatioris which'include remote firmware updating,
user-defined functions, calibration constants, configuration parameters, and data logging are easily impleme~ted with'the 2817.
For example, in the field of data communications, 2817
E 2PROMs are used to store table lookup data that configure the protocol for a given I/O channel. Because the
data is stored in E 2PROM, the user can quickly reconfigure the I/O channel to a different protocol via an end
system keyboard. The 2817 E 2PROMs provide user
flexibility as well as user friendly implementation.
Transmission errors and service information can also be
logged into the E 2PROM.
SIMPLE INTERFACE REQUIREMENTS
The 2817 does not need the external timing and complex
digital switching logic that is required for interfacing the
2816 to a micropr~or bus. From an external circuitry
standpoint, all that is needed is a static Vpp 21 V supply
and a write protection circuit. The 2817 requires a static
21V for both read cycles and write operations. It will be
possible to read the 2817 with either 5V or 21V on Vpp) on
parts shipped after January 1983. The write protection circuit is needed to prevent data loss during Vcc power transitions. The TTL SSI devices that are normally used in
systems to drive the CE and WE inputs are typically
unstable when Vcc is below 4 volts. These TTL drivers
could cause a spurious write operation to occur when Vcc
is below normal operating level, and a data byte would be
lost (see Figure 1). To prevent data loss under such conditions, the WE input should be maintained at VIH (or equal
to Vcd during Vcc power transitions (see Figure 2).
In navigation or ;adar systems, program code is often
changed to store new flight information. Prior to
E 2PROMs, the EPROM boards containing the code had
to be physically removed to be reprogrammed. With the
2817 E 2PROM, reprogramming is easily accomplished
because of the in-circuit alterability of E 2PROMs.
The realm of potential applications is limited only by the
user's imagination. The 2817 E2PROM is already used in an
extensive spectrum of applications. FPROMs are used not
only to replace other non-volatile storage mediums in current
applications but also to make possible new applications.
DESIGNING IN THE 2817
The 2817 E2PROM is easy to use. Reading is accomplished in the same manner as with the 2716 EPROM:
CE = OE = LOW, and,WE = High. The read access time
of 250ns makes the 2817 compatible with even high performance microprocessQrS (such as 8086-2) for zero wait state
operation.
5-68
AP·148
A WRITE PROTECTION CIRCUIT
EXAMPLE
When Vee is below 4.5V the zener is not have sufficient
voltage across it to remain on. When the zener is not
conducting, QI is off. Q2 is then turned on, bringing the
base of Q3 low. Q3 is turned off which causes the WE
input of the 2817 to be pulled to Vee. In this condition
the system WE signal will not be able to affect the WE
input of the 2817. When Vee is above 4.5V, QI is on,
Q2 is off, and Q3 acts as an inverter, permitting the
system WE signal to pass through.
A circuit satisfying the condition of WE at VIH (or Vcd
to prevent a spurious write operation is shown in Figure
3. The components used are all readily available, inexpensive, and occupy little board space. This circuit has
been tested extensively at 25 cC.
The circuit operates by monitoring system Vee and using it to qualify the system WE output signal. The zener
diode determines when transistor QI turns on and off.
/
POWER UP
_ _- - - 5 V
Vee
ov
WE
OV
I
~
POWER DOWN
5V
Vee
I
~
-----OV
V,H
WE
----OV
Figure 1. Typical TTL Driver Instability during Vee Power Transitions
POWER UP
~_---5V
Vee
OV
~_---V'H
WE
OV
POWER DOWN
5V
Vee
-----OV
V,H
WE
-----ov
Figure 2. Controlled WE during Vee Power Transitions
5-69
intJ
Ap·148
sv
~~
~?"-
--430a
1Ka
1200
1N,':~A
2H3904
5% 'TOLERANCE
03
1N914
2N2222A
02
2N2222A
100a
033,,1
~O1
1N914
-=-
...
-=-
;.
E
V
NOTE TOLERANCES.
RESISTORS 5%
CAPACITORS 10%
Figure 3. 2817 Write Protection Circuit
ADVANTAGE OF STATIC 21V
LARGE ARRAYS
With the 2817 the system designer can leave Vpp on during
normal operation rather than switch Vpp on and off. The
2817 on-chip intelligence automatically generates and
shapes the programming pulses internally from the external 21 V static supply. The 2816 requires external logic to
produce a switching Vpp signal to accomplish the same
task. If the 2817's Vpp had to be switched on for write
cycles there would be some delay involved in bringing Vpp
up to 21V. There would also be noise coupled into the surrounding TTL circuitry resulting from the fast switching
of a high voltage.
An array of 8 2817's will require only 71mA (l5mA for
one device in write mode, 56mA for 7 devices in standby
or read mode).
The TL497A based circuit discussed above can be used. It
will output 21V or 24V. There are also numerous 5V to
24 V converters available at this current rating and higher.
To provide a regulated 21 V output from these converters
an LM317 voltage regulator can be used as shown in
Figure 4.
Since it is generally a good practice to decouple any
power supply, it is recommended that Vpp (Pin I) be
decoupled with a 0.1 microfarad capacitor.
r----,
110VACI
i
21V Is Easy To Obtain
24V
I
S~~~y j-+I
L ___ ..J
:
r----,
OR
The 21 V for Vpp can come from a number of sources. A
separate AC input 21V supply could be used. A less expensive alternative for a small array of 2817's is a DC to
DC converter. Modular 5V to 21V (or 24V) converters
are available from various power supply vendors that
can provide anywhere from 30mA to 200mA. (See Appendix A) An example would be the ELPAC/TDK
CE-0299: It costs from $6 to $14, can supply 3 2817's (I
device in write mode = 15mA, 2 devices in read or
standby mode = 16mA), and fits into a 24 dip socket.
(If a 28 pin socket is used instead of a 24 pin socket, the
former could be used as an additional memory socket
when the circuit is upgraded to the 5V-only 2817A.)
I
~ D~~~C I- I CONVERTER I
svoc'
5VTQ
I
I
OR
I
l
12VTO
I
r
I
t- -...l
-+I o~~~c
I CONVERTER I
1
L_;,;_..J
I
r----,I
I
LM317
+r--1
L ___ ..J
r----,
12VDC
I
I
I
I
I
TL497
360KU
:!:1%
200n
:5%
~ s:~~~t~~G t- _ ..I
IL CIRCOIT
___ ..JI
ALTERNATIVES
,
Note: All resistors are 1/4 Watt.
The TL497 A-based circuit shown in the 2817 data sheet
costs about $4 in large quantities. It can provide enough
current for 8 devices.
Figure 4. Voltage Regulator For Supplying Vpp
In Large Arrays
5·70
AFN02231A
inter
AP·148
CONNECTING THE ROY/BUSY OUTPUT
TO THE SYSTEM
The 2817's on-chip intelligence controls the programming cycle and provides a system feedback signal. When
the address and data are latched into the 2817 by the
WE input pulse, the ROY/BUSY output goes low indicating that a write operation is in progress. After a
predetermined amount of time has elapsed to insure successful programming, the ROY /BUSY output returns
high to indicate the write operation is complete.
21171
IOI't
=~
.2I17A
'RDyliUfil---l>Co-,--,.-~ .KYO
"!'110M
Note: For MCSC 48 Family,
Input to ",C is INT pin..
The system CPU can deal with the 2817 ROY/BUSY
output in one of two ways: the output can be used as an
interrupt to the CPU, or it can be polled.
F!lUre7-. ~.I)r.I¥eD . . . . . .I'OI..r
'yslem
If the CPU is not needed for system functions while the
E2PROM write cycles are in progress, then polled mode
would be acceptable since it usually requires less software and/or hardware than interrupt mode. Otherwise,
an interrupt-driven mode should be used.
110 PORT
28171
2817A
DATA IUS
ADvliiiiYl----t"l
CPU
Figures 5, 6, and 7 show how the ROY/BUSY output
could be used as an interrupt in 8088, 808SA, or
805 I-based systems, respectively. Figures 8 and 9 show
hardware diagrams for polled mode operation.
uo
DECOOER
ADDRESS BUS
Note: 1/0 Port latch is set on the rising edglil of ROY/BUSY.
28171
2817A
ADY/iUSY
...
....
8251A
••
-
INTERRUPT
rPROM
Figure 8. Polled Mode, General
INTA
....
'"
CONTROLLER
....
28171
2817A
Figure 5. Interrupt· Driven 8088 System
RDY/iUsi
....
....
TEST
IUSE WAIT INSTAUcnON)
Figure 9. Polled Mode For 8088 System
28171
2817A
ADY/BUSY
-.
Polled mode with the 8088 can be done easily and effectively with minimal software and hardware as shown in
Figure 9. To write to the 2817, simply do the following:
AST7&
RST
rPAOM
......
'"
MOV
MOV
WAIT
Figure 8. Interrupt· Driven 808SA System
5-71
AL, DATA BYTE ;LOAD AL REG WITH DATA
E2~ROM, AL
;WRITE IT TO E2
;WAIT UNTIL WRITE OPERATION
;ISOONE
AP·148
The 8088 will remain in a wait state while the test input
is high (ROY /BUSY is low). When the test input returns
low, program execution will continue with the next instruction following 'WAIT'.
The following two steps describe how a data block can be
transferred from RAM to E2PROM in an interrupt-driven
system. The operation is initiated by two actions: (I) a
software pointer is loaded indicating the target E2PROM
data block (2) a system memory write cycle is initiated to
the first address of the E2PROM datil block. Normal processing then continues while an interrupt subroutine such
as the one shown in Figure 10 does the rest.
LOAD POINTER
NO
As each E2PROM write operation is completed, the interrupt subroutine is called up via the ROY/BUSY output to write the next byte. When the data block has been
completely transferred to E2PROM, a software busy
flag is cleared to indicate the status to the CPU.
INITIATE
WRITE OF
NEX,T BYTE
CLEARE2
BLOCK TRANSFER
BUSY FLAG
FUTURE UPGRADABILITY TO THE
5V·ONLY 2817A
A powerful set of intelligence is currently integrated onto the 2817. In the future, the circuitry to generate the
programming voltage from a 5 volt supply will be integrated on-chip with the 2817A. Figure II a) and b)
shows how to design in a jumper and a resistor location
'for a 2817 PC board layout so that the 5V-only 2817A
, can be easily installed in the future. Table I shows the
pinout differences between the two devices.
IIICROPROCESSOR EXECUTES
OTHER TASKS
Figure 10. Interrupt Subroutine Servicing Blocks
Transfer To 2817
The 2817 A has a write protection circuit on-chip so that
the external circuit in Figure 3 is not required. This circuit can remain on board and be used with the 2817A if
desired.
Table 1.
Differences in Pinout of 2817 and 2817A
The ROY/BUSY pin of the 2817A is an open drain output. The design enables the user to tie the ROY/BUSY
line from 2 or more 2817A's together. If two 2817A's
are tied together, the ROY/BUSY line will not go back'
high until both 2817A's are successfully programmed.
This is ideal in 16 bit bus architectures. The 7.5K
resistor shown is a minimum value for 1 TTL'load, since
the total sink current should 1;10t exceed the device
rating: 2.lmA @ VOL = O.4V.
PINS
Device
1
2
26
2817
2817A
VPP
ROY/BUSY
RDY/BUSv
NC
TIMING CAP
NC
The resistor value can be calculated as follows:
R(pULLUP) = _ _
4._6V
__
2.1 MA - IlL
Where IlL = The total VIL input current of all devices
connected to ROY/BUSY.
5-72
AFN02231A
intJ
AP·148
.5V
~,,
RPlILLUP
75KO
21Y
RP\llLUP
75KIl
~
V..
,
RDV
f,
--+---I
v....
SUPPLY
"
W1l ...
TO UPGRADE FADM 2817 TO 2817A
1 REMOVE TC, 21V, W2
'"
2 INSTALL W1, RPULLUP
TO UPGRADE FROM ,.t7A TO 2865
, INSTALL W3
RDY/iUsV
(1nLLOAD)
TO UPGRADE FROM
2817 TO 2I17A
Figure 11B. Upgrade Layout For 2817/2817A12865
1 REMOVE TC, 21Y SUPPLY.
2 INSTALL RPULLUP AND PUT
JUMPER ON W1
Figure 11A. Upgrade Layout For 281712817A
THIS IS A FEW OF THE MANY 5V TO 21V (OR 24V) CONVERTERS THAT ARE AVAILABLE.
DESCRIPTION
ELPAC/TDK CE·0299
DATEL UPM·24/40-D5
RELIABILITY, INC. VA12·12
INTRONICS OCR 5/12·12
.
VOUT
21V
24V
23V
24V
lOUT
35 MA
40 MA
40 MA
80 MA
EST. COST (1)
SIZE
$ 6 (14)
$29 (46)
$17 (24)
$36 (40)
24 PIN DIP
2.5 sa IN
24 PIN DIP
24 PIN DIP
NOTES: 1. The numbers in the 'cost' column Indicated both large and small quantities as follows: Large Qty's
(small qty's).
'
VENDOR INFORMATION
PHONE NUMBER
VENDOR
'ADDRESS
ELPAC/TDK POWER SYSTEM
3131 S. STANDARD AVE.
SANTA ANA, CA 92705
(714) 979-4440
DATEUINTE~SIL
11 CABOT BLVD.
MANSFIELD, MA. 02048
(617) 339-9341
(617) 828-8000
RELIABILITY, INC. OF TEXAS
P.O. BOX 218370
HOUSTON, TEXAS 77218
(~13)
INTRONICS
NEWTON, MASS.
(617) 964·4000
,
5·73
492·0550
ARTICLE
REPRINT
AR·119
March 1980
Reprinted from ELECTRONICS, February 28, 1980; Copyright © McGraw·HIII, Inc" 1980. All rights re~erved.
5-74
AFN-01913A
AR-119
16-K EE-PROM relies on tunneling
for byte-erasable program storag,e
Thin oxide is key to floating-gate tunnel-oxide (Flotox) process
used in 2,048-:-by-8-bit replacement for UV-light-erasable 2716 E-PROM
by W. S. Johnson, G. L. Kuhn, A. L. Renninger, and G. Perlegos,
o The
erasable programmable read-only memory, or
is the workhorse program memory for microprocessor-based systems. It is able to retain data
for years, and it can be reprogrammed, but to clear out
its contents for new data, ultraviolet light must be made
to stream through its quartz window. This works well for
many applications, but the technique foregoes singlebyte-in favor of bulk-erasure and in-circuit selfmodification schemes.
Electrical erasability is clearly the next step for such
memories, but like ultraviolet erasure a few years back,
it is hard to achieve. In fact, the design of an electrically
erasable read-only memory is paradoxical. In each cell,
charge must somehow be injected into a storage node in
a matter of milliseconds. Once trapped, however, this
charge may have to stay put for years while still allowing
the cell to be read millions of times. Although these
criteria are easily met individually, the combination
makes for a design with conflicting requirements.
These demands are more than met in a new EE.PROM,
which is a fully static, 2-K-by-8-bit, byte- or
E·PROM,
IntelCorp. Santa Clara. Calif
chip-erasable nonvolatile memory. At 16,384 bits, this
new design not only meets the goal of high density, but
also has long-term retention, high performance, and no
refreshing requirement, in addition to functional
simplicity unmatched by present nonvolatile memories.
The device need not be removed from a board for
alterations, and performance is consistent with the latest
generation of 16-bit microprocessors such as the 8086.
This achievement required the development of a new
nonvolatile process technology, HMOS·E, as well as a new
cell structure, Flotox, for floating-gate tunnel oxide.
Conflicting requir.~.nts
Nonvolatile semiconductor memories generally store
information in the form of electron charge. At cell sizes
achievable today, this charge is represented by a few
million electrons. To store that many electrons in a
IO-millisecond program cyclj'l requires an average
current on the order of 10. 10 amperes. On the other hand,
if it is essential that less than 10% of this charge leaks
away in 10 years, then a leakage current on the order of
Electronics/February 28, 1980
5·75
AFN-ol913A
AR-119
The next memory. The 16-K electrically
erasable programmable read-only memory is
eminently suitable for microprocessor
program storage. Organized as 2,0413 by 8
bits, the EE-PROM allows full-chip or
individual-byte erasure using the same
supply (V po) as for programming.
,ECOND LEVEL
POLYSILICON
GATE OXIDE
p SUBSTRATE
I. I
SECOND·LEVEL
PO LYSILICON
fl RST LEVEL
POLYSILICDN
IfLDATING)
GATE OXIDE
p SUBSTRATE
Ibl
1. Firat Famo8, now Flotox. The Famos cell (a) found in all
E-PROMs stores charge on the floating gate by avalanche means
Flotox cell (b), the heart of the EE-PROM, relies on electron tunneling
through thin oxide to charge and discharge the floating gate.
10.21 A or less must be guaranteed during read or storage
operations. The ratio of these currents, I : 10", represents
a difficult design problem. Few charge-injecting
mechanisms are known that can be turned off reliably
during nonprogram periods for such a ratio.
One structure that has proven capable of meeting such
stringent reliability requirements has done so for many
millions of. devices over the last nine years. This is the
floating-gate avalanche-injection MOS (Famos) device
used in the 1702,2708, 2716, and 2732 E-PROM families,
In the Famos structure, shown in Fig. la, a polysilicon
gate is completely surrounded by silicon dioxide, one of
the best insulators around. This ensures the low leakage
and long-term data retention.
To charge the floating gate, electrons in the
underlying MOS device are excited by high electric fields
in the channel, enabling them to jump the
silicon/silicon-dioxide energy barrier between the
substrate and the thin gate dielectric. Once they
penetrate the gate oxide, the electrons flow easily toward
the floating gate as it was previously capacitively
coupled with a positive bias to attract them.
Because of Famos' proven reliability, the floating-gate
approach was favored for the EE-PROM. The problem, of
course, was to find a way to discharge the floating gate
electrically. In an E-PROM, this discharge is effected by
exposing the device to ultraviolet light. Electrons absorb
photons from the uv radiation and gain enough energy
to jump the silicon/silicon-dioxide energy barrier in the
reverse direction as they return to the substrate. This
suffices for off-board program rewriting, but the object
of the EE·PROM is to satisfy new applications that
demand numerous alterations of the stored data without
removing the memory from its system environment.
What evolved was the new cell structure called Flotox
(Fig, I b),
In the quest for electrical erasability, many methods
were considered, and several potc;ntially viable solutions
were pursued experimentally. One initially attractive
Electronics/February 28. 1980
5-76
AFN-01913A
AR·119
(-)
FOWLER·NOROHEIM
TUNNELING CURRENT
1 DECADE
0'i'V
(+)
POLYSILICON
GATE
SILICON
SUBSTRATE
2. Tunneling. For a thin enough oxide. as shown here. under a field
strength of 10' V/cm, Fowler-Nordheim tunneling predicts that a
certain number of electrons will acquire enough energy to Jump the
forbidden gap and make it from the gate to the substrate.
3. Current characleri.tic. In Fowler-Nordheim tunneling, current
flow depends strongly on voltage across the oXide. riSing an order of
magnitude for every 0 8 V Charge retention is adequate so long as
the difference between programming and reading IS at least 8 8 V
approach attempts to harness a parasitic charge-loss
mechanism discovered in the earliest E-PROMs, Referring
again to Fig. I a, the polysilicon grains on the top surface
of the floating gate tend, under certain processing
conditions, to form sharp points called asperities. The
sharpness of the asperities creates a very high local
electric field between the polysilicon layers; shoving
electrons from the floating gate toward the second level
of polysilicon. This effect is purposely subdued in today's
E-PROMS by controlling oxide growth on top of the
floating gate because this parasitic electron-injection
mechanism would otherwise interfere with proper
E-PROM programming.
It was first thought that asperity injection could be
used to erase the chip. In fact, fully functional,
electrically erasable test devices were produced; but the
phenomenon proved unreproducible and the devices
tended to wear out quickly after repeated program and
erase cycling, After over a year's effort, that approach
was abandoned.
flow freely toward the positive electrode.
This posed two fundamental problems. First, it was
commonly believed that silicon dioxide breaks down
catastrophically at about 10' v/cm, and MOS FETs are
normally 'operated at field strengths 10 times below this.
Second, to induce Fowler-Nordheim tunneling at
reasonable voltages (20 v), the oxide must be less than
200 angstroms thick. Oxide thickness below about
500 A had rarely even been attempted experimentally,
and it was feared that defect densities might prove
prohibitively high.
To be weighed against these risks, however, were
several advantages. Tunneling in general is a low-energy,
efficient process that eliminates power dissipation.
Fowler-Nordheim tunneling in particular is bilateral and
can be used for charging the gate as well as discharging
it. Finally, the tunnel oxide area could be made very
small, which is of course consistent with the needs of
high-density processing.
With these motivating factors, development was'
initiated to grow reliable, low-defect oxides less than 200
A thick. The success of this effort resulted in the
realization of a working cell structure called Flotox.
The Flotox device cross section is pictured in Fig. lb.
It resembles the Famos structure except for the
additional tunnel-oxide region over. the drain. With a
voltage V. applied to the top gate 'and with the drain
voltage Vd at 0 v, the floating gate is capacitively
coupled 'to a positive potential. Electrons are attracted
through the tunnel oxide to charge the floating gate. On
the other hand, applying a positive potential to the drain
and grounding the gate reverses the process to discharge
the f10atjng gate.
Flotox, then, provides a simple, reproducible means
for both programming and erasing a·memory cell. But
Tunneling solution
The solution turned out to be the one that initially
seemed impossible. After investigating many methods of
producing energetic electrons, it was decided to
approach the problem from a different direction: to pass
low-energy electrons through the oxide. This could be
accomplished through Fowler-Nordheim tunneling, a
well-known mechanism, depicted by the band diagram in
Fig. 2. Basically, when the electric field applied across
an insulator exceeds approximately 10' volts per
centimeter, electrons from the negative electrode (the
polysilicon in Fig, 2) can pass a short distance through
the forbidden gap of the insulator and enter the
conduction band. Upon their arrival there, the electrons
Electronics/February 28, 1980
5·77
AFN·01913A
This value, including margins for processing
variations, is reasonable. Furthermore, data is not
disrupted during reading or storage so that rio refreshing
is required under normal operating or storage conditions.
Extensive experimental testing has verified that data
retention exceeding 10 years at a temperature of 125"C
is possible.
'
Another important consideration is the behavior of the
electrically erasable memory cell under repeated
program erase cycling. This is commonly referred to as
endurance. The threshold voltage of a typical Flotox cell,
in both the charged and discharged states, is shown in
Fig. 4 as a function of the number of programming or
erasing cycles. There is some variation in the threshold
voltages with repeated cycling but this remains within
tolerable limits -out to very high numbers of cyclessomewhere between 10' and 10· cycles.
4. Good endurance. The endurance of the EE-PROM, depends on
the threshold-voltage difference, between the charged and
discharged states, Though repeated cycling degrades thresholds, the
chip should stay within tolerable limits for 10' to 10' cycles,
Putting Flotox to work
The Flotox cell is assembled into a memory array
using two transistors per cell as shown in Fig. 5. The
Flotox device is the actual storage device, whereas the
upper device, called the select transistor, serves two
what about charge retention and refresh considerations purposes. First, when discharged, the Flotox device
with such a thin oxide? The key to avoiding such exhibits a negative threshold. Without the select
problems is given in Fig. 3, which shows the exceedingly transistor, this could -result in sneak paths for current
strong dependence of the tunnel current on the voltage flow through nonselected memory cells. Secondly, the
across the oxide. This is characteristic of select transistor prevents Flotox devices on nonselected
Fowler-Nordheim tunneling.
rows from discharging when a column is raised high.
The array must be cleared before information is
The current in Fig. 3 rises one order of magnitude for
every 0.8-Y change in applied voltage. If the 11 orders of entered. This returns all cells to a charged state as shown
magnitude requirement is recalled, it is apparent that the schematically in Fig, Sa. To clear the memory all the
difference between the voltage across the tunnel oxide select lines and program lines are raised to 20 Y while all
during programming and that during read or storage the columns are grounded. This forces electrons through
the tunnel oxide to charge the floating gates on all of the
operations must be in excess of 8.8 Y.
COLUMN 2
COLUMN 1
COLUMN 2
OV
(3)
(b)
5. Working. To clear a Flotox cell, select and program lines are raised to 20 V and columns are grounded (a)- To write a byte of data, the
program line is grounded and the columns of the selected byte are raised or Iqwered according to the data pattern (b),
Electronics/February 28, 1980
5-78
AFN-01913A
AR-119
ADORES~ESJ
CHIP
_
ENABLE, CE
>C
VALID
ADDRESSE~
(
DATA IN
DATA OUT
I
\
OUTPUT _
ENABLE, DE
•
~~~~
>-
DATA VALID
r
~R:A~~T=EH%W,ALL
j~10ms~
Vpp
VALID
I
\
CE
I
\
>C
»1(bl
AOORES~
selected rows. An advantage of this EE·PROM over
is the availability of both byte- and chip-clear
operations. The byte-clear one is particularly useful for a
memory of this size. When it is initiated, only the select
and program lines of an addressed byte rise to 20 v.
To write a byte of data, the select line for the
addressed byte is raised to 20 v while the program line is
grounded as shown in Fig. 5b. Simultaneously, the
columns of the selected byte are raised or lowered
according to the incoming data pattern. The bit on the
left in Fig. 5b, for example, has its column at a high
voltage, causing the cell to discharge, whereas the bit on
the right has its column at ground so its cell will
experience no change. Reading is accomplished by
applying a positive bias to the select and program lines of
the current. A cell with a charged gate will remain off in
this condition but a discharged cell will be turned on.
VALID
E·PROMS
From the outside
I n terms of its pinout and control functions, the
has evolved from the 2716 E-PROM. Both are
housed in 24-pin dual in-line packages, for instance, and
both offer a power-down standby mode. In addition, both
utilize the same powerful two-line control architecture
for optimal compatibility with high-performance
microprocessor systems. Referring to Fig. 6a, it is seen
that both control lines, chip enable (CE) and output
enable (OE), are taken low to initiate a read operation.
The purpose of chip enable is to bring the memory out 'of
standby to prepare it for addressing and sensing. Until
the output-enable pin is brought low, however, the
outputs remain in the high-impedance state to avoid
system bus contention. In its read mode, the EE·PROM is
functionally identical to the 2716.
A single + 5-v supply is all that is needed for carrying
out a read. For the clear and write functions, an
additional supply (V pp) of 20 v is necessary. The timing
for writing a byte is shown in Fig. 6b. The chip is
powered up by bringing CE low. With address and data
applied, the write operation is initiated with a single
10-ms, 20-v pulse applied to the Vpp pin. During the
EE·PROM
CE
\
>C
--JI
L
_____
"'j \
----~lOms~\.--lei
8. Timing. The Flotox memory's operating modes are shown for
reading (a), writing 'or clearing of bytes (b), and chip clearing (c).
Both writing and erasing require a 10-ms program-voltage puisEO', The
read mode is fun'ctionally identical to that of a 2716 E-PROM.
.write operation, OE is not needed and is held high.
A byte clear is really no more than a write operation.
As indicated in Fig. 6b, a byte is cleared merely by being
written with all 1s (high). Thus altering a byte requires
nothing more than two writes to the addressed byte, first
with the data set to all I s and then with the desired data.
This alteration of a single byte takes only 20 ms. In other
nonvolatile memories, changing a single byte requires
that the entire contents be read out into an auxiliary
memory. Then the entire memory is rewritten. This
process not only requires auxiliary memory; for a
2-kilobyte device it takes about one thousand times as
long (20 ms vs 20 seconds).
Chip clear timing is shown in Fig. 6c. The only
.difference between byte clear and chip clear is that OE is
raised to 20 v during chip clear. The entire 2 kilobytes
are cleared with a single 10-!lls pulse. Addresses and
data are not all involved in a chip-clear operation.
0
Electronic8/February 28. 1980
5-79
AFN-D1913A
ARTICLE
REPRINT
AR-174
June 1981
Reprinted from ELECTRONICS, May 19, 1981 COPYflght 1981, McGraw-HIli Incorporated All fights reserved
- 5-80
AFN-01961A
AR·174
EE-PROM goes to work
updating remote software
Analog signals transmitted over telephone-line data links
alter on-site memory for microsystem upgrading and maintenance
by Randy Battat and John F. Rizzo,
o
Intel Corp.• Sants Clsra. CaHI.
tions so it can be written into from many information
sources. But because it is an excellent medium for storing nonvolatile. programs and data, it is particularly
suited to downline loading-in. this case, in changing
memory contents at remote sites via a data link.
The telephone is ideal for transferring information,
Microprocessor system software needs frequent revision, which is inconvenient, difficult, and costly. But
because it combines the nonvolatility of ROM and the
ftexibility of random-access memory, an electrically
erasable programmable read-only memory at the microprocessor site allows remote software changes to be
made through a telephone-line data link, eliminating
field service expenses.
As technology progresses, design and service costs are
coming to determine-more than component costs-the
cost of microprocessor systems (see "The cost of software service"). Intel's 2816 BE-PROM not only solves the
service problems, but it also makes existing designs more
functional since they need only be updated, not replaced.
The cost of software service
Servicing a software change In a field application today
averages about $100 per hour. By 1985, assuming an
inflation rate of 15%, these costs will approach
$200/h. A typical microprocessor system (2,000 in the
field) requires a service time of 2 h. If each system
needs to be updated a minimum of two times during
)he product'S life, the cost is at Jeast $400 per system.
That means $800,000 for the total retrofit. If a doubling
of the cost of labor in the next five years is assumed,
the new retrOfitting cost comes to $1.6 million.
.
By installing a remote-software serial link, software
can be updated over telephone lines. Adding a 2816
EE-PROM and a remote link to the system will cost about
$50, a mere one sixteenth the 1985 service cost.
TOday, as seen In the figure. a 40% savings can result.
Memory requirement.
In a remotely controlled EE.PROM, the memory must
be nonvolatile, retaining data even when the host system
is powered down. Fllrthermore, with today's high-speed
microprocessor systems such .as the Intel 8086-2, the
Zilog ZSOOO, and the Motorola MC68000, only fast
memory devices can achieve full throughput. For example, a high-performance 8086-2 system with a zero time
wait-state operation requires a memory-read access time
of 250 nanoseconds.
Also, as software costs rise, high-level languages will
often be used to reduce design time. These languages are
memory-intensive, requiring high-density memory chips
to effectively contain dedicated system programs without
.
sacrificing printed-circuit board space.
Finally, a remote link-addressable EE-PROM must have
read-mostly operation. Normally program memory and
certain types of data memory are accessed in a read
mode. At times, however, it is necessary to reload an
entire program (as in the case of a software revision) or
to reconfigure portions of data storage (when on~ certain parameters need to be changed). Then the ability to
write into the memory in the circuit is 'essential.
The 2816 fills all these user requirements. It is nonvolatile, having greater than 20-year data retention. Its
access time of 250 ns is compatible'with today's highspeed microcomputer systems. The chip is also electrically erasable on a per~byte or per-chip basis-a true
read-mostly memory. It offers users 16,384 bits of storage organized as 2048 8-bit bytes.
The EE-PROM allows in-circuit erase and write, opera-
5-81
AFN-G1961A
AR-174
lal
RS·232
CONNfCTOR
JI085
SERIAL IN
DATA,
----01
8085
SERIAL OUT
DATA
RECEIVE
DATA
TRANSMIT
DATA
,Ibl
1. bay downkNldlng. A microprocessor at a ramote site with an
EE-PROM as a peripheral may have Its software ohBnged by maans of
a telephona data Hnk (a). An acoustlcaOy coupled modem is required
with an interlace (b) that Is simple to Implement.
since it is readily available ~ requil'!lS no speclal interface. Using an acoustic coqpler, ,serilit binary 'data is
converted into high- and IOw:tiequency to1'Ies 'that are
then transmitted over a worldWide link. Modems interface easily with lI1i~; ,anG, 'in atklition, the
software overhead fOr SlIGIi:-a:dowtilfne;.foad!rig oPetation
isminimal. .
.,
...x......... "'.......
Progr~ms doWnl~~l~ ~io BE-P~S find ~y
applications in ioiffla.·~_11 rriloi'btOinpatet 's:;s- ,
, terns. But fllgll:rdiess Of size, "H configtiriitions reqnirti a
modem to interface' cIectrieal 'ipals from a host pr technology. The 2815's E'I functionality
enables in-circuit reprogram mabie memory flexibility, while maintaining the non-volatility of the data stored.
The Intel 2815 is erased and written in-circuit. Byte and chip erasure are accomplished with a single 50 mS
pulse after which data can be written a byte at a time. Because of its unique architecture, selection of the chip to
be erased or written is performed with the same address control circuitry as that used for read operations.
Read operations with the 2815 are performed at standard 5VTTL levels. The 250 ns access time is fast enough
so that the 2815 can be interfaced to processor system busses with no wait states. The microprocessor to 2815
interface is achieved with a minimum of external circuitry.
The 2815 was designed in accordance with Intel's byte-wide pinout philosophy and therefore conforms to the
JEDEC approved byte-wide family standard. The two-line control architecture of this standard ensures elimination of bus contention in high-speed microprocessor systems. The 2815 is pin-for-pin compatible with the Intel
2816 ~PROM and it is therefore directly upgradable for those systems requiring faster write times in the future.
Application of the 2815 for program storage, error logging, or prototyping memory maximizes the user
potential to reduce service costs. As a program storage medium, users are able to update firmware remotely,
saving the costs of increased parts inventories and more frequent service calls. Revision levels, service call
logs, and system configuration parameters can also be stored non-volatilely, so that they can be easily accessed
or updated on a service call. The 2815 is also an excellent alternative to CMOS RAMs and batteries in systems
requiring non-volatile parameter storage. The 2815's many features, wide temperature range, extremely reliable
operation, and design-in ease combine to give you a powerful tool for adding dramatically increased
functionality to your systems.
'HMos-e is a patented process of Intel Corporation.
DATA INPUTs/OUTPUTS
'01°0.1,1°7
PIN NAMES
A2
6
A,[ ,
Aor
~1&
19
E"'PROM
18
Al0
a
8
10100 [ ,
ADDRESs
A'-·"l
INPUTS
"IO,l
10
12/02l
11
GNof L
12-_ _
AO·A,0
ADDRESSES
CE
CHIP ENABLE
Of
OUTPUT ENABlE
000,
DATA OUTPUTS
10'17
DATA INPUTS
V,,
PROGRAM VOLTAGE
~
2815 Functional Block Diagram
Pin
Conflgur~tion
Intel Corporatron Assumes No Responslbilty for the Uae of Any CirCUitry Other Than Circuitry Embodied In an Intel Product No Other Circuit Patent Licenses are Implied
©INTEL CORPORATION. 1982
'5-90
oc:~~
inter
2815
DEVICE OPERATION
>-___...--______... TO
The 2815 has 6 modes of operation, listed in Table 1.
All operational modes are designed to provide maximum microprocessor compatibility and system consistancy. The device pinout is a part of Intel's JEDEC
approved byte-wide Non-Volatile Memory family,
allowing appropriate and cost-effective density and
functionality upgrades.
DE
2K
10K.
CHIP
ERASE
All control input Signals are TTL compatible with the
exception of chip erase. A 9 to 15V signal is required
at pin 20 to enable the chip erase function. The Vpp
voltage must also be pulsed to 21V during chip erase,
byte erase, and byte write, and held to 4 to 6 volts
during the read and standby modes.
12K
Figure 1. OE Chip Erase Control
Table 1. Mode Selection Vcc= +5V
~
Mode
CE
(18)
OE
(20)
V pp
(21)
Inputsl
Outputs
READ
V IL
V IL
+4 to +6
DOUT
STANDBY
VIH
DON·T
CARE
+4 to +6
HIGH Z
BYTE ERASE
VIL
VIH
+21
DIN=VIH
BYTE WRITE
VIL
VIH
+21
WRITE MODE
To write a byte of data, the selected address and data
are provided at the inputs of the 2815 (all at TTL
levels). The write is then performed when the Vpp line
is raised.
The shape of the Vpp pulse is important In ensuring
long term reliability and operating characteristics.
Vpp must be raised to 21V through an RC waveform
(exponential). See figure 2a for a specific diagram of
the Vpp pulse. The TPRC specification has been designed to accommodate changes of RC due to temperature variations. Figure 2 shows a recommended
Vpp switch design, useful where programming will
occur over the specified temperature and operating
voltage conditions. The circuitry shown in this figure
will provide sufficient drive for four 2815 devices. The
circuitry in Figure 3 shows the additional circuitry
needed to provide enough drive for eight 2815
devices.
DIN
[10]
CHIP ERASE
VIL
+9 to
+15V
+21
DIN=VIH
E/W INHIBIT
VIH
DON·T
CARE
+4 to
+22V
HIGH Z
ERASE MODE
The 2815 is erased and reprogrammed electrically
rather than optically, as is required with EPROMs. By
applying a pulse to the output enable (OE) and Vpp
pin of the 2815, the chip erase function is performed
and all 2K bytes of data are returned to a logic 1 (FF)
state. The chip erase function is engaged when the
OE pin is raised above 9 volts. When OE is greater
than 9 volts and CE and Vpp are in the normal write
mode, the entire array is erased. The data input pins
must be held to a TTL high level during this time.
Figure 1 is the recommended OE control switch.
ToV pp
(30mA)
Byte erasure is accomplished by writing a pattern of
FF to the byte being addressed while the OE pin is
held at a high TTL level.
Figure 2. Vpp Switch Design-4 Devices
5-91
AFN·02025A
2815
For systems where 24V is not available as a supply
voltage. the design of a step-up regulator has been
included (Figure 4). This design provides the neces·
sary voltage and current to allow the programming of
eight 2815 devices.
}-+------Iwp-----~
V,
~
21V
-------~-~------,
A characteristic of all E2 PROMs is that the total number of erase/write cycles is not unlimited. The 2815
has been designed and manufactured to meet applications-requiring up to 104 erase/write cycles.
V,
== 6V
Figure 2a. Vpp Waveform
24V~-------,-~~----~--------------,
3.9K
+5V
10K
12K
>----+--r
Vpp
CONTROL
TO
1N914
2N3904
-'--4>---~~ V pp PIN
OF2815
47K
NOTES
1 SK IS 21V FINE ADJUST
2 RESISTOAS ARE 1/4 WATT
Figure 3. Vpp Switch Design-8 Devices
+5V
R1
i----- l
I
0.51!2W
I
:p:
I
I
I
I
I
+24V
@
7SmA
I
I
I
-
L _-___ -l
BYPASS
CAPACITORS
A1
TL497
R5
1.2K
300pF
R3
18K
C1
NOTES UNLESS SPECIFIED
1 RESISTOAS ARE Y4 WATT
2 CAPACITOR VALUES ARE}J..F
3 L 1 IS 475 rnA Inductor (J W Miller #4630)
Figure 4. Step-up Regulator Converts +5V Into +24V
5-92
AFN-02025A
2815
READ OPERATION
By applying the appropriate address to lines Ao-A1O'
8-bit data is presented at the data lines after an access delay. Assuming that the address is stable,
lowering CE will cause data to be presented a maximum of tacc later (OE is low at lacc-toE time). With all
conditions satisfied except OE, low data will be valid
a maximum of toE ns after OE is lowered.
Optimal system efficiency depends to a great extent
on a tightly coupled microprocessor/memory interface. The E2 PROM device should respond rapidly
with data to allow the highest possible CPU performance. The 2815 satisfies this high performance
requirement because of access times typically
less than 250 ns.
The 2815 uses Intel's proven 2-line control architecture for read operations. Both CE and OE must be at
logic low levels to obtain information from the device.
Figure 5 shows a typical system interconnection.
Here, the 2815 contains program information that the
8088 requires for the system function.
8088
RO
8283
LATCH
8287
BUFFER
Figure 5. iAPX 88/2815 Read Architecture
while the other devices, connected to a common
STANDBY MODE
Vpp line, are deselected by CEo
The 2815 has a standby mode which reduces active
power dissipation by 50%. The 2815 is placed J!!
standby mode by applying.aTTL high signal to the CE
input. When in the standby mode, the outputs are in
high impedance state, independent of the OE input.
OR-TIEING
Because 2815s are usually used in larger memory
arrays, Intel has provided a 2-line cont'rol architecture that accommodates the use of multiple memory
connections. The 2-line control allows removal of bus
contention from the system environment and much
easier memory system implementation.
The 2815 Erase/Write Inhibit Mode is similar to
Standby Mode. Standby power is dissipated in
this mode and the device is deselected. One
typically enters this mode during a write cycle to
an array of 2815's. One device is being written
5-93
AFN-02025A
2815
array is totally erased and new firmware containing
advanced features, software corrections, or more efficient routines are loaded into the E2PROMs from
the factory. Costly service calls to replace firmware
stored in ROMs are thereby eliminated.
To most effectively use these two control lines, it is
recommended that CE be decoded from addresses
as the primary device selection function. OE should
be. made a common connection to all devices in the
system, and connected to the RD line from the system bus. This assures that all deselected memory
devices are in their low power standby mode and that
the output pins are only active when data is desired
from a particular memory device. Timing for a system
configured in this manner is illustrated in Figure 6.
ROM Patch-Using the 2815 as branch table and
firmware patch storage medium enables the user to
store major routines in ROM, but maintain the flexibility to remotely update the code as a whole. This
capability is illustrated in Figure 7a. In Figure 7a, a
s~stem's structured firmware is shown stored in
E PROM and ROM. The branch table, stored in 2815
devices, contains a series of calls to routines stored
in ROM. These are called in sequence.
PIN COMPATIBILITY
The 2815 pinout has been designed for compatibility
with present and future memory products. The 2815
E2PROM is a member of Intel's JEDEC standard,
byte-wide memory family which allows density
upgrades, functional interchange, and extended
product life. Figure 6 shows this JEDEC 28-pin site
approach.
During the course of a product's life, faults could be
discovered in the ROM routines. By remotely changing the branch table and adding a firmware patch,
physical ROM swapping is avoided to correct the~!l
faults. This type of update (depicted in Figure 7b) is
easily implemented with the 2815. This powerful application of the 2815 can save you the costs of ordering new ROMs, distributing them to a service force,
and servicing the customer's equipment.
APPLICATIONS
The 2815 has been designed to meet those applications where write and erase speed are not critical
system parameters. Many of these applications exist
in systems where E2 is used to increase the system's
. serviceability. The 2815 is effective as a program
storage, ROM patch, error logging, diagnostics, or
signature storage medium.
Data Logging-The 2815 can be used to store randomly occurring error data. This data, which points to
hard-to-detect system faults, can be directly loaded
into the E2 PROM. A record is thereby accumulated
from which a serviceperson can spot troublesome
timing paths or failing components. Faster time to
repair and more productive preventative maintenance result.
Program Storage-The use of the 2815 for program
storage enables the periodic update of firmware via a
remote telecom link. In this application, the 28.15
5-94
AFN-02025A
inter
2815
...
~
U>
N
II)
N
'"...
:;
N
N
U>
U>
;::
;::
N
N
N
...
N
N
II)
...'"
G)
~
...
U>
N
Vpp
VCC
A12
PGM
A7
A7
A7
Vee
Vce
NC
A8
A8
As
As
Ag
Ag
As
As
Vpp
A11
Vpp
OE
OElVpp OE
OE
A10
A10
A10
A10
CE
CE
CE
CE
Vee
A7
A11
Figure 6. JEDEC 28·Pin Site Byte·Wide
Philosophy
-
ROUTINE
1
ROUTINE
2
~
ROUTINE
3
ROUTINE
4
ROM/EPROM
Figure 7a. ROM Patch Technique Using 2815
(Original Firmware Configuration)
BRANCH {
TABLE
JUMP 1
JUMP 2*
JUMP 3
JUMP 4
ROUTINE
2'
~
~~
~~
ROUTINE
1
ROVTINE
2
ROUTINE
3
ROUTINE
4
ROM/EPROM
Figure 7b. Routine 2* Replaces Routine 2 (No
Hardware Changes)
5-95
AFN-0202SA
2815
The 2815 can also store records of service and revision levels of the equipment in the end system itself.
This process would distribute the record keeping to
the user site where the records are immediately
accessible.
a production system's life so that faster diagnostics
and repair of those systems would be possible.
Signature Storage-A powerful diagnostic tool is
the use of system signatures to speed the time of
repair. When a system is first shipped a good signac
ture, one obtained by exercizing the properly functioning system's circuitry, is stored in 2815 E2 PROM.
This application is shown in Figure 8a.
System revision levels and repair records can then be
accessed remotely, before a service call is made. A
serviceperson can then be assured of carrying the
correct equipment and spares for that particular installation. The costs incurred for maoaging this system documentation are also reduced.
During the course of the equipment's life, a failure
may occur which requires .identification. A new signature is thus generated which will contain data from
the failed circuitry. A comparison of the good and
bad signatures is then sent to the factory via telephone, where the failed circuitry is identified (Figure
8b). One repair scenario is to have a serviceperson
sent, with the correct eqUipment and spares, to
quickly replace the faulty module. Another possibility
is to have the customer do his own service by swapping the faulty board.
Diagnostics-The 2815 is an excellent storage
medium for diagnostics routines used by a diagnostic processor. This processor, concurrently with a
main processor, would execute continuous machine·
diagnostics. Implemented with E2 memory and a
common interface, this diagnostic processor could
be made generic for many user systems. Routines
would be loaded into the 2815s on the diagnostic
processor to test a particular user's system. After that
user's system is debugged, the same diagnostic processor could be removed, have new routines loaded
into the 2815s, and be. inserted for the testing of
another user's system.
The power of the 2815 is especially evident for this
application when there are several revision levels or
options existing for the end equipment. This is particularly true when the users .can configure or expand
the system themselves. A common 2815 memory
module can be used to store all revisions of good
signatures. An example of this kind of situation is
depicted in Figure 8c where a user has opted for a
new RAM card. The new card is simply inserted and a
new signature stored in the same 2815 memory array.
Several cost-saving benefits result. By using the
common diagnostic processor, reduced types of test
equipment are required for service calls. Additionally, diagnostic routines would not have to be static.
New, more powerful routines could be written during
RAM
I
PROCESSOR
I
I
I
I
GOOD
SYSTEM
SIGNATURES
L_
I/O
I
I
I
SYSTEM
BOARD
1
SYSTEM
BOARD
2
SYSTEM
BOARD
3
I
I
_---1
SYSTEM BUS
II
INTERFACE
WITH
MODEM
/
~
TO FACTORY
Figure 8. System Is Operational
5-96
AFN·02025A
2815
r------,I
E'
I
I
PROCESSOR
I
I
I
GOOD
SYSTEM
SIGNATURES
FAILED
I
I
SYSTEM
SIGNATURES
I
L _
RAM
PROM
I/O
I
SYSTEM
BOARD
1
SYSTEM
BOARD
SYSTEM
BOARD
2
3
I
\\
_ -.J
SYSTEM BUS
~-
II
I
INTERFACE
I
WITH
MODEM
~
TO FACTORY (COMPARISON OF SIGNATURES INDICATING BAD COMPONENT)
Figure 8b. Component in Board 2 Fails
PROM
I
I
PROCESSOR
I
I
I
GOOD
SYSTEM
SIGNATURES"
L _
RAM
I/O
I
I
I
SYSTEM
BOARD
SYSTEM
BOARD
SYSTEM
BOARD
1
2
3
I
I
_ -.J
,
SYSTEM BUS
II
RAM'
II
INTERFACE
WIMODEM
SYSTEM
BOARD
4
TO FALORY
'SIGNATURE INCLUDING A NEW RAM BOARD
Figure 8e. Updated Good System Signature Is Stored
5-97
AFN-02025A
2815
AP-103.-Programming E2 PROM with a Single
5-Volt Power Supply
AVAILABLE LITERATURE
Much of the literature which has been written about
operation of the 2816 is equally applicable to the
2815. A brief synopsis of some applicable notes is
given below as a reference to system designers and
architects. These notes and others will be available in
the E2 PROM Family Applications Handbook II.
AP-107-Hardware and Software Download
Techniques with 2816
AP136-A Multibus-Compatible 2816 E2 PROM
Memory Board
AP138-A 2716 to 2816 Programming Socket
Adapter
AP100-Reliability Aspects of a Floating Gate
E2 PROM
To obtain this literature, contact your local Field
Sales office. Your Field Applications En~ineer is
available to discuss all aspects of the Intel E product
line with you.
AP-101-The 2816 Electrical Description
AP-1 02-2816 Microprocessor Interface
Considerations
5-98
2815
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias .............. -10'C to +80'C
Storage Temperature ................ -65'C to +100'C
All Input or Output Voltages with
Respect to Ground ................... +6V to -0.3V
Vpp Supply Voltage with Respect to
Ground During Write/Erase ......... +22.5V to -O.lV
Maximum Duration of Vpp Supply at 22V
During E/W Inhibit .......................... 24 Hrs.
Maximum Duration of Vpp Supply at 22V
During Write/Erase ........................ 70 ms[5]
'NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indIcated in the operational sectIons of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
D.C. AND A_C. OPERATING CONDITIONS DURING READ AND WRITE
2815,2815-3,2815-4
I
I
Temperature Range
0'C-70'C
VCC Power Supply[61
5V ± 5%
D.C. CHARACTERISTICS
READ
Symbol
Parameter
Typ.lll
Min.
Units
10
!"A
VIN = 5.25V
10
110
!"A
mA
OE = CE =VIL
50
mA
CE =VIH
5
mA
CE = VIL, Vpp 4 to 6
-0.1
.8
V
2.0
VCC +1
.45
V
ILO
Output Leakage Current
VCC Current Active
50
ICCl
IpP(R)
VOC Current (Standby)
25
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Vpp
Output High Voltage
ICC2
Test Conditions
Max.
III
Input Leakage Current
Vpp Current (Read)
2.4
Read Voltage
4
VOUT = 5.25V
V
IOL
V
IOH = -400!"A
6
V
=
2.1 mA
WRITE
Symbol
Parameter
Vpp
Write/Erase Voltage
VOE
Ipp(W)
OE Voltage (Chip Erase)
Min.
Typ.[11
,Max.
Units
20
21
22
V
9
15
V
Vpp Current
(Byte Write/Erase)
9
15
mA
Ipp(C)
Vpp Current (Chip Erase)
3
5
mA
IppOJ
Vpp Current Inhibit
5
mA
Test Conditions
IOE -10!"A
CE = VIL
Vpp = 22, CE = VIH
Footnotes follow timing diagrams.
CAPACITANCE[l] (TA =
Symbol
CIN
A.C. TEST CONDITIONS
25'C, f = 1 MHz)
Parameter
Input Capacitance
Typ.
Max.
Units
5
10
pF
Test
Conditions
VIN = OV
COUT
Output Capacitance
10
pf
VOUT = OV
CVcc
Vcc Capacitance
500
pF
OE = CE = VIH
CVpp
Vpp Capacitance
50
pF
OE = CE = VIH
-
5-99
-
Output Load: 1TTL gate and
C L = 100 pF
Input Pulse Levels: 0.45 to 2.4V
Timing Measurement Reference
Level: Input 1V and 2V
Output .BV and 2V
AFN-02025A
inter
2815
A.C. CHARACTERISTICS
READ
2815 Limits
Symbol
Parameter
2815·3 Limits
2815·4 Limits
Min. Typ.[11 Max. Min. Typ.[1] Max. Min. Typ.[11 Max.
Test
Units Conditions
tACC
Address to Output
Delay
200
250
300
350
400
450
ns
CE
tCE
CE to Output Delay
200
250
300
350
400
450
ns
IcE = VIL
tOE
Output Enable to
Output Delay
tOF
tOH
= OE = VIL
10
100
10
120
10
150
ns
IcE = VIL
Output Enable High
to Output Float
0
80
0
100
0
130
ns
IcE = VIL
Output Hold from
Addresses, CE or OE
Whichever Occurred
First
0
ns
'cE = OE = VIL
0
0
WRITE
Symbol
Parameter
Min.
Limits
Typ.[11
Max.
Units
Test Conditions
lAs
tcs
tOS(7)
Add to Vpp Set-Up Time
150
ns
CE to Vpp Set-Up Time
150
ns
Data to Vpp Set-Up Time
0
ns
tDH(7)
twp(5)
Data Hold Time
50
Write Pulse Width
50
tWR
Write Recovery Time
50
ns
Vpp
0
ns
Vpp
ns
70
los
Chip Erase Set-Up Time
IoH
tpRC
Chip Erase Hold Time
0
Vpp RC Time Constant
450
tpFT
Vpp Fall Time
1
teos
Byte Erase/Write Set-Up Time
0
teoH
Byte Erase/Write Hold Time
0
ns
ns
600
Vpp
= 6V
ms
= 6V
= 6V, VOE = 9V
Vpp = 6V, VOE = 9V
750
!J- S
100
!J- S
Vpp
ns
Vpp
= 6V
= 6V
Vpp = 6V
AFN-02025A
inter
2815
WAVEFORMS
READ
1,-------- - - - - ----..
ADDRESSES
ADDRESSES VALID
1'---------- -
----"'1
~--~---------"'I
- --------JJ
VALID
OUTPUT
OUTPUT----------~----------_44f<
BYTE WRITE
ADDRESSES
~
>
-
...-ICS ----.
\
4--tAS---..
IWR ....
..... tPRC[4]
V
'-
(4-6V)
105-'
~tpFT
- --
4-IDH
VALID
DATA IN
v"
-
... IWR~
twp-'j
1/\
Vpp
4-
'eos_
i-
-+
_'eOH
v"
5-101
AFN-02025A
2815
WAVEFORMS (Continued)
CHIP ERASE
CE --------------""\
vpp ____________________- - {
(4-6V}
DATA IN
----------------'1
OE ________~v~'H______--'1
NOTES:
1. This parameter IS only sampled and not 100% tested.
2. OE may be delayed up to 300 ns after falling edgeof CE without
impact on tACC for 2615. _
3. tOF is specified from OE or CE whichever occurs first.
4 The rising edge of Vpp must follow an exponential waveform.
That waveform's time constant is specified as tpRC' See
Figure 2a.
5-102
5. Adherence to TWP specification is Important to device
reliability.
6 To prevent spurious device erasure or write, VCC must be
applied simultaneously or before 21-volt application of Vpp.
Vpp cannot be driven to 21 volts without previously applying
VCC.
7. The data-in set up and hold times are Identical for byte erase
and chip erase
AFN-02025A
2816
16K (2K x 8) ELECTRICALLY ERASABLE PROM
• HMOS*-E FLOTOX Cell Design
• Reliable Floating Gate Technology
Very Fast Access Time:
• -2816,250
ns Max.
to JEDEC Byte-Wide Family
• Conforms
Standard
Microprocessor Compatible
• Architecture
Low Power Dissipation:
• -Active
Current, 11.0 mA Max.
-2816-3,350 ns Max.
-2816-4, 450 ns Max.
-Standby Current, 50 mA Max•
•. Single Byte Erase/Write Capability
Erase/Write Specifications
• Guaranteed
0-70°C
• 10 ms Byte Erase/Write Time
• Chip Erase Time of 10 ms
The Intel 2816 is a 16,384 bit electrically erasable programmable read-only memory (E 2 PROM). The 2816
can be easily erased and reprogrammed on a byte basis. A chip erase functiol1'is also provided. The device
operates from a 5-volt power supply in the read mode; writing and erasing are accomplished by providing a
Single 21-volt pulse.
The 2816, with its very fast read access speed, is compatible with high performance microprocessors such as
the 8086-2. Using the fast access speed allows zero wait operation in large system configurations.
The electrical erase/write capability of the 2816 makes it ideal for a wide variety of applications requiring insystem, non-volatile erase and write. Never before has in-system alterability been possible with this combination of density, performance and flexibility. Any byte can be erased or written in 10 ms without affecting the data in any other byte. Alternatively, the entire memory can be erased in 10 ms allowing the tQtal timeto rewrite
all2K bytes to be cut by 50%. The 2816 provides a significant increase in flexibility allowing new applications
(dynamic reconfiguration, continuous calibration) never before possible.
The 2816 E2 PROM possesses Intel's 2-line control architecture to eliminate bus contention in a system
environment. A power down mode is also featured; in the standby mode power consumption is reduced by
over 55% without increasing access time. The standby mode is achieved by applying a TTL-high signal to the
CE input.
Byte erase and write are controlled entirely by TTL signal levels, yet require no control signals beyond CE and
OE. For byte write a selected chip (CE = TTL low) senses the 21V Vpp pulse and automatically goes into write
mode. Byte erase mode is identical to byte write except that data-in must be all logic ones (TTL.high). Never
before has an in-system alteration of non-volatile information been implemented with such simple control.
-HM05-e IS a patented process of Intel Corporation
DATA INPUTSIOUTPUTS
Vcc~
GND~
101°0"7"°7
PIN NAMes
Ao.A,,!
ADDRESS
INPUTS
Figure 1. 2816 Functional Block DiaGram
Ao-A10
ADDRESSES
CE
CHIP ENAILE
OE
OUTPUT ENABLE
0".0,
DATA OUTPUTS
..·17
DATA INPUTS
V"
PROGRAM VOLTAGE
Figure 2. Pin Configuration
Intel Corporabon Assumes No ResponBIbll1ty for the Use of Any Clrcuttry Other Than Circuitry Embodied In an Intel Product No Other Circuit Patent licenses are Implied
©INTELCORPORATION,I982
5-103
OCTOBER 1982
ORDER NUMBER: 2,08CJ8.OO,
2816
DEVICE OPERATION
Read Mode
The 2816 has six modes of operation, listed in
Table 1. All operational modes are designed to provide maximum microprocessor compatibility and
system consistency. The device pinout is a part of
Intel's JEDEC approved byte wide Non-Volatile
Memory family, allowing appropriate and costeffective density and functionality upgrades.
Optimal system efficiency depends to a great extent
on a tightly coupled microprocessor/memory interface. The E2 PROM device should respond rapidly
with data to allow the highest possible CPU performance, The 2816 satisfies this high performance requirement because of access times typically less
than 250 ns.
All contr91 inputs are TTL compatible with the exception of chip erase. The Vpp voltage must be
pulsed to 21 volts during write and erase, and held to
4 to 6 volts during the other two modes.
The 2816 uses Intel's proven 2-line control architecture for read operation. Figure 3 shows the timing
disadvantages of a single-line control architecture.
2-line control, shown in Figure 4, has been developed by Intel to solve this bus contention and the associated system reliability problems. Both CE and
OE must be at logic low levels to obtain information
from the device. Chip enable (CE) is the power control pin and should be, used for device selection. The
output enable (OE) pin serves to gate internal data to
the output pins. Assuming that the address inputs
are stable, address access time (tACe) is equal to the
delay from CE to output (tCE-)' Data is available at the
outputs after a time delay of toE, assuming that CE
has been low and addresses have been stable for at
least tACC-toE'
Table 1. Mode Selection Vcc=+5V
~
CE
(18)
OE
(20)
READ
V IL
V IL
STANDBY
V IH
BYTE ERASE
V IL
V IH
+21
DIN=VIH
BYTE WRITE
V IL
VIH
+21
DIN
CHIP ERASE
V IL
+9 to
+15V
E/W INHIBIT
V ,H
MODE
(21)
INPUTS/
OUTPUTS
+4
to
+6
DOUT
+4
to
+6
HIGH Z
Vpp
DON'T
CARE
{91
+21
DIN=V'H
to
DON'T
+4
CARE-
+22V
Figure 5 shows a typical system interconnection.
Here the 2816 contains program information that the
8086 re'quires for system function.
HIGH Z
~tACC~
K
ADDRESSES
'DECODE
'\1/'
ADDRESS t
--
tDECODE
-tCE--
'\
ADDRESS 2
--,
/
/
tTURNOFF
OUTPUTS 1
DESELECTING
DATA BUS
'\V
OUTPUTS 1 ' \ /
ACTIVE
DATA 1 VALID
)(
"-
-tACC~
CE2
DATA BUS
OUTPUTS 1 X
ACTIVE
DATA 1 VALID
XOUTPUTS 2
ACTIVE
K
DATA 2 VALID
Figure 3. Single-Line Control and Bus Contention
5-104
AF~1635B
inter
2816
---tACC~
ADDRESSES
)K
tDECODE
ADDRESS 2
ADDRESS t
~--tCE
__
--tRD-
\.
-tOE-
/
\.
DATA BUS
)(
DATA t VALID
ACTIVE
CE2
OEIRD)
,'----,'----
~
NO OVERLAP
Figure 4. Two-Line Control Architecture
8087
8089
8283
LATCH
8287
BUFFER
Figure 5. iAPX 86/2816 Read Architecture
5-105
AFN-OI635B
2816
Write Mode
CONTROLLERS
The 2816 is erased and reprogrammed electrically
rather than optically, as opposed to EPROMs which
require UV light. The device offers dramatic flexibility because both byte (single location) and chip
erase are possible.
Controller I Description
A close examination of the broad application spectrum for the E2 device reveals an inherent need for
single location erase capability. Program store applications can be classified in several ways. Figure 6
lists various storage modes and the required erase
function. In greater than 800A> of all cases, a byte
erase feature is necessary.
APPLICATION TYPE
• Strict Program Store
The Controller I interface provides the lowest cost,
smallest P.C. board space implementation, though it
is unable to offer the maximum CPU throughput
capability since wait states are inserted into the
memory cycle during the 10 ms write time. Figure 7
shows the block diagram for this implementation. A
timer device is provided to time 10 ms, which connects directly to the CPU READY line. When activated, the timer engages the Vpp switch, locks the
CPU address, data, and control bus, and writes the
2816. After completion of the write cycle, the CPU is
relinquished to do other tasks. Such a control application is appropriate when the processor can be
dedicated to the write, such as in program store.
IDEAL
ERASE MODE
CHIP
• Relocalable Program Structures
BYTE
• Program Store Extension
• Program Execution Conslants
e Program Dependent Data Siore
BYTE
BYTE
• Oa.a Store Applications
BYTE
BYTE
Figure 6. Microprocessor Storage Types
To write a particular location, that byte must be
erased prior to a data write. Erasing is accomplished
by applying logic 1 (TTL-high) inputs to the data
input pins, lowering CE, and applying a 21-volt programming signal to Vpp. The OE pin must be held at
V1H during byte erase and write operations. The programming pulse width must be a minimum of 9 ms,
and a maximum of 70. The rising edge of Vp p must
conform to the RC time constant specified above.
Once the location has been erased, the same operation is repeated fora data write. The input pins in this
case reflect the byte that is to be stored.
A characteristic of all E2 PROMs is that the total
number of erase/write cycles is not unlimited. The
2816 has been designed and manufactured to meet
applications requiring up to 1 X 104 erase/write cycles per byte. The erase/write cycling characteristic
is completely byte independent. Adjacent bytes are
not affected during erase/write cycling.
Because the device is designed to be written in system, all data sheet specifications (including write
and erase operations) hold over the full operating
temperature range (O-70°C).
READ
ACCESS
""250n,ec
ADDRESS
DATA
CONTROL
Figure 7. Controller I
Controller II Description
To provide a higher CPU throughput capability, the
interface shown in Figure 8 was designed. In this
case, all latching and timing signals are generated
by discrete devices. The CPU simply sends a write
operation to the interface as it would to a RAM device. After the CPU has engaged the write sequence,
it is free to perform other tasks notrelated to 2816
control. At the completion of the write cycle, the
interface interrupts the CPU which then vectors to
an interrupt service routine. Controlier II offers realtime CPU performance with a high degree of hardware overhead.
5-106
AfN.0163SB
inter
2816
access and hardware overhead were exceptionally
important. This controller takes the 2816 completely
off-line for both read and write operations. The write
cycle is accomplished in the same way as in Controller III. Reading, however, is accomplished
through several I/O operations .
....,
ACCE. .
= 250 IIMC
PLUS
....
BUf;FIIA
DELAY
""210 nue
READ
ACCESS
_250 "UC
CONTROL
PLUS
SYSTEM
r'---'---'-_ _ _.L.-I.-J"j0VERH£AD
8155
Figure 8. Controller II
DATA
Controller III Description
CONTROL
The Controller III implementation was designed to
provide the real-time processing capability of Controller II, without the large hardware overhead. See
Figure 9. In this design an Intel 8155 I/O port timer
device is used to advantage. The ports provide the
latching of data and address during the write cycle,
while the timer performs accurate pulsing of the Vpp
for the required duration. Much of the hardware has
been reduced througtl thll 8155. The interrupt
structure of Controller II is used as well. Read access is very fast despite a multiplexer and a buffer
delay.
Figure 10. Controller IV
Chip Erase Mode
Should one wish to erase the entire 2816 array at
once, the device offers a chip erase function. When
the chip erase function is performed all 2K bytes are
returned to a logic 1 (FF) state.
The 2816's chip erase function is engaged when the
output enable (OE) pin is raised above 9 volts. When
OE is greater than 9 volts and CE and Vpp are in the
. normal write mode, the entire array is erased. This
chip erase function takes approximately 10 ms. The
data input pins must be held to a TTL high level
during this time. Figure 11 is a recommended OE
control switch.
READ
-
ACCESS
"'250npc
~
PLUS
______- ._______________ ro
OE
7407
B UFfER
DELAY
=290 nne
2K
10K
DATA
CHIP
ERASE
CONTROL
1.2t1:
Figure 9. Controller III
1.2K
Controller IV Description
Data store applications were in mind for the Controller IV design shown in Figure 10. In this case,
read access was not a concern, though write erase
Figure 11. ~ Chip Erase Control
For footnotes see page 13.
5-107
AFN-OI635B
2816
V pp Pulse
Voltage Generation
The shape of the Vpp pulse is important in ensuring
long term reliability and operating characteristics.
Vpp must rise to 21V through an RC waveform
(exponential). The TpRC specification has been designed to accommodate changes of RC due to temperature variations.
The Intel 2816 is a new generation of non-volatile
memory in which writing and erasing can be accomplished on board by providing a 21 volt pulse. In
order to generate the Vpp pulse, a power supply with
output voltage of +24V is needed. In a system
environment where this voltage is not available, a
switching regulator can be used to convert +5V to
+24V. Figure 12c shows the circuit diagram for such
a voltage converter. In systems where 24 volts is not
available, this circuit proves to be a cbst effective
alternative.
Figure 12a shows a recommended Vpp switch design, useful where programming will occur over the
specified temperature and operating voltage conditions. Figure 12b shows the waveform.
NV~---------~~~---~~---------------~
UK
TO
Vpp
"f-----vpp PIN
CONTROL
OF 2816
47K
NOTES.
1 5K IS 21V FINE ADJUST
2 RESISTORS ARE 1/4 WATT
Figure 12a. Operational Amplifier Vpp Switch Design
i4--------- t wP------l
--------~------~
v,
= 6V
For footnotes see page 5·115.
Figure 12b. Vpp Waveform
5-108
AFN.()1635B
inter
2816
i----- l
I
I
:F:
I
I
I
I
+24V
@
I
I
IL _-___
.JI
BYPASS
CAPACITORS
7SmA
AI,
TL497
C2
.1
C3
22
RS
UK
300pF
R3
18K
Cl
NOTES UNLESS SPECIFIED
1 RESISTORS ARE Y4 WATT
2 CAPACITOR VALUES ARE "F
3 L 1 IS 475 mA INDUCTOR (J. W MILLER 14630)
Figure 12c. Step-up Regulator Converts +5V Into +24V
Applications
The 2816 E2 PROM is a new and powerful addition to
the non-volatile family. It offers a high degree of
RAM-like flexibility while retaining the non-volatile
characteristics of ROM.
Because of these device parameters, the device is
ideal for new and future designs as well as a replacement for existing ROM devices. Some of these
potential uses are listed below:
1. Calibration constants storage (continuous
calibration).
2. Software alterable control stores (dynamic
reconfiguration).
Figures 13, 14, 15, and 16 are block diagrams of
some typical applications. These applications are
explained as follows:
DYNAMIC RECONFIGURATION
The ability of a computer system to alter its operating software while running is now possible with the
2816. The system can monitor external factors, as
well as change loop constants. subroutines and
other software features in real-time. Figure 13 iIIus-·
trates this optimal performance. In memory systems.
the 2816 can be used to map around hard memory
3. Remote communications programming.
4. PC and NC Industrial Applications.
5. CRTterminal configuration and custom graphic
and font sets.
6. Military replacements for core memory and
fuse-link PROMs.
7. Point of sale terminals.
8. Remote alterable look-up tables.
9. Printer and communications controllers.
10. Remote data gathering.
Because of these device attributes, applications
never before possible can now be realized in high
performance, consistent microprocessing systems.
Figure 13. Dynamic Reconflguration
5-109
2816
failures in real-time, allowing self-healing memory
systems. Such a self-correcting mechanism extends
the operating time and reduces service costs to the
end user.
CONTINUOUS SELF-CALIBRATION
A high cost of machine service and downtime is due
to inStrument calibration and readjustments. Use of
the 2816 and microprocessor based instruments to
contain calibration con'stants allows features never
before possible. See Figure 14. The instrument can
now continuously calibrate itself, without expensive
downtime in service interaction. The 2816 allows
this flexibility and reduction of service costs.
Figure 15,. CRT Terminal
capability to remotely (over telephone lines) configure the look up table from a central data base computer. The non-volatility of the 2816 is used to advantage as the data store remains intact after power is
removed from the system.
...---:=.,,--,
"""",,o,;;.;;;'-;;;i;;":;;''---'
PROOUCT
UNIVERSAL
PRICE
DESCRIPTION
PRODUCT
CODe
{2 bytes)
(15 bytes)
I
I
{5bYI~_-,- _ _
,...---'---.1\
e2 PROM
LOOK UP TABLE
Figure 14. Continuous Self-Calibration
CRT TERMINAL
Custom fonts, graphics characters, and individual
configurations can all benefit from the features of
the 2816. A CRT terminal, shown in Figure 15, can
now be enhanced by using the E2 as a replacement
forjumpers'and dip switches. It can also be used as a
programmable character generator, and in graphics
configuration.
POINT OF SALE TERMINAL
Using the 2816 to contain non-volatile price and
product descriptions, as shown in Figure 16, is an
ideal application in point of sale terminals. With the
ability of the 2816 to be altered in-system comes the
TO INVENTORY
RECORD
Figure 16. POS Terminal
Pin Compatibility
The 2816 pinout has been designed for compatibilit~ with present and future memory products. The
E PROM is a member of Intel's JEDEC standard\
Byte-Wide memory family which allows density upgrades, functional interchange, and extended product life, Figure 17 shows this JEDEC 28 pin site
pinout approach.
5-110
inter
..'"
'W
N
2816
•
iii ~
'"~
~
N
N
~
N
.iii
v••
Vee
PGM
A12
A,
Standby Mode
'W
....
'"
N
A,
A,
A,
Vee
Vee
Vee
He
A.
A.
A.
A.
A,
A,
Ag
Ag
V••
A"
V••
Au
OE
OElVpp OE
A"
A,.
A,.
A,.
EE
CE
CE
CE
The 2816 has a standby mode which reduces active
power dissipation by 55% from 110 mA to 50 mAo The
2816 is placed in the standby mode by applying a
TIL high signal to the CE input. When in the standby
mode, the outputs are in a high impedance state,
independent of the OE input.
EJW Inhibit Mode
i5E
Figure 17. JEDEC 28 Pin Site Byte-Wide
Philosophy
The 2816 EraselWrite Inhibit Mode is similar to
standby mode. Standby power is dissipated in this
mode and the device is deselected. One typically
enters this mode during a write cycle to an array of
2816's. One device is being written while the other
devices, conne.:;ted to a common Vpp line, are
deselected by CEo
Output OR-TIEING
Because 2816s are usually used in larger memory
arrays, Intel has provided a 2-line control function
that accommodates this use of multiple memory
connections. The 2-line control function allows low
power dissipation (by deselecting unused devices),
and the removal of bus contention from the system
environment.
To most effectively use these two control lines, it is
recommended that CE (pin 18) be decoded from
addresses as the primary device selection function.
OE (pin 20) should be made a common connection
to all devices in system, and connec~ed to the RD
line from the system control bus. This assures that
all deselected memory devices are in their low
power standby mode and that the output pins are
only active when data is desired from a particular
memory device.
5-111
AFN.()l635B
2816
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ............. -10°C to +80°C
Storage Temperature ............... -65°C to +100°C
All Input or Output Voltages with
Respect to Ground ................... +6V to -0.3V
VppSupply Voltage with Respect to
Ground During Write/Erase ........ +22.5V to -O.W
Maximum Duration of Vpp Supply at 22V
During E/W Inhibit .......................... 24 Hrs.
Maximum Duration of Vpp Supply at 22V
[7]
During Write/Erase ........................ 70 ms
"NOTICE: Stresses above those lIsted under' 'Absolute MaxImum
Ratings" may cause permanent damage to the device. ThIs is a
stress rating only and lunctional operatIon 01 the device at these
or any other condItions above those mdicated in the operational
sectIons of thIs specllication IS not ImplIed. Exposure to absolute
maxImum ratmg condItions lor extended periods may affect
deVIce reliabIlity.
I
D.C. AND A.C. OPERATING CONDITIONS DURING READ AND WRITE
I
I
2816
2816·3
2816·4
Temperature Range
0°C-70°C
0°C-70°C
0°C-70°C
VCC Power Supply[8]
5V ± 5%
5V ± 5%
5V ± 5%
D.C. CHARACTERISTICS
READ
Symbol
Parameter
Limits
Typ.[l]
Min.
Test Conditions
Units
Max.
III
Input Leakage Current
10
,.,.A
VIN = 5.25V
ILO
Output Leakage Current
10
,.,.A
Your = 5.25V
ICC2
VCC Current (Active)
50
110
mA
OE = CE = VIL
ICCl
VCC Current (Standby)
25
50
mA
CE = VIH
IpP(R)
Vpp Current (Read)
5
mA
CE = VIL, Vpp = 4 to 6
VldD.C.)
Input Low Voltage (D.C.)
-01
8
V
VIH
Input High Voltage
2.0
VCC+ 1
V
45
V
IOL = 2.1 mA
V
IOH = -400,.,.A
VOL
Output Low Voltage
VOH
Output High Voltage
Vpp
Read Voltage
VldA.C.)
Input Low Voltage (A. C.)
2.4
4
V
6
-0.4
Time = 10 ns
V
WRITE
Symbol
Parameter
Vpp
Write/Erase Voltage
Ipp(W)
Vpp Current (Byte Erase/Write)
VOE
OE Voltage (Chip Erase)
IpP(I)
Vpp Current Inhibit
Ipp(C)
Vpp Current (Chip Erase)
Limits
Units
Min.
Typ.[l]
Max.
20
21
22
V
9
15
mA
15
9
3
V
5
mA
5
mA
Test Conditions
CE = VIL
IOE = 10,.,.A
Vpp = 22, CE = VIH
Footnotes follow timing diagrams
5-112
AFN-Q1635B
inter
2816
CAPACITANCE[1) TA =
Symbol
A.C. TEST CONDITIONS
25'C, f = 1 MHz
Parameter
CIN
Input Capacitance
COUT
Typ.
Max.
Units
Output Load: 1TTL gate and
Test
Conditions
CL =100pF
Input Pulse Levels: 0.45 to 2.4V
Timing Measurement Reference
Level: Input 1V and 2V
Output .8V and 2V
= OV
10
pF
VIN
Output Capacitance
10
pF
VOUT
CVcc
Vee Capacitance
500
pF
OE
= CE = VIH
CVpp
Vpp Capacitance
50
pF
OE
= CE = VIH
5
= OV
A.C. CHARACTERISTICS
READ
Symbol
Parameter
2816 Limits
2816·3 Limits
2816-4 Limits
Test
[ ]
[ ]
[ ]
Units Conditions
Min. Typ. 1 Max. Min. Typ. 1 Max. Min. Typ. 1 Max.
Address to Output
Delay
200
250
300
350
400
450
ns
CE = OE = VIL
tCE
CE to Output Delay
200
250
300
350
400
450
ns
OE = VIL
tOE
Output Enable to
Output Delay
10
100
10
120
10
150
Output Enable High
to Output Float
o
80
o
100
o
130
Output Hold from
Addresses, CE or OE
Whichever Occurred
First
o
o
o
WRITE
Symbol
Parameter
Min.
Limits
Typ.[l]
Max.
Units
tAS
Add to'Vpp Set-Up Time
150
tes
CE to Vpp Set-Up Time
150
ns
tOS[9)
Data to Vpp Set-Up Time
0
ns
tOH[9)
Data Hold Time
twp[7]
Write Pulse Width
Test Conditions
ns
50
ns
9
10
70
Vpp
= 6V
ms
50
ns
Vpp
= 6V
0
ns
VPP
= 6V, VOE = 9V
ns
Vpp
= 6V, V6E = 9V
tWR
Write Recovery Time
tos
Chip Erase Set-Up Time
tOH
Chip Erase Hold Time
tpRe
Vpp RC Time Constant
tpFT
Vpp Fall Time
1
tBOS
Byte Erase/Write Set-Up Time
0
tBOH
Byte Erase/Write Hold Time
0
0
450
600
750
/Ls
100
/LS
Vpp
= 6V
ns
Vpp
= 6V
ns
Vpp
= 6V
Footnotes follow timing diagrams
5-113
AFN'()1635B
2816
WAVEFORMS
READ
K
~------------------~
ADDRESSES
I~
ADDRESSES VALID
__________________
-JI
~
~------
v
___-+ _ ____ _ _-JI
v
---------1
VALID
OUTPUT----------+-----------~
OUTPUT
. . . . - - tACC---"
BYTE ERASE OR WRITE I51
ADDRESSES
>4-
\
. . . - - - lAS
tcs-+
-
IWR'"
~tpRC
141
~
toS-+
-
..... IWR ........
- - . tpFT
(4-6V)
K
V
-----+- I... t-twp-I
Vep
..
- --
~IOH
VALID
DATA IN
,
teos-+
-
......
--'eoH
Footnotes follow timing diagrams
5-114
AF~1e35B
inter
2816
WAVEFORMS (Continued)
CHIP ERASE[61
CE --------------"'"
v,' ____________________--;
(4~6V)
DATA IN
-----------------'1
DE ________-'"V':::.H______--JJ
NOTES:
1. This parameter is only sampled and not 100% tested.
2. OE may be delayed up to 230 ns after falling edge of CE
without impact on tACC for 2816.
3. tOF is specified from OE or' CE whichever occurs first.
4. The rising edge of Vpp must follow an exponential waveform.
That waveform's time constant is specified' as tpRC' See
Figure 12b.
5. Prior to a data write, an erase operation must be performed.
For erase, data in = VIH.
6. In the chip erase mode DIN = VIH.
5-115
7. Adherence to'TWP specification is important to device
reliability.
8. To prevent spurious device erasure or write, VCC must be
applied simultaneously or before 21 volt application of Vpp.
Vpp cannot be driven to 21 volts without previously applying
VCC·
9. The data in set up and hold times for chip erase are identical
to those specified for by1e erase.
AFN-Q1635B
2816A
16K (2K x 8) ELECTRICALLY ERASABLE PROM
• 5 Volt Only Operation
• HMOS*-E Flotox Cell Design
• Fast Read Access Time:
-2816A, 250ns Max
-2816A-3, 350ns Max
-2816A-4, 450ns Max,
• 10,000 Erase/Write Cycles
• Unlimited Number of Read Cycles
• Conforms to JEDEC Universal Site
• Erase/Write Specifications
Guaranteed 0-70°C
• Byte Erase/Write with TTL Level WE
Signal
• 9ms Byte Erase/Write Time
• 9ms Chip Erase Time
• Inadvertent Write Protection on Power
Up and Power Down
• Completely Compatible with 2816
The Intel 2816A is a 16,384-bit electrically erasable programmable read-only memory (E 2 PROM), The 2816A can
be easily erased and reprogrammed on a byte basis with a TTL-low level signal on WE. The 2816A operates from
a single 5 Volt supply. External programming voltage and write pulse shaping are not required because they are
generated by on-chip circuitry.
The Intel 2816A is also completely upward compatible with the Intel 2816 E 2 PROM. Dual voltage detection logic
allows the 2816A to use an existing, externally supplied high voltage programming pulse required with the 2816
to write to the Intel 2816A. No hardware changes are required when substituting a 2816A in an existing 2816
socket. 8ystem upgrades to 5 volt only operation can be implemented, however, by removing the 21Vand write
shaping circuitry. The 2816A, like the 2816, has fast read access speeds allowing zero wait state read cycles with
high performance microprocessors such as the iAPX186.
The electrical erase/write capability of the 2816A makes it ideal for a wide variety of applications requiring
m-system, non-volatile erase and write. Any byte can be erased in 9ms without affecting the data in any other
byte. Alternatively, the entire memory can be erased in 9ms allowing the total time to rewrite all2k bytes to be cut
by 50%. The 2816A is part of the Intel E2 PROM family that provides a significant increase in flexibility allowing
new applications (remote firmware update of program code, dynamic parameter storage) never before
possible.
The 2816 E2 PROM possesses Intel's 2-lme control architecture to eliminate bus contention in a system
environment. A power down mode is also featured; in standby mode, power consumption is reduced by over
50% without increasing access time. The standby mode is achieved by applying a TTL-high signal to the CE
input.
The 2816A 82815 is available for very cost sensitive applications which require the flexibility E2 PROMs provide
without the need for fast byte erase/write and fast chip erase. The 2816A 82815 has byte erase/write and chip
erase times of 50 ms each.
'HMOS-E
IS
a patented process of Intel Corporation
1
Ad
1
2
Ad
2
A,
3
AT
Figure 1. 2816A Functional Block Diagram
=-
A,
As L 3
A2l
6
2816A
A,
l
7
e2PROM
Ao
19
AlO
A4l
4
A"
5
Ad
6
A,[
7
i
8
Ao
i
8
101001
9
001
9
1,10,
10
0,[
10
12102,
11
021
11
GND·
12
GNO [
12
13
-; IJi03
2716
EPROM
~
t
CE A"
O'E
OUTPUT E-NA;LE
DATA ~TP~TS
10 17
DATA INPUTS
'''Pi
wR'Te
-
--
~NA!,-e ,,,p op~
---
00 0]
WE
l
~
A•• "
,,"
CHIP
ENA6LE
--
__
Figure 2. Pin Configuration
Intel CorporatIOn Assumes No Responslbilly for the Use of Any CircUitry Other Than CircUitry Embodied
(f; INTEL CORPORATION, 1982
!
PIN NAMES
~
5-116
In
an Intel Product No Other CirCUIt Patent licenses ale Implied
NOVEMBER 1982
ORDER NUMBER: 210823-001
2816A
DEVICE OPERATION
The 2816A has six modes of operation, listed in Table
1. All operational modes are designed to provide
maximum microprocessor compatibility and system
consistency.
Table 1. Mode Selection
~
MODE
CE
(18)
OE
(20)
WE
(21)
INPUTS/
OUTPUTS
Read
VIL
VIL
VIH
DOUT
Standby
VIH
Don't
Care
Don't
Care
HighZ
Byte Erase
VIL
VIH
VIL
DIN=VIH
Byte Write
VIL
VIH
VIL
DIN
Chip Erase
VIL
+9
to
+15V
VIL
DIN=VIH
No Operation
VIL
VIH
VIH
High Z
All control inputs are TTL-compatible with the exception of chip erase.
READ MODE
Optimal system efficiency depends to a great extent
on a tightly coupled microprocessor/memory interface. The E2 PROM device should respond rapidly
with data to allow the highest possible CPU performance. The 2816A satisfies this high performance
'requirement because of read access times typically
less than 250ns. Program execution directly out of
electrically erasable memory has never before been
possible; the 2816A opens this new, powerful applications segment.
The 2816A uses Intel's proven 2-line control architecture for read operation. The 2-line control function
removes bus contention from the system environment and allows low power dissipation (by deselecting unused devices).
Figure 3 shows the timing disadvantages of a
single-line control architecture. 2-line control,
shown in Figure 4, has been developed by Intel to
solve this bus contention and the associated system
reliability problems. Both CE and OE must be at logic
low levels to obtain information from the device. Chip
enable (CE) is the power control pin and should be
used for device selection. The output enable (OE) pin
serves to gate internal data to the output pins.
Assuming that the address inputs are stable, address
access time (tACC) is equal to the delay from CE to
output (tCE)' Data is available at the outputs after a
time delay of tOE, assuming that CE has been low and
addresses have been stable for at least tACC-tOE.
Figure 5 shows a typical system interconnection.
Here the 2816A contains program information that
the 8086 requires for system function. CE (pin 18) is
decoded from addresses as the primary device selection function. OE (pin 20) should be made a common
connection to all devices in system, and connected
~~-IACC~~-
K
ADDRESSES
IDECODE-
)V
ADDRESS I
-,
--ICE
-.~
ADDRESS 2
IDECODE
ITURNOFF
V
1\
OUTPUTS 1
DESELECTING
DATA BUS
V
1\
OUTPUTS 1
ACTIVE
'IV
DATA 1 VALID
--IACC--
DATA BUS
OUTPUTS 1
ACTIVE
X
DATA 1 VALID
XOUTPUTS 2' V
ACTIVE
Figure 3. Single-Line Control and Bus Contention
5~117
DATA 2 VALID
2816A
--IACC~
ADDRESSES
)(
IDECODE -
ADDRESS 1
ADDRESS 2
~~~~ICE-
-IRD-
\
I\.
-16E-
JK
DATA BUS
,
K
DATA 1 VALID
ACTIVE
,,'---,,'----
~
NO OVERLAP
Figure 4: Two-Line Control Arcllitecture
8087
8089
AD
8283
LATCH
8287
BUFFER
Figure 5. iAPX 86/2816A Read Krchitecture
5·118
AFN-OOB65A
2816A
the chip erase function is performed, all 2K bytes are
returned to a logic 1 (FF) state.
to the RD line from the system control bus. This
assures that all deselected memory devices are in
their low power standby mode and that the output
pins are only active when data is desired from a
particular memory device.
The 2816A's chip erase function is engaged when the
output enable (OE) pin is raised above 9 volts. When
OE is greater that 9 volts and CE and WE are in the
normal write mode, the entire array is erased. This
chip erase function takes approximately 10ms. The
data input pins must be held to a TTL-high level
during this time.
WRITE MODE
The 2816A is erased and reprogrammed electrically
as opposed to EPROMs which require ultraviolet
light for erasure. The device offers dynamic flexibility
because both byte (single location) and chip erase
are possible.
STANDBY MODE
The 2816A has a standby mode which reduces active
power dissipation by 50% from 100ma to SOma. The
2816A is placed in standby mode by applying a TTLhigh signal to the CE input. When in the standby
mode, the outputs are in a high impedance state,
independent of the OE and WE input.
A close examination of the broad application spectrum for the E2 device reveals an inherent need for
single location erase capability. Program store applications can be classified in several ways. Figure 6
lists various storage modes and the required erase
function. In greater than 80% of all cases, a byte
erase feature is necessary.
APPLICATION TYPE
The standby mode for the 2816A is a superset of the
standby mode for the 2816. The standby mode for the
2816A includes the E/W Inhibit mode of the 2816.
IDEAL
ERASE MODE
• STRICT PROGRAM STORE
• RELOCATABLE PROGRAM STRUCTURE
CHIP
BYTe
• PROGRAM STORE EXTENSION
BYTe
• PROGRAM EXECUTION CONSTANTS
• PROGRAM DEPENDENT DATA STORE
• DATA STORE APPLICATIONS
BYTE
BYTE
BYTe
NO OPERATION MODE
This mode is frequently entered while in a read or
write cycle. In the READ cycle, CE may go low before
OE goes low because tCE (CE to Output Delay) is
longer than tOE (OE to Output Delay). While CE is low
with OE and WE at TTL-high, no READ, ERASE, or
WRITE operation will occur. The read operation
would begin in the READ cycle when OE input also
falls to TTL-low.
Figure 6. Microprocessor Storage Types
To write a particular location, that byte must be
erased prior to a data write. Erasing is accomplished
by placing the byte address at the address input pins,
applying logic 1 (TTL-high) to all eight data input
pins, and lowering CE, WE to VIL. The OE pin must be
held at V IH during byte erase and write operations.
The WE pulse width must be a minimum of 9ms, and
a maximum of 70ms. Once the location has been
erased, the same operation is repeated for a data
write. The data input pins in this case reflect the byte
that is to be stored. The data to be programmed,
address and control signals must be presented to the
2816A throughout the required programming time.
Because the device is designed to be written in system, all data sheet specifications (including write
and erase operations) hold over the full operating
temperature range (0-70° C).
CHIP ERASE MODE
Should one wish to erase the entire 2816A array at
once, the device offers a chip erase function. When
The No Operation mode differs from Standby Mode
in that active power is drawn by the 2816A in this
mode.
WRITE TIME CHARACTERISTICS
The 2816Awrite time specification is 9ms (min.) and
70ms (max.). If the write pulse width applied to the
WE input is 9ms, the programmed byte is guaranteed
to be correctly and reliably programmed to any location in the 2816A.
The maximum pulse width to the WE input of 70ms
limits the duration of the pulse width. Exceeding this
specification may overstress the E2PROM cells and
affect long term device reliability. Any write pulse
width between 9ms and 70ms will also guarantee
byte programming and chip erase over the full temperature range.
Programmed data will be retained by the Intel 2816A
for over 10 years.
5-119
AFN-0086SA
2816A
APPLICATIONS .
Although the number of read cycles is unlimited, a
characteristic of all E2 PROMs is that the total number of erase/write cycles is not unlimited. The 2816A
has been designed and manufactured to meet applications requiring up to 1 X 104 erase/write cycles per
byte. The erase/write cycling characteristic is completely byte independent. Adjacent bytes are not affected during erase/write cy~ling.
The 2816A E2 PROM is a new and powerful addition
to the Intel non-volatile' family. Like other Intel
E 2 PROMs, it offers a high degree of flexibility
through in-circuit alterability while retaining the nonvolatile characteristics of ROM.
Because of these device parameters, the device is
ideal in many applications. Some of the potential
uses are listed below:
Write Protection on Vee Power Up and
Power Down[1]
1. Calibration constants storage (continuous
calibration)
An erase/write of a byte in the 2816A is accomplished with input signals CE, WE = VIL. During system (Vcc) power up and power down, this condition·
may be present as Vcc ramps up to or down from its
steady state value of 5 volts. To prevent the possibility of an inadvertent byte write during this power
transition period, an on-chip sensing circuit disables
the internal programming circuit if Vcc falls below 4
volts.
The hardware designer should determine if the circuitry driving the CE and WE inputs provides a stable
VIH level when Vee is above 4.0V.lf the drive circuitry
is stable at Vee >4.0V then the 2816A's internal WE
protection circuit should be adequate. If the designer
feels that write protection is needed when Vee is
above 4.0V, then an external circuit such as the write
protection circuit in Application Note (AP) 148
should be used.
2. Software alterable central stores (dynamic
reconfiguration)
3. Remote communication programming
4. PC and NC Industrial Applications
5. CRT Terminal configuration and custom graphic
and font sets
6. Military replacement for core memory and fuselink PROMs
7. Point of sale terminals
8 Remote alterable look-up tables
9. Printer communications, controllers
10. Remote data or error logging
11. Replacing CMOS RAM and battery backup
12. Remote firmware update of program cbde
VPP OPTION
Although the Intel® 2816A requires only 5 volts for
programming, it was designed to be totally upward
compatible with the Intel 2816. No hardware changes
are required when substituting a 2816A into a 2816
socket. Shaping of the Vpp programming pulse is
also not required with the 2816A. Table 2 lists the Vpp
Option Modes.
Table 2. VPP Option Modes
MODE
~
CE
(18)
OE
(20)
VPP
(21)
INPUTS/
OUTPUTS
Byte Erase
VIL
VIH
20-22V
DIN=VIH
VIL
VIH
20-22V
DIN
VIL
+9V
to
+15V
20-22V
DIN=VIH
Byte Write
Chip Erase
5-120
AFN-00865A
2816A
ABSOLUTE MAXIMUM RATINGS·
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the devIce at these or any other conditions above
those indicated in the operatIonal sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Temperature Under Bias ............. -10°C to +BO°C
Storage Temperature ............... -65°C to +100°C
All Input or Output Voltages with
Respect to Ground .................. +6V to -0.3V
D.C. AND A.C. OPERATING CONDITIONS DURING READ AND WRITE
I
I
2816A
2816A-3
2816A04
Temperature Range
acC-7acC
acC-7acC
acC-7acC
Vee Power Supply
5V± 5%
5V± 5%
5V±5%
D.C. CHARACTERISTICS
Limits
Symbol
Parameter
Units
Min.
Typ.[2)
Test Conditions
Max.
III
Input Leakage Cu rrent
10
/LA
ILO
Output Leakage Current
10
/LA
VOUT =5.25V
lee2
Vee Current (Active)
50
100
mA
OE =CE =VIL
lee1
Vee Current (Standby)
25
50
mA
CE =VIH
VldD.C.)
Input Low Voltage (D.C.)
-0.1
.B
V
20
Vee+ 1
V
45
V
VIN =5.25V
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
VldA.C.)
Input Low Voltage (A.C)
leew
Vee Current (Byte Erase/Write)
130
mA
OE Voltage (Chip Erase)
15
V
VOE
IOL =2.1mA
2.4
V
IOH =-400/LA
-0.4
V
Time =10 ns
9
"WE=CE=VIL
IOE = 10 /LA
A.C. TEST CONDITIONS
Output Load ............. 1TTL gate and CL = 100 pF
Input Pulse Levels ....................... -O.B to 2.2V
Timing Measurement Release:
Level .............. Input 1V and 2V/Output .BV and 2V
Input rise/fall time ............................. 10 ns
CAPACITANCE[2]
Symbol
TA = 25"C, f =1 MHz
Parameter
CIN
Input Capacitance
COUT
Output Capacitance
Cvee
Vee Capacitance
CWE (VPP)
WE Input Capacitance
Typ.
Max.
Units
5
10
pF
VIN =OV
10
pF
VOUT =OV
500
pF
OE =CE =V'IH
50
pF
OE =CE =VIH
5-121
Test Conditions
AFN-00885A
~[fJ~[l"O~O~~[fJW
2816A
A.C. CHARACTERISTICS
READ
tACC
Test
2816A-4 Limits
2816A Limits
2816A Limits
Units Conditions
Min. Typ.[21 Max. Min. Typ.[21 Max. Min. Typ.[21 Max.
Parameter
Symbol
Address to Output
Delay
200
200
250
300
350
400
450
ns
CE
= OE = VIL
250
300
350
400
450
ns
OE
=. VIL
tCE
CE to Output Delay
tOE
Output Enable to
Output Delay
10
100
10
120
10
150
ns
CE
= VIL
tPF
Output Enable High
to Output Float
0
80
0
100
0
130
ns
CE
= VIL
tOH
Output Hold from
Addresses, CE or OE
Whichever Occurred
First
0
ns
CE
= OE = VIL
0
0
WRITE
Limits
Parameter
Symbol
Units
Min.
Typ.[21
Test Conditions
Max.
tAS
Address to Write Set-Up Time
150
ns
tes
CE to Write Set-Up Time
150
ns
tOS[31
Data to Write Set-Up Time
0
ns
tDH[31
Data Hold Time
100
ns
Vpp =6V
twp[41
Write Pulse Width for 2816A
9
70
ms
twp[41
Write Pulse Width for 2816A S2815
50
70
ms
tWR
Write Recovery Time
100
ns
Vpp =6V
tos
Chip Erase Set-Up Time
0
ns
Vpp =6V, VOE =9V
tOH
Chip Erase Hold Time
0
ns
Vpp =6V, VOE =9V
tBOS
Byte Erase/Write Set-Up Time
0
ns
Vpp =6V
tBOH
Byte Erase/Write Hold Time
0
ns
Vpp =6V
tWWR
Cycle Delay Time Following Write Cycle
40
MS
5-122
AFN-00865A
intJ
2816A
WAVEFORMS
READ
',----------~K
ADDRESSES VALID
__________________
-JI
ADDRESSES
~
~-----
v
1'-____-+
__ - - - ___JI
v
_to,I·'r
- ----------'1
OUTPUT
~ ~ ~ ~O~~_~~T--J.I.I.U»)~
-----+----~~
+---IACC - - - + -
BYTE ERASE OR WRITE I71
ADDRESSES
K
}
.....-Ics-..
\
twA ....
-
..--tAS---""
4-
/
4----
lwP----"" ... twR.....
,
lOS .........
-
......
__ tOH
VALID
DATA IN
'BOS-+-
I-
5-123
......
-'BOH
AFN-Q0BB5A
intJ
2816A
WAVEFORMS (Continued)
CHIP ERASE[8]
C"E-------""""'\
les
~------Iwp------~
WE - - - - - - - - - - ,
DATA IN
----------'1
OE ______~V~IH~_____'I
NOTES:
1. To prevent SpUriOUS device erasure or write, CE or WE input signals must be at V I H when V CC at or above 4.0 volts
2. This parameter is only sampled and not 100% tested.
3. The data in set up and hold times for chip erase are identical to those specified for byte erase
4. Adherence to TWP specification is important to device reliability.
5. DE may be delayed up to 230 ns after failing edge of CE Without Impact on tACC for 2816A.
or BE whichever occurs first
6. tOF IS specified from
7. Prior to a data write, an erase operation must be performed. For erase, data in = VIH.
8. In the chip erase mode DIN =VIH.
De
5-124
AFN-<1086SA
inter
2816A
WAVEFORMS (Continued)
CONSECUTIVE BYTE ERASE OR WRITE CYCLES
CE - - - - ,
WE _ _ _ _'-\J.o~-------IWp---------l
CiE
IWp--
----I
xxxxxxx
DONTCARE
BYTE WRITE FOLLOWED BY READ CYCLE
CE - - - - - .
WE-----...,
CiE----...J
INPUTfOU;~~
- - - - - ( ' - -_ _ _ _ _D_:J.:
....~_~N
_ _ _ _ _ __ i '
DATA OUT
VAUD
NOTES: (Continued)
9 Adherence to tWWR is Important for device reliability
5-125
AFN-00865A
2816A
VPP OPTION SPECIFICATIONS[10]
ABSOLUTE MAXIMUM RATINGS
'NOTlCE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to a,bsolute maximum rating conditions for extended periods may affect
device reliability.
Vpp Supply Voltage with Respect to Ground
During Write/Erase....... .... . ... +22.5V to -O.lV
Maximum Duration of Vpp Supply at 22V
During Erase/Write Inhibit .................... 24 Hrs.
Maximum Duration of Vpp Supply at 22V
During Write/Erase ............................ 70 ms
D.C. CHARACTERISTICS
Limits
Symbol
Units
Parameter
Min.
IpP(R)
Vpp Cu rrent (Read)
Vpp
Read Voltage
Ipp(W)
Vpp Current (Byte Erase/Write)
Vpp
Write/Erase Voltage
Ipp(C)
Vpp Current (Chip Erase)
CAPACITANCE[2]
Typ.[21
.01
mA
4
6
.01
20
Test Conditions
. Max.
V
mA
21
22
.01
CE =VIL, Vpp =4
to 6
CE =VIL
V
mA
TA =25"C, f =1 MHz
Parameter
Units
Vpp Capacitance
Test Conditions
pf
OE =CE =VIH
A.C. CHARACTERISTICS
Limits
Symbol
Parameter
Units
Min.
Typ.[21
tPRC
Vpp RC Time Constant
750
,",s
tpFT
Vpp.Fall Time
100
,",s
5-126
Test Conditions
Max.
Vpp =6V
AFN-008SSA
inter
2816A
BYTE ERASE OR WRITE (7 )
ADDRESSES
}
4-lcs--'"
\
twR ....
-
...-tPRC
4 - - I A S - - - " ;.... t-
(4-6V)
lOS-+-
[111
IWp--+-1
---+-
-
K
V
-
... twR .....
tpFT
vf\
- --
4 - IOH
VALID
DATA IN
'BOS_
~
--
i--'BOH
NOTES: (Continued)
10 Only spec.flcations umque to Vpp option operatIon are shown All other specifications under 5 volt only operatIon apply to Vpp
optIon operatIon as well, except where noted
11. Refer to 2816 Data Sheet, Fig 12bfordetall
5-1?7
2817
16K (2K X 8) ELECTRICALLY ERASABLE PROM
• Self Timed Byte Write with Automatic
Erase
'
• Fast Byte Write Time:
-Write Typical, 5 mS
-Cycle Typical, 10 mS
• Very Fast Read Access Time:
-2817, 250 nS
-2817-3,350 nS
-2817-4, 450 nS
• Direct Microprocessor Interface
Capability
• Static 21 Volt Vpp
• Reduces Support Component
Requirement by 70% to 90%
Over 2816 and 2815
• Reliable Intel FLOTOX E 2 PROM
Technology \
The Intel 2817 is a 16,384 bit Electrically Erasable Programmable Read Only Memory. Like the Intel 2816 and
2815, it has completely Non-Volatile Data: Storage. However, in addition, it offers a high degree of integrated
functionality which enables in-circuit byte writes to be performed with minimal hardware and software
overhead. The Intel 2817 is a product of Intel's advanced E2PROM technology and uses the powerful HMOS*-E
process for reliable, non-volatile, data storage.
The Intel 2817 eliminates all the interfacing hardware logic and firmware required to perform data writes. The
device has complete self-timing which leaves the processor free to perform other tasks until the 2817 signals
'Ready.' With a transparent erase before write, the user benefits by saving an erase command contributing to
efficient usage of system processing time. On chip latching further enhances system performance.
The Intel 2817's very fast read access time makes it compatible with high performance microprocessor
applications. It uses Intel's proven 2-line control architecture which eliminates bus contention in ii system
environment. Combining these features with the 2817's 'Ready' signal makes the device an extremely powerful,
yet simple to use, E2 memory-available to the designer today.
The density, and level of integrated control, makes the Intel 2817 suitable for users requiring low hardware
overhead, high system performance, minimal board space and design ease. Designing with, and using the 2817,
is extremely cost effective as 70% of the required voltage and interfacing hardware required for other E2PROM
devices has been eliminated. See Figures 1. 2, and 3 for the Intel 2817's block diagram, pinout, and simple
interface requirements.
'HMOS-E is a patented process of Intel Corporation.
v"
v"
W!
PIN NAMES
A,
A,
ADDRESSES
AO-AlO
A,
CE
CHIP ENABLE
OE
OUTPUT ENA8LE
00-0 7
DATA OUTPUTS
10 -17
DATA INPUTS
Vpp
STATIC PROGRAMMING VOLTAGE
ROY/BuSY
DEVICE READYI BUSY
TC
N.C
TIMING CAPACITOR
,
..
rc
"
"
A,
OE
A,
A"
A,
Sf
17/07
NO CONNECT
Is/De
1,/01
Is/Os
1.10.
13103
Figure 1. 2817 Functional Block Diagram
Figure 2. 2817 Pin Configuration
Intel Corporation Assumes No Responsibilty for the Use of Any Circuitry Other Than Circuitry Embodied
© INTEL CORPORATION, 1982
5-128
In an Inlel Product. No Other Circ'Jit Patent Licenses aTe Implied.
NOVEMBER 1982
ORDER NO. 210255-003
inter
2817·
FROM DECODER
+5VDC
FROMIil)---:---tOE
Vpp
+21V DC
FROMWII---;---!w.
TC
~
RDYllIUSV .
TO INTERRUPT
5600 pF
GND
chip verification to ensure successful byte pro·
gramming. This is achieved by comparing the data
. written to the cell with the data latched on chip during the write request. The timing capacitor (TC) is
used by the 2817 to generate the correct internal
Vpp rise time constant for cell programming. Its
value is 5600 pF ± 10%.
Should a regulated +24V DC be available in the system, the circuit shown in Figure 4 can be used to
provide the required Vpp voltage. Should +24V not
be available, the implementation in Figure 5 can be
used to provide the static programming voltage.
There are also many DC/DC converter modules
available that convert + 5V to + 21V. See AP 148
(Using the Intelligent 2817 E2 PROM) for additional
detail.
I
I
.....-SY-ST-E-M- I --2-81-7-"
REQUIREMENTS I REQUIREMENTS
lN91_
~24VDC----v\
V'---r------;
~--Vpp
+21V
Figure 3. Simple 2817 Interface Requirements
DEVICE OPERATION
The Intel 2817 has 4 modes of user operation which
are detailed in Table 1. All modes are designed to
enhance the 2817's functionality to the user and
provide total Intel E2 PROM microprocessor
compatibility.
Table 1. Vee = +5V, Vpp = +21V(1)
~n
Mode
CE
~
WE
Read
VIL
VIL
VIH
DOUT
Standby
Write
VIH
X
X
High Z
VOH
VIL
VIH
DIN
VOH
X
X
High Z
VOL
Busy
U
X
10/0 0- 17/0 7 ROY/BUSY
VOH
The Write Mode
Figure 4. Voltage Stepdown from +24V DC
to +21V DC
The Read Mode
One aspect of the 2817's high performance is its very
fast read. access time-typically less than 250 ns. It's
read cycle is similar to that of EPROMS and static
RAM's. It offers a 2 line control architecture to eliminate bus contention. The Intel 2817 can be selected
using decoded system address lines to CE and then
the device can be read, within the device selection
time, using the processor's RD signal connected to
'DE. As an option, the 2817 can be read with +5
volt on·Vpp(2)
The Standby Mode
The 2817 is programmed electrically in·circuit, yet it
provides non·volatile storage without the constraint
of ultraviolet erasure with EPROMs or of batteries
with CMOS RAMs. Writing to non,volatile memory
has never been easier as no external latching, eras·
ing or timing is needed. When commanded to byte
write, the 2817 automatically latches the address,
data, and control signals, and starts the write. Con·
currently, the 'Ready' line goes low indicating that
the 2817 is Busy and that it can be deselected to
allow the processor to perform other tasks. During
the write, the static Vpp is used to perform an
automatic byte erase, then write. The 2817 has on·
The 2817 has a standby mode in which power consumption is reduced by 50%. This offers the user
power supply cost benefits when designing a system
with Intel 2817's. This mode occurs when the device
is deselected (CE=1). The data pins are put into the
high impedance state regardless of the signals applied to OE and WE concurrent with the reading and
writing of other devices.
System Implementation
The 2817 is compatible with Intel MCS$-80/85 and
5-129
AFN-021Q1 A
2817
'sv
R1
r-----l
I
.SIl'hW
I
I
CRl
pi
-
1N914
~__________+-______-+ ~;K ~
I
L _-___ ...J
41
TL497
, BYPASS
CAPACITORS
RS
C2
C3
.1
22
1.2K
R3
18K
300pF
C1
NOTES UNLESS SPECIFIED
1 RESISTORS ARE Y4 WATT
2 CAPACITOR VALUES ARE J,.I.F
3 L 1 IS 475 rnA Inductor .,(J W Miller #4630)
Figure 5. Step-up Regulator Converts +5V to +21V
DATA & ADDRESS TO OTHER DEVICES
SELECT OTHER DEVICES
...
WRITE
j
---
--
Vss
RESET
ADo-AD7
0
~x,
I
:I
I
I
8282
I
Aa-A12
I
----
.....----.
I
8205
I
I
~
I
~
CE
~
I
I
RO
I
iiE
RST6.S
GNO
n
T C h 5600
f
pF
I
I
I
I
I
I
I
I
I
I
r-- tSV
2817
As-Ala
I
ClK
TRAP
Vee
I
_S,
_S,
Vpp 1--+21V
Ao-A7
I
8085
A 13 -A 15
,
0 0 -0 7
I
I
I
ALE
SOD
SID
,--------------I
I
Vee
~x'
---
READ
INTR RSr5.S RST7.5
I
I
I
I
I
I
I
I
ROYIBUSY
~ _____ !~~N~E~S_ _ _ _ _ _ _ _ _ - '
SYSTEM NEEDS
Figure 6. 2817/8085 Interface Example
5-130
AFN-02101 A
intJ
2817
iAPX-86/88 Microprocessors. It requires no interface
circuitry and minimal support circuitry. Figure 6
shows an example of the 2817 interfaced to an Intel
8085. The Intel 8282 de-multiplexes the address lines
from ADo-A~ with the ALE signal. The Intel 8205
decodes the 2817's CE using A13-A15, with the
remaining decoded outputs used to select other
devices. When selected, the 2817 can be read from
and written to. The 'Ready' signal is connected to
RST 6.5, a level sensitive interrupt of the 8085.
Depending on the software design of the system, the
processor can be interrupted or the RST 6.5 can be
masked off and used as a status bit.
Interfacing to the Intel 8088 is similar to the 8085
interface. The difference lies in the use of the 8259A
(Programmable Interrupt Controller). The Ready line
can be connected to any of the interrupt request pins
in order to interrupt the processor, or to generate a
status bit. (See Figure 7).
tion parameters and accumulated totals. Soft key
configuration in a graphics terminal is an example
where user defined functions, such as protocol,
color, margins and character fonts can be keyed in
by the user. Calibration constants can be stored in
the 2817 with a smart interface for a robot's axis of
movement. Movement constants, compensation
algorithms and learned axis characteristics would
be included. In programmable controllers and data
loggers, configuration parameters for polling time,
sequence and location, can be stored in the 2817.
Additional applications include accumulated totals
for dollars, energy consumption, volume and even
the logging of service performed on computer
boards or systems.
The Intel 2817 is cost effective for lower density
E2 PROM applications and can therefore be used
to provide a lower system cost to the user. Figure
8 shows the system cost of the 2817 compared to
the 2816. It can be seen that for low density ap. plications the 2817 is cost effective to use. At
higher densities the 2816 may be more cost effective because support costs are amortized, or
Applications
The Intel 2817 is ideal for non-volatile memory requirements in applications requiring storage of user
defined functions, calibration constants, configuraVee
I
MNIMX
101M
Ri5
WR
INTA
DT/A
ilEi'I
8088
ALE
~
AOr)-AD7
As-A,,,
"v-
INTR
ADDRESS
8282
~
QOE
~.}
I
T
-"
8286
.
r--------r-.
t:
8205
~~F-----;)
DATA
~~ L
"
/
c
·
IR7 ·
IRe
I--
8259A
PROGRAMMABLE 1R6
I--
EN
CI~J¥=~~~JR
INT
.
f-~
r-- -- -- ---- -- -- ----I
~I
V
I
I
I
WE OE CE
Dn- 0 7
Ap-A'I
Vpp
L - ROY/BUSY
Vee
2817
Te
5800pF
1
I...L.
2817 INTERFACE""
rr-
I
21V 1
5V
GND~
-=-
I
I
I
I
I
-----------------~
Figure 7. 2817/8088 Interface Example
5-131
AFN...Q21 01 A
2817
TOTAL SUPPORT COMPONENT COST REQUIRED
0%
100%
30"/e>
:;;
o
~
5-24 VOLT
CONVERSION
o
~
PULSE SHAPING
INTERFACE LATCHES,
TIMERS AND LOGIC
~
...'"
~
1-010 1 - - - - - - - - 2815 REQUIRES 100"10 -------.lo~1
1-0101--------2816 REQUIRES 1 0 0 " 1 0 - - - - - _ 0 1
I·
DENSITY
Figure 8. Total E2 System Cost
spread over, many devices-thus reducing overall
system cost. The 2817 user will find that tangible
cost savings per system include: board space and
component reductions, reduced assembly costs,
savings in inventory costs, handling costs and
Quality Assurance. The designer will find the 2817
reduces design time by a sizeable factor over the
2816 due to the integration of timing, logic, latching
and Vpp shaping circuitry.
The 2817 will also open up new applications in environments where flexible parameters/data
storage could not be implemented before. For example, applications with board space constraints
are ideal for the 2817 as it needs only 25% of the
board space required by the 2816 and 2815. This is
due to the on-Chip integration of all functions required except for the Vp p generator. Figure 9
shows the reduction in support component costs
using a 2817 over a 2816, 2815. Figure 10 illustrates the system board space requirements of
the 2817, 2816, and 2815.
Write Time Characteristics
01
2817
REQUIRES
3()<>A.
Figure 9. Support Components Cost Requirements
for E2 PROMs
~ 200
Z
::>
w
() 1.50
1f
l!la:
g 100
III
~
~
w
a:
75
50
25
2K
4K
5K
8K
10K
12K
14K
DENSITY (BYTES)
Figure 10_ System Board Space Requirement
(typical) erase followed by a 5 ms (typical) write. The
total cycle is then typically 10 ms. This cycle is the
time that Ready is held low by the deviqe. The 2817
maximum specification is 75 ms, 37.5 ms for erase
and 37.5 ms for write.
The 2817's internal write cycle contains an automatic
erase feature. The 2815 and 2816 do not have this
capability-they must be given an external erase
cycle prior to a write. The 2815 has a write time
specification of 50 ms minimum-that is, the device
can not be written or erased any faster than 50 ms.
The 2816 has a specifiqation of 9 ms. Typically,
these devices will write in times less than 50 or 9
ms, but the worst case bit defines the minimum
specification.
For special applications requiring faster worst case
write times, the 2817-W provides a complete byte
write (including erase) within a maximum of 20 ms.
This compares to a 75 ms maximum for the standard
2817.
The 2817, however, automatically qetermines when a
byte has been successfully written and therefore,
average write times are significantly faster. The
2817's internal cycle consists of an automatic 5 ms
To summarize, because of rapid on-average write/
erase times, and sophisticated internal control, the
2817 will write on average in 10 ms. This compares
with 18 ms for the 2816 and 100 ms for the 2815.
A write operation to a typical byte location is completed within 10 ms for both the 2817 and 2817-W.
5-132
AFN-02101A
inter
2817
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ............. -10°C to +80°C
Storage Temperature ............... -65°C to +100°C
All Input or Output Voltages with
Respect to'Ground ................... +6V to -.3V
Maximum Vpp Voltage ..................... 22.5V DC
"NOTICE: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and function'll operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification
is not implied. Exposure to absol/Jte maximum rating conditions for extended periods may affect device reliability.
D.C. AND A.C. OPERATING CONDITIONS DURING READ AND WRITE'
2817,2817-3,2817-4
Temperature Range
O°C-70°C
Vee Power Supply(3)
5V ± 5%
Vpp Power Supply(1) (4)
21V ± 1V
Timing Capacitor
5600 pF ± 10%
D.C. CHARACTERISTICS
READ
Symbol
Parameter
Min.
Typ(S)
Max.
Units
Test Conditions
III
Input Leakage Current
10
/LA
Vln = 5.25V
ILO
Output Leakage Current
10
/LA
VOut = 5.25 V
100
150
leeA
Vee Current (Active)
mA
OE = CE = Vil
Ices
'Vee Current (Standby)
70
mA
CE = VIH
IpPR
Vpp Current (Read and
Standby)
8
mA
Vpp = 22V
Vil
Input Low Voltage
-0.1
.8
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
Vee+ 1
.45
2.4
V
V
IOl = 2.1 mA
V
IOH = -400/LA
'---.
WRITE
Symbol
Parameter
Min.
Typ.(S)
Max.
Units
22
V
Vpp Current (Write)
15
mA
RDY/BUSY
= VOL
Vee Current (Write)
150
mA
RDY/BUSY
= VOL
Vpp
Write Voltage
Ippw
leew
/
20
5-133
Test Conditions
AFN·02101 A
2817
CAPACITANCE
(TA = 25°C f = 1 MHz)
Symbol
Typ.(S)
Parameter
Max.
Units
10
pF
VIN = OV
10
pF
VOUT = OV
500
pF
OE = CE = VIH
pF
OE = CE = VIH
CIN
Input Capacitance
GoUT
Output Capacitance
CVcc
VCC Capacitance
CVpp
Vpp Capacitance
50
5
,
Test Conditions
A.C. TEST CONDITIONS
Output Load ........... 1 TTL gate + Cl = 100 pF
Input Pulse Levels ................... 0.45 to 2.4V
Timing Measurement
Reference Level ................. Input 1V and 2V,
Output .BV and 2V
A.C. CHARACTERISTICS
READ
Symbol
Parameter
2817 Limits
Min. Typ..cS) Max.
tACC
Address to Output
delay
tCE
CE to Output Delay
tOE
Output Enable
to Output Delay
tOF
Output Enable
High to Output Float
tOH
Output Hol ....
BUBBLE
DETECTOR
INPUT
TRACK
OUTPUT
TRACK
t
t
~-
~(
LOOP 3
~(
LOOP 2
~)-
~(
LOOP 1
~-
BUBBLE
GENERATOR
\
Figure 6.
Block-Replicate Architecture
6·6
WRITING DATA INTO THE BUBBLE MEMORY
Seed Bubble
The seed bubble, at the beginning of the input track, is generated by an electric current pulse in a hairpin-shaped loop of conductive material. The pulse is strong enough to reverse the bias field locally and thus allow a bubble domain to be created.
Once having been created, the seed bubble remains in existence as long as the external bias field is maintained.
The seed circulates under a permalloy patch, driven by the rotating field that-propagates bubbles elsewhere in the memory.
This bubble is constrained to a kidney shape by interaction of the bias and rotating field with the metal patch (Figure 7).
The seed is split in two by a current pulse in the hairpin-shaped conductor. One of them remains under the patch as the seed,
quickly regaining its original size; the other one, driven by the rotating field, is transferred to the input track section of the
chip. The current pulse that splits the seed is generated to store a binary I in the memory; to store a 0, the pulse is omitted, and
no bubble is generated.
PERMALLOY
PATCH
BUBBLE
SPLIT SEED
DIRECTION
OF CURRENT
PULSE
AL-CU
CONDUCTOR
INPUT
TRACK
Figure 7.
Seed Bubble and Bubble Generation
A seed bubble is maintained at one end of the input track. Bubbles corresponding to binary I's in the input word are split
from the seed and propagate along the input track. When the input track contains exactly one page (64 bytes) then the bubbles
exchange places with old bubbles previously circulating in the loops. This is accomplished by an operation called swapping.
Thereafter the new bubbles circulate, while the old bubbles now in the track propagate to the end and are destroyed.
6-7
Swapping
Transfer of data from the input track to a storage loop involves a swap, bringing the old data onto the input track for destructionat the end of the line, while the new data takes its place in the loop. This is done whena current pulse in an associated conductor under the chevrons causes a bubble to jump from the input track to the storage loop and vice versa. The swap pulse is
essentially rectangular, preserving the bubble without cutting it in two.
OUTPUT
TRACK
o
SWAP
GATE (A)
Figure 8.
REPLICATE
GATE (8)
Swapping and Replication ConfIguration in Bubble Memory
READING DATA STORED IN THE BUBBLE MEMORY
To read the stored data, the circulating bubbles are replicated, one bubble or one unoccupied bubble site from each loop, onto
the output track, after which they propagate to a bubble detector at its far end. Mter detection, these output bubbles are also
destroyed. Meanwhile, the data in the loops continues to circulate, permitting a particular page to be read out repeatedly
without regeneration, and protecting the stored data if power fails.
Replication
Data is transferred from the storage loop to the output track by replication, continuing to circulate in the loop after having
been read out.
For replication, the bubble is propagated under a large element where it is stretched out. As it passes under a hairpin shaped
conductor loop it is cut by a current pulse just as in bubble generation.
The replicating current pulse waveshape has a high, narrow leading spike for cutting the original bubble in two, and a lower and
wider trailing portion during which the new bubble moves under the output track. The entire pulse lasts about one-quarter of a
cycle of the rotating field. In this manner the data in the storage loops is replicated onto the output track, and yet retained in the
storage loops in case of a sudden power failure.
Near the end of the output track is a bubble detector-essentially a magnetoresistive bridge formed by interconnecting the
permalloy chevrons to make a continuous electrical path of maximum length (Figure 9). As bubbles pass under the bridge, the
resistance changes slightly, modulating the currents through the bridge and creating an output voltage of several millivolts.
Bubbles are stretched at right angles to the direction of propagation by adding parallel rows of chevrons; these stretched bubbles
generate larger output signals at the detector. Beyond the detector, the output track runs the bubbles into the guard rail and
destroys them.
6-8
MAGNETORESISTIVE
DETECTOR
0
0
0
0
~o
~
~
~
~
~
OUTPUT
TRACK
Figure 9. Bubble Detection
Redundancy
The Intel magnetic bubble memory unit physically stores data in 320 storage loops, with capacities of 4,096 bits each. Of the
320 loops, 272 are actually used (active) and 48 are spares (inactive); the boot loop records which loops are used.
Boot Loop
Some of the loops of an individual memory are set aside as spares. The decision as to which loops are to be used (active) and
which are not to be used (inactive) is made after the memory unit has been assembled and is undergoing tests at thefactory.
The outcome of this decision is stored in an extra loop included in each memory chip, in the form of a 12 bit code for each
"active" and "inactive" loop.
Whenever power is turned on in the memory system, the system must be initialized before it can be used. Part of the initialization process inc1udesreading the contents of this extra loop, called the boot loop, and placing this information in a bootloop
register in the formatter/sense amplifier. From then on, as long as power is on, this register identifies the "active" loops for
both reading and writing; "inactive" loops are ignored. The formatter does not attempt to store data in "inactive"loops, and
the sense amplifier ignores any data that appears fr~m these loops.
Data Storage-External Appearance
Data is stored logically as 2,048 pages of 512 data bits each. 256 data bits plus 14 error-correction check bits and 2 unused bits
are stored in each half of the bubble chip. If automatic error correction is not used, these 16 bits are available for data storage.
Error Correction
Error detection and correction can be performed in the formatter / sense amplifier, which includes a 14-bit cyclic redundancy
code that corrects a single burst error of up to five bits in each 270-bit block including the code itself. These code bits are
appended to the end of each 256-bit data block when writing into the cell, and checked when the block is read. The error correction feature can be used or not at the user's discretion, by properly setting a register in the bubble memory controller chip.
If it is not used, the loops occupied by the code bits become available for additional data.
6·9
inter
Access Time and Data Rate
Bubbles circulate at a rate of 50 kilohertz (the rotating field makes 50,000 complete revolutions per second). Average access
time to the first bit of the first page is about 41 milliseconds-half the length of time required for a bubble to make one complete circuit of the loop, plus the time to shift a bubble along the length of the output track.
The 320 active and spare loops are actually in four "quads" of 80 loops each (Figure 10). This arrangement shortens the
input-and output tracks and thus reduces the read and write cycle times. The quads are separately addressable in pairs; in each
pair the quads store odd-numbered and even-numbered bits of a word respectively. There are four seed bubbles and four
input tracks, and four output tracks. The four output tracks share two detector bridges in such a way that there can never be
bubbles from two tracks in a single detector simultaneously. By this means the four streams of output bubbles are interleaved
into two bit streams that are stored in two registers in the sense amplifier. The data in these registers is interleaved again into a
single stream transmitted serially to the controller.
+12V
BRIDGE OUTPUT
.... DETECTOR (ODD)
OUTPlIT TRACK
OUTPUT TRACK
"
REPliCATE
GATE
. / SWAP
GATE
.+H+----+t-1'
INPUT TRACK (ODD QUAD)
INPUT TRACK (EVEN QUAD)
Figure 10. Organization of Bubble Memory (One-Half Chip)
SPECIFIC·STRUCTURES OF A MAGNETIC BUBBLE MEMORY
A magnetic bubble memory system consists of a controller and up to eight I-megabit magnetic bubble subsystems. A minimum system has a controller and one subsystem. The subsystem comprises one magnetic bubble unit in which the data is
actually stored, and the peripheral units listed in Table 2 and diagrammed in Figure II. These circuits are described later
in this primer.
6-10
inter
Table 2. Components of Intel Bubble Memory System
CONTROLLER
SUBSYSTEM
Memory
7220-1 Bubble Memory Controller
(for I to 8 subsystems)
7110 Magnetic Bubble Unit
Peripheral Units
7242 Formatter/Sense Amplifier
7230 Current Pulse Generator
7250 Coil Predriver
7254 Drive Transistor Assembly
(2 required per subsystem)
BUaBLE
MEMORY
CONTROLLER
(8Me)
TO
ADDITIONAL
BPK70's
Figure 11. Minimum Magnetic Bubble Memory System, Shaded Portion is Bubble Subsystem
SUPPORT CHIPS
Five semiconductor integrated circuits are necessary to support each bubble chip. These components are described in some
detail in the following paragraphs. In addition, each bubble memory system requires a controller, a separate integrated circuit
described later.
Formatter/Sense Amplifier (FSA)
Serial data to be stored in or read from the bubble memory passes through the FSA. The FSA keeps track of which loops in
the bubble memory are spares, executes the error correction coding and decoding if it is implemented, and shifts data to the
bubble memory input tracks or from the output tracks, amplifying the output signals from the memory.
6-11
intJ
The FSA has a chip-select input, which is normally grounded (permanently enabled). However, each FSA drives the chipselect input of other circuits associated with the same bubble chip, so they are all enabled at the proper time.
Current Pulse Generator (CPG)
All signals except those that control the rotating field originate in the CPG. This device is the source of a current pulse that
cuts a new bubble from the seed bubble whenever the FSA has a binary I to be stored. Later, when this bubble reaches the
loop in which it is to reside, the CPG issues the signal that swaps it with the bubble or non-bubble previously stored in that
location of the loop. When data is to be read, the bubble is replicated on the output track by still another signal from the CPG.
Coil Predriver (CPO)
Four digital signals (positive and negative versions of both X and Y waveforms) are sent to the CPD from the controller with
appropriate durations and phases to control the rotating field that moves the bubbles in the memory. The CPD combines and
inverts these to form eight pulsed outputs that are amplified in a separate transistor package to drive the coils surrounding the
bubble chip with a triangular current waveform.
Photo 2. The Minimum Magnetic Bubble Memory System
Including Controller
CONTROLLER
The bubble memory controller is the interface between the memory system and the equipment it serves. It converts serial data
to 'parallel and parallel data to serial, and generates all timing signals required by the other support circuits in the bubble
memory system. It can control up to eight bubble subsystems, for a total of a megabyte of memory.
Internal storage on the controller includes a first-in-first-out buffer with a capacity of 40 bytes. This buffer stores data to be
sent serially to the FSA orjust received from the FSA on one side, and data to orfrom the parallel bus served by the bubble
memory on the other. It also serves as a speed matching device between the user at the parallel bus and the FSA which must
transfer data to and from the bubble device at exactly the rotating field ratio in each channnei.
6-12
GLOSSARY
Bias field-a magnetic field perpendicular to a magnetic thin film that maintains conditions necessary to support formation
of magnetic bubbles in the film.
Boot loop-in a magnetic bubble memory with serial! parallel! serial architecture and redundant loops, a special loop containing information that identifies which loops are active and which are inactive, as determined by factory test. This loop also
contains the information necessary to synchronize the bubble memory page locations with the controller after power up.
Bubble, magnetic-a cylindrical magnetic domain in a thin film of orthoferrite or garnet. When viewed from above, the cylindrical shape appears spherical, hence the name "bubble." A bubble represents a binary I in most magnetic bubble memories.
Chevron-one of many possible shapes for a magnetic pattern deposited on a thin film to steer bubbles ina desired direction.
Asymmetric chevrons are used in Intel memories.
Detector-a means of distinguishing bubbles from non-bubbles (I s from Os) when a word is read from the bubble memory.
Domain, magnetic-a small region of a ferromagnetic substance that contains many similarly oriented atoms, so that the
region as a whole is magnetized in that direction.
E1PROM-an acronym for electrically erasable programmable read-only memory, which is a memory component that,
though nominally read-only, can accept changes to any work stored in it by electrical means, but at substantially slower speed
than that at which stored words are read.
EPROM-an acronym for erasable programmable read-only memory, which is a memory component that, though nominally read-only, can be completely erased, usually by exposure to ultraviolet light, and then reloaded with new information, but
at substantially slower speed than that at which stored words are read.
Ferrite-any of several compounds of iron, oxygen, and another metal, with magnetic properties that are useful in certain
microwave applications and in computer memories.
Field, magnetic-a region of space in which a magnetic force exists and can be measured.
Gamet~a naturally occurring silicate mineral sometimes used in jewelry. Synthetic garnets with the same crystal structure
can be made of oxides of iron and yttrium or one of the rare earths. Gamet is the preferred material for the thin magnetic film
in a bubble memory.
Input track-a series of magnetic metal patterns that control the movement of bubbles in a thin film, and thereby lead them
from a bubble generator toward one or more storage patterns.
Ion implantation-a process involving accelerators, similar to the machines used by nuclear physicists, for depositing dopants
on and just below the surface of an electronic component; used to alter the physical properties of the material.
Latency-a delay between a request to read or write data in a memory and the actual beginning of the operation, imposed by
a requirement for the address to move physically (but not necessarily mechanically) to a point where the data transfer can
take place.
Magnetization vector-an expression of the magnitude and direction of a magnetic field at a point in space.
Magnetoresistance-a change in electrical resistance due to the presence of a magnetic field.
6-13
Major loop-in a magnetic bubble memory, an endless loop containing a bubble generator, a bubble detector, and/ or a
bubble annihilator, through which data is read or written, and which transfers bubbles to or from one or more minor loops
(q. v.) in which they are stored. In some designs the major loop is not endless, and all bubbles not transferred out of it collapse
when they reach the end. In these cases the major loop becomes an input or output,track (q.v.).
Minor loop-in a magnetic bubble memory, an endless loop in which bubbles are stored, having been transferred into it from
a major loop or input track (q.v.) and accessible by transfer into a major loop or output track (q.v.).
Non-Volatility-a property of some memory technologies that retains the integrity of stored data when power is turned off.
Orthoferrite-one of several oxides of iron and either yttrium or a rare earth. The molecular structure is simpler than that of
garnet (q. v.). Orthoferrites were the first materials used for the thin magnetic film in experimental bubble memories, but have
yielded to garnets, which have more desirable properties-notably ease of prepanltion as thin films with the necessary
magnetic characteristics.
Output track-a series of magnetic metal patterns that control the movement of bubbles in a thin film, and thereby lead them
from one or more storage patterns toward a bubble detector.
Permalloy-an easily magnetized and demagnetized alloy of nickel and iron.
PROM-acronym for programmable read-only memory-a read-only memory whose content is loaded by the user after
delivery, as opposed to read-only memories whose content is fixed during manufacture. Once loaded, the data in a PROM is
not alterable.
Pseudo-random acceSs--a property of some memory technologies in which the time of access to blocks of stored data is
largely (but not necessarily entirely) independent of the position of the block in the storage medium, but in which the time of
access to bits, words or other entities depends on the position of that entity within the block.
Random access---a property of some memory technologies in which the time of access to any stored bit, word, or other entity
is wholly independent of that entity's position in the storage medium.
Saturation-a state of magnetization of a material by a field such that, if the field is increased, the magnetization of the material does not increase and the magnetic flux density increases in proportion to the field (having increased much more rapidly in
weaker fields).
Seed-a permanent bubble in a magnetic bubble memory, from which other bubbles are cut to represent stored binary Is.
Serial access---a property of some memory technologies in which the time of access to any stored bit, word, or other entity
depends strongly on that entity's position in the storage medium.
Thin mm-any film of material deposited on a suitable substrate to take advantage of the material's special properties when
dispersed as a film. Thickness ranges usually from about 10-9 to 10-6 meter, and occasionally to 10-5 meter or more, as in
bubble memories.
T -I bar-one of several possible shapes for a magnetic pattern deposited on a thin film to steer bubbles in a desired direction,
consisting of shapes like the letter T and the letter I alternately along a track. This pattern was used extensively in early bubble
memory designs, but is no longer generally employed.
6-14
intJ
APPLICATION
NOTE
Ap·119
December 1982
ORDER NUMBER: 210367-002
6-15,
INTRODUCTION
To date, a major obstacle in the implementation of
bubble memories in systems has been the inherently complex control requirements imposed
by the bubble memory devices themselves. With
the advent of Intel's BPK 72 bubble memory prototype kit, a design engineer can immediately
realize the benefits of non-volatility, form factor,
density and reliability without the complex control
concerns. This application note provides
additional background on the operating
characteristics of the BPK 72 and is intended to
further ease the design effort required in the implementation of bubble memory systems.
OVERVIEW
This application note provides an example of Bubble Memory system implementation using the
BPK 72 and an Intel 8086 microprocessor. Before
looking at this example, some explanation is
necessary as to how this implementation was attained and how a user can take advantage of the
principles involved.
6-16
Ap·119
As an introduction, the basic architecture of the
BPK 72 is reviewed followed by an explanation of
the operating characteristics of the BPK 72 kit as
a whole and of the 7220 Bubble Memory Controller. Once the building blocks .are in place, a
detailed account of the implementation of a bubble memory kit is offered. The final section, which
involves the. actual implementation of the BPK 72
and an SDK-86, completes the application note.
The 7250 and the two 7254s supply the drive currents for the in-plane rotating magnetic field (X
and Y coils) that move the magnetic bubbles
within the MBM. The 7230 supplies the current
pulses that generate the magnetic bubbles and
transfer the bubbles into and out of the storage
loops of the MBM.
The 7242 accepts Signals from the bubble detectors in the MBM dtJring read operations, buffers
the signals and performs data formatting tasks
that include the transparent handling of bootloop
information. During write operations, the 7242
enables the current pulses of the 7230 that cause
the bubbles to be generated in t~e 7110 MBM.
Automatic error detection and correction of the
data can be performed by the 7242.
BUBBLE SYSTEM OVERVIEW
A block diagram of the Intel Magnetics 128K-byte
system is shown in Figure 1. The support circuitry
used with one 7110 magnetic bubble memory
(MBM) in the BPK 72 kit consists of the following
integrated circuit components: one 7250 Coil
Predriver, two 7254 Quad VMOS Drive Transistor
packs, one 7230 Current Pulse Generator, and one
7242 Formatter/Sense Amplifier. The 7220 Bubble
Memory Controller (BMC) completes the basic
system.
-
The 7220 provides the user interface, performs
serial-to-parallel and parallel·to-serial data conversions, and -generates all timing signals necessary
for the proper operation of the MBM support circuitry.
8086 BUS
t
7220
SUBBLE MEMORY CONTROLLER
COIL PRE DRIVER
7250
r+
"'"
l
l
DRIVE
TRANSISTORS
FORMATTER!
SENSE AMP
...
l
II
DRIVE
TRANSISTORS
l
INTEL MAGNETICS
7242
BUBBLE
MEMORY
...
1110
.I
'-1
~ ~
...l
7230
CURRENT PULSE
GENERATOR
I
J
Figure 1. Block Diagram of the 128K Byte Magnetic Bubble Memory System
6-17
AP·119
8°fUS
I
7220 CONTROLLER
BUBBLE MEMORY
I
~
7250 (CPO)
COIL
PREDRIVER
...
...
DRIVE
TRANSISTOR
VMOS (2·7254)
-
FORMATTER/SENSE AMP
I
7242
..
-
II
-
INTEL
MAGNETICS
BUBBLE
MEMORY
7110
...
-
. I 7230 (CPG)
'j CURRENT
PULSE
GENERATOR
r--
1 MEGABIT BUBBLE STORAGE UNIT
•
• •
I I I
1 MEGABIT BUBBLE STORAGE UNIT
~
r
••• ••• ••• •••
••
•
II
'.
1 MEGABIT BUBBLE STORAGE UNIT
~
Figure 2. Bubble Memory System Expansion up to One Megabyte
Figure 2 shows how larger systems can be built
from the basic components. A Bubble Storage
Unit consists of one 128K·byte MBM and the five
support chips shown. The components needed for
one MBM cell are available as the BPK 70 kit.
Larger systems can be constructed from the components supplied with one BPK 72 kit (which in·
cludes the 7220 controller) and one or more BPK
70 kits. For example, a one megabyte system can
be assembled from one BPK 72 kit and seven BPK
70 kits. No additional TTL parts are required when
building multibubble systems with up to eight
MBMs.
One 7220 is capable of controlling up to eight Bubble Storage Units simultaneously. Larger systems
can be configured with multiple 7220's and addi·
tional Bubble Storage Units.
Functional Organization of the
7110 Bubble Memory
The Intel Magnetics 7110 Bubble Memory utilizes
a "major track/minor loop" architecture. With this
architecture, if a binary 1 is to be written, a "seed
bubble," always present in the 7110, is split in
two. One bubble remains at the generator as the
6-18
Ap·119
seed, and the other is propagated down the input
(major) track. If a 0 is to be written, the seed bubble is not duplicated. The data generated is sent
down the input track, in serial, until it is aligned
with the "swap" gates at the minor loops of the
device. The new data is then swapped into the
minor loops in parallel at the same time the old
data is swapped out to the major track.
Table 1. 7110 Loop Operation
To read data from the 7110, data is rotated in the
minor loops until it is positioned at the "replicate"
gates opposite the output track. On receipt of a
replicate signal, the data in the minor loops is
duplicated by splitting the bubbles. The original
data remains in the minor loops, and the duplicate
data is clocked down the output track where the
detector elements of the bubble memory operate
to transform the presence or absence of a bubble
into small electrical signals that are converted into digital '1' and '0' signals in the 7242 FSA.
With the 7110, the process of reading data from
the minor loops by simultaneously splitting all of
the bubbles in a page is known as "block
replicate." The advantage of the block replicate ar·
chitecture is that the data currently stored in the
minor loops is not compromised during a read
operation; the data to be read never leaves the
minor loops. This architecture can be contrasted
with earlier architectures that required the data to
leave the minor loops, be detected and then
returned to the minor loops. In the event of a
power failure, bubble systems not utilizing the
block replicate architecture could suffer a loss of
data during a read operation; the data being sensed would not be returned from the major loop to
the minor loops.
abcde
abcde
abcde
abcde
00000
00011
00000
00000
11111
00000
00000
00000
10110'
00011
00000
0000011111
00000
00000
00000
10110'
00000
00000
00000
11111
00000
00000
00000
10110'
00000
00011
00000
11111
00000
00000
00000
10110·
00000
00011
00000
1.2
1.3
1.1
1.4
• "" page zero
The 7110 MBM actually contains 320 minor loops,
of which 272 must be good. The additional 48
loops provide 15% redundancy. This redundancy
factor allows some of the loops in the 7110 to be
bad while maintaining a completely functional
one megabit device. A map of the good and bad
loops is placed on the label of the 7110 and is also
~(
LOOP 272
~(
LOOP 271
~)-
..,)--
BUBBLE
DETECTOR
INPUT
TRACK
OUTPUT
TRACK
With the 7110 MBM, there are 2048 pOSitions for
the data within a minor loop. To move the bubbles
in the MBM, a magnetic field is induced and
rotated in the plane of the 7110. As the field is
rotated 360 degrees, every bubble is moved ahead
one position, and all of the bubbles maintain the
same pOSition relative to one another. All of the
bubbles in similar positions in the loops are referred to as a "page."
t
t
By way of illustration, suppose the bubble is made
of five minor loops (a,b,c,d,e) capable of holding
nine pages of data (Table 1). During four 360
degree "rotations" of the in·plane magnetic field,
the nine pages of data shift four pOSitions
(1.1, 1.2, 1.3, 1.4).
BUBBLE
GENERATOR
~(
LOOP 3
~(
LOOP 2
~(
LOOP 1
5>..,)j) ...
Figure 3. Functional Organization of the 7110
6-19
AP·119
encoded and placed in the boot loop of the device
as it is tested. This map, the bootloop, consists of
forty bytes of data. Each good loop in the 7110 is
represented by a one, each bad loop by a zero.
When the system is initialized, the 7220 BMC
reads the bootloop from the 7110 and decodes it.
The bootloop is then automatically placed in the
bootloop register of the 7242. The boot loop
register serves as a working 'map' of the 7110 for
read and write operations.
'
With the pages of data rotating around the minor
loops, there must be a mechanism to orient the
device and to assign a starting address to a page.
The mechanism used to identify page zero involves the bootloop that resides on the 7110. Page
zero (or address zero) is defined as the position of
the 7110 after the boot loop has been read by the
7220 controller. Thus, each time the host CPU
sends an "initialize" command, the bootloop is
read by the 7220, and the 7110 is queued at page
zero. From this point, any desired page in the bubble can be obtained by the controller.
Data Flow Within the Bubble Memory
System
To better understand the relationship between the
7110 MBM and its support circuitry, the data flow
within the bubble system during a read operation
is examined. During the read operation, bubbles
from the storage loops are replicated onto an output track and then moved to a detector within the
MBM. All movements within the MBM occur under
the influence of a rotating magnetic field; the
number of rotations and the rotation timing are
under the control of the 7220 BMC. The detector
outputs a differential voltage according to
whether a bubble is present or absent In the
detector at any given time. This voltage is fed to
the detector input of the 7242 Formatter/Sense
Amplifier (FSA).
The data path between the 7110 MBM and the
7242 FSA consists of two channels (channel A and
channel B) connected to the two halves of the
MBM. When data is written, the bit stream is divided with half of the data going to each side of the
MBM. During a read operation, data from each half
of the MBM goes to the corresponding channel of
the FSA. In the FSA, the sense amplifier performs
a sample-and-hold function on the detector input
data, and produces a digital 0 or 1. The resulting
data bit is then paired with the corresponding bit
in the FSA bootloop register.
If an incoming data bit is found to be from a good
loop (a corresponding "1" in the FSA boot loop
register), it is stored in the FSA FIFO; otherwise, it
is ignored. This process continues until both FSA
FIFOs (channels A and B) are filled with 256 bits.
Error detection and correction, if enabled by the
user, is applied to each block of 256 bits at this
point. If error correction is not enabled, 272 bits of
data can be buffered in each FIFO.
As data leaves the 7242 FSA, the bit patterns buffered in each of the FSA FIFOs is interleaved and
sent to the 7220 BMC in the ,form of a serial bit
stream via a one-line bidirectional data bus (010
line). In the 7220 BMC, the data undergoes a serialto-parallel conversion and is assembled into bytes
that are buffered in the 7220 FIFO. It is from this
FIFO that the data is written onto the user inter- '
face.
COMMUNICATING WITH THE 7220
The CPU views the 7220 BMC as two input/output
ports on the bus. When the least-significant bit of
the address line is active (AO = 1), the command/status port is selected. When the leastsignificant bit of the address line is inactive
(AO = 0), the bidirectional data port is selected. In
order to define the operations on these ports, it is
necessary to understand something of the internal organization of the 7220 Bubble Memory Controller.
For simplicity, the user need only view the 7220 as
containing a 40-byte FIFO and a collection of 8-bit
registers. The FIFO is a buffer through which data
passes on its w'ay from the 7242 Formatter/Sense
Amplifier (FSA) to the user, or from the user to the
FSAs. The primary purpose of the FIFO is to
reconcile differences in timing requirements between the user interface to the 7220 controller and
the controller interface to the FSAs.
The six 8-bit registers internal to the 7220 are loaded by the user prior to any operation of the bubble
system and contain information regarding the
operating mode of the 7220. Loading the 7220
registers before any commands are sent is similar
to passing parameters to a subroutine prior to invocation, hence, the registers are often referred to
as "parametric registers."
Data transferred between the CPU and the 7220
FIFO and parametric registers takes place over an
8-bit data port. The choice as to whether the data
is destined for the FIFO or the parametric
registers, however, is made through the command/status port. In one case, the' actual commands that cause some operation to take place,
such as a read or write, consist of a 4-bit code sent
by the CPU to select one of 16 possible commands. This 4-bit code occupies the low-order nibble (bits 0, 1, 2, and 3) of the command byte. The
command byte must also have bit 4 set to indicate
to the 7220 that a command is being sent. In the
6-20
AP·119
second case, another 4-bit code on the command
port (bits 0, 1, 2, and 3) is used to select either one
of the parametric registers or the 7220 FIFO. As
shown in Table 2, if bit 4 of the command byte is
set to zero, the value of the low·order nibble is
taken to be a pointer value that specifies a
parametric register or the 7220 FIFO. This pointer
is referred to as the "Register Address Counter"
(RAG).
Table 3. Register Address Counter Assignments
Register Name
Table 2. Command Port Function
FUNCTION
Command
RAC
07
0
0
06
0
0
05 04 03
0
0
1
0
C
R
02
C
R
01
C
R
00
D7 D6 D5 D4 D3 D2 D1 DO
Readl
write
Utility Register
0
0
0
0
1
0
1
0
R/W
Block Length
Register (LSB)
0
0
0
0
1
0
1
1
W
Block Length
Register (MSB)
0
0
0
0
1
1
0
0
W
Enable Register
0
0
0
0
1
1
0
1
W
Address Register
(LSB)
0
0
0
0
1
1
1
0
R/W
Address Register
(MSB)
0
0
0
0
1
1
1
1
R/W
7220 FIFO
0
0
0
0
0
0
0
0
R/W
C
R
Once the FIFO has been selected, the RAC stops
incrementing and continues to point to the FIFO
until changed by the user software. This sequence
minimizes the number of instructions necessary
for a given transaction and aids in establishi·ng a
protocol to ensu re that all of the necessary i nformation is sent to the controller. The user,
however, is not bound to follow this automatic sequence. Each parametric register may be selected
and loaded in any order; specific registers may be
updated where needed, but in each case, the host
software must explicitly name the register to be
loaded. Until a user is familiar with the bubble
system, it is recommended that the autoincrementing feature be used.
RAC values that may be sent out on the command
port and the corresponding register names are illustrated in Table 3. The RAC points to, or selects,
six unique registers and the 7220 FIFO. Once a
RAC value is sent by the CPU to the 7220 via the
command port, the next read or write operation to
the data port transmits data to or receives data
from the register addressed. Notice that the six
registers have values that are in ascending order
starting at OAH and that the FIFO has a value of O.
The reason for this ordering is due to the autoincrementing feature of the RAC; once the first
register is selected, each subsequent byte of data
on the data port causes the RAC to be
automatically incremented and to point to the
next register in the sequence. Once the mostsignificant byte of the Address Register has been
loaded, the RAC value automatically rolls over
from OFH to 0 and paints to the 7220 FIFO. The
system is now in position to transfer data to or
from the FIFO without the user code explicitly
pointing to the FIFO.
It is important to remember that once a command
has been given to the 7220 BMC, the parametric
registers must not be updated until the Status
byte indicates that the operation. is complete. The
parametric registers are, in effect, working
registers for the controller during the execution of
a command. For example, during a Read or Write
operation, the Block Length Register, which contains the terminal page count for the operation, is
decremented by the 7220. Similarly, the Starting
Address Register,' which initially contains the
starting page for an operation, is incremented by
the controller as each pa1;}e is transferred. Attempting to modify these registers during the operation
of a command causes the block count and add ress to be incorrect.
Addressing the Bubble Memory System
One of the interesting aspects of the,lntel Bubble
Memory System is its, inherent addressing flexibility. The user may treat a 7220 BMC with eight
6·21
AP·119
bubbles as a collection of 16K pages Of 64 bytes
each (addressing each bubble in turn) or as collection of 2K pages of 512 bytes each (addressing
eight bubbles' in parallel). Of course, tbere are a
variety of configurations in between these two extremes, each dictated by the user's need for
speed, power consumption, address space, and
cost. Control over the configuration is achieved at
run time via two of the parametric registers: the
Block Length Register and the Starting Address
Register.
The Block Length Register (BLR) is a 16-bit value
divided into two fields: the "terminal count" field
and the "channel" field. The bit configuration for
the BLR is as follows:
Table 4. Block Length Register
channel
CCCCXTTT
MSB
terminal count
-
T T T T T T T T"
LSB
The "terminal count" field ranges over eleven bits
and defines the total number of pages requested
for a read or write operation. With eleven bits in
the field, a user may request from one to 2048
pages be transferred (eleven bits of zero-indicate a
2048-page transfer). The width of the page is effectively defined in the "channel" field. This field
specifies the number of FSA channels that are to
be addressed. Recalling that each 7242 FSA has
two channels to communicate with one 7110 bubble memory, the legaL combinations in this field
address one channel (one half of a 7110), two, four,
eight, or 16 channels. These combinations
translate into page sizes of 32, 64, 128,256, or 512
bytes, respectively. (The one-channel mode of
operation is usually reserved for diagnostic purposes, and examples of its use will be illustrated
later.)
Table 5 shows the relationship between the
"channel" field and the number of FSA channels
selected. Notice that the channel field bits are encoded. A value of "0001" binary selects two FSA
channels: 0 and 1.
Table 5_ FSA Channel Select
Channel field (BLR MSB bits 7, 6, 5,4)
0000 0001
Number of
channels
selected:
0
0,1
0010
0,1,2,3
0100
1000
o to 7 o to F
Thus, a BLR value of "0001" in the high-order four
bits selects one bubble through channels 0 and 1
Similarly, a BLR value of "0010" selects two bub\ bles in parallel with a page size of 128 bytes. This,
however, is not the complete story. For example, a
value of "0100" in the BLR selects four bubbles in
parallel through channels 0 to 7. Suppose, that
there are eight bubbles in the system and that the
user desires to arrange the eight bubbles as two
sets of four. The mechanism to communicate
through channels 0 to 7 and channels 8 to F
resides with the Address Register (AR).
The Addres's Register contains a 16-bit value divided into two fields: a "starting address" field of
eleven bits and a "magnetic bubble memory
(MBM) select" field of four bits.
Table 6. Starting Address Register
MBM Select
starting _address
X"MM'MM'-AAA
AAAAAAAA
MSB
LSB
The eleven bits in the starting address field of the
AR are set by the user to indicate to the 7220 BMC
on which page of a bubble's 2048 pages the
transfer is to start. For example, if a read operation is to start at page 1125 and is to continue for
16 pages, the starting address field contains
1125, and a value of 16 is placed in the terminal
count field of the BLR. After each page is transferred, the starting address field is incremented and
the terminal count is decremented by the controller.
Continuing with the example of two banks of four
bubbles, notice in Table 7 that the MBM select
field is needed to switch between the two banks.
A value of "0000" in bits 3, 4, 5, and 6 of the highorder byte of the address register selects bank 0
or FSA channels 0 through 7; a value of "0001"
selects bank 1 or FSA channels 8 through F. Each
bank contains 2048 pages of 256 bytes.
6-22
AP·119
To operate eight bubbles serially, a user needs only to specify a value of "0001" once in the channel
field of the BLR and to begin with a value of
"0000" in the MBM select field. As page 204& is
written in the first bubble, the AR, managed by the
7220 controller, rolls over to 0 and updates the
MBM select field with no additional bit manipulation. In this case, the bubble system appears as
16K pages of 64 bytes each. Power consumption
is one-eighth of that consumed by operating eight
bubbles in parallel. However, the data rate is
limited to the data rate of one bubble.
rates, respectively. (If the error correction mode is
changed, the CPU must issue an Initialize command to the 7220 controller).
INTERRUPT ENABLE (NORMAL)
INTERRUPT ENABLE (ERROR)
lJJ~~~~~~~
MFBTR
WRITE
BOOTLOOP ENABLE
DMA ENABLE
ENABLE RCD
ENABLE ICD
ENABLE PARITY INTERRUPT
Table 7. FSA Channel SelectiMBM Select
MBM SELECT "CHANNEL FIELD" (BLR MSB bits 7, 6, 5, 4)
AR MSB BITS
(6,5,4,3)
0000
0001
0010
0100
1000
o0 0 0
o0 0 1
o0 1 0
o0 1 1
o1 o0
o1 o1
o1 10
o1 1 1
1 0 o 0
1 0 o 1
1
1
1
1
1
1
0
0
1
1
1
1
1 0
1 1
o0
o1
1 0
1 1
0
1
2
3
4
5
6
7
8
9
A
B
C
0,1
2,3
4,5
6,7
8,9
A,B
C,O
E,F
0,1,2,3
4,5,6,7
8,9,A,B
C,O,E,F
Figure, 4. Enable Register Definition
The interrupt capabilties of the 7220 are reflected
in the NORMAL, PARITY and ERROR INTERRUPT
bits of the ENABLE register byte. The 7220 controller is capable of issuing interrupts to a CPU at
the normal completion of an operation, if a parity
error is encountered between the 7220 controller
and the CPU, or if a data transfer error is found by
the 7242 FSA. Any (or all) of these conditions are
selected via the Enable register byte, and any
resultant interrupts are sent to the CPU via a
single INT line. At this point, the software must
examine the status register to determine the
cause of the interrupt. (An additional interrupt, the
FIFO half-full interrupt, is issued on the ORO pin
and is not controlled by the Enable byte).
One of the more difficult aspects of the ENABLE
register byte to understand is the operation of the
ERROR INTERRUPT bit (bit 2). This bit normally is
not used alone, but in conjunction with the
ENABLE RCO and ENABLE ICO bits of this
register. These three bits form combinations that
gate selected 7242.error conditions to the CPU.
For example, if, while operating under error correction, a user does not wish to be bothered by an
Interrupt that indicates an error has been corrected automatically by the system, a specific pattern of these three bits would be selected (100 or
010 from Table 8). If the user wishes to be notified
of all errors, another pattern would be selected
(011 or 101).
o to 7 oto F
8 to F
0
E
F
The Enable Register
The Enable register is the parametric register that
defines the various modes of operation of the
7220 controller. The data transfer mode (polled, interrupt driven, or OMA operation) is selected by
setting the appropriate bit in this register.
Likewise, the type of error correction to be applied
to the data is selected, based on the bits selected
in this register.
While the function of "each of the enable register
fields is described in the BPK 72 manual, some'of
the finer pOints and implications are detailed here.
Note that it is possible to completely change the
operating characteristics of the bubble system
through software control. A system can go from
the OMA mode with error correction enabled to a
system operating in polled 1/0 with no error correction enabled by altering the value of the Enable
register. Though most implementations will not
take advantage of this degree of flexibility, there
are cases where the Enable register is modified
during system operation. For example, the normal
interrupt and MFBTR bits can be modified between operations to change interrupt and read data
6-23
Ap·119
Table 8. Error Correction Combinations
Enable
ICD
Enable
RCD
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Interrupt
Enable
(ERROR)
0
1
0
1
0
1
0
1
Interrupt Action
No interrupts due to errors
Interrupt on TE only
Interrupt on UCE or TE
Interrupt on UCE, CE or TE
Interrupt on UCE or TE
Interrupt on UCE, CE or TE
Not used
Not used
The purpose of the ERROR INTERRUPT bit is not
to enable or disable error interrupts, but rather to
aid in selecting the type of error interrupt received
by the CPU. If any type of error correction is
selected, interrupts are enabled automatically.
The ENABLE RCD (read corrected data) bit causes
the error correction algorithm to be applied to the
data being transferred from the 7110 MBM in an
almost transparent manner. The RCD bit allows
the 7220 controller to send its own commands to
the 7242 FSA. These commands cause the FSA to
automatically correct and transfer to the controller, any data that is found to be in error and
that is considered correctable.
With only the RCD bit on, no interrupt is generated
if a correctable error is found. However, the user is
informed that a correctable error was encountered
and corrected during the data transfer via the 7220
status byte at the end of the operation. Uncorrectable and timing errors cause an interrupt to
, which the CPU must respond. With both the RCD
bit and ERROR INTERRUPT bit on, the CPU is
notified via an interrupt whenever a correctable,
uncorrectable or timing error is encountered.
The RCD mode of operation is suitable for
transfers where a GO/NO GO termination is sufficient. For example, when loading executable code
from the bubble to RAM, it is necessary to know
that the transfer was good (with errors corrected)
or aborted due to an uncorrectable error.
A retry of an uncorrectable page of data is accomplished by sending another Read cqmmand
without modifying the parametric registers. It may
be the case that the errors encountered were soft
(read) errors that may not be present on a retry.
Thus, what may have been detected as an uncorrectable error, may become correctable error (or
simply vanish) on a subsequent read of the offending page. In this case, the error correction ability
of the system corrects the errors automatically
without additional user intervention.
a
The advantage of the RCD mode of operation is
that error correction can be applied transparently
to the CPU except for uncorrectable conditions.
The disadvantage is that a page of uncorrectable
data is passed to the controller before the interrupt is sent. The software must have the ability to
clear the 7220 FIFO prior to rer~ading the offending page from the bubble.
If a given page continues to show up as having a
correctable error after a number of retrys, it is up
to the user's protocol to determine the action to
be taken. One protocol suitable for handling errors involves "scrubbing" the data. Suppose a
page appears with an error and, on retry, the error
is still present. If the error is correctable, the data
should be corrected and written back to the bubble and then read back into RAM. The probability
of encountering an uncorrectable error after the
first retry is 1 in 10". Data scrubbing after one
retry maintains this level of reliability.
The ENABLE ICD (internally correct data) bit also
enables the error correction capability of the bubble system, but allows a slightly different interaction between the 7.220 controller and the 7242 FSA
than defined for the RCD mode. Error interrupt
conditions are the same as defined for RCD operation. With the ICD bit on, correctable errors are
handled automatically, but the operation halts for
uncorrectable or timing errors. With both the ICD
and ERROR INTERRUPT bits olj), the operation
halts for correctable, uncorrectable or timing er·
rors. The ICD mode differs from the RCD mode in
that when an operation halts due to an error, the
offending page is held in the 7242 FSA and is not
automatically transferred to the 7220 FIFO.
Though the difference is subtle, the ICD mode of
operation allows more flexibility in error logging
and recovery. With data held in the 7242, the
number of the bad page can be read for logging
purposes, and the data can be recycled through
the error correction network or reread from the
bubble repeatedly. When the CPU is interrupted
due to an error in the ICD mode, the user must
look at the 7220 status byte to determine the type
of error encountered. If tbe error is correctable,
the user's software sends a Read Corrected Data
command (OCH) to the controller. This command
causes the controller to issue it's own commands
to the 7242 to correct the error and to transfer the
data to the. 7220 FIFO. (Recall this action is done
automatically when the RCD mode is selected; uncorrectable errors can be handled as described
above).
As an example of how the ICD.mode can be utiliz·
ed, suppose that during.a data transfer in the RCD
mode, a correctable error consistently occurs. The
6-24
Ap·119
error, of course, is automatically handled by the
7242, and the only indication that an error had
been corrected is through the status byte at the
end of the transfer. There is no information as to
how many or in what page the error or errors appear. One way to diagnose the problem is to
reread the entire data block in the ICD mode with
the ERROR INTERRUPT bit on. The transfer stops
at the appearance of any error, and the data remains in the 7242. The page number of the error
can be found by reading the Address Register
since this register is incremented automatically
after each page is read if no error is detected.
The user should then issue an RCD command to
the 7220 to allow the page to be corrected and
transferred to the 7220. Once the transfer is complete, the enable register again is changed to
disable all error correction, and the 7220 is
reinitialized. The entire block is read again and
compared with the corrected version. (Error correction bits are appended to the data and can be
ignored.) If a bad loop is suspected, the bad loop
location could be calculated and the bootloop
modified.
It is unlikely that repeated correctable errors are
sufficient motivation to modify the boot loop.
Repeated uncorrectable errors, however, at the
same location, might be sufficient reason. Note
that modifying the bootloop is an extreme
measure and should only be performed as a last
resort and only if justified by test data.
The Status Register
The 7220's 8-bit Status register is accessed by
1). This register
reading the Command port (AO
provides information regarding error conditions,
the termination of commands, and the readiness
of the controller to transfer data or accept new
·commands.
=
lJ~~g~~~~
Values for the Uncorrectable Error and Correctable Error fields are generated when error correction is utilized as previously defined. The PARITY
ERROR bit is set when a parity error is encountered on data sent to the controller on the
00-07 lines. The TIMING ERROR bit is set for a
number of conditions. The most frequent cause of
a timing error is when the CPU fails to keep up
with the rate at which the controller is filling or
emptying the FIFO (an overflow or underflow condition). With one bubble in the system and the
MFBTR bit of the Enable byte set to one, the controller moves data to or from the FIFO at a rate of
about one byte every 80 microseconds. With eight
bubbles operating in parallel, the rate is about one
byte every 10 microseconds. (With the MFBTR bit
set to 0, the data rate on a one page transfer or the
last page of a multi page transfer is four times
these rates.) Once a Read or Write command is
issued, if the CPU cannot meet these transfer requirements, a timing error results.
Another way in which a timing error occurs is
when the proper number of bits is not set in the
boot loop register of the 7242 FSA. The 7242 must
have 272 loops active to operate properly (270 with
error correction enabled). If a mistake is made
either when the bootloop of the 7110 is written or
if the boot loop register is loaded incorrectly from
RAM by the user, a timing error results. A timing
error also occurs if the Write Bootloop command
is issued to the 7220 controller and the WRITE
BOOTLOOP ENABLE bit of the Enable byte is not
on. Finally, a timing error is generated if the
boot loop synch code is not found when a Read
Bootloop or Initialize command is issued.
The OP FAIL and OP COMPLETE bits of the status
register simply indicate the state of an operation
after a command is executed. If an operation fails
(OP FAIL
1), tlle cause can be determined by
looking at the other error bits of tlie status byte.
When an operation (command) terminates successfully, the OP COMPLETE bit is set, and the
status register shows a 40H.
=
The FIFO AVAILABLE bit of the status byte is
more complex than the other bits since its meaning can change depending on the type of operation being performed as outlined below.
From an operational point of view, the FIFO
AVAILABLE bit acts as a gate fQr the FIFO handling software. During a write operation, if the FIFO
bit is set (1), there is room for more data; if the
FIFO bit is clear (0), the FIFO is full. During a read
operation, if the FIFO bit is set, data has been
placed in the FIFO by the controller; if it is clear,
the FIFO is empty.
FIFO AVAILABLE
PARITY ERROR
CORRECTABLE
ERROR
UNCORRECTABLE
ERROR
TIMING ERROR
OP FAIL
OPCOMPLETE
~-------_ BUSY
Figure 5_ Status Register Definition
6-25
I
Ap·119
be low in order for the controller to accept a new
command (except Abort). Sometime between TO
and T1, the BUSY bit goes high. Thus, between T1
and T2, the status byte will be 80H.
Table 9. FIFO Available Bit Semantics
& writing
BUSY = 1
& reading
& reading
1
room lor data
data avail.
data avail.
0
no room
for data
no data
no data
FIFO AVAIL
BIT
BUSY
=1
BUSY
=0
At T2, the FIFO is internally placed in the "write
mode," and FIFO AVAILABLE changes meaning
from "FIFO has data" to "FIFO has room". For
proper operation, the FIFO must be empty prior to
issuing the WRITE command. This condition can
be guaranteed by using the FIFO Reset command.
Assuming the FIFO is empty, at T2 the status byte
changes from 80H to 81 H. The status byte remains
at 81H until T6 (unless the CPU is able to fill the
FIFO in which case, the FIFO AVAILABLE bit toggles between 0 and 1).
Note that it is possible to complete an operation
with data still remaining in the FIFO (indicated by
a 41 H status value). This condition is quite legal~ it
is up to the software to remove the data or to issue
a FIFO RESET command.
At T7 (the completion of the command), the status
byte should be 40H if the CPU did not load data
between T6 ar')d T7. If data was loaded during this
interval, the status value is 41H.
The BUSY bit indicates when the controller is in
the process of executing a command. When a
command is sent, the BUSY bit goes active within
a few microseconds after the command is received and remains active until the operation either
completes or fails. It is important to note that the
BUSY bit remains active until all other bits in the
status byte have been set. Thus it is possible to
see logically-exclusive conditions such as BUSY
and OP COMPLETE at the same time. The key to
interpreting the status byte is to consider the
status byte valid only after the BUSY bit returns to
an inactive level. The single exception to this rule
is the FIFO AVAILABLE bit.
Notice that if the FIFO contains data when the
Write command is sent, the CPU can, by mistake,
overflow the FIFO during the "seek" portion of the
command. This condition results from the FIFO
AVAILABLE bit being a "1" due to data present in
the FIFO, not because there is room in the FIFO.
While the following diagnostic routines take advantage of the "preloading" ability of the FIFO,
the examples of operational software at the end of
this application note do not preload the FIFO.
7220 Commands
The 7220 command set consists of 16 commands
identified by a 4-bit command code. The function
of most of the commands is obvious from the
command name (e.g., Initialize, Abort, Read,
Write). Th,ese commands are' adequately described in the BPK 72 manual. There are, however,
some commands and protocols that merit additional discussion (specific examples are covered
later in this document).
The action of the controller during a write operation is one of the more complex sequences and
serves as a good illustration of the behavior of the
BUSY and FIFO AVAILABLE bits. Suppose a Write
command is sent to transfer an arbitrary number
of pages. Table 10 shows the activity of the con·
troller at various steps in the sequence.
Table 11. 7220 Commands
Table 10. Stages of a Write Command
wait for
2 bytes
of FIFO generate swap overhead
overhead
seek data
T4
15
I
I
FIFO
reset
03
02
02
0
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
0
0
0
0
0
0
0
(time line is not to scale)
1
1
1
1
1
1
1
1
Before the Write command is sent, the FIFO is in a
general-purpose mode and remains in this mode
until T2. When the command is sent at TO,
the BUSY bit is low and, in fact, the BUSY bit must
6-26
01
1
1
1
1
1
1
1
1
Command Name
Write Bootloop Register Masked
Initialize
Read Bubble Data
Write Bubble Data
Read Seek
Read Bootloop Register
Write Bootloop Register
Write Bootloop
Read FSA Status
Abort
Write Seek
Read Bootloop
Read Corrected Data
Reset FIFO
MBM Purge
Software Reset
Ap·119
In general, all commands sent to the 7220 controller must be preceded by the setting of the
parametric registers. While there are some exceptions as with the Abort command, it is usually
necessary to supply operating information to the
controller via the parametric registers prior to issuing any command. Since many initial problems
stem from failing to load the registers prior to is·
suing commands, the user software should never
assume that the regsiters contain valid data.
After the bubble system has been powered up, the
7220 controller inhibits (or ignores) all commands
except an Initialize or Abort command. One of
these commands must be sent prior to issuing
any other command. Normally, the first command
issued after loading the parametric registers is
the Initialize command. This complex command
reads and decodes the boot loop information from
each bubble in the system and places this infor·
mation in the boot loop register of the correspon·
ding 7242 FSA. Pointers internal to the 7220
automatically are prepared for normal operation.
As described later, the combination of the Abort,
MBM Purge and Write Bootloop Register commands is functionally similar to the Initialize command. (The only time the MBM Purge command is
used is in conjunction with the Abort command).
Once the system has been initialized, the remainder of the command set can be selected.
Assuming, for example, that a Read command is
to be executed, the user selects the page number
and length of the transfer via the parametric
regisiters and then issues the Read command. If
the system uses the polled mode, the CPU reads
the status register and waits for the BUSY bit to
go active and then for the FIFO READY bit to indicate that data is being sent to the FIFO. Data
can be taken from the FIFO until the FIFO READY
bit goes inactive.
should issue a FIFO Reset command in order to
'clear the 7220's FIFO counter before initiating the
data transfer. If a prior transfer is stopped with
data remaining in the FIFO or if the FIFO is partially filled, the 7220's internal FIFO counter is not
zero, and there is a danger that the subsequent
transfer count may be incorrect. If the FIFO is
reset properly, execution of a FIFO Reset command is redundant.
Although the 7220 FIFO may be treated as a
40-byte RAM buffer, the temptation to "pre-load"
the FIFO with 40 bytes of data and then to issue a
Write command should be avoided due to the
danger of overflowing the FIFO. Prior to issuing a
Write command, a FIFO Reset command should
be sent, and the parametric registers should be
loaded. Following the Write command, the CPU
should monitor the status byte and wait for the
BUSY and FIFO AVAILABLE bits to go active.
When this status condition occurs, the user software should then send the proper number of bytes
to the 7220. The FIFO AVAILABLE bit of the status
byte should be polled prior to sending each byte.
An exception to not preloading the FIFO is when a
Write Bootloop, Write Bootloop Register, or Write
Bootloop Register Masked command is used.
Prior to issuing any of these commands, a FIFO
Reset command must be sent before preloading
the boot loop data into the FIFO. When one of the
bootloop-related commands is issued, the 7220
controller immediately begins taking data from
the FIFO. If the FIFO is not preloaded, incorrect
data may be transferred. The operation of the normal Write command differs from the bootlooprelated commands in that, after a Write command
is issued, the 7220 waits for at least two bytes to
be present in the FIFO before beginning to
transfer data to the bubble.
If the FSA encounters an error condition during a
read or write operation, the status of the FSA is
reflected in the 7220 status byte. If the user
system decodes the error and decides to continue, the error flags in the 7220 controller and
FSA first must be cleared. To clear the status
bytes, the software can issue an Initialize command. However, this command resets all of the
current operating parameters in the 7220 con·
troller. To continue processing without resetting
the system, the software can use the Software
Reset command. This command resets any error
flags and clears the FIFO, but does not affect the
parametric register fields that define the system
configuration (e.g., number of FSA channels
selected).
If the page selected for the read operation is not in
position to be read (Le., the page is not at the
replicate gates), additional time is required to execute the Read command as the proper page is
rotated into position. In systems where faster
response is desired, the Read Seek command can
be used to place the page into position in order to
free the CPU to perform other tasks. Once the
page is in position, approximately eight
milliseconds are required before the data is
available to the CPU. This latency only occurs on
the first page of a multipage transfer. Similarly,
when a page is not in a position to be written,
Write Seek can be used to position the page at the
swap gates.
If there is any doubt regarding the state of the
FIFO prior to a read or write operation, the user
6-27
AP·119
INSTALLING THE BPK 72 BUBBLE
MEMORY KIT
7220 are communicating and that the power-up sequence is being performed by the 7220.
This section examines the individual components
of the Bubble Memory System and how each component can be analyzed_ All elements of the bubble system need not be working before any meaningful diagnostics can be effected_ In general, a
user first establishes communication between the
host CPU and the 7220 controller. Next, communication with the 7242 formatter/senseamplifier is verified via the 7220 controller. Finally,
the operation of the 7110 Bubble Memory is
checked. The software that exercises each of
these phases of implementation should be small,
well-defined device drivers that can be controlled
through a system monitor.
Table 12. Reading 7220 Controller Status
RDSTAT:
; THIS PROGRAM READS THE 1220
~6A~~tDB~+!TUS,
:
THE HOST CPU MUST
; READ FROM THE 7220 WITH AO = 1.
IN
MOV
RET
The procedures that follow are applicable to most
startup problems. The procedures are organized in
chronological fashion and address each step of
the installation process as it would normally occur. Software drivers in 8086 assembly language
are provided to illustrate the basic functions supported by the device drivers.
AL,49H
; COMMANDS/STATUS
; PORT ADDRESS OF
; 7220
STATUS, AL ; MOVE A\,. REGISTER
; TO STATUS
Once the power-up sequence is complete and the
7220 status register has been read, the 7220 FIFO
can be accessed. The software drivers that write
and read the FIFO are shown in Tables 13 and 14.
Notice that these code sequences do not send
commmands to the 7220; only data is transferred
to and from the controller. The purpose here is to
test the bus interface and timing between the CPU
and the 7220 controller. In this case, the 7220
FIFO is used as a general purpose RAM. Any data
can be written to the FIFO, but it is best to use an
easily indentifiable sequence (e.g., an incrementing pattern) for easy recognition.
Powering Up for the First Time
With power removed from the IMB-72 board, insert
all of the supporting integrated circuits with the
exception of the 7110 Bubble Memory Module. Insert the "dummy module" included in the BPK 72
kit in place of the 7110. The dummy module is
electrically equivalent to the 7110 module and
allows the circuits of the BPK 72 kit to be tested
without the possibility of damaging the bubble.
With both the + 5V and + 12V power supplies
turned off, insert the 1MB 72 with the dummy
module into the edge connector. As power is applied to the system, monitor the RESET.OUT/pin
of the 7220 controller and verify that the signal
goes from low to high after power is applied. The
low-to-high transition indicates that the power-up
sequence has been completed successfully.
Table 13. Writing the 7220 FIFO·
WTFIFO:
; THIS PROGRAM WRITES 40 BYTES FOR
; MEMORY TO THE 7220 FIFO.
; DATA IS ASSUMED TO BE ATBUFADR.
MOVE
SI,BUFADR
MOV
CX,40
WRT1:
LODSB
Communicating With the 7220 Bubble
Memory Controller
The first step in communicating with the 7220 is
to write initial values to the parametric registers
using the code sequence in Table 15. When the
registers have been set, the code shown in Table
12 can be used to examine the 7220 status byte'.
OUT
48H, AL
LOOP
WRT1
RET
The status value returned in Table 12 should be
40H. The user should not continue until the proper
status value can be obtained repeatedly after performing the power-up sequence. Reading back the
correct status indicates that the host CPU and the
6-28
LOAD BUFFER
POINTER
LOAD COUNT
PUT BYTE AT SI
INTO AL, AUTO INCR
SI
OUTPUT BYTE TO
DATA PORT
DECREMENT COUNT,
LOOP IF NOT 0
Ap·119
Once forty bytes have been written to the FIFO, '
the 7220 status byte should be read. The status
value should be "41 H" (indicating that data is in
the FIFO). Other status values such as "parity
error" can be ignored. While status values give
some indication of the CPU·7220 interaction, the
integrity of the data is more important here. If the
data read back is not the same as the data sent, a
fundamental timing and/or interface problem between the CPU and the 7220 is indicated.
To verify that data is being transmitted to the
7220, the code sequence shown in Table 14 can be
used to read back the FIFO data into user RAM
space for direct comparison with the original
pattern.
Under normal operating conditions an Initialize
command is the second command sent to the
system. However, the Initialize command
assumes that the 7110 Bubble Memory is installed
and attempts to read boot loop information. Since
the dummy module is installed at this time, timing
errors result from the attempted Initialize command. Although no harm results from using the Initialize command, an Abort command followed by
an MBM-Purge command can be used in place of
the Initialize command to eliminate timing errors.
The Abort command is sent by executing the code
sequence at label "CMN09" in Table 16. When
Abort command execution is complete, the user
should read the status byte and check for an opcomplete indication (40H).
Table 14. Reading the 7220 FIFO
RDFIFO:
; THE PROGRAM READS 40 BYTES FROM
; THE 7220 FIFO INTO MEMORY,
MOV
MOV
RD1:
IN
DI, BUFADR ;
;
;
CX,40
;
AL,48H
STOSB
LOOP
RD1
;
;
;
;
;
;
LOAD BUFFER AD·
DRESS INTO DI
LOAD COUNT INTO
CX
INPUT FROM DATA
PORT
STORE AL AT ADDR
IN DI, AUTO INCR. DI
DECREMENT COUNT
IN CX, LOOP IF NOT 0
RET
After reading the FIFO, the status byte should be
read (a value of "40H" or "42H," indicating that
the FIFO has no data, should be obtained). The
user should not proceed until the FIFO can be
written and read correctly and until the FIFO
status indicates the amount of data in the FIFO
(not empty or empty). These steps verify that the
CPU can communicate with the 7220. Note that no
data has been transferred to or from the 7242 Formatter/Sense Amplifier or the 7110 bubble device
(or dummy module).
Communicating With the 7242
Formatter/Sense Amplifier
The next step in verifying the BPK 72 is to ensure
that the 7220 is driving the 7242 Formatter/Sense
Amplifier properly by first setting up the 7220 for
interaction with the 7242 and then sending com·
mands to the 7220 to exercise the 7242 functions
that can be verified easily.
6-29
AP·119
Table 15. Write Register Sequence for Two FSA Channels
WTREG2:;
WRITE REGISTERS
; 2 FSA CHANNELS SELECTED.
; THIS IS USED FOR DEBUG TO WRITE/READ THE
; BOOTLOOP REGISTERS AND CHECK FOR MISSING SEEDS, ETC.
; THE FOLLOWING VALUES INTO THE 7220 REGISTERS
B
01H
: 1 PAGE TRANSFER
C = 10H
: SELECT 2 CHANNELS (WHOLE BUBBLE)
D
08H
: STANDARD TRANSFER RATE
E = DOH
: PAGE 0
: FIRST BUBBLE
F = OOH
=
=
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
RET
AL,OBH
49H,AL
AL,01H
48H, AL
AL,10H
48H, AL
AL,08H
48,H, AL
AL,OOH
48H, AL
AL,OOH
48H, AL
; SELECT B REGISTER
; ONE PAGE TRANSFERS
; WHOLE BUBBLE (2 FSA CHANNELS)
; LOW FREQ
; START ADDRESS = OOOOH
; FIRST BUBBLE
Once the op'complete status is received, the
MBM·Purge command is issued by executing the
routine labeled "CMNDE" in Table 16. This com·
mand, as described in the BPK 72 manual, clears
a" of the controller registers, counters and ad·
dress RAM (except the block length register), the
NFC bits, the FSA present counter and the higr'
order four bits of the address register. After the
command is complete, the user again should
receive an operation complete indication on
reading the status byte.
After the Abort and MBM·Purge commands are ex·
ecuted and is status verified, additional com·
mands may be sent to the 7220 BMC. Since the
purpose of this section is to verify the interaction
of the 7242 and 7220, manually loading and
reading the 7242 bootloop registers can be used
for the verification. Two additional commands are
required to load and read the bootloop registers:
the Write Bootloop Register command and the
Read Bootloop Register command. These com·
mands transfer data between the 7242 bootloop
registers and the 7220 FIFO. Since the ability to
transfer data between user RAM and the 7220
6·30
AP·119
Table 16. 7220 Controller Commands
CMNDS:
; 7220 COMMANDS
; THESE 16 ROUTINES EACH SEND A SINGLE COMMAND TO THE 7220.
; FOR EXAMPLE, THE "INITIALIZE COMMAND" WILL WRITE 11H
; TO THE 7220 WITH AO = 1. THESE ARE THE 7220 COMMANDS LISTED
; IN THE BPK-72 USERS MANUAL.
CMNDO:
MOV
AL,10H
; WRITE BOOTLOOP REGISTER MASKED COMMAND
OUT
49H, AL
RET
CMND1:
MOV
AL,11H
; INITIALIZE COMMAND
OUT
49H, AL
RET
CMND2:
MOV
AL,12H
; READ COMMAND
OUT
49H, AL
RET
CMND3:
MOV
AL, 13H
; WRITE COMMAND
OUT
49H, AL
RET
CMND4:
; READ SEEK COMMAND.
MOV
AL,14H
OUT
49H, AL
RET
CMND5:
AL,15H
; READ BOOTLOOP REGISTER COMMAND
MOV
OUT
49H, AL
RET
CMND6:
AL, 16H
; WRITE BOOTLOOP REGISTER COMMAND
MOV
OUT
49H, AL
RET
CMND7:
; WRITE BOOTLoop COMMAND
MOV
AL,17H
49H, AL
OUT
RET
CMND8:
; READ FSA STATUS COMMAND
MOV
AL,18H
49H, AL
OUT
RET
CMND9:
MOV
AL,19H
; ABORT COMMAND
49H,AL
OUT
RET
CMNDA:
; WRITE SEEK COMMAND.
MOV
AL,1AH
49H, AL
OUT
RET
CMNDB:
6-31
AP-119
Table 16. 7220 Controller Commands (cont.)
MOV
OUT
RET
CMNDC:
MOV
OUT
RET
CMNDD:
MOV
OUT
RET
CMNDE:
MOV
OUT
RET
CMNDF:
MOV
OUT
RET
AL,1BH
49H,AL
; READ BOOTLOOP COMMAND
AL,1CH
49H, AL
; READ CORRECTED DATA COMMAND
AL,1DH
49H,AL
; FIFO RESET COMMAND
AL,1EH
49H, AL
; MBM PURGE COMMAND
AL,1FH
49H, AL
; SOFTWARE RESET COMMAND
FIFO has been verified previously, these two adqi·
tional commands verify the system's ability to
transfer between user RAM and the 7242 FSA.
The 7220 parametric registers must be loaded
prior to sending the Write Bootloop Register com·
mand. The sequence of operations is important;
loading the parametric registers destroys the first'
byte of data in the 7220 FIFO. If valid bootloop in·
formation is placed in the FIFO before the
parametric registers are loaded, the first byte of
bootloop register information is invalid. Accor·
dingly, the sequence of operations must be as
follows:
(1) load the 7220 parametric registers
(2) load bootloop data into the 7220 FIFO
(3) send the Write Bootloop Register command.
As a point of interest, if a user wishes to maintain
the system bootloop. in EPROM rather than to
allow automatic handling by the system, the In·
itialize command would not be used and would be
replaced by a sequence similar to the one describ·
\ ed.
After the 7220 parametric registers are loaded, the
CPU next must load the 7220 FIFO with 40 bytes
of bootloop register data using the "write FIFO"
sequence from Table 13. This sequence then is
followed by the code sequence to issue the Write
Bootloop Register command. The data pattern
written to the bootloop register should be an easi·
Iy identified sequence of bytes such as an in·
crementing pattern. Under operational conditions,
the data written to the bootloop registers
represents "loop map" information that is written
on the label of the 7110 device. Under these test
conditions, it only is necessary to ensure that the
40 bytes sent out are the same 40 bytes read back.
Once the Write Bootloop Register command has
been sent, the status byte is read (when the BUSY
bit goes low) and an operation·complete status is
verified. Any parity error indication may be ig·
nored. Valid status at this pOint indicates that
communication with the 7242 has been establisl)·
ed. To verify that the data has been transferred
properly, the contents of the bootloop register are
read into the 7220's FIFO. The CPU then must
transfer the data to user RAM in order to compare
the data with the original pattern. To read the
bootloop register, it only is necessary to issue the
Read Bootloop Register command. This com·
mand places the contents of the 724'2's bootloop
register into the 7220's FIFO. The user then must
execute the "read FIFO" sequence from Table 14
in order to transfer the data from the 7220 FIFO to
RAM. Comparing the loop map written into the
bootloop register and the loop map read from the
bootloop register should show the loop maps to
be equal.
6-32
Ap·119
Installing the 7110 MBM
Reading and writing the 7110 bubble memory requires the application of specific control signals
at the appropriate times within the read or write
cycles. These control signals originate from the
7254 and 7230 integrated circuits and are
generated under the control of the 7220 BMC.
Prior to installing the 7110, the presence of the
control signals should be verified., While it is
unlikely that the 7110 can be seriously damaged, it
is possible for the "seeds" and boot loop
established at the factory to be lost if there are
problems with the 7254 or 7330 control signals
and, if lost, would require additional steps on the
part of the user to regenerate the seeds and
bootloop data. With the dummy module installed,
the required control signals can be verified directlyon the bubble socket, and the possibility of
damaging the bubble can be avoided.
The first control signal waveform to check is the
coil drive on pins 9, 10, 11, and 12 of the 7110
socket. The drive current can be verified by ensuring that the voltage waveform on these pins (or on
pins 1 and 7 of the 7254) conforms to Figure 6A
when the drive field is being rotated. To rotate the
drive field, the following code sequence can be
used:
1. Write the parametric registers.
2. Send the Read command.
bootloop register of the 7242 first must be loaded
to allow data to be written. A Write Bootloop
Register Masked command can be used to write a
bootloop register pattern of all ones; it is only
necessary to write the bootloop register once.
Finally, the SWAP pin is tested for proper operation during a write operation. The waveforms on
pins 13 and 14 of the 7110 (SWAP.A and SWAP.B)
should appear as shown in Figure 6D. The code
sequence described for a write operation may be
used.
One additional check of the system should be
made prior to installing the 7110 device to determine if valid status values are received after a
Read or Write command is issued to the 7220
BMC. Since the bubble is not yet installed, no data
actually is transferred; the system should,
however, execute the Read or Write command,
and valid status should be received. Since a new
command cannot be issued to the 7220 while a
command is in progress, an Abort command is
sent to cancel any command that may be pending
from the last test performed. Next, a FIFO Reset
command is sent to clear any data remaining in
the FIFO. The status byte received should indicate an OP-COMPLETE and FIFO AVAILABLE
status condition. The 7220 now is ready to execute a Read or Write command.
First, the 7220 parametric registers are loaded using the modified "diagnostic" driver shown in
Table 17. This routine selects one FSA channel
(half of a bubble) and, with ECC disabled, requires
the loading of only 34 bytes in the 7220 FIFO. By
limiting the FIFO to less than 40 bytes, FIFO
underflow/overflow conditions are eliminated, and
timing errors are avoided in the status byte. After,
the 7220 FIFO is preloaded with 34 bytes of data
(any pattern), a Write command' is issued to the
7220 BMC. The 7220 status value received following command execution should reflect OPCOMPLETE since the 7220 transferred the data
from its FIFO to the 7242 and executed the Write
command as though the bubble were in place.
Next, the "cut and transfer" pulses generated during a read operation should be checkj3d. The
waveforms on pins 2 and :3 of the 7110 socket
(REPLICATE.A and REPLICATE. B), should appear
as shown in Figure 6B.
The cut and transfer pulses that occur during a
write operation should now be verified. The
waveforms on pi ns 7 and 8 of the 7110 socket
(GENERATE. A and GENERATE. B) should appear
as shown in Figure 6C. Since a write operation is
required, a new code sequence must be used for
this test:
1.
2.
3.
Write the parametriC registers.
Write data (any patten) to the FIFO.
Send the Write command.
6-33
Ap·119
+ 12V
A:
PINS 9, 10, 11, 12
OV
1-40~s-l
+12
B:
PIN 2, 3
(DURING READ)
c:
PIN 7,8
(DURING WRITE)
0:
PIN 14,13,
(DURING WRITE)
5 ~s
12V
12V
~
28.75
+ 4.3V
~s
(Not drawn to scale)
Figure 6. Control Signal Waveforms
To test the system in the read mode, the 7220
parametric registers are reloaded and a Read command is issued to the 7220. The user software
must now read 34 bytes of "data" from the 7220's
FIFO. Note that the data read will consist of all
zeroes since no bubble is in place.
Installing the 7110 is no different from iristalling
any other device. Remove the dummy module in
the 7110 socket and insert the 7110 Bubble
Memory. Note that the 7110 is keyed to prevent
the device from being'inserted incorrectly. When
power is applied, the system should execute its
power-up sequence as described for the dummy
module, and the 7220 status byte should return
OP-COMPLETE after the parametric registers
have been loaded.
When the system completes all of the previous
tests successfully, the 7110 bubble memory
device may be inserted. Before proceeding,
REMOVE POWER FROM THE SYSTEM.
6-34
Ap·119
Table 17. Write Register Sequence for One FSA Channel
WTREG1:;
WRITE REGISTERS (ONE HALF BUBBLE)
THIS PROGRAM WRITES THE 7220 REGISTERS "B" THROUGH "F".
DIAGNOSTIC ROUTINE WITH ONE FSA CHANNEL SELECTED
THE FOLLOWING VALUES ARE WRITTEN TO THE 7220 REGISTERS.
B = 01H
1 PAGE TRANSFER
OOH
SELECT 1 CHANNEL (HALF BUBBLE)
C
D
08H
LOW FREQ
PAGE 0
E = OOH
F
OOH
FIRST BUBBLE
=
=
=
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
MOV
OUT
RET
AL, OBH
49H, AL
AL,01H
48H, AL
AL,OH
48H,AL
AL,08H
48H,AL
AL,OH
48H,AL
AL,OH
48H,AL
;
;
;
;
;
SET REGISTER ADDRESS COUNTER (RAG) TO B REGISTER
PROT ADDRESS OF 7220 WITH AO = 1
SET B REGISTER TO 01H (ONE PAGE TRANSFER)
PORT ADDRESS OF 7220 WITH AO 0
SELECT HALF BUBBLE (1 FSA CHANNEL)
=
; SELECT LOW FREQ (NO ERROR CORRECTION)
; START ADDRESS = OOOH
; SELECT THE FIRST BUBBLE
Normal Read and Write Operations
Under normal operating conditions, a user sends
an Initialize command and then proceeds to access the bubble. The Initialize command
automatically purges the RAM area of the 7220,
reads and decodes the bootioop on the 7110, fi lis
the 7242 bootloop registers, and places the 7110
at page O. This very important command is the
next command to be tested before reading and
writing data.
To verify the Initialize command, load the 7220
parametric registers to select both FSA channels
for one bubble and then send the Initialize command. Status following execution of this command should be 40H, OP-COMPLETE. Once the
7220 is initialized, data can be transferred to and
from the bubble. For a first attempt, it is recommeded that the operations be kept simple. That is,
avoid error correction, DMA, or interrupts and only
attempt single page transactions until reasonably
familiar with the basic operations.
Prior to issuing the Write command, a FIFO Reset
command is sent and then the parametric
registers are loaded to select the page address
and number of FSA channels. After the Write command is sent, the data should be output to the
7220 FIFO. When the proper number of bytes have
been transferred, the 7220 status byte should
reflect OP-COMPLETE and FIFO AVAILABLE to
indicate that the data has been written into the
7110 bubble memory and can now be read. To read
back the data written, issue a FIFO Reset command and reload the parametric registers to select
the same page address in which the data was written. Issue the Read command to move the data
from the 7110 to the 7220 FIFO and then use the
"read FIFO" routine to transfer the data to user
RAM. As always, the 7220 status byte should be
checked after the operation.
6·35
AP·119
AN IMPLEMENTATION EXAMPLE
To;illustrate the ease with which Intel's bubble
memory solution r:pay be implemented, an MCS~86
System Design Kit (SDK-86) is used 'as a vehicle to
control a single BPK 72 bubble memory kit.
The bus interface between the 8086 CPU and the
7220 bubble memory controller requires seven integrated circuits and consists of four sections: address decode, data bus decode and buffering, a
clock circuit, and miscellaneous control logic.
The system requJres power supply voltages of
+ 12V, + 5V, and, if a CRT is used, -12V.
The 8086 bus is expanded through two 50-pin,
wirewrap connectors, and the BPK 72 is connected to the SDK-86 by a flat cable into a 40-pin .
connector located on the SDK-86. The following
interface diagram shows how the signals required
by the bubble system are derived from the 8086.
Detailed diagrams of the address, data, clock and
control logic are in the appendix.
Either the SDK-86's Keypad or Serial monitor may
be used to write and debug the necessary soft- .
ware drivers to control the BPK 72. There is,
however, an EPROM-based monitor (BMDSDK) explicity designed for the BPK 72 and is available
from the Intel Insite Library. Some of the bubblespecific portions of this monitor are discussed in
the following text.
Monitor Software
The BMDSDK Bubble Monitor is a highly-modular
program that is written in 8086 assembly language
and that resides in two 2716 EPROMs. This
monitor implements, at the console level, most of
the standard SDK-86 monitor functions
(display/change memory, etc.) and all of the 7220
commands. The current version of the monitor'
utilizes only polled I/O protocol; implementing an
interrupt-driven system on the SDK-86 is possible
using the principles outlined in this application
note. The DMA mode of operation is not available
with the hardware described.
The BPK 72 driver routines are confined to one
module; a listing of this module is included in the
appendix. To provide some feeling for the
elements of "operational" softwar&as opposed to
the test drivers discussed earlier, the write function implemen,ted in BMDSDK monitor is examined. The flow chart in Figure 9 shows how the
routine is constructed on a functional basis. Note
that the subroutine reflects a very "safe" approach in that the FIFO Reset command always is
sent prior to issuing the Write command. While
the FIFO Reset command is not mandatory, if
there is any a doubt regarding the state of the
FIFO prior to a read or write operation, resetting
the FIFO is a good idea. Note also that a running
byte count is maintained and that the routine exits
when the count goes to zero. Such a counter is not
actually necessary; the FI FO AVAI LABLE bit
alone can be used to gate the data to the 7220.
The Galling program supplies the BMWRIT routine
with the total number of bytes to be transferred in
the CX register. The total number of bytes written
is sent to the console at the end of the operation
as a monitor function. BMWRIT also returns the
value of the status byte to the calling program.
Note that at label WRIT01, the routine does not
progress after the Write command is sent unless
both the BUSY and FIFO AVAILABLE bits are set
by the controller. Once these values are set, the
code issues a byte of data to the controller only if
the FIFO AVAILABLE bit indicates there is room.
The remainder of the code in BMWRIT is concerned with processing sp,ecial write requests for the
bootloop and bootloop register commands.
6-36
AP·119
GND +5V -12V
+12V
J7
BG
BG
BPK 72
J8
Jl
BG
G
SDK·86
J3
G
II at
cable
,-----1
I
I
KEYPAD
I
I
L _____ .J
Figure 7. SDK·86/BPK 72 Implementation
6·37
Ap·119
USER
HARDWARE
SDK·S6
SIGNALS
BOO - BD15
,...
BDTIR
BHE!
/
I 16
'"'
11
11
BPK72
SIGNALS
DATA BUS
BUFFERS
AND
DECODING
LOGIC
I
I
--1l
I
I
I 15
~
11
11
I
I
ADDRESS
DECODE
LOGIC
'"' CSt (7220)
~
-"'1
I
/1
AO
I
I
I
I
CLOCK
CIRCUIT
I
o ClK
I
INTRO~-----Ir-------------------~----------~~--~OINT
'1
o
<
BRD!O~-----Ir-----------------~~----------~r---
'4 ,
RDI
BWT!O~-----Ir-------------------~----------~r---~OWRI
(>0'1
o RESETI
RESET O~----II----~--OUT
/.f
I
I
I
+5V~
I
I
I
I
I
+ 12V"
WAITI
o CSI (7242)
I
I
Figure 8. SDK·86/BPK 72 Interface Diagram
6-38
DACKI
I
I
-:;.
~
I
I
Vee
~ Voo
GND
Ap·119
SEND WRITE
COMMAND
INPUT
STATUS
INPUT
STATUS
Ve.
EXIT TO
ERROR
HANDLER
Figure 9. BMWRIT Flowchart
6-39
Ap·119
Table 18. BMWRIT Procedure for the SDK·86
FUNCTION: BMWRIT· WRITE BUBBLE MEMORY DATA.
INPUTS: CX = # OF BYTES TO WRITE.
OUTPUTS: A = STATUS: F/F(C= 1: ERROR OCCURED) BX=# OF BYTES WRITTEN.
CALLS: SNDREG, BMWAIT.
DESTROYS: ALL.
DESCRIPTION:
THIS PROCEDURE PERFORMS A BUBBLE MEMORY WRITE OPERATION.
AN ERROR WILL OCCUR IF THE NUMBER OF BYTES GIVEN FOR THE
WRITE OPERATION EXCEED THE NUMBER THAT THE BMC EXPECTS
(DERIVED FROM COMMAND, BLOCK LENGTH AND NUMBER OF FSA
CHANNELS), OR IF THE NUMBER OF BYTES IS LESS THAN THAT
WHICH THE BMC EXPECTS.
BMWRIT:
XOR
MOV
MOV
MOV
OUT
CALL
MOV
MOV
OUT
WRIT01:
IN
TEST
JZ
TEST
JZ
AL, AL
STATUS,AL
BX,CX
AL, CFR
BMSTAT, AL
SNDREG
SI, BUFADR
AL, BMCMD
BMSTAT, AL
AL, BMSTAT
AL, BUSYBT
WRIT01
AL, FIFOBT
WRIT01
=
;A
0
; CLEAR STATUS
;
;
;
;
;
FIFO RESET
SEND REGISTERS TO BMC.
SET UP SRC BFR PTR (IN DATA SEG)
GET COMMAND
ISSUE IT.
; WAIT FOR BUSY ...
; AND FIFO READY
KEEP STUFFING DATA INTO FIFO UNTIL DONE OR AN ERROR OCCURS.
(NOTE: BMC GOING NOT BUSY IS AN ERROR).
WRIT03:
IN
AL, BMSTAT
; GET STATUS
TEST
AL, FIFOBT
; FIFO READY?
JZ
WRIT04
; NO, WAIT FOR IT
LODSB
; YES, GET DATA FOR IT
OUT
BMDATA, AL
; GIVE IT TO BMC
LOOP
WRIT03
; LOOP UNTIL DONE.
JMP
BMWAIT
; XFER DONE, WAIT FOR A GOOD STATUS
WRIT04:
TEST
AL,BUSYBT
JNZ
WRIT03
; OK IF STILL BUSY
BX, CX
, BX:# OF BYTES XFERED
SUB
JMP
CTRL99
; ERROR IF NOT BUSY AND CX NOT ZERO
SPECIAL WRITE FOR BOOTLOOP AND BOOTLOOP REG CMNDS
BMWRTB:
XOR
MOV
MOV
MOV
OUT
CALL
MOV
AL,AL
STATUS,AL
BX,CX
AL, CFR
BMSTAT, AL .
SNDREG
SI, BUFADR
;A = 0
; CLEAR STATUS
FIFO RESET
SEND REGISTERS TO BMC.
SET UP SRC BFR PTR (IN DATA SEG)
; FILL FIFO WITH 20/40/41 BYTES
6-40
Ap·119
Table 19. BMWRIT Procedure for the SDK·a6 (cont.)
WRTB01:
LODSB
OUT
LOOP
IN
TEST
JZ
MOV
WAITPO:
IN
TEST
LOOPNZ
JCXZ
WAITE:
MOV
RET
BMDATA, AL
WRTB01
AL, BMSTAT
AL, BUSYBT
SHORT WAITEX
CX,OFFFFH
AL, BMSTAT
AL, BUSYBT
WAITPO
CTRL99
;
;
;
;
;
;
;
;
;
;
;
STATUS,AL
; A = STATUS
SUMMARY
STICK IN FIFO.
LOOP UNTIL FILL COUNT = O.
GET BMC STATUS
CHEGK BUSY BIT.
NOT BUSY, ALREADY DONE.
JUST IN CASE ...
POLLED WAIT MODE
GET STATUS
CHECK BUSY BIT
LOOP IF STILL BUSY
PROBABLY AN ERROR IF CX=O
The BPK 72 is a subsystem in itself that should be
viewed as simply one more component on the
system bus. This component-level approach, plus
the inherent flexibility of the kit, provides the user
with maximum utility and functionality. By
understanding how each of the subsystem parts
fits together and by approaching the implementation of the kit in a methodical fashion as described in this note, the development of a working
system is facilitated.
The purpose of this application note is to provide
a more clear understanding of the functions and
characteristics of the BPK 72 one-megabit bubble
memory kit. This kit has been designed specifically to relieve the user of the design effort that
historically is associated with implementing a
bubble memory system, and to provide a simple
interface that is compatible with a broad range of
microprocessor systems.
6-41
Ap·119
APPENDIX A
SDK·86/BPK 72
HARDWARE INTERFACE
6·42
AP·119
SDK·86 EXPANSION AREA
50 49
EJ
J8
US
'---
[j
-
G
-
40 39
2
J1
U4
2
B
B
B
1
50 49
J3
2
1
Top View User Hardware Section
Figure 10. Parts layout
6-43
Ap·119
9
111
,...
BOO (J1·2)
1
-
2
B01 (J1.4)
,...
B02 (J1·6) .....
.....
B04 (J1-10) .....
B03 (J1·8)
B05 (J1·12) .....
B06 (J1·14)
INTEL
5
8286
6
16
15
14
8
12
19
1
U4
2
18
17
3
4
INTEL
16
,...
5
8286
15
,...
6
14
7
13
8
12
.....
B012 (J1·26) .....
B014 (J1·30) ".....
....
B015 (J1·32) "
T
-
J11
BOTtR (J1·48) "
BHEI (J3·2)
17
,...
B010 (J1·22) .....
B013 (J1·28)
4
13
,...
B011 (J1·24)
.!!. r--
US
3
-19
7
".....
B09 (J1·20)
OE
,...
B07 (J1·16) .....
B08 (J1·18)
T
-
04 (J8·30)
-"
05 (J8·32)
--
OE
9
.,...
-2
= 20
Gnd = 10
Figure 11. Data Bus Buffer and Decoding Logic
6·44
02 (J8·26)
,...
1
vee
01 (J8·24)
-"
.....
..... 03 (J8·28)
U6
8286 -
-
DO (J8·22)
-"
1"\
-
,...
.....
-"
-"
06 (J8·34)
-"
07 (J8·36)
Ap·119
AO (J3-4) O l - - - - - - - - - - - - - - - - O A O (JS-1S)
1
M (J3-6)
A2 (J3-8)
--
2
A1
3
"
,.
A3 (J3-10)
A2
4
E1
51- E2
6
E3
-
1
A4 (J3-12) ,..
A5 (J3-14)
-
2
A7 (J3-1S) 0 -
4~ E1
A11 (J3-26)
-
8205 06 ~
131
121
91r---v;U3
I
A14 (J3-32) ,..
4 )
--
A15 (J3-34) "
S
10 )
-
A13 (J3-30)
A2
5_ E2
1.J
A12 (J3-28)
U1
1 rEa
A9 (J3-22) ,..
A10 (J3-24)
14
I"'"
A1
3
A8 (J3-20)
8205 01
AO
A6 (J3-16) ,..
BM/IO (J3-44)
U2
AO
21
...... 6
j5 f1i2U3
Figure 12_ Address Decode LOiiIic
6-45
(7220)
- (JS-40)
CS
Ap·119
R3
+5V
5.1K
0
S
R1
5
CLK
(JS·4)
51011
R2
T
12
US
C1
56pF
51011
C2T56PF
I
BRDI (J3·46) 0 .......- - - - - - - - - - - - - - - -......0 RDt (J6·12)
BWRI (J3·46)0
0 WRI (JS·16)
INTR (J1·3S)0
OINT (J6·20)
3~..;..4_ _ _ _ __
RESET OUT (J1·34) 0 .......-----....,....,..--
0 RESETI (JS·10)
U6
WAIT (JS·14)
5.1K
R5
DACKI (JS·6)
5.1K
CS/(7242)
(JS·5)
+5V
.....
Vcc(JS·S)
""
+12V
C6
l
I
VDD (JS·2, 38)
I
C3·C5
--
GND (JS·1, 3, 27, 37,39)
Figure 13. Clock Circuit and Control Signals
6-46
AP·119
Table 21. SDK·861BPK 72 Cable Wiring
Table 20. SDK·B6 Pinout
Pin
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
J1/J2
J3IJ4
BOO
BHE!
B01
AO
B02
A1
B03
A2
B04
A3
BOS
A4
B06
AS
B07
A6
B08
A7
BD9
A8
B010
A9
B011
A10
B012
A11
B013
A12
B014
A13
B015
A14
RESET OUT
A15
PCLK!
A16
INTR
A17
TEST
A18
HOLD
A19
BHLOA
BM/IOI
BOENI
BROI
BOT/AI
BWRI
BALE
BINTAI
J5
P2C1
P2C2
P2C3
P2B7
P2BO
P2B6
P2B3
P2B4
P2B2
P2B5
P2B1
P2CO
P2C4
P2C5
P2C6
P2C7
P2AO
P2A7
P2A1
P2A6
P2A2
P2A5
P2A3
P2A4
-
J6
-
P1B3
P1B4
P1B2
P1B5
P1B1
P1B6
P1BO
P1B7
P1C3
P1C2
P1C1
P1CO
P1C4
P1C5
P1C6
P1C7
P1AO
P1A7
P1A1
P1A6
P1A2
P1A5
P1A3
P1A4
Signal
J8
+ 12v
2,38
+5v
Ground
DO
01
02
03
04
05
06
07
CSI (7220)
AO
ROI
WAI
INT
RESETI
CSI (7242)
WAITI
CLK
OACKI
8
F
1,3,27,37,39
22
24
26
28
30
32
34
36
40
18
12
16
20
10
1, A, P, 22, Z
11
12
13
14
15
16
17
18
5
E
14
8
4
L
4
6
Cable is standard 40 conductor Flat Cable.
All Odd Conductors are grounded at J8.
All Odd Pins are Ground except as follows:
41
43
45
47
49
J2
CSXI (FOOOO·FOFFF)
CSYI (FCOOo-FCFFF)
BS3
BS4
BSS
Table 22. SDK·861BPK 72 Parts List
Item
Description
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
1C8205 • Bindry Decoder
1C8286 • Octal Bus Tranciever
10.746525 • Dual 4 Input M
IC·74H04 • Inverter
Resistor 5100 1/4w
capacitor, 56pF 25V
capacitor, .1 pF 25V
Crystal, 8.000MHz Serie Res.
Connector, 50 pin wi rewrap
Connector, 40 pin wlrewrap
Connector, 40 pin
Connector, 44 pin Edge w/w
IC Socket, 20 pin w/w
IC Socket, 16 pin w/w
IC Socket, 14 pin w/w
Adapter Plug Assembly, 16 pin
Flat Cable, 40 Conductor, 1 Ft.
1C-74LS74· Dual D Flip-Flop
Resistor 5.1K 1/4W :j: 5%
20
1C-74LS32 • OR Gate
1
2
3
4
P1
B,X
6-47
QT
Ref
2
2
1
1
2
2
4
1
2
1
1
1
2
3
3
1
1
1
3
U1, U2
U4,U5
U3
U6
R1, R2
C1,C2
C3·C6
Y1
J1, J3
J8(M)
J8 (F)
P1
07
R3, R4, R5
R5
U8
Intel (T1·74LS13)
Intel
Any
Any
Any
Any
Any
Any
3M # 3433
3M # 3432
3M # 3417
Any
Any (Augat)
Any
Any
Augat # 616-CE1
3M # 3365
Any'
Any
Any
Y
10
J
K
N
H
Ap·119
APPENDIX B
SDK·86/BPK 72
SOFTWARE DRIVER
6·48
ISIS-II MCS-86 MACRO ASSEMbLER V2.1 ASSEMBLY OF MODULE DRIVER
OBJECT MODUJ.E PLACED IN :Fl:DRIVER.OBJ
ASSEMBLER INVOKED BY:
a.m8G :fl:DRIVER.a86 xref print(:fl:DRIVER.lst)
LOC
OBJ
LINE
3
=1
=1
=1
=1
=1
=1
=1 .
=1
=1
=1
=1
=1
=,1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
+1
$TITLE (
NAME
DRIVER
$INCLUDE(:Fl:RAMDEF.EaT)
4
5
6
7
8
9
10
STACK
SEGME~T
STACK
EXTRN
ENDS
11
DATA
22
23
24
25
26
27
28
29
30 +1
31
32
DATA
SEGMENT
EXTRN
EXTNN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTNN
EXTRN
ENDS
file RAMDEF.A86
STACK
BMSTAK:NEAR
PUBLIC
RAM:BYTE,SCRBUF:BYTE.MYBU~BYTE
DEFADR:WORD,DEFBUB:BYTE,DEFNFC:BYTE,DEFENA:BYTE
DEFMOD:BYTE,DEFPAG:WORD,DEFBLK:WORD
BUFADR:WORD,BLKLEN:WORD,ENABLE:BYTE,PAGENO:WORD
BBLNUM:BYTE,NFC:BYTE,MODE:BYTE,STATUS:BYTE,BMCMD:BYTE
INBUF:BYTE,INBUFP:WORD,INBUFC:BYTE
INBUFA:WORD,INBUFL:BYTE
OUTBUF:BYTE,OUTBFP:WORD,OUTBFC:BYTE
OUTBFA:WORD,OUTBFL:BYTE
RDLEN:WORD,WRLEN:WORD
PROMPT:BYTE,LEVMSK:BYTE
BPADR:WORD,USERRG:WORD
POPREGS:WORD,PUSHREGS:WORD
USERBX:WORD,USERDS:WORD,USERBP:WORD,USERSS:WORD
USERSP:WORD,USERIP:WORD,USERCS:WORD,USERFL:WORD
USERPC:WORD
$INCLUDE(:Fl:BMC.EQU)
,
; THESE ARE THE COMMAND EQUATES FOR BMDS
33
,
34
35
36
37
38
39
40
41
42
43
CWBRM
CIZ
CRD
CWD_
CRS
CRBR
CWBR
CWB
CRFS
CAB
CWRS
CRB
CRCD
CFR
CPURG
CSR
44
BPK-72 DRIVER ROUTINES.)
publics from module RAMDEF,
12
13
14
15
16
17
18
19
20
21
45
46
47
48
49
50
debug WORKFILES(:FO:.:FO:)
SOURCE
1
2
0010
0011
0012
0013
0014
0015
0016
0017
0018
0019
001A
001B
001C
001D
001E
001F
PAGE
BPK-72 DRIVER ROUTINES.
M S-86 MACRO ASSEMBLER
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
lOR
llH
12H
13H
14H
15H
16H
17H
18B
19B
lAB
lBB
lCB
lDB
lEH
lFB
, WRITE BOOT LOOP WITH MASK.
;INITIALIZE
;READ
;WRITE
;READ SEEK
;NEAD BOOT LOOP REGISTER
;WRITE BOOTLOOP REGISTER
;WRITE BOOT LOOP
;READ FIFO STATUS
;ABORT
, WRITE SEEK,
;READ BOOT LOOP
;READ CORRECTED DATA
; FIFO RESET
, MBM PURGE COMMAND.
;SOFTWARE RESET
LOC
0001
0002
0004
0008
0010
0020
0040
OOBo
~
0
0001
0002
0004
0008
0010
0020
0040
0080
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
51
52
53
54
55
56
57
5B
59
60
61
62
63
64
65
66
67
6B
69
70
71
72
73
74
75
76
77 +1
2
SOURCE
LINE
OBJ
OOEl
OOliO
PAGE
BPK-72 DRIVER ROUTINES.
MCS-B6 MACRO ASSEMBLER
: I/O PORT ADDRESSES.
·
.
·
BMSTAT
BMDATA
'
EQU
EQU
OE1H
OEOH
BUBBLE MEMORY DEVICE STATUS PORT.
BUBBLE MEMORY DEVICE DATA PORT.
; STATUS WORD BITS
FIFOBT
PARERR
UNCERR
CORERR
TIMERR
OPFAIL
OPDONE
BUSYBT
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
01H
02H
04H
OBH
lOH
20H
40H
BoH
FIRST BIT IS FIFO STATUS
SECOND BIT IS PARITY ERROR.
THIRD BIT IS UN CORRECTABLE ERROR BIT.
FOURTH BIT IS CORRECTABLE ERROR BIT.
FIFTH BIT IS TIMING ERROR BIT.
OPERATION FAIL BIT.
OPERATION COMPLETE BIT.
BUSY BIT.
;
; ENABLE REG BITS
·
INTENA
IE RENA
DMAENA
RSVDl
WBLENA
RCDENA
ICDENA
RSVD2
$EJECT
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
01H
02H
04H
08H
10H
20H
40H
80H
INTERRUPT NORMAL
INTERRUPT ERROR
DMA
WRITE BOOT LOOP
READ CORRECTED DATA
INTERNALLY CORRECTED DATA
l>
'tI
.:..
.....
<0
LOC
OBJ
PAGE
BPK-72 DRIVER ROUTINES.
M S-86 MACRO ASSEMBLER
LINE
78
79
80
61
SOURCE
CODE
BPK72 DRIVER routines
~2
83
84
85
86
87
•
The routines in this module constitute the routines
needed to directly drive the BPK72 bubble memory
development board. This module is designed to be self
contained, and may be called by ANY user procedures.
8&
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
The procedures in this module are
BMCTRL
Perform non-data transfer BHe operations.
BMREAD - Perform data read BHe operations.
BMWRIT - Perform data write BHe operations.
ZAPRKG - Set internal registers to an acceptable value
Parameter passing
•
•
All parameters are passed to the BHe driver routines via
common (PUBLIC) variables. These variables are
BUFADR - The memory address of the input/output buffer
to be used for data transfer operations.
ENABLE - The enabl. byte to be passed to the BHC before
every operation.
PAGENO - The starting block number to be passed to the
BHC before everv operation.
(NOTE: This field
has' no meaning for control operations).
BLKLEN - The number of pages to be transfered by the SHC.(NOTE: This field has no meaning for control
•
operations).
BBLNUH
The bubble select to be transfered to the BMC
before everv operation.(NOTE: This field has
no meaning for SOME control operations).
NFC
- The number of FSA channels passed to the BMC
before every operation. (NOTE: This field has
no meaning for SOHE of the control operatioNs).
~14
115
116
117
118
119
120
121
122
123
124
125
126 +1
SEGMENT PUBLIC
ASSUME DS:DATA,CS:CODE.SS:STACK
;* •••• 5 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •
For a detailed definition of the ENABLE,PAGENO.BLKLEN.
BBLNUM. and NFC fields, refer to the BPK-72 USER MANUAL •
or the Bubble Memory Design Handbook.
•
, ..•...•••..•...•••••....••....•..••••.•.•••••••.......•....•
;
.EJECT
LOC
OBJ
PAGE
BPK-72 DRIVER ROUTINES.
M S-86 MACRO ASSEMBLER
LINE
127
128
129
130
131
132
133
134
135
SOURCE
;
•.........•.•.....••.•.•......
ENTRY POINTS
,
;
,
PUBLIC
ZAPREG,BMCTRL,BMWAIT,BMREAD,BMWRIT.BMWRTB
....•••••...•..... , ...
; MISC EQUATES
136
OOOB
003C
137
138
139
REGl
STATER
140 +1
$EJECT
EQU
EQU
OBH
3CH
FIRST BMC REGISTER TO USE IS BLOCK LENGTh
STATUS WORD ERROR MASK
IGNORE PARITY ERR. REV D OF BMC
BPK-72 DRIVER ROUTINES.
M S-86 MACRO ASSEMBLER
LOC
OBJ
0001
0002
0080
LINE
141
142
143
144
145
146
147
148
149
150
151
152
153
154 +1
PAGE
SOURCE
MODE BYTE DEFINITION
The bits 1n the MODE BYTE specify the type of the data transmission
TO USE, AND WHETHER TO PRINT STATUS AFTER EACH OPERATION.
If Interrupis are enabled in the MODE BYTE, they must also be selected
in the ENABLE BYTE for desired operation to occur.
INTMOD
DMAMOD
DBGMOD
$EJECT
EQU
EQU
EQU
01H
02H
80H
FIRST BIT IN MODE WORD IT INTERRUPT SELECT.
SECOND BIT IN MODE ~ORD IS DMA SELECT.
DEBUG BIT OF MODE WORD
l>
l'
.....
.....
CD
BPK-72 DRIVER ROUTINES.
M S-86 MACRO ASSEMBLER
LOC
0000
0000
0003
0006
0008
OOOB
0000
0010
0012
0013
OBJ
E8D700
AOOOOO
E6El
E80EOO
243C
AOOOOO
7502
F8
C3
0014
0014 A20000
0017 F9
0018 C3
0019
0019
001B
0010
001F
0022
0022
0024
0026
0028
002A
0021
0020
E4El
A880
740B
B9FFFF
E4El
1880
EOFA
E3EA
120000
C3
LINE
E
E
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
SOURCE
;*, ••••••••••••••••••••••••••••
FUNCTION: BMCTRL - PERFORM BMC CONTROL OPERATIONS (NON-DATi TRANSFER).
INPUTS: NONE
OUTPUTS: A=STATUS;F/F(C=l: AN ERROR OCCURED).
CALLS: SNDREG,BMWAIT
DESTROYS: ALL
DESCRIPTION: THIS PROCEDURE IS USED TO PERFORM NON-DATA TRANSFER
BMC OPERATIONS.
BMCTRL:
CALL
MOV
OUT
CALL
AND
MOV
JNZ
CLC
RET
173
E
174
175
176
177
178
179
180
181
HI2
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
19i1
199
200
201
202
203
204
205
206
207
208
209 +1
PAGE
SNDREG
AL,BMCMD
BMSTAT,AL
BMWAIT
AL,STATER
AL,STATUS
SHORT CTRL99
LOAD BMC REGISTERS.
GET COMMAND.
INITIATE COMMAND.
WAIT FOR COMPLETION.
DO WE HAVE AN ERROR?
LOAD STATUS INTO 'A' FO~ EXIT
ERROR, RETURN WITH fLAG SET.
CLEAR CARRY(ERROR FLAG)
AND RETURN
WE HAD AN ERROR, RETURN WITH ERROR FLAG(CARRY FLAG) SET.
THIS IS THE GENERAL ERROR EXIT
l>
CTRL99:
MOV
STC
RET
;.* ••••••••••••
"U
STATUS,AL
SET ERROR FLAG (CARRY FLAG)
AND RETURN.
~I
••••••••••••••
FUNCTION: BMWAIT
INPUTS: NONE
OUTPUTS: STATUS IN A
CALLS: NOTHING
DESTROYS: A,FlF
DESCRIPTION: THIS PROCEDURE WILL WAIT UNTIL THE CURRENT BMC
OPERATION COMPLETES.
CHECK CURRENT STATUS (GOOD ONLY IF RAC=O AND BSY=O)
IN
TEST
JZ
MOV
AL,BMSTAT
AL,BUSYBT
SHORT WAITEX
CX,OFFFFh
WAITPO:
IN
AL,BMSTAT
TEST
"AL, BUSYBT
LOOPNZ WAIT PO
JCXZ
CTRL99
WAITEX:
MOV
RET
$EJECT
STATUS,AL
GET BMC STATUS
CHgCK BUSY BIT.
HOT BUSY, ALREADY DONE.
JUST IN CASE •••
POLLED WAIT MODE
GET STATUS
CHECK BUSY BIT
LOOP IF STILL BUSY
PROBABLY AN ERROR IF CX=O
CORRECT STATUS AND RETURN.
A = STATUS
.....:...
CD
MCS-86 MACRO ASSEMBLER
LOC
002E
002E
0030
0033
0035
0038
003c
003E
0040
0043
0045
004B
0048
004A
004C
004E
0050
0052
0052
0054
0056
0058
005A
005B
005D
005F
005F
0061
0063
0065
OBJ
32CO
A20000
8BD9
E8A200
8B3EOOOO
8CD8
BECO
AOOOOO
E6El
B9FFFF
E4E 1
ABBO
E1FA
E3C4_
BBCB
E4E 1
ABOl
7407
E4EO
AA
E2F5
EBBA
A8BO
75EF
2BD9
EBAD
LINE
E
PAGE
BPK-72 DRIVER ROUTINES.
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256 +1
SOURCE
FUNCTION: BMREAD
INPUTS: CX = NUMBER OF BYTES TO READ, ES SET TO DS
OUTPUTS: A = STATUS; F/F(C=l: ERROR OCCURED)
BX = NUMBER OF BYTES READ
CALLS: SNDREG
DESTROYS: ALL
DESCRIPTION: ALL PARAMETERS ARE PASSED THROUGH COMMON(PUBLIC)
VARIABLES( SEE MODULE HEADER).
MREAD:
XOR
MOV
MOV
CALL
HOV
MOV
MOV
MOV
OUT
AL,AL
STATUS,AL
BX,CX
SNDREG
DI,BUFADR
AX,DS
ES,AX
AL,BMCMD
BMSTAT,AL
MOV
CX,OFFFFH
IN
TEST
LOOPZ
JCXZ
MOV
AL.BMSTAT
AL,BUSYBT
BMRDl
CTRL99
CX,BX
A
=D
CLEAR STATUS.
SAVE BYTE COUNT FOR LOOP
SEND REGISTERS TO BMC.
SET UP DEST BFR PTR (IN EXTRA SEG)
SET EXTRA SEG FOR BYTE MOVE DEST
GET COMMAND
ISSUE IT.
:J>
BMRDl :
WAIT FOR BUSY, BUT NOT FOREVER
CX=O PROBABLY AN ERROR
READ LOOP
,
BMRD2:
IN
TEST
JZ
IN
STOSB
LOOP
JMP
AL,BMSTAT
AL, FIFOBT
SHORT BMRD3
AL,BMDATA
BMRD2
BMWAIT
TEST
JNZ
SUB
JMP
AL,BUSYBT
BMRD2
BX.CX
CTRL99
BMRD3:
$EJECT
GET STATUS
FIFO EMPTY?
YEP, GO CHECK FOR BUSY.
NOPE, GET DATA
STORE IT
AND GO FOR MORE.
XFER DONE, WAIT FOR A GOOD STATUS
NOTHING IN FIFO, IS OP COMPLETE?
CHECK BUSY BIT
STILL BUSY, WAIT.
BX <- , OF BYTES XFERED
l'
.....
.....
CC
LOC
LINE
OBJ
2'H
258
259
260
261
262
263
264
265
266
267
268
269
0067
0067
0069
006C
006E
0070
0072
0075
0079
007C
007E
o07E
0080
0082
0084
0086
0088
0088
008A
008C
008E
008F
0091
0093
0095
0095
0097
0099
009B
009E
009E
OOAO
00A3
00A5
32CO
A20000
8BD9
BO 10
E6E1
886500
8B360000
AOoOOO
E6El
E4E 1
A880
74FA
A801
74F6
E4E 1,
A801
7407
AC
E6EO
E2F5
EB84
E
E
E
32CO
A20000
8BD9
BOlD
;f •••••••••••••••••••••••••••••
FUNCTION: BMWRIT - WRITE BUBBLE MEMORY DATA.
INPUTS: CX = # OF BYTES TO WRITE.
OUTPUTS: A = STATUS; F/F(C=l:ERROR OCCURED), BX=# OF BYTES WRITTEN.
CALLS: SNDREG,BMwAIT.
DESTROYS: ALL.
DESCRIPTION: THIS PROCEDURE PERFORMS A BUBBLE MEMORY wRITE OPERATION.
AN ERROR WILL OCCUR IF THE NUMBER OF BYTES GIVEN FOR THE
WRITE OPERATION EXCEED THE NUMBER THAT THE BHC ilPECTS
(DERIVED FROM COMMAND, BLOCK LENGTH AND NUMBER OF FSA
CHANNELS). OR IF THE NUMBER OF BYTES IS LESS THAN THAT
WHICH THE BMC EXPECTS.
270'
,
BMWRIT:
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
300
301
302
303
304
305
306
307
308
309
310
311
8
SOURCE
271
272
273
274
275
276
277
299
A880
75EF
2BD9
E976FF
PAGE
BPK-72 DRIVER ROUTINES.
M S-86 MACRO ASSEMBLER
=
XOR
MOV
MOV
MOV
OUT
CALL
MOV
MOV
OUT
ALtAL
A
STATUS,AL
BX,CX
AL.CFR
BMSTAT.AL
SNDREG
SL BUFADR
AL, BMCMD
BMSTAT,AL
CLEAR STATUS
IN
TEST
JZ
TEST
JZ
AL.BMSTAT
AL,BUSYBT
WRITOl
AL ,FIFOBT
WRITOl
0
FIFO RESET
SEND REGISTERS TO BMC.
SET UP SRC BFR PTR (IN DATA SEG)
GET COMMAND
ISSUE IT.
l>
WAIT FOR BUSY •••
.:..
.....
WRIT01:
"tI
CQ
AND FIFO READY
KEEP STUFFING DATA INTO FIFO UNTIL DONE OR AN ERROR OCCURS.
(NOTE: BMC GOING NOT BUSY IS AN ERROR).
WRIT03 :
IN
TEST
JZ
LODSB
OUT
LOOP
JMP
BMDATA,AL
WRIT03
BMWAIT
GET STATUS
FIFO READY?
NO. WAIT FOR IT
YES, GET DATA FOR IT
GIVE IT TO BMC
LOOP UNTIL DONE.
XFER DONE, WAIT FOR A GOOD STATUS
TEST
JNZ
SUB
JMP
AL,BUSYBT
WRIT03
BX,CX
CTRL99
OK IF STILL BUSY
BI <- # OF BYTES XFERED
ERROR IF NOT BUSY AND CX NOT ZERO
AL,BMSTAT
AL, FIFOBT
WRIT04
WRIT04:
SPECIAL WRITE FOR BOOT LOOP AND BOOTLOOP REG CMNDS
BMWRTB:
XOR
MOV
MOV
MOV
AL,AL
STATUS,AL
BX,CX
AL.CFR
A = 0
CLEAR STATUS
MCS-86 MACRO ASSEMBLER
LOC
OBJ
00A7 E6E 1
00A9 E82£00
OOAC 8B360000
OOBO
OOBO
OOBl
00B3
00B5
00B8
OOBA
LINE
312
313
314
315
316
317
31~
AC
E6EO
E2FB
AOOOOO
E6E 1
E95CFF
PAGE
BPK-72 DRIVER ROUTINES.
,319
320
321
322
323
324
325 +1
SOURCE
OUT
CALL
MOV
BMSTAT.AL
SNDR~G
SI. BUFADR
F H'O RESET
SEND REGISTERS TO SMC.
SET UP SHC BFR PTR (IN DATA SEG)
nLL FIFO WITH 20/40/41 BnES
WRTBO 1 :
LODSB
OUT
LOOP
MOV
OUT
JMP
BMDATA,AL
WRTBOl
AL. BMCMD
BMSTAT.AL
BMWAIT
STICK IN FIFO.
LOOP UNT IL FILL COUNT=O.
SEND CMND
$EJECT
J>
"U
.:..
.....
CO
LOC
OOBD
OOBD
OOBE
OOBF
OOCO
00C3
00C7
00C8
OOCC
OOCE
0001
0003
0006
0007
0008
0009
LINE
OBJ
326
327
328
329
330
331
332
333
334
335
336
337
5~
BBOOOO
891EOOOO
43
891EOOOO
32CO
A20000
FECO
A20000
5B
58
90
C3
E
E
E
E
340
341
342
343
344
345
346
347
348
349
350
351
352
353 +1
10
SOURCE
;
,
.••.•..•.......•.•••.•.•..•.••
FUNCTION: ZAPREG - ZAP ALL INTERNAL REGISTERS.
INPUTS: NONE
OUTPUTS: NONE
CALLS: NOTHING
DESTROYS: NOTHING.
DESCRIPTION: SET ALL INTERNAL REGISTERS EXCEPT 'ENABLE' TO AN
ACCEPTABLE VALUE.
NOTE:
AN ACCEPTABLE VALUE MAY
OR MAY NOT BE THE ONE DESIRED AS A DEFAULT.
ZAPREG:
PUSHF
PUSH
PUSH
MOV
MOV
INC
MOV
XOR
MOV
INC
MOV
POP
POP
POPF
RET
338
339
9C
50
PAGE
BPK-72 DRIVER ROUTINES.
M S-86 MACRO ASSEMBLER
$EJECT
AX
BX
BX.O
PAGEHO,BX
BX
BLKLEN,BX
AL,AL
BBLNUM.AL
AL
NFC.AL
BX
AX
SAVE FLAGS
SAVE REGISTERS
STARTING PAGE NUMBER
BLOCK LENGTH
BUBBLE NUMBER
=1
=0
# OF FSA CHANNELS
RESTORE REGISTERS.
1 (2 CHANNELS)
l>
........l'
CO
LOC
OODA
OODA
ODDS
OODC
DODD
OODE
ODED
q>
0'1
CD
00E2
00E6
00E8
OOEA
ODED
OOEF
OOF 1
DOn
LINE
OBJ
9C
50
53
51
BOOB
E6E1
8B1EOOOO
8AC3
E 6EO
ADD 000
Bl0q
D2EO
OAC7
E6EO
E
E
00F5 AOOOOO
00F8 E6EO
OOFA
OOFE
0100
0102
0105
0107
0109
01 DB
0100
010E
010F
0110
8B1EOOOO
8AC3
E6EO
AOOOOO
Bl03
D2EO
OAC7
E6EO
59
5B
58
90
0111 C3
E
E
PAGE
BPK-72 DRIVER ROUT IN~S.
M S-86 MAC RO ASSEMBLER
35q
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
319
380
381
382
383
384
385
386
387
388
389
390
391
392
393
39q
395
396
397
398
399
400
401
402
,403
404 +1
11
SOURCE
;**~
••• *** •• *****.**.**.*****k*
F'UNCTlON: SNDREG - FORMAT AND SEND INTERNAL REGISTERS TO BMC.
INPUTS: NONE
OUTPUTS: NONE
DESTROYS: NOTHING.
DESCRlPTlON: FORMAT AND SEND ALL INTERNAL REGISTERS TO THE BMC.
SNDREG:
PUSHF
PUSH
PUSH
PUSH
MOV
OUT
CONSTRUCT AND
MOV
MOV
OUT
MOV
MOV
SHL
OR
OuT
AX
BX
CX
AL,REGI
BMSTAT,AL
SE~D
SAVE REGISTERS
GET FIRST REGISTER ADDRESS.
SELECT IT.
BLOCK LENGTH.
BX.BLKLEN
AL.BL
BMDATA,AL
AL.NFC
CL.4
AL,CL
'AL, BH
BMDATA,AL
HL =
A
GIVE
A
BLOCK LENGTH
BLOCK LENGTH LSB
IT TO BMC.
NUMBER OF FSA CHANNELS.
MERGE INTO BLOCK MSB
GIVE IT TO BMC.
SEND ENABLE BYTE.
MOV
OUT
AL, ENABLE
BMDATA,AL
HL =
A
GIVE
A
AL,BH
MERGE INTO PAGE NUMBER MSB.
GIVE IT TO BMC.
RESTORE REGISTERS AND RETURN.
POP
POP
POP
POPF
RET
$EJECT
STARTING PAGE NUMBER
ADDRESS REGISTER LSB
IT TO BMC.
BUBBLE NUMBER
BX,PAGENO
AL,BL
BMDATA,AL
AL,BBLNUM
CL,3
AL.CL
BMDATA,AL
CX
BX
AX
"'0
......:...
CQ
GET ENABLE BYTE
GIVE IT TO BMC
CONSTRUCT AND SEND ADDRESS REGISTER.
MOV
MOV
OUT
MOV
MOV
SHL
OR
OUT
l>
BPK-72 DRIVER ROUTINES.
M s-86 MACRO ASSEMBLER
LaC
OBJ
LINE
~05
~06
PAGE
12
SOURCE
CODE
ENDS
END
»
l'
.....
.....
CD
M S-86 MACRO ASSEMBLER
BPK-72 DRIVER ROU1INES.
PAGE
13
XRE~' SYMBOL TABLE LISTlNG
NAME
C1l
~
77SEG
BBLNUM.
BLKLEN.
BMCMD
BMCTRL.
BMDATA.
BMRDl
BMRD2
BMRD3
BMREAD.
BMSTAK.
BMSTAT.
BMWAIT.
BMWRIT.
BMWRl'B.
BPADR
BUFADR.
BUSYBT.
CAB
CFR
CIZ
CODE.
CORERR.
CPURG
CRB
CRBR.
CRCD.
C.RD •
CRFS.
CRS
CSR
CTRL99.
CWB •
CWBR.
CWBRM
CWD_.
CWRS.
DATA.
DBGMOD.
DEFADR.
DEFBLK.
DEFIIUB.
DEFENA.
DEFMOD.
DEFNFC.
DEFPAG. '
DMAENA.
DMAMOD.
ENABLE.
F !FOBT.
lCDENA.
TYPE
SEGMENT
V BYTE
V WORD
V BYTE
L NEAR
NUMBER
L NEAR
L NEAR
L NEAR
L NEAR
L NEAR
NUMBER
L NEAR
L NEAR
L NEAR
V WORD
V WORD
NUMBER
NUMBER
NUMBER
NUMBER
SEGMENT
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
L NEAR
NUMBER
NUMBER
NUMBER
NUMBER
NUMBER
SEGMENT
NUMBER
V WORD
V WORD
V BYTE
V BYTE
V BYTE
V BYTE
V WORD
NUMBER
NUMBER
V BYTE
NUMBER
NUMBER
VALUE
OOOOh
OOOOH
OOO{)H
OOOOH
OOEOH
0048H
0052H
005FH
002Eh
OOOOH
00E1H
0019H
0067H
009EH
OOOOH
OOOOH
0080H
0019H
001DH
0011H
0008H
001EH
001BH
0015H
001CH
0012H
001dH
0014H
001FH
0014H
0017H
0016H
0010H
0013H
001AH
0080H
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
OOOOH
0004H
0002H
OOOOH
0001H
0040H
ATTRIBUTES,
XRE~'S
SIZE=OOOOH PARA PUBLIC
EXTRN 16# 346 391
EXTRN 15# 344 372
EXTRN
161 167 229 279 322
131 1651
CODE PUBLIC
,4# 247 296 320 374 379 384 390 395
CODE 233# 236
CODE
243# 249 253
CODE 246 251#
CODE PUBLIC
131 22 "
EXTRN 8#
53# 168 197 202 230 234 244 276 280 282 292 312 323 368
CODE PUBLIC
131 169 193 .. 250 298 324
CODE PUBLIC
131 27,.
CODE PUBLIC
131 3071
EXTRN 23#
EXTRN
15# 226 278 314
'65# 198 203 235 252 283 300
43#
47# 275 311
35#
78# 79 405
SIZE=0112H PARA PUBLIC
61'
48#
45;
39#
46#
36#
42#
38#
49#
CODE
172 179# 205 237 255 303
41#
40#
34#
37#
44#
SIZE=OOOOH PARA PUBLIC
11' 28 79
153#
EXTRN 13#
EXTRN 14#
EXTRN 13#
EXTRN 13#
141
EXTRN
EXTRN 13#
EXTRN 14'
71#
152#
EXTRN 15# 383
58# 245 285 293
75#
»
l'
....
....
CD
MCS-86 MACRO ASSEMBLER
q>
Ol
I\)
NAME
IEHENA.
INBUF
INBUFA.
INDUFC.
I NBUFL.
INBUFP.
INTENA.
1NTMOD.
LEVMSK.
MODE.
MYBUF
NFC
OPDONE.
OPFAIL.
OUTBFA.
OUTBFC.
OUTBFL •
OUTBFP.
OUTBUr.
PAGENO.
PARERR.
POPREGS
PROMPT.
PUSHREGS.
RAM
RCDENA.
RDLEN
REG1. _.
RSVDl
RSVD2
SCRBUF.
SNDREG.
STACK
STATER.
STATUS.
TIMERR.
UNCERR.
USERBP.
USERBX.
USERCS.
USERDS.
USERFL.
USERIP.
USERPC.
USERRG.
USERSP.
USERSS.
WAITEX.
WAITPO.
WBLENA.
WRIT01.
WRITO~ •
WRIT04.
WRLEN
WRTB01.
TYPE
VALUE
NUMBER
0002H
OOOOH
V BYTE
V WOR-D
OOOOH
V BYTE
OOOOH
V BYTE
OOOOH
V WORD
OOOOH
0001H
NUMBER
NUMBER
0001H
V BYTE
OOOOH
V BYTE
OOOOH
V BYTE
OOOOH
V BYTE
OOOOH
NUMBER
0040H
NUMBER
0020H
V WORD
OOOOH
V BUE
OOOOH
V BYTE
OOOOH
V WORD
OOOOH
V BYTE
OOOOH
V WORD
OOOOH
NUMBER
0002H
V WORD
OOOOH
V BYTll
OOOOH
V WORD , OOOOH
V BYTE
OOOOH
NUMBER
0020H
V WORD
OOOOH
OO,OBH
NUMBER
NUMBER
0008H
NUMBER
0080H
V BYTE
OOOOH
L NEAR
OODAH
SEGMENT
NUMBE~
003CH
V BYTE
OOOOH
NUMBER
0010H
NUMBER
0004H
V WORD
OOOOH
V WORD
OOOOH
V WORD
OOOOH
V WORD
OOOOH
V WORD
OOOOH
V WORD
OOOOH
V WORD
OOOOH
OOOOH
V liORD
V WORD
OOOOH
V WORD
OOOOH
L NEAR
002AH
L NEAR
0022H
NUMBER
0010H
L NEAR
007EH
L NEAR
008-8H
L NEAR
0095H
V WORD
OOOOH
OOBOH
L NEAR
BPK-72 DRIVER ROUTINES.
PAGE
14
ATTRIBUTES, XREFS
701
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
17#
181
111
181
17#
691
151#
EXTRH
EXTRN
EXTRN
EXTRN
641
22#
161
12#
161 348.375
631
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
EXTRN
201
191
201
19#
191
151 342 388
591
EXTRN
EITRN
EXTRN
EXTRN
7H
E1TRN
24#
22#
24#
12#
21#
137# 367
72#
76#
EXTRN 12#
CODE 166 225 277 313 362#
SIZE=OOOOH PARA STACK
138# 170
EXTRN 16# 171 180 207 223 273 309
62#
60#
EXTRN 251
EXTRN 251
EXTRN 26#
EXTRN 25#
EXTRN 26#
EXTRN 261
EXTRN 27#
EXTRN 23#
EXTRN 26#
EXTRN 25#
CODE 199 206#
CODE 201# 204
73#
CODE
CODE
CODE
EXTRN
CODE
281# 284 286
291# 297 301
294 299#
211
318# 321
J>
"P
.....
.....
CD
BPK-12 DRJVER ROUTINES.
MCS-86 MACRO ASSEMBLER
NAME
TYPE
VALUE
ATTRIBUTES, XREFS
ZAPREG.
L NEAR
OOBDH
CODE PUBLIC
ASSEMBLY COMPLETE. NO ERRORS FOUND
131 331#
PAGE
15
intJ
APPLICATION
NOTE
Ap·127
December 1982
-Intel Corporation, Inc, 1982
December 1982
ORDER NUMBER 2103O().O()1
6-64
Ap·127
INTRODUCTION
Intel has developed a new, comprehensive power-fail circuit that is incorporated into all Intel Bubble Board Memory products: BPK 72 Bubble Memory Prototype Kit, iSBX™ 251 MULTIMODULE™ board, and the iSBC® 254
MULTIBUS® compatible board. The use of this circuit also is recommended for all customer-designed bubble memory
boards. The ov~rall performance enhancements offered ,by this circuit include improved noise immunity and a factor-offour reduction in the time required to shut down the bubble system.
Scope and Organization
In an effort to focus on implementation details, this application note is organized so that a reader can obtain sufficient information to implement a bubble design without an intimate working knowledge of the power fail circuitry. However, for
those interested, a complete detailed explanation of the integrated powerfail circuitry and the additional external circuitry is
included. Appendix A contains a technical discussion of the effects of power loss on a Magnetic Bubble Chip. In addition,
the previous circuit versions (Revision 0 and Revision 1), along with the present circuit, are completely documented and
compared in Appendix B.
Bubble Memory Operation and the Powerfail Function
The power-fail circuitry is partially integrated into two of the five MBM support components, and additional required circuitry is provided by external components. Historically, several evolutionary improvements have been made in the external
circuitry (see Table 1) to further reduce the risk of data loss following an abrupt power failure.
An essential feature of the bubble memory (MBM) is non-volatile data storage. This non-volatility results from two perma-
nent magnets within the bubble device that produce a magnetic field (bias field) that maintain the magnetic domains, or
bubbles (representing data) in the chip even when power is removed. The bubbles remain stationary in fixed positions until
the data is accessed. To move the bubbles, an in-plane rotating magnetic field is induced by pulsing two mutuallyperpendicular coils surrounding the bubble chip. Sp~ial conductor lines on the bubble chips provide all the current related
functions for reading and writing to the bubble device. A special support IC produces current pulses (swap, relicate, and
generate) to perform these functions. A complete set of support circuits provides the necessary timing and waveforms to
precisely maneuver the bubbles to their desired positions. To prevent bubbles from moving to undesired positions, certain
precautions must be observed.
As power is applied or removed, the system must prevent any current transients in the coils or bubble function conductors.
If power is removed with the coils operating, the system must ensure that the coil currents are shut down in an orderly
fashion to guarantee that the magnetic bubbles come to rest in stable, known positions. The powerfail reset circuit ensures
that the system is powered up in an orderly manner and serves to alert the system should power fail. Both the power-up and
Table 1. Powerfail Reset Circuit Product History
Powerfail Circuit Revision Level
.
Product
BPK 72
0
1
2
July 1979 thru
August 1982
Rev, A thru Rev, G
N/A
September 1982
iSBX™.251 Board
N/A
September 1981
thru October 1982
November 1982
iSBX·251C Board
N/A
N/A
July 1982
December 1980 thru
July 1982
July 1982 thru
November 1982
November 1982
i~BC®
·254 Board
6-65
AP·127
power-down sequences require a finite period of time to complete their functions until the sequence is complete. To allow
proper execution of a power down sequence, the system voltages ( + 5V DC, + 12V DC) must not decay to a level that
prevents operation of the powerfail circuitry and critical bubble memory functions. In most power supply designs, adequate
energy storage is available to provide enough "hold time" to complete an orderly shutdown. However, if de power decays
too rapidly sufficient time may not exist for a proper shutdown and may cause data to be lost within the MBM.
System Description
The basic Intel Bubble Memory system consists of one 7110 magnetic bubble memory and five in,tegrated support components: a 7220-1 Bubble Memory Controller (BMC), a 7230 Current Pulse Generator (CPO), a 7242 Formatter-Sense
Amplifier (FSA), a 7250 Coil Predriver (CPO), and two 7254 quad drive transistor packages. These support circuits are interfaced to the MBM as shown in Figure 1 to form the basic one megabit (l28K byte) system. The support components provide all of the functions necessary for the storage and retrieval of data within the MBM. In addition, two of the support
components, the 7220-1 BMC and the 7230 CPO, contain the integrated powerfail circuitry that facilitates proper power-up
and power-down operations.
OVERVIEW -
POWER UP/DOWN OPERATION
A block diagram of the power fail circuitry for the bubble memory system is shown in Figure 2. The following paragraphs
provide an operational overview of the integrated powerfail circuit and the external circuit requirements.
During a power up sequence, the 7230 holds PWR.FAIL/· active (low) until both supplies are above the minimum required
level. The 7230 contains power supply monitors ( + 5V and + 12V) that determine when either supply falls below threshold
level and activate PWR.FAILI signal accordingly. On power-up, the PWR.FAILI signal is delayed an additional 2 msec by
an external RC network (time delay 1) to allow the 7220-1 substrate bias generator to fully charge. Following this delay, the
positive-going transition on the 7220-1 PWR.FAILI input initiates a 7220-1 power-up sequence;
The RESET.OUTI signal was designed to remain active during the power-up sequence and then to go inactive at the conclusion of the 50 p,s power-up sequence. However, the RESET .OUTI signal is indeterminate during execution of the 7220-1
power-up sequence. A second external RC network (time delay 2) derived from PWR.FAILI ensures that RESET.OUTI is
COIL PREORIVER
7260
FORMATTERI
SENSE AMP
INTEL MAGNETICS
BUBBLE
MEMORY
7242
7110
*" /" denotes an inactive signal.
Figure 1. System Block Diagram
6-66
intJ
Ap·127
7220-1
BMC
RESET
OUTI
TIME
DELAY
2
Cst
7230
r----,
Vee
Voo
..j POWER I
I SUPPLY I
-lMONITORSI
L___ J
I
I
I
I
I
L___ ~~~
__________________ JI
PWR.FAIU
Figure 2. Block Diagram of Powerfail
I
held active (~0.8V) during this time. The RESET.OUTI signaYoccassionally will remain in its active state following a '
power-up sequence; accordingly the first command issued to the BMC during an initialization sequence must be an Abort
command to ensure that RESET. OUT I is deactivated.
The power-up sequence is designed to power the system up in an orderly fashion and to prevent any current transients from
reaching the bubble device. The power-down sequence ensures thaHhe coil drivers are shut down in the proper phase and
that the support circuits are reset. When power fails, the 7230 notifies the 7220-1 by asserting the PWR.FAILI signal. The
7220-1 responds to a negative transition on either the PWR.FAILI input or the RESETI input (external circuit revision
lev"l dependent) and initiates a power-down sequence. If the coils are active (i.e., bubbles propagating), the 7220-1 first terminates the coil drive control signals during the appropriate phase and then resets the support circuits by asserting the
RESET. OUTI signal. The two system supply voltages must not decay faster than the specified rates to ensure the RESETI
input to all the support circuits (excluding the 7220-1) reaches an active level (less than 0.8 volts).
Powerfail Reset Circuit Solution
The external circuitry shown in Figure 3, in conjunction with the integrated circuitry contained in the 7230 and 7220-1, comprises the powerfail circuit (revision 2). This design contains six additional components compared to previous powerfail circuits and includes an 8-pin DIP IC (TI 75463).
This revised circuit has been fully developed and tested by Intel and currently is incorporated in many bubble products.
Operational details are noJ required for the user to implement a custom design using the circuit in Figure 3. However, for
any bubble memory designs that cannot conform to the recommended powerfail circuit, a reader must understand the
system characteristics and requirements prior to choosing an alternative design.
The software implementation details to ensure correct powerfail circuit operation are shown in Figure 4. This routine
should be implemented as a routine for cold start operation (application of power) and warm start operation (a RESETI
pulse applied to the 7220-1 BMC). The voltage decay rates shown in Table 2 also cannot be exceeded.
The power-up routine is based on the typical power-up timing shown in Figure 5. This timing does not assume that a system
reset has been incorporated into the powerfail circuit. If the hardware reset line is used, the user must ensure that the 7220-1
RESET I input is inactive before issuing the first Abort command. In addition, user software always must issue an Abort
command every time the system ,is reset.
6·67
Ap·127
+5V
R1
1K
D1
POWER.
FAIL!
R2
21
1
1----+---1.:>1---""fv---.....-..:,....--_----I
Cx
3.9K
""\...
7230
.011'F
POWERFAILI
BUS
POWER.
FAILI
C1
I2.2I'F
RESET.
I
2
R3
+SV
OUTI
S.1K
7220-1
4
SYSTEM
RESET
02
3
RESETI
Cx
01 1'F
I·
R4
5.6K
7250 RESETI
5
}---+----..-----::--+.... 7242 RESETI
Q1 GATE
R5
33K
NOTES
1. ALL RESISTORS 1/4 WAn, 5% TOL
2 ALL CAPACITORS 10 VDC. 10% TOL
3 01,02 ARE IN914 OR EQUIVALENT
4 ICl IN75463
5 Cx IS OPTIONAL-RECOMMENDED FOR EXTREMELY NOISY
POWER SUPPLY SITUATIONS
6 SYSTEM RESET MAY BE USED AS SHOWN PROVIDED OUTPUT
OF INVERTER IS OPEN COLLECTOR
Figure 3. External Powerfail Circuit Solution
Table 2. Power Supply Decay Rate Specifications During Power·down or Power Failure
Power Down/Powerfaii Decay Rate
Vee
VDD
(volts/msec)
(volts/msec)
Min.
Max.
Min.
None
0.45
None
6-68
I
Max.
1.1
Ap·127
GUARANTEE RESET.OUTI
HAS CHANGED TO
INACTIVE STATE
ALLOW TIME FOR
~:~:f.~~~ ~~ CHARGE-...._ - - , . . - - _..
TO ~2.0VOLTS
Figure 4. Power·up Flowchart
6-69
Ap·127
7230 POWERFAIL
TRIP THRESHOLD
"<..
~~~~I~~---VCCNOD - - - - - - - -
0-2.0V
-.---"1L _ _ _ _ _ _ _ _ _......
PWR'::I:e _ _ _ _
PIN
~2MS......---.+j
I
7220·1
PWR.FAIU
INPUT
PIN
I_
I I
5V
i
:----
- - - - -....j-+L.___--=-+011!!!!==----2.SV
==--T
---------::;;;:::;;;:::;;;:=::;;;:~'"'il
I I
.
I I
7220·1
RESET.OUTI _ _ _ _- - PIN
0-2.0V .... - - - -
O•8V
- - - - - - -~---~--------------------I
---..1
/ <0.8V
;::50pa
2.0V
~~~~~---------~~---------------~~~
BUS
.,lOOMS
I
:
I-
I
72~~'~
••••
_ _ _ _ _ _ _ _'"'\,__r-"'L....J
NOTES:
1. 7220·1 INPUTS SHOULD NOT LEAD Vee BY GREATER THAN 0.5 VOLTS.
2. THE ABOVE SEQUENCE APPLIES ONLY IF THE SYSTEM RESET INPUT IS INACTIVE.
Figure 5. Power-up Timing for Powerfall Reset Circuit (Revision 2)
6·70
inter
Ap·127
The worst case power-down timing sequence is also included in Figure 6. The total system power-down time varies according to whether the coils are active (Le., rotating magnetic field is on) or inactive. The worst case power-down sequence is
guaranteed to be completed provided that the above voltage decay rates are met.
INTEGRATED POWERFAIL CIRCUIT CHARACTERISTICS
Introduction
The following section provides an in-depth look at the input and output characteristics of the support circuits that contain
the integrated powerfail circuitry. A complete understanding of these characteristics establishes the groundwork necessary
for the detailed description of the overall powerfail circuit operation that follows.
VCCIVDD
--
SEE MAXIMUM VccN••
DECAY RATE SPECIFICATION
TABLE 2.
/
,,I
,,
--
I
7220-1 RESETI
(POWERFAI~~U~
----...,1
'
I
.,
7220-1
RESET.OUTI
PIN
I
-----+-----------.,
,
,,
, •
7220-1
PWR.FAIU
..
I,
----"i-----------~l
i
--t~------------
PIN
RESETI
(M~~~:UM)
'
+-i_ _ __
- I 5,. I -+___________-+!..._ _ _ _ _ _
SIG:~~ _ _ _ _
,,
,
'"
1
:
:
~-+I~~
,
2O•• _ _ _..,.~1
,:
Figure 6. Power·down Timing for Powerfal! Reset Circuit (Revision 2)
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-O.8V
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7230 PWR.FAIU OUTPUT
The 7230 Current Pulse Generator PWR.FAIL! output is responsible for indicating when the system supply voltages
( + 5V, + 12V) reach correct operating levels. During power up, normal operation, and power down, an internal zener
reference comparator circuit within the 7230 senses both Vee and VDD and indicates when both levels are above approximately 92 percent of their nominal values. An active state on PWR.FAIL/ indicates one or both dc voltages are below this
threshold. The PWR.FAIL! output is an active-low, open-collector output requiring an external pullup resistor. ,
The PWR.FAIL! output is asserted (active low) as power is applied until the + 5V and + 12V supplies both reach approximately their 92 percent levels at which point the 7230 output transistor switches off to allow the PWR.FAIL! signal to rise
to an inactive level governed by an external RC network. The RC networks on the PWR.FAIL/ line must hold the
PWR.FAIL! signal at an active level for at least 2.0 milliseconds to guarantee adequate time for the BMC to power up. The
7230 PWR.FAIL! output then will remain inactive until one or both system voltages fall below the threshold.
The PWR.FAIL/ output is not an internally latched signal. In other words, the output responds immediately to any transition through the threshold (trip point). The disadvantage to this excellent response capability is that the output will toggle
on transitions through the threshold. Systems should be designed to avoid an extremely noisy power supply or temporary
power loss that could cause the PWR.FAIL! signal to pulse for a very short duration.
During temporary power 10ssJn Revision 0 and Revision I circuits, the PWR.FAIL! input to the 7220-1 could pulse below
VIH (2.5 volts) and initiate a power down sequence. The 7220-1 PWR.FAILI input should remain active until the entire
power down sequence is completed (maximum 110 psec). As detailed later in the 7220-1 PWR.FAIL! input description, if
the 7220-1 PWR.FAIL! input goes inactive during execution of a power down sequence, the sequence is immediately terminated. This type of termination can stop the drive field in the wrong phase and compromise bubble data. The solution is
to use the 7220-1 RESET/ input to initiate a power down sequence rather than the 7220-1 PWR.FAIL! input.
Two important considerations in properly designing a powerfail circuit are I) the accuracy of threshold trip point of
the 7230 PWR.FAIL! output and 2) the behavior of this output at low voltages (below 2 volts).
The worst case threshold level that the 7230 PWR.FAIL! output will trip must be above the worst case operating
limits of the support circ~its with an additional margin to allow for an adequate period of time to complete a power
down sequence (worst case 110 microseconds for revision level I and 2 powerfail reset circuits). In the case of the 7230
CPG and the 7110 MBM, which both have a ±5OTo voltage specification for Vee and/or VDD, special power fail
characteristics are applicable. As shown below, (Table 3) only critical bubble memory functions are guaranteed at
these supply values and not full memory operation.
Table 3. Powerfail Characteristics for 7230 Threshold Trip Point"
Symbol
Min.
Typ.
Max.
Vcc TH
Voo TH
4.43V
10.75V
4.60V
11.10V
4.70V
11.28V
*Powerfall charactenstlcs apply to 7110 bubble memory data Integrity only and not to full memory operation
Second, the 7230 PWR.FAIL! output cannot be guaranteed active (low) until Vee reaches about 2.0 volts since the
output transistor is not operational until that point. As Vee is applied, 'the output is not active and will track (f6110w
within a few tenths of a volt) Vee until Vee reaches approximately 2.0 volts. At this point, the output transistor turns
on and the output goes active (low) and remains low until the system voltages both reach the threshold trip point as
described earlier. A similar response occurs as power is removed. The output transistor turns on and pulls the output
active (low) at the threshold point and remains turned on until Vee reaches approximately 2.0 vqlts where the output
goes inactive (transistor not operating). This operation must be controlled on power-up and depends on the rate of rise
of system voltages. This is because the PWR.FAIL! output is indirectly connected to the RESET/input of the support
circuits (7250 and 7242 and QI reference current switch) through two RC networks in Rev. 0 and Rev. I power-fail circuits. These inputs can rise to as much as 1.5V before the 7230 PWR.FAIL/ output turns on, which is above VIL max-
6-72
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imum (O.SV) thus potentially enabling these circuits; This could result in current transients reaching the drive coils or
bubble function conductors and move bubbles from their rest position resulting in data loss. Observing the rate of rise
specifications protects against this possibility. The revision 2 powerfail circuit eliminates this problem and has no rate
of rise limitation.
7220·1 PWR.FAIU INPUT.
The 7220-1 PWR.FAIL/ input serves a dual function; a positive transition initiates a power-up sequence while a
negative transition initiates a power-down sequence of the bubble memory system. In order for the 7220-1 to become
fully functional an on chip back-bias generator must fully charge the 7220-1 substrate. Therefore, before any sequence
can be executed, including the power-up sequence a time delay is required. An external RC delay on the PWR.FAIL/
input ensures this input is held low «O.SV) at least 2.0 milliseconds after Vee has reached the 7220-1 voltage
specificatiqn range.
The power-up sequence is initiated once the RC network charges to a point where the 7220-1 recognizes a positive transition on the PWR.FAIL/ input. From a cold start (application of power), a positive transition must occur or the controller will not power-up correctly. Once the power-up sequence is completed, the RESET.OUT/ is designed to be
released, however, two possible exceptions exist. First, jf the 7220-1 RESET/is held low during power-up, the 7220-1
internal power-up sequence will be completed however RESET.OUT/ will not be released until RESET/ is inactive.
Second, the 7220-l's internal RESET.OUT/ output transistor may remain turned on dependent upon the power-up
status of certain internal 7220-1 flip-flops. Because of this an ABORT command is always necessary to internally reset
these flip-flops, in turn ensuring release of the RESET.OUT/ output.
If the 7220-1 BMC does not receive a positive transition on PWR.FAILI during power-up, a power-up sequence is not
initiated. This leaves the controller in an unknown state. In this unknown state the controller cannot communicate
properly with the data and control inputs. This can only occur as a result of:
I. "Brown out" -
short duration of power failure in which power drops below specified .levels.
2. Power-up circuit failure - The PWR.FAIL/ pin never reaches VIH (minimum) of 2.5 volts.
The above conditions are resolved by ensuring a positive transition occurs on the PWR.FAIL/ input during power-up
and after brownout. It is necessary to execute a power-up sequence even though power to the system is only interrupted momentarily in order to restOre the 7220-1 to the required internal state.
Once the PWR.FAIL/ positive transition has occured, this input should remain in the inactive state (VIH > 2.5V) as
long as power is applied to the system. If power is removed, it is the negative transition of this input which intitiates
the second function, power down. The function can also be initiated with the RESET/ input of the 7220-1.
An important consideration is how the 7220-1 PWR.FAIL/ input distinguishes between positive and negative transitions. On power up (positive transition), crossing. the input threshold (typically 1.6V to 1.9V) a 'pulse is generated internally which resets the 7220-1 to a known state and initiates a power-up sequence. On power down (negative transition), crossing the input threshold (typically 1.35V to 1.6V with the designed- in hysteresis) the signal initiates a powerdown sequence. If a power-down sequence has been initiated, a positive transition must not inadvertently occur on the
7220-1 PWR.FAIL/ input prior to the power-down sequence completion: A positive transition internally generates a
reset pulse (to halt any current BMC activity) and initiates a power-up sequence effectively terminating a power down
sequence. The result is a possibility of shutting the coil drives down in the improper phase resulting in data loss in the
MBM.
The PWR.FAIL/ input has built in hysteresis to reduce the susceptibility to mUltiple threshold crossings or glitching.
However, the values of hysteresis range from 50 mV to 400 mY. To improve noise and power fluctuation immunity,
the use of PWR.FAIL/ input for initiating a power down sequence was abandoned in Revision I and Revision 2 circuit designs. The 7220-1 RESET/ input is used instead to initiate power down (see next section.)
6-73
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7220·1 RESET/INPUT
The 7220-1 RESET/ input, when asserted, will terminate any current BMC activity and initiate a RESET sequence
(identical to the sequence initiated by the PWR.FAIL/ input going active). After the sequence is concluded, the
RESET. OUT/ is activated to reset the MBM support circuitry. RESET.OUT/ will remain active until RESET/ is inactive.
The RESET/ input is a level sensitive latched input. This is a distinct advantage over the PWR.FAIL/ input; where
any fluctuations of the input once the signal was recognized could possibly terminate the power down sequence. The
RESET/input is latched on the negative edge of the BMC clock and must be active low « .8V) for at least one clock
period (250ns) to guarantee recognition.
7220·1 RESET.OUTI
The RESET .OUT / output has two functions: I) to guarantee the bubble memory system is disabled during power-up
and after power down of the bubble memory system and 2) to provide a pulse (reset) to the support circuits during normal operation. Since the RESET. OUT/ output is an active low open drain, it requires an external pullup resistor to
Vee·
The support circuits controlled by RESET.OUT/ are the 7250 Coil Predriver, the 7242 Formatter Sense Amplifier,
and a VMOS transistor switch which enables a reference current for the 7230. These circuits must be disabled during
the entire power-up sequence and immediately following the conclusion of a power-down sequence to prevent any current transients or extraneous enable pulses. Data loss is a possible consequence should the support circuits not remain
disabled during power cycling.
During power up the RESET.OUT/ signal can not be guaranteed active (low) until the 7220-1 power-up sequence has
executed. Therefore, external circuitry must assure RESET. OUT/ does not rise above V1L maximum (.8V) until 50 I's
after initiation of the power-up sequence. By ensuring the RESET. OUT/ is active during power-up it guarantees the
support circuits are reset to a known state. The 7220-1 BMC is designed with the capability to reset the support circuits
during normal operations by pulsing the RESET.OUT/ 750 I's (3 clock periods). This pulse can occur as the result of
two user issued commands to the BMC: an INITIALIZE command and an MBM PURGE command.
The external RC network on the RESET. OUT/ signal prevents the RESET. OUT/ pulse from going active during its
750 I's duration. In spite of an inability to reset the support circuits by issuing the proper command, correct operation
is guaranteed since the support circuits only require a one time reset signal at power-on.
Additional Bubble Memory Controller Inputs
The 7220-1 has several additional inputs that could indirectly affect power up operation. It is important that the user
exercise caution and adhere to all requirements to ensure proper power-up operations. The following outlines those requirements.
ClK (CLOCK)
The CLK input of the 7220-1 must be present when the positive power up transition occurs at the 7220-1 PWR.FAIL/
input. This requirement allows the BMC to properly execute a power-up sequence. The input requirements are a
precise 4MHz (±.IO/o) with a 50 percent duty cycle (±5%).
DACKI (DATA ACKNOWLEDGE)
The DACK/ input is normally used in conjunction with an INTEL DMA controller chip (8257 or 8237) which
automatically provides drive for this input. However, if DMA is not used a 5.IK pullup resistor to Vee is required.
This requirement prevents erratic BMC operation.
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WAITI
The WAIT! input must also be guaranteed inactive through an external5.IK pullup resistor. It is designed to be used
in parallel controller applications to maintain synchronization between controllers should an error be detected in one
during a data transfer.
CSI, RDI, WRI, AO, 00·08
These inputs require no special considerations other than to observe the VIH minimum specification. This specification prevents an incorrect power-up sequence execution.
_ENERGY STORAGE REQUIREMENTS
The data integrity and non-volatility of the MBM during power down operations is guaranteed by design provided the
voltage decay rates specifications for both Vee and VDD are observed. Most commercially available power supplies
provide enough energy storage to fulfill these requirements. However, some applications may exist where the bubble
memory could suddenly become disconnected from the dc supply; a case where the power supply energy storage is not
of value. In these special applications, the local onboard capacitance must meet the hold up time requirement.
The worst case onboard capacitance values can be determined according to the following equation:
C=
Qmax
V min
I max
~T
max
~Vmin
A worst case calculation must include the following considerations: I) If any additional circuitry exists on the pc board
that uses the same power supplies, the additional current drain must be accounted for and 2) the worst case (minimum)
threshold trip point of the 7230 is used.
The capacitance required on a pc board containing one! megabit bubble memory system is calculated as follows:
CSV
366 X 10- 3 amp x (110 x 10- 6 sec)
0.01
x 5 volts
805/LF
381 x 10 -3 amp x (110 x 10 -6 sec)
C 12V = ------':-7'":""---..,-:---:--'0.01
x 12 volts
Supplemental Power.ail SenSing
In many systems, additional signals are available that provide advanced warning of an imminent power failure or the
existence of an abnormal condition prior to actual loss of dc power (e.g., AC powerfail sensing, AC or DC overvoltage, ambient over!under temperature). These signals are easily incorporated into the powerfail circuit design via
an open-collector gate or inverter connected to the PWR.FAIL! signal bus.
' '
The advantage of utilizing these signals is the bubble memory system can complete a power down sequence prior to
losing dc power. However, local dc powerfail sensing is always required due to the possibility of local dc power loss
without the loss of AC power.
Noise Effects o' Power'ail Circuit Operation
The 7230's powerfail voltage monitoring function is implemented internally with two independent, 10gically-dR'ed
voltage comparators. The comparators respond quickly to a sudden loss of Vee or VDD and therefore can respond to
noise transients on the power supply lines that cross the comparator switching threshold. As much as 100 mV of noise
6·75
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from coil drive switching is not uncommon. Note that the operating power supply tolerance for all INTEL Bubble
Memory products is ±5"7o including up to 50 mV of noise on the power supply lines. This tolerance should not be confused with the operation of the powerfail circuit beyond the normal operating range during power-down operation.
To minimize "nuisance" activation of the PWR.FAILI signal bus, ample high frequency decoupling on the 7230's
Vee and VDD pins should be provided. Typically, 0.01 IIF to 0.1 IIF ceramic disk or mica capacitors are sufficient.
Another source of unwanted powerfail circuit activation is noise that is coupled directly onto the PWR.FAILI signal
bus. This noise is minimized through good printed circuit layout practices and, if required, by the inclusion of a small
capacitor directly on the PWR.FAILI bus. This capacitor slightly increases the power-down time and should be kept
as small as possible (0.01 IIF maximum).
APPENDIX A
TECHNICAL DISCUSSION OF POWER LOSS EFFECT ON 7110
The effects of power loss on an MBM are best understood by describing the way in which the device functions and the
way in which it can lose data.
A magnetic bubble memory device (See Figure 7) consists of a bubble memory chip, two mutually-perpendicular coils,
two permanent magnets, and a shield to provide protection from interference by external magnetic fields. The two
permanent magnets produce an external magnetic field (bias field) that maintains the magnetic domains, or bubbles,
in the chip even when power is removed. To move the bubbles, an in-plane rotating magnetic field is induced by pulsing the two mutually-perpendicular coils.
""PEA
BIAS
LOWER
~
BIAS
MAGNET
~
Figure 7. Device Break·down
6·76
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The bubble memory chip itself consists of a thin magnetic garnet crystal film grown on a non-magnetic gadoliniumgallium-garnet substrate. This thin film possesses a property that magnetic moments associated with each atom in the
single crystal structure have only two possible directions: an upward or downward direction perpendicular to the plane
of the film. This constraint in direction results in only two conditions of magnetization (see Figure 8). These magnetic
moments tend to group rhemselves together into magnetic domains. The size and shape of the domains are determined
primarily by a balancing of several forces that minimize the sum of magnetic energy.
Without an external field, the film surface area of upward domains is equal to that of downward domains and there is no
net magnetic field within the plane of film. Application of an external magnetic field perpendicular to the film causes domains to line up in the direction of the field. As the external field is increased, the downward domains enlarge while the opposing (upward) domains shrink until they finally are reduced to a cylindrical shape. This microscopic magnetized cylinder
opposing the externally applied field is a magnetic bubble. Within the magnetic film, the presence of a magnetic bubble
represents a binary one and the absence of a magnetic bubble represents a binary zero.
The memory function is provided by the bubble. However, an organized means is needed to propagate the bubbles
along certain paths and to provide storage sites. A soft ferromagnetic material (permalloy) is deposited on the thin
garnet film in C-shaped patterns. These patterns are arranged to form shift-register like loops that provide the means
to store and move bubbles. Each pattern is magnetized according to the rotating magnetic field, and the polarity of
each pattern changes instantaneously as the rotating magnetic field vector changes. The rotating field is generated by
driving the X and Y coils with triangular-waveform currents, one lagging the other by 90 0 in phase. A magnetic bubble
propagates from one storage site (permalloy pattern) to the next for every 360 0 of rotation of the rotating field. Each
storage site has a preferred position (home) for the bubble to reside corresponding to zero degrees of the rotating
magnetic field. All bubbles start, stop and are stored in this position.
0,.
In the event of power failure, it is important that the rotating magnetic field is shut down in the proper phase (i.e.,
If an orderly shut down is not complete, the rotating field may be shut down in an improper phase that causes bubbles
to stop in an unstable position within the storage loops. When this type of stoppage occurs, the bubbles either will
come to rest in another, but incorrect, stable position or will leave their original storage loop (possibly contaminating
valid data in another storage loop).
As power is applied, it also is important that the rotating magnetic field does not move (i.e., current transients must be
prevented from reaching the coils). This function also is provided via the powerfail circuitry. Thus, the purpose of the
powerfail circuitry is twofold 1) to prevent any current transients from reaching the X-Y coils or bubble function
generators and 2) to halt the coils in proper phase should power fail.
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EPITAXIAL
..........I----SINGLE·CRYSTAL THIN
FILM (GARNET)
WITHOUT EXTERNAL FIELD
APPLIED
MAGNETIC DOMAINS SHRINK
AS EXTERNAL FIELD IS
APPLIED UNTIL DOMAIN
IS CYLINDRICAL IN
SHAPE (BUBBLE)
HEXTERNAL
1
HEXTERNAL
j
Figure 8. Device Magnetization
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APPENDIX B
DETAIL POWER CIRCUIT DESCRIPTION
As discussed in the Introduction, the powerfail reset circuit actually consists of two portions - an integrated section
and several additional external components. The degree to which external disturbances (noise, power fluctuations) influence system performance depends heavily on the system environment and configuration. Consequently, the reliable
analysis of their effect on system performance is difficult and generally is best accomplished by measurement. In this
Appendix, each revision level of the powerfail reset circuit is detailed. Several timing diagrams based on measurement
and computer simulation also are included.
Powerfall Reset Circuit -
Revision 0
Summary
The overall performance of the powerfail reset circuit (revision 0) is adequate provided that a specific set of conditions
is observed. The requirements are summarized below (Table 4). Noise is also a concern. System generated noise is
typically low level and can usually be neglected in portions of the circuit where the signal levels are high. Often,
however, bubble systems generate significant levels of noise in, a system where signal levels are low. Even low-level
noise can degrade overall bubble memory system performance.
Table 4. Power Supply Requirements for Powerfail Reset Circuit (Revision 0)
Vee
(volts/msec)
Voo
(volts/msec)
Min.
Max.
Min.
Max.
Power-Up Voltage
Rate of Rise
0.11
None
None
None
Power-Down/Power Failure
Decay Rate
None'
0.70
None
.15
\
Noise, power fluctuations, and a rapid decay of voltage are the primary contributors to the incorrect operation of the
first powerfail reset circuit (revision level 0). Since noise and power fluctuations are unavoidable in most practical
systems, techniques for minimizing these effects were developed for subsequent circuits. Note that no bubble memory
is immune to extremely abrupt removal of dc power. All bubble memory systems require a minimal amount of time to
effect an orderly shutdown in order to maintain data integrity.
Subsequent circuit designs have been implemented to minimize system requirements by reducing the overhead required to power-down the bubble system.
The most serious fault of any powerfail reset circuit is where bubble memory data integrity is jeopardized. The first
powerfail reset circuit design (revision 0) could not prevent data loss when:
I) Power was removed too rapidly for the system to ensure proper power-down.
2) Power was applied too sl<;>wly.
3) Multiple threshold crossings or "glitches" occured on the 722~1 PWR.FAILI input while the coils were active.
The first two conditions can be easily prevented by following the requirements shown in Table 4. The third condition
was difficult to reliably prevent and was the motivation for the revision of the circuit.
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AP-127
Power-up
. When power initially is applied to the system (Figure 9), the PWR.FAILI signal is designed to be asserted by the 7230
CPO until both Vee and VDD reach approximately 92 percent of their nominal values. Referring to Figures 9 and 10,
. the 7230 internal PWR.FAIL/ output transistor cannot be guaranteed operational until Vee reaches approximately
2.0 volts. During this indeterminate state of the output transistor, the floating output lags Vee by approximately 0.7
volts. Therefore, the RC networks on the PWR.FAILI signal line (RIICI and R2/C2) begin charging immediately
after power is applied. They continue to charge until the 7230 PWR.FAIL/ output transistor turns on. The 7230
PWR.FAIL/ output goes inactive (transistor off) when both supplies have reached the power-fail trip point. Since the
RESET/ input of the 7242 FSA and the 7250 CPD are tied via the RICIIR2C2 network to 7230 PWR.FAILI output,
these support circuits potentially could be enabled if the 7230 PWR.FAIL/ output were allowed to rise above V1L (0.8
volts). A current transient then could activate the MBM coils or bubble function conductors and cause bubbles to
move to an unstable position. Note that a slow power-on ramp would be the only condition that could prematurely
enable the support circuits.
Once Vee reaches approximately 2.0 volts, the PWR.FAIL/ output transistor turns on to pull the PWR.FAIL/ signal
low until both Vee and V DD reach the powerfail trip point. When the trip point is reached, the output transistor is
turned-off and the PWR.FAIL/ signal is allowed to rise to the inactive level. The 'RC networks continue to hold the
PWR.FAIL/ signal at an active level for at least 2.0 milliseconds after Vee and V DD have reached the trip point level.
The RC delay ensures adequate time for the 7220-1 BMC's substrate bias generator to become fully operational and
fully charge the 7220-1 substrate to its operational bias voltage. At some time before the PWR.FAIL/ signal reaches
the 7220-1 VIH (maximum) of 2.5 volts, the 7220- 1 power-on initialization sequence starts. Up to this point, the 7220-1
is in an indeterminate state and the RESET. OUT/ signal, which is derived from the PWR.FAILI signal should be active. The behavior of the RESET.OUT / signal, however, is similar to the 7230 PWR.FAILI output at low Vee (below
approximately 2.0 volts). As Vee is slowly applied to the system, the RESET.OUT/ output transistor initially is inactive and the pullup resistor forces this output to follow 7220-1 PWR.FAIL input. Once Vee reaches approximately 1.8
volts, the output transistor should turn on (RESET. OUT / active) and remain active until completion of the power up
sequence. During the inactive period, the RESET.OUT / signal is capable of reaching the inactive level and potentially
enabling the support circuits prematurely.
Vee
Vee
Vee
,Voo
Rl
12K
PWR FAILlt-----4---...,..----~--_'i PWR.FAILI
R2
7230
33K
7220-1
+-_r--2,RESET OUTI
REFR.
CSI
R3
3.48K
Voo
Figure 9. Revision 0 Circuit
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7230 POWERFAIL
TRIP THRESHOLD
VccIVoo· - - - - -
72~~'fr~~AIU
_ _ _ _ _ _ _ _""'1
?;2mS-'-"\
O·20V
7230/7220·1 PWR.FAllf
PIN
7220·' RESET.OUTI
SWITCH
0·2.0V
722().1 RESET.OUT/. _ _ _PIN
Power-up Timing
·VCC OR VD D' WHICHEVER IS LAST TO CROSS POWERFAIL TRIP THRESHOLD.
--
VCC/VDD·-~
,
I
I
----;1
I
7230S~'fr~~AIU
-- --
I
I
I
I
7230/7220·1 PWR'FAILI~'
PIN
,
I
I
,
I
i --I
:....
I
722().k~~fgoUTI
I
I
--_-_-_-_-,;;.O.,;;,BV:...._ _ _ _ _ _ _ _ _ _ _ __
300/LS~
I
_ _ _....., _ _ _ _.,..._ _ _ _ _ _
~I-----------
f-- (M~i~",.tM)-1
,
I
7220·1 R~~ET.OUT/----+------------\'
I
N.--------
I
I
,
1-"95'5-1
,:
I
,
I
,
,
1'"".0------
I
-500
-----~.I
Power-down Timing
·VCC OR VDD' WHICHEVER IS FIRST TO CROSS POWERFAIL TRIP THRESHOLD.
Figure 10. Power·up/Power·down Timing (Revision 0)
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At the completion of the power-on initialization sequence, the 7220-I's internal RESET.OUTI output transistor
should be allowed to turn off. However, depending on the power-up state of certain internal 7220-1 flip-flops, this
output may remain active. An Abort command is capable of internally resetting these flip-flops and releasing the
RESET.OUTI output to allow it to rise to the inactive level as determined by the R2/C2 delay network. When
RESET. OUT! reaches its inactive level, the 7242 FSA and 7250 CPD RESET I lines are deactivated and 7230 current
reference switch QI is turned on. The 7242 ENABLE.AI line, which is controlled by the 7220-1, may now be activated; when active, this line enables the 7230 CSI and 7250 CSI (chip select) lines. The system now is fully operational and ready to execute an Initialize command (provided the Abort command had been issued).
Power·down Operation
If either vee or VDD falls below the 7230 powerfail trip level, the internal PWR.FAILI signal in the 7230 is asserted
immediately. However, due to the charge on capacitor CI in the power-up delay network, the PWR.FAILI signal is
prevented from reaching the active low level until CI discharges to V1L (maximum O.BV).
When the PWR.FAILI signal level reaches the logic low-level threshold of the 7220-I's PWR.FAILI input, an internal power-down sequence is initiated within the 7220-1. As discussed earlier in the 7220-1 PWR.FAILI input description, the 7220-1 PWR.FAILI input cannot tolerate any positive threshold crossings during the power-down sequence.
If a positive transition should occur; a power-up sequence will be initiated taking precedence over the power-down sequence currently in progress, and this unorderly shutdown could result in the loss of data.
The execution time of 7220-1 power-down sequence varies according to whether the coils are active (Le., rotating
magnetic field is on) or inactive. If the rotating field is off, the power down sequence is completed in approximately 10
microseconds. If the rotating field is on and a swap operation has not been initiated, the worst-case power-down time
is increased to 26 microseconds; if a swap operation has been initiated, the power-down time sequence requires a maximum of 110 microseconds. The power-down time is shown in Figure 10. Note that the total system power-down time,
since the operation is not complete until the RESET. OUTI signal line is asserted, is the sum of the 7220-I's internal
power-down sequence time and the discharge times for capacitors CI and C2. To ensure proper operation of the
bubble system for data integrity during power-down operations, the power supply maximum decay rates must be
observed.
Powerfail Reset Circuit -
Revision 1
Summary
The powerfail reset circuit (revision I) was designed to reduce the requirements placed on the revision 0 powerfail reset
circuit and to further reduce the risk of data loss during power-up/down operation. Specifically, the improvements
realized were:
1. The possibility of data loss was eliminated provided)hat the circuit was operated within voltage decay rates
specifications.
2. Power-down time was shortened to reduce the energy storage requirements.
;
,
The power supply requirements (shown in Table 5) were relaxed with this implementation, which reduces the system
requirements and the possibility of data loss.
Power·Lip
The power-up operation of the circuit shown in Figure II is unchanged from the power-up operation of the revision 0
circuit. The characteristics associated with the operation of the powerfail reset circuit below approximately 2.0 volts
were not resolved with this circuit solution. If the voltage rise time specifications were not observed, the support circuits could have been enabled prematurely and would allow current transients to reach the drive coils or bubble function conductors (resulting in data loss).
6-82
Ap·127
Table 5. Power Supply Requirements for Powerfail Reset Circuit (Revision 1)
Vee
Voo
(volts/msec)
(volts/msec)
Min.
Max.
Min.
Max.
Power-Up Voltage
Rate of Rise
0.12
None
None
None
Power·Down/Power Failure
Decay Rate
None
0.45
None
1.1
1
PWR.FAILI
Vee
C1
2.2.F
R1
5.1K
R2
100K
~ ~ 1N914
7220·1
-::PWR.FAILI
4
,
RESET I
I
7230
;*~I ~oO~trONAL)
,
R3
33K
I
.~-
RESET.OUT I
1
I
2
RESET.OUTI
C2
1.0 F
Figure 11. Revision 1 Circuit
Power·down
The simple modifications implemented in the external powerfail circuit (revision 1) greatly reduced the overall powerdown operation timing (See Figure 12). This modification made use of the 7220-1 RESET/input to initiate a powerdown sequence instead of the 7220-1 PWR.FAILI input by effectively isolating the 7230 PWR.FAIL/ signal from
delay capacitor CI during power-down operations (eliminating an initial capacitor discharge delay). The 7220-1 BMC
initiates an internal power-down sequence whenever its RESET/input goes active, identical to the negative transition
of the 7220-1 PWR.FAILI input. The difference between these two 7220-1 input signals is that the RESET/ input is
latched and does not recognize a low-to-high transition and power-up therefore must be initiated by the positive transition of the 7220-1 PWR.FAIL/ input. With this circuit, the power-up operation timing was unaltered, and the
power-down operation timing was reduced from approximately 500 microsecpnds in the revision 0 powerfail circuit to
approximately 200 microseconds in the revision 1 powerfail circuit.
6-83
inter
Ap·127
The primary reason for further refining this approach was the increased possibility for a "communication lockout"
by the 7220-1. "Communication lockout" resulted when power was temporarily lost from the system. Specifically, the
following two conditions were responsible for the "communication lockout":
1) The 7220-1 RESET I input was activated low due to power loss (minimum pulse width must be 250 nanoseconds to
ensure that it is latched) and initiated a power-down sequence.
2) The 7220-1 PWR.FAILI discharged but not below the inactive state (0.8 to 2.5 volts, typically 1.5 volts), before
power was n,stored. A power-up sequence could not be initiated to reset the BMC to a known state and communication is "locked out."
VCCIVDO ___ ...
SEE MAXIMUM VccNoo
DECAY RATE SPECIFICATION
TABLE 5
,.J
...
7220·' RESETI
INPUT
(POWERFAILI BUS)
------1
-
7220·'
R~~~~t~
....----~------------,
SWITCH
1
1
1
I·
7220·'
PWR.F~\~
I
-----+;'-------..
1
RESETI
SIG~t~
I
11D,s
(MAXIMUM)-----l·~
1
i
----____________
------~I
1
1
1
1
----+I------------.,..!'---
....
:
:
1
1
- iI
1
----....,--I~---====D.8V
95,s
-1
1
1
1
1
1
1
1
I
I....~--------- 2OD,s - - - - - - - - -___1
Figure 12. Power:down Timing (Revision 1)
6·84
intJ
Ap·127
Even if the circuit is operated within the voltage decay rate specifications, this inconvenience is still possible; the only
solution is to pulse the 7220-1 PWR.FAILI input long enough to discharge CI to a worst case value of 0.8 volt either
by power cycling or external control. This user inconvenience and special system requirement led to the development
of the next powerfail reset circuit.
Power.ail Reset Circuit -
Revision 2
The powerfail reset circuit (revision 2) was developed to eliminate the possibility of data loss during power-up and
power-down operation provided the power supply requirements are observed. The following paragraphs describe the
principals of operation of the powerfail reset circuit. As power is applied or removed, several different signal value
combinations are possible which complicate the analysis of this circuit. For the sake of simplicity, a general overview
of a typical case is included rather than a detailed representation of each case. Throughout this discussion it is helpful
for the reader to refer to the schematic diagram (Figure 3) and the timing diagrams (Figure 5 and 6).
Power·up
The overall circuit operation is complicated by the additional component, ICI. The power-up operation of the revision 2 circuit is very similar to previous circuits, however, the possibility of prematurely enabling the support components is eliminated. Diodes 01, 02 and resistor R5 serve to prevent capacitor C2 from charging beyond a level
(0.8V) that could potentially deactivate the RESET/signal bus to the 7242 FSA, the 7250 CPO and the VMOS transistor switch. Resistor R5 is chosen so that as Vee is applied, diodes 01 and 02 will be forward biased and provide
sufficient voltage drop to prevent capacitor C2 from charging above 0.8V.
Once the 7220-1 power-up sequence is complete or the first Abort command is received, the 7220-1 RESET. OUT/ is
deactivated and capacitor C2 is allowed to fully charge. When the RESET/signal bus reaches an inactive state the
power-up sequence is complete and the system is prepared to accept an Initialize command (provided the Abort command has been issued).
Power·down
The power-down operation of the external powerfail reset circuit (revision 2) is very similar to revision I. The fundamental difference is the ability to maintain a charge on capacitor CI throughout the 7220-1 power-down sequence.
This eliminates any glitch sensitivity or incorrect circuit operation during momentary power loss. The 7220-1 BMC initiates an internal power-down sequence whenever its RESET/input goes active. The 7220-1 RESET.OUT / signal is
gated through ICI and remains inactive during this time period preventing capacitor Cl from discharging. At the completion of the 7220-1 power-down sequence RESET. OUT / signal is pulled low which causes both of the ICI OR gate
outputs to go low. The current sinking capability of these outputs act to quickly discharge capacitors Cl and C2 and
complete the power-down sequence.
6-85
intJ
APPLICATION
NOTE.
AP-150
December 1982
DECEMBER 1982
ORDER NUMBER: 211184..001
INTEL CORPORATION, 1982
6·86
AP-150
8085 TO BPK 72 INTERFACE
INTRODUCTION
Bubble Memory is quickly emerging as the preferred high density storage medium for a variety of microprocessor
applications. Considering their size and reliability, Bubble Memory allows the designer to utilize the advantages of
microprocessors in environments that were not possible using other high density peripheral storage technologies.
Aside from portable or rugged environmental applications, bubbles also open up new design possibilities for desk-top
terminal applications. Some of the benefits that can be realized from the implementation of Bubble Storage are
increased flexibility, reduced maintenance, and non-volatility.
In addition to a one megabit Bubble Memory, Intel magnetics also manufactures a complete family of integratedsupport circuits that simplify the task of designing with Bubble Memory. The family of support circuits provides an
easy-to-use microprocessor interface via a single VLSI component, the Bubble Memory Controller (BMC). The
remaining support circuits are controlled by the Bubble Memory Controller allowing the designer total freedom from
the control signals associated with Bubble Memory technology.
At the component level, the BPK 72 (Bubble Memory Prototype Kit) provides the best opportunity to discover the
potential of bubble storage. The BPK 72 comes complete with all the hardware and documentation necessary to
prototype a one megabit (128K-bytes) Bubble Memory System. After the kit is assembled, the designer is left with the
simple task of interfacing to a host processor.
This application note demonstrates how little effort is required to interface a BPK 72 with an 8085 microprocessor.
The first four sections, "Introduction, BPK 72 Overview, Constructing the Hardware Interface, Implementing the
8085/BPK 72 Software Driver," and Appendix A (software listing) provide all the information necessary to interface
a BPK 72 with an 808~ microprocessor based system. The remaining chapters describe in detail the hardware and
software considerations involved with designing and implementing a Bubble Memory Interface.
A set of generalized flowcharts describing the software driver may also be found in Appendix A to facilitate the task of
intf!rfacing with other microprocessors.
BPK 72 OVERVIEW
The BPK 72 consists ofa one megabit Bubble Memory Module, a lOcm x 10cm printed circuit board (IMB-72), and
the complete family of integrated-support circuits.
A block diagram of the BPK 72 is presented in Figure 1. It illustrates the key components in a one megabit, 128K-byte
Bubble Memory System.
808fUS
I
I
I -
7220
BUBBLE MEMORY CONTROLLER
COil PilEDRIVER
,,~
-+
J.
,
"'" I I
TRANSISTORS
FORMATTERI
~
l
i-
I'ITEL MAGNETICS
IIUBBlE
MEMORV
7242
~
1110
-
!~
7230
CURRENT PULSE
GENEII,uOR
Figure 1. Block Diagram of the BPK 72
6-87
!
ORIVE
TRANSISTORS
l
AP-150
The 7110 Bubble Memory Module is supported by the following integrated circuits:
7220·1 Bubble Memory Controller (BMC)
The 7220-1 provides a convenient microprocessor interface and generates the timing signals necessary for the
proper operation of the remaining support circuitry.
7242 Formatter Sense Amplifier (FSA)
The 7242 is responsible for detecting and enabling the generation of magnetic bubbles within the 7110. The
7242 also performs data formatting tasks and the option of automatic error detection and correction.
7250 Coil Predriver and 7254 Drive Transistors
The 7250 and two 7254s supply the drive currents for the rotating magnetic field that move the magnetic
bubbles within the 7110 Bubble Memory Module.
7230 Current Pulse Generator (CPG)
The 7230 generates a set of waveforms necessary to input and output data from the 7110.
CONSTRUCTING THE HARDWARE INTERFACE
The hardware necessary to interface a BPK 72 with an 8085 microprocessor consists of a few simple connections to
the system bus and the addition of only three integrated circuits; 7406-hex inverteF (open collector), 7430-eight
input nand gate, and an 8284A-Intel clock generator.
A schematic is presented in Figure 2 of the interface logic between a BPK 72 and the demultiplexed bus from an 8085
microprocessor.
The interface uses the ei,ght input nand gate to enable chip-select on the BPK 72 when an I/O instruction is executed
at ports OFEH C"H" designates hexadecimal notation) or OFFH. The address line A8 from the microprocessor bus is
connected to AO on the BPK 72 to select one of two internal ports. If the ports OFEH and OFFH are not available,
simply connectA8 to the input of the nand gate and move a higher order address line (A9-AI5) toAO on the BPK 72.
In the event that the I/O addresses are changed, the user must enter the new port locations into the software driver
(see Appendix A). The I/O port locations are initialized as equates at the beginning of the program. All system
dependent variables have been parameterized whenever possible.
.
The designer has the option of memory mapping the BPK 72 or utilizing 2 of the 256 I/O ports available on the 8085.
The I/O ports were chosen for this interface to simplify the address decoding and to provide easy access to existing
systems.
POWER SUPPLY REQUIREMENTS
The BPK 72 operates on standard + 5V and + 12V DC power within a 5% tolerance. The worst case power
consumption is a follows:
+ 5VDC = 2 watts maximum
+ 12VDC '" 5 watts maximum
When power is applied or removed from a Bubble Memory System, the rotating magnetic field within the 7110 Bubble
Memory is held in the proper phase to insure non-volatility. This is accomplished through the use of a power fail reset
circuit. The following power supply specifications must be observed to effectively support the power fail circuitry:
A. VDD
+ 12V, ±5% tolerance
Power off/power fail voltage decay rate-less than 1.1 volts/millisecond
B. VCC = +5V, ±5% tolerance
Power off/power fail voltage decay rate-less than 0.45 volts/millisecond
C. Voltage sequencing-no restrictions
D. Power on voltage rate of rise-no restrictions
=
6·88
AP-150
8085 TO BPK 72
HARDWARE INTERFACE
BPK72KIT
El EDGE CONNECTOR
~apXl
lm8~+SV
24 MHZ
: ~GND
8085 MICROPROCESSOR BUS
~x2
101M
C1
5pI
A1S
~FIC
~EFI
UJ=:SV
A14
GND
A13
CLK
PCLK
4 MHZ
( F ) - +SV
~O
All
(4)
2
~'7
U1r-
A12
4
,-1 CSYNC A
( B , l ( ) - +12V
Al0
(Y) Cst
A09
(10) AU
A09
(18) D7
D07
(17) De
D06
(16) OS
DOS
D04
D03
(15) D4
7
(14) D3
2
2
0
(13) D2
D02
(12) D1
D01
(11) DO
DOG
(J) RDI
lID
(K)
WII
7408
RESET OUT
U3
+S~~
Rl
GND
I
'AU ~ 0, PORT ADDRESS OFEH
AU ~ 1, PORT ADDRESS DFFH
,AU WITH RESPECT TO THE BI'I(.72.
WRI
(H) RESETI
+SVDC
I
S.1K
(L) DACK/
(E) 7242 CSI
(1,22,A,p,r GND
Jl
7242
J
Figure 2. Hardware Interface
The interface designer should verify that the system power supply decay rates meet the specifications previously
listed. To simulate worst case conditions, connect a 2 watt load on the + 5 volt supply and a 5 watt load on the + 12 volt
supply. The power supply decay rates can be easily measured during the removal of power with a standard
oscilloscope. Do not use the IMB-72 board with the 7110 dummy module during the power supply decay measurements. The dummy module is not capable offully loading the power supplies. No attempt should be made to use. the
IMB-72 board with the 7110 Bubble Memory until the power supply decay rates have been verified.
Note: The procedure outlined in Appendix B, "Powering-Up for the First Time," should be performed prior to
installing the 7110 Bubble Memory Module in a newly assembled IMB-72 board.
All BPK 72 kits Rev G or earlier contain an older version of the power fail circuit. The revision letter can be found on
the solder side ofthe IMB-72 printed circuit board. The old version performs the power fail protection function, but
has limited immunity to power supply noise. An IMB-72 printed circuit board containing the new power fail circuit is
available from Intel Magnetics. A new board, additional hardware, and documentation are available at no cost to
customers with older BPK 72 kits containing the original power fail circuit. Customers are urged' to utilize the
improved power fail circuit in all future designs.
.
Intel Magnetics Applications
3065 Bowers Avenue SC2-962
Santa Clara, CA 95051
(408) 987-7602
6-89
AP-150
Table 1. 8085/BPK 72 Interface Parts List
Item
Description
Quantity
Reference
Manufacturer
I
IC-7430-8 input nand gate
I
U1
any
2
IC-8284A-clock generator
I
U2
Intel
3
IC-7406-hex inverter open collector
I
U3
any
4
Crystal-24.0000MHz fundamental mode, series resonant
I
YI
any
5
Resistor-5.1Kohm, 1/4W, 5%
I
RI
any
6
Mica Capacitor-5pf, IOOVDC, 5%
I
CI
7
Edge connector, 44 pin
I
EI
any
TRW, CINCH
#50-44B-IO
Ir.'IPLEMENTING THE 8085/BPK 72 SOFTWARE DRIVER
An 8085 to BPK 72 software driver program listing is presented in Appendix A. The driver consists of a set of
subroutines that can be called to perform commonly used Bubble Memory commands. A detailed description and
flowchart of each subroutine is provided with the program listing. The software driver is relocatable and may be
linked with other programs. The name of the program is "BPK72." It begins at 0800H and requires less than lK bytes
of memory allocation.
The software driveI: is written in 8085 assembly language. It can be easily incoI:porated into existing systems as part of
a utility program to transfer data between the BPK 72 and the 8085's addressable memory. The subroutines have been
designed to eliminate the need for any further software development concerning the operation of the BPK 72.
Assembly was chosen over higher level languages to provide the most efficient and portable code. With only minor
modifications to the parameterized variables, the program, "BPK72," wilfrun on almost any 8085 based system.
The following subroutines in the program "BPK72" will now be discussed:
INBUBL-Initialize Bubble Memory
WRBUBL-Write Bubble Memory data
ROBUBL-Read Bubble Memory data
ABORT-Abort present command, reset BPK 72
INITIALIZING THE BUBBLE
After powering up, the BPK 72 must be initialized before any data transfers can begin. Initialization is needed to
synchronize the 7220 Bubble Memory Controller with the data in the 7110 Bubble Memory storage loops and also
because the 7110 employs redundancy. The 7110 Bubble Memory contains 320 storage loops. However, only 272 of
the 320 loops are necessary for a 100% functional one megabit part. The additional 48 loops provide a 15%
redundancy. Redundancy is used to significantly increase the yield of Bubble Memory modules during manufacture.
A map of the active and inactive loops is placed on a label attached to the case of the 7110. The same map is also placed
in the 7110 durinll final test. When the system is initialized, the 7220 reads the map (boot loop) from the 7110 and
decodes it. The boot loop is transferred from the 7220 into a pair of boot loop registers in the 7242 formatter sense
amplifier. The boot loop registers are used to format data to insure that only functional loops are enabled during read
or write operations.
6·90
AP-150
Only one call to the initialization subroutine, INBUBL, is necessary to initialize a BPK 72. The following is an
example of how to call INBUBL:
8085 Addressable Memory
8685 Microprocessor
BReg= 10H CReg= OOH------...
.. lOOOH=
lOOlH =
1002H =
DReg= XXH EReg= XXH
1003H =
1004H =
HReg= XXH LReg= XXH
A Reg = will return the
value oftpe7220's
status register.
OlHBlockLengthRegLSB
lOH Block Length Reg MSB
OOH Enable Reg
OOH Address Reg LSB
OOH Address Reg MSB
XX-Don't care
No effect on the operation
of the BPK 72.
Call INBUBL.
The example shown above demonstrates how to set up the B-C registers prior to calling the initialization subroutine,
INBUBL. The B-C register pair must contain the address of the first of five consecutive locations within the 8085's
addressable memory. In this example, the B-C registers are pointing to the first of five memory locations starting at
1000H. The data contained in 1000H through 1004H is a memory image of the parametric registers within the Bubble
Memory Controller. The parametric registers contain a set of flags and parameters that determine exactly how the
7220 will respond to a software command.
Note the values used for the block length and address registers. These values must always be used during the
initialization process with a one megabit Bubble Memory System. The enable register is shown with a OOH indicating
the absence of error detection and correction. The 7220 and 7242 provide an optional error detection and correction
feature to enhance data integrity. It is recommended that first time users begin without the use of error correction.
Later on if error correction is desired, a 20H should be placed in the memory location designated as the enable
register. A discussion concerning the use of error correction may be found in the section titled, "Communicating with
the 7220."
Figure 3 illustrates the sequence of program flow necessary to initialize a Bubble Memory System using the
subroutine INBUBL. Note that Figure 3 includes a test of-the Bubble Memory Controller's status register. The status
register is separate from the parametric registers and contains information about error conditions, completion or
termination of commands, and the 7220's readiness to transfer data. To simplify the task of verifying a successful
initialization, INBUBL returns the value of the 7220's status register to the calling routine through the 8085's "A"
register. A successful initialization will return a 40H status. All other values indicate a BPK 72 system failure. Consult
Appendix C in the unlikely event that the subroutine INBUBL fails to return a successful status.
READING AND WRITING
Only one call to the subroutine RDBUBL or WRBUBL is necessary to transfer data between the BPK 72 and the
8085's addressable memory.
Like many high density peripheral storage devices, Bubble Memory data is organized into pages rather than bytes.
The 7220 Bubble Memory Controller partitions the one megabit Bubble Memory into 2048 pages of either 64 or 68
bytes in length. The page length is dependent upon the use of automatic error detectjon and correction-64 bytes
with error correction and 68 bytes without. Data transfers are specified in terms of whole pages. Therefore the
minimum amount of data that can be transferred from one read or write command is 64 or 68 bytes.
The parametric registers are used to communicate to the controller which page or pages will be transferred during a
read or write command. The address register LSB and the first three bits of the address register MSB define the
starting page address for read or write commands. The block length register determines how many pages will be
transferred starting at the location defined by the address register. Theoretically, data transfers can range from 1 to
2048 pages in length. However, this application limits the maximum data transfer between the BPK 72 and the 8085's
6-91
AP·150
SET UP MEMORY
IMAGE IN 8085 RAM
OF THE 7220
PARAMETRIC REGS.
>_N:!:O~. SEE APPENDIX C
Figure 3. Initializing the BPK 72
memory to no more than 255 contiguous pages. This limitation results from the need to prevent data transfers that
could exceed the addressable memory space of the 8085. The block length register LSB may be assigned any value
between 1 and 255 depending on the size of the transfer. A detailed description of the parametric registers may be
,found in the section titled, "Communicating with the 7220."
The following is an example of how to use the Read Bubble Memory subroutine, RDBUBL, to transfer the first 16
pages (OOH-OFH) of data from the BPK 72 to the 8085's addressable memory, starting at location 2000H:
8085 Addressable Memory
8085 Microprocessor
B Reg = 10H C Reg = OOH
.. 1000H =
1001H =
DReg = 20H E Reg = OOH~ 1002H =
.
1003H =
H Reg = XXH L Reg = XXH
1004H =
A Reg = will return the
value of the 7220's
status register.
lOB Block Length Reg LSB
lOH Block Length Reg MSB
OOH Enable Reg*
OOH Address Reg LSB
OOH Address Reg MSB
2000H = start data transfer
243FH = last data transfer
(1088 byte transfer)
XX-Don't care
No ~ffect on the operation
of the BPK 72.
*-Assumes that the BPK 72 was.
initialized without error
correction.
Call RDBUBL.
6·92
AP-150
The Write Bubble Memory subroutine, WRBUBL, can be substituted for the call to RDBUBL to transfer data from
the 8085's addressable memory to the first 16 pages in the BPK 72.
The example shown above demonstrates how to set up the B-C and D-E registers prior to calling a read or write
subroutine. Just as in the case of initialization, the B-C registers contain the address of the first of five consecutive
memory locations within the 8085's addressable memory. The data contained in the memory addressed by the B-C
registers is used to load the 7220's parametric registers. The D-E register pair contains the address of the first byte of
data to be transferred to or from the 8085's addressable memory.
Figure 4 illustrates how the read and write subroutines, RDBUBL and WRBUBL, should be called from another
routine. The flowchart includes a program path to handle errors in the unlikely event that the read or write
subroutines fail to return a successful status. First time users can omit the additional program flow for preliminary
evaluation. The next section, "Checking the Status," describes the appropriate status values necessary to verify a
successful data transfer.
EXECUTE
COUNTER ~ 2"
WRBUBL42H
DECREMENT
EXECUTE
COUNTER"
~_
_.....L_ _ _ _
SEE APPENDIX C
"MAY BE OMITTED FOR
PRELIMINARY EVALUATION
Figure 4. Reading and Writing to the BPK 72
6·93
AP~150
CHECKING THE STATUS
After calling a subroutine to initialize, read, or write Bubble Memory data, the 7220's status register should be read to
verify that the command was successfully executed. Note that flowcharts 1 and 2 include a test of the status register
to detect for any errors. In order to facilitate the task of verification, each of the commonly used subroutines in the
program "BPK72" return the contents of the 7220's status register to the calling routine through the 8085's "A"
register. It is the responsibility of the calling routine to verify the success of each subroutine. A list of acceptable
status register values for each of the subroutines in the program "BPK72" is presented in Table 2.
Table 2. Acceptable Status Register Values
Subroutine
Acceptable Status
Register Value(s)
Comments
INBUBL
40H
OP-complete
WRBUBL
40H
42H
OP-complete
OP-complete, parity error
RDBUBL
40H
48H
OP-complete
OP-complete, correctable error"
ABORT
40H
OP-complete
\
"Level I error correction only
If any read errors are encountered during the transfer of data, they will almost always result from external noise
interfering with the signal path between the 7110 Bubble Memory and the 7242 formatter sense amplifier. Since the
data within the Bubble Memory is usually correct, a second attempt to transfer data should be ,successful. Figure 4
illustrates the use of the ABORT command to reset the Bubble Memory Controller before making another attempt to
read or write Bubble Memory data.
Service information is presented in Appendix C in the unlikely event that any of the subroutines in Table 2 do not
function properly.
\
7220 MICROPROCESSOR INTERFACE OVERVIEW
The key to any interface incorporating a BPK 72 is the Bubble Memory Controller. The controller provides a
complete interface to a TTL level microprocessor bus that allows the designer total freedom from the intricate timing
and waveforms necessary to support a Bubble Memory System. A block diagram of the 7220 Bubble Memory
Controller is presented in Figure 5.
,
The 7220 interface circuitry consists of one 8-bit bidirectional port. The port provides access to internal registers. The
, address line AO is used to select either the command/ status or parametric/ data registers. A command register is used
to issue instructions such as read or write Bubble Memory data. The status register provides information about the
cOlI!pletion or termination of commands and the 7220's readiness to transfer data. The parametric registers contain a
set of flags and parameters that determine exactly how the 7220 will respond to a software command. The data ,
register is actually a forty byte FIFO to buffer the timing differences between the 7110 Bubble Memory and a host
processor. In order to transfer data to (from) the BPK 72, the host processor must load the parametric registers
followed by issuing a read or write Bubble Memory data command.
.
,
To maintain design flexibility, the 7220 Bubble Memory Controller provides the user with three different modes of
data transfer:
1. DMA, direct memory access
2. Interrupt-driven
3. Polled 110
6-94
AP-150
x+
X-
v:+-
v=
TMA
mT
BUBBLE
SIGNAL
DECODER
WAIT
SEQUENCER
DETON
ERRFlG -
CONTROL:-=B::-US'___--l
Vee - GND--
REP EN
8OOl1N
SWAP EN
BOOT SW EN
SHIFT CLK
SYNC
C/O
-CLK
MBM
ADDRESSING
lOGIC AND
RAM
STATUS REGISTER
L-_"""'_ _ _ _ _---j PACR~~~~~~ ~~~I~~~~S
08
SYSTEM
BUS
INTERFACE
DACK DRQ
INT
010
Figure 5. BlocK Diagram of the 7220 Bubble Memory Controller
In the DMA data transfer mode, the 7220 operates in conjunction with a DMA controller (such as Intel's 8257) using
the DRQ (data request) and DACK (data acknowledge) lines for handshaking. With the help of a DMA controller, the
7220 transfers the data to (from) the host processor's memory. Once the data transfer begins, program intervention is
not required until the entire data transfer has been completed.
In the interrupt mode, the 7220 along with an interrupt controller (such as Intel's 8259) uses the DRQ (data request)
line to initiate a data transfer. The DRQ line becomes active when the 7220 is ready to send or receive a burst of data. A
typical data burst is 22 contiguous bytes for an interrupt-driven interface. A set of software drivers are also necessary
to service the interrupts to coordinate the transfer of data between the 7220 and the memory associated with a host
processor. One advantage to the interrupt mode is multitasking. Since the host processor is only servicing the 7220
during cJata transfers, dead time between data transfers can be utilized for other processor tasks.
A polled mode interface reads the 7220 status register to determine when to transfer one byte of data. Of all the
interfac;e modes, polled I/O is the simplest configuration to implement. No special hardware or external controllers
are necessary to interface the 7220 with a microprocessor. The major portion of a polled mode design is the software.
Just as in the interrupt mode, a set of software drivers are required to read and write data to the 7220.
6-95
AP-150
This application uses a polled mode configuration. The polled I/O data transfer mode was selected over DMAand
interrupt-driven to simplify the interface design. A polled mode interface does not require the use of a DMA or
interrupt controller. Furthermore, the polled mode interface provides the most flexibility for incorporating a BPK 72
into existing 8085 systems. Since the majority of a polled mode design consists of software, simple program
modifications to accommodate existing systems can be easily entered into the software driver provided in AppendixA.
In terms of performance, the polled I/O transfer mode is the lowest compared to DMA or interrupt-driven. The DMA
and interrupt modes offer the advantage of multitasking. However, the average access time and data transfer rate
remain the same for each data transfer mode. The following formulas and examples demonstrate how to calculate the
transfer time for a one megabit Bubble Memory System:
READ
N-page transfer:
Transfer time = seek time + 8.7 ms + 7.5 ms (N-l)
WRITE N-page transfer:
Transfer time = seek time + 7.5 ms (N)
Average seek time = 41 ms
Worst case seek time = 82 ms
Average data rate = 8.5 K-bytes/sec
For Example:
A. Time to read 1 page (assuming avg seek time):
Transfer time = 41 ms + 8.7 ms = 49.7 ms
B. Time to write 1 page (assuming avg seek time):
Transfer time = 41.ms + 7.5 ms = 48.5 ms
C. Time to read 10 contiguous pages (assuming avg seek time):
Transfer time = 41 ms + 8.7 ms + 7.5 ms (10-1) = 117.2 ms
D. Time to write 10 contiguous pages (assuming avg seek time):
Transfer time = 41 ms + 7.5 ms (10) = 116.0 ms
HARDWARE INTERFACE DESCRIPTION
To simplify the task of interfacing a BPK 72 with a microprocessor, the 7220 Bubble Memory Controller provides a
convenient set of TTL signals that may be directly connected to a system bus. The interface signals on the BPK 72
necessary to implement a polled mode configuration are presented in Table 3.
PARITY BETWEEN THE 8085 AND BPK 72
The 7220 has the capability of generating and detecting odd parity using the bidirectional data line D8. The parity bit
may be used to increase the reliability of the data path between the 7220 and a host processor. During data transfers,
odd parity is generated for read operations and tested for write operations. The host processor may read the 7220
status register to determine if a parity error occurred during a write operation. Parity is typically implemented when a
long transmission path exists between the host processor and the 7220. Since most systems utilize a simple edge
connector backplane and a short transmission path (less than 18 inches), parity is not necessary. Parity is not
implemented in this application to minimize the hardware ,complexity.
The parity bit, D8, is not stored within the 7110 Bubble Memory module. A separate and more effective error
detection and correction feature is available as an option to increase the data integrity within the 7110. See the section
titled, "Communicating with the 7220" for further details about the option of automatic error detection and
correction.
6-96
AP-150
Table 3. BPK 72 Polled Mode Interface Signals
Signal
Function
AO
Address line
AO = O. Selects the FIFO data buffer or the parametric registers.
AO = I Selects command/status regIsters.
00-07
8 bit bidirectional data bus.
08
Optional odd parity bit, not used in this application.
CS/
Chip select input. A logic high will tri-state the 7220 interface signals. (Slash, "/" designates a low active
signal, system ground)
RD/
Read 7220 registers or data FIFO.
WR/
Write 7220 registers or data FIFO.
DACK/
DMA acknowledge. If DMA is not used, DACK/ requires an external pullup resistor to VCC (5.1 Kohm).
CLK
4 MHz TTL level clock.
Clock period = 250 ns, 0.25 ns tolerance.
Duty cycle = 50%, 5% tolerance.
RESET/
A low on this pin forces the interruption of any 7220 activity, performs a controlled shut-down, and initiates a
reset sequence. The next instruction following RESET/must be an abort command.
7242 CS/
7242 chip select signal is used to select banks of 7242s. 7242 CS/ must be tied low (system ground) for a single
bank configuration.
4 MHZ CLOCK
The BPK 72 requires an external 4 MHz (may be asynchronous with respect to a host processor) TTL level clock, The
specifications for the period ,and duty cycle are presented in Table 3, The 7220 uses the external clock to generate the
timing signals that control the rotating magnetic field within the 7110 Bubble Memory~ For reliable operation, the
clock tolerances must be observed to assure that the rotating field is stai:)le and accurate.
An Intel integrated circuit, 8284A clock driver, is used to generate the 4 MHz external clock. The 8284A along with a
24MHz series resonant crystal (fundamental mode) will provide a precise and accurate clock for any interface
incorporating a BPK 72. The circuit configuration for the 8284A is illustrated in Figure 2. Other techniques of clock
generation are acceptable as long as the duty cycle and period are within the specifications listed in Table 3.
SOFTWARE INTERFACE DESCRIPTION
The software driver presented in Appendix A contains the following subroutines that may be called from another
routine:
* INBUBL
-Initialize the BPK 72.
-Read Bubble Memory data.
- Write Bubble Memory data.
-Abort present command, reset BPK 72.
- Reset 7220 FIFO data buffer.
** FIFORS
- Write 7220 FIFO data buffer.
** WRFIFO
-Read 7220 FIFO data buffer.
** RDFIFO
***f** WRBLRS -Write 7242 boot loop registers.
** RDBLRS
-Read 7242 boot loop registers.
***f** MBMPRG-Bubble Memory purge command.
*** RDBOOT -Read Bubble Memory boot loop.
*** BOOTUP -Write Bubble Memory boot loop.
* Most commonly used commands
** Necessary to verify successful assembly of the BPK 72 (see .Appendix B)
*** Diagnostic routines (see Appendix C)
* RDBUBL
* WRBUBL
* ABORT
6·97
AP-150
Each of the subroutines listed above is described in further detail in Appendix A. Along with each subroutine is a
generalized flowchart displaying the program flow. The user is encouraged to read the software driver to better
understand the software interaction necessary to interface a BPK 72 with an 8085 microprocessor.
COMMUNICATING WITH THE 7220
Some additional background is necessary to understand the operation of the 7220 Bubble Memory Controller. Figure
6 illustrates the user-accessible registers that control and format the flow of data between the 7110 Bubble Memory
and a host processor.
The address assignments for the user-accessible registers within the 7220 are presented in Table 4. The registers are
listed in two groups. The first group (status, command, register address counter) consists of those registers that are
selected and accessed in one operation. The second group contains the FIFO data buffer and the parametric registers
(utility, block length, enable, address), they are selected according to the contents of the register address counter
(RAC).
Table 4. Address Assignments for the User-Accessible Registers
AO
D7
D6
D5
D4
D3
D2
D1
DO
Symbol
I
0
0
I
0
0
I
S
S
S
Name of Register
Read/Write
0
I
C
C
C
C
CMDR
Command Register
Write Only
0
0
B
B
B
B
RAC
Register Address Counter
Write Only
S
S
S
S
S
STR
Status Register
Read Only
NOTES:
SSSSSSSS
CCCC
BBBB
B3B2BlBO
LSB
MSB
8·bit status information returned to the user from the STR
=
= 4-bit command code sent to the CMDR by the user.
= 4-bit register address sent to the RAC by the user.
= 4-bit contents of RAC at the time the user makes a read or write request with AO = O.
= Least Significant Byte
= Most Significant Byte
Table 5. Parametric Registers and FIFO Data Buffer
,
RAe
AO
B3
B2
B1
BO
0
I
1
1
1
1
1
0
0
1
1
1
1
0
I
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
Symbol
UR
BLRLSB
BLRMSB
ER
ARLSB
ARMSB
FIFO
Name of Register
Utility Register
Block Length Register LSB
Block Length Register MSB
Enable Register
Address Register LSB
Address Register MSB
FIFO Data Buffer
Read/Write
Read or Write
Write Only
Write Only
Write Only
Read or Write
Read or Write
Read or Write
To successfully implement the hardware and software presented in this application, certain restrictions are placed
on the contents of the user-accessible registers. Each of the user-accessible registers and any necessary restrictions will now be discussed in further detail.
COMMAND REGISTER
The 7220 command set consists of 16 commands identified, by a 4 bit command code. A list of the commands is
presented in Table 6.
'
6·98
AP.150
4-BIT ADDRESS
FIFO DATA BUFFER
PARAMETRIC REGS
WR------,
00(0-8)
INTERNAL BUS (S-BIT)
-.1ItI
WR - - - - - - - - '
AO - - - - - - - - - - - - ' - - - - '
Figure 6_ 7220 User Accessible Registers
Table 6_ 7220 Commands
D3
D2
D2
D1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
1
1
Command Name
Write Bootloop Register Masked
Initialize
Read Bubble Data
Write Bubble Data
Read Seek
Read Bootloop Register
Write Bootloop Register
Write Bootloop
Read FSA Status
Abort
Write Seek
Read Bootloop
Read Corrected Data
Reset FIFO
MBM Purge
Software Reset
The commands liste!f in Table 6 are provided for reference purposes only. The software driver in Appendix A consists
of a series of subroutines that automatically issue the appropriate commands to perform a data transfer.
The function of each command is usually apparent from the command name (e.g., initialize, read bubble data, write
bubble data). Additional detail concerning the function of each command may be found in the BPK 72 user's manual.
REGISTER ADDRESS COUNTER
The register address counter consists of a 4 bit address that points to one of the six parametric registers:
Utility register (UT)-The utility register is a general purpose register available to the user in connection with Bubble
Memory System operations. It has no direct effect on the oper.ation of the 7220. It is provided as a convenience to the
user.
6-99
AP-150
Block length register (BLR)-The contents of the block length register determine the system page size and the
number of pages to be transferred in response to a single bubble read or write command. The bit configuration is as
follows:
BLOCK LENGTH REGISTER MSB
BLOCK LENGTH REGISTER LSB
17161514131211101
17161514131211101
x '-...._ _ _ _ _...yl""'"_ _ _ _ _ _ _,/
~"" _
___
J
NUMBER OF FSA
CHANNELS (NFC)
~
NUMBER OF PAGES TO BE TRANSFERRED
Figure 7. Block Length Registers
The 7220 has the capability of supporting up to eight 7110 Bubble Memory modules. Each 7110 contains two channels
that are sensed by a 7242 formatter sense amplifier (FSA). In multiple Bubble Memory configurations, the BLR
allows the user to select the page size. Since the BPK 72 consists of only one Bubble Memory module, the field
specifying the number of FSA channels in the BLR MSB must contain -OOOIB ("B" designates a binary notation).
After the FSA field is set, the page size is dependent upon the use of error detection and correction. Error correction
will be discussed in the next section describing the function of the enable register.
The BLR LSB and the first 3 bits of the BLR MSB determine the number of pages to be transferred during a single
re.ad or write command. This application restricts the user to no more than 255 contiguous pages to preyent data
transfers that could exceed the addressable memory space of the 8085.
For This Application
BLR MSB-IOH at all times.
("H" designates a hexadecimal notation)
BLR LSB-Selectable from OIH to FFH (I to 255 pages).
CAUTION: OOH in the BLR LSB will enable a 2048 page transfer resulting in a timing error.
Enable Register (ER)-The user sets the bits in the enable registCl' to enable or disable various functions within
.
the 7220. The individual bit descriptions are as follows:
INTERRUPT ENABLE (NORMAL)
INTERRUPT ENABLE (ERROR)
lJJbk~~~~~~
MFBTR
WRITE BOOTLQOP ENABLE
DMA ENABLE
ENABLE Reo
ENABLE ICO
ENABLE PARITY INTERRUPT
Figure 8. Enable Register
6·100
AP-150
One of the most important functions concerning the enable register is the option of automatic error detection and
correction. If error correction is enabled during a write operation, the 7242 formatter sense amplifier appends each
256 bit block of data with a 14 bit fire code. Both the data and the fire code are stored within the 7110 Bubble Memory
module. During a read operation, the 7242 compares the data with the fire code to check for any errors. With respect
to the FSA, errors are either correctable (the FSA is able to reconstruct the data using an error correction algorithm
before transferring the data to the 7220) or uncorrectable. Additional information about the fire code is available in
the BPK 72 user's manual.
The enable register offers three levels of error correction. All three levels utilize the same error correction algorithm
but differ in their interaction with a host processor. Table 6 defines the relevant register bits for the various levels of
error correction.
Table 6. Error Correction Levels
Error Correction
Level
Bit 6 (ICD)
Enable Register
Bit5 (RCD)
Bit 1 (Int Enable)
Level 0
0
0
0
Levell
0
I
0
Level 2
I
0
0
Level 3
I
0
I
Level 0 does not enable the error detection and correction algorithm. In this mode, the 7220 partitions one megabit
systems into 2048 pages consisting of 68 bytes per page.
Level I is the most popular level .of error correction. If an error is detected during a read operation, the 7242
automatically cycles the data through its error correction algorithm and transfers the data to the 7220. If the error was
correctable, the 7220 will continue to function normally i.e., correctable errors in Levell are transparent to the host
processor. If the error was uncorrectable, the 7220 will stop reading at the end of the page wherein the error was
encountered. In the unlikely event that the 7220 stops because of an uncorrectable error, the host processor should
try at least one more attempt to read the data. In most cases, errors result from random noise that can interfere with
the signal path between the 7110 and 7242. Since the data is usually correct within the 7110, another attempt to read
the data should yield a successful status.
Level 2 and Level 3 differ from Level I in that page-specific logging of uncorrectable errors is' possible and the
transfer of erroneous data can be prevented. Level 3 differs from Level 2 in that Level 3 also allows the logging of
correctable errors.
Neither Level 2 nor Level 3 is supported by this application because the probability of an uncorrectable error is
typically one in 1016 bits read. An error rate of this magnitude will produce few if any uncorrectable errors
throughout the useful life of a Bubble Memory System.
It is recommended that Level I error correction be utilized to improve the integrity of the data within the 7110. In
Level I, the 7220 assigns 64 bytes to a page in one megabit Bubble Memory Systems.
Aside from error correction, the enable register performs many other functions.
Enable. Parity Interrupt-If this bit is set, any parity errors between the host and the 7220 during write
operations will generate an interrupt. Since parity and the interrupt mode are not used in this application, the
enable parity interrupt bit should be reset to a logical zero.
Write Bootloop Enable-This bit must be reset to prevent accidental erasure of the boot loop within the 7110.
MFBTR-The MFBTR bit should always be reset to maximize the data transfer rate between the 7220 and 7242
during read operations.
6-101
AP-150
DMA Enable-If this bit is set, the 7220 will attempt to transfer data in the DMA mode. Since this application
utilizes a polled mode interface, this bit must be reset to a logical zero.
Interrupt Enable (Normal)-If this bit is set, an interrupt is sent to the host processor after the successful
completion of a Bubble Memory command. Since this application uses a polled mode interface, this bit should
be reset to a logical zero.
For This Application
Enable Reg-OOH. No error correction.
-20H. Levell error correction.
Address Register (AR)-The contents of the address register determine which starting address locations will be
used during a read or write command. For systems with a multiple Bubble Memory configuration, an additional
magnetic Bubble Memory (MBM) select field is used to specify which Bubble Memory(s) will be selected. The
bit configuration is as follows:
ADDRESS REGISTER MSB
ADDRESS REGISTER LSB
171615141312"11101
x,
'~'
MBM SELECT
171615141 312 11101
__________
~y~
__________
~/
STARTING ADDRESS WITHIN EACH MBM
Figure 9. Address Registers
Since the BPK 72 consists of only one 7110 Bubble Memory module, the MBM select field must contain -OOOOB
(" B" designates a binary notation).
For This Application
AR MSB-OOOOOXXX
AR LSB--XXXXXXXX, X = user selectable page address
from 0 to 2047.
STATUS REGISTER
In a polled data transfer mode, the status register provides information about error conditions, completion or
termination of commands, and the 7220's readiness to transfer data or accept new commands. The bit configuration
for the status register is as follows:
lJ=k~g~~~E
FIFO AVAILABLE
PARITY ERROR
CORRECTABLE
ERROR
UNCQRRECTABLE
ERROR
TIMING ERROR
OP FAIL
QP COMPLETE
' - - - - - - - - - - _ BUSY
Figure 10. Status Register
6·102
AP-150
Busy-When active (Logic I), the Busy bit indicates thatthe 7220 is in the process of executing a command. Bits
1 through 6 of the status register are valid only when the busy bit is not active (Logic 0).
OP Complete-When active (Logic 1), the OP Complete bit indicates the successful completion of a command.
OP Fail-When active (Logic I), the OP Fail bit indicates that the 7220 was unable to successfully complete the
current command.
Timing Error-When active (Logic I), the Timing Error bit indicates that an FSA has reported a timing error to
the 7220, or that the host system has failed to keep up with the required data rate during a read or write
operation.
Correctable Error-When active (Logic I), the Correctable Error bit indicates that an FSA has detected a
correctable error in the last block of data read from the 7110.
Uncorrectable Error-When active (Logic I), the Uncorrectable Error bit indicates that an FSA has detected
an uI1correctable error in the last block of data read from the 7110.
Parity Error-When active (Logic I), the Parity Error bit indicates that a parity error was detected between the
7220 and the host processor. Parity errors are only detected by the 7220 during write operations. Since parity is
not used in this application, ignore all parity errors.
FIFO Ready- When the 7220 is busy, an active FIFO Ready bit (Logic I) indicates that the FIFO has data for
reading or space for writing. When the 7220 is not busy, the FIFO Ready bit (Logic 0) indicates that the 40 byte
FIFO and the input and output latches are completely empty.
SUMMARY
This application note is intended to eliminate almost all of the development effort necessary to interface an 8085
microprocessor with a BPK 72. With the addition of only a few IC's and the software driver presented in Appendix A,
the designer is well on the way to incorporating the benefits of improved reliability, reduced maintenance, and
non-volatility into any 8085 microprocessor based system.
6-103
AP-150
APPENDIX A
8085 TO BPK-72 INTERFACE
SOFTWARE DRIVER LISTING
AND
FLOWCHARTS
6-104
AP-150
ASM89 :F1: BPKHDR
1515-II 8080/8085 MAr...RO ASSEMBLER, \13.0
LOC OBJ
LINE
BPK72
PAGE
1
SOURCE STATEMENT
1;
2;
3;
4,
5;
6.
7j
8;
9;
*******,.-"'-******************************-****************-**********
PROGRAI'I' 8es5 TO BPK72 SOFTWARE DRIVER Vl 13
ULI'IONT S. SM ITH JR.
INTEL CORPORATION
3065 BOWERS AVENUE
SANTA CLARA, CALIFORNIA 95051
10 ;
1·, ,.
~
13;
14 ,
15 ABSTRACT
16 ;
17 ,
THIS PROGRAM CONSISTS llF A SET OF BUBBLE MEl10RV SOFTWARE DRIVERS
18 ;
THAT SUPPORT it POLLED MODE INTERFACE BETWEEN A BPKn 1l'IBIT BUBBLE
19 '
11Et'lORV PROTOTYPE KIT., AND A STANDARD 806'5 MICROPROCESSOR. ThE
20 ;
PROGRAM UTILIZES A SET OF PUBLIC DIRECTIVES THAT CAN BE CALLED
21 }
TO PERFORM A BUBBLE MEMORV INITIALIZATION} READ, WRITE, AND OTHER
22 }
CO~1110NLY USED COMI1ANDS. IN THE lINLlkEL Y EVENT THAT THE 7110 BUBBLE
23 '
11EMORI' BOOT LOOP IS LOST., TWO ROUTINES ARE PROVIDED TO E;'if!t1lNE AN[J
24 }
REWR ITE THE BOOT LOOP CODE.
25,;
26 .'
27 )
28 ' PROGRAM ORGAfHZAilON.
29;
30 .;
FUNCTIONS:
31 ;
INTPAR
32 ;
FIFOP.5
Il ;
BYTCNT
I
34 ,
WRITE
35 ;
j6 ;
37
REA[I
ABORT
38 ;
19;
40 '
41 '
42 ;
4:; ,
44 '
RDBUBL
.lNeJjBl
BOOTlJP
RDBCH)T
WRFIFO
RDFIFt}
WPBLRS
45 ;
RflBLRS
46 ;
. 47 ;
MBt1PRiJ
WRBIJBL
I
48;
49 ;
E~TERNAL
DECLARATIONS NONE
50;
51 ;
52 $EJECT
6-105
AP-150
ISIS-II 8eSii/80S5 MACRO ASSE!1BLER, '.11 0
LOC OSJ
LINE
BPK72
PAGE
2
SOuRCE STATEfoiENT
5: :
54 ' PUBU C Sl'rlBOLS
55.,
56
57
S8
59
6@
'
'
'
,
:
61.:
62 '
6::1 .:
64 :
6S;
66 :
67.:
mORS - PE5ET 722(1 FIFO [)ATA BUFFER
ilBORT - ABORT PRESENT COt'1t1AN!), RESET BPK72
WRBU8L - WRITE BUBBLE rlEMORY [)ATA
RD8UBL - READ BllBBLE rlEt10R'r' L'ATA
lNBUBL - INITIALIZE THE BPK72
800TI.I/' - WRITE BUBBLE f1Et-lORY BOOT LOOP
P.iiBOOT - READ BUBBLE t1ErlOR~ BOOT LOOP
flRFIFO - fiRITE 1220 FIFO DATi1 BUFFER
~:rlFIFO - READ 72213 FIFO DATA BUFFER
flPBLRS - WRITE 7242 BOOT LOOP REGISTERS
R&BLRS - READ 7242 BOOT L,]OP REGI5TERS
MBMPRG - BUBBLE MEMORY PURGE COMP1AHD
68,
69 ;
713 ,**************************************************************",$**************
71 '
72
NAME BPK72
7:S .'
74 : *****:011<* .,,*************...1<*****..**..*,....*..************..**************.4<**********4<
75,
(i5 '
77 ; *****"'.¥¥***************>i-**************:t***********4<************..*************
78
79
O~:G
0800H
86 '
.1
81
82
8:.
84
85
86
,.n·*'t<*"""'***"'*"**********·*",*"****1<**..*********************..'1,*********$*4<*******
:
,
,*****.**",****"",***********"$,,**..,,,,***********.,****,,******"'****$"'''''''*************
:
;
PROGRAN mUATES
87.,
OOFE
00FF
88 ,*******",*:1<.",*******.•****************4<**********************.>*,...***:1<.1<**",******:1<.1<
89,
90 :
91 PRTAOO EQU
, A POLLED MOuE INTERFACE REQU IRES ONL',. TWO lIO
BFEH
92 PRTfi01 EQU
0FFH
PORTS DESIGNATED BY THE A0 LINE ON THE BPK72 BOARD.
93
THIS APPLICATION USES:
94
0FEH - Ae=!l FOR PRTAOO (PORT A!l= 0)
95
96
R&lWR BUBBLE MEt-lORY DATA AND REGS
97
0FFH - A!l=l FOR PRTA01 (PORT A!l= 1j
98
RD STATUS REG
99
WR BUBBLE ~1Et1OR'r' COPlNAHDS
leo
101 .:
1132 $EJECT
6-106
AP-150
ISIS-II 8089/8985 I!f!CRO ASSEllBLER, 113. 9
LOC OBJ
LINE
BPK72
PAGE
l
SOURCE STATEIIENT
103 ;***---**--***-**"'***-***"'**-*---~
104 ;
105 ; FUNCTION. INTPAR
196', INPUTS: 8-C REGS, STARTING ADDRESS OF PARAI1ETRIC REGS IN RAI1
197 . OUTPUTS: 7229 PARAMETRIC REGS
108 . CALLS'
NONE
109 , DESTROYS. A, F/FS
0899 C5
9891 £IS
9892 3E0B
9894 D3FF
989€ lE95
9898 tlA
0899 D3FE
9800 93
9B9C 10
0800 C29808
aB10 D1
0811 C1
9812 C9
119;
111, DESCRIPTION: LOAD THE 722tl PARAI1ETRIC REGS
112 ;
THE 8-C REGS CONTiHN THE ADDRESS TO THE FIRST OF FIIIE CONTIGUOUS
113 ;
I1EHORY LOCATIONS IN RAM. THE !)ATA ADDRESSED BY THE B-C REGS IS
114 ,
USED TO LOAD THE PARAMETRIC REGISTERS III THE 7229 BUBBLE MEliORY
115 ,
CONTROLLER. INTPAR COPIES THE DATA IN RAI1 TO THE PARAMETRIC REGS.
116 •
117 IIiTPAR. PUSH
B
, SAllE e-c REGS
118
PUSH
, SAllE D-E REGS
U
A,0BH , LOAD A REG WITH BLR LSB ADDRESS
119
M\lI
120
OUT
PRTA01 ; LOAD 7220 RAC WITH BLR LSB ADDRESS
E,05H , INITIALIZE LOOP COUIiTER
121
1'1\11
122 LOAD. LDAX
I LOAD A REG FROri B-C REG ADDRESS
B
121
124
OUT
IIiX
12'5
126
OCF!
127
1213
129
JNZ
POP
POP
RET
PRTA00
I
B
I
E
LOftii
£I
B
I
.
.
;
;
WRITE PARAMETRIC REG
INCREMENT B-C REGS TO THE NEXT ADDRESS IN RAM
DECREMENT LOOP COUNTER
IF NOT ZERO, JMP LOAU
RESTORE D-E REGS
RESTORE B-G REGS
REllJRN TO CALL
130,
m.
132;
133 $EJECT
6-107
AP-150
LOAD 7220 RAe -
BLOCK LENGTH
REG LSBADD
OBH
INITIALIZE LOOP
COUNTER = OSH
WRITE 7220
PARAMETRIC REG
DECREMENT LOOP
COUNTER
NO
COMMENTS: THE UTILITY REGISTER IS NOT USED. THE RAC IS
AUTOMATICALLY INCREMENTED AFTER EACH WRITE
(WR/) IS EXECUTED. THE-RAC WILL NOT INCREMENT
BEYONDOOH.
Figure 11. INTPAR
6·108
AP-150
ISI5-II 8089/8985 /1ACRO A55E11BLER.. 'n. 9
Lot OBJ
LINE
BPK72
PAGE
4
SOURCE STATEI'IENT
134 ; "'"***********-**************-*-*****--****-*******~***
125,
136 , FUNCTION: FIFORS
137; INPUTS. BPf-72 STATUS REG
138 ; OUTPUTS: ISSUE FiFO RESET COl1Htll11> TO BPH2
139 ;
A REG: BPK72 STATUS REG
149 . CftiS.
0811 05
0814 C5
98159649
9817 11FFFF
981A 3E1D
9B1C om
081E OBFF
002907
9821 0A2E98
0024 18
0825 AF
9826 B2
0827 BZ
0828 C21EB8
982B n1BB8
982E OOFF
9830 AS
/ 9831 CA3BllB
9834 1S
0835 AF
9836 E2
9837 B3
9838 C22E08
983B C1
983C 01
08:$0 DEFF
083F C9
NONE
141 ; DESTROYS. A, F/FS
142 •
143 ; DESCRIPTION. RESET 7229 FIFO DATA BlfFER
144 ;
A FIFO RESET COMI'IANi) IS ISSUE£t TO THE BPI<-72. AFTER ISSUING THE
145 ;
COI1MANf). THE BPK72 STATUS REG IS POLLED UNTIL AN OP-cot1PLETE..
146 ,
41lH. HAS BEEN REAV OR THE TIME OUT LOOP COUNTER DECREMENTS TO
147 .
ZERO. FIFORS RETlJRNS THE VALUE OF THE BPK72 SinTUS REG TO THE
148 ;
CALLING ROUTINE VIA THE 81185 S A REG. ONLY A STATUS OF 49H
149 •
INDICATES A SUCCESSFUL EXECLITION OF THE FUNCTION FIFORS.
159 ,
151
PUBLIC FIFORS , VECLARE PUBLIC FUNCTION
, SAllE IJ-E REGS
152 FIFORS: PUSH
0
. , SAVE s-c: REGS
PUSH
E
153
B,49H ; LOfI[l B REG: 4~J OP-CiJtIPLETE
I'IYI
154
0, IlFFFFH; INTIALIZE TIME OUT LOOP COUNTER
LXI
155
A,1!)H , LOfI[l A I*:G: FIFO I*:SET COMtlAND
156
MVi
OUT
PRTA9l , WRITE FIFO RESET C0I'1IflID
157
PRTAB1 , READ STATUS REG
158 BUS'fFR IN
RLC
159
• TEST BUSY BIT= 1
POlliR , IF BU5'f= 1, POLL. STATUS REG FIl( ~
JC
169
, DECI"EHENT TIME OtJT LGOP CDUNTER
161
0
Deli
, CLEAR A REG
162
A
"t*************,,***'
184 , FUNCTION. BYTCNT
185 j HlPUTS. 8-C REGS.- STARTING ADDRESS OF F'APJiI'IETRIC REGS IN RfII-l
186, OUTPUTS. H-L REGS= BYTE COUNTER
187 j CALLS
NONE
188.- DESTROYS. A, H, L, FiFS
189 .•
190.- DESCRIPTION. BYTE COUNTER
191 ;
THE B-C REGS CONTAIN THE ADDRESS TO THE FIRST OF FIVE CONTlGUQUS MEI10RY
192 ,
LOCATIONS IN RAM. THE DATA ADDRESSED 8~' THE 8-( REG5 IS 1J5E[I TO LOAD
193 THE PARAMETRIC REGS IN THE 7Zc'0 BUBBLE MEI'lORY CONTROLLER. THE ENABLE
194 ,
195 ,
196 ,
197 ,
198 ,
199 ;
200
201
202
203
..-
REG 15 READ FROM RAN TO DETERMINE IF ERROR CORREmON HAS BEEN ENABLED.
THE USE OF ERROR CORRECTION REQUIRES R 64 Bm TRANSFER/PAGE - 68 BYTE
TRANSFERiPAGE WiTHOUT ERRGR CORRECTION. THE BLGC~. LENGTH rtEG L58 IS
ALSO REAIl FROM RAM TO DETERMINE THE NUMBER OF PAGES TO BE TRAN5FER~'E[)
DURING THE Nm READ OR WRITE COMMAND. THE NIJNBER OF 8'iTES PER PAOE
~lULTiPLIE[\ 8... THE Nlh'1BER OF PAGES 15 CONPLITEIl At-[J PASSEL) TO THE GALLING
ROUTINE lilA THE 0085' 5 H-L REGS. DATA TRANSFERS ARE LIMITED TO 16, ~2ti
BYTES Vl iTH ERROR CORRECTI ON ANL' 17, ~40 B'iTES· wlTHOUT otU THE t3LRLSB
15 LlSED TO GENERATE THE BYTE COIJNTER
0840 C5
3841 D5
3842 0ft
204 B'rTCHT. PUSH
205
PUSH
L[JAX
206
0843 6F
2137
0844 133
0845 03
208
0846 0R
0847 67
0848 1640
084A ::;E60
084C A4
084D C25208
0850 1644
0852 2600
0854 1E09
0856 70
0857 iF
0858 6F
8859 1V
885ft eA6l@S
38SD 7C
085E 026208
0861 32
0862 iF
€l86? 6?
0864 C3563S
3867 01
3868 Cl
3869 C9
209
210
211
212
213
214
215
216
2:1.7
218
219
220
221 MULT.
222
8
D
B
rl011
INX
Lfl
B
IN:':
B
LDA:\
B
MOil
H, A
D.- 40H
fl.- b0H
i1
MULT
v.,44H
MYI
11111
ANA
.mz
IWI
Mill
H,(jH
E,09H
A,L
224
225
1-1111
[101/
RAR
rl0V
~E
['Cp-
227
228
229
2:;0
2Z1 t1lJLT1 :
.2:)2
SZ
E
DONE
H-H
r1iJLTl
C'
23
~1ULTO.
234 DONE
235
236
237.,
~1(I\1
JNC
AVl'
Ri1R
NOV
JI1F'
POP
POP
RET
SRIIE
, SAllE
LOAD
rlOliE
INCREI-1ENT 8-C REGS TO fI{)[·RESS THE ENNBLE REG IN RAI-l
LOf1[1 i1 PEG WlTH ENABLE REG
MOVE ENABLE REG TO H REG
, INIiItiUZE [. REG bot E'ITES/PAGE XFER.- 4011
El"ROR CORRECTION tiIGH ORDER 8~TE OF RESULT
MOllE HIljH ORDEr' F:E5ULT INTO H REG
C(,mINlJE LliOPING
RESTORE c.-E REGS
RESTORE 8-C REGS
RETIJi'N TO CALL
6·111
AP-150
ENTER
+
READ 7220
BLRLSB REG
FROM RAM
+
MULTIPLIER
BLRLSB
~
+
READ 7220
ENABLE REG
FROM RAM
MULTIPLICAND
68 DECIMAL
44H
~
~
CORRECTION
MULTIPLICAND
64,DECIMAL
40H
MULTIPLY
MULTIPLICAND
MULTIPLIER
+
BYTE COUNTER
~ RESULT
t
RETURN
)
COMMENTS: THE PARAMETRIC REGS-BLRLSB AND THE ENABLE REG
CAN NOT BE READ FROM THE n20. THEY MUST BE READ
FROM A MEMORY IMAGE IN RAM. SINCE ONLY THE BLRLSB
IS USED TO COMPUTE THE BYTE COUNTER, DATA
TRANSFERS ARE LIMITED TO 255 PAGES.
Figure 13. BYTCNT
6·112
~
AP-150
ISIS-II 888010085 I'IACRO ASSEI1BlER, VI II
LOC OBJ
LINE
23B
239
249
241
BPK72
PAGE
6
SOURCE STATEMENT
j
***********-****-****-********_********--*_***
j
FUNCTION: WRITE
INPUTS: D-E REGS, STARTING ADDRESS IF DATA IN RAM
242 ,
H-L REGS, BYTE COUNTER
243 j
BPK72 STATUS REG
244 j OUTPUTS: WRITE DATA TO BUBBLE 1'1EI'IOR'r'
24~
986A D5
986B C5
986C 01FFFF
II86F 3E13
0871D3FF
0873 liB
0074 ff
0875 Be
0876
9877
987A
087C
B1
CAR198
98ro
D27398
DBFF
07
j
j
j
CALLS:
NONE
246 , DESTRO'r'S: A, H, L.. FIFS
247,
24B j DESCRIPTION: TRANSFER DATA FROM RAM TO BUBBLE I1EMOR'r'
249 ;
THE D-E REGS CONTAIN THE STARTING ADDRESS IN RRI1 OF DATA
259 i
TO BE WRITm INTO THE BUBBLE 1'1OOR'r'. THE H-L REGS HUST
251 i
CONTAIN A BYTE COUNTER INDICATING THE NlHlER OF DATA BYTES
252 ,
TO BE TRANSFERRED. THIS FUNCTION BEGINS BY ISSUING THE WRITE
253 i
BUBBLE I1E~Y DATA COMI1AND FOLLOWED BY POLLING THE STATUS REG
254 •
TO DETERMINE IF THE T.:2li FIFO DATA BUFFER IS READY TO RECEIVE
255 ,
DATA. DATA IS TRANSFERRED UNTIL THE BYTE COUNTER OR TIME
2S6 ;
OUT LOOP COUNTER DECREHENTS TO ZERO. THE PARAt1ETRIC REGISTERS
257 ;
I'A.IST BE LOADED WITH THE DESIRED VALUES PRIOR TO CALLING THIS
258 j
FUNCTION.
259 ;
D
, SAVE D-E REGS
2611 WRITE: PUSH
B
j SAIfE B-C REGS
261
PUSH
262
LXI
B,9FFFFHi INITIALIZE TII£ OUT LOOP COUNTER
263
HVI
fl., BH
i LOAD A REG= WRITE BUBBLE 1'1EI1OR'r' DATA CO/1I1fINI)
264
OUi
PRTA01 j WRITE, WRITE BUBBLE i'IEMORY DATA Cot9\AND
;265 BUS'r'iolR. ilC;:
B
j UECREMENi TIME OUi LOOP COUNTER
A
, CLEAR MREG
266
XRI1
B
, TEST B REG= 00H
267
ORA
268
ORA
C
j TEST C REG= 00H
269
;Z
FINSHW . IF ZERO, TIME OUT ERROR, JI'1P FINSHW
P~TA01 , REIID STATUS REG
270
IN
271
RLC
, TEST BUS\' BIT=1
272
BliSVWR j IF ZERO.• CONTINUE POLLING BUSY BIT
JNC
, CONI INUED ON NEXT PMGE
273
274 $EJECT
6·113
AP·150
BPK72
ISIS-I! 8",8tl/8B85 11ACRO fiS5Ei1BLER, 1/3. 0
'-i!C 06J
il881)
13882
13883
0886
DBFF
ijF
vA960e
DBFF
0888 07
0889
088C
BSSD
e88E
BeeF
t389tl
D2A10S
0B
AF
80
81
CAA108
089:: cella8
~896 1A
13897 [GFE
0899 E
d89H 2B
0898 AF
fl8SC B4
089D B5
089£ (28008
08A1 ':1
08A2 Dl
08A1 C9
UNE
IN~:
290
DCX
XRFI
291
ORA
292
ORA
293
294
JNZ
295 FINSHW' POP
296
POP
297
298 ;
7
SOliRCE STATEMENT
275 POLLVlR' IN
276
RRC
277
Ie
278
IN
279
RLC
2<30
..TNC
281
DCX
282
>,RA
283
ORA
284
ORA
285
E
286
.IMP
287 WFIFO: WA1:
288
OUT
289
PAGE
RET
PRTA01 , READ STATUS REG
TEST FIFO READY BIT= 1
I F FIFO Rt:tID'r= L JMP VlFIFO
VlFIFO
PPTA01
READ SiAiUS REG
, TEST BUSY BIT= 1
FINSHW .' r F ZERO, ERROR, JMP FINSHW
B
; DECRENENT TIME OIJT LOOP COUNTER
FI
CLEAR FI REG
, TEST 8 REG:: 00H
B
C
TEST C REG= 00H
IF ZERO, TINE OIJT ERROR, Ji1P FINSHW
FINSHVl
POLLWR ; CUNTINUE POLLING FIFO READY BIT
[;
; LOAD A REG FP.O~l D-E REG AWRES5
PRTA0I-)
WRITE A REG TO 7220 FIFO DATA BUFFER
r,
; INCREMENT D-E REGS TO NEXT ADDRESS IN RAM
; DECREt1ENT BYTE COUNTER
H
FI
CLEAR A REG
, TEST H REG= 00H
H
i TEST L REG= e0H
L
I F BYTE COUNTER NOT ZERO, .Jt1P POLLWR
POLLWR
RESTORE B-C REGS
B
; i06 ,
307 ,
30S ;
399 ,OIJTPUTS
310 CALLS.
311 ; ~STROV5.
312
3D , DESCRIPTION. TRANSFER DATA FROM BUBBLE MEMORY TO RAM
214 I
THE D-E REGS CONT~IN THE SiARTING fI[lDRESS IN RAN USED TO STORE
315 ,
DATFI READ FROM THE BUBBLE MEMOR'i. THE H-L REGS MUST CONTAIN
316 ,
A BYTE COUNTEP INDICATING THE NUMBER OF DATA BYTES TO BE
J17 ;
TRflNSFERRE[I THIS FUNCTION BEGINS BY ISSUING THE REAU BUBBLE
318 ;
MEMORV DATA COItIAND FULLQf.lE[! BV POLLING THE STATUS REG
319 ;
TO DETERMINE IF THE 7220 FIFO DATA BUFFER CONTAINS DATA
320 ;
AIIAILMBLE FOR READING DATA IS TRflNSFERRED UlfTIL THE BYTE
321 ;
COUNTER OR TIME OUT LOUl' COlkiTER DECREMENTS iO ZERQ. THE
J22 ,
PARIlMETRIC REGS MUST BE LOADED WITH THE DESIRED IIALUES PRIOR
323 ,
TO CALLING THIS FUNCTION
I
I
00fI4 D5
eeA5 C5
9SA6 01FFFF
9SA9 3Ei2
IlSAB [lJFF
OOAI) 0B
08AE AF
324 ;
325 READ.
326
PUSH
PUSH
327
LXI
328
HYI
329
OUT
330 815l'RD: 0Cli
m
XRfI
m
:m
ORA
0Ri!
12
9884 D8FF
334
335
0S86 97
336
OOAF 80
11880 B1
ee81 CADB0S
9887 D2AOOS
IN
RLC
JNC
:m
338
:m
D
: SAVE
B
;
B.0FFFFH:
A, 12H ;
PRTA01 ,
B
•
[1-£ REGS
SAllE B-C REGS
INITIALIZE TIME OUT LOOP COLINTER
LOAU A REG= REA£> BUBBLE MEMORV DATA CUlt1ANO
WRITE, READ BUBBLE ~1EMORi' [lATA COI'1/'IANI)
DECREMENT TIME OUT LOOP COUNTER
A
• ':!.EflR A REG
B
: TEST B REG: 00H
C
: TEST GREG: 00H
FINSHR ; IF ZERO. iIME OUT ERROR, JHP FINSHR
PRTA01 , READ STATUS REG
• TEST B!JS'T' BIT= 1
BUS't'R[l J IF ZERO: CONTIIlUE POLLING BUSY BIT
J CONTINUED ON NEl<:T PAGE
$EJECT
6·116
AP·150
1515-I I 8080/8085 t1ACRO A5SH1BLER., 1/3. 0
LOC OBJ
0BBA DBFF
08BC 0F
08BD DADell8
08(:0 DBFF
08C2 07
08C3 D2DB08
08(6 08
e8C7 AF
08C8 B13
13B(:9 B1
08CA CADB0t:
08CD GBReS
08De [lBFE
tl8£12 12
0S[)3 E
13BD4 28
08[)5 AF
138Dt; 84
13B[li' 85
08D8 C2BA08
tl8DB (1
08DC Dl
08DD C9
LINE
345
146
INC
DCX
XRA
347
34B
ORA
349
ORA
350
J:
Jt1P
151
IN
352
~:FIFO
35?
5TAX
IN>:
DCi:
;-:;RA
OPA
t)P.A
.TNZ
FIN5HR POP
POP
RET
354
356
357
358
?5S
360
~t;1
~62
PRGE
9
SOURCE STRT81ENT
340 POLLR['. IN
Hi
RRC
342
JC
143
IN
344
RLC
355
BPK72
PRTR01
READ STATUS REG
TEST FIFO READY BIT= 1
RFIFO
IF FIFO READY= 1, JtiP RFIFO
PRTA01
READ STATUS REG
TEST BUSY BIT= 1
FINSHI< , IF ZERO, ERROR, Jt1P FINSHR
, DECREt'lENT mtE OllT LOOP COUNTER
B
, CLEAR A REG
A
TEST B REG= 00H
B
, TEST C REG= 130H
C
IF ZERO, TIME OUT ERROR, .IMP FINSff<
FINSHR
POLLRD
CONilNUE POLLING FIFO READY BIT
L,)AD A REG WIiH ONE BYTE FROM FIFO DATA BUFFER
PRTA013
STORE A REG IN REG D-E AD[lRES5
D
D
HKREt1ENT D-E REGS TO NEXT ADVRES5 IN RAI'1
H
, DECRENENT BYTE COUNTER
, CLEAR A REG
Ii
H
TEST H PEG= 00H
L
TEST L REG= 00H
POLLPD , IF 8','TE COUNTER NOT ZERO, Jpjp POLLR[;
f!
F.:E5TORE B-C REGS
D
RESTORE D-E REGS
RETURN TO CALL
j
36} ,
~64 '
365 '
:.66 $EJECT
6·117
AP-150
INITIALIZE
TIMEOUT
LOOP COUNTER
ISSUE READ
BUBBLE MEMORY
DATA COMMAND
DECREMENT
LOOP COUNTER
YES
READ 7220
STATUS REG
READ LOOP
READ FIFO
1 BYTEXFER
DECREMENT
LOOP COUNTER
DECREMENT
BYTE COUNTER
RETURN
, COMMENTS: MIN READ LOOP TIME ~ 21's.
MFBTR ~ 0:
MAX READ LOOP TIME ~ 201'5.'
MFBTR ~ 1:
MAX READ LOOP TIME ~ 801'5.
MINIMUM TIME OUT LOOP COUNTER ~ O.Ssec
'ONLY FOR SINGLE PAGE AND LAST PAGE OF MULTI PAGE TRANSFERS.
Figure 15. READ
6·118
AP-150
1515-I I 808018085 MACRO ASS81BLER.. V3. 0
lOC OSJ
LINE
BPK72
PAGE
10
SOURCE STATEMENT
"'********-******-********___***__*****_*_*
367 . ***. . . . .
36B ;
369 ; FUNcTI ON ABORT
370 . INPUTS, BPK72 STATUS REG
:m , OUTPUTS: ISSUE ABORT COIt1AND TO BPK1'2
n REG: BPK72 STATUS REG
:m ; CALLS: NONE
374 : DESTROYS' A, F/FS
m,
375,
376 • DESCPIPTION' ABORT PRESENT COMMilliD, RESET BPK72
AN ABORT COItlAND IS ISSUED TO THE BPK72. I AFTER ISSUING THE
COtflAND, THE BPK72 5TflTUS ~EG IS POLLED OOIl AN OP-COlf'LETE.
40H. HAS BEEN READ OF. THE TIME OUT lOOP COOOER DECREMENTS
TO ZERO, THE ABORT FUNCTION RETURNS THE IIALUE OF THE BPI<-72
STATUS REG'.TO THE CALLING ROUTINE VIA THE 80S5'S A REG. ONLY A
STATUS OF 4011 INDICATES N SUCCESSFUL EXECUTION OF THE ABORT
FUNCTION
3?7 ,
:;7S i
379 .
380 ;
381 ,
382 ,
383 •
384.
3'85
08DE 05
880F C5
08E0 llFFFF
088 0649'
88ES JE1!:!
08E70lFF
08E9 DBFF
386
~87
388
:::89
390
391
392 BUS'y'fl,
OOEB 0('
~9~
08EC 1i11F908
08EF 18
08F0 AF
98F1 B2
08F2 B2
0SF3 C2E908
08F6C0609
88F9 fiBFF
0BFB AS
08FC Cn0609
08FF 18
0900 AF
0901 B2
:::94
:::9'5
9902 B:!
090;
0906
0907
0908
990A
C2F90B
Cl
01
DBFF
C9
ABO~T
~96
:;97
398
399
400
401 POllA
402
463'
404
405
406
407
40S
409 RETA
4i~
411
412
413 '
414 '
415.
416 $EJECT
PUBLIC ABORT ;
o
.
FUSH
PuSH
B
,
LXI
D,. eFFFFI1,
11\11
B. 4011 ;
A, 1911 ;
!'1VI
OUT
PRTo101 ,
IN
PRTA01 ,
RlC
"
POllA ;
JC
jj
OCt:
·
H
:~RA
·
vPA
,
o
ORA
E
;
!NZ
BUSYA ;
,
JMP
RETA
P~TA0i •
IN
,Ril
B
·
Y.t.iR
JZ
DCX
D
:
XRA
•
ORA
•
,
OPA
E
JNZ
POllR ,
PDF
B
•
,
D
P'Jf
IN
PPTA01 ,
PET
•
DECLARE PUBLIC FUNCTIOh
SAllE v-E REGS
SAllE B-C REGS
INITIALIZE TIME OUT lOOP COUNTER
lOAD B REG= 4011, OP-coMPLETE
lOA!} A REG= ilBORT ,:OMI1AND
WPITE ~T COt'lllAND
REND STATUS REG
TEST BUSY BIT= 1
IF BUSY= 1, POll STATUS .REG FOR 40H
DECREMENT TIME OUT lOOP COUNTER
CLEAR A REG
TEST 0 REG= e0i1
iEST E REG= 0011
IF NOT ZERQ, CONTINUE POLLING ABORT CDI'1I1fOO
TIME OUT ERROR, RETURN
IFAF
99E1l B4
99E1 B5
Il9E2 CA23IlA
99E5 C3D8Il9
;
;
;
;
652
09C6 [)lFF
Il9DB CAE8Il9
C,28H
fI, IlFFH
PRTAIII.!
C
651
JC
659
66Il
XRA
661
ORA
JNZ
662
~
66l
JI1P
664 POl.U1R: IN
665
XRA
666
JZ
667
OCX
668
XRA
669
ORA
67Il
ORA
671
JZ
672
JI1P
673
674 $EJECT
PAlE
18
SOURCE STATEMENT
Il9BE C2BB89
99C121FFFF
Il9C4 3E16'
891)2 C2C81l9
891)5 Cl23IlA
99[)8 DBFF
Il9I)A AS
BPK72
LOll) C REG=. 28H, BYTE COOOER= 48 DECIIft..
LOll) A REG= FFH
WRITE A REG INTO FIFO DATA BUFFER
DECREl'lENT BYTE COUNTER
IF BYTE COONTER= ZERO. CONTINJE
INITIALIZE TII'IE OUT LOOP COUNTER
LOA[) A REG= WRITE BOOT LOOP REG catIfN)
WRITE. WRITE BOOT LOOP REG catIfH)
REAl> STATUS REG
TEST BUSY BIT= 1
IF BUSY= L pw. STATUS REG FOR 4IlH
DECREl'IENT TlI'IE OUT LOOP COUNTER
CLEAR A REG
TEST H REG= IlIlH
TESTL REG: IlIlH
IF NOT ZERO. CONTINUE POLLING IoIRBLRS wtIfN)
TitlE OUT ERROR, RET~N
READ STATUS REG
TEST STATUS= 4IlH
IF ZERO, CONTINlE. OP-cotfLETE
DECREI1ENT TlI£ OUT LOOP COUNTER
CLEAR A REG
TEST H REG: IlIlH
TEST L REG= IlIlH
IF ZERO, TlI'lE OUT, ERROR
CONTINUE POLLING IIRBLRS catIfN)
CONTINUE!) ON NEXT PAlE
6·131
AP·150
BPK72
ISIS-I I 888918085 IKRO RSSE11III.ER. YJ."
LOC OBJ
B9E8 CI>1308
89EB AS
89EC C2239A
89EF IlE28
89F11A
99F2 13
89F3 DlFE
09FS 00
&6 C2F199
99F9 AF
89FA
89FC
89FF
9A81
IlA83
8A85
IlA07
8A08
8A8B
DlFE
21FFFF
iIEFD
3Ei?
D3FF
DBFF
87
DA158A
2B
8A8C AF
i!A00 B4
8A8E B5
8A8F C205i!A
0012 C32300
8A15 DBFF
8A17 Ai
8A18 AS
0019 CA2300
8A1C 2B
0010 AF
OO1E B4
001F B5
8A28 C2150A
i!A23 E1
8A24 D1
0025 C1
0026' cooees
8A29 DBFF
8A2B C9
LINE
675 CONT:
676
m
PAGE
19
SOURCE STATEI1ENT
CALL
XRA
JHZ
678
"VI
679 BLCOOE: LDAX
68!l
INX
681
OUT
682
OCR
683
JNZ
684
XRA
68S
OUT
6S6
LXI
687
1'1\11
MVI
688
OUT .
689
698 BUSYBL: IN
RLC
691
692
JC
693
OCX
694
XRA
695
ORA
696
ORA
697
JHZ
698
JMP
699 POLLBL: IN
ANA
700
781
XRA
702
JZ
783
OCX
784
XRA
785
ORA
786
ORA
787
JNZ
708 RETBT. POP
789
POP
718
POP
711
CALL
712
IN
713
RET
714 ;
715 ;
716,
717 $EJECT
FIFORS ;
;
B
RETBT ;
C,28H ;
;
D
;
D
PRTAe8 ;
;
C
BLCODE ;
;
A
PRTA0Il ;
II, 9FFFFH;
C,8FDH ;
A, 17M ;
PRTA81 ;
PRTA81 ;
POLLBI..
H
A
H
L
BUSYBL
RETBT
PRTA81
C
~
RETBT
H
A
H
L
POLLBL
H
D
B
INTPAR
PRTA01
CALL FIFO RESET
TEST STATUS= 40H
IF NOT ZERO.. ERROR, JI'P RETBt
LOAD C REG: 2SH. BYTE COUNTER= 49 DECIIft.
LOAD A REG FROM D REG fI>DRESS
INCREI'IENT D REG TO TI£ I£XT fIlDRESS
WRITE BOOT LOCf CODE INTO FIFO DATA BUFFER
DECREMENT BYTE CruNTER
IF NOT ZERO, JIIP BLCOOE
CLEAR A REG
WRITE 41ST BYTE OF ZEIIO INTO FIFO DATA BlfFER
LOAD TII£ OUT LOOP COUNTER
I'IASK, I1ASK OUT PARITY BIT
LOAD A REG: WRITE BOOT LOOP ~
WRITE. WRITE BOOT LOOP CM1fINI)
READ STATUS ~G
; TEST BUSY BIT= 1
; IF!JUSY=1, POLL STATUS REG FOR OP-ct11PlETE
; DECREMENT TIME OOT LOCf COUNTER
; CLEAR A REG
; TEST H REG: 88H
; TEST L REG: eeH
; IF NOT ZERO, ~INUE POLLING THE IiRBL cm1fH)
; TII'E OUT ERROR, RETURN
; READ STflTUS REG
; RESET BIT L PARITY BIT
; TEST STATUS= 48H OR 42H, OP-coMPLETE
; IF ZERO, CONTINUE, OP-coMPLEtE
; DECREMENT TII'E OOT LOOP COtmER
; CLEAR A REG
j TEST H REG: 88H
j TEST L REG: 88H
; COOlNUE POLLING WRITE BOOT LOOP COI1MAND
j RESTCRE H-l REGS
j RESTORE D-E REGS
; RESTCRES-C REGS
; CALL INTPAR. LOAD THE PARMTRIC REGS
; ·READ STATUS REG
6·132
AP·150
A
Figure 20. BOOTUP
6·133
AP-150
DECREMENT
LOOP COUNTER
DECREMENT
LOOP COUNTER
READ 7220
STATUS REG
COMMENT" MINIMUM TIME OUT LOOP COUNTER = lOOMS
Figure 20 (Can't). BOOTUP
6·134
AP-150
ISIS-II 8880/8085 I1ACRO A55E11BLER, 1118
LOC OBJ
LINE
BPK72
PAGE
28
SOURCE STAlEI1ENT
718 ; ***"***-******'"***********. ,,,,,'***.... u****""*,,,*******,,*, ,t "U, t I , I "
719 ;
728 i FlKTION: RDBOOT
,
721; INPUTS: D-E RE~ STARTING ADDRESS IN RAIl
722 ;
BPK72 STATUS REG
721 ;
READ BUBBLE i'IEI'KJRY BOOT LOOP
724; OUTPUTS: COPY BUBBLE MEI'IORY BOOT LOOP TO RAI1
725 ;
A REG: BPK72 STATUS REG
726; CALLS:
FIFORS
727 ; DESTROYS: A, FIFS
728 ;
729; DESCRIPTION: READ BUB8I.E I100RY BOOT l.OEf
738 ;
THE D-E REGS CONTAIN TI£ STARTING ADDRESS TO THE FIRST OF 48
i'31 ;
CONTIGUruS I'EI1ORY LOCATIONS IN RAI1 THAT WILL BE LOADED WITH
732 ;
A COPY OF THE BOOT LOOP CODE. RDBOOT RETURNS THE VALlE OF TIE
713 ;
BPK72 STATUS REG TO TI£ CALLING ROUTINE lilA THE 8885'5 A REG.
n4 i
ONLY A STATUS OF 48H INHCATES A SUCCESSFUl.. EXECUTION OF RDBOOT.
735 ;
PUBLIC RDBOOT ;
B
;
D
;
H
;
B, 48H ;
741
!WI
C, 28H ;
742
CfLL
FIFORS ;
743
XRA
B
;
RETRDB i
744
JNZ
745
INR
B
;
It 8FFFFH;
74~
LXI
747
I1IJI
fI, 1BH
;
748
OOT
PRTA81 ;
749 BUSYRB: IN
PRTA81 ;
758
RLC
;
751
JC
BlLPRD ;
;
752
DCX
H
;
753
XRA
A
;
754
ORA
H
755
ORA
L
;
756
JNZ
BU5YR8 ;
757
JItI
RETRDB ;
;
758
759 $EJECT
736
8A2C C5
IIfI2D D5
IlA2E E5
ilft2F 8648
W1 Il£28
IlfI3l CJ)1388
8fI36 AS
IlfB7 C26A8fI
8A3A 84
IIA3B 21FFFF
8fI3E 3E1B
8fI48 D3FF
8fI42 DBFF
8A44 87
8fl45 DfI52efI
8fI48 2B
8fl49 AF
8fI4fI B4
8fI4B B5
.8fI4C C2428A
8fI4F C36A8fI
737 ROBOOT: PUSH
738
PUSH
739
PUSH
748
MYI
DECLARE PUBLIC FUNCTION
SAVE B-C REGS
SAVE D-E REGS
SAVE H-L REGS
LOR) B REG: 41l11. IP-COI1PLETE
LOflI C REG= 28H. BYTE COIJfiER= 48' DECIIft.
CALL FIFO RESET
TEST STATU5= 4IlII. OP-COI1Pl.ETE
IF NOT ZERO, ERROR. JItI RETRDB
B REG= 41H. OP-roft.ETE, FIFO FULL
INITIALIZE TII1E our LOOP COIJfiER
LOAD A REG= READ BOOT LOOP CMfAII)
WRITE.. READ BOOT LOOP COItfANI)
READ STATUS REG
TEST BUSY BIT= 1
IF BUSY: L p(ll STATUS REG FOR 4tH
DECREIENT TII1E OUT LOOP COlIfTER
CLEAR A REG
TEST I H REG= 8flH
TEST L ~ 80H
IF NOT ZERO, CONTINUE p(llING RDBL CMRI)
TII1E OOT ~ RET\Rj'
CONTINUED ON NEXT PAGE
6-135
....
AP~150
BPK72
ISIS-II 898818885 IIACRO AS5EIELER, Ylil
LOC OBJ
IIFI52 DBFF
8A54 AS
IlA5S CfI62IIA
8fI58 2B
9AS9 AF
8A5fI B4
8A5B B5
IIfI5C CfI6IIIIA
I!A5F C352IIA
8A62 D8FE
8fI64 12
8fI65 jJ
8A66 lID.
8A67 C26211A
IlA6R DBFF
8fI6C E1
8A6I) D1
IIA6E C1
IlA6F C9
ME' 21
LINE
768 BTLPRD: IN
761
XRfI
762
12
763
OCX
764
765
766
7(;7
768
769 FIFORD:
m
771
m
m
XRfI
0Rf!
0Rf!
12
JI'IP
IN
STAX
INX
OCR
JNZ
774 RETRDB: IN
77S
POP
776
POP
m
POP
778
RET
779 i
READ STATUS REG
TEST STATUS= 4tH. ~ FIFO FULL
i IF ZERO, JI'IP TO FIFO READ
i DECREMENT TII£ ouT L()(f (;(ltfTER'
A
i CLEAR A REG
H
i TEST HREG= IIIIH
; TEST L REG= IIIIH
L
RETRDB i IF ZERO. TItE em, ERR(R
BTLPRD i COOIIlIE POLLING RDBL COItIAII)
PRTAIIII i READ FIFO DATA BIfFER
D
i WRITE RAM AT ADDRESS IN D REG
D
j INCREI'ENT DREG TO NEXT RAP! ADDRESS
i DECREI£NT BYTE COOOER
C
FIFORf) i IF NOT ZERO, JI'IP FIFO READ
PRTfIII1 i READ STATUS REG
; REST~ I+-L REGS
H
D
i RESTORE D-E REGS
; REST~ B-C REGS
B
i RETURN TO CALL
PRTfIII1
i
B
FIFORD
H
i
7811 $EJECT
6·136
AP-150
INITIALIZE
BYTE COUNTER
40 DECIMAL
28H
INITIALIZE
TIMEOUT
LOOP COUNTER
ISSUE READ
BOOT LOOP
COMMAND
RE;AD7220
STATUS REG
READ 7220
STATUS REG
READ 7220
STATUS REG
DECREMENT
BYTE COUNTER
DECREMENT
LOOP COUNTER
YES.
YES
COMMENT: MINIMUM TIME OUT LOOP COUNTER
~
200MS
Figure 21. RDBOOT
6·137
YES
DECREMENT
LOOP COUNTER
AP-150
ISIS-II 808018085 MACRO ASSEMBLER, 113.0
LOC OBJ
LINE
BPK72
,PAGE
22
SOURCE STATEMENT
********************************************************************-*
781 ;
782;
,
793 ; FUNCTION: WRFIFO
784, INPUTS, D-E REGS, STARTING ADDRESS OF DATA IN RA/'I
785 "
BPK72 STATUS REG
786 i OUTPUTS: WRITE 40 BYTES IN THE BPK72 FIFO DATA BUFFER
797 ,;
A REG= BPK72 STATUS REG
788 ; CALLS:
FIFORS
789; DESTROYS: A, FIFS
790 ;
791 ,; DESCRIPTION: WRITE 7220 FIFO DATA BUFFER
792 ;
THE [l-E REGS PROVIDE THE ADDRESS TO THE FIRST OF 40 CONTIGIJOUS
mi
BYTES IN RAM THAT CONTAIN DATA TO BE LOADED INTO THE BPK72 FIFO
794 ;
DATA BUFFER. WRFIFO WILL TRANSFER THE DATA FROM RAM TO THE FIFO
795 ;
DATA BUFFER, WRFIFO RETURNS THE IIALUE OF THE BPK72 STATUS REG
796 ;
TO THE CALLING ROUTINE lilA THE 8085 / S A REG, ONL'f A STATUS OF
797 ;
41H OR 43H INDICATES A SUCCESSFUL EXECLITION OF WRFIFO,
798 ;
!:lA70 C5
!:lA71 D5
!:lA72 0640
!:lA740E28
0A76 CD1308
0079 AS
!:lA7A C2850A
007D 1A
!:lA7E D3FE
!:lA80 13
!:lA81 00
0A82 C27D0A
!:lASS D1
!:lA86 C1
0A87 DBFF
!:lA89 C9
799
800 WRFIFO:
801
802
803
804
805
806
807 INFIFO,
808
809
818
811
812 RETWF:
813
814
815
816 ;
817;
818 ;
819 $EJECT
PUBLIC WRFIFO ; DECLARE PUBL Ie FUNCTION
; SAVE B-G REGS
PUSH
B
,; SAVE D-E REGS
PUSH
D
MY!
B, 40H ; LOAD B REG: 40H, OP-COMPLETE
MYI
C,.28H ; LOAD C REG: 28H, INITIALIZE LOOP COUNTER
CALL
FIFORS , CALL FIFORS, WRITE FIFO RESET COItIIlND
; TEST FOR STATUS REG: 4011, OP-COMPLETE
XRA
B
JNZ
REM ; IF NOT ZERO, FIFO ERROR, Ji'P REM
LDAX
D
, LOAD A REG FROM D-E REG ADDRESS
OUT
PRTA00 ; WRITE A REG TO 7220 FIFO DATA BUFFER
; INCREMENT D-E REGS TO NEXT ADDRESS IN RAM
INX
D
DCR
C
; DECREMENT LOOP COUNTER
JNZ
INFIFO ; IF LOOP COIJITER NOT ZERO, JMP INFIFO
POP
D
; RESTORE IH REGS
POP
B
; RESTORE S-G REGS
IN
PRTA01 ; READ STATUS REG
; RETURN TO CALL
RET
6-138
AP-150
INITIALIZE
LOOP COUNTER ~
40 DECIMAL, 28H
WRITE FIFO
1 BYTEXFER
DECREMENT
LOOP COUNTER
Figure 22. WRFIFO
6·139
ISIS-II 888818985 I'KRO RSSEIIBI.ER, Vl 8
LOC O8J
LItE
828 ;
BPK72
PAGE
23
SOI.RCE STATEIIENT
*********_*****_******...........It**...................I ••••• It
821 ;
822 ; FUNCTION: RDFIFO
823 j INPUTS: D-E REGS STARTING fI>DRESS IN RftI
824 ;
.BPK72 STATUS REG
825 ;
REAl) 40 BYTES OF DATA FRa'I BPK72 FIFO DATA BUFFER
826 ; OOTPUTS: TRANSFER FIFO DATA BUFFER TO RftI
827 ;
A REG: BPK72 STATUS REG
828; CALLS:
NONE
829 j DESTROYS. R, FIFS
838 ;
, 831; DESCRIPTION: REAl) 7228 FIFO DATA BUFFER
832 ;
THE D-E REGS CONTAIN TI£ fI>DRESS TO TI£ FIRST OF 40 CONTIGUOUS
833 ;
BYTES IN RAI1 TlftT WILL BE LOADED WITH THE CONTENTS OF THE BPK72
834 i
FIFO DATA BlFFER. RDFIFO WILL TRANSFER THE DATA FROI'I THE FIFO DATA
835 j
BlfFER TO RfII'I. RDFIFO RETURNS THE YALUE OF TI£ BPK72 STATUS REG
836 ;
TO THE CALLING ROUTINE VIA 11£ 8885'5 A REG. ON...Y A STATUS OF 48H
837 ;
OR 42H INDICATES A SUCCESSFUl.. EXECUTION OF RDFIFO.
838 ;
839
PlB.IC RDFIFO ; DECLARE PUBLIC FUNCTION
IlASA CS
8A88 D5
8fISC 1lE28
IIII8E DBFE
8fI99 12
8A91B
9A92
0A93
IlfI96
0A97
0fI98
848 RDFIFO: PUSH
B
841
[)
PUSH
842
HVI
843 OUTFIF: IN
844
STfIX
845
IN>:
81)
S46
OCR
C28E1lA
Di
C1
DBFF
847
JNZ
POP
POP
iJA9A C9
848
849
858
851
IN
RET
C,28/l
PRTA80
[)
I)
C
OUTFIF
[)
B
PRTA81
; SAVE B-C REGS
i SAVE D-E REGS
; LOAD C REG= 2SH. INITIALIZE LO(f CMTER
; LOAD A REG WITH 01£ BYTE FROI1 FIFO DATA BlfFER
; LOAD A REG' IN I)-E REG AOORESS
; INCREI1ENT H REGS TO NEXT AOORE5S
; DECfIDENT LOOP COUNTER
; IF LOOP C.ouNTER NOT ZERO, Jl'IP OUTFIF
; RESTORE I)-E REGS
j RESTORE B-C REGS
; REAl) STATUS REG
; REMN TO CALL
852 ;
853 i
854 $EJECT
6·140
AP-150
INITIALIZE
LOOP COUNTER ~
40 DECIMAL, 28H
READ FIFO
1 BYTE XFER
DECREMENT
LOOP COUNTER
NO
READ 7220
STATUS REG.
Figure 23. RDFIFO
6·141
AP-150
ISIS-II 89S01B0S5 I'IRCRO ASSEl'lBLER, Vl 9
LOC OOJ
LINE
BPK72
PAGE
24
SOURCE STATEMENT
*************_*******************************__*****'t'******
IlA9B C5
0A9C
0A9D
0A9F
0AfI1
0AA4
0flA7
0AA8
IlAA9
0AfIC
E5
0641
0EFD
21FFFF
CD700A
Ai
AS
C2CE9A
05
3E16
0AAF D3FF
9AB1 OOFF
8AB397
8AB4 DAC10A
0AB72B
0AB8 AF
0AB9 B4
0ABA B5
0ABB C2B10A
0ABE GCE0A
!lAC1 OOFF
!lAC3 A8
0AC4 ~0A
0AC72B
!lACS AF
0AC9 B4
0ACA B5
0ACB C2C10A
0ACE E1
0ACF C1
9AA()
eroe DBFF
0AD2 C9
BS5 ;
856 ;
857 ; FUNCTION: WRBLRS
S58; INPUTS: D-E REGS, STARTING ADDRESS OF DATA IN RAM
859 ;
BPK72 STATUS REG
B60 ,; OUTPUTS: WRITE BUBBLE MEMORY BOOT LOOP REGISTERS COI'II'IAND
861 ;
A REG= BPK72 STATUS REG
862 ; CALLS:
WRFIFO
863 " DESTROYS: A, FIFS
864 ;
865 ; DESCRIPTION: WRITE 7242 BOOT LOOP REGISTERS
866;
THE D-E REGS PROVIDE THE ADDRESS TO THE FIRST OF 40 CMIGUOUS
867 ;
MEI'1ORY LOCATIONS IN RAM THAT CONTAIN DATA TO BE LOADED INTO
86B ;
THE 7242, FORtlATTER SENSE AMPLIFIER, BOOT LOOP REGIstERS,
869 ;
WRBLRS WILL TRANSFER THE DATA FROM RfI'I TO THE BOOT LOOP
870 ;
REGISTERS, WRBLRS RETURNS THE VALUE OF THE BPK72 STATUS REG
871 ;
TO THE CALLING ROUTINE VIA THE 8085'S A REG. ONLY A STATUS OF
872 ;
40H INDICATES A SUCCESSFUL EXECUTION OF WRBLRS,
873 ;
874
PlRIC WRBLRS ; DECLARE PlRIC FUNCTION
; SAVE B-C REGS
875 WRBLRS: PUSH
B
; SAVE H-L REGS
876
PUSH
H
B,41H ; LOAD B REG= 41/i, OP-coMPLETE, FIFO FULL
877
1'1\11
C,0FDH ; /'!ASK, MASK OUT PARITY BIT
878
1'1\11
879
H,0FFFFH; INITIALIZE TIME OUT LOCF COUNTER
LXI
WRFIFO ; CALL WRITE FIFO DATA BUFFER
B80
CALL
; RESET BIT 1, PARITY BIT
C
881
ANA
; TEST STATUS= 41H OR 43H, OP-coI!PLETE, FIFO FULL
B82
XRA
B
RETWBL ; IF NOT ZERO, ERROR, JMP RETWBL
883
JNZ
; B REG: 40H, OP-COI'IPLETE
B84
OCR
B
A,16H ; LOAD A REG: WRITE BOOT LOOP REG COI1I1ANI)
8B5
1'1\11
OUT
8S6
PRTA01 ; WRITE, WRITE BOOT LOOP REG COIt1fH)
BS7 BSYWBL: IN
PRTA01 ; READ STATUS REG
88B
RLC
; TEST BUSY BIT= 1
889
JC
POUR ; IF BUSY= 1, POLL STATIJS REG FOR 40H
B90
DO:
; DECREMENT TIME OUT LOOP COIJNTER
H
891
XRA
; CLEAR A REG
A
892
; TEST H REG: OOH
ORA
H
; TEST L REG= OOH
893
ORA
L
894
JMZ
BSYWBL ; IF NOT ZERO, CMINUE POLLING WRBLR COIt1AND
RETWBL ; TIME OUT ERROR, RETURN
B95
JMP
B96 POLWBL: IN
PRTA01 ; READ STATUS REG
897
,; TEST STATUS REG: 40H, OP-coMPLETE
XRA
B
B98
JZ
RETWBL i IF ZERO, OP-cot1PLETE, JMP RffiIBl.
899
OCX
H
; DECREMENT TIME OUT LOOP COlINTER
A
; CLEAR A REG
900
XRA
H
i TEST H REG: OOH
991
ORA
; TEST L REG= OOH
902
ORA
L
JNZ
903
POLWBL ; IF NOT ZERO, CONTINUE POLLING WRBI..R COItIANI)
i RESTORE H-L REGS
904 RETWBL: POP
H
; RESTORE B-C REGS
905
POP
B
906
IN
PRTA01 ; READ STATUS REG
907
; RETURN TO CALL
RET
90S $EJECT
6·142
AP-150
INITIALIZE
TIMEOUT
LOOP COUNTER
ISSUE WRITE
BOOT LOOP REGS
COMMAND
READ 7220
STATUS REG.
READ 7220
STATUS REG
DECREMENT
LOOP COUNTER
DECREMENT
LOOP COUNTER
YES
READ 7220
STATUS REG.
(
COMMENT: MIN TIME OUT LOOP COUNTER
~
1 MS
Figure 24. WRBLRS
6·143
RETURN)
AP-150
ISI5-I I 8880I88S5 IfICRO ASSEJt3I..ER, VI 8
LOC II!J
LINE
BPK72
8003 C5
8AD4 E5
8AD5 86C1
8AD7 21FFFF
8ftOO 3Et5
8AOC !)3FF
8AllE llBFF
IlAE8 87
8AE1 l>AEE9A
1!AE4 2B
9AE5 AF
8AE684
I!AE7 85
8AE8 C2I>E9A
I!AEB C3810B
I!AEE DBFF
eAF8 AS
8AF1 CAFE8A
0AF42B
8AF5 AF
8AF6 B4
8AF7 B5
8AF8 CA818B
8AFB C3EE1lA
IlffE COOfI8A
8B81 E1
8B82 C1
8883 OOFF
IlB85 C9
25
SOURCE STATEI£NT
909 ;** .........................
918 j
911 j
912;
913 ;
914 ;
915;
916 ;
917 ;
918 j
PAGE
**......................_ .............****
FlIOCTION: RDBlRS
INPUTS: I>-E REGS, STARTING AOORESS IN RAM
BPK72 STATUS REG
READ I>ATA FRIJI 7242 BOOT LO(f REGISTERS
OUTPUTS: TRANSFER BOOT LOCf REGISTER DATA TO RAIl
A REG= BPK72 STATUS REG
CALLS:
RDFIFO
l>ESTROYS: It FIFS
919 j
928; DESCRIPTION: REA[) 7242 BOOT LO(f REGISTERS
921 j
TIE I>-E REGS CONTAIN TIE ADDRESS TO TJE FIRST OF 48 CONTIGUOUS
922 ;
I1EI'IORY LOCATIONS IN RAM TO BE LOADEI) WITH TIE CONTENTS OF TI£
923 ;
7242. FORI'IRTI'ER SENSE flI'tPLIFIER, BOOT LOCf REGISTERS. RDBlRS
924 ;
WILL COPY TI£ CONTENTS OF TIE BOOT LOCf REGISTERS TO RAI'I.
925 j
RDIlI..RS ~ TI£ VALlE OF TIE BPK72 STATUS REG TO TIE
926" j
CALLING ROUTINE VIA TIE 8085'S A REG. ONLY A STATUS OF 49H
927 j
IN!) ICATES A SUCCESSFUL EXECUT ION OF RDBlRS.
928 ;
929
PlKIC ROOLRS ; I>ECLARE PlKIC FlIlCTION
930 RI>BLRS: PUSH
B
; SAVE B-C REGS
H
j SAVE H-L REGS
931
PUSH
B,8C1H ; LOAD 8 REG= CiH, OP-caRETE, FIFO FULL )22 BYTES (BUSY BIT=!)
932
IIYI
H, 8FFFFH; INTIALIZE TIlE OUT LO(f COlJjTER
933
LXI
934
IIYI
It 1SH j LOAD A REG= READ BOOT LOCf REGS COItIfM)
935
OUT
PRTA81 ; WRITE TIE READ BOOT LOOP REGS COI1I'fANI)
936 BSYRBl.: IN
PRTA81 j READ STATUS REG
m
RLC
; TEST BUSY BIT= 1
938
JC
POLR8l ; IF BUSY= L PIl..L STATUS REG FOR C1H
H
; !)ECRE/'lENT TIlE OUT LOCf COlJjTER
939
DCX
948
XRA
A
j CLEAR A REG
941
ORA
H
; TEST H REG= OOH
942
ORA
L
; TEST L REG= 8!IH
943
JNZ
BSYRBL ; IF NOT ZERO, CONTINUE POLLING REAl) BOOT LOOP REG COIfIANI)
944
JI'IP
RETRBL ; TIME OUT ERROR. RETURN
945 POLRBL: IN
PRTAil1 .; READ STATUS REG
946
XRA
B
; TEST STATUS= C1H. OP-COI1PLETE, FIFO FULL
947
JZ
CALLRI> ; IF ZERO, OP-CO!fl.ETE, JI'IP CALLRD
948
DCX
H
; I>ECREl'IENT mE OUT LOCf COlJjT£R
A
; QEAR A REG
949
XRA
958
ORA
H
; TEST H REG= 8!IH
L
; TEST L REG= OOH
951
ORA
952
JZ
RETRBL ; IF ZERO, ERROR. JIf> RETRBL
PIl..RBL ; CONTINUE POLLING READ BOOT LOOP REG COI1I1ANI)
953
JI'IP
Rl)FIFO ; CALL REA[) FIFO
954 CALLRI>: CALL
H
; RESTORE H-L REGS
955 RETRBL: POP
B
; RESTORE B-C REGS
956
POP
"957
IN
PRTAiI1 ; READ STATUS REG
958
RET
; RETURN TO CALL
959 $EJECT
6·144
AP-150
INITIALIZE
TIME OUT
LOOP COUNTER
ISSUE READ
BOOT LOOP REGS
COMMAND
READ 7220
STATUS REG
READ 7220
STATUS REG.
NO
DECREMENT
LOOP COUNTER
DECREMENT
LOOP COUNTER
NO
CALL
RDFIFO
YES
YES
COMMENT: MIN TIME OUT LOOP COUNTER
READ 7220 '
STATUS REG.
= lMS
Figure 25. RDBLRS
6-145
AP·150
ISIS- II 8000/8005 MACRO
LOC OBJ
AS~
LINE
VI 0
BPK72
PAGE
26
SOURCE STAIDlENT
960 ; ****.---********-~************~*******
961;
,
962 ; FUNCTION: i'lBHPRG
963; INPUTS: BPK72 STATUS REG
964 ; OUTPUTS: ISSUE I1BM PURGE COft1ANI)
965 ;
A REG: BPK72 STATUS REG
966 ; CALLS:
NONE
967 ; DESTROI'S: fL FIFS
968 ;
969; DESCRIPTION: I'IIlI1 PURGE COItIfINI)
970 ;
AN I'IIlI1 PURGE COItIAN) IS ISSUED TO TI£ BPK72. AFTER ISSUING TI£
971 i
COtIMANI), THE BPK72 STATUS REG IS P(llE[) UNTIL AN OP-ct»IPlETE
972 i
973 ;
974 ;
975 ;
IIB06 D5
8887 C5
!lB!lS !l64!l
0B0A llFFFF
I!B!lD JEiE
8B8F DSFF
!lB11 OOFF
1lB13 07
9814 DA211lB
1lB17 1B
1lB18 AF
IlB19 B2
081A B3
981B C2111lB
IlB1E C32E08
IlB21 OOFF
0823 AS
0824 CA2E1lB
!lB27 18
!lB28 AF
8B29 B2
1IB2A 83
0B2B C2211lB
!lB2E C1
!lB2F D1
1lB38 OOFF
11832 C9
40H, HAS BEEN READ OR TI£ TII1E OUT LOOP COONTER DECREI'ENTS
TO ZERO. t91PRG RETIMiS THE Yfl.UE (F THE BPK72 STATUS REG TO
THE CALLING ROUTINE VIA THE 8005'S A REG. ONlY A STATUS OF 400
INDICATES A SUCCESSFUL EXECUTION OF \'B'IPRG.
976 ;
977
PUBLIC /91PRG ;
D
;
978 t91PRG: PUSH
B
;
979
PUSH
B, 40H ;
98!l
HVI
D,8FFFFH;
981
LXI
fL 1EH ;
982
I'IVI
PRTA91 ;
983
OUT
984 BSYi'lBM: IN
PRTA01 .'
;
985
RLC
POLI1BI1 ;
986
JC
D
;
987
OCX
A
;
988
XRA
D
;
989
ORA
E
;
990
ORA
BSYi'IBI1 ;
991
JNZ
RE1l'IIlI'I i
992
JI1P
993 POLMBI'f: IN
PRTA01 ;
B
;
994
XRA
RETi'lBII ;
995
JZ
D
i
996
OCX
A
;
997
XRA
D
;
998
ORA
E
;
m
ORA
POLI1BI1 ;
1!l!l!l
JNZ
B
i
1!l1l1 RETI9I: POP
D
;
1002
POP
1003
IN
PRTA!l1 ;
;
1004
RET
1!l!l5 $EJECT
DECLARE PUIl.IC FUNCTION
SAVE D-E REGS
SAVE B-G REGS
LOfI) B REG: 40H, OP-cort'LETE
INITIALIZE TII1E OUT LOOP COUNTER
LOAD A REG: I'I1I'I MGE COItIfINI)
WRITE I1BI1 PURGE CMIAND
READ STATUS REG
TEST BUSY BIT= 1
IF BUSY= 1, POLL STATUS REG FOR 40H
DECREi'lENT TII1E OUT LOOP COUNTER
CLEAR A REG
TEST D REG: !l!lH
TEST E REG: !l!lH
IF NOT ZERO, CONTINUE PCtiING THE I1B/'IPRG COI11AND
TIME OUT ERROR, RETlRII
READ STATUS REG
TEST STATUS: 40H, OP-coI1PLETE
IF (f-C0I'IPl.ETE. Jl1P RE1l'IIlI'I
DECREI1ENT TII1E OUT LOOP COUNTER
CLEAR A REG
TEST D REG: !l!lH
TEST E REG: !l!lH
IF NOT ZERO, CONTIIU POLLING 118M PURGE rot1fN)
RESTORE B-C REGS
RESTORE D-E REGS
READ STATUS REG
RETURN TO CALL
6·146
AP-150
INITIALIZE
TIMEOUT
LOOP COUNTER
READ 7220
STATUS REG
ISSUE
MBMPURGE
COMMAND
READ 7220
STATUS REG
DECREMENT
TIMEOUT
LOOP COUNTER
DECREMENT
TIMEOUT
LOOP COUNTER
READ 7220
STATUS REG
COMMENT: MINIMUM TIME OUT LOOP COUNTER
= 1501'S.
Figure 26. MBMPRG
6·147
ISIS-U 8888/8885 IKRO
LOC IBJ
fISSEtIIlER,
LIE
1.886 ;
1887
PtIlLIC SYI1IKlS
fIBT A88DE
RDBIB.. AIm6
BOOTlJI A II99C
ROFIFO A IlA8A
V3. 8
.1!PK72
Pf&
27
SOCIC£ STRTEIENT
EN)
FIRRS A8813
II!8I.RS A 8A9B
IIIIIIIl A 8961
IIiBIJll A898B
IBfRG A IIB86
WIFO A8A78
RDBI.RS A81
RDBOOT AftC
BOOTlJI A II99C
BSYIIIIt A 8B11
EIUSYFR A 881E
CONT Rm
INFIFO R 8fl7D
1U.T1 R 88Q
PCllIN A 8geR
PRTR81 II 8IFF
RETBT II 8fI2l
~ ~ 8fICE
WIFO R 8fl7Il
IISYRIlL A fIII)E
ElUSYIN A ~7A
1)(1£
R 9867
INTPAR A 8888
IU.TO R 8856
fItlI.RI) R I8BR
RDBI.RS II 81
RETFR A 883B
RETIF A 8fI85
WRITE R 886R
8S'Ml. AR1
BUSYRB A 8A42
FIFIR> R 9fI62
I.OfI)
R 88111
OOTFIF R 8fI8E
P(UIIR A11888
RDBOOT II ftC
RETIN II 8997
RE'TI« A~
Ell~
o
.,
+
I
I
+
254
356
POLARIZATION KEY
i;10
a
gg ~~8;;
+ +
~I
lL~
~~
'0
~
~:=
J
Il-~g
PIN 1
+038
3759-013
1480+ 015
- 005
457
180
Figure 3. Package Outline
:1~"'l
t'\;
(h)
~22X~;~~~;!~H
r1lJ'I=====;;lill~
1
"-'
~~f_il •
~ ~ ,,~
_~ ~ §
...
POLYESTER 94V-O
rr=,iJJL
~~
:: . . . .
14.)
~~~
~I§~.
PIN 1 IDENTIFICATION
PIN'l~!:
~l
I
\
(2Ox)
~=p!.~
DIA
t! "'d?£
,,~~
"!
I . 20
~ ~ ---------~
(2x) COVER 30% GF
~'''I
°l~
OIA
~====~--------
CROSS RECESS BINDING HEAO
1t'\;
... .
~~:~~
NON PLATED HOLES
150
~~~~:~~ ~~TEO
RECOMMENDED
PC BOARD PREPARATION
-(4,)
~~S~~:ER
TAlL
SIDE OF P C BOARD
KEEP CLEAR OF
ELECTRICAL LINES
ASS Y TOOL MAY
CONTACT THESE
&1'
'" ""
HEAT STAKING PINS
NOTE:
SEE PACKAGING INFORMATION, 1983 MEMORY CATALOG FOR DETAILS ON ALTERNATIVE SOCKETS
Figure 4. Socket Outline
6-179
AFN-014838
...
int:_IO
7110
~~
DUMMY
+12V
DUMMY
~~~~~- DETECTOR (ODD)
OUTPUT TRACK
OUTPUT TRACK
REPLICATE
GATE
BOOT
REPLICATE
,
GATE
.
I
<++-++------+\-,/
INPUT TRACK (ODD QUAD)
SWAP
GATE
INPUT TRACK (EVEN QUAD)
Figure 5. Major Track-Minor Loop Architecture of 7110 (one half shown)
6·180
AFN~01483B
inter
7110
ABSOLUTE MAXIMUM RATINGS·
Operating Temperature ......... -20°C to +85°C Case
Relative Humidity ............................... 95%
Shelf Storage Temperature (Data
Integrity Not Guaranteed) ......... - 65°C to + 150"C
Voltage Applied to DET.SUPPLY .............. 14 Volts
Voltage Applied to PULSE.COM ............ 12.6 Volts
Continuous Current between DET.COM and
Detector Outputs ........................... 10 mA
Coil Current ............................... 0.5A D.C.
External Magnetic Field for
Non-Volatile Storage ................... 20 Oersteds
Non-Operating Handling Shock
(without socket) .............................. 200G
Operating Vibration (2 Hz to 2 kHz
with socket) .................................. 20G
D.C. CHARACTERISTICS
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Tc = Range Specified on first page. VDD = 12V ± 5%)
7110-1, -4 Limits
7110-5 Limits[Sl
Min.
Nom.[11
Max.
Min.
Max.
Unit
RESISTANCE: PULSE.COM to GEN.A or GEN.B
9
30
59
8
61.5
ohms
RESISTANCE: PULSE.COM to REP.A or REP.B
9
20
26
8
27
ohms
RESISTANCE: PULSE.COM to SWAP. A or SWAP.B
44
100
149
40
155.5
ohms
RESISTANCE: PULSE.COM to BOOT.REP
3.5
8
24
3
25
ohms
Parameter
RESISTANCE: PULSE.COM to BOOT.SWAP
5
15
36
4.5
37.5
ohms
RESISTANCE: DET.OUT A+ to DET.OUT.A-
670
1030
1903
620
1984
ohms
RESISTANCE: DET.OUT B+ to DETOUT B-
670
1030
1903
620
1984
ohms
RESISTANCE: DETCOM to DET.SUPPLY
355
600
1050
338
1095
ohms
X.COIL RESISTANCE
4.6
Y.COIL RESISTANCE
2.0
ohms
X.COIL INDUCTANCE
97
JLH
Y.COIL INDUCTANCE
80
OPERATING POWER
1.20
1.75
watts
STANDBY POWER
0.25
.45
watts
6-181
329
ohms
JLH
711'0
DRIVE REQUIREMENTS CHARACTERISTICS[2l
Symbol
(T c
=
Range Specified on first page.)
Parameter
Min.
Nom.[ll
Max.
Units
49.95
50.000
50.05
kHz
fR
Field Rotation Frequency
Ipx
X.Coil Peak Current
600
rna
Ipy
Y.Coil Peak Current
750
rna
81x
X.Coil Positive Turn-On Phase
268
270
272
. degrees
82x
X.Coil Positive Turn-Off Phase
16
18
20
degrees
83x
X.Coil Negative Turn-On Phase
88
90
92
degrees
8 4x
X.Coil Negative Turn-Off Phase
196
198
200
81y
Y.Coil Positive Turn-On Phase
0
0
0
degrees
82y
Y.Coil Positive Turn-Off Phase
106
108
110
degrees
83y
Y.Coil Negative Turn-On Phase
178
180
182
degrees
84y
Y.Coil Negative Turn-Of/Phase
286
288
290
degrees
CONTROL PULSE REQUIREMENTS
(Tc = range specified on first page)[Sl
Pulse of Leading Edge
(Degrees)[3l
Amplitude
Pulse
Min.
Nom lll
Width
(Degrees)13l
Max.
Min.
Nom. lll
Max.
Min.
Nom)1l
270 (Odd)
90 (Even)
274
94
3
6.75
8
Max.
GEN.A, GEN.S CUT
62
75
81
266
86
GEN.A, GEN.S TRANSFER
34
40
49
266
86
270 (Odd)
90 (Even)
274
94
86
90
94
REP.A, REPS CUT
170
200
240
268
270
277
3
6.75
8
REP.A, REPS TRANSFER
126
145
160
268
270
277
86
90
94
SWAP
111
125
134
176
180
184
513
517
521
85
100
1'10
268
270
277
3
6.75
8
BOOT. REP TRANSFER
63
75
80
268
270
277
86
90
94
BOOT.SWAP[4l
63
75
80
176
180
184
BOOT.REP CUT
,
360
NOTES:
1. Nominal values are measured at TC = 2SoC.
2. See Fig 6 for test setup and X-V coil waveforms.
3 Pulse timing IS given in terms of the pulse relations as shown in Figure 7. For example, a 7110 operating at fR=SO kHz would have.a
REP.A transfer width of 90° which IS 5 p.s.
4. Boot.Swap is not normally accessed dUring operation. It is uti/ltized at the factory to write the index address and redundant loop
;nformation onto the bootstrap loops before shipment
5 7110-5 is sold only as a matched part with the 7230-S. Matched parts are tested over temperature range for Vee = 12V ±5%.
6·182
AFN-014838
7110
OUTPUT CHARACTERISTICS
Symbol Min.[21 Nom.[11 MaxPl Units
2.7
S1
mV
6
1
So
2.3
Test
Conditions
i-CUT WIDTH
I
See
notes 1,2,3
CUT AMPLITUDE
mV
NOTES:
1. Nominal values are measured at Tc= 25°C
2. Min.!Max. values for S,I50 are measured at worst case
cond itlons and tested to a system error rate of
10- 9 when used with the 7242 formatter sense
amplifier without ECC enabled
3. See Fig 8 for test setup. and Fig 9 for detector output
waveforms and timing.
PHASE
(LEADING EDGE)
I
I
------l-----:TRANSFER WIDTH ---j
Figure 7. Control Pulse Waveform
7110
Iv
• x-
Ix
.. X+
_~f">~_+-
CURRENT
PROBE
,.
y+ --+-~8~-=-y- •
CURRENT
PROBE
1S pI
18
t---t--;---i
HIGH·IMPEDANCE
VARIABLE THRESHOLD
COMPARATOR
Figur~
Figure 6.
x-v Coil Waveforms
8. Test Setup for Output Measurement
Figure 9. Detector Output Waveforms
6-183
7220-1
BUBBLE MEMORY CONTROLLER
7220-1
7220-5
• 8080/8085/8088/8086 Microprocessor
Interface
• Interfaces Up to Eight BPK-70 Bubble
Storage Subsystems
-20 to +85°C
• DMA Handshake Capability
• Single or Multiple Page
Block Transfers
• HMOS Technology
• Standard 40·Pin Dual In· Line Package
• Self·Contained Timing
The Intel® 7220-1 is a complete Bubble Memory Controller (BMC) designed to provide all the interface between Intel
Bubble Memories and standard microprocessors such as the 8080, 8085, 8088, and 8086.
The 7220-1 has self-contained timing generation and DMA handshake capability. Single and/or multiple page block
transfer capability is supported.
The 7220-1 is capable of interfacing with up to eight BPK 70 one megabit bubble storage subsystems. The 7220-5 is
capable of interfacing with up to four BPK 70 one megabit bubble storage subsystems. The 7220-1 uses Intel's high
performance HMOS technology. The 7220-1 is packaged in a standard 40-pin dual in-line package. All inputs and outputs
are directly TTL compatible and the device uses a single + 5 volt supply.
1-------,--------1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
TO
8080
BOB5
....
Y+
v=
TID
1M.S
REP.EN
BOOTEN
SWAP.EN
800T.S EN
c/o
BUS.RD
I
(FSAI
SHIFT.elK
I
I
I
L ______ _
TO
DIO
I
I
I
I
I
I
cs
Figure 2.
Pin Configuration
Figure 1. Block Diagram of a 128K Byte
Bubble Storage System
ADDITIONAL
BPK70's
Intel CorporalJon Assumes No Responslbllty for the Use of Any CircUItry Other Than Circuitry Embodied
©(NTEL CORPORATION. 1982
x=
I
I
S!~~E
I
I
I
I
X+
I
FOR~:~ERI
8088
PWR.FAIL
RESET.OUT
.
6-184
In
an Intel Product No Other CircuIt Patent Licenses are Implied
NOVEMBER 1982
ORDER NUMBER, 2102 ....001
7220·1
HARDWARE DESCRIPTION
The 7220-1 Bubble Memory Controller is packaged in a
40-pin Dual In-Line Package (DIP). The following lists the
individual pins and describes their function.
Table 1. Pin Description
PinNo.
1/0
Vee
40
I
GNO
Signal Name
Source/Destination
Description
+ 5 VOC Supply
20
I
PWR.FAll
1
I
7230 CPG
A low forces a controlled stop sequence and holds
BMC in an IDLE state (similar to RESET).
RESET.OUT
2
°
7250 CPO/7242 FSA
7230 Reference
Current Switch
An active low signal to disable external logic
initiated by PWR.FAIL or RESET signals, but not
active until a stopping point in a field rotation is
reached (if the BMC is causing the bubble
memory drive field to be rotated).
ClK
3
I
Host Bus
4 MHz, TIl·level clock.
RESET
4
I
Host Bus
A low on this pin forces the interruption of any
BMC sequencer activity, performs a controlled
shut·down, and initiates a reset sequence. After
the reset sequence is concluded, a low on this pin
causes a low on the RESET.OUT pin, furthermore,
the next BMC sequencer command must be either
the Initialize or Abort command; all other
commands are ignored.
RO
5
I
Host Bus
A low on this pin enables the BMC output data to
be transferred to the host data bus (Oo·Os).
WR
6
I
Host Bus
A low on this pin enables the contents of the host
data bus (Oo·Os) to be transferred to the BMC.
OACK
7
I
Host Bus
A low signal is a OMA acknowledge. This
notifies the BMC that the next memory cycle is
available to transfer data. This line should be
active only when OMA transfer is desired and the
OMA ENABLE bit has been set. CS should not be
active during OMA transfers except to read status.
If DMA is not used, OACK requires an external
pullup toVcc (5.1K ohm).
ORO
8
0
Host Bus
A high on this pin indicates that a data transfer
between the BMC and the host memory is being
requested.
INT
9
°
Host Bus
A high on this pin indicates that the BMC has a
new status and requires servicing when enabled
by the host CPU.
Ao
10
I
Host Bus
A high on this pin selects the command/status
registers. A low on this pin selects the data
register.
11·18
I/O
Host Bus
Host CPU data bus. An eight·bit bidirectional
port which can be read or written by using the
RO ~nd WR strobes. Do shall be the lSB.
19
I/O
Host Bus
Parity bit.
00.0 7
Os
Ground
6-185
AFN'()1756C
inter
7220-1
Table 1. Pin Description (Continued)
PinNo.
1/0
SourcelDestination
Description
CS
21
I
Host Bus
Chip Select Input. A high on this pin shall disable
the device to all but OMA transfers (i.e., it ignores
bus activity and goes into a high impedance state).
010
22
I/O
7242 FSA
A bidirectional active high data line that shall be
used for serial communications with 7242 FSA
devices.
SYNC
23
0
7242 FSA
An active low output utilized to create time
division multiplexing slots in a 7242 FSA chain. It
shall also indicate the beginning of a data or
command transfer between BMC and 7242 FSA.
SHIFT.ClK
24
0
7242 FSA
A controller generated clock that initiates data
transfer between selected FSAs and their
corresponding bubble memory devices. The timing
of SHIFT.ClK shall vary depending upon whether
data is being read or written to the bubble
memory.
BUS.RD
25
0
*
An active low Signal that indicates that the 010
line is in the output mode. It shall be used to
allow off-board expansion of 7242 FSA devices.
WAIT
26
110
*
A bidirectional pin that shall be tied to the WAIT
pin on other BMCs when operated in parallel. It
shall indicate that an interrupt has been generated
and that the other BMCs should halt in
synchronization with the interrupting BMC. WAIT is
an open collector active low signal. Requires an
external pullup resistor toV ee (5.1K ohm).
ERR.FlG
27
I
7242 FSA
DET.ON
28
0
*
CID
29
0
7242 FSA
A high on this line indicates that the BMC is
beginning an FSA command sequence. A Iowan
this line indicates that the BMC is beginning a
data transmit or receive sequence.
BOOT.SW.EN
30
0
7230 CPG
An active low signal which may be used for
enabling the BOOT.SWAP of the 7230 CPG.
SWAP.EN
31
0
7230 CPG
An active low Signal used to create the swap
function in external circuits.
BOOT. EN
32
0
7230 CPG
An active low signal enabling the bootstrap loop
replicate function in external circuitry.
REP.EN
33
0
7230 CPG
An active low signal used to enable the replicate
function in external circuitry.
TM.B
34
0
7230 CPG
An active low timing signal generated by the
decoder logic for determining TRANSFER pulse
width.
TM.A
35
0
7230 CPG
An active lOw timing signal generated by the
decoder logic for determining CUT pulse width.
36·39
0
7250 CPO
Four active low timing signals generated by the
decoding logic and used to create coil drive
currents in the bubble memory device .
Signal Name
Y-,Y+,
X-,X+
An active low input generated externally by
7242 FSA indicating that an error condition
exists. It is an open collector input which requires
an external pullup resistor (5.1 K ohm).
An active low signal that indicates the system is
in the read mode and may be detecting. It is useful
for power saving in the MBM.
• Not used in minimum (128K byte) system
6-186
AFN-Q1756C
inter
7220-1
Microprocessor-Bus compatible interface for the
magnetic bubble memory system.
FUNCTIONAL DESCRIPTION
The 7220-1 Bubble Memory Controller provides the user
interface to the bubble memory system. The BMC
genera~es all memory system timing and control,
maintains memory address information, interprets and
executes user request for data transfers, and provides a
Figure 3 is a block diagram of the 7220-1 Bubble Memory
Controller (BMC). The following paragraphs describe the
functions of the individual functional sections of the BMC.
POWER FAIL,
ABORT, AND
RESET LOGIC
SEQUENCER
I
I
I
•
Vee
FSA
SELECT
LOGIC
GND
I
N
T
E
R
N
A
L
B
U
S
I
L
I
~
REGISTER
FILE
FIFO
X+
XV>
V-
;
D.
Ao
III!
WII
IIlillR
CI
==:
SYSTEM
BUS
INTERFACE
DATA REGISTER,
DMAAND
INTERRUPT
LOGIC
BUBBLE
SIGNAL
DECODER
DIO & BOOTLOOP
ENCODER/DECODER
DRO
TM.A
TM.B
REP.EN
BOOTEN
SWAP.EN
INT
C/ii
CLK
DIO
Figure 3. 7220-1 Bubble Memory Controller (BMC), Block Diagram
System Bus Interface-The System Bus Interface (SBI)
logic contains the timing and control logic required to
Interface the BMC to a non-multiplexed bus. The logic
also contains the circuitry to check and generate odd
parity on transfers across the bus. The interfacehas input data, output data, and status data latches. The BMC
can interface asynchronously to the host CPU. With a
4-MHz clock, it is capable of sustaining a 1.14 Mbyte per
second transfer rate, while data is available in the BMC
FIFO.
o
FIFO- The FIFO consists of a 40 x 8 bit FIFO RAM for
data storage. The FIFO block also contains input and
output data latches, providing double data buffering, to
Improve the RIW cycle times seen at the system bus interface. The FIFO may be used as a general purpose
FIFO .when a command Is not being executed by the
BMC Sequencer. In this mode, the FIFO READY status
bit becomes a FIFO not-empty indicator Indicating that
the RAM and input/output latches have at least one byte
of data.
DMA and Interrupt Logic-The ORO pin has, two functions:
(1) If the OMA enable bit in the enable register is set,
the ORO pin, in conjunction with the OACK pin, provides a standard OMA transfer capability; I.e., it has
the ability to handshake with an 8257 or 9517/8237
OMA controller chip.
(2) Itthe OMA enable bit is reset, the ORO pin acts as a
"ready for data transfer interrupt" pin. It becomes
active when 22 bytes may be read from or written In·
to the BMC; it is reset when this condition no longer
exists.
Register File-The register file contains 7elght·bit
registers that are accessible by the host CPU. Refer to
the Register Section for details.
6·187
AFN-01756C
7220-1
MBM Address logic and RAM- The MBM address logic
consists of the block length counter, starting address
counter, adder, and MBM Address RAM. The MBM Address RAM is used to store the next available page address for each of up to S dual FSAs. The address maintained is the read address; the write address is generated,
when needed, by adding a constant to the stored read
address.
The block length counter enables multiple page transfers of up to 204S pages in length.
The starting address counter is used as a register to
hold the desired start address. Once'the start address is
reached, the counter is incremented on each subsequent page transfer so that its value is equai to the present read address.
010 Bootloop Oecoder/Encoder- Performs parallel-toserial and serial-ta-parallei conversions between the
FIFO data and the serial bit stream on the 010 line. This
block also generates the BUS.RO signai, which indIcates the direction of data transfer on the 010 line (thiS
is useful in situations which require external buffering
on the 010 line). This block also contains the circuitry
which decodes the boot loop data during a Read
Bootloop or Initialize operation, and encodes the bootloop data during a Write Bootloop operation.
Table 2. 7220-1 BMC 'Timing (Degrees)**
Signal
Start
X+
Y+
270·
O·
YTM.A(OOO)
TM.A (EVEN)
TM.B(OOO)
TM.B (EVEN)
BOOT.EN
REP.EN
SWAP.EN
BOOT.SW..EN:
SHIFTClK (RO)
lS0·
270·
r-
SHIFTCLK (WR)
90·
90·
270·
90·
252·
252·
lS0·
lS0·
lS6.75·
72·
Wlclth
End
His·
37S·
lOS·
19S·
2SS·
274.5·
94.5·
360·
lS0·
360·
360·
697·
lS0·
2S5.75·
360·
lOS·
lOS·
lOS·
4·
4·
90·
90·
lOS·
lOS·
5.7·
~C'
99·
2SS·
'Slays low for 4118 field rolallon penods when wriling Ihe MBM
Boolloop,
"AII phases relalive 10 Y+slari phase All enlnes ±1 26"excepl TM A
width which " ± 0 5"
SWAP.EN, REP.EN, BOOT.SW.EN, and BOOT. EN all go
to the 7230 CPG. They are used to enable, respectively,
the data swap, data replicate, boot swap, and boot
replicate functions within the MBMs.
Sequencer-Controls the execution of commands by
decoding the contents of its own internal ROM in which
the BMC firmware is located. This block also sets and
resets flags and status bits, and controls actions in
other parts of the BMC.
Power Fail and Reset-Provides a means of resetting
the bubble systems in an orderly manner, when activated by the PWR.FAIL signal, the FiESET signal, or the
ABORT command. The additive noise on the PWI:\.FAIL pin
should be less than 150 mV for proper powerfail
operation.
FSA Select logic block contains the logiC which controls the timing of the interacti'on between the BMC and
the FSAs. The FSA selection is determined by the four
high-order bits in the BlR and the four ./ligh-order bits in
the AR, both set by the user.
Bubble Signal Decoder block contains the logiC for
creating all the MBM timing signals. The BMC to bubble
memory interface consists of active low timing signals.
The starting and stopping point of each signal is determined by the decoder logic. Each signal may occur
every field rotation or only once in a number of field rotations. The field rotation in vyhich a timIng pulse occurs
is controlled by the sequencer logic.
Figure 4 and Table 2 illustrate the typical timing signals
for the BMC. These signals are described in the following paragraphs.
X +, X -, Y +, and Y - go to the 7250 CPOs, and are
used to enable the coil drive currents in the MBMs.
, TM_A and TM.B go to the 7230 CPGs, and are used to
determine, respectively, the pulse widths for the CUT
and TRANSFER functions used in replicating and generating the bubbles.
6-188
SHIFT.ClK goes to the FSAs. It is used to control the
timing of events at the interface between each FSA and
its correspondil)g MBM. (Refer to 7242 FSA Specification for a description of the BMC/FSA interla,ce.)
SYNC and C/O control the serial communications between the BMC and the FSAs (on the 010 line).
USER·ACCESSIBLE REGISTERS
The user operates the bubble memory system by reading from or writing to specific registers within the bubble memory controller (BMC). The following paragraphs
identify these registers and gives brief functional
descriptions, including bit configurations and address
aSSignments.
Register Addressing
Seli~ction of the user-accessible registers depends on
register address information sent from the user to the
BMC. This address information is sent via a Single ad·
dress line (deSignated Ao) and data bus lines 0 0 through
0 4.
Both Command Register (CMOR) and Register Address
Counter (RAC) are 4-bit registers which are loaded from
00-03' The status register is selected and ·read, by a
single read request. The command register is selected'
and loa,dep by a single write request. TheJemaining
registers are accessed indirectly, and the desired register
is first selected by placing its address in the RAC. and then
read or written .with a subsequent read or write request.
AFN-01756C ,
inter
7220-1
Figure 4. 7220-1 BMC Timing Diagram
Table 3. Address Assignments for the
User-Accessible Registers (Continued)
Table 3 gives a complete listing of the address asign·
ments for the user-accessible registers. The registers
are listed in two groups. The first group (STR, CMDR,
RAG) consists of those registers that are selected and
accessed in one operation. The second group (UR, BLR,
ER, AR, FI FO) consists of those registers that are
addressed indirectly by the contents of RAC.
RAC
AO 83 82 81 80
Table 3. Address Assignments for the
User-Accessible Registers
lAo 07 D6 D5 04 03 02 01 DO
Symbol
0
0
1
1
0
0
0
Symbol
Name of Register
ReadIWrite
1
UR
BLR LSB
Read or Write
Write Only
0
0
BLRMSB
0
1
1
0
ER
AR LSB
Utility Register
Block Length
Register LSB
Block Length
Register MSB
Enable Register
Address Register
LSB
Address Register
MSB
FIFO Data Buffer
0
0
1
1
0
1
1
1
1
1
1
0
1
1
1
1
ARMSB
0
0
0
0
0
FIFO
Name of Register ReadIWrite
1 0 0 0 1 C C C C
CMDR
Command
Register
1 0 0 0 0 B B B B
RAC
Register Address Write Only
Counter
1 S S S S S S S S
STR
Status Register
Write Only
Write Only
Write Only
Read or Write
Read or Write
Read or Write
SSSSSSSS = a·bit status informatJon returned to the user from the STR
CCCC = 4·bit command code sent to the CMDR by the user.
BBBB = 4·bit register address sent to the RAC by the user.
B3B2B1BO= 4·bit Gontents of RAC at the time the user makes a read 0
write request with AO = O.
LSB = Least Significant Byte
MSB = Most Significant Byte
Read Only
6-189
AFN-OI756C
7220-1
The register file contains the registers with address
1010 through 1111. These registers are also called
parametric registers because they contain flags and
parameters that determine exactly how the BMC will
respond to commands written to the CMDR.
To facilitate such operations, the BMC automatically increments the RAC by one count after each transfer of
data to or from a parametric register.
The RAC increments from the initially loaded value
through address 1111 and then on to 0000 (the FIFO address). When it has reached 0000, it no longer increments. All subsequent data transfers (with AO 0) will
be to or from the FIFO until such time as the RAC is
loaded with a different register address.
=
REGISTER DESCRIPTIONS
Commands relating to the bootloop, and used only for
diagnostic purposes, are:
Read Bootloop Register
Write Bootloop Register
Write Bootloop Register Masked
Read Boot/oop
Write Bootloop
Status Register (STR) 8 Bits, Read Only
The user reads the BMC status register in response to
an interrupt signal, or as part of the polling process in a
polled data transfer mode. The status register provides
information about error conditions, completion or termination of commands, and about the BMC's readiness
to transfer data or accept new commands. The individual bit descriptions are as follows:
Command Register (CMDR) 4 Bits, Write Only
STATUS REGISTER
The user issues a command to the BMC by writing a
4-bit command code to the CMDR.
FIFO READY
PARITY ERROR
Table 4 lists the 4-bit command codes used to issue the
sixteen commands recognized by the BMC:
~--~... UNCORRECTABLE ERROR
' - - - - - -__ CORRECTABLE ERROR
Table 7 is a listing of the commands and their functions.
'-------~... TIMING ERROR
' - - - - - - - -__ OP FAIL
' - - - - - - - - - -..... OP COMPLETE
' - - - - - - - - - - - - - - . ,... BUSY
Table 4_ Command Code Definitions
03
02
01
Do
Command Name
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Write Bootloop Register Masked
Initialize
Read Bubble Data
Write Bubble Data
Read Seek
Read Bootloop Register
Write Bootloop Register
Write Bootloop
Read FSA Status
Abort
Write Seek
Read Bootloop
Read Corrected Data
Reset FIFO
MBM Purge
Software Reset
1
0
0
1
1
BUSY (when '" 1) indicates that the BMC is in the
process of executing a command. When equal to
0, BUSY indicates that the BMC is ready to receive
a new command. In the case of Read Bubble Data,
Read Bootloop, read Bootloop Register, or Read
Corrected Data commands, BUSY may also indicate
that the data has not been completely removed from
the FIFO, and that DRO is still active. BUSY will then
drop as soon as DRO does (after the user has finished reading the data remaining in the FIFO).
OP COMPLETE (when = 1) indicates the successful
completion of a command.
OP FAIL (when = 1) indicates that the BUSY bit has
gone inactive with either theTIMING ERROR or UNCORRECTABLE ERROR bits active.
The most commonly used commands in normal operation are:
TIMING ERROR (when = 1) indicates that a FSA has
reported a timing error to the BMC, or that the host
system has failed to keep up with the BMC, thereby
causing the BMC FIFO to overflow or to underflow.
TIMING ERROR is als6 set if no boot/oop sync word
is found dunng initialization, or if a Write Bootloop
command is issued when the WRITE BOOTLOOP
ENABLE bit is equal to zero in the enable register.
Initialize
Read Bubble Data
Write Bubble Data
Reset FIFO
Read Seek
Write Seek
Abort
Read Corrected Data
Software Reset
Read FSA Status
MBM Purge
CORRECTABLE ERROR (when = 1) inpicates that
a FSA has reported to the BMC that a correctable
error has been detected in the last data block
transferred.
6-190
AFN·01756C
7220-1
UNCORRECTASLE ERROR (when = 1) indicates
that at least one FSA has reported to the BMC that an _
uncorrectable error has been detected in the last
data block transferred.
=
PARITY ERROR (when 1) indicates that the
BMC's parity check circuitry has detected a parity
error on a data byte sent to the BMC by the user on
the data lines 00-08'
/
FIFO READY has two functions. The FIFO READY
functions are as follows:
ENABLE RCD enables the BMC to give the Read
Corrected Data command to the FSAs when an error
has been detected. This causes each FSA to correct
the error (if possible) and also to transfer the corrected'data to the BMC. The Read Corrected Data command is also used to read into the BMC data
previously corrected by the FSA in response to an
Internally Correct Data command. In either case,
when the data transfer has been completed, the
BMC reads each FSA's status to determine whether
or not the error was correctable. In the cas!! of an
uncorrectable error, bad data may have been sent to
the user. The value of ENABLE RGD affects the action of INTERRUPT ENABLE (ERF!OR).
NOTE: IF RAC "to FIFO, FIFO READY = 1
STATUS BITS
FIFO READY
READ
WRITE
BUSY
1
1
data in
FIFO
space in
FIFO
0
1
no data
no space
1
0
0
0
ENABLE ICD enables the BMC to give the Internally Correct Data command to the FSAs when an
error has been detected by the FSA's error detection
and correction circuitry. Each FSA responds to such
a command by internally cycling the data through its
error correction network. When finished, the FSA
returns status to the BMC as to whether or not the
error is correctable. The value of ENABLE ICD affects the action of INTERRUPT ENABLE (ERROR).
- data in FIFO - FIFO empty -
Although the status word can 'be read at any time, the
status information, bit 1 through 6, is not valid until the
BUSY bit is low.
=
WRITE BOOTLOOP ENABLE (when 1)' enables
the bootloop to be written. If this bit is equal to
zero, and a Write Bootloop command is received
by the BMC, the command is aborted and the TIM·
ING ERROR bit is set in the STR.
STR Bits 1 through 6 are reset when a new command is
issued. They may also be reset by making a write request (WR=O) to the BMC with Ao=1, 0.=0, and 0 5 =1
(that is, writing the RAC with 0.= 1). This operation also
resets the "INT" pin to "0". NOTE: A byte of FIFO data
can be lost when using this procedure if the RAC is
written to other than the FIFO address when data is still
present in FIFO.
MFBTR controls the maximum burst transfer rate
from FSA(s) to BMC FIFO. This rate is variable on
the "last page" of a multiple page transfer. (In one
page transfers the last page is the only page.) See
Table 5 for effects of this bit on the various 7220-1
commands.
Enable Register (ER) 8 Bits, Write Only
The user sets various bits of the enable register to
enable or disable various functions within the BMC or
the FSAs. The individual bit descriptions are as follows:
INTERRUPT ENABLE (NORMAL)
INTERRUPT ENABLE (ERROR)
L-.._ _ _ DMA ENABLE
' - - - - - _ MAXIMUM FSA·BMC TRANSFER RATE
' - - - - - - _ WRITE BOOTLOOP ENABLE
' - - - - - - - - - - . . E N A 8 L E FICO
L-..--------_ENABLEICD
L - . . - - - - - - - - - _ E N A B L E PARITY INTERRUPT
In the above figure and In
abbreviations are used:
t~e
text below, the following
ICD = INTERNALLY CORRECT DATA
RCD READ CORRECTED DATA
UCE = UNCORRECTABLE ERROR
CE
CORRECTABLE ERROR
TE = TIMING ERROR
=
=
Table 5. MFBTR Bit Definitions
Number
01 MBMI
Operated
in Parallel
Maximum
Required
Host Interlace
Date Rate
Read Command
Write Command
1
50K byte/sec
0
N/A
2
lOOK byte/sec
Ii
N/A
4
200K byte/sec
8
1
400K byte/sec
t 2 5K byte/sec
0
0
N/A
N/A
2
4
25K byte/sec
50K byte/sec
8
lOOK byte/sec
1
1
1
1
0
0
0
MFBTR Bit
0
NOTE. The MFBTR bl.t should always be set to "0" for all commands
except "Read Bubble Data."
=
DMA ENABLE (when 1) enables the BMC to
operate in DMA data transfer mode, using the DRQ
and DACK signals in interaction with a DMA controller. When equal tq zero, DMA ENABLE sets up
the controller to support Interrupt driven or polled
data transfer.
ENABLE PARITY INTERRUPT enables the BMC to
Interrupt the host system (via the INT line) when
the BMC detects a parity error on the data bus
lines 00-07'
'
6-191
AFNo017S6C
intJ
7220·1
INTERRUPT ENABLE (ERROR) selects error conditions under which the BMC stollis command execution and interrupts the host processor (via the
INT line). INTERRUPT ENABLE (ERROR) operates
in conjunction with ENABLE ICD and ENABLE
RCD.
what starting address location shall be used in a data
read or write operatiCin. The bit configuration is as
follows:
ADDRESS REGISTER MSB
X-.MBM SELECT
Enable
ICD
Enable
RCD
Interrupt
Enable
(ERROR)
Interrupt Action
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
·1
0
1
Interrupt on TE only
Interrupt on UCE or TE
Interrupt on UCE, CE, or TE
Interrupt on UCE or TE
Interrupt on UCE, CE, orTE
Not used
Not used
No interrupts due to errors
TE = Timing Error, CE = Correctable Error,
UCE = Uncorrectable Error.
INTERRUPT ENABLE (NORMAL) (when = 1)
enables the BMC to interrupt the host system (via
the INT line), when a command execution has been
successfully completed (OP COMPlETE= 1 in the
STR).
The selection of the M BMs to be read or written is
specified by AR MSB Bits 3-6. The BMCs interpretation
of these bits depends on the number of MBMs in a
group, which is specified by BlR MSB Bits 4-7.
Table 6 shows which MBM groups are selected in
response to given values for BlR MSB Bits 4-7 and AR
MSB Bits 3-6. A 1-megabyte system (8 MBMs) is
represented, with the FSA channels numbered 0
through F:
Table 6_ Selection of FSA Channels
AR MSB Bits
(6,5,4,3)
The utility register is a general purpose register available to the user in connection with bubble memory
system operations. It has no direct effect on the BMC
operation, but is provided as a convenience to the user.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Block length Register (BlR) 16 Bits,
Write Only
The contents of the block length register determine the
system page size and also the number of pages to be
transferred in response to a single bubble data read or
write command. The bit configuration is as follows:
BLOCK LENGTH REGISTER MSB
BLOCK LENGTH REGISTER LSB
1716151413121,101
NUMBER OF FSA
CHANNELS INFC)
STARTING ADDRESS WITHIN EACH MBM
Within each MBM there are 2048 possible starting address locations for a data read or write operation, hence
the requirement for 11 bits in the starting address.
Utility Register (UR) 8 Bits, Read or Write
1716151413121,101
_____ x
ADDRESS REGISTER LSB
17161 5 14131 21,101
BlR MSB Bits (7,6,5,4)
0000
0001
0010
0100
1000
0
1
2
3
0,1
2,3
0,1,2,3
o to 7
OtoF
4,5,6,7
8,9,A,S
C,D,E,F
8to F
4
5
6
7
8
9
A
S
C
D
E
F
4,5
6,7
8,9
A,B
C,D
E,F
NUMBER OF PAGES TO BE TRANSFERRED
The system page size is proportional to the number of
magnetic bubble memory modules (MBMs) operating in
parallel during the data read or write operation. Each
MBM requires two FSA channels. Bits 4 through 7 of
BlR MSB actually specify the number of FSA channels
to be accessed.
The acceSSing of single FSA channels is done only as
part of diagnostiC processes. AR MSB Bit 7 is not used.
The BlR lSB, together with the 3 least significant bits
of the BlR MSB, specify the number of pages to be
transferred. Up to 2048 pages can be transferred in
response to a single bubble data read· or write command, hence the requirement for 11 bits. All 11 bits
equal to zero specifies a 2048 page transfer.
The BMC FIFO is a 40-byte buffer through which data
passes on its way from the FSAs to the user, or from the
user to the FSAs. The FIFO allows the data transfer to
proceed in an asynchronous and flexible manner, and
relaxes timing constraints, both to the FSAs and also to
the user's equipment. The user's system must, however,
meet the data rate requirements. When the BMC is busy
(executing a command) the FIFO functions as a data
buffer. When the BMC is not busy, the FIFO is available
to the user as a general purpose FIFO.
FIFO Data Buffer (FIFO) 40 x 8 Bits, Read or
Write
Address Register (AR) 16 Bits, Read or Write
The contents of the address register determine which
MBM group is to be accessed, and, within that group,
6-192
AFN~01756C
inter
7220-1
FUNCTIONAL OPERATION
data bit from the B channel FIFO is placed on the 010
fine. The BMC continues to output SYNC pulses, once
every 20 or 80 clock cycles, each time receiving two data
bitslin return.
The IC components used in the bubble memory systems
have been designed with transparency in mind-that is,
a maximum number of operations are handled by the
hardware, and firmware of these components.
Each one-Megabit Bubble Memory (MBM) operates in its
own domain, and is unaffected by the number of bubble
memories in the system. The roles played by the MBM's
immediate support circuitry can be described as if the
system contained only one MBM module.
In the BMC, the data undergoes serial-to-parallel conversion, and is assembled into bytes, which are then placed
in the BMC FIFO, which can hold 40 bytes of data. From
this FIFO, the data bytes are written onto the user interface.
, During a write operation, the data flow consists of the
corresponding operations in the reverse order.
Data Flow Within the Magnetic Bubble
""emory (MBM) System (Single MBM
Systems)
Multiple·MBM Systems.
The 7220-1 BMC can interface up to 8 one-megabit BPK70
Bubble Storage subsystems. The data flow in a multipleBPK70 system is in most respects similar to that which
occurs in a one-BKP70 subsystem. The difference is in
the time-division multiplexing that occurs on the 010
bus line between the BMC and the FSAs.
During a read operation, data flows as follows: The
data from the MBM is input to the Formatter/Sense
Amplifier (FSA). Data from each channel (A channel or B
channel) of the MBM goes to the corresponding channel
of the FSA. In the FSA, the data is paired up with the corresponding bit in the FSA's boot loop register to determine whether it represents data from a 'good' loop. If it
does, the data bit is stored in the FSA FIFO. Error detection and correction (if enabled by the user) is applied to
each block of 256 data bits.
For data transfer operations, the BMC may exchange
data with as few as two FSA channels (one BPK70) or as
many as 16 FSA channels (eight BPK70s).
SOFTWARE INTERFACE-The general procedure for
communicating with the BMC is:
From the FSA FIFO, data is sent to the bubble memory
controller (BMC) in the form of a serial bit stream, via a
one-line bidirectional data bus (010). The data is multiplexed onto the 010 line, with data bits coming alternately from the A and B channels of the FSA. The BMC
outputs a SYNC pulse to the SElECT.IN input of the
FSA. The FSA responds by placing a data bit from the A
channel FIFO on the 010 line. One clock cycle later, a
Pass parameters to the BMC by loading the
registers.
Send the desired command.
Read the status/command register until BMC is not
busy (or use "INT" pin).
Examine the status register to determine whether
the operation was successful.
Table 7. Detailed Command Descriptions
Initialize
The BMC executes the Initialize command by first interrogating the bubble system to
determine how many FSAs are present, then reading and decoding the bootloop from each
MBM and storing the results in the corresponding FSA's bootloop register. All the parametric
registers must be properly set up before issuing the Initialize command.
Read Bubble Data
The Read Bubble Data command causes data to be read from the MBMs into the BMC FIFO,
The selection of the MBMs to be accessec1 and the starting address for the read operation is
specified in the address register (AR). The block length register (BlR) specifies the number of
system pages to be read. All the parametric registers must be properly set up before isstJing
the Read Bubble Data command.
Write Bubble Data
The Write Bubble Data command causes data to be read from the BMC FIFO and written into
the MBMs. The selection of the MBMs to be accessed and the starting address for the write
operation is specified in the address register (AR). The block length register (BlR) specifies
the number of system pages to be written. All the parametric registers must be properly set up
before issuing the Write Bubble Data command.
Read Seek
The Read Seek command rotates the selected MBMs to a designated page address location.
No data transfer occurs. The positioning is such that the next data location available to be read
is the specified (i n AR) page address plus one.'The Read Seek command may be used to reduce
latency (access time) in cases where information is available for the user to predict the
location of an impending read reference to the MBMs.
6-193
AFN-01756C
inter
7220-1
Table 7. Detailed Command Descriptions (Continued)
Write Seek
The Write Seek command rotates the selected MBMs to a designated page address location.
No data transfer occurs. The positioning is such that the next data location available to be
written is the specified (inAR) page address plus one. TheWrite Seek command may be used to
reduce latency (access time) in cases where information is available for the user to predict the
location of an impending write reference to the MBMs.
Abort
The Abort command causes a controlled termination of the command currently being
executed by the BMC. The Abort command will be accepted by the BMC (and is typically
issued) when the BMC is busy.
MBM Purge
The MBM Purge command clears all BMC registers, counters, and the MBM address RAM.
Furthermore, it determines how many FSA channels are present in the system and stores this
value in the 7220-1. The "INITIALIZE" command uses this command as a subroutine.
Read Corrected Data The Read Corrected Data command causes the BMC to read into the BMC FIFO a 256-bit block
of data from the FIFO of each selected FSA channel, after an error has been detected. The data
cydes through the error correction network of the FSA. After the data has been read, the FSA
reports to the BMC whether or not the error was correctable. The Read Corrected Data
command is used only when the system is in error correction mode (ENABLE ICD or ENABLE
RCD set in the ER).
Software Reset
The Software Reset command clears the BMC FIFO and all registers, except those containing
initialization parameters. It also causes the BMC to send the Software Reset command to
selected FSAs in the system. No reinitialization is needed after this command.
Read FSA Status
The Read FSA Status command causes the BMC to read the B-bit status register of all FSAs,
and to store this information in the BMC FIFO. The Read FSA Status command is independent
all parametric registers.
Read Bootloop
Register
The Read Bootloop Register command causes the BMC to read the bootloop register of the
selected FSA channels and to store this information in the BMC FIFO. Twenty bytes are
transferred for each FSA channel selected.
Write Bootloop
Register Masked
Proper operation of the FSAs during data transfer to or from the MBMs requires that the
bootloop register contain (if error correction is used) exactly 270 logic 1s for each FSA
bootloop register. The user may select any subset of 270 "good" loops from the total number
of available loops (if error correction is not used, 270 replaced by 272). As an alternative, the
Write' Bootloop Register Masked command may be used. This command counts the number of
logic 1s and masks out the remaining 1s after the proper count has been reached, The
Initialize command uses this command as a subroutine,
Read Bootloop
The Read Bootloop command causes the BMC to read the bootloop from the selected MBM,
and to store the decodeci bootloop information in the BMC FIFO. The Initialize command uses
this command as a subroutine,
Write Bootloop
The Write Bootloop command causes the existing contents of the selected MBM's bootloop to
be replaced by new bootloop data based on 40 bytes of information stored in the FIFO (the
user must actually write 41 bytes, where the 41st byte is all Os). Encoding of the bootloop data
is done by the BMC hardware.
6-194
AFN-01756C
7220-1
ABSOLUTE MAXIMUM RATINGS
Temperature under bias .............. -40 to +100·C
Storage Temperature ............. - 65·C to + 150·C
All Input or Output Voltages and
Vee Supply Voltage ..................... -0.5V to 7V
'NOTICE: Stresses above those listed under "Absolute Max·
imum Ratings" may cause permanent damage to the device.
This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated
in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
D.C. CHARACTERISTICS (TA = see front page; Vee = 5.0V +5%, -10%)
Parameter
Symbol
Vil
I nput low Voltage
Min.
Max.
Unit
0.8
V
Test Condition
VIH('I
.Input High Voltage (all but PWR.FAll)
2.0
Vee+ 0.5V
V
VIH (2)
Input High Voltage (PWR.FAll)
2.5
Vee+ 0.5V
V
VOl(,)
Output low Voltage
(All outputs except DET.ON, BUS.Rp,
SHIFT.ClK, and SYNC
.45
V
10l
VOl (2)
Output low Voltage
DET.ON, BUS.RD, SHIFT.ClK, SYNC
.45
V
IOL = 1.6 rnA
VOH
Output High Voltage
Illll
Input leakage Current
10
,..A
O",VIN",V ee
10
,..A
0.45", VOUT '" Vee
200
rnA
10Fli
Output Float leakage
lee
Power Supply Current from Vee
V
2.4
10H
= 3.2 rnA
= 400,..A
A.C. CHARACTERISTICS
(T A = see table 1; Vee = 5.0V + 5%, - 10%; CL = 150 pF; unless otherwise noted.)
Symbol
Min.
Max.
Unit
tp
Clock Period
Parameter
249.75
250.25
ns
t~
Clock Phase Width (High Time)
.45tp
.55 tp
tR·tF
Input Signal Rise and Fall Time
Test Condition
30
ns
Min.
Max.
Unit
150
ns
Under Pin loads'
10
250
ns
Ul)der Pin loads'
FSA INTERFACE TIMINGS (under pin loading)
Symbol
Parameter
teDv
ClK to 010 Valid Delay
teDF
ClK.to 010 Entering Float
teDE
ClK to 010 Enabled from Float
teDH
ClK to 010 Hold Time
150
tesol
ClK to SYNC leading Edge Delay
te$OT
ClK to SYNC Trailing Edge Delay
10
toe
010 Setup Time to Clock
tDHe
010 Hold Time from Clock
teol
ClK to Output leading Edge
teoT
ClK to Output Trailing Edge
tEW
ERR. FlG Pulse Width
tseFT
SHIFTClK to Y - Trailing Edge
ns
Under Pin loads'
ns
Under Pin loads'
120
ns
Under Pin loads'
100
ns
Under Pin loads'
80
ns
Under Pin loads'
0
ns
Under Pin loads'
150
ns
Under Pin loads'
190
ns
Under Pin loads'
ns
Under Pin loads'
ns
Under Pin loads'
0
0
200
80
6·1.95
Test Condition
200
-
AFN·017S6C
inter
7220.. 1
A.C. CHARACTERISTICS (Continued) (TA = see table 1; VCC =5.0 +5%, -10%; Cl =150 pF;
READ CYCLE (HOST INTERFACE)
Symbol
unless otherwise notell.)
Parameter
Min.
Max.
Unit
tAC
Select Setup to RD~
0
ns
tCA
Select Hold from RDf
0
ns
tRR
RD Pulse Width
200
ns
tAD
Data Delay from Address
150
ns
tRO
Data Delay from RDt
150
ns
tOF
Output Float Delay
10
100
ns
toe
DACK Setup to RD~
0
ns
tco
DACK Hold from RDt
0
ns
tKO
Data Delay from DACK~
150
(DMA Mode)
41.-1,
"Read:' Cycle Time
tCYCR
Test Condition
ns
In non DMA mode.
ns
ICYCR Min. = 61.-1.
WRITE CYCLE (HOST INTERFACE)
Symbol
Parameter
Min.
Select Setup to WR ~
tAC
Max.
Unit
0
ns
tCA
Select Hold from WRf
0
ns
tww
WR Pulse Width
200
ns
tow
Data Setup to WRf
200
ns
tWD
Data Hold from WRf
0
ns
tDC
DACK Setup to WRt
0
ns
tco
DACK Hold from WR f
0
ns
tCYCW
'Write" Cycle Time
tca
Request Hoid from RD or WR
(Non-Burst Mode)
tDEADW
Inaclive Time between WRI and WRI
41p
tDEADR
Inactive Time between RDI and RDI
150
Test Condition
4tp + tww
150
ns
ns
7250·7230 INTERFACE TIMINGS
Symbol
Parameter
Max.
Unit
Test Condition
tCBl
ClK to Bubble Signal leading Edge
250
ns
Under Pin loads'
tCBT
ClK to Bubble Signal Trailing Edge
250
ns
Under Pin loads'
Min.
"Bubble Pm loads Showl} Below
PIN LOADINGS
Pin Names
X+, X-, Y+, YTM A, TM B, REP EN, BOOT EN,
SWAP EN, BOOT SW EN, CiD.
ERR FLG, WAIT, SYNC
DET ON & SHIFT CLK
BUS READ
Value
Unit
150
pF
50
pF
100
pF
10
pF
6-196
AFN'()1756C
inter
7220-1
WAVEFORMS
READ (HOST INTERFACE)
i+----------tCVCR--------+I
DACK------' W--------~------------------------~
cs --------1~ Jr----1I+-------------t--,L _----~ r---+---Ao -----+OJ 1'--++---------t--4'----,., "----t---
c
DATA BUS
1+----10>0----+1
14----IDEADR-----+1
t-----IKD>----~
WRITE (HOST INTERFACE)
....- - - - - - - - - I c " . - - - - - - - - - - - - i
~----~~~---~------------~ ,----~ ,----1~--Ci ----~ .JI~--++----------------+-,..
,---'" ,---1--
A o - - - - J ~--~--------~~'----J ~
....- - - I w w ' - - - - - I
___
~_
WI!
DATA BUS
1+-----IDW'----_I+--lwD
DMA (HOST INTERFACE)
i+----tDe"o----i
DRO
I-Ico
\
,1/
IIIlORWII
6-197
~---------
AFN'()1756C
inter
7220-1
WAVEFORMS (Continued).
7242 INTERFACE TIMINGS
Y- _ _
SHIFTCLK (READ)
~~.j=
J
7250 & 7230 INTERFACE TIMINGS
CLK
BUBBLE SIG
7250 & 7230
6-198
AFN-01756C
7230
CURRENT PULSE GENERATOR
FOR BUBBLE MEMORIES
7230
o to 70 e
0
7230-4
10 to 55°e
7230-5
-20 to +85°e
• TTL Compatible Inputs
• Provides All Pulses for Intel Bubble
Memories
-Replicate, Swap, Generate,
Boot Replicate and Bootswap
• Current Sink Outputs Designed to
Directly Drive Bubble Memory
• Direct Interface to Bubble Memory
Controller
• Automatic Power Fail and Reset
• Operates from +5 and +12 Volts Only
• Schottky Bipolar Technology
• Standard 22-Pin Dual-In-Line Package
The Intel 7230 is a Current Pulse Generator (CPG) designed to drive Intel Magnetics Bubble Memories. The 7230
is a Schottky Bipolar, TTL input compatible device that converts digital timing signals to analog current pulses.
The CPG provides all pulses for Intel Magnetics Bubble Memories (7110 Family). These include Replicate,
Swap, Generate, Boot Replicate and Bootswap pulses. The high-current sinking outputs directly drive the
bubble memory. It also directly interfaces to the Intel Magnetics Bubble Memory Controller (7220-1) and
Formatter/Sense amplifier (7242).
The 7230 operates from 5-volt and 12-volt power supplies and is in a standard 22-pin dual-in-line package.
1----------------1
TO
8080
8085
8088
8086
7220-1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
BUBBLE
MEMORY
CONTROLLER
(BMC)
I
~-:::",::--....I
I
Figure 2. Pin Configuration
I
I
I
I
I
TO
ADDITIONAL
Figure 1. Block Diagram of Single Bubble
Memory System-128K Bytes
Intel Corporation Assumes No Responslbllty for the Use of Any Circuitry Other Than Circuitry Embodied
© INTELCOR,PORATION, 1982
6-199
In
an Intel Product No Other CIrcuit Patent Licenses 8J'B Implied'
NOVEMBER 19B2
ORDER NUMBER: 210798-001
intJ
7230
EXTERNAL RESISTOR REQUIREMENTS
Connect a 1% 3.48K ohm resistor based between pin
20 and ground or referenced current switch as outlined in BPK72 User's Manual.
.
Table 1. Pin Description
Symbol
Pin No.
BOOT.EN
10
An active low input enabling the BOOT. REP output current pulse.
BOOT.REP
13
An output providing the current pulse for bootstrap loop replication in
the bubble memory.
14
An output providing a current pulse which may be used for writing data
into the bootstrap loop.
BOOT.SW.EN
9
An active low input enabling the BOOT.SWAP output current pulse.
CS
7
An active low input for selecting the chip. The chip powers down during
deselect.
GEN.A
18
An output providing the current pulse for writing data into the "A" quads
of the bubble memory.
GEN.B
19
An output providing the current pulse for writing data into the "~" quads
of the bubble memory.
BOOT.SWAP
-
Description
GEN.EN.A
5
An active low input enabling the GEN.A output current pulse.
GEN.EN.B
4
An active low input enabling the GEN.B output current pulse.
PWR.FAIL
21
An active low, open collector output indicating that either Vee or Voo is
below its threshold value.
J
REFR.
20
The pin for the reference current generator to which an external
resistance must be connected.
REP.A
15
An output providing the current pulse for replication of data in the "A"
quads of the bubble memory.
REP.B
16
An output providing the current pulse for replication of data in the "B"
quads of the bubble memory.
REP.EN
8
An active low input enabling the REP.A and REP.B outputs.
SWAP
17
An output providing the current pulse for exchanging the data between
the input track and the storage loops in the bubble memory.
SWAP.EN
6
An active low input enabling the SWAP output.
TM.A
2
An active low timing signal determining the cut pulse widths of the
BOOT.REP, GEN. A, GEN.B, REP. A and REP.B outputs.
TM.B
3
An active low timing signal determining the transfer pulse widths of the
BOOT.REp, GEN.A, GEN.B, REP.A and REP.B outputs.
6-200
AFN'()13678
7230
1--_ _ _ _ _~2::!1__<> PWR FAIL
EXTERNAL
RESISTOR
REFERENCE CURRENT
GENERATOR
TM.S
REP EN o-=-...,....+-H-"<:--....
I
I
I
I
L ______ _
TO
AD:;~?~:L
SELECT OUT
2
C/D
3
ERR FLAG
4
RESET
VOD
SHIFT elK
DEl A+
14
ENABlE.8
12
DATA,OUT.B
11
DATA OUT A
'---_---.r-
Figure 2. Pin Configuration
I
I
Figure 1. Block Diagram of Single Bubble
Memory System-128K Bytes
Intel Corporation Assumea No Reaponsibilty for the Use of Any Circuitry Other Than Circuitry Embodied in an Intel Product. No Other Circuit P~tent Licenses 8'Pe Implied.
,© INTEL CORPORATION, 1982
6·204
ORDER
NUM:~:'E~~i~:~
intJ
7242
Table 1. Pin Description
Pin No.
Description
C/O
3
Command/Data signal. This signal shall cause the FSA to enter a
receive command mode when high and to interpret the serial data line
as data when low. Any previously active command will be immediately
terminated by ciO.
CLK
18
Same TTL-level clock used to generate internal timing as used for
7220-1.
CS
1
An active low signa!...]!sed for multiplexing of FSAs. The FSA is
disabled whenever CS is high (i.e., it presents a high impedance to the
bus and ignores all bus activity).
Symbol
DATA.OUT.A, DATA.OUT.B
.11, 12
DET.A+,DET.A-,DET.B+,
DET.B-
6,7,8,9
010
17
Output data from the FIFO to the MBM generate circuitry. Used to
write data into the bubble device (active low).
Differential signal lines from the MBM detector.
The Serial Bus data line (a bidirectional active high signal).
13, 14
TTL-level outputs utilized as chip selects for other interface circuits.
They shall be set and reset by the Command Decoder under
instruction of the Controller (active low).
ERR.FLG
4
An error flag used to interrupt the Controller to indicate that an error
condition exists. It shall be an open drain, active low signal.
RESET
16
An active low signal that shall reset all flags and pOinters in the FSA as
well as disabling the chip as the CS signal does. The RESET pulse
width must be 5 clock periods to assure the FSA is properly reset.
SELECT.IN
19
An input utilized for time-division multipleXing. An active low signal
whose presence indicates that the FSA is to send or receive data from
the Serial Bus during the next two clock periods.
SELECT.OUT
2
The SELECT.lN pulse delayed by two clocks. It shall be connected to
the SELECT.IN pin of the next FSA. It is delayed by two clocks because
the FSA is a dual-channel device. Channel A shall internally pass
SELECT.lN to Channel B (delayed by one clock).
SHIFT.CLK
15
A Controller-generated clock signal that shall be used to cloc~ data
out of the bubble lIO Output Latch to the bubble mo.dule during a
write operation and to cause bubble signals to be converted by the
Sense Amp and clocked into the Bubble I/O Input Latch on a read.
ENABLE. A, ENABLE.B
1/0 Latches, Flags, and Bus Control-Each channel
FUNCTIONAL DESCRIPTION
The following is a brief description of each block of
the 7242 FSA,
Serial Communications-The Serial Communications block handles all transfers on the Serial Bus
and is shared by both channels of FSA.
Command Decoder-The Command Decoder interprets commands by the Serial Communication logic
and sets the appropriate command and enable lines.
It also maintains FSA status, and generates various
reset lines.
of the FSA has its own internal Data Bus, on which all
data transfers ~re made. There is a Flag and a bidirectional Latch in each "I/O Latches-Flag" block. Only
one Latch is used in a given operation and the Flag
tells the Bus Controller whether or not the Latch is
full. The Bus Controller monitors these flags, and
other control signals, to determine when each device
. should have access to the internal Data Bus. When a
transfer is to be made, the appropriate devices are
enabled, the Bus is enabled, and the transfer takes
place synchronously by virtue of a transparent State
Machine Sequencer.
Internal Data Bus-The Internal Data Bus is the
main data link between the Serial Communications
block and all other data sources in each half of the
FSA.
6-205
FIFO-The FIFO is a variable-length First-In-FirstOut buffer utilized to store data passing to and from
the MBM module. The FIFO is logically 272 bits in
length in the "no error correction" mode. It is 270 bits
in the "error correction" mode, since 256 bits of the
AFN·01358B
7242
data and a 14-bit error correction code must be used
in this mode of operation.
The FIFO pointers are reset by hardware or software
resets or each time a command to read or write is
received by the Command Decoder.
If a block length other than 272 bits is used in the no
error correction mode, the FIFO pointers will not
return to word zero at the end of each block transfer.
This is of no consequence if one is not concerned
about the absolute location of data in the FIFO.
Keeping in mind that the FIFO is only 272 bits
physically, any block length may be used up to and
including 320.
Bootstrap Loop Register-The Bootstrap Loop
Register is a 160-bit register that contains
information detailing the location of bad loops in the
MBM module. This data will enable bubble I/O to
ensure that bits are not loaded in the FIFO from bad
loops, or written from the FIFO into bad. loops. A
logic zero (absence of a bubble) is written into bad
loops.
Error Correction Logic-The Error Correction Logic
contains the circuitry to implement a burst error
correcting code capable of correcting any single
burst error of length equal to or less than 5, anywhere
in the 270-bit data stream, including the error
correction code which is 14 bits in length. A
Correction Enable bit may be set or reset via a special
command. When reset, the entire error correction
network is disabled and block length may vary from
270 bits. Error detection shall be accomplished on all
data transfers (when enabled); however, correction
cannot take place unless the FSA is operated in a
buffered mode (i.e., an entire block is read prior to
passing any data to the Controller).
Bubble I/O-The Bubble I/O consists of an
integrated Sense Amplifier and an output driver. The
Sense Amplifier consists of a sample-and-hold
circuit and a differential, chopper-stabilized
comparator.
Enables-The ENABLE.A and ENABLE.B outputs
are utilized as chip selects for external circuitry. To
set an ENABLE line, the desi'red channel of the FSA
must be selected and Read or Write MBM, Set Enable
Bit, Initialize, Read Corrected Data, or Internally
Correct Data command is sent. Any other command
sequence will reset the ENABLE lines.
COMMANDS
FSA Commands
The FSA shall receive a four-bit command word via
the Serial Bus. In addition, some of the commands
require additional data bits, e.g., status to be passed
serially. The four bits shall be interpreted as shown in
Table 2. The effects on the Status bits, Correction
Enable bit, and Enable pins are summarized in
Table 3.
The following is a brief description of each command
available in the 7242 FSA.
No Operation-Deselects the chip and prevents
further internal activity (default state for reset,
unselected or unaddressed channels). Resets the
FIFO and Bootloop pointers. The Enable pins
(ENABLE.A and ENABLE.B) become inactive.
Software Reset-Resets all FIFO and Bootloop
pointers and flags. Status flags, Error Correction
Enable bit, error correction shift register, and the
Enable pins become inactive.
Initia/ize-The chip is set to read data from the MBM
Boot/oop and pass it to the Controller. Resets the
FIFO and Bootloop pointers and the Error Correction
Logic, and disables the Bootloop register (so that it
does not interfere with the data flow). The Enable
pins become active in addressed channels.
6-206
AFN·01358B
7242
BUS
CONNOLr----------------------------.
INTERNAL DATA BUS A
INTERNAL DATA BUS B
BUS
CONTROL~--------------------------------~
•
Figure 3. Logic Diagram
6-207
AFN·01358B
inter
7242
Table 2. Command Code Description
Data
Code
Description
Correction
Enabled
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
No Operation
(Reserved)
Software Reset
Initialize
Write MBM Data
Read MBM Data
Internally Correct Data
Read Corrected Data
Write Bootloop Register
Read Bootloop Register
(Reserved)
(Reserved)
Set Enable Bit
Read ERR.FLG Status
Set Correction Enable Bit
Read Status Register
Not
Enabled
None
None
None
MBM Bootloop
Variable
Variable
-
None
MBM Bootloop
270 Bits In
270 Bits Out
None
270 Bits Out
160 Bits In
160 Bits Out
-
-
160 Bits In
160 Bits Out
-
-
None
1 Bit Out
None
8 Bits Out
None
1 Bit Out
None
8 Bits Out
Table 3. Command Function Summary
Command Description
Command
Code
No Operation
Software Reset
Initialize
Write MBM Data
Read MBM Data
Internally Correct Data
Read Corrected Data
Write Bootloop Register
Read Bootloop Register
Set Enable Bit
Read ERR.FLG Status
Set Error Correction
Enable Bit
Read Status Register
0000
0010
0011
0100
0101
0110
0111
1000
1001
1100
1101
1110
1111
Data Flow
(RlW)
Reset FIFO
& Bootloop
Pointers
-
X
X
X
X
X
-
R
W
R
R
W'
R
Reset
Status
(Errors)
Reset Error
Correction
Logic
X
X
X
X
X
X
X
-
-
X
X
X
X
-
-
H
H
L
L
L
L
L
H
H
L
R
H
-
X
R
X
Write MBM Data-Data input by the Controller is
written into the good loops in use in the MBM (under
control of the Bootloop register) each time a
SHIFT.ClK is received. It also activates the Enable
pins and resets the FIFO and Bootloop pointers. If
the Correction Enable bit is set, the FSA computes
the correction code and appends it to the data
stream to be stored in the MBM (last 14 of 270 bits).
Read MBM Data-This command activates the
ENABLE pins and resets the FIFO and Bootioop
pointers independent of the state of the Correction
Enable bit. If the Correction Enable bit is reset, data
from the MBM, of block length dictated by 2 times the
number of logic "1s" in the Bootloop register, is
sensed and screened by the FSA Sense Amp and
Bootloop register, and stored in the FIFO. As soon as
Enable
H
H
one bit is guaranteed in the FIFO, simultaneous
reading from the FIFO may be done by the Controller.
The FIFO need not be emptied after each page is
read, but one must insure that more than 272 bits of
FIFO are not needed at any time during the transfer.
If the Correction Enable is set, data must be read in a
buffered mode. First, a full block of data is read from
the MBM . At that point the FIFO contains 270 bits of
data. If an error is detected by the Error Correction
network, the FSA raises the UNCORR.ERR and
CORR.ERR flags which generate an interrupt to the
Controller. If no error is detected, the 270 bits of data
may be read from the FIFO while simultaneously
reading and checking the next block of data from the
MBM. When an error is detected the Gontroller may
respond to the interrupt in one of three ways.
6·208
AFN-01358B
7242
1. Ignore it and try again (must make sure to reset
the Error Correction shift register before a retry).
Read ERR.FLG Status-Reads the composite error
status for addressed channels of the FSA. (The composite status is the logic OR of CORRERR, UNCORRERR and TIMER.R. The ERR.FLG pin is the
logic NOR of both channels' composite error status:
ERR.FLG.A and ERRFLG.B.) ENABLE pins become
inactive.
2. Send a Read Corrected Data command to the
FSA. This command will correct the data stream
(if possible) and interrupt the Controller when the
block has been read. At this time the Controller
can send a Read Status command to see if the
error was correctable (CORR.ERR) or
uncorrectable (UNCORR.ERR).
Set Error Correction Enable Bit-Enables the Error
Correction Logic in addressed FSAs and disables it
in unaddressed FSAs. ENABLE pins become inactive and FIFO and Bootloop pointers are reset. Furthermore, when this enable is set, the corresponding
FIFO becomes a 270-bit FIFO (logically) instead of a
272-bit FIFO as in the no correction mode.
3. Send an internally Correct Data command to the
FSA. The FSA corrects the data without
transferring it to the Controller. When finished,
the FSA interrupts the Controller. At this point it
can be determined whether or not the error is
correctable. If so, a Read Corrected Data
command may be sent to read the good data.
Read Status Register-The 8-bit Status Word for the
addressed FSA is output to the Controller. Only one
FSA channel can be addressed at a time, or bus
contention may result. ENABLE pins become inactive and error flags in the addressed FSA channel are
reset.
Internally Correct Data-Internally cycles the data
through the error correction network and returns
status as to whether or not the data is correctable.
Requires approximately 1400 clock cycles to
complete. ERRFLG will be inactive during internal
cycling, but will return active at its completion. Also
activates the ENABLE pins and resets the FIFO and
Bootloop pointers.
Read Corrected Data-Cycles data through the
error correction network with each Controller read
(SELECT.IN at the FSA). At the end of 270 reads,
status is available to indicate whether .or not the data
was successfully corrected. ERRFLG acts as in
Internally Correct Data. This command is required to
read data corrected internally as well, but has no
effect on the data read if it was successfully
corrected. Activates the ENABLE pins and resets the
FIFO and Bootloop pointers.
SERIAL INTERFACE
Command Sequence-The FSA communicates
with the Controller via a Serial Interface. The Controller/FSA Interface contains the following signals:
1. CLK
2. SELECT.lN (Formatter)
3. SELECT.OUT (Formatter)
4. SYNC (Controller)
5.010
6.
cio
7. SHIFT.CLK
Write Bootloop Register-Contents of the FSA's
Bootloop register are written with 160 bits from the
Controller. The Controller must read the MBM
Bootloop first, to determine which loops are good.
The number of good bits in the 160-bit register is 135
if correction is used, and variable up to 160 if
operating in the no correction mode. ENABLE pins
become il1active and the FIFO and Bootloop pOinters
are reset.
8. ERRFLG
Commands from the Controller to the FSA shall take
place in the following format (see Figure 4).
1. Controller raises C/O flag indicating that a command is coming, and simultaneously outputs a
SYNC pulse. This SYNC pulse is shifted down the
FSA chain in shift register fashion via the FSA
SELECT.lN/SELECT.OUT lines.
Read Bootloop Register-As above except that data
is read from the FSA Bootloop to the Controller.
2. Controller outputs a serial data stream on the 010
line beginning in the clock period following
SYNC. Each bit in the stream corresponds to an
address bit for a particular FSA (up to 16 channels). Each FSA, upon receiving SELECT.lN will
look for the presence or absence of a logic one on
Set Enable Bit-ENABLE pins become active for
addressed channels, inactive for unaddressed
channels. Also resets the FIFO and Bootloop
pointers.
6-209
AFN.()1358B
7242
010 in the clock period following receipt of
SELECT.IN. (A logic one indicates that the FSA
shall accept the command.)
3. Twenty clock periods after the first SYNC the Controller sends
low followed by a four-bit command on the 010 line.
cm
4. If the command is a Read Status command (1111),
the addressed FSA returns 8 bits of Status starting 4 clock periods after the last command bit is
received. Note that the Status is returned during
this period for any FSA position. Therefore only
one FSA channel should be addressed at a time to
avoid contention.
5. If the command requires further data (see section
on FSA Commands), more SYNC pulses are sent
by the Controller. This will occur at integral multiples of 80 or 20 clock periods starting no sooner
than 40 clocks after the first command SYNC
pulse. Some number of SYNC periods may pass
before the second SYNC to allow the FSA to set
itself up and get data ready for the Controller.
There are several possibilities:
a. For the Read ERR.FLG Status command the
second SYNC can occur40 clocks after the first
SYNC. This SYNC (or SELECT. IN) causes each
addressed FSA to send the appropriate Status
Information. No further SYNCs (without C/O
high) should be sent.
b. For the Read MBM Data (or initialize) command the second SYNC must wait the appropriate number of SHIFT.CLOCKs to assure that
valid data is available in the FIFO.
After this wait, each addressed FSA channel
sends one bit of data on the 010 line for each
SYNC (or SELECT.IN) pulse.
c. For the Read Bootloop Register command, the
second SYNC can occur 60 clock cycles after
the first SYNC. The data transfer then proceeds as in b. above.
d. For the Write MBM Data or Write Bootloop
commands, the 010 line is used to transfer
data to the FSA on successive SYNC pulses.
The first data bit can be transferred by a
second SYNC pulse, 40 clock cycles after the
first SYNC. (However, data to the MBM will not
be available at the Oataout pins until 40 clock
cycles after the SYNC which transferred it.)
Each transfer to the addressed FSA will be
initiated by a SYNC (or SELECT.IN).
6. SYNC (SELECT.IN) precedes the data it transfers
by 1 clock cycle. Data Transfers to or from the
FSA's FIFO must contain the proper number of
SYNCs (externally counted) or a timing error may
occur (TIMERR flag will be set, causing an interrupt to the Controller).
_-----2. CLOCKS-----_.I.....------2. ClOCKS-----_.1
1'. . . .
ClK
C/id
I
I
I
SYNC
I I~------------------T_--+-----------------~--~-1J
I
,I
, - - -_ _ _ _.,.-_lsBs
I
DIO __L-~~JL~~JL~~~~~~_____LJLAJ~____+~~~~JL~~----
1~.-----ADDR,6EsBs,TwsoRD'----NOTE
l~o:~:DN~
4 BITS
I_~~TRUci' _I
8 BITS
STATUS INFO IS ONLY PRESENT ON BUS FOR THE READ STATUS COMMAND SEQUENCE
Figure 4. Command Sequences
6·210
AFN-OI3588
intel'
7242
Data Sequences-Bubble data shall be passed between the Controller and FSAs in the following
fashion (see Figure 5).
2. Uncorrectable Error
1. Controller outputs a SYNC pulse.
3. Timing Error
2. Each FSA then outputs (inputs) a single bit on 010
after SYNC (SELECT.IN) has been clocked into its
control section. Only previously enabled FSAs
output (input) data and the Controller must know
when to input (output) data bits.
The Status Word that shall be passed to the Controller after receipt of a Read Status command shall be in
the following format:
3. After 80 or 20 clocks, another SYNC pulse is output and the sequence repeats until all data has
been transferred.
1. Correctable Error
(UNCORRERR)
SPARE 1 ("0 '\
UNCORRECTABLE ERROR
SPARE 2 ("0")
CORRECTABLE ERROR
FIFO FULL IFIFOFL) - - - - - '
Error Conditions-Each FSA shall upon detection of
an error set a Status bit and pull down ERR.FLG. This
signal can be asynchronous to SYNC. Error Status
bits shall be:
(CORRERA)
(TIMERR)
FIFO EMPTY (FIFOMT)
TIMING ERROR
'-------
iE~6~ CORRECTION ENABLE
NOTE- EAROR FLAGS SHALL BE RESET UPON
BEING READ BY THE CONTROLLER OR BY A
SOFTWARE RESET OR INITIALIZE
1 - - - - - - - - - - - - - - 8 0 CLOCK C Y C L E S - - - - - - - - - - - - - _ I
CLK
SYNC U
r---------------------------------------~L~(------------~U~----
010
--,/'7"1~.A-"
lywl"-.AJo.II~I'_"_;X:I'_"
llwX,-I\..X..A..Jl
11....J1'-r-'--\-------~~f-------c;rrn
~l~--~--~~~--~j
~
DATA TO ST FSA
DATA TO 9TH FSA _ _ _ _- '
DATA TO 16TH FSA _ _ _ _ _---,_ _ _- - '
Figure 5. Data Sequences
6·211
AFN-013586
7242
BUBBLE INTERFACE
FSA ERRROR CORRECTION
Bubble Interface-Each Bubble Interface shall consist of a DATAOUT signal and a pair of differential
inputs from the MBM detector bridge.
Error Correction-The error correction logic consists of a burst error correcting File code capable of
correcting 5 or fewer bits in a single burst; the number of check bits is 14.* Error correction/detection
shall take place on each 256-bit data block. The FSA
shall set low ERR.FlG each time a correctable or
uncorrectable error is detected. ERR.FlG shall be
set high upon being read by the Controller or by a
software reset being issued. The polynomial implemented is given below:
'
Read Timing-The timing for reading a bit from the
memory shall be as follows:
1. Controller outputs a SHIFT.ClK. FSA samples
bubble signal during SHIFT.ClK and holds signal
after trailing edge.
G(X) = 1
2. Trailing edge of SHIFT.ClK initiates signal conversion timing.
+
X2 +
x5 + x9 + X11
+ X14
DATA FORMAT
3. Data is latched at end of conversion period in the
Bubble input latch, and will subsequently be
loaded into the FIFO.
Data Format-Data into a single FSA channel from
the bubble memory shall be in the format described '
below. The two channels of the bubble are represented identically. The following definitions apply:
Write Timing-The timing for writing a bit from the
FIFO shall be as follows:
1. Controller lowers SHIFT.ClK.
01/ = data from odd quads of bubble device, loop 1/
e1/ = data from even quads of bubble device, loop 1/
2. Data is gated out of FSA by SHIFT.elK.
Data Block Format3. Controller outputs a generate pulse (to external
logic, not to FSA).
01 8 1°1 8 1°2 82°2 8 2 ... °80 8 80°808 80
1st bit
4. Controller raises SHIFT.ClK. The DATA.OUT pin is
forced high.
When using correction, the first 270 good bits will be
used; the last 14 of these are to be used for the error
correcting code. The remaining 50 bits must be masked as "bad" bits in the FSA Bootloop register.
5. FIFO and Bootloop register are incremented after
the leading edge of SHIFT.ClK.
System Timing-The SYNC pulse (which denotes
the beginning of a data transfer from Controller to
Formatter or vice-versa) shall be synchronous- with
the beginning of a bubble memory field rotation. Due
to timing constraints in the FSA, the following
statements hold:
320th bit
When operating without correction, any number of
,bits may be used by loading the Bootloop register
appropriately. The preferred number is 272 bits,
however.
1. Data read from the bubble memory into the FSA
shall not be available to the Controller until 40
clock cycles after SHIFT.ClK.
2. Data cannot be written to the bubble memory
until 40 clock cycles after SYNC.
'See "Error-Correcting Codes" by W. W. Peterson and
E.J. Weldon, Jr., pp. 366-370, M.I.T. Press, 1972.
6-212
AFN-01358B
intJ
7242
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ABSOLUTE MAXIMUM RATINGS·
Temperature Under Bias ............ -40°C to +100°C
Storage Temperature ............... -65°C to +150°C
All Input or Output Voltages and
Vee Supply Voltage .................. -0.5V to +7V
Voo Supply Voltage .................. -0.5V to +14V
D.C. CHARACTERISTICS
(TA
= O°C to 70°C; Vee = 5,ov +5%, -10%;
Voo
=
12V ±5%)
Limits
Symbol
Unit
Parameter
Min.
Typ.
Test Conditions
Max.
VIL
Input Low Voltage
-0.5
0.8
V
VIH
Input High Voltage
2.0'
Vee +0.5
V
VOL
Output Low Voltage (All Outputs Except
SELECT.OUT)
.2
0.45
V
IOL
VOLSO
Output Low Voltage (SELECT.OUT)
.2
0.45
V
IOL
VOH
Output High Voltage (All Outputs Except
SELECT.OUT)
2.4
V
VOHSO
Output High Voltage (SELECT. OUT)
2.4
VTHR
Detector Threshold
2.3
2.7
mV
= 400/-LA
= 200/-LA
VOO = 12.0V
3.0
V
2.5
= 3.2mA
= 1.6mA
IOH
IOH
IIIL I
Input Leakage Current
0
5
/-LA
O';;VIN ';;Vee
IIOFL I
Output Float Leakage
0
10
/-LA
0.45 ,;;VOUT .;;Vee
lee
Power Supply Current from Vee
35
120
mA
100
Power Supply Current from Voo
5
30 )
mA
'Minimum VIH is 2.2V for the 7242-5 device.
6·213
AFN-01358B
7242
A.C. CHARACTERISTICS.
(TA = O°C to +70°C; vee
unless otherwise n(i)ted)
Symbol
= 5.0V +5%,
-10%; Voo
Min.
Max.
Unit
240
500
ns
.45tp
:55 tp
Parameter
tp
Clock Period
tf
Clock Phase Width
=
12V ±5%; Cl
tn tf
Clock Rise and Fail Time
tSle
SElECT.lN Setup Time to CLK
50
ns
teoe
C/O Setup Time to CLK
50
ns
teye
SELECT.IN or SRIFT.CLK Cycle Time
30
= 120 pF;
Test Conditions
ns
20 tp
toe
010 Setup Time to Clock (Read Mode)
50
ns
tese
CS Setup Time to CLK
100
ns
tRle
RESET.IN Setup Time to CLK
100
ns
10
tlH
Control Input Hold Time for C/O, SELECT.IN and 010
tesol
CLK to SELECT.OUT Leading Edge Delay
100
ns
Cl - 50 pF
tesoT
CLK to SELECT.OUT Trailing Edge Delay
80
ns
Cl - 50 pF
teov
CLK to 010 Valid Delay*
100
ns
ns
teoH
CLK to 010 Hold Time*
teDE
CLK to 010 Enabled from Float*
100
ns
tSIDE
SELECT.IN Trailing Edge to 010 Enabled from Float*
70
ns
teoF
CLK to 010 Entering Float*
100
ns
tseoo
SHIFT.CLK to DATAOUT Delay*
200
ns
tsewR
SHIFT.CLK WiC;Hh (Read)
4tp
tseww
SHIFT.CLK Width (Write)
tp
CAPACITANCE
(TA
Symbol
0
ns
teye
teye
11 tp
2 tp
= 25°C, Vee = OV, f = 1 MHz)
Max.
Unit
CIN
Input Capacitance
Parameter
Min.
10
pF
COUT
Output Capacitance
10
pF
COlO
010 Capacitance
10
pF
Test Conditions
*010 Write Mode
A.C. TESTING INPUT, OUTPUT WAVEFORM
INPUTIOUTPUT
2.
0.5
=x:: >
TEST POINTS
:x=
<:
A C TESTING INPUTS ARE DRIVEN AT 2 4V FOR A LOGIC 1 AND a 45\1 FOR
A LOGIC 0 TIMING MEASUREMENTS ARE MADE AT 2 OV FOR A LOGIC 1
AND 0 8V FOR A LOGIC 0
6-214
AFN-01358B
7242
WAVEFORMS
DIO INTERFACE TIMING
BUBBLE DATA INTERFACE TIMING
~--------------------t~c--~------------------~
'SCWR.
tscww
SHIFT.eLK
DATA.OUT.A
DATA.OUT.B
---+-""'
tSCDO
(WRITE)
6-215
AFN·01358B
7250
COIL PRE-DRIVE
FOR BUBBLE MEMORIES
7250
7250-5
• Very Low Power
• Only One Power Supply Required, +12V
• Power Fail Reset for Maximum
Protection of Bubble Memory
• TTL Compatible Inputs
• CMOS Technology
• Standard 16-Pin Dual In-Line Package
The Intel 7250 is a low power Coil Pre-Driver (CPO) for use with Intel Magnetics Bubble Memories. The 7250 is
controlled by the Intel 7220-1 Bubble Memory Controller (BMC) and directly drives Quad VMOS transistor
packs, which are connected to the coils of the bubble memory.
The 7250 is a high-voltage, high-current driver constructed using CMOS technology. The device has TTL
compatible inputs and the outputs are designed to drive either low on-resistance VMOS transistors or bipolar
transistors.
The 7250 is in a standard 16-pin dual in-line package.
~----------------,
I
,I
I
I
I
I
I
I
I
.........."
TO
8085
I
7220·1
BuaBLE
MEMORY
CONTROLLER
(SMe)
I
I
I
I,
I
I
I
Y-.OUT
GND
Y+.OUT
--..----'-.-
L _______ _
TO
ADDITIONAL
BPK70's
Figure 1. Block Diagram of Single Bubble
Memory System-128K Bytes
Figure 2. Pin Configuration
Intel Corporation Assumes No Responsibilty for the Use of Any CircUitry Other Than Circuitry Embodied In an Intel Product. No Other Circuit Patent Licenses are Implied.
©
INTEL CORPORATION, 1982
6.216
OCTOBER 1982
ORDER NUMBER: 2'0800-00'
7250
Table 1. Pin Description
Symbol
Pin No.
Description
CS
1
Chip select. It is active low. When high chip is deselected and 100
is significantly reduced.
RESET
2
Active low input from RESET.OUTof 7220-1 Controller forces
7250 outputs inactive so that bubble memory is protected in the
event of power supply failure.
3,4
Active low inputs from Controller which turn on the high-current
X outputs.
12,13,14,15
High-current outputs and their complements for driving the
gates of the 7254 VMOS quad transistors which in turn drive the
X coils of the bubble memory.
5,6
Active low inputs from Controller which turn on the high-current
Voutputs.
7,9,10,11
High-current outputs and their complements for driving the
gates of the 7254 VMOS quad transistors which in turn drive the
V coils of the bubble memory.
X+ IN,
.x- .IN
X-.OUT
X-.OUT
X+.OUT
X+.OUT
V+.IN, V-.IN
V-OUT
V-.OUT
V+.OUT
V+.OUT
Figure 3. Logic Diagram
6-217
AFN·013598
7250
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent·damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
ABSOLUTE MAXIMUM RATINGS·
Ambient Temperature Under Bias ... -40°C to +100°C
Storage Temperature ............... -65°C to +150"C
Voltage on Any Pin with
Respect to Ground ............. ....:0.5 to Voo +0.5V
Supply Voltage. Vpp ................... -0.5 to +14V
Output Current .............................. 250 mA
(One Output @ 100% Duty Cycle)
D.C. CHARACTERISTICS
(TA =see range specified on first page
Voo = 12V +5%. -10%; unless otherwise specified)
Symbol
Limits
Parameter
Min.
IIINI
Input Current
VIL
Low-Level Input Voltage
Typ.
Test Conditions
Max.
Unit
5
/LA
0.8
V
2.2
VI = 0.8V
VIH
High-Level Input Voltage
VOL1
Output Low Voltage
2.0
V
V
VOL2
Output Low Voltage
0.2
V
IOL = 10 mA
VOH1
Output High Voltage
Voo-2
V
IOH = -100 mA
VOH2
Output High Voltage
Voo-0.2
V
IOL
Output Sink Current
100
mA
IIOHI
Output Source Current
100
mA
VOH = Voo-2.0V
1000
Supply Current
4.5
mA
Chip Deselected: CS = VIH.
Voo = 12.6V
1001
Supply Current
75
mA
f = 100 kHz, Voo = 12.6V,
Outputs Unloaded
6-218
IOL = 100 mA
IOH = -10 mA
VOL = 2.0V
AFN-01359B
7250
A.C. CHARACTERISTICS
(T A = see range specified on first page
Voo
Symbol
=
12V ±5%, unless othlilrwise specified)
Parameter
Min.
Typ.
Test Con~ltlons
Max.
Unit
tp1
Propagation Delay from X+ .IN,
l<-1N, Y+.lN, V-.IN
100
ns
500 pF Load
tp2
~rOpagation Delay from
ESET
150
ns
500 pF Load
tr
Rise Time (10% to 90%)
45
ns
500 pF Load
tF
Fail Time (90% to 10%)
45
ns
500 pF Load
ts
Skew Between an Output and
Its Complements
20
ns
CS or
A.C. TEST CONDITIONS
\-----------1---------- ~~-:.::
~:
~I ~-------~----ov
1t=~-
OUTPUT
CAPACITANCE*
Symbol
C IN
(TA
= 25°C, Voo = OV, VBIAS = 2V, f = 1 MHz)
Parameter
Min.
Typ.
Input Capacitance
Max.
110
I
Unit
Test Conditions
pF
'Thls psrameler is periodically sampled and Is noI100% lesled.
6·219
AFN.o1359B
7254
QUAD VMOS DRIVE TRANSISTORS
FOR BUBBLE MEMORIES
• Designed to Drive X and Y Coils of 7110
Bubble Memories
• Operates from" DO Only
• No Bias Currents Required
• VMOS FET Technology
• Fast Turn~On and Turn-Off: 30 ns
Maximum
• N-Channel and P-Channel Transistors
in the Same P~ckage
• Built-In Diode Com mutates Coil Current
When Transistor is Turned Off
• Standard 14-Pin Dual-In-Line Package
The 7254 is a quad transistor pack designed to drive the X and Y coils of Intel Magnetics Bubble Memories. Two
7254 packages are required for each bubble memory device. Each 7254 package would drive either the X or Y
coil as shown under "circuit diagram." This recommended connection circuit takes into account the fact the
01/02 and 03/04 are tested as a pair for "On" resistance value to assure optimal bubble performance.
~----------------,
I
'
I
I
I
I
I
I
I
TO
8080
8085
8088
8088
I
I
I
I
7220-1
BUBBLE _
MEMORY
CONTROLLER
(BMC)
I
I
I
7110
ONE MEGABIT
BUBBLE
MEMORY
UNIT
(MBM)
7242
FORMATIERI
SENSE
AMP
(FSA)
I
I
I
I
L ______ _
TO
ADDITIONAL
BPK70's
Figure 1. Block Diagram of Single Bubble
Memory System-128K Bytes
Figure 2. Pin Configuration '
Intel Corpora1ion Assume. No Reaponalbllty for the Use of Any Circuitry Other Than Circuitry Embodied 111 an Intel Product No Other Circuit Patent Licensea lIN Implied
© INTEL CORPORATION. 1982
6.220
OCTOBER 1982
ORDER NUMBER: 210801_
7254
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ... -40°C to +100°C
Storage Temperature ............... -65°C to +150°C
Gate Voltage (with respect to
Source and Drain ............................. 15V
Continuous Drain Current ........................ 2A
Peak Drain Current .............................. 3A
Power Dissipation (T A = BO° C) ................ 1.05W
Power Dissipation (T A = 25°C) ................ 1.75W
D.C_ CHARACTERISTICS
Symbol
·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions' for extended periods may affect
device reliability.
All Limits Apply for N- and P-Channel transistors, T A = -30° to 85°C unless
otherwide noted.
Limits
Parameter
Min.
BVOSS
Drain-Source Breakdown Voltage
VGS(th)
Gate-Source Threshold Voltage
Typ.
Max.
Unit
Test Conditions
20
V
VGS = 0,10 = lOJLA
0.8
V
VGS = VOS, 10 = 1 rnA,
TA = 25°C
0.65
V
VGS = VOS, 10 = 1 rnA,
TA = 85°C
IGSS
Gate Leakage Current
100
nA
VGS = 12V, VOS = 0,
TA = 25°C
loSS
Drain Leakage Current
500
nA
VGS = 0, VOS = 20V,
TA = 25.o C
RoS
On-Resistance for sum of
01+02,03+04 (Note 1)
3.0
n
VGS= 11.4V,10= lA,
TA = 25'C
VF1
Parasitic Diode Forward Voltage
(Note 1)
.75
V
VGS = OV, 10 = 50 rnA,
TA = 25'C
VF2
Parasitic Diode Forward Voltage
(Note 1)
1.20
V
VGS = OV, 10 = 1000 rnA,
TA = 25'C
Test Conditions
20
2.5
NOTE:
1 Pulse test-SO!,-s pulse, 1% duty cycle, rDS Increase O.so/JC.
A_C. CHARACTERISTICS T A =
25°C
Max.
Unit
N-Channel Turn-On Time
20
ns
tON(P)
P-Channel Turn-On Time
30
rlS
tOFF(N)
N-Channel Turn-Off Time
20
ns
tOFF(P)
P-Channel Turn-Off Time
30
ns
Symbol
TON(N)
Parameter
Min.
Typ.
+17V
INPUT
OUTPUT
Figure 3. Switching Time Test Circuit
Figure 4. Switching Time Test Waveforms
6-221
AFN-01360B
.....
.,...
....
CAMCITANCI TA = HOC
,.
CllleN)
N·Channellnput Capacitance
Cllsep)
P·Channe' Input Capacitance
Typ.
....
Unit
Teat Condltlona
175
pF
VGS = O. VOS = '12'1,
f= 1 MHz
190
pF
VGS = O. VOS = 12'1,
f = 1 MHz
.,2V
,
1M
QI
1
2
3
D,
•
14
'.-J=: I I c~~: "
o.--f
r-
0,-1
r-
G•
tz
G,
::~:: ~
7
D.
D.
~~
. :;i"s, "
t
•
•
Q2
Q3
0,
I
G,
-:-
7
•
-• t
S
4
, ,
-
U
1*
10
- -"
.,
~
14
-
0.711 ,11••
0.140'''.•
F9
0.012(0.311
~ UtO
0.320 11.131~• 0.001 (0.201
(7.371
TYP.
0.1101".1
0.12513.111
DIMENIIONS IN INCHIS AND (MILLIMETERSI
' ....... ,.......lnfor....11on
8-222
AFN-Gl36OB
7114
4-MEGABIT BUBBLE MEMORY
100 KHz
7114 A-1
50 KHz
7114-1
CASE
OPERATING
TEMP. eC)
0->75
7114 A-4
7114-4
10->55
OPERATING FREQUENCY
• 4,194,304 Bits of Usable Data Storage
• Non-Volatile, Solid-State Memory
• True Binary Organization: 512-Bit Page
and 8,192 Pages
• Major Track-Minor Loop Architecture
• Redundant Loops with On-Chip Loop
Map and Index
NON-VOLATILE
STORAGEeC)
-20->+75
-40->+90
• Single-Chip 20-Pin Dual In-Line
Package
• Small Physical Volume
• Maximum Data Rate 400 Kbit/Sec
(7114A)
• Average Access Time 40 msec (7114A)
• Block Replicate for Read; Block Swap
for Write
The Intel Magnetics 7114 (unless otherwise indicated 7114 refers also to 7114A) is a very high-density
4-megabit non-volatile, solid-state memory utilizing magnetic bubble technology. The usable data storage
capacity is 4,194,304 bits. The defect-tolerant design incorporates redundant storage loops. The gross capacity
of Intel Magnetics bubble memory is 5,242,880 bits.
The 7114 has a true binary organization to simplify system design, interfacing, and system software. The device
is organized as 512 data storage loops each having 8,192 storage bits. When used with Intel Magnetics
complete family of support electronics, the resultant minimum system is configured as 512K bytes of usable
data storage. The support circuits also provide automatic error correction and transparent handling of redundant loops.
.
The 7114 has a major track-minor loop architecture. It has separate read and write tracks. Logically, the data is
organized as a 512-bit page with a total of 8,192 pages. The redundant loop information is stored on-chip in the
boot loop along with an index address code. The 7114 provides totally non-volatile data storage when operated
within the stated limits.
1----------------1
I
" .
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
REPLICATE B
OETOUT A+
I
I
REPLICATE A
DET OUT A-
I
I
BOOT REP
B~B6
DET SUPPLY 1+12V)
PULSE COM 1+12VI
I
BOOT SWAP
I
I
NC
I
GENERATE B
I
X+COILIN
I
DETOUTB+
7114
INTEL MAGNE11CS
BUaBLE MEMORY
DETOUT
s-
DETCOM
SWAPB
SWAP A
Y·COIL IN
I
I
ADOITIOti ...t
8PK14S
Figure 1. Block Diagram of Single Bubble
Memory System-512K Bytes
Figure 2. Pin Configuration
Intel Corporation Assumes No Responslbllty for the Use of Any Circuitry Other Than CIrcuitry Embodied
@INTELCORPORATION, 1982
~,
6·223
In
an Intel Product No Other Circuit Patent Licenses 8Y8lmplied.
NOVEMBER 1982
ORDER NUMBER: 210713-001
7114
,
Symbol
Table 1. 7114 Pin Description
Name and Function
Pln#
BOOT.REP
4
Two-level current pulse input for reading' the boot loop.
BOOT.SWAP
5
Single-level current pulse for writing data into the boot loop. This pin is
normally used only in the manufacture of the MBM.
DET.COM
15
Ground return for the detector bridge.
DET.OUT
16-19
Differential pair (A+, A- and B+, B-) outputs which have signals of
several millivolts peak amplitude.
DET.SUPPLY
20
+12 volt supply pin.
GEN.A and GEN.B
7,8
Two-level current pulses for writing data onto the input track.
PULSE.COM
REP.A and REP.B
SWAP.A and SWAP.B
1
3,2
+ 12 volt supply pin.
Two-level current pulses for replicating data from storage loops to
output track.
13, 14
Single-level current pulse for swapping data from input track to
storage loops.
X-.COILlN, X+.COILIN
9, 10
Terminals for the X or inner coil.
Y- .COILlN, Y+ .COILIN
11, 12
Terminals for the Yor outer coil.
The 7114 is packaged in a dual in-line leaded package complete with permanent l)1agnets and coils for
the in-plane rotating field. In addition, the 7114 has a
magnetic shield surrounding the bubble memory
chip to protect the data from external magnetic
fields.
The operating data rate is 400 Kbit/sec for 7114A, and
200 Kbit/sec for 7114. The 7114 can be operated
asynchronously and has start/stop capability.
GENERAL FUNCTION DESCRIPTION
The Intel Magnetics 7114 is a 4-megabit bubble
memory module organized as two identical 2,048K
binary half sections. See Major Track-Minor Loop
architecture diagram. Each half section is in turn
organized as four 512K subsections referred to as
octants.
The module consists of a bubble die mounted in a
substrat~ that accommodates two orthogonal drive
coils that surround the die. The drive coils produce a
rotating magnetic field in the plane of the die when
they are excited by 90" phase-shifted triangular current waveforms. The rotating in-plane field is responsible for bubble propagation. One drive field rotation
propagates all bubbles in the device one storage
location (or cycle). The die-substrate-cpil subassembly is enclosed in a package consisting of permanent magnets and a shield. The shield serves as a
flux return path for the permanent magnets in addition to isolating the device from stray magnetic
fields. The permanent magnets produce a bias field
that is nearly perpendicular to the plane of the die.
This field supports the existence of the bubble
domains.
The package is constructed to maintain 1.5 degree
tilt between the plane of the bias magnet faces and
the plane of the die. This serves to introduce a small
component of the bias field into the plane of the die.
During operation when the drive coils are energized
this small in-plane component is negligible. During
standby or when power is removed the small in-plane
field ensures that the· bubbles will be confined to
their appropriate storage locations. The direction of
the in-plane field introduced by the package tilt
(holding field) is coincident with the 0" phase direction of the drive field.
Architecture
A 7114 octant subsection is composed of the follow,ng elements shown on the architecture diagram.
,
STORAGE LOOPS
Each octant subsection contains eighty identical
8,192-bit storage loops to provide a total max·
imum capacity of 655,360 bits. The excess storage
is provided for two purposes: a) it allows a redundancy scheme to increase device yield; and b) it
provides the extra storage required to implement
error correction.
REPLICATING GENERATOR (GEN)
The generator operates by replicating a seed bubble
that is always present at the generator site (GEN).
6·224
AFN-01439A
7114
INPUT TRACK AND SWAP GATE
Bubbles following generation are propagated down
an input track. Bubbles are transferred to/from the
input track from/to the 80 storage loops via seriesconnected swap gates spaced every two propagation cycles along the track. The swap gate's ability to
transfer bubbles in both directions during an operation eliminates the overhead associated with removing old data from the loops before new data can be
written. The swap gate is designed to function such
that the. logical storage loop position occupied
by the bubble transferred out of each loop is filled
by the bubble being transferred into each loop.
Transferred-out bubbles propagate down the
remaining portion of the input track where they are
dumped into a bubble bucket guard rail.
tion is propagated to a bubble bucket guard rail. A
"dummy" detector stack sits in the immediate
vicinity. It is connected in series with the active detector and serves to cancel common mode pickup
which originates predominately from the in-plane
drive field.
OUTPUT TRACK AND REPLICATE GATE
Bubbles are read out of the storage loops in a nondestructive fashion via a set of replicate gates. The
bubble is split in two. The leading bubble is retained
in the storage loop and the trailing bubble is transferred onto the output track. Replicate gates are
spaced every two propagation cycles along the output track.
b) A synchronization code that assigns data addresses (pages) to the data in the storage loops.
Since bubbles move from one storage location to
the next every field rotation, the actual physical
location of a page of data is determined by the
number .of field rotations that have elapsed with
respect to a reference.
DETECTOR
Bubbles, following replication, are propagated along
the output track to a detector that operates on the
magneto-resistance principle. The cylindrical bubble domains are stretched into long strip domains by
a chevron expander and are then propagated to the
active portion of the detector. The detector consists
of a thin film, lying underneath a stack of chevrons,
through which a current is passed. As the strip
domain propagates below the thin-film detector, its
magnetic flux causes a fractional change in film
resistance which produces an output signal of
several millivolts. The strip domain following detec-
BOOT LOOp, BOOT SWAp, AND
BOOT REPLICATE
One of the four octants in each half chip contains a
functionally active Boot Storage Loop. This loop is
used to store:
a) A loop mask code that defines which loops within
the main storage area should be accessed. Faulty
loops are "masked out" by the support
electronics.
The boot loop is read from and written into via the
same input and output tracks as the main storage
loops. However, it has independently accessed swap
and replicate gates. The boot swap, under normal,
circumstances, is intended only to be used during
basic initialization at the factory at which time loop
mask and synchronization codes are written. The
boot replicate is intended to be accessed every time
power is applied to the bubble module and its peripheral control electronics. At such a time, the control
electronics would read and store the mask information, plus utilize the synchronization information to
establish the location of the data circulating within
the loops.
6-225
AFN-01439A
7114
IDENTIFICATION lABEL.
~
___________________
1
---------------------~
I'
'I
135
J_n_________
~
i,
U'375~
J / ~ . -..
~==-----L
1500~L
f
-l
SEATING PLANE
(20x) 015
PACKAGE OUTLINE
MAJOR TRACK-MINOR LOOP ARCHITECTURE
OF 7114 (ONE HALF SHOWN).
Figure 3. Package Outline and Device Architecture
6-226
7114
ABSOLUTE MAXIMUM RATINGS*
Operating Case Temperature ........ O°C to 75°C Case
Relative Humidity ............................... 95%
Shelf Storage Temperature (Data
Integrity Not Guaranteed) ......... -65°C to +1500C
Voltage Applied to DET.SUPPLY .............. 14 Volts
Voltage Applied to PULSE.COM ............ 12.6 Volts
Continuous Current between DET.COM and
Detector Outputs ........................... 10 mA
Coil Current ................... 2.5A D.C. or A.C. RMS
External Magnetic Field for
Non-Volatile Storage ................... 20 Oersteds
Non-Operating Handling Shock ................. 200G
Operating Vibration (2 Hz to 2 KHz) .............. 20G
'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. ThIS is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
D.C. AND OPERATING CHARACTERISTICS (TC = Range Specified on First Page)
Limits
Min.
Nom.[l)
Max.
Unit
RESISTANCE: PULSE.COM to GEN.A or GEN.B
12
30
58
ohms
RESISTANCE: PULSE.COM to REP.A or REP.B
Parameter
13
27
35
ohms
RESISTANCE: PULSE.COM to SWAP. A or SWAP.B
20
47
71
ohms
RESISTANCE: PULSE.COM to BOOTREP
3.5
8
23
ohms
RESISTANCE: PULSE.COM to BOOTSWAP
5
20
49
ohms
RESISTANCE: DETOUT A+ to DET.OUT A-
770
1190
2200
ohms
RESISTANCE: DET.OUT B+ to DETOUT B-
770
1190
2200
ohms
RESISTANCE: DET.COM to DET.SUPPLY
560
950
2100
ohms
NOTE:
1 Nominal values are measured at 25'C.
6-227
AFN-01439A
7114
DRIVE REQUIREMENTS (Tc = Range specified on First Page) (See note 2) Vdd =12V ±5%
Symbol
Min.
7114
Nom.[ll Max.
Min.
49.95
50.00
99.90
Parameter
50.05
fR
Field Rotation Frequency
Ipx
X.Coil Peak Current
Ipy
Y.Coil Peak Current
81x
'X. Coil Positive Turn-On Phase
82x
X.Coil Positive Turn-Off Phase
16
18
20
16
S3x
X.Coil Negative Turn-On Phase
88
196
90
198
92
88
200
0
0
110
270
84x
X.Coil Negative Turn-Off Phase
81y
Y.Coil Positive Turn-On Phase
82y
Y.Coil Positive Turn-Off Phase
0
106
83y
Y.Coil Negative Turn-On Phase
178
108
180
84y
Y.Coil Negative Turn-Off Phase
286
288
PT
Total Coil Power
100.00
Units
100.10
KHz
1.6
.58
.74
268
7114A
Nom.[1] Max.
A
2.1
272
268
A
270
272
Degrees
18
20
Degrees
92
Degrees
196
90
198
200
Degrees
0
0
0
Degrees
108
110
Degrees
182
106
178
180
182
Degrees
290
286
288
290
Degrees
2.9
Watts
-Ax
X.Coil D.C. Resistance
1.5
7.4
1.0
Ohms
Ry
Y.Coil D.C. Resistance
3.3
0.4
Ohms
Lx
X.Coil Inductance
89
15
p.H
Ly
Y.Coillnductance
78
14
p.H
NOTES:
1. Nominal values are measured atTe = 25°C.
2. See Figure 4 for test set-up and X-V COIl waveform.
CONTROL PULSE REQUIREMENTS (see Notes 2 and 3) (TC = Range Specified on First Page)
Current (mA)
Pulse
GEN. A, GEN.B CUT
Phase of Leading Edge
(Degrees)
Nom.[ll Max.
Min.
Width
(Degrees)
Min. Nom.[ll Max.
Min.
Nom.
Max.
39
44
50
275
95
279 (late)
99 (early)
283
103
6
9
279 (late)
99 (early)
283
103
13.5
25
29
33
275
95
86
90
94
REP.A, REP.B CUT
130
148
165
284
288
292
6
9
13.5
REP.A, REP.B TRANSFER
100
115
288
140
152
130
165
284
SWAP
176
180
292
184
86
513
90
517
521
BOOT.REP CUT
33
292
6
9
13.5
33
284
'284
288
25
38
29
42
BOOT.REP TRANSFER
288
292
86
90
94
BQOTSWAP
35
39
44
176
180
184
GEN.A, GEN.B TRANSFER
See Not~
94
4
NOTES:
1. Nominal values are at T e = 25°C,
2. Pulse timing is given in terms of the phase relations as shown below. For example, a 7114 operating at tf:! = 50.000 KHz would have
a REP. A transfer width of goo whIch is 5l'sec.
3. l'No level pulses are described as shown below in Figure 5.
4. BOOT.SWAP is not nQrmally accessed during operatIon. It is utilized at the factory to write the index address and redundant loop
information into the bootstrap loo~s before shipment.
6·228
AFN·01439A
intel"
7114
7114
Iv
Y + __+-----<~r:+--=
• X-
I,
=~7---""'"
x+
y- •
CURRENT
CURRENT
PROBE
PROBE
(Elty
~O")
Figure 4. X-V Coil Waveforms and Test Set-Up
PHASE
(LEADING EDGE)
1 - TRANSFER WIDTH ---lI
-1
Figure 5. Two-Level Current Pulse
12 VOLT
Figure 7. Detector Output Waveforms
20 _._--:::
i
O.l/Lfd
15 Mf
16
i ttl ~-j-+---l
OUTPUT CHARACTERISTICS (T c = Range
Specified on Front Page)
HIGH·IMPEDANCE
S.l!!
Nom.
Units
Test
Conditions
S,
18
mV
See notes
So
1
mV
1,2
Symbol
15
~~~~:~~;6'~ESHOLD
NOTES:
Figure 6. Test Set-Up for Output
Voltage Measurement
1 Nommal values are measured at Te ~ 25°C
2 See Figure 6 for test set·up, and Figure 7 for detector output
waveforms and timmg
6·229
AFN-01439A
Packal'.
Information
7
PACKAGING INFORMATION
All dimensions
In
inches and (millimeters)
NOTES:
1. All packages drawings not to scale.
2. Type P packages only. Package length does not include end flash burr. Burr is .005 nominal, can be .010 max. at one end.
3. All package drawings end view dimensions are to outside of leads.
PLASTIC DUAL IN-LINE PACKAGE TYPE P
835121.209)
r---i25i2O:95s')~
l6-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
,_ _ _ _ ___
PIN " _ _
t
o
25516.477)
24516.223i
I
~~~~---.i
f-I~:;::;:;::;:=-==-=
I
,-I
L,r:jII~
JI032TVP
(0813) .
If
10381)
I
II
-
,-,~-,
~---.t
. ---
.032 TVP
11.524)
1•. 8131
C
~
II
060 TYP
1 036 tZti.289J
1.025 (26.035)
b
I
-II-
t-
22-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
[
MAX
--j
-Ftl
I
18255)
14013556)
130 (3.302) 010 TYP
1
I
10254)
.:
I
l
""016 (0 406)
I
.J
400
MAX
00
15°
REF
-::1
'-'3PIN~_1
255 (6.467)
245 16.223i
~~_
~
i
~ U," m".
II
(0381)
-II- .20 10508)
~ (2.794)
,060 TYP
032 TVP
090 12286)
11.524)
10.813)
1 105 (28 067)
1095 (27813)
1_ _ _ _
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130
___
-F=1
[-
- ' , 4 0 (3556)
_..t
(3302).,.TYP
,-_.
If I I
L=-.!
325
•
I--- 075 W!QID
,-'
r----
325
060 (!,§W
(1 016)
ii40
.,5MIN
10381)
02010508)
20~~:80)kw' _ _ ·~
MIN
(10160)
NQTE4
(10160)
NOTE 4.
900 (22 403) REF _ .
I
.-I
~~ -j
\.-
---.i
'"l
,-I
125 (3175)
I
~~~:~:::
00
15°
I REF
I
, -,
.90 12286)
PLANE
I
.:
245 (6223)
~ (2794)
~---l'---'
I
10254)
-_'~PIN~ ~55IL671
I L:j
20-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
-FEi-,1
895122733)~
20~~x080)~800~20 320),REF
MIN
130 (3302) 010TVP
905 (22 987)
b
T,m.C'--;---'
[-'~~:511
.14013556) ,
~ 015MIN
OOOTYP
{15241
C
la-LEAD PLASTIC DUAL IN-LINE
PACKAGE TYPE P
-,
,r"v'v-J
I
110 (2794)
000 (2286)
325
~ ~~ l~ :;~
700 (17780) REF - -
MAX ' ]
,,~
,
(.254)
-:
I
l
016 (0406)
J
400
MAX
00
--;;
I
~~F
,
(10.160)
NOTE 4
~
~N-.!I
__
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.355 (9017)
.345 (&"363)
"""'~~~I·.
l:g ~
[I£l)]
~
- , .15513.937)
----.t
II
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.145 (3.683)
.015 MIN.
(0.381)
-II- .020 (0.508)
(1524)
7-1
032 TYP
(0.813)
:016(0406)
I
.~~.~T4~P
--i 10~O
!
I
I
I
~ (1~~~) -I
500
NOTE 4
REF
PACKAGING INFORMATION
c:
All dimensions In Inches and (millimeters)
PLASTIC DUAL IN-LINE PACKAGE TYPE P
24-LEAD PLASTIC DUAL IN·LlNE
PACKAGE TYPE P
_
[
~ ,3' 6231---+j
1235(31369). _
!iN-.!!
PIN;-t
5451138431
535,'35891
-- -
-.-~"'
MAX
-
-7.'if.i~-t--
L
j
~: :~ ~:::
21I-LEAD PLASTIC DUAL IN·LINE
PACKAGE TYPE P
i
:,:,~;.~P
C
PLANE
-
.
~~8i~t
--r
150
j3"iiijj
0'5 MIN.
,0.3811
-.1-020'05081
0'6 ,04061
II
L
I
r-I.
.~ :~:::
[
,
,02541
..:
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L
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0°
150
REF
(17 780)
NOTE 4
-_-JPIN~-l
~(b.843J
-
535,'36651
'~~X0801 I '300~33.0~)~REF2. m
~m-:: _ =
=r
-----r
'25,3'75)
MIN
010 TVP
-+I
_'455(36957)~
1 445 136 703)
[
SEATING
4O-LEAD PLASTIC DUAL IN·LlNE
PACKAGE TYPE P
I
[
4
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-
Ms.:~
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150
(3.8'0)
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II
c·
625
MAX
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O'OTVP-RfY'
(0.254)
,03811
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-.:
,
L MAX
Oii,iiMii)
i
700
150
REF
___
(17780)
NOTE 4
2.066 ,62 '97)
2ii4s(51943) - - - - ,
_ !_!N~I '
-I
i'='-'='-~---
546,'3943)
635113.589)
~~...pi.---1
1900(48260)REF -
200(5080)
MAX
==r
.r;t;:::;:;:~
-
.11
O6OTVP
032'TVP
" 524)
'0.8'3)
.625
1 - 085(2159)
065 (1 651)
--r
175 (4445)
'""i55 (3937\ 0'0 TVP
0'6 MIN
,03811
j..-~(O.508)
.0'810408)
,0.254)
J--"~~~5)J
-F1
I
~
'L
..:
700
MAX
(17780)
NOTE 4
7·2
j
fY'
15'
I REF
PACKAGING INFORMATION
CERAMIC DUAL IN·L1NE PACKAGE TYPE D
16-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
c=
All dimensions in inches and (millimeters)
790(2o.066)~
150(190501
PIN 1
18-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
t ~j
(8.128)
200(5.080)
MAX.
.800
REF.
(20.320)
-t-,R;:;;;;;i=Fi;:;;
,
SEATING
PLANE
-E :
(7.820)
'::;0101~L:L==r 165(4191)
::I
140(35561
OlOryp
(0 254),
,
125 (3175)
MIN
110 (2194)
090(2286)
400
I.-
032 TVP
(0813)
~, ..!!:..
-........:
"
•
10'
REF.
-I
MAX
(10180)
NOTE 4
2D-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
200(50801
MAl(.
.126 (3175J
MIN
110 (27941
032 TV"
(0813)
090 122a6i
c=
22-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
~
'096~~
1 060 (26 924)
PIN 1
-----
400 (10 161
370 (9398)
;.~-~
(lIS 400)
200(6....1
MAX
l
~~~~-1
I
-
(10888)
MAX
.~~~~L:L=:J
SEATING
PLANE
.::]
--r
L
MIN.
032 TV"
(o.S13)
7-3
180(4672)
:.150(3.8101
015 MIN.
(0.381)
126 (3175)
t~J
(1iifeo)
,
.080(1524)
.~:i
.010TYP.
(0.264)
~/ ..!!:..
~
10"
I ,
•
I.-
500
•
MAX
-I
(12700)
NOTE 4
REF
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
CERAMIC DUAL IN·LlNE PACKAGE TYPE D
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
C
,.285 (32'G391-=:]
1.235 (31.369)
PIN 1
---
-1
600 (15 240)
515 (13 081)
-.l
~~~oPiL
(15.748)
C
~
.090 (2.286)
MAX.
.
.600 ~
(15.240)
,
~:: II
'i'i'!il::::r=J .175(4.445)
-='.=H"'R"
l020MI~4O(3.:)
-
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(.508)
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700
-.,
l.-
MAX
(17780)
016 {0.406}
(0813)
f 1~
TVP.-l
{0.254},
.
REF.
--I
NOTE 4.
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
o
.090 (2.2SB)
Jo
MiX'
1.100 REF.
(27.940)
•200 (5.08)
MAX.
.010 [(15 48)
MAX
600
{0.2.4}
(15.240)
__
.185(4.699)
~
,J!:...
•
...:
10'
.140(3.556)
SEATING
PLANE
--.:
125/3.175)
--II-
~(2'794)-.I
MIN
.032 TYP,
090 (2286)
L.020 MIN.
(.508)
020
J
.010TYP,f=
{0.264}
L J
,
{0.508}
REF.
700
.016 (0.406)
MAX
(17780)
{0.813}
NOTE 4
1 485 (37719)
28-LEAD HERMETIC DUAL IN-LINE
. PACKAGE TYPE D
- - - 1435 (36449) ~
1
--- .-
!!~I
1
.600 (15.240)
.515 /13.0811
~~~oPil
.200
(~:.
t II_
I
t---- i
r-I
(15.748)
~.175(4.445)
060 TVP
'-
II
t
020 MIN
(0.508)'
.
~~~8~;r
1
~I
,
.010 TVP
{0254}
-1~020{0508}
{15241
620
600
(15.240)
~- .140(3.556)
,110 (2794)
090 12.286)
28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
C.
MAX
IifR=;=n=n
_
125J~N175}
~
. _ _ .085 (2.1.59)
(33.020)
C
SEATING
PLANE
1.300 REF
.
:
700 - I
0'
1li"
REF.
~(1~~0)--I
016 (0.4061
NOTE 4
1485 (37.719)
C=~~3:-9}
o
600 115.240)
515 (13.081)
I
1.300 REF
T-liFF'FFffi;;;:-c..-::-=:::-~~i~~j!J:
:-::-:-!:-::-9~
=1
~
",SE",A",Tlii'NG"-_--t-_ _V
PLANE
L.I
j
12513.175)
MIN
·08~tl58)
(15.148)
~_-;:==::::.I- {Q254}
Mo;~ [
(33.020)'
200 (5 08)
MAX
110(2794)
090 (2.286)
032 TYP.
(0 813}
-H-
°r~~N.
020(0508)
016 (0 406)
.010 TYP
(0254)
.~
(15240)
-f~--
,0'
-
~ R~~.
L J
700
MAX
(17780)
NOTE 4
7-4
J
PACKAGING INFORMATION
CERAMIC DUAL IN·LlNE PACKAGE TYPE D
40-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE D
c
All dimensions in inches and (millimeters)
loao (528321~
2 030 (51 562)
---
PIN 1
1
600 (152401
515 (13081)
~.......j.!~
I--- .08~'59)
(1~~48)
C(15~)]
.
,.n.J""\.F\.LI::J-:::::::
t
'L
--i
pq-it- 10'"
--I-
010 TV'
102541,
(.508)
~
020 10 5081
016 104061
032 TV'
110 (2794)
090 (2286)
.020 MIN
(0813)
rf
',REF
700
--i
MAX
(17 780)
NOTE 4
CERAMIC DUAL IN·LlNE PACKAGE TYPE C
l6-LEAD CERAMIC DUAL IN-LINE
PACKAGE TYPE C
PIN 1 MARK
I--- 030
070 (UZID
(0762)
700 REF.
(17780) - ,
165(4.191)
.110 (2794)
L JLJI
t-i;j;;:;;;;::;;O;';;;;,
.;;;s;~--+--V
050 TVP
110(2794)
03:!TVP
090(2.286)
(0 B13)
r
910 (23114)
890 (22 808)
=--:::J
=="
--050 TYP
(1 270)
~(0,813)
.~(2794)
090 t2.286}
7-5
]
R
rf
,
010TV,
(0 254)
10'"
"-.:
L.. _r1;~ --I
I
::
REF
(8255)
NOTE 4
165(4191)
110 (2 794)
I
L
~ 050(1.270)
.015(0381)
IT _. " ,
l8-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
;)~:
075(1905)
115(2921)
p-----''---'- 085(2159)
.020 (0 508)
_ .02210 55BI
(12701
[
.100(2.540)
JLJ
_
PIN 1 MARK
="""
_I
Eta
075(1 905)
; ; 115(2921)
~~-~~
~ 050(1.270)
025 (0635)
~ 10.55B)
.015 (0.381)
O'OTVP
(0.254)
"-.,
I
"
I
325
I
I--- MAX ---I
~-
NOTE 4
rf
10'"
REF
PACKAGING INFORMATION
CERAMiC DUAl-IN·LlNE PACKAGE TYPE C
~O-LEAD
HERMETIC DUAL IN-LINE
PACKAGE TYPE C
All dimensions In Inches and (millimeters)
1010(......'
r-- .... (.6.i4ii
1- - - - _~ .....0;-"""IJ'Jjaf--.
110(27941
:090(2.2881
C
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
1215(~----I
1 186 (3D 099)
-=-
"'~I ~
PIN 1
I
PIN 1 MARK
f
.605 (15.367)
.585
'+~
__--=-
J!ZQ
U.ml
030 (0.762)
I
1.100 REF
(27940) -
t--~~..F
r.859)
I
' , -_ _ _ .100(2.540)
-=~Pn~~~~
t
•0000.04OTYP
(1.270)1(1 018)
~~
.0~(1.~) 'F""'ir~
150 (3.810)
.085~1$)
.080(1.524)
t-~~-t
~1~.~·
rJ'
111'"
REF•
.025(.835)
022 (0.568'
0i6 (0381)
110 (2794)
000 (2 286)
r---
28-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE C
~(35941)
1_ _ _ _ 1385{351,191
'-=f""'~6f1
=I_ _
.210(5334)
...-.joi.:i~~
I
~.54O)
.100
~
_080_(_,._524_)
.0501.040 TYP
(1.270)1(1.018)
110 (2.794)
-l~ 022 (0 568'
.040 (1.018)
0i5 (-0.38-"
ii9ii (22i6i
PIN 1 MARK
O5OI.04OTYP
(1.270)1(1 016)
7-6
.O(1~.~r
I
i
•
rJ'
, ,:.,
,,'
885
i
I- (~8~9)--I
NOTE 4.
40-LEAD-HERMETIC DUAL IN-LINE
PACKAGE TYPE C
0i0 (2286)
R
.080~.0112)
•150(3.810)
.. '.~--'- .090 ~.288)
,110 (2 794)
[::iJ
/
PACKAGING INFORMATION
All dimensions in inches and (millimeters)
CERAMIC DUAL IN·L1NE PACKAGE TYPE B
24-LEAD HERMETIC DUAL IN-LINE
PACKAGE TYPE B
r---
1__ __
1 285 (32639)
1 235 (31 369) -------,
-----
~--
_ ~N-.!II
600 (15240)
515 (13081)
~
_
220{5558j
MAX
__
SEATING
PLANE
100 (2 540)
MIN
2!.Q
(2794)
090 (2286)
---1Wo-REF
j
~~~~o~
:===_
---I
5-
CERAMIC LEAD LESS CHIP CARRIERS
18-LEAD CERAMIC LEAD LESS
PACKAGE TYPE F
7-7
125"i3175i
155 (3937J
060 TYP
--
~~28~;t
(156~48)
1 150 (3810)
190 (4826)
IIII-----J I
t
[' IL
L-=-1 h
~
(1 524)
09~~l86)
015MIN
010TYP
(03.'1
(02541
020 (0508\
016 (0 406)
~(1;~O)~
~
'
L J
-: k
700
MAX
~~;:~)
1~
REF
BUBBLE LEAD·LESS PACKAGE AND SOCKETS
BUBBLE SOCKET #7904
10 92::t.: 0 13
430"
-OOS-TI
I
457
180
~;~;~;~;~~H
r:-
CROSS RECESS BINDING HEAD
'l~'t1~~
JtiJ;;;;====;;;!l:ll~
~
II
<,'"0"" W% "
POLYESTER 94V-O
PIN 1 IDENTIFICATION
7-8
~
I
I
SECTIONJ..A
4 MBIT LEADED BUBBLE MEMORY PACKAGE
END VIEW
TOP VIEW
'-=ro
.l
.280
IDENTIFICATION LABEL
I..
1.500
..I
r
JJ
.oao TYP.
L
.375
SIDE VIEW
,"","_ _ _ 1.35 _ _-...j"~.015 RADIUS
1
113
f--------
~J
r ~I.
.135
~
t
_.
_ -1.500----1
SEATING PLANE
~L.016
P.C. BOARD SPACE REQUIREMENTS
.041 ",.002 DIA. (20x)
PLATED THRU HOLE
.200 DIA (4x)
FAR SIDE OF P.C.
BOARD KEEP CLEAR
OF TRACES
.:z
O~
·L
1.300 1.48
.08h .003 DIA. (4x)
NON PLATED HOLE
)
7·10
~8
f
u.s. SALES OFFICES
ALABAMA
Intel Corp
303 Williams Avenue, S W.
Suite 1422
Huntsville 35801
Tel (2051533-9353
ARIZONA
Intel Corp
11225 N 28th Dnve
Suite 2140
PhQanIX 85029
Tel' (602) 869-4980
CALlF()RNIA
Intel Corp
' Q.OIlGt~
Intei Corp
3300 HOlcomb Bndge Road
Surte225
Norcross 30092
Tel (404) 449-0541
ILLINOI8
Intel Corp.
Golf Road.
2~
SulteS1S
ROlling Meadow$ 60008
Tel (312)981·7200
TWX 910-651-5881
INDIANA
NEWJERIEY
InteiCorp·
Rantan Plaza III
Rantan Center
Fort Washtngton 19034
Edison 08837
Tel. (215) 641-1000
TWX 510-661-2077
Intel Corp.
201 Penn Center Boulevard
Tel (2011225-3000
TWX 710-480-8238
NEWMlXlCO
BFA Corp
PO Box 1237
Las Cruces 88001
Tel, (5051523-oeDl
TWX 91()..983.()543
BFA Corp,
3705 W..terfl8k:l. N E
1010 Hurley Way
Intei Corp
Su.. 3OO
Tel (505) 292-1212
Tel' (9161929-4078
9100 Purdue Road
SUite 400
IndianapolIS 46288
Intei Corp
Tel (3171675-0623
NEW YORK
Intei Corp,.
300 Motor Parkway
Sacramento 95825
7870 Opportunity Road
Suite 135
San Diego 92111
Tel (714) 268-3563
Intel Corp *
2000 East 4th Street
Su1t8100
Santa Ana 92705
Tel (714) 835-9642
- TWX 910-595-1114
Intel Corp.
3375 Scott Boulevard
Santa Clara 95051
Tel (408) 98Ht088
TWX 910-339-9279
911).338-D255
Intel Corp·
5530 OorbIn Avenue
SUite 120
Tarzana 91356
Tel (213) 706-0333
TWX 910-495·2045
COLORADO
Intel Corp
4445 Northpark Dnve
Su1t8100
Colorado Spnngs 80901
Tel (3031594-8622
Intel Corp •
650 S Cherry Street
Surte720
Denver 60222
Tel (3031321-110116
TWX 91()..931·2289
CONNEcnCUT
Intel Corp
36 Padanaram Road
~:In~)o::~.~
TWX 71().456-1199
EMe Corp ,
48 Purnell Place
ManchtSter 06040
Tel (2031646-6065
is~CC::r Street
Wallingford 06492
IOWA
Intel Corp
St Andrews BUilding
1930 St Andrews Dnve N E
Cedar RaPIds 52402
Tel (3191393-5510
KANSAS
Intel Corp.
8400W 110th Street
Suite 110
Overland Park 66210
Tel (9131642-8060
LOUISIANA
Industnal Digital Systems Corp
2332 Severn Avenue
SIn,. 202
Metalne, LA 70001
Tel (5041831-8492
MARYLAND
Intel Corp·
7257 Pat1
Source Exif Data:
File Type : PDF
File Type Extension : pdf
MIME Type : application/pdf
PDF Version : 1.3
Linearized : No
XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37
Create Date : 2014:07:17 15:25:28-08:00
Modify Date : 2014:07:17 15:08:59-07:00
Metadata Date : 2014:07:17 15:08:59-07:00
Producer : Adobe Acrobat 9.55 Paper Capture Plug-in
Format : application/pdf
Document ID : uuid:be7e6d99-1f63-cb46-9dc4-438792ee0b13
Instance ID : uuid:c5ca9fdc-c7e0-aa46-8ead-943dc1e2bef2
Page Layout : SinglePage
Page Mode : UseOutlines
Page Count : 816
EXIF Metadata provided by EXIF.tools