1983_NEC_Integrated_Circuits_for_Consumer_Use 1983 NEC Integrated Circuits For Consumer Use
User Manual: 1983_NEC_Integrated_Circuits_for_Consumer_Use
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t-IEC
INTEGRATED CIRCUITS
FOR CONSUMER USE
1983/1984
NEC cannot assume any responsibility for any circuits shown or represent that
they are free from patent infringement.
NEC reserves the right to make changes at any time without notice in order to
improve design and supply the best product possible.
©
1983
NEC Corporation
INTEGRATED CIRCUITS FOR ~CONSUMERUSE
1983/1984
II1II
~_1.__A_L_P_H_A_-_N_U_M_E_R_IC_A__L_IN__D_EX______________________________
2.
QUICK REFERENCE GUIDE
3. CROSS REFERENCE GUIDE
4. MAINTENANCE AND OBSOLETE TYPES
5. GENERAL STATEMENT
*
NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
o History
0
Types and Featu res
o Type Number Designation
0
Device Technologies
*
STANDARDS OF INTEGRATED CIRCUITS
*
HINTS ON CORRECT USE
*
*
TECHNICAL SYMBOLS AND TERMS
RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
6 -1.
CAR AUDIO
6 -2.
HOME AUDIO
6-3.
PORTABLE AUDIO
7. TV APPLICATIONS
8. DIGITAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11. ARRAYS
12. OTHERS
13. APPLICATION NOTES
ALPHA-NUMERICAL INDEX
ALPHA-NUMERICAL INDEX
Page
JJPA53C
14-DIP
5-Unit NPN Darlington Transistor Array ......... 870
~A54H
7-SIP
6-Unit Diode Array (Common Cathode) ......... 872
~A56C
16-DIP
7-Unit NPN Single Transistor Array . . . . . . . . . . . . 874
~A64H
7-SIP
6-Uriit Diode Array (Common Anode) . . . . . . . . . . . 878
~A67C
14-DIP
6-Unit NPN Darlington Transistor Array ......... 880
~A79C
16-DIP
7-Unit NPN Transistor Array . . . . . . . . . . . . . . . . . 882
p.PA80C
16-DIP
7-Unit PNP-NPN Transistor Array . . . . . . . . . . . . . . 884
~A81C
16-DIP
7-Unit NPN Darlington Transistor Array ......... 886
p.PA2001C
16-DIP
7-Unit NPN Darlington Transistor Array ......... 888
p.PA2002C
16-DIP
7-Unit NPN Darlington Transistor Array ......... 888
p.PA2003C
16-DIP
7-Unit NPN Darlington Transistor Array ......... 888
p.PA2004C
16-DIP
7-Unit NPN Darlington Transistor Array ......... 888
p.PB553AC
8-DIP
150 MHz Prescaler (Vcc=5 V) . . . . . . . . . . . . . . . . 578
p.PB556C
8-DIP
150 MHz Prescaler (Vee =3 V) . . . . . . . . . . . . . . . . 582
p.PB562C
8-DIP
1 G Hz Prescaler (V cc=5 V) . . . . . . . . . . . . . . . . . . 586
p.PC494C
16-DIP
Switching Regulator Control . . . . . . . . . . . . . . . . . 816
p.PC494G
16L-MFP
Switching Regulator Control . . . . . . . . . . . . . . . . . 827
p.PC574J
TO-92
33 V Tuning Voltage Stabilizer . . . . . . . . . . . . . . . 382
p.PC587C2
14-DIP
FM-MPX Demodulator . . . . . . . . . . . . . . . . . . . . .
p.PC1018C
16-DIP
AM-RF, MIX, IF
p.PC1026C
14-DIP
FM-MPX Demodulator . . . . • . . . . . . . . . . . . . . . . 101,973
p.PC1028H
7-SIP
FM-I F with Peak Detector. . . . . . . . . . . . . . . . . . .
p.PC1031H2
Po
10SIP
B/W Vertical Deflection . . . . . • . . . . . . . . . . . . . . 552
p.PC1032H
8-SIP
Dual Pre Amplifier. . . . . . . . . . . . . . . . • . . . . . . . 125
p.PC1043C
16-DIP
FG Motor Servo . . . . . . . . . . . . . . . . . . . . . . . . . 896
p.PC1052V
15-VDIP
Receiver for Radio-Control Systems . . . . . . . . . . . . 902
p.PC1053V
15-VDIP
Servo-Amplifier for Radio-Control Systems ....... 906
p.PC1158H2
7-SIP
Pre Amplifier with ALC . . . . . . . . . . . . . . . . . . . . 296
93,973
+ FM - IF Amplifier . . . . . . . . . . . 272
74,960
p.PC1161C3
16-DIP
FM-MPX Demodulator with Post Amplifier ....... 195
p.PC1163H
7-SIP
FM-I F Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . 177
pPC1167C2
16-DIP
FM-I F with Quadrature Detector . . . . . . . . . . . . . . 186
p.PC1176C
16-DIP
FM Noise Canceller . . . . . . . . . . . . . . . . • . . . • . . 121, 1001
P.PCl177H
Po
12SIP
3.5 W (4 Q) BTL Power Amplifier . . . . . . . . . . . . . 314
p.PCl180C
16-DIP
DOLBY B-Type Noise Reduction Processor ....... 254
p.PCl181 H3
Po
7- SIP
5.8 W (4 Q) Power Amplifier . . . . . . . . . . . . . . . . . 137
P.PCl182H3
Po
7- SIP
5.8 W (4 Q) Power Amplifier . . . . . . . . . . . . . . . . • 137
J,LPCl185H2
Po
12SIP
Dual 5.8 W (4 Q) Power Amplifier . . . . . . . . . . . . . 142
P.PCl188H
Po
12SIP
20 W (8 Q) Power Amplifier . . . . . . . . . . . .' ..... 222
J,LPCl197C
16-DIP
FM-MPX Demodulator . . . . . . . . . . . . . . . . . • . . • 286, 1049
..
ALPHA-NUMERICAL INDEX
Page
2
pPC1200V
15-VDIP
FM-I F with Quadrature Detector . . . . . . . . . . . . ..
79, 966
pPC1204C
16-DIP
REC/PB Amplifier. . . . . . . . . . . . . . . . . . . . . . . . 302
pPC1212C
8_ DIP
TAB
1 W (4 fl) Power Amplifier . . . . . . . . . . . . . . . . . . 326
pPC1213C
8_ DIP
TAB
2.4 W (4 fl) Power Amplifier . . . . . . . . . . . . . . . . . 336
pPC1215V
19-VDIP
AM Tuner for D.T.S. . . . . . . . . . . . . . . . . . . . . ..
57, 928
pPC1216V2
19-VDIP
AM Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
66, 939
pPC1217G
20-MFP
REC/PB System . . . . . . . . . . . . . . . . . . . . . . . . . 307
pPC1218H
8-SIP
250 mW (8 fl) BTL Power Amplifier ........... 347
pPC1221C
14_ DIP
TAB
Pre + ALC + 1 W (4 fl) Power Amplifier ...•...... 350
PPC1222C
16-DIP
AM Tuner + FM-IF Detector . . . . . . . . . . . . . . . . . 278,1043,1045
pPC1222C(R)
16-DIP
AM Tuner + FM-I F Detector . . . . . . . . . . . . . . . . . 278, 1043, 1045
pPC1224H
8-SIP
Dual Pre Amplifier. . . . . . . . . . . . . . . . . . . . . . .. 217
pPC1225H
Po
12SIP
30 to 50 W Power Amplifier Driver
234
pPC1227V
19-VDIP
FM-MPX Demodulator with Soft Separation ...... 109
pPC1228H
8-SIP
Dual Pre Amplifier . . . . . . . . . . . . . . . . . . . . . .. 130
pPC1230H
12-
pPC1235C
16-DIP
FM-MPX Demodulator with Post Amplifier
pPC1237H
8-SIP
Power Amplifier Protection
pPC1238
5-
Po
VDIP
10 W (8 n) Power Amplifier
228
pPC1241H
8-
Po
SIP
5.8 W (4 fl) Power Amplifier
152
pPC1242H
8-
Po
SIP
5.8 W (4 fl) Power Amplifier
152
pPC1243C
16-DIP
AM Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
pPC1245V
19-VDIP
FM-I F with Peak Detector . . . . . . . . . . . . . . . . ..
Po
SIP
20 W (4 n) BTL Power Amplifier .............. 146
...... 206, 1024
. . . . . . . . . . . . . . . . 247
85
pPC1246C
16-DIP
Pre Driver for 3-Phases DC Brushless Motor . . . . . .. 911
pPC1252H2
8-SIP
dbx VCA Noise Reduction System. . . . . . . . . . . .. 256
pPC1253H2
8-SIP
dbx RMS Level Sensor Noise Reduction System .... 262
pPC1263C2
14_ DIP
TAB
Dual 1.2 W (8 fl) Power Amplifier . . . . . . . . . . . . . 357
PPC1277H
Po
12SIP
Dual 4.2 W (8 fl) Power Amplifier . . . . . . . . . . . . . 363, 1065
PPC1320C
16-DIP
FM-MPX Demodulator . . . . . . . . . . . . . . . . . . . . 115
PPC1350C
14_ DIP
TAB
Pre + ALC + 450 mW (8 fl) Power Amplifier ...... 368, 1069
PPC1352C
28-DIP
NTSC Chroma & Picture . . . . . . . . . . . . . . . . . . . . 473
PPC1353C
14_ DIP
TAB
SI F Processor & Picture . . . . . . . . . . . . . . . . . . .. 456
PPC1356C2
22-DIP
PI F Processor & Picture . . . . . . . . . . . . . . . . . . .. 442
PPC1361C
24-DIP
12 Channel Selector
PPC1362C
20-DIP
12 Channel Selector . . . . . . . . . . . . . . . . . . . . . . 392
PPC1363C
24-DIP
16 Channel Selector . . . . . . . . . . . . . . . . . . . . . . 398
PPC1364C2
28-DIP
SECAM Chroma. . . . . . . . . . . . . . . . . . . . . . . .. 491
386
ALPHA-NUMERICAL INDEX
Page
pPC1365C
28-D IP
PA L Chroma & Picture
PPC1366C
14_ DIP
TAB
B/W PI F Processor . . . . . . . . . . . . . . . . . . . . . . . 452
pPC1373H
8-SIP
Remote Control RX Amplifier . . . . . . . . . . . . . . . 405
pPC1377C
22-DIP
Color Synchro Processor . . . . . . . . . . . . . . . . . . . 560
pPC1378H
Po
7SIP
Color Vertical Deflection . . . . . . . . . . . . . . . . . .. 565
pPC1379C
16-DIP
TAB
B/W Synchro & Deflection . . . . . . . . . . . . . . . . .. 569
pPC1382C
14-DIP
SIF Processor & DC Attenuator . . . . . . . . . . . . . .. 463
505
pPC1384C
28-DIP
PAL Chroma & Picture . . . . . . . . . . . . . . . . . . . . 525
pPC1391H
8-SIP
SI F Processor. . . . . . . . . . . . . . . . . . . . . . . . . .. 469
pPC1394C
14-DIP
Switching Regulator Control. . . . . . . . . . . . . . . .. 832
pPC1397C
22-DIP
Picture Multiplex Adaptor . . . . . . . . . . . . _ . . . .. 545·
pPC1470H
TO-126
Motor Govener
pPC2002
Po
5VDIP
5.4 W (4 Q) Power Amplifier . . . . . . . . . . . . . . . . 159
pPC78LOO
SP-8
3-Terminal Positive Voltage Regulator (0.1 A) . . . .. 840
pPC78MOOH
TO-220
3-Terminal Positive Voltage Regulator (0.5 A) . . . .. 846
pPC7800H
TO-220
3-Terminal Positive Voltage Regulator (1 A) . . . . . ..
pPC7900H
TO-220
3-Terminal Negative Voltage Regulator (1 A) . . . . . .. 858
pPD832G
54-FLAT
3.5 Digit LCD Clock
742, 1091
pPD833G
54-FLAT
3.5 Digit LCD Clock
742, 1091
PPD1701 C-Oll
28_ SLlM
DIP
EU R LW/MW/FM DTS (Clock)
590
pPD1701 C-013
28_ SLlM
DIP
JPN/US AM/FM DTS (Cloci<) . . . . . . . . . . . . . . . . 598, 1076
pPD1701 C-014
28_ SLlM
DIP
JPN/US/EU R AM/FM DTS (Clock) . . . . . . • . . . .. 607
pPD1703C-017
28_ SLlM
DIP
US/CND VHF/UHF/CATV TV DTS (Remo. Con.) .. 617
pPD 1703C-018
28_ SLlM
DIP
JPN/US/EUR LW/MW/FM DTS . . . . . . . . . . . . . . 626
pPD1703C-020
28_ SLlM
DIP
JPN/US/EUR LW/MW/FM DTS (Clock, Timer)
pPD1704C-Oll
42-DIP
JPN/US/EUR AM/FM DTS
. . . . . . . . . . . . . . . . . . . . . . . . . 921
(Clock, Timer, Remo. Con.)
pPD1705C-012
42-DIP
64-FLAT
649
660
US/CND VHF/UHF/CATV TV DTS
(Clock, Timer, Remo. Con.)
pPD1706G-Oll
852, 1128
689
JPN/US/CND LW/MW/FM/SW DTS
(Clock, Timer) . . . . . . . . . . . . .. 704
pPD1913C
16-DIP
Remote Control Transmitter. . . . . . . . . . . . . . . .. 411
PPD1937C
16-DIP
Remote Control Receiver . . . . . . . . . . . . . . . . . .. 418
PPD1943G
20-MFP
Remote Control Transmitter. . . . . . . . . . . . . . . .. 411
PPD1986C
16-DIP
Remote Control Transmitter. .. . . . . . . . . . . . . .. 423
pPD1987C
16-DIP
Remote Control Receiver . . . . . . . . . . . . . . . . . .. 428
3
ALPHA-NUMERICAL INDEX
Page
J,LPD1990AC
4
14-DIP
Serial I/O Time Keeping . . . . . . . . . . . . . . . . . . . . 792, 1106
J,LPD2006G
54-FLAT
3.5 Digit FIP/LED Clock . . . . . . . . . . . . . . . . . . . . 771
J,LPD6102G
24-MFP
Remote Control Transmitter . . . . . . . . . . . . . . . . . . 433
J,LPD6517P3
CHIP
3.5 Digit Multiplex LCD Quartz Watch
J,LPD6529C
42-DIP
Automotive Clock . . . . . . . . . . . . . . . . . . . . . . . . . 787
. . . . . . . . . . 805
1. ALPHA-NUMERICAL INDEX
2. QUICK REFERENCE GUIDE
3.
CROSS REFERENCE GUIDE
4.
MAINTENANCE AND OBSOLETE TYPES
5.
GENERAL STATEMENT
*
NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
o History
0
Types and Featu res
o Type Number Designation
0
Device Technologies
*
STANDARDS OF INTEGRATED CIRCUITS
*
HINTS ON CORRECT USE
*
*
TECHNICAL SYMBOLS AND TERMS
RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
6 - 1.
CAR AUDIO
6-2.
HOME AUDIO
6-3.
PORTABLE AUDIO
7. TV APPLICATIONS
8. DIGITAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11. ARRAYS
12. OTHERS
13. APPLICATION NOTES
QUICK REFERENCE GUIDE
QUICK REFERENCE GUIDE FOR AUDIO ICs
AM TUNER ICs
Function
Type No.
Package
",PC1018C
16-DIP
",PC1215V
19-VDIP
",PC1216V2
19-VDIP
",PC1222C/C(R)
16-DIP
",PC1243C
16-DIP
AM-RF
CON.
AM
IF
•
•
•
•
•
•
•
•
•
•
AM
DET
FM
IF
Application
FM
DET
Remarks
•
Home
Audio
Car
Audio
A
•
•
• • •
•
•
•
for DTS
C(R): Reverse S Curve
A
•
Portable
Audio
•
Page
272
57
66
•
-
278
169
FM-IF AMPLIFIER ICs
Application
Function
Type No.
",PC1028H
Package
7-SIP
",PC1163H
7-SIP
",PC1167C2
16-DIP
",PC1200V
15-VDIP
",PC1245V
19-VDIP
FM
IF
FM
DET
0
0
•
•
•
•
•
•
•
Signal
Meter
DET
PEAK
•
QUADRATURE
•
Home
Audio
Car
Audio
Portable
Audio
A.
0
A.
•
•
QUADRATURE
A
PEAK
A
Page
74
177
A
186
•
•
79
85
FM-MULTIPLEX les
Function
Type No.
Package
PLL
",PC587C2
14-DIP
",PC1026C
14-DIP
",PC1161C3
16-DIP
",PC1197C
16-DIP
",PC1227V
19-VDIP
",PC1235C
16-DIP
",PC1320C
16-DIP
•
•
•
•
•
•
•
POST
AMP
Application
VCO
STOP
Sep. Adj.
Home
Audio
Car
Audio
•
•
•
A
•
•
•
•
•
•
•
•
•
•
•
•
Page
93
101
195
A
•
Portable
Audio
•
•
•
286
109
206
A
115
7
QUICK REFERENCE GUIDE
PRE AMPLIFIER ICs
Type No.
Package
Supply
Voltage
VCC
(V)
",PC1032H
8-SIP
8- 17
/JPC1158H2
7-SIP
2.2 - 15
/JPC1204C
16-DIP
8 .... 20
/JPC1217G
20-MFP
/JPC1224H
8-SIP
±10 .... ±25
/JPC1228H
8-SIP
6,..., 16
1.8"'" 6
Electrical
Characteristics
Function
PRE
AMP
ALC DUAL
•
•
• •
• •
• •
•
•
•
•
Application
Page
Avo
(dB)
T.H.D.
(%)
Noise
(",Vr.m.s.)
81.0
0.1
1.4
70.0
0.05
1.2
85.0
0.3
1.3
72.0
0.07
1.0
72.0
0.002
0.8
100.0
0.05
1.1
Home
Audio
Car
Audio
•
•
•
Portable
Audio
125
•
•
•
296
302
307
217
•
A
130
Portable
Audio
Page
POWER AMPLIFIER ICs
Type No.
Po
RL
(W)
(n)
VCC
(V)
Remarks
Po
12- SIP
3.5 .... 10
3.5
4
6
BTL (1 W DUAL)
Po
7- SIP
9.5"" 16
5.8
4
13.2
OTL
/JPC1185H2
Po
12- SIP
9.5"" 18
5.8X2
4
13.2
OTL
",PC1188H
Po
12- SIP
±17"'" ±23
18
8
±22
OTL
1
4
6
OTL
2.4
4
9
OTL
/JPC1181 H3/82H3
/JPC1212C
8- DIP
TAB
3.5"'" 9
",PC1213C
8- DIP
TAB
4.5"" 11
/JPC1218H
8- SIP
1.8...., 5
0.25
8
3
BTL
/JPC1221C
14- DIP
TAB
3.5"'" 9
1
4
6
OTL Pre+ALC
/JPC1230H
Po
12- SIP
9"'" 16
20
4
13.2
BTL
±6 ...... ±1.5
8.4
8
±13
OTL
/JPC1238
Po
5- VDW
/JPC1241 H/42H
Po
8- SIP
9 .... 16
5.8
4
13.2
OTL
/JPC1263C2
14- DIP
TAB
3,..., 13
1.2 X 2
8
9
OTL
/JPC1277H
Po
12- SIP
5"'" 16
4.2X2
4
12
OTL
/JPC1350C
14- DIP
TAB
3.5 .... 10
0.45
8
6
OTL Pre+ALC
8,..., 18
5.4
4
14.4
/JPC2002
Po
5- VDIP
Applications
Electrical Characteristics
VCC
(V)
/JPC1177H
8
Package
Supply
Voltage
OTL
Home
Audio
Car
Audio
•
•
•
314
137
142
•
222
•
•
•
•
•
326
336
347
350
146
•
228
•
152
•
•
•
•
•
357
363
368
159
QUICK REFERENCE GUIDE
QUICK REFERENCE GUIDE FOR DTS ICs
DIGITAL TUNING SYSTEM ICs ,uPD1700 Series (AUDIO & TV)
~
Item
Package
Last Channel
Memory
Preset
Memory
J.LPD
1701 C-Oll
J.LPD
1701C-013
J.LPD
1701 C-014
J.LPD
1703C-017
J.LPD
1703C-018
28- SLIM
DIP
28- SLIM
DIP
28- SLIM
DIP
28- SLIM
DIP
28- SLIM
DIP
FM, MW, LW
FM,MW
FM,MW
TV
FM,MW, LW
7(FM)/
7(MW+LW)
6(FM)/6(MW) 6(FM)/6(MW) 6(FM)/6(MW)
Auto Down
28?L1M
DIP
FM, MW, LW
•
•
•
•
•
•
J.LPD
1704C-Oll
J.LPD
1705C-012
42-DIP
42-DIP
FM,MW
TV
J.LPD
1706G-Oll
64-FLAT
FM,MW
LW,SW
10(FM+MW
+ LW+SW)
6(FM)/6(MW) 8(FM)/8(MW)
•
Preset Ch.
Address Ind.
Auto Up
J.LPD
1703C-020
•
•
•
0
0
0
0
0
0
0
0
•
•
0
•
0
0
0
•
•
0
0
•
•
•
0
0
0
0
0
0
0
•
0
0
0
0
0
0
0
IF Offset
0
0
0
0
0
0
0
Dimmer
0
0
0
0
24
12
12
24
24
12
12/24
1
3
1
1
Manual Up
Manual Down
Rotary Tuning
0
10-Key Direct
Muting
Clock (Hr)
Timer (Series)
Slee p (
Indicator
I
A~to
off )
mmute
64
60
LED
•
0
0
A
A
A
A
0
FIP
A
A
A
0
0
0
•
0
LCD
0
Remo. Con.
c
...aco
.~
0..
a.
«
a
:.c:J
«
Car
•
•
•
Home
A
A
Portable
A
A
J.LPB553AC
•
A
A
A
A
A
•
•
•
A
A
A
A
A
•
TV·CATV
Prescaler
0
0
J.LPB562C
•
J.LPB553AC'
J.LPB562C
•
J.LPB556C
9
QUICK REFERENCE GUIDE
QUICK REFERENCE GUIDE FOR TV ICs
CHANNEL SELECTOR ICs
Type No.
Package
Supply
Voltage
VCC
(V)
Tuning
Voltage
Stabilizer
•
~PC574J
TO-92
-
~PC136~C
24-DIP
12
~PC1362C
20-DIP
12
~PC1363C
24-DIP
12
Indicator
Function
12 Ch
Selector
16 Ch
Selector
Neon
•
•
•
•
•
•
LED
Remarks
Page
33 V Zener
382
•
•
•
386
392
398
DIGITAL TUNING SYSTEM ICs
Refer to "DIGITAL TUNING SYSTEM ICs J,LPD1700 Series" on Page 9.
INFRARED REMOTE CONTROL SYSTEM ICs
Type No.
Package
Supply
Voltage
VCC
(V)
~PD1986C
16-DIP
2.2- 7.2
~PD1913C
16-DIP
2.0"'" 3.3
~PD1943G
20-MFP
2.0 - 3.3
~PD6102G
24-MFP
2.0"'" 3.3
~PC1373H
8-SIP
6 - 14.4
~PD1937C
16-DIP
12
~PD1987C
16-DIP
12
Function
Receiver
Transmitter
TV
•
General
Page
Remarks
Pre Amplifier
for TV
•
•
•
•
27-KEY
423
20-KEY 32-Custom Code
411
32-KEY 256-Custom Code
411
64-KEY 256-Custom Code
433
405
•
•
27-Command Receiver
418
26-Command Receiver
428
PIF ICs
Type No.
Package
Supply
Voltage
VCC
(V)
~PC1356C2
22-DIP
12
~PC1366C
DIP
14_
TAB
12
Function
AGC
Video
Detector
Video
Amplifier
AFT
SIF
Independence
•
•
•
•
•
•
•
•
•
•
SIF Amp.
& Det.
DC
Volume
Audio
Driver
Audio
Output
•
•
•
•
•
•
•
VIF
Amplifier
Page
442
452
SOUND ICs
Type No.
10
Package
Supply
Voltage
VCC
(V)
~PC1353C
DIP
14_
TAB
12
~PC1382C
14-DIP
12
~PC1391H
8-SIP
12
Function
Remarks
Page
456
•
463
for Stereo &
Bilingual Demo.
469
QUICK REFERENCE GUIDE
CHROMINANCE & LUMINANCE ICs
Type No.
Package
Supply
Voltage
VCC
(V)
J.lPC1352C
28-DIP
12
J.lPC1364C2
28-DIP
12
J.lPC1365C
28-DIP
12
J.lPC1384C
28-DIP
12
J.lPC1397C
22-DIP
12
Function
Video
Amp.
Pedestal
Clamp
Color
Sync.
Color
Demo.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Video
Text
Interface
PALl
SECAM
Auto Sw.
•
•
•
Remarks
Page
NTSC; DC Res.: 75 %
473
SECAM
491
PAL; DC Res.: 100 %
505
PAL; DC Res.: 75 %
525
Analogue Inputs
545
DEFLECTION ICs
Type No.
Package
Supply
Voltage
Function
Sync.
Sep.
VCC
(V)
IlPC1031H2
Po
10SIP
12 - 18
IlPC1379C
DIP
16_
TAB
12
IlPC1377C
22-DIP
12
IlPC1378H
Po
7-S IP
24
Vert.
OSC
(H+V)
Sep
•
•
• H Sep
V Sep
•
•
Application
Hori. AFC'
OSC· X-Ray·
Pre-Driver
Vert.
Output
•
•
•
•
Page
Color
B/W
•
•
Small
Small
•
•
•
552
569
560
565
QUICK REFERENCE GUIDE FOR
VOLTAGE REGULATOR ICs
SWITCHING REGULATOR CONTROL ICs
Type No.
J.l.PC494C
Package
Supply
Voltage
VCC
(V)
Reference
Output
Voltage
VREF
(V)
16-DIP
J.l.PC494G
16L-MFP
J.l.PC1394C
14-DIP
7 - 41
6.6
(Shunt)
5 ± 0.25
Function
Features
Output
Mode
OSCWave
Form
Over Current
Protection
Single
or
Push-Pull
Saw-Tooth
D.C.
Single
Saw-Tooth
Dynamic
Dead
Inhibit Time
Control
•
•
•
Sync.
•
•
Low
Voltage
Protection
•
Page
816
827
832
I I
QUICK REFERENCE
GUIDE
3-TERMINAL REGULATOR ICs
Type No.
*
12
Original
~PC78L05
SP-8
@
78L05
~PC78L08
SP-8
@
78L08
~PC78L10
SP-8
@
-
'* - 20- + 150
'* -20 -+ 150
'* -20 -+ 150
'* -20 -+ 150
'* -20 -+ 150
~PC78L12
SP-8
@
78L12
~PC78L15
SP-8
@
78L15
~PC78M05H
TO-220AB
78M05
-20 -+ 80
~PC78M08H
TO-220AB
78M08
~PC78Ml0H
TO-220AB
~PC78M12H
TO-220AB
~PC78M15H
TO-220AB
~PC78M18H
~PC78M24H
VIN
(V)
VOUT
(V)
'*
'*
'*
'*
'*
10
MAX.
(A)
PT
MAX.
(W)
MIN.
MAX.
5
7
30
0.1
0.8
8
10.5
30
0.1
0.8
10
12.5
35
0.1
0.8
12
14.5
35
0.1
0.8
15
17.5
35
0.1
0.8
*
5
7
35
0.5
20
-20 -+ 80
*
8
10.5
35
0.5
20
-
-20 -+ 80
*
10
12.5
35
0.5
20
78M12
-20 -+80
*
12
14.5
35
0.5
20
78M15
-20 -+80
*
15
17.5
35
0.5
20
TO-220AB
78M18
-20 -+ 80
*
18
21
35
0.5
20
TO-220AB
78M24
-20 -+ 80
*
24
27
40
0.5
20
J.LPC7805H
TO-220AB
7805
-20 -+ 80
*
5
7
35
1.0
20
~PC7808H
TO-220AB
7808
-20 -+ 80
*
8
10.5
35
1.0
20
~PC7812H
TO-220AB
7812
-20 -+ 80
*
12
14.5
35
1.0
20
~PC7815H
TO-220AB
7815
-20 -+ 80
*
15
17.5
35
1.0
20
~PC7818H
TO-220AB
7818
-20 -+ 80
*
18
21
35
1.0
20
~PC7824H
TO-220AB
7824
-20 -+ 80
*
24
27
40
1.0
20
~PC7905H
TO-220AB
7905
-20 -+ 80
* -5
- 7
-35
1.0
20
~PC7908H
TO-220AB
7908
-20 -+ 80
* -8
-10.5
-35
1.0
20
~PC7912H
TO-220AB
7912
-20 -+ 80
*-12
-14.5
-35
1.0
20
~PC7915H
TO-220AB
7915
-20 -+ 80
*-15
-17.5
-35
1.0
20
~PC7918H
TO-220AB
7918
-20 -+ 80
*-18
-21
-35
1.0
20
~PC7924H
TO-220AB
7924
-20 -+ 80
*-24
-27
-40
1.0
20
@ ~PC78LOO
'*
*
Package
Operating
Temperature
Range
(OC)
Series are used NEC original packages called SP-8.
If package dimension is needed, see each specification.
Junction Temperature.
Output Voltage Accuracy ± 10 %.
Output Voltage Accuracy ±5 %.
QUICK REFERENCE GUIDE
QUICK REFERENCE GUIDE FOR ARRAYS
TRANSISTOR ARRAYS
~___________TypeNo.
------ -~
Item
Package
Number of units
Sink
Outputs
~PA2001C ~PA2002C ~PA2003C ~PA2004C
~PA53C
~PA56C
~PA67C
~PA79C
~PA80C
~PA81C
14-DIP
16-DIP
14-DIP
16-DIP
16-DIP
16-DIP
16-DIP
16-DIP
16-DIP
16-DIP
5
7
6
7
7
7
7
7
7
7
•
•
0
0
G
Cit
•
60
60
60
60
•
•
Source
•
Vo(V ss ) MAX. (V)
30
40
30
20
(-60)
45
10 MAX. (A/unit)
0.4
0.1
0.15
0.15
50m
0.4
0.5
0.5
0.5
0.5
3200
200
-
2800
2800
2800
•
Single
hFE TYP. (-)
NPN Darlington
•
LED, Lamp
c:
CtI
0
0
0
•
0
0
0
0
20
-
2.7
10.5
•
0
0
0
22
20
...
G
•
Induction Load
A.
A
0
.~
0.
c.
0
Printer
0
.~
2500
PNP-NPN
0
Reverse Bias
Protected Inputs
(kn)
450
Separate
- - - - - - .. - -
Clamp Diode
Input Resistance
2500
2800
10.5 &
20
20
-
A.
0
0
0
0
0
...
G
•
•
0
A.
0
0
0
0
14-25 V
PMOS
5V
TTL,
CMOS
10 V
CMOS
Zener
-----1
Feed-forward,
Feed-back,
Measures for
correction
~------~------~
c
o
.;::;
C'O
E
.Ec
"C
Qj
g
S2
Field
1. ALPHA-NUMERICAL INDEX
2.
QUICK REFERENCE GUIDE
3. CROSS REFERENCE GUIDE
4. MAINTENANCE AND OBSOLETE TYPES
5.
GENERAL STATEMENT
*
NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
a History
0
Types and Features
a Type Number Designation
0
Device Technologies
*
STANDARDS OF INTEGRATED CIRCUITS
*
HINTS ON CORRECT USE
*
*
TECHNICAL SYMBOLS AND TERMS
RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
6-1.
CAR AUDIO
6-2.
HOME AUDIO
6-3.
PORTABLE AUDiO
7. TV APPLICATIONS
8. DIGITAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11. ARRAYS
12. OTHERS
13. APPLICATION NOTES
•• t., ..:,
i
I
I
CAR AUDIO
INDEX
Page
J..LPC1215V
AM Tuner for DTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
57
J..LPC1216V2
AM Tuner. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
66
J..LPC1028H
FM-I F with Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
74
J..LPC1200V
FM-I F with Quadrature Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
79
J..LPC1245V
FM-IF with Peak Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
85
J..LPC587C2
FM-MPX Demodulator _ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
93
J..LPC1026C
FM-MPX Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,
101
J..LPC1227V
FM-MPX Demodulator with Soft Separation . . . . . . . . . . . . . . . . . . . . ,
109
J..LPC1320C
FM-MPX Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
115
J..LPC1176C
FM Noise Canceller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
121
J..LPC1032H
Dual Pre Amplifier
125
J..LPC1228H
Dual Pre Amplifier
130
J..LPC1181H3
5.8 W (4 n) Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
137
J..LPC1182H3
5.8 W (4 n) Power Amplifier . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
137
J..LPC1185H2
Dual 5.8 W (4 n) Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . .
142
J..LPC1230H
20 W (4 n) BTL Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . .
146
J..LPC1241H
5.8 W (4 n) Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
152
J..LPC1242H
5.8 W (4 n) Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
152
J..LPC2002
5.4 W (4 n) Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
159
•
55
CAR AUDIO
BLOCK DIAGRAM
AM Block
'\7 Ant.
"--
..
AM
Detector
AM
IF Amp.
AM
Front End
p
AM OUT
J,tPC1215V (for DTS)
J,tPC1216V2
FM Block
\17 Ant.
AMIN
R CH. OUT
'--
FM
Front End
r--
FM
IF Amp.
r--
FM
IF Limiter
FM
Detector
f-
~
Noise
Canceller
-
MPX.
t-
~
L CH. OUT
A
MIX
RF
( JE9016 ) ( JE9011 )
( JE9011 )
I
I
I
OSC
( JE9011
I
I
J.,LPC1176C
J,tPC1028H
J,tPC1200V
J,tPC1245V
I
I
J,tPC587C2
J.,LPC1026C
J,tPC1227V
PC1320C
AF Block
R CH IN
~
Pre Amp.
P.H.
~
P.H.
Pre Amp.
~
I I
I
Control
Amp.
Control
'--______
Amp.
f
I
Po Amp.
~------~OC]
___'~--~'___p_O_A_m_p_.___'~-------o(]
L CH. IN
J.,LPC1032H (Dual)
J,tPC1228H (Dual)
56
SPEAKER
'----------'
J.,LPC1181H3
J.,LPC1182H3
J.,LPC1185H2 (Dual)
J,tPC1230H (BTL)
J.,LPC1241H
jJPC1242H
J.,LPC2002
SPEAKER
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1215V
ELECTRONIC TUNING AM RADIO RECEIVER SUBSYSTEM
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The ,uPC1215V, a monolithic integrated circuit, is a subsystem that provides the mixer, low level oscillator, IF
amplifier, detector and On channel detector stages for an electronic tuning AM radio receiver.
The ,uPC1215V also provides internal AGC for the first IF amplifier stage, delayed AGC for an optional external
RF amplifier, oscillator buffer amplifier to drive a logic section and local/distance sensitivity control.
The ,uPC1215V is suitable for use in automotive radio receivers, specially where compact mounting is required,
such as car stereo sets, because its package is the 19-1eads vertical dual in-line plastic package (V-DIP).
FEATURES
o Varactor-Diode tuning.
o Good sensitivity and wide AGC range.
o Excellent overload characteristics.
o Delayed AGC for RF amplifier.
o Special low level oscillator to reduce tracking error.
o Oscillator buffer output.
o ON channel detector for auto scan stop.
o Local/Distance sensitivity control.
o Occupation of minimum area in P.W.Board.
PACKAGE DIMENSIONS (in millimeters)
c 1.3
~
q
2 8
2 .5 MAX.
1\
~
x «x «x «x
«
MARKING
1
2
3
4
5
6
7
8
9
~
~
~
~
L11
N
co
co
cO
S
~
::!
10 11 12 13 14 15 16 17 18 19
"--
-
t--
2.54
I---
~
I
I
2. 54
0.6 MAX.
I----22.86
II
0.35
1
2.54
I--
57
pPC1215V
BLOCK DIAGRAM
CONNECTION DIAGRAM
Connection
Pin No.
Connection
Pin No.
1
GND1
2
AGC for Antenna
3
AGC Filter
4
AGC for RF
5
OSC Tank
6
MIX Input
OSC Buffer Output
7
OSC Bypass
8
9
MIX Output
10
GND2
11
1 st. I F Amp. Input
12
AGC Input
13
1st. IF Amp. Output
14
Detector Output
15
2nd. IF Amp. Input
16
VCC
17
On Channel Det. Input
18
LO/DX Control Input
19
On Channel Signal O:.Jtput
EaUIVALENT CI RCUIT
19
18
58
,uPC1215V
ABSOLUTE MAXIMUM RATINGS (Ta=25 DC)
DC Supply Voltage
15
Vcc
V
3.0
430 (Ta = 75 DC)
Input Voltage
Vi
Package Dissipation
Pd
Operating Temperature
T opt
Storage Temperature
T stg
Vp·p
mW
-30 to +75
-40 to +125
°c
°c
8.0 to 15
-30 to +75
°c
RECOMENDED OPERATING CONDITIONS
DC Supply Voltage Range
VCC
Operating Ambient Temperature
Ta
ELECTRICAL CHARACTERISTICS (Ta=25
CHARACTER ISTIC
SYMBOL
°c,
MIN.
V
Vcc=10 V, f=1.0 MHz, f mod .=400 Hz, mod.=30 %)
TYP.
MAX.
UNIT
TEST CONDITION
Circuit Current
ICC
10
14
21
mA
Maximum Sensitivity
MS
14
21
28
dBJ,LV
Signal to Noise Ratio
SIN
8.0
13
dB
Vi = 21 dBJ,LV
Vo
70
100
130
mVr.m.s.
Vi=74 dBJ,LV
Detector Output Volt.
Harmonic Distortion
On Channel Signal
T.H.D.
0.5
V19·L
V19-H
At no signal
Vo=30 mVr.m.s.
1.0
%
Vi =120 dBJ,LV
0.5
V
Vi = 0 d BJ,L V, R L = 18 kn
V
Vi = 74 dBJ,LV, RL = 18 kn
8.0
TUNER PERFORMANCE CHARACTERISTICS
(Ta=25
°c,
Vcc=10 V,f=1.0 MHz,f mod .=400 Hz, mod.=30 %)
CHARACTER ISTIC
TEST CONDITION
VALUE
UNIT
Maximum Sensitivity
V 0 = 30 mVr .m.s.
22
dBJ,LV
Usable Sensitivity
SIN =20 dB
28
dBJ,LV
Detector Output Voltage
Total Harmonic Distortion
Vi =74 dBJ,LV
100
mVr.m.s.
Vi =74 dBJ,LV
0.3
%
Vi=126 dBJ,LV
0.6
%
Vi=74 dBJ,LV, mod.=80 %
1.2
%
Signal to Noise Ratio
Vi=74 dBJ,LV
52
dB
I F Rejection Ratio
Vo=30 mVr.m.s., IF =450 kHz
56
dB
Image Rejection Ratio
Vo = 30 mVr.m.s., f+2 IF
57
dB
Selectivity
M=±10 kHz
39
dB
40
dB
47
dB
Tweet
Vi=74 dBJ,LV, 2 IF=900 kHz
3 IF = 1 350 kHz
OX Sensitivity
V19=8.0V
26
dBJ,LV
On Channel Bandwidth
Vi =74 dBJ,LV
5.0
kHz
At terminal 5
150
mVr.m.s.
At terminal 8
4.0
Vp-p
Oscillation Voltage
59
m
o
'l::
"'tJ
C')
..l
TEST CIRCUIT
N
..l
o22~ld 9
(J1
<
AC. Volt. Meter
Distortion Meter
Ql : 2SK49H
Vee
Dummy Antenna
30 Q 15 pF
~I
L2
. 022 JiF
~
-
SG: 50
Q
+ 10 V
+
65 pF
47 JiF
'.022.F
+
2.2 JiF
I
Lli
I
,uPC1215V
150 k.Q
+
2.2 JiF
.01 JiF
~PF
150 k.Q
l '1
.022
CT3
IIF
I
18
:S2]:: 1
D
m
I
CJ)
k.Q
r
.022 JiF
CF2
Tuning Voltage
DC. Volt. Meter
,uPC1215V
COIL DATA
L 1 & L2 : Ant. & R F Coil
Tank -r-~,.......,
Drain
GND
Vee
: OSC Coil
CD
MIX
Vee
14T
(D-Q)
48T
o
: 1FT
TYPE 7MC·4718N (Toko inc.)
~
@
®
®
IFT2
62T
Qu=60 min., L=95 ,uH
0
3
7T
TYPE 7BR·6048Z (Toko inc.)
~
30
IFTl
Qu =80 min., L = 170 pH
CD-ev, ev-Q), @-@
MIX
L3
TYPE 7BR·5407N (Toko inc.)
eFl
Qu=115±20 %, C=180 pF built in
CD-ev, ev-Q), @-@
GND
1FT
69T
77T
14T
TYPE 7MC·l0l000CO (Toko inc.)
L = 680 .uH, C = 180 pF built in
------
CERAMIC FILTER
CFM2-450BL
CFM2-450ZL
Center Frequency
450 kHz
450 kHz
6 dB Bandwidth
6 kHz min.
4 kHz min.
Selectivity ±9 kHz
16 dB min.
18 dB min.
I nsertion Loss
6 dB max.
6 dB max.
Input Impedance
1.5 kn
1.0 kn
Output Impedance
2.0 kn
1.5 kn
Marking
2
3
I : Input
2:GND
3: Output
61
m
I\)
~
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('")
-'
N
TYPICAL APPLICATION
-'
U'I
Antenna
L
<
AF Output
Ql: 2SK195
R4 68 Q
e1
e2
I 01"F
I-----r--l
L2
I:
Vee +10 V
hD2 iT
k
1[" eT2
r
OSC. Output
to PLL .S",th.g,,,
01 "F
ell
I
"'8 1+
.01 "F
ox
~
C21
lO,uF
+
pPCI215V
Logic Vee
R5
. 047 ,uF
Tuning Voltage
-from PLL Synthesizer
VOl. VD2 & VD3: ISV1l7
ICl~
1
.022 ,uF
,uPC1215V
TYPICAL CHARACTERISTICS (Ta = 25°C)
SIGNAL TO NOISE RATIO
DETECTOR OUTPUT CHARACTERISTICS
+10
co
"0
I
60
0
OJ
tlD
.'S -10
"0
>
:J
a. -20
I
-30
-50
-60
.Q
VCC=lO V
f=l.O MHz
ro
-
co
50
I
"0
J-, ...--i\.
0
>
I
Ii
:J
',p
/
---
Sj nal
I'
Noise
0
I
80
60
40
20
100
120
Vi-Input Voltage -dB,uV
o
80
60
40
20
100
120
Vi -Input Voltage -dBJ,N
OUTPUT VOLTAGE AND TOTAL
HARMONIC DISTORTION vs. MODULATION
TOTAL HARMONIC DISTORTION
VS, INPUT VOLTAGE
500
10
?f(
I
c:
I
8
0
',p
u
'c0
fmod=400 Hz
ro
0
I
2
0
~
0
20
0
U
120
Vo
:c
:J 200
r---
6
'c
bQ
.'S
>
"0
\
I
Vi
E
I 300
\\....
l-
0
t0
;;
\\
,\
4
c:
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\
f mo d=400 Hz
Vi=74 BJ,tV
?f(
8
I
400
\
6
E
ro
I
VeC=lO V
f =1.0 MHz
\
(5
Vi
0
10
VCC=10 V
f =1.0 MHz
0
I
100
~
2
:/
./
\I,-Input Voltage -dB,uV
:):)
o
o
V
~fo,..
V
/'
J
T:e- " V
V
~
20
40
60
mod- Modulation-%
80
100
TOTAL HARMONIC DISTORTION
vs, MODULATION FREQUENCY
ELECTRICAL FIDELITY
+10
10
,
i
~
V
/
V
V
/
./
~r-.
0
I
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I
-10
?f(
I
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0
0
Vi
0
\
o
,~ -20
a:::
I
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> -30
-40
30
VCC=lO V
f =1.0 MHz
mod=30 %
Vj =74 dBtt V
III100
6
I
u
'c
I
0
\
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ro
:c
\
ro
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c:c
"0
I
ell
tlO
.:3
(5
>
Vee=IO V
f =1.0 MHz
fmod=400 Hz
mod=30 %
Vo=30 mVr.m.s.
\V
-20
-30
V
/'
+20
+10
Vee=lO V
f mo d=400 Hz
mod=30 %
40
30
~
1
'5
c.
.=
20
Usable Sensitivity
(S/N,=20 dB)
r-- 10....
I
I
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I
I
Max. Sensitivity(Vo =30 m~r.m.s )_.- -
CI:I
c
c
2c
-
f - Detune Frequency- kHz
o
0.6
1.0
0.8
1.4
1.2
1.6
f - Receiving Frequency - MHz
IF REJECTION AND IMAGE REJECTION
TWEET CHARACTERISTIC
0
Vec=IO"V
f mo d=400 Hz
mod=30 %
fif=450 kHz
80
c:c
"0
I 60
-10
_
....
0
:p
CI:I
0::
C
0
+:;
40
U
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'(jj'
0::
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1\ ' ".
\
Vi=120 dBpV
I
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f=1.0 MHz
f mo d=400 Hz
mod=30 %
RL=18kO
,
Vi=30 dBpV I
\
50 \
~ \
~CD ~
~
I\.ll
,
+4
+2
-2
o
f - Detune Frequency - kHz
+6
2 IF(900 kHz)
-"~t~~3~~:~
T 1'F:- -
-
-
-50
1.6
1.4
1.2
1.0
0.8
~ 10
I
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,
-40
Vee=IO V
f mo d=400 Hz
mod=30 %
Vo=30 mVr.m.s.
12
B
\ i\
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I-
ON CHANNEL BANDWIDTH
Ql
c
"\
,
-30
I
f -Receiving Frequency-MHz
en
f\, ~
ell
ell
l-
20
0
\
c:c
"0 -20
I
~
IF
1
~ejection
Imfge
o
20
40
60
80
100
120
COMPONENTS LAYOUT FOR P.W.ASSEMBLY (Copper side)
AF Output
Vee
OSC. Output
GNO
r
Vee
NEe
OUT
CIS
'~H-
R~'.~ .... C13 i '
V;:;' I
C6 ".:;.;.'
C,19
. C22
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'
.
<.'.'
"
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Cl
C3
T
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IVriIl
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j
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,-',"
1~:2Rl~
;
.
T
.
L:J2
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'.' '. .:. * Tell--Jr-'
'-'-If--L~
CJ ""t
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LO/OX
Logic Vee -------
Antenna
f
\"'.R7 .R6'
,
8~
,'-;J
5
J
Vr
jlPCI215V
Tuning Voltage
1::
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c.n
<
m
OJ
BIPOLAR ANALOG INTEGRATED CIRCUIT
p,PC1216V2
AM TUNER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
ThepPC1216V2, a monolithic integrated circuit, is an AM tuner. It is suitable for use in automotive radio receivers,
specially where compact mounting is required, such as car stereo sets, because its package is the 19-1ead vertical
dual in-line plastic package (V-DIP).
Internally, R F amplifier, Mixer, IF amplifier, Detector and two types of AGC circuit are included.
FEATURES
• Reduction of the adjustment time and the mounting area for I F transformer.
• Minimum difference of maximum sensitivity at the various receiving frequency.
• Good SIN and good tweet characteristic.
• High strength against the electrostatic damages for the antenna terminal.
• Low transient noise when power switch is turned on.
• Wide AGC range is provided by the two AGC circuits (delay type) employed in the I F and R F stages, in addition
to the capability of withstanding large input and the yield of high SIN.
• Easy to handle because of its V-D IP construction.
• Free of mismounting in P.W. Board due to its lead formation.
PACKAGE DIMENSIONS in millimeters
~
25.5 MAX.
~
~
~ ..........
~
x« x«
MARKING
1
2
3
4
5
6
7
8
9
~
C\J
2
-0
>
-=;
r\,
'"
~
'0
i=0
c
bO
en
0
l\......
-50
Not
.-100
8
E
VI
is
6
u
vi
E 400
.;
>
Ql
-=;
:::c
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\
\
fij
"0
I-
I
ci
2
\
~
~
0
20
200
Q)
I 100
0
~
40
:::c
'"
I
ci
~
....,:
--- -- -- --I-80
60
100
Vo......V
4
./
I-
0
.....::::..±..-
'c
"0
Ql
, i\.
1--
V
0
120
2
o /'
../
~
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Vi-Input Voltage-dB.uV
/'
V
0
I
60
40
20
m - Modulation- %
I
- -
~'" ~
Ql
bD
2
-0
>
-10
~,
r\
:::I
C.
-=;
o
.8u
,
-20
Vec= 13 V
f
= 1 MHz
Ql
o
m =30%
10 -30 Vi = 74 dB.uV
~
RL = 10 kS2
Ql
-40
30
\
\
I
100
300
1k
fmod- Modulation Frequency- Hz
70
-
T.H.O.
ELECTRICAL FIDELITY
"0
3k
/
,/'
+ 10
CD
./
,,/
6
u
fij
u
\ m=30%
~
is
0
0
\
m=80% \
I
§
c.
0
\
~
0
bO
\ \,
4
120
Vee=13V
-f
= 1 MHz
f mod=400 Hz
8 - Vi = 74 dB.uV
RL = 10 kS2
:;J
2 300
"6
>
'c
§
100
10
c
E
I
:::I
0
80
60
DETECTOR OUTPUT AND TOTAL HARMONIC
DISTORTION vs. MODULATION
Vee = 13 V
f
= 1 MHz
f mo d=400 Hz
RL = 10 kS2
1
\
,
I
40
20
120
10
I
L
Vi-Input Voltage- dB ,LV
80
40
60
Vi-Input Voltage-dB,LV
I
I
o
TOTAL HARMONIC DISTORTION
VS. INPUT VOLTAGE
c
10
/
/
.....
500
.2
/
i
I
20
20
z
(f)
\
Ql
I
I
V
I
0
~
30
.........
1\
U
.& -40
Vee = 13 V
f
= 1 MHz
fmod=400 Hz
m =30%
RL =10 kQ
V
1
0::
\
o
J
40
"I
B -30
:::J
-60
0
:;::;
fij
0
0
~
I
Vee = 13 V
f
= 1 MHz
fmod= 400 Hz
m
=30%
RL = 10 kS2
'-
-20 ~ r--...
Ql
bO
II
CD
"0
II
E
E
I
~
I,..-
~
50
10k
--
80
~
100
jlPC1216V2
TOTAL HARMONIC DISTORTION
vs. MODULATION FREQUENCY
10
Vee= 13 V
f
= 1 MHz
Vi =74 dB/.N
RL =10 kQ
8
~
I
c
a
:ea
6
ill
i:5
u
'c
a
§
C'J
\
4
:J:
Ci'i
(5
\
l-
,
I
ci
:i
\
,
m=80%
~
....,.:
\, " ..... ..........
m=30%
---- --- -
~
o
30
-~
1k
300
100
;,.
./
....
3k
10k
fmod -Modulation Frequency- Hz
IF REJECTION AND IMAGE REJECTION
TWEET CHARACTERISTIC
o
100
80
--- ---- -. . . .V
I
~
~
CD
"0
I
60
0
'+0
C'J
a::
I
/
I
V
\
-10
IF Rej ection
~
F+=- f - -
Image Rejection
I
-
\~
.~
~ -20
I
\\.
\\,
\
\1\.
c
0
U
Vee = 13 V
fmod= 400 Hz
m =30 %
RL = 10 kQ
A maxi mum output
value of a detector
output beat.
40
Vee = 13 V
fmod=4oo Hz
m =30%
Vo =40 mVr.m.s.
RL = 10 kQ
Q)
'iiJ
a::
20
/~ ~
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-40
\~
21F
J
V
".....
-50
I
I
,."
/
31F
I
o
o
0.5
20
40
80
100
120
Vi-Input Voltage- dB ,N
1.5
1.0
60
f- Receiving Frequency- MHz
ONE-SIGNAL SELECTIVITY
CHARACTE RISTIC
MAX. SENSITIVITY AND USABLE SENSITIVITY
50
100
,
I
80
\
CD
"0
I
60
C'J
a::
c.
E
",
40
::t
CD
I
"0
I
\,
\
I
/
-10
/
\
2 30
(5
>
~
+10
t:.f- Detune F requency- kHz
.........
c.
""'--
E
Vee = 13 V
f
= 1 MHz
fmod=400 Hz
m =30%
Vo =20 mVr.ms.
RL =10 kQ
I:
\ oJ
Cll
tlD
V
I
\
-20
>
I
20
Q. 30
40
I
I
,
g
~
\
I
I
Vee = 13 V
fmod=4oo Hz
m =30%
RL = 10 kQ
\
+20
C'J
c
c
Usable Sensitivity (S/N= 20 dB)
20
2c
c::(
I
~
-
10
"-
-
Max. Sensi'tivity(Vo-40 mVr.m.s.)
I
+30
o
0.5
I
j
I
-
I
I
1.0
1.5
f- Receiving F requency- MHz
71
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I\)
1::
"n
~
N
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en
<
N
TYPICAL APPLICATION
ANT.
120Q
4.7JiH
AGe
DEl.
AGe
VR
~
' - { ) to Power Amp.
"
'-- 700
E
1.2
'c0
co
fMOO=400 Hz
DO
~
>
1.0
C
u
b 600
VCC=lO V
fFM=lO.7 MHz
500
0.8 :; 400
.fr
'0
....
I
300
0.4
.sg
0.2
8I 100
J:
d
I
C5
0
.,.:
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40
I
2
......
'co
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co
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100
80
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T.H.D.
CD
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-10
co
=:!CD
.~ 3 o "t) -20
Q
...- V
-~
/""
0
0
~
c::
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/'
/
200
L.I..
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~
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~
0.6 o...
E
co
ro
VOAF . /
~
V
/
I
0
I
c::
0
:e
1.8
1.6
0
1.4
20
1.2
0.8
~
-I
0.6
d
0.4
I
:; -3
~
Co
o
... -4
0
N-5
Q
I
-6
0
I
I
I
I
VCC -Supply Voltage - V
I
--- -- --.J.:.~.~~80
100
4
f'\.
VCC=lO V
Vin=80 dBp
~
'r'\.
\
3
1\
"'\
1\
2
T.H.O.(Llf = ± 75 kHz)- I - - -
T~H.O.(Af:! ±2~.5
I-- . /
SIN
60
r-......
co
g
10
76
0:::
~
U
~
1'-
\
70
,
........ AMR
\
\
~
~
!:?
5
I
r-.
c::
~
r
\\~
I
-80
~
>
ICC
~ \
Z
~ -70
~
S CURVE
V6AF
c::
.-1-0...
1- 60 (f) 60
r- r---....
-
I-....
Vin -Input Voltage-dBp
I
(.)
0
L.I..
0.2
E
...
...
f= 10.7 MHz
fMOO=400 Hz
Vin=80 dBp
~ ........
Q)
....
:t:
.,.:
Q)
co
~
E
1.0
co
J:
I
0
III
'c0
"t)
20
I
DO
.s
u
CD
VOAF
/ V
TOTAL HARMONIC DISTORTION,
DETECTOR OUTPUT VOLTAGE, CIRCUIT
CURRENT vs. SUPPLY VOLTAGE
~ 2.0
V
kHz) I - I
15
I
-600 -500 -400 -300 -200 -100
0
~
f'.... r-
~
+ 100 +200 +300 +400 +500 +600
(10.7 MHz)
f-Carrier Frequency-kHz
-120
JLPC1028H
LIMITTING SENSITIVITY, DETECTOR
OUTPUT VOLTAGE VL AMBIENT
TEMPERATURE
DETECTOR OUTPUT VOLTAGE VL
MODULATION FREQUENCY
II]
II
--.......~
....
::J
.s-5
::J
\
o
.....
o
I
~ -10
~
ll-
I
~-15
o
~
Co=O.OI J-IF
I
I-I--
1
10
100
1 k
VCC=10 V
f=10.7 MHz
Vin=80 dB~
go=O
~
II]
'tJ
I
___ ' "
bO
~
'E
\
:.::i
I
10 k
70
.iii
c
~
100 k
Ic:
~
fMOO-Modulation Frequency-Hz
'tJ
I
2
50
bO
c
ra
.c
c..>
Q)
I
VCC=10 V
f=10.7 MHz
Vin=80 dBJ-I
Q)
:::.;
60
:;:;
~~2F-~
I
80
I
I
I
a
I
I
bO
ra
==0
-1
30
I
:; -2
:
-3
I
.....
20
~Q) -4
10
~
o
Vin(lim)" t - - -
I
c.
;3
I
I
>
40
r"'"
V
:--VL1VOAF
r-
I
I
I
I
-5
I
I
I
I
c(-6
u..
~ -20
o
~
20
40
60
80
Ta -Ambient Temperature-'C
DETECTOR COIL TUNING PROCEDURE
1. In the test circuit, the signal generator SG is connected to the input terminal pin 1, and the AF voltmeter and
the total harmonic distortion meter are connected to the output terminal pin 7.
2. The SG is set at f
= 10.7
MHz, fMOD
= 400
Hz, .6.f
= ±22.S
kHz and the input level to the device under test
shou Id be 200 JiV.
3. After the procedure of 1 and 2, the detector coil is adjusted so that the output level as indicated by the AF
voltmeter is maintained the maximum value.
4. Then the detector coil is finely adjusted so that the total harmonic distortion is obtained the minimum value.
5. After the setting of 1 mV input level, the procedure of 3 and 4 are repeated.
(By the tuning at 200 JiV and 1 mV input level, the device provides the most stable characteristic from weak to
strong input signal level.)
TYPICAL APPLICATION
50kVR
• 7511s De·emphasis
CF: Ceramic Filter
CFSA-107
TaKa INC. made
SFE 10.7MA
MURATA CO. made
or equivalent.
Det. Coil
fo= 10.7 MHz, 00=50
C=22 pF (Built in)
TKACA-17473Z
TaKa INC. made
or equivalent.
77
,uPC1028H
PRINTED CIRCUIT BOARD PATTERN
in millimeters (inches)
FOIL SIDE
o
o
~.OU.T
LO
LO
U
o
Cl
~
.-.
•
N
o
o
II--.------loo-----~.l
( 3.93'1)
COMPONENTS LAYOUT
o
o
NEC t-lPC I 028H
--r-~~~~~~Ak~:;:b2
330Q.
FRONT
....
END
0-1-+----1--_ AF OUTPUT
Oet.Coll
o
o
GND
CF: Ceramic Filter
SFE10.7 MA (Red)
MURATA CO. made
or equivalent
Tr: 2SC1674
2SC1675
DETCOIL DATA
4
pin 5
0
2
0
Pin6
78
0
TYPE TKACA-17473Z
TaKa INC., made
fO= 10.7 MHz
C=22 pF
Q u =50
BIPOLAR ANALOG INTEGRATED CIRCUIT
I1PC1200V
SUPER LOW NOISE FM-IF AMPLIFIER
WITH QUADRATURE DETECTOR
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCR IPTION
The pPC1200V, a monolithic integrated circuit, is a FM-I F amplifier with a quadrature detector. FM interstation
noise and lateral recovered audio signal can be extremely reduced by the new developed circuit.
The IC, pPC1200V, enables the best use of an FM noise canceller section, because it does not affect the SIN at
low input level.
Outline is a new developed 15-lead Vertical Dual In-Line Plastic Package (V-DIP), so that it is suitable for use in
automotive radio receivers, where small mounting space is required.
FEATURES
• Low undesirable noise level : - 60 dB
• Very low lateral uncomfortable sound either upper or lower from the tuning point.
• Capability for effective use of FM noise canceller.
o Occupation of minimum area in P.C. Board.
o Easy to handle because of its V-D IP construction.
o Free of mismounting in P.C. Board due to its lead formation.
o Wide range of power supplies : 7 to 12 V
PACKAGE DIMENSION (in millimeters)
2.8±0.2
195 MAX
~
'I
r
~
~
xx
xc:t: c:t:x c:t:c:t:
::E ::E ::E::E
MARKING
\D CY) O"!r-:
1 2 3 4 5 6 7 8 910111213141" <.006 :::~
i
i
I
.....
1
1
I
I
2.54
I--
2.54
I----
0.6 MAX.
II
~ 1~
~
17.78
CONNECTION DIAGRAM
Pin No.
Electrical Connection
1
3
5
BYPASS
7
9
GND
Pin No.
Electrical Connection
BYPASS
2
4
BYPASS
6
IF2 INPUT
BYPASS
8
GND
11
N.S. CONTROL
13
15
AUDIO OUTPUT
10
12
14
IFl INPUT
IFl OUTPUT
IF2 OUTPUT
DETECTOR INPUT
BYPASS
VCC
79
jlPC1200V
BLOCK DIAGRAM (Top View)
EQUIVALENT CIRCUIT
r----------
I
I
Vee
I
I
I
I
I
I
I
OUTPUT
I
IF INPUT 0--4
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
15
V
Vi
3
V p _p
Package Dissipation at Ta = 75°C
Pd
310
mW
Operating Temperature
Topt
- 30 to 75
°c
Storage Temperature
Tstg
-40 to 125
°c
10
V
Supply Voltage
Vcc
Input Voltage
RECOMMENDED OPERATING CONDITIONS (Ta=25 °C)
Operating Supply Voltage
Vcc
Supply Voltage Range
VCC
Operating Ambient Temperature
Ta
7 to 12
V
-30 to 75
°c
ELECTRICAL CHARACTERISTICS (Ta = 25°C, VCC = 10 V, f = 10.7 MHz, fmod. = 400 Hz, DEV. =±22.5 kHz)
CHARACTER ISTIC
Circuit Current
80
SYMBOL
ICC
Limi:ting Sensitivity (1)
Vi(lim) 1
Recovered Audio Voltage
Vo
MIN.
TYP.
MAX.
UNIT
12
19
25
mA
110
47
53
dBJ,LV
150
200
mVr.m.s.
TEST CONDITIONS
Vi =0 dBJ,LV
-3 dB point, VR = 0
n, SW: ON
Vi =100 dBJ,LV
AM Rejection
AMR
45
dB
Vi =100 dBJ,LV, AM: f mo d.=400 Hz, m=30 %
Signal-to-Noise Ratio
SIN
67
dB
Vi =100 dBJ,LV
Total Harmonic Distortion
T.H.D.
0.1
Limiting Sensitivity (2)
Vj(lim)2
50
0.5
%
dBJ,LV
Vi =100 dBJ,LV
-3 dB point, VR=5.1 kil,SW : OFF
,uPC1200V
TEST CI RCUIT
T
IF~'NPUT
0.02:"F
S.G.
U1
or-..
RG=75
VCC
AUDIO OUTPUT
AC Voltmeter and
Distortion Meter.
C. F. : Ceramic Filter
SFEI0.7MA (MURATA CO.)
T
154AC41109Z (TaKa INC.)
fo= 10.7 MHz, Qu= 110
C =82 pF
TYPICAL CHARACTERISTICS
Vo, T.H.D. vs.
Vo, AMR, T.H.D. vs. Vi
(D
'0
I
~ 0.8
I
c
o
0.6
0.4
I
I
ci
:C
r-:
7
[7
(D_-40
'0
I
'iii
f-
,r\
~-20
:::E
q::
o
.&-60
.8
~
\
\
\
Vee =10 V
f
=10.7 MHz
f MOD =400 Hz
Dev. = ± 22.5 kHz
-.......- f""...
I
o
~
E
I
c.
1.0
20
40
60
80
Vi-IF Input Voltage-dB,uV
100
120
400
'6
::J
q::
0.5
I
0
200
~
ci
:C
r-:
0
0
~
0
0
I
-------- ----- T.H.D.
600
Vee =10
f
=10.7 MHz
fMOD =400 Hz
=100 dBJlV
Vi
~
«l
'0
Noise
E
~
E
u
'c0
f-
:::>
« -80
1.5
(/)
'iii
\
0
o
'6
iii
Ci
I
AMR
\
\
../
:::>
o
o
\
I
c
0
:e
\
\
I
:::>
0.2
~
Signal
0
0::
«l
'0
~
'0)
I
u
'c
E
0
0::
t
~
(5
c
~f
800
2.0
20
40
±Af-
60
80
100
Modutaticifl - kHz
81
,uPC1200V
vaDe vs.
Vee=10V
0
co
"'0
I
c~o~
(75 Jls)
-5
::l
0
I
C=6800 pF
\ . (50 Jls)
\\
~
.e0
'6
-10
I
0
-15 Vee =10 V
=10.7 MHz
f
M = ±22.5 kHz
Vi =100 dBJlV
-20
10
30
100
~
>
I
llD
'0
>
::l
.e::l
o
U
Q
.k
3 k
10 k
4r---~-----+----~----~--~~~~+-~--~--~
I
g
\\
300
6r---~--~~~~-r----~----+-----+-----~--~
Q)
2
\~
::l
«
~
o
>
3~
30 k
-0.4
100 k
__
~
____
-0.3
~
____
-0.2
Vo, ICC, T.H.D., Vi (lim) vs.
70
2.0
co
~
I
c:
~
~
c:
200
I
/
o
60
Q)
en
~ 1.5 ~ 15 >150
E
ti
I
I
o
C
u
llD
c:
~ 50
:.:::i
I
~
20
'co
E
1.0
ro
:r:
t
::l
U
~
.e::l
10 0100
I
/
/
,'(vI-a) I
/
/
/
Va
70
-
Vi(lim)1
en
llD
'c0
50
:.:::i
!
8
I
I
I
10
12
14
Vee - Supply Voltage - V
~
40
15
I
____
~
____
0.1
~
____
0.2
__
~
0.4
200
~
.e-
t
::l
::l
1.0
u 10
:r:
'5
>
E
0
0
100
'6
=10.7 MHz
fMOD =400 Hz
fl.f =±22.5 kHz
::l
"iii
t>
C3
«
I
0 0.5
:i
u
~
I
0
!:)
50
~
16
T.H.O. (Vj=100 dBJlV)
;L
0
0
0
-30
0
25
50
Ta -Ambient Temperature -
82
~
0.3
I
c
~
I
THO. (Vj=l00 dB.uV)
E
ro
«
E
u
c:
o
1.5
0
'E
f
=10.7 MHz
fMOO=400 Hz
± ±22.5 kHz
~f
c:
0
:;::
0
:;::
10.5
20
2.0
ti
Q)
-
o
I
~
c:
Vi.(lim)2
' ..."",
.......
~
~
co
"'0 60
'5
~
lo
----
I
Z.
~ .............
____
VO , ICC, T.H.D., Vi (lim) vs. Ta
I(Vj=100 dBJlV)
"iii
~ 40
Vee
--
/'-
~
-0.1
10.7 ±~f -Frequency - MHz
fMOD - Modulation Frequency - Hz
"'0
ll.f
75
"C
j.lPC1200V
TYPICAL APPLICATION
T
C.F.
T
FIE
SFElO.7MA (MURATA Co.)
154AC41109Z (TaKa INC.)
DMA - 040 (SANKEN ELE. LTD.)
GAIN 33±3 dB
NF
5 dBMAX.
88-108 MHz
f
• 75 J.l s de'emphasis
AUDIO
')UTPUT
The procedure below should be carefully followed,
in order to get the best use of J..LPC1200V.
1. Limiting sensitivity should be 5 to 10 dBJ..LV
2. F M TUN ER should have Noise Figure as low as possible.
3. VR (connected with pin~11) should be adjusted until the
optimum point of low lateral sound and high sensitivity
is reached.
TYPICAL PERFORMANCE with complementary stages (Ref. Application Circuit)
AUDIO OUTPUT vs. INPUT VOLTAGE
Signal
O~----~~~,-,-+-------~------~------~------~------~
m -20
"0
Vee
f
fmod.
Oev.
I
:J
B:::l
0
0
'6
=10 V
=98 MHz
=400 Hz
= ± 22.5 kHz
-40
:::l
«
I
0
~
-60
Noise
-80
-20
0
20
40
Vi-Input
60
80
100
120
oltage - dB J.l V
83
,uPC1200V
AUDIO OUTPUT vs. CARRIER FREQUENCY
Vee =10 V
+10
f
=98 MHz
f mo d.=400 Hz
Dev.
±22.5 kHz
Vi
=40 dBJlV
=
o
-10
CD
"0
1::J
~
0
VR=
0 kO
0
-20
:0
::J
«
I
~
-30
-40
-0.4
-0.3
-0.2
-0.1
fc
o
98±~f-earrier
+0.4
Frequency-MHz
COMPONENT LAYOUT FOR P.C. ASSEMBLY (Copper side)
IF INPUT Vee used for FM Tuner
o
...... OUT
----I_~
AUDIO
OUTPUT
o
84
NEe
JLPC1200 V
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1245V
FM IF SYSTEM WITH DIFFERENTIAL PEAK DETECTOR
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The pPC1245V is a monolithic integrated circuit that provides all the functions of an FM-I F system. It includes a
three-stage I F amplifier/limiter configuration with level detectors for each stage, a differential peak detector, and
an audio amplifier that features a muting (squelch) circuit. It also includes desirable features such as AGC for the
R F tuner, an AFC drive circuit, an output signal to drive a tuning meter and/or provides stereo switching logic, qnd
a station detector that provides a stop signal for search control in Electronically Tuned Radio. The pPC1245V is
suitable for use in automotive radio receivers. Outline is 19 leads Vertical Dual In-Line Package. (V-DIP).
FEATURES
•
High S+N/N ratio: 67 dB TYP.
•
Low distortion with single tune coil: 0.1 % TYP.
•
Soft muting circuit
o Programmable muting threshold and attenuation level
•
Programmable AGC voltage and threshold for R F amplifier
•
Programmable deviation where muting occurs and stop signal width
o Reduction of the occupation of mounting area in P.C. Board and hand-insertion time, due to the external shape
of the V-DIP.
PACKAGE DIMENSIONS (in millimeters)
25.5 MAX.
x x x x
c(
MARKING
c(
c(
c(
::E
::E ::E
:::E
LO
N
00
cd
8
00
~ ;!
1 .2 3 4 5 6 7 8 9 10111213141516171819
I
III
I
2.54
r---
2.54
I--
0.6 MAX.
22.86
0.35
1
2.54
I--
85
IlPC1245V
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Supply Voltage
VCC
Input Voltage
VI
16
V
3.0
430
mW
Package Dissipation (Ta=75 °C)
Po
Operating Temperature
T opt
Storage Temperature
Tstg
-30 to
-40 to
VCC
7.0
V
+75
+125
°c
°c
RECOMMENDED OPERATING CONDITION
Supply Voltage Range
to 15
V
ELECTRICAL CHARACTERISTICS (Ta=25 °C, Vcc=10 V, f=10.7 MHz, fMOD =400 Hz, .1f=±22.5 kHz)
CHARACTERISTIC
Supply Current
Recovered AF Voltage
SYMBOL
ICC
MIN.
12
TYP.
MAX.
18
25
mA
No Signal
VOAF
130
mVr.m.s.
Vi(limit) 1
44
dB,uV
V o =VoAF-3 dB
Vi (limit) 2
50
dB~N
_
R3=22 kn
Vo -VoAF-3 dB, Mute ON, R8=5.6 kn
Limiting Sensitivity
Vi=80 dBl-tV
Total Harmonic Distortion
T.H.D.
0.1
%
Vi=80 dB,uV
Signal to Noise Ratio
SIN
67
dB
Vi=80 dB,uV
AM Rejection Ratio
AMR
42
dB
Vi=80 dB,uV,
AM: 400 Hz, 30 % mod
VSl
0
V
Vi=O dB,uV, R2=4.7 kn
VS2
1.0
V
Vi=60 dB,uV, R2=4.7 kn
VS3
5.3
V
Vi= 100 dB,uV, R2=4.7 kn
VAGC1
9.0
V
Vi=O dB,uV, V16=3.0 V
Vi=100 dB,uV, V16=3.0 V
Vi=80 dBJ.N
Signal Meter
Output Voltage
AGC Output
8S
TEST CONDITION
UNIT
0.5
VAGC2
0.1
V
AFC Output
VAFC
5.2
V
Stop Signal Width
BWSD
100
kHz
Vi=80 dB,uV, R5=5.6 kn
V SD = 5 V, Rg=3.3 kn
,uPC1245V
BLOCK DIAGRAM
r---+--"VVIr----.-......._
VCC D--+-----,
BIAS
AFC OUTPUT
~f
AUDIO
DETECTOR
AMPLIFIER
AUDIO
OUTPUT
+
I
SOFTL.P.F.
MUTE.
SENS.
ADJ.
SIGNAL
METER
OUTPUT
AGC VCC
OUT.
MUTING
AGC
MUTE
SENS. ATT.
ADJ.
ADJ.
SO OUTPUT
CONECTION DIAGRAM
Pin No.
1
3
5
Electrical Connection
Pin No.
Electrical Connection
VCC
2
AGC Output
Signal Meter Output
4
Bypass
Mute Sensitivity Adj.
6
IF Input
7
IF Bypass
8
IF Bypass
9
GND
10
GND
11
Detector Input (+)
12
Reference Voltage
13
Detector Input (-)
14
AFC Output
15
Bypass
16
AGC Sensitivity Adj.
17
Mute Att. Adj.
18
Audio Output
19
SO Output
87
j.lPC1245V
TEST CIRCUIT
Vcc= 10 V
.022 pF 300
AFC Output
AGC Output
Q
~
G
r-t---Ef--U
g
to AC Voltmeter
& Distortion Meter
RG=
50 Q
VCC
Signal Meter
Output
COIL DATA
Coil: 119ACS-14891Z (TaKa)
Type No.
119ACS-14891Z(TOKO INC.)
CD-@)
21T
Ct=22 pF
Q u =90 MIN.
(Bottom View)
TYPICAL PERFORMANCE CHARACTERISTICS (Ta=25 °C)
Va, Noise, AMR, T.H.D.
VS_
vi
Vo
o·r---------------------~--------------------~-----~~~--~--------~--------_+--------~
VCC=10 V
f=10.7 MHz
fmod=400 Hz
6f=±22.5 kHz
-20
CD
:g.
c:i
:x:t-=
~
::E
c(
Z
6
-40
~
-60r---------------------~------------------4-------------------------~~~----~--------------_+-----------------~
-80~
o
________
~
20
________
~
__________
40
~
________
60
Vi (dBpV)
aa
~
80
________
~--------~
100
120
,uPC1245V
Vo, !::,. V AFC, VSD VS.!::" f
1.0
0
10
/
\ /
-2
-4
8
0.5
-6
-8
6
~
(.)
u..
~
~
0
CD
.:g
0
en
0
>
:t
Vi(limit)2
co
.:g
j~
:::::.
f 10.7 MHz
fmod=400 Hz
Af= ±22.5 kHz
- ---
~
50
S
(.)
10
9
;r
45
5
~,
§
0.2
Vi(limit)l
.....
I
c:i
:I:
t-
40
o
T.H.O. (Vi=80 dBJ.lV)
0.1
~--
o
6
8
12
10
14
---16
Vee (V)
89
,uPC1245V
vo,T.H.D. vs. ~f
600r----------r----------~~----------~--------~
500
VCC=10 V
f=10.7 MHz
fmod=400 Hz
Vj=80 dBJlV
400
vi
E
0.6
~
.5
300
0
~
0.4
200
0.2
100
~
ci
:i
...,:
o
22.5
75
50
100
Af (kHz)
Vs, VAGe, VSD vs. vi
10
VCC=10 V
f=10.7 MHz
8
VSO"
~
VAGC
6
0
en
>
U
~
-§-
en
>
4
I
/'t
2
o
20
~
40
V
/
80
60
Vi (dBIlV)
90
/.
100
120
jlPC1245V
TYPICAL APPLICATION
Vcc
RI03
100 Q
-JVV~--~-t
i
RIOI
100 Q CF
IF Input Q-Vtk----,
_.
.L
DOo
I
......
~
LO
o
VREF
~
AFC Output
CIOI
.022. F
!
....
0
a::
N
~
Cl4
a::
Audio Output
AGC Output 0 - -...............- - - - ,
....
a::
jlPC1245V
VCC
10 V
N
U
~
Coil:
Ceramic filter:
Q1 :
Q2:
C13:
*
Vcc
119AC5-l489l Z (TaKa) or quivalent
SFE10.7MS2 (MURATA) or quivalent
2SC1675, 2SC1674 or quivalent
2SC945 or quivalent
0.01 ",F 75 ",5 deempha5i5
91
tLPC1245V
COMPONENT LAYOUT FOR P.W. ASSEMBLY ( Copper Side)
IF Input O--+---+-
pPC1245V
92
c=)
BIPOLAR ANALOG INTEGRATED CIRCUIT
J-lPC587C2
FM MULTIPLEX STEREO DEMODULATOR
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTION
The ,uPC587C2 is a silicon monolithic integrated circuit designed for FM multiplex stereo demodulator applications in FM stereo radio receivers using phase locked loop CP.L.L.) techniques.
The device contains a demodulator system, a voltage controlled oscillator, phase detectors, low
pass filters, dividers and a D.C. amplifier.
It also includes a stereo-monaural switching circuit and a driver circuit for a stereo indicator lamp.
The features available in the device make possible a system delivering high fidelity sound within
the cost restrains of inexpensive stereo receivers.
FEATURES
• No coil necessary, all tuning performed with single potentiometer.
o Automatic stereo/monaural swi tching.
• Wide supply operating voltage range: Vcc=7 to 16V.
• Low distortion at monaural operation: T.H.D. = 0.07% TYP. at f= 1kHz, Vin=300mV
• Replaceable to the ,uPC 1026C
BLOCK DIAGRAM
V.C.O.
CONTROL
L.P.F.
L.P.F.
COMPOSITE
INPUT
AUDIO
AMP
OUTPUT
1
POWER
SUPPLY
PHASE
DETECTOR
INPUT
19kHz
MONITOR
OUTPUT
4
5
LEFT
OUTPUT
RIGHT
OUTPUT
L.P.F.
L.P.F.
LAMP
DRIVER
93
jlPC587C2
PACKAGE DIMENSIONS AND CONNECTION DIAGRAM (Top
View)
19.4MAX.
(0.76MAX.)
12
Rl
(RO.04)
2.54
(0.100)
_-+-+++-_12....;(0.047)
__
0 _.
5 ±0.1
_-t-t--:(0.02)
Pin No.
94
Electrical Connections
Pin No.
7.62
U-~----~~
0.25±~g:~5
__
~
(0.300)
(0.010)
Electrical Connections
1
POWER SUPPLY (Vee)
8
L.P.F.
2
COM POSITE INPUT
9
L.P.F.
3
AUDIO AMP. OUTPUT
10
19kHz MONITOR OUTPUT
4
LEFT CHANNEL OUTPUT
11
PHASE DETECTOR INPUT
5
RIGHT CHANNEL OUTPUT
12
L.P.F.
6
LAMP DRIVER
13
L.P.F.
7
GND.
14
V.C.O. CONTROL
EQUIVALENT CIRCUIT
POWER SUPPLY (Vee)
Q1
PHASE
COMPOSITE AUDIO AMP. DETECTOR
INPUT
OUTPUT
INPUT L.P.F. L.P.F.
20
30
0 11
13 0 0 12
A'uri U
V.C.O. CONTROL
;:>14
~
I
~f
00
I
R15 I Rl~v
R13
.LAA1~012
R2
J~
r
~r-~--~-
A"
013(
019 IR21~
A"
R24
A"f
r~
A,,'
I
tD1
018 t...J
1036
R23
*02
R 14
...
'VVV
D4t
R6
yD5
t
R17
017.)~
R1S<:
~
Rl~~
111033
0341111037
038
~
~R48
R58
R49
R59
~
RIGHT OUTPUT 5
LEFT OUT PUT
R60
O)--+----+-----~
4 0>---+---+-.......-----,
051
B.~3~
R71
058
r
• .,)059
R69
0'47
)10
19kHz
R70
·VVV
R56
R50
IR51
050
;:t------J
R64
.,.,
~
R61~
R!i2f
MONITOR OUTPUT
('")
en
(X)
L.P.F. 8 6
9 L.P.F.
06
STEREO INDICATOR
LAMP.
CD
01
-...J
('")
N
p,PC587C2
ABSOLUTE MAXIMUM RATINGS (Ta=25"c)
Supply Voltage
Vee
16V
Paokage Dissipation
(Ta=75"C )
Lamp Driver Current (Pin 6)
Po
350mW
100mA
IL
Operating Temperature
Storage Temperature
-20 to +75"C
-40 to + 125"C
Topt
Tstg
RECOMMENDED CONDITIONS (Ta=25"c)
Operating Supply Voltage
Supply Voltage Range
Vee
10V
7 to 16V
Operating Ambient Temperature
Ta
-20 to +75"C
ELECTRICAL CHARACTERISTICS
(Ta=25"c, Vcc= IOV, Vin=300mV
CHARACTERISTIC
SYMBOL
Circuit Current
Icc
Input Impedance
Zi
MIN.
7
(CO~~~~ite = I~)'
TYP.
MAX.
UNIT
13
18
mA
f= I kHz, RL=3.9kn)
TEST CONDITIONS
Quiescent
50
kQ
30
40
dB
f= 100Hz, Vin (Pilot).. =30mV
35
45
dB
f= 1kHz, Vin (Pilot) =30mV
30
40
dB
f = 10kHz, Vin (Pilot) =30mV
-9
-6
dB
Monaural Input, Vin (L+R) =300mV
Ch.B.
-1.5
0
1.5
dB
Monaural Input, Vin (L+R) =300mV
Ch.B.
-1.5
0
1.5
dB
Stereo Input, Vin (Pilot) =30mV
0.07
0.5
%
Monaural Input, Vin (L+R) =300mV
0.15
0.5
%
Stereo Inpu.t, Vin (Pilot) =30mV
12
16
20
mV
Pilot Level
3
6
9
dB
Pilot Level
± 1.5
±3
%
Vin (Pilot) =30mV
19kHz Rej.
35
dB
19kHz, Vin (Pilot) =30mV
38kHz Rej.
45
dB
38kHz, Vin (Pilot) =30mV
SCA Rejection
SCA Rej.
70
dB
Pilot
Composite
Maximum Input Level
Vi
1
Vrms
Stereo Channel Separation
Voltage Gain
Sep.
Au
Channel Balance
Total Harmonic Distortion
Lamp Indicator Input Level
T.H.D.
LAMP ON
I
Lamp Hysteresis
Capture Range
C.R.
Ultrasonic Frequency Rejection
96
0.7
SCA
1
10' Composite
Monaural Input, T.H.D.= 1%
1
10
J1,PC587C2
TEST CIRCUIT
19kHz MONITOR
16kQ
Potentiometer
l.L.
::t
l"-
v
o
o
+
INPUT
10.uF
STEREO INDICATOR LAMP
A
1---+-~... Vee
Icc
~_-+-_.}-J~.J-1-H--O RIGHT CHANNEL OUTPUT
38kHz B.E.F.
BL-13 (KORIN LAB.)
}-+---4I....--t:i--(1 LEFT CHANNEL OUTPUT
1. Use'a polystylene capacitor to the 470pF capacitor connected pin 14 for temperature compensation
to V.C.O.
2. Radj 1 and Radj 2 should be set the voltage gain between the output" terminal of t"he IC and
the output terminal of the S.E.F. is OdS.
3. For tuning the V.C.O. perform with the 5k Q potentiometer connected pin 14 by reading a frequency
of 19kHz at Pin 10.
97
j1PC587C2
TYPICAL CHARACTERISTICS (Ta=25'C)
VOLTAGE GAIN
vs. SUPPLY VOLTAGE (Monaural)
CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
25
5
4
0IdB}-6 dB
Quiescent
3
20
«
co
E
"0
1
f=l kHz
-
2
1
c
c
~
15
-
~
o
"~
.,' ~
10
~
Q)
OJ
0
co
~ -1
>
6
""
I" -2
«
1
o
52
-3
5
-4
o
-5
6
8
10
12
6
16
14
8
CHANNEL BALANCE
vs. SUPPLY VOLTAGE (Monaural)
f=l kHz
Vin(L+R) I--=300mV
2
1
1
Cii
0
co
co
1
§
(L-R)
gCD
.c
§co
cri
Right
40
-
-
~
-
f=l kHz
Vin (pilotl=30mV
30
-
20
1
g.
-5
10
Cf)
o
-6
6
10
12
14
Vee-Supply Voltage-V
8
60
co 50
"0
1- -
1
c
o
-- J;E!!t
Right
1---
--
8
6
16
CHANNEL SEPARATION
vs. PILOT INPUT LEVEL
10
12
14
Vee-Supply Voltage-V
16
FREE RUN FREQUENCY CHANGE
vs. SUPPLY VOLTAGE
+300
JVee=10V
I
f----
f=l kHz
f----
----~- ~--
I
N
Q)
co
.c
co
m
a.
+200
1
OJ
C
"':: 40
+ 100
0
>-
o
30
~
0
..
~
g (19kHz)
CD
c
c
It
co
20
c
-100
~
1
a:
c:i.
CD
Cf)
Le!!,
o
g-4
c3
I-
Cf)
1 -3
~
-
.~
-2
o
I"~~
"0
CD -1
c
c
\
50
cD
co
~
16
60
3
~
c
14
12
CHANNEL SEPARATION
vs. SUPPLY VOLTAGE
4
~
10
Vee-Supply Voltage-V
Vee-Supply Voltage-V
CD
10
~
-200
1
o
a
S8
<]
20
40
60
80
Vi(pilotl-Pilot Input Level-mV
100
-300
6
8
10
12
14
Vee-Supply Voltage-V
16
jlPC587C2
VOLTAGE GAIN
vs. FREQUENCY (Monaural)
CHANNEL SEPARATION
vs. FREQUENCY
4
60
2
(D
-c
I
c
.g
m
g-
0
50
C/)
-c
\
/
40
I
c
cti
~
-4
",
i\
-6
~
-8
I:. -10
I
c:i.
Vcc= 10V
Vin (pilot) =30mV
Q)
C/)
~
2
I
30
-2
<:)
(jj
c
c
ct:I
.c
0
...........
(D
ct:I
20
10
«
'\
-12
-14
-16
0.01 0.03
0.1
3
0.3
10
30
0.01 0.03
0.1
0.3
3
10
30
f -Frequency-kHz
f-Frequency-kHz
TYPICAL APPLICATION
Vcc=10V
Vin=300
mV
OdB=
6dB
19kHz MONITOR
F : 38kHz BAND
ELIMINATION FILTER
B3EN0102
(MURATA CO.)
Ra 16kQ
u..Co
a
r~
o
INPUT
C3
+
STEREO INDICOTOR LAMP.
lOpF '--____~------__- - J
~--------~~+-~~~~~~~+-----------------------+-~Vcc
LEFT CHANNEL OUTPUT
RIGHT CHANNEL OUTPUT
99
pPC587C2
TYPICAL PRINTED CIRCUIT BOARD PATTERN
PRINTED CIRCUIT LAYOUT
o
,uP058702
Rl=500k-Q
R2=500kQ
R3=3.9kQ
R4=3.9kQ
R5=100Q
R6=100kQ
R7= 1kQ
Ra=16kQ
R9=5kQ
Potentiometer
100
COMPONENT LAYOUT (Bottom View)
•
_ _~ ,uPC58702
o
01=470pF
02= 100,uF
03= 10,uF
04=4.7,uF
05=4.7,uF
06=O.Ol,uF
07=O.01,uF
Oa=O.22,uF
09=O.47,uF
010 =O.22,uF
011 =O.047,uF
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1026C
FM MULTIPLEX STEREO DEMODULATOR
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTION
The ,uPC1026C is a silicon monolithic integrated circuit designed for FM multiplex stereo demodulator applications in FM stereo radio receivers using phase locked loop (p L L ) techniques.
The device contains a demodulator system, a voltage· controlled oscillator, phase detectors, low
pass filters, dividers and a D.C. amplifier.
It also includes a stereo-monaural switching circuit and a driver circuit for a stereo indicator lamp.
The features available in the device make possible a system delivering high fidelity sound within
the cost restrains of inexpensive stereo receivers.
FEATURES
• No coil necessary, all tuning performed with single potentiometer.
• Automatic stereo/monaural switching.
• Wide supply operating voltage range : V cc= 7 to 16V
• High Voltage gain
: Av= -1.5dB (RL=3.9kQ)
• Replaceable to the ,u PC587C2.
BLOCK DIAGRAM
v.c.o.
CONTROL
L.P.F.
1
2
POWER
SUPPLY
COMPOSITE
INPUT
L.P.F.
PHASE
DETECTOR
INPUT
19kHz
MONITOR
OUTPUT
L.P.F.
L.P.F.
RIGHT
OUTPUT
LAMP
DRIVER
GND
4
AUDI.O
AMP.
OUTPUT
LEFT
OUTPUT
101
,uPC1026C
PACKAGE DIMENSIONS in millimeters (inches)
19.4MAX.
(0.76MAX.)
14
13
12
11
10
Rl
(RO.04)
LO
LO
(Os
.N
1.2(0.047)
--+-+++--
_--+-f--:-0 _.5 ±0.1 0.25±~g:~5
(0.02)
7.62
(0.300)
(0.010)
CONNECTION DIAGRAM
Pin No.
102
Electrical Connections
Pin No.
Electrical Connections
1
POWER SUPPLY (Vee)
8
L.P.F.
2
COMPOSITE INPUT
9
L.P.F.
3
AUDIO AMP. OUTPUT
10
19kHz MONITOR OUTPUT
4
LEFT CHANNEL OUTPUT
11
PHASE DETECTOR INPUT
5
RIGHT CHANNEL OUTPUT
12
L.P.F.
6
LAMP DRIVER
13
L.P.F.
7
GND.
14
V.C.O. CONTROL
EQUIVALENT CIRCUIT
POWER SUPPLY (Vee)
PHASE
COMPOSITE AUDIO AMP. DETECTOR
INPUT
OUTPUT
INPUT L.P.F. L.P.F.
21""\
')1
Rl
Dr
R
4
C1
R2
0
R5
03
f-
~
5
1-
>
R.'
7.
14
:>
Drr
o~"
R6
R25
R22
oJ< • •
-R 15
R l~V
V
~
0,,(
019 R21 ~
>
f-'vVv- ~23
025
~
..-
018
011
R 12
V
R14
016
017
V
~,D5
R17
)07
O~,
34 R32
R33
R36
: R42
R37:
R43 :-
R44
~
~
R39
R3S:
35
t--
031
I>-
028
~~"
R'~
R18
o29030
027
R 23
08
V
~ R29
t:=+ R31
).
R30
R
• R27
R28~
r----
R24
~' Yo"
R26
R 20
" ,"
0 4 ,~
R45
032
..-
R40
033
R41
....
034
035
036
R46
R47
P-
037
038
R57
>
~
~R48
R49 ~
'v
R58
R59
R60
RIGHT OUTPUT 5"
LEFT OUTPUT 4
r
OlQ
~ ~09
3
V.C.O. CONTROL
~12
~O
R8
H:04)-
~~02 R
GN
,J
°
03 ~~
~r 0 1
13~
(
,,11
~ .~R"
0,
>
31""\
049
~
'-'
M B
~
R55
R53
-
vv
045
I
..
R50
I
o,,~
o,,~
.B 54
R56
R69
")-r1
R63
°
R70
1.0
19kHz
MONITOR OUTPUl
0
"
R";"D,~~ R"~(
050)-056 057
R51
R52 e
059
lJ
R62
0 46
R71
058
Jo"
055
054~
R61'>
R66 e R6
1:::
."
R6
o
-'
I
P F
R (~
Q I
P F
(
6
STEREO INDICATOR
LAMP.
o
tAl
o
N
en
o
,uPC1026C
ABSOLUTE MAXIMUM RATINGS (Ta=25'C)
Supply Voltage
Vee
16V
Package Dissipation (Ta=75"C )
Po
350mW
Lamp Driver Current (Pin 6)
IL
100mA
Operating Temperature
Topt
-20 to +75"C
Storage Temperature
Tstg
-40 to + 125 "C
RECOMMENDED OPERATING CONDITIONS (Ta =25t)
Operating Supply Voltage
Vee
10V
Supply Voltage Range
7 to 16V
Ta
Operating Ambient Temperature
-20 to +75"C
ELECTRICAL CHARACTERISTICS
(Ta=25'C, Vcc= IOV, Vin=150mV
CHARACTERISTIC
SYMBOL
Circuit Current
Icc
Input Impedance
Zi
(CO~~~~ite= I~)'
MIN.
TYP.
MAX.
UNIT
7
13
18
mA
f= 1kHz, RL=3.9kQ)
TEST CONDITIONS
Quiescent
50
kQ
30
40
dB
f= 100Hz,
35
45
dB
f= 1kHz.
30
40
dB
f=10kHz,
Av
-4.5
-1.5
2.0
dB
Monaural Input.
Vin(L+R) = 150mV
Ch.B.
-1.5
0
1.5
dB
Monaural Input,
Vin(L+R) =150mV
Ch.B.
-1.5
0
1.5
dB
Stereo Input.
0.15
0.5
%
Monaural Input, Vin(L+ R) =150mV
0.15
0.5
%
Stereo Input, Vin (Pilot) = 15 mV
5
8
11
mV
Pilot Level
3
6
9
dB
Pilot Level
± 1.5
±3
%
Vin (Pilot) = 15 mV
19kHz Rej.
35
dB
19kHz,
Vin(Pilot) =15mV
38kHz Rej.
45
dB
38kHz.
Vin (Pilot) = 15mV
SCA Rejection
SCA Rej.
70
dB
Pilot
Composite
Maximum Input Level
Vi
0.6
Vr.m.s.
Stereo Channel Separation
Voltage Gain
Sep.
Vin(Pilot) =15mV
Vin(Pilot) =15mV
Vin (Pilot) =15 mV
Channel Balance
Total.Harmonic Distortion
Lamp Indicator Input Level
T.H.D.
LAMP ON
Lamp Hysteresis
Capture Range
Vin(Pilot) =15mV
C.R.
Ultrasonic Frequency Rejection
104
0.4
1
SCA
10' Composite
Monaural Input, T.H.D. = 1%
1
10
pPC1026C
TEST CIRCUIT
19kHz MONITOR
16kQ
Potentiometer
l.L.
:t
I'-
v
o
o
,uPC1026C (Top View)
+
INPUT
10pF
STEREO INDICAOR LAMP
A
t---+----t~ Vee
Icc
'--_-+_ _>:.t--....-~---u
RIGHT CHANNEL OUTPUT
38kHz B.E.F.
BL-13 (KaRIN LAB.)
o-i...--.---t;:I--() LEFT CHANNEL OUTPUT
1. Use a polystylene .capacitor to the 470pF capacitor connected pin 14 for temperature compensation
to V.C.O.
2. Radj 1 and Radj 2 should be set the voltage gain between the output terminal of the IC and
the output terminal of the S.E.F. is Od·S.
3. For tuning the V.C.O. perform with the
5~ Q
potentiometer connected pin 14 by reading a frequency
of 19kHz at Pin 10.
105
,uPC1026C
TYPICAL CHARACTERISTICS (Ta=25°C)
VOLTAGE GAIN
vs. SUPPLY VOLTAGE (Monaural)
CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
25
5
4
Quiescent
6,
-1
I", -2
-
o
~
30
Q)
g.
0
(19kHz)
o'" 20
~
c
-100
c
c
,
,......
=>
a:
ci.
(l)
(l)
10
~
,
0
o
:;
10
20
30
40
Vi(pilotl-Pilot Input Level-mV
106
10
12
14
Vee-Supply Voltage-V
Vce=10V I - -
Right
C
o
8
FREE RUN FREQUENCY CHANGE
vs. SUPPLY VOLTAGE
~ 40
(l)
-
30
I
g.
-5
(fJ
-
o
B-4
~
Right
(l)
~
cD
,
Le!!,
(fJ
-2
, -3
!D
-
40
c
(L-R)
ca'" 0
\
50
!D
!D
~
16
60
3
Q)
14
CHANNEL SEPARATION
vs. SUPPLY VOLTAGE
4
,
12
Vee-Supply Voltago-V
Vee-Supply Voltage-V
!g
-
2
15
=>
o
o
0' dB='-l.JdB
3
20
50
-200
-300
6
8
10
12
14
Vee-Supply Voltage-V
16
,uPC1026C
CHANNEL SEPARATION
vs. FREQUENCY
VOLTAGE GAIN
vs. FREQUENCY (Monaural)
4
60
CD
I
c
':?
50
IIR->L - I -
Q)
(J)
/
40
Q)
0)
a
Vcc= lOV
Vln (pol,,,) = 15 mV
20
",
OdB=
-1.5dB
-6
C1l
I
g
Vin=
150mV
'\
0
0
(J)
"-
c
,
30
............
-2
co -4
L -R
c.>
~
I
f\
Vcc= IOV
0
CD
u
~
0.
I
2
I I
u
-8
>
I
.;-10
\
-12
-14
-16
10
0.01 0.03
0.1
3
0.3
10
30
0.01 0.03
0.1
0.3
3
10
30
f -Frequency- kHz
f - Frequency - kHz
TYPICAL APPLICATION
19kHz MONITOR
F : 38kHz BAND
ELIMINATION FILTER
B3EN0102
(MURATA CO.)
Ra
16kQ
INPUT
STEREO INDICOTOR LAMP.
~--------~--~~----~~~--r-----------------------~~Vcc
F
F
Rl
500kQ
LEFT CHANNEL OUTPUT
RIGHT CHANNEL OUTPUT
107
,uPC1026C
TYPICAL PRINTED CIRCUIT BOARD PATTERN
PRINTED CIRCUIT LAYOUT
COMPONENT LAYOUT (Bottom View)
o
,uPC1026C
Rl=500kQ
R2=500kQ
R3=3.9kQ
R4=3.9kQ
R5= 100Q
R6=100kQ
R7=1kQ
R8= 16kQ
R9=5kQ
Potentiometer
loa
Cl=470pF
C2= 100,uF
C3= 10,uF
C4=4.7,uF
C5=4.7,uF
C6=O.01,uF
C7=O.01,uF
C8=O.22,uF
C9=0.47,uF
ClO =O.22,uF
Cll =O.047,uF
BIPOLAR ANALOG INTEGRATED CIRCUIT
p,PC1227V
FM MULTIPLEX STEREO DEMODULATOR
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRI PTION
The IlPC1227V is a silicon monolithic integrated circuit designed for FM multiplex stereo demodulator applications in
FM stereo radio receivers using phase locked loop (PLL) techniques.
The· device includes a variable blend facility that gives a smooth change from monaural to stereo reception. It also
includes independent separation adjustment for Land R channels, forced monaural and VCO stop functions. Outline is a
new developed 19-1ead Vertical Dual In-Line Plastic Package (V-DIP), so that it is suitable for use in auto'motive radio
receivers, where small mounting space is required.
FEATURES
•
•
•
•
•
•
•
•
•
•
No coil necessary, all tuning performed with a single potentiometer.
Automatic stereo/monaural switching.
High Voltage gain: Au =-0.6 dB (RL = 3.9 kUJ
Easy to handle because of its V-DIP construction
Reduction of the occupation of mounting area in P.C. Board and hand-insertion time, due·to the external shape of the
V-DIP.
Free of mismounting due to its lead formation.
Stereo noise reduction
White Noise reduction
Independent separation adjustment
Wide supply voltage range: Vee = 6 to 14 V
PACKAGE DIMENSIONS in millimeters
25.5 MAX.
x« x« x«
MARKING
1
2
I~
3 4
5
2.54
7
8
:::E:
LO
C\I
00
00
00
ci
c>i
.....
o:i
.....
.....
:::E:
9 10 11 12 13 14 15 16 17 18 19
i
I
I
I
...
~
6
x«
~
:::E:
-
...
2.54
0.6 MAX
22.86
.11.
0.35
-
2.54
109
,uPC1227V
ABSOLUTE MAXIMUM RATINGS (Ta
= 25°C)
Supply Voltage
16
430
VCC
Package Dissipation (Ta
= 75°C)
PD
Lamp Driver Current (Pin 9)
IL
Operating Temperature
T opt
Storage Temperature
Tstg
75
-30 to +75
-40 to + 125
RECOMMENDED OPERATING CONDITIONS (Ta = 25°C)
Operating Supply Voltage
VCC
8
Supply Voltage Range
VCC
6 to
14
Operating Ambient Temperature
Ta
-30 to
+75
ELECTRICAL CHARACTERISTICS
[Ta
= 25 ° C, VCC
=1-), f
= 8 V, vin = 300 mV (Pilot .
CHARACTE R ISTIC
Composite
SYMBOL
Circuit Current
ICC
Input Impedance
ZI
Stereo Channel Separation
Sep.
MIN.
12
10
= 1 kHz.
RL
TYP.
MAX.
UNIT
20
28
mA
= 3.9 kn]
TEST CONDITIONS
Quiescent
50
kn
35
45
dB
f = 100 Hz, Vin (Pilot) = 30 mV
40
55
dB
f = 1 kHz, Vin (Pilot) = 30 mV
dB
f = 10 kHz, Vin (Pilot) = 30 mV
Monaural input, Vin (L+R) = 300 mV
35
45
-3.5
-0.6
+2.5
dB
Ch.B.
-2
0
+2
dB
Monaural Input, Vin (L+R) = 300 mV
Ch.B.
-2
0
+2
dB
Stereo Input, Vin (Pilot) = 30 mV
0.05
0.3
%
Monaural Input, Vin (L+ R) = 300 mV
Stereo Input, Vin (Pilot! = 30 mV
--
Voltage Gain
Av
Channel Balance
Total Harmonic Distortion
T.H.D.
0.05
0.3
%
Lamp Indicator Input Level
LAMP ON
4
8
12
mV
Pilot Level
4
dB
Pilot Level
C.R.
±2
±4
%
Vin (Pilot) = 30 mV
19 kHz Rej.
35
dB
19 kHz, Vin (Pilot) = 30 mV
38 kHz Rej.
45
dB
38 kHz, Vin (Pilot) = 30 mV
SCA Rej.
70
dB
SCA
Pilot
1
=Composite 10, Composite
Monaural Input, T.H.D. = 1 %
Lamp Hysteresis
Oapture Range
Ultrasonic Frequency Rejection
SCA Rejection
Maximum Input Level
Vi
0.6
1.0
Vr.m.s.
Signal-to-Noise Ratio
SIN
70
80
dB
Forced Monaural Level
V mono
0.8
V
#8 terminal
VCO Stop Level
V stop
0.8
V
#8 terminal
dB
V 14 = 0.4 V
dB
V 14 = 1.0 V
Sep. C1
Stereo Channel Separation
Sep. C2
Voltage Gain
AvH
Sep. C3
110
3
0
17
40
55
-23.5
-19
-15
1
10
Monaural Input, Vin (L+ R) = 300 mV
dB
V 14 = 1.6 V
dB
V 14 =0.4V,f=10kHz
jLPC1227V
TEST CIRCUIT
19 kHz
MONITOR
FORCED
MONAURAL
VCO STOP
POL YSTYLENE CAPACITOR
LOW PASS FILTER: BL - 13 (KORIN LAB.)
*** Amp1 and, Amp2 should be set so that, the
voltage gain between the output terminal of the
IC and the output terminal of the LPF is 0 dB'
HCC
SNC
j.lPC1227V (Top View)
R SEP.
ADJ
STEREO
INDICATOR
VCC
330
3.3 k Q
Q
+
100 }.IF
(* *)
LEFT CHANNEL OUTPUT
BLOCK DIAGRAM
PRE
AMP.
P.D
OUTPUT INPUT LPF
7
VCC
VCO
~----------------~13~--~
3
COMPOSIT
SIGNAL
INPUT
LPF
LPF
2 19 kHz MONITOR
' - - - f - - + - - - - - - - - - { 9 LAMP DRIVER
151---------{
HI-CUT
COMPONENT
~--~14~--------~
L SEP. R SEP HIGH·CUT CONTROL
ADJ. ADJ.
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&
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VCO STOP
GND
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HCC
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IN
HIGH - CUT CONTROL
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&
STEREO NOISE
CONTROL
(SNC)
114
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1320C
FM MULTIPLEX STEREO DEMODULATOR
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTION
The IlPC1320C is FM stereo demodulator with utilize phase locked loop technology.
The device features excellent channel separation over a wide band of frequencies and a wide range of operating voltage with
low distortion.
It contains an automatic stereo-monaural switching circuit, a VCO mute circuit for FM/ AM radio application, a forced
monaural switching circuit and stereo indicator lamp driver.
FEATURES
•
Less external part; No coil
•
Wide operating voltage range; Vee
•
Wide dynamic range; Vin = 1 000 mVr.m.s. TYP.
•
Excellent channel separation maintained over wide frequency range (fixed or adjustable).
•
High voltage gain; Av = -0.8 dB
•
Containing an automatic stereo-monaural switching circuit, a forced monaural switching circuit and a '(CO mute
= 5.4 to
14 V
circuit for FM/AM radio application.
PACKAGE DEMENSIONS (Unit: mm)
Typical values unless
otherw i se noted.
0.6
115
,uPC1320C
ABSOLUTE MAXIMUM RATINGS (Ta
= 25°C)
Supply Voltage
VCC
14
Lamp Voltage (Pin 6)
VLAMP
18
Package Dissipation (Ta = 75°C)
Po
Lamp Driver Current (Pin 6)
IL
350
75
Operating Temperature
Topt
-30 to +75
Storage Temperature
Tstg
-40 to +125
RECOMMENDED OPERATING CONDITIONS (Ta
= 25°C)
Operating Supply Voltage
VCC
8
5.4 to
Supply Voltage Range
Operating Ambient Temperature
Ta
14
-30 to +75
ELECTRICAL CHARACTERISTICS
(Ta = 25°C, Vcc=
8
V, Vin = 350 mV
CHARACTERISTIC
SYMBOL
Circuit Current
ICC
Input Impedance
Zi
Stereo Channel Separation
Sap.
Output Voltage
Channel Balance
(cO~~o;site '" 16), f
MIN.
8
40
Va
250
Ch.B.
-2
Ch.B.
-2
TYP.
MAX.
UNIT
12
18
mA
TEST CONDITIONS
Quiescent
50
kS1
45
dB
f
55
dB
f
45
dB
0
+2
dB
= 100 Hz, Vin (Pilot) = 35 mV
= 1 kHz, Vin (Pilot) = 35 mV
f = 10 kHz, Vin (Pilot) = 35 mV
Monaural Input, Vin (L+R) = 350 mV
Monaural Input, Vin (L+R) = 350 mV
Stereo Input, Vin (Pilot) = 35 mV
0.1
0.5
%
Monaural Input, Vin (L+R) = 350 mV
Stereo Input, Vin (Pilot)
320
430
dB
0
+2
dB
Total Harmonic Distortion
T.H.D.
0.1
0.5
%
Lamp Indicator Input Level
LAMP ON
4
8
12
mV
4
dB
Pilot Level
C.R.
±2
±5
%
Vin (Pilot)
19 kHz Rej.
35
dB
19 kHz, Vin (Pilot) = 35 mV
38 kHz Rej.
45
dB
38 kHz, Vin (Pilot)
SCA Rejection
SCA Rej.
70
dB
SCA _ =-'Pilot
=_1_
10' Composite
10
Composite
1.0
Vr.m.s.
83
dB
Lamp Hysteresis
Capture Range
Ultrasonic Frequency Rejection
116
= 1 kHz, RL = 3.9 kn)
Maximum Input Level
Vi
Signal·to-Noise Ratio
SIN
Forced Monaural Level
V mono
0.8
V
VCO Stop Level
V stop
0.8
V
0.6
= 35 mV
Pilot Level
= 35 mV
= 35 mV
Monaural Input, T.H.D.
Vi
= 350 mV
=1 %
j.lPC1320C
TEST CIRCUIT
POLYSTYLENE CAPACITOR
LOW PASS FILTER: BL - 13 (KORIN LAB.)
Amp1 and, Amp2 should be set so that, the
voltage gain between the output terminal of the
IC and the output terminal of the LPF is 0 dB
19 kHz
MONITOR
sw
1
V
1\
FORCED MONAURAL
VCO STOP
Vee
3.9 kQ
RIGHT CHANNEL OUTPUT
-
+
C14
LEFT CHANNEL OUTPUT
BLOCK DIAGRAM
VCO
LPF
LPF
P.D
INPUT
19 kHz
MONITOR
LPF
LPF
FORCED MONAURAL
VCO STOP
VCO
76 kHz
VCO
MUTE
P.D:
F .D:
VCC
COMPOSIT
SIGNAL
INPUT
PRE
AMP.
OUTPUT
L-CH
OUTPUT
R-CH
OUTPUT
LAMP
DRIVER
GND
PHASE
DETECTOR
FREQUENCY
DIVIDER
SEPARATION
ADJUST
117
,uPC1320C
TYPICAL CHARACTERISTICS (Ta
= 25°C)
TOTAL HARMONIC DISTORTION, Rch. OUTPUT
LEVEL, CHANNEL BALANCE vs. SIGNAL INPUT
LEVEL
TOTAL HARMONIC DISTORTION vs.
FREQUENCY
2.4
~
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VCC=B V
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VOLTAGE
0
-4,<:°25
o
25
50
75
Ta- Ambient Temperature-'C
119
,uPC1320C
Components Layout for P.C. Assembly (Copper side)
NEe
Application Information
1. Separation Adjustment
Separation control is normally adjusted by a variable resistor connected to Pin 15.
A phase compensator, however, is recommended to use as show below when the variable resistor is not enough to provide
typical separation due to large IF phase delay.
from IF Stage - -...
2. Stereo-Monaural Switching
Applying voltage higher than 0.8 V to Pin 9 make ~PC1320C switch from stereo to monaural condition. The monaural
switching is also performed by keeping Pin. 11 grounded. (stereo operation is kept by Pin. 10 grounded.)
120
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1176C
FM NOISE CANCELLER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
pPC1176C, a monolithic integrated circuit, is an FM Noise Canceller for use in automotive radio receivers.
The incoming noise such as that from car ignition can be suppressed. Internally, buffer-amplifier, delay circuit, gate circuit, noise detector, control circuit for gate and stereo signal holding circuit are included.
FEATURES
o Effective pulsive noise suppression.
o Minimum distortion level due to the stereo signal holding circuit.
o Automatic change of the blanking time, according to noise intensity .
• Excellent response for highly repetitive noise.
BLOCK DIAGRAM (Top View)
Noise
Detector
Vee
Control Ci rcuit for Gate
121
,uPC1176C
PACKAGE DIMENSIONS (in millimeters)
19.4MAX.
---+]
R1
N
ci
+1
It>
It>
'"
O.5±O.1
ABSOLUTE MAXIMUM RATINGS (Ta=2SoC)
Supply Voltage
VCC
Package Dissipation
PO
Operating Temperature
T opt
Storage Temperature
T stg
-40 to +125
°c
15
V
350*
mW
-20 to +75
°c
*Ta= 75°C
ELECTRICAL CHARACTERISTICS (Ta = 2SoC, VCC = 10V)
CHARACTERISTIC
Circuit Current
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
ICC
13
16.5
23
mA
Vi =0
Voltage Gain
Av
-0.3
0.7
1.7
dB
Vi = 500mVr.m.s., f = 1 kHz
Blanking Time
TB
30
J.I.S
VT
40
mVp
Triggering Voltage
122
SYMBOL
Vi = 500mVp, f = 1 kHz, tw = llJ.s
f = 1 kHz, tw = 10IJ.s
TYPICAL APPLICATION CIRCUIT
Vee
I
lJ...
'+
330pF
Pulse
Shaping
Circuit
Noise
Detector
GND
IL
::2
('t")
('t")
INPUT
(to FM Det.)
Trigger
Circuit
C
. for Gate
antral ·
Circuit
-------------------
+
Buffer
Amp.
4.7 pF
Delay
Circuit
Vee
Schmitt
Noise
Control
Circuit
Gate
Circuit
Stereo
Signal
Holding
Output
Circuit
::2
"N
4.7kQ
+
4.7JlF
OUTPUT
(to MPX or Po·amp.)
lJ...
~
2kQ
1.5k5~
II
VR should be adjusted to maintain the
amplitude and frequency of the 38
kHz signal when the gate circuit is
turned off.
1::
"
()
-a
-a
-..J
0)
I\)
W
()
I\)
~
1:::
\J
Diagram of Components Mounted on a Printed-Circuit Board (Bottom View)
o
~
~
.......
m
o
4.7J1 F
OUTPUT
•
t;
r~~:·~::~,:.~: ~+ ~~==·:r:.-=~-::)\
OUTPUT
L \'q v
/.__. _. ,,_~.~,. _._.,~~__ l
rt
r-I'r-
fL-~-~~:WII {
'~-~200PF":"~'----
2kQ
\"c,. . lL.
\~'8~T
'_'VVV-7-f?~~:'-:';~~ --!
t .-- -
lkQ VR
INPUT
1.5kQ ~'~f
··TlL.--,~
NEe
BIPOLAR ANALOG INTEGRATED CIRCUIT
J-lPC1032H
DUAL LOW NOISE PREAMPLI FIER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The J.LPC1032H is a silicon monolithic integrated circuit designed for use as a 2 channel preamplifier for a car stereo
set. The device has features of low noise, high gain, high output voltage and wide supply volta~e range.
Especially, as an advanced production process is used, the device has an excellent feature of very low pulsive noise.
An internal voltage regulator circuit permits the J.LPC1032H to operate satisfactorily over wide variation of supply
voltage.
FEATURES
PACKAGE DIMENSIONS
19.5MAX.
(0.76M".)
in millimeters {inches}
o Two channel
_I
2.B±0.2
o
(0.11)
CI
(C 0.04)
o Wide supply voltage range
o Minimum number of external parts required
• Low noise, especially low pulsive noise
• SIP assures easy mounting on printed circuit board.
EOUIVALENT CIRCUIT
0.25
( 0.01)
I(g.~~il--:~-
CONNECTION DIAGRAM
INI
NFBI
OUT I
Vl'l'
GND
OUT2
NFB2
IN2
125
,uPC1032H
ABSOLUTE MAXIMUM RATINGS (Ta
= 2SoC)
Supply Voltage
VCC
Package Dissipation
PD
Operating Temperature
T opt
-20 to +75
Storage Temperature
T stg
-40 to +125
18
V
270*
*Ta =
RECOMMENDED CONDITIONS (Ta
mW
°c
°c
75°C
= 2SoC)
Operating Supply Voltage
VCC
13.2
Supply Voltage Range
VCC
V
8 to 17
V
Operating Ambient Temperature
-20 to +75
°c
Load impedance
10kil TYP.
ELECTRICAL CHARACTERISTICS (Ta
CHARACTERISTIC
= 2SoC, Vcc = 13.2V, f = 1 kHz, RL = 10 kil)
SYMBOL
MIN.
TYP.
MAX.
7
11.0
Circuit Current
ICC
Open Loop Voltage Gain
Avo
70
81
Voltage Gain
Av
33.5
35
1.1
1.7
50
100
Maximum Output Voltage
VOM
Total Harmonic Distortion
T.H.D.
Input Impedance
fj
Equivalent Input Noise Voltage
vnin
0.1
1.4
Cross Talk
-0.3
0
TEST CIRCUIT
35.5
kn
""Vr.m.s.
@
RG
dB
®
Vo
= 2.2kn, NAB~ 35dB
= 1V, (The other channel
dB
®
Vo
= 0.3V
dB
V
0.3
2.0
+0.3
TEST CONDITIONS
CD
CD
®
®
®
®
rnA
dB
-62
Channel Balance
UNIT
%
vin
Vo
Vo
=0
= 0.3V
= 0.3V, RNF = 1.8kn
T.H.D. = 1%,
Vo
= 0.3V,
NAB~35dB
NAB~
35dB
vin = 0, RG = 2.2kn)
TEST CIRCUITS
® Av Test Circuit
CD Icc, Avo Test Circuit
(for Ch. 1)
Vcc=13.2V
126
lOO"F
.----1_EI-+~~------ovcc= 13.2V
J,lPC1032H
@ VOM, T.H.D., rj Test Circuit
® Vnin Test Circuit
(for Ch. 1)
(for Ch. 1)
100!,F
100!1F
~_--t::1t-:-+~--------oVcc=
13,2V
r""_-"-+-""---o Vee = 13 ,2V
Flat Amp,
B,P,F,
Vn
Av(dB)(f= 1kHz)
vnin is calculated by vn and amp. gain (Av +40 dB).
External components of the IC are the same as the Test Circuit.3
® Cross Talk, Channel Balance Test Circuit
RL
10kQ
o---I::I-~>---<:
0 uti
0---'-1'1---.>---<: Out 2
RI.
I
Ok~l
External Components of the IC are the same as the Test Circuit
Cross talk Test Procedure
20 log Out2 /Out I
Switch Position
SW I ~2. SW 2 ~ 1
20 log Outl/Out2
Switch Position
SW I ~ 1. SW 2 ~ 2
Channel Balance Test Procedure
20 log Outl/Out2
Switch Position
SW I ~2. SW 2 ~2
(3.)
TYPICAL CHARACTERISTICS (Ta = 25°C)
OUTPUT VOLTAGE vs.
INPUT VOLTAGE
(Test Circuit
TOTAL HARMONIC DISTORTION vs.
OUTPUT VOLTAGE
®)
(Test Circuit
100
®)
10
50
~
g
~Ci
20
~
10
:>
~
0
'0
1
g,
0,5
>
c5
~
0,2
,;
"
100Hz
1 OkHz
f= 1kH>:",
0,5
:x::
~
0,2
~
0,1
~
~~
10kHZ,
1P OH Z
~
0, I
I
cl 0,05
~
0,0 5
'2
:x:
.
0,0 2
0,0 1
0,1 0,2 0,5
1= 1 kHz
~
1111
0,02
1
5
10 20
50 100 200 500 1000
Vin-Input Voltage- mVr.m,s,
0,01
0,01 0,02 0,05 0,1
0,2
0,5
J
III j
10
V o - Output Voltage- Vr,m,s,
127
,uPC1032H
TOTAL HARMONIC DISTORTION vs.
OUTPUT VOLTAGE
VOLTAGE GAIN vs. FREQUENCY
(Test ClrcuiteD,®)
(Tesl Circuit®)
120
10
~
!g
~
~
c
u
0g
~
:z:
b
0.5
~
lI
ci
0.05
~
a
60
<
'"z<
BV
<
~cl~~ 13.~V. : 7~'1
,
0.2
0.5
'""
Vo- Output Voltage- Vr.m.s.
.?-
t--..
--I'-- ....
40
~SAHI
"
20
o
10
10
20
50
I.B
~
1.4
>
1.2
~
"
1.0
E
O.B
')(
0.6
a
o
~
~
I
:0:
~
!g
.... k
....
';;j
CI
I. ....
..
~
60
"0
g
40
.
Q.
0
..~
20
0.2
20
30
50
70
100
CIRCUIT CURRENT, MAXIMUM OUTPUT VOLTAGE,
OPEN LOOP VOLTAGE GAIN AMBIENT TEMPERATURE
(Test CircuiteD, ®)
b
BO
E
';;j
CI
...
a'"
60
Q.
0
0
..
c:
I.B '--
16
:>
.
1.6
>
1.2
14
~
U
20
<
0
~
!!
12
a
10
"
Q.
"
-
~
r-- ~
-
r-- 1--_
AIJO
1.4
1.0
0
B
§
E
~
Q.
I
iii
':;
40
0
g
~
~
2.0
IB
(.)
>
...J
<
.~
O.B
Icc
-
0.6
~
4
o
I
0.4
~
> 0.2
o
SOk lOOk
-20
~
E 14
"0 1.5
i
"
6
':;
>
~I
---
~
(.)
1.0
0.5
10
~
B
~
6
U
I'
7
I
4
o
--
Vm.t
I
I
....
o
4
---
Ie ..
it-'
~
I
....
0
/'
I
,
, /
12
.;
....
10
12
14
Vee-Supply Voltage-V
RL-Lood Resistance-kQ
~
ZOk
1'1,.-.....
~
0
10
!g
10k
Avo
16
<
:0:
<
20
Sk
IB
2.0
~
c:
0.4
~
>
E
...J
100
2k
20
Q.
>
o
+20
+ 40
+ 60
Ta-Ambient Temperature-'C
128
BO
b
I
2.5
iii
~
....
lk
(Test CircuitCD,@)
100
1.6
500
CIRCUIT CURRENT, MAXIMUM OUTPUT VOLTAGE,
OPEN LOOP VOLTAGE GAIN vs. SUPPLY VOLTAGE
2.0
~
100 200
I-Frequency-Hz
(Test Circuit ®)
E
r-...r-.
L,..ol--'' '
MAXIMUM OUTPUT VOLTAGE vs.
LOAD RESISTANCE
iii
"""'i;
[.....-- f-
=>
0.02
0.05 0.1
BO
~
~
0.01
0.01 0.02
Avo
';;j
CI
>
I'..
0.2
0.1
:i
...,:
100
+ BO
16
IB
20
,uPC1032H
TYPICAL PRINTED CIRCUIT BOARD PATTERN
Bottom View (Unit: millimeters)
~----------------70~--------------~~
Components Layout
Foil Side
Components Side
lOOJlF(l6V)
....-------H....:...+--..------------oVcc
">---o----1R---OOUT
2.7kQ
129
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1228H
LOW NOISE DUAL 'PREAMPLIFIER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The ~PC1228H, a silicon monolithic integrated circuit, is a low noise dual preamplifier designed for car stereo
applications. The device consists of two separate amplification channels, and its major features are low noise, low
distortion, high gain, large dynamic range and wide supply voltage range.
Outline is a 8-lead single in-line plastic package, for small mounting space and easy mounting on P. C. Board.
FEATURES
• High open loop gain
: AvO = 100 dB TYP.
• Low noise
: Vnin= 1.1 ~V TYP.
• Low distortion
: T.H.D. = 0.05 % TYP.
• Large dynamic range
: VOM= 2.0 Vr.m.s. TYP.
• Wide supply voltage range
: VCC = 6 to 16 V
• High output current
: I ODC= 1 rnA MAX.
• Low impedance load driving capability
: RL = 1 kn MIN.
• Small feedback capacitance capability
PACKAGE DIMENSIONS in millimeters (inches)
19.5 MAX.
(0.76 MAX.)
2.8± 0'.2
(0.11 )
C 1
(C 0.04)
MARKING
l.8
(0.07)
2.54±0.2t
( 0.1)
I
II
17.78
( 0.7)
130
1.0±0.1
(0.04)-M-~
,uPC1228H
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage
18
270*
-30 to +75
-40 to +125
VCC
Package Dissipation
PD
Operating Temperature
T opt
Storage Temperature
T stg
V
mW
°c
°c
* Ta=75 °c
RECOMMENDED CONDITIONS (Ta
= 25°C)
Operating Supply Voltage
VCC
Supply Voltage Range
Vcc
Operating Ambient Tamperature
Ta
Load impedance
RL
ELECTRICAL CHARACTERISTICS (Ta
--
CHARACTER ISTIC
Quiescent Current
Open Loop Voltage Gain
MIN.
TYP.
T.H.D.
Input Impedance
q
Vo = 0.3 V, f = 100 Hz
40
dB
(2)
Vo = 0.3 V, NAB
2.0
V
(2)
T.H.D. = 1 %, NAB
%
(2)
Vo = 0.3 V, NAB
kn
(2)
}JVr.m.s.
(3)
0.05
50
4.8
0.3
100
1.1
Vnin
TEST CONDITIONS
Vin= 0
Avo
Total Harmonic Distortion
TEST CIRCUIT
(1)
100
1.0
UNIT
dB
3.3
90
Av
MAX.
mA
2.5
VOM
V
°c
(1 )
ICC
Voltage Gain
V
= 25°C, Vcc = 10 V, f = 1 kHz, RL = 10 kil)
SYMBOL
Maximum Output Voltage
Equivalent Input Noise Voltage
13.2
6 to 16
-30 to +75
10 kil TYP.
Cross Talk
-50
-65
Channel Balance
-0.3
0
1.7
+0.3
dB
(4)
dB
(4)
RG = 2.2 kil, NAB
Vo = 1 V, (The other channel
Vin = 0, RG = 2.2kn)
Vo = 0.3 V
CONNECTION DIAGRAM
Pin No.
Electrical connection
1
2
3
Input 1
Negative feed back 1
Output 1
Power supply: +VCC
Ground
Output 2
Negative feed back 2
Input 2
4
5
6
7
8
131
j.lPC1228H
TEST CIRCUITS
(2) Av, VOM, T.H.D., Zin test circuit (for Ch. 1)
(1) ICC, Avo test circuit
...--_-----0 Vee= 10 V
\
\
(3) Vnin test circuit (for CH. 1)
(4) Cross talk, Channel balance test circuit
.--__---0 Vee=10 V
B.P.F·
I=3dB\
RG=
2.2 kQ
{5Hz 30
Vn
k~
NOTE: Vnin is calculated by Vn and amp. gain (Av +40dB).
NOTE1: External components of the IC are the same as the test
circuit (2).
2: Cross talk procedure
Switch position SW.1
Switch position SW.1
3: Channel balance
Switch position SW.1
132
~2,
SW.2 ~1, 20 log V02/V01
2010g V01/V02
~1, SW.2~2,
~2,
SW.2 ~2, 20 log V01/V02
,uPC1228H
TYPICAL CHARACTERISTICS (Ta
= 25°C)
TOTAL HARMONIC DISTORTION
vs. OUTPUT VOLTAGE
OUTPUT VOLTAGE vs. INPUT VOLTAGE
10
Test Circuit(2)
VCC 10 V
0.5
V
2
V
/
f=1 kH
100 HZ/
>
I
zV V
I
V
c
0
0.2
~
0.1
is
tID
0
2
0.5
>
:J
.e::::s
0.2
I
0.1
V
V
V
,
1'.."
-
0.01
I
/
~~
I
0.002
0.001
0.5
0.2
10
2
20
50
om
100
0.02
0.05
0.2
t-....
0.1
Q)
0.02
Q)
tID tID
II
~~
~C)
VCi~v
0
0
0
0
cQ)
'0
...J ...J
~,
I
I
/~"\,
I'\.
u
/
'"
50
I
"
r-....
~~
'-'
~~
40
~
..........
0.002
30
0.001
0.010.02
0.05
0.1
0.2
Vo -
2
0.5
5
140
>
I
Q)
>
:J
2
L
1
.e::::s
f=l kHz, T.H.D.=l %
-
CIRCUIT CURRENT, MAXIMUM OUTPUT
VOLTAGE, VOLTAGE GAIN vs. SUPPLY VOLTAGE
15
Test Circuit(l), (2)
VCC=10 V
3
60
ro
ro
'0
'0
I
I
>
I
tID
<.!:l
<.!:l
Q)
Q)
a
2
a
>
a.
a.
0
0
0
0
0
.2u
2
>
E
::::s
E
a
2 ElO
I
>
:J
tID
tID
~
Q)
c
.~ 120 'ro40 2
0
,/
C
~
::::s
.e
::::s
'x
ro
~
'5
I
I
~
~
10
RL - Load Resistance - k Q
15
II
--1---
,I
Ava (f=l kHz)
-- -_..
0
a
f--- I--
_.-
ICC(Vi=O)
~
~
80
5
I
~
~
~
-- .-
~
VOM (f= 1 kHz, T.H.D. = 1 %)
J
!::?
I
I
0
0
~
~
-
AV (f= 1 kHz)
/
/
U
0
E
~
::::s
...J
...J
i:3
E
~
20'~
1 I 5
~100
u
a
100 k
10 k
f - Frequency - Hz
Test Circuit(2)
VCC=10 V
a
v(NAB)
III
1k
10
3
2
100
10
"
Output Voltage - V
MAXIMUM OUTPUT VOLTAGE vs.
LOAD RESISTANCE
tID
,
1/
60
Q)
0
r--.
l/~
CJ*'
oa. '"
0
l-
"~
II
F-
70
a. a.
...... ~
1\.\
~
»
ci 0.005
:i
10
Test Circuit(l),(2)
VCC=10 V
n
~~
22
0.01
0
t7
80
00
"
0
2
I
c
ro 'ro
-
c
:c
I
90 f -
<.!:l<.!:l
0.05
E
ro
'0
.S:
10 V, 13.2 V
VCC=6 V
'0
1IAVOI_
~
/
1111/
ro ro
II il
0
IIII
100
I I II I
~
2
0.5
0.2
Output Voltage - V
VOLTAGE GAIN vs. FREQUENCY
110
Test Circui t(2)
f 1 kHz
I 11 1
0.5
0.1
Vo -
TOTAL HARMONIC DISTORTION vs.
OUTPUT VOLTAGE
'
.~
)
-
Vi -Input Voltage - mV
is
f-.I
~
[7 /"
0.01
0.1
"-e
~
....
c::i
:i 0.005
/
I
I'
I'\.i'-.
1'\1"r--.
i'
0.02
I-
0.05
c
"",
~
0.05
:c
ro
'0
~
0.02
f=l lHZ r\~
E
ro
V VV
/V
0
0
V
V
'c0
V
I"
10 kHz"
't
10 kHz
Q)
a
I'
~
l-
Test Circuit(2
VCC 10 V
1-100 Hz
a
o
5
10
15
20
Vee - Supply Voltage - V
133
jlPC1228H
QUIESCENT CURRENT, MAXIMUM OUTPUT VOLTAGE,
VOLTAGE GAIN vs. AMBIENT TEMPERATURE
Test Circuit(l), (2)
VCC=10 V
140
CD
"t:I
I
120
oS
100
tID
(5
>
~
oS
g
I
6
tID
·ro
~
>
6
-
Q)
c:
Co
80 ~
0
Co
o
o
E
::l
E
...J
·x
5 E
I
-
c:
u
i"- "-
·5
ro
~
(3
3
I
:E
u
I 2 !::?
:E
~
~
.,/
4
4 ~
::l
3
f"""oo.
1- r---t-.,
o
r.....
I""- r--...
VOM (f= 1 kHz, T.H.D.= 1 %)
0
.~
20
.I
AVO(f=l kHz)
<:
o
4
2
6
8
10
14
12
16
30
PO-Output Power-W
20
20 30 50
100 200300 500
1k 2 k 3 k 5 k 10 k 20 k30 k50 k 100 k
f-Frequency-Hz
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWE R
20
~
I
10
c::::
SUPPLY VOLTAGE CHARACTERISTICS
80
Vee= 13.2 V
RL=4 Q
I
,"
:
,
5
.B
U)
is
3
0
'c0
2
E
r--. ..... ""'-.
1'0
~
'00.5
~
....
........
I
d 0.3
~ 0.2
....... ......
..,:
0.1
0.05
.......
"
....
100 H{
--
--t-o
...... ~ ...!....kHz
0.2 0.3 0.5
1
::J
1::
0
~
::
(!)
c::::
a.
0.6 :; 6
cr 40
C,)
E
30
g
I 30 ~ 0.4
< ~'0
20 d 0.2
~
..,:
..J
PO-Output Power-W
5
10
20
10
o
.e
5
I 4
0
~
o
./
~
~
~
/ ---%)
I
....J.---.
.
I
I
I
TH.D.I(~~l ~~Zw)_
/'
10
(T.H.D.= 10
f == 1 kHz
I
lee(NO Signal)
2
--o
I
/
=1 kHz )
PO=0.5 W
~
'/
Q"
I
eI
I
~ 50 ~40 E
.:;
2
ro
.~
:c
-~
3
A"
C 60 c:::: 50 0 0.8 S 8
~
'ro
.~
~
,:
2
Q
10
I
CD
'0
20
0.1
RL=4
I
60.~ 1.0
70
I
r---. ~ ..JJ
l-
140
<:
E
I
....... -!.: 10 kHf
:c
12
1.2
~
~I
0
:e
70
---
12
14
16
18
VcC-Supply Voltage-V
20
,uPC1181H3, ,uPC1182H3
TEMPERATURE CHARACTERISTICS
120
70
1.2
12
1.0
10
VCC=13.2 V
~
RL=4
I
100
~
:e.e
b50 is
::
[Xl
I
"0
(I)
.-
c 80
~
~
60 glJ40
~
~
.-
g
60
.~
c3
ro
E 0.6
~
C3 40 ~ 30
~
co 0.4
;,-
I
~
~
20
I
0.8 ~ 8
~
20 c:i 0.2
o
(PO=0.5 W)
'5 6 "-
.s-
o
10
p
o
----
(T.H.D.= 10
f=l'kHz
%)
.-- ~
:J
4
-
ICC(No Signal)
0..
2
:i
..,;
Av f= 1 kHz
-
0..
o
I
o
Q
I-
o
-
-25
T.H.D.
o
(PO ,0.5 W)
f = 1 kHz
25
50
75
Ta-Ambient Temperature-·C
TYPICAL APPLICATIONS
VCC
(1) Circuit Example
1 000 J.lF
INPUT
Cl
220 J.lF
Fig. A
• The supply ripple rejection ratio is improved by C6 •
(2) Circuit Example
VCC
1 000 J.lF
INPUT
Cl
220 J.lF
Fig. B
• The capacitor C4 is for preventing a parasitic oscillation.
A mylar film capacitor is recommended.
If an oscillation occure, increase capacitance of C4 , or connect an additional resistor R 1 as shown in Fig. B.
141
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1185H2
7 W DUAL AF POWER AMPLIFIER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRC·UIT
The pPCl185H2 is a dual audio power amplifiers in a 12-lead single in-line package, specifically designed for car stereo
application.
This device provides an output power of 7 watts per channel to 4 ohm load with 10 percent distortion at 14.4 volts power
supply.
The pPCl185H2 is pin to pin equivalent to the pPCl185H.
FEATURES
• Very low number of external small size components.
• Easy mounting with no electrical isolation between the package and heat sink.
• Space saving due to the single in-line package.
• Very low transient noise at power switch-on.
• No damage for reverse insertion on the PC-board.
• Thermal shut-down circuit included.
• Load dump protection circuit included.
PACKAGE DIMENSIONS (in millimeters)
CONNECTION DIAGRAM
2.5
142
Pin No.
Function
1
GND (for input)
2
Output 1
3
Boot Strap 1
4
Filter
5
N.F.1
6
Input 1
7
Input 2
8
N.F.2
9
+VCC
10
Boot Strap 2
11
Output 2
12
GN 0 (for output)
,uPC1185H2
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage (Surge PW = 200 ms)
VCCsurge
40
V
Supply Voltage (Quiecent)
VCC1
25*
V
Supply Voltage (Operational)
VCC2
18
V
Circuit Current (Peak)
Icc
4.5
A
Package Dissipation
Po
20
W
Operating Temperature
T opt
Tstg
-30 to +75*
°c
°c
Storage Temperature
peak
-55 to +150
*Using an aluminum heat sink Oth(c-a) =6 °C/W
EL~CTRICAL CHARACTERISTICS (Ta=25
CHARACTERISTIC
Circuit Current
Output Power
Total Harmonic Distortion
SYMBOL
ICC
Po
°c,
Vee = 13.2 V, f= 1 kHz, RL =4 il)
MIN.
TYP.
MAX.
UNIT
30
80
180
mA
5.0
7.0
T.H.D. = 10 %, VCC = 14.4 V
5.8
W
T.H.D.=10 %, VCC=13.2 V
8.5
W
T.H.D.=10%,RL=2n, VCC=13.2V
1.0
0.4
Voltage Gain
AI)
Channel Balance
AAu
Cross Talk
CT
Output Noise Level
Un
Uin=O
W
0.3
T.H.D.
TEST CON DITIONS
51
54
30
45
1.4
%
PO=0.5 W
%
PO=2 W, RL =2 n
58
dB
±1.5
dB
PO=0.5 W
dB
f = 1 kHz, other ch RG = 0
mVr.m.s.
4
PO=0.5 W
RG = 1 0 kn.
TEST CIRCUIT
SWI
47J.lF /6.3V
Table 1
Vee
SW1
SW2
OFF
3
3
Po
ON
1
(3)
3
(1)
T.H.D.
ON
1
(3)
3
(1 )
Au
ON
1
(3)
·3
(1 )
13.2V
ICC
7
*Mylar Film Capacitor
SW3
Un
ON
2
2
SVR
ON
3
3
CT
ON
1
(3)
3
(1 )
The position of switches at testing AMP1
is show in table 1. The numbers in parenthesis show the position of switches in
testing AMP2.
143
,uPC1185H2
BLOCK DIAGRAM
+
Vee
1 000 JlF
NOTICE:
This device is not recommended for bridge and power booster amplifiers because
the ~pe1230H suitable for its.
144
J,lPC1185H2
TYPICAL CHARACTERISTICS (Ta =25°C)
POWER DISSIPATION vs.
OUTPUT POWER
PACKAGE DISSIPATION vs.
AMBIENT TEMPERATURE
18
24~----~----~----~------~A-I-P-a-ne-l-t-=~2~m-m-----'
::I
Use silicone grease
Unit :mm
20~----~p---~----~----~
::
c:
:3~
14
I
c:
16 t-----+_
121---+_
VI
Q)
bO
co
81-----+------r--
u
co
is
8
~
6
a..
4
0
a..
I
4~~E~S
o
Cl
a..
Free Air
(OJ-a=32 -C/W)
25
50
75
100
125
-,
~
~
~
~
-- - -....
4
60
II)
(!)
~
2
~
I
.,
........ ......
.....
,~
*
I
c:
0
:e
,
.8VI
10
is
5
3
2
'c0
"
30
10
12
14
,"
,
I
.... ~ ...
. .... ... -J,,=
J:
2
0
ex:
I-
I
100 200 300 500
I
VCC=13.2 V
RL=4 Q
E
co
"'Iii"
20 30 50
I
8
50
30
20
u
40
20
10
6
TOTAL HARMONIC DISTORTION
VCC=13.2 V
vin=2.45 mV
RL=4 Q
,/-
I
vs. OUTPUT POWER
70
50
"""""""
PO-Output Power-W
VOLTAGE GAIN vs. FREQUENCY
I
c:
·iii
VCC=13.2 V_ RL=2 Q
VCC=16 V
RL=4 Q
VCC=13.2 V
RL=4 Q
I
2
Ta - Ambient Temperature-·C
"tJ
_I-
J.
~
r- r---...
2
0
150
"'VCC=16 V
RL=2 Q
I
,,--
//.
I
"tJ
a..
-"",,-
~7
a. 10
.iii
VI
.:.:
)/-
12
.~
co
·iii
is
f=l kHz
2 ch
operate
16
d
:i
t-=
1k 2 k 3 k 5 k 10 k 20 k30 k50 k 100 k
f-Frequency-Hz
0 ~Hz
~J.gO~ ...
~
0.5
0.3
0.2
I
0"'
I,~
~~~~.
1 kHz I"
.• ?II
l..o'
r-~
0.1
I
I
0.020.030.05 0.1
0.20.3 0.5
1
2 3 5
10
20
30
PO-Output Power-W
SUPPLY VOLTAGE CHARACTERISTICS
SUPPLY VOLTAGE CHARACTE RISTICS
14
7
12
::
10
/
I
~0
a..
8
~
~
~.,
~
0
I
0
,
4
a..
~v
200
.....c:
~
~, R=4 Q
Q)
~ 150
u
~,
2
is 1.5
bO
40
~
~ 100
I
E
(5
co
==j 30 J:
ex:
c.>
.9 50
u
'c0
.,
Iii
-0
20 lI 0.5
r
,.
--
d
o
8
10
12
14
16
18
20
t-=
ICC (No Signal)
I
I
I
I
e=l kHZ)
T.H.D. PO=0.5 W
10 :i
6
Q
(f =1 kHz )
Av PO=0.5W
VI
'iii
(!)
2
C3
/'
I
c:
RL=4
I
:zj
Q)
.....
/'"
*
0
II)
I
I
1c: 5 0 2
I
",'"
2
o
~.,
E
/
~,
)'
6
60
ex:
/
/
.....
.s-
f=l kHz
T.H.D.=lO %
R=2 Q
2.5
250
o
6
8
10
12
14
16
18
20
Vce-Supply Voltage-V
VCC-Supply Voltage-V
145
BIPOLAR ANALOG INTEGRATED CIRCUIT
I1 P C1230H
23 W AF POWER AMPLIFIER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
The ,uPC1230H is an audio power amplifier in a 12-lead single in-line package, specifically designed for car stereo application.
Typically it provided 23 watts output power at 14.4 volt and 20 watts at 13.2 V on a 4 ohm load.
This device can be used without
ou~put
capacitors, because it incorporates the orignal short circuit protection which protects
output power transistors and a speaker at the same time when the output terminal is shorted to ground.
FEATURES
• Can be used as OCL connection.
• Very low output offset voltage: Voffset = 150 mV (MAX.)
• High output power: Po =23 W TYP.
Po =20 W TYP.
RL =4
RL =4
n
n
at 14.4 V
at 13.2 V
• Very low distortion.
• Very low number of external low size components, very simple mounting system with no electrical
isolation between the package and the heat sink .
• Low thermal resistance: () J-C ;,: 2.5 °C/W
• Following protective circuit as provide
(1)
(2)
(3)
(4)
Load dump protection
Output therminal short circuit protection
Thermal shut down protection
Speaker protection
PACKAGE DIMENSIONS
(in millimeters)
32.0 MAX.
5.0 MAX.
24.0±0.2
2.5
0.3
--I-~-1.4
146
MAX.
,uPC1230H
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
VCC surge
40
V
Supply Voltage (Quiecent)
VCC1
25*
V
Supply Voltage (Operational)
VCC2
18
V
Circuit Current (Peak)
ICC peak
4.5
A
Package Dissipation
PD
20
W
Operating Temperature
T opt
-30 to +75*
°c
Storage Temperature
T stg
-55 to +150
°c
Supply Voltage
(Note)
*Using an aluminum heat sink 0th(c-a) =4 °C/W
Note: Pulse width = 200 ms, Trise 2: 1 ms
RECOMMENDED OPERATING CONDITIONS (Ta=25 °C)
Supply Voltage Range
9.5 to 16
v
Load Impedance
3.2 to 16
n
ELECTRICAL CHARACTERISTICS (Ta=25 °c, Vcc = 13.2 V, RL =4
CHARACTERISTIC
Quiescent Current
Output Offset Voltage
Output Power
Voltage Gain
Total Harmonic Distortion
Output Noise Level
Supply Voltage Rejection Ratio
Input Resistance
Rolloff Frequency
SYMBOL
MIN.
ICC
16
53
kHz)
TYP.
MAX.
UNIT
90
180
mA
vin=O
±150
mV
Vin =0
Voffset
Po
n, f= 1
TEST CONDITIONS
23
W
VCC=14.4 V, T.H.D.=10 %
20
W
VCC=13.2 V, T.H.D.=10 %
Vin =2.45 mV
55
56
dB
T.H.D.
0.15
1.0
%
vn
0.65
mV
RG =0, BW=20 to 20 kHz
SVR
45
dB
RG =0, frip = 100 Hz, Vrip = 0.5 V
Av
PO=2 W
Ri
45
kn
fH
90
kHz
Au =-3 dB from 1 kHz Ref.
High
fL
15
Hz
Au =-3 dB from
Low
TEST CIRCUIT & TYPICAL APPLICATIONS
m
47 pF/16 V
0.1 pF
I
:t
~
;J;C S
1 kHz Ref.
VCC
013.2 V
:S;C9 2200 pF/16 V
r':4---dr---.,
1100 pF/16 V
*Mylar film capacitor
147
jlPC1230H
BLOCK DIAGRAM
VCC
47 .uF/16 V
+
+
2200 .uF/16 V
input
1 Q
100 .uF/6.3 V
LOAD DUMP
TERMINAL SHUTDOWN
THERMAL SHORT·
CIRCUIT
PROTECTOR
100 .uF/6.3 V
CONNECTION DIAGRAM
Pin No.
1
Output 2
2
Boot Strap 2
3
Divided Output
4
Input 2
5
N.F.1
6
Input 1
7
GND (for input)
8
Filter
9
148
Function
+VCC
10
Boot Strap 1
11
Output 1
12
GND (for output)
0;r
0.1 /-iF
1 Q
RL
4Q
J,lPC1230H
PACKAGE DISSIPATION vs.
AMBIENT TEMPERATURE
POWER DISSIPATION VI.
OUTPUT POWE R
30
30
25
~
I
c
0
:;:;
1"'-900
a.
·iii
VI
15
I--
C1I
boO
-
III
~
0
III
0..
I
f=l kHz
..-
~
~I-j
~
III
I
~
20
III
i5
.~~
I
'<7
c",<
I
Free
Ai~
\\-r-
')
25
d._I_J.
50
Ta-Ambient
\"
·s.
I C'/~~~'"
75
4$'_
,~~
~c/W)
o
VI
'*',
C'
/~
q~8
"I
100
-
Te~perature-·C
20
a.
·iii
\"0,\~
'.;>~
(,.
(t9.
I......
10
c
~"/KIs:; \;;-~
1\"
100
0
0..
i5
....C1I
0..
I
-'
0
0..
'1~
\~
)f'
125
I
50
o
150
Vee=13.2 V
RL=4 Q
Vin=5.6 mVr.m.s.
/
/"
- .... r-.
-
i""""'-- ~ 10 V
10
20
Po-Output Power-W
30
~
I
Vee 13.2 V
RL 4 Q
RG 600 Q
50
c
~ 20
o
Vi 10
o
o
o
·2
E
45
2
III
::I:
"0
10 kHz
100 Hz
I§
>
I~
Vee= 13.2 V_
--I"---. .........
TOTAL HARMONIC DISTORTION
OUTPUT POWER
(.!)
~
"'-
r-
J
VS.
·ro
~
----
-
16 V
~
~
55
c
~
\ ;_
:..,-
-
100
60
co
/
10
~~f\
f--
l"- i"'-
/"'!"'"
~
0
VOLTAGE GAIN VI.
FREQUENCY
"0
RL =4 Q
AI Panel t-2 mm
Use silicon grease
Unit; cm
o 0.5
t-
40
I
C 0.2
0«
:x::
....: 0.1
0.01 0.02
35
30
10
20
50 100 200 500 1k 2 k
5 k 10k 20 k
f-Frequency-Hz
.......
~
.L IT
I""
I
IL
'1'1
TI
f=l kHz nTI
0.05 0.1 0.2
0.5 1
Po-Output Power-W
10
20
50 100
50 k 100 k
149
,uPC1230H
OUTPUT POWER vs.
SUPPLY VOLTAGE
SUPPLY VOLTAGE CHARACTERISTICS
30
20
f= 1 kH z
/I
I
==
L
20
T.~.D.= 10 %
-0
V
/
:;
.9:::I
,
/
0
0
a.
/
10
,,, , " V
V
T.H.D.=l
~
%
30
U
/'1'
V
2
a.
o.
:::I
en
15
0
u
20
till
30
(5
:::I
en
,
0::
>
en
C1)
0:
'5 10
,
'\.
.e
>
-E:0.
>
a.
0.
C1)
2
C1)
till
~loo
0
C1)
'(j)
0::
:::I
40
0
I
r--
0.
'':
c:
;::.
10
100
1 k
10 k
trip-Ripple Frequency-Hz
150
(!)
'(ij
l,....-o'
c:
till
t-
I
I
..f'
-~
100 k
-
I--
I
U
2
..
,'"",
~:::I
C1)
~t-
-
\'lli"" 0)
\~
I
0
~'
SVR (RG=O. frip= 100 Hz. Vrip=O.5 V r . m. s )
__ I
,
~
,
,
,--,--1
T.H.D. (f=1 kHz. PO=2 W. RG=600 Q)
0
45
0
-
-- --
10
15
Vee-Supply Voltage-V
Vee 13.2 V
RG 0
V ripple= 0.5 Vr .m.s.
>
E
I
c: 10
0
Gv (f=l kHz. PO=2 w)
I
:i
50
20
1000
~
c:
ci
I
-0
-:Q
I
>- 40 ~
1 g50
0
SUPPLY VOLTAGE REJECTION RATIO
vs. RIPPLE FREQUENCY
0::
~
-0
:x:
(5
Vee-Supply Voltage-V
.~
II)
u
>
>
en
0
2
E
ro
till
0::
I
B
VI
'c
C1)
V
~
Ci
C1)
'(j)
0::
",'
II)
100
I
c:
0::
V
10
55
RL =4 Q
~
I
:3ro
7T
/
I
C1)
~
0
a.
150
II)
/
/
60
RL=4 Q
20
jlPC1230H
COMPONENTS LAYOUT FOR P.W. ASSEMBLY (Copper side)
HO£l18d ri
INPUT
151
BIPOLAR ANALOG INTEGRATED CIRCUITS
~PC1241H,~PC1242H
7 W AF POWER AMPLIFIER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The J,lPC1241 Hand J.lPC1242H are audio power amplifiers which is especially designed for car radio and car stereo.
The devices are encapsulated in newly developed small packages featuring low thermal resistance, providing easy design for 2 n
load circuit and 4 U load BTL circuit.
At 14.4 V the devices give output power of 7 W at RL = 4 nand 11 Wat RL = 2 n
FEATURES
•
High output power:
Po= 7 W TYP.
@
RL = 4 n, T.H.D. = 10 %, Vee= 14.4 V
Po =ll W TYP.
Po =18 W (Bridge)
@
RL = 2 n, T.H.D. = 10 %, Vee= 14.4 V
@
RL = 4 n, T.H.D. = 10 %, Vee= 14.4 V
T.H;D.=O.l % TYP.
@
RL = 4 n, Po= 0.5 W
•
Low distortion :
•
High reliability: of the chip and package with additional complete safety during operation thanks to protection
against;
(1) Load dump voltage surge.
0
(2) Over rating chip temperature (150 C).
(3) Output DC and AC short circuit to ground or Vee.
(4) Revere insertion.
These ICs are not destroyed nor damaged even when any of neighboring two terminals are shorted to each other.
• Space and cost saving: very low number of external components, very simple mounting system with no electrical
isolation between the package and the heat sink (one screw only).
• Pin orders of these types are symmertical each other, which reduces the area of Printed Circuit Board effectively.
PACKAGE DIMENSIONS (in millimeters)
3.8 MAX.
20.32 MAX.
1J1.3±003
R 3.S±0.1
0
x
x
c:(
:i:
...
It')
z
:iil
co
Lri
c:(
:E
....
10
N
~
c::i
+I
0'1
0
z
....
1.8 MAX.
:iil
~
1.27 MIN.
12.541
152
...;
j1.
PC1241H,j1. PC1242H
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Supply Voltage (Surge PW=200 ms)
VCC surge
50
V
Supply VOltage (Quiecent)
V CCl
25*
V
Supply Voltage (Operational)
VCC2
18
V
Circuit Current (Peak)
ICC peak
4.5
A
Package Dissipation
PD
12
W
Operating Temperature
Topt
-30 to +75 *
°c
Storage Temperature
T stg
-55 to +150
°c
·Using an aluminum heat sink 100 X 100 X 1 mm
RECOMMENDED CONDITIONS (Ta=25 °C)
Supply Voltage Range
Load Impedance
9.5 to 16
V
2 to 16
n
ELECTRICAL CHARACTERISTICS (Tu=25 0 C, f = 1 kHz, RL =4 n)
CHARACTERISTIC
SYMBOL
Circuit Current
MIN.
ICC
Output Power
TYP.
MAX.
UNIT
25
45
80
mA
5.0
5.8
Po
RL=4 n, T.H.D.=10 %, VCc=13.2 V
7
W
RL=4 n, T.H.D.=10 %, VCC=14.4 V
9.2
W
RL=2 fl, T.H.D.=10 %, VCc=13.2 V
W
RL=2 n, T.H.D.=10 %, VCC=14.4 V
1
%
RL=4 fl, Po=0.5W, VCc=13.2 V
%
RL=2 n, Po =l W, VCc=13.2 V
51.5
54
dB
Po =0.5W
1.4
4.0
mVr .m . s.
0.1
T.H.D.
0.4
Voltage Gain
Av
Output Noise Level
Vn
49
tr.n=O, VCC=13.2 V
W
11
Total Harmonic Distortion
TEST CONDITIONS
RG=10 kn
TEST CIRCUIT
r------------++-------O
VCC
14.4 V
1 000 J.lF
SG
3
* Mylar Film Capacitor
153
j1.
PC1241H,j1. PC1242H
BLOCK DIAGRAM
r--------------------nVcc
+
47.uF
)-------------.(81------_
/6.3 V
OVER VOLTAGE
LOAD DUMP
PROTECTION
&
47 .uF/!O V
IN
RL
4 Q
L-.-----l
4
}------------~
5 1-------'
CONNECTION DIAGRAM
pPC1242H
pPC1241H
Pin No.
NEe
,uPC1241H
234
154
5
678
876
5
432
pPC1241H
pPC1242H
1
Input
2
Bypass
3
Feedback
4
GND (for Input)
5
GND (for Output)
6
Output
7
Bootstrap
8
Power supp Iy
J1 PC1241 H,J1 PC1242H
TYPICAL CHARACTERISTICS (T a =25°C)
POWER DISSIPATION vs.
OUTPUT POWER
POWER DISSIPATION vs.
OUTPUT POWER
:;:
I
ro
:;:
0
~
;;:
0
V
0-
;;:
~P'
i--"'"
5
0
0-
10 V
--
13.2 V
7. V'
I
')~'
"0
~
r---
-
-r-- 1E~
l,...--I--
~
13.2 V
~
./
V
0
t-
r-
./
Vee=18 V
~
--I--I-"
.~
l - t-
-- - -
r/
10
ro
c.
16 V
l"'- t-
'1/"
"0
0
:,J
--r-r--
/""
II 1/ ....
3
I
c
Vee=18 V
4
0-
I
.I.
5
.9
~
0>
«
~
0-
I"'-
~
I;> 30
C>
4
.......
40 Z
a
\I
ro
I
I
~.
U
0
aJ
"0
.::£
0-
60
~-+-t--t
8
0
~
70
~
:~
Q)
Vee=13.2 V
RL=4 Q
Po =0.5 W
RG=600 Q
80
~. --+--+--1
10
I
ro
20
PACKAGE DISSIPATION vs.
AMBIENT TEMPERATURE
c
0
:,J
15
Po -Output Power-W
AI Panel
12 ~-+-+--+-'-"--f-o.!:--!-+--+"""~--I Use silicon
grease
:;:
10
PO-Output Power-W
20
2
10
o
25
50
75
100
125
o
150
10
1k
100
Ta-Ambient Temperature-'C
10 k
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER
Vee 13.2 V
RL 4 Q
RG=600 Q
Vee 13.2 V
RL 2 Q
RG=600 Q
~
~
I
c
0
:,J
I
c
10
0
:e
~
~
u
u
§
I
10
0
0
'c
0
100 k
f-Frequency-Hz
'c
0
1.0
§
ro
f
:§
......
0
l-
~
10 kHz
L."ooo'
100 Hz
.......V
"'- ~~Hr;r
I
c:i 0.1
::i
I
..... Iit'
100 Hz
I L
l-
V
10 kHz
~
co
"0
I
c:i
::i
1 kHz
0.1
....,:
....,:
0.01
0.001
f
ro
0.01
0.1
Po-Output Power-W
1.0
10
0.01
0.01
0.1
10
Po-Output Power-W
ISS
p PC1241 H,p PC1242H
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs. SIGNAL SOURCE RESISTANCE
vs. FREQUENCY
Vee 13.2 V
Rl 4 Q
P.o=0.5 W
RG=600 Q
~
I
r::
~
I
10
0
Vee 13.2 V
f 1 kHz
Rl=4 Q
Po=0.5 W
10
r::
0
~
a
~
VI
~
,
u
·c
a
u
·c
\.
0
E
0
E
<0
<0
:I:
:I:
v-
co
iii
-0
l-
i\.
I
c::i
:i
0.1
"0
I
..--
l-
...... ~
t-=
~
0.1
c::i
:i
t-=
0.01
10
10 k
1k
100
0.01
10
100 k
100
100 k
10 k
1k
RG-Signal Source Resistance- Q
f-Frequency-Hz
OUTPUT NOISE VOLTAGE vs.
SIGNAL SOURCE RESISTANCE
SUPPLY VOLTAGE REJECTION
vs. RIPPLE FREQUENCY
Vee=13.2 V
Rl=4 Q
8
Vee=13.2 V
Rl=4 Q
RG=O Q
Vrip=0.3 V
80
70
7
CD
"0
..
>
E
!tID
.e
0
>
I
6
r::
0
Q)
5
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a:: 50
4
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0
Q)
~
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z
tlO
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0
60
u
Ir::
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3
>.
a.
a.
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30
U)
I
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a::
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U)
,/
~
~
~
2
:--.
./
40
>
~
20
10
o
1k
100
100 k
10 k
o
1M
SUPPLY VOLTAGE CHARACTERISTICS
15
f=1 kHz
T.H.D.=lO %
==!
,,
Q)
/
a.
"5
/'t'
~
0
0
a.
,
5
,.
~'
k'"
,
...
,
,
V
/'
V
~
,
)~Rl=4
100
..!.r::
I
(!)
~
u
9
·c
0
I
~
,
,,
:I:
~
0
I-
c:(
20
0.5
10
15
20
o
o
I
l
-
Ilee (v:=O)
~
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a::
40
30
Q)
tID
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>
>.
a.
a.
~
U)
20
,,
J
"_t~D.
10
I
a::
>
U)
(f=1 kHz, Po =0.5 W)
-- -
o
5
0
0
-v
10
.
r::
50
I
',--
I
c::i
:i
t-=
1.00'
-- -
,.
CD
"0
1. I. 1_ H~O Hz, Vrip=O.3
V)
SVR (frlp
_
<0
~ 30
50
60
J
-f----
1.0
E
.e
~
I
40
tID
U
/
~
u
Q)
·5
:r
70
Av (f=1 kHz, Po=0.5 W)
Ci
r::
u
Q
~ 50
·ro
~
/V
vee-Supply Voltage-V
156
,
I
0
o
5
~
r::
/
~
.e
60
,1
V
VCC=13.2 V
Rl=4 Q
70
,/
'/
10
~
0
I
1.5
150
Q/
100 k
10 k
trip-Ripple Frequency-Hz
o UTP UT POWE R vs.
SUPPLY VOLTAGE
Rl=2
1k
100
10
RG-Signal Source Resistance- Q
15
vee-Supply Voltage-V.
10
o
20
jJ.
PC1241H,jJ. PC1242H
TEMPERATURE CHARACTERISTICS
120
70
1.2
12
VCC=13.2 V
RL=4 Q
~
100
c(
80
l'c:
S
:e
1.0
10
.e
'3
b
>
40
!:?
i,....oo-'
~
10-
:I:
(5
~
--
3.6±O.1
~
4.8MAX.
1.3
2.2
4.5
8.4
ABSOLUTE MAXIMUM RATINGS
Peak Supply Voltage (50 ms)
DC Supply Voltage (quiescent)
DC Supply Voltage (operational)
VCC1
40
V
VCC2
, VCC3
28
V
18
V
Output Peak Current (repetitive)
ICC{peak)1
3.5
A
Output Peak Current (non repetitive)
ICC{peak)2
4.5
A
Package Dissipation (Tease = 90°C)
Po
15
W
Operating Temperature
Topt
-30 to 75
°c
T stg
-40 to 150
°c
4
°C/W
8 to 18
V
Storage Temperature
THERMAL DATA
Thermal Resistance junction-case
Rth(j-c)
RECOMMENDED OPERATING CONDITION (Ta=25°C)
Operating Supply Voltage Range
160
VCC
JlPC2002
ELECTRICAL CHARACTERISTICS
(Refer to the test circuit. : Ta = 2SoC, RL =4n, f= 1kHz, using an aluminum heat sink 100x 100x2 mm)
CHARACTER ISTIC
VCC=14.4V
SYMBOL
Quiescent Current
MIN.
ICC
Output Power
Po
VCC"13.2V
TYP.
UNIT
TEST CONDITIONS
TYP.
MAX.
35
55
85
54
rnA
4.8
5.4
4.5
W
RL "4n, T.H.D. -10%
9.0
7.5
W
%
RL -2n, T.H.D."10%
RL a4n, Po-0.5W
Total Harmonic Distortion
T.H.D.
Open Loop Voltage Gain
Closed Loop Voltage Gain
Avo
Av
Output Noise Voltage
Un
Input Resistance
Ri
70
Supply Voltage Rejection Ratio
SVR
30
0.05
1.0
0.05
0.06
1.0
0.06
%
RL "2n, Po"1.0W
78
dB
Po-0.5W
Po"0.5W
78
39.5
Ui=O
40
40.5
40
dB
0.6
3.0
0.6
rnVr.rn.s.
150
150
kn
39
39
dB
RG -10kn
RG-10kn
Uripple" 0.5V
f ripple"" 1OOHz
TEST CI RCUIT
SW.1
r-
I
r--~-_ _--.._ _ _Ii--o--o--t-_ _"""---o Vee = 14.4V
r
SW.2
L _____ J
+
0.1# -
lOOJ,F/16V
lOpF/lOV
lOOOJ,F/lOV
Output
lOkO
4.7 JlF / lOY
SW.3
In
r- ---,
1~~~/6V
470J,lf/6V
• Mylar capacitor
Switch position
~
ICC
SW.1
2
1
1
1
1
1
1
SW.2
2
1
1
1
1
2
SW.3
1
1
1
2
1
1
2
1
SW.
Po
T.H.D.
Avo
Av
Un
SVR
161
jJ.PC2002
TYPICAL CHARACTERISTICS (Ta = 25°C)
PACKAGE DISSIPATION vs.
AMBIENT TEMPERATURE
POWER DISSIPATION AND EFFICIENCY
vs. OUTPUT POWE R
100
20r--,---.--,---r--.---.-H-ea-t-s-n-k-A-I----~
10
VCC- 14. 4V
f= 1kHz
Use sillicone grease
80
:=
8
I
c::
:=
o
*'
0:1
c::
I
I
c::
>u
+:
.~
0
.~
60
CLl
'u
w
I
CLl
bO
l::-
~
6
~
~
~
o
.~
0
~
i'
40
~
0
c..
I
4
7
"0
c..
U
0:1
c..
I
o
c..
20
/
2
V
/
.'
~
~//
.....
/
=20)
. V 71(RL =40) 71(RL
,_ ... .;
~
.
~
...
...
... .......
...--r
=+-l
Pd(RL =20)
~'
-r--. ...... Pd(RL =40)
/0- ",.
~
--.-~
/
0
50
100
150
Ta-Ambient Temperature-'C
200
0
2
POWER DISSIPATION vs.
OUTPUT POWE R
10
---- RL =20
....
8
........
:=
TOTAL HARMONIC DISTORTION
vs. 0 UTP UT POWE R
20
!
f=lkHz
--RL=40
--
--' --
f---
'18V -
--- ---
0
+:
0:1
c.
'm
,"'~
6
0
....CLl
0
t)
.,.... .... ...
,, ".." ~
-- --- -- -- --
Vee=14.4V-
r- __
4
c..
I
I
c.."
2
r--
/'
'/
,
I-"'"
/ ....
---
"
............
o
5
I
I
0
2
u
'c
0
§
I
~
0
I
0
~
If
*'
+:
~.
c::
Vec=14.4V
RL =40
10
c::
, ....
I
0:1
:r: 0.5
-~
r-..... t" Vee = 14. 4V
18V -
f
~
r---......
10kHz
r-t-~
0
I-
0.2
I
ci
:C 0.1
l-
f ' ,,~
~
8V
100Hz
IJ 1./
0.05
III
8V
2
10
8
4
6
Po - Output Power - W
4
6
PO-Output Power-W
8
10
0.02
0.01' 0.02
I
III
0.05 O. 1 0.2
lkHz~
I II
0.5
5
2
10
Po-Output Power-W
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER
20
10
OPEN LOOP VOLTAGE GAIN AND CLOSED
LOOP VOLTAGE GAIN vs. FREQUENCY
Vec=14.4V
RL =20
160
:?
:,., ;r~·~~ F1 ~
VCC=14.4V
Avo test circuit
*'
I
5
lO~+
c::
0
+:
0
t)
2
0
Ii
u
'c0
f
§ 0.5
0:1
l/~
10kHz
V
:r:
(ij
0 0.2
l-
I
ci
:C
~
4,O,l;lCXl.uFVCC
;t~. ,...,
~
o.l.uFl
vO
I"k
1
~
O. 1
f:::~
-
0.05
0.02
0.01 0.02
V
i)
100Hz
~
162
~
RL =40
0.05 O. 1 0.2
0.5
PO-Output Power-W
2
V-
f"'..
I
Av (PO=O.5W)
, i
I""
.,.... I-f-'
20
t~ZI-
I
5
10
010 20
50.100 200
500 1k 2k'
5k 10k 20k
f- Frequency - Hz
50k lOOk
,uPC2002
QUIESCENT CURRENT. CLOSED LOOP VOLTAGE GAIN.
TOTAL HARMON IC DISTORTION AND SUPPLY VOLTAGE
REJECTION RATIO vs. SUPPLY VOLTAGE
OUTPUT POWER vs.
SUPPLY VOLTAGE
15
-60
f= 1kHz
T.H.O.=lO%
/
en
I
~
/;""~(
I
10
~
a
a..
/
/
"=i
.e::J
0
I
0
a..
5
V
/
V
/
V
'<:y
co
0::
/
150
If
a
~I
Q)
'c
:r:
I I I
U
c.
a
a
ro
2
-0
>
r-- r- SVR (RG = lOkU fripple = 100Hz. Vripple =0. 5V) f--
::J
>
a
E
Av (PO=0.5W, f=lkHz)
_L
100
~
2
-0
u
Q)
c
Q)
lil
-l
ro
r-
.~
Cf)
I
>
Cf)
0::
-
~
.,/
15
o
o
20
~-
(5
f-
::J
10
I J I
ICC (vi=O)
--
::J
50
O. 1 ~20 0'
a
I
U
!
u
I
ci
..Y
;,
:i
«
>.
0. -20
c.
.... V
I
tl
bD
/"
c
(5
0::
/'
I
a
.~ O. 2 ~ 40
-40
.iii'
«;.v/
V
en
'0
c
~
Q)
'O<~/
RL =40
r--
'C!2.
c
~
60
'0
1/
=::
0.3
o
o
5
VCC-Supply Voltage-V
T.H.O. (PO=O. 5W, f= 1kHz)
20
15
10
VCC-Supply Voltage-V
OUTPUT POWER. CLOSED LOOP VOLTAGE GAIN. TOTAL
HARMONIC DISTORTION. SUPPLY VOLTAGE REJECTION
RATIO AND QUIESCENT CURRENT vs. AMBIENT TEMPERATURE
150
-60
0.3
60
15
5-40 ~ 0.2 ~40
=::10
VCC=14.4V
RL=411
en
'0
I
c
'C!2.
I
en
0::
a
:p
c
"iii
~
I
.Q
100
~::J
(5
Q)
.iii'
Q)
I
U
..Y
>
E
co
bD
c.
a
a
SVR
f--
~
a
a..
"=i
-0
a
Q)
lil
2
u
2
:r:
-0
%
-l
>
0
ro
Z,-20
~ 0.1 ~20
Vl
~5
c.
a
c.
a..
I
::J
U
Cf)
ci
I
I
;,
:i
0::
«
~
>
Cf)
o
o
o
L-
I 1
(RG = 10k11, fripple = 100Hz, Vripple =0. 5V) '---
!
I
I'
I
I
1 1
II
II
I
-
I-- ICC (v·=O)
r-L.t
~l
-
:;;-
-~
Po (T.H.D. = lO%,f= 1kHz)
I
I
1
1
1
I
.-~
1
...
.....
~
c--
o
Av (PO=O. 5W, f= 1kHz)
=-
I
Q)
'c
0::
'5
0' 50
I
'';::::
u
u
C
Q)
'0
c
0
-50
__ 1.\--1.0. (Po=O.
I
5Wf=1\-120
APPLICATION CIRCUIT (Top view)
33 Q
+Vee
Audio Output
Signal
Meter
ANT.
172
,uPC1243C
COIL SPECIFICATION (Bottom view)
(1) OSC Coil
c
RWR-43208N (TOKO Co.)
v.C.
Base
GND
~ II
®
3
11
CD
II
II
II
Qu = 110 -
(796 kHz)
G)-@ @-@ @-@
@ VCC
4T
58T
L = 160 JlH
10T
±6 %
@
Collector
(2) IFT1 (IF transformer) CFT455B (TOKO Co.)
Centre freq. 455 kHz ± 3.5 kHz
Selectivity ± 10 kHz
26 dB Mini.
Collector
Base
VCC
GND
(3) IFT2 (IF transformer)
RMC-43198C (TOKO Co.)
Centre freq.
~
~
(2)
CD
@
~jjII ~~
II
Qu
= 80 -
455 kHz
180 pF (Included)
(455 kHz)
CD-@
@
164T
(4) Bar antenna AR12¢-120 (Coil Snake Co.)
roooOOOl
db
V.C.
flrlcb
234
GND OUT GND
G)-@ @-@) @-@
58T
6T
5T
IN(ANT.)
(5) Air variable FB621 U (Alps Electric Co.)
Capacitor
CMAX • = 326 pF
CM1N • = 9 pF
173
,uPC1243C
EXAMPLE FOR PRINTED CIRCUIT BOARD
HE'
,,·GNO
JlPC12.43C
COMPONENT LAYOUT
r--------------- -,
AF
OUTPUT
jlPC1243C.
R1:
R2:
R3:
R4:
RS:
1kS1
2.2 kS1
33 S1
10 kS1
10kS1
C1
C2
C3
C4
Cs
Cs
C7
Cs
Cg
C10
C11
C12
C13
C14
C1S
C16
174
:
:
:
:
:
0.022pF
0.022pF
0.022pF
0.022 pF
47 pF
: 0.022pF
: 0.01 pF
: 0.022pF
: 22pF
: 10 pF
: 10 pF
: 0.022pF
: 33)lF
: 0.022pF
: 2.2pF
: 0.022pF
Ceramic
Ceramic
Ceramic
Ceramic
Chemical
Ceramic
Ceramic
Ceramic
Chemical
Chemical
Chemical
Ceramic
Chemical
Ceramic
Chemical
Ceramic
:
VR
:
OSCCOIL
:
IF1
:
IF2
:
ANT.CO.
Air vari. con. :
Signal meter:
1 kS1 MAX.
RWR-4320SN
CFT-4SSB
RMC-4319SC
AR12 cJ>- 120
FB621 U
SOO pA MAX.
,uPC1243C
TOTAL HARMONIC DISTORTION vs. INPUT
SIGNAL
DETECTOR OUTPUT VOLTAGE AND SIGNAL
TO NOISE RATIO vs. INPUT SIGNAL
Vee=12 V
mVr.m.s.
f=1 MHz
fMOD=400 HZ,MOD=30 %
~
o dB= 180
CD
CD
"0
"0
Q)
2
0
~
0 "0
0::
>
::;
~
'0
-
r----
0-
r----
z -20
.8
0
:::l
u -40
~bO -40 .8
(j)
~
/
Cl
I
"en
--
-----~-
I -60
/
---
'"
----
-
o
20
40
-
i5
4
u
'c
0
-- - - f--
~
3
ro
2
i \
l\
\\
::x:
f--
'\
'0
"-
~
"i'o....
100
120
140
.......
40
20
0
Yin -Input Signal- dB/m
0
-10
-20 ....-
I
-
,
--
r-
~
a;
Q)
!t
I
r--
!t
~
-
~
" -/
-30
~
~
2 IF
-
I/"I\ I
\V
f---- f---'
i\.
-50
40
60
Vee=12V
Q)
2
"0
>
::;
0.8
-5
0
0.6 --
f---
--
f-
.....
0.4
rI
0::
I
80
f--
F
>
/'/
V
/
J
I
V
t--
100
120
140
20
40
§ 6
2
g
:::l
-5
o
-2:~
Vo
-4
5
~~,-'f--
Cl
I
-8 E f--10 ~ 3
Cl
~
>
-14 ~ 2
-16 I
-18 q 1
-20
-22 0
10
i3
,-
"0
'"'"
80
Ero
I
T.H.D.
20 30 50
100 200300 500
-
1k
140
c:
0
n
Q)
I
+
'w
0::
~--
60
.......
40
/
-
-I--
---
:::-
IF. Rej.
-
....-, /
0
2 k 3 k 5 k 10 k
fMOD - Modulation Frequency - Hz
-
+
-- - - I -
-Image Rej.- -
20
I
120
Vee=12 V
fMOD=400 Hz
MOD=30 %
Vo=10 mVr.m.s.
100
0::
--+-
\
100
CD
I
'"
I
~ -12 ro
~
f--.-
"\
-6'~ 4
80
IF REJECTION AND IMAGE REJECTION vs.
FREQUENCY
Vee 12 V
Vj=100 dB/m
fMOD=30 %
I
ot0
60
Yin -Input Signal- dB/m
~
~bO
-- r -
0.2
LO
DETECTOR OUTPUT VOLTAGE AND TOTAL
HARMONIC DISTORTION vs. MODULATION FREQUENCY
"0
-
--
Yin - Input Signal- dB/m
CD
I
140
I---i--
I
0
20
120
L t-
>
c
r--U
I
LO
'\
-40 f-- ---
o
f - - c---
~
--
30 % MOD-
100
PIN 15 OUTPUT VOLTAGE vs. INPUT SIGNAL
Vee=12 V
f=1 MHz
fMOD=400 Hz
MOD=30 %
CD
80
Yin - Input Signal- dB/m
TWEET vs. INPUT SIGNAL
"0
60
_-
80 % MOD
r--...... -...Lf
l_
\
c:i
::C
~
80
60
~ .....
I
SIN
--
0
>
I
!
~
-
Vo
- -
~-
~+~
-
.e -20 - -
z -60
0
5
t
20
I
I
Vee=12 V
f=1 MHz
fMOD=400 Hz
I
c:
........ ..,/
I
T
-
--
1.5
0.5
f - Frequency - MHz
175
JlPC1243C
ONE-SIGNAL SELECTIVITY
FREQUENCY
VI.
MAXIMUM·SENSITIVITY AND TOTAL
HARMONIC DISTORTION VI. SUPPLY
VOLTAGE
DETUNE
~
~
I 5 I
5 z;.
~
80
\
III
-c
I
60
\
z;.
.s:
40
~
,
/
\
(/)
20
tIO
en
IV
-30
-20
-10
~f -
/
o
VCC=12 V
f=1 MHz
fMOO=400 Hz
MOO=30 %
Vo=10 mVr.m.s,
+10
+20
+30
Delune Frequency - kHz
CIRCUIT CURRENT
VI.
SUPPLY VOLTAGE
No Signal
16
<
15
L..-
ICC
E
I
,-1:: 14
~
--
--
:J
(.)
... 13
'5
f:!
U
I 12
(.)
£}
11
10
8
9
10
11
12
13
Vee - Supply Voltage - V
176
)(
:I: 2 ~
\ /
0
-20
V
/
t\
Q)
coc
/
14
15
~
~
q
MA X. ~ens
:~
]? 4 ~ O
o ~ 2
.~ 3 E 4
o
:J
E .§ 6
8
'.10
1
~
en
12
>< 14
~O~
l'
1
~t
X.sens..:.!) dB
{Vin=37 dB
Vo,=10 mV
T.H.O.
f'in=130 dB
M9 0 =80 %
I
T
I
I
-- -I
8
9
I
T.H.O.
!--
10
11
12
13
Vee - Supply Vollage - V
14
'._
15
BIPOLAR ANALOG INTEGRATED CIRCUIT
J1PC1163H
FM IF AMPLIFIER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The J,.LPC1163H is a semiconductor integrated circuit for FM·I F amplification, and contains a emitter followered differentia'l
amplifying stage and a constant current source. The limiting characteristics for AM signals of the J,.LPC1163H are excellent, and
since it has been designed to minimize distortion at high level inputs, it is most suitable for use in high class FM·IF amplifiers.
FEATURES
• The distortion characteristics at high level inputs are excellent.
• The group delay characteristics of the FM·IF circuit have minimum disparity.
• A terminal for varying the constant current is provided, enabling 10 to be varied from 4.5mA to 15mA.
This makes possible its employment as a driver for ratio detector.
• Very few external components are required.
• High stability for parasitic oscillation.
• Capability for cascade connection.
• Wide range of supply voltage: 10V to 15V
EQUIVALENT CIRCUIT
7 )"'--+---+--f
PACKAGE DIMENSIONS
in millimeters (inches)
19.5MAX.
(O.77MAX.)
CONNECTION DIAGRAM
Pin No.
1
MARKING
2
3
4
6
7
Electrical
Connection
2
Vcc
OUTPUT
3
BYPASS
4
GND
5
6
7
BYPASS
INPUT BIAS
INPUT
177
,uPC1163H
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage
Vcc
15
V
Output Collector Voltage
Vz
20
V
Voltage Between Input Terminals
Vi
5
Vp-p
Power Dissipation
Pd
Operating Temperature
T opt
- 20 to
+75
°c
Storage Temperature
T stg
-40 to +125
°c
10'" 12'" 15
V
270 (Ta = 75°C)
mW
RECOMMENDED OPERATING CONDITIONS (Ta = 25°C)
Supply Voltage
VCC
ELECTRICAL CHARACTERISTICS (Ta = 25°C, Vce = 12 V, f= 10.7 MHz)
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
ICC
6.0
8.6
13.0
mA
Vi=O
Output Current
IC
1.5
2.1
3.2
mA
Vi = 0, 1 pin Current
Voltage Gain
Av
26.5
30.0
33.5
Supply Current
dB
Vi = 20 mA, R1 = 1 kn
Cin
3.0
pF
Vi =30mV
gin
0.01
m'U
Vi =30mV
Output Capacitance
Co
3.4
pF
Vi=l00mV
Output Conductance
90
0.035
m'U
Vi=loomV
Forward Transfer Admittance
IYfl
36.6
m'U
Vi = 100 mV
0.0038
m'U
Vi = 100 mV
I nput Capacitance
Input Conductance
Reverse Transfer Admittance
IYrl
TEST CIRCUIT
• IcC,
Au
L1
L2
1kQ
L= 1 ~H
0 0 ~ 50
{ Rs ~ 0.5 n
Self-Resonance Frequency ~ 18 MHz
{
00~100
I nterna I Capacita nce = 82 pF
fo=10.7MHz±3%
RF V.V
S.G.
RG=50Q
f= 10.7MHz
O.022.tLF
1J1FI
0.022
.178
5
PM=30dB
(TOA)
tLPC1163H
• 9in, Cin
RX
METER
5-_
0.022,uF
1
0.022
,uFI
RX METER
TYPE 250-A (BOONTON)
• 90, Co
RX
METER
RX METER
TYPE 250-A (BOONTON)
• Yf
S.G.
R(;=50Q
f=1O.7MHz
RF VOLT METER
8405A (YHP)
• Yr
S.G.
RG=50Q
f= 10. 7MHz
RF VOLT METER
8405A (YHP)
179
,uPC1163H
TYPICAL CHARACTERISTICS (Ta =25°C)
VOLTAGE GAIN, PHASE VI. FREQUENCY
(Measure in Differential Circuit)
OUTPUT VOLTAGE vs. INPUT VOLTAGE
(Measure in Differential Circuit)
10000
0
30
",..
/
1000
~-80
V
100
-140
V
10
-160
-ISO
.s-
aI
J
0
I
>
1.0
33012 7
Hmo
Rc
S,G.
l
If
0.1
.",
0.01
-20
2
Vee
IN
I
6
~"
3
R,lkQ
1
2
OUT
O,022pF
Vec=12V
RL lkQL Load
Rc 33012
-'
0
20
40
60
80
Vin -Input Voltage-dB,uV
100
120
OdB,uV= l,uV
RESISTER FOR 3 pin, VOLTAGE GAIN
CONSTANT CURRENT
(Measure In Differential Circuit)
r
200
50
VS.
Vcc= 12V
f=10.7MHz
I- Vi=10mV(SOdB,uV)
RL = lkoQ L Load
lao
160
Of
I
'a.
...
I
c:
l>'
~
(!)
.E 120
~
40
'iii
(Y")
'iii
co
"C
c: 140
100
Q)
0:::
80
~3O
.... i""""
.B
'0
>
I
40
~ ~"" L
~
\
10 \
10
,
\
20
0
~
~
<20
60
180
'-
\ ,
-120
<
J
IlO
'0
Av i"""
qJ
-100
.B
'0
> 0
I
>
E
I
Q)
S-
IlO
........
"- ~
'\I
Q)
Vcc= 12V
R.=51Q
,~
~-6O
J
:;
~r--~
~-4O
-
r-.;...
f"""'o.. .........
-20
II
.B
>
.....
2
3
5
7
10
lo-Constant Current-rnA
15 20
30
20
10
5
f-Frequency-MHz
30
50
100
,uPC1163H
INPUT RESISTANCE AND CAPACITANCE
vs. INPUT VOLTAGE
(Measure in Differential Circuit)
OUTPUT RESISTANCE AND CAPACITANCE
vs. INPUT VOLTAGE
(Measure In Differential Circuit)
Vcc= 12V
IJ...
0.
12
120
10
100
c:
c:
'u
<0
<0
"til
8
a.
'iiI
6
<0
CIJ
a:: 60
"5
0.
U
Vcc= 12V
f=lO.7MHz
CIJ
u
19
80
c:
"5
0.
T
~ 100
I
I
u
0.
<0
~ 10
Q)
CIJ
8
'u
<0
u
120
I
CIJ
u
2
Ri
~
I
12
f=10.7MHz
g
80
tl
'11\
CIJ
6
a::
60
c:
T
4
40
Co
....... ........
0:
c.5
2
20
o
o
o
20
Ci
40
60
100
Vin-Input Voltage-mV
140
120
80
Ro
2
20
o
o
o
3.0 r-- r--
Kl
Kl
E
I
u 0.2
12.0
c:
to
c:
to
U
J
:::J
"50.
en
"5
0.
T
T
c:
0.1
.is
bi
/
.11'/
2
3
5
J
~
'5
.s:::J
'i' 0.1
IL
0
llO
-
120
140
Vcc=12V
f--
Vin=l00mV
CIJ
,
J
:::J
en
'5
~
a:::J
/1
./1
0
I 1
0
.c
bo~"
~v
gi
20 30
10
f-Frequency-MHz
100
E
I
c:
U
I
1.0
80
Kl
~ 2
c:
20.
0
I
c:
3
2u
:::J
'0
~
c:
U
0
g 0.2
I
u
C.
CIJ
:::J
'0
t.ii
0.3
Vin=30mV
E
CIJ
60
OUTPUT ADMITTANCE vs. FREQUENCY
(Measure In Differential Circuit)
Vcc=12V
Kl
E
I
40
Vi n-Input Voltage - mV
INPUT ADMITTANCE vs. FREQUENCY
(Measure in Differential Circuit)
0.3
20
50
100
200
2
3
--
~
go
......
5
10
20
30
50
100
200
f- Frequency-MHz
181
,uPC1163H
FORWARD TRANSFER ADMITTANCE
vs. FREQUENCY
REVERSE TRANSFER ADMITTANCE
vs. FREQUENCY
(Measure in Differential Circuit)
(Measure in Differential Circuit)
Vcc= 12V
Vcc= 12V
60
0.06 >-- I---
Vin=lOOmV
Vin=l00mV
I.
[0
~
E
~
I
I
g
!';l
Q)
t
~
t
:g
0.05
C1l
50
'E
"0 0.04
«
40
«
I
if
!\,
C1l
Vi
c:
~
;::.
2 30
j
0.03
!';l
I
~
"
1/
CI.J
0.02
>
CI.J
~
cr:
I
~ 20
I
)
>;
0.01
j..Oii'"
10
2
3
o
1
2
3
20
10
30
V
II
5
10
20
f-Frequency-MHz
50
f-Frequency-MHz
VOLTAGE GAIN, V2, V3, CI RCUIT CURRENT
vs. AMBIENT TEMPERATURE
(Measure in Differential Circuit)
Vcc= 12V
f=1O.7MHz
Vin= lOmV(80dB,uV)
15
«
E
co
I
V2
1-c:
"0
c:
'iii
>10
I
(.!)
->
C1l
bO
.s
'0 40
>
I
160
%
0
I
.......
, .....
I""i"o
~
qJl'\
"
~
l\I'
20
Vee
II
I
RL
1
7
!,PC1l6
6
0022!'F
V
S.G.
R,,7!i.Q
Eft
5
OUT
2
3
4
o
F=
~
I--
2
1
3
5
10
20
30
50
100
f- Frequency -MHz
I-I--
lOO22!'F
Vrr=l2V
RL=lkll
751!
f=lO.7MHz
II
"
40
V
0.1
"""r-...
80
I
l.0
Av,""
60
II
;:
.......V in = 10mV(80dB,uV)
100
::J
a
t-....
"J 140
;;
So 120
c:
.iii 20
if
100
>
E
I
180
I
I
Rg =51Q
L Load
~
F=
~
e-
I--
0.0 1
-20
0
20
40
60
80
100
Vin-Input Voltage-dB,uV
120
140
OdB,uV=l,uV
CIRCUIT CURRENT, VOLTAGE GAIN vs. SUPPLY VOLTAGE
50
20
18
« 16
E
1-c:
t
::J
u
14
12
~
'-'
'-'
'-
-
f---
f= 10. 7MHz
RL= 11& L Load
V in = lOmV(80dB,uV)
I edNO SIGNAL)
40
8
6
4
I
.~
'"
<..:)
""
1/'
,
/
2
0
,
ci.
10
0
~
I
20
2
0
~
30
ClJ
bD
>
I
-- -.... '
!
I-- -- -,Oi\\ere(\~~~
Circuit ~ ~
o
Av
C~~
.... ........
"0
·s 10
U
I
CD
-
1/'
_.... """
5
,.
10 ,
........... ~
/'
,
,
......
,,-"
V
\
Circuit
A"
L
. /V
~
....
... "'"
... "
~
Icc
10
15
20
Vee-Supply Voltage-V
183
jlPC1163H
TYPICAL APPLICATIONS
• FM-IF amplifier using a ceramic filter.
n
IN
Rl
OUT
I coFI
t:::::I
t:::::I
L\
L2
Vee
R1 to R4 :
C
:
L1 & L2 :
C. F.
:
Match to the impedance of the ceramic filter.
High frequency bypass capacitors. 0.022 pF ceramic capacitor.
Decoupling inductances of the power supply circuit.
Ceramic filter.
• FM-IF amplifier using a Ie
IN
filter~
0---'"
..--t----oOUT
1FT
LC Filter.
Vee O - - - - - . J
~--------------~---~Vec
R1 & R2 : Match to the input and output impedance.
C
: High frequency bypass capacitors. 0.022 JJF ceramic capacitors.
L1 & L2 : Decoupling inductances of the power supply circuit.
1FT
: FM intermediate-frequency filter coils.
PLF (Toko Company)
184
jlPC1163H
• FM-I F detector circuit.
IND----.
:
:
:
:
Match to input impedance.
High frequency bypass capacitors. 0.022 J.LF ceramic capacitors.
FM detector filter coil.
Registor for adjusting detector drive current.
(Adjustment of constant current 10 .)
• Recommended line-up for high class stereo tuner.
r--------------------------------~-----,
I
I
I
I
I
r-----.
I
I
I ____
: L.C.
I filter
:
LI
,uPC1l63H
L.C.
filter
,uPC1l63H
L.C.
filter
,uPC1l63H
,uPC577H
OUT
~
,uPC1l63H: FM detector
Detector I
section
FM-IF limiter secti.:m.
stage
:
driver
________________________________ I __
_ _ _ JI
~
Precautions on the use of the J,LPC1163H.
1. When the J,LPC1163H is used with a discrete resistor connected between pin 3 and ground, caution
must be taken so that Pd does not exceed 270mW at 75°C with the change of the differential constant current 10 from 4.5mA to a maximum of 15mA.
2. The recommended operating supply voltage of the J,LPC1163H is 12V, and it should be used within
a range of 10V to 15V. Since the dielectric strength of the output terminal 2 is 20V~ care should
be taken not to exceed this voltage when a tuned load is used.
185
BIPOLAR ANALOG INTEGRATED CIRCUIT
J,lPC1167C2
FM IF SYSTEM WITH QUADRATURE DETECTOR
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The pPC1167C2, a monolithic integrated circuit, is a FM-I F system with Q-DET for use in Hi-Fi FM stereo tuners.
This device includes three-stage IF amp1ifier/limiter, quadrature detector, AF preamplifier and specific circuits for AGC, AFC,
muting (squelch), signal meter and center meter.
The external form is 16 pin, dual in-line plastic package.
FEATURES
• Exceptional input limiting sensitivity.
: 25 dBpV TYP.(-3 dB point from VOAF with 100 dBpV input)
• High AM Rejection Ratio.
: 55 dB TYP. (Vi = 100 dBpV, AM,: 400 Hz, 30 % MOD.
FM : 400 Hz, 75 kHz, DEV.)
• Low Total Harmonic Distortion.
: 0.02 % TYP. (Vi = 100 dBpV)
• High recovered audio voltage.
: 340 mV TYP. (Vi = 100 dBpV)
• Low transient noise at mute circuit turn-on and off.
• Adjustable muting sensitivity.
: 27 dBpV TYP. (VR1 = open)
35 dBpV TYP. (VR1 = 33 k!1)
• Adjustable muting band width.
: BW(MUTE) =±75 kHz TYP. (Vi = 100 dBpV, V 12 = 1.4 V, R7 = 5.6 k!1)
• Wide range of power supplies.
: 8.5 V to 14 V
19.4 MAX.
(0.763 MAX.)
PACKAGE DIMENSIONS
in millimeters (inches)
R1
(R 0.039)
0-15°
18S
jlPC1167C2
FUNCTIONAL BLOCK DIAGRAM
15
16
,
14
.f13l
,
/
~
Y
MUTE
S Meter
CIRCUIT
CIRCUIT
I
I
12
11
I
1
10
I"9l
1
MUTE
DRIVE
CIRCUIT
I
r---
OR
oV
Level
CIRCUIT
SWITCH
DET.
•
Level
Level
Level
DET.
DET.
DET.
Quadratur
DET.
1st IF
~
>----
1
AMP
I
L:..J
}-
2nd IF
3rd IF
AMP
AMP
t
AUDIO
MUTE
t-CIRCUIT
I
~
3
I
4
I
J
5
AMP
II
I
-,
AUDIO
6
AFC
AMP
1
7
8
I
TERMINAL CONNECTION
TERM. NO.
CONNECTION
1
IF INPUT
2
TERM. NO.
CONNECTION
9
DETECTOR INPUT
INPUT BYPASS
10
REFERENCE BIAS
3
INPUT BYPASS
11
VCC
4
GND
12
MUTE DRIVE OUTPUT
5
MUTE CONTROL
13
SIGNAL METER OUTPUT
6
AUDIO OUTPUT
14
GND
7
AFC OUTPUT
15
AGC OUTPUT
8
IF OUTPUT
16
MUTING SENSITIVITY ADJUSTMENT
187
,uPC1167C2
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage
VCC·
15
Supply Current
ICC
40
rnA
V
Input Voltage
VI
3
V _
p p
Package Dissipation
PD
420"
mW
Operating Temperature
T opt
-20 to +60
°C
Storage Temperature
T stg
-40 to +125
°C
*Ta=60 °c
RECOMMENDED OPERATING CONDITION (Ta=25 °C)
CHARACTERISTIC
Supply Voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
8.5
12
14
V
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
(Vec = 12 V, f= 10.7 MHz, fMOD = 400 Hz, f=±75 kHz DEV.,
CHARACTERISTIC
Supply Current
SYMBOL
MIN.
TYP.
MAX.
UNIT
ICC
14
23
31
rnA
25
31
dBJJV
340
460
mV
0.02
0.2
I nput Limiting Voltage
Vi(lim)
Recovered Audio Voltage
VOAF
Total Harmonic Distortion
T.H.D.
Signal to Noise Ratio
AM Rejection
Muting Sensitivity
240
TEST CONDITIONS
No Signal
-3 dB point from VOAF
with 100 dBJJV input
Vi = 100 dBJJV
%
Vi = 100 dBJJV
75
81
dB
Vi = 100 dBJJV
A.M.R. (1)
45
55
dB
Vi = 100 dBJJV
AM : 400 Hz, 30 % MOD.
FM : 400 Hz, 75 kHz DEV.
Vj(MUTE)1
19
27
SIN
35
dBJJV
V12= 1.4 V, VR1 =Open
V12= 1.4 V, VR1 =3.9 kn
35
dBJJV
Muting Attenuation
MUTE (ATT)
69
75
dB
V 5 = 2 V, V R 1 = Open
Muting Band Width
BW(MUTE)
90
150
kHz
Vi= 100 dBJJV, V12= 1.4 V
R7=5.6 kn
V12(1)
4.5
6.0
Vi(MUTE)2
Mute Drive Output
V
Vi=O dBJJV
0
0.3
V
Vi = 100 dBJJV
V13(1)
0
0.3
V
Vi=O dBJJV
V13(2)
2.0
V
Vi =70 dBJJV
V12(2)
Signal Meter Drive Output
AGC Output
V13(3)
3.0
4.0
V
Vi = 100 dBJJV
V15(1)
5.0
6.0
7.0
V
Vi =0 dBJJV
0.1
0.5
V
Vi = 100 dBJJV
V15(2)
IBB
Rg = 330 Q)
jlPC1167C2
TEST CIRCUIT FOR ELECTRICAL CHARACTERISTICS
Multipath Output (}-_ _ _.....-_ _ _ _ _ _......_ _ _--.
VCC
2.2 J.lH
RI2
rO.022 pF
33 k
AGC for RF AMP
47 kQ
2.2 kQ
AFC OUTPUT
MUTING ON
0.022 J.lF 300 Q
+
75 Q
0.022PF
+
1
S1
12kQ
0.47 J.lF
MUTING
OFF
+
1
to STEREO THRESHOLD
LOGIC CIRCUITS
AUDIO OUTPUT
RL
20 kQ
V.T.V.M
M,
: Center Meter
VA'
: Muting level adjusting
semi-fixed potentiometer
5,
: Muting switch
52
: Muting level adjusting switch
T2
: TKAEA25868 X
l,
: 7BA220
(K.K.TOKO)
L2
: 7BA2A2K
(K.K.TOKO)
T,
: TKAEA24638 AUO (K.K.TOKO)
(K.K.TOKO)
18S
,uPC1167C2
TYPICAL APPLICATION (Top View)
Signal Meter
VR3
30 k.Q
Vee
S3
f
Multipath Output
VR4
50 k.Q
AGC
47 k.Q
100 k.Q
2.2 kQ
S2
Muting Level
Sensitivity
VRI
t
50 kQ
0.022 f.1. F
5V~~0.022
""1
330 Q
FMIF~~n
c:::::J
AFC OUTPUT
12 I
>
N
>
0
:i
('r')
~
0.3
\
70
Vec=12 V
fFM= 10.7 MHz
RG=330 Q
0.9
, A.M.R.
~
>
1.0
I
r\
~
50
en
1
1 1 1
I 1 1
0.8
VCC=12 V RG==330 Q
fFM = 10.7 MHz, ~f=75 kHz dev.
0.7
fMOO=400 Hz
'AM=400 Hz(30 % MOO)
0.6 ~
I~'
20
.:3
VOAF
l/
10
T
11 1
1 1 1
1 1 1
1 1
1 1
.....
0.2
"- -60
-
.-1
70
....- '--80 90 100
'\
1\ 1\
5
,
4
V12
1\ 1\ ( M_uting Drive )
2
\
\
0.1
.--1
0
o
10
,
.... f-
I\,.H
30 40
20
50
f---
-10
I I
CO
LL
-30
1 1I
1
1/
1-.....
;
I-f-- 1--1-1- f -
--·40
CO
.:3
I
>
-
'-V12
-
.s
::J
1
fMOD=4oo Hz
Vi=loo dBJlV
R7=5.6 k Q
\
,
,
-50
::!:
I
-60
-60
--
1
- --.
-70
..--- . . . r... 1\ i
i 1
1 1
o
10
20
30
40
50
Yin
60
70
80
90
- 100
100 110 120
(dB,u)
1
,
I
1
1
1
I
1
-80
-80
,
7
VCC=12 V
fFM = 10.7 MHz
~f=75 kHz dev.
I
,
~ -40
-50
-70
-30
f-I-
~
VR 1=OO Qt- TRl=33 kQ
~
o
-20
I 11
11111111
1 1 1 1 I liT
-10
Vee= 12 V RG=330 Q
fFM= 10.7 MHz
M=75 kHz dev.
I
17
111
I
0
I I I
i
I
-20
.:3
I"
I I
I \
70 80 90 100 110 120
60
Fig.4 Mute ATT. vs. CARRIER FREQUENCY
1
1
---vOAF /
,/ (5 'lTletet
Vin (dB,u)
Fig. 3 VOAF vs. Vin
1 1
-
\
1'1
Vv13
,
Yin (dB,u)
o
\
I
If-
1\
V15
(AGe)
f-~
\ ,VRl-33 kQ
3 ~ VRI Open
110 120
_
i
I
6
.- -I
,
,
1
4
1
3
1
2>
:
I
~
N
i
/' MUTE ATT.
II 1"'1-+-4-1
I
o
II II 1
I I I
- 50
0
+ 50
+ 100
CARRIER FREQUENCY: fc 10.7 MHz ± ilf kHz.
Fig. 5 VOAF, T.H.D. vs. MODULATION FREQUENCY
I II I
0
-
-
vOAF
I
co
"'" I"':
-20
.:3
LL
0.2
I'
-,...--
Vee 12 V
fFM=10.7 MHz
~f=75 kHz dev.
I
0.15
f--t-f--VOAF: fMOO=400 Hz f--- 0.1
f---
-30
~
0
>
.....
I
-10
-40
;
0
:i
~
II
/
0.05
17
I
-50
~
THO.
I ill!
-60
50 70
200 300
500 700 1 k
0
2k 3k5k
7 k 10 k
MODULATION FREQUENCY fMOD
20 k
(Hz)
193
,uPC1167C2
Fig. 7 BW(MUTE) vs. R7
Fig. 6 VR 1 vs. Vin
VCC=12 V
. fFM= 10.7 MHz
f MOD=400 Hz
~f=75 kHz dey.
i
60
Vcc= 12 V
fFM= 10.7 MHz
VIN= 100 dBJl V
fMOD=400 Hz
~f=75 kHz dey.
600
---c--1.0
50
500
I
-c---
Cl
-=-
N
40
~
Cl
U
.r::
>
ro
400
WI-
=>
IL
rX 30
:9}
\
I
-=-
j
i
\
::';!
\
/
~ 300
~
\
~ 0.5
'\
rr:
20
I
'\
200
\
o
o
o
I I
I I
I 1
20
30
40
Vin
194
100
-R- - - - V R - - -
10
50
(dBjiV)
60
1
\
\
I
I
!
\
'\
10
!
CD
70
80
90
100
o
I
i
,!
~
10
i
i
I
r- r-l.
-I-- I--
20
R7
I
i
-....
30
(kQ)
i
!
I
!
i
40
50
BIPOLAR ANALOG INTEGRATED CIRCUIT
JLPC1161C3
FM MULTIPLEX STEREO DEMODULATOR
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
ThepPCl161 C3 is a silicon monolithic integrated circuit for FM mUltiplex demodulator developed for high class stereo FM tuners.
As the IC adopts a PLL (Phase Locked Loop) system, complexity of control usually experienced when using conventional external coil is eliminated and the demodulator can easily be constructed by simply controlling the external semi-fixed potentiometer. Internal circuits are composed of a stereo demodulator, a lamp driver, an input stage pre-amplifier that is capable of
establishing variable input signal levels, a VCO (Voltage Controlled Oscillator) constituting PLL, a phase comparator, a LPF
(Low Pass Filter), a frequency divider, and a DC amplifier. A stereo-monaural automatic switching circuit, a circuit for manual
switching, VCO forced stop circuit etc. are built-in.
FEATURES
o External parts are small. Coil is not used.
o Low monaural total harmonic distortion.
T.H.D. = 0.02 % TYP , at f= 1 kHz.
T.H.D. =0.03 % TYP, at f= 10 kHz.
o Low stereo total harmonic distortion.
T.H.D. = 0.02 % TYP , at
T.H.D. = 0.06 % TYP , at
T.H.D.=0.12 % TYP, at
o High channel separation
Sep. = 55 dB TYP , at f=
f= 1 kHz (L+R).
f = 10 kHz (L or R).
f= 10 kHz (L+R).
1 kHz.
o Built-in output stage post amplifier.
Vout = 1.5 Vr.m.s. TYP , at V in = 300 mV.
V out =3.5 Vr.m.s. TYP, at V in =700 mV.
• Stereo-monaural switching can be made either automatically or manually from outside. The shock noise at switching is reduced considerably.
• Stereo-monaural switching operation is perfectly synchronized with a stereo indicator lamp.
• Monitoring of VCO free running frequency can be performed by directly connecting the frequency counter to No.
g terminal.
• High signal to noise ratio.
SIN = 82 dB TYP , at Vin = 300 mV.
o Wide maximum input level.
Vin = 700 mVr.m.s , T.H.D. = 1 %.
PACKAGE DIMENSIONS
in millimeters (inches)
194 MAX
(0 763 MAX)
TERMINAL CONNECTION
No.
1
,r~~~0~7)!625~~~3)
a·"Jl.
: ' II
25
II
No.
CONNECTION
9
ST. LAMP & 19 kHz MONITOR
2
10
LOW PASS FILTER
3
PRE AMP O.UTPUT
11
LOW PASS FILTER
4
POST AMP BIAS
12
DETECTOR INPUT
:":
5
POST AMP BIAS
13
LOOP FILTER
i
6
R·CH OUTPUT
14
LOOP FILTER
762
•
(01)
(0019)
CONNECTION
Vee
PRE AMP INPUT
(001)
0-15
7
L-CH OUTPUT
15
OSC RC. NETWORK
8
GND
16
ST.-MONO. SW & VCO STOP
NOTE: Numerical values show TYP. values unless otherwise designated.
195
,uPC1161 C3
FUNCTIONAL BLOCK DIAGRAM
VCO
76 kHz
ST-MONO SW
VCO STOP
SW
PILOT
PRESENCE
DETECTOR
PHASE LOCK
DETECTOR
38 kHz TO
19 kHz
DIVIDER
76 kHz TO
38 kHz
DIVIDER
STEREO
SWITCH
LAMP DRIVER
38 kHz TO
L CH
POST AMP
PRE AMP
STEREO
DEMODULATOR
NF AMP
R CH
POSTAMP
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage
15
V
75
400*
mA
VCC
Lamp Current
IL
Package Dissipation
Po
mW
Operating Temperature
T opt
- 20 to +70
Storage Temperature
T stg
- 40 to +125
°c
°c
*Ta=70 DC
RECOMMENDED OPERATING CONDITION (Ta=25 °C)
CHARACTER ISTIC
Supply Voltage
196
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
9
12
15
V
,uPC1161C3
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
(Vcc=12 V, f=1 kHz, R1 =47 kn, R+L=270 mV, Pilot=30 mV)
CHARACTERISTIC
Supply Current
Channel Separation
Voltage Gain
Channel Balance
SYMBOL
MIN.
TYP.
ICC
12
20
40
50
dB
45
55
dB
Sep.
Av
T.H.D.
Stereo Total
Harmonic Distortion
T.H.D.
UNIT
30
mA
dB
f= 10 kHz
17
dB
Monaural, Vin = 300 mV*
-1.5
0
1.5
dB
Monaural, Vin = 300 mV
-1.5
0
1.5
dB
Stereo, Pilot = 30 mV
0.02
0.1
%
0.1
%
0.02
f= 100 Hz
%
R+L= 270 mV
Pilot = 30 mV
%
6
dB
±3
%
Pilot= 30 mV
19 kHz Rej.
35
dB
Pilot = 30 mV
38 kHz Rej.
45
dB
Pilot= 30 mV
20
mVr.m.s.
f = 1 kHz
f= 10 kHz
±1.5
Hy.
C.R.
SCA Rejection
Vin=300 mV
12
Capture Range
f = 1 kHz
45
6
Stereo Lamp Hysteresis
Ultrasonic Frequency
Rejection
Pilot= 30 mV
13
0.12
L-ON
f=100Hz
9
0.02
Pilot Level for Lamp On
TEST CONDITIONS
No Signal
35
C.B.
Monaural Total
Harmon ic Distortion
MAX.
Pilot Level, R,=47 kn.
Pilot Level
SCA Rej.
70
dB
Maximum I nput Level
Vin
0.7
Vr.m.s.
Signal to Noise Ratio
SIN
82
dB
Vin = 300 mV, After LPF
Stereo-Monaural Switching
SWoON Voltage
Vs
1.4
1.6
V
No. 16 Terminal Voltage
Where Stereo Lamp-O F F
VCO Stop Voltage
Vo
VCC
V
No. 16 Terminal Voltage
Where VCO Stops
7
Pilot = 30 mV, SCA = 30 mV
Monaural, T.H.D. = 1 %
* Av is from the output level measured at I C output terminal. Av can be set by the input impedance R,.
197
,uPC1161C3
TEST CIRCUIT FOR ELECTRICAL CHARACTERISTICS
19 kHz Monitor
470 pF
3.3 !IF
1 kQ
Stereo Lamp
VC)
0----0
Vs
Lamp Protecting
Resistor
S3
MPX Input
r
SOOPF
+
22 kQ
1 000 pF
3.3 kQ
Rch·OUT
-
10IlF
Sep. Adj.
500 kQ VR
LPF
3.3 kQ
10 IIF
+
1 000 pF
-
Lch·OUT
3.3kQ
LPF
veo Adj.
Sep. Adj.
S1
S2
S3
BL-13 (K.K. KORIN)
veo tuning semi-fixed potentiometer
Separation adjusti ng semi-fixed potentiometer
Vee ON-OFF SW
SW tor 19 kHz monitor
SW for veo stop
NOTES:
1. Use polystyrene capacitors for that connected to No. 15 terminal to compensate the
temperature coef. of veo.
2. For adjusting the veo oscillation frequency, make S2 open, connect the frequency
counter to No.9 terminal 19 kHz monitor and then set by varying the semi-fixed
potentiometer veo Adj. connected to No. 15 terminal
3. For separation adjustment, vary the semi-fixed potentiometer Sep. Adj. connected
between terminals No.4 and No.5 to set at the best point.
198
,uPC1161 C3
TYPICAL APPLICATION
19kHz Monitor
1 kQ
Vs~1.6
V
01----St. -Mono
manual SW
ON-+
veo
STOP
0.047IiF
MPX input
I
47 kQ
Rch·OUT
+
500 pF
1000 pF
3.3 kQ
10/ I F
Sep. Adj.
10 ."F
500
k~2
L.P.F.
VR
101lF
22 kQ
+
1 000 pF
1001lF
Vee
+12 V
3.3 kQ
Lch·OUT
+
lO,uF
LPF
VCO Adj.
Sep. Adj.
*470 pF
BL-13 (K.K. KORIN)
VCO tuning semi-fixed potentiometer
Separation adjusting semi-fixed potentiometer
Polystyrene capacitor
NOTES:
When the unit is used with power supply voltage of less than 12 V, the mid- point electric
potential of the output terminals 6, 7 in the above typical application may change and
Total Harmonic Distortion at output terminal will increase.
In this case change the bias registor 47 kn between terminals 5, 6 and terminals 4, 7 and
keep at mid-point electric potential.
199
,uPC1161 C3
EXAMPLE OF PRINTED-CIRCUIT BOARD (Unit: mm)
100
o
o
(Bottom View)
OUTBOARD COMPONENTS MOUNTED ON A PRINTED-CIRCUIT BOARD
+Vcc
stereo·monaural switching
-----co~
MPX input
VCO STOP
Rch·OUT
Lch·OUT
(Bottom View)
200
Rl=47 kQ
R6 =47 kQ
Rll=15kQ
Cl=I00J.lF
C6 =1000 pF
Cll=lOJ.lF
Sep. Adj. =500 kQ VR
R2=10 kQ
R7 =3.3 kQ
R12=3.3 kQ
C2=4.7 flF
C7 =0.22 J.lF
C12=10 J.lF
VCO Adj. =5 kQ VR
R3=22 kQ
Rs =47'kQ
R13=3.3.kQ
C3=500 pF
Cs =1.5J.1F
C13=10 J.lF
BL·13=19 kHz
R.=10 kQ
Rg =3.3 kQ
Ru=1 kQ
C.=O.047 J.lF
Cg =3.3J.1F
C14=10 J.lF
Rs=22 kQ
R10 =1.0 kQ
RL =Lamp
Protecting
Resistor
Cs=l000 of
C10 = 470 pF( Polystyrene
capacitor)
LPF(K.K KaRIN)
tlPC1161C3
ON CIRCUIT GAIN
The circuit gain of the IlPCl161C3 is obtained from, the input stage PRE AMP, the demodulator,
and output stage POST AMP, and can be expressed equivalently from external resister ratio by
following equation :
A2::;: (R3#R2)
+ Rs
R3#R2
Av ::;: 20 log (A1 • A2)
(dB)
">---0 Rch-OUT
6
2
. > - - - - - 1 Demodulator
7
~--o
Lch-OUT
VCCo-----~~---<~----~--~I~--~
The change of the circuit gain in case an input resister R1 has been varied is shown in the following
drawing.
R2=10kQ
R3=22 kQ
Rs =47 kQ
18
en
17
.:s
16
~
15
<......
..
~
i\.
'r\.
14
bO
.9.
"""f'-~
~13
12
"' "'-
11
33
39 43
47
51
R\ (kQ)
56
''"
62
68
201
j.lPC1161C3
TYPICAL CHARACTERISTICS (Ta=25 °C)
SEPARATION vs.
MODULATION FREQUENCY
70
II
II
60
CD
7c:
TOTAL HARMONIC DISTORTION
vs. MODULATION FREQUENCY
~
50
- ......
-~
R-+L
I:
"""
r;
~
I
~~R- f--
..g 40
0
0-e
Vi
is
",-,
u
~
I
MAINJ
I
0
,
ro
c.
~
c:
0.5
0.3
0.2
0.1
'g 0.05 f-R
MONO
~ 0.03 -L
30
7§ 0.02 ,-L
I
g. 20
---
r-- r-- I-~ 1-
R~
o
l-
(f)
I
ci
~
am
~
-
~
~
-- ..
....:::
~otifj
~0.005
a
30 50
100 200 300 500
30 50
1 k 2 k 3 k 5 k 10 k 20 k 30 k
100 200 300 500 1 k 2 k 3 k 5 k 10 k 20 k 30 k
f -Modulation Frequency -Hz
f -Modulation Frequency -Hz
TOTAL HARMONIC DISTORTION
vs. MAIN SIGNAL INPUT VOLTAGE
TOTAL HARMONIC DISTORTION vs.
MODULATION FREQUENCY (STEREO)
f =1 kHz
0.5
~
I
0.3
0.2
c:
0
:p
~
;
0
Vi
0.1
u
.~
0.05 -
is
-
E
ro 0.03
.
:c
0.02
7§
Ronly
Rsub
~Sf
-
I-
I 0.01
~ 0.5
~
I
c:
:e
r-=:=- -
",'Ls~ub
0
Malo
1.0
MAIN
0.3
0
Vi
is 0.2
Lonly
ci
~0.005
u
'c
0
50
100 200 300 500
E
1 k 2 k 3 k 5 k 10 k 20 k 30 k
ro
:c
f -Modulation Frequency -Hz
0.1
Cij
0
I" 0.05
),
ci
~
TOTAL HARMONIC DISTORTION
vs. SIGNAL INPUT VOLTAGE
-'-: -- ....
0.03
~~ L
0.02
L
f=l kHz
~
'-
0.01
1.0
,•
.
0.5
I
c:
0.3
0
0.2
Vi
,
u
'c
0
E
~
",
/
/
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
CHANNEL BALANCE vs.
MODULATION FREQUENCY
!
is
a
~
,,'
,~
Yin-Main Signal Input Voltage-Vr.ms.
.
~
2
0.005
~
~ ~,
......
0.1
ro
:c
CD
7+4~~+H+--~~~++~t--4-4~++~t--+~
Cij
;§ 0.05 .---t---+-+-SUB.R +----+11'-,-+-+---+-~
I.
R.ONLY
\
~ 0.03 t--+--+--t-.......t-'\-'Io~.."!;_,~~r'-+---+-+---l
~
B+3~~+H+-~~r+++~~-+-+~++~~-+~
~+2~~+H+-~~~++~t--4-4-+-++~t--+-4
~
_
~~,...~ ... SUB.L
0.021--t--~,!F.i=,:,:~:,~,=~_~
......
~ot.;,,:..-t.~~
I--I----+~
L-ONLY
~+1~~+H+-~~~++~t--4-4~++~t--+-4
~
O~-++-++I+---+--1f-++++++I-""-+--+-+#~I--+--1
~-1~~+H+--4~~++~~-+-+~++~~-+--1
B-2~~+H+--;~r+++~t--+-+-+-++~t--+-4
I -3r+++~---r-r+++H#---~~++~--~~
~-4~~+H+-~~~++~t--+-4~++~~-+-4
u
0.005 L . - - - L . . _ I . - - J -___L---J-_ _ _ _
a 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
....L.----L_~___'
Vin-Signal Input Voltage-Vr.m.s.
202
30 50
100 200300500
1k
2 k 3 k 5 k 10 k 20 k30 k
f - Modulation Frequency - Hz
,uPC1161 C3
TOTAL HARMONIC DISTORTION
vs. SUPPLY VOLTAGE
SEPARATION vs.
SUPPLY VOLTAGE
70
f = 1 kHz
f -1 kHz
0.5
60
R-+L
CD
\.
"U
~
I
0.3
0.2
:e
"-L-+R
.~ 50
I
g
~
rtl
Co
Q)
1il
(/)
(5
I 40
0.1
u
'c
ci.
Q)
a!
o
I
(/)
§
rtl
30
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Vee-Supply Voltage-V
SEPARATION vs.
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70
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TOTAL GAIN vs.
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60
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Vin-Signal Input Voltage-Vr.m.s.
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Vee -Supply Voltage-V
CHANNEL BALANCE vs.
SUPPLY VOLTAGE
FREE-RUNNING FREQUENCY
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f = 1 kHz
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PILOT LAMP INPUT LEVEL. FOR
LAMP OFF VS. SUPPLY VOLTAGE
(PILOT ONLY)
PILOT LEVEL AND AMBIENT
TEMPERATURE VS. CAPTURE
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16
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PILOT LAMP INPUT LEVEL FOR
LAMP ON-OFF VS. AMBIENT
TEMPERATURE
+5~--~~--~~--r--r--~~~~
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CAPTURE RANGE VS. AMBIENT
TEMPERATURE (PILOT=30 mV)
~+3~~~~--+--+--~~--~~~~
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nl
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0
10 20 30 40 50 60 70
Ta-Ambient Temperature-OC
204
-20-10 0
10 20 30 40 50 60 70
Ta-Ambient Temperature-%
,uPC1161C3
FREE-RUNNING FREQUENCY DRIFT
AMBIENT TEMPERATURE
VS.
~
Put into temperature
test chamber only Ie
(exclude external
components)
19.30
.:t::.
b..:: 19.20
Cl
>.
19.10
r-..... ..........
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w
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I
- - - 0 Rch-OUT
6
Demodu-
A2
lator
7
>---0 Lch-OUT
4
vCCO-----~~--~r-----~--~
The change of the circuit gain in case an input resister RI has been varied is shown in the following drowing.
18
R= 10 kO
17
16
15
ro
-0
14
I
:{
13
<
12
tlO
.2
0
N
11
R=22 kO
R=47 kO
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r":~
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"-
10
9
~
8
33
39
43
47
51
56
62
"
68
Rl-kO
211
pPC1235C
EXAMPLE OF
PRINTED·CI~CUIT
BOARD
(Unit: mm)
100
oU)
(Bottom View)
OUTBOARD COMPONENTS MOUNTED ON A PRINTED·CIRCUIT BOARD
stereo·monaural switching
o
Rch.OUT
Lch·OUT
212
Rl=47 kQ
Rs =47 kQ
Ru=15 kQ
Cl=100J.lF
Cs =1000 pF
Cu=10J.lF
R2=10 kQ
R7 =3.3 kQ
R12=3.3 kQ
C2=4.7 J.lF
C7 =0.22J.1F
C12= 10 J.lF
VCO Adj. =5 kQVR
R3=22 kQ
Rs =47 kQ
R13=3.3 kQ
C3=500 pF
Cs =1.5 J.lF
C13=10 J.lF
BL·13= 19 kHz LPE(K.K KORIN)
R4=10 kQ
R9 =3.3 kQ
R14=1.0 kQ
C4=0.047 J.lF
C9 =3.3J.1F
C14=10 J.lF
Rs=22 kQ
RIO=1.0 kQ
RL =Lamp
Protecting
Resistor
Cs=l 000 pI
Clo=470 pF(Polystyrene
capacitor)
Sep. Adj. = 500 k Q VR
,uPC1235C
TYPICAL PERFORMANCE CHARACTERISTICS
TOTAL HARMONIC DISTORTION vs.
MAIN SIGNAL INPUT VOLTAGE
SEPARATION vs.
MODULATION FREQUENCY
70
f= 1 kHz
60
MONO
a::l
"0
I
-R
~
50
.J'
R...,..L to.. r-.
"
c:
40
g.
30
ero
1.0
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20
0.5
J
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I
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MAIN
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10
I
0.2
Vl
0
a
u
30 50
100 200300500
1k
2k 3k 5k
'c
10k 20k30k
I
0.1
0
E
f - Modulation Frequency - Hz
ro
I
J
0.05
~
TOTAL HARMONIC DISTORTION
vs. MODULATION FREQUENCY
(STEREO)
I
ci
I
0.5
co
;§
0.03
0.02
0.01
Rsuh.
III
I~
~,.
-~
1111 \
1\
Lonly
Ronly
100
200300500
a
~
1k
2k 3k 5k
10k
f= 1 kHz
f - Modulation Frequency - Hz
1.0
0.5
c:
o
0.3
0.2
.B
Vl
is
0
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0.3
0.1
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0.2
'2
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0
E
ro
0.03 I-R
0.02 I·...;,
R
[
0.01
ro
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
20k30k
I
~
I
L/V
~-:/ R
TOTAL HARMONIC DISTORTION vs.
SUPPLY VOLTAGE
30 50
~
I
......... l/
VV
Vin - Main Signal Input Voltage - Vr.m.s.
TOTAL HARMONIC DISTORTION
o
.. V
..V
1'.. ......
vs. MODULATION FREQUENCY
u
1.....1:':: r.
-... ~
0.005
0.05 i-i-Lsub
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I
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1
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0.2
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ro
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11"
R
0.03
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V.I
ro
MAIN It-f-
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c
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-
V
J
_'"'::t-
-
-
i.-
II'
100 200300500
1k
2k 3k 5k
f - Modulation Frequency - Hz
10k 20k30k
I
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0.1
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ro
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I
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ci
I
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0.01
1"00;
~
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MONO R
0.005
8
10
12
14
16
18
Vee - Supply Voltage - V
213
,uPC1235C
SEPARATION vs. SUPPLY
VOLTAGE
TOTAL HARMONIC DISTORTION vs.
MAIN SIGNAL INPUT VOLTAGE
70
f= 1 kHz
f= 1 kHz
60
"0
--,
~
R~L
CD
1.0
I
n•
0.5
c
I
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50
0
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c
0
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0.3
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0
0.2
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0
E
ro
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U)
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en
I
ci.
40
Q.l
30
0.1
I
ro
0.05
-0
I
R·ONLY
0.03
q
I
8
6
A
\
10
12
14
16
Vee - Supply Voltage - V
0.02
.....:
20
SUB·R
f-
~::-:--,
...
J.
~
"L·ONLY
SEPARATION vs. SIGNAL INPUT
VOLTAGE
0.01
70
f=l kHz
0.0050
0.1 0.2 0.3 0.4
0.5 0.6 0.7 0.8 0.9 1.0
CD
I
0
CHANNEL BALANCE vs. SUPPLY
VOLTAGE
Q.l
U)
I
ci.
+2
30
Q.l
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-1
~
-2
ro
c
ro
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U
40
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50
en
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f= 1 kHz
I
L
:;::::;
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ro
+3
CD
--- -- --
...-
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c
I
I
60
Vin - Signal Input Voltage - Vr.m.s.
R or L
~
.- -
20
---,--
o
0.1
0.2
0.3
0.4
0.5
0.60.7
0.8
0.9
1.0
Vin - Signal Input Voltage - Vr.m.s.
-3
I
a:i
U -5
TOTAL GAIN vs. SUPPLY
VOLTAGE
-6
6
8
10
12
14
16
f= 1 kHz
+3
Vee - Supply Voltage - V
+2
CHANNEL BALANCE vs.
MODULATION FREQUENCY
!g
+1
I
o
CD
"0
I
Q.l
u
c
ro
ro
CD
iii
c
c
ro
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I
ai
-1
+4
+3
+2
+1
0
-1
-2
-3
-4
;§
-2
I
~ -3
-4
I
-5
-6
100200300500
1k
2 k3k 5k 10k 20k30k
f - Modulation Frequency - Hz
214
/'
ro
U
30 50
R or L
6
8
10
12
Vee - Supply Voltage - V
14
16
,uPC1235C
TOTAL CURRENT DRAIN vs.
SUPPLY VOLTAGE (NO SIGNAL)
PILOT LAMP INPUT LEVEL FOR
LAMP OFF vs. SUPPLY VOLTAGE
(PILOT ONLY)
vi
23
c::(
E
;;
22
E
I
c:
21
0
20
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19
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---
18
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V
E
-- -----
I
c:
0
v
Co
E
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11
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10
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17
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13
12
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co
f-
15
E
16
9
co
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15
:§
14
I
c::
16
14
12
10
8
6
z
0
8
7
6
.,j
Vcc - Supply Voltage - V
6
vee PILOT LAMP INPUT LEVEL FOR
LAMP ON vs: SUPPLY VOLTAGE
(PILOT ONLY)
vi
E
;;
E
I
(5
I
PILOT LEVEL AND AMBIENT
TEMPERATURE vs. CAPTURE
RANGE
90
8
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oS
Supply Voltage - V
I
i
I
9
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4
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I
3
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0.
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8
10
12
80
70
60
50
40
f-
30
a::
20
a...J
E 2
co
-20·C
I
~5 ·C" \
25·C
~
!II
16
14
o +1 +2 +3 +4 +5
VCC - Supply Voltage - V
C.R. - Capture Range CAPTURE RANGE vs. AMBIENT
TEMPERATURE (PILOT=30 mVr.m.s.)
+4
vi
14
;;
E
13
I
12
E
I
%
PILOT LAMP INPUT LEVEL FOR
LAMP ON-OFF vs. AMBIENT
TEMPERATURE
+5
~
+3
+2
ON
(lJ
(5
llJJ
c:
co
+1
~
0
a:::
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U
I
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<.:i
C
11
E
co
10
o
C.
co
16
14
12
10
8
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-1
9
-2
"5
Co
-3
oS
Co
8
I
7
E
-4~~-+--4---+--4---+--1---r--+--~
-5~~~--~--~~--~--~--~~--~
-20 -10
0
10
20
30
40
50
Ta - Ambient Temperature - 'c
60
70
.::l
'0
0:
OFF
6
5
I
f-
a
...J
c:::
I
4 _ 20 -10
0
10
20
30
40
50
60
70
Ta - Ambient Temperature - 'c
215
,uPC1235C
FREE-RUNNING FREQUENCY DRIFT
AMBIENT TEMPERATURE
FREE-RUNNING FREQUENCY
DRIFT vs. SUPPLY VOLTAGE
VS.
Put into temperature
N
test chamber only Ie
(exclude external parts)
19.30
:I:
~
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-
19.20
.....
;§
19.10
>.
u
19.00
cQ)
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at
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r--.......
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~
~
18.90
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u
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r-....... I'-
~
cr
Q)
bD
18.80
·cc
18.70
·c
cb
~
u.
18.60
0:::
I
18.50
I..i..
18.40
I
~
c
~
19.0
Lt
bD
c
c
0::
18.9
~
cb
~
~
-20 -10
0
10
20
30
40
50
Ta - Ambient Temperature _ ·e
216
19.2
N
I
60
70
18.8
6
8
I
10
12
Vee - Supply Voltage - V
14
16
BIPOLAR ANALOG INTEGRATED CIRCUIT
p.PC1224H
HIGH SUPPLY VOLTAGE LOW NOISE DUAL PRE AMPLIFIER
DESCRIPTION
The IlPC1224H is a monolithic integrated circuit and a dual pre amplifier designed for the low-end class to the middle
class Hi-Fi audio sets and in an 8-pin single in-line plastic (SIP) package.
The circuit inside of IlPC1224H is composed of the two stage differential amplifiers acting as a voltage amplifier stage
and the SEPP (Single End Push Pull) circuit acting as a final stage.
FEATURES
•
•
•
•
•
IlPC1224H has a dual pre amp in an 8-pin SIP package, so that it has a merit of design and assembly of small sets_
Very low noise.
0.815IlVr.m.s. TYP. (RG= 0 il, Av = 36 dB at 1 kHz, RIAA, without Filter)
Low distortion.
0.0024 % TYP. (Vee = ± 22 V, Vo = 1 Vr.m.s., RL = 10 kil, f = 1 kHz)
Wide input dynamic range. 222 mVr.m.s. TYP.
(Vee = ± 22V, T.H.D. = 0.1 %, f = 1 kHz, Av = 36 dB)
IlPC1224H can drive a lower impedance load because its final stage is the SEPP circuit.
PACKAGE DIMENSIONS (Unit: mm)
BLOCK DIAGRAM &
CONNECTION DIAGRAM
2.8±O.2
19.5 MAX.
Cl
+Vcc
Outl
NFBI
INI
-vcc
IN2
NFB2
Out2
1.2±O.1
-1 Regulated Power Supply
6.7 MAX.
1.2
2.54±O.2
17.78
217
,uPC1224H
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage
Allowable Power Dissipation
Differential Mode Input Voltage
Common Mode Input Voltage
Operating Temperature
Topt
Storage Temperature
Tstg
± 25
330
±10
VCC
Po
Ta
= 65°C
VID
to ± Vcc
-20 to +65
-40 to +125
VICM
V
mW
V
V
°c
°c
RECOMMENDED OPERATING CONDITIONS (Ta = 25°C)
CHARACTER ISTIC
MIN.
TYP.
MAX.
Supply Voltage
VCC
±10
±22
±24
V
Input Bias Resistance
RIN
20
50
100
kn
Load Impedance
RL
1
10
100
kn
Closed Loop Voltage Gain
Av
15
36
ELECTRICAL CHARACTERISTICS (Vee
=±22 V,
SYMBOL
MIN.
CHARACTER ISTIC
Quiscent Circuit Current
218
UNIT
SYMBOL
ICC
Open Loop Voltage Gain
AVO
Total Harmonic Distortion
T.H.D.
Maximum Output Voltage
VOM
80
RL
=10 kn,
Au =36 dB, RIAA, Ta = 25°C)
TYP.
MAX.
UNIT
3
5S
mA
100
0.0024
12
dB
dB
0.03
%
1.6
IlVr•m.s.
14
Equivalent Input Noise Level
NL
0.8
Common Mode Reduction Ratio
C.M.R.
90
Supply Voltage Reduction Ratio
SVR
65
25
Channel Separation
Ch.sep.
90
Vr.m.s.
(+)
(-)
TEST CONDITIONS
=0.1 Vr.m.s.
= 1 Vr.m.s., f = 1 kHz
T.H.D. =0.1 %, f = 1 kHz
Rg = 0 n, without Filter
Vo
Vo
dB
RIN ~10 kn
dB
RIN ~ 10 kn. fripple
dB
Vo
= 100 Hz
= 10 Vr.m.s., f = 1 kHz
,uPC1224H
TEST CI RCUIT
SWl
1
2
........---() +22
~
V
1 SW2
....---------{')
10 k Q
2o-------~'~--~------~
SW4
510 kQ
330 J,lF
+
~-----------_o-22V
SW1
SW2
SW3
SW4
ICC
2
2
2
1
AvO
1
1
1
2
T.H.D.
1
1
2
1
VOM
1
1
2
1
NL
1
2
2
1
TYPICAL APPLICATION CIRCUIT
510 kQ
39 kQ
6 800 pF 1 930 pF
r------------,
I
3
'\---;~..AJ.},....--.....!..f:I---.......-__o
L-ch OUTPUT
L-ch INPUT D - - - - I l ¥ - - . - - - - - {
-22VO----4--~
R-ch INPUT o---n-:---..-~~
\..-...-.J.N\.--..!...FI---.......---o R-ch OUTPUT
10 kQ
510 kQ
39 kQ
219
,uPC1224H
TYPICAL CHARACTERISTIC
VOLTAGE GAIN vs. FREQUENCY
VCC=±22 V
Vo=O.l Vr.m.s.
Rl=lO kQ
120
CD
~
100
'0
......
"""
I
c
'jij
r--....
I
16
>
g
"- .....
-.e
:J
.........
:J
"-"
60
I
.;(
18
E
tlO
tlO
!!
..:
Q)
Q)
g
20
!!
80
(!)
MAXIMUM OUTPUT VOLTAGE
vi
0
~
r"-~
40
E
:J
E
'x
nI
::E
I
::E
VS.
FREQUENCY
VCC=±22 V
T.H.D.=O.l %
Rl=IO kQ
,
14
'"\
12
,
10
~
8
6
\,
4
2
0
20 10
2030 50
100 200300500 1 k 2 k3 k 5 k 10 k20 k30 k50 klOO k
>
10203050
100200300500
f - Frequency - Hz
lk
2k3k5k IOk20k30k50k
f - Frequency - Hz
TOTAL HARMONIC DISTORTION vs.
OUTPUT VOLTAGE
VCC=±22 V
Av=36 dB
(at 1 kHz RIM)
Rl=10 kQ
0.5
MAXIMUM OUTPUT VOLTAGE
SUPPLY VOLTAGE
VS.
20
0.3
0.2
~
~
I
c
0.1
0
'of
~
0.05
C
u
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> 12
'5 10
V
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0.2 0.5
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'=1 kHz
IH.D.=O.l %
Rl=10 kQ
.e
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V
\., J
0.002
18
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0.005
::x:
'=20 kHz
/
V
vi
V
0
/
6
V
/
/
4
./
2
V
>
/
5
8
0
±2
±4
±6
±S ±10 ±12 ±14 ±16 ±IS ±20 ±22 ±24
± Vee - Supply Voltage - V
10
20 30
Vout - Output Voltage - Vr.m.s.
MAXIMUM OUTPUT VOLTAGE
VOLTAGE GAIN VS.
SUPPL Y VOLTAGE
vs. LOAD INPEDANCE
18
16
100
>
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tlO
14
!!
./
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-
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-II
CD
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c
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60
(!)
/V'
10
80
Vo=O.l Vr.m.s.
'=50 Hz
'0
/
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E
:J
E
120
VCC=±22 V
T.H.D.=O.l %
f=l kHz
Q)
tlO
,/
!!
g
40
I
.;(
8
20
6
1k
2k 3k
5k
10 k
20 k 30 k 50 k
RL - Load Impedance - Ohms
220
100 k
o
±2
±4 ±6
±S ±10 ±12 ±14 ±16 ±IS ±20 ±22 ±24
±Vee - Supply Voltage - V
tlPC1224H
CIRCUIT CURRENT vs.
SUPPLY VOLTAGE
SUPPLY VOLTAGE REJECTION
vs. SUPPLY VOLTAGE
5
70
VIN=O
c:(
C
~
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d~.R(+)
60
4
~
E
I
3
(.)
III
CD
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50
~
f ripple·=lOO Hz
RIN:;?;10 kQ
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hl
.(j)
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40
CI)
DO
.e
1
~ 30
>.
a.
Co
:::l
o
IJ)
±2 ±4
±6 ±8 ±10 ±12 ±14 ±lG ±lS ±20 ±22 ±24
I
S~.R(
20
a:
± Vee - Supply Voltage - V
:>.
IJ)
10
CHANNEL SEPARATION
VS.
a
FREQUENCY
120
CD
7
"0
I
:2
SO
r- ~
l,...--
100
..V
VCC=±22 V
VOUT=10 Vr.m.s.
r-- t---r-
r-....
It
--"V
~
.....
)
II
±2 ±4
±G ±S ±10 ±12 ±14 ±lG ±lS ±20 ±22 ±24
±Vee -
Supply Voltage - V
...........
/
~
<0
Co
~
60
Q;
c
C
<0
<3
40
I
Co
~
..c.
(.)
20
0 10
20 30 50
100
200 300 500
1k
2k3k 5k
10 k
20 k 30 k 50 k 100 k
f - Frequency - Hz
221
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1188H
20 W AUDIO POWER AMPLIFIER
DESCRIPTION
The J.LPCl188H is a monolithic
int~grated
circuit and a power amplifier designed for Hi-Fi audio sets and in a 10pin
Single In-Line plastic package. J.LPC1188H can provide 20 W (TYP.) to 8 ohms at 1 % T.H.D. and ± 22 V Supply voltage.
FEATURES
•
20 W TYP. (Vee = ± 22 V, Au =40 dB, f = 20 Hz -- 20 kHz, R L = 80, T.H.D. = 1 %)
20 W TYP. (Vee =± 22 V, Au = 27.5 dB, f= 20 Hz", 20 kHz, R L = 80, T.H.D. = 0.5 %)
High output power_
0.02 % TYP. (Vee = ± 22 V, Au = 40 dB, f = 1 kHz, R L = 80, Pout = 5.0 W)
0.005 % TYP. (Vee = ± 22 V, Au= 27.5 dB, f = 1 kHz, R L = 80, Pout = 5.0 W)
• Wide frequency band width.
f= 250 kHz (-3 dB)
• J.LPC1188H has a muting function which eliminates pop on noise and the thermal and the over current protection
circuit.
•
Low distortion.
•
Available for N FB tone control amp.
BLOCK DIAGRAM
Muting
~------------------------------~ 4 ~------------------------------------~
Thermal Protection
Muting Circuit
'"
~
ii:
GND
INPUT
Circuit for level
shift and
phase inverse
1
Pre Driver
:J
Constant Current
Source
Current Limitter
.e
~
o
Q)
"C
in
'------------(8~-------------------I
NFB
222
Phase Compasation
-VCC
:J
Co
:J
o
jlPC1188H
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage (Quiescent)
VCC
± 30
V
Circuit Current
Package Dissipation
ICC(peak)
5
30*
W
Operating Temperature
Storage Temperature
Topt
Tstg
Thermal Resistance Junction to Case
Rth(joc)
PD
A
°c
°c
-20 to +70
-55 to +150
3
°C/W
°
* Tta b=60 C
RECOMMENDED OPERATING CONDITIONS (Ta = 25°C)
CHARACTERISTIC
UNIT
MIN.
TYP.
MAX.
±17
±22
±23
V
100
kn.
Operating Supply Voltage
Input Impedance
47
56
Closed Loop Voltage Gain
26
40
dB
Load Impedance
4
8
n
ELECTRIC CHARACTERISTICS (Vee = ±22 V, Av
CHARACTERISTIC
SYMBOL
MIN.
= 40 dB, RL = 8 n,
RG
= 600 n,
TYP.
MAX.
UNIT
Ta
= 2SoC)
TEST CONDITIONS
Output Offset Voltage
VIO
-100
0
+100
mV
No Signal
Circuit Current
ICC
30
60
120
mA
No Signal
Output Power
Po
16
18
W
T.H.D.
Open Loop Voltage Gain
Avo
65
75
dB
Po
Total Harmonic Distortion
T.H.D.
0.1
0.3
%
Output Noise Voltage
NV
0.4
1.0
mV
Power Band Width
P.B.W.
Supply Voltage Rejection Ratio
S.V.R.
50
250
kHz
56
dB
= 0.5 %, f = 20 Hz - 20 kHz
= 0.3 W, f = 1 kHz
Po = 10 W, f = 20 Hz - 20 kHz
RG = 2.2 kn, No Filter
Po = 0.3 W, -3 dB
RG = 2.2 kn, fripple = 100 Hz
PACKAGE DIMENSION
Unit: mm
Typical value unless otherwise noted
32.0 MAX.
24.0 ±0.2
5.0 MAX.
r-I
CONNECTION DIAGRAM
1
0.3
OUTPUT
2
NC
3
+VCC
4
MUTING
5
PHASE COMP
6
PHASE COMP
7
INPUT
8
NFB
9
GND
10
-VCC
223
,uPC1188H
TEST CIRCUIT
+VCC=22V
SW2.
SG
IH.D.
SW3.
-VCC=-22V
NOTE: Turn on plus and minus power supply at the same time or minus power supply at first.
ITEM
SYMBOL
SW1
SW2
SW3
Circuit Current
ICC
2
3
1
Output Offset Voltage
VIO
1
3
1
Output Power
Po
1
1
1
Open Loop Voltage Gain
Avo
1
1
2
Total Harmonic Distortion
T.H.D.
1
1
1
Output Noise Voltage
NV
1
2
1
Supply Voltage Rejection Ratio
SVR
1
2
1
APPLICATION CIRCUIT
+22V
INPUTo---H-_~
Speaker
RL=8 ohms
-22V
224
DY.M
jlPC1188H
TYPICAL CHARACTERISTICS (Ta = 25°C)
POWER DISSIPATION
w.
AMBIENT TEMPERATURE
OUTPUT POWER vs. FREQUENCY
40~----~----~----~----~------------~
26
24
22
AI Panel t=2 mm
With Silican Glyce
~
-
20
18
:t 16
0
a.. 14
:; 12
:::J
10
0
I
8
0
a..
6
4
....I
VCC=±22 V
IH.D.=0.5 %
Av=40 dB
JJ8J- -
-~
lJ
I
CI)
~
10~----~----+--
I
o
a..
o
25
50
,
1\
.e
CI)
:t
l--
i-'~-
100
75
150
,,
~\
\\
2
Ta - Ambient Temperature _·C
0
10
20 30 50 100 200 300 500 1 k 2 k 3 k 5 k 10 k 20 k 30 k 50 k 100 k
f - Frequency - Hz
VOLTAGE GAIN
I II
80
~
'(;i
CI)
"
V
17
VCC=±22 V
Pout =0.3 W
1"
"
60
50
""
r E
Ie
C1l
C1l
oot:
ro ::>
~u
o
U
::>
::>
::>
ICC
~
00'
I
I
50
/
0
ri . /V
10
>~
j......-
i-"'"
,""'"
---
'Q)
0::
-
C1l
bO
.e
"0
40
>
.-
>.
0.
a.
30
::>
en
I
c:
l/:V
1/V
>.
20
en
10
r/
/
Q
V V
~V
50
C1l
4
1/
~
I
c..
o
.e.~
ou
(1= 1 kHz
)
o IH.D.=O.5 %
o
cC1l
::>
f - - f--p
Co
::>
.g
g~
.....
20
::>
>.~
~
~
o
c..
C
:;:;
u
V
I
100
60
0::
/
::
E I
:;:;
co
VIC f - - ~
~
/
0
±10
±20
±30
Vee - Supply Voltage - V
o
0
±10
±20
±30
Vee - Supply Voltage - V
OUTPUT NOISE VOLTAGE vs. INPUT IMPEDANCE
VCC=±22 v
Av =40 dB
Without Filter
3.0
vi
J
E
I
.;;
E
I
C1l
00
.e
-0
II
2.0
/
>
C1l
II>
'I
'0
z
/
"5
.s-
0
I
1.0
V
I
V
>
z
~
1-0--....
I ••
0
"
20 30 50 100 200 300 500 1 k 2 k 3 k 5 k 10 k 20 k30 k 50 k 100 k
RG -Input Impedance - Q
227
BIPOLAR ANALOG INTEGRATED CIRCUIT
,u PC1238
10 W AF POWER AMPLIFIER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
The pPC1238 is an audio power amplifier designed for median Hi-Fi stereo set and TV set sound power amplifier.
This device can provide 8.4 watts to 8 ohm at 1 % T.H.D. and ±13 V supply voltage.
The pPC1238 incorporates the thermal protection circuit to protect the damage of IC chip against load damping etc.
Since the package is a 5 Pin TO-220 package, it greatly simplifies construction of a power amplifier both in design and as-·
sembly.
FEATURES
• Low equivalent input noise voltage .
• High output power
• Available for NFB tone control mode.
8.4 W TYP. (at 8 Q, Vee =±13 V)
12.5 W TYP. (at 4 Q, Vee =±13 V)
• Negligible power ON/OFF noise.
• High density components assembly due to 5 Pin TO-220 package .
• Low T.H.D.
0.012 % TYP. (Pout =2 W, RL =8 Q)
0.02 % TYP. (Pout = 2 W, RL == 4 Q)
CONNECTION DIAGRAM
o
Pin No.
1
Electrical Connection
Non inverting input
2
Inverting input
3
4
-Vee
Output
5
+Vee
PACKAGE DIMENSIONS (in millimeters)
~PC1238H
~PC1238V
¢ 3.6±0.1
4.8 MAX.
10.4 MAX.
I
a
co
~
a
N
...i
N
~I
r-..
"'1
!
1.0 M_A_X.-+-+-_
6.8
3.4
1
228
8.4
JlPC1238
ABSOLUTE MAXIMUM RATINGS (T a =25 °C)
Supply Voltage (Quiescent)
Vcc
±18
V
Supply Voltage (Operational)
VCC
±15
V
Circuit Current
ICC(peak)
4
A
Package Dissipation
PD
*25
W
Junction Temperature
Tj
150
°c
Operating Temperature
T opt
-20 to +65
°c
Storage T em peratu re
T stg
-40 to + 150
Thermal Resistance Junction to Case
°c
°C/W
3.4
Rth (j-c)
*Ttab = 65°C
RECOMMENDED OPERATING CONDITIONS (Ta =25 °C)
CHARACTER ISTIC
Operating Supply
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
±6
±13
±15
V
Terminated Input Resistance
RIN
47
56
100
kn
Closed Loop Voltage Gain
Av
20
35
dB
Load Impedance
RL
4
8
n
ELECTRICAL CHARACTERISTICS
(Refer to the test circuit: Ta=25 °c, V cc =±13 V, Av=35 dB, RG =600
CHARACTERISTIC
on,
RL =8
on)
SYMBOL
MIN.
TYP.
MAX.
UNIT
Output Offset Voltage
VOFF
-100
0
+100
mV
No Signal
Circuit Current
ICC
30
60
130
mA
No Signal
Output Power
Po
7
8.4
Total Harmonic Distortion
T.H.D.
0.2
Open Loop Voltage Gain
Avo
83
Equivalent Input Noise Voltage
VNI
3
Power Band Width
P.B.W.
Supply Voltage Rejection Ratio
S.V.R.
45
1
10
TEST CONDITIONS
W
T.H.D.=1 %, f=1 kHz
%
f = 40 Hz - 15 kHz
PO=0.1 -7 W
dB
PO=0.1 W, f=500 Hz
J.,LV r .m .s.
RG=2.2 kn
f=40 Hz - 15 kHz(-3 dB)
75
kHz
Po =0.1 W, -3 dB
51
dB
f = 100 Hz, RG =2.2 kn
229
,uPC1238
TEST CIRCUIT & TYPICAL APPLICATIONS
SW1
~-------o
S.G.
V.T.V.M.
+ 13 V
1 SW2
2
2.2
kQ
~
J--1t--+----1~__----<...._--__..-__140 Hz 15
kHz
-13dB/OCT
3
Q
2
I
SW3
56 kQ
V.T.V.M.
0.22
_
+ 100
IIF
IIF
IIF
1
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _--Q
Switch Position
TEST
ITEM
Output Offset Voltage
Circu it Current
230
SW1.
SW2.
SW3.
VOFF
1
3
1
ICC
2
3
1
SYMBOL
Output Power
Po
1
1
1
Total Harmonic Distortion
T.H.D.
1
1
1
Equivalent Input Noise Voltage
VNI
1
2
2
Supply Voltage Rejection Ratio
S.V.R.
1
2
1
1
-13 V
jlPC1238
TYPICAL CHARACTERISTICS (T a =25°C)
PACKAGE DISSIPATION vs.
AMBIENT TEMPERATURE
POWER DISSIPATION vs. OUTPUT POWER
10
AI Panel
t=2 mm
Use silicon grease
& insulator
30
::
I
c
\. ~......
25
a.
'Vi
~.
is
Q)
co
U
0-
I
10
0
0-
5
en
V
is
...
£/
~c0'(-'?
'l?
C//it;
VCC=±13V
f= 1 kHz
/
?:
o
-
SQ
"
0-
I
•
2S'~ ~
f r~~l
5
Q)
\~
.loa
co
a.
~
-
.::t:.
~
'Vi
~
15
,/
o
\\
-
I
I
c
~
20
en
IlO
I
::
\"'"~
0
~
.l"R~~4 Q
"0
0-
~
C/l1;; ~
.I
Free I_r~
Air (64 C W)
0
50
o
150
100
15
10
5
20
PO-Output Power-W
T a-Ambient Temperature-OC
OUTPUT POWER vs. FREQUENCY
VCC=±13 V
T.H.D.= 1 %
Av=35 dB
16
::
...I
Q)
;:
14
RL =4 Q
12
0
sJ
0-
.....::J
10
:J
S
0-
6
a.
0
I
0
'"
-'"\ "
.....
4
2
~O
20 30
50
100
200300 500
1k
2k 3 k 5 k
10 k
20 k30 k 50 k
f - Frequency - Hz
VOLTAGE GAIN vs. FREQUENCY
100
VCC= ± 13 V
PO=O.l. W
90
./
SO
!Xl
70 I-
I
c
60
"0
'ro
(!)
Q)
IlO
.s
"0
50
>
40
.;
30
I
10'''''
V
V
.... ~ ....
'/
/
~LOOP
~ ...... ......
~~
'"
--
~
- Closed Loop
",.,.-
'"
I'-... ......
-r-.
20
10 I-
qo
20 30
50
100
200300 500
1k
2 k 3 k 5k
10 k 20 k 30 k 50 k
f - Frequency - Hz
231
JlPC1238
TOTAL HARMONIC DISTORTION vs.
OUTPUT POWE R
TOTAL HARMONIC DISTORTION vs.
OUTPUT POWER
~
I
c:
Vee ±13 V
Av 35 dB
RL=4Q
Vee ±13 V
Av 35 dB
RL=a Q
~
3
I
3
0
2
c:
2
0
1::
1::
.s
.s
I
III
III
0
C
u
u
'2
0.5
'2
E
m
0.3
E
m
0.3
(ij
0.2
0
J:
J:
0.2
(ij
f=15~~ "'"
-0
I-
0.1
I
c:i
::i 0.05
...:
0.03
~
0.02
0.01
0.1
l-
I
'#
'r-..,
-
i"" I"-
0.2 0.3
0.5
2
3
"'
0.03
-
~
-
1'1"-
0.02
I)
1 kHz
..""
~
5
.....
~1.
~~,
0.1
c:i
::i 0.05 ..........
...:
I'
......
"""""'"
:...
-0
l-'~
b,o\,\1.
15 kHz
f
0.5
0
0.01
0.1
10
2
0.2 0.3 0.5
PO-Output Power-W
l1k~
3
,
I
5
10
20
PO-Output Power- W
TOTAL HARMONIC DISTORTION vs. FREQUENCY
10
Vee ±13 V
Av 35 dB
5
~
3
I
2
c:
0
1'1
t
.s
III
0
u
0.5
'2
0
E
0.3
J:
0.2
m
:e
0
........
.......
0.1
l-
--.
...... ~
I
::00..
c:i
::i 0.05
...:
PO=4
.....
-
!
-I-
I
I III
0.1 W (a Q)
0.03
f
:..-t-r
.....
1
I
I
4 W (RL=a
0.1 W (4 Q)
........
v
W(RL =4 Q)
QV V ",I
-
.....
, ,"" n
0.02
0.01
10
2030 50
11
100200300500 1 k 2 k 3 k 5 k 10 k 20 k
50 k 100 k
f - Frequency - Hz
OPEN LOOP VOLTAGE GAIN,
CIRCUIT CURRENT vs. SUPPLY VOLTAGE
OUTPUT POWER vs. SUPPLY VOLTAGE
100
f=l kHz
T.H.D.=l %
Av=35 dB
Avo (f=500 Hz) /
20
3:
L
Q)
~
0
(
15
RL=4Q
Q.
....::s
.e
::s
0
/
0
Q.
IjaQ
/ /
5
L
Y'
o
±5
v:
±10
±15
vee-Supply Voltage-V
232
, ~ee(VIN=O)
1
/J
10
I
/
±20
o
±5
±10
±15
vee-Supply Voltage-V
±20
JlPC1238
OUTPUT OFFSET VOLTAGE, SUPPLY
VOLTAGE REJECTION RATIO VS.
SUPPLY VOLTAGE
50
100
m
"0
I
>
0
E
~
I
c::
(\J
CI)
!:!
0
>
(5
.0)
~
CD
0:
.l!!
(5
...
VOFF( VIN =0)
c:
bO
0
CI)
bO
50
S.V.R(fHUM= 100 Hz)
!:!
.e
(5
0
C.
c.
::I
>
::I
>.
I
u..
u..
::I
en
I
0
>
0:
>
en
-50
0
±5
±10
±15
±20
vee-Supply Voltage-V
233
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1225H
30-50 W POWER AMPLIFIER DRIVER
DESCRIPTION
~PC1225H
is designed for use with a Hi-Fi power amplifier driver. It is composed of a differential amplifier, a pre driver, a
driver and protection circuit.
It is in a 12 pin small power SIP. (Single In Line)
FEATURES
•
Excellent Low Distortion
= ±36 V, f = 1 kHz, Av = 30 dB, Po = 30 W, RL = 8 Ohms)
(Vee = ±36 V, f = 20 kHz, Av = 30 dB, Po = 30 W, RL = 8 Ohms)
0.002 % TYP. (Vee
0.006 % TYP.
•
Wide Frequency Band
900 kHz TYP. (-3 dB)
•
Wide Power Band Width
90 kHz TYP. (Po
•
= 25 W, T.H.D. = 0.1
%)
Excellent Low POP ON/OFF Noise
BLOCK DIAGRAM
Muting
+VccP(Pre-amp Stage)
+VccD(Driver Stage)
2>-------------~1)__--_
NonInverted
Input
OUTPUT 1
(POWER DRIVE)
Inverted
Input
OUTPUT 2
(POWER DRIVE)
+VccP(Pre-amp Stage) Phase CompasatiM
Bias
+VccD(Driver Stage)
NOTE: The protection circuit is for this Ie and cannot protect external Power Transistors. Thus, design a Po Tr protection circuit besides.
234
,uPC1225H
ABSOLUTE MAXMUM RATINGS (Ta = 25°C)
Supply Voltage (Ouiscent)
VCC1
±50
V
Supply Voltage (Operational)
VCC2
±45
V
Ouiscent Circuit Current
ICC
200
rnA
Allowable Package Dissipation
PD
4.1 *
W
Operational Temperature
T opt
-20 to +75
°c
Storage Temperature
T stg
-40 to +150
°c
*Ta=75°C
Using an aluminum heat sink 100 x 100 x 1 mm
RECOMMENDED OPERATING CONDITION
Supply Voltage (Operational)
VCC = ±18 to ±36 V at Max Power Output
Input Bias Resistance
RIN
= 1 to 50 to
Power Transistor hFE
h FE
Closed Loop Voltage Gain
AV
= 50 at Max Power Output
= 26 to 30 dB
ELECTRICAL CHARACTERISTICS (VCC
CHARACTERISTIC
SYMBOL
100 kohms
= ±36 V, Av = 30 dB, Use Standard Test Circuit, Ta = 25°C)
MIN.
TYP.
MAX.
UNIT
CONDITION
Output Offset Voltage
VOFF
±5
±100
mV
SEE TEST CIRCUIT 1
Quiscent Circuit Current
ICC
20
40
rnA
Maximum Output Voltage
VOM
20
23
V
Open Loop Voltage Gain
Avo
80
95
dB
VIN =0
T.H.D. = 0.05 %
f = 20 to 20 kHz
Vo=1.5V,f=1 kHz
Output Noise Voltage
VNO
0.07
mV
RG = 10 kohms
Power Band Width
P.B.W.
900
kHz
Vo = 1.5 V, -3 dB
Supply Voltage Rejection Ratio
S.V.R.
70
dB
RG
55
0.14
= 2 kohms, f = 100 Hz
235
,uPC1225H
PACKAGE DIMENSIONS
in millimeters (inches)
40(0157)
30 MAX.(118 MAX)
28(1.10)
t/J 3.6(0.142)-2
15(0.59)
R 3.5(0.138)-2
!
\
~
'1?
I
0
~
I
17\
-x
-
T,
Marking
1
-
«
I
m roo
_xe.
«
It)
0
-
It)
c;;
3
4
5
6
00
7
8
)
IJLJL;JL )
9
10
11
12
LJ 1;.1 l;JL J L
~
1
I
Il)
00
+1+1
0
;z;
0
1.2(0.047)
0.5(0.020)
2.54(0.1)
\,I
s
N
~
0
N
'"
....
I
LII
I
:::E
*~
I
2
I-
:::E
It)
0
\0
\Oil)
N
e.
'"
-
1.4(0.055)
1-0.45(0.018)
Typical dimensions unless specified otherwise.
PIN CONNECTION DIAGRAM
Pin No.
236
Pin connection
1
+V CCD (for Driver)
2
+VCCP (for Preamp)
3
MUTING
4
INPUT
5
NFB
6
PHASE COMP
1
BIAS
8
BIAS
9
-v CCP (for Preamp)
10
-V CCD (for Driver)
11
LOWER OUTPUT
12
UPPER OUTPUT
________~~PC1225H
TEST CIRCUIT 1 (VOFF)
+36 V
D.V.M
Ql }
Q2 2SCl844F
56 kQ
TEST CIRCUIT 2 (ICC)
Ql} 2SCl844F
Q2
20 kQ
237
J,lPC1225H
TEST CIRCUIT 3 (VOM)
+36 V
-36 V
10 JlF
6~} 25C1844F
V,T.V,M
TEST CI RCU IT 4 (AvO)
+36 V
-36 V
15553
390 Q
'390 Q
390 Q
15553
6J
o
100 kQ
V.T.V.M.
238
25C1844F
,uPC1225H
TEST CIRCUIT 5 (VNO)
Vcc
VEE
6~
}
2SC1844F
20 kQ
30 dB Amp
V.T.V.M.
LPF
(30 kHz -12 dB Oct)
TEST CIRCUIT 6 (S.V.R.)
+36 V
s.G61
f~lOOHU
-36 V
11
ISS53
2 kQ
390 Q
1SS53
8~
}
2SC1844F
3.3 kQ
239
j.lPC1225H
TYPICAL APPLICATION CIRCUIT
Vcc
Vcc
0.1 JlFr
2501110
....-........--05P OUT
258849
VCC=36 V
VEE=-36 V
56 kQ
Po- Ta
Characteristic
10.---.---~---.---~------~
==
~
~
.~
Heat sink: AI
Use silicon Glice
Unit:mm
Rthj_c=10 'C/W
8 . - - - - + Rthj_a=18 'C/W 100x100x1
Rthj_a=53.5 'C/W Free Air
(@-<]) Pin:15 pF,
60
I
r--",
~t---..
I
«>
:> 40
"
t......
'I-
®-@ Pin:0.033 JJ F)
0
«
.......
r-....r--....,.
Avo
0
VEE=-36 V
RL=390 Q
No Phase Compo
~K ®-
I
>~
:OJ
c
10
>
0
"0
E
I
C1l
tID
I
2
C1l
100 '~100 ~'~OO g40 ~ 20
21.
u
C1l
0
C1l
tID
:J
0
>
'w
I
2
>
a::
c:
~
o
>
80
c.
2'
~ 80
2
0
0
...J
.s-
~
'0
0
«>
>
0100
(f)
I
40 I 40 0
z
a::
>
uj
20
20
0
0
u
0
1l
~
::;
0
:J
.s-
'5
'x
ro
g-
>=
E
E
::J
:J
c: 60 >. 60 c.
:J
c.
~
0
I
C
0
z
0
::J
5
f - f-~
f--
0 f - - I--f-f-
-
f-
AVO(f=l kHz, Vo=1.5 V)
~
S.V.R.( )
::J
0
0
VOM(f
20 kHz)
V:-
I
l--' ~
VO~F
~
0 -5
I 20 610 I
I
I
I.L.
~
I.L.
f - f - VNOU
0
..".
0
S?
>
> -10
~
~
-
-
ICC('J\l'CO)
"..
,.VV
±20
±30
±40
±50
Vee - Supply Voltage - V
OUTPUT NOISE VOLTAGE
vs. SOURCE RESISTANCE
1000
30 dB FLAT AMP
30 kHz/-12 dB oct
500
>~
I
C1l
tID
2
L.P.F
300
~
200
V l.--""
0
>
~
'0
100
:J
c.
:J
50
.,V
z
0
I
0
z
30
..--
L.--
'-"-" ~
+--
--
I.-- I-""""
~
"'1T
20
>
10
0
II
300
500
1 k
2 k 3 k 5 k
10 k
RG - Source Resistance -
20 k 30 k 50 k 100 k 200 k 300 k
Q
241
pPC1225H
MAXIMUM OUTPUT VOLTAGE vs.
OUTPUT CURRENT
30
VCC=±36 V
-
.,;
E
~
I
~ 20
!!
r- r-
-
t-This indicates Protectio n Action
~
o
100
200
lout - Output Current - mAr.m.s.
POWER DISSIPATION vs. OUTPUT CURRENT
4
==I
c:
.Q
roc.
3
,V~
.~
/"'"
.-
0
~
Q)
2
~
0
0..
I
0
0..
/~ V
~~V ~
V
~~
.........
,-~-
-
----
~
- --
tv
-
VCC= ±36 V Correspond to 5ow
r_
~ ri7
I
I
--r~-A
I I I
Vec= ±32 V'Correspond
I
I
I
I
I
I
I .~-~
I
I
VCC= ±28 V Correspond
~
v
.t
to 40 W
I
I
I J.
to 3ow
I
!
0
100
200
lout - Output Current - mAr.m.s.
THERMAL RESISTER vs. AREA OF HEAT SINK
50
..
~
Free Air
==
$J
----
'"
:---.....
.............
~
I 10
~~
~
'in
Q)
c:::
ro
Rthj_c=IO 'C/W
5
'"
O~l~fuCk
E
Q)
.c:
l-
I
::I:
o
.c:
OUT
I
Attach with
Silicon Glice
cE'
3
10
A - Area of Heat Sink - cm 2
242
100
fLPC1225H/IlPC1237H/MP-80 EVALUATION CIRCUIT
VEE
Vee
Vec
25C945
0.033 J.lF
,
I
cr
~Rch
258849
(25A1l41)
250414
(250882, 2581449)
36 V
+
10 000 J.lF~
+
10000 J.lF ~
5P OUT
15553
10/]1 W
Vee= __---+----......,
rO.033 pF
>----_. . . .
VEE = .....
v.
,~
-36 V
a
u.+
.:.!
8-
~
::t:z
VEE
25A733
36 kQ
56 kQ
VEE
Vee
Vec
15 kQ
Vee
47 kQ I AC off Oetection
15553
Vee
MR-31-24T
10 kQ
0.033 J.lF
o-T--+--O Lch 5P OUT
56 kQ
258819
(25A1l41)
250414
(250882, 2581449)
220 J.lF
33 J.lF
Relay Orive
VEE
390/]1 W
56 kQ
Automatic reset/Latch
(GNO)! (0.022 J.lF)
Muting
1:::
"'tJ
56 kQ
o
~
N
N
Note:
N
~
W
Attach 2SD414 on Po Tr Heat Sink.
Attach AI Heat Sink, which is larger than 60 mm X 60 mm X 1 mm, with J,LPC1225 H.
c.n
::J:
I\)
~
~
1:::
"
n
Note:
..I
#1
C
#2
These terminals are for JP- lines to
a temperature Compensation transistor (2SD414 or others).
#3
Use 0.02 J,lF capacitance in case of
using J,lPC1237H at latching function, while connect each other at
automatic resetting.
This capacitance is for preventing
POP ON/OFF noise.
Thus, neglect it in caseofusinga relay.
These terminals are for JP-lines in
case of using the same power supply
(J,lPC1237H and Power Amplifier)
These terminals are for JP- lines in
case of using the same power supply
(J,lPC1225H and Power Tr)
This terminal is for AC-OFF Detection. Thus, use 8.2 k ohms instead of
22 k ohms, neglect 1SS53 and connect these 1 SS53's termi nals and
neglect 4.7 J,lF in case of using DC
#4
B
#5
ROUT
(~
MR31
(Relay)
#fj
#7
LOUT
#8
MR31
@ (Relay)
These terminals are for 3-terminals
regulators (J,lPC7818H, J,lPC7918H)
as a J,lPC1224H power supply.
power supply.
These capacitances are for preventing
a parastic oscillation. Use a 0.1 J,lF.
#9
These trimmers are for adjusting an
idling current. Recommend Neo-Pot
PS61 Series.
#10
These capacitance are for the 3-terminals regulator input.
Design of 1 J,lH (example)
#11
«l1_~_=~)11]~ mm
0.8 mm-J-l:
I·22 Turn·1
#12
->
This indicates a copper board pattern
N
N
U1
J:
J,lPC1225H
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER
RL=8 Q
VCC=36 V
VEE=-36 V
2SA1141
2SC2681
Id=60 mA
~
I
c:
-
r-I- -
r-rr-~
0
:.e
~
i5
0.1
u
'2
0
E
IV
:x:
ro
"0
I-
0.01
I
0
:i
r-=f':: l-I-r-.....
--
20 kHz
r- ~ -~
.......
I}
~f--o'"
..... r---- ~
r-:
1 kHz
~f""
~
20 kHz
0.001
0.1
10
Po - Output Power - W
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER
2SA1141
2SC2681
Id=60 mA
~
RL=4 Q
I
VCC=36 V
c:
0
~
i5
VEE=-36 V
O. 1
u
'c
0
20 kHz
E
-
I"
ro
:x:
~ =:::::::::
ro
"0 0.0 1
~
f=:: ~~
l-
~
J
20 Hz
I
0
:i
1 kHz
r-:
0.001
0.1
10
100
Po - Output Power - W
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
2SA1141
2SC2681
Id=60 mA
RL=8 Q
~
VCC=36 V
I
c:
o
'i:
VEE=-36 V
0.1
J
~
II /
IJ
I /
i5
u
'c
o
/.'(/
E
IV
:x:
~
o
l-
I
o
:r:
r-:
0.0 1
,r--_
", Po=1 W
~'pO'=lO
-~
0.001
10
\j
100
1k
--,
/.
{
. /W
..0
W
-~ ~
Po=50 W
II I
10 k
lOOk
f - Frequency - Hz
245
jlPC1225H
TOTAL HARMONIC DISTORTION
vs. FREQUENCY
2SA1141
2SA2681
Id=60 mA
RL=4 Q
~
I
I
c:
0
:e
0.1
VCC=36 V
VEE=-36 V
I
~
/"
Ci
~'I
u
"c:
0
E
ro
::I:
ro
"0 0.01
b...
I
~~
/
I",
c:i
-
Po=10 W
Po=l W
'
......... .......
.......
l-
'"
::x:
~
~
~
Po =70 W
t-:
0.001
10
100
1k
10 k
100 k
f - Frequency - Hz
POWER STAGE IDLING CURRENT
vs. SUPPLY VOLTAGE
80
+2SA1l41
2SC2681
RE=0.25 Q
VIN=O
70
~
60
>
E::l
E::l
o 5
I
I 10
'5
0
5
0
V
~
'-..
--
o
-5
-5
-10
246
10
'5
o
-10
2
Time-s
3
4
o
2
Time-s
3
4
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1237H
PROTECTOR IC FOR STEREO POWER AMPLIFIER
DESCRIPTION
J,LPC1237H is a monolithic integrated circuit designed for protecting stereo power amplifiers and loudspeakers, and is
in an 8 pin single in-line package.
FEATURES
• Work stably within a wide power supply voltage range. (Vee = 25 to 60 V)
• Contain a relay driver. (Max. 16 = 80 mAl
• Work as either latching function or automatic resetting function by using pin 3. (In both overload detection and output
offset detection, either function can be selected.)
o Need only single power supply.
• Both positive and negative output offset can be detected through the same pin. (Output offset detection through pin 2)
• AC voltage can be detected. (For AC-power-OFF mute through pin 4)
• The time delay from amplifier power ON to relay ON can be freely set by selecting external components. (For ACpower-ON mute through pin 7)
• The moment that amplifier-power is turned off, it can make relay broken OF F and then loudspeaker disconnected
from amplifier to prevent a shock off noise.
BLOCK DIAGRAM
Vee
,--------------------------(7}--------fSI------------.
t------i
Vee ON
Overload detector
6
mute
C-
o
:;::
I
.9-
u:
Ae -
Output Offset detector
OFF detector
Switch for latch/automatic - reset
......- - - - - { 5
)-------------t
GND
}-------------4.4J------------....I
247
J,lPC1237H
PACKAGE DIMENSIONS
in millimeters (inches)
19.5 MAX.
(0.767 MAX.)
2.8±0.2
(0.11)
Cl
(CO.04)
MARKING
0.25
(O.OI)-H~-
1.0 ± 0.1
(0.04)
17.78
(0.7)
_-+--_
Typical dimension unless specified otherwise.
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Power Supply Voltage
VCC
Allowable Power Dissipation
Po
Operational Temperature
Topt
-20 to +75
Storage Temperature
Tstg
-40 to +125
°c
°c
Pin 6 Maximum Current
16 max
80
rnA
Pin 4 Maximum Voltage
V4 max
10
V
Pin 8 Maximum Voltage
V8max
8
V
Pin 1 Maximum Current
11 max
3
rnA
Pin 2 Maximum Current
12 max
±3
rnA
Pin 7 Maximum Voltage
V7 max
8
V
60
V
320*
mW
*Ta = 75°C
RECOMMENDED OPERATING CONDITIONS
Supply Voltage
VCC= 25 to 45 to 60 V
ELECTRICAL CHARACTERISTICS (Vee = 45 V, Ta = 25°C, State using latching function)
UNIT
CHARACTER ISTIC
SYMBOL
MIN
TYP.
MAX.
Pin 1 Threshold Voltage
0.67
0.76
0.58
V
Vth 1
V
Vth+2
0.70
Pin 2 Positive Threshold Voltage
0.54
0.62
Pin 2 Negative Threshold Voltage
Vth-2
V
-0.17
-0.23
-0.12
Pin 4 Threshold Voltage
V
Vth 4
0.74
0.90
0.60
Pin 8 Reference Voltage
V
V8
3.8
3.0
3.4
248
CONDITION
level to invert at pin 6
level to invert at pin 6
level to invert at pin 6
level to invert at pin 6
RL = 1.5 kn
JLPC1237H
TEST CIRCUIT (State using latchung function)
15 kQ
~____~~__~~------~----o45V
1.5 kQ
RL
Switch positions
Item
SW 1
SW2
SW3
Vth 1
1
3
2
Vth+2
2
1
2
Vth-2
2
2
2
Vth 4
2
3
1
V8
2
3
2
TYPICAL APPLICATION CIRCUIT
,--,
Relay
r+vccl
I
I
I
I
I
I
I
: G--tl------O
0 I
I
~---------------------------------------------71~
I
I
I
I
I
Lch
~_____1~5Mk~Q____________~__~__~+VCC
Rch
45 V
156
56 kQ
+
I
I
Speaker L
0 - - + - -__
L
Terminal for overload detection
I
t---+----.--'
IkQ
I
)
Q
~--------------------------------------------+I~~O
I
1
24 V. 37 rnA
( Internal resistance 650
33 }.IF
I
I
L-~C~_J
560
Amplifier set
jlPC1237H
249
,uPC1237H
NOTE FOR USING pPC1237H
1. FUNCTION FOR OUTPUT OFFSET DETECTION (pin 2)
1) If too much DC current flows through a speaker voice coil due to large output offset DC level, the voice coil might
be overheated and the speaker might be broken. To prevent the damage, it is necessary to detect the Output Offset
DC level and to disconnect the speaker from the power amplifier by breaking off a relay if the detected DC level is
shifted beyond a threshold level. pPC1237H has a function to detect both the positive and the negative Output Off·
set DC level with its single power supply. As shown below, you can easily make the positive and the negative thresh·
old level equivalent and also set up their level by choosing proper resistances.
2) How to determine the threshold levels of Output Offset detection. (±Vth)
[1] The threshold level of positive output offset detection (+Vth) is given by Eq. (1).
RA
+Vth = (2 + - ) • Vth +2,
Re
........................................................... (1)
where Vth +2 is the original positive threshold level of pin 2, and Vth +2 = 0.62 V TYP.
[2] The threshold level of negative Output Offset detection (- Vth) is given by Eq. (2).
- Vth = - { - Vth - 2 • (2 + RA) + Ic2 • RA },
Re
.............................................. (2)
where Vth - 2 is the original negative threshold level of pin 2, and
Vth-2 =-0.17 V TYP.
and Ic2 is the current from pPC1237H and,
Ic2 = 12.5 pA TYP.
at nearly - Vth.
3) You can easily find how to make ±Vth level equivalent as shown below
RA
+
{
_
RA
}
(2 + - ) • Vth 2 = - -Vth 2· (2 + - ) + Ic2 • RA ,
Re
Re
...................................... (3)
therefore determine RA, Rs and Re from Eq. (3)
Attention; The original positive and negative threshold level at pin 2 without any resistances are unbalanced; +Vth
= 0.62 V TYP. and - Vth = -0.17 V TYP.
Example of design
If you need the output offset threshold level ±Vth to be ±2.0 V, determine RA, Rs and Re as shown below.
[1] Substitute 2.0 to +Vth in Eq. (1) and obtain RA/Re.
RA
2.0 = (2 + - ) X 0.62
Re
RA;:! 1.226
Re
[2] Substitute - 2.0 to - Vth in Eq. (2) and obtain RA (Rs) and Re.
-2.0 = -0.17 (2 + 1.226) - 12.5 (pA) X RA (kn) (V)
RA = 116.1 kn
Re = 94.7 kn
Therefore, if you need ±Vth to be 2.0 volts, choose RA , Rs and Re as shown below.
RA = Rs = 120 kn and Re = 91 kn
The lower limits of RA and Rs are given by the maximum rating (± 3 mA) of pin 2 and
+Ve
-=---£. < ±3 (mA)
RA(B)
In case of recommended condition, that is RA = Rs = 56 kn and Re = 00, ±Vth can be obtained as shown below.
[1] +Vth = (2 + 56 (kn))
0.62 = 1.24 (V)
t--1~~IIIr---o
00
RS*
[2] -Vth =-0.17 (2 + 56 (kn)) -12.5 (pA) X 56 (kn) = -1.04 (V)
Vth
The threshold level' of )
( Output offset detection
00
fig. 1
* Rch
power amplifier output terminal is usually an imaginally GND
as seen from Lch power amplifier, so that the equivalent circuit
can be obtained as shown above.
250
JLPC1237H
2. FUNCTION OF AC LEVEL DETECTION
When you turn off the power switch, it sometimes causes a shock-off noise, therefore it is necessary to break off the
relay and then to keep the power amplifier apart from loud speaker at the moment that power switch is turned off. In
other words, the protection circuit is required to have a function to detect that power-off time. However, in fact, it is
difficult to detect that power-off time from actual DC supply voltage line. Because it cannot be turned 0 V instantaneously due to a large capacitance inserted between the power supply line and GND. In case of pPC1237H, it can
detect this power-off time from AC power supply directly, that is, this is a function to detect AC level.
The AC power supply level (usually 50 Hz or 60 Hz) can be transmitted to pin 4 through a half-wave rectification circuit
as shown below.
And it works within a wide range of AC level by choosing a proper resistance as R4 (Refer to the characteristic curve
shown as fig.5 for the choice of R4), If power switch is turned off while the relay is being made ON and the speaker is
being connected to the power amplifier output, the relay will be broken OFF to disconnect the speaker after a time
delay (AC OFF mute) according to the discharge time constant determined by the voltage on pin 4, the external
capacitance C4, and the internal resistance of the IC.
fig. 2
3. FUNCTION OF OVERLOAD DETECTION (pin 1)
The original threshold level of pin 1 is 0.67 V TYP. In case of using a constant-current drive, as the means of detection,
the threshold current level is 110 pA TYP. When current which is larger than 110 pA flows to the IC, the relay will be
broken OFF.
Note;
The overload detecting circuit is not included in the
detection.
Ie because of patent problems. Use the external circuit as an overload
4. FUNCTION OF LATCHING AND AUTOMATIC RESETTING (pin 3)
If the IC detects the abnormal condition such as the larger output offset level or the overload, the IC can make the relay
broken OF F. And then, two functions can be selected after the condition returns to the normal state. One is that the
relay is made ON automatically and the other is that it keeps the relay broken off until once the power switch is turned
off and then is turned on again.
The former is a function of automatic resetting and the latter is a function of latching. pPC1237H has both functions and
can be selected either functiun by using pin 3. In case of latching, connect pin 3 to the ground through the capacitor,
which is for preventing misoperation. For automatic resetting, connect it to the ground directly. This function is valid
for both overload detection and output offset detection.
5. TIME DELAY FROM POWER AMPLIFIER POWER SWITCH ON TO RELAY ON (power-on mute at pin 7)
To suppress shock-on noise generated by power ON, a time delay is provided by connecting a circuit with a time
constant. This time delay is set to make relay ON to connect speakers after enough time for the power amplifier and the
preamplifier to reach a stable operating condition. The ON mute time is determined as follows,
T (ON mute) = - C7 • R7 • Qn
Va - V7
,
Va
where Va is reference voltage at pin 8, 3.40 volts, TYP. and V7 is threshold level at pin 7, 2.06 volts, TYP.
R7
~ToPins
Iji C7
-rtr
fig. 3
6. HOW TO MAKE IT WORK WITHIN A WIDE RANGE OF POWER SUPPLY VOLTAGE (pin 8)
By choosing a proper resistance Ra connected to pin 8, the IC can work within a wide range of power supply voltage
Vee from 25 to 60 volts.
In case that pin 8 is directly driven by a regulated power supply, set Va to 3.40 volts, TYP. As for the choice of Ra
value, refer to the characteristic curve shown as fig.6.
RS
% - - -.....ovcc
fig. 4
251
jlPC1237H
fig. 6 OPTIMUM VALUE
OF EXTERNAL RESISTANCE RS
fig. 5 OPTIMUM VALUE
OF EXTERNAL RESISTANCE R4
R4 to VAC Characteristic
RS to V CC Characteristic
50
I
40
/
20
J
/
~
I
00
cr:
/
,/
,,~
.::.:
I
I
~
cc
j
30
20
V
"..,
~
-'
",..",~
",..", io-"""
"..,
",..",
l....,..oo ~
J
/
o
20
/
30
40
50
Vee - Supply Voltage - V
J
10
{
/
I
o
J
RS
10
20
30
40
50
60
@---Wr---o Vce
VAC - Ae Supply Voltage (50 Hi) - Vr.m.s.
Example) Use of E-24 series.
Select 15 kn RS for 45 volts Vcc.
If no resistance of specified value is available,
choose a resistance which is as close as possible
to and lower than the value specified by the diagram.
Example) Use of E-24 series.
Select 24 kn R4 for 40 volts r.m.s. V AC'
If no resistance of specified value is available,
choose a resistance which is as close as possible
to and lower than thevalue specified by the diagram.
252
60
jlPC1237H
TEMPERATURE CHARACTERISTIC
Vs' TON mut, Vth4, Vth+2, and Vth1 to Ta Characteristics
VCC=45 V
RS=15 kQ
5
i
1.0 -
4.0
>
I
~
4
->
>
I-
=>
I
~3~
z
~
N
.s
>
3.0 ";0.5
2
.s
f--
Vs
"""
r-~
~
- - --- --
~ ~ ........
.......;:::: ~ .......
...
r--- r-- ~ ::a... ......
. -......r-- ......
-20
o
- ...... ......
20
40
~
r-- ~ !-.l.Vth4
.....
I
I
~
TON MUTE- r--
......
-
60
Vthl
........
r0-
~
Vth+2
Vth-2-
N
I
80
Ta - Ambient Temperature -'C
253
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1180C
DD
DOLBY B-TYPE NOISE REDUCTION PROCESSOR
DESCRIPTION
The pPCl180C is a monolithic integrated circuit specifically designed to realize the Dolby B-Type Noise Reduction
System.
The device consists of a Buffer Amplifier (B.A.), a Noise Reduction Processor (N.R.Processor) consisting of an Inverter
Amplifier (INV), a Side Chain Amplifier (SCA), an Overshoot Suppression Circuit (OS), a Voltage Control Amplifier
(VCA), an Integration Circuit (INT), a Hi-Pass Filter (HPF), and a Detector Circuit (DET).
The IC is encapsulated in a 16 pin, dual-in-line plastic package.
Available only to licensees of Dolby Laboratories Licensing Corporation, San Francisco, from whom licensing and application information must be obtained.
"Dolby" and the Double-D symbol are trade marks of Dolby Laboratories.
FEATURES
• Very close matching to standard Dolby Characteristics
• Use's Low Noise Devices
Buffer Amp. Noise Level (6 dB gain)
-98 dBv
(CCIR/ARM)
Noise Reduction Processor Noise Level
-80 dBv
(CCIR/ARM)
Buffer Amp. Distortion
0.02 %
(f = 10 kHz)
Noise Reduction Processor Distortion
0.03 %
(f= 333 Hz)
Noise Reduction Processor Distortion
0.08 %
(f=10kHz)
• Low Total harmonic distortion (at Dolby level)
• Low supply current
9 mAo
Icc
FUNCTIONAL BLOCK DIAGRAM
r------------------------------------,
I
16
Vee
I
r--------------------------------~I
I
II
I
I I
Noise Reduction Processor
Power
Ref-l
Supply
I
I
I
DET
£l·
I
-M-
I
A
i
IL_
.
2 __ 1
IN-l
254
8
_
OUT-l
IN-2
OUT-2
IN-3
OUT-3
IN-6
IN-5
OUT-5
IN-4
6
I
I
_.J
By-Pass
By-Pass
By-Pass
,uPC1180C
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Supply Voltage
Vcc
Power Dissipation
Po
28
V
350*
mW
Operating Temperature Range
T opt
-15 to +75
Storage Temperature Range
T stg
-55 to +125
Lead Temperature
TL
°c
°c
°c
260**
*Value at Ta = 75°C
**Soldering at 10 s MAX.
RECOMMENDED OPERATING CONDITIONS (Ta = 25°C)
CHARACTERISTICS
SYMBOL
MIN.
TYP.
MAX.
24
26
V
12
dB
Supply Voltage
VCC
18
Buffer Amp. Gain
Av-(B.A.l
6
ELECTRICAL CHARACTERISTICS [Ta = 25
°c, Vee = 24 V,
UNIT
Dolby Level = 1 Vr.m.s. (= 0 dBv)]
TEST CONDITIONS
CHARACTER ISTICS
SYMBOL
Supply Current
ICC
No Signal
Signal Handling
V om (1)
f= 10 kHz, T.H.D.= 1 %, RL =5 kn
Distortion
T.H.D.(1)
f= 10 kHz, Vo=6 dBv, RL =5 kn
Noise Level
V no (1)
Input Shorted, Using CCIR/ARM
Av
f=333 Hz
V om (2)
MIN.
TYP.
MAX.
UNIT
9
12.5
rnA
Buffer Amp.
I NV Amp. Gain
15
dBv
17
0.02
0.07
%
-98
-88
dBv
-0.5
0
0.5
dB
REC, f=333 Hz, Vo=O dBv, RL =10 kn
15
17
12.5
Noise Reduction Processor
Signal Handling
dBv
dBv
Signal Handling
V om (3)
REC, f= 10 kHz, Vo=O dBv, RL = 10 kn
Distortion
T.H.D.(2)
P.B, f=333 Hz, Vo=O dBv, RL=10 kn
0.03
0.08
Distortion
T.H.D.(3)
REC, f= 10 kHz, Vo=O dBv, RL = 10 kn
0.08
0.14
%
Noise Level
V no (2)
REC, Rg=O, Using CCIR/ARM
-80
-70
dBv
REC Mode Response
F.R(1)
f=333 Hz, Vin=O dBv
-0.7
0
+0.7
dBv
REC Mode Response
F.R(2)
f= 1 kHz, Vin=-20 dBv
-18.1
-16.7
-15.3
dBv
REC Mode Response
F.R(3)
f=5 kHz, Vin=-20 dBv
-18.0
-16.8
-15.6
dBv
REC Mode Response
F.R(4)
f=5 kHz, Vin=-40 dBv
-30.4
-29.7
-28.8
dBv
Cross Talk
Vcrs
REC, f=333 Hz, B.A. to N.R.Processor,
Vo=15dBv
-70
dBv
I
15
%
For alignment instruction see section 3.8 of licence information manual.
255
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1252H2
VCA FOR dbx NOISE REDUCTION SYSTEM
DESCRIPTION
PACKAGE DIMENSIONS
in millimeters (inches)
The pPC1252H2 is dbx noise reduction
19.5 MAX.
(0.76 MAX.)
system VCA (Voltage Controlled Amplifier),
used in tape deck and other audio equip-
2.8±0.2
(0.11)
o
C1
(C 0.04)
ment.
The pPC1252H2 features excellent lineality
VCA for wider input level due to N EC's
super low noise and high hFE NPN/PNP,
complementary process.
Since the package is 8 pin SIP. It can be
0.25
built in a compact set.
(0.01)
1.0 ± 0.1
17.78
(0.7)
--1-4----
(0.04)
FEATURES
• . Wide operating supply volt~ge
Vee
= ±4 to ±15 V
(TYP. ±12 V)
= -30 dB to +30 dB)
Excellent lineality Control Constant
Ve = -5.9 mV/dB (Av
•
Low total hamonic distortion
T.H.D.
•
Low noise
NVa = -94 dBV TYP. (Vee = ±12 V, RIN = 33.2 kU,
•
= 0.01
% TYP.
(Vee = ±12 V, f = 1 kHz, Va
= 0 dBV)
Av = 0 dB, BPF = 10 Hz to 20 kHz)
Vce
FUNCTIONAL BLOCK DIAGRAM
~----------------~v'v~--->20kQ
:>-----oVo
256
jlPC1252H2
ABSOLUTE MAXIMUM RATINGS (T a = 25°C)
Supply Voltage
VCC, VEE
+15
V
Supply Current
Icc
30
mA
mW
PD
330*
Operating Temperature Range
Power Dissipation
T opt
- 20 to +75
0
Storage Temperature Range
Tstg
-40 to +125
°c
C
* Value at Ta = 75°C
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
Operating Supply Voltage
VCC, VEE"
±4
±12
±15
V
ISET
-
2.0
-
mA
Vin
-40
+10
dBV
Bias Current
Input Level Range
UNIT
** See Note
ELECTRICAL CHARACTERISTICS (Ta = 25
CAHRACTER ISTIC
SYMBOL
°c, VCC =+12 V, VEE =-12 V, ISET = 2
rnA, RIN = ROUT =33Iill, f= 1 kHz)
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
1.0
2.0
3.0
mA
Non Signal
6
20
nA
Non Signal
Supply Current
ICC
Equivalent Input Bias Current
liN
Gain Cell Idling Current
IDLE
20
tJ.A
Non Signal
VOFF
±0.5
mV
Av
Gain Cell Offset Voltage
Control Constant
Vc
-5.9
-6.1
mY/dB
Total Harmonic Distortion
T.H.D.1
0.007
0.07
%
Total Harmonic Distortion
T.H.D.2
0.02
0.10
%
Total Harmonic Distortion
T.H.D.3
0.02
0.15
%
Output Noise Level
NV
-94
-84
dBV
Symmetry Control Voltage
VSYM
0
+4
mV
Note)
-5.8
-4
= 0 dB, T.H.D. ~ 0.07 %
Av = -30 dB to +30 dB
Av = 0 dB, Vo = OdBV, BPF = 400 Hz to 5 kHz
Av = +20 dB, Vo = OdBV, BPF = 400 Hz to 5 kHz
Av = -20 dB, Yin = OdBV, BPF = 400 Hz to 5 kHz
Av = 0 dB, RIN = 33 kn, BPF = 10 Hz to 20 kHz
Av = 0 dB, T.H.D. ~ 0.07 %
VCC, VEE and ISET are defined as follows.
JlPC1252H2
I
VEE - 4·V BE
SET
=----R
EXT
VEE -
2.4
2mA
REXT
tISET
REXT
257
,uPC1252H2
TEST CIRCUIT
(1) ICC
~-~-OVOUT
(2) Vc
+12 V
...----...---'V\J'\r-"'-;" VR 1
20 kQ MAX.
-12 V
33 kQ
47 pF
(3) T.H.D. 1-3
33 kQ
47 pF
tC1 =400 Hz 1-12 dB/oct
tC2=5 kHz
tC1
-:>----4----1 /
. - - - - ' \ / \ J ' \ r -....
120 kQ
tC2
B. P. F.
\
1--------,
i~~:k:
MAX.
-12 V
T.H.D.1; Make T.H.D. minimum with VR 2 after adjusting GC1 = 0 mV with VR 1 at V in = 0 dBV
T.H.D.2; Make T.H.D. minimum with VR2 after adjusting GC1 = -120 mV with VR 1 at Vin = -20 dBV
T.H.D.3; Make T.H.D. minimum with VR 2 after adjusting GC1 = +120 mV with VR, at V in = 0 dBV
2sa
,uPC1252H2
(4) VNO
fC1 = 10 Hz } 12 dB/oct
fC2=20 kHz
fC1
~-----t
/
fC2
B.P.F.
\
I---i
(5) VSYM
+ 12
V
VR1
.---..----.J'vv\r--_~>
20 k Q
MAX.
33 kQ
47 pF
S.G
tCl
-
tC2
.~
+ 12
V
~vv--l~~2kQ
V.T.V.M
T.H.D.
400 Hz-5 kHz BPF
1/2 J,lPC4558C
-12 dB/OCT
!MAX.
D.V.M
-12 V
-12 V
Make T.H.D. minimum with VR2 after adjusting GC1
Voltage of 4 pin.
= 0 mV with
VR 1 at V in
= 0 dBV
and Measure Symmetry Control
259
JlPC1252H2
VOLTAGE GAIN vs.
CONTROL CONSTANT VOLTAGE
VCC=±12 V
1=1 kHz
60
50
f".. l'-.l'.
CD
"C
I
c:
.iij
Cl
.....
til)
~~
-.....:
~
-300 -200 -100
,
~
I
,20
30
<
-
30
20
10
~
I
c:
0
:e
O~
-10
>
Vcc + 12 V
1-1 kHz
BPF
(400 Hz to 5 kHz)
40
~~
Q)
2
TOTAL HARMONIC DISTORTION vs.
INPUT VOLTAGE and OUTPUT VOLTAGE
100
200
.B
300
,~ ~
~~
r'\
"1
-40
-50
-60
0.3
f--
v~r~m120
I Ll1
111111
-8
-10
10
II \,
100
1k
19 k
f - Frequency - Hz
260
100 k
f,\
IIII
1M
dB
,uPC1252H2
Note for use
1. Since pPC1252H2 is designed for Noise Reduction System, recommend to use pPC1252H2 with pPC1253H2 (RMS Revel
Sensor), which controlspPC1252H2, in case of composing dbx NR System.
2. Documents issued by dbx, in corporated have priority over NEC, such as application note or data about dbx NR system.
3. If you plan to use pPC1252H2 except dbx NR system, inform NEe of it as soon as possible.
APPLICATION CIRCUIT
33 kQ
J,tPC1252H2
47
F
Signal INo---1
1 JlF
Signal OUT
GCla-----------------~
r------ o - -------,
:
-'"
I
I
~
I
VEE
I
20 kQMAX.
0--'VVVV'v--0 VCC
I
I
I
I
I
I __________________
VCA SYM ADJ.
I
L
~
·1. Possible to connect 4 pin to GND in case of using,this IC at T.H.D. ~ 0.05 %.
·2. Iset is set to be 2 rnA at REXT= 4.7 kS1, VCC = 12 V, VEE = -12 V, so readjust REXT in case that supply voltage is different from above.
Gel is an input terminal of IlPC1252H2 control voltage.
261
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1253H2
RMS LEVEL SENSOR FOR dbx NOISE REDUCTION SYSTEM
DESCRIPTION
PACKAGE DIMENSIONS
in millimeters (inches)
The pPC1253H2 is dbx noise reduction system RMS
(Root Mean Square) level sensor, used in tape deck and
other audio equipment.
19.5 MAX.
(0.76 MAX,)
2.8±0.2
(0.11)
o
The pPC1253H2 features high accurate RMS level sensor
for wide input due to N EC's super low noise and high
hFE PNP process.
Since the package is 8 pin SIP, it can be built in a compact set.
0.25
(0.01)
1.0±0.1
(0.04)
17.78
(0.7)
FEATURES
•
Wide operating supply voltage
Vee = ±4 to ± 15 V (TYP. ± 12 V)
•
Excellent lineality Control Constant
Vc = 5.9 mY/dB
•
Wider input range
vin
= -40 dBV to +10 dBV
FUNCTIONAL BLOCK DIAGRAM
10 kQ
Vee 0----'VI/'v---0 VEE
0.1
Vino--f
262
f.1
.--'VV'\,--,
Vout
(Ve)
,uPC1253H2
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage
Vce, VEE
±15
V
Supply Current
ICC
30
mA
Power Dissipation
PD
330*
mW
Operating Temperature Range
T opt
-20 to +75
°c
Storage Temperature Range
T stg
-40 to +125
°c
* Value at Ta = 75°C
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC
Operating Supply Voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC,VEE
±4
± 12
±15
V
Vin
-40
+10
dBV
Input Level Range
Bias Current
ELECTRICAL CHARACTERISTICS (Ta
CHARACTERISTIC
24
Is
SYMBOL
pA
= 25°C, VCC = +12 V, VEE =-12 V, f = 1 kHz,
MIN.
TYP.
MAX.
UNIT
Zin
= 33 kn)
TEST CONDITIONS
Supply Current
ICC
0.9
2.0
mA
No Signal
Output Level
VO*
111
136
161
mV
VIN = 0 dBV
Control Constant
Vc
5.8
5.9
6.1
mV/dB
Vin = -40dBVto +10 dBV
* Output Level is defined as follows.
VOUT
263
,uPC1253H2
TEST CI RCUIT
(1) ICC
20 Q
1------0
+ 12 V
33 kQ
Vino--1
0.1 pF
3.3 kQ
) - - - - - 0 Vout
0.01 pF
~--------------~n-12V
20 Q
(2) V o , Vc
.------------i~
+ 12
V
33 kQ
0.1 pF
3.3 kQ
0.01 pF
V
DC VOLT METER
MQ
~--------------~()-12V
Note for use
1. Since JlPC1253H2 is designed for dbx Noise Reduction System, recommend to use JJPC1253H2 with JlPC1252H2 (VCA) in
case of composing dbx N R system.
2. Documents issued by dbx incorporated have priority over NEC, such as application note or data about dbx NR system.
264
jlPC1253H2
APPLICATION CIRCUIT
JlPC1253H2
33 kQ
L---~-------------oOUT
0.01 JlF
+--N-~""""---'\I\/\I---.n
i~~;~;'-
Vee
--1
D--"NVv-O
I
:
Vee
VEE: VEE VEE
* 1L __ ~~ ~~A~~..J
*1.
Possible to omit RMS SYM.ADJ. in case of using this IC with J.,LPC1252H2 at T.H.D.
*2.
Make GND common about these terminals.
*3.
This resistor is for RMS time constant.
~
0.05 %.
Connect 7 PI N OUT to GCl of J.,LPC1252H2 (VCA).
TYPICAL CHARACTERISTICS (Ta = 25°C)
SUPPLY CURRENT, CONTROL CONSTANT vs.
AMBIENT TEMPERATURE
OUTPUT LEVEL vs. INPUT LEVEL
Vee=±12 V
f=l kHz
--
10
CD
~-
'0
.
§:
0.5
:::J
en
U
~c
I
u
}:}
I
5
---
~
I--~
~~
~ ~t-"
I--- ~
-
-100
-50
lA
~r1
!h ~
'Ve
V~
~
E
I
Q)-
>
Q)
V~
V
0
-25
o
25
Ta - Ambient Temperature -
50
75
-doD
-,
'5a.
'5
-3bo
-j
1-
-4PO
I
o
50
>- -1100
0
o
100
0
1/
...J
~v
u
>
Ta=25 'C
~ ~ "Ta=-25 'C
~
r,-
0
u
q
~~
'lee
'E
U
300 I
20(
Ta=75 "C
VCC=±12V
'=1 kHz
I
-500
Vin - Input Level- dBm
'e
265
1. ALPHA-NUMERICAL INDEX
2.
QUICK REFERENCE GUIDE
3. CROSS REFERENCE GUIDE
4. MAINTENANCE AND OBSOLETE TYPES
5.
GENERAL STATEMENT
-(:( NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
o History
0
Types and Features
o Type Number Designation
0
Device Technologies
-(:( STANDARDS OF INTEGRATED CIRCUITS
-(:( HINTS ON CORRECT USE
-(:( TECHNICAL SYMBOLS AND TERMS
-(:( RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
7.
6-1.
CAR AUDIO
6-2.
HOME AUDIO
6-3.
PORTABLE AUDIO
TV APPLICATIONS
8. DIGITAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11. ARRAYS
12. OTHERS
13. APPLICATION NOTES
PORTABLE AUDIO
INDEX
Page
~PC1018e
AM-RF, MIX, IF + FM-IF Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . 272
~PC1222e
AM Tuner + FM-I F Detector
~PC1222e(R)
AM Tuner + FM-I F Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278
~PCl197e
FM-MPX Demodulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
286
~PCl158H2
Pre Amplifier with ALe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
296
~PC1204e
REC/PB Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 302
~PC1217G
REC/PB System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .. 307
~PCl177H
3.5 W (4 n) BTL Power Amplifier .......... . . . . . . . . . . . . . . . .. 314
~PC1212e
1 W (4 n) Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326
~pe1213e
2.4 W (4 n) Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 336
~PC1218H
250 mW (8 n) BTL Power Amplifier. . . . . . . . . . . . . . . . . . . . . . . . .. 347
278
~PC1221e
Pre + ALe + 1 W (4 n) Power Amplifier. . . . . . . . . . . . . . . . . . . . . .. 350
~PC1263e2
Dual 1.2 W (8 n) Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .. 357
~PC1277H
Dual 4.2 W (4 n) Power Amplifier ... . . . . . . . . . . . . . . . . . . . . . . .. 363
~PC1350e
Pre + ALe + 450 mW (8 n) Power Amplifier . . . . . . . . . . . . . . . . . . . . 368
-
269
PORTABLE AUDIO
BLOCK DIAGRAM
Tuner Block
R CH.
OUT
L CH.
OUT
Ant.
Ant.
/JPCl197C
H - - - -.....
AM OUT
/JPC1018C
AF Block
(1) Monaural Radio Cassette
MIC
~
HEAD
-
I
I
Pre
Amp.
I
I-u-~p_o
_ A_mP-..l.1----1rr1
~
SP
I
/JPCl158H2
I
DISCRETE
I
/JPCll77H (BTL)
/JPC1212C
/JPC1213C
(2) Stereo Radio Cassette
------~__p_O_A_m_p_.~r-----Qjsp
/JPC1204C
1
I
L _ _ _ _ _ ..l
/JPCl158H2 + DISCRETE
~______~-u------~__p_O_A_m_p_.~r---~Qjsp
/JPC1204C
1
I
L _ _ _ _ _ ..l
,uPC1158H2 + DISCRETE
270
/JPC1263C2
/JPC1277H
IL
_ _ _ _ _ ...JI
/JPC1277H
PORTABLE AUDIO
(3) Cassette Tape Recorder
,---rr1
MIC
~~---~~~--~~-pr-e-A-m-p-'~--------------~--PO--A-m-p-.~------~ ~
SP
J.LPC1221C
J.LPC1350C
(4) Mini & Micro Cassette
SP
Rec/Play
SW
J.LPC1217G
J.LPC1218H
271
BIPOLAR ANALOG INTEGRATED CIRCUIT
IlPC1018C
AM TUNER, AM/FM-IF AMPLIFIER CIRCUIT
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The IlPC1018C is a silicon monolithic integrated circuit designed for AM/FM radios and cassette tape recorders with an
AM/FM radio.
The IlPC1 018C contains a AM tuner and FM-I F amplifiers.
FEATURES
PACKAGE DIMENSIONS
• Wide operating voltage.
V CC
in millimeters (inches)
= 2.5 '" 6.0V
• Excellent low voltage characteristics.
I
• High gain FM-IF amplifiers.
• The AM stage is composed of a mixer, a local oscillator, a
I F amplifier and an AGe circuit.
• The AM stage has an excellent AGC characteristic and
low distortion.
19.4MAX
~7@MAX)
I
i:~~-;:[1~
* Typical
04 ",0.15
(0016)
BLOCK DIAGRAM (Top View)
AM
CON.
AM
CON.
AM
AM
AGC
IN
OUT
IF IN
IN
FM IF
IN (1)
GND (1)
AM
LOCAL
OSC
272
FM IF
OUT (1)
+B2
AM
AM
IF OUT
BYPASS
GND (2)
FM IF
IN (2)
+B1
FM IF
OUT (2)
FM
BYPASS
value unless
otherwise noted.
0·- 15·
jlPC1018C
ABSOLUTE MAXIMUM RATINGS (Ta
Supply Voltage
= 25°C)
9.0
V
Package Dissipation
Vee
PD
350*
mW
Operating Temperature
T opt
-20 to +75
°e
Storage Temperature
T stg
-40 to +125
°e
*Ta
RECOMMENDED OPERATING CONDITION (Ta
CHARACTERISTIC
Supply Voltage
= 25°C)
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
2.5
4.0
6.0
V
ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
= 75°e
SYMBOL
(Ta
= 25°C,
MIN.
TYP.
VCC
= 4.0V)
MAX.
UNIT
TEST
CIRCUIT
TEST CONDITIONS
Circuit Current
ICC(AM)
4.5
8.0
11.5
mA
No Signal
(AM)
Voltage Gain (MIX)
Av (MIX)
7.5
11.5
15.5
dB
f=1 MHz, RG=50n
RL =lkn
(AM)
3
Voltage Gain (I F)
Av (I F)
44.0
50.0
56.0
dB
f=455kHz, RG=50n
RL=330n
(AM)
3
Circuit Current
ICC(FM)
5.0
9.0
13.0
rnA
No Signal
(FM)
4
(FM)
4
(FM)
Voltage Gain (I F 1 )
Av (1Ft!
38.0
42.0
46.0
dB
f=10.7MHz, RG=50n
RL =1kn
Voltage Gain (I F2 )
Av (lF 2 )
27.0
33.0
39.0
dB
f=10.7 MHz, RG=50n.
RL =330n
TEST CIRCUIT 1
1
2
TEST CIRCUIT 2
Vee
Vee
O.022,uI I
r
O.022,u
O.022,u
O.022,u O.022,u
273
,uPC1018C
TEST CIRCUIT 4
TEST CIRCUIT 3
vCC 0----..._--.
330Q
O.022,u 6
ffOQ
50Q
TYPICAL APPLICATION
1kQ
4.7kQ
FM
+ Bl---<-+-L...........-.+--' I
~EI--_80 (f = 1.4MHz)
GND~B'tt
@ AM IF COIL
CFZ·455C (TaKa)
.--,
Call
BAND WIDTH 6kHz MIN.
SELECTIVITY (± 10kHz DETUNING) 20dB MIN.
GND
Batt
®
Base
7P
BLACK
TYPE NO.
BODY COLOR
Call
Batt
®
7 LC·252222No. (TaKa)
AM DETECTION COIL (455kHz)
i~(S
4
1
6
S
1-3 146T
2-3 37T
4-6 33T
GND
Diode
CAPACITOR Co··· .. ··· '180pF
Qu •.•••••.•••.•..•.•••. '" ·70 ± 20%
FM DETECTION COIL (10.7MHz) (TaKa)
PLiMARY
SECONDARY
TYPE NO.
119AC-470085Ls
119FC-560061N6
CAPACITOR
(GRAY) 47pF(CI) 4-2
(BLUE) 56pF(C2) 1-2
5Y;T
6T
2-3
2-3
8T
6T
1-5
4-6
5J1T
IT
7P
Diode
Call
Diode
GND
®
FM CERAMIC FILTER (10.7MHz)
CFS·l07M (TaKa)
1~rTI~3
c::5 -L E=:J
20
32 1
TIT
l. INPUT
2. GND
3. OUTPUT
02
- 3dB BAND WIDTH ........ ·300±50kHz
-20dB BAND WIDTH ........ ·600kHz(MAX.)
INSERTION LOSS .... · ...... ·6dB(MAX.)
275
,uPC1018C
TYPICAL CHARACTERISTICS (Ta = 2SoC)
FM-IFI
OUTPUT VOLTAGE
VS. INPUT VOLTAGE
AM-MIX, AM-IF
OUTPUT VOLTAGE vS.INPUT VOLTAGE
3000
3000
,.hL
1000
700
vi
E 500
~
E
AM
I
300
I
'5
.s
IF
I
I
.rg
FM-IF2
OUTPUT VOLTAGE vs.
INPUT VOLTAGE
100
70
50
1/ AM-MIX.
I
I
~
300
(5
100
70
.e
50
0
30
>
'5
I
:::J
30
I
0
>
I
V
10
7
5
I
0
>
I
V
40
60
80
100
120
I
>
'5
.s
:::J
0
I
I
0
>
3
o
20
40
60
80
100
~
1~
40
60
00
100
Vi-Input Voltage-dB,uV
500
300
E
;;
vi
E
~
100
70
50
E 100
I
o
140
FM-IFI
OUTPUT VOLTAGE vs. FREQUENCY
500
>
I
Vi-Input Voltage-dB,uV
vi 300
5
"0
120
I
I
3
140
I
I
I
30
10
7
5
AM-MIX
I
100
70
50
10
7
OUTPUT VOLTAGE vs. FREQUENCY
E
~
:;
.e
30
\
:::J
10
0
5
I
0
>
50k70k100k
300k 500k
1M
3M 5M
10
30M
10M
f- Frequency - Hz
300k 500k
50k70k100k
1M
3M
5M
30M
10M
f-Frequency-Hz
AM-IF
OUTPUT VOLTAGE vs. FREQUENCY
FM-IF
OUTPUT VOLTAGE vs. FREQUENCY
500
vi
500
300
300
E
vi
~
E
I
'5
E
~
100
70
50
-
30
I 100
Q)
10
50k 70k lOOk
300k 500k 1M
3M 5M
70
'0
50
.s
30
>
'5
"
:::J
0
bO
.rg
"
.e
I
0
>
E
10M
..,....
....
"-
,;'
:::J
\
0
I
0
>
"-
"
10
30M
f-Frequency-Hz
50k 70k lOOk
300k 500k 700k 1M
f-Frequency-Hz
276
3M
5M 7M 10M
30M
140
P.W. BOARD PATTERN
AM<±>
o
o
0)
I
.. AM IN
AM OSC
FM IN
o
NEe
CIOl8C
o
1:::
."
('")
~
o
~
(X)
('")
N
.,J
.,J
BIPOLAR ANALOG INTEGRATED CIRCUIT
f.J,
PC 1 222 C , f.J, PC 1 222 C ( R)
AM TUNER, FM IF SYSTEM WITH QUADRATURE DETECTOR
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The MPC1222
is a low voltage silicon monolithic IC. It is designed for using in AM tuner and FM-IF.
MPC1222 contains an AM Mixer, AM/FM IF amplifier, AM detector, FM detector and also AGC circuit.
This IC is suitable for using in AM/FM radio, radio cassette etc ..
FEATURES
• Wide operating voltage.
V cc=2.0 V -6.0 V
e Excellent low voltage characteristics.
•
AM stage is composed a Mixer, local oscillator, I F amplifier, AM detector and AGC circuit.
•
FM stage is composed a high gain FM-I F amplifier and FM detector.
• The AM stage has an excellent AGC characteristic and low distortion.
• MPC1222C(R) is designed for upper heterodyne.
• MPC1222C is designed for lower heterodyne.
BLOCK DIAGRAM (Top View)
278
FUNCTION
AM Stage· . . . . . . . . . . . . . . . . . . MIXER CIRCUIT
LOCAL OSC
IF AMPLIFIER
DETECTOR CIRCUIT
AGC CIRCUIT
FM Stage . . . . . . . . . . . . . . . . . . . IF AMPLIFIER
DETECTOR CIRCUIT
PACKAGE DIMENSIONS in millimeters (inches)
* Typical value unless
otherwise noted.
CONNECTION DIAGRAM
Pin No.
CONNECTION
Pin No.
1
AM LOCAL OSC
9
AM OUTPUT
2
IF BYPASS
10
AGC INPUT
3
FM IF INPUT
11
AM IF INPUT
4
GND
12
AM MIX BIAS
5
DET. INPUT (1)
13
AM MIX OUT
6
DET. INPUT (2)
14
AM RF AGC BYPASS
7
FM OUTPUT
15
AM MIX INPUT
8
VCC
16
AM IF AGC BYPASS
CONNECTION
279
,uPC1222C,,uPC1222C(R)
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Supply Voltage
VCC
Package Dissipation
Po
Operating Temperature
T opt
-20 to +75
°c
Storage Temperature
Tstg
-40 to +125
°c
9.0
V
350*
mW
*Ta= 75°C
RECOMMENDED OPERATING CONDITION (Ta=25°C)
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
2.0
4.0
6.0
V
Supply Voltage
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
(VCC=4 V
FM: f= 10.7 MHz, ~f=±22.5 kHz DEV.
AM: f= 1 MHz, MOD.=30 %
MIN.
TYP.
MAX.
UNIT
ICC-FM
6.5
10
15
mA
VO-FM
35
50
70
mVr.m.s.
Input Limiting Voltage
Vi(lim)
33
39
45
dBJ..LV
I-
Signal to Noise Ratio
S/N-FM
50
60
~
Total Harmonic Distortion
T.H.D·-FM
AM Rejection Ratio
A.M.R.
Drop Voltage Gain Loss
~AV-FM
Circuit Current
ICC-AM
MAX. Sensitivity
CHARACTERISTIC
w
Circuit Current
Detector Output Voltage
(!)
«
m
u.
SYMBOL
0.2
25
0.8
35
-3 dB point from Vo
with 100 dBJ..LV input
%
Vi=80 dBJ..LV
dB
Vi=80 dBJ..LV
AM: 30% MOD.
1.5
5.0
dB
VO=5 mVr.m.s.
VCC=4 -> 2 V
6
12
18
mA
No Signal
Vi-AM
28
35
42
dBJ..LV
VO-AM
25
34
50
mVr.m.s.
«
I-
Signal to Noise Ratio
SIN-AM
45
:E
Oscillation Voltage
Total Harmonic Distortion
Drop Voltage Gain Loss
D.AV-AM
«
Vi=80 dBJ..LV
Vi=80 dBJ,N
Detector Output Voltage
m
TEST CONDITIONS
No Signal
dB
w
(!)
280
fMOD = 400 Hz)
VO=10 mVr.m.s.
Vi=100 dBJ..LV
51
dB
VOSC
150
mVr.m.s.
Vi=100 dBJ..LV
T.H.D.-AM
0.5
2.0
%
Vi=100 dBJ..LV
5
10
dB
VO=10 mVr.m.s.
VCC=4~2 V
fOSC= 1 455 kHz
j.lPC1222C,j.lPC1222C(R}
TEST CIRCUIT
100Q
0.022
JlF
FM
o
FM/AM
AM
+ 33JlF
1-
10 k Q
0.01
JlF
AM
Jl
F
~
Jl
100 k Q
FM
Vee
! '0~2~'~2~
ffi
0.022
F
V.V
T.H ..
0
w
It)
FM
3.9 k Q
" - -_ _ _ _ _- - J
L1:
T1:
T2:
T3:
T4:
L2:
25A-1195-08 (CORIN)
26-1791-13 (CORIN)
CFZ-455C (TOKO)
5251 (TOKO)
12747 (TOKO)
7BA 180JH (TOKO)
AM ANT. COIL
AM LOCAL OSCILLATION COIL (MM)
AM IF COIL
AM DETECTION COl L (455 kHz)
FM DETECTION COIL (10.7 MHz)
PHASE SHIFT INDUCTOR
AM STAGE REFERENCE CHARACTERISTICS
(Vcc=4V, f=1 MHz, MOD=30%, fMOO=400Hz, at APPLICATION CIRCUIT)
CHARACTER ISTIC
SYMBOL
TYP.
UNIT
dBJ..LV/m
TEST CONDITION
Usable Sensitivity
Vi-SIN
48
Maximum Sensitivity
Vi-AM
35
dBJ..LV/m
VO=10 mVr.m.s.
Detector Output
VO-AM
34
mVr.m.s.
Vi=100 dBJ..LV/m
SIN Ratio
SIN
51
dB
Vi=100 dBJ..LV/m
Total Harmonic Distortion
T.H.D.
0.5
%
MOD=30 %, Vi=100 dBJ..LV/m
Drop Voltage Gain Loss
b.AV-AM
5
dB
VO=10 mVr.m.s., VCC=4
S/N=20 dB
~
2V
281
,uPC1222C,,uPC1222C(R}
TYPICAL APPLICATION
FM
100 Q
+
r
0.022
JJF
I
/
I
I
/ e
(J
I
FM/AM SWITCH
AM
10 kQ
AM OUT
9.
2.2 kQ
11
II
0.068
1
II
II
Ll
/ I
/
o
JJF
L2
0
\.0
I
(
\
LOOP ANT.
\
\
\
\
\
\
\
\
\
\
\
\
\
\AM SG
\
\
\
\
\
\
\
FM OUT
\
\
\
\
\
/
V
AM
AM
AM
FM
LOCAL OSCILLATION COIL (MM)
IF COIL
DETECTION COIL (455 kHz)
DETECTION COIL (10.7 MHz)
AM BAR ANT
CORE: ¢ 10 x 80 mm
LO=600 JlH
Q=220
L1: L2=107:25
282
26-1791-13 (CORIN)
CFZ-455C (TOKO)
5251 (TOKO)
12747 (TOKO)
COIL SPECIFICATIONS
(1)
ANTENNA COIL (MW)
25A-1195-08 (CORIN)
Batt(:(:\: 12)
VC
AM SG
GND
(2)
RF INC ~ 15)
La=650 ""H
00=210±20% (at 796 kHz)
1-2 25T 2-3 82T
1-3 107T 4-6 10T
AM LOCAL OSCILLATION COIL (MW) (CORIN)
TYPE NO.
BODY COLOR
7P
BLACK
1-3 99T
4-6 11T
BLACK
VC
GND
(3)
~j(:
Coli
L=260 ""H (±6 %)
Qu>80 (f=1.4 MHz)
Batt
CFZ-455C (TOKO)
AM IF COIL
r--l
~3:B~~
\-~;
Coli
Batt
GND
Base
!..._..J
(4)
AM DETECTION COIL (455 kHz)
TYPE NO.
BODY COLOR
Batt
Coli
~~
1
(5)
S
7P
BLACK
Coli
Batt
:m
Co
1 S
5251 (TOKO)
1-2:2-3=1: 1
04
06
FM DETECTION COIL (10.7 MHz)
TYPE NO.
BODY COLOR
BANDWIDTH 6 kHz MIN.
SELECTIVITY (±10 kHz DETUNING) 20 dB MIN.
CAPACITOR Co ...... 180 pF
Qu ............................ 70±20 %
12747 (TOKO)
7P
BLACK
04
06
CAPACITOR Co ...... 82 pF
Qu ............................ 70±20 %
283
,uPC1222C,,uPC1222C{R)
P.C. BOARD PATTERN
R1· .. ···· .. ·.. •···
R2 ................
R3 ................
R4 ................
R5 ................
RS ................
R7 ................
100 n
51 n
12 kn
560 n
3.9kn
2.2 kn
10 kn
C1
C2
C3
C4
C5
................
................
................
................
................
Cs ................
C7 ................
C8 ................
Cg ................
C10..............
C11 ..............
C12 ..............
284
0.022 JlF
0.022 JlF
33 JlF
33 JlF
0.022 JlF
10JlF
4.7 JlF
0.01 JlF
0.068 JlF
0.022 JlF
33 JlF
0.022 JlF
T1:
T2:
T3:
T4:
L1:
AM LOCAL OSC COIL 2S-1791-13 (CaRIN)
AM IF COIL
CFZ-455C (TaKa)
AM DET. COIL
5251 (TaKa)
FM DET. COIL
12747 (TaKa)
PHASE SHIFT INDUCTOR: 7BA 180JH (TaKa)
,uPC1222C,,uPC1222C(R)
TYPICAL CHARACTERISTICS (Ta =25°C)
AM STAGE
FM STAGE
OUTPUT VOLTAGE, TOTAL HARMONIC DISTORTION, AM Rejection,
AND NOISE VOLTAGE VS. INPUT VOLTAGE
1-- VO-FM
o
-
\.
-10
I I
I I
~
1 I
c
0
Vcc-4.O V
'(FM)-400 Hz
1\
4
V
-40
~~
-50
/
,
\
r-i'
1J
I I
VN
1\
I'
1\
-60
lfl·~·R~
.......
IL
",..-
LloI-±22.5 kHz dey
.....
Lf-
3
-
1.1
o
I
iii
co
40
I
a
30
ro
U> e::
I
::E
en"
\
\
"""'12 [
::C
.-:
a
'/...'r'
10
ex::
I
E 15
I
..:J
.e-
10 0:J
20
0
'0 -10
4
dey.
ICC-FM
II
3
I
J-.I
I.t:. VO-FM'-I-
-~
A
II
2
~ ~
Vee - Supply Voltage - V
E
H-t--+H-/+-I-t-+-+-t-tICC~AM'-I~-+J--t-_+f--:::I14
....
6
I-+-If-+++-++-t-+-If-+-+T.~.D.- AM -+-+-t-+-l4
'::!:
c:i
ex::
1 0t--t-t--H+-+c:::b__1-'f'-9-J--+~-t---+-1-+-+--+-1-+-I12
f-
:ii ~
G~
If-
::C
.-:
9
c:
'0
2
I
::!:
g'iii
10 fte s t = 1.0 MHz rt-t-+-rt-+-+-rt-t-~
f MOD =400 Hz rt-t-+-rt_If-+-+-+-rt-i
MOD = 3 0 %
I-+-+-+-t-Vq~ AM+-+-+-+-.-l
:::E 0
C\l
o
I-
!g
~ ~
ro
C\l
I
T.H.D·-FM 1 - -
5
a
:.::;
l-
5 u
I -30
::E
LL- 40
I
c
2a
c
..c
b
~
I
c
E
en
.J I I
10
2
I A I I
CHANGE OF OUTPUT VOLTAGE, CHANGE OF
MAXIMUM SENSITIVITY vs. SUPPLY VOLTAGE
~
ftest= 10.7 MHz
fMOD=400 Hz
L::.f=±22.S kHz
30
co
Vi - input Voltage - dBJl V
CI RCUIT CURRENT, CHANGE OF OUTPUT VOLTAGE
TOTAL HARMONIC DISTORTION VS. SUPPLY VOLTAGE
CD
3
T.H.D·-AM
~
~
:J:
\
'\
~~
4
010203040 SO 60708090100110120
Vi -Input Voltage- dBJlV
"0
1-1'
j
/IJ
//
1-1- 8
1-1-
:...-
'/
J
00:'::;
I
I
I
c:
ftest.= 1.0 MHz
t--I- 7 :e
fMOD=400 MHz 1-'~
1-- 6 i5
MOD=30 %
SIN-AM
I
--~ S .~
1\
t.o
VO-AM
70
"0
(5
-I-~
I
ro
:J:
l-
T.H.D·-FM -I-fA
6
'c
~
VCC=4.0 V
::E 60
ex::
u
0
2
LJ
-80
E
I
~
E
1/
-70
t
i5
',AM)_400 Hz MOO_30"
I
-30
vi
E
::i
I
'tl$t-10.7 MHz
I
-20
OUTPUT VOLTAGE, TOTAL HARMONIC DISTORTION,
SIGNAL TO NO~SE RATIO, vs. INPUT VOLTAGE
ex::
b
9
3 OH-t--Mt......-f""'''''t-+-I-t-+--+'''+-II-t'-I-t'-t-+-I-t-i 2
I
I'
I
I
0
o
2
3
4
5 6
7
8
9 10
Vee - Supply Voltage - V
DETECTOR OUTPUT VOLTAGE, TOTAL HARMONIC DISTORTION
vs. MODULATION FREQUENCY
II.
CD
I
"5 -40
.e:J
0
1\
3
J
-SO
T.H.D·-AM
j I IT!"
I -60
::!: -70
ex::
6 -80
>
VCC=4.0 V
ftest=1.0 MHz
MOD=30 %
4
Vj=74 dBJlV
V9-AM -
"0
"-l. I
20
T
SO 100 200 SOO lk
i'
I
2
I
c
0-ea
co .B
;§ Vl
I
Q
::!: .!:!
c
~ a
... v
2k
~
c:i
::C
5k 10k 20k
0
.-:
§
ro
:J:
fmod - Modulation Frequency - Hz
285
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1197C
FM MULTIPLEX STEREO DEMODULATOR
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTION
The ~PC1197C is a silicon monolithic integrated circuit for FM multiplex demodulator designed for stereo cassette tape
recorder with radio receiver, car stereo and car radio operated at a low supply voltage.
The circuit consists of a voltage control oscillator (VCO) for a demodulator and a phase locked loop (PLL), phase comparators, low pass filters (LPF), frequency dividers and a DC amplifier. It also contains accessory circuits such as separation
adjustor stereo-monaural switcher, VCO stopper and stereo-monaural switcher in depressed supply voltage.
FEATURES
• No coil is needed due to PLL (Phase Locked Loop) system. The absence of coil, essential component in conventional
systems, enable to reduce the number of external components and save manpower for adjustments.
• The circuit provides stability in a wide range of power supply voltage. (Vee = 4 to 16 V)
• A stereo/monaural switch can be controlled by a DC voltage obtained from I F signal by smoothing. It is also designed
to provide very small shock noise generated when the stereo/monaural is switched.
• vca, an unnecessary function for AM reception, can be stopped simply by connecting the control terminal to the
power supply. (Vee - 3.0 V)
• When the power supply voltage is depressed the mode is forced to shift to monaural. (Forced monaural reception;
Vee - 3:5 V)
• Separation adjustment terminal enables to adjust optimum channel separation.
BLOCK DIAGRAM
19 kHz
YCO
L.P.F.
L.P.F.
ST.lMONO.
SW & YCO Stop
L.P.F.
9
Composite
Preamplifier
Signal Input Output
286
Left
Right Channel Lamp
Channel Output
Driver
Output
GND
Separation
Adjuster
j.lPC1197C
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
16
V
350*
mW
Power Supply Voltage
VCC
Allowable Power Dissipation
PD
Operational Temperature
T opt
-20 to
+ 75
°c
Storage Temperature
T stg
-40 to
+ 125
°c
*Ta = 75°C
RECOMMENDED OPERATION CONDITIONS (Ta = 25°C)
Supply Voltage Range
VCC
4 to 16 V
Operating Voltage
VCC
9V
ELECTRICAL CHARACTERISTICS (Ta
CHARACTERISTIC
= 25°C,
VCC
SYMBOL
Circuit Current
ICC
Separation
Sep.
= 9 V,
MIN.
vi
= 200 mV,
TYP.
L = 45 %, R = 45 %, Pilot = 10 %)
MAX.
UNIT
CONDITION
12
mA
Without signal
30
45
dB
f = 100 Hz
40
55
dB
f = 1 kHz
30
45
dB
f=10kHz
Monaural Total Harmonic Distortion
T.H.D.
0.3
0.5
%
monaural Vin = 200 mV
Stereo Total Harmonic Distortion
T.H.D.
0.2
0.5
%
stereo pilot = 20 mV
Output Voltage
Vo
Channel Balance
Ch. B.
Lamp-on Level
LAMP-ON
Lamp Hysteresis
Hys. (LAMP)
Capture Range
C.R.
Rej (19)
Rej (38)
Ultrasonic Frequency Rejection
SCA Rejection ratio
Rej (SCA)
mV
Vi = 200 mV
dB
monaural Vi
8
mV
pilot signal
4
dB
pilot signal
±4
%
pilot = 20 mV
35
dB
pilot = 20 mV
45
dB
pilot = 20 mV
170
-2
0
70
2
dB
pilot
composite
-
SCA
composite
=
200 mV
1
10'
1
10'
Signal to Noise Ratio
SIN
86
dB
Vi = 200 mV
Allowed Maximum Input Level
Vi (MAX)
500
mV
T.H.D.
Forced-monaural Level
V (MONO)
0.7
V
#9 terminal
VCO-stop level
V (STOP)
3.0
V
#9 terminal
Stereo-monaural
Switch-over Voltage
VCC (MONO)
3.5
V
Supply Voltage
~
2%
287
j.lPC1197C
TEST CI RCUIT
19kHz
Monitor
sw
FOrced.monaUral)
( and yeo·stop
O.047}lF
PACKAGE DIMENSIONS
in millimeters (inches)
Typical values are shown
unless specified otherwise.
X
N
==
LO
LO
LO
en
I
40
en
r...
r'\.
\
,/
ci
...---
i-'
30
20
10
o
10
30
50
100
300 500
1 k
3 k 5 k
10 k
30 k 50 k 100 k
f - Frequency - Hz
SEPARATION vs. PILOT INPUT LEVEL
(Stereo)
VCO FREE RUNNING FREQUENCY vs.
SUPPLY VOLTAGE
VCC=9V
1=1 kHz
L=45 %. R=45 %
Pilol=10 %
Vin=O
N
J:
.;,t:
I
>c:
+300
80
u
:J
rr
~
u..
DO
+200
70
+100
\
c:
'c
c:
~
(J
-200
u..
0
>
I
0
(J
60
I
\
0
(19 kHz)
-100
:J
0::
CD
-0
c
~g.
................
50
en
'", .....
40
I
g.
" i'-...
30
en
-300
...............
20
.?
10
o
4
6
8
10
12
14
16
18
o
20
10
20
Vee - Supply Voltage - V
30
V
10
0
~
C
u
'c0
/
5
/
3
/
<0
1.0
~
0
I-
/
0,5
/
0 0.3
I
t-=
,/
I
V
/
E
J:
0.1
60
70
80
90
100
/
I
c:
10
:e
~
C
u
'c
0
5
3
E
<0
J:
~
0
1.0
I
0.5
l-
0
I
t-=
\
\
0.3
/
o
1=1 kHz
V'in=200 mV
~
0
c:
t:
50
30
VCC=9 V
1=1 kHz
I
40
TOTAL HARMONIC DISTORTION vs.
SUPPLY VOLTAGE (Monaural)
TOTAL HARMONIC DISTORTION vs.
SIGNAL INPUT LEVEL (Monaural)
~
30
Vin(pilot)- Pilot Input Level- mV
0.1
100 200 300 400 500 600 700 800 900 1000
Vin - Input Signal Level- mV
o
2
4
6
8
10
12
14
16
18
20
Vee - Supply Voltage - V
293
,uPC1197C
TOTAL HARMONIC DISTORTION vs.
FREQUENCY
(Monaural)
~
I
VCC=9 V
Yin 200 mV
10
t:
0
:e
~
Q
3
u
'c
0
§
1.0
ra
:J:
'iii
(5 0.5
I
f-
V
I 0.3
0
I
....,:
0.1
10
30
50
100
300 500
1k
3 k 5 k
30 k 50 k 100 k
10 k
f - Frequency - Hz
TOTAL HARMONIC DISTORTION vs.
FREQUENCY
(Stereo)
VCC=9 V
~
10 Vin(L+R)=200 mV
I
,,
L=45 %. R=45 %
5 Pilot=10 %
t:
0
~
.B
V>
I
3
Q
I
.g
0
§
L
1.0
ra
I
:J:
'iii 0.5
(5
f-
I 0.3
0
I
~
r--
~
....,:
0.1
10
30
50
300 500
100
1k
3k
5k
30 k 50 k
10k
100 k
f - Frequency - Hz
TOTAL HARMONIC DISTORTION vs.
PILOT INPUT LEVEL
(Stereo)
MAXIMUM INPUT LEVEL vs.
SUPPLY VOLTAGE
(Monaural)
30
1.0
~ 10
VCC=9 V
f=l kHz
L=45 %. R=45 %
Pilot 10 %
>
L
E
I
I
0
1::
.2
V>
Q
L
3
u
'c
I
0
E
t:
ra
:J:
1.0
'iii
I
C1>
...J
~
'5
1I
0.5
L
0 0.3
I
....,:
-..!II
0.1
0.6
::E:
0.4
'x
ra
/
o
.-""
20
V
x
L
«
::E:
/
C
0.2
~-
40
60
80
V in(pilot) - Pilot Input Level- mV
294
c.
E
E
=>
E
I
(5
f-
>
L
5
0.8
Q)
L
t:
f=l kHz
T.H.D.=2 %
100
o
2
4
6
8
10
12
14
Vee - Supply Voltage - V
16
18
20
tLPC1197C
POWER DISSIPATION AND SATURATION
VOLTAGE OF LAMP DRIVER vs.
LAMP CURRENT
CAPTURE RANGE
80
;: 200
E
I
VCC=9 V
>
E
I
70
a;
>
60
50
0::
40
::J
0.
\
.::
30
E
3-
r\
20
\
10
-"," , ,
~
0
18.00
17.00
tvco -
U
...
~ 100
o
c..
a.
50
E
(II
I
c..
20.00
o
21.00
VCC=9 V
External parts
excluded
1.0
u
c
0-
~
o
I..&...
t-- r--
-r--
~
.~ (19 kHz )
c
c
:::>
-0.5
(II
2.5
2.0
I--
en
~
V
80
1.5
a.
E
OJ
[/7
40
~
i5
~ ~ ~~
60
§
:;:;
1.0
-t
0.5
~
U:J
o
u
>
100
VCO FREE RUNNING FREQUENCY vs.
AMBIENT TEMPERATURE
VCC=9 V
External
parts
included
N
I
I
>.
1.0
Cll
:::>
0-
Cll
t-- t--
0::
e
./
bY
/
~
~
IL - Lamp Circuit - mA
u
c
t--
;.--
20
VCO Free Running Frequency - Hz
>.
0.5
~
...V
"C
N
::J
---
...J
I
Cll
-
>
i5
VCO FREE RUNNING FREQUENCY vs.
AMBIENT TEMPERATURE
I
;/
Cll
/
V
19.00
3.0
~
c
o
V
.!:
>
E 150
I
I
\
\
Cll
.!2
:;:;
I
>
~
DO
3.5
c
o
,
...J
4.0
-1.0
U::
0.5
DO
c
.§
0
&
(19 kHz )
-0.5
I..&...
o
o
u
>
I
o
u
-1.0
u
>
I
2?
o
-25
25
75
50
o
u
2?
Ta - Ambient Temperature -'C
-25
o
25
50
75
Ta - Ambient Temperature -'C
CIRCUIT CURRENT vs.
AMBIENT TEMPERATURE
INPUT PILOT LEVEL (LAMP ON-OFF) vs.
AMBIENT TEMPERATURE
20
10
.",...
9
8
>
E
I
a;
>
7
Cll
6
.!2
5
,/
LAMP ON
-"V
0.
-=
E
:s
.!:
4
16
<:
E
V
----
V V
~
---
V
"E 12
~
:::>
V~
LAMP OFF- I - -
2
>
o
25
U
·5
~
50
Ta - Ambient Temperature -'C
10
(3
8
I
u
6
9
VCC=9V
External
parts
included
-25
14
I
3
o
~
V
...J
0::
"5
V
VCC=9 V
quiscent
18
4
2
75
o
-25
o
25
50
75
Ta - Ambient Temperature -'C
295
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1158H2
LOW NOISE PREAMPLIFIER WITH AUTOMATIC LEVEL CONTROL
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The ,uPC1158H2 is a silicon monolithic integrated circuit designed for high gain, low noise preamplifier
with Automatic Level Control (ALC).
As an advanced production process is used, the device has an excellent feature of very low pulsive
noise characteristics.
It is ideally suitable for use as a recording and playing amplifier in a cassette tape recorder.
FEATURES
PACKAGE DIMENSIONS
• Low noise, especially low pulsive noise.
in millimeters (inches)
• Wide supply voltage range
(Vee =2.2 -15V).
Cl
(CO.04)"
.High gain: A vo =70dB TYP.
• High output voltage :VOM = 1.0 Vr.m.s.
TYP.
I
I
.~
X"
I
• Low distortion.
23456
19.5MAX.
(O.767MAX)
e.~
....
~"
....
0
d
025
(0.01)
1.0±0.1~-+--
(0.04)
,uPC1158H2
EQUIVALENT CIRCUIT
.-----....---...-__._-...J\,/\,f\r-----,.----o 7
Vee
INPUT
10---+---......
6 ALC INPUT
L-----......--+----+--+--+-......------o 4 GROUND
2
3
N.F.B.
OUTPUT
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Package Dissipation (Ta=75°C)
Vee
PD
Operating Temperature
Topt
-20 to +75
Storage Temperature
Tstg
-40 to +125
Supply Voltage
15.0
270
RECOMMENDED CONDITIONS (Ta=25°C)
Operating Supply Voltage
V
V
5.0
Supply Voltage Range
2.2 to 15.0
ELECTRICAL CHARACTERISTICS (Ta=25°C, Vcc=5V, f= 1kHz, RL= IOkQ)
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
2.2
rnA
Vin=O
Circuit Current
Icc
0.9
1.5
Open Loop Voltage Gain
Avo
64
70
dB
vin=-80dBm
Voltage Gain
Av
33.5
dB
vin=-50dBm
Maximum Output Voltage
VOM
1.0
V
T.H.D.=l%
Input Impedance
ri
100
kQ
f=lkHz
Equivalent Input Noise Voltage
Vnin
1.2
Collector Voltage of ALC Transistor
V5
0.7
0.7
2.0
,Nr.m.s.
V
Ra=2.2kQ, NAB Equalized
15-30kHz BPF+40dB Amp.
Pin 7 to Pin 6: lookQ
Pin 7 to Pin 5: 100Q
297
j1PC1158H2
TEST CIRCUITS
Test Circuit for General Characteristics Given in the Table Below.
1 - - . - - 0 Vee=5V
+
3
1 kQ
3.3,uF
t-'VV'Ir-....-~--....--O
+ -
6800pF
CHARACTERISTIC
I
OUTPUT
RL
10kQ
SYMBOL
Sl
S2
S3
S4
TEST POINT
Circuit Current
Icc
OFF
OFF
NAB
OFF
Pin 7
Open Loop Voltage Gain
Avo
OFF
ON
FLAT
ON
Pin 3
Voltage Gain
Av
OFF
OFF
NAB
ON
Pin 3
Maximum Output Voltage
VOM
OFF
OFF
NAB
ON
Pin 3
Collector Voltage of ALC Transistor
V5
ON
OFF
NAB
ON
Pin 5
Test Circuit for Noise Voltage.
,...-----....---- 60
f--"1 kHz
"-
I
/,
"- ,fL ..
r-l00Hz
'"
L..II
............ r--...
e
--
~
1.4
~
1.2
E
1.0
0.8
0,6
'S
o
::J
,~
co
~
~
->
I
c
.(tj
~
......
1,. ...
...
f"'!'"
80
'"
<1)
-
0
60
>
Q.
0
0
..J
Q.
0.2
0
0
20
0
e
3
5
7
20
10
30
50 70 100
0
RL -Load Resistance-kQ
--
1--
VOM
~
.5:2
I
:;;
->
'"
2
,1-- ~
E
::J
E
'x
co
6
I
<1)
f--,-
.c:l
0
~
~
0
-
Icc
<1)
co
E
'S
40
c
0.4
I
-0
2.0
1.8
co
.c:l 1.6
~
2
100
CD
o
o
-20
o
+20
+40
+60
+80
Ta - Ambient Temperature - ·C
CIRCUIT CURRENT, MAXIMUM
OUTPUT VOLTAGE, OPEN LOOP
VOLTAGE GAIN vs.
SUPPLY VOLTAGE
2.5
100
1-""
CD
>
-0
I
c
80
'(tj
co
60
>
Q.
0
0
..J
40
c
<1)
I
2.0
20
'"
'S
1.5
Q.
'S
~
0
~
0
.~
E
::J 1.0
E
'x
co
6
I 0.5
:;;
~~~
4
E
I
C
~
Q.
0
0
<1)
co
.c:l
'"
.c:l
I
0
<1)
0
5
/'
3
~,;
/. V
J0 /.Icc
V//
2
I
()
.5:2
lV
:f
->
o
,;"
V
VV
VOM
::J
e
L
Ava
"
0
~
o
2
4
6
8
10 12 14 16 18 20
Vee -Supply Voltage - V
299
,uPC1158H2
TYPICAL APPLICATIONS
Pre Amplifier for Cassette Tape Recorder.
Vee
51-5
+
15953
3.3kQ
EH
* Rec./Play Switch S1-1 - Sl-7 are shown in play mode.
* Actual D.C. resistance of feed back element between
pin 2 and pin 3 is advisable about 18 kQ or more.
Relay Driver for Radio Control Equipment.
~~~--.-------------------~-----oVcc
33f.lF
+
15953
O.047f.lF
~
300
5.1kQ
33kQ
MONITOR
J,lPC1158H2
TYPICAL PRINTED CIRCUIT BOARD PATTERN
(1)
Pre-Amplifier for Cassette Tape Recorder.
PRINTED CIRCUIT LAYOUT & COMPONENT LAYOUT (BOTTOM VIEW)
FLAT
NAB
o
o
0
a
o
IN
o
o
<.0
,uPCl158H2
lOkQ
o
o
o
o
a
Vee
ALC
OUT
45
ALC OUT
301
BIPOLAR ANALOG INTEGRATED CIRCUIT
j1PC1204C
RECORDING AND PLAY' BACK AMPLIFIER
DESCRIPTION
The J,LPC1204C is a silicon monolithic integrated circuit designed for cassette tape recorders. The pPC1204C contains a pre
amplifier, an ALC circuit, a recording amplifier and a meter amplifier. The pPC1204C is encapsulated in an 16 pins dual in-line
plastic package.
PACKAGE DIMENSIONS
FEATURES
in millimeters (inches)
• Wide operating range. Vcc = 8 - 12 - 20V
19.4MAX.
(0.763MAX.)
• Low noise, especially low pulsive noise.
• The pre amplifier and the recording amplifier have high
R1
(RO.039)
gain and low distortion characteristics.
---t-
L!"l
.
<.D
• Wide ALC range.
• Integrated functions necessary to cassette sound re-
~
L!"l
Typical value unless
otherwise noted.
N
6
producing.
(a pre amplifier, a recording amplifier, an ALC circuit and
a meter amplifier)
2.54
(0.1)
0-15'
0.5±0.1
(0.019)
EQUIVALENT CIRCUIT
11
16
12
08
09
14
302
15
235
6
7
8
4
9
10
,uPC1204C
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Supply Voltage
V
20
Vcc
(Ta = 75°C)
mV
Operating Temperature
T opt
-20
to +75
°c
StNage Temperature
T stg
-40
to +125
°c
Pd
Package Dissipation
350
RECOMMENDED OPERATING CONDITION (Ta=25°C)
CHARACTERISTIC
Supply Voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
8
12
20
V
ELECTRICAL CHARACTERISTICS (Ta=25°C, VcC=12V)
CHARACTERISTIC
Circuit Current
(PRE AMPLIFIER) 52dB
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
ICC
2.4
4.0
6.0
mA
No Signal
dB
Vo= 0.3 Vr.m.s.
f=l kHz
Voltage Gain
Avol
78
Maximum Output Voltage
Voml
Total Harmonic Distortion
T.H.D.
0.3
0.6
%
Equivalent Input Noise Voltage
Vnin
1.3
2.0
J,LVr.m.s.
1.6
85
2.5
Vr.m.s.
T.H.D.=l%
Vo= 0.3 Vr.m.s.
30 kHz B.P.S., RG=2.2 kn.
(RECORDING AMPLIFIER) f=l kHz
Voltage Gain
Avo2
Maximum Output Voltage
Vom2
Total Harmonic Distortion
T.H.D.
47
1.9
dB
54
2.7
0.03
Vr.m.s.
0.1
Vo= 0.3 Vr.m.s.
T.H.D.=l%
%
Vo= 0.3 Vr.m.s.
dB
T.H.D.=3%
(ALC)
ALC Range
ALC
56
303
JLPC1204C
TEST CIRCUIT
471lF
220Q
+
~-------r----~A---~~--~-o---+-----oVCC=12V
SW7
+
120kQ
8.2kQ
2.21t.Q
SWI
3
'1
2.2kQ
3. 9k~2
820kQ
75kSl
2
/
B.P.F
50Hz- 30kHz
SWITCH POSITIONS
SYMBOL
304
SW1
SW2
SW3
SW4
SW5
SW6
SW7
ICC
2
3
3
1
2
2
1
Avo
1
1
2
3
2
2
2
Vem
1
2
2
3
2
2
2
T.H.D.
1
2
2
3
2
2
2
Vnin
3
2
1
3
2
2
2
Avo
2
3
3
2
1
2
2
Vom
2
3
3
2
2
2
2
T.H.D.
2
3
3
2
2
2
2
ALC
4
3
3
1
2
1
2
jlPC1204C
TYPICAL APPLICATION
B.2kll
22012
r-----------~--------~~~~~~~--~_oVCC=12V
+
47,11F
120k~2
2.2kll
RECIN
r------+--o--o SW1
60011
2f1J.IlA
I
1BOpF 2. 7k~2
15kO
0.015/IF
(P.B POSITION)
REC & P.B
HEAD
3.3k~1
Bias
OSC
CHARACTERISTICS (Ta=2SoC)
TOTAL HARMONIC DISTORTION
OUTPUT VOLTAGE
(PRE AMP. :P/B·POSITION)
TOTAL HARMONIC DISTORTION
vs. OUTPUT VOLTAGE
(PRE AMP. :REC.·POSITION)
VS.
5
~
I
3
Vcc= 12V
RL =22kQ
RG =600Q
I
~
r
I
c:
:e
1il
u
'c0
E
::r::
'"
,
I-~
l-
u
f= 10kHz
t.;~
V
"- ~~
I
0.1
0
::C 0.07
~
0.05
0.030.050.07 0.1
E
I
,,~
1
o
~
"\ ~
I
"-e
'c
/
0.3
ro
'0
o
is
100Hz
0.7
0.5
c:
o
1il
0
is
:::c
'"
L 1
/
I
o
is
I
Vo- Output Voltage- Vr.m.s.
0.5
""
"
0.3
5 7 10
~
f= 10kHz
~
."
l-
f= 1kHz
0.3 0.50.7 1
0.7
ro
'0
/
j
5 Vcc= 12V
3 RKL=22kQ
RG = 2.2kQ
//
'" V
f= 100Hz
f= 1kHz I -
0.1
0.07
0.05
0.030.050.070.1
0.3
0.50.7 1
5 7 10
Vo- Output Voltage- Vr.m.s.
305
ttPC1204C
VOLTAGE GAIN vs. FREQUENCY (PRE AMP.)
TOTAL HARMONIC DISTORTION
vs. OUTPUT VOLTAGE (REC. AMP.)
Vcc= 12V
vo= O. 3Vr.m.s.
VCC= 12V
RL = 15kQ
RG =600Q
i
10
CD
""0
100
7
I
c
'ro
80
C!1
r-
V
60
I
0
»
««
-I'
c
0
't
~r--.
-1= ~
--
--I-
- r-
-
0
30
10
0
u
'c
3k
300 500 700 Ik
50 70 100
I
Vi
I-....;;":::~
20
o
3
I
.... 1---
I- JP;B MODE)
52dB FLAT AMP.
(REC MODE)
40
~
1-- t--- .........
NAB AM
~-:::~-
Q)
bO
2
"0
>
5
AVO
5k 7k 10k
0
~
::r:
0.7
C"IJ
0.5
""iij
0.3
"0
30k 50k 70k lOOk
/
'I
/
"
l-
I
c::i
:i
t-=
f- F requency- Hz
,
0.07
VOLTAGE GAIN vs. FREQUENCY (REC.AMP.)
60
I
c
..... ~'"
V
""0
'"
....... r--..
30
"0
AV(NF)
io-"" V"
>
I
20
0
/"
10
'- ........ ~
'\.
\
1\
"
~
30
o
3k
5k 7k 10k
vi
0
...:
0
I
'c
E
30k 50k 70k lOOk
>
f - F requency- Hz
(])
bO
2
"0
>
CIRCUIT CURRENT, MAXIMUM OUTPUT
VOLTAGE vs. SUPPLY VOLTAGE
5
10
>
I 4
Q)
« 8
vi
E
0
I
bO
2
>
0
>
E
I
3
:J
.&
:J
o
~
~:J
---
6
U
~~
/~
, ~ ..... " ,.......
ICC
~
2
E
·s 4
E
U
I
{~ ~
u 2 if·
!::)
:J
.~
C"IJ
~
I
E
a
>
0
~
07
vom(REC)
8
9
",
-~
..... ~
",
-
~
i'.
u
..-1""'"
0
I
0.7
0.5
~
C"IJ
::r:
I
c::i
:i
t-=
" ,~
~
Vee 12V
RL 2.2kQ
RG= 1kHz
T.H.D.
10
7
5
Vi
"S ""iij
c. "0
"S I-
...:
"0
3
111111
I
0
300 500 700 lk
0.3 0.50.7 1
100
70
50
:p
50 70 100
I
I
ALC CHARACTERISTICS
(REC. POSITION)
c
30
0.070.1
...... f= 100Hz
Yo-Output Voltage- Vr.m.s.
"
»
««
10
" r-r-
-- .... ... ~
Q)
bO
.s
If
//
/~
~~
~~
C!1
1kHz
~
0.01
./
40
'iij
f
VCC= 12V
vo= O. 3Vr.m.s.
-
AVO
50
CD
0,05
0.03
70
/,
f= 10kHz /~
0.1
-Vout
0.3
O. I
0.07
0.05
0.03
0.01
lOp
~
/
30" 50p lOOp 300" 500p 1m
In:m
10m
30m 50m 100m
7m
70"
70m
Vi-Input Voltage- Vr.m.s.
vom(PRE)
VOLTAGE GAIN
vs. SUPPLY VOL TAG
90
10 11 12 13 14 15 16 17 18 19 20 21
VcC-Supply Voltage-V
co
""0
80
..
~
~
I I I I.. I,
AV (Pre Amplifle r) -
-r----
I
.~ 70
C!1
Q)
bO
~60
>
I
>
AV(REC)
« 50 1-- r40
7
8
9
10 11 12 13 14 If 16 17 18 19 20 21
Vee-Supply Voltage-V
306
-
BIPOLAR ANALOG INTEGRATED CIRCUIT
j.lPC1217G
RECORDING/PLAY'BACK PREAMPLIFIER SYSTEM
DESCRIPTION
J1PC1217G is a monolithic integrated circuit designed for a tape recorder works at low voltage and
encapsulated In a smaller package (20-pin MINI FLAT).
J1PC1217G has a microphone ampl ifier, a play'back ampl ifier, a recording amplifier, a ALC circuit, a LED
driver and recording/play'back changeover switch so that is suitable a small tape recorder.
FEATURES
•
A recording/play'back changeover switch is built in so that easily design switch circuit.
•
Wide operating voltage range. Vee = 1.8 to 3 to 6 V
•
Excellent low voltage characteristic.
•
New smaller package (20-pin MINI FLAT) so that a small tape recorder is easily designed.
•
Only two ICs (J1PC1217G, 1218H; Po AMP.) are necessary for a tape recorder.
BLOCK DIAGRAM
47 .u
IO.u
-47
t
i-
P +
-
¥fO
+
VCC=3 V
P
220 k
20
19
18
17
16
15
14
307
jlPC121"7G
INTERNAL FUNCTION
MIC. AMP.
a AMPLIFIER
PIS
AMP.
REC. AMP.
ALC
a ADDITIONAL FUNCTION - LED DRIVER
RIP SWITCH
PACKAGE DIMENSIONS (Unit: mm)
°
1
045 MAX
o04
±ooon
20 19 18 17 1~ 1~ 14 13 12 11
925 MAX
~
\~
1,-4
fr
t
10.1 MIN.
7.25 MAX.
\~
'-
1.5 MIN. 10.65 MAX.
CONNECTION DIAGRAM
PIN No.
308
CONNECTION
PIN No.
CONNECTION
1
Input (MIC.)
11
GND
2
NFS (MIC')
12
RIP Switch Input
3
Input (PIS)
13
LED Driver Output
4
NFS (PIS)
14
VCC
5
Output (MIC., PIS)
15
AlC Time Constant
6
ALC Output
16
Filter
7
Input (REC.)
17
Filter
8
NFS(REC')
18
Recording Clamp
9
Output (R EC.)
19
Filter & Bias
10
ALC Input
20
GND
,uPC1217G
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Supply Voltage
10
V
500
mW
Vcc
Package Dissipation
PD
Operating Temperature
T opt
-20 to+75
°c
Storage Temperature
T stg
-40tO+125
°c
RECOMMENDED OPERATING CONDITION (Ta=25°C)
CHARACTERISTIC
SYMBOL
Supply Voltage
VCC
ELECTRICAL CHARACTERISTICS (Vcc=3 V, f= 1 kHz, RL =
CHARACTERISTIC
Circuit Current
P
I
B
M
I
C
R
E
C
SYMBOL
MIN.
10
kn, Ta=25 °C)
TYP.
MAX.
.UNIT
(10.5)
mA
ICC(P/B)
6.5
Vo Itage Gai n
Avo(P/B)
72
Output Maximum Voltage
VOM(P/B)
Total Harmonic Distortion
T.H.D·(P/B)
Input Noise Level
(0.5)
(0.7)
%
(1.6)
!JVr.m.s.
1.0
Rin(P/B)
36
Circu it Current
ICC(REC)
8.5
Voltage Gain
Avo(MIC)
52
(0.4)
Vr.m.s.
0.8
Vnin(P/B)
(13.5)
VOM(MIC)
0.3
(0.7)
%
Input Noise Level
Vnin(MIC)
1.0
(1.6)
!JVr.m.s.
Input Impedance
Rin(MIC)
36
kn
Voltage Gain
Avo(REC)
70
dB
Output Maximum Voltage
VOM(REC)
T.H.D·(REC)
(45)
ALC Range
Ripple Rejection
LED Current
ILED
Vr.m.s.
0.7
Vr.m.s.
0.9
(6)
T.H.D.=1 %
VO=0.3 Vr.m.s.
RG=2.2 kn
*
T.H.D.=1 %
0.2
(0.7)
%
VO=0.3 Vr.m.s.
2.6
(9)
dB
Vin=-70 - -40 dBm
dB
T.H.D.~3%
dB
RG=2.2 kn, f=100 Hz
64
70
R.R.R.
*
dB
. T.H.D·(MIC)
ALC Effect
RG =2.2 kn
mA
Output Maximum Voltage
(0.5)
T.H.D.=1 %
VO=0.3 Vr.m.s.
kn
Total Harmonic Distortion
Total Harmonic Distortion
No Signal
dB
0.065
Input Impedance
CONDITION
9
(12)
mA
* f= 10Hz - 10kHz B.P. F. (6 dB/oct)
309
,uPC1217G
TEST CIRCUIT
TEST CIRCUIT 1
CD
Voltage Gain (PIS AMP.)
(2) Frequency Characteristics (PIS AMP.)
TEST CIRCUIT 2
CD
Voltage Gain (MIC. AMP.)
@ Frequency Characteristics (MIC. AMP.)
TEST CI RCUIT 3
CD
(6) Frequency Characteristics (REC. AMP.)
Voltage Gain (REC. AMP.)
47 k Q
47 kQ 18 kQ
TEST CI RCUIT 4
PIS AMP. Noise
RG
2.2 kQ
Amp
f= 10 Hz-IO kHz
B.P.F.
(12dB/oct)
310
1
3300 PF
18 k Q
j1PC1217G
TEST CI RCU IT 5
MIC. AMP. Noise
20 kQ
f=10 Hz-10kHz
B.P.F.
(12dB/oct)
TEST CIRCUIT 6
ALC Characteristics
47kQ
18kQ
10
311
,uPC1217G
TYPICAL CHARACTERISTICS (Ta=25 °C)
CIRCUIT CURRENT. OUTPUT MAXIMUM
VOLTAGE vs. SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION vs.
OUTPUT VOLTAGE (MIC. AMP.)
18~----'-----.-----r-----r-----r---~r----'
I
161------~--_4-----+-----r----~----T_--__i
t=lO kHz",
3
14
,,"
, ,,'
"
E
::;
12
ex::
E
I
I
Q)
00
ro
~ 0.3
o
:e
E
::s
E
'c
o
::E
::c
':5
~
8
'x
ro
I
u
!d 6
::s
.e::s
o
I
E
,
4
o
>
L
~
C 10 ~----+-----+-----t---~~~~~~~r.~__1 2 ~
~
~
::s
U
>-
U
V
0.5
~
Ci
<.J
E
ro
1
1/1/
J J
t.=l
k~l/
VII
V
/ V
V
~ i'"
L
(5
I
Vee=3 V
f=100 Hz
0.1
ro
~
L
If
L
L
V
l
I
L
0.7
.,;
/
L
0.07
c:l
I 0.05
~
0.03
2
0
4
3
2
5
6
Vee - Supply Voltage - V
0.0 1
0.1
TOTAL HARMONIC DISTORTION vs.
OUTPUT VOLTAGE (MIC. AMP.)
0.3
0.5 0.7
Vo - Output Voltage - Vr.m.s.
3
TOTAL HARMONIC DISTORTION vs.
OUTPUT VOLTAGE (REC. AMP.)
IL
I
Vee=3 V
Vee=3 V
0.7
0.7
0.5
~
0.5
I
c:
',e
0.3
:e
c:
~
i5
~
<.J
'c
o
Ci
E
ro
::c
roO
;§
O. 1
I 0.07
c:i
I
~
0.3
0.0 5
"
<.J
t=100 Hz,
".
~
'c
o·
f'...bl
E
ro
"
"
~~
~
::c
~
2
~
~.-. f-"'"
~~
~
I 0.0 7
t't=10 kHz
r"-
0.03
~
t- ~
~
"
~
1 kHz
) . I't-=
f=100 H z _
c:l
I
'" '" '"
........
i"'"
~
0.1
o
II
'J
f=lO kHz,
~
0.05
~t=l kHz
0.03
0.0 1
0.1
0.3
0.5
0.7
Vo - Output Voltage - Vr.m.s.
3
0.0 1
0.1
0.3
0.5
0.7
Vo - Output Voltage - Vr.m.S.
312
3
,uPC1217G
VOLTAGE GAIN vs. FREQUENCY (MIC. AMP.)
70
I
VCC=3 V
60
AVO
III
~
"0
I
c
Oro
50
-
........
(!)
~
OJ
DO
2
"0
>
..... ~
40
~""
I
«>
6
30
«>
20
.".
~
,,-
10
10
--
30
-
AVN
r-- ....... .........
50 70 100
300
3 k
500 700 1 k
5 k 7 k 10 k
30 k 50 k 70 k 100 k
f - Frequency - Hz
VOLTAGE GAIN vs. FREQUENCY (P/B AMP.)
80
V~~=3IV\
---
70 " ,
"....--
~
AVO
-
j"""oo.
~
..........
III
"0
I
Oro
~
60
"""
c
(!)
OJ
DO
2
50
"0
>
~
..... ~
I
«>
40
~
6
«>
,/
30
/'
~
i'
~Ioo
AVN
~t--....
r--""
~
t-..."" ~~
............
/'
20
10
30
50
70 100
300
~!'oo
500 700 1 k
--3 k
5 k 7 k 10 k
30 k 50 k 70 k 100 k
f - Frequency - Hz
VOLTAGE GAIN vs. FREQUENCY (REC. AMP.)
80
70
III
"0
t~J3IJ
~
----
AVO-
.......... .......
60
I
Oro
c
(!)
OJ
2
>
"0
«>
40
......., ,.,..~
c5
«>
30
..... ""
""""
'"-
~
50
DO
I
~
./
-
AVN
.....
" """"
....... ......
.........""
/
'/
20
10
30
50 70 100
300
500 700 1 k
3 k
5 k 7 k 10 k
30 k
50 k 70 k 100 k
f - Frequency - Hz
313
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1177H
2-CHANNEL AUDIO POWER AMPLIFIER
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The pPC1177H is a silicon monolithic integrated circuit in a 12-pin single in-line plastic package, designed for audio power
amplifier applications in cassette tape recorders or radio recievers which operate at a 6 volt power supply.
The pPC1177H has two audio power amplification circuits and each of the two provides 1 W output power at 6 V/4 n. In
addition, the pPC1177H provides 3.5 W output power at 6 V/4 n, when it is operated as a BTL amplifier.
FEATURES
•
•
•
•
•
•
•
•
•
High output power. BTL
3.5 W (TYP.) at 6 V/4 n, T.H.D.=10 %
DUAL
1 W (TYP.) at 6 V/4 n, T.H.D.=10 %
Wide operating voltage range. V cc=3.5 to 10 V
No shock noise at power supply switch-over.
Soft clipping wave form.
High ripple rejection ratio. R.R.R.=55 dB (TYP.)
DC-short (pin 1, pin 12 to pin 10) protection circuit.
Excellent low voltage characteristic. LlAvo=3 dB (TYP.)
LlAvo=Avo (6 V)-Avo (3.5 V)
Flat and pierced fin so that an external heat sink can easily be attached.
A 12-pin single plastic package so that can easily be mounted on PCB.
BLOCK DIAG RAM
(External compornents; DUAL amplifier)
r----.--o vee
+
470 J1F
100 Q
s.p
s.P
2.2 Q
20 k.Q
20 k.Q
314
j1PC1177H
PACKAGE DIMENSIONS (Unit: mm)
Typical value unless otherwise noted
30 MAX.
4.0
28
¢ 3.6-2
I
15
I
\
~
~
(
1
.-l
"I
/
~
yu
I
-
I
x
0
-
-
0
R 3.5-2
.1
«
~
0
~
o::i
I
2
3
4
5
6
7
8
9
10
11
L ~
L ~
L ~
LII~
l.J
I r-1
l r1
l ,J
L ~
t
12
L
1
it
LO
I
0
I
+1
LO
I
a
>
40
-
Av
,
l,....o- --~
i'.
"'
r--
30 f - - :VCC=6 V
~
V
Ix
0
0...
I-
r-:
~
CD
I
'c
~
....-
40
0
I
>
«
""--i""---
,"
-
30
6
>
«
T.H.D.(P o =0.25 W)
20
10
0.1
o
10
3
vee-Supply Voltage-V
0.05
10
vee-Supply Voltage-V
VOLTAGE GAIN vs. FREQENCY
70
Avo
60
V'
- r-....
CD
"0
I
50
Au
c
'iii
t!J
Cl)
40
bD
.!3
0
>
I
./
Vee =6 V
RL=4 Q
Po=0.25 W
'""'-
r---
~
..V
"-- ~~
30
«>
6
«> 20
10
50
100
200 300
1k
2k
500
f-Frequency -Hz
3k
5k
10k
20 k 30 k
50 k
100 k
323
,uPC1177H
TOTAL HARMONIC DISTORTION vs. OUTPUT POWER
20
VCC=6 V
RL=4 Q
10
~
I
c:
0
t0
II
tl
CS
u
f=10 kHz ..",
'2
0
E
:x:
'"
---
]
,..."
I
~
0
...,
l-
I 0.5
c:i
f=.l!!--
....: 0.3
f=l00 Hz ____ ~
::x::
./
I
",
./
0.2
0.01
0.02 0.03 0.05
0.1
0.2 0.3 0.5
Po-Output Power-W
TOTAL HARMONIC DISTORTION vs. FREQENCY
VCC=6 V
RL=4 Q
Po =0.25W
~-
'/'
V
L
/
....
0.5
0.3
./
.............
~
...............
./
0.2
]
o
l-
0.1
I
c:i
::x::
....:
0.05
0.03
20
30
50
1CX'
200 300
500
2k 3k
1k
f-Frequency -Hz
5k
10k
20 k 30k
50k
100 k
CROSS TALK vs. FREQENCY
70
VCC=6 V
RL=4Q
P o=0.25W
RG=O
60
.............
50
(ij
I-
~
Ch1-~~
I
.>t!
........
"'
CD
'0
40
!a
0
U
I
t-=
30
"
Ch2!...ch1
,~
""'"
....
i'-- r--.
e,j
20
10
o
20
324
30
50
100
200 300
500
1k
2 k 3k
f-Frequency-Hz
5k
10 k
20 k 30 k 50 k
,uPC1177H
POWER DISSIPATION vs. OUTPUT POWER
only AMP.l
RL == 4Q
~
1.5r--------t~~----+_------~--------~--------~----~~~------~------~
I
c:
o
.~
.~
o
Q)
~
o
a.
I
"0
a.
0.5r--------1·---------r----~~~--------+_--------r_------_+--------~------~
0.5
2.5
1.5
3.5
Po-Output Power-W
POWER DISSIPATION vs. AMBIENT TEMPERATURE
10r--------.--------.-------~--------~------~~------~
Rthj-c==lO'C/W
AI Panel
Rthj-a==18'C/W lOOXlOOXl Use Silicon grease
Rthj-a==53.5 'C/W Free Air
Unit:mm
.~
I
c:
o
:.;::;
------...-----11
FILTER
r--
::::1
,-:
--,
MUTING
L _____
1
~
..J:
<-I-----<0:\+5
I
SEPP
I
I
I
L__
:~.----u:;:l:6
I
1
_ __ .JI
~-~~------~--~--oTAB
R
:\+8
326
,uPC1212C
ABSOLUTE MAXIMUM RATINGS (Ta
= 25
DC)
Supply Voltage
(No Signal)
11
V
Supply Voltage
(Operating)
9
V
Allowable Power Dissipation
W
2.4
-l(.
Operating Temperature
-20 to
70
DC
Storage T em peratu re
-40 to 150
DC
*" 50 x 50 x 0.035 mm copper heat sink on P.C.B.
RECOMMENDED CONDITIONS (Ta
= 25
DC)
Supply Voltage
V CC = 3.5 to 6 to 9 V
Load Impedance
RL
ELECTRIC CHARACTERISTICS (Ta
= 25
=4 n
DC)
Refer to the test circuits Vcc=6 V, RL =4 n, 50 X 50 X 0.035 mm)
( copper heat sink on P.C.B. unless otherwise specified
CHARACTERISTIC
Quiscent Circuit Current
SYMBOL
MIN.
TYP.
MAX.
UNIT
25
mA
No Signal
dB
Po =0.25 W, f=l kHz
dB
Rf=100 n.
f= 1 kHz
Rf=360 n.
f= 1 kHz
ICC
8
15
Open Loop Voltage Gain
Avo
55
65
Voltage Gain (Closed Loop)
Av
41
45
48
34
Output Power
Po
0.7
Input Sensitibity
2.4
1.3
1.0
0.54
0.41
0.22
W
I nput Sensitivity
mV
mV
Po =50 mW
RL =4 n., f=l kHz
Rf= 100 n. (A v =45 dB)
Rf=360 n. (A v =34 dB)
Vi(rms)
2.5
8.9
T.H.D.=10 %
f=l kHz, Rf=100 n.
VCC=9 V, RL=4 n.
VCC=9 V, RL=8 n.
VCC=6 V, RL =4 n.
VCC=6 V, RL=8 n.
VCC=4 V, RL=4 n.
VCC=4 V, RL=8 n.
Po =l W
RL =4 n., f= 1 kHz
Rf= 100 n. (A v=45 dB)
Rf=360 n. (A v=34 dB)
Vi(rms)
16.4
47.4
CONDITION
Total Harmonic Distortion
T.H.D.
0.4
1.5
Output Noise Voltage
NL
0.2
0.8
Supply Voltage Rejection Ratio
S.V.R.
40
55
dB
I nput Impedance
Ri
10
20
kn.
%
mV r .m .s.
Po =0.25 W
RG=O
RG=O, f r ipple=100 Hz
V ripple=0.3 V r . m .s.
NOTE: In case that only a TYP. value is specified, this specification is for helping to design.
327
pPC1212C
TEST CIRCUIT
Fig. 1 TEST CIRCUIT
---VCC=6 V
* Mylar Capacitor
SWITCH POSITION
~
SW1
SW2
SW3
ITEM
Circuit Current
ICC
2
1
1
Open Loop Voltage Gain
Avo
1
2
2
Voltage Gain
Av
1
1
2
Output Power
Total Harmonic Distortion
Output Noise Voltage
Po
1
1
2
T.H.D.
1
1
2
NL
2
1
2
TYPICAL APPLICATION
Fig.2
SINGLE OPERATION
100 J1F
r---------------+----nVCC=6 V
IN 0----1'1---1
SP. 4
lS(
328
Mylar Capacitor
n
,uPC1212C
Fig.3
BTL OPERATION
VCC=6 V
100 JiF
+
INO---H--~
*
1°.068
pF
f20
Po=3.2 W TYP.
at VCC=6
v,
T.H.D = 10 %
16 kn
*Mylar Capacitor
Fig.4
SINGLE OPERATION WITHOUT BOOTSTRAP
r----------~--~VCC=6V
IN Q - - - B - - - {
SP. 4
n
Po=O.2 WTYP.
at VCC=6 V, T.H.D= 10 %
* Mylar Capacitor
NOTE FOR USE
(1) Capacitor Cg is for preventing the parastic oscillation. A mylar capacitor is recommended for this position.
(2) The ground side of C4 , Cg and the loud speaker should be attached at the place of the copper foil close to the tab of
pPC1212C.
(3) Interference noise rejection in a strong electric field can be achieved by adding a capacitor (about 1 000 pF) between
pin 1 and pin 2.
329
w
w
o
~
APPLICATION INFORMATION
Fig. 5
."
n
LOW COST FM-AM RADIO WITH 1.0 W OUTPUT POWER (VCC=6 V)
-l
N
-l
100
..
N
n
AM
nil
1t I
10k
-w.
2.2 k
.AfW-
.J+ ~I J 6 6 ¢:6 J.
~r
°:'1
VCC=6 V
180
::s.
co
100
Ji
AM
+470
Ji
FM
10k
1
33
3.9 k
Jilt
j?022
7fT
Ji
I
SP. 4 0
ANT
75Q~i~P
*Mylar Capacitor
0-
§:;J;
Q1 :2SC1674
Q2:2SC1674
Q3: 2SC1675
o : lS2207
UNIT
RFC
::t
470 k
L1
0.6 mm¢ UEW 2 & 3/4T 5 mmq, (inside) core bobin ANTENNA 3/4T
L2
0.6 mm¢ UEW 2 & 3/4T 5 mmq, (inside) core bobin VCC 1 & 3/4T
L3
IF TRAP 2.2 pH
l4
0.6 mmq, UEW 1 & 3/4T 5 mmq, (inside) core bobin
T1
10.7 MHz IFT.11T : 2 T C=75 pF
L5
ANTENNA COIL 25A-1195-08 (KOHRIN)
Capacitance
F
T2
AM OSC 26-1791-13 (KOHRIN)
Resistance
n
T3
T4
AM 1FT CFZ-455C (TaKa)
AM DET. 5251 (TaKa)
T5
FM DET. 12747 (TaKa)
ls
PHASE SHIFT COIL 7BA180JH (TaKa)
,uPC1212C
P.C. BOARD PATTERN (COPPER SIDE)
C1212
IN
Vce
r--------------,I
1
1
I
L1
:
'I
I
I
I
,
fI
I
I ______________ J I
L
+ C8
-tt-
OUT
---t Ie;
331
jlPC1212C
TYPICAL CHARACTERISTICS (Ta = 25°C)
Fig.6
Fig.7
OUTPUT POWER vs. SUPPLY VOLTAGE
TOTAL HARMONIC DISTORTION vs. OUTPUT POWER
16
f= 1 kHz
ToHoDo=10 %
Vee=6 V
Av=45 dB
Rf=100 n
f=1 kHz
300
~ 12
/
/
1/ /
I
c:
o
t
.B
III
Co)
°c
~
I /
200
nl;j)
RL=302
==I
Id
....
Q)
~
0
:J
.s-
o
I
n
ci
:i
,....:
I
1.0
II
4
I
o
/
h / ,.~
JV V V
-/
V
V
./
V
4
6
/
n
8
10
008
12
POWER DISSIPATION AND EFFICIENCY vs. OUTPUT POWER
100
2
RL=4 n
f=1 kHz
EF. Vee= 705 V
r.-' V
EF. Vee=6 V ~/
I
>Co)
c:
Q)
LiJ
I
La...
LLI
~
~/
/I ~/V
I # ~~
"2
1/1
-,
~/
'.;-
" ".""
.""
~
".-
~
V
./
/
~
:--
--
--
:::
I
-~~91
c:
.g
.",..
I
r--. ~
ro
Co
1
\j::-:t--.
Q)
~
o
c..
~
Pd. Ve(J= 705 V
I
"0
c..
""
Pd. Vee=6 V
I
o~
o
Pd. Vee=9 V
I
o
2
Po - Output Power - W
332
~
£.
~
.",..
...,..,....
/
/I
/
a I .-.-RL=302
n
./
/
Vee - Supply Voltage - V
50
°u
;;:::
/
/./ r
I
I
n.J
Po - Output Power - W
' RL=16
Fig.8
I
RL=4
~
2
n
I
0.4
/
000
/
L
I
/
I I
I
II
/
n
RL=8
'f
I
RL=8
0
c..
nA
I
I
t-
VI 'd
/ I / '!-
:::J
0
r
8
ro
RL=4
/r
c..
/"t:RL=16
ro
:J:
;/
I
I
i:5
3
o
I
1.2
jlPC1212C
Fig. 9
INPUT SENSITIVITY vs. Rf
Fig. 10 VOLTAGE GAIN (CLOSED LOOP) vs. Rf
60
60
50
VCC=6 V
RL=8 n
f=l kHz
V
/'
40
Po at T.H.D.= 10 % 'J.o
Q)
tlO
co
~
>
:;
30
0.
.E
I
c=
">
/
20
10
vV'
n
"0
>
E
I
VCC=6 V
RL=4
f=1 kHz
CD
V'
V
V
V
L
r---.... r--...
I
-a.
00;;;;;;;
0
.5:!
V
"0
40
-- -
r-.. :--
Q)
I/)
0
~J
r-.:.:.. r-- t-- ......
8
c=
.;0
(!)
Q)
tlO
!!
"0
..,V
>
20
I
>
c:(
Po =50 mW '1\
I
~
I
~
0
300
200
100
o
100
Rf-n
Fig.11 QUISCENT OUTPUT VOLTAGE AT PIN 6
vs. SUPPLY VOLTAGE
Fig. 12 QUIESCENT CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
8
30
c:(
6
E
I
>
~:::I
//
I
Q)
tlO
/~
!!
>
:::I
:::I
4
o
[7
l7
V
20
U
"0
-.e
300
200
Rf-O
t----
·5
Y
~
----
C3
~
Q)
u
I/)
~----
Q)
·5
0'
I
u
~
~
~
----
10
9
V
1//
o
3
o
4
8
12
4
5
6
7
8
9
10
Vee - Supply Voltage - V
Vee - Supply Voltage - V
333
pPC1212C
Fig. 13 OPEN LOOP VOLTAGE GAIN, VOLTAGE GAIN vs. FREQUENCY
70
Vee=6 V
Avo
~
./
60
--........ .........
...
......
RL =4 n
Po =0.25 W
~
r-... ...... r-.,
50
.....
~~
III
"0
Av
I
ro
../
40
(!)
Q)
tID
----~
...
.!::
..............
..........
2
~
30
I
>
«
0
«>
20
10
o
30
50
300
100
3 k
1 k
500
5 k
10k
30k
50k
lOOk
f - Frequency - Hz
Fig. 14 TOTAL HARMONIC DISTORTION vs. FREQUENCY
10
l
l
~
I
I
Vee 6 V
RL =4 n
Po=0.25 W
c:
0
:e
~
is
u
·c
v---
2
0
E
ro
V
I
""iii
"0
ci
:i
t-=
i.--'i--'
7
/
~
I
V
I--"
0.5
r;;1""0 I-
___
-~
0.3
V
........
/'
0.2
30
50
300
100
3 k
1 k
500
10 k
5 k
30 k
50 k
100 k
f - Frequency - Hz
~
I
Fig. 15 THERMAL CHARACTERISTICS
c:
0
50
t
2.0
20
~
Vee=6 V
RL =4
is
u
III 45
"0
§ 1.5
I
c:
·ro
0
~ 40
~
I 1.0
2
"0
>
ci
:i
>
;;
I
«
15
(.)
.::;
10
~
(3
t-=
35
E
C
~=:J
"2
(!)
«
I
ro
I
n
f= 1 kHz
·c
I
(.)
I 0.5
!:?
5
t:;::
T. H. D. (Po = 0.25 W)
0
Cl.
30
~
.e=:J
0
I
0
Cl.
334
O
-.9 20
-10
0
10
20
30
40
Ta - Ambient Temperature _·C
50
60
70
,uPC1212C
Fig. 16 OPEN LOOP VOLTAGE GAIN, VOLTAGE
GAIN vs. SUPPLY VOLTAGE
80
RL =4
Fig. 17 TOTAL HARMONIC DISTORTION
vs. SUPPLY VOLTAGE
10
n
RL 4 n
f= 1 kHz
Po=0.25 W
f= 1 kHz
Vo= -10 dBm
70
en
u
I
c
'ro
'*
Avo
60
"......-
I
~
c
o
0-e
o
L?
ti
is
OJ
tlD
.3
(5
>
.~
o
OJ
E
Av
.... -
ro
L?
~
(5
ro
I
m
;§
40
-.J
c
"- .............
0.5
f""--
I
>
0.
0
0
\
u
'c
50
ci
I
30
0.3
r:
OJ
0.
0
I
>
UEW 2 & 3/4T 5 mmcf> (inside) core bobin VCC • 1 & 3/4T
L3
IF TRAP 2.2 "H
0.6 mmcf> UEW1 & 3/4T 5 ml11 .
u
c:
Cl.l
I
V
V~
~
]
W 50
I
I.J...
UJ
IV
~
~
~V
I
o
':10
~
r-:-:-:--
VCC=lO V
VCC=9 V
~
-~~.I./'
V V~~
- ~~K:
-- ":J;}
I
Q)
2
c
Oro
~
(!)
Q)
:::>
00
2
a
-5
20
o
>
I
4
Q)
«>
~
Q)
°5
V
0'
I
~ 2
300
200
100
/
0/
0'
o
/
I
c
V
V
V
/
v
~/
Rf-O
o
4
8
12
Vee - Supply Voltage - V
Fig. 12 QUIESCENT CIRCUIT CURRENTvs. SUPPLY VOLTAGE
Fig.11 INPUT SENSITIVITY vs. Rf
30
VCC=9 V
60
RL=4 n
1= 1 kHz
50
Po ,.
T.H.D.~lV
/
/
V
V
«
E
I
>
"E
I
Q)
00
40
2
a
>
'5
c..
30
E
I
c
">
20
/
/
V
/
20
~
:::>
V
Q
°5
~
C3
...
"E
Q)
~
Q)
°5
0-
--- ----
~
~
-~
~
~
---
--------
10
I
Q
9
10
0
Po =50 mW
-
I
i
100
200
Rf-O
0.-
.--.."
J
300
o
3
4
6
7
8
9
10
11
Vee -Supply Voltage - V
343
JlPC1213C
Fig. 13 OPEN LOOP VOLTAGE GAIN, VOLTAGE GAIN vs. FREQUENCY
70
60
/'
OJ
-'~
V
...
100-
I
c:
~ ....
~
~
~
40
Q)
tlD
2
g
>
, r-...
Av
'iij
I
~'- .....
50
"0
(!)
VCC=9 V
RL =40
Po =0.25 W
Avo
~
30
/~
/ ~"'"
~
~
~,
~
6
>
~
20
10
o
20
30
300
100
50
500
3 k
1 k
10 k
5 k
30 k 50 k
100 k
30 k
100 k
f - Frequency - Hz
Fig. 14 TOTAL HARMONIC DISTORTION vs. FREQUENCY
10
Vee 9 V
RL =40
Po =0.25 W
*
I
c:
0
t
.8
VI
3
i:5
.......
u
'c
0
E
'"
/
:J:
ii'i
.... ~~
1/
" i"o..
I
::c
~
./
~
ci
l,....'
./
~
0.5
!'~
.-;
""- ........
0.3
0.2
20
30
50
100
-
_...
300
/'
L.,.o~ ... ",
500
1 k
3 k
10 k
5 k
f - Frequency - Hz
Fig. 15 TOTAL HARMONIC DISTORTION vs.
OUTPUT POWER
20
Vec=9 V
RL=4 n
10
/
c:
I
t
5
I/,
*
.8
VI
i:5
u
3
E
2
'c0
I
•
I
0
... y
",
f=lO
kH,;., .....
'"
~
"'
,
T
T
J
.-... ....
:J:
ijl kH,
ii'i
~
I
ci
::c
.-;
~!;i'
~
0.5
0.3
JII'
---
0.2
0.01
_........... ...- -""
"...,.,
f= 100 ,Hz
0.03
0.05
0.1
0.3
Po - Output Power - W
344
V
I-"""'"
0.5
2
3
50 k
JlPC1213C
Fig. 16 THERMAL CHARACTERISTICS
55
2.5
25
V
50
2.0
c:(
:;:
co
'0
I
c: 45
'n;
(:J
CIl
E
I
...
CIl
;t
I
'E 15
1.5
~
«£
2
.e
t'4O
cr
.;f
rE
'0
r---
ICC (No Signal)
---------
u
(} 10
I
1.0
VCC=9 V
Rt.,=4 n
f= 1 kHz
Av (Po =0.25 W)
~---
'3
:l
35
1
:l
C,,)
~
bO
",
I
Po (T. H. D. = 10 %)
./
---
20
I
,,--
r--
C,,)
~
0.5
5
~
:.--
-~
~
---~
T. H(. (po=or W)
30
o
o
-20
-10
o
20
10
30
40
50
60
70
Ta - Ambient Temperature -'C
Fig. 17 OPEN LOOP VOLTAGE GAIN, VOLTAGE
GAIN vs. SUPPLY VOLTAGE
80
Avo
co
'0
I
60
~--
c:
'n;
(:J
2
'0
>
I
>
c:(
6
Av
1---
CIl
bO
40
RL =4 n
f= 1 kHz
Po =0.25 W
20
>
c:(
o
4
6
8
9
10
11
VCC - Supply Voltage - V
Fig. 18 AVAILABLE POWER DISSIPATION vs.
AMBIENT TEMPERATURE
3.0 r---r---"~---r----r----r--""""'T'1r--~-----....,
CD Infinit Heat Sink
(2) 50 x 50 x 0.035 Cu
Q) 35 x 35 x 0.035 Cu
2.5 t------1r----t----+---t---+---+-----:~@ Free Air
UNIT: mm
Q) RthO-a)=63 'C/W
:;:
2.0t--.....,---+~--+~-+--+---t_-~--~--~
...I
CIl
;t
«£
:l
.e
:l
o
1.5 t---I----If---f----=lIood-~-+---+--_+_\_-_+--~
@RthO-a)=I00 'C/W
I
rE
1.0 t---I---i~---t---.::,:-t---+----3io~~--_+-__\__+--~
0.5 t---j---+---t---+---+--~~-~~-__Il~-_I
~2~0--~0~-~20--~4O----~6O---80~--1~OO---1~20---14O~~~16O
Ta - Ambient Temperature -'C
345
,uPC1213C
DESIGN OF HEAT SINK
Keep much margin at the design of heat sink.
The heat sink shown the foiling sentence is nessesary when the pPC1213C is operated under next conditions.
10 V
Conditions : Maximum Operating Voltage
Maximum Ambient Temperature
70°C
4il
Load Impedance
There is the equation between junction temperature and thermal resistance.
Tj=Ta + Rth(j-a) x Pd
(1)
Tj
: Junction Temperature
Ta
: Ambient Temperature
Rth(j-a) : Thermal Resistance (Junction to Ambient)
Pd
: Power Dissipation
According to Fig. 8, Pd(MAX.) = 1.42 W at Vee = 10 V
And absolute maximum rating shows, Tj
< 150 °c
From the equation (1) and those values,
Rth (j-a) < 56.3 °C/W
(2)
According to Fig. 18, copper size on P.C.B. satisfying the inequality (2) is 50 x 50 x 0.035 mm.
346
BIPOLAR ANALOG INTEGRATED CIRCUIT
IlPC1218H
0.25 W AUDIO POWER AMPLIFIER
DESCRIPTION
,uPC1218H is an audio power amplifier in an 8-pin single in-line plastic package.
,uPC1218H is composed a BTL power amplifier and a muting circuit, suitable to a tape recorder works at 3 V power supply.
FEATURES
• High output power.
0.25 W (TYP.) VCC =3 V, RL =8 ohms
• Low voltage operation.
V CC = 1.8 to 3 to 5 V
• A muting circuit is built in. Connect pin 7 to GND.
• No shock noise at power supply switch on and off.
CONNECTION DIAGRAM
PACKAGE DIMENSIONS (Unit: mm)
No.
2.8±0.2
19.5 MAX.
C 1
x
-< x
~
-<
.......
8
c.O
~
Input
2
NFB
3
High Cut
x
4
Output 1
~
00
5
GND
6
Output 2
7
Filter & Muting
8
VCC
-<
LO
0.4
~V
,
~ 20
«
0.2
o
o
5
4
3
2
10
~V
/V
T.H.D.CPo=20 mW)-
Itt'
",V
"
o
o
0
6
/~
PoCT.H.D.= 10 %)
2
"0
f
0
1/
c:
c..
~ 0.6
I"
/
ICC
::2
0.1
co
0
.,V
<.,)
:3-
3:
E 0.8 ~ 40
40
:J
<.,)
I
Av
~
tID
I
50
1.0
E
~::J
~
RL=8 n
f= 1 kHz
50
E
<.,)
60
«
«
I
c:
1.2
RG=O
2
4
3
5
6
vee-Supply Voltage-V
Vee - Supply Voltage - V
VOLTAGE GAIN vs. FREQUENCY
8
80
Vee=3 v
RL=812
Po=50 mW
.....
Avo ~
70
~
60
co
v
"0
I
c:
·ro
./
50
~
tID
40
"
Av
"'"
CIl
2
~
6
,~
5
I-
~
4
I
t...-~
"0
>
7
II
I
0
30
«;;:;
«
20
;;>
V
~
I
c:
.-e0
E
III
0
U
·c
0
§
C\l
3
/
:r:
ro
(5
I-
2
I
c::i
I
T.H.D.
10
.....:
o
10
30 50
100
300500 1 k
0
3 k 5 k 10 k
30 k50 k 100 k
f - Frequecy - Hz
TOTAL HARMONIC DISTORTION vs.
OUTPUT POWE R
~
OUTPUT POWER vs. POWER DISSIPATION
1.2
100
Vee 3V
RL 812
50
RL =8
I
§
1.0
30
I
:;:;
S
3:
I
c:
is
10
:;:;
·Eo
5
·Vi
§
0
0.8
./
C\l
0.
3
f---
f= 10 kHz
C\l
III
7
./
:r:
ro
~=100
(5
I
HZ,l kHz
0 0.6
....CIl
~
0
c.. 0.4
I
I-
0.5
I
0.3
V
V
'/
V
/
"0
~
-
.,...,.
lJ
c..
""
~
".".,
,7
V
--
~2
Vee=5 V
Vee=4 V
Vee=3 V
0.2
.....:
0.1
10
3
5
100
3
5
1000
Po-Output Power-mW
o
0.2
0.4
0.6
0.8
1.0
1.2
Po - Output Power - W
349
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1221C
1 W AF POWER AMPLIFIER WITH PRE AMPLIFIER
AND ALC CIRCUIT
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
The pPC1221C is a silicon monolithic integrated circuit designed for an audio power amplifier application at 6
volts power supply.
The device contains a high gain low noise preamplifier, an automatic level control (ALC) and a high gain low
distortion power amplifier.
The perfect audio circuit of a cassette tape recorder is obtained with the device.
FEATURES
•
All functions of a preamplifier, an ALC circuit and a power amplifier are encapsulated in a 14-pins dual in-line
package with heat sink TAB.
•
Low noise, especially low pulsive noise.
•
Power amplifier stage has high gain, high output power and low distortion characteristics.
•
Preamplifier stage has high gain and low distortion characteristics.
•
Wide ALC range: output voltage change 1.5 dB TYP., ALC range 60 dB TYP.
•
Wide supply operating voltage range: Vcc=3.5 to 9 V.
•
Low spurious radiation when driven to output clipping level.
BLOCK DIAGRAM
PRE
INPUT
ALC
INPUT
R.P.HEAD
BIAS &
FILTER
FILTER
Vee
POWER
OUTPUT
TAB
4
GND
350
PRE
FEEDBACK
PRE
OUTPUT
ALC
OUTPUT
POWER
INPUT
POWER
FEEDBACK
j.lPC1221C
PACKAGE DIMENSIONS AND CONNECTION DIAGRAM (Top View)
in millimeters (inches)
14
9
8
3
4
5
6
19.4 MAX.(0.763 MAX.)
7
13
12
10
11
R1
(R-0.039) "--'>..c-t+- _ _ _ _ __
2
762(0300)
I
24.6 MAX.(0.968 MAX.)
6.5(0.256)
i
I
I
0.5±0.1 MAX.
(0.02 MAX.)
~t-
(0.047)
1
0.3~g:65 - I
( 0.012)
2.5412.54
~
\
\
J
--
\
\
1
I
8.4± 1.5
0.33
4.44(0.175)
I
(0.100) (0.100) 4.96
f---co.195)
Pin No.
GND
Pin No.
ELECTRICAL CONNECTIONS
8
Power; Output
9
Power Supply VCC
2
Pre.; Feedback
3
Pre.; Output
4
ALC Output
11
Filter
R.P. Head Bias & Filter
10
Boot Strap
6
*
12
Power; Input
13
ALC Input
7
Power; Feedback
14
Pre.; Input
5
*
ELECTRICAL CONNECTIONS
1
Pin 5 is terminal to reject radiations in strong electric field.
351
j.lPC1221C
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Supply Voltage (DC)
VCC1
13
V
Supply Voltage (AC)
VCC2
9
V
Circuit Current
ICC (peak)
Package Dissipation
Po
A
2.4*
W
°c
°c
Operating Temperature
T opt
-20 to +75
Storage Temperature
T stg
-40 to +125
* Mounted and soldered on a 50 mm x 50 mm
copper foil of a printed circu it board (X X X3 grade).
RECOMMENDED OPERATING CONDITIONS (Ta=25 °C)
6
Operating Supply Voltage
V
3.5 to 9 V
Supply Voltage Range
ELECTRICAL CHARACTERISTICS (Ta=25 °c, Vcc=6 V, f=1 kHz, NAB, RL(pre) =10 kil, RL(power)=4 il)
CHARACTER ISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
25
40
mA
TEST CONDITIONS
[OVER ALL CHARACTERISTIC]
Circuit Current
ICC
10
Output Power
Po
0.8
No Signal
1
W
VR-MAX. T.H.D.=10 %
1.0
2.0
%
VR-MAX. PO=0.5 W
Total Harmonic Distortion
T.H.D.
Output Noise Level
NL1
9
20
mVr.m.s.
ALC Characteristic
ALC1
1.5
9
dB
Vi=-70--40 dBm, RL'=56 n
ALC Range
ALC2
60
dB
T.H.D.;:;:; 3 %, RL'=56 n
65
dB
RL(pre)=10 kn, VO=0.3 Vr.m.s.
-
Using P. head as an RG.
VR-MAX.
[PRE AMPLIFIER STAGE]
Open Loop Voltage Gain
Avo1
55
Voltage Gain
Av2
30.8
dB
Maximum Output Voltage
VOM
0.5
0.7
Vr.m.s.
Input Impedance
Ri1
18
27
kil
Open Loop Voltage Gain
Avo2
63
70
dB
Voltage Gain
Av2
44
NAB, VO=0.3 Vr.m.s.
RL(pre)= 10 kil, T.H.D.=1 %
[POWER AMPLIFIER STAGE]
dB
NL2
Ripple Rejection Ratio
R.R.A.
40
50
dB
Ri2
15
25
kn
Input Impedance
352
46
Output Noise Level
0.4
2.0
mVr.m.s.
PO=50 mW
PO=50 mW
VR-MIN. (RG=O)
RG=O
J,lPC1221C
TEST CI RCUIT
Vcc=6V
150Q
RL
56Q
JL
PC1221C
7.: Polyester Film
Capacitor
f
4.7:
J.lF
SG
f= 1kHz
RG=600Q
ITEM
ALL
ICC
Po
T.H.D.
NL
ALC
PRE
Avo
Av
Vorn
POWER
Avo
Av
NL
R.R.R.
SW1
SW2
SW3
SW4
SW5
SWS
SW7
SWa
OFF
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
1
2
OFF
OFF
OFF
OFF
OFF
OFF
OFF
2
ON
1
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
OFF
OFF
OFF
OFF
1
2
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
2
2
1
2
2
2
1
1
1
2
2
2
1
4
4
4
3
3
4
4
OFF
ON
OFF
OFF
OFF
2
2
2
1
2
2
2
2
2
2
2
1
1
1
1
2
2
2
2
2
2
2
353
CA>
01
~
~
""tI
("")
";.,,l
N
N
MPC1221C TYPICAL APPLICATION
";.,,l
(')
S2
+
220
).IF
@
-----------
®
-----l
-:I
R.
~
6V
......l.-
I
I
MIC JACK
ur·
1000).lF 1+
.....-----b@
MONITOR
JACK.
Filter
P
Ss
(2)
(]
22kQ
1
56Q
SP4Q
100Q
1000
pF
I nsurt a capacitor (about 1000 pF) between pin 5 and pin 14 when the JlPC1221 C is affected by radiations in strong
electric field.
7.(
Polyester Film Capacitor
j.lPC1221C
CHARACTERISTICS
TOTAL HARMONIC DISTORTION vs.
OUTPUT POWER
TOTAL HARMONIC DISTORTION vs.
OUTPUT VOLTAGE
(POWER AMPLIFIER STAGE)
(PRE AMPLIFIER STAGE)
10
Vee 6.0 V
RL(pre)-10 kQ
5
~
~
3
I
0
'';:::;
RL(Po)
I
I
I
c
c
o
20
1/
r-----
~
10
i:5
0.5
.~
c
r - - t;;.,f
:"\
<.)
5
r-. \f-< 'f'~'ioo
0.3
0
§
r~
ro
I
0.1
ro
"0
I-
J-
r=f
1\
!I
/'p
~
10 kHz
1
ro
I
.....
2
......... "
.I
I
0.5
d
:i
~
0.01
0.01
0.03 0.05 0.1
0.3 0.5
0.2
0.1
0.01
3
Po - Output Power - W
OUTPUT NOISE LEVEL,
TOTAL HARMONIC DISTORTION
vs. SUPPLY VOLTAGE
OUTPUT POWER, OUTPUT VOLTAGE GAIN
vs. AMBIENT TEMPERATURE
(PRE AMP. + POWER AMP.)
(PRE AMP. + POWER AMP.)
20
Vee =6 V
2
f=l kHz
RL(P0=4 Q)
T.H.D.{Po =0.1 W)RL(Pre)=10 kQ
NAB
J I
0
a
~
>
E
1/t;.A u
I
I
.....
~
0
-2
I
I
Po{T.H.D.= 10
c..
%)
/
.... 1.0
-
:l
b.O
~
0
0
I
>
-4
0
I
c..
;,
:l
4:
CD
en
C
10
Z
:i
ro
I
z
20
40
60
80
Ta - Ambient Temperature - "C
I
ci
:i
.... /
/'
£--
.....
0.5
~
-6
o
~/
'0
5
...J
o
1.0
I-
:l
-20
§
ro
I
.e-
I
1.4
-
r--
j
1.0
0.8
0.6
/
I
/
60
II
E
....cI
~
:l
40
/
/
U
0.4
:;
0.2
C3
a
I
.r-
;:,
4:
/
II
Au(uo =-10 dBm) /
80
4:
1.2
Po(T.H.D.=lO %)
RL(Po)=4 Q
RL(Pre)=10 kQ
NAB
20
I
V
V
./
V
lee{No Signal)
.J. /
~
1-0
~
a
2
4
6
8
10
Vee - Supply Voltage - V
355
ttPC1221C
VOLTAGE GAIN vs. FREQUENCY
IIIII
VCC=6 v
Rt.(P o)=4 Q
Rt.(Pre)=lO kQ
Po=50 mW(Pre+Po )
90
80
~r!~~~
. /r-f.(.
~oA=BO.3 vr.m.s.(Pre)/
m
"0
70
I
c:
.iii
I--
~
i'r-.
60
(,!)
Q)
tlO
50
g
40
~
I
;:,
i/
30
«
Vi-"
V
Po
--""
'" II
Pre
-i""'-~
-r--- 1"- ....
-r-.
20
10
10
50
20
100 200
500
1 k
2 k
5 k 10 k 20 k
50 k 100 k
f - Frequency - Hz
TOTAL HARMONIC DISTORTION vs.
OUTPUT POWER
(PRE AMP. + POWER AMP.)
~
Vee 6 V
R L(Po)-4 Q
R L(Pre)=10 kQ
50
I
g
t:
.E
en
I
u
f=100
10
:e
.E
en
-
'c0
--~-
E
ro
~nt
o
f
0.5
...,:
ro
0.2
0.5
2
5
10
m
"0
I
:;:;
Q)
0
E
en
3 tlO
c:
ro
10
~
0
C,,)
u
Q)
'c0
E
ro
Vee=6 V
f=l kHz
E
I
tlO
ro
2
~
>
0
.....
::l
:::I:
ro
.s-
I-
0
o
::l
~ -10
I
d
~
-20
\
\ ,..\ I
\/
Ii\.
Vo
.....
IH.D
~
V
-90 -80 -70 -60 -50 -40 -30 -20 -10
Vi - Input Level - dBm
356
Q
ALe range
/ \....
I
0
RL(Po)=56
,
c:(
::C
...,:
2
-
~
50
100
200
0
/
V
~
I-oo~
"'500
1 k 2 k
f - Frequency - Hz
Output Power-W
20
/
\
\\
::C
...,:
T.H.D., ALC OUTPUT VOLTAGE CHANGE vs.
INPUT LEVEL
c:
I
V
\
\
4
I
Po -
~
6 t-po =0.1 W
l-
0.2
I
~
0
1 kHz
d
0.1
0.010.02 0.05 0.1
4
.",Po =0.5 W
:::I:
d
::C
8
u
I
1<,
./
-~- ;..or--:
2
ro
I
NAB
c:
H~,
I"
:::I:
l-
Q
RL(Pre)=10 kQ
10
C
5
o
E
ro
Vee=6 V
RL(P o)=4
0
C
'c
(PRE AMP. + POWER AMP.)
~
NAB
20
TOTAL HARMONIC DISTORTION vs. FREQUENCY
5 k 10 k 20 k
50 k 100 k
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1263C2
DUAL AUDIO POWER AMPLIFIER
DESCRIPTION
The pPC1263C2 is a dual audio power amplifier in a 14-lead dual in line plastic package, and designed for portable audio sets.
FEATURES
•
Wide operating voltage range. Vee = 3 to 16 V
•
High output power.
Po =2 Wat 12V/Sn/10%
Po = 1.6 W at 9 V / 4 n / 10 %
Po = 1.2 W at
9V/ S
n / 10 %
Po = 0.7 W at
6 V /4 n / 10 %
Po = 0.5 W at
6 V / S n / 10 %
Po = 50 mW at 4.5 V /32 n / 10%
(Vee / RL / T.H.D.)
•
High ripple rejection ratio.
R.R.R. = 50 dB
•
Low quiescent current.
Icc = 1 0 rnA
•
Easy assembly so that two power amplifiers are built in a package.
PACKAGE DIMENSIONS in millimeters (inches)
14
13
12
11
10
9
8
R1
(R 0.039) - > r i + - - - - - - - - - - - - --t+------+-
2
3
4
5
19.4 MAX.(0.763 MAX.)
6
7
762(0300)
24.6 MAX.(0.968 MAX.)
6.5(0.256)
0.3:g:~5-:
(0.012)
I
V
\
\
J
-
~
I
f
8.4± 1.5
0.333)
357
,uPC1263C2
ABSOLUTE MAXIMUM RATINGS (Ta
= 25°C)
RATING
UNIT
Supply Voltage (No Signal)
SYMBOL
VCC1
18
V
Supply Voltage (Operating)
16
V
2.4 *
W
Operating Temperature
VCC2
PD
T opt
-20 to 70
Storage Temperature
T stg
-40 to 150
ITEM
Allowable Power Dissipation
°c
°c
* 50 X 50 X 0.035 mm Copper heat sink on PCB.
RECOMMENDED OPERATING CONDITIONS (Ta
ITEM
Supply Voltage (AL=16
n)
= 25°C)
MAX.
UNIT
3
16
V
SYMBOL
MIN.
VCC (16)
TYP.
Supply Voltage (RL=8
n)
VCC (8)
3
13
V
Supply Voltage (RL=4
n)
VCC (4)
3
9
V
Load Impedance
RL
4
8
n
Voltage Gain
Gv
34
44
dB
MIN.
TYP.
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
(Vcc=9 V, RF33 [2, f=1 kHz, RL=8 [2)
ITEM
Circuit Current
SYMBOL
MAX.
UNIT
ICC
10
mA
No Signal
Gv 1
44
dB
Po =0.25 W, Rf=33
Gv2
34
dB
Po =0.25 W, Rf=120 n
Pol
2
W
VCC=12 V, RL=8
P02
1.6
W
VCC=9 V, RL=4 n, T.H.D.=10 %
1.2
W
VCC=9 V, RL=8 n, T.H.D.=10 %
P0 4
0.7
W
VCC=6 V, RL=4 n, T.H.D.=10 %
P0 5
0.5
W
VCC=6 V, RL=8 n, T.H.D.=10 %
P0 6
50
mW
T.H.D.1
0.8
%
Po =0.5 W, Rf=33
T.H.D.2
0.4
%
Po =0.5 W, Rf=120
Output Noise Voltage
NL
0.6
mV r .m •s.
Ripple Rejection Ratio
R.R.R.
50
dB
Cross Talk
C.T.
55
dB
RG=O, Po =0.25 W
dB
Po =0.25 W
Voltage Gain
Output Power
P0 3
0.9
TQtal Harmonic Distortion
358
CONDITIONS
Cbannel Balance
Ch.B.
Input Impedance
Zin
-2
0
5
2
Mn
n
n, T.H.D.=10 %
VCC=4.5 V, RL=32 n, T.H.D.= 10%
n
n
RG=10 kn
RG=O, f(ripple)=1 00 Hz,
V(ripple)=0.3 V r .m .s.
tlPC1263C2
BLOCK DIAGRAM
r------@-----
---.-@)---- - - - - - ,
I
I
I
I
...---------{ 9
13~----I
"">-----~8
12~-----1
TAB
14
5
2
I
3
I
I
I
I
I
I
I
L ___
_J
CONNECTION DIAGRAM
PIN NO.
CONNECTION
PIN NO.
CONNECTION
1
Filter
8
Output 1
2
Input 2
9
Bootstrap 1
3
NFB2
10
VCC
4
Compensation 2
11
Compensation 1
5
Bootstrap 2
12
NFB 1
6
Output 2
13
Input 1
7
NC
14
GND
TAB
GND
359
JLPC1263C2
TYPICAL APPLICATION
r-------------~----~--------OVCC
I
t2
+ Cs
I C7
....L..:
lO.IPF
C2 (Ce)
r--~
I 22
1----
C4
~
--------+-----~-----.
pF
I
I
I
SP 1
I
I
TAB
I
I
:
I
I
L __
100
pF
:
1
Cll (Ce)
C13
,---1 r----+--~+t:::I------,
22 pF
0.1 :F
~
220 J.lF
12
SP 2
4
*Mylar Capacitor
NOTE FOR USE
(1)
(2)
(3)
(4)
360
Mylar capacitor is recommended as C4, C12.
Add C2, C11, in the case of reducing voltage gain at high frequency.
Add C7 or increase capacitance of C4, C12, when a oscillation may occur due to the pattern on PCB.
Voltage gain can be changed by value of R1 , R3.
,uPC1263C2
TYPICAL CHARACTERISTICS (Ta =25°C)
CIRCUIT CURRENT
VS.
SUPPLY VOLTAGE
OUTPUT POWER vs. SUPPLY VOLTAGE
2
50
RL=4
~
Q
7 IJ
RL =8
30
II
:;
u
RG=O
'3
~
I)
IV V
)V
7/ v . .
.e
:::l
20
U
:::l
I
l/
u
9
10
i.-- ~
~
V
V
o
V
I
8
4
16
12
8
4
5
2
50
4
"
40
~
I
c
0
CD
t
"0
'n;
30
3
C!)
RL=8
Q)
bO
2
-0
>
I
0
u
V o=0.3 Vr.m.s.
~
~
'c
0
Q
f=1 kHz
Rf=33 Q
20
2
E
ro
::I:
Iii
0
C!)
I
30
C!)
Q)
bO
2
-0
>
I
20
;0
C!J
I
ci
:::C
10
8
10
~
\
16
12
I
............. Gv
...........
8
bO
2
6
0
.....c:
Q)
Q)
4
:::l
0'
I
U
0
~
2
0
u
'c0
E
ro
Iii
0
\
I
ci
:::C
"' .................
...,.:
IH.D.
100
200
MAXIMUM POWER DISSIPATION
5
Q)
'13
--
~
0
vs. SUPPLY VOLTAGE
10
~
'5
0.
'5
-
Rf-Q
aUECIENT OUTPUT VOLTAGE vs.
SUPPLY VOLTAGE
I
"""-- """--
t
l-
vee-Supply Voltage-V
>
c:
0
\
o
20
~
::I:
...,.:
IH.D.
4
'"
"0
c:
'n;
Vo = 1 Vr.m.s.
~
CD
l-
o
RL=8 Q
f=1 kHz
.~
-- --
Gv
20
TOTAL HARMONIC DISTORTION,
VOLTAGE GAIN vs. Rf
50
I
16
12
vee-Supply Voltage-V
VOLTAGE GAIN vs. SUPPLY VOLTAGE,
TOTAL HARMONIC DISTORTION
I
c
Q
V
...
o
20
vee-Supply Voltage-V
40
I
~L=32
/
/
v
/'
/
o
/
JIf /
o
a..
%
Q
V7
E
I
~
I
I
40
c:
f=1 kHz
T.H.D.=10
I
V
/
4
V
V
V
VRG=O
V
v
::
I
c:
:3ro
4
0.
'iii
II)
i5
t
~
0
3
a..
E
:::l
E
'x
ro
I
2
RL=4
~
I
~
'i5'
a..
vee-Supply Voltage-V
16
20
j
V
RL=8
~
12
II
VV
17:I7 v""
X
8
QJ
[,7
Q
./
V RL =32
Q
./
0
~ ~V
4
8
12
16
20
vee-Supply Voltage-V
361
jlPC1263C2·
VOLTAGE GAIN, TOTAL HARMONIC
DISTORTION vs. FREQUENCY
60
II
50
I
c:
'(!)
co
bO
30
I
20
::>
Vee=9 V
RL=8 Q
Rf=33 Q
Vo = 1 Vr.m.s.
)1
>
(!)
't---.
10
30
~
~~
'< /)f:'~
<:::-./00
:e
4
0
3
1'-.
2
),..-'J..
50
o
3 k
5 k
10 k
0
I
-j..
1k
:::c
ro
c::i
11 I
300 500
E
l-
V
100
~
0
.2
c:
./
T.H.O.
0
ro
/),.c-
i"--""
t---
o
dB~ol
~- t-t-.l
t'-t--,
vY
Q)
.e
<5
5
c:
Gv
U. 1--"....- r-~[J1
V Co =47 J.lF
40
~
I
III
e~='2do' ~~
>
6
:i
..-;
30 k 50 k
F-Frequency-Hz
PACKAGE DISSIPATION vs. AMBIENT
TEMPERATURE
TOTAL HARMONIC DISTORTION
vs. OUTPUT POWER
~
30
,
I
c:
o
~
~
10
u
5
o
'c
o
E
ro
:::c
ro
o
Infinite
Heat Sink
;:
I
~.
2
c.
.~
3
\",,\Q
1
I-
~ 0.5
:i 0.3
..-;
-I-""
0.01
'f-~"L.- 1--'":'--
0
"
~
\""
1.5
Q)
bO
ro
..:.::
u
ro
\",,\~"L
UNIT:mm
0-
I
\ 'f-'r\"L
Cl
0-
0.5
0.03 0.05 0.1
0.3 0.5
Po-Output Power-W
3
5
a
25
50
75
100
Ta-Ambient Temperature-'C
362
Fig.A
Vee 9 V
RL 8 Q
Rf=33 Q
125
150
BIPOLAR ANALOG INTEGRATED CIRCUIT
pPC1277H
4.2 W DUAL AUDIO POWER AMPLIFIER
DESCRIPTION
The pPC1277H is a dual audio power amplifier designed for a stereo radio cassette and in a 12-pin power single in line plastic
package.
The pPC1277H has two audio power amplifiers and each of the two provides 4.2 W output power at 12 V /4 ohms.
FEATURES
• High output power.
4.2 W /ch (TYP.)
Vee = 12 V, RL =4 ohms
5
W/ch (TYP.)
Vee = 12 V, RL =3 ohms
2.2 W/ch (TYP.)
Vee = 9 V, RL =4 ohms
3
Vee = 9 V, RL =3 ohms
W/ch (TYP.)
• Wide operating voltage range.
Vee = 5 to 16 V
• No shock noise at power supply switch on and off.
• Soft clipping wave form.
• High ripple rejection ratio.
R.R.R. = 50 dB (TYP.)
• Few external components.
12 parts
• Thermal shut'down circuit is built in.
• A 12·pin power SIP can easily be mounted on PCB and a external heat sink can easily be attached.
BLOCK DIAGRAM
r--------------~-------~
~11:4l
~
I
16
IN1
47 J-lF
+
Vee
10
Filter
3
2
1
15
1
1
RL
I1
0
12h
I
17
1
I
IN2
111
I
1
I
0.068 PF
Thermal
Shut Down
1L _______________________ 1
~
I
363
,uPC1277H
PACKAGE DIMENSIONS
in millimeters (inches)
CONNECTION DIAGRAM
(0.196 MAX.)
U
Pin No.
Connection
1
GND (Input)
2
Output 1
3
Boot Strap 1
4
Filter
N~--IJ"--~
5
NFB 1
~~
~~~---.sCTl-L_
..__
6
Input 1
7
Input 2
8
NFB 2
Boot Strap 2
9
10
4
(0.0118)
0.75±0.1
(0.0295)
VCC
11
Output 2
12
GND (Output)
ABSOLUTE MAXIMUM RATINGS {Ta~25 °C}
Supply Voltage (No Signal)
VCC1
Supply Voltage (Operating)
VCC2
16
Allowable Power Dissipation
Po
13*
Operating Temperature
T opt
Storage Temperature
T stg
20
-20 to +75
-40 to +150
3
* 100 x 100 x 2 mm AI heat sink
RECOMMENDED OPERATING CONDITIONS (Ta
=25°C)
Supply Voltage
5 to 12 to 16
Load Impedance
3 to 4 to 8
V
ohms
ELECTRICAL CHARACTERISTICS
(
CHARACTER ISTIC
Circuit Current
Voltage Gain
SYMBOL
MIN.
TYP.
MAX.
UNIT
ICC
Av
20
45
90
mA
42
45
48
dB
Po 1
1.8
2.2
W
Po2
2.5
3
W
Po3
3.2
4.2
W
Po4
4
5
W
Output Power
364
VCC = 12 V, RL =4 ohm, f= 1 kHz, Ta =25 °C,)
100 x 100 x 2 mm AI Panel Heat Sink
Total Harmonic Distortion
T.H.D.
0.2
1
%
Output Noise Voltage
NL
0.6
2
mVr.m.s.
Cross Talk
C.T.
45
55
Channel Balance
Ch. B.
-2
0
Ripple Rejection
R.R.
40
50
dB
Input Impedance
Zin
30
50
kohm
dB
+2
dB
TEST CONDITION
No Signal
Po =1 W
T.H.D.=10 %
VCC =9 V, RL =4 ohm
T.H.D.= 10 %
VCC =9 V, RL =3 ohm
T.H.D.= 10 %
VCC =12 V, RL =4 ohm
T.H.D.=10 %
VCC=12 V, RL =3 ohm
Po =1 W
RG = 10 kohm
Po =1 W
other ch. RG = 10 kohm
Po =1 W
RG=O, f=100 Hz
v=0.3 Vr.m.s.
,uPC1277H
TEST CIRCUIT
"""--0 Vee
SWITCH POSITION
(AMP 1 : TEST)
ITEM
Circuit Current
Voltage Gain
SYMBOL
SW 3
SW 1
SW 2
ICC
2
2
1
Av
1
1
1
Output Power
Po
1
1
1
Total Harmonic Distortion
T.H.D.
1
1
1
Output Noise Voltage
NL
2
1
1
TYPICAL
APPLICATION
47 ~F
+
+
vee
1 000
~F
OUT 1
INl
IN2
"1
eg *
0.068
OUT 2
*Polyeater Film Capacitor
TYPICAL PCB
(COPPE R SI DE)
0
0
365
,uPC1277H
TYPICAL CHARACTERISTICS (Ta = 25°C)
POWER DISSIPATION vs.
OUTPUT POWER
PACKAGE DISSIPATION vs.
AMBIENT TEMPERATURE
24
~
10
AI Panel t=2 mm
Silicon Grease
20
\
I
,g 16
~
C'J
\
cm 2
"'- ~OO
........ ~
0.
·iiI
Ul
Ci 12
100 cm2
Q)
be
~
, ,
'","'- '~, \
\
- r-- r-- -"'-r- "
~
&8
C'J
0.
"\
\
·iii
Ci
~
0
o
a.. 4
a..
........
~ee Air
o
20
~
4
I
........
0
a..
~
I
....
/
1/
6
a..
T.H.D.=lO
5
%/
~
0
Ul
I
/
366
8
10
12
14
Vee - Supply Voltage - V
16
"0
I 40
c:
.(ij
Q
f=1 kHz
468
Po - Output Power - W
10
12
lee(Vi=O)
I
V
(!)
·5
~
Q)
2
30
A v (PO=O.1 W)
(5
u
0.8
a:J
>
I 40
u
...Y
0.4
30
o
20
I 20
~
10
T.H.D.(PO=O.1 W)
t-=
/.. ~
6
Vee=12 V
RL =3 Q
f--
V
4
:: 50
ci
//
o
~:::l
~ 1.2
I
/ V
/
1.6
l-
I /
2
2
50
70
E
I
<:60
o
·2
~
/ //
VV
3
!,Vee=16V
RL =4 Q
Vee = 12 V
~
C'J
II
4
a..
"-
60
80
2.0
:r:
=4 Q
II I/RL
T.H.D.=l0 %-
0.
0
.8
Ci
V
RL =3 Q
a
I
c:
/ J
~
,
RL =4 Q
f = 1 kHz
.Q
/ /
V
Q)
~
*-I
)
~
I"
SUPPLY VOLTAGE CHARACTERISTICS
2.4
7
Vee=16 V
RL =3 Q
2 ch Action
OUTPUT POWER vs. SUPPLY VOLTAGE
8
.............
160
f = 1 kHz
9
l"-
....... ~
RL =4
0
10
..............
"'" "'"
2
140
---
I - --r-....
//
II ,/" - - ...........
'II - ..........
r/
~~
40
60
80
100
120
Vee - Supply Voltage - V
/'"
...........
Q;
.......
I
6
Ul
\
J
/'
./"
c:
a
...,.
Inflnlt
I
Heat Sink
.....
8
I
.r. I
V
18
6
8
10
12
14
Vee - Supply Voltage - V
16
18
j.lPC1277H
VOLTAGE GAIN, TOTAL HARMONIC
DISTORTION vs. FREQUENCY
70
1.4
Vcc= 12 V
RL =4 Q
60
CD
50
-0
1
\
\
\...............
~ 30 /1\
~
tlD
>
\
20
V
t\
50
I~,·~
--
I'-....
10
30
o
0.8
V
o
0.6 ~
(I]
(5
.....
'J
0.4
1
o
I
0.2 t-=
ml
11
1 k
f - Frequency - Hz
300 500
100
0
·c
E
J
\
1
.~
Vi
6
V
(I]
>
1.0
I
1
« u20
!::?
T.H.D.
........... r'
(PO=l W) _ ~
I
2:
~
AV
Po
(T.H.D.=lO %)
o
/11
f= 100 Hz
""""-.
F40
(I]
>
...........
«
c.!)
1
;§ 0.4
I
.-
o
::;
o
(I]
Cil
c
~1.4
~ '; 70
Ta -
Ambient Temperature -
~ + 40
4
Q)
.
>
Cl
I
Cl
30
° ~ 30
20
;:, a:
'-V
o
....
I
6
Supply Voltage -
8
10
V
- , ......
/V
Po
I
~ 50
~
0
> 40
;:,
YOM
/
II"
/
L
Po ~ 50 Imlyj ~ ~ro + P~)
V o =0.3 V( Pro), NABVCC=6 V
V- - -........
CJ
«
,
L,
Ii
0
I
80
60
lOW
'C
III
co
I
E
Pre+~o
90
c
5W
VOLTAGE GAIN vs. FREQUENCY
100
"0
I
80
60
40
I
o
CJCl
0
20
3W
1.8 f= 1 kHz
RL( PRE) = 10 kQ
I 1.6 RL( Po) =8 £2
80
10
0...>
o
IW
Vcc=6 V
90
_0.
u
.5:?
I
I
-20
300500
100
g,
I 0.8 RL(Pa) =8 Q
+-
/~
I
f-
100
L~li
I
0
~
11
V
'"
~~II~./~~l/m'l~r!Hm~
0.1
II II
Hz~
0.3
I
o
~
0
-10 kHz
I
120
0
----- r - r
f--l kHz
Vcc=6 V f-lRL(Po)-=8£2
IIIII
- - -t-
0
(j)
--c----
~-+-++++++---10+0-HZ- r/
r,Y ! f
c
--r
,
/[
III
1O,-k~Z
3
f - --. -.
30
20
/V ""~,...
"
~-~t
~
Pre
-I'-- ......
10
o
30
100
10k
lk
f - Frequency -
lOOk
Hz
371
,uPC1350C
TOTAL HARMONIC DISTORTION vs. FREQUENCY
(PRE AMP. + POWER AMP.)
P~~50
mV
50
f-Vc~ -'c Sv
30 f-pLAY
PLAY
c:
.g
,/
I!
10 \
c:
o
.~
o
en
10
o
B
.~
o
TOTAL HARMONIC DISTORTION vs.
OUTPUT POWER
(PRE AMP. + POWER AMP.)
en
3
~
E
~
\
:r:
(ij
;§
./
B
5
.§
3
~'I
10\kHz~/
o
/~
!:
ttl
:r:
"11:::::_
(ij
(5
l-
o
~
~
1k
300
100
3k
30k
10k
0.1
f - Frequency - Hz
1 kHz
10
3
30
TEST CIRCUIT STATUS
ITEM
SW1 SW2 SW3 SW4 SWs SW6 SW7 SWa SW9
ICC
OFF
1
OFF ON
2
OFF
2
OFF
1
Po
T.H.D.
ON
2
OFF OFF
2
OFF
2
OFF
1
ON
2
OFF OFF
2
OFF
2
OFF
1
NL 1
ON
1
OFF OFF
2
OFF
2
OFF
1
ALC
ON
2
OFF OFF
1
OFF
1
OFF
2
Av01
ON
2
ON
OFF
4
OFF
2
ON
2
Av02
ON
1
OFF OFF
3
ON
2
OFF
2
NL2
ON
1
OFF OFF
4
OFF
2
OFF
2
TEST CIRCUIT
} - - 4 - - - - o Vcc=6V
R.&. P.
HEAD
SG
f=lkHz
Ra=600Q
372
-
100
Po - Output Power -
15953
r-
1
0.3
~
30 50
i {
l)~
120 ~z
r""-o..
I 0.5
:i 0.3
I
300 500
mW
R6
r---i?-'
TYPICAL APPLICATION
II
REMOTE ON & OFF
SWITCH JACK
+
470llF =C7
v:r~ov
S3
CIS
3300pF
+
10001lF= Cs
.MIC.JACK
15kQ
1S953
1,
01
Cl
SI-2
~
9>
Cg
220llF
22kQ
+
Rl10Q
ClOr
O.0681l~
,uPC1350C (Top View)
TAB
S.P.
8Q
Rt.:
56Q
22kQ
R14
SI-3
ERASE HEAD
r
~
1:::
SW 1 :REC./P.B.
(P.B. POSITION)
SW2:AC/OC OPERATION
(DC OPERATION)
SW3 : Power Switch
(ON POSITION)
-a
C')
~
W
(J1
o
C')
(,)
~
W
,uPC1350C
TYPICAL CHARACTERISTICS (Ta = 25 OCt TYPICAL APPLICATION CIRCUIT)
RECORDING CHARACTERISTI CS
~~~~6 V I
Vin=-90dBm
CD
80
"0
IL
I 70
c
~ 60
~
b-...
/"
/~
(I)
~ 50
'"
~ ....
~
.... fo-' ....
o
> 40
I
;;:,
<{
30
20
10
o
1k
100
f -
Frequency -
ALC OUTPUT VOLTAGE CHANGE vs.
INPUT LEVEL
I
E
CD
1+4
(I)
OJ
C
~
o
+ 2
I
&-4
::J
o
() -
6
-.J
<{ -
8
I
-> -10
-12
T.H.D. AT ALC OUTPUT vs.
INPUT LEVEL
,0
~
-
k--"'"
--
;
a.
;
0
~
io-
Output Voltage
change
I
I
I
J
::J
lOOk
10
1
Vee=6V
f-RL'=56Q
"0
10k
Hz
()
I
-.J
<{
;C
c
0
I
\
3.0
Vee 6 'v
RL' 56 Q
\
AU
I
range
\
1.0
';:0
'\
0
'\.
U;
0
0
'c
0.3
0
\..
........ ~
I
./
E
ro
I
iii 0.1
I
1
0
f-
I
q
90 -80 -70 -60 -50 -40 -30 -20 -10 0
Vi -
Input Level -
dBm
:r;
f-
-90 -80 -70 -60 -50 -40 -30 -20 -10 0
Vi - Input Level - dBm
NOTES FOR USE
1. About capacitor C 10
To avoid parasitic oscillation at power amplifier stage, apply the suitable capacitor as C 10 as follows.
For a cassette tape recorder, a ceramic capacitor or a Mylar capacitor can be used equally.
For a cassette tape recorder with radio, use a Mylar capacitor. If a ceramic capacitor is used, a parasitic
osci Ilation may occur caused by feed back as rad iation from the capacitor to an R F stage.
2. About recovery time at recording
A recovery time depends on a time constant of a capacity value of C2 and a pallarel value of R4 and an input
impedance of IC at pin 13.
The recovery time can be adjusted by R4 value.
374
,uPC1350C
PRINTED CIRCUIT BOARD DESIGN CONSIDERATION
1. Use the widest possible printed foil for a power supply and a ground.
2. The earthing point of C8, C10 and an output terminal should be located as close as possible to the earthing
(ground) pins (pin 1 and TAB).
3. One-point earthing is ideal, but if this is impossible, keep the input loop out of the output loop.
Output loop
Output
Input loop
GND
(pin1 )
(good example)
In
Output
Input
Input loop
GND
(pin 1)
(bad example)
375
•
1. ALPHA-NUMERICAL INDEX
2. QUICK REFERENCE GUIDE
3. CROSS REFERENCE GUIDE
4. MAINTENANCE AND OBSOLETE TYPES
5. GENERAL STATEMENT
-(:( NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
o History
0
Types and Features
o Type Number Designation
0
Device Technologies
-(:( STANDARDS OF INTEGRATED CIRCUITS
-(:( HINTS ON CORRECT USE
-(:( TECHNICAL SYMBOLS AND TERMS
*
RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
6 -1.
CAR AUDIO
6-2.
HOME AUDIO
6- 3.
PORTABLE AUDIO
7. TV APPLICATIONS
8. DIGlTAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11. ARRAYS
12. OTHERS
13. APPLICATION NOTES
•
TV APPLICATIONS
INDEX
Page
pPC574J
33 V Tuning Voltage Stabilizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
382
pPC1361C
12 Channel Selector
386
pPC1362C
12 Channel Selector
392
pPC1363C
16 Channel Selector
398
pPC1373H
Remote Control RX Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405
pPD1913C
Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
pPD1937C
Remote Control Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
pPD1943G
Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411
pPD1986C
Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423
pPD1987C
Remote Control Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
pPD6102G
Remote Control Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433
pPC1356C2
PI F Processor & AFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442
pPC1366C
B/W PI F Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
pPC1353C
SI F Processor & Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
pPC1382C
SI F Processor & DC Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463
pPC1391H
SI F Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469
pPC1352C
NTSC Chroma & Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473
pPC1364C2
SECAM Chroma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
pPC1365C
PAL Chroma & Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
505
pPC1384C
PAL Chroma & Picture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
525
pPC1397C
Picture MUltiplex Adaptor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
545
pPC1031 H2
B/W Vertical Deflection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
552
pPC1377C
Color Synchro Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
560
pPC1378H
Color Vertical Deflection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
565
pPC1379C
B/W Synchro & Deflection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
569
-
379
w
o
(X)
BLOCK DIAGRAM
-I
<
Color TV Block
»""C
""C
SOUND BLOCK
I[ t
r-
o-
VIF BLOCK
Ant.
. . . . - - - - - - - - I'PC1382C - - - - - - - - ,
~~:~::~
r
2SC2688 x 2 2SC2802 x 2
~n;:l
~
L.t.::J
UHF & VHF
Tuner
Booster
Amplifier
»
-I
Mono
o-
Stereo & Bilingual
L ~I
PIF
~u8ABC
II
II ~~;~, I
~
I'PC2002.I'PC1238 - -
POWER
SUPPLY BLOCK
AGC
I I'~~;'~
r--"I'PC1394CCHROMA & VIDEO BLOCK
t
I"'"
Switching
Regulator
I'PC1365C (PAL) - - - - - - ,
I'PC1384C (PAL)
~
TUNER CONTROL BLOCK
I'PC574J
I'PC78L( )( )
I'PC78M()( )H
I'PC78( )()H -
I'PC1361C
;- I'PC1362C
,
r- I'P8562C -
I 16 Channel
r- I'PD1913C
I'PD1943G
I'PD1986C
I'PD6102G
~
~
'"
~I
I
I II
r--~
I'
PreAmplifier
LI
I -L ALC
COT
2SC2688
2SC2802
I
PAL& SECAM
Auto Switch
DEFLECTION
BLOCK
r--I'PC1378H--
Dnver
y
r---"PC1377C------------6Bit D/A
Converter
Synchro.
Separator
"PC1373H
~
1
Indicator
PD 1705C·012
"PD1705C.014
~~IHI
J
Remo.-Con.
Transmitter -!J~
Color
Synchronize
I'PA64H.I'PA56C
"PA2001 C-2004C
H""--c-ontr-olle-r
(Y
2SC1507
2SC2687
'--"T'"""--
r-- I'PA54H.I'PA53C -
,pm703C·'1>
•
~L-_ _ _ _~:
LSelector
--
1 GHz
Prescaler
~
~L~ter
:- I'PC1363C -
Voltage
Stabilizer
~:~~~;~~~~~~~) ~
,PC<3"C2I5'CAMI
r--I'PC1397C-
r-I'PD1937C 1
I'PD1987C
~
Infrared ..
------------------~-
Vertical
j
Horizontal
AFC
Ht
Driver
L.....-_
Horizontal
OSC
X-Ray
Protector
Vertical
Output
Horizontal
Pre-Driver
Ll.....
I I.
Horiz'ontal
Driver
Horizontal]
Output
2SC2688
2SC3209
2SC1325A
2SC1358
2SC1875
z
rn
B/WTV Block
SOUND BLOCK
'\[7
/JPC1353C
Ant.
-MC-5156MC-5192
~
~
Booster
Amplifier
I-
Y
SAW
Filter
POWER
SUPPLY BLOCK
r-- /JPC1394C-
2SC2688 x 2 2SC2802 x 2
VIF BLOCK
I
UHF & VHF
Tuner
I
-
l
~
/JPC1382C
I
I
SIF Amp.
& Detector
Sound
Driver
DC Volume
t-4~
Sound
Output
,
Mono
1-1.
~.
J
/'
/JPC1366C
I
I
1
I
PIF
Amplifier
1t
AGC
I
I
1
L
1
1
I
I
Video
Detector
,
1
Video
Buffer
I
DY
I
(
l
I
Video
Amplifier
IE
J1
~
CRT
\~
2SC2688
Switching
Regulator
SP
DEFLECTION
BLOCK
J
,~PC1379C-
I
J
l
I
Synchro.
Separator
Horizontal
AFC
~
I
1
.,
Booster
I
•
/JPC1031H2
Vertical
OSC
I
'I
Vertical
Driver
Horizontal
I
OSC
1
I
I
Vertical
Output
Horizontal
Pre-Driver
r
I
J
KHorizontal
Driver
2SC2002
Horizontal"
Output
j
2SC2373
-I
<
»
""r-(")
»-I
o
2
en
(,.)
Q)
BIPOLAR ANALOG INTEGRATED CIRCUIT
j.lPC574J
MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
VOLTAGE STABILIZER FOR ELECTRONIC TUNER
The JIPC574J is a monolithic integrated voltage stabilizer especially designed as
PACKAGE DIMENSIONS
voltage supplier for electronic tuners.
(Unit: rnrn)
1
FEATURES
• Low temperature coefficient
• Low dynamic resistance
• Typical reference voltage of 33 V
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
10
rnA
Zener Current
Iz
Power Dissipation
Po
Operating Ambient Temperature Range
T opt
-20 to +75
°c
T stg
-40 to +125
°c
Storage Temperature Range
200
(Ta =
75°C)
mW
Pin Connection
1. Anode
2. Cathode
ELECTRICAL CHARACTERISTICS (Ta =25 °C)
EQUIVALENT CIRCUIT
CHARACTERISTIC
r -____--,.-~--O
2
Stabilized Voltage
Stabilized Voltage
SYMBOL
MIN.
Vz
31
AVz/AT
-1.0
TYP.
0
MAX.
UNIT
35
V
1.0
mV;oC
01
02
03
04
05
382
I z =5 rnA
I z = 5 rnA
Ta = -20 to +75
Temperature Drift
Dynamic Resistance
TEST CONDITIONS
rz
10
25
n
I z =5 mA
f = 1 kHz
IAC=0.5 mA
°c
j.lPC574J
TYPICAL CHARACTERISTIC (Ta
= 25°C)
POWER DISSIPATION vs.
AMBIENT TEMPERATURE
DYNAMIC RESISTANCE vs.
ZENER CURRENT
80
~ 400
~
E
I
c
0
~ 300
c.
.iii
III
0
ID
200
::0
I
u
c
\
20
2III
~
Ta= +25 ·C
1\
Q.)
'" --
Q.)
u
"- .......
10
'Ero
8
c
>.
£:)
6
I
~
4
100
Iz
IAc=lO _
f= 1 kHz
.iii
'0::
I
Cl..
\
40
OJ
Cl..
£:)
\
\
60
Free Air
--
--
- -1 - - - -- c-----
-20
2
o
50
25
75
o
4
STABILIZED VOLTAGE TEMPERATURE
DRIFT vs. ZENER CURRENT
u
.!!......
>
E
....I
10
8
STABILIZED VOLTAGE VARIATION
vs. TIME
>
E
+4 ----------------r----+-------
I
c
~ + 3 1-------+------ ~----f----~
6
Iz-Zener Current-mA
Ta - Ambient Temperature-·C
0
I
+80
+60
:;:;
z
ro
+ 2 -----+-----1-----+------ - - - - -
~
.~
>
Cll
c.
E +1
.....Cll
~-=--
-------c------r- - - - -
Q.)
tID
2
>
-1--- ----+----l----+-
'0
] =:
-----c-----I-----
i
1
i5
ro
-4 - - - - 1-------
~
0
N
2
~
t~
~
Cll
~
i5
ro
=_-=-
en
------t
4
0
I'"
I
- 20
Free Air
z
-40 1---+----1 I =5 rnA XY-Recoder ~_lz=5 rnA __
r%~ ~
,V z=33.11V
I
-60
>
-80
Or----+-~~_r----~------+-~==~
Cll
+40
I
I
10
20
30
min.
t-Time
STABILIZED VOLTAGE VARIATION &
SUPPLY VOLTAGE VARIATION vs.
ZENER CURRENT
~~
+ 1.0 r - - - - - - - , - - - - . . , - - - - - - , - - - - , - - - - - ,
c
~ +0.8
.~
>
~
+0.6
+30
c
0
:;:;
~ +0.4
+20 .~
2
g
+ 10
+0.21-....L.--,---,---'-.H,c,----+------t
~
Q.)
tID
2
~
0 '0
]
i5
0
~
-0.2
-10 ~
6
-0.4
-20
~
-0.6
-30 ~
>
c.
o
J5
I
<:N - 0.81-----+
~
N
>
3
-1.0
0
Iz-Zener Current-mA
383
J.lPC574J
MEASURING CIRCUITS
Measuring Circuit for Stabilized Voltage V z
I z=5 rnA
A
v
Digital Volt Meter
Measuring Circuit for Dynamic Resistance rz
1
z
1AC=lO
Iz-
2
C
0.1 J.lF
,uPC574J
rv
f
= 1 kHz
-vz
~-+----+5
384
rnA
tlPC574J
TYPICAL APPLICATION
Ach
8ch
----T1
Ych
Zch
15 k.Q
~i
to tuning diodes (VARACTOR)
in case of Ych ON
385
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1361C
ELECTRONIC CHANNEL SELECTOR
DESCRIPTION
The pPC1361 C is an electronic channel selector integrated circuit with 4 bit output. It is capable of selecting up to 12
channels. The output terminals are design to permit the direct driving of LED or neon lamps.
This IC consists of Clock Oscillator circuit, Channel Up and Down circuit, Channel skip circuit, 4 bit Up and Down
Counter circuit, 1-12 Decoder circuit, 4 bit Output Buffer circuit and 12 channel Output Buffer circuit, all of which are
contained in a 24 pins dual in-line package.
PACKAGE DIMENSIONS in millimeters (inches)
FEATURES
•
4 bit output
•
LED, Neon lamps direct drive.
•
Low power consumption.
~
IK=5 mA, VkSAT 150 mV MAX.
Vcc=12 V, Icc=9 mA TYP.
33 MAX
(1.299
MAX)
~
~";50, ~t ~:: :-::::: j
1
•
-
2
3
4
5
6
7
8
15.24
(0.6)
13.2
(0.52)
9 10 11 12
Up to 12 channel selection.
•
Internal schmitt trigger circuit. (CHU, CHD INPUT)
•
Power ON initial channel set.
,
2.25:!:&:l,g
(0.01)
•
TV Radio etc. channel selection use.
I
0'-15'
27.94
(1.10)
BLOCK DIAGRAM
24 PINS DIP
+ 12 V-.-+----f
4 BIT BINARY
OSC
386
UP DOWN COUNTER
J,lPC1361C
ABSOLUTE MAXIMUM RATINGS
(Ta=2S °C)
Supply Voltage
1S.0
V
I K1 ...... 11, 24
-S to 30
rnA
I AO ""A3
-S to 10
rnA
Input Current to Control Circuit
IC18, 19
-5 to 10
rnA
Input Current to Control Circuit
IC13
-S to 30
rnA
VCC
Input Current to Channel Selection Circuit
Input Current to Control Circuit
*Output Voltage to Channel Selection Circuit
V K1 - 11 , 20
-0.5 to 45
*Output Voltage to Control Circuit
V 13, V AO""A3
-0.5 to 14.4
V
* Input Voltage to Control Circuit
V 15, 16, 17
-0.5 to V cc+0.5
V
V
Power Dissipation
Pd
300
mW
Operating Temperature Range
T opt
-20 to +75
°c
Storage Temperature Range
T stg
-40 to +125
°c
* At VCC=12 V
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply Voltage
VCC
9.6
12.0
14.4
V
Channel Selection Input Current
IK
5.0
fOSC
2.0
10.0
kHz
Clock Oscillation Frequency
ELECTRICAL CHARACTERISTICS
CHARACTER ISTIC
rnA
(Ta=2S±3°C)
SYMBOL
MIN.
TYP.
MAX.
UNIT
2.0
9.0
13.0
rnA
VCC=12 V
VOL(K)
150
rnV
VCC=9.6 V, IOL =5 rnA
Channel Selection Leakage Current
IOH(K)
10
}J.A
VCC=14.4 V, VOH=35 V
Address Output Saturation Voltage
Supply Current
IDD
Channel Selection Saturation Voltage
VOL(A)
0.5
V
Address Output Leakage Current
IOH(A)
10
}J.A
AFT Defeat Output Voltage
VOL(D)
6
V
AFT Defeat Leakage Current
IOH(D)
10
}J.A
TEST CONDITIONS
VCC=9.6 V, IOL =2 rnA
VCC=14.4 V, VOH=14.4 V
VCC=9.6 V, IOL =12 rnA
VCC=14.4 V, VOH=14.4 V
Channel Input High Threshold Voltage
VTH(CH)
7.2
9.0
V
VCC=12 V
Channel Input Low Threshold Voltage
VTL(CH)
5.0
8.0
V
VCC=12 V
Channel Input Leakage Current
ICH(CH)
-5
Channel Input Leakage Current
ICH(CH)
5
}J.A
VCC= 14.4 V, VIL =0 V
}J.A
VCC=14.4 V, VIH =14.4 V
Key Input Current
IIH(KJ)
200
}J.A
VCC=9.6 V
Key Input Leakage Cummt
IIL(KJ)
-10
}J.A
VCC=14.4 V, VIL =0 V
Skip Input Current
IIH(SK)
50
}J.A
VCC=9.6 V
Skip Input Leakage Current
IIL(SK)
-5
}J.A
VCC=14.4 V, VIL =0 V
Channel Hold Voltage
VHOLD
6.5
OSC Frequency
fOSC
1.0
V
2.0
3.0
kHz
VCC=12 V, R=33 kn , C=0.033 }J.F
387
w
(X)
(X)
EQUIVALENT CIRCUIT
'1;:
""D
()
...Ii
W
en
...Ii
, ()
12 V
47 k
i
1f
47 k
1f
O.OI
T
JlF ' "
12 V
33 k
0.033
JlF
r
I
I
I
I
I
I
I
L
DEF
---~--------------
NR·22 NR·23
GND
Logic Blocks consist of PMOS technology
Output and I nput consist of Bipolar technology.
NR·25 NR·26
NR·28 NR·29
I
I
--'
j.lPC1361C
CONNECTION DIAGRAM (Top View)
CHANNEL SELECTION 11 (K11)
(K12)
CHANNEL SELECTION 12
CHANNEL SELECTION 10 (K10)
(A3)
ADDRESS OUTPUT A3
CHANNEL SELECTION 9 (K 9)
(A2)
ADDRESS OUTPUT A2
8 (K 8)
(A1)
ADDRESS OUTPUT A1
CHANNEL SELECTION 7 (K 7)
(AO)
ADDRESS OUTPUT AO
CHANNEL SELECTION
(SKP)
SKIP INPUT
5 (K 5)
(KIN)
KEY SENSE INPUT
CHANNEL SELECTION 4 (K 4)
(OSC)
OSC FILTER
CHANNEL SELECTION
(CHU)
CHANNEL UP INPUT
CHANNEL SELECTION
CHANNEL SELECTION
CHANNEL SELECTION
2 (K 2)
(CHD)
CHANNEL DOWN INPUT
CHANNEL SELECTION
1 (K 1)
(VCC)
+12 V
(GND)
(DEF)
AFT DEFEAT OUTPUT
GROUND
PIN FUNCTION
K1 --12
GND
DEF
VCC
CHANNEL SELECTION OUTPUT
#11 ...... 1, #24
These are the output terminals constructed of collector-opened transistors, so they can drive potentiometers
and indicators, and key output. They have saturation voltage of 150 mV at Ik=5 mA, so they can drive
neon or LED lamps directly.
#12
GROUND
AFT DEFEAT OUTPUT
#13
This terminal is made of open collector transistor output through a resistor of 330 n. It is used for AFT
(Automatic Fine Tuning ...... TV use) defeat, sound muting and LED indicate erasing.
#14
+12 V (9.6 --14.4 V)
CHD
CHANNEL DOWN INPUT
#15
Usually pulled up to V CC through a resistor, Channel selector changes at positive going edge of input signal
of this terminal and the channel selector works orderly from K 12 to K 1.
CHU
CHANNEL UP INPUT
#16
Usually pull up to VCC through a resistor, Channel selector changes at positive going edge of input ~ignal
of this terminal and the channel selector works orderly from K1 to K12. If CHU and CHD terminals put
down to ground at same time, initial channel is selected. So, it is very useful to remote control operation use.
These terminals include schmitt trigger circuit. If these terminals are not used as remote control operation,
connect these terminals to V CC directry.
OSC
OSC FILTER
#17
When a Channel key is pushed or skip function is operated, oscillator contained in this IC oscillate with
C, R connected to this terminal. Typical oscillation frequency is 2 kHz. (R=33 kn, C=0.033 J,LF)
KIN
KEY INPUT
#18
When channel selection key is pushed, as pushed channel is not selected, "High" level of signal is applied to
this terminal through a potentiometer resistor. Then channel selector scans terminals of K1 -- K12. And
when sense up this terminal, it pull down the voltage of this terminal and stop the scanning.
389
,uPC1361C
SKP
SKIP INPUT
#19
Usually pull up to Vee through resistor. When only 10 channels are used, connect open channel outputs
(K11, K12) to this terminal with CR filter.
AO --A3
#20 --23
ADDRESS OUTPUT AO --A3
These are internal 4 bit counter output terminals constructed of collector·opened transistors. These output
can be used as 7 segment LED display or possition output for MPU reading.
Address output
Selectchannel
K 1
AO ... L
A1. .. L
A2 ... L
A3 ..• L
K2
H
L
L
L
K3
L
H
L
L
K4
H
H
L
L
K5
L
L
H
L
K6
H
L
H
L
K7
L
H
H
L
K'8
H
H
H
L
K9
L
L
L
H
K 10
H
L
L
H
K 11
L
H
L
H
K 12
H
H
L
H
*
APPLICATION CIRCUIT
12 Position Display/4 bit Encoder Output
33 k 0.01 /.LF
,...-I----I-..l..---'--L...,
K2
~
AO
K3
Al
A2
A3
Vee
DEF
''""
K'12
KIN
27 k
390
GND
4bit
Binary
Output
L. .. GND
H •.. OPEN
j1PC1361C
APPLICATION CIRCUIT
Example of TV channel selection circuit with 7 segment LED display
33 k
lSS54
x 12
lSS54r--r~~-r~-++-r4~+-~4-~~4-~~~-+~~~+-~~~
TUNING VOLTAGE OUTPUT
x12
~---VH
-""----l--VL
TUNER
BAND OUTPUT
j.lPC1361C
x3
r--I
ION
-,
I
I
I
I 0
I
I
I
I
I
I
IL.. _ _
I
_J
2
3
C
0
4
B
5
A
a
3*
.----
{AFT DEFEAT
OUT
SOUND MUTE
4-7 segment Decorder I Driver
ex. SN29764N/SAB2064
2SA733
h
15
14
g
13
12
e
11
d
c
10
9
+5V _-+----..J
7 segment LED
391
BIPOLAR ANALOG INTEGRATED CIRCUIT
pPC1362C
ELECTRONIC CHANNEL SELECTOR
DESCRIPTION
The JlPC1362C is an ·electronic channel selector integrated circuit. It is capable of selecting up to 12 channels. The
output terminals are design to permit the direct driving of LED or neon lamps.
This IC consists of Clock Oscillator circuit, Channel Up and Down circuit, Channel skip circuit, 4 bit Up and Down
Counter circuit, 1-12 Decoder circuit and 12 channel Output Buffer circuit, all of which are contained in a 20 pins dual
in-line package.
PACKAGE DIMENSIONS in millimeters (inches)
FEATURES
•
LED, Neon lamps direct drive.
Ik=5 mA, VkSAT 150 mV MAX.
•
Low power consumption.
Vcc=12 V, ICC=5 mA TYP.
•
Up to 12 channel selection.
•
Internal schmitt trigger circuit. (CHU, CHD INPUT)
•
Power ON initial channel set.
•
TV, Radio etc. channel selection use.
•
Using with JlPD1986C (TX), JlPD1937C (RX),
I
27.0 MAX.
(1.062 MAX.)
=--:l
(~t:::::;3
direct address remote control system is realized.
BLOCK DIAGRAM
20 PINS DIP
+ 12 v_+-----l
OSC
392
4 BIT BINARY
UP DOWN COUNTER
10.16(0.4)
,uPC1362C
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Supply Voltage
V
I K1 "'9, 18"'20
rnA
IC16, 17
-5 to 10
rnA
-5 to 30
rnA
Input Current to Control Circuit
Input Current to Control Circuit
IC11
* Output
* Output
*
15.0
-5 to 30
VCC
Input Current to Channel Selection Circuit
Voltage to Channel Selection Circuit
VK1"'9,18"'20
Voltage to Control Circuit
Input Voltage to Control Circuit
-0.5to 45
V
V1 1
-0.5 to 14.4
V
V15
-0.5 to Vcc
V
Power Dissipation
Pd
300
mW
Operating Temperature Range
T opt
-20to +75
Storage Temperature Range
T stg
-40 to +125
°c
°c
* At VCC=12 V
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC
SYMBOL
Supply Voltage
VCC
MIN.
TYP.
MAX.
9.6
12.0
14.4
Channel Selection Input Current
IK
5.0
Clock Oscillation Frequency
fOSC
2.0
I
UNIT
V
rnA
10.0
kHz
ELECTRICAL CHARACTERISTICS (Ta=25 ±3 °C)
MIN.
TYP.
MAX.
UNIT
2.0
5.0
10.0
rnA
VCC=12 V
VOL(K)
150
rnV
VCC=9.6 V, 10 L =5 rnA
Channel Selection Leakage Current
10H(K)
10
p.A
V CC = 1 4.4 V, V 0 H = 3 5 V
AFT Defeat Output Voltage
VOL(D)
6
V
AFT Defeat Leakage Current
IOH(D)
10
p.A
Channel Input High Threshold Voltage
VTH(CH)
7.2
9.0
V
Channel Input Low Threshold Voltage
VTL(CH)
5.0
7.0
V
VCC=12 V
Channel Input Leakage Current
ICH(CH)
-5
p.A
VCC=14.4 V, VIL=O V
Channel Input Leakage Current
ICH(CH)
p.A
VCC=14.4 V, VIH=14.4 V
Key Input Current
CHARACTERISTIC
SYMBOL
Supply Current
IDD
Channel Selection Saturation Voltage
5
TEST CONDITIONS
VCC=9.6 V, IOL=12 rnA
VCC=14.4 V, VOH=14.4 V
VCC=12 V
IIH(KI)
200
p.A
VCC=9.6 V
Key Input Leakage Current
IIL(KI)
-10
p.A
VCC=14.4 V, VIL =0 V
Skip Input Current
IIH(SK)
50
p.A
VCC=9.6 V
Skip Input Leakage Current
IIL(SK)
-5
p.A
VCC=14.4 V, VIL =0 V
OSC Input Current
mA
VCC=9.6 V, V IH=4 V
IIH(OSC)
1.5
Channel Hold Voltage
VHOLD
6.5
OSC Frequency
fOSC
1.0
3.0
V
2.0
3.0
kHz
VCC=12 V, R=33 kn, C=0.033 p.F
393
t.)
E
c::(
E
I
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C
~:J
tlD
g2
10
o
>.
'.;J
C.
a.
e
,,'/
:J
(.)
200
//
c
(.)
en
I
250
Q)
5
,
150
~
+-'
,,/
100
I
50
..J
4
8
./1/
:J
g
12
16
~
20
0
/
//
:J
.so
o
/'
C\l
(/)
/""
!:?
/v
/"
L
5
10
15
20
25
IOL(K) - Channel Selection Output Current - mA
Vee - Supply Voltage - V
APPLICATION CIRCUIT 1
15 k
VH
115 V
j.J.PC574J
+12 V
4·12 LINE DECODER
27 k
10k
4 BIT BINARY
OSC
INITIAL
UP DOWN COUNTER
SET
~--------~10~----------------------~
GND
396
,uPC1362C
APPLICATION CI RCUIT 2
EXAMPLE OF TV CHANNEL SELECTION
10 POSITION SELECTION CIRCUIT (2 POSITION IS SKIPED)
DISPLAY SUPPLY VOLTAGE
1 k
r--4~_ _- -_ _--~--~--~--~--~--~------~----~~-------------o+12V
lSS54
XlO
SR603C
X10
15 k
32 V
lSS54
r
XIO
0.01 )IF
Jl.PC574J
lSS54
XlO
_ _ _..J..-_
~PC1362C
r----l
I
ION
: 0
I
I
I
I
VL
TUNER
BAND OUTPUT
(Bottom View)
X3
l
I
I
I
I
I
L ___ J
CHANNEL
LOCK SW
L-----~~~~~---_+--_+~_+~----~--~~--~---+12V
'*'{AFT DEFEAT
OUT
SOUND MUTE
LED MUTE
2SA733
397
BIPOLAR ANALOG INTEGRATED CIRCUIT
JLPC1363C
ELECTRONIC CHANNEL SELECTOR
DESCRIPTION
The IlPC1363C is an electronic channel selector integrated circuit. It is capable of selecting up to 16 channels. The
output terminals are design to permit the direct driving of LED lamps or neon tubes.
This IC consists of Clock Oscillator circuit, Channel Up and Down circuit, Channel skip circuit, 4 bit Up and
Down Counter circuit, 1-16 Decoder circuit and 16 channel Output Buffer circuit, all of which are contained in a
24 pins dual in-line package.
PACKAGE DIMENSIONS
FEATURES
•
33MAX
(I.mMAX)
LED direct drive.
-
in millimeters (inches)
g1
1k=,15mA, VkSAT 150mV MAX.
•
Low power consumption.
Vcc=12V, Ic c =15mATYP.
•
Up to 16 channel selection.
•
Internal schmitt trigger circuit. (CHU, CHD INPUT)
r-- (~3~)
Power ON initial channel set.
i, - - - - - - - . 1
•
1524
(0.6)
• IlPC1360C pin compatible. (V cc=6V)
I~
•
TV, Radio etc. channel selection use.
•
Using with IlPD1986C (TX), IlPD1937C (RX),
direct address remote control system is realized.
BLOCK DIAGRAM
24 PINS DIP
K13
+ 12V--+------I
K14
K15
4-16 LINE DECODER
OSC
398
----j
4 BIT BINARY
UP DOWN COUNTER
'g~
2 25
(001)
j.lPC1363C
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Supply Voltage
VCC
15.0
V
mA
Input Current to Channel Selection Circuit
I K1 - 11 ,20-24
-5 to 50
Input Current to Control Circuit
IC15-19
-5 to 10
mA
Input Current to Control Circuit
IC13
-5 to 20
mA
* Output Voltage to Channel Selection Circuit
* Output Voltage to Control Circuit
* Input Voltage to Control Circuit
-0.5 to 50
V
V13
-0.5 to 14.4
V
V 17
-0.5 to VCC
V
VK1-11,20-24
Power Dissipation
Pd
350
mW
Operating Temperature Range
T opt
-20 to +75
°c
Storage Temperature Range
T sta
-40 to +125
°c
* At VCC= 12V
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC
SYMBOL
MIN.
9.6
TYP.
MAX.
12.0
14.4
Supply Voltage
VCC
Channel Selection Input Current
IK
15.0
Clock Oscillation Frequency
fOSC
2.0
UNIT
V
mA
kHz
10.0
ELECTRICAL CHARACTERISTICS (Ta=25 ±3°C)
CHARACTER ISTIC
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
7.0
15.0
22.0
mA
VCC=12V
mV
VCC=9.6V, IOL=15mA
10
p.A
VCC=14.4V, VOH=35V
VCC=9.6V,IOL=12mA
Supply Current
100
Channel Selection Saturation Voltage
VOL(K)
150
Channel Selection Leakage Current
IOH(K)
AFT Defeat Output Voltage
I
VOL(D)
6
V
AFT Defeat Leakage Current
IOH(D)
10
J.tA
Channel Input High Threshold Voltage
VCC:;::14.4V, VOH:;::14.4V
VTH(CH)
3.5
7.0
V
VCC=12V, Ri=15kn.
Channel Input Low Threshold Voltage
VTL(CH)
1.5
2.5
V
VCC=12V, Ri=15kn
Channel Input Leakage Current
ICH(CH)
-5
J.tA
VCC=14.4V, VIL =QV
Key I nput Current
IIH(KIl
200
J.tA
VCC:;::g·6V
Key Input Leakage Current
IIL(KIl
-10
J.tA
VCC:;::14.4V, VIL :;::QV
Skip Input Current
IIH(SK)
50
p.A
VCC:;::g·6V
Skip I nput Leakage Current
IIL(SK)
-5
p.A
VCC=14.4V, VIL =OV
OSC I nput Current
IIH(OSC)
1.5
3.0
mA
VCC=9.6V, VIH=4V
OSC Leakage Current
IIL(OSC)
10
p.A
VCC=14.4V, VIL =1.0V
1.5
2.5
kHz
"CC=12V, R=68kn., C=0.022J.t F
OSC Frequency
fOSC
399
~
o
o
~
""C
EaUIVALENT CIRCUIT
(')
...l
W
en
W
(')
K16
12V
~--
------,
I
I
I
D-16
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Q1
...-+---.-_-J
FF1
Q It----+-~--'
FF3
FF2
R Q
R
Q
Q
Q
RQ
FF4
R Q
12V
OSC
QII----f---J
CR
I
I
I
o.0221' F
I
I
I
S TlI-------'
I
I
I
I
I
I ___________________ _
L
DEF
~ ________ ~._~._.~_ ~ _______ ::~3~_N~=~1_______ ~~:~~~~3~
---0------GND
Logic Blocks consist of PMOS technology
Output. Input and OSC consist of Bipolar technology.
I
I
I
I
I
I
_...J
JLPC1363C
CONNECTION DIAGRAM (Top View)
CHANNEL SELECTION 11 (Kll)
(K12)
CHANNEL SELECTION 12
CHANNEL SELECTION 10 (K 10)
(K13)
CHANNEL SELECTION 13
CHANNEL SELECTION
9 (K 9)
(K14)
CHANNEL SELECTION 14
CHANNEL SELECTION
8 (K 8)
(K15)
CHANNEL SELECTION 15
CHANNEL SELECTION
7 (K 7)
(K16)
CHANNEL SELECTION 16
CHANNEL SELECTION
6 (K 6)
(SKP)
SKIP INPUT
CHANNEL SELECTION
5 (K 5)
(KIN)
KEY SENSE INPUT
CHANNEL SELECTION
4 (K 4)
(OSC) OSC FILTER
CHANNEL SELECTION
3 (K 3)
(CHU) CHANNEL UP INPUT
CHANNEL SELECTION
2 (K 2)
(CHD) CHANNEL DOWN INPUT
CHANNEL SELECTION
1 (K 1)
(VCC)
+12V
(GND)
(DEF)
AFT DEFEAT OUTPUT
GROUND
PIN FUNCTION
K1 '" 16
(#11'" 1, #24'" 20)
CHANNEL SELECTION OUTPUT
These are the output terminals constructed of collector-opened transistors, so they can drive potentiometers
and indicators, and key output. They have saturation voltage of 150mV at I K = 15mA, so they can drive
LEDs directly.
GND
#12
GROUND
DEF
#13
AFT DEFEAT OUTPUT
This terminal is made of open collector transistor output through a resistor of 330n.
It is used for AFT
(Automatic Fine Tuning ..... TV use) defeat, sound muting and LED indicate erasing.
Vee
#14
+12V (9.6'" 12V)
CHD
#15
CHANNEL DOWN INPUT
Usually pulled up to Vee through a resistor, Channel selector changes at positive going edge of input signal
of this terminal and the channel selector works orderly from K16 to K1.
CHU
#16
CHANNEL UP INPUT
Usually pull up to Vee through a resistor, Channel selector changes at positive going edge of input signal
of this terminal and the channel selector works orderly from K 1 to K 16. If CHU and CH D terminals put
down to ground at same time, initial channel is selected. So, it is very useful to power on channel set or
remote control operation use.
These terminals include schmitt trigger circuit and this hysteresis level is controled by external resistors.
401
,uPC1363C
VCC
0
>
<1>
bD
:J
c.
:J
Vi
OFF
Ri =
7.5kQ
Ri =
lOkQ
Ri =
15kQ
0
t
o
2
-
4
3
Input Voltage
6
5
(V)
Vi
CHU, CHD Input Schmitt Characteristic
#17
OSC
OSC FILTER
When a Channel key is pushed or skip function is operated, oscillator contained in this IC oscillate with
C, R connected to this terminal. Typical oscillation frequency is 2kHz. (R = 68k, C =
#18
KIN
O.022~F)
KEY INPUT
When channel selection key is pushed, as pushed channel is not selected, "High" level of signal is applied
to this terminal through a potentiometer. Then channel selector scans terminals of K 1""" K 16. And when
sense up this terminal, it pull down the voltage of this terminal and stop the scanning.
#19
SKP
SKIP INPUT
Usually pull up to VCC through resistor. When only 12 channels are used, conect terminals (K13"" K16)
to th is term i nal.
CHARACTERISTICS
SUPPLY CURRENT vs.
SUPPLY VOLTAGE
CHANNEL SELECTION SATURATION
VOLTAGE CHARACTE RISTIC
>
E
25
I
250
<1>
bD
.
a.
c.
,V
;j
en
I
10
V
1/
>
1/
200
c:
0
·z
~
;j
ro
en
150
~
V~
:J
c.
;j
100
0
()
I
~
9
5
":i
50
0
>
0
4
8
12
16
VCC-Supply Voltage-V
402
20
V V
0
V
5
~
V
10
I'
V
15
i.'"
20
25
IOL(K) -Channel Selection Output Current - rnA
J,lPC1363C
INITIAL CHANNEL SET and REMOTE CONTROL CIRCUIT
VCC
VCC
VCC
15k
+--"'\/\,f'v---_-i CHU
CHU
CHD
15k
L...-1V\Jf\r-.--...--f CHD
7.5k
~-"V\,f\.~_~V\l'J----f
(a) Only Channel Selection Use
CHD
(b) Remote Control Use
(c) Remote Control Use (Short Pulse Width)
APPLICATION CIRCUIT 1
ISS54X 12
1k
tlPC574J
+12Vo-~~-------------4
15k
4-16 LINE DECODER
10k
OSC
INITIAL
SET
4 BIT BINARY
UP DOWN COUNTER
GND
403
,uPC1363C
APPLICATION CIRCUIT 2
EXAMPLE OF TV CHANNEL SELECTION
12 POSITION SELECTION CIRCUIT (4 POSITION IS SKIPED)
1k
DISPLAY SUPPLY VOLTAGE
~--~--~--~--4---~--~--~--~--~----~--~------~----~,~A~------------~+12V
1SS54
X 12
SR603C
X 12
+115V
ISS54
X 12
TUNING VOLTAGE OUTPUT
1SS54
X 12
- - - - - VH
_ _ _+-_ VL
TUNER
BAND OUTPUT
~-+--- U
.u PC 1363C
r---- ,
I
I
ION
:
I
I
I
I
I
0
I
I
I
I ____ ...JI
L
CHANNEL
LOCK SW
L---+-T-+---4---~--~-r~~----
__----~--~----
I
I
t
L CHANNEL
404
DOWN KEY
2SA733
+12V
AFT DEFEAT
OUT
SOUND MUTE
LED MUTE
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1373H
REMOTE CONTROL PREAMPLIFIER
DESCRIPTION
The pPC1373H is a silicon monolithic integrated circuit designed for a remote control preamplifier of infrared signals.
This device has features of low power, high sensitivity and wide supply voltage.
PACKAGE DIMENSIONS
FEATURES
in millimeters (inches)
• Wide operation Voltage
Vee =6 to 14.4 V
• Low Power Consumption
Icc =2.S mA TYP.
• High Input Sensitivity
SO pVp-p TYP.
2.8±0.2
(0.11)
19.5 MAX.
(0.76 MAX.>
• Peak Detector
• Small Size Package
8 pin-SIP
• Minimum number of External parts required
• Designed for Use with the pPD1913C, 1943G Remote
Control Transmitter IC.
2.54±0.2
(0.1)
1.2±0.1
(0.05)
17.78
0.6 MAX.
(0.02 MAX.)
0.25
(0.01)
1.0±0.1
(0.04)
(0.7)
BLOCK DIAGRAM
8 PIN SIP
~-----------------------------------------------~~------------------------------'--------------~~---------------------'~-Vec
BIAS
PIN·Photo
Diode
-HI-
~;:
.... .s::
~~
.-
Q)
.-
>
Q)
E
...J...J
~
0
.:t(.
('Q
Q)
Q..
IlQ
c:
.0.
('Q
.s::
(/)
OUT
U1f
405
jlPC1373H
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage
VCC
15
V
Power Dissipation
Pd
270
mW
Operating Temperature
Topt
-20 to +75
°c
Storage Temperature
T stg
-40 to +125
°c
RECOMENDED OPERATING CONDITIONS
CHARACTER ISTIC
Power Supply
Input Frequency
UNIT
SYMBOL
MIN.
TYP.
MAX.
VCC
6.0
8.5
14.4
V
fin
30
50
kHz
ELECTRICAL CHARACTERISTICS (Ta=25 °c, Vcc =8.5 V, fin =40 kHz)
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
ICC
1.5
2.5
3.5
mA
Input Terminal Voltage
VIN 1
2.1
2.6
3.1
V
Input Terminal Voltage
VIN 2
3.4
4.1
4.9
V
1st Stage Voltage Gain
Supply Current
60
V;n
50
100
J.l.V
I nput Impedance
rin
60
80
kn
Output Voltage
VOL
0.5
V
IOH
2
J.l.A
Output Leak Current
Noise
lin =70 J.l.A
dB
AVL
Detection Input Voltage
40
TEST CONDITIONS
#7 - #3, Vout = 500 mVp-p
IOl = 0.1 mA, vin = 1 mVp-p
VOH=14.4 V
Input Open
Output Terminal is not fall.
TEST CIRCUITS
COl L
J.lPC1373H
C
R
CANS-4612Z TOKO INC.
5 mH 0.1 4>·2 UEW 303T
3300 pF
100 kn
OUT
51
Q
L--_ _ _ _ _ _ _~--..-~-.:...:.-_+~-----
406
VCC=+8.5 V
j.lPC1373H
1 kQ
STANDARD APPLICATION
r-~~~~--------~----------~-----'----~+--------VCC
47 JJF
VCC
PIN
Photo "Diode
PH302
OUT
COIL
126LNS-6285Z TaKa INC.
5mH O.08cP-2 UEW313T
CONNECTION DIAGRAM
TERMINAL
1
........
OUT
2
........
C3
I ntegral Capacitor
3
........
T
Tuning Coil
C2
Peak Hold Capacitor
GND
Ground
By-pass Capacitor
5
........
........
6
........
C1
7
........
IN
Input
Vce
Power Supply
4
OUT
C3
T
GND
Cl
IN
VCC
Output
8
........
PIN FUNCTION
o VCC
Power Supply
..... (#8)
Operation voltage is 6.0 to 14.4 V.
o IN
Input
. . . . . . . . . . (#7)
This input impedance is 60
kn
typical.
This input has ABLC (Automatic Bias Level Control) circuit for not saturated by violent
light, so this terminal voltage is always fixed.
. . . . . . (#3)
o T
Tuning coil
o C1
By-pass capacitor ... (#6)
This 1st amplifier has gain of 60 dB and this gain is determined of impedance of coil and
external resistor R #6
80
70
......
"
60
III
l'c
50
til)
40
I'...
...... r--.,.
~
";
"
~
2
~ 30
20
10
o
1
100
10
R:l*6-Resistor-Q
1000
Fig. 1 1st stage amplitude gain
407
,uPC1373H
o C2
Peak hold capacitor .. (#4)
The signal of tuning coil terminal is detected by peak detector circuit. In this case,
detecting level depend on input signal strength, so noise wave is suppressed.
Time constant of peak hold is changed by capacitor C#4' and sensitivity is adjusted
by resistor R#4. (see Fig. 2)
external resistor R #4
Vce= 12 V ..• 220 kG
=10 V •.• 160 kG
=8.5 V .•• 150 kG
5.0
Vee=10
Q..
~
'le=12 v
1.0
I
('t)
..
0.5
t\:
\.
\
!:!
,
"" "
\.
~
g
...
E-
v
\/
I
m
o
~
\
"
~~
/~
v
100 Vee 8.5
:l
y
........
50
-- ---
.......
.......
....... .......
'"'"'- -.........
m
-::----.....;
10m
o
50
100
150
200
250
R#4-Resistor-Q
Fig. 2 Sensitivity of peak detector characteristic
o C3
Integral Capacitor ... (#2)
Carrier wave through peak detector is integrated by this capacitor.
This time constant is determined of external resistor R#1 and this capacitor C#2.
o OUT Output
. . . . . . . . . . (#1)
Active Low output. This terminal is made of open collector transistor.
___
~ vee +6 V-l44r-V_ _ _ _ _ _ _~--------VDD
I
I
100 kQ
I
VDD
~----~---~ IN
Receiver. IC
GND
I
_______ -1I
408
,uPC1373H
CHARACTERISTIC
VCC-ICC Characteristic
AB LC I in - V in Characteristic
8
>
4
I
6
V
Q)
bO
2
<:
E
(5
I
C
3
~
::s
C,.)
------
>-
c..
c.
::s
2
4
'5
c.
~
~
:..--
.5
c::
">
2
o
5
C,.)
~~
-
./"
10
20
5:?
100
50
'200
lin -Input Current - p.A
o
15
10
5
20
VCC - Supply Voltage - V
1st Stage V in - VOL Characteristic
1st Stage fln-AVL Characteristic
5
C.
I
C.
80
2
>
I
~
Q)
bO
2
>
//
(5
500m
"iij
c::
bO
en
~
200m
::s
o
~ 100m
o
~
50m
/
V
V
/
--
a:l
"'0
~
I
60
c::
.iij
C!)
Q)
bO
~
/
40
....
II>
...J
~
20
--
.7
/1\
V \
f'.r---,
r-r-.
<:
o
10
20
40
70
100
200
fin -Input Frequency - kHz
200J-l 500 Jl 1 m
2m
5m 10m
Vin-Input Signal Voltage-V p _ p
Output Saturation VoJtage
0.8
>
I
~
0.6
Q)
bO
2
>
0.4
'5
c.
'5
(5
0
I
...J
0
>
0.2
0
V
/
V
/'
0.1
0.2
0.3
0.4
0.5
IOL - Output Current - mA
409
,uPC1373H
APPLICATION
455 kHz Ceramic Resonator
OSCI
TX
OSCO
K1 0 -
-=- 3 V
r
VOO
Infrared LED
SE303A
LMP
~PD1913C/~PD1943G
CCS
+
1 k
100 pF
100 pF
REM
KOO-K07
K1 3
2.0
Q
RX
r---------------------,
I
1 k 38 kHz
100 0
47 tiF
tiPC1373H
PH302
GNO
C1
22 Q
+
L-,J;-_-
..
- 4.7 tiF
I
I
I
I
100
kQ
1----
~--+------------+----~IN
I
I
I
03
~--02
4 bit MPU
tiP0550C etc
~--01
~--OO
I
TO.047 I
~--B3
,J, tiF...JI
_______________
~--B2
1----
B1
BO
~-~VSS
410
MOS DIGITAL INTEGRATED CIRCUITS
p,PD1913C,p,PD1943G
REMOTE CONTROL TRANSMITTER
CMOS LSI
The J1PD1913C, J1PD1943G are CMOS ICs for control circuits of infrared remote control transmitter which are available for
TV, STEREO, VTR and TOY etc.
J1PD1943G is designed to transmit 8960 commands [(32 KEY + 3) x 256 custom code] and J1PD1913C is able to transmit 736
commands [(20 KEY + 3) x 32 custom code]. For the digital commands, these use a P.P.M system of 16 bit code, which transmit the code twice (invert in the second time) to prevent operation by false codes. These ICs are designed to be received with
4 bit CPU.
FEATURES
• Low Voltage Operation ..........
• Low Power Consumption (CMOS) ...
V 00 = 2.0 to 3.3 V
100 < 1 J1A at Standby Mode
• 32 Function KEY and 3 dual Action KEY (J1PD1913C is 20 Function KEY)
• 256 Custom Codes selected by External Diode (J1PD1913C is 32 Custom Codes)
• 16 bit Pulse Position Modulated code
• High Efficiency Transmission
IR LED ON Duty 3 %
• Indicator Output
• Package
J1PD1913C
J1PD1943G
16 PIN DIP
20 PIN MINI FLAT (small size flat package)
BLOCK DIAGRAM
+
l
Infrared LED
Key Matrix
* oO°J.lPD1913C is unable to use
Customer Code Select Diode
411
,uPD1913C,,uPD1943G
IlPD1913C
CONNECTION DIAGRAM (Top View)
PACKAGE DIMENSIONS (in millimeters)
1.2
REM
Voo
t=l.
0.5±0.1 2.54
+0.15
O• 25 -0.05
OSCO
OSCI
0-15
IlPD1943G
CONNECTION DIAGRAM (Top View)
PACKAGE DIMENSIONS (in millimeters)
12.5 MAX.
KIO
Kll
x
~[~
-+tN
1.25
412
0.6 MAX.
~
9.25 MAX.
I
7.25 MAx.N.15
10.65 MAX.
10
2
20
CCS
19
KoO
KI2
3
18
Kol
KI3
4
17
Ko2
REM
5
16
Ko3
Voo
6
15
Ko4
TEST
7
14
Ko5
OSCO
8
13
Ko6
OSCI
9
12
Ko7
Vss
10
11
LMP
,uPD1913C,,uPD1943G
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Supply Voltage
Voo -VSS
4.0
V
Input Voltage
VIN - VSS
-0.3 to Voo
V
Output Current
IOH(REM, lMP)
-15.0
mA
Power Dissipation
Pd
250
mW
Operating Temperature Range
Storage Temperature Range
Topt
-20 to +75
°c
Tstg
-40 to + 125
°c
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX ..
UNIT
Supply Voltage
VOO
2.0
3.0
3.3
V
Oscillation Frequency
fOSC
400
455
500
kHz
Lamp Output Current
IOl(lMP)
rnA
1
ELECTRICAL CHARACTERISTICS (Ta=25 °c, VD D =3.0 V)
CHARACTER ISTIC
SYMBOL
MIN.
TEST CONOITIONS
TYP.
MAX.
UNIT
0.1
1.0
rnA
fOSC = 455 kHz
1
p.A
fOSC=STOP
Supply Current
IOO(OP)
Supply Current
IOD(ST)
Input High Voltage
VIH(KI)
0.7 VOO
VOO
V
Input low Voltage
Vll(Kt)
0
0.3 VOO
V
Input Pull Oown R
R(Kt)
150
600
kn
Output Current
IOH(REM)
-5
Output low Voltage
VOI-(lMP)
300
rnA
0.3
V
VOH(REM) = 1.5 V
IOl = 1.0 rnA
413
PIN FUNCTION
PIN
(tl PD1943G)
PIN
(tl PD1913C)
FUNCTION
KIO
2
2
KI1
Key Input 0 }
Key Input 1
3
3
KI2
K ey I nput 2
4
4
KI3
Key Input 3
5
5
REM
Remote Output
6
6
7
Internaly Pulldown to Vss by Resistor
Voo
Positive Supply..... 2.0 to 3.3 V
TEST
TEST Terminal ..... normally Open
Oscillator Output } Ceramic Resonator
Oscillator Input
(400 to 500 kHz)
8
7
OSCO
9
8
OSCI
Rf
o~
T
10
9
LMP
Lamp Output
11
10
Vss
Ground
12
K07
Key Output 7
11
K06
Key Output 6
14
12
K05
Key Output 5
15
13
K04
Key Output 4
K03
Key Output 3
14
K02
Key Output 2
K01
Key Output 1
17
18
VDD
Indicator for Transmission
13
16
=r
19
15
KoO
Key Output 0
20
16
CCS
Custom Code Select Input
Custom Code is selected by diode Connection
to Key Output (KoO to K07)
This terminal is usualy pull up to Voo by internal Resistor.
en
u
u
I
o
o
~
......
o
~
N
o
~
~ II~~ I~
Custom Code Select
Example ... CO to C7
414
=10
0 1 10 10
I
OPERATION OF DUAL ACTION KEY
Keys (K21 to K24) are used for preventing failure caused by mistakes.
KEY
REC KEY
PLAY KEY
K21
K22
Exsample ; Casset Tape Recorder
DO
01
02
03
04
05
06
07
K21
+ K22
1
0
1
0
1
1
0
0
K21
+ K23
0
1
1
0
1
1
0
0
K21
+ K24
1
1
1
0
1
1
0
0
(a) Operation
K21 Transmission
D5+K22-24 Transmission
K21
t>108 ms
push
•
K22-24
push
(b) No operation
I
K21 Transmission
No transmission
K21
36 ms108 ms
,..------1
K22-24
K22-24 Transmission
1..--------------1_·1
No Transmission
415
,uPD1913C,,uPD1943G
Transmission Code
0
......
(\J
M
uu (.)u
oo::tlO \.Or--.
UU UU
I: I: I~ I: I: I: I: I:
......
(\J
M
oo::tlO \.0 r--.
ClO ClO OCI ClO
I~ I: I: I: I: I: I: I~
Data Code
Custom Code
Custom Code
Leader Code
0
Data Code
Key Data Code
KEY
~
K 1
0-
N
~
~
~
~
*
K 3
*
*
K 6
*
K 7
Ko1
*
K 8
*
*
K10
*
K11
Ko2
*
K12
K13
*
*
K14
*
K15
Ko3
*
K16
K17
*
*
K18
*
K19
*
*
K22
*
K23
Ko5
*
K24
K25
*
*
K26
*
K27
K30
Ko6
*
K28
K29
Ko4
*
K20
K21
KoO
*
K 4
K 9
Ko
*
K 2
K 5
OATA COOE
CONNECTION
~
*
*
*
K31
Ko7
*
K32
*
07
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
03
04
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
0
01
0
1
NOTES
06
02
00
05
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
1
1
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
1
0
1
0
1
0
0
~
0
1
1
0
1
0
0
0
1
1
1
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
1
1
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
/JP01913C is unable to use
/JP01913C is unable to use
/JP01913C is unable to use
Dual Action Key Code
KEY
416
00
01
02
03
04
05
06
07
K21 + K22
1
0
1
0
1
1
0
0
K21 + K23
0
1
1
0
1
1
0
0
K21 + K24
1
1
1
0
1
1
0
0
NOTES
Ex. fosc = 455 kHz
Remote Output Waveforms
o
1111111111111111111111111111111
67.5
01
I
ms.1
I.
•
01·
. I
..
108 ms
..
108 ms
.
.
.--J.--+------
I I ~~~ ~ ~~ ~ ~ H~~H~~~~~~ ~ ~~ ~~ ~ ~ ~~~ ~H
9 ms
4.5 ms
Custom Code
8 bits
13.5 ms
Leader Code
Custom Code
8 bits
Data Code
8 bits
27 ms
Data Code
8 bits
27 ms
67.5 ms
o
"----20d
111111111111111111111111111111111111111111111111111111111111111111
~
I
9 ms
1
11.25 ms
1
1
0
0
1
I
2 25
.
ms
II
~'.
••
0.56 ms
Carrier
8:~
9
ms
0'
0.56
ms
~
Carrier Frequency'" ···fc =fosc/12 =38 kHz
417
MOS DIGITAL INTEGRATED CIRCUIT
tLPD1937C
REMOTE CONTROL RECEIVER
P-MOS LSI
DESCRIPTION
The IlPD 1937C is P-MOS IC for decoding the signal from receiver of remote control system for TV etc.
By using with IlPD1986C which is the transmitter control IC, this IC will provide direct channel selection signal.
When IlPC1363C is used as channel selection IC, complete remote control system can be realized. The package
is 16 pins plastic dual in-line.
PACKAGE DIMENSIONS
in millimeters (inches)
FEATURES
•
•
Capable to receive 27 commands;
Channel 1 - 20
Channel up, down
OPtion
Volume up, down
Mute on/off
Power on/off
·
kl
Capable to control 5 commands directly;
Channel up, down
Volume up, down
Power on/off
•
Using with IlPC1363C, direct addressing is easily realized.
•
Capable to control the vo1.ume for 31 steps.
7.62
to~
0.25 ~:~5
BLOCK DIAGRAM
16 PIN DIP
r-~~---~~---------------------~-------------------------+12V
'-C~___- - - - - -
PH302....----.....
.:::-
OPTION OUTPUT
1--o-~---------
CHANNEL UP
(AND DIRECT SHIFT PULSE)
38 kHz AMP
1-0---"'"-------- CHANNE L DOWN
&
DETECTOR
VOL
t--D-_-'I/II\r--o......--
POWER RELAY
418
VOLUME CONTRO L
TO DCATT.
•
0-15
tlPD1937C
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Supply Voltage
VOD-VSS
-15.0 to +0.3
V
Input Voltage
VIN-VSS
-VOO to +0.3
V
Output Current
IOH (CHU, CHO, INI)
-5.0
mA
IOH (VOL, POW)
-10.0
mA
Power Dissipation
Pd
360
mW
Operating Temperature Range
Topt
-20 to +75
°c
Storage Temperature Range
Tstg
-40 to +125
°c
ELECTRICAL CHARACTERISTICS (Ta=-20 to 75°C, VOO=-9.6 to 14.4 V)
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply Voltage
VOO
-9.6
-12.0
-14.4
V
Supply Current
IDO
-4.0
-10.0
-20.0
mA
Input High Voltage
VIH (1-5,13)
0
-1.5
V
Input Low Voltage
VIL (1-5,13)
-5.0
VOO
V
Input Pull Down Current IlL (1 -5,13)
5.0
50
J.lA
TEST CONDITIONS
Ta=25 °c, OSCI=VSS
VOO=-12 V
Ta=25 °c, VIN=VSS
VOO=-12 V
Output High Voltage
VOH (CHU)
-2.5
V
IOH=-1.0 mA
Output High Voltage
VOH (CHO)
-2.5
V
IOH=-1.0 mA
Output High Voltage
VOH (OPT)
-2.5
V
IOH=-1.0 mA
Output High Voltage
VOH (VOL)
-2.5
V
IOH=-5.0 mA
Output High Voltage
VOH (POW)
-2.5
V
IOH=-5.0 mA
Output Low Current
IOL (1""5,13)
100
J.lA
0
Ta=25 °c, VOL =-11.5 V
VOO=-12 V
419
j.lPD1937C
CONNECTION DIAGRAM
(Top View)
PIN
420
POWIN
1
CHUIN
2
CHDIN
3
VOLUIN
4
VOLDIN
5
POW OUT
6
VSS(+12 V)
FUNCTION
8
VDD
Negative supply GND norminal
12
VSS
Positive supply +12 V norminal (9.6--14.4 V)
10
OSCI
Oscillator Input
11
OSCO
Oscillator Output
13
REMIN
Remote Signal Input
POW IN
Power ON/OFF Key Input
2
CHUIN-
Channel Up Key Input
3
CHDIN
Channel Down Key Input
4
VOLUIN
Volume Up Key Input
5
VOLDIN
Volume Down Key Input
6
VOL OUT
Volume Output
7
POW OUT
Power ON/OFF Output
14
CHU OUT
Channel Up Pulse Output and Direct Channel Shift Pulse
15
CHD OUT
Channel Down Pulse Output
16
OPT OUT
Option Output for free use.
}
455 kHz Ceramic Resonator
CSB455A (MURATA MFG. Co;) is connected
to these pins.
This output is in the form of a pulse.
Connect to CR filter.
j.lPD1937C
1) CHANNEL SELECTION OUTPUT
• Direct Channel Operation
CHU OUT
(I nitial Channel Set and)
\Channel Shift Pulse
t--_ _1_8_m_s____-t---9-m_s-----'!f-t--1.1 ms
CHD OUT
!Initial Channel Set)
shift pulse = CH number - 1
MAX. 19
• UP, DOWN Channel Operation
II
---in
I---....I
r--
CHU or CHD
OUT
/18 ms
I.
0.72 s
(Continuous Operation)
./
2) VOLUME OUTPUT
+12 V
VOL
OUT
r--------------.r
DCOUT
7
0.47 IJ.F
I::l
o
+
U
o
1
22%
Repetition frequency •.........•.•.•. 3.6 kHz
VOL Steps .....•••.•.•.•.•.•..••.•.•.•....• 31
MIN. to MAX. time .•.•...•.•...•.•... 6.85
o
-
time 0.22s /step
EXAMPLE OF INPUT AMP CIRCUIT
PH301, PH302
3.3 kn
.---.-----~--------~~~~~~----~----~~~~~~--------~--------~--+12V
IJ.PD1937C
REMIN
(# 13)
0.221J.F
2SK68A
1SS53
2SC945
2SC945
421
,uPD1937C
OUTPUT WAVE FORM
"
-....
mIill'""
INPUT {
.----,
.....
nIH'"''
11111
I
I
I
I
,..---,
~---,
:
:
I
I
I
I
REM IN
KEVIN
~
==:t9
ms
MIN.72 ms
n 'IIlIlI.II.,IIIII'!1
111111 '1 111.111111
11111111111111.11'
1 ' - - - -..... 1
108 ms
1 MAX. 22.5 msJ
I
81 ms
I
18 ms
76.5 ms
140ms
MUTE OFF
VOL OUT
INTERNAL SOUND)
(
MUTE
M\ TE ON
~~-------r------------j~;r-------------~
--------------------------r- r-______
+ ____________
POWER ON
P_O_W_E_R_O
__
FF
____________---1__
POW OUT
99
ON
J'lt ______ ~F!' __________ _
ms
-- - -- - --- ---- --- -- -----.,
__ -..1 ""-________..... __
MUTE ON
VOL OUT
-{-r--1__
~
INTERNAL SOUND)
(
MUTE
OPT OUT
APPLICATION CIRCUIT
EXAMPLE OF TV REMOTE CONTROL
TUNNING SYSTEM USING PH302.
r---------------------------------------------~------~~---12v
r-;-----------------------------------------~4r~~~~V-~v~~~~~~
J..l PD1937C and JJPC1363C.
27k
PIN Photo Diode OPTION OUTPUTQ--_--,
PH301 ,.. ___________ ,
~lt>n
I
3BkH'AMP
I
&
I
DETECTOR
~:--~~~-f--~~b;====f===~~~~-c-e-ra-m-ic--~-----------r-----------------+12V
Resonator
l00IlF
~-t------+-~--~-.
I
l------,t-----J
-c=
AC 117/100V
ON/OFF
II
47k
VOLUME
CONTROL
TO DC ATT
POW
ON/
OFF
422
CH
UP
CH
OW
VOL VOL
UP
OW
2SD471
MOS DIGITAL INTEGRATED CIRCUIT
,uPD1986C
REMOTE CONTROL TRANSMITTER
CMOS LSI
DESCRIPTION
J,LPD1986C is CMOS IC for controlling the transmitter of remote control system for TV set etc. By using with
J,LPD1987C which is the receiver control IC, the direct channel control system can be obtained. When infrared
emitting diode is used as transmitter element, this system will be very stable against any interference. The package
is 16 pins plastic dual in-line package type.
PACKAGE DIMENSIONS
in millimeters (inches)
FEATURES
•
19.4 MAX.
(0.763 MAX.)
Capable to transmit 27 commands;
Channel 1 - 20
Channel up, down
Volume up, down
R 1
(R 0.041
Mute on/off
Option *
Power on/off
* J,LPD1987C is not able to decode this option code.
•
Minimum misoperation by infrared transmission
•
Wide operation voltage range (2.2 -7.2V)
•
Low power consumption (lDD = 1 J,LA at KEY OFF condition)
-W--
2.54
to.ll 0.5tO.l
~
k-l.
0.25 ~:~
0-15
(0.0191
BLOCK DIAGRAM
CERAMIC RESONATOR
100pF ~
~ 100 pF
OSCI
Voo
OSCO
OSCILLATOR
16 PIN DIP
455 kHz
MULTIPLIER
REM
OUT
423
,uPD1986C
ABSOLUTE MAXIMUM RATINGS (Ta =25 °C)
Supply Voltage
VOO-VSS
-0.3 to +8.0
V
Input Voltage
VIN-VSS
-0.3 to VOO
V
Output Current
IOH(REM)
-10.0
mA
Power Oissipation
Pd
360
mW
Operating Temperature Range
Topt
-20 to +75
°c
Storage Temperature Range
Tstg
-40 to +125
°c
ELECTRICAL CHARACTERISTICS (Ta = -20 to +75 °c, VOO = 6.0 V)
CHARACTER ISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
6.0
7.2
V
0.3
1.0
mA
OSC=455 kHz
1.0
Il A
OSC STOP, T a=25 °c
Supply Voltage
VOO
Supply Current
IOO(OP)
Supply Current
IOO(ST)
Input High Voltage
VIH(KI)
0. 7V OO
VOO
V
Input Low Voltage
VIL(KI)
0
0. 3V OO
V
Output High Voltage
VOH (REM)
VOO-l
VOO
V
Input Pulldown Current
IlL (KI)
-10
-100
IlA
2.2
TEST CONOITIONS
IOL=-1.0mA
VIN=Voo,Ta=25°C
REMOUT CHARACTERISTIC (lOL -VOH)
VOH-Output Voltage-V
-2
-1
~----~------~----~------~------
o
~---+----+-----+----+-~'----I-1.0
«E
+-'
~---+----+-----+--+--f--+-----I-2.0
c:
~
::J
U
;
~---+----+----+--+-#----+-----I-3.0
9::J
cr...J
9
424
1-----+----7rC....-+----::I~_+---_t_--___;
-4.0
' - - -_ _ _ _~_ _ _ _.l.-...I......_ _ ____L._ _ _ _ _~_ _ _ _~
-5.0
,uPD1986C
CONNECTION DIAGRAM
(Top View)
PIN
FUNCTION
8
VSS
Ground
9
VOO
Positive supply
2.2 to 7.2 Volt.
Operating voltage is wideband
10
OSCI
Oscillator Input
11
OSCO
Oscillator Output
455 kH z Ceramic Resonator
CSB455A (MURATA MFG. Co.)
12
REM OUT
Remote Signal Output
13--16
K 10"'K 13
Key Input 0"'3
1--7
KO"'K7
Key Output 0-7
READER BITS
""""I"'"
See Fig 1 and Table 1
DATA BITS
-----,- ----T--- -T-- --T-----,
,
,
I
,
I
,
I
LSB
I
I
I
:
l
I
I
I
I
:
I
I
I
'MSB:
:
:
i
9ms
36ms
38 kHz Carrier
.1
CH1 ...... CH20, POW, MUTE, OPT """'-" Only Double Block Pulses
50% Duty
CHU, CHD, VOLU, VOLD -- •.. -- ...•.•... Continuous Block Pulses
Fig. 1
Remote Signal Output (1 Block)
425
,uPD1986C
Table 1
Data bit code
CONNECTION
426
DATA BIT CODE
FUNCTION
KIN
KOUT
KIO
KO
CH 1
DIRECT ADDRESS CHANNEL 1
0
0
0
0
0
Kll
KO
CH 2
DIRECT ADDRESS CHANNEL 2
0
0
0
0
1
KI2
KO
CH 3
DIRECT ADDRESS CHANNEL 3
0
0
0
1
0
KI3
KO
CH 4
DIRECT ADDRESS CHANNEL 4
0
0
0
1
1
KIO
K 1
CH 5
DIRECT ADDRESS CHANNEL 5
0
0
1
0
0
KI1
K 1
CH 6
DIRECT ADDRESS CHANNEL 6
0
0
1
0
1
KI2
K1
CH 7
DIRECT ADDRESS CHANNEL 7
0
0
1
1
0
KI3
K1
CH 8
DIRECT ADDRESS CHANNEL 8
0
0
1
1
1
KIO
K2
CH 9
01 RECT ADDRESS CHANNEL 9
0
1
0
0
0
K 11
K2
CH 10
01 RECT ADDRESS CHANNEL 10
0
1
0
0
1
KI2
K2
CH 11
DIRECT ADDRESS CHANNEL 11
0
1
0
1
0
KI3
K2
CH 12
DIRECT ADDRESS CHANNEL 12
0
1
0
1
1
KIO
K3
CH13
DIRECT ADDRESS CHANNEL 13
0
1
1
0
0
KI1
K3
CH 14
01 RECT ADDRESS CHANNEL 14
0
1
1
0
1
KI2
K3
CH 15
DIRECT ADDRESS CHANNEL 15
0
1
1
1
0
KI3
K3
CH 16
DIRECT ADDRESS CHANNEL 16
0
1
1
1
1
KIO
K4
CH 17
DIRECT ADDRESS CHANNEL 17
1
0
0
0
0
KI1
K4
CH18
DIRECT ADDRESS CHANNEL 18
1
0
0
0
1
KI2
K4
CH 19
DIRECT ADDRESS CHANNEL 19
1
0
0
1
0
KI3
K4
CH 20
01 RECT ADDRESS CHANNEL 20
1
0
0
1
1
KIO
K5
VOLD
VOLUME DOWN
1
1
0
0
0
KI1
K5
VOLU
VOLUME UP
1
1
0
0
1
KI2
K5
CHD
CHANNEL DOWN
1
1
0
1
0
KI3
K5
CHU
CHANNEL DOWN
1
1
0
1
1
Kll
K6
MUTE
MUTE ON/OFF
1
1
1
0
1
KI2
KG
OPT
OPTION
1
1
1
0
0
KI3
K6
POW
POWER ON/OFF
1
1
1
1
1
MSB
LSB
jlPD1986C
APPLICATION CIRCUIT
o
EXAMPLE OF 18 FUNCTION TRANSMITTER CIRCUIT
INFRARED LED
SE303A x 2
+6 V
+
:
4.7 kn
1
J.,LPD1986C
2SC945
o
1.5V
x4
2SC200 1
EXAMPLE OF CONSTANT CURRENT LED DRIVE CIRCUIT
2SC945
SE303Ax2
+
:
~I
w:::>
a:o
o
..-
U
U
o
o
(/)
CJ)
1.5 V
x4
I
o
o
>
(/)
CJ)
>
1SS53 x 2
2SC200 1
427
MOS DIGITAL INTEGRATED CIRCUIT
I1PD1987C
REMOTE CONTROL RECEIVER
P-M OS LSI
DESCRIPTION
The IlPD1987C is P-MOS IC for decoding the signal from receiver of remote control system for TV etc.
By using with IlPD1986C which is the transmitter control IC, this IC will provide direct channel selection signal.
When IlPC1360C is used as channel selection IC, complete remote control system can be realized. The package
is 16 pins plastic dual in-line.
PACKAGE DIMENSIONS
in millimeters (inches)
FEATURES
•
•
Capable to receive 26 commands;
Channel 1 - 20
Channel up, down
Volume up, down
Mute on/off
Power on/off
R 1
(R 0.04/
Capable to control 5 commands directly;
Channel up, down
Volume up, down
fl
Power on/off
•
Using with IlPC1360C, direct addressing is easily realized.
•
Capable to control the volume for 31 steps.
7_62
(0.31
0_25 ~:~5
BLOCK DIAGRAM
16 PIN DIP
r-4r~--~~--------------~------------------+12V
Vss
t-o-IN_I~------_INITIAL SET
(FOR DIRECT ADDRESS)
PH302 , . . . - - - - - - ,
~
t-o-~-------
CHANNEL UP
(AND DIRECT SHIFT PULSE)
38 kHz AMP
&
t-o-~-------
CHANNEL DOWN
~O--:-~-J\N\r--1>---
VO LUME CONTRO L
TO DCATT.
DETECTOR
I
CI
56 pF
CO
OSCO
1470 pF'--_ _ _ _ _ _ _ _ _-o-_ _ _ _ _ _ __
CERAMIC RESONATOR
455 kHz
POW
ONI
OFF
~
POWER RELAY
428
0-15
0
J,lPD1987C
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Supply Voltage
VOO-VSS
-15.0 to +0.3
V
Input Voltage
VIN-VSS
-VOO to +0.3
V
Output Current
IOH (CHU, CHO, INI)
-5.0
rnA
IOH (VOL, POW)
-10.0
rnA
Power Oissipation
Pd
360
mW
Operating Temperature Range
Topt
-20 to +75
°c
Storage Temperature Range
Tstg
-40 to +125
°c
ELECTRICAL CHARACTERISTICS (Ta=-20 to 75°C, VOO=-9.6 to 14.4 V)
CHARACTER ISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply Voltage
VOO
-9.6
-12.0
-14.4
V
Supply Current
100
-4.0
-10.0
-20.0
rnA
Input High Voltage
VIH (1--5,13)
0
-1.5
V
Input low Voltage
VI l (1--5,13)
-5.0
VOO
V
Input Pull Oown Current III (1--5,13)
5.0
50
JlA
TEST CONOITIONS
Ta=25 °c, OSCI=VSS
VOO=-12 V
Ta=25 °c, VIN=VSS
VOO=-12 V
Output High Voltage
VOH (CHU)
-2.5
V
IOH=-1.0 rnA
Output High Voltage
VOH (CHO)
-2.5
V
IOH=-1.0 rnA
Output High Voltage
VOH (INI)
-2.5
V
IOH=-1.0 rnA
Output High Voltage
VOH (VOL)
-2.5
V
IOH=-5.0 rnA
Output High Voltage
VOH (POW)
-2.5
V
IOH=-5.0 rnA
Output low Current
IOl (1--5,13)
100
J.J.A
0
Ta=25 °c, VOL=-11.5 V
VOO=-12 V
429
,uPD1987C
CONNECTION DIAGRAM
(Top View)
POWIN
1
CHUIN
2
15
CHDIN 3
VOLUIN
CHD OUT
CHU OUT
4
VOLDIN 5
12
VSS(+12 V)
POW OUT 6
11
osco
ascI
PIN
430
FUNCTION
8
VDD
Negative supply GND norminal
12
VSS
Positive supply +12 V norminal (9.6""14.4 V)
10
OSCI
Oscillator Input
11
OSCO
Oscillator Output
13
REM IN
Remote Signal Input
POW IN
Power ON/OFF Key Input
2
CHUIN
Channel Up Key Input
3
CHDIN
Channel Down Key Input
4
VOLUIN
Volume Up Key Input
5
VOLDIN
Volume Down Key Input
6
VOL OUT
Volume Output
7
POW OUT
Power ON/OFF Output
14
CHU OUT
Channel Up Pulse Output and Direct Channel Shift Pulse
15
CHD OUT
Channel Down Pulse Output
16
INIOUT
Option Output for free use.
455 kHz Ceramic Resonator
CSB455A (MURATA MFG. Co.) is connected
to these pins.
This output is in the form of a pulse.
Connect to CR filter.
,uPD1987C
1) CHANNEL SELECTION OUTPUT
• Direct Channel Operation
INI OUT
Initial Channel Set )
( (CH1) to JJPC1360C - - - '
CHU OUT
(Channel Shift Pulse)
18 ms
J---------I----~----...~~
1.1 ms
shift pulse = CH number - 1 MAX. 19
• UP, DOWN Channel Operation
II------411
CHU or CHD
OUT
118 ms
I.
0.72 s
(Continuous Operation)
2) VOLUME OUTPUT
+12V .--------------------~
VOL
OUT
47 kn
DCOUT
7
I:::J
o
+
U
0.47 JJF
o
t
22%
Repetition frequency •...•.....•.•..• 3.6 kHz
VOL Steps ................................. 31
MIN. to MAX. time ...•.....•.•.•...•. 6.8 s
o
-
time 0.22 s/step
EXAMPLE OF INPUT AMP CIRCUIT
PH301, PH302
3.3 kn
.---.----~--------~~~~~~-~----~~-=~~~--------~~--------~--+12V
+
+
10 JJF
33 JJF
JJPD1937C
REM'IN
(# 13)
100 kn
0.22 JJF
2SK68A
1SS53
I
0.1 JJF
2SC945
2SC945
2SC945
431
jlPD1987C
OUTPUT WAVE FORM
hrrrnl1
1111 ~ !;..
INPUT {
nn'111',
"'
I
I
I
I
,..---,
r---,
~---,
'1111
:
:
I
I
I
I
REM IN
KEVIN
~
~9ms
MIN. 72 ms
INI OUT
~~~~c,;EL
(
18 ms
81 ms
..............
.,;1
'.1I'"III
•• 1t1l11l1
1 !! , ,
I MAX. 22.5 ms -I
{ CHU OUT
11
I
108 ms
UP. DOWN
OUT
I I • I I .. .. 1111
CHU or
CHD OUT
63 ms
76.5 ms
MUTE OFF
VOL OUT
INTERNAL SOUND)
(
MUTE
POW OUT
VOL OUT
(
~
MUTE ON
POWER ON
'"'I ---- --(-r --------ON
-+---------------------p...;~...;:...;:;;.;.9R-~..;;.~....F-.F..._-_-_-_-_-_-_-_-_-_--+--_-_-_-_-_-_-...IjL - - - - ~
--- -- - --- - --- --- -- -----~----------------~~~~~M~U=T~E=O~N~~~~~~~~---l---------
INTERNAL SOUND)
MUTE
APPLICATION CIRCUIT
EXAMPLE OF TV REMOTE CONTROL
TUNNING SYSTEM USING PH302,
r----------------------------------------------~------~~~-116V
r-+-----------------------------------______
4-~4_--~~~TUNNING
VOLTAGE
J.l PO 1987C and J.l PC1360C.
10k
;r!
PIN Photo Diode
PH301
r-----------,
~kH'AMP
&
I
I
I
I
DETECTOR
+6V
:
1---t-------+----4---+----,
I
l __ -
---;t-----.J
-e=
AC 1171100V
ON/OFF
II
47k
VOLUME
CONTROL
TO DC ATT
POW
CH
ON/ UP
OFF
432
CH VOL VOL
OW UP
OW
2SD471
MOS DIGITAL INTEGRATED CIRC.UIT
/LPD6102G
MULTI-PURPOSE REMOTE CONTROL TRANSMITTER IC
CMOS LSI'
DESCRIPTION
The J.LPD6102G is a versatile remote control infrared transmitter (TX) integrated circuit for TV, VCR, stereo,
air conditioner and many other applications. The maximum of 34304 commands are ·available with the custom
code selection by external diodes. This enables effective control of various apparatus without interference. The
transmitting code consisting of 16 bits can be directly decoded by a 4-bit MPU, thus giving a wide applicatior).
The package is a 24-Pin MINI FLAT that is the best suited for miniaturization of apparatus.
PACKAGE DIMENSIONS (in millimeters)
FEATURES
15.3 MAX.
= 2.0 to 3.3 V
ct
Low Voltage Operation .....VDD
•
Low Power Consumption ... 100 < 1 J.LA at Standby Mode
•
64 Function KEYs and 3 dual Action KEY
o 256 Custom Codes selected by External Diode
o 16 bit Pulse Position Modulated code
o High Transmission Efficiency .. I R LED ON Duty 3 %
X
o Indicator Output
108 ms
~1".----------------1""';
I K22 -
24
1...----------......~
push
(b) No operation
K21
I
I ..
No transmission
1<21 Transmission
36 ms
< t < 108 ms
... 1
~-----------------1.~
1 K22 - 241
(e) No operation
K2 1
a.-__ _
_""'1 .36 ms < t < 36 ms
.•
-I
IK22-24I~----------------------------------------~...
(d) No operation
K21
I ..
K22-24
t> 108 ms
~I--------------~.
.. I
~--------------------------------~No Transmission
K22 - 24 Transmission
439
tlPD6102G
Remote Output Waveforms
------I
Ex. fosc = 455 kHz
KEY Input
.1r - - - ~i
I •
~!
~
I
~~s
111111111111111111111111111111111
I:
67.5 m,'08 m:
01
01
I
I
I
108 ms
I
I
,....
9 ms
4.5 ms
13.5 ms
Custom Code
8 bits
Leader Code
Custom Code
8 bits
Data Code
8 bits
27 ms
27 ms
~~ ~ ~~~ ~
~tl l l l l l l l l l l l l l l l l l l l l l l l lil 1 1
9 ms
I:
.1.
4.5 ms
13.5 ms
II j~~5
1.1~~O::
•
11M •
o
2nd
111111111111111111111111111111111111111111111111111111
9 ms
Data Code
8 bits
I
ms •
•
.1 ~25ms II
0.56 ms
Carrier
8.77
ps--J-l--. I
~
9 ms or 0.56 ms
Carrier Frequency ...... .f c = f osc/12
440
~
= 38 kHz
•••
•
1
~
1125 ms
:
t-t--.
It• - - - - . .- -
III
••
1
0
•
•
0
•
1
.1.
jlPD6102G
APPLICATION
455 kHz Ceramic Resonator
+
100 pF
100 pF
-=- 3V
l
TX
OSCI
I
OSCO
SEL VOO
LMP
,",P06102G
CCS
REM f-------<
Infrared LED
SE303A
2SC2001
KIO ....
2.0n
RX
r------------------,
1 kn
100 n
38 kHz
100 kn
1----
PH302
C2
J.lPC1373H
GNO
IN
Cl
VCC
OUT~r-~-----------+----~IN
C3
22n
+
4.7 J.lF
1----
I
1 - - - - 01
4 bit MPU
I
1
03
02
1-----
DO
J.LP0550C etc
10.0471
J.LF!
1 - - - - 83
1----
L_~--------------~
82
t---- 81
1 - - - - 80
"----I
VSS
SE303A ............ Infrared LE D
PH302 ......•...... PIN Photo Diode
pPC1373H ...•...... Preamplifier for Remote Control
RX IC .•........... TV use
PLL .... pPD1700 Series
VTR, VIDEODISC, STEREO, AIRCONTROL, OTHERS
4 bit CPU . .. pcom 43 series
J,Lcom 7500 series
8 bit CPU .... pPD8048, 8049
pPD7800 series
441
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1356C2
COMPLETE PICTURE IF Ie FOR COLOR TV
51 LICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
The
~PC1356C2
is a silicon monolithic integrated circuit for PI F section in Color Television receivers. As it contains picture
detector and sound I F detector separatedly, it can offer excelent low buzz characteristics. This IC has all functions including
picture IF amplifier (4th), picture low-level detector, sound IF detector, AFC detector, IF AGC, RF AGC and picture
amplifier.
PACKAGE DIMENSIONS (Unit:mm)
FEATURES
• As it contains picture detector and sound IF detector
27 MAX.
separatedly, it can offer excellent low buzz characteristics
for Audio Multiptex TV.
•
High input sensitivity; TYP. 32 dB~
• The AGC control range is wide; TYP. 70 dB
~~8.6
~r-------~: 10.16
:::E
• As input is differential mode, it can be used with SAW
filter.
~
ci
UU~
~
.
U U~~N
O.S±O.I"; 0.2S~g:~~ 0-15·
BLOCK DIAGRAM
22 PINS
-y
RF AGC
REVERSE? 17
t--------tll,.J\.. PICTURE
'-V OUT
5
SOUND TRAP
442
¢
SIF
OUT
,uPC1356C2
TV BLOCK DIAGRAM
,uPC1356C2
ANTENNA
SOUND
DET.
SIF
AMP.
CHROMA
AMP.
SYNC
SEP.
SOUND
OUT
SPEAKER
COLOR
DEMO.
COLOR
SYNC.
CONNECTION DIAGRAM (Top View)
SIF DET COIL
STABLE VOLTAGE
SIF DET COIL
2
21
CAPACITOR
GND
3
20
CAPACITOR
MUCHING COIL
4
19
PIF INPUT
SIF OUT
5
18
PIF INPUT
PICTURE DET COIL
6
17
RF AGC OUT (REVERSE)
AFT COIL
7
16
RF AGC DELAY
AFT COIL
8
15
AGC TIME CONSTANT
PICTURE DET COl L
9
14
KEYING PULSE INPUT
AFT OUT
10
13
SUPPLY VOLTAGE
PICTURE OUT
11
12
IF AGC REF. LEVEL
443
,uPC1356C2
ABSOLUTE MAXIMUM RATINGS (Ta
±3 °C)
V13MAX.
15
V
Terminal 22 Current
122MAx.
100
rnA
Terminal 14 Current
114MAx.
±3
mA
900 (Ta ~ 65°C)
mW
Power Dissipation
Pd
Operating Temperature
T opt
-15 to +65
°c
Storage Temperature
T stg
-40 to +125
°c
ELECTRICAL CHARACTERISTICS (Ta
CHARACTERISTIC
444
= 25
Supply Voltage Pin-13
SYMBOL
= 25°C, Vcc = 12 V, RA = 120 fl, fp = 58.75 MHz)
TEST
CIRCUIT
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
Total Supply Current
ICC
1
55
70
90
rnA
Zero Carrier
Termina~
13 Current
113
1
20
30
40
rnA
Zero Carrier
Terminal 22 Current
122
1
35
40
50
rnA
Zero Carrier
Terminal 22 Voltage
V22
1
6.6
7.2
7.6
V
Maximum RF AGC Voltage
9.0
9.2
10.0
V
V 16 = 7 V
0
0.5
V
V16 = 0 V
V17H
1
Minimum RF AGC Voltage
V17L
1
Terminal 11 Voltage
V11
1
3.7
4.1
4.7
V
Terminal 10 Voltage
V10
2
5.0
6.5
7.7
V
Maximum AFT Out Voltage
11.0
V
V7 = 4.8 V
Va=5.1 V
1.0
V
V7 = 5.1 V
Va = 4.8 V
41
V10H
2
Minimum AFT Out Voltage
V10L
2
Input Sensitivity
Vi (Jim)
3
25
32
dB.u
fm = 400 Hz m=40% Vo = 0.8 Vp.p
AGC Range
G.R
3
60
80
dB
fm = 10 kHz m=40% Vo = 0.8 Vp-p
Maximum I nput Voltage
Vi(MAX)
3
100
55
mVr.m.s.
fm = 10 kHz m=40% Vo = 0.8 Vp-p
Signal To Noise Ratio
SIN
3
50
SI F Output Voltage
Vo(SIF)
3
12
Carrier Leak
CL(OET)
3
dB
25
50
mVrms
5
50
mVr.m.s.
13
MHz
3
5
%
DP
3
5
deg
AFT Control Sensitivity
Sf
3
50
150
AFT Band Width
BW
3
0.2
1.1
PI F Input Resistance
Ri
4
1.5
kn
PIF Input Capacitance
Ci
4
3.5
pF
Picture Frequency Response
fC
3
Differential Gain
DG
Differential Phase
5
2.1
fm = 15.75 kHz m=80% Vo = 1.5 Vp-p
= 10 mVr.m.s.
Vi
fm = 400 Hz m=40% Vi(P) = 3 mVr.m.s.
fs = 54.25 MHz Vies) = 300 .uVr.m.s.
Vi
= 20 mVr.m.s.
m=40% Vi =20 mVr.m.s.
fp = 58.75 MHz Stair Step fm = 3.58 MHz
m=85%
14 % Modulated White To Sync Level
Vo(DET) = 1.4 Vp-p
mV/kHz
fm = 400 Hz m=40% Vo = 0.8 Vp-p
MHz
fm = 400 Hz m=40% Vo = 0.8 Vp-p
JlPC1356C2
TEST CIRCUIT 1
12 V
,uPC1356C2
*:
0.01 JJF
100 k
*
TEST CIRCUIT 2
120
* *
:jc
*
12 V
100 k
* : 0.01
JJF
445
~
~
m
1:::
TEST CIRCUIT 3
""CJ
"en
"
~
SWI
2
MANUAL GAIN CONT
W
2
en
10 kVR
N
120
A)
,
Q
,+
47 pF
10 k
J
51
I
I
~n!
i
""T"
..,....
..,....
I
12 V
*
J.
J
..,....,
I
*
5 kVR
IF. AGC REF. LEVEL
*
I
________ LI _________ _
SHIELDING
,uPC1356C2
I
I
11
1 k
2.2 k
100 k
1 k
*
1
[SG2
h
175
1
820
*
J
1 k
*
4.5 MHz
CERAMIC
FILTER
* : 0.01
#IF
,uPC1356C2
TEST CIRCUIT 4
120
RX
METER
50 ,uF
12
12 V
,uPC1356C2
11
*:
0.01 IlF
SWITCH TABLE
ICC
113
122
V22
11.12
.1.1
V17H
V17L
V11
V'O
V'OH
TEST CIRCUIT
1
1
1
1
1
1
1
1
1
2
2
2
SWl
1
1
1
1
1
1
2
1
1
-
-
-
SW2
-
-
-
-
-
-
-
-
-
SW2
OFF
2
2
SW3
-
-
-
-
-
-
-
-
-
OFF
AA'
BB'
METER
A,
A2
A3
A4
A4A5
A4A5
V,
V,
V2
V3
V3
V3
ITEM
V'OL
1
ITEM
Vj(Jm)
G.R.
VjMAX
SIN
Vo(SIF)
CL(DET)
fC
D.G.
D.P.
Sf
B
Rj
Cj
TEST
CIRCUIT
3
3
3
3
3
3
3
3
3
3
3
4
4
SWl
1
1
1
2
1
2
2
2
2
2
2
-
-
SW2
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
ON
-
-
MGC
GAIN
MIN
MGC
GAIN
MIN
MGC
GAIN
MIN
MGC
GAIN
MIN
MGC
GAIN
MIN
MGC
GAIN
MIN
SG2
SG2
SG2
SG2
SG2
SG2
-
-
MGCVR
SG
METER
VARIABLE
SG,
OSCILLO
SG,
OSCILLO
SG,
OSCILLO
SG,
NOISE
METER
SG,
OSCILLO
VTVM
DIGIT DIGIT
RX
RX
DG/DP DG/DP
VOLT VOLT
OSCILLO
METER METER
METER METER
METER METER
447
jiPC1356C2
TYPICAL CHARACTERISTICS (Ta = 25 °C)
PICTURE DET. OUTPUT VOLTAGE, SIN, CARRIER LEAK
2.0
0
0
r
I
I
1
I
OJ
"0
I
Q)
be
vi
E
~
oS
(5
>
E
I
..>t! 1.0
til
Q)
...J
....
OJ
:::l
"0
J5 -5
~-5
.......
"-
,,
....
...
I
I
Q)
0
Q)
'E
~
.au
til
u
I
...J
u
INPUT VOLTAGE
1\
I J J
Vo;fp=58.75 MHz
L
fm= 400 Hz. m= 40 %
Vo= 0.5 Vp- P
ust
At
I f
L .I.
I
Cl;Ip= 58.75 MHz CW
/
~
0
en
VI.
S/W ;Ip = 58.75 MHz
fm=15.75kHz m=80 %
Vo= 1.5 Vp-p Adjust
i:i:
I
0
~-1O
0 -10
o
60
40
20
80
100
Vi-Input Voltage-dB,u
AFT OUTPUT TERMINAL VOLTAGE vs. CARRIER FREQUENCY -
=;-
1
\
10.0
11\
Q)
be
oS
\
\
g
roc:
l 10
.~
Q)
I-
:J
5.0
Cl.
I
o
1
\'2
\
1\
"5
I-
u...
ex:
I
o
->
~
o
58.6
58.7
58.8
58.9
fp- Carrier Frequency- MHz
AFT OUTPUT TERMINAL VOLTAGE vs. CARRIER FREQUENCY -
=;-
10.0
Q)
be
oS
13)/
~V
;§!
roc:
.~
fo
Q)
I-
....
:::l
.e:::l
5.0
o
I-
u...
ex:
I
o
/
->
/
~
o
56
57
58
59
60
fp- Carrier Frequency - MHz
448
61
2
STANDARD APPLICATION CIRCUIT
KEYING PULSE
6.8k
Vcc= 12 V
U
47 J.l
5 k
0.01 J.l
B
\r
RF AGC
DELAY AMP.
RF AGC
REVERSE
8.2 k
NOISE
FILTER
IF AGC AMP.
~VIDEO
PICTURE
AMP.
OUT
r
SIF
DET.
.--J\N\r-----.+ AFT
OUT
PIF
IN
3rd
IF AMP.
4th
IF AMP.
PICTURE DET. COIL
47 J.l
0.01 J.l
A-
T
m-
+
SIF DET.
MUCHING COIL
47
AFT COIL
B
In case of
Peak Type AGC
+
RA
120
~
""C
o
~
w
en
0)
o
~
~
CD
N
JLPC1356C2
COIL SPEC. (COIL MAKER; TaKa, INC.)
COIL DRAWING
(BOTTOM VIEW)
ITEM
SIF DET. MUCHING COIL
~
3
1
13 TO
13 TO
TV4BVC - 21135AFO
C
[gJ
4-6
6-2
2-4
l-A
A-B
C
5% T
2% T
3T
4% T
3T
100 pF
0.2t/> 2 UEW
A-81.0t/>TINNEDWIRE
TYPE No.
10 KN
10 KN
180PNA - 10212BS
TURN
96 ± 20 %
6T
95 ± 20 %
6%T
4-6
WIRE
0.16 t/> 2 UEW
0.16 t/> 2 UEW
TYPE No.
10KN
10KN
COIL No.
180PNAS - 10232ALR
180PNAS - 10235ALR
MUCHING C.
33 pF
33 pF
NO LOAD O.
TURN
12
V
PIF Input Voltage
Vi
10
mVr.m.s.
*5
V p _p
V
*Keying Pulse
---JJ;-----
5 Vp-p
V"------ - ------ ----- Comparative
----------
Level
5T
1% T
3%T
0.23 t/> 2 UEW
VCC
R F AGC Voltage
97±20 %
93±20 %
6-1
6-3
6-4
Supply Voltage
Keying Pulse
450
40pF
4-6
STANDARD USING CONDITION (Ta = 25°C)
a V ------------
180PNA -10223BS
33 pF
NO LOAD O.
WIRE
3
7% T
3% T
4T
5% T
5T
100 pF
O.2t/> 2 UEW
A-B 1.0 t/> TINNED WIRE
MUCHING C.
AFT COIL
7 V
4-6
6-2
2-4
l-A
A-B
C
WIRE
COIL No.
®
0
CD
=45 MHz SPEC.
TV4BVC - 21132AFO
6
PICTURE DET. COIL
fp
COIL No.
TURN
C
= 57 MHz SPEC.
TYPE No.
4
2
fp
6-1
6-3
6-4
7T
2%T
4T
0.23 t/> 2 UEW
JLPC1356C2
COMPONENTS LAYOUT
• P.C. BOAD PATTERN
o
o
COMPONENTS (For fp = 57 MHz)
SYMBOL
RI
R:z
R3
R4
Rs
R6
R7
Rs
R9
RIo
R11
Rll
RI3
RI4
R ls
RI6
RI7
R is
RI9
SPEC.
220 n
120 kn
1.8 kn
100 kn
100 n
470 kn
6.8 kn
10 kn
10 kn
8.2 kn
5kn
3.9 kn
2.7 kn
120 n
220n
1 kn
47 n
200 n
560n
SPEC.
SYMBOL
CI
C:z
C3
C4
Cs
C6
C7
Cs
C9
CIO
Cl1
Cll
CI3
0.47 p.F
0.01 p.F
0.01 p.F
0.01 p.F
47 p.F
0.01 p.F
20 pF
20 pF
20 pF
0.01 p.F
33 pF
0.01 p.F
47 p.F
VR I
VR:z
5 knoB
5 knoB
TI
T:z
T3
T4
TO-KO
TO-KO
TO-KO
TO.KO
10V
16V
10V
TV4BVC-21132AFQ
180PNA-l0212BS
180PNAS-l0232ALR
MTKAC-19951Z
451
BIPOLAR ANALOG INTEGRATED CIRCUIT
pPC1366C
VIDEO IF PROCESSOR FOR BjW TV
DESCRIPTION
The pPC1366C is a silicon monolithic integrated circuit designed for VIF section in B/W television receivers.
This IC has all functions including video IF amplifier, video low-level detector, RF .AGC, IF AGC and noise
canseller.
This IC is encapsulated in 14 pin dual in-line package with heat tab.
FEATURES
• High input sensitivity; TYP. 30dBp.
• It can be used both of keyed type AGC and peak type AGC.
• It can be operated with the power supply voltage above 7V.
• Since the video detector has wide bandwidth, it's suitable for the sound carrier frequency of 4.5, 5.5,
6.0, 6.5MHz.
• As input is differential mode, it can be used with SAW filter.
• All functions for VI F stage are provided by this single chip IC and this IC will realize reduction of
assembly cost as well as reduction of number of external components.
CONNECTION DIAGRAM (Top View)
TAB
7
SUPPL Y VOLT AGE(1)
6
TUNER AGC OUTPUT
PACKAGE DIMENSIONS in millimeters (inches)
~:
;;;. 08 D;~",;o", ",~.",
19.4MAX. (0.763)
24.6MAX.(O.968)
CAPACITOR
10
5
RF AGC ADJ. VR.
CAPACITOR
11
4
AGe TIME CONST.
SUPPLY VOLTAGE(2)
12
3
VIDEO OUTPUT
GND
13
2
KEYING PULSE INPU,
DETECTOR COIL
14
1
DETECTOR COIL
I O.5(o.oi)
--ti- I
2.54 2.54 4.44(0.175)
12
(0.047)
(O.1)(O.1~
(0.195)
452
"',,
unless otherwise specified.
,uPC1366C
BLOCK DIAGRAM
KEYING PULSE
TUNER AGC
1.u
VCC=12V
SIF
1
10k
+
4.5MHz
TRAP
NOISE
CANCEL
RF AGC
VIDEO
AMP
TAB
IF AMPLIFIER
LOW LEVEL
DETECTOR
(PEAK AGe)
*
(MANUAL GAIN CONTROL)
;;2 OPEN
;; 12
TUNER
DETECTOR COIL SPEC
TOKO 10KN TYPE 180PNA - 1021285
frequency : 57MHz (C = 33pF±3%)
No load Q : 96±20%
Turn
: 4-6 6T
Wire
: 0.16ct> 2UEW
®
®
CD
453
pPC1366C
ABSOLUTE MAXIMUM RATINGS (Ta=2S0C)
Supply Voltage Pin-7
V7
Input Signal Voltage
Vs Vg
15
V
3
Vp-p
Power Dissipation
Pd
875 (Ta = 75°C) Free Air
Operating Temperature
T opt
-20 to +75
°c
Storage Temperature
T stg
-40 to +125
°c
VCC = 12V,
Ta = 25±3°C
mW
)
ELECTRICAL CHARACTERISTICS ( f= 58.75MHz, fM = 15.75kHz
CHARACTER ISTIC
Total Supply Current
454
SYMBOL
ICC
Input Sensitivity
Vi (sens)
Maximum Input Voltage
Vi(max.)
MIN.
TYP.
MAX.
UNIT
40
SO
60
mA
17+112, RA=1S0n
dBJL
MOD =SO%, VO = 1.4Vp-p
dBJL
MOD=SO%, -1dB Point
MOD = SO%, vi = 3mVr.m.s.
30
3S
100
Video Output Voltage
Vo
1.0
1.4
1.7
Vp-p
Video Output DC Voltage
Vo.
3.3
3.S
4:3
V
Signal to Noise Ratio
SIN
40
SO
RF AGC Voltage (High)
V6H
S
9
RF AGC Voltage (Low)
Val
0
Differential Gain
TEST CONDITIONS
. No Signal
dB
MOD=SO% - 0%, vi=3mVr.m.s.
11
V
VS=OV
O.S
V
VS=7V
D.G.
10
%
Stair Step fM =3.SSMHz
Differential Phase
D.P.
10
deg
Stair Step fM = 3.SSMHz
Video Detector Band Width
BW
MHz
-3dB Point
Input Resistance
Rin
1.S
kn
Input Capacitance
Cin
3.3
pF
S.S
jlPC1366C
TYPICAL CHARACTERISTICS (Ta =2SoC)
INPUT SENSITIVITY vs.
SUPPLY VOLTAGE
VIDEO DETECTOR OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
a.
::t
CD
"C
I
f= 5S. 75MHz. f M=15.75 kHz
MOD=8O%. RA = 150Q
90
a.
>
I
~ 1.5
2
SO
I
Z' 70
.:;
:p
'iii
c:
..,
U)
"0
50
a
/
:l
Co
\
1\
30
1.0
/
'-
\.
.E
B
u
!!l
.-:..--- f-
c3
III
~ 20
~
~-
/
>
60
"5Co 40
.!....
v
JV
I
0.5
o
il
QJ
"C
10
V
:>
f= 5S.75MHz. fM= 15.75kHz
MOD=SO%. RA = 150Q
I
o
0
~
10
15
vee-Supply Voltage-V
5
0
10
15
5
vee-Supply Voltage-V
SIN vs. INPUT VOLTAGE
o
-10
f=5S.75MHz. f~= 15.75kHz
MOD=SO%-O%
Vi =3mVr.m.s .• RA = 150Q
,
\
\
-20
\
\
I\.
-40
\
;"
-50
20
"
........
40
60
80
Vi-Input Voltage-dBJ.l
100
VIDEO DETECTOR OUTPUT VOLTAGE ATTENUATION vs. FREQUENCY
-
o
:l
~r\
-5
.9:::J
o!g
0QJ c:1
0
c3~
g
~
"
o
...
:,
f=5S.75MHz
MOD =40%
Vi = 3mV r.m.s.
:l
~ -lQ I-
:2:::
><
I
l-
I-
<
-15
0.1
1.0
10.0
f-Frequency-MHz
455
81 POLAR ANALOG INTEGRATED CI RCUIT
I1PC1353C
2.4 WATTS AUDIO AMPLIFIER, SIF AMPLIFIER
AND DETECTOR FOR TV
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTION:
The IJPC1353C is a silicon monolithic integrated circuit designed for SI F and Audio section in television receivers.
This IC has all functions including sound I F Amplifier, FM Detector, DC volume control circuit, Audio Output
amplifier with 2.4 Watts output power and voltage regulator.
This IC is encapsuiated in 14 pin dual in-line package with heat tab.
FEATURES:
1. All functions for SI F and audio stage are provided by this one-chip IC and this IC will realize reduction of
assembly cost as well as reduction of number of other components.
2. Audio output power is controlled by electronic attenuation circuit which operate at DC. Therefore, unnecessary radiation, oscillation etc. are eliminated. Due to DC control, shielded wire is not required and
variable resistor will be placed anywhere required.
3. Electronic attenuator has enough attenuation (Typ. 80dS) by the adoption of squelch circuit.
In addition, as attenuation characteristic is same with resistance change of variable resistor, suitable variable
resistor will be selected easily.
4. As Peak differencial detection method is adopted for FM detection, outside circuitry can be very simple and
circuit adjustment will be very easy.
5. As operation voltage (Vcc) range for output stage is very wide (9-18V), suitable Vcc can be freely determined
for required output level.
For example:
Po
Po
= 2.4W
= 1.2W
at Vcc = 18V, RL
at Vcc = 12V, RL
=8
=8
Ohms
Ohms
jlPC1353C
PACKAGE DIMENSIONS in millimeters (inches)
CONNECTION DIAGRAM (Top View)
IR~'04Jf; ; ;; ;:E-D;men';on,a,.tVPkal'~I",
unless otherWise specified.
SOUND POWER OUT
8
7
SOUND POWER INPUT
I-'=--=t9.4MAX.,O.763J
BOOTSTRAP CAPACITOR
9
6
DE COUPLING CAPACITOR
I
SUPPLY VOLTAGE FOR SOUND PO'MR
STAGE
FEED BACK CAPACITOR
10
5
SUPPLY VOLTAGE FOR SIF STAGE
"
4
SIF DETECTOR OUTPUT
3
DE EMPHASIS CAPACITOR
2
FM DETECTOR COIL
12
SIF INPUT (HOT END)
SIF INPUT (COLD END)
13
VOLUME CONTROL
14
I
I
(062~61
24.6MAX.(0.968)
:
I
0.5± 0.1
(0.02)
J.,
I
I 0.5(0.02)
-rr
i
Il
---ill=
+0 1
1 2 2.54 2.54 4.4~(0.175) 0.3-0:05
(0.012)
(0.047)(0.1 )(0.1) 4.961
1(0.195)1
FM DETECTOR COIL
,
l
~
"
7.62
(0.3)
-
-\-
BLOCK DIAGRAM
RB
Vee
~------------------------------------------------~~~~--~~~~~----~
+
4.71-1F
220l-lF
-------,
r----- ------------I
I
I
I
I
I
I
I
I
L-------T-------- ,
I
I
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Supply Voltage Pin 10
Vl0
20
V
Supply Current Pin 10
110
1
A
Supply Current Pin 5
15
100
mA
Input Signal Voltage
Vi
3
Vp_p
Power Dissipation
Pdl
Power Dissipation
Pd2
1.4*
Operating Temperature
Topt
-20 to +75
Storage Temperature
Tstg
-40 to +150
0.8 (Ta=75°C) FREE AIR
W
W
* PRINTED CIRCUIT COPPER AREA 50x50 mm 2
457
tl PC13 53C
ELECTRICAL CHARACTERISTICS (Ta=25±3°C)
1
IF STAGE
VCC=12V
( f o=4.5MHz
CHARACTERISTIC
RB=100n Rg=50n V14;;:::1.3V)
fM=400Hz
f=± 25kHz
SYMBOL
Pin 5 Voltage
MIN. TYP. MAX.
UNIT
TEST CONDITIONS
V5A
7.5
8.0
8.5
V
Pin 5 Voltage
V5B
7.5
8.0
8.5
V
VCC=18V RB=330 n
Pin 10 Current
Il0A
14
19
24
mA
NO INPUT SIGNAL
Pin 10 Current
, 110B
16
28
35
mA
VCC=18V RB=330n
NO INPUT SIGNAL
200 400
/JVr.m.s.
VOAF(Vi=10mVr.m.sJ
-3dB
360
mVr.m.s.
Vi=10mVr.m.s.
0.7
%
Vi=10mVr.m.s.
I F Limiting Voltage
Vi(Jim)
Detector Output Voltage
VoAF
Detector Distortion
T.H.D·l
AM Rejection
AMR
-40 -50
dB
AM MOD 30% fM=
400Hz Vi=10mVr.m.s.
Maximum Attenuation
ATT max
-60 -80
dB
V14=OV
300
VCC=12V
( f=400Hz
RB=100n
RG=600n
CHARACTER ISTIC
SYMBOL
MIN. TYP. MAX.
Sound Stage Voltage Gain
GVAF
33
2
SOUND POWER STAGE
PoA
Sound Output Power
UNIT
TEST CONDITIONS
dB
Vi=30mVr.m.s.
1.2
W
T.H.D.=10%
2.4
W
VCC=18V RB=330n
T.H.D.=10%
37
0.9
Sound Output Power
PoB
Sound Output Distortion
T.H.D.2A
0.6
2.0
%
Po=0.5W
Sound Output Distortion
T.H.D.2B
0.5
2.0
%
VCC=18V RB=330n
Po=0.5W
1.5
4.0
%
Po=O.5W
3
2.0
41
IF STAGE + SOUND POWER STAGE
Over All Sound Output Distortion
T.H.D·3
Vi=10mVr.m.s.
4
458
REFERENCE DATA
UNIT
TEST CONDITIONS
200 --210
mA
T.H.D·2A=10%
110
270 -- 280
mA
T.H.D.2B=10%
Sound Output Power
PoA'
1.1
W
T.H.D.=3%
Sound Output Power
PoB'
2.0
W
VCC=18V RB=330n
T.H.D.=3%
Sound Stage Band Width
BW
50 '" 50k
Hz
-3d8
CHARACTER ISTIC
SYMBOL
Pin 10 Current
110
Pin 10 Current
PIN INPEDANCE
fo=4.5 MHz
R
C
5.5 MHz
R
C
Pin 12 IF Input
2
9.5
2
9.4
1.9
9.4
1.9
9.4
kn/pF
Pin 1 Detector Connect
2.4
6.3
2.4
6.2
2.4
6.1
2.4
6.1
kn/pF
Pin 2 Detector Connect
11.5
9
9
8.5
8.5
8.3
7.8
8.1
kn/pF
6.0 MHz
R
C
6.5 MHz
R
C
UNIT
jlPC1353C
TEST CIRCUIT
j---..-o Vcc 12V or
O.OlI'F
18V
f
~
SI
IF SG .......
fo=4.5MHz
+
220l'F
QACVOLT
\:!::!J METER
I')(F\ DISTORTION
'-:::.) METER
CHARACTERISTICS
POWER DISSIPATION vs.
AMBIENT TEMPERATURE
SUPPLY CUR RENT vs.
SUPPLY VOLTAGE
3.0
25
::
~Ox60(mm2)
I
c:
.gco
2.0
5Ox50( mm 2
1"-
Co
.jJi
o
FRJE AIJ
~
o
'"
~ 1.0
~
E
I
c:
e
:;
a.>g.
Vl
~~
~
,
,
l\.
"
J
15
10
V
0
~
J
5
V
" ~
'~
0
-20 0
25
50
75
100 125
Ta -Ambient Temperature-OC
o
o
150
2
~
~
:J
'5
-r- -1---
~-40 0 200
I
~
Qi
-50
~
100
u.
0 ...:r::::
\-- i
V
~
~
V
j...-:"
vII
~
,;1-'
X
Co
~
20
~
YoU
i-3D ~ 300
Q)
18
1000
>
-20 E 400
~
I
~
6
8
10 12 14 16
Vce - Supply Voltage - V
.;
~
a:
4
DETECTED OUTPUT VOLTAGE vs.
FREQUENCY DEVIATION
-10 u; 500
I
Rs=300n
...V
DETECTED OUTPUT VOLTAGE, AM REJECTION,
TOTAL HARMONIC DISTORTION vs. INPUT VOLTAGE
.Q
L
j
I
~
V
l(
u
~~~.
..........
L
20
...
Printed Circuit Board
1.5~m~Copper thick;t = 301l
f\.. th!ck; t ':"
....... t--...
/'
V
Q)
.I.
S
Vec=12V
f=4.5MHz
MOD=30%AM
fM=400Hz I
Af=±25kHz
1\
1\l'
L
800
I
,/
1\
l'
~
r-- t----...
'I'vI-'
T.H· O.l
1
104
10
Vi-lTlput Voltage-mVr.m.s.
it
Ii
/
~ 600
...
:J
~
V
:J
o
400
/
a!
E
9 200
Q)
u.
105
j
V
o
o
L
V
V
Vce=12V
f=4.5MHz r MOD=30%AM
Vi=l mVr.m.s._
/
±20
±40
±60
±80
f-Frequency Deviation-kHz
459
DETECTED OUTPUT VOLTAGE vs.
ELECTRONIC ATTENUATER
TERMINAL VOLTAGE
DETECTED OUTPUT VOLTAGE, ELECTRONIC
ATTENUATER TERMINAL VOLTAGE vs.
ANGLE OF ROTATION (A CURVE VOLUME)
~
,,;500
E
500
en
~
Ql
~
E400
I
&
!9
;g3oo
...
:I
---,
Vcc=12V
f--- ....c..: =4.5MHz
f
f -MOD=30%AM
II
fM=4ooHz
M=±25kHz
f-Vi=l mVr.m.s.
-
9:I
°200
N
Vl'Y
It!
. ///
Q)
0100
-----
I
u.
<{
-
a
>
0
.-""
~
o
~
'0
>
/
~
1.5
f
'E
~
I
;g3oo
:I
c:
1.0 ~
OUTPUT POWER vs. INPUT VOLTAGE
(AUDIO AMPLIFIER STAGE)
5.0
-
/
W
270
/
/
/
o
0.5 ~
. /.....VOAF
180
Angle of Rotation - DEG
E400
I
~
~<0
J
'l
90
:>
Vcc=12V
f=l kHz
f=l kHz
I- T.H.D.-10%
1~
1~
1~
V1AF - Input Voltage - p.Vr.m.s.
105
o
o
POWER DISSIPATION vs.
OUTPUT POWE R
0.5
I.
I
~
1.0
0.5
460
/
1/
1.5
~
o
/
/ ..,,-
1/
/
o
0.5
-
MOD=30%AMfM=4ooHz
M=±25kHzYi=l rpVr·rr· s.
m -2
--
a: -5
~~VRs=loon
-....,
1.0
1.5
2.0
Po-Output Power -W
V
-1
J.f=4.15MH~
/"
l2.0
'iii
C
~
L J.
....,,-i-"'1
o
. . . . . .V
1.5
1.0
Po-Output Power - W
2.0
2.5
FREQUENCY RESPONSE
(AUDIO AMPLIFIER)
Vcc=18V Rs=3oon
2.5
/
,.,....V
3.0
~c:
:;
/
V
'I
10
Vcc=18V
J
II
o
I
I
I
2.5
l'
VCCl12~Uill
-
Vi=30mVr.mt
"-1"\
\
-3
5!c:
0-4
\
I
,
~
-6
-7
10
102
103
f - Frequency - Hz
1~
105
JlPC1353C
PRINTED CIRCUIT BOARD AND COMPONENTS TABLE
AT ONE SUPPLY POWER
~YSTEM
NEC
,uPC1353C
.<~
B
<
O.
VOLUME
GND
SYMBOL
CHARACTER ISTIC
Cl
CERAMIC
0.0221lF
C2
CERAMIC
10 pF
C3
CHEMICAL
100IJF 10V
C4
CHEMICAL
330IJF 25V
C5
CHEMICAL
100IJF 25V
C{)
CHEMICAL
2201lF 25V
C7
CHEMICAL
471lF 10V
Ca
CERAMIC
O.OlIJF
Cg
CHEMICAL
100IJF 10V
ClO
CHEMICAL
4.71lF 10V
Cll
CERAMIC
0.0151JF
C12
CERAMIC
0.1IJF
VR
5k-A Curve
Tl
INPUT COIL
T2
DET. COIL
AT TWO SUPPLY POWER SYSTEM
SYMBOL
CHARACTERISTIC
Rl
22k 1/4W
R2
2701/4W
RB
loon
or 330n 1/2W
461
pPC1353C
COIL SPEC.
INPUT COIL
DETECTOR COl L
FOR
FOR
4.5MHz
~
4.5MHz
3-4
20T
1-6
5T
C
82pF
fo
4.5MHz
au
110±20%
®
~
0.14> OUEW
5.5MHz
1-3
24T
C
82pF
fo
4.5MHz
au
108:t20%
Coil Material
0.14>
28T
1-6
4T
C
82pF
fo
5.5MHz
au
59±20%
1-3
29T
C
76pF
fo
5.5MHz
au
49:t20%
CD
0
Coil Material
Coil Material
0.14> OUEW
0.14> OUEW
MOUNTING HEATSINK
15
LO
N
The method of mounting the heatsink show below, in the case of
heatsink need, when sound output power will be larger and the
heatsink don't directly mount with IC's TAB.
Heat sink
Printed Circuit Board
462
OUEW
FOR
5.5MHz
3-4
®
~
0
Coil Material
FOR
~
CD
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1382C
TV SOUND IF PROCESSOR AND ATTENUATOR
DISCRIPTION
JIPC1382C is a TV sound IC. It can be operated with no adjustment, using ceramic filters externally; It contains a DC
controlled attenuator, which has wide effective area and gentle characteristic in the chainging, so it is convenient especially for
a remote controlled set.
FEATURES
•
PACKAGE DIMENSIONS
(Unit: mm)
Gentle chainging DC controlled attenuator is convenient
for remote controlled sets.
•
Operation with ceramic filters makes TV sound circuit
no adjustment completely.
o SRPP output circuit can be driven directly.
•
Muting works quickly.
•
Low distortion demodulation.
BLOCK DIAGRAM
U
Mutihg pulse
14 PINS
~~
,...----~100V
463
,uPC1382C
TV BLOCK DIAGRAM
v / / / / / / / / / '//~
V
~ ~
,uPC1382C ~
V// / / / / / / / //,
ANTENNA
~[7
AFT
SIF
DEl.
I-~
'----.......
UHF/VHF
TUNER
PIF
AMP.
~
1
t--<~
IFI RF
AGC
~
t----t~~
SIF
AMP.
~/
,/
/.
~
.~
/ / / / ./ 1/ /
~
SOUND
DET.
t--
f-
SOUND
OUT
~
PICTURE
AMP.
~
SYNC
SEP.
SPEAKER
'--
'--
V.OSC
I--
COLOR
DEMO.
CHROMA
AMP.
H.OSC
AFC
COLOR
SYNC.
t--
~
COLOR f-OUT
rf--
CRT
H.DRIVE
H
Y.ORIVE
I--
H.OUT
t--
f--
V. OUT
0-----
Power supply
Input for IF Amplifier (+)
AF output
Input for IF Amplifier (-)
Feed back
Lou Pass Capacitor
Input for attenuator
Regulated Voltage
Ou tput of detector
Discriminator
Muting
Discrim inator
Ground
Controlled voltage for DC attenuator
I
"-r-N
I--
CONNECTION DIAGRAM (Top View)
464
k:
rL/JLL/~//////////~~
PIF
DEl.
~
ATTENUATOR
jlPC'1382C
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Power supply voltage
VCC
0
15
V
V
mA
Pin 13, 14 voltage
V13, V14
0
5
Pin 2 output current
12
0
20
Power dissipation
Pd
Operating temperature
Storage temperature
350.(Ta=75°C)
mW
T opt
-20 to +75
°c
T stg
-40 to +125
°c
V,
ELECTRICAL CHARACTERISTICS (Vcc=12
SYMBOL
Ta=25±3 °C) *Mark f=4.5 MHz, odf=±25 kHz, fM=400 Hz, AMMOD=30 %
MIN.
TYP.
MAX.
UNIT
CKT
ICC
15
20
25
rnA
1
Vi(lim)
-
200
400
J,LVr.m.s.
1
*-3 dB point
Detector output voltage
VOAF
450
600
750
mVr.m.s.
1
* Vi=10 mVr.m.s.
Detector output distortion
T.H.D·DET
AM rejection
AMR
CHARACTERISTIC
Total supply current
IF limitting voltage
CONDITION
VCC=12 V Zero carrier
-
0.4
1.0
%
1
* Vi=10 mVr.m.s.
-44
-55
dB
1
* Vi ~3 mVr.m.s.
dB
2
fin=400 Hz, Vi=600 mVr.m.s.
DC VR maximum attenuation
ATTVR
70
80
-
DC VR distortion
T.H.D·VR
-
0.4
1.0
%
2
fin=400 Hz, Vi=600 mVr.m.s. V8~5 V
AF voltage gain
GVAF
11.5
15.0
-
dB
2
fin=400 Hz, Vi=100 mV.r.m.s. R3=1 kn
IF input resistance
Rin
1.5
kn
3
IF input capacitance
Cin
2.0
pF
3
Pin 4 input resistance
Rin4
20
kn
3
Pin 4 input capacitance
Cin4
2.8
pF
3
MUTING CHARACTERISTIC
r---- V6
r---------VrH=3 V
-----------0 V
465
J,lPC1382C
TEST CIRCUIT 1
f
SG1 SG
*
0---1
SW2
50
4.7 }IF
~ CERAMIC DISCRIMINATER
Q
14
* : 0.01}1F
SW1
12VO
o
47 }IF
TEST CIRCUIT 2
12V
* : O.OI}1F
TEST CIRCUIT 3
* : 0.01
466
}IF
,uPC1382C
SWITCH TABLE
CKT
SG
ICC
1
-
Ui(lim)
1
UOAF
1
T.H.D·DET
ITEM
CONDITION
SW1
SW2
SW3
SW4
VV1
VV2
T.H.D. T.H.D.
RX
M1
M2
M1
-
-
-
-
-
0
-
-
V CC:=12 V Zero carrier
A
OFF
-
-
0
SG1
*-3dB point
B
ON
-
SG1
* Uj=10 mVr.m.s.
B
ON
-
0
0
1
SG1
* Ui:=10 mVr.m.s.
B
ON
-
-
-
-
AMR
1
SG1
* Ui
B
ON
-
-
0
-
-
-
ATTVR
2
SG2
fM=400 Hz, Uj=600 mVr.m.s.
-
-
B
A-+B
-
0
-
-
T.H.D·VR
2
SG2
fM:=400 Hz, Ui=600 mVr.m.s.
-
B
A
-
-
-
0
-
GVAF
2
SG2
fin=400 Hz, Ui=100 mVr.m.s.
-
A
A
-
0
-
-
-
Rin
3
-
-
1
-
-
1
3
-
2
Cin4
-
-
3
-
-
Rin4
-
-
-
Cin
-
-
3
-
-
-
2
~
3mVr.m.s.
-
-
-
-
* f=4.5 MHz, Af=±25 kHz, fM:=400 Hz, AMMOD=30 %
CERAMIC DISCRIMINATOR
MURATA CDA4.5MC 20
SPECI FICATION OF DETECTION COl L
(:J
Frequency
No loading Q
Turn
Internal C
Wire
TOKO TKAC·27071BY
4.5 MHz
68 ± 20 %
1-3 31~ T
1-215~ T
2-316 T
82 pF
0.12 rP OUEW
TOKO TKAC·26984Y
5.5 MHz
60±20%
26T
13 T
13 T
82 pF
0.12 rP OUEW
467
~
m
())
J,LPC 1382C APPLICATION CIRCUIT
~
."
(")
~
Muting pulse
=t-F3
U- o
W
V
CO
N
47 kOS VR
•
•
(")
47 0
'1M
0 VCC1=12 V
0,01
oVCC2= 100 V
10 kO
Power
regulator
D(]
SIF IN
---..L
c:::=::::J
~1'Fl
100 kO
4700 pF 160 V
CDA4.5MC20
(MURATA)
Example using 1FT
OUTPUT POWER TRANSISTOR
5 pF.
r
i~~i.J
L _____
3.5 W
Tr: 2SD401
2.0 W
1.0 W
Tr : 2SC2371
Tr: 2SC1941
BIPOLAR ANALOG INTEGRATED CIRCUIT
pPC1391H
SOUND IF PROCESSOR FOR SOUND MULTIPLEX TV
DISCRIPTION
pPC1391 H is sound IF processor for sound mUltiplex TV. It can be operated with no adjustment, using ceramic filters
externally. The quadrature detector realizes excellent low distortion. It is included in a 8 pins SIL package.
FEATURES
PACKAGE DIMENSIONS (Unit: mm)
• Operation with ceramic filters makes TV sound circuit
no adjustment completely.
•
2.8±O.2
19.5 MAX.
Low distortion . . . . . . . . . . . . . . . . 1 0.2 % 1
• High sensitivity . . . . . . . . . . . . . . . 200 pVr.m.s.
•
Excellent AMR . . . . . . . . . . . . . . . 1-55 dB (TYP.) 1
17.78
BLOCK DIAGRAM
SPINS
i~-------i
I
I
L __ __
~--If~----'
I
I
L __ _
8 .
7
Detector
JVCC=12 V
Output
l---»--C;>
I
I
469
,uPC1391H
TV BLOCK DIAGRAM
ANTENNA
AFT
CH ROMA.
AMP.
SYNC
SEP.
COLOR
OUT
COLOR
SYN~
H.OUT
V.OUT
CONNECTION DIAGRAM (Top View)
Power supply
Detect filter
2
Detect filter
Detect output
Ground
5
Capacitor
6
SIFinput
SIFinput
470
,uPC1391 H
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Power Supply Voltage
VCC
Pin 7,8 Input Voltage
V7 ,VS
15
V
3
Vp-p
270 (Ta=75°C)
mW
Power Dissipation
Pd
Operating Temperature
Topt
-20 to +75
°c
Storage Temperature
Tstg
-40 to +125
°c
ELECTRICAL CHARACTERISTICS (Vcc=12 V, Ta=25±3 °c, f=4.5 MHz, fM=400 Hz, AM MOD=30 %)
CHARACTER ISTIC
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
S.O
16.0
24.0
mA
-
1S0
360
",Vr.m.s.
VOAF
VOAF1
150
200
Vi=3 mVr.m.s., .6.f=±25 kHz
320
410
mVr.m.s.
Vj=3
Detecter Output Distortion - 1
vOAF2
T.H.D.1
-
mVr.m.s.
-
0.2
0.5
%
Detecter Output Distortion - 2
T.H.D.2
-
0.6
1.5
%
Vi=3 mVr.m.s., .6.f=±50 kHz
AM Reject jon
AMR
-45
-55
-
dB
Vj=3
Total Supply Current
ICC
IF Limitting Voltage
VjOim)
Detecter Output Voltage - 1
Detecter Output Voltage - 2
Zero carrier
(Vj=3
mVr.m.sJ, -3 dB point
mVr.m.s., .6.f=±50 kHz
Vi=3 mVr.m.s., .6.f=±25 kHz
mVr.m.s., .6.f=±25 kHz
TEST CIRCUIT
J,lPC1391H
VCC=12 V
+
lOOpF
471
,uPC1391H
APPLICATION CIRCUIT
Using 1FT
JlPC1391H
Using ceramic filter
(MURATA CDA4.5MC19)
JlPCl391H
Vee
r----
-SIF IN
+
lOO,uF
VOAF
(Detect output)
DETECTION COIL SPECIFICATION
TOKO 10KN TYPE TKAC-27071BY
~
~
472
Frequency
No loading Q
Turn
Internal C
Wire
: 4.5 MHz
: 68±20 %
1-3 31%T
1 - 2 15% T
2- 3
16 T
: 82 pF
: O.12ct> OUEW
BIPOLAR ANALOG INTEGRATED CIRCUIT
J-lPC1352C
CHROMINANCE AND LUMINANCE PROCESSOR FOR NTSC COLOR TV
DESCRIPTION
IlPC1352C is an integrated circuit for NTSC system to process both color and luminance signals of the color televisions. It is an
MSI contained in a 28 pins dual in line package and provides two functions. One is the processing of color signal for the band
pass amplifier, color synchronizer, demodulator circuits, and the other is the processing of luminance signal for the luminance
amplifier and pedestal clamp circuits, the number of peripheral parts and controls can be minimized, and the manhours
required for the assembling can be considerbly reduced.
FEATURES
•
It needs very few external components, and minimize the adjustments.
o DC controlled circuits make aremote controlled system easy.
•
Protection diodes in every input terminals and output terminals.
•
"Color killer" does not need any adjustments.
o "Contrast" control does not prevent the natural color of the picture
any more, as the color saturation level changes simultaneously.
o ACC (Automatic color controller) circuit operates very smoothly
with peak level detector.
"
PACKAGE DIMENSIONS in millimeters
"Brightness control" terminal can be used for ABL (Automatic
beam limitter) also.
38.0"".
~
-E~:~~~~~~I
13.2
1 2 3 4 5 6 7 8 9 10 11 12 1314
~02S,g~
+0.5±0.1
2.54
~
::;:
S
N
BLOCK DIAGRAM
473
,uPC1352C
TV BLOCK DIAGRAM
Speaker
V.
Out
PIN CONNECTION (Top View)
474
Power Supply
B Output
Clamp Filter
G Output
Brightness Cont.
R Output
Resolution Cont.
Demo Input
Luminance Input
Blanking Input
Peaking Filter
Oscillator
Tint Cont.
Oscillator
Auto Setting
Voltage
Oscillator
Color Cont.
Gate Pulse Input
Contrast Cont.
APC, ACC Input
Chroma Output
Killer Filter
Condenser
(By pass)
APC Filter
Chroma Input
APC Filter
GND
ACC Filter
~PC1352C
THE STANDARD OPERATING CONDITIONS
Characteristic
Value
Unit
12
V
Chrominance Input Voltage
(Burst signal level)
150
mVp-p
Luminance Input Voltage
(Sync White Level)
1.0
Vp-p
Burst Gate Pulse Input Voltage
3.0
Vp
Blanking Pulse Input Voltage
2.5
Vp
Color saturation controlling Voltage Range
0-5.7 (at VCC=12 V)
V
Tint controlling Voltage Range
0 .... 5.7 (at VCC=12 V)
V
Contrast controlling Voltage Range
0 ..... 12 (at VCC=12 V)
V
Resolution controlling Voltage Range
0 .... 12 (at VCC=12 V)
V
Brightness controlling Voltage Range
8 .... 10 (at VCC=12 V)
V
Supply Voltage
Note: In case of operating in VCC=14.4 V, Set the surrounding temperature Ta to be 67°C.
ABSOLUTE MAXIMUM RATINGS (Ta = +25 °C)
VCC
14.4
V
Brightness Controlling Voltage
V3
14.4
V
Resolution Controlling Voltage
V4
14.4
V
Contrast Controlling Voltage
V10
14.4
V
Tint Controlling Voltage
V7
14.4
V
Color Controlling Voltage
V9
14.4
V
Auto Controlling Voltage
V8
14.4
V
Luminance Input Signal Voltage
V5
+5
V
Chrominance Signal I nput Voltage
V13
+2.5
V
Demodulator Input Signal Voltage
V25
+5
V
126,127,128
-40
mA
Gate Pulse Input Voltage
V20
+5
V
Gate Pulse Output Current
120
-10
mA
V24
±6
V
Power Dissipation
Pd1 (Ta=25°C)
1.2
W
Power Dissjpation
Pd2 (Ta=70 °C)
750
mW
ODerating Temperature
T opt
-20 .... +70
°c
Storage Temperature
T stg
-40 .... +125
°c
Supply Voltage
R.G.B Output Current
Blanking Pulse Input Voltage
Test Conditions (Vcc=12 V)
Characteristic
MIN.
TYP.
MAX.
Color saturation controlling
terminal 9
OV
V8/2 V
V8V
Tint controlling terminal 7
OV
V8/2V
V8V
Contrast controlling
terminal 10
OV
VCcx 0.78 V
VCCV
Resolution controlling
terminal 4
OV
VCCV
475
,uPC1352C
ELECTRICAL CHARACTERISTICS (Ta=25
°c unless otherwise noted Vcc=12 V)
Color control is manual state and tint is center for the items not specifically specified
No.
Characteristic
Symbol
Test
Ckt.
Test Condition
MIN.
TYP.
MAX.
Unit
32
43
54
mA·
1
Supply Current
ICC
1
2
Burst Output
Voltage
eb
3
Rainbow color bar signal input
150 mVp-p, Color auto center,
Contrast max.
0.5
0.7
0.9
Vp-p
3
ACC Range 1
ACC1
3
Rainbow color bar signal input
300 mVp-p,
Burst Output Voltage/eb
0.9
1.0
1.1
times
4
ACC Range 2
ACC2
3
Rainbow color bar signal input
15 mVp-p,
Burst Output Voltage/eb
0.6
0.8
1.0
times
5
Chroma Output
Voltage 1
ec 1
3
Rainbow color bar signal input
150 mVp-p, Color min, Contrast max.
0.5
0.7
0.9
Vp-p
6
Chroma Output
Voltage 2
ec2
3
Rainbow color bar signal input
150 mVp-p, Color min, Contrast max.
-
-
5
mVp-p
7
Chroma Output
Voltage 3
ec3
3
Rainbow color bar signal input
150 mVp-p, Color center,
Contrast max.
120
190
260
mVp-p
8
Chroma Output
Voltage 4
ec4
3
Rainbow color bar signal input
150 mVp-p, Color auto center,
Contrast max.
130
190
260
mVp-p
9
Variable Range
of Chroma Output
Voltage at auto
~eca
3
Rainbow color bar signal input
150 mVp-p, Color auto max min,
Contrast max.
+25
-25
+35
-35
+45
-45
%
-
-
±150
Hz
Hz/mV
10
Free running
Frequency
fo
2
No input signal to Terminal 19
Be trimed 3.579545 MHz by using
a trimer capasitor for standard
sample,
Deviation from f; 3.579545 MHz
11
Oscillator
controlling
sensitivity
(3
2
Burst signal input 0.7 Vp-p,
Converted from V16-17 in case of
100 Hz burst frequency variation
1.0
1.5
2.0
12
Phase detector
sensitivity
}J.
2
Burst signal input 0.7 Vp-p,
Converted from phase error and
V16-17 in case of 100 Hz burst
frequency variation
25
45
65
13
Phase error
~rP
2
Burst signal input 0.7 Vp-p,
Phase error to 100 Hz of burst
frequency variation
-
1.5
3.0
degree
1100 Hz
14
A.P.C. pull-in
frequency range
fp
2
Burst signal input 0.7 Vp-p,
Mesured by changing the burst
frequency
±350
±500
-
Hz
15
Variable Range
of Tint
2
Burst signal input 0.7 Vp-p,
Tint; max min, manual,
Tint center, Range from 0 as
a standard
+37
-37
+45
-45
+53
-53
degree
16
Variable Range
of Tint at auto
2
Burst signal input 0.7 Vp-p,
Tint; max min, auto
Tint center, Range from 0 as
a standard
12
-12
+17
-17
+22
-22
degree
~61
~62
mVI
degree
(continued on next page)
476
JLPC1352C
No.
Characteristic
Symbol
Test
Ckt.
Test Condition
MIN.
TYP.
MAX.
Unit
1.5
2.0
2.5
Vp-p
17
B-Y Output
Voltage
e01
3
Oem. input 0.2 Vp-p, f=3.59 MHz,
Bright VR was set to be V26=3.5 V(DC)
No blanking input
18
Ratio of R-Y
to B-Y
RIB
3
Oem. input 0.2 Vp-p, f=3.59 MHz,
R Output Voltage/e 0 1
Bright VR was set to be V26=3.5 (DC)
No blanking input
0.86
0.94
1.04
times
19
Ratio of G-Y
to B-Y
GIB
3
Oem. input 0.2 Vp-p, f=3.59 MHz,
G Output Voltage/e 0 1
Bright VR was set to be V26=3.5 V(DC)
No blanking input
0.25
0.30
0.35
times
20
Relative
Output phase
G-Y to R-Y
LR
3
Oem. input 0.2 Vp-p, f=3.59 MHz,
B= 0 degree, phase difference
Bright VR was set to be V26=3.5 V(DC)
No blanking input
94
97.5
102
degree
21
Relative
Output phase
G-Y to B-Y
LG
3
Oem. input 0.2 Vp-p, f=3.59 MHz,
B= 0 degree, phase difference
Bright VR was set to be V26=3.5 V(DC)
No blanking input
228
235
242
degree
22
Maximum Color
difference
Output Voltage
e02
3
Oem. input 1.2 Vp-p, f=3.59 MHz,
Bright VR was set to be V26=3.5 V(DC)
No blanking input
4.8
5.7
-
Vp-p
23
Residual
Carrier
3
No signal input,
Output; 3.58 MHz each,
Carrier leak component,
Bright VR was set to be V26=3.5 V(DC)
No blanking input
-
-
100
mVp-p
24
Demodulation
frequency
characteristic
3
Attenuation factor of demodulation
output at f=500 kHz,
Oem. input 0.2 Vp-p, f=3.08 MHz,
Assuming the output at f= 10 kHz
is 0 dB
-1.5
-0.9
-0.4
dB
25
Overall Color
difference
Output Voltage
3
Rainbow color bar signal input
150 mVp-p,
Color auto center,
Contrast max, in R output
1.0
1.7
2.4
Vp-p
26
Overall Color
difference
Output Variable
Range by Contrast
~eoc
3
Rainbow color bar signal input
150 mVp-p,
Color auto center,
Contrast maxImin, in R output
3.4
3.85
4.3
Vp-p
27
Color killer
talerance
ek
3
Burst input Voltage at terminal 13
150 mVp-p=O dB,
Attenuation value in operating
the killer
-27
-32
-40
dB
4.5
5.0
5.5
times
4.0
4.5
5.0
times
ecar
eof
e03
28
Luminance Gain
Av1
3
R,G,B Output each,
Studio color bar input 1 Vp-p in
white level, Contrast max,
Resolution min,
Pedestal of terminal 26 is 2 V,
Bright VR was set
29
Luminance Gain
Variable Range
by Contrast
~evc
3
Studio color bar input 1 Vp-p in
white level, Contrast maxImin.
Resolution min, in B output
(continued on next page)
477
,uPC1352C
No.
Characteristic
30
Luminance Amp.
frequency
characteristic
31
Resolution
Variation Range
32
DC Restored
33
Brightness
controlling
sensitivity
34
Maximum R,G,B
Output Voltage
35
Differential
Gain
36
Queiscent Output
Voltage
37
Eo
Supply Voltage
Coefficient
38
Eo
Temperature
Cofficient
39
Difference
Output Voltage
478
Symbol
Test
Ckt.
Test Condition
MIN.
TYP.
MAX.
Unit
5
6
-
MHz
9.0
dB
3
Sine wave signal input 0.1 Vr.m.s.
Input frequency at Av1 =-6 dB
Resolution min, in B output,
Bright VR was set to be V26=3.5 V(DC)
No blanking input, 0 dB= 16 kHz Output
..1fvp
3
Sine wave signal 0.1 Vr.m.s., f= 2 MHz
Contrast max,
Resolution min-max, in B Output
max/min
5.0
7.0
TDC
3
Stair Step signal input 1 Vp-p,
APL 10-90 %
in B Output
65
75
85
%
BR
3
..1E o /..1V3, Eo=2 V-5 V,
R,G,B Output each
4.0
4.5
5.0
-
EoM
1
R.G.B Output Voltage each at
V3= 12 V
7.0
-
-
V
3
Stair Step signal input 1 Vp-p,
f=3.58 MHz, APL=50 %,
Contrast max, Resolution min,
Pedestal of terminal 26 is 2 V,
Bright VR was set
-
-
5.0
%
Eo
3
R,G,B Output each,
Bright VR was set to be V3=9 V,
No Luminance signal input,
Contrast max, VCO is operating,
Blanking
2.5
3.5
4.5
V
Eo-v
3
VCC=12 V ±20 %,
V26=3.5 V (VCC=12 V),
R, G, B Output each
Blanking
0.2
0.25
0.3
V/V
..1 Eo -t
3
Ta=-20-+70 °c,
V26=3.5 V (Ta=25 °Cl
R,G,B Output each
-4.0
-2.0
0
mVfC
3
V26=3.5 V
VCO is operating,
R,G,B Output each,
No blanking input
-
0
300
mV
fv
D.G.
..1ER-G
..1EG-B
..1EB-R
:
,uPC1352C
Test Circuit 1
~vcc
+ 12
~
V
\SI
\
28
r
\
27
2
26
3
25
4
24
5
23
6
22
7
21
8
20
9
19
10
18
11
17
12
\
\
\
\
\
\
\
\
0.01
\
\
\
\
\
~+4V
\
\
\
\
\
\
\
\
\
56 k
\
\
0.01
16
13
15
14
\
A
\
~,.o
\
\
8
S2
,,~
R;n
C ; ""F
Supply Current
Icc
S1 ; ON
S2 ; Side A
Maximum R,G,B
Output Voltage
EoM
S1 ; ON
S2 ; Side B
S3 ; Each
479
~
(J)
o
Test Circuit 2
1:;:
."
o
~
W
ew Output
01
ew
N
o
Vee
CEN~=~--"'"
Burst Signal
-(B-V)Signal
Gate Pulse
Genarator
Gate Pulse
Burst 0.7 Vp-p
-(B-V)
' - - - - - - 0 '-0
o
Variable Burst
frequency
OFF
~
.---------t(0)
100 P
~390p
11
.I
veo Output
Oscilloscope
De
Volt
meter
r---{+
'-.J
APe difference
Voltage
Vee
TEST Ie
----
5.6 k
~\
SG-
3.9 k
14
113
112
11
rIO
5 k Blanking Pulse Input
pPD4001
pPD4049
~
.J
9T 101
111
121
13
141
15
16
2
OFF
~
ON
CEN
ON
IN
+f
CEN
f
-
Vector Scope
A.P.C. pullin Freq. range
fp
2
CEN
ON
IN
+f
CEN
f
-
Oscilloscope
Variable Range
of Tint
A81
OFF
IN
CEN
-
Vector Scope
Variable Ra~ge
of Tint at auto
A82
OFF
IN
CEN
-
Vector Scope
B·Y Output
Voltage
eo l
OFF
./.
ON
OFF
MAX
./.
./.
ON
MIN
OFF
MAX
2
./.
./.
ON
MIN
2
OFF
~
ON
3
-
OFF
-
-
-
OFF
FIX
OFF
OP
EXT
0.2 Vp-p
f=3.59
B
e0 3
-
V26=
3.5 V
MIN
-
Oscilloscope
Demo. Output
Voltage B
-
(continued on next page)
o
w
en
N
o
~
1
Characteristic
Symbol
Test
Ckt
Power
Supply
2
Tint
3
4
fB
5
6
Auto
Burst
-IB-YI
Input
Burst
frq.
Power
Supply
Luminance
Input
8
9
10
11
12
Auto
Color
Contrast
Chroma
Input
ACC
Pulse
Input
7
13
14
15
16
17
1
2
3
4
VCO
Demo
Input
R
G
B
Demo
Output
Attenuater
Brightness
Brightness
Rt1olution
ACC
Level
MIN
-
Oscilloscope
Demo. Output
Voltage R B
MIN
-
Oscilloscope
Demo. Output
Voltage G B
-
Measuring
Apparatus
Ratio of R·Y
toB-Y
RIB
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
OFF
OP
EXT
0.2 Vp·p
f=3.59
B
R
eo3
-
V26~
Ratio of G-Y
to B-Y
G/B
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
OFF
OP
EXT
0.2 Vp·p
f=3.59
G
I
eo 3
-
V2S3.5 V
Relative
Output phase
B-Y to R-Y
LR
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
OFF
OP
EXT
0.2 Vp·p
f=3.59
B
R
eo3
-
V263.5V
MIN
-
Phase Meter
Relative
phase R B
Relative
Output phase
G-Y to B-Y
LG
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
OFF
OP
EXT
0.2 Vp·p
f=3.59
B
G
eo 3
-
V263.5V
MIN
-
Phase. Meter
Relative
phase B G
Maximum
Detected
Output
Voltage
e02
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
OFF
OP
EXT
1.2 Vp-p
f=3.59
B
R
eo3
-
V26=
3.5 V
MIN
-
Oscilloscope
·Demo. Output
Voltage B R
Residual
Carrier
ecar
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
OFF
OP
R
G
B
eoc
-
V263.5 V
MIN
-
Oscilloscope
Output
3.58M Carrior
Demodulation
frequency
characteristic
eof
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
OFF
OP
EXT
0.2 Vp·p
f=3.08
R
G
B
OFF
-
V26=
3.5V
MIN
-
A.C. Voltage
Meter
Overall
Detected
Output Vol.
e0 3
3
OFF
~
ON
OFF
ON
CEN
MAX
IN
FIX
IN
OP
INT
R
eo3
A
TP-2
150 mVp·p
V26=
3.5 V
MIN
-
Oscilloscope
Demo. Output
Voltage R
Overall
Detected
Output Variable
Range by Cont.
controlling
Ae oc
3
OFF
~
ON
OFF
ON
CEN
MAX
~
MIN
IN
FIX
IN
OP
INT
R
e03
A
TP-2
150 mVp-p
V263.5V
MIN
-
Oscilloscope
Demo. Output
Voltage R
ek
3
OFF
~
ON
OFF
-
-
-
IN
FIX
IN
OP
INT
R
e0 3
A
TP-2
150 mVp-p
V263.5V
MIN
-
Oscilloscope
Demo. Output
Voltage R
3
OFF
~
ON
IN
Studio
Color
Bar
White
1 Vp-p
MAX
OFF
VAR
IN
NOP
EXT
NO.
R
G
B
OFF
-
Terminal26
Pedestal
2V
MIN
V15=
8V
Oscilloscope
ev
IN
Studio
Color
Bar
White
1 Vp-p
EXT
NO.
B
OFF
-
Terminal26
Pedestal
2V
MIN
V158V
Oscilloscope
ev
EXT
NO.
B
OFF
-
V26=
3.5 V
MIN
V158V
A.C. Voltage
Meter
o dB= 16 kHz
ev
V158V
A.C. Voltage
Meter
ev
Coli or
killer
talerance
Luminance
Gain 1
AVl
EXT
Luminance Gain
Variable
Range
by Contrast
cont.
Ae ve
3
OFF
~
ON
Luminance Amp
Frequency
characteristic
fll
3
OFF
~
ON
IN
Sine
Wave
0.1 Vr.m.s.
3
OFF
~
ON
IN
Sine
Wave 2M
0.1 Vr.m.s.
ReSOlution
Variation
Range
Af llp
MAX
OFF
VAR
IN
NOP
MAX
OFF
VAR
OFF
NOP
MAX
OFF
VAR
OFF
NOP
No.
EXT
NO.
B
OFF
-
-
3.5V
V263.5 V
MIN
MAX
J
U1
(')
~
W
--
(continued on next page)
~
Q)
1:::
."
c.n
N
(')
~
Q)
en
~
."
1
Characteristic
Symbol
Test
Ckt
Power
Supply
2
Tint
3
4
fB
5
6
Auto
Burst
-(B-YI
Input
Burst
frq
Power
Supply
Luminanee
Input
IN
Stair
step
1 Vp-p
APL
90%
D.C.
Transfer
TDC
3
OFF
~
ON
Brightness
Controlling
Sensitivity
BA
3
OFF
~
ON
OFF
3
OFF
~
ON
IN
Stair
step
APL
50%
Differential
Gain
D.G.
7
Auto
-
8
9
10
Color
Contrast
-
11
12
13
14
15
16
Chroma
Input
ACC
Pulse
Input
VCD
Demo
Input
A
G
B
MAX
OFF
VAA
IN
NOP
EXT
NO.
MAX
OFF
VAA
IN
OP
MAX
OFF
VAA
IN
NOP
17
1
2
3
4
Demo
Output
Attenuater
Brightness
Brightness
Aesolution
ACC
Level
B
OFF
-
Terminal26
Pedestal
2V
MIN
V158V
EXT
NO.
A
G
B
eo3
-
eo3
D.C.
2-5V
MIN
V158V
EXT
NO.
B
OFF
-
Terminal26
Pedestal
2V
o
Measuring
Apparatus
N
MIN
V158V
Oscilloscope
ev
V3e o 3
D.C. Voltage
Meter
Vector
Scope
ev
Eo
3
OFF
~
ON
OFF
-
-
MAX
OFF
FIX
IN
OP
EXT
NO.
R
G
B
eo3
-
V39V
MIN
-
D.C. Voltage
Meter
Eo
Supply Vol.
Coeffisient
Eo-v
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
IN
OP
EXT
NO.
A
G
B
eo3
-
V39V
MIN
-
D.C. Voltage
Meter
Eo
Temperature
Coefficient
Eo -t
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
IN
OP
EXT
NO.
R
G
B
eo 3
-
V3=
9V
MIN
-
D.C. Voltage
Meter
EA-G
EG·B
EB-R
3
OFF
~
ON
OFF
-
-
-
OFF
FIX
OFF
OP
EXT
NO.
R
G
B
eo3
-
V26=
3.5 V
(VCC·
12Vl
MIN
-
D.C. Voltage
Meter
Queiseent
Output
Voltage
Difference
Output
Voltage
---
----~
----
~
w
c.n
o
tLPC1352C
ACC Characteristic
Contrast Control Characteristic
ACC Gain reduction
VCC = 12 V VCO is No operation
1.0
colorbar
S.G.
0.7
J\.
.I\.
11
13
ATT
~
/
12
BPF
A;
"'
0.5
0.3
V
/
,
0.2
V
......
......
~
roc
'§
a::
0.1
a
~
:cOJ
'C:I
>
Cll
2:-
.-=:
Contrast Control
~~
80
-(R-Y)OutPu~
40
OJ
20
". ~
~
60
Cll
f-
c.
---
V
/
.".. ~1
~
I-- ., Luminance Output
Cll
tlD
I
.8
"0
/
,
100
4
2
0
6
8
10
12
Control Voltage V10 (V)
0.05 ::
:::J
.e
:::J
0
tl
~
CD
-50
-40
-30
-20
-10
0
Chroma input Attenuation (dB)
o dB = 150 mVp-p in Burst signal
Brightness Control Characteristic
Color Control Characteristic
J5"'"
Demodulator input vs. Output
Color Saturation control
2
I
,
I
~
~~
I
Co
~
-I r
2:Cll
tlD
.r:l
>
"'5
Co
"'5
O. 1
f
~~
3.59 MHz
AUTO
6
~
I
Co
2:5
Cll
tlD
1
I
I
OJ
.r:l
"0
>
"'5
Co
"'5
4
0
3
~
e
.r:.
U
j
0.0 1
I
/
"0
u
2
,/
/
"
o
1
234
5
Control Voltage V9 (V)
at Manual control Voltage
6
o
~
Cll
So
Cll
3
10
0
;:::
~-1O
f"
~ -20
~'-30
a.
-40
-50
-
o
~
~~
/
.-
i"""V
.Y
~ ~ " . AUTO
. /~G-Y)OutPut
0.8
14
~
3
12
1
VCC=12.0V+-
26
5
1\.1 Vp-p
l[
.1 I.
~Ite ieVjl-
--9.6 V -
I
I
I
I
I I I I
I I I I
L/
3
4
5
6
Control Voltage V7 (V)
at Manual control Voltage
1.0
Luminance Input Voltage 1 Vp-p
---14.4~_
Contrast MAX.
V
2
0.6
0.4
0.2
Brightness control Characteristic.
J-..Manual
/'
Demodulator Input-Output
Tint ControlA
~
/
Chroma input Voltage (Vp-p) Terminal 25
Tint Control Characteristic
50
40
30
20
. /~
:~-Y) and (R-Y) Output
0
E
~
::l
25
S.G.
"0
0
I",",
26
/ ' Manual
I
J
BRIGHT
II-
o
White level
,.
' ,
.,.,.
Black level
,
1/
'
, /1:
'r.
/
"\CBlack Ilevel/ I !/
output signal I
, I I
~
J
I I I III
I I I I I /'1/
2 3 4 5 6 7 8 9 10 11 12 13
Brightness controlling Voltage V3 (V)
487
j.lPC1352C
R.G.B. Output Stage Dynamic Page
luminance OutPUt Voltage vs. Supply Voltage Characteristic.
Brightness controlling V.R. is fixed
5 luminance Input Voltage 1 Vp-p 'IL
14 Contrast MAX.
~
3
/
12
~
/'
1
10
Vee~
!:
~
R
~
8
V~ V
6
,
,,~
./
,
RGB output
upper limit -
'I 1 1
~
i'
-
~
White
--I"""'"
.,
I~ell-
"'-" ~ rl I I I
lumi~nce o~tPUt ra~ge
I
3
2
o
~
..... 1"
7
4
~PC1352C
/'
J J J
~ Bla~k I~Vel:_
11
j
9 10 11 12 13 14 15
Supply Voltage Vee (V)
BAND PASS COIL
CD-@88T
@-@43-1/4T
WIRE MA TERIAL
0.124> OUEW
INSIDE CAPACITOR
C1 =47 pF
Pin Connection
4SS
Qu 15±20 % at f=3.58 MHz
Qu 24±20 % at f=3.58 MHz
APPLICATION CIRCUIT
Contrast
,
Resolution
,
Brightness
0
VCC = 12 V
5 k6
AUTO
Color
Saturation
10k
~~f~13
~
Blanking
Pulse
COMPOSITE
INPUT SIGNAL
GND
A~
1::
."
o
...II
W
U'I
N
o
~
(J)
CD
,uPC1352C
~PC1352C
PRINTED CIRCUIT BOARD PATTERN (BOTTOM VIEW)
o
NEe
J.lPC1352C
AUTO SWITCH
VCC---t--i-r--+---COMPOSITE
SIGNAL
OUTPUTS
R--+-~--.....,....
---i-
B--foooO..............
BURST GATE PULSE
490
BIPOLAR ANALOG INTEGRATED CIRCUIT
J1,
PC1364C2
CHROMINANCE PROCESSOR FOR SECAM COLOR TV
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
J,LPC1364C2 is an integrated circuit for the chrominance signal processing of SECAM system receivers. This IC in 28 pins dual in
line package has the functions required for the chrominance signal processing such as Iimitters, (R-Y)/(B-Y) demodulators,
SECAM switch, identification circuit, killer, color control, clamp and R/G/B matrix circuit. The outputs are available in
original R, G, B color signals. In addition, by the combination with NEC's PAL chrominance IC - J,LPC1365C, PAL/SECAM
dual system can be realized.
PACKAGE DIMENSIONS in millimeters
FEATURES
•
R, G, B outputs in original color signals.
• PAL/SECAM dual
system capability by the combination
of J,LPC1364C2 and J,LPC1365C.
o Excellent white balance and crosstalk characteristics.
• Simple adjustment for contrast level and color control.
38.0 MAX.
-t:~:~:::1
12 34 , 67 89101112131.
L1
N
~j25'8~>M
2.54 ! ~
+0.5±0.1
~
0·-15·
BLOCK DIAGRAM
r-----------~~~~====~~~------------------I
Video
Input
Pulse
491
jlPC1364C2
TV BLOCK DIAGRAM
(PAL·SECAM DUAL SYSTEM)
SIF
Amp
SIF
Det.
A.F
Out
r--------------,
I
UIVHF
Tuner
PIF
Amp
Color
Sync
PIF
Det.
PAL
I
I
I
I
I
I
I
I
,
(PAL)
-.J
PIN CONNECTION (Top View)
Power Supply
Blanking Pulse Input
Video Input
Capacitor(Killer)
B Output
Burst Gate Pulse Input
G Output
Capacitor(ldent)
R Output
Coil(ldent)
Ca pacitor(CI amp)
Coil(ldent)
Capacitor(Clamp)
Color Control(Contrast)
Capacitor(Clamp)
8
B-Y de-emphasis
R-Y de-emphasis
9
Coil(B-Y Demo)
Coil (R-Y Demo)
Color Control
Bias Output
Line Pulse Input
Chroma Input 2
Chroma Output
(Delayed Signal)
492
Capacitor (by-pass)
CapacitorCby-pass)
G.N.D.
Chroma Input 1 (Direct Signal)
Speaker
jlPC1364C2
STANDARD USING CONDITIONS
Supply Voltage
12
V
200
mVp-p
1
Vp-p
Video Input Signal (Black Level)
10
V De
Burst Gate Pulse
3
Vp
Line Pulse
3
V-p
Blanking Pulse
3
Vp
Chroma Input Signal (Burst Signal)
Video I nput Signal
2
V
Color Controlling Voltage (Pin 19)
R.G.B. Output Black Level
5.2 to 6.7 to 8.2'
V
Color Controlling Voltage (Pin 22)
5.9 to 7.4 to 8.9
V
(Relative Contrast)
ABSOLUTE MAXIMUM RATINGS (Ta
= 25 °c Unless otherwise)
Supply Voltage
Vee
15
V
Signal Input Voltage
ej
5
V p.p
Pulse Input Voltage
ep
(Ta
=+70°C)
±6
V
750
mW
Power Dissipation
Pd
Operating Temperature
T opt
-20 to +70
°c
Storage Temperature
Tstg
-40 to +125
°c
493
j.lPC1364C2
ELECTRICAL CHARACTERISTICS (Ta
NO
= 25°C unless otherwise noted, Vcc = 12 V)
SYMBOL
CHARACTERISTIC
Contrast max, Color typo
TEST MIN. TYP. MAX. UNIT
CKT
TEST CONDITION
No Input Signal, Killer on V3 = 3.5 V
1
Supply Current
ICC
1
33
45
57
rnA
2
Pin 11 Voltage
V11
1
1.9
2.3
2.7
V
Same as No.1
3
Pin 17 Voltage (Killer off)
V17
1
8.0
8.6
9.2
V
Same as No.1, Killer off
4
Pin 17 Voltage (Killer on)
V17k
1
11.0
11.3
11.6
V
Same as No.1, Killer on
5
Demodulator Output
eOB,eOR
1
0.6
0.9
1.3
Vp-p
6
Limitting Sensitivity
eL
1
2.5
5
10
mV p _p
7
A.M. Reject Ratio
AMR
1
34
40
-
dB
f12 = 4.02 MHz, f15 = 4.48 MHz,
e12 = e15 = 200 mVp-p
f15 = 4.25 MHz ±230 kHz, eDB = -3 dB
f15 = 4.25 MHz, AM mod = 30 %, fm = 1 kHz,
e15 = 200 mVp-p' Line Pulse off, Compare with
eDB
494
f12 = 4.30 MHz, f15 = 4.25 MHz
beat frq. = 50 kHz, Compare with eDB, eOR
8
Cross talk Level
CT
1
37
43
-
9
Residual Carrier Level
e car
1
-
100
200
10
Maximum Color Differ.ential
Output
eOM
1
4.5
5.7
-
V _
pp
Set eDB = eOR = 1 Vp-p (±0.5 Vp-p)
by f12, f15, Color max.
11
(B-Y), (R-Y) Color
Differential Output
eOB,eOR
1
2.0
3.0
4.0
Vp-p
Same as No.1 0 Color typo
12
Demodulator (G-Y)/(B-Y)
Ratio
G/B
1
0.17
0.19
0.21
times
Same as No. 11, eDR = 0 Vp-p
13
Demodulator (G-Y)/(R-Y)
Ratio
G/R
1
0.46
0.51
0.56
times
Same as No. 11, eDB = 0 Vp-p
14
Maximum Color Gain
ACR,ACB
1
17
19
21
dB
Set eDB = eDR = 0.3 V p _p by f12, f15 Color max.
15
Color Gain Relative Ratio
ACR/ACB
1
-
0
±7
%
Same as No. 14
16
Contrast Cont. Range
eOC
1
15
17
19
dB
Contrast max. to min., Color typo
Set eOB = eOR = 1 Vp-p by f12, f15 at
Contrast max.
17
Residual Color Level
(Killer on)
eOK
1
-
-
30
mVp-p
18
DC Output Voltge
Eo
1
2.7
3.5
4.3
V
19
DC Output Difference Voltage
Ex-y
1
-200
0
200
mV
20
Eo
Temperature Coefficient
AEo/AT
1
-2
0
+2
21
Ex-y
Temperature Coefficient
AEx-y (T)
1
-
0
±60
mV
Same as No. 20
22
Ex-y
Supply Voltage Coefficient
AEx-y (V)
1
0
±60
mV
V3 = 3.5 V at VCC = 12 V, VCC = 12 V ± 20 %
23
Y Amp. Voltage Gain
Ay
1
4.3
4.8
5.3
times
e y = 0.5 Vp-p, f = 10 kHz, V3 = 3.5 V, Killer on
24
VAmp.
Frequency Characteristic
fy
1
5
6
-
MHz
e y = 0.5 Vp-p, OdB = Ay, -3 dB
25
Over all Color Differential
Output Voltage
eOT
2
2.5
3.6
5.0
V _
pp
ein = 200 mVp-p, Color bar Signal, Color tyP.,
Contrast max., B Output
26
Killer Sensitivity
ek
2
28
34
40
dB
o dB= ein 200 mvp _p ' Color bar Signal,
27
White Balance Changing Level
By Input
AEx-y (IN)
2
-
±60
mV
ein = 20 to 400 mVp-p, White Signal
28
White Balance Changing Level
By Color Cont.
AEx-y (Color)
2
0
±60
mV
ein = 200 mV p _p , White Signal, Contrast max.,
Color max. to min.
dB
mV p _p e12 = e15 = 200 mV _ , f12 = f15 = 4.25 MHz
pp
Set eOB = eOR = 1 Vp-p by f12, f15, at Killer off,
Killer on
No Input Signal, Killer on, V2 = 10.3 V
No Input Signal, Killer on, V3 = 3.5 V
mVtC V3 = 3.5 V at Ta = 25°C, Ta = -20 to +70°C
Attenuator Level at Killer on
.uPC1364C2
NO
CHARACTERISTIC
SYMBOL
~Ex-y
TEST
MIN. TYP. MAX.
CKT
UNIT
29
White Balance Changing Level
by Contrast Cont
30
Pin 15 Input Impedance
Ri15
Ci15
3
31
Pin 12 Input Impedance
Ri12
Ci12
3
32
Pin 10 Input Impedance
Ri10
Ci10
3
17
15
33
Pin 20 Input Impedance
Ri20
Ci20
3
17
15
34
Pin 23, 24 Input Impedance
Ri23,24
Ci23,24
3
25
13
35
Pin 17 Output Resistance
R017
-
120
180
270
36
Pin 9, 21 Output Resistance
R09,21
-
4.0
6.0
8.0
37
Minimum Gate Pulse Voltage
Vc (min)
1.5
V
38
Minimum Trigger Pulse Voltage
VFF
1.5
V
39
Minimum Blanking Pulse
Voltage
VBLK
2.0
V
(Contrast)
0
±60
mV
2.8
4.5
4
6.6
5.6
9.5
kn
2.8
3.7
4
5.5
5.6
8.0
kn
2
-
pF
pF
kn
pF
kn
pF
kn
pF
TEST CONDITION
ein = 200 mV p _p , White Signal, Color typ.,
Contrast max. to min.
v
f
= 4.4 MHz,
100 m p _p
f
= 4.4 MHz,
100 mVp-p
Same as No. 31
Same as No. 31
Same as No. 31
n
kn
495
jlPC1364C2
TEST CIRCUIT 1
~----------------~~eD8
VCC=12 V
5.1 kQ
1.5 kQ
••
3.9 kQ
4.7).1F
V"
i
m
:> 33
,,~
TYP
0.47 ).IF
ONi S25
68 kQ
.JLJL
Vyy-
-'1z =
kQ
~
OFF::>
1.5 kQ
A,/"
,''v''''
VCC=12 V
L-o b
MIN.
ZZ
0--
MAX
,I)
S22
150 pF:;:
'--
J
'YY
68 pF
MAX. ()\ 0 -
.... 1.8 kQ
S19
(>
MIN.
.
COLOR
CONTRAST .
7.7
N
::r:
S180_ON_ _ _
J LLINE
JL_
_./
~
GATE PULSE
VCC=12 V
:t
LO
N
-:i-
KILLER
ON
15
1~15
28
27 26 25 24 23
1
POWER
2
4
3
5
6
22 21 20
19
7
10 11 12
8
9
18
17 16
A ' - - - -....
~ON
0..,
___
0
VIDEO
INPUT
OFF
9
zz zz zz
I
To:Cn
47 ).IF.z,.,. .. ~
VCC=12 V
',I.
S2
-v
p:
("'"
""53
~::>
)
J'\~
1.5 kQ
L..--
~ ""S90-
v"
~--1;I;I---""" 150 pF
. 1 ,.
..,
-
AlA
,..
AA
68 "'1"pF
1.8 kQ
.11
"
G
f~
G)
()R
Q
4.7 ).IF N
3 kQ
8 C)
S_4-J§''- __________
(:> R
~
I __L-~0.5
.s u==:
DEMODULATOR OUTPUT
e12
-
-
7'rT
~
3.3 kQ x3 /;Ir
.
,..
8
496
f\.
}~
E~_ _ _ _
o
, 'v
. J:,
'"
3.9 kQ
330 Q x3
470 pF x3
eo
..
.."
VCC=12 V
fi710 kQ 1 kQ
Q);.
0.01 ).IF -+___________
L..--.-____
0---
..V":-l.'"
1,75
.~
;~ 75 '~
).IF
II
0.01 ).IF
,...
IT~
112
14
T 0.01
rfr
).IF..
m10).lF .z~ =~
13
O.~1 pF
15
1~
Sl
ON
PULSE
~-----+--------~~V17
'"'
OFFl S27
68 kQ
0---0
OFF
Vp-p
--0.5 Vp-p
---T-
1 Vp-p
VII
tlPC1364C2
TEST CIRCUIT 2
COLOR
VR22
5.1 kQ
3.3 kQ
.r
3.3 kQ
3.9 kQ
MAX.
MIN.
CONTRAST
VR19
VCC=12 V
0 01
. ,uF
3.3 kQ
5.6 kQ
68 pF
47 pF
1.8 kQ
0.47.,uF
JUL
--.JLlL
LINE PULSE
GATE PULSE
2.2 ,uF
47 Q
~CAM
75
QJ
S.G.
497
~
1.4 V
I
I·
I
I
tl
I
I
.1
I
I
t2 I
__________________~I~I
I
I
1.4 v-~-
I
1-- - +- I
I
I
I
I
SECAM Burst Gate Pulse
Level> 0.7 V
I
I.
I
--r'-------
I
I
I
I
:
I
:4.9
I
. . -1
I
_I
I
II,
I
I I I
-1 I I.. I as. - I I~s-
I
I
I
I
I
O'7v-~i~--~~
I
_____________-J....I_.....J
500
luJ______
J.LPC1364C2
VCC= 12 V
33 kQ
VCC=12 V
470
~~g
Q
Level
0.01 JlF
, LS,
L7
Contrast
~ ~
,
0.01
, JlF
10 kQ
Vl
Vl
Q}
E
.s=
OIl
J5
Sub
390 Q
Brightness
· nal
Video Input SIg
Composite Video
I
Signal
I
47Q33pF
~I'
~
_1_
~-1
Vp-p
V--Ll~lack
I~
Level = 10 VDC
R
.--+--
G
...--+---+-- B
1:
-g
Blanking
0.01 JlF-'- 6.S kQ LlO
1
Burst Gate
Pulse
Pulse
3.3 kQ x3
o
....a
W
en
~
o
N
01
o
JLPC1364C2
PAL·SECAM DUAL SYSTEM
VCC=12 V
Burst Gate Pulse(PAL)
tl PC 1365C( PAL)
47 JlF
Composite
Video Signal
§]
r:;;l
VC_C_=-11~2_V..-_ _ _-+--.._-,
100
~ f~O.OlJlF
q
o
{
"'-
0
100
Q
ex
~~-----------~-+~~--~~~
Q
0
10
kQ
Color Level(PAL)
LL.
Co
L2
220
Q
2.2 JlF
r-~~----~~~r------+~
tl PC 1364C2(SECAM)
L8
L7
~~-~--"-~-r----~~
Brightness
R
G
'-+--+--B
6.8 kQ LID
Io.01
502
JlF
Burst Gate
Pulse(SECAM)
Pulse
-'"
jlPC1364C2
L 1 1 H D. L. Matching
Input Coil
(PAL, SECAM)
Type No. TKRNS - 24984NK (Pink Core)
Taka Corp.
(])
o
fa;
6-4;
C out;
au;
Wire Material;
CD
4.43 MHz
18T
330 pF (4 - 6)
59 ± 20 %
0.1/UEW
L2 1 H D. L. Matching
Output Coil
(PAL, SECAM)
~
~
Type No. TKRNS - 24985VN (Black Core)
Taka Corp.
fa;
4-2;
2-6;
C out;
au;
Wire Material;
4.43 MHz
18T
18T
75 pF (4 - 6)
44 ± 20 %
0.1 /U EW
L3 Chroma Input Coil
(PAL)
Type No. 163NEF - 1148 WWJ (No Core)
Taka Corp.
fa;
6 - 4;
3 - 1;
C in;
Wire Material;
4.43 MHz
35 % T
76 T
47 pF
0.1/UEW
L7 (B-Y) Demodulator
(SECAM)
:\JV4
r®... ..
CD
CD
Ji)""'
®
Type No. TKRES - 25656AYC (Yellow Core)
Taka Corp.
fa;
3 - 4;
C in;
au;
Wire Material;
4.25 MHz
33 % T
82 pF (3 - 4)
75 ± 20 %
0.1/0UEW
503
j.lPC1364C2
L8 (R-Y) Demodulator
(SECAM)
Type No. TKRES - 25658AYK (Green Core)
Toko Corp.
®
)
fo;
3 - 4;
C in;
au;
Wire Material;
4.406 MHz
32 Y2 T
82 pF
75 ± 20 %
0.1/OUEW
L9 Be" Filter
(SECAM)
Type No. TKRNS - 25657 A YC (Red Core)
Toko Corp.
3-4;
C out;
au;
Wire Material;
19YzT
220 pF
70 ± 20 %
0.12/0U EW
L 10 Ident Detector
Type No. TKR ES - 25659A YC (Orange Core)
TokoCorp.
fo; 4.406 MHz
3 -4; 39 Yz T
®J
504
C in
au
Wire Material
68 pF
63 ± 20 %
0.1/OUEW
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1365C
PAL CHROMINANCE AND LUMINANCE PROCESSOR
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
pPC1365C is a luminance and chrominance stage LSI for PAL system TV sets. It contains luminance amplifier, chroma IF
amplifier, sub-carrier oscillator, PAL switching circuit, chroma demodulator, matrix circuit, and the other necessary additions.
It puts out R,G,B primary colors. This LSI restores 100 % of the DC level. And it is easy to adapt remote control system to
"BRIGHTNESS", "CONTRAST", and "COLOR SATURATION", as the control terminals are designed to high impedance.
FEATURES
•
•
•
•
•
•
•
PACKAGE DIMENSIONS in millimeters
This LSI has built-in function for PAL-SECAM dual system.
1) Two ICs construction by NEC's SECAM IC pPC1364C2.
3&0 MAX.
2) Only one 1-H delay line is required for dual system.
3) Automatically switchable function for PAL/SECAM signals.
This LSI can process both of the chrominance and the luminance
signals.
Due to DC control method for color, contrast, and brightness
control, the wiring is rather easy and the expansion to remote
control receiver are also rather easy.
The level of color killer circuit can be adjusted from the outside and
the color killer circuit has proper hysterisis characteristics.
The input circuit requires only a band pass filter and 4.43 MHz
trap. Furthermore, the demodulated outputs are R,G,B signals.
So that the chroma output stages are quite simplified.
The contrast control can automatically adjust the levels of chroma
and contrast- luminance signal under the relation that the normal picture is always kept.
The output terminals of demodulated chroma signals and all input circuits are protected by the surge protection diode.
IC BLOCK DIAGRAM
505
JlPC1365C
TV BLOCK DIAGRAM
Speaker
PIN CONNECTION (Top View)
Power Supply
28
G Output
Blanking Input
2
27
B Output
Capacitor
(Pedestal Clamp)
3
26
R Output
Brightness
Control
4
25
B-Y Demo Input
Luminance Input
5
24
R-Y Demo Input
6
23
Line Pulse Input
Contrast Control
7
22
Oscillator Input
Color Control
8
21
Oscillator Input
Chroma Output
9
20
Oscillator Output
Capacitor
10
19
Burst Gate Pulse Input
18
A.P.C. Filter
Capacitor
(Emitter Peaking)
(By-Pass)
Chroma Input
506
A.C.C. Filter
A.P.C. Filter
Killer Filter
Burst Input
(A.P.C., Ident Killer)
GND
Burst Output
,uPC1365C
J,lPC1365C Standard Using Conditions
Supply Voltage
12
V
100
mVp.p
Chrominance Input Signal
(Burst Signal Level)
Luminance Input Signal
1
Vp-p
Gate Pulse Input Level
3
Vp
H. Pulse Input Level
3
Vp
Blanking Pulse Input Level
3
Vp
Demodulator Chrominance Input Signal
0.2
Vp-p
R,G,B Output Voltage (Black Level)
2.0
V
Color Saturation Controlling Voltage
o to 12
o to 12
o to 12
V
Contrast Controlling Voltage
Brightness Controlling Voltage
ABSOLUTE MAXIMUM RATINGS (Ta
Supply Voltage
. Power Dissipation
Vee
Pd
V
V
= +25 °c Unless otherwise)
(Ta
= +70 DC)
15
V
750
mW
Vp-p
V
Signal Input Voltage
ej
5
Pulse Input Voltage
ep
±6
Operating Temperature
Topt
Tstg
Storage Temperature
-20 to + 70
-40 to + 125
°c
°c
507
J,lPC1365C
ELECTRICAL CHARACTERISTICS (Ta
NO
CHARACTERISTIC
= 25°C unless otherwise noted, Vee = 12 V)
SYMBOL
TEST
CKT
MIN.
TYP.
MAX
UNIT
TEST CONDITION
1
Burst Output Voltage
eb
1
0.9
1.2
1.6
V _
pp
Input 100 mV p _p
Rainbow color bar signal
2
ACC Range
ACC
1
0.6
0.8
1.0
times
Input 10 mV p _p
Burst Outputl eb
3
Chroma Output Voltage 1
e c1
1
0.5
0.7
1.0
Vp-p
Input 100 mV p _p
Rainbow color bar signal
Saturation control MAX
4
Chroma Output Voltage 2
e c2
1
V _
pp
Input 100 mV p _p
Rainbow color bar signal
Saturation control MID
5
Chroma Output Voltage 3
e c3
1
6
mVp-p
Input 100 mVp _p
Rainbow color bar signal
Saturation control MIN
6
Killer Sensitivity
ek
1
-34
-40
-46
dB
7
Killer Hysterisis
ekh
1
-
1
2
dB
0.2
o dB = Input 100 mVp _p
508
Rainbow color bar signal
Killer ON Input level
Killer ON-OFF Input level
8
Oscillator Controlling Sensitivity
{3
2
1.3
1.8
2.3
Hz/mV
Measure Vp Voltage at
Burst frequency fo ± 100 Hz
9
Phase Detector Sensitivity
J.l
2
20
40
60
mV/degree
Measure Vp Voltage at
Burst frequency fo ± 100 Hz
10
Phase error
AI/>
2
-
1.5
3.0
degree/100 Hz
Burst frequency fo ± 100 Hz
11
APC Pull-in frequency Range
fp
2
±300
±500
-
Hz
Changing frequency of
Burst signal
12
APC Detector Output balance
Voltage
Vp
2
-100
0
+100
mV
No Input signal at Pin 16
13
B-Y Output Voltage
e0 1
1
1.5
2.0
2.5
V _
pp
Input 0.2 Vp-p f = 4.44 MHz
10 kHz beat Output signal
14
Ratio of R-Y to B-Y
RIB
1
0.49
0.56
0.63
times
Input 0.2 V p _p f = 4.44 MHz
10kHz beat Output signals
15
Ratio of G-Y to B-Y
G/B
1
0.30
0.34
0.38
times
Input 0.2 Vp-p f = 4.44 MHz
10kHz beat Output signals
= 4.44 MHz
= 4.44 MHz
= 4.44 MHz
16
Relative Output Phase B-Y to R-Y
LR
1
85
90
95
degree
Input 0.2 V p _p f
17
Relative Output Phase B-Y to G-Y
LG
1
228
236
244
degree
Input 0.2 V Pop f
18
Maximum Color Difference
Output Voltage
e02
1
4.5
5.5
-
V _
pp
19
Output Residual Carrier level
e car
1
-
-
100
mVp_p
20
Overall color
Difference Output
Voltage at B-Y signal
e0 3
1
1.0
1.7
2.5
V _
pp
21
Overall color
Difference Output Variable
Range by. Contrast
e oc
1
15
17
19
dB
Input 100 mV p _p
Rainbow color bar signal
Contrast control MAX/MIN
22
Luminance Gain
Av1
1
4.1
4.6
5.1
times
Input 1 V p _p
Color bar 100 % White signal
Contrast control MAX
Input 1.2 Vp-p f
10 kHz beat Output signal
at B-Y Output Pin
No Input signal at Pin
24 and 25
Saturation control MID
Input 100 mV p _p
Rainbow color bar signal
Contrast control MAX
tlPC1365C
TEST
CKT
MIN.
TYP.
MAX
UNIT
TEST CONDITION
AAvl
1
-
1.0
1.1
times
Input 1 V p _p
Color bar 100 % White signal
Contrast control MAX
Luminance Gain Variable Range
by Contrast
e vc
1
15
17
19
dB
Input 1 V p _p
Color bar 100 % White signal
Contrast control MAX/MIN
Differential Gain
D.G.
1
-
-
6
%
Input 1 V p _p
Stair step signal
RGB Output, Black level
NO
CHARACTERISTIC
23
Relative Ratio of Luminance Gain
24
25
SYMBOL
=2 V
Input 1 Vp-p
Stair step signal
AP L = 10 to 90 %
26
DC Restoration
TDC
1
90
95
100
%
27
Luminance Amp Frequency
Characteristic
fv
1
4.0
5.5
-
MHz
28
Brightness Controlling Sensitivity
BR
1
3.8
4.3
4.8
-
Quiescent Output Voltage
2 to 5V, (V26, V27, V28)
Sensitivity 3 V/AV4
29
Maximum R,G,B Output Voltage
EOM
1
7
-
-
V
Brightness Controlling
Voltage = 12 V
Input 0.1 Vr.m.s.
Sine wave signal, -3 dB down
Pin 6 open
=
~O
Quiescent Output Voltage
Eo
1
2.5
3.3
4.1
V
No Luminance Input signal
Brightness V4 = 9 V
Contrast MAX
VCO operating
31
Quiecent Output Voltage
Temperature Coefficient
EO-T
1
-2
0
+2
mVfC
R,G,B Output
Ta = -20 to +70 °c
V26 = 3.5 V at Ta = 25°C
32
Difference Output Voltage
{ER-G
EG-B
EB-R
Ex -y
1
-300
0
+300
mV
V26 = 3.5 V
VCO operating
33
Difference Output Voltage
Temperature Coefficient
AEx.y/AT
1
-
0
60
mV
26
Ta
34
Supply Current
ICC
3
32
43
54
mA
35
Changing Black level by Contrast
AEoc
1
-100
0
+100
mV
36
Minimum Gate Pulse Input Voltage
VG (min)
-
-
2
V
Pin 19
37
Blanking Pulse Input Voltage
Range
VB
1.8
-
5
V
Pin 2
38
Minimum FF Trigger Input Voltage
VFF (min)
-
-
1.5
V
Pin 23
= 3.5 V at Ta = 25°C
= -20 to +70°C
VCC = 12 V
No Luminance Input signal
V26 = 2 V at Contrast MAX
Contrast control MAX/MIN
509
UI
o
1::
"'0
pPC1365C TEST CIRCUIT 1
1
VC~:~2 kVO
O} 0~7
ec
OFF
n
ON- OFF
...Ii
W
en
en
8
S-8
To Pin 9
To
.01JlFl kQ
l2
VCC=12 V
0.022
STOP
G
Pin23
E;~
S-7
--ro--Oev
R
To
Pin 13
n
ON
I
~I
Oe 8
I
I
I
I
3.3 kQ
1 kQ
0
I S-12
I
8 I
4.7 J.tF
°1
oR~e03
I'"'
---v
3.3 kQ
°
eb
0.01
0--11
~
~
~-H-I-0-0-PF-III~
JlF
S=:~OO
h
nON
-;W
I
I
I
JLPC1365C
1r
S-lO
cl
0.01 .F
I
S;goa'
1
Generator
~ S_4/
0
::t.
0....
ON
S-2
b
hv
. IilL.fl n
I,j,.
NOR~
Input A
8
I
INVERT
:3
I
I0
:
a
TP
©1
o--w.r-,
56 k
OFF
o~
d
~
1.5 k Q I ~
10 kQ
,/,/
./
./
,/
~ecar
R
J~
G
o
I
ON ), OFF
o
I
,/
,/
I
I PAL
I
14 13 12
7TT
8
° PAlISECAM
I
VCC=12 V
68 kQ
120 pF
Input
)
./
,/
I
5.6 kQ
I
I
rJr
I VCC=12 V
pF
I
330 Q
330 PF~
PAl~
~
Go II
~~--~
~PAl/SECAM
8.8 MHz Trap
S-11
MAX.
d
S-5
VCC=12 V
VR-l
::t.
o0
....
7fT
0
ON
---o----------------~
S-3
TP2 Cd
OFF
S-6L--..o--
1
JI0 JiF
0.01 JlF
r
ONq
-S-Power
OFF 0
47 JlF
VCC=12 V
MID
1.5 kQI1.5 kQ 15 kQ
6
GND
j.lPC1365C
/JPC1365C Signal Generator (TEST CI RCU IT 1)
VCC=12 V
Luminance
Composite
Input Signal
10 Jlf
V Output
~I
LJ
1 Vp-p
2.2 JlF
680 PF.Lm-
GND
o--m-
1
470 Q
2
560 kQ
3
22
4
5
20
(.)
......
6
(Y)
.....
7
a..
8
1.0
(.)
::t.
10
11
1000 pF
27 kQ
S-14
6.8 kQ
15
Burst Gate Output
0:
.:.:;
14
N
-1Lpulse
(.)
N
en
220 pF
"<:t-
12
C
11
b
0
"<:t-
o
a..
::t.
10
9
H. Output Pulse
I~
! I
LWJ
L.=f-c
Burst Signal
3.5
JlS
I
I
~H.pulse
51
j.lPC1365C
IlPC1365C TEST CIRCUIT 2
VCC=12 V
0.022 J.lF
VCC=12 V
+
o~------~~----~
eose
27
25 24
23
22
21
20 19
18 17
OFF 0
16
100 pF
,uPC1365C
234
S-Power
ON o-----+-......
47 J.lF
VCC=12 V
o
OFF
0.47 J.lF
7.5 kQ
VCC=12 V
~
GND
S-16
+f
fo 0 --0---.
-f
B'urst Signal
Signal
Generator
(See next page)
Qref
512
Pulse
)lPC1365C
pPC1365C Signal Generator (TEST CI RCUIT 2)
Pulse
2.2 kQ
6.8 kQ
JLPD4049C
2.2 kQ
2345678
VCC=12 V
10 kQ
\ 1 500 pF 1 000 pF
Gate frequency Burst Signal Width
S-16
ADJ
Gate Pulse
10 kQ Width ADJ
ADJ
Burst Signal
27
26 25
24
23 22 21
20 19 18 17
16
15
12 13
14
JLPC1365C
7
10 11
8
u..
::t
2.2 }.IF
~I
h
0
ci
u..
::t
a
.>C
56 kQ
VCC=12 V
513
)lPC1365C
~PC' 365C TEST Circuit 3
Open
13 kQ
c
c
13 kQ
c
19 18 17 16
15
,uPC1365C
7
8
r
1 JlF
VCC=12V----~~~----+_~~--r_----~----------------------~
c
75 kQ
c
----------J
VOC=4 V_____
514
,uPC1365C
~
eb
ACC
e cl
e c2
e c3
ek, ekh
e ol
RIB
G/B
LR
S-l
Input
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
ON
S-2
Lum
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
S-3
Lum
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
S-4
Chro.
ON
ON
ON
ON
ON
ON
OFF'
OFF
OFF
OFF
S-5
Cont.
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
S-6
Satu.
MID
MID
MAX
MID
MIN
MID
MID:
MID
MID
MID
S-7
VCO
NORM
NORM
NORM
NORM
NORM
NORM
NORM
NORM
NORM
NORM
S-8
FF.
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
S-9
Dem.
INT
INT
INT
INT
INT
INT
EXT
EXT
EXT
EXT
S-10
Syst.
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
S-12
Output
B
B
B
B
B
B
B
R
G
R
S-13
Output
eo3
e o3
e o3
eo3
e o3
e o3
e o3
e o3
e o3
e o3
S-14
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
D =SG
D=SG
D=SG
S-ll
Blk
I
VR-l
Be trimmed V26 = 3.5 V by Brightness VR (VR-l)
VR-2
Input
A
A=SG
A
A
A
B-C=ATT
SG
Measure
Point
D =SG
A=SG
B - C = ATT
Rainbow
eb
ec
eb
f = 4.44 MHz
ec
ec
ec
e o B,e o 3
eoB
e o B,e o 3
Phase
Meter
Oscilloscope
I
ATT
I
e o B,e o 3
I
ATT
I
I
AC Volt meter
515
j.lPC1365C
~
LG
e o2
eear
e o3
e oe
S-1
Input
ON
ON
ON
ON
ON
S-2
Lum.
INV
INV
INV
INV
S-3
Lum.
OFF
OFF
OFF
S-4
Chro.
OFF
OFF
S-5
Cont.
MAX
S-6
Satu.
S-7
VCO
~Av1
eve
DG
TDC
fv
ON
ON
ON
ON
OFF
INV
INV
INV
INV
INV
NORM
OFF
OFF
ON
ON
ON
ON
ON
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
MAX
MAX
MAX
MAX,MIN
MAX
MAX,MIN
MAX
MAX
MAX
MID
MID
MID
MID
MID
MID
MID
MID
MID
MID
NORM
NORM
NORM
NORM
NORM
STOP
STOP
STOP
STOP
STOP
S-8
FF.
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
S-9
Dem.
EXT
EXT
EXT
INT
INT
EXT
EXT
EXT
EXT
EXT
S-10
Syst.
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
S-11
Blk
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
S-12
Output
G
B
BRG
B
B
BRG
B
BRG
B
BRG
S-13
Output
e o3
e o3
e o3
e o3
e o3
ev
ev
ev
ev
ev
S-14
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
VR-1
Be trimmed V26 = 3.5 V by Brightness VR (VR-1)
Avl,
Be trimmed V26 = 2 V by Brightness VR (VR-1)
V26 = 3.5 V
VR-2
Input
SG
Measure
Point
D=SG
f = 4.44 MHz
eoB, e o3
Phase
Meter
516
D=SG
eoB
-
A
A
eear
Rainbow
e o3
A
A
A
Stair Step
Video SG 100 % White
e o3
Oscilloscope
ev
ev
A
ev
Vector
scope
C=SG
SG=CW
ev
Oscilloscope
ev
RF
Volt meter
j.lPC1365C
~
BR
EoM
Eo. Eo-T
* Ex-y
AEx_y/AT
AEoc
5-1
Input
ON
ON
ON
ON
ON
5-2
Lum.
INV
INV
INV
INV
INV
5-3
Lum.
OFF
OFF
OFF
OFF
OFF
5-4
Chro.
OFF
OFF
OFF
OFF
OFF
5-S
Cont.
MAX
MAX
MAX
MAX
MAX,MIN
5-6
5atu.
MID
MID
MID
MID
MID
5-7
VCO
NORM
NORM
NORM
NORM
NORM
5-8
FF.
OFF
OFF
OFF
OFF
OFF
5-9
Oem.
EXT
EXT
EXT
EXT
EXT
5-10
5yst.
PAL
PAL
PAL
PAL
PAL
5-11
Blk
OFF
OFF
OFF
OFF
OFF
5-12
Output
BRG
BRG
BRG
RG
B
5-13
Output
e o3
eo3
eo 3
e o3
e o3
5-14
ON
ON
ON
ON
ON
VR-l
5ee TE5T
Condition
TP = VCC
TP=9 V
V26=
3.SV
Eo3
e o3
eo3
e o 3. e ov
V 26
VG (min)
VB
VFF
PAL
PAL
PAL
=2 V
VR-2
Input
5G
Measure
Point
eo 3
DC Voltmeter
517
jlPC1365C
----S-15
fo ±f
{3
J.I.
A¢
fp
Vp
ON
ON
ON
OFF ON
ON OFF
OFF
+f (300 Hz)
-f (300 Hz)
fo
eref, eosc
eref
Vp
Phase Meter
f.Counter
f.Counter
DC Voltmeter
+f (100 Hz)
-f (100 Hz)
S-16
Burst
Measure
Point
SIS
Vp
Vp
eref
eref, e osc
f.Counter
DC Voltmeter
Phase Meter
f.Counter
DC Voltmeter
JlPC1365C
J.LPC1365C Input and Output signals
Luminance Input Signal
/
White level
R19
R20
470 Q 1 'kQ
Luminance Delay Line
:-1
I
I
I
RIO
I
11T" l.8 k Q
f
4.43 MHz Trap
R18
47 Q
C25
100 pF
Band Pass Filter
14-_--f
'----------/-,--------10
om
pF
1
mI I I I I I I I I~I I I I I at
Output Signal
Terminal 11
100 mVp-p
(Burst Signal)
1
White
---------,
I
I
I
3.5 Vp-p at Luminance
J
I
I
I
I
I
7!!
________
.--1I
Terminal 26. 27. 28
R31
\
R33
U
Input =1 Vp-p
Contrast MAX.
Black
--OV
Black level
=2 V
(Controled by the brightness. control)
519
)lPC1365C
pPC1365C Input Pluse
Burst Gate Pulse
Burst signal = 100'" 200 mVp-p
at Terminal 11
~IIIII :~-EI
I
I
I
Inl
-------'.
2!3 vp
L - ._ _
--1 I--
.....It~ 0 v
4.5 - 3
Terminal 19
pS
Line Pulse
n
------~.
t
1 -2 Vp
L - ._ _ _ _
~t_ov
Terminal 23
Blanking Pulse
(Line Pulse and
Field Pulse)
t
2 - 5 Vp(Max. 5 Vp)
,---~~-o v
I
I
In case of commonly
using of Input Pulse
I
I
I
I
I
I
I
I
Terminal 19
___--'rll--__
4.7 kQ
Terminal 23
520
JlPC1365C
J.lPC1365C
*Color, Contrast and Brightness controlling circuit
VR 1
Brightness Control
VR102
Sub Brightness
V R2
Contrast Control
V R 103
Sub Contrast
VR3
Color Control
VR104
Sub Color
I
VCC=12 V
I
I
I
I
Terminal 7
8
VR1
VR2 ~........J\M-----"------{
VR3
I
I
IL __________ _
VR102
VR103
VR104
V7 (Contrast)
5.5 to 7.0 to 8.5 V
V8 (Color)
4.0 to 5.5 to 7.0 V
V2 (Brightness)
8.2 to 8.7 to 9.2 V
Terminal 4
*Color Killer Setting VR105
* APC Setting
Method;
1; Connect Resistor (100 kU) between the Terminal 13 and GND
as shown Fig. 1 (Killer OFF)
Terminal 13
2; Connect Capacitor
100 kQ
(0.01 J.lF) between the
Terminal 16 and GND as
Fig 1
shown Fig. 2 (Burst Input OFF)
r
~I---Il~O
3; Trim 4.433618 MHz by
0.01 pf
using VR107
Term;n,1 16
Fig 2
* 1H Delay Line Circuit
VCC=12
v
VR101
1 kQ
C1
0.01 JlF
Terminal 24
, - . - - - - - - - . . . - - - - (R-Y)
@
R4
®
®
2 kQ
L - -_ _ _ _ _~--_Terminal
L1
Chrominance 1H Delay Line
25
(B-Y)
L 1 ; Pre Chrominance Delay Line Terminating Coil
L2, VR 101 ; Delay Phase and Amplitude Adjustment
V R 106 ; Sub carrier Phase Adjustment
521
OJ
I\)
I\)
):::
The Block Diagram and External Components for Il PC1365C
"'tJ
o
...I
W
VCC=12 V
Burst Gate
Pulse
0)
en
o
.--+----+B
R31-33 3.3 kQ
R34-36 270 Q
Composite Signal
Input
RI9
R20
D.l.
C7
470 Q
RIO
1.8 kQ
L5 4.43 MHz
Trap
lUI
RI8
C25
47 Q
100~PF
C24
120 p
"
:
I _ _ _:
L--..-.tl
APC
VRI07
4.7 kQ
• CI8 0.02 JLF
Killer
VRI05
4.7 kQ
R4
2 kQ
Trl 2SA733
Phase
CII 0.01 JLF
CIO 0.01 JLF
C9 0.01 JLF
C6
10 JLF
RI3
68 kQ
R30
Line Pulse
Brightness
VRI 10 kQ
Color
VR3 10 kQ
Contrast
VR2 10 kQ
L6 8.2 JLH
R29 1.5 kQ
CI9 39 pF
C20 47 pF
tlPC1365C
Printed Circuit Board Pattern (Bottom View)
R.B.G Output
VR107 "
L2
Xtal
CIS
-~ R2~C2::8l T~
.~
--:-f
VRI06
Burst Gate
Pulse
~
L4 1
---A/I.f.rlC16
T
T
C26
ff
l&iL6
R33
I
C19
R27
¥+••
I
I
I
Line Pulse
R30
VR1£!.~ C~'R2
"'NY- t J.
. R36
\ ... ,
*
1-
R4$ [~J
R35
.1i::'9 ~4
d0 R26
R24
t
C:l
R32 R31
Rl
, "
t 'f +"1< I)
1
1
I
I
1"
C.11
r--c::J--,. I
S
RIO
R3
r
1,1
I
I L:.....J
I
I 1H D.L.
L_c_.J
fJ,t -tR~1 ~:
IC3T
loC8
1T
if
R17
''t~
t
-Wt-I C9
, VR3
-wr
Rl:
1t
P'.
1.
VR2
VRI02
1;--1
~25 !I
R9
-tiC24....1f!1rr
-w.-
..
R6"
~,J 1~R7t f: r---l1~
t
VRI03
VCC
I
i
Composite Signal
4.43 MHz
L5
I..: ___ ..J
Blanking Pulse
Ground
f ~~;
fR20
L-D.L.
VRI
,uPC1365C Table of the external components
Symbol
R1
R2
R3
R4
R5
R6
R7
R8
R9
RIO
Rll
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
Value
100 Q
100 Q
390 Q
2 kQ
(56 kQ)
(3.9 kQ)
2.7 kQ
5.6 kQ
68 kQ
1.8 kQ
33 kQ
33 kQ
68 kQ
39 kQ
22 kQ
68 kQ
5.6 kQ
47 Q
470 Q
1 kQ
68 kQ
470 kQ
4.7 kQ
27 kQ
27 kQ
1 kQ
(1.2 k12)
1 kQ
1.5 kQ
0.2 kQ)
3.3 kQ
3.3 kQ
3.3 kQ
270 Q
270 Q
270 Q
Symbol
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
Value
0.01 pF
0.01 pF
47 pF
0.01 pF
4.7 pF
10 pF
10 pF
10 pF
0.01 pF
0.01 pF
0.01 pF
0.01 pF
1 pF
0.47 pF
47 pF
100 pF
0.022 pF
0.022 pF
39 pF(Xtal CL = 16 pF),
68 pF(Xtal CL = 20 pF)
47 pF
18 pF
Symbol
VR-1
VR-2
VR-3
Value
10 k Q Brightness
10 k Q Contrast
10 k Q Color Saturation
VR101
VR102
VR103
VRI04
VR105
VR106
VR107
1 kQ D ' .. Level
4.7 k Q Sub Brightness
47 k Q Sub Contrast
47 k Q Sub Color Saturation
4.7 k Q Killer Adj
1 kQ Phase Adj
4.7 kQ APC Adj
L1
L2
L3
L4
L5
L6
D.l. Matching Coil Type No TKRNS 24984NK (Toko Corp.)
D.l. Matching Coil Type No TKRNS 24985VN (Toko Corp.)
Band Pass Filter Type No 163NEF1148WWJ (Toko Corp.)
33 pH
4.43 MHz Trap Type No LCS2HIH·102 (TDK Corp.)
8.2 pH
Tr1
Xtal
L·D.L.
1 H D.L.
2SA733
4.43 MHz
Luminance
1 H Delay
(NEC)
CL =16 pF or 20 pF
Delay Line Type No CTS·1804C (Showa Densei Corp.)
Type No EFD EN (Matsushita Corp.)
Line
120 pF
100 pF
4.7 pF
523
tlPC1365C
1 H Delay Line Matching Coil Specification
L 1 Input Coil
(PAL)
CD
Type No.
TKRNS - 24984N K
Product
TaKa Corp.
fo
4.43 MHz
CD
6-4
18 T
Cout
330 pF (4 -6)
G)
au
59 ± 20 %
Wire Material; 0.1 1 UEW
L2 Output Coil
Type No.
TKRNS - 24985VN
Product
TaKa Corp.
fo
4-2
4.43 MHz
18 T
2-6
18 T
Cout
75 pF (4 -6)
au
44 ± 20 %
Wire Material; 0.1 12UEW
Chrominance Input Coil Specification
L3 I nput Coil
(PAL)
Type No.
163NEF - 1148WWJ
Product
TaKa Corp.
fo
4.43 MHz
6-4
35114 T
3 -1
76T
Cout
PH 47 pF
Wire Material; 0.1 1 UEW
524
BIPOLAR ANALOG INTEGRATED CIRCUIT
p.PC1384C
PAL CHROMINANCE AND LUMINANCE PROCESSOR
SILICON BIPOLAR MONOLITHIC INTEGRATED CIRCUIT
DESCRIPTION
IlPC1384C is a luminance and chrominance stage LSI for PAL system TV sets. It contains luminance amplifier, chroma IF
amplifier, sub-carrier oscillator, PAL switching circuit, chroma demodulator, matrix circuit, and the other necessary additions.
It puts out R,G,B primary colors. This LSI restores 75 % of the DC level. And it is easy to adapt remote control system to
"BRIGHTNESS", "CONTRAST", and "COLOR SATURATION", as the control terminals are designed to high impedance.
FEATURES
PACKAGE DIMENSIONS
in millimeters
• This LSI has built-in function for PAL-SECAM dual system.
1) Two IC's construction by NEe's SECAM IC IlPC1364C2.
2) Only one l-H delay line is required for dual system.
3) Automatically switchable function for PALISECAM signals.
• The black level moved by the contrast control circuit.
•
Luster is provided even in a vacant channel by the 75 % DC restoration.
• This LSI can process both of the chrominance and luminance signals.
•
Due to DC control method for color, contrast, and brightness
control, the wiring is rather easy and the expansion to remote
38.0 MAX.
-t:~~::::1
1 2345 67891011121314
C'!
U
32
.
~!t25.g:,M
-I!-0.5±O.1
control receiver are also rather easy.
2.54!
~
~
o· -15'
• The contrast control can automatically adjust the levels of chroma
and contrast-luminance signal under. the relation that the normal picture is always kept.
• The output terminals of demodulated chroma signals and' all input circuits are protected by the surge protection diode.
IC BLOCK DIAGRAM
525
,uPC1384C
TV BLOCK DIAGRAM
Speaker
v.
Out
PIN CONNECTION (Top View)
Power Supply
28
G Output
Blanking Input
2
27
B Output
Capacitor
(Pedestal Clamp)
3
26
R Output
Brightness
Control
4
25
B-Y Demo Input
Luminance Input
5
24
R-Y Demo Input
6
23
Line Pulse Input
Contrast Control
7
22
Oscillator Input
Color Contro I
8
21
Oscillator Input
Chroma Output
9
20
Oscillator Output
Capacitor
10
19
Burst Gate Pulse Input
Chroma Input
11
18
A.P.C. Filter
A.C.C. Filter
12
17
A.P.C. Filter
Killer Filter
13
16
Burst Input
(A.P.C., Ident ,Killer)
GND
14
15
Burst Output
Capacitor
(Emitter Peaking)
(By -Pass)
526
,uPC1384C
pPC1384C Standard Using Conditions
Supply Voltage
12
V
100
Chrominance Input Signal
Luminance Input Signal
1
mvp_p
Vp_p
Gate Pulse Input Level
3
Vp
H_ Pulse Input Level
3
Vp
Blanking Pulse Input Level
3
Vp
Demodulator Chrominance Input Signal
0.2
V p _p
R,G,B Output Voltage (Black Levei)
2.0
V
Color Saturation Controlling Voltage
o to 12
o to 12
o to 12
V
(Burst Signal Level)
Contrast Controlling Voltage
Brightness Controlling Voltage
ABSOLUTE MAXIMUM RATINGS (Ta
Supply Voltage
Vee
Power Dissipation
Pd
Signal Input Voltage
ej
Pulse Input Voltage
ep
Operating Temperature
Storage Temperature
V
V
= +25 °c Unless otherwise)
15
V
750
mW
5
V p _p
±6
V
T opt
-20 to +70
T stg
-40 to +125
°c
°c
(Ta=+70°C)
527
tlPC1384C
ELECTRICAL CHARACTERISTICS (Ta = 25°C unless otherwise noted, Vcc = 12 V)
NO
CHARACTERISTIC
SYMBOL
TEST
CKT
MIN.
TYP.
MAX
UNIT
TEST CONDITION
1
Burst Output Voltage
eb
1
0.9
1.2
1.6
V p _p
Input 100 m V p _p
Rainbow color bar signal
2
ACC Range
ACC
1
0.6
0.8
1.0
times
Input 10 mv p _p
Burst Output/eb
3
Chroma Output Voltage 1
e c1
1
0.5
0.7
1.0
Vp-p
Input 100 mvp _p
Rainbow color bar signal
Saturation control MAX
4
Chroma Output Voltage 2
e c2
1
V _
pp
Input 100 mvp _p
Rainbow color bar signal
Satu ration control MID
5
Chroma Output Voltage 3
e c3
1
6
mvp _p
Input 100 mV p _p
Rainbow color bar signal
Saturation control MIN
6
Killer Sensitivity
ek
1
-34
-40
-46
dB
7
Killer Hysterisis
ekh
1
-
1
2
dB
0.2
o dB = Input
528
100 mvp _p
Rainbow color bar signal
Killer ON Input level
Killer ON-OFF Input level
8
Oscillator Controlling Sensitivity
(3
2
1.3
1.8
2.3
Hz/mV
Measure V p. Voltage at
Burst frequency fo ± 100 Hz
9
Phase Detector Sensitivity
J.L
2
20
40
60
mV/degree
Measure Vp Voltage at
Burst frequency fo ± 100 Hz
10
Phase error
~¢
2
-
1.5
3.0
degree/100 Hz
Burst frequency fo ± 100 Hz
11
APC Pull-in frequency Range
fp
2
±300
±500
-
Hz
Changing frequency of
Burst signal
12
APC Detector Output balance
Voltage
Vp
2
-100
0
+100
mV
No I nput signal at Pin 16
13
B-Y Output Voltage
e o1
1
1.5
2.0
2.5
Vp-p
Input 0.2 V p _p f = 4.44 MHz
10 kHz beat Output signal
14
Ratio of R-Y to B-Y
R/B
1
0.71
0.78
0.85
times
Input 0.2 V p _p f = 4.44 MHz
10 kHz beat Output signals
15
Ratio of G-Y to B-Y
GIB
1
0.30
0.34
0.38
times
Input 0.2 V p _p f = 4.44 MHz
10 kHz beat Output signals
16
Relative Output Phase B-Y to R-Y
LR
1
85
90
95
degree
Input 0.2 V p_p f
17
Relative Output Phase B-Y to G-Y
LG
1
228
236
244
degree
Input 0.2 V p-p
18
Maximum Color Difference
Output Voltage
e o2
1
4.5
5.5
-
Vp-p
19
Output Residual Carrier level
e car
1
-
-
100
mVp-p
20
Overall color
Difference Output Voltage
at B-Y signal
e o3
1
1.0
1.7
2.5
V _
pp
21
Overall color
Difference Output Variable
Range by Contrast
e oc
1
15
17
19
dB
Input 100 mvp~p
Rainbow color bar signal
Contrast control MAXIM IN
22
Luminance Gain
Av1
1
4.1
4.6
5.1
times
Input 1 V p _p
Color bar 100 % White signal
Contrast control MAX
= 4.44 MHz
Input 1.2 V p _p f = 4.44 MHz
10 kHz beat Output signal
at B-Y Output Pin
No I nput signal at Pin
24 and 25
Saturation control MID
Input 100 mVp _p
Rainbow color bar signal
Contrast control MAX
,uPC1384C
TEST
CKT
MIN.
TYP.
MAX
UNIT
~Av1
1
-
1.0
1.1
times
Luminance Gain Variable Range
by Contrast
e vc
1
15
17
19
dB
Input 1 Vp-p
Color bar 100 % White signal
Contrast control MAX/M I N
Differential Gain
D.G.
1
-
-
6
%
Input 1 V p _p
Stair step signal
RGB Output, Black level
NO
CHARACTERISTIC
23
Relative Ratio of Luminance Gain
24
25
SYMBOL
TEST CONDITION
Input 1 V p _p
Color bar 100 % White signal
Contrast control MAX
=2 V
Input 1 V p _p
Stair step signal
AP L = 10 to 90 %
26
DC Restoration
TDC
1
68
75
82
27
Luminance Amp Frequency
Characteristic
fv
1
4.0
5.5
-
MHz
Input 0.1 Vr.m.s.
Sine wave signal, -3 dB down
Pin 6 open
28
Brightness Controlling Sensitivity
BR
1
3.8
4.3
4.8
-
Quiescent Output Voltage =
2 to 5 V, (V26, V27, V28)
Sensitivity 3 V/~V4
29
Maximum R,G,B Output Voltage
EOM
1
7
-
-
V
Brightness Controlling
Voltage = 12 V
%
30
Quiescent Output Voltage
Eo
1
2.7
3.5
4.3
V
No Luminance Input signal
Brightness V4 = 9 V
Contrast MAX
VCO operating
31
Quiecent Output Voltage
Temperature Coefficient
EO-T
1
-2
0
+2
mV/oC
R,G,B Output
Ta = -20 to +70°C
V26 = 3.5 V at Ta = 25°C
32
Difference Output Voltage
RG
EG-B
EB-R
Ex -y
1
-300
0
+300
mV
V26 = 3.5 V
VCO operating
33
Difference Output Voltage
Temperature Coefficient
AEx_y/AT
1
-
0
60
mV
V26 = 3.5 V at Ta = 25°C
Ta = -20 to +70°C
34
Supply Current
ICC
3
32
43
54
mA
VCC
No Luminance Input signal
V26 = 2 V at Contrast MAX
Contrast control MAX/MIN
t
35
Changing Black level by Contrast
~Eoc
36
Minimum Gate Pulse Input Voltage
37
Blanking Pulse Input Voltage
Range
38
Minimum FF Trigger Input Voltage
1
= 12 V
-100
0
+100
mV
VG (min)
-
-
2
V
Pin 19
VB
1.8
-
5
V
Pin 2
VFF (min)
-
-
1.5
V
Pin 23
529
OJ
o'-'>
1::
""C
J,LPC1384C TEST CIRCUIT 1
o
....Ii
VCC=12 V
IhN-OFF~
k:
1
56
0.01 pF
ec
W
00
~
o
0
II
OFF
To Pin 9 ~-H---J\M~
NORMAL
0.01 pFl kQ
ON
B
~;-8 ~
1H
D.l.
o
l2
To
Pin 13
Pin 23
e
30
S--7
--,0----()
ev
01
G
AM
o
VCC=12 V
0
R
To
I
I
STOP
330Q::
330 pi: I
EXT
7Ir
1 kQ
I S-12
I
B I
I
4.7 pF
R
3.3 kQ
--fo---Oe 3
0
G
eb
0.01
()---11
t1l:
~H
~
pF
l---OOFF 120 Q
S-4 ----o-ANv-,
120 PF!
100
II
PFI~
I
I
PAL~
~,},-
-rl-J
1:J
16
o
24 25 26 27 28
)
PALISECAM
VCC=12 V
pPC1384C
5.6 kQ
7
VCC=12 V
68 kQ
/'
o
~
1.5 kQ I 10 kQ
~PAL/SECAM
::t.
o
8.8 MHz Trap
S-l1
l~
OFF
0.01 pF
'"
/'
1
PAL
u..
/'
/ ' '"
R~ecar
S-1O
14 13 12
S-1
A
/'" '"
B
7TT
ON
MAX.
S-5
u..
Input B
8
S-2
h
v
INVERT
MIN. 13.6 kQ
o
ON
NO~
Input A
VCC=12 V
VR-l
8
::t.
Generator
b
::t.
o
u..
Signal
I
I
I
1 ..
~ pF
nON
eoB
~II
Ol-----~
3 kQ
0
ON
-----Or-----------------------------~
I
J
S-3
MID
TP2 (0)
MIN
OFF
10 pF
0.01 pF
r
lONg
OFF 0 S-Power
147 pF
VCC=12 V
4 k Q 11.5 k Q11.5 k Q 15k Q
6
GND
tlPC1384C
pPC1384C Signal Generator (TEST CI RCU IT 1)
VCC=12 V
Luminance
Composite
Input Signal
V Output
~nal
LJ
1 Vp-p
GND
1
2
560 kQ
,-----+-........-1 22
3
4
.--~
20
5
t-:--:--~-------+-.....,
O.ll~F ~3.9 kQ
1/ ~TO.01 JiF
rJr
1 JiF
33 k Q ~
7
f--H-.
AA
T
It.
II
0.01 JiF
=t..
6
3.9 kQ
~
II
"I.
AAf
3.3 k Q1
JiF
k6 ]~
. 7fT 0.01
81--_---~---4-~~
~2.7 kQ
~
10
1
-'-
0.01 JiF
i:r-~~--~
111-~ 000
.. ~27 kQ
pF
7lr
S-14
6.~ kQ
'-~a~~~'w~.-+-~15
~~~
'-- 14
N
~~
4r---~An~,v.--+-~~~
220 pF
rI:
Burst Gate Output
r-------~
3ilr
12
,11
LID
:0
6.8
kQ
2.2 'kQ
7fr
b
n Pulse
~L-
Burst Gate Pulse Width ADJ.
7~-~-~,.~.-~~r~~r.-~~
---~-------~_9__________8~~
10 k Q 10 k Q
H. Output Pulse
I~
! I
WlJ
Burst Signal
~3.5JiS
I
I
~H.pulse
531
)lPC1384C
JlPC1384C TEST Circuit 2
VCC=12 V
0.022 J.lF
30 kQ
1 kQ
VCC=12 V
30 kQ
+
0.022 J.lF
()~--------~~----~
0.01 J.lF
eose
1----0-OFFO
19
25 24 23 22
27
18 17
16
100 pF
j1PC1384C
2
S-Power
3
4
ON f " \ - - - - - - t - - - t
VCC=12 V
7.5 kQ
VCC=12 V
~
S-16
GND
+f
fo 0
----c~-.
-f
Burst Signal
Signal
Generator
(See next page)
532
Pulse
j.lPC1384C
pPC1384C Signal Generator (TEST Circuit 2)
Pulse
2.2 kQ
6.8 kQ
j.lPD4049
2.2 kQ
2
345
6
8
7
330 pF
VCC=12 V
Gate Pulse
10 kQ
\
1 500 pF 1000 pF
S-16
10 k Q Width ADJ
Gate frequency
Burst Signal Width
ADJ
ADJ
~--4-~-------------+----~~-'
1-4
0.01 JlF
Burst Signal
27
26
25
24
23 22 21
20 19 18
17
16
j.lPC1384C
7
10
8
I.L.
:1.
2.2 JlF
~I
12 13
11
14
h
0
0
I.L.
:1.
0
.:r<::
56 kQ
VCC=12 V
533
p,PC1384C
J,LPC1384C TEST Circuit 3
Open
13 kQ
C
C
13 kQ
21
20
19
18 17
10
11 12 13
J.lPC1384C
7
8
r
10 kQ
1 pF
VCC=12V----~~-+----~~~--~----~----------------------~
C
75 kQ
C
VDC=4V----~--------~
534
C;O.OI J.lF
ttPC1384C
~
eb
ACC
e c1
e c2
e c3
ek, ekh
e o1
RIB
G/B
LR
S-1
Input
ON
OFF
ON
ON
ON
OFF
ON
ON
ON
ON
S-2
Lum
INV
INV
INV
INV
INV
INV
INV
INV
INV
INV
S-3
Lum
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
S-4
Chro.
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
S-5
Cont.
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
MAX
S-6
Satu.
MID
MID
MAX
MID
MIN
MID
MID
MID
MID
MID
S-7
VCO
NORM
NORM
NORM
NORM
NORM
NORM
NORM
NORM
NORM
NORM
S-8
FF.
ON
ON
ON
ON
ON
ON
OFF
OFF
OFF
OFF
S-9
Dem.
INT
INT
INT
INT
INT
INT
EXT
EXT
EXT
EXT
S-10
Syst.
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
S-11
Blk
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
S-12
Output
B
B
B
B
B
B
B
R
G
R
S-13
Output
e o3
e o3
e o3
e o3
e o3
e o3
e o3
e o3
e o3
e o3
S-14
OFF
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
D=SG
D= SG
D =SG
VR-1
Be trimmed V26 = 3.5 V by Brightness VR (VR-1)
VR-2
Input
A=SG
A
A
A
D=SG
B-C=ATT
f = 4.44 MHz
Rainbow
SG
Measure
Point
A =SG
A
B - C = ATT
eb
ec
eb
ec
ec
ec
e o B,e o 3
eoB
e o B,e o 3
Phase
Meter
Oscilloscope
I
ATT
I
e o B,e o 3
I
ATT
I
I
AC Volt meter
535
,uPC1384C
~
LG
e o2
e car
e o3
e oc
Avl, ..1Avl
e vc
DG
TDC
fv
5-1
Input
ON
ON
ON
ON
ON
ON
ON
ON
ON
OFF
5-2
Lum.
INV
INV
INV
INV
INV
INV
INV
INV
INV
NORM
5-3
Lum.
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
ON
ON
5-4
Chro.
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
5-5
Cont
MAX
MAX
MAX
MAX
MAX, MIN
MAX
MAX, MIN
MAX
MAX
MAX
5-6
Satu.
MID
MID
MID
MID
MID
MID
MID
MID
MID
MID
5-7
VCO
NORM
NORM
NORM
NORM
NORM
STOP
STOP
STOP
STOP
STOP
5-8
FF.
OFF
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
OFF
5-9
Oem.
EXT
EXT
EXT
INT
INT
EXT
EXT
EXT
EXT
EXT
5-10
Syst.
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
PAL
5-11
Blk
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
5-12
Output
G
B
BRG
B
B
BRG
B
BRG
B
BRG
5-13
Output
e o3
e o3
e o3
e o3
e o3
ev
ev
ev
ev
ev
5-14
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
ON
VR-1
Be trimmed V26 = 3.5 V by Brightness VR (VR-l)
Be trimmed V26 = 2 V by Brightness VR (VR-1)
V26 = 3.5 V
VR-2
Input
SG
Measure
Point
D=SG
f = 4.44 MHz
e o B,e o 3
Phase
Meter
536
D=SG
eoB
-
A
A
e car
Rainbow
e o3
A
A
Stair Step
Video SG 100 % White
e o3
Oscilloscope
ev
ev
A
A
C=SG
SG=CW
ev
ev
ev
Vector
scope
Oscilloscope
RF
Volt meter
JlPC1384C
~
BR
EoM
Eo, Eo-T
*E x-y
dEx_y/dT
dE oc
S-1
Input
ON
ON
ON
ON
ON
S-2
Lum.
INV
INV
INV
INV
INV
S-3
Lum.
OFF
OFF
OFF
OFF
OFF
S-4
Chro.
OFF
OFF
OFF
OFF
OFF
S-5
Cont.
MAX
MAX
MAX
MAX
MAX, MIN
S-6
Satu.
MID
MID
MID
MID
MID
S-7
VCO
NORM
NORM
NORM
NORM
NORM
S-8
FF
OFF
OFF
OFF
OFF
OFF
S-9
Dem.
EXT
EXT
EXT
EXT
EXT
S-10
Syst.
PAL
PAL
PAL
PAL
PAL
S-11
Blk
OFF
OFF
OFF
OFF
OFF
S-12
Output
BRG
BRG
BRG
RG
B
S-13
Output
eo 3
eo 3
eo 3
eo3
eo3
S-14
ON
ON
ON
ON
ON
VR-1
See TEST
Condition
TP=9 V
V26=
3.5 V
V 26 = 2 V
eo3
e o 3, eov
TP = VCC
VG (min)
VB
VFF
PAL
PAL
PAL
VR-2
Input
SG
Measure
Point
eo3
eo 3
eo3
DC Voltmeter
537
pPC1384C
-----S-15
fo ±f
(3
}J.
~cp
fp
Vp
ON
ON
ON
OFF ON
ON OFF
OFF
+f (300 Hz)
-f (300 Hz)
fo
eref, eose
eref
Vp
Phase Meter
f.Counter
f.Counter
DC Voltmeter
+f (100 Hz)
-f (100 Hz)
S-16
Burst
Measure
Point
Vp
eref
f.Counter
DC Voltmeter
538
Vp
eref, eose
Phase Meter
f.Counter
DC Voltmeter
tlPC1384C
J,LPC1384C Input and Output Signals
Luminance Input Signal
;!
2 Vp_ p
~
/
White level
R20
R 19
470 Q 1 kQ
Luminance Delay Line
Terminal
:I
I
I
I
I
5
RIO
777" 1.8 k Q
f
4.43 MHz Trap
R18
47 Q
C25
100 pF
Band Pass Filter
l-+---~I----------!-:-------O
1
0.01 JlF
m
11111111111111111111111111111
Output Signa I
mt
Terminal 11
100 mVp-p
(Burst Signal)
1
Whi~
----------,
I
I
I
I
I
3.5 Vp_ p at Luminance
Terminal 26, 27, 28
J
U
~
~--~-------
.",.
I
I
I
I
: _______ --1
R31
\
R33
Input
=1 Vp-p
Contrast MAX.
Black
--OV
Black level
=2
V
(Controled by the brightness control)
539
jlPC1384C
pPC1384C Input Pulse
Burst Gate Pulse
Burst signal = 100'" 200 mVp-p
at Terminal 11
:~-E-
----I.!JJIIIII
I
I
I
I
n
,
'---.--
------~..
--l l--
2-3 Vp
\
4.5 - 3
OV
Terminal 19
jJs
Line Pulse
n
----'
t
1-2 Vp
'--_-'-i 0 V
Terminal 23
Blanking Pulse
(Line Pulse and
Field Pulse)
t
2 - 5 Vp(Max. 5 Vp)
'--_....L'-O V
Terminal 2
I
I
I
In case of commonly
using of Input Pulse
I
I
I
I
I
I
I
Terminal 19
-----Jnl----4.7 kQ
Terminal 23
540
JlPC1384C
JlPC1384C
*Color, Contrast and Brightness controlling circuit
VRl
Brightness Control
VR102
Sub Brightness
VR2
Sub Contrast
VR3
Color Control
VR104
Sub Color
I
I
Terminal 7
I
I
8
Contrast Control
VR103
I
Vcc= 12 V
VR1
VR2 <:._--'lMr-----...-------{
VR3
I
I
IL __________ _
VR102
VR103
VR104
V7 (Contrast)
5.5 to 7.0 to 8.5 V
V8 (Color)
4.0 to 5.5 to 7.0 V
V2 (Brightness)
8.2 to 8.7 to 9.2 V
Terminal 4
*Color Killer Setting VR 105
* APC Setting
Method;
1; Connect Resistor (100 kQ) between the Terminal 13 and GND
as shown Fig. 1 (Killer OFF)
----:--0
2; Connect Capacitor
(0.01 JlF) between the
100 kQ
Terminal 16 and GND as
shown Fig. 2 (Burst Input OFF)
i
Terminal 13
Fig 1
r1
3; Trim 4.433618 MHz by
---111--...,....----10
om ,F
Term''''
using VR 107
16
Fig 2
* 1H Delay Line Circuit
Vcc= 12 V
VR101
1kQ
C1
0.01 J.lF
Terminal 24
...----------...----
@
R4
2 kQ
®
®
(R-Y)
L2
1 - -_ _ _ _ _' - -_ _ _Terminal
L1
25
(B-Y)
Chrominance 1H Delay Line
L 1 ; Pre Chrominance Delay Line Terminating Coil
L2, VR10l ; Delay Phase and Amplitude Adjustment
V R 106 ; Sub carrier Phase Adjustment
541
01
~
I\)
"f;:
The Block Diagram and External Components for Il PC1384C
."
(")
~
W
VCC=12 V
Burst Gate
Pulse
CO
.--.----.- +B
~
(")
R31-33 3.3 kQ
R34-36 270 Q
Composite Signal
Input
RI9
R20
D.L.
C7
4~
j
Pedestal
Clemp
L54.43 MHz
Trap
JL
Jl
C25
RI8
47 Q
I.
100~PF -~--I
I
C24
120 P
"
I
I
I ___:
L--...II
APC
VRI07
4.7 kQ
• CI8 0.02 .u F
Killer
VRI05
4.7 kQ
R4
2 kQ
Trl 2SA733
Phase
Cll 0.01 .uF
C10 0.01 .u F
C9 O.Ol.u F
C6
l0.uF
R13
68 kQ
R30
Line Pulse
Brightness
VRI 10 kQ
Color
VR3 10 kQ
Contrast
VR2 10 kQ
L6 8.2 .uH
R29 1.5 kQ
CI9 39 pF
C20 47 pF
tlPC1384C
Printed Circuit Board Pattern (Bottom View)
Burst Gate
Pulse
Line Pulse
VCC
Blanking Pulse
Ground
Composite Signal
.uPC1384C Table of the external components
Symbol
R1
R2
R3
R4
R5
R6
R7
R8
R9
RIO
Rll
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
R26
R27
R28
R29
R30
R31
R32
R33
R34
R35
R36
Value
100 Q
100 Q
390 Q
2 kQ
(56 kQ)
(3.9 kQ)
2.7 kQ
5.6 kQ
68 kQ
1.8 kQ
33 kQ
33 kQ
68 kQ
39 kQ
22 kQ
100 kQ
5.6 kQ
47 Q
470 Q
1 kQ
68 k'Q
470 kQ
4.7 kQ
27 kQ
27 kQ
1 kQ
0.2 kQ)
1 kQ
1.5 kQ
0.2 kQ)
3.3 kQ
3.3 kQ
3.3 kQ
270 Q
270 Q
270 Q
Symbol
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
CI8
C19
C20
C21
C22
C23
C24
C25
C26
Value
0.01 J.lF
0.01 J.lF
47 J.lF
0.01 J.lF
4.7 J.lF
10 J.lF
10 J.lF
10 pF
0.01 J.lF
0.01 J.lF
0.01 J.lF
0.01 J.lF
1 J.lF
0.47 J.lF
47 pF
100 pF
0.022 J.lF
0.022 J.lF
39 pF(Xtal CL = 16 pF),
68 pF(Xtal CL =20 pF)
47 pF
18 pF
Symbol
VR-1
VR-2
VR-3
Value
10 k Q Brightness
10k Q Contrast
10k Q Color Saturation
VR101
VR102
VR103
VR104
VR105
VR106
VR107
1 kQ D.L. Level
4.7 k Q Sub Brightness
47 k Q Sub Contrast
47 k Q Sub Color Saturation
4.7 kQ Killer Adj
1 kQ Phase Adj
4.7 kQ APC Adj
L1
L2
L3
L4
L5
L6
D.L. Matching Coil Type No TKRNS 24984NK (Toko Corp.)
D.L. Matching Coil Type No TKRNS 24985VN (Toko Corp.)
Band Pass Filter Type No 163NEFl148WWJ (Toko Corp.)
33 J.lH
4.43 MHz Trap Type No LCS2HIH·102 (TDK Corp.)
8.2 J.lH
Trl
Xtal
L·D.L.
1 H D.L.
2SA733
4.43 MHz
Luminance
1 H Delay
(NEC)
CL = 16 pF or 20 pF
Delay Line Type No CTS·1804C (Showa Densei Corp.)
Type No EFD EN (Matsushita Corp.)
Line
120 pF
100 pF
4.7 J.lF
543
,uPC1384C
1 H Delay Line Matching Coil Specification.
L 1 Input Coil
(PAL)
0)
Type No.
TKRNS - 24984NK
Product
TOKO Corp.
to
4.43 MHz
o
6 -4
18 T
Cout
330 pF (4 -6)
G)
Qu
59 ± 20 %
Wire Material ; 0.1 1 U EW
L2 Output Coil
Type No.
TKRNS - 24985VN
Product
TOKOCorp.
to
4.43 MHz
4-2
18 T
2 -6
18 T
Cout
75 pF (4 -6)
Qu
44 ± 20 %
Wire Material; 0.1 12UEW
Chrominance Input Coil Specification.
L3 Input Coil
(PAL)
Type No.
163NEF - 1148WWJ
Product
TOKO Corp.
to
4.43 MHz
6-4
35 1/4 T
3 -1
76T
Cout
PH 47 pF
Wire Material; 0:1
544
1 UEW
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1397C
ANALOG INTERFACE CIRCUIT FOR TELETEXT SYSTEM
The JlPC1397C is a monolithic integrated circuit for the interface stage between the external analog signals and chroma
stage. This IC is packaged in 22 pins dual in package. This is most suitable interface IC for view data and CRT display application because of clamping circuit built in R, G and B circuit separately and excellent switching characteristics of video/data
switch-circuit. Contrast function can control both of video signal and data signal, and brightness function also can do it. White
peak level can set by external voltage applied to pin 15.
PACKAGE DIMENSIONS (Unit: mm)
FEATURES
•
External analog inputs are acceptable as well as digital.
•
High data switching speed.
•
R,G,B
Blanking
The rise time
35
35
ns
The fall time
35
35
ns
The delay time
20
20
ns
Contrast and Brightness can be controlled commonly on
TV and external signals.
•
Can be connected directly to R,G,B, output TV-signals
1:::~~3
1.2~
~W
~LI~I~~
~r
'
~~
10.16
of any IC's.
2.54
-ll-
0.5±0.1
~--tr
0.25+0.10
-0.06
0-15'
BLOCK DIAGRAM
VCC=12 V
22 PINS
1 k 5.1 k
EXTERNAL
INPUTS
~~"-VCC
75
Q
WHITE
PEAK
LEVEL
x3
PULSE
545
,uPC1397C
PIN CONNECTION DIAGRAM (22 Pin Dual In Line Package)
Capacitor
(Clamp)
GND
R.Data Input
R.Output
R.Video Input
Capacitor
(Clamp)
G.Data Input
G.Output
G.Video Input
Capacitor
(Clamp)
B.Data Input
B.Output
B.Video Input
Power Supply
Capacitor
White Peak level
FAST BlK Input
Brightness Cont.
Feed Back Output
SAND CASTLE PULSE
Contrast Cont.
Gate Pulse
1 TV SET Block Diagram
Sound
~
luminance
Chrominance
Processor
Remote Cont. TX
Channel
Select
Control
!
TElE TEXT
Decoder
·1
Adapt
2 CRT DISPlA V SET Block Diagram
Inputs Signals Connector
R.G.B. Inputs
{
(Analog ,Digital)
Sync Inputs. ___ {
(Line,Frame)
546
pPC1397C
ABSOLUTE MAXIMUM RATINGS (T a =+25 °c
Supply Voltage
Vcc
Power Dissipation
Pd
RGB (VIDEO) Input
ERGB
unless otherwise)
Ta=+70°C
15
V
850
mW
o to Vcc
o to VCC
Voc
Escp
-6 to VCC
Voc
EGP
-6 to VCC
Voc·
RGB (DATA) Input
EOATA
SAND CASTLE Pulse
Gate Pulse
o to VCC
o to Vcc
Voc
Fast BlK Pulse
EF.BLK
Control Voltage
E cont
Operating Temperature
T opt
-20 to +70
°c
Storage Temperature
T stg
-40 to +125
°c
Voc
Voc
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC
UNIT
SYMBOL
V
Supply Voltage
VCC
12 ± 10 %
RGB (VIDEO) Input Voltage
ein B - W
3
Vp-p
Black level of RGB (VIDEO) Input Voltage
EinBK
2.7 (at feed back)
VOC
RGB (OAT A) Input Voltage
ein RGB
1 Vp-p ± 3dB
75 ohm terminated
Black level of RGB (DATA) Input Voltage
Ein BK
0-2
VOC
Return level of RGB (DATA) (Line, Frame)
Ein BK (R)
Less than ein RGB X Max. 1 %
VOC
Fast BLK Input, H. Level
L. Level
VF.BLK (H)
VF.BLK (L)
1- 3
0
VOC
VOC
Gate Input Pulse Voltage
VG
3
SAND CASTLE Pulse
BLK Level
Gate Level
VSCP
Brightness Control Voltage
White Peak Supression Setting Voltage
2-6
Vp
more than 8
VOC
VOC
Vc BR
1-2-4
VOC
VWPS
4-9
VOC
547
,uPC1397C
ELECTRICAL CHARACTERISTICS (Ta =25°C unless otherwise noted, Vcc =12 V)
NO
1
Supply Current
2
RGB (VIDEO) Gain
3
Relative Ratio Gv ( i )
4
RGB (DATA) Gain
SYMBOL
TEST
MIN. TYP. MAX. UNIT
CKT
43
ICC
Gv(i)
AGvx-y
GeG)
mA
TEST CONDITIONS
VCC = 12 V
No Input; RGB (VIDEO), RGB (DATA)
Clamp Gate Pulse
0.9
1.17
1.5
times
RGB (VIDEO) Input; B'" W=3 Vp-p
Bk. Level = 2 VDC
Set; Bk. Out Level = 2 VDC
Contrast = Max, WPS Level = V CC
0.85
1.0
1.15
times
Same as No.2
2.9
3.5
4.1
times
1.3
1.5
1.7
times
RGB (DATA) Input; Contrast = Max.
B - W = 1 Vp-p
Set; Bk. Out Level = Contrast = Typ.
2VDC
5
Relative Ratio Ge ( i )
AGex-y
0.85
1.0
1.15
times
Same as No.4
6
Relative Ratio GelGv
GelGv
2.7
3.0
3.3
times
Same as No.2, 4
7
RGB (VIDEO), RGB (DATA)
Frequency Characteristic
f~(i)
6.0
-
-
MHz
RGB (VIDEO), RGB (DATA) Input;
0.5 Vp-p. 0 dB frq. = 100 kHz
-3 dB, Contrast = Max.
8
RGB Quiescent Output Voltage
3.2
3.5
3.8
VDC
RGB (VIDEO) Input; B - W = 0 Vp-p
Bk. Level = 2.7 VDC
BRT Cont = 3.5 VDC
9
Eo G)suPPI Y Voltage
B Coefficient
AEO-v(i)
-
0.3
-
V/V
V cc = 12 V ± 20 %
EoB = 3.5 VDC (at VCC = 12 V)
(~)Temperature
B Coefficient
AEo-T ( i )
-2
0
+2
mV/oC
Ta=-20-+70°C
EoB = 3.5 VDC (at Ta = +25 °C)
Eo ( i )
10
Eo
11
Difference Output Voltage
AEox-y
-100
0
100
mVDC
RGB (VIDEO) Input; B - W = 0 Vp-p
Bk. Level = 2.7 VDC,
BRT Cant = 3.5 VDC
12
Eox-y Temperature Coefficient
Eox-y
(T)
-
0
60
mVDC
Ta=-20 - +70 °c
Maximum Changing Level
13
Maximum Output Voltage
14
Changing Bk. Level
RGB (VIDEO)/RGB (DATA)
EoM
DC Restored (VIDEO), (DATA)
TDC
16
Brightness Control Sensitivity
BR
Contrast Cont. Range
8.5
-
VBK
15
17
548
CHARACTERISTIC
(~)
Rcont.
-
-
-
60
V
RGB (VIDEO) Input; B - W = 3 Vp-p,
Bk. Level = 2.7 VDC,
White Clip Level, Cant. = Max.
BRT = 2 - 6 VDC, WPS Level = VCC
mVDC
RGB (VIDEO) Input; B - W = 3 Vp-p,
Bk. Level = 2.7 VDC, RGB (DATA)
Input; B - W = 1 Vp-p,
Set; Bk. Out Level = 2 VDC
RGB (VIDEO) Input; B .... W = 3 Vp-p
Bk. Level = 2.7 VDC, APL = 10 - 90 %
No Blanking,
Set; Bk. Out Level = 2 VDC
90
95
100
%
0.9
1.0
1.1
V/V
15
17
19
dB
BRT Cant. Voltage
Changing Bk. Level
= 1.5'" 2.5 VDC
RGB (VIDEO) Input; B - W = 3 Vp-p
Bk. Level = 2.7 VDC, RGB (DATA):
B ,., W = 1 Vp-p, Cant. = Max./Min.
Set; Bk. Out Level = 2 V DC
pPC1397C
TEST
MIN. TYP. MAX.
CKT
NO
CHARACTERISTIC
18
Maximum Changing Black
level by Contrast
19
White Suppression Output
Voltage
WS(i)
6.5
20
Gate Pulse Minimum Input
Voltage
VGPM
SAND CASTLE
BlK
Pulse Input
Threshold
level
21
22
GATE
SYMBOL
UNIT
+50 mVDC
RGB (VIDEO) Input; B"" W = 0 Vp-p
Bk. level = 2.7 VDC,
Set; Bk. ~vel = 2 VDC
Contrast = Max. ,.., Min.
7.0
7.5
VDC
RGB (VIDEO) Input; B"" W
Bk. level = 2.7 VDC,
Set; WS level = 7 VDC
BRT Cant. = 2,.., 6 VDC
-
-
1
Vp
Vsc th
(BlK)
1.0
1.5
2.0
V
Vsc th
(GATE)
6.5
7.0
7.5
V
Eoc
-50
0
Fast BlK Pulse Input
Threshold level
Vth
(F.BlK)
0.5
0.7
0.9
V
Fast BlK SW Time Rise, Fall
tr, f sw
-
35
60
ns
Relative Rise, Fall Time
~tr,
-
0
20
ns
23
24
25
TEST CONDITIONS
f sw
= 3 Vp-p
I nput level RGB Output
RGB (VIDEO)
less than Vth
(F.BlK)
More than Vth
RGB (DATA)
(F.BlK)
RGB (VIDEO) Input; W = 3 Vp-p,
Bk. level = 2.7 VDC, RGB (DATA)
No I nput, Cant. = Max.
Set Bk. Out level = 2 VDC
=
Fast BlK SW Time Delay
td sw
-
20
ns
Same as No. 23
Relative Delay Time
~td
-
-
20
ns
load Condition; 3.3 kn/10 pF at Fall Time Only
RGB (DATA) SW Time Rise,
Fall
f(~)
~tr, f ( i )
-
35
60
ns
RGB (VIDEO) Input; B ,.., W = 0 Vp-p
Bk. level = 2.7 VDC, RGB (DATA)
-
-
20
ns
Input; B ,.., W = 1 Vp-p, Cant.
Set Bk. Out level = 2 VDC
-
20
ns
Same as No. 25
-
-
ns
load Condition; 3.3 knl10 pF at Fall Time only
Relative Rise, Fall Time
RGB (DATA) SW Time
Delay
sw
tr,
td(i)
= Max.
26
Relative Delay Time
~td(i)
20
549
JlPC1397C
~PC1397C
INPUT SIGNAL LEVEL
• R, G, B VIDEO Input Voltage
R.Video
Input----t
White Level
1
G.Video
Input----t
-1
3
Pedestal
1
I
'tLevel
I I I
I I 'I
1
I
VJr-p
B.Video
Input
----I
2.7 VOC
I
~I~I-rlI~--------~~~I -t
II II
I I I,
,
1 1
I I II
•
I I
I I I I
I I
,
j
'I
R, G, B DATA Input Voltage
I
75 ohm terminated
I
I
I
I
0.01 jlFx3
I
1
,
I,
G.Oata Input
I
I
I
I
B.Oata Input
Input
1 VJr-p Level
t
I
±3dB
0-2 VOC
GNO-~--+-..;---~::---~-.........L..-+-+- -1
I,
I,
• FAST BlK Input
75 ohm terminated
I I'
UJ
I!
GNO
I
r-----.
I
I
I
: in!
• Gate Pulse
GNO
~: i! y~~~
Iii
I
1
}
voc
L.Level
I
Threshold 0.7 VOC
0 VOC
d---------- 1- ~~
!
I
I
I
~
1
I
,
• SAND CASTLE Pulse,
I I
I I
I
I
I'
,
,II ~
I
I I
I
I
Threshold 0.6 VOC
I
I'
I I
10 V
Clamp Level
1-- L------------i--1 ~--Threshold7 VOC
1
I
I 'I
!~:I
,I
:I
I
I
Burst Gate..f""""
~
I
II,
, > Blanking Level
II
3V
Line Blanking-- - - - - - - - - - - - - - - - - ~Threshold 1.5 VOC
GNO--==·-~__~==============~
550
__
~=---==
Frame Blanking
APPLICATION
NTSC System
Japan. CAPTAIN.
USA TE LETEXT
PAL - SECAM System
W.G. Video Text, Bildshirmzeitung
FRANCE, Antiope
PAL System
U.K. TELETEXT, Prestel
NTSC
PAL
JlPCPS2C
JlPC136SC
Interface IC
JLPC1397C
SECAM
JlPC1364C2
Red
From Red
Out
-------.-1
Green
Out
Blue
Out
RGB
Matrix
r----r:m---
~
Green
Out
Out
~BIU'
RGB
~Green
Matrix
Out
~I TBIU'
Out
From Green
Out
From Blue
Out
UV~
Y
To BRT
B-Y(PAL)
R-Y(PAL)
1:::
."
o
w
~
CD
......
U1
U1
o
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1031H2
VERTICAL DEFLECTION DEVICE FOR MONOCHROME TV
AND SMALL-SIZED COLOR TV
DESCRIPTION
The J,LPC1031 H2 is a semiconductor integrated circuit for use in vertical-deflection circuit of monochrome TV and
small sized color TV.
It oscillates Vertical signal synchronizing with Vertical synchronization signal, and puts out the Vertical Deflection
current with the single chip.
And as it has some compensating circuits against the effect of temperature in it, it shows excellent characteristics.
It uses a Single In-line Package easily mountable on heatsink.
PACKAGE DIMENSIONS
FEATURES
•
Less number of required, external components.
•
Wide range of operational voltage (9 to 18 volts).
•
Freely adjustable pull-in range (by the resistor be put
in millimeters (inches)
4
26MAX. (1. 024)
25(0.984)
12 (0.472)
2-¢3.5
(¢O.l38)
2-R3.5
(R0.138)
§
between terminal 5 and the ground, and presenting
('1')_
-t---tt--t8
time constant of integrating circuit).
('I')
~
~~~~~~~ ~~~4~
•
Adjustable blanking pUlse-width.
•
Large output current-capacity (2 Ap _p ).
d
Built-in adjusting circuit for fly back time.
•
Easy mounting on printed circuit boad.
It)
x
-cc
~ M
00
•
en
8
~
W
a;
-
!
1.4
(0.055)
0.45
(0.02)
BLOCK DIAGRAM
Pulse
Clamp
r--
10 PIN SIP
c
- - - , . - - - - - - - - - - - - -
I
I
I
I
Deflection
Yoke
2-7Q
SYNCH
and
OSC
I
I
I
Vertical
Synchronization
Pulse
1.3V p _ p
Vee
'--N--+--lt'-t-~
-e---l--
,,~
IV p_ p
552
IV p_ p
I
I
I
J
lOV p _ p
,uPC1031H2
ABSOLUTE MAXIMUM RATINGS (Ta=2SoC)
Power Supply Voltage
Vee
Output Current
Ip _p
Power Dissipation
Pd1
Power Dissipation
Pd2
20
V
2
A _
p p
1.5 (Ta=+75°C)
W
Without heatsink
2.15 (Ta=+75°C)
With aluminum heatsink
W
(31.6 x 31.6 x 1 mm t)
Operating Temperature Range
Topt
- 20 to +75
°c
Storage Temperature Range
Tstg
- 40 to +150
°c
ELECTRICAL CHARACTERISTICS (Vec=12V, Ta=+2S±3°C)
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST
CKT.
Circuit Current
Icc
15
30
46
mA
1
No input signal and no load condition
Output Terminal Voltage
VN
5.6
6.0
6.4
V
1
No input signal and no load condition
Vertical Oscillation Frequency
flv
Hz
1
Synchronization signal voltage applied
at terminal 5 is 1.3 Vp_p
HZ
1
Oscillation capacitor; 1 SlF (Tantalum)
resistor; 38.1 k ohms
HZ
1
CHARACTERISTIC
Free-running Frequency
Pull-in Range
50/60
fva
53
60
fp
-10
-12
67
TEST CONDITIONS
With specified integration circuit, applied
voltage of synchronization signal is 1.3 V Pop
at terminal 5
Drift of Free-running
Frequency vs. Power
Supply Voltage
Deviation of Pull-in Range vs.
Power Supply Voltage
Output Saturation Voltage
Output pulse width of terminal 4
Llfva
±1.0
Hz
1
Frequency drift from standard frequency
(tvo 60 Hz at VCC=12 V) vs. power
supply voltage (Vec= 12 ±2 V)
Llfp
+3.0
Hz
1
Deviation from the frequency range for pull in
(at V CC = 12 V) vs. power supply voltage
(VCC= 12 ±2 V)
1.3
1.6
V
1
Output current: 0.7 A
420
600
SlS
1
Oscillation capacitor; 1 SlF (Tantalum)
resistor; 38.1 k ohms
Vsat
To
300
FUNCTION
553
j.lPC1031H2
TEST CIRCUIT
D.C.Current Meter.
Vee
0--0-----
To Oscilloscope
D.Y.
R\' :2.712
L :S.3mH
To Oscilloscope
and Digital
2"B:V~' M., ,
Integrating circuit
20k
To Frequency Counter
----+----o,..~
Adjusting Variable Resistor
for Vertical
Synchronization Level.
To Frequency counter.
3."
Trl 2SA733
Tr2 2SC94S
\
L'/
~n ~~:rtical Synchronization
1.3?~nal
SWITCH POSITION
CHARACTE R ISTIC
Circuit current
SWITCH POSITION
SYMBOL
lee
SW1
SW2
SW3
SW4
'SWS
1
2
2
OFF
OFF
Output terminal voltage
VN
1
2
2
OFF
OFF
Vertical oscillation frequency
fv
3
1
1
ON
ON
fvo
3
1
2
OFF
ON
Free-running oscillation frequency
Pull-in range
Drift of free-running frequency
vs. power supply voltage
Deviation of frequency range for
pull in vs. power supply voltage
Output saturation voltage
MEASUREMENT METHOD
Measure the voltage at terminal 1, by using
a digital voltmeter.
Apply the synchronization signal of 1.3 Vp.p to
terminal 5.
-
3
1
1
",OFF
ON
ON
Adjust the pull in frequency, by using VR-1, after
SW4 has been turned to the OFF position, and
then confirm that the perfect synchronization is
obtained when SW4 has been turned to the ON
position.
Llfvo
3
1
2
OFF
ON
Vary the power supply voltage in the range of
Vee = 12 ±2 V.
Llfp
3
1
1
",OFF
ON
ON
Vary the power supply voltage in the range of
Vee = 12 ±2 V.
3
3
1
ON
ON
Adjust VR-2 so that the terminal voltage across the
resistor of 0.5 ohms may be 0.7 Vp-p, and then
measure the waveform at the output terminal.
fp
V sat
N
Ground
IVsat
Output pulse width of terminal 4
To
3
2
2
OFF
ON
Measure the output pulse width at terminal 4, by
using an oscilloscope.
~
554
,uPC1 031 H2
TYPICAL CHARACTERISTICS (Ta =2SoC)
POWER DISSIPATION VS.
AMBIENT TEMPERATURE
10
~
b
Aluminume heatsink
Using silicone gresse
Units;mm
8
.2
"'"
~
a.
'iii
6
III
0
'"
~co
4
~
2
a..
FREE-RUNNING OSCILLATION FREQUENCY
VI. AMBIENT TEMPERATURE
..........
"i"-
r-....,100X 100 X
""""
""
_31.6X31.6Xl
I---Frei'Air--
a..
50
25
r'\.
'X"finite heats ink
. . . r-....
1---"""""t-",
75
"'
............
100
""'-,
~"
----.
150
125
Ta-Ambient Temperature-'C
Ta - Ambient Temperature -
OUTPUT TERMINAL VOLTAGE
AMBI ENT TEMPERATURE
FREE-RUNNING OSCILLATION FREQUENCY
vs. POWER SUPPLY VOLTAGE
VS.
H~~~
Vee
I
I
~PCI03IH2
~
'T~
> 6.2
~
'E
I I
00l7J
'0
volll,I-+--+-t--+-i
Output termlnll
-
TMter~mi-n~~.-u-ni~~i-cI~t~~+-~-4--+-~-1
her. Ire open circuit.
6.11--r---.,--.-~----":r::-'=:";""'::::"::;':"":::~:::""'--+--+-+--+-t-~
~ 6'0I---F====1=*,,-+-+--+-I-4-~_..t---!=-~,.J--~--1
~
62
I
.:: 60
~~ 58
-' rV
6
2.7k
2
100"
I
.PCIOlIHZ
!r
0.047"
To froquency
4
caunlor
B
~ foo-
4.7k :....-,...;;;; ....
/
".I.
If
o
l TN ......... ____1M .....
'--
. . . . . . . CIfC...
z,s... ~ ...... , .....
,HtSt. HO\.D.
T_I'.. '.".....-.:'I •• OHI.
~ 5.91--+--1--+--+-+--+-t--+--1--+--+-+--+-t-~
:3I
-.:
'c
at Vee
-'--
In
5.81--+--1--+--+-+--+-t--+-1--+--+-+--+-t-~
10
-20
20
60
40
80
14
12
16
18
20
Vee-Power. Supply Voltall-V
la-Ambient lemperature-'C
OUTPUT TERMINAL VOLTAGE
POWER SUPPL Y VOLTAGE
VERTICAL PULL IN FREQUENCY
POWER SUPPLY VOLTAGE
VS.
VS.
f-
S;I~" ,. ~3lil -1••or!'nalJ
V.rlltld supply 'fIoItlll .t
termiNll2.
:£:'-10
;V
'3 -30
CL
~
-
I--1 - -
~
V
9
~~~ ./ t V:
I
~
u
'"
.c
>-
i>:
1·.2Ap.p
0.8
0.6
4k
10k
open
12k
6k
14k
8k
Resistance value between terminal 2 and terminal 9 - Q
0.6r--+------+-----~----~~----+_------
10
12
14
16
18
Clamping voltage at terminal 10-V
557
,uPC1031H2
EXAMPLE OF PERIPHERAL CIRCUIT FOR THE J,LPC1031H2
JL
Rl
---'I.Nv-...-J\I~-a-:--+--{
Composite
synchronization
signal
+
C1
22,.,/IOV
(Tantalum)
Typical Example of Components Layout with the J,LPC1031H2 on P.C. Board
P.C. Board Pattern and Components Layout.
COMPONENTS
SYMBOL
R1
R2
R3
R4
Rs
RS
R,
C1
C2
C3
C4
558
SPECI F ICATION
SYMBOL
SPECI F ICATION
Cs
C10
C11
C12
10pF
22pF
22pF
2200pF
47pF
47pF
0.047 pF
100pF
VR1
VR2
VR3
SOkO-B
20kO-B
2kO-B
Cs
20kO
1/4W
2.7kn
1/4W
S.6kn
1/4W
82n
1/4W
O.S to 30,1 to 2W
10pF
1 pF
10V
25 V (Tantalum)
C,
Ca
Cg
10V
10V (Tantalum)
10 V (Tantalum)
16V
10V
10V
2SV
tlPC1031H2
EXAMPLE OF PERIPHERAL CIRCUIT FOR THE J,LPC1031H2
VCC (9-18V)
..:I:
CI~
II
~
CI>
oX
~>---&oL--4 ,~
c:
o
u
CI>
CI>
o
Composite
synchronization
signal
Typical Example of Components Layout with the J,LPC1031H2 on P.C. Board
P.C. Board Pattern and Components Layout
tLPCI031H2
o
I
I
'.Icc ,,-:-*C6.'
f
"
C 12
GNO
',t.
LIN.
o
COMPONENTS
SYMBOL
R,
R2
R3
R4
R5
R6
R7
C,
C2
C3
C4
SPECIFICATION
20kn.
2.7 kn
5.6kn
39!2
0.5 to 3!2,
10J,.LF
1 J,.LF
1/4W
1/4W
1/4W
1/4W
1 to 2W
10V
25 V (Tantalum)
SYMBOL
SPECIFICATION
C5
C6
C7
Cs
C"
C'2
10J,.LF
lOJ,.LF
2200J,.LF
47 J,.LF
47 J,.LF
220J,.LF
0.047 J,.LF
100J,.LF
VR,
VR2
VR3
50k!2-B
20 kn-B
1 k!2-B
Cg
ClO
10V
10 V (Tantalum)
16V
10V
10V
10V
25V
559
BIPOLAR ANALOG INTEGRATED CIRCUIT
ttPC1377C
SYNCHRONIZATION SIGNAL PROCESSOR OF COLOR TV
DESCRIPTION
The pPC1377C is a silicon monolithic integrated circuit designed for horizontal deflection circuit and vertical deflection
circuit of color TV set.
It consists two synchronization signal separators, vertical oscillator, vertical saw tooth shaper, vertical pre-drive, vertical
retrace blanking pulse generator, horizontal AFC, horizontal oscillator, horizontal pre-driver and abnormal high voltage prevention circuit, in it.
The horizontal part can take the operation current from high +B line as it has a shunt type regulator in it.
The synchronization signal separators are provided for horizontal signal and vertical one independently, so it works
very stable even in the ghost phenomenon, weak electrical field and etc.
FEATURES
•
Provided two synchronous signal separators realizes very stable synchronization, as they are provided each of horizontal
signal and vertical one independently.
•
Remarkably improved interlace tracking brought by the completely separated wiring in horizontal part and vertical one.
•
Vertical retrace blanking time can be set freely and strictly by the adjust terminal.
•
Very low drift of oscillation frequency of vertical oscillator and horizontal one against ambient temperature.
BLOCK DIAGRAM
560
,uPC1377C
(Unit: mm)
PACKAGE DIMENSIONS
27 MAX.
{:;;;:::::i
1.2-++-
.------------.---r! ~
jJ~.
l:;~
tI
=r~
~
-U-
2.54
0.5±0.1
I.!'l
d
CONNECTION DIAGRAM
~ --JJ:.
('Y')
10.16
0-15"
0.25+ 01 0
-Q~
(Top View)
Input of Horizontal Synchronization Signal Separator
22
Input of Vertical Synchronization Signal Separator
Output of Synchronization Signal Separator
2
21
VCC of Vertical Part
Input of AFC Detector
3
20
Output of Vertical Synchronization Signal Separator
Output of AFC Detector
4
19
Input of Vertical Synchronization Signal
Input of Horizontal Oscillation
5
18
Vertical Oscillation (Charge)
Input of X·ray Protector
6
17
Vertical Oscillation (Discharge)
Reference of X·ray Protector
7
16
Ground of Vertical Part
Integration Circuit of X·ray Protector
8
15
Vertical Feedback
Ground of Horizontal Part
9
14
Output of Vertical Amplifier
Output of, Horizontal Pulse
10
13
Vertical Blanking Pulsewide Adjust
VCC of Horizontal Part
11
12
Output of Vertical Blanking Pulse
561
ILPC1377C
Mark (+) of current expresses that the current is flowing into the
terminal.
ABSOLUTE MAXIMUM RATINGS (Ta=25 ± 3°C)
Mark (-) of current expresses that the current is flowing
out from the terminal.
Power Supply Voltage for Vertical Part
V21
15
V
Power Supply Current Drain for Horizontal Part
V11
30
rnA
Vertical Output Current
rnA
114
-30 to +0
Horizontal Output Current
110
-10 to +10
Power Dissipation
Po
600
Operating Temperature
T opt
Storage Temperature
Tstg
rnA
(Ta=75°C)
mW
-20 to +75
°c
-40 to +125
°c
RECOMMENDED CONDITIONS (T a=25 °C)
Power Supply Voltage for Vertical Part
12
V
Power Supply Current Drain for Horizontal Part
15
rnA
ELECTRICAL CHARACTERISTICS (Ta=25 °C)
CHARACTERISTICS
562
(V21 = 12 V, 111 = 15 rnA, Standard Circuit)
SYMBOL
MIN.
TYP.
MAX.
UNIT
Power Supply Current for Vertical Part
121
10.5
14
17.5
mA
Power Supply Voltage for Horizontal Part
V11
12.0
13.0
14.5
V
111=15mA
Vertical Free-running Frequency
fvo
48
50
53
Hz
C18=1 J'F, R17=33 kn
Drift of Vertical Free-running Frequency
Ltfvo(VCC)
0
0.8
1.0
Hz
Ltfvo (VCC)=lfvo (9.6 V)-f vo (14.4 V)I
Drift of Vertical Free-running Frequency
Ltfvo(Ta)
0
0.6
1.0
Hz
Lt fvo(Ta)=lfvo(-20 °C)-f vo (+75 °C)/
Vertical Synchronizing Capture Frequency
fpv
46
48
50
Hz
Output Middle Voltage
VMID
12
13
14
V
Drift of Output Middle Voltage
LtVMID(Ta)
1.0
V
LtVMID(Ta)=IVMID(-20 °C)-VMID(+75 °C)I
Retrace Pulse Width (1)
RPW(1)
0.95
1.0
1.05
ms
C13=0.047 J'F, R13=30.75 kn
Retrace Pulse Width (2)
RPW(2)
1.9
2.0
2.1
ms
C13=0.1 J'F, R13=28.5 kn
Retrace Pulse Voltage
RPV
10
11
Drift of Horizontal Power Supply. Voltage
LtV11 (Ta)
Horizontal Synchronizing Capture Frequency
fPH
Efficiency of Horizontal Oscillation Control
0
CONDITIONS
V21=12 V
Output Power: J'PC1378H
Vp-p
130
mV
LtV11 (Ta)=ILtV11 (-20 °C)-..:1V11 (+75 °C)I
C5=5 600 pF
±500
±700
±900
Hz
(J
38
40
45
HzlJ'A
Gain of AFC Detector
J'
190
300
420
J'A/rad
Horizontal Free-run.ning Frequency
fHO
15.00
15.75
16.50
kHz
Drift of Horizontal Free-running Frequency
LtfHOU11 )
0
50
Hz
LtfHO(J11 )=lfHO(15 mA)-fHo(9 mA)1
Drift of Horizontal Free-running Frequency
LtfHO(Ta)
0
40
100
Hz
LtfHO(Ta)=lfHO(-20 °C)-fHO(+75 °C)/
Horizontal Output Pulse Width
PWH
24.5
26
27.5
Horizontal Output Pulse Voltage
PWV
10
11
Horizontal Output Current
110
-3.5
-4.5
Input Voltage of X-ray Protector
V6
-0.1
C5=5 600 pF, R5=14.5 kn
J's
V p _p
-6.0
mA
0.1
V
V7 = 6.2 V
,uPC1377C
TYPICAL CHARACTERISTICS (Ta
= 25°C)
1. Vertical part
DRIFT OF VERTICAL OSCILLATION
AGAINST AMBIENl; TEMPERATURE
DRIFT OF VERTICAL OSCILLATION
AGAINST POWER SUPPLY VOLTAGE
(Hz)
(Hz)
/
Ta=25 'C
I\.
g
"
~
c:
0
:;:::;
~
g
~ +1
~
+1
c:
""""
"
--
0
:;:::;
!'..
.......
0
·u
External Parts is
25 'C Constant
VCC=12 V
+2
+2
~
~ .............. I
·u
...............
'0 -1
~
~
-2
-20 -10
0
-2
7
6
8
10
9
11
12
14
13
10
20
30
40
50
60
70
('C)
Ambient Temperature Ta---~
(V)
Power Supply Voltage V 2 1 -
2. Horizontal part
DRIFT OF HORIZONTAL OSCILLATION
AGAINST POWER SUPPLY CURRENT
POWER SUPPLY CURRENT vs.
POWER SUPPLY VOLTAGE
(Hz)
(mA )
Ta=25 'C
Ta=25 'C
l
16
0
0
:x:
~
/
c:
0
:;:::;
~
-500
/
·u
0
V
/
VI'I
Shunt Regulator
Voltage
14
.....
......
~
8
..:N
0
:x: -1000
'0
.....
~
-- --
6
V
0
12
10
//
"2c:
Shunt Regulator -.....
Voltage
w
~
/
o
a..
4
V
~
.--
2
~
----
./
/
If
4
5
6
8
9
10
11
12
13
14
(V)
Power Supply Voltage V 1 1 -
6
7
8
9
10
11
12
13
14
(V)
Power Supply Voltage V 1 1 DRIFT OF HORIZONTAL OSCILLATION
AGAINST TEMPERATURE
DRIFT OF HORIZONTAL OSCILLATION
AGAINST POWER SUPPLY VOLTAGE
(Hz)
(Hz)
Ta=25 'C
0
I
t
II
0
:x:
~
I
c:
0
:;:::;
I
I
....I
::J
.e
::J
0
Ta=25 ·C
9
8
iii
:e
./
7
V~
Q)
>
'0
6
~
5
2
"0
>
./
V ...
4
/
Q)
~
"0
:i
I
0
3
/
V
""
2
~
>
-.::I
6
7
8
9
10
11
12
13
14
V4-Power Supply Voltage-V
2. Horizontal part
DRIFT OF HORIZONTAL OSCILLATION
AGAINST POWER SUPPLY VOLTAGE
1
·c
Ta=25
N
12
1000
c
o
.
0..
Co
::J
~
8
7
Q)
Shunt Reg.
~
0
a..
-500
6
./'
I
8
I
o
::I:
5
4
-; -1000
3
572
10
en
I
I
Shunt Reg.
11
....c::::
~::J
~
c::::
..:N
HORIZONTAL POWER SUPPLY CURRENT
VERSUS VOLTAGE
4
5
6
VlO-Power Supply Voltage-V
7
/'"
V
~~
3
4
5
/
6
VlO-Power Supply Voltage-V
7
tlPC1379C
DRIFT OF HORIZONTAL OSCILLATION
AGAINST POWER SUPPLY CURRENT
DRIFT OF HORIZONTAL OSCILLATION
AGAINST TE,MPERATURE
T a=25 'C
N
:r::
~
I
I
c:
0
:.;:.
c:
o
:.;:.
500
C\l
C\l
'u
III
'u
III
0
:§
I~
c:
0
N
"§
:r::
-500
'0
...
I
100
o
0
E
External Part is
Constant
(IC only)
200
..............
i'-....
2
c:
~
I
/
I
'':
0
o
:r::
...
...........
'"
.........
~
.............
..............
~
-100
I'-
E
-1000
I
o
0
:
2=
-.::J
8
6
4
10
-200
-20 -10
12
0
10
20
30
40
50
60
70
Ta -Ambient Temperature-·C
IIO-Power Supply Current-rnA
3. PD - Ta Characteristic
POWER DISSIPATION vs.
AMBIENT TEMPERATURE
2,0
;:
I
c:
0
Infinite heatsink
Rth(j-tab)
=40 ·C/W
:.;:.
C\l
I'..
a.
'in
"\~
III
is
....
Q)
1.0
'\
K\
[/" r\.
~
0
a..
Free
I
A{
Rth(j-a)
=70 ·C/W
CI
a..
1\
\
""t\
~~
o
25
50
100
125
Ta -Ambient Temperature-·C
"
150
573
01
..J
~
1:::
'"0
APPLICATION CIRCUIT
o
..a
W
---..
to
o
(~
a.
~ {Ly=20
mH}
.....
Q
Ry =10
VCC2=110 V
8.2 kQ
!
I
+
25
J.ls
-=FtJL
1 ,uF /16 V
or
L-JVVv--_~ VCC2=12 V
430 Q
100 ,uF
1.
ALPHA-NUMERICAL INDEX
2.
QUICK REFERENCE GUIDE
3.
CROSS REFERENCE GUIDE
4.
MAINTENANCE AND OBSOLETE TYPES
5.
GENERAL STATEMENT
*
NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
o History
0
Types and Features
o Type Number Designation
*
*
0
Device Technologies
STANDARDS OF INTEGRATED CIRCUITS
HINTS ON CORRECT USE
* TECHNICAL SYMBOLS AND TERMS
* RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
6 - 1.
CAR AUDIO
6-2.
HOME AUDIO
6-3.
PORTABLE AUDIO
,7. TV APPLICATIONS
8. DIGITAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11. ARRAYS
12.
OTHERS
13. APPLICATION NOTES
DIGITAL TUNING SYSTEM
INDEX
Page
pPB553AC
150 MHz Prescaler (Vee = 5 V) __ ....... '.' . . . . . . . . . . . . . . . . . ..
pPB556C
150 MHz Prescaler (Vee
~PB562C
1 GHz Prescaler (Vee
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
586
pPD1701C-011
EU R LW/MW/FM DTS (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
590
~PD1701C-013
JPN/US AM/FM DTS (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
598
~PD1701C-014
JPN/US/EUR AM/FM DTS (Clock) . . . . . . . . . . . . . . . . . . . . . . . . . .. 607
~PD1703C-017
US/CND VHF/UHF/CATV TV DTS (Remo. Con.). . . . . . . . . . . . . . . ..
617
pPD1703C-018
JPN/US/EUR LW/MW/FM DTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
626
~PD1703C-020
JPN/US/EUR LW/MW/FM DTS (Clock, Timer) . . . . . . . . . . . . . . . . . .. 649
pPD1704C-011
JPN/US/EUR AM/FM DTS (Clock, Timer, Remo. Con.) . . . . . . . . . . . ..
660
pPD 1705C-0 12
US/CND VHF/UHF/CATV TV DTS (Clock, Timer, Remo. Con.) . . . . . ..
689
pPD1706G-011
JPN/US/EUR LW/MW/FM/SW DTS (Clock, Timer) ................ 704
=3
V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
= 5 V).
578
582
..
577
BIPOLAR DIGITAL INTEGRATED CIRCUIT
fL PB 553AC
150MHz DIVIDE-BY-16/17 LOW POWER PRESCALER
DESCRIPTION
The pPB553AC is a VHF two-modulus prescaler intended for use in PLL Digital Tuning Systems in conjunction
with pPD1700 series. Advanced bipolar process technology is utilized to realize high frequency operation with
extremely low power consumptions. The device provides ';-16 and ';-17 division ratio for NEC's original pulse
swallowing method, and is guaranteed to operate up to 130 MHz over the -35°C to +75 °c temperature range
with a VCC variation from +4.5 V to +5.5 V. An included amplifier allows it to be operated with small amplitude
signal of 150 mVp-p.
FEATURES
•
•
•
•
•
•
•
High frequency operation: 150 MHz (';-16)
130 MHz (';-17)
NEC's original pulse swallowing operation: ';-16/';-17
Small input amplitude: Vin = 150 m Vp-p (MIN.)
Single supply voltage: VCC = 5.0 V ±10 %
Low supply current: ICC = 8.9 mA (TYP.)
Incorporated buffer amplifier: VO=1.2 Vp-p (TYP.)
Small package: 8 pin plastic dual in-line package (DIP)
PACKAGE DIMENSIONS (Unit: mm)
10.5 MAX.
ill
2.54
578
jk5
h
I
7.62
JLPB553AC
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VCC
-0.5 to 6.0
V
Input Voltage
Vi
-0.5 to VCC
V
Output Current
Junction Temperature
10
T·J
Storage Temperature
Tstg
rnA
°c
10
+125
-55 to +125
°c
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range
VCC
Ta
4.5 to 5.5
V
Ambient Temperature
-35 to +75
°c
Output Load Capacitance
CL
less than 10 pi cofarad
ELECTRICAL CHARACTERISTICS (VCC
CHARACTERISTIC
SYMBOL
=5 V
MIN.
±10 %, Ta
= -35 to +75 °C)
TEST CONDITIONS
TYP.
MAX.
UNIT
12.7
rnA
VCC
mW
Ta
= 5.0 V
Power Supply Current
ICC
8.9
Power Consumption
Pc
44.5
Frequency Response
fin
1.0
150
MHz
Vin ~0.15 Vp-p, ';'-16
Frequency Response
fin
1.0
130
MHz
Vin ~ 0.15 Vp-p, .;.-17
Output Voltage
Vo
0.9
Vp-p
OUT terminal
Input Voltage
Vin
0.15
Vp-p
IN terminal
High Level Input Voltage
VIH
0.8VCC
Low Level Input Voltage
VIL
1.2
2.0
0.2VCC
= 25°C
V
PSC terminal
V
PSC terminal
Note: CHK terminal should be connected to GND.
579
,uPB553AC
BLOCK DIAGRAM (Top View)
x
ENABLE PULSE
GENERATOR
PSC
G: CMOS to ECl
level Translator
VCC
Cir-
CHK
~
GND
0-----
TIMING PULSE GENERATOR
T
IN
+16 DIVIDER
OUT
Q
TIMING CHART
IN
CHK
PSC
X (ENABLE
PULSE)
OUT
. - - - - - - - 1 7 p u l s e s - - - - - - - - + - - - - - - - - 1 6 pulses - - - - - - - . . .
CONNECTION DIAGRAM
Pin Number
Symbol
Function
1
VCC
Power Supply (V CC)
2
IN
Signal Input
3
CHK
Check (Normally to GND)
4
GND
GND
5
OUT
Output
6
PSC
Division Ratio Control*
7
NC
No Connection
8
NC
No Connection
*: When PSC terminal fixed high or low level, the J,LPB553AC functions as a -:-/16 prescaler.
580
J.lPB553AC
APPLICATION·'
J,LPB553AC
FM OSC.
f---1:
2
OUT
IN
~}
.~
FM
PSC
t
6
AA
~v~
PSC
FM RADIO
J,.LPD' 700 series
FM TUNING
ACTIVE
VOLTAGE
FILTER
EO'
MUTE
MUTE
STATION DETECTOR
SO
APPLICATION·2
FM FRONT END (U.S.)
__ ,...
BUFFER
..
I•
PRESCALER
__ ,
r------------------------------------------------,
to Mixer
1
~-.------~~--~~---.--------.----------------------oVcc
470n
1(+12V)
RD5.1EB
I
I
10/JF/6V
I
TO.0 1/JF
o
U1
>
(/)
I
-Tn
r
I
r--.....---~~-,
1
1000pF
2 /JPB553AC 5
I
from PLL (PSC)}
I
/JPD 1700
series
1 - - - - 9 t o PLL (FM)
I
10PF
3
4
!
__________________________________________ J
Tuning Voltage
581
BIPOLAR DIGITAL INTEGRATED CIRCUIT
IlPB556C
150 MHz DIVIDE-BV-16/17 LOW POWER PRESCALER
DESCRIPTION
The J1PB556C is a VHF two-modulus prescaler intended for use in PLL Digital Tuning Systems in conjunction
with J1PD1700 series. Advanced bipolar process technology is utilized to realize high frequency operation with
extremely low power consumptions. The device provides ";'16 and ";'17 division ratio for N EC's original pulse
swallowing method, and is guaranteed to operate up to 130 MHz over the -35°C to +75 °c temperature range
with a VCC variation from +2.55 V""+4.5 V. An included amplifier allows it to be operated with small amplitude
signal of 150 mVp-p.
FEATURES
o High frequency operation:
150 MHz (";'16)
130 MHz (";'17)
•
NEC's original pulse swallowing operation: ";'16/";'17
•
Small input amplitude: Vin = 150 m Vp-p (MIN.)
•
Single supply voltage: VCC
= 2.55
V""4.5 V
•
Low supply current: ICC = 9.4 rnA (TYP.)
•
Incorporated buffer amplifier: Va
•
Small package: 8 pin plastic dual in-line package (DIP)
= 1.2 Vp-p
(TYP.)
PACKAGE DIMENSIONS (Unit: mm)
10.5 MAX.
i
0;
~.5
582
rr=rl
7.62
J,lPB556C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VCC
Input Voltage
Vi
Output Current
10
Junction Temperature
Storage Temperature
-0.5 to 6.0
V
-0.5 to VCC
V
+125
mA
°c
-55 to +125
°c
10
Tj
Tstg
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range
VCC
Ambient Temperature
Ta
-35 to +75
CL
less than 10pF
Output Load Capacitance
ELECTRICAL CHARACTERISTICS (VCC
CHARACTER ISTIC
Power Supply Current
V
°c
2.55 to 4.5
SYMBOL
= 2.55--4.5 V, Ta = -35 to +75
MIN.
TYP.
MAX.
UNIT
°C)
TEST CONDITIONS
ICC
9.4
rnA
VCC == 5.0 V
Power Consumption
Pc
28
mW
Ta==25°C
Frequency Response
fin
1.0
150
MHz
Vin~0.15
Vp-p,716
Frequency Response
fin
1.0
130
MHz
Vin~0.15
Vp-p, 717
Output Voltage
Vo
0.9
Vp-p
OUT terminal
Input Voltage
Yin
0.15
Vp-p
IN terminal
High Level Input Voltage
VIH
0.8VCC
Low Level Input Voltage
VIL
1.2
2.0
0.2VCC
V
PSC terminal
V
PSC terminal
Note: CHK terminal should be connected to GND.
583
.uPB556C
BLOCK DIAGRAM (Top View)
x
ENAB lE PU lSE
PSC
GENERATOR
G: CMOS to ECl
level Translator
VCC
Gr
CHK
~
GND
~
TIMING PULSE GENERATOR
T
IN
+16 DIVIDER
OUT
Q
TIMING CHART
IN
CHK
PSC
X (ENABLE
PULSE)
OUT
-+I. .
~------17 p u l s e s - - - - - - - -..
- - - - - 1 6 pulses
------~.~I
CONNECTION DIAGRAM
Pin Number
Symbol
Function
VCC
Power Supply (V CC)
2
IN
Signal Input
3
CHK
Check (Connect to GND)
4
GND
GND
5
OUT
Output
6
PSC
Division Ratio Control *
7
NC
No Connection
8
NC
No Connection
•
*: When PSC terminal fixed high or low level, thepPB556C functions as a ';-/16 prescaler.
584
,uPB556C
APPLICATION
FM
PSC
FM RADIO
J.LPD1706G
FM TUNING
VOLTAGE
E01
I~~--~ SD
STATION DETECTOR
MUTE
585
BIPOLAR DIGITAL INTEGRATED CIRCUIT
ILPB562C
1 GHz DIVIDE-BY-128/136 LOW POWER PRESCALER
The pPB562C is a ECl two-modulus prescaler for operation at input frequency up to 1 GHz. It is intended for
use in TV Pll Digital Tuning Systems with the p PD 1700 series. This prescaler divides by either 128 or 136,
as determined by the signal form the pPD1700 series (EX. J.LPD1703C-017) applied to the Pulse Swallow Control
Input (PSC).
FEATURES
•
High frequency operation: 1 GHz
•
Dual mode operation with NEC's original pulse swallowing method
128/136 .... ·.. ·.. •.. ·up to. 1 GHz
b
64/68 .......... · ...... ·up to 500 MHz
• Single supply voltage: Vec = 5.0 V ± 10 %
•
low supply current: ICC = 23.0 mA (TYP.)
•
Incorporated buffer amplifier: Vo
= 1.2 Vp-p
(TYP.)
• Small package: 8 pin plastic dual in-line package (DIP)
BLOCK DIAGRAM
~---------------------------OPSC
+5V~~--~~----------~~-----O
I----~OPLL
r- - - -
I
-1-- - - - - --1
L _ _ --,
1/4,1/8
1/16,1/17
Divider
Divider
Buffer
GND
VCoo-----------~--~
1 000 pF
0.01 J.&F~
586
~PB562C
PACKAGE DIMENSIONS (Unit: mm)
10.5 MAX.
R1
CONNECTION DIAGRAM (Top View)
VCC
BIAS
PSC
IN
NC
GND
M
4
1 VCC
2 IN
3 NC
Power Supply (+5 V)
Signal Input
4
GND
Ground
5
OUT
Signal Output
6
M
Division Ratio Control (VCC: 64/68, GND: 128/136)
7
PSC
Pulse Swallow Control
8
BIAS
Bias
587
,uPB562C
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VCC
-0.5 to 6.0
V
Input Voltage
Vin
-0.5 to V CC +0.5
V
Output Current
10
-10.0
rnA
Storage Temperature
Tstg
-55 to +125
°c
RECOMMENDED OPERATING CONDITIONS
Supply Voltage Range
4.5 to 5.5
Ambient Temperature
Ta
Output Load Capacitance
CL
-35 to +75
Less than 30 pF
ELECTRICAL CHARACTERISTICS (VCC
CHARACTER ISTIC
sss
SYMBOL
=5 V
MIN.
Power Supply Current
ICC
Output Voltage
Vo
1.0
Input Voltage
Vin
0.4
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
High Level Input Current 1
±10 %, Ta
=-35 to +75 ° C)
TYP.
MAX.
23.0
30.0
1.2
1.5
UNIT
rnA
TEST CONDITIONS
VCC=5.0 V, Ta=25
Vp-p
OUT terminal
Vp-p
IN terminal
°c
V
PSC term i na I
0.3 VCC
V
PSC terminal
IIH 1
10.0
pA
PSC terminal
High Level Input Current 2
IIH 2
40.0
pA
M terminal
Frequency Response 1
fin 1
100
1000
MHz
Vin~O.4Vp-p,
Frequency Response 2
fin 2
100
500
MHz
Vin~0.4Vp-p, M=VCC
0.7VCC
M=GN D
,uPB562C
APPLICATION 1
IlPB562C
VCO
II
II
IN
I I
OUT
II
IN
PSC
M
PSC
77
UN Tuner
TU
LPF
VB
f--- 01
E01
IlP01703C-017
IlP04042
UB
01
Sa
02 Latch
02
Sb
f - 03 Clock
03
Sc
r---
Band Out
SW
t
05
APPLICATION 2
IlPB562C
VCO
II
II
OUT
IN
1
TU
t
LPF
VB
UB
SW
L
IN
psc
M
UN Tuner
I
II
psc
EO
IlPO 1705C-011
B01
Band Out
B02
589
MOS DIGITAL INTEGRATED CIRCUIT
I1PD1 701 C-011
PHASE LOCKED LOOP FREQUENCY SYNTHESIZER
LW/MW/FM DIGITAL TUNING SYSTEM CONTROLLER
CMOS LSI
DESCRIPTION
The J.,LPD1701 C-Ol1 is a single chip CMOS LSI designed for using as a PLL Frequency Synthesizer Digital
Tuning System Controller.
TheJ.,LPD1701C-Oll is packaged in a 28 pin slim dual in-line package (DIP).
FEATURES
•
•
•
•
•
•
•
Clock, PLL and Controller is realized in a single chip.
LW, MW and FM bands for Europe
High reference frequency (FM: 25 kHz) It results in a high carrier to noise ratio.
External programmable IF offset for FM band (10.650 MHz, 10.675 MHz, 10.700 MHz, 10.725 MHz)
High speed and low power consumption due to CMOS.
Stand-by mode ...supply current I DD = 0.5 mA (TYP.)
Display brightness control (DIMMER)
FUNCTION OF RADIO
•
•
•
•
•
•
Automatic up search (SEEK ARI/STEREO)
Automatic down search (SEEK ARI/STEREO)
Manual up search
Manual down search
Preset station memory ..... FM: 6 stations, MW: 6 stations
Last station memory. . .. .. FM: 1 station, MW: 1 station, LW: 1 station
FUNCTION OF CLOCK
•
•
•
•
24 hour display format .... hours, minutes, colon
Leading-zero blanking
Hours and minutes set controls
Minutes and seconds reset control
PACKAGE DIMENSIONS
in millimeters (inches)
e~:o~):
:~:-}
I
35.15 MAX.
(1.38 MAX.)
2.54 (0.1)
33.02
(1.3)
590
I
8.5 (0.33)
,uPD1701 C-011
ABSOLUTE MAXIMUM RATINGS
Voo
-0.3 to +6.0
V
Input Voltage
VI
-0.3 to Voo
V
Output Voltage
Vo
-0.3 to Voo
V
Output Current
IOH
-10
mA
Storage Temperature
Tstg
-55 to +125
Operation Temperature
Topt
-35 to +75
°c
°c
Supply Voltage
ELECTRICAL CHARACTERISTICS (Ta=-35 to +75 °c, VDD=4.5 to 5.5 V)
CHARACTERISTIC
High Level Input Voltage
TEST CONDITIONS
MAX.
UNIT
0. 8V oo
Voo
V
SO terminal
VIH2
0. 7V oo
Voo
V
CE terminal
VIH3
0. 6V oo
Voo
V
KO to K3 terminals.
VIL1
0
0. 3V oo
V
CE terminal
VIL2
0
0.2 V oo
V
SO, KO to K3 terminals.
VOH1
4.0
V
EO, 0, MUTE: IOH=-0.5 rnA
VOH2
4.0
V
SEG: IOH=-1.0 mA
VOH3
4.0
V
PSC: IOH=-0.2 rnA
SYMBOL
MIN.
VIH1
TYP.
.
Low Level Input Voltage
High Level Output Voltage
VOL1
0.5
V
EO: IOL=0.5 mA
VOL2
0.5
V
o,SEG,MUTE,PSC: IOL=0.2 mA
100
~A
Low Level Output Voltage
High Level Input Current
25
K: VI=Voo=5.0 V
IIH
5.0
fin1
0.5
2.5
MHz
AM: vi=1.0 Vp-p, DC cut, sine wave
fin2
0.5
8.8
MHz
FM: vi=0.8 Vp-p, DC cut, square wave
0.5
s
2.0
mA
Frequency Response
Supply Voltage Rise Time
Supply Current
Tr
100
0.5
Voo: 0 -+ 4.5 V
CE: Low Level
591
,uPD1701 C-011
SYSTEM DESCRIPTION
NEC's Digital Tuning System provides full electronic control of a vari-cap tuned FM/AM radio receiver and
stereo. The block diagram of the system is shown in Fig. 1. This is a Phase Locked Loop Digital Tuning System
which consists of two integrated circuits; controller plus PLL in a single chip, and two-modulus prescaler.
The controller (~PD1701 C-Oll) provides Phase Locked Loop capability with on-chip frequency division, a
reference oscillator whose frequency is controlled by an external crystal of 4.5 MHz, and phase comparator
circuitry. It accepts directly an AM local oscillator signal and an FM signal from two-modulus prescaler
(~PB553AC), and outputs control signals for closed loop operation of these oscillators. The outputs drives filters
for supplying analog voltages to the vari-cap tuners. The controller also provides the signals to drive the display.
The frequency of the tuned station is displayed on a 3.5 digit multiplexed display. Six favorite stations on each
band can be stored as well as "last stations tuned" information.
The two-modulus prescaler (~PB553AC) is suitable for pulse swallowing in this system.
pPD1701 C-011
MUTE
MUTE
FM
TUNING
LW/MW/FM
I\..
'\
5
E01
ACTIVE
AM
TUNING
D1
y
D5
/
~
-------FILTER
E02
DISPLAY
pPB553AC
FM
OSC.
~
PRESCALER
FM
t
PSC
I
RADIO
SEG.A
I\..
7
AM
OSC.
~
AM
STATION DETECTOR
4.5 MHz
SEG.G
1
X1
SEGMENT
rI
DRIVERS
~/
KO
T
A
/ 4
\.
'I
X2
K3
Fig.1 BLOCK DIAGRAM
592
\
SD
c::::J
crystal
DIGIT
DRIVERS
KEY and SWITCH
MATRIX
,uPD1701 C-011
PIN CONNECTION (Top View)
LW/MW GNO
FM
KO
K1
K2
K3
a
b
c
d
e
01
02
03
04
9
IlP01701C-011
E01
E02
CE
PSC
X1
X2
SO
MUTE
D5
VOO
EXPLANATION OF INPUT AND OUTPUT TERMINALS
EOl
E02
These three-state outputs are used (via active filters) to supply analog voltages to the tuner
vari-cap for controlling the local osc.
CE
This input is used to designate the stand-by mode to the chip.
It is low to designate the stand-by mode. (Display: off, PLL: disabled)
PSC
This output is used to control the division ratio of the FM two-modulus prescaler
(pPB553AC).
Xl, X2
These inputs are for connection to a 4.5 MHz crystal.
SO
This input is used to control the station searching operation (AU/AD). It is high to indicate
the presence of a station and the operation is terminated.
MUTE
This output line is high to mute the radio in the case of station change, band change, and so
on.
01 to 05
These outputs are used as digit drivers for the display.
VDD
This is a 4.5 to 5.5 volt supply for the chip.
a to g
These outputs are used as segment drivers for the display. They are also used as vertical drive
for the control key and mode switch matrix.
KO to K3
These inputs are from seven by four matrix. Various functions are entered through the matrix.
See Fig. 2 for the matrix assignments.
FM
This is the FM band local oscillator input. The frequency is divided by 16/17 using a twomodulus prescaler (pPB553AC).
GND
LW/MW
System ground.
This input is the LW/MW band local oscillator input.
593
,uPD1701 C-011
CONTROL KEY AND MODE SWITCH MATRIX
KO
K1
K2
K3
o:
momentary switch
D :alternate switch
6 :diode switch
/
: sw ontsw off
-94
---------------or
Fig.2
* Manual up or down search
MU, MD
*
Automatic up or down search
AU, AD
(SEEK)
*
A momentary depression will tune to next channel, and continuous depression more than 0.5
second allows traversing up or down the entire band until the key is released.
A momentary depression causes automatic up or down search which is terminated by activation
of SD terminal (active high).
Preset of the station
ME
The tuning information is stored into internal RAM by depressing ME key and then the desired
memory key within 5 seconds from the time ME key was initially depressed. If any key is
depressed in this period, the ME function is cancelled.
Ml to M6 Six favorite stations can be recalled from internal RAM for each band. When it is switched from
one band to another band, it will tune to "Iast-tuned-to station" on that band. Each time a station
is changed, the controller provides a signal to mute the radio.
594
J,lPD1701 C-011
* Clock function
HA, MA
OADJ
These keys are used for hours and minutes setting. (See note)
A momentary depression resets minutes and seconds.
NOTE: MU and MD keys can be used to set minutes and hours, keeping depressing ME key when
time is displayed.
* Switching-over the display
RCAl
A
P
DIMMER
A momentary depression will change the display mode when radio is on.
eN:
Frequency is given priority for the display.
OFF: Clock is given priority for the display.
ON:
There is a priority on the display.
When RCAl key depressed, the display returns to the prior matter after 5.sec display of
another.
OFF: There is no priority on the display.
ON:
Display brightness is reduced (duty: 20 % of normal brightness).
OFF: Display brightness is normal.
* ARI/STEREO search
ARI
OFF:
ON:
Normal automatic search (AU, AD)
In the case of FM band, ARI/STEREO search is possible.
A momentary depression of AU/AD key causes up or down ARI/STEREO search which
is terminated by activation of SD terminal and AR I SD switch. (Timing diagram is shown
below.)
PLL "LOCK"
SO
45 ms
SO
ARI SO
125 ms or 500 ms
I
r
ARI SO
Fig. 3
500/125
ARI SD
This switch is for a selection of timing in the case of ARI/STEREO search.
ON:
The controller waits 500 ms from the activation of SD terminal.
OFF: The controller waits 125 ms from the activation of SD terminal.
This switch is normally a transistor switch. In the case of ARI/STEREO search, ARI (SK, BK or
DK) or STEREO SD signal is read from this switch.
595
.uPD1701 C-011
* Selection of the radio band
LW, MW/FM
These switches are for selection of the radio band (LW, MW, FM).
Channel
Spacing
Receiving Frequency
Intermediate
Frequency
LW
MW/FM
BAND
ON
x
LW
155 to 281 kHz
9 kHz
450 kHz
OFF
ON
MW
531 to 1602 kHz
9 kHz
450 kHz
OFF
OFF
FM
87.5 to 104/108 MHz*
50 kHz
**
x : Don't care.
Table 1
IFO, IF1** Two external diodes program the chip to accept 4 different frequencies from 10.650 MHz to
10.725 MHz in 25 kHz steps.
IFO
IFl
Intermediate Frequency
OFF
ON
10.650 MHz
ON
ON
10.675 MHz
OFF
OFF
10.700 MHz
ON
OFF
10.725 MHz
Table 2
108/104 *
This switch is used to preset the FM receiving band.
Receiving Frequency
108/104
ON
87.50 MHz to 108.00 MHz
OFF
87.50 MHz to 104.00 MHz
Table 3
* Display interface
The center frequency of tuned station is displayed on a 3.5 digit LED display. The segment outputs a, b, c, d,
e, f, and g are also used as inputs for 7 segment drivers. The segment output go to common collector NPN
transistor array (J,LPA56C) to drive the segments of the common cathode 7 segment LED display. The digit
outputs go to NPN darlington transistor array (J,LPA53C) to drive the LED display.
II
I~
05
04
02
03
Fig.4
596
FM.OP
a
MW
LW
ME
c
d
COLON (STOP)
e
b
COLON (FLASH)
50 kHz
01
9
Fig.5 APPLICATION CIRCUIT
! ! ! ! !~ r
i~-J-T-
KEY and SWITCH MATRIX
SEGMENT DRIVER
M
I I I I ::
h
1111::11 1_
-r-r
f5V
("A56;
v
h.
YV'W
i
'VIII,
A'A
I
rh~----o/;
3.3 k x 7
from
AM VCO
V
t..)
L-_L_j __ L_j __ I__ .!-_~ __ .1_J
'A
33n x 7
m
a
+5V~
O.OlJ.1J;
from 0
FM VCO
c
b
d
e
1
81
rDl rLil
lQJ
lQ
8
g
LEO (Cathode Common)
1
II--------l
1000p
2.2J.1
10k~.22,",
2._2J.1_t;~~~k--------~
o _________
0
~
to~
2pOX r~2
10k
0.01 J.I
DIGIT
4.5 MHz
HC-18/U
TOYO COM
1=1
1=1
05
04
D~[§ ___ L
0
0
03
I
I
I
I
TQC-231A~8C
I ____
L
02
01
___ L ___ L ___ L,
J.lPA53C
x5
,
,
_ _ _ _ _ _ _ _ ,..., _____ ._____
I
I
I
I
I
~-J
J.lPC78L05
5V
F14C
IIo...l
~I
100J.l
f+
-
1~22J.1
-;J;
5V
J.lPC78M05
fr
o0 m . Y
Acc
SW.
radioc
switch
I~ , )
to,",PB553AC
and .PA56:
Muting
1
00.
.
OutPut
L -_ _..._
to radio
_
~
I~
~
.......
0
~
C')
I
0
~
~
01
CD
~
MOS DIGITAL INTEGRATED CIRCUIT
IlPD1701 C-013
PHASE LOCKED LOOP FREQUENCY SYNTHESIZER
FM/AM DIGITAL TUNING SYSTEM CONTROLLER
CMOS LSI
The ~PD1701 C-013 is a single chip CMOS controller designed for using as a Phase Locked Loop Frequency
Synthesizer Digital Tuning System Controller.
The ~PD1701C-013 is packaged in a 28 pin slim dual in-line package (DIP).
FEATURES
•
PLL, swallow counter and system controller are realized in a single chip.
•
FM and AM bands - - - - Japan and U.S. bands.
•
High reference frequency. (FM: 25 kHz, AM: 9/10 kHz)
•
External programmable I F offset for FM band.
It results in a high carrier to noise ratio.
•
High speed and low power consumption due to CMOS.
•
Stand-by mode - - - - Supply current IDD
= 0.5 rnA
(TYP.)
•
Display brightness control (DIMMER) - - - - Duty ratio 1 : 4
•
Internal display decorder for 3.5 digit multiplexed display.
•
Automatic power-on clear without any external components.
FUNCTION OF RADIO
•
Automatic up search (SEEK)
•
Automatic audition
•
Manual up or down search
(SCAN)
•
Preset station memory call
•
Preset station memory - - - - FM: 6 stations, AM: 6 stations
•
Last tuned station memory - - - - FM: 1 station, AM: 1 station
FUNCTION OF CLOCK
•
12 hour display format - - - - hours, minutes, AM/PM, colon
•
Leading-zero blanking
•
Hours and minutes set controls
•
Minutes and seconds reset control
PACKAGE DIMENSIONS
in millimeters
i:~:~-:-::~t
I
I
35.15 MAX.·
x
--1L
33.02
0.5
±
0.1
~--------==~------~
598
~~
~
~
,uPD1701 C-013
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VOO
-0.3 to +6.0
V
Input Voltage
VI
-0.3 to VOO
V
Output Voltage
Vo
-0.3 to VOO
V
Output Current
IOH
-10
Storage Temperature
Tstg
-55 to +125
Operation Temperature
Topt
-35 to +75
mA
°c
°c
ELECTRICAL CHARACTERISTICS (Ta= -35 to +75 ° C, VDD= 4.5 to 5.5 V)
CHARACTERISTIC
High Level Input Voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONOITIONS
VIHl
0. 8V OO
VOO
V
SO terminal
VIH2
0. 7V OO
VOO
V
CE terminal
VIH3
0. 6V OO
VOO
V
KO to K3 terminals
VILl
0
0. 3V OO
V
CE terminal
VIL2
0
0. 2V OO
V
SO, KO to K3 terminals
Low Level Input Voltage
High Level Output Voltage
VOHl
4.0
V
EO, 0, MUTE: IOH=-0.5 mA
VOH2
4.0
V
SEG: IOH=-1.0 mA
VOH3
4.0
V
PSC: IOH=-0.2 mA
VOLl
0.5
V
EO: IOL =0.5 mA
VOL2
0.5
V
O,SEG,MUTE,PSC: IOL = 0.2 mA
100
J1.A
K: VI=VOO=5.0 V
Low Level Output Voltage
High Level Input Current
25
IIH
5.0
fin 1
0.5
2.5
MHz
AM: vi=1.0 Vp-p, OC cutsinewave
fin2
0.5
8.8
MHz
FM: vi= 0.8 Vp-p, OC cut square
wave
0.5
s
2.0
mA
Frequency Response
Supply Voltage Rise Time
Tr
Supply Current
100
0.5
VOO: 0-- 4.5 V
CE: Low Level
599
j.LPD1701 C-013
SYSTEM DESCRIPTION
NEe's Digital Tuning System provides full electronic control of a vari-cap tuned FM/AM radio receiver and
stereo. The block diagram of the system is shown in Fig. 1. This is a Phase Locked Loop Digital Tuning System
which consists of two integrated circuits; controller plus PLL in a single thip, and two-modulus prescaler.
The controller chip (J,LPD1701 C-013) provides Phase Locked Loop capability with on-chip frequency
division, a reference oscillator whose frequency is controlled by an external crystal of 4.5 MHz, and phase comparator circuitry. It accepts directly an AM local oscillator signal and an FM signal from two-modulus prescaler
(,uPB553AC), and outputs control signals for closed loop operation of these oscillators. The outputs drives filters
for supplying analog voltages to the vari-cap tuners. The controller also provides the signals to drive the display.
The frequency of the tuned station is displayed on a 3.5 digit multiplexed display. Six favorite stations on each
band can be stored as well as "last stations tuned" information.
The two-modulus prescaler (pPB553AC) is suitable for pulse swallowing in this system.
pPD 1701C-013
MUTE
MUTE
FM
TUNING
"-
5
E01
ACTIVE
AM
TUNING
01
05
/"
~
------FILTER
E02
DISPLAY
pPB553AC
FM/AM
FM
OSC.
PRESCALER
I
FM
RADIO
t
PSC
AM
OSC.
SEG.A
SEG. G
....
~
AM
STATION DETECTOR
4.5MHz
SO
1
KO
'.f'\.
V
~
X2
K3
Fig. 1 Block Diagram
600
DRIVERS
KEY and SWITCH
A
T
~
SEGMENT
~7
X1
c:J
crystal
DIGIT
DRIVERS
4
MATRIX
tlPD1701 C-013
PIN CONNECTION (Top View)
KO
Kl
K2
K3
b
c
01
02
a
pP01701C-013
EOl
E02
CE
PSC
Xl
X2
SO
MUTE
03
04
05
VDO
EXPLANATION OF INPUT AND OUTPUT TERMINALS
EOl
E02
These three-state outputs are used (via active filters) to supply analog voltages to the tuner
varicap for controlling the local oscillators.
CE
This input is used to designate the stand-by mode to the chip. It is low to designate the standby mode. (display: off, PLL: disable)
PSC
This output is used to control the division ratio of the FM two-modulus prescaler (pPB553AC).
Xl,X2
These inputs are for connection to a 4.5MHz crystal.
SO
This input is used to control the automatic station searching operation. It is high to indicate the
presence of a station.
MUTE
This output line is high to mute the radio in the case of station change, band change, and so on.
01 to 05
These outputs are used as digit drivers for the display. (Active high)
VOO
This is a 4.5 to 5.5 volt supply for the chip.
a to g
These outputs are used as segment drivers for the display. They are also used as vertical drive
for the control key and mode switch matrix. (Active high)
KO to K3
These inputs are from seven by four matrix. Various functions are entered through the matrix.
See Fig. 2 for the matrix assignments.
FM
This is the FM band local oscillator input. The frequency is divided by 16/17 using a twomodulus prescaler (uPB553AC).
GNO
AM
System ground.
This is the AM band local oscillator input.
601
,uPD1 701 C-013
CONTROL KEY AND MODE SWITCH MATRIX
SEG.A
SEG.B
SEG.C
SEG.D
SEG.E
SEG.F
SEG.G
KO
K1
K2
K3
o:
D:
momentary key,
alternate switch,
6:
diode switch
Fig. 2 Control Key and Mode Switch Matrix
*
Manual up or down search
MU, MD
A momentary depression will tune to next channel, and continuous depression more than
0.5 second allows traversing up or down the entire band until the key is released.
*
Automatic up search (Saw-tooth search)
SEEK
A momentary depression causes automatic up search which is terminated by activation of SD
terminal (active high).
SCAN
*
A momentary depression causes automatic station-to-station search.
Preset of the station
ME
The tuning information is stored into the internal RAM by depressing ME key and then the
desired memory key (M1 to M6) within 5 seconds from the time ME key was initially depressed.
If any other key is depressed in this period, the ME function is cancelled.
M 1 to M6
Six favorite stations can be recalled from internal RAM for each band. When it is switched from
one band to the other, it will tune to "Iast-tuned-to station" on that band.
Each time a station is changed, the controller provides a signal to mute the radio.
*
Clock set controls
HA, MA
These keys are used for hours and minutes setting. (See note)
DAD
A momentary depression will reset minutes and seconds.
Note
MU and MD keys can be used to set minutes and hours, keeping depressing ME key when time
is displayed.
602
,uPD1 701 C-013
*
Switching-over the display between radio and clock
A, B, P
Display mode switches A, B initial switch P and control key RCAl control the display mode as
RCAl
follows_
1. A: ON, B:ON, P:ANY
No priority on the display. A momentary depression of RCAl key causes alternate display
change between time and frequency whenever it is performed. Whenever frequency is
handled, frequency is displayed.
2. A: ON, B: OFF, P:OFF
Clock display is prior to frequency.
A momentary depression of RCAl key causes
alternative display chnage_ When time is displayed, a depression of RCAl or one of the
frequency handling key recalls frequency information on the display for 5 seconds. After
that, the display turns back to clock automatically.
3. A:ON,B:OFF,P:ON
Frequency is prior to the clock.
A momentary depression of RCAl key causes the
alternative display change. When frequency is displayed, a momentary depression of RCAl
key recalls clock display and it remains there for 5 seconds. If any other key is handled
when time is displayed, handling of one of the time adjust keys (HA, MA, OAD) keeps the
time display, the display turns back to frequency automatically 5 seconds after the time
adjust is completed. Whenever frequency is handled, frequency is displayed.
4. A: OFF, B:OFF, P: ANY
Clock only.
5. A: OFF, B: ON, P: ANY
Disabled.
*
Switching-over the Manual UP/DOWN signal generator
ROT
ON: Pulse repetition rate more than 6 milisecond will be acceptable as MU or MD signal for an
application of the endless-rotary switch as the signal generator.
OFF: Pulse repetition rate more than 60 milisecond will be acceptable preventing from miscounting
by chattering of the momentary switches applied for UP/DOWN signal generator.
*
Protection from the miss key input
lOCK
This switch is for protection from miss key input.
ON ....................................... All of the key input is disabled.
OFF ..................................... All of the key input is enabled.
*
Protection from the key chattering
Key make time ..................... less than 15 ms
Key break time ..................... less than 15 ms
603
,uPD1701 C-013
* Selection of the radio band
J/U
This switch is for selection of the district.
AM/FM
This switch is for selection of the radio band.
Band Switch
Selected Band
J/U
AM/FM
off
FM U.S.
87.9 to 107.9 MHz, channel spacing 200 kHz
on
AM U.S.
530 to 1 620 kHz, channel spacing 10 kHz *3
off
FM Japan
76.1 to 89.9 MHz, channel spacing 100 kHz
on.
AM Japan
531 to 1 602 kHz, channel spacing 9 kHz
off
on
* 3: See AM band I F offset
Table 2
* FM band I F offset
IFO, IFl
These switches program the chip to accept 4 different intermediate frequencies.
Intermediate Frequency
IFO
IF1
Japan
U.S.
on
off
10.750 MHz
10.650 MHz
on
on
10.725 MHz
10.675 MHz
off
off
10.700 MHz
10.700 MHz
off
on
10.675 MHz
10.725 MHz
Table 3
* AM band I F offset
IF2
This switch programs the chip to accept 2 different intermediate frequencies.
Bl/B2
This switch is for selection of the receiving band and channel spacing of AM radio for U.S. band.
J/U
Bl/B2
on
X
IF2
Intermediate
Frequency
on
261 kHz
off
450 kHz
on
261 kHz
off
450 kHz
on
260 kHz
off
450 kHz
on
Receiving
Frequency
Channel
Spacing
531 to 1 602 kHz
9 kHz
531 to 1 602 kHz
9 kHz
530 to 1 620 kHz
10 kHz
off
off
Table 4
604
,uPD1701 C-013
*
Display interface
The center frequency of tuned station is displayed on a 3.5 digit LED display. The segment outputs
a, b, c, d, e, f, and g are also used as inputs for 7 segment drivers. The segment outputs go to common
collector NPN transistor array (J,LPA56C) to drive the segments of the common cathode 7 segment LED
display. The digit outputs go to NPN darlington transistor array (J,LPA53C) to drive the LED display.
ME
-J J J J J J
-J J I- I I- I
- -
J
(f)
J
-
04
05
03
a
AM
PM
b
FM.OP
c
COLON (STOP)
d
COLON (FLASH)
e
9
01
02
Fig.4
*
Display format
o Segment Pattern
,, ,=-, =,-,
*
'-'I ,=
-'
,- ,-,, ,=,
,=,
L'
,-,
=,I-,
'-'
a
f,-,b
-
e,-;jc
d
Display brightness control (DIMMER)
DIM
This switch is for selection of display brightness.
ON - - - - Display brightness is reduced. (Duty factor: 1/32)
OFF - - - - Display brightness is ordinary. (Duty factor: 1/8)
SEG. F orG
SEG. F orG
diode switch: "on"
diode switch: "off"
Fig. 3 Diode Switch
SEG.E
SEG. E
alternate switch: "on"
alternate switch: "off"
Fig. 4 Alternate Switch
605
m
o
m
1::
"C
~
--.I
Fig. 5 APPLICATION CIRCUIT
o
~
+5V
SI::GMI::N I UHIVI::H
~ V~
17
"
,~ :~
:~
f"""I
;,. ~,. ~,. ~ io
~f:; -'f:; ;f:; ;~
~
~
A~ -~
22 k x 4
0.01}.t
from
AM VCO
::
n
rl,
n
~
AM TUN.
VOLTAGE
o
J
I
f"""I
I
L~
K1
K2
K3
r
~~ ~ ~
abc
d
e
~
nlJr
~
20 ~ 1-2:2
7
p'
P
22/J~~
4.7k
100/J
±~
o
cy"c
radio switch
.... 1
1;O/J
A
t.....
......
~~
--- - -
~-c
_J
---- '----:.
d
e
f
g
5V
J/
;J;-
' - - - - - to radio
I
I
I I
I I
0
-
I I
I I
-
0
-
-
I I
I- I
:
-
0
FM,DP
COLON
04
03
02
01
O~I_~~__ __ --1----1----1----1-,
I
/JPA53C
I
TOYOCO~
:
x5
TQC-231A·8C
I
-----r----- ----------~-] 1
L____
~± 2~2/J
/JPC78M05
from
Ace SW.
ME
DIGIT
~I
~
33n
05
5V
F14C
~
_
v
0.01 }.t
I
3.3k
/ ; MHz
HC-18/U
,,2.2k
t-o.
g a b
I
llO'lL
4.7k
0.033}.t
0.022/J
. H
v
I
3.3k X7
T
ro
t.....
pPD1701C·013 (Top View)
/JPC78L05
from
battery
(12V)
f
rl
.L
10k
22
. /J
v
1-"'"
.A
~o /JPB553AC
+ z~ and /JPA56C
-7f7 lOOp
"'
Muting"'"
Output ./
......
)
I
o
~
I
LJ
~
.~~ -.:~-~
KO
h-
(")
w
N
1:5 ~ 1.1:5
1000p
:
AM GND FM
I
!
7
10k
FM TUN.
VOLTAGE
~
N
J
,....
~r---jo.~~ l lr~r~r~r~ [
c NCPSC OUT]
}.tPB553AC
Vee INCHKGND
from
FM VCO
L...
~
I ....
'v ·'17
I'~ I'~
L~
!I h-
..,
r -r------.------+-------+-_---.----.---,
KE Y and SWI TC H MAT R I X
rh,
L:P-"'17
C
I
:
MOS DIGITAL INTEGRATED CIRCUIT
J1 P01 701 C-014
PHASE LOCKED LOOP FREQUENCY SYNTHESIZER
FM/AM DIGITAL TUNING SYSTEM CONTROLLER
CMOS LSI
The J,lPD1701 C-014 is a single chip CMOS controller designed for using as a Phase Locked Loop Frequency
Synthesizer Digital Tuning System Controller.
The J,lPD1701 C-014 is packaged in a 28 pin slim dual in-line package (DIP).
FEATURES
•
PLL, swallow counter and system controller are realized in a single chip.
•
FM and AM bands - - - - Japan, U.S. and Europe bands.
•
High reference frequency. (FM: 25 kHz, AM: 9/10 kHz)
It results in a high carrier to noise ratio.
•
External programmable I F offset for FM band.
•
High speed and low power consumption due to CMOS.
•
Stand-by mode - - - - Supply current IDD = 0.5 mA (TYP.)
•
Display brightness control (DIMMER) - - - - Duty ratio 1 : 4
•
Internal display decorder for 3.5 digit multiplexed display.
•
Automatic power-on clear without any external components.
FUNCTION OF RADIO
•
Automatic up search (SEEK)
•
Automatic audition
•
Manual up or down search
•
Preset station memory call
(SCAN)
.• Preset station memory - - - - FM: 6 stations, AM: 6 stations
•
Last tuned station memory - - - - FM: 1 station, AM: 1 station
FUNCTION OF CLOCK
•
12 hour display format - - - - hours, minutes, AM/PM, colon
•
Leading-zero blanking
•
Hours and minutes set controls
.·.Minutes and seconds reset control
PACKAGE DIMENSIONS
in millimeters
i:~::-:-::~-t
I
35.15 MAX.
I
607
,uPD1 701 C-014
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VDD
-0.3 to +6.0
V
Input Voltage
VI
-0.3 to VDD
V
Output Voltage
Vo
-0.3 to VDD
V
Output Current
IOH
-10
Storage Temperature
Tstg
-55 to +125
Operation Temperature
Topt
-35 to +75
mA
°c
°c
ELECTRICAL CHARACTERISTICS (Ta= -35 to +75 ° C, VOO= 4.5 to 5.5 V)
CHARACTERISTIC
High Level Input Voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
VIHl
0.8VDD
VDD
V
SD terminal
VIH2
0.7VDD
VDD
V
CE terminal
VIH3
0.6VDD
VDD
V
KO to K3 terminals
VILl
0
0.3VDD
V
CE terminal
VIL2
0
0.2VDD
V
SD, KO to K3 terminals
Low Level Input Voltage
High Level Output Voltage
VOHl
4.0
V
EO, D, MUTE: IOH=-0.5 mA
VOH2
4.0
V
SEG: IOH=-1.0 mA
VOH3
4.0
V
PSC: IOH=-0.2 rnA
VOLl
0.5
V
EO: IOL =0.5 mA
VOL2
0.5
V
D,SEG,MUTE,PSC: IOL= 0.2 mA
100
p.A
K: VI=VDD=5.0 V
Low Level Output Voltage
High Level Input Current
25
IIH
5.0
finl
0.5
2.5
MHz
AM: vi=1.0 Vp-p, DC cut
sine wave
fin2
0.5
8.8
MHz
FM: vi= 0.8 Vp-p, DC cut
square wave
0.5
s
2.0
mA
Frequency Response
60a
Supply Voltage Rise Time
Tr
Supply Current
IDD
0.5
VDD: 0-- 4.5 V
CE: Low Level
jLPD1701 C-014
SYSTEM DESCRIPTION
N EC's Digital Tuning System provides full electronic control of a vari-cap tuned FM/ AM radio receiver and
stereo. The block diagram of the system is shown in Fig. 1. This is a Phase Locked Loop Digital Tuning System
which consists of two integrated circuits; controller plus PLL in a single thip, and two-modulus prescaler.
The controller chip (pPD1701 C-014) provides Phase Locked Loop capability with on-chip frequency
division, a reference oscillator whose frequency is controlled by an external crystal of 4.5 MHz, and phase comparator circuitry. It accepts directly an AM local oscillator signal and an FM signal from two-modulus prescaler
(pPB553AC), and outputs control signals for closed loop operation of these oscillators. The outputs drives filters
for supplying analog voltages to the vari-cap tuners. The controller also provides the signals to drive the display.
The frequency of the tuned station is displayed on a 3.5 digit multiplexed display. Six favorite stations on each
band can be stored as well as "last stations tuned" information.
The two-modulus prescaler (pPB553AC) is suitable for pulse swallowing in this system.
~PD1701C-014
MUTE
MUTE
FM
TUNING
5
EOl
ACTIVE
AM
TUNING
Dl
D5
~
DIGIT
/
DRIVERS
~
1------FILTER
E02
DISPLAY
~PB553AC
FM/AM
FM
OSC.
PRESCALER
i
FM
RADIO
t
PSC
SEG.A
"-
7
AM
OSC.
SEG. G
r-
"-
r-V
SEGMENT
DRIVERS
AM
STATION OETECT-GR
4.5MHz
1
T
Xl
KO
KEY and SWITCH
A
'/
c::::J
crystal
~~
SO
~
X2
4
MATRIX
K3
Fig. 1 Block Diagram
609
tLPD1701C-014
PIN CONNECTION (Top View)
AM
GNO
KO
FM
K1
K2
b
c
d
e
01
02
03
04
a
K3
9
J,&P01701C-014
E01
E02
CE
PSC
X1
X2
SO
MUTE
05
VOO
EXPLANATION OF INPUT AND OUTPUT TERMINALS
E01
E02
These three-state outputs are used (via active filters) to supply analog voltages to the tuner
varicap for controlling the local oscillators.
CE
This input is used to designate the stand-by mode to the chip. It is low to designate the standby mode. (display: off, P LL: disable)
PSC
This output is used to control the division ratio of the FM two-modulus prescaler (J,.LPB553AC).
X1 , X2
SO
This input is used to control the automatic station searching operation. It is high to indicate the
presence of a station.
MUTE
This output line is high to mute the radio in the case of station change, band change, and. so on.
01 to 05
These outputs are used as digit drivers for the display. (Active high)
VOO
This is a 4.5 to 5.5 volt supply for the chip.
a to g
These outputs are used as segment drivers for the display. They are also used as vertical drive
for the control key and mode switch matrix. (Active high)
KOto K3
These inputs are from seven by four matrix. Various functions are entered through the matrix.
See Fig. 2 for the matrix assignments.
FM
This is the FM band local oscillator input. The frequency is divided by 16/17 using a twomodulus prescaler (~PB553AC).
GNO
AM
610
These inputs are for connection to a 4.5MHz crystal.
System ground.
This is the AM band local oscillator input.
flPD1701 C-014
CONTROL KEY AND MODE SWITCH MATRIX
SEG.A
SEG.B
SEG.C
SEG.D
SEG.E
SEG.F
SEG.G
KO
K1
K2
K3
o:
D:
momentary key,
alternate switch,
6:
diode switch
Fig. 2 Control Key and Mode Switch Matrix
*
Manual up or down search
MU, MD
A momentary depression will tune to next channel, and continuous depression more than
0.5 second allows traversing up or down the entire band untilthe key is released.
*
Automatic up search (Saw-tooth search)
SEEK
A momentary depression causes automatic up search which is terminated by activation of SD
terminal (active high).
SCAN
*
A momentary depression causes automatic station-to-station search.
Preset of the station
ME
The tuning information is stored into the internal RAM by depressing ME key and then the
desired memory key (M1 to M6) within 5 seconds from the time ME key was initially depressed.
If any other key is depressed in this period, the ME function is cancelled.
M 1 to M6
Six favorite stations can be recalled from internal RAM for each band. When it is switched from
one band to the other, it will tune to "Iast-tuned-to station" on that band.
Each time a station is changed, the controller provides a signal to mute the radio.
*
Clock set controls
HA, MA
These keys are used for hours and minutes setting. (See note)
DAD
A momentary depression will reset minutes and seconds.
Note
MU and MD keys can be used to set minutes and hours, keeping depressing ME key when time
is displayed.
611
,uPD1701 C-014
*
Switching-over the display between radio and clock
A, B, P
RCAl
Display mode switches A, B initial switch P and control key RCAl control the display mode as
follows.
1. A: ON, B: ON, P:ANY
No priority on the display. A momentary depression of RCAl key causes alternate display
change between time and frequency whenever it is performed. Whenever frequency is
handled, frequency is displayed.
2. A: ON, B: OFF, P: OFF
Clock display is prior to frequency. A momentary depression of RCAl key causes alternative
display change. When time is displayed, a depression of RCAl or one of the frequency
handling key recalls frequency information on the display for 5 seconds. After that, the
display turns back to clock automatically.
3. A: ON, B: OFF, P: ON
Frequency is prior to the clock. A momentary depression of RCAl key causes the alternative
display change. When frequency is displayed, a momentary depression of RCAl key recalls
clock display and it remains there for 5 seconds. If any other key is handled when time is
displayed, handling of one of the time adjust keys (HA, MA, OAD) keeps the time display,
the display turns back to frequency automatically 5 seconds after the time adjust is
completed. Whenever frequency is handled, frequency is displayed.
4. A: OFF, B: OFF, P: ANY
Clock only.
5. A: OFF, B: ON, P:ANY
Disabled.
*
Switching-over the Manual UP/DOWN signal generator
ROT
ON: Pulse repetition rate more than 6 milisecond will be acceptable as MU or MD signal for an
application of the endless-rotary switch as the signal generator.
OFF: Pulse repetition rate more than 60 milisecbnd will be acceptable preventing from miscounting
by chattering of the momentary switches applied for UP/DOWN signal generator.
*
Protection from the miss key input
lOCK
This switch is for protection from miss key input.
ON ............................... AII of the key input is disabled.
OFF ............................. AII of the key input is enabled.
*
Protection from the key chattering
Key make time ............ Iess than 15 ms
Key break time ............ Iess than 15 ms
612
,uPD1701 C-014
* Selection of the radio band
BO,B1
These switches are for selection of the district.
AM/FM
This switch is for selection of the radio band.
Band Switch
Selected Band
80
B1
on
X
off
Receiving Frequency
Channel Spacing Reference Frequency
AM/FM
on
AM Japan
531 to 1 602 kHz
9 kHz
9 kHz
off
FM Japan
76.1 to 89.9 MHz
100 kHz
25 kHz
on
AM Europe
531 to 1 602 kHz
9 kHz
9 kHz
off
FM Europe
87.9 to 107.9 MHz
100 kHz
25 kHz
on
AM U.S. *3
531 to 1 602 kHz
9 kHz
9 kHz
off
FM U.S.
87.9 to 107.9 MHz
100 kHz
25 kHz
on
AM U.S. *3
530 to 1 620 kHz
10 kHz
10 kHz
off
FM U.S.
87.9 to 107.9 MHz
100 kHz
25 kHz
on
on
off
off
* 3: See AM band I F offset
Table 2
* FM band I F offset
IFO, IFl
These switches program the chip to accept 4 different intermediate frequencies.
Intermediate Frequency
IFO
IF 1
Japan Band
Europe Band
U.S. Band
on
off
10.750 MHz
10.650 MHz
10.650 MHz
on
on
10.725 MHz
10.675 MHz
10.675 MHz
off
off
10.700 MHz
10.700 MHz
10.700 MHz
off
on
10.675 MHz
10.725 MHz
10.725 MHz
Table 3
613
,uPD1 701 C-014
* AM band IF offset
I F2
This switch programs the chip to accept 2 different intermediate frequencies.
81
This switch is for selection of the receiving band and channel spacing of AM radio for U.S. band.
80
81
Receiving
Frequency
Channel
Spacing
531 to 1 602 kHz
9 kHz
530 to 1 620 kHz
10 kHz
Intermediate
Frequency
IF2
on
261 kHz
off
450 kHz
on
260 kHz
off
450 kHz
on
off
off
Table 4
*
Display interface
The center frequency of tuned station is displayed on a 3.5 digit LED display. The segment outputs
a, b, c, d, e, f, and g are also used as inputs for 7 segment drivers. The segment outputs go to common
collector NPN transistor array (SlPA56C) to drive the segments of the common cathode 7 segment LED
display. The digit outputs go to NPN darlington transistor array (SlPA53C) to drive the LED display.
I I--I
I I--I
ME
(f)
I--I I- I
I- I I- I
04
05
b
PM
FM.OP
c
CO LON (STOP)
d
COLON (FLASH)
e
9
01
02
03
a
AM
Fig. 4
*
Display format
o Segment Pattern
, ,=.,
I
*
-,
-,
-
, =,
I_I 1-
,- ,-,, ,=,
,=,
'-'
,-, ,-,
=,
Display brightness control (DIMMER)
DIM
This switch is for selection of display brightness.
ON - - - - Display brightness is reduced. (Duty factor: 1/32)
OFF - - - - Display brightness is ordinary. (Duty factor: 1/8)
614
I_'
- Ib
e,7i c
a
fl
d
,uPD1701 C-014
SEG. F orG
SEG. F or G
diode switch: "off"
diode switch: "on"
Fig. 3 Diode Switch
SEG.E
SEG.E
alternate switch: "off"
alternate switch: "on"
Fig. 4 Alternate Switch
615
m
m
~
Fig.5 APPLICATION CIRCUIT
-C
+5V
SEGMENT DRIVER
I
,~
L~ "
, '"'
,,",
17 'v
,
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r
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from
"....,
AM VCO
o:~~ X , JIT
fl r
nnfth
~C NCPSC OUT.!
J.tPB553AC
V" INCHKGND
+5V
from
0
FM VCO
~l~rr ~
~
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crt)
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:r~r~[[~~,I;~n
KO K1
K2
K3
,
b
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d
~PD1701C -014 (Top Viewl
X2 SO MUTE 01 02 03
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.... ,
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radio 'Witoh
...,
12~
~
5V
i+ +~
to J.tPB553AC
_
to radio
f
g
03
0
I_I
02
~
x5
AM
PM
FM.DP
COLON
01
L ___ L ___ L ___ L,
I
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L____ --------- ---------- ~-] 1
I-'PC78M05
•
1001-'
I_I
I-'PA53C
: >
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04
D~I~ ____
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100.-
I_I
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DIGIT
HC-18/U
TOYO COM
TQC-231 A:8C
e
d
0
b
122
c
b
LED (Cathode Common)
0.01 I-'
I-'PC78L05
from
Ace SW. 0
a
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p'7 I p
7f7
4.5 MHz
Oo022.r
10k
from
battery
(12V)
7,
l~ l,.J L)
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20
t..
--- -- --- -- -- -- ---
L_
33n x 7
1
I
.....
I
3.3 k x 7
and .PA56C
_ ZIL 1001-'
7"
,
Muting
Output
~
}
~
A
.......
i
~-" ~L~
EOl E02 CE PSC Xl
l)
1000p
AM TUN. "....,
VOLTAGE
"-
i'l 0i'l
N
10k
FM TUN.
VOLTAGE
i~M GND
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22 k x 4
.
t-
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r--------
KEY and SWITCH MATRIX
I'h
C
_J
MOS DIGITAL INTEGRATED CIRCUIT
pPD1 703C-01 7
PHASE LOCKED LOOP FREQUENCY SYNTHESIZER
TV DIGITAL TUNING SYSTEM CONTROLLER
CMOS LSI
The IlPD1703C-017 is a Single chip CMOS controller designed for using as a Phase Locked Loop Frequency
Synthesizer Digital Tuning System Controller for TV. It consists of a PLL and system controller.
FEATURES
• PLL and Controller is realized in a single chip
•
Pulse Swallowing Method using the IlPB562C
•
VHF/UHF/CATV in U.S. and CANADA
•
Direct tuning by 10 keys and automatic up or down search
•
Last station memory
TV: 1 station, CATV: 1 station (M/S ... off)
•
Manual fine tuning (1 step: 40 kHz ±2 MHz MAX.)
PACKAGE DIMENSIONS
in millimeters (inches)
t:~~=:?:rt
35.15 MAX.
(1.38 MAX.)
I
Fine tuned station memory in VHF and CATV
o Function of remote control
•
28 pin slim dual in-line package (DIP)
•
High speed and low power consumption due to CMOS
•
Single power supply: VDO = 5 ± 0.5 V
•
Low stand-by current ..... less than 10 IlA(CE ... low)
33.02 (1.3)
BLOCK DIAGRAM
vco
Low
Pass
Filter
617
jlPD1703C-017
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VDD
-0.3 to +6.0
V
Input Voltage
VI
-0.3 to VDD
V
Output Voltage
Vo
-0.3 to VDD
V
Output Breakdown Voltage *
VBDS
-35
V
Output Current
IOH
-10
mA
Storage Temperature
Tstg
-55 to +125
Operation Temperature
Topt
-35 to +75
°c
°c
*: Segment Output Terminals (P-ch open drain)
ELECTRICAL CHARACTERISTICS (Ta=-35 to +75°C, VDD=4.5 to 5.5 V)
CHARACTERISTICS
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
MIN.
VIH1
0.8VDD
VDD
V
SD terminal
VIH2
0.7VDD
VDD
V
CE terminal
VIH3
0.6VDD
VDD
V
KO to K3 terminals
VIL1
0
0.3VDD
V
CE terminal
VIL2
0
0.2VDD
V
SD, KO to K3 terminals
VOH1
4.0
V
EO,D,MUTE: IOH=-0.5 mA
VOH2
3.0
V
SEG: IOH=-0.5 mA
VOH3
4.0
V
PSC: IOH=-0.2 mA
TYP.
MAX.
UNIT
TEST CONDITIONS
VOL1
0.5
V
EO: IOL=0.5 mA
VOL2
0.5
V
D,MUTE,PSC: IOL=0.2 mA
100
pA
K: VI=VDD=5.0 V
8.8
MHz
vi=0.8 Vp-p, DC cut
s
High Level Input Current
IIH
5.0
Frequency Response
fin
0.5
Supply Voltage Rise Time
Tr
0.5
Supply Current
IDD
10
pA
CE: Low Level
IOFF
-5.0
pA
SEG: VDS=-30 V
Output Off Leak Current
618
SYMBOL
25
VDD:
0~4.5
V
tLPD1703C-017
OUTLINE OF FUNCTIONS
(1) BANDS
VHF/UHF/CATV in U.S. and CANADA
eM/S ... off
VHF
2ch-13ch
UHF
: 14 ch - 83 ch
CATV : A ch -
W ch
eM/S ... on
VHF
2ch-13ch
UHF
: 14 ch - 83 ch
CATV : A ch -
I ch
(2) FUNCTION OF TUNING
eDirect tuning by 10 keys
eAutomatic up or down search
(3) MANUAL FINE TUNING (MFT)
e1 step: 40 kHz ± 2 MHz MAX
eFine tuned station memory in VHF and CATV
M/S: on ... VHF (2 ch - 13 ch) and mid-band (A ch - I ch)
M/S: off ... mid-band and super-band (A ch - W ch)
(4) AUTO FINE TUNING (AFT)
e1 step: 40 kHz ± 2 MHz MAX
e1 cycle: 5 ms
(5) FUNCTION OF R EMOTE CONTROL
eUse of the pPD1986C (transmitter) and the pPD1937C (receiver)
(6) DISPLAY
eDynamic display of 3 digits (cycle: 150 Hz)
(7) REFERENCE FREQUENCY
e5 kHz
619
jlPD1703C-017
PIN CONNECTION (Top View)
GNO
IN
Kl
K2
Sb
Sc
Sd
Se
Sf
Sg
01
02
03
04
05
VOO
Sa
pPD1703C-017
E01
E02
CE
PSC
Xl
X2
MUTE
EXPLANATION OF INPUT AND OUTPUT TERMINALS
E01
These three-state outputs are used (via active filters) to supply analog voltages to the tuner vari-
E02
cap for controlling the local osc.
CE
This input is used to designate the stand-by mode to the chip.
It is low to designate the stand-bY mode (display: off, PLL: off, system clock: stop).
PSC
X1,X2
SD
This output is used to control the division ratio of the two-modulus prescaler (pPB562C).
These inputs are for connection to a 4.5 MHz crystal.
This input is used to control the station searching operation (CHU/CHD). It is high to indicate
the presence of a station and the operation is terminated.
MUTE
D1 to D5
VDD
Sa to Sg
This output line is high to mute the TV set in the case of station change, band change, and so on.
These outputs are used as digit drivers for the display.
This is a 4.5 to 5.5 volt supply for the chip.
These outputs are used as segment drivers for the display. They are also used as vertical drive for
the control key and mode switch matrix.
KO to K3
These inputs are from seven by four matrix. Various functions are entered through the matrix.
These inputs are provided with internal pull down resistors.
IN
GND
This is the local oscillator input.
System ground.
* Please keep 28 pin open because it is pulled up internally.
620
,uPD1703C-017
COMPOSITION OF KEYS
~""
K3 (22)
K2 (23)
K1 (24)
KO (25)
Sa (21)
1
2
3
CLR
Sb (20)
4
5
6
FTU
Sc (19)
7
8
9
FTD
Sd (18)
CHD
0
CHU
FTR
Se (17)
RCD
RCU
Sf (16)
AFTD
AFTU
AFT
CATV/TV
Sg (15)
M/S
CONNECTION TO THE MATRIX OF KEYS
-l--+-+~~--I-t-+---+-I-4-I41-+--+---+------....------------- to display
o
D
momentary key switch
alternate switch
K
L. diode
or
s-J
'V transistor
621
,uPD1703C-017
EXPLANATION OF CONTROL KEYS
These keys are used for direct tuning. Each station is tuned by using two keys within them (EX,
• 0-9
(10 keys)
8 ch: 0, 8, 12 ch: 1, 2). If a second key is not depressed within 4 seconds from when a first key
was depressed, a first key is cancelled. If wrong ch is selected, the pPD1703C-017 shows the error.
•
•
CLR
(Clear)
This key is used for cancelling a first key when a wrong key (within 10 keys) is depressed first
FTU, FTD
These keys are used for manual fine tuning. While these keys are depressed, tuning frequency
(Fine Tuning Up)
increases (or decreases) by 40 kHz at every 125 ms. The range is ±2 MHz.
(EX. 8 ch: 8, CLR, 0, 8).
(Fine Tuning Down) In VHF and CATV bands (M/S: off ... mid-band and super band, M/S: on ... VHF band and
mid band), fine tuning condition can be memorized at each channel (1 step: 320 kHz). In UHF
band, it returns to each initial condition when other channels are selected.
•
CHU,CHD
These keys are used for automatic up (or down) search.
(Channel Up)
While these keys are depressed, tuning frequency increases (or decreases) to the next station at
(Channel Down)
every 750 ms.
Interval time can be shortened by repeating the depressing of them.
•
FTR
This key is used for resetting fine tuning condition of a current channel.
(Fine Tuning Reset)
EXPLANATION OF MODE SWITCHES
•
AFT
This switch is used for selecting the mode of fine tuning.
(Auto Fine Tuning) While this is on, AFT is effective but MFT is ineffective. In this case, frequency changes automatically by 40 kHz according to the external AFT signal. While this is off, AFT is ineffective but MFT
is effective.
•
CATV/TV
This switch is used for selecting CATV or TV band.
(Band Switch)
While this is on, VHF and CATV bands are selected. While this is off, VHF and UHF bands are
selected.
APPLICATION OF AFT
10 knx 2
.-....------..-----{) + 12 V
Sf
---4--K3
A FT Signal
AFTD
O-__--+--1--T""~
33 knX2
----i---K2
AFTU
2SA733X2
* Please keep the time constant of AFT signal less than 5 ms.
622
,uPD1703C-017
EXPLANATION OF A DIODE
MIS
FUNCTION
off
VHF and UHF or mid-band and super-band can be tuned with CATV lTV switch.
on
VHF, UHF and mid-band can be tuned without CATV lTV switch.
* RELATION BETWEEN CATV CHANNEL AND INPUT CHANNEL NUMBER
-MIS
: off
B
A
C
F
E
D
H
G
·1
J
K
L
M
N
0
P
Q
R
S
T
U
V
W
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
-MIS
A
on
B
C
E
D
G
F
H
I
84 85 86 87 88 89 90 91 92
EXPLANATION OF BAND SIGNAL OUTPUTS
Band signals a're out from four segment outputs (Sa, Sb, Sc and Sd) when D5 is on.
'~
Sa
Sb
Sc
Sd
VL
H
L
L
L
VH,MB
L
H
L
L
SB
L
H
L
H
UB
L
L
H
L
band
H: high level, L :Iow level
623
,uPD1703C-017
EXPLANATION OF REMOTE CONTROL SYSTEM
The pPD1703C-017 can be remotely controlled by using the pPD1986C (transmitter) and the pPD1937C (receiver).
* OUTLINE OF FUNCTIONS
•
Direct tuning by 10 keys
•
Automatic up or down search
•
Function of clear (ClR)
•
Power on/off
•
Muting on/off
•
Volume up/down (32 step)
•
One option
* COMPOSITION OF KEYS AT THE pPD1986C
~
K13 (16)
K12(15)
K11 (14)
K10 (13)
KO (1)
3
2
1
0
K1 (2)
7
6
5
4
ClR
9
8
VOlD
K2 (3)
K3 (4)
K4 (5)
K5 (6)
CHU
CHD
VOlU
K6 (7)
POW
OPT
MUTE
APPLICATION OF REMOTE CONTROL SYSTEM
Se
SE303Ax2
-----+--K3
RCD
47 k
2SA733 x 2
ISS53 x 4
---+--K2
2.2 k
2.2 k
OPT. Out
0----,
RCU
PH302
-----,
38kHzAMP~~~~+-~--~----------~--~-o+12V
+
&
D ET ECTOR
22~
.-+---~+-+-+---.
I
--{)--
L0-
AC 117/100 V
ON/OFF
II
IS954
47 k
~----+-~~~-VOLUME
CONTROL
TO DC ATT
POW VOL VOL
ON/OFF UP DOWN
624
2SD471
APPLICATION CIRCUIT
us
i-a-T-TT-r-(71
1_
;;i ~ : IIIL III
! 'r:
L
~
SSO--f-.
r
VH
0----
11111
t
V L 0>------------'
+5 V
Segment Driver
! !! ! ~ I j II
+5 V
I
111111
!
T
:
I
11 K
I
I
1
1,
I
b
c
d
e
L. __ I ___ I ___ 1___ 1___ 1___ 1_
68
n
l
IJ5~ J
iI
I
I
~ __
I
J_J
x 7(
1
a
m
g
LED (Cathode Common)
-
m
20
0.01 p.
Tuning Voltage
0
0.47p
~
PIt fP
CA:~ 1f ~/7 ~I
-r= +5V
10.01 p.
J,
.----___--'t Se
1
D5
.
D1
D2
[~~~~~~~~~~-~~~~-~~~~~~] ~
4.5 MHz
HC- 18/U
TOYO COM
TQC-231A
-8C
4.7 k
2SC945 x 2
1::::
""C
C
....l
--.J
o
eN
('")
(Muting Output
I
}
SD Input
m
N
U1
active high
o
....l
-...J
MOS DIGITAL INTEGRATED CIRCUIT
fLPD1703C-018
PLL FREQUENCY SYNTHESIZER AND CONTROLLER
FOR LW,MW AND FM TUNERS
The J,LPD1703C-018 is CMOS LSI with built-in PLL and controller capable of receiving LW/MW/FM in
U.S.A.,. Europe and Japan.
The J,LPD1703C-018 is provided in a shape of 28-pin Slim DIP (Dual In-Line Package) with less substrate
occupying area.
In combination with a dedicated prescaler J,LPB553AC, J,LPD1703C-018 is capable of composing high-fidelity
LW/MW/FM digital synthesizer tuners for stereo systems such as home stereo systems.
FEATURES
•
F IP (Fluorescent Indicator Panel) direct drive capability (segment only).
•
Built-in PLL, swallow counter and controller.
•
Low data retention current (10 J,LA or less)
•
Capable of preset station display (dot display by LED).
•
FM reference frequency is as high as 25 kHz (the pulse swallowing method is employed).
•
LW/MW/FM in U.S.A., Europe and Japan are selectable by the initialization switch.
•
9N/9N + 2 switching of LW is possible (9N ... 153 - 351 kHz, 9N + 2 ... 155 - 353 kHz).
•
Seven (7) buttons-Fourteen (14) preset station memories (7 for FM and 7 for LW + MW).
•
Momentary or alternate switches can be used as a preset station key and band selector key (MW·FM).
•
Last channel memory is available for each LW/MW/FM band.
•
AUTO and MANUAL UP/DOWN selection is possible (saw tooth wave tuning).
•
FM IF offset capability (4 ways by 25 kHz step)
•
Built-in frequency preset function for adjustment at time of mass production of a set.
•
European FM band 4.1/2 digit display (other bands are displayed in 4 digits).
•
28-Pin Slim plastic DIP; saves board area.
•
A single power supply of 5 V ± 10 %.
PACKAGE DIMENSIONS
in millimeters (inches)
E:~=::~lI
.35.15 MAX.
O.3SMAX.)
.
I
-:BS.5(0.33)
~~
r------------------,~~~.~~~~
-ffr-A- f""t--f'9r-A-IR-fI'HfI--Fl-I1-Fr-A-R-f'...... q
N C\!
_ .n 9
-
0.25
~i
(0.01)
~~
2.54 (0.1)
33.02
(1.3)
626
~
M
~
10.16
(004)
0° - 15°
tLPD1703C-018
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VDD
-0.3 to +6.0
V
Input Voltage
VI
-0.3 to +VDD
V
Output Voltage
Vo
-0.3to+VDD
V
Output Absorption Current
10
10
Operating Temperature
TOPT
-35 to +75
Storage Temperature
Tstg
-55 to +125
°c
°c
Output Breakdown Voltage
VBDS
Sa-Sg terminals -35
V
rnA
(Drain source voltage)
RECOMMENDED OPERATION CONDITIONS
CHARACTE R ISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
5.0
5.5
V
Supply Voltage
VDD
4.5
RAM Retention Voltage
VRAM
2.5
V
Output Breakdown
CE terminal = 0
Sa-Sg terminals (Drain
-30
VBDS
V
Voltage
Supply Voltage Rise Time
CONDITION
sou rce vo Itage) 10 F F=-5 JlA
Trise
500
ms
MAX.
UNIT
VDD=Oto4.5V
ELECTRICAL CHARACTERISTICS
CHARACTERISTIC
SYMBOL
MIN.
TYP.
CONDITION
High Level Input Voltage
VIH1
0.8VDD
VDO
V
SO terminal
"
VIH2
0. 7V OO
VOO
V
CE terminal
"
VIH3
0. 6V OD
VDO
V
KO-K3 terminals
Low Level Input Voltage
VIL1
0
0. 3V OO
V
CE terminal
"
VIL2
0
0. 2V OO
V
SO, KO-K3 terminal
High Level Output Voltage
VOH1
4.0
V
PSC, MUTE, 01 - 05 terminal IOH = -0.2 mA
"
VOH2
4.0
V
E01, E02 terminals
IOH = -0.5 mA
627
tLPD1703C-018
High Level Output Voltage
VOH3
Low Level Output Voltage
VOL1
"
VOL2
High Level I nput Current
+1'H1
"
+1'H2
Low Level Input Current
-11L1
Output Leakage Current
628
V
Sa - Sg terminals
IOH = -0.5 mA
0.5
V
E01, E02 terminals
IOL = 0.5 mA
0.5
V
MUTE, 01 - 05, PSC
terminals IOL = 0.2 mA
100
JlA
KO - K3 terminals
V,N = VOO = 5.0 V
300
JlA
X1 terminal
V,N = VOO = 5.0 V
300
JlA
AM, FM terminals
V,N = OV, VOO = 5.0 V
1
JlA
E01, E02 terminals
Vo = V 0 0 = 5.0 V
3.0
5.0
25
10-3
IL
AC Input Voltage
Vin
1.0
VOO
Vp_p
AM, FM terminals
Response Frequency
fAM
0.5
2.5
MHz
AM terminal, Vin=1.0 Vp_p
(MIN.), DC cut
"
fFM
0.5
8.8
MHz
FM terminal, Vin=0.8 Vp_p
(MIN.), square wave, DC cut
Operating current
1001
mA
Normal operation (excluding
display current)
"
1002
JlA
CE terminal = 0 Ta = 25°C,
VOO = 5 V
RAM Retention Voltage
VRAM
Output Breakdown Voltage
VBOS
3
10
2.5
-30
V
CE terminal = 0
V
Sa - Sg terminals (Drain
source voltage), IOFF=-5 JlA
JLPD1703C-018
OUTLINE OF FUNCTION
Receiving Frequency, Channel Spacing, Reference Frequency, Intermediate Frequency
~
U.S.A.
Europe
Japan
Frequency
Channel
Reference
Range
Spacing
Frequency
MW1
530 - 1 620 kHz
10 kHz
10 kHz
MW2
522 - 1 611 kHz
9 kHz
9 kHz
FM
87.9 - 107.9 MHz
200 kHz
25 kHz
MW
522 - 1 611 kHz
9 kHz
9 kHz
LW1
155 - 353 kHz
9 kHz
1 kHz
LW2
IF
450 kHz
10.650,10.675,10.700,10.725 MHz
450 kHz
153-351 kHz
9 kHz
1 kHz
FM
87.50 - 108.00 MHz
50 kHz
25 kHz
MW
522 - 1 611 kHz
9 kHz
9 kHz
450 kHz
FM
76.1 - 89.9 MHz
100 kHz
25 kHz
10.675,10.700,10.725,10.750 MHz
10.650,10.675,10.700,10.725 MHz
Tuning Functions
(1)
AUTO UP/DOWN TUNING (Saw Tooth Wave Mode).
When a high level is input at SO terminal, the auto tuning is stopped and signal from that station is
continuously received.
(2)
MANUAL UP/DOWN TUNING (Saw Tooth Wave Mode)
Step forwarding by the momentary switch. Further, when the switch is kept depressed for more than
0.5 sec., the receiving frequency is continuously forwarded till the switch is released.
(3)
Preset Memory Calling
FM .......... 7 channels (M1 - M7)
LW + MW ..... 7 channels (M1 - M7)
FM and LW+MW are of 7 channels independent preset type. LW and MW are of total 7 channels
random access preset type.
DESCRIPTION OF TERMINALS
Terminal Configuration Diagram (Top View)
EOl
AM
E02
2
GNO
CE
3
FM
PSC
4
KO
Xl
5
X2
6
SO
7
MUTE
8
01
9
Kl
1:
K2
-0
0
'-J
22
K3
w
()
21
Sa
6
......
20
Sb
19
Sc
0
CO
52
10
03
11
18
Sd
04
12
17
Se
55
13
16
Sf
VOO
14
15
S9
629
jlPD1703C-018
Terminal No.
Symbol
Terminal Name
Description
Charge pump output from the phase detector composing P LL.
When the divided oscillation frequency is higher than the reference frequency, these terminals go high, and when lower than
reference frequency, low level is output. When both are in accord
Error Out
with each other, the terminal become floating.
As the same signal is simultaneously output on E01 and E02,
2
these terminals may be connected to either LPF (Low Pass Filter)
of MW, LW or FM.
Activation of this device is controlled by this terminal.
When the device is to be normally operated, set this terminal
at the high level, and when the device is not used, set at the low
level.
High level ... Normal operation
3
CE
Chip Enable
Low level ... Memory retantion state
(stand-by current is
10 pA or less. Display is OFF, PLL is stopped
functioning, internal clock generator is stopped.)
Note that CE terminal only accepts the pulse that is longer
than 134 ps. Be sure to force this terminal high after the VDD
terminal is 4.5 V or above.
This terminal outputs a signal to switch the modulo of the
two-modulus prescaler when a pulse swallowing method is used
4
PSC
Prescaler
Control
for frequency division (in case of FM).
This terminal should be connected to PSC terminal of a dedicated two-modulus prescaler pPB533AC.
5
X1
The X'tal oscillator terminals. A 4.5 MHz X'tal should be conX'tal
6
X2
nected to these terminals. (Toyo Tsushinki: TQC-231A-8A is
recommended)
When this terminal is forced to high level in AUTO TUNING
7
SO
Station
Detector
(AUTO UP/DOWN) mode, the scanning is quitted.
A high level signal should be input within 75 ms after PLL is
locked.
This terminal outputs an active-high signal for muting shock
noise when PLL is out of lock.
When CE terminal is forced to low level (back-up state), this
terminal is forced to low level unconditionally.
The length of the muting signals are as follows.
At time of LW/MW/FM switching ... 700 ms (TYP.)
At time of MANUAL UP/DOWN
8
MUTE
MUTE
... 200 ms (TYP.)
( 1 step operation)
At time of AUTO UP/DOWN
... 200 ms (TYP.)
(after SO terminal is forced to high level.)
At time of Preset Memory calling
... 450 ms (TYP.)
Above show the muting signal which is output just after PLL
data are changed. Actually, premuting time of 50 ms (before PLL
data change) is added for. (For details, see MUTE Timing Chart
on Page 645.)
630
,uPD1703C-018
These terminals are the display digital signal outputs and are
Digit Outputs
active-low.
(For details, see the display connection diagram on Page 640.)
This is the power supply terminal of the device. When the
device is in operation, 5 V±1 0 % should be supplied. Under the
preset memory back-up condition, supply voltage can be reduced
14
VDD
VDD
to 2.5 V.
Note that the rise time of supply voltage VDD must be 500 ms
or less.
If the rise time is excessively long, the initialization
will not be operate properly.
These terminals are the display segment signal outputs and
key return signal source terminals, and are active-high.
Sa - Sg
Segment
Outputs
(For configuration of key matrix see Page 632.)
As these terminals withstand voltage up to-3D V, they can be
directly connected to the segment terminal of F IP (Fluorescent
Indicator panel).
(For details see the display connection diagram on Page 640.)
Key Return
22 - 25
Signal Inputs
These terminals are the input terminals of key return signals
from the external key matrix. (For details see the key matrix
configuration shown on Page 637.)
26
27
28
FM
GND
AM
FM Local
FM local oscillator divided in 1/16 or 1/17 by the prescaler
Oscillator
JlPB553AC is input into this terminal. As an AC amplifier is
Signal Inputs
built in, signals should be input after DC is cut by a capacitor.
GND
This terminal should be connected to a system ground.
AM Local
Signals from MW and LW local oscillator are input to this
Oscillator
terminal. As an AC amplifier is built in, signals should be input
Signal Inputs
after DC is cut.
631
j.lPD17.03C-018
1. CONFIGURATION OF KEY MATRIX
1-1 Arrangement of Key Matrix
KO (25)
Kl (24)
K3 (22)
K2 (23)
MEMORY
Sa (21)
Sb (20)
Sc (19)
Sd (18)
Se (17)
Sf (16)
S9 (15)
(
D
Momentary Switch
I~I
Momentary or Alternate Switch
Alternate Switch
Diode Matrix (Short or Open by Diode)
D
632
Open
) is Terminal No.
jlPD1703C-018
1-2. Connection of Key Matrix and Type of Switch
Sa
Sb
Sc
------r_~~~~~~~~~~~----r_--~~--------------------------------
Sd ----__i--~f-+_t_--f-t--l-__+_t_I_+___t_--__il_--_t----_....-------------------------- To 0 isplay
Circuit
Sf
Sg
----~~--7+~--~~_.~r_--+_----r_--__i----_+----~----4_----._--------__
KG
Kl
K2
K3
Sa
Sb
Sc
Sd
Se
Key Input
-+-$•
+
Sg
Sf
.
Momentary Switch
Momentary or Alternate Switch
Alternate Switch
Diode Matrix (Short or Openl
As the preset station Keys (M1 -
M7) and Band Selector Keys (FM, MW), either Momentary or Alternate
Switch can be used. However depending upon which switch is used, an inserting position of diodes (for preventing
turn-around of key return signal) may differ.
The following shows the examples;
633
,uPD1703C-018
Example 1: When Momentary switches are used as Preset station Keys and Band Selector Keys.
~----~4--+~--+44--4~~~~------------------------------------~
Sb----~~~~~~~--~~~~--~~--------------------------------~
Sc ----~-4+t--+_1_4_-~~...+_--_1~--.......- - - - - - - - - - - - - - - - - - - - - - - - - - - - To Display
Circuit
~----~--~~~~~~~r+__~--~----r_--~-----------------------'-
Sf ----~~~~--~~--~----~--~----r_--_+----~--~------------~
S9 ----~~--~~~~--~~--~----~--_+----4_----~--_+----._-----~-
KO
K1
K2
K3
Sa
Sb
Sc
Se
Sf
Sg
Example 2: When Alternate Switches are used as Band Selector Switches.
~ ----~~~~+-_r~--~~~~-------------------------------------~
Sb ----~~~~+-~~--r+;-~~--~~-----------------------------~
H-----+----+------------------------------
Sc ------lI-----iH--+--++4---f-+-l-......
~ ----~-----r--~~--~~--~----+----+----~------------------------
Sf ---~~-~r-_r~--~----~----+----+----~----r_--_+--------------
S9 ----~~--~~~~--~~--~----+---_+----~----~--_+----4_--------
KO
634
K1
K2
K3
Sa
Sb
Sc
Se
Sf
Sg
To Display
Circuit
,uPD1703C-018
Example 3: When Alternate Switches are used as Preset station Keys and Band Selector Keys.
Sa --~~+--rT+--r+~-r~-M~----------------------------------------
Sb --~~+-~~--r+~-r~--~----~----------------------------------
Sc ------+----+-+-+--t-+-+--+-+-+--+-----+----.------------------------ To Display
Circuit
Sd
Sf
S9
----~~~~--~~~~--+-----+----4----4_-~~-~-~~-----
KO
Kl
K2
K3
Sa
Sb
Sc
Sd
Se
Sf
__
Sg
(Note) LW Key cannot be used as Alternate Switch.
635
jlPD1703C-018
2. DESCRIPTION OF KEY MATRIX
2-1. Initialization Diode Matrix
Initialization Diode Matrix is available in 4 types as shown below. These matrixes are read in when power is
initially supplied to VDD (initialize) and when CE terminal is changed from low fevel to high level. However, the
9 kHz/l0 kHz and 9N/9N+2 Switches are constantly read in. Even in this case, PLL data and display are changed
only when a momentary switch (UP, DOWN, Ml - M7 Switches) is depressed.
(1) Switches for specifying I F offset of FM
IF1,IFO
(2) Switches for specifying FM band area (U.S.A., Europe, Japan)
BAND 1, BAND 0
(3) Switches for specifying MW band channel spacing and reference frequency
9 kHz/10kHz
(4) Switche for selecting LW band frequency range
9N/9N+2
These initializations will be performed by shorting or opening the intersecting points on the matrix by Diode.
(In the following table, "1" means shorting by Diode and "0" means opening.)
Symbol
Description of Function
Switches for specifying I F offset frequency of FM.
IF offset can be varied in 4 levels, as shown below, by 25 kHz step without changing indicated
frequency:
IFl
IFO
IFl
IFO
U.S.A. Band
European Band
Japanese Band
0
0
0
1
10.700 MHz
10.700 MHz
10.700 MHz
10.725
10.725
10.675
1
0
1
1
10.650
10.650
10.750
10.675
10.675
10.725
Switches for specifying FM band areas.
One of FM bands of U.S.A., Europe and Japan can be selected.
BANDl
BANDO
BANDl
BANDO
Band Area
Frequency Range
Channel Spacing
200 kHz
0
0
U.S.A. Band
87.9 - 107.9 MHz
0
1
European Band
87.50 - 108.00 MHz
50 kHz
1
0
Japanese Band
76.1 - 89.9 MHz
100 kHz
1
1
Prohibited *
* Both BAND1 and BANDO must not be ON (1). If both are ON, the band area will not be
properly set.
Switch for specifying MW band channel spacing, reference frequency and frequency range.
The setting can be independently made regardless of FM band areas (BAND1, BANDO).
9 kHz/l0 kHz
636
9 kHz/10 kHz
Frequency Range
Channel Spacing
Reference Frequency
0
530 - 1 620 kHz
10 kHz
10 kHz
1
522 - 1 611 kHz
9 kHz
9 kHz
,uPD1703C-018
This switch is always read in. However, PLL data and indication will change only when a
momentary switch (UP, DOWN, M 1 - M7, etc.) is depressed.
Switch for selecting LW band frequency range.
9N/9N + 2
9N/9N+2
Frequency Range
Channel Spacing
Reference Frequency
0
155 - 353 kHz
9 kHz
1 kHz
1
153 - 351 kHz
9 kHz
1 kHz
This switch is always read in. However, PLL data and indication will change only when a
momentary switch (UP, DOWN, M1 - M7, etc.) is depressed.
2-2 Alternate Switch
Symbol
Description of Function
This is an AUTO/MANUAL tuning selector switch.
ON (1) ... AUTO Tuning
OFF (0) .. MANUAL Tuning
AUTO/MANUAL tuning starts when UP or DOWN momentary switch is depressed after this
switch is set at ON or OFF position.
(For details see Momentary and Alternate Switches on Page 632.)
(Note 1)
AUTO tuning operation does not stop even when this switch is changed to MANUAL Tuning
AUTO/
during AUTO Tuning operation. If it is desirable to stop AUTO tuning simultaneously with the
switching to MANUAL tuning, a system should be so configured that high level signal is constant-
MANUAL
Iy supplied to SO terminal during MANUAL tuning.
(Note 2)
In Auto tuning mode, the J.LPD1703-018 increases or decreases frequency step by step corfirming that the PLL system is completely locked, in order to scan the band as fast as possible. Therefore if the PLL system is malfunctioning and is not locked, the J.LPD1703-018 halts the AUTO
tuning operation and waites for the PLL to be locked. In this condition, all the keys are not accepted. To escape this condition, force CE terminal to low level then high level, and the frequency
can be varied by manual tuning.
In the recomended application, the CE terminal is to be connected to the main-power-supply of
the set. So the end user can vary the frequency after operating the power-supply-switch, even if
the above malfunction occurs.
637
,uPD1703C-018
2.3 Momentary and Alternate Switches
Either momentary Switch or Alternate Switches can be used as Preset Keys (M 1 - M7) or Band Selector
Keys (MW, FM).
When Alternate Switches are used for Preset station Key, the interlocking including UP and DOWN Keys is
required.
Symbol
Description of Function
This switch is used to write frequencies for tracking adjustment at factory into the preset
memories. When this switch is depressed, following frequencies are written into the preset memories (M1 - M7):
FM
(1 ) When U.S.A. Band (BAND1=0, BANDO=O) is set:
M1
M2
M3
M4
M5
M6
M7
89.7 MHz
101.7 MHz
87.9 MHz
87.9 MHz
92.9 MHz
-
-
M5
M6
M7
90.0 MHz
-
-
(2) When European Band (BAND1=0, BANDO=l) is set:
M1
M2
M3
M4
88.40 MHz 94.40 MHz 100.40 MHz 106.0 MHz
TRACKING
(3) When Japanese Band (BAND1=1, BANDO=O) is set:
POINT
PRESET
M1
M2
M3
M4
M5
M6
M7
77.0 MHz
83.0 MHz
89.0 MHz
76.1 MHz
78.6 MHz
-
-
M6
M7
MW
(1) When Channel Spacing 9 kHz (9 kHz/l0 kHz=l) is set:
I
61:~HZ I
M2
1503 kHz
M3
I
-
M5
M4
I
-
I
-
I
-
I
-
I
(2) When Channel Spacing 10kHz (9 kHz/1 0 kHz=O) is set:
Ml
I
630 kHz
M2
I
1620 kHz
M3
I
-
M5
M4
I
-
I
-
M7
M6
I
-
I
-
I
- indicates "Don't Care" (previously stored content is called).
This switch is used to write the currently received frequency into Preset Memory.When either
one of M1 - M7 Keys is pushed within 5 sec. after this key is pressed, the frequency displayed
MEMORY
is written into a memory corresponding to the key pressed.
To release the memory·write-enable state before the 5 sec. push UP/DOWN key or switch
LW, MW, FM Bands.
638
jLPD1703C-018
These are the preset memory writing and calling keys.
It is possible to store FM and MW or LW stations per one button. As MW and LW are of random
preset type, storage in optional location in total 7 channels M1 - M7 is possible.
(1) Write
When either one of M 1 - M7 keys is pushed within 5 sec. after MEMORY key is pressed,
the frequency currently received is written into a memory corresponding to the key pressed.
M1 - M7
(2) Calling
When either one of M 1 - M7 keys is pressed, content (frequency) of a memory corresponding to the key pressed is called out. When a preset key is pressed, a mute signal of approximately 450 ms is output.
And when frequency bands are switched (LW ---+ MW or MW - + LW), a mute signal of
approximately 750 ms is output.
(For details see MUTE Timing Chart on Page 645.)
These are AUTO and MANUAL tuning keys. When these keys are pressed, the following
operations are executed:
(1) When AUTO/MANUAL Switch is set at AUTO:
oWhen UP key is pressed, frequency is continuously kept going up in saw tooth wave form.
If a high level is input in SD terminal at this time, AUTO UP operation is stopped.
UP
When DOWN key is pressed during AUTO UP mode, the mode changes to AUTO DOWN
operations.
oThe operation of DOWN key is almost the same as UP key. The only difference is that this
DOWN
key decreases the frequency.
*1. In AUTO UP or DOWN operation, frequency is going up or down at the speed of 80 ms/step.
*2. When UP key is pressed in AUTO UP operation or DOWN key in AUTO DOWN operation, AUTO UP/DOWN operation is kept continued. In addition, when UP or DOWN key is
kept pressed, AUTO UP or DOWN operation does not stop even when the SD terminal is
forced to highllevel.
MW
FM
LW
These are FM, MW and LW band selector switches. Alternate Switches may be used for FM
and MW. (Alternate Switch cannot be used for LW.)
When the bands are switched, a MUTE signal of approx. 750 ms is output through MUTE
terminal.
639
,uPD1703C-018
3. DESCRIPTION OF DISPLAY
3-1 Desplay Connection Diagram
The display connection diagram is shown below. D1 - D5 and Sa - Sg correspond to the digit terminals (01 - 05) and the segment terminals (Sa - Sg) of pPD1703C-018.
The segment terminals of pPD1703C-018 are capable of withstanding voltage up to -30 V (P-ch open drain
output) and it is therefore possible to connect these terminals direct to FIP (Fluorescent Indicator Panel).
The digit lines should be connected to F IP via one-stage buffers (PNP transistor), because those outputs are
CMOS-complementary-type and active-low.
I
n n
I
FM
I
1 1
I 1
I
I
I
I
I
I
1
1
I
n ,.' o
(Sg):
MW(Sa)1
LW (Sd):
I(Sg~
~
l
I
1
I
I
:
1
I
(Sg)
I~I IMEMO
I(sg)
I ___ :MHz
l(st)1
I
~
I
04
03
02
005
01
(Sg)
(Se) I(Sg):
(Sg)
1KHz
:
(Note 2)
005
(Sb)
(St)1
005
(S~ + Sd)
(Note 1
05
Fig. 1 Display Connection Diagram
(Note 1)
Display of "kHz" is made by OR signal of Sa and Sd. If no LW is available, "kHz" can be displayed by
Sa only.
(Note 2) This is the digit for "50 kHz" in Europe an FM. Note that this digit is controlled by only 3 segment
lines; Se, Sf and Sg, and organized the number "5" and "0".
In MW and LW, nothing ts displayed here. For FM in U.S.A. and Japan, don't connect the 05 or Sg
line in this digit.
640
jlPD1703C-018
3-2 Examples of Display
Shown below are examples of display when F IP shown in Fig. 1 is used.
(1) FM in U.S.A.
MHz
FM
(2) FM in Europe
FM
MHz
(3) FM in Japan
MHz
FM
(4) MW (Channel Spacing 10 kHz)
MEMO*
MW
kHz
(5) MW (Channel Spacing 9 kHz)
MW
kHz
(6) LW in Europe
)-,
LW
'_I
kHz
* MEMO Display lights up for 5 sec. after the momentary key MEMORY is pressed.
When Preset Station key M1 - M7 is pressed following the MEMORY key, the currently received frequency
is written and then the MEMO display disappears.
641
,uPD1703C-018
4. PRESET STATION INDICATORS*
An example of the preset station indicator circuit is shown in Fig. 2. The timing chart at this time is shown in
Fig. 3.
To Segment terminals of FIP
1SS53
P1
P2
+5 V
P3
P4
SlPD1703C-018
5V
300 n.
P5
P6
P7
ip-------
To digit terminal of FIP
100 kn.
-25 V
Fig. 2 Example of Preset Station Display Connection
02
1.
Tl
.1
04
HI·
i
t
Tl
·1
t-FreqUenCy Display (Display of Highest Significant
~Position"1")
Preset Station Display (BCD code is transmitted
from Se - Sg)
Fig. 3 Timing Chart
In this system, the most significant digit of display is to be connected to two segment lines Sb and Sc, and it dis*
plays "1" or blank
By using the remaining segment lines at the most significant digit timing, data for the preset station indicator are
output. The preset data are output on the Se-Sg lines at the rising edge of 04 (most significant digit signal) in
BCD form.
The J,tPD4035BC in Fig. 2 latches the BCD preset station data at the rising edge of 04, and the
J,tPB74LS42 decodes the BCD data and then drives the LEOs. Consequently preset station indicators are displayed
in static.
642
,uPD1703C-018
* Preset station indicator shows which preset memory is selected.
Output Status Through Segment Terminals Sa - Sg
at Timing T1 and T2 of Digit Signal D4
~t
Imlng
Sa
Sb
Sc
Sd
Se
Sf
S9
Blank
Blank
Blank
T1
Blank
Highest Significant
Position "1" Display
or Blank
Blank
T2
Blank
Blank
Blank
Blank
BCD Code Output
Preset Station BCD Code Output
Sg
Sf
Se
Preset Station
0
0
1
P1 (M1 Key)
0
1
0
P2 (M2 Key)
0
1
1
P3 (M3 Key)
1
0
0
P4 (M4 Key)
1
0
1
P5 (M5 Key)
1
1
0
P6 (M6 Key)
1
1
1
P7 (M7 Key)
643
,uPD1703C-018
5. TIMING CHART
5·1 Display and Keying
Segments Sa ,." Sg
Segment Output
Digit 51
I
J
I
1
1
1
I
Digi t Output 100 iJS I
100 iJS ~
,33.3 iJS
I
200 "'s (TYP.l
1
I
1
I
I
I
I
I
I
1
I
1
Sa
i
I
33.3 iJS
I
I
I
I
I
KEY return
signal source segment output
200 iJS
(TYP.l
t
Keying
ISe "" Sgl
I •
• 1•
I
,
Sb.Sc
I
.1
Sa"" Sg
I
I
I
Segment output
Preset station
display output
66.6 iJsl
I
Digit 0 utput
33.3 iJS ~
1
I
I
I
,
J
,I
I
33.3",s
100 ",sl
I
J
600 iJS (TYP.)
,I
I
Sd
33.3 iJS
KEY return signal
segment output
I
200 iJS
:
(TYP.l
I
t
Keying
644
j.lPD1703C-018
5-2 MUTE Timing Chart
(1) KEY ON chattering preventing time
(2) MUTE first-out time
(3) Division ratio setting and display content updating time
(4) MUTE last-out time
(5) Scan time
(6) PLL lock time
(1) MANUAL UP/DOWN
(D
I- 15 ms
_.
~
.1
4_5_m_s~__~.+i_~----10--m1!~II!_.----~12~5~-~2~5~0~m~S~__~.~1
____
I
I
_
'------
Band Edge (Max. Frequency ~ Min. Frequency. Min. Frequency ~Max. Frequency)
(f)
____
~----U)--~~I.-----4~5-m~s----.~i-:----10--m~~*i_.------------6-2-5----7-5-0-m-s------------~.~I_____________
I.. 15 ms ·1
(2) AUTO UP/DOWN
When SO signal is input
@
15-
45 ms
10 ms I
125 - 250 ms
75 ms
CD
I
SO detection (input available)
When no SO signal is input.
45 ms
15-
10 ms
I
75 ms
15 ms
15-
10 ms I
75 ms
SO detection (no input)
SO detection (no input)
Band Edge (Max. Frequency ~ Min. Frequency. Min. Frequency ~ Max. Frequency)
@
45 ms
I
5 - 10 ms:
375 - 500 ms
:
I
I
75 ms
I
I
125 - 250 ms
CD
I
I
I
15 ms
l
SO detection (input availabel)
645
jlPD1703C-018
(3) PRESET MEMORY CALL
I
i 5 .... 10 ms ..i
45 ms
375 .... 500 ms
I
~.----------~.~.-.------.~
: : ~----~~~~~------~.
ffi
~
___________________
\·15 ms .. \
When the band is changed (MW -+ LW. LW -+MW)
ffi
I
i 5"" 10 m~ :
45 ms
---""1-,1-5-m-s-.I'"
I
I
(4) When FM/MW/LW are switched and Power is ON (CE
___
__
~__ffi__~I~.
I- 15 ms ·1
646
625"" 750 ms
~4_ _--~~--~1~----_1~----------~~----------------~
.....- - - - - - - -
= Low -+ High)
®
.~i._5_""_1_0_m~s~.i~.___________6_2_5_-_7_5_0_m_s____________~.~I
--4_5_m_s--__
________
,uPD1703C-018
6. EXAMPLES OF FM/MW/LW POWER SUPPLY SWITCHING CIRCUIT
When Momentary Switch is used as a FM, MW, LW band selector switch, the tuner side power supply switching should be performed externally by the circuits shown below.
Input signal in the following diagram utilizes symbol of display ("FM", "MW", "LW") signals.
Example 1
J,LPD4011BC
r- - - - - - - - ...,
Segment Output
FM(Sg) ~------__~4_--~
D-....-"'---------
FM
~~r_--------~_
MW+LW
J,LPD4011 Be
MW(Sa)
r---------,
~""-r_-------~- MW
O-~t---------4-
LW
Digit Output
C LOC K (D5)*(}------__~4_..J
5V
Example 2
Segment Output
FM(Sg)
,....--~FM
' - - - - - ME+ LW
,....---- MW
' - - - - - LW
Digit Output
CLOCK (05)* ~-----af-""""..J
*Note: CLOCK (05) is the inverted signal of 05 terminal from J,LPD1703-018. Output of digit buffer can be used as this signal.
647
m
~
(J)
~
."
C
APPLICATION EXAMPLE OF CIRCUIT DIAGRAM
+ 40mentary
c:::>
SWI
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,17\;
.I,
,
.I\,
~,
',/
I"'~I'" ~I'"
\,~ \,
I"'~ ~
I"'~
1SS53 ~
leode Matrix)
-
t
,,~
IN CHK GNO
v
0.011l F
Fro m FM VCO
±
"- ~"- ~
KO
K1
Ho
Il..... 20 pF ~
->-
I...J )
-,o"T
~~I'"
K3
Sa
Sb
Iii"!
1B
Sc
Sd
Se
nI
'
'I
V"-
""
100 k11
O""C
Set Main Switch
-25 V
~t 1SS53
~~
High capacitance capacitor 1
(for back-up)
i>7
i i I
1m21m
18117116115114113J
GNOP/S CK R J K TIC OA
,t
~
f--
. .+-f-
~
100 k11
IlPD4035BC
A B C 000 Oc OB VOO
9111011 11 111211131114111511161
0.01 IlF
~
,'177 7~
'-~""l:..-
,,,,
., . . . F
2SC945
)
100kl11
1
I
,-l
5V
1
~
r-
161]15j 11411 13111211lill101 91
VCC A 8 C 0 9 8 7
74 LS42
v,......,~
77
I
5V
J2SA733
.,"-
1SS5:
-25 V
+5 V
47
k11
~~
L.....--
r
47
k11
~~
~~ ~ ~
100 k11
Sg
.----
To =M VCO
......
...,
9
n-~
2SC945
+5 .7 V
Sf
*
')2
T~ F
P
I
H:
.....
K2
~w~~ CU~LUlt~ML~JEL~ ;~~~~;
47 k11
,...
'" ~~
IlPD1703C-018
I
1SS53
To ... W,MWVCO
f
r;4) r,5J r;il
/7
0.01 IlF
e
r~
~ L.U
33
AM GNO FM
H
0
I-" "
~ ~ ~ t ~~
L
CO
gment
of FIP
d
PF
LpLU~4J
+5V
C
''"
~
,. t'\,. t'\t..
"I-' , 1-"
I
o
...a
b
r--
;
VCC
I'
i
mmrt,r51
NC NC PSC OUT
IlPB553AC
~\"
(')
a
GGG1
-r.
~ ~~ r;~
r;~;~ r~r.m
"-~
0.0,1, IlF
0·4
w
....
,
,
'I'"
~ "
"I'"
\,,1-/ , 1-" " ,...
Iternate SW)
.....
....
o
1SS53
I"~I'" ~I" 'I'"
Fro n LW,MWVCO
...a
.......
0
To
Grid
of
FIP
2
3 4 5 6 GNO
1121 31 411 5 1161PII81
1
I
PI
J~ ~ ~~
P
G
G
P~
~ ~
30011
( MUTE Output
+5 V
SD Input
*4.5 MHz X'tal (Toyo Tsuhinki: TOC-231 A-8C)
The applied circuits and circuit constants listed in this material are not intended for mass production design with deviations and temperature characteristics of component
parts considered. Further, this company will not assume any responsibility as regards the patents on the circuits listed in this material.
MOS DIGITAL INTEGRATED CIRCUIT
flPD1703C-020
PLL TUNING RADIO CONTROLLER AND
24 HOUR DISPLAY FORMAT TIMEPIECE WITH TIMER CIRCUIT
The I1PD1703C-020 is a CMOS LSI with 24 Hour display format timepiece built-in with timer circuit and
PLL controller capable of receiving LW/MW/FM in U.S.A., Europe and Japan.
In combination with a prescaler I1PB553AC, I1PD1703C-020 can provide LW/MW/FM digital synthesizer
tuner with timer clock.
Since the package of I1PD1703C-020 is slim DIP (Dual In·Line Package), it greatly simplify Clock-Radio in
design and assembly.
FEATURES
Clock part
• 24 hour display format clock. ([Hour], [Minute])
• Control timer with snooze timer.
• Duration of control timer and sleep timer is 64 minutes.
• Duration of snooze timer is 4 minutes.
• Program tuning (ie. To receive the programed station at the control time set in advance) is possible.
Radio part
•
•
•
•
•
Auto up/down tuning.
Manual up/down tuning.
Last channel memories are available for each LW/MW/FM band.
Six (6) preset station memories for MW/FM band.
Built-in PLL swallow counter and controller.
Common features
• FIP (Fluorescent Indicator Panel) direct drive capability. (Segment only)
• 28 Pin slim plastic DIP.
• A single power supply of 5 V±lO %.
PACKAGE DIMENSIONS
in millimeters (inches)
e~::-~:~3
I
35.15 MAX.
(1.38 MAX.)
.1
254(0.1)
33.02(1.3)
649
jlPD1703C-020
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VOO
-0.3 to +6.0
Input Voltage
V,
-0.3 to VOO
Output Voltage
Vo
-0.3 to VOO
Output Breakdown Voltage *
VBOS
-35
Output Current
IOH
-10
Storage Temperature
Tstg
-55 to +125
Operating Temperature
Topt
-35 to +75
* : Segment Output Terminals (P-ch open drain)
ELECTRICAL CHARACTERISTICS (Ta=-35 to +75 °C, V00=4.5 to 5.5 V)
CHARACTERISTIC
High. Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
High Level Input Current
Frequency Response
650
SYMBOL
MIN.
TYP.
MAX.
UNIT
TEST CONOITIONS
V,Hl
0.8 VOO
VOO
V
SO terminal
V,H2
0.7 VOO
VOO
V
CE terminal
V,H3
0.6 VOO
VOO
V
KO to K3 terminals
V,L1
0
0. 3V OO
V
CE terminal
V,L2
0
0. 2V OO
V
SO, KO to K3 terminals
VOHl
4.0
V
EO, 0, MUTE: IOH=-0.5 mA
VOH2
3.0
V
SEG: IOH=-0.5 mA
VOH3
4.0
V
PSC: IOH=-0.2 mA
VOLl
0.5
V
EO: IOL =0.5 mA
VOL2
0.5
V
0, MUTE, PSC: IOL =0.2 mA
100
J.lA
K: VI=VOO=5.0 V
25
IIH
5.0
finl
0.5
2.5
MHz
AM: vi=1.0Vp-p, OC cut sine wave
fin2
0.5
8.8
MHz
FM: vi=0.8 Vp-p, OC cut square wave
0.5
s
VOO: 0-4.5 V
J.lA
CE: Low Level
J.lA
SEG: VOS=-30 V
Supply Voltage Rise Time
Tr
Supply Current
100
Output Off Leak Current
IOFF
500
-5.0
,uPD1703C-020
PIN CONNECTION (Top View)
GNO
FM
KO
Kl
K3
b
c
51
02
a
d
e
/JPO 1703C-020
EOl
E02
CE
PSC
Xl
X2
SO
MUTE
05
VOO
EXPLANATION OF INPUT AND OUTPUT TERMINALS
E01
E02
These three-state outputs are used (via active filters) to supply analog voltages to the tuner
varicap for controlling the local oscillators.
CE
This input is used to designate the stand-by mode to the chip. It is low to designate the stand-by
mode. (display: off, PLL: disabled)
PSC
This output is used to control the divison ratio of the FM two-modulus prescaler (MPB553AC).
X1, X2
SO
MUTE
0" to 05
These inputs are for connection to a 4.5 MHz crystal.
This input is used to control the automatic station searching operation. It is high to indicate the
presence of a station.
This output line is high to mute the radio in the case of station change, bnad change, and so on.
These outputs are used as digit drivers for the display. (Active low)
VOO
This is a 4.5 to 5.5 volt supply for the chip.
a to g
These outputs are used as segment drivers for the display. They are also uses as vertical drive
for the control key and mode switch matrix. (P-ch open drain, Active high)
KO to K3
FM
These inputs are from seven by four matrix. Various functions are entered through the matrix.
This is the FM band local oscillator input. The frequency is divided by 16/17 using a twomodulus prescaler (IlPB553AC).
GND
System ground.
AM
This is the AM band local oscillator input.
651
,uPD1703C-020
DISPLAY
DISPLAY FORMAT
FREQUENCY DISPLAY
MW, LW
, J,- -'- L',-,
MW(LW)
(ME)
I
FM
_I
KHz
FM
(ME)
1/
--
-'-'
'- _I.L
LI
MHz
CLOCK DISPLAY
STANDARD TIME
TIMER
TIMER
Ie ·/111
/
Note:
652
- /-"11
--
ME flag is indicated the conditions enable to preset for the memory.
( ) marks are indicated the conditions provided to display functions, but be not lit for the lamps.
,uPD1703C-020
CONTROL KEY AND MODE SWITCH MATRIX
~
OUTPUT
K3
a
MUP
HAD
b
M1
c
ASKUP
d
TIM
e
CLOCK
f
DIMMER
9
IFO
K2
0
0
0
0
0
0
D.
MOW
MAD
M2
ASKDW
FRO
AM/FM
CNDI
IF1
KO
K1
0
0
M5
0
0
M3
0
ME
SET
0
LOCK
D.
SNZ
0
LW/MW
0
CSS
0
CNT
0
M4
0
SLI
0
M6
USA/JAP
D.
PRO
o
o
0
0
momentary k.ey
alternate switch
D. diode switch
(initial set)
0
0
0
d
EUR/JAP D.
KEY MATRIX CONNECTIONS AND SWITCH TYPES
Key input
Segment output
KO- K3
'~r
momentary key
J
-L-L-a-g
X<
segment output
KO- K3
only for ME k e y : - L i
SET
a- 9
-$-
KO-K3
alternate switch
--4a-g
4a-g
KO- K3
--,~--+~-~~-~~----------g
T1
diode switch
(initial set)
KO- K3
K3
K2
K1
Key input
KO
r
~
open
a-g
653
,uPD1703C-020
DESCRIPTION OF KEY MATRIX
Initialization Diode Matrix
Initialization Diode Matrix is available in 2 types as shown below. These matrixes are read in when power is
initially supplied to VDD (initialize) and when CE terminal is changed from low level to high level.
These initializations will be performed by shorting or opening the intersecting points on the matrix by
Diode. (In the following table, "1" means shorting by Diode and "0" means opening.)
(1) Switches for specifying IF offset of FM
IF1, IFO
IF offset can be varied in 4 levels, as shown below, by 25 kHz step without changing indicated frequency:
IFl
IFO
U.S.A. Band
European Band
Japanese Band
0
0
10.700 MHz
10.700 MHz
10.700 MHz
0
1
10.725
10.725
10.675
1
0
10.650
10.650
10.750
1
1
10.675
10.675
10.725
Note: I F offset frequency of LW/MW is 450 kHz only.
(2) Switches for specifying band regions (U.S.A., Europe, Japan)
USA/JAP, EU R/JAP
USA/JAP
EUR/JAP
OFF
OFF
OFF
ON
ON
OFF
ON
Band
Area
JAPAN
EUROPE
FM
76.1-89.9 MHz
100 kHz
MW
531 -1602 kHz
9 kHz
FM
87.5-108.0 MHz
50 kHz
MW
531-1602 kHz
9 kHz
LW
155-290 kHz
9 kHz
FM
87.9-107.9 MHz
MW
530-1620 kHz
U.S.A.
ON
Channel Space
100 kHz
10 kHz
Prohibited *
* Both USA/JAP and EUR/JAP must not be ON (1). If both are ON, the band area will not be
properly set.
o Mode change over switch (Alternate Switch)
These switches are always changeable .
•
Clock
The radio control function is stopped and radio control key input is rejected.
At the frequency display, clock is returned to the standard clock display.
ON ............... Only operated for clock function. PLL function is stopped and current consumption
becomes low.
Muting signal (active high) is switched ON.
OF F ............. Radio control is enabled.
654
jlPD1703C-020
When the clock switch is changed over from ON to OFF, (at the radio control function restarted) the
condition becomes to the frequency display at automatically and muting signal is switched OFF after
approximately 500 ms.
•
AM/FM, LW /MW
Switches for sellecting the band (LW, MW, FM)
AM/FM
LW/MW
Band
OFF
OFF
FM
ON
OFF
MW
ON
ON
LW
At transferred, the muting signal for approximately 500 ms. is outputed and at the same time frequency
display is indicated.
•
DIMER (Dimmer)
By switching ON with dimmer switch, the brightness transfers to approximately 1/10.
ON .............. Dark
OFF ............
•
Bright
CNDI (Control Disable)
If control timer is not requried and the switch is turned ON, in spite of maching with the control timer
setting value to standard clock value, no control output is delivered.
ON ............... Control timer function is not operated.
OFF ............. Normal operation.
•
LOCK
Without regard to that at the recording time and like the receiving channel have varied or the control
output have cut by accident, in the event of this switch is being turned on, inputs of the channel
exchange switch and the control switch for control output may be prohibited.
ON .............. Each key MUP, MOW, M1-M6, ASKUP, ASKDW, SLI, CSS, and SNZ is rejected.
OF F ............ Normal condition.
•
PRO (Program)
This is the interrupting receiving switch. When the switch is maintained "ON", maching with the
control timer setting value to the standard clock time, the radio receiving channel can be changed to
the channel preset to memory 1 (correspond to M 1) of the receiving band. (AM or FM)
Also, at the radio is turned on by the control function, the channel corresponded to M 1 can be received
automatically. (no relation to last channel)
However, if LOCK switch is being turned on, these functions can not be operated even if PRO switch
is turned on.
a Momentary Switch
•
MUP/HAD (Channel Manual Up/Hour Advance)
MUP/HAD switch is used for manual up of the receiving channel and setting of "o'clock" on the
standard clock and control timer.
Ma.nual up of the receiving channel is performed with MUP/HAD switch after changing to frequency
display by means of FRQ switch is turned once on.
At the same time, if MUP/HAD switch is one time switched on, the channel is advanced only one step.
If MUP/HAD switch is kept "ON", the channel is automatically stepped up at intervals of approximately
45 ms. When the LOCK switch is being switched on, adjustment of channel is impossible.
(during
a station seek up, muting signal is outputed.)
Adjustment of the "o'clock" on the standard clock is performed by MUP/HAD key, keeping ME/SET
655
pPD1703C-020
key switch "ON" condition at the standard clock display. In this condition, when MUP/HAD switch
is one time switched "ON", the time will be advanced at one hour. Also, when MUP/HAD switch is kept
"ON", the time will be advanced at an interval of one hour per approximately 250 ms.
Before the setting of the control timer, one time the ALM Key is switched on as a result the control
timer display is indicated, then the setting is performed with the same manner on "o'c1ock" adjustment
of the standard clock, However, ME/SET Key is not required as "ON".
•
MDW/HAD (Channel Manual Down/Minute Advance)
The switch is used for the manual down of receiving channel and settings of "Minute" on the standard
clock and control timer.
Adjustment menas is the same manner as the switch MUP/HAD, however, in case the standard clock,
every adjusted by MDW/MAD key, "second" is reset. (00 second)
o M1""" M6 (Memory 1 - Memory 6)
These keys switches is used for call and write of the preset memory on each AM and FM six stations
corresponded to M1"""M6 Key.
When any key of M 1""" M6 is switched on, the call of the preset memory can be performed to call the
station preset in the memory corresponded to the specified key.
Before the write of preset memory, at the frequency display condition, ME/SET switch is tunred on,
and becomes the state of the write prepared. (M E lamp is lit.)
Then, by menas of some one of these keys M 1'" M6 is switched on, the write can be perfomred the
channel indicated in the memory corresponded to the specified key.
At the same time, ME lamp is not lit and it indicates to write in the memory.
•
ASKUP (Auto Seak Up)
ASKUP switch is used for automatic seek up for a station. (up direction)
When the key switch is turned on, it becomes the frequency display is automatically and ups the
channel at intervals of approximately 10 ms.
In case a radiocasting catched, the channel up is stopped, as a result the radiocasting is received.
o ASi
I"t'\r t"\r 1-\1"t"\
I~
a
t'\~
~
b
rr..~ t'\~ r..r t'\ ~
\,1-/\ 1-1, V' 1/ ....
rr..r r..~ r..r t'\ ~
d
V
"rt'\r, V' V"
t"\r t'\
+
>
'V'
....
V' V' 1/ ....
c
+
~
..
~~
...
r-f
~
-.
?
1:1
~
~
TIMER
CONTROL
COLON
MW
FM
ME
9
50 kHz
L~
... ~ ... ~
~
0-
{J27 J
II
....,
"
...
<;t
X
0.01 J.lF
fro nAM VCO
~
I-I
f
r i-I ri-l
1.1-1
1"':'11'" M r h rh
I- U L 1-1
LJ I- ~ L f"
-
I-I
I-I
e
~~
..::~ I'" i-I
~~
I I
I-I
I-I
LW
\,1-/\ V' V\, 1/ ....
x4 ~ ..
I
05
04
03
02
01
~-
?~ ,in I~
22 21 20 19 18 17 16 15
25 24
AM GNO FM KO K1 K2 K3 Sa Sb Sc Sd Se Sf Sg
16 5
PSC out
~~ 1SS53
j,lP01703C-020
J.lPB553AC
VCC IN CHK GNO
39,
q2
+5V
n
1
0.01 J.lF I
E01E02 CE PSCX1 X2 SOMUTE 01020304 05 V OO
4 5 U1 6 7 8 9 10 11 12 13 14
1 2 3
~ 47
c:
from FM VCO
)
~
I
0.01 J.lF
2.2 J.l
-
2.2 J.lF
>
> 0.033 J.lF
~
H
m
U1
to
~~
.:¥.
.:¥.
.:¥.
r--
r--
r--
<;t
<;t
+5 V
<;t
V'
.:¥.
.,
r--
<;t
••.1
lZ~
"
"
f'..
.......
~
-C
.......
.,1'..
r,
C
...a
3.3 kSl
t-----J
J "
47 kn
c:
1SS53x2
"'1
4.7 kSl
2SC945x2
or 2SC1280
"-J
>
100 knx5
A
4.7 kn
2SC945x2
or 2SC1280
+5 .7 V
....,
"
3.3 kn
AI<
lOkSl
"
vv
.:¥.
r--
<;t
I.?-
77
>----
-'"
to F MVCO
~~~
HI
HU~
JJF
1122
pF
<;t
10 k
to A vi VCO
kn
0.01
~~
c: c: c: c:
-25 V
4
L--{
MUTE output )
<
{CONTROL output
c:
~. >
0
~
7f7
SO input
~Z +
77
o
W
("')
I
o
N
o
MOS DIGITAL INTEGRATED CIRCUIT
f1PD1704C-011
PLL FREQUENCY SYNTHESIZER AND CONTROLLER
FOR AMjFM TUNER
The pPD 1704C-011 is a single chip AM and FM band PLL frequency synthesizer plus controller for the U.S.A.,
Europe and Japan with a 24-Hour clock and three source-programmable timers. By using pPD1987C (remote
control transmitter) and pPD1937C (remote control receiver) as peripherals, the pPD1704C-011 can be remotecontrolled through infrared ray.
Since the pPD1704C-011 employing pulse-swallowing method in FM band tuning by using pPB553AC
prescaler, the reference frequency of FM is as high as 25 kHz. Therefore, the pPD1704C-011 can constitute
a multifunctional high performance AM/FM digital tuning system for home stereos and receivers.
The pPD1704C-011 is fablicated with advanced CMOS process and is packaged in 42-pin DIP.
FEATURES
•
Single chip PLL + Controller
•
Single power supply; +5 V±1 0 %
•
Compatible with AM and FM band receivers for the U.S.A., Europe and Japan
•
FM reference frequency is as high as 25 kHz (the pulse swallowing method is employed)
•
Built-in 24 hour clock
•
Built-in three sets of source programmable timers. (ONCE, EVERYDAY 1 and 2)
•
Sixteen preset channel memories (8 for AM and 8 for FM)
•
Two last channel memories; AM(1) + FM(1)
•
Auto up/down seek tuning (Saw-tooth mode)
•
Manual up/down tuning (Saw-tooth mode)
•
Auto preset channel scanning (Holding 5 sec for each preset)
•
Compatible with remote control system of pPD1986C and pPD1937C
.. Source selector function (PHONO, TAPE, AUX)
660
•
FM intermediate frequency compensating capability (4 ways by 25 kHz step)
•
Wide variety of function selectability by diode matrix; FM ONLY, NO CLOCK etc.
•
F IP (Fluorescent Indicator Panel) direct drive capability. (Segment lines only)
•
5-digit frequency display
•
10-key clock adjusting
•
Low-power battery back up capability (~10pA : only in No CLOCK mode).
•
42-pin DIP package
,uPD1704C-011
PACKAGE DIMENSIONS
in millimeters
50.0 MAX.
~---------------
1 234
567
89101112131415161718192021
~~
I.
--tt50.8
o.k~ I
N
Note: Typical values are shown unless other use specified.
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage
VOD
-0.3 to +6.0
V
Input Voltage
VI
-0.3 to +VOD
V
Output Voltage
Vo
-0.3 to +VOO
V
Output Absorbing Current
10
10
Operation Temperature
Topt
-35 to +75
Storage Temperature
Tstg
-55 to +125
Output Breakdown Voltage
VBOS
mA
°c
°c
-35 across Sa - Sg terminals
(drain-source voltage)
V
RECOMMENDED OPERATION CONDITIONS
CONOITIONS
SYMBOL
MIN.
TYP.
MAX.
Power Supply Voltage
VOO
4.5
5.0
5.5
V
Oata (RAM) Retention Voltage
VRAM
2.5
5.5
V
Oscillation Stop Voltage
VOSS
3.8
V
Output Breakdown Voltage
VBOS
-30
V
IOH=-5 pA Across Sa-Sg
Terminals (Drain-Source
Voltage)
Rise Time of Power Supply Voltage
Trise
500
ms
VOO=0-4.5 V
CHARACTERISTIC
3.2
UNIT
CE=O, CKSTP Instruction
Executed
661
,uPD1704C-011
ELECTRICAL CHARACTERISTICS (V00=4.5 to 5.5 V, Ta=-35 to +75 °C)
CHARACTER ISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
CONDITIONS
High-Level Input Voltage
VIHl
0.8 VDD
VDD
V
SD, RMC Terminals
"
VIH2
0.7 VDD
VDD
V
I/O Ports, CE Terminal
(Note)
"
VIH3
0.6 VDD
VDD
V
KO to K3 Terminal
Low-Level Input Voltage
VILl
0
0.3VDD
V
I/O Ports, CE Terminal
"
VIL2
0
0.2 VDD
V
KO to K3, SD, RMC
Terminals
High-Level Output Voltage
VOHl
4.0
V
E01, E02 Terminals
IOH=-0.3 rnA
"
VOH2
4.0
V
51 to 56, MUTE, I/O
Ports IOH=-0.2 rnA
"
VOH3
4.0
V
PSC Terminal
10H=-0.1 rnA
"
VOH4
3.0
V
Sa to Sg Terminals.
IOH=-0.5 rnA
Low-Level Output Voltage
VOLl
0.5
V
EO" E02 Terminals,
I/O Ports. 10L=0.5 mA
"
VOL2
0.5
V
01 to 06, MUTE, PSC
Terminals 10L=0.2 mA
High-Level Input Current
+IIH2
100
p.A
KO to K3 Terminals
VIN=VOD=5.5 V
"
+IIH2
p.A
X 1 Terminal (during pull
down) VIN=VDD=5.0 V
p.A
AM, FM Terminals (during pull up) VIN=O,VDD
=5.0 V
1
p.A
EO" E02 Terminals, Ta
=25 o C
2.5
MHz
AM Terminal, Vin=1.0
Vp-p (Mim.), Dc Cut
10
40
300
Low-Level Input Current
-IILl
300
Output Leakage Current
IL
10-3
Response Frequency
fAM
0.5
fFM
3
mA
FM Terminal, Vin=0.8
V p_p (Mim.), Rectangular
wave, Dc Cut
Operation Current
IDDl
3
mA
Input/Output Currents
from Input/Output Terminals Excluded
Data (RAM) Retention Current
IDD2
10
Clock Operation Current
IDD3
600
"
10
p.A
CE=O, CKSTP instruction
executed, Ta=25 °c, VDD
=5.0 V
p.A
CE=O V D D=5.0 V
Note: I/O ports include AC OUT, FM/AM, selection terminals (AUX, TAPE, PHONO, TUNER) A to D, DP,
and COLON.
662
,uPD1704C-011
FUNCTIONAL OUTLINE
Receiving frequency range, channel spacing, reference frequency, and intermediate frequency.
Frequency Range
U.S.A.
Europe
Japan
AM
530-1620 kHz
FM
87.9-107.9 MHz
AM
522-1611 kHz
FM
87.50-108.00 MHz
AM
FM
Channel
Spacing
Reference
Frequency
Intermediate Frequency
10 kHz
10 kHz
450 kHz
200 kHz
25 kHz
10.650, 10.675, 10.700, 10.725 MHz
9 kHz
9 kHz
50 kHz
25 kHz
522-1611 kHz
9 kHz
9 kHz
76.1-89.9 MHz
100 kHz
25 kHz
450 kHz
10.650, 10.675, 10.700, 10.725 MHz
450 kHz
10.675, 10.700, 10.725, 10.750 MHz
Channel Selection
(1) Auto tuning (saw-tooth wave mode)
Auto up-channel tuning
. . . . . . . Channel once received is held.
Auto down-channel tuning
(2) Manual tuning (saw-tooth wave mode)
Manual up-channel tuning
. . . . . . Stepwise action through momentary switch. When held depressed
Manual down-channel tuning
for 0.5 second or more, fast action continued until the switch is released.
(3) Preset scan . . . . . . . . . . . . . . . . . . . . Preset channels from 1 CH. to 8CH. are repeatedly scanned with
holding for 5 seconds at each channel. To stop scanning at the
currently received station, press the preset station key currently
selected.
(4) Recall preset memory . . . . . . . . . . . . . 8 channels each for AM and FM through 8 button switches.
Timer
(1) EVERYDAY (for two systems) . . . . . . . By setting both ON and OFF time with a source, the specified
source is switched ON at the ON-time and the whole system is
switched OFF at the OFF-time. These action will be repeatedly
performed everyday.
(2) ONCE (for one system) . . . . . . . . . . . . By setting both ON and OFF-time with a source, the specified
source is switched ON at the ON-time, and the whole system is
switched OFF at the OFF-time.
In this case, the timer action is performed only once. And
after the action, the ONCE-Timer data are cleared.
663
,uPD1704C-011
Remote Control
By attaching IlPD1986C (transmitter) and IlPD1937C (receiver), functions including power ON/OFF, AM/FM
switching, preset channel call, and source selection can be remote controlled by infrared ray.
TERMINAL CONFIGURATION (Top View)
TUNER
PHONO
TAPE
AUX
FM/AM
AM
RMC
PSC
FM
SD
CE
E02
Vss(GND)
EO,
DESCRIPTION OF TERMINALS
664
Terminal
Number
Symbol
Terminal
Name
1-7
Sa-Sg
Segment
Outputs
Terminals for display segment signals and for key return signal source;
active high. (Fordetails,see 1. KEY MATRIX CONFIGURATION.) These
terminals are open-drain outputs and it is provided with dielectric strength
of -30 V max. So it can be directly connected to segment terminals of FIP
(fluorescent indicator panel) with pull-down resistances. (For the connections, see 3-1. Display Connection Diagram)
8-11
KO-K3
Key Return
Signal
Inputs
Input terminals for key return signals from externally connected key
matrix. As the key return signal sources, segment terminals Sa-Sg and
AND signal. of TUNER and PHONO terminals are used. (See 1. KEY
MATRIX CONFIGURATION.)
12-17
51-06
Digit
Outputs
Display digit signal outputs; active low. To interface to a F IP (fluorescent
indicator panel), single stage buffers using PNP transistors (2SA733 or
equivalent) should be inserted between them. (For details, see 3-1.
Display Connection Diagram.)
Description
jlPD1704C-011
18
MUTE
mute
Muting signal output to cancel shock noises when PLL is momentarily
unlocked; active high.
This line goes high before 55 ms to PLL data (content of programmable
counter) changes, anQ it goes low after 55 ms from the completion of the
data change.
Mute signal is issued while in either" of the following cases.
o AM/FM and selector switchings
o MANUAL UP/DOWN
o AUTO UP/DOWN
o Preset memory call (including preset scan)
o Switching from CLOCK set to RADIO.
KE::" YIN
~
-
::
55 ms
i' I ii
55 ms
I
_ _ _ _ _ __
LpLL data processing time (10 ms max.)
The signal is continuously issued in either of the following cases.
o OFF key is depressed. (OFF mode)
o When the following mode is set through MODE SW; TIMER READ,
TIMER WRITE, TIMER CANCEL
o CE terminal is forced low.
19
20
Xl
X2
X'tal
Terminal to which crystal oscillator is connected. The oscillation frequency of the crystal should be 4.5 MHz. (Type TQC-231A-8S manufactured by Toyo Tsushinki is recommended.)
21
VOD
Power
Supply
Terminal for power supply to the device. (5 V±10 %.) The voltage can
be lowered to 2.5 V in data retention mode. (When device CLOCK is
stopped, i,e, when NONCLOCK is specified through the diode matrix and
CE=O). The rise time of VDD should be 500 ms or less (for 0 ~ 4.5 V).
If the rise time is excessively long, the initialization will not operate
ploperly.
Error Out
Output terminals of charge pump in the phase detector of PLL section
(3-state).Comparing the reference frequency with the oscillation frequency
divided by the programmable divider, these terminals go high if the
divided oscillation frequency is higher than the reference frequency.
And go low if it is lower than the reference frequency. If they are the
same, these outputs becomes high-impedance. Since EOl and E02 output
the same signal at the same time, either of them can be connected to the
LPF (low pass filter) of either AM or FM.
22
24
23
GND
Ground
Terminal to be connected to system ground.
25
CE
Chip Enable
Terminal for input selection signal to device. The terminal voltage has to
be high level to operate the device normally and low level to leave the
device id Ie.
(1) When NONCLOCK is set through the initial setting diode matrix.
CE = High ..... normal operation.
CE = Low ..... display OFF, PLL operation stopped, internal
clock generator stopped; current consumption 10
IlA or less, VDD = 5 V.
(2) When NONCLOCK is not set through the initial setting diode matrix.
CE = High ......normal operation
CE = Low ..... display OFF, PLL operation stopped; current
consumption 500 IlA typical, VDD = 5 V.
665
jLPD1704C-011
High level or low level for 134 J,lS or shorter cannot be accepted. When
NONCLOCK is selected through the initial setting switch, CE terminal
should be forced to high level after the rise up of VDD, and forced to low
level 200 ms before VDD falls. (See Note 1.)
666
26
SO
Station
Detector
Input terminal of station detection for auto tuning (AUTO UP/DOWN).
The auto tuning is stopped on receiving high level. To avoid missing
the station, this input should be forced to high level within 50 ms after
PLL is locked.
27
FM
FM Local
Oscillator
Signal
Inputs
Input terminal of FM programmable counter.
This terminal is normally connected to the output of the two-modulus
prescaler J,lPB553AC.
Since an ac amplifier is employed inside, the input signal should be fed
through a dc-cut capacitor.
28
PSC
Pulse
Swallow
Control
Terminal for output signal to switch frequency dividing ratio of prescaler
when pulse swallowing method is used in frequency dividing (i.e. for FM
signal reception). Connect to PSC terminal of special prescaler J,lPB553AC.
The frequency dividing ratios of J,lPB553AC are 1/16 and 1/17.
29
RCM
Remote
Control
Inputs
Input terminal of remote control signal.
Connect to CHU OUT terminal of receiving remote control ICJ,lPD1937C.
The remote control action is discriminated by the number or input
pulses to this terminal. (For details, see 2-4. Transistor Switch)
30
AM
AM Local
Oscillator
Signal
Inputs
Input terminal of AM programmable counter.
It accepts the output signal (VCO) from AM local oscillator. Since an ac
amplifier is employed inside, the input signal should be fed through a dccut capaCitor.
31
ACOUT
AC Outlet
Control
Terminal for AC service outlet control.
This terminal is used to control the cut-out relay for the main power
supply of the receiver set. This goes high level whenever either one of the
source selector terminals (TUNER, PHONO, TAPE, and AUX) is to be
turned on.
When the OFF key is pressed, it becomes low level. Since this terminal
becomes high impedance when the CE terminal is shifted to low level
under the NONCLOCK conditions, a pull-down resistor should be used if
NONCLOCK specification is required. (See Note 3.)
32
FM/AM
FM/AM
Power
Supply
Control
Terminal for switching power supply to tuner's FM or AM section. High
level output is issued to operate FM and low level output to operate AM.
This is also used in conjunction with the TUNER terminal to issue an
ACKNOWLEDGE signal of AM and FM source selection in TIMER READ
and TIMER WRITE modes.
The schematic of the ACKNOWLEDGE signal generator is as follows.
J,lPD1704C-011
When FM or AM key is depressed in TIMER WRITE mode with the circuit
shown above, the LED corresponding to the specified band will be turned
on for 50 ms.
In TIMER READ mode, the LED, corresponding to the band set in
WRITE mode, will be turned on for 5 seconds.
33
34
35
36
AUX
TAPE
PHONO
TUNER
Source
Selector
Outputs
Source selector outputs for TUNER, PHONO, TAPE, and AUX. TUNER
terminal goes to high level when FM, AM, or preset key is depressed, and
PHONO, TAPE, and AUX terminals goes to high level when PHONO, TAPE,
and AUX keys are depressed, respectively.
When OFF key is depressed, all terminals are forced to low level. (See
Note 3.)
'.I/-40
A
B
C
D
Preset
Station
Indicator
Outputs
Output terminals of BCD signals to indicate the preset channel memorys.
The output combinations for preset stations are shown in the table below.
PRESET STATION
NON PRESET
P1
P2
P3
P4
P5
P6
P7
P8
D C B A
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 1
1 0
1
1
1
1
0 0
0 1
1 0
1: High level Output
0: Low Level Output
1 1
1 1
1 0 0 0
By connecting llPB74LS42 (BCD-to-decimal decoder) to these terminals,
the dot pattern display of preset station can be made with LEDs. (See
Note 3.)
41
42
COLON
Decimal
Point
Terminal to output a decimal point indication signal to the display for
FM frequency; active low.
DP as well as COLON terminals cannot be directly connected to fluorescent
indicator panel. Insert a buffer for the purpose. (See Note 3.)
COLON
Terminal to output a colon indication signal in CLOCK display mode;
active low. (See the discription of DP terminal above.)
667
,uPD1704C-011
(Note 1)
When no clock function is necessary, turn the NONCLOCK switch ON. And if, in this mode of
operation, low-power-data-retention is required while radio is off, do not use OFF key, which will be
described later, to turn system power supply off, but use CE terminal. The example circuit is shown
below.
IIII~
vDD
+
~
ON
CE
(+5 V±10 %)+VF
fFF
The value of CR connected to CE terminal should be set so that the following condition is satisfied.
------------------------------
---~5V
VDD---~
-+---+---500 ms MAX.
0.3 VDD
CE-----+--+----1--0 J.,tS MIN.
(Note 2)
----<~---+__-130
ms MI N.
If NONCLOCK is not specified, CE terminal should be connected to VDD as shown below.
VDD 1 - - -.......- . - - - - - +5 V±10 %
CE
1----...----'
+
22:
77
(Note
668
3f
AC OUT, A, 8, C, 0, AUX, TAPE, PHONO, TUNER, and DP terminals are shifted to low level or high
impedance status dependent on the internal conditions when CE terminal is changed to low level
under the NONCLOCK (refer to 2. Description of Key Matrix) conditions.
tlPD1704C-011
1. KEY MATRIX CONFIGURATION
1-1. Key Matrix Configuration
K3(11 )
K2(10)
Sa(l )
O(AM)
Sb(2)
4 (EVERYDAY2)
5
OFF
Sc(3)
(1
8
EVERYDAY1)
(2
ON
(O~~E
)
9 (FM)
EVERYDAY1) 3
OFF
(EVERb~AY2)
6 ( ONCE)
OFF
7
REMCON*
CLK CALL
CH SCAN
DOWN
UP
Se(S)
MEMORY
PHONO
TAPE
AUX
AUTO/MANUAL
S9(7)
IFO
TUNER
& PHONO
MODSW2
(note)
IFl
MODSWl
(note)
BANDl
Momentary
(Normally OFF)
OFF
Sci(4)
Sf(6)
Type of Key
KO(8)
Kl (9)
MODSWQ
(note)
* Transistor Switch
MODSW .•• Rotary Switch AUTO
/MANUAL .. ; Alternate Switch
BANDa
Initially Set Diode Matrix
NONCLOCK
FM ONLY
(Note) Rotary switch to be used as mode switch should be of shorting type.
1-2. Connection of Keys and Switch Types on Key Matrix
PHONO TUNER
VDD--------~~--~--~~------~--------------------------~
669
tlPD1704C-011
Key Input
---+-+-1---- Momentary Switch
- - -.......---+---- Segment Output
Segment Output
----&~:t---
Transistor Switch
Remote
Control n..._-""\J\_'"
Signal
Input
Key Input
Key Input
----1r+-f--- Alternate Switch
--4~---f--""'-
Segment Output
K2
t /__
QJ o{ ~
/Shortin g Type
-"""~~M'7W'~~'t'-7,*-
L_.1
Rotary Switch
~
-
-~
.,,:...~.....,
Segment Output Sf
Ko
KJ
Key Input
---"""~r----Diode
Matrix
Open
--4~---f-_
Segment Output
or
670
,uPD1704C-011
2. DESCRIPTION OF KEY MATRIX
2-1. Initial Setting Diode Matrix
There are four types of initial setting matrices as described below. They are read in when VDD is first fed with
power (initializing) or when CE terminal is forced to high level from low level.
(1) Switches for setting IF offset value of FM.
IF1,IFO
(2) Switches to specify the BAND range for the target area. (American, European, or Japanese)
BAND1, BANDO
(3) Switch to kill the clock function.
NONCLOCK
(4) Switch to meet the FM single receiver.
FM ONLY
These settings are done by shorting with a diode or by opening the crosspoint on key matrix. (In the following
table, ON means short~circuiting with a diode and OFF means opening.)
Symbol
IFl
IFO
BAND1
BANDO
Functional Description
Switches to set IF offset value of FM.
Intermediate frequency can be set in for ways, 25 kHz apart from each other, without changing
the frequency displayed.
IFl
IFO
American band
European band
Japanese band
OFF
OFF
10.700 MHz
10.700 MHz
10.700 MHz
OFF
ON
10.725
10.725
10.675
ON
OFF
10.650
10.650
10.750
ON
ON
10.675
10.675
10.725
Switches to specify the BAND range for the target area.
Either American, European, or Japanese band can be selected.
BAND1
BANDO
OFF
OFF
American band
OFF
ON
Japanese band
ON
OFF
European band
ON
ON
Prohibited *
Found Area
* Do not turn both BAND1 and BANDO ON. If both are turned ON, receiving band cannot be set
duly.
NONCLOCK Switch to kill the clock function.
When no clock function is required, make this switch ON.
Then, data retantion is capable with a low current consumption (10 pA or less).
(Refer to Notes 1 and 2 of Terminal Descriptions.)
ON .......... With Clock Function
OFF "......... With Clock Function
FM ONLY
Switch to set receiving band to FM only.
When this switch is ON, AM band is not received even if 'O(AM)' key is pressed. Then band
switching keys 'FM' and' AM' can be accepted only as '9' and '0' for time adjustment.
ON .......... FM only
OFF ......... FM and AM
671
,uPD1704C-011
2-2. Alternate Switches
There are two kinds of alternate switches. They can be switched any time.
(1) Switch to select auto tuning or manual tuning.
AUTO/MANUAL
(2) Programmable mode switches to specify operation modes; CLOCK SET, TIMER WRITE, TIMER CANCEL,etc.
MODSW2, MODSW1, MODSWO
Symbol
AUTO/
MANUAL
Description of Function
Switch to select auto tuning or manual tuning.
ON .......... Auto Tuning
OFF ......... Manual Tuning
Auto or manual tuning starts when the momentary switch of UP or Down is pressed after the
setting of this switch.
In the auto tuning operation, the frequency is scanned step by step after confirming that the PLL
system is locked. Therefore, in the long lock-up time P LL system, the scanning speed will be
slower than the short one. And if the PLL feedback loop is malfunctioned and the PLL is never
locked, the scanning will not be started or be stopped.
Programmable mode switches to specify modes such as CLOCK SET, TIMER WRITE, TIMER
CANCEL.
Use shorting-type rotary switch with two circuits and six positions for these switches. (For connections, see 1-2 "Connection of Keys and Switch Types for Key MatriX".)
MODSW2
MODSW1
MODSWO
Programmable Mode
1
0
1
CLOCK SET
1
0
0
RADIO
1
1
0
TIMER OPERATION
0
1
0
TIMER READ
0
0
0
TIMER WRITE
0
0
1
TIMER CANCEL
(Note)
MODSW2
MODSW1
MODSWO
1 and 0 in the table means ON (short) and OFF (open) respectively. Since the mode
switch code is modified gray code, the sequence of the codes cannot be changed to others
than the above.
1. CLOCK SET mode
Mode to set present time.
tLPD1704C-011 is provided with a 24-hour clock system (0:00-23:59), The time can be set
by the following procedure.
Q) Set time in 4-digit input using ten-key 0-9.
(Ex. Setting to 8:15 A.M,)
"0,,1 Ll
I -- "8,,1''-' '-' .
I '-' •
I. -- "'''1. '-'i , L''_I ••
I
I
I-- "5"1"'-' '-'0 .· '-''-I
.
I
(Note) If some wrong key was pressed, finish the 4-digit keying and then start keying
again from the first digit.
@ Turn the programmable mode switch to RADIO coincidentally to time signal. The clock
function starts to operate at the moment of switching over to RAD 10,
(Note 1) If clock setting is performed while listening to the radio, radio broadcast
frequency is indicated when the mode switch is returned to RADIO .
. If the similar process is followed in PHONO, TAPE, or AUX mode, the time is
indicated, but zero (0) i"n the most significant digit will be suppressed to blank
as shown below.
672
j.lPD1704C-011
, ,. '-'.
''-I
,:,.
2) At the time when VDD (5 V ±1 0 %) is supplied to the device, "E" is indicated.
1:=
3)
MODSW2
MODSW1
MODSWO
I
When the mode switch is in the position of CLOCK SET mode, the internal
clock stops functioning. The clock starts functioning when the mode switch is
turned to another, and the value of second is set to "0" internally.
2. RAD I0 mode
In this mode, the tuner functions such as write and call of AM/FM preset memory, UP/DOWN
tuning in AUTO/MANUAL, and preset memory scan etc.) and source selection (PHONO, TAPE,
or AUX) can be performed.
3. TIMER OPERATION mode
Mode for executing instructions of time and source (AM, FM, PHONO, TAPE, or AUX)
specified in TIMER WRITE mode.
Each of three timer systems, EVERYDAY1, EVERYDAY2, and ONCE, is respectively
executed (ON or OFF) at the programmed time. Once programmed in ON/OFF-time and
source, EVERYDAY1 and EVERYDAY2, repeat the ON and OFF operation to the
programmed source everyday at the programmed time, while ONCE is automatically erased
after the execution of ON and OFF operation and it will not be executed next day.
Among these three systems, the priority sequence ONCE, EVERYDAY2, EVERYDAY1 is
established. (For details, see 4 Description of Programmable Timer Performance)
When timer is executed, one of the following terminals is to be activated corresponding to the
programmed source.
Programmed Source
Terminals to be activated
FM
FM/AM=High, TUNER=High, AC OUT=High
AM
FM/AM=Low, TUNER=High, AC OUT=High
PHONO
PHONO=High, AC OUT=High
TAPE
TAPE=High, AC OUT=High
AUX
AUX=High, AC OUT=High
If the timer of either one of the systems is ON, all key and remote controlled inputs in this
mode cannot be accepted because of protection against wrong operations. Such a manual input
operation should be done after switching to RADIO mode if desired.
4. TIMER READ mode
Mode to confirm ON/OFF time and source programmed in TIMER WRITE mode. The
procedure is as follows;
Set the programmable mode switch to TIMER READ mode. Then source selector
terminals (TUNER, PHONO, TAPE, and AUX) and AC OUT terminal are forced to low
level, and the present time is indicated.
@ Press ON key of either of EVERYDAY1, EVERYDAY2, or ONCE, Programmed
ON-time, source selector terminal and the preset station are indicated for about 5 seconds.
After that, the present time indication is recovered.
@ Press OFF key of EVERYDAY1, EVERYDAY2, or ONCE. Programmed OFF time is
indicated for about 5 seconds. After that, the present time indication is recovered.
(Note) If ON or OFF time is not programmed, only colon (:) is indicated for about 5
seconds.
CD
5. TIMER WRITE mode
Mode for programming ON and OFF times and source to be operated. Note that OF F-time
must be set whenever the ON-time is to be set. If OFF-time is not set, timer-ON action will
never be performed and the ON-time which was set alone will be erased. This function is
provided to avoid accidents caused by the timer which will never be turned off. Since such a
673
ILPD1704C-011
OF F-time checking is performed when the ON-time is encountered, OFF-time should be set at
least before the ON-time.
In otherwise, if only OFF-time is set, the timer-OFF action will function properly. That is,
OFF-time has a higher priority than the ON-time.
Five sources, AM, FM, PHONO, TAPE, and AUX, are programmable. The programming
procedure is as follows.
Set programmable mode switch to TIMER WRITE mode. Then the present time is
indicated.
@ Press the desired ON-key of EVERYDAY1, EVERYDAY2, or ONCE. Then the colon
is displayed, and a preset station indicater LED corresponding to the depressed ON-key
turns on for about 60 ms.
@ Set time in 4-digit input by using ten-keys 0-9 of momentary switches just similar to the
clock set.
(Ex.) Setting 6:00 p.m.
CD
I
r"o"
. --
J
II '-ILI .• '-, II
I I
r"o"
J
'I
IIII '-'
I_I • I I'
• ,_, '-I
@ Press key corresponding to the desired source (FM, AM, PHONO, TAPE, or AUX).
MODSW2
MODSW1
MODSWO
®
(Even if FM ONLY is specified, you must input FM.)
In cases that PHONO, TAPE, or AUX key is pressed, the corresponding source
selector terminal goes High for about 500 ms.
In cases that FM or AM key is pressed, TUNER terminal goes High and FM/AM
terminal is activated until a preset station key (1-8) is pressed. By using the statuses
of the TUNER and FM/AM terminals, source selection ACKNOWLEGE signal can be
generated (refer to description of AM/FM terminal).
When PHONO, TAPE, or AUX key is pressed, present time will be indicated after
about 500 ms (the source selector terminal goes High level for that 500 ms), whereas the
programmed ON time is indicated until preset station key is pressed when FM or AM key
is pressed.
When FM or AM is selected as a source in (1), the next step to press the desired preset
station key (1-8) is required. Then, preset station indicator LED corresponding to the
pressed key turns on for about 60 ms. After that, the display will be changed from the
programmed ON time to the present time.
(Note) If any wrong time is set or wrong source is selected, switch the programmable mode
switch to another mode, and, restart programming from
or restart programming
from @ after finishing @ or ®.
Press OFF key that corresponds to the ON key pressed in @.
Then, only colon is indicated. The preset station indicator LED corresponding to the
pressed OFF key turns on for about 60 ms.
Set time in 4-digit number by using ten-keys 0-9 of momentary switch.
(Ex.) Setting 8:30 p.m.
CD
@
(j)
1_
r"3" J
1-"L L'.,· _,-'
r"o..1 _II , • _II
1
--
J
'I
I '- LI • _, '-'
When the input of the fourth digit is over, the above display is changed to the present
time indication.
(Note) When any key is wrongly pressed, finish the process up to the fourth digit and
then restart the process from @.
® Set programmable mode switch to TIMER-OPERATION. Then the present time is
indicated.
(Note) If timer operation is desired, be sure to set programmable mode switch to TIMER
OPERATION. Otherwise timer does not function.
6. TIMER CANCEL mode
Mode for canceling programmed times ON/OFF times and source. Follow the process described
below.
674
jLPD1704C-011
CD
o
MODSW2
MODSW1
MODSWO
@
Set programmable mode switch to TIMER CANCEL. Then the present time is indicated.
Press the ON key of timer to be canceled. (EVERYDAY1, EVERYDAY2, or ONCE).
Then colon is indicated momentarily, the programmed ON time and source are canceled,
and, immediately, the present time indication is recovered.
Press OFF key that corresponds to the ON key pressed in procedure
As in
colon is indicated momentarily, the programmed OFF time is canceled, and,
immediately, the present time indication is recovered.
0.
0,
2-3. Momentary Switches
Symbol
Description of Function
These keys are multiple function keys. Their functions varies dependent on the positions of
programmable mode switches (MODSWO,1,2).
(1) In the CLOCK SET mode.
1(EVE~~DAY 1) 2(EVE~:fAY1) 3(EVE~~DAY2) 4(E\lE~~~AY2)
O(AM)
I
0
II
I
7
1
II
8
7
II
8
2
I
9(FM)
I
I
9
I
3
II
4
5(O~~E)
II
5
6(~~E)
II
6
I
I
When CLOCK SET mode is selected, the keys are used as ten-keys for setting time.
(2) In the RADIO mode
O(AM)
I
AM
I
7
I
7
l(EVERYDAYll 2(EVERYDAY1) 3(EVE~~DAY2) 4 (EVE~~~AY2)
ON
I
OFF
4
1
2
3
I
II
8
8
II
II
9(FM)
FM
II
II
II
6(OtF~E)
5(O~~E)
5
II
6
I
I
When RADIO mode is selected, the keys are used for AM/FM band switching and as preset
stati on keys.
(3) In the TIMER OPERATION mode.
1(EVERci~AY 1) 2(EVE~WAY 1) 3 (EVEROYJAY2) 4(EVE~~fAY2)
O(AM)
0-9
I
AM
7
I
7
II
II
1
8
8
II
II
2
9 (FM)
FM
II
3
II
4
6(OONF~E)
5(O~~E)
II
5
II
6
I
I
The functions of the keys are almost the same as those in the RADIO mode. Only difference
is that the keys are not accepted during timer operation.
(4) In the TIMER READ mode.
O(AM)
I
-7
1(EVERO~AY1) 2(EVE~:fAY1)
I IEVE~~DAYI I IEVE~WAYI I
I
--
4(EVE~WA Y2)
!EVERJ~AY21 IEVE~~~AY2
9(FM)
8
I -- I
3(EVER YDAY2)
ON
II
--
I
-
I
5(O~~E)
ONCE
ON
6('b~~E)
II
ONCE
OFF
I
denotes that the corresponding key input is rejected.
When TIMER READ mode is selected, only ON/OFF keys of EVERYDAY1, EVERYDAY2,
and ONCE are in effect to confirm programmed timer times and source.
(5) In the TIMER WRITE mode
I
O(AM)
1(EVEf1ci~AY1) 2(EVE~~~AY1) 3(EVE~~AY2) 4(EVE~~fAY2)
O(AM)
/1(EVE~~OAY1) I /2(EVE~:?AYll I /3(EVERO
YJ AY2 ll f4(EVE~WAY2~
I
8
7
I
7
/
I
8
9(FM)
I
I
9(FM)
6('b~~E)
5(O~~E )
I
5(O~~E)
II
6(~t'lVl
I
I
When TIMER WRITE mode is selected, the functions of the keys are differently dependent on
the sequence of key operation. (For details, see 2-2. Alternate Switches)
(6) In the TIMER CANCEL mode.
675
,uPD1704C-011
O(AM)
1(EVEfgNDAY') 2 (EVE~~~AY') 3(EVERJ~AY2) 4(EVE~WAY2)
I EVE~~DAY'I
8
7
0-9
1- I
1
IEVE~:fAY' I IEVE~~DAY21 IEVE~~fAY21
5(O~~E)
6 (OO~~E)
I,-_O_~_~_E---Jl ,-1_O_O~_1=_E---,I
9(FM)
-- II'-_-::"-::"-::"--11 -- denotes that the corresponding key input
is rejected.
When TIMER CANCEL mode is selected, depressing ON/OFF keys of EVERYDAY1,
EVERYDAY2, or ONCE cancels the programmed timer times and sources.
OFF
This is the key to cut off power supply relay. By depressing this key, AC OUT terminal and
select or terminals (AUX, TAPE, PHONO, and TUNER) are forced to low level and get indication
of time on the display.
To turn on the power Supply relay, depress one of the AM, FM, preset station keys (1-8) or
source selector keys (TAPE, PHONO or AUX) in the RADIO mode.
CLKCAL
Key to call present clock time during frequency display. When this key is pressed, the present
clock time is indicated for five seconds and then the frequency display is recovered.
CHSCAN
Key to scan preset channels.
When this keys is pressed, the memorized preset stations (1-8) are in turn scanned from "1",
holding for 5 sec at each preset station. To stop scanning at the currently received station, press the
preset station key currently selected.
UP
DOWN
676
Kyes for auto and manual tunings. When either key is pressed, the following functions are
performed.
(1) When AUTO/MANUAL switch is set to AUTO.
Keying of UP increases frequency in saw-tooth wave mode. If the SD terminal is forced to
high level during this process, the automatic upward searching is stopped. Keying of DOWN
brings about automatic downward searching.
Function of the DOWN key is almost the same as that of the UP key. Only difference is that
the DOWN key decreases the frequency.
*1 Automatic upward ordownward searching is performed at the rate of 60 ms/step (MIN).
This rate will varies depending on the lock-up time of the PLL system.
*2 If UP or DOWN key is pressed during automatic searching is carried on, the automatic
upward/downward searching is kept going on.
(2) When AUTO/MANUAL switch is set to MANUAL.
When UP or DOWN key is momentarily pressed, frequency is shifted by one step (channel
space) upward or downward.
When UP or DOWN key is kept pressed for 0.5 second or more, the frequency shift is
continued upward or downward at the rate of 60 ms/step (TYP.) until the key is released.
(Note) Even if the AUTO/MANUAL switch is turned to MANUAL during auto process, the
auto tuning is not intercepted. If the auto-tuning is required to be stopped immediately by switching to MANUAL, formulate the system in such a way that SD
terminal is forced to high level whenever the AUTO/MANUAL Switch is turned to
MANUAL.
MEMORY
Key used to write currently received frequency into a preset memory. When either of keys 1-8
is depressed within 5 seconds after this key is pressed, the currently received frequency is
written into the memory corresponding to the keyed-in switch (1-8).
The memory write-enable state lasts 5 sec. from the time when the MEMORY key is pressed. To
cancel this state within the 5 sec., press a key other than preset channel keys (1-8) or change
the mode switches (MODSWO, 1,2).
PHONO
TAPE
AUX
Keys to select a source. When programmable mode switches (MODSWO, 1, 2) are set to RADIO,
keying one of these switch wi /I force AC OUT terminal and the source selector terminal corresponding to the pressed key to high level. When programmable mode switches are set to TIMER
WR ITE, the deying-in of either switch will shift the corresponding select terminal to high level
for about 500 ms.
jlPD1704C-011
2-4. Transistor Switch
Remote control signal is input to this switch. (For configuration, see 1-2, Connection of Keys and Switch
Types on Key Matrix.) The remote control signal should also be input to the RMC terminal at the same time.
Fig. 1 shows the wave form of remote control signal. The first 10 ms low level stands for initializing signal.
The number of the following pulses determines the type of operation.
Active Low
I·
10 ms
6 ms
.II.~
t
1.5 ms
0.5 ms
Fig. 1 Timing Waveform of Remote Control Signal
The signal discriminated by key input (K1 terminal) via the transistor switch is the initializing signal only.
The following pulse train is discriminated by RMC terminal.
Table 1 shows the correspondence between pulse counts and operations.
Table 1 Number of Pulses and Related Operation
Number of Pulses
0-7
Operation
Preset CH (1-8)
8-10
Oon't care
11
AUX
12
PHONO
13
FM
14
TAPE
15
AM
3. DESCRIPTION OF DISPLAY
3-1. Display Connection Diagram
Fig. 2 shows the connection of the display. 01-06, Sa-Sg, COLON, and OP (decimal point) correspond to
digit terminals (01-06), segment terminals (Sa-Sg), COLON terminal, and OP terminal of JlP01704C-011,
respectively.
Since the segment terminals of JlP01704C-011 have breakdown voltage of 30 V (corresponding to Pch open
drain output voltage), they can be directly connected to FIP (fluorescent indicator panel). Oigits (01-06),
CO LON, and OP are complementary outputs and they are output in active low. Hence one stage of buffer
(with PNP transistor 2SA733 or equivalent) is required.
677
,uPD1704C-011
:
FM
AM
(Sa)
:
:
I
I
I
I
I
I
I
l
I
06
(COLON)
:
:: I·'-·1I. :i
I
I
(Sb)
I
I
I
I
:
005
004
(OP):
,-)
I•I
(OP)
:
I (Sf)
I
Fig. 2 Example of Indicator Display
3-2. Examples of Displays
The typical displays are as follows.
(1) FM in the U.S.A.
FM
I-'
I_I
•
1-'
I
MHz
(2) FM in Europe
-,
I ,
FM
MHz
(3) FM in Japan
FM
(4) AM in the U.S.A.
AM
678
•
,'-'= ,-=,
1-'
,_,
MHz
MEMO*
kHz
I-
I(Sb) I
I I
I
I (Se) (S9) (Sc) I
I
I
I
(Sd)
I
I
I
02
003
I
I MEMO
(Sa)
001
(Sc)
MHz
(Sa)
kH Z
(Sb)
06
,uPD1704C-011
(5) AM in Europe or in Japan
AM
kHz
(6) Clock display
•
•
* Display of MEMO is turned on for 5 seconds when the momentary key MEMORY is pressed, i.e. when
the key is pressed in order to write the current frequency into the memory. If preset key either of 1-8 is
pressed within that 5 seconds, the new frequency is memorized and the indication MEMO goes off.
4. DESCRIPTION OF PROGRAMMABLE TIMER OPERATIONS
There are three sets of programmable timers; EVERYDAY1, EVERYDAY2, and ONCE.
Once programmed with ON/OFF times and source, EVERYDAY1 and EVERYDAY2, execute everyday ON
and OFF of the programmed source at the programmed ON/OFF times.
While, in ONCE, programmed source and ON/OFF times are canceled after the source ON/OFF execution is
performed.
The priority of these timers is in the sequence of ONCE, EVERYDAY2, and EVERYDAY1. In each timer
system, OFF has higher priority than ON. Hence the following performance patterns are realized according to
the timing relationship.
CD
ON and OFF times are not crossed over.
~
ON time
OFF time
ONCE
9:00
11 :00
EVERYDAY2
EVERYDAY2
21 :00
23:00
EVERYDAY1
EVERYDAY1
6:00
7:30
time
OFF
ON
.
- - -I
I
ONCE
:
:
ON_OFF:
5
,
'
6
7
I,
8
:
9
:
!
:
:
!
..
,!
,
10 11 121121 22 23 24o'clock
(Note) - Denotes timer in operation.
@ ONCE goes ON during EVERYDAY2 is in operation.
-------
ON time
OFF time
ON
ONCE
ONCE
20:00
23:00
EVERYDAY2
EVERYDAY2
19:00
21 :00
EVERYDAY1
EVERYDAY1
6:00
7:30
time
OFF
!
ON r----:---; OFF
5
6
7
8
9
18 19 20 21 22 23 24 o'clock
@ EVERYDAY2 goes ON during EVERYDAY1 is in operation.
-----=-
ON time
OFF time
EVERYDAY2
EVERYDAY1
EVERYDAY2
11 :00
14:00
EVERYDAY1
10:00
12:00
ON
ON~OFF
,
time
OFF
9
1
,
10 1112 13 14 15 16 1718 19 20o'clock
679
.uPD1704C-011
@
EVERYDAY2 goes ON during ONCE is in operation.
-----
OFF time
ON time
ONCE
10:00
14:00
EVERYDAY2
EVERYDAY2
12:00
17:00
time
®
I
ONCE
ON time
OFF time
12:00
17:00
I
ON
I
I
OFF
. ON
i
!.. N 0 gOing
iZ
EVERYDAY2
EVERYDAY2
16:00
19:00
EVERYDAY1
10:00
13:00
time
OFF
ON
I
9
I
I
I
10 11 12 13 14 15 16 17 18 19 20 o'clock
Continuously programmed in the sequence of ONCE, EVERYDAY2, and EVERYDAY1.
---=----
OFF time
ON time
O~FF
ONCE
ONCE
12:00
14:00
EVERYDAY2
EVERYDAY2
14:00
16:00
EVERYDAY1
EVERYDAY1
16:00
18:00
time
----
Reversed sequence of
I
,
ON
ONCE
OFF time
ONCE
16:00
18:00
EVERYDAY2
EVERYDAY2
14:00
16:00
EVERYDAY1
,
14:00
time
OFF
:----i
ON
ON
I
12:00
,
10 11 12 13 14 15 16 17 18 19 20o'clock
@
ON time
EVERYDAY1
9
No going ON
~GOingOFF
!
I
S80
I
11 12 13 14 15 16 17 18 19 20 o'clock
9
ONCE
EVERYDAY1
(j)
!
I
/No going ON
./
ONCE goes ON during EVERYDAYl is in operation, and, EVERYDAY2 goes ON during ONCE is in
operation.
----
®
OFF
0
ONCE
9
,
:
!
:----1
:
r------:
,
10 11 12 13 14 15 16 17 18 19 20o'clock
,uPD1704C-011
5. TYPICAL APPLICATIONS
A wide variety of set models can be developed by combining initial setting diode matrix, NONCLOCK
and FM ONLY and remote control function. The following table shows some examples of the variations and
effective keys on each variation.
LEGEND on symbols
(key)
0
Function effective
Function ineffective
x
•
All the key functions diffective
AM
Only AM effective
FM
Only FM effective
Ineffective (prohibited)
~
KEY
_ g..c
NONCLOCK
:~'='i
":~(J)
1
4
3
2
OFF ON OFF
ON
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
8
7
ON OFF
ON OFF
ON OFF
OFF ON OFF
ON OFF ON
FM ONLY
OFF
ON
BAND
Both AM and FM
FM Only
x
Remote Control
c
oQ
6
5
x
0
0
....
t.)
C
::J
u.
x
Source Selector
Clock
x
Timer
x x
o (AM)
x
0
AM
1 (EVERYDA Yl )
ON
2 (EVERYDAYl )
OFF
3 (EVERYDAY2)
ON
4 (EVERYDA Y2 )
OFF
5 (ONCE)
ON
6(ONCE)
OFF
x
0
x x
0
1
0
2
0
2
4
5
6
3
4
x
0
x
x
AM
1
0
2
•
2
3
•
•
3
4
x
0
x x
0
•
AM
•
•
•
•
1
•
•
•
•
3
0
•
AM
0
x
0
x
0
•
4
5
0
5
0
5
6
•
6
•
6
REMCON
CJ)
OFF
0
CLKCAL
>-
•
H~
~
o~
4
5
6
3
•
6
X
•
•
1
2
5
•
•
•
•
•
•
2
3
4
5
•
6
X
X
-
0
1
•
•
•
4
0
X
0
0
0
•
•
1
2
3
0
4
0
•
•
5
6
8
8
QJ
3
•
•
•
•
•
x
0
-
0
0
7
9 (FM)
en
2
0
X
-
0
x
0
X
0
1
0
7
..c
X
-
•
•
•
•
•
1
x
0
x
0
x
0
•
FM
•
FM
•
-
•
-
•
9
•
-
•
FM
-
•
9
-
•
9
•
•
-
-
•
9
•
-
•
-
-
•
•
-
•
QJ
~
CHSCAN
OJ
:>
°B
UP
~
w
•
DOWN
MEMORY
PHONO
•
-
TAPE
•
-
•
-
•
-
AUX
CLOCK SET
M
a
RADIO
D
E
TIMER OPE
S
W
TIMER READ
TIMER WRITE
•
-
-
•
•
-
-
-
•
•
-
•
•
-
•
-
•
-
•
-
•
-
•
-
•
-
•
-
•
-
•
-
•
TIMER CANCEL
S81
j.lPD1704C-011
5-1. Example of types without remote control nor clock
(Corresponding type numbers: 1, 4, 13, and 16)
Voo
...-__+---t TU N E R
KOt------,
OPEN
.--__+---tPHONO
ScJ------'
VOO ~--
0
I
0
:::>
:::>
\~/
I
U
:::>
o
-'
U
t_
I-
>
I-
>
U
(Y)
~
I----t--J~ ~
a:
r--
0)
oa.
I-
::I.
a.
o
I-
w
-'
:::>
I-
o
w
U
>
a:
w
en
I~
,--_+-t_-l
- -
5-eS
.-..----tdO 'NOlO:::>
1 - - - - - ; 0 - V'
w
(J\.1..)
a.
x nV' .---..;-.~
1 - - - - . . , lI\IV'/lI\I:I
o
a.
o NOH d t-.......,r-t---1
::I.
a:
«
I-
w
I-
3dV'1.1-1H-t-t---t
r-- 9-00
83 N nl. .......H-I-t---t
~
u.
U
w
-'
w
en
w
u
a:
:::>
o
en
v
l.no:lV'~
S87
m
(X)
(X)
l::
"'C
APPLICATION EXAMPLE OF CIRCUIT DIAGRAM
C
.------------------------------------------------------------------------------------.-. D.P.
Digit
To FIP
Ii
I1I1
~ ~ ~ ~ ~,~
+5 V
01
16 15 14 11
11 10 9
r
I II
r
~
III
....l
a
'-I
o
b
~
c
d
o
I
e
To FIP Segment
o
....l
~
g
1SS53
...--COLON
100 kn
MUTE output
•
+5.7V~
•
• -25 V
••
+5V
System Power Supply
1SS53
47 kn
2SA733
JlPD1704C-011
100 kn
-25 V
+5V
4~~.kn t
0.01 JlF
From FM VCO
o---f
+5V
I
47 k
Q01JlF
From AM VCO
~~l~~mME
22k
~r---~~~----~
0.01 JlF
+30 V____- - - .
2.2 kn~1000p~6.8 kn
4--I I I \I
To
,
I
To FM, AM VCO
+ N-13.9
,..,
....
-In
KEY
Input
kn
1 kn
:)
2SC945
6
Remote
Control
Signal
Input
SO Input
66666
Power Supply
Control for Sets
o
AM FM AUX TAPE
I
FM,AM
Power Supply Control
PHONO
300 n
P1 P2 P3 P4 P5 P6 P7
P8
MOS DIGITAL INTEGRATED CIRCUIT
I1 PD17 05C-012
PHASE LOCKED LOOP FREQUENCY SYNTHESIZER
TV DIGITAL TUNING SYSTEM CONTROLLER
CMOS LSI
~PD1705C-012
is a CMOS LSI developed for television receivers of PLL frequency synthesizer system designed
to U.S.A. and Canada. PLL and controller are contained on a single chip. This LSI, with the pre-scaler J,.LPB562C,
constitutes a high performance PLL television receiver system. Since PLL section uses pulse-swallowing
system, fine tuning can be easily done with a high precision. Furthermore, it is provided with functions of
remote control, clock, and timer.
FEATURES
• PLL and controller are packed in one chip.
• Multifarious station selection modes are provided.
la-key direct selection .....................
with automatic/manual switching
channel up/down selection ............... with automatic/manual switching
• High precision fine tuning capable by the use of pulse-swallowing system (1 step 40 kHz ± 2.2 MHz, max.)
• CATV stations can be selected.
• 12-hour system clock and ON/OFF timer contained within.
• Remote control receiver contained. (J,.LPD1913C and J,.LPC1373H are used.)
• Provided with the function to output BCD channel number to CRT display interface.
• CMOS structure with low power consumption.
• Single power supply of +5 V.
• 42-pin dual in-line package (DIP)
PACKAGE DIMENSIONS
in millimeters
e!
~
025+ 0 • 10
•
-0.05
15.24
0-15
0
689
tt PD17 05C-012
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VOO
-0.3"'+6.0
Input Voltage
VI
-0.3-+VOO
Output Voltage
Va
-0.3"'+Voo
Output Current
10
10
Operation Temperature
Topt
-35""+75
Strage Temperature
Tstg
-55"'+125
Output Breakdown Voltage
VBOS1
Sa-Sg terminal: -35
V
Output Breakdown Voltage
VBOS2
CHO-CH3, MS terminal: -15
V
Output Breakdown Voltage
VBOS3
B01, B02 terminal: +15
V
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC
Supply Voltage
SYMBOL
VOO
MIN.
TYP.
MAX.
UNIT
4.S
S.O
5.S
V
Output Breakdown Voltage
VBOS1
-30
V
Sa-Sg terminal: IOFF=-5 JJ.A
Output Breakdown Voltage
VBOS2
-11
V
CHO-CH3,MS terminal:IOFF=-10 JJ.A
Output Breakdown Voltage
VBOS3
13
V
B01,B02 terminal: 10FF=-S JJ.A
Trise
500
ms
VOO=0-4.S V
Supply Voltage Rise Time
ELECTRICAL CHARACTERISTICS (Ta=-35 to +75
CHARACTERISTIC
SYMBOL
MIN.
TYP.
°c, VDD=4.5 to 5.5
MAX.
UNIT
V)
TEST CONOITION
High Level Input Voltage
VIH1
0. 8V OO
VOO
V
REM terminal
High Level Input Voltage
VIH2
0. 7V OO
VOO
V
AFTU,AFTO,SO,CE terminal
High Level Input Voltage
VIH3
0. 6V OO
VOO
V
KO-K3 terminal
Low Level Input Voltage
VIL1
0
0. 3V OO
V
AFTU,AFTO,SO,CE terminal
Low Level Input Voltage
VIL2
0
0. 2V OO
V
KO-K3,REM terminal
High Level Output Voltage
VOH1
4.0
V
EO,VOL terminal: 10H=-0.S mA
High Level Output Voltage
VOH2
4.0
V
01-0S,MUTE,PSC,LMP terminal:IOH=-0.2 mA
High Level Output Voltage
VOH3
3.0
V
Sa-Sg terminal: 10H=-0.S mA
High Level Output Voltage
VOH4
2.S
V
CHO-CH3,MS,POW terminal: IOH=.-2.0 mA
Low Level Output Voltage
VOL1
O,S
V
EO,VOL,LMP terminal:IOL =O.S rnA
Low Level Output Voltage
VOL2
O.S
V
01-0S,MUTE,PSC terminal: 10L=0.2 mA
Low Level Output Voltage
VOL3
2.0
V
B01,B02 terminal:IOL =2.0 mA
High Level Input Current
+IIH1
100
JJ.A
KO-K3 terminal:VIN=VOO=S.O V
High Level Input Current
+IIH2
300
JJ.A
Xl terminal (Pull Oown):VIN=VOO=5.0 V
Low Level Input Current
-IlL
300
JJ.A
IN terminal (Pull Up):VIN=O V, VOO=S.O V
High Level Input Leak Current
+IUH
10
JJ.A
CE,REM,AFTU,AFTO,SO terminal:VIN=VOO=S.O V
Low Level Jnput Leak Current
-IUL
10
JJ.A
CE,REM,AFTU,AFTO,SO,KO-K3 terminal:VIN=O V
JJ.A
EO terminal:Vo=VOO,VO=O V
MHz
IN terminal:VIN=0.7 Vp_p(MIN.),OC
Output Off Leak Current
690
TEST CONOITION
10
40
10- 3
IL
Frequency Response
fiN
Supply Current
1001
3
mA
Normal Operation
Supply Current
1002
0.6
mA
CE terminal=O V,VOO=S V
Oscillation Stop Voltage
VOOS
3.2
0.5
8.8
3.8
V
,uPD1705C-012
OUTLINE OF FUNCTIONS
(1)
BANDS
VHF/UHF/CATV in U.S. and CANADA
VHF
2 ch - 13 ch
o UHF
14 ch- 83 ch
•
A ch - W ch
•
(2)
(3)
(4)
(5)
CATV
FUNCTION OF TUNING
Q
10-key direct selection with automatic/manual switching.
•
channel up/down selection with automatic/manual switching.
MANUAL FINE TUNING (MFT)
~
1 step
40 kHz ± 2.2 MHz MAX.
•
1 cycle
125 ms
AUTO FINE TUNING (AFT)
o 1 step
40 kHz ± 2.2 MHz MAX.
"
8 ms
1 cycle
FUNCTION OF CLOCK AND TIMER
•
12-hour clock (AM or PM is displayed)
o On-off timer in every 24 hours
(6)
(7)
FUNCTION OF REMOTE CONTROL
•
Contains remote control receiver
•
Using thellPD1913C (transmitter) and thellPC1373H (pre-amplifier)
DISPLAY
•
Dynamic display in 5 digits (at 130 Hz)
Channel .. ············2 digits and a display of CATV, panel locked, or remote controlled reception.
Clock ................. · 4 digits and a display of AM, PM, panel locked reception, or remote controlled·
reception.
•
(8)
BCD output terminal for CRT display interface is provided to be connected via IlPD4508C to MM58146.
REFERENCE FREQUENCY
fr = 5 kHz
691
,uPD1705C-012
PIN CONNECTION (Top View)
VOL MS LMP
CHI CHo BO l POW
IN
REM CE
GND EO
JlPD 1705C-012
EXPLANATION OF INPUT AND OUTPUT TERMINALS
692
Pin
Number
Symbol
Name of
Terminal
3-9
Sa-Sg
Segment
7-segment display output, also used as output for key-matrix.
dielectric strength (-30 V). Active high.
10-13
KO-K3
Key
Input of key-matrix return signal.
14-18
05-01
Digit
19,20
Xl, X2
Reference
Frequency
Oscillator
Output of digit signal for display, also used for latch pulses for BCD output
to CRT display (03, 04). Active high.
Crystal oscillator of 4.5 MHz is connected here. Feedback resistance is
contained.
21
VOO
Power
Supply
Voltage of +5 V ±10 % is supplied here. VDD rise time of 500 ms or less is
Irequired. For too long rise time, initializing may not be normally
performed.
22
EO
Phase
Detection
Output
Charge pumping output from phase detector. This output supplys tuning
voltage to varactor of tuner via a low-pass filter.
23
GNO
Grounding
Connected to the ground of system.
24
CE
Chip
Enable
High: Normal operation
Low: Memory retention (display off, PLL function disabled).
Low level signal less than 134 J,lS is neglected.
25
REM
Remote
Control
Signal Input
Input terminal for remote control signal. The output of preamplifier
J,lPC1373H is connected here. Active low.
26
IN
Local
Oscillator
Input
Tuner local Qscillation signal is input here via prescaler J,lPB562C. An a.c.
anplifier is contained. So input should be connected through a capacitor.
27
PSC
Pulse
Swallow
Control
Output terminal of pulse swallow control signal.
terminal of prescaler p.PB562C.
28
MUTE
Muting
Output terminal of signal to cut noises when PLL is unlocked. Active high.
Descriptions
High
Connected to PSC
jlPD1705C-012
Pin
Number
Symbol
29
32
B01
B02
Name of
Terminal
Band
Descriptions
Output terminal of tuner band switching signal. The form of the signal is
shown below.
1--:1
MB, V~
H
H
VL
L
H
1
1
SB
H
L
1
UB
L
L
I
31
POW
Power
Output terminal for controlling power supply.
33-36
CHOCH3
Channel
Number
Output
Output terminals for BCD data to CRT display interface. The number of
receiving channel is output in 2-digit dynamic BCD signal.
37,38
AFTU
AFTD
AFT Input
Input terminal for AFT signal. AFT signal converted in binary form by
comparator J,LPC393C is supplied here.
SD
Station
Detector
Input terminal for stop signal during auto tuning. Active low. However,
it is necessary that it turns to low level within 100 ms after PLL locking.
40
LMP
Lamp
Output terminal for displaying remote control signal reception. A pulse of
20 ms duration is output when remote control signal is received.
41
MS
Mode
Switch
Output terminal of return signal for sensing CATV/TV and AUT/MAN
switching.
42
VOL
Volume
Output terminal of varialbe-duty pulses to control volume. The signal
is input to d.c. attenuator via an external lowpass filter.
-
39
CONNECTION TO THE MATRIX OF KEYS
~
K3 (13)
K2 (12)
K1 (11)
KO (10)
Sa (3)
0
1
2
3
Sb (4)
4
5
6
7
Sc (5)
8
9
CLEAR
RECALL
Sd (6)
FTU
CHU
VOLU
MUTE
Se (7)
FTD
CHD
VOLD
Sf (8)
HADJ
MADJ
PL
Sg (9)
CLOCK
ONTIM
OFTIM
MS (41)
CATV/TV
AUT/MAN
SDCONT
POWER
TIMER
-
693
j1PD1705C-012
COMPOSITION OF KEYS
--+-+-+-~I-+-If--++-+-~I-+-"""-------___- - + - - - + - - - - + - - - - -___
KO
K2
Sg
Sf
Se
Sc
Sa
MS
694
o
momentary key switch
D
alternate switch
"'V
transistor
VOL
to display
j1PD1705C-012
EXPLANATION OF CONTROL KEYS
Symbol
0-9
(Number Key)
Function
Used for direct channel selection. For direct channel selection, input the number of
desired channel in two digits. (Channel 8 or 12 is selected by keying (0), (8) or (1), (2),
respectively.) When, after keying the first digit in either of 2-9, the second keying is
delayed more than 2-3 seconds, the channel corresponding to the first keyed number is
selected. (keying of only (3) selects Channel 3.) If some non-existing channel number
is keyed-in, no channel selection is done, and the display recovers the preceding channel
number.
In auto-mode (when AUT/MAN switch is on), when no station is detected in the channel
specified by keying, the channel automatically shifts up as far as the channel where
station can be detected.
CLEAR
If the first keying has been done wrong for direct channel selection, depress this key to
recover the original state immediately. Then, follow the selection process from the
beginning.
RECALL
This key switches display modes. Every time when this key is depressed, clock or channel
is alternatingly displayed.
CHU
(up-channel
selection)
In auto-mode (when AUT/MAN switch is on), when this key is depressed, the channel
shifts up until the channel transmitting wave is found. When this key is further kept
pressed down, the reception of the selected channel will be kept for 600 ms and then the
channel will shift up again until another station is received. This procedure is repeated
until the key is released.
In manual mode (when AUT/MAN switch is off), when this key is kept depressed, the
channel again shifts up by 1 after a waiting time of 600 ms. This procedure is repeated
until the key is released.
CHD
(down-channel
selection)
This key is only different from CHU in the shifting down-channel, instead of up-channel.
Others are the same as CHU.
FTU
(fine tuning
upward)
This key serves for fine tuning. It is enabled only in manual mode. Depressing this key
and then releasing within 500 ms makes the tuning frequency shift upward by 40 kHz.
After the depression is kept for 500 ms, the tuning frequency is raised by 40 kHz, once
after every 125 ms. When the upper limit (+2.2 MHz) is reached by this procedure, the
frequency goes down to the lower limit (-2.2 MHz) and again the upward shifting
starts.
When other channel is selected, the fine tuning condition is resetted.
FTD
(fine tuning downward)
This key is only different from FTU in the frequency shift downward instead of
upward. Other features are the same as FTU.
VOLU
(increase volume)
This is the key to control sound level. When this key is depressed the sound level is
raised by 1 step in every 100 ms until the key is released. The total number of steps is
64, (duty ratios are 0, 3/67-65/67) so as to adjust the sound level smoothly,
VOLD
(decrease volume)
This key is only different from VOLU in the volume level attenuating instead of raising.
Other features are the same as va LU.
MUTE
(muting)
This key is used to mute sound. Every time when this key is depressed, mute output is
reversed. The muting is released when power is turned on, when a volume control key
(VOLU or VOLD) is operated, or when any channel is selected.
POW
(power)
This key controls the power source. Every time when this key is depressed, power output
is reversed. When power is in off-state, only POW key, P L key, time adjuster key and
switch is in enabled condition. When power is turned on, channel is on display, while it
is turned off, clock is displayed.
PL
(panel lock)
This key prevents misoperation. When panel lock is on, keys other than POW key and
PL key are ineffective. When power is on, panel lock is released.
695
,uPD1705C-012
Symbol
HADJ
(hour adjust)
This key is used to adjust hour. This is effective only when a time adjuster switch
(CLOCK, ONTIM, or OFTIM) is on position. When this key is depressed and then
released within 500 ms, the hour is advanced by 1 hour. If the depression is held longer
than 500 ms, the hour is further advanced byl hour once every 250 ms after the 500 ms
until the key is released.
MADJ
(minute adjust)
This key is used to adjust minute. The performance is basically the same as HADJ.
When the advancement reaches 60 minutes, it returns to zero without counting up in
hour.
CLOCK
(clock adjustment)
This is the clock adjustment mode switch. When this is turned on, clock is displayed and
HADJ and MADJ keys are available. While this is on, the clock is stopped, and, when the
switch is turned off, the clock start from a second. When panel lock is on, the clock
cannot be adjusted by turning this switch on, but, it should be noted that second is reset
to a by this switch.
ONTIM
(on-timer
adjustment)
This is the on-timer adjustment mode switch. When this switch is turned on, the ontimer mode is displayed and the on-timer can be adjusted to the desired setting by using
HADJ and MADJ keys.
OFTIM
(off-timer
adjustment)
This is the off-timer adjustment mode switch. When this switch is turned on, the offtimer mode is displayed and the off-timer can be adjusted to the desired setting by using
HADJ and MADJ keys.
TIMER
(timer)
696
Function
This is the timer selection switch. When this switch is turned on, the timer acts at the
preset time. When it is off, the timer does not act at the preset time.
CATV/TV
(band switching)
This is the band selection switch. When the switch is on, CATV is selected, and when off,
TV is selected. When CATV is selected, Channels 2-36 (Channels 2-13: VHF, and,
Channels 14-36: CATV) can be received, while TV is selected, Channels 2-83 (Channels
2-13: VHF, and, Channels 14-83: UHF) can be received. The switching initialize the
channel to Channel 2.
AUT/MAN
(auto/manual)
This is the mode selection switch for channel selection and fine tuning. When this is on,
auto mode is taken, and when off, manual mode is taken. In auto mode, the channel
selection is accompanied by the detection of broadcast signal and AFT acts always. In
manual mode, no signal detection is performed. At the same time, MFT mode is taken
and FTU and FTD keys are effective.
SDCONT
(station detect
control)
This is the broadcast signal detection time adjustment switch. Usually it is off where the
station signal detection is started about 100 ms after PLL lock. When it is on, the time
for detection is prolonged by the unit of 100 ms until the switch is turned off. Therefore
it is possible to control station signal detection time by external signal using transistor
switch.
,uPD1705C-012
RELATION BETWEEN CATV CHANNEL AND INPUT CHANNEL NUMBER
The correspondence of CATV channels to actually keyed-in channel numbers as well as displayed channel
numbers is shown in the following table.
A
B
C
0
E
F
14 15 16 17 18
G
H
I
J
K
L
M
N
0
P
22 23 24 25 26 27 28 29
19 20 21
0
R
S
T
U
V
W
30 31 32 33 34 35 36
EXPLANATION OF REMOTE CONTROL SYSTEM
The J-LPD1705C-012 contains remote-control receiver. Combined with J-LPD1913C (transmitter) and J-LPC1373H
(receiver preamplifier), it can be remote controlled.
Functions enabled by the remote control are:
•
direct channel selection with 10-key (auto/manual)
•
channel up/down selection (auto/manual)
•
channel selection clearing (see the description above of CLEAR key)
•
Power on/off
•
muting on/off
•
•
panel lock on/off
volume up/down (in 64 steps) .... initial level 25 %
o remote-controlled reception identification signal (on lMP terminal)
Note
When the J-LPD1705C-012 receives remote control signal the reception identification pulse of about
Note
The custom code of CO - C7 = 00100000 is used for transmission. The function does not start with
20 ms is issued from lMP terminal. Use this pulse externally with some external time constnat.
codes other than this. For details of custom code. see the catalogue for J-LPD1913C.
*COMPOSITION OF KEYS AT THE J-LPD1913C
~
KIO (1)
KI1 (2)
KI2 (3)
KI3 (4)
KOO (15)
CHU
CHD
VOlU
VOlD
K02 (14)
POWER
MUTE
MUTE
Pl
K04 (13)
0
1
2
3
K05 (12)
4
5
6
7
K06 (11)
8
9
CLEAR
RECAll
697
,uPD1705C-012
APPLICATION OF REMOTE CONTROL SYSTEM
+
J.J.
PC1373H
' - - - -__- 0
~~+-------~--+----+------
DISPLAY FORMAT
Display format is 7-segment 5-digit dynamic display. (repetition frequency: 130 Hz and duty ratio: 15 %)
Display is connected in the following fashion.
-...J
I
I
II
II II
I- I n
LI
c)
02
c~
01
(
03
COLON
AM
PM
CATV
PL
0
0
05
CLOCK DISPLAY
Clock is displayed in 4 digits of numerics and 1 digit of dot (AM or PM, COLON, and PL).
AM
698
II
0
I
0
1-' I-
1_'
_I
PM
~
-
...., Sd
~
-
""" Se
Sf
...
~
04
I -I
I 1-
0
0
Sa
...., Sb
....., Sc
Sg
REM
+12V
j,lPD1705C-012
CHANNEL DISPLAY
Channel is displayed in 2 digits of numerics and 1 digit of dot (CATV and PL). The digit of ten is displayed at
D3 timing and the digit of one at 04 timing.
-III- 1
I I -,
1_11Note
CATV
Channel and clock are alternatingly displayed by operating RECALL key. When power line is connected
or when power switch is turned off, clock is displayed. Whereas, when power switch is turned on or
when selection key (0-9, CHU, CHO) or CATV lTV switch is operated, channel is displayed. Furthermore, when clock adjustment switch (CLOCK, ONTIM, and OFTIM) is on, clock is displayed.
OPERATION OF CLOCK AND TIMER
CLOCK
Clock should be adjusted following the schedule below.
1) Turn CLOCK switch on. Only clock is displayed. When no adjustment is done before, only AM and COLON
are displayed.
o
o
AM
2) Press HAOJ key to adjust hour. The display of AM 1 :00 appears at the moment of key depression. The display
continues to advance until the key is released.
I 0
AM
I
0
'-I '-I
,_, '_'
3) Press MAOJ key to adjust minute. The displayed minute continues to advance until the key is released.
No counting up occurs in hour if the minute reaches 60.
AM
4) Turn CLOCK switch off coincidentally with other clock or time signal. The clock starts from 0 second at the
moment of switch off.
699
,uPD1705C-012
TIMER
Adjust timer according to the following procedure.
1) Turn ONTIM (OFTIM) switch on. Timer is displayed.
o
o
AM
2) Adjust timer to the desired time in the same procedure as clock adjustment.
PM
3) Turn ONTIM (OFTIM) switch off. The display is changed to clock.
AM
-1
0
I
0
-11_I
=1
4) Turn TIMER switch on.
Note:
During panel lock, clock cannot be adjusted. But when CLOCK switch is turned on/off, clock is reset to
o second.
Note:
700
When both on-timer and off:timer are set to the same time, off-timer is dominating.
do~s
Note:
While CLOCK switch is on, clock
Note
While one of time adjustment switches is on, remote control is ineffective.
not advance.
Note:
Do not turn on two or more time adjustment switches at a time.
,uPD1705C-012
AUTO-SEARCH FUNCTION
J,lPD1705C-012 is provided for channel selection with a function to tune in automatically to a transmitting
station by detecting the presence of the wave (when in auto mode). The searching of channels are performed in
an specified derection (up-channel for up-channel selection, or down-channel for down-channel selection), or, in
up-channel direction when direct selection is performed.
If there were a deviation in the frequency of wave transmitted by a station, the reception of signal at the right
frequency might be impossible. In such cas'es, the receiving frequency is shifted by 320 kHz as far as ±1.6 MHz
to be tuned in the transmitted signal. When a signal is detected half ways, the searching is finished. When the
detection is not completed in ±1.6 MHz range, the next channel will be sought. The searching procedure within a
channel is shown in the following figure.
1.6 MHz
I
I
I
I
: - 100 m s .: -/- :
PL L lock period
~----------~v-----------~
detection of broadcast signal
FINE TUNING
J,lPD1705C-012 has a high precision fine tuning function to correspond to frequency shift of station. In virtue
of this feature, the shift in receiving frequency can be easily compensated to keep the optimum receiving condition. Two types of fine tuning functions are available; manual (MFT) and auto (AFT).
1) MFT (manual fine tuning)
This tuning is operated with FTU or FTD key. Selection of another channel resets the fine tuning status.
FTU and FTD keys are effective only when AUT/MAN switch is off (in manual mode). The fine tuning is done
in 40 kHz step at every 125 ms and the limit of frequency shift is ±2.2 MHz.
2) AFT (auto fine tuning)
It is effective only when AUT/MAN switch is on (in auto mode). This is operated by external AFT signal
and it always follows the change in AFT signal. However, it is ineffective during channel selection. The fine
tuning. is done in 40 kHz step at every 8 ms and the limit of frequency change is ±2.2 MHz. AFT is operated
by the signal applied to AFTU or AFTD terminal. When AFTU terminal is at high level, the tuning frequency
is raised, while AFTD terminal is at high level, the frequency is lowered. When both AFTU and AFTD
terminals are assigned with low level, the operation is stopped,
Note:
In either AFT or MFT, when the frequency is shifted as far as the upper or lower limit respectively,
the frequency is shifted back to the lower or upper limit.
Thus the fine tuning is continued
cyclically.
701
,uPD1705C-012
CRT DISPLAY
pP01705C-012 is provided with terminals (CHO-CH3) for output of BCD channel number for CRT display.
This output is presented in dynamic format which is the same as the display format (that is, digit of 10 is output
at the timing of 03 and digit of 1 is output at the timing of 04). Therefore, by providing a latch (,uPD4508BC)
externally, the output can be taken outside.
MSO
+5 V
--H-t-+------.
04
CHO
CH 1
CH2
OUTPUT PATTERN
numeric
702
BCD output
0
0
0
0
0
1
0
0
0
1
2
0
0
1 0
3
0
0
1
1
4
0
1 0
0
5
0
1
0
1
6
0
1
1 0
7
0
1
1
1
8
1
0
0
0
9
1 0
0
1
1
1
1
1
CH3
03
APPLICATION CIRCUIT
C
SD Input
)
(SCD Output)
i
,
,
Muting Output
i
1S954
AFT Signal
Remote Control
Signal Input
+12 V
-c=
I
AC117/100 V
ION/OFF
r----.----- +15 V
VOLUME
....-----<"'>VSW
CONTROLo------+--~~~~~--_4--~
TO DC ATT
220~
47 k
2SC945x2
2SA733x3
..---_-n US
;J; 0.01 ~
1
OVB
lO.01~
~
20p
4.5 MHz
HC-1B/U
TOYO COM
TOC-231A
-BC
'"----1--1
I
0 from VCO
1000p
L---
Latch Pulse
220
b
c
d
e
9
REM AM
D5
C
1SS53x10
[]~
[W[WCATV
o~
/ I:J ~
~ LED (Cathode Common)
PM
1:::
"'tJ
+33 V
47X7
LI Ll
.,10 k
10 k
~
f'>Tuning Voltage
D5
4.7 k
2SC945x2
'"U'1
o
0.47~
PL
(")
I
o
~
..J
o
w
N
MOS DIGITAL INTEGRATED CIRCUIT
fLPD1 706G-011
PLL SYNTHESIZER CONTROLLER FOR LW/MW/FM/SW
with built-in LCD driver
The pPD1706G-011 is a 6-band (LW/MW/FM/SW1/SW2/SW3) PLL synthesizer controller with a timer, developed specifically for use in radiQ cassettes intended for Japan/U.S./Europe. Since it has a built-in LCD driver
for display, LCD (Liquid Crystal Display) can be directly driven. By combining it with a low voltage drive
prescaler pPB556C designed for the purpose, therefore, you can build a low-voltage, low-power-consumption
LCD drive digital tuning system.
FEATURES
•
PLL and controller in a chip
•
LCD direct drive (1/3 duty, 1/3 bias)
•
Single 3 V ±10 % supply
•
Low power consumption: due to CMOS
•
Capable of receiving six bands (LW/MW/FM/SW1/SW2/SW3)
•
Pulse swallowing method (FM/SW2/SW3)
•
Capable of controlling radio cassette (with radio/tape switching terminal)
•
Main power control terminal provided
•
Power on reset circuit self-contained (no external parts required)
•
Clock function self-contained (12 hour/24 hour display switching possible)
•
Alarm timer self-contained (buzzer modulation signal output possible: 3 kHz + 4 Hz + 0.5 Hz modulation)
•
Sleep timer self-contained (60 minutes maximum ... Time can be set in the unit of five minutes.)
•
A variety of tuning modes
*
Manual up/down search (saw-tooth mode): 125 ms/1ch.,
* Automatic up/down search (saw-tooth mode):
* Preset channel tuning: Random preset system
* Direct frequency tuning: With error display
•
•
125 ms/10ch.
60 ms/1ch.
10 preset channels can be stored in memory. (Random system)
Last one memory (when power is OFF) and last preset channel memory (when bands are switched over)
functions self-contained
•
Uses 150 kHz crystal
•
Uses 64-pin flat package which allows thinner assembly
•
Allows I F offset of FM (four different I Fs spaced 25 kHz apart).
•
Employs quasi static key scan system (no key scan noise generated).
•
All output terminals N-ch open drain (breakdown voltage 8.5 V MIN.)
(ex-cept KSO through KS9, E01, E02, PSC, COMO through 2, 1a through 9a)
704
jlPD1706G-011
PACKAGE DIMENSIONS (Unit: mm)
14
12.0 ± 0.3
~
~
P'""
-
-
~
r-
I
I
I
I
II
,. 64
1
52
"
51·
:-=-
.
-
I
0
I
I
0
0
0
I
I
0
0
0
0
I
I
I
I
I
I
0
I
0
I
('t)
I
I
0
I
q
co
+l
I
0
N
0
I
0
I
0
I
I
0
I
I
I
I
0
0
19
33
\. 20
32
I
I! i!
I
I
I
I
.....
-
I-
l!5
N
-
...
--
-
~(DDDOOOOO
0
.J
- - 0.4 +0.2
- 0.1
1.0 ±0.15
'--_ _
+l
UJ
0
I
I
'¢
ci
0
I
I
0
I'"
x
«
~
rq
00000)\----....,
19.6 ± 0.4
705
,uPD1706G-011
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VOO
-0.3 to +6.0
V
Input Voltage
VI
-0.3 to VOO
V
Output Voltage
Vo
Output Current
10
+10,5( SWl S,SW2S,SW3S, FMS,
)
MWS,LWS,MUTE,PWROUT
P LS terminal
V
mA
10
Operation Temperature
Topt
-35 to +75
Storage Temperature
Tstg
-55 to +125
°c
°c
ELECTRICALCHARACTERISTICS (Test Condition unless otherwise speCified:)
T opt=-35 '" +75 °C, VDD=2.55"'3.3 V
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply Voltage
V001
2.7
3.0
3.3
V
CPU and PLL operation
Supply Voltage .
V002
2.55
3.0
3.3
V
CPU operation, PLL stop
CHARACTE R ISTIC
Supply Current
1001
2.0
Supply Current
1002
8.5
Supply Voltage Rise Time
Oscilation Start Voltage
Output Breakdown
Voltage
Low Level Output Current
VOOS
Vo
100
2.7
VOH1
Low Level Output Voltage
VOL1
High Level Input Voltage
VIH1
Low Level Input Voltage
VIL1
IOH2
Low Level Output Current
IOL2
High Level Output Voltage
VOH4
Low Level Output Voltage
VOL4
High Level Input Voltage
VIH4
Low Level Input Voltage
VIL4
High Level I nput Current
IIL4
High Level Input Voltage
VIH5
Low Level Input Voltage
VIL5
High Level Output Voltage
VOH6
Low Level Output Voltage
VOL6
8.5
0.6
0.4
0. 7V OO
0.3 Voo
1.0
0.5
6
IlL I
Output Voltage for LCD
Vo
(IOL=400 J.l.A)
V
"
V
" CE terminal
V
mA
V
"
"
(VOL =0.4 VOO)
KSO'" KS7 (lOH=-200 J.l.A)
"
V
"
V
"
E01, ED2,terminal(VOH=0.6VOO)
J.l.A
V
10- 3
0
KS8, KS9 terminal (lOH=-400 J.LA)
40
"
(lOL=8 J.LA)
(VOO=VIH=3.3 V)
SO terminal
"
V
PSC terminal (lOH=-0.1 mAl
02VOO
V
6.2
MHz
"
(lOL =0.2 mAl
VIN= 1 Vp_p sine wave (DC cut)
8.5
MHz
1
J.l.A
V
0.8 VOD
Output Off Leak Current
V
02 VOO
02VOO
0.5
mA
KO"'K3
0.8 VOD
fFM
CL =20 pFx2
SW1 S, SW2S, SW3S, FMS, MWS,
LWS, MUTE, PWROUT, BUZ terminal
" (VOL=0.5 V)
V
0.6 VOO
fAM
CPU operation, PLL stop
V
VOO-O.4
FM Response Frequency
J.l.A
ms
mA
-1.0
0.5
FM terminal 8.5 MHz input
V
VOO-O.4
AM Response Frequency
mA
V
IOL2
High Level Output Voltage
High Level Output Current
706
tr
TEST CONDITION
0.2
VIN=0.8 V p _p sine wave (DC cut)
E01, E02, terminal
1a-9a,COMD-2 terminal(Voo=3 V)
j,lPD1706G-011
CHARACTER ISTIC
SYMBOL
MIN.
Output Voltage for LCD
TYP.
MAX.
Vl
0.8
1.0
1.2
V
"
V2
1.8
2.0
2.2
V
"
V3
2.8
Pull·down Current
"
3.0
TEST CONDITION
UNIT
1a-9a, COMO-2 terminal (VOO=3 V)
"
"
V
IPDl
400
p.A
AM,FM terminal(VDD=VIH=3.0 V)
IPD2
300
p.A
XI terminal (
High Level I nput Current
IIHl
2
p.A
AM, FM terminal (
Low Level Input Current
IlL 1
-2
p.A
)
"
"
)
"
1. GENERAL DESCRIPTION OF FUNCTIONS
1-1. Receiving frequencies
Band
Receiving Frequency
Range
LW
153...... 281 kHz
1 kHz
1 kHz
522 ...... 1611 kHz
9 kHz
3 kHz
530""1610 kHz
10 kHz
5 kHz
MW
FM
87.5...... 108.0 MHz
76.1 ...... 108.0 MHz
Channel Spacing
Reference
Frequency
450 kHz
450 kHz
(Note)
200 kHz
50 kHz
Intermediate Frequency
25 kHz
10.650,10.655,10.700,10.725 MHz
(Note)
-10.675, -10.700, -10.725, -10.750 MHz
5 kHz
450 kHz
50 kHz
2.300...... 2.935 MHz
SWl
2.940...... 3.575 MHz
3.580...... 4.215 MHz
4.540...... 5.175 MHz
5.820...... 6.455 MHz
SW2
7.100...... 7.735 MHz
'9.500 ...... 10.135 MHz
5 kHz
11.580...... 12.215 MHz
15.100...... 15.735 MHz
SW3
17.500...... 18.135 MHz
21.340 ......21.975 MHz
25.500...... 26.135 MHz
Note) Selectable by diode matrix
(For details, see P. 11)
707
,uPD1706G-011
1-2. Tuning functions
(1) Automatic tuning (saw-tooth mode)
OAutom.atic up
} .... Once a station is received, the station is retained.
.
o Automatic down
(2) Manual tuning (saw-tooth mode)
oManual up
}
.... ·Step feed by momentary switch.
oM anua I d own
If key continues to be depressed for more than 0.5 sec., fast feed is made until
key is released. If FAST key is doubly depressed, ultra fast feed is made.
(3) Direct frequency key in ........... Frequency is directly input by 10 keys.
(4) Preset memory call ................. Common to all bands, 10 stations in total
1-3. Timer functions
(1) Alarm ............ When preset time arrives, buzzer pulse is output. At the same time, power is turned on.
The ON state lasts for 120 minutes, and then both are forced to the OFF state. (Daily
timer)
(2) Sleep .............
708
Can be set to 60 minutes maximum five minutes apart.
,uPD1706G-011
2. PIN DESCRIPTION
2-1. Pin Configuration (Top View)
51 50 49
,... 47
,...
.....
..... ,... 48
46 45 44 43
,...
r-
r-
....
42
,... 41
r-
40 39 38 37 36
r-
r-
r-
r-
.....
35 34
..... .....
33
,...
52 I
I 32
53 I
I 31
54 I
I 30
55 I
I 29
NEe
56 I
57 I
I 28
I 27
J..LPD1706G-011
58 I
I 26
59 I
I 25
60 I
1 24
61 I
I 23
62 I
1 22
0
63 I
1 21
I 20
64 I
- -2 -3
Pin. No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Symbol
NC
8a
7c
7a
6a
5c
5b
5a
3b
4c
4b
4a
3a
2c
2b
2a
'-
4
'-
5
Pin. No.
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
.... .... .... .... - - ....
6
7 8 9 10 11 12
Symbol
1c
1b
la
7b
9a
VL
VH
COM2
COMl
VOO
COMO
KS9
KS8
T/R
PWRSW
SW1S
Pin. No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
-
-
'-
-
~
l.-
I.-
13 14 15 16 17 18 19
Symbol
SW2S
SW3S
FMS
MWS
LWS
MUTE
PWROUT
BUZ
KSO
KSl
KS2
KS3
KS4
KS5
KS6
KS7
Pin. No.
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
Symbol
XI
XO
K3
K2
Kl
KO
PSC
AM
FM
VOO
SD
PWRIN
TEST
EOl
E02
GNO
(NC : No Connection)
709
,uPD1706G-011
2-2. Pin Description
Pin No.
Symbol
Pin Name
Description
LCD SEGMENT SIGNAL
LCD segment signal output terminals
(LCD of 1/3 duty and 1/3 bias to be used. See note.)
Of power voltages for LCD, intermediate ones are output to
these pins. If these intermediate potentials do not stabilize
when a large-size LCD is to be driven, connect large capa·
Intermediate
22
23
24,25,27 COMO"'2
voltage output
city capacitors between VH, VL and GND.
terminals for LCD
Normally opened.
LCD COMMON SIGNAL
LCD common signal output terminals
Device power terminals
3 V±1 0 % voltage supplied when device is operated.
Power can be supplied to either pin 26 or 58 only.
26
VDD
VDD rise time must be less than 100 ms (0 to 2.7 V).
POWER SUPPLY
Extremely long rise time might result in failure of proper ini-
58
tialization. When VDD does not fall completely to 0 V and
rises again to 2.7 V, reset is not assured. In such a case,
reset must be made from outside using PWR IN terminal.
Key return signal source output terminals for initialization
28
KS9
KEY RETURN SIGNAL
29
KS8
SOURCE FOR
these outputs to terminals KO through K3, make sure that
41
KSO
ALTERNATE SWITCH
diodes for prevention of counter flow are inserted.
KS1
l
KS7
KEY RETURN SIGNAL
Key return signal source output terminals for momentary
SOURCE FOR
switches on key matrix.
diode matrix on key mtarix and alternate switch. To input
(Refer to Key Matrix Configuration of P. 713)
51"'54
K3
l
KO
MOMENTARY SWITCH
KEY RETURN SIGNAL
Key return signal input pins for key matrix. (For details,
INPUT
refer to Key Matrix Configuration on P. 713)
TAPE and RADIO switching signal input terminal.
To be combined with TAPE/RADIO switch of set. Input as
follows:
When TAPE is selected: High level (PLL stopped, time dis-
30
T/R
TAPE/RADIO
SWITCHING INPUT
played)
When RADIO is selected: Low level (PLL operated, time
or frequency displayed)
PWROUT terminal should be directly connected when
RADIO is selected.
P.737)
Note)
710
Recommended LCDs:
EPSON
KT -104
ALPS ELECTRIC CO., LTD.
PAD32901
HITACHI LTD.
LP031-C
(For details, refer to Application on
,uPD1706G-011
Pin No.
Symbol
Pin Name
Description
Input pin for ON/OFF detection of main switch of set.
When main power is to be turned on by PWROUT output,
input high level.
31
PWRSW
MAIN SWITCH ON/OFF
REQUEST INPUT
When it is to be turned off, input low level. When high level
is input, low level is output to PWROUT terminal and PLL
operates. When low level is input, high level is output to
PWROUT terminal, and PLL stops
(For details, refer to
Application on P. 737.)
SW1S
VCO select signal output terminal, and active low output.
SW2S
Since it is N-channel open drain output, external pull-up
32
SW3S
37
FMS
VCO SELECT SIGNAL
resistor is required. Output breakdown voltage is 8.5 V
OUTPUT
maximum.
MWS
LWS
Muting signal output terminal for killing shock noise which
may otherwise be produced when P LL is out of lock.
Active high.
38
MUTE
MUTE OUTPUT
Since it is N-channel open drain output, external pull-up resistor is required.
Output breakdown voltage is 8.5 V max.
For details of timing, refer to Mute Timing Chart on P. 732.
Output terminal for ON/OFF switching signal of main power
of set.
Normally this terminal is used so that main power will be
turned on when this terminal is low and turned off when this
terminal is high. Since it is N-channel open drain output, ex-
39
PWROUT
MAIN POWER
SWITCHING OUTPUT
ternal pull-up resistor is required.
Output breakdown voltage is 8.5 V max.
(For details, refer to Application on P. 737.)
PWROUT terminal varies with the state of PWRIN terminal
and condition of ALARM and SLEEP.
When it varies, however, MUTE signal is always output at
least 250 ms beforehand to minimize power ON/OFF shock
noise.
Buzzer modulation signal output terminal.
Outputs 3 kHz signal modulated by 4 Hz and 0.5 Hz when
ALARM is ON.
40
BUZ
BUZZE R OUTPUT
(For details, refer to illustration shown below.)
Since it is N-channel open drain output, pull-up resistor is required. 125 1245 ms
IS
B U zlllllll mnn mnn
terminal
I
i
3 kHz signal
nmn
I
1s
IIl1lIInmnnmnnmn
I
·1
1s
Crystal connection terminals.
Connect 150 kHz crystal.
49
XI
50
XO
CRYSTAL
Recommended crystals:
• KYOTO CERAMICS
• TOYO TSUSHINKI
KF-38Z
• KINSEKI
P3-150
TQC-122A-7C
711
,uPD1706G-011
Pin No.
Symbol
Pin Name
55
PSC
PRESCALER CONTROL
56
AM
VCO INPUT FOR LW,
MWand SWl
57
FM
VCO INPUT FOR SW2,
SW3 and FM
Description
Outputs signal for switching the frequency dividing ratio of
prescaler (J.LPB556C) in modes (FM, SW2 or SW3) where
pulse swallowing system is employed for frequency division.
Connect this terminal to PSC terminal of the prescaler
J.LPB556C.
The dividing ratio of J.LPB556C is 1/16 and 1/17.
Terminal for inputting LW, MW or SWl local oscillation
outputs.
An AC amplifier is incorporated, and DC should be cut with
a capacitor.
Terminal for inputting FM, SW2 or SW3 local oscillation
outputs frequency-divided into 1/16 and 1/17 by the
prescaler J.LPB556C.
An AC amplifier is incorporated, and DC should be cut with
a capacitor.
Terminal for inputting signal for detecting whether broadcast station has been received during automatic tuning
(automatic up/down).
59
SD
STATION DETECTOR
60
PWRIN
MAIN POWER ON/OFF
REQUEST INPUT
61
TEST
62
63
64
712
DEVICE TEST
TERMINAL
ERROR OUT
GND
GROUND
High level should be input when a station is received.
It must be input in less than 30 ms after frequency dividing
ratio has changed.
(Refer to P. 734)
Input terminal for detecting main power ON/OFF of the set.
Connect this terminal to main power. If this terminal is
LOW, no alarm operation is performed.
Avoid creating contradictory state where PWRSW terminal
is HIGH and PWRPIN terminal is LOW.
When reset is to be made using PWRIN terminal, input high
level after it has been set LOW. This terminal however,
does not accept pulses shorter than 140 J.LS. When reset
is made using this terminal, state of diode switch at initialization is loaded.
Device test terminal.
Normally connected to GN D.
Charge pump output of phase detector constituting PLL. If
divided oscillation frequency is higher than reference frequency, these pins output high level. When it is lower, on
the other hand, terminals output low level.
If they coincide, the terminals enter floating state.
Since EOl and E02 output same signal simultaneously, they
may be connected to LPF (Low Pass Filter) of any of LW,
MW, FM, SW1, SW2 or SW3.
Connect to GN 0 of the set.
,uPD1706G-011
3. KEY MATRIX CONFIGURATION
-
ClK/FRQ
-
SW
-
DIRECT
ME
FM
MW
lW
FAST
UP
DOWN
-
0
1
2
3
KSs
-
4
S
6
7
KS6
-
S
9
• (AM/PM)
ENTER
-
CANCEL
CORRECT
SLEEP
ALARM
~,
- -KSO
-
KSs
-
~,
- I-
,
~ '--
AUTO
/MANUAl
SW1
SW3
BANDO
~
Momentary switch
,
~
Alternate switch
lOCK
24 H/12 H
} Diode matrix
KS9
-
IFO
IF1
BAND1
10 kHz/9 kHz
KO
Switch Connections
Momentary switch
KSm - 4 _ - - - + - - -
Kn
Alternate switch
KSm - - t - - - - t - - - -
Diode matrix
KSm
--_.._---t--
Kn
Kn
or
KSm
-------1-open
Kn
713
,uPD1706G-011
4. DESCRIPTION OF KEY MATRIX
4-1.
Initialization Diode Matrix
Initialization diode matrices are of the following five kinds. All of them are loaded when power is applied
to VDD for the first time (at initialization) or when PWRIN changes from LOW to HIGH.
(1) Switch for setting I F offset values of FM
IFO
IFl
(2) Switch for setting FM band areas (the US., Europe, Japan)
BANDl
BANDO
(3) Switch for setting MW band channel spacing and reference frequency
10 kHz/9 kHz
(4) Switch for selecting SW bands
SW1, SW3
(5) Switch for selecting 12/24 hour systems of clock
24H/12H
These should be set by shorting or opening intersecting points on the matrix with diodes. (on the following
table, "1" means shorting by Diode and "0" means opening.)
SWITCH
FUNCTION DESCRIPTION
Switches for setting IF offset values of FM.
Four different I Fs spaced 25 kHz apart can be set without changing displayed frequencies.
IFl
IFO
IFl
IFO
U.S. band
European band
Japanese band
0
0
10.700 MHz
10.700 MHz
-10.700 MHz
0
1
10.725 MHz
10.725 MHz
-10.675 MHz
1
0
10.650 MHz
10.650 MHz
-10.750 MHz
1
1
10.675 MHz
10.675 MHz
-10.725 MHz
Switches for setting FM band areas.
U.S., European or Japanese FM band can be selected.
Receiving frequency Channel
range
spacing
BANDl
BANDO
BANDl
0
0
Japanese band
BANDO
0
1
European band 87.50-108.00 MHz 50 kHz
1
0
Inhibited*
1
1
U.S. band
Band area
76.1CY'-'108.00 MHz
87.5""107.9 MHz
50 kHz
200 kHz
* Do not set switches as shown, as correct band (area) cannot be set.
Switch for setting MW band channel spacing, reference frequency and frequency range.
Can be set independently regardless of FM band areas (BAND1, BAN DO).
10 kHz/
9 kHz
714
10 kHz/9 kHz
Receiving frequency
range
0
522""1611 kHz
9 kHz
3 kHz
1
530"'1610 kHz
10 kHz
5 kHz
Channel
spacing
Reference
frequency
,uPD1706G-011
Switch
Function Description
Switches for inhibiting receiving bands of SW bands.
Receiving band
SW3
SW3
SW1
SW1
0
0
0
1
1
0
SW1, SW2
1
1
SW2
SW1, SW2, SW3
SW2, SW3
Switch for selecting 24/12 hour system.
24H/12H
4-2.
Display
24H/12H
0
12-hour display (combined AM/PM display)
1
24-hour display
Alternate Switches
The alternate switches are of the following two kinds. These are always switchable.
(1) Switch for switchover between automatic tuning and manual tuning
AUTO/MANUAL
(2) Switch for locking all switches on key matrix
LOCK
Switch
Function Description
Switch for switchover between automatic tuning and manual tuning.
ON .. , Automatic tuning (automatic seek operation)
OFF .. , Manual tuning
Automatic and manual tuning operations are initiated by depressing the UP or DOWN
AUTO/
momentary switch after setting AUTO/MANUAL switch.
MANUAL
(For details, refer to Description of UP and DOWN keys on P. 716)
Even if this switch is changed over to MANUAL during automatic tuning, tuning operation
does not stop. To stop operation on switchover to MANUAL, compose the circuit so that high
level will be input to SO terminal whenever switchover is made to MANUAL.
To prevent accidentally changing receiving frequency or cutting off PWROUT output as
during a recording, set this switch to ON, and all switch inputs on the key matrix will be in-
LOCK
hibited.
ON
.. , Switch locked
OFF ... Normal operation
715
,uPD1706G-011
4-3. Momentary Switches
Symbol
Function Description
Present time and frequency display switching key. This key is enabled only during the radio
ClK/FRO
operating mode. When this key is pushed while present time display is ON, switchover is made
to frequency display. When this key is pushed while frequency display is ON, switchover
is made to current time. display.
Key for setting direct frequency input mode. When this key is pushed during the radio opera-
DIRECT
ting mode, the direct frequency input mode is created, allowing a frequency to be directly
keyed in by 10 keys and the set to be tuned in on the frequency. (For details, refer to Operating
Procedures on P. 720)
Use this key to write a new frequency to preset channel memory. This key is enabled only
during the radio operating mode. Push anyone of the 10 keys in less than five seconds after
ME
push ing th is key, and the frequency being received at the moment can be preset to the preset channel memory corresponding to the key pushed. (For details, refer to the Operating
Procedures on P. 725)
Switches for selecting lW, MW, FM and SW bands. During the radio operating mode, push
lW
anyone of these keys, and switchover will be made to the selected band. If there is a chan-
MW
nel previously written to preset channel memory of the selected band,the set is tuned to the
FM
last received preset channel. If the preset channel memory has no written channel for the
SW
band, the set is tuned to the lowest channel of the band.
(Refer to P. 725)
Ultra fast key for manual UP/DOWN.
FAST
After the UP or DOWN key has been depressed during the radio reception, depress this key
simultaneously, and ultra-fast operation of 125 ms/10ch will take place.
Automatic and manual tuning keys. When these keys are pushed, the following operations
will be performed.
(1) AUTO/MANUAL switch in AUTO position
Pushing the UP key will sustain up-tuning operation in sawtooth mode, whereas pushing
the DOWN key will sustain down-tuning operation.
If high level is input to SO terminal during the period, automatic tuning operation will
stop.
UP
DOWN
(2) AUTO/MANUAL switch in MANUAL position
Each time the UP or DOWN key is pushed, up or down tuning to another channel a
step (channel space) apart will be made.
If the UP or DOWN key continues to be pushed for more than 0.5 second, up or down
tuning will continue at a speed of 125 ms/1 ch until the key is released.
(Note)
Even if the AUTO/MANUAL switch is changed over to MANUAL during automatic tuning, the automatic tuning operation does not stop. To stop the operation on switchover
to MANUAL, compose the circuit so that high level will be input to SO terminal whenever
switchover is made to MANUAL.
716
,uPD1706G-011
Function Description
Symbol
Numeric keys or preset channel memory write/call keys.
(1) As numeric keys (10 keys)
When the present time or alarm time is to be corrected, push the COR RECT key and
then directly key in a desired time.
o
In the direct frequency input mode, a desired frequency can be keyed in directly by these
1
keys.
2
3
(2) As preset channel memory keys
During the radio operating mode these keys correspond to the preset channel memory on
4
1: 1 basis.
5
0
To write
6
In less than five seconds after ME key has been pushed, push anyone of keys from 0
7
through 9, and a new channel will be written to memory corresponding to the key
8
pushed.
9
0
To call
When anyone of the keys 0 through 9 is pushed during the radio operating mode,the
channel corresponding to the key pushed will be called.
Operates as decimal point key or AM/PM switching key.
-(AM/PM)
In, the direct frequency input mode, this key operates as the decimal point key. When time is
corrected during 12-hour display, the key operates as the AM/PM switching key.
(1) Direct tuning
After a channel has been directly keyed in by 10 keys, push this key, and the set will be
tuned to this channel.
ENTER
(2) To correct present time and alarm time
After a desired time has been directly keyed in by 10 keys, push this key, and the time
will be set. In correcting the present time, correction will begin with 0 second when this
key is pushed.
When this key is pushed during the direct tuning, present time correction or alarm time cor-
CANCEL
rection mode, the mode is cancelled. When this key is pushed during an alarm or sleep operation, the operation is cancelled.
Present time correction key.
CORRECT
When this key is pushed while present time display is ON, the present time correction mode
is created. In this case, the LCD presents "CORRECT" display, whereas flashing display of
second stops.
Accepted only when PWRSW terminal is LOW and when ALARM is not ON. When this key
is pushed while there is no "SLEEP" display on the LCD, the set enters the sleep state, and
"SLEEP" display is presented. At this point, the sleep time is set to 60 minutes, and the
SLEEP
PWROUT output will be forced to the OFF state 60 minutes later.
This key can also be used to check the remaining sleep time. When the key is pushed, the
remaining time (in minutes) will be displayed on the LCD.
When the SLEEP key is pushed while the sleep time is being displayed on the LCD, the
sleep time is reduced by five minutes.
When this key is pushed, the alarm time is displayed. Alarm time correction can be made by
depressing 10 keys or AM/PM key while the alarm time is on display.
ALARM
The time on display is set when the ENTER key is pushed. When the alarm time arrives
while "ALARM" display is ON, the PWROUT and BUZ terminals are caused to be ON.
To put out the "ALARM" display, push the ALARM key and then push the CANCEL key.
717
j.lPD1706G-011
5. CONTROL TERMINALS
By terminals PWRIN, PWRSW, PWROUT and T/R, modes are set as shown below.
(In the following table, 0 denotes low level, 1 denotes high level, and X denotes low or high level.)
PWRIN
PWRSW
PWROUT
T/R
X
0
0
0
X
0
0
1
X
0
1
0
X
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
0
1
X
X
Mode
Power ON through alarm or sleep
operation
RADIO
TAPE
Inhibited (When PWRSW is lOW, T/R must
always be HIGH.)
Power OFF for both RADIO and TAPE
Normal operation
RADIO
TAPE
Impossible modes (when high level is input to
PWRSW pin, PWROUT pin always outputs
low level. When PWRIN pin is lOW, do not
input high level to PWRSW.)
Display (Note 1)
FREo.(Note 2)/TIME
TIME
TIME
FREo.(Note 3)/TIME
TIME
(Note 1) FREO. and TIME displays mean the following displays.
TIME: Display of time (present time, alarm time, sleep time)
Display of above-mentioned time or receiving frequency
F REO./TIME:
(Note 2) In alarm or sleep mode, time display is given priority. For example, when the radio is turned on in the
alarm or sleep mode, the channel will be displayed for the first five seconds only and the time displayed thereafter. When the ClK/FRO key is pushed while the time display is ON after the radio has
been turned on, the channel will be displayed for five seconds only and the time displayed thereafter.
(Note 3) In the normal operating mode where the timer is not used, the channel will be displayed while the
radio is ON, and the time displayed during other modes. If the ClK/FREO key is pushed
while the radio is ON, the display will change to time display. The time display will be retained until
other keyes or switches are operated.
718
,uPD1706G-011
6. LCD PATTERN
COMMON LINES
nn
n
00
0
?:?:
1'1.)....
~
a
LCD PATTERN
SEGMENT LINES
8a
7c
7a
6a
5c 5b 5a
3b
4c
4b
4a
3a
2c
2b 2a
1c
1b
1a
7b
9a
719
/lPD1706G-011
7. OPERATING PROCEDURES
7 -1. Station selection
1.
Manual Up/Down
Set the AUTO/MANUAL switch to MANUAL and depress the UP key or the DOWN key.
Continue the depression for more than 0.5 second, and the UP or DOWN operation occurs at a speed
of 125 ms/1 ch or so (Fast feed).
. At this time~ the MUTE of about 60 ms is output by each 1 ch of up or down operation, while
no output is given for the remaining 60 ms. (Intermittent MUTE)(See the description on P. 30.)
D~press the UP or DOWN key and the FAST key at the same time, and the up or the down operation
is executed at a speed of 125 ms/10ch. (Ultra fast feed)
While the ultra rapid feed is under way, the MUTE is being continually output. Release the FAST
key, and the operation of fast feed is restored. If you release the UP or the DOWN key while depressing
the FAST key, the UP/DOWN operation stops.
2.
Auto Up/Down
Depress the UP or the DOWN key while the AUTO/MANUAL switch is set to AUTO, and the frequency shifts to the UP or the DOWN direction by 1 channel stepwise and whether input (high level)
is fed to the SO terminal or not is checked. If there is input, the shift stops at that frequency. If no input
is fed, the frequency continues to shift stepwise.
While automatic scanning is under way, the MUTE output continues to be fed. (As to detailed timing,
refer to the description on P. 31 )
To stop the automatic scanning half-way, depress the UP key, the DOWN key, or the FAST
key.
3.
Direct station selection
The frequency to be tuned may be directly input by 10 key. Depress the 01 RECT key while the
.radio is on, then "01 RECT" is displayed showing that direct station selection can be accepted. Next, input
the desired frequency within the existing band range by the 10 key and the decimal point key. Fianlly,
depress the E NTE R key, and the set will be tuned to that frequency.
In case the input frequency is outside the existing frequency band, "ERROR" is displayed for 5
seconds. Thereafter the frequency to which the circuit was tuned before the DIRECT key was
depressed will be restored. In case, further, the input frequency does not coincide with the channel
frequencies within the existing frequency band, then tuning is made to the freq~ency of a channel
just below the desired frequency.
During the time from depression of the direct key till depression of the ENTER key is depressed, and
while "ERROR" is being displayed, the radio will continue to be tuned to the frequency received just
before the direct key is depressed.
To cancel the direct station selection after depressing the 01 RECT key and before depressing
the ENTER key, simply depress the CANCEL key.
In case, further, you realized an error in the input frequency before depressing the ENTER key,
then depress the DIRECT key for a second time. By doing so, exactly the same state as when you first
depressed the direct key is restored. Thereafter, you may repeat the input of the 'correct frequency.
720
,uPD1706G-011
EXAMPLE 1)
Correct station selection of MW band (Japan)
Key
Frequency
being
received
Display
,MW
-,
~
-;
-,
Cc
522 kHz
Description
The preset 0 ch is being received.
kHz
The direct station selection is started. The
DIRECT
522 kHz
MW
frequency display goes out and "01 RECT"
is displayed instead.
kHz
DIRECT
[J
I
MW
522 kHz
I
Optional frequency is input by 10 key. The
frequency is displayed at the right-hand end.
kHz
,,-,
DIRECT
G
MW
"-'
,,-,,-,
522 kHz
Id
522 kHz
Id.
522 kHz
Id.
kHz
DIRECT
G
MW
"_, '-'
kHz
DIRECT
G
\ENTERI
MW
,,-,,-, C'
IUULI
kHz
11-"-' ,-,
MW
IL/UO kHz
"01 RECT" display goes out and the circuit
1008 kHz
is tuned to 1 008 kHz. The display is shifted
to the right by one unit.
721
j.lPD1706G-011
EXAMPLE 2) A frequency outside the MW (Japan) band is input
Frequency
being
received
Display
Key
1'-' ,-,,-,
, L'
MW
1008 kHz
1008 kHz is being received.
1008 kHz
cuit tuned to 2000 kHz by direct
LI I I
kHz
DIRECT
You would like to have the cir-
, ,-, II ,-,
L'L'
MWC
LI
-, ,-, ri ,-,
MwL '_I L' LI
ERROR
(5 seconds after)
MW
Descri ption
station selection.
kHz
1008 kHz
2000 kHz is outside the MW band.
So, liE R ROR" is displayed.
kHz
, 'I 'I , ,
I L/LI L' kHz
1008 kHz
The original frequency of 1008
kHz is displayed after 5 seconds.
EXAMPLE 3) A frequency other than the channel frequencies in the MW (Japan) band is input
Key
Frequency
being
received
Display
MW
"1 ,-, , I
IL'L/LI kHz
1008 kHz
DIRECT
B080G
MW
IL/2S
Description
1008 kHz is being received.
You would like to have the circuit
1008 kHz
kHz
tuned to 1425 kHz by direct station selection.
1425 kHz does not coincide with
1008 kHz
MW
the channel frequencies. So, the
circuit is tuned to 1422 kHz which
is obtained by disregarding the
lowest unit.
722
j,lPD1706G-011
EXAMPLE 4) Correct station selection within the FM (Japan) band (Fraction of unit are input)
Key
Frequency
being
received
Display
,",-"
-; ,- ,-
MW
FM
'-- -
"
1422 kHz
Band is changed over, cH 5 has
(J L'.L' L'MHz
80 MHz
,-,-, ,--
DIRECT
-' -'
been
preset
on
the
last preset
memory of FM band.
[&ffi
FM
1422 kHz in MW frequency band
is being received.
kHz
,-, ,-, ,-,
Description
You would like to have the circuit
80 MHz
MHz
,-,,-
tuned to 85.15 MHz by direct station selection.
DIRECT
FM
Input the decimal point, and the
80 MHz
L'_'.
MHz
display is shifted to the left.
The fractional units are input one
DIRECT
FM
,-,e
IL
, I _'. I:J MHz
after another beginning from the
80 MHz
tenth unit.
After two fractional
units are fed, the 10 Key is rejected.
FM
IENTERI
,-,,- ,,-
L'_'.
, - ' MHz
"Direct" display goes out, and the
85.15 MHz
circuit is tuned to 85.15 MHz.
723
j.lPD1706G-011
EXAMPLE 5) Correct station selection within FM (Japan) band (in case fractional units are not fed)
Key
Frequency
being
received
Display
FM
Lilli-I
L/.J. 1LI MHz
85.1 MHz
FM
85.1 MHz within the FM band is
being received.
DIRECT
FM
Description
You would like to have the circuit
0"
LII_I
85.1 MHz
MHz
e", 1-' ,-,
LI L/.I_'I_'
tuned to 80 MHz by direct station
selection.
"01 RECT" display goes out, and
MHz
80 MHz
the decimal point and "00" are
indicated at the fractional units
and the tuning is made to 80 MHz.
(Caution)
With regard to the FM and SW bands, the fractional units of the frequencies are displayed together
with the decimal point in terms of MHz.
In respect of the LW and MW bands, the frequencies are displayed in terms of kHz without the
indication of fractional units.
quency.
724
So, the decimal point key is rejected when you are selecting a fre-
j.lPD1706G-011
4.
Preset channel
The preset channel is based upon random preset system, and a total of 10 stations can be preset.
Each of the 10 keys 0"'9 corresponds to each of the memories.
o How to preset
Depress the ME key while the frequency is being displayed, and "ME" is shown.
5 seconds, the "ME" indication goes out and the original state is restored.
After about
Depress one of the
keys 0"'9 as required while the "ME" indication is on and the frequency under reception is preset
on the channel corresponding to the depressed key. Then the "ME" display goes out and the preset
channel number is displayed instead.
o Preset channel calling
Depress the required key while the radio is on, and the corresponding preset channel is selected
and the circuit tunes to the frequency of that channel.
In case the frequency band of the required preset channel is different from that of the channel
under reception just before the selection is made, then the band is also changed over automatically.
5.
Last one memory
This memory is used when the radio power supply is disconnected. When the power supply comes on
again, the circuit is tuned to the same frequency as when the power supply was cut off.
6.
Last preset channel memory
This memory is used when the bands are changed over. If there exists a frequency already written into
the preset memory within the frequency band when the band is selected, the circuit will be tuned to the
preset channel within the band being received just before the band is changed over. In case the frequency
within the band is not written in the preset memory, the tuning is made to the lowest frequency within
the band.
725
j.lPD1706G-011
EXAMPLE)
Band selection
Display
Key
Description
III II I I
MW
~
kHz
11-'
IU
MW
FM
1008 kHz of MW band is being received by the preset
IULlel
1/
I I
channel (2 ch).
The frequency is shifted upward by one step and 1017
kHz is received.
kHz
DC In
The FM band is selected. The preset channel within the
U -'. I L/MHz
[M]
FM band received at the last reception (1 ch) is called
out.
The MW band is selected. The preset channel received
E1
III ,-, 0
MW
LW
726
at the last reception (2 ch) is called out. (Note: 1017
IUL/LI
~
kHz which was received at the last reception within the
kHz
'5- -'::J
,-
MW band is not called out as it was not preset.)
The LW band is selected. No frequency is preset in LW
kHz
band. So, the lowest frequency is called out.
jlPD1706G-011
7-2. How to adjust the current time
The current time may be changed only when it is being displayed. To change it when the frequency is
shown, first depress the CLK/F RQ kt;y so that the time is displayed.
Next, depress the COR RECT key, then the time display goes out and "COR RECT" and ":" (colon) are
then displayed, and the flashing of the seconds is interrupted. (In the case of a time display of a 12-hour
system, AM or PM is also displayed.)
Input the required time by 10 key. In the case of a 12-hour system time display, AM and PM may be included by the AM/PM key.
Depress the ENTER key after the input of the new time has finished and the newly set time is displayed.
The flashing of seconds is also restored, starting from zero.
In case the input time is not correct, or in case a wrong key (i .e., any key other than 10 key, AM/PM key
and CANCEL key) is depressed, "ERROR" is displayed for 5 seconds and the frequency shows while the
radio is on. In other cases, however, the time is displayed. If a mistake is made, there is no need to adjust the
time since the mechanism continues as normal.
To cancel the change of the time display after depressing the CORRECT key, you should again depress
the ·CANCE L key. No time adjustment is necessary.
EXAMPLE 1) How to adjust the current time (in the case of a 12-hour display system)
Key
Display
MW
rcLYJ
~
Description
/11/10
IL'L'LI kHz
,.,- ,,, I':J
'-'
AM
:fgfl':
Radio is under operation (1008 kHz within the MW
band is being received)
Current time is indicated. (by 12-hour system)
Second is flashing.
I, \' "
I I
CORRECT
AM
(OHR[CT
The correction of current time starts. The time display goes out and "COR RECT" is indicated.
CORRECT
,
,
-'-'
AM
The time is fed by 10 key. The display is at the right
hand end.
CORRECT
,-; c
AM
The numerals are shifted by one unit to the left.
'::' J
(Note)
When the input contains 4 or more digits only 1 or 2 is
CORRECT
1./- I
-,.~
,-
AM
displayed at the uppermost unit.
727
j1PD1706G-011
Key
Display
Description
-,--. -'-,.
.J'_' C
PM
Change AM/PM .
-,J:~C
PM
The 0 second starts at the time when the ENTE R key is
CORRECT
depressed and the second start flashing.
(Note) In the sequence described above, an optional order may be selected between the work of time input
and that of the selection between AM/PM.
EXAMPLE 2) In case erroneous time is fed. (in a 12·hour display system)
Description
Display
Key
, ,,=
FM
L' _'.
,
Radio reception is under way. (85.1 MHz
I
MHz
~
, ,. ,,,I I
ffi
I'
~
is received by the preset 5 ch within FM
band)
PM
~~:
The current time is being displayed. (12hour system) . The second is flashing.
CORRECT
I -,.,-, II
I -",_, LI
PM
The time is supplied by 10 key.
CORRECT
I _,.,-, ,-,
I _"LI LI
PM
13:00 in a 12-hour system is an erroneous
time. So, "ERROR" is indicated.
ERROR
FM
(After 5 seconds)
"C I ,-,
L/_'. ,,_, MHz
[M§J
As the radio reception is under way, the
frequency
display
is
restored
after
seconds.
(Note) In doing this, the time before depressing the CORRECT key is maintained in a correct manner.
728
5
/1PD1706G-011
7-3.
1.
Alarm operation
How to enter the alarm time
The alarm time may be corrected only when it is being displayed. Depress the ALARM key. The
alarm time and "ALARM" are then displayed after 5 seconds or so. (The second does not flash.)
Depress the 10 key or the AM/PM key while the alarm time is displayed, and the alarm time correction
mode is obtained and "COR RECT" is displayed.
Depress the ENTER key after finishing the time input. When the radio is on,. the frequency is
displayed. In other cases, however, the current time is displayed. At the same time "ALARM" is
displayed.
EXAMPLE 1) Change of alarm time (12-hour display system)
Key
Display
Description
,,-, ,-, CJ
'L"_" ,
MW
~
kHz
ALARM
Alarm time display.
I _",-, ,-,
IALARMI
AM
IL 'L' L'
ALARM
1008 kHz within MW band is being received by preset
channel 2 ch.
CORRECT
,-
"ALARM" is lit.
Second does not flash.
Depress the 10 key (or AM/PM key) within 5 seconds
AM
,:I
after depressing the ALARM key, and the alarm time
can be changed. At the same time, "CORRECT" is
displayed.
ALARM
COR RECT
,- , - -
_'_ I I
AM
'-" _, L'
ALARM
MW
left stepwise every time you feed one unit.
, ,-, ,-, n
Depress the ENTER key, and the alarm time is set to
6:50AM. The frequency is displayed when the radio
"_, L" ,
[M1]
The time is displayed on the right side and shifts to the
kHz
is on. And the "ALARM" display is left to be lit.
729
,uPD1706G-011
2.
Alarm operation
When the alarm time coincides with the existing time during "ALARM" is displayed, the alarm becomes
ON.
In other words, the PWROUT terminal comes to low level and the BUZ terminal is set on.
The pulse of 3 kHz modulated by 4 Hz and 0.5 Hz
the BUZ terminal output chart on P. 8.)
is output from the BUZ terminal.
(Refer to
However the alarm operation is not made if the PWR IN
terminal is at the low level.
In case the T/R terminal is at the low level when the alarm becomes on the radio is actuated at the
same time and the last channel is called out.
In case any key is not operated after actuation of the alarm, the alarm goes off after 120 minutes. In
other words, at this time, the PWROUT terminal comes to high level and the BUZ terminal comes to
low level. If the radio has been selected, it also stops.
In case you would like to stop the alarm before 120 minutes elapse, invert the input of the PWRSW
terminal, and the alarm goes OFF. Also you may stop the alarm by depressing the CANCEL key.
While the alarm is on, the time display has priority. If, therefore, the radio is on in the 120 minutes
while the alarm is set (T/Ff terminal is at low level) and the keys related to the radio (including ClK/FRQ
key) are depressed and the frequency is displayed, the time display is restored after 5 seconds or so.
If the ME key is depressed while frequency is displayed, "ME" and frequency are displayed for the
f1rst 5 seconds, and the frequency is further displayed for 5 seconds after "ME" goes out.
3.
Alarm timer set off
While "ALARM" is displayed, the alarm is always set when the alarm time corresponds to the
current time. (Provided, however, the PWR I N terminal is at the high level.)
To eliminate the "ALARM" display, depress the CANCEL key within 5 seconds after depressing
the ALARM key. In other words, by depressing the CANCE l key while the alarm time is displayed,
the "ALARM" display goes out and the alarm operation is not actuated even when the alarm time
coincides with the current time.
4.
Alarm timer settiAg
To see the alarm time, depress the ALARM key. In case, you would like to actuate the alarm at
that time, depress the ENTE R key within 5 seconds after depressing the ALARM key. In other words"
by depressing the ENTER key while the alarm time is displayed, "ALARM" is displayed and the alarm
is actuated when the alarm time coincides with the current time.
PWRIN terminal has been at the high level.
730
It is necessary, however, that the
,uPD1706G-011
7 -4.
1.
Sleep operation
Sleep time setting
The sleep timer is of such a structure that the power is supplied only during the set time, while the
power supply is turned off at other times. The sleep time is divided by 5 minutes intervals and the maximum set time is 60 minutes.
Depress the SLEEP key, and the sleep timer is set and "SLEEP" is displayed. However, this only occurs
when the PWR I N terminal accepting the sleep key is at the high level and the P.WRSW is at the low level.
Further, the alarm timer has priority over the sleep timer. So, the SLEEP key is rejected while the alarm
timer is on (PWROUT terminal is at the low level).
"SLEEP" is displayed while the sleep timer is in operation and the radio is operated when the T /R
terminal is at the low level.
If the sleep key is depressed while "SLEEP" is displayed, the remaining time of the sleep timer is
displayed. If the sleep key is again depressed while the indication of remaining time of the sleep timer is
displayed, the sleep time is reduced by 5 minutes.
EXAMPLE)
How to set the sleep time
Key
Indication
-',U
MW
[0]
PWRIN terminal = High level
8'
I' 'L
SLEEP
Description
PM
~
::~;
,,-,,-, n
""1"
-
PWRSW terminal = Low level
T/R terminal = Low level
Current time is displayed.
Sleep timer is set on and "SLEEP" is displayed. By doing so, the sleep time is set to 60 minutes and the last
kHz
channel is called out.
The remaining time of the sleep time is displayed (in
SLEEP
e"
au
terms of minutes). After 5 seconds, the frequency is
displayed if the radio is in operation. In other cases,
the time display is restored.
SLEEP
Depress the SLEEP key within 5 seconds after the operation described al:iove and the sleep time is reduced by
5 minutes.
SLEEP
(After 5 seconds)
MW
[M]
2.
5 seconds after depressing the sleep key, the frequency
, " 1-' 1-:1
I tJ I_II ,
is displayed when the radio is in operation. In other
kHz
cases, the time display is restored.
Suspending sleep operation
To suspend the sleep operation while the sleep timer is set, either depress the CANCE L key or set
either depress the CANCE L key or set the PWRSW terminal to high level.
Note: The alarm timer has priority over the sleep timer. So, when the alarm timer is actuated while the
sleep operation is under way, the sleep operation is suspended at that time.
731
,uPD1706G-011
8. MUTE TIMING
8-1.
1)
Preset channel calling
In case VCO is not changed over
30 ms
30 ms
375 ms MIN.
~----~I
f
·1
MUTE ______
Key
2)
t
Change of frequency division ratio
In case VCO is changed over
30 ms
30 ms
30 ms
I.MIN·.I. MIN .•
MUTE ______
~----~I
t
Key
1. MIN .• 1.
t
375 ms MIN.
..I
t
VCO change over
Change of frequency division ratio
8-2. Direct selection
I'"
30 ms
150 ms MAX. _I_ MIN.
"I"
MUTE ______~----------~
375 ms MIN.
t
Change of frequency division ratio
ENTER key
8-3. Manual UP/DOWN
1)
1 channel UP/DOWN (In case VCO is not changed over)
I"
MUTE
MIN ...
I.
_.,....--~I
t
Key
732
30 ms
30 ms
30 ms
MIN ... I.MIN· ..
t
I_
450 ms TYP.
-I
I.....-.------Inl--------
Change of frequency division ratio
j.lPD1706G-011
2)
1 channel UP/DOWN (In case VCO is changed over)
30 ms
MIN.
I•
-I-
-I-
I
MUTE
t
30 ms
MIN.
t
-I-
400 ms MIN.
-I-
I'
((
450 ms TYP
I
-I
n
t
VCO
Change of frequency division ratio
Key
3)
30 ms
MIN.
Rapid feed UP/DOWN
30 ms
60 ms
450 ms TYP.
MIN.
MUTE _.,-_ _...,,1
t
Key
_I~l ~___-----,I
1 I
I I---_____
I n case VCO is not changed over.
As to details. refer to the following charts.
Change of frequency
division ratio
a) In case VCO is not changed over
30 ms
I_ MIN .•
-----.II
30 ms
1 ..
MIN .•
j
I
,
__ _
Change of frequency division ratio
b) In case VCO is changed over
30 ms
30 ms
I.. MIN··I .. MIN .• / ..
t
VCO change over
375 ms MIN.
-I
t
Change of frequency division ratio
733
jlPD1706G-011
4)
Ultra rapid feed UP/DOWN
60 ms
450 ms
MAX .
30 ms
MIN. 120 ms TYP.
• ,- .,..
30 ms 60 ms 60 ms
120 ms TYP. MIN. TYP.
TYP.
., ... ,....I -I
·1"
1
Ck:dJl""""--
J-------.jl ~
MUTE _ _.....I
Change of frequency division
ratio for 10 channels
Change of frequency division
ratio for 1 channel
_-+-+-1- 65 ms
MAX.
_____
FAST key
8-4.
~/
\ ..
FAST MODE
.~_ _ _ _ _ _ __
Auto UP/DOWN
30 ms
I_MIN .•
30 ms
30 ms
I... MIN ... I_ MIN ... I_ MIN .• I.
~I
MUT_E
30 ms
t
30 ms
MIN ....
30 ms
30 ms
30 ms
•
t
+
•
SO
SO
SO
SO
Note) StD indicates the timing of SO terminal check.
Frequency band change-over
30 ms
,. MIN.
...I
30 ms
MIN.
..I. . I..
30 ms
MIN.
MUTE
t
Band key
734
t
VCO change over
30 ms
375 MIN.
1,,-----
t
Check that either SO = High
or UP key. DOWN key.
or FAST key is depressed
for the secondt time.
Change of frequency division ratio
1
30 ms
1... MIN ... I.. MIN ... I.. MIN. "I_ MIN .• 1" MIN. "'1" MIN .• 1
Key
8-5.
30 ms
·1
,uPD1706G-011
8-6.
Change-over from Tape to Radio
\
..
375 ms MIN.
I•
375 ms MIN.
..\
MUTE
t
J-____________________________________________________________________________________
PLL operation starts
T/R
8-7.
~~:~~x:
~
Change-over from Radio to Tape
375 ms MIN.
IMUTE
1 ms TYP.
5 ms MAX.
-, L,.
pLL operation stops
I
TIR
8-8. Power Supply Switch Operation
(The Power supply ON/OFF operation by Alarm/Sleep operation is also in the same timing.)
1)
PWRSW OFF -+ ON (Low -+ High) (Tape)
1mSTYP.=:tt==
PWRSW
5msMAX·_
1
MUTE
---~I~·======·~T·======~·I~-_
375 ms MIN.
375 ms MIN.
_
PWROUT
T/R
"High"
125 ms
BUZ
_____
(whenalarmisactuatedl
125 ms
-'1111111111111111111111111...0------1 11111111111 IIIIIIIIIL
~
3 kHz
~
3 kHz
735
,uPD1706G-011
2)
PWRSW ON
~
~
OFF (High
~·I~I--·-
PWRSW
Low) (Tape)
ms TYP.
5 msMAX.
1
___________~IP~----------3-75---m-s-M-I-N-.---------.-I-.--------3-75---m-S-M-I-N-·---------~~I____________
MUTE
I
PWROUT
Tiff
"High"
3)
PWRSW OFF
PWRSW
MUTE
_
~
ON (Low
~
r"-
_ _ _-=-'...
·..;-1
.
High) (For radio)
TYP. '
51 ms
msMAX.
P---------------------------------------------------~
375 ms MIN.
375 ms MIN.
30 ms i
MIN.
T
PL L operation starts
PWROUT
Tiff
Note) When the TAPE/RADIO select switch is thrown to the RADIO side, it is interlocked with PWROUT.
4)
PWRSW ON ~ OFF (High ~ Low) (For radio)
PWRSW
MUTE
-
~·'~I--"
1
ms TYP.
5 ms MAX.
~1..
----------37-5-m---s-M-IN-.----------.-I-.---------37-5-m---s-M-IN-·----------.~I_________
P L L operation stops
~r----------------------------
PWROUT ________________________________~I
T/R
736
jlPD1706G-011
9. EXAMPLE OF APPLIED CIRCUIT
LCD
III
COMO 1
K3
2
la
I
I
I
I
I
I
9a
K2
Kl
I
l..------f KO
f--
KSO
f--
KSl
SO
r - KS4
MATRIX
r - KS5
f--
KS7
f--
KSS
I
Station
t - - - - - - - - - - - - - - - - - detection signal
'"'0--.--------------- Buzzer
AM ~----+--~::r-------~
0.001 ~F
PSC
t-t-~---------,PSC
~PB556C
VCCIN
r-- KSg
Lower tha n S.5 V
EOl
FMS
RELAY
r -I
I
I
I
•~
()
(
/vcc
I
~
-MWS
(R
I
__ .J
U?>TO-R-+----II---.->--~:~~~~~---~lJ--+-3-V-+~-1O-o/c-O...,->--i
.....
LWS
t---t--~~-
VCO LOW
output
VCC~
LPF IN
I
/
/
-=-
/
~P01706G
Back -u p battery
I
-011
20 pF X 2
/
/
XIt-t-+----+--~~'~vA~
/
::!::/'
~-1---~""r '"'o-~/~,-~_.~PWRSW
r
VCO LOW
E02
VOO
VCOHI
output
VCCI-
--
T/R
IT "\
t -.....--+-+--
SW2S
SW1S
J,
:f
VCO HI
SW3S
OUT
-,
I
I
I
--
PWR
I
LPF IN
RELAY DRIVER
output
FM t-t-+-----~II~---~
0.001 ~F
OUT
KS6
f--
I
BUZ t-t---<'"'T
KS3
KEY
I
I
I
I
MUTE r . - - - - - - - - - - - - - - - - - M U T E
output
BUZZER SW
r - KS2
f--
l-
I
POWER SW/
/
/
/
7,'r7
/
17
<
I
PWRIN
\
,
T
150 kHZ:
I---77
L--1
Lower than 3 V
,
XO
TEST GNO
7fT
"R
)...
~
0
T
737
1. ALPHA-NUMERICAL INDEX
2.
QUICK REFERENCE GUIDE
3. CROSS REFERENCE GUIDE
4. MAINTENANCE AND OBSOLETE TYPES
5.
GENERAL STATEMENT
*
NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
o History
0
Types and Features
o Type Number Designation
*
*
*
*
Device Technoiogies
STANDARDS OF If'JTEGRATED CIRCUITS
HINTS ON CORRECT USE
TECHNICAL SYMBOLS AND TERMS
RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
'7
I.
0
6 -1.
CAR AUDIO
6-2.
HOME AUDIO
6-3.
PORTABLE AUDIO
TV APPLICATIONS
8. DIGITAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11. ARRAYS
12. OTHERS
13. APPLICATION NOTES
CLOCKS & WATCHES
INDEX
Page
J.lPD832G
3.5 Digit LCD Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
742
J.lPD833G
3.5 Digit LCD Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .•
742
J.lPD2006G
3.5 Digit FIP/LED Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . ..
771
J.lPD6529C
Automotive Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
787
J.lPD1990AC
Serial I/O Time Keeping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
792
J.lPD6517P3
3.5 Digit Multiplex LCD Quartz Watch . . . . . . . . . . . . . . . . . . . . . . . . . 805
•
741
MOS DIGITAL INTEGRATED CIRCUIT
J-lPD832G,J-lPD833G
a-CHANNEL DIGITAL LIQUID CRYSTAL DISPLAY,
TIMEPIECES AND TIMER CIRCUIT WITH 4MHz OR
32kHz CRYSTAL OSCILLATOR OPERATION.
GENERAL DESCRIPTION
The pPD832G and pPD833G are CMOS LSI operating at the reference frequency of either 4.2 MHz or 32 kHz
crystal oscillation, for use as mUlti-purpose electronic timepieces (clock & watch) and timers of 4-digit liquid
crystal display type.
Composition of 8-Channel Digital Timepieces (clock & watch) and Timer
1.
Standard time
2.
Alarm timer
3.
Snooze timer
4.
Sleep timer
5.
Control timer
6.
Dual time
7.
Stopwatch
8.
Counter
FEATURES
742
1.
Hours, minutes, seconds, AM and PM can be displayed.
2.
Selection of either 12-hour or 24-hour display format is possible.
3.
I nstantaneous second correction is possible within an error of ±30 seconds.
4.
Minutes and hours can be set independently. (at 1 pps or one push per one word step.)
5.
That the tens digit of minutes, AM and PM can be set independently for alarm time (or control time)
or dual time is very convenient.
6.
Provided with a fine alarm tone.
7.
Alarm timer offers the 4-minute duration alarm. By using the SNZ (snooze) terminal, the timer
can offer the alarm every four minutes through the CANCEL-REFRESH method.
8.
The trial sounding of alarm can be made.
9.
The duration of control timer and sleep timer can be set in four ways at 15 minutes, 30 minutes,
60 minutes and 120 minutes.
10.
The application as an multi-timer is possible with its two-phase control timer signal.
11.
Since the dual time is available, it can be used as displaying second time zone or elapsed time.
12.
The stopwatch can count up to 24 min.
13.
The counter can count up to 1440 counts.
,uP 0832G,,uP 0833G
14.
All memory sections excluding the LCD driver section with VSH series (3.0 to 6.0 V) are composed of
VSS series. Thus, the system design is very simple with this device.
15.
The source voltage for the alarm out, control out and sleep out terminals is variable from 1.5 to 6.0 V
through the employment of open drain P-channel transistor.
16.
(i) Standard time, dual time, and sleep timer or (ii) Standard time, stopwatch and sleep timer can be
used in parallel independently.
APPLICATIONS
o 0 ig ita I alarm clock
o Sleep timer
o Snooze timer
o Traveller's watch
o Appliance timers
o Measuring timer for the distance covered
o Clock and watch displaying different time zone (World time)
o Sequential controller
o Desk timer
o Portable timer for miscellaneous controls
TYPES
Type No.
Frequency of the crystal
pPD832G
4.194304 MHz
pPD833G
32.768 kHz
BLOCK DIAGRAM
.--------0
12/24 0 - - - - - - - - - - - - - - - - - - - - - - - - ,
COM
1,-1.
0----------,
STANDARD
TIME
~----o
AM(S)
~----o
PM(ADEG)
1 - - - - - - 0 h(C)
TST,
~----o
SEC
8
Fs
a,-g,
I-----~ COLON (COM)
.-l
~-----<>
a2-g2
~----.
co
Q.
(f)
:.0
I
I
.~
(f)
(f)
':::J
':::J
0
I
I
(f)
(f)
(l)
c
c
Automatic setting signal at 1Hz rate
or
{ One push one word signal
Set the terminal F H "ON"
[
Repeat the
J
o~N ~ OFF operation
0
'0
'0
AM/PM
[IJ
,-----
Keep the terminal Fs
set to ON
=>
f--
Fig.6
* An example of the setting of hours is given below for 12-hour indication.
Presuppose the display of hours is AM 11 and you want to correct it to AM 10. Fist, make the setting
so that the display of hours becomes 10 in accordance with method 1 above. In this case, the display AM
is shifted to FM with the overflown hours. This can be neglected. Then, set the display to AM in accordance with method 2 above. Through this operation with automatic setting signal at 1 pps, hours can be
set within 13 seconds, in case where there is no erroneous setting. With the one push one word signal,
hours can be set to the desired figure with in 3 seconds.
As explained above, the setting' of alarm time or control time for an electronic instrument requires only
7 seconds to complete even in the case of the longest set span.
3.
Relationship between Ordinary Expression of Time and Expression of Time for J.lPD832G Series
The time can be displayed with pPD832G series either by 22-hour indication or by 24-hour
indication. Table 1 shows the relationship between ordinary expression of time and expressions of times
in 1-hour indication and 24-hour indication of J.lPD832G series.
Relationship between ordinary expression of time and
Expressions of times in 12-hour and 24 -hour Indication
Ordinary expression
of time
Forenoon
Afternoon
12 hours format
12 : 00AM-11 : 59AM
12 : 00PM-11 : 59PM
24 hours format
0: 00
-11 : 59
12: 00
-23 : 59
755
f.-l? D832G, JlP D833G
Ordinary
expression of
time
12 hours format
24 hours format
Twelve O'clock One 0' clock
midnight
o : 00
One O'clock
Two O'clock
in the
afternoon
afternoon
1: OOPM
13 : 00
in the morning in the morning
12 : OOAM
in the
Two O'clock
2 : OOPM
14: 00
Eleven
O'clock
Twelve noon
in the morning
1 : OOAM
2: OOAM
11 : OOAM
12:00PM
1: 00
2: 00
11 : 09
12: 00
Three
O'clock
in the
afternoon
Eight
O'clock
in the
afternoon
Eleven
O'clock
in the
afternoon
3 : OOPM
15 : 00
8: OOPM
:20 : 00
11 : OOPM
23 : 00
Twelve
O'clock
midnight
12 : OOAM
0: 00
Table. I
4
Trial Sounding of Alarm Tone
Since the alarm time is set in accordance with methods 1 through 3 above, the alarm tone begins
to be generated immediately from the terminal ALM OUT when the display corresponds to the present
time of standard time in the course of setting of the hours with the terminals FM, FH and FS. At this
time, control signal (VDD level) is also present at the CONT OUT terminal. But, in the course of further
setting, if the display is deviated from the present time, the alarm tone stops sounding, and, at the same
the control signal is also off.
On the contrary, with alarm time (or control time) fixed, if the standard time is set through the
operat,ion of the terminals FM, FH and FS, the alarm tone begins to sound when the display corresponds
to the alarm time fixed, and stops sounding when the display deviates from the alarm time fixed. This
operation can be applied also to the control signal.
Such sounding of alarm tone as explained above may be called a very convinient trial sound of
alarm.
* I n other words, when the alarm is generated (at the same time, the control signal is also generated,)
the alarm output (or control signal output) can be cancelled before the duration ends through the ON
operation of the terminal FM or FH.
The cancellation of alarm tone is effective with the terminals FM and FH of either standard time
or alarm timer.
The terminals FS can generate alarm tone (or control signal) when the two hours correspond, but
can not cancell the alarm tone (or control signal). There are the cases where the alarm tone (or control
signal is off at the end of the duration brought by the carried minutes display when the time is between
30 and 50 minutes.
5.
Setting of Alarm Time (or Control Time)
The alarm time (or control time) can be set to the any hours at an interval of one minute (resolusion: 1 minute). Once the alarm time is set, the alarm tone (or control signal) can be obtained every 24
hours at the preset time.
6.
Durations of Alarm Tone or Control Signal
When the time of the alarm tone (or control signal) corresponds to the hours of standard time,
the alarm tone of 2048 Hz frequency modulated by 8 Hz frequency is emitted every other second. The
duration of alarm tone is 4 minutes. The alarm tone stops automatically at the end of duration and
starts again at the same hours after 24 hours. The output waveform of the alarm tone is shown in Fig. 7.
756
JLPD832G,JLPD833G
I
Actual time
The desired alarm time
• IL--___________
ALM OUT --~rlt-'- - - - -.. . .
o
2
3
4MIN.
2048 HZ
---HActual
Alar m Tcne - - { f - - . . 1 UUI L..-J,UU~--' ~'u L......IU LJ '--J UUIL...-IIUU I........IUU L-...IUUI ' - -_ _ _ _ _ _ _ _ _ _ _ _ _- - ' LJU 1......1 UUL-...1 U UIL...-I uu , _
from the terminal
ALM OUT.
f-------1
I
sEc _ _ _ _ _-oa--rI__
· - - - - - - 1 SEC _ _ _ _ _----l
o
Fig.7
On the other hand, the control signal is present at the terminal CNT OUT. As shown in Table 2,
there are four types of control duration, 16-minute, 32-minute, 64-minute and 128-minutes-durations.
One of the four control durations can be selected in combination with the input terminals 60/30 and
60/120. Therefore, with those control signals, the recording is possible for 15-minute audio cassette
tape to 2-hour video tape.
Terminal 60/30
L
H
L
H
Terminal 120/30
L
L
H
H
Duration (MIN)
64
32
128
16
L = VSS level
H
= VDD
level
Table 2
The relationship between the output waveforms at the ALM OUT and CaNT OUT is shown in
Fig. 8. In this case, the terminal SNZ is not operated. When the duration of control signal ends, the
control signal stops and does not start again until the pre-set time reaches after 24 hours.
Actual time
!
I
The desired control time
L__
CNT OUT
Actual time
I
L__
t
16MIN. 32MIN.
64MIN.
128MIN.
~________ J~__________________________________________________
Set
to ON 'im"itan,o",'y
~rl~
ALM OUT
t
4MIN.
L
~
10MIN.
The desired alarm time
Keep the terminal SNZ to OFF
Fig.S
757
,uP D832G,,uP D833G
7.
Relationship between SNZ Terminal and Alarm Tone (Control Signal)
When the hours of standard time corresponds to the pre-set hours for the alarm time, the alarm
tone (or control signal) is generated. The alarm is automatically off in four minutes. The control signal
is off at the end of pre-set duration (15 minutes, 30 minutes, 60 minutes and 120 minutes). If you want
to take a snooze while the alarm tone is on, set the terminal SNZ to on, then, the alarm is simultaneously
off. The alarm tone is on again after 4~~ minutes from the OFF operation of the terminal SNZ. The
operation of the terminal SNZ to stop the alarm tone and start it again three or four minutes later as
explained above is referred to as the cancel-refresh method.
The duration of cancel-refresh operation of alarm tone is extended every terminal SNZ operation.
Even though the cancel-refresh method is employed, the alarm tone is not on again if it is lasts fully for
four minutes.
The cancel-refresh method is to be applied to the protable alarm timer (or traveller's watch) with
its built-in IlPD832G series which is expected to be commercialized in feature for the purpose of preventing the battery from dischargir:'g uselessly while the user keeps the timer away, levaing it on.
The relationship in operation between the terminals ALM OUT and SNZ is shown in Fig. 9.
The desired alarm time
tr--4MIN.~
ALMOUT
[
SNZ
--11i------'
L - -_ _ _ _ _ _~fl~
t=3-.4 MIN ----i
t==3-4 MIN - - t -t-'>-----::-4 MIN.---j
nL-___~r-_-o_0__0----1,
SNZ
_ _. . .1
. 1 ~ 0
----t--~n
ALM OUT
____~rl______~~________________rr===---o-3---;-MIN-·-o~I~'----4-M-IN-~--~~
SNZ
------t--------~------------------~I~-----------------------------
ALM OUT
(
________________________
(
ALM OUT
SNZ
L-
n~__~rr~__________________
_--JnL-___-t-r_o_3_-~_M,_N~___'1l 1==3-~"'"-+---4MINL
In
(
°
nJ
n
1MIN.
f---l
CNT. OUT
I
Jf
Fig 9. Relationship in operation between
the terminals ALM OUT and SNZ.
Even though the control signal from the terminal CNT OUT is not off through the ON operation
of the terminal SNZ, the duration of control-signal is extended. I ri other words, the ON operation of the
terminal SNZ resets the duration circuit for the control signal. From the instance the terminal SNZ is off,
the counting of control signal duration starts. The counting is effective up to 16~~ minutes for the 15minute duration, 32~~ minutes for the 30-minute duration, 64:..9 minutes for the 60-minute duration
and 128~~ minutes for the 120-minute duration.
Fig. 10 shows the relationship in operation between the terminals CNT OUT and SNZ on the
basis of 32-minute duration. As can be understood from the figure, the duration of control signal can
be extended through the ON operation of the terminal SNZ.
758
,uP D832G,,uP D833G
The desired control time
t
f---32
CNT OUT
[
SNZ
---1l
CNT OUT
[
SNZ
I
MIN
-1
.1
Tilis diagram is drawn by the basis of 32-MIN duration.
nL-.--p-3'-_3-2M-IN-.
-j----
1
• • • 1_ _ _ _ _ __
----+-j
.--------.I~_
---J
F
31-32""·---j
.
CNT OUT
.
.IL--___
[
SNZ
ALM OUT
____
~nL__
_____________________________________
t4MIN
Fig. 10. Relationship in between the terminals
CNT OUT and SNZ.
8.
Stopping the Alarm Tone (or Control Signal)
When you need to stop and clear the alarm tone (or control signal) completely, set the terminal
ACS to ON.
If the terminal ACS is off after clearing the alarm tone (or control signal), it is on again at the
pre-set hours after 24 hours.
* If the alarm tone (or control signal) is not required every 24 hours, proceed with the following
steps.
1.
Disconnect the terminal ALM OUT from the alarm tone source.
2.
Set the volume of alarm tone to the minimum.
3.
Disconnect the terminal CNT OUT from the controlled electronic instrument.
4.
Keep the terminal OUT set to VDD level.
.......... I n this case, the memory operates as dual time.
5.
Keep the terminal STW set to VDD level.
.......... In this case, the memory operates as stopwatch.
* While the sleep timer is in use, the alarm timer can not be used. (In this time, the control signal
is also on from the terminal CNT OUT.) I n other words, while the sleep timer is in operation, the alarm
timer does not emit the alarm tone even though the pre-set time corresponds to present hours.
6-4.
Snooze Timer
When you want to take a snooze a little longer after the alarm tone starts, set the terminal SNZ
to ON. Then, you can take a snooze for three to four minutes.
In addition to the application and operation previously explained in the preceeding paragraph for
the alarm timer, the snooze timer is applicable to the follwings.
By making the oscillator frequency programable with J,lPD833G a notifying tone (or calling
bell) can be produced at a regular interval. When the notifying tone is heard, set the terminal
759
J.lp 0832G, J.lp 0833G
SNZ ON and OFF.
The main oscillator signal frequencies and duration of notifying tone are as shown in Table below.
Oscillator
Frequency
I nterval of Notifying Tone
Pulse at ALM OUT Terminal
65.536 kHz
Every 2 minutes
8-burst pulse every 0.5 Sec
32.768 kHz
Every 4 minutes
8-burst pulse every other Sec
16.384 kHz
Every 8 minutes
8-burst pulse every2.0 Sec
8.192 kHz
Every 16 minutes
8-burst pulse every 4.0 Sec
4.906 kHz
Every 32 minutes
8-burst pulse every 8.0 Sec
2.048 kHz
Every 53 minutes (Approx. 1 hrs.)
8-burst pulse every 16 Sec
1.024 kHz
Every 128 minutes (Approx. 2 hrs.)
8-burst pulse every 32 Sec
512 kHz
Every 256 minutes (Approx. 4 hrs.)
8-burst pulse every 64 Sec
256 Hz
Every 512 minutes (Approx. 8.5 hrs.)
8-burst pulse every 128 Sec
Be sure to set the terminal SNZ ON and OFF. Then, the notifying tone stops immediately. In this
case, the notifying tone can be heard again after the specified interval. (I h case of 1.024 signal frequency,
the notifying tone is heard again after two hours.)
The snooze timer is effective for use as a timer to notify such regular interval of hours as required
for the application of drops to a patient, the sackling of an infant, the medication to a patient, etc.
6-5.
Sleep Timer
The sleep timer offers such conveniecnes that the user can sleep listening in mood music or classic
music, or appreciating a theatri'cal performance through the radio or television.
1.
How to set Sleep Timer
To set the sleep timer, connect the terminal SLP OUT to sllch electronic instrument as television,
radio, etc. Then, switch the electronic instrument on. Next, set the terminal SCI to ON. The sleep timer
automatically controls the electronic instrument at the end of pre-set duration (15 minutes, 30 minutes,
60 minutes or 120 minutes).
Even though the terminal SCI is kept to ON, the SCI signal inside the LSI is driven by the single
pulse of approximately 8-ms width. Thus, the button switch (single pole single through switch) should
be used. The duration is similar to that of control signal. When determining the duration, use the 60/30
and 60/120 terminals as shown in Table 3.
Terminal 60/30
L
H
L
H
Terminal 60/120
L
L
H
H
Duration with the
use of the terminal
SCI (MIN)
6~-64
31-32 127-128 15 -16
L
Table 3.
760
= VSS
level
H = VDD level
,uPD832G,,uPD833G
The available durations ranging from 15 to 120 minutes offers the conveniences so much to
the users.
The sleep timer has the priority in setting the hours over the alarm timer. Thus, the alarm tone
stops immediately after the ON operation of the terminal SCI, and the sleep signal is emitted instead
from the terminal SLP OUT. At the same time, the control signal (one phase control signal) is emitted
from the terminal CNT OUT. Refer to Fig. 11 for the time chart of the signals to be emitted.
32~~MIN.
_-1j,'---_--;1
~----------~.-)
SLP OUT
I~----------
ALM OUT
SCI
__________
~r---l~
-1 r- 8
__________________
-j
ms
1/
~1
r- 8
ms
-..InL-____________. . .nL-____________
One-phase control _ _ _ _ _ _
signal
CNT OUT
If
r--f.'
I
)
~---------'
SCI signal inSide LSI
This diagram is drawn by the basis of 32MIN duaration
Fig. II
If you want to stop and clear the sleep timer completely, during the application, set the terminal
ACS to ON.
* The sleep timer has no display for the lapse of hours. If the memory is set so that the time is used
as dual time or stopwatch and let it start counting instanteneously after the terminal SCI is on, the lapse
of hours can be displayed for the sleep timer.
* When the alarm timer is used, it should be set to the time one minute or more later than the
end of duration for the sleep timer. Then, the sleep timer and alarm timer can be set together.
* When the alarm timer is set to a certain hours in the duration of sleep timer, if the standard
time corresponds to the alarm time, the alarm is not on until it reaches again at same hours after 24
hours. The sleep timer does not operate, unless the terminal SCI is set to ON, whenever using the
sleep timer.
* The sleep timer is effective, when the memory is not used as alarm timer (or control timer for
electronic instrument), as dual timer (with the terminal OUT set to VOO level) or stopwatch (with the
terminal STW set to VOO level). I n other words, the sleep timer can be used as independent 3-channel
timer in parallel with the combinations of 1 standard time, dual timer and sleep timer, and 2 standard
time, stopwatch and sleep timer.
2.
Applications of Sleep Timer
In addition to its proper applications as sleep timer, it can be used for slot machines to determine
the duration of service with the coin or the equivalent in shape. Among those slot machines are massaging machine, cooler, gas range, game machine, telescope, etc. of coin timer type.
761
,uP D832G,,uP D833G
3.
Relationship between Terminal SNZ and Sleep Signal
The ON operation of the terminal SNZ does not disconnect the sleep signal, but it extends its
duration. In other words, the ON operation of the terminal SNZ resets the duration circuit for the sleep
signal.
From the instance the sleep signal is off, the duration for the control signal is counted. The
counting is effective for 16~~ minutes for 15-minute duration, 32~~ minutes for 30-minute, 60~~
minutes for 60-minute and 128~9 minutes for 120-minute. This operation of terminal SNZ is quite
similar to that of terminal CNT OUT explained in the preceeding paragraph. Fig. 12 shows the relationship in operation between the terminals SLP OUT and SNZ on the basis of 32-minute duration.
r
M
31-32
".-1
r
31-32""·-j
•
CNT OUT
.
.I~__-
.....
1 _ _-
one-phase control signal
This diagram is drawn by the basis of 32M IN duration
Fig. 12
4.
2-Phase Control Signal
The ON operation of the terminal SC I produces the sleep signal from the terminal CNT OUT. In
addition to the sleep signal, the control signal (one-phase control signal) is also obtained from the
terminal CNT OUT. Therefore, if the control time is set to the hours out of the duration of theone-phase
rontrol signal, the two-phase control signal can be obtained as shown in Fig. 13. Thus, a multitimer can
be established. In this case, sleep signal, one-phase control signal and two-phase control signal are same
in duration. In other words, the duration is determined in combination with terminals 60/30 and 60/120.
Refer to Table 2 and 3.
The multi-timer which can be obtained by triggering the terminal SCI with the trigger pulse signal
produced by the separate IC is shown in Fig. 13.
762
,uP 0832G,,uP 0833G
IThe
----InL--_ _
SCI
1--32~~ MIN'--1
CNT OUT
__---'I
I
-----i-!- desired control time
,....----....,
.I~_________~I
-Two-phase
control signal
.1....___
32
M1N
'----l
SLP OUT
Trigger pulse for SCI
prodoced in another I C
L
r-
CNT OUT
f-- 32.:::~MIN__l
---' •
1'-_______1
SLP OUT
---' .
32':::~MIN'---1
i--------,
.....
1 _ _-'
- - Control signal
• ,-I_ _ _
for multi-timer,
.,'-------------This diagram is drawn by the basis of 32MIN duration
Fig. 13
* The durations of one-phase control signal and 2-phase control signal are extended when the
terminal SNZ is set to ON. This is same in operation as explained in the preceeding paragraph.
6-6.
1.
Dual Time
Display
With the terminal OUT set to VDD level, the merrory is used as dual time. If you want to see the
ALS terminal to ON. Then, the dual time (Fig. 2, (2), ii) is displayed regardless of the displays for
Normal and seconds (Fig. 2, (1), i and ii).
In case of alarm timer (or control timer), a statical display of hours are presented with the dot
illuminating. But the dot flashing every other second for the dual time. The dual timer has no display
for seconds. The resolution as the dural time is one minute.
2.
How to set the Dual Time
The method of time setting is similar to that of alarm timer (or control timer as explained in Item
2 of Paragraph 6-3).
3.
Applications of Dual Time
(1.)
Dual time is an optimum traveller's watch when it is used as a time for displaying the time differential
(or as a part of world timer).
It can be used to constitute an independent 3-channel timer in combination with standard timer and
sleep timer.
(2.)
Dual time can be used as a time to measure the lapse of hours. In case of 12-hour indication, AM 12
hours are interpreted as 0 (zero) hour. If the display on the dual time is AM 3 hours 25 minutes, the
amount of lapse of time is 3 hours and 25 minutes, and if the dual time displays PM 12 hours 40 minutes,
it indicates that 12 hours and 40 minutes have passed.
The display succeeding PM 1 should be added 12 hours for the counting of the amount of laspe of time.
For examle, it the display on the dual time is PM 3 hours 58 minutes, the amount of laspe of time is 15
hours 58 minutes (3 hours 58 minutes +12 hours).
In case of 24~hour indication, the counting is made from 0 hour as the cardinal point. Thus, no addition
is required to obtain amount of lapse of time. Table 4 shows the relationship between 12-hour indication
and 24-hour indication for the display of amount of laspe of time.
763
pPD832G,pPD833G
12-hour format
(HRS)
AM
24- hour format
(HRS)
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
AM
12
1
2
3
4
5
6
7
8
9
10
11
0
1
2
3
4
5
6
7
8
9
10
11
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM
PM
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Table.4
6-7.
1.
Stopwatch
Display
When the terminal STW is set to VDD level, the memory is provided with the function of stopwatch.
To see the display of stopwatch, set the terminal ALS to ON. Then, the stopwatch (Fig. 2, (2), iii) is
displayed regardless of displays on the standard time (Fig. 2, (1), i and ii). The stopwatch is provided
with displays of seconds and minutes. The minutes is displayed on the space for hours and the seconds,
on the space for minutes.
The dot flashing every other second for the display of seconds on the standard time. But the
colon is illuminated for the stopwatch.
2.
Application of Stopwatch
When using the stopwatch, keep the terminal STW set to VDD level and set the terminal ALM to
ON. Then, the stopwatch is ready for operation. At this time, if the FM terminal is set to ON, the display
is reset to 00 minute 00 seconds and hold as it is. The start-stop operation is made through the use of the
terminal FH. The stopwatch can count up to 23 minutes 59 seconds.
In case of 12-hour indication, the display succeeding to 9 minutes 59 seconds is A M 10 minutes
00 second, and AM indicates that the count reaches 10 minutes. The display ~~ 0 minute 00 second
comes next to AM 19 minutes 59 seconds. I n this case, ~~ represents 20 minutes. Fig. 14 will help you
understand the method of display explained above.
In case of 24-hour indication, the display is made in digit from 0 minute 00 second to 23 minutes
59 seconds.
Shows 20 Minutes
Start
MIN. SEC
n_nn
u-uu.
MIN. SEC
10 - C 0
1-1-_1-1.
MIN. SEC
0:59_
AM MIN. SEC
AM MIN. SEC
PM
PM
I-n n
I- U U •
1 -C 0
1 - _I -I •
AM MiN .• ~IE~
PM
LI u.
2-
~------------------------------------------------------------------------------------~
Starting of second counting
Shows 23 minutes
Full count
AM MIN. SEC
AM MIN. SEC
PM
PM
2: ~Ig-
MIN. SEC
n-n:!
U-UL.
MIN. SEC
O-Co
_I_::IU.
:::
58_
MIN. SEC
g:S9.
Fig. 14
764
AM MIN. SEC
:I·C 0
_I - _I J_
MIN. SEC
n -n
AM MIN. SEC
In - nn
IU-UU.
I
U.U I-
PM
AM MIN. SEC
1
n -n
IU - U
1
I.
jlP D832G, jlPD833G
* Since the terminal FH offers the start-stop (hold) operation of stopwatch, the measurement can
be made without counting the time wasted.
6-8.
Counter
Counter is an article used in reckoning and can kaep counting the number of people entered in a
certain place, quantity of items unloaded, amount of traffic at the specific place, calling a roll of pupils,
etc.
The function of counter is not designed independently, but is incidentally produced from the
stopwatch explained in Paragraph 6-7. Therefore, its capacity is 720 counts (12 x 60) for 12-hour
indication and 1440 counts (24 x 60) for 24-hour indication.
The counter for 24-hour indication which is provided with re-cycle count mechanism may be
more convinient to use than that for 12-hour indication.
1.
Application
First keep the terminal ALS set to VOO level. I n this case, the alarm (or control) time is displayed
for any hours.
Then, set the terminal STW to ON to obtain the display of stopwatch, and perform ON-OFF
operation of the terminal FM to obtain indication shown in Fig. 2, (2), iv. Finally, set the terminal STW
to 0 F F. The counter is ready for use.
The terminal STW is set to ON for every counting. The stopwatch starts operating when the
terminal STW is switched over from OFF to ON. Thus, the terminal STW should be set to the OFF
when the stopwatch is not in use.
Be sure to insert the circuit for preventing the terminal STW from chattering into its input circuit
as shown in Fig. 15. The use of common terminal for the signal to drive the liquid crystal is required for
the synchronization on the LSI circuit to shift the display from 19: 59 to 20:00 count for 24-hour il'Jdication.
~---- To the terminal
STW
100k
2SC945
Switch for counting
::£
o
o
I
::£
o
-'<:
o
o
~~
_ _- 4_ _ _ _ _ _ _ _ _ _ _ _-+__
From COM Signal
~ Circuit
for the
Prevention of chatterig.
-+~~
________________
+-~_
vss
lOOk
•
I.
-II-..
Circuit for - - - - -..
the Synchronization
~
O----Circuit for
the inversion of phase
Fig. IS
As the summary to the explanation for every channel, Fig, 16 shows the relationships between
the terminal OUT and dual time, that terminal STW and stopwatch, the terminal ALS and alarm (or
control) timer, and the terminal SEC and standard time.
765
,uP D832G,,uP D833G
Memory
Alarm timer or
Control timer
Stopwatch
Dual time
OUT
L
L
H
H
H
H
L
L
STW
L
L
L
H
L
H
H
H
ALS
"5
a..
L
H
L
L
H
H
L
H
LIH
LIH
coc
"E
'-
~
E
SEC
L
H
LIH
MIN MIN
~
c
~
(f)
Q)
E
0
"0
(!)
E
i=
H
L
H
E
~
--~vDD
15V
8
Vss
I
V SH C 2N C,NC'P N
P
0.151 1
f
INDICATOR FOR
-SECOND"
~I
~A:V jlltl~--,,~I
1500I.ft:
~~
POWER'
TRANSFORMER
AC power supply sw.
1,6L
:
!-i~
3:0V 0.15/1
~
- ~
~~~~ ~3
2SCI;8~~ -~ ~ECEPT ACLE
CNT OUT
U
T
l,nllXTAL32.768kHz
~~fi20P
::f'.L11 ~, ~~ i~
~c §i
2SC1280
~ ~~
6V
lIi Capacitors for protecting from the surge voltage of power
transformer OFF. (O.Ol-0.68pF)
AC100V
CD Make pPD832G and pPD833G pack by aluminum foil certainly when be carred or be kept.
770
The input terminals be unused connect to VSS always.
RECEPT ACLE
~ ~l5
MATTERS DEMAND SPECIAL ATTENTION!
@
••
I
-
,,::,:;:~~:~
0
S
-GVcc
DC
power
Supply
~
500k L1
.----~~4__+--~ACS
I
~
I
I
2SCI2BO.$.
INDICATOR
fOA'HAS"AND
"MIN"
:~ SP
___ ..,RELAY
::w
BATTERY
~R51:D ~
S
'111
I
I .-------*r--"'-1**
-+--+------ISCI
"""-1>----¢---------------.l
270270
2SC1280
~
lS953
r--------*-:+-----lSNZ
SLEEP CONTROL INPUT
J
,uPD833G
r
. _. -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_
~6~~~ot
L.;
.-----<
'------------------~-+~F~
~...L.o.::.;SN..:..:O:..:O:..=Z_=.E______- - l
V[!;
25C,,,(x51
'----------------------~--~DUT
~
.
*
-'"
RS1
_~r-.~7--~-~-±~-r. ~-r-------------------~---~·~~~
270270
e
J
'------+-1-00-k----I60/120
0<7"
SR51:D •
SECOND
l
'-'-_-_-_-_--'+-f--_-_-_-_-_-_-_-f-l~~/23~
IT~ t~t y~ f Fm§i ;/'
~
I-r=r 1{ 1"
ti: -tr.: ','.'" Q
iii~l\m))
S~::::~~
~~;;;OL
-;---'1
I}-:-Y:
SR"'0t:
7~
COM
'----+------l TEST
~++==::t~-II
S0~~CH ~;-
?
?
L=---o==F='=X;---11
",'
SR51:D
OU~~ME
?
60/120
,.1
~-
'2~70----27-0 ~---- -'~
60/30
MOS DIGITAL INT'EGRATED CIRCUIT
flPD2006G
QUARTZ-OPERATED ELECTRONIC CLOCK
CMOS LSI
The captioned Model2006G CMOS LSI has been developed for FIP (Fluorescent Indicator Panel)/LED-operated
quartz clock, which is operated at the reference frequency of 32.768 kHz.
The model s,.tPD2006G allows the direct operation of both FIP and LED.
The package type is 54 pin flat package.
FEATURES
•
•
•
•
•
Direct FIP/LED operation.
Clock counter is operated with 1.5 V, and can be backed up by battery.
Alarm timer, sleep timer, control timer, stop watch and dual time functions are provided.
Control time limit can be set to 16,32, 64 or 128 minutes.
Time signal tone can be output.
FUNCTIONS
1. Standard Time
2.
3.
4.
5.
6.
7.
Alarm Time
Snooze Timer
Sleep Timer
Control Timer
Dual Time
Stop Watch
771
JlPD2006G
ABSOLUTE MAXIMUM RATINGS (Ta=25 °c, Voo=Common)
Supply Voltage
Supply Voltage
Operating Temperature
Storage Temperature
VSS
VSH
Topt
Tstg
-3.0
-30.0
-20 to +75
-40 to +125
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
(f=32.768 kHz, Voo=Common, VOO-VSS=1.5 V, Co = 5 ....... 40 pF, CG = 5 ....... 30 pF)
CHARACTERISTIC
Operating Voltage
Total Current Consumption
772
SYMBOL
MIN.
VOO-VSS
1.2
ISST
Osc. Start Voltage
VSTA
Operating Voltage
VOO-VSH
9
TYP.
MAX.
CONOITION
UNIT
Ta=-20 to +75 ° C
1.5
2.0
V
2.0
5.0
J.lA
1.35
V
TSTA = 10 s, CG = Co = 20 pF
26
V
Ta=-20 to +75
No load
°c
Segment Out Current
Ip
5
rnA
VOO-VSH=20 V, VOS=2 V
h & 1 Hz Seg. Out Current
Ip
8
rnA
VOO-VSH=20 V, VOS=2 V
PM Seg. Out Current
Ip
16
rnA
VOO-VSH=20 V, VOS=2 V
Alarm & Control & Sleep Output Current
Ip
500
J.lA
VOO-VSH=20 V, VOS=2 V
MUT & Time Tone Output Current
Ip
500
J.lA
VOO-VSH=20 V, VOS=2 V
DIM
BLOCK DIAGRAM
Oimmer
(VSH)
12/24
t1""t4
OSC
IN 0
OSC
OUT
TST1 0
SEC 0 - - - - .
FS~
FM~ ~
F
H
U
OSC
Eill
I
dliSt
I
760
?-6
L
TIME
\IVIIIIUlt:/
Q)
Comparator
LA
I l b Control
H
760
Ir1
ALARM
CONTROL
TIMER
\IIUUI/
t3
OUT '"'
Control
: ~
H
~I
AC
0-----
STOP WATCH
724
II
II
SNZ
ACS 0
Vss
0-----
VDD~
(1 Hz)
I
I
W
0
h (C)
1---0
a1 ,.. gl
t:
~
I
Sleep
a2-g2
a3 ""93
---
~
1-0
dot (1 Hz)
§
1-0 MUT OUT
Alarm
I
~
1-0 ALM OUT
I
r
CNTDUT
SLPOUT
~TSGOUT
Time Tone
1
VSH
..J
..J
t-o
Q)
I I
Time Limit
•
SLI 0
(2048 Hz)
a()
~
-ALARM/CONTROL TIMER
-DUAL TIME
- STOP WATCH
II
"0
DUAL TIME
STW
AOS 0
ro PM (ADEG)
.....
In
:~~
1A1~AM{B)
"II
• STANDARD TIME
1PPS
~
TID~III
ASD 0
?-9
STANDARD
1
ASN
I~
C
N
0
0
0')
G')
j.lPD2006G
PACKAGE DIMENSIONS
Terminal No. & Name
(Unit: mm)
09.5
1.5 MAX.
3.0
~~
(/>3
+0
0.5_ 0.0 3
3;9 ±0.03
7.8 ±0.05
0.15±0.01
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Name
a1
b1
d1
c1
e1"
f2
92
a2
b2
d2
e2
c2
f3
93
a3
b3
e3
c3
d3
VDD
ALM OUT
TSG OUT
SLP OUT
CNTOUT
MUTOUT
TST 1
N.C.
No.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
N.C. = No Connection
Sketch of Pin
No. & Name
93
91
f1
a3
h&C
b3
e3
c3
d3
VDD
ALM OUT
TSG OUT
SLP OUT
CNT OUT
MUTOUT
TST 1
N.C.
AM & B
PM & ADEG
1 Hz
pPD2006G
VDD
OSCIN
VSS
DIM
ASN
12/24
DSTSAFFFASSAA
UT I ESSMHCNLCO
TWDCD
SZI
S
774
VSH
OSC OUT
Name
DUT
STW
TID
SEC
ASD
FS
FM
FH
AOS
SNZ
SLI
AC
AOS
12/24
ASN
DIM
VSS
OSCIN
VOO
OSC OUT
VSH
1 Hz
PM &ADEG
AM &8
h&C
f1
91
,uPD2006G
(1) Standard Ti me
Display
12-Hour Display
m
h
11-1-1- -I
PM 11_1- -I :1 ()
,.
(1) Ordinary Display
4
to
I ' 'I
I \
t-~\I"I
m
s
m
h
-I :1 - 1- -I
I -I ()
1_1m
-1--11-I-I:II()
(2) Second Display
Active
Term.
24-Hour Display
-I
I
--I
s
1I I I ()
SEC
(2) Memory
Display
h
(i)
Alarm/Control Time
-I- 11-1
PM
1_-_11_1-
4
-1--11-1
1- - -11_1 e>
..
4
h
II
I
..
1',,'1I
'I
:.~
(ii) Dual Time
PM
m
(iii) Stop Watch
m
1",'1I
,:.~\ 1
II
,
t~, I~V~I
r-'" ..
~-) I ' ' I
I
I" I
m
h
1 I I - -11-1
ASD
I -I - -11_1-
m
m
h
11_1 - -III
I I - _II_Ie>
m
s
1-1-1-11-1
I_I - I_I I_I _
-
t>
indicates an intermittent display of the dot every second.
•
indicates the dot kept on.
DUT
ASD
s
1-' 1-1'-1
1_' -1_11_1-
I- I I
I 1 -I
(iv) Time Limit
Active
Term.
24-Hour Display
12-Hour Display
I- I I
I-I -I
STW
ASD
TID
: } indicates the colon kept on.
Active Terminal means to set any specified input terminal to the VDD level.
775
,uPD2006G
Fluorescent Indicator Panel (FIP@)
(1) 12 hour display format
(2) 24 hour display format
Note: The suffixes of segments differ from those of Fluorescent Indicator Panel catalog as following.
s,LPD2006G
h
FIP5D15S
a4/ b4
a3
a2
al
776
,uPD2006G
TIMER FUNCTION
Sleep Timer:
It can be operated by an SLI input, SLP OUT - ON, and can be turned off at the preset time limit.
SLP OUT, CNT OUT, ALM OUT and MUT OUT will be turned off by an ACS input.
Alarm Timer (Control Timer):
It will be operated by matching the current time and the alarm time.
ALM OUT ... 2048 + 8 + 0.5 Hz output To be turned off after 4 minutes.
MUT OUT ... ON
To be turned off after 4 minutes.
To be turned off at the preset time limit.
CNT OUT ... ON
ALM OUT by an SNZ input
To be held for 4~~ min. and kept outputting for another 4
minutes.
ALM OUT & MUT OUT - OFF by an AOS input,
ALM OUT, MUT OUT, CNT OUT & SLP OUT - OFF by an ACS input.
TIME SIGNAL TONE FUNCTION
2048 Hz is output from TSG OUT for one second at every 00 min. 00 sec.
777
j.lPD2006G
Timer Output
Sleep Timer
(Time limit: 64min.)
SLI
----~fl~--------------~~S~--~n~------------------------I_
64min.
-I
j
SLP
OUT~
L, ft-___ -----:_-_-_'..L.:__________
r""1
1
A C S - - - - - - - - - - - - -____
~(~(-----------~n~------------
Alarm Timer
(Time limit: 64min.)
I
ALM
4min.
_
I
I
4±O min. -,
o U T - - - - ' l 111111 11111 II 111111111 III.....---(( ~_----lI"I'I"ml\lllllm"lTrl"lIIlll""'"lllllll--l~lfP-
.........".--oCt
VDD~4~6_-+--,
OSCINI-4~5~~--44
VSS~~--
DIM 1-4;..;;:3-+-_ _ _--,
to RADIO 26
42
& TUNER
TST10 S T S A F F F ASS A A ASN
27 N CUT I E SSM HeN Leo
41
. 'T woe D
S Z I
S 12/241
47kn
~
IlPD2006G
fl 53
h & C 52
51
AM & B
PM &,ADEG 50
1Hz~4~9__~
48
VSH
-20V
OSC OUT 1-4;....7_......._ _-,
MUT OUT
a:
RECEPTACLE
3
~----~~ALM OUT
La
~~ TSG OUT
~----~SLPOUT
24
2SC945
M
In
~
~
~
.-
VSS
12V
~75mA
282930313233343536 37 3~9 40 1Mn
l-~
O.68I'F
L
FH
---L...-
-----0
0-
FM=
I ~IX
~T'T1
~
~
----0
~---t----,
I
1
I
~o
DIM
....
O~-+--
'0-------..
SEC
,...
~
4r
~I
a:
TID
1
0
loon
lW -20V
RECEPTACLE
0--------.
ACS
--L-
13 c2 e2d2b2a292 12 e, cl dl bl al 9,54
e3
, -__
18~C3
~____
19,d
20 3
TSG OFF 21 VDD
PIEZO BUZZER
~
r-----------~O
""0-
VARIABLE DIMMER
1.5V
100V
~'~~V
F
:7=i ·F:
-
~ 2B2DM
~:--!.J
-.J
(,)
0
~
VSH
-20V
OUT
0
*+1000SJF
1
1.5V
l
Lvss
en
STW
VOD
~ Capacitors for protecting from the surge voltage of power
transformer OFF. (0.01 ...... 0.68IlF)
~VSS
I
:
I
1
0
~
."
C
N
o
o
0)
Ci)
...J
(X)
~
1::
APPLICATION CIRCUIT FOR FULL FUNCTION (24 Hour Format)
to ALARM OUTPUT
INDICATOR LED
F,IP
0
.-tl~
FIP4B15S/FIP4A 15S
to AOS Switch
-tl
I
I
I
(REAR)
,.t..
~r'""llH'~" """U""~Ll'LF2
S
ALARM OUTPUT
INDICATOR
~
-a
AOS
G)
--L..-
~
Ln
a:
.Jt.
0
C/)
ALARM
TIME SIGNAL
--L..-
13~~~ 17~6 ~~~~,
2SC945 47kn
(0((
D~~
~ ( ~ g'
r-----------~O
o~----~
ACS
--1..-
14 93 f3 c2 e2 d2 b2 a2 92 f2 e1 C1 d, b1 a, 91 54
PIEZO BUZZER
15 a3
f1 53
16 b
17 3
e3
h & C 52
l...-.._~18::..JC3
-20V
L-_~19~d3
48'
~---~ALM OUT
J,.LPD2006G
VSH 7
-20V
OSC OUT J-4~_ _ _-----.
",,-_2.2_. TSG 0 UT
23
V
l...-..---~~SLPOUT
24
~4,-,,6__-+~
--L-
,I
I
0 I M J-4;..::34-_ _ _ _-,
42
S A A ASN
LeO
41
I
S 12/24
0 S T
F F F
27 N CUT I S M H
. . TWO
TST!
C>-<
L;:---+----,
VSS~~~
M UT OUT
1 ~IX
--:;-T'n
---0
44
~---~2~5~CNTOUT
5
DO
OSCIN~4,-,,5~~_ _~
0-
FM::
1Hz~4~9~__~
20
TSG OFF 21 VOO
to RADIO 26
& TU N E R
FH
--L..~-----o
AM & B 51
PM & AOEG 50
I
A
RECEPTACLE
DIM
0---
"~
~
,
~
SEC
0---
I
TID0---
"'''0-.
RECEPTACLE
VARIABLE DIMMER
1.5V
100V
~l~~V ~
15V
I~
STW
:::
0---
"~
-n=:VSH
-20V
+1000pF
OUT
2B20M
~-
+I
1
1.5V
J7 ·
Lvss
0
Voo
*
~VSS
I
Capacitors for protecting from the surge voltage of power
transformer 0 F F. (0.01 '" O.68J,.LF)
:
I
I
o
o
en
SLI
SNZ
~~
C
N
0
LED
2W
-20 V 75 n
* Switch
to AOS
to LED
display
of alarm output
2S8549
TLR4047 iTLR4042
(THE REVERSE SIDE)
AOS
~
APPLICATIONS
(12 HRS. FORMAT)
0
~
I
I
J,
LED brightness
SLI
----Lo------~
r-------------O
SNZ
-----L-
o
.-----0
(Y)
0---------4
ACS
~,
-----L-
a:
.---------~o
en
((ft(
Alarm tone
Time signal \\\1
D
0---------4
FH
----L...-
D
~----o
0-
FM
Piezoelectric
buzzer
-20 V
J..LP02006G
FIX
When it is unused
OUT function.
connect X to VOO.
X
-20 V
o-------;---~~~--i
I
m
I
I
;JJJ
Radio
12 V Relay
75mA
Tuner
1 W-20 V
2SC945
~
~
c::
~
~
M
~
Q
2820M
~
-
I
r-J
I
I
I
l
I
_.J
TID function
connect TID
to VSS.
Then can set
the timer
duration 64
minutes by
~ -----r-~I~~e~r~----J
---~
-------------,
L
__
r---------
-1.5 V
.. Vss
tt=
~
:l-~f-n~t~~~ - - - ,
r--------
:
1+
"0SEC
*
nl
"v
U
~
VSS~IIIIII
100
1 W -20 V
100 V
DIM
*11
~
12 V Relay
75mA
Radio or
TV drive
oV
~~~-1-+-+-+--~~4-~
7kn
~
A F N F F A S
S SCM H
D
100lil
Radio or
TV drive
illS
I
I
STW
-r-voo
~
OUT
1500J..LF
-20 V
VSH
Available to
select STW
or OUT function.
.
0
~VSS
I
* Capacitors for protecting from surge
voltage of power supply VSH & AC line.
0
~
...J
(X)
01
Connect near
possible .
LSI with capacitors as
OJ
_______________________ J
1:::
"tI
C
N
o
o
0)
C)
~
Q)
m
2W
-20 V 75 n
~ to AOS
SWitch
to LED
display
of alarm output
LED
TLR4040/TLR4042
(THE REVERSE SIDE)
o
"*
~
,
,
C
N
o
o
en
J.
SLI
G)
--L-
SNZ
M
--L-
------------0
cr>
LOT
o~----_.
ACS
--Lo~----~
a:
Alarm ton:
APPLICATION
(24 HRS. FORMAT)
...
ALARM OUTPUT C;
DISPLAY
~
o
1:::
"'0
AOS
-----------0
((f(D
0
FH
;
~
Time signal \ \\\
FIX
Piezoelectric
buzzer
-20 V
l
2SC945
J..LPD 2006G
kn
47
When it is unused
OUT function,
connect X to VDD'
X
-20 V
o-------+---~-v--l
TSG OFF
m
I
,,
I
I
~
Relay
Radio
Tuner
Radio or
TV drive
",
'"
emf
V
12 V
75 rnA
_
~
~
*-,
1 *;f
2B2DM
oV
,..-----
I
I
r
I
I
I
_.J
TID
i ' _.J
~----------------------------------------------~I----~
IL
____________
-----------..
I
If not using
TID function
I
connect TID
I
to VSS·
Then can set
I
the timer
I
duration 64
I
minutes by
I
Clear.
-All
- ________
JI
l
r---------------------,
STW
Available to
-or-
.+
SEC
o'----+--__.
I_-VSS
"v
~
*
-1.5V
100 V
~
ss--=.I I I I I I
100nl
1 W -20 V
Radio or
TV drive
J;
0.010.68 jJF
•
v
DIM
2g3031~333435rr6373839«r18i
*:
*,
~
~
~
':'l
2SC945 47 kn
;; m
~
.------<>...
A F N F F A S
+
select STW
or OUT function.
~
VDD
+
OUT
_ 1500 J..LF
-20 V
~__~r-~------VSH
• VSS
* Capacitors for protecting from the surge
voltage of power supply VSH & AC line.
Connect near LSI with capacitors as
possible.
o
-
- - - - __ - ________________ J
MOS DIGITAL INTEGRATED CIRCUIT
fLPD6529C
AUTOMOTIVE CLOCK
CMOS LSI
GENERAL DESCRIPTION
The pPD6529C is a monolithic CMOS LSI for crystal controlled automative clocks. The circuits interface
directly with fluorescent indicator panel. The display format is 12 hours. It is also provided with a 4-ways
display brightness control function and can be driven by an external clock signal.
FEATURES
•
Crystal controlled oscillator (4.194 304 MHz)
•
Direct interface to fluorescent indicator panel (F IP4E8S)
•
12 hours display format
•
4-ways display brightness control (duty controlled dimmer
•
External clock drive possible (1 024 Hz)
•
Separated hours and minutes set controls (2 Hz)
•
On the hour adjustment control (±30minutes)
•
1 024 Hz output
•
42 Pin DIP mold
1, 1/4, 1/8, 1/16)
BLOCK DIAGRAM
VOOo--
PACKAGE DIMENSIONS
VSS~
in millimeters (inches)
56.0 MAX.
(2.20)
H·S
~~::::::~:~:~::t-
M·S
RES
1 2 3 4 5 6 7 8 9 10 11 1213141516 1718192021
'§~iD ~
~ci ~~ I~I
~=- ~90
~:::
f--_ _ _ _ _ _ _ _ _ _O_.5_±_0--i.1 (0.02)
~'9
,o.,os
02~-~'o
Z
.
~O.O\
OS 1
<>--1~----i
OS2
<>--1~----i
,
15.24
OSCIN
(0.6)
OSC'OUT
CLOUT
CL1NO-----------J
787
~PD6529C
CONNECTION DIAGRAM
(Top View)
0
0
>
I--
N
(Y')
I--
N
I--
$'
(Y')
eo
(Y')
..c
~ ~
I
U
Z
~ ~
V
N
N
eo
en
z :J
a
en U U
ill
en en U
a: a a z
U
Z
Z
....J
I-:J
en
.tJ
"0
'+-
ro
..c
I--
~
~
~ ~ ~
ru
"0
..U
N
..c
..c
PIN
NO.
SYMBOL
INPUT OUTPUT
INTERNAL
PIN
STATE
NO.
2
DS1
Dimmer input 1
3
DS2
Dimmer input 2
b4 c4
5
g3
Pull down
SYMBOL
INPUT
23
t
Segment output P-ch Open Drain
OUTPUT
RES input
H·S
Hour adj. input
M·S
T1
Minute adj. input
8
c3
29
b1
g2
30
a1
10
e2
31
f1
11
c2
32
b2
12
g1
33
d2· a2
13
e1
34
f2
14
d1
35
1 Hz
15
c1
36
CLOUT
AC
Clock output
Clear input
20
VSS
21
VSS
-Power supply
'37
b3
38
a3
Segment output
t
P-ch Open Drain
1 Hz signal
Segment output
f3
40
T2
41
T3
42
Pull down
NC
39
Pull down
STATE
Test pin 1
9
19
INTERNAL
OSCOUT OSC output
OSC input
RES
27
18
PIN
NAME
26
28
Ex. Clock input
u
25
e3
NC
en
OSCIN
d3
CllN
en
24
7
17
J
U
.[J,
XX o'clock 00 minute 00 second
RES
} c:::) (XX+1) o'clock 00 minute 00 second
XX o'clock 59 minutes 59 seconds
[4] B LK input (pin 1)
Put this pin (25) to Low Level (open) and the display outputs are turned off (Blanking).
Ouring Blanking, H·S,.M·S and RES inputs are ineffective.
Return this pin to High Level and the display outputs are recovered.
[5] OS1 input (pin 2) and OS 2 input (pin 3)
Combine OS1 and DS2 as shwn below and the display brightness is dimmed accordingly.
DS2 DS1 Output ON Duty Ratio
L
L
1
L
H
1/4
H
L
1/8
H
H
1/16
Clock Mode
Internal, External
•
~
Internal Clock Mode
4.194 304 MHz crystal oscillator is used.
•
External Clock Mode
1 024 Hz signal is input to CLIN pin.
Dimmer Freqency ; 512 Hz
[6] AC input (pin 19)
Put this pin to High Level (VDD) and this IC is reset to display 1 o'clock 00 minute (00 second).
[7] CLIN input (pin 17)
When this IC is to be driven by a crystal oscillator, put this pin to Low Level (VSS).
When this IC is to be driven by an external clock, input a 1 024Hzsignal voltage within the specified input
voltage range.
[8] CLOUT output (pin 18)
A 1 024 Hz signal with 50 % duty is output on this pin (as a CMOS output). When this IC is operated on
an external clock, this output is suppressed.
[9] T1 (pin 28),T2 (pin 40) and T3 (pin 41)
These pins are provided for the LSI testing and should be kept on Low Level (VSS) during operation.
790
j.lPD6529C
APPLICATION 1
F14C
100 n
BATTERY
(12 V)
+
10
IJF
RD15F
RD
5.6E
~
IGN.SW
150 n/2 W
VDD
DISPLAY SW
OSCIN OSCOUTi
1SS53
BLK
AC
GRID
+
---'-10 IJF
H·S
M·S
N
ID
:i
B::J
0
0...
:t
0
.....
c:
Q)
0...
E
LL
<0
RES
100 n
LIGHT
(12 V)
+
VI
u
(J)
en
ex)
w
q
Cl
Q)
en
DS1
F14C
RD15F
DS2
CLOUT
CLIN
(1 024 Hz)
VSS
680 n
APPLICATION 2 (Operate by external clock)
F14C
100 n
BATTERY
(12 V)
RD15F
OFF
+
RD
5.6E
0.1 IJF
~
IGN.SW
150 n/2 W
VDD
DISPLAY SW
OSCIN
AC
1SS53
BLK
GRID
+
-!-
10 IJF
H·S
M·S
RES
DS1
F14C
+
~
::J
B::J
<0
100 n
LIGHT
(12 V)
u
(J)
N
ID
0
:t
0
.....
c:
0...
Q)
RD15E
E
Cl
en
co
w
q
0...
u:
Q)
100 kn
en
CLIN
EX. CLOCK
(12 V)
56 kn
1SS53
Vss
680 n
791
MOS DIGITAL INTEGRATED CIRCUIT
pPD1990AC
SERIAL I/O CALENDAR & CLOCK
CMOS LSI
The pPD 1990AC is a CMOS integrated circuit having a clock function, which has been designed with the intent
of connecting to microcomputer.
This IC counts independently the month, date, day of the week, hour, minute and second, and is able to have
the output and input of these time data freely upon command from the microcomputer. By employing this IC,
the microcomputer is freed from performing clock functions, and will be able to be use exclusively to other complicated operations.
The pPD1990AC employs the oscillation of a32.768 kHz crystal as a reference. And all functions are enclosed
in a 14 pin dual in-line package.
FEATURES
• Timekeeping (hours, minutes and seconds) and calendar (months, date and day of the week).
o Serial input and output of date.
(Input & output code: All digits Binary Coded Decimal, except "Month" which is Hexa-Decimal Code)
o Reference frequency is 32.768 kHz, which is generated by a crystal oscillator circuit.
o Provided with timing pulse outputs. (Selection of 64 Hz, 256 Hz or 2 048 Hz is possible.)
•
By using CS (chip selection) terminal, multi-chip applications are possible.
PACKAGE DIMENSIONS
in millimeters (inches)
CONNECTION DIAGRAM
(Top View)
VOO (+)
C1
OUT ENBl
.-=
CS
~~~]~:mrmt
~~
LO
LO
0-
•
~~ M.~
.- z z
-
~ ~
('\j
(Y) -
M "":
o
-
'
'
254
I'
I
(0 100)
.
Jk
1.2:
(0.047)
7.62
0.5 ± 0.1
(0 300)
0
0
1
~
025+ •
0-15
•
(0.02) • -0.05
(0.010)
OATAIN
OATA OUT
GNO
ClK
(Vss)
NO.
Terminology
NO.
Terminology
1
C2
8
ClK
2
C1
9
DATA OUT
3
Co
STB
10
11
TP
OUT ENBl
4
792
TP
"!
5
CS
12
XTAl
6
OATAIN
13
XTAl
7
GND(VSS)
14
VOD (+)
jlPD1990AC
SERIAL I/O CALENDAR BLOCK DIAGRAM
,...
OUT ENBl .....
,...
ClK '"
40 Bit Shift Register
Multiplexer
N-ch
Open Dr
.---
DATA ,...
'V
IN
SO
PS
PS
~
~
~
Man
~ -th PS
1...-.--
GND
I
I
I
I
I
Date
Hour
Min
Sec.
I
I
I
I
.
~-
Time Counter
OSC
15 Stage Binary Divider
r---
0
b
,...
.....
1Hz
I--
i..----
..---
------l
~
32Hz Mu~er
I-t---
-i
64 Hz
256 Hz
2048 Hz
TEST
'--'-
-
0
t
I
1
~
0
-.
'"
N-ch
Open Ora
--
G NO
y
CS
,...
'V
SO
COMMAND
Latch/Decoder
()
STB
1 1
GND(VSS)
VDD(+)
: Serial Data
PS
: Preset
DNJ
: Day of the Week
CS
: Chip Select
TP
: Timing Pulse
fosc = 32.768 kHz
VDD = 2.0 to' 5.5 V
793
,uPD1990AC
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Input Voltage
Operating Temperature Range
Storage Temperature Range
Output Terminal Voltage
6.0
VSS-O.3 to VOO +0.3
-40 to +85
-55 to +125
VSS-0.3 to 6.0
VOO-VSS
VIN
T opt
Tstg
VOUT
ELECTRICAL CHARACTERISTICS (f=32.768 kHz,CG=CO=20 pF,Xtal RS=20 kn, Ta=25 °C)
CHARACTER ISTIC
Operating Voltage
SYMBOL
MIN.
VOO-VSS
2.00
Current Consumption
ISS
Low Level Output Current
IOL
TYP.
20
UNIT
5.50
V
50
/J.A
VOO-VSS=3.60 V
/J. A
VOO-VSS=2.0 V
VOL =0.4 V
kHz
VOO-VSS=2.0 V,Outy 50 o/c
/J.A
VOO-VSS=3.60 V
*500
CLK Input Frequency
fCLK
Input Leakage Current
liN
High Level Input Voltage
VIH
0. 8V OO
VOO
V
Low Level Input Voltage
VIL
VSS
0. 2V OO
V
VSTA
2.0
Oscillation Starting Voltage
OC
TEST CONOITIONS
MAX.
100
1
V
TSTA=10 s
* TP and OATA OUT are N-channel open drain output.
A.C. ELECTRICAL CHARACTERISTICS (FOR REFERENCE --- NOT SPECIFIEO)
(f=32.768 kHz, VOO-VSS=2.0 V, Ta=25 °C)
CHARACTER ISTIC
CO-2, CS-STB Set-up Time
SYMBOL
MIN.
TYP.
MAX.
UNIT
tsu
2
/J.s
STB Pulse Width
TSTB
2
/J.s
CO-2, CS-STB Hold Time
THLO
2
/J.s
STB LATCH Oelay Time
td1
CLK-OATAOUT Oelay Time
tcJc-o
OATA I N Set-up Time
tosu
2
/J.s
OATA IN Hold Time
tOHLO
2
/J.s
TEST CONOITIONS
*4
/J.s
except Time Read mode
2
/J.s
RL=33 kil, CL=15pF
* Note: When group 0 is Time Read mode, STB LATCH delay time is 40/J.s MAX. (td2).
794
,uPD1990AC
FUNCTION SPECIFICATIONS
o Reference frequency (X tal osc.).
o 32.768 kHz
o Data.
o Hours, Minutes, Seconds, Months, Date and Days of the Week ("Hours" 24 hour form) (Automatic
adjustment of long and short months). The data is output in order to "Second", "Minute", "Hour",
"Day", "Day of Week", "Month". Refer to Fig. 1.
o Data format
o Binary Coded Decimal (except "Month" which is Hexa-Decimal Code)
o Data input-output and Clock.
o Serial input, serial output.
o Data input and output in synchronization with the clock input from the ClK.
o Timing pulse output.
o One of 64 Hz, 256 Hz or 2048 Hz can be selected by command.
o Mode selection.
o Selected according to input to Co, Cl, C2.
Group "0" C2=0
Register control (control of data input-output).
Group "1" C2=1
Tp selection (Selection of timing pulses) and TEST MODE setting.
o Commands of group "0" and those of group "1" are independently latched by the STB input.
o Chip select.
o ClK and STB inputs prohibited by connecting CS input to GND(VSS) level.
o Prohibition of output of data.
o Making OUT ENBl input GND level DATA OUT terminal become high impedance.
o leap year
o The correction for length of the month is automatically performed and leap year is not automatically
performed. But it is possible to set calendar FEB. 29, and the day after, it will be Mar. 1.
Month
pay of Week
(Hexa
-Decimal)
(0 31 0 21 0.;00)
(9- ~)
I I I
I I
I I I
I [ I
I [ [
Unit of
Ten's of
Unit of
Ten's of
days
days
hours
hours
minutes
minutes
seconds
Uni~ of
seconds
(BCD)
(BCD)
I(B9°)1
(BCD)
(BCD)
(BCD)
(BCD)
(BCD)
0 310 2-,0./0 0
Ten's of
I
I
I
Unit of
I I
I
Ten's of
I
40 Bit Shift Register
* DATA of 40 Bit Shift Register appears on DATA OUT terminal from LSB of Second.
Fig. 1
795
tlPD1990AC
TERMINALS
•
Input terminals.
o DATA IN
o ClK
o Co- C2
o STB
o CS
o OUT ENBl
Data input of 40 bit shift register.
Shift clock input of 40 bit shift register.
Command input (3 bit).
Strobe input.
Chip select input (Prohibits ClK & STB).
Output control input (Makes the DATA OUT high impedance by inputting low level).
• Output terminals. (N-channel Open Drain)
o DATA OUT Data output of 40 bit shift register.
o TP
Time pulse output.
•
Oscillation terminals.
o XTAl
Oscillation inverter input (OSC IN).
o XTAl
Oscillation inverter output (OSC OUT).
• Power supply terminals.
o VDD
Plus power supply.
o GND (VSS)
Common line.
COMMAND SPECIFICATIONS
Group
0
1
C2
C1
Co
0
0
0
0
0
0
FUNCTION
DATA OUT
= 1 Hz
1
Register Hold
(TEST MODE is released)
Register Shift
DATA OUT
= [lSB]
1
0
Time Set & Counter Hold
DATA OUT
= [LSB]
0
1
1
Time Read
DATA OUT
= 0.5 Hz
1
0
0
1
0
1
1
1
0
1
1
1
TP = 64 Hz Set
(TEST MODE is released)
TP = 256 Hz Set
(TEST MODE is released)
TP = 2 048 Hz Set
(TEST MODE is released)
TEST MODE Set
* Groups "0" and "1" hold their functions independently, in other word, the command of the group "0" ("1")
can change the group "0" ("1") function mode only. Then you must release the JlPD 1990AC from TEST
MODE by setting commands of TP selection (group "1") or Register Hold Mode.
o Command input.
o 3 bit, binary code input. Co,C1,C2
•
796
Number of commands.
o Register control
o TP control
o TEST MODE set
tlPD1990AC
o Commands.
o Register control [Group "0"]
Register Hold MODE [000]
Holds the 40 Bit Shift Register.
The data is held, and shifting of the data becomes impossible.
1 Hz is output from the DATA OUT terminal. The TEST MODE is released by this command.
Shift MODE [00 1]
Shifting of data of the 40 Bit Shift Register becomes possible.
Data is shifted in synchronization with the clock input on ClK terminal.
DATA OUT terminal outputs data from [lSB] of the 40 Bit Shift Register.
Time set MODE [0 1 0]
Presets the data of the 40 Bit Shift Register in the Time Counter.
Resets the Flip- Flop (F IF) of 11 to 15 bits of the 15 Stage Binary Divider and hold the Time Counter.
By setting other command of group "0", the Time Counter is released from the reset and the hold.
[lSB] is output from the DATA OUT terminal.
Shifting of data becomes impossible.
Time read MODE [0 1 1]
Reads into the 40 Bit Shift Register the data of the Time Counter.
DATA OUTterminal outputs the data of [lSB] ([lSB]=0.5 Hz). Shifting of data becomes impossible.
"*
*
*
*
o TP control [Group"1"]
TP = 64 Hz set MOD E [1 0 0]
64 Hz (duty 50 %) is output from the TP terminal.
TP = 256 Hz set MODE [1 0 1]
256 Hz (duty 50 %) is output from the TP terminal.
TP = 2 048 Hz set MOD E [1 1 0]
2048 Hz (duty 50 %) is output from the TP terminal.
TEST MODE set MODE [1 1 1]
Sets up the TEST MODE (Not used for ordinary operation). When TEST MODE is released by Register
Hold MODE [000], TP terminal is 64 Hz output.
*
*
*
*
G
TEST MODE (Set by command of TEST mode (111))
In this mode DATA OUT terminal is enabled in spite of OUT ENBl input.
There are 2 type TEST MODE selected by OUT ENBl terminal.
TEST MODE 1 ; OUT ENBl = 0
In this mode every Counter ("Month", "Day of Week", "Date", "Hour", "Minute", "Second") is advanced at
a 1 024 Hz in parallel. In this case overflow carry of each counter is not affect to the next counter.
Month
f-
D/W
f--
Date
I--
Hour
I--
Minute
~
I
Second
--
1 024 Hz
TEST MODE 2 ; OUT ENBl = 1
In this mode TIM E COUNTE R is advanced at 1 024 Hz in stead of 1 Hz from "Second" counter input.
I
Month
I
I
I
I
D/W
Date
Hour
I
I
Minute
Socond
~
1 024 Hz
797
pPD1990AC
Following table shows the signals appeared on DATA OUT and TP terminals during the J,LPD1990AC is in the
TEST MODE.
CODE
C2 C1 Co
MODE
DATA OUT
1 Hz
TP
REGISTER HOLD
0
0
0
REGISTER SHIFT
0
0
1
LSB of 40 Bit SIR "0" or "1"
32 Hz
TIME SET
0
1
0
LSB of 40 Bit SIR "0" or "1 "
32 Hz
TIME READ
0
1
1
512 Hz
OTHERS
64 Hz *By this command, TEST
MODE is released.
TIC is advanced
TEST
MODE
is remained.
at 1 024 Hz in
parallel or serial.
~
TIC is advanced
32 Hz
at 1 024 Hz in
parallel or serial.
SIR = Shift Register
T /C = Time Counter
*Note:
While J,LPD1990AC is TEST Mode, by setting the Register Hold mode (Group "0" mode), Test Mode
changes TP=64 Hz mode in group "1" and as a result Register Hold mode is set. 1 Hz appears on DATA
OUT terminal and 64 Hz appears on TP terminal.
DATA INPUT/OUTPUT TIMING DIAGRAM
Command (C2. C1. CO) is set to [0011 (Shift Mode).
CS= "H"
ClK
DATA
IN __ _
L-+----- July
16 (Sun.)
2 Hours 24 Minutes
INPUT
TI M I NG
35 Seconds.
OUT
ENBl
OUTPUT
TIMING
DATA
OUT
November 25 (Sat.)
2 Hours 23 Minutes
49 Seconds.
o
1 2 3 4
5 6 7 8 9 1011
33 34 35 36 37 38 39
Written-in data lSB (HH H)
appears at output.
(Note)
798
Reading-in timing of CPU (Trailing edge of ClK).
JlPD1990AC
TIMING DIAGRAM FOR SETTING COMMANDS
CAN CHANGE
STABLE
CAN CHANGE
VIH-~~
-+--+--VIH
C2,C1,CO
Vil -~.-_ _ _ _ _ _ _ _ _ _- J
-I-~-Vll
I~-----------------------I
~-----------------------
tsu
cs
tsu
VIH--~~--------~~
STB
Vll~~-----~r-
ts-C*
ts-C*
/
ClK
r--------------
I
Vll--~------~----------------~--+""-------+---------------~'-+--
- - - - - - - - - - - - - - -
IN CASE OF BEING IN ORDINAlY MODE
OLD MODE
INTERNAL
MODE OF
IlPD1990AC
I"
'd,"--I
I
NEW MODE
IN CASE OF BEING IN THE TIME READ MODE
I•
i
td2**----.-l·
NEW MODE
OLD MODE
tsu
tHlD
tSTB
tdl
td2
ts-c
2 J.Ls MIN.
2 J.Ls MIN.
2 J.Ls MIN.
4 J.Ls MAX. (In case of being in.ordinaly mode.)
40 J.Ls MAX. (In case of being in the Time Read mode.)
2 J.Ls MIN.
Note: * Setting Register Shift command (001 ), input level of the ClK must be low level.
** The delay time until new mode becomes valid is 4 J.LS. MAX. (tdl). But in the case of J.LPD1990AC being
in the Time Read mode, it takes 40 J.LS MAX. (td2).
799
,uPD1990AC
TIMING DIAGRAM OF DATA INPUT AND OUTPUT
ClK
V,H
/
"
\.
\
V,l 7
\.
tdC-O
~
DATA a UT
I
X
tDSU
V,H
"\.
V,l
/
DATA IN
tdC-O
tDSU
tDHLD
VOH
Val
"
tDHlD
/
X
;{
~
2 JlS MAX. (RL=33 kn, CL=15 pF)
2Jls MIN.
2Jls MIN.
INPUT AND OUTPUT CIRCUITS FOR JlPD1990AC
Input circuits
(for C2, Cl, CO, STB, DATA IN, ClK, OUT ENBl, CS)
------------lSI-----------------
~--------------------_.----~VDD
p
R
input
....
O}------~----4I.....__--J\A./\,..-__4.....__-
GND
R =: 1 kn
Output circuits
(for DATA OUT, TP terminals)
------lSI--------
r--~--+-----{O
..
N-channel Open Drain
BOO
I
output
jlPD1990AC
APPLICATION CIRCUIT
CPU
C2
C1
I
I
I
I
I
STB
ClK
OUT ENBl
I
L
T
lP
30 pF
CD
'XI
Ih..
5 -30 pF
STB
ClK
OUT ENBl
I
CS I - - -
DATA OUT
I
I
-L
DATA IN
r---.
i OUTPUT
TP
XTAl
Co
INTER-
I
DATA OUT
GND
Cl
I
I
FACE
DATA IN
32768 kHz
XTAl
C2
:
i
:
:
I
i
:L ___ J!
INPUT
Co
VCC
p. PD1990AC
r---,
INTER- ~
FACE I
___ -l
TP
VDD
GND
r----,
.
POWER
I
I
SUPPLY
I
I
I' - CIRCUIT
_ _ _ ..J
!
+5 V
CO M
7/1
r~-----,
J
POWER DOWN
I
I
PROTECTION
I
I
CIRCUIT
I
I
L ______ J
801
j.lPD1990AC
POWER SUPPLY CIRCUIT
2SA733
Trl
+5 V (Vcc)
to VDD of",PD1990AC
15 kn
4.7 ¢=
Ni·Cd x 3
4.7 kn
GND
POWER DOWN PROTECTION CIRCUIT
to VDD of ",PD1990AC
+5 V (VCC)
~--------~~----------~
A1
to CS of ",PD 1990AC
A2
/
GND
The Power Down of Vee line makes es terminal inactive, with R1 and R2 resistors.
The trigger level of this circuit is calculated as following.
(R1+R2)·VBETr3
Vtrigger
802
=- - - - - - - R2
JLPD1990AC
INPUT INTERFACE
For STB input
to VDD of J,LPD1990AC
STB(CPU)
to STB of ",PD1990AC
22 kn
22 kn
For other input (C2, C1, CO, DATA IN, ClK, OUT ENBL)
to VCC (+5 V)
3.3 kn
to input terminal of ",PD1990AC
from CPU
OUTPUT INTERFACE (DATA OUT, TP)
to VCC (+5 V)
33 kn
to CPU
from DATA OUT or TP
terminal of J,LPD1990AC
803
,uPD1990AC
APPLICATION
2SA733
VCC(+5 V) '"'
""
Powe r Supply
Voltage
510 n :
15 kn· ~ 1 kn
..;
K
ZZ 4.7 JlF
2SC945
4.7 kO:
-=-Ni-Cd
-=3.6 V
I
7i7"
7;f'r
7.7-
14
~ Vee
VCC
3.3 kn
i
C2
1
C2
XTAl
2
C1
XTAl
12
Vee
i
i
ClK
~
....L.Uen
3
77
3.3 kn
8
ClK
Vee
3.3 kn
6
u
en
cb
T
a--
CD=5-30 pF
3.3 kn
Co
CG=30 pF
13
Vee
3.3 kn
!
C1
32.768 kn
VDD
11
OUT ENBl
~ Vee
33 kn
Cl.
::s.
OUT ENBl
CS
5
9
DATA OUT
DATA OUT
33 kn
!vec
33 kn
10
TP
TP
VDD
~
10 kn
51 kn
]-.... 2SA 733
22 kn
STB
GND
1
804
4
,
STB
k~ 2se945
10 kn
22 kn
7'r7
Vss
7J,
77
~
MOS DIGITAL INTEGRATED CIRCUIT
,uPD6517P3
3.5 DIGIT MULTIPLEXED LCD QUARTZ WATCH
CMOS LSI
* This LSI is supplied in dice form only.
The J1 PD6517P3 is a CMOS LSI for an electronic wrist watch operated on the oscillation source of 32.768 kHz.
A multiplexed (1/2 duty and 1/2 bias) 3.5-digit liquid crystal display element in 12-hour or 24-hour system is
used with the LSI.
The functions of basic time ('hour', 'minute', and 'second' and calendar ('month' and 'date') are provided.
FEATURES
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
All output terminals for driving liquid crystal elements are arranged on one side of the chip.
The display is standard 3.5 digit multiplexed LCD.
Basic time displays 'hour and minute'. By operating switches, 'month and date' or 'second' can be displayed.
Two operation switches are provided.
The display automatically returns to 'hour and minute' display about 2 seconds after performing 'month
and date' display.
Correction of 'second', 'minute', 'hour', 'date', and 'month' can be done separately.
The place to be corrected is indicated by blinking.
One touch correction of ±30 seconds.
12-hour or 24-hour system can be optionally selected by bonding.
Voltage doubler circuit is integrated within.
Outline of Functions
(1) Normal display
(2) Calendar display
(3) Second display
'hour and minute'
'month and date'
'second'
B05
Q)
o
m
CJ
o
~
~ ~
'/
S1
0--
SET
MONTH
~ GATE
INPUT
S2
~
+12
j
----
().
SET
~
.....
------
GATE
~
V//#//A
~
.......---D-A-T-E----,J
----
t
I" . " ,
\.
t t < , i ......
....----------..t
PLA
-e-e-
...
HOUR
t
.::
G)
:c
0
»
"
I
.•..
'-----0
I-
•.:.,
~.
~
r
~
~
\",~~
fW
8
8>i . .,. .',
0
~
~
/
~
~
~
\
~------------------~
J-f-+----t
~
'-----,-,-......
AC ().
.....
T1
SET
I
GATE
L
J--~
j
l;60·
::'. :.' .""',.".
TEST
SET
~
INPUT
~
0--
IN
0--
OSC
+60
OSC OUT
0--
STAGES
VDO
0------
+
1
'
-
.........--O-IV-I....
O-ER-"""'--+32768
L
t
-
.'
. . . . ,. .:. . :..': . .,. . "'"g } : , " j
t
0
m
n
":.:,.
~
L2:)
g
I
......
~
B4/C3
......- -
I
t
VOLTAGE
COMMON
~
COM-X
DOUBLER
DRIVER
~
COM-Y
OC
~
I i--V
W
":
I
I
VSS
"".'.':'.> "f,>
........:.........
; ' ; :,
SECOND
GATE
1HZ
T3
lifr'
l :'"
L..
o--~'
T2 0---
OSC
JJ
:'.':'
U.•
MINUTES
I
3:
AOEG1/C,
~
~
:.',
~
GATE
-
"»c
I
.1
~~
> ...,.:' ••..........':".' . :",:",• :,~
'--_ _ _ _ _ _ _ _ _ _ _ _ _ _---. .",
SET
JJ
~\I~
+28,29,30,31
~-+---+-I---------'
CONTROL
C')
-""-.-
~/~~~~ ~ J ~,~
0--
12/24 H
/.
~
~
r
0
--:"'"""I
crN
VSH
jlPD6517P3
ABSOLUTE MAXIMUM RATING (Ta=25°C)
Supply Voltage (1 )
VOO-VSS
-0.3 to +5.0
V
Supply Voltage (2)
VOO-VSH
-0.3 to +5.0
V
Operating Temperature
Topt
-10 to +60
°c
Storage Temperature
Tstg
-40 to +125
°c
RECOMMENDED OPERATING CONDITIONS
UNIT
CHARACTERISTIC
SYMBOL
MIN.
TYP.
MAX.
Operating Voltage 1
VOO-VSS
1.3
1.55
1.7
V
Operating Voltage 2
VOO-VSH
2.2
3.0
3.4
V
ELECTRICAL CHARACTERISTICS
voo=common, Voo-VSS=1.55 V, VOO-VSH=3.1 V, f o =32.768 kHz, CI=30 kil, CG=33 pF, CO: integrated)
( within T a=25 °c
SYMBOL
CHARACTER ISTIC
MIN.
TYP.
MAX.
UNIT
CONOIITON
Operating Voltage Range 1
VOO-VSS
1.2
1.55
1.8
V
Functional Operation
Operating Voltage Range 2
VOO-VSH
2.0
3.0
3.6
V
Functional Operation
0.8
1.5
J1.A
C1 =C2=0.1 J1.F
no load
1.4
V
Current Consumption
100
Oscillation Start Voltage
VSTA
Frequency Stability
ILl f /f 0 I: (V 0 0 -V SS)
Frequency Adjustment
Range
ILlf/fol: CG
3
50
tSTA~10 s
ppm
CG=20 pF, VOO-VSS=
1.45 to 1.55 V
ppm
CG=5to 33 pF
Sl, S2 Input Current
liN
3
10
60
J1.A
VOO-VI=QV
Tl
liN
50
150
400
J1.A
VOO-VI=O V
Common Output Current
Ip, IN
3
16
J1.A
VOO-VO=0.2 V
Segment Output Current
Ip, IN
0.5
5
J1.A
VOO-VO=0.2 V
Doubler Voltage
VSHD
2.8
Integrated Capacitor
CD
T3, AC Input Current
20
V
RL=3 Mil,
Cl =C2= 0.1 J1.F
pF
f=10 kHz, Vp-p=O.l V
807
,uPD6517P3
TERMINOLOGY AND COORDINATES OF PAD
29
0
o
D
o
D
D
D
D
y
D
D
D
E
E
o
(0,0)
N
D
N
D
o
22
o
Chip Size: 2.245 x 2.20 mm
0
D
DDDDDDDDD o
D D
10
11
2.245 mm
·1
The origin of coordinates is the center of chip.
COORDINATES
COORDINATES
PAD NO.
808
TERM INOLOGY
1
T3
X
Y
1003
982
PAD NO.
TERMINOLOGY
16
E3/F3
Y
X
-92
-982
2
T2
799
17
G3/AD3
-275
3
T1
617
18
C3/B3
-457
4
VSS
435
19
E4/F4
-639
5
12/24
253
20
G4/A4
-821
6
VDD
71
21
C4/B4
-1003
7
OSCIN
-111
22
COM X
-669
8
OSC OUT
-487
23
S1
-453
9
COMY
-669
24
S2
-270
10
C1/ADEG1
-982
25
AC
-73
11
D2/B1
818
26
C1N
108
12
E2/F2
635
27
DC
617
13
G2/A2
453
28
C2N(VSH)
799
14
C2/B2
271
29
VDD
982
15
D4/COL
89
(Unit: j..Lm)
,uPD6517P3
OPERATION DIAGRAM
hour
Sl
()
minute
()
•
Sl
month
•
date
second
auto return
after 2 seconds
S2
e . . ., \ '
• -::.."
I I 1/
S 1; ±30 second correction
second
I,
I
S2
hour
() ....
() -:.
" \
\
I
I / ,,-
Sl ;+1 *
minute
-''''
\
,
'
S2
24-hour
system
12-hour system
Sl ;+1
*
, I I
..
_'0 :::
-' I I ....
I I '
S2
Sl;+l
month
*
date
,/ I
I
t
()
colon blinking at 1 Hz with 50 % duty
•
colon turned on
()
S2
•
Sl;+l *
date
\ 1/
::
S2
~ digit
to be corrected blinking at 2 Hz with 50 % duty_
/ 1\
@
keeping S2 pressed down for 2 seconds or more will return
to the normal mode.
1 advance for 1 push of S 1.
keeping Sl pressed down for 2 seconds or more will make 4
advances in one second.
Time after all clear has been performed (AC on)
12-hour system: January 1st 1 o'clock 00 minute 00 second (set to AM 1 o'clock)
24-hour system: January 1st 0 o'clock 00 minute 00 second.
'tl Date can be set to anyone of 1 to 31 regardless of the month.
When "hour-minute" display is recovered after the calendar correction, non existing date (e.g. February 31)
is corrected to the first day of the next month.
'tl In this watch, February ends at 28th.
But, the date February 29 which has been set in 'date' correction mode, is preserved when 'month-date'
display mode is recovered.
'tl When 'hour' digit is being corrected in 12-hour system, 'A' or 'P' will be displayed corresponding to AM ro PM.
'tl
809
,uPD6517P3
FUNCTIONS OF PADS
(1) AC Pad
By connecting this AC pad to VDD, all counters are all-cleared to January 1, 1 o'clock 00 minute 00 second
(i.e_ set to AM 1 'clock) in 12-hour system, or January 1,0 o'clock 00 minute 00 second in 24-hour system.
The AM or PM mark for 12-hour system is only displayed in correction mode.
If a capacitor of 0.01-0.1 J.1F is connected between this pad and VDD, all counters are cleared every
time when power is turned on.
Some disorder in the display may happen after the power is turned on, but the functional display is recovered
by correcting time and calendar.
(2) DC, Cl N, VSH Pad
A voltage doubler is contained inside.
The double voltage is avaialble on Pad VSH if capacitor of 0.047-0.33 J.l.F is connected from outside
between Pad DC and Pad Cl N, and between Pad VSH and VDD.
The doubled voltage is supplied to liquid crystal driving power source.
(3) Sl Pad
When this Pad is connected to VDD, either of the following actions is performed.
(i)
In the case of ordinary display function, change-over between the display functions of the ordianry
display is performed.
(ii) In correction modes, every time when Sl is connected to VDD, the content of the blinking digit
advances by 1 (1 push 1 advance), except for 'second'. When 1 push reset to 00 second if the second is
displayed between 01 and 29 seocnd, and advance to 1 minute if the secodn is displayed between 30
and 59 second. When this pad is kept connected to VDD for 2 seconds, the content of the blinking
digit advances by 4 in a second (4 pulses per second).
(iii) When normal display mdoe is changed from 'hour and minute' to 'month and date', the display
automatically returns to 'hour and minute' display after about 2 seconds.
(4) S2 Pad
When this pad is connected to VDD, either of the following actions is performed.
(i)
In normal display mode, 'second' starts to blink to indicate that 'second' correction mode is taken.
(ij) In correction mode, the digit to be corrected is changed from one to another.
(iii) In correction mode, holding this pad connected to VDD for 2 seconds or more makes 'hour and minute'
of normal display mode be recovered.
(5) 12/24 Pad
Connection of this pad to VDD makes 12-hour system operate and to VSS makes 24-hour system operate.
(6) Tl, T2, and T3 Pad
(i) These pad are provided for testing.
In normal operations they should be kept open.
(ii) These pads are used to test with an IC tester, tests cannot be done with liquid crystal elements
loaded because the liquid crystal elements should be driven by DC voltaege (i.e. High or Low level).
(iii) The process and test patterns for testing with an IC tester should be consulted with the respective
separate specifications.
BIO
,uPD6517P3
LCD FORMAT
12-Hour System Display
COM
02/
E2/
y
/81
/
G2/
F2 /
A2
C2/ 04/
/
E3/ G3/ C3/
82 /cOL /
F3 /A03 /
E4/
83 /
G'V
F4 /
A4
C4/
COM
/84
x
24-Hour System Display
COM C1/02/
y
~~~
/81
E2/ G2/ C2/ 04/ E3/ G3/ C3/ E4/ G4/ C4/
/
F2 /A2 /82 /cOL /F3
~03
/83 /
(
F4 /A4 /84
COM
X
)---- COM X
@@----COMY
811
,uPD6517P3
APPLICATION CIRCUIT
to LCD of 3-volt
operation _ _
_______
r-------~A
32.768 kHz r--...&...-L...----------1.--..
o
S1
OSCOUT
....-----~OSC
S2
IN
0.01 J.LF
ACJ-----l~
r--~
_ ___l
VDD
/-LPD6517P3
C1 N t - - - - - - - - ,
C1
0.068 /-LF
12/24
....-~--IVSS
812
DC t - - - - - - - '
r
VSH t - - - - - - - ,
C2
0.068 ~F
1. ALPHA-NUMERI,CAL INDEX
2.
QUICK REFERENCE GUIDE
3.
CROSS REFERENCE GUIDE
4.
MAINTENANCE AND OBSOLETE TYPES
5.
GENERAL STATEMENT
-{:( NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
o History
0
Types and Features
o Type Number Designation
0
Device Technologies
-{:( STANDARDS OF INTEGRATED CIRCUITS
*
*
*
6~
HINTS ON CORRECT USE
TECHNICAL SYMBOLS AND TERMS
RELIABILITY AND QUALITY CONTROL SYSTEMS
AUDIO APPLICATIONS
6 - 1.
CAR AUDIO
6 -2.
HOME AUDIO
6- 3.
PORTABLE AUDIO
7. TV APPLICATIONS
8. DIGITAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11.
ARRAYS
12. OTHERS
13. APPLICATION NOTES
-
VOLTAGE REGULATORS
INDEX
Page
tLPC494C
Switching Regulator Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
816
tLPC494G
Switching Regulator Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
827
tLPC1394C
Switching Regulator Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
832
tLPC78LOO
3-Terminal Possitive Voltage Regulator (0.1 A) •. . . . . . . . . . . . . . . . . ..
840
tLPC78MOOH
3-Terminal Possitive Voltage Regulator (0.5 A) .. . . . . . . . . . . . . . . . ..
846
tLPC7800H
3-Terminal Possitive Voltage Regulator (1 A) . . . . . . . . . . . . . . . . . . . .
852
tLPC7900H
3-Terminal Negative Voltage Regulator (1 A) . . . . . . . . . . . . . . . . . . . .
858
815
BIPOLAR ANALOG INTEGRATED CIRCUIT
pPC494C
SWITCHING REGULATOR CONTROL CIRCUIT
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTION
The pPC494C is an inverter control unit which provides all the control circuitry for PWM type switching regulators.
Included in this device is the voltage reference, dual error amplifiers, oscillator, pulse width modulator, pulse steering
flip flop, dual alternating output switches and dead time control.
FEATURES
o Complete PWM Power Control Circuit.
• Adjustable Dead-time (0 to 100 %).
•
No Double pulsing of same output during load transient condition.
•
Dual error amplifiers have wide common mode input voltage capability (-0.3 V to V CC-2 V).
• Circuit architecture provides easy synchronization.
•
Uncommitted outputs for 250 mA sink or source.
• With Miss-operation Prevention Circuit for low level supply voltage.
•
Full Pin-Compatible TL494C.
PACKAGE DIMENSIONS (Unit: mm)
NON·
19.4 MAX.
15 14 13
3
816
4
CONNECTION DIAGRAM (Top View)
I
INV
INPUT
INV
INPUT
REf.
OUT
OUTPUT
CONTROL VCC
NON·
INV
INPUT
INV.
INPUT
FEED· DEAD·
BACK TIME
CONTROL
C2
E2
RT
GND
_1~_9 ~
5
6
7
8
CT
Cl
,uPC494C
BLOCK DIAGRAM
VCC
Ref Out
GND
RT
CT
Dead-Time ~
Control ~-.
Non-Inv. Input
Inv. Input
Non-Inv. Input
Inv. Input
Feed-Sack
3 ~------'
ABSOLUTE MAXIMUM RATINGS (Ta =25°C)
Supply Voltage
VCC
41
V
Error Amplifier Input Voltage
VICM
VCC+0.3
V
Output Voltage
VCER
41
V
Output Current
IC
250
rnA
Total Power Dissipation
P T (Ta=25°C)
1000
mW
Operating Temperature Range
T opt
-20 to +85
°c
T stg
-65 to +150
°c
Storage Temperature Range
RECOMMENDED OPERATING CONDITIONS
CHARACTER ISTIC
Supply Voltage
SYMBOL
VCC
Output Voltage
VCER
Output Current
MIN.
TYP.
MAX.
UNIT
7
40
V
-0.3
40
V
IC
200
mA
Error Amplifier Sink Current
IOAMP
-0.3
mA
Timing capacitor
CT
0.47
10000
nF
Timing Resistance
RT
1.8
500
kn.
Oscillation Frequency
fosc
T opt
1
300
kHz
-20
+70
°c
Operating Temperature
817
JLPC494C
ELECTRICAL CHARACTERISTICS (VCC=15 V, f=10 kHz, -20 ~ Ta ~ +70 DC, unless otherwise noted)
BLOCK
Output Voltage
Reference
Section
Oscillator
Section
SYMBOL
MIN.
TYP.
MAX.
UNIT
Vref
4.75
5
5.25
V
I re f=1 mA, T a=25 °c
CHARACTERISTIC
Line Regulation
REGIN
8
25
mV
7 V~VCC~40 V
I re f=1 mA, Ta=25 ° C
Load Regulation
REGL
1
15
mV
1 mA~ Iref~10 mA, T a =25 °c
Temperature Coefficient
Vref
0.01
0.03
°
%/C
(Note 2)
Short Circuit Output Current
Ishort
50
mA
Frequency
fosc
10
kHz
(Note 1)
Standard Deviation of Frequency
Frequency Change with
Temperature
1
Input Bias Current
-2
Maximum Duty Cycle
(Each Output)
45
Input Threshold Voltage
Vth
%
-10
/JA
%
49
o °c ~ Ta ~ 70°C, CT=0.01
7V ~VCC ~40 V, CT=0.01 /JF
T a=25°C, RT=12 kn
O~VI ~5.25
V
VI=O
Zero duty cycle
3.3
10
mV
VOAMP=2.5 V
V
Maximum duty cycle
VIO
110
25
250
nA
VOAMP=2.5 V
0.2
1
/JA
VOAMP=2.5 V
Common Mode
Input Voltage
I
Low
I
High
Open-loop Voltage Amplification
-0.3
V
VICM
7 V~VCC~40 V
VCC-2
Av
CMR
60
80
dB
VOAMP=0.5 V to 3.5 V, T a=25 °c
500
830
kHz
Ta=25°C
65
80
dB
VCC=40 V, T a=25 °c
Output Sink Current
0.3
0.7
mA
VOAMP=0.7 V
Output Source Current
-2
-10
mA
VOAMP=3.5 V
Standard deviation is a measure of the statistical distribution about the mean as derived from the formula;
f
1
osc'7 0.817 RTeCT + 1.42.10-6
.
/JF
RT=12 kn
3
0
Calculation expression of frequency fosc is as follows
BIB
1
CT=0.01 J.LF, RT= 12 kn, T a=25 °c
7 V~VCC~40 V, CT, RT,·const.
Ta=25°C
Input Offset Current
Common Mode Rejection Radio
Note 2:
%
Vref=O, T a=25 °c
2
Unity Gain Bandwidth
Note 1 :
2
-20 °c ~Ta ~ +85 °c
I re f=1 mA
Input Offset Voltage
Input Bias Current
Error
Amplifier
Section
%
10
Frequency Change with Voltage
Dead-time
Control
Section
TEST CONDITIONS
(Hz)
Maximum duration of short circuit condo is one second. (non repetitive)
G=
JLPC494C
BLOCK
PWM
Section
CHARACTERISTIC
SYMBOL
MIN.
Input Threshold Voltage
Input Sink Current
0.3
Collector Cutoff Current
ICER
TYP.
MAX.
UNIT
4
4.5
V
rnA
V(pin 3)=0.7 V
100
}J.A
V CE=40 V, V CC=40 V
-100
}J.A
VCC=VC=40 V
0.7
2
Emitter Cutoff Current
TEST CONDITIONS
Zero Duty Cycle
VCE(sat)
0.95
1.3
V
IC=200 rnA, VE=O,
Common Emitter
VCE(ON)
1.6
2.5
V
I E=200 rnA, V C=15 V
Emitter follower
100
200
ns
100
200
ns
Collector Saturation Voltage
Output
Section
Output Voltage
Rise Time
common
Emitter
Emitter
follower
tr
Total
Device
Emitter
Emitter
follower
n
10=100 rnA
common
Output Voltage
Fall Time
VCC=15 V, RL~150
70
200
ns
70
200
ns
12.5
rnA
VCC=15 V
all other inputs and outputs open
rnA
V(pin 4)=2 V, see Fig. 1
Ta=25 DC
tf
Standby Current
ICC(S.B)
8
Bias Current
ICC(B!.)
10
819
JLPC494C
Fig. 1 Test Circuit
VCC=15 V
RL
(4)
VCC
u------IDead time
Test Input {
RL
150 Q
150 Q
2 W
2 W
C1
E1
Output 1
(3) Fead Back
(6) RT
(5) CT
C2
E2
Output 2
0.01 F
(+)}
(_) EA.
r--11--~(+)
C.L
(-) Sense
(3) Output
Control
Ref
Out
(
14
)
* Recommend film capacitor
GND
(7)
Voltage Waveform
r------VCC
Voltage at
C1
-----0
mn
Voltage at
C2
.-----VCC
---0
Voltage at
C3
Dead-time Control
Threshold
I
I
Input
I
I
I MAX.
10%1~
I
I-!
feed Back Input
0.7 V _ _ _ _ _ _ _ _ _ _ _
(E.A. Output)
FUNCTION TABLE
OUTPUT CONTROL
INPUT (13 pin)
At Ref-Out
Grounded
820
OUTPUT FUNCTION
Normal push-pull operation
Single-ended or parallel output
Threshold
I
I
--l~
,uPC494C
TYPICAL PERFORMANCE CHARACTERISTICS (Ta =25
± 2°C, V 1N =15 V)
MISS·OPERATION PREVENTION
CIRCUIT CHARACTERISTICS
MAXIMUM POWER DISSIPATION
1.2
6
3:
I
c
.2
1.0
I
0.8
V>
V>
Q)
2
-0
0
~
:;:
>
0.6
0
4
0...
0.4
I
0.2
0
I
i
>
f-
I
25
75
100
0
125
1
i
0...
0
-,L
.-
I
I
w
~
i
I
i
()
I
!
i
I
6
VCC-Supply Voltage - V
REFERENCE VOLTAGE vs.
SUPPLY VOLTAGE
REFERENCE VOLTAGE vs.
TEMPERATURE
40r-----~----,-----,_--------~
>
E
I
>
I
Q)
Q)
~
tl.O
()
3
2
-0
0
I
VCC=15 V
!
IREF=l rnA
,--1-----+-------,,
I
I
!
:
'
Q)
Q)
~
20
..c.
4
>
g
I
-+--
Ta-Ambient T9mperature --'C
6
~
VCE
i
I
~
L~
!
\
:J
E
:J
E
·x
I
5 V
~30Q
1
i
>
ro
e-
Circuit
i
I
>
Q)
a;
Q)
u
a::
~
I
l.L.
a;
W
a::
>
a::
I
-40 ~----t--
l.L.
W
a::
>
""1
10
0
15
20
25
30
35
40
-60~
-25
VCC-Supply Voltage - V
____ ____ ____ ____ __
0
25
50
75
100
~
~
~
~
~
Ta-Ambient Temperature -'C
FREQUENCY vs. RT AND CT
FREQUENCY vs. TEMPERATURE
4
500~~~-+--+--+---+-~
N
:z:
.x
>.
u
cQ)
200~~--~~~-+---+--+-~--~~
Lt
I
()
If)
Rr=12kQ
Cr=O.Ol /IF
Q)
tl.O
100~-+---+~~-~~-+--+--+---+~
1ii
..c.
()
50~~---~--+-~---~
:J
CT
Q)
VCC= 15 V
"2R.
I
o
i
.Vj
1
-........ '--
---
-2
20~-~~~~+--+---~
10 ~-+--~---Po.:-+ ---+--'....
-4
.2
I
-6
2
5
10
20
50 100 200
RT-Timing Resistance - k Q
500
I
-25
o
25
50
75
100
Ta-Ambient Temperature -'C
821
j.lPC494C
DUTY CYCLE vs. DEAD TIME
CONTROL INPUT VOLTAGE
OPEN-LOOP VOLTAGE GAIN vs.
FREQUENCY
120
CJ)
0
"0
I
100
t:
'iij
~
10
(!)
I
Q)
Q)
~
(5
U
>-
u
20
>
........
60
a.
.;:-
0
0
..J
:::l
Cl
80
bO
30
C:
40
~
0
VCC=15 V
RT=12 kQ
CT=O.Ol JlF
40
50
2
0
~
«
20
3
10
100
Dead Time Control Input Voltage - V
2.0
1k
'"'"
LO k
100 kiM 10 M
STANDBY AND BIAS CURRENT
vs. SUPPLY VOLTAGE
12
-
I
ICC(BI)
1.8
I
-
VCE(ON)
1.6
-
~ r---
1.4
1.2
- - -
1.0
VCE(sat)
~I--
-
0.8
....-~-
0.6
o
40
80
120
~
160
IC. IE-Output Current - mA
822
~
f-Frequency - Hz
COLLECTOR SATURATION VOLTAGE
vs. OUTPUT CURRENT
0.4
'"
200
10
8
If
6
V
I
ICC(S.B)
-
~
ICC(S.B)
VCC Terminal Biased
Other Terminal Open
4
2
o
-
ICC(BI)
VOT=2 V(4 pin)
10
20
30
VCC-Supply Voltage - V
40
,uPC494C
BASIC APPLICATION CIRCUIT
Fig.2 Circuit
Vout
Output Terminal
}
JP 2
n
of S.M.P.S
rsense
Vcc
VR 3
R13
-Iosense
100
R14
7.5 k Q 5 kQ
r
c1
JP1
C6
+
110 Q
R12
110 Q
R11
47 J.lF
C2
12 V
r
E2
E1
C1
Rg
110 Q
RIO
110 Q
C5: recommend film capacitor
fosc~40 kHz
+5 V (VREF.)
CONNECTION DIAGRAM
OUTPUT
FUNCTION
OUTPUT CONTROL
INPUT (13 pin)
Push-Pull
At Ref-Out
Operation
(JP1 Wired)
Single-Ended or
Grounded
Parallel Output
(JP2 Wired)
OUTPUT VOLTAGE WAVEFORM
OUTPUT MODE
Open Collector (Rg, R10 0 n)
C1
~_o
C2
~o
E1
~_o
E2
~-o
Open Collector (Rg, R10 0 n)
C1,C2
~_o
Emitter Follower (R11, R12 0 n)
E1, E2
rLrLrLnJLfL_o
Emitter Follower (R11, R12 0 n)
823
J,lPC494C
Printed Pattern
(Pattern Side, Actual Size)
Vee
C2
E2
-Iosense
El
+ losense
Cl
Vosense
GND
GND
TYPICAL EXAMPLE OF APPLICATION CIRCUITS
1) Forward Type
+Vcc
+12 V
+
----.~-+_+___JVW-+-{)-
(12)
VCC
(8)
Cl
(3) OUTPUT
CONTROL
El
14) Ref OUT
GN
824
(9)
To EA.I1
To EA.l
(Over Current (Vo sense)
Protection)
}
Vout
j.lPC494C
2) Push-Pull Type
(Isolated)
+Vcc
GND
+12 V
To EA.II
(12)
To EA.I
~........:.(l:..;:l~) C2 VCC
(0) E
(9)
2
E1
(8) C1
GND
(7)
(13)
14)
Ref Out
(Non Isolated)
+Vcc (40 V max.)
(2)
Vcc C2 (1)
+
E2 (0)
(13)
_ } Vout
(9)
~----~------~~~~--r-~
E1~4-......,
(4) Ref Out C1 (8)
GND
To EA.II
GND
To EA.I
3) Stepdown Chopper
+Vcc (40 V max.)
I
(9)
E1
(13)
I
I
I
OUTPUT C1 (~ _.J
CONTROL
GND
To EA.II
To EA.I
1 . - . - . - - -.... (7)
(Over Current Protection)
825
j1PC494C
SYNCRONIZED OPERATION
If syncronized operation is needed, muster-slave circuit can be used. This circuit is shown bellow.
Initially, RT terminal of slave IC is connected to Pin 14 (Ref Out) and internal oscillator is stopped.
+Vee
(12)
Vee Ref
OUT
(14)
RT
(6)
(M) RT
(7)
(12)
GND eT
(M): Muster
~
(5)
(S) : Slave
Ref (14)
Vee OUT
(6)
(S) RT
(7)
GND CT
(5)
I
I
I
t next
eT terminal
MISS-OPERATION PREVENTION METHOD
If supply voltage (Vee) level drops bellow 2 V to 2.5 V, Miss-Operation Prevention Circuit is stops. But,
internal toggle flip-flop is still active condition, and each outputs section are on condition.
So, if prevention circuit from such operation is required, next circuit will be available.
+vee
2SA 1_15-2---_____
RD2.7 EB
826
BIPOLAR ANALOG INTEGRATED CIRCUIT
J1,PC494G
SWITCHING REGULATOR CONTROL CIRCUIT
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTION
The IlPC494G is an inverter control unit which provides all the control circuitry for PWM type switching regulators.
Included in this device is the voltage reference, dual error amplifiers, oscillator, pulse width modulator, pulse steering
flip flop, dual alternating output switches and dead time control.
FEATURES
• Complete PWM Power Control Circuit.
• Adjustable Dead-time (0 to 100 %).
•
No Double pulsing of same output during load transient condition.
• Dual error amplifiers have wide common mode input voltage capability (-0.3 V to V CC-2 V).
• Circuit architecture provides easy synchronization.
•
Uncommitted outputs for 250 mA sink or source.
• With Miss-operation Prevention Circuit for low level supply voltage.
•
Equivalent to TL494C.
•
Very Small Package. (SQ-16L)
CONNECTION DIAGRAM (Top View)
PACKAGE DIMENSIONS (Unit: mm)
NON
0.45 MAX.
16 IS
14
13
12
11
10
INV
INPUT
INV
INPUT
REf.
OUT
OUTPUT
CONTROL VCC
NON·
INV.
INPUT
INV.
INPUT
FEED· DEAD·
BACK TIME
CONTROL
C2
E2
EI
RT
GND
CI
9
7.35 MAX.
10.2 MAX.
r~ '~i': .05=O.l
[!1l]
0.4 ± 0.1
.
1$1 0.25 I@I
CT
MIN.
I-=~---------i
10.65 MAX.
827
,uPC494G
BLOCK DIAGRAM
Vee
Ref Out
GND
Non-Iny. Input
Iny. Input
Non-Iny. Input
Iny. Input
Feed-Back
3 ~-----'
ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Supply Voltage
Vcc
41
V
Error Amplifier Input Voltage
VICM
Vcc+0.3
V
Output Voltage
VCER
41
V
Output Current
Ic
250
mA
Total Power Dissipation
P T (Ta=25°C)
780*
mW
Operating Temperature Range
T opt
-20 to +85
°c
Storage Temperature Range
T stg
-65 to +150
°c
* 5 em x 5 em Glass-Epoxy PC board is used. (thickness t= 1.6 mm)
RECOMMENDED OPERATING CONDITIONS
CHARACTER ISTIC
VCC
Output Voltage
VCER
Output Current
IC
Error Amplifier Sink Current
IOAMP
MIN.
MAX.
UNIT
7
TYP.
40
V
-0.3
40
V
200
mA
-0.3
mA
10000
nF
- -- - - - - - f - - - - I - -
Timing capacitor
CT
0.47
Timing Resistance
RT
1.8
500
kn
1
300
kHz
-20
+70
°c
Oscillation Frequency
Operating Temperature
828
SYMBOL
Supply Voltage
fosc
T opt
--
j.lPC494G
ELECTRICAL CHARACTERISTICS (VCC=15 V, f=10 kHz, -20 ~ Ta ~ +70 DC, unless otherwise noted)
SYMBOL
MIN.
TYP.
MAX.
UNIT
Output Voltage
Vref
4.75
5
5.25
V
I re f=1 rnA, T a=25 °c
Line Regulation
REGIN
8
25
mV
7 V~VCC~40 V
I re f=1 rnA, Ta=25 ° C
Load Regulation
REGL
1
15
mV
BLOCK
Reference
Section
CHARACTERISTIC
1 mA~ Iref~10 mA, T a =25 °c
-20 °c ~Ta ~ +85 °c
I re f=1 mA
Temperature Coefficient
Vref
(Note 2)
Short Circuit Output Current
Ishort
50
mA
Vref=O, T a=25 °c
Frequency
fosc
10
kHz
CT=0.01 .uF, RT= 12 kn, T a=25 °c
10
%
0.01
(Note 1)
Oscillator
Section
TEST CONDITIONS
Standard Deviation of Frequency
Frequency Change with
Temperature
1
Frequency Change with Voltage
0.03
%/C
2
%
1
%
-10
.uA
7 V~VCC~40 V, CT, RT,·const.
T a=25 °c
o °c ~
Ta ~ 70°C, CT=0.01 .uF
RT=12 kn
7V ~VCC ~40 V, CT=0.01 .uF
T a=25°C, RT=12 kn
- - - - - - - ----_.-----------
-2
Input Bias Current
Dead-time
Control
Section
Maximum Duty Cycle
(Each Output)
45
49
Input Threshold Voltage
Common Mode
Input Voltage
I
I
High
Maximum duty cycle
0
2
10
mV
VOAMP=2.5 V
110
25
250
nA
VOAMP=2.5 V
0.2
1
.uA
VOAMP=2.5 V
Input Bias Current
Low
Zero duty cycle
3.3
VIO
Input Offset Current
-0.3
I
I
r--0pen-Ioop Voltage Amplification I Av
Unity Gain Bandwidth
i
Common Mode Rejection Radio
i
I
CMR
7 V ~VCC~40 V
V
VICM
VCC-2
60
80
dB
500
830
kHz
65
80
dB
I
I
I
I
VOAMP=0.5 V to 3.5 V, T a=25 °c
Ta=25°C
VCC=40 V, Ta=25 °c
Output Sink Current
0.3
0.7
mA
VOAMP=0.7 V
Output Source Current
-2
-10
mA
VOAMP=3.5 V
i
Standard deviation is a measure of the statistical distribution about the mean as derived from the formula;
Calculation expression of frequency fosc is as follows
f
Note 2:
VI=O
V
Vth
Input Offset Volfage
Note 1 :
%
._-
V
--
3
Error
Amplifier
Section
O~VI ~5.25
-
1
osc =c 0.817 RT-GT + 1.42.10-6
(Hz)
0=
N -1
Maximum duration of short circuit condo is one second. (non repetitive)
829
JLPC494G
BLOCK
PVVM
Section
CHARACTERISTIC
SYMBOL
MIN.
Input Threshold Voltage
Input Sink Current
0.3
Collector Cutoff Current
ICER
TYP.
MAX.
UNIT
4
4.5
V
rnA
0.7
2
Emitter Cutoff Current
TEST CONDITIONS
Zero Duty Cycle
V(pin 3)=0.7 V
100
,.,.A
VCE=40 V, VCC=40 V
-100
fJ.A
VCC=VC=40 V
VCE(sat)
0.95
1.3
V
IC=200 rnA, VE=O,
Common Emitter
VCE(ON)
1.6
2.5
V
IE=200 rnA, VC=15 V
Emitter follower
100
200
ns
100
200
ns
Collector Saturation Voltage
Output
Section
Output Voltage
Rise Time
Output Voltage
Fall Time
Total
Device
830
common
Emitter
Emitter
follower
tr
n
10=100 rnA
common
Emitter
Emitter
follower
VCC=15 V, RL=c150
70
200
ns
70
200
ns
12.5
rnA
VCC=15 V
all other inputs and outputs open
rnA
V(pin 4)=2 V, see Fig. 1
Ta=25°C
tf
Standby Current
ICC(S.B)
8
Bias Current
ICC(B!.)
10
,uPC494G
Fig. 1 Test Circuit
VCC=15 V
RL
RL
150 Q
2W
(4)
. VCC
o---~Dead time
Test Input {
12 kit
(3) Fead Back
(6) RT
(5) CT
0.01 F
(+)l
EA.
C.L
(-) Sense
(13) Output
Control
150 It
2 W
C1
E1
Output 1
C2
E2
Output 2
(_)
r--+---~(+)
Ref
Out
()
14
* Recommend film capacitor
GND
(7)
Voltage Waveform
.------VCC
Voltage at
C1
----- 0
.....----VCC
Voltage at
C2
---0
Voltage at
C3
Dead-time Control
Threshold
Input
I
1
I
I
~I--------------
I MAX.
I'O%I~
1-1
Feed Back Input
(E.A. Output)
Threshold
I
I
I
0.7 V --------------~
FUNCTION TABLE
OUTPUT CONTROL
INPUT (13 pin)
At Ref-Out
Grounded
OUTPUT FUNCTION
Normal push-pull operation
Single-ended or parallel output
831
BIPOLAR ANALOG INTEGRATED CIRCUIT
I1PC1394C
SWITCHING REGULATOR Ie FOR TV SET
The pPC1394C is a switching regurator IC especially designed for TV sets. It can be used for both type of TV sets, insulated
type and no insulated type.
It operates in synchronizing with the horizontal retrace pulse, so does not generates any visual noise in the picture on CRT.
The output transistor in a powersupply circuit is protected doubly by the internal protection circuit for over load.
ON/OFF operation of the powersupply is able to operated easily without any. mechanical relay using provided terminal. So
timer operation, remote control and etc. are very easy.
PACKAGE DIMENSIONS in millimeters
FEATURES
• Wide range of regulating input line voltage.
: AC 80 to 280 V
• The output power transistor is doubly protec~ed by the
current limitter and the shut down circuit.
7.36 MAX.
o No visual noise due to horizontal synchronous operation.
20.32 MAX.
x
1------------=---~.
I
• A terminal for remote control, timer operation and etc.
~ ~.r---------------of the powersupply is provided.
~ ~ ~~~~~~~~~~
~ ..j.
• Shut down circuit is easily resetable using ON/OFF termi10
Z
Z
nal.
~ ~
e Low stand-by and starting current. (2 rnA)
__
I
0-15"
BLOCK DIAGRAM
14 PINS
r
ON (5 V)
OFF (0 V)
832
,uPC1394C
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Current
IS
Sink of Output Terminal
30
mA
17
10
mA
Input Voltage of Current Limitter
V5
3.0
V
Input Voltage of ON/OFF Circuit
V4
Vs
V
13
1.5
mA
V2
Vs
V
VlO
-5 to Vg
V
Sink of ON/OF F Circuit
Input Voltage of Duty Limit Circuit
Input Voltage of Synchronous Circuit
External Oscillation Resistor
Ro
5 to
00
kSl
External Oscillation Capacitor
Co
o to
1
flF
V1
Vs
V
V14
Vs
V
I nput Voltage of Error Amplifier
Reference Voltage
Drain of Error Amplifier
-2
113
Input Voltage of Shut Down Circuit
V 12
to 0
mA
V
Vs
Integration Voltage of Shut Down Circuit
V6
Vs
V
Power Dissipation
Po
150 (Ta =75°C)
mW
Operating Temperature
T opt
-20
to +75
°c
Storage Temperature
T stg
-40
to +125
°c
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
CHARACTERISTICS
SYMBOL
Supply Terminal Voltage
Vs
Thermal Drift of Vs
dVS(T a)
Starting Supply Current
(1)
Starting Supply Current
(2)
CONDITION
Is=12mA
MIN.
TYP.
MAX.
UNIT
6.1
6.6
7.1
V
200
mV
1.0
1.5
mA
3.0
4.2
mA
Difference of MIN. and MAX. of Vs in
Ta from -20°C to +75 °c
IS(1 )
VS=3 V, Pin 7: Open
IS(2)
Vs = 3 V, Pin 7 : Ground
-
Starting Pulse Height
P7(S)
Vs = 3 V, Pin 7 : Open, Pin 6 : Ground
1.5
2.3
3.0
V p _p
Starting Supply Terminal Voltage
VS(S)
Pin 7 : Open, Pulse of Pin 7 = 1.5 V p _p
2.0
2.6
3.0
V
Starting Oscillation Frequency
fo(S)
Vs = 3 V, Pin 10 : Open
10
13
20
kHz
Output Pulse Height
P7
Pin 7 : Open, Pin 6 : Ground
5.0
6.0
7.1
V p _p
Drain of Output Terminal
17
Pin 7 : Ground, V2 = Vs
-6.3
-5.0
-3.7
mA
0.3
V
Saturation Voltage of Output Terminal
V7(sat)
17 = 5 mA
I ntegration Terminal Current
(1 )
16(1 )
15 = 100 MA
-700
-500
-300
MA
Integration Terminal Current
(2)
16(2)
V5=0.SV
-700
-500
-300
MA
Leak of Integration Terminal
16L
V5=0.3V
-10
Trigger Voltage of Shut Down Circuit
V6T
P7
< 100 mV p _p
Drain of Duty Limit Terminal
12
V2=3 V
Pulse Width set by Pin 2 Voltage
PL
V = 2.33 V, frequency: 15.75 kHz,
Low level period
Thermal Drift of PL
dPUT a )
V2 = 2.33 V, Difference of MIN. and MAX. of
PL in Ta from -20°C to +75 °c
0
MA
2.5
3.5
V
-20
0
MA
35
MS
2
MS
25
i
30
I
--
I
V4(ON)
13=3 mA, V3=0.3 V
3.5
V
ON Current of Pin 4
14(ON)
13=3 mA, V3=0.3 V
200
MA
Output Saturation of ON/OFF Circuit
V3(sat)
13=3mA,V4=3.5V
300
mV
1
MA
S
20
mV
53
SO
dB
-10
MA
ON Voltage of Pin 4
Leak of ON/OFF Output
Offset Voltage of Error Amplifier
Opened Gain of Error Amplifier
Cu rrent of Pi n 1
13L
V(OS)
AVO
11
1.5
2.5
V 4 = 1.5 V, V3 = Vs
Absolute Value
f : 1 kHz, Signal of Pin 13 : 1 V p _p
Pin 1 : Ground
45
833
tLPC1394C
CHARACTERISTICS
CONDITION
SYMBOL
Current of Pin 14
114
Maximum Voltage of Error Amplifier
Output
V13(MAX.)
V1 =3.5 V, V14= 3.0 V
Minimum Voltage of Error Amplifier
Output
V13(MIN.l
V1 = 2.5 V, V14= 3.0 V
Sink of Error Amplifier Output
Free Running Oscillation Amplitude
Starting Oscillation Amplitude
Thermal Drift of fo
dVso(Ta )
High level of Oscillation
VOH(S)
V
50
300
mV
/JA
4.0
V _
pp
V8= 3.0 V
0.5
1.5
Pin10:0pen
12.3
13.3
Pin 10 : Open, Difference of MIN. and MAX.
of fo in Ta from -20°C to +75 °c
2.7
3.0
Difference of MIN. and MAX. of Vso in
Ta from -20°C to +75 °c
3.8
1.0
V8 = 3.0 V
Difference of MIN. and MAX. of VOH in
Ta from -20°C to +75 °c
Synchronous Signal Voltage
Vs
Oscillation is synchronizing. (15.75 kHz)
-1.0
Synchronous Signal Current
Is
Oscillation is synchronizing. (15.75 kHz)
-200
CONNECTION DIAGRAM (Top View)
Error Voltage Input
834
5.7
250
dVOH(Ta)
Thermal Drift of VOH
/JA
3.3
VOH
Starting VOH
UNIT
-10
100
Synchronous Frequency: 15.75 kHz
Vso
MAX.
50
Vfo
dfo(Ta )
Thermal Drift of V so
TYP.
Vso
V 1 = 2.5 V, V 14 = 3.0 V, V 1 3 = 3.0 V
Pin 10 : Open
fo
Synchronous Oscillation Amplitude
5.0
113
Vfo(S)
Free Running Oscillation Frequency
MIN.
Pin 14 : Ground
Reference Voltage Input
Duty Limit
2
Error Amplifier Output
ON/OFF Output
3
Comparator Input
ON/OFF Input
4
11
Oscillation
Current Limit
5
10
Synchronization
Shut Down
6
9
Ground
Pulse Output
7
8
Power Supply
V p _p
14.3
kHz
500
Hz
3.3
V _
pp
150
mV
4.5
V
V
1.8
-40
100
mV
+0.3
V
/JA
,uPC1394C
0#1 (Error Voltage Input)
This terminal is an inversion input of error amplifier. A feedback voltage of output is applied to this.
0#2 (Duty Limit)
This terminal is for setting maximum value of output transistor's on time. This value is decided by setting the ratio of the
resistance value between terminal 2 and Vee to one between terminal 2 and 3.
This terminal can also be used for soft-start function on applying the primary voltage.
0#3 (ON/OF F Output)
0#4 (ON/OFF Input)
These terminals are used for ON/OFF control of output, so that it is convinieri"tly used for remote control of the power
source of the set.
When terminal 3 is low level, the output is on and when it is high, the output is off. It can be directly driven for low active
control signal, but for high active signal, it is convinient to use built-in ON/OFF circuit.
0#5 (Current Limit)
This terminal is used for protecting the control transistor from instantaneous overload. As input to this terminal, a waveform
similar to emitter current of the output transistor, when operating the over current limiting function, terminal 7 is kept on a
high level but a pulse is out again in the next period.
0#6 (Shut Down)
This terminal is used for shutting down the output when the overcurrent limiting function is operated. The voltage of this
terminal is rising up gradually when operating the overcurrent limiting function and it rises up certain voltage (about 3 V),
shut down function is operated.
If output shut down operation is unnecessary, terminal 6 is grounded.
0#7 (Pulse Output)
This is a Pulse output terminal for controling the output transistor. The low level is on timing of the controller. Therefore,
when overcurrent limit and shut down circuit operate, output is pulled up to high level.
0#8 (Power Supply)
This is a power supply terminal, as a shunt regulator is built in, this terminal can be connected to the primary voltage through a
resistance, the recommended range of input current is 10 to 15 mAo
0#9 (Ground)
0#10 (Synchronization)
This terminal is used for synchronizing the operation to external signal. Horizontal fly-back pulse can usually be used for this.
When synchronization is not needed, terminal 10 is left open.
0#11 (Oscillation)
0#12 (Comparator Input)
Output of error amplifier is input to this terminal. The change of input voltage is converted to the change of pulse width and it
controls the output pulse width of terminal 7.
0#13 (Error Amplifier Output)
0# 14 (Reference Voltage Input)
This terminal is a non-inversion input of error amplifier. For reference voltage, it is suitable to divide a zener diode of about
6 V into two. It can be used to the voltage of terminal 8.
835
,uPC1394C
EXAMPLE OF APPLICATIONS
1. Isolated type
AC
INPUT
+ DC
_ OUTPUT
2. No isolated type
2-1 Inverting mode
AC
INPUT
Error
JL
+
DC
OUTPUT
Current
limitter
2-2 No inverting mode
AC
INPUT
0>------1
+
DC
OUTPUT
J:
836
)LPC1394C
PATTERN OF PRINTED WIRING BOARD (Bottom View)
This printed wiring board is designed for the circuit of application 1
:"'0
r~
.'~-uL'-
D'IO
"'\ \
*J~tf'\~
-4+A~:
,
-4~
o
837
00
w
00
l:
APPLICATION 1 (Isolated type)
""C
o
w
~
::1
• •
TDK
SRW19ES-08
U)
JLFLYBACKPULSE
~
o
TDK
220 J./F +
400 V
SRW42ES-07
220 kQ
1W
22 kQ 3 Wx4
•• ,
10 kQ
-
,.. DC105 V
100 kQ
AC80 V to 280 V
2 200 pF 330 J./F
160 V
3_3 k£2
Fl4FX4
4700 pFX4
2SC3232
1 000 pFI (Under development)
TDK
SRW221S-30
2W
2SC2688
10 kQ
1.5
kQ
500
Q
18 kQ
Reray
rOFF
---1
ON(5 V)
14700 pF
APPLICATION 2 (No Isolated type)
27 k\l 3 W X 2
"""\ r
V
43 k\l
INPUT
AC 80 to 280 V
FLYBACK PULSE
5 Vp _p
250 pF
400 V
27 k\2 3 W
W
N
x2
1.0
o
c::
2SC3232
(under development)
TDK SRW2215·30
OUTPUT
5.6 mH
0.3 \1 3 W
DC 105 V
>
LL.
:::.
('t)
('t)
>
0
:: 1+
:::.
25C2688
N
N
47 k\l
JON m
~
I
(5V)
1.5kU
,
56kU
OFF
~
500 \lB
~
""C
(")
-'
W
to
~
(")
Q)
W
(0
BIPOLAR ANALOG INTEGRATED CIRCUITS
f1PC78LOO SERIES
THREE TERMINAL POSITIVE VOLTAGE REGULATORS
PACKAGE DIMENSIONS (Unit: mm)
The pPC78LOO series are monolithic three terminal positive regulators which employ internally current limiting, thermal shut down, make them
essentially indestructible. They are intended as fixedvoltage regulators in a wide range of application
includingllocal on card regulation for elimination of
distribution problems associated with single point
I
7.0 MAX.
regulation.
0.60±0.10
FEATURES
0.80±0.10
• Output current in excess of 100 mA
• No external component required
o Internal thermal overload protection
•
'1. ,1.,
ttffi¥
Internal short circuit current limiting
..
2
EQUIVALENT CIRCUIT
~........-
- - - - - - -........- - . . . . . - -__-.....--{) 1
r-:---+--+-I--~>-~~-o 2
IN PUT
3
X
L!l
::;!
~
~
1
1. INPUT
2. OUTPUT
3. GND (COMMON)
I
Q)
OJ
0
'';:;
0.6
co
~
5
>.....
4
0
Q.
.~
0
Ii
::J
.... 0.4
S::J
0
0
I
3
>
2
Q)
~
a..
I
"0
a.. 0.2
Tj=125 C
0
r--.
20
40
60
80
o
100
V out =5.0 V
~
4
VI
::J
U
.....
c
3
~
a
I---""
----
~
l-----
2
I
.Lc
~
::J
U
.....
c
Q)
(J
~
3.5
I
(J)
VIN=10 V
VOUT=5 V
IOUT=40 mA
~
co
3.0
V
~L.
30
20
10
T
o
VIN-Input Voltage-V
J..
.....
':
~
T
T
T
T
T
25
50
75
100
125
T a-Ambient Temperature- ° C
DROPOUT VOLTAGE vs.
JUNCTION TEMPERATURE
DROPOUT CHARACTERISTICS
7
J,lPC78L05
>I
VOUT=5 V
Tj=25°C
J,lPC78L05
6
ro
'';:;
>I
2
:J
-
mA-
:J
2
(5
c
LL
0
I
0
>
DROPOUT CONDITIONS
tJ, V OUT=5 % OF VOUT
o
>
o
...L
I
T
...L
T
I
M
r
W
10=40 mAA
::J
S::J 3
I
1
4
>.....
r----
:J
Q.
T
10=0
T
OJ
r--- r---.
S
r--- r--- I~ r---2
'0=10 rnA--10=100
~
5
Q)
f----
o.....
844
~
:J
co
£
r--..
,~
~
c
~
J,lPC78L05
a
CJ)
0
---
r--
E
/
Q)
,~
:J
4.0
20
/JPC78L05
~17.5
OJ
.f!o
15
>12.5
;
a.
c
>
QJ
~.
7. 5
;:;
-:.
;:= :=
;
;
o
0
>.~
+-'.~
;0
o
4
VIN=10 V
6
8
Time-/Js
12
10
Vo=5 V
100
I
;:
]V
I
o
IOUT=100 mA
(RESISTIVE LOAD)
2
;:
JI\
0
>
OUTPUT VOLTAGE
o
;;..
QJ>
::J
o.QJ
-20 0
c
.2
:
;..
f6'1
1/
o
u
0
.:: c
l\..
0
>
\
;:.
~
-10 0
to
; .~
LOAD TRANSIENT RESPONSE
« 200
E
.!.c
40
E
"\
30
20
0.7
[7
+-'
::J
S::J
0.5
0.4
0
0.3
1/
0.2
V
10
10
50 100
V
0.1
500 1 k
5 k 10k
Frequency-Hz
50 k 100 k
10
50100
500 1 k
5 k 10k
50 k 100 k
Frequency-Hz
845
BIPOLAR ANALOG INTEGRATED CIRCUITS
I1PC78MOOH SERIES
THREE TERMINAL POSITIVE VOLTAGE REGULATORS
The IlPC78MOOH series are monolithic three terminal positive regulators which employ internally current limiting, thermal shut down, and safe-area
compensation, make them essentially indestructible.
They are intended as fixed-voltage regulators in a
wide range of application including local on card
regulation for elimination of distribution problems
associated with single point regulation.
PACKAGE DIMENSIONS (Unit: mm)
10.66 MAX.
C")
r--- - 70 °C/W ~t--.
!9
"0
>.....
~
2.0
- --
1.0
0.5
~
NO
~, S/II.;
25
75
50
\
5
:J
S:J
"~ \
~
0.2
0.1
I
ClJ
OJ
0
I
a
'\
/
>
./V
\
~
"
100
J
~
V
o
o
~
1.0
0.5
10 - Output Current - A
125
Ta - Ambient Temperature _ °c
PEAK OUTPUT CURRENT AS
A FUNCTION OF INPUT/OUTPUT
DIFFERENTIAL VOLTAGE
DROPOUT VOLTAGE AS A FUNCTION
OF JUNCTION TEMPERATURE
>
~
·E
~
~
o
!. . . . . . . . . . .
-~
2.0
I
-r---r--
--__ r--r-...................
r--..
I
c:
IOUT=
~
500mA_
.....
I
~
---
:;
U
2
200 m A - I--r=:::::::-~ 100 rnA
--20m A
1 .0 ~----+-r-...~"""""'=+---+----1r---+---t---t---t----l
I
-OmA
~
co
1--_
:J
Q.
c:
-r--__
1.0
:;
S:J
o
1
..........
/
~
1.5
;
,
«
r--.-
",.-r--.. ~
0.5
o
a
-25
0
25
50
~
ClJ
Q.
o
o
75 100 125 150
5
LOAD TRANSIENT RESPONSE
(/JPC78M05H)
I
c:
I
.>co
VIN=10V
Vo=5V
a
.';=
~
ClJ
0
I
c:
ClJ
0.5 t:
IN/PUT
.....
:J
U
o
~
~
a
..J
;::
E
I
c:
a
.';=
>.....
0.5
S-
0
ClJ
OJ
j~
:J
0
:J
0
OUTPUT VOLTAGE
I
I
I
I
.....
>
.....
I
ClJ
OJ
.....
ClJ
!9
>
10 ~
"0
5 >
co
0
o
25
15
~
.>
\!~
VdLTAG~
>
1.0
:J
20
15
LINE TRANSIENT RESPONSE
(/JPC78M05H)
«
\,
I
>
10
VOl F - Input-Output Differential - V
Tj - Junction Temperature - °c
LO~O CU~RENT
..............
co
tN o/V 0=2 % 1----+--+---+--t---r---t--1
o
:J
i'-.....r---......
I
>
"0
Tj=25°C
........:..
::"Tj=125°C i'-.....~
ClJ
.:x.
ClJ
OJ
.... ~
r---.. ~
a..
u. 0.5 I--~-~-+--t--r---t--t----t---+----i
!9
~
Tj=25°C
-10 f-lo=500 mA
Vo=5 V
o
2
4
6
8
10
12
Time - /JS
851
BIPOLAR ANALOG INTEGRATED CIRCUITS
fL P C7800H
SERIES
THREE TERMINAL POSITIVE VOLTAGE REGULATORS
PACKAGE DIMENSIONS (Unit: mm)
The J.lPC7800H series are monolithic three terminal positive regulators which employ internally current limiting, thermal shut down, and safe-area
compensation, make them essentially indestructible.
They are intended as fixed-voltage regulators in a
wide range of application including local on card
regulation for elimination of distribution problems
associated with single point regulation.
Typical values unless specified
10.66 MAX.
~2MAX.
I
it
1.3'0.2
FEATURES
o Output current in excess of 1 A
o No external component required
o Internal thermal overload protection
o Internal short circuit current limiting
o Low output resistance 17 mn
I
1.3
O.5!O.2
2B:8llJl
2.542.54
JEDEC : TO-220AB
IEC
EQUIVALENT CIRCUIT
1 IN
CONNECTION DIAGRAM
GNO
NEC
JAPAN
78XX
01
1 3
2
I t \
IN
3 GNO
852
GNO
OUTPUT
JLPC7800H SERIES
TYPICAL APPLICATION
INPUT
J..LPC78XXH
0.33 J..LF
Notes:
Cl
2
OUTPUT
3
*
Although no output capacitor is needed for
stability. it does improve transient response.
* * Required if regulator is located an appreciable
distance from power supply filter.
ABSOLUTE MAXIMUM RATINGS
Input Voltage
{
Internal Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature
Operating Junction Temperature Range
Operating Junction Temperature Range
V
V
(5 V through 18 V) 35
(24 V) 40
Internally Limited
-20 to +80
-55 to +150
Soldering 10 s 230
o to 125
o to 200
°c
°c
°c
°c
°c
(Continuous)
(short t~rm, 30 min. MAX.)
ELECTRICAL CHARACTERISTICS pPC7805H (VIN=10 V, 10=500 rnA, 0 ° C ~ Tj~ 125 ° C)
CHARACTERISTIC
Output Voltage
SYMBOL
MIN.
TYP.
MAX.
4.8
5.0
5.2
Vo
Load Regu lation
REGIN
IBIAS
Quiescent Current Change
1::.IBIAS
7 V':sYIN~20 V, 5 mA~lo~ 1.0 A, PT~15 W
100
Tj=25 °c, 7 V~VIN~25 V
1
50
15
100
5
50
4.2
8.0
1.3
mV
Tj=25
mV
mA
mA
NL
Ripple Rejection
62
0
Tj=25
0
C, 250 mA~lo~750 mA
Tj=25
0
C
7 V,:S,vIN~25 V
C, 10 Hz~f~100 kHz
40
J..LV
T a=25
78
dB
f=120 Hz, 8 V~VIN;;:;'18 V
0
Dropout Voltage
2.0
V
Output Resistance
17
mn.
f=1 kHz
Ro
C, 8 V~VIN~ 12 V
Tj=25 °c, 5 mA~lo<1.5 A
5 mA~lo~1.0 A
0.5
Output Noise Voltage
Tj=25°C
5.25
REGL
Quiescent Current
V
TEST CONDITONS
3
4.75
Line Regula!ion
UNIT
10 =1.0 A, Tj=25
Short Circuit Current
loshort
750
mA
Tj=25
0
C
Peak Output Current
lopeak
2.2
A
Tj=25
0
C
Temperature Coefficient
of Output Voltage
1::. Vol1::.T
-1.1
mVtC
0
C
10=5 mA, 0 °C~Tj~125
0
C
853
tlPC7800H SERIES
°c ~
ELECTRICAL CHARACTERISTICS f.LPC7808H (VIN=14 V, 10=500 rnA, 0
CHARACTERISTIC
Output Voltage
SYMBOL
Load Regulation
TYP.
MAX.
7.7
8.0
8.3
8.4
10.5 V;SYIN~23 V, 5 mA~lo~1.0 A, PT~15 W
6.0
160
Tj=25 °c, 10.5 V~VIN~25 V
2.0
80
12
160
4.0
80
4.3
8.0
Vo
REGIN
REGL
Quiescent Current
IBIAS
Quiescent Current Change
A IBIAS
Output Noise Voltage
1.0
V
mV
mV
mA
mA
56
Tj=25°C
Tt25°C, 11 V;:;;YIN~17 V
Tj=25 °c, 5 mA~lo~1.5 A
Tj=25 ° C, 250 mA~lo~750 mA
Tj=25 0 C
10.5 V~VIN~25 V
5 mA~lo~ 1.0 A
0.5
NL
Ripple Rejection
TEST CONDITIONS
UNIT
MIN.
7.. 6
Line Regulation
52
J.LV
T a=25 °c, 10 Hz~f ~1 00 kHz
72
dB
f=120 Hz, 11.5 V~VIN~21.5 V
10 =1.0 A, Tj=25 ° C
Dropout Voltage
2.0
V
Output Resistance
Ro
18
mn
f=1 kHz
lopeak
350
A
Tj=25 ° C
Peak Output Current
lopeak
2.2
A
Tj=25 ° C
Temperature Coefficient
of Output Voltage
AVo/AT
Short Circuit Current
-0.8
mV/oC
10=5 mA, 0 °C~Tj~125 ° C
ELECTRICAL CHARACTERISTICS f.LPC7812H (VIN=19 V, 10=500 rnA, 0
CHARACTERISTIC
Output Voltage
SYMBOL
MIN.
TYP.
MAX.
11.5
12.0
12.5
Vo
.11.4
Line Regulation
Load Regulation
REGL
IBIAS
Quiescent Current Change
tJ.IBIAS
Output Noise Voltage
V
55
Tj ~ 125°C)
Tj=25 ° C
14.5 V~VIN~27 V, 5 mA~lo~1.0 A, PT~15 W
mV
Tj=25
0
C, 14.5 V~VIN~30 V
3.0
120
Tj=25 °c, 16 V~VIN~22 V
12
240
Tt25 ° C, 5 mA~lo~1.5 A
4.0
120
4.3
8.0
mV
mA
mA
Tj=25 ° C, 250 mA~lo~750 mA
T(25 ° C
14.5 V~VIN~30 V
5 mA~lo~1.0 A
0.5
NL
°c ~
TEST CONDITIONS
75
J.LV
T a=25° C, 10 Hz~f~100 kHz
71
dB
f=120 Hz, 15
2.0
V
Ro
18
mn
loshort
350
rnA
Tj=25 ° C
Peak Output Current
lopeak
2.2
A
Tj=25 ° C
Temperature Coefficient
of Output Voltage
tl Vol tl T
-1.0
mV/oC
V~VIN~25
V
10 =1.0 A, Tj=25 ° C
Dropout Voltage
Output Resistance
Short Circuit Current
aS4
240
1.0
Ripple Rejection
UNIT
12.6
10
REGIN
Quiescent Current
Tj ~ 125°C)·
f=1 kHz
10=5 rnA, 0 °C~Tj~125 ° C
j.lPC7800H SERIES
ELECTRICAL CHARACTERISTICS }1PC7815H (VIN=23 V, 10=500 rnA, 0 °c ~ Tj ~ 125°C)
CHARACTERISTIC
Output Voltage
SYMBOL
Vo
MIN.
TYP.
14.4
15.0
14.25
Line Regulation
Load Regulation
Quiescent Current
Quiescent Current Change
REGIN
REGL
IBIAS
MAX.
15.6
UNIT
V
11
300
150
12
300
4.0
150
4.4
8.0
1.0
t:.IBIAS
mV
NL
Ripple Rejection
54
Dropout Voltage
Output Resistance
Tj=25 DC, 17.5 V':s'VIN,:S,30 V
Tj=25 DC, 20 V':s'VIN,:S,26 V
mV
Tj=25 DC, 5 mA,:S,l o,:S,1.5 A
Tj=25 DC, 250 mA,:S,lo,:S,750 mA
mA
mA
0.5
Output Noise Voltage
Tj=25°C
17.5 V~VIN,:S,30 V, 5 mA~.lo~1.0 A, PT,:S,15 W
15.75
3.0
TEST CONDITIONS
Tj=25°C
17.5 V~VIN,:S,30 V
5 mA~lo':s'1.0 A
90
pV
T a=25 DC, 10 Hz~f,:S,100 kHz
70
dB
f=120 Hz, 18.5
2.0
V
Ro
19
mrl
f=1 kHz
V~VIN~28.5
V
10 =1.0 A, Tj=25 ° C
Short Circuit Current
loshort
230
mA
Tj=25°C
Peak Output Current
lopeak
2.1
A
Tj=25°C
Temperature Coefficient
of Output Voltage
t:. Vo/t:.T
-1.0
mV/oC
10=5 mA, 0 °C,:S,Tj~ 125 ° C
ELECTRICAL CHARACTERISTICS }1PC7818H (VIN=27 V, 10=500 rnA, 0 °c ~ Tj ~ 125°C)
CHARACTERISTIC
Output Voltage
SYMBOL
Vo
MIN.
TYP.
MAX.
17.3
18.0
18.7
17.1
Line Regulation
Load Regulation
IBIAS
Quiescent Current Change
t:.IBIAS
Output Noise Voltage
360
REGIN
Quiescent Current
5.0
180
12
360
4.0
180
4.5
8.0
1.0
Ripple Rejection
53
TEST CONDITIONS
Tj=25 ° C
21 V':s'VIN,:S,33 V, 5 mA,:S,lo,:S,1.0 A, PT,$15 W
mV
mV
Tj=25 ° C, 21 V~YIN~33 V
Tj=25 ° C, 24 V,$VIN~30 V
Tj=25 ° C, 5 mA~lo,$1.5 A
Tj=25 ° C, 250 mA,$lo,$750 mA
rnA
rnA
Tj=25 ° C
21 V,:S,VI N,$33V
5 mA~lo,$1.0 A
0.5
NL
Dropout Voltage
V
18.9
15
REGL
UNIT
110
IJ-V
T a=25 DC, 10 HZ,:S,f,$100 kHz
69
dB
f=120 Hz, 22
2.0
V
10 =1.0 A, Tj=25 °c
Ro
22
rnrl
f=1 kHz
Short Circuit Current
loshort
200
rnA
Tj=25°C
Peak Output Current
lopeak
2.1
A
Tj=25°C
Temperature Coefficient
of Output Voltage
t:. Vo/t:.T
-1.0
mV/oC
Output Resistance
V,$VIN~32
V
10=5 rnA, 0 °C,$Tj,:S, 125 ° C
855
JLPC7800H SERIES
ELECTRICAL CHARACTERISTICS J.LPC7824H (VIN=33 V, 10=500 rnA, 0 °c ~ Tj ~ 125°C)
CHARACTERISTIC
SYMBOL
Output Voltage
MIN.
TYP.
MAX.
23.0
24.0
25.0
Vo
22.8
Line Regulation
REGIN
Load Regulation
REGL
Quiescent Current
IBIAS
Quiescent Current Change
l!.IBIAS
480
mV
Ripple Rejection
50
Dropout Voltage
Tj=25 °c, 27 V~VIN~38 V
6
240
Tj=25 ° C, 30 V~VIN~36 V
480
Tj=25 ° C, 5 mA;Slo;S 1.5 A
4.0
240
4.6
8.0
mV
Tj=25
mA
mA
0.5
NL
Output Resistance
27 V~VIN~38 V, 5 mA~lo~1.0 A
12
1.0
Output Noise Voltage
Tj=25 ° C
V
25.2
18
TEST CONDITIONS
UNIT
0
C, 250 mA~lo~750 mA
Tj=25°C
27 V~VIN~38 V
5 mA,$lo;S1.0 A
170
p.V
Ta=25° C, 10 Hz~f.:s100 kHz
66
dB
f=120 Hz, 28 V~VIN~38 V
2.0
V
10=1.0 A, Tj=25 ° C
Ro
28
mn
f=1 kHz
Short Circuit Current
loshort
150
mA
Tj=25 ° C
Peak Output Current
lopeak
2.1
A
Tj=25 ° C
Temperature Coefficient
of Output Voltage
l!. Vo/l!.T
-1.5
o
mV/ C 10=5 rnA, 0 ° C~Tj~ 125 ° C
TYPICAL CHARACTER ISTICS (Ta=25 °C)
WORST CASE POWER DISSIPATION vs.
AMBIENT TEMPERATURE
100
CURRENT LIMITING CHARACTERISTICS
6
50
~
I
c
.g
10
5.0
(5
~
Q)
3:
0
a..
I
'C
a..
()HS===O
~
20
(tl
.~
2.0
1.0
0.5
--
--
0.1
25
>
...........
I
Q)
()HS"",o
° ""
'\
~1!8/",
\
,
'~
50
75
4
Cl
~
0.2
100
!9
0
>
.....
3
::::l
B
2
::::l
0
\
VIN=10 V
Vo=5 V
-Tj=25°C
'\.
o
o
125
T a - Ambient Temperature -
856
J.LPC7J05H
5
0
C
I
0.4
V
0.8
I
---
1.2
,."
1.6
J
/
2.0
10 - Output Current - A
JLPC7800H SERIES
>
PEAK OUTPUT CURRENT AS
A FUNCTION OF INPUT/OUTPUT
DIFFERENTIAL VOLTAGE
DROPOUT VOLTAGE AS A FUNCTION
OF JUNCTION TEMPERATURE
2.5...---..--..,.--,--.....,---r----r-...,-----,
«
I
co
'';::::;
c
I
2.0 I--+---+-~I-=-+---+-
....c
1. 51---+--+-==~....::::=......o;;::-+-
U
Q)
~o
;
0.
;
2
t
::J
....
::J
E::J
0
1 .0 I---+~'""'_,,-l__-+---+---'-----+-__j
~
::J
co
0.
Cl...
Q)
C
I
0.51--+---I--~-I---+--+--+--l
~
Cl...
co
Q)
o
0.
>
2.5
o
-25
0
25
50
75
0
100 125
Tj - Junction Temperature -
0
0
C
LOAD TRANSIENT RESPONSE
>
I
.;;
Q)
o
Q)
OJ
VIN=10 V
:
~
~
1.0
;
0.5
;
0
0.
o
Vo~5 V
~
::
I
....c
U
co
.;;
"0
Q)
co
a
...J
20
~
Time -lots
40
Q)
~
OJ
~
0
10
E::J
O
I
g -10
50
60
15
~
1o
.'S
OJ
"0
5 ::
::;:
:;:
o
~
;~
o
::J
0.
C
Output Voltage
-
1.....
I
0
30
>
IotPC7805H
0
>
10
I
.~
~::J
/",
I
Input Voltage
I
c
0
o
;r:-
I
E
t
::J
~
>
0.5
Output Voltage
::J
~ -1.0
o
:~
V~
~ -0.5
3.6±O.2
~2MAX.
I
cri
-fl-
1.3.0.2
FEATURES
•
•
•
•
•
Output current in excess of 1 A
No external component required
Internal thermal overload protection
Internal short circuit current limiting
Low output resistance 70 mn
2.542.54
JEDEC : TO-220AB
IEC
EQUIVALENT CIRCUIT
r-~------~----~~------~~------~--~~~~lGND
CONNECTION DIAGRAM
D,
INPUT
NEC
JA~AN
79xx
r--t--+--o
2 OUTPUT
0,
,
3 2
It\
GND INPUT OUTPUT
'-------------.-.... . . . . .--------<~.-...-------~-.......
NOTE:
858
®
®
__o
-5 V to -8 V OPTIONS
-12 V to -24 V OPTIONS
3 Fin
INPUT
tlPC7900H SERIES
TYPICAL APPLICATION
THERMAL RESISTANCE
RTH(j-c)
INPUT
3
0.33 J..LF
Notes:
J..LPC79XXH
OUTPUT
2
4 °C/W TYP.
83 °C/W TYP.
RTH(j-a)
C1
*
Although no output capacitor is needed for
stability, it does improve transient response.
** Required if regulator is located an appreciable
distance from power supply filter.
ABSOLUTE MAXIMUM RATINGS
v
Input Voltage
,uPC7905H, 08H, 12H, 15H, 18H, 24H -35
,uPC7924H
-40
Internal Power Dissipation
Internally Limited
Operating Temperature Range
-20 to +80
Storage Temperature Range
-55 to +150
Lead Temperature
Soldering 10 s 230
Operating Junction Temperature Range
o to 125
o to 200
Operating Junction Temperature Range
V
°c
°c
°c
°c
°c
(Continuous)
(short term, 30 min. MAX.)
ELECTRICAL CHARACTERISTICS JlPC7905H (VIN=-10 V, 10=500 rnA, 0 °c ~ Tj ~ 125°C)
CHARACTER ISTIC
Output Voltage
SYMBOL
MIN.
TYP.
-4.S
-5.0
Load Regulation
Quiescent Current
Quiescent Current Change
Output Noise Voltage
100
1
50
70
150
20
SO
1.0
2.0
REGL
IBIAS
mV
mV
mA
1.3
mA
AIBIAS
0.5
NL
-7 V~VIN~-20 V, 5 mA~lo~1.0 A, PT~15 W
Tj=25 °c, -7 V~VIN~-25 V
Tj=25 °c, -S V~VIN~-12 V
Tj=25 °c, 5 mA~lo~1.5 A
Tj=25 °c, 250 mA~lo~750 mA
Tj=25 °c
-7 V~VIN~-25 V
5 mA~lo~1.0 A
100
J..LV
Ta=25 °c, 10 Hz~f~100 kHz
62
dB
f=120 Hz, -S V~VIN~-1S V, 10=500 mA
1 .1
V
10 =1.0 A, Tj=25 °c
lopeak
2.1
A
Tj=25 °c
AVO/AT
-0.4
mVrC
54
Dropout Voltage
Peak Output Current
-5.25
3
TEST CONDITIONS
Tj=25 °c
V
REGIN
Ripple Rejection
Temperature Coefficient
of Output Voltage
UNIT
-5.2
Vo
-4.75
Line Regulation
MAX.
10=5 mA, 0 °C~Tj~125 °c
859
j.lPC7900H SERIES
ELECTRICAL CHARACTERISTICS MPC7908H (VIN=-14 V, 10=500 rnA, 0 °c ~ Tj ~ 125°C)
CHARACTER ISTIC
Output Voltage
SYMBOL
MIN.
TYP.
MAX.
-7.7
-8.0
-8.3
Vo
Load Regulation
Quiescent Current
Tj=25°C
V
-8.4
-10.5 V~VIN~-23 V, 5 mA~lo~l.O A, PT~15 W
6.0
160
Tj=25 °c, -10.5 V~VIN~-25 V
2.0
80
80
200
30
100
1.0
2.0
-7.6
Line Regulation
rnV
REGIN
REGL
IBIAS
rnV
rnA
1.0
Quiescent Current Change
Output Noise Voltage
rnA
AIBIAS
0.5
Tj=25 °c, 5 mA~lo~1.5 A
Tj=25 °c, 250 rnA~lo~750 mA
Tj=25°C
-10.5 V~VIN~-25 V
5 mA~lo~1.0 A
J.l.V
Ta=25 °c, 10 Hz~f~100 kHz
62
dB
f=120 Hz, -11.5 V ~ VIN ~ -21.5 V, 10=500 mA
1.1
V
10 =1.0 A, Tj=25 °c
lopeak
2.1
A
Tj=25°C
AVo/AT
-0.6
mVrC
NL
54
Dropout Voltage
Peak Output Current
Tj=25 °c, -11 V~VIN~-17 V
200
Ripple Rejection
Temperature Coefficient
of Output Voltage
TEST CONDITIONS
UNIT
10=5 mA, 0 °C~Tj~125 °c
ELECTRICAL CHARACTERISTICS MPC7912H (VIN=-19 V, 10=500 rnA, 0 °c ~ Tj ~ 125°C)
CHARACTER ISTIC
Output Voltage
SYMBOL
MIN.
TYP.
MAX.
-11.5
-12.0
-12.5
Vo
Line Regulation
Load Regulation
Quiescent Current
Quiescent Current Change
Output Noise Voltage
REGIN
IBIAS
8S0
10
240
3.0
120
85
240
30
120
1.5
3.0
rnV
rnA
1.0
rnA
AIBIAS
0.5
-14.5 V~VIN~-27 V, 5 rnA~lo~1.0 A, PT~15 W
Tj=25 ° C, -14.5 V~V I N~-30 V
Tj=25 °c, -16 V~VIN~-22 V
Tj=25 °c, 5 rnA~lo~1.5 A
Tj=25 °c, 250 rnA~lo~750 rnA
Tj=25°C
-14.5 V~VIN~-30 V
5 mA~lo~1.0 A
300
J.l.V
Ta=25 °c, 10 Hz~f~100 kHz
62
dB
f=12C Hz, -15 V~VIN~-25 V, 10=500 rnA
1.1
V
10 =1.0 A, Tj=25 ° C
lopeak
2.1
A
Tj=25°C
AVo/AT
-0.8
rnVrC
NL
54
Dropout Voltage
Peak Output Current
-12.6
rnV
REGL
Ripple Rejection
Temperature Coefficient
of Output Voltage
Tj=25°C
V
-11.4
TEST CONDITIONS
UNIT
10=5 mA, 0 °C~Tj~125 °c
jlPC7900H SERIES
ELECTRICAL CHARACTERISTICS IlPC7915H (VIN=-23 V, 10=500 rnA, 0 °c ~ Tj ~ 125°C)
CHARACTERISTIC
Output Voltage
SYMBOL
MIN.
TYP.
-14.4
-15.0
Vo
-14.25
Line Regulation
Load Regulation
Quiescent Current
Quiescent Current Change
Output Noise Voltage
REGIN
11
300
3.0
150
90
300
30
150
IBIAS
1.5
3.0
1.0
~IBIAS
mV
mA
mA
0.5
NL
TEST CONDITIONS
Tj=25°C
V
mV
-17.5 V~VIN~-30 V, 5 mA~lo~1.0 A, PT~15 W
Tj=25 ° C, -17.5 V~V I N~-30 V
Tj=25 ° C, -20 V~V I N~-26 V
Tj=25 °c, 5 mA~lo~1.5 A
Tj=25 °c, 250 mA~lo~750 mA
Tj=25°C
-17.5 V~VIN~-30 V
5 mA~lo~1.0 A
375
JJ.V
Ta=25 °c, 10 Hz~f~100 kHz
60
dB
f=120 Hz, -18.5 V~VIN~-28.5 V, 10=500 mA
1.1
V
10 =1.0 A, Tj=25 °c
lopeak
2.1
A
Tj=25°C
~Vo/AT
-1.0
mV/oC
54
Dropout Voltage
Peak Output Current
UNIT
-15.6
-15.75
REGL
Ripple Rejection
Temperature Coefficient
of Output Voltage
MAX.
10=5 mA, 0 °C~Tj~125 °c
ELECTRICAL CHARACTERISTICS IlPC7918H (VIN=-27 V, 10=500 rnA, 0 °c ~ Tj ~ 125°C)
CHARACTER ISTIC
Output Voltage
SYMBOL
MIN.
TYP.
MAX.
-17.3
-18.0
-18.7
Vo
-17.1
Line Regulation
Load Regulation
Quiescent Current
360
mV
IBIAS
Output Noise Voltage
180
Tj=25 °c, -24 V~VIN~-30 V
360
Tj=25 °c, 5 mA~lo~1.5 A
30
180
1.5
3.0
mA
Temperature Coefficient
of Output Voltage
0.5
NL
54
Dropout Voltage
Peak Output Current
mA
~IBIAS
Ripple Rejection
Tj=25 °c, -21 V~VIN~-33 V
90
1.0
Quiescent Current Change
-21 V~VIN~-33 V, 5 mA~lo~1.0 A, PT~15 W
5.0
mV
REGL
TEST CONDITIONS
Tj=25°C
V
-18.9
15
REGIN
UNIT
Tj=25 °c, 250 mA~lo~750 mA
Tj=25°C
-21 V~VIN~-33 V
5 mA~lo~1.0 A
450
JJ.V
Ta=25 °c, 10 Hz~f~100 kHz
60
dB
f=120 Hz, -22 V~VIN~-32 V, 10=500 mA
1.1
V
10 =1.0 A, Tj=25 °c
lopeak
2.1
A
Tj=25°C
AVo/AT
-1.0
mVrC
10=5 mA, 0°C~Tj~125 °c
861
j.lPC7900H SERIES
ELECTRICAL CHARACTERISTICS IlPC7924H (VIN=-33 V, 10=500 rnA, 0 °c ~ Tj ~ 125°C)
CHARACTER ISTIC
SYMBOL
Output Voltage
Vo
MIN.
TYP.
MAX.
-23.0
-24.0
-25.0
Line Regulation
-25.2
18
480
6
240
90
480
mV
REGIN
Load Regulation
mV
REGL
Quiescent Current
IBIAS
30
240
1.5
3.0
1.0
Quiescent Current Change
Tj=25°C
V
-22.8
AIBIAS
TEST CONDITIONS
UNIT
mA
mA
0.5
-27 V~VIN~-38 V, 5 mA~lo~1.0 A
Tj=25 DC, -27 V~VIN~-38 V
Tj=25 DC, -30 V~VIN~-36 V
Tj=25 ° C, 5 mA~ lo~ 1.5 A
Tj=25 DC, 250 mA~lo~750 mA
Tj=25°C
-27 V~V I N~....;38 V
5 mA~lo~1.0 A
600
J.LV
Ta=25 DC, 10 Hz~f~100 kHz
59
dB
f=120 Hz, -28 V ~ VIN ~ -38 V. 10=500 mA
Dropout Voltage
1.1
V
10=1.0 A, Tj=25 ° C
Peak Output Current
lopeak
2.1
A
Tj=25°C
AVo/AT
-1.0
mVrC
Output Noise Voltage
NL
Ripple Rejection
51
Temperature Coefficient
of Output Voltage
10=5 mA, 0 °C~Tj~125 °c
TYPICAL CHARACTERISTICS (Ta=25 °C)
WORST CASE POWER DISSIPATION vs.
AMBIENT TEMPERATURE
100
CURRENT LIMITING CHARACTERISTICS
-6
50
~
I
c
.g
20
10
C1J
Q.
:~
5.0
'-
2.0
0
Q)
~
0
.e..
I
."0
1.0
-~
0.5
,e..
fJHS""70 ° "
~
-~
~il".\'/""
\
,
'~
0.2
0.1
25
-5
~ r--......
50
75
100
....::J
\
"
125
T a - Ambient Temperature - °c
862
J
0..
:; -2
o
VIN=-10 V
J.LPC7905H
-1 t - Tj=25 °c
o
o
I
0.4
V
0.8
/
/
~ V1.2
1.6
2.0
10 - Output Current - A
tlPC7900H SERIES
PEAK OUTPUT CURRENT AS
A FUNCTION OF INPUT/OUTPUT
DIFFERENTIAL VOLTAGE
~So
0.5
:
0.5
,0
/'..
1.0
VIN=-10 V
j.LPC7905H
Cl
~
--"
25
"0
..::
>
CIN. COUT=O
o
30
20
VDIF - Input-Output Differential - V
10
I -20
co
~ -15
I
I
::J
C.
.=:
~
\
I
Q)
\
-10
u
c
co
==
--==
-
Q)
Cl
>....
40
60
Time -
j.LS
80
100
OUTPUT IMPEDANCE AS A
FUNCTION OF FREQUENCY
LINE TRANSIENT RESPONSE
>
\
;.I
0
" ,,-2$
~.
~
Q)
0.5
co
+-'
B::J
1.0
u
~
u
LOAD TRANSIENT RESPONSE
-5
E
I
c.
~
E
"-
V
0
\
:J
B::J
Q)
Cl
~
10=200 mAo Tj=25 °c
>....
C.
:;
0
0.1
0
+5
"0
::J
V
....
j.LPC7905H
o
20
40
Time
60
-j.LS
0.01
80
100
10
100
1k
10 k
100 k
Frequency - Hz
863
1. ALPHA-NUMERICAL INDEX
2. QUICK REFERENCE GUIDE
3. CROSS REFERENCE GUIDE
4. MAINTENANCE AND OBSOLETE TYPES
5.
GENERALSTATEMENT
*
NEC's INTEGRATED CiRCUITS FOR CONSUMER USE
o History
Types and Features
0
o Type Number Designation
0
Device Technologies
* STANDARDS OF INTEGRATED CIRCUITS
* HINTS ON CORRECT USE
*
TECHNICAL SYMBOLS AND TERMS
*
RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
6- 1.
' CAR AUDIO' '"
6~2."
HOME AUDtO '
6- 3.
PORT~BLE AUDIO:
,
,
'
7. TVAP'PtfCATlONS,' "
'.,
,.
.'
",
".).
,".>
~
9.
,
"
CLO:CK~~wAt¢fU:~
'-l,~ <
'"lo~VOCiAGEiflEGlJtA=tOA:S"
ARRAYS
INDEX
Page
tlPA53C
5-Unit NPN Darlington Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . 870
tlPA54H
6-Unit Diode Array (Common Cathode) . . . . . . . . . . . . . . . . . . . . . . . . . 872
tl PA5 6C
7-Unit NPP Single Transistor Array . . . . . . . . . . . . . . -. . . . . . . . . . . . . . 874
tlPA64H
6-Unit Diode Array (Common Anode) . . . . . . . . . . . . . . . . . . . . . . . . . . 878
tlPA67C
6-Unit NPN Darlington Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . 880
J,tPA79C
7-Unit NPN Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 882
tlPA80C
7-Unit PNP-NPN Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . 884
tlPA81C
7-Unit NPN Darlington Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . 886
tlPA2001C
7-Unit NPN Darlington Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . 888
J,tPA2002C
7-Unit NPN Darlington Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . 888
tl PA2 0 03C
7-Unit NPN Darlington Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . 888
tlPA2004C
7-Unit NPN Darlington Transistor Array . . . . . . . . . . . . . . . . . . . . . . . . . 888
867
ARRAYS
• TRANSISTOR ARRAYS
J.(PA53C:
J.(PA56C:
LED, LAMP, PRINTER HUMMER DRIVER
LED, LAMP DRIVER
ABSOLUTE
MAXIMUM RATINGS
ABSOLUTE
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
SYMBOL
RATINGS
UNIT
SYMBOL
TYP.
UNIT
VCEO
30
V
hFE
3200
-
IC
0.4
A/unit
VCE(sat)1
0.9
V
PO-
1.2
W/pkg
VCE(sat)2
1.3
V
ELECTRICAL CHARACTERISTICS
SYMBOL
RATINGS
UNIT
SYMBOL
TYP.
UNIT
TEST
CONDITIONS
V
IC-200mA
VCEO
40
V
hFE2
200
-
VCEK1.0 V
IC-50mA
Ic-lOOmA
VIN~5.0 V
IC
0.1
A/unit
VCE(sat)2
0.2
V
IC-50mA
IB~5 mA
Po
0.55
W/pkg
VBE(sat)
0.B6
V
TEST
CONDITIONS
VCE~5.0
IC~4oo
mA
mA
mA
IC~50
IB~5
VIN-20 V
• PW=IO ms, duty cycle;:;;; 10 %
OUT
J.(PA67C:
J.(PA79C:
PRINTER HUMMER DRIVER
ABSOLUTE
MAXIMUM RATINGS
PRINTER HUMMER DRIVER
ABSOLUTE
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
UNIT
TEST
CONDITIONS
mA
VIH~5.0 V
VCC-2.0 V
SYMBOL
RATINGS
UNIT
Vo
30
V
10·
0.15
A/unit
10FF
-/10
p.A
VIL;:;;;1.0V
VCC=20V
Po
0.55
W/pkg
VOL
-/1.3
V
VI-13V
10·100mA
SYMBOL
ION
MIN./MAX.
100/-
ELECTRICAL CHARACTERISTICS
SYMBOL
RATINGS
UNIT
SYMBOL
Vo
20
V
hFE
10·
0.15
A/unit
VCE(sat)
Po
0.55
W/pkg
• PW-20 ms, duty cycle;:;;; 10 % (All units turned on)
VI
UNIT
TEST
CONDITIONS
-
VCC-5 V
VCE-l V
10-120mA
-/0.6
V
VCC-5 V
IOE120mA
11~0.2 mA
-/4.0
V
VCC"'5V
VCE-l V
10-120 mA
TYP./MAX.
2500/-
• PW;:;;; 30 ms, duty cycle;:;;; 10 % (The same current for all units)
OUT
J.(PA80C:
J.(PA81C:
FIP, LED DRIVER
LED, LAMP, PRINTER HUMMER DRIVER
ABSOLUTE
MAXIMUM RATINGS
ABSOLUTE
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
SYMBOL
RATINGS
UNIT
SYMBOL
TYP.
UNIT
TEST
CONDITIONS
VSS
-60
V
hFEl
280
-
VCE-2.0 V
10~20 mA
10
50
mA/unit
hFE2
450
-
VCE=2.0 V
Po
0.55
W/pkg
VCE(sat)
0.95
V
10~40mA
10·20mA
11~0.3mA
ELECTRICAL CHARACTERISTICS
SYMBOL
RATINGS
UNIT
SYMBOL
TYP.
UNIT
TEST
CONDITIONS
VCC
45
V
hFE
2500
-
VCE=2.5 V
10=200 mA
10·
0.4
A/unit
VCE(sat)1
0.82
V
110=100mA
VI=13V
Po
0.8
W/pkg
VCE(sat)3
1.2
V
10=400 mA
VI-13V
• PW=10 ms, duty cycle;:;;; 10 % (All units turned on)
GNO'
20 kn
OUT
20 kn
IN
20 kn
OUT
100 kn
Vss
8S8
20 kn
ARRAYS
pPA2001C,2002C,2003C,2004C:
LED, LAMP, RELAY, PRINTER HUMMER DRIVER
ABSOLUTE
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
SYMBOL
RATINGS
UNIT
SYMBOL
TYP.
UNIT
TEST
CONDITIONS
VCC
60
V
hFE
2800
-
VCE-2.0 V
10-350mA
10
0.5
A/unit
VCEIsatl1
0.9
V
10-100mA
11-250j.lA
PO"
2.5
W/pkg
VCEIsatl3
1.2
V
10-350 mA
II-SOOj.lA
"PA2001C
" PW ~ 20 ml, duty cycle::;; 10 % IThe same current for all unitsl
j.lPA2003C
SK
SK
~____~~~~~OUT
~~~~r-~--~OUT
• DIODE ARRAYS
ILPA54H:
pPA64H:
HIGH SPEED SWITCHING
HIGH SPEED SWITCHING
ABSOLUTE
MAXIMUM RATINGS
ABSOLUTE
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
SYMBOL
RATINGS
UNIT
SYMBOL
VRM
75
V
VR
50
V
10
0.1
PD
0.3
TEST
CONDITIONS
ELECTRICAL CHARACTERISTICS
RATINGS
UNIT
SYMBOL
IF-30 mA
VRM
75
V
VF
0.8
V
IF-30 mA
"A
VR-30 V
VR
50
V
IR
0.005
j.lA
VR-30 V
2.0
pF
VR-O
f-1.0 MHz
10
0.1
A/unit
Ct"
5.0
pF
VR-O
f-1.0 MHz
1.3
ns
Refer to the
individual
catalogue.
Po
0.3
W/pkg
trr
4.0
ns
Refer to the
individual
catalogue.
UNIT
VF
O.B
V
IR
0.01
A/unit
Ct "
W/pkg
trr
" 1 unit
2
3
4
5
6
TYP.
UNIT
TEST
CONDITIONS
SYMBOL
TYP.
" 1 unit
ICommon Cathode I
2
3
4
5
6
7
ICommon Anodel
8S9
TRANSISTOR ARRAY
pPA53C
LED, LAMP DRIVER
NPN SILICON EPITAXIAL DARLINGTON TRANSISTOR ARRAY
DESCRIPTION
The pPA53C is a monolithic array of five darlington transistors.
Applications are printer hummer driver and .LED display driver with MOS output signal.
FEATURES
PACKAGE DIMENSIONS
• High DC Current Gain
in millimeters (inches)
• High Output Drive Current
• Package is 14pin PLASTIC DIP.
ABSOLUTE MAXIMUM RATINGS
Maximum Voltages and Currents (Ta = 25°C)
Collector to Base Voltage (RBE=oo)
Collector to Emitter Voltage (Open Base)
I r'lput Voltage
.
Continuous Collector Current
Peak Collector Current
Maximum Power Dissipation
Total Power Dissipation
Maximum Temperature
Storage Temperature
Operating Temperature
*PW = 10ms, duty cycle
~
VCBO
VCEO
VIN
IC(DC)
IC*
30
30
30
0.4
2.0
V
V
V
A/unit
A/package
1.2
W/package
-40 to + 125
-25to+ 75
Tstg
Topt
°c
°c
10%
ELECTRICAL CHARACTERISTICS (Ta = 2SoC)
CHARACTERISTICS
Circuit Current
DC Current Gain
SYMBOL
MIN.
TYP.
MAX.
UNIT
0.5
100
p.A
2000
3200
IL
hFE
VCE=20V,
VIN=O
VCE=5.0V, IC=200mA
Collector Saturation Voltage
VCE(sat) 1
0.9
1.3
V
Ic=100mA, VIN=5.0V
Collector Saturation Voltage
VCE(sat)2
1.3
2.2
V
Ic=400mA, VIN=20V
CONNECTION DIAGRAM (Top View)
EQUIVALENT CIRCUIT
NC
01
I
Rl
20kn
RBI 20kn
RBl 2kn
870
TEST CONDITIONS
02
03
0,
05
: I nput( Base)
o : Output(Collector)
GND(Common Emitter)
NC
JlPA53C
TYPICAL CHARACTERISTICS (Ta = 25°C)
COLLECTOR CURRENT vs.
COLLECTOR TO EMITTER VOLTAGE
COLLECTOR CURRENT vs.
COLLECTOR TO EMITTER VOLTAGE
500
500
Pulsed
PW= 3OO.us
duty cycle 1.5%
\
\
Ej
~p- ~..o
~(.~
400
I
~ 300
::J
/I'
U
.c:u
r
~
'-'
."
~ ....-
200
~
"0
u
I
"'3a~
,
I"
c
I
100
t
--
----
I
"~4-
-
l a
C
.... ....
~ ~-
~
....
~
t
1--<::)
.
I~~
/
, V. /' /1 a.,.....
300 V'
::J
U
.8u
200
~
"0
u
I 100
60
I
o
5.0V
10
Ie
I
C1l
5000
.....:~
<.!l
2000
~
t
::J
"0
~~
1000
0
/
500
I
u.:
200
O°C
Ta
//
/
25°t
/ / '/
;..
.I::
~
'-
0.5
"0
u
I
50'?
~
V
100
10
.c:u
C1l
\
V/
c?5 1.0
/
B
~
/i.//
/
c
o 2.0
V
U
U
>
~
'iii
100·11l
F 5.0
/.~
c
50
Ta=O'C
I I
V
5°c
~
'" "
0.2
--
50°C
LL
W
~ 0.1
20
50
100 200
I e-Collector Current-rnA
500 1000
10
20
50
100
200
500
1000
I e-Coll ector Current-rnA
OUTPUT VOLTAGE vs.
INPUT VOLTAGE
30
Vee= 20V
RL= 180Q
>
I
C1l
tlO
2
VourVIN TEST CIRCUIT
/ Ta=O°C
20
~ /25°C
"0
>
.uPA53C
r----------l
V 5doc
~
I
.e
I
::J
0
I
I-
10
:J
0
\\
>
Vee
\A
\,
o
2
3
\..
4
5
6
L_________ -1
VIN-Input Voltage-V
871
DIODE ARRAY
tL PA 54H
HIGH SPEED SWITCHING
SILICON EPITAXIAL DIODE ARRAY
DESCRIPTION
The IlPA54H is a common cathode monolithic array of six high speed switching diodes.
FEATURES
• High Speed Switching Time -trr 1.3 ns TYP.
• Small Terminal Capacitance - Ct 2.0 pF TYP.
• Small Size enables High Density Mounting
• Good Electrical Thermal Balance of Six Diodes due to
1 Ch i p Structu re
• Package is 7 pin PLASTIC SIP.
. PACKAGE DIMENSIONS
in millimeters
19.5 MAX.
MARKING
234567
ABSOLUTE MAXIMUM RATINGS
Maximum Voltages and Currents (Ta
= 25°C)
Peak Reverse Voltage
1±0.1
VRM
75
V
Reverse Voltage
VR
50
V
Peak Forward Surge Current (1 ps)
'F (surge)
Peak Forward Current
'FM
Average Rectified Current
10
Maximum Power Dissipation (Ta=25 °C)
P
Power Dissipation
1.0·
A
200·
mA
100·
mA
300··
mW
Maximum Temperatures
Junction Temperature
Tj
T stg
Storage Temperature
·1 Unit ··Package
PIN CONNECTION
125°C
-55 to +125
°c
tfflfrt
2
3
4
5 6
7
Common Cathode
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
CHARACTERISTIC
MIN.
TYP
MAX.
UNIT
TEST CONDITIONS
Forward Voltage
VF
0.8
1.0
V
IF=30mA
Reverse Current
IR
0.01
0.1
IJA
VR=30 V
Terminal Capacitance *
Ct
2.0
4.0
pF
VR=O, f=1.0 MHz
Reverse Recovery Time
trr
1.3
3.0
ns
See trr Reverse Recovery Time Test
Circuit
* 1 Unit
872
SYMBOL
,uPA54H
TYPICAL CHARACTERISTICS (Ta=25 °C)
FORWARD CURRENT vs.
FORWARD VOLTAGE
100
I
.....
10
5
?;
0.5
u..
I
LL.
0.2
-~I
I I
0.1
0.01
o
0.2
0.2
>
~
0.1
I 0.05
a:
-
0.02
-
50°C
-
25 °c
-
0.01
0.005
I
/
0.5
~
I
J
J
0.02
u~
Q)
I
I
1/
0.05
2
~
e
/ / /
(5
.....c
-
Ta=100 °c
5
I
!~1 'f
J....j
10
1
O~ '{-oUIJ
2
U
"Ero
20
// /
/ / ~
c
~::J
50
/ //
20
E
100
/ / :/
50
«
REVERSE CURRENT vs.
REVERSE VOLTAGE
I0.6
0.4
0.002
0.8
1.0
1.2
1.4
0.001
1.6
o
20
VF - Forward Voltage - V
40
60
80
VR - Reverse Voltage - V
REVERSE RECOVERY TIME vs.
FORWARD CURRENT
TERMINAL CAPACITANCE vs.
REVERSE VOLTAGE
10
10
VR=6.0 V
irr=O.l I r
See Test Circuit
f 1.0 MHz
~
I
fj
c
!S
'(3
ro
en
5
C
I
2
r-- r--
ro
U
-
i=
- I - r-I-
r---
ro
Q)
8
Q)
E
a.
.=E
100
~
>
---...
Q)
~
6
/'f'
0
u
/~
Q)
a:
Q)
~
0.5
4
Q)
>
l-
Q)
a:
I
I
......
.U 0.2
2
.....
5
2
10
20
50
100
0
/
V
20
V
40
60
80
100
IF - Forward Current - rnA
VR - Reverse Voltage - V
trr REVERSE RECOVERY TIME TEST CIRCUIT
trigger
I
0.02 ILF
PULSE
~,
GENERATOR
(Zout=50 n)
DC VOLTAGI=I+
REGURATOR
OUT
..... ,
- ....,
I
SAMPLING
SCOPE
(Zin=50 51)
IF
0~--I-----+~-t-""'!!'0.1.
Ir
3 kn
J
Test Conditions: IF=10 rnA, VR=6 V, RL=100
n
irr=O.l Ir
trr
873
TRANSISTOR ARRAY
Il PA 56C
SEGMENT DRIVER
NPN SILICON EPITAXIAL TRANSISTOR ARRAY
DESCRIPTION
The pPA56C is a monolithic array of seven transistors.
This device is especially suited for driving common cathode seven segment LED, relays, and lamps.
FEATURES
PACKAGE DIMENSIONS
•
in millimeters
High Voltage Ratings VCBO=60 V
• Package is 16 Pin PLASTIC DIP.
19.4 MAX.
ABSOLUTE MAXIMUM RATINGS
161514131211109
Maximum Voltages and Currents (Ta = 25°C)
Collector to Base Voltage
VCBO
60
V
Collector to Emitter Voltage
VCEO
40
V
Emitter to Base Voltage
VEBO
5.0
V
Continuous Collector Current
IC(DC)
100
mA/unit
Continuous Collector Current
IC(DC)
550
mA/package
Pd
550
mW/package
Maximum Power Dissipation
Total Power Diss·ipation
Maximum Temperature
Tr2
Tr3
Tr4
Tr5
Tr6
T opt
-25 to +75
°c
Tstg
-40 to +125
°c
CONNECTION DIAGRAM (Top View)
EQUIVALENT CIRCUIT
Tr1
Operating Temperature
Storage Temperature
Tr7
9
~~~~~~~r
1 163
24
57
61011131214 158
Sub.
Note: Sub. -terminal is to be connected to the lowest voltage level in the application.
874
j.lPA56C
ELECTRICAL CHARACTERISTICS (Ta
CHARACTERISTIC
Collector Cutoff Current
Emitter Cutoff Current
DC Current Gain
DC Current Gain
= 25°C)
TYP.
MAX.
UNIT
ICBO
0.001
0.1
JlA
VCB=40 V, IE=O
lEBO
0.001
0.1
JlA
VEB=3.0 V, IC=O
SYMBOL
MIN.
TEST CONDITIONS
hFEl
50
250
VCE=1.0 V, IC=10 rnA
hFE2
40
200
VCE=1.0 V, IC=50 rnA
Collector Saturation Voltage
VCE(sat)l
0.07
0.3
V
IC=10 rnA, IB=1.0 rnA
Collector Saturation Voltage
VCE(sat)2
0.2
0.6
V
IC=50 rnA, IB=5.0 rnA
Base Saturation Voltage
VBE(sat)
0.86
1.0
V
IC=50 rnA, IB=5.0 rnA
Gain Bandwidth Product
fT
320
MHz
Output Capacitance
Cob
4.0
pF
Turn On Time
ton
40
ns
Storage Time
tstg
200
ns
Turn Off Time
toff
230
ns
VCE=10 V, IE=-10 rnA
VCB=10 V, IE=O, f=1.0 MHz
See Switching Time Test
Circuit
875
J.lPA56C
TYPICAL CHARACTERISTICS (Ta = 25°C)
COLLECTOR CURRENT vs'
BASE TO EMITTER VOLTAGE
TOTAL POWER DISSIPATION vs.
AMBIENT TEMPERATURE
100
600
~
'\.
E 500
\
I
c:
.2
~
400
+-'
It!
\
.~
.!!?
0
300
~0
a..
l\.
\
10
I
3.0
£u
\.
u
\.
80
T a - Ambient Temperature -
I
~
160
0.1
«
E
/Ih~ / ];,.WV V
0.3
80
I
c:
~V V
+-'
~
:;
60
°c
0
1:)
~
'I
40
(5
'I
U
/
0
«
~.
~
V~60_ - ~,
40
V~
140
I
+-'
c:
~ 30
V
120'
::l
£u
~
r-
20
lL
I
4
o
5
VCE - Collector to Emitter Voltage - V
DC CURRENT GAIN vs.
COLLECTOR CURRENT
"
•
100
.....
'"
80
1
40'
..!
IS=20JlA
10
20
30
40
VCE - Collector to Emitter Voltage - V
50
BASE AND COLLECTOR SATURATION VOLTAGE vs.
COLLECTOR CURRENT
>
VCE 1.0 V
1.0
I
>
~
VSE(~atl
1.l9
c:
~
~o
~,~It-
60
I
1000
~O'~
U
~ 10
3
I
.iO
•
o
IS=O.l mA
-
E
U
/'
2
0.4
'\SO
~
t-"
I
~ 20
50
0.2
/~
0.2
COLLECTOR CURRENT vs.
COLLECTOR TO EMITTER VOLTAGE
~
VL V
u
I
o
0.6
0.8
1.0
VSE - Sase to Emitter Voltage - V
COLLECTOR CURRENT vs.
COLLECTOR TO EMITTER VOLTAGE
~~ ~~
!I
0.3
120
I
I
1.0
I
\~
100
I
~
(5
100
40
I
:;
u
\
0
I
c:
I
I
~
0
~
30
E
l-
I
«
+-'
200
a;
VCE 1.0 V
Free Air
al(5
300
c:
.=:
g>C:
0.3
~::l ~"-
0.1
>o .~0
c: e
.-o ....::l
.... t"-.
+-'
~
:;
u
u 100
o
II
iii B
en
u
I
VCE(sa!l~
al~
w
u..
.c
VI
It!
~
-
0
cnu
30
I
I
........
It! It!
/
0.03
~~
WW
10
0.1
876
cnu
0.3
3
10
30
IC - Collector Current - mA
100
>>
IC=10'IS
0,01
0.1
30
10
3
0.3
IC - Collector Current - mA
100
pPA56C
GAIN BANDWIDTH PRODUCT vs.
EMITTER CURRENT
1000
INPUT AND OUTPUT CAPACITANCE vs.
REVERSE VOLTAGE
100
VCE 10 V
N
IE O(Cob)
IC=O(Cib)
f=1.0 MHz
u..
u.. a.
I
~
0.1
J,300
u
:J
"0
"".
o
I ~ 30
~~
III
u
c:
ro
.t::
/'
ct
.r:.
:2 100
c:
ro
.t:!
u
ro
a.
~a1O
u
~
~
c:
a.... ;a.
co
c: 0
"0
:J
ro
a.
I
c:
~ 30
:9
--~
.g
I"'-Cib
I""'r- ""
Cob- ...... 1'-0.
I
uu
I
~
....
:J
3
.t"
1~0.3
-10
-30 -100 -300
-1
-3
IE - Emitter Current - mA
1
0.1
0.3
3
10
30
VCB - Collector to Base Voltage - V
VEB - Emitter to Base Voltage - V
100
SWITCHING TIME TEST CIRCUIT
10 V
1.2 kn
PW=1.0 1-'s
duty cycle~5 %
50
n
-3 V
877
DIODE ARRAY
j1PA64H
HIGH SPEED SWITCHING
SILICON EPITAXIAL DIODE ARRAY
DESCRIPTION
The J,LPA64H is a common anode monolithic array of six high speed switching diodes.
FEATURES
• High Speed Switching Time -trr 4.0 ns TYP.
o Small Terminal Capacitance -Ct 5.0 pF TYP.
e Small Size enables High Density Mounting
• Good Electrical Thermal Balance of Six Diode due to
1 Chip Structure
• Package is 7 pin PLASTIC SIP.
PACKAGE DIMENSIONS
in millimeters
19.5 MAX.
"I .2.8±0.2
r-------------~·-x
t1
«X .
~«x
,.....~«
ABSOLUTE MAXIMUM RATINGS
Maximum Voltages and Currents (Ta = 25°C)
Peak Reverse Voltage
VRM
Reverse Voltage
0.25
VR
Peak Forward Surge Current (1 jls) IF (surge)
1t0.1
75
V
50
V
1.0*
A
Peak Forward Current
I FM
200*
rnA
Average Rectified Current
10
100*
rnA
300**
mW
Maximum Power Dissipation (Ta=25 DC)
Power Dissipation
P
Maximum Temperatures
Junction Temperature
Tj
Storage Temperature
Tstg
* 1 Unit
125
-55 to +125
°c
°c
** Package
PIN CONNECTION
tf f Iff t
1234567
Common Anode
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
CHARACTERISTIC
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
Forward Voltage
VF
0.8
1.0
V
IF=30 rnA
Reverse Current
IR
0.005
0.1
p,A
VR=30 V
Terminal Capacitance *
Ct
5.0
8.0
pF
VR=O, f=1.0 MHz
Reverse Recovery Time
trr
4.0
8.0
ns
See trr Reverse Recovery Time Test Circuit
* 1 Unit
878
SYMBOL
,uPA64H
TYPICAL CHARACTERISTICS (Ta = 25°C)
FOWARD CURRENT vs.
FORWARD VOLTAGE
100
/
50
~ 2.0
1.0
/
"EC1J
3: 0.5
~
0
I
rv
II
~
::l
LL
I
c:
+-'
~
0.2
J
0.01 0
I I
I
~
.....
-
2.0
1.0
0.5
25 DC
!---~ ~
V .....
~~
0.2
0.1
o
40
20
60
80
100
VR - Reverse Voltage - V
I
I I I
0.2
a:
I
a:
I
II
I I
0.02
>
I
V
VCE 5.0 V
VI 13 V
I
Cll
OJ
~
c
"co
tJ 3000
C
~
u
1000
0
~
I
w
LL
..c
:J
e
:J
o
w
>
"
V
.-'"
1.0
Cll
-I
/
300
3.0
+-'
t....~
:J
U
~
1/
+-'
~
o
/
-I
0.3
I
-I
o
100
10
>
30
100
300
10 - Output Current - mA
0.1
10
30
100
300
10 - Output Current - mA
OUTPUT VOLTAGE vs.
INPUT VOLTAGE
VO-VI TEST CIRCUIT
>
I
JJ. PA67C (1 unit)
r------------,
20
Cll
OJ
~
"0
>
VOUT
+-'
:J
e
:J
0
I
0
10
___________ ..JI
>
VCC=20 V
RL=200 on
o
\
2
\
"
3
4
5
VI - Input Voltage - V
SSI
TRANSISTOR ARRAY
f1 PA79C
MINI PRINTER DRIVER
NPN SILICON EPITAXIAL TRANSISTOR ARRAY
DESCRIPTION
The J.LPA79C is a monolithic array of seven transistors.
This device is especially suited for driving low supply voltage printer with up to 0.1 A output current per unit.
FEATURES
• Low Saturation Voltage -VCE(sat)~0.6 V
• High DC Current Gain -hFE~1000
• Reverse Bias Protected Inputs
• Transient Protected Outputs
• Package is 16 pin PLASTIC DIP
PACKAGE DIMENSIONS
in millimeters
161514131211109
ABSOLUTE MAXIMUM RATINGS
Maximum Voltages and Currents (Ta = 25
12345678
19.4 MAX.
Supply Voltage
~~r~
Jljffim~O-150
0.25:g:A~
0.5±0.1 2.54
0
C)
20
V
-40 to + 30
V
V CC
I nput Voltage
VI
Output Voltage
V
20
Va
Continuous Output Current IC(DC)**
Peak Output Current
IC*
200
mA/unit
150
rnA/unit
550
mW/package
Maximum Power Dissipation
Total Power Dissipation
Pd
Maximum Temperature
Operating Temperature
T opt
-25 to + 75
Storage Temperature
T stg
-40 to +125
**DC (1 unit)
* PW,£30 ms, duty cycle,£10 % (The same current for all units)
ELECTRICAL CHARACTERISTICS (Ta = 25°C)
CHARACTERISTIC
SYMBOL
Output Leakage Current
ILl
DC Current Gain
hFE
Collector Saturation Voltage
MIN.
1000
TYP.
MAX.
UNIT
10
J.LA
TEST CONDITIONS
VCC=20 V, VI=O
VCC=5 V, VCE=l V, 10=120 rnA
2500
VCE(sat)
0.6
V
Output Leakage Current
IL2
10
J.LA
Input Voltage
VI
4.0
V
VCC=5 V, VCE=1 V, 10=120 rnA
Forward Voltage (Clamp Diode)
VF
2.0
V
IF=120 rnA
EQUIVALENT CIRCUIT
162
153
144
VCC=5 V, 10=120 rnA, II =0.2 rnA
VCC=VCE=5 V, VI=1.5 V
CONNECTION DIAGRAM (Top View)
135
126
11 7
10
.-~-r~~~+-~~~~~~~--~~~~~~~~--~-o9Rl
=20kll
R2 =1 kll
R3 =20 kll
R4 =2 kll
~----~------~------~------+-----~~----~~~8
882
J1,PA79C
TYPICAL CHARACTERISTICS (Ta = 25°C)
COLLECTOR SATURATION VOLTAGE vs.
OUTPUT CURRENT
OUTPUT CURRENT vs.
COLLECTOR TO EMITTER VOLTAGE
200
«
II /V -
~
120
B::J
80
0
I
.9
>
40
e
....
o
r
u
l1J
1.0
2.0
3.0
4.0
5.0
0.01
10
50
20
100
200
500
10 - Output Current - mA
DC CURRENT GAIN vs.
OUTPUT CURRENT
OUTPUT VOLTAGE vs.
INPUT VOLTAGE
---
VCC 5V
VCE=1 V
----
V
2000
)~
::J
U
f---u 1000 f-------
0
-~
VCC=5 V
RL=50
>
./
5.0
en
\
.c:l
"0
>.....
I~
n
1
I
VCE - Collector to Emitter Voltage - V
Ctl
./
./
.!:
L
./
u
E
LL
L
~0.02
C)
I
/~
I
l
5000
l1J
y
./
~ 0.05
--
~
~V
-
2u
11=45~A -
o
c
0.2
Z
c?5 0.1
~
.....
~
-.
c
.g
VCC 5V
10=100·11
V
"0
g
I
::J
./
./
~ 0.5
50~A
IV
::J
u
.....
-
/60~A
2.5
\
>
I'
\
200
20
50
100
200
500
o
1.0
10 - Output Current - mA
2.0
3.0
4.0
5.0
VI - Input Voltage - V
Va-VI TEST CIRCUIT
r------
VCC=5 V
I
I
Va
SS3
TRANSISTOR ARRAY
I1 PA 80C
FLUORESCENT INDICATOR PANEL DRIVER
PNP-NPN SILICON EPITAXIAL TRANSISTOR ARRAY
DESCRIPTION
The J.lPA80C is a monolithic 'array of seven PNP-NPN structured transistors. This device is especially suited
for driving FIP (Fluorescent Indicator Panel).
PACKAGE DIMENSIONS
FEATURES
in millimeters
~l~~~~~~J~
11
2 3 4 5 6 7
19.4 MAX.
81
N
1.2
•
Pull down resistors incorporated
•
Base current limiting resistors incorporated
•
Package is 16 pin plastic DIP (Dual In-Line Package).
Maximum Voltages and Currents (Ta=25 0 C)
U§1~~
m7.62_
Supply Voltage
Input Voltage
i~
"l~0-15
0
VSS
-60
V
V
-20
50
Output Current
"'0.25~g:~~
0.5±0.1 2.54
High voltage rating VSS: -60 V
ABSOLUTE MAXIMUM RATINGS
X
mmm1:
-U-
•
mA/unit
Maximum Power Dissipation
mW
550
Total Power Dissipation
Maximum Temperature
Storage Temperature
T stg
-40 to +125
0
C
Operating Temperature
T opt
-25 to + 75
0
C
ELECTRICAL CHARACTERISTICS (Ta=25 °C)
CHARACTERISTIC
SYMBOL
Output Leakage Current
DC Current Gain
MIN.
TYP.
IL
MAX.
UNIT
1.0
J.lA
100
280
VCE=2.0 V, 10=20 rnA
hFE2
250
450
VCE=2.0 V, 10=40 rnA
Input Current
0.95
II
1.5
V
1.0
rnA
10=20 rnA, 11=0.3 rnA
VI=-5.0 V
CONNECTION DIAGRAM (Top View)
EaUIVALENT CIRCUIT
15
VCE=50 V
hFE1
Collector Saturation Voltage VCE(sat)
16
TEST CONDITIONS
14
13
12
11
10
11
2
RSl : 20 kn
Rl : 20 kn
RS2: 2 kn
R2: 100 kn
884
3
4
5
6
7
12
13
14
15
1=1 nput (Sase)
O=Output
16
17
Vss
j.lPA80C
TYPICAL CHARACTERISTICS (Ta=25 °C)
DC CURRENT GAIN
OUTPUT CURRENT
1000
COLLECTOR SATURATION VOLTAGE vs.
OUTPUT CURRENT
VS.
>
VCE 2.0 V
~
./
'ro 300
!
l?
+-'
C
~
:J
u 100
u
~~
u.
V
-0
>c
/'
~
/
~
1.0
B
()
0.6
~
/
30
3.0
.g
e
~
60
w
.!:
10- 50 .11
6.0
!9
/
c
0
I
10
I
600
o
V
u
I
/
V
0.3
+-'
~
w
10
U
3
1
6
10
60
30
100
10 - Output Current - mA
OUTPUT VOLTAGE vs.
INPUT VOLTAGE
-60
>
0.1
1
30
3
6
10
10 - Output Current - mA
60
100
Va-VI TEST CIRCUIT
VSS=-40 V
RL=10kn
}JPA80C (1 Unit)
r------,
>
I
ClJ
OJ
-40
---
~
o
>
+-'
:J
0.
;
o
-20
I
o
>
o
-1
-2
-3
-4
-5
-6
VI - Input Voltage - V
aas
TRANSISTOR ARRAY
J-lPA81C
LED,LAMP DRIVER
NPN SILICON EPITAXIAL DARLINGTON TRANSISTOR ARRAY
DESCRIPTION
The J.LPA81 C is a monolithic array of seven darlington transistors. This device is especially suited for driving
LED, lamps and printer hummers with MOS output signal.
FEATURES
PACKAGE DIMENSIONS
in millimeters
•
High DC current gain.
•
High output drive current.
•
Package is 16 pin plastic DIP (Dual In-Line Package).
ABSOLUTE MAXIMUM RATINGS
Maximum Voltages and Currents (Ta=25 °C)
Output Voltage
Vo
Input Voltage
Peak Output Current
45
V
45
400
V
rnA/unit
800
mW/package
Maximum Power Dissipation
Total Power Dissipation
Pd
Maximum Temperature
Operating Temperature
Storage Temperature
* PW=10 ms, duty cycle
T opt
-25 to + 75
Tstg
-55 to +125
~1 0 % (All units turned on)
°C
°C
ELECTRICAL CHARACTERISTICS (Ta=25 DC)
CHARACTERISTICS
SYMBOL
MIN.
TYP.
MAX.
UNIT
10
J.LA
Output Leakage Current
IL
DC Current Gain
hFE
Collector Saturation Voltage
VCE(sat)l
0.82
1.2
V
VI=13 V, 10=100 mA
Collector Saturation Voltage
VCE(sat)2
0.95
1.4
V
VI=13 V, 10=200 mA
Collector Saturation Voltage
VCE(sat)3
1.2
2.2
V
VI=13 V, 10=400 mA
Input Current
II
1.5
mA
1000
VCE=2.5 V, 10=200 mA
R~:b3 tE tB b3 b3 tE tE
AS2
A1
20 kn
AS1 20 kn
AS2 2 kn
VCE=40 V
2500
EQUIVALENT CIRCUIT
sss
TEST CONDITIONS
VI=17 V, 10=0
CONNECTION DIAGRAM (Top View)
08
11
12
16
I
:
17 GND
Input (Sase)
Output (Collector)
GND (Common Emitter)
o :
j.lPA81C
TYPICAL CHARACTERISTICS (Ta=25 °C)
DC CURRENT GAIN vs.
OUTPUT CURRENT
COLLECTOR SATURATION VOLTAGE vs.
OUTPUT CURRENT
>
VCE 2.5 V
~
6000
/'"
3000
<.?
....
c
~
:J
~
1000
U
u
V
/
>c
V
~
~
~
u.
..t:
1,....000
1.0
B 0.6
~
600
I
w
3.0
o
.;;
~
0
VI 13 V
6.0
~
o
~
c
·co
10
I
./
300
V
100
10
V
"0
u
I
/
0.3
....
~
w
U
30
60
100
300
10 - Output Current - mA
600 1000
>
0.1
10
30
60
100
300
600 1000
10 - Output Current - mA
OUTPUT VOLTAGE vs.
INPUT VOLTAGE
Va-VI TEST CIRCUIT
30
VCC=20 V
RL =180
n
}JPA81 C (1 unit)
r-------,
__
>
I
I
Q)
01
~
20
~
4 __ _
--~
'\
0
>....
:J
0.
S
0
I
10
L- _ _ _ _ _ _ _ J
0
>
\.
o
2
3
4
5
6
VI - Input Voltage - V
SS?
TRANSISTOR ARRAYS
/1PA2001 C,/1PA2002C,/1PA2003C,/1PA2004C
LED, LAMP, RELAY DRIVER
NPN SILICON EPITAXIAL DARLINGTON TRANSISTOR ARRAY
DESCRIPTION
The pPA2001 C, 2002C, 2003C and 2004C are monolithic arrays of seven darlington transistors.
These devices are e.specially suited for driving relays, solenoids, LED, lamps, and other devices with up to
0.3 A output current per unit.
FEATURES
PACKAGE DIMENSIONS
o Transient Protected Outputs
in millimeters
•
High DC Current Gain
o High Output Drive Current
161514131211109
o High Output Voltage
~::::::JE[
I~
81
2 3 4 5 6 7
19
.4MAX.
~~2 ~::: ~
mwm
.Jr;2
O.5±O.1 2.54
o Package is 16 pin PLASTIC DIP.
M
~
~~
~
7.62
0-15'
O.25:.g:M
CONNECTION DIAGRAM (Top View)
EQUIVALENT CIRCUIT (1 Unit)
pPA2001C
pPA2002C
SK
IN 0-....-1
~--1---~OUT
SK
I N o--t~-'Vv"v--1~
----~~~OUT
I
I
I
IL ____
pPA2003C
* ___ _
pPA2004C
I
: I nput (Base)
o
:
GND
SK
I
:f
IL _ _
888
* ____ _
Output (Collector)
(Common Emitter)
: Surge Killer
ABSOLUTE MAXIMUM RATINGS
Maximum Voltages and Currents (Ta = 25 °C)
Output Voltage
Vo
60
V
Input Voltage (except MPA2001C)
VI
-0.5 to +30
V
Input Current (only MPA2001 C)
II
25
mA/unit
Output Current
10
500
mA/unit
Output Current
10*
2.3
A/package
Reverse Voltage (Clamp Diode)
VR
60
V
IF
500
rnA/unit
Total Power Dissipation
Pd
900
mW/package
Total Power Dissipation
Pd*
2.5
W/package
Operating Temperature
Topt
-30 to + 75
°c
Storage Temperature
Tstg
-55 to +150
0
Forward Current (Clamp Diode)
Maximum Power Dissipation
Maximum Temperature
C
* PW~20 ms, duty cycle~10 % (The same current for all units)
ELECTRICAL CHARACTERISTICS (Ta = 25 °C)
CHARACTERISTIC
Output Leakage Current
DC Current Gain
SYMBOL
TYP.
IL
hFE
Collector Saturation Voltage
MIN.
VCE(sat)
1000
VCE=50 V
MA
VCE=50 V, Ta=70 °c
V CE=2.0 V, 10=350 mA
1.1
V
10=100 mA, 11=250 MA
1.0
1.3
V
10=200 mA, II =350 J1.A
1.6
V
10=350 mA, II =500 J1.A
11
V
VCE=2.0 V,10=100 mA
12
V
VCE=2.0 V, 10=200 mA
13.5
V
VCE=2.0 V, 10=350 mA
2.0
V
VCE=2.0 V, 10=100 mA
2.4
V
VCE=2.0 V, 10=200 rnA
3.4
V
VCE=2.0 V, 10=350 rnA
5.0
V
VCE=2.0 V, 10=100 mA
6.0
V
VCE=2.0 V, 10=200 mA
8.0
V
V CE=2.0 V, 10=350 mA
1.3
mA
VI=17 V
1.35
rnA
VI=3.85 V
1.0
rnA
VI=5.0 V
VR=50 V
VI
J1.PA2002C
MPA2003C
MA
TEST CONDITIONS
0.9
J1.PA2004C
Input Current
10
100
J1.PA2002C
J1.PA2003C
UNIT
2800
1.2
Input Voltage
MAX.
II
J1.PA2004C
Reverse Current (Clamp Diode)
IR
50
J1.A
Forward Voltage (Clamp Diode)
VF
2.0
V
Terminal Capacitance
Ct
15
pF
IF=350 rnA
VI=O, f=1.0 MHz
Note: Input Voltage and Current of the J1.PA2001 C depend on external resistor.
sss
,uPA2001C,,uPA2002C,,uPA2003C,,uPA2004C
TYPICAL CHARACTERISTICS (Ta
= 25°C)
COLLECTOR SATURATION VOLTAGE vs.
OUTPUT CURRENT
OUTPUT CURRENT vs.
COLLECTOR TO EMITTER VOLTAGE
500
~401J.l.A
V
I.--- ~
~
--
~
r:::
o
.~
~
~
---
1.0
L..
B
......... ~
t)
2
o
0.5
u
'1'=100J.l.A
I
]
I
)
.'S
(5
~
I
100
5.0
>
I
I
0
'0 100·1,
I
~
120 J.l.A
w
U
0
2
4
3
5
>
0.1
10
50
VCE - Col/ector to Emitter Voltage - V
100
500
1000
10 - Output Current - mA
INPUT CURRENT vs.
INPUT VOLTAGE (J.l.PA2002C)
DC CURRENT GAIN vs.
OUTPUT CURRENT
20
VCE 2.0 V
5000
io"
/7
r:::
~
:J
~ 1000
o
I
w
1.6
I
r:::
1.2
/
E
/V
+-'
VCC=20 V
RL =180 n
n
20
20
>
I
I
Q)
Q)
OJ
OJ
~
~
>....
>....
"0
"0
:J
B:J
:J
B-:J
10
0
I
0
10
0
I
0
>
>
\
o
2
\
""
4
6
8
10
12
14
o
0.5
1.0
......
1.5
2.5
2.0
3.0
VI - Input Voltage - V
VI - Input Voltage - V
OUTPUT VOLTAGE vs.
INPUT VOLTAGE (J.lPA2004C)
Va-VI TEST CIRCUIT
VCC=20 V
RL=180
20
n
J..LPA2002C-2004C (1 Unit)
>
VCC=20 V
I
r-----'
Q)
OJ
~
I
0
>....
:J
B:J
o---~I_4
I
I
10
0
I
0
L
I
r-_I~~~--~
I
I
GND.
----I~
Vo
>
o
2
3
4
5
6
VI - Input Voltage - V
891
1. ALPHA-NUMERICAL INDEX
2.
QUICK REFERENCE GUIDE
3.
CROSS REFERENCE GUIDE
4.
MAINTENANCE AND OBSOLETE TYPES
5.
GENERAL STATEMENT
*
NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
o History
0
Types and Features
o Type Number Designation
0
Device Technologies
*
STANDARDS OF INTEGRATED CIRCUITS
*
HINTS ON CORRECT USE
*
*
TECHNICAL SYMBOLS AND TERMS
RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
7.
6 - 1.
CAR AUDIO
6 - 2.
HOME AUDIO
6- 3.
PORTABLE AUDIO
TV APPLICATIONS
8. DIGITAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11. ARRAYS
12. OTHERS
13. APPLICATION NOTES
..
OTHERS
INDEX
Page
J,lPC1043C
FG Motor Servo . . . . . . . . . . . . . . . . '. . . . . . . . . . . . . . . . . . . . . . ..
896
J,lPC1052V
Receiver for Radio-Control Systems. . . . . . . . . . . . . . . . . . . . . . . . . ..
902
J,lPC1053V
Servo-Amplifier for Radio-Control Systems. . . . . . . . . . . . . . . . . . . . ..
906
J,lPC1246C
Pre Driver for 3-Phases DC Brushless Motor . . . . . . . . . . . . . . . . . . . . .
911
J,lPC1470H
Motor Govener . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
921
895
BIPOLAR ANALOG INTEGRATED CIRCUIT
,uPC1043C
MOTOR CONTROL CIRCUIT
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
The J,lPC1043C is a silicon monolithic integrated circuit developed by NEC for Frequency Generator DC Motor speed control of Hi-Fi player and VTR etc.
The package is 16-pin plastic Dual In-Line Package.
FEATURES
• Operating at wide range supply voltage.
(Vee =9 to 28 V)
• Available for wide range FG. Servomotor.
)
f = 20 to 3 000 Hz
( Vin = 1 to 2 000 m V pop
• Applicable for any kind of motors by choising the external power transistor.
PACKAGE DIMENSJONS
CONNECTION DIAGRAM (Top View)
in millimeters (inches)
19.4 MAX.
(0.763 MAX.)
896
PRE·AMP(lN)
16
RESEYSET
TIMING
PRE·AMP(lI)
2
15
DIFFERENTIAL INPUT
PRE·AMP OUTPUT
3
14
DC AMP OUTPUT CONTROL
SCHMITT(lI)
4
13
ROTATION ADJUSTMENT
SCHMITT'ON)
5
12
HOLD
SCHMITT OUTPUT
6
11
DC AMP~ II
POWER SOURCE
7
10
DC AMP OUTPUT
GND
8
REGULATION VOLTAGE
,uPC1043C
BLOCK DIAGRAM (Top View)
DIFFER EN
TIATION
SAMPLING
&
HOLD
TIMING
CIRCUIT
SCHMITT
TRIGGER
+
POWER
CIRCUIT
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Supply Voltage
VCC
Circuit Current
15*
V
Icc
100
mA
Power Dissipation (Ta = 75°C)
Po
350
mW
Operating Temperature Range
T opt
-20 to +75
°c
Storage Temperature Range
T stg
-40 to +125
°c
* Power source directly applied to No.7 pin.
RECOMMENDED OPERATING CONDITIONS
CH ARACTE R ISTI C
Supply Voltage (RCC=O)
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC1
9
12
15
V
Supply Voltage (RCC = 560 n)
VCC2
19
24
28
V
FG Frequency
fref
20
3000
Hz
PRE-AMP Voltage Gain
Av
20
60
dB
Threshold Voltage
VTH
±20
±200
mV
Operating Temperature Range
Topt
-20
+60
°c
897
,uPC1043C
ELECTRICAL CHARACTERISTICS (Vee = 12 V, Ta=25 °C)
CHARACTERISTIC
MIN.
TYP.
MAX.
UNIT
TEST CONDITIONS
Non-signal input,
Output current = 0
Circuit Current
ICC
4
7
10
mA
Regulation Voltage
V9
5.1
5.7
6.3
V
Voltage at No.9 pin
Maximum Output Voltage
Vo max.
3.5
4.25
V
Output Current = 0
Maximum Output Current
lOmax.
8
12
17
mA
Output Voltage =0
Shunt Regulation Voltage
V70N
15
16.3
18
V
VCC=28 V, RCC=560
dB
f= 100 Hz
Test Circuit - 2
S.G. output terminated
700 mVr.m.s.
PRE-AMP Voltage Gain
898
SYMBOL
Avo
75
84
n
Rotation Temperature
Coefficient
D.NA
0
0.02
%/oC
VCC=28 V, RCC=560 n
Ta = -20 to +60 °c
Rotation
N max . - Nmin.lN (25 °CI/80 °c
Rotation Coefficient
Input Voltage
D.NV
0
0.02
%/V
Variation of Rotation at
V CC = 19 to 28 V, RCC = 560
Variation of Rotation 10 s
to 30 MIN after VCC on at
Vec= 24 V, RCC= 560 n
Rotation Drift
D.NT
0
0.1
%
Output Ripple Voltage
Vo
20
35
mV p _p
Test Circuit-4
Schmitt Noise Voltage
VTN
0
0.7
V _
pp
Test Circuit - 5
ON Resistance
RQ48 ON
100
300
n
Test Circu it - 6
n
tlPC1043C
TEST CI RCUIT -1
TEST CIRCUIT -2 (Avo)
(Icc, Vg, Vo max, 10 max, V7 ON)
b
SW2
lOOk Q
~
~ 1 2v
a
I I
+
100tl F
L---t---,.~--o VCC
lkQ
0. 047 lOkQ
SG
"
m 75Q
~28V
a
l2V ~ l~SG
ICC
Vg
VO max .
lOmax.
V70N
SWI
a
a
a
a
b
SWITCH
SW2
a
a
b
b
a
SW3
a
a
a
b
a
MEASUREMENT
POINT
A7
Vg
VlO
AlO
V7
tlF 10 F +
"
b RCC=560Q
;~
= l2V
tl
I 0.047
I
tl F
Output Impedance=75 Q
~ATT
Input/Output Impedance=75 Q
TEST CIRCUIT -4 (v o )
l30kQ·
r-r'~~..---+------Q SPECI FI ED
MOTOR
FG
22
t-------\Mr----Q
Hi-'Wv-------'
+VCC = 28V
tlF
L--~--------~~---~----------__oCOUNTER
~ Adjust
~ Adjust
SG frequency to obtain 1.4 to 1.5 V
DC Voltage on NO. 10 pin, and then measure
with oscilloscope.
VR 1 so that the measured volue
by counter becomes 20 ms.
TEST CIRCUIT -5 (VTN)
TEST CIRCUIT -6 (R048 ON)
VDC
OSCILLOSCOPE
560Q
t---~_---o
VCC= 28V
'------------0
~ Adjust
+ VCC= 12V
VDC to obtain voltage of 1.5 V between
NO. 13 and NO.9 pin, measure· current,
and calculate by V(1.5 V)/A.
899
,uPC1043C
pPC1043C TIMING CHART
@FG Output
@Schmitt Trigger Output
(SPIN)
@Oifferential Input
(15PIN)
@Timing Trigger Pulse
@Timing Pulse
(lSPIN)
CDSampling Pulse
®Reset Pulse
@Saw-Tooth
Waveform Pulse
(l3PIN)
/2
!
V9
V
Jd
~
Ii
Vg
1
o~_~O______~HI~--------~n~_
v:nfE=~~~~~:;i~~~~~~~:~
V9Q!!
1I~---------4~-+-
V:41 r----.
I .
III
III '
Vg
(Pulse Width=O.2STT)
ON
OFF (Pulse Width=O.S5 TT)
ON
H-________
II
II
II
II
!-------l'f-----------+i+-I-~-
voOg.J..1-gi
CDHolding Capacitor
(l2PIN)
-
900
r
v;eference standard voltage
If
J,lPC1043C
APPLICATION CIRCUIT
Speed Control
r--------------i
I 220kQ
I
I
I
I
I
:
r----~o.!:]J
r-------I
I
I
I
VCC
I
I
I
I
L_______ _
560Q
VCC=24 V
RCC
Note
1:
Note 2:
Set preamplifier gain so that about 2 V p-p voltage is obtained here.
Setting timing time constant T16 on No. 16 pin.
1
x 0.05 ..... (5 % of FG period)
T16 = fref
Note 3:
Setting time constant T13 on No. 13 pin for waveform generator.
1
T13=
fref' (-Qn 0.5)
=C13· R 13
C13 can be obtained by the formula.
C
13::0;:
Note 4:
0.65· T16
3000
DC amplifier gain is determined as shown below.
RNF
AU=--6.8 x 10 3
901
BIPOLAR ANALOG INTEGRATED CIRCUIT
pPC1052V
RECEIVER FOR RADIO-CONTROL SYSTEMS
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTIONS
The JiPC1052V is a silicon monolithic integrated circuit developed for receiver for digital-proportional radio-control
systems.
Included in this device is mixer, oscillator, detector, and
~omparator.
FEATURES
•
Operating at wide range supply voltage (Vee=4.2 to 10.5 V)
•
Wide AGC range.
•
Internal regulation voltage circuit.
•
Reduction of the occupation of mounting area in P.W. Board and hand-insertion time, due to the external shape of the
V-DIP.
PACKAGE DIMENSIONS
CONNECTION DIAGRAM
(in millimeters)
2.8±0.2
19.5 MAX.
~
~
V
x x x x
ex:: ex:: ex:: ex::
MARKING
:::E :::E :::E :::E
lD
123456 7 8 9 101112131415
;
I
('I)
u::icri
0\
:::
r-..
~
2.54
-
I
I
2.54
0.6 MAX.
17.78
X tal
2.
3.
OSC
4.
BY-PASS
5.
MIX. OUT
6.
AGe
7.
IF IN
8.
GND
9.
GND
10.
IF OUT
12.
BY-PASS
13.
VR
14.
OUTPUT
15.
Vee
11.
'-f-.
I
I---
902
I
I
I-' .......
0.35
1
2.54
t--
MIX.IN
1.
BY-PASS
,uPC1052V
BLOCK DIAGRAM (Top View)
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Supply Voltage
VCC
12
V
400
mW
-10 to +50
°C
Power Dissipation
Po
Operating Temperature Range
T opt
Storage Temperature Range
Tstg
-40 to +125
°C
RECOMMENDED OPERATING CONDITION (Ta=25 °C)
CHARACTERISTIC
Supply Voltage
SYMBOL
MIN.
TYP.-
MAX.
UNIT
VCC
4.2
9.0
10.5
V
MIN.
TYP.
MAX.
UNIT
ELECTRICAL CHARACTERISTICS (VcC=9.0 V, T a=25 °C)
CHARACTERISTIC
SYMBOL
TEST CONDITIONS
Circuit Current
ICC
10
14.5
19
rnA
Maximum Sensitivity
M.S.
22
32
42
dBj.,tV
Maximum Sensitivity
Coefficient
LlM.S.
-1
-3
dB
VCC=9 V ~ 4 V
Output Pulse Width Coefficient
(at Large Input Voltage)
LlPW
3
6
J..LS
VIN=110 dBJ..LV
High-Level Output Voltage
VOH
0.7 VR
VR
V
RL=7.5 kn.
Low-Level Output Voltage
VOL
0
0.4
V
RL=7.5 kn.
Regulation Voltage
VR
V
At no signal
3.3
At no signal
Output pulse width
coefficient = 10 J..LS
903
,uPC1052V
TYPICAL CHARACTERISTICS (Ta =25 DC)
CIRCUIT CURRENT vs.
SUPPLY VOLTAGE
REGULATION VOLTAGE vs.
SUPPLY VOLTAGE
25
20
I
1.c:
~
=>
u
(I)
0
15
>
c:
:8co
·5
~
i:3
I
u
!:?
,
3.5
bD
2
10
3.0
I
:l
bD
(I)
a:::
I 2.5
a:::
5
>
2.0
0
2
4
10
8
6
12
o
2
Vee-Supply Voltage-V
4
OUTPUT PULSE WIDTH COEFFICIENT
~ 100
I
~
·u
:::
80
Cl)
o
U
~
60
~
~
:l
40
0.
=>
-5
o
I
;:
0.
"1
20
a
6
8
Vee- Supply Voltage- V
vs. INPUT VOLTAGE
20
'-
AGe range 100 d B - ~
40
I
I
I
60
80
100
120
140
VIN-Input Voltage-dBtN
TEST CI RCU IT (.1PW VS. V IN)
Vee=9 V
50 ~o.o:: :F /
Pulse
Modulation ...--.
904
-
Oscilloscope
10
12
,uPC1052V
APPLICATION CI RCUIT
(1) RADIO-CONTROL SYSTEM
B
(S-006P
attery
SUM2
X
4
CD
96VV)
ON/OFF Switch(Appllcatlon)
r:17 ---------,
II
I
I
I
I
f = 27 MHz Band
I
I
I
I
ol
'9
o
N
Tl :
T2 :
T3:
T4 :
5 k(B)
4
ON/OFF Switch
(Application)
TKXN-27185X(TOKO)
TKXN-27184Z(TOKO)
RMC-162453N9(TOKO)
RMC-222633NO(TOKO)
5 k(B)
3M3
Rl
RF : Feedback Resistance
2SC2001
(2) RADIO-CONTROL SYSTEM ~
Battery
SUM3 x 4
( SUM2 x 4
66VV)
1=27 MHz Band
1,
<>n·
~T'
~
Tl :
T2 :
T3:
T4:
TKXN-27185X(TOKO)
TKXN-27184Z(TOKO)
RMC·162453N9(TOKO)
RMC-222633NO(TOKO)
ON/OFF Switch
(Application)
5 k(B)
3
~
M3
RF : Feedback Resistance
Rl
2SC2001
905
BIPOLAR ANALOG INTEGRATED CIRCUIT
pPC1053V
SERVO-AMPLIFIER FOR RADIO-CONTROL SYSTEMS
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTIONS
The pPC1053V is a silicon monolithic integrated circuit developed for servo-amplifier for digital-proportional radio-control
systems.
Included in this device is the decoder, gate/latch circuit, and servo-amplifier. It operates stably for a wide range of power
supply voltage fluctuation. It can be widely applied to steering control and speed control.
FEATURES
• Internal 2CH servo-circuits and 2CH ON/OFF switch-circuits.
• Operating at wide range supply voltage. (Vcc=3.6 to 9.6 V)
• Internal regulation voltage circuit.
• Reduction of the occupation of mounting area in P.W. Board and hand-insertion time, due to the external shape of the
V-DIP.
CONNECTION DIAGRAM
PACKAGE DIMENSIONS
(in millimeters)
PIN No.
2.8±0.2
19.5 MAX.
~
:---
V
x« x« x« «x
MARKING
1 2 3 4 5 6 7 8 9 10 1112131415
I
:
~
~
~
\0
M
0"1
r-..
t-
I.Ci ex) ::: N
I
~!-
-
CONNECTION
IN
Input
2
CH3
ON/OFF Switch ·3
3
RS
Reset
4
CH4
ON/OFF Switch ·4
5
M2
Mono stable multivibrator ·2
6
VCC
Power supply
7
ST2
Schmitt trigger input ·2
8
003
Drive output ·3
9
VR
Regulation voltage output
I
I
2.54
906
I
I
~
r----
SYMBOL
1
10
2.54
0.6 MAX.
r--17.78
0.35
1
~
11
002
Drive output ·2
ST1
Schmitt trigger input ·1
12
OS
Sink output
13
M1
Mono stable multivibrator'1
14
001
Drive output ·1
15
GND
Ground
jlPC1053V
BLOCK DIAGRAM (Top View)
ABSOLUTE MAXIMUM RATINGS (Ta=25 °C)
Supply Voltage
Vcc
9.8
V
20
rnA
Output Current
CD
los, 1001
Output Current
@, @
1002,1003
12
rnA
ON/OFF Output Current (CH3, CH 4 )
13,14
12
rnA
Power Dissipation
Po
400
mW
Operating Temperature Range
T opt
-10 to +60
°c
Storage Temperature Range
T stg
-40 to +125
°c
RECOMMENDED OPERATING CONDITION (Ta =25 °C)
CHARACTERISTIC
Supply Voltage
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
3.6
6.0
9.6
V
ELECTRICAL CHARACTERISTICS (VCC=6.0 V, T a=25 °C)
CHARACTER ISTIC
SYMBOL
MIN.
TYP.
MAX.
UNIT
13
24
rnA
Circuit Current
ICC
High-Level Input Voltage
VIH
1.5
VCC
V
Low-Level Input Voltage
VIL
0
0.4
V
Input Resistance
RIN
G)
Drive Output Current Q)
Sink Output Current
TEST CONDITIONS
At no signal
11
kn.
VIN=3.3 V
lOS
5
10
rnA
RL=470 n.
1001
5
10
rnA
RL=390 n.
0
Drive Output Current ®
1002
3
6
rnA
RL=560 n.
1003
3
6
rnA
RL=560 n.
Saturation Voltage (CH3)
V3 (sat)
0.9
2
V
10=6 rnA
Saturation Voltage (CH4)
V4 (sat)
0.9
2
V
10=6 rnA
Regulation Voltage
VR
2.1
2.4
V
10=0
Drive Output Current
1.8
907
j.lPC1053V
TYPICAL CHARACTERISTICS (Ta=25 °C)
CIRCUIT CURRENT vs.
SUPPLY VOLTAGE
REGULATION VOLTAGE vs.
SUPPLY VOLTAGE
20
<:
E
3.0
15
1.c
~
~
u
~
G
I
u
5
o
I
Q)
tlO
2.0
/
2
'0
>
c
V
:8ro
V
'::;
.!:?
~
~
10
~
>
V
::;
tlO
1.0
f
Q)
a::
I
I
a::
>
/
o
2
4
6
8
6
4
2
10
8
10
vee-Supply Voltage-V
vee-Supply Voltage-V
13, 14 OUTPUT CURRENT
1002, 1003 OUTPUT CURRENT
vs. OUTPUT VOLTAGE
vs. OUTPUT VOLTAGE
12.5
<:
E
I
12.5
\
10
t:::
~
0
I
.:!
}j
7.5
<:
E
I
\
\
~
0
I
5.0
("t)
5.0
\
Cl
9
N
2.5
Cl
2.5
\
9
0
2
6
4
8
10
2
0
4
YO-Output Voltage-V
1001 OUTPUT CURRENT
lOS OUTPUT CURRENT
vs. OUTPUT VOLTAGE
15
~
0
I
5
o
VCC=6 V
<:
E
i\
\
~
9
~
~
u
10
'5
.9~
0
\
2
4
I
U)
9
6
8
10
5
o
VCC=6 V
/
15
1.c
YO-Output Voltage-V
908
10
20
~
u
'5 10
.9-
;:;
8
vs. OUTPUT VOLTAGE
\
1.c
6
YO-Output Voltage-V
20
<:
E
VCC=6 V
\
10
C
~
~
u
'5 7.5
.9-
\
C
Q)
u
'5
c.
'5
VCC=6 V
/
/
0.1
/
V
0.2
0.3
YO-Output Voltage-V
0.4
0.5
tlPC1053V
BLOCK DIAGRAM AND INTERNAL WAVEFORMS (TIMING CHARTS)
OS
001
M1
GNO
T",,20 ms
1.5 ms 1.5 ms 0.8 ms
0.2-0.3 ms __++-I-----+__--1I-t-~
1
®INPUT
2
34567
n n n n
JUJU
II
II
II
II
II
II
II
II
~ L-..J L.....J
- - - - - - - - - - ; J;~-~ ""'"--
L..'
~
"'----
SERVO·
®AMPLIFIER·l
SERVO·
© AMPLIFIER·2
__~r-l~________________~{~__~
OUTPUT VOLTAGE OF ON/OFF SWITCH (CH 3t CH4)
Pulse Count
Output Voltage of CH3
Output Voltage of CH4
1
Hi
Lo
2
Lo
Hi
3
Hi
Hi
4
Lo
Lo
5
Hi
Lo
6
Lo
Hi
7
Hi
Hi
909
,uPC1053V
APPLICATION CIRCUIT
(1)
CD
RADIO-CONTROL SYSTEM
S-006P
Battery ( SU M2 X 4
9V)
6V
1=27 MHz Band
c.~l.
10
•
U")
•
C>
N
Tl :
T2 :
T3:
T4:
(2)
TKXN·27185X(TOKO)
TKXN·27184Z(TOKO)
RMC·162453N9(TOKO)
RMC·222633NO(TOKO)
RADIO-CONTROL SYSTEM
SUM3 X 4
X 4
Battery ( SUM2
5 k(B)
5 k(B)
4
ON/OFF Switch
(Appli( ation)
3M3
Rl
RF : Feedback Resistance
2SC2001
@
66VV)
1=27 MHz Band
.l
~9'
~
Tl : TKXN·27185X(TOKO)
T2 : TKXN·27184Z(TOKO)
T3: RMC·162453N9(TOKO)
T4: RMC·222633NO(TOKO)
910
ON/OFF Switch
(Application)
5 k(B)
4
3
M3
Rl
2SC2001
RF : Feedback Resistance
BIPOLAR ANALOG INTEGRATED CIRCUIT
pPC1246C
PREDRIVER FOR 3-PHASES DC BRUSHLESS MOTOR
DESCR IPTION
PACKAGE DIMENSIONS
The J.LPC1246C is silicon monolithic integrated cir-
in millimeters (inches)
cuit developed for predriver for 3 phases DC brush less
motor.
R1
CR 0.039)
It includes comparators, current switch, rotatory direction switch and drivers in 1 chip.
It inputs from
hall elements.
FEATURES
•
Current switch.
•
Forward/Reverse function.
•
Small input/output phase error.
•
Low current consumption.
1.2
Icc
~
-J.JJ:-=":":"'
:""'' '
(0.047) 0.25:g:~5 0-15·
(0.01)
-5"'" 5 deg.
= 4.5 rnA TYP.
BLOCK DIAGRAM
16 PINS
Rotatory Direction Selector
Vs
OUTPUT
HALL
ELEMENT
OUTPUT
Current
Switch
OUTPUT
I
I
I
OUTPUT
HALL
ELEMENT
OUTPUT}
OUTPUT
GND
911
,uPC1246C
CONNECTION DIAGRAM (Top View)
OUT2
OUT4
OUT6
OUTS
OUT3
OUll
GND
:
l-
I-
.:-
t-=-
t-=-
t-=-
0..
l-
0..
I-
0..
l-
0..
I-
0..
l-
0..
I-
Uo.
UJ
0
0
0
0
>
(!)
UJ
UJ
(!)
~
~
0
~
~
0
~
~
~
~
~
~
~
~
is
z
a:::
pPC1246C
l-
I-
l-
I-
l-
I-
en
0..
0..
0..
0..
0..
0..
UJ
~
~
~
~
~
~
~
~
~
~
~
~
a:::
~
>
UJ
0
>
a:::
~
0..
0..
~
en
IN!
IN2
ABSOLUTE MAXIMUM RATINGS (Ta
912
IN4
IN3
INS
Vee
IN6
= 25°C)
Supply Voltage
Vee
18
V
5
V
Input Voltage to Differential Amp.
V10
Common Mode Input Voltage
VleM
0.3 to Vee
V
Terminal Voltage to V R EF
ReverseTerminal Voltage
VREF
o to Vee
o to Vee
V
V
390
mW
VREV
Power Dissipation
Po Ta = 70°C
Operating Temperature
T opt
-10 to 70
°c
Storage Temperature
Tstg
-55 to 125
°c
jlPC1246C
RECOMMENDED OPERATING CONDITIONS
CHARACTERISTIC
SYMBOL
MIN.
TYP.
VCC
9
12
VICM
1.5
Supply Voltage
Common Mode Input Voltage
VS-Output Current
VS-IO
CHARACTER ISTIC
15
V
VCC-1.5
V
= 25 °C, Vcc = 12 V)
SYMBOL
ICC
I nputlOutput Characteristics
Input Offset Voltage
UNIT
Ref. Fig. 1 - 3 Within Area of
Obligue Lines
ELECTRICAL CHARACTERISTICS (Ta
Circuit Current
MAX.
VOFF
MIN.
TYP.
MAX.
UNIT
2
4.5
7.5
mA
CONDITIONS
VREF
=
0
-5
0
5
deg
-4.2
0
4.2
mV
VICM = 1.5 to 10.5 V
Input Bias Current
IB
-
50
600
nA
VICM = 6 V
Propagation Delay Time
Tpd
-
3
-
p.s
VI = 5 mY, VREF = 10 V, Vo = 9 V
VREF = 10 V, RL = 470
VREF = 8 V, RL = 470
Output Voltage H (11,12,13 PIN)
VOH
8.9
9.3
9.6
V
Output Voltage L (14, 15,16 PIN)
VOL
8.2
8.6
9.0
V
Output Leak Current
IS
-
-
5
p.A
n
n
Ref. PAGE 916,918
Fig. 1 OUTPUT CURRENT vs. SERVO VOLTAGE
50r-~V~CC-=~9~V~-'--~---r~~~~~~~~~
40
I~~
o VCC-VS
(0
~
5
/
/
V
/
~
/
I
VI
>
/~
o
I
L
,
/~
0.2
0.4
0.6
0.8
1.0
IL- Load Current - A
917
,uPC1246C
INPUT CONDITION FOR MEASUREMENT
•
INPUT/OUTPUT CHARACTERISTIC
TABLE 1
IN CASE OF 7 PIN OPEN
IN CASE OF 7 PIN SHORT
TERM~ION
VI
V2
V3
VI
11
VL
VH
~
~
12
VL
VH
VL
VL
VH
VH
VH
VL
~
~
VL
OF MEASUREMENT
13
VH
14
VL
15
~
16
VH
INPUT LEVEL
5mV=s;;:VH=s;;:50mV OR
~
~
V2
V3
VH
VL
~
~
VH
VL
~
~
VH
VL
VH
VH
~
VL
VL
-50mV=s;;:VL=s;;:5mV
• PROPAGATION DELAY TIME
TABLE 2
IN CASE OF 7 PIN OPEN
TERM~ON
VI
V2
11
VIN
VL
~
~
12
VIN
13
VL
14
VIN
15
~
16
VL
OF MEASUREMENT
VI
V2
V3
VL
VIN
~
~
VL
VL
VIN
VIN
VIN
~
VL
V3
~
~
IN CASE OF 7 PIN SHORT
VL
VL
VL
VIN
VIN
~
~
VIN
INPUT LEVEL
VIN = 5 mV, f =s;;: 10 kHz, Duty 50 % PULSE WAVE -50 mV =s;;: VL
~I
. I
Yo·
I
I
~
VIN
VIN
VL
VL
< -5 mV
/,----
/I 90 %
i,
,
--jTPDt--• OUTPUT LEAKAGE CURRENT IS
INPUT CONDITION FOR MEASUREMENT
TABLE 3
IN CASE OF 7 PIN OPEN
TER1~ION
OF MEASUREMENT
VI
V2
V3
VI
V2
V3
VL
VH
~
VL
VH
11
VH
VL
~
~
12
VH
VL
~
13
VL
VH
VH
14
VH
15
~
16
VL
~
~
VL
VL
VL
VH
VH
~
~
INPUT LEVEL
-50 mV =s;;: VL=S;;: -5 mV, 5 mV=s;;: VH =s;;: 50 mV
918
IN CASE OF 7 PIN SHORT
VH
~
~
VL
VH
VH
VL
VL
~
JLPC1246C
CIRCUIT CURRENT vs. SUPPLY VOLTAGE
INPUT/OUTPUT CHARACTERISTIC
10
5
/
/
/
E
I
c:
~
:::l
U
4
/V
~
'3
V
5
~
C3
I
u
!:?
/
/
V
3
/
o
UJ
8
2
''~
......
/
~
UPPER VOLTAGE
5
LOWER VOLTAGE
20
15
/V
o
5
10
15
20
o
25
~10
OUTPUT VOLTAGE
10
VS.
OUTPUT VOLTAGE
10
OUTPUT CURRENT
!\..
VREF=10 V
~
VREF= 10 V
I
CI)
10 V 1.6 mV/'C-
I
VCC=12 V
RL =470 Q
>
6
VREF=5 V
"
~
"0
>
"5
0
AMBIENT TEMPERATURE
8
01)
.e
VS.
VREF
8
>
25
SUPPLY VOLTAGE VCC(V)
Vcc - Supply Voltage - V
I
CI)
01)
6
~
"0
VREF=5 V
>
"5
.e
4
:::l
VREF=5 V
1.7 mV/'C
VRE~=1 V
2.0 mV/,C
25
50
4
0
I
I
0
0
>
>
"
VREF=1 V
I\.
VREF= 1 V
o
20
40
60
10 - Output Current - rnA
2
o
-25
o
75
Ta - Ambient Temperature - 'C
919
pPC1246C
APPLICATION
IS945
Servo Out
Vs
ROTATORY DIRECTION SELECTOR
OIPJ;
REV.
*
VREF
2S0992
IN2
OUT!
IN!
OUT2
IN4
OUT3
*
J.1
PC1246C
IN3
OUT4
OUT5
IN6
*
OUT6
INS
Vee
GNO
• HALL ELEMENT
Vee
920
BIPOLAR ANALOG INTEGRATED CIRCUIT
J-lPC1470H
MOTOR SPEED REGULATORS
SILICON MONOLITHIC BIPOLAR INTEGRATED CIRCUIT
DESCRIPTION
The J,LPC1470H is a monolithic integrated circuit intended as speed regulators for DC motors of record players, tape and
cassette recorders etc. The devices is packaged in a new developed 4-lead quase-TO-126 plastic case.
FEATURES
• Excellent versatility in use.
• High Output current.
• Low Quiescent current.
• Low Reference voltage.
• Excellent parameters stability versus temperature.
• Excellent characteristic at low supply voltage.
BLOCK DIAGRAM
PACKAGE DIMENSIONS
in millimeters
2.8 MAX.
II
1 234
1.2
I
I
I
GND
I
0.6S±0.1
-WE
2.02.02.0
Connection Diagram
1. VCC
2. RT
3. GND
4. MOTOR
921
,uPC1470H
ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
V
Vcc
18
Circuit Current
14
2*
A
Package Dissipation
Po
Topt
1.2
W
-20 to +75
Tstg
-40 to + 150
°c
°c
Supply Voltage
Operating Temperature
Storage Temperature
*t
~
5s
RECOMMENDED OPERATING CONDITION
Supply Voltage Range
3.5to 16
VCC
V
ELECTRICAL CHARACTERISTICS (Ta = 25 °C, VCC= 12 V)
MIN.
TYP.
MAX.
UNIT
1.10
1.27
1.40
V
Id
0.5
0.8
1.2
mA
Reflection Coefficient
k
18
Saturation Voltage
V4 (sat)
CHARACTERISTIC
SYMBOL
Reference Voltage
Vref
Quiescent Current
~k
Line Regulation
V
Fig. 4
14 = 100 mA, VCC = 6.3 - 16 V
Fig. 2
~Vref/ ~V
v;:;t
CC
0.06
%/V
14 = 100 mA, VCC= 6.3 - 16 V
Fig. 1
-0.02
%/mA
14 = 30 - 200 mA
Fig. 2
-0.02
%/mA
14 = 30 - 200 mA
Fig. 1
0.01
%/oC
14 = 100 mA, Ta = -20 - +75 °c
Fig. 2
0.01
%/oC
14 = 100 mA, Ta = -20 - +75 °c
Fig. 1
~Vref/ ~Ta
Vref
* Pulse Test: PW
~
TEST CI RCUIT
Fig. 2
Fig. 1
(
AVref_ /,
V ref
AV cc
AVref
Vref
II.
I
I
"kl
k, Ak / AVcc,
AVref IAI4)
Vref
I '
lATa
r-----~------~----_Qvcc
(
Ak_
;')
T/
AI4
Akk~Ta
r-----~--------~------Ovcc
4
922
Fig. 3
%IV
k
V ref,
Fig. 2
0.4
~Vref/~IM
~
~k/ ~Ta
Temperature Coefficient
22
2.0
Fig. 1
n
RM1 = 44 n, RM2 = 33 n
VCC = 4.2 V, RM = 4.4 n
RM = 180
k'~Vcc
~kk/~IM
Load Regulation
20
1.5
TEST CONDITIONS*
14 = 10 mA
10 ms, Duty Cycle
~
2%
,uPC1470H
fig. 4
Fig.3
.-----~------~--------oVee
r-------------~----~Vee
APPLICATION INFORMATION
L
R : Torque Control Resistance
T
RS: Speed Control Resistance
Vee
+
c
,---I
1
--I
I
-------------
I
I
I
I
I
I
I
I
I
I
I
I
I
I
L ______________ _
I
_ _ _ _ _ _ _ _ _ _ _ _ -.JI
[BASIC EQUATION FOR THE MOTOR]
E t = Vref
1.
+ RT
.
Vref
(1 2 +~)
Vee
.
i2 =1(14 + Id
. RT
.
_.
14 - l m
RS
+ Vref
~
1.
.
V ref )
E t = V ref + R T ( j(14 + Id +Rs
1.
V ref
.
V ref }
Et=Vref+RT { "j((l m + RS)+ld+~
RT
1
Et = V ref { 1 + RS (1 +
l
K) f +
They also give:
RT id +
RT
K
.
1m
Em = Eo + Rmim
Eo=Vref {1+::
{ R
m
(1+~)}
+RTid
Eo: Back Electromotive Force
Rm: Internal Resistance (of th~ Motor)
(
K : Reflection Coefficient (= 14 !i2)
= RT
K
923
jlPC1470H
APPLICATION CfRCUIT
+
Note 1. The motor speed can be adjusted by the variable resistor RS.
Note 2. If RT max.
924
> K· Rm min, instability of the motor may occur.
Vee= 12 V
Rm = 19.5 n
RT = 330 n
RS = 1 kn
Eo = 2.3 V
K
= 20
1. ALPHA-NUMERICAL INDEX
2. QUICK REFERENCE GUIDE
3. CROSS REFERENCE GUIDE
4. MAINTENANCE AND OBSOLETE TYPES
5. GENERAL STATEMENT
*
NEC's INTEGRATED CIRCUITS FOR CONSUMER USE
o History
0
Types and Features
o Type Number Designation
*
*
*
*
0
Device Technologies
STANDARDS OF INTEGRATED CIRCUITS
HINTS ON CORRECT USE
TECHNICAL SYMBOLS AND TERMS
RELIABILITY AND QUALITY CONTROL SYSTEMS
6. AUDIO APPLICATIONS
6 -1.
CAR AUDIO
6-2.
HOME AUDIO
6- 3.
PORTABLE AUDIO
7. TV APPLICATIONS
8. DIGITAL TUNING SYSTEMS
9. CLOCKS & WATCHES
10. VOLTAGE REGULATORS
11. ARRAYS
12. OTHERS
13. APPLICATION NOTES
-
APPLICATION NOTES
INDEX
Page
CAR AUDIO:
- APPLICATION OF ELECTRONICALLY TUNED AM TUNER
FOR MOBILE RADIO pPC1215V
928
-
939
I
-
I .....................................
APPLICATION OF MOBILE AM TUNER I J..lPC1216V21 . . . . . . . . . . . . . . . . . . . . . . .
DIFFERENTIAL PEAK FM DETECTOR I J..lPC1028H I . . . . . . . . . . . . . . . . . . . . . . ..
960
- APPLICATION OF I J..lPC1200vl FM-IF IC FOR CAR RADIO . . . . . . . . . . . . . . . . . . . 966
- APPLICATION OF THE I J..lPC587C21 ANDI J..lPC1026CIINTEGRATED CIRCUIT
PLL STEREO MULTIPLEX DECORDERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
973
- EXPLANATION OF CIRCUIT OPERATION OF FM NOISE CANCELLER IC
IJ..lPC1176C 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1001
HOME AUDIO:
- EXPLANATION AND TYPICAL APPLICATIONS OF THE 1 J..lPC1235CI,
AN FM MPX IC FOR HIGH CLASS STEREO TUNER . . . . . . . . . . . . . . . . . . . . . . . . 1024
PORTABLE AUDIO:
-I J..lPC1222C 1 AND I J..lPC1222C(R)1 : THEIR OPTIMUM USAGE . . . . . . . . . . . . . . . . . . 1043
-I J..lPC1222C(R)I, I J..lPC1222CI ; APPLICATION TO SHORT WAVE BAND . . . . . . . . . . . 1045
• APPLICATION OF THE 1 J..lPC1197C 1 INTEGRATED CIRCUIT
PLL MULTIPLEX STEREO DEMODULATOR: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1049
I
I
- APPLICATION NOTE FOR J..lPC1277H EXTERNAL PARTS
AND CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . " . . . . . . . . . . . . . . 1065
-I J..lPC1350C I EXAMPLE OF APPLICATION CIRCUIT
WITH 4 n LOAD AND 0.7 W OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1069
DIGITAL TUNING SYSTEMS:
I
- APPLICATION CI RCUIT OF J..lPD1701C-0131 . . . . . . . . . . . . . " . . . . . . . . . . . . . . . . 1076
CLOCKS & WATCHES:
- PROGRAMMABLE PORTABLE CLOCK LSI: IJ..lPD832G SERIES
I " " . " ...... " ... " 1091
I
- HOW TO USE 1 J..lPD1990AC TIME KEEPING LSI FOR
MICROCOMPUTER SYSTEM . . . . . . . . . . . . . . . . . . " ....... " . . . . . . . "."
.0"
••
1106
VOLTAGE REGULATORS:
I
- APPLICATION CIRCUIT OF J..lPC7800H SERIES 13-TERMINAL REGULATORS ..... 1128
..
927
APPLICATION OF ELECTRONICALLY TUNED
AM TUNER FOR MOBILE RADIO tLPC 1 21 5V
1. INTRODUCTION
pPC1215V is a bipolar integrated circuit developed for AM tuners of electronically tuned car radio or car
stereo. The circuit contains a mixer, an oscillator, an oscillator buffer, I F amplifiers, a detector and AGC circuits
as well as a station detector (SO) that issues seek stop signal during station search. With a varactor tuned F ET
amplifier provided externally, an electronically tuned car-radio can be formed.
Because it is packed in a newly developed 19-Pin V-DIP, the area needed for loading is small and thus an improved manoeuverability and the prevention of misfitting trouble can be expected.
2. FEATURES
o
o
o
o
o
o
Suitable for an electronic tuning with a varactor diode.
Low level of oscillation that can minimize the tracking error due to the varactor diode non-linearity.
Provided with a large amplitude oscillation output terminal for PLL synthesizer.
Containing a station detector for the output of auto-scan-seek stop signal.
Containing a detector circuit and a small number of external components needed.
Packaged small.
3. BLOCK DIAGRAM
ANT
RF AMP
Detector Output
Local Output
+
---~---12
---@---,
I
I
I
I
I
I
I
I
I
-'
J"L
SO
Output
Fig. 1 Block Diagram
928
,uPC1215V
4. CIRCUIT DISCRIPTION
4-1 R F Amplifier stage
The antenna of car-radio is capacitive in the AM band, and the capacitive characteristics depend on antenna
length and diameter as well as cable length. Therefore it is difficult to form a tuning circuit with a varactor diode
in the R F amplifier input stage bacause the varactor is inserted parallel to the antenna equivalent capacitance. In
view of this difficulty, an untuned input circuit configuration with some loss in SIN ratio is common. For an
untuned RF input circuit, a J-FET is used since it is well matched to the high equivalent impedance of antenna
and it has a good linearity. Because of untuned input, the interference is larger. On the other hand, it has an
advantage that it does not need any antenna trimmer capacitance adjustment which is indispensable to p-tuned
radios. To use pPC1215V, J-FET2SK195 is needed for the RF amplifier. Pin 2 is provided to pPC1215V for the
output of AGC to the R F amp lifier.
r-----------------Q
V cc=1
aV
C6
C7
r----o
to Mix. Input
from AGC1
I
I
Vtune
'----s;-------I
t----
+
3
from AGC2
Cs
Fig.2 RF Amplifier
The R F amplifier circu it has the untuned input, a single stage series resonance circuit on the source side, and a
single stage parallel resonance circu it on the drain side. The DC gain of the J-FET is maxim ized by feeding I DSS.
The AC gain is maximized to desired signals by means of the source series resonance circuit but it is suppressed to
interference signals. Thus th is circu it configuration has a very small amount of loss and it is much insensitive to
interferences.
The AGC circuit are provided to both the input and the output sides of the FET amplifier. The AGC's have a
similar circu it configuration as that of .ALC for low frequency signals. It operates on a principle that the signal
of the saturated resistance of the AGC transistor) to
path is short-circu ited with a low impedance (about 50
suppress the signal transfer to the next stage. The increase in input signal first sets the AGC on the side of pin 4
into action to prevent MIX to be saturated. The AGC on pin 4 reduces the gain by about 25 dB through the
series resistance of the saturated resistance of 010 and R97. The AGC on pin 2 reduces the gain by as much as
40 dB. Since these AGC circuits can thus maintain the constancy of the output voltage for input voltage variation of as much as 65 dB altogether, good receiving characteristics can be obtained for a wide range of signal
intensity. Furthermore, an AGC circuit of ALC type suppresses the signal input to R FA-F ET. Therefore the
saturation of F ET can be suppressed, and, because of the overall signal level reduction, the R F signal applied to
the varactor diode is kept low enough to reduce distortions in modulating signals caused by the non-linearity of
the varactor diode.
n
929
,uPC1215V
4-2 Frequency Mixer Stage and Local Oscillator
The R F signal from the R F amplifier is delivered to the mixer stage conposed of 013, 014, 011, and 012.
After mixing an I F component is issued from pin 9. The input impedance of the mixer is determ ined by R 10
and it is about 2 kn II 8 pF.
The local oscillator is composed of 017 and 018, feedback resistances R 16 and R 17, L3 of external parallel
resonance circuit, and the varactor capacitance. Due to the non-linearity of the varactor diodes, the varactor
capacitance varies when an oscillator signal with a large amplitude is superposed. In such a case a tracking error
results because of a difference between the varactor capacitance in the mixer and that in the RF stage. Therefore
the oscillation level should be maintained low. It is maintained at about 150 mV r.m.S. over the whole frequency
range by R 16 and R 17.
The amplifier composed of 019, 020, and 021 are a buffer amplifier to deliver the local oscillation into the
P LL frequency synthesizer. The output amplitude from this fuffer is 4.0 V p-o and readily delivered to the CMOS
LSI.
.----__- - - - - - - - - _ - - Q v c c
1FT,
CF,
+ r r - t o 1st IF
I
I
c::I
I
C8
A5
;J;
C9
VtU~C3
Fig.3
-- -
L
3
Mixer and Local Oscillator
4-3 Intermediate-Frequency Amplifier Stage
The 1st I F amplifier stage is composed of an I F amplifier stage and AGC circu it. I nher~ntly it has a gain of
about 34 dB by the emitt&r-grounded amplifier of 034 and the output is drawn out from the emitter follower of
04,. Its gain is controlled by 028, 029, and AGC, circuit in such a manner that the gain reduction of up to about
27 dB is resulted from the increase of detected AGC, voltage. For further input level increase, the before
mentioned R F AGC is set into action. The input impedance of the' st I F amp lifier is determ ined by R32 and it is
about 2.5 kn II 40 pF.
to 2nd IF
r--t--.--.-----.-+--Q
Fig.4 I F Amplifier
930
Vee
,uPC1215V
4-4 Detector stage
The detector stage composed of 053 and a smoothing capacitance is located next to the second IF ampl ifier
composed of 047 and 048. The input impedance to pin 15 is determ ined by R 54, and it is about 4 kn II 20 p F.
4-5 AGC Circuit
pPC1215V has two independent AGC detectors and three AGC circuits. The AGCl detector supplies an AGC
control voltage to the first I F amp lifier, and, a somewhat delayed AGC control voltage to the RFAGC, both
determined by the DC voltage on pin 12 which is the smoothed detector output.
Since the AGC input voltage on pin 12 is directly coupled with the detected output on pin 14, the detected
output and the AGC range can be adjusted by the resistance Rg which is externally connected to pin 14. If Rg is
smaller, the AGC input voltage on pin 12 is less and thus the input voltage at which the AGC starts to operate
becomes larger to increase the detected output. If Rg is larger, AGC starts to operate at a smaller input voltage
and thus the detected output is maintained at a low constant level. The maximum distortionless detected output
(with a voltage depression effeet also taken into account) is 150 mVr.m.s. Accondingly, adjust Rg so that an
output of about 100 mVr.m.s. is obtained at an input of 74 dBpV for a modulation of 30 %.pPC1215V's are
classified into the following ranks according to the needed Rg resistance value in order that the lC's are used at
an optimum detected output with a minimum variation.
}
rank 0 ........ Rg: 12 kn
rank E ........ Rg -18 kn
These settings give a detected output of about 100 mVr.m.s.,
respectively.
rank F ........ Rg = 39 kn
ran k H ........ Rg = 00
On the other hand, the AGC2 detector shown in Fig. 3 is provided for preventing the saturation of RF amplifier or mixer due to the cutoff of AGC from AGCl detector by detuning or due to the interference signal from
the adjacent channel. Therefore it is inactive in normal operations.
from 1st IF
SD Output
to AGC
--4------t--J
to RF AGC
Fig. 5
AM Detector
Fig. 6 Station Detector
4-6 Station Detector Stage
The station detector (SO) is provided to stop automatic scan-seeking when a station is found. A high-level. DC
output is obtained by this detector when a station is found. It has almost the same circuit configuration as the
detector shown in Fig. 5. An I F signal of 450 kHz obtained by the I F amplifier is discrim inated from that of the
adjacent channel by a narrow-band ceramic filter CFM2-450ZL and delivered to this stage through pin 17. After
amplified by one stage by 054 and 060, the signal is demodulated by 036 and a smoothing capacitance, DCamplified by 065 and 069 to drive Darlington open collector transistors 072 and 073.
The input impedance on pin 17 is about 1.8 kn II 25 pF .
.Since the output is obtained from the open-collector transistor 073, the power supp Iy voltage can be set
arbitrarily, for example, to 5 V which is the same as logic system voltage.
931
?ft.
u
:::J
I
~
--
SIN (l:i=20 dB/.N)
........
-'" ~
T.H.D. (Vi=120 dB }.LV)
" ...
8
I
I
I
I
10
i
12
14
16
Vee - Supply Voltage - V
Fig. 8 Dependencies on Power Supply Voltage
933
,uPC1215V
+10
30~----------~----------~----------~----------
150
__
en
""0
+5
I
.g
ttl
a:
z
VI
E
N
C/)
i
I
~
dQ)
O
U:
c.5
C/)
E
I
20
....:J
B:J
0
0
>::s..
'-
B
....
~0
CD
""0
(.)
Q)
I
Q)
..J
I -5
~
0
VI
c
I
Q)
en
0
.E
Vcc=10 V
f = 1 MHz
fmod. =400 Hz
m = 30%
15
X
~
>
\
J
0.1
:::l
~
9o
n. t\ r...
0
IrJ ~V'-
>
V
-0.1
>
:::l
o
o
en
1
>
o
+-'
8
~
0
./V...-
1
o
>
V
0.1
. . . i --
....
....
....
f - I---
>
~~
I.
+-'
4
:::l
o
o
(J)
2
1
o
o
en
\
-._-
6
1
+-'
--
0.1
1'\
-
CIl
-
0.2
0.4
t- Time-s
>
0.6
Fig. 11 Rise-up Waveform
AGC Constants
R7 = 10 k!1, C14 = 10IlF
R6=10k!1, C13=lOIlF
0.8
o
0
0.6
0.2
0.4
t- Time-s
0.8
Fig. 12 Rise·up Waveform
AGC Constants
R7 = 10 k!1, C14 = 0.47 IlF
R6=10k!1, C13=221lF
935
jLPC1215V
from Mute
+
Det. Output
Fig. 13 AGC Smoothing Circuit
6-4 Tweet
Because provided with a detector circuit with little higher harmonics, J.LPC1215V is superior in low tweet.
However, the contained station detector works adversely with respect to the tweet. For suppressing tweet which
is especially a source of trouble during weak input reception, insert a capacitance of 0.01 J.LF between pins 14
and 16,and 0.047 J1F between pin 19 and the GND to suppress an AC component on pin 19 for stop-seek output.
Also, GND should be located as close to the GND pin 10 of the IC as possible. The station detection, which is only
necessary for auto-sean-seek and unnecessary otherwise, may be put inactive during mute off by using mute pulse
to forcefu Ily sh itt the level of DC bias of station detector input on pin 17 with a transistor switch.
7. OTHER TYPICAL APPLICATION CIRCUITS
7-1 Two Stage RF Amplifier
The one-stage series resonance circu it connected to the source of the R F stage FET which is shown in Fig. 7,
Typical Application 1 of J.LPC1215V cannot have high Q because the load Q is determined by the source impedance of the F ET. I n cases where I F and image interference ratio characteristics are of principal concern, the
RF stage can be composed of a double-tuning circuit.
Fig. 16 is an example of M-coupled double-tuning circuit. Table 3 shows the principal electrical characteristics.
C-couple double-tuning circuit can also be conceived. In this case it is necessary to design the circuit with the
change of coupling coefficient taken into account for varying the varactor capacitance. A two-stage RF amplifier
can be used also, with the adjustment of gain balance needed, To reduce IF stage gain, the increase of loss between pins 13 and 15 is also effective.
Table 3 Overall Characteristics (Application Circuit 2)
(T a = 25°C, Vee
= 10 V, f = 1 MHz, fmod = 400
CHARACTERISTIC
= 30
Vo
Usable Sensitivity
S/~~ =
Detector Output Voltage
Vi
mVr.m.s.
20 dB
Signal to Noise Ratio
= 74 dBJ.LV
Vi = 126 dBJ.LV
Vi = 74 dBJ.LV
I F Rejection Ratio
Vo =
I mage Rejection Ratio
= 30 %)
TEST CONDITION
Maximum Sensitivity
Total Harmonic Distortion
936
Hz, m
Vo
30 mV r .m .s., IF
= 450 kHz
= 30 mV r .m.s., f+2
IF
VALUE
UNIT
22
dBJ.LV
29
dBJ.LV
100
mVr.m.s.
0.5
%
50
dB
72
dB
64
dB
tLPC1215V
7-2 Application in LW-band
A LW/MW car radio using pPC1215V can be composed by providing respective separate tuning circuits for LW
and MW (with two sets of varactor diodes, altogether six in number) which can be selected by a switch. However,
to reduce the cost, it is usually to use only three varactor diodes which can be commonly used for LW and MW.
The coil selection is done by using switching diodes. This switching system encounters some difficulties in local
oscillator which are not suffered by conventional mechanical tuners. However, for the LW receiving frequencies
155-281 kHz, common padding capacitances and oscillation coil can be used in both LW and MW without any
increase in tracking error, thus the diode switching is unnecessary. This can be realized by rendering the LW-band
tuning voltage coverage a little broader than that for MW-band. For example, if
MW : 530-1 620 kHz be covered by 430-28 pF capacitance
and
LW : 155-281 kHz be covered by 470-25 pF capacitance,.
the tracking errors in the both bands are minimized with the constants:
Losc = 103.2 pH, Cpad = 470 pF,
stray capacitance for MW CSM = 30.8 pF, and
stray capacitance for LW CSM + Cs + CSL = 435.6 pF.
Thus, the addition of a 408.8 pF capacitance is only necessary to switch over to LW from MW.
Since the F ET of R F amp lifier is externally connected, the band can be selected by switching diodes as has
been done in conventional discrete circu its. When calculated using the above mentioned frequency bands and
varactor capacitances for The Application Circuit 2 of Fig. 16, the following data are obtained.
LR F-MW
CSM
LR F-LW
CSL
206 pH
18 pF
1 666 pH
167.4 pF
SW.Di
0.047 p.F
220 kD.
_~Vtune
220 kD. 470 pF
Vtune~
VD
I
I
l fD
u
0.047 .F
CSM
LW MW
Vee Vee
Fig. 14 MW/LW Switching of Local Oscillator
Fig. 15 MW/LW Switching of RF Amplifier
937
<0
W
OJ
~
Det. Output
ANT.
~
g
""C
Ir----------------------------------------------~----~--~,~-.------~--OVcc:10V
o
~
N
2SK195
~
U'I
<
MPC1215V
.-u.
q::t
"'f
~11 I
; 18 22
-t
kn
C
.l..
17
1 000
Vt
Ll:00~
L2:00~
1-3: 68T. Qu=80min.
4-6: 27T L=170 pH
T
~pF
L3: 7BR-6048Z. T1 : 7MC-4718N. T2: 7MC-10100CO
CF1 : CFM2-450BL
CF2: CFM2-450ZL
1-2: 63Y2T Qu=80 min.
2-3 : 6T
4-6: 2T
L=170 pH
VD1 - VD3 : Varactor Diode
C=500-30 pF
Fig. 16 Application Circuit 2
~
C
22
u.'
t=I :
R
l' "'"~
12
3.9 kn
,
0
so
Output
APPLICATION OF MOBILE AM TUNER !LPC 1216V2
1. INTRODUCTION
The ,uPC1216V2 is a bipolar monolithic IC developed as an AM tuner for a car radio and car stereo, and contains a series of circuits from radio frequency amplifier to AM detector. Since this IC is designed to accomodate
ceramic filters for its I F selective elements, an adjustment-free I F stage is achieved. Furthermore, having little
dependency of the maximum sensitivity on receiving frequency, it is free from sensitivity decrease toward 1 400
kHz and large increase of inter station noise around 600 kHz.
Because it is packaged in newly developed 19-pin vertical dual in-line package (V-DI P), the I C requires small
mounting area. In addition, it can be handled with much more ease and can be free of mismounting due to its
lead formation.
Th is document first describes the performance of each stage, the role of the external components and the characteristics with the changes of those components constants. Finally, an example of circuit application with
perfectly adjustment-free I F stage is described with the characteristics of this circuit.
2. FEATURES
•
o
•
•
•
•
•
•
Adjustment-free I F stage
Little difference in maximum sensitivity on receiving frequency
Large electrostatic breakdown strength at the antenna input
Extremely low pop noise
Low distortion
Superior two-signal selectivity
High sensitivity
Small package
3. ELECTRICAL CHARACTERISTICS
Table 1 is the list of ,uPC1216V2 pincipal electrical characteristics measured by the Fig. 27 test circuit.
Table 1. TUNER PERFORMANCE CHARACTERISTICS
(Ta = 25°C, VCC = 13 V, f = 1 MHz, fmod = 400 Hz, MOD
CHARACTER ISTIC
= 30 %, RL = 10 kQ)
TEST CONDITIONS
VALUE
UNIT
13
dBJ.,N
Max. Sensitivity
Input Voltage at which Det. Output Voltage is 40 mVr.m.s.
Usable Sensitivity
Input Voltage at which SIN is 20 dB
23
dBJ.,N
Detector Output
vi = 74 dBJ.,N
110
mVr.m.s.
Detector Distortion
vi = 74 dBJ..LV
0.4
%
Signal-to-Noise Ratio
vi = 74 dBJ..LV
54
dB
Overload Distortion
vi=126dBJ..LV
0.4
%
I F Rejection
f = 1 MHz, Vo = 40 mVr.m.s., IF = 450 kHz
72
dB
Image Rejection
f = 1 MHz, Vo = 40 mVr.m.s., f + 2 IF
74
dB
Selectivity
f = 1 MHz, Dof = ±1O kHz
45
dB
Tweet
vi = 74 dBJ..LV,
2 IF = 900 kHz
45
dB
3 I F = 1 350 kHz
50
dB
939
j.lPC1216V2
BLOCK DIAGRAM (Top View)
4. CIRCUIT DESCRIPTION
4-1
RF STAGE
The radio-frequency (R F) stage consists of an R F amplifier and an automatic gain control (AGe) circuit.
(see Fig. 1)
. At the antenna resonance circuit, the desired station signal is selected from the signals received by the antenna.
This signal is introduced into the Ie via pin-l, then amplified by transistors 01 .02 and 05 . 06,and outputted
through pin-4. When AGe is not in action, the gain of RF amplifier is about 34 dB (Fig. 2), and its -3 dB cutoff
frequency is about 14 MHz (Fig. 3). When a large signal arrives, AGe is set in action to attenuate the gain of the
RF amplifier. FigA shows the relationship between AGe voltage and gain attenuation. The voltage gain is approximately 34 dB for AGe voltage less than about 1.4 V, whereas, the gain attenuation in05 . 06 takes place
for an AGe voltage from 1.4 to 1.55 V because the bias voltage of 05 begins to decrease. A further large input
that brings more than 1.65 V or so will decrease the bias voltage of 03 to decrease the gain of 01 . 02. In this
way, the output voltage is kept the level constant for input voltage change within about 70 dB. Therefore, a
good receiving characteristics are obtained over the wide range from a faint to large input.
10
120
0.047 Jolt'
c:
;); "'"
0.047 JolF
~'
l~~I
C:LL2
o~
SG
en
~
~
RF
4
l'g
loon
+LL
VCC
~
0
-:i.-
17
3
n
S
I
..... ~f-'
TEST CIRCUIT
:>
/
I
Q)
OJ
"
~
o
I",,~
>
':)
/V
0.
8 0.1
I
,
I
~
I
vee
~~
0.0 1
0.1
/V
I
v
f
= 13
= 1 MHz
RL
=
1 krt
10
IIi - Input Voltage - mVr.m.s.
Fig .. '
940
Equivalent Circuit of R F Stage.
Fig. 2 Voltage Transfer Characteristic of
RF Stage.
100
,uPC1216V2
vcc = 13 V
O~--~----~~--~--~f
va
RL
I-----t.---+-----\-I--.~
= 1MHz
= 15 mVr.m.s.
=
1 kn
0 dB is ref erred to
Av=34 dB.
-201-----t-----+---~--+_----~-~
100
_....
t~
~
-I--
/"
>
r--"
E
I
-401------t-----+-----I-'l---+_----~--~
"-
Cll
OJ
~ 10
o
""~
>
-60
:J
a.
VCC = 13 V
= 1 mVr.rn.s.
vi
= 1kn
RL
The same test circuit as
in Fig. 2
:;
o
1
0.1
f -
10
Frequency - MHz
Fig. 3 Frequency Response of R F Stage.
4-2
100
TEST CIRCUIT
-80~--~----~----~--~----~--~
1.2
1.4
1.6
1.8
V17 - AGC Voltage - V
Fig.4 AGC Characteristic of RF Stage.
FREOUENCY CONVERTER STAGE
The frequency converter stage contains a local oscillator and a mixer (Fig. 5). The local oscillator is composed
of 013.014 and its oscillation frequency is determined by an LC circuit connected through pin-S. The mixer
consists of 0S·09·011. The RF signal fed through pin-6 is amplified by 011 (Av=10 dB, see Fig. 6). Then it is
mixed with the local oscillation signal within 0s·09and converted to an intermediate frequency (IF) signal by the
selectors (T 1 and CF 1) connected to pin-7.
A bypass capacitor C6 is connected to the emitter of 011 (pin-5) for the following purpose. Generally, factor of R F resonance circuit, which is the R F load, is inverse proportional to the receiving frequency, that is,
is lower at higher frequencies than at lower frequencies. In addition, the loss between pin-4 and pin-6 is proportional to the receiving frequency, that is, the loss is larger at higher frequencies. Therefore, the gain of the R F
stage in the high frequency region is lower by approximately 15 dB than in the low frequency region. In conventional I C's, sensitivity decrease in the high region and abnormal increase of inter station noise in the low
region have been experienced as shown by dotted curves in Fig. S. Countermeasures such as insertion of a damping resistor parallel to L T2 have been taken, but they could not solve the problems satisfactorily. Whereas, in
pPC1216V2, the capacitor C6 compensates that frequency characteristic and minimized frequency dependence
of maximum sensitivity as far as possible. The gain increase in high frequency region brings about some deterioration in image rejection, but it brings about the improvement in I F rejection (Fig. S).
If necessary, the mixer gain, concerned with maximum sensitivity, can be changed by varing the constant
of C6. (Fig. 9) Furthermore, the insertion of a several-hundred-ohm resistor in series to C6 makes the frequency
characteristics flat as shown by dotted curve in Fig. 7. In this case, the frequency characteristics become similar
to those of conventional I C's as shown by a dotted curve in Fig. S.
°
°
941
,uPC1216V2
10
lOOn VCC
0.047 I'F 120 n
~~".
J;
0.047 }JF
l00}JF
~ 'M"
;n
G
c6
,
':::L
5
I
;J;
TEST CI RCU IT
7'
V
.....
:l
a.
; 0.1
~~
o
Vee
I
o
/
::.
RL
I'
0.01
1.....
C6
III
11
100
Vi - Input Voltage - mVr.m.s.
Fig. 6 Voltage Transfer Characteristic
of Converter Stage
100
Vee
"
""- 'ti,
>::t
CD
"0
~
Y
Q)
OJ
2
~.....
:l
~
t7Z@
().
~:P
Q"«
Q~
~1.t
0'
lx><::l,;'"
S 10 t=.(IO-'/~.L
o
C-.-
I
o
.......
./
::.
1
0.1
,....,
/'
.........
,
-- -""
-- r-- --... -...
V
,X
"'"
,/'
"-,
v...
....
1---
/
"
1
~
1 300 PF
270 n
.......
11
:
. . r.
1/
V
Vi
en 20
E
ee
= 13V
= 10 mVr.m.s.
RL = lkU
The same test circui
as in Fig. 6
1
10
f - Frequency - MHz
,,",
><:.:
..........
100
gi
.;; E 10
:::=
E~
a ........
w.~
270
,
~I
: ®---ll--i'
1 500 pF
---: @}-H-'vv,-f.:
1'
"
560 pF
-
1/
1/
L.-;..
/, ..... 1F REJECTION-
1//
Fig.7 Frequency Response of Converter
Stage.
942
.~~ ...
RL
TEST CI RCU IT:
Fig.27
r--.....
~~
S)<::l.A'"
r"'-,
I--
= 13V
= 400 Hz
= 30%
= 10 kU
........
"
..,,- P< ~ ....,
I
:>E 100
I
~~
80
I
fmod
m
.I
IMAGE
90 i - - - ~REJECTION
en
1000
10
1
Fig. 5 Equivalent Circuit of Frequency
Converter Stage.
1000
13V
1 MHz
= 1 kU
= 560 pF
f
n
1
1
MAXIMUM SENSITIVITY I - (vo=40 mVr.m.s.)1
.L-1
J.__ +--r
" -'I,
~
.-::-
~
INTER STATION
NOISE (Vi a dB.uVL
r-,...c:: ~,
........
0.5
I
--r-t----T"-"::
1.0
f -
---
1.5
Receiving Frequency - MHz
Fig.8 Effect of C6 on Receiving Frequency
Dependency
jlPC1216V2
m 40
I
1J
VOLTAGE GAIN
VCC = 13V
f
= 1 MHz
= 1 mVr.m.s.
vi
RL = 1 kn
c
'iii
<.9
Q)
OJ
30
~
"0
>;:..
'" "
It-"~
l>~
./
'Vi
E
The same test circuit
~
~
as in Fig. 6
~
<100
10
3
C.- Capacitance- pF
Fig. 9 Maximum Sensitivity and Voltage
Gain in Converter vs. Capacitance C6
4-3
IF STAGE
The IF stage is composed of an IF amplifier and AGe circuit (Fig. 10). The IF signal taken out the converter
stage is fed through pin-ll to a differential amplifier 018 . 019. The amplified signal is output to pin-12 via
emitter follower transistor 021. The voltage transfer and frequency characteristics of the I F stage are shown
in Figs. 11 and 12, respectively.
When an input signal is increased, AGe circuit operates to lower the 020 base voltage, then the 020 collector
current which is the constant current source of 018·019 decreases, thus leading to the gain attenuation of IF
amplifier. Fig. 13 shows the relationship of the input voltage necessary for a constant output voltage to the AGe
voltage (V17). For V17 less than approximately 1.3 V the AGe circuit is inactive. For V17 at about 1.4 V the
circuit starts to work, and the voltage gain is attenuated accordingly to the increase of AGe voltage until V17
reaches about 1.5 V, the gain is no longer attenuated for V17 more than 1.5 V. In this case, the AGe circuit
for the R F stage is set into action instead.
943
,uPC1216V2
10
0.047 JJF
fl
en
~
;>
11
IF
12
':{
11
/
TEST CI RCU IT
I
'"""""
Q)
OJ
~
a
>....
Wi""
/
:J
e
/
:J
00.1
I
~
,,-
Vee
f
/
= 13V
= 450 kHz
/
1111
10
100
Vi - Input Voltage - mVr.m.s.
Fig. 11
Fig. 10 Equivalent Circuit of I F Stage.
1000
vcc -
13V
- 1 mVr.m.s.
Vi
The same test circuit as
in Fig.ll
'"
~
;> 100
.;:;
I
TEST CIRCUIT
It!
:J
Q)
~ -10r--~---+~-~--~--r--~
OJ
~
a
~
>....
e
1 I--......,-_~---l, l~ "
0.047 JJF
a
E
:J
Voltage Transfer Characteristic of
I F Stage.
.~
i'..
10
~ -20r--~----+-4-~--+---~-~
:J
I
I
i=
a
" ,
~ -30 Vce = 13 V
1'1..
a
~
:;-
f
u
...
0 10
·2
a
E
1
G
~
DE
15
~
}JF
-Va
oJ
~ra:
1
':i
/ ' .......
/
0
TEST CI RCU IT
,
.I
100
:l
Cl.
:;
§
I
+'
0.047 }JF
"*'
/
/
0
ro
/
~OJ
ro
0
>
a
I-
u
I
a:
q
Vce - 13V
f
= 450 kHz
fmad = 400 Hz
= 30%
m
= 10 kn
RL
I
a
~
~
0.1
1
/
"-
10
OJ
I
I
1
J
"
I'
10
I
T.H.D.
100
1000
Vi - Input Voltage - mVr.m.s.
Fig. 14 Equivalent Circuit of Detector
Stage
Fig. 15 Voltage Transfer Characteristic of
Detector Stage
945
,uPC1216V2
!g +1
~
a
:J
~
;- -1
a
I--
-
"0
f
= 450 kHz
fmod = 400 Hz
m
= 30%
Vi
= 94 dBJ.lV
RL = 10 kn
The same test circuit
as in Fig. 15
-2
"0
Q)
o~ -3
u
~ -4
*-
6
I
f
;"
.--
"0
..........
m
vi
RL
'\
~-5
= 13V
= 450 kHz
= 30%
= 94 dB,.N
= 10kn
Vee
::l.
.§ °1
EC
.... 0
The same test circuit as
in Fig. 15
1'1'
I·E
_ 0
~
"'-
-
~ 1-1-
I
I
rot;
V
,:
I
q
"~
\
I
a
r-=
"~
10 k
1k
100
I
I
2
~o
~
T.H.D.
:
3
u>R.
--_. -- -- T.H.D. -- T'=~<2.~
I--~--
30
10
5
100 k
I
10
15
Fig. 17 Characteristics of Detector Stage as
a Function of Supply Voltage
200
en
~
:>
E
I
OJ
:J
Co
/
~~
~
--'
~
~~
.,V
Q)
>
8
./
I
o
::l.
0
-~ -I-
.....
vee
=
f
= 450 kHz
""
...
13 V
100
10
1
RL -
Load Resistance -
kn
Fig. 18 Recovered Output vs. Load Resistance
946
~
fmod = 400 Hz
= 30%
m
= 94 dBJ.lV
Vi
The same test circuit
asinFig.15
V
Q)
a:
15
I
'ICC - Supply Voltage - V
Fig. 16 Electrical Fidelity Characteristic of
Detector Stage
¥
-
V19 - Voltage at pin-19- V
fmod - Modulation Frequency - Hz
a::; 100
f--
%
jlPC1216V2
(1) Waveform at pin-15. C14=1 0 pF
J:
Cl)
en
~
0
A
0.5
:r
I
~
(2) Waveform at loaded end. C14=10 pF
1.0
/ '\:""
o
o
>
o
0.2
0.4
0.8
0.6
0.2
(3) Waveform at pin-15. pin-16 is open.
I
/
4
/
!--i
'V ~
0.5
f
"\
o
\
I
o
;.:~,~<' ..
,' .::::,":,:.'.
'.',' .•. ::'
,.
0.8
0.6
1,0
6
o
..,'
(4) Waveform at loaded end. pin-16 is open.
8
2
0.4
'.:,"'.
~
/C .........
~;<
'<.
, .......,.
:<.: .... I··',:::··:·",::· ''':' ..,',
I'.. ':","',,": L:.'::':':::·"":·' I:,':':':':""::':":':: !::'.::"':.,.'
-0.5
-0.1
0.2
0.4
-1.5
0.8
0.6
o
0.4
0.2
0.6
0.8
...
Time- s
Fig. 19 Switch-on Responce
(VCC = 13 V, f = 1 MHz, fmod= 400 Hz, m = 30 %, Vi = 74 dBJ.LV, RL = 10 kn TEST CIRCUIT: Fig. 27)
1.2
1.0
2
a.
6.
Cl)
E 0.8
I
,~
i=
z
9
0
c
~
~0.6
a.
a. 1
a
a.
,
"
\
.~
~
z
9
./
~/
~N
,,/
0.2
o
\
"r
0.4
I
z
a.
>
tON
\
:.c
(J)
I
/'
,
I
>
o
,,""
o
10
/
/'
---
L
/
'/
VCC = 13V
=
1 MHz
f
fmod = 400 Hz
= 30%
m
= 74 dB~V
Vi
= 10 kn
RL
TEST CIRCUIT: Fig. 27
20
30
C14 - Capacitance - IlF
Fig. 20
Relationship of Switch-on Popping
Noise and Time to C14
947
jlPC1216V2
4-5 AGC CIRCUIT
pPC12l6V2 has two independent AGC detectors, one working effectively for one-signal reception, another
for two-signal (desired and undesired signals) reception. The AGCl controls three AGC circuits, two in the R F
stage and one in the IF stage, and AGC2 controls two RF stage AGC circuits.
AGCl works on the same principle as that for an AGC adopted in conventional receivers. The difference lies
in the detection of AGC, voltage. Contrasted with the conventional utilization of detector output as AGCl voltage, this IC provides a separate detecting circuit to obtain AGCl voltage by rectifying the output of the I F stage
before its entrance to the ceramic filter CF2. This configuration is devised to avoid the widening of tunable region
due to large input as well as the possible abnormal operation of AGCl circuit due to the use of ceramic filters.
Fig. 21 shows the voltage transfer characteristic of the AGCl detecting circuit. In this figure, the solid and dashed
lines are relationship of AGCl voltage V17 to input voltage at pin-18 and at the antenna, respectively.
AGC2 circuit is provided for the protection of the desired signal from the interferences by adjacent signals.
For example, assume that the antenna is receiving a distant station at frequency 1 000 kHz with the antenna
input of 40 dBpV and there is a interfering station at 1 040 kHz, aparted from the desired frequency by 40 kHz.
Fig. 23 shows the interference on the desired signal as a function of the undesired signal strength. I n the figure,
the solid curve shows how far the desired signal is suppressed with increasing the undesired signal when the desired signal is modulated with 400 Hz 30 %, and the undesired signal is unmodulated. With 22 pF capacitor on pin-5,
the output decreases about 5 dB even at the undesired signal of 120 dBpV. However, when AGC2 circuit is inaction with pin-5 grounded, the output depression is as much as about 20 dB. The dashed curve shows how much
interfering signal is output with the increase of undesired signal when the desired signal is unmodulated and the
undesired signal is modulated with 400 Hz 30 %. With 22 J.lF capacitor on pin-5, the desired to interference signal
ratio is as much as almost 20 dB even at the undesired signal of 120 dBJ.lV. Whereas, when AGC2 is not in action,
the interference noise output increases with the increase of the undesired signal. The noise output is larger than
the desired signal by 10 dB at about 105 dBJ.lV of the undesired signal. Further increase of the undesired signal
will saturate the R F amplifier and makes it work as a kind of limiter amplifier, resulting in the decrease of both
desired and undesired signal outputs. In other words, if receivers without AGC2 circuit set close to a transmission antenna of broadcasting station, they will receive this station instead of the desired signal, or produce no
sound at all.
The AGC2 voltage is produced by detecting the output of the frequency converter stage and smoothing it by
pin-5. As shown in Fig. 24, when the input signal more than about 94 dBJ.lV comes to pin-6, the voltage V5 more
than 0.6 V is obtained to actuate the AGC2 circuit.
948
j.lPC1216V2
>
I
,.....
a.
.....
co
OJ
01
I
,
... -...
~
- ~-
1--
V
I
,.....
VCC
f
m
>
o
20
'= 13V
= 450 kHz
=
40
0%
,,
i
/
..... ~
r--- r--.~
I
;
0 100
r---
OJ
W
>
004~
,
~'"
SG
c:
g
LL+
V
:: 100
80
/
0
u
Cll
a:
I
a
:::.
10
10 k
120
100 k
IIi - Input Voltage - dBJ.N
Fig. 21
1-1-
"0
TEST CIRCUIT
60
f
E
I
.....
:J
a.
II
~
a
>
~
:>
I--
I
-- 100-- --- -'"
13V
Vce
f
- 1 MHz
fmod = 400 Hz
m
= 30 %
= 74dBJ.LV
Vi
TEST CIRCUIT Fig. 27
en
1. --
\
C
1000
V
VCC = 13 V
f
= 1 MHz
m
= 0%
TEST CIRCUIT Fig. 27
2
R4 - Resistance -
Voltage Transfer Characteristics of
AGC1 Detector
Fig. 22
1M
n
Recovered Output vs. R4
1.0
+2or---------------------------------------~----~
DUMMY ANTENNA
VCC=13 V
DESIRED SIGNAL
Ides=1 000 kHz SG1~5 pF
vi = 40 dB~V SG
a::l
"0
I
::J
UNDESIRED SIGNAL lund=1 040 kHz
TEST CIRCU IT: Fig. 27
2
I-t--o
J.u.
160-R g{n)T ~
m
I~-
...........
_V~
~ 0.8~--r__1--_+--~--~~~--~--r__1--~
.~
a.
co
~0.6r---r_--r__4--~--1+--_+--_+--~--~~
!:l
9-
o
::J
o
>
"§
I
§;
o
~0.4r-~---+--~--+-~r--1--~--4---+-~
~-20r_--~----_r----~----~--_4----.~+_--~--~
I
Vee = 13 V
o
:::.
0.2 I---I--l---f---+--!-+----f-----l f
m
-404~O~--~----~----~----~----~----~----~--~
=
1 MHz
a
%
°7~0~~~80~~~9~0--~-1~0~0--~-1~1-0--L--J120
Vi(undl - Undesired Signal Input Voltage - dBJ.LV
Fig. 23 Two-signal Receiving Characteristics
=
"i - Input Voltage -dBJ..lV
Fig. 24
Voltage Transfer Characteristic of
AGC2 Detector
949
jlPC1216V2
4-6
OTHERS
Table 2 shows input/output impedance of each stage, and Table 3 DC Voltage of each terminal. Table 4 is
a list of external components. The table summarly describes recommended constants and purpose of the external components along with the influences of the change in these constants on the overall characteristics. Fig. 27
shows a typical application of pPC1216V2 which are used to measure overall characteristics.
Table 2 Input and Output Impedance at Terminals
PIN No.
INPUT IMPEDANCE
OUTPUT IMPEDANCE
FUNCTION
TEST FREQ.
1
RF AMP.
1 MHz
6
MIX AMP.
1 MHz
11
IF AMP.
500 kHz
14
DET.
500 kHz
18
AGCl DET
500 kHz
12
IF AMP.
450 kHz
15
DET.
400 Hz
TYP.
5.8
34
2.5
7
3.2
4
2.8
12
7.0
6
160
20
4.3
UNIT
kn
pF
kn
pF
kn
pF
kn
pF
kn
pF
n
pF
kn
120 n
100n
Note; RX= RX Meter
VCC(13 V)
Fig.25 Input Impedance Test Circuit
950
jlPC1216V2
o.o47rFI~ ~
Note 1 ;
Note 2;
RX = RX Meter
SG = Signal Generator f=450 kHz, m==30 %, vi=94 dBJ..I.V
V = AC Voltmeter
Output impedance at pin-15 is defined equivalently asthe R L which gives an output 6 dB lower than
the output voltage that will be obtained for R L =00.
Fig.26 Output Impedance Test Circuit
Table 3 DC Voltage on Terminals (Test circuit: Fig. 27)
PIN No.
VOLTAGE (V)
PIN No.
VOLTAGE (V)
1
2.8
2
2.0
3
0
4
11
5
1.3
6
2.0
7
11
8
11
9
0
10
0
11
3.5
12
3
13
1.1
14
9
15
1.8
16
3
17
1.1
18
9
19
11.5
951
I
I
/
V
2
-60
0
o
20
Fig.29
0
0
§
6
200
u
I 100
0
q
2
L
./
0
o
o
Fig.30
/
V
J:
~
~
NOISE
Recovered Output and Total Harmonic
Distortion vs. Input Voltage
Vy V
II
Ql
120
//
ro
J: 4
co
'0
0
/V
1/
0
a:
80
100
60
40
Vi - Input Voltage - dBJ.LV
v
e
>
"'..."-
.~
0
.52
OJ
T.H.O'\
= 13 V
=
f
1 MHz
fmod = 400 Hz
vi
= 74 dBJ.,tV
RL = 10 kn
e
S
'2
\
\
vee
0
.;:;
I 300
1\
\
-50
*8
B:::J
1-40
~
en 400
E
\
o
10
:>
\\
\
~
500
~
13 V
f
1 MHz
fmod : 400 Hz
:
m
30%
RL : 10 kn
:
- '~
a:
4
_I--
vee :
,
~
'0
l-
ci
I
./
"0
ro
/
....
I
en -10
~
I
0
....
u
5. -20
'c 8 S
0
o
§
~~
./
~i"'""
v
./
i-20
-
T.H.O.
I
40
60
m - Modulation - %
--
.......
,/
80
100
Recovered Output and Total Harmonic
Distortion vs. Modulation
100
+10
en
"0
...I
0
::J
Co
S-10
*10
I
e
0
.;:;
0
8
t>
(5
u
§
'-30
~
6
ro
0
l-
/
r--.......
If
'c0
o
"2
E
~ -20 J:ro 4
a:
80
Vo
I 2
,
Vee
f
\
m
m=80%
m=30 %1\
Vi
i\
I\~
",
RL
'.
~
T.H.IO~
-
en
= 13V
=
1 MHz
= 30%
= 74 dBIlV
= 10kn
III -
I IllTn
1k
100
fmod - Modulation Frequency - Hz
Fig. 31
956
Electrical Fidelity
"0
"\
160
\\
\
:~
,
~
\
40
Ql
C/)
l
10 k
o
-30
/
"
\
20
Ij
~-'
J
\
~
r\
--
I
I
I
/
\
I
1\ J
-20
/
/ vee
: 13V
=
f
1 MHz
fmod = 400 Hz
= 30%
m
= 20 mVr.m.s.
Vo
RL = 10 kn
-10
0
+10
+20
f - Oetu ne Frequ ncy - kHz
Fig.32 One-signal Selectivity
+30
jlPC1216V2
90
en 80
"C
o
IMAGE REJECTION
~
..............
I
Vee
fmod
m
-10
en
" ""'-
~\
RL
u
c
~ 70
~
A maximum output value
of an output beat
\~
-20
Q)
= 13V
= 400 Hz
= 30%
= 10kO
E
c
I
\,
~ -30
\
I\.
'\
I
\
r?-40
\
i'..
"\
V
"- --
3 IF
--j--
o
--"'....
40
80
60
100
vi-Input Voltage-dBIlV
Fig. 33 Tweet Characteristics
1"F REJECTION
Vee
--
~
= 13V
RL
= 10kn
USABLE SENSITIVITY (sJN=21 dB) I - -
/
I
C20
':;
120
-
I
:..-:-:-:+:-::T
.!.
1
I
1
,I
~ MAX. SENSITIVITY (vo=40 mVr.m.s.l
';;;
'r:;;
c
(/)10
20
"'- j"--..
/
"C
Q)
-60
..---><........
~~
fmod = 400 Hz
= 30%
m
~
'\
}
'....
-50
2 IF
---
~
> 30
k..
f'.... r-.
/'
........
V
50 I
\
~
/
60
\\
"C
/'
,
0.5
1.0
1.5
f - Receiving Frequency - MHz
Fig. 34 Receiving Frequency Characteristics
957
jlPC1216V2
6. CAUTION
6-1. Don't earth the pin-4, pin-8 or power line connected with these pins by mistake. If this is done, the IC may
be damaged.
6-2. When the resistance (100 12) is not used between pin-19 and battery, the capacitance (22 J.LF) of RF
stage power line should"be change for less than 0.5 J.LF.
120
22 JJ.F
~
n
~_--o
+
100 IlF
0.5 IlF
Battery
+
Il PC1216V2
(Safety precaution)
The following application is recommended to keep away the above problems.
~----~~--~VCC
+
IlPC1216V2
* Add a capacitor (0.01 J.LF) between pin-8 and the tuning coil.
** Replace the resistor R2 (12012) with a coil (22 J.LH).
6-3. The C6 should be changed the constant more than 3300 pF in a long wave application. If the constant is
560 pF the conversion gain and maximum sensitivity may be insufficient.
I
6-4. The oscillation amplitude at pin-8should be more than 3 VP-p. if not, the deviation of maximum sensitivity
will be increase.
6-5.
Connect the C10 and CT3 with the power line instead of GND. If not, some IC's will not oscillate.
6-6. The ceramic filter CF1 should be selected so that an oscillation signal leakage may be small. A large
leakage ceramic filter causes maximum sensitivity drop in appearance, because the AGC circuit operates
with the leakage.
6-7. The center tap of 1FT T2 should be used so that the good performance can be obtained at lower supply
Voltage.
958
ttPC1216V2
7. DIFFERENCES BETWEEN /JPC1216V and /JPC1216V2
7-1. The /JPC1216V2 is improved in the supply voltage dependencies of detector output voltage, maximum
sensitivity and local frequency. (See Fig. 35)
7-2. The /JPC1216V2 is improved in the temperature dependencies of detector output voltage and maximum
sensitivity. (See Fig. 36)
The resistance R4 is not necessary in /JPC1216V2 appl ication.
7-3.
vi
E
'- ...........
~
E
I
180
,I
Vj=74 dB,N
~
~ ...
,,-
g-
I-IPC1216V2
100
:>
--..... ......
......
I
a
::::...
~
c. 120
\
V 0=40 mVr.m,S.
\
I
:l ':;
E ' ::;
.~ .~
0
o
TC1216r
(.fJ
-10
+2
~
"PC12\6V2
co
u
a
..J
---~p
I"
-2
;
-4
/
6
.........
>:t
~ -----
1/
8
80
60
20
I
E ~ 10
E ' ::;
~ c
2c5i
0
I
16
Fig. 35 Supply Voltage Dependencies
(f=1 MHz, fmod=400 Hz, m=30 %)
~216V
-..,--~
I-IPC1216V2
~
'" '""
~
,
""
Vj=74 dBI-IV
Vo=40 mVr.m.s.
I
"~
"PC121r2
(.fJ
fo=l 450 kHz
10
12
14
VCC - Supply Voltage - V
"
CI)
._ 0(j)
I-IPC1216V
-'-
"0
:l ':;
,
u
o
=:w---
,/
I
80
+20
CI)
2c5i
160
E
-..;;:::::
VCC=13 V
f=l MHz
f mo d=400 Hz
m=30%
vi
............. I-IPC1216V
120
;
oI
J
140
2 -10
18
-40
o
20
40
-20
Ta - Ambjent Temperature -
60
80
°c
Fig. 36 Ambient Temperature Dependencies
959
DIFFERENTIAL PEAK FM DETECTOR I1PC I 028H
1. INTRODUCTION
The /lPC1028H is a silicon monolithic integrated circuit intended for an FM I F amplifier with a differential
peak detector. This detection system is required minimum external components, is easy to adjust and is of cheap
overall cost, compared with the other FM detection systems such as the ratio detector, the Foster-Seeley detector,
the quadrature detector and so on.
The /lPC 1028H contains a three-stage direct coupled differential amplifier, a low-pass filter, a differential peak
detector and a regulator.
Outline is a 7-lead single in-line package, so that it is suitable for use in automotive radio receivers, where small
mounting space is required.
2. DESCRIPTION OF INTERNAL CIRCUIT
Fig. 1 Equivalent Circuit
7
OUTPUT
As
6
DET. INPUT(-)
BYPASS
2~----~~------+---~------~
2-1 FM-IF AMPLIFIER AND LIMITER SECTION
The intermediate frequency (IF) signal taken out from the front end section, passes through the selection
devices connected between the front end and I F section, and is applied to the input terminal of the /lPC1028H.
It is amplified by the differential amplifier 0 1 to Os and 0 12 ,0 13 through the emitter follower Os. In order to
obtain excellent limiting characteristics, the differential amplifier 0 12 and 0 13 is of transistor current sink
structure. The limiting sensitivity V j (lim) of the /lPC1028H is 48dB/lV TYP. When the level of the I F signal
exceeds 48dB/lV, the differential amplifier 0 12 and 0 13 is pushed into the limiting region and starts limiting
action. When the level of the I F signal increases further, not only the differential amplifier 0 12 and 0 13 , but
the differential amplifier 0 4 and Os, and at further higher levels the differential amplifier Oland O 2 is pushed
into the limiter region and the effect of the limiting action is improved.
960
2-2 LOW-PASS FILTER SECTION
The IF signal amplified by the FM-IF and limiter section contains high harmonic frequency components of
the IF signa/. These high frequency components are sufficiently attenuated by the low-pass filter composed of
R 14, R 1 S , R 16, C3 and C4 •
J1 PC1028H.
2-3 DIFFERENTIAL PEAK DETECTOR SECTION
After high frequency components are eliminated by the low-pass filter section the I F signal is injected into the
FM detector circuit 0 17 to 0 23 , through the emitter follower transistor 0 15 , On the other hand, the I F signal is
injected from 0 15 to the LC circuit; a single tuned coil connected between pin 5 and pin 6, and a capacitor connected between pin 6 and GNO. Then the I F signal is transformed into the AM component proportional to a
certain frequency deviation, due to the characteristics of the LC circuit. The AM signal is injected into 0 18 and
0 21 through the buffer amplifier 0 17 and 0 22 . The 0 18 and 0 21 work in class AB to half-wave rectify the AM
signal. That is, the AM signal is peak detected and smoothed by capacitors C 1 and C"2. The signal which has
been turned into a smoothed audio frequency component is amplified by differential amplifier 0 19 and 020' and
the output is taken out from pin 7 through 0 24 •
2-4 VOLTAGE REGULATOR
The constant voltage is composed by 06' 0 7 , 010,011,016 and 0 3 with the standard voltage of Zener diode
Os' and supplies stable bias to the I F amplifier and the detector sections.
3. CHARACTERISTICS
As shown in Fig. 2, the -3dB limiting sensitivity of the J.lPC1028H is48dBJ.lV TYP .. The gain distribution of
automotive radio receivers is devised so that a limiting sensitivity of about 10dB will be obtained, when a
front end of about 30dB gain, two ceramic filters and one transistor to recover the filter loss are used before the
J.lPC1028H.
The J.lPC1028H alone shows the excellent characteristics of 0.1% TYP. distortion factor with 30% modulation
and 80dB/lV input voltage, and 0.3% TYP. distortion factor with 100% modulation. SIN of 65dB TYP.can be
obtained.
An AM rejection ratio is 40dB TYP. and 50dB TYP. with AM component of 30%, and a FM component of
30% (±22.5kHz) and 100% (±75kHz) respectively.
~he
Fig. 2
o
'*I
>
E
c
3
...
~
;
a
2
J:
CD
-20
'\
10
V
~
1
20
V
.~ -30
3)
V V
Q)
~~-40
E~
40
I -50
ai a:
50
-60
60
~ ~
\\
I
o
-so
70
20
40
1.2
':~~7~Hl_
t22.5MHl
AM '''''0.= 400Hz _
MOD =30%
OdB = 165mV
~~ ~ p
't:
~
0
u
1.0
O.S
£
0.6
'c
§
E
600
I
Ql
Cl
0
'\
I
I
-70
~
>
c
~,=
\ \ r
ci
:i
...,:
F''!D
",.f--.. ~
V
*I
Jcc = IOV
r-..
DETECTOR OUTPUT VOLTAGE, TOTAL
HARMONIC DISTORTION vs. CARRIER
FREQUENCY DEVIATION
700
1.4
.. V
~-
"Oc.
1
~
i5
u
'c
§
-10
vL.
o
I
o
.~
Fig. 3
DETECTOR OUTPUT VOLTAGE, AM
REJECTION, TOTAL HARMONIC
DISTORTION, SN RATIO vs. INPUT
VOLTAGE
V
60
/'
V
80
100
ilJ.' - Carrier Frequency Deviation - kHz
The modulation (modulation frequency deviation) versus detector output characteristics are shown in Fig. 3,
the detector shows a high output of 165mV TYP. with 30% modulation, and 550mV TYP. with 100% modulation.
In Fig. 4, the detector output versus modulation frequency characteristic is shown. When applying deemphasis at the output of the J.lPC1028H, de-emphasis characteristic of 75 J.lS can be obtained by connecting
a 0.01J.lF capacitor between pin 7 and GNO in combination with the internal impedance. When FM stereo
demodulation IC (MPX) is to be used after the J.lPC1028H, a capacitor of 100 to 200pF should be connected
between pin 7 and GNO to eliminate the high frequency components of the carrier, and de-emphasis should be
applied at the output of the MPX IC.
961
,uPC1028H
DETECTOR OUTPUT VOLTAGE vs.
MODULATION FREQUENCY
Fig. 4
Vee
I
AI
C!l
"C
I
~
Vi
0
(5
.............
>
:>
~
0
-5
~
~
'\\
Co·O.Ol,.F
t
0
I
-10
..a
;:,
-15
10
lk
100
I MOO
-
Co
\
=10V
= 10.7MHz
-± 22.5kHz
= 8OdB,.V
Co =0
.l20;--'\-
\
lOOk
10k
Modulation Frequency - Hz
Fig.5 shows DC output voltage of pin 7 (V 7 ) versus frequency, and V 7 at 10.7MHz is 3.5VTYP .. This DC
output can be utilized as the AFC voltage.
Fig. 5
6
5
>I
l"-
e:
a:
-r-..
..........
~
Vee = lOV
Vi = 8OdB,.V
1'\
,
\
.,
&
:g
~
Fig. 6 TEST CIRCUIT
S-CURVE
3
I
\,
">-~:>----....-tr----o
AF Output
'"\
I"-
>
" ----
Det. Coil:
L = 9,.H,Cl - 22pF,OU - 50
TKACA·17473
TaKa INC., or Equivalent.
~
1
-600-500-400-300-200-100
0
+100+200+300+400 +500 +600
(10.7MHz)
I - Carrier Frequency - kHz
The peak frequencies of Fig. 6 can be determined from the following equations.
1
fOI = 211V'L (C I
fO=
211'
j
L (CI
+ C2)
C
+y)
fOI is the series resonant frequency and gives the lower peak frequency, f02 is the parallel resonant frequency
and gives the upper peak frequency, fa shows the center frequency.
Fig.7 shows the power supply voltage dependencies of the pPC1028H. The characteristics indicate that
operation at 6 or 7V is possible, but giving a safety margin, the recommended operating range has been made 8
to 15V.
962
jlPC1028H
Fig. 7
TOTAL HARMONIC DISTORTION,
DETECTOR OUTPUT VOLTAGE, CIRCUIT
CURRENT vs. SUPPLY VOLTAGE
1
2.0
1.B
20
f
f
·
·
10.7MHz
• 400Hz
8OdBj£V
""0
Vi
0
, ...
In
1.6
~
1
1.4
~
-2
:; -3
~
~
~ 10
g-5
U
1' ... -
~--
I
S
;,
T.H.D. (~f·
... -r---
-B
0.2
I--
~
~-7
0.4
... ...
~~-
':;
a1-6
0.6
~~
Icc
0-4
o
O.B
-- -
E
I
c:
Q)
>
1.0
VO~F
...
«
'0
1.2
,
T.H.1D.
5
t
75kHzl- f - -
(~If - t J2.5k~ZI- f - 15
10
v cc
- Supplv Voltage - V
As can be seen in Fig. 7, the characteristicS are smooth and without irregularities within the recommended
voltage range, giving stable operation.
Fig. 8 shows the temperature dependencies of the IlPC 1028H. The circu it of the IlPC 1028H is designed so
that the temperature dependencies have been kept to a minimum.
Fig. 8
LlMITTING SENSITIVITY, DETECTOR
OUTPUT VOLTAGE vs. AMBIENT
TEMPERATURE
BO
Vee
In
'0
>
70
:s.
>-
c:
2!
u
.~
I
I
Vi
I
:
22.5kHz
= 8OdBj£V
=
I
0
I
I
C>
~
"0
I
-1
:
>
"~ 40
~
"E
o
:J 30
I
~
10V
Q)
50
III
~
~f
C>
~ 60
:§
I
Q)
In
&
=
10.7MHz
f
f"OD • 400Hz
20
10
o
--
Vi(liml-
I
I
3
I
:
-4
I
I
I
~ -5
;,
... -4
:I
~:I
...
U
:I
l: 10
U
c. -5
-;
0 -6
0 -7
-S
~
Q)
0
I
-9
I -10
CJ
CJ
0
I
........... ~
§ 0.6
·E
f
.f
CJ
·8 0.4
E
10
J: 0.3
/--
co
(5
I- 0.2
X.
0
r:
......
I 0.1
----
---
.-" ~
T.H.D.1 (A f = ± 75kHz DEV.l
r---
I
-
r---
V?"dAf =±22.5kHz DEV.l
f
= 10.7MHz
f,t.AOO
= 400Hz
V·I".
= SOdB/JV
V OAF" OdB = 136mVr.m.s.
I
0
:~ 0.5
0
d
«
-
'* 0.7
LL
~
VOAF, Icc, T.H.D. vs. Vee
O.S
I
2
4
6
_
T.H.D.2(A f -± 22.5kHz DEV.1
""-
Recommended Operating
0
-
I
I
I
I
8
10
12
14
~anget--I
16
Vee - Supply Voltage - V
965
APPLICATION OF ,uPC1200V FM-IF IC FOR CAR RADIO
1. INTRODUCTION
pPC1200V is an FM-IF amplifier employing a quadrature detector.
The IC utilizes a new type of muting circuit to sufficiently reduce white noises from weak signals, detuning
noises and side detection outputs occurring in both tuning and detuning. Consequently, this device can combine
with an FM noise canceller without causing malfunction of the canceller due to white noises to lead to degradation
in characteristics of both devices, thus achieving full performance of the canceller. Unlike ones with conventional
mut,ing methods, the IC produces greater outputs as the tuning point is approached, making selection of a program easy,
The package is the newly developed 15-pin V-DIP, which greatly reduces mounting area and meets requirements of car radios which calls for high density mounting of parts.
2. FEATURES
•
Low undesirable noise level: -60 dB
•
Very low lateral uncomfortable sound either upper or lower from the tuning point.
•
Capability for effective use of FM noise canceller.
•
Occupatio'n of minimum area in P.C. Board.
•
Easy to handle because of its V-DIP construction.
•
Free of mismounting in P.C. Board due to its lead tuning point.
• Wide range of power supplies: 7 to 12 V
3. GENERAL SPECIFICATION
PACKAGE DIMENSION (in millimeters)
(Fig. 1)
2 8tO 2
:.....-:
195 MAX
~
XX XX
MARKING
cdcxi ":N
1 2 3 4 5 6 7 .8 910111213141
I
I
I
I I
11
I
~
966
~
;;;.-
- - -__ to F M Detector
45dB
25dB
.1
Fig. 5 Block Diagram of I F Amplifier
Intermediate frequency (IF) signals delivered from
the front end section is supplied, through a sffiecting
80
co
device, to pin 2 of the J.LPC1200V to be amplified by
-0
IF1 AMP and IF2 AMP, which consist, respectively,
.g
of a three-stage differential amplifiers with 45 dB in
a:
voltage gain (R L=330 n) and a single stage differential
·0
amplifier with 25 dB in voltage gain (RL=1 kil).
6
"i'
coc:
The ceramic filter inserted between pins 4 and 6 is
effective in improving signal-to-noise ratios (SIN)
and usable sensitivity of a radio receiver. This is
because wide bandwidth noises are all amplified by
\
\
I
co
~V
OJ
en
I
z
......
20
en
filter. The narrower this bandwidth is, the higher
/
,//
'l
;;;;;.-
I~/ -with a capacitor
40
to within a bandwidth specified by the ceramic
ex
'"
I//
~
z
/
60
the front end and IF 1 AM P before they are lim ited
the SIN ratio becomes, (Vn
with a c~rami~-filt~r
/1
~I
20
V
Vcc =10 V
f
=10.7 MHz_
fMOD=400 Hz
=±22.5 kHz
ld
80
60
40
Vi - Input Voltage - dBIlV
100
Fig.6 Signal-to-Noise Ratiovs. Input Voltage
1I~).
Fig. 6 shows SIN ratios measured by the circuit shown in Fig. 4. Those for the same unit except for
the filter between pins 4 and 6 replaced by a 0.022 J.LF capacitor. This comparison clearly proves the effect
of the ceramic filter between pins 4 and 6.
(2) Quadrature FM Detector
J.LPC1200V employs a well-known quadrature detector which allows easy adjustment with only one tuning
coil. Further, the detector has no steep drop in detected output due to variation of ambient temperature
which occurs in a ratio detector at high temperature.
(3)
Level Detector and Controller
The two types of the level detector are built-in; LEVEL DET. 1 and LEVEL DET. 2. LEVEL DET. 1
detects decrease in input signal level while LEVEL DET. 2 detects deviation from the tuning point. Both
outputs are added and converted in the controller to the signals V11 required for controlling the noise
suppressing circuit. (See Figs. 7 and 8.) The capacitor to be connected to pin 11 takes a part of smoothing
AM modulated components. A smaller capacitor makes the response speed of a control circuit fast but gives
degraded AM suppression characteristics and larger side peaks.
969
j.lPC1200V
Vo
0
/
Cll
-0
CI)
Cl
a
-20
::J
S::J
4
-40
/
>
VCC=10 V
=10.7 MHz
f
V
/
(5
>....
,-'"~
I
CI)
Cl
a
3
(5
>
.....
.....
-~11
a
B
u -60
........
~
CI)
0
I
V\
Cll
/v
I
A
0
V
c:
2
~ """-....
0:
I
kn
fl(n
VR-1O
>
Cl
a
-20
I
I
(5
>....
::J
5"
-40
-
........
0
I
4
\
I
\,
--
j
V
Cl
3
kn
7~
5kn
!9
(5
>
c:
2 0:
I
->
......
~
>
CI)
VR=10
~
VCC=10 V
vj=80 dBIJV
30
40
Vj -
50
60
70
o
80
I
I
o
-0.5
I F I nput Voltage - dBIJV
o
0.5
10.7±f - Frequency - MHz
Fig. 8 Pin-" Voltage vs. Frequency
Fig. 7 Pin-11 Voltage vs. Input Voltage
(4)
"
~
Vl1
~
-60
CI)
A
/\ Vo
",~'\.. - V"V_
---" ~ - --'"~ ""
a
B
u
/
FJ
J
CI)
(:)
~kn
0
l'
.........
V
Noise Supressor
When noise level increases due to decrease in input voltage or due to deviation from a tuning point,
this circuit decreases in gain to reduce uncontortable noises to be demodulated by the FM detector.
10
FM
IF INPUT--.......-~
Q-DET.
Detector
Output
NOISE
SUPPESSOR
t-----t13 Output
Level
Detector ---..-fCONTRO LLE R I - - - - - - - - - - - - - . . . .
Output
+
Fig. 9 Block Diagram of Noise Suppressor
Degree of noise suppression depends on the voltage at pin " ,
noise suppression degree. As shown in Figs. 7 and 8. V"
V,,: the higher V"
increases gradually with decrease in input level or
further deviation from the tuning point, generating gradual variation in the output.
970
produces the greater
)lPC1200V
Signal
vcc -10V
f
,. 98 MHz
l~-.f--#--4----+--i--fMOD
400 Hz
At
- ±22.5 kHz
a
-8~2~0--~0----~+---~4~0--~60~--+---~100~~120
ui - Input Voltage - dS",V
Fig. 10 AUDIO OUTPUT vs.INPUT VOLTAGE
fc 9B±M - Carrier Frequency - MHz
Notes: Figs. 10 and 11 those obtained
from application circuit (Fig. 18)
Fig. 11 AUDIO OUTPUT vs. CARRIER FREQUENCY
Setting of noise suppression levels and side peak magnitudes are at customer's proposal by selecting
a desirable resistance value of VR to be connected to pin 11. VR=O gives the same characteristics as from
conventional ICs, in which limiting sensitivity is maximum while noise levels and side peaks are left not
suppressed. Increasing the resistance value of the VR, though lessening the limiting sensitivity to some degree,
achieves decreased noise levels and side peaks. This is shown in Figs. 10 and 11. The semi-fixed resistor to be
connected to pin 11
should be adjusted and set to an appropreate resistance value so that optimum
characteristics are obtained.
Unlike car radio units with a conventional muting method where outputs abruptly disappears when
input level is smaller than a specified level, p PC1200V does not have such unnatural abruptness but offers
an optimal FM tuner for field intensities peculier to a car radio.
5. TYPICAL CHARACTERISTICS
CD
"0
~ 0.8
c
.g
~ 0.6
(5
'c
I
a:
~ -20
~
0.4
~-40
"0
iii
ci
i
y~
'iii'
a:
~
o
l-
.~
Signal
0
I
u
~
2.0
I
g
I
)
;:)
0.2 ;-60
o
~
o
'0
;:)
...:
o
~-80
I
o
::.
0
/
11
\
\
\
"
\
\
~
...
I
c
.g 1.5
\
"-
Vee =10Vf
= 10.7 MHz
fMOD = 400 Hz
Dev. =±22.5kHz
AMR
"'-"
""
~
u
:;
9- 400
E
(5
'c0
~
I
1.0
100
Fig. 12 v o , AMR, T.H.D. vs. Vi
120
Vce = 10
= 10.7 MHz
f
fMOD = 400 Hz I
= 100 dS",V
Vi
;:)
0
I
0
:0
;:)
iii
I-
0
---- ---- ~--T.H.D.
40
60
80
Vi -IF Input Voltage -dS",V
800
cf!.
...:
0
I
~O
0
0
20
it:,.
40
60
f - Modulation - kHz
80
100
Fig. 13 v o , T.H.D. vs. IJ. f
971
,uPC1200V
7r---~----~----r---~----~--~----~----,
VCC"10V
O~--~----~--~--~~----+---~--~~--~
>
I
~ 6
co
~
-5·~---+-----+----+-----r---~~~-r----r----4
(5
>
:l
:l
9-
5
=c:l
u
6o -10~---+-----+----+-----r----+--~~----r----4
5~---4~~~~~~~~+---~r----r----1-----i
o
o
«
I
I
u
4
0
VCC·l0V
f
=10.7 MHz
ld z :1:22.5 kHz
vi =l00dBJ.'V
-15
..0
0
>
tOA
-201~0----~30-----100~--~3~00----~----~--~~--~----~·
-0.3
-0.2
fMOO - Modulation Frequency - Hz
>::t
I
20
';P.
60
c
.Q
t::
1.5
E
~
'r;;
c
Ql
en 50
Ol
0
0
'c
§1.0
I
'2
5
~
~
.~
I
iii
U
I
-
I-
u
~
;,-
0
v o (vi=l00 dBJ.'V)
,
:g
..........
~
en
---
.Vj(lim)1
f
0
= 10.7 MHz
At
:C
~
,
0
o
0
g
Of
T.H.O. (V i'" 100 dBJ.'V)
"
8
10
I
J
I
12
14
----
1.5
«
0.2
0.3
0:4
>
E
I
I
;
~
a.
:l
'E
J:
:.:i
~
U
I
l-
E
I
~ 1.0
5
~
0
::>
~15
15
E
~
0
0
'c0
~ 40
I
6
*'I
60
u 10
':;
Ol
c
fMOO'"400 Hz ":1:22.5 kHz
.. 50
ci
ot
I
'r;;
I
.y 5
'0
,... .........
~10
>::t
co
~
.:;
.;:;
«
I
10.5
40
10
---
,, ' -
,
,,
9-
°E
'E
:.:i
E
0.1
20
20
2.0
70
I
I
15 ;15
I
1;;
---
ll"-O)
,"-,,
E
«
0
:~
20 0
50
5
J:
~
16
T.H.O. (v i-100 dBJ.'V)
Vcc - Supply Voltage - V
0L-
0
0
~30
Fig. 16 vo, ICC, T.H.D., Ui(lim) vs. VCC
0
25
50
75
Ta - Ambient Temperature _ °c
Fig. 17 vo, ICC; T.H.D., vi(lim) vs. T a
6. TYPICAL APPLICATION
2SC1674
or 2SC1675
C.F.
T
FIE
SFE10.7MA (MURATA Co.)
154AC41109Z (TaKa INC.)
DMA-040 (SANKEN ELE. LTD,)
GAIN
33 ± 3 dB
NF
5 dB MAX.
f
88- 108 MHz
+--
~~ 0 ,
()
11
00
-...J
V.C.O. CONTROL
13'C) 0"12
)
o
14
.N
T
5t
R5
03
~
R7.
A
0 4 ~~
°v
~"
Kl'
~R 9
>
R,o
>
>-
~
"
R 1!)
R22
~11
Ql1
R13
YO,2
l~~
R20
R'6
0 19
't
R21 ~
>
!A2~
'vv
1:
R 26
.--- R28'
R29
t:=
025
"'023
~
29 0 30
R33
011
027
R23
R12
yyy
IVV
R14
0 20
017
'" 016
V
-.... 05
R17
R'~
I
R18
"o
R43
: R42
R37,>
o
R44
~
1
~
'Yv
N
31.
031
0)
R39
R38,
028
o
~
R45
035
036
032
R40
~~"
l/
R31
R30
34 R32
>R36
R27
018
.A
R6
R2!)
.yy
R8
'v'",
K:04)r-.
~~D2 R3
~
GN
3~()
2,l;(
:')1
R
U1
PHASE
COMPOSITE AUDIO AMP. DETECTOR
INPUT
OUTPUT
INPUT L.P.F. L.P.F.
R46
R41
R47
~
033
034
~
037
038
R57
':)7
>
~R48
R58
R49
R59
RIGHT OUTPUT
LEFT OUTPUT
--
R60
049
""
M' B
~53
R55
,...--
0" j1-
~
R50
~54
059
lJ
R69
AA
R70
RS2 >R63'
R~ D,~~ R"~
056 57
'v
H56
R7I
058
O"rrt
045 046
O"~
Jo"
050
'"
R51
055
:>
R61 ~
R52f
L
:
(
9 L.P.F
054(
R66 H67 Rs
( 6
STEREO INDICATOR
LAMP.
610
19kHz
MUNITOR OUTPUT
j.lPC587C2,j.lPC1026C
Voltages of each pin (Vcc
= 10 V,
Refer to Test Circuit)
1.
2.
3.
4.
5.
6.
7.
pPC587C 2
10V
2.8V
4.7V
7.4V
7.4V
10V
0
pPC1026C
10V
2.1V
4.7V
7.4V
7.4V
10V
0
8.
9.
10.
11.
12.
13.
14.
pPC587C 2
2.1V
2.1V
-
2.1V
2.1V
2.1V
-
pPC1026C
2.1V
2.1V
-
2.1V
2.1V
2.1V
-
5. DESCRIPTION OF CIRCUIT
(1) Input Buffer/Amplifier and Bias Supply.
Vee
INPUT
2
PRE
OUT
3
The equivalent circuit of the bias supply and input signal
amplifier is shown in Fig. 5.
In Fig. 5 the stabilized voltage Vs is expressed by 01 +
02 - VBE(OBE1) - VBE(OBE2) and is constant against
variations of the power supply. The various bias voltages
are established, based on this stabilized voltage.
Since 03 operates as an emitter follower circuit, the bias
voltage V2 of the input ampl ifier is expressed by the
following equation.
' - - 4 - - - - - - - - t - - - V4
GND
(HIGH)
7
TO DEMODULATER
On the other hand, the reference voltage V 1 to the DC
Bias Supply and Buffer/ Input Amplifier. amplifier and VCO, to be described later, is determined by
04 attached to the voltage stabil izing circuit.
The input signal amplifier is composed of transistors 05, 06, 07 and resistors R7, R8, and R9, and capacitor
Cl. Since 06 is a multi-collector transistor, it's collector current is nearly the same as the collector current of
05, and the current gain is close to unity.Cl is for frequency stability, and its value is 5 to 20pF. The voltage
gain of the input signal ampl ifier is determined by the feedback circuit R7, R8, and 05, but since the impedance
of 05 can be neglected, the voltage gain can be approximated by the following equation.
Fig.5
Av(AF) =
R7 + R8
---'--~
R7
Stereo signals entering pin (2) are amplified by an amount indicated by the above equation, and then
introduced to the phase detector of the PLL circuit through terminal (3). Besides the above, stereo signals pass
through emitter follower 09, from the emitter of 05, to be injected into the stereo demodulator circuit.
979
j.lPC587C2,j.lPC1026C
(2) Demodulator Circuit.
(Low)
Rout
(High)
5
38kHz
38kHz
--u-
Jl..
Lout 0---+----.---.,
4
R69
R70
Fig. 6
Demodulator Circuit.
Fig. 6 is a stereo demodulator circuit. The circuit consists of a common double-balanced type detector circuit,
and the stereo signal is injected into the lower transistors 039 and 040 while the 38kHz subcarrier is injected into
the upper transistors 041, 042, 043, and 044. Stereo demodulation is accomplished by the subcarrier switch ing
the above transistors. R50, R51, and R52 are feedback resistors inserted for the purpose of cancelling the cross
talk components produced during switching. The subcarrier is a 50% duty cycle 38kHz wave obtained from a
bistable multivibrator (flip-flop) circuit, into which a 76kHz signal produced by the VCO is injected. In both
the ~PC587C2 and ~PC1 026C the stereo lamp and stereo demodulation are synchronized and accomplished
by 059. The base of 059 is controlled by the stereo lamp circuit, and when the stereo lamp is turned ON, 059
will also be turned ON and a 38kHz subcarrier of reverse phase will be injected into the' demodulation circuit.
041, 044 and 042, 043. On the other hand, when the stereo lamp is turned OFF 059 is also turned OFF. and
an in-phase 38kHz subcarrier is injected into 041, 044, and 042. 043 so that a monaural wave is obtained
from output terminals (4) and (5).
(3) Lamp Driver.
DET-IN
Vs
Vee 38kHz
38kHz
Jl.
V4
R59
.IL..
19kHz
L...r
19kHz
R69
R70
8
L.P.F.
6
9
L.P.F.
STEREO INDICATOR
LAMP
Fig. 7
S80
Lamp Driver Circuit.
jlPC587C2,jlPC1026C
Fig. 7 shows a lamp driver circuit with it's auxil iary circuits. Transistors 045 and 046, resistors R53, R54,
R55, R56, R59, and R60, with the addition of external discrete capacitors (8) and (9) form the phase detector
circuit and low-pass filter. In the phase detector circuit the product is formed by the 19kHz (obtained by
counting down the 76kHz frequency produced by the VCO with;a bistable multivibrator (flip-flop)) injected
from the bases of 045 and 046 and the pilot signal contained in· the stereo signal. The high frequency
components of the product are eliminated by the L.P.F., and only terms concerning the phase difference remain.
0
This 19kHz signal differs 90 in phase with the 19kHz signal required· by the PLL loop circuit (That is, it is in
synchronization with the phase of the pilot signal), and when the pha?es are precisely in step the DC component
obtained through the phase detector circuit and L.P.F. will be at maximum level, and when the phases shift the
DC component will decrease. This change in the level of the DC component will move in a positive direction at
terminal (8), and a negative direction at terminal (9). Th is state, when expressed as an equation will take the
following form.
Pilot signal
ep(t) = Epcos wpt
19kHz signal e19(t) = E19cos(wp + t+cos(2wp+t ........ Eliminated byL.P.F.
The lamp drive circuit is composed of transistors 047 to 057 and accessory resistors. 047 and 048 compose
a circuit for amplifying the control voltage obtained from the L.P.F., and 049 is the active load of this
differential amplifier. Now, if the collector current 1047 of 047 and the collector current 1048 of 048 change by
Alc (Alc = 1048 - 1047) due to the control current passed through the phase detector, Alc will flow intact into
the base of 051. 051 is a multicollector transistor, and it's collector current will amplify the change Alc of the
base current and 06 will become biased by this current. And, when this diode is biased transistor 053 will
operate causing lamp driving transistor 056 to be turned ON, thus the lamp will light. On the other hand, when
053 turns ON it will draw the base current of 058, and as a result 058 and 059, will be turned on and stereo
operation will start. Since 051, 052, 06, R62, R63, and R64 form a positive feedback loop, when the lamp is
turned ON the rise of current will be abrupt. In addition, transistors 054, 055, 056, and resistor R68 form a
negative feedback circuit, which composes a current limiting circuit for performing current limiting action.
(4) Phase Detector and DC Amplifier.
DET-IN
11
L.P.F. L.P.F.
13 12
Vs-+------+--r~--~~----
'-----+-- V .C.O.
V1-+--+-~~----~r-~----
Fig. 8
Fig. 8 shows the phase detector and DC amplifier. The
19kHz signal obtained through the dividing circuit will
switch the pilot signal of the stereo signal coming into
terminal (11), and will supply a DC voltage proportional
to the phase difference of these to the DC amplifier composed of 012 to 016. When the phase difference of the
19kHz signal and pilot signal, entering the phase detector,
0
is 90 the control voltage of the PLL circuit will be O. When
the phase of the 19kHz signal advances from the above,
a positive control voltage will be produced, and when the
19kHz phase lags a negative control voltage will be
produced.
When this state is expressed as an equation, it becomes
as follows.
Phase Detector and DC Amplifier.
981
,uPC587C2,,uPC1026C
= Epcoswpt
Pilot signal
ep(t)
19kHz signal
e19(t) E19sin(Wp+¢)t
ep(t)
(Note) (To be precise, 19kHz is a square wave.)
Ep.E19 {
2
sin¢t + sin (2wp+ ¢)t
= e19(t) =
=
Ep~19 sin¢t
} ......... Eliminated by L.P.F.
The DC ampl ifier is composed of transistors 012 to 016, and converts the changes of the control voltage to
current to be sent to the VCO.
(5) VCO
V.C.O.
14
Fig. 9 shows the VCO (Voltage Controlled Oscillator).
This circuit is basically a comparator, which produces
oscillations through variations of the reference voltage.
Now, when transistor 019 is operating, both 021 and
022 will become conducting and the instantaneous
reference voltage of the comparator applied to the base
of 019 is expressed as follows.
R
21
Q
23
On one hand, current will flow from the emitter of 022,
and this current will charge the external discrete capacitor
through R20. The charging time tl of this capacitor is
expressed as follows:
Fig. 9
VCO
When the above charging is completed the comparator will be switched-over and 018 will be turned ON.
At this point, the reference voltage V L of the comparator will become as follows.
The charge accumulated in the external capacitor of terminal (14) will discharge at a rate determined by the
external resistor R and capacitor C.
(6) Divider Circuit.
Vs
----~----~-------.----~~------~~~----__.
R36
R37
.JLJL
76kHz
IL
38kHz
Lr .n...
1.S ..n.
19kHz
Fig. 10 Divider Circuit.
982
19kHz
,uPC587C2,,uPC1026C
Fig. 10 shows the divider circuit. This circuit is a bistable multivibrator (flip-flop). This multivibrator serves
to produce 38kHz and 19kHz, 50% duty cycle, voltages from the 76kHz voltage generated by the VCO. The
38kHz voltage is the subcarrier required for FM stereo demodulation, the 19kHz having a 90° phase difference
with the pilot signal is required as the control voltage of the PLL, and the 19kHz synchronized with the pilot
signal is required for driving the stereo lamp and controlling the stereo switch.
6. CIRCUIT APPLICATIONS OF THE PLL-MPX IC
The J-LPC587C2 and J-LPC1026C are most suitable for use as the FM multiplex demodulatior circuit of car
rad io and stereo sets.
Applications of the J-LPC587C2 shall be described following:
(1) Overriding Stereo-Monaural Switching Circuit.
Stereo multiplex operation on the J-LPC587C2 becomes possible when the 19kHz pilot signal of an ordinary
input synchronizes with the 19kHz generated within the IC, and through this the lamp driver transistor is excited
and the gate circuit is turned OFF to inject a 38kH~ subcarrier into the demodulation circuit. However, cases can
be imagined when stereo ON operation is required regardless of the input conditions of the MPX input circuit.
A general circuit for this case is shown in Fig. 11. As described before, to obtain stereo-ON operation it is
necessary to pass current through the base of transistor 051. but since 047, 048, 049, and 050 consist a
differential amplifier circuit, stereo-ON operation can be obtained if the voltage of terminal (8) is kept higher
than terminal (9). The overriding switching circuit will differ according whether a plus or ground potential is
employed as the control voltage. But, for example, when manual switching of overriding monaural operation is
required, this can be obtained by grounding terminal (9).
R70
®-----------L.P.F.
100n
Fig. 11 Overriding Monaural Circuit.
983
,uPC587C2,,uPC1026C
(2) Beat Interference of AM Reception.
1
5kn Vol.
470PF
r -I
I
I
I
AM-ON
Switch
--+--JVV\,--I16k n
veo
(fil_ _ _ _ _ _ _ _ _
01
cl
I
.,)"
Differing from conventional coil type stereo demodulation circuits, the J,.LPC587C2 has an internal oscillation
circuit, and there are cases when the internal oscillator
voltage of the PL L becomes a source of interference during
AM reception. To solve this problem it is necessary to stop
the VCO. If, as described before, attention is paid to the
fact that the VCO is an oscillator circuit utilizing a
differential comparator, it can be seen that the VCO can
be stopped by grounding the input terminal (14), and the
76kHz oscillation stopped.
Fig. 12 VCO Stop Circuit.
(3) Adjustment of the Lighting Level of the Stereo Lamp.
The method of adjusting the lighting level of the stereo lamp is made clear from the characteristics of the
circuit of Fig. 7. That is, the lighting level can be changed by varying the input ON level of the differential
amplifier composed of transistors 047, 048, 049, and 050. Ordinary, the base potential of transistor 048 will
rise when the 19kHz pilot signal increases, and this ON level will reach a value determined by selecting the
collector current of 047 at a value four times that of 048. Therefore, the lamp lighting level can be changed by
varying the offset voltage of the above differential amplifier. Methods of changing this are shown in Figs. 13 and
14.
®
Fig. 13
984
Fig. 14
-n
cO·
Coupling capacitor of the PLL input.
Divides the audio frequencies and 19kHz
frequency.
L.P.F. of the PLL loop.
Determines the locking range
and the PLL loop gain.
~
0'1
0
Monitor terminal for determining
the oscillation frequencies of the
19kHz VCO, monitor PLL, by
connecting a counter.
en
CI'l
~
~.
"0
.....
o·
:J
0
-t'I
I
Low·pass filter for operating lamp.
C = 0.22J.,LF. Determines the low
region cutoff frequency according
to the time constant made in combination
with the internal impedance.
m
x
.....
en
~
:J
~
0
Vi·
Q
en
.....
en
()
Semi-fixed resistor for determining
the oscillation frequency of the VCO.
Set the resistor so that the oscillation
frequency of terminal (10) is 19kHz.
0
3
"0
0
:J
en
:J
.....
CI'l
0
-t'I
.....
::::r
en
""tJ
r
r
:s:
INPUT
""tJ
o---::.t1-+II-----+---~
X
-~
"'C
Lamp series resistor. Lamp current is
determined by, Vcc - VCE(sat)
R
Input coupling capacitor. C = 2.2J.,LF.
Has an effect on the low frequency
and separation characteristics.
The low region frequency characteristics
by are determined the time constant
made in combination with the 50kn
input impedance.
-
U)
0
I~,
u.
:2.
r-<:t
0
Cll0
MPX input
C3
+
Stereo Indicator lamp
2.2~F
loon
R5
.
...--.._--, lamp protector resistor
u.
:2.
q
0
C!
~
Ol
M
C!
u.
Ol
o
~
M
:2.
a
R3 __~~~_C_7~____________________~_____ Vcc
C6
~________~~~~~~
~----'-------G Vcc
o-+-.....---f:t---Q Rch·OUT
......-~I----C!
R17
~
C"')
19kHz L.P.F.
Bl·13 Korin Giken
+
o-t--+---f:t----o
lch-O UT
987
.uPC587C2,.uPC1026C
Printed Circuit Board
Components Layout for P.W. Assembly (Copper side)
Rl =
R2 =
R3 =
R4 =
R5 =
R6 =
988
56kO
56kn
3.9kn
3.9kO
1000
100kO
R7 = lkn
Ra=16kn
R9 = 5kn Vol.
RlO = 13kO
Rll = 13kO
R12 = 3.3kO
R13
R14
R15
R16
R17
= 2kO Vol.
= 2kn Vol.
= 3.3kO
= 3.3kO
= 3.3kO
Cl = 470pF
C2 = 100l'F
C3 = 2.2s.&F
C4 = 4.71'F
C5 = 4.71'F
C6 = O.OlI'F
C7 = O.OlI'F
Ca = 0.22s.&F
C9 = 0.471'F
ClO = 0.22s.&F
Cll = 0.0471'F
C12 = 4.71'F
C13 = 4.71'F
C14 = 10l'F
C15 = 10l'F
jlPC587C2,jlPC1026C
7. EXAMPLE OF A FM TUNER EMPLOYING A PLL-MPX IC.
Circuit examples employing the J.,LPC587C2 and J.,LPC1026C as the MPX section are shown in Figs. 16and 17,
respectively. And, in Figs. 62 and 63 are shown examples of overall circuit applications of the J.,LPC587C2
employing the J.,LPC1028H as peak detector and FM-I F amplifier, and the J.,LPC1 026C employing the J.,LPC577H
as the FM-I F ampl ifier.
Overall characteristics of the overall circuit application of Fig. 63 are shown in Figs. 62,64,65, and 66.
The difference between the J.,LPC587C2 and J.,LPC1026C has been descri~ed before, but it should be noted that
when the J.,LPC577H is used in the final stage of the FM-I F amplifying circuit, since the detector output is not so
large, it is desirable to use the J.,LPC1026C, which has a high lamp lighting sensitivity, as the MPX. And, when
the J.,LPC1 028H is used as the FM-I F ampl ifier, since a large detector output can be obtained, it is desirable to used
the J.,LPC587C2 as the MPX.
8. TYPICAL CHARACTERISTICS of JJPC587C2 (Ta = 25° C)
Fig. 18 CIRCUIT CURRENT
VS. SUPPLY VOLTAGE
Fig.19
VOLTAGE GAIN
vs. SUPPLY VOLTAGE (Monaural)
(J.,LPC587C2)
(J..LPC587C2)
25
5
4
Quiescent
E 20
I
;:;)
«
5
o
6
Fig.20
10
14
8
12
Vee - Supply Voltage - V
-3
-4
-5
8
10
14
12
Vee - Supply Voltage - V
6
16
Fig. 21
CHANNEL BALANCE
3
I
2
60
f = 1 kHz
Vin(L+R)= 300mV
ClJ
u
c:
co
co
co
(L-R)
o
~ -1
~ 50
I
c:
.g
eco
40
g.
30
(f)
c:
.1
~ ....
-1--
Left
-- Right
I-
-~_--
""'~-
f
-- -- --
= 1 kHz
Vin(pilot)
= 30mV
Qi
~ -2
u
I -3
c:
~ 20
~
U
a:i
.s:: -4
I
ci 10
u
ClJ
-5
-6
CHANNEL SEPARATION
(J..LPC587C2)
(J..LPC587C2)
4
co
16
vs. SUPPLY VOLTAGE
vs. SUPPLY VOLTAGE (Monaural)
'0
= 1 kHz
·ro
-
u
~
3
'0
....c:
~
co
(f)
6
8
10
12
14
Vee - Supply Voltage - V
o
16
6
8
10
12
14
16
Vee - Supply Voltage - V
989
,uPC587C2,,uPC1026C
Fig.23 FREE RUN FREQUENCY CHANGE
Fig.22 CHANNEL SEPARATION
PILOT INPUT LEVEL (~PC587C2)
vs. SUPPLY VOLTAGE
VS.
60
Vcc = 10V
Left
--1--- -- ---- Right
40
I--
I
~
-- ---
+200
c
co
..c
U
>u
~
+100
C
co
Cl)
C.
g.
0
J:(19kHz )
~ 30
Q)
c
c
§
~ 20
a:
u
10
(I)
en
o
o
60
20
40
80
Vj(pilot) - Pilot Input Level - mV
-100
U:
-200
I
~
-300
6
100
(~PC587C2)
4
co
I I
R -+L-
"C
I 50
c
.g
~
~ 40
en
Cl)
V
-
--- --
V
f\
0.01 0.03
0.1
3
0.3
f - Frequency - kHz
10
-2
(.!)
-4
"
Vcc = 10V
Vin = 300mV
o dB=
-6 dB
Iff-
'0
Vcc = 10V
Vin(pilot)
=30mV
20
~
.......
> -8
u
en
0
Cl)
..c
I
~
~ -6
\
c
~ 30
2
'co
L -+R\
Q)
990
16
10
12
14
Vee - Supply Voltage - V
vs. FREQUENCY (Monaural)
~PC587C2)
60
10
8
Fig. 25 VOLTAGE GAIN
Fig.24 CHANNEL SEPARATION
ys. FREQUENCY
g.
' ....
(I)
(I)
I
ci.
~PC587C2)
+300
I
f = 1kHz
~ 50
I
c
.g
N
30
r\
I
;:) -10
\
Ol
."
§
§co
.... 800
1
0.7
0.5
§
x
~
T.H.D.= 1%
/...--
-- f - -
V
co
./
0.1
I 0.07
• 0.05
r:
600
.§
~
I
r
c:
0.3
I
f = 1 kHz Monaural
/
::l
C.
ro
o
/
..J
J:
I
---
E
Vjn '('L~R) = 300mV
B
.~
II
>
10V
3
o
(,uPC587C2)
1200
I
400
I
I
x
E200 I
0.03
-S
f-
0.01
10
3050100
3005001k
o
3k5k 10k 30k50k100k
8
10
12
14
VCC - Supply Voltage - V
6
f - Frequency - kHz
Fig. 32 CHANNEL SEPARATION vs. OSCI LLATOR
FREE RUNNING FREQUENCY
(,uPC587C2)
60
/,
~ 50
I
c:
.g
eco
/
c:
c:
::l
0Ol
U:
\,
Cl
.=c:c:
""r-..
)
Qi
>-
CJ
c:
/ f\
1/
30
V
~ 19.00
Ol
Ol
~
~
1--"-
L-- V
~
-
U:
co
6
Fig. 33 OSCILLATOR FREE RUNNING FREQUENCY
vs. AMBIENT TEMPERATURE
N
(,uPC587C2)
~ 19.50
Ol
7
40
c.
Ol
CJ)
I
Vee=10V
Vjn(pilot) = 30mV
16
B
20
1E
I
.~
ci
~1O
o
I
~
'+-
o
18.00
18.50
-25
19.00
20.00
fosc - Oscillator Free Running Frequency - kHz
Fig. 34 POWER DISSIPATION OF LAMP DRIVER,
SATURATION VOLTAGE OF LAMP DRIVER
vs. LAMP CURRENT
(,uPC587C2)
~
200
~
180
>
5
160
~140
co
..J
o
§
120
100
V
.~
co
.~ 80
."
o....
60
Ol
~ 40
a..
I
20
o
992
25
N
75
50
°c
Fig. 35 OSCILLATOR FREE RUNNING
FREQUENCY vs. ELAPSING TIME
(,uPC587C2)
~ 19.20
Ol
>
'+-
I
....
.::!
Ol
;§
o
Ta - Ambient Temperature _
/
o
--V
20
V
..J.?:-;7'
/
/
V
/ 4
c.
E
co
..J
'+-
3
Pd
o
Ol
en
!!l
'0
-
2
~
~ ~ VeE (sat)
40
80
60
IL - Lamp Current - mA
o
>
~
g
Cl
.~ 19.00
c:
::l
a:
a
1E
....
!w
u
>
19.10
U:
J:
I
100
c:
c:
.g
e
::l
1
>-
CJ
~~
", -
Ol
18.90
~
B
.~
. Vee = 7V. I L = OmA
1
I
Vee = 10V. IL = 40mA
Vee = 16V.IL = 100mA
18.80
o
I
CJ
-.-0
18.70
0
2
t - Elapsing Time - min.
3
j.lPC587C2,j.lPC1026C
Fig. 37 PILOT LEVEL (Lamp ON-OFF)
vs. AMBIENT TEMPERATURE
Fig. 36 CAPTURE RANGE vs.
AMBIENT TEMPERATURE
(J,LPC587C2)
5
-
4
E
I 14
2
a;
Q)
OJ
co
~
---
...J
c::
::J
V--
. - '~
0
~
10
I
8
a...
g -1
u
I -2
c::
c.5 -3
...--i---f--
-4
-5
-25
r--
---
.§ 6
f-- ~
"a.
:s
4
Vee = 10V
--
-----
LAMP OFF
~ I----
2
o
0
25
50
75
Ta - Ambient Temperature _ °e
Fig. 38 POWER DISSIPATION
vs. SUPPLY VOLTAGE
(J..tPC587C2)
-25
0
25
50
75
Ta - Ambient Temperature _ °e
Fig. 39 CAPTURE RANGE
(J..tPC587C2)
100
500
>
~
y
~
~ 12
C
~
~t\Mpl ON
16
.......-
E
LAMP-OFF
I
400
a;
I
c
Vee = 10V
80
>
Q)
...J
o
"~ 300
a.
coc 60
OJ
en
.~
is
.......
Cii 200
~
o
a...
----
I
~ 100
6
8
~
-~
V
---
14
12
10
Vee - Supply Voltage - V
~
....::J
a.
.::
40
.§
E:
20
:s-
J
1
\
\,
"- ,
\
16
O
,
/
I
I
"
';'
17.00
18.00
19.00
20.00
21.00
f - Oscillator Free Running Frequency - kHz
993
jlPC587C2,jlPC1026C
9. TYPICAL CHARACTERISTICS OF IlPC1026C (Ta = 25°C)
VOLTAGE GAIN vs. SUPPLY VOLTAGE
(Monaural) (,uPC1026C)
Fig. 41
Fig.40 CIRCUIT CURRENT vs.
SUPPLY VOLTAGE (,uPC1026C)
5
25
-.
4
Quiescent
-2
U
I
I
e
~ -3
5
-4
o
-5
8
12
10
14
Vee - Supply Voltage - V
6
6
16
3
C\l
co
CD
~
.c.
co 50
'0
f = 1 kHz
Vin(L+R)= 150mV
2
c
w
c
I
c
,g
(L-R)
~
0
C\l
Q.
-1
U)
ClJ
c
C\l
.c.
I
-3
u
40
f = 1 kHz
8
6
10
12
60
14
I
co
30
-
20
o
16
6
I 50
c
o
l. _
-- -- .... -- -- -- -Left
Right
40
12
14
16
Fig.45 FREE RUN FREQUENCY CHANGE vs.
SUPPLY VOLTAGE (pPC1026C)
N
I.
~-
10
8
Vee - Supply Voltage - V
Vee = 10V ~
f = 1 kHz f -
'0
--
+300
I
I
~
+200
c
C\l
.c.
c.;.
C\l
+100
(J
c
0.
ClJ
ClJ
\.
g
0
U: 19kHz )
U)
:J
30
c
&
U 20
I
-100
ClJ
~
ci.
~ 10
o
o
994
-
ci. 10
en
Fig.44 CHANNEL SEPARATION vs.
PILOT INPUT LEVEL (pPC1026C)
c
c
C\l
.c.
.... -
-
Vin(pilot) =15mV
Vee - Supply Voltage - V
w
Le!J
Right
ClJ
-5
'§
....
I
u -4
-6
\
~~,
w
c
u -2
CD
~
16
60
4
ClJ
12
14
10
Vee - Supply Voltage - V
Fig.43 CHANNEL SEPARATION vs.
SUPPLY VOLTAGE (pPC1026C)
Fig.42 CHANNEL BALANCE vs. SUPPLY
VOLTAGE (Monaural) (MPC1026C)
(J
8
u..
I
~
10
20
30
40
Vi(pilot) - Pilot Input Level - mV
50
-200
-300
6
14
12
10
Vee - Supply Voltage - V
8
16
,uPC587C2,,uPC1026C
Fig.47
Fig.46 CHANNEL SEPARATION vs.
FREQUENCY (JlPC1026C)
VOLTAGE GAIN vs.
FREQUENCY (Monaural) (JlPC1026C)
4
60
1
2
CO
"0
50
co
I
c
.g
co
roQ.
~
/
40
c
c
30
I
20
co
.r:::
U
c
-4
(!J
-6
'co
.........
Uin =
a dB1~0_;
=
i'.
'\
-1.5 dB
~
Cll
OJ
.s
-8
>
-10
o
Vee -10V
Uin (Pilot)
=15mV
ci.
o
-2
I
\
\
Cll
(f)
Cii
"0
vee~~
\
I
~ -12
-14
Cll
(f)
10
0.01
0.03
10
3
0.3
0.1
30
-16
0.01
0.03
0.1
f - Frequency - kHz
3
0.3
f- Frequency - kHz
(JlPC1026C)
(JlPC1026C)
10
10
7
I
3
/
~
V
c
.2
/
+"'
.S:
c
0.7
/
0.5
lI"
/
0
E
co
. . .V
0.3
I
/'
co
'0
l-
I
.....
//
q
0.07
r-: 0.05
0.01
3
-
~
I
c
0
'2
.~
0
.S:
c
0
I
E
co
0.7
0.5
0.3
co
'0
I-
I
q
I
r-:
I
Uin(L+R)=150mV
f = 1 kHz
5
'/
0.1
0.03
7
I
Vee = 10V
f = 1 kHz
5
0
30
Fig. 49 TOTAL HARMONIC DISTORTION
vs. SUPPLY VOLTAGE
Fig. 48 TOTAL HARMONIC DISTORTION
vs. INPUT SIGNAL LEVEL
.~
10
0.1
.....
V
I---
0.07
0.05
0.03
-
a
0.01
100 200 300 400 500 600 700 800 900 1000
Vi - Input Signal Level - mV
6
8
10
12
14
16
Vee - Supply Voltage - V
995
j.lPC587C2,j.lPC1026C
Fig. 50 TOTAL HARMONIC DISTORTION
VS. INPUT SIGNAL LEVEL (Stereo)
(,uPC 1026C)
Fig.51 TOTAL HARMONIC DISTORTION
vs. FREQUENCY (Stereo)
(,uPC1026C)
10
10
7
Vin (pilot) = 15mVf = 1kHz
5
1
II'>
III
:r:
/
0.3
I
1
.S!
c
0.7
0.5
E
0.3
o
,/
f-
V
0.1
I- 0.07
I 0.05
V
./
l-
~
3
~
. . .V
(5
ci
:i
10V
Vin (pilot) = 15mV
:r:
/
-/
ro
I
Vee
III
0.5
E
---
/
0.7
CJ
'c0
is
V
c
0
.;:;
(5
.g
B
y
'*
B
c
/
3
7
5
"""- r-~~
q 0.03
V
:r:
~
-/
0.1
I
0.01
10
30 50 100 300500 1k
0.07
3k 5k 10k 3Qk50kl00k
f - Frequency - Hz
0.05
0.03
0.01
o
10
20
30
40
50
60
70
80
90 100
Vi(pilot) - Input Signal Level - mV
Fig. 53 MAXIMUM INPUT LEVEL
vs. SUPPLY VOLTAGE
(,uPC1026C)
Fig. 52 TOTAL HARMONIC DISTORTION
VS. FREQUENCY (Monaural)
(,uPC1026C)
'*
c
10
1200
7
5
Vee - lOV
vin'iL+R)'=
~~~~
'f
3
(5
1
Qi
0.7
0.5
..J
~
'2
o
E
III
I
..... 800
::l
0.
0.3
J
ro
/
"""-
~
.::
E 600
::l
.~
0.1
I 0.07
.0.05
o
T.H.D.= 1%
>E 1000
>
CD
:r:
:i
I
! I
f = 1kHz (Monaural)
X
III
~
I
0.03
400
x
~
J
III
.s
0.01
10
3050 100
300500 1 k
3k 5k 10k 30k50kl00k
5
'/
/
V
/
200
I
f - Frequency - Hz
o
6
8
10
12
14
Vee - Supply Voltage - V
996
16
,uPC587C2,,uPC1026C
Fig. 54 SEPARATION vs. OSCILLATOR
FREE RUNNING FREQUENCY
(/1PC1026C)
60
Vee
Vin
50
en
"C
I
I
c: 40
o
"-
/
ero
~ 30
19.50
I
>
CJ
c:
Q)
:::J
rr
~
u.
\
.....
Cl
c:
'c
\..
/
1/
CJ)
~
= 10vI
(pilot) = 15mV
.If\
/
'';:;
Fig. 55 OSCILLATOR FREE RUNNING FREQUENCY
vs. AMBIENT TEMPERATURE
N
(J1PC1026C)
I
§
a:
"-
19.00
f.....-
OJ
~
U.
Qi
...
c:
c:
~ 20
--
...--
~~
~
B
~
U
'u
o
I
ci
~
I 18.50
10
~
o
25
75
50
°c
Ta - Ambient Temperature -
20.00
19.00
18.00
o
-25
.....0
fosc - Oscillator Free Running Frequency - kHz
Fig. 56 POWER DISSIPATION AND SATURATION
VOLTAGE OF LAMP DRIVER vs. LAMP
CURRENT. (J1PC1026C)
~
200
/
160
~
--
140
0-
E
ro
/
,I
120
-1
'0c:
100
'g
80
o
V
0-
.~
60
(5
-:;
40
Qj
~
~
I
20
~?
V
o
"C
a...
7'"
--
/
/
Pd
3
I
>
CJ
'': U
rr
~~
0>
0E
ro
-1
~-
a5 19.10
~
~
19.00
'cc:
-
~
u.
~
>
1
g
ro
a
100
80
CJ)
4
*-
3
~
ro
2
c:
= 10V
'g
o
I 18.70
CJ
18
E 16
I
Qi
...
a...
---
1-- ~
a:
-3
-4
-5
Vee = 10V
>
14
12
.2 10
I -2
U
20
-1
a.
B -1
~ f.--
-25
~
o
r--
I
8
.2
6
-;s
4
...
E:
~
~
2
25
50
Ta - Ambient Temperature _
75
°c
3
Fig. 59 LAMP TERN ON AND TURN OFF
SENSITIVITY vs. TEMPERATURE
(J1PC 1026C)
>
0
2
0
t - Elapsing Time - min.
Q)
Q)
--
1
I
Vee = 1OV • I L = 40mA
Vee = 16V. IL = loomA
B 18.80
I
-
I
I
"~
~
:§
a:
~
~~
18.90
I
Vin (pilot) = 15mV-
-
Vee = 7V.IL = OmA
~
Fig. 58 CAPTURE RANGE vs. AMBIENT
TEMPERATURE (J1PC1026C)
Vee
l
u.
"0
I L - Lamp Current - mA
5
I
:::J
2 ~
~
VCE(sat)
'';:;
60
40
I
:::J
ro
20
N
~ 19.20
...~
I 180
Qj
>
Fig. 57 OSCILLATOR FREE RUNNING
FREQUENCY vs. ELAPSING TIME
(J1PC 1026C)
0
-25
---
LAMP ON
J
~
~
-+-- ~
~
LAMP OFF
r--
o
25
50
Ta - Ambient Temperature _
75
°c
997
,uPC587C2,,uPC1026C
Fig.61 CAPTURE RANGE
(IlPC1026C)
Fig. 60 POWER DISSIPATION vs.
SUPPLY VOLTAGE (pPC1026C)
500
!f:
E
100
V~e = 10V
UXMP.OFF
400
80
I
c:
>
E
0
.;:;
co 300
c.
.v;
I
a;
CI)
0
.... 200
Cll
~
0
0-
I
"
0-
....-
100
o
---
.......-
8
6
------
10
..--
.-'
V
~
60
>
Cll
-I
.....
.2 40
a:
I
\
c.
S 20
12
14
0
16
Vee - Supply Voltage - V
17.00
\,
18.00
J
V
"
' . ""
19.00
20.00
21.00
fosc - Oscillator Free Running Frequency - kHz
Fig.62 Typical Application of the IlPC587C2
Vee = 10V
Vee
FM-FRONT ~~~~~__~__~____~~____+-~50~!~1____~r-________~
ENO
50n
12kn
FM-FRONT END
(1) CMU-AT01
(Mitsumi Ltd.)
121
R-eh OUT
~;~;d~t:~::gNTf150n!~~
PG = 30dB
C")
"1
C")
SFE10.7MA
SFE10.7MA
IF1: 2SC1675
IF2: ~PC1028H
Fig.63 Typical Application of the IlPC1026C
FM-FRONT
END
MPX:
~PC587C2
Vee = 10V
F: B3EN0102
Vee
50n
~~N-~~--------~~r---------------~~~--~~--~-'~------~~
12kn
FM·FRONT END
(1) CMU.AT001
(Mitsumi Ltd.l
PG = 33dB SFE10.7MA
l~:t::~~t~')f50nl~~
g
L-ch OUT
~
PG = 30dB
C")
IF1: 2SC1675
998
MPX:
~PC1026C
F: B3EN0102
jlPC587C2,jlPC1026C
Fig. 64 MPX OUTPUT VOLTAGE vs. ANTENNA INPUT LEVEL
Vout (Signal)
0
I
Vee = 10V
f = 98MHz
fmod = 400Hz
M = 75kHz DEV.
m=30%
I
-10
I
I
co
"0
I
,-r\
Ol
en
!:l
I
"0
I
I
>....
I
:J
9:J
I
I
\
\
I
I
0
X
a..
(FM)
(AM)
FM-FRONT-END
FM-IF1
IF2
[
MPX
\
\
\
\
FX-A53
2SC1675
pPC577H
pPC1026C
\
~
I
\.
-40
....
\
:J
\
0
>
\
\
,-..
\
I
\
-50
\
.,/ ...... x. . ..;I
~_..lC-~-x,
I''Ie,
'v,
I
\
'x....
~,AM
R .~
"'1c_ _ _ .-'I
""r-.
-~
I
-2
I
-10
-12
-14
50
\
100 200 300 500
1k
2k 3 k 5k
10k 20 k 30 k 50 k 100 k
300 k
f-F requency-Hz
Fig. 11 Frequency Characteristic of LPF
3.3 HPF
As with the LPF, the HPF consists of an active filter. The HPF detects the differentiated noise in the input
signal and sends it to the waveform shaping circuit. Fig. 13 shows the frequency characteristic of the HPF at the
constants shown in Fig. 12 and the cut-off frequency fL of 100 kHz.
Vcc
>---{14
I
I
L5 pF C6
:
-IJPC1176C- _...J
390 k RS
Fig. 12 HPF Circuit
1006
,uPC1176C
VCC=10 V
Vin=500 mV
540 mV=O dB
lpil, .... 14pin
-
+2 f++ttt_----1r--t~H+Ht_---1r-_t_HI_++Ht_-t-__+-T""TTl
CD
,--r-r-
j~
-2 f+t-++t--II-+-t--1H+t+t--If-f-t--1H+t-Hl--l-+-+-+-t--H+t----
~
-4 H+ttt_~r--t-+-H+Ht_---1r--t_HH+H+--j-+-+-+-+-H+I--___+- I -
o
~H+ttt_---1f---t-HH+m----1-+-~,H+~-j~--+-+~+I--___+_+~
1>
';
';:
500~s
./
80
/~
'en
c:
Pin 10 for monitor; Input
pulse peak value at wh ich
Q)
U)
~
60
Cl
Cl
~
I
f-
40
>
~
V
E
I
~
BLJL
/
/
V
./
t he gate ci rcu i t sta rts to
operate,
20
0
2
3
4
5
6
7
8
R 13-External Resistance of Pin 13-kn
Fig. 15 Trigger Sensitivity vs. Resistance R 13
3.5 Continuous Noise Control Circuit
On entrance of noise, the monostable multivibrator operates and issues a control signal to open the gate, and
a current proportional to this control signal flows to pin 10. If the noise is repeated at very short intervals (30 ,us),
the original signals are not allowed to come out. In order to avoid such inconvenience, this circuit is provided,
which decreases the trigger sensitivity and closes the gate compulsorily so that the signals are passed as they are.
The detecting element of this circuit is illustrated in Fig. 16.
The higher becomes the frequency of
repetition of noise, the more is charged capacitor C12 at pin 12. Thus, the potential of pin 12 decreases,
making Tr04 conductive and permitting a control signal to decrease the trigger sensitivity to be generated.
,..---+--..------...---0 V CC
I Current proportional
t to control signal
Fig. 16 Peripheral Circuit of Continuous Noise Control Circuit
3.6 Monostable, Multivibrator
The monostable multivibrator is actuated by noise which has been detected by HPF and subjected to waveform shaping. On actuation, the monostable multiviurator sends a control pulse to the gate circuit to open
the gate and Gut off the original signals.
The time in which the gate is open is called blanking time, ~nd its length is determined by the time
constant circuit, i.e., C13 and R16 connected to pin 11.
Fig. 17 shows the blanking time vs. the capacitance C13,
1008
J,lPC1176C
60
50
~
I
Output
(to MPX)
resistance
/t ~ I
Coupling capacitor
tL
c.
C15
L.P.F.
Storage capacitor
g
Stereo signal holding circuit
Fig. 19 Peripheral Circuits
3.9 Effect of Noise Canceller
The effect of J-LPC1176C on noise suppression was evaluated using a spectrum analyzer connected to the
network as shown in Fig. 20.
Signal generator
f=1 kHz
Vin=250 mV
Sine wave
J..IPC1176C
J..IPC2002
Noise canceller
Po Amp
Po
O.5W
Artificial noise
Spectrum
Vin2.5 Vp-p
Tw=1 J..IS
Repetition 15 J..IS
analyzer
Fig. 20 Block Diagram of Network for Evaluating Noise Suppression by J-LPC1176C
The result of the evaluation is shown in Fig.21. This is merely one example, and different results will be
obtained depending on the timing of noise.
1010
,uPC1176C
Photo 1
without artificial pulse;
waveform of power
amplifier alone.
Photo 2
with artificial pulse;
without noise canceller
Photo 3
with artificial pulse;
with noise canceller on
SCAN-WIDTH
10 kHz/DIV
BAND-WIDTH
1 kHz
SCAN TIME 0.2 s/DIV
Fig. 21
Effect of Jl PC1176C on Noise Suppression
1011
JlPC1176C
4. ABSOLUTE MAXIMUM RATING OF J.LPC1176C (Ta=25°C)
Supply Voltage
VCC
Package Dissipation
PD
Operating Temperature
Storage Temperature
15
V
350*
mW
Topt
-20 to +75
°c
Tstg
-40 to +125
°C
*Ta=75°C
5. ELECTRICAL CHARACTERISTICS OF J.LPC1176C (Ta=25
CHARACTERISTIC
TEST CONDITIONS
SYMBOL
MIN.
TYP.
MAX.
UNIT
Circuit Current
ICC
13
16.5
23
mA
Vi=O
Voltage Gain
Av
-0.3
0.7
1.7
dB
Vi=500 mVr.m.s., f=1 kHz
Blanking Time
TB
30
J.Ls
Vi=500 mVp,f=1 kHz, tw=1 J.Ls
Triggering Voltage
VT
40
mVp
f=1 kHz, tw=10 J.Ls
6. PACKAGE DIMENSIONS (in millimeters)
19.4 MAX.
R1
-----+]
O.5±O.1
Unless otherwise specified, typical values are given.
1012
°c, VCC=10 V)
,uPC1176C
7. PRINTED-CIRCUIT BOARD
Example of component mounting (bottom view)
f-
~
a..
Z
~
U~ zoz,
..,
j
u
u
>
f-
~
a..
f-
~
o
1013
,uPC1176C
8. PRECAUTIONS FOR USE OF IlPC1176C
8.1 FM IF Stage and Detector Stage
As mentioned in Section 3.3, noise is detected by HPF, whose cut-off frequency is set at 100 kHz. Thus,
it follows that noise components of higher frequencies than this are detected. Therefore, the FM I F stage should
have a bandwidth (200 k to 300 kHz) broad enough to pass not only signal components (50 Hz to 53 kHz)
but also noise components.
Noise (white noise) in the I F stage may cause malfunction in the noise canceller and deteriorate the SIN
ratio. Due consideration should be made with respect to the noise characteristics of the I F stage including the
front end. The noise canceller will be more effective when used in combination with NEC's IF IC Il PC1200V
or IlPC1245V which exhibits a good SIN in weak electric fields.
Noise in the I F stage ma·y be suppressed to some extent by connecting a high-cut filter (500 kHz) to
pin 1.
When establishing the trigger sensitivity with resistance R 13 connected to pin 13, as mentioned in Section
3.4, it is necessary that the front eqd, I F stage, and detector stage be connected.
Vee
High-cut filter
IN
O---r-~~-'-+--~--~--~.
Fig. 22 High-cut Filter to Suppress IF Stage Noise
8.2 Blanking Time
The blanking time TS is established by capacitor C13 connected to pin 11, as mentioned in Section 3.5.
Too short a blanking time decreases the cancelling effect due to a partial leakage of noise; and too long a blanking
time distorts the original signals and deteriorates the distortion. See Fig. 23. An adequate blanking time is 20
to 40 lIs.
Input
I
I
I
I
I
I
I
I
I
I
I
I I
I I
I
I
II
II
I I
I I
I I
I I
:
ill
V~
I
Output
I
I
I
I
I
!J1\
V::V
I
I
II
• I, ,
• I
I
II
I
I
I.
I
TS
TS
Leak of noise due to too short 1"S
Adequate TS
Fig. 23 Noise Pulse vs. Blanking Time
1014
II
I I
I I
v4b
I
-I
I
I"
'TSI
Distortion due to too long TS
,uPC1176C
8.3 Stereo Signal Holding Circuit
(1) Holding of 19 kHz pilot signal
The pilot signal contained in stereophonic broadcasting will vary suddenly in its level, as shown in Fig. 7,
when the gate is opened due to the presence of noise. This is the cause of parasitic noise. The 19 kHz holding
circuit prevents the occurrence of this discontinuity and parasitic noise. The effect of this circuit will be more
pronounced when the pilot signal alone is received or in the case where Land R signals are modulated to a
lesser extent.
(2) Holding of 38 kHz subcarrier
In stereophonic broadcasting, not only the 19 kHz pilot signal but also the (L-R) subcarrier modulated by
38 kHz DSB (Double Side Band) are superposed on the original signal. Unless this signal is held when the gate is
opened, the waveform is distorted after stereophonic demodulation. This effect is apparent when a signal of
(L-R) sub, L only, or R only is received.
(L+R)
(L-R) sin wt
75 90 %
!r--,r---,
--"I
60
N
I
90 %
I 'v; I
II
I
1 ..... 1
II
I
,~20
I~ I
II
I
I c.. I
II
I
I 10 r----'"1 r--t
I %I
II
I
c3
:I
40
.:,t.
c
,Q
I
50 H l!: 1 5 19 23
I:
:
38
53
Modulation frequency (kHz)
Fig. 24 Frequency Spectrum of Stereophonic Broadcasting
For the best operation of the noise canceller in the reception of stereophonic broadcasting. both 19 kHz
pilot signal and 38 kHz subcarrier should be held simultaneously. In actual, however, either of them should be
selected for the construction of llPC1176C circuit.
The holding circuit for 38 kHz subcarrier is recommended.
Fig. 25 shows three circuit examples with
19 kHz or 38 kHz holding circuit and without holding circuit.
(1) With 19 kHz holding circuit
OUT
R18
(3) Without holding circuit
(2) With 38 kHz holding circuit
OUT
R
1.5 k
R18
1.5 k
C14
C14 6800 pF
3900 pF
C16 2200 pF
1
C14
p
3900 pF
6800
R20
2k
Fig. 25 Use of Holding Circuit
1015
j.lPC1176C
8.4 Adjustment of Stereo Signal Holding Circuit
The holding circuit for either 19 kHz or 38 kHz should be adjusted by VR1 connected to pin 7 until the
waveform becomes flat while watching the waveform on the oscilloscope arranged in the circuit as shown in Fig.
26.
38 kHz (or 19 kHz)
signal generator
Oscilloscope
pPC1176C
Sy nch ron iz i ng
trigger
Pulse generator
1.5 kn
1 kn
Tw=1 ps
Vi=200 mV
_____"n
pulse
T\T\fil\l\T\
./\!filllTi/\
J\/\/'\iVVi
(1) In optimum adjustment;
loop gain = 1
(2) Out of adjustment;
loop gain >1
(3) Out of adjustment;
loop gain <1
Fig. 26 Adjustment of Stereo Signal Holding Circuit
1016
jlPC1176C
8.5 Connection with MPX
On processing by the noise canceller, the signal passes through the LPF (delay circuit) and the phase in the
high frequency band rotates. In such case, separation becomes poor after stereo demodulation by the next MPX
stage. This may be remedied by compensating the high frequency output of the noise canceller. See Fig. 27.
noise canceller
~-~r:i~-"'O"'--:__
M_P_X_ _..I
J,LPC1176C
Fig. 27 High Frequency Compensation for Separation Adjustment
If NEC's MPX IC JlPC1320C, JlPCl187V or JlPC1227V is used, good separation is obtained without
compensation as shown in Fig. 27, because they are provided with a separation adjusting terminal for compensation.
9. BASIC CHARACTERISTICS OF JlPC1176C
Vcc-10 V
*-I
5
1pinlnput~
3
f=1 kHz
I
2
~
c:
0
.;:;
.~
0
,
I
I
0.5
f
u
'2
0
§
I
ro
ro
0
V
0.3
0.2
~f
I
0.1
,
l-
I
0
:C
~
J
'"
0.05
"
0.03
..
-
,
/
0.02
0.01
0.01
0.02 0.030.05
0.1
0.2 0.3 0.5
2
3
5
Vin-Input Voltage-Vr.m.s.
Fig. 28 Total Harmonic Distortion vs. Input Voltage
1017
JLPC1176C
Vee
10
V
5
1pinlnput~
3
f=100 Hz
I
I
2
*
I
c:
J
0
'';::;
.~
0
.~
7
7
0.5
c:
0.3
§
0.2
7
I
V
0
~~
co
I
";§
/
0.1
0
~
0:I
r=
'0.05
.....
./
"
0.03
1--_
~
~
0.02
0.01
0.01
0.020.03 0.05
0.1
0.2 0.3
2
0.5
3
5
Vin-I nput Voltage-Vr.m.s.
Fig. 29 Total Harmonic Distortion vs. Input Voltage
Vee
10
V
5
1Pinlnput~
3
f=10 kHz
I
2
I
*c:I
0
'';::;
.
~
0
0.5
.~
0.3
c:
I
I
••
1
0
§
0.2
co
0.1
I
co
~
0
I
0.05
r:
0.03
c:i
:i
-'
"' '-.
l-
~~
~
roo.
~
0.02
0.01
0.01
0.02 0.03 0.05
0.1
0.2 0.3 0.5
2
3
Vin-Input Voltage-Vr.m.s.
Fig. 30 Total Harmonic Distortion vs. Input Voltage
1018
5
.uPC1176C
VCC=10 V
5
1pinlnput ~
3
~
2
I
a
.;:;
c
.~
0
u
0.5
'ca
0.3
Ctl
0.2
E
I
Vin=500 mV
Ctl
(3
l-
~
-I-...
0.1
I
0
I
r-=
I"
0.05
-,
0.03
~
"'"
0.02
,
100mV
r"t-i'
0.01
20 30
50
100
200 300 500
1k
2k 3 k
5k
10k
20 k 30 k 50 k
f-Frequency-Hz
Fig. 31 Total Harmonic Distortion vs. Frequency
I
VCC=10 V
1.4
1pin Input
~
2.5
T.H.D.
1.2
6pin Output
I
f=l kHz
II
~/
~
I
c
en
.~
:>I
a
.;:;
0
.~
C
0.8
1.5
>
/
+-'
Ctl
0.6
::J
0.
a
0
I
l-
I
0.4
I
r:
/
7
.JV
I::l
a
>
V
V
0.5
0.2
0
/
/V
S
Ctl
7/
VOUT /
OJ
OJ
~
a
E
q
)
E
a
I
2
V
V
V
o
V
V
'/
/
I
I
/
~
o
0.5
1.5
2
2.5
Vin-Input Voltage-Vr.m.s.
Fig. 32 Total Harmonic Distortion, Output Voltage vs. Input Voltage
1019
j.lPC1176C
~
20
18
«
E
.!.c
~
16
./
14
~
U
I
u
~
No Signal
)~
12
#I'
10
... V
/'"
:::l
u
....
:::l
/"
/'
...V
./
#I'
'"
8
6
6
8
10
12
14
16
vee-Supply Voltage-V
Fig. 33 Circuit Current vs. Supply Voltage
1pin Input
+4
f=1 kHz
A
/\
'\.T'
500 mVr.mos.
+2
co
l'c
0
~,
,
---
°co
(!)
OJ
Cl
-2
~
0
>I
>
-4
«
-6
-8
-10
6
8
10
12
vee-Supply Voltage-V
Fig. 34 Voltage Gain vs. Supply Voltage
1020
14
16
~PC1176C
1.6
lpin Input
1.4
~
A. A.
~cr'
1=1 kHz
1.2
I
c
0
.'::;
.~
1\
1.0
\
0
.S!
c
0
I
E
co
co
0.8
0.6
0
l-
I
ci
.
\
""
"
.....:
"
0.2
\
", 1\
0.4
I
"\
.\
Vin=500 mV
"-
100'~
"mV
mV
......
"
',I
6
---
I
8
~ .....
-- .......
10
12
14
16
vee-Supply Voltage-V
Fig. 35 Total Harmonic Distortion vs. Supply Voltage
lpinlnput
70
10pin Monitor
~
Vp-p
-t:'", J
60
~
I
'--ItITs I.
500l-ls
50
Cll
E
i=
en
c
40
.:,£
c
~
en
I
en
/..30
I-
20
I
"
/
10
6
8.
10
12
14
16
vee-Supply Voltage-V
Fig. 36 Blanking Time vs. Supply Voltage
1021
,uPC1176C
1pin Input
70
~
~,",~
,
en
60
E
~
E
\
40
en
~
'Cl
Cl
start to operate
o
\
c(lJ
(lJ
Input pu Ise height at
which the gate circuit
50
C
°Vi
mVp-p
500~s
I
0>
0';:::;
1Opin Monitor
30
~
----
I
f-
>
20
10
6
10
8
14
12
16
vee-Supply Voltage-V
Fig. 37 Trigger Sensitivity vs. Supply Voltage
VCC=10 V
1pin Input
60
50
~
/
--'
co
l'c
,.-
~
40
--
--\ "-
::J
C
30
I
....
20
Jlill
t'''J
500",s
~
co
~
.
e pulse
~
02
....
2
~
~
With 38 kHz
holding circuit
EB pulse
~~
10
2
3
4
5
6
7
Vp-Input Pulse Level-Vp-p
Fig. 38 Attenuation vs. Input Pulse Level
1022
8
J.lPC1176C
Vcc-10 V
1pin Input
L
~
50
500/-ls
40
~
I
~
(l)
.s
I-
30
c
~
/
c
~
_........
-hsl-
OJ
CO
V ....
10pin Monitor
/
/
V'
20
I
II
CO
I-
V
10
/
2 3
5
10
20 30
50
100
200 300 500 1000 2000 3000 5000
Vp-Input Pulse Level-mVp-p
Fig. 39 Blanking Time vs. Input Pulse Level
10. EPI LOGUE
Although there is no established method for evaluating the noise canceller, an example is shown in Fig. 40.
Actual test on an automobile is also considered to be important.
Two-signal dummy t - - - - - i
antenna
Set under test
Noise generator
Fig. 40 Block Diagram for Evaluating System
1023
EXPLANATION AND TYPICAL APPLICATIONS OF
THE j.lPC1235C, AN FM MPX IC
FOR HIGH CLASS STEREO TUNER
1. EXPLANATION OF THE IlPC1235C
1-1. Outline
The ~PC1235C is a semiconductor integrated circuit for FM multiplex demodulator developed for high class
stereo FM tuners. As the Ie adopts a PLL (phase locked loop) system, complexity of control usually experienced
when using conventional external coil is eliminated and the demodulator can easily be constructed by simply
controlling the external semi-fixed potentiometer.
Internal circuits are composed of a stereo demodulator, a lamp driver, an input stage pre-amplifier that is capable
of establishing variable input signal levels, a VCO (voltage controlled oscillator) constituting PLL, a phase comparator, an LPF (low pass filter), a frequency divider, and a DC amplifier.
A stereo-monaural automatic switching circuit, a circuit for manual switching, VCO forced stop circuit etc.
are built-in.
1-2. Features and Use
Features
(1) PLL system can reduce the number of external components and controlling procedures.
(2) Stereo-monaural switching can be made either automatically or manually from outside. The shock noise at
switching is reduced considerably.
(3-) Stereo-monaural switching operation is perfectly synchronized with a stereo indicator lamp.
(4) Total harmonic distortion is largely improved by the adoption of new circuits. Low distortion can give a
wide input level.
(5) Fine adjustment of channel separation can be made with an external semi-fixed potentiometer. Channel
separation characteristic from low to high pass is improved notably.
(6) Hight signal-to-noise ratio.
Use
FM multiplex demodulator of high class stereo.
2. CHARACTERISTICS OF THE
~PC1235C
2-1. Maximum Ratings of the ~PC1235C
Table 1 Absolute Maximum Ratings (Ta = 25°C)
ITEM
SYMBOL
RATING
UNIT
Supply Voltage
VCC
15
V
Lamp Current
IL
75
mA
400*
mW
Package Dissipation
Po
Operating Temperature
Topt
-20 to +70
Storage Temperature
Tstg
-40 to +125
°c
°c
2-2. Recommended Operating Condition of the ~PC1235C
Table 2 Recommended Operating Condition
CHARACTERISTIC
Supply Voltage
1024
SYMBOL
MIN.
TYP.
MAX.
UNIT
VCC
9
12
15
V
,uPC1235C
2-3. Electrical Characteristics of the J,.LPC1235C
Table 3 Electrical Characteristics (Ta
[VCC
= 12
V, f
= 1 kHz,
R1
CHARACTER ISTIC
Supply Current
Channel Separation
= 47
= 25°C)
kil, R + L
SYMBOL
ICC
Sep.
Voltage Gain
AV
Channel Balance
C.B.
= 270
mY, Pilot
TYP.
MAX.
UNIT
12
20
30
mA
40
50
dB
45
55
dB
35
45
dB
8
12
16
dB
Monaural, *Vin
-1.5
0
1.5
dB
Monaural, Yin
-1.5
0
1.5
dB
Stereo, Pilot
0.01
0.08
%
Yin
T.H.D.
0.02
T.H.D.
.Harmonic Distortion
0.1
0.12
Pilot Level for Lamp On
L-ON
Stereo Lamp Hysteresis
Hy.
Capture Range
C.R.
Ultrasonic Frequency
6
12
TEST CONDITION
No.Signal
= 100 Hz
f = 1 kHz
f = 10 kHz
f
Pilot
= 30 mV
= 300 mV
= 300 mV
= 30 mV
= 300 mV
%
%
20
= 100 Hz
f = 1 kHz
f = 10 kHz
f
%
0.02
Stereo Total
mY]
MIN.
Monaural Total
Harmonic Distortion
= 30
= 270 mV
Pilot = 30 mV
R+ L
mVr.m.s. Pilot Level, R 1 = 47 kil
dB
Pilot Level
±3
%
19 kHz. Rej.
35
dB
38 kHz. Rej.
45
dB
SCA Rejection
SCA Rej.
70
dB
Maximum I nput Level
Yin
0.9
Signal to Noise Ratio
SIN
= 30 mV
Pilot = 30 mV
Pilot = 30 mV
Pilot = 30 mY, SCA = 30 mV
Monaural, T.H.D. = 1 %
Yin = 300 mY, After LPF
Rejection
6
±1.5
81
Stereo-Monaural Switching
SW-ON Voltage
VCO Stop Voltage
Vo
89
1.4
Vs
7
Vr.m.s.
dB
1.6
VCC
Pilot
No. 16 Terminal Voltage
V
V
Where Stereo Lamp-OFF
No. 16 Terminal Voltage
Where VCO Stops
* AV is from the output level measured at IC output terminal. AV can be set by R 1, and the input impedance.
1025
j.lPC1235C
2-4. Test Circuit of the J,lPC1235C
19kHz Monitor
Lamp Protecting
Resistor
MPX Input C2
47kn.
C3
C5
R5
r500PF
22kn.
10kn.
1000pF
R3
ICC
100~F
+
C,- -
Rch-OUT
lO~F
LPF
Sep. Adj.
500kn. VR
lO~F
C6
Rg
+ -
1000pF
3.3kn.
C14
22kn.
10kn.
3.3kn.
C13
+ -
R4
lO~F
For Measuring
R7
Lch-OUT
R2
lO~F
LPF
veo Adj.
Sep Adj.
S1
S2
S3
BL-13 (K.K KORIN)
tuning semi-fixed potentiometer
Separation adjusting semi-fixed potentiometer
veo
Vee
ON-OFF SW
SW for 19 kHz monitor
VCO stop SW
Fig. 1 Test Circuit for Electrical Characteristics (Top View)
NOTES:
1. Use polystyrene capacitors for that connected to No. 15 terminal to compensate' the temperature coef. of
veo.
veo
2. For adjusting the
oscillation frequency, make S2 open, connect the frequency counter to No.9
terminal 19 kHz monitor and then set by varying the semi-fixed potentiometer
Adj. connected to
No. 15 terminal.
3. For separation adjustment, vary the semi-fixed potentiometer Sep. Adj. connected between terminals
No.4 and No.5 to set at the best point.
1026
veo
,uPC1235C
2-S.Package Dimensions of the J.LPC123SC
NOTE: Numerical values show TYP. values unless otherwise designated.
..
N
X1P
"
::;
'"
on
.. ..,"!
i
,
•
~
M
O.~O.l
Fig.2 Package Dimensions of the J.LPC123SC (Unit: mm)
3. FUNCTIONAL BLOCK DIAGRAM OF THE J.LPC1235C
3-1. Functional Block Diagram of the J.LPC1235C
...........-+-~STEREO
SWITCH
t----+-~LAMP DRIVER
ST-MONOSW
veo STOP
sw
Fig.3 Functional Block Diagram of the J.LPC1235C
3-2. Terminal Connection
Table 4 Terminal Connection
No.
Connection
No.
Connection
ST. LAMP & 19kHz MONITOR
1
VCC
2
PRE AMP INPUT
10
SWITCH FI L TER
3
PRE AMP OUTPUT
11
SWITCH FI LTER
4
POST AMP BIAS
12
DETECTOR INPUT
5
POST AM P BIAS
13
LOOP FILTER
6
R-CH OUTPUT
14
LOOP FI LTER
7
L-CH OUTPUT
15
OSC RC. NETWORK
8
GND
16
ST.-MONO SW & VCO STOP
9
1027
,uPC1235C
3-3. Typical Voltage of Each Terminal
Table 5 Typical Voltage of Each Terminal (VCC = 12 V, Test circuit)
J,lPC1235C
1
2
3
4
5
6
7
8
12 V
2.3 V
5.5 V
9.9 V
9.9 V
5.2 V
5.2 V
0
9
10
11
12
13
14
15
16
2.3 V
2.3 V
2.3 V
2.3 V
2.3 V
3.3 V
0
-
J,lPC1235C
3-4. Equivalent Circuit of the J,lPC1235C
2
3
1213
14
15
~"~ ~
Jr- "" "~"'~.
~[J
I:, ~
". "..
t'IMooirr-t-t--'T'L"" Om
0,.
".
0 66
R96
0 67
Reo
5
6
4
7
Re2
10
9
11
16
8
Fig. 4 Equivalent Circuit of the J,lPC1235C
INPUT
3-5. Explanation of the Equivalent Circuit
(1) Input amplifier and bias supply circuit.
Bias supply circuit and equivalent circuit of the input
amplifier are shown in Fig. 5. Regulated voltage Vs is
expressed by
and constitutes a constant voltage circuit with a diode 01,
transistors 01, 02 and a resistor R 1. ,Therefore, Vs is
constant to variation of the power supply voltage. The input
amplifier is made up of a preamplifier' consisting of
transistors 03 to 09, resistors R2 to Ra and a capacitor C1
Demodulator Demodulator
and an NF amplifier consisting of transistors 011 to 016
High
Low
and resistors R 11 to R 15.
Fig. 5 Bias Supply Circuit and Input Amplifier
1028
J,lPC1235C
04 and 05 are differential amplifiers and perform low current operation making the multicollector transistor
03, a current mirror circuit, active load and obtain a high circuit gain.
The output of the pre-amplifier is supplied to the base of 015, i.e. the input of NF amplifier, through
Darlington-connected 08, 09 and feedback from the emitter of 013 by R3.
Improvement of distortion is effected by the NF amplifier and betterment of channel separation is devised
by eliminating crosstalk component through the feedback resistor inserted in the emitters of 015, 016.
Gain of the input amplifier is determined by a feedback resistor R3 and an input resistor Ri out fitted to
No.3 terminal and expressed by following equation:
-'- R3
A 1 ~Ri
C1 is a capacitor inserted to stop oscillation and R 11, R 12 are ,resistor inserted for offset voltage
compensation. Of the composite signal input from No.2 terminal only the pilot signal is passed through LPF
out fitted to No.3 terminal and lead to the phase detector of PL L circuit. Further, the main signal and
subsignal of the composite signal are lead to the demodulator through the emitter-follower of transistor 10.
(2) Demodulator
Fig. 6 shows configuration of the double balance type demodulator. Transistors 060 to 063 are Jhose which
perform switching by 38 kHz which is a subcarrier injected from the frequency divider. The composite signal
is input from the bases of 064, 065 and divided into L, R-Ch signals. The resistors R76, R77, R78 inserted
in the emitters of 064, 065 are, similar to NF amplifier, inserted as feedback resistor to eliminate crosstalk
component. The switching signal, i.e. a subcarrier of 38 kHz, is 38 kHz that is 50 % of duty cycle obtained
°
by injecting the oscillation frequency, 76 kHz, of VCO into one stage bistable multivibrator (flip flop).
High
Low
R Signal - + - - .
38 kHz 38 kHz
n
L
U
Signal-~-+-+-~
5
6R
Post Amp OUTPUT
Bias
4 P~;t 7-L------Amp
Bias
OUTPUT
Vee O--'V\I'v-~"I"Ir'
Rf
Rb
Fig.6 Demodulator
Fig.7 Output Stage Post Amplifier
(3) Output stage post amplifier
The structure of the output stage post ampl ifier is shown in Fig. 7.
The L, R signals separated by the demodulator are injected respectively into the bases of 055, 090 of the
differential amplifier composed of transistors 054, 055 and 089, 090.
Further, bias is given to the base voltage of 054, 089 to the same voltage (when no signal) as the base
voltage of 055, 090 by external components through No.5, NO.4 terminals. The transistor 053 is a
1029
,uPC1235C
transistor of multicollector and constant current circuit of the differential amplifier, and the transistors
058, 059 and 093, 094 are active load.
The L, R signals amplified by the differential amplifier are output from No.6 (R signal), NO.7 (L signal)
terminal respectively through the emitter-follower of transistors 056, 091 and feedback to No.5, NO.4
terminals by external resistors R6, R8.
Accordingly, gain of the output stage post amplifier can be expressed equivalently from external resistor
ratio by following equation:
A2
. Ra//Rb + Rf
Ra//Rb
~.
(4) Phase detector and DC amplifier
DET-IN
12
LPF LPF
1314
P
E
Vs~------~~--~~-----
-7\ I
a\]
:q~
D
f\f\
V~
(f) Input Signal (Pilot Signal)
(a) Input Signal (Pilot Signal)
D
:q-n--n [
(b) 020 Base Signal (19 .kHz Signal)
(g) 020 Base Signal (19 kHz Signal)
(c) 021 Base Signal (19 kHz Signal)
(h) 021 Base Signal (19 kHz Signal)
011
7
11
[)
n
c
I
(j) 024 Base Signal (Output Signal)
(d) 024 Base Signal (Output Signal)
o_[\~~l'
\j
(e) 025 Base Signal (Output Signal)
Fig.8 Phase Detector
and DC Amplifier
Fig. 9 Phase Detector
Input Output Waveform
\J '\
(j) 025 Base Signal (Output Signal)
Fig. 10 Phase Detector
Input Output Waveform
Fig. 8 shows structure of the phase detector and DC amplifier. The phase detector is composed of transistors
020, 021. The 19 kHz pilot signal amplified by the input amplifier is input from No.3 terminal to No. 12
terminal through LPF being an input signal of the phase detector. The input signal (19 kHz pilot signal) is
compared with the phase of 19 kHz that is the oscillation frequency of VCO, 76 kHz, divided into 1/4, and
an output voltage corresponding to the phase difference is generated. When the phase difference between
the two signals is 90°, the output voltage becomes zero in DC (Fig. 9).
Fig. 10 shows the waveform when 19 kHz signal advances. That is, (j) becomes high level in DC and (j)
becomes low level and becomes input of the differential amplifier that constitutes the DC amplifier.
However, the output waveform is a waveform when LPF out fitted to No. 13, No. 14 terminals are removed.
When LPF is passed through, the above can be expressed by following equations:
Here, if the output voltage of the phase detector is assumed to be eo(t), all but fundamental wave are
attenuated by LPF, hence the following equation:
1030
,uPC1235C
Accordingly, an output voltage proportional to cosine of the phase difference of the two signals is generated
and when the phase difference is 90°, above equation becomes zero and the oscillation frequency of the veo
is taken to have locked to the input signal.
(5)
veo
veo
(Voltage Controlled Oscillator) is shown in Fig. 11.
VCO determines high level and low level dividing the reference voltage Vs by resistor, actuates the
comparator (astable multivibrator) making the level the reference voltage and produces blocking oscillation
by charging and discharging the capacitor out fitted to No. 15 terminal.
Now, if transistor 030 is in ON-state, transistors 032, 033 will come to ON state, and the reference-voltage
of the comparator which is the base voltage of 030 becomes a high level.
This relation is expressed by following equation:
Then, current flows from another emitter of 033 and the current charges the external capacitor e to high
level through the resistor R32When charging is completed, transistor 029 becomes ON state and discharged by external resistor R_
Then, since 030 is in OFF state, 032, 033 become OFF state and the reference voltage of the comparator
becomes low level voltage given by the following equation:
The state is manifested in waveform in Fig. 12.
In the figure, t1' t2 represent time required for charging and discharging respectively and given by following
equations:
t1
= R32 . e·
In
VS-VL
VS-VH
---"«---'=-
t2 = R . C' In VH
VL
c
NO'15ter~:a'~i~i
waveform
V
I
I
I
n
I
OL;
VHnt
I
Q30
base
wdveform
VL
Fig. 12
Fig. 11
(:
t2
I
:
~----
veo Waveform
veo
1031
,uPC1235C
(6) Divider
LnJL
040 Collector
VS----H---~----;---~------~--~----~
R38
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I I~r I~I
041 Collector
~I
I
I
I
I
'III:
JUl
04'7 Co Ilector
~
I
I
I
I
:
I
I
I
I
J
.n..
LI .n..
19 kHz
1...[.rt
Lf
I
I
I
I
I
I
I
I
I
I
I
I
I
I: I
1 :::
I! L
I
38 kHz
:
I
I
I
052 Co lIector
:
I
048 Co Ilector :
051 Collector
I
' ':
T1-0T
:
76 kHz
I
i
I
19 kHz
Fig. 14 Divider Output Waveform
Fig. 13 Divider
Fig, 13 shows the frequency divider.
These are bistable multivibrator (flip flop), and composed of a frequency divider that produces from 76
kHz, oscillation frequency of vea, switching signal 38 kHz of duty cycle 50 % required for stereo demodulation, and a frequency divider that produces 19 kHz injected into the phase detector from 38 kHz to control the veo, and a frequency divider that produces 19 kHz required for driving the stereo indicator lamp
synchronized with the pilot signal as well as for controlling the stereo switch.
Fig. 14 gives phase relation of the above.
The collector waveform of transistor 048 and that of transistor 052 appear at a 90° phase shift. Therefore,
the collector waveforms of °51,° 52 are synchronized with the pilot signal.
(7) Lamp driver and stereo switch
DET-IN (Pilot Signal)
38 kHz
38kHz
l..I
JL
Vee
r -__~R6~3______-44-__________4-4-__~______~___ ~
19kHz
L-.f
19 kHz
R64
to demod ulator
10
LPF
11
LPF
9
ST LAMP & 19 kHz MONITOR
Fig. 15 Lamp Driver and Stereo Switch Circuit
1032
,uPC1235C
The lamp driver is shown in Fig. 15.
The phase detector composed of transistors 066, 067 and resistors R63, R64, R79, R80, R81, R82 performs
phase detection by the input signal (pilot signal) and 19 kHz divider output signal synchronized with the
above. The state is expressed in equations as below:
wS
ep(t) = Ep cos- t
Pilot signal
2
19 kHz divider output signal
edt)
=~Er (cos ws t -~cos 3 WS t +~cos 5 ws t ... )
IT
2
3
2
5
2
Here, if the output voltage of the phase detector is assumed as eo(t), since all but the standard wave are
removed by LPF out fitted to No.1 0, No. 11 terminals, equation becomes as below:
2
eo(t) =-Ep Er
IT
Accordingly, output proportional to the pilot signal is obtained for eo(t) after LPF.
When the pilot signal is input to the phase detector, difference in voltage level is brought about at No.1 0,
No. 11 terminals, and the collector current Id069) of 069, flows more than the collector current Id068)
of 068'
.
Consequently, the current difference AIC = IC (069) -IC (068) becomes unable to be let flow by the 'multicollector transistor i.e. active load, thus reducing the base current of 071 by Al c.
When 071 is turned ON, the collector current flows to the diode 05, and 074 is biased, and, consequently,
076 is turned ON. Since 076 is a multicollector, flow is effected on the one hand to the divider to turn
042, 043 of the qivider ON, and the switching signal of 38 kHz is supplied to the demodulator. Thus,
stereo demodulation is effectuated.
On the other hand, the current flows to the lamp driver made up of transistors 078 to 080 and light the
lamp. When the pilot signal is not input, the input level of No.1 0, No. 11 terminals become zero and the
collector current of 064' 065 constituting the differential is supplied only from 070' Thus, 071 becomes
OFF, and as no current flows to 05, 076 also becomes OFF. Consequently, 042, 043 become OFF and the
switching signal of 38 kHz is not supplied to the demodulator and monaural function is effected. At the
same time, the lamp driver becomes OFF so that the lamp is not lit.
(8) VCO stop, ST.-MONO switching circuit
Fig. 16 shows VCO stop and ST.-MONO switching circuit.
When voltage is supplied to No. 16 terminal, the constant-voltage circuit constituting with transistors 086'
087, diodes 09, 010 and resistors R94, R96 operates to give bias voltage to the transistor 084 and turns
031 of VCO ON and 032,033 OFF. Consequently, charge and discharge by the external capacitor at No.15
terminal are not effected and VCO stops.
At the same time, as bias is provided to 083 and 075 of the lamp driver is turned ON, 076 becomes OFF
and the switching signal of 38 kHz is not supplied to the demodulator. Thus charge is made to monaural
function and lighting is not effected.
To lamp driver
Vs
Vee
. . . - - - f - - - - - t - - veo
16
8
GND
Fig. 16 VCO Stop, ST.-MONO Switching Circuit
1033
,uPC1235C
4. APPLICATION EXAMPLES OF THE
~PC1235C
4-1. Stereo-Monaural Manual Switching Circuit
R95
----;0 022;F
LPF
11-------------------- 9
LPF
16
ST. RAMP
8
GND
& 19 kH.z MONITOR
V S ~ 1 .6 V C>----<>
ON -+ Stereo-monaural manual
switching
Fig. 17 Stereo-Monaural Manual Switching Circuit
The ~pe1235e, by virtue of synchronization with 19 kHz pilot signal normally input with 19 kHz generated
within Ie, injects the subcarrier of 38 kHz into the demodulator by driving the lamp driver as well as turning ON
of the gate circuit. In consequence, stereo multiplex demodulator function is made possible. However, the
necessity of monaural function at a set point irrelevant to condition of input circuit is considered. Fig. 17 shows
the operation circuit for such case.
As mentioned in previous section, when. the constant- voltage circuit is operated by applying voltage to No. 16
terminal, transistor 075 is turned ON and the gate circuit is turned OFF. Therefore, the subcarrier of 38 kHz
is not injected to the demodulator and monaural function can be effected forcibly.
The voltage level then applied to No. 16 terminal is V16 ~ 1.6 V.
Therefore, stereo-monaural switching becomes possible by virtue of muting voltage from I F stage etc.
4-2. On Beat Interference When Receiving AM.
As the ~pe1235e adopts PLL (Phase Locked Loop) system, it has an internal oscillator. While AM receiving,
the internal oscillation voltage can give interference so that veo becomes necessary to be stopped.
As stated in foregoing section, when transistor 031 is turned ON and, in consequence, transistors 032, 033 are
turned OF F, charge and discharge at external capacitor are not effected and the oscillation of veo stops.
Accordingly, if voltage is applied to No. 16 terminal, transistor 084 becomes ON and 031 becomes OFF. Thus,
by simply applying voltage to No. 16 terminal, oscillation of veo can be stopped and at the same time, forced
monaural function becomes possible. Further, as the voltage level at the time of stereo-monaural manual
switching is 5 ~ V16 ~ 1.6 V, and that when veo stop is Vcc ~ V16 ~ 7 V, individual function is possible according to the level of voltage applied.
1034
j.lPC1235C
470pF
--------9
----------~
; / RL
~VL
OFF--+~;~i~or P.L
BGNO-
~VCC
AM-ON Switch
' - - - - - - - 0 1 9 kHz Monitor
Fig. 19 VCO Monitor Circuit
Fig. 18 VCO Stop Circuit
4-3. On
-----
veo Monitor
VCO monitor circuit is shown in Fig. 19.
This is to monitor from No.9 terminal dividing the oscillation frequency 76 kHz of VCO into 1/4 (19 kHz)
by the divider.
At this time, monitoring can be performed by making input signal to monaural signal and directly connecting
the frequency counter to No.9 terminal by cutting off the stereo indicator lamp. VCO oscillation frequency
is adjusted by means of a semi-fixed potentiometer connected to No. 15 terminal.
4-4. On Stereo Lamp Lighting Level
The stereo lamp lighting level can be adjusted, as is clear from the circuit shown in Fig_ 15, by changing the input
ON level of the differential amplifier circuit made up of transistors 068' 069' 070, 072.
Generally, when 19 kHz pilot signal increases, the base potential rises, and if it becomes above a certain potential,
more collector current i2 of 069 flows than the current i 1 of 068' Further, in case the 19 kHz pilot signal is not
input, as active load 070 is set so that collector current of 068 and 069 becomes i 1 i2' if it becomes i2 ~ i 1,
the collector current of 069 cannot be supplied by 070 only.
Accordingly, deficiency i2-i 1 of the collector current of 069 is reduced from 071 and light the lamp.
From the above, it will be understood that to charge the lamp lighting level can be performed by charging the
offset voltage of above mentioned differential amplifier circuit.
Examples of change are shown in Fig. 20 and Fig. 21.
>
-
@
@
:~
R1
• R
Q])
Fig. 20
R3
GY
R2
Fig. 21
1035
,uPC1235C
4-5. Explanation of External Componentes
~~N-~----~-+----4-~~~----+-----------~Rch-OUT
VCC~----------~~--~~~~~--~--~~--~I~----~----------~Lch-OUT
Fig. 22 Explanation of External Components
a. Semi-fixed potentiometer for determ.ination of VCO oscillation frequency.
b. PLL loop LPF. Determines lock range together with PLL loop gain.
c. Lamp operation LPF. Determines low pass cutoff frequency by internal
impedance and time constant. When the value of C is large, cutoff frequency
becomes low.
d_ 19 kHz veo monitor terminal and stereo indicator lamp. To monitor 19
kHz switch is turned OFF and to light the lamp switch is turned ON.
e. Manual monaural switching switch and VCO stop. Then, monaural level
5 V ~ V16 ~ 1.6 V, veo stop level Vee ~ V16 ~ 7 V.
f. PLL input coupling capacitor. Divides audio frequency from pilot frequency.
g. Input coupling capacitor. Effects low pass Fre-characteristics and low pass
Sep-characteristics.
h. Input resistor. Determines gain of the input amplifier.
i.
Input registor of output stage post amplifier. Effects gain of amplifier.
j.
Semi-fixed potentiometer for adjusting Sep.
k. Resistor to determine gain of the output post amplifier.
I.
Output capacitor and resistor. Determines output de-emphasis characteristics.
Effects gain being feedback resistor of the output post amplifier.
m. Lamp protecting resistor.
n. Lamp by-pass resistor
1036
,uPC1235C
4-6. Typical Application (Top View)
19kHz monitor
470pF*
3.3/-lF
P.L.
VS~1.6V
Lamp protecting registor
0 - - -.....
ON
Stereo - mono
manual switching
ON
-+veo
STOP
MPX Input 4.7J..1F R1
47kn
~---+----~
+
l00DpF
22kn
10kn
3.3kfl
Rch-OUT
-
lO/-lF
3.3kn
+
Sep. Adj.
LPF
500kn VR
lOJ..IF
3.3kn
+ 3.3kfl
Lch-OUT
Vee
+12V
LPF
VCO Adj.
Sep. Adj.
*470 pF
BL-13 (Karin giken)
VCO tuning semi-fixed potentiometer
Separation adjusting
semi-fixed potentiometer
Polystyrene capacitor
Fig. 23 Typical Application
NOTES:
When the unit is used with power supply voltage of less than 12 V, the mid-point electric potential of the
output terminals 6,7 in the above typical application may change and Total Harmonic Distortion at output
terminal will increase.
In this case change the bias resistor 47 kn. between terminals 5, 6 and terminals 4, 7 and keep at mid-point
electric potential.
1037
jlPC1235C
Example of printed-circuit board (unit: mm)
100
t"
~.:~
"'., 'Z-::, '.-<"
9'
';.""~,
'"T- ,:' ~ >
o
I
I
o
<0
L
o
(Bottom view)
Fig. 24 Example of Printed-Circuit Board
Outboard components mounted on a printed-circuit board
+Vcc
Stereo-Monaural Switching
VCO STOP
MPX Input
o
o
o
o·
o
Rch-OUT
VCO Adj.
Lch-OUT
Stereo Indicator Lamp
19 kHz monitor
Sep. Adj.
(Bottom View)
Rl=47 kn
R6 =47 kn
Rll=15 kn
Cl =1 00 IJF
C6=1 000 pF
C11 =10 IJF
Sep. Adj.=500 kn VR
R2=10 kn
R3=22 kn
R7 =3.3 kn
R8 =47 kn
C2=4.7 IJF
C3=500 pF
R9 =3.3 kn
VCO Adjt=5 kn VR
BL-13=19 kHz
LPF (Korin giken)
R5=22 kn
RlO=1.0 kn
C7 =0.22IJ F
C8 =1.5IJF
C9 =3.3IJ F
ClO=470 pF
Polystyrene
C12=10 IJF
C 13=10 IJF
R4=10 kn
R12=3.3 kn
R13=3.3 kn
R14=1.0 kn
R L =Lamp
protet:ting
resistor
C4=0.047 IJF
C5=1 000 pF
C14=10 IJF
capacitor
Fig. 25 Outboard Components Mounted on a Printed-Circuit Board
1038
,uPC1235C
4-7. Typical Performance Characteristics
f = 1 kHz
No signal
-
~
~'18
0
~
-2
>
Ul
I -3
I 17
>
U
u
c
ro
~
f--
.....
L~R
50
Cll
Q.
~
Cll
g
Ul
U:
ClJ
C
19.0
en
~ 40
.s::
.~
U
c
c
I
a:
Q.
Cll
~
18.9
~
~ 30
u..
I 18.8
20
o
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8
Vin - I nput Signal Level - V
0.9
Fig. 30 CHANNEL SEPARATION vs.
I NPUT SIGNAL LEVE L
1.0
6
10
12
14
8
Vee - Power Supply Voltage - V
16
Fig.31 FREE RUNNING FREQUENCY DRIFT vs.
POWER SUPPLY VOLTAGE
1039
pPC1235C
Vee = 12 V
Vin(pilot) = 30 mV
o dB = 18 dB
70
co
60
-... ~~
o
"0
I
c 50
o
.~
~
~40
----
,,'"
R~ r--::.: ..... ....L~R
~ ->-
'
......
~
co
-2
~
"0
,
"",
Q)
(j)
a:;
~ 30
I
-4
c
~
-6
~
-8
~
-10
~
~
u
I 20
ci.
~-12
JS
I
a>
>
CI)
..J
...
1.0
·8
g
o. 1
\
,
,,
,
'
,
E
~ 0.0 5
\~
'iii
~
j
I
">
0.2
ci
8
,'-- --- --,,- --
0.0 2
:i
r..:
~-
~"
~V
0.0 1
IJ'
I
,
~
I
1/
/
c:
Il't
0.0 3
/
.~ 0.4
I
a
V
E
::l
E
I
u
'c
~
/
a:I
0.2
i:5
V
c:
~ 0.6
0.3
c:
0.8
~
::l
0.5
I
/
::l
~
V
r-t-'""
L
V
10
12
14
16
Vee -Power Supply Voltage-V
RONLY
~_l:~
Fig.37 MAXIMUM MONAURAL INPUT LEVEL
vS.POWER SUPPLY VOLTAGE
~
~O~O ?-
0.00 5
8
10
12
14
16
Vee - Supply Vo Itage - V
18
Fig.36 TOTAL HARMONIC DISTORTION
VS. SUPPLY VOLTAGE
Vec
= 12 V
= 30 mV
Yin (pilot)
60
OJ
V
50
/
"0
I
c
I'
0
.;::;
~
(exclude external parts)
Q)
"\
:J
19.10
u::
19.00
cr
Q)
t\.
~ r--.....
............
1'--."
OJ
\
c
c
c
18.90
a:
18.80
-~
t'......
..............
:J
40
~
Q)
Q)
(1)
a.
Q)
u::
(/)
""
18.70
0
Qi
c
c
19.30
>- 19.20
u
c
L ~ . /~
Put into temperature
test chamber only IC
N
I
~
U
30
>
(1)
18.60
I
.!:
U
~ 18.50
I
......0
ci.
20
Q)
18.40_ 20 -10
(/)
0
10
20
30
40
50
60
70
Ta - Ambient Temperature _ DC
Fig. 39 VCO FREE RUNNING FREQUENCY
vs. AMBIENT TEMPERATURE
10
o
18.20
19.00
19.80
fosc - VCO Free Running Frequency - kHz
Fig.38 CHANNEL SEPARATION vs.
VCO FREE RUNNING FREQUENCY
1041
,uPC1235C
+5
Vee = 12 V
Vin(pilot) = 30 mV
Vee = 12 V
N
I
'L
~
=0
+4
mA
I
> 19.20
+3
u
c
eft.
Q)
:J
I
rr
+2
Q)
Q)
Ol
U:
19.10
Ol
.~
c
~
C
:J
a:
c
+1
C1l
a:
Q)
~ ""-
~
0
C1l
-1
Q.
19.00
U
Q)
~
I
-2
a:
0
U
>
U
18.90
-3
I
u
-4
. . .0
o
2
-5
3
-20 -10
0
10
20
30
40
50
60
70
Ta - Ambient Temperature _ DC
T -Time After VCCON - minutes
Fig.41 CAPTU RE RANGE vs.
AMBIENT TEMPERATURE
Fig. 40 TIME DRIFT OF VCO FREE
RUNN ING FREQUENCY
14
13
>
12
I
11
>
E
ON
E
Q3
>
Q)
....J
roc
Ol
en
.2
0....
I
c
->
I
80
0
70
lO
Cii
9
_20 e
60
>
Vee = 12 V
Q)
....J
roc
50
.2' 40
8
C/)
~
:J
a. 30
7
c
OFF
6
I
II
I\~ /75
~~
20
4
I °
-20 -10
0
10
20
30
40
50
60
70
Ta - Ambient Temperature _ DC
Fig. 42 PILOT LAMP INPUT LEVEL FOR
LAMP ON-OFF vs. AMBIENT
TEMPERATURE
-5 -4
-3
e
''-.
'"~ L/
-2
f'\
I
75 De
f\
10
o
25°e
/25°e
c
>
o
_20 e
o
~
5
1042
90
-1
0
J
Jh
VII
~~
~
+1
+2
+3
+4
+5
C.R. - Capture Range - %
Fig.43 PILOT LEVEL AND AMBIENT
TEMPERATURE vs. CAPTURE RANGE
,uPC1222C AND ,uPC1222C(R) . THEIR OPTIMUM USAGE
1 OUTLINE OF J.LPC1222
The ,uPC1222 is a silicon monolithic integrated circuit operating on a low supply voltage. It includes an FMIF .amplifier, FM detecter, AM-M IX, OSC, AM/I F-Amp., AM-detecter, and AGC circuit.
Its optimum usage is for radio sets and radio cassette sets with 4.5 V power supply, however, its characteristics
allow it to be used for medium class stereo radio cassette sets.
2 DIFFERENCE BETWEEN ,uPC1222C AND ,uPC1222C(R)
,uPC1222C(R) (hereinafter called (R) type) has suffix (R) which stands for "reverse" to indicate that the
detection characteristic curve of the FM detecter, or so-called S curve, is in reverse to that of J1PC1222C (called
C type).
Since their electrical characteristics are, except S curves, utterly same, they can be used without any difference for sets using no AFC.
10.7 MHz
10.7 MHz
Fig. 1-a S curve of C type
Fig.1-b S curve of (R) type
3 THE PROPER USE OF C TYPE AND (R) TYPE
On designing an FM radio set, its AFC circuit is configured as shown in Fig. 2-a when the set is for domestic
(Japanese) use, and as shown in Fig. 2-b when for overseas use.
The circuit shown in Fig.2-b has one more external resistor than that shown in Fig. 2-a and setting of the
bias is more complicated in the former circuit (Fig. 2-b).
J.LPC1222C
J.LPC1222C
7
~J\A,"v--_.U--4~
r-- to OSC
...
AFC Circuit
OSC Circuit
Fig.2-a AFC circuit in the Japanese system
AFC Circuit
Fig.2·b AFC circuit in the American and European systems
1043
)lPC1222C,)lPC1222C(R)
In these cases, if an (R) type is used for an American or European system, its AFC circuit can be as that shown
in Fig. 2-a.
Therefore, same printed circuit boards can be used for domestic and overseas sets whose reception wave bands
are designed as so-called wide band (76 to 180 MHz).
Thus, the proper use of pPC1222 is configuring the AFC circuit as shown in Fig. 2-a, and;
using pPC1222C for domestic sets, and
using pPC1222C(R) for overseas sets.
4 DIFFERENCE IN INTERNAL STRUCTURE
The internal structure of the (R) type is completely same as that of the C type except connections of R48
and R49. In the (R) type they are connected in reverse to those in the C type.
FM-OUT
FM-OUT
Fig.3-a pPC1222C
1044
Fig.3-b pPC1222C (R)
/LPC1222C(R), /LPC1222C;
APPLICATION TO SHORT WAVE BAND
1 OUTLINE OF IlPC1222C{R), IlPC1222C
MPC1222C(R) and MPC1222C are FM-I FlAM Tuner System ICs operating at low voltages (V cc=2 V min.)
and it includes detection circuits. MPC1222C(R) is same as MPC1222C in their characteristics except that their
FM detection S curves are in reverse to each other. Hereinafter, they are represented by MPC1222.
2 APPLICATION OF IlPC1222 TO SHORT WAVES
1) Notices on Designing Oscillation Coils
1 Making coupling between primary and secondary of oscillation coils as tight as possible:
When the secondary coil is tightly coupled to the primary, the oscillation frequency is determined by L
and C of the primary side. On the contrary, if this coupling is loose, oscillation whose frequency is determined by secondary coil and capacity of inside IC occurs to affect the waveform of oscillation to be introduced into #1 pin and sometimes to stop oscillation.
2 Making the turn ration of primary and secondary coils large:
The larger number of turns of the secondary coil enables what is described above ( 1 ).
Be careful,
however, that, by so doing, capacity within the IC affects the primary side to make it sometimes impossible
to acquire the cover range desinged using the value of L in the primary side.
I n order to satisfy what are mentioned in 1 and 2 simultaneously, it is a good method to wind the secondary
coil over the primary as shown in Fig. 1. Split winding, shown in Fig. 2, generally used for short waves is not
suitable for MPC1222, an oscillation circuit.
Core
Core
Primary coil
ItZ:z:lZZZ!---,. Primary coil
Secondary coil
Secondary coil
~---l--.
Lead
Lead
Fig. 1
Fig.2
1045
jlPC1222C,jlPC1222C(R)
2) Example of Oscillation Coil for Short Wave
An oscillation coil for short waves made as an example is explained below:
GND/~~
vc
~~
o Bobbin: ¢ 7.5 mm
o Core: 10 MHz
Batt
o Wire material: polyurethane covered copper
wire
Coil
diameter:O.15 mm
Fig. 3 Coil terminal connection
Table 1 Coil data and Oscillation Frequencies
No.1
CD-@
29I-LH
No.2
CD-@
4.851-LH
No.3
CD-®
1.241-LH
No.4
No load Q
Inductance
Coil No.
CD-@
71
(2.52 MHz)
CD-®
@-@: 8~T
@-@: 3~T
:CD-@: 7~T
CD-®
CD-@:3~T
@-@: 3~T
@-@:
Way of winding
Oscillation frequency (VC : 80 pF)
Overlap
2.6 - 6.4 MHz
Overlap
7.6 - 23 MHz
Parallel
19.6 - 42 MHz
Parallel
25 - 70 MHz
T
CD-@
68
(7.96 MHz)
66
(25.2 MHz)
0.441-L H
CD -@: 44~T
1:1)- ®: 14~
74
(7.96 MHz)
CD-@
Number of turns
3;l T
4
Note 1: Coils are designed so that they match the trackingless variable capacitor (COSC Max.=80 pF) useo for
MW.
2: "Overlap" and "Parallel" in the item of "Way of winding" represent those shown in Figs. 4 and 5 respec-
tively. Winding Coils No.3 and 4 in parallel offers no problem. It is because coupling between primary
and secondary coils is tight enough due to high frequency.
_
Bobbin
#
..
Primary coil
Secondary coil
I
Lead
Fig.4 Overlap winding
1046
__
Bobbin
~
primary
coil
Secondary coil
I
Lead
Fig.5 Parallel winding
JLPC1222C, JL PC1222C(R)
1FT: CFZ-455C(TOKO}
AMDET Coil: 7MC-5251Y(TOKO}
100
FMDET Coil: 119AC-12747Z(TOKO}
n
+
10 kn
TI
0.022 J.lF
2.2kn
0.068 "F
I
100 kn
v. V. A F
0.01 J.lF
L..---4----+-----.-----Q Vee
0.022"F
I
+
3.9 kn
FM DET Coil
Fig. 6 Short wave measuring circuit
* Turn the switch (SW) to CD when M I X gain measuring, and to ~ when total gain measuring.
1047
o
~
Q)
1:::
"'C
Fig. 7 VOLTAGE GAIN AND OSCILLATION VOLTAGE vs. FREQUENCY
(")
I
~
V cc=4 V
1
1
1
1
1 1
N
N
N
mod.=30 %
f mo d=400 Hz
60
1
J:
I I I
..(")
1
1:::
"'C
L-L---+--+-+---+----+--+---t---t--t----1-111,-"\G v (Total)
(")
~
50L-1-l-LJ-t----~--4-----~~L-~_+_+-t~t---_i--~----_r---t--~r_
Vo(AF) = 10 mVr.m.s.
(/)
~
---lr--t:r- MW band (the coil recommended in the catalog)
->E
- 0 - - - 0 - - Coil No.1
en
"0
I
c
40~1--+-~~+-~~
-x-x-
I
Q)
Coil No.2
OJ
I I
Vosc (at #1 pin)
Coil No.3
co
I 400
>
c
.g
OJ
Q)
>
u
- - - 0 - - 0 - Coil No.4
OJ
~
o
S
0
Q)
30
300
I
.,. .......x
>
C)
x1
1
1
I
I
I
I
1
1
I
I
I
I
...
200
l
:~
c
0
.;:;
~
'u
I
1100
0
I
10
>
I
~
0
201
J\~
A
----~--
L~x+-)(
.~.
to(~t=d
~-6.
I~
II11
10
Measuring Circuit-CD
Vj=60 dB.uV
o
700k
1M
2M
3M
5M
7M
10M
f- Frequency - Hz
20M
30M
50 M
70 M
N
N
N
--:c
(")
APPLICATION OF THE J.lPC1197C INTEGRATED CIRCUIT
PLL MULTIPLEX STEREO DEMODULATOR
1. DESCRIPTION
The J,LPC1197C is a silicon monolithic integrated circuit designed for PLL (Phase Locked Loop) FM multiplex
stereo demodulator applications in FM stereo radio receivers. The device contains VCO (Voltage Controlled
Oscillator), phase detectors, LPF (Low Pass Filter), frequency dividers and DC amplifiers for a stereo composit
signal. It also contains an automatic stereo-monaural switching circuit, a VCO mute circuit for FM/AM radio
application, a forced monaural switch-over circuit, and an automatic change-over circuit from stereo to monaural
at low supply voltage.
2. FEATURES
(1) Wide operating voltage range. V cc = 4 to 16 V
(2) Low noise stereo-monaural switch-over.
(3) Built in switch-over circuit for forced monaural and VCO mute circuits for FM/AM radio application.
V(#9)~3
V for VCO mute
0.7 V ::; V (#9)
< 3 V for forced monaural
(4) Automatic switch-over from stereo to monaural at low supply voltage. (V cc ::; 3.5 V)
(5) No coil is necessary, all tuning is performed with only two potentiometers.
(6) The terminal (8) is for separation adjust.
3. PACKAGE DEMENSIONS
R 1
UNIT: mm
Typical values unless
otherwise noted.
O.5±O.1
1049
pPC1197C
4. BLOCK DIAGRAM
VCO
LPF
19 kHz
MONITOR
P.D
INPUT
LPF
LPF
LPF
STE./MO. SWITCH-OVER
VCO STOP
P.D:
F.D:
STABILISED
VOLTAGE
CIRCUIT
COMPOS IT
SIGNAL
INPUT
PRE
AMP.
OUTPUT
R-CH
OUTPUT
L-CH
OUTPUT
Fig.1
ITEM
SYMBOL
Package Dissipation
Vce
Po
Operating Temperature
Topt
Storage Temperature
Tstg
6. RECOMMENDED CONDITION (Ta
1050
GND
SEPARATION
ADJUST
Block Diagram
5. ABSOLUTE MAXIMUM RATINGS (Ta
Supply Voltage
LAMP
DRIVER
= 25°C)
RATING
UNIT
16
V
350*
-20-+75
-40--+125
mW
°c
°c
=25°C)
ITEM
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply Voltage
Vee
4
9
16
V
PHASE
DETECTOR
FREQUENCY
DIVIDER
J,lPC1197C
7.
ELECTRICAL CHARACTERISTICS
(Ta=25
°c, Vcc=9
V,vi=200 mVr.m.s., L=45%, R=45%, PILOT=10%)
CHARACTER ISTIC
Circuit Current
Separation
SYMBOL
Icc
Sep.
CONDITIONS
MIN.
TYP.
MAX.
16
UNIT
No Signal
7
12
f=100 Hz
30
45
mA
dB
f=1 kHz
40
55
dB
f=10 kHz
30
45
dB
Total Harmonic
Distortion
T.H.D.
vi=200 mVr.m.s. Monaural
0.3
0.5
%
Total Harmonic
Distortion
T.H.D.
vi=200 mVr.m.s. Stereo
0.2
0.5
%
Output Voltage
vo
vi=200 mVr.m.s. Monaural
Channel Balance
ch.B
vi=200 mVr.m.s. Monaural
Input Pilot Level for
Lamp ON
mVr.m.s.
170
-2
0
2
dB
4
8
12
mVr.m.s.
4
dB
±1.5
±4
%
LAMP-ON
vi=Pilot
Lamp Hysteresis
Hys. (LAMP)
vi=Pilot
Caputure Range
C.R.
vi(pilot)=20 mVr.m.s.
Rej. (19)
vi(pilot)=20 mVr.m.s.
35
dB
Rej. (38)
vi(pilot)=20 mVr.m.s.
45
dB
_ 1
vi(pilot)
vi(compsit) - fO,
_ 1
vi(SCA)
vi (composit) -fO
70
dB
500
mVr.m.s.
86
dB
Ultrasonic Frequency
Rejection
SCA Rejection
Maximum Input Level
Signal To Noise Ratio
Forced Monaural
VCO Stop
Stereo-Monaural
Switch-over Voltage
Rej. (SCA)
vi(MAX.)
SIN
T.H.D.~2 %
vi=200 mVr.m.s.
V (Monaural)
Terminal No.9
V(Stop)
Terminal NO.9
Vcc(Monaural)
Supply Voltage
V
0.7
2.7
3.0
3.5
3.7
V
V
10SI
,uPC1197C
8. TEST CIRCUIT
19 kHz
MONITOR
FORCED MONAURAL
VCO STOP
lVB
SW
O.047Il F
Fig.2 Test Circuit
POL YSTYLENE CAPACITOR
LOW PASS FILTER: BL - 13 (KaRIN LAB.!
Transistors Q1 and Q2 should be set so that, the voltage gain
between the output terminal of the IC and the output terminal
of the LPF is 0 dB.
1052
,uPC1197C
9.
EQUIVALENT CIRCUIT
Fig.3 shows the equivalent circuit of the J..LPC 1197C
#3
#13
#11
#10
#15 #14
#16
#7
#8
#6
#9
#12
Fig.3 Equivalent Circuit
1053
o
-'
1::
."
0
m
-'
01
~
P
Low pass filter of the PLL loop. Determines
the locking range and the PLL loop gain.
Monitor terminal for the oscillation
frequency of the 19 kHz veo
en
n
Low pass filter for operating lamp. Determines
the low region cut off frequency according
to the time constant made in combination
with the internal impedance.
jJ
"
0
-f
2
0
."
m
Semifixed resistor for determining the
oscillation frequency of the VCO.
Set the resistor so that the oscillation
frequency of the terminal (10) is 19 kHz
X
100kn
~tolF
-I
m
jJ
2
»
r0
en
n
C5
jJ
O.047Il F
Lamp series resistor.
Lamp current is determined by
Vee- VeE(sat)
R
=i
m
("')
0
s:
"2
0
m
-' -+
1-'- ~
'\f\A
-,
2
0 VB
-f
11l F
Input coupling capacitor. This has
an effect on the low frequency and
separation characteristics. The low
region frequency characteristics by
are determined the time constant
made in combination with the
50 kn input impedance.
en
o VCC
+
Output capacitor
Determines with the output load
resistor R. the output de-emphasis
characteristic
Output load resistor.
-1.4 dB when 3.3 kn
Fig.4 Description of External Discrete Components
100llF
n
~
(,0
'-J
n
,uPC1197C
11. TYPICAL APPLICATION
1 J..lF
·20k.l1
100k.l1
..-----+-..JVI/\r----o to IF
RS
+
Cll
-
1 J..lF
0.047 J..lF
~----~--------------_+----------------1---~VCC
L.P.F.
L.P. F.
Rg
RlO
Lout o--+-~'\I'Ir-.__~Vv_-+---o Rout
3.3 k.l1
3.3 kD.
Fig. 5 Typical Application
11-1. Notes for Use
(1) The J1PC1197C is designed to have a equivalent thermal constant to a polystylene capacitor.
(2) In the application which the terminal (9) is connected to the terminal (1) to force monaural or to stop
VCO, when the supply voltage is over 10 voltages, insurt a resistor which have a value shown by the
next equation.
1.1 { Vcc (MAX.) - 10 }
~
R ~ 2 { Vee (MAX.) - 4 }
Vcc (MAX.): Maximum voltage ofa power supply
Vcc (MIN.) : Minimum voltage of a power Supply
1055
,uPC1197C
11-2. Printed wiring board (Copper side)
105mm
L
N"EC
E
E
L!1
to
C1197
R
Fig.6 Printed Wiring Board
11-3. Components layout for P.W. assembly (Copper side)
105mm
E
E
L!1
to
Rl=18kn
vRl=5kn
R3 = 1 kn
R4 = 100 kn
R5 = 3.3 kn
R6 = 3.3 kn
R7 = 330 n
R8 = 100 kn
Rg = 3.3 kn
RlO = 3.3 kn
Cl = 470 pF * POL YSTYLENE
C2 = 0.331l F
CAPACITOR
C3 =
C4 =
C5 =
C6 =
1 IlF
2.21l F
0.047 IlF
1 IlF
Fig.7 Components Layout for P.W. Assembly
1056
C7 = 0.015~F
C8 = 0.0151l F
Cg = 3.3 ~F
ClO = 3.31l F
Cll = 1 IlF
C12 = 100 IlF
,uPC1197C
12. DESCRIPTION OF CIRCUIT
Vee
#,~~~----~~----~~---+-
Vs
12-1. Stabilized Voltage Circuit
The equivalent circuit of the stabilized voltage Circuit is shown in Fig. 8. In Fig. 8 the stabilized voltage
Vs is expressed by the equation (1) the reference voltage Vr is expressed by the equation (2). Both are
constant against variations of the power supply.
I
Vs = R 11 +
~ 12 + R 13
X
Vr . . . . . . . . . . . . "
(1)
#7~~~~~~~~--~~~~
13
vr=~:
V,
GND
Fig.8 Stabilized Voltage Circuit
{VBE(03)-VBE(02)}+VBE(Os) .... (2)
The biases of other circuits are designed with the stabilized voltage Vs. The circuit composed of a diode
03, transistors O2 , 05 and resistors R4 , Rs, R6 is the thermal compensation circuit of the reference voltage
Vr.
Vr
= V BE
(05) + Ic (02) . Rs + IB (05) . Rs
= V BE
(05) +
~:
l'.V BE + IB (05) . Rs (l'.VBE
= V BE
(03) - VBE (02) )
- V
+ Rs (KT I J03) + I
R
- BE (05) R6
n J02
B (05)' 5
q
== V
.
BE (05)
+ RR s (KT InR
RS
6
q
4
) ............
(I B (05)' Rs«
(3)
1)
aVr = aVBE (05) +.IS. &.
(Rs)
(4)
aT
aT
q . R6 In R4 ......... .
The equation (4) expresses the reference voltage compensated against thermal vaviations is given by to
choose the values of resistors R4 , Rs and R6 fitly.
12-2. Input Signal Amplifier
The equivalent circuit of the input buffer amplifier
is shown in Fig. 9. The input signal amplifier is composed of transistors 0 12 , 0 13 , 0 14 , resistors R 19
R20 , R21 and a capacitor C3 . Since transistor 0 13 is a
multi-collector transistor, its collector current is nearly
the same as the collecter current of transistor 0 12 .
-And its current gain is close to unity. Capacitor C3 is
for frequency stability, and its value is 5 to 20 pF.
The voltage gain of the input signal amplifier is
determined by the feedback circuit R 19, R20 , and
expressed by the following equation (5).
I
Pre Out
Vee------------+_--~~4-----
Vs--~----~--+_--+__+4-~---
v,
A v (AF) -- R 19 R+ R20 . . . . . . . . . . . . . . . . . . (5)
20
Stereo signals entering terminal (2) are amplified
by an amount indicated the above equation, and then
Fig.9
Input Signal Amplifier
introduced to the phase detector of the PLL circuit
through terminal (3). Besides the above, stereo signals
pass through emitter follower 0 16 and are injected into the stereo demodulator circuit.
1057
,uPC1197C
12·3. Demodulator Circuit
The equivalent circuit of the stereo demodulator is
38 kHz
38 kHz
shown in Fig. , O. The circuit consists of a common
V4
U
.fl.
double-balanced type detector circuit, the stereo
signals are injected into the lower transistors 0 42 and
-+----+- Vs
0 43 while the 38 kHz subcarrier is injected into the
upper transistors 0 38 , 0 39 , 0 40 and 0 41 . Stereo demodulation is accomplished by the subcarrier switching the above transistors.
The resistors R S4 ' R ss , Rso and external resistor
Rs (Fig. 2) are feedback resistors inserted for the
parpose of cancelling the cross tal k components produced during the switching. To adjust the external
resistor Rs give the best separation.
The subcarrier is a 50 % duty cycle 38 kHz wave
obtained from bistable multivibrator (flip-flop) cirFig. 10 Demodulator Circuit
cuit, into which a 76 kHz signal produced by the VCO
is injected. I n the pPC" 97C the stereo lamp and
stereo demodulation are synchronized and accomplished by transistor 0 46 . The base of 0 46 is controlled by the stereo lamp circuit, and when the stereo
lamp is turned on 0 46 will also be turned on and a 38 kHz subcarrier of reverse phase will be injected into
the demodulation circuit, 03S, 0 39 ,0 40 and 0 41 . On other hand, when the stereo lamp is turned off 0 46
is also turned off, and an in-phase 38 kHz subcarrier is injected into 03S, 0 39 , 0 40 and 0 4 I so that a
monaural wave is obtained from the output terminal (4) and (5).
12· 4. Lamp Driver
Fig. , 1 shows a lamp
driver circuit with its auxiliary circuits.
The phase detector circuit and low pass filter are
composed of transistors
OS2, OS3, resistors R 64 ,
R 6S , R 66 , R67 and the
external capacitor C4 (Fig.
P.D INPUT
v2
v~S
19kHz
19kHz
______+-+-__
~~__~__-4____~______~________
L..-+-____
2)
GND
+---+-~
__
Vg
The lamp driver circuit
is composed of transistors
# 11
# 10
OS4 to 0 66 with ist auxiliLPF
ary resistors. Transistor
Fig: 11 Lamp Driver
OS4 and Oss amplify the
DC voltage obtained through LPF. Transistor OS7 is a active load of the differential amplifier .. Now, if the
collector current Ic (054) of OS4 and Ic (055) of Oss change by ~Ic (~Ic = 1c(055) - Ic (054))' due to the
control current passed through the phase detector, ~Ic will flow intact into the base of Oss.
Oss is a multicollector transistor, and its collector current will amplify the change ~Ic of the base current and 0 10 will become biased by this current. And, when this diode is biased transistor 0 62 will operate
causing lamp driving transistor 0 64 to be turned on, thus the lamp will light. On the other hand, when 0 62
turns Gn it will draw the base current of 0 63 , and as a result 0 63 and 0 46 will be turned on and stereo operation will start.
Since transistors OSS, OS9 diode 010 and resistor R69 form a positive feedback loop, when the lamp is
turned on, this rise of current will be abrupt. In addition transistors 0 61 , 0 64 , 06S and resistor R73 form a
negative feedback loop, which composes a current limiting circuit for performing current limiting action.
1058
,uPC1197C
12-5. Phase Detector and DC Amplifier
Fig. 12 shows the phase detector and the DC amplifier.
The 19 kHz signal obtained through the divider will
switch the pilot signal of the stereo signals coming into terminal 13, and will supply a DC voltage proportional to the
phase difference of these to the DC amplifier composed of
0 19 to 0 23 . When the phase difference of the 19 kHz signal
and pilot signal, entering the phase detector, is 90° the control voltage of the PLL circuit will be O. When the phase of
the 19 k Hz signal advances from the above, a positive control voltage will be produced, and when the 19 kHz phase
lags a negative control voltage will be produced.
When this state is expressed as an equation, it becomes
as follows.
P.D INPUT
LPF
#13
Vs
V,,-5_ _ _-+_-+-<
J l . L.S
19 kHz
Pilot Signal ep (t) = Ep cos wpt
19 kHz Signal e19 (t) = E19 sin (wp + ¢) t
(Note) (To be precise, 19 kHz is a square wave.)
ep(t) x e19(t)
19 kHz
Fig. 12 Phase Detector
and DC Ampl ifier
= Ep ~ E19 {sin¢t + sin (2wp + ¢) t }
= Ep ; E19 sin¢t ........ (6) Eliminated by LPF
The DC amplifier converts the change of the control voltage to current to be sent to the VCO.
12-6.
veo (Voltage Controlled Oscillator)
Fig. 13 shows the VCO.
This circuit is basically a comparator, which produces oscillations through variations of the reference
voltage.
Now, when transistor 0 25 is operating, both 0 29
and 0 30 will become conducting and the instantaneous reference voltage of the comparator applied to
the bace of 0 25 is expressed as follows.
#16 veo
Ve~e-+__4-+-~_ _ _ _ _~
Vs
GN~D
VH
= (VS
- VCE(sat.l (0 30 ))
X
R
R35 R
"
32
35
+
...
(7)
_ _ _~__~____~_-4_-*___
Va
#9
Fig.13 VCO
On one hand, current will flow from the emitter of 0 30 , and this current will charge the external capacitor C 1 (Fig. 2) through R 30 . The charging time tl of this capacitor is expressed as foilows:
VS -VL
tl = R 3o C 1 In Vs _ VH .................... (8)
When the above charging is completed the comparator will be switched-over and 0 24 will be turned on.
At this point, the reference voltage VL of the comparator will become as follows.
VL
= Vs
x
R34
R:~35
......................
(9)
1059
,uPC1197C
The charge accumulated in the external capacitor of terminal 16 will discharge at a rate determined by
the external resistor R 1 , R2 and capacitor C1 (Fig. 2).
The forced monaural circuit and VCO stopper are composed of transistors 0 67 , 0 68 , 0 28 ,0 60 and resistors R76 , R77 . 0 60 is turned on by the external voltage on terminal 9, and as a result 0 64 turns off and the
lamp turns off. (0.7 ~ V9 -:; 3 V)
When higher voltage is added on terminal 9 0 69 will turn on, as a result 0 29 will turn off and VCO will
be stopped.
12·7. Divider Circuit
Fig. 14 shows the divider circuit.
19 kHz
19 kHz
19 kHz
19 kHz
38 kHz
38 kHz
This circuit is a bistable multivs ____~+------+~--~------~--~~----_+.
vibrator (flip-flop). This multivibrator serves to produce 38
kHz and 19 kHz, 50 % duty
cycle, signals from the 76 kHz
signal generated by the VCO.
The 38 kHz signal is the subcarrier required for FM stereo
demodulation, the 19 kHz having
a 90° phase difference with tha
Fig. 14 Divider Circuit
pilot signal is required as the
control voltage of the PLL, and
the 19 kHz synchronized with the pilot signal is required for driving the stereo lamp and controlling
the stereo switch.
u
1060
,uPC1197C
13. CHARACTERISTIC CURVES
Fig.15 CIRCUIT CURRENT vs. SUPPLY VOLTAGE
Fig.16 VOLTAGE GAIN vs. SUPPLY VOLTAGE
(Monaural)
20
No Signal
18
bdB=-l.4dB
f = 1 kHz
vi = 200 mVr.m.s.
+2
16
~
14
I
C
~
12
~
~
u 10
r-I- ......
--
ell
f- f-f-'
+1
"0
I
c
'co
I
c.:J
0
OJ
/
Cl
:::l
~
~
8
U
"0
>
I
I -1
>
6
u
u
u
+300
~
+200
e
80
70
co
cr
Q)
-0
U::
+100
en
e
e
e
o
I 60
e
\
.g
........ r-..,
ro
~
-100
Q)
Q)
r--. . . . .
50
~
&(19 kHz )
l"'-
40
I'-
I
U::
o
u
>I
'r--...
0.
30
Q)
-200
....... ~
C/)
20
-300
o
.J
10
o
2
4
6
8
10 12 14 16
Vee - Supply Voltage - V
18
o
o
20
30
Vee = 9V
f = 1 kHz
10
f = 1 kHz
vi = 200 mVr.m.s.
V
0
.;:;
e 10
o
1/
'co
11
ro
:: 1.0
E
o
l-
E
co
:: 1.0
co
o
7
I
'/
3
./
0.1
l-
1/
5
o
3
u
V
§
5
(5
/
3
'co
~
'/
(5
I
/
/
?fiI
20
10
'g
5
3
E
e
co 0
I
I
II III
a
0.;
5
I
3
o
:i
r=
1-0
I
o
:i
0.1
10
1062
e
co 0
I';:;
'iii
1-0
3 5 100
3 5 1k
3 5 10 k
f - Frequency - Hz
3 5 lOOk
o
?fi- 20
I 10
'co
§
]o .-gl.0
\
2
4
6
8
10
12
14
16
18
20
Fig.26 TOTAL HARMONIC DISTORTION
(Stereo)
vs. FREQUENCY
u
.;:;
1
3
Vee - Supply Voltage - V
I II
vee -9V
===
~ Vin= 200 mVr.m.s.
5
0.1
100 200 300 400 500 600 700 800 900 1000
Vin - Signal Input Level - mVr.m.s.
Fig.25 TOTAL HARMONIC DISTORTION
(Monaural)
vs. FREQUENCY
u
\
·E
/
5
u
100
30
?fi-
g
20 30
40 50 60 70 80 90
vi(pilot) - Pilot Input Level - mVr.m.s.
Fig.24 TOTAL HARMONIC DISTORTION
vs. SUPPLY VOLTAGE
(Monaural)
Fig.23 TOTAL HARMON IC DISTORTION
vs. SIGNAL INPUT LEVEL (Monaural)
e
10
r=
j
IIIIIII
=
=
"11111
I
Vee = 9V
~ vj(L+R) = 200 mVr.m.s.
5 I---3 I---- L = 45%,R = 45%
I - - Pilot = 10%
I
1
5
3
~
0.1
10
I
3 5
100
3 5
1k
3 5
f - Frequency - Hz
10 k
3 5 lOOk
,uPC1197C
Fig.27 TOTAL HARMONIC DISTORTION
vs. PILOT INPUT LEVEL (Stereo)
Fig.28 MAXIMUM INPUT LEVEL
vs. SUPPLY VOLTAGE (Monaural)
30
Vee ~ 9V
f ~ 1 kHz
Vi(L+R) ~ 200 mVr.m.s.
L ~ 45%.R ~ 45%
~ 10
o
.;::
f--- pilot ~ 10 %
-
f ~ 1 kHz
T.H.D. = 2 %
;=:
g
5
~
3
'co
,/
/
Vl
E 1.0
/
V
V
E
~
/
E
Cii 0.8
/
ro
I
ro
o
>
OJ
...J
;
0.
I
~
5
q
3
/
v
L/
I
r:
~
C
E 0.6
/
:J
./
-
.Sx
ro
I
~
I
I 0.4
0.1
o
x
ro
20
40
60
80
100
vi(pilot) - Pilot Input Level - mVr.m.s.
E
;S 0.2
o
o
Fig.30
Fig.29 CAPTURE RANGE
2
4
6
8
10
12
14 16
Vee - Supply Voltage - V
18
20
POWER DISSIPATION AND SATURATION
VOLTAGE OF LAMP DRIVER
vs. LAMP CURRENT
80
Vee ~ 9V
v! 70
~
,
:>E
60
I
~OJ
50
\
...J
40
\
>
OJ
\
~
a::
I
I
I
30
V
\
~ 20
§
.;::; 10
\
I
V
, , ,,
~~
o
17.00
18.00
19.00
20.00
21.00
tv eo - veo Free Running Frequency - kHz
....OJ
3.5
>I
o 150
3.0
....0
2.5
-5
~
.2
c;
.~
0.
E
co
...J
'0
§
.;::
co
100
0.
.~
(5
tv
50
~
o
--
_
a..
I
~
0
.,'" V
o
/V
I---- ~
....
V
20
V
V
~ f-- ~
V
40
60
80
/
OJ
c:n
co
2.0
-
1.5
> '':
ro.... Eco
~...J
C/l
1.0
I
...
0.5
~
o
~
100
w
I L - Lamp Current - mA
1063
pPC1197C
Fig.31
VCO FREE RUNNING FREQUENCY
vs. AMBIENT TEMPERATURE
Vee = 9 V
Exclude external parts
N
I
Fig.32 VCO FREE RUNNING FREQUENCY
vs. AMBIENT TEMPERATURE
Vee= 9 V
N
I
~
~
I
>
u
>
u
cQ)
cQ)
1.0
:J
CJ"
1.0
:J
CJ"
Q)
Q)
Lt
0.5
Cl
r-r-
C
.§
Lt
C
r-r-
-0.5
8
a
"§
r- r-t-
~ (19 kHz )
al
Lt
0.5
Cl
r- r- ~
0
~(19 kHz )
al
-0.5
U:
8
-1.0
-1.0
>
>
I
I
o
u
.2
a
-25
50
25
°e
~
I
20
1,.;' ......
9
I,...;
8
7
LAMP ON
...... 1,.;'
"" ....
......
>
Q)
.2
a:...
....... ~
16
E
50
25
Ta - Ambient Temperature _
Fig.33 INPUT PILOT LEVEL (LAMP ON - OFF)
vs. AMBIENT TEMPERATURE
en
a
-25
75
Ta - Ambient Temperature _
.-1- j..--
~ 12
-~-
-
:J
LAMP OFF
u 10
:J
~
U
I
3
.2
u
~
Vee = 9 V
~ 2
8
6
4
.;s
2
o
-25
a
25
1064
75
50
Ta - Ambient Temperature -
°c
o
-25
a
25
50
Ta - Ambient Temperature _
75
°e
APPLICATION NOTE FOR fLPC1277H
EXTERNAL PARTS AND CHARACTERISTICS
1 INTRODUCTION
IlPC 1277H is a dual channel audio power amplifier circuit designed for radio cassette tape recorders.
It
operates in the power supply voltage range of 5 to 16 V and can be used for a vartety of stereo radio cassette
sets.
Th is docu ment explains how IlPC 1277H's external parts change its characteristics.
2 BLOCK DIAGRAM
Figure 1 briefly shows external parts and their effect upon characteristics using a block diagram.
Ripple rejection
Stability
ratio, Rise time,
Shock noise
Low frequency
output
I Nl
Low frequency
0---{)-----I
Low frequency
voltage gain, Low
frequency output
~____
voltage gain
Rise time
Cg T O.068
~-----~~
Shock noise
m
~F
47 J.LF:
I
I
IL
Effect upon
characteristics
Thermal
_ _ _ _ _ _ _ _ _ _ _ -.lI
Stability
Fig. 1 Block diagram
3 VOLTAGE GAIN
IlPC 1277H has a built-in resistor for setting the closed
loop voltage gain as shown in the figure right. Add
a resistor between the feed back terminal and ground
INo------t
OUT
Rf
N F D--"'\IV\,..---
I
v
v--: -::;/ vi-"
40
100 / ~v
30 r-pF
47 pF/
/
20
>
/
~
---
a:J
I--
"0
I
.~
OJ
OJ
e
~/
1000/ /
30 _pF
.-/
./
V
V-
I-f-
1--'-
f--~I -
V
v
v
/
:F=("/
0
470
I
20 220 pF
>
v
>
c..:J
c..:J
10
10
o
10
30
50
f -
100
Frequency -
300 500
1000
Output power is effected by bootstrap capacitor C4
(C5) and output coupling capacitor C7(C8).
By the bootstrap circuit, whose configuration is
shown in the figure right, the output voltage is feed
back to the driver stage resulting that:
Vo (MAX.)=VCC - VCE(02)
Removing C4 (C5) results in:
Vb(MAX.)=VCC- VBE(02)+VBE01+ V C+ V (R*)
to limit the output amplitude and high output cannot
be obtained.
impedance
10
30
50
100
300 500
of
output capacitor C7
(C8)
becomes not negligible, the load current becomes smaller by an amount corresponding to that impedance and
small output is resulted.
Figure 4 shows output power vs. frequency characteristics when C4 and C7 are changed.
1000
Fig. 3 VOLTAGE GAIN vs. FREQUENCY
.----------.------{] VCC
4 OUTPUT POWER
When
o
f - Frequency - Hz
Hz
Fig. 2 VOLTAGE GAIN vs. FREQUENCY
1066
//
40
C\l
c..:J
/
/
10pF
VCC=12 V
RL =47r2
C4=47 pF
R*
,uPC1277H
5
I
~
./
I-C4=1 000 J.LF /
i/
f- C4=10 J.LF /1
~
"OJ
3
-
f-f--
+-'
-
I---
:J
Q.
:;
2
V
IIII
C4=470
C4=100
/
J.L E
'/
II
a..
I
20 30
II
/
/
/
50
/
/
C4=1O J.LF
C7=470 J.LF
I
II
I
/
V
__ T
/"
/
//
VCC=12 V RL =4 n.
/'
/
/
J.L Fj'
I
o
/
/
-.
/"
/
I 1 I
a
a..
0
I
a
1--:::::::
/"
4
I
I
I I I
C4; NULL
C7=470 J.LF
100
300 500
1k
3k
5k
10 k
20 k
f - Frequency - Hz
Fig.4 OUTPUT POWER vs. FREQUENCY
5 SHOCK NOISE AND RISE UP TIME
~__~~--------------------------'-----~~-D#10
VCC
r-----_------47 JJ;/1
C3<'00 JJF /'"
,.",
",
/
"'"
/
/
/
,/
'"
/
1C3=1 00 JJF
/
o
I
o
>
/
>
/
----
/
/
,/
/
I
/
/
I
'"
'"
/
I
/
I
I
/
//
I
,
/ C3>100 JJF,
.v ......
_./
tON - 0.5 s
(C, =47 JJF)
• t
----, t
Fig.5
C,
AND RISE UP TIME
Fig.6 C3 AND RISE UP TIME
6 OTHERS
o Power decoupling capacitor C6, oscillation preventing capacitor and resistor are provided so that pPC 1277H
has stable operations in wide ranges of voltage, 5 to 16 V temperature, -20 to +75 PC, and load, 3 to 8
n.
o Filter capacitor C3 is provided to reduce the ripple voltage occuring in AC power supply. Also, gentle rise
up of this capacitor is, as set forth earlier, utilized to minimize the shock noise.
lOSS
,uPC1350C EXAMPLE OF APPLICATION CIRCUIT WITH
4 Q LOAD AND 0.7 W OUTPUT
DESCRIPTION
pPC1350C is a silicon monolithic integrated circuit developed for uses in cassette tape recorders. The standard operating condition is 6 V power supply and 8
n
load. This IC includes functions of a preamplifier, auto-
matic level control (ALC) circuit, and ITL and OTL power amplifiers. One piece of this IC enables to construct
the amplifier unit of a tape recorder.
This document shows one example of an application circuit with 4 n load.
1. EXAMPLE OF APPLICATION CIRCUIT
Figure 1 shows an application circuit example when used for 4
n load.
REMOTE ON & OFF
~..-..o--- SWITCH JACK
C18
3300 pF
Cg
470/lF
ClOTo.068
"fti'
"F
SP
4n
SW1: REC.lP.B.
(P.B. POSITION)
SW2: AC/DC OPERATION (DC OPERATION)
SW3: Power Switch
(ON POSITION)
Fig. 1 EXAMPLE OF APPLICATION CIRCUIT
1069
jlPC1350C
2. ELECTRICAL CHARACTERISTICS
2-1. ABSOLUTE MAXIMUM RATINGS AND RECOMMENDED OPERATING CONDITIONS
Absolute Maximum Ratings (Ta=25 °C)
Item
Symbol
Rating
Unit
Supply Voltage (D.C.)
VCC1
12
V
Supply Voltage (A.C.)
VCC2
10
V
Circuit Current
ICC(peak)
500
mW
Power Dissipation
Po
2.4 *
W
Operating Temperature
T opt
-20"'+75
°c
Storage Temperatu re
Tstg
-40'" +150
°c
".0':."
*Copper heat sink of 50 mm x 50 mm x 1.5 mm
Recommended Operating Condition (Ta=25°C)
Item
Supply Voltage
MIN.
TYP.
MAX.
Unit
3.5
6
7.5
V
2-2. OUTPUT POWER
2-3. POWER DISSIPATION
pPC 1350C is designed for a tape recorder and it gives
standard output of 0.7 W when its load is 4
T.H.D.=10 %).
n
(Vcc=6 V,
Fig. 2 shows output power vs. supply
Fig. 3 shows power dissipation vs. output power
characteristics.
Refer to this characteristic for thermal
designing.
vo Itage characteristic.
1.0
RL=4n
0.8 ~ f=1 kHz
T.H.D.=1O %
~
I
....
Q)
3:
0.6
0
0-
....:l
B:l
0
OA
I
I
0
0-
7
V
V
V
/
1.0
V
0.8
o
3
,,
V
co
D..
,J
.~
....Q)
3:
004
0
0-
I
,IJ
6
7
8
Vee - Supply Voltage - V
Fig. 2 OUTPUT POWER vs. SUPPLY VOLTAGE
1070
0.6
0
.~
(5
5
I
I---'1-0---
./
I
c
J
4
/~ -----
~
1/
0.2
I
Vcc=7.5 V
V
/
V
V
.
/
,
~
,. l.....-'
r---~6V
~
--
-I'--- I- Vcc=5 V
0.2
o
0.2
004
0.6
0.8
1.0
Po - Output Power - W
Fig.3 POWER DISSIPATION vs. OUTPUT POWER
,uPC1350C
2-4. VOLTAGE GAIN
III11I1
In J,lPC1350C, its pre-amp. stage gain and power amp.
stage gain approximate following equations:
(A) Pre-amp. stage
Gv l
:::~~
RL =4
NAB
"0
I
c
80
c.:J
~
60
·ro
(Used as a FLAT Amp.)
Vcc=6 V
100
--
/-
~
n
1\
o
1
G 1::: R15
V
en
(R9+ R l0)2
Rl0+ WC12R9 w=27Tf
>
40
I
2
::::0
<:J
(Used as an NAB EO. Amp.)
20
o
10
(B) Power amp. stage
3 5 100
3 5· 1 k
3 5 10 k
3 5100 k
f - Frequency - Hz
Fig. 4 VOLTAGE GAIN vs. FREQUENCY
Using the constants of the application circuit example
shown in Fig. 1, the voltage gains are 30.8 dB (F LAT),
IIIII1
30.2 dB (NAB EO. at , kHz), and 46.8 dB (power amp.
stage) respectively.
en
The low frequency characteristics
100
"0
I
are determined by time constants of R7, Cl', R'3, and
c
C 17 in the feed back circu it and C9 and R L in the out-
c.:J
FLAT
80
Namely, low cut-off frequencies fL', fL2,
...... 1"60
Ol
I
~
0
and fL3 are represented by following equations:
>
I-..
~
ctl
(lJ
put circuit.
Vcc=6 V
RL =4 n
40
I
::::0
f
f
c.:J
- --'--L1 - 27TC" . R7
o
10
2---'---
3510031k
L - 27TC 17 . R 13
100 k
10k
f - Frequency - Hz
and
Fig.5 VOLTAGE GAIN vs. FREQUENCY
20
I n the example of the application circuit shown in Fig.
"
20
fL ,:::::50 Hz, fL2::::48 Hz, and fL3:::: 85 Hz. Overall
voltage again versus frequency characteristics are shown
C12.
I
.Q
+-'
in Fig. 4 when used as an NAB. EO. Amp., and in Fig.
5 when as a FLAT Amp.
10
c
II
8en
0
.~
c
I
...........
Fig. 6 shows the total harmonic distortion vs. output
§
I
~
t--..
0
2-5. TOTAL HARMONIC DISTORTION
I
120 Hz
ctl
1.0
-;
'~ '\
1
---l\
t'-
..... 1--...
/
II
'--.
I
II
/'
10 kHz
ctl
power characteristic and Fig. 7, the total harmonic
~
distortion vs. frequency characteristic. This IC is design-
I
ed to have a low total harmonic distortion factor and
it is most appropriate for use in tape recorders.
........
i"'-...
I
0
.............
1
II
1/
1 kHz
I
r-:
Vcc=6 V
RL =4 n
NAB
0.1
2-6. ALC CHARACTERISTICS
0.01
Fig. 8 shows ALC output change vs. input level
characteristics and Fig. 9, ALC output distortion factor
vs. input level characteristics.
It gives ALC range
0.1
1.0
2.0
Po - Output Power - W
Fig. 6 TOTAL HARMONIC DISTORTION vs.
OUTPUT POWER
(wherein distortion factor is 3 % or below) of 60 dB
1071
,uPC1350C
(TYP.) and output change (difference of outputs bet-
vee 6 V
RL 4n
Po=O.l W
NABEQ
c:
ween input levels of -70 and -40 dBm) of 1.8 dB
.Q
(TYP.) when V cc=6 V and R L=56 n.
B
+-'
-8
/
/
-10
-12
-90 -80 -70 -60 -50 -40 -30 -20 -10
Vin - Input Level - dBm
If a lower junction temperature is
Fig.8 ALC OUTPUT CHANGE vs.
INPUT LEVEL
desired, make the area of the printed circuit board with
copper heat sink on TAB part wider, or make the area
of the print board itself larger to reduce Rth (j--a).
",
Output Change
Regien
/
a
Rth(j-a)=55 °C/W, in Fig. 12. Substituting these values
in the equation to obtain the junction temperature,
rrt
U
-.J
'*
10.0
Thus the junction temperature can be lowered.
+-'
,
::J
Note
B::J
o
Rth (j-a) = 90°C/W
Free Air
U
Rth (j-a) = 65 0 C/W
30x30x 1.5 mm with
~
copper heat sink
.g
50x50x1.5 mm
Rth O-a) = 50°C/W
Unit
c:
1.0
~
with copper heat sink
(5
infinitely large heat sink
'c
mm
§
vee =6 V
Rl/= 56 n
f=l kHz
I
~~
ALC Regie •.
\
-.J
\
\
\
,
\
u
o
I
"-
co
J
V
0.1
-90 -SO -70-60 -50 -40 -30 -20 -10
0
V in - Input Level - dBm
Fig.9 TOTAL HARMONIC DISTORTION
(ALC OUTPUT) vs. INPUT LEVEL
1072
100 k
Vec=6 V
RL'=56 n
f=l kHz
Q)
co
..c:
U
and ambience
Tj:::::72 °c is given.
100
5
Fig. 7 TOTAL HARMONIC DISTORTION vs.
FREQUENCY
In heat sink design, refer to Fig. 3, power dissipa-
Tj:
3
f - Frequency - Hz
3. HEAT SINK DESIGN
T a:
-
\
0
jlPC1350C
2.0
4. NOTICES ON DESIGNING PRINTED CIRCUIT BOARD
100
1.6
(1) Since JlPC1350 is a high gain amplifier, design
80
«
m
~
power supply and grounding wires thick to highten
50
,
E
"0
I
I
Vee =6 V
RL =4 n
f=l kHz
NABEQ
40
~
f
L
Gu (P 0=0.3 W)
circuit stability.
'c~ (No Signal)
(2) Although one point grounding is ideal, when it is
t
impossible to realize, take care that the input loop
does not come into the output loop.
I-- -r
Mingled in-
V
put and output loops may cause deterioration of
-
Ipo (T.H.D.=10 %)
---.
the distortion factor and oscillation.
o
(Good example)
Input loop
o-20
0
o
40
20
60
Output loop
80
°c
Ta - Ambient Temperature -
Fig. 10 OUTPUT POWER, VOLTAGE GAIN AND CIRCUIT
CURRENT vs. AMBIENT TEMPERATURE
10.0
Vee
GND
IN
OUT
6V
RL =451
f=l kHz
c
...
.2
a
Po=0.3 W
.~
==
-
o
.~
(Bad example)
c
o
§
Output loop
1.0
III
I
~
r-o
3
---
.....
I
q
I
GND
IN
OUT
r:
0·~20
o
40
20
60
80
100
°c
Ta - Ambient Temperature -
Fig. 11 TOTAL HARMONIC DISTORTION vs. AMBIENT TEMPERATURE
(3) Mount C8: 1 000 JlF (for bypass), C 10: 0.06 JlF
(output oscillation preventing capacitor), and
the
speaker terminal close to TABpin (GND).
2.5
(4) Fig. 13 shows the example of a printed circuit
board.
r-- ""'\. \.
~
I
'r" _ infinitely large
\.,
2.0
5. CAUTIONS ON HANDLING
"
...
.2
III
0.
.~
(1) Output oscillation preventing capacitor C10:0.068
1.5
0
power amp. stage. Select the type of this capacitor
0
1.0
a..
I
"t:1
a..
"
'\.
_ 50x50x 1.5 mm--with copper heat sink
"
,. "
.~
Use a ceramic capacitor or Mylar capacitor
for C, O.
,
I
I
I
I
'"
heat sink
"""
",
'"
'\.'\.
"0.5
=
mm
:\..\. with copper-
-"
-FreeAir'
according to the set in which JlPC 1350C is used.
(A) When used for a cassette tape recorder:
1
'\. ~ 30x30x 1.5
L~
f---
,,
\.
\.\.
'\.
."-
Q)
3:
~
~
'-
JlF
This capacitor is for preventing oscillation on the
i
\.
r-- ~
I
heat sink'
\.
c
I'-\.
I'o...~
....
"\:"
o
o
25
50
75
100
125
150
T a - Ambient Temperature -
°c .
Fig. 12 POWER DISSIPATION vs.
AMBIENT TEMPERATURE
1073
,uPC1350C
2 pin
77.5
2 pin
--t~++-.:;
(NAB)
. GND
GND
'NEe
PoOUT
Vee
Fig. 13 PRINTED CIRCUIT BOARD
(B) When used for radio cassette tape recorders:
The 5th terminal of J,LPC1350C is the DC bias
capacitor is used, unnecessary radiation emit-
terminal for the erasing head and the 12th terminal
ted from the capacitor may return to the R F
stage of the radio.
(2) Recovery time during recording
is the DC bias terminal for the recording head.
(5) When the power amp. stage only is used.
In that case, connect the input terminal (13th termi-
Recovery time is determined by the time constant
nal) of the pre-amp. stage to GN D through a capacit-
of the circuit in which capacitor C2, input resistor
or. If the input terminal of the pre-amp. stage is left
to IC's 13th terminal, and R4 are connected in
open, oscillation may occur to worsen the power
parallel and is changed by varying R4: 1 Mn.
amp. stage characteristics.
(3) TAB
Since TAB of J,LPC1350C is GND within the IC, be
sure to solder it to GND of the printed circuit
board.
1074
(4) Bias terminals
Use a Mylar capacitor for C10. If a ceramic
,uPC1350C
The 4
n
load application circuit of J1PC1350C is explained in the preceding sections. Besides what are set
forth there, this IC is designeci so that it has low output shock noise at power on/off and it is durable against
electrostatic breakdown. Therefore, this IC can fully be used as an amplifier for a cassette tape recorder.
1075
APPLICATION CIRCUIT OF ,uPD 1 701 C-O 13
DESCRIPTION
The J,lPD1701 C-013 is a CMOS LSI designed for use in Phase Locked Loop Frequency Synthesizer Digital Tuning
System, which consists of PLL, swallow counter and system controller.
The J,lPD 1701 C-013 provides full electronic control of var2ctor tuned FM/AM radio receiver with clock function.
NEC's original pulse swallowing method is applied to FM band in conjunction with J,lPB553AC, so that high
reference frequency results in good signal-to-noise ratio. The J,lPB553AC is a VHF two-modulus prescaler which
provides 1/16 and 1/17. division ratio. Advanced bipolar process technology is utilized to realize high frequency
operation with extremely low power consumptions.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1076
PLL, swallow counter and system controller are realized in a single chip.
Occupation of minimum mounting area in P.C. Board due to 28 pin slim DIP.
High speed and low power consumptions due to CMOS.
Very low stand-by current ........ 100=0.5 mA (TYP.)
Single power supply voltage ....... VDD=5.0 V ± 10 %
FM and AM bands . . . . . . . . . . . . . Japan and U.S. bands
External programmable I F offset for FM band.
Japan band . . . . . . . . . . . . . . 10.675,10.700,10.725,10.750 MHz
U.S. band . . . . . . . . . . . . . . . 10.650, 10.675, 10.700, 10.725 MHz
External programmable I F offset for AM band.
Japan band . . . . . . . . . . . . . . 450/261 kHz
U. S. band . . . . . . . . . . . . . . . 450/260 kHz or 450/261 kHz
High reference frequency. It results in good signal-to-noise ratio.
FM band . . . . . . . . . . . . . . . . 25 kHz
AM band . . . . . . . . . . . . . . . . 10 kHz or 9 kHz
Four station selection modes are available.
(1) SCAN (Automatic audition) of available program.
(2) SEE K (Automatic search and stop) for FM and AM.
(3) UP or DOWN manual tuning to any station by single stepping or sequencing With momentary
switches or endless-rotary switch.
(4) Favorite station programming of 6 FM and 6 AM stations for pushbuttons selection.
Ample time correction modes are available.
(1) Hour fast shift (HA key only or ME key and MD key)
(2) Minute fast shift (MA key only or ME key and MU key)
(3) One touch setting to correct tim·e (OAD key: ±30 minutes zero reset)
Two stage switching of display brightness (duty cycle: 25 %)
Two independent frequency input terminals are provided for both FM and AM bands.
Two independent error-out terminals are provided for both FM and AM bands.
Direct interface to the FM two-modulus prescaler J,lPB553AC.
Automatic power-on clear without any external components.
Internal display decoder for 3.5 digit multiplexed display.
j1PD1701C-013
1. SYSTEM DESCR IPTION
NEC's Digital Tuning System provides full electronic control of a varactor tuned FM/AM radio receiver and
stereo. The block diagram of the system is shown in Fig. 1. This is a Phase Locked Loop Digital Tuning System
which consists of two integrated circuits; controller plus PLL in a single chip, and two-modulus prescaler.
The controller chip (J.,LPD1701 C-013) provides Phase Locked Loop capability witjl on-chip frequency division, a reference oscillator whose frequency is controlled by an external trystal of 4.5 MHz, and phase comparator circuitry. It accepts directly an AM local oscillator signal and an FM signal from two-modulus prescaler
(J.,LPB553AC), and outputs control signals for closed loop operation of these oscillators. The outputs drives filters
for supplying analog voltages to the vari-cap tuners. The controller also provides the signals to drive the display.
The frequency of the tuned station is displayed on a 3.5 digit multiplexed display. Six favorite stations on each
band can be stored as well as "last stations tuned" information.
J,lPD 1701 C-013
-
MUTE
MUTE
FM
TUNING
AM
TUNING
01
FIL TER
-
V'
05
E01
ACTIVE
t-------
DIGIT
~
5
DRIVERS
~~
E02
DISPLAY
J,lPB553AC
FM/AM
FM
OSC.
PRESCALER
FM
t
PSC
11
RADIO
AM
OSC.
SEG.A
SEG. G
7
r--
~
SEGMENT
r--V
DRIVERS
AM
--
STATION DETECTOR
4.5 MHz
1
1
SO
{1
X1
KO
KEY and SWITCH
A
:: K...
c:::J
crystal
4
MATRIX
K3
X2
Fig. 1 Block Diagram
2. PIN CONNECTION (Top View)
The pin connection of the J.,LPD1701 C-013 is shown in Fig. 2.
AM
K3
GND
a
b
c
01
02
d
e
9
J,lPD 1701C-013
E01
E02
CE
PSC
X1
X2
SO
Fig.2
1077
,uPD1701C-013
3. CONTROL KEY AND MODE SWITCH MATRIX
The operation of the system is controlled by a 4 x 7 key and switch matrix (15 momentary switches, 5 alternate switches and 7 initial switches). Various functions are entered through the matrix. The configuration of
the matrix is shown in Fig. 3.
SEG.A
SEG.B
SEG.C
SEG.D
SEG.F
SEG.E
SEG.G
KO
Kl
K2
K3
o:
o:
momentary key.
alternate switch
6.:
diode switch
Fig. 3 Control Key and Mode Switch Matrix
4. SWITCHING-OVER THE DISPLAY BETWEEN RADIO AND CLOCK
Display mode control switches A, S, initial switch P and control key ReAL control the display mode as
follows.
* 1:
*2:
1078
MODE
A
S
Display
Priority
Enable keys and switches
0
ON
ON
Frequency
or time
None * 1
All keys and switches
1
ON
OFF
Frequency
or time
Frequency *2
or time
All keys and switches
2
OFF
OFF
Time only
-
HA, MA. and OAD keys
A, S, and DIM switches
3
OFF
ON
Disabled
-
A and S switches
A momentary depression of ReAL key causes alternate display change between frequency and time whenever it is performed. Whenever frequency is handled. frequency is displayed.
P=ON
Frequency is prior to time. A momentary depression of ReAL key causes alternative display change. When
frequency is displayed, a momentary depression of ReAL key recalls time on the display and it remains
there for 5 seconds. If any other key is handled when time is displayed, handling of one of the time setting
keys (HA. MA and OAD) keeps the time display. the display turns back to frequency automatically 5
seconds after the time setting is completed. Whenever frequency is handled, frequency is displayed.
P=OFF
Time is prior to frequency. A momentary depression of ReAL key causes alternative display change. When
time is displayed, a depression of ReAL key or one of the frequency handling keys recalls frequency on
the display for 5 seconds. After that, the display turns back to time automatically.
,uPD1701C-013
5. APPLICATION EXAMPLE OF A SWITCH AND B SWITCH
This section describes connection diagram of power supply source of radio unit, display drivers and control
unit, and application example of A switch and B switch, and state diagram of each application example.
There are two kinds of applications. One kind of applications use DPDT (Dual Pole Dual Transfer) switches.
The other one use DPTT (Dual Pole Triple Transfer) switches. One of two poles is used to control power supply
source, and the other one is used to control A switch and B switch.
Each state of the state diagram is shown as follows.
OFF
: Disabled
F R EQ : Frequency is displayed.
TIME : Time is displayed.
l
MUTE terminal
Low level
1 : High level
o : High or
1
A, B SW }
1 : on
O:off
Enable keys and switches
1 : All keys and switches *
2 : All keys and switches except HA,
MA, and OAD keys *
3 : HA, MA, and 0 AD keys, A and
B switches
4 : A and B switches
X: Disabled
Fig.4
* Except initial switches
1079
j.lPD1701C-013
Time display priority method-1 (Using DPDT SW)
Condition : B SW=off (OPEN)
P SW=off (OPEN)
Radio ON
Radio OFF
Ace
Ace key
kr
OFF
Pow. SW
~n~~~~__~----~------CE~V)
(+12 V)
(/
F14C
VDD
(-15
VI
I
I
I
I
A SW
~L....-_~/o_ _ _ _ _ _~_I_______:__ ::
__
Fig. 5
1080
1SS53
,uPD1701C-013
Time display priority method-2 (Using DPDT SW)
Condition : B SW=off (OPEN)
P SW=off (OPEN)
Acc key ON
Acc key OFF
Acc key
Battery
(+12 V)
1
r
ere
("
F14C
I
1SS53
I ~------r~.------~:~::
Voo
(+5 V)
ASW
~""'II
CE (+5 V)
Fig.6
1081
,uPD1701C-013
Time display priority method-3 (Using DPTT SW)
Condition : P SW=off (OPEN)
Acc key ON
Radio OFF
SW 1
A~1
Ace key
Battery~
(+12 V)
F14C
(
R05.1EB
VOO
(+5 V)
CE (+5 V)
03
1SS53
I
~o_12-::::""'::::-:-:~__--1:a!-:----4:_~:
Fig.7
1082
,uPD1701C-013
Frequency display priority method-1 (Using OPOT SW)
Condition : B SW=off (OPEN)
P SW=on (CLOSE)
Acc off
Radio ON
Acc key ON
Radio OFF
Acc key OFF
1
Pow. SW
Acc key
~~~~O~~~~~-~~~~~~~~~~~~~~~~~~~-CE(~V)
('
F14C
I
I
I
VOO
(+5 V)
A SW
~
lSS53
o--------------~.~t-I------------~:-
~_~_~______________________________________.~
sKe3
Fig.8
1083
,uPD1701C-013
Frequency display priority method-2 (Using DPDT SW)
Condition : B SW=off (OPEN)
P SW=on (CLOSE)
Ace off
Radio ON
Acc key ON
Radio OFF
Acc key OFF
I
Acc key
Battery~
(+12 V)
('
F14C
o--------------~
: A SW
VOO
(+5 V)
CE (+5 V)
1SS53
~----~.~1----------~:-:3
Fig.9
1084
Radio
Unit
Pow.SW
,uPD1701C-013
Frequency display priority method-3 (Using DPTT SW)
Condition : P SW=on (CLOSE)
Ace off
r
Ace key ON
Ace key OFF
SW2
-r.
A+-O
Ace key
Battery
(+12 V)
F14C
VOO
(+5 V)
R05. 1 EB
CE (+5 V)
03
I
Il
~,
~,
1 SS53
----II:w.--_>s:3
ASW
o°..:.:.--l
B SW
:'
1
1
......
K
:
Fig. 10
1085
,uPD1701C-013
Display priority switching-over method (Using DPDT SW)
Condition : B SW=on (C LOSE)
P SW= Don't Care.
I
Acc off
~------------~--~----4
Radio ON
Ace key ON
Radio OFF
»
»
(')
(')
(')
(')
o
o
::3
::3
Aee key OFF
Battery
(+12 V)
Acc SW
11
F14C
VOO
(+5 V)
Pow. SW
r'
I
I
~------~----------~----------~ CE~5V)
A SW
,-E_~~
__o_ _ _ _ _ _ _~_,_ _ _ _ _ _ _ _:_. ::
Fig. 11
1086
1SS53
,uPD1701C-013
6. DISPLAY INTERFACE
The J,lPD1701 C-013 provides 5 digit outputs (01 to 05) and 7 segment outputs (Seg a to Seg g) for display
of frequency or time. Mode informations are provided from segment outputs at the timing of 01, and frequency
or time (numerical) informations at the timing of 02 to 05. I ncorporated display decoder allows the display
to be driven by simple current buffers.
The outputs for display are active high for both segment outputs and digit outputs.
~uts
Digit Outputs
a
b
c
d
e
f
g
-
-
Mode Digit
Note
01
AM
PM
FM
DP
02
A
B
C
0
E
F
G
LSD
03
A
B
C
0
E
F
G
2nd Digit
04
A
B
C
0
E
F
G
3rd Digit
05
-
B
C
-
-
ME
-
MSD.
COLON 1 COLON 2
1--.
6-1. DISPLAY FOUNT
When the segment outputs and digit outputs are connected as Fig. 13, a display fount as shown in Fig: 12
will be obtained.
I-I
I_I
Fig. 12
6-2. MODE IN FORMATIONS
The mode informations are used to indicate AM, PM, FM/DP, COLON 1, COLON 2 and ME.
Mode
Description
AM
The morning (When time is displayed) or AM band (When frequency is displayed)
PM
The afternoon
FM/DP
FM band and Decimal Point
COLON 1
Not blinking colon
COLON 2
Blinking colon
ME
Memory enable (It is able to preset station to memory when frequency is displayed)
1087
pPD1701C-013
6-3. AN APPLICATION CIRCUIT OF DISPLAY
Fig. 13 shows an application circuit of display using 7 segment LED (cathode common type).
~
r---
01
1:
I-- I--
02 I-- I--
-0
»
(]1
VJ
()
03 I-- f - -
0
;,:
cO'
=i ~
<'
04 I-- I--
0
"0
05 I-- f - -
<
roO
r---
~
~
77
B
C")
9
u
0
I'-
~
0
0-
::t
+5 V
--
0
0
a ~
b
j
u
(1)
1:
d~
»
e --vw-
()
9
-I
0
to
C --"NY-
f --/\Mr-
0
Cf)
f--'vvv-0
(]1
0)
3(1)
~
~
<'
~
VI
--'IIItv-
b
Fig. 13 An Application Circuit of Display
1088
0
N
z
1
I-,
, ,-, , I
, ,-I I-I
0-
0
I-I
FM
ME
,uPD1701C-013
7. CRYSTAL RESONATOR
The oscillation circuit of the J,lPD1701 C-013 is of the single stage CMOS inverter type, and a crystal resonator
of 4.500 000 MHz nominal frequency is connected between the input (X 1 ® pin) and output (X2 ® pin) of the
oscillator stage. As properties required of a crystal clock oscillator circuit, low current consumption, low oscillation starting voltage, small frequency variation, etc. can be mentioned. In general, the current consumption will
become less, the smaller the equ ivalent series resistance (R 1) of the crystal resonator, and the smaller and equal
are the gate and drain capacitors, CG and CD. However, in practice it is necessary to make either CG or CD a
variable capacitor, since the oscillation frequency will deviate from the desired value due to deviations in the
capacitor of CG and CD, the frequency of the crystal resonator, and the stray capacity of the oscillator stage of
the J,lPD1701 C-013. As a condition to reduce the oscillation starting voltage, CG and CD should both be less than
30 pF, the oscillation starting voltage becoming minimum when CG and CD are within a range of 10 to 25 pF.
The oscillation frequency will be stable against variations of voltage and temperature, when stable components
are used for the series resistor (R 1) and CG and CD. An optimum crystal should be selected by giving consideration to the above matters. An example is given following.
Nominal frequency
4.500000 MHz
Type
HC-18/U
± 20 ppm
Frequency deviation
less than 70 n
Equivalent series resistance
12 pF
load capacitor (Cl)
X2
X1
22pF
CD
J----o
Test Point
{ 1 000 pF ~
Fig. 14
8. POWER SUPPLY VOLTAGE
The operating voltage range of the J,lPD1701 C-013 is 4.5 to 5.5 V, and is lower than the 12 volt battery
systems of most automobiles. Therefore, it is necessary to connect a voltage regulator (J,lPC78M05, etc.) between the VDD terminal ( @ pin) and GND terminal ( @ pin), in order to prevent a voltage of over (-0.3 to
+6.0 V) being applied.
108S
o
~
•• -
to radio or TV
1101
,uPD832G SERIES
10·9 Display on alarm sign (How to be unused COM terminal)
The "cock" mark in the LCD stands for the sign of "DAI L Y ALARM." When this mark to be flashed at a
1 Hz rate is visible, alarm is available everyday at the pre-set time.
(i)
Turn off alarm output solely when the "cock"
mark is invisible.
In this case, the sleep output and control
output can be utilized even if HO LI DA Y.
",PD832G Series
(ii)
Turn off not only alarm but also sleep and
control output.
",PD832G Series
dot (1 Hz) (O}----...-l-4-l
VEE
piezo electric buzzer
1.5 V:s,vDD-VEE$.6.5 V
: This is the sign of "DAI L Y ALARM" armed
with alarm and is flashing at a 1 Hz rate.
()
()
: The COLON is flashing at a 1 Hz rate.
[NOTICE] 1. When is displayed the ALARM mode, the sign of "DAI L Y ALARM" is frozen. That condition is ( ~).
2. This circuit is suitable for the "M" product of J.lPD833G that has not COM signal terminal.
(But is provided the integrated Voltage Tripier.)
1102
j.lPD832G SERIES
10-10 How to be extended the duration of sleep timer output.
When the B button is pushed momentarily, the sleep output is activated. But in case of extending the duration
of Sleep timer output while the sleep output, has to be pushed the B button in the following circuit.
IlPD832G Series
Switch on the B button
relay
64 min.
SLP OUT
B
____
'\
I
~rl~:--------~---------I
I
I
}
NORMAL
64min.
I
SLP OUT
----~
L}
100 V AC
B
Vss
......_------
In Cilse of
extending
the duration
of sleep timer.
[The duration of sleep timer is 64 minutes.]
[NOTICE] 1. In case of this, it is not used the Snooze function.
2. When the CNT OUTPUT is activated, it is avai lable to be extended the duration of the control
timer by pushing the B button.
3. Whenever is pushed the B button, it can be renewed the duration of the sleep timer. It will be
started the Sleep timer when is switched off the B button.
1103
,uPD832G'SERIES
10-11 How to apply Lithium battery to pPD832G Series
A
M
&
b3 a2 1393 b2a2 1292 b, a, I, 9, B
CNT OUT
SLP OUT
CIN
FS
FM
CIP&DC
C,=O.'IJ
+
FH
DUT
VDD
STW
ALS
SEC
SNZ
ACS
SCI
Switch B
ALM OUT
c3 d3 e3 c2 d2 e2 d CJ d 1 el h P C
& M 0
a
t
1
Hz
C &M
560 k
A
D
E
G
* N.C. (in case of IJPD833G)
50 k
c::r
a
~
Piezo electric buzzer
~
[NOTICE] After lithium battery (+3 V) is connected to VAA - VSH, it should be pushed momentarily on by
switch B.
1104
,uPD832G SERIES
Lamp to light LCD
to
r----------------- "' ,
,,
I,
,
o------'l/V\r---II>t----,
3 Volt type LCD
SN Z _ _---'-"1"--'-----_
IlP D832G Series
;'
/
o
300
DUAL TIME
r----------.-......
I
/
,
STOP WATCH//
I
I
ALARM & CONTROL
/
r--------- - - - - - 300
I;
-,
, .----f----t----+--<
I
B MEMORY
I
;'
I
r--------,
SEC
/
=d~
,
//',
I
'
,,
~_----<~_ _- - l
piezo electric buzzer
,,
300
light emitting diodes
SR 503Dx6
1,50011
2B2DM
+
rv
AC6 V
1------"
0.001 - 0.0068 IlF
*
Capacitor for absorption of surge cased by power transformer when AC-line is turned on or off necessary 0.01
to 0.68 pF.
1105
HOW TO USE /LPD 1 990AC
TIME KEEPING LSI FOR MICROCOMPUTER SYSTEM
INTRODUCTION
The conventional time keeper for ECR or microcomputer system is a one-board clock built with various counters,
logic gates and flip-flops for TTLs, and MaS MSls. Because this one-board clock is required a wide space for mounting and a large amount of power in the system, it has difficulty in functioning as a battery-operated clock stably for
a long time when the system power supply is turned off.
Recently, a one-board time keeper using the LSI, named ,uPD1990AC, has attracted notice.
This time keeper ,uPD1990AC is a one chip LSI and consumes a very small amount of power. It is suitable for a
long battery operation when the system power supply is turned off. The ,uPD1990AC is an easy to use I C controlled
with 3 bit commands.
Since the ,uPD1990AC has N-channel open-drain outputs, the interface between the ,uPD 1990AC and the system
can easily be formed.
This manual describes the',u PD1990AC CMOS LS I best suited for the establishment of clock functions in
microcomputer systems.
1106
,uPD1990AC
TABLE
1.
2.
3.
4.
OF CONTENTS
OUTLINE OF jlPD1990AC
1-1.
Features
1-2.
Package dimensions and connection diagram
1-3.
Block diagram
1-4.
Absolute maximum ratings
1-5.
Electrical and AC characteristics
1-6.
Command
1-7.
The correspondence of the data between the 40 Bit Shift Register and the Time Counter
1-8.
The form of loading and reading the data
1-9.
Input circuit and output circuit of jlPD1990AC
COMMAND DESCRIPTION
2-1.
Register control modes. [Group "0"]
2-2.
TP (Timing Pulse) Control mode and TEST mode [Group "1"]
SOFTWARE FOR jlPD1990AC
3-1.
How to read out the Time Data from jlPD1990AC
3-2.
How to set the Time Data to jlPD1990AC
INTERFACES FOR jlPD1990AC
4-1.
Crystal oscillator circuit
4-2.
Power supply circuit
4-3.
Interface for output terminal
4-4.
Interface for input terminal
4-5.
Interface for CS terminal
4-6.
Example of application circuit
1107
,uPD1990AC
1. OUTLINE OF J-lPD1990AC
The J-lPD1990AC is an IC that supplies time data serially to a system using microcomputers and the like.
Time data consists of 40 bits of month, date, day of the week, hour (24-hour system), minute, and second. Month
data is expressed in hexadecimal (1 through C) and other data, in BCD (Binary Coded Decimal).
Time data is serially input and output in synchronized with the external clock applied to the ClK terminal.
The operation of the J-lPD1990AC is controlled with commands of 3 bits (CO,. C1, and C2) each. These
commands are divided into two groups: O-group commands to control the input and output of time data and
1-group commands to select timing pulses and test mode.
The supply voltage is VDD-VSS=2.0'"'-'5.5 V. When using two commercially available batteries {UM-1 , UM-2,
UM-3, UM-4, UM-5, or silver oxide), a supply voltage of 3.0 V is obtainable. The use of two Ni-Cd batteries
(possible to charge) gives a supply voltage of 2.4 V and that of three Ni-Cd batteries gives 3.6 V. Using these Ni-Cd
batteries, the J-lPD1990AC will be worked semi permanently. This means system power-fai lure never affects the
time keeping· and in addition, there is no need for battery replacement. Thus, it can be said that the J-lPD1990AC
is the most suitable time keeper for system.
The J-lPD1990AC is in the form of 14-pin DIP (Dual In-line Package).
1-1.
1108
Features
o Time data:
Month, date, day of the week, hour, minute and second
o Data format:
BCD (only month is expressed in hexadecimal using 1 through Co)
o Data input and output system:
Serial transmission system synchronized with external clocks applied through
ClK input
o Timing pulse output:
Either 64 Hz, 256 Hz, or 2048 Hz can be selected according to programs.
o Multi-chip structure:
Multi-chip structure is possible by chip selection (CS)
o Crystal oscillator:
A crystal oscillator with a standard oscillation frequency of 32.768 kHz
J,lPD1990AC
1-2. Package dimensions and connection diagram
CONNECTION DIAGRAM (Top View)
PACKAGE DIMENSIONS
in millimeters (inches)
I
VDD (+)
19.4 MAX,
I
XTAl
IJ
xx
««
Co
XTAl
STB
4
CS
5
11 OUT ENBl
TP
DATA IN
DATA OUT
22
LDOO
GND 7
(VSS)
<::i .-. ..l.----.--_
.9
N
Fig. 2
(V)
M ...-,
o
ClK
2.54
(0.100)
Fig. 1
NO.
Terminology
NO.
Terminology
1
C2
2
C1
3
10
TP
4
Co
STB
11
OUT ENBl
5
CS
12
XTAl
6
DATA IN
13
XTAl
7
GND (VSS)
14
VDD (+)
8
9
ClK
DATA OUT
1109
j.lPD1990AC
1-3.
B lock diagram
OUT ENBl 0
ClK
'OJ
DATA
IN
40 Bit Shift Register
ClK
..
N-cha nnel
Open Drain
Multiplexer
r---'""I
SO
PS
~
~
:--
........ :-GNO
l.-
DM
PS
I I,
L-~
Month
I
I--
~
PSPS
Date
Hour
Min
I
I
I
t--
1 Hz
'---
,---r--rI--rr- -.,...
32
64
256
2040
TEST
r---
c2v
c 1'-'"
J
\
COMMAND
latch/Decoder
)
STB
=
-
Multiplexer
N-ch annel
Ope n Drain
J
I
GND
v
CS...,.
fosc
Hz
Hz
Hz
Hz
~
--
CO~
1
GNO(VSS)
32.768 kHz
VDD = 2.0 to 5.5 V
1110
~~
15 Stage Binary Divider
I~
lO
sr'
Time Counter
OSC
-
•I
I
-
l'"'
I
Fig. 3
1
VDD(+)
SO
Serial Data
PS
Preset
D/W
Day of week
CS
ChipS elect
TP
Timing Pulse
tLPD1990AC
1-4.
1-5.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
VOO-VSS
Input Voltage
VIN
6.0
V
V
VSS-0.3 to VOO +0.3
Operating Temperature Range
Topt
-40 to +85
DC
Storage Temperature Range
Tstg
-55 to +125
DC
Output Termi nal Voltage
VOUT
6.0
V
Electrical and AC characteristics
ELECTRICAL CHARACTERISTICS 1.
= 32.768 kHz, CG = CD = 20 pF, Xtal RS = 20 kn, Ta = 25
(f
CHARACTERISTIC
SYMBOL
TYP.
MIN.
Operating Voltage
VOO-VSS
Current Consumption
ISS
Low Level Output Current
IOL
*500
CLK Input Frequency
fCLK
DC
Input Leakage Current
liN
High Level Input Voltage
VIH
Low Level Input Voltage
VIL
VSS
Oscillation Starting Voltage
VSTA
2.0
2.00
20
0.8 VOO
MAX.
UNIT
DC)
TEST CONOITONS
5.50
V
50
Il A
VOO-VSS=3.60 V
IlA
VOO-VSS=2.0 V
VOL =0.4 V
100
kHz
VOO-VSS=2.0 V, Duty 50 %
1
IlA
VOO-VSS=3.60 V
VOO
V
0.2 VOO V
V
TSTA= 10 s
* TP and DATA OUT are N-channel open drain output.
A.C. ELECTRICAL CHARACTERISTICS (FOR REFERENCE - - - NOT SPECIFIED)
(f
CHARACTER ISTIC
= 32.768
SYMBOL
MIN.
kHz, VDD-VSS
TYP.
= 2.0
MAX.
V, Ta
UNIT
CO"-'2, CS - STB Set-up Time
tsu
2
Il S
STB Pu Ise Width
TSTB
2
Il S
CO"-'2, CS-STB Hold Time
THLO
2
J1S
STB LATCH Delay Time
td1
CLK-OATA OUT Delay Time
tdc-o
DATA IN Set-up Time
tosu
2
J1S
DATA IN Hold Time
tOHLO
2
J1S
= 25
DC)
TEST CONDITIONS
*4
Il S
except Time Read mode
2
J1S
R L=33 kn, C L= 15 p F
* Note: When group 0 is Time Read mode, STB LATCH delay time is 40 IlS MAX. (td2).
I I I I
jlPD1990AC
1-6.
Command
REGISTER CONTROL MODE GROUP [Group 0]
C2
=0
MODE & COMMAND
REGISTER HOLD
REGISTER SHIFT
CODE
C2 Cl CO
a
a
a
a
FUNCTION
a
Data of 40 Bit SIR are not shifted, and data is held.
The TEST MODE is released by this command.
1 Hz
1
Data of the 40 Bit SIR can be shifted to Data OUT
term inal and the external data can be shifted to the
40 Bit SIR, each synchronizing with a clock input
at the ClK terminal.
lSB = a or 1
lSB
0.5 Hz
TIME SET
a
1
a
Data of the 40 Bit SIR are not shifted. The TIC is
kept to transfer data from the 40 Bit SIR and the
11 - 15 stage remains reset. Set a command (ie.
000, 001, all ) besides this command ,to start TIe.
TIME READ
a
1
1
Data of 40 Bit SIR are not shifted. Data of the
TIC keep to transfer to the 40 Bit SIR.
note
DATA OUT
= a or 1
SIR: Shift Register
TIC: Time Counter
Only to change TIME READ mode to another mode, the time to be changed another mode has to need
40 J.1s MAX. (=td2) from the rising edge of STB pulse for setting a new command.
TP CONTROL MODE AND TEST MODE GROUP [Group 1]
C2
=1
MODE & COMMAND
FUNCTION
TP = 64 Hz
1
a
a
TP terminal is the 64 Hz output.
TP = 256 Hz
1
a
1
TP terminal is the 256 Hz output.
TP = 2 048 Hz
1
1 a
TP terminal is the 2 048 Hz output.
1
In this mode, TP terminal is the 32 Hz output. The TEST
MODE is released by TP MODE (100,101,110) or REGISTER
HOLD MODE (000).
When is released by MODE (000), TP terminal is 64 Hz output.
TEST MODE
1112
CODE
C2 Cl CO
1
1
,uPD1990AC
1-7. The correspondence of the data between the 40 Bit Shift Register and the Time Counter.
DATA IN
8#4
8#3
8#2
8#1
DATA OUT
8#0 t-----.
t !.,.-------___-_
___ .J '--.-J
'__ _ _ _ _ _ _
--,/
-~
_ _ J ).'---'~'__ _ _ _ _ _ _ _ _ _
r-----------
__________ J
---..,---..
,...----------y
'(
----------,
- - - - -_____
--"\ l
_
-J
'__ _ _ _ _ _ _ _ _ _ _
~
---------~ ~
,-----,
,--------___ ..J'__.JI..'__
_ _ _ _ _ __
~'__
,-----,
,---------
~"'>___.J!..~ _ _ _ ../'\..._JI..~ _ _ _ _ _ _ _
STB
ClK
DATA IN
'-----I~-----
----------
Seconds/Units---+----Il-----+-----Month----oI----Il---tdl
INTERNAL
MODE OF
J,lPD1990AC
--+-"---td 1
REGISTER SHIFT MODE
Note: tdl = 4 J,lS (Delay time)
-.j...-4.-tdl
TIME SET
REGISTER HOLD
Starting point
for time count
1121
,uPD1990AC
4. INTERFACES FORpPD1990AC
The following is the Block diagram interface between pPD1990AC and CPU SYSTEM.
(1)
Crystal oscillator circuit
(2)
Power supply circuit
(3)
Output interface
(tl)
Input interface
(5)
CS interface
APPLICATION CIRCUIT
CPU SYSTEM
C2
,-----,
f--'
Cl'
I
INPUT
c:::::J
T
Co
'-1.1 CD
.'"
INTER- I - - - - -..... STB
FACE
1 - - - - - - 4 DATA IN
DATA IN
J
ClK
1------1
I
OUT ENBl
Cl K
-,-t - - - - - - I OUT ENBl
r - Ii
j
i
DATA OUT
GND
.l •. -
Cl
STB
VCC
t----.____-tl ~ 30 pF
t - - - - - - I C2
I
Co
32_768 kHz
J..LPD1990AC
I
TP
i
I---~
OUTPUT
INTERFACE
DATA OUT
I
1---,
TP
L _---1·
CS I - -
VDD
GND
r:----,I
+5 V
I
---+----+--_--~
POWER
SUPPLY " 1 - - - - - - - - - - - - '
~I~~
COM __---~-4_------------------~-_r---~
7i7
r-----l
L----J
I
L
!t-----------I
_ _ _ _ _ .J
CS
CIRCUIT
Fig. 4
1122
5-30pF
,uPD1990AC
4·1.
Crystal oscillator circuit
The oscillator circuit of the IlP01190AC is of one-stage CMOS inverter system, incorporating a feedback
resistor for bias. A crystal oscillator of nominal 32.768 kHz is connected between Xtal (13th pin) and Xtal (12th
pin).
A CG=about 30 pF capacitor is connected between Xtal (13th pin) and VSS (GNO) and a CO=5--30 pF trimmer
capacitor, between Xtal (12th pin) and VSS (GNO). Crystal oscillator frequency deviation and variation in
capacitor CG and floating capacity at the oscillating stage cause a discrepancy between the actual and nominal
osci Ilation frequencies. To adjust this, the Xtal (12th pin) capacitor uses a variable capacitor.
Crystal Oscillator Circuit
5--30 pF
Fig. 5
4·2.
Power supply circuit
Originally, the time keeper ought to continue to count the time accurately even though power fails or its AC cord
is misremoved from the socket outlet or the system power is turned off. From this point of view, the power supply
circuit of the jlP01990AC must be of battery-backed up type.
The jlP01990AC can use a battery of any type as a power source if its voltage is in a 2.0 through 5.5 V
operating voltage range.
For reference, the following shows a example of circuit using Ni-Cd batteries (easy to charge).
POWER SUPPLY CIRCUIT
+5
v
2SA733
(VCC)
to VDD of J,LPD1990AC
SYSTEM POWER
SUPPLY
15 kn
4.7 kn
Ni-Cd
X3
GND
Fig. 6
1123
tl PD1 990AC
SYSTEM POWER SUPPLY = "ON"
pPD1990AC is operated by System Power Supply (about 5 V).
SYSTEM POWER SUPPLY = "OFF"
pPD1990AC is operated by about Ni-Cd batteries (about 3.6 V).
4-3.
Interface for output circuit
The output circuit (DATA OUT and TP) of the pPD1990AC has N-channel open-drain outputs as shown.
To form an interface with the system, insert a pull-up resistor, Rpu, between the system power supply Vce
and the output terminal.
Notice that a low-level output current of IOL ==(VCC-VDS)/Rpul/RS (PA) flows in accordance with Ohm's
law.
Decide the pull-up resistor value Rpu so as to balance it against the low level output current and other conditions.
Vee
Vee (System Power Supply)
Vee
Voo
RS
OATA OUT
TP
SYSTEM
VSS
J.LP01990Ae
epu SYSTEM
Fig. 7
1124
J1,PD1990AC
4-4.
Interface for input circuit
(a)
Terminals of C2, C1, CO, ClK, DATA IN, and OUT ENBl
To form an interface with the system, insert a pull-up resistor Rpu between the system power supply
VCC and the input terminal.
Vee (+5 V)
Vee (+5 V)
Vee (+5 V)
Voo
Rpu
RS
VSS
epu
SYSTEM
J.lP01990Ae
Fig. 8
Notice that a leakage current (CPU SYSTEM) of IOL flows in accordance with Ohm's law.
Decide the pull-up resistor value Rpu as following.
Rpu ~ 5 - 3.5
IOl
5 V: Power-supply (VCC)
3.5 V: Minimum of high level input voltage in
J.LPD1990AC
1125
j.lPD1990AC
(b)
Terminal of STB
to VOO of IlP01990AC
For STB input
10 kn
STB
(from CPU SYSTEM)
22 kS1
to STB of IlP01990AC
- - - - - - ' V \ \ r - -.........- - - I
22 kn
10 kn
GNO
Fig. 9
The STB input is low when the CPU system output is floating and when the CPU system is off.
4-5.
Interface for CS terminal
VCC (+5 V)
VCC (+5 V)
!
VOO
IlP01990AC
CS 1-------...
VSS
Fig. 10
A pull-down resistor R is inserted so that the CS input is low when the power supply (VCe) is off.
And the ClK and STB input prohibited by connecting CS input to GND level.
1126
,uPD1990AC
4-6.
Example of application circuit
Vcc (+5 V)
2SA733
System Power
Supply
510
15 kn
n
4.7 J..LF
2SC945 --Ni-Cd
-=-3.6 V
1
4.7 kn
14
VCC
VCC
32.768 kHz
VDD
3.3 kn
C2
13
VCC
3.3 kn
C1
VCC
~
w
Co
8
Vcc
f-
3.3 kn
DATA IN
::J
6
ClK
u
U
0
(J)
3.3 kn
11
OUT ENBl
33 kn
9
DATA OUT
33 kn
TP
VCC
«
DATA IN
VCC
a.
c::J
CD=5-30 pF
VCC
en
>en
12
CG=30 pF
3
3.3 kn
ClK
C1
XTAl
2
3.3 kn
Co
C2
XTAl
10
VDD
~
0
a.
OUT ENBl
::1.
DATA OUT
5
CS
33 kn
TP
4
22 kn
ST B t----'\A/\r---4--C
~--~STB
10 kn
VSS
GND
7
Fig. 13
1127
APPLICATION CIRCUIT OF ,uPC7800H SERIES
3-TERMINAL REGULATORS
1. INTRODUCTION
The manufacturing and circuit design techniques of integrated circuits have made rapid and remarkable progress in recent years. NEC has released 3-terminal regulators (J.LPC7800H series) featuring an output current
capability of 1 A, low noise and excellent stability.
The regulators are available in fixed output voltages options
5 V, 8 V, 12 V, 15 V, 18 V and 24 Vwith standard TO-220 plastic package. As they have built-in current limiting
circuit, thermal shut-down circuit and safe area compensation circuit, these monolithic circuits are very easy to
use in various applications.
2. ABSOLUTE MAXIMUM RATINGS
Although J.LPC7800H series include various protective circuits, it is necessary to examine the design of the application circuits so that they can operate within the absolute maximum ratings shown in Table 1.
Table 1 Absolute Maximum Ratings
(Ta=25
°e, unless otherwise noted.)
ITEM
Input Voltage
VIN
RATINGS
UNIT
(J.LPC7805H through J.LPC7818H) 35
V
(J.LPC7824H)
40
Operating Temperature Range
Topt
-20 to +80
V
W
°c
Storage Temperature Range
Tstg
-55 to +150
°c
Lead Temperature (Soldering 10 sec.)
TL
Internal Power Dissipation
Operating Junction Temperature Range
* Internally Limited
1128
SYMBOL
PT(Tc=25 °C)
20 *
230
o to +125
°c
°c
,uPC7800H SERIES
3. EQUIVALENT CIRCUIT AND THE OPERATION OF THE CIRCUIT
3-1
Equivalent Circuit
~~--------~------~~----~~--~--~1
Fig. 1
3-2
IN
Equivalent circuit
Fundamental Block Diagram
O-----~----------------~--------------~--------~~
1 UNREGULATED INPUT
Constant Current Source
Rll
~------4--o
3
2 REGULATED OUTPUT
3GND
Fig. 2
Fundamental Block diagram of the 3-terminal regulator
1129
J,lPC7800H SERIES
3-3
Pin Connection
GND
NEe
7800
132
It\
IN GND OUT
Fig. 3
3-4
Pin connection
Reference Voltage Circuit
The reverse breakdown voltage between the base and the emitter of a transistor has continuously been utilized
as the reference voltage inside the monolithic IC. It is, however, difficult for this method to obtain a voltage of
less than 6 V, and thus, the temperature compensation is required by adding another circuit. Instead of that
conventional technique, the pPC7800H series adopt a circuit utilizing the forward voltage drop between base and
emitter of a transistor as shown in FigA "Basic circuit"to get a reference voltage of lower than 6 V which remains
relatively stable against temperature change.
~----------~----------~----~------oVREF
R'
~AVBE2
3
I
~--------------~
\
03
VBE3
'--
Fig. 4
1130
Basic voltage reference diagram utilizing the forward voltage drop between base and emitter
of a transistor
,uPC7800H SERIES
In the circuit shown in Fig.4:, the reference voltage VREF can be obtained as follows;
:\)
VREF
= VSE3
+~ ICO'2 ··Ri
+ "SO) • Ri
~
=
VS~3 +,fu
: .(AVBE 2 ) + IS0 3 . Ri
R3
•
>
:~Ri kT .J 1
= V SE + - , (-In-)+Iso' ·Ri
3
R3 q
J2
3
~V
(VSE 1
SE 3
+
Ri (kT I Ri)
R'3 q n R'1
= VSE 2 , ISQ)
• R;
«
(1 )
1
Differentiating equation (1) by temperature T, equation (2) is obtained;
(2)
It may be understood that the temperature compensated reference voltage can be obtained by selecting
suitable resistance ratios R2' /R3' and R2' /R 1'.
Fig. 5 shows the reference voltage circuit of IlPC 7800H series obtaining.
GND
Fig. 5
3-5
VREF circuit of IlPC7800H series
Error Amplifier
The error amplifier consists of Q3, Q4, Q9 and Ql1. Of these transistors, Q3 and Q4 compose the reference
voltage circuit. Suffer circuit Qll is added to eliminate an excessive current change of Q9 which may be caused
by considerable voltage change of unregulated input or load condition and to get better stability of the operating
current finally. The constant current source consisting of Q9 works as an active load of the error amplifier. A
negative feedback path is provided through feedback resistors R 19 and R20, and the output voltage is given by
the following equation;
VOUT = VREF • (1
+
R20
R
)
.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(3)
19
Various output Voltage are obtained by varying the ratio of R20/R19.
1131
,uPC7800H SERIES
3-6
Start-up Circuit and Thermal Overload Protection Circuit
Fig. 6 shows start-up circuit and thermal overload protection circuit.
+Vcc
(Input)
(3.1V)
-----=-ry
~14 i L.
-t:===-:=-=====::;-1
!-I--"R-~
··
W
Fig. 6
I (oAV)
1
I
Q 13
f' 13.5VII
!
I--- Thermal protection circuit
IL ___________.JI
Start-up Circuit and Thermal Overload Protection Circuit
When a voltage is applied to the input terminal, 012 and 013 are biased through R4 causing diode-connected
transistor Oa to be driven, and the constant current transistor Og biased by Oa starts to supply the current to
the reference voltage circuit enabling entire circuit to start operation. The 013 base potential is determined
according to the voltage of zener diode Dl and the voltage split ratio of R5, R6, R7 and is approximately 3.1 V.
On the other hand, the emitter potential of the transistor becomes about 3.5V due to the operation of the
reference voltage circuit resulting O.4V of reverse bias between the base and the emitter. 013 operates at startingup time only and then it stops operation.
And current iSilupplied to the reference voltage circuit through Oa, Og. Also the base potential of 014 is fixed
to about O.4V by the resistance split of R5, R6, R7. If the junction temperature exceeds 150°C, 014 is fully
turned on causing the base current of the output transistors 016,017 to decrease and also cutting the output
current.
3-7
Output Short-circuit Protection, Output Transistor Safe Area Compensation
The thermal overload protection circuit is effective for persistent overloads which would cause excessive chip
temperature. It is not effective against instantaneous overloads which could result in secondary breakdown of the
pass transistor or damage to metal interconnection due to high current density. Transistor 015 and resistor R 11
protect against instantaneous overloads by limiting output current. If the output current rises to a high level, the
current through R 11 will turn on 015 shunting base current away from the driver transistor and preventing
further increase in output current. In order to operate the power transistor in the output stage within its forward safe area, a power limiting circuit is built in as shown in Fig. 7.
1132
,uPC7800H SERIES
----------~----------~----------~----_O1
IN
Rll
- - - - - - - 4_ _- - - -____________--+______________-----{)
Fig.7
2 OUT
Circuit of Output Stage
When the voltage between collector and emitter of 017 exceeds SV, zener diode D2 conducts and biases the
output current limiting transistor 015, cutting the base current of 016, Q17 and also cutting the output current.
Accordingly, the output capacity decreases correspondingly as the input/output voltage differential becomes
larger, causing 017 to be operated within the safe operating area as shown in Fig. S.
3.0
~
2.5
~
co
Q)
l~ ~..... 1'00..
a.
9
2.0
c:
f1
u
,y
.....
~:::J
.....
1.5
r--.-
:::J
e
:::J
0
E
1.0
r':K
.........
.........
"'-I '
Tj
= ooc
~ i'...
i" ~
i'...
..... ~
Tj
x 0.5
........
= 125°C
co
~
o
5
10
15
20
= 25
C-
,~
"~ ~
:::J
.§
Tj
""
25
~
30
Input-output voltage differential VIN-VO (V)
Fig. 8
Maximum outpu$ current vs input-output voltage differential
1133
,uPC7800H SERIES
4. TYPICAL APPLICATIONS
The pPC7800H series has an output current capacity of lA within a range of Tj<100 °c, and stable output
voltage is obtained by connecting a capacitor of more than 0.22 pF to the input terminal for preventing
oscillation. The output terminal capacitor is necessary to improve the transient response. It is effective at 10 pF
or more. A suitable value ranges from 50 pF to 100 pF.
In order to operate these regulators under the best condition, it is desirable to operate them at a junction
temperature of lower than 125°C. Accordingly, it is necessary, to use them with a suitable heat sink. If no heat
sink is used, the load current should be under 200 mA. In this case, a resistor of more than 50 n should be
connected to the input terminal to reduce a power loss at the time of output short-circuit.
Although the application circuits in this section are based on only pPC 7805H, they can also be applied to·8 V,
12V, 15V regulators.
4-1
Typical Circuit
(With heat sink)
pPC7805H
2
...,::....--...---'OVO
VIN> (VO+ 3V)
el
l
3
o.33j1F
47pF
C 1 : Mount closely to the input terminal for preventing oscillation
C2 : Improves transient response (electrolythic capacitor)
Fig.g
(recommend mylarfilm type capacitors)
Typical circuit of 3-terminal regulator
Fig. 9 is an example of typical application circuits of 3-terminal regulators. This circuit operates as a regulated
power supply having an output voltage of 5 Vand an output current capacity of 1 A.
4-2
High output current circuit
Fig. 10 shows a circuit example of increasing the output current capacity to higher than 2 A by adding a PNP
power transistor. The maximum output current is limited by the power dissipation of the external transistor, and
it is about 3 A taking the maximum ratings of 2SB616 into consideration.
Determine the R 1 value from equation (6)
lOUT
= I REG + ICO I
I REG
=
VBEOI
RI
+
. . . . . . . . . . , . . . . . . . . . , .... , . . . . . . . . . . . . . . . . .
ICOI
hFE
(4)
(5)
Rearraging equations (4) and (5) with reference to R 1;
(1
hFE • VBEOI
'IREG - lOUT
+ hFE)
Assuming lout(max)
:::0
3 A, Ireg(max)
A suitable value of R 1 is about 1...... 3
1134
n.
...................................
= O.4A,hFE = 20 and
Rl is about 2.6
n.
(6)
ttPC7800H SERIES
(with heat sink)
Fuse (3A)
2S8703
VIN> (VO + 4V)
-ICOl
(with heat sink)
RI
30n
~1
I
--lOUT
2
J,tPC7805H
5V
Vo
3
O.33~F
NOTE: 01 may be broken by output short circuit. If there is possibility of shortening the load, refer to examples of
application circuits in Figs. 12 and 13, and also please note to use a heat sink with enough margin.
Fig. 10 Circuit example of increasing the output current
When the output current is less than 0.2 A, 01 is OFF, and the output current is supplied through R 1 and the
IC. When it exceeds 0.2A,it is supplied through not only the IC but also 01. Fig.11 shows a current buffer circuit
obtained by adding a current limiting protective circuit to the one shown in Fig.10.
VIN> (Vo + 5V)
(with heat sink)
J,tPC7805H
2
30n
5V,3A
Vo
3
Fig. 11
Current Buffer (with short-circuit protection)
Fig. 12 shows an application circuit when the output current is limited by utilizing the built-in output current
protective functions in IlPC 7800H series.
Diode 01 cancels the voltage between base and emitter of 01, and the current ratio of the regulator and
external transistor is determined by R1. The maximum output current is three times the maximum output
current of IlPC7805H.
Considering a voltage loss by R 1 and 01, the mini mum input voltage to the regulator
should be more than (VO + 5 V).
1135
,uPC7800H SERIES
(with heat sink)
2S8703
u-----~--~~--._--~
VIN> (Va + 5V)
r---------------~
R t 0.50
(with heat sink)
la
",PC7805H
1------+----0 Va
2
1N5624
3
Fig. 12 Example of an application circuit with built-in current limitting circuit
4-3
Method of getting an optional output voltage (Simplified method)
(with heat sink) •
",PC7815H
3
Va
2
(
t18
(24V)
VR2
10,
\
(
VR1
\
• To be electrically insulated.
Fig. 13 Method of getting an optional output voltage
Two resistors are externally connected to the 3-terminal regulator having a fixed output so as to get an
optional output voltage as shown in Fig.13. Assuming regulator current be IQ and idling current of the external
resistor R2 be IB, the following equation is obtained.
Va
= VRI + VR2
= Rt
•
(IQ + IB) + R2 ·IB
(7)
=(R t +R 2 ) 'IB+R t 'IQ
Since VR2 is equal to the fixed output voltage of the 3-terminal regulator;
. . . . . . . . . . . . . . . . '"
..............................
(8)
Substituting equation (8) into equation (7);
(9)
1136
jlPC7800H SERIES
From equation (9), it may be understood that the output voltage is determined by the fixed output voltage
VR2, circuit current IQ and the external resistors R 1, R2 of the 3-terminal regulator.
IQ changes by about 0.05 rnA against the input voltage variation of about 1V. Fig.14 shows the characteristic
curve of the circuit current variation (b.IQ) vs input ripple voltage (b. VIN). By re-writing the equation (9) with
this variation, equation (10) is obtained.
Va
Rl
) . VR2 + RI
= (1 + -R
1
• (10 + AIO)
...............................
(10)
1.2
~ 1.0
E
a
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