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"

I

I'
i

il

INTERFACE
BIPOLAR lSI
BIPOLAR MEMORY
PROGRAMMABLE lOGIC
DATABOOK

I

Transmission Line Drivers/Receivers
Bus Transceivers

I'

Peripheral/Power Drivers
level Translators/Buffers

!II,

Display Controllers/ Drivers

I
I

iI
"

I

Memory Support
Dynamic Memory Support

'I
,i
I

i

,

Microproce$sor Support
Data Communications Support
Disk Support
Frequency Synthesis
Interface Appendices

(fJI

Bipolar PROMs

fBI

Bipolar and ECl RAMs

fD

2900 Family/Bipolar Microprocessor
Programmable logic
All physical dlm.l'uslons appeal' at the end of the databook.

fa

fa

Introduction
The 1983 edition of the National Semiconductor Interface I
Bipolar LSI I Bipolar Memory I Programmable Logic
Databook Is the most comprehensive available. It contains complete specifications on these high technology
products, as well as applications information, product
selection and cross reference guides.

Quality and Reliability
As electronic systems become more and more· complex,
the need for consistently high Quality integrated ciroults
becomes increasingly important. Having recognized this
need as far back as the 1970s, National Semiconductor Initiated a unlQue~ company-wide Quality Improvement Program. The results have been dramatic and, we believe,
. unmatched In this Industry. Over the years, National has
regularly been named by many major customers as "Qual·
ity Manufacturer of the Year." We are proud of our success, which sets a standard for others to achieve. And yet
our Quest for perfection is ongoing, so that customers can
continue to rely on National Semiconductor Integrated circuits and products in their system designs.

2

Einfuhrung

Introduction

Die 1983er Ausgabe des National Semiconductor Interface/Bipolar LSI/Bipolar Memory/Programmable Logic
Datenbuches ist die umfassendste Ausgabe die jemals
zur verfUgung stand. Sle beinhaltet komplette Spezifikationen dieser hochtechnologischen Produkte so wle
Angaben uber Anwendungsmoglichkelten, Produktselektion und Referenzlisten.

L'edition 1983 du catalogue National Semiconductor
Interface/Bipolar LSI/Bipolar Memory/Programmable
Logic est Ie plus accessible des catalogues disponibles.
Le contenu de celte edition specifie completement ces
produits technologie de pointe et decrit des examples
d'application, plus une selection de produits avec une
liste de correspondance.

a

Qualite et Fiabilite

Qualitat und Zuverlassigkeit

La complexite croissante des systemes electroniques
demande des circuits integres de plus en plus haute qualite. Conscient de ce besoin des les annees '70 National
Semiconductor fut I'origine d'un programme unique accentuant la qualite de to us ses produits. Les resultats
furent spectaculaires et inegales. Depuis National
Semiconductor a regu la distinction pour la qualite de ses
produits de la part de ses clients. Nous sommes flers de
ce succes qui force les aut res
suivre nos standarts.
Notre recherche de la perfection se poursuit apportant la
confiance pour nos clients en nos produits et leur utilisation pour leurs systemes.

Mit der zunehmenden Komplexltat der elektronischen Systeme wird die Notwendigkeit integriete Schaltungen mit
hoher Qualitat immer wichtiger. Dies bereits in den 70iger
Jahren erkannt, entwickelte National Semiconductor ein
einmaliges, firmenweltes "Qualitatsverbesserungsprogramm". Die damit von National Semiconductor erreichten Ergebnisse sind bis heute-wie wir glauben-unerreicht. Wah rend der letzten Jahre wurde National
Semiconductor regelmassig als "Qualitatsherstelier Nr
1" bewertet. Auf diesen Erfolg sind wir stolz. Er setzt neue
Mass-Stabe fUr die Industrie. Und doch gehen unsere
Austrengungen zu immer hoheren Perfektion we iter, so
dass sich unsere Kunden auch In Zukunft auf National
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ihren System en absolut verlassen konnen.

a

a

3

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OR SYSTEMS WITHOUTTHE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied, and National reserves the right. at any time without notice, to change said circuitry or specifications.

4

Table of Contents
Edge Index by Product Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction. . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alpha-Numerical Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .

1
2
13

Section 1-Transmission line Drivers/Receivers
8election Guides ............................................ ;..........
1-2
D81488 Quad Line Driver .............................. , . . . . . . . . . . . . . . . . . .
1-7
D81489/D81489A Quad Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-10
D826L831C/D826L831M Quad High 8peed Differential Line Driver. . . . . . . . . . . . . . .1-12
D826L832C/D826L832M,D826L832AC,D826L833C/D826L833M,
D826L833AC Quad Differential Line Receivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-15
D83486 Quad R8-422, R8-423 Line Receiver ...................... _. .. . . . . . . . .
1-18
D835871083487 Quad TRI-8TATE Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-22
D81603/D83603, D855107/D875107, D8551 08/D8751 08, D875207, D875208
Dual Line Receivers ................................................... '
1-25
D81650/D83650, D81652/D83652 Quad Differential Line Receivers ......... , .. ,. . .
1-31
D81691 A/D83691 (R8-422/R8-423) Line Drivers with TRI-8TATE ............... , . . .
1-37
D81692/D83692 TRI-8TATE Differential Line Drivers ...... , . . . . . . . . . . . . . . . . . . . .
1-42
D83695108369610836971083698 Differential TRI-8TATE BuslLine
1-47
TransceiverslRepeaters ...................... ',' . . . . . . . . . . . . . . . . . . . . . . . .
D855113/D875113 Dual TRI-8TATE Differential t.:ihe Driver. . . . . . . . . . . . . . .. . . . . . .
1-52
D855114/D875114 Dual Differential Line Drivers ....................... , . . . . . . .
1-57
D855115/D875115 Dual Differential Line Receiver ...... , . . . . . . . . . . . . . . . . . . . . . .
' 1-61
D855121/D875121 Dual Line Drivers ....................................... , .
1-66
D85512210875122 Triple Line Receivers. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-68
D875123 Dual Line Driver ...................................... , ........ , .
1-71
D875124 Triple Line Receiver .. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-73
D875125, D875127 8even-Channel Line Receivers. . . . . . . . . . . . . . . .. . . . . . . . . . . . .
1-76
D875128, D875129 Eight-Channel Line Receivers ..... , ................ , . . . . . . .
1-80
D875150 Dual Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-84
D875154 Quad Line Receiver, ......... , ..... '..... , . , . . . . . . . . . . . . . . . . . . . . . .
1-87
D87820/D88820 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-91
D87820A/D88820A Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-94
D878C20lOS88C20 Dual CM08 Compatible Differential Line Receiver ........... ,
1-98
D878301088830 Dual Differential Line Driver ........ , ................. " . . . . . .
1-101
D87831/D88831, D878321088832 Dual TRI-8TATE Line Driver ... , ........ : . . . . . . .
1-104
D878C120/D888C120 Dual CM08 Compatible Differential Line Receiver. . . . . . . . . .
1-109
D878L8120/D888L8120 Dual Differential Line Receiver
(Noise Filtering and Fail-8afe) ................ " . . . . .. .. . . . .. .. . . . .. . . .. .
1-116
1-123
AN-22 Integrated Circuits for Digital Data Transmission .......................
1-139
AN-108 Transmission Line Characteristics ..................................
AN-214 Transmission Line Drivers and Receivers for EIA 8tandards
1-145
R8-422 and R8-423 .....................................................
AN-216 8ummary of ElectricaLCharacteristics of 80me Well Known Digital
1-155
Interface 8tandards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5

Table of Contents

(Continued)

Section 2- Bus. Transcelvers
8election Guides ...................................................... .
2-3
OP7303/0P8303 8-Bit TRI-8TATE Bidirectional Transceivers .................... . 2-5,2-6
OP7304B/OP8304B 8-Bit TRI-8TATE Bidirectional Transceivers ......•...•....... 2-5, 2-11
OP7307/0P8307 8-Blt TRI-8TATE Bidirectional Transceivers .................... . 2-5,2-16
OP73081DP8308 8-Bit TRI-8TATE Bidirectional Transceivers .................... . 2-5,2-20
0826810, 0826811 Quad Bus Transceivers .................................. .
2-24
083662 Quad High 8peed Trapezoidal Bus Transceiver ....................... .
2-29
2-33
AN-259 083662-The Bus Optimize! ....................................... .
2-40
AN-337 Reducing Noise on Microcomputer Buses ........................... .
083666IEEE-488 GPIB Transceiver ........................................ .
2-48
083667 TRI-8TATE Bidirectional Transceiver .........................•.......
2-56
2-61
0875160AI0875161AI0875162A IEEE-488 GPIB Transceivers .................. .
2-68
. 087640/088640 Quad NOR Unified Bus Receiver ............................ .
2-70
087641/088641 Quad Unified Bus Transceiver ............................... .
088642 Quad Transceiver ............................................... .
2-72
087833/088833, 0878351088835 Quad TRI-8TATE Bus Transceivers ............ .
2-75
087834/0S8834, 087839/088839 Quad TRI-8TATE Bus Transceivers ............ .
2-79
2-83
087836/088836 Quad NOR Unified Bus Receiver ............................ .
087837/088837 Hex Unified Bus Receiver .................................. .
2-85
087838/088838 Quad Unified Bus Transceiver .............................. .
2-87
088T26A, 088T26AM, 088T28, 088T28M 4-Blt Bidirectional Bus Transceivers .... .
2-89

Section 3- Peripheral/Power Drivers
8election Guide ....... '. . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OP7310/0P8310/0P731110P8311 Octal Latched Peripheral Drivers ...............
081611/083611, 0816121083612, 081613/083613, 081614/083614
Dual Peripheral Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
083616 Bubble Memory Coil Driver...... ....... ..... .........•...... .... ....
081631/083631,0816321083632, 081633/083633, 0816341083634
CM08 Oual Peripheral Orlvers ........ . . . . . . . . . . . . . . . . . . . . ... . . . . . . . . . . . . .
083654 Printer 8olenoid Driver ................... ~ . . . . . . . . . . . . . . . . . . . . . . . . .
083656 Quad Peripheral Orlver ..............•.............................
083658 Quad High Current Peripheral Driver .................................
083668 Quad High Current Peripheral Driver ..............•..................
083669 Quad High Current Peripheral Driver .................................
083680 Quad Negative Voltage Relay Orlver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
083686 Dual Positive Voltage Relay Driver. . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . .
081687/083687 Negative Voltage Relay Driver .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0855450/0875450 8eries Dual Peripheral Orlvers . . . . . . • . . . . . . . . . . . . . . . . . . . . . . .
0855461/0855462/0855463108554a4, 0875461/08754621087546310875464
8eries Dual Peripheral Drivers •....................•..•..................
AN-213 8afe Operating Areas for Peripheral Drivers. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3-3
3-4
3-11
3-17
3-24
3-29

3-33
3-35
3-38
3-41 .
3-44
3-47
3-49
3-51
3-62
3-68

Section 4-Level Translators/Buffers
8electlon Guide ..................•..............•........•......•..•....
OP8480 10k ECLto TTL level Translator with Latch ...........................
OP8481 TTL to 10k ECl level Translator with latch....... .... .............. ..
6.

4-3
4-4
4-7

Table of Contents (Continued)
OP8482 100k ECL to TTL Level Translator with Latch ..........................
OP8483 TTL to 100k ECL Level Translator with Latch ..... ,....................
OS1630/0S3630 Hex CMOS Compatible Buffer .............. : . . . . . . . . . . . . . . . .
OS7800/0S8800 Dual Voltage Level Translator.. ... ..... .. . .... . . . ........... .
OS7810/0S8810 Quad 2-lnput TTL-MOS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . .
OS7811/0S8811 Quad 2-lnput TTL-MOS Interface Gate .........................
OS7812/0S8812 Hex TTL-MOS Inverter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS78L12/0S88L12 Hex TTL-MOS Inverter/Interface Gate. . . . . . . . . . . . . . . . . . . . . . .
OS7819/0S8819 Quad 2-lnput TTL-MOS AND Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4-10
4-13
4-16
4-19
4-22
4-22
4-22
4-25
4-27

Section 5- Display Controllers/Drivers
Selection Guides .......................................................
OP8350 Series CRT Controllers ...................... ; . . . . . . . . . . . . . . . . . . . . .
AN-199 A Low Component Count Video Data Terminal Using the OP8350
CRT Controller and the I NS8080 CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-212 Graphics Using the OP8350 Series of CRT Controllers. . . . . . . . . . . . . . . . . . .
AN-243 Graphics/Alphanumerics Systems Using the OP8350 . . . . . . . . . . . . . . . . . . .
AN-270 Software Design for a High Speed (38.4 kbaud) Data Terminal ............
OP-XXX Advanced Graphic CRT Controller, AGCRTC . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75491 MOS-to-LED Quad Segment Driver.. .. . .. .. .. .. .. . .. .. . . . . . . . . ... .. .
DS75492 MOS-to-LED Hex Digit Driver ........................ " ......... '"
DS55493/DS75493 Quad LED Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS554941OS75494 Hex Digit Driver ............. , ........................ '"
DS8654 8-0utput Display Driver (LED, VF, Thermal Printer) . . . . . . . . . . . . . . . . . . . . . .
DS8656 Diode Matrix ................................ " ... . . ...... . ... .. .
OS866414-Digit Decoder/Driver With Low Battery Indicator. . . . . . . . . . . . . . . . . . . . .
OS866614-Digit Decoder/Driver. . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .
DS8669 2-Digit BCD to 7-Segment DecoderlOriver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8692, DS8693, OS8694 Printing Calculator Interface Set. . . . . . . . . . . . . . . . . . . . . .
DS8859A, DS8869A Open Collector Hex Latch LED Drivers . . . . . . . . . . . . . . . . . . . . .
DS8861 MOS-to-LED 5-Segment Driver ................. ,. , , . .... .. . ... ..... .
DS8863 MOS-to-LED8-Digit Driver..........................................
OS8963 MOS-to-LED 8-Digit Driver. . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8867 8-Segment Constant Current Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS8870 Hex LED Digit Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8871, DS8872, DS8873 Saturating LED Cathode Drivers. . . . . . . . . . . . . . . . . . . . . .
DS8874 9-0igit Shift Input LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
DS8877 6-0igit LED Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS7880/DS8880 High Voltage 7-Segment Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . .
OS8881 Vacuum Fluorescent Display Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8884A High Voltage Cathode Decoder/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS8885 MOS to High Voltage Cathode Buffer.. .. ........ . . .... . ..... . . .. ....
DS8887 8-Digit High Voltage Anode Driver (Active-High Inputs) . . . . . . . . . . . . . . . . . .
DS7889/0S8889 8-Segment High Voltage Cathode Driver (Active-High Inputs) . . . . . .
DS7897A1DS8897A 8-Digit High Voltage Anode Driver (Active-Low Inputs) . . . . . . . . .
DS8891A High Voltage Anode Drivers (Active-Low Inputs) ... . . . . . . . . . . . . . . . . . . .
DS8973, DS89759-Digit LED Drivers........................................
AN-84 Driving 7-Segment Gas Discharge Display Tubes with
National Semiconductor Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AN-99 Driving 7-Segment LED Displays with National Semiconductor
Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7

5-3
5-6
5-30
5-44
5-48
5-76
5-104
5-106
5-106
5-109
5-111
5-113
5-113
5-117
5-120
5-123
5-126
5-133
5-136
5-136
5-136
5-139
5-141
5-143
5-145
5-147
5-149
5-152
5-156
5-158
5-160
5-160
5-160
5-164
5-166
5-169
5-173

Table of Contents (Continued)
Section 6-Memory Support
Selection Guides ........................................................
OS0025C Two Phase MOS Clock Oriver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS0026, OS00565 MHz Two Phase MOS Clock Orivers ................. , . .... . .
OS3245 Quad MOS Clock Oriver ...................................... '.' . . .
OS1617/0S3617 Bubble Memory Sense Amplifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS1628/0S3628 Octal TRI-STATE MOS Orivers ...............................
OS1644/0S3644, OS1674/0S3674 Quad TIL to MOS Clock Orivers . . . . . . . . . . . . . . . .
OS1645/0S3645, OS1675/0S3675 Hex TRI-STATE TIL to MOS Latches/Orivers . . . . . .
.
OS1647/0S3647, OS1677/0S3677, OS16147/0S36147, OS16177/0S36177
Quad TRI-STATE MOS Memory I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS1648/0S3648, OS1678/0S3678 TRI-STATE TIL to MOS Multiplexers/Orivers . . . . . .
OS1649/0S3649, OS1679/0S3679 Hex TRI-STATE TIL to MOS privers . . . . . . . . . . . . .
OS1651/0S3651, OS1653/0S3653 Quad High Speed MOS Sense Amplifiers. . . . . . .. .
OS16711OS3671 Bootstrapped Two Phase MOS Clock Oriver ....................
OS3685 Hex TRI-STATE Latch .............................................
OS16149/0S36149, OS16179/0S36179 Hex MOS Orivers . . . . . . . . . . . . . . . . . . . . . . . . .
OS553251OS75325 Memory Orivers . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .
OS75361 Oual TIL-to-MOS Oriver. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .
OS75362 Oual TIL-to-MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OS75365 Quad TIL-to-MOS Oriver . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . .
AN-76 Applying Modern Clock Orivers to MOS Memories. . . . . . . . . . . . . . . . . . . . . . .

6·3
6·4
6·7
6·14
6-17
6-24
6-27
6-30
6-35
6-41
6-46
6-49
6-55
6-59
6-62
6-66
6-73
6-78
6-83
6-88

Section 7- Dynamic Memory Support
AN-302 The OP8400 Family of Mem6ry Interface Circuits ...................... .
OP84240/244 Octal TRI-STATE MOS Orivers ................................. .
Single-Chip Controllers Cover All RAMs from 16k to 256k ...................... .
OP8408 Oynamic RAM Controller/Oriver ................................... , .
OP8409 Multi-Mode Oynamic RAM Controller/Oriver ......................... .
OP8419 High Speed Oynamic RAM ControllerlOriver ...........................
App Brief 1 OP8408, OP8409 Application Hints .............................. .
App Brief 9 OP8408/9 Fastest ORAM Access Mode ........................... .
AN-305 Precautions to Take When Oriving Memories ............... : ......... .
. DP8400 E2C2 Expandable Error Checker and Corrector ....................... .
AN-306 Expanding the Versatility of the OP8400 ............................. .
AN-308 OP8400s in 64-Bit ExpanSion ...................................... .
Error Correction the Hard Way ............................................ .
Simplification of 2-Bit Error Correction ..................................... .
Effortless Error Management ................•......................... ; ..
OP84300 Programmable Refresh Timer .................................... .
.OP84312 Oynamic RAM Controller Interface Circuit for
the NS16032 CPU .................................................... .
OP84322 Oynamic RAM Controller Interface Circuit for
the 68000 CPU ....................................................... .
OP84332 Oynamic RAM Controller Interface Circuit for
the 8086 and 8088 CPUs ................................................ .
AN-309lnterfacing the OP8408/09 to Various Microprocessors ................. .
App Brief 2 Memory Systems with ~CC Using the OP8400 ..................... .

8

7-3
7-15
7-20
7-26
7-43
7-64
7-65
7-66
7-68

7-72
7-104
7-116
7-124
7-127
7-134
- 7-139
7-144
7-152
7-167
7-177
7-191

Table of Contents (Continued)
Section 8- Microprocessor Support
Selection Guide ........................................................
DP8212/DP8212M 8-Bit Input/Output Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP82161DP8216M, DP8226/DP8226M 4-Bit Bidirectional Bus Transceivers. . . . . . . . .
DP8224 Clock Generator and Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8228/DP8228M, DP8238/DP8238M System Controller and Bus Driver. . . . . . . . . . .

8-3
8-4
8-11
8-16
8-22

Section 9- Data Communications Support
DP8340 Serial Bi-Phase Transmitter/Encoder ................................
DP8341 Serial Bi-Phase Receiver/Decoder ............................ '. . . . . . .
DP8342 High-Speed Serial Transmitter/Encoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8343 High-Speed Serial Receiver/Decoder ................................

9-3
9-12
9-23
9-32

Section 10-Disk Support
AN-334 LSI Components for Winchester Disk Drives and Controllers . . . . . . . . . . . . .
DP8460 Data Separator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DP8464 Disk Pulse Detector ..............................................
DP8466 Disk Data Controller.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .

10-3
10-10
10-31
10-34

Section 11-Frequency Synthesis
Selection Guide ........................................................
DS8906 AM/FM Digital Phase-Locked Loop Frequency Synthesizer. . . . . . . . . . . . . .
DS8907 AM/FM Digital Phase-Locked Loop Frequency Synthesizer. . . . . . . . . . . . . .
DS8908AM/FM Digital Phase-Locked Loop Frequency Synthesizer ..............
DS8614, DS8615, DS8616, DS8617 130/225 MHz Low Power Dual
Modulus Prescalers . . . . . . . . . .. . . .. . . .. . . . . . . . . . . . . . . . .. . . . . . . . . . . . .. . .
DS8626 120 MHz Divide-by-40 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8629120 MHz Divide-by-100 Prescaler................ ................ ....
DS8627, DS8628130/225 MHz Low Power Prescalers ............ ... .... .......
DS8621 275MHz/1.2 GHz VH F/UHF Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS8622 500 MHz/1.2 GHz Dual Modulus VHF/UHF Prescaler ...................
AN-335 Digital PLL Synthesis .............................................

11-3·
11-4
11-10
11-16
11-23
11-27
11-27
11-30
11-33
11-36
11-40

Section 12-lnterface Appendices
Interface Cross Reference Guide ..........................................
AN-336 Understanding Integrated Circuit Package Power Capabilities ...........
Industry Package Cross Reference Guide. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sections 13 thru 20 for future expansion in supplement books

9

12-3
12-11
12-16

Table of Contents (Continued)
Section 21-Bipolar PROMs
Introduction .•............... , .......... '.................... .' . . . . . . . . . . . .
Bipolar PROM Selection Guide . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S188. DM54/74S288 (32 x 8) 256-Bit TIL PROMs. . . . . . . . . . . . . . . . . . . . . . .
DM54/74S387, DM54/74S287 (256 x 4) 1024-Bit TIL PROMs. . . . . . . . . . . . . . . . . . . . .
DM54/74S570, DM54/74S571, DM54/74S570A, DM54/74S571 A,
DM54/74S571 B (512 x 4) 2048-Bit TIL PROMs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74LS471 (256 x 8) 2048-Bit TIL PROMs ................................
DM54/74S473, DM54/74S472, DM54/74S473A, DM54/74S472A,
DM54/74S472B (512 x 8) 4096-Bit TIL PROMs .. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S475, DM54/74S474, DM54/74S475A, DM54/74S474A,
DM54/74S474B (512 x 8) 4096-Bit TIL PROMs ......................... , .. ..
DM77/87SR474, DM77/87SR474B (512 x8) 4k-Bit Registered TIL PROM ..........
DM77/87SR476, DM77/87SR25, DM77/87SR476B, DM77/87SR25B
(512 x 8) 4k·Bit Registered TIL PROM, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54/74S572, DM54/74S573, DM54/74S572A, DM54/74S573A,
, DM54/74S573B (1024 x 4) 4096-Bit TIL PROMs .............. ~ .. . . . . . . . . . . . .
DM77/87S180, DM77/87S181, DM77/87S181A, DM77/87S280,
DM77/87S281 DM77/87S281 A (1024 x 8) 8192-Bit TIL PROMs ....... . . . . . . . . . .
DM77/87LS181 (1024 x 8) 8192-Bit TIL PROMs ...............................
DM77/87SR181 (1024 x 8) 8k-Bit Registered TIL PROM ........................
DM77/87S184, DM77/87S185, DM77/87S185A, DM77/87S185B
(2048 x 4) 8192·Bit TIL PROMs ..........................................
DM77/87S190, DM77/87S191, DM77/87S290, DM77/87S291, DM77/87S190A,
DM77/87S191A, DM77/87S290A, DM77/87S291A, DM77/87S190B,
DM77/87S191 B, DM77/87S290a, DM77/87S291 B
(2048 x 8) 16,384-Bit TIL PROMs .............. ; .. ~ . . . . . . . . . . . . . . . . . . . . . . .
DM77/87S195A, DM77/87S195B (4096 x 4) 16,384-Bit TIL PROMs. . . . . . . . . . . . . . . .
DM77/87S321, DM77/87S421, DM77/87S321 A, DM77/87S421 A
(4096 x 8) 32,768-Bit TIL PROMs ............ ~ . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Non Registered PROM Programming Procedure ............. , . . . . . . . . . . . . . . . .
Registered PROM Programming Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Test Load ....... .-......................... '. . . . . . . . . . . . . . . . . . . . . .
SWitching Time Waveforms
Non-Registered PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Registered PROMs ..................................... : . . . . . . . . . . . . . .
Key to Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Approved Programmers for NSC PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality Enhancement Programs for Bipolar Memory. . . . . . . . . . . . . . . . . . . . . . . . . .
DM76S64IDM86S64 BipolarCharacter Generator ..... ~ . . . . . . . . . . . . . . . . . . . . . . .
DM76S128IDM86S128 Bipolar Character Generator. . . . . . . . . . . . . . . . . . . . . . . . . . .

10

21-3
21-4
21-6.
21-8
21-10
21-12
21-14
21-16
21-18
21-20
21-22
21-24
21-26
21-28
21-30

21-32
21-34
21-36
21-38
21-40
21-42
21-42
21-42
21-42
21-43
21-43
21-44
21-55

Table of Contents (Continued)
Section 22- Bipolar and ECl RAMs
OM54S189IDM74S189 64-Bit (16 x 4) TRI-STATE RAM. . . . . . . . . . . . . . . . . . . . . . . . . .
oM54S289IDM74S289 64-Bit Open-Collector RAM ............................
OM54S189AIDM74S189A High Speed 64-Bit TRI-STATE RAM. . . . . . . . . . . . . . . . . . . .
OM75S06IDM85S06 Open-Collector, DM75S07IDM85S07 TRI-STATE,
DM75S07AIDM85S07A High Speed TRI-STATE Non-Inverting,
64-Bit (16 x 4) RAMs ...................................................
DM77S401IDM87S401, DM77S4021DM87S402 First-In, First-Out (FiFo)
64 x 4, 64 x 5 Serial Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77S401AIDM87S401A, OM77g402A/DM87S402A First-In, First-Out (FiFo)
64 x 4, 64 x 5 Serial Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM75S68/DM85S6816 x 4 Edge Triggered Registers ..........................
IDM29705/29705A 16-Word by 4-Bit Two-Port RAM/Register File ................. '
OM10414, DM10414A 256 x 1 ECl Random Access Memory ....................
DM10415, DM10415A 1024 x 1 ECl Random Access Memory. ... . . .. . . . . .. . . .. .
DM104221024-Bit(256 x 4) ECl RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OM10422A 1024-Bit (256 x 4) ECl RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OM10470 Standard, OM10470A High Speed, DM10470l low Power
4096-Bit (4096 x 1) ECl RAMs ...........................................
OM 10474IDM 10474A (1024 x 4) 4096-Bit, 10k ECl RAM. . . . . . . . . . . . . . . . . . . . . . . . .

22-3
22-3
22-3

22-10
22-16
22-20
22-24
22-27
22-32
22-37
22-42
22-45
22-48
22-53

Section 23-2900 Family/Bipolar Microprocessor
Introduction ............................................................ .
IDM2901A, IDM2901A-1, IDM2901A-2 4-Bit Bipolar Microprocessor .............. .
IOM2902 look-Ahead Carry Generator .....................•................
IDM2909A/11A Microprogram Sequencer .................................. .
IDM2910A Microprogram Controller ....................................... .
IOM2980316-Way Branch Controller ....................................... .
IDM29811 Next-Address Controller ......................................... .
DM10900 8-Bit Parity AlU Slice ........................................... .
IDM2900 Family Applications Information .................................. .
System Architecture of the IDM2901A ................................... .
Expanding the IDM2901 Bit-Slice Microprocessor .......................... .
Hardware Multiplication .............................................. .
Byte Swapping ...................................................... .
Instruction Fetch Cycle .................................. ~ ............ .
File ExpanSion ...................................................... .
Using the IOM2909A/11A in a Computer Control Unit ....................... .
Speed Enhancement of Bipolar Bit-Slice Microprocessor Systems ............ .
AN-203 Bit Slice Microprocessor DeSign Takes a Giant Step Forward with
"Schottky-Coupled-logic" Circuits ...................................... .
AN-217 High-Speed Bit Slice Microsequencing Design ........................ .
AN-230 Fine Tuning the AlU Carry Path .................................... .

11

23-3
23-4
23-21
23-24
23-34
23-51
23-57
23-62
23-72
23-72
23-72
23-75
23-76
23-76
23-76
23-78
23-86
23-93
23-105
23-112

Table of Contents (Continued)
Section 24-Programmable Logic
Introduction and General Description ............ , .......................... '
The PAL-A New Extension of Fusible-Link Technology ...............•......
Comparison (PROMs, PALs, and FPLAs) ....................... , ......... .
PALs For Every Task (Family Description) ................................ .
PAL Part Numbers .............................• ' .. '.. ; .................. .
.PAL Logic Symbols ................................................... .
Data Sheets .......... ; ... ' .............. , , ... , .. , , .... , ............ '.. , . ,
Programmable Array Logic (PAL) Series 20/20A Description , .... ,., ... ,., .. ,.
Programmable Array Logic Family Series 24 .. , ... , ..... , , ., , , , .. , .... , , . , .
PAL Design " .... , ............... ,., .... ,"',.,., ...... ,., ....... ,,:,.,
Selecting the Right PAL ...... , , , .. , ...... , , , . , ... , .. , ....... , . , . , . ~ , . , .
PAL Logic Diagrams, ......... , .......... , ... , ....... '....... , ......... .
Designing the PAL; Manual Method ., " ..... ~ ......... , .. ; . , ... , . , . , .. , . ,
Designing the PAL; PALASM .......... , ...... , . , .......... , : ........... ,
PALASM Flow Chart ......... , .. , .. , . , . , . , , . , , , . , . , ... , " , .' .... '. , . , ... , ,
PALASM Source Code for 20 Series .... ,', ..... ,.,.,."., .. ; ... ,. , . , ... , ..
PALASM Source Code for 24 Series .. ,.,., ... " ..... ,.,',:,.,: ... ,.".,"
PAL Logic Diagrams and Programming Format Coding Sheets ... , ..... , ... : ..
Application Suggestions .. , , ... , ...... , , . " ..... , .. , , , ... , . , . , , . ,'. , . , , . , ..
Basic Gates ... , , , .... , .. , , , , . , ... , , , , , . , . , ... , , , . , .......... ,'. , , .... .
6·Bit Shift Register .... , ....... ".' .......• , ~ , , . , . , .... , . '.' , .. ,.; .... , , ,. ,
Control Store Sequencer .. , . , . , , , . , ...... , . , .. , .. , . , , ... , . , . , .... , .... .
Memory Mapped I/O . , . , . , ...... , ........ , .... , ........ , ............ , . ,
8080 Control Logic for CPU Board ........ ; •... , ...... , .......... '...... , ..
Hexadecimal Decoder/Lamp Driver ... ,., ............. , ..... ;., ......... .
Hex Keyboard Scanner. , ....... , . ~ .. , . , ............ , ............ , ..... .
Micro Floppy Control Logic (Mini·Diskette) ... ,., .......... ,., ............ ,
Between Limits Comparator/Register .,., ............... , ..... ,.;,.,., .... '
Priority Encoder with Registers, , ..... , , , ...... , .... , ... , .. , . , ..... , . , .. :
Quad 3-line/1-line Data Selector Multiplexer ................. , ............ .
4-Bit Counter with Multiplexing ....... , . , .. , .... , , .', .. , ........ , ..... , .. ,
4-Bit Up/Down Counter with Shift , .......... , ............................ '
ALU Accumulator .... , . , . , .. , . , . , : , ..... ; , ,'.. , ..... , ... , .............. ,

Physical Dimensions . . , ... , . ~ . , .. , . , . , ..... , .. , , ......... , . , .... : ... .

12

24-3
24-4
. 24-6
24-10
24-13
24-13
24-18
24·18
, 24-27
24·32
'24·32
24-107
24-35
24-41
24-47
24-48
24·79
24-132
24-164
24-164
24-170
24·176
24-185
24-189
24·195
24-200
24-204
'24-208
24-215
24-217
24·219
24-221
24-223

A-1

Alpha-Numerical Index
App Brief 1 DP8408, DP8409 Application Hints .............................. .
App Brief 2 Memory Systems with ECC Using the DP8400 ....... : .............. .
App Brief 9 DP8408/9 Fastest DRAM Access Mode ........................... .
AN·22 Integrated Circuits for Digital Data Transmission' ...................... .
AN·76 Applying Modern Clock Drivers to MOS Memories ...................... .
AN·84 Driving 7·Segment Gas Discharge Display Tubes with
.
National Semiconductor Circuits ....................................... .
AN·99 Driving 7·Segment lED Displays with National Semiconductor
Circuits ............................................................ .
AN·108 Transmission Line Characteristics ................................. .
AN·199 A low Component Count Video Data Terminal Using
the DP8350 CRT Controller and the INS8080 CPU .......................... .
AN·203 Bit Slice Microprocessor Design Takes a Giant Step Forward, with
"Schottky·Coupled·logic" Circuits ...................................... .
AN·212 Graphics Using the DP8350 Series of CRT Controllers .................. .
AN·213 Safe Operating Areas for Peripheral Drivers .......................... .
AN·214 Transmission Line Drivers and Receivers for EIA Standards
RS·422 and RS·423 ................................................... .
AN·216 Summary of Electrical Characteristics of Some Well Known
Digital Interface Standards ............................................ .
AN·217 High·Speed Bit Slice Microsequencing Design ........................ .
AN·230 Fine Tuning the AlU Carry Path .................................... .
AN·243 Graphics/Alphanumerics Systems Using the DP8350 .................. .
AN·259 DS3662-The Bus Optimizer ........... '............................ .
AN·270 Software Design for a High Speed (38.4 kbaud) Data Terminal ........... .
AN·302 The DP8400 Family of Memory Interface Circuits ...................... .
AN·305 Precautions to Take When Driving Memories ......................... .
AN·306 Expanding the Versatility of the DP8400 ............................. .
AN·308 DP8400s in 64·Bit Expansion ...................................... .
AN·309lnterfacing the DP8408/09 to Various Microprocessors ....... : ......... .
AN·334 lSI Components for Winchester Disk Drives and Controllers ............ .
AN·335 Digital Pll Synthesis ............................................ .
AN·336 Understanding Integrated Circuit Package Power Capabilities .......... .
AN·337 Reducing Noise on Microcomputer Buses .. : ........................ .
DM 10414256 x 1 ECl Random Access Memory ............................. .
DM10414A 256 x 1 ECl Random Access Memory ............................ .
DM104151024 x 1 ECl Random Access Memory ............................ .
DM10415~ 1024 x 1 Eel Random Access Memory ........................... .
DM104221024·Bit (256 x 4) ECl RAM ...................................... .
DM10422A 1024·Bit (256 x 4) ECl RAM ..................................... .
DM10470 Standard 4096·Bit (4096 x 1) ECl RAM ............................. .
DM10470A High Speed 4096·Bit (4096 x 1) ECl RAM .......................... .
DM10470l low Power 4096·Bit(4096 x 1) ECl RAM ........ .'., ................ .
DM10474 (1024 x 4) 4096·Bit, 10k ECl RAM ......................... : ....... .
DM10474A (1024 x 4) 4096·Bit, 10k ECl RAM ................................ .
DM10900 8·Bit Parity AlU Slice ........................................... .
DM54S188 (32 x 8) 256·Bit TIL PROM ...................................... .
DM54S189 64·Bit (16 x 4) TRI·STATE RAM ................................... .
DM54S189A High Speed 64·BitTRI·STATE RAM ............................. .
DM54S287 (256 x 4) 1024·Bit TIL PROM .................................... .
DM54S288 (32 x 8) 256·Bit TIL PROM ..................... ; ................ .
DM54S289 64·Bit Open·Collector RAM ..................................... .
13

7-65
7·191
7·66
1·123
6·88
5·169
5·173
1·139
5·30
23·93
5·44·
3·68
1·145
1·155
23·105
23·112
5·48
2·33
5·76
7·3
7·68
7·104
7·116
7·177
10·3
11·40
12·11
2-40
22-32
22·32
22·37
22-37
22·42
22~45

22·48
22·48
22·48
22·53
22·53
23·62
21·6
22·3
22·3
21·8
21·6
22·3

Alpha-Numerical Index (Continued)

:
:
"
,

DM54S387 (256 x 4)1024-Blt TTL PROM . . . . • . . . . . . . . . . . • . . • . . . . . . . . . . . . . . . . .
DM54LS471 (256 X 8) 2048-Bit TTL PROM. . . . • . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . .
DM54S472 (512 X 8) 4096~Blt TTL PROM . . . . . . . . • • . . . . .. .. .. .. . .. .. . .. . .. .. ..
DM54S472A (512 X 8) 4096-Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S472B (512 X 8) 4096-Bit TTL PROM. . . . . . . . . . . . . . . • . . . . . . . • . . . . . . . . . . . .
DM54S473 (512 X 8) 4096-Bit TTL PROM ........ : . . . . . . . . .. . . . . . . . . . . . . . . . . . .
DM54S473A (512 X 8) 4096-Blt TTL PROM ................................. -. . .
DM54S474 (512 X 8) 4096-Bit TTL PROM . .. .. . . .. .. . .. .. . .. .. .. .. . .. .. .. . .. ..
DM54S474A (512 X 8) 4096-Blt TTL PROM ........... -. ........_. . . . . . . . . . . . . . ..
DM54S474B(512 x8)4096-Blt TTL PROM ...•...................•............
DM54S475 (512 X 8)4096-Bit TTL PROM. . . .. .. . . . .. . . . . . . . . . . . . . . .. . . . . . . . . .
DM54S475A(512 x8) 4096-Blt TTL PROM ....................................
DM54S570 (512 X 4) 2048-Blt TTL PROM. . • .. .. .. . .. .. .. .. . .. .. .. .. .. .. .. .. . .
DM54S570A (512 X 4) 2048-Bit TTL PROM. . . . . . • . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S571 (512 X 4)2048-Bit TTL PROM .................... ,................
DM54S571 A (512 X 4)2048-Blt TTL PROM ................ :...................
DM54S571 B (512 X 4) 2048-Blt TTL PROM. ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S572 (1024 X 4) 4096-Bit TTL PROM .. .-. . . . . . . . . . . . . . . . . . . . . . . . . . .. . • . . .
DM54S572A (1024 X 4) 4096-Bit TTL PROM.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM54S573 (1024 x4) 4096-BitTTL PROM....................................
DM54S573A (1024 X 4) 4096-Blt TTL PROM ...•.................•....... , ..... '
DM54S573B (1024 X 4) 4096-Bit TTL PROM. . . . . . . . . . . . . . . . . . . .. . . .. . . . . .. . . . .
DM74S188 (32 X 8) 256:-Bit TTL PROM . . . • . . . . . . • • . . . . . . . • . . . . . . . . • . . . . . • . . . .
DM74S189 64-Bit (16 X 4) TRI-8TATE RAM. . . . . . . . . .. . . . . . .. . . . .. .. .. . .. .. . . . .
DM74S189A High Speed 64-BltTRI·STATE RAM ..•.................•..........
DM74S287 (256 X 4) 1024-Bit TTL PROM. .. . . . . . .. . . . . . . . . . . . . . . • .. .. .. .. .. . .
DM74S288 (32 X 8) 256-Bit TTL PROM ............................. '. . . . . .. . ..
DM74S289 64-Blt Open·Coliector RAM ................. .' . . . .. . . . . . . . .. . . . . . .
DM74S387 (256 X 4) 1024-Bit TTL PROM ...............•...... ~ . . . . . . . . . . . . . .
DM74LS471 (256 X 8) 2048-Blt TTL PROM. . .. . . . . . . . . .. . . . . . .. . . . .. . . . .. .. . . .
DM74S472(512x8) 4096-Blt TTL PROM. ....................................
DM74S472A(512 X 8)4096-Bit TTL PROM....................................
DM74S472B (512 X 8) 4096-Bit TTL PROM. . . . . . • . . . . . . . . . • . . • . . . . . . . . . . . . . . . .
DM74S473 (512x 8) 4096-Bit TTL PROM.....................................
DM74S473A(512 x8)4096-Bit TTL PROM ....................................
DM74S474(512x8)4096-BitTTLPROM .....................................
DM74S474A (512 x8) 4096-Blt TTL PROM ....................................
DM74S474B(512x8)4096-BitTTLPROM ................................ ;...
DM74S475 (512 X 8)'4096-Blt TTL PROM. . • . . .. .. . . .. • . . . . . . . . . . . .. . . .. . . . .. •
DM74S475A(512 x 8)4096-Blt TTL PROM....................................
DM74S570 (512 X 4) 2048-Blt TTL PROM. . . . . . . . . . . .. . . .. • . . . . . . . . . . . .. . . . .. .
DM74S570A(512x4)2048-BltTTLPROM ................................. ',"
DM74S571 (512 X 4) 2048-Bit TTL PROM ..••......•.•....•....-. • . . . . . . . . . . . . .
DM74S571A (512 X 4) 2048-Blt TTL PROM. . . . . . . . . .. • . . • •. . . . . . • . . .. . . . . . . . • .
DM74S571B(512x4)2048-BltTTLPROM •......•.....•....••...... ~.........
DM74S572 (1024 X 4) 4096-Blt TTL PROM .. . .. . . . .. .. . .. . . . . .. .. . . . .. . . . . . . . .
DM74S572A (1024 X 4) 4096-Blt TTL PROM. . . . . . . . . . . . • . . • .. . . . . . . . . . . . . . . . . •
DM74S573 (1024 X 4) 4096-Bit TTL PROM. • • • . . . . . . . • . . . . • . . . • . . . . . . . . . . . . . • .
DM74S573A (1024 X 4) 4096-Blt TTL PROM. . . • . • . . . . . . . • . . . . . • . • . . • . . . • . . • . • .
DM74S573B (1024 X 4) 4096-Blt TTL PROM. • . • • . . . • • • . . . • . . . . • • . . . . . . . . . . . . • .
DM75S06 Open-Collector Non·lnverting, 64-Blt (16 X 4) RAM ....••..............
DM75S07 TRI-8TATE Non·lnvertlng, 64-Blt (16 X 4) RAM ...•.....••••.•.•.•...•.
14

21-8
21-12
21-14
21-14
21-14
21-14
21-14
21-16
21-16
21-16
21-16
21-16
21-10
21-10
21-10
21-10
21-10
21-22
21-22
21-22
21-22
21-22
21-6
22-3
22-3
21-8
21-6
22-3
21-8
21-12
21-14
21-14
21-14
21-14
21-14
21-16
21-16
21-16
21-16
21-16
21-10
21-10
21-10
21-10
21-10
21-22
21-22
21-22
21-22
21-22
22-10
22-10

Alpha-N umerical Index (Continued)
DM75S07A High Speed TRI·STATE Non·lnverting, 64·Bit (16 x 4) RAM. . . . . . . . . . . . .
DM75S6816 x 4 Edge Triggered Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM76S64 Bipolar Character Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM76S128 Bipolar Character Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77SR25 (512 x8)4k·Bit Registered TTL PROM. . . .. . .... . ........ . ... . . .. ..
DM77SR25B (512 x 8) 4k·Bit Registered TTL PROM. . . . . . . . . . . . . ... . . . . . . . . . . . . .
DM77S180 (1024 x 8) 8192·Bit TTL PROM. . . . .. .. . . .. . ... . .. . . . . .. . . .. . . . . .. .
DM77LS181 (1024 x 8) 8192·Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77S181 (1024 x 8) 8192·Bit TTL PROM.. . . . .. .. .. . . . . . . . . . . . . . . .. . . . . . . .. .
DM77S181A (1024 x 8) 8192·Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77SR181 (1024 x 8) 8k·Bit Registered TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77S184 (2048 x 4) 8192·Bit TTL PROM.. . . .. .. . . .. .. . .. . . . . .. . . .. .. .. . . .. .
DM77S185 (2048 x 4) 8192·Bit TTL PROM.. . . .. .. . . .. . .. .. . . .. .. . . .. . . . . . . .. .
DM77S185A (2048 x 4) 8192·Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77S185B (2048 x 4) 8192·Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77S190 (2048 x 8) 16,384·Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .
DM77S190A (2048 x 8) 16,384·Bit TTL PROM .................................
DM77S190B(2048x8)16,384·BitTTLPROM .................................
DM77S191 (2048 x 8) 16,384·Bit TTL PROM. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77S191A (2048 x 8) 16,384·Bit TTL PROM .................................
DM77S191 B (2048 x 8) 16,384·Bit TTL PROM .................................
DM77S195A (4096 x 4) 16,384·Bit TTL PROM .................................
DM77S195B (4096 x 4) 16,384·Bit TTL PROM .................................
DM77S280 (1024 x 8) 8192·Bit TTL PROM. .. .. . . .. .. .. .. .. . . .. .. . .. . .. .. .. . ..
DM77S281 (1024 x 8) 8192·Bit TTL PROM. . . . .. . .. .. .. .. .. . . . . .. . . .. .. .. . . .. .
DM77S281A (1024 x 8) 8192·Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
, DM77S290 (2048 x 8) 16,384·Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77S290A (2048 x 8) 16,384·Bit TTL PROM .•............. :.................
DM77S290B (2048 x 8) 16,384·Bit TTL PROM .................................
DM77S291 (2048 x 8) 16,384·Bit TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77S291A (2048 x 8) 16,384·Bit TTL PROM .................................
DM77S291 B (2048 x 8) 16,384·Bit TTL PROM .................................
DM77S321 (4096 x 8) 32,768·Bit TTL PROM .................... ; . . . . . . . . . . . . . .
DM77S321A (4096 x 8) 32,768·Bit TTL PROM .................................
DM77S401 First·ln, First·Out (FiFo) 64 x 4, 64 x 5 Serial Memories ...............
DM77S401A First·ln, First·Out (FiFo) 64 x 4,64 x 5 Serial Memories. . . . . . . . . . . . . .
DM77S402 First·ln, First·Out (FiFo) 64 x 4, 64 x 5 Serial Memories ...............
DM77S402A First·ln, First·Out (FiFo) 64 x 4,64 x 5 Serial Memories ..... ; . . . . . . . .
DM77S421 (4096 x 8) 32,768-Bit TTL PROM ................................... '
DM77S421A (4096 x 8) 32,768·Bit TTL PROM ...........•....••...............
DM77SR474 (512 x 8) 4k·Bit Registered TTL PROM ................. ; . . . . . . . . . .
DM77SR474B (512 x 8) 4k·Bit Registered TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM77SR476 (512 x 8) 4k·Bit Registered TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . ..
DM77SR476B (512 x 8) 4k·Bit Registered TTL PROM. . . . . . . . . . . . . . . . . . . . . . . . . . .
DM85S06 Open·Coliector Non·lnverting, 64·Bit (16 x 4) RAM ....................
DM85S07 TRI·STATE Non·lnverting, 64·Bit (16 x 4) RAM ........................
DM85S07A High Speed TRI·STATE Non·lnverting, 64·Bit (16 x 4) RAM. . . . . . . . . . . . .
DM85S68 16 x 4 Edge Triggered Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM86S64 Bipolar Character Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DM86S128 Bipolar Character Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . .
DM87SR25 (512 x 8) 4k·Bit Registered TTL PROM. . . . . . . . . . . . . . . . . . • . . . . . . . . . .
DM87SR25B (512 x 8) 4k·Bit Registered TTL PROM. . . . . . . . . . . . . . . . . . • . . . . . . . . .
15

22·10
22·24
21·44
21·24
21·20
21·20
21·24
21·26
21·~4

21·24
21·28
21·30
21·30
21·30
21·30
21·32
21·32
21·32
21·32
21·32
21·32
21·34
21·34
21·24
21·24
21·24
21·32
21·32
21·32
21·32
21·32
21·32
21·36
21·36
22·16
22·20
22·16
22·20
21-36
21·36
21·18
21·18
21·20
21·20
22·10
22·10
22·10
22·24
21·44
21·55
21·20
21·20

Alpha-Numerical Index (Continued)
DM87S1BO (1024 x 8) 8192-Bit TIL PROM ................................•...
DM87LS181 (1024 x 8) 8192-BitTIL PROM •............... .' ......•......... ,.
DM87S181 (1024 X 8) 8192-Bit TIL PROM ............. '...................... .
DM87S181A (1024 X 8) 819,2.Bit TIL PROM ........................•..........
DM87SR181 (1024 X 8) 8k·Bit Registered TIL PROM .......................... .
DM87S184 (2048 X 4) 8192-Bit TIL PROM ..................••................
DM87S185 (2048 X 4) 8192-Eilf TIL PROM .............. -. .................... .
DM87S185A (2048 X 4) 8192-Bit TIL PROM .................................. .
DM87S185B (2048 X 4) 8192-Bit TIL PROM .................................•.
DM87S190 (2048 X 8) 16,384-Bit TIL PROM ............•......................
DM87S190A (2048 X 8) 16,384-Bit TIL PROM ••...............................
DM87S190B (2048 X 8) 16,384-Bit TIL PROM ................................ .
DM87S191 (2048 X 8) 16,384-Bit TIL PROM .................................. .
DM87S191A (2048 X 8) 16,384-Blt TIL pAOM ................................ .
DM87S191 B (2048 X 8) 16,384.Bit TIL PROM .............•.. " ............... .
DM87S195A (4096 X 4) 16,384-Bit TIL PROM ................................ .
DM87S1958 (4096 x 4) 16,384-Bit TIL PROM ................ ~ ............... .
DM87S280 (1024 X 8) 8192-Bit TIL PROM ................................... .
DM87S281 (1024 X 8) 8192-Bit TIL PRoM ............... ; ................... .
DM87S281A (1024 X 8) 8192-Bit TIL PROM ......•..............•.•........•..
DM87S290 (2048 X 8) 16,384·Bit TIL PROM .................................. .
DM87S290A (2048 X 8) 16,384-Bit TIL PROM ...................... ; ......... .
DM81S290B (2048 X 8) 16,384-Bit TIL PROM ............. ; .................. .
DM87S291 (2048 X 8) 16,384·Bit TIL PROM ......•............................
DM87S291A (2048 X 8) 16,384-Bit TIL PROM ........ , ....................... .
DM87S291 B (2048 X 8) 16,384-Bit TIL PROM ................................ .
DM87S321 (4096 X 8) 32,768-Bit TIL PROM ........................... , ...... .
DM87S321A (4096 X 8) 32,768-Bit TIL PROM ................................ .
DM87S401 First·ln, First·Out (FiF'o) 64 X 4, 64 X 5 Serial Memories .......•.......
DM87S401A First·ln, First·Out (FiFo) 64 X 4, 64 X 5 Serial Memories ............. .
DM87S402 First·ln, First·Out (FiFo) 64 X 4, 64 X 5 Serial Memories .............. .
DM87S402A First·ln, First·Out (FIFo) 64 X 4, 64 X 5 Serial Memories ............. .
DM87S421 (4096 X 8) 32,768-Sit TIL PROM .................................. .
DM87S421 A (4096 X 8) 32,768-Bit TIL PROM .....................
DM87SR474 (512 X 8) 4k:Blt Registered TIL PROM .........•..................
DM87SR474B (512 X 8) 4k·Bit Registered TIL PROM .............•.............
DM87SR476 (512 X 8) 4k·Bit Registered TIL PROM ........................... .
DM87SR476B (512 X 8) 4k·Bit Registered TIL PROM .......•.............•.....
DP-XXX Advanced Graphic CRT ContrOller, AGCRTC ...... ; ...•...............
DP7j03 8-Bit TRI-STATE Bidii"ectional Transceiver .................•...........
DP73048 8-Bit TRI·STATE Bidirectional Transceiver ....•......................
DP7307 8-Bit TRI·STATE Bidirectional Transceiver ..................•..........
DP7308 8-Blt TRI-STATE Bidirectional Transceiver .........••..................
DP7310 Octal Latched Peripheral Drivers .................................. ..
DP7311 Octal Latched Peripheral Drivers ................................... .
DP8212 8-Bit Input/Output Port .......................................... ..
DP8212M 8-Bit Input/Output Port ......................................... ..
DP8216 4-Bit Bidirectional Bus Transceiver ............•.••.•................ '
DP8216M 4-Bit Bidirectional Bus Transceiver ................................ .
DP8224 Clock Generator and Driver ...................................... ..
DP82264-Bit Bidirectional Bus Transceiver ................................ ..
DP8226M 4-Bit Bidirectional Bus Transceiver ..............•.....•..........•
i

16

•••••••••••

21-24
21-26
21-24
21-24
21-28
21-30
21-30
21-30
21-30
21-32
21-32
21-32
21-32
21-32
21-32
21-34
21-34
21-24
21-24
21-24
21-32
21-32
21-32
21-32
21-32
21-32
21-36
21-36
22-16
22-20
22-16
22-20
21-36
21-36
21-18
21-18
21-20
21-20
5-104
2-5,2-6
2-5, 2-11
2-5,2-16
2-5,2-20
3-4
3-4
8-4
8-4
8-11
8-11
8-16
8-11
8-11

Alpha-Numerical Index (Continued)
DP8228 System Controller and Bus Driver .................................. .
8·22
DP8228M System Controller and Bus Driver ................................. .
8·22
DP8238 System Controiler and Bus Driver .................................. .
8·22
DP8238M System Controller and Bus Driver ................................. .
8·22
DP8303 8·BitTRI·STATE Bidirectional Transceiver ............................. . 2·5,2·6
DP8304B 8·Bit TRI·STATE Bidirectional Transceiver .......................... . 2·5,2·11
DP8307 8·Bit TRI·STATE Bidirectional Transceiver ............................ . 2·5,2·16
DP8308 8·Bit TRI·STATE Bidirectional Transceiver ............................ . 2·5,2·20
DP8310 Octal latched Peripheral Drivers ................................... .
3·4
DP8311 Octal latched Peripheral Drivers ................................... .
3·4
DP8340 Serial Bi·Phase Transmitter/Encoder ............................... .
9·3
DP8341 Serial Bi·Phase Receiver/Decoder .................................. .
9·12
DP8342 High·Speed Serial Transmitter/Encoder ............................. .
9·23
DP8343 High-Speed Serial Receiver/Decoder ............................... .
9·32
DP8350 Series CRT Controllers ........................................... .
5·6
DP8400 E2C2 Expandable Error Checker and Corrector ....................... .
7·72
DP8408 Dynamic RAM Controller/Driver .................................... .
7·26
DP8409 Multi·Mode Dynamic RAM Controller/Driver ......................... .
7·43
DP8419 High Speed Dynamic RAM Controller/Driver ..... , ................... .
7·64
DP8460 Data Separator ................................................. .
10·10
DP8464 Disk Pulse Detector ............................................. .
10·31
DP8466 Disk Data Controller ............................................. .
10·34
DP8480 10k ECLto TIL level Transl;3.tor with latch .......................... .
4·4
DP8481 TIL to 10k ECl level Translator with latch .......................... .
4·7
DP8482100k ECl to TIL level Translator with latch ......................... .
4·10
DP8483 TIL to 100k ECl level Translator with latch ......................... .
4·13
DP84240 Octal TRI·STATE MOS Driver ............. ; ....................... .
7·15
DP84244 Octal TRI·STATE MOS Driver ..................................... .
7·15
DP84300 Programmable Refresh Timer .................................... .
7·139
DP84312 Dynamic RAM Controller Interface Circuit for the NS16032 CPU ........ .
7·144
DP84322 Dynamic RAM Controller Interface Circuit for the 68000 CPU ........... .
7·152
DP84332 Dynamic RAM Controller Interface Circuit for the 8086
and 8088 CPUs ...................................................... .
7·167
DS0025C Two Phase MOS Clock Driver ..................................... .
6·4
DS00265 M Hz Two Phase MOS Clock Driver ................................ .
6·7
DS00565 M Hz Two Phase MOS Clock Driver ................................ .
6·7
DS1488 Quad Line Driver ................................................ .
1·7
DS1489 Quad Line Receiver .............................................. .
1·10
DS1489A Quad Line Receiver ........................ ~ .................... .
1·10
DS1603 Dual Line Receiver ............................................... .
1·25
DS1611 Dual Peripheral Driver ............................................ .
3·11
DS1612 Dual Peripheral Driver ................... " ........................ .
3·11
3·11
DS1613 Dual Peripheral Driver ............................................ .
3·11
DS1614 Dual Peripheral Driver .............................. , ............. .
6·17
DS1617 Bubble Memory Sense Amplifier ................................... .
6·24
DS1628 Octal TRI·STATE MOS Driver ...................................... .
4·16
DS1630 Hex CMOS Compatible Buffer ...................... '............... .
3·24
DS1631 CMOS Dual Peripheral Driver ...................................... .
DS1632 Dual Peripheral Driver ............................................ .
3·24
3·24
081633 Dual Peripheral Driver ............................................ .
DS1634 Dual Peripheral Driver ............................................. .
3·24
DS1644 Quad TIl·to·MOS Clock Driver ..................................... .
6·27
17

Alpha-Numerical Index (Continued)
OS1645 Hex TRI·STATE TIL·to·MOS Latch/Driver .............................
DS1647 Quad TRI·STATE MOS Memory I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1648 TRI·STATE TIL·to·MOS MultiplexerlDriver ......................... ;..
DS1649 Hex TRI·STATE TIL·to·MOS Driver ...................... ; . . • . . . . . . . . .
DS1650 Quad Differential Line Receiver ................................... ; .
DS1651 Quad High Speed MOS Sense Amplifier. . . . . . . • . . . . . . . . . . . . • . . . . .. . . .
DS1652 Quad Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1653 Quad High Speed MOS Sense Amplifier ........................ , . . . . .
DS1671 Bootstrapped Two Phase MOS Clock Driver . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1674 Quad TIL·to·MOS Clock Driver. . .. . . . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1675 Hex TRI·STATE TIL·to·MOS Latch/Driver .............................
DS1677 Quad TRI·STATE MOS Memory I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1678 TRI·STATE TIL·to·MOS Multiplexer/Driver ............................
DS1679 Hex TRI·STATE TIL·to·MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
DS1687 Negative Voltage Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS1691A (RS·4221RS·423) Line Driver with TRI·STATE ..........................
DS1692 TRI·STATE Differential Line Driver ........... :. . . . . . . . . . . . . . . . . . . . . . .
DS16147 Quad TRI·STATE MOS Memory I/O Register " . . . . . . . . . . . . . . . . . . . . . . . .
DS16149 Hex MOS Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . .
DS16177 Quad TRI·STATE MOS Memory I/O Register ..........................'
DS16179 Hex MOS Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS26LS31C Quad High Speed Differential Line Driver. . . . . . . . • . . . .. . . . . . . . . . . . .
DS26LS31M Quad High Speed Differential Line Driver. . . . . . . . . . . . . . . . . . . . . . . . .
DS26LS32C Quad Differential Line Receiver ........ ; . . . . . . . ... . . . . . . .. . . . . . .
DS26LS32AC Quad Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS26LS32M Quad Differential Line Receiver ..................... ; . . . . . . . . . . .
DS26LS33C Quad Differential Line Receiver .......... ; . .. . . . . . . . . . . . . . . . . . . .
DS26LS33AC Quad Differential Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .
DS26LS33M Quad Differential Line Receiver.. ...... ........... . .. .... ... .. ..
DS26S10 Quad Bus Transceiver ......•.................•...............'. . . .
DS26S11 Quad Bus Transceiver. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3245 Quad MOS Clock Driver·. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . . . . . . . ..
DS3486 Quad RS·422, RS·423 Line Receiver........................... .......
DS3487 Quad TRI·STATE Line Driver........... . .... ..•........ ...... ..... ..
DS3587 Quad TRI·STATE Line Driver. . .. . . .. .. . . . . . . . . . . . . . . . .. . . . .. . . . . . . . .
DS3603 Dual Line Receiver .... , ............•............. ;...............
DS3611 Dual Peripheral Driver ..•........... ~.. ........ ...... ....... .... ...
DS3612 Dual Peripheral Driver ................ ~., .... ,.............. .......
DS3613 Dual Peripheral Driver ........................................ ~....
DS3614 Dual Peripheral Driver... .................. ....•. ........... .......
DS3616 Bubble Memory Coil Driver ....•.•... : . . . . . . . . . . . . . . . ... . . . . . . .. . .. . .
DS3617 Bubble Memory Sense Amplifier. . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . .
DS3628 Octal TRI·STATE MOS Driver ............•...•.......... , . . . . . . . . . . .
DS3630 Hex CMOS Compatible Buffer ........................ ; . . . . . . .. . . . . .
DS3631 CMOS Dual Peripheral Driver . . .. .. . . . . . . . . . . . . • . . . . . . . . . . . . . . . . .. . .
DS3632 CMOS Dual Peripheral Driver.. . . .. • . .. .. . . . . . .. . . . . .. . . . . . . . . . . . . . .
DS3633 CMOS Dual Peripheral Driver ............... ; • .. . . .. . . . . .. . . . .. . . . . .
DS3634 CMOS Dual Peripheral Driver.. . . • . . . . . . . . . . . . . . .. . . . . . . . .. .. . . . . . . .
DS3644 Quad TIL·ta-MOS Clock Driver ......•..............................
DS3645 Hex TRI·STATE TIL·to·MOS Latch/Driver . . . . • . . . • . . . . . . . . . . . . . . . . . . . .
DS3647 Quad TRI·STATE MOS Memory I/O Register. . . . . . . . . . • . • • . . • • . . . . . . . • .
DS3648 TRI·STATE TIL·to·MOS Multiplexer/Driver. . . • . . . . . . . . . . . . . . . . . . . . . . . .
18

6·30
6·35
6·41
6·46
1·31
6·49
1·31
6·49
6·55
6·27
6·30
6·35
6·41
6·46
3·49
1·37
1·42
6·35
6-62
6·35
6·62
1·12
1·12
1·15
1·15
1·15
1·15
1·15
1·15
2·24
' 2·24
6·14
1·18
1·22
1·22
1·25
3·11
3·11
3·11
3·11
3·17
6·17
6·24
4·16
3·24
3·24
3-24
3·24
6·27
6-30
6·35
6·41

Alpha-Numerical Index (Continued)
DS3649 Hex TAl-STATE TTL-to-MOS Driver .•................................
DS3650 Quad Differential Line Aeceiver. . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . .
DS3651 Quad High Speed MOS Sense Amplifier. . . . . . .. .. . . .. .. . . . . . . . . . . . . ..
DS3652 Quad Differential Line Aeceiver. . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3653 Quad High Speed MOS Sense Amplifier. . . . . . . . . • . . . . . . . . . . . . . . . . . . . .
DS3654 Printer Solenoid Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3656 Quad Peripheral Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3658 Quad High Current Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3662 Quad High Speed Trapezoidal Bus Transceiver ...................... : .
DS36661EEE-488 GPIB Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3667 TAl-STATE Bidirectional Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3668 Quad High Current Peripheral Driver ... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3669 Quad High Current Peripheral Driver. . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . .
DS3671 Bootstrapped Two Phase MOS Clock Driver. . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3674 Quad nL-to-MOS Clock Driver. . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . .. ..
DS3675 Hex TAl-STATE TTL-to-MOS Latch/Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3677 Quad TRI-STATE MOS Memory I/O Register. . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3678 TRI-STATE TTL-to-MOS Multiplexer/Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3679 Hex TRI-STATE TTL-to-MOS Driver .•................................
DS3680 Quad Negative Voltage Relay Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3685 Hex TRI-STATE Latch .............................................
DS3686 Dual Positive Voltage Relay Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3687 Negative Voltage Relay Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS3691 (RS-422/RS-423) Line Driver with TRI-STATE ...........................
DS3692TRI-STATE Differential Line Driver. . . .. ... ......... . . . . .. . ...........
DS3695 Differential TRI-STATE Bus/Line Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . .
DS3696 Differential TRI-STATE Bus/Line Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . .
DS3697 Differential TRI-STATE Bus/Line Transceiver/Repeater. . . . . . . . . . . . . . . . . .
DS3698 Differential TRI-STATE Bus/Line Transceiver/Repeater. . . . . . . . . . . . . . . . . .
DS36147 Quad TRI-STATE MOS Memory 110 Register. . . . . . . . . . . . . . . . . . . . . . . . . .
DS36149 Hex MOS Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS36177 Quad TRI-STATE MOS Memory 110 Register. . . . . . . . . . . . . . . . . . . . . . . . . .
DS36179 Hex MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7640 Quad NOR Unified Bus Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
DS7641 Quad Unified Bus Transceiver ......................................
DS78C20 Dual CMOS Compatible Differential Line Receiver. . . . . . . . . . . . . . . . . . . .
DS78C120 Dual CMOS Compatible Differential Line Receiver. . . . ... . ..... .. .. ..
DS78L12 Hex TTL-MOS Inverterllnterface Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS78LS120 Dual Differential Line Receiver (Noise Filtering and Fail-Safe) . . . . . . . . .
DS7800 Dual Voltage Level Translator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . .
DS7810 Quad 2-lnput TTL-MOS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7811 Quad 2-lnput TTL-MOS Interface Gate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7812 Hex TTL-MOS Inverter ............................ : . . . . . . . . . . . . . . . .
DS7819 Quad 2-lnput TTL-MOS AND Gate ...................................
DS7820 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7820A Dual Line Receiver ..................................... , ........
DS7830 Dual Differential Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7831 Dual TRI-STATE Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS7832 Dual TRI-STATE Line Driver. ..... ........ ...... ... ... ... . . .... . . .....
DS7833 Quad TRI-STATE Bus Transceiver ......... .'. . . . . . . . . . . . . . . . . . . . . . . . .
DS7834 Quad TRI-STATE Bus Transceiver ...................................
DS7835 Quad TRI-STATE Bus Transceiver ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19

6-46
1-31
6-49
1-31
6-49
3-29
3-33
3-35
2-29
2-48
2-56
3-38
3-41
6-55
6-27
6-30
6-35
6-41
6-46
3-44
6-59
3-47
3-49
1-37
1-42
1-47
1-47
1-47
1-47
6-35
6-62
6-35
6-62
2-68
2-70
1-98
1-109
4-25
1-116
4-19
4-22
4-22
4-22
4-27
1-91
1-94
1-101
1-104
1-104
2-75
2-79
2-75

Alpha-Numerical Index (Continued)
D87836 Quad NOR Unified Bus Receiver ................................... .
D87837 Hex Unifie~ Bus Receiver .................... '..................... .
D87838 Quad Unified Bus Transceiver ................................ '..... .
D87839 Quad TRI·8TATE Bus Transceiver ........... ~ ...................... .
D87880 High Voltage 7·8egment Decoder/Driver .......•.......................
D87889 8·8egment High Voltage Cathode Driver (Active·High Inputs) ............ .
D87897 A 8·Digit High Voltage Anode Driver (Active·Low Inputs) ................ .
D88T26A 4·Bit Bidirectional Bus Transce.iver ................................ .
D88T26AM ~·Bit Bidirectional Bus Transceiver .............................. .
D88T28 4·Bit Bidirectional Bus Transceiver ................................. .
D88T28M 4·Bit Bidirectional Bus Transceiver ............ ; .................. .
D88614130/225 MHz Low Power Dual Modulus Prescaler ..................... .
D88615130/225 MHz Low Power Dual Modulus Prescaler ..................... .
D88616130/225 MHz Low Power Dual Modulus Prescaler ..................... .
D88617130/225 MHz Low Power Dual Modulus Prescaler ..................... .
D88621 275 MHz/1.2 GHz VHF/UHF Prescaler ............. " ................ .
088622500 MHz/1.2 GHz Dual Modulus VHF/UHF Prescaler .................. .
D88626120 MHz Divide·by·40 Prescaler .................................... .
D88627130/225 MHz Low Power Prescaler ................................. .
D88628130/225 MHz Low Power Prescaler ................................ ,.
D88629120 MHz Divide·by·1QO Prescaler ................................... .
D88640 Quad NOR Unified Bus Receiver .............. '..................... .
D88641 Quad Unified Bus Transceiver ..................................... .
D88642 Quad Transceiver ................................................ .
D88654 8·0utput Display Driver (LED, VF, Thermal Printer) ..................... .
D88656 Diode Matrix ................................................... .
D8866414·Digit Decoder/Driver with Low Battery ,Indicator' .................... .
D8866614·Digit Decoder/Driver ......... ; .............. ; .................. .
D88669 2·Digit BCD·to·7·8egment DecoderlDriver ............................ .
D88692 Printing Calculator Interface 8et ................................... .
D88693 Printing Calculator Interface 8et ................................... .
D88694 Printing Calculator Interface 8et ............. ; ..................... .
D888C20 Dual CM08 Compatible Differential Line Receiver ................... .
D888C120 Dual CM08 Compatible Differential Line Receiver .................. .
0888L12 Hex TIL·M08 Inverterllnterface Gate ............ 'f' • • • • • • • • • • • • • • • • •
0888L8120 Dual Differential Line Receiver (Noise Filtering and Fail·8afe) ........ .
D88800 Dual Voltage Level Translator. .............. : ...................... .
D888.10 Quad 2·lnput TIL·M08 Interface Gate ............................... .
D88811 Quad 2·lnput TIL·M08 Interface Gate ............................... .
088812 Hex TIL·M08 Inverter ............................................ .
D88819 Quad 2·lnput TIL·M08 AND Gate .................................. .
D88820 Dual Line Receiver ............................................... .
D88820A Dual Line Receiver ............................................. .
D88830 Dual Differential Line Driver ................................. ; ... ; ..
D88831 Dual TRI·8TATE Line Driver ......................................... .
D88832 Dual TRI·8TATE Line Driver .......................... ",' ............ .
D88833 Quad TRI·8TATE Bus Transceiver .......................... '........ .
D88834 Quad TRI·8TATE Bus Transceiver .................................. .
088835 Quad TRI·8TATE Bus Transceiver .' ................................. .
D88836 Quad NOR Unified Bus Receiver ................................... .
D88837 Hex Unified Bus Receiver ......................................... .
. D88838 Quad Unified Bus Transceiver ..................................... .
20

2·83
2·85
2·87
2·79
5·,149
5·160
5·160 .
2·89
2·89
2·89
2·89
11·23
11·23
11·23
11·23
11·33
11·36
11·27
11·30
11·30
11·27
2'68
2·70
2·72
5·113
5·113
5·117
5·120
5·123
5·126
5·126
5·126
1·98
1·109
4·25
1·116
4·19
4·22
4·22
4·22
4·27
1·91
1·94
1·101
1·104
1·104
2·75
2·79
2·75
2·83
2·85
2·87

Alpha-Numerical Index (Continued)
OS8839 Quad TRI-STATE Bus Transceiver .................................. .
OS8859A Open Collector Hex Latch LED Driver .............................. .
OS8861 MOS-to-LED 5-Segment Driver ..................................... .
OS8863 MOS-to-LEO 8-Digit Driver ......................................... .
OS8867 8-Segment Constant Current Driver ................................. .
OS8869A Open Collector Hex Latch LED Driver .............................. .
OS8870 Hex LED Digit Driver ............................................. .
OS8871 Saturating LED Cathode Driver .................................... .
OS8872 Saturating LED Cathode Driver .................................... .
OS8873 Saturating LED Cathode Driver .................................... .
OS8874 9-0igit Shift Input LED Driver ...................................... .
OS8877 6-0igit LED Driver ............................................... .
OS8880 High Voltage 7-Segment OecoderlDriver ............................. .
OS8881 Vacuum Fluorescent Display Driver ................................. .
OS8884A High Voltage Cathode DecoderlDriver ............................. .
OS8885 MOS-to-High Voltage Cathode Buffer ............................. '.. .
OS8887 8-0igit High Voltage Anode Driver (Active-High Inputs) ................. .
OS8889 8-Segment High Voltage Cathode Driver (Active-High Inputs) ............ .
OS8891A High Voltage Anode Driver (Active-Low Inputs) ...................... .
OS8897 A 8-0igit High Voltage Anode Driver (Active-Low Inputs) ................ .
OS8906 AM/FM Digital Phase-Locked Loop Frequency 8ynthesizer ............. .
088907 AM/FM Digital Phase-Locked Loop Frequency 8ynthesizer ............. .
OS8908 AM/FM Digital Phase-Locked Loop Frequency Synthesizer ............. .
OS8963 M08-to-LED 8-Digit Driver ......................................... .
OS8973 9~Digit LED Driver ............................................... .
088975 9-0igit LED Driver ................................. " ............. .
OS55107 Dual Line Receiver ........ ~ ..................................... .
0855108 Dual Line Receiver ........................... ; ................... .
OS55113 Dual TRI-STATE Differential Line Driver ... ' .......................... .
OS55114 Dual Differential Line Driver ...................................... .
OS55115 Dual Differential Line Receiver .................................... .
OS55121 Dual Line Driver ................................................ .
OS55122 Triple Line Receiver ............................................. .
0855325 Memory Driver ........................................... ' ...... .
DS55450 Dual Peripheral Driver ........................................... .
OS55451 Dual Peripheral Driver ........................................... .
D855452 Dual Peripheral Driver .................. : ...... '.................. .
OS55453 Dual Peripheral Driver ........................................... .
D855454 Dual Peripheral Driver ...............•.................... ~ ...... .
D855461 Dual Peripheral Driver ............................................ .
0855462 Dual Peripheral Driver ........................................... .
D855463 Dual Peripheral Driver .. ., ..................... ~ .................. .
OS55464 Dual Peripheral Driver ........................................... .
D855493 Quad LED 8egment Driver ....................................... .
OS55494 Hex Digit Driver ................................................ .
OS75107 Dual Line Receiver .............................................. .
OS75108 Dual Line Receiver ......................... '.' ................... .
OS75113 Dual TRI-STATE Differential Line Driver ............................. .
DS75114 Dual Differential. Line Driver ...................................... .
DS75115 Dual Differential Line Receiver .................................... .
OS75121 Dual Line Driver ................................................ .
0875122 Triple Line Receiver ............................................. .
21

2-79
5-133
5-136
5-136
5-139
5-133
5~141

5-143
5-143
5-143
5-145
5-147
5-149
5-152
5-156
5·158
5-160
5-160
5-164
5-160
11-4
11-10
11-16
5-136
5-166
5-166
1-25
1-25
1-52
1-57
1-61
1-66
1-68
6-66
3-51
3-51
3-51
3-51
3-51
3-62
3-62
3-62
3-62
5-109
5-111
1-25
1-25
1-52
1-57
1-61
1-66
1-68 .

Alpha-Numerical Index (Continued)
0875123 Dual Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75124 Triple Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75125 Seven-Channel Line Receiver ........................•..... : . . . . . . .
DS75127 Seven-Channel Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75128 Eight-Channel Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75129 Eight-Channel Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75150 Dual Line Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
DS75154 Quad Line Receiver ........................................ , . • . . .
DS75160A IEEE-488 GPIB Transceivers .....................................
DS75161A IEEE-488 GPIB Transceivers .....................................
DS75162A IEEE-488 GPIB Transceivers .....................................
DS75207 Dual Line Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . .
DS75208 Dual Line Receiver. . ...... ... ..... ...... . . ..... ..... . ... .. .... .. .
DS75325 Memory Driver ............•.... ; . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
DS75361 Dual TTL-to-MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75362 Dual TTL-to-MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75365 Quad TTL-to-MOS Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
DS75450 Series Dual Peripheral Driver ................ '.............. : . . .. . . .
DS75451 Dual Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75452 Dual Peripheral Driver............. ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75453 Dual Peripher~1 Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75454 Dual Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75461 Dual Peripheral Driver .. . . . . .. . . .. . . . . . . . . . . . . . . . .. . . . .. . . . . . .. . . .
DS75462 Dual Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • .
DS75463 Dual Peripheral Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75464 Oual Peripheral Driver .......... : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75491 MOS-to-LED Quad Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75492 MOS-to-LED Hex Digit Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75493 Quad LED Segment Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS75494 Hex Digit Driver. . . ........ . . .... . ..... .. ..... .. . . ..... .. ..... ...
Effortless Error Management .............................................
Error Correction the Hard Way. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDM2900 Farnily Applications Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
IDM2901A 4-Bit Bipolar Microprocessor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDM2901A-1 4-Bit Bipolar Microprocessor .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDM2901A-2 4-Bit Bipolar Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDM2902 Look-Ahead Carry Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDM2909A Microprogram Sequencer .•.....................................
IDM2910A Microprogram Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDM2911A Microprogram Sequencer ......................... ~ . . . . . . . . . . . . .
IDM2970516-Word by 4-Bit Two Port RAM/Register File. . . . . . . . . . . . . . . . . . . . . . . .
IDM29705A 16-Word by 4-Bit Two Port RAM/Register File. . . . . . . . . . . . . . . . . . . . . . .
IDM2980316-Way Branch Controller. . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDM29811 Next-Address Controller. . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . .
Programmable Array Logic Family Series 24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplification of 2-Bit Error Correction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Controllers Cover All RAMs from 16k to 256k. . . . . . . . . . . . . . . . . . . . . . .

22

1-71
1-73
1-76
1-76
1-80
1-80
1-84
1-87
2-61
2-61
2-61
1-25
1-25
6-66
6-73
6-78
6-83
3-51
3-51
3-51
3-51
3-51
3-62
3-62
3-62
3-62
5-106
5-106
5-109
5-111
7-134
7-124
23-72
23-4
23-4
23-4
23-21
23-24
23-34
23-24
22-27
22-27
23-51
23-57
24-27
7-127
7-20

~

Section 1
Transmission Line
Drivers/Receivers
TEMPERATURE RANGE

-55'Clo + 125'C

°DS26LS31M
° DS26LS32M
° DS26LS33M

DS3587
° DS1603
° DS1650
° DS1652
° DS1691 A
° DS1692

O'Clo +70'C
DS1488
DSl489
DS1489A
DS26LS31C
DS26LS32C
DS26LS32AC
DS26LS33C
DS26LS33AC
DS3486
DS3487
DS3603
DS3650
DS3652
DS3691
DS3692
DS3695
DS3696
DS3697
DS3698

°DS55107
°DS55108
°DS55113
°DS55114
°DS55115
DS55121
° DS55122

DS7820
° DS7820A
° DS78C20
° DS7830
° DS7831
° DS7832
° DS78C120
° DS78LS120
MM78C29
MM78C30

DS75107
DS75207
DS75108
DS75208
DS75113
DS75114
DS75115
DS75121
DS75122
DS75123
DS75124
DS75125
DS75127
DS75128
DS75129
DS75150
DS75154
DS8820
DS8820A
DS88C20
DS8830
DS8831
DS8832
DS88C120
DS88LS120
MM88C29
MM88C30
AN-22
AN-lOS
AN-214
AN-216

DESCRIPTION

PAGE
NUMBER

Quad Line Driver
Quad Line Receiver
Quad Line Receiver
Quad Differential Line Driver
Quad Differential Line Receiver
Quad Differential Line Receiver
Quad Differential Line Receiver
Quad Differential Line Receiver
Quad RS-422, RS-423 Line Receiver
Quad TRI-STATE Line Driver
Dual TRI-STATE Line Receiver
Quad Differential Line Receiver
Quad Differential Line Receiver
RS422-RS423 Line Drivers
TRI-STATE Differential Line Driver
Differential TRI-STATE Bus/Line Transceiver
Differential TRI-STATE Bus/Line Transceiver
Differential TRI-STATE Bus/Line Transceiver/
Repeater
Differential TRI-STATE Bus/Line Transceiver/
Repeater
Dual Line Receiver
Dual Line Receiver
Dual Line Receiver
Dual Line Receiver
Dual TRI-STATE Differential Line Driver
Dual Differential Line Driver
Dual Differential Line Receiver
Dual Line Driver
Triple Line Receiver
Dual Line Driver
Triple Line Receiver
Seven-Channel Line Receiver
Seven-Channel Line Receiver
Eight-Channel Line Receiver
Eight-Channel Line Receiver
Dual Line Driver
Dual Line Receiver
Dual Line Receiver
Dual Line Receiver
Dual CMOS Compatible Differential
Line Receiver
Dual Differential Line Driver
Dual TRI-STATE Line Driver
Dual TRI-STATE Line Driver
Dual CMOS Compatible Line Receiver
Dual Differential Line Receiver
Quad Single-Ended Line Driver
Dual Differential Line Driver
Integrated Circuits for Digital Data
Transmission
Transmission Line Characteristics
Transmission Line Drivers and Receivers
for EIA Standards RS-422 and RS-423
Summary of Electrical Characteristics of
. Some Well Known Digital Interface Standards

1-7
1-10
1-10
1-12
1-15
1-15
1-15
1-15
1-18
1-22
1-25
1-31
1-31
1-37
1-42
1-47
1-47
1-47
1-47
1-25
1-25
1-25
1-25
1-52
1-57
1-61
1-66
1-68
1-71
1-73
1-76
1-76
1-80
1-80
1-84
1-87
1-91
1-94
1-98
1-101
1-104
1-104
1-109
1-116
CMOS
CMOS
1-123
1-139
1-145
1-155

° Also available screened In accordance with MlkSTD-883 Class B. Refer to National Semiconductor's "The Reliability Handbook".

Selection Guide
UNBALANCED (COMMON-MODE) TRANSMISSION DRIVERS AND RECEIVERS

Unbalanced data transmission isn't recommended for long lines or fast data rates. Unbalanced
line receivers are sensitive to common-mode noise, such as ground I R noise and induced
reactive noise. Unbalanced line drivers should employ slew rate control to prevent near ,end
crosstalk to other wires in the cable. Receivers should employ response control and hysteresis.
Unbalanced data transmission was preferred because the cabling requires only one wire/
signal plus ground and the circuits were lower cost. New lower cost circuits available today
negate the last argument .. Many old interfaces such as RS-232 will continue to exist for
many years, and so will the application for unbalanced circuit5~

10k
4k

i=
!::.
:r:

RECOMMENDED
OPERATING
AREA

'"w
2:

-'

w

Line length is a function of data rate (baud) and slew rate. The recommended safe operating
area (line length vs baud rate is shown below for 24 AWG wire. It assumes that a differential
line receiver is used which is referenced at the driver ground. Also, it assumes that the
driver slew rate is between 0.1 to 0.3 times the reciprocal of the baud rate (minimum unit
interval). Otherwise, line lengths greater than 50 feet are not recommended. The exception
to line length is the 360 I/O coaxial interface. The coaxial provides improved grounding
and eliminates crosstalk.'
.

lk

.....

z

:::;

100

10
lk

100

10k

lOOk

DATA MODULATION (BAUD RATE)

UNBALANCED DRIVERS

~I
Propagation
Delay
(n's)

Output
Voltage
(V)

Output
Current
(mA)

200
60
200
200
10
10
20

±60r±9
±5
±2
±2
2.4
2.4
0.7

±6
±10
±20
±20
-100
-100

18
26
18
27

0.7
0.7
0.7
0.7

Slew Rate
Control

Party·Line
Application

Open·Collector
or
Open Emitter

10S/C
10S/C

Ves
Ves
Ves
Ves

TRI·STATE@

300

Ves

300
300
300
300

Ves
Ves
Ves
Ves

Emitter and
Collector
Collector
Collector
Collector

CEXT
CEXT

TRI·STATE
Emitter
Emitter

Co "ector

Power
Supplies
(V)
±90r±15
±12
5 or ±5
5 or ±5
5
5
5
5
5
5
5

Standard
RS·232
RS·232
RS·423
MIL 188·114
3601/0
3601/0

Circuitsl
Package

,Device Number
Commercial
Military
O°C to +70°C
--55°C to +125°C

4
2
4
4
2
2
2

OS1488
OS75150
OS3691
OS3692
OS75121
OS75123
OS75450

OS1691A
OS1692
OS55121

2
2
2
2

OS75451
OS75452
OS75453
OS75454

OS55451
OS55452
OS55453
OS55454

Comment

Page
No.
1·7

±10V common·mode range
50n coax. driver
50n coax, driver (IBM)

'·84
1·37
1·42
1·66
1·7
3·5
3·5
3·5
3·5
3·5

UNBALANCED RECEIVERS
Propagation
Delay
(ns)

Input
Range

(V)

(V)

Hysteresis
(mV)

Response

250
1150

CEXT

±25

CEXT
CEXT

30
30

3
3

22

3

±25

800

50
50
17
23

±0.2

±25
±25
±7
±7

50
50
100
100

±15
±15
±15
7
7

200
200
100
600
400

17

c"

Threshold
Sensitivity

±25

±0.2
±0.2
±0.2
±0.5
±0.5
±0.1

23
25
20
20
16
16
16

0.8
0.8
0.7
0.7
0.7

16

0.7 to 1.7

to
to
to
to
to

2
2
1.7
1.7
1.7

Control

Strobed or
TRI-STATE®

CEXT

Power
Supplies
(V)

RS·232
RS·232

4

5 or 15

RS·232
RS-423

4

5
5 to 15

TRI·STATE

5

TRI-STATE
TRI·STATE
TRI-STATE
TRI·STATE
Strobed
Strobed

~2/7

5
5
5
5
5
5
5
5

~2/7

~2/7

~2/7

Circuits/
Package

5
5

Strobed
Strobed

CEXT

Standard

4

RS-423
RS-423

2
2
4

RS-423
RS-423
RS·423
RS-423

4
4
4
4

3601/0
3601/0

3
3

3601/0

7

360 1/0

7 .

5

360 1/0

8

5

360 1/0

8

Device Number
Military
Commercial
DoC to +70°C
~55°C to +125°C
OS1489
OS1489A
OS75154
OS88LS120
OS88C120
OS26LS32C
OS26LS32AC
OS26LS33C
OS26LS33AC
OS3486
OS75122
OS75124
OS75125
OS75127
OS75128
OS75129

Comments

Preferential in applica·
tions to OS 1489
OS78LS120
OS78C120

Fail-safe
Fail·safe

1-10
1-10
1-87
1-116
1-109
1-15

OS26LS32M
Fail·safe
OS26LS33M
Fail·safe
OS55122
OS55124

Page
No.

50n coax. receiver
50D. coax. receiver (IBM)
IBM coax. receiver
IBM coax. receiver

IBM coax. receiver

IBM coax. receiver

1-15
1-15
1-15
1-18
1-68
1-73
1·76
1-76
1-80
1-80

ap!nD UO!I:lalas

Selection Guide
BALANCED (01 FFERENTIAL) TRANSMISSION LINE DRIVERS AND RECEIVERS_
10k

Balanced data transmission is applicable for long lines in the presence of high common-mode
noise. Balanced circuits don't generate much noise and are also not susceptible to commonmode noise, and therefore work well in long lines when cabled with other signals.
Line length is a function of data rate (baud) and the combination of I R drop and skin
effect. Refer to AN-' 08 and AN-22. The recommended safe operating area (line length vs
baud rate) is shown for 24 AWG wire.

4k

-i='....
%
I-

'"

1k

ell

RECOMMENDED " "
OPERATING
AREA

2

w
....

....w

I:IQ
100
<
(..)

~

-

10
1001t -

10k

1M

'"

-40

10M

DATA MODULATION (BAUD MTE)

BALANCED DRIVERS

~

./..
Propagation VOL (V)! VOH (V)! Party Line
TRI-STATE® Open-Collector
Delay (ns) IOl(mA) IOH(mA) Application

Power
Standard
Supplies (V)

Device Number
Circuits!
Military
Commercial
Package
O°C to +70°C -55°C to +125°C

Comments

Page
No..

10

0.5/40

1.8/-40

5

2

OS8830

OS7830

100

0.4/11

2.9/-57

5 or 15

2

MM88C30

MM78C30

CMOS comparator

CMOS

5 or 15

2

MM88C29

MM78C29

Non-inverting MM88C30

CMOS

5

2

OS8831

OS7831

5

2

OS8832

OS7832

5

2

OS75113

OS55113
OS55114

100

0.4/11

2.9/-57

10

0.5/40

1.8/-40

Yes

TRI·STATE

10

0.5/40

1.8/-40

Yes

TRI-STATE

13

0.4/40

Yes

TRI·STATE

.
OPtional

15

0.4/40

2/-40
2/-40

200

-2/20

2/-20

Yes

TRI-STATE

5 or

200

-2120

2/-20

Yes

TRI-STATE

5 or ±5

Optional

OS75114
OS3691

OS1691A

2

OS3692

OS1692

RS485
RS485

1
1

OS3695

RS·485 Transceiver

1-47

OS3696

RS-485 Transceiver

147

1

RS-485 Transceiver
RS-485 Transceiver

147

Yes

TRI-STATE

5

15

Yes

TRI-STATE

5

15

Yes

TRI-STATE

5

15

TRI-STATE
TRI·STATE

5
5

RS485
RS-485
RS422

1
4

OS3697
OS3698
OS26LS31C

TRI-STATE

5

RS-422

4

OS3487

12

0.5/40

2.5/-20

15

0.5/48

2/-50

Yes

1-104
1-52
1-57

2
RS·422

15

Yes
Yes

1-104
OS8831 without VCC clamp diode

2

5

±S

1-101

OS26LS31M
OS3587

1-37
±10V TRI·STATE common·mode
range

1-42

1-47
1-12
1-22

------

BALANCED RECEIVERS

Propagation
Delay (nsl

~

Threshold Common-Mode
Sensitivity
Range
IV)
(mVI

Hysteresis
(mVI

Power
Response
Strobed or
Supplies Standard
Control TRI-STATE®
(VI

Circuits!
Package

Device Number
Military
Commercial
O°C to +70°C --55°C to +125°C

Comments

Page
No_

40

±1000

±15

Yes

Strobed

5

2

OS8820

OS7820

1-91

30

±1000

±15

Yes

Strobed

5

2

OS8820A

OS7820A

1-94

60

±200

±10

50

Yes

Strobed

5 to 15

RS-422

2

OS88C20

OS78C20

CMOS compatible

1-98

60

±200

±10

50

Yes

Strobed

5 to 15

RS-422

2

OS88C120

OS78C120

Fail-safe, CMOS
compatible

1-109

50

±200

±10

50

Yes

Strobed

5

RS-422

2

OS88LS120

OS78LS120

Fail-safe

20

±500

±15

Yes

Strobed

5

2

OS75115

OS55115

17

±200

±7

100

TRI-STATE

5

RS-422

4

OS26LS32C

OS26LS32M

17

±200

±7

100

TRI-STATE

5

RS-422

4

OS26LS32AC

17

±500

±15

200

TRI-STATE

5

RS-422

4

OS26LS33C

17

±500

±15

200

TRI-STATE

5

RS-422

4

OS26LS33AC

25

±200

±10

80

TRI-STATE

5

RS-422

4

OS3486

10

±25

±3

TRI-STATE

±5

4

OS3650

OS1650

1-31

10

±25

±3

Strobed

±5

4

OS3652

OS1652

1-31

22

±200

+12, -7

'70

TRI-STATE

5

RS-485

1

OS3695

RS-485 Transceiver

22

±200

+12, -7

70

TRI-STATE

5

RS-485

1

OS3696

RS-485 Transceiver 1-47
RS-485 Transceiver 1-47

22

±200

+12, -7

70

TRI-STATE

5

RS-485

1

OS3697

22

±200

+12, -7

70

TRI-STATE

5

RS-485

1

OS3698

17

±25

±3

Strobed

±5

2

OS75107

17

±10

±3

Strobed

±5

2

OS75207

17

±25

±3

Strobed

±5

2

OS75108

17
17

±10

±3

Strobed

±5

2

OS75208

±25

±3

TRI-STATE

±5

2

OS3603

1-116
1-61
1-15

Fail-Safe

1-15

Fail-Safe

1-15

1-15

OS26LS33M

1-18

1-47

RS-485 Transceiver 1-47
1-25

OS55107

1-25
1-25

OS55108

1-25

I

1-25

OS1603

Note. Voltage comparators (such as the LM710) have good threshold sensitivity and good common-mode range and, in turn, also make good line receivers. These comparators generally use 2 power supplies

(±15V), which may not be available in some digital systems.

ap!n~

UO!I:»alas

~National

a

Transmission Line
Drivers/Receivers

Semiconductor

051488 Quad Line Driver
General Description

Features

The OS1488 is a quad line driver which converts
standard TTL input logic levels through one stage
of inversion to output levels which meet EIA
Standard No_ RS-232C and CCITT Recommendation V_ 24_

•
•
•
•
•

±10 rnA typ
Current limited output
Power-off source impedance
300.\1 min
Simple slew rate control with external capacitor
Flexible operating supply'range
Inputs are TTL/LS compatible

Schematic and Connection Diagrams
,..----.-----.--.----<>,'
Dual-In-Line Package

v-

v-

GND

TOPVIEW

Order Number DS14BBJ or DS14BBN
See NS Package J14A or N14A

1I4Cllcu,I

Typical Applications
RS232C Data Transmission

1/4081489/
TTL/DlL

114051488

DS1480A

--~-,

--1

Ie>--

TTL/OTL
__ -r--,

--...
--"L_
.,t.1---

---L_~

TTL/DTL

TTL/DTl

---((-1:==-o--+---,----+---f::'O-=:~_ , [ , l - - -

TTL

TTL

-.. -,(:;::-<>O---il-----l"----I----c(

. . _.r--

_"",:(-1:==

rHTERfACEDATA
TERMINAlEDUIPfIlHIT

"'Optional for noise filtering.

RS232C Data Transmission

MaS to TTL/LS Translator

1-10

Absolute Maximum Ratings

(Note 1)

The following apply for T A = 25°C unless otherwise specified.
Power Supply Voltage
Input Voltage Range
Output Load Current
Power Dissipation (Note 2)
Operating Temperature Range
Storage Temperature Range
Maximum Power Dissipation' at 25°C
Cavity Package
Molded Package

10V
±30V
20mA
lW
O°C to +75°C
~65°C to +150u C
1308 mW
1207 mW

'Derate cavity package 8.7 mW/oC above 2SoC; derate molded package 9.7 mW!"C above 2SOC.

Electrical Characteristics

(Notes 2, 3 and 4)

DS1489/DS1489A: The following apply for Vcc = 5.0V ±1%, O°C -:; TA ::; +75°C unless otherwise specified.
CONDITIONS

PARAMETER
VTH

Input High Threshold Voltage
V OUT ::; 0.45V,
IOUT= 10 mA

VTL

liN

VOH

Input Low Threshold Voltage

Input Current

Output High Voltage

DS1489
DS1489A

VouT22.5V
lOUT = -0.5 mA

MAX

UNITS

1.0
0.9

1.25

1.5

V

TA = 25°C

1.75
1.55

2.00

1.6
2.25

TA = 25°C

0.75

1.00

MIN
TA = 25°C

TVP

0.65

V

2.40

V
V

1.25
1.35

V
V

V IN = +25V
V IN = -25V

+3.6
-3.6

+5.6
-5.6

V IN - +3V
V IN = -3V

+0.43
-0.43

+0.53
-0.53

2.6

3.8

5.0

V

2.6

3.8

5.0

V

0.45

lOUT = -0.5 mA

V IN = 0.75V
Input - Open

VOL

Output Low Voltage

V 1N = 3.0V, lOUT = 10 mA

0.33

Isc

Output Short Circuit Curr~nt

V IN'= 0.75V

3.0

+8.3
-8.3

mA
mA
mA
mA

V
mA

Icc

Supply Current

V IN = 5.0V

14

26

mA

Pd

Power Dissipation

V IN = 5.0V

70

130

mW

Swi~ching

Characteri$tics

(VCC = 5V, TA = 25°C)

PARAMETER
tpdl

Input to Output "High"

CONDITIONS

TVP

MAX

RL = 3.9k. (Figure 1) (ac Test Circuit)

28

85

ns

RL = 390n, (Figure 1) (ac Test Circuit)

20

50

ns

110

175

ns

9

20

ns

MIN

UNITS

Propagation Delay
tpdO

I nput to Output" Low"
Propagation Delay

t,

Output Rise Time

tf

Output Fall Time

= 3.9k, (Figure 1) (ac Test Circuit)
,R L = 390n, (':igure 1) (ac Test Circuit)
RL

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range#l they are not meant to imply that the devices should be operated at tt'lese limits. The table of "Electrical Characteri~tics"
provides conditions for actual device operation.

1II0te 2; Unless otherwise specified minImax limits apply across the O°C to +7SoC temperature range for the DS1489 and DS1489A.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or.min on absolute value basis.
Note 4: These specifications apply for response control pin = open.

1-11.

~National

Transmission Line
Semiconductor
Drivers/Receivers
DS26LS31C/DS26L$31M Quad High Speed
Differential Line Driver
.

a

General Description

Features

The DS26LS31 is a quad differential line driver designed
for digital data transmission over balanced lines. The
DS26i..S31 meets all the requirements of EIA Standard
RS-422 and Federal Standard 1020. It is designed to
provide unipolar differential drive to twisted-pair or
parallel-wire transmission lines.

•
•
•
•
•
•

The circuit provides an enable and disable function
common to all four drivers. The DS26LS31 features
TRI-STATE® outputs and logically ANDed complementary outputs. The inputs are all LS compatible and
·are all one unit load.

•
•
•
•
•

The DS26LS31 features a power up/down protection
circuit which TRI-STATEs the outputs during power
up or down preventing erroneous glitches on the transmission lines.

•

Output skew - 2.0 ns typical
Input to output delay - 10 ns
Operation from single 5V supply
16-pin hermetic and molded DIP package
Outputs won't load line when VCC = 0
Four line drivers in one package for maximum
package density
Output short·circuit protection
Complementary outputs
.Meets the requirements of EIA Standard RS-422
Pin cpmpatible with AM26LS31
Available in military and commercial temperature
range
Glitch free power up/down

LOIJic Diagram
ENABLE

ENABLE.

GNO

VCC

OUTPUT
D2

OUTPUT
D1

Connection Diagram

OUTPUT
C2

INPUTA

INPUT B

INPUT C

INPUT 0

OUTPUT
C1

OUTPUT
.82

OUTPUT
81

Dual-In-Line Package
16 5V

INPUT A

15 INPUT D
CHANNEL A{
OUTPUTS

14

--11-----'

CHANNEL 0

13 } OUTPUTS

'---of--

ENABLE.

..l~=:::;-ln_~~1!.2 ENABLE
11
CHANNEL C

10 } OUTPUTS

INPUT 8
GNO

TOP VIEW

Order Number DS26LS31CJ, DS26LS31CN or
DS26LS31MJ
See NS Package J16A or N16A
1-12

OUTPUT
A2

OUTPUT
A1

Absolute Maximum Ratings

Operating Conditions

(Note 1)
7V
7V
5V
-o.25V t06V

Supply Voltage
Input Voltage
Output Voltage
Output Voltage (Power OFF)

Supply Voltage, VCC
DS26LS31M
DS26LS31
Temperature, T A
DS26LS31M
DS26LS31

Maximum Power Dissipation· at 2£fc

Cavity Package
Molded Package

1509mW
1476mW

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

-55
0

·C
·C

+125
+70

• Derate cavity package 10.1 mW/" C above 25" C; derate molded
package 11.9 mW/"C above 25·C.

Electrical Characteristics (Notes 2,3 and 4)
CONDITIONS

PARAMETER
VOH

Output High Voltage

10H = -20mA

VOL

Output Low Voltage

10L = 20 mA

V,H

Input High Voltage

V,L

Input Low Voltage

MIN

TYP

MAX

UNITS
V

2.5

V

0.5

V

2.0

-40

0.8

V

-200

f..lA

IlL

Input Low Current

V,N = 0.4V

IIH

Input High Current

V,N = 2.7V

20

f..lA

'I

Input Reverse Current

V,N = 7V

'0

TRI·STATE Output Current

I
I

VCL

Input Clamp Voltage

'SC

Output Short·Circuit Current

ICC

Power Supply Current

Switching Characteristics

0.1

mA

VO= 2.5V

20

f..lA

VO= 0.5V

-20

f..lA

-1.5

liN = -18 mA
-30

V

-150

mA

35

60

mA

TYP.

MAX

All Outputs Disabled
or Active
VCC= 5V, TA = 25°C

PARAMETER

CONDITIONS

MIN

UNITS

tPLH

I nput to Output

CL = 30 pF

10

15

ns

tpHL

I nput to Output

CL = 30 pF

10

15

ns

Skew

Output to Output

CL = 30 pF

2.0

6.0

ns

tLZ

Enable to Output

CL = 10 pF, 52 Open

15

35

ns

tHZ

Enable to Output

CL = 10 pF, 51 Open

15

25

ns

tZL

Enable to Output

CL = 30 pF, 52 Open

20

30

ns

tZH

Enable to Output

CL = 30 pF, 51 Open

20

30

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.

Note 2: Unless otherwise specified, minImax limits apply across the -55·C to +125·C temperature range for the DS26LS31M and across the
O·C to +70·C range for the DS26LS31. All typicals are given for VCC = 5V and TA = 25·C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise

specified.
Note 4: Only one output at a time should be shorted.

,

1-13

AC Test Circuit and Switching Time Waveforms
TEST
POINT

I

CL (INCLUDES
PROBE AND JIG
CAPACITANCE) _ '::"

75

NOle. S1 and S2 of load circuil are closed except where shown.

FIGURE 1. AC Test Circuit

DISABLE
INPUT 3V - - - - - , - - - - - - - - -.....
f= I MHz.lrSI5...
1.3V

1= 1 MHz. Ir S 15 .'.
IIS6 ••

11S6 •• OV

OV
IpZL

OUTPUT

IpLZ

OUTPUT
S2 OPEN

VOL-------~------------~J.

VOH-------r------------~·
OUTPUT
S10PEN
IpHZ

IpZH

FIGURE 2. Propagation Delays

FIGURE 3. Enable and Disable Times

Typical Applications

Two-Wir.e Balanced System, RS-422

DATA
OUTPUT

1-14

~

a

National,
'
Semiconductor

Transmission Line
Drivers/Receivers

DS26LS32C/DS26LS32M, DS26LS32AC,

DS26 LS33CI DS26LS33M, DS26LS33AC
Quad Differential Line Receivers
General Description

Features

The DS26LS32 and DS26LS32A are quad differential line
receivers designed to meet the RS-422, RS·423 and Fed·
eral Standards 1020 and 1030 for balanced and unbal·
anced digital data transmission.

• High differential or common·mode input voltage
ranges of ± 7V on the DS26LS32 and DS26LS32A and
± 15V on the DS26LS33 and DS26LS33A
• ± 0.2V sensitivity over the input voltage range on the
DS26LS32 and DS26LS32A, ± 0.5V sensitivity on the
DS26LS33 and DS26LS33A
• Input fail·safe circuitry on the DS26LS32A and
DS26LS33A
• DS26LS32 and DS26LS32A meet all requirements of
RS·422 and RS·423
• 6k minimum input impedance
• 100 mV input hysteresis on the DS26LS32 and
DS26LS32A, 200 mV on the DS26LS33 and DS26LS33A
• Operation from a Single 5V supply
• TRI·STATE drive, with choice of complementary output
, enables for receiving directly onto a data bus
• Pin replacement for Advanced Micro Devices
AM26LS32

The DS26LS32 and DS26 LS32A have an input sensitivityof
200 mV over the input voltage range of ± 7V and the
DS26LS33 and DS26LS33A have an input sensitivity of
500 mV over the input voltage'range of ± 15V.
Both the DS26LS32A and DS26LS33A differ in function
from the popular DS26LS32 and DS26LS33 in that input
fail·safe circuitry is provided for each receiver, which
causes the outputs to go to a logic "1" state when the In·
puts are open.
'
Each version provides an enable and disable function
common to all four receivers and features TRI·STATE@out·
puts ,':ith ,8 mA sink capability, Constructed using low
power Schottky processing, these devices are available
over the full military and commercial operating tempera·
ture ranges.

Logic Diagram
ENABLE

!

GNO

ENABLE

IN OZ

!

IN 01

OUTPUT 0

vee

IN ez

IN el

OUTPUT e

IN BZ

IN Bl

IN AZ

IN AI

OUTPUT A

OUTPUT B

TL/F/5255·1

Connection Diagram

Truth Table

Dual·ln·Line Package

0

1
INPUTS A {

ENABLE

16 vee

Z

OUTPUT A
ENABLE

1

Input

Output

X

Hi·Z
1

VID  2.7V
= 8 rnA, VOL 2 0.5V

10
10
IIB(D)

Input Bias Current

VCC

= OV or 5.25V, Other Inputs at OV

VI - -10V

-3.25

mA

VI- -3V

-1.50

mA

= 3V
VI = 10V

1.50

mA

3.25

mA

VI

Input Balance

-7V:S; VIC:S; 7V, VIH(3C)
(Note 4)
10
10

= 2V,

= 0.4 rnA, VID = O.4V
= 8 mA, VID = -0.4V

10Z

Output TRI·STATE Leakage Current

= a.8V, VOL = 0.5V
VI(D) = -3V, VIL = 0.8V, VOH = 2.7V

lOS

Output Short·Circuit Current

VI(D)

IlL

Input Current - Low Logic State

VIL

2.7

-40

VI(D) = 3V, VIL

V
IJ.A

40

IJ.A

-100

mA

= 0.5V

-100

IJ.A

= 2.7V

20

IJ.A

100

IJ.A

~

Va

V
0.5

= '3V, VIH TRI·STATE = 2V,

-15

0, (Note 3)

(TRI·STATE Control)
IIH

VIC

Input Current - High Logic State

VIH

(TRI·STATE Control)

VIL - 5.25V

Input Clamp Diode Voltage

liN

= -10 mA

-1.5

V

85

mA

(TRI·STATE Control)
ICC

Power Supply Current

All Inputs VIL

= OV

Note 1: uAbsolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: All currents into device pins are shown as positive. out of device pins are negative. All voltages referenced to ground unless otherwise
noted.
Note 3: Only one output at a time should be shorted.
Note 4: Refer to EIA RS422{3 for exact conditions.

1·19

Switching Characteristics

(Unless otherwise noted, Vee = 5V and T A = 25°e.)

PARAMETER

MIN

TYP'

MAX

UNITS

Propagation Delay Time - Differential Inputs to Output
tPHL(D)

Output High to Low

19

35

ns

tPLH(D)

Output Low to High

19

30

ns

ns

Propagation Delay Time - TR I·STATE eontrol'to
Output
tPLZ

Output Low to TRI·STATE

23

35

tPHZ

Output High to TRI·STATE

25

35

ns

tpZH

Output TRI·STATE to High

18

30

ns

tpZL

Output TRI·STATE to Low

20

30

ns

AC Test Circuits and Switching Time Waveforms

TO SCOPE
(INPUT)

DIFFERENTIAL
INPUTS

...

~U~t

GENERATOR

It

~

TO SCOPE
(OUTPUT)

~
-

....
CL = 15 pF
_ .... INCLUDES PROBE
TANDSTRAY
CAPACITANCE

~ ~ 51
~

-::

TRI-STATE® CONTROL

1.5V

3V
INPUT

I

2V

.

,...Jr-1.5V
OV
tPLH(D) - -

~r

-- -

'--

VOH
OUTPUT

...,1,.3V
VOL
OV

f--tpLH(D)

\

1.3V

Input pulse characteristics:

t-rLH = tTHL = 6 ns (10% to 90%)
PRR = 1 MHz, 50% duty cycle

FIGURE 1. Propagation Delay Differential Input to Output

'·20

~

AC Test Circuits and Switching Time Waveforms
TO SCOPE
(INPUT)

PULSE
GENERATOR

(Continued)

TRI-STATE
CONTROL

It

TO SCOPE
(OUTPUT)
2k
DIFFERENTIAL
INPUTS
CL = 15 pF INCLUDES
PROBE AND STRAY
CAPACITANCE

T

ALL DIODES lN916 OR
EQUIVALENT

5k

•

1.5V for tpHZ and tpLZ
-1.5V for tPLZ and tpZL

1

Input pulse characteristics:
trLH = tTHL = 6 ns (10% to 90%)
PRR = 1 MHz, 50% duty cycle

tpHZ

tpLZ
3V

3V
EIN

INPUT
SWI CLOSED
• SW2 CLOSED

L

~~.::

EOUT

OV

~HZ

: I

tpZL

tpZH
3V
INPUT

SWI CLOSED
SW2 CLOSED

OV

3V
INPUT

SWIDPEN
SW2 CLOSED

VOH--Lt~H

SWI CLOSED
SW2 OPEN
tpZL
~5V

1.5V

-VBE

OUTPUT
VOL
OV

OV

FIGURE 2. Propagation Delay TRI·STATE Control Input to Output

1·21

!cen

.
~ Semiconductor
~National

Transmission Line
~rivers/Receivers

;;: 053587/053487 Quad TRI·5TATE® Line· Driver
co

, II)
C")

en
c

General Description

Features

National's quad RS-422 driver features four independent driver chains which comply with EIA Standards
for the electrical characteristics of balanced voltage
digital interface circuits_ The outputs are TR I-STATE®
structures which are forced to a high impedance state
when the appropriate output control pin reaches a logic
zero condition_ All input pins are PNP buffered to
minimize input loading for either logic one or logic zero
inputs. In addition, internal circuitry assures a high
impedance output state during the transition between
power up and power down.

•
•
•
•
•
•
•
•
•.

Four independent driver chains
TRI-STATE outputs
PNP high impedance inputs (PIA compatible)
Power up/down protection
Fast propagation times (typ 10 ns)
TTL compatible
Single 5V supply volt~ge
Output rise and fall times less than 20 ns (typ 10 ns)
Pin ,compatible with MC3487

•

Output skew - 2 ns typ

Block Diagram
JOo--o NON-INVERTING
"-~OUTPUTS

INPUT

JO......- Q INVERTING
OUTPUT
CONTROL D---t

Connection Diagram
Dual-In-Line Package
16 VCC

INPUT A

AlB CONTROL

OUTPUTS B {

INPUT B
GNO

TOP VIEW
Order Number DS3587J, DS3487J or DS3487N
See NS Package J16A or N16A

Truth Table
INPUT

CONTROL
. INPUT

NON-INVERTER
OUTPUT

H

H

H

l

l

H

l

H

X

l

Z

Z

L - Low logic state
H = High logic state

X = Irrelevant
Z

= TRI-STATE

(high impedance)

1-22

INVERTER
OUTPUT

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Storage Temperature

lead Temperature (Soldering, 10 seconds)

Operating Conditions

(Note 1)

Supply Voltage (V CC)
OS3587
OS3487
Temperature (TA)
OS3587
OS3487

8V
5.5V
-65°C to +150°C
300°C

Maximum Power Dissipation* at 2SoC

Cavity Package
Molded Package

1509mW
1476 mW

MIN

MAX

UNITS

4.5
'4.75

5.5
5.25

V
V

+125
70

°c
°c

-55
0

*Derate cavity package 10.1 mWrC above 2SoC; derate molded

package 11.9 mW/"C above 25°C.

Electrical Characteristics

(Notes 2, 3, 4 and 5)

PARAMETER
Vil

Input low Voltage

VIH

Input High Voltage

IlL

Input low Current

IIH

Input High Current

CONDITIONS

TYP

MAX
0.8

2.0
-200

/1 A

VIH = 5.5V

100

/1 A

Input Clamp Voltage

ICL = -18 rnA
IOL=48mA

VOH

Output High Voltage

IOH = -20 rnA

lOS

Output Short·Circuit Current

IOZ

Output Leakage Current (TRI·STATE)

-1.5

V

0.5

V

-140

rnA

Vo = 0.5V

-100

/1A

Vo = 5.5V

100

/1A

100
-100

/1 A
/1A

2.5

V

-40

IVos-Vosl

Difference in Output Offset Voltage

VT

Differential Output Voltage

IVTI-IVTI

Difference in Differential Output

/1 A

50

Output Low Voltage

,.
VCC =0

V

VIH = 2.7V

VCl

Output Leakage Current Power OF F

UNITS

V

Vil = 0.5V

VOL

IOFF

MIN

VO= 6V
Vo = -0.25V

0.4

V
V

2.0
0.4

V

Voltage
ICC

Power Supply Current

Switching Characteristics
PARAMETER'

Active

50

80

rnA

TRI·STATE

35

60

rnA

UNITS

,
Vee= 5V, TA = 25°e
TYP

MAX

tpHL

Input to Output

CONDITIONS

MIN

10

15

ns

tPLH

Input to Output

10

15

ns

tTHL

Differential Fall Time

10

15

ns

tTLH

Differential Rise Time

10

15

ns

tpHZ

Enable to Output

RL = 200n, CL = 50 pF

17

25

ns

tPLZ

Enable to Output

RL = 200n, CL = 50 pF

15

25

ns

tPZH

Enable to Output

RL = "", CL = 50 pF, 51 Open

11

25

ns

tPZL

Enable to Output

RL = 200n, CL = 50 pF, 52 Open

15

25

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply
that the devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
Note 2: Unless otherwise specified, min/max limits apply across the O°C to +70°C range for the OS3487. All typicals are given for VCC = 5V and
TA=25°C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise
specified.

Note 4: Only one output at a time should be shorted.
Note 5: Symbols and definitions correspond to EIA RS422, where applicable.
1-23

AC'Test Circuits and SWitching Time Waveforms
5V
3V---------,--------~

INPUT
OV---.1
INPUT
OUTPUT

1.5V

.".""","""T
CL=50pF
INCLUDES PROBE

1.5V

Input pulse: f = 1 MHz. 50%; tr = tf :5 15 ns.

FIGURE 1. Propagation Delays

5V

1/4053487
,J200

3V OR

~~~--

OV

__--~I--4~arSl
CONTROL
INPUT

CONTROL
INPUT

lk

tpZH

----t--t-_--

VOH---+"\

VOH

VOL _~-t-'+::.:r
tPLZ

VOL ----t--+---tpZL

OUTPUT

i!'iJTiiii'f

Input pulse: f = 1 MHz. 50%; tr = tf:5 15 ns.
51 and 52 closed except as noted.
eL includ~s probe and jig capacitance.

51 = open for tpZH
52 = open for tpZL

FIGURE 2. TRI-STATE Enable and Disable Delays

RL
100

3V

INPUT

INPUT

TEMCT2
CURRENT TRANSFORMER
OR'EQUIVALENT

1/4053487

OV

--.I
.z:.-----::i..90%

T- T- -

OUTPUT
(DIFHRENTIAL)

CL
15pF
INCLUDING PROBE
AND JIG CAPACITANCE

tTHL
Input pulse: f = 1 MHz, 50%; tr = tf:5 15 ns.

FIGURE 3. Differential Rise and Fall Times
1-24

enc
encn
Transmission Line .....
...... 0)
en
_

~National

OriverslReceivers

D Semiconductor

051603/053603, 0555107/0575107, 0555108/0575108,
0575207, 0575208 Dual Line Receivers
General Description

Features

The eight products described herein are TTL
compatible dual high speed circuits intended for
sensing in a broad range of system applications.
While the primary usage will be for line receivers
or MOS sensing, any of the products may effec·
tively be used as voltage comparators, level trans·
lators, window detectors, transducer preamplifiers,
and in other sensing applications. As digital line
receivers the products are appl icable with the
SN55109/SN75109 and SN55110/SN75110 com·
panion drivers, or may be used in other balanced
or unbalanced party·line data transmission systems.
The improved input sensitivity and delay specifi·
cations of the DS75207 and DS75208 make them
ideal for sensing high performance MOS memories
as well as high sensitivity line receivers and voltage
comparators. TR I·STATE® products enhance
bused organizations.
.

•

Diode protected input stage for power "OFF"
condition

•

17 ns typ high speed

•

TTL compatible
±10 mV or ±25 mV input sensitivity

•

±3V input common-mode range

•

High input impedance with normal Vcc , or
Vcc = OV

• Strobes for channel selection
TR I-ST ATE outputs for high speed buses

• Dual circuits
• Sensitivity gntd. over full common·mode range
•

Logic input clamp diodes-meets both "A" and
"8" version specifications

•

±5V standard supply voltages

Connection Diagrams
Dual-In-line Package

INPUT
IA

vcc -

INPUT
18

Dual-I n-Line Package

INPUT

INPUT

ourpUT

2A

28

2V

STROBE
2G

GND

OUTPUT

STROBE

STROBE

IV

lG

S

INPUT

INPUT

Vcc +

vcc-

2A

28

INPUT
IA

INPUT
18

Ne

OUTPUT
IV

OUTPUT
2Y

STROBE
lG

DISABLE
0

STROBE
2G

GND

TOPVlfW

TOPVIEW

Order Number DS55107J, DS75107J,
DS55108J, DS75108J, DS75207J
or DS75208J
See NS Package J14A

Order Number DS1603J or DS3603J
See NS Package J14A

Order Number DS75107N, DS75108N,
DS75207N or DS75208N
See NS Package N14A

Order Number DS3603N
See NS Package N14A

Product Selection Guide
TEMPERATURE~

PACKAGE-+
INPUT SENSITIVITV-+

---Jjsoc::; T A

~ +125°C

CAVITY alP
±25mV

aOc ::;TA

:5+7O°C

CAVITY OR MOLDED DIP
±25mV

±10mV

0575107
0575108
DS3603

0575207
0575208
053604

OUTPUT LOGICl
TTL Active Pull-up
TTL Open Collector
TTL TAI·STATE

0555107
0555108
D51603

1·25

...... ~
en
en
I\) en

"'............

~

o
"'......

Input protection diodes are incorporated in series
with the collectors of the differential input stage.
These diodes are useful in certain applications
that have mUltiple VCC+ supplies or VCC+ sup·
plies that are turned off.

vcc +

,PO 0

0_

•

•

..... W

00)

co

,..:0

Absolute Maximum Ratings

,...Lt)
Lt) .....

Supply Voltage, Vcc +
Supply Voltage, VccDifferential Input Voltage
Common Mode Input Voltage
Strobe Input Voltage
Storage Temperature Range

ON

.....

,..:

-0

Lt)N
Lt)Lt)

('I) .....

OaS
COo

~soc

(Notes 1, 2 and 3)
130BmW
1207mW
300°C

·Derate cavity package B.7 mW,oC above 25°C; derate
molded package 9.7 mWrC above 25°C.

Operating Conditions

('I),...

0575107,0575207
0575108, 0575208
053603

0555107,
0555108,
051603

-

CO Lt)
.....

UiC::g

Maximum Power Dissipation * at 250 C
Cavity Package
Molded Package
Lead Temperat~re (Soldering, 10 secl

7V
-7V
±6V
±SV
S.SV
to +IS0°C

MIN

NOM

MAX

MIIII

Supply Voltage VCC +

4.SV

.SV

S.SV

4.7SV

NOM
SV

MAX
S.2SV

Supply Voltage VCC -

-4.SV

·SV

-S.SV

--4.7SV

-SV

-S.2SV

Operatmg Temperature Range

-SSvC

to

+12S"C

O°C

to

+70°C

Note 1: "Absolute Maximum Ratings" are those values beyond which the safetY of the device,cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
'" provides conditions for actual device operation.

Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125D C temperature range for the 051603, 0555107 and 0555108
and across the oDe to +70°C range 'for the 053603, 0575107, 0575108. All typical values are for TA = 2SDe and Vee 5V:
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
I:::

Typical Applications
line Receiver Used in a Party-line or Data·Bus System
RECEIVERS

TWlSTEO'''I''
TR"IIISMlssrOILL
LINE

'0'

U.,..Iwn ..
DS1S1IJ(DS15U.

orDS3803
LIn.•••i... lIl
SIU5lotfSlllJS1111
... 0$1131

DRlvt:RS

line Receiver Used in MOS Memory System

"LTD MOS.

MOSTOTTLAEtElVEflSIOS3lQtl

MllUUMOSMEMOAY AARAY

DRIVERS

1-26

Schematic Diagrams
OS55107/0S75107,OS75207
OS55108/0S75108,OS75208

vcc+o--...- ....--~~-1I-....- ....- - - - -....--~~-.... - - - - - 00-1
~
lZO:::

900
'80

1.6k

'00

4k
8.5k

"

.t'-----,
~

.....r

'''-;

I

~ . . - ..

I

,

~4k
I

INPUTS

I

I

I
:
I

OUTPUT

INPUT A 0 - - - + - - - - '

" I"
'----4-...

----oSTROIIE G
. .- - -. . .- - -_ _oQSTROBES

vcc -o---. .- - - - 4 I -....._ _..._ _ _ _ _ _....

Note 1: l/Z of the dualcin:ultls'shown.
Note 2: '"'ndlcates connectLons common to second half of dual c;rcU/ t.
Note 3: Components shown with dash hnesare applicable t~ the D555101, OS75107 and 0575207 onlv.

OS1603/0S3603

OUTPUT

INPUTS

INPUT A

0---+----1
..--+--+~----t-~~--4~GND
3k

' - - - -...----+--oSTR08E G

Jk

Uk

DISABLE D

------...J

vcc-o---...---~.........I - -...

Notet: 112 of the dual circuit is shown.
Note 2: *lndicate5 connections common to second half of duaJ Clr1:oit

1-27

055510710575107, 055510810575108
Electrical Characteristics
PARAMETER
IIH

IlL

IIH
IlL

CONDITIONS
Vce+ = Max, V ce- = Max,

Into Al, Bl, A2 or B2

V IO = 0.5V, Vie = -3V to 3V

Low Level Input Current

Vce+ = Max, Vec- = Max,

Into Al, Bl, A2 or B2

V lD = -2V, VIC = -3V to 3V

High Level Input Current
Into Gl or G2

Vcc+ = Max,
V cc- = Max

Low Level Input Current

Vce+ = Max, Vcc- = Max,

Into Gl or G2

VILIS) = O.4V

Low Level I nput Current Into S

TYP

MAX

UNITS

30

75

/lA

-10

/lA

40
1

/lA
mA

-1.6

mA

l VIH(SJ= 2.4V

IVIH(S) - Max Vcc+

IV IHIS) = 2.4V

Vce+ = Max,

IVIH(S) = Max Vee+

Vce- = M~x
IlL

MIN

High Level Input Current

High Level Input Current Into S

IIH

.

(TMIN :S;TA :S;TMAx )

Vcc+ = Max, V ee- = Max
VILIS) = 0.4V

V OH

High Level Output Voltage

Low Level Output Voltage

High Level Output Current

Vec+ = Max, Vee- = Max,

VI

High Logic Level Supply

Vec+ = Max, Vce- = Max,

Current From V cc

V IO = 25 mY, T A = 25°C

High Logic Level Supply
Current From V cc

Vcc+ = Max, V ce- = Max,
V IO = 25 mY, TA = 25°C

Input Clamp Voltage on G or S

Vcc+ = Min, V ee- = Min,

-18

liN = -12 rnA, T A = 25°C

5witching Characteristics

Propagation Delay Time, Low to
High Level, From Differential
I nputs A and 8 to Output

If.HL(O)

Propagation Delay Time, High to
Low Level, From Differential
Inputs A and B to Output

If.LH(S)

CONDITIONS

/lA

-70

mA

18

30

mA

-8.4

-15

rnA

-1

-1.5

V

MIN

TYP

MAX

UNITS

(Note 3)

17

25

ns

(Note 4)

19

25

ns

RL = 3900, CL = 50 pF, (Note 3)
(Note 4)
(Note 1)

17

25

ns

19

25

ns

RL = 3900, CL = 50 pF

Propagation Delay Time, High to
Low Level, From Strobe Input G

"

RL = 3900, CL = 50 pF,

or S to Output

RL = 3900, CL = 50 pF

or S to Output
Note 1:
. Note 2:
Note 3:
Note 4:

250

(Note 1)

Propagation Delay Time, Low to
High Level, From Strobe Input G

tpHL(S)

V

(Vce+ = 5V, Vcc- = --5V, TA = 25~C)

PARAMETER
If.LH(O)

0.4

,

(Notes 2 and 3)

IccH-

mA

V

Vec+.= Min, Vcc- = Min

Short Circuit Output Current

IccH+

-3.2

2.4

V OH = Max Vee+. (Note 4)
los

mA

Vcc+ = Min, Vce- = Min,
ISINK = 16 mA, V IO = -25 mY,
VIC = -3V to 3V

10H

/lA

2

Vcc+ = Min, Vee- = Min,
I LOAO = -400/lA, V IO = 25 mY,
VIC = -3V to 3V, (Note 3)

VOL

80

(Note 3)

10

15

ns

(Note 4)

13

20

ns

(Note 3)

B

15

ns

(Note 4)

13

20

ns

Differential input is +100 mV to -100 mV pulse. Delays read from 0 mV on input to 1.5V on output .
Only one output at a time should be shorted.
0855107/0875107 only.
0555108/0875108 only.

1-28

-

c.no
c.nC/)

-c.n ...._

0575207, 0575208
Electrical Characteristics
PARAMETER
IIH

IlL

IIH

IlL

MIN

High Level I nput Current

Vee+ = Max, V ee- = Max,

Into Al, Bl, A2 or B2

V ID = 0.5V, Vie = -3V to 3V

Low Level Input Current
Into Al, Bl, A2 or B2

Vee+ = Max, Vee- = Max
V ID = -2V, Vie = -3V to 3V

High Level Input Current

Vee+ = Max,

Into Gl or G2

Vee- = Max

Low Level I nput Current

Vee+ = Max, Vee- = Max,

Into Gl or G2

VILIS) = 0.4V

IVIHISI

Vee+ = Max,

Low Level Input Current Into S

=;

MAX

UNITS

30

75

J.lA

.9J0
""JIJ

-10

J.lA

0_

40

J.lA
mA

High Level Output Voltage

1
-1.6

2.4V

I V IH1S) - Max Vee+

Vee+ = Max, V ee- = Max,

Low Level Output Voltage

VOL

80

J.lA

2

mA

-3.2

mA

2.4

V

Vee+ = Min, V ee- = Min,
0.4

' SINK = 16 mA, V 10 = -10 mV,
Vie = -3V to 3V
10H

High Level Output Current

Vee+ = Min, V ee- = Min,
V OH = Max V ee +, (Note 4)

los

Short Circuit Output Current

Vee+ = Max, Vee- = Max
(Notes 2, 3 and 4)

leeH+

'eeH-

-18

J.lA

-70

mA

18

30

mA

mA

High Logic Level Supply

Vee+ = Max, Vee- = Max,
VID = 10mV, TA = 25°C

High Logic Level Supply

Vee+ = Max, Vee- = Max,
V ID = 10 mV, T A = 25°C

-B.4

-15

Vee+ = Min, V ee- = Min,
liN = -12 mA, TA = 25°C

-1

-1.5

TYP

MAX

UNITS

RL = 470n, CL = 15 pF, (Note 1)

35

ns

RL = 470n, CL = 15 pF, (Note 1)

20

ns

RL = 470n, CL = 15 pF

17

ns

RL = 470n, CL " 15 pF

17

ns

Input Clamp Voltage on G or S

5witc::hing Characteristics

(Vee+

PARAMETER
tpLHiD)

250

V

Current From Vee

Current From Vee
VI

mA

Vee+ = Min, V ee-"; Min,
' LOAD = -400J.lA, VID = 10 mV,
Vie = -3V to 3V, (Note 3)

V

= 5V, vce- = --5V, TA = 25°C)
CONDITIONS

MIN

Propagation Delay Time, Low·to·
High Level, From Differential
I nputs A and B to Output

tPHLIDI

Propagation Delay Time, High·to·
Low Level, From Differential
I "puts A and B to Output

tpLHIS)

Propagation Delay Time, Low-toHigh Level, From Strobe Input G
or S to Output

tpHLisl

Propagation Delay Time, High-toLow Level, From Strobe Input G
or S to Output

Note 1:
Note 2:
Note 3:
Note 4:

Differential input is +10 mV to -30 mV pulse. Delays read from 0 mV on input to 1.5V on output.
Only one output at a time should be shorted.
0575207 only.
0575208 only.

1-29

c.nc.n
Nc.n

.:"I""

VILIS) = O.4V
V OH

00)

TYP

Iv IHIS) = 2.4V
I VIHIS) = Max Vee+

Vee- = Max
IlL

.... W

CONDITIONS

High Level Input Current Into S

IIH

""0)

(O°Cs;;TA s;;+70°C)

""c.n
c.n ....
NO

0"""
CO

co
...,:0
oC\l
.... It)

OS1603IOS3603
Electrical Characteristics

It)"'"

,.......,:
-0
1t)C\I
It)It)
~,....

PARAMETER
I'H

I'L

Oed'

COo
('I) ....

-CO,....
It)

0ct8

(T M1N STA STMAX )

I'H
I,L

CONDITIONS

High Level Input Current

Vee+ = Max, V ee- = Max,

Into A1, 61, A2 or B2

V ,D = 0.5V, V'c = -3V to 3V

Low Level Input Current

Vee+ = Max, V ee- = Max,

Into A1, B1, A2 or B2

V ,D = -2V, Vie = -3V to 3V

'VIIN

TYP

MAX

UNITS

30

75

p.A

-10

p.A

High Level Input Current

Vcc+ = Max,

V'HIS) = 2.4V

40

p.A

Into G1, G2 or D

'vee- = Max

V ,HIS) - Max Vee+

1

rnA

Low Level Input Current Into D

Vee+ = Max, Vee- = Max,

-1.6

rnA

V, LID I = 0.4V
I,L

Low Level I nput Current

Vcc+ = Max,

Into G1 or G2

Vcc-

=

Max.

V'LIG) = 0.4V
V OH

High Level Output Voltage

V cC+

,

V ,HID ) = 2V

-40

p.A

V, LID) = O.BV

-1.6

rnA

= Min, V cc- = Min,

ILOAD = -2 rnA, V ,D = 25 mV

2.4

V

V,LID) = O.BV, V'c = -3V to 3V
VOL

= Min, Vcc- = Min,
ISINK = 16 rnA, V ,D =-25 mV,

Low Level Output V,?ltage

Vcc+

0.4

V

V OUT = 2.4V

40

p.A

V OUT = O.4V

-40

p.A

-70

rnA

V, LID) = O.BV, Vie = -3V to 3V .
100

Output Disable Current

Vcc+

= Max,

V ee- = Max
V'HID) = 2V
los

ICCH+

Short Circuit Output Current

Vee+ = Max, V'LID) = O.BV,
V ee- = Max, (Note 2)

High Logic Level Supply

Vee+ = Max, V ec- = Max,
V ,D =25mV, TA = 25°C

2B

40

rnA

Current From Vec-

Vee+ = Max, Vee- = Max,
V 'D = 25 mV, TA = 25°C

-8.4

-15

rnA

Input Clamp Voltage on G or D

Vcc+ = Min, V cc- = Min,

-1

-1.5

TYP

MAX

UNITS

RL = 390n, CL = 50 pF, (Note 1)

17

25

ns

RL = 390n, CL = 50 pF, (Note 1)

17

25

ns

RL = 390n, CL = 50 pF

10

15

ns

RL = 390n, CL = 50 pF

B

15

ns

RL = 390n, CL = 5 pF

20

ns

RL = 390n, CL = 5 pF

30

ns

RL = 1.k to OV, CL = 50 pF

25

ns

RL = 390n, CL = 50 pF

25

ns

Current From V CC+

leeH-

V,

High Logic Level Supply

-1B

liN = -12 rnA, TA = 25°C

Switching Characteristics

(Vee+ = SV, V ee- = -5V, TA = 2Soc)

PARAMETER
tpLHID)

V

CONDITIONS

MIN

Propagation Delay Time, Low·to·
High Level, From Differential
Inputs A and B to Output

tpHLID)

Propagation Delay Time, High·to·
Low Level, From Differential
Inputs A and B to Output

tpLHIS)

Propagation Delay Time, Low·to·
High Level, From Strobe Input G
to Output

tpHLIS)

Propagation Delay Time, High·to·
Low Level, From Strobe Input G
to Output

t. H

Disable Low·to·High to Output.
High to Off

toH

Disable Low·to·High to Output
Low to Off

tH'

Disable High·to·Low to Output
Off to High

tHO

Disable High·to·Low to Output
Off to Low

Not. 1: Differential input is +100 mV to -100 mV pulse. Delays read from 0 mV on input to 1.5V on output.
Note 2: Only one output at a time should be shorted.

1·30

c

~National

Transmission Line ~
Drivers/Receivers (J)

051650/053650, 051652/053652

-

Quad Differential Line Receivers

P

~ Semiconductor

CAl

(J)

UI

c

General Description
this configuration the 051652/0S3652 provides the
"ANO" function. All addresses have to be true before
the output will go high. This scheme eliminates the need
for an "ANO" gate and enhances speed throughput for
address decoding.

The 051650/053650 and 051652/053652 are TTL
compatible quad high speed circuits intended primarily
for line receiver applications. 5witching speeds have
been enhanced over conventional line receivers by the
use of 5chottky technology, and TRI·5TATE® strobing
is incorporated offering a high impedance output state
for bussed organizations.

Features

The 051650/053650 has active pull-up outputs and
offers a TRI-5TATE strobe, while the 051652/053652
offers open collector outputs providing implied "ANO"
operation.

•
•
•
•
•
•

The 051652/053652 can be used for address decoding
as illustrated below. All outputs of the 051652/053652
are tied together through a common resistor to 5V. In

Connection Diagram

High speed
TTL compatible
Input sensitivity
±25 mV
TRI-5TATE outputs for high speed busses
5tandard supply voltages
±5V
Pin and function compatible with MC3450 and
MC3452

Truth Table

Dual-In-Line Package

vee

-IN B

+IN BOUT B

VEE

OUT 0

+IN 0

-IN D

OUTPUT
INPUT

STROBE

VID;:::25 ri1V

-25 mV -:; VID -:; 25 mV

VID -:; -25 mV

-IN A

+IN A

OUT A

STB
OUT C
TOP VIEW

+IN C

-IN C

DND

L = Low Logic State
H = High Logic State

Order Number DS1650J, DS1652J,
0S3650J, DS3652J,
OS3650N or DS3652N
See NS Package J16A or N16A

OS16501

OS16521

OS3650

OS3652

L
H

H

Open

Open

Open

L

X

X

H

Open

Open

L

L

L

H

Open

Open

Open = TRI-STATE
X = Indeterminate State

Wired "OR" Oata Selecting Using TRI-STATE Logic

Typical Applications

¢

STROBE

Implied "AND" Gating
oS16501
OS3650

~

f-o-

500

9

STROBE

ADD 100+o-f-1Y

OATA
OUTPUT

OS16501
053650
AOo Zo-+o-r-IY
OATA
LINES
OS16501
OS3650

AOo 3o-+o-tr-iY

AOo 40---0-+--1/'

~

STROBE

~h-o---oOUTPUT

.J

OS16501
OS3650
01

QZ

Q3

STROBE

1·31

6-0 Q4

~
~

f-o-

~

(J)

CAl

(J)

~

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Power Supply Voltages

d'
11)

-Cii
CO
M
CO

c

VCC
VEE
Differential-Mode Input Signal Voltage
. Range, V IDR
Common-Mode Input Voltage Range, VICR
Strobe Input Voltage, VJ(S)
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

Supply Voltage, VCC
OS1650,OS1652
OS3650,OS3652
Supply Voltage, VEE
.OS1650,OS1652
OS3650, OS3652
Operating Temperature, TA
OS1650,OS1652
OS3650, OS3652
Output Load Current, IOL
Oifferential-Mode Input
Voltage Range, VIDR
Common·Mode Input
Voltage Range, VICR
Input Voltage Range (Any
Input to GNO), VIR

+7.0VOC
-7.0VOC
±6.0 VOC
±5.0 VOC
5.5V OC
-65°C to +150°·C
300°C

Maximum Power Dissipation* at 2SoC

Cavity Package
Molded Package

1509mW
1476mW

"Derate cavity pac'bage 10.1 mypOC above 25°C; derate molded
package 11.8 mWI C above 25 C.

Electrical Characteristics

MIN

MAX

UNITS

4.5'
4.75

5.5
5.25

VOC
VOC

-4.5
-4.75

-5.5
-5.25

VOC
VOC

-55
0

+125
+70
16

°c
'c
mA

-5.0

+5.0

VOC

-3.0

+3.0

VOC

-5.0

+3.0

VOC

(VCC = 5.0 VDC, VEE = -5.0 VDC, Min:::; T A:::; Max, unless otherwise noted) (Notes 2 and 3)
PARAMETER
VIS

CONDITIONS

=

(Common·Mode Voltage Range
-3V::; VIN::; 3V)
IIH(I)

High Level Input Current to
Receiver Input

IIL(I)

IIH(S)

MAX

UNITS

Low Level Input Current to
Receiver Input

±25.0

mV

(Figure 51

75

/1A

(Figure 61

-10

/1A

High Level Input Current to

(Figure 31

IIL(S)

Low Level Input Current to Strobe
Input

VOH

High Level Output Voltage

ICEX

High Level Output Leakage
Current

VOL

Low Level Output Voltage

Short·Circuit Output Current (Note 4)
Output Oisable Leakage Current
High Logic Level SUpply Current

High Logic Level Supply Current
from VEE

100

/1 A

VIH(S) - 2.4V,
053650, 053652

40

/1 A

VIH(S) = VCC

1

rnA

VIH(S) = O.4V

-1.6

rnA

OS1650,OS3650

lOS

from VCC

VIH(S) = 2.4V,
OS1650,OS1652

2.4

VOC

(Figure 11

10FF

IEEH

TYP

Min::; VCC::; Max
Min;::: VEE;::: Max

Strobe Input

ICCH

MIN

Input Sensitivity, (Note 5)

,

OS1652,OS3652

250

(Figure 11

OS3650, OS3652
OS1650,OS1652

0.45

(Figure 41

OS1650/0S3650

(Figure 71

OS1650
OS3650

(Figure 21

,

'(Figure 21

0.50
-18

-70

/1A

VOC
rnA

100
40

/1 A

45

60

rnA

-17

-30

rnA

/1A

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for 1I0perating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Elactrical Characteristics"
provides conditions for actual device operation.

Note 2: Unless otherwise specified, minImax limits apply across the O°C to +7rf'C range for the OS3650, OS3652 and the -55°C to +125°C
range for the OS1650, OS1652. All typical values are for T A = 25°C, VCC = 5V and VEE = -5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: A parameter which is of primary concern when designing with line receivers is. what is the minimum differential input voltage required
as the receiver input terminals to guarantee a given output logic state. This param~ter is commonly referred to as threshold voltage. It is well
known that design considerations of threshold voltage are plagued by input offset currents, bias currents, network source resistances; and voltage
gain. As a design-convenience, the OS1650, OS1652 and the OS3650, OS3652 are specified to a parameter called input sensitivity (VIS). This
parameter takes into consideration input offset currents and bias currents and guarantees a minimum input differential voltage to cause a given
output logic state with respect to a maximum source impedance of 200n at each input.
1-32

Switching Characteristics

(Vcc = 5 Voc, VEE = -5 Voc, T A = 25°C unless otherwise noted)

PARAMETER
tPHL(O)

tPLH(O)

TYP

MAX

High-to-Low Logic Level Propagation

CONDITIONS
OS 1650/0S3650

21

25

ns

Delay Time (Differential Inputs)

OS1652/0S3652

20

25

ns

(Figure 8)

Low-to-H igh Logic Level Propagation
Delay Time (Differential Inputs)

tPOH(S)

TRI-STATE to High Logic Level
Propagation Oelay Time (Strobe)

tPHO(S)

MIN

High Logic Level to TRI-STATE
Propagation Oelay Time (Strobe)

UNITS

OS 1650/0S3650

20

25

ns

OS 1652/0S3652

22

25

ns

OS1650/0S3650

16

21

ns

OS1650/0S3650

7

18

ns

OS 1650/0S3650

19

27

ns

OS1650/0S3650

14

29

ns

OS1652/0S3652

16

25

ns

OS1652/0S3652

13

25

ns

(Figure 9)
tPOL(S)

TRI-STATE to Low Logic Level
Propagation Delay Time (Strobe)

tPLO(S)

Low Logic Level to TRI-STATE
Propagation Oelay Time (Strobe)

tPHL(S)

High-to-Low Logic Level Propagation
Delay Time (Strobe)
(Figure 10)

tPLH(S)

Low-to-High Logic Level Propagation
Oelay Time (Strobe)

Electrical Characteristic Test Circuits
V1
V2

1

16

2

15-

;0-

3
4

O.IV

V3

~

0--0-0
leEX

\

Vl

VOH

081652/
083652

+2.975V
+2.975V
-3.0V

'CEX

V2
081652/
081652

081650/
081650

V3
OS1652/
081652

+3.0V

+2.975V

-2.975V

-2.975V

-3.0V

~
10

081650/
081650

+3.0V

+2.975V
-3.0V

+0.4 rnA
+0.4 rnA
-3.0V

GNO

+3.0V

+3.0V

-16 rnA

-3.0V

GND

GND

-16 rnA

Channel A shown under test. Other channels are tested similarly.

FIGURE ,_ ICEX, VOH and VOL
1-33

11

GND

GNO
GND
-3.0V

V4
081652/
DS1652

GNO
-3.0V

GND
-2.975V

+3.0V

MIN VEE

~

+3.0V

+3.0V

12

',,'''OC

+3.0V
-2.975V

-3.0V

VOL

051650/
083650

;,

±

~~

0516'J
. 053650 ":'

081650/
083650

053652

~

051652/
053652

'"

0516521

7

V4

MAX

0516501
053650,

~6

~

MIN Vee

~
c.o
c.o

-lii

Electrical Characteristic Test Circuits (Co~i~i

CW)

3Vo-~----------------------,

leCH
16

c

16

MAl,(VIII:

15

cS
IJ)

OS16501
OS3650,
OS16521
OS3652

c.o
CW)
c.o

OS16501
OS3650,
OS1652/
OS3652

MI\XV.E!t

MAX
Vee
3V

MAX
VEE

lii
c

FIGURE 3. IIH(S) and IIL(S)

FIGURE 2. ICCH and IEEH

16

16

MAX
Vee

25mV

15

VI-2V

MAX
Vee

3V
O.BV

OS16501
OS3650

MA.X

.. '

OS16501
OS3650,
OS16521
OS3652

3V

,-'

VEe

lOS

Note. Channel A shown under test, other channels are tested
similarly. Only one output shorted at a time.

MAX
VEE

Note. Channel A(-) shown under test, other channels are
tested similarly. Devices are tested with VI from 3V to -3V.

FIGURE 4. lOS

FIGURE 5. IIH

IlL
16

VI-2V

15

VI o-+-4--o~
3V

o-+-I--o...:.r

OS16501
OS3650,
OS16521
OS3652

MAX
Vee

15

2V
MAX
VEE

16

3V

OS16501
OS3650,
OS16521
OS3652

MAX
Vee

MAX
VEE

Note. Channel A(-) shown under test, other channels are tested
similarly. Devices are tested with VI from 3V to -3V.

Note. Output of Channel A shown under test, other outputs
are test~d similarly for VI = O.4V and 2.4V.

FIGURE 6. IlL

FIGURE 7. 10FF

AC Test Circuits and Switching Tiine:,"forms
5V

100mV
16

E'N

200mv~0%
.
ov

OS3650,
OS3652
EO

':~:J:

{'PHLIOI

1.5V

VOL

EO
Note. Output of Channel S shown under test, other channels ere t~

E'N
ov
'PLOlsl
~1.5V

OSI6501
053650

ED

j-;;.,o--lH-o -5V

VOL
tpHO(S)
3V---

, ~o .
Note. Output of Chaonel S shown under test, other channels·sre..tested Similarly.

50%

E'N
OV

'. '''-=;C.
tpOL(S)

tPLO(S)
tPOL(S)
tPHO(S)
tPOH(S)

V1
100mV
100mV
GND
GND

V2
GND
GND
100mV
100 mV

S1
Closed
Closed
Closed
Open

·.a
C1osed'

CL
.15pF

. Open

.50pF
¢I!¥~.dc .j,spF
CI03i!d :5QpF

CL includes jig and probe capacitance.
EIN waveform characteristics: tTLH and tTHL:; 10 ns
10% to 90%

E'N

5V - VO I

'POLISI

ED
VOL
tPOH(S)

measur~d

3V

.

E'N

PRR = 1 MHz

OV

Outy Cycle = 50%

'POHI51
VOH
EO
~

OV

FIGURE 9. Strobe Propagation DeIa'( ~k.fXS·), tPOL(S), tPHO(S) and tPOH(S)

1·35

VOH -0,5V
"'" 1.5V

AC Test Circuits and Switching Time Waveforms

(Continued)

5V

--.l.---.

1DDmvo---....

EIN3V~0%

3110

ov

~++-----<~ ED

"'LH~S)'PHLlS)

-5V

VOH

15pF
T OUTPUT

~-~~-t---oGNO

4k

4k

~~--oSTROBE

1/4 of circuit shown

081652/083652
1·36

~National

a

Transmission Line
Drivers/Receivers

Semiconductor

DS1691A/DS3691 (RS·422/RS·423) Line Drivers
with TRI·STATE®
General Description

Features

The DS1691AIDS3691 are low power Schottky TTL line
drivers designed to meet the requirements of EIA standards RS-422 and RS-423. They feature 4 buffered outputs
with high source and sink current capability with internal
short circuit protection. A mode control input provides a
choice of operation either ali 4 independent line drivers or
2 differential line drivers. A rise time control pin allows the
use of an external capacitor to reduce rise time for sup·
pression of near end crosstalk to other receivers in the
cable.

• Dual RS·422 line driver with mode pin low, or quad
RS-423 line driver with mode pin high
• Individually TRI-STATEable differential drivers in
differential mode
• Short circuit protection for both source and sink outputs
• Outputs will not clamp line with power off or in
TRI-STATE
• Individual rise lime control for each output
• 1000 transmission line drive capability
• Low Icc and lEE po~er consumption
R8-422
'
35 mW/drivertyp
26 mW/drivertyp
RS-423
• Low current PNP inputs compatible with TTL, MaS and
CMOS

With the mode select pin low, the DS1691A1DS3691 are
dual differential line drivers with TRI-STATE outputs. They
feature ± 10V output common-mode range in TRI-STATE
and OVoutput unbalance when operated with ± 5V supply.

Connection Diagram

Connection Diagram

With Mode Select LOW
(R5-422 Connection)

With Mode Select HIGH
(RS·423 Connection)

RISE TIME CONTROL A

VCC

......,,---r- OUTPUT A

INPUT A

INPUT B/OISABLE

I..<""I,~-+'-'- OUTPUT B

INPUT BIOISABLE

MODE SELECT

RISE TIME CONTROL B

GNO

'2 RISE TIME CONTROL C

INPUT C/OISABLE

1<.1'.....-+'...
'

INPUT 0

RISE TIME CONTROL A

VCC

INPUT A

...=..ji---t
'---ll-!=-

MODE SELECT

INPUT C/OISABLE

OUTPUT 0

INPUT 0

...=..ji---t
>-.....;p
'---+:"

RISE TIME CONTROL 0

VEE

TOP VIEW

TOP VIEW

Truth Table
Operation
RS-422

Inputs

A (D)

B(C)

0
0

0
1

0

1
TRI-STATE

1
1

0

0
0

0

1
1

0

0
0
0
RS-423

Outputs

Mode A (D) B(C)
0

1
1
1
1

1
1
1

TRI-STATE
1
TRI-STATE

0
TRI-STATE

0
0

0

1
1

0

1
1

Order Number DS1691AJ, DS3691J or DS3691N
See NS Package J16A or N16A
1-37

RISE TIME CONTROL B
RISE TIME CONTROL C

GNO

OUTPUT C

OUTPUT A

>--.,~ OUTPUT B

OUTPUT C
OUTPUT 0
RISE TIME CONTROL 0

-

Absolute Maximum Ratings (Note 1)
Supply Voltage
Vcc
VEE
Maximum Power Dissipation' at 25·C
Cavity Package
Molded Package
Input Voltage
Output Voltage (Power OFF)

Operating Conditions
Min

7V
-7V

Supply Voltage
DS1691A
Vcc
VEE
DS3691
Vcc
VEE
Temperature (TA)
DS1691A
DS3691

1509mW
1476mW
15V
±15V
-65·Cto +150·C
Storage Temperature
300·C
Lead Temperature (Solderi ng, 10 seconds)

Max

Units

4.5
-4.5

5.5
-5.5

V
V

4.75
-4.75

5.25
-5.25

V
·V

-55
0

+125
+70

·C
·C

• Derate cavity package 10.1 mW/"C above 2S"C; derate molded package
11.9 mW/"C above 2S"C.

DC Electrical Characteristics (Notes 2, 3, 4 and 5)
Parameter

I

Conditions

I

Min

I

Typ

I

Max

I

Units

RS·422 CONNECTION, VEE CONNECTION TO GROUND, MODE SELECT S O.BV
VIH

Hi'gh Level Input Voltage

VIL

Low Level Input Voltage

IIH

High Level Input Current

IlL

Low Level Input Current

VIN=O.4V

VI

Input Clamp Voltage.

IIN= -12mA

Va

Differential Output Voltage
VA,B

2

VT
VT

Differential Output Voltage
VA,B

RL =

V

40

p.A

10

100

,..A

-30

, -200

,..A

1

VIN=2.4V
VINS 15V

Va

V
0.8

VIN=2V

00'

VIN=0.8V

RL = 1000
Vcc'i?4.75V

VIN=2V
VIN=0.8V

-1.5

V

3.6

6.0

V

-3.6

-6.0

2

2.4

-2

-2.4

V
V
V

Vas, Vas

Common·Mode Offset
Voltage

RL=1000

2.5

3

V

IVTI-IVTI

Difference in Differential
Output Voltage

RL = 1000

0.05

0.4

V

IVosl-IVosl

Difference in Common·
Mode Offset Voltage

RL=1000

0.05

0.4

V

Vss

IVT-VTI

RL = 1000, Vcc'i? 4.75V

VCMR

Output Voltage Common·
Mode Range'

VDISABLE = 2.4V

IXA

Output Leakage Current
Power OFF

IXB
lox

TRI·STATE Output Current

ISA

Output Short Circuit Current

ISB

Output Short Circuit Current

Icc

4.0

V
100

VCMR=10V

VCc=OV

VCMR= -10V

Vcc=Max

VIN=2.4V

VIN=O.4V
Supply Current.

1·38

V

4.8

±10

VCMRS10V
. VCMR'i? -10V '

p.A

-100

p.A

100

,..A

-100

,..A

VOA=6V

80

150

mA

VoB=OV

-80

-150

mA

VOA=OV

-80

-150

mA

VOB=6V

80

150

mA

18

30

mA

AC Electrical Characteristics TA = 25°C (Note 5)
Parameter

I

I

Conditions

Min

I Typ I

Max

I

Units

R5-422 CONNECTION, Vcc = 5V, MODE SELECT = O.BV
tr

Output Rise Time

RL = 1000, CL = 500 pF (Figure 1)

120

200

ns

tf

Output Fall Time

RL = 1000, CL = 500 pF (Figure 1)

120

200

ns

tpOH

Output Propagation Delay

RL =: 1000, CL = 500 pF (Figure 1)

120

200

ns

tpOL

Output Propagation Delay

RL = 1000, CL = 500 pF (Figure 1)

120

200

ns

tPZL

TRI·STATE Delay

RL = 4500, CL = 500 pF, Cc = 0 pF (Figure 4)

250

350

ns

tpZH

TRI·STATE Delay

RL = 4500, CL = 500 pF, Cc = 0 pF (Figure 4)

180

300

ns

tpLZ

TRI·STATE Delay

RL == 4500, CL = 500 pF, Cc = 0 pF (Figure 4)

180

300

ns

tpHZ

TRI·STATE Delay

RL = 4500, CL = 500 pF, Cc = 0 pF (Figure 4)

250

350

ns

Max

Units

DC Electrical Characteristics (Notes 2, 3, 4 and 5)
Parameter

Conditions

Min

Typ

RS·423 CONNECTION, IVccl = IVEEI, MODESELECT~2V
VIH

High Level Input Voltage

VIL

Low Level Input Voltage

IIH

. High Level Input Current

IlL

Low Level Input Current

1

VIN=2.4V
VINS 15V

10

VIN=O.4V

-30 .

VI

Input Clamp Voltage

IIN= -12 mA

Va

Output Voltage

RL = 00, (Note 61
Vcc?:.4.75V

VIN=2V

Vr
VT

Output Voltage

RL-=4500,
Vcc?:.4.75V

VIN =0.4V

IVTI-IVTI

Output Unbalance

IVccl = IVEEI =4.75V, RL=4500

Vo

V

2
0.9

V

40

p.A

100

p.A

-200

p.A

-1.5

V

4.0

4.4

6.0

V

VIN=0.4V

-4.0

-4.4

-6.0

V

VIN=2.4V

3.6

4.1

-3.6

-4.1
0.02

V
V
0.4

V

p.A

Ix+

Output Leakage Power OFF

VCC=VEE=OV

Vo=6V

2

100

Ix -

Output Leakage Power OFF

VCC=VEE=OV

Vo= -6V

-2

-100

p.A

Is+

Output Short Circuit Current

Vo=OV

VIN=2.4V

-80

-150

mA

Is

Output Short Circuit Current

Vo=OV.

VIN=O.4V

80

150

mA

ISLEW

Slew Control Current

Icc

Positive Supply Current

VIN=0.4V, RL=

00

18

30

mA

lEE

Negative Supply Current

VIN = O.4V, RL =

00

-10

-22

mA

±140

p.A

Not.t: "Absolute Maximum Ralings" are Ihose values beyond which the safely of Ihe device cannot be guaranleed. They are nol meanl to imply that the
devices should be operated at these IImlls. The tables of "Eleclrlcal Characterlslics" provide conditions for aclual device operation.
Not. 2: Unless otherwise specified, minimax limits apply across Ihe - 55·C 10 + t25·C temperature range for the OSt691A and across the O·C 10 + 70·C
range for the 053691. All typlcals are given for VCC =5V and TA = 25·C. VCC and VEE as listed In operating conditions.
Not.3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.
Not.4: Only one oulput at a time should be shorted.
Nota 5: Symbols and definitions correspond to EIA RS-422 and/or R5-423 where applicable.
Nota 6: At - 55·C, the output voltage Is + 3.9V minimum and - 3.9V minimum.

1-39

AC Electrical Characteristics TA = 25°C (Note 5)
Conditions

Parameter

RS·423 CONNECTION, Vee = 5V, VEE - 5V, MODE SELECT

Min

Typ

Max

Units

=2.4V

tr

Rise Time

RL = 4500, C L = 500 pF, Cc

=0 (Figure 2)

120

300

ns

tf

Fall Time

RL = 4500, CL = 500 pF, Cc = 0 (Figur,e 2)

120

300

ns

tr

Rise Time

RL

Fall Time

RL

tre

Rise Time Coefficient

=4500, C L = 500 pF, Cc = 50 pF (Figure 3)
=4500, CL = 500 pF, Cc = 50 pF (Figure 3)
RL =4500, C L = 500 pF, Cc = 50 pF (Figure 3)
RL =4500, CL = 500 pF, Cc = 0 (Figure 2)
RL =4500, CL'" 500 pF, Cc =0 (Figure 2)

3.0

tf

tpDH

Output Propagation Delay

tpDL

Output Propagation Delay

3.0

'"

0.06

p.s/pF

p's

180

300

ns

180

300

ns

AC Test Circuits and Switching Time Waveforms
I

V~
2
INP~

A

.,
I~

.'+

OUTPUT

3V

I

INPUT

-

'

=

5

.f"

OUT

16

~~
15

INPUT
OV

e -L .,
l

J

I

t,:S;lDns

J

'l

r--- 20 "

'1DUTPUT

-=

I

\

tr~tOns

20~s

______

.

vL

OUTPUT

....!

D.lVss/

VEE

-1

FIGURE 3. Rise Time Control for RS-423

1-40

t,

-

1
-

~
If

AC Test Circuits and Switching Time Waveforms

(Continued)

INPUTB

OUTPUT

OUT

FIGURE 4. TRI-STATE® Delays

Switching Waveforms

INPUT

Vee·5V vEE" -5V
MODE" 1 UNBA~~~~~

Vee·5V VEE" GND

Blel
MODE. 0

BA~~~~~~
AID)

_.,

.~~"",'V

Vee· 5V, VEE· -5V

-J* :

______

Typical Rise Time Control Characteristics
Rise Time vs External Capacitor

CAPACITANCE (pFI

1-41

- - tpZL

ien ~National
Semiconductor

-m
c

Transmission Line
Driversl Receivers

~

0816921083692 TRI-8TATE® Differential Line Drivers

lii
c

General Description

Features

The OS1692/0S3692 are low power Schottky TTL line
drivers electrically similar io the OS1691AIDS3691 but
tested to meetthe requirements of MIL-STO-188-114. They
feature 4 buffered outputs with high source and sink current capability with internal short circuit protection, A
mode control input provides a choice of operation either
as 4 independent line drivers or2 differential line drivers, A
rise time control pin allows the use of an external capacitor to reduce rise time for suppression of near end crosstalk to other receivers in the cable.

• Oual differential line driver or quad single-ended line
driver
• Individually TRI-STATEable differential drivers meet
MIL-STD-188-114
• Short circuit protection for both soqrceand sinkoutputs
• Individual rise time control for each output
• 1000 transmission line drive capability
• Low Icc and lEE power consumption
Differential mode
35 mWldrivertyp
26 mWldrivertyp
Single-ended mode
• Low current PNP inputs compatible with TTL, MOS and
CMOS

With the mode select pin low, the OS1692/0S3692 are dual
differential line drivers with TRI-STATE outputs, They
feature ± 10V output common-mode range in TRI-STATE
and OVoutput unbalance when operated with ± 5V supply.

Logic Diagram (1/2 Circuit Shown)
,.---OCEXT, AID)
INPUT A 1 0 ) Q - - - - - - - f . ) > O _ - - - 4 , . . . . . . - - - - - - - - I

X>--QOUTPUT AID)

INPUT B IC)
TRI·STATE"Q-....-------+---r~
DISABLE

X)---OOUTPUT B IC)

SE~~~~o------C:>O-....- - L J

Connection Diagram

Truth Table
Outputs

Inputs

16 RISETIME CONTRa L A

VCC
INPUT A

15 OUTPUT A

Mode

A (D)

B(C)

A (D)

B(C)

INPUT B/OISABLE

14 OUTPUT B

0
0
0
0
1
1
1
1

0

0
1
0
1
0
1
0
1

0
TRI-STATE
1
TRI-STATE
0
0
1
1

1
TRI-STATE
0
TRI-STATE
0
1
0
1

13 RISE TIME CONTROL B

MODE SELECT

12

GNO

RISE TIME CONTROL C

INPUT C/OISABLE

11 OUTPUT C

INPUT 0

10 OUTPUT 0
RISE TIME COilTROL 0

TOP VIEW

Order Number DS1692J, DS3692J or DS3692N
See NS Package J16A or N16A

1-42

0
1
1
0
0
1
1

Absolute Maximum Ratings (Note 1)

Operating Conditions

5upply Voltage
7V
Vee
-7V
VEE
Maxirpum Power Dissipation * at 25·C
Cavity Package
1509mW
Molded Package
1476mW
Input Voltage
15V
Output Voltage (Power OFF)
:I: 15V
Storage Temperature
-65·Cto + 150·C
Lead Temperature(50Idering, 10 seconds)
300·C

Min
Supply Voltage
051692
Vee
VEE,
DS3692
Vcc
VEE
Temperature (TA)
051692
053692

'Derate cavity package 10.1 mWf'C above 25'C; derate molded package
11.9 mWf'C above 25·C.

Max

Units

4.5
-4.5

5.5
-5.5

V'
V

4.75
-4.75

5.25
-5.25

V
V

-55
0

+125
+70

·C
·C

Electrical Characteristics DS16921D53692 (Notes 2, 3 and 4)
Parameter

Conditions

Min

Typ

Max

Units

051692, Vcc = 5V:I: 10%,053692, Vcc = 5V:I: 5%, VEE CONNECTION TO GROUND, MODE 5ELECT sO.8V·
Va

Differential Output Voltage
VA.S

RL =

VT
VT

Differential Output Voltage
VA.S

RL = 1001}
Vcc?:.4.75V

Vas, Vas

Common·Mode Offset
Voltage

RL=100{l

2.5

3

V

IVTI-IVTI

Difference in Differential
Output Voltage

RL= 1001}

0.05

0.4

V

IVosl-IVosl

Difference in Common·
Mode Offset Voltage

RL = 1001}

0.05

0.4

V

Va

VIN =2V

2.5

3.6

V

-2.5

-3.6

V

2

2.6

V

-2

-2.6

00

VIN=0.8V
VIN =2V
VIN =0.8V

Vss

IVT- VTI

RL ";100{l, Vec?:.4.75V

lox

TRI·STATE Output Current

Vas -10V

ISA

Output Short Circuit Current

4.0

Iss

Output Short Circuit Current

Icc

Supply Current

VIN =O.4V

4.8

V

-0.002

-0.15

mA

0.002

0.15

mA

VoA =6V

80

1.50

mA

Vos=OV

-80

-150

mA

VOA=OV

-80

-150

mA

Vos=6V

80

150

mA

18

30

mA

Vo?:.15V
VIN=2.4V

V

051692, Vcc =5V:l:10%, VEE= -5V:l:l0%, 053692, Vcc= 5V:l:5%, VEE = -5:1:5%, MODE 5ELECTsO.8V

'!.9
Va

Differential Output Voltage
VA.S

VT
VT

Differential Output Voltage
.V A.S

IVTI-IVTI

Output Unbalance

lox

TRI·STATE Output Current

Is+
Is-

Output Short Circuit Current

RL=

00

RL=200{l

VIN =2.4V

7

8.5

V

VIN =0.4V

-7

-8.5

V

VIN =2.4V

6

7.3

V

VIN =O.4V

-6

-7.3
0.4

V

0.002

0.15

mA

Vo= -10V

-0.002

-0.15

mA

VIN=2.4V

-80

-150

mA

VIN =O.4V

80

150

mA

Vo= 10V

Vo=OV

V

0.02

IVeel = I VEE\' RL=200{l

p.A

ISLEW

Slew Control Current

Icc

Positive Supply Current

VIN =O.4V, RL =

00

:I: 140
18

30

mA

lEE

Negative Supply Current

VIN =O.4V, RL =

00

-10

-22

mA

1·43

Electrical Characteristics (Notes 2 and 3) VEESOV
Parameter
VIH

High level Input Voltage

VIL

low level Input Voltage

IIH

High level Input Current

Conditions

Min

Typ

Max

Units
V

2
0.8

V

1

40

p.A

VINS 15V

10

100

p.A

-30

-200

p.A

..

VIN=2.4V

IlL

low level Input Current

VIN=O.4V

VI

Input Clamp Voltage

IIN=-12mA

IXA
IXB

Output leakage Current
Power OFF

VCC=VEE=O

-1.5

I
I

Vo= -15V

V

0.01

0.15

mA

-0.01

-0.15

. mA

Vo=15V

Switching Characteristics TA = 25°C

I

Parameter

Conditions

I

Min

I

Typ

I

Max

I

Units

Vee·= 5V, MODE SELECT = O.BV
tr

Differential Output Alse Time

AL. = 1000, C L = 500 pF (Figure 1)

120

200

ns

tf

Differential Output Fall Time

AL= 1000, C L =500 pF (Figure 1)

120

200

ns

tpOH

Output Propagation Delay

AL = 1000, C L = 500 pF (Figure 1)

120

200

ns

tpOL

Output Propagation Delay

AL = 1000, CL = 500 pF (Figure '1)

120

200

ns

tPZL

TRI-STATE Delay

AL = 1000, CL = 500 pF (Figure 2)

180

250

ns

tPZH

TAl-STATE Delay

AL = 1000, C L = 500 pF (Figure 2)

180

250

ns

tpLZ

TAl-STATE Delay

AL = 1000, CL

80

150

ns·

tpHZ

TAI-STATE Qelay .

=500 pF (Figure 2)
AL =1000, C L =500 pF (Figure 2)

80

150

ns

190

300

ns

190

300

ns

190

300

ns

190

300

ns

Vee = 5V, VEE = - 5V, MODE·SELECT = O.BV
tr

Differential Output Aise Time

tf

Differential Output Fall Time

tpoL

Output Propagation Delay

tpOH

Output Propagation Delay

tPZL

TAl-STATE Delay

tPZH

TRI-STATE Delay

tpLZ

TAl-STATE Delay

tpHZ

TAl-STATE Delay

=500 pF (Figure 1)
AL =2000, CL =500 pF (Figure 1)
AL =2000, C L =500 pF (Figure 1)
AL =2000, C L =500 pF (Figure 1)
AL =2000, CL =500 pF (Figure 2)
AL =2000, CL =500 pF (Figure 2)
AL = 2000, CL =500 pF (Figure 2)
AL =2000, C L =500 pF (Figure 2)
AL = 2000, CL

180

250

ns

180

250

ns

80

150

ns

80

150

ns

Nole 1: "Absolute Maximum Ratings" are Ihose values beyond which Ihe safely of the device cannot be guaranteed. They are not meant to imply that the
devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for actual device operation.
NOle2: Unless otherwise specified, minImax limits apply across the - 55'Cto + 125'C temperature range forthe 051692 and across theO'C to + 70'C range
for the 053692. All typlcals are given forVcc =5V and TA =25'C. VCC and VEE as listed in operating conditions.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unlessotherwis8 specified.

Nole 4: Only one output at a lime should be Shorted.

,
-~-

1-44

AC Test Circuits and Switching Time Waveforms

Vee
2
INPUT

*UK eT2 CURRENT
TRANSF. OR
EOUIVALENT

-=

OUT

FIGURE 1. Differential Connection

INPUT 8

'TEK CT2 CURRENT
TRANSF. OR
EOUIVALENT

-=

OUTPUT
OUT

FIGURE 2. TRI·STATE Delays for DS1692IDS3692

1·45

Switching Waveforms

INPUT

VCC = 5V VEE = GND
B ( C ) - - - i . r---~-~---"""'\r_---+
MDDE' 0

B~~~~~~~
A(D)--~

B(C)~

MDDE' 0

'--=.-,O:::'V-------J ' - - - - +
VCC = 5V, VEE = -5V

BA~~~:~:~.OV-----------'~~
.

Typical Rise Time Control Characteristics

1k

~
"'~
"'
~

100

10

1
10

100

lk

CAPACITANCE (pF)

1·46

10k

:

c

~National

Transmission Line
Drivers/Receivers

~ Semiconductor

PRELIMINARY

Features
• Meets new EIA standard RS485 (PN1488), for multipoint
bus transmission.
• 15 ns driver propagation delays with 2 ns skew (typical).
• Single channel per package isolates faulty channels
(from shutting down good channels).
• Single + 5V supply.
• -7V to +12V bus common mode range permits ±7V
ground difference between devices on the bus.
• Thermal shutdown protection.
• Power-up down glitch-free driver outputs permit live insertion or removal of transceivers.
• High impedance to bus with driver in TRI-STATE or
with power off, over the entire common mode range' allows the unused devices on the bus to be powered
down.
• Line fault reporting capability on OS3696 and OS3698
allows automated fault location and re-routing under
processor control.
• 12 kO Minimum receiver input impedance.
• 70 mV typical receiver hysteresis.

(X)

Connection and Logic Diagrams

Vee

RO

iii
DE

110/11

D1

SlID

Vee

RO

h

}.UI

liMn
if

110/11

DI

GIlD

(TOPVlEWI

}.UI

(TOPVlEWI
TLIF15272-1

TLIF15272-2

TLIF15272-3

TLIF15272-4

Order Number OS3695N, DS3696N,
DS3697N or DS3698N
See NS Package N08E
1-47

.....

CO

General Description

Is a registered trademark of National Semiconductor Corp.

-e
CO

The 053695, 053696, 053697 and 053698 are high speed
differential TRI-STATE buslline transceivers/repeaters designed to meet the requirements of EIA standard RS485
with extended common mode range (+ 12V to - 7V), for
multipoint data transmission_

TAI~STATE.

Ien

CO

OS3695/0S3696/0S3697/0S3698 Differential
TRI-STATE ® Bus/Line Transceivers/Repeaters

The driver and receiver outputs feature TRI-STATE capability, for the driver outputs over the entire common mode
range of + 12V to -7V_ Bus contention or fault situations
that cause excessive power dissipation within the device
are handled by a thermal shutdown circuit, which forces the
driver outputs into the high impedance state. The 053696
and 053698 provide an output pin which reports the occurrence of a line fault causing thermal shutdown of the device.
This is an "open collector" pin with an internal 10 kO pull-up
resistor. This allows the line fault outputs of several devices
to be wire OR-ed.
Both AC and OC specifications are guaranteed over the 0 to
70"C temperature and 4.75V to 5.25V supply voltage range.

en

co

-CD
0)

.....
0)

-!
0)
I I)

en
c

Absolute Maximum Ratings

(Note 1)
Supply voltage, vec
7V
Control input voltages .
7V
Driver input voltage
7V
Driver output voltages
+15V/-10V
Receiver input voltages (D$3695, DS3696)
+15V/-10V
Receiver common mode voltage (DS3697, DS3698) ±25V
Receiver output voltage
5.5V
Continuous power dissipation @70'C
780mW
Storage temperature range
-65'Cto + 150'C
Lead temperature (Soldering 10 seconds) .
300'C

Recommended Operating Conditions
Supply voltage, Vcc
Bus voltage
Operating free air temperature T A

Electrical Characteristics (Nc;>tes 2 and 3) Symbol

(O'C";TA";70'C,

Parameter

VODI

Differential Driver Output
Voltage (Unloaded)

VOD2

' Differential Driver Output
Voltage (with Load)

Min

Max

Units

4.75
-7
0

5.25
+12
70

V
V
'C

4.75V-~

-*

DS3895
TL/F/5272-13

1-51

~National

a

Transmission Line
Drivers/Receivers

Semiconductor

D8551131D875113 Dual TRI·8TATE®
Differential Line Driver
General Description

Features

The DS55113/DS75113 dual differential line drivers
with TR I-STATE outputs are designed to provide all the
features of the DS55114/DS75114 line drivers with the
added feature of driver output controls. There are
individual controls for each output pair, as well as a
common control for both output pairs. When an output
control is low, the associated output is in a highimpedance state and the output can neither drive nor
load the bus. This permits many devices to be connected
together on the sa01e transmission line for party-line
applications.

•
•
•
•
•
•
•
•
•
•
•
•

The output stages are similar to TTL totem-pole outputs,
but with the sink outputs, YS and ZS, and the corresponding active pull-up terminals, YP and ZP, available
'on adjacent package pins.

Connection Diagram

Each circuit offers choice of open-collector or active
pull-up (totem-pole) outputs
Single 5V supply
Differential line operation
Dual channels
TTL/LS compatibility
High-impedance output state for party-line applications
Short-circuit protection
High current outputs
Single-ended or differential AND/NAND outputs
Common and individual output controls
Clamp diodes at inputs
Easily adaptable to DS55114/DS75114 applications

Dual-In-Line Package

2C

CC

Positive logic: Y = AS
Z=AS
Output is OFF when
C orCC is low

lZP

lZS

lVS

lA

lVP

lC

18

GND

TOP VIEW

Truth Table

Ordar Number DS55113J, DS75113J, or DS75113N
SlIa NS Package J16A or N16A
.

INPUTS
OUTPUT CONTROL

OUTPUTS
AND NAND

DATA

C

CC

A

B*

V

Z

L

X
L

X

Z

Z

Z

H

H
H

L
L

H

H

L
X

X
X
X
L

Z

X

H

H

H

H

H

L

X

1-52

H

H = high level
L = low laval
X = irrelevant
Z = high impedance (OFF)
*S input and 4th line of truth
table applicable only to
driver number 1

Absolute Maximum Ratings
Supply Voltage (VCC) (Note 1)
Input Voltage
DFF-State Voltage Applied to
Dpen-Collector Outputs
Maximum Power Dissipation* at 25°C

Supply Voltage (VCC)
DS55113
DS75113

7V
5.5V
12V
1433 mW
1362mW

Cavity Package

Molded Package
Operating Free-Air Temperature Range
DS55113
DS75113
Storage Temperature Range
Lead Temperature (1/16" from case for
SO seconds): J Package
Lead Temperature (1/IS" from case for
10 seconds): N Package

cCJ)

Operating Conditions

(Note 1)

MIN

MAX

UNITS

~
.....

4.5
4.75

5.5
5.25

V
V

C

High Level Output Current (lOH)

--40

mA

Low Level Output Current (lOL)

40

mA

125
70

'e
°e

Operating Free-Air Temperature (TA)
DS55113
DS75113

-55°C to +125°e
oOe to +70o e
--B5°e to +150o e

c.n

-55
0

300°C
2S0°C

'Derate cavity pac~age 9.S mvg/e above 25°C; derate molded
package 10_9 mW/ e above 25 e (Note 2).

Electrical Characteristics

Over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS (Note 3)

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VIK

Input Clamp Voltage

VOH

High Level Output Voltage

10H = -10 rnA

2,4

3,4

2,4

3,4

10H = -40 rnA

2

3.0

2

3.0

VCC = Max, 10 = -40 rnA
VOH = 12V
VCC = Max
VOH = 5.25V

0.23
-1.1

TA=25°e

1

TA=125°C

OFF-State IHigh-lmpedance-

Vec = Max.
Output Controls

State) Output Current

at 0.8V

IIH

IlL

ICC

V

-1.5

V
V

0,4

V

-1.5

V

10
1

10

Voltage

CC

High Level

A:B.C
CC

Low Level

A,B.C

Input Current

CC

Current INote 5)
Supply Current 180th
Drivers)

~A

20

TA = 70°C
±10

±10

Vo = 0
Vo = O,4V

-150

-20

±BO

120

Va - 2.4V

±80

±20

Vo = Vec

80

20

1

1

2

2

40

40

80

80

-1.6

-1.6

3.2

3.2

Vec =Max. VI = 5.5V

Short-Circuit Output

lOS

0.23

-1.1

TA=25°C

A.B.C

Maximum Input

Input Current

TA = Max

0.4
-1.5

0.8

200

TA = 25°C. Vo = 0 to VCC

II

-0.9

VIL = 0.8V

VCC = Min. VIH = 2V. VI L = O.BV. 10L = 40 rnA

Input Current at

-1.5

UNITS
V

VCC = Min. VIH = 2V.

Low Level Output Voltage

10Z

0575113
TYP
MAX
(Note 4)

2

-0.9

Vec = Min. II = -12 mA

Output Clamp Voltage

Output Current

MIN

O.~

VOK

IOloff)

0555113
TYP
MAX
(Note 4)

2

VOL

OF F-State Open·Coliecto,

MIN

~A

rnA

VCC = Ma~. VI = 2,4V

VCC = Max. VI = O.4V

-40

Vcc=Max. VO=O

-90

-120

-40

-90

-120

All Inputs at OV. No Load.

VCC= Max

47

65

47

65

TA = 25°C

VCC = 7V

65

85

65

85

~A

rnA

rnA

rnA

Note 1: All voltage values are with respect to network ground terminal.
Note 2: For operation above 25° C free-air temperature, refer to Dissipation Derating Curves in the Thermal information section.
Note 3: All parameters with the exception of OFF-state open-collector output current are measured with the active pull-up connected to the sink
output.
Note 4: All typical values are at TA = 25°C and Vee = 5V, with the exception of ICC at 7V.
Note 5: Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

1-53

~

CJ)

~
.....
CU

Switching Characteristics

Vee = 5V, eL = 30 pF, TA = 25°e

PARAMETER

CONOITIONS

MIN

OS55113
TYP

MAX

13

12

Propagation Delay Time, Low-to-

tPLH

High-Level Output

OS75113
TYP

MAX

20

13

30

ns

20

12

30

ns

MIN

UNIT

(Figure 1)
Propagation Delay Time, High-to-

tPHL

Low-Level Output

tPZH

Output Enable Time to High Level

R L = 180n, (Figure 2)

7

15

7

20

ns

tPZL

Output Enable Time to Low Level

R L = 250n, (Figure 3)

14

30

14

40

ns

= 180n, (Figure 2)

10

20

10

30

ns

RL = 250n, (Figure 3)

17

35

17

35

ns

tpHZ

tPL~

Output Disable Time from High

RL

Level
Output Disable Time from Low

Level

Schematic Diagram

(One side shown only)

,

INPUT 18

r-<> INPUT lA

0-

06)

1611'1
Ok

Ik

l

~

;r

SOD

Ik

} TO OTHER
DRIVER

-+J

~

,..--

600

.....

Ok

1(1

~T wI

....-

':"

ANO (4)
PULL·UP

,.

~

~
9

vee
600*

,V,

'J
,.

'00

9D

~,

'"
AND SINK (3)
OUTPUT
1YS

~

..

"

~

~

~~

'"

~,.

4k

~
~

':"

PULL·UP

~,

.

Ir

~,.

'Z'

.

~
5k

h

':"

4k

Uk

;t-

r-t:
100

IDO

':"

~

OUTPUT 111
CONTROL
1C

~
~~ ~~

r+r-

lZS

~~

* These components common to both drivers.

~.

181

Resistor values shown are typical and in ohms.

,N.

':"

1-54

'"
(2) NAND SINK
OUTPUT

Vee

COMMON O'UTPUT (9)
CONTROL CC
(COMMON TO BOTH SIDESI

111 NAND

'DO

9D

':"

'DO

9

AC Test Circuits and Switching Time Waveforms
r-----~---.

I.'

5V
JV
INPUT

VOH
NAND
OUTPUT

VOL

~~----t-l-~L-----~:~+-+---~-------~~~UT
AND

VOH

OUTPUT

VOL

FIGURE 1. tpLH and tpHL
INPUT

JV

-+""..--_.t.

INPUT
OUTPUT

I
I
I
I
I
I

1k
SV -J\lV\,--o-..........

IL _________________

VOH------h~~_+~,

180
OUTPUT

VOFF "" BV

~

FIGURE 2. tpZH and tpHZ
INPUT
5V
INPUT

250

OUTPUT
SV

"

I

,

5V---"

I

1 1LI ________
'::"

OUTPUT
VOL _ _ _ _ _,'--_ _...;r.

I
~

________

I
I

~

FIGURE 3. tpZL and tpLZ
Note 1: The pulse generator has the following characteristics: ZOUT
Note 2: CL includes probe and jig capacitance.

=50n, PRR =500 kHz, tw = 100 ns.

Typical Performance Characteristics *
Output Voltage vs Data
Input Voltage

l/v~c=Jv
/ V~c = J.SV

NO LOAO
TA=ZS"C

I
Vcc = 4.SV

Output Voltage vs Data
Input Voltage

L

'"~
'"!;;>
:=:>
'"
>'"

V,- OATA INPUT VOLTAGE (V)

I

Tl = lJSOC

l-

I

VCC = S.SV

i=
II

Ji

D

o

LOAD = SDO!lTO GROUNO
TA=ZS"C
I VCC·SV

TA = -SS"C r-

I

o

J--

6

IT~=Z~OC

NO LOAD
Vcc = sv

2w

Output Voltage vs Output
Control Voltage

VCC=4.SV

l-

I
o
V,- DATA INPUT VOLTAGE (V)

OISABLEO

o

J

HIGH

I

o

V,-,NPUT VOLTAGE (OUTPUT CONTROL) (V)

*Oata for temperatures below O°C and above 70°C and for supply vol.tages below 4.75V and above 5.25V are applicable to 0555113
circuits only. These parameters were measured with the active pull-up connected to the sink output.

1-55

,....
~
.....
CJ)

('I)

Typical Performance Characte~istics·
Output Voltage vs Output
Control Voltage

c

CW5
,....

rg

CJ)

C

6
LOAO = 500n TO GROUN:
VCC=5V
..

~

+-

~,TA=,25

C,
_ TA=125 C_

~

'"

..
..:='"..
~

r-

>

!;

,l,

OISABLED

Output Voltage vs Output
Control Voltage

-

t-

I-

o

V,-INPUT VOLTAGE {OUTPUT eONTROLI {VI

"'"

,.~

...
'"
!;

...
,.
~

I

I

II1I

o

+-rT

v~=:!40mhl

1'6

o
25

-15 -50 -25

50

15 100 125

o

-20

TA - FREE·AIR TEMPERATURE ('CI

-40

'""

0.4

I---+-+-

~

0.3

f--I---t-:..I~-+-+--I

~
c

0.2

~

I

•

.-

0.5 f--t--+-+-t--t~~

~

_VCC=4.51i"""'- ....

"f.

o

~

c=i5V- I--

I

VOL (lOL - 40 mAl

0.4

r-~-..,..-..,...-r--,,--,

TA = 25 C

t--..

..~'"
,...'"

I I I I
I I I I

1.2
0.8

-- -

~
"""" ...... J -~
,.....
-.

'"~

V,-,NPUT VOLTAGE (OUTPUT CONTROLI (VI

0.6

I
I

::z:'CC = 5V

~

I

o

Low Level Output
Voltage vs Output

I
~

LOW

Current

VCC - 4.5V

l- I-l- l- I--

TA=-55 C
DISABLED

V,- INPUT VOLTAGE (OUTPUT CONTROLI (VI

VOH(lOH=-10mA~

TA=25 C

>

o

Current

1 1 1 1
1 1 I. I.

TA!125 ' C

I

LOAD = 500n TO VCC
TA=25C

Temperature

2.4

..
..~.
!;

High Level Output
Voltage vs Output

2.8

'"~

ilow

Output Voltage vs Free·Air

3.6

vrr

~

- :-

>

o

3.2

LOAD = 5DO~1 TO Vee

~

TA=-55 C

HIGH
DISjBLr

~

Output Voltage vs Output
Control Voltage

5~5V

T

I-::

>

~

Vclc =

VCC = 5V
I I
VCC =4.5V

I

o

(Continued)

~

,J:

0.1 H~f--+--+--+-+--I

I

-60

-80

20

-100 -120

10H - OUTPUT CURRENT (mAl

40

60

80

100

120

10L - OUTPUT CURRENT {mAl

Supply Current (Both
Supply Current (Both
Drivers) vs Supply Voltage
80

"...
oS

~

1''"l
~

~
I

""

10

56

NO LOAD
TA=25'C

"...

1

60

INPUTS GROUNDE~P"

50

A'

40

,J

o

52

~
~

50

I

I

10

'54

oS

i

INPUTS OPEN

3D
20

Supply Current (Both

Driv.ers) vs Free-Air
Temperature

""

...... 10'

VCC - 5V
INPUTS GRDUNOEO
NO LOAD

...... ......

48
46
44

Vce=5V
RL " '
CL = 30 pF.
INPUTS: 3V SDUARE WAVE
TA = 25 C

V

.........

......

42
40
38
36
-15 -50 -25

o

Drivers) vs Frequency
100

Vce - SUPPLY VOLTAGE IVI

o
0

25

50

15 100 125

ffl

"""
j::.5.

,,'"
>-~

g~
.......
"
.....
-"

16

I
I

VCC = 5V
CL = 30 pF
(FIGURE 11
tpLH

14
12

tpHL

10

~

-r:::: -

30

i.---

-

20

-

~~

It~

~
tpZH

g:

o

II

o
50

40 100

f.--" -'~

t5

:;"

25

10

II

VCC = 5V
(FIGURES 2 AND 31

25

10

-15 -50 -25

1

Output Enable and Disable
Times vs Free-Air Temperature

. Temperature
18

0.4

f - FREQUENCY (MHz)

Propagation Delay Times
from Data Inputs vs Free-Air
20

0.1

TA - FREE·AIR TEMPERATURE (" CI

15 100 125

-15 -50 -25

TA - FREE·AIR TEMPERATURE ('CI

25

50

75 tOO 125

TA - FREE·AIR TEMPERATURE ( CI

*Data for temperatures below O°C and above 70°C and for supply voltages below 4.75V and above 5.25V are applicable to DS55113
circuits only.

Th~se

parameters were measured with the active pull-up connected to the sink output.

1·56

~National

Transmission Line
Drivers/Receivers

~ Semiconductor

D8551141D875114 Dual Differential Line Drivers
General Description

Features

The DS55114/DS75114 dual differential line drivers are
designed to provide differential output signals with high
current capability for driving balanced lines, such as
twisted pair at normal line impedances, without high
power dissipation. The output stages are similar to TTL
totem·pole outputs, but with the sink outputs, YS and
ZS, and the corresponding active pull·up terminals, YP
and ZP, available on adjacent package pins. Since the
output stages provide TTL compatible output levels,
these devices may also be used as TTL expanders or
phase spl iUers.

•

Each circuit offers choice of open'collector or active
pull·up (totem-pole) outputs

•
•

Single 5V supply
Differential line operation

•
•
•

Dual channels
TTL/LS compatibility
Design to be interchangeable with Fairchild 9614
line drivers

•

Short-circuit protection of outputs

•
•

High current outputs
Clamp diodes at inputs and outputs to terminate
line transients

Connection Diagram

•

Single-ended or differential AND/NAND outputs

•

Triple inputs

Truth Table

Dual-In-Line Package
Vee

ZZP

16

15

ZZS

ZYS

2YP

2C

"

2A

14

A

INPUTS
B

C

H

H

H

All Other Input Combinations

OUTPUTS
Y
Z
H

L

L

H

H = high level
L = low level
lZP

lZS

lVS

lYP

1A

1C

IB

GND

TOP VIEW

Positive logic:

Y = ABC
Z = ABC

Orde, Number DS55114J, DS75114J, or DS75114N
See NS Package J16A or N16A

Schematic Diagram

(Each Driver)
INPUTS

~
(1,
11)

(6,
10)

TO OTHER

DRIVER

(5,9)
(16)

Vee

4k
(1,15)

AND

PUlL·UP
yp

-=-

NAND
PUll·UP

90

zp

5k

5k

(3,13)
AND
SINK OUTPUT
ys

(2,14)

NAND

,ua

,ua

SINK OUTPUT
2S

181

L--4------~----~~--------~~4---------~----~--~------~----~--4_------__oGNO

Resistor values shown are typical and in ohms.

1-57

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Supply Voltage (VCC)
7V
Input Voltage
5.5V
OFF·State Voltage Applied to Open-Collector Outputs
12V
Ma'ximum Power Dissipation" at 2!fC
Cavity Package
1433mW
Molded Package
1362mW
Operating Free-Air Temperature Range
DS55114
•
-55·C to +12!fC
O'C to +70·C
DS75114
-65·C to +150·C
Storage Temperature Range
Lead Temperature (1116" from case
300·C
for 60 seconds): J Package
Lead Temperature (1116" from case
260·C
for 10 seconds): N Packege

Supply Voltage (V CC)
DS55114
DS75114

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

High Level Output Current (lOH)

-40

mA

Low Level Output Current (IOL)

40

mA

125
70

'c
'c

Operating Free-Air Temperature (TA)
DS55114
DS75114 .

-55
0

"Derate cavity package 9.6 mWI" C above 25· C; derate molded
package 10.9 mWI"C above 2!fC (Note 2).

Electrical Characteristics

Over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

CONDITIONS (Note 3)

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

VIK

Input Clamp Voltage
High Level Output Voltage

VOL

Low Level Output Voltage

"OK

Output Clamp Voltage

II

2

DS75114
TYP
MAX
(Note 4

UNITS

2

OFF·State Open·Coliector
Output Current

VCC = Min, II = -12 rnA

I

VIL = 0.8V

Input Current at Maximum

Vee = Max

Vce = Max', VI = 2.4V
VCC = Max, VI = O.4V

Supply Current (Both
Drivers)

3.4

IOH=-40mA

2

3.0

2

3.0

0.2

0.4

0.2

6.1
-1.1

6.5
-1.5

6.1
-1.1

1

TA= 125·C

V·
V

0.45

V

6.5
-1.5

V

100
200

TA=25·e

1

100

TA = 70·e

/lA

200

Vce = Max, VI = 5.5V

Low Level Input Current

Current (Note 5)

2.4

TA=25·C

-1.5

-0.9

3.4

IIcc = 5V, 10.= 40 rnA, T A = 25·C
VCC = Max, 10 = -40 rnA, TA = 25·C
VOH = 12V

-1.5

2.4

IOL=40mA

High Level Input Current

Short·Circuit Output

0.8

IOH=-10mA

VCC = Min·, VIH = 2V, VIL = O.BV,

VOH = 5.25V

lriput Voltage

-0.9

VCC = Min, VIH = 2V,

IIH

ICC

MIN

0.8

IlL
lOS

DS55114
TYP
MAX
(Note 4)

V

VOH

10(ofl)

MIN

1

1

40

-40

VCe=Max,VO=O

-1.1

-1.6

-90

-120

-40

rnA·

40

/lA

-1.1

-1.6

rnA

-90

-120

_ rnA

Inputs Grounded, No Load,

Vce = Max

37

50

37

50

TA = 2S·C

Vee = 7V

47

65

47

70

rnA

Note 1: All vol'tage values are with respect to network ground terminal.
Note 2: For operation above 2SoC free-air temperature, refer to Dissipation Derating Curves in the Thermal Information section.
Note 3: All parameters, with the exception of OFF-state open·collector output current, are measured with the active pull-up connected to the
sink output.
Note 4: All typical values are at T A = 25· C and V CC = 5V, with the exception of ICC at 7V.
Note 5: Only one output should be shorted at a time, and duration of the short-circuit should not exceed one second.

Switching Characteristics
PARAMETER
tpLH

Propagation Delay

Vee = 5V, TA = 25°e

CONDITIONS

MIN

Ti~e,

Low·to-High-Level Output

DS55114
TYP

MAX

DS75114
TYP

MAX

15

20

15

30

ns

11

20

11

30

ns

MIN

UNITS

CL = 30 pF, (Figure 1)
tpHL

Propagation Delay Time,

High·to-Low-Level Output

1-58

AC Test Circuit and Switching Time Waveforms

INPUT

INPUT

VCC=5V

r------.
I
.--1 >4--+--0

2k

VANO
OUTPUT

ov
I

V

>r+--+--o~~;p~

*

II

OUTPUT

el
" " " 30 ,F

-lpHl

~_!

VOH~__'P_l_H_---t_f_ _ _ _ _~_~

1.5V--

VOl----+---'

(NOTE 2)

Z
OUTPUT

Note 1: The pulse generator has the following characteristics: ZOUT
Note 2: CL iQcludes probe and jig capacitance.

:::--_-_-_-_-_---:--__

~~_____,-_'_~J~

= son, tw = 100 ns, PRR = 500 kHz ..

FIGURE 1

Typical Performance Characteristics
Output Voltage vs Data
Input Voltage

Output Voltage vs Data
Input Voltage

N~ LoAD

NO LOAD
Vce = 5V

a

I- TA=2n

!:;

..~

>

>

?:
w

w

veJ = 5.lv Vee = 5V

"'"c

TA = -55'C--

--

.."

0.3

e

....

0.2

I

0.1

Vcc = 5.5V

/

3.6

<=4.5V

'~

3.2

~

2.8

"~

2.4

5
~
C>

1.6

>

V

=>
c

,I'

I
C>

'"

>

>

o

o

W W

ID

~

~

~

~

ro

10L- OUTPUT CURRENT (mA)

~

~

~ee=5V

r--

_J........ r-..
.r-....
r-- --Vce=4.5V

>

5
~
C>

o

-20

2

VCe=4.5V

I I I I

r--r--r- V;OH 1H~ pi- r-r .l......+-+I-

VOH (lOH - -40 mAl

1.2
0.8

25

50

Free-Air Temperature
VCe = 5V
(FIGURE 11

g
~
:E

>=

3D

>

~

20
'pLH

...;. ....-

./

>=
~

o

0

•

-80 -100 -120

40

i§

0.4 t-- r-VOL (lOL =4DmAI-::
'= '=
-15 -50 -25

-60

Propagation Delay Times vs

'"

I I I
I I I
I I I

-40

10H - OUTPUT CURRENT (mA)

Output Voltage ~s Free-Air
Temperature

,

I

';";"J

.......

VI - DATA INPUT VOLTAGE (V)

Low Level Output Voltage

TA = 2S"'C

I
I

1

C

vs Output Current
0.4

--

..

I

r-;;;)ee = 5.5V

w

I
:t:

o

o

a

>

VI- DATA INPUT VOLTAGE (V)

~

T~ =2;'e

>

o

w

T~J5oe

'"I
'"

I
C

!:;
c
>

TA = 25'C

5
~

vec - 4.5V

>

a

I

c

~
5c

High Level Output Voltage
vs Output Current

15 100 125

TA - FREE·AIR TEMPERATURE ( CI

~

10

t~HL

:::
o
-15 -50 -25

0

25

50

15 100 125

TA - FREE·AIR TEMPERATURE ( C)

*Data for temperatures below O'C and above 70'C and for supply voltages below 4.75V and above 5.25V are applicable to 0555114 circuits only.
These parameters were measured with the active pull~up connected to the sink output.

1-59

Typical Performance Characteristics *
Supply Current (Both Drivers)
vs Supply Voltage

C

I-

15
~

B
~

C

I

.g

15

INPUTS GROUNDED

40
30
20

~

~

.4;;TS OPEN-

I

10

o

..~

40

I-

50

I
u
u

ill

NO LOAD
TA'25 C

60

ll::

vs Frequency

42

70

."

o
VCC - SUPPLY VOLTAGE IV)

Supply Current (Both Drivers)

vs Frao·Air Temperature

80

.g

(Continued)

Supply Current (Both Drivers)

~

~
I
u
u

38
36

100
VCC' 5V
RL =00
CL = 30 pF
INPUTS' 3V SQUARE WAVE
iA=25"C

Vce' 5V
INPUTS GROUNDED
OUTPUTS OPEN

-- ......

r......

34

"

32
30
-75 -50 -25

~

'\
o

0

25

50

75 100 125

TA - FREJ;·AIRTEMPERATURE I"C)

0.1

0.4

I

10

40 100

f - FREnUENCY IMH,)

*Da;" for temperatures below O·C and above 70·C and for supply voltages below 4.75V and above 5.25V are applicable to DS55114
circuits only. These parameters were measured with the active pull·up connected to the sink output.
'

1-60

~National

a

Transmission Line
Drivers/Receivers

Semiconductor

c
en
CJ'1
~
......

~

c
en
.....

~
......

0555115/0575115 Dual Differential Line Receiver

CJ'1

General Description
The OS55115/0S75115 is a dual differentia'lline receiver
designed to sense differential signals from data transmission lines. Oesigned for operation over military and
commercial temperature ranges, the OS55115/0S75115
can typically receive ±500 mV differential data with
± 15V common-mode noise. Outputs are open-collector
and give TTL compatible signals which are a function of
the polarity of the differential input signal. Active
output pull-ups are also available, offering the option of
an active TTL pull-up through an external connection.

controlled and optional
are also available.

input termination resistors

Features
• Single 5V supply
• High common-mode voltage range
• Each channel individual,ly strobed
• Independent response time control
• Uncommitted collector or active pull-up option
• TTL compatible output
• Optional 130[1 termination resistors
• Oirect replacement for 9615

Response time may be controlled with the use of an
external capacitor. Each channel may be independently

Function Table

Connection Diagram
Dua'-' n-Line Package
VCC

2YS

2YP

2
2 RESP
STRB TIME CONT - B2

2RT

A2

.STROBE

DIFF.
INPUT

OUTPUT

L

X

H

H

L

H

H

H

L

H=

1YS

1YP

1
1 RESP
STRB TIME CONT

81

1RT

A1

GND

TOPVIEW'

Order Number DS55115J, DS75115J or
DS75115N
See NS Package J16A or N16A

1-61

v,tive2'than
: V,H min or VID more posiVTH max

L = V,:; V,L max or VID more negative than VTL max
X = irrelevant

I

Absolute Maximum Ratings

Operating Conditions

(Note 1)

MIN
7V
±25V
5.5V
14V

Supply Voltage, VCC (Note 1)
Input Voltage at A, Band RT Inputs
Input Voltage at Strobe Input
Off·State Voltage Applied to Open-Collector Outputs

Supply Voltage, (VCC)
DS55115
DS75115

Cavity Package
Molded Package

Operating Temperature, (T A)
D555115
D575115

Operating Fr'ee-Air Temperature Range

_55' C to +125' C
O'C to +10'C
-65'C to +150'C

UNITS
V
V

5.5
5.25
-5

Low Level Output Current, (lOL)

1433 mW
1362 mW

D555115
D575115

4.5
4.75

High Level Output Current, (lOH)

Maximum Power Dissipation* at 2S<> C

MAX

-55
0

mA

15

mA

125
70

'c
'c

Storage Temperature Range
Lead Temperature (1/16 inch from case
for 10 seconds)
300'C
"Derate cavity package 9.6 mW/'C above 25~C; derate molded
package 10.9 mWrC above 25'C.

Electrical Characteristics

(Notes 2, 3 and 5)

PARAMETER

VTH

VTL

DIfferential Input High-

Threshold Voltage
Differential Input

VIH(STROBE)

VIL(STROBE)

VOH

VOL

IlL

ICC

-200
15

-

to
-15

MAX

500

200

500

mV

-500

-200

-500

mV

2.4

15

24

to
-15

to
-19

Vee: Min, VIO: -0.5V,
10H: -SmA

Low Level Outpu,t Voltage

TA: Min

2.2

TA: 25'e

2.4
2.4

3.4

,

0.22

TA - Max

Vee: Min, VID : 0.5V, IOL : 15 mA
Vee: Max, VI : O.4V,
Other Input at 5.5V

Low Level Input Current

V

TA: 25'e

VSTROBE: 4.5V

TA - Max

Vee: Max, VID : 0.5V,
VSTROBE: O.4V

-0.5

.TA: Max

Vee: Min, VID : -0.5V:

0.5

TA~25'e

2.4
2.4

-1.15

VRe: O
Vee: Min, VOH: 12V,
VID: -4.SV

TA: 2s'e

100

Off·State Open·eollector

TA - Max

200

Line Terminating

Resistance
Short-Circuit Output
Current

V

-3.4

0.45
-0.9
-0.7

-1.2

IJ.A

-1.15

-2.4

rnA

-3.4

mA

TA-25'e

100

TA: Max

200

Vee: SV

TA: 25'e

77

Vee: Max, Vo: OV,
VID: -O.SV, (Note 4)

TA: 25'e

-15

VIC: OV

TA: 25'e

167

-40

-80

32

50

mA

5
10

Vee: Min, VOH : 5.25V,

130

V

0.5

Via: -4.7SV

. Vee: Max, VID: 0.5V,

Receivers)

V

-0.7

-2.4

Vee: Max, Via: 0.5V,

Output Current

-0.5

2
'5

Response Time Control

-1.2

3.4
0.22

0.4
-0.9
-0.7
-0.7

Current (Pin 4 or Pin 12)

TA: 25'e

0.4

2.4

TA: Min
TA:25'e

V

2.4

0.4

High Level Output Voltage

Supply Current (Bo\h

MIN

UNITS

TYP

24
to
-19

Low-Level Strobe

Low Level Strobe Current

lOS

a

Input Voltage

ISL

RT

200

Input Voltage

High Level Strobe Current

IO(OFF)

VO: D.4V, IOL: 15 mA, VIC: D

High-Level Strobe

ISH

14,112

MAX

VIO: ±lV

Voltage Range

0875115

TYP

MIN

Va: 2.4V, 10H: -5 mA, VIC':

Low·Threshold Voltage
Common-Mode Input

VieR

0855115

CONDITIONS

IJ.A

74

-130

179

n

-14

-40

-100

mA

32

50

mA

Note 1: ,. Absolute Maximum Ratings' are those values beyond which the safelY of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the -55'e to +125'C temperature range for the D555115 and across the oOe to
+70'e range for the DS75l15. All typical values are for TA : 25'C, Vce : 5V and VCM : OV.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.

Note 4. Only one output at a time should be shorted.
Note 5: Unless otherwise noted, VSTROBE

= 2.4V.

All parameters with the exception of off-state open-collector output current are measured

with the active pull-up connected to the sink output.

1-62

Switching Characteristics Vee = SV. eL = 30 pF. T A = 2soe
..
PARAMETER
CONDITIONS
MIN
tpLH

tpHL

Propagation Delay Time, Low-

to·High Level Output

Propagation Delay Time, Highto-Low Level Output

DS55115
TVP
MAX

MIN

DS75115
TVP
MAX

UNITS

RL = 3.9 kn. (Figure II

18

50

18

75

ns

RL = 390n. (Figure 1)

20

50

20

75

ns

Schematic Diagram
VCC

lk

1.5k

RT

RESPONSE
TIME
STROBE CONTROL

VCC

VCC

lk

1.64k
1.64k

1 pF

2.6k

20

L--+~t--o ~~LL.UP
INPUT A o-+-'lN"""'~-+--H

5k

500
7k

INPUT B

o----I-----+---I-------..J
130

150

3k

SINK
OUTPUT

r----'

150

I
I
I
I
I

YS

I
I

1.5k

IL"::- ___ .J
COMMON TO
BOTH RECEIVERS

Typical Application
Basic Party-Line or Data-Bus Differential Data Transmission

TWISTED
PAIR
LINE

--'-I.._A>--"'OI+
L _ _ _ _ _ _ .J
LOCATION 2

=c::t::

LOCATION 4

~ DS75115 RECEIVER

DS75113 DRIVER

*ZO is internal to the OS55115/0S75115
A capacitor may be connected in series with

1-63

Zo to reduce power dissipation.

Typical Performance Characteristics
Input Current vs Input

Output Voltage vs

Output Voltage vs Common-Mode

Voltage

Temperature

Input Voltage

6

5V.l .L.1 .L !...1. V

Vcc =
INPUT NOT UNDER TEST AT OV~
ITA=25 e

V

~

.5

:i'l

~

co

/

>

~

-2

V

-4

-6

I
I

3.2
2.B

I

co

>

-

2.4

l/,v

-25 -20-15 -10 -5 0

5 10 15 20 25

Vce = 5V

-"

co

O.B
_ VOL (VIO = 0,5V, 10L =15 mAl

w

l-

~
co

>
!;

25

50

~

w

~

/

0,1

Vcc = 5,5V

'"
~

co
>

!;
;!:

=
co
I

co

>

co

-50

10

15

20

25

30

~0,2

Output Voltage v.
Strobe Input Voltage

J

...- VCC=5VVCC - 4,5V

~

Output Voltage v. Strobe
Input Voltage
NO LOAD
VID = 0.5V
TA=25"C

~

w

~
>

~

I-

=
~
co

.1

o
Vs - STROBE INPUT VOLTAGE (VI

Propagation Delay Times
vs Temperature
30

40

30 1-+-+-It-h~£.j--1-l
20

~

10

~
I-

30

:i'l
0:

40

4-+TA= 25"C

Supply Current (Both Receivers)
vs Temperature
35

~
~

1-+-+-fIt-nof'-

~I

t-+--:l,,+-+-+--+-t--I

1l

:!
[:l

"i=>~

25
20

25

i=


o
0.1

'"
>

co

Vcc = 0.5V
NO LOAD
VIO = 0,5V

~=125"C

w

!;

Vec = 4,5V,\

>

LOAD = 2k TO VCC
TA=25'C

~

~

~VCC=5V

I

co

0,2

6

'"

~>
I=
~
co

0,1

-0,1

VIO - DIFFERENTIAL INPUT VOLTAGE (VI

10l - LOW LEVEL OUTPUT CURRENT (mAl

Output Voltage v.
Differential Input Voltage

-0,1

~
w

~I

>

10H - HIGH LEVEL OUTPUT CURRENT (mAl

-0,2

Vcc· 5V
LOAD = 2k to Vcc

~

1\
-40

,l'

,.I

5 10152025

Output Voltage v.
Differential Input Voltage

V

I

>

~IO ~ IV
-25-20-15-10-50

VIC - COMMON·MOOE INPUT VOLTAGE (VI

Vce=~

, ,,"/

0,2

~

VIO = -IV

>

75 100 125

0,3

;!:

;:

'"

0.4

~

rv;;;;

~

!;

/

I

w

NO LOAD
TA = 25"C

Vcc = 4.5V

3.4

~

'" 0.01

O.QOl

I'F may

0.01

0.1

CR - CAPACITANCE (JJF)

cause slowing of rise and fall times of the output.

AC Test Circuit and Switching Time Waveforms
OPEN

2.4V

INPUT

PULSE
GENERATOR
(NOTE 1)

B
~~...............

JO"-. . . .-oVO

>-"-L_~

T

~kpF
(NOTE 2)

RESPONSE
TIME CONTROL
OPEN
Note 1: The pulse generator has the following characteristics: ZOUT = 5011, PRR = 500 kHz/tw = 100 ns.
Note 2: CL includes probe and test fixture capacitance.

3V--~~~------~~

90%

DIFFERENTIAL
INPUT

OV
-3V

~10% tpHL

VOH
OUTPUT

I.SV
VOL----~~---------J

FIGURE 1. Propagation Delay Times

1-65

10

,....
C\I

~

II?A National
a Semiconductor

C\I

0555121/D575121 DUal Line Drivers

C

,....

~

Transmission Line
Drivers/Receivers

General Description

Features

The DS55121/DS75121 are monolithic dual line
. drivers designed to drive' long lengths of coaxial
cable, strip line, or twisted pair transmi'ssion lines
having impedances from 50 to 500 ohms. Both
are compatible with standard TTL logic and
supply voltage levels.

• Designed for digital data transmission over 50
to 500 ohms coaxial cable, strip line, or
twisted pair transmission. lines
• TTL compatible
• Open emitter-follower output structure for
party-line operation

The DS55121/OS75121 will drive terminated low
impedance lines due to the low·impedance emitter·
follower outputs. In addition the outputs are
uncommitted allowing two or more drivers to
drive the same line.

• Short-circuit protection
• AND-OR logic configuration
• High speed (max propagation delay time 20 ns)

Output short-circuit protection is incorporated
to turn off the output when the output voltage
drops below approximately 1.5V.

• Plug-in replacement for the SN55121/SN75121
and the 8T13

Typical Performance
Characteristics

Connection Diagram
Dual-In-Line Package

,2

F2
16

15

02

C2

.2

.2

Output Current vs Output Voltage
V2

-300

"

;;: -250

.s....
a:i

a:

r-r-r-r-r-r-r-",,-,
I-I--I-I--I-I-f-

-200

§

~ -150

~

-100

I

.E -50

o

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vo - OUTPUT VOLTAGE (V)

AI

B1

Cl

01

E1

F1

VI

GNO

Truth Table

TOPVIEW

Order Number DS55121J, DS75121J or DS75121N
See NS Package J16A or N16A

OUTPUT

INPUTS

V

A

B

C

0

E

F

H

H

H

H

X

X

H

X

X

X

X

H

H

H

AllOlhel Input

L

Cornbln3

'3

RJ

Y3

INPUTS

OUTPUT
V

A

st

H

H

X

X

X

X

L

H

L

L

X

H

X

L

X
L
L

X

L

H

X

X

L

H
H
H
H

X
X

R

S

H == high level, L "" low level, X

L

=

irrelevant

ts mput and last two lines of the truth table
are applicable to receivers 1 and 2 only.

A1

,81

RZ

OZ

'2

8Z

YZ

GND

TOP VIEW

Order Number DS55122J, DS75122J or DS75122N
See NS Package J16A or N16A

AC Test Circuit and Switching Time Waveforms
Vee

2.6Y

84.S

:;:;S.Ons
2.GV

IN31164

INPUT

OUTPUT
5.Dk

VOH

OUTPUT
Voc

':'

Note 1: The pulse gllnilitor has the following ch.raeteristies:
loUT .. 50!!, tw '" 200 nl, duty cycle'" 50%. 1, '" If = 5.0 ns.
Note 2: CL includtsprob8 and jig capacitance.

1-68

Absolute Maximum Ratings

Operating Conditions

(Note 1)

,
Supply Voltage, VCC
Input Voltage
R Input
A, B, or S Input
Output Voltage
Output Current
Maximum Power Dissipation"" at 25"' C
Cavity Package
Molded Package

Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

6.0V

UNITS

MIN

MAX

4.75

5.25

V

+125
+75

°c
°c

High Level Output Current,

--500

JlA

IOH
Low Level Output Current.

16

rnA

Supply Voltage, VCC

Operating Temperature, T A

6.0V
5.5V
6.0V
'.100 rnA

-55

OS55122
OS75122

1433 mW
1362mW
-£5°C to +150°C
300°C

0

IOL

*Derate cavity package 9.6 mW/oC above 25°C; derate molded
package 10.9 mWtC above 25°C.

Electrical Characteristics

Vee = 4.75V to 5.25V (unless otherwise noted) (Notes 2 and 3)

PARAMETER

CONOITIONS

V'H

High Level Input Voltage

A,B,R,orS

V'L

Low Level Input Voltage

A,B,R,arS

Hysteresis

Vee

= 5.0V, T A = 25°C,

Input Clamp Voltage

Vee

= 5.0V,

I,

Input Current at Max Input Voltage

Vee

=5.25V, V'N

V OH

High Level Output Voltage

-VT-~

I,

= -12

= -500JlA

VilA! :::

Low Level Output Voltage

= 16 rnA·

I'H

av, V UB1

= 1.45V,

VUA) =

VIlA)

High Level Input Current

= 0.8V,

V,

= 4.5V,

av, VIIB)

INoto 4)

= OV,

V"s)

V 1H - 2.0V, V"
IOL

0.3

R,INoto 6)

=2.0V, INote 7)

= 0 8V,
-:-

V,

los

Short Circuit Output Current

Vee' 5.0V, TA

Icc

Supply Current

Vee

Switching Characteristics
PARAMETER

tpLH

tpHL

0

V

1.0

mA

V

V
V
0.4

INote 4)

0.4

INoto 8)

40

A, B, or S

Low Level Input Current

-1.5

2.6

170

V, ' 3.8V, R
I'L

V

2.6

OV,

= 1.45V, V"S' = 2.0V,

O.4V, A, B, or S

= 25"C,

INote 5)

UNITS

0.8
0.6

= 5.5V,II, B, or S

VilA)
VOL

MAX

V

mA, A, B, or S

V'H = 2V, V'L
10H

TYP

2.0

V,

VT-t

MIN

V
V

pA
pA

0.1

-1.6

mA

·-50

-100

mA

72

mA

TYP

MAX

UNITS

20

30

ns

20

30

ns

=5.25V

Vec = 5.0V, TA = 25°C
CONOITIONS

Propagation Delay Time, Low-to-High

(See ac Test Circuit and SWltchlllg

Level Output from R Input

Time Waveforms)

Propagation Delay Time, High-to-Low

(See ac Test CIrCLIlt and Switching

Level Output from R Input

Time Waveforms)

MIN

,

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: All currents into device pins are shown as positive, currents out of device pins'shown as·negative, all voltage values are referenced with
respect to network ground terminal, unless otherwise noted. All values shown as max or min on absolute value basis.
Note 3: Min/max limits apply across the guaranteed operating temperature range of -55°C to +125 °c for 0555122 and oOe to +7Soe for
OS75122, unless otherwise specified. Typicals are for Vee = 5.0V. TA = 25°C. Positive current is defined as current into the referenced pin.
Note 4: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the truth table
for the desired au tput.
Note 5: Not more than one output should be shorted at a time.
Note 6: Hysteresis is the difference between the positive going input threshold voltage, VT+, and the negative going input threshold voltage, VTNote 7: Receiver input was at a high level immediately before being reduced to 1.45V.
rJota 8: R::!ceiver input was at a low level immediately before being roised to.1.45V.

1·69

Typical Performance Characteristics
Out'"'t Voltage VI Receiver Input Voltage
4.0

~

3.5

YI

3.0

~

2.5

~

2.0

~

1.5

I

1.0

co

co

co

~

Jcc ! 5.JV
NO LOAD
T. =+25"C

VT _

VT •

0.5

o

o 0.2

0.4 0.6 '0.8 1.0 1.2 1A 1.6 1.8 2.0
V, -INPUT VOLTAGE (V)

Typical Applications

L __ '~S~2_ _ .J
75

15 COAXIAL CABLE

75 COAXIAL CABLE

.".

Single·Ended. Party Line Circuits

INPU~

V'H~
V,
V
T_

T+

V"
VOH--r--I

L

OUTPUT.-J

It.

Yo,

Tbe
gaUl and bmlt·m hYltere51S of the 0555122/DS75122
hne receivers enlble them to be used asSchmrtttrlygen in
squlnnguppulses.

Pulse Squaring

1·70

L __'~Sl.!!!2 _ _ .J

~National

Transmission Line
Drivers/Receivers

~ Semiconductor
D575123 Dual Line Driver
General Description

Features

The DS75123 is a monolithic dual line driver
designed specifically to meet the I/O interface
specifications for IBM System 360. It is com·
patible with standard TTL logic and supply voltage
levels.

•

The low-impedance emitter-follower outputs of
the DS75123 enable driving terminated low impedance lines. In addition the outputs are un·
commited allowing two or more drivers to drive
the same line.

• 3.11V output at

Meet IBM System 360 I/O interface specifica·
tions for digital data transmission over 50n to
500n coaxial cable, strip line, or terminated
pair transmission lines

• TTL compatible with single 5.0V supply

• AND-OR logic configuration
• Plug-in replacement for the SN75123 and the
8T23

Typical Performance
Characteristics

Connection Diagram
Dual-In-Line Package
F2

01

~1

15

C1

., .,

-59.3 mA

• Short circuit protection

Output short-circuit protection is incorporated
to turn off the output when the output voltage
drops below approximately 1.5V.
.

16

10H =

• Open emitter-follower output structure for
party-line operation

V1

Output Current vs Output Voltage
-300

14
~

E

-250

....

i

:>
u

-200
-150

~

~ -10'1
I

.E -50

,.

o

.,

C1

01
E1
TOP VIEW

F1

VI

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Vo - OUTPUT VOLTAGE (V)

GND

Order Number DS75123J or DS75123N
See NS Package J16A or N16A

Truth Table
INPUTS

E

B

C

0

H

H

H

H

X

X

H

X

X

X

X

H

H

H

F

All Othel Input Combllldtions

H = high level, L

J.DV

:::: 5.0 n5

,.ov ------1-ir=-=-i
INPUT

>--+-""--,,,,-0 OUTPUT
C,
(NOTE 2J

OUTPUT
':'

Note 2:

':'
ZOUT .

CI. INCLUDES PROBE AND JIG CAPACITANCE.

1-71

50!I,

L

= low level, X = irrelevant

AC Test Circuit and Switching Time Waveforms

Note 1: THE PULSE GENERATORS HAVE THE FOLLDWING CHARACTERISTICS:
tw '" 200ns, DUTY CYCLE = 50%.

OUTPUT
Y

A

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Supply Voltage, VCC
Input Voltage
Output Voltage

Supply Voltage, VCC
High Level Output Current,
IOH
Temperature, T A

7.0V
5.5V
7.0V

Maximum Power Dissipation* at 25°C

Cavity Package
Molded Package
Operating Free-Air Temperature Range

Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

MIN

MAX

4.75

5.25
-100

0

+75

UNITS
V
mA
°c

1371 mW
1280mW
O°C to +75°C
-B5°C to +150°C
300°C

"Derate cavity package 9.1 mW/'C above 2s"C; derate molded
package 10.2 mWI"C above 25'C.

Electrical Characteristics

(Notes 2 and 3)

PARAMETER

CONDITIONS

V,H

High Level Input Voltage

V'L

Low Level Input Voltage

V,

Input Clamp Voltage

Vee = 5.0V, I,

I,

Input Current at Max Input Voltage

Vee

V OH

High Level Output Voltage

Vee = 5.0V, V,H = 2.0V,
10H = -59.3 mA, (Note 4)

10H

High Level Output Current

Vee
VOH

= 5:0V, V,H = 4.5V, TA
= 2.0V, (Note 4)
= 0.8V,

MIN

= 5.25V, V ,N

-1.5

= 5.5V

= -240!lA,

1
ITA = 25°C
ITA =0"Cto+75°C

Low Level Output Voltage

V'L

Off State Output Current

Vee = 0, Vo

I'H

High Level Input Current

V, = 4.5V

I'L

Low Level Input Current

V,

los

Short Circuit Output Current

Vee

leeH

Supply Current, Outputs High

Vee

= 5.0V, TA = 25°C
= 5.25V, All Inputs at <.OV, Outputs Open

feeL

Supply Current, Outputs Low

Vee

= 5.25V, All

PARAMETER
'Propagation Delay Time, Low·
to·High Level Output

t pHL

Propagation Delay Time, High·
to· Low Level Output

10L

V
mA

V
-250

0.15

(Note 4)

= 3.0V

40

= O.4V

V

V

3.11
2.9
-100

= 25°C,

UNITS
V

=-12 mA

VOL

t pLH

MAX

0.8

1010FFI

Switching Char...acteristics

TYP

2.0

-D.l

mA

V
!lA

40

!lA

-1.6

mA

-30

mA

28

mA

60

mA

TYP

MAX

UNITS

20
35

ns
ns

20
25

ns
ns

Inputs at 0,8V, Outputs Open

Vee = 5.0V, T A = 25°C
CONDITIONS

MIN

RL = 50n, (See ac Test Circuit

CL = 15 pF

and Switching Time Waveforms

C L = 100 pF

12
20

RL = 50n, (See ae Test Circuit
and Switching Time Waveforms

C L = 15 pF
CL = 100pF

12
15

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
lemperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: All currents into device pins are shown as positive, currents out of device pins shown as negative, all voltage values are referenced with
respect to network ground terminal. unless otherwise noted. All values shown as max or min on absolute value basis.

Note 3: Minimax limits apply across the guaranteed operating temperature range of O°C to +75°C for DS75123, unless otherwise specified. Typi·
cals are for

Vee = 5.0V, T A = 25°C. Positive current is defined as current into the referenced

pin.

Note 4: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the truth table

for the desired output.

1-72

~National

Transmission Line
Drivers/Receivers

~ Semiconductor

0575124 Triple Line Receiver
General Description

Features

The 0575124 is designed to meet the inputl
output interface specifications for I BM System
360. It has built·in hysteresis on one input on
each of the three receivers to provide large noise
margin. The other inputs on each receiver are in
a standard TTL configuration. The 0575124 is
compatible with standard TTL logic and supply
voltage levels.

•
•
•
•
•
•

Built·in input threshold hysteresis
High speed .. typ propagation delay time 20 ns
Independent channel strobes
Input gating increases application flexibility
Single 5.0V supply operation
Plug·in replacement for the SN75124 and the
8T24

Connection Diagram and Truth Table
Dual-. n-Line Package
vee

S

OUTPUT
y

X

X

L

L

H

L

H

X

H

X

X

L

H

L
L

H

X

H

X

L

H

A

INPUTS
Bt
R

H

H

X

X

L

X

L
X
X

H '" high level, L = low level, X = irrelevant
te input and last two lioes of the truth table
A1

B1

R2

S2

A2

B2

V2

GND

TDP VIEW

Order Number DS75124J or DS75124N
See NS Package J16A or N16A

Typical Application
A
B
C
D

r-----,
·1
95 CDAXIAL CABLE

1·73

are applicable to receivers 1 and 2 only.

,

"=:t

C\I
,...

Absolute Maximum Ratings

Operating Conditions

(Note 1)

U")

l'o(/)

C

Supply Voltage, VCC

7.0V

Input Voltage
R Input with VCC Applied
R Input with VCC not Applied
A, 8, or S Input
Output Voltage
Output Current
Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package

Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

Supply yoltage, VCC

MIN

MAX

4.75

5.25
-800

V
I'A

16

mA

+75

°c

High Level Output Current,

7.0V
6.0V
5.5V
7.0V
±100 mA

UNITS

IOH

Low Level Output Current,
IOL
Operating Temperature, TA

0

1433 mW
1362 mW
O°C to +75°C
-65°C to +150°C
300°C

*Derate cavity package 9.6 mW/oC above 25°C; derate molded
package 10.9 mW/oC above 25°C.

Electrical Characteristics

(Notes 2 and 3)

PARAMETER
V ,H

CONDITIONS

High Level Input Voltage

MIN

A.B,orS

2.0

R

1.7

TYP

MAX

UNITS
V
V

V ,L

Low Level I nput Voltage

A, B, or S

V T1 -V T-

Hysteresis

Vee = 5.0V, TA = 25 u C, R, (Note 6)

V,

I nput Clamp Voltage

Vee = 5.0V, I, = -12 mA, A, B, or S

-1.5

I,

Input Current at Maximum

Vee = 5.25V, V ,N = 5.5V, A, B, or S

1

mA

5.0

mA

5.0

mA

R

Input Voltage

V OH

R

0.2

V

0:7

V

0.4

I V, = 7.0V

I V, = 6.0V, Vee = 0
IOH = -SOO,uA,

0.8

V

High Level Output Voltage

V 1H =: VIHMIN' V 1L
(Note 4)

VOL

Low Level Output Voltage

V 1H = VINMIN' V 1L '" V1L MAX, IOL = 16 mA, (Note 4)

0.4

V

IIH

High Level Input Current

V, = 4.5V, A, B, or S

40

/JA

V, = 3.11V, R

170

/JA

-0.1

-1.6

mA

Short Circuit Output Current

Vee = 5.0V, T A = 25'~C, (Note 5)

-50

-100

mA

Supply Current

Vee = 5.25V

72

mA

TYP

MAX

UNITS

20

30

ns

20

30

ns

Low Level InlJut Current

los
Icc

Switching Characteristics

T A = 25°C, nominal power supplies unless otherwise noted

PARAMETER

tpHL

V

V, = O.4V, A, B, or S

I'L

tpLH

:::; VILMAX,

2.6

V

CONDITIONS

Propagation Delay Time, Low-to-High

(See ac Test Circuit and Switching

Level Output from R Input

Time Waveforms)

Propagation Delay Time, High-to-Low

(See ac Test Circuit and Switching

Level Output from R Input

Time Waveforms)

MIN

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "OperatIng
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation_

Note 2: All currents into device pins are shown as positive, currents out of device pins shown as negative, all voltage values are referenced with
respect to network ground terminal, unless otherwise noted_ All values shown as max or min on absolute value basis.
Note 3: Min/max limits apply across the guaranteed operating temperature range of O°C to +75°C for OS75124, unless otherwise specified_ Typicals are for V CC == 5.0V, T A = 25° C. Positive current is defined as current into the referenced pin.
Note 4: The output voltage and current limits are guaranteed for any appropriate combination of high and low inputs specified by the truth table
for the desired output_
Note 5: Not more than one output should be shorted at a time_
Note 6: Hysteresis is the difference between the positive going input threshold voltage, VT+, and the negative going input threshold voltage, VT-'

1-74

AC Test Circuit and Switching Time Waveforms

Vee

2.6V

84.5

lN3D64

)0-+--...--"'" OUTPUT

I

5.0k

L __ -.l.- __ ..J

INOTE 2)

-=

Note1: THE PULSE.GENERATOR HAS THE FOLLOWING CHARACTERISTICS:
DUTY CYCLE = 50%.

Note 2:

CL INCLUDES PROBE AND JIG CAPACITANCE.

~5.0ns

2.6V-H.-=-.....,.",i
INPUT

VOH

---+r-----"'\

OUTPUT
Va'

Typical Performance Characteristics

Output Voltage v.
ReceivBr Input Voltage
4.0

,.

3.5

w

3.0

'"':;"

,.

. =' 5.0V
J.
I- .'Vee
NO LOAD
TA '" 25°C

2.5

0

~

2.0

Vr_

Vr •

1.5

0

I

,.a

1.0
0.5

o

o

0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.B 2.0

V, - INPUT VOLTAGE IV)

1·75

louT'" 50!!, tw = 200 ns,

.....

('I

lti ~ National

Transmission Line
Drivers/Receivers

&i a'Semiconductor

c
~

~
en
c

0575125, 0575127 Seven-Channel Line Receivers,
General Description

Features

The 0575125 and 0575127 are monolithic seven·channel
line receivers designed to satisfy the requirements of the
IBM System 360/370 input/output interface specifica·
tions. Special low·power design and Schottky clamped
transistors allow for low supply current requirements
whiie maintaining fast switching speeds and high current
TTL outputs. The 0575125 and 0575127 are character·
ized for operation from O·C to 70 ·C.

•
•
•
•
•
•
•

Meets IBM 360/370 I/O specification
Input resistance- 7 kG to 20 kG
Output compatible with TTL
Schottky·clamped transistors
Operates from single 5V supply
High spee~-Iow propagation delay
Ratio specification for propagation delay time, low·to·
highlhigh·to·low
,
,
• Seven channels in one 16·pin package
'_. Standard Vee and ground positioning on 0575127

Connection Diagrams
D575125
Dual·ln·Llne Package
IV

16

Vee

1,5

3V

14

4V

5V

13

12

D575127
Dual·ln·Line Package

6V
11

7V
10

Vee

2V

19

16

IV
15

2V

14

3V

4V

13

12

5V

11

6V

7V

10

I

D
IL
1

lA

2

2A

3

3A

5

4
4A

5A

6

6A

7
lA

2 ,

18

GND

IA

2A

3A

4A

5A

6A

7A

TOP VIEW

TDPVIEW

loglc:Y=A

loglc:Y=A

Order Number DS75125J or DS75125N
See NS Package J16A or N16A

Order Number D575127J or DS75127N
See NS Package J16A or N16A

-

1·76

GND

Absolute Maximum Ratings

Recommended Operating Conditions

(Note 1)

Supply Voltage, Vcc(Note 1)
Input Voltage Range
DS75125
DS75127

7V

Supply Voltage, Vee
High·Level Output Current, 10H
Low·Level Output Current, 10L
Operating Free·AirTemperature, TA

-0.15Vto7V
-2Vt07V

Maximum Power Dissipation· at 25°C

Min

Typ

Max

Units

4.5

5

5.5
-0.4
16
70

V
mA
mA
"C

0

Cavity Package
Molded Package

1509mW
1476mW
Operating Free-AirTemperature Range
O"Cto70"C
Storage Temperature Range
- 65"Cto 150"C
Lead Temperature (Soldering, 10 seconds)
300"C
"Derate cavity package 10.1 mW/"C above 25"C; derate molded package
11.9 mW/"C above 25"C.

Electrical Characteristics

over recommended operating free-air temperature range (Note 3)

Parameter

V IH

High·Level Input Voltage

V IL

Low·Level Input Voltage

Conditions

Min

Typ
(Note 5)

Max

1.7

V
0.7

V OH High·Level Output Voltage

Vcc=4.5V, V IL =0.7V, 10H= -0.4 mA

VOL Low·Level Output Voltage

2.4

Units

3.1

Vcc=4.5V, VIH=1.7V, IOL=16 mA

0.4

IIH

High·Level Input Current

V cc =5.5V, V I =3.11V

0.3

IlL

Low·Level Input Current

Vcc= 5.5V, VI = 0.15V

los

Short·Circuit Output Current (Note 4)

Vcc= 5.5V, Vo= 0

rl

Input Resistance

Icc

Supply Current

V cc = 4.5V, OV, or Open,
Ll,V I =0.15V to 4.15V
V cc =5.5V, 10H= -0.4 mA,
All Inputs at 0.7V

V
V

0.5

V

0.42

mA

-0.24

mA

-18

-60

mA

7

20

kn

15

25

mA

28

47

mA

Typ

Max

Units

V cc =5.5V, 10L= 16 mA,
All Inputs at 4V

Switching Characteristics V cc = 5V, TA = 25°C
Parameter

Conditions

Min

t pLH Propagation Delay Time, Low-to·High-Level Output

7

14

25

ns

t pHL Propagation Delay Time, High·to·Low·Level Output

10

18

30

ns

tpLH Ratio of Propagation Delay Times
tpHL

RL = 400n, CL
See Figure 1

=50 pF,

0.5

0.8

1.3

tTLH Transition Time, Low·to-High-Level Output

1

7

12

ns

tTHL Transition Time, High-to-Low·Level Output

1

3

12

ns

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature Range"
they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device

operation.
Note 2: For operation above 25°C free-air temperature, refer to Thermal Ratings for ICs in Section 12 of Interface Databook.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.

Note 4: Only one output should be shorted at a time.
Note 5: All typical values are at VCC=5V, TA=25"C.

1-77

Schematic (each receiver)
cv~ee__________~__~________________~____________~____~__-__~--~_--~_--~~-___-___-__~~~~~~~~:~
150
NOM

A

INPUT

12k
NOM

I

~--------------------------------~~-------------------;~~}~~:J~:~

GND

L __ ~O~ON~C~R~

AC Test Circuit and Switching Time Waveforms
Vee

3V
INPUT
OV
VOH
OUTPUT

':"

VOL

':"

Not. ,: The pulse generator has the following characteristics: ZOUT~ 5011, PRR = 5 MHz,
Note 2: C L includes probe and jig capacitance,
Note 3: All diodes are' N3064 or equivalent.

FIGURE1

1-78

10%

__

...J '

Typical Performance Characteristics,

Voltage Transfer
Characteristics

Voltage Transfer
Characteristics
5

~
w

:;
"'"
Q

....>
"....
~

"I

- r-~A ~70'~--r-'

Vee 0 5V
NO LOAD

~

4

-

TA

f-

3

2

-

f-

o'e

w

I I

~
>

0

Q

Vee
4

0

Vee

Vee 0 5V
NO LOAD

5,5V

0

4,5V

"

~

.s....

0,3

B

0,2

~

2

I

Q

1

>

/

~

3

....

!-- TA=25'e-

TA '" 25°C

~

5V

Vee

'"

Q

>

Input Current vs
Input Voltage
0,4

5

I

/
/

0,1

.=

1

/

1/

TA = 25'e
NO LOAD
0

I

0
1

0

2

0
0

1

0,6

"'"
~

0,5

~

0,4

>

~

0,3

~

~I
Q

>

30
~

......V

.s....

~

~

'"
B
~

/

w

~

Supply Current vs
Supply Voltage

Vee" 5V
VI =5V
TA = 25"e

w

02

2

~
I

'"''"'

0,1

~

ALL SEVEN CHANNELS
NO LOAD
TA = 25'e

25

ALL INPLTS
AT4V

20
15

ATOik- V~

ALL INPUTS

10

-

I

r-:- L

/.,. /

V

5
- 0

0
0

5

10

15

20

0

1

2

3

4

5

Vee - SUPPL V VOLTAGE (V)

10 - OUTPUT CURRENT (mAl

1-79

3

4

VI -INPUT VOLTAGE (VI

Low-Level Output Voltage
vs Output Current
~

1

0

2

VI -INPUT VOLTAGE (VI

VI-INPUT VOLTAGE (VI

6

5

~National

a

Transmission. Line'
Drivers/Receivers

Semiconductor

0875128, 0875129 Eight-Channel Line Receivers
General Description

Features

The 0575128 and 0575129 are eight-channel line
receivers designed to satisfy the requirements of the
input-output interface specification for IBM 360/370_
Both devices feature common strobes for each group of
four receivers_ The 0575128 has an active-high strobe; the
0575129 has an active-low strobe_ Special low-power
design and schottky-diode-clamped transistors allow
low supply-current requirements while maintaining fast
switching speeds and high-current TTL outputs_ The
0575128 and 0575129 are characterized for operation
from 0 °C to 70°C_

•
•
•
•
•
•
•
•
•

Meets IBM 360/370 1/0 specification
Input resistance - 7 kO to 20 kO
Output compatible with TTL
Schottky-clamped transistors
Operates from a single 5V supply
High speed -low propagation delay
Ratio speCification -tpLH/tpHL
Common strobe for each group of four receivers.
0575128 strobe-active-high
0575129 strobe-active-Iow

Connection Diagrams
0575128
Dual-In-Line Package

yee

IV

2V

3V

4V

5V

6Y

1V

BV

2S

Order Number D575128J or D575128N
See Ns Package J20A or N20A

IS

IA

3A

2A

4A

5A

6A

1A

BA

GND

7Y

BY

2S

TOP VIEW
positive logic: V = AS

0575129
Dual-In-Line Package

vee

IV

2Y

3V

4V

5V

6V

Order Number Ds75129J or D575129N
5ee N5 Package J20A or N20A

IS

lA

2A

3A

4A

5A

6A

1A

TOP VIEW
positive logic: V = AS

1-80

BA

GNO

Absolute Maximum Ratings over operating

Recommended Operating Conditions

free-air temperature range (unless otherwise noted)
Supply Voltage, Vce (Note 1)
A Input Voltage Range
Strobe lriput Voltage
Maximum Power Dissipation' at 25'C
Cavity Package
Molded Package
Operating Free·AirTemperature Range
Storage Temperature Range
Lead Temperature
1116 inch from Case for 60 Seconds: J Package
'Lead Temperature
1116 inch from Case for 10 Seconds: N Package

7V
-0.15Vto7V
7V

Min
4.5

Supply Voltage, Vce
High-Level Output Current, IOH
Low-Level Output Current, IOL
Operating Free·Alr Temperature, TA

Typ
5.0

Max Units
5.5
V
-0.4 rnA
16 rnA
70 ·C

0

1564mW
16B7mW
0'Ct070'C
-65'Cto150'C
300'C
260'C

• Derate cavity package 10.4 mW/'C above 25'C; derate molded package
13.5 mW/'C above 25·C.

Electrical Characteristics

over recommended operating free-air temperature range (Note 3)

Parameter
V IH ' High-Level Input Voltage

~
S

V IL

~
S

Low-Level Input Voltage

V OH High-Level Output Voltage

S Vcc=4.5V, 11= -18 mA

High-Level Input Current

A Vcc= 5.5V, VI = 3.11V
S V cc =5.5V, V I =2.7V

IlL

Low-Level Input Current

A Vcc=5.5V, V =0.15V
S V cc =5.5V, V I =O.4V

los

Short-Circuit Output Current V cc =5.5V, Vo=O
(Note 4)

rl

Input Resistance

Icc

Supply Current

2.4

OS75128
OS75129
OS75128
OS75129

Vee = 5.5V,
V cc =5.5V,
V cc =5.5V,
V cc =5.5V,

Strobe
Strobe
Strobe
Strobe

V

0.5

V

V

-1.5
0.3

2.4V,
0.4V,
2.4V,
O.4V,

All
All
All
All

A Inputs
A.lnputs
A Inputs
A Inputs

at
at
at
at

mA
fAA

-0.24
-0.4

mA

-6Q

mA

20

kO.

31
31
53
53

mA

7
19
19
32
32

0.7V
0.7V
4V
4V·

V

0.42
20

-18

at
at
at
at

0.7
0.7
3.1
0.4

Vcc=4.5V, OV, or Open, tN I =0.15V to 4.15V

Units
V

V cc =4.5V,.V IH =1.7V, IOL=16 mA

Input Clamp Voltage

IIH

Max

1.7
2

Vcc=4.5V, V IL =0.7V, 10H= -0.4 mA

VOL Low-Level Output Voltage
. VI

Typ
(Note 5)

Min

Conditions

SWitching Characteri$tics V cc = 5V, TA = 25 DC
Parameter
tpLH

Propagation Delay Time, Low-to-High-Level Output

tpHL

Propagation Delay Time, High-to-Low-Level Output

tpLH

Propagation Delay Time, Low-to-High-Level Output

tpHL

Propagation Delay Time, High-to-Low-Level Output

Conditions

A

7

14

25

7

14

25

ns

10

18

30

10

18

30

ns

26

40

20

35

ns

22

35

16

30

ns

S
C L =50 pF,

Ratio of Propagation Delay Times

tTLH

Transition Time, Low-to-High-Level Output

tTHL

Transition Time, High-to-Low-Level output

Units

RL =4000,

tpLH
tpHL

D575128
D575129
Min· Typ Max Min Typ Max

A

0.5
See Figure 1

0.8

1.3

0.5

0.8

1.3

1

7

12

1

7

12

ns

1

3

12

1

3

12

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for
actual device operation.

Note 2: For operation above 25'C free-air temperature, refer to Thermal Ratings for ICs, Section 12, Interface Databook.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values
shown as max or min on absolute value baSis.

Note 4: Only one output should be shorted at a time.
Note 5: All typical values are at VCC = 5V, TA = 25·C.
1-81

Schematic Diagram (each receiver)
r------t~--------------~------------~--~-o~C

,
r---:----------I
.

INPU!o-~-----------""""""__--------1I--I

lZk
NOM

I
I
I
I

....________....O~UTPUT

11k

NOM

O~J_

r---,I II

OS761z81

I

I
I

I

II

-+.....~

INPU~Oo'++-....

....----+..----------~-----.._oGNO

..J.J

I

,

r

I

I

I
I

I
I
I
L ___________ __ JI
I
I
_1

I
I

ONE OF lWO

I
I

I

I
I
L ~C.!!!!.R!.COMMON

TO THREE
OTHER
CHANNELS

_ _ _ __

j

I
I
I

TO SEVEN
OTHER CHANNELS

AC Test Circuit and Switching Time ,Waveforms

OUTPUT

Vee

(SEENOTE3)

. . .I-.....H ...-t...-,

F~~~::~:o-+

50.F

.

OUTPUT

TISEENOTEZ)
VOL

Nola 1:
Nota 2:
Note 3:
Note 4:

Input pulses 'are supplied by a generator having the following characteristics:
Includes probe and jig cap~citanc~.
.
All diodes are 1N3064 or equivalent.
The strobe inputs of 0575129 are in·phase with the output.

----I-=F::.:..--....;;=r

Zo = 5011, PRR=5 MHz.

Note 5: VREFt =O.7V and VREF2= t.7V for testing data (Al inputs, VREFI =VREF2=1.3V for strobe inputs.

FIGURE 1

1-82

c

~

Typical Characteristics

en
.....

Voltage Transfer Characteristics
From A Inputs
l - i- ~A .17I1"k_r-1-

.
.
...
~.
.
~

Voltage Transfer Characteristics
From A Inputs

VCC'5V
NO LOAD

I- f-TA/i

.

I I

s:...

VCC = ~.5V

~

w

v~c· SV

w

~

>

TA =25"C

1--1-

v C'4.S":

~

.~.

I

I

>

>

u

o

o

TA=2S"C
NO LDAD

o

VI-INPUT VDLTAGE IVI

VI-INPUT VDL TAGE IV)

Input Current vs
Input Voltage. A inputs
0.4

".s...f5

....=="
"
~
I

Low-Level Output Voltage va
Output Current

..

VCC' 5V
ND LDAD
TA = 25"C

8.6

~

0.5

.

0.]

>

0.2

8.1

o

~
w

/

~

0.4

S

0.3

. "I!:

"
1/ "

VCC = SV
VI=SV
TA=2S"C

~
",..

/"

w

~

0.2

~

0.1

/"

;::

...

I

,;>

o

0

o
VI-INPUTVDlTAGE IVI

10

IS

ID - OUTPUT CURRENT ImAI

1-83

20

...~

~National

a

Transmission Line
Drivers/Receivers

Semiconductor

0875150 Dual Line Driver
General· Description

Features

The DS75150 is a dual monolithic line driver designed'
to satisfy the requirements of the standard interface
between data terminal equipment and data communication equipment as defined by EIA Standard RS-232-C.
A rate of 20,000 bits per second can be transmitted with
a full 2500 pF load. Other applications are in datatransmission systems using relatively short single lines,
in level translators, and for driving MOS devices. The
logic input is compatible with most TTL and LS families. Operation is from -12V and +12V power supplies.·

• Withstands sustained output short·circuit to any
low impedance voltage between -25V and +25V
• 2/ls max transition time through the -3V to +3V
transition region under full 2500 pF load
• Inputs compatible with most TTL and LS families
• Common" strobe i"nput
• Inverti ng output
• Slew rate can be controlled with an external capacitor
'.
at the output
±12V

• Standard supply voltages

Schematic and Connection Diagrams

.v~~~~~------~--~----~-------,
TO OTHER
LINE DRIVER

INPUT A

Dual·ln·Line Package

STROBE s ~,""","""'I-I""'-I

+Vcc

1Y

2,y

-Vee

STROBE
S

INPUT
1A

INPUT
ZA

GNU

TO OTHER

LINE DRIVER

GNO -<~__________, -____--4~__"""__
CDmponent values shown ate nominal.

112 of clrtuitsbown

1-84

Absolute Maximum Ratings
Supply Voltage +VCC
Supply Voltage -Vec
Input Voltage
Applied .Output Voltage
Storage Temperature Range

Operating Conditions

(Note 1)

15V
-15V
15V
±25V
-65°C to +150°C

Supply Voltage (+VCC)
Supply Voltage (-VCC)
Input Voltage (VI)

MAX

UNITS

10.8
-10.8

13.2
-13.2

.v

+5.5

V

0

Output Voltage (VO)

Maximum Power Dissipation* at 25°C

Cavity Package
Molded Package
Lead Temperature (Soldering, 10 seconds)

MIN

Operating Ambient Temperature

1133mW
1022mW
300'C

0

V

±15

V

+70

°c

Range (TA)

'Derate cavity package 7.6 mW/'C above 25'C; derate molded
package 8.2 mWI'C above 25'C.

DC Electrical Characteristics

(Notes 2, 3, 4 and 5)
CONDITIONS

PARAMETER
V,H

High-Level Input Voltage

V,L

Low- Level Input Voltage

(Figure 2J

VOH

High-Level Output Voltage

+Vee = 10,8V, -Vee = -13_2V, V,L = 0_8V,

MIN

TVP

MAX

V

2

(Figure 1J

0_8
5

UNITS

V
V

8

R L = 3 H2 to 7 H2, (Figure 2J
VOL

Low-Level Output Voltage

+Vee = 10.8V, -Vee = -10.8V, V,H = 2V,
RL = 3 kn to 7 kn. (Figure 1J

I'H

High-Level Input Current

+Vee = 13_2V, -Vee =-13.2V, Data Input

-8

-5

V

1

10

IlA

2

20

IlA

-1

-1.6

rnA

-3.2

rnA

V, = 2.4V, (Figure 3J

I'L

Low-Level Input Current

+Vee = 13.2V,-Vee =-13.2V,
V, .: 2.4V, (Figure 3J

Strobe Input

+Vee = 13.2V, -Vee =-13_2V,

Data Input

-

V, = OAV. (Figure 3J
+Vee = 13_2V, -Vee =-13.2V,

Strobe Input

-2

Vo = 25V
Vo =-25V

-3

5
-6

15
-15

30
-30

mA
mA

10

22

mA

-1

-10

mA

8

17

mA

-9

-20

mA

V, = OAV, (Figure 3J
los

Short-Circuit Output Current

+Vee = 13_2V,'--Vee =-I3.2V,
(Figure 4J. Note 4

Vo = OV, V, - 3V
Vo = OV, V, - OV

+leeH
-l eeH

+leeL
-l eeL

Supply Current From +Vee,

+Vee = 13.2V,-V ee =-13.2V, V, =OV,

High-Level Output

RL = 3 kn, TA = 25°C, (Figure 5J

Supply Current From -Vee,

+Vee = 13.2V,-V ee =-13.2V, V, =OV,

High- Level Output

RL = 3 kn, TA = 25°C, (Figure 5J

Supply Current From +Vee,
Low- Level Output

+Vee = 13_2V, -Vee = -13.2V, V, = 3V,

Supply Current From -Vee,
Low- Level Output

+Vee = 13.2V, -Vee = -13.2V, V, = 3V,
RL = 3 kn, TA = 25°C. (Figure 5J

2

_mA
mA

RL = 3 kn, TA = 25°C, (Figure 5J

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Unless otherwise specified minimax limits apply across the O'C to +70°C range for the DS75150. All typical values are for TA = 25'C
and +VCC = 12V, -Vcc = -12V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted_
Note 5: The algebraic convention where the most·positive (least·negative) limit is designated as maximum is used in this data sheet for logic levels
only. e.g., when -SV is the maximum, the typical value is a more-negative voltage.

1-85

AC Electrical Characteristics

(+Vcc = 12V,-Vq ;.=-12V, TA = 25°C)

PARAMETER
tTLH

tTHL

t TLH ,

CONDITIONS

MIN

TYP

MAX

UNITS

0.2

1.4

2

J.Ls

0.2

1.5

2

J.Ls

Transition Time, Low-to-High

CL = 2500 pF, RL = 3 kn to 7 kn,

Level Output

(Figure 6)

Transition Time, High-to-Low
Level Output

CL = 2500 pF, RL = 3 kn to 7 kn,
(Figure 6)

Transition Time, Low·to-High

CL = 15 pF, RL = 7 kn, (Figure 6)

40

ns

CL =15pF, RL = 7 kn, (Fiigure 6)

20

ns

CL = 15 pF, RL = 7 kn, (Figure 6)

60

ns

CL = 15 pF, RL = 7 kn, (Figure 6)

45

ns

Level Output
tTHL

Transition Time, High-to-Low
Level Output

tnt'!

Propagation Delay Time,
Low·to·High Level Output

tpHL

Propagation Delay Time,
High·to·!-ow Level Output

DC Test Circuits
+Vcc

.v",

-v""

+Vcc

-Vee

t---~
.~
L_r_.J R,

~---~
'.~
L_J_.J ~R',

i

VI

v"

.

":"

l'

":"

~~f~t
SEE

NOTE

-,,;-

Vo,

-v",

OPEN

L_J_...J

':"

Note: When testing "H. the other Input 15 It JV; when testmg
IlL. the

EldainIWtisUItedseparltely.

I

.v",

3V

1~
L-r_.J~
':'"

FIGURE 3. IIH,IIL

.v'"

-Vee

I

l

other mputis open.

FIGURE 2. VIL, VOH

FIGURE 1. VII,!, VOL

-Vee

""",",,, i~ _~ _~i
Vo

.

-1"".-1",

"~
L_J_-.J ~3k

':"

IS tested for,bothmputcondltioftSltelchofthespecdled
output conditions.

'os

FIGURE 5. ICCH+' ICCH-, ICCL+, ICCL-

FIGURE 4. lOS

Typical Performance Characteristics

AC Test Circuit and
Switching Time Waveforms

l~;:~i!~R
I
ISEE NOTE lIJ

r

.v'"

-v""

Tl

L~1O"-j

~.

J- J

OH
Y

v o,
OUTPUT

10%

1.5V,

5~

I.5V

'",,'1~-3V

_

I--t~,

-b"

l' T
-=

20
OUTPUT

-----1 ",,:>o--"":+--oOPEN

5.5V

~c:.

_j

5V

Open

Open

Gnd

Open

Open
Pin 15

Open

Open

T and5V
Gnd

Open

-

-Vee:,

L

___

~

Open

12V

Open

Gnd

Pin 15
Pin 15

T

12V

T

Gnd

Pin 15

T

Open

Vee,

Vccz

(Pin 151

(Pin 16)

Open
Pin 15
Open

5.5V
5.5V
Open

Pin 15

T

Open
Open
13.2V
13.2V

T'

L

Vccz- R'l

>-----1 ::><>---....:..f--oOPEN
~
Vl(oP£NJ

Open
Open

0--013.2V

16

-

Open

FIGURE2. 'I

OPEN
15

VCC2

(Pin 16)

Open

Gnd

v,

vee1
(Pin 15)

_ _ _ -JI

FIGURE 3. VI(OPEN)

1-89

DC Test Circuits (Continued)

5.5VJt<:.
OPEN

Icc,

5t/

OPEN

Va:.

V= R'l

OPEN

_ _ l!L_ ....J!....L·

OPEN!

rT -

v

:>-----1

'V

Each autp.t is

15

Veer -

-J !

o--<)13.2V

Icca

16

~_-....:.+-OOPEN

FIGURE 5. ICC

FIGURE 4. lOS

AC Test Circuit and Switching Time Waveforms
5V

_

OUTPUT

Vee.

PULSE
GENERATOR
(NOTE I)

OPEN

, OPEN

VCC2

~

.l!&.....Ll

15_

R1 - ,

t

L

y

\ .....J
---I--~'-....

jiLL DIODES ARE IN30&4

~

":,.

INPUT

~~

CL "'5DpF
(NOTE 2)

5V----i~~--~~
OV ---:,,;,f1
-5V
VOH---~~I

OUTPUT
Vot.

----+4-==---..;::;:""'f

Nota 1: The pulst g8nar.tor his tbe following characteristics: loUT = son, tw '" 200 ns. duty cycle ~ 20%.
Note 2: CL incl..... probe and jig tlPlatloce

FIGURE 6.

Typical Performance Characteristics
Output Volta... VI
Inpilt Volt....

I

,.

-

f--

FAIL~AFE
OPERATION

I

(NOTE!)

vT-1

•

-3

-%

Vr '

-VT

NORMALJ.
i-OPEtATljN

-

-I

INPUT VOLTAGE (V)

1·90

L

L ___ ~ ___ .J

tIltI. separately.

INPUT

OPEN

VCC2-Rll

r-

~National

a

Transmission Line
Drivers/Receivers

Semiconductor

087820/058820 Dual Line Receiver
General Description
The 057820, specified from -5SoC to +12SoC, and
the 058820, specified from O°C to +70°C, are
digital line receivers with two completely independent units fabricated on a single silicon chip.
Intended for use with digital systems connected
by twisted pair lines, they have a differential input
designed to reject large common mode signals while
responding to small differential signals. The output
is directly compatible with TTL or L5 integrated
circuits.

• Each channel can be strobed independently
• High input resistance
• Fan out of two with TTL integrated circuits

The response time can be controlled with an ex·
ternal capacitor to eliminate noise spikes, and the
output state is determined for open inputs .. Ter·
mination resistors for the twisted pair line are
also included in the circuit. Both the 057820 and
the 058820 are specified, worst case, over their
full operating temperature range, for ±10·percent
supply voltage variations and over the entire input
voltage range.

Features
• Operation from a single +5V logic supply
• Input voltage range of ±lSV

Schematic and Connection Diagrams
Dual-In-Line Package
"fSPONSETlNE
CONTROL

"

RI'

'"
~

.."'
.,..U,

NGNINVERTING

.,

-~
RI
IX

TERMINATION

-

"

.11

~~.,

"

~"

w

. >-

.,

.U

RI

.."

,,,
Rl

...

'"

"

...1S.

.s

"

"
'15

"'

'"

..,"

'""'

.11

."

R1l

OUTPUT

"'"

TOPVUW

GROUND
R1

INVERtiNG
'N'UT

"

Order Number DS782OJ, DS8820J
or DS8820N
See NS Package J14A or N14A

RZ

'"
STROlE

Typical Application
Linl Drivulnd RICliver

1/2057130

TWISTED PAIR LINE

OUTPUT

tExaCI value depends on line length.
·Optionaltocontrol response time.

1-91

Absolute Maximum Ratings

Operating .Conditions

(Note 1)

)

Supply Voltage .
Input Voltage
Differential Input Voltage
Strobe Voltage
Output Sink Current

Supply Voltage (V CC)
DS7820
DS8820

8.0V
±20V
±20V
8.0V
25mA

Temp~rature

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70

°c
°c

(TA)

DS7820
058820

Maximum 'Power Dissipati~n* at 25°C

MIN

--65
0

Cavity Package
Molded Package

1308mW
1207mW
Storage ,Temperature Range
~5°C to +150°C
300°C
Lead Temperature (Soldering. 10 sec)
°Derate cavity package 8.7 mW/"C above 25°C; derate molded
package 9.7 mW/"C above 25°C.

Electrical Characteristics

(Notes 2 and 3)

PARAMETER
V TH

\

Input Threshold Voltage

CONDITIONS

MIN

TYP

V CM =0

-0.5

0

0.5

V

:-1.0

0

1.0

V

5.5

V

0.4

V

250

kn
kn
n

V OH

High Output Level

lOUT $0.2 mA

2.5

Low Output Level

ISINK $ 3.5 mA

0

R,-

Inverting Input Resistance

3.6

5.0

R, +

Non-Inverting Input Resistance

1.8

2.5

,

Line Termination Resistance

tr

Response Time

1ST

Strobe Cu rrent

TA = 25°C

120

\

170

COELAY = 0

40

ns

COELAY = 100 pF

150

ns

-1.0

VSTAOBE = 0.4V
VSTAOBE = 5.5V

Icc

I,N+

Power Supply C'urrent

Non·1 nverting Input Current

Inverting Input Current

3.2

Y'N = 15V

-1.4

mA

5.0

J.l.A

6.0

mA

Y'N =0

5.8

10.2

mA

Y'N = -15V

8.3

15.0

mA

Y'N = 15V

5.0

7.0

mA

Y'N =0
Y'N =-15V
I'N-

UNITS

-15V ~ V CM ~ 15V

VOL

RT

MAX

-1.6

-1.0

-9.8

-7.0

mA
mA

Y,N = 15V

3.0

4.2

mA

Y'N =0
Y,N =-15V

0
-3.0

-0.5

mA

-4.2

mA

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: These specifications apply for 4.5V :,; Vee:'; 5.5V, -15V :,; VCM :,; 15V and --65° C :,; TA :,; +125° C for the 057820 or 0° C :,; TA :,;
+70°C for the DS8820 unless otherwise specified; typical values given are for Vee = 5.0V, TA = 25°C and VCM = 0 unless stated differently.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.

Note 4: The specifications and curves given are for one side only. Therefore, the total package dissipation and supply currents will be double the
values given when both receivers are operated under identical conditions.

1·92

Typical Performance Characteristics
Supply Voltage Sensitivity

(Note 3)

0.3

~
w

'"

O.l

>

0.1

'"co~
~

>

~.o.t;; I ~~J
- "'t-- ollT""D411
. • lOUT =3.5;:;:: b
0.2

0.2

~

'"~ -0.1

'"
5-

;::::: _~Iollr'"'Z.5V I

I

~-D.4
co

;:;
4

4.5

5.5

-20

SUPPL Y VOLTAGE (VI

co

-l

~
;!; -4

\"" Cc..'IY .. 100 pF

'"

/"

w

~

o

...>
'"~

....

0.4
TIME (",I

0

w

110

./

i'"

170

./

" --

0:

160

I I
I I

-75 -50 -25

O.B

0.6

.,z

OUTPUT LOW- I - -

o
0.2

190

§

=5.0V

0.2
0.1

25 50

-75 -50 -25

300

........

Vee' 5.0V
OUTPUT LOW

vee = SV

.....

~

~1Ir"

........

~iO", - t-1"0.
Olll'pll,.
........
'
... '1

o

\

0.2

-O.l

DiffERENTIAL INPUT VOLTAGE (VI

I

'"
~
co

,Ii'

Termination Resistance

w

~

Cd."y=D,

~

~

I I

~

co

OUTP~T "IIG"

Vee' 5V
TA = 2SoC

w

'"'"~

...>

-0.4

lO

Output Voltage Levels

~

25°C -

l'-:~'

INPUT VOLTAGE (VI

Response Time

IZ5'C-

I"~

I
10

• !-'

rll

I

-10

~

55'C,

I

-0.3

, ...

~~

I I

-

ffi

-0.2

Vee =5V
'-fAN OUT' 2

0.4

~
;!;

;!

ffi

TA = 25°C

2:
w
'"
o~

...

~

:t

Transfer Function

Common Mode Rejection

20

·Transmission Line
Drivers/Receivers

~National

a

Semiconductor

DS7820AlDS8820A Dual Line Receiver
General Description
The DS7820A and the DS8820A are improved
performance digital line receivers with two completely independent units fabricated on a single
silicon chip_ Intended for use with digital systems
connected by twisted pair lines, they have a differential input designed to reject large common mode
signals while responding to small differential signals_ The output is directly compatible with TTL
or LS integrated circuits_ Some important design
features include:

• Fanout of ten with TTL integrated circuits
• Outputs can be wire OR'ed
• Series 54/74 compatible

The. response time can be controlled with an external capacitor to reject input noise spikes. The
·output state is a logic "1" for both inputs open.
Termination resistors for the twisted pair line are
also included in the circuit. Both the DS7820A
and the DS8820A are specified, worst case, over
their full operating temperature range (-55"e
to 125°C and aOe to 70°C respectively). over the
entire input voltage range, for ±10% supply voltage variations.

• Operation from a single +5V logic supply
•

Input voltage range of ±15V

• Strobe low forces output to "1" state
•

High input resistance

Schematic and Connection Diagrams

Dual-In-Line Package

RfSPDNSETIME
CONTROL

,-_+-,':::.3_ IIII'U1
'10

'"
~

RI.

50.

'"

.

RI.

."'

,-"
1I'IIIIPII1

~:: .~"N~"
-,...
.,., .

.... 010

".

"r

OJ

ftONINVERTING

INPUT
1'1

"

'QIf"'1

"

'10

TERMINATION

UURrAINATION

RI'

4.llk

"

,.

R4

OUTPUT

RI.

,."'

........

Note: Pin 7 connected to bottom of nVlty package.

Order Number DS7820AJ, DS8820AJ
or DS8820AN
See NS Package J14A or N14A

'1514•

Ii'

.,
INVERTING
INPut

I-I

50

RESPO'J$ETlME

U.

'13

•3

STROlE

GROl/ND

Ok

-

10

RZ

'"

Note: SChematic shows one-balf of unit.

Typical Applications

Single Ended (EIA-RS232CI Receiver with Hysteresis

Differential Line Driver and Receiver
CI

Ql,f

OUTPUT

IOUTPlIY'''I-FOR

OPEN INPUT)
Your

*OptlOnal to control respome time.

1·94

Absolute Maximum Ratings
Supply Voltage
Common·Mode Voltage
Differential Input Voltage
Strobe Voltage
Output Sink Current

Supply Voltage (V CC)
DS7820A
DS8820A

8.0V
±20V
±20V
8.0V
50mA
_65°C to 150°C

Storage Temperature Range
Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package
Lead Temperature (Soldering, 10 sec)

c
en

Operating Conditions

(Note 1)

Temperature (TAl
DS7820A
DS8820A

UNITS

MIN

MAX

4.5
4.75

5.5
5.25

V
V

+125
+70

°c
°c

-

-

'";::ffi

-0.4

6.0

~
is

~ou'

w

..
'"~
>

5
~

.

~

)n'- l-

--""~
-0.4

'"w
'"
'"
!1i'"

::l
a:

.'"

;::
z

'";;;
...ffi

r

-0.2

E
ffi
+10

,d:.-t
I

V~ = 5~

1'.
I "-

~fQ.s- _ _ ~
I
-20

-10

50

-2

~

-4

"..

200

i

..
a:

100

.......

.........

-20

"

Vee::: 5V

~

~

~'C

I'
'I

.
.
>

r- TO "0" OUTPUT

~

;::

"

3D

~is

26

i:i

22

......

....

I;

=).

..~

.'"
a:

....-:;
".

18
-75 -50 -25

0

DIFFERENTIAL
TO "1" OUTPUT

25
TA ('C)

50

0,2

20

10

~~'OU1~~
\.Olllt~\. \6 ..~
Ilo(

-75 -50 -25

0

75 100 125

In

I
50

75 100 125

Noise Rejection
Vee

/

ST~08i TO !'1" .lUTP~T- ~ I--

\/

22
18

25
TA C'C)

1000

w

1/

I
~
I
J..-I-"

0, 1

Ver5~
26

I

I

.

.-

5

''lIo: I:=' ~

3D

~
,..

20

I
LOGICAL "1" OUTPUT,
lou, • -400 "A - I--

~
0.3

Strobe Delays

./

r- DtIFFEkEN}IAL

i-- -

~
~

~.

-10

I

c- Vee = 5V

COMMON·MODE VOLTAGE (VI

I

38
34

10

-10

5

w

o

+20

+10

I

-10
-20

34

~

~:"INPUT

to

ut c~

~

Differential Input Delays
42

A

-6

Output Voltage Levels

\

~

iii

COMMON·MOOE VOLTAGE (V)

!,..

...... ~

INPUT VOLTAGE CWITH RESPECT TO GROUNDI (VI

l
JOUTPUT
cc =' 5.0v
LOW

~

,,"'"

.....

-INPUT.:::>

B

75 100 125

TA ('CI

3::

I

o

I

-8

oS

1'...

a:

/ / ' .....

I

ffi
a:

~

25

75 100 125

1. = 25°C

oS

160

0

50

r-~ee' 5V

.....

""

L
l""- I- ....

170

25
TA (OC)

Input Characteristics

./

180

_

TA = 25'C_

"iI,.

,Oill;oil"

-75 -50 -25

Internal Power Dissipation

~(O. _ _

.......

tt:

is

L

300

°ill>

.........

+20

,190

-75 -50 -25

0.4

0.2

.......

1-+",",,,,,,,+--+-t-+-1-1-1

i=
-150 L--'--'_-'-......_L--L..--''-.J

Power Supply Current

.........

.."'"

~

a:

DIFFERENTIAL INPUT VOLTAGE (V)

10

~

Termination Resistance

-55'C_

I I
I I

501-+-1---'

~

::l -50

COMMON·MODE VOLTAGE (V)

~\25'~ --.. :::.~

I I
I I
I I

to

= 16.:!,....,

O.4\1~r--

-10

-20

Transfer Function

~

w

'"

;i -100 1-+-1-+--'

SUPPLY VOLTAGE (V)

FANOUT = 10
Vee" S.OV
VCM '" OV

.§

......

-0.2

5.5

I--

\lou1' ""

-0.2

5.0

25°C

-4~~"~L
=t.~~,lo"'· ~

:::: I--

::l

-0.1

4.5

:::

Vee::: 5V

'"
i=

~
is

Temperature Sensitivity
100 ......::0-,-. ....,.......,,--.:::,-,

;;

5

::l

(Note 3 )

14

STROBE TO "0" OUTPUT

10
-75 -50 -25

0

25

50

TA rC)

1-96

75 100 125

/

§i
w

~

/'

V01FF =±2.SVPULSE

'"
:;
~

...... r<.

./

=5V

T. = 25'C

!

100

w

'"

is

'"x

'"'"

10
10

100

1~00

CRESPONSE TIME CONTROL

10,000
(pFI

AC Test Circuit and Waveforms

PULSE
GEN.

...-oSTROBE
-=
INPUT

PULSE
GEN.

1-----~

-'ncludes Jig and Probe

50
. t, =t,= 100s
PRR, I MHz

OIFF +Z.5V----:j r-_ _""

OV

INPUT
-Z.5V

STROBE
INPUT

OV

OUTPUT

A = Differential Input to "0" Output
B = Differential Input to "1" Output
C = Strobe Input to "0" Output
o = Strobe Input to "1" Output

FIGURE 1

1·97

~National

Transmission Line
Drivers/Receivers

a

Semiconductor
DS78C20/DS88C20

.

Dual CMOS Compatible Differential Line Receiver
General Description

Features

The OS78C20 and OS88C20 are high performance,
dual differential, CMOS compatible line receivers for
both balanced and unbalanced digital data transmission.
The inputs are· compatible with E IA and Federal
Standards.

• Meets requirements of EIA Standards RS·232·C
RS·422 and RS·423, and Federal Standards 1020 and
1030
• Input voltage range of ±15V (differential or common·
model
• Separate strobe input for each receiver
• 1/2 VCC strobe threshold for CMOS compatibility
• 5k typical input impedance
• 50 mV input hysteresis
• 200 mV input threshold
• Operation voltage range = 4.5V to 15V
• OS7830/0S8830 or MM78C30/MM88C30 recom·
mended driver

Input specifications meet or exceed those of the popular
OS7820/0S8820 line receiver, and the pinout is identical:
A response pin is provided for controlling sensitivity to
input noise· spikes with an external capacitor. Each
receiver includes a 180n terminating resistor, which may
be used optionally on twisted pair lines. The OS78C20
is specified over a -55°C to +125°C operating tempera·
ture range, and the DS88C20 over a O°C to +70°C range.

Connection Diagram

Dual·ln·Line paCkage
Vee
14

-INPUT

TERMI·

RESPONSE

-INPUT

NATION

+INPUT

STROBE

13

12

11

10

.INPUT

TERMI·
NATION

STROBE

RESPONSE

TIME

OUTPUT

OUTPUT

GNO

TIME

TOP VIEW

Typical Applications

Order Number DS78C20J, DS88C20J or DS88C20N
See NS Package J14A or N14A

RS-422/RS-423 Application

RS·232·e Application with Hysteresis

e,

Vee

O.OlpF
(NOTE 1)

Vee

Vee

0'

RI

LINE DRIVER AND RECEIVER (NOTE 31

OUTPUT

INPUT

STROBE

Note 1: (Optional internal termination resistor).
a) Capacitor in series with internal line termination resistor, terminates the
line and saves termination power. Exact value depends on line length.
bl Pin 1 connected to pin 2; terminates the line.
c) Pin 2 open; no internal line termination.
d) Transmission line may be terminated elsewhere or not at all.

Note 2: OPtional to control response time.
Note 3: Vec 4.5V to 15V for the DS78C20. For further information on line
. drivers and line receivers, refer to application notes AN·22, AN·83 and AN· lOB.

1·98

For signals which require fail·safe or have slow rise
and fall times, use Rl and 01 as shOwn above.
Otherwise, the positive inpuf (pin 3 or 11 i may be
connected to ground.
VOH

Vee

R1 ±5%

5V

4.3 k!1

10V

15 k!1

15V

24 k!1

(OUTPUT"
"i" FOR
OPEPtlINPUTI

ov

I.IV

V,.

2.&V

Absolute Maximum Ratings
Supply Voltage
Common.Mode Voltage

18V
±25V
±25V
18V
50 rnA

Differential Input Voltage

Strobe Voltage
Output Sink Current

Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package
Storage Temperature Range
Lead Temperature ISoldering, 10 seconds)

c

Operating Conditions

(Note 1)

Supply Voltage IV CC)

MAX

UNITS

4.5

15

V

o

"C
°c

S2

I\)

Temperature IT A)
DS7BC20
DSB8C20

-55
0

+125
+70

Common-Mode Voltage IVCM)

-15

+15

c

;o

V

1364 mW
1280 mW
-B5°C to +150"C
300"C

I\)

o

·Derate cavity package 9.1 mWrC above 2SoC; derate molded
package 10.2 mW/oC above 25°C.

Electrical Characteristics

(Notes 2 and 3)
CONDITIONS

PARAMETER
VTH

Differential Threshold Voltage

V

VOUT>VCC-1.2V

-15V ...-0 OUTPUT
SOpF*

tr = tf ::; 10 ns
PRR = 1 MHz

_

*Includes probe and jig capacitance

2.SV - - - - - - , , . - - - - - . .
DIFF
INPUT

-2.SV _ _ _- J

___ J

STROBE
INPUT

OV

OUTPUT

1·100

~National

a

Transmission Line
Drivers/Receivers

Semiconductor

0578301058830 Dual Differential Line Driver
General Description
The DS7830/DS8830 is a dual differential line
driver that also performs the dual four-input NAND
or dual four-input AND function.

normally associated with single-wire transmissions.

Features

TTL (Transistor-Transistor-Logic) multiple emitter
inputs allow this line driver to interface with
standard TTL systems. The differential outputs
are balanced and are designed to drive long lengths
of coaxial cable, strip line, or twisted pair transmission lines with characteristic impedances of
50n to 500n. The differential feature of the
output eliminates troublesome ground·loop errors

• Single 5 volt power supply
• Diode protected outputs for termination of
positive and negative voltage transients
•

Diode protected inputs to prevent line ringing

•

High speed

• Short circuit protection

Schematic'" and Connection Diagrams
r-----~~-_-..__,,,

Dual·ln-Line and Flat Pack aye

AND
OUTPUT

AND

NAND

OUTPUT

OUTPUT

NAND
OUTPUT

GND

TOPVIEW

Order Number DS7830J,
DS8830J or DS8830N
See NS Package J14A or N14A

*2 PER PACKAGE.

Typical Application
Digital Data Transmission

TWISTED PAIR LINE

OUTPUT

*Optlonal to control response time.

1·101

Absolute Maximum Ratings

.Operating Conditions

(Note 1)

Supply Voltage tv CCI
OS7830
OS8830

7.0V
5.5V
_65°C to +150°C
300°C

Vee
Input Voltage
Storage Temperature

Lead Temperature (Soldering. 10 secl
Output Short Circuit Ouration (125°CI

Temperature (TAl
OS7830
OS8830

1 second

Maximum Power Dissipation* at 25°C

MIN

MAX

4.5
4.75

5.5
5.25

V
V

+125
+70

°c
°c

--55
0

UNITS

130BmW
Molded Package
1207 mW
"Derate cavity package B.7 mW/oC above 25°C; derate molded
package 9.7 mWI"C above 2SOC:
Cavity Package

Electrical Characteristics

(Notes 2 and 3)

PARAMETER

CONDITIONS

V IH

Logical "1" Input Voltage

V IL

Logical

V OH

Logical "1" Output Voltage

Logical

VOL

IIH

IlL

V IN = 0.8V

"a" Output Voltage

V IN = 2.0V·

"a" I nput Current

lOUT = -0.8 mA

2.4

lOUT = 40 rnA

1.8

lOUT = 32 mA

V

lOUT = 40 mA

0.22

0.5

V

V IN = 2.4V

120

J1A

V IN = 5.5~

2

mA

-4.8

mA

-100

-120

mA

11

18

mA

-1.5

V

V IN = O.4V

Output Short Circuit Current

Vee = 5.0V, T A = 125°C, (Note 4)
V IN = 5.0V, (Each Driver)

VI

Input Clamp

Vee = Min; liN =·-12 mA
TA = 25°C, Vee = 5V, unless

PARAMETER
Propagation Delay AND Gate

Propagation Delay NAND Gate

tpdO
Differential Delay

-40

,-1.0

otherwis~ noted

CONDITIONS

tpdo

V
0.4

Supply Current

.11

V
3.3
0.2

Icc

tpdl

V

0.8

Ise

tpdl

UNITS
V

"a" I nput Voltage

Switching Characteristics

MAX

2.0

Logical "1" Input Current

Logical

TYP

MIN

MIN

TYP

MAX

UNITS

RL =400n, CL = 15 pF

8

12

ns

(Figure 1)

11

18

ns

RL = 400n, CL = 15 pF

8

12

ns

(Figure 1)

5

8

ns

Load, lOOn and 5000 pF,

12

16

lis

12

16

ns

(Figure 2)

Differential Delay

t2

Load, lOOn and 5000 pF,
(Figure 2)

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Unless otherwise specified min/lnax limits apply across the --55°C to +12SoC temperature range for the OS7830 and across the O°C to
+70°C range for the 088830. Typical values are for T A = 25°C and VCC = S.OV.
Note 3: All currents into device pins shown as pOSitive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.

Note 4: Only one output at a time should be shorted.

'."TSil

-

-.

~ I: . ..

$c,~

~

....

... .... ,~

.----

'N~TSH

v•
"D

§

SAM£LOAD

FIGURE 1.

5000,F

v,

DV

VA -v~

FIGURE 2.
1·102

51{"

Typical Performance Characteristics
Output High Voltage (Logical "'''1
Vs Output Curr~nt
4.0

~

3.0

w

'"'"

!::;
>

'"

....... r-...

'"

I
t--- ~125e
.......

]

1'~25

2.0

'"

;::
~

-55 C

1.0

o

15

~

'"" I

~

'"

~

'"

e

~ 2.0
w
1.8

20

>

:---

I-

5

Threshold Voltage Vs Tamperature

Differential Delav Vs Temperatura

10

.......

~

'"'"~

~

....

I-

>

~

~

E

20

40

60

~

i5

,....~

1.2

AN GATE ~

1.0

t·50 ·25 0 25 50 75 100 125

OUTPUT SOURCE CURRENT (mAl

~ANDrGATE

~I

I

I-

80 100 120 140

1. ' ''_

..... ~

:z:

II

o

1.6
1.4

I Lob'C!L
r- GU~R~NTJEO
INPUT VOLTAGE

TtNTEED
LDGIC~Tt
INPUT VOLTAGE

-50 -25 0 25 50 75 100 125
TEMPERATURE (OCI

TEMPERATURE (OCI

Differential Output Voltage
(IVAND - VNANDII

w

LOAD ".
SOH
LOr

-!l

,.

J25

:--...

55°C +125°C o~
25°C

200

~"

180

";::'"
:::

1/
II

160
140
100

'"

80

-55°el

",-. 10'

~

120

iii
i5

1\
\ I
50

J

v;

'"

20~"" f""'oo ~

IX

Vs Data Input Frequencv

!

t:"'N..
l7' ~ r-...
LD~~ I
loon

Output Low Voltage
(Logical "0"1 Vs Output Current

Power Dissipation (No Load)

VS Differential Output Current

25°

lb "'125'

~

75

100

r

J

0.12571.025710.020.05710

OUTPUT CURRENT (mAl

20

40 60

80 100 120 140

OUTPUT SINK CURRENT (rnA)

DATA INPUT FREDUENCY (MHz)

'AC Test Circuit
,---------------,
VtC I

,,

IIZOSJIlII/DSII3D

I

'.

I

,I
,

I

I

;>o-~'<>-,

I

"'-~'---

'.

Switching Time Waveforms

. ~) '"1,'l
ov

IV
~-~

f = 1 MHz
tr = tf $. '0 ns (10% to 90%1
Dutv cycle = 50%

1·103

.

~
~
c......o

CJ)

c
~
co

co
co

......

CJ)

c

~Nal:1onal

a

Transmission Line
DriverslReceivers

Semiconductor

057831/058831, 057832/058832

Dual TRI·5TATE® Line Driver
General Description

Mode of Operation

Through simple logic control, the DS7831/
DS8831, DS7832/DS8832 can be used as either
a quad single-ended Iine driver or a dual differential
line driver. They are specifically designed for
party line (bus-organized) systems. The DS7832/
DS8832 does not have the Vee clamp diodes
found on the DS7831/DS8831.

To operate as a quad single-ended line driver apply
logical "O"s to the Output Disable pins (to keep
the outputs in the normal low impedance mode)
and apply logical "O"'s to both Differential/
Single·ended Mode Control inputs. All four
channels will then operate independentlY and no
signal inversion wi II occur between inputs and
outputs.

The DS7831 and DS7832 are specified for operation over the -55°C to +125°C military temperature range. The DS8831 _and DS8832 are specified
for operation over the O°C to +70°C temperature
range.

To operate as a dual differential line driver apply
logical "0"5 to the Output Disable pins and apply
at" least one logical "1" to the Differential/Single·
ended Mode Control inputs. The inputs to the A
channels shou Id be connected together and the
inputs to the B channels-should be connected together.

Features
• Series 54/74 compatible
• 17 ns propagation delay
• Very low output impedance-high drive
capability
• 40 mA sink and source currents
• Gating control to allow either single·ended or
differential operation
• High impedance output state which allows
many outputs to be connected to a common
bus line.

In this mode the signals applied to the resulting
inputs will pass non·inverted on the A2 and 8 2 outputs and ,inverted on the A, and B, outputs.
When operating in a bus-organized system with
outputs tied directly to outputs of other
(continued)

Connection and Logic Diagram
Dual~ln-Line
"A"OUTPUT
OISASLE

OUTPUT
A2

Package

INPUT
A2

OUTPUT
A1

INPUT
Al

DifFERENTIAl!
SINGLE·ENDED
MODE CONTROL

Order Number DS7831J, OS8831J,
OS7832J, OS8832J, OS8831 N or OS8832N
See NS Package J16A or N16A

"8"OUTPU1

DISABlE

OUTPUT
8Z

INPUT
82

OUTPUT INPUTDIHERENTlALf GNO
81
81 SINGLE ENDED

MODE CONTROL

TOPVIEW

Truth Table

(Shown for A Channels Only)

"A" OUTPUT DISABLE

DIFFERENTIAL!
SINGLE·ENDED
MODE CONTROL

INPUT Al

OUTPUT Al

INPUT A2

logical "1" or

Same as
Input Al

Logical "1 m
Logical "0"

Same as
Input A2

Opposite of

Logical "1 or
Logical "0"

Input A2

Logical "0"

X
X
1
X

X

X

X

Logical "1" or
Logical "0"

X

Input Al
High
Impedance

state

X '" Don't Care

1-104

OUTPUT A2

Same as
High

X

impedance

state

J

Absolute Maximum Ratings
Supply Voltage
I~put Voltage
Output Voltage

Supply Voltage (V CC)
057831, 057832
058831 , 058832

7V
5.5V
5.5V
-65"C to +150"C

Storage Temperature Range

Temperature (T A)
057831, 057832
058831,058832

Time that 2 bus-connected devices may
be in opposite low impedance states
simultaneously
Maximum Power Dissipation* at 2SoC
Cavity Package
Molded Package

c

Operating Conditions

(Note 1)

00

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70

"C
"C

~5

a

1433mW
1362mW
300"C

Lead Temperature (Soldering, 10 sec.)

·Oerate cavity package 9.6 mWrC above 2SoC; derate molded
package 10.9 mW/"C above 25"C.

Electrical Characteristics

(Notes 2 and 3)

PARAMETER
Logical "1" Input Voltage

Vee = Min

V'L

Logical "0" Input Voltage

Vee

VOH

Logical "1" Output Voltage

= Min

10 = -40 rnA

1.8

10 =-2mA
10 = -40 rnA

2.4
1.8

10 =-5.2 mA

2.4

10 =40mA

057831, 057832
Vee = Min

058831, 058832

10 = 40 rnA

V

2.5

V
V

0.29

0.50

V
V

0.29

0.40
0.50

1

"L

Logical "0" "Input Current

Vee = Max, V'N = O.4V

100

Output Disable Current

Vee = Max, Vo = 2.4V or O.4V

-40

Ise

Output Short Circuit Current

Vee = Max, (Note 4)

-40

Supply Current

Vee = Max in TRI·5TATE

Input Diode Clamp Voltage

Vee = 5.0V, TA = 25"C, I'N = -12 rnA

VeLO

Output Diode Clamp Voltage

lOUT =-12 mA
lOUT = 12 rnA

V
mA

40

/lA

-1.0

-1.6

rnA

40

/lA

-100

-120

rnA

90

rnA

-1.5

V

058831,058832, V'N = 2.4V

Icc

V

0.40

057831, 057832, V'N = 5.5V

VeL!

V

2.9

10 = 32 rnA

"H

Vee = 5.0V,
TA = 25"C

V

2.3
2.7

10 - 32 rnA

Logical "1" Input Current

= Max

UNITS

0.8

057831, 057832

Vee

MAX

V

= Min

Vee

Logical "0" Output Voltage

TYP

2.0

058831, 058832
YOL

MIN

CONOITIONS

V'H

65

0578311058831

-1.5

057832/0S8832
057831/058831

V

V ee +1.5

V

Switching Characteristics T A = 25°C, Vee = 5V, unless otherwise noted
PARAMETER
tpdO

CONOITIONS

MIN

TYP

MAX

UNITS

13

25

ns

13

25

ns

6

12

ns

14

22

ns

14

22

ns

18

27

n,

Propagation Delay to a Logical "0"

from Inputs AI, A2, 81, 62
Differential Single-ended Mode
Control to Outputs

~Pd1

Propagation Delay to a Logical "1"

from Inputs AI, A2, 81, 62
Differential Single-ended Mode
Control to Outputs

t'H

Delay from Disable'lnput~ to ~igh.
Impedance State (from Logical "1"

RL = 400n, CL = 1'5 pF

See Figures 4 and- 5.

Level)
IoH

Delay from Disable Inputs to High
I mpedance State (from Logical "0"

Level)
tH'

Propagation Delay from Disable Inputs
to Logical "1" Level (from High
Impedance State)

tHO

Propagation Delay from Disable Inputs
to Logical "0" Level (from High
Impedance State)

1-105

en

~

CD
CD

...~

Notes
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of ·'Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for the OS7831 and 087832 and across
the oOe to +70o e range for~he OS8831 and OS8832. All typical values are for TA = 25"e and Vee = 5V.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Applies for TA = 125°e only. Only one output should be shorted at a time.

Mode of Operation

(Continued)

OS7831/0S8831 's, OS7832/0S8832's (Figure
1), all devices except one must be placed in the
"high impedance" state. This is accomplished by
ensuring that a logical "1" is applied to at least
one of the Output Disable pins of each device
which is to be in the "high impedance" state. A
NOR gate was purposely chosen for this function
since it is possible with only two OM 5442/
OM7442, BCO-to·decimal decoders, to decode as
many as 100 OS7831/0S8831 's, OS7832/
OS8832's (Figure 2).
The unique device whose Disable inputs receive
two logical "0" levels assumes the. normal low

impedance output state, providing good capacitive
drive capability and waveform integrity especially
during the transition from the logical "0" to
logical "1" state. The other outputs-in the high
impedance state-take only a small amount of
leakage current from the low impedance outputs.
Since the logical "1" output current from the
selected device is 100 times that of a conventional
Series 54174 device (40 mA vs. 400 IlA), the
output is easily able to supply that leakage current
for several hundred other OS7831 /OS8831 's,
OS7832/0S8832's and still have available drive
for the b.us line (Figure 3).

FOR DRIVING
OTHER
TTL INPUTS
BUS LINES

~

OUTPUTS
SelECTED AS

DRIVING DEVICE

SELECTED AS

DRIVING ---.
DEVICE

D 0
S S

8 8
8 8
J J
12

GATED INTO
HI IMPEDANCE
STATE

GATED INTD
THIRD STATE -

8 B
B B

J J
12

t-HHr--.

Figure 1

-

40/JA
LEAKAGE
CURRENT
PER CONN.

o
GATED INTO
HI IMPEDANCE
STATE

DD
S S

40mA

0
S S

8
8
J
1

8
8
J
2

Figure 3

Figure 2

1-106

40/JA

Typical Performance Characteristics
Propagation Delay from Input
to Output (Channel '1
30

J J JJ J

E

...~
....'"
z
;:
~

30

Vee' 5.OV
D1FFERENTIAL/S1NGLHNDED MIIDE
CONTROL INPUTS AT LOGICAL "0"

25
>-

Propagation Delay from Input
to Output (Channel '1

20
15

>-

-

I
'PdO

....~
..'"go
z

go

to

~

I

o
-15 -50 -25

0

25

30

J J. J J J

Vee' 5.0V
DIFFERENTIAL/SINGLHNOEO MODE
CONTROL INPUTS AT LOGICAL "I"

25

-

I

20
15

.......

i--'" i"""

Ipdl

~~

;:

tT '- r-- r--

10

!

Propagation Delay from Input
to Output (Channel 21

10

-

tpdo

=

0

25

30

>-

~
..

15

-

1/
>-

..

10

15

l- f- ~

10

--

0

25

i--'"
~

'H'

~

.
~

J

....

20

0

25

50 15

"-

10

100 125

Iii

IIIII

o

-15 -50 -25

IIIUW

10

100

1000

10.000

CL (pFI

Total Supply Current vs

Logical "'" Output Voltage vs

Frequency

Source Current

Logical "0" Output Voltage vs
Sink Current

Vee :'~:OV ''''''''
, """'T.'25°C
-1
ALL CHANNELS SWITCHIN~J

60

0.5

.....

VreT V

:---. ~

r--. ::::):

50

g

30

25'C

'

TEMPERATURE rCI

10

.s

40

z
;:

o

TEMPERATURE ('CI

Oi

>-

....

TA

50

~

go

50 15 100 125

~

15 100 125

Vee'" 5.0V

"H
o'---'--..J......-'---'----'-----'-I..-...J

50

60

~

I-"'"

25

Propagation De(ay vs Load
Capacitance

:g

J'HO

0

TEMPERATURE rCI

V: e ' 5~oV

20

~

~f-

-15 -50 -25

-15 -50 -25

15 100 125

25

.... ",

Ipd1

go

50

Vee'" S.OV

",

CO
CO
CO

10

Delay from Disable to Low
Impedance State

30

:......-IOH

z
;:

15 ~ i=- f-- tpdO

....~
...'"

TEMPERATURE ('CI

Delay from Disable to High
Impedance State

E

20

o

-15 -50 -25

TEMPERATURE ('CI

20

en
....,

>-

o

50 15 100 125

c

!

~

J

Ve~ '5~OV

25

t--,..!-25'C

,

~ 0.3

:--- ,.l..-55'C

40
125°C---..

30

,

20
10
.1

10

40

100

f(MHzl

lOUT

Vee = SV

.P

DS1BJ2

1

'~_55°C

-20

--25'cl

I

1\
160

20

OUTI'UTAI

_----I
DS1UI/

1

!

>-

.,~

15
10

-

OSI131

1

Ipd2

20

+-

51100pF

......
~

'IilPUTA2·

-

...t~
,

~
l

50
TEMPERATURE (OCI

1-107

.....-4 '.41 I--

':
DV
DV

100
VI-V:

IVI

DliTPUTA2

IJlfUT:

-4 ..."...-

-50
VOUT

80

lOUT (mA)

I

-2

&0

40

(mM

INI'U10-.....

J:I+-i- 125°C

-40

1~
~

25

_55°C__..

ii

~

:>

1/ ~

Vee' 5.oV

I
25'C~

Oi

0.1

tial Mode

Q

.s

0.2

i-

V ~ ~ '-- -55'C

~

30

1 OS1B31
lZS C------

+20

i-

'15.o

Propagation Delay in Oifferen·

lOUT vs VOUT High Impedance
Output State
..co

.. !

'7 ~~~ ~
I
V ~
moc_1I'"
... V I

0

120

80

.,

VJ"

:>

>

\

\
.01

0.4

~

100

Switching Time Waveforms

tpd1 8. tpdO

tOH

3V

,,
,I

INPUT
INPUT

IV

DV---oJ

-:".rI
I

I
I

'IVERTED
OUTPUT.

n

OUTPUT

ACTUAL
LOGICAL "U"
VOLTAGE

:

I
I
I

,. 1.5V

1

~'P.lt..­

I

I
I
I

NDNINVERTED

I

OUTPUT

I

I

3V

t1H

I
I
I

IN'UT

IV

t,.

OUTPUT

ACTUAL

Input characteristic:

LOGICAL .....

I

14-

:_1.

-l
'\j

VOLTAGE

Amplitude" 3.0V
Frequency" 1.0 MHz, 50% duty cycle
,I," It:::;; 10ns (10%10 90%)

o:15V

tH1

\~

INPUT
INPUT

DV

-l .. ,

DV

I
I

OUTPUT

I
I

OUTPUT

FIGURE4
SV

I"

AC Load Circuit

D'

OST832I
OSll32

r

e
,

SwltchS1

Switch 52

C,

,,-

closed

50 pF

tp"o

closed

closed

50 pF

t,.

"

"

....

• 5 pF

closed

'

...

• 5 pF

closed

50 pF

'

closed

50 pF

tp.'

',.

"

'.,
'.,

....

".....

...

·Jig capaCitance.

l

"
FIGURE 5

1-108

Transmission Line
Drivers/Receivers

~National

a

Semiconductor

DS78C120/DS88C120 Dual CMOS Compatible
Differential Line Receiver
General Description
The DS78C120 and OS88C120 are high performance,
dual differential, CMOS compatible line receivers for
both balanced and unbalanced digital data transmission.
The inputs are compatible with EIA, Federal and MIL
standards.

•
•
•
•

Functional Description

Input specifications meet or exceed those of the popular
OS7820/OS8820 line receiver.

The line receiver will discriminate a ±200 mV input
signal over a common-mode range of ± 1OV and a
±300 mV signal over a range of ±15V.

Features
•

Full compatibility with EIA Standards RS232-C,
RS422 and RS423, Federal Standards 1020, 1030
and MIL-188-114

•

Input voltage range of ±15V (differential or commonmode)

Circuit features include hysteresis and response control
for applications where controlled rise and fall times and/
or high frequency noise rejection are desirable. Threshold offset control is provided for fail-safe detection,
should the input be open or short. Each receiver includes
a 180n terminating resistor and the output gate contains a logic strobe for time discrimination. The
DS78C120 is specified over a -55°C to +125°C temperature range and the OS88C120 from O°C to +70°C.

• Separate strobe input for each receiver
•

1/2 VCC strobe threshold for CMOS compatibility

•

5k typical input impedance

50 mV input hysteresis
200 mV input threshold
Operation voltage range = 4.5V to 15V
Separate fai I-safe mode

Connection Diagram
Dual-In-Line Package
Vee

FAIL-SAFE
OFFSET -INPUT

16

15

,1

2

TERMINATION +INPUT

4

OFFSET -INPUT TERMIFAIL-SAFE
NATION

STROBE

RESPONSE
TIME OUTPUT

6

+INPUT STROBE RESPONSE OUTPUT
TIME
TOP VIEW

Order Number DS78C120J, DS88C120J
or DS88C120N
See NS Package J16A or N16A
1-109

8
GNO

Absolute Maximum Ratings

Operating Conditions

(Note 1)
18V

Supply Voltage
Input Voltage
Strobe Voltage
Output Sink Current
Maximum Power Dissipation* at 25°C
Cavity Package
.Molded Package
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)

Supply Voltage (VCC)

±25V
18V
SOmA
1433 mW
1362 mW
-ss'C to +150'C
300'C

MIN

MAX

UNITS

4.5

15

V
'c
'c

Temperature (T A)
DS78C120
DS88C120

-55
0

+125
+70

Common-Mode Voltage (VCM)

-15

+15

V

'Derate cavity package 9.6 mW/C above 25°C; derate molded
package 10.9 mW/C above 25°C.

Electrical Characteristics

(Notes 2 and 3)
CONDITIONS

PARAMETER
VTH

Differential Threshold Voltage

lOUT = -200 !-lA,
VOUT>VCC-l.2V

= 1.6 mA, VOUT:S; 0.5V

VTL

Differential Threshold Voltage

lOUT

VTH

Differential Threshold Voltage

lOUT = -200 !-lA,
VOUT

<: VCC -

MIN

-7V 12k

STROBE~

3

..)

"#

--'"
Q

10k
lk

,/

5k

~ 3.5k

~15k

14k

";;.c:

~ 3k ~ 10k

~

1

II
I J't.Y ~~r

(J)
~

0

:<
2-

~
~

5k

- 25

--0

1
FAIL-SAFE
OFFSET

1

I W

1

OUTPUT

t

J

56k

INVERTING~
INPUT

J. 120
':"

':"
NON·
_INVERTING

T
120
':"

':"

':"
':"

':"

':"

':"

':"

GNO

EINPUT
180
TERMINATION
RESISTOR

O~~88sa/O~~8lsa

AC Test Circuit and Switching Time Waveforms
Differential and Strobe Input Signal

OIFF.INPUT

JO-1HJ OUTPUT

OPEN
OPEN

*Includes probe and test fixture capacitance
2.5V -------I'---~
OIFF
INPUT
-2.5V _ _ _ _oJ

'"-----Ii

VCC
STROBE
INPUT
OV

OUTPUT

tr=tf~

lOn,S

PRR = 1 MHz
Note. Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection).

Application Hints

Balanced Data Transmission

1/2 MM18C30
LINE ORIVER
1/2 OS18C120
LINE RECEIVER

OUTPUT

Unbalanced Data Transmission
1/40S1488
OR 1/4 053691

OUTPUT

T
1-112

Application Hints

(Continued)
Logic Level Translator

VIL

VT

VIH

INPUT VOLTAGE

The DS78C120/DS88C120 may be used as a level translator to interface between ±12V MOS, ECl, TTL and CMOS. To configure,
bias either input to a voltage equal to 1/2 the voltage of the input signal, and the other input to the driving gate.

100

LINE DRIVERS

POSITIVE INPUT ~

Line drivers which will interface with the DS78C120/
DS88C120 are listed below.
10

Balanced Drivers
DS26LS31
MM87C30, MM88C30
DS7830, DS8830
DS7831, DS8831
DS7832, DS8832
DS1691, DS3691
DS1692, DS3692
DS3587, DS3487

V ~EGATIVE INPUT

Quad RS422 Line Driver
Dual CMOS
Dual TTL
Dual TRI-STATE® TTL
Dual TRI-STATE TTL
Quad RS423/Dual RS422 TTL
Quad RS423/Dual TRI-STATE
RS422TTL
Quad TRI-STATE RS422

/

0.1

10

lk

100

10k

RESPONSE CONTROL CAPACITOR (pF)

FIGURE 1. Noise Pulse Width vs Response
Control Capacitor

Unbalanced Drivers
DS1488
DS75150

Quad RS232
Dual RS232

RESPONSE CONTROL AND HYSTERESIS
OUTPUT

In unbalanced (RS232/RS423) applications it is
recommended that the rise time and fall time of the line
driver be controlled to reduce -cross-talk. Elimination
of switching noise is accomplished in the DS78C120/
DS88C120 by the 50 mV of hysteresis incorporated
in the output gate. This eliminates the oscillations which
may appear in a line receiver due to the input signal
slowly varying about the threshold level for extended
periods of time.

RESPONSE CONTROL
TCAPACITOR

NEGATIVE INPUT
NOISE PULSE

High frequency noise which is superimposed on the
input signal which may exceed 50 mV can be reduced
in amplitude by filtering the device input. On the
DS78C120/DS88C120, a high impedance response
control pin in the input amplifier is available to filter
the input signal without affecting the termination
impedance of the transmission line. Noise pulse width
rejection vs the value of the response control capacitor
is shown in Figures 1 and 2. This combination of filters
followed by hysteresis will optimize performance in a
worse case noise environment.

-t---I':::::=1

~:

Ir-..- -.....-t-I NOISE PULSE WIDTH
POSITIVE INPUT
NOISE PULSE

~I

-1---1

FIGURE 2
1-113

~~

Application Hints

(Continued)

TRANSMISSION LINE TERMINATION
On a transmission line which is electrically long, It IS
advisable to terminate the line in its characteristic
impedance to prevent signal reflection and its associated
noise/cross-talk. A 180n termination resistor is provided
in the DS78C120/DS88C120 line receiver. To use the
termination resistor, connect pins 2 and 3 together and
pins 13 and 14 together. The 180n resistor provides a
good compromise between line reflections, power dissipation in the driver, and IR drop in the transmission
line. If power dissipation and IR drop are still a concern,
a capacitor may be connected in series with the resistor
to minimize power loss.

input thresholds are offset from 200 mV to 700 mY,
referred to the non-,inverting input, or -200 mV to
-700 mV, referred to the inverting input. Therefore,
if the input is open or short, the input will be greater
than the input threshold and the receiver will remain in
a specified logic state.
The input circuit of the receiver consists of a 5k resistor
terminated to ground through 120n on both inputs.
This network acts as an attenuator, and permits operation with common-mode input voltages greater than
±15V. The offset control input is actually another input
to the attenuator, but its resistor value is 56k. The offset control input is connected to the inverting input
side of the attenuator, and the input voltage to the
amplifier is the sum of the inverting input plus 0.09
times the voltage on the offset control input. When the
offset control input is connected to 5V the input amplifier will see VIN(INVERTlNG) + O.45V or VIN(lNVERTI NG) + 0.9V when the control input is connected
to 1OV. The offset control input will not significantly
affect the differential performance of the receiver over
its common-mode operating range, and will not change
the input impedance balance of the receiver.

The value of the capacitor is recommended to be the' line
length (time) divided by 3 times the resistor value.
Example: if the transmission line is 1,000 feet long,
(approximately 1000 ns) the capacitor value should be
1852 pF'. For additional application details, refer to
application notes AN-22 and AN-l08 in the National
Semiconductor Interface Data Book.

FAIL-SAFE OPERATION
Communication systems require elements of a system to
detect the' presence of signals in the transmission lines,
and it is desirable to have the system shut-down in a
fail-safe mode if the transmission line is open or short. To
facilitate the detection of input opens or shorts, the
DS78C120/DS88C120 incorporates an input threshold
voltage offset. This feature will force the line receiver
to a specific logic state if presence of either fault is a
condition.

It is recommended that the receiver be terminated
(500n or less) to insure it will detect an open circuit in
the presence of noise.
The offset control can be used to insure fail-safe operation for unbalanced interface (RS423) or for balanced
interface (RS422) op'eration.
For unbalanced operation, the receiver would be in an
indeterminate 'logic state if the offset control input was
open. Connecting the offset to 5V offsets the receiver
threshold 0.45V. The output is forced to a logic zero
state if the input is open or short.

Given that the receiver input threshold is ±200 mY,
an input signal greater than ±200 mV insures the receiver
will be in a specific logic state. When the offset control
input (pins 1 and 15) is connected to VCC = 5V, the

Unbalanced RS423 and RS232 Fail-Safe
LINE RECEIVER
112 OS78CI20

5V

w
,co

-

~

Q

(OFFSET CONTROL
INPUT OPEN)

(OFFSET CONTROL
INPUT = 5vI

>

I-

:::>

I!:
:::>
Q

O.45V
INPUT VOLTAGE

INPUT VOLTAGE

1-114

Application Hints

(Continued)
Balanced RS422 Fail-Safe

BALANCED
LINE DRIVER

o
0-0

5Vo------------t--~

1J

co

..:;
w

w
co

..
I-

..

0

>

0

0

l-

~
=>

I-

I-

::=>

l-

:;

....0

>

>

...=>

=>

I0

'"
;;;:

-

-

=>

0

0
0

INPUT VOLTAGE

INPUT VOLTAGE

INPUT VD LTAGE

In a communications system, only the control signals
are required to detect input fault conditions. Advantages
of a balanced data transmission system over an unbal·
anced transmission system are:

For balanced operation with inputs short or open,
receiver C will be in an indeterminate logic state.
Receivers A and B will be in a logic zero state allowing
the NOR gate to detect the short or open condition.
The strobe will disable receivers A and B and may
therefore be used to sample the fail·safe detector.
Another method of fail·safe detection consists of filter·
ing the output of the NOR gate D so it would not
indicate a fault condition when receiver inputs pass
through the threshold region, generating an output
transient.

Truth Table

w
co

1. High noise immunity
2. High data ratio
3 Long line lengths

(For Balanced Fail-Safe)
INPUT

STROBE

A-OUT

0

1

1

1

X

B-OUT

C-OUT

D-OUT

0

1

0

0

1

0

1

0

1

0

0

X

1

0

0

1

1

0

0

1

0

1

1

0

0

X

0

1

1

0

0

1-115

'?A National
a Semiconductor

Transmission Line
Drivers/Receivers

DS78LS120/DS88LS120 Dual Differential
Line Receiver (Noise Filtering and Fail-Safe)
General Description
The DS78LS120 and DS88LS120 are high performance,
dual differential, TTL compatible line receivers for both
balanced and unbalanced digital data transmission. The
inputs are compatible with EIA, Federal and MIL
standards.

Input specifications meet or exceed those of the popular
OS7820/0S8820 line receiver.

Features

The line receiver will discriminate a ±200 mV input
signal over a common·mode range of ±10V and a
±300 mV signal over a range of±lSV.

•
•

Circuit features include hysteresis and response control
for applications where controlled rise and fall times and/
or high frequency noise rejection are desirable. Thres·
hold offset control is provided for fail·safe detection,
should the input be open or short. Each receiver includes
an optional 180n terminating resistor and the output gate
contains a logic strobe for time discrimination. The
OS78LS120 is specified over a -SSoC to +12SoC temper·
ature range and the OS88LS120 from oOe to +70o e.

•
•
•
•
•
•

Meets EIA Standards RS232·C, RS422 and RS423,
Federal Standards 1020,1030 and MIL·188·114
Input voltage range of ±lSV (differential or common·
model
Separate strobe input for each receiver
Sk typical input impedance
Optional 180n termination resistor
SO mV input hysteresis
200 mV input threshold
Separate fail·safe mode,

Connection Diagram
Oual·ln·Line Package
Vee

16

FAIL-SAFE
OFFSET -INPUT

TERMI·
NATION +INPUT

STROBE

RESPONSE
TIME OUTPUT

15

2
FAIL·SAFE -INPUT
OFFSET

3
TERMI·
NATION

4

5

6

7

+INPUT STROBE RESPONSE OUTPUT
TIME
TOP VIEW

Order Number DS78LS120J, DS88LS120J
or DS88LS120N
See NS Package J16A or N16A

1·116

8
GNO

Absolute !VIaximum Ratings
Supply Voltage
Input Voltage
Strobe Voltage
Output Sink Current
Storage Temperature Range

Operating Conditions

(Note 1)

MIN
4.5

Supply Voltage (VCC)
Temperature (T A)
DS78LS120
DS88LS120
Common·Mode Voltage (VCM)

7V
±25V
7V
50mA
-{;5'C to +150'C

Maximum Power Dissipation* at 25°C

MAX
5.5

UNITS
V

+125
+70
+15

DC
DC

TYP

MAX

UNITS

0.06
0.06
-o.OB
O.OB

0.2
0.3
0.2
0.3

V
V
V
V

0.47

0.7

V

-55
0
-15

V

Cavity Package
1433 mW
Molded Package
1362 mW
300'C
Lead Temperature (Soldering, 10 seconds)
'Derate cavity package 9.6 mWI'C above 25'C; derate molded
package 10.9 mWI'C above 25'C.

Electrical Characteristics

(Notes 2 and 3)

PARAMETER

MIN

CONDITIONS
: lOUT = - 4OO IlA,,vOUT;::2.5V

-7V< VCM< 7V
-15V < VCM < 15V
-7V<;'VCM<;'7V
-15V <;, VCM <;, 15V

VTH

Differential Threshold Voltage

VTL

Differential Threshold Voltage

lOUT = 4 rnA, VOUT <;, 0.5V

VTH

Differential Threshold Voltage

lOUT = -4001lA, VOUT<: 2.5V

-7V<;'VCM<;'7V

VTL

With Fail Safe Offset = 5V

lOUT = 4 rnA, VOUT <;, 0.5

-7V<;'VCM<;'7V

RIN

Input Resistance

-15V

RT

Line Termination Resistance

TA= 25'C

100

180

300

n

RO

Offset Control Resistance

TA = 25'C

42

56

70

kn

liND

Data Input Current (Unterminated)

VCM = lOV
VCM = OV
VCM - -10V

3.1
-0.5
-3.1

rnA
rnA
rnA

Input Balance

VTHB

<;, VCM <;, 15V, OV <;, VCC<;' 7V

-0.2
4

V
kn

5

2
0
-2

OV <;, VCC <;, 7V

lOUT = -400 IlA, VOUT <: 2.5V,
RS = 500n, (Note 5)
lOUT - 4 rnA, VOUT <;, 0.5V,
RS = soon, (Note 5)

-0.42

-7V

<;, VCM <;, 7V

0.1

0.4

V

-7V

<;, VCM <;, 7V

-0.1

-0.4

V

VOH

Logical "1" Output Voltage

IOUT=-400IlA, VDIFF= lV, VCC=4.5V

VOL

Logical "0" Output Voltage

lOUT = 4 mA, VDIFF = -lV, VCC = 4.5V

0.35

0.5

V

ICC

Power Supply Current

VCC= 5.5V,
VDIFF = -0.5V, (Both Receivers)

9

12
16

rnA.
rnA

100

Il A

-400

IIi>.

VCM= 15V
VCM=-15V

IIN(1I

Logical "1" Strobe Input Current

VSTROBE = 5.5V, VDIFF = 3V

IIN(O)

Logical "0" Strobe Input Current

VSTROBE =

VIH

Logical "1" Strobe Input Voltage

VOL <;, 0.5, lOUT = 4 rnA

VIL

Logical "0" Strobe Input Voltage

VOH <: 2.5V, lOUT = -4001lA

lOS

Output Short-Circuit Current

VOUT = OV, VCC = 5.5V, VSTROBE = OV, (Note 4)

Switching Characteristics

2.5

10
1

av, VDIFF = -3V

-290
2.0

V

3

1.12
1.12

V
O.B

V

-30

-100

-170

rnA

MIN

UNITS

VCC~5V,TA~25°C
TYP

MAX

tpdO(D)

Differential Input to "0" Output

38

60

ns

tpd1(D)

Differential Input to "1" Output

38

60

ns

tpdO(S)

Strobe Input to "0" Output

16

25

ns

tpd1(S)

Strobe Input to "1" Output

12

25

ns

PARAMETER

CONDITIONS

Response Pin Open, CL = 15 pF, RL = 2 kn

Note 1: t.\bsolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified min/max limits apply across the -5S'C to +125"C temperature range for the DS78LS120 and across the O'C to
+70' C for the DS8BLS120. All typical values are for T A = 25' C, VCC = 5V and VCM = OV.
Note 3: All currents into device pins shown as positive, out of device pins as negative.~all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Refer to EIA-RS422 for exact conditions.
II

1-117

DS78LS120J.DS88LS120

~
~

-n"
D)

RESPONSE
eONTR,OL

Vee

o

cZ"
;;

17k

25

3
18k

5k

•

VI/I,;

•

•

8k
10k

........
....

00

1.5k

":"
56k

5k

FAIL-SAFE~

NON-INVERTING

~INPUT

OFFSET
5k

INVERTING~

180

INPUT

120

120

TERMINATION
RESISTOR

0 OUTPUT

AC Test Circuit and Switching Time Waveforms
Differential and Strobe Input Signal
OUTPUT

INPUT
OPEN

*Includes probe and test fixture capacitance

2.SV

-------~---......

OIFF
INPUT

-2.SV

----.I

,------

....
=

:=

'"~
CI

(OFFSET CONTROL
INPUT OPEN)

(OFFSET CONTROL
INPUT· 5V)

>
....
=
:==
CI

=
CI

o
O.45V
INPUT VOLTAGE

INPUT VOLTAGE

1-121

Application Hints

(Continued)
Balanced RS422 Fail-Safe

BALANCED
_ LINE DRIVER

5V~----------~~~

...

...

...'"'"
...>
......
...
Of
C>

A

co

~

..!

C>

C>

::::>

::::>

::::>

...

...

::::>

::::>

...""==

>

>

==

C>

C>

C>
C>

-

INPUT VOLTAGE

INPUT VOLTAGE

For balanced operation with inputs short or open,
receiver C will be in an indeterminate logic state.
Receivers A and B will be in a logic zero state allowing
the NO R gate to detect the short or open condition.
The strobe will disable receivers A and B and may
therefore be used to sample the fail·safe detector.
Another method of fail-safe detection consists of filtering the output of the NOR gate D so it would not
indicate a fault condition when receiver inputs pass
through the threshold region, generating, an output
transient.

Truth Table

w

'"~

,..!

INPUT VOLTAGE

In a communications system, only the control signals
are required to detect input fault conditions. Advantages
of a balanced data transmission system over an unbal·
anced transmission system are:
1. High noise immunity
2. High data ratio
3 Long line lengths

(For Balanced Fail-Safe)
INPUT

STROBE

A-OUT

0

1

1

1
1

0
0
0

X
0
'1

X

B-OUT

C-OUT

O-OUT

0

1

0

1

1

0

0
0

1

1

1

1

1

1

0
0
10
0
0

1-122

X
0
0
0

»z

Integrated Circuits for
Digital Data Transmission

•

~

INTROI?UCTION

It is frequently necessary to transmit digital data
in a high'noise environment where ordinary inte·
grated logic circuits cannot be used because they
do not have sufficient noise immunity. One ~olu·
tion to this problem, of course, is to use high·
noise·immunity logic. In many cases, this approach
would require worst case logic swings of 30V,
requiring high power·supply voltages. Further,
considerable power would be needed to transmit
these voltage levels at high speed. This is especially
true if the lines must be terminated to eliminate
reflections, since practical transmission lines have a
low characteristic impedance.

DATA

DATA
INPUT

OUTPUT

GROUNDA
I. Sin!lle·Ended Svstem

INDUCED
NOISE
DATA
OUTPUT

DATA

INPUT

A much better solution is to convert the ground
referred digital data at the transmission end into a
differential signal and transmit this down a bal·
anced, twisted·pair line. At the receiving end, any
induced noise, or voltage due to ground· loop cur·
rents, appears equally on both ends of the
twisted·pair line. Hence, a receiver which responds
only to the differential signal from the line will
reject the undesired signals even with moderate
voltage swings from the transmitter.

V,

GROUND A
b. Differential S'{ltem

FIGURE 1. Comparing
Data Transmission

GROUND
NOISE

Differential

GROUND B

and Single·Ended

at the receiving end. Therefore, extremely high
noise immunities are not needed; and the trans·
mitter and receiver can be operated from the same
supplies as standard rntegrated logic circuits.

Figure 1 illustrates this situation more clearly.
When ground is used as a signal return as in Fig·
ure 1a, the voltage seen at the receiving end will be
the output voltage of the transmitter plus any
noise voltage induced in the signal line. Hence, the
noise immunity of the transmitter·receiver com·
bination must be equal to the maximum expected
noise from both sources.

This article describes the operation and use of a
line driver and line receiver for transmission sys·
tems using twisted·pair lines. The transmitter pro·
vides a buffered differential output from a DTL or
TTL input signal. A four·input gate is included on
the input so that the circuit can also perform logic.
The receiver detects a zero crossing in the differ·
ential input voltage and can directly drive DTL or
TTL integrated circuits at the receiving end. It also
has strobe capability to blank out unwanted input
signals. Both the transmitter and the receiver in·
corporate two independent units on a single silicon
chip.

The differential transmission scheme diagrammed
in Figure 1b solves this problem. Any ground noise
or voltage induced on the transmission lines will
appear equally on both inputs of the receiver. The
receiver responds only to the differential signal
coming out of the twisted·pair line and delivers a
single·ended output signal referred to the ground

1·123

~•

Z

!;

,I

f!:

1/

,

,I

>

!;

gross overload conditions. Figure 5 shows the
ability of the circuit to drive a differential load:
that is, the transmission line. It can be seen that
for output currents less than 35 mA, the output
resistance is approximately l5n. At both temperature extremes, the output falls off at high currents.
At 'high temperatures, this is caused by current
limiting of the high output state. At low temperatures: the falloff of current gain in the low·
state output transistor produces this result.

150

OUTPUT SINK CURRENT {mAl

FIGURE 4. Low-Stale Output Current as a Function of
Output Current

Figure 4 is a similar graph of the low-state output
characteristics. Here, the output resistance is about
5n with normal values of output current. With
larger currents, the output transistor is pulled out
of saturation; and the output voltage increases.
This is most pronounced at -55°C where the transistor current gain is the lowest. However, when
the output voltage rises about two diode drops
above ground, the collector-base junction of the
current-limit transistor becomes forward biased,

Load lines have been included on the figure to
show the differential output, with various load
resistances. The output swing can be read off from
the intersection of the output characteristic with
the load line. The figure shows that the driver can
easily handle load resistances greater than lOOn.

1·126

This is more than adequate for practical, twisted·
pair lines.

25

A
w

";::z

..
...":;:

Figu're 6 shows the no load power dissipation, for
one·half of the dual line driver, as a function of
frequency. This information is important for two
reasons. First, the increase in power dissipation at
high frequencies must be added to the excess
power dissipation caused by the load to determine
the total package dissipation. Second, and more
important, it is a measure of the "glitch" current
which flows from the positive supply to ground
through the output transistors when the circuit i~
going through a transition. If the output stage is
150

~

.

.5
z
;::

:;:
ill

125
100

.
~

,,~

15

Ci
a:

50

~

25

..;

-15 -50 -25

V

111-

10

15 100 125

To summarize the characteristics of the DS7830
line driver, the input interfaces directly with stand·
ard TTL circuits. It presents a load which is
equivalent to a fan out of 3 to the circuit driving
it, and it operates from the 5.0V, ± 10% logic
supplies. The output can drive low impedance lines
down to 50n and capacitive loads up to 5000 [IF.
The time skew between the outputs is minimized
to reduce radiation from the twisted·pair lines, and
the circuit is designed to clamp common mode
transients coupled into the line. Short circuit pro·
tection is also provided. The integrated circuit con·
sists of two independent drivers fabricated on a
41 x 53 mil·square die using the standard TTL
process. A photomicrograph of the chip is shown
in Figure 8.

5

1.0

50

FIGURE 7. Propagation Time as a Function of Tempera-

ONE SIDE

0.1

25

ture

n

~

0

TEMPERATURE (OCI

,,~

~

~

o

'/

/

L"..o'

10

~

g:

r-

'Ii

15

;::

II l W)· T
~q
- t "
~

I
V+'5V

20

100

SWITCHING FREQUENCY (MHz!

FIGURE 6. Power Dissipation as a Function of Switching

Frequency

not properly designed, the current spikes in the
power supplies can become quite large; and the
power dissipation can increase by as much as a
factor of five between 100 KHz and 10 MHz. The
figure shows that, with no capacitive loading, the
power increase with frequencies as high as 10M Hz
is almost negligible. However, with large capacitive
loads, more power is required.
The line receiver is designed to detect a zero cross·
ing in the differential output of the line driver.
Therefore, the propagation time of the driver is
measured as the time difference between the appli·
cation of a step input and the point where the
differential output voltage crosses zero. A plot of
the propagation time over temperature is shown in
Figure 7. This delay is added directly to the propa·
gation time of the transmission line and the delay
of the line receiver to determine the total data·
propagation time. However, in most cases, the
delay of the driver is small, even by comparison to
the uncertainties in the other delays.
'

FIGURE 8. Photomicrograph of the 057830 Dual Line

Driver

1·127

~•

Z



:0

Y+=5V
FANOUT=2

5S'C

2

po'"

I-b'J

flit,

co
I

'1 Ii i"-

0

-0.4

-0.2

-.....

2S'C

12S'C

I
I
I

0.2

0

0.4

DIFFERENTIAL INPUT VOLTAGE (VI

FIGURE 14. Voltage Transfer Function

-0.2

I--t--t--t--t--t--t--t--t

-0.3 L---'---'_-'---'---'_-'---'--,
4
4.5
5.5

SUPPLY VOLTAGE (VI

FIGURE 12. Differential Input Voltage Required for
High or Low Output as a Function of Supply Voltage

The transfer function of the circuit is given in
Figure 14. The loading is for a worst case fanout
of 2. The digital load is not linear, and this is
reflected as a non-linearity in the transfer function
which occurs with the output around 1.5V. These
transfer characteristics show that the only
significant effect of temperature is a reduction in
the positive swing at _55°C. However, the voltage
available remains well above the 2.5V required by
digital logic.

?:

....

4

~>

-2

w

Figure 13 is a similar plot for varying common
mode input voltage. Again the differential input
voltages are given for high and low states on the
output with a worst case fanout of 2. With
precisely matched components wi~hin the
integrated circuit, the threshold voltage will not

~to

2

!i~

0

.
..

w ...
~:o
~

Ci!!

~
w

to

!:;
co
>

-

.LCdeIIY=

4

,

3
I

0

100 pF

I

I

2

...
:0

r-

-4

I!:
:0
co

Vee = SV

T.=2S'C-

Cdll. , =0

0

02

0.4

0.6

0.8

TIME (psi

FIGURE 15. Response Time With and Without an External Delay Capacitor

-20

-10

10

20

INPUT VOL TAGE IVI

FIGURE 13. Differential Input Voltage Required for
High or Low Output as a Function of Common Mode Voltage

1-131

Figure 15 gives the response time, or propagation
delay, of the receiver. Normally, the delay through
the circuit is about 40 ns. As shown, th'e delay can
be increased, by the addition of a capacitor
between the response-time terminal and ground, to
make the device immune to fast noise spikes on
the input. The delay will generally be longer for
negative going outputs than for positive going
outputs.

10

Under normal conditions, the power dissipated in
the receiver is relatively low. However, with large
common mode input voltages, dissipation increases
markedly, as shown in Figure 16. This is of little
consequence with common mode transients, but
the increased dissipation must be taken into
account when there is a dc difference between the
grounds of the transmitter and the receiver. It is
important to note that Figure 16 gives the
dissipation for one half the dual receiver. The total
package dissipation will be twice the values given
when both sides· are operated under identical
conditions.

.......

.......

1
...... 10.1
~lPbl'

. I
1_
IV··5V ONESIOE-

~O~_r-r-

:-.

0b
l'...
I).bl'
........
-l'lq-l'
.......

......

I'..

.......

-Z

-zo

-10

0

10

ZO

INPUT VOL TAGE IV)

FIGURE 17. Power Supply Current as a Function of
Common Mode Input Voltage
300

iz
0

zoo

;::

I

1\

.~

tt

.iii"
~

I

100

f

""

'~

~

Z5"j('
:llZ5°C

T

"~

o
-ZO

The variation of the internal termination resistance
with temperature is illustrated in Figure 1B.Taking
into account the initial tolerance as well as the
change with temperature, the termination resis·
tance is by no means precise. Fortunately, in most
cases, the termination resistance can vary
appreciably without greatly affecting the charac·
teristics of the transmission line. If the resistor
tolerance is a problem, however, an external resis·
tor can be used in place of the one provided within
the integrated circuit.

v· =5.0V OUTPUT LOW
ONE SIDE

-10

10

ZO

INPUT VOLTAGE IV)

ZOO

FIGURE 16. Internal Power Dissipation as a Function of
Common Mode Input Voltage

190

..

~

§
u

z
c

In

.iii

Figure 17 shows that the power supply current
also changes with common mode input voltage due
to the current drawn out of or fed into the supply
through R9. The supply current reaches a
maximum with negative input voltages and can
actually reverse with large positive input voltages.
The figure also shows that the supply current with
the output switched into the low state is about
3 mA higher than with a high output.

180
170
160

"-

-- -

150
-15 -50 -Z5

0

~

Z5 50

15 100 lZ5

TEMPERATURE 1°C)

FIGURE 18. Variation of Termination Resistance With
Temperature

1·132

DATA TRANSMISSION

10

The interconnection of the OS7830 line driver
with the 057820 line receiver is shown in Figure 19. With the exception of the transmission
line, the design is rather straightforward_ Connections on the input of the driver and the output or
strobe of the receiver follow standard design ru les
for .oTL or TTL integrated logic circuits. The load
presented by the driver inputs is equal to 3 standard digital loads, while the receiver can drive a
worst·case fanout of 2. The load presented by the
receiver strobe is equal to one standard load.

UNTERMINATED

r\... V

2w

~~

'"'"

....
::'"

30m

..Ri

~

r--

150n
15n

>

~

~IJI'

-5

V'

-10
TIME (psI

FIGURE 20. Transmission Line Response With Various

The purpose of C 1 on the receiver is to provide dc
isolation of the termination resistor for the transmission line_ This capacitor can both increase the
differential noise immunity, by reducing attenuation on the line, and reduce power dissipation in
both the transmitter and receiver. In some applica. tions, C1 can be replaced with a short between
Pins 1 and 2, which connects the internal termination resistor of the OS7820 directly across the
line. C2 may be included, if necessary, to control
the response time of the receiver, making it
immune to noise spikes that may be. coupled differentially into the transmission lines.

Termination Resistances

The effect of termination mismatches on the transmission line is shown in Figure 20. The line was
constructed of a twisted pair of No. 22 copper
conductors with a characteristic impedance of
approximately 170n. The line length was about
150 ns and it was driven directly from a OS7830
line driver. The data shows that termination resistances which are a factor of two off the nominal
value· do not cause significant reflections on the
line. The lower termination resistors do, however,
increase the attenuation.

OUTPUT

tExactvalue depends on linelen.!lth.
tV+ is 4.5V to S.5V for bath the OS1820 31'd 051830.
"OptIonal to control response tIme.

FIGURE 19. Interconnection of the Line Driver and Line
Receiver

1-133

~

z

0"

«

Figure 21 gives the line-transmission characteristics
with various termination resistances when a dc
isolation capacitor is used. The line is identical to
that used in the previous example. It can be seen
that the transient response is nearly the same as a
dc terminated line_ The attenuation, on the other
hand, is considerably lower, being the same as an
unterminated line. An added advantage of using
the isolation capacitor is that the dc signal current
is blocked from the termination resistor which
reduces the average power drain of the driver and
the power dissipation in both the driver and
receiver.

The effect of different values of de isolation
capacitors is illustrated in Figure 22. This shows
that the RC time constant of the termination resistor/isolation capacitor combination should be 2 to
3 times the line delay_As before, this data was
taken for a 150 ns long line.
10
150n+200 pF

~/ /

..

150n +1100 pF

IR:~

~
~

I I

r--- 150n+4000 pF

~

c:t

..5
>

r-

c:t

10
300n +2000 pF

1'i1;~

-&

15Dn+20OO pF

...

~

Ih": ....

~

-10

r--..

~

15Sl +2000 pF

TIME Ipsl

c:t

..5
>

c:t

~

FIGURE 22. Response of Terminated Line With Different DC Isolation Capacitors

~~

-5

In Figure 23, the influence of a varying ground
voltage between the transmitter and the receiver-is
shown. The difference in the characteristics arises
because the, source resistance of the driver is not
constant under all conditiol)s. The high output of

-10

TIME (",I

FIGURE 21. Line Response for Various Termination
Resistances With a DC Isolation Capacitor
10

10

10

VCM =OV

f\.1a-

.

~

UNTERMINATED

~

c:t

..
5

I'rr~

-5

II"

c:t

>

r-5

U"

.L J..l

a. VCM = OV

TIME

15V

TI
150n

c:t

-5

I~sl

b_ VCM=-15V
FIGURE 23_ Line Response With Different Terminations
and Common Mode Input Voltages

1-134

•

IsDn +2000 pF

v ......

rr-

-

4

TIME(..,)

J.V CM

UNTERMINATED - -

-10

-10

-10

"-

~

('iii po;

n:; ~
~Iol"

~

150n

c:t

..
.
5

~

1\ 150n +2000 pF

>

c:t

5'"

~
c:t

150n +2000 pF

t-

'UNTERMINATED

N!

~

150n

>

l ......

.

~

I~~

~

1\

VCM " -15V

TIME(~sl

c. VCM-15V

l>
Z

~

the transmitter looks like an open circuit to, voltages reflected from the receiving end of the transmission Ii'ne which try to drive it higher than its
normal dc state. This condition exists until the
voltage at the transmitting end becomes high
enough to forward bias the clamp diode on the 5V
supply. Much of the phenomena which does not
follow simple transmission-line theory is caused by
this. For example, with an unterminated line, the
overshoot comes from the reflected signal charging
the line capacitance to where the clamp diodes are
forward biased. The overshoot then decays at a
rate determined by the total line capacitance and
the input resistance of the receiver.

ducts, giVing effects which are similar to those
described for the high output. However, a current
of about 9 mA is required to do this, so it does not
happen under normal operating conditions.
To summarize, the'best termination is an RC combination with a time constant approximately equal
to 3 times the transmission-line delay. Even
though its value is not precisely determined, the
internal termination resi~tor of the integrated circuit can be used because the line characteristics are
not greatly affected by the termi nation resistor.
The only place that an RC termination can cause
problems is when the data transmission rate
approaches the line delay and the attenuation'
down the line (terminated) is greater than 3 dB.
This would correspond to more than 1000 ft. of
twisted-pair cable with No. 22 copper conductors.
Under these conditions; the noise margin can disappear with low-duty-cycle signals. If this is the
case, it is best to operate the twisted-pair line with,out a termination to minimize transmission losses.
Reflections should not be a problem as they will
be absorbed by the line losses.

When'the ground on the receiver is 15V more
negative than the ground at the transmitting end,
the decay with an unterminated line is faster, as
shown in Figure 23b. This occurs because there is
more current from the input resistor of the
receiver to discharge the line capacitance. With a
terminated line, however, the transmission characteristics are the same as for equal ground voltages because the terminating resistor keeps the line
from getting charged.
Figure 23c gives the transmission characteristics
when the receiver ground is 15V more positive
than the transmitter ground. When the line is not
termi nated, the differential voltage swing is in:
creased because the high output of the driver will
be pulled against the clamp diodes by the common
mode input current of the receiver. With a dc isolation capacitor, the differential swing will reach this
same value with a time constant determined by the
isolation capacitor and the input resistance of the
receiver. With a dc coupled termination, the characteristics are unchanged because the differential
load current is large by comparison to the common mode current so that the output transistors
of the driver are always conducting.

CONCLUSION

A method of transmitting digital information in
high-noise environments has been described. The
technique is a much more attractive solution than
high-noise-immunity logic as it has lower power
consumption, provides more noise rejection, operates from standard 5V supplies, and is fu lIy compatible with almost all integrated logic circuits. An
additional advantage ,is that 'the circuits can be
fabricated with integrated circuit processes used
for standard logic circuits.

The low output of the driver can also be pulled
below ground to where the lower clamp diode con-

1-135

APPENDIX A
LINE RECEIVER
Design Analysis
The purpose of this appendix is to derive mathematical expressions describing the operation of the
line receiver. It will be shown that the performance of the circuit is not greatly affected by the
absolute value of the components within the integrated circuit or by the supply voltage. Instead, it
depends mostly on how well the various parts
match.

where V IN is the common mode input voltage and
R.IIR b denotes the parallel connectiori of the two
resistors. In Equation (A. 1), R8 = R9, R3 = R10,
R10« R11, R9» R10, R3« R11, R8»R3
and

R3
«3 so it can be reduced to
R4 +2R6+ R3
+
V+ - 3V BE - R1P
R9 V
IC1=
R10+R11+R3
(A. 2)
which shows that the collector current of Q1 is
not affected by the common mode voltage.

The analysis will assume that all the resistors are
well matched in ratio and that the transistors are
likewise matched .. since this is easily accomplished
over a broad temperature range with monolithic
construction. However, the effects of component
mismatching will be discussed where important.
Further, large transistor current gains will be
assumed, but it will be pointed out later that this
is valid for current gains greater than about 10.

The output voltage on the collector of 02 is
VC2 = V+ - IC2R12

A schematic diagram of the 0$7820 line receiver
is shown in Figure A-1. Referring to this circuit,
the collector current of the input transistor is
given by
V+ - V BEl - VBE3 - V BE4
ICl = R9/1 R10+ Rll + R3// R8
R3
R3/1 R11
R4 + 2R6 + R3 V BE 1 - R8 + R3// R 1 V IN
R9//R10+R11 +R3//R8
+
R10//Rl1
(VIN-V) R9+Rl011R11
(A.l)
+
R911 R10+ Rll + R3 II R8

+
VC2 =V -

R12 (v+ - 3V

_ Rl0 v+)
BE
R9
R10+Rll+R3
. (A. 4)

It is desired that this voltage be 3V BE so that the
output stage is just on the verge of switching with
zero input. Forcing this condition and solving for
R12 yields
V+ - 3V
R12=(Rl0+R11+R3) +
RB1EO +
V -3V BE -Rg V
(A. 5)
RESPONSE·TIME
CONTROL

r-------~._--~----~~~--------~----._---------v·

O.

.---....---l: DID

5k

"Ii
320
0'

08
81
170

:i---+---iC

. . .- -...._ - - - - - - - OUTPUT

5k

TERMINATIDN

"'

187

04

05

"

1k

(A. 3)

For zero differential input voltage, the collector
. currents of 01 and 02 will be equal so Equation
(A. 3) becomes

",.
750

...________+-____-+______...._--..------------- G"DUND

"'

167
STROBE

FIGURE A-1. Schematic Diagram of One Half
of the DS7820 Line Receiver

1-136

»
z
Finally, the threshold error due to finite gain in
the output stage can be considered. The collector
current of 07 from the bleeder resistor R 14, is
large by comparison to the base current of 08, if
08 has a reasonable current gain. Hence, the collector current of 07 does not change appreciably
when the output switches from a logic one to a
logic zero. This is even more true for 06, an
emitter follower which drives 07. Therefore, it is
safe to presume that 06 does not load the output
of the first-stage amplifier, because of the compounded current gain of the three transistors, and
that 08 is driven from a low resistance source.

This shows that the optimum value of R 12 is
dependent on supply voltage. For a 5V supply it
has a value of 4.7 kn. Substituting this and the
other component values into (A. 4),
V C2 = 2.83V SE + 0.081V+,

(A. 6)

which shows that the voltage on the collector of
02 will vary by about 80 mV for a lV change in
supply voltage.
The next step in the analysis is to obtain an
expression for the voltage gain of the input stage.

.,
5k

'
rA
Ik

~:1

R7
11r.

Ru

1~1E2

HI
1k

~....

I

A12

1

~VOUT

14.m

I

It follows that the gain of the output stage can be
determined from the change in the emitter-base
voltage of 08 required to swing the output from a
logic one state to a logic zero state. The expression
kT
IC1
,lVBE = q log. IC2

FIGURE A-2•. Equivalent Circuit Used to Calculate Input
Stage Gain

(A. 13)

An equivalent circuit of the input stage is given in
Figure A-2. Noting that R6 = R7 = R8 and
R2 ~ 0.1 (R6 + R7//R8), the change in the emitter
current of 01 for a change in input voltage is
0.9 R2
,lIE2= Rl (0.9 R2+ R E2 ) ,lV IN ·
(A. 7)

describes the change in emitter-base voltage required to vary the collector current from one
value, IC1' to a second, Ic2 . With the output of
the receiver in the low state, the collector current
of 08 is

Hence, the change in output voltage will be
,lV OUT = od E2 R12

IOL =

=

0.90: R2 R12
,l VIN .
Rl (0.9 R2 + R E2 )

Since 0: ~ 1, the voltage gain is
0.9 R2 R12
The emitter resistance of 02 is given by
kT
RE2 = qlC2 '
where
so

V+ - 3V BE
IC2=
R12
kTR12
R _
E2-:- q (V+-3V BE )

V+ - VOL - V BE9 - VBE10
R17

V BE9 V BES
VBE7
+ R15 - R14 + R13 + ISINK '

(A. 8)

(A. 14)

where VOL is the low state output voltage and
ISINK is the current load from the logic that the
receiver is driving. Noting that R13 = 2R14 and
figuring that all the emitter-base voltages are the
same, this beconies
V+--V OL -2V BE V BE
IOL =
R17
+ R15

(A. 9)

(A. 10)

(A.ll)

V BE
-2R14 + ISINK '

(A. 12)

(A. 15)

Similarly, with the output in the high state, the
collector current of 08 is

Therefore, at 25°C where V BE = 670 mV and
kT/q = 26 mV, the computed value for gain is
0.745. The gain is not greatly affected by temperature as the gain at -55°C where V BE = 810 mV
and kT/q = 18 mV is 0.774, and the gain at 125°C
where V BE =480 mV and kT/q = 34 mV is 0.730.

IOH =

v+ - VOH - V BE9 - VBE10
R17

V BE9
V BE8
+R15 - R14
V BE7
+ R13 - ISOURCE '

With a voltage gain of 0.75, the results of Equation (A. 6) show that the input referred threshold
voltage will change by 0.11 V for a 1V change in
supply voltage. With the standard ±10-percent
supplies used for logic circuits, this means that the
threshold voltage will change by less than ±60 mV.

(A. 16)

where V OH is the high-level output voltage and
ISOURCE is the current needed to supply the input
leakage of the digital circuits loading the
comparator.

1·137

~

~•

Z

Z•
......

o

CO

INTRODUCTION

Digital systems generally require the transmission of
digital signals to and from other elements of the system.
The component wavelengths of the digital signals will
usually be shorter than the electrical length of the cable
used to connect the subsystems together and, therefore,
the cables should be treated as a transmissions line. In
addition, the digital signal is usually exposed to hostile
electrical noise source which will require more noise
immunity then required in the individual subsystems
environment.

switching transients from actuating devices of neighbor·
ing control systems. Also external to a specific sub·
system, another subsystem may have a ground problem
which will induce noise on the system, as indicated in
Figure 2.

The requirements for transmission line techniques and
noise immunity are recognized by the designers of sub·
systems and systems, but the solution used vary con·
siderably. Two widely used example methods of the
solution are shown in Figure 1. The two methods
UNBALANCED METHOD
5V
INDUCED NOISE ALONG CABLE ROUTE
GROUND PROBLEMS IN ASSOCIATED EQUIPMENT

FIGURE 2. External Noise Sources

The signals in adjacent wires inside a cable may induce
electromagnetic noise on other wires in the cable. The
induced electromagnetic noise is worse when a line ter·
minated at one end of the cable is near to a driver at the
same end, as shown in Figure 3. Some noise may be

BALANCED METHOD

FIGURE 1.

illustrated use unbalanced and balanced circuit tech·
niques. This application note will delineate the char·
acteristics of digital signals in transmission lines and
characteristics of the line that effect the quality, and will
compare the unbalanced and balanced circuits perfor·
mance in digital systems.

CABLE

FIGURE 3. Internal Noise Sources

NOISE

induced from relay circuits which have very large tran·
sient voltage swings compared to the digital signals in the
same cable. Another source of induced noise is current
in the common ground wire or wires in the cable.

The cables used to transmit digital signals external to a
subsystem and in route between the subsystem, are
exposed to external electromagnetic noise caused by
1·139

~
,...

z•

«

DISTORTION
The obi.ective is the transm ission and recovery of digital
intelligence between subsystems, and to this end, the
characteristics of the data recovered must resemble the
data transmitted. In Figure 4 there is a 'difference in the
pulse width of the data and timing signal transmitted,
and the corresponding signal received. In addition there
is a further difference in the signal when the data is
"AND"ed with the timing signal. The distortion of the
signal occurred in the transmission line and in the line
driver and receiver.
TRANSMITTED
NRZ DATA

n

---1

\....-.--

TRANSMITTEOJUUlJUl
TIMING

The rise time in a transmission line is not an exponential
function but· a complementary error function. The high
frequency components of the step input are attenuated
and delayed more than the low frequency components.
This attenuation is inversely proportional to the frequency. Notice in Figure 6 particularly that the signal
takes much longer to reach its final dc value. This effect
is more significant for fast risetimes.
The Duty Cycle of the transmitted signal also causes
distortion. The effect is related to the signal rise time as
shown in Figure 7. The signal doesn't reach one logic
level before the signal changes to another level. If the
signal has a 1/2 (50%) Duty Cycle and the threshold of
the receiver is halfway between the logic levels, the distortion is small. But if the Duty Cycle is l/B as shown in
the second case the signal is considerably distorted. In
some cases, the signal may not reach the receiver threshold at all.

RECEIVED-D
DATA

'------

112.0UTVJUUlJUl

CYCLE DATA

RECEIVEOJWWL
TIMING

RECOVERED
DATA

----1ltf.______
.

112 DUTVCYCLE A
LINE RESPONSE'

~_

FIGURE 4. Effect of Distortion
1/8 DUTY
CYCLE DATA

A primary cause of distortion is the effect the transmis·
sion line has on the rise time of the transmitted data.
Figure 5 shows what happens to a voltage step from the
driver as it travels down the line. The rise time of the
signal increases as the signal travels down the line. This
effect will tend to affect the timing of the recovered
signal.
OFT

250FT

----

n

n

-.J L---.J L
/V
'<~
. . _____
-V-

1/8 DUTY CyclE \ .
LINE RESPONSE

T
H

FIGURE 7. Signal Distortion Due to Duty Cycle

In the previous example, it was assumed that the
threshold of the receiver was halfway between the ON E
and ZERO logic levels. If the receiver threshold isn't
halfway the receiver will contribute to the distortion of
the recovered signal. As shown in Figure 8, the pulse
time is lengthened or shortened, depending on the
polarity of the signal at the receiver. This is due to the
offset of the receiver threshold.
DRIVER

_ _ LINE IR DROP

r:--;;"-A-""""..
L
X V ~Vnt

V

INPUT
TIME

~

~...

L----....:..

---.J

'x ./\C-+

50
.
,.
\
RECEIVER
RECEIVER
THRESHOLD
INPUT - - -......~:--,f-.-"<-----"'---

FIGURE 6_ Signal Response at Receiver

~

-In

RECEIVER _ _ _ _
OUTPUT
__

l-etf/1

RECEIVER

OUTPUT

----,L

......... - O
POSITIVE PULSE

r----

__

..J NEGATIVE PULSE

FIGURE 8. Slicing Level Distortion

THE STEP RESPONSE OF A TRANSMISSION
LINE RESEMBLES A COMPLIMENTARY
ERROR FUNCTION RATHER THAN AN

UNBALANCED METHOD

EXPONENTIAL FUNCTION

Another source of distortion is caused by the IR losses
in the wire. Figure 9 shows the I R losses that occur in a
thousand feet of no. 22 AWG wire. Notice in this

TIME

FIGURE 6. Signal Rise Time

1-140

example that the losses reduce the signal below the
threshold of the receiver in the unbalanced method. Also
that part of the I R drop in the ground wire is common
to other circuits-this ground signal will appear as a
source of noise to the other unbalanced line receivers in
the system.

termination until it reaches its final dc value. In both the
rise and fall time diagrams, there are transient voltage
and current signals that subtract from the particular
signal and add to the system noise.
v

r---------,I
DM1400

I

1.2k

fZO

5.0V

LM75452·

3D
r-----,
I
~~I~~~~~~~

-=.1
I

I
I

IL-l
I

I

I
I

I

I

I
I

I

I

I

I

3D

f
L... _ _ _ _ _ _.....
_ -:-...
....;_ ....I
L ____...-:.J-,,~
.1/Ir~"-~---1-+-.':'
\,o.B3v l

t

FIGURE 11. Line Reflection Diagram of Rise Time

IA DROP SUBTRACTS
FROM NOISE MARGIN

IR DROP GENERATES
GROUND lOOP NOISE

FIGURE 9. Unbalanced Moth'od

Transmission lines ,don't necessarily have to be perfectly
terminated at both ends, (as will be shown later) but the
termination used in the unbalanced method will cause
additional distortion. Figure 10 shows the signal on the
transmission line at the driver and at the receiver. In this
case the receiver was terminated in 120n, but the characteristic impedance of the line is much less. Notice that
the wave forms have significant steps due to the
incorrect termination of the line_ The signal is subject to
misinterpretation by the line receiver during the period
of this signal transient because of the distortion caused
by Duty Cycle and attenuation. In addition, the noise
margin of the signal is reduced.

BALANCED METHOD

-

AT DRIVER

In the balanced method shown in Figure 13, the transient voltages and currents on the line are equal and

AT RECEIVER

100 FT TWISTED
PAIR SHIELDED

FIGURE 12. Line Reflection Diagram of Fall Time

DM1830
3D

2oo.s/DIV

I

----..J

170

FIGURE 10. LM75451, DM7400 Line Voltage Waveforms
3D

The signal waveforms on the transmission line can be
estimated before hand by a reflection diagram. Figure 11
shows the reflection diagram of the rise time wave
forms. The voltage versus current plot on left is used to
predict the transient rise time of the signal shown on the
right. The initial condition on the transmission line is an
IR drop across the line termination. The first transient
on the line traverses from this initial point to zero current. The path it follows corresponds to the characteristic impedance of the line_ The second transient on the
diagram is at the line termination. As shown, the signal
reflects back and 'forth until it reaches its final dc value.
Figure 12 shows the reflection diagram of the fall time.

Again the signal reflects back and forth between the line

1-141

1~

INPUT

30

BALANCED LINE SIGNAL

OUTPUT

THE GROUND lOOP CURRENT IS MUCH lESS THAN SIGNAL CURRENT

FIGURE 13. Cross Talk of Signals

opposite and cancel each others noise. Also unlike the
unbalanced method, they generate very little ground
noise. As a result, the balanced circuit doesn't contribute
to the noise pollution of its environment.

an unbalance reflection at the terminator. Therefore, the
lines should also be terminated for unbalanced 'signals.
Figure 16 shows the perfect termination configiJration
of a balanced transmission line. This termination method
is prim.arily required for accurate impedance measurements.

The circuit used for a line receiver in the balanced
method is a differential amplifier. Figure 14 shows a noise
transient induced equally on line A and line B from line
C. Because the signals' on line A and B are equal, the
signals are ignored by the differential line receiver. '
Likewise for the same reason, the differential signals on
line A and B from the driver will not induce transients on
line C. Thus, the balanced method doesn't generate noise
and also isn't susceptible to noise. On the other hand
the unbalanced method is more sensitive to noise and
also generates more noise.

BALANCED

R08=RxI/ ZR ou:: 90

, FIGURE 16. Impedance Measurement

MEASURED PERFORMANCE

....
SIGNAL ON LINEA

SIGNAL ON LINE.

The unbalanced method circuit used in this application
note up to this point is the unbalanced circuit shown in
Figure 1. The termination of its transmission line was
greater than the characteristic impedance of the unbal·
anced line and the circuit had considerable threshold
offset. The measured performance of the unbalanced circuit wasn't comparable to the balanced method. Therefore, for the following comparison of unbalanced and
balanced circuits, an improved termination shown in
Figure 17 will be used. This circuit terminates the line in
600 and minimized the receiver threshold offset.

~
~

DIFFERENCE SIGNAL lA-B) --~~-.....,'"V--

FIGURE 14. Cross Talk of Signals

5V

The characteristic impedance of the unbalanced transmission line is less than the impedance of the balanced
transmission line. In the unbalanced method there is
more capacitance and less inductance than in the balanced method. In the balance method the Reactance to
adjacent wires is almost cancelled (see Figure 15). As a
result a transmission line may have a 60n unbalanced
impedance and a gOn balanced impedance. This means
that the unbalanced method, which is more susceptible
to IR drop, must use a smaller value termination, which
will further increase the IR drop in the line.

----j'

r- b>

oOOO'A
0 0 0

FIGURE 17. Improved Unbalanced MethOd

A plot of the Absolute Maximum Data Rate versus cable
type is shown in Figure 18. The graph shows the dif·
ferent performances of the DM7820A line receiver and

UNBALANCED

138.

Zoco,x •

00000
0000
000
FIGURE 15.

vi<

§

1o,.

:i!

000

276
a
Zo :-109vi< b

100

'!.

E

00,00

SINGL~:ttttt

I0Io..TWISTED PAIR

~

t-

"
"
"
a:

00000
0000
000

t-

NINE "1'STED PAIR~

ID

Q

SINGLE TWISTED
PAIR SHIELDED

''""
'"
;(

"
't-"
::

Zo Unbalanced < Zo Balanced

ALL WIRE ;122
AWG STRANDED
DM7820A/DM7830
118 DUlY CYCLE

~

The inipedance measurement of an unbalance and balance
line must be made differently. The balanced impedance
must be measured with a balanced signal. If there is any
unbalance in the signal on the balanced line, there will be

fg

"

1.0
10

II

100

1000

LINE LENGTH (FT)

FIGURE 18. Data Rate vs Cable Type

1-142

Q

'"
:ii

Q

'"~

100

Q

isw

...
"
"...
"
:;

112 DUTY CYCLE

II:

Q

'"x
:;
"
...
::

.10

1=='=

100

100

1IB DUTY CYCLE
DM1B2oAlDM1BJo
NINE TWISTED PAIR
Zo BALANCED 9Ull

1Ij~IJ~yCY~

§

~

"

ABSOLUTE 1IB DUTY CYCLE
_MAXIMUM

:1i
<

'"'"

~I

T,

w

.55l

1111

1.0

::l

100

10

1__

----T,-I

1000

LINE LENGTH 1FT}

BIT RATE =

FIGURE 24. Data Rate YS Signal Cross Talk of
LM75452. DM7400

Figure 25 shows the test configuration of the balanced
circuit used to generate worst case Near End cross talk
NEAR END

'''~~~'m~[f

INTERVAL PER BIT

BAUD RATE '" MINIMUM

".2
T2

U~IT INTERVAL " ~

The data in this note was plotted versus Baud Rate.
The minimum unit interval reflected the worse case
conditions and also normalized the diagrams so that
the diagrams were independent of duty cycle. If the
duty cycle is 50% then the Baud Rate is twice the
Bit Rate.
REFERENCES
IC's for Digital Data Transmission, Widlar and Kubinec,
National Semiconductor Application Note AN-22.

1/2 DUTY CYCLE

Data Bus and Differential Line Drivers and Receivers,
Richard Percival: National Semiconductor Application
NoteAN-83.
RADC TR73-309, Experimental Analysis of the Transmission of Digital Signals over Twisted Pair Cable,
Hendrickson and Evanowski, Digital Communication
Section Communications and Navigation Division, Rome
Air Development Center, Griffis Air Force Base, New
York.

CABLE WITH

NINE TWISTED PAIR

Fast Pulse Techniques, Thad Dreher, E-H Research
Laboratories, Inc., The Electronic Engineer, Aug. 1969.
170

Transient Analysis of Coaxial Cables, Considering Skin
Effects, Wigingtom and Nahmaj, Proceedings of the IRE,
Feb. 1957.

\

8 NEAR END GENERATORS

Reflection and Crosstalk in Logic;Circuit Interconnections, John DeFalco, Honeywell, Inc., IEEE Spectrum,
July 1970.

FIGURE 25. Signal Cross Talk Experiment Using
DM7830, DM7820A

1-144

Transmission Line Drivers
and Receivers for EIA
Standards RS·422 and RS·423

National Semiconductor
Application Note 214
John Abbott
October 1978

With the advent of the microprocessor, logic designs
have become both sophisticated and modular in concept.
Frequently the modules making up the system are
very closely coupled on a single printed circuit board
or cardfile. In a majority of these cases a standard bus
transceiver will be adequate. However because of the
distributed intelligence ability of the microprocessor,
it is becoming common practice for the peripheral
circuits to be physically separated from the host pro·
cessor with data communications being handled over
cables (e.g. plant environmental control or security
system). And often these cables are measured in hun·
dreds or thousands of feet as opposed to inches on a
backplane. At this point the component wavelengths
of the digital signals may become shorter than the
electrical length of the cable and consequently must
be treated as transmission lines. Further, these signals
are exposed to electrical noise sources which may
require greater noise immunity than the single chassis
system.

Semiconductor's application note AN·1OB and E.I.A.
standards RS422 (balanced) and RS423 (unbalanced).
A summary review of these notes will show that the
controlling factors in a voltage digital interface are:

It is the object of this application note to underscore
the more important design requirements for balanced
and unbalanced transmission lines, and to show that
National's DS1691 driver and DS7BLS120 receiver
meet or exceed all of those requirements.

1) The cable length
2) The modulation rate
3) The characteristic of the interconnection cable
4) The rise time of the signal

RS·422 and RS423 contain several useful guidelines
relative to the choice of balanced circuits versus unbalanced circuits. Figures 1a and 1b are the digital
interface for balanced (1a) and unbalanced (1b) circuits.
Even though the unbalanced interface circuit is intended
for use at lower modulation rates than the balanced
circuit, its use is not recommended where the following
conditions exist:
1) The interconnecting cable is exposed to noise
sources which may cause a voltage sufficient
to indicate a change of binary state at the load.
2) It is necessary to minimize interference with
other signals, such as data versus clock.
3) The interconnecting cable is too long electrically
for unbalanced operation (Figure 2)

THE REQUIREMENTS
The requirements for transmission lines and noise
immunity have been adequately recognized by National

Ir

.I

CABLE
A' TERMINATIONiRECEIVER

CABLE

~c-=D~_
l--

r

lDADa

BALANCED
rDRIVER-I---INTERCONNECTlNG

:. 1,
V'RDUND

Legend:
R t = Optional cable termination resistance/receiver input impedance.

VGROUND = Ground potential difference
A, B = Driver interface

A', B' = Load interface

C = Driver circuit ground

.

C' = Load circuit ground

FIGURE 1a. RS422 Balanced Digital Interface Circuit

rr

UNBALANCED
ORIVER-r--INTERCONNECTING
CABLE

o

I.

,

A

SIGNAL CONDUCTOR

C

SIGNAL COMMON RETURN

B'

VGRDU.D_O::-C·_ _ _ _ _ _....

Legend:

Rt = Transmission line termination and/or receiver input impedance
VGROUND = Ground potential difference
A, C

= Driver interface

A', S' = Load interface

e = Driver circuit ground
C' = Load circuit ground

FIGURE 1b. RS423 Unbalanced Digital Interface Circuit
1-145

CABLE LENGTH
, While there is no ,maximum cable length specified,
guidelines are given with respect to conservative operating distances as a function of modulation rate. Figure
2 is a composite of the guidelines provided by RS-422 ,
'and RS-423 for data modulation versus cable length.
The data is for 24 AWG twisted pair cable terminated
for worst case (due to I R drop) in a 100 Ohm load,
with rise and fall times equal to or less than one half
unit interval at the applied modulation rate.

As pointed out in AN-lOa, the duty cycle of the transmitted signal contributes to the distortion. The effect
is the result of rise time. Due to delay and attenuation
caused by the cable, it is possible due to AC averaging
of the signal, to be unable to reach one binary level
before it is changed to another. If the duty cycle is
1/2 (50%) and the receiver threshold is midway between
logic levels, the distortion is small. However if the duty
cycle were l/a (12.5%) the signal would be considerably distorted.

The maximum cable length between driver and load
is a function of the baud rate. But it is influenced by:
CHARACTERISTICS

1) A maximum common noise range of ±7 volts
A) The amount of common-mode noise
Difference of driver and receiver ground potential plus driver offset voltage and coupled
peak random noise.
B) Ground potential differences between driver
and load.
e) Cable balance
Differential noise caused by imbalance between the signal conductor and the common
return (ground)
2) Cable termination
At rates above 200 kilobaud or where the rise
time is 4 times the one way propagation delay
time of the cable (RS-422 Sec 7.1.2)
3) Tolerable signal distortion'

Driver Unbalanced (RS-423)
The unbalanced driver characteristics as specified by
RS-423 Sec 4.1 are'as follows:

MODULATION RATE
Section 3 of RS-422 and RS-423 states that the unbalanced voltage interface will normally be utilized
on data, timing or control circuits where the modulation
rate on these circuits is below 100 kilolJauds, and balanced voltage digital interface on circuits up to 10
megabauds. The voltage digital interface devices meeting
the electrical characteristics of this standard need
not meet the entire modulation range specified. They
may be designed to operate over narrower ranges to
more economically satisfy specific applications,particularly at the lower modulation rates.

~

1) A driver circuit should be a low impedance (50
Ohms or less) unbalanced voltage source that
will produce a voltage applied to the interconnecting cable in the range of 4 volts to 6 volts.
2) With a test load of 450 Ohms connected between
the driver output terminal and the driver circuit
ground, the magnitude of the voltage (VT) measured between the driver output and the driver
circuit ground shall not be 'less than 90% of the
magnitude for either binary state.
3) During transitions of the driver output between
alternating binary states, the signal measured
across a 450 Ohm test load connected between
the driver output and circuit ground should be
such that the voltage monotonically changes
between 0.1 and 0.9 of VSS. Thereafter, the
signal shall not vary more than 10% of VSS
from the steady state value, until the next binary
transition occurs, and at no time shall the instantaneous magnitude of VT and VT exceed
6 volts, nor be less than 4 volts. VSS is defined
as the voltage difference between the 2 steady
state values of the driver output.

lk

::c

>to

,2

~

~ 100

...
INPUT

STROBE

RESPONSE
TIME OUTPUT

>INPUT STROBE RESPONSE OUTPUT
TIME
TOP VIEW

GNO

FIGURE 13. DS78LS120/DS88LS120 Dual Differential Line Receiver

INPUT

OUTPUT

RESPONSE
PIN

RESPONSE
CONTROL
NODE

STROBE

OUTPUT

FIGURE 14. Application of DS88LS120 Receiver Response Control and Hysteresis
lOOk

----,
:!
:c

NEGATIVE INPUT
NOISE PULSE

>- 10k

"
l:

I------t-

.
~

O.5V

0

----2V

w

!!l
~
w

U r-

lk

;;

POSITIVE INPUT
NOISE PULSE

n-

----1

NOISE PULSE WIOTH

L - -o.SV

RESPONSE CONTROL CAPACITOR loF)

FIGURE 15. Noise Pulse Width vs Response Control Capacitor

1-152

zv
0

FAIL-SAFE OPERATION
Communication systems require elements of a system
to detect the loss of signals in the transmission lines.
And it is desirable to have the system shut-down in a
fail-safe mode if the transmission line is open or short.
To facilitate the detection of input opens or shorts,
the DS78LS120/DS88LS120 incorporates an input
threshold voltage offset. This feature will force the
line receiver to a specific logic state if presence of
either fault condition exists.

It is recommended that the receiver be terminated
in 500 Ohms or less to insure it will detect an. open
circuit in the presence of noise.

The receiver input threshold is ±200 millivolts and an
input signal greater than ±200 mill ivolts insures the
receiver will be in a specific logic state. When the offset
control input is connected to a VCC = 5 volts, the
input thresholds are offset from 200 to 700 millivolts,
referred to the non·inverting input, or -200 to -700
millivolts, referred to the inverting input. Therefore,
if the input is open oOr short, the input will remain
in a specific state (See Figure 16).

For balanced operation with inputs short or open,
receiver C will be in an indeterminate logic state. Receivers A and B will be in a logic zero state allowing
the NOR gate to detect the short or open fault condition. The "strobe" input will disable the A and B
. receivers and therefore may be used to "sample" the
fail-safe detector (See Figure 17).

For unbalanced operation, the receiver would be in an
indeterminate logic state if the offset control input
was open. Connecting the offset to +5 volts, offsets
the receiver threshold 0.45 volts. The output is forced
to a logic zero state if the input is open or short.

DRIVER DS3691

5V

LI.I

'"~

-'

Q

(OFFSET CONTROL
INPUT OPEN)

(OFFSET CONTROL
INPUT = 5V)

>

I-

=
....
~o

Q

o

o

O.45V

INPUT VOLTAGE

INPUT VOLTAGE

FIGURE 16. Fail-Safe Using the DS88LS120 Threshold Offset for Unbalanced Lines

1-153

DRIVER OS3691
BALANCED LINE

) 0 - . ; . . . . - - - - - ~!~~VEO

FAULT

5V

STROBE

w

1J
INPUT VOLTAGE

...
""~

....
~
....
:::>

....>
....~:::>

w

!:;
0
>

0

>
.....
~
....
:::>
0

'"
';<

...«
w

""'"
!:;

-

INPUT VOLTAGE

0

..,

0

0
0

INPUT VOLTAGE

FIGURE 17. Fail·Safe Using the DS88LS120 Threshold Offset for Balanced Lines

1-154

Summary of Electrical
Characteristics of Some
Well Known Digital Interface
Standards

National Semiconductor
Application Note 216
Don Tarver
December 1978

FORWARD
Not the least of the problems associated with the design
or use of data processing equipment is the problem of
,providing for or, actually, interconnecting the differing
types and models of equipment to form specific proces:
sing systems.

standards because of the desire to provide/use equipment which interconnect to them.
Compliance with either the "official" or "defacto"
standards on the part of· equipment manufacturers is
voluntary. However, it is obvious that much can be
gained and little lost by providing equipment that offers
either the "official" or "defacto" standard I/O ports.

The magnitude of the problem becomes apparent when
one realizes that every aspect of the electrical, mechanical and architectural format must be specified. The most
common of the basic decisions confronting the engineer
include:

As can be imagined, the entire subject of interface in
data processing systems is complicated and confusing,
particularly to those not intimately involved in the dayto-day aspects of interface engineering or management.
However, at the component level the questions simplify
to knowing what standards apply and what circuits or
components are available to meet the standards.

• Type of logic (negative or positive)
• Threshold levels
• Noise immunity
• Form of transmission
• Balanced/unbalanced, terminated/unterminated
• Unidirectional/bidirectionai, simplex/multiplexed
• Type of transmission line
• Connector type and pin out
• Bit or byte oriented
• Baud rate

This application note summarizes the important electrical characteristics of the most commonly accepted
interface standards and offers recommendations on how
to use National Semiconductor integrated Circuits to
meet those standards.

If each make and/or model of equipment presented a
unique interface at its I/O ports, "interface" engineering
would become a major expenditure associated with the
use of data processing equipment.

1.0 INTRODUCTION
The interface standards covered in this application
note are listed in Table I. The body of the text
expands upon the scope and application of each
listed standard and summarizes important electrical
parameters.

Fortunately, this is not the case as various interested
or cognizant groups have analyzed specific recurring
interface areas and recommended "official" standards
around which common I/O ports could be structured.
Also, the I/O specifications of some equipment with
widespread popularity such as the IBM 360/370 computer and DEC minicomputer have become "defacto"

Table " summarizes the National Semiconductor
IC's applicable to each standard,

1-155

»
z

•
I\)
......
0')

....

CD
C\I

•
Z



~~.'~). .
~

OUT

~

v,

-:!:

2.2.2 EIA RS422, RS423
In a move to upgrade system capabilities
by utilizing state-of-the-art devices and

FIGURE 2. EIA RS423 Application

* Modulation

rate = reciprocal of minimum puls.width (i .•. ,
20 ms puis. = 50 baud)

1-158

»z
•

TABLE III. EIA RS232C SPECIFICATION SUMMARY
PARAMETER

CONDITIONS

VOH

Driver Output Voltage Open

VOL

Circuit

EIA RS232C
TYP

MAX

UNITS

25

V

-25

VOH

Driver Output Voltage Loaded

VOL

Output

RO

MIN

I\)
.....
0)

3 kn~ RL ~7 kn

V

5

Driver Output Resistance Power

V

15
-5

-15
-2V~ VO~ 2V

V

300

n

500

mA

OFF
lOS

Driver Output Short-Circuit

-500

Current
Driver Output Slew Rate
All Interchange Circuits

30

Control Circuits

I

Rate and Timing Circuits

RIN

Receiver Input Resistance

V/ms

6

V/ms

% of Unit Interval

4

3V ~ VIN ~ 25V

3000

%

-2

Receiver Open Circuit Input

V/fJ-s

6

7000

n

2

V

Bias Voltage
Receiver Input Threshold
Output; MAR K

-3

V

Output; SPACE

3

V

TABLE IV_ EIA RS423 SPECIFICATION SUMMARY
PARAMETER
Vo

CONDITIONS

Driver Unloaded Output Voltage

Vo
VT

Driver Loaded Output Voltage

lOS

EIA RS423
TYP

UNITS

MAX

4

6

V

-4

-6

V

3_6

RL; 450n

V

-3_6

VT
RS

MIN

Driver Output Resistance
Driver Output Short-Circuit

Va; OV

V
50

n

±150

mA

Current
Driver Output Rise and Fall

Baud Rate ~ 1k Baud.

Time

Baud Rate ~ 1k Baud

Driver Power OFF Current

VO; ±6V

±100

fJ-A

VTH

Receiver Sensitivity

VCM ~ ±7V

±200

mV

VCM

Receiver Common-Mode Range

RIN

Receiver Input Resistance

300

.,

fJ-S

% Unit

30

Interval
lOX

±1O

V

4000

n
±3

Receiver Common-Mode Input

V

Offset

.
1-159

co
,..
~

2.2.2.2 RS422

Z
o-__-+~

DATA

IN

INTERFACE

....

)

I

2k

DATA
OUT

-1V
1/4081691

1/4DS7Rl81Z0 .

FIGURE 4. MIL·STD·188C Application

TABLE VI. MIL·STD·188C SPECIFICATION SUMMARY

PARAMETER
VOH

MIL·STD·188C
LOW LEVEL LIMITS
TYP
MIN
MAX

CONDITIONS

Driver Output Voltage Open Circuit

RO

Driver Output Resistance Power ON

lOS

Driver Output Short·Circuit Current

5

7

V

-7

-5

V

(Note 1)

VOL

UNITS

lOUTS lOrnA
-100

100

n

100

rnA

Driver Output Slew Rate
All Interchange Circuits

(Note 2)

5

Receiver Input Resistance

Mod Rate S 200k Baud

6

Receiver Input Threshold
Output = MARK

(Note 3)

15

%IU

Control Circuits
Rate and Timing Circuits
RIN

100
-100

Output = SPACE

/lA
/lA

Note 1: Ripple <0.5%, VOH, VOL matched to within 10% of each other.
Note 2: Waveshaping required on driver output such that the signal rise or fall time is 5% to 15% of the unit interval at the applicable

tion rate.
Note 3: Balance between marking and spacing (threshold) currents actually required shall be within 10% of each other.

MILSTD 111 114
AL
........o:::-_t-<>-_ _T·_
:2'INTERFACE

FIGURE 5. MIL·STD:188.114 (Balanced Applications)
1·161

modula~

3.0 COMPUTER TO
STANDARDS

2.4.2 MIL·STD-188·114 Balanced
This standard is similar to RS422 with
the exception that the driver offset
voltage level is limited to ±0.4V vs ±3V
allowed in RS422.

PERIPHERAL

INTERFACE

To date, the only standards dealing with the interface between processors and other equipment are
the "defacto" standards in the form of specifications issued by IBM and DEC covering the models
360/370 I/O ports and the Unibus@, respectively.

2.4.3 MIL-STD-188-114 Unbalanced.

3.1 IBM specification GA-22-6974-0 covers the
electrical characteristics, the format of information and the control sequences of the data
transmitted between 360/370's and up to 10
I/O ports.

This standard is similar to RS423 with
the exception that loaded circuit driver
output voltage at R L = 450n must be
90% of the open circuit output voltage vs
±2V at RS = 100n for RS422.

the interface is an unbalanced bus using 95n,
terminated, coax cables. Devices connected to
the bus should feature short-circuit protection,
hysteresis in the receivers, and open-emitter
drivers. Careful attention should be paid to
line lengths and quality in order to limit cable
noise to less than 400 m V.

2.4.4 MIL·STD-1397 (Slow and Fastl
2.5 U.S. Government (non·military) standards
FED-STD·1020 and 1030 are identical without exception to EIA RS423 and RS422,
respectively.

TABLE VII. MIL-STD-1397 SPECIFICATION SUMMARY

PARAMETER

COMPARISON LIMITS
(MIL-STD)
1397
1397
(SLOW)
(FAST)

CONDITIONS

Data Transmission Rate

42

VOH
VOL

Driver Output Voltage

±1.5

10H
10L

Driver Output Current

RS

Driver Power OFF Impedance

VIH
VIL

Receiver Input Voltage

UNITS

250

k Bits/Sec
V

0

-10 to -15.5

-3

V

~-4

mA
mA

~100

Fail·Safe Open Circuit

r------,

kn

~4.5

~-1.1

~-7.5

~-1.9

V
V

r----------,

I
I

I

95 COAX CABLE

I
I

I
I

95

95

L _ _ '~S~ _ _ J

L ____

FIGURE 6. IBM 360/370 I/O Application

@Registered trademark of Digital Equipment Corp.

1·162

~S!!!!.

____ J

TABLE VIII. IBM 360/370 SPECIFICATION SUMMARY
PARAMETER
VOH

CONDITIONS

Driver Output Voltage

VOH

IOH = 59,3 mA

VOL

IOL = -240p.A
Receiver Input Threshold
Voltage

IIH

Receiver Input Current

MAX

=30p.A

IOH

VIH

IBM 360/370
TYP

IOH = 123 mA

VOH

VIL

MIN

7

v

5.85

V

3.11

V
0.15

V

1.7

V
V

0.7
VIN

= 3,11V

-0.42
0.24

VIN = 0.15V

IlL

UNITS

mA
mA

Receiver Input Voltage
Range
Power ON

-0.15

7

Power OFF

-0.15

6

Rece'iver Input Impedance

0.15V ~ VIN ~ 3.9V

Reaeiver Input Current

VIN = 0.15V

PD ~390 mW

CABLE Termination

n

7400

CABLE Impedance

V
V

240

p.A

83

101

90

100

n
n

400

mV

Line Length (Specified as
Noise on Signal and Ground Lines)

.v

~~ 1~~ I" 1~~·I ~i:.
FIGURE 7. DEC Unibus® Application

TABLE IX. DEC UNIBUS ® SPECIFICATION SUMMARY
PARAMETER
VOL

Driver Output Voltage

Vo
VIH

CONDITIONS

DECUNIBUS®
TYF'

MAX

IOl = 50mA

0.7

V

7

V

Receiver Input Voltage

1.7

V

1.3
Receiver Input Current

III

UNITS

Absolute Maximum

VIL
IIH

MIN

V

V.lN = 4V

100

p.A

VIN = 4V Power OFF

100

p.A

3.2 DEC Unibus®
Another example of an unofficial industry
standard is the interface to a number of DEC
minicomputers. This interface, configured as a
120n double-terminated data bus is given the
®Registered trademark of Digital Equipment Corp.

1-163

name Unibus®. Devices connected to the bus
should feature hysteresis in the receivers and
open·collect!>r driver outputs. Cable noise
should be held to less than 600 mV.

4.0 INSTRUMENTATION TO COMPUTER INTERFACE STANDARDS
b)

4.1 Introduction
The problem of linking instrumentation to processors to handle real-time test and measure·
ment problems was largely a custom interface
problem. Each combination of instruments
demanded unique interfaces, thus inhibiting the
wide spread usage of small processors to day-today test, measurement and control applications.

4.2 IEEE 488
IEEE 488 covers the functional, mechanical
and electrical interface between laboratory
instrumentation (Le., signal generators, DPM's,
counters, etc.) and processors such as program·
mabie calculators and minicomputers. Equipment with IEEE 488 I/O ports can be readily
daisy chained in any combination of up to 15
equipments (including processor) spanning distances of up to 60 feet. 16 lines (3 handshake,
5 control and 8 data lines) are required.

Two groups addressed the problem for specific
environments. The results are:
a)

The CAMAC system pioneered by the
nuclear physics community.

IEEE 488 bus standard based upon
proposals made by HP, and

+-__+--+-......._---~~:,~"-'-_+_+-.....--.---_+

16 LINES

",-,-

"
~
DEFINED:
5V

3k
IN ....---4.......-.0UT

16 LINES } -

:~ 6.Zk

1

PORTA

515 PORTS

~~

I'

PORT"N"

~GNO

FIGURE 8. IEEE 488 Application
TABLE X. IEEE 488 SPECIFICATION SUMMARY
PARAMETER
VOH

Driver Output Voltage

CONDITIONS

MIN

MAX

UNITS
V

2.4

10H = -5.2 mA
10L = 48 mA

VOL

IEEE 488
TVP

0.4

V

±40

IlA

Driver Output Current
10Z

TRI-STATE®

Vo = 2.4V

10H

Open Collector

Vo = 5.25V

VIH

Receiver Input Voltage

250

O.4V Hysteresis Recommended

2.0

IIH

Receiver Input Current

IlL

RLl
RL2

V
0.8

VIL

IlA

V

VIN = 2.4V

40

VIN = O.4V

-1.6

IlA
mA

12

mA

Receiver Clamp Current

VIN = -1.5V

Termination Resistor

VCC = 5V (±5%)

2850

3150

V= Gnd

5890

6510

1-164

a)·

4.3 CAMAC
The CAMAC system is the result of efforts by
those in the nuclear physics community to
standardize the interface between laboratory
instruments and computers before the introduc·
tion of IEEE 488.

l>
Z•

.....

I\)

Minimal system: for data transfer over
short distances (usually on 1 PC board),
and,

b)

en

Expanded system: for data transfer to
extend the memory or computational
capabilities of the system.

5.2 Minimal Systems and Microbus1M
It allows either serial or parallel interconnection
of instruments via a "crate" controller.

Microbus™ considers the interface between
MaS/LSI microprocessors and interfacing
devices in close physical proximity which communicate over 8-bit parallel unified bus systems.
It specifies both the functional and electrical
characteristics of the interface and is modeled
after the 8060, 8080 and 8900 families of
microprocessors as shown in Figures 8, 9 and
10.

The electrical requirements of the interfaces
are compatible with DTL and TTL logic levels.
5.0 MICROPROCESSOR
STANDARDS

SYSTEMS

INTERFACE

5.1 Microprocessor systems are bus organized
systems with two types of bus requirements:

The electrical characteristics of Microbus are
shown in Table XI.

TABLE XI. MICROBUS ELECTRICAL SPECIFICATION SUMMARY

VOL

VIL
VIH

UNITS

~0.4V

Output Voltage (At 1.6 mAl

~2.4V

(At -100/lA)

VOH

RECEIVER
HYSTERESIS
STANDARD
(RECOMMENDED)

DRIVER

PARAMETER

Input Voltage

0.8

0.6

2.0

2.0

V
V

10

10

pF

Internal Capacitive Load at 25°C

15

tr

Rise Time (Maximum)

100

ns

!f

Fall Time (Maximum)

100

ns

MICROBUS

H
~J2
I

CHIP SELECT
LOGIC

r-----~
A11-AO

~~ :

""C

:

~

t-___.....;.A~15io;-:'AO'-----1I1

5r
LATCH

NAOS

1'r--

A
OB)-OBO

I

,

r

I
~

r
5V

8060

NROS

t- - -....-+--:ii1i:;.-_.r
_____

~t-

~_~W~R~~

FIGURE 9. 8060 SC/MP II System Model
1·165

co
,...
:Z
N

MICROBUS

40k-

q
,

OV-7V
<10k

**

r-"
REVERSE CHANNEL MODEM

**

,

RCS

11

REVERSE CHANNEL SEND

RCR

12

REVERSE CHANNEL RECEIVE

SI

17

SYNC IN

SO

18

SYNC OUT

~ 3k-7k

'*

"'.J:-

• .J:.

**
2.5 Vrms-

SYNC MODEM

..

....

18.0V~s

'V

-! ~k-7k
..... 1

~ 3k-7k

-=-te
":'"

AA

2.5 Vrms18Vrms

COMMUNICATIONS
CONTROL
CIRCUITRY

CLOSES
WHENEVER:
RINGING IS
DETECTED

*

~

~ >40k

RR

19

REMOTE RELEASE

RC

20

REMOTE CONTROL

RY

21

READY

RI·l

22

RING INDICATOR 1

RI·2

23

RING INDICATOR 2

'*

*

FEMALE MALE
CONNECTOR

OPENTO
• - TERMINATE
CALL

, , CLOSE FOR
~ ~ AUTO ANSWER

* Must be closed or Data Set cannot be placed
** Receive Sensitivity
ON
OFF

3V-25V
3V-25V

In

data mode

Source
5V-25V
5V-25V

FIGURE 12. Functional and Electrical Characteristics of RS357
6.3 EIA RS4~
RS408 recommends the standardization of the
2 interfaces shown in Figure 13.

VOL:::; 0.4V at IOL = 48 mA
VOH:;:: 2.4V at IOH:::; -1.2 mA, and
. CL :::;2000 pF.

The' electrical characteristics of NeE to DTE
interface are,. in summary, those of conven·
tional TTL drivers (series 7400) with:

Short circuit protection should be provided.
1-168

»
z
•
......

N

0)

SWITCHED OR DEDICATED,
COMMON CARRIER, OR
PRIVATE LINE TO DATA
SOURCE/SINK

(TYPICALLY A MODEM
IF INCLUDED IN
SYSTEM)

DATA
CDMMUNICATlDNS
EQUIPMENT

-

-

-INTERFACE DEFINED BY RS232C

(TYPICALLY INCLUDES
SERIAL TD PARALLEL
CDNVERTER, ETC.)

DATA
TERMINAL
EQUIPMENT (DTE)
TYPICALL Y - INTERFACE DEFINED BY THIS STANDARD
<40 FEET

(TYPICALLY COULD
INCLUDE A SWITCH TO
SELECT EITHER LOCAL
TAPE READER OR DATA
TERMINAL EQUIPMENT)

NUMERICAL CDNTROL
EQUIPMENT (NCE)

(TYPICALLY A MACHINE
TOOL, DRAFTING TABLE,
ETC.)

CONTRDLLED
EQUIPMENT

FIGURE 13. EIA RS408 Interface Applications

1-169

Section 2

Bus Transceivers

TEMPERATURE RANGE
- 55°C to

+ 125°C

*OP7303
*OP7304B
*OP7307
*OP7308
*OS26S10M
*OS26S11M

*OS7640
*OS7641
*OS7833
*OS7834
*OS7835
*OS7836
*OS7837
*OS7838
*OS7839
OS8T26AM
*OS8T28M
OM54S240
OM54S241

DOC to

+ 70°C

OP8303
OP8304B
OP8307
OP8308
OS26S10
OS26S11.
OS3662
AN-259
AN-337
OS3666
OS3667
OS75160A
OS75161A
OS75162A
OS8640
OS8641
OS8642
OS8833
OS8834
OS8835
OS8836
OS8837
OS8838
OS8839
OS8T26A
OS8T28
OM74S240
OM74S241

DESCRIPTION

8-Bit TRI-STATE Bidirectional Transceivers
8-Bit TRI-STATE Bidirectional Transceivers
8-Bit TRI-STATE Bidirectional Transceivers
8-Bit TRI-STATE Bidirectional Transceivers
Quad Bus Transceiver
Quad Bus Transceiver
Quad High Speed Trapezoidal Bus
Transceiver
OS3662-The Bus Optimizer
Reducing Noise on Microcomputer Buses
IEEE-488 GPIB Transceiver
TRI-STATE Bidirectional Transceiver
IEEE-488 GPIB Transceiver
IEEE-488 GPIB Transceiver
IEEE-488 GPIB Transceiver
Quad NOR Unified Bus Receiver
Quad Unified Bus Transceiver
Quad Transceiver
Quad TRI-STATE Bus Transceiver
Quad TRI-STATE Bus Transceiver
Qliad TRI-STATE Bus Transceiver
Quad NOR Unified Bus Transceiver
Hex Unified Bus Receiver
Quad Unified Bus Transceiver
Quad TRI-STATE Bus Transceiver
4-Bit Bidirectional Bus Transceiver
4-Bit Bidirectional Bus Transceiver
Octal TRI-STATE Line Driver/Receiver
Octal TRI-STATE Line Driver/Receiver

• Also available screened in accordance with MlkSTD-883 Class B. Refer to National Semiconductor's "The Reliability Handbook".

PAGE
NUMBER

2-5,2-6
2-5,2-11
2-5,2-16
2-5,2-20
2-24
2-24
2-29
2-33
2-40
2-48
2-56
2-61
2-61
2-61
2-68
2-70
2-72
2-75
2-79
2-75
2-83
2-85
2-87
2-79
2-89
2-89
LOGIC
LOGIC

BUS CIRCUITS

Data bus circuits are not transmission line circuits in the normal interpretation where the transmission line is electrically long (1/4 wave length) with respect
to the baud rate. Like unbalanced transmission lines, the data transmission is susceptible to common-mode noise, such as ground I R noise and induced reactive
noise from crosstalk. A bus is a communications method where many elements of a system time share the same signal (address or data) bus. A bus shouldn't
extend out of its subsystem's electronic enclosure without special care. Line length in excess of 10 feet is not recommended without slew rate control. Cable~
should be in the form of twisted pair or flat cable where a signal wire is alternated with a ground wire.

OPEN-COLLECTOR BUS CIRCUITS
Bus Driver
Propagation
Delay (ns)

~

30
30
20
20
10
10
8
8
20
18
26
18
27

VIL (V)/
IOL(mA)

0.9/100
0.7/50
0.7/50
0.8/100
0.8/100
0.8/100
0.5/50
0.5/50
0.7/300
0.7/300
0.7/300
0.7/300
0.7/300

Bus Receiver
Propagation
Delay (ns)

VIL (V)/
IlL (IlA)

VIH (V)/
IIH(IlA)

23
20
20

1.2/-50
LOS/-50
1.05/-50

1.8/50
2.65/S0
2.6S/S0

40
30
17
20
10
10
7
7

1.50/400
1.2/-100
1.05/-100
1.3/-40
1.75/-100
1.75/-100
0.8/-500
0.8/-500

1.9/100
1.8/100
2.65/100
3.1/450
2.25/100
2.25/100
2/100
2/100

Hysteresis

(V)

Driver/
Receiver/
Transceiver
Receiver

1
1

Receiver

Receiver

Transceiver
Transceiver

1

Transceiver

Transceiver
Transceiver
Transceiver
Transceiver
Transceiver
Driver
Driver
Driver

Driver
Oriver

30
30

0.95/50
0.95/50

2/50
2/50

0.65
0.65

Receiver
Receiver

Device Number
Circuits/
Package

Commercial
O°C to +70oC

Military
-SSoC to +12SoC
057640
057836
057837

Comments

Page
No.

Quad NO R receiver
Quad NO R receiver

2·68
2·83
2·8S

Trapezoidal transceiver

2·29
2·70
2·72
2·87
2-24

4
4
6

058640
058836
058837

4
4
4
4
4
4
4
4
2
2
2
2
2

053662
058641
058642
058838
0526510
0526511
0536147
0536177
0575450
0575451
0575452
0575453
0575454

057838
0526510M
0526511M
0516147
0516177
0555450
0555451
0555452
0555453
0555454

Input to bus is non·inverting
Quad bidirectional I/O register
Quad bidirectional I/O register
ANO separate output transistors
AND
NANO
OR
NOR

2-24
6·35
6·35
3·51
3·51
3·51
3·51
3·51

1
1

OM8131
OM8136 .

OM7131
OM7136

6 bit bus comparator
6 bit bus comparator

LOGIC
LOG)C

057641
50n coax. driver

,

ap!nE) UO!IOalas

Selection Guide
!

TRI-STATE® BUS CIRCUITS
Bus Receiver

Bus Driver

~

Propagation
Delay
Typ (ns)
14
14
14
14
14
17
20
16
4.5
6
4.5
6
8
8
10

VOL (V)/ VOH (V)/
IOL(mA) IOH(mA)

Propagation
Delay
Typ (ns)
20
20
20
20
14
17
15
15
4.5
6
4.5
6
7
7
15

VIL (V)/
IIL!JlA)

vIHM/
IIH(IlA)

0.8/-40
0.8/-40
0.8/-40
0.8/-40
0.85/-200
0.85/-200
0.95/-250
0.95/-250
0.8/-400
0.8/-400
0.8/-400
0.8/-400
0.8/-500
0.8/-500
0.8/-250

2/80
2/80
2/80
2/80
2120
2/20
2/10
2/10
2/50
2/50
2/50
2/50
2/100
2/100
2/80

0.8/-250
0.8/-250
0.8/-250

2/80
2/80
2/80

0.5/50
0.5/50
0.5/50
0.5/50
0.5/48
0.5/48
0.6/55
0.6/50
0.55/64
0.55/64
0.55/64
0.55/64
0.5/50
0.5/50
0.5/50.

2;4/-10
2.4/-10
2.4/-10
2.4/-10
2.4/-10
2.4/-10
3.6/-1
3.6/-1
2.4/-3
2.4/-3
2.4/-3
2.4/-3
2.4/-5
2.4/-5
3.6/-5

10
10
11
20

0.5/50
0.5/50
0.5/50
0.45/15

3.6/-5
3.6/-5
3.6/-5
3.6/-1

10.
10
15

30

0.45/10

2.4/-1

20

0.8/-250

30

0.45/10

2.4/-1

20

20
20
20
20
·20

0.5/48
0.5/48
0.5/48
0.5/48
0.5/48

2.5/-5.2
2.5/-5.2
2.5/-5.2
2.5/-5.2
2.5/-5.2

20
20
20
20
20

Hysteresis.
(mV)
400
400
400
400

400
400
400
400

Driver/
Circuits/
Receiver/
Package
Transceiver
Transceiver
4
Transceiver
4
Transceiver
4
Transceiver
4
Transceiver
4
Transceiver
4
Transceiver
4
Transceiver
4
Transceiver
40r 8
Transceiver
4 or 8
Transceiver
8
Transceiver
8
Transceiver
4
Transceiver
4
Transceiver
8

Device Number
Military
Commercial
O°C to +70°C -55°C to +125°C
OS7833
OS8833
OS7835
OS8835
OS7834
OS8834
OS8839
DS7839
OS8T26AM
OS8T26A
OS8T28M
OS8T28
OP8216M
OP8216
OP8226M
OP8226
OM74S240
OM54S240
OM74S241
DM54S241
OM74S940
OM54S940
OM54S941
OM74S941
OS1647
OS3647
OS1677
OS3677
OP7304B
OP8304B

Comments

Page
No.

Non·inverting TR I-STATE receiver
Inverting TRI-STATE receiver
Inverting
Non-inverting
Inverting
Non-inverting
8080 MPU non-inverting
8080 MPU inverting
Non-Inverting
Inverting
Non-Inverting
Inverting
Quad bidirectional I/O register
Quad bidirectional I/O register
Bidirectional non-inverting
IEEE 488

2-75
2-75
2-79
2-79
2-89
2-89
8-11
8-11 .

Bidirectional inverting

2-5,2-6
2-5,2-16
2-5,2-20
8-4

LOGIC
LOGIC
LOGIC
LOGIC
6-35
6-35
2-5,2-11

Driver

8
8
8
8

OP8303
OP8307
OP8308
OP8212

OP7303
OP7307
OP7308
OP8212M

2/20

Transceiver

8

OP8228

OP8228M

0.8/-250

2/20

Transceiver

8

OP8238

OP8238M

0.8/-100
0.8/-100
0.8/-100
0.8/-100
0.8/-100

2/20
2/20
2/20
2/20
2/20

Transceiver

8
8
8
8
8

OS3666

IEEE 488 GPIB

OS3667
OS75160A
OS'75161A
OS75162A

2-48
2-56

IEEE 488 GPIB
IEEE 488 GPIB
IEEE 488 GPIB

2-61
2-61
2-61

Transceiver
Transceiver
Transceiver

·400
400
400
400
400

Note. Unless otherwise specified, bus circuits listed above are TTL compatible and use 5V supplies.

Transceiver
Transceiver
Transceiver
Transceiver

Bidirectional inverting
Bidirectional non-inverting
8080 MPU data latch and service
request f/f
8080 MPU system bus controller
and bus driver
8080 MPU system bus cqntroller
and bus driver

8-22
8-22

~National

·Bus Transceivers

~ Semiconductor

(A) (A)

....

..... (A)

CC

"tJ"tJ

..........
(A) (A)

-COCO
(A) (A)

General Description

00

This family of 8 high speed Schottky 8-bit TRI-STATE
bidirectional transceivers are designed to provide bidirectional drive for. bus oriented microprocessor and
digital communications systems. They are all capable
of sinking 16 mA on the A ports and 48 mA on the
B ports (bus ports). PNP inputs for low input current
and an increased output high (VOH) level allow compatibility with MaS, CMOS, and other technologies
that have a higher threshold and less drive capabilities_
In addition, they all feature glitch-free power up/down

on the B port preventing erroneous gl itches on the
system bus.in power up or down_

DP7303/DP8303 and DP7304B/DP8304B are featured
with Transmit/Receive (TiR) and Chip Disable (CD)
inputs to simplify control logic_ For greater design
flexibility, DP7307/DP8307 and DP7308/Dp8308 are
featured with Transmit (T) and Receive (R) control
inputs_

Logic Diagrams
DP7303/DP8303

DP7304B/DP8304B

AOo-+-_-;

X>---_--+-oBO

I

I

A2o---r-

( AJo-t~PORT ::~_

A6o-(

=

A7~_

_~Bl

~B2
--1
-j-oBJ }
_~:;

apORT

=j-oB6

.

_.....J'""""OB7

APORT

(

>---1>-1t-O BO

I

Al~=

I
_ .c..r-<>Bl

AJo-t-

~B2
--1
-j-oBJ }

~~~_

_~::

A2o---r-

A6o-(

=

A7~_

=j-oB6
TRANSMIT/RECEIVE

IT/AI

[JISA(~~~o-+-

AO

_ _ _ _ _ _ _ _--'

DP7308/DP8308

r------,
AO

BO

BO

I

I

I

I

I

I

I

I

::~_

=

A60-{:
A7<>-1-_
If!

OISA(~~~;o-

DP7307/DP8307

Al~_

TRANSMIT

CHIP

r------,

A2
AJo-(-

APORT

(TIAI

_ _ _ _ _ _ _--1

( ~-

-~
-j-oBJ1
_~B1

B2

=~::

SPORT

_.....J'""""OB7

TRANSMIT/RECEIVE

CHIP

-00

DP7303/DP8303 (Inverting) with Transmit/Receive and Chip Disable Control Inputs
DP7304B/DP8304B (Non-Inverting) with Transmit/Receive and Chip Disable Control Inputs
DP7307/DP8307 (Inverting) with Transmit and Receive Control Inputs
DP7308/DP8308 (Non-Inverting) with Transmit and Receive Control Inputs

LA1o---t...
_

..........
(A) (A)
COCO

a-Bit TRI-ST ATE® Bidirectional Transceivers

AOo-+-_-1

CC

"tJ"tJ

APORT

BPORT

=j-oB6

_J-<>B7
RECEIVE

rd== =~"}
A2
AJo-t-

-j-oBJ '

::~_

~::

A60-{:=
A7<>-1-_

J-oB6
=J-<>B7

TRANSMIT

IAI

If!

2-5

B2

BPORT

RECEIVE

IAI

CO~

JlJ

§J

co
Q.

C

s
CW)

'Ii:

~National'

a

Bus Transceivers

Semiconductor

DP7303/DP8303 a-Bit TRI-STATE®
Bidirectional Transceiver (Inverting)

C

Features
•

8-bit bidirectional data flow reduces system package
count
• Bidirectional TR I-STATE inputs/outputs interface
with bus oriented systems
• PNP inputs reduce input loading
• Output high voltage interfaces with TTL, MaS,
and CMOS

• Pinouts simplify system interconnections
• Transmit/Receive and chip disable simplify control
logic
.
•
•

Compact 20-pin dual-in-line package
Bus port glitch free power up/down

• 48 mA/300 pF bus drive capability

Logic and Connection Diagrams
Dual-In-Line Package
20 Vee

AD 1

AOo-ll-1-1 -:>0--......-+--0.0

I
[

AJo-t-

::~_

_~::

A2o---r-

AEo-t

=

16 83

A5

15 B4

B PORT

14

A6

TRANSMIT/RECEIVE

--4-o(iru--v ITIA)

01SAI~~~o-""'_ _ _ _ _ _--I

GND

B5

13 86

A1
CHIP DISABLE

CHIP

B2

A.

BPORT

=j-oB6

r---4

17

AJ
APORT

_..J-O B1

A100--t.. _

BO

18 B1

A2

_ ---.r--o. '
~.2
--1
-j--o.J }

Al~_

APORT

Al

I

L-

19

12 87

9 .
10

L-._ _ _ _- - I

11 TRANIii'EC

TOP VIEW

Order Number DP7303J, DP8303J,
or DP8303N
See NS Package J20A or N20A

Logic Table
RESULTING CONDITIONS

INPUTS

B Pcirt

Chip Disable

Transmit/Receive

A Port

0

0

OUT

IN

0

1
X

IN

OUT

1

TRI-STATE
X = Don't care

2-6

TRI-STATE

Absolute Maximum Ratings

Recommended Operating Conditions

(Note 1)

Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
5.5V
-65°C to +150°C
Storage Temperature
Maximum Power Dissipation* at 25°C
1667 mW
Cavity Package
Molded Package
1832 mW
Lead Temperature (soldering. 10 seconds)
300°C
'Derate cavity package 11.1 mW(C above 25°C; derate molded
package 14.7 mW(C.

DC Electrical Characteristics

Supply Voltage (VCe!
DP7303
DP8303
Temperature (TA)
DP7303
DP8303

Min

Max

Units

4.5
4.75

5.5
5.25

V
V

Conditions

-55
a

125
70

°c
°c

Typ

Min

Max

Units

A Port (AO-A7)
Volt~ge

VIH

Logical "1" Input

VIL

Logical "0" Input Voltage

CD = VIL. T/R = 2.0V

V

2.0

CD = VIL. T/R = 2.0V
DP8303
DP7303

VOH

Logical "1" Output Voltage

CD=T/R=VIL

10H = -O.4mA

VCC-1.15

VCC-0.7

10H = -3mA

2.7

3.95

VOL

Logical "a" Output Voltage

lOS

Output Short Circuit
Current

CD = VIL. T/R = VIL. Vo = OV.
VCC = max. Note 4

IIH

Logical "1" Input Current

CO= VIL, T/R = 2.0V, VIH = 2.7V

II

Input Current at Maximum
Input Voltage

CD = 2.0V, VCC = max, VIH = 5.25V

IlL

Logical "a" Input Current

CD = T/R =VILlloL = 16mA (8303)
iloL = 8 mA (both)

VCLAMP Input Clamp Voltage
100

Output/Input
TRI·STATE Current

-10

0.8

V

0.7

V
V
V

0.35

0.5

V

0.3

0.4

V

-38

-75

mA

0.1

80

p.A

1

mA
p.A

CD = VIL, T/R = 2.0V, VIN = Q.4V

-70

-200

CD = 2.0V, liN = -12mA

-0.7

-1.5

V

VIN = O.4V

-200

p.A

VIN = 4.0V

80

p.A

CD = 2.0V

B Port (BO-B7)
VIH
I

Logical "1" Input Voltage

VIL

Logical "a" Input Voltage

CD = VIL, T/R = VIL

VOH

Logical "1" Output Voltage

CD = VIL, T/R = 2.0V

V

2.0

CD = VIL, T/R = VIL
DP8303
DP7303

VOL

Logical "0" Output Voltage

CD = VIL, T/R = 2.0V

3.9

V

10H = -lamA

2.4

3.6

V

IOL = 20mA

0.3

0.4

V

10L =48mA

0.4

0.5

V

-150

mA

80

p.A

1

mA

-70

-200

p.A

-0.7

-1.5

V

VIN =0.4V

-200

p.A

VIN =4.0V

+200

pA

CD = VIL, T/R = VIL, VIH = 2.7V

II

CD = 2.0V. VCC = max. VIH = 5.25V

IlL

Logical "0" I nput Current

CD = VIL, T/R = VIL, VIN = 0.4V
CD = 2.0V, liN = -12mA

2·7

V

2.7

Logical "1" Input Current

100

V

10H ':' -5mA

Input Current at Maximum
Input Voltage

CD = 2.0V

0.7
VCC-0.8

IIH

Output/Input
TRI·STATE Current

V

VCC-1.15

CD = VIL, T/R = 2.0V, Vo = OV,
V CC = max, Note 4

VCLAMP Input Clamp Voltage

0.8

10H = -0.4 mA

Output Short Circuit
Current

lOS

-25

'1:J

i!1
w

C

'1:J

CD

(Notes 2 and 3)

Parameter

C

-50
0.1

W

o

W

('II)

o
~

DC Electrical Characteristics (cont'd.)

c

Control Inputs CD, T/R

a.

( 'II)

~
.....
a.

c

Parameter

(Notes 2 and 3)
Min

Conditions

VIH

Logical "1 ".Input Voltage

VIL

Logical "0" Input Voltage

IIH

Logical "1" Input Current

VIH = 2.7V

II

Maximum Input Current

VCC = max, VIH - 5.25V

IlL

Logical "0" Input Current

VIL = O.4V

Max

2.0
0.8

liN = -12mA

V

0.7

V

20

/lA

1.0

mA

-0.1

-0.25

mA

-0.25

-0.5

mA

-0.8

-1.5

V

0.5

I T/R

Units

V

I DP8303
I DP7303

I CD

VCLAMP Input Clamp Voltage

Typ

Power Supply Current
ICC

Power Supply .Current

CD=2.0V=VIN, Vcc=max

70

100

mA

CD =0.4V, VINA =T/R = 2V, VCC= max

100

150

mA

AC Electrical Characteristics

Vcc = 5 V, TA

= 25°C
Conditions

Parameter

Min

Typ

Max

Units

A Port Data/Mode Specifications
tPDHLA Propagation Delay to a Logical "0" from
8 Port to A Port

CD = 0.4 V, T /R = 0.4 V (figure A)
Rl = lk, R2 = 5k, Cl = 30pF

8

12

ns

tPDLHA Propagation Delay to a Logical "1" from
B Port to A Port

CD = 0.4 V, T /R = 0.4 V (figure A)
Rl = lk, R2 = 5k, Cl = 30pF

11

16

ns

tPLZA

Propagation Delay from a Logical "0" to
TRI·STATE from CD to A Port

BO to B7 = 2.4 V, T/R = 0.4 V (figure C)
S3 = 1, R5 = 1k, C4 = 15 pF

10

15

ns

tpHZA

Propagation Delay from a Logical "1" to
TRI·STATE from CD to A Port

BO to B7 = 0.4 V,T/R = 0.4 V (figure C)
S3 = 0, R5 = 1k, C4 = 15 pF

8

15

ns

tPZLA

Propagation Delay from TRI·STATE to
a Logical "0" from CD to A Port

BO to B7 = 2.4 V, T/R = 0.4 V (figure C)
S3 = 1, R5 = 1k, C4 = 30 pF

20

30

ns

tPZHA

Propagation Delay from TRI·STATE to
a Logical "1" from CD to A Port

BO to B7 = 0.4 V, T/R = O.4V (figure C)
S3 = 0, R5 = 5k, C4 = 30 pF

19

30

ns

B Port Data/Mode Specifications
tPDHLB Propagation Delay to a Logical "0" from
A Port to B Port

CD = 0.4 V, T /R = 2.4 V (figure A)
Rl = lOOn, R2 = 1k, C1 = 300pF
Rl = 6670., R2 = 5k, Cl = 45pF

12
7

18
12

ns
ns

tpDLHB Propagation Delay to a Logical "1" from
A Port to B Port

CD = 0.4 V, T /R = 2.4 V (figure A)
R1 = lOOn, R2 = lk, Cl = 300pF
R1 = 6670., R2 = 5k, Cl = 45pF

15
9

20
14

ns
ns

tPLZB

Propagation Delay from a Logical "0" to
TRI·STATE from CD to B Port

AO to A7 = 2.4V, T/R = 2.4 V (figure C)
S3 = 1, R5 = 1k, C4 = 15 pF

13

18

ns

tPHZB

Propagation Delay from a Logical "1" to
TRI·STATE from CD to B Port

AO to A7 = 0.4 V, T /R = 2.4 V (figure C)
S3 = 0, R5 = lk, C4 = 15pF

8

15

ns

tpZLB

Propagation Delay from TRI·STATE to
a Logical "0" from CD to B Port

AO to A7 = 2.4V, T/R = 2.4V (figure C)
S3 = 1, R5 = lOOn, C4 = 300pF
S3 = 1, R5 = 6670., C4 = 45 pF

25
16

35
25

ns
ns

Propagation Delay from TRI·STATE to
a Logical "1" from CD to B Port

AO to A7 = 0.4 V, T/R = 2.4 V (figure C)
S3 = 0, R5 = lk, C4 = 300pF
53 = 0, R5 = 5k, C4 = 45pF

22
14

35
25

ns
ns

tpZHB

2·8

C

AC Electrical Characteristics (cont'd.)

Vee

Parameter

"tJ

= 5V, TA = 25°e·

Conditions

......

Min

Typ

Max

Units

35

ns

Transmit/Receive Mode Specifications
Propagation Delay from Transmit Mode to
Receive a Logical "0," T /R to A Port

eD = 0.4 V (figure B)
Sl = 1, R4 = 100 n, C3 = 5 pF
S2 = 1, R3 = 1 k, C2 = 30 pF

23

tTRH

Propagation Delay from Transmit Mode to
Receive a Logical "1," T/R to A Port

CD = 0.4 V (figure B)
Sl = 0, R4 = 100 n, C3 = 5 pF
S2 = 0, R3 = 5k, C2 = 30 pF

22

35

ns

tRTL

Propagation Delay from Receive Mode to
Transmit a Logical "0," T /R to B Port

CD = 0.4 V (figure B)
Sl = 1, R4 = lOOn, C3
S2 = 1, R3 = 300 n, C2

26

35

ns

Propagation Delay from Receive Mode to
Transmit a Logical "1," T/R to B Port

CD = 0.4 V (figure B)
Sl = 0, R4 = lk, C3 = 300pF
S2 = 0, R3 = 300n, C2 = 5pF

27

35

ns

tTRL

= 300pF
= 5 pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not
meant to imply that the devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for
actual device operation.
.
Note 2: Unless otherwise specified, min/max limits apply across the supply and temperature range listed in the table cf necommended
Operating Conditions. All typical values given are for V CC = 5 V and T A = 25' C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless
otherwise specified.
Note 4: Only one output at a time should be shorted.

Switching Time Waveforms and AC Test Circuits

INPUT 3V

.:~::

1.5 V - t f

tr"'tf"'10ns
10"10 TO 90%

J'-'

t 5V

tP_O_HL_~\I:.
\::.....

" - - - 1 . 5 V t;_tP_O_LH_ _ _ _ _ _

t

On ORAn

VCC

VCC

RI
OUTPUT

I

PULSE
GENERATOR

II

"1"'

,........-~,

r-

-:t

±o.

~~

-U...

DEVICE
UNDER
TEST
R2

~

~,

-r-

-=-

NOTE, CllNCLUOESTEST FIXTURE CAPACITANCE.

FIGURE A. Propagation Delay from A Port to B Port or from B Port to A Port

2·9

C

"tJ

Q)

-

tRTH

W
0
W

W
0
W

i-

Switching Time Waveforms and AC Test Circuits (cont'd;)

o

If

111% TO 90%
OV

~

OUTPUT

1.SV

,

C-

O

tr '" tf ... 10ns

fN~~

( 'I)

(

tRTL

BPORT

.......

-=:y.:-RTH
.

1.SV
OUTPUT

VCC

A PORT

o-----t......--f

t---t----o B PORT
51 "I

52"1
VCC-+O

Rl

R4

VCC

NOTE: C2 ANO Cl INCLUOE TEST FIXTURE
CAPACITANCE.

FIGURE B. Propagation Delay from T/R to A Port or B Port

INPUT
CD

3V-------'--------------------~
If
tr '" tf .;;; 10ns
10% TO 90Cfg
OV

PORT OUTPUT

---+.,
IPHZ
PLZ

~
O.SV

PORT OUTPUT

---.1.
tpZL-'

VCC

O.4V

t--...........---o ~~~~UT
INPUT

DEVICE

t-+-------1CO

UNOER
TEST

RS

NOTE: C41NCLUOES TEST FIXTURE CAPACITANCE.
PORT INPUT IS IN A FIXED LOGICAL
CONDITION. SEE AC TABLE.

FIGURE C. Propagation Delay to/from TRI·STATE@from CD to A Port or B Port

2·10

al
~

o

C")

CO

Bus Transceivers

~National

~ Semiconductor

~

DJ

C

~

oC")
.....
Q.

......

(A)

Q.

"al

C

"'C

C

OP7304B/OP8304B 8-Bit TRI-STATE®
Bidirectional Transceiver (Non-Inverting)

"'C
CO
(A)

o

~

DJ

C

Features
•

8-bit bidirectional, data flow reduces system package
count

•

Bidirectional TR I-STATE inputs/outputs interface
with bus oriented systems

•

PNP inputs reduce input loading

•

Output high voltage interfaces with TTL, MOS,
and CMOS

•

48 mA/300 pF bus drive capability

•
•

Pinouts simplify system interconnections
Transmit/Receive and chip disable simplify control
logic

•
•

Compact 20-pin dual-in-line package
Bus port glitch free power up/down

Logic and Connection Diagrams

Dual-In-Line Package
AD 1

>---.....+- 81

AJo-t-

:~~_

_~::

A6o-t

=:::1-o

17

AJ

-:1--o

=

18

A2

~82 }
-...J
8J

A'D--t- _

19

Al

I

0--1:
o----r--- =

20 VCC

81
82

APORT

A4

16 BJ

A5

15 B4

B PORT

BPORT

B6

_ .....r-<'8'

14

A6

TRANSMIT/RECEIVE

...-_...._--+'O

I

I

I

1--

=_ 1
_ --.r--o"
~'2
-...J
-:::]-0'3

Al~

A2~-

.

{

A3o-t-

APORT

r-<> 84

::~_

20 Vee

Al

19

A2

18 B1

so

A3

17 82

A4

16 BJ

AS

\5 b4

A PORT

oPORT

B PORT

~B5

.

=:J-<>'6

AGo-t=
A700-t..._

AO

14

A6

_...J'""'007

B5

13 06

A7

12 87

GNO

10

11

R

TOP VIEW

Order Number DP7307J, DP8307J
or DP8307N
See NS Package J20A or N20A

Logic Table
CONTROL INPUTS
Transmit

RESULTING CONDITIONS

Receive

A Port

1

0

OUT

B Port
IN

0

1

IN

OUT

1

1

TRI-STATE

0

0

TRI-STATE

Both Active"

*This is not an intended logic condition and may cause oscillations.

2-16

Absolute Maximum Ratings

Recommended Operating Conditions

(Note 1)

Supply Voltage
7V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature
-65°C to +150°C
Maximum Power Dissipation' at 25~C
Cavity Package
1667 mW
Molded Package
1832mW
Lead Temperature (soldering, 10 seconds)
300°C
'Derate cavity pac~age 11.1 m~tC above 25°C; derate molded
package 14.7 mW/ C above 25 C.

DC Electrical Characteristics

Supply Voltage (VCC)
DP7307
DP8307
Temperature (TA)
DP7307
DP8307

Min

Max

Units

4.5
4.75

5.5
5.25

V
V

125
70

°c
°c

Conditions

Min

Typ

Max

Units

A Port (AO-A7)
VIH

Logical "1" Input Voltage

T = V I L, R = 2.0V

VIL

Logical "0" Input Voltage

T=VIL,R=2.0V

VOH

Logical "1" Output Voltage

2.0

T=2.0V,R=VIL

V

DP8307

O.B

V

DP7307

0.7

V

10H = -0.4 rnA

VCC-l.15

VCC-O."Z

10H = -3mA

2.7

3.95

VOL

Logical "0" Output Voltage

T = 2.0V,
R=VIL

lOS

Output Short Circuit
Current

T = 2.0V, R = VIL, Vo = OV,
VCC = max, Note 4
T = VIL, R = 2.0V, VIH = 2.7V

0.35

IIOL = 16mA (8307)
.IIOL = B rnA (both)
-10

V
V
0.5

V

0.3

0.4

-38

-75

rnA

V

0.1

80

JlA

1

rnA
/JA

IIH

Logical "1" Input Current

II

Input Current at Maximum
Input Voltage

R = T = 2.0V, VCC = max, VIH = 5.25V

IlL

Logical "0" Input Current

T= VIL, R = 2.0V, VIN = 0.4V

-70

-200

T= R = 2.0V, liN = -12mA

-0.7

-1.5

V

VIN = O.4V

-200

/J A

VIN =4.0V

BO

/JA

VCLAMP Input Clamp Voltage
10D

Output/Input
TRI·STATE Current

T = R = 2.0V

B Port (BO-B7)

R = VIL

VIH

Logical "1" Input Voltage

T= 2.0V,

VIL

Logical "0" Input Voltage

T = 2.0V, R = V I L

VOH

Logical "1" Output Voltage

2.0

T=VIL, R=2.0V

R = 2.0V

OPB307

O.B

V

0.7

V

VCC-l.15

VCC-O.B

10H = -5mA

2.7

3.9

V

10H = -lOrnA

2.4

3.6

V

T = VIL,

lOS

Output Short Circuit
Current

T = VIL, R = 2.0V, Vo = OV,
VCC = max, Note 4

IIH

Logical "1" Input Current

T = 2.0V, R = VIL. VIH = 2.7V

II

Input Current at Maximum
I nput Voltage

IlL

Logical "0" Input Current

10L = 20mA

0.3

10L = 4BmA

100

Output/I nput
TRI·STATE Current

V

10H = .;.0.4 rnA

Logical "0" Output Voltage

VCLAMP Input Clamp Voltage

V

OP7307

VOL

-25

0.4

V

0.4

0.5

-50

-150

rnA

BO

/JA

1

rnA
/J A

0.1

T = R = 2.0V, VCC = max, VIH = 5.25V

V

T = 2.0V, R = VIL, VIL = 0.4V

-70

-200

T= R = 2.0V, liN = -12mA

-0.7

-1.5

V

VIN = O.4V

-200

/J A

VIN =4.0V

+200

/JA

T = R := 2.0V

2·17

......
~
......

C
"'tJ
CO

-55
0

(Notes 2 and 3)

Parameter

C
"'tJ

~
......

DC Electrical Characteristics (cont'd.)

(Notes 2 and 3)
Conditions

Parameter

Typ

Min

Max

Units

Control Inputs T, R
VIH

Logical "1" Input Voltage

VIL

logical "0" Input Voltage

2.0
I DP8307

0.8

l DP7307

0.7

V

20

J.lA

IIH

Logical "1" Input Current

O.S

II

Maximum Input Current

VCC - max, VIH - S.2SV

IlL

Logical "0" Input Current

VIL = O.4V

VIH = 2.7V

V

1.0

mA

IR

-0.1

-0.2S

mA

IT

-0.2S

-O.S

mA

-0.8

-1.5

V

liN = -12mA

VCLAMP Input Clamp Voltage

V

Power Supply Current
ICC

Power Supply Current

T = R = 2.0V, VIN = 2.0Vi VCC = max

70

100

mA

T=O.4V, VINA= R = 2V, VCC= max

100

150

.mA

AC Electrical Characteristics

VCC= 5V, TA = 2S0C
Conditions

Parameter

Min

Typ

Max

Units

8

12

ns

A Port Data/Mode Specifications
tPDHLA Propagation Delay to a Logical "0" from
B Port to A Port

T = 2.4V, R = O.4V (figure A)
R 1 = 1k, R2 = Sk, Cl = 30 pF

tPDLHA Propagation Delay to a Logical "1" from
B Port to A Port

T = 2.4 V, R = 0.4 V

(figure A)
Rl = lk, R2 = Sk, Cl = 30pF

11

16

ns

tPLZA

Propagation Delay from a Logical "0" to
TRI-STATE from R to A Port

BO to B7 = 2.4 V, T = 2.4 V (figure B)
S3 = 1, R5 = 1k, C4 = 15 pF

10

15

ns

tPHZA

Propagation Delay from a Logical "1" to
TRI-STATE from R to A Port

BO to B7 = O.4V, T = 2.4V (figure B)
S3 = 0, R5 = lk, C4,= 15pF

8

15

ns

tpZLA

Propagation Delay from TRI-STATE to
a Logical "0" from R to A Port

BO to B7 = 2.4 V.. T = 2.4,V (figure B)
S3= 1, R5= lk,C4=30pF

25

35

ns

tPZHA

Propagation Delay from TRI·STATE to
a Logical "1" from R to A Port

. BO to B7 = O.4V, T = 2.4 V (figure B)
S3 = 0, R5 = 5k, C4 = 30 pF

24

35

ns

12
8

18
12

ns
ns

15

9

23
14

ns
ns

B Port Data/Mode Specifications
tPDHLB Propagation Delay to a Logical "0" from
A Port to B Port

T = 0.4V, R = 2.4V (figure A)
Rl = lOOn, R2 = lk, Cl = 300pF
Rl = 667 n, R2 = 5k, Cl =45 pF

tPDLHB Propagation Delay to a Logical "1" from
A Port to B Port

f

= 0.4 V, R= 2.4V (figure A)
Rl = lOOn, R2 = lk, Cl = 300pF
Rl = 667 n, R2 = 5k, Cl = 45pF

tPLZB

Propagation Delay from a Logical "0" to
TRI-STATE from T to B Port

AO to A7 = 2.4V, R= 2.4 V (figure B)
S3= 1, R5= 1k,C4= 15pF

13

18

ns

tpHZB

Propagation o'elay from a Logical "1" to
TRI-STATE from T to B Port

AO to A7 = O.4V, R = 2.4V (figure B)
S3 = 0, R5 = 1k, C4 = 15 pF

8

15

ns

tPZLB

Propagation Delay from TRI-STATE to
a Logical "0" from T to B Port

AO to A7 = 2.4V,R = 2.4V (figure B)
S3 = 1, R? = lOOn, C4 = 300pF
S3= 1, R5=667n,C4=45pF

32
18

40
25

ns
ns

Propagation Delay from TRI-STATE to
a Logical "1" from T to B Port

AO to A7 = 0.4 V, R= 2.4 V (figure B)
S3 = 0, R5 = 1k, C4 = 300 pF
S3 = 0, RS = 5k, C4 = 45 pF

25
16

35
25

ns
ns

tpZHB

2-18

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not
meant to imply that the devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for
actual device operation.
Not82: Unless otherwise specified. minimax limits apply across the supply and temperature range listed in the table of Recommended
Operating Conditions. All typical values given are for VCC = 5V and TA = 25°C.
Note 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless
otherwise specified.

OUTPUT

On OR An

VCC

VCC

INPUT

OUTPUT

DEVICE
UNDER
TEST

NOTE, CIINCLUOES TEST FIXTURE CAPACITANCE.

FIGURE A. Propagation Delay from A port to B port or from B port to A port

tt =

t, "lDns

10% TO 90%
OV

----+.,
tPHZ
PLZ

~
0.5V

---..i

IPZl--

Vce
PORT

2.4VO

~

INPUT 0.4 V

_ _ _ _ _ _~

S4

C

o......

10% TO 90%

PORT OUTPUT

(,)

tr = tf <: 10ns

PORT OUTPUT

......
o
......
(,)

CO

Switching Time Waveforms and AC Test Circuits

CONTROL INPUT

'"tJ

'"tJ

Note 4: Only one output at a time should be shorted.

3V

o

1--....- - - - 0 ~~~~UT

CONTROL
INPUT
DEVICE
UNDER
TEST

t-.....---iliORT

R5

NOTE, C41NCLUOESTEST FIXTURE CAPACITANCE.
PORT INPUT IS IN A FIXED LOGICAL
CONDITION. SEE AC TABLE.

Figure B. Propagation Delay to/from TRI-STATE from

2·19

Rto A Port and T to B Port

~
co

C") .

a..

c

co

~

Ii:
c

Bus Transceivers

~National

~ Semiconductor
·DP730S/DPS30S 8~Bit TRI-STATE®
Bidirectional Transceiver (Non-Inverting)

Features
•
•

8-bit bidirectional data flow reduces system package
count
Bidirectional TR I-SJATE inputs/outputs interface
with bus oriented systems

•

Pinouts simplify system interconnections

•
•
•

Independent T and Rcontrols for versatility
Compact 20-pin dual-in-line package
Bus port glitch free power up/down

• PNP inputs reduce input loading
• Output high voltage interfaces with TTL, MOS,
and CMOS
•

48 mA/300 pF bus drive capability

Logic and Connection Diagrams
Dual-ln·Line Package

r------,
AD 0--1-.....,

.>----.-4-080

I

I

I

I

APORT

A3o-tt::6:1-ASo--{:

11

AJ
A PORT

-j--08J

82

A4

16 83

AS

16 84

SPORT

BPORT

=J--08S
_
...,r-<>87

A7C>-L_

18 81

A2

"1-081

=
-C'::
=

19 80

Al

. ~B1}

~-

Al~_

A10--1"""

20 Vee

AD 1

14

AS

13 B6

A7

RECEIVE

85

IAI
12

GND

10

11

87

A

TOP VIEW

Order Number DP7308J, DP8308J
or DP8308N
See NS Package J20A or N20A

Logic Table
CONTROL INPUTS
Transmit

RESU L TING CONDITIONS
B Port

Receive

A Port

1

0

OUT

IN

0

1

IN

OUT

1

1

' TRI-STATE

0

0

TRI-STATE

Both·Active*

*Thls is not an Intended logic condition and may cause oscillations.

2-20

Absolute Maximum Ratings

Recommended Operating Conditions

(Note 1)

Supply Voltage
7V
5.5V
Input Voltage
Output Voltage
5.5V
_65°C to +150°C
Storage Temperature
Maximum Power Dissipation' at 25°C
Cavity Package
1667 mW
1B32mW
Molded Package
300°C
Lead Temperature (soldering, 10 seconds)

Supply Voltage (VCC)
DP730B
DPB30B
Temperature (T A)
DP730B
DPB30B

Min

Max

Units

4.5
4.75

5.5
5.25

V
V

125
70

°c
°c

-55
0

ilDerate cavity package 11.1 mW/oC above 2SoC;derate molded

package 14.7 mWt"C above 25°C.

DC Electrical Characteristics

(Notes 2 and 31

Parameter

Min

Conditions

Typ

Max

Units

A Port (AO-A])
VIH

Logical "1" Input Voltage

T=VIL,R=2.0V

VIL

Logical "0" Input Voltage

T = V I L, R = 2.0V

VOH

VOL

Logical "1" Output Voltage

Logical "0" Output Voltage

2.0

T=2.0V,R=VIL

T= 2.0V,
R=VIL

O.B

V

DP730B

0.7

V

10H = -O.4mA

VCC-1.15

Vce- 0.7

V

10H = -3mA

2.7

3.95

V

IIOL = 16 mA (B30B)

0.35

0.5

V

IIOL = B mA (both)

0.3

0.4

V

Output Short Circuit
Current

T = 2.0V, R = VIL, Vo = OV,
VCC = max, Note 4

IIH

Logical "1" Input Current

T = VIL, R = 2.0V, VIH = 2.7V

II

Input Current at Maximum
Input Voltage

R = T = 2.0V, VCC = max, VIH = 5.25V

IlL

Logical "0" Input Current

lOS

VCLAMP Input Clamp Voltage
100

Output/Input
TRI·STATE Current

V

DPB30B

-10

-3B

-75

mA

0.1

BO

JJ.A

1

mA
JJ.A

T = VIL, R = 2.0V, VIN = O.4V

-70

-200

T=R=2.0V,IIN=-12mA

-0.7

-1.5

V

VIN=O.4V

-200

JJ.A

VIN = 4.0V

BO

JJ.A

T=R=2.0V

B Port (BO-B7)
VIH

Logical "1" Input Voltage

VIL

Logical "0" Input Voltage

2.0

T=2.0V,R=VIL

DPB30B

VOH

Logical "1" Output Voltage

T = V llo R = 2.0V

10H = -O.4mA

VCC-1.15

VCC-O.B

V

10H = -5mA

2.7

3.9

V

10H = -10mA

2.4

3.6

T= 2.0V, R = VIL

V

DP730B

VOL

Logical "0" Output Voltage

lOS

Output Short Circuit
Current

T = VIL, R = 2.0V, Vo = OV,
VCC = max, Note 4

IIH

Logical "1" Input Current

'f = 2.0V, R = Vllo VIH = 2.7V

II

Input Current at Maximum
Input Voltage

T = R = 2.0V, VCC = max, VIH = 5.25V

IlL

Logical "0" Input Current

10L = 20mA

T = V I L, R = 2.0V

0.3

10L = 4BmA

VCLAMP Input Clamp Voltage
100

Output/Input
TRI·STATE Current

-25

O.B

V

0.7

V

V
0.4

V

0.4

0.5

-50

-150

rnA

BO

JJ.A

1

mA
IJ.A

0.1

V

T = 2.0V, R = Vllo VIN = O.4V

-70

-200

T = R = 2.0V, liN = -12mA

-0.7

-1.5

V

VIN = O.4V

-200

IJ.A

VIN = 4.0V

+200

IJ.A

T = R = 2.0V

2-21

C

"'C

~

C

"'C
00

~

00

DC Electrical Characteristics (cont'd.)

(Notes 2 and 3)

Parameter

Typ·

Min

Conditions

Max

Uniu

Control Inputs T, R
V,H

Logical "1" Input Voltage

V,L

Logical "0" Input Voltage

2.0

V
0.8

I DP8308
DP7308

I
IIH
"

IlL

Logical "1" Input Current

0.5

V,H = 2.7V

Maximum Input Current

VCC = max, V,H = 5.25V

Logical "0" Input Current

V,L = O.4V

TR
IT

VCLAMP Input Clamp Voltage

'iN = -12mA

V.

0.7

V

20

iJ.A

1.0

rnA

-0.1

-0.25

rnA

-0.25

-0.5

rnA

-0.8

-1.5

V

Power Supply Current
ICC

Power Supply Current

T= R = 2.0V, Y,N = O.4V, VCC= max
T= V,NA =0.4V,

AC Electrical Characteristics

R = 2V,

VCC= max

70

100

mA

90

140

rnA

Vcc = 5V, TA = 2SOC

Parameter

Conditions

Min

Typ

Max

Units

A Port Data/Mode Specifications
tPDHLA Propagation Delay to a Logical "0" from
B Port to A Port

T';' 2.4V, R = O.4V (figure A)
Rl = lk, R2 = Sk, C1 = 30pF

14

18

ns

tPDLHA Propagation Delay to a Logical "1" from
B Port to A Port

f

= 2.4 V, R = 0.4 V (figure A)
Rl = lk. R2 = Sk, C1 = 30pF

13

18

ns

tPLZA

Propagation Delay from a Logical "0" to
TRI·STATE from Rto A Port

BO to B7 = 0.4 V, T = 2.4 V (figure B)
S3= 1, RS= 1k;C4= 1SpF

11

15

ns

tpHZA

Propagation Delay from a Logical "1" to
TRI-STATE from Rto A Port

BO to B7 = 2.4 V, T = 2.4 V (figure B)
S3=0, R5= 1k,C4= 1SpF

8

15

ns

tPZLA

Propagation Delay from TRI-STATE to
a Logical "0" from R to A Port

BO to B7 = 0.4 V, T = 2.4 V (figure B)
S3 = 1, RS = 1k, C4 = 30 pF

24

35

ns

tPZHA

Propagation Delay from TRI-STATE to
a Logical "1" from R to A Port

BO to B7 = 2.4 V, T = 2.4 V (figure B)
S3 = 0, RS = Sk. C4 = 30pF

21

30

ns

18
11

23
18

ns
ns

R 1 = 100 n, R2 = 1k, C1 = 300 pF
R1 = 667 n, R2 = 5k, C1 = 45 pF

16
11

23
18

ns
ns

\

B Port Data/Mode Specifications
tpDHLB Propagation Delay to a Logical "0" from
A Port to B Port

T = O.4V, R = 2.4V (figure A)
Rl = lOOn, R2= lk,Cl = 300pF
R 1 ~ 667 n, R2 = 5k, C1 = 45 pF

tpDLHB Propagation Delay to a Logical "1" from
A Port to B Port

T = 0.4 V, R = 2.4 V (figure A)

tpLZB

Propagation Delay from a Logical "0" to
TRI-STATE from T to B Port

AD to A7 = 0.4 V, R = 2.4 V (figure B)
S3= 1, RS= lk,C4= lSpF

13

18

ns

tPHZB

Propagation Delay from a Logical "1" to
TRI-STATE from f to B Port

AO to A7 = 2.4 V, R= 2.4V (figure B)
53 = 0, R5 = 1k, C4 = 15 pF

B

lS

ns

tPZLB

Propagation Delay from TRI-5TATE to
a ·Logical "0" from f to B Port

AO to A7 = 0.4 V, R = 2.4 V (figure B)
53 = 1, R5 = 100 n, C4 = 300 pF
53 = 1, R5 = 667n, C4 = 45pF

25
17

35
25

ns
ns

Propagation Delay from TRI-5TATE to
a Logical "1" from f to B Port

AD to A7 = 2.4 V, R= 2.4 V (figure B)
S3 = 0, R5 = 1k, C4 = 300pF
S3 = 0, R5 = 5k, C4 = 45 pF

24
17

35
25

ns
ns

tPZHB

2-22

C

Note 1: ",Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not
meant to imply that the devices should be operated at these limits. The tables of "Electrical Characteristics" provide conditions for

"'0

actual device operation.

-

Note 2: Unless otherwise specified, minImax limits apply across the supply and temperature range listed in the table of Recommended
Operating Conditions. All typical values given are for VCC = 5 V and T A = 25° C.
Nota 3: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless
othOerwise specified.

......

~

co
C

"'0

Note 4: Only one output at a time should be shorted.

co

Switching Time Waveforms and AC Test Circuits

~

co
3V

tr =tf .. 10ns
IO%TO 90%

V,

t;'POLH

OUTPUT
BIIOR An

1.5

---I

VCC

VCC

INPUT

OUTPUT

DEVICE

UNDER
TEST

NOTE' CI INCLUDES TESTFIXTURE CAPACITANCE,

FIGURE A. Propagation Delay from A pott to B port or from B port to A port

t, = tf ... 10ns

, CONTROL INPUT

10% TO 90%
OV

PORT OUTPUT

----+..,
'PHZ
PLZ

~
D,5V

PORT OUTPUT

--1.

VCC
2,4VO

PORT
$)_ _ _ _ _ _-1
INPUT 0,4 V
'4

1---1----0 ~~~~UT

DEVICE
UNDER
TEST
I-~---tii DR T

R5

NOTE: C4 INCLUDES TEST FIXTURE CAPACITANCE,
PORT INPUT IS IN A FIXED LOGICAL
CONDITION, SEE AC TABLE,

Figure B. Propagation Delay to/from TRI-8TATE from

2-23

Rto A Port and f

to B Port

.
~ Semiconductor .

~National

Bus Transceivers

0826810, 0826811 Quad Bus Transceivers
General Description
The D526510 and D526511 are quad Bus Transceivers
consisting of 4 high speed bus drivers with open-collector
outputs capable of sinking 100 mA at O.BV and 4 high
speed bus receivers. Each driver output is connected
internally to the high speed bus receiver in addition to
being connected to the package pin. The receiver has a
5chottky TTL output capable of driving 10 5chottky
TTL unit loads.

The D526510 and D526511 feature advanced 5chottky
processing to minimize propagation delay. The device
package also has 2 ground pins to improve ground current handling and allow close decoupling between Vee
and ground at the package. Both GND 1 and GND 2
should be tied to the ground bus external to the device
package.

An active low enable gate controls the 4 drivers so that
outputs of different device drivers can be connected
together for party-line operation.

Features
•
•
•
•
•
•

The bus output high-drive capability in the low state
allows party-line operation with a line impedance as low
as 100n. The line can be terminated at both ends,
and still give considerable noise margin at the receiver.
Th~ receiver typical switching point is 2V.

Input to bus is inverting on D526510
Input to bus is non-inverting on D526511
Quad high speed open-collector bus transceivers
Driver outputs can sink 100 mA at O.BV maximum
Advanced 5chottky processing
PNP inputs to reduce input loading

Logic and Connection Diagrams
OS26S10

DS26S11
IZ

ZO

ZI

ZZ

ZO

Z3

Dual-in-Line Package

Z3

OSZ6S11N

iiii

ZO

,11

10
TOP VIEW

Z3

Dual-in-Line Package
vee

GND 1

zz

ZI

13

t

IZ

ZZ

ZI

ifj

DSZ6S10N

ZI

ifj

GND Z

GND 1

Order Number DS26S1OJ, DS26S10MJ
or DS26S10N
See NS Package J16A or N16A

iili

ZO

10

"
TOP VIEW

Order Number DS26S11J, DS26S11MJ
or DS26S11N
See NS Package J16A or N16A

2-24

GND Z

Absolute Maximum Ratings

Operating Conditions

-65°C to +150°C
Storage Temperature
-55°C to +125°C
Temperature (Ambient) Under Bias
-C.5V to +7V
Supply Voltage to Ground Potential
DC Voltage Applied to Outputs for
-C.5V to +VCC Max
High Output State
-C.5V to +5.5V
DC Input Voltage
200mA
Output Current, Into Bus
Output Current, Into Outputs (Except Bus)
30mA
DC Input Current
-30 mA to +5 mA

Supply Voltage (VCC)
DS26S10XC, DS26S11XC
DS26S10XM, DS26S11 XM
Temperature (TA)
DS26S10XC, DS26S11 XC
DS26S10XM, DS26S11XM

MIN

MAX

UNITS

4.75
4.5

5.25
5.5

V
V
°c
°c

+70
+125

0
-55

Maximum Power Dissipation- at 2SoC

Cavity Package
1433 mW
Molded Package
1362mW
"Derate cavity package 9.6 mW/"C above 25°C; derate molded
package 10.9 mW/"C above 25°C.
,

Electrical Characteristics
PARAMETER
VOH

(Unless otherwise noted)
CONDITIONS
(Note 1)

Output High Voltage
(Receiver Outputs)

MIN

VCC= Min, 10H = -1 rnA,

Military

2.5

VIN = VIL or VIH

Commercial

2.7

Output low Voltage
(Receiver Outputs)

VCC = Min, 10l = 20 rnA,

VIH

Input High level
(Except Bus)

Guaranteed Input lOllical High for
All Inputs

VIL

Input low level
(Except Bus).

Guaranteed Input logical low for
All Inputs

VI

Input Clamp Voltage
(Except Bus)

VCC = Min, liN = -18 rnA

VOL

IlL

Input low Current
(Except Bus)

IIHo

Input High Current
(Except Bus)

II

Input High Current
(Except Bus)

ISC

ICCl

TYP
(Note 2)

VCC = Max, VIN = 2.7V

VCC = Max, (Note 3)

Power Supply Current
(All Bus Outputs low)

VCC = Max, Enable = Gnd

V
V
V

0.5

V

2.0

0.8

V

-1.2

V

Enable

-0.36

rnA

Data

-0.54

rnA

20
30

/lA

100

/lA

Enable
Data

VCC = Max, VIN = 5.5V

Output Short-Circuit Current
. (Except Bus)

UNITS

3.4
3.4

VIN = Vil or VIH

VCC = Max, VIN = O.4V

MAX

Military
Commercial

-20
-18

DS26S10

45

DS26S11

/lA

-55

rnA

-60

rnA

70

rnA

80

rnA

Bus Input IOutput Characteristics
CONDITIONS
(Note 1)

PARAMETER
VOL

Output low Voltage
Military
VCC= Min

Commercial

TYP
(Note 2)

MAX

IOl=40mA

0.33

0.5

IOl=70mA
10l = 100 rnA

0.42

0.7

0.51

0.8

IOl-40mA

0.33
0.42
0.51

0.5
0.7

MIN

10l = 70 mA
10L - 100 mA

10

Bus Leakage CUrrent
Military
Commercial

/lA

100

Bus Leakage CUrrent (Power OFF)

Vo = 4.5V

VTH

Receiver Input High Threshold

Bus Enable = 2.4V,

Military

VCC= Max

Commercial

Bus Enable = 2.4V,

Military

2.0

VCC= Min

Commercial

2.0

Receiver Input Low Threshold

0.8

200

Vo = 4.5V
Vo = 4.5V

10FF

VTL

V

-50

Vo = O.BV
VCC= Max

UNITS

100
2.4
2.25

/lA
V

2.0
2.0

V

1.6
1.75

V
V

Note 1, For conditions shown as min or max, use the appropriate value specified under Electrical Characteristics for the applicable device type.
Note 2: Typical limits are at VCC = 5V, 25°C ambient and maximum loading.
Note 3: Not more than one output should be shorted at a time. Duration of the short circuit test should not exceed one second.

2-25

....

i

Switching

N

en

Charac~eristics

(TA = 25°C, VCC = 5V)

PARAMETER

C
cI

~
N

en
C

CONDITIONS

MIN

TYP

MAX

10

15

UNITS
ns

10

15

ns

12

19

ns

12

19

ns

14

18

ns

13

18

ns

15

20

ns

14

20

ns

tPLH

Data Input to Bus

tpHL

Data Input to Bus

tPLH

Data Input to Bus

tPHL

Data Input to Bus

tPLH

Enable Input to Bus

tpHL

Enable Input to Bus

tpLH

Enable Input tci Sus

tpHL

Enable Input to Sus

tPLH

.Sus to Receiver Out

RS = 50n, RL = 280n, Cs = 50 pF (Note 1),

10

15

ns'

tpHL

Sus to Receiver Out

CL=15pF

10

15

ns

tr

Bus

tf

Bus

OS26S10
OS26S11
RS = 50n, CB = 50 pF (Note 1)
OS26S10
OS26S11

RS = 50n, Cs = 50 pF (Note 1)

4.0

10

ns.

2.0

4.0

ns

Note 1: Includes probe and jig capacitance

Truth Tables
DS26S11

OS26S10
INPUTS

INPUTS

OUTPUTS

I

Z

L

L

H

L

H

H

L

H

X

Y

Y

Z

E

L

L

L

L

H

L

H

H

X

Y

Y

I

L

OUTPUTS

B

B
H

E

H = High voltage level
L = Low voltage level
X = Don'1 care
Y = Voltage level of bus (assumes control. by another bus transceiver)

Typical Application

L'oo 'oo '
L'oo'oo'
L'I'I' ~ECEIVERL'I"
~ 0526S10~: =} RECEIV~R
~~~} R~CEIVER
=}'

STROBE

INPUTS

STROBE

10 11 12 13

E

INPUTS

10 11 12 13

0526SI0:::}
Z2 I-- OUTPUTS

Z2 -

nl--.
5V

100

'"

INfifi'f

STROBE

10 11 12 13

OUTP~TS

nl--

~~S2S2

~~S2S2

Y

Y

ii'iPii'i'f

STROBE

E

OS26S11

Z2

10 11 12 13

I-- OUTPUTS

nl-~~S2S2

E

OS26S11
.

::
Z2 -

n~~S2S2

5V

.1lI0

.1!'!.

..A~O
,.AI 00
100 PARTY·lINE OPERATION

2-26

RECEIVER
OUTPUTS

AC Test Circuit and Switching Time Waveforms

ZTEST
POINT

Vee

PULSE
GENERATOR
NO.1

I INPUT

RO
50

.....
to'
DS26S11
ONLY

PULSE
GENERATOR
NO.2

eL
15 pF
T ( N OTE ll
BTEST
POINT

3V---------J----------,
1.5V

OV

-----.I

3V--,""",,\
DS26S10
TINPUT

OV------~-~-----J

3V--------t-------------r---~------·,_--------~
EINPUT

OV--~-~------~-----.I
VOH-----------r~--------~

BTESTPOINT

VOL - - - - - - - -

ZTESTPDINT

ALL DIODES
1N916 OR
EQUIVALENT

EINPUT

Note 1: Includes probe and jig capacitance.

DS26S11
TINPUT

Vee

J_--_____ II;""

VOH _ _ _tP_H_L__
1.5V\

--I

VDL

2·27

\'-----.11

-

Typical Performance Characteristics
Typical Bus Output Low Voltage vs Ambient Temperature
1.0

~

..
w

co

:=::>

.

'"
;;
....I

'"

>

~

V~C='5V

w

co

~
'"~

I

0.8

~

'">
....
::>

Receiver Threshold Variation
vs Ambient Temperature

0.6 I--

L1

!E

18US =100mA

~

IBUS= 70mA

i=

0.4

~

o
5

25 45

65

B5 105 125

TA - AMBIENTTEMPERATURE rC)

I I

2.4

2.3

f-

I-V~c=15.5J

2.2
2.1

2.0
1.9

~ . 1.8

IBUS= 40 mA
0.2

-55 -35 -15

2.5

Vcc - 5.25V

r-MIL~ r-

Vcc = 4.75V

~

~
V

COM'L

Vcc = 4.5V

1.7

'f

1.6

I I

!;"

1.5
-55 -35 -15

5

I

25

45

65

85 105125

TA - AMBIENT TEMPERATURE ('C)

Schematic Diagram
if
2, (7), (9),(15)

2k

Rl

3, (6),
(10), (14)

4,(5),
(11), (13) .

To---~~~--~~~

Vcc = Pin 16
GNO 1 = Pin 1
GNO 2 = Pin 8
Connect for OS26S10
* Remove Rl, aI, 01 for OS26S10

2-28

~National

Bus Transceivers

~ Semiconductor

OS3662 Quad High Speed TrapezoidalT~ Bus Transceiver
General Description

Features

The DS3662 is a quad high speed Schottky bus transceiver
intended for use with terminated 1200 impedance lines. It
is specifically designed to. reduce noise in unbalanced
transmission systems. The open collector drivers generate precise trapezoidal waveforms with rise and fall times
of 15 ns (typical), which are relatively independent of capacitive loading conditions on the outputs. This reduces
noise coupling to the adjacent lines without any appreciable impact on the maximum data rate obtainable with
high speed bus transceivers. In addition, the receivers use
a low pass filter in conjunction with a high speed comparator, to further enhance the noise immunity. Tightly
controlled threshold levels on the receiver provide equal
rejection to both negative and positive going noise pulses
on the bus.

• Pin to pin functional replacement for DS8641
• Guarantef)d AC specifications on noise immunity and
propagation delay over the specified temperature and
supply voltage range
• Temperature insensitive receiver thresholds track bus
logic level
• Trapezoidal bus waveforms reduce noise coupling to
adjacent lines
• Precision receiver thresholds provide maximum nOise
immunity and symmetrical response to positive and
negative going pulses
• Open collector driver output allows wire-OR connection,
• l:Iigh speed Schottky technology
• 15 p.A typical bus termination current with normal Vee or
withVee=OV
• Glitch free power up/down protection on the driver
output
• TTL compatible driver and disable inputs, and receiver
outputs

The external termination is intended to be a 1800 resistor
from the bus to 5V logic supply, together with a 3900
resistor from the bus to ground. The bus can be terminated
at one or both ends. A two input NOR gate is provided to
disable all drivers in a package simultaneously.

Block and Connection Diagram

, Dual-In-Line Package

Vee

BUS 1

IN 1

OUT 1

BUS 2

IN 2

IN 4

OUT 4

IN 3

OUT 2 DISABLE A

DISABLE B GNO

TOP VIEW

Order Number DS3662J or DS3662N
See NS Package J16A or N16A
TrapezOldal™ Is a trademark of National Semiconductor

2-29

Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions

Supply Voltage

7V

Input and Output Voltage
Storage Temperature Range
Maximum Power Dissipation· at 25·C
Cavity Package
Molded Package

5.5V

SupplyVoltage(Vccl

- 65·Cto 150·C

Max
5.25

0

70

Temperature Range (TA)

1509mW
1476mW

Units
V
·C ,

• Derate cavity package 10.1 mW/'C above 2S'C; derate molded package
11.8 mW/'C above 2S'C.

300·C

Lead Temperature (Soldering, 10 seconds)

Min
4.75

Electrical Characteristics (Notes 2 and 3)
Parameter

I

Conditions

I

Min

I

Typ

I

Max

I

Units

DRIVER AND DISABLE INPUTS
V IH

Logical "1" Input Voltage

V IL

Logical "0" Input Voltage

II

Logical "1" Input Current

V IN '7 5.5V

IIH

Logical "1" Input Current

V IN = 2.4V

IlL

Logical "0" Input Current

V IN =O.4V

VCL

Input Diode Clamp Voltage

ICLAMP= -12 mA

2.0

V
0.8

V

1

mA

40

/LA

-1

-1.6

mA

-0.8

-1.5

V

DRIVER OUTPUT/RECEIVER INPUT
VOLB

Low Level Bus Voltage

V DIS = 0.8V, V IN = 2V, I BUS = 100 mA

0.6

0.9

V

IIHB

Maximum Bus Current

V IN =0.8V, VBus=4V, Vcc=5.25V

10

100

/LA

100

/LA

IILB

Maximum Bus Current

V IN =0.8V, V Bus =4V, Vcc=OV

V IH

High Level Receiver Threshold

V IN = 0.8V, 10L = 16 mA

V IL

Low Level Receiver Threshold

V IN =0.8V, 10H= -400 /LA

1.90

1.70
1.70

V
1.50

V

0.5

V

RECEIVER OUTPUT
VOH

Logical "1" Output Voltage

V IN =0.8V, V Bus =0.5V, 10H= -400/LA

VOL

Logical "0" Output Voltage

V IN =0.8V, V Bus =4V, 10L = 16 mA

los

Output Short Circuit Current

V DIS =0.8V, V IN =0.8V, V Bus =0.5V,
Vos = OV, Vcc = 5.25V, (Note 4)

Icc

Supply Current

VDIS=OV, V IN =2V

2.4

3.2

V

0.35
-40

-70

-100

mA

50

90

mA

Max

Units

Switching Characteristics (Notes 2 and 3)
Parameter

Conditions

Min

Typ

PROPAGATION DELAYS
t pLHD

Disable to Bus "1"

25

35

ns

tpHLD

Disable to Bus "0"

25

35

ns

t pLHB

Driver Input to Bus "1"

20

30

ns

t pHLB

Driver Input to Bus "0"

20

30

ns

t pLHR

Bus to Logical "1" Receiver Output

25

40

ns

t pHLR

Bus to Logical "0" Receiver Output

25

40

ns

15

20

ns

20

10

ns

Figure 1

Figure 2

Figure 3

NOISE IMMUNITY
t rB, t'B

Rise and Fall Times (10%-90%) of the
Driver Output

Figure 2

tnR

Receiver Noise Rejection
Pulse Width

No Response at Receiver
Output as per Figure 4

10

Notel: "Absolute Maximum Ratings" are those values beyond which the safety 01 the device cannot be guaranteed. They are not meant to Imply that the
devices should be operated at these limits. The tables of "Electrical Characteristics" and "Recommended Operating Conditions" provide conditions for
actual device operation.
Note 2: Unless otherwise specified minimax limits apply across the supply and temperature range listed In the table of "Recommended Operating Condl·
tlons". All typical values are forTA= 2S'C and VCC= SV.
Nale 3: All currents Into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values

shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.

2-30

AC Test Circuits and Switching Waveforms
5.0V

,---------,

-500ns--'-3.0V---+'F::::::-----;;;;:~

91
OV
VOH---+----~----+_-,

Vo

5.0V--,,...,...;.----.....

zoo

V O L - - - + -J
-

tplHD
ENABLE TO BUS
IHIGH LEVEL)

Nole. 1,=11=2.5 ns. Pulse wldlh = 500 ns measu,ed betWeen 1.5V levels. 1= 1

MHz.

FIGURE 1. Disable Delays

5.0V

.----------,

3.0V
'V,
OV

91

V,

...
Z.5.~

VOH

Vo

1

Vo
VOL

_ _ _ ..: _ _ _ _ ':..

zoo

~

tpLHB

11.14

ORIVER INPUTTO BUS
ILOW LEVELl
Nole. 1,= 11=2.5 ns. Pulse wldlh=500 ns measu,ed belween 1.5V levels. 1= 1

DRIVER INPUTTO BUS
IHIGH LEVELl

MHz.

FIGURE 2. Driver Propagation Delays

5.0V

3.4V -------/.,,=,...----::::::"'1..
OV _ _ _ _1:;:,0%::,;.'f

390
V,";';~:--+--I

VOH

-------.,1-....

Vo

1.6k

VOL-----~~-~~---4_-j

tpLHR

Nole.

BUS TO LOGIC lOW LEVEL

BUS TO LOGIC HIGH LEVEL

RECEIVER OUTPUT

RECEIVER OUTPUT

I, = II = 15 ns. Pulse wldlh = 500 ns measured belween 1.7V levels. 1=1 MHz.

FIGURE 3. Receiver Propagation Delays
5.0V

, - - - REcEivER - - - ,
V,

390

.o-_---:1~10;:.:.,.:.;13
~
1
1
'4,1

lZ0

.

11,141
.

I

. .-

1

Z.5V

1 3,6,

1

~_2 _______ ~

J

3.4V

V,
...-

'5PF

....-Vo

BUS LOGIC
HIGH LEVEL

V,
OV

BUS LOGIC
LOW LEVEL

1,=11=2.5 ns

1,=1,=2.5 ns

(a) Receiver Output (VO) to
Remain Greater than 2.2V

(b) Receiver Output (Vo) to
Remain Less than O.7V

Uk

FIGURE 4. Receiver Noise Immunity: "No Response at Output" Input Waveforms

2·31

ien

Typical Application
1200 Unified Data Bus

C

5V

5V

!' 180

~

180

1..I --t-,II ..I
'1/4 DS36&2

390

~

,tf-.:.,

'1/4 DS3662

I
I I
I
I I
)
I
I I
.
I
I I·
L ___ _ .JL _ ; _

I
I
I
I
I

~

Ir,: _

_

t _,

1/4DS3662

II.. _

_

t _,

I

'1/4 DS3662

I
I

I I
I I

I
I

I

I
I
I I

I
I
I

I

.J L ____ .J L ____ .J

2-32

390

083662 - The. Bus Optimizer

»
z

National Semiconductor
Application Note 259
R.V. Balakrishnan
April 1981

•

m

I. Introduction
A single ended Bus is an unbalanced Data Transmission medium, which is timeshared by several system
elements. Like any unbaianced system, it is highly susceptible to common-mode noise, such as ground nOise
and crosstalk. In general, the latter determines the
maximum physical length of the Bus that can be incorporated with acceptable reliability. Crosstalk is a major
problem in high speed computer Buses which employ
Schottky Transceivers for increased data rate capability.
It is therefore highly desirable to minimize crosstalk
noise in Bus circuits to allow for longer Buses and to
provide higher system reliability.
This article describes the operation of the DS(3662 Quad
High Speed Trapezoidal Bus Tranceiver, which has been
specially designed to minimize crosstalk problems. The
Driver generates precise Trapezoidal waveforms that
reduce noise coupling to adjacent Bus channels. The
Receiver uses a low pass filter, whose time constant is
matched to the Driver slew rate to provide maximum
noise rejection with acceptable signal delay characteristics. Precision high speed circuitry optimizes noise
immunity without sacrificing the high data rate capability
of Schottky Tranceivers.

II. The Problem
Conventional Bus Drivers are designed to provide high
output currents for charging and discharging relatively
large Bus capacitances quickly. These high speed transitions are characterized by peak slew rates of up to 5
volts/ns around the mid-region of the transition. This
can cause considerable noise coupling to adjacent
lines, commonly referred to as crosstalk.·Crosstalk also

s-L

includes noise induced by sources external to the Bus.
Additional noise may be generated due to reflections at
imperfect terminations.
Bus Receivers are designed to respond to high speed
transitions and to provide low propagation delays.
Unfortunately, their fast response results in high noise
sensitivity. The combined effect of the noise on the Bus
and the sensitivity of the Receiver to the noise severely
limits the Bus performance.

III. The Solution
The above situation can be considerably improved by
employing noise reduction techniques in both the Driver
and the Receiver circuits. Slew rate control can be used
in the Driver to reduce crosstalk, and Receiver noise sensitivity can be reduced by using a low pass filter at its
input. These techniques are commonly used in line
transmission circuits where the associated data rates
in general are considerably lower. However, these
techniques do present some difficulties in high speed
Bus circuits. Increased rise and fall times, resulting
from slew rate control, can affect data rates unless care
is taken to limit the maximum rise and fall times to minimum pulse width requirements. With any appreciable
slew rate control, the rise and fall times of the resulting
Driver output waveform will be comparable to the pulse
widths at maximum data rates. This condition dictates
high fidelity of the transmitted waveform and precise
Receiver thresholds at the middle of the Bus voltage
swing in order to minimize pulse width distortion.
Figure 1 illustrates the different sources of pulse width
distortion due to the trapezoidal nature of the signal ..

~

DRIVER INPUT

V.

V•

....l.-

~
I I
-

VoI2- -

I

VTH

...L.-

---VTH
AND
~
I
I
RECEIVER INPUT

DRIVER OUTPUT
AND
RECEIVER INPUT

I
I

I

I
I

~

RECEIVER OUTPUT

V.

.
RECEIVER OUTPUT

V•

.....L..-

....l.....-

r~

-VTH
AND
~
I
I
RECEIVER INPUT

DRIVER OUTPUT

V·I2U===~ ~~gEIVER INPUT
I

DRIVER OUTPUT

V.I2- -

I

JL
I

I

DRIVER INPUT

I

I

IL

DRIVER OUTPUT

V.I2- -

.

I
I

I
I

~

RECEIVER OUTPUT

DISTORTION DUE TO OFF CENTERED
RECEIVER THRESHOLDS (VTH)

RECEIVER OUTPUT

DISTORTION DUE TO NON SYMMETRICAL
TRAPEZOIDAL DRIVER OUTPUT WAVEFORM

Figure 1_ Pulse Width Distortion
2-33

~
z


_0

......
""""
!:i!:i
u:u:
......
.....
IE IE

..

~.L

C*

OUTPUT
(TO RECEIVER)

BUS
TERMINATION

3902 _

FILTER
DELAY

~

e.;:-

~

2V

1V

~~ ov

FILTER
DELAY

...

-

-_::r--

I--t-h-----=~"~~-I__+__;~__
tSIGNAL .,.,...
~
NOISE .........

'I.......

, , / ) ....

BUS LOGIC HIGH
LEVEL=3.4V

~-+/""""""~"J "
, ..
"
I+---l'---,jot'-,,:t-----~,,~+--'~,i.:....-."'f_...J/------ RECEIVER THRESHOLD

~
~

"

...

..:...::..
NOI~?

0

10

20

" \ '.,

30

40

VTH=1.7V

~~'-'
r
SIGNAL.......... _

.... ~~ .... _

"

50"

0

10

20

30

40

50

TIME IN NANO SECONOS

Figure 2. Ideal Receiver Low Pass. Filter Response

2-34

»
z
•

120Q UNIFIED DATA BUS

+5V

PJ

+5V
180Q

390Q

Figure 3. Bus Termination

JL

DRIVER INPUT

~ DRIVER OUTPUT

Vo _ _ Ir.
Vo12
- " II
OV
I
I

~Ip~

Ipm" 20ns


ful Bus length to less than 10 feet. In" contrast, the
DS3662's Driver generates much less crosstalk and its
Receiver is immune to the Induced noise even when the
noise amplitude exceeds the signal amplitude as seen
In the oscillogram at 50 feet. When the same experiment was repeated with the DS8641, It responded to the
noise even at 10 feet as shown in Figure 14.

The AC response of the DS3662 Driver and Receiver are
depicted in Figures 11 and 12 respectively. Figure 11
shows the typical Driver output waveform as compared
to a standard high speed Transceiver output. Oscillo·
grams in Figure 12 demonstrate the ability of the
Receiver to distinguish the trapezoidal signal from the
noise. Here the Receiver rejects a noise pulse of 19ns
width, while accepting a narrower signal pulse (= 16 ns)
of the same amplitude (The signal is triangular since the
pulse width is smaller than the rise and fall time of the
Trapezoidal Driver output).

Figure 15 shows the plots of maximum data rate versus
line length for the three Transceivers discussed above
under two different conditions. The graph in Figure 15a
is obtained with no consideration to the pulse width dis·
tortion whereas the one in Figure 15b is obtained for a
maximum allowable pulse width distortion of ±100/0. A
square waveform is used so that the pulse width dis·
tortion criteria will apply to both positive and negative
going pulses. These graphs clearly show that the
DS3662 can be used at considerably higher data rates
with lower distortion for longer distances than the other
two Transceivers (Figure 15b) although the others have
a slightly higher data rate capability at short distances
with high timing distortion (Figure 15a).

The performance of the Transceiver under actual ope·
rating condition is demonstrated in Figures 13 through
15. Oscillograms in Figure 13 clearly show the capa·
bility of the DS3662 in real life situations. Here it is compared with the DSBB34 under identical conditions. The
Transceivers drive a minicomputer Bus (flat ribbon
cable) 100 feet long, terminated at the far end with taps
at various lengths for connecting to the Receiver input.
The cable is randomly folded to generate crosstalk
between the various parts. In addition a noise pulse is
induced on the signal line by driving an adjacent line
with a pulse generator. This corresponds to the second
dominant pulse in the Bus waveforms at approximately
600ns from the main Signal pulse. As can be seen, the
DSBB34 with fast rise and fall times on the Driver output
generates more crosstalk and its Receiver easily
responds to this crosstalk and to the externally induced
noise (even though it has hysteresis!), limiting the use-

VII. Conclusion
The DS3662, with its combination of a trapezoidal Driver
and a noise rejecting Receiver utilizing on chip capaci·
tors, represents a Significant improvement in high speed
Bus circuits and a solution to"Bus noise problems com·
monly encountered in Mini and Microcomputer systems.

-TIME 10 NS/D1V

-TIME 10 NS/D1V

TYPICAL HIGH SPEED BUS DRIVER
OUTPUT WAVEFORM

DS3662 - TRAPEZOIDAL DRIVER
OUTPUT WAVEFORM
Figure 11.

4V
3V
2V
lV
OV
3V
2V
1V
OV
NOISE INPUT

-

TIME 10 NS/D1V

SIGNAL INPUT

Figure 12. 053882 Receiver Response
2-37

Z
•

fa

fa
N

•
Z

OS3662

OS8834


Z•

088641

I\)

4V

en
CO

3V
RECEIVER
INPUT

2V
lV
OV

10 FEET

4V
RECEIVER
OUTPUT

2V
OV
-+

TIME 100 N8/D1V
Figure 14.

DS3662
I......

i'

OS3662~

OS8641
08834· ......

DS8834
TWISTED PAIR CABLE

~22 AWG STRANDEDJo

ERMINATEO 180/3
50% OUlY,RYCLE
10

os841

TWISTED PAIR CABLE
(22 AWG STRANOEOJ
TERMINATED 180/3 0 g
50% OU1'f,,~~CLE

g

100

1000

10

100

LINE LENGTH (FT)

LINE LENGTH (FT.)

(b)

(a)

FIgure 15. Data Rate vs. Line Length

2·39

1000

......

~ Reducing Noise on

~

National Semiconductor
Application Note 337
R. V. Balakrishnan
May 1983

Microcomputer Buses

Abstract: This paper focuses on the noise components
that have a significant impact on the performance of a
high speed microcomputer bus. An overview of their
nature is followed by ways to minimize theircontribution
by suitable design of the PC board backplane, the termination network and the bus transceiver. The D83662 trapezoidal bus transceiver, which is specifically designed to
minimize such noise on high speed buses, is presented
along with its performance data. And to conclude, some
possible new transceiver designs for further improvement
of the bus performance are explored.

The bus appears like a transmission line to any signal having a transition time 't,' less than the round trip delay '2T L'
of the bus. The bus delay 'TL' is given by:
h= L --.lL1 C1
where

(1)

L = length ofthe bus
L1 = distributed inductance per unit length·
C1 = distributed capacitance per unit length

For a typical unloaded 1000 microstrip line, C1 '" 20 pFIft
and L1 '" 0.2 ,.H/ft. Therefore, h'" 2.0 nslft. This corresponds to approximately half the speed of light.
However, the capacitive loading at each connector on the
backplane increases the deiay time significantly. The
'loaded delay time 'TLL' is given by:

INTRODUCTION
As the microcomputer bus bandwidth is extended to
handle ever increasing clock rates, the noise susceptibility of a single-ended bus poses a serious threat to the
overall system integrity. Thus, it is mandatory that the
various noise contributions be taken into account in thedesign of the bus transceiver, the PC board backplane and
the bus terminations to avoid intermittent or total failure
of the system.
Although noise such as crosstalk and reflections are inevitable in any practical bus configuration, their Impact on
the system can be determined and minimized by 9areful
design of all three components mentioned above. The
combined contribution of the noise under worst-case conditions should be within the noise margin for reliable bus
operation.

TLL=TL --.11 + (C L/C1)

(2)

where C L = distributed load capacitancelunit length
Given a 10 pF loading at each connector (connector+
transceiver capaCitance) and a 0.6" spacing between connectors, C L =200 pF/ft and hL=6.6 nslft. So even a 6"
long bus has a 2T LL = 6.6 ns, which is higher than the transition time (t,) of many high speed bus drivers. When in
doubt, it is always better to use the transmission line approach thaI) the lumped circuit approach as the latter Is an
approximation of the former. Also, the transmission line
analysis gives more pessimistic (worst-case) values of
crosstalk and reflection and is, hence, safer.

CROSSTALK REDUCTION

The design of the transceiver plays a significant role in
minimizing crosstalk and reflection. The bus can be optimized for minimum noise at a given bandwidth by using a
trapezoidal driver having suitable rise and fall times along
with a matched low pass filtered receiver which provides a
symmetrical noise margin. The OS3662 is one such transceiver, the first member in the family of trapezoidal bus
transceivers available from National Semiconductor
Corporation. This device represents a significant Improvement in high speed bus circuit design and provides a solution to commonly encountered bus noise problems.

The crosstalk is due to the distributed capacitive coupling
Cc and the distributed Inductive coupling Lc between two
lines. When crosstalk is measured on an undrlven sense
line next to a driven line (both terminated at their
characteristic impedances), the near end crosstalk and
the far end crosstalk have quite distinct features, as
shown in Figure 1. Their r~spective peak amplitudes are:
VNE=KNE(2h)(Vl/tr)
VNE=KNE(V 1)

fortr>2h

(3)

fortr<2h

(4)

VFE = KFE(L)(Vl/t r)

(5)

where VI = signal swing on the drive line.
The coupling constants are given by the expressions:

THE MICROCOMPUTER BUS
A typical micrQcomputer bus usually consists of a printed
circuit board backplane with signal and ground traces on
one side and a ground plane on the other. The iength
ranges from a few inches to several feet with as many as
32 closely spaced (0.6" typical) card edge connectors.
Each signal line interacts with the ground plane to form a
transmission line with characteristic impedance 'Z' in the
range of 901l-120IHypical. It is desirable to have as large a
'Z' as possible in order to reduce the drive requirement of
the bus driver and to reduce the power dissipate-d at the
terminations. But much larger values of 'Z' translate to
significantly larger physical dimensions and therefore are
not very practical.

K

_ L (CcZ + Le/Z)
NE4TL

K

FE=

Ce Z - Lo/Z
1ft
2
ns

(6)

(7)

The near end component reduces to zero at the far end and
vice versa. At any point in between, the crosstalk is a fractional sum of near and far end crosstalk waveforms shown.
It should be noted from expressions 6 and 7 that the far
end crosstalk can have either polarity whereas the near
end crosstalk always has the same polarity as the signal
causing it. In microstrip backplanes the far end crosstalk
pulse is usually the opposite polarity of the original Signal.

2-40

Although the real world bus is far from the ideal situation.
depicted in Figure 1, .several useful observations that
apply to a general case can be made:

2. Smaller signal amplitude with the same transition time
reduces bus drive requirements without reducing noise
immunity.

1. The crosstalk always scales with the signal amplitude.
2. Absolute crosstalk amplitude is proportional to slew
rate VIII" not just 111,.
3. Far end crosstalk width is always t,.
4. For t,<2h, the near end crosstalk amplitude VNE expressed as a fraction of signal amplitude VI is a function
of physical layout only.
5. The higher the value of 't,' the lower the percentage of
crosstalk (relative to signal amplitude).

3. Far end crosstalk is eliminated if the receiver is designed to reject pulses having pulse widths less than or
equal to t,.
4. When t,< 2T L, the near end crosstalk immunity for a
given percentage noise margin has to be built into the
backplane PC layout. Since (V NEiVl) = KNE for this case,
KNE should be kept lower than the available worst-case
noise margin. KNE may be reduced by either increasing the
spacing between lines or by introducing a ground line in
between. The ground line, in addition to increasing the
spacing between the signal lines, forces the electric field
lines to converge on it, significantly reducing crosstalk.

The corresponding design implications are:
1. The noise margin expressed as a percentage of the signal swing is what's important, not the absolute noise
margin. Therefore, to improve noise immunity, the percentage noise margin has to be maximized. This is achieved by
reducing the receiver threshold uncertainty region and by
centering the threshold between the high and low levels.

5. For minimum crosstalk the rise and fall times of the
signal waveform should be as large as possible consistent with the minimum pulse width requirements of the
bus. A driver that automatically limits the slew rate of the
transition can go a long way in reducing crosstalk.

I----------~------~I.r-L---------------·I

~II ~

DRIVEN LINE

RTI_1

~III

I 11

RT

II

SENSE LINE

RTI

IIIRT
I

~-

---y

"----

I

-tr+ 2TL -

~

I -j

VI
VNE=KNE2lL- lorl,>2lL
=KNE VI

I,

for 1,<2lL

¥I

~
VFE;KFEL

~:

~tr-

FAR END CROSSTALK

NEAR END CROSSTALK

TlIF15281·1

FIGURE 1. Crosstalk Under Ideal Conditions

2-41

.....
('I)
('I)

•

z


output design
'

Connection Diagram

•
•
•
•
•
•
•
•
•

Meets IEEE Standard 488-1978
High speed Schottky design
Low power consumption
High impedance PNP inputs (drivers)
500 mV (typ) input hysteresis (receivers)
On·chip bus terminators
No bus loading when Vee is removed
Power up/down protection (glitch·free)
Mode control implements 2·device expansion for com·
plete IEEE·488 interface configuration
• Accommodates multi·controller systems

Dual·ln·Line Package
SC

u

..1.

24

I-- VCC

.!!. (NOT USED I

TE...!
REN/IFC

..!

~REN/IFC

NRFDINDAC

..!

!!.. NRFD/NDAC
.!!!.. DATA A

DATAA-l

.!!.. DATAB

DATA B...!!.
DS3666
BUS

DATAC...!.

!!. DATA C

DATA D....!

1!.. DATA 0

....!

!!!.. ATN/EOI

EDI/ATN..!.!!.

.!!. Eol/ATN

SROIDAV..!.l

.!i. SROIilAV

MODE

GND

TERMINAL

. .!!. DC

.E.
TOP VIEW

Order Number DS3666N
See NS Package N24C
TR1·STAT~ Is a registered trademark at National Semiconductor Corp.

2-48

TLIFI5244·1

Logic Diagram

c

en
w

SC~.O-----__~

C')
C')
C')

TE~

REN/IFC _2_2----1-~..--_t

,>_~._----;;.3

REN/IFC

+-_.._~

~-~t------

NRFD/NDAC

NRFD/NDAC _2_1_ _ _ _

DATA A ..;;2;;.0---_I-~t_-_I I~-~~----;;.DATAA

DATAB..;;I;;.9----+--~-_I

1>-_....+----"- DATA B

TERMINAL

BUS

18

DATA C -----1-~..--_t '>-~.._t_---;;.DATAC

DATA 0 ..;;1;..1_ _ __I-~t_-_I I~-~~t_---;;.DATAD

14

SRQ/DAV -----1-~..--_t

EOI/ATN -,1;;.5----I-I-~~-_t

I.>_~t-t_--+l-l SRO/DAV

'>_~t-t_-+-+l;;.O

DC~.o-+-+-'-+--i--~

EOI/ATN

Note 1:

-D>-

Denotes driver

Note 2:

~

Denotes receiver

Note 3: Symbol "OC" specifies open collector output

ATN/EDI

Note 4: Driver and receiver outputs that
are not specified "OC" are totem-pole
configurations

16

Note 5: The data and SRQ/DAV driver outputs can have their active pull-ups disabled
by switching the appropriate inputs EOI/ATN,
Mode, and ATN/EOI. This mode configures
the outputs as open collector.
MODE

2·49

cc

Ic

Device Truth Tables
TRANSCEIVER DIRECTION
Mode

X
X
X
X
H
H
H
H
L
L
L
L
L
L

Control Input Level
TE
DC
ATN/EOI
SC

H
L
X
X
X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
H
L
H
L
X
X
H
L

X
X
H
L
H
L
X
X
X
X
H
L
X
X

REN/IFC

X
X
X
X'
X
X
X
X
X
X
'H
H
L
L

Transceiver Signal Direction
NRFD/NDAC
SRQ/DAV
EOI/ATN

Data

T
R
R
T

T
R
T
R
R
T
T
R
T
R
R
T

OUTPUT CONFIGURATION
Mode

Control Input Level
EOI/ATN*
ATN/EOI

X
X
X
X
H
L

H
L
H
L
X
X

H
H
L
L
X
X

Transceiver Bus Output Configuration
SRQ/DAV
Data
Totem·Pole
Totem·Pole
Totem·Pole
Open Col/ector
Totem·Pole
Open Collector

H = High level Input
L = Low level Input
X = Don't care
T = Transmit, I,e" signal outputted to bus
R = Receive, I.e" signal outputted to terminal
,
·The EOIIATN transceiver signal level Is sensed for inlernalloglc control of bus port data
output configuration

Functional' Description
,

'

The DS3666 is an 8·channel bi·directional transceiver with
internal logic specifically configured to implement the
IEEE-488 bus interface. Expansion logic is included so
that two DS3666 devices may be interconnected to form
the complete 16·lIne interface. This approach is equivalent
to pairing the DS75160A and the DS75162A devices to implement the 16·line bus. The port connections to the bus
lines have internal terminators, in accordance with the
IEEE·488 Standard, that are deactivated when the device
is powered down. This feature guarantees no bus loading
when Vcc=OV. The bus port data outputs have a control
mode that either enables or disables the active upper
stage of the totem·pole configuration. When the upper
stage Is disabled, the data outputs operate as open collec·
tor outputs, which are necessary for parallel polling. In
compliance with the system organization of the manage·
ment signal lines, the NRFD/NDAC bus port output is a
fixed open collector configuration. Also, the SRQ/DAV bus
port output is configured so that the SRQ output is open
,collector in the expanded Implementation of the device.
Transceiver direction control is divided into three groups.
The NRFD/NDAC and data lines are controlled by the TE
input. The RENIIFC line is controlled by the SC input. And

the EOliATN and SRQ/DAV lines are controlled by the TE or
DC input, depending on the expansion mode. A special
case is the direction of the designated EOlline, which is a
function of both the TE and DC inputs, as well as the logic
level present on the ATN line.

TABLE OF SIGNAL LINE ABBREVIATIONS
Signal Line
Classification '
Control
Signals
Data
110 Ports

Management
Signals

Mnemonic

Definition

DC
TE
SC
Data A, Data B,
Data C, Data 0
ATN
DAV
. EOI

Direction Control
Talk Enable
System Controller
BI·dlrectional Data
Transceivers
Attention
Data Valid
End or Identify
Interface Clear
Not Data Accepted
Not Ready for Data
Remote Enable
Service Request

IFC
NDAC,
NRFD
REN
SRQ

2·50

IEEE·488 Interface Configuration Truth Tables (see Configuration Diagram)
MANAGEMENT SIGNALS
Control Input Level
SC
TE
DC

ATN"

H
H
H
H

H
H

H

R

L

T

L
L

H

R

L

T

L
L
L
L

H
H

H

R

L

T

L
L

H

R

L

T

X
X
X
X

H

X
X
H

L

X
X

L

DATA SIGNALS

Transceiver Signal Direction
EOI REN
IFC SRQ NRFD NDAC DAV

H
H

T
T
T
T

T
T
T
T

T

R
R
R
R

R
R
R
R

T

R
T

R
R
T

R

,Control Input Level
Data Transceivers
ATN
EOI
TE Direction Bus Port ConfiQuratlon

R
R

R
R

T
T

X
H

X
H

L

R

H

T
T

T
T

R
R

L

H

R
R

R
R

T
T

H
L
L

H
L

H
H

T
T
T
T

T
T

T
T

R
R

Input
Totem·Pole Output
Totem·Pole Output
Totem·Pole Output
Open Collector Output

T

R
R

L
L

T

H = High level input
L= Low level input
X = Don't care
T = Transmit, i.e., signal outputted to bus
R = Receive, i.e., signal outputted to terminal
"The ATN signal level is sensed for internal multiplex control of EOI transmission direction logic

IEEE-488 Interface Configuration
Implementation Using the 053666

r-----1

I
IFC
NOAC
DATA (Bl)
DATA (B2)
DATA (B3)
DATA(B4)
ATN
OAV

=>
......Ii!;

!!!
REN

SRn

I

DATA (01)

20

6

19
DS3666

NDAC
DATA (D2)

18

I

8

17

I

+5V~
10

16

I

I
I

15

I

14

I

..!!.

13

.'

I
I

3
4

21

I

5

20

I

6

19

I

18

I

I

7

I

8

I

OV..!
10
11

I

I
GND

I
L

-ITE SC

-

..!!.

053666

ATN
DAV

I
I

l!. VCC
#22 USED)
(NOT

2

DATA (03)
DATA (D4)

11

1

DATA (B8)

EOI

IFC

5

DATA (B6)
DATA (B7)

I
I

,
,
I

NRFO
DATA (B5)

21

4

I
I

w

I

~~SED)

I

GNO
~

23 (NOT

I-- VCC

2

7

,

24

3

I

Terminal Interface
Block Diagram

I
I

REN
NRFD
DATA (D5)
DATA (D6)

17

DATA (07)
DATA (08)

~
15

I

14
I

13

EOI
SRn

I

- - - - -

-I
DC

TUF15244-3

2-51

TUF15244·4

Absolute Maximum Ratings (Note 1)

Operating Conditions
Min

Max

Units

Supply Voltage, Vcc
7.0V
Input Voltage
5.5V
Storage Temperature Range
- 65·Cto 150·C
Maximum Power Dissipation' at 25·C
Molded Package
2005mW
300·C
Lead Temperature(Soldering, 10 seconds)

Vcc, Supply Voltage
4.75
TA, Ambient Temperature
0
io L, Output Low Current: Bus
Terminal

5.25
70
48
16

V
·C
mA
mA
I

• Derale molded package 16.0 mW/'C above 25·C.

Electrical Characteristics (Notes 2 and 3)
Parameter

,

Conditions

VIH

High·Level Input Voltage

Min

Typ

Max

2

Units
V

VIL

Low·Level Input Voltage

VIK

Input Clamp Voltage

VHYS

Input Hysteresis

'Bus

VOH

High·Level
Output Voltage

Terminal
Bus (Note 5)

10H = - 800 jtA
10H- -5.2 mA

VOL

Low·Level
Output Voltage

Terminal
Bus

10L= 16 mA
10L-48 mA

0.3
0.4

0.5
0.5

V

IIH

High·Level
Input Current

VI=5.5V
VI-2.7V

0.2
0.1

100
20

p.A

IlL

Low·Level
Input Current

Terminal
and
Control
Inputs

VI=0.5V

-10

-100

jtA

VBIAS

Terminator Bias
Voltage at Bus Port

3.0

3.7

V

ILOAD

Terminator
Bus Loading
Current

11 = -18 mA

Driver
Disabled

-0.8

II(bUS)=O (No Load)
VI(bus) = -1.5V to O.4V
VI(bus) = 0.4V to 2.5V

Bus

Driver
Disabled

Short·Circuit
Output Current

Icc

Supply Current

CIN

Bus·Port
Capacitance

Terminal
Bus (Note 5)

Bus

V

500

mV

2.7
2.5

3.5
3.4

V

2.5
-1.3
0

-3.2
2.5
-3.2
2.5
2.5

0
0.7

mA

40

jtA

-35
-75

-75
-150

mA

VI = 0.8V, SC = 2.0V, TE = 2.0V,
DC = 2.0V, Mode = 2.0V,
ATN/EOI = 2.0V

90

135

mA

Vcc = 5V or OV, VI = OV to 2V,
f=1MHz

20

30

pF

Vcc = 0, VI(bus) = OV to 2.5V ,
los

V

-1.5

400

VI(bUS) = 2.5V to 3.7V
VI(bUS) - 3.7V to 5V
VI(bUS) ..; 5V to 5.5V

0.8

VI = 2V, Vo = OV (Note 4)

-15
-35

Note 1: "Absolule Maximum Ratings" are those values beyond which Ihe safely of Ihe device cannot be guaranteed. They are not meant to imply that the
device should be operated at these limits. The table of ~'Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minimax limits apply across the O'C 10 + 70'C temperature range and the 4.75V to 5.25V power supply range. All typical
values are for TA =25'C and VCC =5.0V.
Note 3: All currents Into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min are so classified on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: This characteristic does not apply to the NRFD/NDAC bus output since Ills open colleclor.
2-52

Switching Characteristics Vcc = 5.0V ± 5%, TA = O°C to WC (Note 1)
Parameter
tpLH

From

Propagation Delay Time,
Low to High Level Output

-----1'-----=-------'----j Terminal
tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

-----1f----=-------'----j Bus
tpHL

Propagation Delay Time,
High to Low Level Output

tPZH

Output Enable Time
to High Level

tpHZ

Output Disable Time
from High Level

Control
Inputs
-t-P-ZL-.+-o-u-t-Pu-t-E-n-a-b-Ie-T-i-m-e--'--I (Note 2)
to Low Level
Output Disable Time
from Low Level

tpZH

Output Enable Time
to High Level

tpHZ

Output Disable Time
from High Level

Max

10

20

Bus

VL =2.3V
RL =38.30
C L =30 pF
Figure 1

14

20

VL =5.0V
RL = 2400
CL =30 pF
Figure 2

14

20

Terminal

10

20

VI =3.0V
VL=OV
RL =4800
CL =15 pF
Figure 1

23

40

15

27

VI=OV
VL =2.3V
RL = 38.30
CL =15pF
Figure 1

28

48

17

35

VI = 3.0V
VL=OV
RL=3 kO
C L =15 pF
Figure 1

18

45

22

33

Bus

Control

__-+_________-linputs
(Note 2)
(Note 3)

tPZL

Output Enable Time
to Low Level

t pLZ

Output Disable Time
from Low Level

tPZH

Output Pull·Up Enable
Time

ATN/EOI

---+---------~Input

Output Pull·Up Disable
Time

(Note 2)

Conditions

Typ

(Note 3)

tpLZ

tpHz

To

Terminal

Bus
Data
Outputs

Min

Units

ns

ns

ns

ns

ns

~~---+----~-+-----~-------1---­

VI=OV
VL =5V
RL = 2800
CL =15pF
Figure 1

28

56

20

35

VI =3V
VL=OV
RL = 4800
CL =15pF
Figure 1

10

20

10

20

ns

ns

Note 1: Typical values are for Vcc= 5.0V and TA =25·C and are meant for reference only.
Note 2: Refer to functional truth table for control Input definition.
Note 3: Test configuration should be connected to only one transceiver at a time due to the high current stress caused by the VI voltage source when the
output connected to that input becomes active.

Switching Load Configurations
TEST
DEVICE
Vlo- IN

TEST
DEVICE

~

OUT .....- . -.........

Vc 0- CONTROL
OUT~

Vc 0- CONTROL

-L 1CL*...
T

-''- C "

-=-

~L

Vc logic high = 3.0V

TLIFI5244-5

Vc logic low=OV

Vc logic high = 3.0V

" ..

_

~ lN914

~ ~ lN914
" , lN914

-f-

~

Vc logic low = OV

TUF15244-6

* CL includes jig and probe capacitance

*CL Includes jig and probe capacitance

FIGURE 1

FIGURE 2
2·53

Switching Waveforms
TERMINAL*
(INPUT)

'H
OV

--=1

Transmit Propagation Delays

1 SV
•

I.SV\_
I.2=tPHL

BUS
(OUTPUTI

BUS*
(lNPUTI

,w
OV

TLIF/5244-?

-=1

Receive Propagation Delays

1.5V\,----

I.SV

l~tPHL-

TERMINAL
(OUTPUT)

I.SV
TLIF/5244-8

Terminal Enable/Disable Times
3V
CONTROl*
INPUT
OV

TERMINAL
OUTPUT

TERMINAL
OUTPUT
TL/F/524409

Bus Enable/Disable Times
3V
CONTROL*
INPUT
OV

BUS
OUTPUT

.·!:=-

t PZH

BUS
OUTPUT

2.07

'-----------------~

*Input signal: f= 1.0 MHz, 50% duty cycle, t r =tf,,5 ns

Performance Characteristics
Bus Port Load Characteristic

~

<
oS

~r0 ~ ~
lii;~~41~f9~1

I-

ffi

a:
a:

B
'"
iil

..

-2
-4
...jj

I

Q

-8

~ -10
-12

~

~

'",I

i%
~
~
~
-2 -1

0

3

6 .

4

VI- BUS VOLTAGE (VI

TUFI5244-"

Refer to Electrical Characteristics Table

2-54

TUF15244·10

IEEE·488 Specification Summary
logic Nomenclature. When referring to the IEEE·488
specification publication, the following logic conventions
are used:
'
1) A "true" condition corresponds to a logic low signal
level.
2) A "false" condition corresponds to a logic high signal
level.
Bus Specification. The IEEE·488 bus is comprised of 16
signal lines intended for digital data exchange at a maxi·
mum rate of 1 Mbaud and for a maximum transmission
path length of 20 meters.
Terminal Devices. The IEEE·488 bus will support a maxi·
mum of 15 interconnected devices. These devices may be
configured in four different modes of operation:
1) Talk only (e.g., counter)
2) Listen only (e.g., printer)
3) Listen and talk (e.g., multi meter)
4) Listen, talk, and control (e.g., calculator)
Data Bus. The data bus has 8 signal lines, denoted 010,
through DIOa. These lines carry data and Interface
messages in a bi·directional asynchronous, bit parallel,
byte serial form.
Data Byte Transfer Control Bus. These 3 signal lines are
used to control the transfer of data bytes across the data
bus lines.
1) NRFD (Not Ready for Data). This signal originates from
a listen device and indicates to a talker that a listen
device is not ready to accept data.

2) DAV (Data Valid). This signal originates from a talker
device and indicates to a Iisten device that data present
on the data bus is valid.
3) NDAC (Not Data Accepted). This signal originates from
a listen device and indicates to a talker device that data
on the data bus has not been accepted.
General Interface Management Bus. These 5 signal lines
provide general management of all bus operations.
1) ATN (Attention). This Signal originates from a controller
device and indicates to other devices on the bus how
the data bus Information is to be interpreted.
2) IFC (Interface Clear). This signal originates from a con·
troller device and causes all interface logic to be set to
a known state.
3) REN (Remote Enable). This Signal originates from a
controller device and is used in conjunction with other
messages to tell a remote device which of two sources
of Information is to be used. The source is designated
as being remote or local.
4) SRQ (Service Request). This Signal is generated by a
remote device to indicate to the controller device a
need for attention.
5) EOI (End or Identify). This signal is generated by a talker
device to indicate the end of a multi byte transfer. This
signal may also originate from a controller, in conjunction with ATN to execute a polling sequence.

2-55

C
en
W
CD
CDCD

Ii ~ Semiconductor
National
tn'

c

Bus Transceivers

~

083667 TRI-STATE® Bidirectional Transceiver

General Description

Features

The DS3667 Is a high speed Schottky 8-channel bidire,ctional transceiver designed for digital information and
communication systems. Pin selectable totem-pole/open
collector outputs are provided at all driver 'outputs. This
feature, together with the Dumb Mode which puts both
driver and receiver outputs in TRI-STATE at the same time,
means higher flexibility of system design. PNP inputs are
used at all driver inputs for minimum loading, and
hysteresis is provided at all receiver Inputs for added
noise margin. A power up/down protection circuit is included at all output\3 to provide glitch·free operation
dlJring Vee power up or down.

• 8·channel bidirectional non-inverting transceivers
• Bidirectional control. implemented with TRI-STATE
output design
• High speed Schottky design
• Low power consumption
• High impedance PNP inputs (drivers)
• Pin selectable totem-pole/open collector outputs
(drivers)
'. 500 mV (typ) input hysteresis (receivers)
• Power up/down protection (glitch-free)
• Dumb Mode capability

Connection Diagram
Dual-In-Line Package

u

TE.2

~Vcc

B12

r!!!- 01

B2.2.

t1!-02

B3.!

~03

~04

B4...2.
BUS

TERMINAL

053667
B5..!

t12-05

B6.2.

~06

B7...!

.!!. 07

BS...!!.

~OS

GN02!!. L..-_ _ _ _ _ _-'.!!..PE
TUFI5245-1

TOP VIEW

Order Number DS3667N
See NS Package N20A
TRI·STATE'·" is a registered trademark of National Semiconductor Corp.

2-56

c
en
CAl

Logic Diagram
01 19

»--1>---+-..;;.2 B1

02 18

»--1>-+-+-..;;.3 B2

03 17

4 B3

04 .;;16=--_ _ _ _--+~H

en
en

.....

1.>-....-+-+_5_ B4

Functional Truth Table
Control
Input
Level
PE
TE

BUS

TERMINAL

05 15

06 14

6 B5

7 B6
1>--1-+-+_.:..

Input

Output

TRI·STATE

TRI·STATE

H

L

T

L
L

H
L

R
D

A: Receiving Mode
D: Dumb Mode

2-57

Terminal Port

T

T: Transmitting Mode

Note 2:--<:ij-- Denotes receiver

Bus Port
Totem·Pole
Output
Open
Collector
Output
Input

H

H: High Levellnpul

Note1:--[9--0enotes driver

Mode

H

L: Low Levellnpul

07 13

Data Transceivers

Input

Operating Conditions

Absolute Maximum Ratings (Note 1)
7.0V
Supply Voltage, Vcc
5.5V
Input Voltage
-65°Cto150°C
Storage Temperature Range
Maximum Power Dissipation' at 25°C
1B32mW
Molded Package
300°C
Lead Temperature(Solderlng, 10 seconds)

Vcc, Supply Voltage
TA, AmbientTemperature
10L' Output Low Current
Bus
Terminal

Min

Max

Units

4.75
0

5.25
70

V
°C

4B
16

mA
mA

.'Derate molded package 14.7 mW/'C above 25·C.

Electrical Characteristics (Notes 2 and 3)
Parameter

Conditions

VIH

High Level Input Voltage

VIL

Low Level Input Voltage

Min

Typ

Max

2

V
O.B

Input Clamp Voltage

VHYS

Input Hysteresis

Bus

VOH

High Level
Output Voltage

Terminal
Bus

10H= -BOO~
10H- -5.2 mA

VOL

Low Level
Output Voltage

.Terminal
Bus

10L= 16 mA
IOL-4B mA

0.3
0.4

0.5
0.5

IIH

High Level
Input Current

TE,PE

VI =5.5V
VI -2.7V

0.2
0.1

100
20

Low Level
Input Current

los

Short Circuit
Output Current

Icc

Supply Current

C IN

Bus·Port
Capacitance

-O.B

-1.5

VIK

IlL

11= -1BmA

Terminal
and Bus

VI =4V

Terminal
and TE, PE
Bus

VI =0.5V

Terminal
Bus

VI =2V, Vo=OV (Note 4)

Bus

Units

V
V

400

500

mV

2.7
2.5

3.5
3.4

V
V

, p.A

200
-10

-100

p.A

-0.4

-1.0

mA

-35
-120

-75
-200

mA

Transmit, TE = 2V, PE = 2V, V = O.BV
Receive, TE=O.BV, PE=2V, VI = O.BV

75
65

100
90

mA

Vcc= OV, VI=OV,
f = 10 kHz (Note 5)

20

-30

pF

-15
-50

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to Imply that the
device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minimax limits apply across the O'C to + 70'C temperature range and the 4.75V to 5.25V power supply range. All typical
values are 10rTA = 25'C and VCC =5.0V.
Note 3: All currents into device pins are shown as positive; all currentsDutof device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min are so classified on absolute value basis.

Note 4: Only one output at a time should be shorted.
Note 5: This parameter is guaranteed by design. It Is not a tested parameter.

2·5B

Switching Characteristics Vee = 5.0V ± 5%, TA = OOG to 700G (Note 1)
Parameter

From

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpLH

Propagation Delay Time,
Low to High Level Output

tpHL

Propagation Delay Time,
High to Low Level Output

tpZH

Output Enable Time
to High Level

tpHZ

Output Disable Time
from High Level

tpZL

Output Enable Time
to Low Level

tpLz

Output Disable Time
from Low Level

tpZH

Output Enable Time
to High Level

t pHZ

Output Disable Time
from High Level

Terminal

Bus

Bus

TE,PE
(Note 2)
(Note 3)

Output Enable Time
to Low Level

t pLZ

Output Disable Time
from Low Level

tpZH

Output Pull·Up Enable
Time
Output Pull·Up Disable
Time

Bus

Terminal

TE
(Note 2)
(Note 3)

tpzL

tpHZ

To

Terminal

PE
(Note 2)

Bus

Conditions

Min

Typ

Max

Units

VL = 2.3V
RL = 38.3n
C L =30pF
Figure 1

10

20

ns

14

20

ns

V L = 5.0V
RL = 240n
C L =30 pF
Figure 2

15

20

ns

10

20

ns

VI =3.0V
VL=OV
RL = 480n
C L =15pF
Figure 1

19

30

ns

15

20

ns

VI=OV
VL = 2.3V
RL = 38.3n
C L =15 pF
Figure 1

24

40

ns

17

30

ns

VI =3.0V
VL=OV
RL = 3 k(l
C L = 15 pF
Figure 1

19

35

ns

17

25

ns

VI=OV
V L =5V
RL = 280n
C L =15pF
Figure 1

27

40

ns

17

30

ns

VI =3V
VL=OV
RL = 480n
C L =15pF
Figure 1

10

20

ns

10

20

ns

Note 1: All typical values are for TA = 25"e, Vee = 5V.
Note 2: Refer to Functional Truth Table for control input definition.
Note 3: Test configuration should be connected to only one transceiver at a time due to the high current stress caused by the VI voltage source when
the output connected to that input becomes active.

Switching Load Configurations
Vl

Q
Vl

~

TEST
DEVICE

~

~ Rl

VIC-- IN

TEST
DEVICE

~

VI C-- IN

Rl

OUT

T
-

VcC-- CONTROL

OUT ~
VcC-- CONTROL
-- ..... C *
Tl

lr~

..LI;~
Cl

_

~ lN914

~~ lN914
~ ~ lN914

TlIF15245·3

Ve logic high = 3.0V

Ve logic high = 3.0V

Ve logic low = OV

Ve logic low = OV

-.=
TLiF/S245-4

* CL includes jig and

* CL includes jig

probe capacitance

FIGURE 1

and probe capacitance

FIGURE 2
2·59

I

Switching Waveforms

en

c

Transmit Propagation Delays
TERMINAL* 3.0V - - : 11sV
(INPUT)
•

OV

,w't-tp-H:-L---

"t:t

PLH

BUS
(OUTPUT)

/2.0V
---I
TLIFI5245-5

Receive Propagation Delays

'~~'HL~

BUS* 3.0V--:1
(INPUT)
1.5V

OV

t=t

PLH

!1.5V

TERMINAL
(OUTPUT)

1.5V

---I

TLIF/5245-6

Terminal Enable/Disable Times
3V
CONTROL*
INPUT

OV

TERMINAL
OUTPUT

TERMINAL
OUTPUT
TUF/5245-7

Bus Enable/Disable Times
3V
CONTROL*
INPUT

OV

BUS
OUTPUT

BUS
OUTPUT
"Inpul signal: f= 1,0 MHz, 50% duty cycle, t r =tfs5 ns

2·60

TUF/5245-8

cc

en
Bus Transceivers en
............
c:.n
c:.n
....L ....L

~National

~ Semiconductor

DS75160A/DS75161A/DS75162A IEEE·488 GPIB Transceivers
General Description

Features

This family ofhigh-speed-Schottky8-channel bi-directional
transceivers is designed to interface TTL/MaS logic to the
IEEE Standard 488-1978 General Purpose Interface Bus
(GPIB)_ PNP inputs are used at all driver inputs for
minimum loading, and hysteresis is provided at all receiver
inputs for added noise margin_ The IEEE-488 required bus
termination is provided internally with an active turn-off
feature which disconnects the termination from the bus
when Vce is removed_ A power up/down protection circuit
is included at all bus outputs to provide glitch-free operation during Vee power up or down.
The General Purpose Interface Bus is comprised of 16
signal lines-8 for data and 8 for interface management.
The data lines are always implemented with DS75160A,
and the management lines are either implemented with
DS75161A in a single-controller system, or with DS75162A
in a multi-controller system.

• 8-channel bi-directional non-inverting transceivers
• Bi-directional control implemented with TRI-STATE®
output design
• Meets IEEE Standard 488-1978
• High-speed Schottky design
• Low power consumption
• High impedance PNP inputs (drivers)
• 500 mV (typ) input hysteresis (receivers)
• On-chip bus terminators
• No bus loading when Vcc is removed
• Power up/down protection (glitch-free)
• Pin selectable open collector mode on DS75160A driver
outputs
• Accommodates multi-controller systems

Connection Diagrams (Top Views)
Dual-In-Line Package

Dual-In-Line Package
20 Vee

TE

19

01

B1

1B
'2

02

B3

17 03

B4

15 04
OS75160A

'US

12

88

GNO

10

17

NDAC

16

NRFD
BUS

NDAI:
NRFO
TERMINAL

DS75161A
15 OAV

OAV

06

"

~Ol

13 07

B7

REN

18 IFC

1Fe

TERMINAL

I.

B6

Vee

19

REN

15 D5

B5

20

TE

13

ATN

08

GNO

ATN

12 SAn

SRO

11 PE

EOI

11

10

TLlFI5243·'

DC

TUF15243·2

Dual-In-Line Package
se

r---'-~----, 22 Vee

21 (NOT USED)

TE

20

REN

19

1Fe

1Fe

DS75162A

17 NRFD

BUS

TERMINAL

16 DAV

OAV

15

E01

TAI·STATE@ is a registered trademark of

Order Number DS75160AN,
DS75161AN or DS75162AN
See NS Package N20A or N22A

18 NDAC

NDAC

NRFO

REN

E01

ATN

14 ATN

SAQ 10

13 SAn

GND 11

12 DC

National Semiconductor Corp.
TLlF15243-3

2-61

0) 0)
I\) 0

-

:t>:t>

c
en
......
c:.n
....L

0)

....L

:t>

Logic Diagrams

Functional Description

DS75160A

DS75160A
This device is an 8·channel bi·directional transceiver with
one common direction control input, denoted TE. When
used to implement the IEEE·488 bus, this device is con·
nected to the eight data bus lines, designated DI0 1-DIO s.
The port connections to the bus lines have internal termin·
ators, in accordance with the IEEE·488 Standard, that are
deactivated when the device is powered down. This
feature guarantees no bus loading when Vcc = OV. The bus
port outputs also have a control mode that either enables
or disables the active upper stage of the totem·pole con·
figuration. When this control input, denoted PE, is in the
high state, the bus outputs operate in the high·speed
totem·pole mode. When PE is in the loW state, the bus·out·
puts operate as open collector outputs which are neces·
sary for parallel polling.

2 Bl
01 .;,;19;""'_ _+-1 C>-4Hf-.:..

02 .:.:18=--_+....-1 '-::>-4.-1_3:. B2

03 .;;11_ _+ ...._/l.;>-4HI-.;..4 B3

DS75161A
This device is also an 8·channel bi·directional transceiver
which is specifically configured to implement the eight
management signal lines of the IEEE·488 bus. This device,
paired with the DS75160A, forms the complete 16·line
interface between the IEEE·488 bus and asingle controller
instrumentation system. In compliance with the system
organization of the management signal lines, the SRO,
NDAC, and NRFD bus port outputs are open collector. In
contrast to the DS75160A, these open collector outputs
are a fixed configuration. The direction control is divided
into three groups. The DAV, NDAC, and NRFD transceiver
directions are controlled by the TE input. The ATN, SRO,
REN, and IFC transceiver directions are controlled by the
DC input. The EOI transceiver direction is a function of
both the TE and DC inputs, as well as the logic level present on the ATN channel. The port connections to the bus
lines have internal terminators identical to the DS75160A.

04 _16_ _+ ....-1 Ii:>--1Hf-B;;.. B7

TABLE OF SIGNAL LINE ABBREVIATIONS
Signal Line

Classification
Control
Signals

Data
110 Ports

Management
Signals

Mnemonic
DC
PE
TE
SC

Bl-BB
01-08
ATN
OAV
EOI
IFC
NOAC
NRFO
REN
SRO

Definition
Direction Control
Pull-Up Enable

9 B8

Devica
OS75161A10S75162A
OS75160A
All
OS75162A

TE

Talk Enable
System Controller
Bus Side of Device
Terminal Side of Device OS75160A
Attention
Data Valid
End or Identify
Interface Clear
OS75161A/OS75162A
Not Data Accepted
Not Ready for Data
Remote Enable
Service Request

TUF/524:)..4

Nota 1:

--a>-

Denotes driver

Nota 2:

~

Denotes receiver

Nota 3: Driver and receiver outputs are totem·pole configurations
Nole 4: The driver outputs of DS75160A can have their active pull·ups
disabled by switching the PE input (pin 11) to the logic low state. This
mode configures the outputs as open collector.

2-62

CC
Logic Diagrams

en
en
..............

(Continued)

en
en
..........

DS75161A

0) 0)
I\) 0

-en

DS75162A

TE

l>l>
C

TE

.......

15

DAV

DAV

en
.....

DAV

DAV

0)

.....

l>

NDAC

NRFD

E01

17

NDAC

16

NRFD

"

E01

TERMINAL

SRO

REN

lFe
DC

13

12

19

18

NOAC

NRFD

NRFD

E01

EDI

TERMINAL

BUS

ATN

NDAC

BUS

ATN

ATN ~----~~Q>--

SRO

SRO

REN

REN ~----~--i~>---"-r-i------------REN

__--~~--------~ATN

~____~~~~-,__--~--------~I~a SRn

.....-+--1I_---------IFC

lFe

lFe ------~_IJ>--

~

SC
TLlF1524J·5

DC
TlIF15243·6

Note 1:

Note 2:

--B>-

4

Denotes driver

Denotes receiver

Note 3: Symbol "OC" specifies open collector output
Note 4: Driver and receiver outputs that are not specified
configurations

2·63

"~C"

are totem·pole

-~~
<,...C

co
,...

Ie
en
c

,... ,...
,....,....
enen
co

II) II)

Absolute Maximum Ratings (Note 1)

OpCi"rating Conditions

,
7.0V
Supply Voltage, Vcc
5.5V
Input Voltage
-65'Cto150'C
Storage Temperature Range
Maximum Power Qissipation* at 25'C
Molded Package
1897mW
300'C
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics

Vcc, Supply Voltage
TA, Ambient Temperature
lou Output Low Current
Bus
Terminal

Min

Max

Units

4.75
0

5.25
70

V
'C

48
16

mA
mA

"Derate molded package 15.2 mW/'C above 25'C.

(Notes 2 and 3)

Parameter

Conditions

Min

Typ

Max

Units

0.8

V

2

V

VIH

High·Level Input Voltage

VIL

Low·Level Input Voltage

VIK

Input Clamp Voltage

VHYS

Input Hysteresis

Bus

VOH

High-Level
Output Voltage

Terminal
Bus (Note 5)

10H = - 800 ,..A
IOH= -5.2mA

VOL

Low-Level
Output Voltage

Terminal
Bus

IOL=16 mA
IOL=48 mA

0.3
0.4

0.5
0.5

V

IIH

High-Level
Input Current

VI=5.5V
VI =2.7V

0.2
0.1

100
20

p.A

IlL

Low-Level
Input Current

VI=0,5V

-10

-100

p.A'

VBIAS

Terminator Bias
Voltage at Bus Port

3.0

3.7

I LOAD

Terminator
Bus Loading
Current

,

-0.8

Ii= -18mA

Terminal and
TE, PE,.DC,
SC Inputs

Driver
Disabled

II(bus) = 0 (No Load)
VI(bUS) = -1.5V to 0.4V
VI(bus) - 0.4V to 2.5V

Bus

Driver
Disabled

mV

2.7
2.5

3.5
3.4

V

2.5
-1.3
0

3.2
2.5
-3.2
2.5
2.5

0
0.7

Vcc = 0, VI(bus) = OV to 2.5V
los

Short-Circuit
Output Current

Terminal
Bus (Note 5)

Icc

Supply Current

DS75160A
DS75161A
DS75l62A

CIN

Bus-Port
Capacitance

Bus

VI = 2V, Vo = OV (Note 4)

V

500

VI(bUS) = 2.5V to 3.7V
VI(bUS) = 3.7V to 5V
VI(bUS) - 5V to 5.5V

-1.5

400

-15
-35

-35
-75

V

mA

40

,..A

-75
-150

mA

Transmit, TE = 2V, PE = 2V, VI = 0.8V
Receive, TE = 0.8V, PE = 2V, VI = O.BV
TE = 0~8V, DC = 0.8V, VI = 0.8V
TE = 0.8V, DC = 0.8V, SC = 2V, VI = 0.8V

85
70
84
85

125
100
125
125

mA

Vcc = 5V or OV, VI = OV to 2V,
f=l MHz

20

30

pF

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed, They are not meant to Imply that the
device should be operated at these limits, The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minImax limits apply across the O'C to + 70'C temperature range and tlie 4.75V t05.25V power supply range. All typical
values are for TA= 25'C and VCC=5.0V.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or illin are so classified on absolute value basis,
Note 4: Only one output at a time should be shorted.
Note 5: This characteristic does not apply to outputs on DS75161A and DS75162A that are open collector.

2-64

cc
en en
..............

Switching Characteristics Vcc = 5.0V ± 5%, TA = O·C to 70·C (Note 1)

en en
Parameter

From

t pLH

Propagation Delay Time,
Low to High Level Output

t pHL

Propagation Delay Time,
High to Low Level Output

Terminal

t pLH

Bus

Propagation Delay Time,
Low to High Level Output
Terminal

Propagation Delay Time,
High to Low Level Output

t pZH

Output Enable Time
to High Level

t pHZ

Output Disable Time
from High Level

t pZL

Output Enable Time
to Low Level

t pLZ

Output Disable Time
from Low Level

tpZH

Output Enable Time
to High Level

t pHZ

Output Disable Time
from High Level

t pZL

Output Enable Time
to Low Level

t pLZ

Output Disable Time
from Low Level

t pHZ

DS75160A
DS75161A
DS75162A
Units
Min Typ Max Min Typ Max Min Typ Max

V L =2.3V
R L =38.3{l
C L =30pF

V L =5.0V
R L =240{l
C L =30pF

10

20

10

20

10

20

ns

14

20

14

20

14

20

ns

14

20

14

20

14

20

ns

TE, DC,
orSC
(Note 2)
(Note 3)

Bus

10

20

10

20

10

20

ns

19

32

23

40

23

40

ns

15

22

15

25

15

25

ns

24

35

28

48

28

48

ns

17

25

17

27

17

27

ns

17

33

18

40

18

40

ns

15

25

22

33

22

33

ns

25

39

28

52

28

52

ns

15

27

20

35

20

35

ns

10

17

NA

NA

ns

10

15

NA

NA

ns

Figure 1
VI=OV
V L =2.3V
RL = 38.3{l
C L =15pF

Figure 1

TE, DC,
orSC
(Note 2)
(Note 3)

VI = 3.0V
VL=OV
R L =3 k{l
C L = 15 pF
Terminal

Figure 1
VI=OV
V L =5V
R L =280{l
C L = 15 pF

Figure 1

Output Pull-Up Enable
Time (DS75160A Only)
Output Pull-Up Disable
Time (DS75160A Only)

PE
(Note 2)

Bus

V I =3V
VL=OV
R L =4BO{l
C L =15 pF

Figure 1

Nole 1: Typical values are forVCC~~.OV and TA =2S'C and are !)leanl for reference only.
Nole 2: Refer to Functional Truth Tables for control input definition.
Note 3: Test configuration should be connected to only one transceiver at a time due to the high current stress caused by the VI voltage source when the out·
put connected to that input becomes active.

Switching Load Configurations
Vl
Q

Vl
TEST
DEVICE

TEST
DEVICE

Rl

DUT
VCo- CDNTRDl

DUT
vco- CDNTRDl

r-fCl*

1~~

-!-I . . .

T

":"

Vc logic high = 3.0V
Vc logic low = OV

Vc logic hlgh=3.0V
Vc logic low = OV

Cl" ,

~ lN914

,~ lN914

~ ~ lN914
"::"

·CL Includes jig and probe capacitance

• CL Includes jig and probe capacitance
FIGURE 1

!' Rl

VI 0 - IN

VI 0 - IN

FIGURE 2

TLlF/5243·7

2-65

-'" -'"

0) 0)

1\)0

»

-

c
en
.......
en

-'"

0)

Figure 2
VI = 3.0V
VL=OV
RL = 480{l
C L =15pF

I

tpZH

Conditions

Figure 1

Bus
t pHL

To

Tl1F1524J.a

-'"

>


Roun f-<>
Roun f-<>

DIN]

DIN4

ROUT4

-d~- 1,~

f-o

1,--

1.SV

1.5V

Input pulse:
tr = tf = 5 ns (10% to 90%!
Freq =,10 MHz (50% duty cycle!
Amplitude = 2.6V

-=1FIGURE 2. Propagation Delay (DIN to DOUT!

2-91

AC Test Circuits and Switching Time Waveforms
Vcc" sv

uv

5Y

Doun

DIE

DDun

ii7E

(Continued)

DO un

DIN1

DOUT4

DON>

Aoun

)

Uk

.

(PROBE)

7D

uv

ON

IPZl
300pF

OUT

1.5Y
1D%

Roun

°IN3

RDUT3

Input pulse:
tr = tf = 5 ns (10% to 90%1
Freq = 5 MHz (50% duty cyclel
-Amplitude = 2.6V

DON4
ROUT4

.,..
FIGURE 3. Propagation Delay (Data Enable to Data Output!

vcc- sv

2.BY

DOUT1

5V

Uk

DIE

24D

1.5V

ON

1.5V

DOUT2

WE
DIN'
DINZ

DIN3

°ODn

"

ROUTt

ROU12

Roun
DIN"

IPLl

IPZl

DOUT4

{PROBEI

)

30pF

15Y

OUT

10%

..,.

Input pulse:
tr = tf =5 ns (10% to 90%1
Freq = 5 MHz (50% duty cy!'lel
Amplitude =2.6V

FIGURE 4. Propagation Delay (Receive/Enable to Receiver Output)

2-92

Section 3
Peripheral/Power
Drivers

TEMPERATURE RANGE
- 55°C to
*DP7310
*DP7311
*DS1611
* DS1612
*DS1613
*DS1614
* DS1631
* DS1632
* DS1633
* DS1634

* DS1687
* DS55451
• DS55452
• DS55453
* DS55454
* DS55461
* DS55462
* DS55463
* DS55464

+ 125°C

O°C to

+ 70°C

DP8310
DP8311
DS3611
DS3612
DS3613
DS3614
DS3616
DS3631
DS3632
DS3633
DS3634
. DS3654
DS3656
DS3658
DS3668
DS3669
DS3680
DS3686
DS3687
DS75450
DS75451
DS75452
DS75453
DS75454
DS75461
DS75462
DS75463
DS75464
MM74C908
MM74C918
AN-213

DESCRIPTION

Octal Latched Peripheral Drivers
Octal Latched Peripheral Drivers
Dual AND Peripheral Driver
Dual NAND Peripheral Driver
Dual OR Peripheral Driver
Dual NOR Peripheral Driver
Bubble Memory Coil Driver
Dual AND CMOS Peripheral Driver
Dual NAND CMOS Peripheral Driver
Dual OR CMOS Peripheral Driver
Dual NOR CMOS Peripheral Driver
Printer Solenoid Driver
Quad Peripheral Driver
Quad High Current Peripheral Driver
Quad High Current Peripheral Driver
Quad High Current Peripheral Driver
Quad Negative Voltage Relay Driver
Dual Positive Voltage Relay Driver
Dual Negative Voltage Relay Driver
Dual AND Peripheral Driver
Dual AND Peripheral Driver
Dual NAND Peripheral Driver
Dual OR Peripheral Driver
Dual NOR Peripheral Driver
Dual AND Peripheral Driver
Dual NAND Peripheral Driver
Dual OR Peripheral Driver
Dual NOR Peripheral Driver
Dual CMOS 30V Driver
Dual CMOS 30V Driver
Safe Operating Areas for Peripheral Drivers

• Also available screened In accordance with MIL:STD-883 Class B. Refer to National Semiconductor's "The Reliability Handbook".

PAGE
NUMBER
3-4
3-4
3-11
3-11
3-11
3-11
3-17
3-24
3-24
3-24
3-24
3-29
3-33
3-35
3-38
3-41
3-44
3-47
3-49
3-51
3-51
3-51
3-51
3-51
3-62
3-62
3-62
3-62
CMOS
CMOS
3-68

PERIPHERAL/POWER DRIVERS
Output High
Voltage (V)

Latch-Up Voltage
(Note 3) (V)

30
30

~

Output Low
Voltage (V)

Output Low
Current (mA)

Propagation
Delay
Typ (ns)

0_5
0.5

100
100

40
40

152
125

100

70

90

8
2

20

13.5

6.6

ON Power Supply
Current (mA),

Drivers/
Package
8

Input
Compatibility
(Logic)

Logic Function
(Driver ON)

Device Number
and Temperature Range
O°C to +70°C
-55°C to +125°C

Note 5

DP8310

DP7310

DP8311

DPi311

TTL

Note 6
Note 7

TTL
TTL

053616

Page
No_
3-4
3-4
3-17

65

30

1.5

600

053656

3-33

0.7

600

2430

4
4

NAND

35

65
65

TTL/L5

70

TTLlL5

NANO

053658

3-35

70

Note 8

1.5

~OO

2000

80

4

TTLlL5

NANO

053668

3-38

70

35

0.7

600

65

4

TTLlL5

ANO

053669

3-41

30

20

0.7

31

55

2

TTL

ANO

0575450

30

20

0.7

300
300'

31

55

2

TTL

ANO

0575451

0555451

30

20

0.7

300

31

55

2

TTL

NANO

0575452

0555452

3-51

30

20

0.7

300

31

55

2

TTL

OR

0575453

0555453

3·51
3-51
3-62

3-51
3-51

30

20

0.7

300

31

55

2

TTL

NOR

0575454

0555454

35
35

30

0.7

300

33

55

2

TTL

ANO

0575461

0555461

30

0.7

300

33

55

2

TTL

NANO

0575462

0555462

35

30

0.7

300

33

55

2

TTL

OR

0575463

0555463

35

30

0.7

300

33

55 .

2

TTL

NOR

0575464

0555464

3·62
3-62
3-62

56

40

1.4

300

150

8

2

CM05

ANO

053631

051631

3-24

56

40

1.4

300

150

8

2

CM05

NANO

053632

051632

3-24

56

40

1.4

300

150

8

2

CM05

OR

053633

051633

3-24

56

40

1.4

300

150

8

2

CM05

NOR

053634

051634

3-24

80

50

0.7

300

75

2

TTL/CM05

ANO

053611

051611

3-11

80

50

0.7

300

125
125

75

2

TTLlCM05

NANP

05~612

051612

3-11

80

50

0.7

300

125

75

2

TTL/CM05

OR

053613

051613

3-11

80
-2.1

50
-60

0.7
-60

300
-50

125
10,000

75
4.4

2
4

TTL/CM05

NOR

053614

051614

3-11 "

TTL/CM05

(Note 4)

053680

(Note 1)
(Note 1)
13.5

56
-56

1.3

300,

1000

28

2

TTL/CM05

NANO

053686

-1.3

300

1000

28

2

TTLlCM05

NANO

053687

15

VCe- 1.8

300

150

0.015

2

CM05

ANO

MM74C908,
MM74C918

3-44
3-47
051687

I

I

I

3-49

CM05
CM05
1000
(Note 1)
(Note 2)
(Note 2)
3-29
45
1.6
250
70
10
053654
Note 1: The 053686, 053687 and 053654 contain an internal inductive fly-back clamp circuit connected from the output to ground. As an example, 053686 driving a relay solenoid connected to 28V would
clamp the output vOltage fly-back transient at 56V caused by the solenoid's stored inductive current. This clamp protects the circuit output and quenches the fly-back.
Note 2: The 083654 is a 10-bit shift register followed by 10 enabled drivers. The input circuit is equivalent to a 4k resistor to ground, and the logic input thresholds are 2.SV and O.8V. The recommended power
supply voltage is 7.5V to 9.5V. The circuit can be cascaded to be a 20 or 30-bit shift register.
Note 3: Latch-up vo~tage is the maximum voltage the output can sustain when switching an inductive load.
Not. 4: 053680 has a differential input circuit.
Not. 5: OP831 0 inverting, positive edge latching.
Not.6: OP8311 inverting, fall through latch.
Note 7: Bubble memory coil driver.
Note 8: 053668 35V, latch-up with output fault protection.

I
I

ap!nD uO!J:>alas

~National·

a

Peripheral/Power Drivers

Semiconductor

DP7310/DP8310/DP7311/DP8311
Octal Latched Peripheral Drivers
General Description
The DP7310/8310, DP7311/8311 Octal Latched Peripheral
Drivers provide the function of latching eight bits of data
with open collector outputs, each driving up to 100mA
DC with an operating voltage range of 30 volts. Both
devices are designed for low input currents, high
input/output voltages, and feature a power up clear (out.
puts off) function.

• Parallel latching or buffering

The DP7310/8310 are positive edge latching. Two active
low write/enable inputs are available for convenient data
bussing without external gating.

Applications

The DP7311/8311 are fall through latches. The active low
strobe input latches d'lja or allows fall through operation
when held at logic "0". The latches are cleared (outputs
off) with a logic "0" on the clear pin.

• Separate active low enables for easy data bussing
• Internal "glitch free" power up clear
• 10% Vce tolerance

• High current high voltage drivers
• Relay drivers
• Lamp drivers
• LED drivers

Features

• TRIAC drivers

• High current, high voltage open collector outputs

• Solenoid drivers

• Low current, high voltage inputs

• Stepper motor drivers

• All outputs simultaneously sink rated current "DC"
with no thermal derating at maximum rated
temperature.

• Level translators
• Fiber-optic LEQ drivers

Connection Diagrams

Dual·ln·Line Package

Dual-ln·Llne Package
WE1

Vee

CUI

Vee

014

WE2

014

STR

013

1S

015

013

015

012

17

016

012

016

011

017

011

017

001

DP73101 16
DPS31 0 15

DiS

001

002

14

DOS

002

003

13

007

003

12

006

004

11

005

GNo

004
GNo

10

OIS
7

DOS
007
006

10

005
TUF5246

TUF5246

Order Number DP7310J, DP7311J,
DP831OJ, DP8311J, DP8310N.
or DP8311N
See NS Package J20A or N20A
3-4

C
"'tJ
.......

Logic Table
DP7310/DP8310
Write
Enable 1
WE 1

OP7311/DP8311

Write
Enable 2
WE2

Data
Input
01 1- 8

Data
Output
D01_8

0

0

1

1

1

1

0

...f"
...f

X
0

Q

0

1

0

-f
...:f

0

0

1

0

1

0

0

1

Q

1

0

1

1

X
X
X

Block Diagram

Data
Input
01 1_ 8

Data
Output
D01 _8

X
0

Q

0

1

0

1

0

0

X

X

1

Clear

Strobe

CLR

STR

X = Don't Care
1 = Outputs Off
0= Outputs On
Q = Pre-existing Output
.E= Positive Edge Transition

Q
Q

DP7310/0P8310

~

DATA (01
IN1)1 :
DATA IN 2
(012)

o-_~l~-4_-f-LA_i
1 LA;H. .

:

C_H-

DATA OUT 2
(002)

.••

••
..
••

DATA IN 8
(Dl8)

~ (001)
DATA OUT 1

o--+-l-__r--L-,

DATA OUT 8
(008)

WRITE ENAr~~11
WRITE ENABLE 2
(WE2)
TUF5246

Bloct<: Diagram

DP7311/0P8311

DATA IN 1
(Dl1)

DATA IN 2
(012)

o-------r--I

DATA OUT 1
(001)

o--+-l--r--'--,

DATA OUT 2
(002)

.• •'.
..

DATA IN 8
(Dl8)

.•

o--+-l--r--'--,

DATA OUT 8
(OOa)

CLEAR
(elR)

STI!!!lE
(STR)

TUF5248

3-5

1

W
.....

o
00
w
.....
o
.......
w
.....

.....

00

w
.....

.....

.....
.....
C")

co

..........

-.....
t:2
o

C")

~

o
.....
C")
.....
Q.

Absolute Maximum Ratings (Note 1)

Operating Conditions

Supply Voltage
7.0V
Input Voltage
35V
Output Voltage
35V
Maximum Power Dissipation' at 25·C
Cavity Package
1821mW
Molded Package
2005mW
-65·Cto + 150·C
Storage Temperature Range
300·C
Lead Temperature (Soldering, 10 seconds)

Supply Voltage {Vce>
Temperature
DP7310/DP7311
DP8310/DP8311
Input Voltage
Output Voltage

Min.

Max.

Units

4.5

5.5

V

-55
0

+125
+70
30
30

·C
·C
V
V

• Derate cavity package 12.1 mWI'C above 25"C; derate molded package
16.0 mWI'C above 25"C.

C

DC Electrical Characteristics
Symbol

Parameter

V,H

Logical "1" Input Voltage

V,L

Logical "0" Input Voltage

VOL

Logical "0" Output Voltage
DP7310/DP7311
DP8310/DP8311

10H

Logical "1" Output Current
DP7310/DP7311
DP8310/DP8311

I'H
I,
I,L

Conditions

Typ.

Max.

2.0

Units
V

0.8

V

Data outputs latched to
logical "0", Vcc = min.
IOL=75ma
IOL=100mA

0.35

0.4
0.5

V
V

Data outputs latched to
logical "1", Vcc=min.
VoH =25V
VoH =30V

2.5

500
250

,..A
,..A

0.1

25

,..A

Logical "1" Input Current

V,H = 2.7V, Vcc == max.
Y,N = 30V, Vcc = max.

1

250

,..A

Logical "0" Input Current

Y,N = OAV, Ycc = max.

-215

-300

,..A

I'N=-12mA

-0.8

-1.5

V

100
100
88
88

125
152
117
125

mA
mA
mA
mA

40
40
25
25

47
57
34
36

mA
mA
mA
mA

Supply Current, Outputs On

Data outputs latched to a
logical "0". AI! inputs are
at logical "1", Vcc=max.

DP731 0
DP8310
. DP7311
DP8311
ICCl

Min.

Input Current at Maximum Input
Voltage

VCla~p Input Clamp Voltage
Icco

DP7310/DP8310, DP7311IDP8311 (Notes 2 and 3)

Supply Current, Outputs Off

Data outputs latched to a
logic "1". Other
conditions same as Icco.

DP7310
DP8310
DP7311.
DP8311

3-6

C

AC Electrical Characteristics
Symbol
tpdO
tpd1

Parameter

Conditions

Min.

Typ.

Max.

Units

High to Low Propagation Delay
Write Enable Input to Output

Figure 1

40

120

ns

Low to High Propagation Delay
Write Enable Input to Output

Figure 1

70

150

ns

tHoLD=Ons
Figure 1

45

20

ns

tpWH'
tpwL

Minimum Write Enable Pulse
W'dth

Figure 1

60

25

ns

tTHL

High to Low Output Transition Time

Figure 1

16

35

ns

tTLH

Low to High Output Transition Time

Figure 1

38

70

ns

CIN

uN" Package Note 4

5

15

pF

Typ.

Max.

Units

Figure 2

30

60

ns

Figure 2

70

100

ns

AC Electrical Characteristics
Symbol

DP7311/DP8311: Vcc=5V, TA=25°C

Parameter

tpdO

High to Low Propagation Delay
Data In to Output

tpd1

Low to High Propagation Delay
Data In to Output

.....
w
.....

o

CO

W

tSETUP Minimum Set·Up Time
Data In to Write Enable Input

i

"'0

DP73101DP8310: VCC = 4.5V, TA = - 55°C to 125°C

tSETUP Minimum Set·Up Time
Data In to Strobe Input

Conditions

Min.

tHoLD=Ons
Figure 2

0

-25

tpwL

Minimum Strobe Enable Pulse Width

Figure 2

60

35

tpdC

Propagation Delay Clear to Data Output

Figure 2

tpwc

Minimum Clear Input Pulse Width

Figure 2

tTHL

High to Low Output Transition Time

Figure 2

tTLH

Low to High Output Transition Time

CIN

Input Capacitance - Any Input

70

ns
ns
135

ns

20

35

ns

Figure 2

38

60

ns

Note 4

5

15

pF

60

25

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Temperature
Range" they are not meant to Imply that the devices should be operated at these limits. The table of "Electrical Characteristics" provides conditions for
actual device operation.
Note 2: Unless otherwise specified mln.lmax. limits apply across the -55'C to +125'C temperature range for the DP7310lDP7311 and across the O'C to
+70'C for the Dp8310/DP8311. All typical values are for TA = 25'C, Vee = 5V.
Note 3: All currents Into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.
Nota 4: Input capacitance Is guaranteed by periodic testing. fTEST =10kHz at 300mV, TA=25'C

3·7

.....

-.....
o
(j

.....

CO
W

.....
.....

,..
,..

('I)

co

Switching Time Waveform

DP7310/DP8310

,..
,..

('I)

1'0

o,..

-

3V
DATA INPUT
OV

('I)

CO

o
,..

3V
WE1 OR WE2

OV ---~--otl

('I)

V+ ---~-..;,L

1'0

c...

OUTPUT

o

VOL

TUF5246

Switching Time Waveform

DP73111DP8311

3V
DATA INPUT

OV
3Y

S'fR
OY

---l---f--J

3V---r--~-----r----~~----~

CUi
OV

Y+
OUTPUT

VOL - - - -

TUF5246·

Switching Time Test Circuits

DP7310/DP8310

DP7311/DP8311

5V

5V

V+ =10V

V+ =10Y

RL=100Q

RL=100Q

OUT

OUT

:;J;
*WE1 = OY WHEN THE INPUT

=

WE2

PULSE GENERATOR CHARACTERISTICS:
Zo=502,lr=lr=5ns

TUF5246

FIGURE 2

FIGURE 1

3·8

CL = 50 pF

TVF5246

C

Typical Applications

"'0

.....
(r.)

DP8310/11 Buffering High Current Device (Notes 1 and 2)

PNP High Current Driver

....
o
....
o
........~
....
....

Q)

NPN High Current Driver

30V MAX.

(r.)

1 OF 8
OUTPUTS

-

v+

30V MAX

-

1 OF 8
OUTPUTS

Q)

(r.)

vTUF5246

TUF5248

1 OF 8
OUTPUTS

TUF5246

Eight Output/Four Output Fiber Optic LED Driver

DP8311 Parallel Outputs (200 mAl Drivers *

DP8311 100mA Drivers

y+
y+

2011mA I
MAX. t

100mA I
MAX. t
1 OF 4
1 OF 8'
OUTPUTS
FAllTHROUGH
MODE

RD

...... lEO TO
FIBER OPTIC

OUTPUTS
FAllTHROUGH
MODE

...... lEO TO
FIBER OPTIC

·PARAllEl ONLY
ADJACENT OUTPUTS

TUF52-46

TUFS246

3-9

,..
,..

('I)

co

Typical Applications

(cont'd)

,....
,..

,....
o
,..

('I)

('I)

+5

CO

o
,..
,....
('I)

a.
c

Digital Controlled 256 Level
Power Supply from 1.2 Volts to 30 Volts

8-Blt Level Translator-Driver

Y+
LOAD OR
OUTPUT PULL-UP

INPUT

Vee

,-aov
·\BIN
1.4VIl1-b

r~~

BOUTI·

ov

VOUT

VIN

·R
0
A
T
A

-1---ov
OP8311

SETS MAX
YOUT

0
U
T
P
U
T
S

+5

STR
WEZ

TUF5246

-SETS VOUT
lUF5246

Reading the State of the Latched Peripherals

200 mA Drive for a 4 Phase Bifilar Stepper Motor

V+

+VSTEPPER
30Y MAX.
DP8310

OATA BUS
IN

D
S
Y
S
T
E

DATA BUS

OUT

A
T
A

S

DP8310

y ADDRESS
S
T 1I0W
E
M 1I0R

M

DM81LS9STRI·STATE
OCTAL
BUFFER

ADDRESS/CE
\lOW

iii iii -HIGH LEVEL INPUT
.....,i-...,......
VOLTAGE MUST NOT
EXCEED Vcc OF THE

·PARALLEL ONLY
ADJACENT OUTPUTS

OM81LS9S

TLIF5246

TUF5246

Nole I: Always use good Vce bypass and ground techniques to suppress transients caused by peripheral loads.
Note 2: Printed circuit board mounting is required If these devices are operated at maximum rated temperature and current (all outputs on DC).

3-10

PeripheraUPower Drivers

~National

a

Semiconductor

081611/083611, 081612/083612, 081613/083613,
0816141083614 Dual Peripheral Drivers
General Description

Features

The DS1611 series of dual peripheral drivers was designed for those applications where a higher breakdown
voltage is required than that provided by the DS75451
series_ The pin outs for the circuits are identical to those
of the DS75451 through DS75454_ The DS1611 series
parts feature high voltage outputs (80V breakdown in
the "OFF" state) as well as high current (300 mA in
the "ON" state)_ Typical applications include power
drivers, relay drivers, lamp drivers, MOS drivers, and
memory drivers.

• 300 mA output current capability per driver

Connection Diagrams

Vee

82

A2

AI

BI
VI
lOP VIEW

High voltage outputs (80V)

• TTL compatible
•

Input clamping diodes

• Choice of logic function

(Dual-In-Line and Metal Can Packages)

Y2

Vee

82

GNU

AI

81
VI
TOP VIEW

Order Number DS1611J-8,
DS3611J-8 or DS3611N

•

A2

Y2

Vee

GND

AI

Order Number DS1612J-8,
DS3612J-8 or DS3612N

B2

A2

81
YI
TOP VIEW

Y2

Vee

82

AZ

V2

GNO

AI

81
VI
TOP VIEW

GND

Order Number DS1613J-8,
DS3613J-8 or DS3613N

Order Number DS1614J-8,
DS3614J-8 or DS3614N

See NS Package J08A or N08A

GNO

GND
TQPVIEW

TOPvrEW

TOPV1EW

Pm411lnellCtrlCillcolltactWllhlhaCUI!.

Pin415 tRller:lllul contacl with thl CUll,

I'ln4,stneleclnCillCDntlctwlthtlirml,

Order Number
DS1611H or DS3611H

Order Number
DS1612H or DS3612H

Order Number
DS1613H or DS3613H

See NS Package H08C

3-11

TQPVIEW

Order Number
DS1614H or DS3614H

Absolute Maximum Ratings
Supply Voltage, VCC
I nput Voltage
Output Voltage (Note 5)
Continuous Output Current
Storage Temperature Range

Operating Conditions

(Note 1)

7.0V
5.5V
80V
300mA
-65~C to +150°C

Supply Voltage (V CC)
DS161X
DS361 X
Temperature (TA)
DS161X
DS361X

Maximum Power Dissipation· at 2SoC
Cavity Package
Molded Package
TO-5 Package
Lead Temperature (Soldering, 10 seconds)

1133mW
1022mW
787mW
300"C

MIN

MAX

UNITS

4.5
4.75

6.5
5.25

V
V

-55
0

+125
+70

°c
°c

'Derate cavity pa~kage 7.6 m~t"C above 25°C; derate molded
flackage 8.2 [J'W/ C above 25 C; derate TO-5 package 5.25 mW/
C above 25 c.

Electrical Characteristics 081611/083611,081612/083612, 081613/083613, 081614/083614 (Notes 2 and 3)
PARAMETER

CONDITIONS

V'H

High Level Input Voltage

(Figure I)

V'L

Low Level Input Voltage

(Figure 2)

V,

Input Clamp Voltage

Vee = Min, I, =-12 mA, (Figure3)

VOL'

Low Level Output Voltage

OS1611, V'L=0.8V

OS1613, V'L =O.SV

Vee = Min.!Figure 1}

OS1614, V'H=2V
OS3611, V'L =0.8V
053612, V'H=2V
OS3613, V'L =O.SV
OS3614. V'H=2V

Output Breakdown Voltage

Vee = Min./Figure I}

Vee

= Max,

V,

UNITS
V
V

-1.2

-1.5

V

10L = 100 rnA

0.2

0.5

V

10L = 300 rnA

0.45

O.S

10L = 100 rnA

0.2

0.5

V
V

10L - 300 mA

0.45

O.S

V

10L = 100 mA

0.2

0.5

V

10L = 300 mA

0.45

0.8

V

10L = 100 mA

0.2

0.5

V

10L = 300 mA

0.45

O.S

V

10L = 100 mA

0.2

0.4

V

10L = 300 mA

0.45

0.7

V
V

10L -100mA

0.2

0.4

10L - 300 mA

0.45

0.7

V

10L = 100mA.

0.2

0.4

V

10L = 300 mA

0.45

0.7

V

10L = 100mA

0.2
0.45

0.4

V
.V

10L = 300mA
OS1611,

V'H = 2V,
10H = 100/JA

OS3611,

V'L = O.SV,
10H = 100pA
Input Current at Maximum

MAX

O.S

V'H = 2V,
10H = 300 /JA

V'L = O.BV,
10H = 300/JA

I,

TYP

2

OS1612, V'H=2V

VOH

MIN

OS1613
OS3613
OS1612,
OS1614
OS3612,
053614

0.7

SO

V

SO

V

80

V

SO

V

= 5.5V, (Figure 2)

1

mA

Input Voltage
I'H

~igh Level Input Current

Vee = Max, V, = 2.4V, (Figure 2)

I'L

Low Level Input Current

Vee

leCH

Supply CUrrent

= Max,

V,

= 0.4V, (Figure 3)
OS1611/
V,

.

-1

= 5V

OS3611
OS1613/

Vee = Max, Outputs

053613

High, (Figures 4 and 5)

OS1612/
V, =OV

053612
051614/
053614

leel

40

/JA

-1.6

mA

11

rnA

14

rnA

14

mA

17

mA

69

mA

73

rnA

71

mA

79

mA

OS1611/

5upply Current

OS3611
V, =OV

OS1613/

Vee = Max, Outputs

OS3613

Low, (Figures 4 and 5)

0516121
OS3612
V, = 5V

051614/
OS3614

3·12

Switching Characteristics

cc
5!l5!l

Vcc = 5.0V, TA = 25°C

~~

OS1611/0S3611, OS1612/0S3612, OS1613/0S3613, OS1614/0S3614
PARAMETER
t po 1

Propagation Delay Time,

Low·To·High Level Output
' 0 '"

200 rnA, e L

= 15 pF,

RL

= 50n,

(Figure 6)

tpDO

MIN

CONOITIONS

Propagation Delay Time,

High-To-Low Level Output
' 0 '"

200 rnA, CL

= 15 pF,

RL

= 50n,

(Figure 6)

OS1611/
OS3611
OS1612/
OS3612
OS1613/
OS3613
OS1614/
OS3614
OS1611/
OS3611
OS1612/
OS3612
OS1613/
OS3613
OS1614/
OS3614

TYP

MAX

UNITS

CC
(f)(f)

130

ns

WW

110

ns

jN ...""""

125

ns

~~

CC

(f)(f)
220

ns

125

ns

110

ns

125

ns

150

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Unless otherwise specified min/max limits apply across the O°C to +70°C temperature range for the OS3611, OS3612, OS3613, OS3614,
and -ssoe to +12Soe temperature range for the OS161 1, OS1612, DS1613 and DS1614. All typical values are for TA = 2SOC and Vee = SV.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Maximum junction temperature is 150°C.
Note 5: Maximum voltage to be applied to either output in the "OFF" state.
Note 6: Delay is measured with a son load to 10V, 1S pF load capacitance, measured from 1.5V input to SO% point on output.

3-13

~~

""",,""""

~~
:I:!~
CC

(f)(f)

WW

~~

~ ...I\)

Schematic Diagrams

(each driver)

DS3611 Dual AND Peripheral Driver
r---~f-----f----------------oV~

.. ~
.,....,...
U;cc
('1)('1)
U)U)

CC
;::(;5

U;U;

CiiCii
cc

Note: 112 01 unit shown.

. 053612 Dual NAND Peripheral Driver

r-----. .----_t_--~t_---:.......---_o

Vee

Nota: 112 ofunitsflown.

053613 Dual OR Peripheral Driver
r---------t-----t---~------------~ov~

A

0---"'-

~--~-------------. .- -__--~--__--~--~GND

No1l: 1l2ofunitsbown.

3-14

Schematic Diagrams

(Continued)
D53614 Dual NOR Peripheral Driver

-------<....- ..- - - - - - - - - < l V "

...---_4>---...

L--~~-_4>_-----_4>--__<....-

. .- - e _ -. .-_4>---"'-0 OUTPUT
AOUTC

It

Emitters

CtOFF(C)

-dt
90%

90%

10%

tF(C)

Ground A Input if B is the driven input or
Ground B if A is the driven Input.

FIGURE 2. Test Set·Up and Timing Waveforms for AOUT and BOUT Collectors

• For AOUTE and BOUTe, A = 3V, B = av;
for BOUTE and AOUTe, A av, B 3V.

=

=

FIGURE 3. Test Set·Up and Timing Waveforms for AOUT and BOUT Emitters

3V=\

; -

'~~ -~'"

R

15.3

VCOIL

BOUTC

---<:>-"-0 OUTPUT

I

90%

AOUTC
OR
BOUTC

AOUTC

10%

VOUTL--------·~----'

~ For AOUTE and BOUTe, A = 3V, B = av;
for BOUTE and AOUTe, A OV, B 3V.

=

=

FIGURE 4. Test Set·Up and Timing Waveforms for AOUT and
3·21

BOUT

Collectors

90%

co
,...
~
en

c

RUN

Vee

3V--"\

} INPUTS

Cf

1.5V---\.

(SEE NOTE 11

053616

t:~(RUN)

R
2k

lN914

lN914

1

---:=:::-r---:::::"\

YOUTH
(SEE NOTE 2)

90%

90%

RUN
OUTPUT

Voun

FIGURE 5. Test Set·Up and Timing Wayeforms for Run Output

I

3V~

VeOiL

}

INPUT

HLO·EN

113.5V)
INPUTS·

VeOIL

R

15.3

HLD·EN

1.:~

d

j.

90%

,tpLZ

90%

AOUTe

BOUTe

--t:>-+-o OUTPUT
AOUTe

Voun - - - - ' - - - - ' " "

"Input Conditions: A = B = 3V

FIGURE 6. Test Set·Up and Timing Wayeforms for AouTe TRI-8TATE

1='=--=--5"-"_-_-_1.0"1'----·1
A~~_ _ _ _ _ _ _ _ _ _ _ _+.--~

L--

. FIGURE 7. AC Switching Characteristics

lOOk

AOUT

A

053616

VOD
COIL
BOUT

DVM

lOOk

FIGURE 8. DC Imbalance Test Circuit
Note 1: Output waveforms may be generated with CS= input, A= B=OV or B= input, A=3V, CS =OV
Note 2:. Reference YOUTH is set at 4V, which includes the active pull-up voltage plus charge-up voltage due to the Internal 5 kll resistor to VCC (typical rise
IIme=12 ns).

3-22

Typical Characteristics

IFvs VFof Output
Clamp Diode Over Ambient
Temperature

..
w

900

co

BOD

Ci
~

700

"

lD

==

w
Im
>m

~

9, 10, 15, 16

9, 10, 15, 16 ..
DATA BUS

)

CONTR~L ~

OS3658

r

LEVELS

L3*

Lf

OS3658

~
7

-

EN

~.

- 8

14

14

--+

..l!, 5, 12, 13

EN
4,5,12,13

"L1, L2, L3, L4 are the windings of a blfllar stepping motor.
" " VMOTOR is the supply voltage of the motor.

3-37

cor----------------------------------------------------------------,

~ ~National
~ ~ Semiconductor

Peripheral/Power Drivers
PRELIMINARY

053668 Quad Fault Protected Peripheral-Driver
General Description

Applications

The OS3668 quad peripheral driver is designed for those
applications where low operating power, high brea~down
voltage, high output current and low output ON voltage are
required. Unlike most peripheral drivers available, a unique
fault protection circuit is incorporated on each output. When
the load current exceeds 1.0 A (approximately) on any output for more than a built-in delay time, nominally 25 p.s, that
output will be shut off by its protection circuitry with no effect
on other outputs. This condition will prevail until that protection circuitry is reset by toggling the corresponding input or
the enable pin low for at least 0.5 p.s. The 25 p.s built-in
delay is provided to ensure that the protection circuitry is not
triggered by turn-on surge currents associated with certain
kinds of loads.

•
•
•
•
•
•
•
•
•

The OS3668's inputs combine TIL compatibility with high
input impedance. In fact, its extreme low input current allows it to be driven directly by a MOS device. The outputs
are capable of sinking 600 mA each and offer- a 70V breakdown. However, for inductive loads the output should 'be
clamped to 35V or less to avoid latch up during turn off
(inductive fly-back protection - refer AN-213). An on-Chip
clamp diode capable of handling 800 mA is provided at
each output for this purpose. In addition, the OS3668 incorporates circuitry that guarantees glitch-free power up or
dpwn operation and a fail-safe feature which puts the output
in a high impedance state when the input is open.
The molded package is specifically constructed to allow increased power dissipation over conventional packages. The
four ground pins are directly connected to the device chip
with a special copper· lead frame. When the quad driver is
soldered into a PC board, the power rating of the dev.ice
improves significantly.

Relay drivers
Solenoid drivers
Hammer drivers
Stepping motor drivers
Triac drivers
LED drivers
High current, high voltage drivers
Level translators
Fiber optic LEO drivers

Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Output fault protection
High impedance TIL compatible inputs
High output current - 600 mA per output
No outpul.latch-up at 35V
Low output ON voltage (550 mV typ @ 600 mAl
High breakdown voltage (70V)
Open collector outputs
Output clamp diodes for inductive fly-back protection
NPN inputs for minimal input currents (1 /LA typical)
Low operating power
Standard 5Vpower supply
Power up/down protection
Fail-safe operation .
2W power package
Pin-for-pin compatible with SN75437

Truth Table

C0r:-nection Diagram *
_ Dual-In-Llne Package
INA

IN8

EN

GND

GND

vee

IN C

IN D

IN

EN

OUT

H
L
H
L

H
H
L
L

Z
Z
Z

L

H=High state
L=Low state
Z = High impedance state

DUTA CLAMP lOUTS

GND

GND

OUT C CLAMP 2 OUT D

Order Number DS3668N
See NS Package N16A

TOP VIEW
TL/F/5225-1

• See Page 3 for the detail of output protection.

3·38

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Supply Voltage

7.0V

Input Voltage

15V
70V

Output Voltage
Continuous Power' Dissipation
@25·C Free-Air (Note 5)

Supply Voltage
Ambient Temperature

Min
4.75
0

Max
5.25
70

Units
V
·C

2075mW
-65·C to + 150·C
300·C
Lead Temperature (Soldering, 10 seconds)

Storage Temperature Range

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Min

Conditions

VIH

Input High Voltage

VIL

Input Low Voltage

IIH

Input High Current

VIN=5.25V, Vcc=5.25V

IlL

Input Low Current

VIN=0.4V

VIK

Input Clamp Voltage

11= -12 mA

VOL

Output Low Voltage

Typ

Max

2.0

Units
V

O.B

V

1.0

20

,...A

±10

,...A

-O.B

-1.5

V

IL =300 mA

0.2

0.7

V

IL = 600 mA (Note 4)

0.55

1.5

V

100

/LA

ICEX

Output Leakage Current

VCE=70V, VIN=O.BV

VF

Diode Forward Voltage

IF=BOO mA

1.2

V

IR

Diode Leakage Current

VR=70V

Icc

Supply Current

All Inputs High

62

All Inputs Low

20

mA

ITH

Protection Circuit
Threshold Current

1

A

Switching Characteristics
Symbol

Parameter

100

,...A

BO

mA

(Note 2)
Conditions

Min

Typ

Max

Units

tHL

Turn On Delay

RL =600, VL =30V

300

ns

tLH

Turn Off Delay

RL =600, VL =30V

2000

ns

tFZ

Protection Enable Delay
(after Detection of fault)

25

,...s

tRL

Input Low Time For
Protection Circuit Reset

1.0

/Ls

Note t: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified. minimax limits apply across the O'C to + 70'C temperature range and the 4.75V to 5.25V power supply range. All typical,
values are for TA=25'C and Vcc=5.0V.
Note 3: All currents Into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are referenced to ground, unless

otherwise specilied. All values shown as max or min are so classified on absolute value basis.
Note 4: All sections of this quad circuit may conduct rated current simultaneously; however. power dissipation averaged over a short interval of time must fall
within specilied continuous dissipation ratings.
Note 5: For operation over 25'C free-air temperature. derate linearly to 1328 mW @ 70'C @ the rate of 16.6 mWrC.
\

3-39

AC Test Circuit
Vee

Switching Waveforms
3tiV

600
INPUT

3V~'5V
·1.5V
OV

L
~

30V
OUTPUT VoL~

r

90%

TL/F/5225-3
TL/F/5225-2

'Includes probe and jig capacitance

Typical Application
Stepping Motor Driver

-

5V

tll
Ll*

~
2

L2*

.,

.

::0

:Ii

.,~
~

.~
9, 10, 15, 16t.

DATA BUS

,

0$3668

L3*

~
7

- ....!!..--

14

-

8

EN

~,5,12,13

TLlF/5225-4

'L1, L2, L3, L4 are the windings 01 a bililar stepping motor.
"VMOTOR is the supply voltage 01 the motor.

Protection Circuit Block Diagram
INPUT

OUTPUT

ENABLE

CURRENT
SENSING
CIRCUITRY

TLlF/5225-5

3-40

~National

Peripheral/Power Drivers

~ Semiconductor

PRELIMINARY

053669 Quad High Current Peripheral Driver
General Description
The DS3669 is a non-inverting quad peripheral driver
similar to the DS365B. These drivers are designed for
those applications where low operating power, high
breakdown voltage, high output current and low output
ON voltage are required. A unique input circuit combines
TTL compatibility with high impedance. In fact, its extreme low input current allows it to be driven directly by a
CMOS device.
The outputs are capable of sinking 600 rnA each and offer
a 70V breakdown. However, for inductive loads the output
should be clamped to 35V or less to avoid latch-up during
turn off (inductive fly back protection-refer AN-213). An
on-chip clamp diode capable of handling BOO rnA is provided at each output for this purpose_ In addition, the
DS3669 incorporates circuitry that guarantees glitch-free
power up or down operation.
The molded package is specifically constructed to allow
increased power dissipation over conventional packages.
The four ground pins are directly connected to the device
chip with a special copper lead frame. When the quad
driver is soldered into a PC board, the power rating of the
device improves Significantly.

Applications
•
•
•
•

Relay drivers
Lamp drivers
Solenoid drivers
Hammer drivers

Connection Diagram

•
•
•
•
•
•

Stepping motor drivers
Triac drivers
LED drivers
High current, high voltage drivers
Level translators
Fiber optic LED drivers

Features
•
•
•
•

Single saturated transistor outputs
Low standby power, 10 mW typical
High impedance TTL compatible inputs
Outputs may be tied together for increased current
capacity

• High output current
600 rnA per output
2.4A per package
• No output latch-up at 35V
• Low output ON voltage (350 mV typ @ 600 rnA)
• High breakdown voltage (70V)
• Open collector outputs
• Output clamp diodes for inductive fly back protection
• NPN inputs for minimal input currents (1 p.A typical)
• Low operating power
• Standard 5V power supply
• Power up/down protection
• 2W power package

Truth Table

Dual-In-Line Package
IN A

IN B

EN

GND

GND

Vee

IN C

IN 0

IN

EN

OUT

L
H
L
H

H
H
L
L

Z
Z
Z

L

H = High state
L=Low state
Z = High Impedance state

OUT A CLAMP lOUT B

GND
GND
TOP VIEW

OUTC CLAMP 2 OUT 0

Order Number DS3669N
See NS Package N16A
3-41

I
c

Absolute Maximum Ratings (Note 1)

Operating Conditions

7.0V
Supply Voltage
15V
Input Voltage
Output Voltage
70V
1.5A
Output Current
Continuous Power Dissipation
2075mW
@ 25·C Free·Air (Note 5)
-55·Cta + 150·C
Storage Temperature Range
300·C
Lead Temperature (Soldering, 10 seconds)

Supply Voltage
Ambient Temperature

Min
4.75
0

Max
5.25
70

Units
V
·C

I

Electrical Characteristics (Notes 2 and 3)
Symbol

Parameter

Conditions

VIH

Input High Voltage

VIL

Input Low Voltage

IIH

Input High Current

IlL

Input Low Current

VIN=O.4V

VIK

Input Clamp Voltage

11= -12mA

VOL

Output Low Voltage

ICEX

Output Leakage Current

VF

Diode Forward Voltage

IF=SOO mA

IR

Diode Leakage Current

VR=70V

Icc

Supply Current

All Inputs Low
EN=2.0V
All Inputs High

Min

Parameter

tHL

Turn On Delay

tLH

Turn Off Delay

Max

Units

O.S

V

10

p.A

± 10

p.A

2.0

V

1.0

VIN = 5.25V, VCC = 5.25V

-O.S
0.2
0.35

IL =300mA
. IL - 600 mA (Note 4)
VCE = 70V, VIN = 2V,'
VEN=O.SV

1.0

-1.5

V

0.4
0.7

V
V

100

·p.A

1.6

V

100

p.A

50

65

mA

2

4

mA

-

Switching Characteristics (Note 2)
Symbol

Typ

Conditions

Min

Typ

Max

Units

RL=600, VL=30V

226

500

ns

RL =600, VL =30V

2430

SOOO

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the

device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minImax limits apply across theO'C to + 70'C temperature range and the 4.7SV to S.2SV power supply range. All typical
values are for TA =2S'C and VCC =S.OV.
Nots 3: All currents into device pins are shown as positive; all currents out of device pins afB shown as negative; all voltages are referenced to ground, unless
otherwise specified. All values shown as max or min afB so classified on absolute value basis.

Nota 4: All sections of this quad circuit may conduct rated current simultaneously; however, power dissipation averaged over ashort Interval of time must fall
within specified continuous dissipation ratings.

Nota 5: For operation over 2S'C free·alr temperature, derate linearly to 1328 mW @70'C @the rate of 16.6 mW/·C.

3-42

Switching Waveforms

AC Test Circuit

Vee

30V

6011

oV
OUT

~4,

30V
OUTPUT
VOL

30 pF*

-+-"....- - - h

5, 12, 1 3 1

'Includes probe and jig capacitance

Typical Applications
Stepping Motor Driver

Lamp Driver

5V

5V

t11

I""

- -1

,.J-!..

2

LZ*

'"~

9, 10, 15, 16

~

DATA BUS

'"
>'"

~

~

)
r

9,10,15,16
CONTROL
LEVELS

OS3669
L3*

A
1-.(

053669

~
7

14
EN

-

a

~*

-

14
~EN

4,5,12,13

~,5,12,13

'l1, l2, l3, l4 are the windings of a blfilar stepping motor,
"VMOTOA is the supply voltage of the motor.

3·43

v+

o

,~ ~National

, ('I)

en

o

a

Peripheral/Power Drivers

,Semiconductor

083680 Quad Negative Voltage Relay Driver
General Description
The DS3680 is a quad high voltage negative relay driver
designed to operate over wide ranges of supply voltage,
common-mode voltage, and ambient temperature, with
50 mA sink capability. These drivers are intended for
switching the ground end of loads which are directly connected to the negative supply, such as in telephone relay
systems.
Since there may be considerable noise and IR drop between logic ground and' negative supply ground in many
applications, these drivers are designed to operate with a
high common-mode range (± 20V referenced to negative
supply ground). Each driver has a common-mode range
separate from the other drivers in the package, which permits input signals from more than one element of the
system.

The driver outputs Incorporate transient suppression
clamp networks, which eliminate the need for external
'networks when used In applications of switching inductive loads. A fall-safe feature is incorporated to insure
that, if the VON input or both inputs are open, the driver will
be OFF.

Features

With low differential input current requirements (typically
100 p,A), these drivers are compatible with TTL, LS and
CMOS logic. Differential inputs permit either inverting or
non-Inverting operation.

•
•
•
•
•
•
•

- 10V to - 60V operation
Quad 50 mA sink capability
TTLILSICMOS or voltage comparator input
High input common-mode voltage range
Very low input current
Fail-safe disconnect feature
Built-in output clamp diode

Connection Diagram

Logic Diagram

Dual-In-Line Package

U

~GNO

AON

...!.

AOFF

..2.

.!l.A

BOFF...!

.!!.a

BON...!

.!.!.C

CON...!

.!!!oo

COFF...!!.

!.VEC

OOFF..2.

.LOON

aON~
BOFF~B

OON~
OOFF~O

TOP VIEW

Order Number DS3680J or DS3680N
See NS Package J14A or N14A'

3-44

Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions
Min

Supply Voltage: GND to V EE Input Voltage: Input to GND
Logic ON Voltage: VON
Referenced to VOFF
Logic OFF Voltage: VON
Referenced to VOFF
Temperature Range

Supply Voltage: GND to VEE -, and Any Pin
Positive Input Voltage: Input to GND
Negative Input Voltage: Input to VEE Differential Input Voltage: VON to VOFF
Inductive Load

-70V
20V
-5V
±20V
LLS5h
ILs50mA
-100mA
-65°Cto + 150°c

Output Current
Storage Temperature
Maximum Power Dissipation' at 25°C
1433mW
Cavity Package
1398mW
Molded Package
Lead Temperature(Soldering, 10 seconds)
300°C
'Derate cavity package 9.6 mWl'C above 25'C; derate molded package
11.2 mW/'C above 25'C.

Max

Units

-10
-20

-60
20

V
V

2

20

V

-20
-25

0.8
85

V
°C

Electrical Characteristics (Notes 2 and 3)
Parameter

Conditions

Min

Typ

Max

Units

V IH

Logic "1" Input Voltage

V IL

Logic "0" Input Voltage

IINH

Logic "1" Input Current

VIN =2V
VIN =7V

IINL

Logic "0" Input Current

VIN =O.4V
VIN = -7V

-0.01
-1

VOL

Output ON Voltage

10L =50 mA

-1.6

-2.1

V

10FF

Output Leakage

VOUT=V EE -

-2

-100

p.A

I FS

Fail-Safe Output Leakage

VOUT=VEE(Inputs Open)

-2

-100

p.A

2

100

p.A

-2

-1.2

V

1.2

V

2.0

1.3

V

1.3

0.8

V

40
375

100
1000

p.A
p.A

-5
-100

p.A
p.A

I LC

Output Clamp Leakage Current

VouT=GND

Vc

Output Clamp Voltage

ICLAMP= -50 mA
Referenced to VEE -

Vp

Positive Output Clamp Voltage

ICLAMP =50 mA
Referenced to GND

IEE(ON)

ON Supply Current

All Drivers ON

-2

-4.4

mA

All Drivers OFF

-1

-100

p.A

L=1h, RL=1k,
VIN = 3V Pulse

1

10

p's

L=1h, RL=1k,
VIN = 3V Pulse

1

10

P.s

1

Cu~rent

IEE(OFF)

OFF Supply

tpO(ON)

Propagation Delay to

tpO(OFF)

Propagation Delay to Driver OFF

D~iver

ON

0.9

Nole 1: "Absolute Maximum Rallngs" are those values beyond which the safety of the device cannot be guaranteed. Except for"Ope,atlng Temperature Range··,
they are not meant to Imply that the device should be operated at these limits. The tabie of "Electrical Chara,teristlcs" provides conditions for actual device
operation.
Nole 2: Unless otherwise specified,~he minimax limits of the table of "Electrical Characteristics" appiy within the range of the tabie of "Operating Conditions".
All typical values are given for VEE = 52V, and TA = 25'C.
Nole 3: All current Into device pins shown as positive, out of the device as negative. All voltages are referenced to ground uniess otherwise noted.

3-45

C

en

(.)

0)
(X)

0

i

Schematic Diagrams

~

C

----l
I
I

VON

I
I

I

..............._~~I--OvOUT

_ _ _ _ -1

VON

15k

GNO

(1/4 CIRCUIT SHOWN)

3-46

~National

a

Peripheral/Power Drivers

Semiconductor

053686 Dual Positive Voltage Relay Driver
General Description
The DS3686 is a high voltage/current positive voltage
relay driver having many features not available in present
relay drivers.

current levels-base drive for the output transistor is
obtained from the load in proportion to the required
loading conditions. Typical Vee power with both
outputs "ON" is 90 mW.

PNP inputs provide both TTL/LS compatibility and
high input impedance for low input loading.

The circuit also features output transistor protection if
the Vee supply is lost by forcing the output into the
high impedance "OFF" state with the same breakdown
levels as when Vee was applied.

Output leakage is specified over temperature at an out,
put voltage of 54V. Minimum output breakdown (ac/
latch breakdown) is specified over temperature at 5 mAo
This clearly defines the actual breakdown of the device
since the circuit has incorporated in it an internal
reference which does not allow output breakdown
'latching found in existing relay drivers. Additionally.
this internal reference circuit feature will eliminate the
need in most cases of an external clamping (inductive
transient voltage protection) diode. When the output is
turned "OFF" by input logic conditions the resulting
inductive voltage transient seen at the output is de tected
by an internal zener reference. The reference'then
momentarily activates the output transistor long enough
so that the relay energy is discharged. This feature
eliminates the need of external circuit protection com,
ponents and insures output transistor protection.

Features
•
•
•
•
•

TTL/LS/eMOS compatible inputs
High impedance inputs (PNP's)
High ?utput voltage breakdown (65V typ)
High output current capability (300 mA max)
Internal protection circuit eliminates need for output
protection diode

• Output breakdown protection if Vee supply is lost
• Low Vee power dissipation (90 mW (typ) both
outputs "ON")
• Voltage and current levels compatible for use in
telephone relay applications

The outputs are Darlington connected transistors. which
allow high current operation at low internal Vee

Connection Diagrams
Dual·ln-Line Package

Metal Can Package

Vee

Vee

82

A2

X2

Pin 4 is in electrical contact with the case

AI

B1

Xl

GND

TOPVIEW

Order Number DS3686H
See NS Package H08C

Order Number DS3686J·8 or DS3686N
See NS Package J08A or NoaA

Schematic Diagram

Truth Table
Positive logic: AB = X

",-"""-"""-0

OUTPUT

INPUT A
INPUT B

A

B

OUTPUT X

a

0
0
1
1

1

1

0--+--1

ZENER

0
1

£DUIVALENT

Logic "0" output "ON"
Logic "I" output "OFF"

L - - _ - + _ - + _ - - - - <......-o GND

3·47

1
1
0

IIen
C

Absolute Maximum Raiings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Maximum Power Dissipation' at 2S·C
Cavity Package
Molded Package
TO·S Package
Lead Temperature (Soldering, 10 seconds)

Operating Conditions

(Note 1)

7V
lSV
S6V
--6SoC to +1S0°C

Supply Voltage, Vcc
Temperature, T A

MIN
4.7S
0

MAX
S.2S
+70

UNITS
V
°c

TYP

MAX

UNITS

0.01

40

/1 A

0.8

V

1133 mW
1022mW
787mW
300°C

°Derate cavity package 7.6 mWt"C above 2S·C; derate molded
package 8.2 mW,·C above 2SoC; derate TOoS package S.2 mW,
·C above 2SoC ..

Electrical Characteristics

(Notes 2 and 3)
CONDITIONS

PARAMETER

MIN

IlL

Logical "0" Input Current

= 180n, VL = 54V, Vo -;:; 2.5V
VCC = Max, VIN = 5.5V
RL = 180n, VL = 54V, Vo -;:; 53.8V
Vce = Max, VIN =O.4V

VeD

Input Clamp Voltage

Vee

= 5V,

VOH

Output Breakdown

Vee

= Max,

IOH

Output Leakage

Vec = Max, VIN

VOL

Output ON Voltage

Vee = Min, IDS3686 IIOL = 100 mA
IIOL - 300 mA
VIN = 2.4V

VIH
.IIH
VIL

Logical "1" Input Voltage

Logical "0" Input Voltage

ICe(l)

Supply Current (Both Drivers)

Vec

lee(O)

Supply Current (Both Drivers)

Vec

tpDO

flropagation Delay to a Logical "0"

CL

VIN

= -12 mA, TA = 25°C

= OV,

lOUT

= 5 mA

56

= 0.4V, VOUT = 54V

= Max, VIN '" OV, Outputs Open
= Max, VIN = 3V, Outputs Open

= 15 pF, VL = 10V, RL = 50n,

= 25°C, Vee = 5V
CL = 15 pF, VL = 10V,
-TA = 25 °C, VCC ='5V

(Output Turn ON)
tpDl

ICLAMP

TA

Propagation Delay to a Logical "1"
(Output Turn OFF)

RL

V

2.0

RL

Logical "1" Input Current

= 50n,

-150

-250

-1.0

-1.5

/1 A
V
V

65
0.5

250

0.85

1.0

V

1.0

1.2

V

2

4

mA

18

28

mA

/1A

50

ns

1

/1S

Note 1: "Absolute Maximum Ratings" are thosa values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Not. 2: °Unless otherwise specified min/max limits apply across the DoC to +70o C range for the 053686. All typicals are given for VCC = 5V and
TA=25 C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all vpltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.

AC Test Circuit and Switching Time Waveforms

vcr

Vl

~

lOV

3V
>

.:

INPUT
PULSE
GENERATOR

(NOTE 11

RL' 50

I

,v

CIRCUIT
UNOER
TEST

'.,1,

~'-Cl''''F
TINOTEz(

Nota 1: The pulse generator has the following characteristics:
PRR =100 kHz, SO% duty cycle, ZOUT '" son, tr = If $ 10 ns.
Nota 2: CL includes probe and jig capacitance.

3-48

om"

~1'5V.

~ t5~ ~
\

'-. ~r,if

1.5V\

VOL------·~-----~·

.
~ Semiconductor
~National

Peripheral/Power Drivers

081687/083687 Negative Voltage Relay Driver
General Description
The 051687/053687 is a high voltage/current negative
voltage relay driver having many features not available
in present relay drivers.

allow high current operation at low internal Vcc
current levels-base drive for the output transistor IS
obtained from the load in proportion to the required
loading conditions. Typical Vee power with both
outputs "ON" is 90 mW.

PNP inputs provide both TTLlL5 compatibility and
high input impedance for low input loading.

The circuit also features output transistor protection if
the Vee supply is lost by forcing the output into the
high impedance "OFF" state with the same breakdown
levels as when Vee was applied.

Output leakage is specified over temperature at an out·
put voltage of -54V. Minimum output breakdown (acl
latch breakdown) is specified over temperature at -5 mAo
This clearly defines the actual breakdown of the device
since the circuit has incorporated in it an internal
reference which does not allow output breakdown
latching found in existing relay drivers. Additionally,
this internal reference circuit feature will el iminate the
need in most cases of an external clamping (inductive
transient voltage protection) diode. When the output is
turned "OF F" by input logic conditions the resulting
inductive voltage transient seen at the output is detected
by an internal zener reference. The reference then
momentarily activates the output transistor long enough
so that the relay energy is discharged. This feature
eliminates the need of external circuit protection components and insures output transistor protection.

Features
•
•
•
•
•

TTLlL5/CM05 compatible inputs
High impedance inputs (PNP's)
High output voltage breakdown (-65V typ)
High output current capability (300 mA max)
Internal protection circuit eliminates need for output
protection diode
• Output breakdown protection if Vee supply is lost
• Low Vee power dissipation (90 mW (typ) both
outputs "ON ")

•
The outputs are Darlington connected transistors, which

Voltalie and current levels compatible for use in
telephone relay applications

Connection Diagrams
Dual-I "-line Package

Metal Can Package

Vee,

B2

A2

)(2

Al

Bt

Xt

GND

vee

GND
TOP VIEW

Pin 4 is in electrical contact with the case

TOPV,EW

Order Number DS1687H
or DS3687H
See NS Package HOSC

Order Number DS1687J-S,
DS3687J·S or DS36S7N
See NS Package JOSA or NOSA

Schematic Diagram

Truth Table

r--.--------<> Vee
Positive logic' AS = X
INPUT A

INPUT B

A

S

0

,
,

0
0

0

,

,

Logic "0" output "ON"
Logic "1" output "OFF"
'---+---~__<> OUTPUT

3·49

OUTPUT X

,
,
,

0

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range
Maximum Power Dissipation' at 26°C
Cavity Package
Molded Package
TO-5 Package
Lead Temperature (Soldering, 10 seconds)

7V
15V
56V
--65"c to +150°C

Electrical Characteristics

(Notes 2 and 3)

Supply Voltaga, VCC
. DS1687
DS3687
Temperature, T A
DS1687
DS3687

1133 mW
1022mW
787mW

VIH
IIH

Logical "1" Input Current

VIL

Logical "0" Input Voltage

IlL

Logical "0" Input Current·

VCC = Max, VIN

VCD

Input Clamp Voltage

VCC = 5V, ICLAMP = -12 mA, TA = 25°C

VOH

Output Breakdown

VCC = Max, VIN = OV, lOUT = -5 mA

IOH

Output Leakage

VCC = Max, VIN = OV, VOUT

VOL

Output ON Voltage

Supply Current (Both Drivers)

5.6
5.25

V

+125
+70

V

°c
°c

TYP

MAX

UNITS
V

Vce = Max, VIN = 5.5V

1.0
0.8

V

=O.4V

-150

-250

/JA'

-1.0

-1.5

-56

= -54V

/JA

-65

V

V

-0.5

-250

/JA

IOL = -l00mA

-0.9

"':1.1

V

IOL = -300mA

-1.0

-1.3

V

IOL = -100mA

-0.9

-1.0

V

IOL = -300 mA

-1.0

-1.2

VCC = Max, VIN = OV, Outputs Open

2

4

mA

VCC = Max, VIN = 3V, Outputs Open

18

28

mA

= -lOV,
TA = 25°C, VCC = 5V

50

ns

1.0

/Js

VIN = 2V

ICC(O)

4.5
4.76

2.0

Vcc=Min,

Supply Current (Both Drivers)

UNITS

-55
0

MIN

CONDITIONS

Logical '1" Input Voltage

I'CC(1)

MAX

'Derate cavity pa'1,kage 7.6 mV;!loc above 25°C; derate molded
package 8.2 omWI C above 25 C; derate TO·S package 5.2 mWI
°c above 25 C.

30etC

PARAMETER

MIN

DS1687
DS3687

tPD(ON) Propagation Delay to a Logical "0"
(Output Turn ON)

CL = 15 pF, VL

tPD(OFF) Propagation Delay to a Logical "1"
(Output Turn OFF)

CL = 15 pF, VL = -10V, RL = son,
TA

RL = 50n,

= 25°C, VCC= 5V

V

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Unless otherwise specified minImax limits apply'across the -55"c to +125°C temperature range for the DS1687 and across the etc to
+70°C range for the DS3687. AlIlVpicals are given for VCC =6V and TA =25°C.
Note 3: All currents into device pins shown as positive, out of deVice pins as' negative, all voltages referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.

AC Test Circuit and Switching Time Waveforms

vecf'v

~
GENERATOR
INOTE 11

'v 0--

Vl

~

-IOV

-T

3V
INPUT

RL "50

CIRCUIT
UNDER
TEU

-'-CL"""

i-

INDTE
"

Note 1: The pulse generator has the following characteristics:
PRR = 1 MHz, 50% duty cycle, ZOUT '" 50n, tr =·tf ~ 10 ns.
Note 2: CL includes probe and jig capacitance.

, . . . . - - - - - -...

~I.5V

I.5v\\.____

·~~7~ ~-t

~National

a

Peripheral/Power Drivers

Semiconductor

0555450/0575450 Series Dual Peripheral Drivers
General Description
The 0555450/0575450 series of dual peripheral drivers
are a family of versatile devices designed for use in
systems that use TTL logic. Typical applications include
high speed logic buffers. power drivers. relay drivers.
lamp drivers. M05 drivers. bus drivers and memory
drivers.
The 0575450 is a general purpose device featuring two
standard 5eries 54/74 TTL gates and two uncommitted.
high current. high voltage NPN transistors. The device
offers the system designer the flexibility of tailoring the
circuit to the application.
The 0555451/0575451.0555452/0575452.0555453/
0575453 and 0555454/0575454 are dual peripheral

Connection Diagrams

ANO. NANO. OR and NOR drivers. respectively. (positive logic) with the output of the logic gates internally
connected to the bases of the NPN output transistors.

Features
•
•
•
•
•
•
•
•

300 mA output current capability
High voltage outputs
No output latch-up at 20V
High speed switching
Choice of logic function
TTL compatible diode-clamped inputs
5tandard supply voltages
Replaces TI "A" and "S" series

(Oual-In-Line and Metal Can Packages)

"

Order Number DS75450J or DS75450N
See NS Package J14A or N14A
Vee

82

A2

YZ

TOPVIEW

Order Number DS55451J-8,
DS75451J-8 or DS75451N

Vee

TOPVIEW

A2

yz

TOP VIEW

Order Number DS55452J-8, Order Number DS55453J-8,
DS75452J-8 or DS75452N
DS75453J-8 or DS75453N
See NS Package J08A or N08A
Vee

GNO

82

82

AZ

V2

TOPVIEW

Order Number DS55454J-8,
DS75454J-8 or DS75454N

Vcc

G'.

TOP VIEW

G••
TOPVIEW

TOPVIEW

PJn4illDllewlulcDnuctl'iithdl.cnB.

I'ln4illnller:trlulcantlClWllhth8t111.

Pi,,4ilinelllcttical;ontBctwiththtCll$'.

Order Number
DS55451 H or DS75451 H

Vee

Order Number
Order Number
DS55452H or DS75452H
DS55453H or DS75453H
See NS Package H08C
3-51

G••
TOPVIEW
Pin4Qln!leetnWcontlClWlththtclS'.

Order Number
DS55454H or DS75454H

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Supply Voltage,(Vcc)
OS5545X
OS7545X

Supply Voltage, (VCC) (Note 2)
7.0V
I nput Voltage
5.5V
Inter-emitter Voltage (Note 3)
5.5V
VCC·to.Substrat~ Voltage
OS75450
35V
Colleetor-to·Substrate Voltage
OS75450
35V
Colleetor·Base Voltage
OS75450
35V
Collector-Emitter Voltage (Note 4)
0575450
30V
Emitter-Base Voltage
OS75450
5.0V
Output Voltage (Note 5)
OS55451/0S75451, OS55452/0S75452,
30V
OS55453/0S75453,OS55454/0S75454
Collector Current (Note 6)
OS75450
300 rnA
Output Current (Note 6)
OS55451/0S75451,OS55452/0S75452,
300 rnA
OS55453/0S75453,OS55454/0S75454 °
OS75450 Maximum Power OisslpationO at 25 C
Cav ity Package
1308m~
Molded Package
1207mW
0575451/2/3/4 Maximum Power Dissipation t at 25°C
Cavity Package
1090 mW
Molded Package
957mW
TO-5 Package
760mW
-es°C to +150°C
Storage Temperature Range
260°C
Lead Temperature (Soldering, 10 seconds)

Electrical Characteristics
PARAMETER

(Note 7)

MIN

MAX

4.5
4.75

5.5
5.25

UNITS

V
V
e

Temperature, (TA)
OS5545X
OS7545X

-55
0

°c
°c

+125
+70

°Oerate cavity pagkage 8.7 mY"/C above 25°C; derate molded
package 9.7 mW/ C above 25 C.
tOerate cavity pa'i,kage 7.3 mVj/C above 25°C; derate molded
package 7.7 omW/ C above 25 C; derate TO-S package 5.1 mW/
°c above 25 C.

OS75450 (Notes 8 and 9)

I

I MIN I TVP I MAX I UNITS

CONDITIONS

TTL GATES
High Level Input Voltage

(Figure 11

V'L

low Level Input Voltage

(Figure

V,

Input ~Iamp Voltage

Vee = Min, I, = -12 mA, (Figure 3)

VOH

High Level Output Voltage

Vec = Min, V'L = 0.8V, 10H = -400pA, (Figure 21

VOL

low Level Output Voltage

Vee

Input Current at Maximum Input

Vee = Max, V, = 5.5V, (Figure 4)

I,

21

= Min,

V 1H = 'iV. IOL

= 16 rnA

High Level Input Current

Vee

= Max, V, = 2.4V,
= Max, V, = O.4V,

2.4

(Figure 4)

(Figure 31

0.8

V

-1.5

V

0.4

V

V

3.3
0.22

(Figure 11

Voltage

I'H

V

2

V'H

Input A
Input G

1
2

mA
mA

Input A
InputG

40
80

pA
pA

Input A
InputG

-1.6
3.2

mA
mA

I'L

Low Level Input Current

Vee

los

Short Circuit Output Current

Vee = Max, (FigureS), (Note 10)

-55

mA

ICCH

Supply Current

Vee

(Figure61

2

4

mA

leel

Supply Current

Vee = Max, V, = 5V, Outputs Low, (Figure 61

6

11

mA

= Max, V, = OV, Outputs High,

-18

OUTPUT TRANSISTORS
V(BRICBO

Collector·Base Breakdown Voltage

Ic = 1001lA, IE = 0

35

V

V(BR)CER

Collector·Emitter Breakdown

Ic = l00pA, R. E = 500n

30

V

5

V

Voltage
V(BRJEBO

Emitter·Base Breakdown Voltage

h'E

Static Forward Current Transfer
Ratio

IE = 100/lA, Ie = 0
TA = +25°C
VeE =3V, INote 11)
TA = aOc

V.E

Base·Emitter Voltage

VCE{SATJ

Collector·Emitter Saturation

(Note 11)

,

Ie =.100mA
Ie = 300mA
le=100mA
Ie = 300mA
I. = 10 mA,
I. - 30 mA,
I. = 10 mA,
I. = 30mA,

(Note 11)

Voltage

3-52

25
30
20
25
Ic = 100 rnA
Ie = 300 mA
Ie - 100 mA
Ic = 300mA

0.85
1.05
0.25
0.5

1
1.2
0.4
0.7

V
V
V
V

Electrical Characteristics

c
en
en

(Continued)

OS55451/0S75451, OS55452/0S75452, OS55453/0S75453, OS55454/0S75454 (Notes 8 and 9)
PARAMETER
V'H

High·level Input Voltage
Low-Level Input Voltage

V,

Input Clamp Voltage

VOL

Low-Level Output Voltage

MAX

2

Vee

= Min.

UNITS
V

1,=-12rnA
IOL = 100 rnA
V'L = 0.8V

Vee

IOL = 300 mA

== Min,

(Figure 7)

IOL = 100 mA
V ,H = 2V
IOL = 300 rnA

High-Level Output Current
Vee

=:

Min,

V'H = 2V
V OH = 30V
V'L = 0.8V

I,

Input Current at Maximum Input Voltage

I'H
I'L
ICCH

Supply Current, Outputs High

Vee

=:

Max, V, = 5.5V, (Figure 9)

High-Level Input Current

Vee

=:

Max, V , =2.4V, (Figure 9)

Low-Level Input Current

Vee

=:

Max, V, =Oo4V, (Figure 8)

Vee

=:

Max,

(Figure 10)

Supply Current, Outputs low
Vee

=:

Max,

(Figure 10)

0.8

V

-1.5

V

0555451, 0555453

0.25

0.5

V

0575451, 0575453

0.25

004

V

0555451, 0555453

0.5

0.8

V

0575451, 0575453

0.5

0.7

V

0555452, 0555454

0.25

0.5

V

0575452, 0575454

0.25

004

V

0555452, 0555454

0.5

0.8

V

0575452, 0575454

0.5

0.7

V

300

pA

0575451, 0575453

100

pA

0555452, 0555454

300

pA

0575452, 0575454

100

pA

1

rnA

0555451, 0555453
(Figure 7)

leeL

TYP

(Figure 7)

V'L

IOH

MIN

CONDITIONS

-1

40

pA

-1.6

rnA

V, = 5V

0555451/0575451

7

11

rnA

V, - OV

0555452/0575452

11

14

rnA

V, - 5V

0555453/0575453

8

11

mA

V,-OV

0555454/0575454

13

17

rnA

V, = OV

0555451/0575451

52

65

inA

V, - 5V

0555452/0575452

56

71

mA

V, - OV

0555453/0575453

54

68

mA

V, = 5V

0555454/0575454

61

79

mA

TYP

MAX

UNITS

12

22

ns

20

30

ns

8

15

ns

20

30

ns

7

12

ns

9

15

ns

Switching Characteristics
OS75450 (V CC

= 5V, T A = 25°C)

PARAMETER
tPLH

CONDITIONS

low-la-High level Output

MIN

RL = 400n, TTL Gates, (Figure 12)

Propagation Delay Time,
CL =15pF

RL - 50n, Ie

~

200 rnA, Gates and Transistors

Combined, (Figure 14)

t pHL

RL = 400n, TTL Gates, (Figure 12)

Propagation Delay Time,

= 15pF

High-To-Low Level Output

CL

RL - 50n, Ie:::::: 200 rnA, Gates and Transistors
Combined, (Figure 14)

tTLH

Transition Time, Low-To-High
Level Output

CL =15pF, RL = 50n, Ie
(Figure 14)

R:

200 rnA, Gates and Transistors

tTHL

TransItion Time, High-To-Low
level Output

CL = 15pF, RL = 50n, Ie
(Figure 14)

R:'

200 rnA, Gates and Transistors Combined,

V OH

High-Level Output Voltage After
Switching

Vs = 20V, Ie ';' 300 rnA, RBE = 500n, (Figure 15)

to

Delay Time

Ie = 200 mA, I B(1) = 20 mA, IB = -40 rnA, VBEIOFF) - -IV,
CL = 15 pF, RL = 50n, (Figure 13), (Note 12)

a

15

ns

tR

Rise Time

Ie = 200 mA, IB(1) = 20 rnA, I B =-40rnA, V BE IOFF)=-lV,
C L = 15pF, RL = 50n, (Figure 13), (Note 12)

12

20

ns

ts

Storage Time

7

15

ns

6

15

ns

Combin~d,

I c =200mA, I S (1)=20mA, I s =-40mA, VSE (OFFl=-lV,

mV

V s-6.5

C L = 15 pF, RL = 50n, (Figure 13), (Note 12)
tF

Fall Time

I'e = 200 mA, IB( 1) = 20 rnA, IB = -40 mA, VBEIOFF) = -IV,
CL = 15 pF, RL = 50n; (Figure 13), (Note 12)

3-53

en
~
en

S2
c

en
.....
en
~

en
o

en
CD
""t

(j)"

tn

U)

CD
"C
CD

en

~

......
en
c
25

Switching Characteristics

(Continued)

OS55451/0S75451,OS55452/0S75452,OS55453/0S75453,OS55454/OS75454 (Vee
PARAMETER

tTLH

en
Q

tTHL

MAX

UNITS

25
35
25
35

ns
ns
ns
ns

Level Output

CL = 15 pF, RL = 50n,
10 ,., 200 rnA, (Figure 14)

0555451/0575451
0555452/0575452
0555453/0575453
0555454/0575454

18
24
16
24

25
35
25.
35

ns
ns
ns
ns

Transition Time, Low-To-High level
Output

CL = 15pF, RL = 50n, 10 '" 200 mA, (Figure 14)

5

8

ns

Transition Time. High-To-Low Level

CL = 15pF, RL =50n, 10 ,., 200 mA, (Figure 14)

7

12

ns

LO

~

TYP
18
26
18
27

Propagation Delay Time, High-To-Low

LO

= 25°C)

0555451/0575451
0555452/0575452
0555453/0575453
0555454/0575454

Level Output

tpHL

TA

MIN

CL = 15 pF, RL = 50n,
10 ,., 200 rnA, (Figure 14)

Propagation Delay Time, Low-To-High

tpLH

= 5V,

CONDITIONS

Output
VOH

Vs = 20V, 10 ,., 300 mA, (Figure 15)

High-Level Output'Voltage After

Vs -6.5

mV

Switching

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Voltage values are with respect to network ground terminal unless otherwise specified.
Note 3: The voltage between two emitters of a multiple-emitter transistor.
Note 4: Value applies when the base·emitter resistance (RBEI is equal to or less than 500n.
Note 5: The maximum voltage which should be applied to any output when it is in the "OFF" state.
Note 6: Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over a short time
interval must fall within the continuous dissipation rating.
Note 7: For the OS75450 only, the substrate (pin 81 must always be at the most·negative device voltage for proper operation.
Note 8: Unless otherwise specified minimax limits apply across the -55°C to +125'C temperature range for the OS55450 series and across the
O°C to +70'C range for the 0575450 series. All typicals are given for Vce = +5V and TA = 25°C.
Note 9: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 10: Only one output at a time should be shorted.
Note 11: These parameters must be measured using pulse techniques. tw = 300l's, duty cycle < 2%.
Note 12: Applies to output transistors only.

,

Schematic Diagrams·

OS55451/0S75451

.
.r.r
~

AI

GO--

f--.

.,

Ok

~'Z

....

~~

v",
Uk

R

Ok

V

~,

U,

~-

B

E1

H

B1

~CI

,

.../~

...

130~
J

1-~

-~y

Ao--T-j

BotJrinpublr.IfJttdamultlnlOusly.

Y, n;;;=;.r-.......

Elchinplltiltntldll~r.ttly.

E.chinpuliSIlSDd.plr,tdV.

FIGURE 1. VIH. VOL

FIGURE 2. Vil. VOH

v,

OPEN

E.chptll'teltldseparltely.

FIGURE 4. II.IIH

FIGURE 3. VI. IlL

FIGURE 5. lOS

3·55

Both 1IItl!' .... testldsimulflnlDusly

FIGURE 6. ICCH.lcel

o

..CD-..

DC Test Circuits

(Continued) .

tA

CIRCUIT

~
~
.....

OS54451

.TEST J;i'OH
'
SEE

VO H

~IOL

TABLE

en
c
o

OS5445:?

Yo,

OS54453

~~

Lt)

OS54454

~

Lt)

en

INPUT
UNDER
TEST

OTHER
INPUT

OUTPUT
APPLY

MEASURE

V OH

10H
VOL

V'H
V'L

V'H
Vee

V'H
V'L

V'H
Vee

V OH

V'H
V'L

Gnd

V OH

V'L

10L

10H
VOL

V'H
V'L

Gnd

10L
V OH

VOL
10H

10L

loc

V'L

VOL
10H

FIGURE 7. VIH. VIL'~OH. VOL

c

4.'Vn SEE'" A.'
NOTES

VI 0"

"~n
":'"

OPEN

t'A

OPEN

Nail A' Elch tnjlUt il tested sePlrltely.

NOle B: When teslll1g 0855453/0815453, OS55454/
DS15454. input not undlr test is groundld.

il

EI~h

For all other Clrcpitsilli.t4.5V,

input istetted upllately.

':'"

":'"

FIGURE 9. II,IIH

FIGURE S. VI. IlL

v""

OPEN

v,

v,

8othfllltesaretestedsimultlneously.

Both gates Ire tested simultilltollsly.

FIGURE 10. ICCH. ICCl for AND. NAND Circuits

FIGURE 11. ICCH,lCCl for OR, NOR Circuits

AC Test Circuits and Switching Time Waveforms
INPU~

2.4V

Vee

OUTPUT

5V

RL "400
·AlldiodesarelN3064

GNO
":"

OUTPUT

CL =1Spf

~(NOTE21

~~,~'. ,.w"",,:'-"-'
~~05" ' ~I
:H
~LH-H/
I't~H'
--3V

INPUT

1.5\1

1511

_ _ _ _ _J.

VOL

Not.l: The pUISB generator has the followin9characteristics: PRR"' 1 MHl, lOUT'"

son.

Note2: CLinciudeprobelndligcapl1:ltlnCII.

FIGURE 12. Propagation Oelay Times, Each Gate (OS75450 Only)

. ~-iF ~ V{-~-5-",-----::
1;.;=D3"~

IOV

INPUT

-1V

"'---"'---4~- OUTPUT

ts

tD

"1

CL = 1Spf

JINOTElI

OUTPUT

'''~

I.-j
.k(i.",
...-----

Note 1: TIIa pulse generator his the follOWing cherlcter!Slics:"duty cyde::; 1"-. ZOUT '" 50.0.
Note 2: CL indudtsprobelndjlgcaplcitlnCI.

FIGURE 13. Switching Times. Each Transistor (0875450 Only)

3-56

AC Test Circuits and Switching Time Waveforms
INPUT

c
en
en

(Continued)

en
~
en

IOV

2.4V

1

l.DV

INPUT
0515450
0555451
0555453
BV
1--~----D.5jJl---------O.-l

+--",,-0 DUTPUT

J.DV

r

0555454

.v

D555453

54

, ..;
VOH

O.4V
Nole ,: The pulsa g2n.tlltor has the followinllcharlcter;sti1;,·
PRn = 1.0 MHz, lOUT"" 5011.
Not.Z: CL indudes probe and jig eapacltlnce.
Note 3: Wilen teltlng DS7S45D,conneCloutput Yto
transl5tarbaseandgroundtheSllbstratetarminal.

OUTPUT

Yo,

FIGURE 14. Switching Times of Complete Drivers

=l
~~~~:;~

l If'''

r~'DM

r~'"

Vs=30V

INPUT~O%

OS55452
INPUT

~~;~~

1.5V

10%

40;4

DUTPUT

---l

_____

3V

DV

\

r

' -_ _ _ _ _ _ _ _ _....J

Notel:Th.puISllgene,atorhasthefollowlngcharicterldics:

PRR" 12.5 kHz, ZOUT= SOn.
Note 2: Whente51ing DS7545D,connectoutputVIotransistor
base with ~ SOOn mlstor from there to ,,!lund .nd IIround tIM
substr.trterminal.
Note J: CL includesprabe and jIg upacitance.

FIGURE 15. Latch·Up Test of Complete Drivers

Typical Performance Characteristics
~

4.0
w

'"~

'"

3.0

">

~

~

2.0

I'....

"

~

~
......
~

0:

~

\

w

1.0

.."

I\,

~

;;;

100

0:

I

VeE:::: 3V
(NOTE 81

~

r\.

~

~

";::

Vee:::: 5V
V1L ""O.8V
TA "" 25"C
(F'GURE 21

80
60
40

20

---

TA

,-

"":1.rC

T~

-I--l

TA - O"C

3:

0:

~

-10

-20

-30

";::

-40

'"~

HIGH·LEVEL OUTPUT CURRENT (mAl

FIGURE 16. DS75450 TTL Gate High·Level
Output Voltage vs High·Level Output Current

10

20

40

70 100

200

400

COLLECTOR CURRENT (mAl

FIGURE 17. DS75450 Transistor Static Forward
Current Transfer Ratio vs Collector Current

3·57

BV

S'10ns

"~.;r
10.

1.5V
'0%

3V

1.5V

j"~_:IO:%===::;';;;::=====I;-

}--o

It;;S'SAS

'--1>--,...0 DUTPUT

~

en

0

INPUT
0555452

DS

c
en
.....
en
~

:::;5.0nl

,

52

VOH
V ,

o

en
(I)

...

CD'
en

'"
CD

·C

Typical Performance Characteristics

(Continued)

cZ

~

w

"'~
'">
;:
'"

1.2
Ie

..
~

~

'"'">

~
~

i; =10

1.0

.

li~~~

(NOTE 8)

=-r: =+10"C

0.8

g;"

0.4

;;!

0.3

'"
~
as,
ci:
'"

0.4

0.2

o

ZOO

10

!E

= 10
10
(NOTE 8)

0.5

IJ
IiiIYO)j

I-

F::::== ~TA =+25"C

0.6

0.6

20
40 70 100
COLLECTOR CURRENT (mA)

~=1125'c
r"TIAI'I
. O'IIC;

II

0.1

~
8

400

lW

0.2

10

ZO

40

ZOO

10 100

400

COLLECTOR CURRENT (mA)

FIGURE 18. OS75450 Transistor Bass·
Emitter Voltage YS Collector Current

FIGURE 19. Transistor Coliector·Emitter
Saturation Voltage V5 Collector Current

Typical Applications
.20-_ _ _...,

.,v

11

.,v

,.

11
SUB

10
SUB

.v

OUTPUT

0575450

0$75450

GND

GND
INPUTG

•• 0------'
'V" Ii + Al . AZ

---..1

INPUT A 0-....
t

A1 .

A~2-....--jt:======~J

FIGURE 21. 500 mA Sink

FI GURE 20. Gated Comparator

'V'

,NPUT

.,v

.v

O------......

--l>""l""".-------oOUT·OF.PHASE OUTPUT

0----,

5V

"

.--.,...-0 IN·PHASE OUTPUT

."
. D)~
D.',' /'

82D

Uk

82'

1\
·V2

14

STROBE

~

13

~
•

2

"

11

,. ,

DUlPUTD

I·

SUB

~

DS75450

~
3

•

,

GNU

6

I'

ThisSlde ean perform the same Of l1Iother funttloll.

OUTPUTQ

FIGURE 23. Square·Wave Generator

FIGURE 22. Floating Switch

3·58

Typical Applications

c
en
en

(Continued)

en
~
en
S2

,y, o-...,..-----...,..--t--,

c

en
......

•5V

r---------,I
DIODE ARRAY

L_
SINK

CURRENT

I
I
I
I
J

t

STROBE

I SOURCE

t CURRENT
TO MEMORY DRIVE LINES

'--+----0 -V2

SOUfce and sink controls aft Ictlvated by high level ,"put wolWjes (VIH

~

2VI.

FIGURE 24. Core Memory Driver

.5V 0 - -....----=-----...,...--.---,
INns
4.1k

...--+-.....--i-ODUTPUT A

INPUT A 0 - - + - - - ,

10

"

-10V OR NEGATIVE
SUPPLY OR MOS CIRCUIT

0815450

CND
STROBE

'--+--+--.4--0

OUTPUT B

INPUT 8 0 - - - -....

IN159

4.1k

FIGURE 25. Dual TTL·to-MOS Driver

.5Vo----...,..-t-------t--t--------,
22k

2.7k

z.n

INPUT B O-....'WH.....-t'---t=---t='-....J
STROBE

0-------'

'---------r----oOUTPUT B

FIGURE 26. Dual MOS·to·TTL Driver

3·59

en
~
en
o

en

...
iii"

CD

o

en

CD

"C:

Typical Applications

(Continued)

+.vo-.....

.....---,

~~----

,.

CD

en

. - - - - - - 0 LINE 1

1

~
~

I'

en

PAIR

LINE

c

o

II)

~

INPUT
FIlOM
TIL

II)

en

c

-==:::t==--o

I"__

L
Terlnination is made.t th, receiving end as follows:
line 1 is Dlminaled to ground througb Zo/2;
lme 2 is terminated 10 ..5V tbrough Zol2;
where Zo IS the Ime Imptdlnce.

LlNE2

..

FIGURE 27. Balanced Line Driver

INPUT A
STROBE

0575451

INPUTB

"Optional ke~p.lIlive resistors maintain oH-state lamp
currentat"" 10% to reduce sur;e current.

FIGURE 28. Dual Lamp or Relay Driver

.vo--.....-....,

-...:~=+====:;----l

,NPuTo-.....

" COMPLEMENTARY OUTPUTS fOR:
GOINO·GO INDICATORS
}
MOS CLOCK DRIVERS

0575451

DM7404

BIPOLAR RELAYS

FIGURE 29. Complementary Driver

.vo-.....-~----~----------~~~~~,

.vo---.----.------------.~~-~~

1k

1uk"

TEST

"1"
'NPUT o--oot--<,J

OS15452

F

390

INPUT

·The two input resiSlors must bt adjusted for the level of MOS input

FIGURE 30. TTL or DTL Positive Logic·Level Detector

FIGURE 31. MOS Negative Logic-Level Detector

3-60

Typical Applications

c
en
U1

(Continued)
5Vo-------~----------------------_,

~
52

U1

c

en
.......

INPUT A
STROBE

0815453

U1
~

INPUTB

U1

o

en
CD

::::!.
CD

FIGURE 32. Logic Signal Comparator

tn
5Vo-----~~--------------------,
SIGNALS FROM}
PEAK DETECTORS

0-:"______-1-____--,

OUTPUT

A

~

B

:

OUTPUT

:

0875453

,.

lOI'llOtllpulotcunonlvwhenmputi
ateiOWSlmul!anenusly.

*lfinputsl,eunused.theyshouldbeconnecu:dto+5VthroughalkreSlStor.

FIGURE 33. In·Phase Detector
5Vo---------~----------------------~--_,

1k

r~::=t::::::~______-4______~~~~~Vl=AB
V1 =A+8
INPUT A
V2 = Vl. C= (A+HI E
YZ=Yl+I>A:B+C

0875464

lNPUTB
INPUTC

FIGURE 34. Multifunction Logic'Signal Comparator

5Vo----------t----------------------t---, ALARM
FROM ALARM {
TRANSDUCERS

RELAY

<>-+--....----1------,
390

390

.-JL:....-----l-'-------f'-------t=-.

D815454

FROM ALARM {
TRANSDUCERS

0-+--....------------'
FIGURE 35. Alarm Detector

3-61

o

CD

".: ~National
CD
CI), ~ Semiconductor

~ttt:t
COCO

--

C")C")

COCO
-COCO
,..
,..
-COCO
C'IC'I

ttt:tttt:t

LI)LI)

~t;.

cc

PeripherallPower Drivers

0855461/213/4, 0875461/2/3/4 8eries Dual Peripheral Drivers
General Description

Features

The 0555461/2/3/4 series of dual peripheral drivers
are functionally interchangeable with 0555451/2/3/4
series peripheral drivers, but are designed for use in
systems that require higher breakdown voltages at the
expense of slightly slower switching speeds. Typical
applications include power drivers, logic buffers, lamp
drivers, relay' drivers, M05 drivers, line drivers and
memory drivers.

•
•
•
•
•

300 mA output current capability
High voltage outputs
No output latch-up at 30V
Medium speed switching
Circuit flexibility for varied applications and choice
of logic function
• TTL compatible diode-clamped inputs
• 5tandard supply voltages

. The 0555461/0575461, 0555462/0575462, 0555463/
0575463 and 0555464/0575464 are dual peripheral
AND, NAND, OR and NOR drivers, respectively, (positive logic) 'with the output of the logic gates internally
connected to the bases of the NPN output transistors.

Connection Diagrams
Vee

8!

A2

V2

AI

81
VI
TOP VIEW

GNO

(Oual-In-Line and Metal Can Packages)

AI

81
VI
TOP VIEW

GND

Vee

112

AI

Y2

Al

81
VI
TOP VIEW

GND

Vee

B2

Alii

AZ

'II
TOP VIEW

V2

GNo

Order Number OS55461J·S, Order Number OS55462J·S, Order Number OS55463J·8, Order Number OS55464J·S,
OS75461J·S or OS75461N
OS75462J·S or OS75462N
OS75463J·8 or OS75463N
OS75464J·S or OS75464N
See NS Package JOSA or NOSA

•••

GN.
TOP VIEW

TOPYIEW

Put41JIneleuflcai canuctwitb the Cia.

Pln4hmelKtnu\cllftbl;twiththttll•.

TOP VIEW
PI"4ISi ....ctriCllcanlaClwhllttleClSe.

Order Number
OS55462H or OS75462H

Order Number
OS55463H or OS75463H

Order Number
OS55461 H or OS75461 H

See NS Package HOSC

3-62

G••
TOPYIEW
pjn4 is ill elllcb'ICIII collClctwlllI till a ••

Order Number
0S55464H or OS75464H

Absolute Maximum Ratings
5upply Voltage (Note·2)
Input Voltage
Inter-emitter Voltage (Note 3)
Output Voltage (Note 4)
0555461/0575461, 0555462/0575462,
0555463/0575463,0555464/0575464
Output Current (Note 5)
0555461/0575461, 0555462/0575462,
0555463/0575463,0555464/0575464

cc

Operating Conditions

(Note 1)
7V
5.5V
5_5V

5upply Voltage (VCC)
055546X
057546X

35V

Temperature (T A)
055546X
057546X

MIN

MAX

UNITS

4.5
4_75

5.5
5.25

V
V

+125
+70

·C
·C

-55

0

Lead Temperature (50ldering, 10 seconds)

m

OS55461/0S75461,OS55462/0S75462,OS55463/0S75463,OS55464/0S75464 (Notes 6 and 7)
CONDITIONS

V'H

(Figure 1)

V'L

Low Level Input Voltage

(Figure 1)

V,

Input Clamp Voltage

Vee

VOL

Low Level Output Voltage

= Min,

I, =-12mA

TYP

MAX

0555461, V'L = O.SV

0555463, V'L =O.SV
0555464, V'H =2V
0575461. V'L =0.8V
0575462, V'H=2V
0575463, V'L =0.8V
0575464. V'H=2V

High Level Output Current
V'H = 2V
Vee = Min, V OH =

35V, (Figure 1)
V'L = O.SV

IOL = 100 mA
IOL = 300 mA
IOL = 100 mA
IOL = 300 mA
J.c, = 100 mA
IOL = 300mA
IOL
IOL
IOL
10
IOL

= 100 mA
= 300 mA
= 100 mA
-300mA
= 100 mAo

V
V

-1.5

V

0.15 .

0.5

0.36
0.16
0.35

0.8
0.5
0.8

V
V
V
V

0.18
0.39
0.17

0.5
0.8
0.5

0.38

0.8
0.4
0.7

0.15
0.36
0.16

10L = 300 mA
IOL ~ 100 rnA

0.35
0.18.

10L = 300 rnA
10L = 100 rnA

0.39
0.17

IOL = 300 rnA

0.38

0555461.
0555463
0575461,
0575463
0555462,
0555464
0575462,
0575464

I,

Input Current at Maximum

I'H

High Level Input Current

Vee = Max, V, = 2.4V, (Figure3)

I'L

Low Level Input Current

Vec = Max. V, = O.4V, (Figure 2)

lecH

Supply Current

Vee = Max, V, = 5.5V, (Figure 3)

Input Voltage

UNITS

0.8
-1.2

0555462, V'H=2V

IOH

MIN
2

Vee = Min,(Figure 1)

NN

cncn

::::I.

Electrical Characteristics
PARAMETER

--cncn

en"
(I)

°Oerate cavity pa'1.kage 7.3 mV;J/oC above 25°C; derate molded
package 7.7 omW/ C above 25 C; derate TO-5 package 5.1 mW/
.oc above 25 c.

High Level Input Voltage

~~

..&. ..&.

~~

1090 mW
957mW
760mW
-65?C to +150·C
260·C

Storage Temperature Range

c.nc.n

WW
-cncn

300mA

Maximum Power Dissipation* at 25°C
Cavity Package
Molded Package
TO-5 Package

0en
...... c.n

,

0.4
0.7

V
V
V
V
V
V
V

0.4
0.7

V
V
V

0.4

V

0.7

V

300

IlA

100

p.A

300

p.A

100

p.A

1

rnA

40

IlA

-1

-1.6

mA

's

11

rnA

13

17

rnA

14

19

rnA

0555461/
V, = 5V

0575461,
0555463/
0575463

Vee = Max, Outputs

High, (Figures 4 and 5)
V, = OV

0555462/
0575462

05554641
0575464

3-63

(/)
Q)

.-'-,
~

~~

-coco

Electrical Characteristics (Continued)
OS55461/0S75461, OS55462/0S75462, OS55463/0S75463, OS55464/0S75464 (Notes 6 and 7)
I

PARAMETER
'eeL

CONDITIONS

MIN
05554611
0575461
0555463/
0575463
0555462/
0575462
0555464/
0575464

Supply Current

C")C")

V, =OV

-,.. ,..

Vee"" Max, Outputs

C'IC'I

coco
coco
q-q-

--

Low, (Figures 4 and 6)

V, = 5V

TYP

MAX

UNITS

61

76

mA

63

76

mA

65

76

mA

72

85

mA

TYP

MAX

UNITS

45

55

ns

50

65

ns

30

40

ns

40

50

ns

8

20

ns

12

25

ns

8

25

ns

12

20

ns

10

20

ns

15

20

ns

10 '

25

ns

11)11)
II) .....

Switching Characteristics

cc

OS55461/0S75461,OS55462/0S75462,OS55463/0S75463,OS55464/0S75464 Vee = 5V, T A = 25°C

U)U)

PARAMETER
tpLH

I

CONOITIONS

Propagation Delay Time,

low-To-High level Output
10 "'200mA, C L =15pF, R L =50n,
(Figure 6)

tpHL

Propagation Delay Time,
High-To-Low Level Output

10 '" 200 mA, CL =15pF, RL =50n,
(Figure 6)

tTLH

Transition Time, Low-To-

High level Output
10 '" 200 mA, CL = 15pF, RL = 50n,
(Figure 6)

tTHL

Transition Time, High-To-

Low Level Output

10 "'200mA, CL = 15

p~,

RL = 50n,

(Figure 6)

VOH

High-level Output Voltage

Vs = 30V, 10 '" 300 mA,'(FiQure 7)

MIN
0555461/
0575461,
0555463/
0575463
0555462/
0575462,
0555464/
0575464
0555461/
0575461,
0555463/
0575463
0555462/
0575462,
0555464/
0575464,
OS55461/
0575461
0555462/
0575462
0555463/
0575463
0555464/
0575464
0555461/
0575461
0555462/
0575462,
0555464/
0575464
0555463/
0575463
Vs -10

mV

After Switching

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.
Note 2: Voltage values are with respect to network ground terminal unless otherwise specified.
Note 3: This is the voltage between two emitters of a multiple-emitter transistor.
N~te 4: This is the maximum voltage which should be applied to any output when it is in the "OFF" state.
Note 5: Both halves of these dual circuits may conduct rated current simultaneously; however, power dissipation averaged over'a short time
interval must fall within the continuous dissipation rating.
Note 6: Unless otherwise specified minimax limits apply across the -55·C to +125°C temperatu're range for the DS55XXX series and across the
O·C to +70oC range for the DS75XXX series. All tYpicals are given for VCC ~ +5V and TA = 25°C.
Note 7: All currents into device pins shown as positive, out of device pins as negative, all voltages 'referenced to ground unless otherwise noted.
All values shown as max or min on absolute value basis.

3-64

cc
cncn
--..len

Schematic Diagrams
0555461/0575461,

~~
en
........en

0555462/0575462

r---.....----.--.-----oV"

-~~
-enen
ww

-enen
~~

f'"
'-'-'_--'-'--j~""-"'-oGND
Resrstofwlues sI10wn are nominal.

0555464/0575464

r---~--~~--'----OV~

r---~--~~--'-~-""'----o~c

ResistOfvllluesshoWDlllllominal.

(H = high level, L = low level)

0555461/0575461

B

L

L

.

L - - 4 - - -...- - - - -....-t-~~t-~~-oGND

'--jo__--...- - - - -......-.-....-oGND
Resistor values dlown UI nominal.

A

en

Resistor nlues s.hown Ire nominal.

0555463/0575463

Truth Tables

::::!.
CD

' -...---.-.--j~-....- ........-.-._ _oGND

Y
L (ON State)

0555462/0575462

0555463/0575463

A

B

Y

A

B

L

L

H (OFF State)

L

L

Y
L (ON State)

0555464/0575464

A

B

Y

L

L

H (OFF State)

L

H

L (ON State)

L

H

H (OFF State)

L

H

H (OFF State)

L

H

L (ON State)

H

L

L (ON State)

H

L

H (OFF State)

H

L

H (OFF State)

H

L

L (ON State)

H

H

H (OFF State)

H

H

L (ON State)

H

H

H (OFF State)

H

H

L (ON State)

3-65

[)C Test Circuits

v'"
v,.

SEE

TEST

VOM

1:&
~~

~IOL

TABLE

V"

v...

.".

.".

INPUT
UNDER
TEST

CIRCUIT

OTHER
INPUT

OUTPUT
APPLY

MEASURE
Haw1: Etcbinputistrnttlllpmtely,

V,H
V'L

V,H
Vee

V OH

IOH

IOL

VOL

DS55462

V,H
V'L

V,H
Vee

IOL
VOH

VOL
IOH

OS55463

V,H
V'L

Gnd

VOH
IOL

IOH
VOL

OS55464

V,H
V'L

Gnd

IOL
VOH

VOL
IOH

OS55461

V'L
V,L

0...

NOh Z: When lUCinl OS55463/DS15463Ind 0515414,
inpallHlt .. lllhl'unis"ounded.
F,,"othercircuiuhisI14.6V.

FIGURE 2. VI. IlL

Each input nbsmIaJIIFlttly.

FIGURE 1. VIH. VIL.IOH. VOL

v,.o----'""'"I
OPEN

.v.

v,

ElChirtputisttstedSlPlrl1ely.
lotb lites Ifl telted limul1lRlol!Sly.

FIGURE 3.1" IIH

FIGURE 4. ICCH.ICCL for
AND. NAND Circuits

3-66

Both lites Irt IHted IimulblAtously.

FIGURE 5. ICCH. ICCl for
OR. NOR Circuits

cc
encn
..... en

Switching Characteristics
INPUT

2.4V

1,
OS55461
0555462

en en

IOV

0l::I00l::I0

---..........

0')0')

l.OV

INPUT
0555461

RL =50

0')0')
I\) I\)

DS5S463

'v

+--....

f - - - - - - - - o ..., - - - - - - - - - '

-oOUT'UT

0')0')

WW

::;; 5.0 ns

l.OV

0')0')

oI::Io.J:'o

ov
VOH
NOI.,:Thepulsegenentorh15thefollo,dngcharacllllstlcs:

OUTPUT

PRR = 1 MHz, ZOUT'" 50n.
NotaZ: CLincludesprobeandjlgcapacitince.

VOC

FIGURE 6. Switching Times of Complete Drivers

Vs=30V

D~~~~I
0555463

INPUT

L...~""'-""-O OUTPUT

r""

:;i
~
I.SV

3V

1.5V

OV
~=IO:%===:;;;;:===:IO:%=1.----40/-15
1--$'"
--l
~IO"

1

l.lI.C';;D".%~--------;;'::;,0%"mi:-t+-=----3V

-~~::~ J,~.5V
OUTPUT

Nole 1: The pulse genultor has the following characteristics:
PRn" 12.5 kHz, lOUT = son.
NoteZ: Cllndudesprllbeandjlgcaplcltance. '

FIGURE 7. Latch·Up Test of Complete Drivers

3·67

l1ft~IO"
'.5~oX,-

____ ov

en
....CD
ai"
en

Safe Operating Areas
for Peripheral Drivers

National Semiconductor
Application Note 213
Bill Fowler
October 1978

Peripheral Drivers is a broad definition given to Interface
Power devices. The devices generally have open-collector output transistors that can switch hundreds of
milliamps at high voltage, and are driven by standard
Digital Logic gates. They serve many appl ications such
as: Relay Drivers, Printer Hammer Drivers, Lamp
Drivers, Bus Drivers, Core Memory Drivers, Voltage
Level Transistors, and etc. Most IC devices have a
specified maximum load such as one TTL gate can
drive ten other TT L gates. Peripheral drivers have many
varied load situations depending on the application,
and requires the design engineer to interpret the limitations of the device vs its application. The major
considerations are Peak Current" Breakdown Voltage,
and Power Dissipation.

of 1 to 10 mA on a transistor curve tracer (LVCEO
is sometimes measured in an Inductive Latch-Up Test).
Observe that all breakdown voltages converge on LVCEO
'at high currents, and that destructive secondary breakdown voltage occurred (shown as dotted line) at high
currents and high voltage corresponding to exceeding
the power dissipation of the device. The characteristics
of secondary breakdown voltage vary with the length
of time the condition exists, device temperature, voltage,
and current.

OUTPUT CURRENT AND VOLTAGE
CHARACTERISTICS
Figure 1 shows the circuit of a typical peripheral driver,
the DS75451. The circuit is equivalent to a TTL Gate
driving a 300 mA output transistor. Figure 2 shows the
characteristics of the output transistor when it is ON
and when it is OFF. The output transistor is capable
of sinking more than one amp of current when it is ON,
and is specified at a VOL; 0.7V at 300 mAo The output
transistor is also specified to operate with voltages up
to 30V without breaking down, but there is more to
that as shown by the breakdown voltages labeled BVCES,
BVCER, and.LVCEO.

vee

vee

OUTPUT ON

OUTPUT
, SATURATED
. 300 rnA

~--------------~~---q~L---~veE

vee

FIGURE 2. Output Characteristics ON and OFF

OUTPUT TRANSFER CHARACTERISTICS VS
INDUCTIVE AND CAPACITIVE LOADS
Figure 3 shows the switchjng transfer characteristics
superimposed on the DC characteristics of the output
transistor for an inductive load. Figure 4 shows the
switching transfer characteristics, for a capacitor load.
In both «ases in these examples, the load voltage (VB)
exceeds LVCEO. When the output transistor turns
on with an inductive load the initial current through
the load is 0 mA, and the transfer curve switches across
to the left (VoU and slowly charges the inductor.
When the output transistor turns off with an inductive
load, the initial current is IOL, whlch is sustained by
the inductor and the transistor curve switches across
to the right (VB) through a high current and high
voltage area which exceeds LVCEO and instead of
turning off (shown as dotted line) the device goes into
secondary breakdown. It is generally not a good practice
to let the output transistor's voltage exceed LVCEO
with an inductive load.

INPUT A
INPUT B

0-+-.

FIGURE 1. Typical Peripheral Driver DS75451
BVCES corresponds to the breakdown voltage when
the output transistor is held off by the lower output
transistor of the TTL gate, as would happen if the
power supply (VCC) was 5V. BVCER corresponds
to the breakdown voltage when the output transistor
is held off by, the 500 resistor, as would happen if the
power supply (VCC) was off (OV). LVCEO corres·
ponds to the breakdown voltage of the output transistor if it could be measured with the base open. LVCE.o
can be measured by exceeding the breakdown voltage
BVCES and measuring the v.oltage at output currents

In a similar case with a capacitive load shown in Figure 4,
the switching transfer characteristics rotate counter
clockwise through the DC characteristics, unlike the
inductive load which rotated clockwise. Even though
the switching transfer curve exceeds LVCEO, it didn't

3-68

Figure 6 shows the switching transfer characteristics
of a capacitive load which leads to secondary breakdown. This condition occurs due to high sustained currents, not breakdown voltage. In this example, the
large capacitor prevented the output transistor from
switching fast enough through the high current and
high voltage region; in turn the power dissipation of
the device was exceeded and the output transistor
went into secondary breakdown.

go into secondary breakdown. Therefore, it is an acceptable practice to let the output transistor voltage exceed
LVCEO, but not exceed BVCER with a capacitive load.
Ie
VB

RL

VB

VB

FIGURE 3. Inductive Load Transfer Characteristics
Ie

1L---=::~--';"':""~...L---.L--_VeE

VB

VB

FIGURE 6. Capacitive Load Transfer Characteristics
Figure 7 shows another method of quenching the
inductive voltage spike caused by the initial inductive
current. This method dampens the switching response
by the addition of RO and CO. The values of RO and
Co are chosen to critically dampen the values of R L
and LL; this will limit the output voltage to 2 x VB.

LL- x ~
---<0.5
(RL + RO)
LLCO-

OFF

1L.-=======""""""".b._,-,2___ VeE
VB

FIGURE 4. Capacitive Load Transfer Characteristics
Figure 5 shows an acceptable application with an inductive load. The load voltage (VB) is less than LVCEO,
and the inductive voltage spike caused by the initial
inductive current is quenched by a diode connected
to VB.
Ie
VB

FIGURE 7. Inductive Load Dampened by Capacitor
Figure 8 shows a method of reducing high sustaining'
currents in a capacitive load. RO in series with the
capacitor (CL) will limit the switching transistor without
effecting final amplitude of the output voltage, since
the I R drop across RO will be zero after the capacitor
is charged.

As an additional warning, beware of parasitic reactance.
If the driver's load is located some distance from the
driver' (as an example: on the inclosure panel or through
a connecting cable) there will be additional inductive
and capacitance which may cause ringing on the driver

~--~~~--~--~~~~~---'-VeE
VB

FIGURE 5. Inductive Load Transfer Characteristics
Clamped by Diode
3-69

,..

Cf)

C'\I

•

Z

c(

output which will exceed' LVCEO or transient current
that exceeds the sustaining current of the driver. A
300 rnA current through a small inductor can cause
a good size transient voltage, as compared with a 20 rnA
transient current observed with TTL gates. For no
other reason than to reduce the noise associated with
these transients, it is good pracitce to, dam pen the
driver's output.

bias currents and voltage of the device, and the power
on the output of the device due to the Driver Load .
POWER LIMITATIONS OF PACKAGE
Figure 9 shows the equivalent circuit of a typical power

device in its application. Power is shown equivalent to
electrical current, thermal resistance is shown equivalent
to electrical resistance, the electrical reactance C and L
are eqUivalent to the capacity to store heat, and the
propagation delay through the medium. There are
two mediums of heat transfer: conduction through mass
and radiant convection. Convection is insignificant
compared with conduction and isn't shown in the
thermal resistance circuits. From the point power
is generated (device junction) there are three possible
paths to the ultimate heat sink: 1. through the device
leads; 2. through the device surface by mechanical
connection; and 3. through the device surface to ambient air. In all cases, the thermal paths are like delay
lines and have a corresponding propagation delay.
The thermal resistance is proportional to the length
divided by the cross sectional area of the material. The
Thermal Inductance is proportional to the length of the'
material (copper, molding compound, etc.) and inversely proportional to the cross sectional area. The
thermal capacity is proportional to the volume of the
material.

In conclusion, transient voltage associated with inductive loads can damage the peripheral driver, and transient currents associated with capacitive loads can
also damage the driver. In some instances the device
may not exhibit failure with the first switching cycle,
but its conditions from ON to OFF will worsen after
many cycles. In some cases the device will recover
after the power has been turned off, but its long term
reliability may have been degraded.

POWER DISSIPATION
Power Dissipation is limited by the IC Package Thermal
Reactance and the external thermal reactance of the
environment (PC board, heat sink, circulating air,
etc.). Also, the power dissipation is limited by the
maximum allowable junction temperature of the device.
There are two contributions to the power: the internal

FIGURE 8. Capacitive Load with Current Limiting Resistor

TpC BOARD

TOEVICE PIN
TjUNCTION

ENERGY
SOURCE

•
'::"

TAMBIENT

TOlE

~

T

TpACKAGE
CONNECTION

T

TAMBIENT

TAMBJENT AIR

FIGURE 9. Thermal Reactance from Junction to Ambient
3-70

'::"

DEVICE PACKAGE

the line intercepts the diagonal line of the package
type, and then project a line (shown dotted) horizontally until the line intercepts the Power Dissipation
Axis (PMAX).

1.4
DIE SIZE = 6000 MIL 2

PC BOARD

1.2

~

DEVICE
PIN

.....
'"

C>

;::

FIGURE 10. Components of Thermal Reactance for a
TypicallC Package

'"

;::
:-1:
in

75

100

125

150

resistance than 8 pin packages; which should be expected since it has more pins to conduct heat and has
more surface area. Something that may not be expected
is that the Thermal Resistance of the molded devices
is comparable to the ceramic devices. The reason for the
lower thermal resistance of the molded devices is the
Copper lead frame, which is a better thermal conductor
than the Kovar lead frame of the ceramic package.
Almost all the peripheral drivers made by National
Semiconductor are constructed with Copper lead frames
(refer to IPJA on the specific devices data sheet). The
difference between the thermal resistance of Copper
and Kovar in a molded package is shown in Figure 12.

I

0.4

0.2

Figure 11 shows that 14 pin packages have less thermal

1.2

~

0.4

FIGURE 12_ Maximum Package Rating Copper vs Kovar
Lead Frame Packages

1.6

0.8

a:
'"
;:

...<>~

50

1.4

'"c;

0.6

AMBIENT TEMPERATURE ('CI

2.0
1.8

Q

'"c;
a:

National Semiconductor specifies the thermal resistance
from device junction through the device leads soldered
in a small PC board, measure in one cubic foot of still
air. Figure 11 shows the maximum package power
rating for an 8 pin Molded, an 8 pin Ceramic, 14 pin
Molded and a 14 pin Ceramic package. The slope of the
line corresponds to thermal resistance {IPJA = ~P/~T}.

~

0.8

in

0.6
0.2
50

75

100

125

150

175

AMBIENT TEMPERATURE ('C)

Another variance in thermal resistance is the size of the
IC die. If the contact area to the lead frame is greater,
then the thermal resistance from the Die to the Lead
Frame is reduced. This is shown in Figure 13. The
thermal resistance shown in Figure 11 corresponds
to die that are 6000 mil 2 in area.

FIGURE 11. Maximum Package Power Rating

The maximum allowable junction temperature for
ceramic packages is 17SoC; operation above this temperature will reduce the reliability and life of the device
below an acceptable level. At a temperature of SOOoC
the aluminum metallization paths on the die start to
melt. The maximum allowable junction temperature
for a molded device is lS0°C, operations above this
may cause the difference in thermal expansion between
the molding compound and package lead frame to
sheer off the wire bonds from the die to the package
lead. The industry standard for a molded device is
lS0oC, but National further recommends operation
below 13SoC if the device in its application will encounter a lot of thermal cycling {such as powered
on and off over its life}.

140

-- -

~. 120

r--

u

"- 100

..'"
u'"

t;

"""-

80

in

.

'"a:

60

:;;

40

-'

a:

'"
::

...

20
Ik

The way to determine the maximum allowable power
dissipation from Figure 11, is to project a line from
the maximum ambient temperature (TA) of the application vertically (shown dotted in Figure 12), until

2k

5k

10k

DIE SIZE (MIL2)

FIGURE 13. Thermal Resistance vs Die Size
3-71

l>
Z•

N
....
CAl

,...

C")

~

Z



5

0.2

w

a:

o

o

500

lk

AIR FLOW (LINEAR FEETIMIN)

FIGURE 14. Thermal Resistance vs Air Velocity

The thermai resistance can also be improved by connecting the package to the PC board copper or by
attaching metal wings to the package. The improvement
by these means is outside the control of the IC manufacturer, but is available from the manufacture of the
heat sink device. If the IC is mounted in a socket rather
than soldered to a PC board, the thermal resistance
through the device leads will worsen. In most cases,
the thermal resistance is increased by 20%; again this is
a variable subject to the specific socket type.

100
KEAK POWER (WATTSI

-'7

e:=
«><

10

3:'"
_w

a: ....
w'"
3: 0
0:::'
... >
""0
«a:
ww

The maximum package rating shown in this note cor·
responds to a 90% confidence level that the package
will have thermal resistance equal to or less than the
value shown_ The thermal resistance varies ±5% about
the mean due to variables in assembly and package
material.

r0.1

ENERGY (JOULES X 10-3)

r-~

"'2

w

0.01
1

10

100

lk

10k

(APPLIED TIME (",I

CALCULATIONS OF POWER DISSIPATION

FIGURE 15_ Peak Power and Energy vs
the Period of Time the Power was Applied

Most IC devices (such as T2L) operate at power levels
well below the device package rating, but peripheral
drivers can easily be used at power levels that exceed
the package rating unknowingly, if the power dissipation isn't calculated. As an example, the 083654
Ten Bit Printer Driver could dissipate 3 watts (DC and,
even more AC), and it is onlY·in a 0.8 watt package.
In this example, the device would be destroyed in
moments, and may even burn a hole in the PC board
it is mounted on_ The 083654 data sheet indicated that
the 10 outputs could sink 300 mA with a Vol of 1 volt,
but it wasn't intended that all the outputs would be

To calculate power dissipation, the only information
available to the design engineer is the parametric limits
in the device data sheet, and the same information
about the load reactance. If the calculations indicate
the device is within its limits of power dissipation, then
using those parametric limits is. satisfactory. If the
calculation of power dissipation is marginal, the parametric limits used in the calculations might be worst
case at· low temperature instead of high temperature
3-72

due to a positive temperature coefficient (T C) of resistance. IC resistors and resistors associated with the
load generally have a positive TC. On the other hand,
diodes and transistor emitter base voltages have a negative TC; which may in some circuits negate the effect
of the resistors TC. Peripheral output transistors have
a positive TC associated with VOL; while output Darlington transistors have a negative TC at low currents
and may be flat at high currents. Figure 16 shows
an example of power dissipation vs temperature; note
that the power dissipation at the applications maximum
temperature (T A) was less than the power dissipation
at lower temperatures. Since maximum junction temperature is the concern of the calculation, then maximum ambient temperatu.re power should be used.
The junction temperature may be determined by projecting a line (shown dotted in Figure 16), with a slope
proportional to 
Z

N
......

w

Refer to Figure 18 voltage and current waveforms
corresponding to the power dissipation calculated for
this example of an inductive load.

POFF =

PON = Average power dissipation in device output
when device is ON during total period (T)

23.1 [
41.7
POFF=65x- (215.9mA+291.7mA) 200
23.1

1'=

IL =

LL

5h

RL

120n

Vcx~T [(lP+ IR) x':"tx (1- e'-tx IT) -IR]

(1-e-23.1/41.7)-291.7mA] ,

- = - - = 41.7 ms

VB-VOL
RL

30-1.5
'
,= - - - = 237.5 mA
120

POFF = 736 mW
Po =

Average power dissipation in device output

PO=

PON + POFF = 110.6 + 736 = 846.6 mW

In the above example, driving a 120 n inductive load
at 5 Hz, the power dissipation exceeded a more simple
calculation of power dissipation, which would have
been:

Ip = 237.5 mA (1- e-100 ms/41.7 ms )

PO=

VOL (VB - VOL)
RL

Ip = 215.9 mA

Po =
,
TON [ {TON e-tIT dt]
PON = VOLx ILX - - 1--T
0
TON

TON
x-T

1.5(30-1.5) 100ms
120
x 200 ms = 182.5 mW

An error '460% would have occurred by not including
the reactive load. The total power dissipation must
also include other outputs (if the device has more
than one output), and the power dissipation due to the
device power supply currents. This is ah example where
the load will most likely exceed the device package
rating. If the load is fixed, the power can be reduced
by changing the period (T) and duty rate (TON/TOFF).

100[ 41.7
_ 100/41.7)]
PON= 1.5x237.5mAx-1--(1-e
200
100

-65V

-------r-.,
-

Ix

I-

PON = 110.6 mW

-30V-

POF F = Average power dissipation in device output
when device is OFF during total period (T)

I!V~~~~~~'D~oLm'-----2-0~Om~'~--

~7\

VC-VB 65-30
IR = - - - = - - = 291.7 mA
RL
120n

IL + IR)
tx =Tl1n ( - - ,
IR

)
o

.

I

lOOms

\

\
t x =·41.7ms l1n (

219.8 + 291.7)
291.7

t [
POFF=Vcx~
(lp+IR)

T

f
0

=23.1 ms

I

~\--~I

200ms

\

,,

'-,

,

IR---------------

e -tITdt
]
tx - - - I R
tx

FIGURE 18. Voltage and Current Waveforms
Corresponding to Inductive Load.

3·74

CALCULATION OF OUTPUT POWER WITH AN
INCANDESCENT LAMP
1 amp, settling to 200 ms, with an 8 ms time constant.
Observe the peak current is clamped at 1 amp, by the
sinking ability of the driver; othervvise the peak current
may have been 1.2 amps. The DS75451 is only rated
at 300 mA, but it is reasonable to assume it could
sink 1 amp because of the designed forced (3 required
for switching response and worst case operating temperature.

An incandescent lamp is equivalent to a reactive load.
The reactance is related to the period of time required
to heat the lamp and the filaments positive temperature
coefficient of resistance. Figure 19 shows the transient
response for a typical lamp used on instrument panels,
and the equivalent electrical model for the lamp. Much
like IC packages the lamp has a thermal circuit and
its associated propagation delay. This lamp filament
has an 8 ms time constant, and a longer 250 ms time
constant from the lamp body to ambient. The DC
characteristics are shown in Figure 20. Note the knee
in the characteristics at 2 volts; this is where power
starts to be dissipated in the form of light. This subject
is important, since more peripheral drivers are damaged
by lamps than an,y other load.

1

~

s

:0

0.6

i

40

~"
~J

0.8

!

0.4

D-

O

;;",'

~

T"'8ms

0.2

7.13

10

20

30

40

50

TIME (ms)

FIGURE 21. Transient Incandescent Lamp Current

o

Calculation of the energy dissipated by a peripheral
driver for the transient lamp current shown in Figure 21
is shown below, and the plot of energy vs time is shown
in Figure 22. Figure 22 also includes as a reference
the maximum peak energy from Figure 15. It can be
seen from Figure 22 that in this example there is a
good safety margin between the lamp load and the
reference max peak energy. If there were more drivers
than one per package under the same load, the margin
would have been reduced. Also, if the peripheral driver
couldn't saturate because it couldn't sink the peak
transient lamp current, then the energy would also
reduce the margin of safe operation.

10 2030 40 50 60 70 80· 90100
TIME (m,)

FIGURE 19. Transient Response of an Incandescent
Lamp

100

. I IIII I I

o

o. 1

2

3

4

5

6

7

8

9

l~mm~i/~~
IL

10

INCANDESCENT

LAMP VOLTAGE (V)

~-++H-+~HrLAMPLOAD

FIGURE 20. DC Characteristics of an Incandescent
Lamp
0.01 L....ot:..-..L..L.ll--l..-L..Ju.L...L-.J...L'-'-.L.Ju..JJ
lk
lOOk
100
10k
10

Figure 21 shows the transient response of a driver
similar to a DS75451 driving the lamp characterized
in Figures 19 and 20. The equivalent load doesn't
include the reactance of the lamp base to ambient,
which has a 250 ms time constant, since 10 ms to an
IC is equivalent to DC. The peak transient current was

TIME ,,",)

FIGURE 22. Energy vs Time for a Peripheral
Driver with an Incandescent Lamp Load

3-75

~
T"'"

N

CALCULATION OF ENERGY IN AN INCANDESCENT
LAMP

.

w

OUTPUT

TRANSLATORS/BUFFERS

OUTPUT CHARACTERISTICS

lOGIC FUNCTION

DEVICE NUMBER
-5S'C to +12S'C

o'c to +70'C

Page
No.

10k ECl

TTL

TRI·STATE@ Fall Through latch

Inverting

DP8480

4-4

TTL

10k ECl

Gated Fall Through latch

Inverting

DP8481

4-7
4-10

lOOk ECl

TTL

TRI-STATE Fall Through latch

Inverting

DP8482

TTL

lOOk ECl

Gated Fall Through latch

Inverting

DP8483

CMOS

CMOS

50 ns Prop. Delay at 500 pF

Hex Buffer

DS3630

DS1630

4-16

TTL

PMOS

Open-Collector -30V to 30V

Dual 2-lnput Gate

DS8800

DS7800

4-19

TTL

MOS

Open-Collector OAV to 14V

Quad 2-lnput Gate

DS8810

DS7810

4-22

TTL

MOS

Open-Collector OAV to 14V

Quad 2-lnput Gate

DS8811

DS7811

4-22

TTL

MOS

Open-Collector OAV to 14V

Hex Inverter

DS8812

DS7812

4-22

TTL

MOS

Active Pull-Up OAV to 14V

Hex Inverter

DS88l12

DS78l12

4-25

TTL

MOS

Open-Collector OAV to 14V

Quad 2-lnput Gate

DS8819

DS7819

4-27

CMOS

TTL

Active Pull-Up Oo4V @ 2.6 mA

H ex Inverter

MM74C901

MM54C901

CMOS

CMOS

TTL

Active Pull-Up 004 V @ 3_2 mA

Hex Buffer

MM74C902

MM54C902

CMOS

CMOS

PMOS

Active Pull-Up OV to 15V

Hex J nverter

MM74C903

MM54C903

CMOS

CMOS

PMOS

Active Pull-Up OV to 15V

Hex Buffer

MM74C904

MM54C904

CMOS

CMOS

NMOS

Open Drain OV to 15V

Hex Buffer

MM74C906

MM54C906

CMOS

CMOS

PMOS

Open Drain VCC to VCC - 15V

Hex Buffer

MM74C907

MM54C907

CMOS

4-13

ap!n~

UOnoalas

i

~National

level Translators/Buffers

~ ~ Semiconductor

PRELIMINARY

c

DP8480.10k Eel to TTL level Translator with latch
General Description

Features

This circuit translates EeL input levels to TTL output
levels and provides a fall-through latch. The TRI-STATE@
outputs are designed to drive large capacitive loads. The
clock and chip select inputs are EeL.

•
•
•
•
•

Logic and Connection Diagram

Truth Table

16'pin flat·pack or DIP
TRI-STATE outputs
EeL control inputs
5.5 ns typical propagation delay with 50 pF load
Outputs are TRI-STATE during power up/down for
glitch free operation
• 10k EeL input compatible

Dual·ln·Llne Package
Vee 1

01

DO

CK

CS

H
L

L
H
DO
Hi-Z

L
L
H

L
L
L
H

X
X

+ __-I

DlO_2

X

=

H high level (most positive)
L = low level (most negative)
X = don't care

011 _3+_-+--1

012~--+-f

Order Number DP8480N or DP8480F
See NS Package N16A or F16B
Dl4 _6+_-+-4

CK

004

7

GND 8

9 GND

TOP VIEW
TRI·STATE· Is a registered trademark of National Semiconductor Corp.

C

Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions

VEE Supply Voltage
-8V
Vcc Supply Voltage
7V
Input Voltage
GNDtoVEE
Output Voltage
5.5V
Maximum Power Dissipation" at 25·C
Molded Package
1476mW
-65·Cto150·C
Storage. Temperature
"Derate molded package 11.8 mW/'C above 2S'C.

VEESupplyVoltage
VccSupplyVoltage
TA, Ambient Temperature

-5.2V±10%
5.0V±10%
0·Ct075·C

Electrical Characteristics (TTL logic) Notes 2, 3 and 4
Parameter

Conditions

Min

Typ

Max

Units

VOL

Output low Voltage

IOL=8 rnA

VOH

Output High Voltage

10H=-lmA

100

Output low Drive Current

Force 5V with Output low

150

rnA

110

Output High Drive Current

Force OV with Output High

-150

rnA

loz

TRI-STATE Output Current

Icc

Supply Current

0.5
2.5

V
V

p.A

1
62.5

rnA

Electrical Characteristics (ECl logic) Notes 2 and 3
Parameter
VIL

VIH ,

Input Low Voltage

Input High Voltage

Conditions

TA

VEE = -5.2V

O·C
25·C
75·C

-1870
-1850
-1830

-1490
-1475
-1450

mV

O·C
25·C
75·C

-1145
-1105
-1045

-840
-810
-720

mV

V EE = -5.2V

Min

Typ

IlL

Input Low Current

0.5

IIH

Input High Current

350

lEE

Supply Current

Max

Units

/LA
/LA
-50

rnA

Switching Characteristics Notes ~ and 5
Parameter

Conditions

Typ

Max

Units

tCDoL

Clock to Data Out Low Delay

C L =50 pF

Min

6.75

11.5

ns

tcooH

Clock to Data Out High Delay

C L =50 pF

6.75

11.5

ns

t OIDOH

Data In to Data Out High Delay

CL=50pF

5.5

9.5

ns

5.5

9.5

ns

tOIOOL

Data In to Data Out Low Delay

C L =50 pF

ts

Data Set-Up Time

CL=50 pF

3.0

1.0

ns

tH

Data Hold Time

CL=50 pF

3.0

1.0

ns

tcpw

Clock Pulse Width

CL=50 pF

5.0

3.0

ns

tZE

Delay from Chip Select to
Active State from Hi-Z State

CL=50 pF

8

ns

tEZ

Delay from Chip Select to Hi-Z
State from Active State

C L =50 pF

8

ns

Notel: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to Imply that the
device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minimax limits apply across the O'C to 7S'C ambient temperature range In stili air and across the specified supply varia·
tlons. All typical values are for TA = 2S'C and nominal supply.
Nate 3: All currents Into device pins are shown as positive; all currents out of device pins are shown as negative. All voltages are referenced to ground, unless
otherwise specified.
Note 4: When DC testing 110 or 100 a 150 resistor should be In series with the output. Only one output should be tested at a time.
Note 5: Unless otherwise specified, all AC measurements are referenced from the 50% level of the ECL input to the O.BV level on negative transitions or the
2.4V level on positive transitions of the output. ECL Input rise and fall times are 2.0 ns ± 0.2 ns from 20% to 80%.

4-5

"tJ

;o

i

Switching Time Waveforms

Il.

C

--ICpw""

i - - - - t - !cOOL

ICooH~-~~1

-

S10pen

CS

DO

-3.5V
S1 CLOSED
-OV
S10PEN
*S1 closed

**S1open

Test Load.

500

CL
INCLUDING PROBE
AND JIG CAPACITANCE

4-6

I

500

IDiooH

~National

level Translators/Buffers

~ Semiconductor

P~ELlMINARY

DP8481 TTL to 10k Eel level Translator with latch
General Description

Features

This circuit translates TTL input levels to ECL output
levels and provides a fall-through latch. The outputs are
gated with CS providing for wire ORing of outputs. The
clock and chip select inputs are ECL.

•
•
•
•
•

Logic and Connection Diagram

Truth Table

16·pin flat-pack or DIP
ECL control inputs
CS provided for ""ire ORing of output bus
10k ECL 1/0 compatible
4.0 ns typical propagation delay

Dual-In-Line Package

DOD

DI

DO

CK

CS

H

L

L
X
X

H

L
L

DO

H

H
H
H

L

X

L

H = high level (most positive)
L = low level (most negative)

X= don't care

001

002

003

Order Number DP8481N or DP8481F
See NS Package N16A or F16B
004 -----,---.......

014

cs

GND

8

9 GND

TOP VIEW

4-7

C

"C

CO

&
.....

,...

~

co

a..

C

·Recommended Operating Conditions

Absolute Maximum Ratings (Note 1)

VeeSupply Voltage
Vcc Supply Voltage
TA> Ambient Temperature

-BV
7V
GNDtoVee
-1Vto5.5V
50mA

Vee Supply Voltage
Vcc Supply Voltage'
Input Voltage (ECL)
Input Voltage (TTL)
Output Current
Maximum Power Dissipation· at 25·C
1476mW
Molded Package
-65·Cto + 150·C
Storage Temperature

-5.2V±10%
5.0V±10%
0·Cto75·C

"Derate molded package 11,8 mWI'C above 25'C,

Electrical Characteristics (TTL Logic) Notes 2 and 3
Parameter

Min

Conditions

Typ

Max

Units

O.B

V

V1L

Input Low Voltage

V1H

Input High Voltage

IlL'

Input Low Current

V 1N=0.5V

-50

I'A

IIH

Input High Current

V 1N =2.5V

1.0

I'A

VCLAMP

Input Clamp Voltage

IIN= -12 mA

Icc

Supply Current

V

2.0

-O.B

V

30

mA

Max

Units

EI$ctrical Characteristics (ECL Logic) Notes 2 and 3
Parameter
V1L

V1H

Input Low Voltage

Input High Voltage

Conditions

TA

Vee= -5.2V

O·C
25·C
75·C

-1870
-1850
-1830

-1490
-1475
-1450

mV

O·C
25·C
75·C

-1145
-1105
-1045

-840
-810
-720

mV

Vee'" -5.2V

Min

Typ

IlL,

Input Low Current

0.5

IIH

Input High Current

350

VOL

Output ,Low Voltage

VOH

VOLC

VOHC

lee'

Output High Voltage

Output Low Voltage

Output High Voltage

Vee= -5.2V

Vee= -5.2V

Vee= -5.2V

Vee= -5.2V

I'A
I'A

O·C
25·C
75·C

-1870
-1850
-1830

-1665
-1650
-1625

mV

O·C
25·C
75·C

-1000
-960
-900

-840
-810
-720

mV

-1645
..; 1630
-1605

mV

O·C
25·C
75·C
O·C
25·C
75·C

Supply Current

-1020
-980
-920

mV
-90

mA

,

4·8

C

"'tJ
00

Switching Characteristics Notes 2 and 4
Parameter

Conditions

Min

Typ

Max

Units

tcoOl

Clock to Data Out Low Delay

4.0

6.5

ns

tcooH

Clock to Data Out High Delay

4.0

6.5

ns

tOIOOH

Data In to Data Out High Delay

4.0

6.5

ns

tDiOOl

Data In to Data Out Low Delay

4.0

6.5

ns

ts

Data Set-Up Time to Clock

3.0

1.0

ns

tH

Data Hold Time

3.0

1.0

ns

tcpw

Clock Pulse Width

5.0

3.0

ns

tCSOOH

Chip Select to Data Out High Delay

3.0

4.5

ns

tCSOOl

Chip Select to Data Out Low Delay

3.0

4.5

ns

tscs

Data Set-Up Time to Chip Select

5.5

3.0

ns

Note1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the
device should be operated at these limits. The table of "Electrlcal Characteristics" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minimax limits apply across the O"C to 7S"C ambient temperature range In stili air and across the specified supply varia·
tions. All typical values are for 2S"C and nominal suPpJy.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative. All voltages are referenced to ground, unless
otherwise speCified.
Note4: Unless otherwise specified, all AC measurements are referenced from the 1.SV level of the TTL input and tO/from theSO% pOint of the EClslgnal and a
SOil resistor to -2V Is the load. ECl Input rise and fall times are 2.0 ns±0.2 ns from 20% to 80%. TTL Input characteristic is OV to 3V with tr= tf " 3 ns
measured from 10% to 90%.

Switching Time Waveforms
I

cs

)
~

j

,

-lcSOOH-

DO

01

_fa.

-ICSOOL-

I
I

..

-Icpw-

~

CK

'0\

-,If..

'--.J

- -tH

DI~~

ts~

}~

~.

--...

r !cOOL

DO

I

~

~

ICOOH

4-9

~

-l-

f\.-I

-tOIOOL-

}r-\.

-

- tDiOOH

&
.....

~ ~National
Q.

c

level Translators/Buffers

~ Semiconductor

PRELIMINARY

DP8482100k Eel to TTL level Translator with latch
General Description

Features

This circuit translates Eel input levels to TTL output
levels and provides a fall-through latch. The TRI·STATEi!l
outputs are designed to drive large capacitive loads. The
clock and chip select inputs are EeL.

•
•
•
•
•

Logic and Connection Diagram

16·pin flat-pack or DIP
TRI-STATE outputs
Eel control inputs
5.5 ns typical propagation delay with 50 pF load
Outputs are TRI-STATE during power up/down for
glitch free operation
, • 100k Eel input compatible

Truth Table

Dual-ln·Line Package
16 Vee

DI

DO

CK

CS'

H
L

L
H
DO
HI-Z

l
l
H
X

l
l
l
H

X
X

DlO~---I

H
L

=high level (most positive)
=low level (most negative)

X = don·t care

011....;3+-_H

012-4--1--1

013-4--1--1

Order Number DP8482N or DP8482F
See NS Package N16A or F16B

0I4....;6~-H

CK

004

7

GNO 8

9 GNO
TOP VIEW

TRI·STATEolI Is a registered trademark of National Semiconductor Corp.

4-10

Absolute Maximum Ratings (Note 1)

Recommended Operating Conditions

VEE Supply Voltage

-8V

VEE Supply Voltage

Vcc Supply Voltage

7V

VccSupplyVoltage

5.0V±10%

TA, Ambient Temperature

0·Ct085·C

Input Voltage

GNDtoVEE
5.5V

Output Voltage
Maximum Power Dissipation' at 25·C
Molded Package
Storage Temperature

-4.5V±7%

1476mW
- 65·C to

+ 150·C

'Derate molded package 11.8 mW/'C above 2S'C.

Electrical Characteristics (TTL logic) Notes 2, 3 and 4
Parameter

i

Conditions

Min

Typ

Max

Units

VOL

Output low Voltage

IOL=8 mA

VOH

Output High Voltage

10H= -1 mA

100

Output low Drive Current

Force 5V with Output low

150

rnA

110

Output High Drive Current

Force OV with Output High

-150

rnA

loz

TRI·STATE Output Current

Icc

Supply Current

0.5
2.5

V
V

1

p.A
62.5

rnA

Electrical Characteristics (ECl logic) Notes 2 and 3
Parameter

Conditions

Min

TA

Typ

Max

Units

V,L

Input Low Voltage

VEE= -4.5V

-1810

-1475

rnV

V ,H

Input High Voltage

V EE = -4.5V

-1165

-880

mV

I,L

Input low Current

0.5

I'H

Input High Current

350

lEE

Supply Current

p.A
p.A
-50

rnA

Switching Characteristics Notes 2 and 5
Parameter

Conditions

Min

Typ

Max

Units

t CDOL

Clock to Data Out low Delay

CL=50 pF

6.75

11.5

ns

t CDOH

Clock to Data Out High Delay

CL=50 pF

6.75

11.5

ns

tDIDOH

Data In to Data Out High Delay

C L =50 pF

5.5

9.5

ns

tDIDOL

Data In to Data Out low Delay

CL=50 pF

5.5

9.5

ns

ts

Data Set·Up Time

CL=50 pF

3.0

1.0

ns

tH

Data Hold Time

C L =50 pF

3.0

1.0

ns

tcpw

Clock Pulse Width

C L =50 pF

5.0

3.0

ns

tZE

Delay from Chip Select to
Active State from Hi·Z State

Cl=50 pF

8

ns

tEZ

Delay from Chip Select to Hi·Z
State from Active State

Cl=50 pF

8

ns

,

Nal.l: '"Absolute Maximum Ratings'" are those values beyand which the safety of the device cannot be guaranteed. They are not meant to Imply that the
device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for actual device operation.

Nale 2: Unless otherwise specified, minimax limits apply across the O'C t08S'C ambient temperature range in stili air and across the specified supply varia·
tlons. All typical values are for TA =2S'C and nominal supply.
Nole 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative. All voltages are referenced to ground, unless

otherwise specified.
Nale 4: When DC testing " 0 or 100 a ISO resistor should be in series wilh the output. Oniy one output should be tested at a time.
Nal.5: Unless otherwise specified, all AC measuremenls are referenced from the SO% level of the ECl input to the 0.8V level on negative Iransitions or the
2.4V level on positive transitions of the output. EeL input rise and fall times

afB

4·11

0.7 ns ±O.1 ns from 20% to 80%.

g
co

Switchi~g Time Waveforms

0C

CK

DI
1---1- !cOOL

DO
tCOOH ~-----;~

--

tDiOOH

S10pen

CS\
-3.5V
Sl CLOSED
00'

-OV

S10PEN

**

~

·S1 closed

**S1open

Test Load
7V

!
Sl
500

CL
INCLUDING PROBE
AND JIG CAPACITANCE

4·12

500

~National

level Translators/Buffers

~ Semiconductor

PRELIMINARY

C

"'C

~.
CO
~

DP8483 TTL to 100k Eel level Translator with latch
General Description

Features

This circuit translates TTL input levels to ECl output
levels and provides a fall· through latch. The outputs are
gated with CS providing for wire ORing of outputs. The
clock and chip select inputs are ECL.

• ECl control inputs

Logic and Connection Diagram

Truth Table

• 16·pin flat·pack or DIP
• CS provided for wire ORing of output bus
• 100k ECl 1/0 compatible
• 4.0 ns typical propagation delay

Dual·ln-Line Package
01

DO

CK

CS

H
L

L
H

X
X

DO

L
L
H

L

X

H
H
H
L

H = high level (most positive)
L = low level (most negative)
X

=don't care

Order Number DP,8483N or DP8483F
See NS Package N16A or F16B

4·13

Recommended Operating Conditions

Absolute Maximum Ratings (Note 1)

VEE Supply Voltage
Vcc Supply Voltage
TA> Ambient Temperature

-8V
VEE Supply Voltage
7V
Vee Supply Voltage
Input Voltage (ECL)
GNDtoVEE
Input Voltage (TTL)
-1Vto5.5V
50mA
. Output Current
Maximum Power Dissipation· at 25·C
1476mW
Molded Package
-65·Cto + 150·C
Storage Temperature

-4.5V±7%
5.0V±10%
0·Cto85·C

I

• Derate molded package 11.8 mW'"C above 25"C.

Electri~al

Characteristics (TTL Logic) Notes 2 and 3

Parameter
VIL

Input Low Voltage

VIH

Input High Voltage

Conditions

Min

Typ

Max
0.8

Units
V
V

2.0

IlL

Input Low Current

V IN =0.5V

-50

p.A

IIH

Input High Current

V IN =2.5V

1.0

p.A

VCLAMP

Input Clamp Voltage

IIN= -12mA

Icc

Supply Current

-0.8

V
30

mA

Electrical Characteristics (ECL Logic) Notes 2 and 3
Parameter

Conditions

TA

Min

Typ

Max

Units

VIL

Input Low Voltage

VEE= -4.5V

-1810

-1475

mV

VIH

Input High Voltage

VEE = -4.5V

-1165

-880

mV

IlL

Input Low Current

0.5

IIH

Input High Current

350

VOL

Output Low Voltage '

VEE = -4.5V

-1810

-1705

VOH

Output High Voltage

VEE = -4.5V

-1025

-955

VOLC

Output Low Voltage

VEE = -4.5V

VOHC

Output High Voltage,

VEE = -4.5V

lEE

Supply Current

p.A,
p.A
-1620

mV

-880

mV

-1610

mV

-90

mA

-1035

4-14

mV

Switching Characteristics Notes 2 and 4
Parameter

Conditions

Min

Typ

Max

Units

tCOOL

Clock to Data Out Low Delay

4.0

6.5

ns

tCOOH

Clock to Data Out High Delay

4.0

6.5

ns

tOIOOH

Data In to Data Out High Delay

4.0

6.5

ns

tOIOOL

Data In to Data Out Low Delay

4.0

6.5

ns

ts

Data Set·Up Time to Clock

3.0

1.0

tH

Data Hold Time

3.0

1.0

ns

tcpw

Clock Pulse Width

5.0

3.0

ns

tCSOOH

Chip Select to Data Out High Delay

3.0

4.5

ns

tcsoOL

Chip Select to Data Out Low Delay

3.0

4.5

ns

tscs

Data Set-Up Time to Chip Select

5.5

ns

3.0

ns

Note 1: ""Absolute Maximum Ratings"" are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the
device should be operated at these limits. The table of ""Electrical Characteristics"" provides conditions for actual device operation.
Note 2: Unless otherwise specified, minimax limits apply across theO'C t085'C ambient temperature range in still air and across the specified supply varia·
lions. All typical values are for 25'C and nominal supply.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative. All voltages are referenced to ground, unless
otherwise specified.
Note4: Unless otherwise specified, all AC measurements are referenced from the 1.5V level of the TTL Input and to/from the 50% point of the ECLsignal and a
50!! resistor to - 2V is the load. ECL input rise and fall times are 0.7 ns:t 0.1 ns from 20% to 80%. TTL Input characteristic is OV to 3V with tr = tf oS 3 ns
measured from 10% to 90%.

Switching Time Waveforms

cs

I

I
-ICSOOH-

-ICSOOl-

'I

DO

---{~01

I
I

I
-tCPW-

~

CK

'--...I

DI~~

-

\J\

l
IH

IS-

~

)'r\J

~r

-

,i{.

DO

I

-l-

'--J

-IOIDOl-

!cOOL

~ ....

\.

~hr

I

--

I- 10100H

ICOOH

4-15

Level Translators/Buffers

~National

a

Semiconductor

081630/083630 Hex CM08 Compatible Buffer
General Description

Features

The OS1630/0S3630 is a high current buffer intended
for use with CMOS circuits interfacing with peripherals
requiring high drive currents. The OS1630/0S3630
features low quiescent power consumption (typically
50t/W) as well as high-speed driving of capacitive loads
such as large MOS memories. The design of the OS 1630/
OS3630 is such that V cc current spikes commonly
found in standard CMOS circuits cannot occur, thereby,
reducing the total transient and average power when
operating at high frequencies.

• High-speed capacitive driver
• Wide supply voltage range,
•

Input/output may interface to TTL

•

Input/output CMOS compatibility

• No internal transient Vee current spikes
• 50t/W typical standby power

Equivalent Schematic and Connection Diagrams
Dual·ln·Line Package
vee

Vee

OUT 6

IN &

13

12

IN 1

OUT 2

14

OUT 5

IN 5

11

10

IN 2

OUT 3

OUT 4

IN 4

IN 3

GNO

84

,100

INPUT

o-_-'VI/'Ir_-'VV'II'-.....o OUTPUT

84
OUT 1

TOP VIEW

Order Number DS163OJ, DS3630J
Dr DS3630N
See NS Package J14A Dr N14A

Typical Applications
14C
CMOS
FAMILY

74C
CMOS
DSJ6JO

FAMILY

~tss.oDLINE

CMOS To Transmission Line Interface

l4C
CMOS
FAMILY

CMOS To CMOS Interface

LED Driver

4-16

Absolute Maximum Ratings

Supply Voltage
Input Voltage
Output Voltage
Lead Temperature (Soldering, 10 secondsl

16V
16V
16V
300°C

Electrical Characteristics

Temperature (TAl
051630
053630

CONDITIONS
Y'N = Vee, lOUT =-400/lA
Y'N = Vee - 2.0V, lOUT = 16 mA

I'NL

Logical "0" Input Current

V OH Logical "1" Output Voltage

Y'N = O.4V, lOUT = 16 mA

Y'N =Vee , lOUT =-400/lA
Y'N = Vee - O.4V, lOUT = 16 rnA

VOL Logical "0" Output Voltage

Y'N =OV, lOUT = 400/lA

I
I

Y'N = OV, lOUT = 16 rnA
Y'N = O.4V, lOUT = 16 rnA

Switching Characteristics

tpd1

MAX

3

15

V

-{i5
0

+125
+70

°c
°c

UNITS

Propagation Oelay to a Logical "0"

Propagation Oelay to a Logical "1"

MIN

TYP

MAX

UNITS

051630

90

200

/lA

053630

90

200

051630

0.5

3.2

/lA
mA

1.5

mA

053630

0.5

051630

-{l.15

053630

V ee -150

-1

mA

-800

/lA

051630

V ee -l

V ee -{l·75

V

053630

Vee-O.g

V ee -0.75

V

051630

V ee -2.5

V ee -2.0

V

053630

V ee -2.5

V ee -2.0

V

051630

0.75

1

V

053630

0.75

0.9

V

051630

0.95

1.3

V

053630

0.95

1.3

V

051630

1.2

1.6

V

053630

1.2

1.5

V

Vee = 5.0V, T A = 25°C unless otherwise specified
TYP

MAX

C L = 50 pF

30

45

C L = 250 pF

40

60

ns

C L - 500 pF

50

75

ns

PARAMETER
t"dO

MIN
Supply Voltage (V CCI

(Notes 2 and 3)

PARAMETER
I'NH Logical "1" Input Current

Operating Conditions

(Note 1)

CONDITIONS

MIN

UNITS
ns

C L = 50 pF

15

25

ns

C L = 250 pF

35

50

ns

C L = 500 pF

50

75

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Unless otherwise specified minimax limits apply across the -5SoC to +12SoC temperature range far the 051630 and across the oDe to
+70°C range for the OS3630. All typicals are given for Vce = S.OV and T A = 25°C.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.

4-17

Typical Performance Characteristics
VOH VI Temperature,
V,N =VCC
0.3
0.4

.,j

~

..~

~

6

>

=lou/'

VOH Active vs Temperature

VOL

-400pA

~.,

0.5
0.6

~

0.7

..

O.B
0.9

lOUT

V,"

;; 760

1.9

~

2.1

.s

g 720

>

6BO

640

2.2

"

·600

26 45 65 85 105 125

VOL

TEMPERATURE I'C).

Temperature

VI

560
-55 -35 -15 5

-55 -35 -15 5 25 45 65 B5 105 125

TEMPERATURE I'C)

25 45 65 B5 105 125

TEMPERATURE I'C)

tpdo vs Load Capacitance

Propagation Delay vs VCC

70
1.6

VIN = DV

1.5

lOUT -

16mA

TA '25'C

60

CL 250pFTA 25'C -

45

Vee'" 5.0V

g
>

1.4

~

1.3

!

>

1.2

j.

V

........

I"",

i=

;;

..

./

.....

40

i5

V

40

30

i'.

g

V

50

1.1
1.0

OV

BOO

2.3

1.1
-55 -35 -15 6

g

=

=-400~A-

1.8

2.0

6

Temperature

B40

1.7

~
>

1.0

VI

BBO

1.6

~

35

.........

go

I"",

0.9
20
-55 -35 -15 5

25 45 65 85 105 125

o

TEMPERATURE I'C)

30
100

200

300

400

3

500

11

LOAD CAPACITANCE IpF) .

13

Vee IV)

Propagation Delay
tpd1 vs Load Capacitance
60

vs Temperature
-Vee 5V
-C L -250pF

Vee'" 5.0V

r-TA '2!1'C

!

50

50

>

~

40

j

~

....
~

30

./

10

V
o

IE

/
100

200

",."

~

/

20

1"",

40

300

400

30

-

-55 -35 -15 5 25 45 65 B5 105 125

500

TEMPERATURE I'C)

LDAD CAPACITANCE IpF) .

AC Test Circuit and Switching Time Waveforms

INPUT

V'
V1NH
INPUT

OV
OUTPUT

VOH
OUTPUT
VOL

Pulse Generator cfIaraC1eristics: PRR" 1.0 MHz, pw. 500 ns, 1,. "!t < 10 ns,

CL includes probe and jig capacitance

V1N"'DtoVcc

4-18

15

Level Translators/Buffers

~National

a

Semiconductor

DS7800/DS8800 Dual Voltage Level Translator
General Description

Features

The DS7800/DS8800 are dual voltage translators
designed for interfacing between conventional TTL
or LS voltage levels and those levels associated
with high impedance junction or MOS FET-type
devices. The design allows the user a wide latitude
in his selection of power supply voltages, thus providing custom control of the output swing. The
translator is especially useful in analog switching;
and since low power dissipation occurs in the "off"
state, minimum system power is required.

•

31 volt (max) output swing

•

1 mW power dissipation in normal state

•

Standard 5V power supply

•

Temperature range:
DS7800
DS8800

•

Compatible with all MOS devices

Schematic and Connection Diagrams
v,

AI

RZ

2DK

UK

Metal Can Package

R3

II.

D1

OJ

'::"

..

OUTPUT

I(

os

,·lI

OJ

TOP VIEW

UK

Order Number DS7800H
or DS8800H
See NS Package H1OC,

V,

Typical Applications
Bipolar to MOS Interfacing

4-Channel Analog Switch

T

r

r--;;;;.~--

r,u1 ___ ..L-,1
I
SWITCH , - " -....----..
"",....... -,'" ,

rJ---~

ANALOG INPUY ,.

OTL~MDSSHln
OR
REGISTER
TTL
0$1100
I

ANALOG INPUTZ

INPUT~

OTL

LEVELS~

DR
TTL

LI---T~

INPUT
LEVELS

ANALOG INPUT)

-=

ANALOG INPUT"

STROlE

"'Analog signals within the range of +8V to -BV.

4-19

_55°C to +125°C
O°C to +70°C

-IIIV

· Absolute Maximum Ratings
VCC Supply Voltage
V2 Supply- Voltage
V3 Supply Voltage
V3-V2 Voltage Differential
Input Voltage
Storage Temperature Range
Lead Temperature (Soldering, 10 seconds)
Maximum Power Dissipation* at 2SoC
Metal Can (TO-5) Package

Operating Conditions

(Note 1)

Supply Voltage (VCC)
057800
058800

7.0V
-30V
30V
40V
5.5V
-55"C to +150·C
300·C
690mW

Temperature (TA)
057800
058800

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

+125
+70

·C
·C

-55
0

'Derate metal can package 4.6 mWfC above 25·C.

Electrical Characteristics

(Notes 2 and 3)

PARAMETER

CONDITIONS

V ,H

Logical "1" Input Voltage

Vee

= Min

V ,L

Logical "0" I nput Voltage

Vee

= Min

I'H

Logical "1" Input Current

I'L
IOL

Logical "0" Input Current

Vee

= Max, V ,N = 0.4V

Output Sink Current

Vee

= Min,

V ,N

-0.2

L057800

= 2V,

= Max, V ,N = 0.8V

IOH

Output Leakage Current

Vee

Ro

Output Collector Resistor

TA

VOL

Logical "0" 0f1tput Voltage

Vee

= Min, V ,N = 2.0V (Note

leeiMAX)

Power Supply Current

Vee

= Max, V ,N = 4.5V

Vee

= Max, V ,N = OV

Power Supply Current

/lA

1

mA

-{).4

mA
mA
mA

2.3

(Notes 4 and 7)

= 25°C

11.5

16.0

10

/lA

20.0

kn

V 2 + 2.0

7)

(Note~)

(Note 5)

V

5

1.6

I 058800

UNITS
V

I V ,N = 2.4V
I V ,N - 5.5V

= Max

Output "OFF"

MAX

0.8

V3 Open

leelMIN)

TYP
(NOTE 6)

2.0

Vee

Output "ON"

MIN

V

0.85

1.6

mA

0.22

0.41

mA

i

Switching Characteristics

T A = 25°C, nominal power supplies unless otherwise noted
\

PARAMETER
tpdO

Transition Time to Logical
"0" Output

tpd1

Transition Time to Logical
"1" Output

CONDITIONS

MIN

TYP

MAX

UNITS

TA

= 25°C, C = 15 pF(Note 8)

25

70

125

ns

TA

= 25°C, C = 15 pF

25

62

125

ns

(Note 9)

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Unless otherwise specified minImax limits apply across the -55°C to +125"C temperature range for the 057800 and across the O·C to
+70°C range for the 058800.
Note 3: All currents into. device pins shown as pOSitive, out of device pins as negative, all, voltages referenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Current measured is drawn from V3 supply.
Note 5: Current measured is drawn from VCC supply.
Note 6: All typical values are measured at T A = 25° C with VCC = 5.0V, V2 = -22V, V 3 =+8V.
Note 7: Specification applies for all allowable values of V2 and V3.
Note 8: Measured from 1.5V on input to 50% level on output.
Note 9: Measured from 1.5V on input to logic "a" voltage, plus lV.

-

-

4-20

c

en

Theory of Operation

CCI

The two input diodes perform the AND function
on. TTL input voltage levels. When at least one
input voltage is a logical "0", current from Vee
(nominally 5.0V) passes through R, and out the
input(s) which is at the low voltage'. Other than
small leakage currents, this current drawn from Vee
through the 20 kn resistor is the only source of
power dissipation in the logical "1" output state.

Since this current is relatively constant, the collec·
tor of O2 acts as a constant current source for the
output stage. Logic inversion is performed since
logical "1" input voltages cause current to be sup·
plied to O2 and to 03' And when 0 3 turns on the
output voltage drops to the logical "0" level.

°

The reason for the PNP current source, 2 , is so
that the output stage can be driven from a high
impedance. This allows voltage V2 to be adjusted
in accordance with the application. Negative volt·
ages to -25V can be applied to V2' Since the out·
put wili neither source nor sink large amounts of
current, the output voltage range is almost exclu·
sively dependent upon the values selected for V2
and V3 .

When both inputs are at logical "1" levels, current
passes through R, and diverts to transistor 0"
turning it on and thus pulling current through R2 •
Current is then supplied to the PNP transistor, 02'
The voltage losses caused by current through 0"
D3, and 02 necessitate that node P reach a voltage
sufficient to overcome these losses before current
begins to flow. To achieve this voltage at node P,
the inputs must be raised to a voltage level which
is one diode potential lower than node P. Since
these levels are exactly the same as those exper·
ienced with conventional TTL, the interfacing
with these types of circuits is achieved.

Maximum leakage current through the output tran·
sistor 0 3 is specified at 10 p.A under worst·case
voltage between V2 and V 3• This will result in a
logical "1" output voltage which is 0.2V below V3.
Likewise the clamping action of diodes D4 , Ds, and
D6 , prevents the logical "0" output voltage from
falling lower than 2V above V2, thus establishing
the output voltage swing at typically 2 volts less
than the voltage separation between V2 and V3.

Transistor O 2 provides "constant current switch·
ing" to the output due to the common base con·
nection of 02' When at least one input is at the
logical "0" level, no current is delivered to 02; so
that its collector supplies essentially zero current
to the output stage. But when both inputs are raised
to a logical "1" level current is supplied to 02'

Selecting Power Supply Voltage
The graph shows the boundary conditions which
must be used for proper operation of the unit. The
range of operation for power supply V2 is shown
on the X axis. It must be between -25V and -avo
The allowable range for power supply V3 is gov·
erned by supply V 2. With a value chosen for V2, V 3
may be selected as any value along a vertical line
passing through the V2 value and terminated by
the boundaries of the operating region. A voltage
difference between power supplies of at least 5V
should be maintained for adequate signal swing.

20

15
10

-5

·10
·15
·20
·25

Switching Time Waveforms

INPUT
OUTPUT _ _ _

!-"'\

4·21

~
c
en
CO
CO

o
o

Level Translators/Buffers

~National

~ Semiconductor
087810/088810 Quad 2-lnput TTL-M08 Interface Gate
087811/088811 Quad 2-lnput TTL~M08 Interface Gate
087812/088812 Hex TTL-M08 Inverter
General Description
These Series 54/74 compatible gates are high output voltage versions of the DM5401/DM7401
(SN 5401 /SN740 1), DM 5403/DM7403
(SN 5403/SN 7403), and DM 5405/DM7405
(SN5405/SN7405). Their open-collector outputs
may be "pulled-up" to +14 volts in the logical "1"
state thus providing guaranteed interface between
TTL and MOS logic levels.

In addition the devices may be used in applications
where it is desirable to drive low current relays or
lamps that require up to 14 volts.

Schematic and Connection Diagrams

r---....----o v",
Ok

INPUTS

,----""'-----0 v"

Uk

INPUTl

OUTPUT

0-::-+---......

OUTPUT
A

Ik

'-----+--oOND

'---~-oOND

OS7810/0S8810,OS7811/0S8811

OS7812/0S8812

Dual-In-Line Package

TOP VIEW

Oual-In-Line Package

GND

TOP VIEW

Order Number OS7810J, OS8810J,
or OS8810N
See NS Package J14A or N14A
Dual-in-Line Package
14

13

12

"

10

TOP VIEW

GNo

Order Number OS7811J, OS8811J,
OS7811W or OS8811N
See NS Package J14A, N14A or W14A

GNo

Order Number OS7812J, OS8812J,
OS7812W or OS8812N
See NS Package J14A, N14A orW14A

4-22

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Supply Voltage (Veel
DS78XX
DS88XX

7V
5.5V
14V
-65°C to +150 o e

Vee
Input Voltage
Output Voltage

Storage Temperature Range
Maximum Power Dissipation* at 2SoC
Cavity Package

Temperature (TAl
DS78XX
DS88XX

1254mW
1106mW
300°C

Molded Package
Lead Temperature (Soldering, 10 seconds I

MIN

MAX

4.5
4.75

5.5
5.25

~5

0

+125
+70

TYP

MAX

UNITS
V
V
°e
°e

"Derate cavity package 8.36 mW(e above 25°C; derate
molded package 8.85 mw(e above 25°C.

Electrical Characteristics

(Notes 2 and 3)

PARAMETER

eOND.lTlONS

MIN

VeLAMP

Input Diode Clamp Voltage

Vee = 5.0V, TA = 25°C, liN = -12 mA

V ,H

Logical "'" I nput Voltage

Vee = Min

V ,L

Logical

"a" Input Voltage

Vee = Min

IOH

Logical "'" Output Current

0.8

I V ,N = 0.8V

V OUT = 10V

"a" Output Current

IOL

Logical

Logical "1" Output Breakdown Voltage

VOL

Logical

I'H

Logical"1" rnput Current

I'L

Logical

"a" Input Current

leelMAxl

Logical

"a" Supply

"a" Output Voltage

Vee = Min, Y'N = 2.0V, V OUT = O.4V

'6
14

Switching Characteristics

tpd1

pA

0.4

V

40

pA

1

mA

-1.6

mA

5.1

mA

Vee = Max, Y'N = OV

1.0

1.8

mA

TYP

MAX

UNITS

4

12

18

ns

'8

29

45

ns

TA = 25°C, Vee = 5V
CONDITIONS

MIN

Propagation Delay Time to a

"a"
COUT = 15 pF, RL = lk

Propagation Delay Time to a
Logical "1"

!

40

3.0

PARAMETER

Logical

pA

Vee = Max, Y'N = 5.0V

Logical "1" Supply Current
(Each Gate)

tpdO

I Y'N = 5.5V

Vee = Max, Y'N = O.4V

Current

V

250

V

I V ,N = 2.4V

Vee =Max

V

mA

Vee = Min, Y'N = 2.0V, lOUT = 16 mA

(Each Gatel
leelMINI

I V ,N = O.OV

Vee = Min, Y'N = OV, lOUT = 1 mA

UNITS

V

2.0

Vee = Min,

V OH

-1.5

Not. 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except fpr "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
provides conditions for actual device operation.

Note 2: Unless otherwise specified minimax limits apply across the -55°C to +125°C temperature range for the DS7810, DS7811,and DS7812
and across the oOe to +70o e range for the DS8810, DS8811, and DS8812.
Note 3: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted.

All values shown as max or min on absolute value basis.

Typical Applications
·HOV

t12V

i

3k

I.

~

1.Sk

.v,

GROUND

INPUT

~

058810,058811,058812

Note: Normal voltages apphed to MOS shIft
registers have been shifted bV+1DVlorthis
appl,catilln.

I

~

CLOCK

1

V OD

DSB81o.0S8811,DSB812

-=1-

MOS stllft register
(EKampleMM5D6)

t1DVL-6V

4-23

IINP"'

-v,

1

MUS ROM
(ExampleMM5221)

AC Test Circujt and Switching Time Waveforms

. q--3.0V
v--1\.--

+5V

INPUT--I:-- , .•

I
I
DUTPUT--~,
I
j

I
I

I
I

1---50~---1

::

t pclO - - - ;

l:

[________ [

t= 1 MHz
tr=tf = 10ns

PW= 100 os

4·24

[____ t pd1

Level Translators/Buffers

~National

a

Semiconductor

DS78L12/DS88L12 Hex TTL·MOS Inverter/Interface Gate
General Description
The DS78l12/DS88l12 is a low power TTL to
MOS hex inverter element. The outputs may be
"pulled up" to +14V in the logical "1" state, thus
providing guaranteed interface between TTL and
MOS logic levels. The gate may also be operated

with Vee levels up to +14V without resistive
pull·ups at the outputs and still providing a guar·
anteed logical "1" level of Vee - 2.2V with an
output current of -2001lA.

Schematic and Connection Diagrams

'"

Dual-In-Line Package

sou

'"

GNO
TOP VIEW

Order Number OS78l 12J. OS88l12J
Order Number OS88l12N
Order Number 0S78l12W
See NS Package J14A. N14A or W14A
Nail. Shown" sc:hem.l.c for tadllnverllf

Typical Applications
TTL Interface to MOS ROM
With Resistive Pull·Up

TTL Interface to MOS ROM
Without Resistive Pull·Up

Ndle.... MOSRDM
(hlm,ItMMWI)

AC Test Circuits

Switching Time Waveforms

Vcc:"140V

,..

-~-

"
J - --'L

Ve<;"SV

,~,

1T.".
. .

fI'Vec" 14V

Figure 1

'

..

--13V--.

r

INPUT

e,'"''

,I

,I

,

I

,

I

I

:

fgrVec"iJIV

IpdO_1

Figure 2

4·25

1,",,-10n.

OUTPUT0cir"
,
.
---

50%---,

~

:

.

"

1---1

\
" - - I .. ,

PW'10Dn.

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

Operating Conditions

(Note 1)

15V
5.5V
15V
--£5·C to +150·C

Supply Voltage (V CC) .
DS78L12
DS88L12
Temperature (T A)
DS78L12
DS88L12

Maximum Power Dissipation* at 2~C

Cavity Package
1308mW
Molded Package
1207 mW
300·C
Lead Temperature (Soldering, 10 sec)
°Derate cavity package 8.72 mWfC above 25"C; derate
molded package 9.66 mW/·C above 25·C.

Electrical Characteristics
Logical "I" fnput Voltage

V,L

Logical "0" Input Voltage

CONDITIONS
Vee = 14.0V
Vee = Min

Logical "I" Output Voltage

VOL

Logical "0" Output Voltage

I'H

Logical "1" Input Current

V,N = 2.0V

V,N = 5.5V

Ise

V,N = 0.4V

Output Short Circuit Current

~ogical

leeH

Supply Current''''
(Each Inverter)

"I"

leeL

Supply Current - Logical "0"
(Each Inverter)

5.5
5.25

V
V

-55
0

125
70

·C
·C

TYP
1.3
1.3
1.3
1.3

Vee = 14.0V. lOUT = -2001'A
Vee = Min. lOUT = 200l'A
= OV. Vee '= Min, lOUT = -5.0I'A (Note 6)

V,N = 2.4V

Logical "0" I nput Current

4:5
4.75

2.0
2.0

= Min

V,N = 0.7V
V,N

I'L

UNITS

MIN

Vee = 14.0V
Vee

VOH

MAX

(Notes 2 and 3)

PARAMETER
V,H

MIN

VOUT = OV
(Note 4)
V,N = OV
V,N = 5.25V

11.8
14.5

Vee = 14.0V. lOUT = 12 rnA
Vee = Min, lOUT - 3.6 rnA
Vee
Vee
Vee
Vee

= 14.0V
= Max

Vee = 14.0V
Vee = Max

-10
-3

Vee = 14.0V
Vee - Max

V
V
0.7
0.7

V
V
V
V
V

1.0
0.4

V

20
10
100
100

I'A
I'A
I'A
I'A

-320
-100

-500
-180

I'A
I'A

-25
-8

-50
-15

rnA
rnA

<1
<1
<1
<1

= Max

UNITS

12.0
15.0
0.5
0.2

= 14.0V

MAX

V

Vee = 14.0V
Vee = Max

0.32
0.11

0.50
0.16

rnA
rnA

Vee = 14.0V

1.0
0.3

1.5
0.5

mA
mA

TYP

MAX

27
11

45
20

ns
ns

79
34

100
55

ns
ns

Vee = Max

Switching Characteristics T A = 2SoC, nominal power supplies unless otherwise noted
PARAMETER
tpdO

tpd1

Propagation Delay to a Logical "0"
from Input to Output
Propagation Delay to a Logical "I"
from Input to Output

CONDITIONS
TA = 25·C

Vee = 5.0V
Vee = 14.0V

(Figure 21

TA = 25·C

Vee = 5.0V
Vee = 14.0V

(Figure 21.(Note 5)

(Figure 11

(Figure 11

MIN

UNITS

I

Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating
Temperature Range" they are not meant to imply that the devices should be operated at these limits. The table of "Electrical Characteristics"
, provides conditions for actual device operation.

.

Note 2: Unless otherwise specified min/max limits apply across the -55·C to +125·C temperature range for the DS78L12 and across the O·C to
+70·C range for the DS88L 12.
Note 3: AII.currents into device pins shown as positive, out of device pins as negative, all voltages neferenced to ground unless otherwise noted. All
values shown as max or min on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: tpdl for VCC';' 5.0V is dependent upon the resistance and capacitance used.
Note 6: VOH = VCC - 1.1V for the DS88L 12 and VCC - 1.4V for the DS78L 12.

4·26

Level Translators/Buffers

~National

a

,Semiconductor

057819/058819 Quad 2-lnput TTL-MOS AND Gate

The OS7819/0S8819 is the high output voltage
version of the SN5409. Its open·collector outputs
may be "pulled·up" to 14V in the logical "1"

state thus providing guaranteed interface between
TTL and MOS logic levels.

Schematic and Connection Diagrams

.K

2.

1.6K

Dual·ln·Line Package
Vee

TOP VIEW

Order Number DS7819J or DS8819J
Order Number DS8819N
Order Number DS7819W
See NS Package J14A. N14A or W14A

4·27

0')

~

co

en

c
05

~
en
c

Absolute Maximum Ratings
Supply Voltage
Input Voltage
Output Voltage
Storage Temperature Range

7.0V
5.5V
15V
~5°C to +150°C

,

at 25°C
Cavity Package
Molded Package
Lead Temperature (Soldering, 10 sec)

Maximum Power Dissipation

"Operating Conditions

(Note 1)

Supply Voltage (V CC)
DS7819
DS8819
Temperature (T A)
DS7819
DS8819

1254mW
1106mW
300°C

,

MIN

MAX

UNITS

4.5
4.75

5.5
5.25

V
V

-55
0

+125
70

°c
°c

'Derate cavity package 8.36 mW/oC above 25°C; derate
molded package 8.85 mW/oC above 25°C.

Electrical Characteristics

(Notes 2 and 3)

PARAMETER·

CONDiTIONS

V ,H

Logical "I" I nput Voltage

Vcc = Min

V ,L

Logical "0" Input Voltage

Vcc = Min

IOH

Logical "I" Output Current

VOL

Logical "0" Output Voltage

I'H

Logical "I" Input Current

I'L

Logical "0" I nput Current

Vcc = Max, V ,N = OAV

IccH

Logical" "I" Supply Current

Vcc = Max, V ,N = 5V

ICCL

Logical "0" Supply Current

,vcc = Max, V ,N = OV

VCL

Input Clamp Voltage

Vcc = 5.0V, T A = 25°C,

Vcc = Min

TA

PARAMETER
tpdO

MAX

= 2.0V, V OUT = 10V

,N

= 4.5V, V OUT ':' 14V

IV
IV

IV

,N

= 2AV

,N

= 5.5V

20.0

MA.

1.0

mA
V

40.0

MA

1.0

mA

-1.6

mA

21.0

mA

33.0

mA

-1.5

= -12 mA

V

40.0

0.4

11.0

liN

UNITS
V

0.8

LV ,N

V

= 25°C, Vcc ": 5V
MIN

CONDITIONS

Propagation Delay to a Logical "0"
COUT = 15 pF, RL

tpd1

TYP

2.0

Vcc. = Min, V ,N = 0.8V, IOUT·= 16 mA
Vcc = Max

Switching Characteristics

MIN

Propagation Delay to a Logical ;'1"

= 400n

TYP

MAX

UNITS

16.0

24.0

ns

16.0

32.0

ns

Note 1: "Absolute Maximum Ratings" are those values beyond which the safetY of the device cannot be guaranteed. Except for "Operating

Temperature Rang~" they are not meant to imply that ~he devic:es'should be operated at these limits. The table of "Electrical Characteristics"

provides'conditions for actual device operation.

Note 2: Unless otherwise specified min/max limits apply across the -55°C to +125°C temperature range for the DS7819 and across the O°C to
+70°C range for the DS8819.
Note 3: All currents into device pins shown as positive, out of de'{ice pins as negative, all voltages referenced to ground unless otherwise noted. All

values shown as max or min on absolute value basis.

AC Test Circuit and Switching Time Waveforms
I

\
,.5V1\

1.§V

/

'5V

r / :' Ie""
~'

INPUT
-

r;

f~

~'

,"V'"
~l4V "
/

OUTPUT
1=1 MHz

t,-1t=10ns
PW"lUD~1

4-28

I~,

-

-·l

~

Section 5
Display Controllersl
Drivers

TEMPERATURE RANGE
O"C to + 70"C

-SS"C to + 12S"C

DP8350
AN-199

AN-212
AN-243
AN-270

* DS55493
* DS55494

DS7880

DS7889
DS7897A

DP-XXX
DS75491
DS75492
DS75493
0575494
058654
DS8656
DS8664
058666
DS8669
DS8692
DS8693
DS8694
DS8859A
058861
058863
DS8867
DS8869A
DS8870
058871
DS8872
088873
DS8874
058877
DS8880
DS8881
DS8884A
058885
DS8887
DS8889
DS8891 A
DS8897A
DS8963
058973
DS8975
AN-84
AN-99

DESCRIPTION

Series CRT Controllers
A Low Component Count Video Data Terminal
Using the DP8350 CRT Controller and the
I NS8080 CPU
Graphics Using the DP8350 Series of CRT
Controllers
Graphics/Alphanumerics Systems Using
the DP8350
Software Design for a High Speed (38.4 kbaud)
Data Terminal
Advanced Graphic CRT Controller, AGCRTC
Quad Segment Driver
Hex Digit Driver
Programmable Quad Segment Driver
Saturating Hex Digit Driver
8-0utput Display Driver
Print Head Diode Array
14-Diglt Decoder/Driver
14-Digit Decoder/Driver (PaS Systems)
Dual Digit, BCD-to-7-Segment LED Decoder/Driver
8-0utput, 350 mA, Transistor Array
Printing Calculator Solenoid Driver
Printing Calculator Solenoid Driver with Clock
Serial Input Hex Latch LED Driver (High Level)
MOS, LED 5-Segment Driver
MaS, LED 8-Diglt Driver
B-Segment LED Constant Current Driver
Serial Input, Hex Latch LED Driver (Low Level)
Hex LED Digit Driver
8-Digit LED Driver
9-Dlgit LED Driver
9-Digit LED Driver, Low Battery Indicator
9-Digit Shift Input LED Driver
6-Digit LED Driver
7-Segment DecoderlDriver
16-Digit Vacuum Fluorescent Grid Driver
7-Segment DecoderlDriver
MOS-to-High Voltage Cathode Buffer
8-Digit High Voltage Anode Driver
B-Segment High Voltage Cathode Driver
a-Diglt High Voltage Anode Driver
B-Digit High Voltage ~node Driver (Low Level)
18V DS8863
9-Digit LED Driver, 5.5V, Vee
9:Digit L!=P Driver with Low Battery Indicator
Driving (-Segment Gas Discharge Display Tubes
with National Semiconductor Circuits
Driving 7-Segment LED Displays with
National Semiconductor Circuits

• Also available screened in accordance with MIL-STD·883 Class B. Refer to National Semiconductor's "The Reliability Handbook".

PAGE
NUMBER
5-6
5-30

5-44
5-48
5-76
5-104
5-106
5-106
5-109
5-111
5-113
5-113
5-117
5-120
5-123
5-126
5-126
5-126
5-133
5-136
5-136
5-139
5-133
5-141
5-143
5-143
5-143
5-145
5-147
5-149
5-152
5-156
5-158
5-160
5-160
5-164
5-160
5-136
5-166
5-166
5-169
5-173

en
CD
CD

!l

ci"
::::J

DP8350 CRT CONTROLLER SERIES SELECTION GUIDE
Item
No.

1
2
3

DP8350
Value

DP8352
Value

. Value

Dots per Character (Width)

(5)

(7)

(7)

Scan Lines per Character (Height)

(7)

(9)

(9)

7

9

9

Parameter

Character Font Size
(Hefeience Only)

DP8353

CD

4

Character Field Cell
Size

10

12

12

5

Number of Video Characters per Row

80

32

80

6

Number of Video Character Rows per Frame

24

16

25

7

Number of Video Scan Lines (Item 4 x item 6)

240

192

300

8

Frame Refresh Rate (Hz)

9

Delay after Vertical Blank Start to Start of Vertical Sync
(Number of Scan Lines)

10

Dots per Character (Width)
Scan Lines per Character (Height)

f1 =60 10=50

C)

c
is:

f1 =60

fO=50

f1 =60

10=50

4

30

27

53

a

32

Vertical Sync Width (Number of Scan Lines)

10

10

3

3

3

3

11

Interval between Vertical Blank Start and Start of Video
(Number of Scan Lines of Video Blanking)

20

72

68

120

20

84

12

Total Scan Lines per Frame (Item 7 + Item 11)

260

312

260

312

320

384

13

Horizontal Scan Frequency (Line Rate) (Item 8 x Item 12)

15.6 kHz

15.6 kHz

19.20 kHz

14

Number of Character Times per Scan Line

100

50

102

1.56 MHz

0.78 MHz

1.9584 MHz

641 ns

1282 ns

510.6 ns

6

5

15

Character Clock Rate (Item 13 x Item 14)

16

Character Time (1

17

Delay after Horizontal Blank Start to Horizontal Sync Start
(Character Times)

a

18

Horizontal Sync Width (Character Times)

43

4

9

19

Dot Frequency (Item 3 x Item 15)

10.92 MHz

7.02 MHz

17.6256 MHz

91.6 ns

142.4 ns

56.7 ns

1

a

1

~

~

Item 15)

20

Dot Time (1

21

Vertical Blanking Output Stop before Start of Video
(Number of Scan Lines)

Item 19)

22

Cursor Enable on All Scan Lines of a Row? (Yes or No)

Yes

Yes

Yes

23

Does the Horizontal Sync Pulse Have Serrations during
Vertical Sync? (Yes or No)

No

Yes

No

24

Width of Line Buffer Clock Logic "0" State within a
Character Time (Number of Dot Time Increments)

4

5

5

25

Serration Pulse Width, if Used (Character Times)

-

4

-

26

Horizontal Sync Pulse Active State Logic Level (1 or 0)

1

·0

1

27

Vertical Sync Pulse Active.State Logic Level (1 or 0)

a

a

1

28

Vertical Blanking Pulse Active State Logic Level (1 or 0)

1

1

1

Video Monitor Format: Ball Brothers TV·12, TV·120 or Equivalent. (DP8350)
Video Monitor Format: RS·170-Compatible (Standard American TV). (DP8352)
Video Monitor Format: Motorola M3003 or Equivalent. (DP8353)

5-3

Selection Guide,
LED DISPLAY SEGMENT DRIVERS

Driversl
Package

4
4
5
6
6
8
8
14

10/Segment
(mA)
Sink*
(Common
Anode)

Source
(Common
Cathode)
30
50
50

50
50
32
32

18
50
25

VMAX
(V)

Device Number

Comments

Input

S,upply

10
15
15
5.5
5.7
10
36
6.6

10
'10
10
7
7.
7
36
7

OOeto +70°C
Programmable constant current

Programmable output, active high latch
Programmable output, active low latch
Constant current output
BCO input, dual·display driver

-55°C to +125°C

0575493
0575491
058861
058859A
058869A
058867
088654
088669

0555493

Page
No.
5·109
5-106
5-136
5·133
5·133
5·139
5-113
5-123

* Digit drivers ~ith o~tPut sink capability may be used to drive segments ~f "common anode" displays

LED DISPLAY DIGIT DRIVERS

~

Driversl
Package
4
6
6
6
6
8
8
8

10/Digit
(mA)
Sink
(Common
Cathode)

Source
(Common
Anode)
50

50
150
250
350
40
350
500
500
50 '

9

10
14

40
40
50
100
100
400
80

VMAX
(V)
Input

Supply

10
10
10
10
10
11
25
15
23
36
11
10
10
10
9.5
10

10
10
10
10
10
11
25
10
18
36
11
11
10
10
10
45
10

10

10

11

-

Device Number

Comments

O°C to +70°C

0575492 pinout, 4.5V to 9V systems
Enable control
0875492 pinout, Darlington output
' Open·collector saturating outputs

Low battery indicator
Serial shift register input
3-cell operation-low battery indicator
No low battery indicator
8erial input
On-board osc., 4 line code input, low battery

0875491
088877
0875494
0875492
088870
088871
088692
088863
088963
088654
088872

-55°C to +125°C

Page
No.

088873
088874
088973
058975
083654
088664

5-106
5-147
5-111
5-106
5·141
5-143
5-126
5-136
5-136
5-113
5·143
5-143
5-145
5-166
5-166
3·29
5-117

088666

5-120 ----

0855494

indicator

80

13

6 sink, 8 source outputs

GAS DISCHARGE DISPLAY DRIVERS
Device
Type
Cathode drivers

Drivers!
Package
7

Device Number
O°C to +70°C -55°C to +125°C
OS8880
OS8884A

7

BCD to 7·segment
BCD to 7·segment with comma
and OP
MOS to high voltage cathode buffer

8
6
8
8

Active
Active
Active
Active

OS8889

7

Anode drivers

Comments

high inputs
low inputs
high inputs
low inputs

OS7880

OS8885
OS8891A
OS8887
OS8897A

Page
No.
5·149
5·156

OS7889

5·158
5·160

OS7897A

5·164
5·160
5·160

VACUUM FLUORESCENT DISPLAY DRIVERS
Device
Type

Drivers!
Package

Comments

Device Number
O°C to +70°C -55°C to +125°C

Page
No.

Ground driver
(segments)

8

7·segment plus DP

OS8654

5·113

Anode driver
(digit)

8
16

4 line BCD input

OS8654
OS8881

5·113
5·152

PRINTER DRIVERS
Device
Type
Mechanical
printer

Thermal
printer

Drivers!
Package

Description
Relay driver
10 hammer serial input driver
Seiko model 310 print head,
interface set
8·digit driver
Diode matrix

Device Number
O°C to +70°C -55°C to +125°C
OS3680
OS3654
OS8692,
OS8693,
OS8694
OS8654
DS8656

5·5

Page
No.
3·44
3·29
5·126
. 5·126
5·126
5·113
5·113

.
Semiconductor

~National

a

Display Controllersl Drivers

DP8350 Series CRT Controllers
General Description
The DP8350 Series of CRT Controllers are single-chlp
bipolar (12L technology) circuits In a 4O-pln package. They'
are designed to be dedicated CRT display refresh circuits. Three standard products are available, designated
DP8350, DP8352, DP8353. Custom devices, however, are
available In a broad range of mask programmable options.
The CRT Controller (CRTC) provides an Internal dot rate
crystal controlled oscillator for ease of system design.
For systems where a dot rate clock Is already provided,
an external clock may be Inputted to the CRTC. In either
case system synchronization Is made possible with the
use of the ~uffered Dot Rate Clock Output.
The DP8350 Series has 11 character generation related
timing outputs. These outputs are compatible for systems with or without line buffers, using character ROMs,
or DM86S64-type latch/ROM/shift register circuits.
12 bits (4k) of bidirectional TRI-STATEG' character memory addresses are provided by the CRTC for direct Interface to character memory.
Three on-chlp registers provide for external loading of the
row starting address, cursor address, and top-of-page
address.
A complete set of video outputs Is available Including
cursor enable, vertical blanking, horizontal sync, and
vertical sync.
The DP8350 Series CRTC provides for a wide range of
programmablility using internal mask programmable
.
ROMs:
TRI-8TATE Is a registered trademark of National Semiconductor Corp.

• Character Field (both number of dots/character and
number of scan lines/character),
• Characters per Row
• Character Rows per Video Frame
• Format of Video Outputs
The CRTC also provides system sync and program inputs
Including Refresh Control, Reset, and Address Mode.

Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

Internal crystal controlled dot rate oscillator
External dot rate clock Input
Buffered dot rate clock output
Timing pulses for character generation
Character memory address outputs (12 bits)
Internal cursor address register
Internal row starting address register
Internal top-of-page address register (for scrolling)
Programmable horizontal and vertical sync outputs
Programmable cursor enable outputProgrammable vertical blanking output
2 programmable refresh rates, pin selectable
Programmable characters/row (128 max.)
Progammable character field size (up to 16 dots x 16
scan line field size)
Programmable scan lines/frame (512 max.)
Programmable character rows/frame
Single +5V power supply
Inputs and outputs TIL compatible
Direct Interface with DM86S64 character generator
Ease of system design/application

Connection Diagram
REGISTEft SELECT B

40

VCC (+5 VI

VERTICAL BLANKINII

39

REGISTEft SELECT A

REfRESH CONTROL

38

REGISTER LOAD

VERTICAL SYNC

37

RAM ADDRESS ENABLE

FULUHALF

36

At!

35

Al

r

couJ:I~~

LC2
LCI

A2

LCD
CLEAR LINE COUNTER
ADDIlESS MODE
LINE BUFFEft
RECIRCULATE ENABLE
LINE RATE CLOCK

A4
11

OUTPUTS

A3
10

DP 8350
OP 8352
OP 8353

A5

A&

RAM ADDRESS
COUNTER
OUTPUTSI
REGISTER
INPUTS

12

A7

13

As

HORIZONTAL SYNC

14

A9

11m'!

15

AID

LINE BUFFER CLOCK
EXTEftNAL CHARI
LINE CLOCK
[lOOi VIDEO SHIFT REGISTER

16

A11
LATCH CHARACTER
IlENERATOR ADDRESS
DOT RATE CLOCK

CURSOR ENABLE

19

22

GND

20

21

17
18

Xl} CRYSTAL
OSCILLATOR
X2
INPUTS

Order Number DP8350N, DP8352N or DP8353N
See NS Package N40A

5-6

C

Block Diagram

"tJ
CO
Ct.)

g

en

...i"CD
en

OUTPUT
ENABLE

REGISTER

LOAD
REGISTER
4

SELECT A

REGISTER

SELECT B

IiDRIZONTAL
SYNC

LINE BUFFER
RECIRCULATE
ENABLE

VERTICAL
SYNC

CLEAR LINE

VERTICAL
BLANKING

COUNTER

LINE RATE

CURSOR

CLOCK

ENABLE

LINE BUFFER
CLOCK

RESET

TIMING AND CONTROL lOGIC
LATCH CHARACTER
GENERATOR ADD.

4

ADDRESS MODE

LOAD VIDEO

SHIFT REGISTER
REFRESH

CONTROL

DOT RATE

CLOCK

~

EXTERNAL

CRYSTAL

CHAR/LINE
CLOCK

LINE COUNTER OUTPUTS

5·7

The Video Display
into cell groupings that define video rows. These cells
are accessed by a specific horizontal address output
(4096 maximum) and are resolved by a row scan-linecounter output' (16 maximum) as shown in Figure 2. The
relation of the video portion of a frame to the horizontal
blanking and vertical blanking intervals is shown in
Figure 3 in a two-dimensional format.

Discussion of the CRT Controller necessitates an understanding of the video display as presented by a raster
scan monitor. The resolution of the data displayed on the
monitor screen Is a function of the dot size. As shown In
Figure 1, the dot size is determined by the frequency of
the system dot clock. The visible size of the dot can be
modified to less than 100% by external gating of the
serial video data. The CRT Controller organizes the dots

-/

/ - DOT INTERVAL

SYSTEM
DOT CLOCK

SERIAL VIDEO DATA
INPUTEO TO MONITOR
, -VISIBLE INTENSIFIED DDT

_____•_ _ _r------.....-

VIDEO

100% DOTS

{

•

•

•

•

•

50% DOTS

\

GATED DDT PROVIDES SPACE
BETWEEN CONSECUTIVE DOTS

Figure 1. Dot Definition

SCAN LINE (ELECTRON BEAM TRACE)

\,

ADDRESS HHH

,

.A

I
I

I.
I.

I

I.

I
ROW

P'
I.

I

I
I
I

I

\

DDT INTERVAL

Figure 2. Character Cell Definition
(Example Shown is a 7 x 10 Character Cell)

Figure 3. Frame Format Definition

5-8

Character Generation/Timing Outputs
of video characters per row. For custom requirements,
the duty cycle of this output Is mask programmable.

The CRT controller provides 11 Interface timing outputs
for line buffers, character generator ROMs, DM86S64type latch/ROM/shift register combination character
generators, and system status timing. All outputs are
buffered to provide TTL compatible direct interface to
popular system circuits such as:

Line Buffer Recirculate Enable: This output is provided
to control the input loading mode of the data shift regis'
ter (line buffer) when used in a system design. The format
of this output is Intended for shift registers that load ex·
ternal data into the input with the mode control in the
low state, and load output data into the input (recircu·
late) with the mode control in the high state. This output
will transition to the low state, synchronous with the line
rate clock falling edge, for one complete scan line of each
row. The pOSition of this scan line will either be the first
scan line of the addressed row, or the last scan line of
the previous row depending upon the logic level of the
address mode input (pin 11), tabulated in Table 3.

• DM86S64 Series Character Generators
• MM52116 Series Character ROMs
• DM74166 Dot Shift Register
• MM5034, MM5035 Octal 80·Blt Shift Registers (Line
Buffers)
Dot Rate Clock: This output is provided for use in
system synchronization and interface to the dot shift
register used in character generation. This output is
non·inverting with respect to an external clock applied
to the X1 oscillator input (see Figure 6). The dot rate
clock output exhibits a 50% duty cycle. All CRTC output
logic transitions are synchronous with the rising edge of
the Dot Rate Clock output.

Memory Address Outputs/Inputs and Registers
Address Outputs (Ao-A11 ): These 12 address bits (4k)
_ are bi-directional TRI-STATE@ outputs that directly inter·
face to the system RAM memory address bus.

Latch Character Generator Address (Character Rate
Clock): This output provides an active clock pulse at
character rate frequency which is active at all times.
The rising edge of this pulse is synchronous with the
beginning of each character cell. This output is in·
tended for direct interface to character/video genera·
tion data latch registers.

In the output mode (enabled), these outputs will exhibit
a specific 12·bit address for each video character cell to
be displayed on the CRT screen. This 12-bit address
increments sequentially at character rate frequency
and is valid at the address bus 2 character times prior to
the addressed character appearing as video on the CRT
screen. This plpelining by 2 characters is provided to
allow sufficient time for first, accessing the RAM memory, and second, accessing the character generation
memory with the RAM memory data. Since a character
cell is comprised of several scan lines of the CRT beam,
the sequential address output string for a given video
'row is identically repeated for each scan line within the
row. The starting address for each video scan line is
stored within an internal 12-bit register called the Row
Start Register. At the beginning of each video scan line,
the internal address counter logic is' preset with the
contents of the Row Start Register (see Figure 4). To
accomplish row by row sequential addreSSing, internal
logic updates the Row Start Register at the beginning of
the first scan line of a video row with the last address + 1
of the last scan line of the previous video row. Since the
number of address locations on the video screen display
is typically much less than the 4k dimension of the 12·bit
address bus, an internal 12-bit register called the Top Of
Page Register, contains the starting address of the first
video row. Internal logic loads the contents of this top
of page register into the Row Start Register at the beginning of the first scan line of the first video row. The Top
Of Page Register is loaded with address zero whenever
the Reset input is pulsed to the logic "0" state.

Line Rate Clock: This output provides an active clock
pulse at scan·line rate frequency (horizontal frequency),
which is active at all times. The falling edge of this pulse
is synchronous with the beginning of horizontal blanking~
This output is intended for direct interface to character
generation scan line counters.
Load Video Shift Register: This output provides a char·
acter rate signal intended for direct interface to the video
dot shift register used in character generation. Active low
pulses are outputted only during video time. As a result
of the inactive time, horizontal and vertical video blank·
ing can be derived from this output signal.
Clear Line Counter: This output signal is active only
during the first scan line of all rows. It exhibits an active
low pulse identical and synchronous to the Line Rate
Clock and is provided for direct interface to character
generation scan line counters.
Line Counter Outputs (LC o to LC 3): These outputs clock
at line rate frequency, synchronous with the failing edge
of the line rate clock, and provide a consecutive binary
count for each scan line within a row. These outputs are
provided for system deSigns that require decoded information indicating the present scan line pOSition within a
row. These outputs are always active, however, the next
to the last row during vertical blanking will exhibit an invalid line count as a function of internal frame synchronization.

In the input mode (disabled), external addresses can be
loaded into the internal 12·bit registers by external control of the register select A, register select B, and register
load inputs (see Table 1). As a result of specific external
loading of the contents of the Row Start Register, Top
Of Page Register, and the Cursor Register, row by row
page scrolling, non-sequential row control, and cursor
location control, can easily be accomplished.

Line Buffer Clock: This output directly interfaces to data
shift registers when they are incorporated as line buffers
in a system design (see Figure 16). This signal is active at
character rate frequency and is intended for shift regis·
ters that shift on a falling edge clock. This output is inac·
tive during all horizontal blanking intervals yielding the
number of active clocks per scan iine equal to the nUl)1ber
5·9

During the non-video intervals, the address output operation Is modified. During all horizontal blanking intervals,
the incrementing of the address counter Is inhibited and
the address count is held constant at the last video ad'
dress + 1. For example, if a video row has an 80 character
cell format and addressing for the video portion of a
given scan line starts at address 1, the address counter
will increment up through address 81. Address 81 is
held constant during the horizontal blanking interval
until 3 character times before the next video scan line.
At this pOint, the address counter is internally loaded
with the contents of the Row Start Register which may
contain' address 1 or 81 as a function of internal control,
or a new address that was loaded from the external bus.
During vertical blanking, however, this loading of the
internal address counter with the contents of the Row
Start Register is inhibited providing scan line by scan
line sequential address incrementing. This allows mini·
mum access time to the CRTC when the address counter
outputs are being used for dynamic RAM'refresh.

The Row-Start Register (RSR) holds the starting address
for each scan, line of the video portion of a frame. The
video addreSSing format is completely determined by the
contents of this register. With no external loading, the
RSR is automatically loaded by internal control such
that row-by-row sequential addreSSing is achieved. Referring to Figure 4, the RSR is loaded automatically once
for each video row during the first addressed scan line.
The source of the loa,ded address is internally controlled
, such that the RSR load for the first video row comes from
the Top-at-Page Register. The RSR load for all subsequent video rows comes from the address counter which
holds the last displayed address + 1. If nOh-sequential
row formatting is desired, the RSR can be loaded externally with a 12-bit address. However, this external load
must be made prior to the internal automatic load. Generally speaking, the external load to the RSR should be
made during the video domain of the last addressed scan
line of the previous row. Figure 4 indicates the internal
automatic loading intervals which must be avoided, if the
load must be made during the horizontal blanking inter·
val. Once an external address has been loaded to the
RSR, the next occurring internal automatic RSR load will
be inhibited by internal detection logic. If an external
load is made to the RSR during the vertical blanking
interval, the 12-bit address is loaded into the Top-OfPage Register instead 'of the RSR as a, result of internal
control. This internal function 'is performed due to the
fact that the address loaded into the RSR for the first
video row can only come from the Top-Of-Page Register.

RAM Address Enable Input: At all times the status of
the bi-dlrectional address outputs is controlled exter·
nally by the logiC level of the enable input. A 'low' logic
level at this input places the address outputs in the TRISTATE® (disabled) input mode. A 'high' logic level at
this input places the address outputs in the active (enabled) output mode.,'
Register Loaci/Select Inputs: When the Register Load
input is pulsed to the logic 'low' state, the Top Of Page,
Row Start, or Cursor Register will be loaded wit!'J a 12-bit
address which originates from either the internal address
counter or the external address bus (refer to discussion
on register loading constraints). The destination register
is selected prior to the load pulse by setting the register
select inputs to the appropriate state as defined in
Table 1.

The Top·Ot·Page register (TOPR) holds the address of the
first character of the first video row. As a function of
internal control t~e contents of this register are loaded
into the RSR at the beginning of the first addressed
scan line of the first video row (see Figure 4). This
loading operation is strictly a function of internal
control and cannot be overridden by an external load to
the RSR. For this reason, any external load to the RSR
during the vertical blanking interval is interpreted
internally as a TOPR load. When the Reset input is
pulsed to the logic "0" state, the TOPR register is
loaded with address zero by internal control_ This yields
a video page display with the first row of sequential
addressing beginning at zero. Page scrolling can be
accomplished by externally loading a new address into
the TOPR. This loading operation can be performed at
any time during the frame prior to the interval where the
TOPR is loaded automatically into the RSR (see Figure
4). Once the TOPR has been loaded, it does not have to
be accessed again until the contents are to be modified,

Table 1. Register Load Truth Tabte
Register'
Select A
(Pin 39) ,

Register
Select B
(Pin 1)

0
0
1
1

0
1
0
1

X

X

Register Register Loading
Load Input
Destination
(Pin 38)
0
0
0
0
1

NoSelect
Top-of·Page
' Row-StartCursor
No Load

"During the vertical blanking interval, a load to this register is internally routed to the Top-OI·Page register.

The Cursor Register (CR) holds the present address of
the cursor ,location. A true comparison of the address
counter outputs ~nd the contents of the ,CR results in a
Cursor Enable output Signal delayed by two character
times. When the Reset input is pulsed to the logic "0"
state, the contents of the CR are set to address zero by
internal control. Modifying the contents of the CR is
accomplished by external loading at ,aflY time during
this frame. Typically, loading is performed only during.
intervals when the address outputs are not actively,
controlling the video display. Once the CR has been
loaded, it does not have to be accessed again until the
contents are to be modified.

Internal Registers and Loading Constraints: There are 3
internal 12-bit registers that facilitate video screen
management with respect to row-by-row page scrolling,
non-sequential row control and cursor location. These
registers can be loaded with addresses from the external address bus while the address outputs are disabled
(RAM address enable inut in the low state), by controlling the register select and load inputs within the constraints of each register.

5-10

C

"'C
CO
c;,.)

en
o

en
CD

First Addressed Scan Line of a Video Row

...

iii"

(J)
~

HORIZONTAL

IRSR

S~~~kll~~"

8LANKING~

IAI

/

VIDEO - - - - - - - - ;

- . -

1-2~1 1~3-1

-1-

2nd Through Last Addressed Scan Lines of a Video Row
LINE BUFFER

EN~mRg~}~J~

---""1:\-----------------------,---\

~

____________________________ J

r- HORIZONTAL 8LANKING~ /

VIDEO

I

\

Note 1: Dimensions are in character time intervals.
Note 2: "A" denotes the interval that the address counter is
preset with the contents of the Row Start Register.
Note 3: "RSR" denotes the interval that the Row Start Register
is internally loaded with either the contents of the Top·Of-Page
Register (1st video 'row) or the last video address + 1 from the
address counter.

Figure 4. Automatic Internal Loading Intervals

Video-Related Outputs
Horizontal Sync: This output provides the necessary
scan line rate sync signal for direct interface to either
three-terminal or compOSite sync monitors. The pulse
width, position, and logic polarity are mask programmable, in character time increments, for custom requirements. This output may also be mask programmed to
have RS-170 compatible serration pulses during thevertical sync interval (refer to DP8352 format and Figure 15)_

is delayed by 2 character times so that it will be coincident with the video information resulting from the corresponding address. Mask programmability allows the
cursor enable output signal to be formatted such that a
signal will be outputted for all addressed scan lines of a
video character cell or any single scan line of that cell.
The cursor enable output signal is inhibited during the
horizontal and vertical blanking intervals so that video
blanking is maintained. When the addressing is advanced by setting the address mode input (pin 11) in the
logic "0" state, the cursor enable signal will also be
shifted with respect to the scan line count. Specifically,
for a character cell with the cursor output active on all
addressed scan lines of the cell, the first scan line of
the cursor Signal will occur at the last scan line count of
the previous video row, and the last scan line count of
the addressed character cell will have no cursor output
signal. This mode of operation gives rise to a unique
situation for the first video row where the first addressed
scan line of a character cell has no cursor output signal
Since its advanced scan line pOSition is inhibited by the
vertical blanking interval.

Vertical Sync: This output provides the necessary frame
rate sync Signal for direct interface to either three-terminal
or composite sync monitors. The pulse width, position,
and logic polarity are mask programmable, in scan line
increments, for custom requirements.
Cursor Enable: This output provides a signal that is intended to be combined with the video signal to display a
cursor attribute which serves as a visual pointer for video
RAM location. Internally, the 12-bit address count is
continuously being compared with the 12-bit address
stored in the Cursor Register. When a true compare is
detected, an active high level signal will be present at
the Cursor Enable output, delayed by 2 character times
after the corresponding address bus output. The signal

5-11

CRT System Control Functions

Table 3. Address Mode Truth Table
Address Mode New Row Addressing At Address
Input (Pin 11) Outputs and Line Buffer Recirculate
Enable Logic .Low Level
(Logic. Level)
(Scan Line Position)

Refresh Control Input: This Input provides a logic level
selectable CRT system refresh rate. Typically, this input
will select either a 60 Hz or 50 Hz refresh rate to provide
geographical marketing flexibility. However, mask pro·
grammability provides the capability of a wide range of
frequencies for custom requirements. For definition of
the input logic truth table and the refresh rate format,
refer to Table 2 and the standard device type format
tables.

0
1

Full/Half Row Control: This control input is provided
for applications that require the option of half-page ad·
dressing. As an example, if the normal video page format
is 80 characters/row by 24 rows, setting this input to the
logic "0" state will cause the video format to become
evenly spaced at 80 characters/row by 12 rows. Specifically, when this input is in the logic "0" state, row addressing is repeated for every other row. This yields successive groups of two rows of identical addressing. The
second row of addressing, however, has the Load Video
Shift Register output and the Cursor Enable output internally inhibited to provide the necessary video blanking.
Setting this input to the logic "1" state yields normal
frame addressing.

Table 2. Refresh Rate Select Truth Table
Refresh Control
Frame Refresh Rate
(Pin 3)
Logic Level
Symbol DP8350 DP8352 DP8353
1
0

f1

to

60Hz
50Hz

60Hz.
50Hz

60Hz
50Hz

Vertical Blanking Output: This output provides a signal
that transitions at the end of the last video scan line of
the last video row and indicates the beginning of the
vertical blanking interval. This signal transitions back to
the inactive state during the row of scan lines just prior
to the first video row. The transition position within this
last row of vertical blanking, as well as the active logic
polarity, is a function of the particular deVice format
(item 21 of the format tables) or is mask programmable
for custom requirements.
Address Mode: When a system utilizes a line buffer shift
register, the first scan line of addressing for a row is used
to load the shift register. As a result of this loading
operation, addressing for a particular row will not begin
accessing the video RAM until the second scan lirie of
addressing for the row. It also follows that the first scan
line of a row can only exhibit addressed data for the pre·
vious video row that is in the shift register. This offset in
addressing becomes a problem for character generation
designs that output video on the first scan line of a row
(with respect to the line counter outputs). The result is
invalid data being displayed for the first scan line. One
solution would be to utilize a character generation de·
Sign that began outputting video on the second scan line
of a row. However, since most single chip character
generators begin video on the first scan line, the DP8350
series CRT controller provides a pin selectable advanced
addressing mode which will compensate for addressing
shifts resulting from shift register loading. Referring to
Table 3, ahigh logic level at this input will cause address·
ing to be coincident with the scan line counter positions
of a row, and a low logic level at this input will cause
addressing to start on the last scan line counter position
of the previous row. This shifted alignment of the ad·
dressing, with respect to the designated scan lines of a
row, is diagrammed in Figure 5. Characteristically, it fallows that, when addressing is advanced by one scan line,
the Line Buffer Recirculate Enable output and the Cursor
Enable output are'also advanced by one scan line. This
advanced position of the Cursor Enable output may
deserve special consideration depending upon the system design.

Last scan line of previous row
First scan line of row.

External Character/Line Rate Clock: This input is intended to aid testing of the CRTC and is not meant to be
used as an 'active input in a CRT system. When this
input is left open, it is guaranteed not to interfere with
normal operation.
Reset Input: This input is provided for power-up synchronization. When brought to the logic "0" state, device
operation is halted. Internal logic is set at the beginning
of vertical blanking, and the Top-Of-Page Register and
the Cursor Register are loaded with address zero. When
this input· returns to the logic "1" state, device operation
resumes at the vertical blanking interval followed by
video addressing which begins at zero. This input has
hysteresis and may be connected through a resistor to
Vee and through a capacitor to ground to accomplish a
power-up Reset. The logic "0" state should be maintained for a minimum .of 250ns.
ADDRESS MODE INPUT = "1'"
LINE COUNTER
,OUTPUT COUNT

ADDRESSEO
SCAN LINES
FOR VIDEO ROW
ARE COINCIDENT
WITH LINE
COUNTER
POSITION

El El • El El El El
El • • ElEl El El
ElEl.ElEl El El
ElEl.ElElElEl
ElEl.ElElElEl
ElEl.ElElElEl
El • • • ElElEl
ElElElBElBB
BBBBBBB
BBBBBBB

0
1
2
3
4
5
6
7
8
9

VIDEO
ROW

X

ADDRESS MODE INPUT = "0"
LINE COUNTER
,OUTPUT COUNT

•• ••• ••
•• B .
B

ADDRESSED
SCAN LINES
FOR VIDEO ROW
ARE ADVANCED
BY 1 SCAN
LINE WITH
RESPECT TO
LINE COUNTER
POSITION

B
B B
B B
B B.
B
B.
• •
B •
B .B
B
B B B B B
El El El El El
El
B
B
B

B B
B B
B B
BB
B B
B B
B B
El El
El El

0 0 0 0 0 DO

0
1
2
3
4
5
6
7
8
9

VIDEO
ROW

X

, Figure 5. Address Mode Functionality
5-12

Table 4. Typical Crystal Specifications

Crystal Inputs X1 and X2: The "Pierce"-type oscillator
is controlled by an external crystal providing parallel
resonant operation_ Connection of external bias components is made to pin 22 (X1) and pin 21 (X2) as shown in
Figure 6_ It is important that the crystal be mounted in
close proximity to the X1 and X2 pins to ensure that
printed circuit trace lengths are kept to an absolute minimum _Typical specifications for the crystal are shown in
Table 4 for each of the standard products, DP8350,
DP8352, and DP8353_ When customer mask options require higher frequencies, it may be necessary to change
the crystal specifications and biasing components_ If
the CRTC is to be clocked by an external system dot
clock, pin 22 (X1) should be driven directly by Schottky
family logic while pin 21 (X2) is left open. The typical
threshold for pin 22 (X1) is Vcc/2.

Specification

Parameter
DP8350

I

DP8352.

I

DP8353

I

Vee
ell

30pF

Figure 6. Dot Clock Oscillator Configuration with
Typical External Bias Circuitry Shown

Custom Order" Mask Programmability: The DP8350

Table 5. Mask Programming Limitations

Series CRT controller is available in three standard options designated DP8350, DP8352, and DP8353. The
functional format of these devices was selected to meet
the typical needs of CRT terminal designs. In order to
accommodate specific customer formats, the DP8350
series CRT controller is mask programmable with a
diverse range of options available. The items listed in
the program table worksheet indicate the available
options, while Table 5 tabulates the programming constraints.

Designation

Parameter

Min.
Value

Max.
Value

Dot Rate Frequency
DC 30MHz
Character Rate Frequency
DC 2.5MHz
Line Buffer Clock Logic "0"
Width (Item 20 x Item 24) 200ns
Item 3. Dots per Character Field
Width
..
4
16
Item 4 Scan Lines per Character
·16
Field
2
Item 12 Scan Lines per Frame
512
Item 14 Character Times
Video
5
122
12;j
perRow
Blankmg
6
Item 11 Scan Lines per Vertical
(Item 4)
Blanking
+2
If the cursor enable output, Item 22, is active on only one
line of a character row, then Item 21 value must be either
"1" or "0" or equivalent to the line selected for the
cursor enable output.
fOOT
fCHAR

-

5-13

"'tI
00
c,.)

Type
At-Cut
Frequency
7.02MHz 17.6256 MHz
10.92MHz
Tolerance
0.005% at 25°C
Stability
0.01 % from O°C to +70°C
Resonance
Fundamental, Parallel
Maximum Series
Resistance
50Q
Load
CapaCitance
20pF

I

C

en
o

en
CD

...iii"

en

DP8350 Series Custom Order Format Table
This table is provided as a worksheet to aid in determining the programmed configuration for custom mask options. Refer
to Table 5 for a list of programming limitations.
Item
No.

1
2

Parameter
Character Font Size
(Reference Onlyj

Value

Dots per Character (Width)
Scan Lines per Character (Height)
Dots per 'Character (Width)

3
Character Field Block Size

4

Scan Line per Character (Height)
~

5

Number of Video Characters per Row

6

Number of Video Character Rows per Frame

7

Number of Video Scan Lines (Item 4 x Item 6)

8

Frame Refresh Rate (Hz) (two pin selectable frequencies allowed) (Item 13 + Item 12)

9

Delay after Vertical Blank start to start of Vertical Sync (Number of Scan Lines)

10

Vertical Sync Width (Number of Scan Lines)

11

Interval between Vertical Blank start and start of Video
(Number of Scan Lines of Video Blanking)

12

Total Scan Lines per Frame (Item 7 + Item 11)

13

Horizontal Scan Frequency (Line Rate) (kHz) (Item 8 x Item 12)

14

Number of Character Times per Scan Line

15

Character Clock Rate (MHz) (Item 13 x Item 14)

16

Character Time (ns) (1 + Item 15)

17

Delay after Horizontal Blank start to Horizontal Sync start (Character Times)

18

Horizontal Sync Width (Character Times)

19

Dot Frequency (MHz) (Item 3 x Item 15)

11=

fO=

-

20

Dot Time (ns) (1 + Item 19)

21

Vertical Blanking Output Stop before start of Video (Number of Scan Lines)
(Range Item 4 -1 line to 0 lines)

22

Cursor Enable on all Scan Lines of a Row? (Yes or No) If not, which Line?

=

23,

Does the Horizontal Sync Pulse have Serrations during Vertical Sync? (Yes or No)

24

Width of Line Buffer Clock logic "0" state within a Character Time
(Number of Dot Time increments) (Typically Yo Item 3 rounded up)

25

Serration Pulse Width, If used (Character Times) (See Figure 13)

26

Horizontal Sync Pulse Active state logic

27

Vertical Sync Pulse Active state logic level (1 or 0)

28

Vertical Blanking Pulse Active state logic level (1 or 0)

le~el

(1 or 0)

Video Monitor: Manufacturer and Model No. (For Engineering Reference)

5·14

,

Absolute Maximum Ratings

Operating Conditions

(Note 1)

Supply Voltage, Vee
7.0V
Input Voltage
5.5V
Output Voltage
5.5V
Storage Temperature R!!nge
-65'C to +150'C
Lead Temperature (soldering, 10 seconds)
300'C

Electrical Characteristics

Conditions

VIH

Logic' "1" Input Voltage
All Inputs Except X1, X2 RESET
RESET

VIL

Logic "0" Input Voltage
All Inputs Except X1, X2

VHYS

RESET Input Hysteresis

Vclamp

Input Clamp Voltage
All Inputs Except X1, X2

All Other Inputs Except X1, X2

VOL

• Logic "0" Output Voltage

los

Min.

Typ.

Max.

2.0
2.6

V

.V
V

V
V

-1.2

Enable Input = OV,
Vee = 5.25V, VIN = 5.25V

10

100

!lA

Vee = 5.25V, VIN = 5.25V

2.0

20

IlA

Enable Input = OV,
Vee = 5.25V, VIN = 0.5V

-20

-100

IlA

Vee = 5:25V, VIN = 0.5V

-20

-100

IlA
V

10H =-1OOIlA

3.2

IOH=-1 rnA

2.5

IOL=5mA

Output Short Circuit Current

Units

-0.8

IIN=-12mA

Logic "0" Input Current
Ao-A11

Logic "1" Output Voltage

'c

0.8

Logic "1" Input Current
Ao-A11

VOH

Units

5.25
+70

0.4

All Other Inputs Except X1, X2
IlL

Max.

4.75
0

Vee = 5V ± 5%, TA = O'C to +70'C (Notes 2, 3, and 5)

Parameter

IIH

Vee, Supply Voltage
TA, Ambient Temperature

(Note 6)
Min.

10

Vee = 5V, Your = OV (Note 4)

4.1

V

-

V

3.3
0.35

0.5

V

40

100

rnA

rnA
220
300
Power Supply Current (Note 10).
Vee = 5.25V
Ice
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of thedevice cannot be guaranteed. They are not
meant to imply that the device should be operated at these limits. The table of "Electrical Characteristics" provides conditions for
actual device operation.
Note 2: Unless otherwise specified, min./max. limits apply across the O'C to +70'C t.emperaiure range and the 4.7SV to 5.2SV power
supply range. All typical values are for TA = 25'C and Vee = S.OV and are intended for reference only.
Note 3: All currents into device pins are shown as positive; all currents out of device pins are shown as negative; all voltages are refer·
enced to ground, unless otherwise specified. All values shown as max. or min. are so classified on absolute value basis.
Note 4: Only one output at a time should be shorted.
Note 5: Electrical specifications do not apply to pin 17, external charlline clock, as this pin is used for production testing only.
Note 6: Functional operation of device is not guaranteed when operated beyond specified operating condition limits.

Switching Characteristics

Vee = 5.0V ±5%, TA =25'C (Note 7)

Parameter
Symmetry Dot Rate Clock Output High
Symmetry With Crystal Control

Load
Circuit

Notes

1

Min.

Typ.

Max.

Units

50%-4

50%-2

50%+1

ns

tpd1

XI Input to Dot Rate Clock
Output Positive Edge

1

17

22

ns

tpdO

XI Input to Dot Rate Clock
Output Negative Edge

1

21

26

ns

t01

Dot Clock to Load Video Shift
Register Negative Edge

1

6.0

10

ns

t02

Dot Clock to Load Video Shift
Register Positive Edge

1

11

15

ns

t03

Dot Clock to Latch Character
Generator Positive Edge

1

8.0

13

ns

t04

Dot Clock to Latch Character .
Generator Negative Edge

1

6.0

10

ns

5-15

=

·c
~

~.

co

DC

Switching Characteristics

(Cont'd.) Ve e ·=5.0V±5%, TA=25·C (Note 7)
Load
Circuit

Parameter

Notes

Min.

Latch Character Generator Positive
Edge to Load Video Shift Register
Positive Edge
1
0
Dot Clock to Line Buffer Clock
tos
1
Negative Edge
N(OT)
Line Buffer Clock Pulse Width
1
8,9
tPWl
Dot Clock to Cursor Enable Output
tOB
Transition
1
Dot Clock to Valid Address Output
1
t07
Latch Character Generator to Line
tOBo
Rate Clock Neg. Transition
1
8,10
Lertch Character Generator to
tOBl
Line Rate Clock Pos. Transition
1
8,10
Latch Character Generator to
t090
Clear Line Counter Neg. Transition
1
8,10
Latch Character Generator to
tOOl
Clear Line Counter Pos. Transition
1
8,10
t08 1- t 091 Clear Line Counter Pos. Transition
to Line Rate Clock Pos. Transition
1
10
Line Rate Clock to Line Counter
tOl0
Output Transition
1
Line Rate Clock to Line Buffer
tOll
Recirculate Enable Transition
1
Line Rate Clock to Vertical
t012
Blanking Transition
1
Line Rate Clock to Vertical Sync
t013
Transition .
1
Latch Character Generator to
t014
Horizontal Sync Transition
1
Register Select Set-up Before
tSl
Register Load Negative Edge
0
Register Select Hold After Register
tHl
0
Load Positive Edge
Valid Address -Input Set-Up Before
tS2
250
Register Load Positive Edge
Valid Address Hold Time After.
tH2
Register Load Positive Edge
0
Register I,.oad Required Pulse Width
150
tpw2
Delay from Enable Input to Address
tLZ, tHZ
Output High Impedance State from
Logic "0" and Logic "1"
2
. tZL, tZH
Delay from Enable Input to Logic
"0" and Logic "1" from Address
Output High Impedance State
2
Note 7: Typical values are for Vee = 5.0V and TA = 25·C and are meant for reference only.
Note 8: "DT" denotes dot rate clock period time, item 20 from option format table.
Note 9: "N" denotes value of Item 24 from option format table.
Note 10: Revised since last Issue.

Typ.

Max.

Units

t02- t 03

Switching Load Circuits

3.0
23
N(OT)+8

35
N(OT)+12

ns
ns

24
15

36
25

ns
ns

425+0T

500+0T

ns

300+0T

400+0T

ns

525+0T

700+ OT

ns

290+0T

400+ OT

ns

10

60

ns

60

120

ns

195

300

ns

160

300,

ns

220

300

ns

96

150

ns
ns
ns
ns

15

30

ns

17

30

ns

.::'~

1K

TO OUTPut

.....
.....

,.
.. ,.

~~t

IK

....

UNDER TEST

H

I.

1<"''1

~F
'='

ns
ns

65

.::'c~

TO OUTPUT
UNDER TEST

ns

.".

.".

1"
.".

Load Circuit 2
Load Circuit 1
Note: CL Includes probe and jig capacitance. All diodes are 1N914 or equivalent.
5-16

c

Switching Waveforms

.. IOns
]
[ lr=ll
X2 (PIN 21) = OPEN

SYMMETRY =

~

X 100%

V~~~!!&
VCC
2 2 .
OV

DDT RATE CLOCK
DDT RATE CLOCK

Figure 7. Dot Rate Clock Output Waveform Symmetry
with Crystal Control

I~II~I
~

Figure 8. X1 Input to Dot Rate Clock Output
Propagation Delay

_CHARACTER~'I-I_ _ _ _ _ _ _ _ _ _ _ _ _ CHARACTER _ _ _ _ _ _ _ _ _-1

OOTA::: :::::
LOAD VIDEO
SHIFT REGISTER

x-

i

~AX

nI

MAX

2

o'9 1:::~I02
_ _------{~---,
~
l J1I

03

LATCH CHARACTER

GENERATOR ADD.

LINE aUFFER CLOC_

MAX -,

CHARACTER_
X+'

, I

I

•

I

J

104

2

I

I,w'

I i'
-10':1-

I

'I
-~~---J·r-----+-I----''--

---( 1-------'l(-..:..----,.-------1.2t-l
------+-,
tD6

ENABLE~~~~~~

IJl __ l _________________ ~~---------J-\..-----1 -------------~~---------J-------I
II
1-10'01\

ADDRESS
COUNTER

ourpurs _____ _________

,----------.,(/~l-------_;-----

I

I

Note 1: All measurement points are 1_5V

.Figure 9. Dot/Character Rate Timing
- - - - - - - - - - - - - LINE

x----------------t--- LlNEX+1 _ _ _ _ _

r-

I

I .

\

\

\

\ \.I012j

IOl1

RECIRCUL~~: :~m: ______ 1_________________ L______ ~~ _____ 1_ J__

j

I -----

~Lw~~~~ ______ l __________ ~ ______ L______ ~~-----l-J--I----I
\
u
I [.I01Jj ____ _

1_________________ L______ ?2 _____ 1____ I ____
I
--I
---.,,----,..---'""I'----,..---""'T---..,.----.,
»
I
I
I
I

VERTICAL SYNC _ _ _ _ _ _

--l !-- 1014 (NOTE il

HORIZONTAL SYNC

\

\

'- _ _ _ h

\

!

1-1014 (NOTE 11

~---

\

I

\

I

\

I

\.

!??,

j

_.L_' __ ..J

Note 1: Actual polarity and position of the horizontal sync start and stop points is a function of the particul.ar device format.
Note 2: All measurement points are 1.5V.

Figure 10. Character/Line Rate Timing
5-17

~

C.-)

~

en
CD

:::!.

CD

en

o

.-CD...

Switching Waveforms

(cont'd)

CD

en

3V*

:5

ENABLE
INPUT

(W)

CO
DC

1.5V

F

.

1.5V·

~r"-I.~.~ 1!'~

OV

I

fO. 5V
--

VOL

-IZH

}-O.5V
VOH~~

~IHz-l

-

=1.5V

fO.5V

Note 1: All measurement points are 1.5V.
Note 2: tr = if'; 10 ns.
Note 3: Address enable (pin 37) = OV.

Figure 11. Register Select and Load Waveforms

Figure 12. Address OutPl,lt EnablelDisable
Waveforms

Timing Diagrams

I.

FR~ME

.1.

F~~~E_

1 _V
I D E O _ I - - VERTICAl_
1nnrNG.
.
TIME
I
BLANKING
LINE RATE ~
M r - I r--o; ~ r---1 rf?-. r--I r--1 r--"I , - - , rCLOCK
, ~ U
U U U U -- U U U U u
1

couNgi~~,'I~~

VERTICAL
LA

---tI ·

2~2

L

2r--iJ.......- - - - -

I
I
RECIRCULATE ~-~~-~t----T---+-.-----T'~--r--ENABLE OUTPUT i.._...L-.I
INOTE2) -, L.._...L-.I"
L._..L-...J
" L.._.L.....I
I '
I
I
LINE COUNTER -.-----r--T--r--r-t==
=-'?,---r-,
r-T-??-r---i
,..--,--.....OUTPUTS
I.-..---...L._...L--L.._...I.- '~
L~e-'--~_~2L-L...l..-.L.....J
I

VERTICAL
I
BLANKING OUTPUT - - I
VERTICAL
SYNC OUTPUT

-r-+,

I

I
1-----(NO;E4) I
~-?h---r-T-?h--,--+-.-.-?n--~-'-T'-"""-...L.--L..-~2
'(2
'22
_-'-_...1.-

a

22

I
I
I
(NOTE J) L. -(~ _..L. _

I

I

I

I

I

I
,

,i-

(~

,

I

,

Note 1: One full row before start of video the line counter is .set to zero state - this provides line counter synchronization in cases
where the number of lines in vertical blanking are not even multiples of the number of lines per row.
Note 2: The position of the line buffer recirculate enable logic low level is a function of the logic level of the address mode input (see
Table 3).
Note 3: The stop point of the vertical blanking output active signal is a function of device type or custom option, and will always be
within one row prior to video.
Note 4: The transition start and stop points of the vertical sync output signal are a function of device type or custom option.

Figure 14. Line/Frame Rate Functional Diagram

HoRIZoNTAL
SYNC
OUTPUT

VER~~~~
OUTPUT

I-Tl-IT2/--

--:-SERRATION PULSE ENVELOPE-I

. -I Tl -T2·1

_ _ _ _ _ _ _.;.(N_O_TE_1.;.1...L.1 lN~~}d

1L..:..(N.;.OT;,,;E;,,;2.;.1-_1
.L1_ _ _ _ __

P=HORIZONTAL SCAN TIME PERIOD liTEM 14 FRoM PROGRAM TABlEI
H= HoRIZONTAL SYNC WIOTH (ITEM 18 FROM PRoGRAM TABLEI
S = SERRATION PULSE WIOTH (ITEM 25 FROM PROGRAM TABLE)
I1 = P·H (MAXI
T2 = H·1 CHARACTER TIME IMAXI

Note 1: The vertical sync transition point is always coincident with the beginning of horizontal blanking.
Note 2: T1 and T2 intervals represent the range of alignment offset between the vertical sync pulse and the serration pulse envelope
and is a function of the horizontal sync position with respect to the beginning of horizontal blanking .

. Figure ,15. Serration Pulse Format
5-18

C

Timing Diagrams

."

(cont'd)

OC)

_ - - - - - - - - - - - S C A N LIN'
VIDEO CHARACTER - - - - POSITION,
ALL SCAN
LINES

HgrA~~~J~L----~·.j.I··,----- V I D E O I - - - - - . I . _ - - - - H~rA~~~J~l------

1-6 1-5 1-4 1-3 1-2 1-'

{

LOAOVID'O
SHIfT
REGISTER

U

VERTICAL
VIDEO
INTERVAL

LlNEC~gJ~ ------.J
HORIZO~~~~

-T T-T-T

SHm~G~~m

ElI

T

U

I

T-IT-T

u

\.\, U

o

U..--i--------------

(' _ n .L.-_ _+ ____________
,n
22>--------"-1~

~tT

T

CLOCK
HORIZONTAL _.,..
SYNC
'

T-T

(NOlE1)

T-T

I
I

I ""-------.....-

T-IT-T

.

.l..

fL-1IL.--~----------

I

n

T-IT

I

T

"T{~
~F

-; :

:--iT'

T

T

,

......

......,

I

I

VIDEO
ROWn
ADDRESS OUTPUTS

LINE
MAX·1

RECIRCULATE
ENABLE OUTPUT

VIDEO
ROWn

LINE
MAX

VIDEO
ROW n+1

LINE 1

Note 1: The horizontal sync output start and stop point positions are a function of device type or custom option.
Note 2: The position of the recirculate enable output logic "0" level is dependent on the state of the address mode input. When address
mode = "0", recirculate enable occurs on the max. line of a character row (solid line) and the address counter outputs roll over to the new
row address at point A. When address mode = "1", recirculate enable occurs on the first line of a character row (dashed line) and the
address counter outputs roll over to the new row address at point B.
Note 3: The address counter outputs clock to the address of the last character of a video row plus 1. This address is then held during
the horizontal blanking interval until video minus three character times. At this point the outputs are modified to the contents of the
Row Start Register (RSR).

Figure 13. Character/Line Rate Functional Diagram

5-19

en
CD

:::!.

---::IL-::O:::GI:::c"::H:::n--------...:I;....----T22t.-------!.....-------------

LINE BUFFER
CLOCK _ _ _ _ _ _ _ _ _ _-..1

LINE RATE
INTERVAL

U

II

w
en
o
CD

-----------,L _~, __ ,

CLOCK _ _ _ _ _ _ _ _ _---1
LINE BUFFER

VERTICAL
BLANKING

~rX

12

LATCH CHARACTER
GENERATOR ADDRESS

ALL8CAN
LINES

ALL SCAN
LINES

X - - - - - - - - - - _ I _ - - - - SCAN LIN' X+"----..

Applications

SYSTEM
INTErFACE

VIDED
INTERFACE

~. . . . . .! -. .DA.~.B.US. .~. . . . . . . .~~

TD ATTRIBUTE
DECDDE LDGIC

I

EQUIVALENT TO
OM76S64

ADDRESS BUS

CRT CONTROLLER

HORIZSYNC

,

1-':::':::::':':':'::--', )

L-_ _ _ _ _ _ _--II-...;V;.;;ER;;.;T.;;;SY;;.;N;.;;C--,

,

TO MONITOR

INP~TS

I
17igure 16. General System Block Diagram

SYSTEM
INTERFACE

,

DATA BUS
VIDEO
INTERFACE

I

,
,
,,I
I
,I
I
,I

I

NUMBER OF MEMORY
BLOCKS IS EQUAL TO
NUMBER OF SCAN LINES
PER CHARACTER CELL

I

/

/

/

I

r--

VIDEO
RAM

~·~I

/

/

I

I
I
I
I.
I

____~C~~C_ON_T_RO_L_B~US~_ _ _~

I
ADDRESS BUS

DISPLAY
CONTROL
BUS

l

-.--

SCAN LINE
COUNTER OUTPUTS
CRT CONTROLLER

Figure 17. Dot·By·Dot Graphics Block Diagram

·5·20

CURSOR
HORIZSYNC
VERT SYNC

C

DP8350 CRT Controller

"'C
CO

w

g:
en

Table 6. Characteristic Format
Item
No.

1
2

Parameter

Character Font Size
(Reference Only)

3

...

Value

Dots per Character (Width)

(5)

Scan Lines per Character (Height)

(7)

Dots per Character (Width)

7

Scan Line per Character (Height)

10

(I)

(ii"

en

Character Field Cell Size
4

I
I

5

Number of Video Characters per Row

80

6

Number of Video Character Rows per Frame

24

7

Number of Video Scan Lines (Item 4 x Item 6)

240

8

Frame Refresh Rate (Hz)

9

fl =60

10=50

Delay after Vertical Blank start to start of Vertical Sync (Number of Scan Lines)

4

30

10

Vertical Sync Width (Number of Scan Lines)

10

10

11

Interval between Vertical Blank start and start of Video
(Number of Scan Lines of Video Blanking)

20

72

12

Total Scan Lines per Frame (Item 7 + Item 11)

260

312

13

Horizontal Scan Frequency (Line Rate) (Item 8 x Item 12)

15.6kHz

14

. Number of Character Times per Scan Line

100

15

Character Clock Rate (Item 13 x Item 14)

1.56MHz

16

Character Time (1 ... Item 15)

17

Delay after Horizontal Blank start to Horizontal Sync start (Character Times)

0

18

Horizontal Sync Width (Character Times)

43

19

Dot Frequency (Item 3 x Item 15)

20

Dot Time (1 ... Item 19)

21

Vertical Blanking Output Stop before start of Video (Number of Scan Lines)

22

Cursor Enable on all Scan Lines of a Row? (Yes or No)

Yes

23

Does the Horizontal Sync Pulse have Serrations during Vertical Sync? (Yes or No)

No

24

Width of Line Buffer Clock logic "0" state within a Character Time
(Number of Dot Time increments)

4

25

Serration Pulse Width, if used (Character Times)

-

Horizontal Sync Pulse Active state logic level (lor 0)

1

27

Vertical Sync Pulse Active state logic level (lor 0)

0

28

Vertical Blanking Pulse Active state logic level (lor 0)

1

.26

641 ns

10.92MHz
91.6ns

Video Monitor Format: Ball Brothers TV-12, TV-120 or Equivalent.

5·21

1

en

CD

·c

enCD

~
CO

Q.

C

VIDEO
CHARACTER
FORMAT

_ ____________t:::::::::::::::::::~7~D~D~n~::::::::::::::::::~~-----------X-I

X

X+l

-------------+----------------------------~--------------~~------------

DDT
CLOCK
LOAD VIDEO
SHIFT
REGISTER

----i

LATCH
CHARACTER

-1

GE~EDRDA;E~~ _ _ _ _ _ _ _

r------4DDTS------1

-------+--..,

LINE
BUFFER
CLDCK _ _ _ _

1-----------.. . ----

CURSOR
ENABLE _ _ _ _ _ _ _..1

--------------'---+---

X

X

ADDRESS
OUTPUTS ________X_+_'________J~______________________
X+_2____________________~r~__X_+_3___
NOTE: DASHED LINES IN WAVEFORMS DENOTE INACTIVE STATE LOGIC LEVELS.

Figure 18. DP8350 Video Character Signals

r------------1DD

CHARACTERS----------~_1

-20CHAR
HORIZONTAL
FORMAT ~~~~~+-

BLANKING

__________.....~~~~~~~~~~~~~~~~~~~~~~-----

1 - - - - - - 4 3 CHAR-----·-I
HORIZONTAL
. SYNC _ _ _ _.....
-15CHARLINE RATE
CLOCK

CLEAR - - - - - ; - LINE
COUNTER

-

-i--------~-------__:-----+_---

L1NE--------~,r_------------------------------------------------------\~------

COUNTER
OUTPUTS ________

~,~

BUFL~~~ - - - - - - .

______________________________________________________

~~------

--------------------1

RECIRCULATE
ENABLE
NOTE: DASHED LINES IN WAVEFORMS DENOTE INACTIVE STATE LOGIC LEVE.LS.

Figure 19. DP8350 Scan Line Signals

5-22

C

"tJ

CD
1 - - - - - - - - - - - - - 2 6 0 SCAN

gJ

LINES-----------~I

- 2 0 LINES-I----------240 LlNES---------J
VERTICAL

BLANKING

FORMAT . .~~~~+_--------------~~~~~~~~~~~~~~~~~~~~~------

en

CD
::::!.
CD

en

VERTICAL
BLANK ________~

- 4 LINES

.

VERTICAL
SYNC

1
-

10 LINES

L

If--

Figure 20. DP8350 60 Hz Refresh Rate Frame Signals

1 - - - - - - - - - - - - - 3 1 2 SCAN L l N E S - - - - - - ' - - - - - - - - - J
- 1 2 LlNESVERTICAL

240 LINES

BLANKING

FORMAT~~. .~~~--------------~~~~~~~~~~~~~~~~~~~~~----­
- ( -IUNE

1-------;

VERTICAL
BLANK _ _ _ _ _-I

L

VERTICAL
SYNC

Figure 21. DP8350 50Hz Refresh Rate Frame Signals

5·23

o
CI)

DP8352 CRT Controller

·C

CI)

tn

o
II)

('I)

CO

0-

C

Table 7. Characteristic Format
Item
No.
1
2

Parameter
Character Font Size
(Reference Only)

3

Value

Dots per Character (Width)-

(7)

Scan Lines per Character (Height)

(9)

Dots per Character (Width)

9

Scan Line per Character (Height)

12

Character Field Cell Size
4
5

Number of Video Characters per Row

32

6

Number of Video Character"Rows per Frame

16

7

Number of Video Scan Lines (Item 4 x Item 6)

192

8

Frame Refresh Rate (Hz)

9

f1 =60

10=50

Delay after Vertical Blank start to start of Vertical Sync (Number of Scan Lines)

27

53

10

Vertical Sync Width (Number of Scan Lines)

3

3

11

Interval between Vertical Blank start and start of Video
(Number of Scan Lines of Video Blanking)

68

120

12

Total Scan Lines per Frame (Item 7+ltem 11)

260

312

13

Horizontal Scan Frequency (I-ine Rate) (Item 8 x Item 12)

14

Number of Character Times per Scan Line

15

Character Clock Rate (Item 13 x Item 14)

16

Character Time (1 .,.Item 15)

17

Delay after Horizontal Blank start to Horizontal Sync start (Character Times)

6

18

Horizontal Sync Width (Character Times)

4

19

Dot Frequency (Item 3 x Item 15)

7.02MHz

20

Dot Time (1 .,.Item 19)

142.4ns

21

Vertical Blanking Output Stop before start of Video (Number of Scan Li.nes)

22

Cursor Enable on all Scan Lines of a Row? (Yes or No)

Yes

23

Does the Horizontal Sync Pulse have Serrations during Vertical Sync? (yes or No)

Yes

24

Width of Line Buffer Clock logic "0" state within a Character Time
(Number of Dot Time increments)

5

25

Serration Pulse Width, if-used (Character Times)

4

26

Horizontal Sync Pulse Active state logic level (1 or 0)

0

27

Vertical Sync Pulse Active state logic level (1 or 0)

0

28

Vertical Blanking Pulse Active state logic level (1 or 0)

1

15.6kHz
50
0.78MHz
1282ns

.

Video Monitor Format: RS-170·Compatible (Standard American TV).

5·24

0

_
VIDEO
CHARACTER

________-4::::::::::::::::::::::::::::::::9~D~DT~S~::::::::::::::::::::::::::::~--------~----

X-I
X+I
FDRMAT __________~------------------------------------------------------------t_-----------DDT
CLOCK

LOAD VIDEO
SHIFT
REGISTER
LATCH
CHARACTER

GE~~RDARTE~~

________--I
~------5DOTS-------1

-----+----j

LINE
BUFFER
CLOCK _ _ _

~-----------....I-------

CURSOR
ENABLE _ _ _ _ _--'

AODRESS

OUTPU~'

____________________ L...-_+_ _

_________
X+_I_______J~

_______________________________

X_+2______________________________~~__X_+J___

NOTE: DASHED LINES IN WAVEFORMS DENOTE INACTIVE STATE LOGIC LEVELS,

Figure 22. DP8352 Video Character Signals

HORIZONTAL

FORMAT~~~~~~------------------~~~~~~~~~~~~~~~~~~~~~~~~~~-----HORIZONTAL
SYNC

LINE RATE

CLOCK

CLEAR
LINE
COUNTER
LINE
COUNTER

-----1- -

-

- -

1-------------------------+---

--------~~----------------------------------------------------------------~~---

OUTPUTS _________J~--------------------------------------------------------------------~L------

BUFL:~~

----------i - - - - - - - - - - - - - - - - - - - - - - - - - -

RECIRCULATE
ENABLE
NOTE: OASHEO LINES IN WAVEFORMS DENOTE INACTIVE STATE LOGIC LEVELS,

Figure 23. DP8352 Scan Line Signals

5·25

1--------------260lINES------------- 6 8 LINESVERTICAL

BLANKING

FDRMAT~~~~~~----------~~~~~~~~~~~~~~~~~~~~~-------

VERTICAL
BLANK

-----I

27 LINES I~

U~--------------~L

VERTICAL
SYNC

-I

J--,3 LINES

Figure 24. DP8352 60Hz Refresh Rate Frame Signals

1--------------312l1NES-------------J
120 l I N E S - I - - - - - - - - - - 1 9 2 l I N E S - - - - - - - - - i
VERTICAL

BLANKING

FDRMAT~~~~~~--------------~~~~~~~~~~~~~~~~~~~~£--------

VERTICAL
BLANK ________-!
VERTICAL
SYNC

53 LINES

~

L

1-1-H""
Figure 25. DP8352 50 Hz Refresh Rate Frame Signals

VERTICAL

------------------j

------3l1NES--------

1--------------------------

SYNC

Figure 26. DP8352 Serration Pulse Format

5-26

DP8353 CRT Controller
Table 8. Characteristic Format
Item
No.
1
2

Parameter
Character Font Size
(Reference Only)

3

Value

Dots per Character (Width)

(7)

Scan Lines per Character (Height)

(9)

Dots per Character (Width)

9

Scan Line per Character (Height)

12

Character Field Cell Size
4
5

Number of Video Characters per Row

80

6

Number of Video Character Rows per Frame

25

7

Number of Video Scan Lines (Item 4 x Item 6)

. 300

8

Frame Refresh Rate (Hz)

9

f1 =60

fO=50

Delay after Vertical Blank start to start of Vertical Sync (Number of Scan Lines)

0

32

10

Vertical Sync Width (Number of Scan Lines)

3

3

11

Interval between Vertical Blank start and start of Video
(Number of Scan Lines of Video Blanking)

20

84

12

Total Scan Lines per Frame (Item 7 + Item 11)

320

384

13

Horizontal Scan Frequency (Line Rate) (Item 8 x Item 12)

14

Number of Character Times per Scan Line

15

Character Clock Rate (Item 13 x Item 14)

16

Character Time (1 .;- Item 15)

17

Delay after Horizontal Blank start to Horizontal Sync start (Character Times)

5

18

Horizont~1

9

19

Dot Frequency (Item 3 x Item 15)

20

Dot Time (1 .;- Item 19)

21

Vertical Blanking Output Stop before start of Video (Number of Scim Lines)

22

Cursor Enable on all Scan Lines of a Row? (Yes or No) .

Yes

23

Does the Horizontal Sync Pulse have Serrations during Vertical Sync? (Yes or No)

No

24

Width of Line Buffer Clock logic "0" state within a Character Time
(Number of Dot Time increments)

5

25

Serration Pulse Width, if used (Character Times)

-

26

Horizontal Sync Pulse Active state logic level (1 or 0)

1

27

Vertical Sync Pulse Active state logic level (1 or 0)

1

28

Vertical Blanking pulse Active state logic level (1 or 0)

1

19.20kHz
102
1.9584MHz
510.6ns

Sync Width (Character Times)

17.6256MHz
56.7ns

Video Monitor Format: Motorola M3003 or Equivalent.

5·27

1

U)

.-CD
enCD
~

0

II)
CW)
eX)

a..
C

9 DOTS
VIDEO
CHARACTER
FORMAT

X+I

X-I

DOT
CLOCK

LOAD VIDEO
SHIFT
REGISTER
LATCH
CHARACTER
GENERATOR
ADDRESS

r-------------500TS------------~

LINE ------~--~
BUfFER
CLOCK _

~------------+---~

\------------'------------

CURSOR
ENABLE

-+-___

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ L..-__

ADDRESS
X+2
X+3 __
OUTPUTS _______X_+_'______ j \________________________________________________________
J~____
NOTE: DASHED LINES IN WAVEFORMS DENOTE INACTIVE STATE LOGIC LEVELS,

Figure 27. DP8353 Video Character Signals

HORIZONTAL
FORMAT~~~~~~__________________~~~~~~~~~~~~~~~~~~~~~~~~------

HORIZONTAL
SYNC

-------4--.. . .

LINE RATE - - - - - - . . . . ,
CLOCK

CLEAR
LINE
COUNTER

----oj - - -- - - r-----...,...-------------------1----

L1NE-------~~----------------------------------------------------------~----COUNTER

OUTPUTS ________-J~----------------------------------------------------------------~------

BUFL~~~

--------I - - - -- - - - - - - - - - - - - - - -- - - - - - - -

RECIRCULATE
ENABLE
NOTE: DASHED LINES IN WAVEFORMS DENOTE INACTIVE STATE LOGIC L~VELS,

Figure'28. DP8353 Scan Line Signals
f-------------------------320 L l N E S - - - - - - - - - - - - - - - - - - 1
- 2 0 LlNES----1-----------300 L l N E S - - - - - - - - - - -

VERTICAL

BLANKING
FORMAT~~~~~---------~~~~~~~~~~~~~~~~~~~~~---

-I
VERTICAL

BLANK _ _ _ _-I

n

1--3 LINES

VERTICAL
SYNC _____

~

~

_________________________

Figure 29. DP8353 60 Hz Refresh Rate Frame Signals

5·28

n

~I

~

f-------------384 LINES------------l
84 L I N E S - - - \ - - - - - - - - -

VERTICAL

BLANKING

FORMAT~~~~~~------------~~~~~~~~~~~~~~~~~~~~~------

VERTICAL
BLANK

---""""""I

Figure 30. DP8353 50 Hz Refresh Rate Frame Signals

5-29

~
,..
z•

-«

A Low Component Count
Video Data Terminal Using
the DP8350 CRT Controller
and the INSS080 CPU

National Semiconductor
Application Note 1.99
AI Brilliott
August 1978

INTRODUCTION

the CPU and the CRTC eliminates the need for line
buffers.

The DP8350 is an 12L - LS technology integrated
circuit, designed to provide all control signals for a
cathode ray tube (CRT) display system. This application
note explains a system using the DP8350 and the
INS8080 microprocessor. The design philosophy shows
how the DP8350 interfaces to the INS8080, completing
the function of a video data terminal with a minimum
component count. After reading and understanding this
application note the reader will realize the ease and
flexibility of designing video terminals with the DP8350*.
To thoroughly understand this application note the
reader must be familiar with the DP8350 and the
INS8080 microprocessor.

THE CHARACTER GENERATOR
The character generator consists of 3 elements: an
address latch to hold the input address to the character
ROM allowing for the access time of the ROM; the
character ROM that stores the ASCII character in a form
for parallel to serial conversion by the shift register;
the shift register converts the character ROMs parallel
output to serial form. The serial output from the shift
register is the true video output, modulating the video
monitors electron beam which writes characters on the
screen. All of the 3 elements of the character generator
are combined in the DM8678, (Figure 3). The DP8350
CRTC provides all the control signals for the DM8678.

The video data terminal described is divided into the
,following sections, (Figure 1).

THE COMMUNICATION ELEMENT

The DP8350 CRT controller (CRTC).

The INS8250 is the asynchronous communication
element (ACE) for the data terminal. The ACE allows
the CPU portion of the data terminal communication
with peripherals or host computers at the correct baud
rate, (Figure 1). The ACE is programmed by the CPU to
send and receive serial data at the standard baud rates
from 110 to 4800 baud. The ACE, in conjunction with
the DS1488 and DS1489 line drivers and receivers, also
provides full RS232G synchronous communication if
higher baud rates are desired. System communication
speed must always be considered to insure the baud rate
does not exceed the time required for the CPU to
process a data byte. Asynchronous communication
at baud rates higher than 4800 are possible by adding
a line buffer.

The 8080 pP system which includes ROM, RAM,
interrupt instruction port, oscillator, and control
support chips.
The character generator.
The communication element.
The keyboard and baud rate select ports.
THE CRTC
The DP8350 generates all the required control and
timing signals for displaying video. information on the
video monitor. Here is a summary of the controller's
functions:

SYSTEM INITIALIZATION

Dot clock, control, and counter outputs for the
character generator.

Application of the terminal's power supply resets the
microprocessor, the communication element, and the
CRT controller. Resetting the ACE is necessary to clear
the interrupt. Resetting the GRTG is not absolutely
necessary since the microprocessor loads the cursor and
top of page registers in the initialization routine.

Bidirectional RAM address refresh counter' for
refreshing the video RAM and allowing microproces·
sor loading to the internal DP8350 registers.
Direct drive horizontal and vertical sync signal
outputs.

Following the reset all interrupts are disabled to avoid
unwanted interrupts from the CRTC, ACE, or I/O ports.
Refer to the initialization routine in the flowchart.

Direct cursor address location output. The cursor is
internally delayed or pipelined, allowing for the
access time of video RAM and the character generator
ROM, (Figure 1).

The stack pointer is loaded to the bottom of scratch pad
RAM (3FFFH) for use as the register save poin'ter,
(Figure 4).

THE CPU

The entire RAM is written with ASCII spaces generating
a cleared screen. After completion of the screen clear
loop the CPU writes OOOH to the cursor and the top of
page registers in the DP8350 CRTC. The routine homes
the cursor to the upper left corner of the screen. The
top of page register was loaded with OOOH, therefore,
the video RAM is refreshed by the CRTC from that
starting address to the last address on the screen of video
RAM (1920 characters).

The microprocessor provides CRTC, operator, and ex·
ternal machine control for the system. When the CRT
controller is not actively refreShing the video RAM,
(i.e., during vertical retrace or blank scan lines), the
microprocessor is enabled for system housekeeping,
(Figure 2). This method of multiplexing the RAM with
*The DP8350 is equivalent to the I NS8276

5-30

HORIZONTAL SYNC

~

DOT

!

VERTICAL SYNC

EN

HOR

elK

(GRTCl

SYNC

VERT

SYNC

LINE

IAD-A'.
.l
Al2

HOLD
ACI(

HOLD

In
02 TTl
AD-A"~I

CPU

INSB080

OP8224
OP8228

MfMRI

~

g~ r----+-T---1

MEMW

aBU-a,,1

~:I'r

U

1

I

AI]'
X

AaaR,JJ

CONTROL BUS

CURSOR*

1/4DM74LSJ2

8MM5257
AD-A11 1/6DM14LSD4

AD-All,
A14

DBO-OB7 MEMW

LR DOTc..>
OBll, OBI MEMW

ATif

tlK ClK

i3

it I ~

III

~

~

c:r
::;.

X

} EXT.
lOGIC
VID

TO VIDEO
MONITOR

m 170W

11111

111

.-:<;;:;,--,.::-0 nnT U c::

~IDEO

1/2DM14LSB6
DM14lSJ2
3/40M14lS0S
1/2 OM14LS74
1/IiDMl4lS04

1

1

fff-:

....

B

~

-11

X=

(,21lt

~B~~'

r II

INTA

!~~ ~~~~i~~!
'"~

_____+ ___-l

DP835D,
1/60M14lSQ4

RAM

EPROM
1 MM2108

1/4DM74lS32
MEMR
OBo-OB7

~ LCfl-Lel

CNT

CRT CONTROLLER

J

••

-11

oct
~

1-+-lf---+l~I~ ASYNCHRONO~~~~MMUNICATION
x

CHARACTER GENERATOR
OM8678

ELEMENT INS82Sa, 1/6 OM74LS04

VIDEol-!-----'

DATA AND CONTROL

DBD-DB7

i70R

I

AIS 818

KEYBOARD BUFfER
OM81lS95
1{6DM74lS04
1I20Ml4lS74

....!J..

TO ASel!
KEYBOARD

~
RS·2l2INTERFACE
051488
OS1489

080-0B3

1ToR-A'f(

BAUD RATE SElECT
BUFFER
oM74l65
DIP SWITCH

+

l

f

KB ACE DBD-DB7 INJA VERT HOR
INT INT
INT INT
INTERRUPT PORT
DPB212
OM141411

...u.

TO EXTERNAL SYSTEMS

COMMUNICATION LINK

*The cursor is internally pipelined bV the CRTC to allow for access time of the RAM and,the character generator.

FIGURE 1. Video Data Terminal Detailed Block Diagram

T.

1

1

LINE
DECODE

VB

RESET

HoR AND VERT
INTERRUPT LATCHES
1I2DM1414
1/2DM74lS74

Abbreviations:
lA ClK
Line rate clock
ClC
Clear line counter
lVSR
Load video shift register
Latch character generator address
LCGA
Line counter
Line CNT
EN
Enable
Video
VID
KBINT
Keyboard interrupt
VB
Vertical blanking

66~·N"

I.....
zc(•

(SCAN LINE

:

CHAR NO.1
(ODDH)

..

:

~R:TJ:=A=CE============C~H.~M_R_~HW~_B_D__
•
CRTC ON
CPU Hi·Z

ROW X

Hi'~

=

==============-7-} CRTC
CPU ON

NEXT
ROW

.

A NEW ROW START INTERRUPT
OCCURS WHEN THE LINE COUNTER
OUTPUTS INCREMENT TO LINE S.
THE DPSl50 ROW START REGISTER
IS THEN LOADED WITH THE NEXT
STARTING ROW ADDRESS DETER·
MINED FROM THE NEW ROW START
LOOK UP TABLE IN RAM.

4

FIGURE 2. Row Start Interrupting and Multiplexing the I NS8080 with the DP8350

ADDRESS
STROBE
OB5
DB4
CHARACTER' 64
AOORESS
OECOOER
1/64

OBl
DB2

64 X 63
ROM

OBI
DBD

CLOCK
CONTROL
5V

LINE
CLOCK

CLEAR

-------r--.r---,
EDSE·TRIGGER
GENERATOR

-...,..--------..1

SERIAL VIOEO
OUTPUT

OUTPUT
ENABLE

FIGURE 3. DM8678 Character Generator Block Diagram

5-32

faster and easier from a hardware/software standpoint.
Exchanging one row with another row is fast since
it is not necessary to rewrite the video RAM. Row
swapping is useful for higher end terminals requiring
row editing functions.

The CPU is ready to perform the communication element
(ACE) load routine. First, the baud rate divisor for the
ACE must be determined. The baud rate select switch
is read providing a code which corresponds to the ap'
propriate 16-bit divisor for the ACE. This divisor
determines the baud rate at which the ACE will communicate. Any additional programming requirements
needed for the ACE to communicate with host computer
systems could also be done at this time. The software in
this system does not contain any additional programming
for the ACE. There are many programming modes
related to the ACE. Details of these modes are beyond
the scope of this application note.

ADDRESS MAP

JtIA
~

~

$

",O!i

~

0
1
2
3
4
5
6
7
B
9
10

The row start look-up table, (Figure 5J, is loaded up by a
simple algorithm that loads and adds the data for
referencing a row number to that row's starting address.
The reference table, (Figure 6J, is initialized next by
direct loading. This table provides the CPU with top of
page,.bottom of page, next row load, cursor row, and
scratch row numbers for system housekeeping.

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
2B
29
30
31
,32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47

Finally, the new row start and vertical interrupt latches
are cleared, (Figure 7J. The register pointers are loaded
and the CPU is forced in a wait loop with interrupts
enabled.
NON-SEQUENTIAL ADDRESSING
The data terminal described here was designed for
non-sequential starting row addressing. In many sy.stems
sequential row addressing is used. If a character row
consists of 10 scan lines the RAM is addressed 10
repetitive times from OOOH through 04FH, (Figure 2J.
The next row ·is refreshed in the same manner from
050H to 09FH. The starting row address is sequential
OOOH, 050H, OAOH-EBOH for row numbers OH, 1 H,
2H,-2FH, respectively. Non-sequential row addressing
would be equivalent to 050H, OOOH, OAOH-EBOH for
row numbers' 1 H, OH,-2FH, respectively, (Figure 4J.
In conjunction with the CPU, non-sequential row
addressing is quite easily accomplished with the DP8350
since this is one of the features designed into the part.
Accomplishing this task basically requires the following
sequence of events. Assume the CRTC has finished
writing a video row in the middle of the monitor's
screen. This system has a 5 x 7 character font in a 7 x 10
field, (Figure 2J. At the completion of the last video
scan line 7 the CRTC line counters continue to count
the last 3 lines. Video is not present since the character
is only 7 scan lines high. The blank scan lines are 7, 8,
and 9 permitting the CRTC address outputs to be
TRI-STATED®, allowing the CPU to run. When the line
counter outputs increment to scan line 8 an interrupt
signals the CPU. The interrupt occurring is the new row
start interrupt. The interrupt routine fetches the next
CRTC row number from the reference table (Figure 6J.
This number is converted to the new starting row
address, explained later, and loaded to the CRTC row
start register. The CPU finishes the routine by clearing
the interrupt, readying itself for the next new row start
interrupt. The entire routine takes 1 scan line of time,
approximately 64 p.s. The CRTC continues to scan
the video RAM from that ,new starting address on
for the next 7 repetitive scan lines of the next row.
Many advantages become apparent using the nonsequential addressing scheme. Scrolling up or down
with the cursor always on the screen may be done

",'Ii

~

$

",O!i

~

o 0
o 1
o 2
o 3
o 4
o 5
o 6
o 7
o B
o 9
o A
o B
o C
o 0
o E
o F
1 0
11
1 2
1 3
1 4
1 5
1 6
1 7
I B
1 9
1 A
1 B
1 C
1 0
I E
I F
2 0
2 1
2 2
2 3
2 4
2 5
,2 6
2 7
2 B
2 9
2 A
2 B
2 C
2 D
2 E
2 F

l:/~

~~
~~

",'" "' ..

~'4~;

o 0 0
o 5 0
DAD
o F 0
1 4 0
1 9 0
1 E 0
2 3 0
2 B 0
2 0 0
3 2 0
3 7 0
3 C0
4 1 0
4 6 0
4 B 0
5 0 0
5 5 0
5 A 0
5 F 0
6 4 0
'6 9 0
6 E 0
7 3 0
7 8 0
7 0 0
B 2
8 7
B C
9 1
9 6
9 B
AD
A'5
A A
A F
B 4
B 9
B E
C3
CB
CD
o 2
o 7 0
o C0
E 1 0
E 6 0
E B 0

04F'-

VIDEO RAM
3B4o CHARACTERS
Bo RAM ADDRESSES
PER ROW BY 24 ROWS
2 PAGES OF VIDEO

4096
BYTE
RAM

LAST CHARACTER
IN VIDEO RAM
EFF

Foo

NEW ROW START
LOOK UPTABlE

F5F
F 60
REFERENCE
TABLE
BOTTOM OF
REF TABLE
TOP OF
SCRATCH

SCRATCH

FFF

FI~URE

5-33

4. RAM Organization

l>
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CD

i,....
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~

~

DP8350/INS8080 VIDEO DATA TERMINAL BASIC SOFTWARE FLOW CHART (Continued)

T"'"

•

z

ACE Interrupt

 I~

0076 D340
0078 01380

76
77 007A 11603F
78 0070 210030
79 0090 0100QO
80
81
S2
83 0093 Fa
84 0084
85
86
97
88 0087
89 008A
90 OOSC
91 008D
""2 008E
93 009F
94 0092
95

ooce

[000
LXI
• POINT B-C TO ACE
213
,TEST FOR FUNCTION
214
,WAIT lOOP FOR INTEIiUFTS
21!i 0170 7B
FUNC
A.E
MOV
216- 0171 FEOI
• HOME AND CLEAR CNTl A (SOH l
CPI
001
EI
• ENABLE INTERRUPTS
217 0173 CAOOOO
START
,lOOP UNTIL INTERRUPTED
JMP
BAC'CPI
ODD
:!1S 0176 FEOD
• CARRAGE RETURN
'21<) 017S CA6EO.2
JZ
CR
,HOME UP CURSOR
(PI
011
• SAVE ROW 41 CNTl Q 
Z•
...A.

CO
CO

m
,..•
z
«

FEATURES
• Keyboard input port
• Serial liD up to 9600 baud
4kbytes RAM
lk byte ROM
•
•
•

2 video pages
80 x 24 characters
5x 7 character font, 7x 10
field size

•
•
•

Block cursor
Single crystal
Maximum CPU timelframe
without line buffers

•

Line or page scroll capability

•
•

Full cursor control
Complete software flexibility

•
•

Modem control capability
Low component count

A

la

v EPROM

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Note 1: See DP8350 data sheet for sync details.
Note 2: SW open reverses video page.

VERTB!"'---------4>-----+t-------"'''''RT;';':'':lA'''''''
BUf/~~~

F lB rn

12 NC

TO

INTERRUPT

14

'IS

ro

Parts:
1 - DP8350
1 - DP8228
1 - DPB224
1 - INSB080A-2
1 -INSB250
8-MM5257
1 -MM270B
1 -DM81LS95
or DMB1LS96
2 - DM74LS32
(Vee 14,7GND)
1 - DM74LS74
(Vee 14,7 GND)
1 - DM74LSOB
(Vee 14, 7 GND)
1 - DM74LS04
(Vee 14,7 GNDl
1 - DM74LS73
(Vee 14, 11 GND)
1 - DM74365
1 - DM7414B
1 - DM7474
1 - DPB212
1 - DM74LSB6
1 - DMB678e,o,8
2 - Res. arrays,
3.3k
1 - 21.B4 MHz
XIsl

B228 PIN 27

10

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lii 12

Dill
DB2
081

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r--------,
1/4051418

114051418

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5-42

=-c. .. ~-:'e-:'
•• M

I..

=t.:;.-:

• =-:: ... 1-'-:.,.

."": _:1"=

T~

-C

E-;'~-:

.:.c:

-:'

j:-~'

.4i: e.:,_'I":"E

=':'0.: •

; CHANGE 8080 ROW It
; TO 230 AND STORE
• JUMP TO POINTER EXCHANGE ROU

••
131eoo

• PUT THE 1ST ROW TO
,17H
• JUMP TO 8080 ROW It STORE

139600
MUD
CHARNU
CLROWI
CRTeRO
FIRSTR
HMCUR

534
535
536
537
538
539
540
541
542
543
544
045
546
547
548
549

031E 3E2F
R04S
0320 77
0321 C30103

MVI
MOV
"MP

A.02F
M••
LOOP1

0324 3E2F
FR048
0326 77
0327 C30F03

MVI
HOV
"MP

A.O.:!F
M. A
LOOP2

032A :::E:!F
LR048
032C 77
0:320 ('31803

MVI
MOV
"HP

A.02F
M.A
LOOP3

0330 C03603 CLROW.
0333 C36E02

CAL.L
"HP

CLRaWI
CR

551
552
553
554
555
556
557
558
559
560
561
562
'563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
579
57':)
59'0
581
582
583
584
'585
586
587

033-6 lE61
CLRDW1
0338 CD6202
CLROW2
0~3B 3E50
0330 3620
LOOP4
033F 3D
0340 C$
0341 23
0342 C33D03

HVI
CALL
HVI
"VI

I'I.O:W

OCR

A

R'
INX
JHP

H
LOOP4

• PUT ROW DATA IN H-L REO
• INTILIZE LOOP COUNTER.
,STORE ASCI I S.PAC'E IN MEM
• DECREMENT L.OOP COUNTER.
,RETURN IF ZERO BIT IS SET
• NEXT LOCATION
,CLEAR NEXT LOCATION.

0'345 0'301
0347 e Q

OUT
RET

001

,RING BEL.L

XRA
MVI
LDAX
RAL
"C
MVI
STAX
RET

A
E.IMA-:.t.

SS9
590
591
502
593
594
595

0370 1F
RESET I
0371 Eb7F
0373 C36403

RAR
ANI
"MP

07F
BACf.."2

0376 El
0377 C9
0000

POP
RET
END

START

'"0

'.6

93600

INIT
j

BELL.

0348
0349
034B
034C
0340
03'50
03'52
0353

AF
IE6a
lA
17
QA5.:!03
3E80
12
RESET
C9

0354
03'5'5
0357
035A
035C
0350
03'5E
0361
03bZ
0364
0365
03M
0367
036Q
03eC
03bD

E'5
IVERTR PUSH
lE61
MVI
C08202
CAL.L
1 E'50
HVI
7E
LOOP6'
HOV
17
RAL
DA7003
IF
ROR
F6S0
OR)
77
BACk2
HOV
23
INX
713
HOV
. CPI
FEOI
eA7603
10
OCR
C35C03
JHP

"C

"'

DONE

IVERTR
LDHLI
LOOP2
LOOP6
NRS
POW
ROLO
SAVRO
SWAP
UPROW
ZCRTC

CL.EAR ROW ROUTINE

E. ROW8080
L.[JHL
A.050

0
RESET
A.080

0
H
E. ROW80eo
LOHL
E.050
A. M

0007

0000
OOF2
0104
0116
0093
00b3
0336
0064
0062
0087
0038
0354
029"3
0'30F
03'5C
0061
0006
0200
027B
02135
02EE
024A

ACEL.D
BIIO
132000
94800
BACK
BELL
CLRAM
CLROW2

OIlC
0004
OOFe

OIOA
0083
034:;
0042
03313
OOO:!.
0
FR048 0324
HOME
OlA4
INTACE Q14A
0005
L
LF
0280
LOOPS 0318
LR048 03lA
NXRO
01l'~E
RESET 0352
Roweos 0061
SCROLL 0205
TEMPI
C06b ...
UPSCt 0308
ZFRO
021E

ADCUR

ADDCH

a!~OO

0161
OOEe
OOFE
00E6
02FB
02EO
CLRAMI O(l4C
CLROW3 01C4
0376
DONE
FUNC
0170
IMASI( OObB
INTt:8 0136
LASTRO 0060
LOOP
0244
LOOP4 0330
H
OOOb
NXROI Oloe
F\E5ETI 0370
ROW:.AV 0065
SP
0006
TEMP2 0067 ...
024F
VERTI
ZLRO
021 Q

IHSO
13;:00

132400
B600
BACt: 1

.0

enoo
BACtZ

C
C.LROW
CR
E
H
INCRO
IVERTN
LOHL
LOOPl
LOOP5
NEWRO
PCUR
R04S
ROZERO
START
UPCLIR
ICHAR
ZROW

02Q8
OODA
OOEO
0110

0364
0001
0330
026E
0003
0004
OIE'5
0346
0282
0;:01
01CF
022'5
0163
031E
0107
0000
02Fl
01F3
OIFB

NO ERROR LINES
SOURCE CHECKSUM'" 403F
OBJECT CHEer-SUM'" OF51
1 CRlSOA ~RC ON JJMFM
INPUT FILE
09,;ECT FILE
J CRTSOA LN ON .JIMFM

,POINT D. E TO MASK

.0:

BIT 13 STATUS

, INVERT BIT 8
,STORE OUT NEW MASK

,LOAD 1ST ADD OF 808oROW TO
• SET COUNTER
,GET CHAR
• CY. BIT a STATUS AND INVERT

RESET I
OBO

H.A
H
A. E
001
DONE
E
L.OOP6

• MAS.... BIT 8 HIGH
• STORE MOD CHAR TO MEM
• POINT TO NEU MEM
,RETURN IF COUNT = ZERO
COUNTER
• DEC

• RESET BIT e

DEFINITIONS

REFERENCES

ACE - Asynchronous communication element
CRTC - Cathode ray tube controller
Video Page - Visible screen data
Video RAM - Entire portion of RAM used only
for display
First Row # - Address for top row of video page
Last Row # - Address for bottom row of video page
CRTC Row # - Address for next row load
8080 Row # - Address for cursor row
Character # - Character location in a row
XXXH are hexidecimal numbers

National Semiconductor Data Sheets:
DPB350 Series Programmable CRT Controllers
INSB250 Asynchr~nous Communications Element
DM8678 Bipolar Character Gener·ator ,
INSBOBO Assembly and Reference Manuals
National Semiconductor Application Notes:
Simplify CRT Terminal. Design with the DP8350,
AN-1gB
DM867B

Bipol~r

Character

G~nerator.

AN-167

Data Bus and Differential Line Drivers and Receivers,
AN-83
Transmission Line Characteristics, AN-l 08
Hardware Reference Manual BLC 80/10 Board Level
Computer. National Semiconductor Microcomputer
Systems Chapter 6 - System Interfacing.

5-43

l>
Z

.!&.

CO
CO

Graphics Using the DP8350
Series of CRT Controllers

National Semiconductor
Application Note 212
Charles Carinalli
December 1978

The DPB350 CRT Controller series is a versatile building
block for both low and high-end CRT terminal applications. This appl ication note demonstrates how the
DPB350 may be used in CRT graphics applications.
Although this presentation is general, when specific
examples are given the DPB350 ROM programmed
version of the DPB350 series will be used (BO characters
per row, 24 character rows, 5 x 7 character, 7 x 10
character field size!.

Both of these graphics display generation techniques will.
be discussed here, with demonstrations of how the
DPB350 series may be used to reduce total component
count.

BACKGROUND INFORMATION

In this graphics system (Figure 4) the character generator
block contains a ROM that has been programmed with·
graphic symbols whose size is contained within the
character cell size. This ROM may at the same time
contain alphanumeric characters that do not use the
full character cell size.

CHARACTER GENERATOR GRAPHICS

The basic function of the DPB350 CRT controller is to
control the elements of the "video loop" (Figure 1). A
memory address generated by the CRT controller is
presented to the CRT memory, which stores a record of
what appears on the CRT display. The character generator converts this stored information into serial video
data to the CRT monitor. The intensity of the CRT
electron beam is modulated by this video data and its
position is controlled by the horizontal and vertical sync
pulses generated by the CRT controller.

The block representation and operation of th is system is
the same as the alphanumeric's system previously de·
scribed. The CRT memory presents the same character
cell data to the character generator on every scan line of
that character cell address. The character generator ROM
is organized with addresses defining a particular symbol
and addresses defining which scan line of a character row
the CRT electron beam is currently on; thus defining
the video data for that scan line of the symbol. The
scan line address data comes directly from the DPB350.
The parallel data that results is video datil for that screen
address cell width. This data is then serially shifted to the
CRT monitor with 11 parallel to serial shift register.

The CRT screen video area is divided into character cells
(Figure 2). Each cell has a unique CRT memory address ..
The DPB350 must present the correct cha racter cell
address to the CRT memory at the appropriate CRT
beam location. Use of the line counter outputs of the
DPB350 make possible the subdivision of each 'character cell address into the unique scan line of the 'present
CRT beam location.

This'system allows every scan line of a character row to
have active video information; thus the graphics symbol
may be programmed to all sides of the cha racter cell
providing continuity from cell to cell both horizontally
and vertically. At the same time, the alphanumeric's
character may be programmed with cell to cell spacing.

For the DPB350 and its unique internal ROM program
format, each character cell is composed of 70 dots (7
dots wide and 10 dots high) Figure 3. When using the
DPB350, each of these dots may be active video data,
Typically however, in alphanumeric display systems, the
character generator will provide cell to cell character
spacing on the CRT screen by blanking some number of
rows and columns of dots. That is why the DPB350's
7 x 10 dot field is used with a 5 i< 7 character generator
(2 horizontal and 3 vertical dot spaces).

Character generator graphics is the simplest most costeffective approach to CRT graphics. It requires a minimum of software development and hardware support.
The DPB350 CRT controller provides all the required
timing and control pulses for the CRT memory, character
generator, and CRT monitor.

In fact, it is the character generator that restricts the use
of the full character cell dot field, not the DPB350!
Using a character generator which allows video on every
scan line and all dots of the cell width, makes graphic
capability possible. This type of graphic display generation is called "character generator graphics."

Graphics capability with this system, however, is somewhat limited since individual dot control is not possible;
only character cell symbol control is available. This
system does apply well in such applications as bar
graphs, circuit schematics, or flow charts and when
these need to be combined with alphanumeric data.

All of the dots on the CRT display may also be independently controlled by a separate CRT memory address
location; this is called "memory mapped graphics."

5-44

"VIDEO LOOP"

VIDEO DATA BUS

t..

SERIAL VIDEO DATA

CHARACTER

GENERATOR

r

...

:..

CRT
MEMORY

I(

VIDEO
CONTROL

BUS

..

CRT
MONITOR

1
J

:..

VERTICAL SYNC
CRT
CONTROLLER

HORIZONTAL SYNC

10.83501

CRT MEMORY
ADDRESS BUS

FIGURE 1. Elements of the "Video Loop"
CHARACTER CELLS PER ROW
C
H
A
R
A

0

1

2

3

• ....
....

80

.,

82

83

84

C

160

161

162

163

16.

T
E
R

240

241

242

243

244

·· ···· ·· ··· ··
· ·

1680

1&11

1682

1683

1684

R

1160

1161

1162

1163

1164

W

1840

1841

1842

1843

1844

o
S

....

....

....
....

....

15

16

11

18

19

ROWI

155

156

151

158

159

HOWZ

235

236

m

238

239

ROW3

315

316

m

318

319

ROW4

·
··

ns5

···

1156

1151

1835

1836

1m

1915

1916

19n

· · ·
·· ·· ··
1758

1159

ROW22

1838

1839

RQW23

1918

1919

ROW 24

CELL DOT WIDTH

NUMBER OF
SCAN LINES PER

CHARACTER CEll

..... ..
···.......
.....

THE 0.8350 HAS
1X10=70DDTSPER

CHARACTER CELL

CELL
WIDTH

FIGURE 2. CRT Screen Cell Address Map Presented to
CRT Memory by the DP8350 (Top of Page Register
Contains Address 0) Character Cells Per Row = 80
Character Rows Per Frame =24

FIGURE 3. The DP8350 Character Cell is
7 Dots Wide and 10 Dots High

M
I

CHARACTER
ISYMBOL}

C
R

~~~O~AT~A~B~U~S----------------~\

ADDRESS

R

o
C

E

S
S

o
R

S
Y
S

CRT
MEMORY

T
E
M

I
N

T

HORIZONTAL SYNC

-i

~~________________~A~O~O~RE~"~B~U~S____________

F
A
C
E

~________V~E~R~TI=CA~L~S~Y~NC~________-H~

~~--~~

DOT FREQUENCY
CRYSTAL

FIGURE 4. Character Generator Graphics
5-45

T

E
R
F

A
C
E

CHARACTER GENERATOR GRAPHICS-WITH
LINE BUFFERS

a system will be greater-both software and hardware.
In any case, the DP8350 easily adapts to such a system
as demonstrated in Figure 6.

Modification of the character generator graphics block
diagram is possible with the addition of a recirculating
line buffer placed between the CRT memory and the
character generator (Figure 5). In this case the character
generator addresses for a character row are loaded
serially into this shift register on the scan line before the
first video scan line of a character row. These addresses
are then recirculated for the number of scan lines per
character row minus one (then the next character row of,
addresses is loaded). This system 'allows access to the
CRT memory by tlie system controller on all but one
scan line of a video character row. In contrast, the
system previously described would have allowed access
only during blanking intervals. In systems that require
heavy access to the CRT memory to update screen
information, this approach is very attractive. '

In this approach, if you subdivide each character cell
such that each scan line of the cell may be independently
addressed, then from, the CRT memory block instead of
8 bits of data defining a character cell code to the
character generator, you get 8 bits of direct video data.
Then the CRT memory block serves double duty-CRT
memory storage and symbol or character generator. All
that is left to do is convert this parallel video data to
serial video data as before.
In the case of the DP8350 internal ROM format program,
each cell is 7 dots wide; thus only 7 bits of video data
are needed per character cell/scan line address. The
DP8350 addresses the memory block as before with the
character cell address, but in this case also with the scan
line address. In this manner, the DP8350 series has a
maximum address capability of 16 bits (64k).

In this case, as before, all the required control pulses for
the "video lopp" are provided by the DP8350 CRT
controller.

VARIATIONS

MEMORY MAPPED GRAPHICS

If memory mapped graphics is desirable but standard
alphanumerics is also required, combination of these
techniques is' possible. For example, if only a small
portion of the CRT screen need be memory mapped and
the remainder can be character generator alphanumerics
and/or graphic symbols. In this case a higher order data
bit from CRT memory defines whether the lower order
data bits are graphics video data or ASCII and graphics
symbol code. Figure 7 is a block diagram of such a
system.

If a very high resolution graphics display is required,
every dot of the ,CRT display may be independently
'controlled, In this case, every dot of the CRT screen
may be mapped to a specific CRT memory data bit-thus
the mime Memory, Mapped Graphics. This type of
system is obviously a more costly type of graphics, since
to control every dot not only is there a need for more
CRT memory, but the microprocessor overhead in such

CHARACTER
(SYMBOL )
AODRESS

M
I

C
R

...

o

P -!!TABr-r'
R

o

V~

o
R

T
E
M
I
N

T
E
R

~~

...

CHARACTER
GENERATOR ROM,
GRAPHICS AND
ALPHANUMERICS'

,:>.

'--,...-

C
E
S
S

S
Y
S

RECIRCULATING
LINE BUFFER

~

..........

RECIRCULATE
CLOCK
ENABLE

LATCH
PULSE

~

t4r r ALINE
N
, ADDRESS

~

LOAD
PULSE

co

CRT
MEMORY

...a:z

E

SERIAL
VIDEO
DATA

I
CURSOR
ENABLE

8

ill

-

DOT
CLOCK

..

.,
'"...

ffico
;;

C
R
T
VIDEO
GATING
LOGIC

I VIDEO

M

o

N,

I

T
0,

ADDRESS BUS

CRT CONTROLLER
DP835D

HORIZONTAL SYNC

R

VERTICAL SYNC

I
N

F

A
C

PARALLEL
'TO SERIAL
SHIFT REGISTER

GD~

DOT FREQUENCY
CRYSTAL

FIGURE 5. Character Generator Graphics (With Line Buffer)

5·46

T

E
R

F
A
C
'E

M

t-______...;O;;.A;;.T;..A,;;,B.;;.US;...._ _ _..,

I

C
R

o

OOT
CLOCK

LOAO
PULSE

P
R

o
C
E

S
S

o
R

'"
ii:

S

...a:

....0>

C

8.....----......"

Y

S

T

•••

E
M

R
T

:il
0>

;;

I
N

T
E
R
SCAN LINE
F t---A-O"-O'"R""E"';SS"'B;';U"":S---i
A~

__~~~~__~

~~-------C-EL-L~AOOR~ES-S-BU-S--~~--~

CRT CONTROLLER
OP8350

HORIZONTAL SYNC
t-------------I~ I
N
VERTICAL SYNC
T
1-....;..;;;...=;.;.;.;;.;;......... E

R
F
A

C
E
OOT FREQUENCY
CRYSTAL

FIGURE 6. Dot by Dot (Memory Mapped) Graphics

PARALLEL
TO SERIAL
SHIFT REGISTOR

8TH BIT

~---------------------io
CRT
MEMORY

AOORESS BUS

LCGA
FROM
OPB350

QI-----I~--------_i

eLK

__~
VIDEO

FIGURE 7. Combined Character Generator and Memory Mapped Graphics.

SUMMARY
This application note has demonstrated 2 basic graphics
techniques that may be implemented using the OP8350
CRT controller. Variations to these techniques are
possible such as changing character cell sizes and sub·
dividing the character cell into dot blocks. In most cases,
these variations are done to decrease hardware or soft·
ware overhead. Since the DP8350 series of CRT con·
trollers offer display format flexibility through internal
ROM program variations-the device adapts equally well

to the~e graphics variations as it does to the standard
applications.

The fact that all the required control functions for the
. "video loop" are contained within the same chip-the
OP8350-makes it very effective in these types of appli·
cations; as a result it will produce the minimum chip
count and cost.
5-47

~

National Semiconductor
Application Note 243
Mike Evans
April 1980

Graphicsl
z Alphanumerics Systems
450ns)to output the valid dot word.
This has to be latched into an octal latch and held for one
dot cycle before it can be loaded into the 7-bit shift'
register. The dots are then shifted out in the dot cycle. '

or

CRTC
(8350)

PART OF
ASCII ROM

4·BIT LINE
t£OUNTER

trco:3

ADDRESS BUS

EPROM

!t_

LINE
~~=I=:I=1~l!=j=t=l=tLINE 9
0-:

DATA BUS

EPROM ----::R__++-t+l-+H-f"k-

2 1 0 6 5

REFRESH
RAM

~P

~

r... EPROM

MM2716
EXTRA
CHARACTERS
/SYMBOL~

EPROM

po.

A

MM52116FDW
STANDARD
ALPHA·
NUMERICS
ROM

OCTAL LATCH
H-BIT SHIFT
REGISTER

VIDEO

Refresh RAM MSB:

o selects alphanumeric ROM
1 selects symbol EPROM

Figure 2. Fixed Character ROM + Symbol EPROM

Disadvantages For Graphics
• Fixed graphics possible with continuous display, but limited to 128 different characters, and 128 standard alphanumerics,
lor ell 1920 positions.
•

Also it is not possible to change characters/symbols once the EPROM has been programmed.

•

The Microprocessor is still slow thru·put.

5-50

l>

Limited Graphics Terminal
To be able to generate any graphics symbol, a character
RAM must ·replace the fixed ROM characters. Charac·
ters or symbols can be loaded into the RAM as required
from a. ROM or a pre·programmed EPROM like the
MM2716 (refer to Figure 3). But now, new graphics
characters can be written into the RAM from the Micro·
processor. These can either be derived internally from
the !,P or obtained directly from peripherals (such as
serially to an Asynchronous Communications Element
like the INS8250, or parallel from an external I/O port).

This limited graphics application thus requires two
RAMs, the Refresh RAM (or Character Position RAM),
and the Character RAM. The Refresh RAM outputs the
selected character address, and the 8350 line counter
outputs select the line in the Character RAM. The 7 dots
outputted from this RAM are latched into the Octal Latch
and held for one dot cycle. The 8th bit of data can be
used as an attribute control bit. The 7 LSBs are then
loaded into the 7·bit shift register.

CRTC
(8350r

MM2716
CHARACTERI
SYMBOL
EPROM

MM52116FDW
ALPHA·
NUMERICS
ROM

~P

4·BIT LINE
COUNTER
LCO·3

REFRESH
RAM

FROM PERIPHERALS

----------------------~
CHARACTER
RAM

Figure 3. Character RAM with ROM/EPROM'Look·Up

Disadvantage for Graphics
•

Only 256 possible characters per display, with the 8·bit data bus, but can re·load different characters for a new frame.

Advantages
•

Can now load standard characters or symbols from EPROM, either at switch·on or during normal running.

•

Can also load characters/symbols/graphics from the liP or peripherals, e.g., to create graphics drawings to connect to
adjacent positions.

•

Can now be a very fast system cycle with·CRTC.

•

Refresh RAM and character RAM can be made the same IC by using one 8k x 8 quasistatic RAM.

by isolating the liP address bus from the CRTC address bus, the liP can share the dot

5-51

z•

I\)

f)

~•

z

-

it

SYMBOL
EPROM

CHARACTER
ROM

,..

~

,..

..

16·BIT
ADDR
BUFFER

,.~

B·BIT
LATCH
BUFFER

>- ... 7'

A
~

II.

,.

B·BIT DATA BUS

...

..

"...

11

I

... po.

~

~
'II

,if

LATCH

DISPLAY RAM
24xBOx10
LOCATIONS
7 DOTSI ADDRESS

"p

.oil

...

",.

~.

640n$
DOT CYCLE

•

~ CRTC-'""'I..f----~p---l.~II-4..!----CRTC__I
Figure 6. Full Graphics System

5·53

:r

OCTAL LATCH
+T-BIT SHIFT
SHIFT REG.

VIDEO

l>
Z•

t

CRTC Address Bus Configuration
The particular RAM address to be written into is
determined by Its 10 x 7 character field position and the
selected line of that field; refer to Figure ~.

and the next 4 addresses A11 to A14 are the 8350 line
counter outputs via a tri-state buffer. The most significant bit, A15 is used to select the· RAM when HI, and the
EPROMs and peripherals when LO

The 11 least significant addresses Ao to A10 contain
character position information from position 0 to 1919,

I-

·1

80 COLUMNS

LINE O-+l~...~...*t-

l-Hf+-+-+-+-+-t-+t+-

4-Hf+-+-+-+-+-t-+t+5

T

~.

2-+14-+-+--1-+-+-+++3-+11+-1-+-1-1-+-++1-

.. ~

r-,~----+-+-------~

6-HH-t.......,...+t+7-Hf+-+-+-+-+-t-+t+-

ROWS

8-+1fH-+--I-+-+-+++-

LINE

·1

---,;;;;r;1

~~*$=I$$t~rI=-

\

\

065432106

I'

, I

11 ILC31LczILCliLcolAl0 I A91 A81 A71 A61A51 A41 A31 Azi Al I AD I

I

SELECT
4 LINE
1-19Z0 ADDRESSES (FROM 2048)_1
RAM ....COUNTER-..
OUTPUTS
0-9

I
AnRIBUTE
BIT

'"

~III
10 10610510410310zIol1001
OISPW8~WoRJ

.,

~~1f8~~0~ROM

RAM LC3 LCZ LCI LCD AID A9 A8 A7 A6 AS A4 A3 AZ Al

I 1 I 0 I 0 I 0 I 0 I 0 I 0·1

,I

I

0 I 0

AD

I 0 10 I 0 I 0 I 0 I 0 I 0 I

LINE 0
POSITION 0
LAST LINE OF r--;--,...,..,--::-r-;---,.--r:-r::--r-:c,-:..,--::-r-::-r-,--,-,-,
DISPLAY START
1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0
AT C800 H
LINE 9
POSITION 0

I I I I I I I I I I I I I I I I I
I

o;sP~WJ~~FO~

I

I 1 11 I 0 I 0 I 1 11

I I

I I

I I I

11 11 0 1 11
1 1 11
1 1
LINE 9
I'
POSITION 1919
START OF r--T-....-...,..--,--;---,.--r-r-.--,-...,..--,-....,--,.--,--,
BACK-UP RAM
1 11 0 11 0 0 0 0 0 0 0 0 0 0 0 0
• AT 0000 H

1

I I
I

AOOREssliWF~~~

I I I I I I I I I I I I I
I

111111 11 11 11 11 1111 11 11 11 11 11 11 11

Figure 7. RAM Addressing

5·54

I

Graphics Design Criteria
2) Paralleled 8·Bit I/O Port, highest priority if CRTC card
is part of a master system, otherwise masked off

In the simple CRT applications, the microprocessor is
used mainly to re·write the Refresh RAM as new infor·
mation is fed in, either from the keyboard, or from the
main computer (via ACE). The f'P can still be used in this
application for alphanumericslgraphics, but it is also
desirable if it can perform graphics computations, such
as drawing lines from the inputted coordinates.

3) Vertical
priority,
register
the n!3w

Sync from the 8350, normally highest
need to quickly change the Top of Page
for scrolling, to change the display before
frame begins

4) ACE, INS8250 -

during serial block transfers this
will take highest priority

This requires the microprocessor to be able to write 7
dot words quickly to the Display RAM. The best way to
implement this is to time multiplex the dot cycle with
the CRTC so that whenever the f'P requires access to
the Display RAM, it merely waits for its slot in the next
dot cycle, which could be up to 640ns later. The infor·
mation is either written or read after 360ns, that is a
maximum of 1f's after the memory access request,
which is fast enough. Now the f'P no' longer has to wait
for blanking to be able to operate, it continues its normal
operation and only enters the WAIT state during RAM
access. Although this is for up to 1f'S, in fact it is in
general invisible because the f'P memory access takes
at least 700 ns.

5) Keyboard - the time to press the keys is much
longer than the interrupt wait time so can be low
priority
6) AID Converter - time for conversion is 1001's so
again can be low priority

Display RAM
The system requires a RAM with 24 x 80 x 10 addresses,
each of 8 bits (representing 7 dots + 1 attribute bit), and
a cycle time of 640ns/2 or 320ns. Using static RAMs
19.2k bytes would require 40 ICs, whereas using dyna·
mic RAMs 16 ICs are necessary, totalling 32k bytes.
This leaves 13k bytes available as spare RAM.

The Microprocessor
Advantages of Dynamic RAMs

The 8080A·2 was chosen for the following reasons:

• Only 16, 16·pin packages instead of 40, 18·pin
packages

• FAST - takes 21.84MHz (2 x 8350 frequency) divided
by 9 (in the 8224), to give a clock cycle of 2.427 MHz,
I.e., 0.41f's per microcycle, or 1.6f's for a short
instruction'
• Software can be developed on STARPLEXTM or
Intellec Development Systems

• Less than $10 for 16,000 bits
Fast access and cycle times using the MM5290·2
(average cycle time is 320ns). Even faster times with
the 5V only 16k MM5295

• INS8080A·2, DP8224 and DP8238 are low cost and
available from National
.

• Standby current only 5% o·f operating current
• Less average power dissipation than for static RAMs

Associated circuitry previously
Application Note AN199

designed

in

This means average power dissipation is 30mA x 12V x
V. x V. x 16 or 1.5W for all 16 packages (only one bank
is accessed per cycle by the CRTC for half the dot cycle
time). For 40, 4k x 1 static RAMs, average power is
80mA x 50V x 40 or 16W. Note that if the MM5295 5V,
16k x 1 dynamic RAM is selected, power dissipation will
be even further reduced, with access and cycle times
about half the 3 rail version.

Note the DP8238 has advanced MEMW mode desirable so that the' microprocessor can go into the
WAIT state earlier in the write cycle.

. Interrupts
The INS8259 is ideal as as an Interrupt Controller,
because most interrupt signals in the system are
positive going, saving D·type flip·flops. It can also be
used to mask off interrupts when necessary.

Disadvantages

Interrupt Priority

• Not easy to interface to
• Need to be refreshed every 2ms of Dynamic RAMs"

1) Horizontal Sync from the 8350, highest priority if row
start has to be quickly changed, normally masked off

• 3 supply rails needed, + 12V, +5V, -5V, but these
are already required for th,e 8080

5·55

see "Refreshing

..z~

c(

Refreshing of the Dynamic RAMs
With 16k dynamic RAMs all 128 rows of every RAM have
to be refreshed every 2ms maximum to maintain valid
data. It is possible to manipulate the addressing of the
CRTC address bus to the dynamic RAM multiplexed address bus, so that there is no need for a separate refresh
counter. This is because for any display row, the 8350 sequences all 80 characters, starting at line 0 and ending at
line 9. Thus we can use the 3 least significant bits of the.
line counter outputs (An, A12, A13, from lCO, LC1, lC2)
for three of the dynamic RAM row address bits, (corresponding to lines 0 to 7 of each display row), and the four
least Significant bits of the character position address
(Ao to A3) for the remaining four RAM row address bits.
See Figure 8.

available for scratch pad, display storage, and Insystem emulation of programs. Therefore each row of
this second bank of dynamic RAMs also has to be
refreshed. By using address bit A4 to select the bank, all
rows of the dynamic RAMs are therefore refreshed every
32 characters, which in fact is eight lines, or in effect
one row of the display. The worst case is when the 32
characters are split over two display rows, There is no
problem during the vertical blanking because the 8350
still outputs incrementing addresses and LCGA continues to activate the control logic. So refreshing still
continues during blanking. Thus the longest period any
RAM row goes without a refresh cycle is 65"s per
line x 10 lines per row x 2 rows 1,3ms, which is still
within the 2ms maximum at 70·C. In other words,
dynamic RAM refreshing ;s automatically performed by
the 8350 sequencing the address and no extra circuitry
is required.

=

Unfortunately, because 19k ad,dresses are required, it is
necessary to use two banks of RAM (8 RAMs in each
bank), giving a total of 32k x 8. This leaves 13k bytes

.
A13, A12, All
LC2, LC1, LCD

•

80 CHARS
31

-------------------------------------------------------------

LINE 9
0
1
2
3
4
5
6
7
B
9
LINE 0

{
~

__________

ONE
ROW

~y~---------------------------J

5 BITS

~
A4, A3, A2, Al, AD

L

SELECT BANK
FIRST
BANK OF a
16k RAMS

4 BITS
3 BITS
7 ROWS
LC4(A14), Al0, A9, AB, A7, AS, A5 _ _ _ _ _~
7 COLUMNS
ROW/COL. EN.

-----I
liAS

....

----f-~r

Figure 8. Automatic RAM Refresh

5-56

SECOND

BANK OF B
16k RAMS

ml

CRT Controller
A graphics/alphanumeric CRT Controller requires the
following (See Figure 9):

6) 50 Hz or 60 Hz capability - the 8350 has a frequency
select input

1) All monitor signals provided - the 8350 provides
Vert/Horiz sync and vertical banking

7) Incrementing position address, tri-state - the 8350
has this, with a maximum enable/disable time of 30 ns

2) Cursor signal - the 8350 has cursor enable

This parameter is important in this application
where it is necessary to switch the memory from the
CRTC address to the microprocessor address, and
back to the CRTC address all in one 7 dot cycle of
640ns. Other CRT controllers are not capable of
enabling and disabling the CRTC address so quickly.

3) Fast dot clock, a 7-dot cycle clock continuous, and a
shift register clock only during display - the 8350
has dot clock, LCGA and LVSR
4) Line counter output 4-bit, tri-state line counter output (but not tri-state)

the 8350 has

Hence the DP8350 requires no extra circuitry apart from
a Quad Latch to disable th,e Line Counter outputs. The
8350 has internal ROMs which determine how many rows
(24), columns (80), lines per row (10), and dots per column
(7). Versions of the 8350 are available with other combinations.

5) Ability to set top of page, row start and cursor reg at
any time - the 8350 can do this using LD REG, RA
and RB inputs during the time the "p is on the CRTC
address bus_ RA and RB can be data bus bits DBO
and DB1, and LD REG can be decoded from the
address bus

LOAD
REGISTERS

RA
RB

SELECT
REGISTER

12-BI1
COM- I--_~-_ CURSOR EN.
PARATOR

VERT, SYNC,
HORIZ, SYNC.
TIMING

VERT. BLANKING

LINE COUNTER
110.92 MHz) x 2
~"

AOORES~
BUS

~

•••

•
,. • • • •' .

_ _IIiI_ _ _ _
CRTC AODRESS ENABLE

~

4-BIT
BUFFER

~

_ _. .

4,BIT LINE CTR

LINE
DOT CK
LCGA
COUNT ENABLE
MEMORY CONTROL LOGIC

Figure 9. 8350 Block Diagram

5-57

LVSR

~

C'I

•

z

<~--------------------------------I
L

8350 ADDRESS
COUNTER

,-1

CRTC ADDRESS
SELECTOR
CRTC AODRESS
8US

a
>C
~----------------~X~------------

HAS

~

,..p ADDRESS

RAM ADDRESS
BUS

CAS

---II

,

\ - 1_ _ _

=><

___
"P_R_OW_ _

l

CRTC ADDRESS

>c

J~~_.-__"_P_CO_LU_M_N_ _ _~~___C.RT_C_CO_L_.__

•

~~~ __ ~_______

•
1

WRITE~

RAM OATA BUS

-<

LATCHED
DATA OUT

SHIFT REG.
INPUT

(CRTC,-11
VAllO

,-2
,-3

(CRTC'I

~-------«~__~_Ll_O_IF_R~_O_-J)~--------~<=====+
DATA LATCHED INTO OCTAL LATCH (FROM ADDRESS a'-l)

OATA LATCHED INTO SHIFT REG (FROM ADORESS , - 2)

Figure 11. Memory Control Logic Timing Diagram

5-59

~.
,

z



Locating the Position of a Dot
The standard DP8350 displays 80 horizontal characters
for each of 24 rows, each character field comprising 10
lines of 7 dots. Thus there are 80 x 7 or 560 horizontal
dots and 24 x 10 or 240 vertical dots in the display. Let
the value of the horizontal dot position be x, where 0" x
< 560, and y be the vertical dot position, where 0" y <
240. Refer to Figure 20.

A good aemonstration of the graphics capability is to
connect an x·y joystick to two analog inputs of the AID
converter and by selecting the program MOVD (move
dot), moving the joystick. The joystick can be moved
quickly from one extreme to another and all dots on the
way are displayed. This program can also use a dot as
the cursor, using the joystick to select its position, and
then to depress keys whenever a desired character is
required at the character position of the dot.

If the x and y values are inputted to the microprocessor,
it can then compute the character position, the line
number and the dot position number. First, the Row
Number r is INTEGER (y/10). This then has to be
multiplied by 80 to produce the ROW START number.
The Column Number then has to be added to this to
obtain the Character Position Number, where the
Column Position c is INTEGER (x/7). The line of the row
is (y - r), and the dot number is (x - c) for the computed
character position.

Dot Word Transfers
With the use of the ACE, it is possible to unload the
contents of the RAM into either an identical terminal to
copy the display, or to store it in a main computer. It can
then be recalled from the computer at a later date and
re-Ioaded into the RAM to be displayed. Or if desired,
sections of the display can be transferred. Copying
from or to the display can be fast, because 7 dots are
read or written at a time. An example of this is to use the
programs SAVE and LOAD .. A section of the display
(such as a circuit diagram) can be saved in the back·up
RAM, and then loaded back on to the display in a
different area. The diagram appears almost instantly.

For the 8080 microprocessor, multiplication and division
of numbers is laborious and time consuming. It is there·
fore easier to use the program subroutine shown in Fig·
ure 21 to compute the character position, line number,
and dot number. A separate subroutine then computes
the dot word from the dot number. This 7·dot word is
then ORed with the word already in the computed dyna·
mic RAM location. All this can be demonstrated using
the program PLOT.

This extra 13k bytes of back·up RAM can also be used
as additional memory for in system emulation of
programs, or for powerful computing capability for
graphics calculations.

This computation takes an average of 300"s and a
maximum of 500"s. Hence up to 3,000 dots can be
plotted per second for any values of x and y to.create a
graphics display.

HORIZONTAL DOT NUMBER x _

VERT DOT
NUMr

y

co '"

"' "'
=== === === === === === ==1===="'::"':;,--

!
0

79

ROW 0

6
7

8

--.;;9
H----+----t- 10
11
12
13
14
15
16
17

80

~1~8H-

LINE 0
NO. L 1
2

81

-+__

_ _ _4-___

=. . .

NMoo::I"Ln!D

159

4
5

1840

0

7
8
9

I
I

ROW 1

CHARACTER

3 POSITION, P
6

II
II

- -;----tt--

DOT NO. d

COL c

ROW r

r-- y

--+---1+--

I
I

x
1841

II
II

I
I
1919

~~~ I

I

ROW 23

~===F====*====--------------------=~====~
COL 0

COL 1

COL 79

ROW r=INTEGER (y/10), LINE L=y-r
COLUMN c=INTEGER (XI7), DOT NUM8ER d=x-c
DOT AT LOCATION x,y IS IN CHARACTER POSITION p, LINE L, DOT NO. d, WHERE p=80rH

Figure 20. CRT Display/83S0 Character Address Positions

5·67

Z
•

I\)

f)

THEN COL. NUMBER IS
25617 OR 36 REM 4
SAVE

~6

IN D,E

SET DOT NUMBER TO 4

ADO 7 TO RESTORE
DOT NUMBER
ADD COL. NUMBER TO
ROW START IN H. L.
H,L NOW CONTAINS
CHARACTER POSITION
IN ADDRESSES A10 TO Ao
ADD SAVED LINE
NUMBER IN Au TO An
WITH A,s=1

ADD 10 TO RESULT TO
OBTAIN LINE NUMBER
SHIFT LEFT 3 POSITIONS
TO CREATE MODIFIED
LINE NUMBER

H,L NOW CONTAINS
RAM ADDRESS OF
CHARACTER POSITION
AND LINE NUMBER
REG CONTAINS DDT NO.

Figure 21. Flow Chart to Add Dot x, y to Display

5-68

Graphics Programs

Display Loading

To perform various graphics functions it was decided to
select the necessary software with four letter program
labels, fOllowed by a carriage return. As long as the
label derived starts at the first column of a row, the
program requested is called up and executed. Some
programs request information from the operator. PLOT
is an example of this, where the values Y1 and X1 are reo
quested by the display. The user types in the desired
values in normal decimal, signifying the end of the number with a carriage return. After both y and x have been
entered, the program continues, in this case plotting a
dot at Y1, X1.

The starting address is first entered (anywhere from
8000 H to FDFFH) by keying in the first two hex numbers
when requested by B = (byte), no carriage return, then
the last two hex numbers. This is repeated for the end
address. The bytes are then entered 2 ASCII characters
at a time. If the addresses are between 8000H and
CFFFH, the words will appear on the display. For
example, 7F will appear as 7 dots, or 83 will appears as
the 2 right-hand dots with attribute. In this way a picture
can be loaded on to the display.

Use of Back-up RAM
If the DMPI addresses are between DOOOH and FDFFH.
the information is stored in the back-up RAM. This is
useful for in-system emulation, for example. By calling
up the program EXTO (External 0), if a program has
previously been loaded in the back-up RAM, starting at
address DOOOH, this program will then be executed after
EXTO, carriage return. Another use of this section of
RAM is the storage of different sequences of circuit
diagrams other than those in the symbol EPROM. The
program DRAW can then call up the starting address.

Conversion of Entered Decimal Numbers
The' conversion of the decimal numbers entered and
saved in the Input Number registers, is performed by the
subroutine ENTR. First the last decimal number entered
(obviously units) is tested for ASCII number units and
then saved. The second number (tens) if entered, is then
tested and decremented until 0 is reached, and each
decrement, 10 is added to the total number. Then the
third number (hundreds) is tested and decremented to 0,
each time 100 is added to the total. At the end of the
conversion, H, L register contains the total number in
binary, This is then saved in the respective register.

Additional Software
The power and versatility of this system is easily
demonstrated with the existing software. This can be
added to as required with new software, calling up
existing subroutines where possible. Up to 4k bytes of
additional software can be incorporated without any
hardware modifications (other than moving two links to
select 2732s instead of 2716s).

Conversion of 2 Hexadecimal Characters to an
8-Bit Word
This subroutine takes 2 ASCII characters each in the
range 0 to 9, A to F, and converts them to a binary word.
First, the 3 ASCII code bits are masked off the number
first entered. This is shifted left 4 times and added to
the masked off 4 bits of the second number entered.
This 8-bit word is now 7 dots plus one attribute bit. With
this method, it is easy to write/read words quickly on to
the display, in the selected location. This can be
demonstrated with the program DMPI (dump·in) as in
the next two sections.

Conclusion
So using all National Semiconductor ICs, at a cost of a
few hundred dollars. the hardware for an intelligent
terminal with full graphics capability can be fitted on
one BLC80/SBC80 size card. The design is ec1sily
expandable to systems requiring color. The bigge"t
modification is to the memory; instead of one bit per
dot, 3 bits are required for blue, green, and red, to givE' 8
possible combinations per dot. A small number of extra
logic ICs are required, as are minor additions to the
software. To select the color, a CTL key can be used
followed by the code for the color. This color will then
be written until changed by the CTL key. A different CTL
key followed by a number could previously have set the
background.

5-69

AN·243
EXTERNAL
DATA BUS

+5V

110 PORT

+

20

Vee

14S

~PDATABUS

'"
KEYBOARD INTERFACE

EXTERNAL

i7O"Ir>-_r-...

U61

EXTERNAL Cl

;

EXTERNAL i7DW
EXTERNAL

.INTERRUPT

3
4

~U"

16 PIN
SOCKET

FO'

TO U20/15

ASCII
INPUT

BAUD
SWITCH ':'"

~+5V
1 (SEE NOTE 1

tm-"C:). U&9/24

GND G2
U20/12

10

19

CLA

U:~~c:~"~5r---1-~---=tr.~~

IU~

______________________________
0S3

U:~~c:~-t---1------t-~--------------------~------~-,,~DATA

J
'!'

c:

J

Ji7IDi

.c:::>-

RSfi

:!!!l..c:::>. TO

BUS

I

TO U69121

J

joIP CONTROL 8US

U69/23

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BAUODUT

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33

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aSR

El~ READY
f3

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SIN 37

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6

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4

J3-11 DATA SET READY

'1.1489

FROM

E5~J3.5SERIAlDATAIN

~

E7E~2
3

U18/12c:>-",_S:.:ET~

NOTES 1. STROBE INPUT MUST BE POSITIVE(+)
Z ALL DEVICES BYPASSED WITH
0.1 ~ 50 vue CAPACITORS BETWEEN
SUPPLY VOLTAGES AND GROUND

J3·3 SERIAL OAYA OUT

U45
'A 14BB

ASYNCHRONOUS
COMMUNICATIONS
ELEMENT

3 UNLESS OTHERWISE SPECifiED, SSI
LOGIC POWER AS FOLLOWS.
Vcc=PlN 14

#

ADOR~SS BUS

U::?2~C)!E!!!

4.

.....1-_ _ +5V

DP8350llNS8080 Full Graphics Video Terminal System -- Peripheral Interface Block

FO~N:E;I:~

:RANSFER TO OTHER
SYSTEMS. LINK El·E2. E3·fe. E5-E6.
AND E7·ES FOR STAND ALONE USE •
CONNECT fl·E3 AND f5·f1

'~.:~~F.t;{;,~" --.J

(

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to ~:l=:;;=:;!:::;!!:!':C~~

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5-73

~

z•

«

88B 00 0
MM271S

MM2116

2~O

MM2716

LS
138

VITA

U18
IN'

8080

,
.04

32

S
374

lS
314

32

0

U19

DP
8238

U46
INS

OS

3648

OS

3648'

LS

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•

SW

02

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NOT
USED

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G[!J 00'" [!JJ. [!J" .".
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M.

MM

5290

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'40

MM

52"

S
240

LS

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@J[!J 00 00 ~~~
LS

=

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1~'

74

S

32

32

LS

B6

UD5~

[!J ~
00 [!J
14

DO

04

....
U6B
ADC

U69
INS
8259

U71

LA'fOUT Of DP835D/INS8oaO GRAPHICS

AlDSKT2

Layout 01 DPB350/lNSBOBO Graphics

Present Capabilities of Alphanumerics/Graphics System
Dumb Terminal Functions
•• All 128 ASCII Characters Displayable
•• Space
•• Carriage Return
•• Horizontal Tab
•• Backspace

(-)or(CTL L)
(-)or(CTL H)

•• linefeed

(+) or (CTL I)

•• Vertical Tab

(t)or(CTL K)

•• Select/Deselect Attribute
•• Tab 8 Spaces

(CTL R) with SW·1 or $·3
(Tab)

(CTL T)

•• Clear Cursor Row

(CTLX)

•• Clear Row Right of Cursor

(CTLS)
(CTL A)

•• Initialize System

•• Select Baud Rate from 110 to 19,200 Using S·1 and CTL E
•• Scrolling Upwards

Non·Standard Character/Symbol Selection
•• By selecting CTL Z, symbols can be displayed for each key of the keyboard, includi~g shifted and control keys. Also
can deselect back to standard ASCII characters with CTL Z.

5-74

»
Z

Graphics Programs
'ClSC:

Clears screen only, leaving 13k back-up RAM
unaffected.

'LIST:

Lists all graphics programs.

'PLOT:

Plots a dot at X, Y. X is the number of horizontal dot positions from the left of screen,
from 0 to 7 x 80 for the 8350, i.e., 0'; x .;
559. Y is the number of vertical dots from
the top of the screen, from 0 to 10 x 24, i.e, .;
o .;y 239. The operator keys in the decimal
values of Y and then X when requested by
the display.

'VLlN:

Draws a vertical line between Y1 and Y2 at
X. These values are entered decimally by
keyboard when requested by the display.

'HLlN:

Draws a horizontal line between X1 and X2
at Y1. These values are entered decimally by
keyboard when requested by the display.

'RECT:

Draws a rectangle linking lines X1, X2, Y1,
and Y2.

'PONG: Bounces a dot around the screen between
the four walls of the display.
'DRAW: Draws a diagram on the screen from a
sequence of operations saved in ASCII code
in memory. The START address of the
sequence is determined by the first four
hexadecimal characters entered on the
keyboard. The address 1DOOH selects a DC
voltage restoring circuit sequence located in
the symbol EPROM. Address 1EOOH selects
a logic circuit and waveforms. Test
sequences can be loaded into back-up RAM
using program 'DMPI' at the starting and
end address entered. This start ac;ldress is
then called up by 'DRAW.' The end address
must contain 0 (zero).
'SAVE:

Saves in the back-up RAM a section of
display contained' withiri rows R1 to R2, and
columns C1 to C2. These values are entered
decimally by keyboard when requested by
display. The start address in the back-up
RAM is selected by the first four
hexadecimal characters entered on the
keyboard.

'lOAD:

loads from the back-up RAM to a section of
display bounded by R1, R2, C1, C2. These
values are entered decimally by keyboard
when requested by the display. The back-up
RAM start address is selected as in SAVE.

'DOTS:

Plots N dots on any line Y1 at postions X1,
Y1: ... XN, Y1; and then any new line
entered in decimal by the operator. Ends the
program by entering 0 (zero) when the next
Y1 is requested.

'MOVD: Uses the 8-channel 8-bit AID converter to
monitor the voltages on a X-V joystick, an
inhibit-draw switch, and an exit-program
switch. In the DRAW mode consecutive dots
are plotted to create a picture as described
by the movement of the joystick. All these
input signals are connected to the first AID
socket. In the inhibit DRAW mode the dot is
moved around by the joystick as a cursor,
and by keying in from the keyboard the
desired charcter, this character will appear
in the character field of the dot.This moving
dot can be used to erase existing dots, or
erase characters by keying 'SPACE' in the
desired position. To exit the program, set the
EXIT program switch in EXIT-DRAW mode
with the Inhibit-Draw Switch in INHIBIT.
'WAVE: Uses the AID converter to create waveforms
on the screen when the signals are
connected to the second AID socket.
'DMPO: Unloads any part of RAM to an external
system starting at an address keyed in by
the operator in hexadecimal characters (four)
and ending at another similarly entered
address. The RAM is unloaded 7 dots at a
time per line of character and converted to
two ASCII characters and then transmitted
serially.
'DMPI:

loads any part of RAM from an external
source (or the keyboard) starting at an
address selected by the first four
hexadecimal characters entered on the
keyboard and ending at another similarly
entered address. The RAM is loaded 7 dots
at a time per line of character, keyed in by
two hexadecimal characters, for each word.
The addresses selected can be display
addresses 8000H to CFFFH or back-up RAM
addresses DOOO to FFFFH (warning: FEOOH
upwards are registers and FFFFH
downwards are stack). Thus a complete _
picture could be loaded on to the display.
Alternately a program could be loaded into
back-up RAM at EXTO (DOOOH), EXT1
(D800H), EXT2 (EOOOH), or EXT3 (FOOOH). the
characters 'EXTn' can then be typed in on
the keyboard and this will then select the
instructions beginning at address EXTn.
Thus in-system emulation is easily
accomplished.

'EXTO:

Executes a program beginning at RAM
address DOOOH. The program must
previously have been entered using DMPI
selecting DOOOH as the starting address.

'EXT1:

As EXTO but starts at D800H.

'EXT2:

As EXTO but starts at EOOOH.

'EXT3:

As EXTO but starts at FOOOH.

5-75

•

N

,J:Io
CA)

National Semiconductor
Application Note 270
Wong Hee
Nick Samaras
February 1982

Software Design for a High
Speed (38.4 kbaud)
Data Terminal

INTRODUCTION
This application note describes a high speed CRT terminal designed around the DP8350 CRT controller and the
INS8080 microprocessor. The hardware is a modified version of the circuit described in Application Note AN-199.
The software was redesigned and optimized for terminal
speed and function. In its present form it is upwards compatible with the Hazeltine 1500 video terminal and has a
limited graphics capability. Furthermore, it is able to
communicate with a host computer via an RS-232 port, at
38.4 kbaud, without using fill·in characters or handshak·
ing. One 2k by 8 EPROM contains all the software required
to implement the terminal. An optional EPROM can be
used to add features such as menu display or to transform
the terminal into a calculator (in the local mode). The
absence of the second EPROM does not affect the operation of the terminal as the software checks for its
·presence.
DATA TERMINAL FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

UNIQUE FEATURES
Graphics Capability: The graphics capability of this
terminal, although limited by the number of symbols (34),
proves to be very helpful. Typical uses include digital
waveform generation (e.g., logic analyzer display), and
graph oriented displays such as histograms. A graphics
menu is available in the local mode. Entering la t from
the keyboard will result in a two line menu display. Line
23 displays upper and lower case characters, while line
24 displays the corresponding graphics symbols (see
Figure 3). In local, entering I B will switch the terminal to
the graphics mode; the ESC key can be used to exit. In remote mode, the format requirements for graphics display
generation are summarized by the flowchart shown at
the bottom of this page.
The same flowchart can be used in local, if the "Iead-in"tt
block is omitted.
Typical transmission sequences are:
7E, 02, 42, 10, 1B
7E, 02, 63,10,10,10, ... ,10, 1B
7E,02,42,8,8,8,4A,7E,OC,7E,OC,1B

Modes: remote/local
Limited graphics
Window scrolling .
Line transmitting and local editing
Hazeltine 1500 compatible'
Video display: two pages, 24 x 80 characters/p~ge
Upper/lower case
Scrolling plus screen roll up/roll down
Cursor: blinking (two rates)
Line, character insert/delete
Attributes: dual intensity/inverse video
Full duplex RS-232 port; 110-38400 baud
Keyboard Input: 7-bit parallel
Full cursor control and addressing
Cursor enable/disable
Single board (BLC/SBC) compatible design

~II

the graphics symbols, along with the upper and lower
case characters, are coded into one 2716 EPROM. As a
result, poth the character set and the graphics symbols
may be customized. The total number of available fonts is
128. The field on each displayed character is 7 rows by 10
columns. The alphanumeric symbols occupy a 5 by 7 subfield typically, except forthose requiring descenders; they
occupy a 5 by 9 section, while the graphics symbols utilize
the whole 7 by 10 field.
Transmit: The data terminal can transmit one line of text
upon receipt of the 14H code from the keyboard in local
mode, Alternately, the host CPU can request transmission
by sending 14H prefixed by the 7E lead-in code.

'The majority of,the sqftware written for the Hazeltine 1500 will run with
no modification. However, there are differences.

t Note that f Indicates a control key entry.
It Lead-in code: 7E_

r---

_+-_-.1

~D-

1-_-+1

GRAPHICS
SYMBOL
SELECT"

I--

* 'Includes the ASCII characters A-Q, a-q, space and DEL.

5-76

CURSOR MOVE
UP, DOWN,
LEFT, RIGHT,
CHARACTER INPUT

ESCI
CLEAR
SCREEN

p

The same function can be used in a relatively unconventional way when programming in BASIC. The majority of
BASIC interpreters used in small business systems or
home computers incorporate a line-oriented editor, almost
adequate for most of the tasks they have to perform: The
basic problem with such editors is that they cannot
change the flow of the program easily. In other words they
cannot change line numbers. This is ashortcoming, as it is
both annoying and tedious having to retype segments of
text in order to change the program flow, just because the
editor cannot handle altering line numbers only.

80 Character Software FIFO: This is one of the key items
that allows terminal communication at 38.4 kbaud without
handshaking. An 80 character first-in, first-out software
buffer is used. The incoming characters are stored temporarily in this buffer, while the microprocessor is servicing
interrupts. As time becomes available, the characters are
retrieved from the FIFO and processed. That includes performing a terminal function or moving an ASCII character
to the video memory. The software allows for a large
number of concurrent service requests such as row start,
keyboard, as well as multiple ACE interrupts.

This terminal offers an efficient solution to this problem.
Simply stated, it allows changing line numbers only. Here
is a brief description of a typical sequence leading to text
and/or line number modification. Let us assume that a
BASIC interpreter is used and that the program that needs
to be changed is in memory. Using the list command, the
program lines to be modified can be displayed. Now, while
in the Command Mode of BASIC, the terminal is switched
to local. The user has effectively at his disposal a screenoriented editor. The cursor can be moved about and text
changed as desired; that, of course, includes line
numbers. When the editing is completed, the user positions the cursor on the line that was altered and types tT.
In response, the cursor scans the line, inverting the attributes. At the same time the line is transmitted to the host
CPU in the same order as it was scanned, from left to right.
Attribute inversion serves as feedback to the user. After
the last character of each line has been transmitted, the
cursor returns to the beginning of the following line. As a
result, consecutive tT keyboard entries transmit successive lines. Thus, altering the flow of a BASIC program involves entering the local mode, changing line numbers,
transmitting the modified program lines, and switching
back to on-line operation. All this can be accomplished at
a fract,ion of the time usually required otherwise. Finally,
entering similar lines of text such as the ones found in
"PRINT" statements, can be accomplished easily by
switching to local, typing the first line and transmitting it;
then moving the cursor up one line, changing the line
number along with parts of the text that are different, retransmitting the line, and so on. In this way the user can
create a long program segment while operating repetitivelyon one line.

Fast Service Routine for Row Start Interrupt: Conventional row start address look-up and loading are not done
during the row start interrupt time; instead, a simple row
counting routine is used. The terminal count (a software
counter) generates a triggering signal for video RAM wraparound address loading. The use of this technique improves the system throughput substantially. Cursor and
Top of the Page address loading (i.e., writing to the appropriate DP8350's registers) is done during the vertical
retrace interval.
Keyboard Controlled Mode Selection: The operating
mode of the terminal can be selected from the keyboard.
To aid the user in identifying which mode the terminal is in,
two cursor blinking rates are used. The low rate indicates
remote mode; a high rate indicates local.
Other functions that can be selected'from the keyboard
are:
1) Upperllower case. The default mode upon power up is
determined by reading the SW3 switch setting.
2) Next page. A software switch that selects for display
page one or two.
Read Cursor: In the local mode the present cursor location can be displayed on line 24, columns 79-80. For example, if the cursor is located on line 8, column 66, entering
I E from the keyboard will result in a display of "Ag" at the
bottom right hand corner of the screen. This can save time
in looking up the ASCII equivalent codes of the X, Y cursor
coordinates to be used in cursor addressing. (Note that,
IE = ENQ = 05H.)
The following is an example of how this could be used in a
BASIC program.

Insert/Delete with Range: This is a rather unusual function that can assist in generating psuedo "screen
window" effects. Specifically, a pre-selected number of
, display lines can scroll while the rest of the display remains fixed. Each "window" is defined as N lines by 80
characters, where: 1 < N < 48, counting from the current
cursor location to the end of page. The brief BASIC program that follows demonstrates the use of this function.
In this example the display lines 1 through 4, and 19
through 24 remain "frozen': The message (100 lines long)
is displayed on lines 5 through 18, demonstrating the
scrolling of a section of the display.
100
110
120
130
140

PRINTCHR$ (&H7E)+CHR$ (&H11)+"Ag"
Upon execution of the above statement, the cursor will
move to line 8, column 66.
Menu Display: In the local mode the user has access to a
menu display that summarizes the terminal's functions,
along with the corresponding control codes (see Figure 1).
This feature is optional and resides in EPROM #2. The important thing to note is that various kinds of menu/HELP
displays can be implemented easily in this fashion. This
function can be accessed from the keyboard. Alternately,
a dedicated HELP key (that generates the 10 code) can be
used.

PRINTCHR$(&H7E) + CHR$(&H11) +" d";
FOR 1= 1 TO 100
PRINT CHR$ (&H7E) + CHR$ (&HlO) + CHR$ (&H49)
+CHR$(12);
PRINT, "WINDOW SCROLLING LINE:", I,
CHR$ (&HOD);
NEXT I

ACKNOWLEDGEMENTS
We would like to thank Barry Siegel for his invaluable
guidance and support. Also we would like to thank Ron
Christopherson for contributing so much of his time to
this project.

5-77

z

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~
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INSERT
CURSOR
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FIGURE 1. Sample Menu Display

Character Generator Fonts

ADDR

........ ......

00OF

'.

:

.....
.... .......
........ ..... .._.

.... ..
:

303F

... ..... .....

404F

:

... . .

:

606F

,
,,

....... ....

i'

:

;
.. ..

:

:

...

:

...

'

..

on ••

..

.

..

: : :

:

:

: :

:

:

....... ..... .. ..
...

... ...

...
.....

:

..

...

505F

ou ••

:

.'

202F

.....

..,

: :

._....

101F

•• u ....

:

::

:

:::

....

..... ...

...

..

..

.-

:

FIGURE 2. Sample Character Font

...

:

.. ..-:

.-

-.

-

.. -. ...

._. .....

_.. ..

-. ..

.. ._- _.- _.. --

'.

--

_. _. -

-

:

.... -.. ..- :._.

...

.-

.....

- -

-.-

-

_. .. _. .. ..

-- _.

:...

-

...

-

._.

:
:

-

FIGURE 3. Graphics Menu Shown at the Bottom of the Screen

A complete listing ofthe software forthe "High Speed Data Terminal" can be found on pages 5-84 through 5-103. A HEX dump
of the character generator set is included on pages 5·82 and 5-83 and the schematic diagram on pages 5·79 and 5-80.
5·78

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5-79

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Part No.
OP8350
INS8080·1
OP8228
OP8224
INS8250

7

MM2716
OM74148

8
9,31,32
10

OM81 LS95
OM74LS365

121019

MM5257

20,22,30

OM74LS74

21

OM74LS73

23

OM74LS86

24,27

OM74LS32

25
26

OM74LS08
OM74LS04

33
37

MM5034

::::Jil:J O!t ::t.
PI-7

TO VDD
CSI
C5l '2V
~al ... F

1'1.3

J.

.( PI.a.,

,

OP8212

39
42
45
46

OM74LS373
OM74166
OM74COO
OS1488
OS1489

47
48

LM555

OM74LSOO

All pull·up resiSlors-4.7k 1/4W

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8

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17 60
18 50
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143'0
70

430
7 20
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50'9
80 U
4112
30 5
20 6
10 9

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22

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02

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2

DUT"13

CONTROL FUNCTIONS SUMMARY
Functions

On·Line / Local

Remarks

OA / OA
00/00
09/ 09
7E, DC / DC
7E, DB / DB
08/ 08
10 / 10
7E, 12 / 12
7E, 1C I 1C
7E,03 / 03
7E,06/ 06
7E, 11, X, Y I
7E,05/ 05

Remote only

Insert
Character insert
Line insert
Line insert with range

7E, 1E I 1E
7E, 1A I 1A
7E,1O,49,Y

Remote only

Delete
Character strip
Character delete
Line delete
Li ne delete with range
Clear to end of line
Clear to end of page

7E,04 I 04
7F I 7F
7E, 13 I 13
7E, 1D,53,Y /
7E, OF I OF
7E,17 / 17

Remote only

Miscellaneous
Local/remote
Upperllower case
Next page
Keyboard lock
Keyboard unlock
Bell

Z
•
I\)
.......
0

Cursor Move/Control
Line feed
Carriage return
Tab
Cursor up
Cursor down
Cursor left
Cursor right
Home
. Home and clear
Enable cursor
Disable cursor
Address cursor
Read curs'or

l>

100
/ 7E
7E,OE I OE
7E, 15 / 15
7E,03 I 03
07/

Local only
Local only

Remote only

Special Functions
Function menu

/10

Graphics on
Graphics off
Graphics menu

7E,02/ 02
7E, 1B I 1B
/ 11

Line transmit
Foreground follows
Background follows
Clear foreground
Scale

7E, 14
7E, 1F
7E, 19
7E, 18

Roll up
Roll down

7E,01 / 01
7E, 16 / 16

I
/
I
/
/

14
1F
19
18
07

A summary of available functions and their corresponding
codes (local mode only):
Enter graphics mode.
Exit graphics mode.
Line 23 displays upper and lower case characters and line
24 the corresponding graphics symbols (local).
Transmits the cursor line and inverts its attributes.

The line above the cursor becomes a scale (1-80). This is
an aid for graphics and text alignment (local).

5·81

~

CHARACTER GENERATOR HEX DUMP

N

•

Z