1983_Signetics_MOS_Microprocessor_Data_Manual 1983 Signetics MOS Microprocessor Data Manual
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MOS Microprocessor
Data Manual 1983
Signetics
Signetics reserves the right to make changes in the products contained in this
book in order to improve design or performance and to supply the best possible
products. Signetics also assumes no responsibility for the use of any circuits
described herein, conveys no license under any patent or other right, and makes
no representations that the circuits are free from patent infringement. Applica·
tions for any integrated circuits contained in this publication are for Illustration
purposes only and Signetics makes no representation or warranty that such
applications will be suitable for the use specified without further testing or
modification. Reproduction of any portion hereof without the prior written con·
sent of Signetics is prohibited.
© Copyright 1983 Signetics Corporation
ii
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
CONTENTS
Product Status Definitions ......................................................................................... iv
Section 1 - Data Communications
SCN2651
Programmable Communications Interface (PCI) ....................................... 1·1
SCN2652/SCN68652
Multi·Protocol Communications Controller(MPCC) .................................... 1·15
SCN26531SCN68653
Polynomial Generator Checker (PGC) ................................................ 1·33
SCN2661/SCN68661
Enhanced Programmable Communications Interface (EPCI) ............................ 1·51
SCN2681 Series
Dual Asynchronous Receiver/Transmitter (DUART) .................................... 1·68
Section 2 - Video Display
CRT Chip Set Comparison Features ............................................................................. 2·1
SCN2670
Display Character and Graphic Generator (DCGG) ...................................... 2·3
SCN2671
Programmable Keyboard and Communications Controller (PKCC) ....................... 2·16
SCN2672
Programmable Video Timing Controller (PVTC) ....................................... 2·37
SCB2673
Video Attributes Controller (VAC) ................................................... 2·58
SCN2674
Advanced Video Display Controller(AVDC) ........................................... 2·69
SCB2675
Color/Monochrome Attributes Controller (CMAC) ..................................... 2·97
Section 3 - Single Chip Microcomputers
SCN80 Series
Single Chip 8·Bit Microcomputer .................................................... 3·1
'SCC80 Series
CMOS Single Chip 8·Bit Microcomputer ............................................. 3·16
SCN8031/SCN8051
Single Chip 8·Bit Microcomputer ................................................... 3·17
'SCC80C311SCC80C51
CMOS Single Chip 8·Bit Microcomputer ............................................. 3·24
Section 4 - SCN68000 16·Blt Family
SCN68000 Series
16·Bit Microprocessor ......... '" ................................................. 4·1
'SCN68008
16·Bit Microprocessor with 8·Bit Bus ............................................... 4·50
SCN68120/SCN68121
Intelligent Peripheral Controller .................................................... 4·52
SCN68230
Parallel Interface/Timer .......................................................... 4·100
SCB68430
Direct Memory Access Interface (DMAI) ............................................ 4·130
'SCN68451
Memory Management Unit. ....................................................... 4·151
'SCN68454
Intelligent Multiple Disk Controller (1M DC) .......................................... 4·152
'SCN68459
Disk Phase Locked Loop (DPLL) ................................................... 4·153
'SCN68562
Dual Universal Serial Communications Controller .................................... 4·154
SCN68681
Dual Asynchronous Receiver/Transmitter (DUART) ................................... 4·156
Section 5 - Video Games
'SCN2621/SCN2622
'SCN2638
'SCN2637
'SCN2650A
Universal Sync Generator (USG) .....................................................
Programmable Video Interface (PVI) ..................................................
Universal Video Interface (UVI) ......................................................
Microprocessor ...................................................................
Section 6 - Application Notes
App Note M22
App Note M24·A
App Note M26
App Note 400
App Note 401
App Note 402
App Note 403
Interface Techniques for the 2651 PCI ................................................ 6·1
Using the 2651 PCI with BISYNC ..................................................... 6·7
Application Techniques for the 2651 PCI .............................................. 6·9
Using the 2653 Polynomial Generator and Checker .................................... 6·11
Using the 2670/71/72173 CRT Terminal Chip Set ....................................... 6·27
2661 Operating Mode Switching Procedures .......................................... 6·43
2670/71/72/73 CRT Set Application Briefs ............................................ 6-44
Section 7 - Mlcrosystems
SMDEV10000
SMSFT1000
SMSFT1600
S68000 User Work Station (UWS) .................................................... 7·1
S68000 Cross Software Macro Assembler ............................................. 7·4
568000 Cross Software PASCAL Cross Complier ....................................... 7·6
5·1
5·2
5·3
5·5
Section 8 - Appendices
General Information .......................................................................................... 8·1
Package Outlines ............................................................................................ 8·2
Sales Offices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8·7
'PRODUCT BRIEF, contact your Signetics sales offices for complete information.
Signetics
iii
MICROPROCESSOR DIVISION
JANUARY 1983
PRODUCT STATUS DEFINITIONS/PART NUMBERING SYSTEM
DEFINITION OF TERMS
Data Sheet Identification
Product Status
Definition
Formative or
In Design
This data sheet contains the design
specifications for product develop·
ment. Specifications may change in
any manner without notice.
Sampling or
Pre·Production
This data sheet contains advance
information and specifications are
subject to change without notice.
'm'Ie'Ii".i"
First
Production
This data sheet contains preliminary
data and supplementary data will be
published at a later date. Signetics
reserves the right to makechangesat
any time without notice in orderto im·
prove design and supply the best
possible product.
No
Identification
Noted
Full
Production
This data sheet contains final
specifications. Signetics reserves
the right to make changes at any
time without notice in order to im·
prove design and supply the best
possible product.
Advance Information
PART NUMBERING SYSTEM
Exampla: SCN2661AC1N28
s
C
N
.._ ..,.J 1
Identifier - Always
se
Process/Power Variation
N = N-Channel
C=C-MOS
B=Blpolar
iv
2
A
T
T
Basic Part Number
2621 A
8031A
2822A
8035A
2638A
8039A
2637A
8040A
2850A
8048A
2851C
8049A
2852A
8050A
2853A
8061A
8OC35
2661A
2661B
80C39
2661C
8OC4O
2870A
8OC48
2670B
8OC49
2671A
80C50
2872A
66000
2873A
66120
26738
66121
66230
26748
28758
66430
2675C
86681
2881A
C
tLIt
Pin Count
14,18,24,28,40, atc.
Package
I=Ceramlc
N=Plastic
L------Tlmlng Variation
S•• appropriate data sheet
L-------Tamparatura
Signetics
C=ODC to +70 0 C
(Commercial)
A= _40°C to +85 D C
(Automotive)
M == - 55°C to + 125°C
(Mllltlry)
p= -20°C to +70 0 C
(Philips)
Section 1
Data
Communications
Signetics
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MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
DESCRIPTION
OTHER FEATURES
The Signetics SCN2651 PCI is a universal
synchronous/asynchronous data communications controller chip designed for microcomputer systems. It interfaces directly to the Signetics SCN2650 microprocessor and may be used in a polled or interrupt driven system environment. The
SCN2651 accepts programmed instructions from the microprocessor and supports many serial data communication
disciplines, synchronous and asynchronous, in the full or half-duplex mode.
• Internal or external baud rate clock
• 16 internal rates-SO to 19,200 baud
• Double buffered transm ilter and recelver
• Full or hall duplex operation
• Fully compatible with 26S0 CPU
• TTL compatible Inputs and outputs
• Single SV power supply
• No system clock required
• 28-pin dual in-line package
The PCI serializes parallel data characters
received from the microprocessor for
transmission. Simultaneously, it can
receive serial data and convert it into
parallel data characters for input to the
microcomputer.
APPLICATIONS
The SCN2651 contains a baud rate genera·
tor which can be programmed to either
accept an external clock or to generate internal transmit or receive clocks. Sixteen
different baud rates can be selected under
program control when operating in the internal clock mode.
The PCI is constructed using Signetics
n-channel silicon gate depletion load tech·
nology and is packaged in a 28-pln DIP.
FEATURES
• Synchronous operation
S to S-blt characters
Single or double SYN operation
Internal character synchronization
Transparent or non-transparent mode
Automatic SYN or DLE-SYN insertion
SYN or DLE stripping
Odd, even, or no parity
Local or remote maintenance loop
back mode
Baud rate: dc to 1M bps (1X clock)
• Asynchronous operation
S to 8-blt characters
1,1 1/2 or 2 stop bits
Odd, even, or no parity
Parity, overrun and framing error detection
Line break detection and generation
False start bit detection
Automatic serial echo mode
Local or remote maintenance loop
back mode
Baud rate: dc to 1M bps (1 X clock)
dc to 62.SK bps (16X clock)
dc to 1S.62SK bps (64X clock)
•
•
•
•
•
•
SCN2651
PIN CONFIGURATION
1
D1
DO
vcc
RiC
i5TR
m
iiSii
BRCLK
TxD
Intelligent terminals
Network processors
Front end processors
Remote data concentrators
Computer to computer links
Serial peripherals
1'iCEMi'fiiSCHG
i5Co
TxRDv
TOP VIEW
PIN DESIGNATION
PIN NO.
27,28.1.2. 5-8
21
12.10
13
11
22
24
23
17
16
18
9
25
19
3
15
14
20
26
4
SYMBOL
NAME AND FUNCTION
TYPE
Do-D7
RESET
8-bit data bus
Reset
Internal register select lines
Read or write command
Chip enable input
Data set ready
Data terminal ready
Request to send
Clear to send
Data carrier detected
Transmitter empty or data set change
Transmitter clock
Receiver clock
Transm itter data
Receiver data
Transmitter ready
Receiver ready
Baud rate generator clock
+5V supply
Ground
I/O
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0
0
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0
1/0
1/0
0
I
0
0
I
I
I
Ao-A1
RIW
CE
DSR
DTR
RTS
CTS
DCD
TxEMT/DSCHG
TxC
RxC
TxD
RxD
TxRDY
RxRDY
BRCLK
Vee
GND
ORDERING CODE
Vcc=SV±S%
PACKAGES
COMMERCIAL
AUTOMOTIVE
MILITARY
O·C to +70·C
-40·C to +8S·C
-SS·C to +12S·C
Ceramic DIP
SCN2651 CC1128
SCN2651CA1128
SCN2651CM1128
Plastic DIP
SCN2651 CCI N28
Contact Factory
Not Available
5ignefics
1·1
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
Table 1
SCN2651
BAUD RATE GENERATOR CHARACTERISTICS
CRYSTAL FREQUENCY=5.0688MHz
THEORETICAL
FREQUENCY
16X CLOCK
BAUD
RATE
0.8 KHz
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200'
ACTUAL
FREQUENCY
16X CLOCK
0.8 KHz
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
PERCENT
ERROR
---0.016
-----0.253
------
DIVISOR
.
3.125
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
NOTE
*Error at 19200 can be reduced to zero by using crystal frequency 4.9152MHz
16X clock Is used In asynchronous mode. In synchronous mode, clock multiplier is 1X.
Table 2
CPU· RELATED SIGNALS
PIN NO.
INPUT/O.UTPUT
FUNCTION
Vee
GNO
RESET
26
4
21
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A,-Ao
10,12
13
11
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I
1/0
TxROY
8,7,6,5,
2,1,28,27
15
RxROY
14
0
TxEMT10SCHG
18
0
+5V supply input
Ground
A high on this input performs a master reset on the SCN2651. This signal asynchronously terminates any device activity and clears the Mode, Command and
Status registers. The device assumes the idle state and remains there until initialized with the appropriate control words.
Address lines used to select internal PCI registers.
Read command when low, write command when high.
Chip enable command. When low, indicates that control and data lines to the PCI
are valid and that the operation specified by the RIW, A, and Ao inputs should be
performed. When high, places the 00-07 lines in the tri-state condition.
8-bit, three-state data bus used to transfer commands, data and status between PCI
and the CPU. Do is the least significant bit; 07 the most significant bit.
This output Is the complement of Status Register bit SRO. When low, it indicates that
the Transmit Oata Holding Register (THR) is ready to accept a data character from
the CPU. It goes high when the data character is loaded. This output is valid only
when the transmitter is enabled. It is an open drain output which can be used as an
interrupt to the CPU.
This output is the complement of Status Register bit SR1. When low, it indicates that
the Receive Data Holding Register (RHR) has a character ready for input to the CPU.
It goes high when the RHR is read by the CPU, and also when the receiver is
disabled. It is an open drain output which can be used as an interrupt to the CPU.
This output is the complement of Status Register bitSR2. When low, it indicates that
the transmitter has completed serialization of the last character loaded by the CPU,
or that a change of state of the OSR or OCD inputs has occurred. This output goes
high when the Status Register is read by the CPU, if the TxEMT condition does not
exist. Otherwise, the THR must be loaded by the CPU for this lineto go high. It is an
open drain output which can be used as an interrupt to the CPU.
PIN NAME
RIW
CE
07-00
1·2
0
Signefics
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE COMMUNICATIONS INTERFACE (PC I)
SCN2651
BLOCK DIAGRAM
1
SYN/DLE CONTROL
DATA BUS
00- 0 7
SYN 1 REGISTER
SYN 2 REGISTER
OLE REGISTER
RESET
AO
A1
(21)
(12)
(10)
RIW
(13)
CE
(11)
OPERATION CONTROL
MODE REGISTER 1
r--
MODE REGISTER 2
COMMAND REGISTER
_
I-'-_-'-_..JI\.
: )
STATUS REGISTER
,----,.---,V
(9)
(25)
RTS
BAUD RATE
GENERATOR
AND
CLOCK CONTROL
--f--
TRANSMIT DATA
HOLDING REGISTER
TRANSMIT
SHIFT REGISTER
(16)
J
I--
-
a
(22)
DCD
CTs
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TxiiiiY
r(=-19.:..:)_.... TxD
(20)
BRCLK
DSR
10-.;...(1...;5)_....
TRANSMITTER
f
10--'-(1...;4)'-....
RECEIVER
.-----.---f
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RECEIVE DATA
HOLDING REGISTER
I
(3)
liXiiiW
RxD
-
(17) _
(23)
DTR
(24)
TxErii'1
(18)
MODEM
CONTROL
(26)
....1 - - - (4)
Vcc
_aND
iiSciffi
BLOCK DIAGRAM
Timing
Modem Control
The PCI consists of six major sections.
These are the transmitter, receiver, timing,
operation control, modem control and
SYN/DLE control. These sections communicate with each other via an internal data
bus and an internal control bus. The internal
data bus interfaces to the microprocessor
data bus vi.a a data bus buffer.
The PCI contains a Baud Rate Generator
(BRG) which is programmable to accept external transmit or receive clocks or to divide
an external clock to perform data commun ications. The unit can generate 16 commonly used baud rates, anyone of which can be
selected for full duplex operation. See Table
1.
The modem control section provides interfacing for three input signals and three output signals used for "handshaking" and status indication between the CPU and a
modem.
Operation Control
The Receiver accepts serial data on the RxD
pin, converts this serial input to parallel format, checks for bits or characters that are
unique to the communication technique
and sends an "assembled" character to the
CPU.
This functional block stores configuration
and operation commands from the CPU and
generates appropriate signals to various internal sections to control the overall device
operation. It contains read and write circuits
to permit communications with the microprocessor via the data bus and contains
Mode Registers 1 and 2, the Command Register, and the Status Register. Details of register addressing and protocol are presented
in the PCI Programming section of this data
sheet.
Receiver
Transmitter
The Transmitter accepts parallel data from
the CPU, converts itto a serial bit stream, inserts the appropriate characters or bits
(based on the communication technique)
and outputs a composite serial stream of
data on the TxD output pin.
Signetics
SYN/DLE Control
This section contains control circuitry and
three 8-bit registers storing the SYN1,
SYN2, and DLE characters provided by the
CPU. These registers are used in the synchronous mode of operation to provide the
characters required for synchronization,
idle fill and data transparency.
INTERFACE SIGNALS
The PCI interface signals can be grouped
into two types: the CPU-related signals
(shown in Table 2), which interface the 2651
to the microprocessor system, and the
device-related signals (shown in Table 3),
which are used to interface to the communications device or system.
1·3
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
Table 3
DEVICE·RELATED SIGNALS
PIN NAME
PIN NO.
INPUT/OUTPUT
BRCLK
20
I
25
I/O
9
I/O
RxD
TxD
3
19
0
DSR
22
I
DCD
16
I
CTS
17
I
DTR
24
0
RTS
23
0
NOTE
"RX'C and
"f"XC outputs have short circuit protection max.
FUNCTION
5.0688MHz clock input to the internal baud rate generator. Not required if external
receiver and transmitter clocks are used.
Receiver clock. If external receiver clock is programmed, this input controls the rate
at which the character is to be received. Its frequency is 1X, 16X or 64X the baud rate,
as programmed by Mode Register 1. Data is sampled on the rising edge oflhe clock.
If internal receiver clock is programmed, this pin becomes an output at 1X the programmed baud rate. *
Transmitter clock. If exiernal transmitter clock is programmed, this input controls
the rate at which the character is transmitted. Its frequency is 1X, 16X or 64X the
baud rate, as programmed by Mode Register 1. The transmitted data changes on the
falling edge of the clock. If internal transmitter clock is programmed, this pin becomes an output at 1X the programmed baud rate. *
Serial data input to the receiver. "Mark" is high, "Space" is low.
Serial data output from the transmitter. "Mark" is high, "Space" is low. Held in Mark
condition when the transmitter is disabled.
General purpose input which can be used for Data Set Ready or Ring Indicator condition. Its complement appears as Status Register bit SRl. Causes a low output on
TxEMT/DSCHG when its state changes.
Data Carrier Detect input. Must be low in order for the receiver to operate. Its complement appears as Status Register bit SR6. Causes a low output on
TxEMT/DSCHG when its state changes.
Clear to Send input. Must be low in order for the transmitter to operate. If it goes
high during transmission, the character in the Transmit Shift Register will be
transmitted before termination.
General purpose output which is the complement of Command Register bit CR1.
Normally used to indicate Data Terminal Ready.
General purpose output which is the complement of Command Register bit CR5.
Normally used to indicate Request to Send.
I
OPERATION
CL 100pf
Receiver
assumed and the receiver continues to sample the input line at one bit time intervals
until the proper number of data bits, the parity bit, and the stop bitls) have been assembled. The data is then transferred to the Receive Data Holding Register, the RxRDY bit
in the status register is set, and the RxRDY
output is asserted. If the character length is
less than 8 bits, the high order unused bits inthe Holding Register are set to zero. The
Parity Error, Framing Error, and Overrun
Error status bits are strobed into the status
register on the positive going edge of RxC
corresponding to the received character
boundary. If a break condition is detected
IRxD is low for the entire character as well as
the stop bit lsI), only one character consisting of all zeroslwith the FE status bit set) will
be transferred to the Holding Register. The
RxD input must return to a high condition
before a search for the next start bit begins.
The SCN2651 is conditioned to receive data
when the DCD input is low and the RxEN bit
in the command register is true. In the
asynchronous mode, the receiver looks for
a high to low transition of the start bit on the
RxD input line. If a transition is detected, the
state of the RxD line is sampled again after a
delay of one-half of a bit time. If RxD is now
high, the search for a valid start bit is begun
again. If RxD is still low, a valid start bit is
When the PCI is initialized into the synchronous mode, the receiver first enters the hunt
mode on a 0 to 1 transition of RxEN ICR2!. In
this mode, as data is snifted into the Receiver Shift Register a bit at a time, the contents
of the reg ister are compared to the contents
of the SYN1 register. Iflhe two are not equal,
the next bit is shifted in and the comparison
is repeated. When the two registers match,
The functional operation of the SCN2651
is programmed by a set of control words
supplied by the CPU. These control words
specify items such as synchronous or
asynchronous mode, baud rate, number of
bits per character, etc. The programming
procedure is described in the PCI Programming section of this data sheet.
After programming, the PCI is ready to perform the desired communications functions. The receiver performs serial to parallel conversion of data received from a
modem or equivalent device. The transmitter converts parallel data received from the
CPU to a serial bit stream. These actions are
accomplished within the framework specified by the control words.
1·4
SCN2651
Signetics
the hunt mode is terminated and character
assembly mode begins. If single SYN operation is programmed, the SYN DETECT status bit is set. If double SYN operation is
programmed, the first character assembled
after SYN1 must be SYN2 in order for the
SYN DETECT bit to be set. Otherwise, the
PCI returns to the hunt mode. INote thatthe
sequence SYN1-SYN1-SYN2 will not
achieve synchronization!. When synchronization has been achieved, the PCI continues
to assemble characters and transfer them to
the Holding Register, setting the RxRDY
status bit and asserting the RxRDY output
each time a character is transferred. The PE
and OE status bits are set as appropriate.
Further receipt of the appropriate SYN sequence sets the SYN DETECT status bit. If
the SYN stripping mode is commanded,
SYN characters are not transferred, to the
Holding Register. Note that the SYN characters used to establish initial synchronization
are not tran'sferred to the Holding Register
in any case.
Transmitter
The PCI is conditioned to transmit data
when the CTS input is low and the TxEN
command register bit is set. The SCN2651
indicates to the CPU that it can accept a
character for transmission by setting the
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
TxRDY status bit and asserting the TxRoY
output. When the CPU writes a character
into the Transmit Data Holding Register,
these conditions are negated. Data is transferred from the Holding Register to the
Transmit Shift Register when it is idle or
has completed transmission of the previous character. The TxRDY conditions are
then asserted again. Thus, one full character time of buffering is provided.
In the asynchronous mode, the transmitter
automatically sends a start bit followed by
the programmed number of data bits, the
least significant bit being sent first. It then
appends an optional odd or even parity bit
and the programmed number of stop bits. If,
following transmission of the data bits, a
new character is not available in the Transmit Holding Register, the TxD output remains in the marking (high) condition and
the TxEMTJDSCHG output and its corresponding status bit are asserted. Transmission resumes when the CPU loads a new
character into the Holding Register. The
transmitter can be forced to output a continuous low (BREAK) condition by setting the
Send Break command bit high.
In the synchronous mode, when the
SCN2651 is initially conditioned to transmit, the TxD output remains high and the
TxRDY condition is asserted until the first
character to be transmitted (usually a SYN
character) is loaded by the CPU. Subsequent to this, a continuous stream of characters is transmitted. No extra bits (other
than parity, if commanded) are generated
by the PCI unless the CPU fails to send a
new character to the PCI by the time the
transmitter has completed sending the
previous character.
Since synchronous communication does
not allow gaps between characters, the PCI
asserts TxEMT and automatically "fills" the
gap by transmitting SYN1s, SYN1-SYN2
doublets, or DLE-SYN1 doublets, depending on the state of MR16 and MR17. Normal
transmission of the message resumes when
a new character is available in the Transmit
Data Holding Register. If the SEND DLE bit
in the command register is true, the DLE
character is automatically transmitted prior
to transmission of the message character in
THR.
PCI PROGRAMMING
Prior to initiating data communications, the
SCN2651 operational mode must be programmed by performing write operations to
the mode and command registers. In addition, if synchronous operation is programmed, the appropriate SYNJDLE registers must be loaded. The PCI can be
reconfigured at any time during program
execution. However, if the change has an
effect on the reception of a character the
receiver should be disabled. Alternatively if
SCN2651
INITIAL RESET
1
Mode Register 1 must be written
before 2 can be written. Mode Register 2
need not be programmed if external
clocks are used.
NOTE
SVNl Register must be written
before SYN2 can be written, and
SYN2 before OLE can be written.
Figure 1. 2651 Initialization Flow Chart
Table 4
2651 REGISTER ADDRESSING
CE
A1
Ao
R/w
FUNCTION
1
0
0
0
0
0
0
0
0
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
Tri-state data bus
Read receive holding register
Write transmit holding register
Read status reg ister
Write SYN1JSYN2JDLE registers
Read mode registers 1/2
Write mode registers 1/2
Read command register
Write command register
NOTE
See AC Characteristics section for timing requirements.
Signetics
1·5
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2651
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
the change is made 1112 RxC periods after
RxRDY goes active it will affect the next
character assembly. A flowchart of the initialization process appears in Figure 1.
The internal registers of the PCI are accessed by applying specific signals to the
CE, AIW, A1 and Ao inputs. The conditions
necessary to address each register are
shown in Table 4.
The SYN1, SYN2, and DLE registers are
accessed by performing write operations
with the conditions A1 =0, Ao= 1, andRIW=
1. The first operation loads the SYN1 register. The next loads the SYN2 register, and
the third loads the DLE register. Reading or
loading the mode registers is done in a
similar manner. The first write (or read)
operation addresses Mode Register 1, and a
subsequent operation addresses Mode Register 2. If more than the required number of
accesses are made, the internal sequencer
recycles to point at the first register. The
pointers are reset to SYN1 Register and
Mode Register 1 by a RESET input or by
performing a "Read Command Register"
operation, but are unaffected by any other
read or write operation.
Mode Register 1 (MR1)
Table 5 illustrates Mode Register 1. Bits
MR11 and MR10 select the communication
format and baud rate multiplier. 00 specifies
synchronous mode and 1X multiplier. 1X,
16X, and 64X multipliers are programmable
for asynchronous format. However, the
multiplier in asynchronous format applies
only if the external clock input option is
selected by MR24 or MR25.
Mode Register 2 (MR2)
Table 6 illustrates Mode Register 2. MR23,
MR22, MR21, and MR20 control the frequency of the internal baud rate generator
(BRG>' Sixteen rates are selectable. When
driven by a 5.0688 MHz input at the BRCLK
input (pin 20>, the BRG output has zero error
except at 134.5, 2000, and 19,200 baud,
which have errors of +0.016%, +0.235%, and
+3.125% respectively.
MR13 and MR12 select a character length of
5, 6, 7, or 8 bits. The character length does
not include the parity bit, if programmed,
and does not include the start and stop bits
in asynchronous mode.
MR14 controls parity generation. If enabled,
a parity bit is added to the transmitted
character and the receiver performs a parity
check on incoming data. MR15 selects odd
or even parity when parity is enabled by
MR14.
The SCN2651 register formats are summar·
ized in Tables 5, 6, 7 and 8. Mode Registers
Table 5
In asychronous mode, MR17 and MR16
select character framing of 1, 1.5, or 2 stop
bits. (If 1X baud rate is programmed, 1.5 stop
bits defaults to 1 stop bits on transmit>' In
synchronous mode, MR17 controls the
number of SYN characters used to establish
synchronization and for character fill when
the transmitter is idle. SYN1 alone is used if
MR17 = 1, and SYN1-SYN2 is used when
MR17 = O. If the transparent mode is specified by MR16, DLE-SYN1 is used for character fill and SYN Detect, but the normal
synchronization sequence is used. Also
DLEstripping and OLE Detect (with MR14=
0> are enabled.
1 and 2 define the general operational
characteristics of the PCI, while the Com·
mand Register controls the operation with·
In this basic frame·work. The PCI indicates
iis status in the Status Register. these
registers are cleared when a RESET input is
applied.
MR25 and MR24 select either the BRG or the
external inputs TxC and RxC as the clock
source for the transmitter and receiver,
respectively. If the BRG clock is selected,
MODE REGISTER 1 (MR1)
I
MRt7
MR16
ASYNCH: STOP BIT LENGTH
00 = INVALID
01 = 1 STOP BIT
10 = 11/2 STOP BITS
11 = 2 STOP BITS
I
MR14
ParHy Type
Parity Control
Character Length
O=ODD
1 = EVEN
0= DISABLED
1 = ENABLED
00 = 5 BITS
01 =6 BITS
10=7 BITS
11 =8 BITS
MR13
MR11
MR12
MR15
I
MR10
Mode and Baud Rate Factor
00 =
01 =
10 =
11 =
SYNCHRONOUS IX RATE
ASYNCHRONOUS IX RATE
ASYNCHRONOUS 16X RATE
ASYNCHRONOUS 64X RATE
SYNCH: NUMBER
SYNCH: TRANSOF SYN CHAR PARENCY CONTROL
o = DOUBLE SYN
1 = SINGLE SYN
O=NORMAL
1 = TRANSPARENT
NOTE
Baud rate factor In asynchronous applies only if external clock is selected. Factor is 16X if
internal clock is selected. Mode must be selected (MRll, MR10) in any case.
Table 6
MR27
MODE REGISTER 2 (MR2)
I
NOT USED
1-6
MR26
MR25
MR24
Transmitter
Clock
Receiver
Clock
0= EXTERNAL
1 = INTERNAL
0= EXTERNAL
1 = INTERNAL
MR23
Signetics
I
MR22
I
MR21
I
MR20
Baud Rate Selection
0000 = 50 BAU D
0001 = 75
0010 = 110
0011 = 134.5
0100 = 150
0101 = 300
0110 = 600
0111 = 1200
1000 = 1800 BAUD
1001 = 2000
1010 = 2400
1011 =3600
1100 = 4800
1101 = 7200
1110 = 9600
1111 = 19,200
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
the baud rate factor in asynchronous mode
is 16X regardless of the factor selected by
MRll and MR1O. In addition, the corresponding clock pin provides an output at lX
the baud rate.
Command Register (CR)
Table 7 illustrates Command Register. Bits
CRO (TxENI and CR2 (RxENI enable or
disable the transmitter and receiver respectively. A 0 to 1 transition of CR2 forces start
bit search (async mode) or hunt mode (sync
model on the second RxC rising edge. Disabling the receiver causes RxRDY to go
high (inactivel. If the transmitter is disabled,
it will complete the transmission of the
character in the Transmit Shift Register (if
any) prior to terminating operation. The TxD
output will then remain in the marking state
(highl while the TxRDY and TxEMT will go
high (inactive). If the receiver is disabled, it
will terminate operation immediately. Any
character being assembled will be neglected.
Bits CRl (DTR) and CRS (RTSI control the
DTR and RTS outputs. Data at the outputs is
the logical complement of the register data.
In asynchronous mode, setting CR3 will
force and hold the TxD output low (spacing
condition) at the end of the current transmitted character. Normal operation resumes
when CR3 is cleared. The TxD line will go
high for a least one bit time before beginning transmission of the next character in
the Transmit Data Holding Register. In synchronous mode, setting CR3 causes the
transmission of the DLE register contents
prior to sending the character in the Transmit Data Holding Register. CR3 should be
reset in response to the next TxRDY.
Setting CR4 causes the error flags in the
Status Register (SR3, SR4, and SRS) to be
cleared. This is a one time command. There
is no internal latch for this bit.
The PCI can operate in one of four submodes within each major mode (synchronous or asynchronousl. The operational
Table 7
sub-mode is determined by CR7 and CR6.
CR7-CR6 = 00 is the normal mode, with the
transmitter and receiver operating independently in accordance with the Mode and
Status Register instructions.
In asynchronous mode, CR7-CR6 = 01
places the PCI in the Automatic Echo mode.
Clocked, regenerated received data is automatically directed to the TxD line while
normal receiver operation continues. The
receiver must be enabled (CR2 = 1I, but the
transmitter need not be enabled. CPU to
receiver communications continues normally, but the CPU to transmitter link is
disabled. Only the first character of a break
condition is echoed. The TxD output will go
high until the next valid start is detected.
The following conditions are true while in
Automatic Echo mode:
1. Data assembled by the receiver is automatically
placed in the Transmit Holding Register and
retransmitted by the transmitter on the TxD
output.
2. The transmitter is clocked by the receive clock.
3. TxRDY output = 1.
4. The TxEMT/DSCHG pin will reflect only the
data set change condition.
5. The TxEN command (CRO> is ignored.
In synchronous mode, CR7-CR6 = 01
places the PCI in the Automatic SYN/DLE
Stripping mode. The exact action taken
depends on the setting of bits MR17 and
MR16:
1. In the non-transparent, single SYN mode
(MR17-MRI6 = 10>, characters in the data
stream matching SYNI are not transferred to
the Receive Data Holding Register (RHR!.
2. In the non-transparent, double SYN mode
(MRI7-MRI6 = 00>, characters in the data
stream matching SYN1, or SYN2 if immediately
preceded by SYN1, are not transferred to the
RHR. However, onlythefirstSYNl of an SYN1SYNI pair is stripped.
3. In transparent mode (MRI6 =1), characters in
the data stream matching OLE, or SYNI if
immediately preceded by OLE, are not transferred to the RHA. However, only the first OLE
of a OLE-OLE pair is stripped.
Note that Automatic Stripping mode does
not affect the setting of the DLE Detect and
SCN2651
SYN Detect status bits (SR3 and SRS).
Two diagnostic sub-modes can also be
configured. In Local Loop Back mode
(CR7-CR6 = 101, the following loops are
connected internally:
1. The transmitter output is connected to the
receiver input.
2. DTR is connected to DCD and RTS is connected to CTS.
3. The receiver is clocked by the transmit clock.
4. The DTR, RTS and TxD outputs are held high.
5. The CTS, DCD, DSR and RxD inputs are ignored.
Additional requirements to operate in the
Local Loop Back mode are that CRO (TxEN),
CRl IOTR), and CR5 (RTS) must be set to 1.
CR2 (RxEN) is ignored by the PCI.
The second diagnostic mode is the Remote
Loop Back mode (CR7-CR6 = 11). In this
mode:
1. Data assembled by the receiver is automatically
placed in the Transmii Holding Register and
retransmitted by the transmitter on the TxD
output.
2. The transmitter is clocked by the receive clock.
3. No data is sent to the local CPU, but the error
status conditions (PE, OE, FE) are set.
4. The RxRDY, TxRDY, and TxEMT/DSCHG outputs are held high.
5. CRI (TxENI is ignored.
6. All other signals operate normally.
Status Register
The data contained in the Status Register
(as shown in Table 8) indicate receiver and
transmitter conditions and modem/data set
status.
SRO is the Transmitter Ready (TxRDY) status bit. It, and its corresponding output, are
valid only when the transmitter is enabled. If
equal to 0, it indicates that the Transmit
Data Holding Register has been loaded by
the CPU and the data has not been transferred to the Transmit Shift Register. If set
equal to 1, it indicates that the Holding
Register is ready to accept data from the
CPU. This bit is initially set when the Transmitter is enabled by CRO, unless a character
COMMAND REGISTER (CR)
CR7
I
CR6
Operallng Mode
00 = NORMAL OPERATION
01 = ASYNCH: AUTOMATIC
ECHO MODE
SYNCH: SYN AND/OR
OLE STRIPPING MODE
10 = LOCAL LOOP BACK
11 = REMOTE LOOP BACK
CRS
CR4
Request to
Send
Reset Error
0= FORCE RTS
OUTPUT HIGH
1 = FORCERTs
OUTPUT LOW
0= NORMAL
1 = RESET
ERROR FLAG
IN STATUS REG
(FE,OE,
PE/DLE DETECT)
CR3
CR2
CRI
CRD
Receive
Control (RxEN)
Data Terminal
Ready
Transmit
Control (TxEN)
a = FORCE DTR
0= DISABLE
1 = ENABLE
ASYNCH:
FORCE BREAK
O=NORMAL
1 = FORCE
BREAK
SYNCH:
SEND OLE
0= NORMAL
1 = SEND OLE
0= DISABLE
1 = ENABLE
OUTPUT HIGH
1 = FORCE DTR
OUTPUT LOW
1
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2651
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
Table 8
STATUS REGISTER (SR)
SR7
SRS
SR4
SR3
SR2
SR1
SRO
FE/SYN Detect
Overrrun
PE/DLE Detect
TxEMT/DSCHG
RxRDY
TxRDY
0= RECEIVE
HOLDING REG
EMPTY
1 = RECEIVE
HOLDING REG
HAS DATA
0= TRANSMIT
HOLDING
REG BUSY
1 = TRANSMIT
HOLDING
REG EMPTY
SR6
Data Set
Ready
Data Carrier
Detect
O=DSR INPUT
IS HIGH
1 = DSR INPUT
IS LOW
0= DCD INPUT
IS HIGH
1 =DCD INPUT
IS LOW
ASYNCH:
0= NORMAL
1 = FRAMING
ERROR
0= NORMAL
1 = OVERRUN
ERROR
SYNCH:
O=NORMAL
1 =SYN CHAR
DETECTED
has previously been loaded into the Holding
Register. It is not set when the Automatic
Echo or Remote· Loop Back modes are
programmed. When this bit is set, the
TxRDY output pin is low. In the Automatic
Echo and Remote Loop Back modes, the
output is held high.
SR1, the Receiver Ready (RxRDY) status bit,
indicates the condition of the Receive Data
Holding Register. If set, it indicates that a
character has been loaded into the Holding
Registerfrom the Receive Shift Register and
is ready to be read by the CPU. If equal to
zero, there is no new character in the Holding Register. This bit is cleared when the
CPU reads the Receive Data Holding Register or when the receiver is disabled by CR2.
When set, the RxRDY output is low.
The TxEMT/DSCHG bit, SR2, when set,
indicates either a change of state olthe DSR
or DCD inputs or that the Transmit Shift
Register has completed transmission of a
character and no new character has been
loaded into the Transmit Data Holding Reg-
ASYNCH:
0= NORMAL
1 = PARITY
ERROR
SYNCH:
0= NORMAL
1 = PARITY
ERROR
OR
DLECHAR
RECEIVED
0= NORMAL
1 = CHANGE
IN DSROR
DCD,OR
TRANSMIT
SHIFT REGISTER IS
EMPTY
when the receiver is disabled and by the
Reset Error command, CR4.
ister. Note that in synchronous mode this bit
will be set even though the appropriate "fill"
character is transmitted. TxEMT will not go
active until at least one character has been
transmitted. It is cleared by loading the
Transmit Data Holding Register. The
DSCHG condition is enabled when TxEN=l
or RxEN=l. It is cleared when the Status
Register is read by the CPU. When SR2 is
set, the TxEMT/DSCHG output is low.
SR3, when set, indicates a received parity
error when parity is enabled by MR14. In
synchronous transparent mode (MR16 = 1),
with parity disabled, it indicates that a character matching the DLE Register has been
received. However, only the first OLE of two
successive DLEs will set SR3. This bit is
cleared when the receiver is disabled and by
the Reset Error command, CR4.
The Overrun Error status bit, SR4, indicates
that the previous character loaded into the
Receive Holding Register was not read by
the CPU at the time a new received character was transferred into it. This bit is cleared
In asynchronous mode, bit SRS signifies
that the received character was not framed
by the programmed number of stop bits. (If
1.S stop bits are programmed, only the first
stop bit is checked,) If RHR = 0 when SRS = 1
a break condition is present. In synchronous non-transparent mode (MR16 = 0), it
indicates receipt of the SYN1 .character is
single SYN mode or the SYN1-SYN2 pair in
double SYN mode. In synchronous transparent mode (MR16 = 1), this bit is set upon
detection of the initial synchronizing characters (SYNl or SYN1-SYN2) and, after
synchronization has been achieved, when a
DLE-SYN1 pair is received. The bit is reset
when the receiver is disabled, when the
Reset Error command is given in asynchronous mode, and when the Status Register is
read by the CPU in the synchronous mode.
SR6 and SR7 reflect the conditions of the
DCD and DSR inputs respectively. A low
input sets its corresponding status bit and a
high input clears it.
DC ELECTRICAL CHARACTERISTICS4,S,6
PARAMETER
LIMITS
TEST CONDITIONS
Min
VIL
VIH
Input voltage
Low
High
VOL
VOH
Output voltage
Low
High
ilL
Input leakage current
Tristate Output leakage current
Data bus high
ILH
Data bus low
ILL
Icc
1·8
Typ
Max
UNIT
V
0.8
2.0
V
0.4
IOL = 1.6mA
IOH = -100"A
2.4
VIN = 0 to S.2SV
-10
10
Vo = 4.0V
Vo = O.4SV
-10
-10
10
10
Power supply current
1S0
Signetics
"A
"A
mA
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE COMMUNICATIONS INTERFACE (PC I)
SCN2651
ABSOLUTE MAXIMUM RATINGS'
PARAMETEr
Operating ambient temperature 2
Storage temperatUfe
All voltages with respect to ground 3
RATING
UNIT
Note 4
-65 to +150
-0.5 to +6.0
°C
°C
V
1
AC ELECTRICAL CHARACTERISTICS4 ,5,6
PARAMETER
LIMITS
TEST CONDITIONS
Min
tRES
tCE
Pulse width
Reset
Chip enable
tAS
tAH
tcs
tCH
tDS
tOH
tRXS
tRxH
Setup and hold time
Address setup
Address hold
RIW control setup
RIW control hold
Data setup for write
Data hold for write
Rx data setup
Rx data hold
tOD
tOF
tCEo
Data delay time for read
Data bus floating time for read
CE to CE delay
fBRG
fR/T'o
Input clock frequency
Baud rate generator
TxC or RxC
1.0
dc
tBRH 9
tBRL9
tR/TH
tR/TL'O
Clock width
Baud rate high
Baud rate low
TxC or RxC high
TxC or RxC low
70
70
500
500
tTxO
Ircs
TxD delay from falling edge of TxC
Skew between TxD changing and falling
edge of TxC outputS
Typ
UNIT
Max
ns
1000
300
ns
20
20
20
20
225
0
300
350
CL - 100pF
CL = 100pF
250
150
700
ns
ns
ns
MHz
5.0688
5.0738
1.0
ns
CL = 100pF
CL = l00pF
650
0
ns
ns
NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or at any other
condition above those indicated in the operation section of this specification is not implied.
2. For operating at elevated temperatures, the device must be derated based on +150°C maximum
junction temperature.
3. This product includes circuitry specifically designed forthe protection of its internal devices from the
damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range.
5. All voltage measurements are referenced to ground. All time measurements are at the 50% level
for inputs (except tSRH and TSRL) and at O.BV and 2.0V for outputs. Input levels for testing are
0.45V and 2.4V
6. Typical values are at + 25°C, typical supply voltages and typical processing parameters.
7. TxRDY, RxRDY and TxEMT/DSCHG outputs are open drain.
8. Parameter applies when internal transmitter clock is used.
9. Under test conditions of 5.0688MHz 'SRG. tSRH and tSAL measured at V,H and V,L respectively.
10. tRfT and tR/TL shown for all modes except local loopback. For local loop back mode
'R/T=O.7MHz and tRITL=700ns min.
Signetics
1·9
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
CAPACITANCE
TA
= 25°C, Vee = OV
LIMITS
TEST CONDITIONS
PARAMETER
Min
C'N
SCN2651
Typ
UNIT
Max
Capacitance
Input
pF
20
tc = 1MHz
Unmeasured pins tied
to ground
COUT
Output
C,IO
Input/Output
20
20
TIMING DIAGRAMS
CLOCK
RESET
-IBRH- _IBRLI-IRlTH- - I R I T L RESET - t = I R E S - r - - - - - - - - - - -
BRCLK,
TXC, RxC.-J
-lIIBRG-1IfRiT
RECEIVE
TRANSMIT
1 BIT TIME
(1,16, OR 64 CLOCK PERIOOS)-f,
TXc
(IN Pun
~I,----------+~I
TxO
tTxD
ITCS
TxC
(OUTPUn
1·10
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE COMMUNICATIONS INTERFACE (PC I)
TIMING DIAGRAMS
SCN2651
(Cont'd)
TxRDY, TxEMT
1
(Shown for S-bit characters, no parity, 2 stop bits [in asynchronous mode [ )
TxC(IX)
"
T,D
w
c
0
IE
TxEN.
II)
:::>
0
z TiiiDv
0
0:
%
..
(,)
z
TiEiii
II)
CEFOR
WRITE
OFTHR
DATA 2
DATA'
_D_AI'
TxD
I
DATA 3
C
DATA 4
A
I
I'
C
C_D_A
I
DATA 3
I
gw
IAI"21314l51B
I
I
a
DATA 4
I
TxEN
IE
II)
:::>
o
~ "Tx'Ao"Y
:z:
(,)
z
~ TxEMT
CEFOR
WRITE
F THR DATA,
DATA 2
DATA 3
DATA 4
NOTES
A
B
C
= Start bit
= Stop bit 1
= Stop bit 2
=
D
TxD marking condition
TxEMT goes low at the beginning of the last data bit, or, if parity is enabled. at the beginning ofthe parity bit.
READ AND WRITE
CE---".
Signetics
1·11
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
SCN2651
TIMING DIAGRAMS (Cont'd)
RxRDY
(Shown for 5-bit characters, no parity, 2 stop bits
I
in asynchronous mode J
)
RxC
1 I 2 I 3 I 4
RxD
SYNl
15
1
11 2 I 3 I 4 I 51 1 I 2 I 3 I 4 I 5
DATA 2
DATAl
1 I 2
I 3 I 4 I 5
DATA 3
1
1 I 2 : 3 I 4 I
51
DATA 4
!
II
I
2
I
I
3
4
I
51
DATA 5
IGNORED
RxEN
w
0
0
.
:I!
SYNDET
STATUS BIT
:::>
0
z
0
II:
:z:
u
z
>-
.
RxRDY
I
CeFOR
READ
READ
STATUS
READ
STATUS
21314151BIC
RxD
READ
RHR
(DATA 1)
DATAl
.
All
1_
2 I 3 I 4 I 51 B I C I - I D 1 DATA 2
_
U
READ
RHR
(ilATA2)
READ
RHR
(DATA. 3)
READ
RHR
(DATA 3)
A l l I 2 I 3 I 4 I 51 B I
I _
DATA 3
_
w
o
o
~
RxEN
:::>
oz
o
II:
:z:
u
z
~
OVERRUN
STATUS BIT
--------------------~--~------------------------~~
CEFOR
READ
READ
RHR
(DATA 1)
READ
RHR
(DATA 3)
NOTES
= Start bit
A
B
= Stop bit 1
C
"" Stop bit 2
D
= TxD marking condition
1·12
Signetics
~
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
SCN2651
TYPICAL APPLICATIONS
1
ASYNCHRONOUS INTERFACE TO CRT TERMINAL
BRCLK
1....-----1
S.0688MHz
OSCILLATOR
CRT
TERMINAL
ASYNCHRONOUS INTERFACE TO TELEPHONE LINES
ASYNC
MODEM
PHONE
LINE
INTERFACE
5.0688MHz
OSCILLATOR
TELEPHONE
LINE
Signetics
1·13
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE COMMUNICATIONS INTERFACE (PCI)
TYPICAL APPLICATIONS
(Cont'dl
SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE
\
\
ADDRESS BUS
I
\
CONTROL BUS
I
I
\
DATA BUS
.JU~
RxD
SCN2651
TxD
RiC
TxC
SYNCHRONOUS
TERMINAL OR
PERIPHERAL
DEVICE
SYNCHRONOUS INTERFACE TO TELEPHONE LINES
PHONE
LINE
INTERFACE
SYNC
MODEM
t
TELEPHONE
LINE
Manufacturer reserves the right to make design and process
changes and improvements.
1·14
Signe1ics
SCN2651
MICROPROCESSOR DIVISION
JANUARY 1983
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
DESCRIPTION
The SCN2652/68652 Multi-Protocol Communications Controller (MPCC) is a monolithic
n-channel MaS LSI circuit that formats,
transmits and receives synchronous serial
data while supporting bit-oriented or byte
control protocols. The chip is TTL compatible, operates from a single +5V supply,
and can interface to a processor with an 8
or l6·bit bidirectional data bus.
FEATURES
• DC to 1Mbps or 2Mbps data rate
• Bit-oriented protocols (BOP): SOLC,
AOCCP, HOLC
• Byte-control protocols (BCP): DDCMP,
BISYNC (external CRC)
• Programmable operation
8 or IS-bit tri-state data bus
Error control-CRC or VRC or none
Character length-l to 8 bits lor BOP
or 5 to 8 bits lor BCP
SYNC or secondary station address
•
•
•
•
•
•
•
comparison for BCP-BOP
Idle transmission of SYNC/FLAG or
MARK for BCP-BOP
Automatic detection and generation 01
special BOP control sequences, i.e.,
FLAG, ABORT, GA
Zero insertion and deletion lor BOP
Short character detection lor last BOP
data character
SYNC generation, detection, and stripping lor BCP
Maintenance Mode for sell-testing
TTL compatible
Single +5V supply
PIN CONFIGURATION
Vcc=5V±5%
Ceramic DIP
Plastic DIP
1
Txsa
TxE
TxU
TxBE
TxA
RESET
VCC
DBOl
Intelligent terminals
Line controllers
Network processors
Front end communications
Remote data concentrators
Communication test equipment
Computer to computer links
ORDERING CODE
PACKAGES
MM
TxC
DB08
APPLICATIONS
•
•
•
•
•
•
•
SCN2652/SCN68652
DB10
DB02
0811
DB03
DB12
DB04
DB13
DB05
DB14
DB08
DB15
DB07
ii/w
DBEN
COMMERCIAL
AUTOMOTIVE
MILITARY
A2
BYTE
D·C to + 7D·C
- 4D·C to + 85·C
-55·Cto +125·C
Al
AO
lMHz
SCN2652AC114D
SCN2652AA 1140
SCN2652AM1l40
2MHz
SCN2652AC2l40
SCN2652AA2l40
SCN2652AM2140
1MHz
SCN2652AC1 N40
Contact Factory
Not Available
2M Hz
SCN2652AC2N40
Contact Factory
Not Available
TOP VIEW
NOTE
00 is least signtficant bIt, highest number (that is.
DB 15, A2) is most signIficant bit.
NOTE: SCN68652 is identical to SCN2652. Order using part numbers shown above.
BLOCK DIAGRAM
-
r-
PARAMETER CONTROL
SYNC/ADDRESS
REGISTER
PCSAR
1
1
16,..
-
_88IT5_
---16 BITS---
DATA
OB15~~
BUS
DBOO
BUFFER
PARAMETER
CONTROL
REGISTER
-Vee
-GND
PCR
1t
RECEIVER
OATAlST ATUS
REGISTER
JI
RDSR
TRANSMITTER
DATAISTATUS
REGISTER
TDSR
RESET
MM
_INTERNAL
BUS
16
16
A2-AOBYTE_
READ/
WRITE
LOGIC
CEAND
CONTROL
DBEN-
"-
R/W_
SlF
RxE
RxA
RxDA
RxSA
.......
I
RECEIVER
LOGIC AND
CONTROL
Jj
II
1L
TRANSMITTER
LOGIC AND
CONTROL
JCTL
TxE
TxA
TxBE
TxU
Signetics
1·15
JANUARY 1983
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
SCN2652/SCN68652
PIN DESIGNATION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
DB15-DBOO
17-10
24-31
1/0
Data Bus: DB07-DBOO contain bidirectional data while DB15-DB08 contain control and status
information to or from the processor. Corresponding bits of the high and low order bytes can be
WIRE OR'ed onto an 8-bit bus. The data bus is floating if either CE or DBEN are low.
A2-AO
19-21
I
Address Bus: A2-AO select internal registers. The four 16-bit registers can be addressed on a
word or byte basis. See Register Address· section.
BYTE
22
I
Byte: Single byte (8 bit) data bus transfers are specified when this input is high. A low level
specifies 16 bit data bus transfers.
CE
1
I
Chip Enable: A high input permits a data bus operation when DBEN is activated.
"R/W
18
I
Read/Write: "R/W controls the direction of data bus transfer. When high, the data is to be loaded
into the addressed register. A low input causes the contents of the addressed register to be
presented on the data bus.
DBEN
23
I
Data Bus Enable: After A2-AO, CE, BYTE and R/W are set up, DBEN may be strobed. During a
read, the 3-state data bus (DB) is enabled with information for the processor. During a write, the
stable data is loaded into the addressed register and TxBE will be reset if TDSR was addressed.
Reset: A high level initializes all internal registers (to zero) and timing.
RESET
33
I
MM
40
I
Maintenance Mode: MM internally gates TxSO back to RxSI and TxC to RxC for off line diagnostic purposes. The RxC and RxSI inputs are disabled and TxSO is high when MM is asserted.
RxE
8
I
Receiver Enable: A high level input permits the processing of RxSI data. A low level disables the
receiver logic and initializes all receiver registers and timing.
RxA
5
a
Receiver Active: RxA is asserted when the first data character of a message is ready for the
processor. In the BOP mode this character is the address. The received address must match the
secondary station address if the MPCC is a secondary station. In BCP mode, if strip-SYNC
(PCSAR13) is set, the first non-SYNC character is the first data character; if strip-SYNC is zero,
the character following the second SYNC is the first data character. In the BOP mode, the closing
FLAG resets RxA. In the BCP mode, RxA is reset by a low level at RxE.
RxDN
6
a
Receiver Data Available: RxDA is asserted when an assembled character is in RDSRL and is
ready to be presented to the processor. This output is reset when RDSRL is read.
RxC
2
I
Receiver Clock: RxC (1 X) provides timing for the receiver logic. The positive going edge shifts
serial data into the RxSR from RxSI.
S/F
4
a
SYNC/FLAG: S/F is asserted for one RxC clock time when a SYNC or FLAG.character is
detected.
RxSN
7
0
Receiver Status Available: RxSA is asserted when there is a zero to one transition of any bit in
RDSRH except for RSOM. It is cleared when RDSRH is read.
= '1',
= '0'.
RxSI
3
I
Receiver Serial Input: RxSI is the received serial data. Mark
TxE
37
I
Transmitter Enable: A high level input enables the transmitter data path between TDSRL and
TxSO. At the end of a message, a low level input causes TxSO = 1 (mark) and TxA = 0 after the
closing FLAG !BOP) or last character (BCP) is output on TxSO.
TxA
34
0
Transmitter Active: TxA is asserted after TSOM (TDSRs) is set and TxE is raised. This output will
reset when TxE is low and the closing FLAG (BOP) or last character !BCP) has been output on
TxSO.
TxBE'
35
a
Transmitter Buffer Empty: TxBE is asserted when the TDSR is ready to be loaded with new
control informal-ion or data. The processor should respond by loading the TDSR which resets
TxBE.
TxU'
36
a
TxC
39
I
Transmitter Underrun:TxU is asserted during a transmit sequence when the service ofTxBE has
been delayed for one character time. This indicates the processor is not keeping up with the
transmitter. Line fill depends on PCSAR11. TxU is reset by REsET or setting of TSOM (TDSRs),
synchronized by the falling edge of TxC.
Transmitter Clock: TxC (lX) provides timing for the transmitter logic. The positive going edge
shifts data out of the TxSR to TxSO.
TxSO
38
a
Transmitter Serial Output. TxSO is the transmitted serial data. Mark
Vee
GND
32
9
I
+SV: Power supply.
Ground: OV reference ground.
I
"Indicates possible interrupt signal.
1·16
Signetics
space
= '1', space = '0'.
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2652/SCN68652
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
Table 1
GLOSSARY
1
REGISTERS
NO. OF BITS
DESCRIPTION'
Addressable
PCSAR
Parameter Control Sync/Address Register
PCR
Parameter Control Register
16
8
PCSARH and PCR contain parameters common to
the receiver and transmitter. PCSARL contains a
programmable SYNC character (BCP) or secondary
station address (BOP),
RDSR
Receive Data/Status Register
16
RDSRH contains receiver status information. RDSRL
= RxDB contains the received assembled character.
TDSR
Transmit Data/Status Register
16
TDSRH contains transmitter command and status
information. TDSRL = TxDB contains the character to
be transmitted.
Internal
CCSR
HSR
RxSR
TxSR
RxCRC
TxCRC
Control Character Sh if! Reg ister
Holding Shift Register
Receiver Shift Register
Transm itter Sh if! Reg ister
Receiver CRC Accumulation Register
Transmitter CRC Generation Register
8
16
8
8
16
16
These registers are used for character assembly
(CCSR, HSR, RxSR), disassembly (TxSR), and CRC
accumulation/generation (RxCRC, TxCRC)'
NOTE
*H = High byte - bits 15-8
l == Low byte
Table 2
- bits 7-0
ERROR CONTROL
CHARACTER
FCS
BCC
Table 3
SPECIAL CHARACTERS
DESCRIPTION
OPERATION
Frame Check Sequence is
transmitted/received as 16
bits following the last data
character of a BOP message.
The divisor is usually CRCCCITT (Xl. + X'2 + X5 + 1) with
dividend preset to 1's but can
be otherwise determined by
ECM. The inverted remainder
is transmitted as the FCS.
BOP
FLAG
ABORT
Block Check Character is
transmitted/received as two
successive characters following the last data character
of a BCP message. The polynomial is CRC-16(X16+X15+
X2 + 1) or CRC-CCITT with
dividend preset to O's (as
specified by ECM). The true
remainder is transmitted as
the BCC.
The MPCC can be functionally partitioned
into receiver logic, transmitter logic, registers that can be read or loaded by the processor, and data bus control circuitry. The
register bit formats are shown in figure 1
while the receiver and transmitter data
paths are depicted in figures 2 and 3.
Frame message
Terminate communication
01111110
11111111 generation
01111111 detection
01111111
GA
Terminate loop mode repeater
function
Secondary station address
(PCSARL1'
Address
BCP
SYNC
(PCSARL) or (TxDB)2
generation
Character synchronization
NOTES
1. (c:a<:) refers to contents of ~
2. For IDLE = 0 or 1 respectively
14
15
APA
PCSAR
12
13
11
13
14
PCR
12
14
A
RERR
B
12
15
TERR
I
I
14
13
12
NOT DEFINED
RAB/
GA
9
3 2 1 0
S/AR
I
RxDB
I
TxOB
1
8
I
9
8
REOM I RSOM I
I
11
10
TGA
TABORT
I I
5 4
RxCL
10
ROR
I
6
I
10
11
11
C
I
I
I
13
7
8
ECM
~XCLEIRXCLEI
TxCL
I
TDSR
9
I
15
RDSR
10
I PROTO I SS/GA I SAM I IDLE
I
15
FUNCTIONAL DESCRIPTION
FUNCTION
BIT PATTERN
9
8
TEOM
TSOM
I I I
NOTE
Refer to Register Formats for mneumonics and description.
Figure 1. Short Form Register Bil Formals
Signetics
1·17
JANUARY 1983
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
SCN2652/SCN68652
TO
RDSRL
BCP.CiiC
RxSI
MM
~F~------------;---------+
CRC·16=O
COMPARATOR
CRC·CCIT = FOBS
BCP
RESET-----r----~--.,
NOTES
1. Detected in SYNC FF and 7 MS bits of CCSR.
2. In BOP mode, a minimum of two data characters
must be received to turn the receiver active.
RxE
RxA
RxOA
RxSA
RxC
Figure 2. MPCC Receiver DBta Path
f~~::' OR PCSARL (SYNC)
RESET
TxE
TxA
TxBE
.
TRANS·
MITTER
CONTROL
LOGIC
r--------~I
L.:J -
TxSO
TxSR(S)
1 BIT
DELAY
TxU
M
U
TxCRC ACC (16)
CRC·16 OR CRC·CCITT
x
BOP
ZERO
INSERTION
LOGIC
BCP
PARITY
GENERATION
T.e
CONTROL
CHARACTER
GENERATOR
NOTES
FLAG
ABORT
GA
1. TxCAC selected if TEOM = 1 and the last data character has been shifted out of TxSR.
2. In BCP, parity selected will be generated after each character is shifted out of TxSR.
Figure 3. MPCC Transmitter Data Path
1·18
Signetics
ZERO
INSERTION
CONTROL
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2652/SCN68652
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
RECEIVER OPERATION
General
After initializing the parameter control registers (PCSAR and PCR), the RxE input
must be set high to enable the receiver data
path. The serial data on the RxSI is synchronized and shifted into an 8-bit Control
Character Shift Register (CCSR) on the
rising edge of RxC. A comparison between
CCSR contents and the FLAG (BOP) or
SYNC (BCP) character is made until a match
is found. At that time, the S/F output is
asserted for one RxC time and the IS-bit
Holding Shift Register (HSR) is enabled. The
receiver then operates as described below.
1
PROCESSOR
MADE EVERY]
[ *TESTAxC
TIME
FOR
~! s:.! -~
BIT TIME
i
BOP Operation
A flow chart of receiver operation in BOP
mode appears in figure 4. Zero deletion
(after five ones are received) is implemented
on the received serial data so that a data
character will not be interpreted as a FLAG,
ABORT, or GA. Bits following the FLAG are
shifted through the CCSR, HSR, and into
the Receiver Shift Register (RxSR). A character will be assembled in the RxSR and
transferred to the RDSRL for presentation to
the processor. At that time the RxDA output
will be asserted and the processor must take
the character no later than one RxC time
after the next character is assembled in the
RxSR. If not, an overrun (RDSR11 = 1) will
occur and succeeding characters will be
lost.
The first character following the FLAG is the
secondary station address. If the MPCC is a
secondary station (PCSAR12 = 1), the contents of RxSR are compared with the address stored in PCSARL. A match indicates
the forthcoming message is intended forthe
station; the RxA output is asserted, the
character is loaded into RDSRL, RxDA is
asserted and the Receive Start of Message
bit (RSOM) is set. No match indicates that
another station is being addressed and the
receiver searches for the next FLAG.
If the MPCC is a primary station (PCSAR12 =
01, no secondary address check is made;
RxA is asserted and RSOM is set once the
first non-FLAG character has been loaded
into RDSRL and RxDA has been asserted.
Extended address field can be supported by
software if PCSAR12 = O.
---(1)
gx~~~~J'~
SUBSEQUENT
CHARACTERS
START OF
MESSAGE
.,
RAA=1
.------t======~I---=--------~
CH
RxDA.' - - - - - '
s~~
RxDB)
......
...
,- ----(P:.fo~DR~~~1s YES
RDSA~Ov::?:i~R_=~
~
S/F., FOR OtER""
REOM=1~~~~
FLAG
IN ceSR*
>-::N"'O------------------'
YES- END__________________
OF M
.....E
L.::=--=
~
?
Figure 4. BOP Receive
When the 8 bits following the address character have been loaded into RDSRL and
RxDA has been asserted, RSOM will be
cleared. The processor should read this 8bit character and interpret it as the Control
field.
before, RxDA is asserted each time a character has been transferred into RDSRL and
is cleared when RDSRL is read by the processor. RDSRH should only be read when
RxSA is asserted. This occurs on a zero to
one transition of any bit in RDSRH except
for RSOM. RxSA and all bits in RDSRH
except RSOM are cleared when RDSRH is
read. The. processor should check RDSRg_
15 each time RxSA is asserted. If RDSRg is
set, then RDSR12-15 should be examined.
Received serial data that follows is read and
interpreted as the Information field by the
processor. It will be assembled into character lengths as specified oy PCRS-10. As
Receiver character length may be changed
dynamically in response to RxDA: read the
character in RxDB and write the new character length into RxCl. The character
Signetics
length will be changed on the next receiver
character boundary. A received residual
(short) character will be transferred into
RxDB after the previous character in RxDB
has been read, i.e. there will not be an over·
run. In general the last two characters are
protected from overrun.
The CRC-CCITT, ii specified by PCSARs10, is accumulated in RxCRC on each character following the FLAG. When the closing
FLAG is detected in the CCSR, the received
CRC is in the 16-bit HSR. At that time, the
Receive End of Message bit (REOM) will be
set; RxSA and RxDA will be asserted. The
1·19
JANUARY 1983
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
processor should read the last data character in RDSRL and the receiver status in
RDSR9-15. If RDSR'5 = 1, there has been a
transmission error; the accumulated CRCCCITT is incorrect. If RDSR'2-'4 .. 0, the
last data character is not of prescribed
length. Neither the received CRC nor closing FLAG are presented to the processor.
The processor may drop RxE or leave it
active at the end of the received message.
SCN2652/SCN68652
PROCESSOR
BCP Operation
The operation of the receiver in BCP mode
is shown in figure 5. The receiver initially
searches for two successive SYNC characters, of length specified by PCRs-,e, that
match the contents of PCSARL. The next
non-SYNC character or next SYNC character, if stripping is not specified (PCSAR '3 =
0), causes RxA to be asserted and enables
the receiver data path. Once enabled, all
characters are assembled in RxSR and
loaded into RDSRL. RxDA is active when a
character is available in RDSRL. RxSA is
active on a 0 to 1 transition of any bit in
RDSRH. The signals are cleared when
RDSRL or RDSRH are read respectively.
If CRC-16 error control is specified by
PCSARs-l0, the processor must determine
the last character received prior to the CRC
field. When that character is loaded into
RDSRL and RxDA is asserted, the received
CRC will be in CCSR and HSRL. To check
for a transmission error, the processor must
read the receiver status (RDSRH) and examine RDSR,5. This bit will be set for one
character time if an error free message has
been received. If RDSR'5 = 0, the CRC-16 is
in error. The state of RDSR15 in BCP CRC
mode does not set RxSA. Note that this bit
should be examined only at the end of a
message. The accumulated CRC will include all characters starting with the first
non-SYNC character if PCSAR'3 = 1, or the
character after the opening two SYNC's if
PCSAR'3 = O. This necessitates external
CRC generation/checking when supporting
IBM's BISYNC. This can be accomplished
using the Signetics 2653 Polynomial Generator/Checker. See Typical Applications.
If VRC had been selected for error control,
parity (odd or even) is regenerated on each
character and checked when the parity bit is
received. A discrepancy causes RDSR'5 to
be set and RxSA to be asserted. This must
be sensed by the processor. The received
parity bit is stripped before the character is
presented to the processor.
When the processor has read the last character of the message, it should drop RxE
which disables the receiver logic and initializes all receiver registers and timing.
1·20
SIF_1 FOR ONE
FlxC BrrnME
~=1
••- - - - - - - - - - -
RxDA=1
(pROCESSOR SHOULD
READ RxDB)
..... _1
(pROCESSOR SHOULD
READ AND EXAMINE
RDSRH - ROVRN,
RERR (IF VRC SPECIFIEDt
RxE=O
WHEN LAST
CHARACTER HAS
BEEN SERVICED
NOTES
1. Test made every Rxe time.
2. Test made on Rx character boundary.
Figure 5. BCP Receive
TRANSMITTER OPERATION
General
After the parameter control registers
(PCSAR and PCR) have been initialized,
TxSO Is held at mark until TSOM (TDSRa) is
set and TxE is raised. Then, transmitter
operation depends on protocol mode.
BOP Operation
Transmitter operation for BOP is shown in
figure 6. A FLAG is sent after the processor
sets the Transmit Start of Message bit
(TSOM) and raises TxE. The FLAG is used to
synchronize the message that follows. TxA
will also be asserted. When TxBE Is asserted
by the MPCC, the processor should load
TDSRL with the first character of the mes-
Signetics
sage. TSOM should be cleared at the same
time TDSRL is loaded (16-bit data bus) or
immedi!\tely thereafter (8-bit data bus!.
FLAGs are sent as long as TSOM = 1. For
counting the number of FLAGs, the processor should reassert TSOM in response to
the assertion of TxBE.
All succeeding characters are loaded into
TDSRL by the processor when TxBE = 1.
Each character is serialized in TxSR and
transmitted on TxSO. Internal zero insertion
logic stuffs a "0" into the serial bit stream
after five successive "1 s" are sent. This
insures a data character will not match a
FLAG, ABORT, or GA reserved control
character. As each character is transmitted,
the Frame Check Sequence (FCS) is gener-
JANUARY 1983
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
ated as specified by Error Control Mode
(PCSARe-lOl. The FCS should be the CRCCCITT polynomial (X16 + X12+ X5+ 1) preset
to 1s. If an underrun occurs (processor is
not keeping up with the transmitter), TxU
and TERR (TDSR15) will be asserted with
ABORT or FLAG used as the TxSO line fill
depending on the state of IDLE (PCSARlll.
The processor must set TSOM to reset the
underrun condition. To retransmit the message, the processor should proceed with the
normal start of message sequence.
INITIALIZE PClAR, PCR, TDSAH
PROCESSOR
T~x~:~ - - - - -
TxBE .. 1
PROCESSOR
SHOULD LOAD
TxDBANDTSOM_O)
SCN2652/SCN68652
'IL...______
fROCESSOA MAY
ETZ:~I~~TxSQ_.oORT=11111111IF IDLE .. O
FLAG_Q1111110IF IDLE ... 1
A residual character of 1 to 7 bits may be
transmitted at the end of the Information
field. In response to TxBE, write the residual
character length into TxCL and load TxDB
with the residual character. Dynamic alteration of character length should be done in
exactly the same sequence. The character
length will be changed on the next transmit
character boundary.
After the last data character has been
loaded into TDSRL and sent to TxSR (TxBE
= 1), the processor should set TEaM
(TDSRg). The MPCC will finish transmitting
the last character followed by the FCS and
the closing FLAG. The processor should
clear TEaM and drop TxE when the next
TxBE is asserted. This corresponds to the
start of closing FLAG transmission. When
TxE has been dropped, TxA will be low 11/2
bit times after the last bit of the closing
FLAG has been transmitted. TxSO will be
marked after the closing FLAG has been
transmitted.
ON UNDERRUN:
TxU_1, TERR ... 1
(PROCESSOR SHOULD
SETTSOM)
TxlE.1
(pROCESSOR SHOULD
LOAD TxDB WITH
NEXT DATA CHAR)
NO
If TxE and TEaM are high, the transmitter
continues to send FLAGs. The processor
may initiate the next message by resetting
TEaM and setting TSOM, or by loading
TDSRL with a data character and then simply resetting TEaM (without setting TSOMl.
(PROCESSOR SHOULD RESET TEOM
AND SET TSCM OR DROP TJCE)
BCP Operation
Transmitter operation for BCP mode is
shown in figure 7. TxA will be asserted after
TSOM = 1 and TxE is raised. At that time
SYNC characters are sent from PCSARL or
TDSRL (IDLE =0 or 1) as long as TSOM =1.
TxBE is asserted at the start oftransmission
of the first SYNC character. For counting
the number of SYNC's, the processorshould
reassert TSOM in response to the assertion
of TxBE. When TSOM = 0 transmission is
from TDSRL, which must be loaded with
characters from the processor each time
TxBE is asserted. If this loading is delayed
for more than one character time, an underrun results: TxU and TERR are asserted and
the TxSO line fill depend on IDLE
(PCSAR11). The processor must set TSOM
NO
TxA_O
* GA will be transmitted If TGA
Is sel together with TEOM
Figure 6. BOP Transmit
Signetics
1·21
1
JANUARY 1983
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
SCN2652/SCN68652
The default value for all registers is zero.
This corresponds to BOP, primary station
mode, 8-bit character length, FCS = CRCCCITT preset to 1s.
PROCESSOR
TSOM.1
T_E=1
'''''=1 _----__
Tx8E=1
.~-==-----------.--{
----I
For BOP mode the character length register
(PCR) may be set to the desired values
during system initialization. The address
and control fields will automatically be 8bits. If a residual character is to be transmitted, TxCL.should be changed to the residual
character length prior to transmission of
that character.
DATA BUS CONTROL
The processor must set up the MPCC register address (A2-AO>, chip enable (CE), byte
select (BYTE), and read/write (RIW) inputs
before each data bus transfer operation.
la8E_1
(PROCESSOR SHOULD
LOAD TxDB)
@ - -••
During a read operation (RIW = 0>, the
leading edge of OBEN will initiate an MPCC
read cycle. The addressed register will
place its contents on the data bus. If BYTE =
1, the 8-bit byte is placed on OB15-08 or
DB07-00 depending on the H/L status ofthe
register addressed. Unused bits in ROSRL
are zero. If BYTE = 0, all 16 bits (OB15-00>
contain MPCC information. The trailing
edge of DBEN will reset RxOA and/or RxSA
if ROSRL or ROSRH is addressed respectively.
"""_0 - - - - - 1
OBEN acts as the enable and strobe so that
the MPCC will not begin its internal read
cycle until DBEN is asserted.
TxU_1, TERR=1
(pROCESSOR SHOULD
SETTSOM_1)
TRANSMIT ACCUMULATED
Cc,.~: ::~I~~gJ~D~~
Tx8E=1
IPROCESSOR SHOULD
CLEAR TEOM AND
DROPTxE)
TxSO = SYNC OR TxOB DEPENDING ON IDLE BIT
Figure 7. BCP Transmit
and retransmit the message to recover. This
is not compatible with IBM's BISYNC, so
that the user must not underrun when supporting that protocol.
CRC-16, if specified by PCSAR8-10, is generated on each character transmitted from
TOSRL when TSOM = O. The processor
must set TEOM = 1 after the last data character has been sent to TxSR (TxBE = 1>' The
MPCC will finish transmitting the last data
character and the CRC-16 field before sending SYNC characters which are transmitted
as long as TEaM = 1. If SYNCs are not
desired after CRC-16 transmission, the processor should clear TEaM and lower TxE
when the TxBE corresponding to the start of
CRC-16 transmission is asserted, When
TEOM = 0, the line is marked and a new
message may be iniated by setting TSOM
and raising TxE,
If VRC is specified, it is generated on each
data character and the data character
length must not exceed 7 bits. For software
1·22
LRC or CRC, TEaM should be set only if
SYNC's are tequired at the end of the
message block.
Special Case
The capability to transmit 16 spaces is provided for line turnaround in half duplex
mode or for a control recovery situation.
This is achieved by setting TSOM and
TEaM, clearing TEaM when TxBE = 1, and
proceeding as required.
PROGRAMMING
Prior to initiating data transmission or reception, PCSAR and PCR must be loaded
with control information from the processor. The contents of these registers (see
Register Format section) will configure the
MPCC forthe user's specific data communication environment. These registers should
be loaded during power-on initialization
and after a reset operation. They can be
changed at any time that the respective
transmitter or receiver is disabled.
Signetics
Ouring a write operation (RIW = 1), data
must be stable on OB15-08 and/or OB07-00
prior to the leading edge of OBEN. The
stable data is strobed into the addressed
register by OBEN. TxBE will be cleared if the
addressed register was TDSRH or TOSRL.
JANUARY 1983
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
Table 4
MPCC REGISTER ADDRESSING
A1
A2
BYTE
BYTE
SCN2652/SCN68652
=0
16-BIT DATA BUS
0
0
1
1
=1
=
1
REGISTER
AD
DB15 - DBOO
X
0
1
X
0
X
1
X
RDSR
TDSR
PCSAR
PCR"
6-BIT DATA BUS = DB7_0 or DB15-8**
0
0
0
1
0
0
0
1
0
1
0
1
0
0
1
1
1
0
1
1
0
1
1
1
RDSRl
RDSRH
TDSRl
TDSRH
PCSARl
PCSARH
PCRl"
PCRH
NOTES
* peR lower byte does not exist. It will be all "O"s when read.
** Corresponding high and low order pins must be tied together.
Table 5
PARAMETER CONTROL REGISTER (PCR)-(R/W)
BIT
00-07
NAME
Not Defined
MODE
08-10
RxCl
BOP/BCP
Receiver Character length is loaded by the processor when RxClE = O. The
character length is valid after transmission of single byte address and control fields
have been received.
10
9
8
Char. length !blts!
0
0
0
8
0
1
1
0
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
RxClE
BOP/BCP
Receiver Character length Enable should be zero when the processor loads RxCL. The
remaining bits of PCR are not affected during loading. Always 0 when read.
11
FUNCTION
12
TxClE
BOP/BCP
Transmitter Character length Enable should be zero when the processor loads TxCL.
The remaining bits of PCR are not affected during loading. Always 0 when read.
13-15
TxCL
BOP/BCP
Transmitter Character Length is loaded by the processor when TxCLE = O. Character
bit length specification format is identical to RxCL. It is valid after transmission of
single byte address and control fields.
Signetics
1-23
JANUARY 1983
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
Table 6
SCN2652/SCN68652
PARAMETER CONTROL SYNC/ADDRESS REGISTER (PCSAR)·(RIW)
BIT
NAME
MODE
FUNCTION
00-07
S/AR
BOP
SYNC/ADDRESS Register. Contains the secondary station address if the MPCC is a
secondary station. The contents of this register is compared with the first received nonFLAG character to determine if the message is meant for this station.
SYNC character is loaded into this register by the processor. It is used for receive and
transmit bit synchronization with bit length specified by RxCl and TxCL.
BCP
08-10
11
ECM
BOP/BCP
IDLE
BOP
BCP
12
SAM
13
SS/GA
BOP
BOP
BCP
14
PROTO
BOP
BCP
15
Table 7
APA
BOP
10
CRC-CCITT preset to 1's
CRC-CCITT preset to O's
Not used
CRC-16 preset to O's
VRC odd
VRC even
Not used
No error control
ECM should be loaded by the
are idle.
1-8
0
BOP
0
0
BCP
0
0
1
8
1
0
0
8
0
1
1
BCP
5-7
BCP
0
0
1
5-7
1
0
1
BCP
1
1
0
5-8
1
1
1
BCP/BOP
processor during initialization or when both data paths
9
8
Suggested Mode
Char. length
Error Control Mode
-----
Determines line fill character to be used if transmitter underrun occurs ITxU asserted
and TERR set) and transmission of special characters for BOP/BCP.
IDLE = 0, transmit ABORT characters during underrun and when TABORT = 1.
IDLE = 1, transmit FLAG characters during underrun and when TABORT = 1.
IDLE = 0 transmit initial SYNC characters and underrun line fill characters from the
S/AR.
IDLE = 1 transmit 'initial SYNC characters from TxDB and marks TxSO during underrun.
Secondary Address Mode = 1 if the MPCC is a secondary station. This facilitates
automatic recognition of the received secondary station address. When transmitting,
the processor must load the secondllry address into TxDB.
SAM = 0 inhibits the received secondary address comparison which serves to activate
the receiver after the first non-FLAG character has been received.
Strip SYNC/Go Ahead. Operation depends on mode.
SS/GA =1 is used for loop mode only and enables GA detection. When a GA is detected
as a closing character, REOM and RAB/GA will be set and the processor should
terminate the repeater function. SS/GA =0 is the normal mode which enables ABORT
detection. It causes the receiver to terminate the frame upon detection of an ABORT or
FLAG.
SS/GA = 1, causes the receiver to strip SYNC's immediately following the first two
SYNC's detected. SYNC's in the middle of a message will not be stripped. SS/GA = 0,
presents any SYNC's after the initial two SYNC's to the processor.
Determines MPCC Protocol mode
PROTO = 0
PROTO = 1
All Parties Address. If this bit is set, the receiver data path is enabled by an address field
of '11111111' as well as the normal secondary station address.
TRANSMIT DATA/STATUS REGISTER (TDSR) (R/W except TDSR 15)
BIT
00-07
NAME
MODE
FUNCTION
TxDB
BOP/BCP
08
TSOM
Transmit Data Buffer. Contains processor loaded characters to be serialized in TxSR
and transmitted on TxSO.
Transmitter Start of Message. Set by the processor to initiate message transmission
provided TxE = 1.
TSOM = 1 generates FLAGs. When TSOM = 0 transmission is from TxDB and FCS
generation (if specified) begins. FCS, as specified by PCSAR._ 10, should be CRCCCITT preset to 1'so
TSOM = 1 generates SYNCs from PCSARL or transmits from TxDB for IDLE = 0 or 1
respectively. When TSOM = 0 transmission is from TxDB and CRC generation lif
specified) begins.
BOP
BCP
1·24
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
Table 7
BIT
09
SCN2652/SCN68652
TRANSMIT DATA/STATUS REGISTER (TDSR) (RIW except TDSR 15) (Continued)
NAME
TEOM
MODE
1
FUNCTION
Transmit End of Message. Used to terminate a transmitted message.
BOP
TEOM = 1 causes the FCS and the closing FLAG to be transmitted following the
transmission of the data character in TxSR. FLAGs are transmitted until TEOM = O.
ABORT or GA are transmitted if TABORT or TGA are set when TEOM = 1.
BCP
TEOM = 1 causes CRC-16 to be transmitted (if selected) followed by SYNCs from
PCSARL or TxDB (IDLE = 0 or 1,. Clearing TEOM prior to the end of CRC-16
transmission (when TxBE = 1) causes TxSO to be marked following the CRC-16. TxE
must be dropped before a new message can be initiated. If CRC is not selected, TEOM
should not be set.
10
TABORT
BOP
Transmitter Abort = 1 will cause ABORT or FLAG to be sent (IDLE = 0 or 1) after the
current character is transmitted. (ABORT = 11111111)
11
TGA
BOP
Transmit Go Ahead (GA) instead of FLAG when TEOM = 1. This facilitates repeater
termination in loop mode. (GA = 01111111)
12-14
Not Defined
15
TERR
Read
only
BOP
BCP
Table 8
Transmitter Error = 1 indicates the TxDB has not been loaded in time (one character
time -112 TxC period after TxBE is asserted) to maintain continuous transmission. TxU
will be asserted to inform the processor of this condition. TERR is cleared by
setting TSOM. See timing diagram.
ABORT's or FLAG's are sent as fill characters (IDLE = 0 or 1)
SYNC's or MARK's are sent as fill characters (IDLE = 0 or 1), For IDLE = 1 the last
character before underrun is not valid.
RECEIVER DATA/STATUS REGISTER (RDSR)·(Read Only)
BIT
NAME
MODE
FUNCTION
00-07
RxDB
BOP/BCP
Receiver Data Buffer. Contains assembled characters from the RxSR. If VRC is
specified, the parity bit is stripped.
OS
RSOM
BOP
Receiver Start of Message = 1 when a FLAG followed by a non-FLAG has been
received and the latter character matches the secondary station address if SAM = 1.
RxA will be asserted when RSOM = 1. RSOM resets itself after one character time and
has no effect on RxSA.
09
REOM
BOP
Receiver End of Message = 1 when the closing FLAG is detected and the last data
character is loaded into RxDB or when an ABORTIGA character is received. REOM is
cleared on reading RDSRH, reset operation, or dropping of RxE.
10
RAB/GA
BOP
Received ABORT or GA character = 1 when the receiver senses an ABORT character if
SS/GA = 0 or a GA character if SS/GA = 1. RAB/GA is cleared on reading RDSRH, reset
operation, or dropping of RxE. A received ABORT does not set RxDA.
11
ROR
BOP/BCP
Receiver Overrun = 1 indicates the processor has not read last character in the RxDB
within one character time +1/2 RxC period after RxDA is asserted. Subsequent characters will be 10st.RORisclearedon readingRDSRH,resetoperation,ordroppingof RxE.
12-14
ABC
BOP
15
RERR
BOP/BCP
Assembled Bit Count. Specifies the numberof bits in the last received data character of
a message and should be examined by the processor when REOM = 1 (RxDA and RxSA
asserted). ABC = 0 indicates the message was terminated (by a FLAG or GA) on a
character boundary as specified by PCRS-10. Otherwise, ABC = number of bits in the
last data character. ABC is cleared when RDSRH is read, reset operation, or dropping
RxE. The residual character is right justified in RDSRL.
Receiver Error indicator should be examined by the processor when REOM 1 inBOP,
or when the processor determines the last data character of the message in BCP with
CRC or when RxSA is set in BCP with VRC.
CRC-CCITT preset to 1's/O's as specified by PCSARs-1O:
RERR = 1 indicates FCS error (CRC '" FOBS/", 0)
RERR = 0 indicates FCS received correctly (CRC = FOB 1=0)
CRC-16 preset to O's on S-bit data characters specified by PSCARs-1o:
RERR = 1 indicates CRC-16 received correctly (CRC = 0).
RERR = 0 indicates CRC-16 error (CRC '" 0)
VRC specified by PCSARs-1Q:
RERR = 1 indicates VRC error
RERR = 0 indicates VRC is correct
Signetics
1·25
MICROPROCESSOR DIVISION
JANUARY 1983
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
SCN2652/SCN68652
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
TA
T STG
Vcc
Operating ambient temperature2
Storage temperature
Input or output voltages
with respect to GND3
With respect to GND
RATING
UNIT
Note 4
-65 to +150
°C
°C
-0.3 to +15
-0.3 to+7
V
V
DC ELECTRICAL CHARACTERISTICS4,5
LIMITS
TEST CONDITIONS
PARAMETER
Min
Vil
VIH
Input voltage
Low
High
VOL
VOH
Output voltage
Low
High
Icc
Power supply current
III
IOl
Leakage current
Input
Output
CIN
COUT
Capacitance
Input
Output
Typ
UNIT
Max
V
0.8
2.0
V
IOl = 1.6mA
IOH = -100/LA
0.4
2.4
Vcc - 5.25V, TA - O°C
150
VIN = 0 to 5.25V
VOUT = 0 to 5.25V
10
10
VIN = OV, f = 1MHz
VOUT = OV, f = 1MHz
20
20
mA
/LA
pF
AC ELECTRICAL CHARACTERISTICS4 ,5,6
1MHz Clock Version
PARAMETER
Min
tACS
tACH
tos
tOH
tRXS
tRxH
Setup and hold time
Address/control setup
Address/control hold
Data bus setup (write)
Data bus hold (write)
Receiver serial data setup
Receive serial data hold
50
0
50
0
150
150
tRES
tOBEN
Pulse width
RESET
DBEN
250
250
too
ITxo
tOBENO
Delay time
Data bus (read)
Transmit serial data
DBEN to DBEN delay
tOF
Data bus float time (read)
f
Clock (RxC, TxC) frequency
tClK1
tClK1
tClKO
Clock high (MM - OJ
Clock high (MM = 1)
Clock low
1·26
Typ
2M Hz Clock Version
Max
Min
Typ
UNIT
Max
ns
50
0
50
0
150
150
ns
m7
250
200
m7
ns
200
325
200
170
250
200
150
1.0
340
490
490
165
240
240
Signetics
150
ns
2.0
MHz
ns
JANUARY 1983
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
NOTES
1. Stresses above those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or at any other condition above those indicated in the operation
sections of this specification is not implied.
2. For operating at elevated temperatures the device must be derated based on +15QoC
maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal
devices from the damaging effects of excessive static charge. Nonetheless, it is
suggested that conventional precautions be taken to avoid applying any voltages
larger than the rated maxima.
SCN2652/SCN68652
4. Parameters are valid over operating temperature range unless otherwise specified.
See ordering code table for applicable temperature range and operating supply
range.
5. All voltage measurements are referenced to ground. All time measurements areat
o.av or 2.0V. Input voltage levels for testing are O.4V and 2.4V.
6. Output load CL =100pF.
7. m =TxC low and applies to writing to TDSRH only.
TIMING DIAGRAMS
RESET
READ AND WRITE DATA BUS
OBEN
IOBEN-
AO-A2
-------"'x ::.=..--------.::,:
IACS---ti-J'"
CE'RIWi~'
BYTE
....
0 0 -0 15
(READ)
'ACS
FLOATING
-----------NOT
Jl VALID A VALID
-'OO-t
00- 0 15
(WRITE)
'OS-t
-
-
-~-----------
-'ACH
-~----------
I-'ACH
FLOATING
A
I-'OF
A
-~'OH
CLOCK
1------1/1-----·1
TxC
X
l
TxSO
----+---JI~----------_r-------------I-TxO-1
I
I
RxC
*,--------
1 - IClKO-I-IClK1I
I
I
1-'Rxs-I_'RxH-l
RxSI
~!
I
I
Signetics
1·27
1
MICROPROCESSOR DIVISION
JANUARY 1983
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
SCN2652/SCN68652
TIMING DIAGRAMS (Cont'd)
TRANSMIT-START OF MESSAGE
TxC
---------8 T x C ' - - - - - - - - ; f - - - . J
SYNC/FLAG'
1ST CHAR
TxBE
LOAD 'st CHAR
RESET TSOM
LOAD 2nd CHAR
~
DBEN
-_....
TxE
TxA
-----_....
1s1 CHAR
1, SYNC may be 5 to 8 bits and will contain parity bit as specified.
2. TxA goes high relative to TxC rising edge after TSOM has been set and TxE has been
raised.
3. TxBE goes low relative to DB EN falling edge on the first write transfer into TOSR.1t is
reasserted 1 TxC time before the first bit of the transmitted SYNC/FLAG. TxBE then
goes low relative to DBEN falling edge when writing into TDSRH andlor TDSRL. It is
reasserted on the rising edge of the TxC that corresponds to the transmission afthe
last bit of each character, except in eop mode when the CRC isto be sent as the
next character (see Transmit Timing-End of Message),
TRANSMIT-END OF BOP MESSAGE
TxSO
LAST CHAR
NEXT TO LAST CHAR
LOAD LAST CHAR
SETTEOM
I
~
MARK
CRC
RESET TEOM
DBEN
I--------r-----
\I
T.A6------------------------------------------------------~,,-------NOTES
4. TxBE goes low relative to the falling edge of DB EN corresponding to loading
TDSRH/L. It goes high one TxC before character transmission begins and also when
TxA has been dropped.
5. TxE can be dropped before resetting TEOM if TxBE (corresponding to the closing
FLAGI is high. Alternatively TxE can remain high and a new message initiated.
6. TxA goes low after TxE has been dropped and 1 1/2 TxC's after the last bit of the
closing FLAG has been transmitted.
1-28
Signetics
JANUARY 1963
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
SCN2652/SCN68652
TIMING DIAGRAMS (Cont'dJ
1
TRANSMIT TIMING-END OF BCP MESSAGE
TxSO
NEXT TO LAST CHAR
LAST CHAR
----------~--------~----------~
MARK
TXBE~
LOAD LAST CHAR
DBEN
SET TEOM
RESET TEOM
J . . . ____---In'L.________...Jnl...__________
1------------------------
TxE
1----------
TxA NOTES
7. When 2652 generated CRC is not required, TEOM should only be set if SYNCs are to
follow the message block. In that case, TxE should be dropped in response to TxBE
(which corresponds to the start of transmission of the last character), When CRC is
required, TxE must be dropped before CRC transmission is complete. Otherwise, the
contents of TxDB will be shifted out on TxSO. This facilitates transmission of contiguous messages.
TRANSMIT UNDER RUN
TXU!.-J
____________~~SETTSOM
DBEN:..
IL-
NOTES
8. TxU goes active relative to TxC falling edge if TxBE has not been serviced after n-1/2
TxC times (where n transmit character length). TxU is reset on the TxC falling edge
following assertion of the TSOM command.
9. An underrun will occur at the next character boundary if TEOM is reset and the
transmitter remains enabled, unless the TSOM command is asserted or a character is
loaded into the TxDB.
=
Signetics
1-29
MICROPROCESSOR DIVISION
JANUARY 1983
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
SCN2652/SCN68652
TIMING DIAGRAMS (Cont'dl
RECEIVE-START OF MESSAGE
RxA
1st CHAR READY
TO BE READ
-rf-----.,
2nd CHAR READY
TO BE READ
-r----.,
DB EN
SlF"
RxE
,--,
--~I
I~
____________________________
~
_____
J
NOTES
9. RxA goes high relative to falling edge of Rxe when RxE is high and:
a. A data character following two SYNC's is in RxDB (BCP model
b. Character following FLAG is in AxDS (BOP primary station model
c. Character following FLAG is in RxDB and character matches the secondary
station address or Art Parties Address (BOP secondary station mode).
10. RxDA goes high on Axe falling edge when a character in RxDB is ready to be read. It
comes up before RxSA and goes low on'the falling edge of DBEN when RxDB is read.
11. S/F goes high relative to rising edge of Axe anytime a SYNC (BCP) or FLAG (BOP) is
detected.
RECEIVE END OF MESSAGE
RxC
RxDA
--.........It.....
DBEN
(S-BIT) - - - - - - - - - '
SlF
~~
RxE'3
RxAt4
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ _
1---------------------------------
1------------,
NOTES
12. At the end of a BOP message, RxSA goes high when FLAG detection (S/F= 1) forces
REOM to be set. Processor should read the last data character (ROSRL) and status
(ROSRH) which resets RxOA and RxSA respectively. For BCP end of message, RxSA
may not be set and SI F = O. The processor should read the last data character and
status.
13. RxE must be dropped forBCPwith non-contiguous messages. It may be left on at the
end of a BOP message (see BOP Receive Operationl.
14. RxA is reset relative to the falling edge of Rxe after the closing FLAG of a BOP
message IREOM = 1 and RxSA active;) or when AxE is dropped.
1·30
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
SCN2652/SCN68652
TYPICAL APPLICATIONS
1
2652 MPCC MICROPROCESSOR INTERFACE
I
RESET
rl
1jL-_....,,......_--,
TS BUFFER
~-"~
L...::::JI'OR
I_-T:..:X:.:C'-----B--I
LR
STATUS
DATA BUS
RxC
DBO~
-"7R'I-
1----'---1L:;,J
LR
DB7
8·BIT
,"P
SYNCHRO·
NOUS
MODEM
MPCC
SCN2652
CONTROL
ADDRESS
A2-AO, iilw DBEN CE
t.?
I-_Tc.:X.:.SO"--I-§}---
._-
RxSI
~
II
RxE
MODEM
CONTROL
LOGIC
~
LR
1-----Il:::J
TxE
..
IRTS' CTS,
DTR,DSR,
DCD
1~______-4~D~C~D__~C_T_S________________~
NOTES
1. Possible ~p interrupt requests are:
RxDA, RxSA, TxBE, TxU.
2. Other 2652 status signals and possible uses are:
S/F line: idle indicator, frame delimiter.
RxA handshake on AxE, line turn around control
TxA handshake on TxE, line turn around control.
3. Une Drivers/Receivers (LD/lR) convert EIA to TTL voltages and vice-versa
4. RTS should be dropped after the CRC (BCP) or FLAG (BOP) has been transmitted.
This forces eTS low and TxE low.
5. Corresponding high and low order bits of DB must be OR tied.
DMA/PROCESSOR INTERFACE
DATA BUS
~
l
WORD COUNT
I
I
RIW CONTROL
ADDRESS PTR
I
I
I
8 OR 16 BITS
RxDA
DATA BUS
RxA
RxE
RxSA
TxA
TxBE
TxE
SCN2652
DMA
CONTROLLER
TxU
SIF
A2-AO
SCN2652
ADDRESS AND
CONTROL
}
DATA BUS
DB15-DBOO
TO PROfESSOR
WRREQ
s
a
RDREQ
BYTE
iilw
RESET
PROCESSOR (P)
AND
SUPPORT LOGIC:
1. INITIALIZES
SCN2652
2. SETSIRESETS
TSOM, TEOM
3. RESPONDS
TO RxSA
I-- RxDA
I--TXBE
iilW
MEMORY
MM
CE
DBEN
_ ADDRESS,
RIW CONTROLS
t>
RxC
t
TxC
RxSI TxSO
ADDRESS, iilW,
CONTROL
ADDRESS,
CE, RIW
I I1
MODEM OR DCE
SYSTEM ADDRESS AND CONTROL BUS
For non-DMA operation, TxBE and RxDA are sent to the processor which then loads or
reads data characters as required.
Signetics
1·31
MICROPROCESSOR DIVISION
JANUARY 1983
MULTI-PROTOCOL COMMUNICATIONS CONTROLLER
SCN2652/SCN68652
TYPICAL APPLICATIONS (Cont'd)
CHANNEL INTERFACE
COMPUTER
OR
TERMINAL
MPCC
SCN2652
MPCC
SCN2652
RxSI
TxSO
No Modem-DC Baseband Transmission
265212653 INTERFACE
TYPICAL PROTOCOLS: BISYNC, DDCMP, SDLC, HDLC
INTERRUPTS
U
TxBE TxU RxDA Rx5A
II
DB7-DBO
MPCC
SCN2652
A2
A1
AO
_TxC
ii/w
CPU
_ _ TxD
-RxD
_RxC
DBEN
CE
DB7-DBO
.Q,
....y
CEO
PGC
SCN2653
A1
ii/w
AO
CE1
f
t
iNT
I
(OPEN DRAIN)
5V
1·32
Signetics
COMPUTER
OR
TERMINAL
MICROPROCESSOR DIVISION
JANUARY 1983
POLYNOMIAL GENERATOR CHECKER (PGC)
DESCRIPTION
The Signetics SCN2653/68653 Polynomial
Generator Checker (PGC) is a polynomial
generator checker/character comparator
circuit that complements a receiver/transmitter (R/T or USART/USRT/UART) in the
support of character oriented data link controls. Table 1 defines many of the more
commonly used PGC terms and abbrevi·
ations.
Parallel data characters transferred between the CPU and R /T are monitored by
the PGC which performs block check character (BCC) and parity (VRC) generation/checking, single character detection,
and two character sequence detection.
Since the PGC operates on parallel characters, the data transmission format may be
serial (synchronous or asynchronous) or
parallel.
There are four modes of BCC accumUlation
and each mode can select one of three poly·
nomials to compute the BCC. In the BISYNC
normal and transparent modes, the PGC determines which characters are to be accumulated and which characters are to be excluded from the accumulation. The block
terminating characters and the initiation and
terminetion of BISYNC transparent text can
be detected and an interrupt generated. The
single interrupt output represents the inclusive OR of four maskable status conditions.
In the automatic accumulation mode, all
characters are accumulated while the single
accumulate mode requires a specific accumulation command for each character to be
accumulated.
Character accumulation control and character comparisons are facilitated by a character class array which places each of 128
characters into one of four character
classes. The four classes are normal,
SYN/BISYNC not included, block terminating character (BTC)/search character (SC),
and secondary search character (SSC).
Additional PGC applications include off-line
R/T operation where the BCC is generated
on data not sent to the R/T, BCC mUltiplexing by sharing the PGC among several R/Ts
and reading/writing the partial BCC accumulation on a character by character basis,
VRC generation / checking on characters
appearing on a bidirectional data bus, and
programmable character comparisons or
SCN2661 Enhanced Programmable Commu·
nications Interface (EPCI). When used in
BISYNC modes with the SCN2661, software
requirements are minimized by the SCN2653SCN2661 control character comparisons,
character sequence comparisons, and auto·
matic OLE insertion/detection.
SCN2653/SCN68653
PIN CONFIGURATION
1
CEO
eEl
R/W
Other bus oriented R/Ts can be interfaced
to the PGC with a minimum of external circuitry. See figure 1 for a typical system configuration.
AO
This NMOS LSI circuit is TTL compatible.
operates from a single + 5V supply and is
contained in a 16 pin dual in line package.
TOP VIEW
FEATURES
• Parallel Block Check Character
accumulation / checking: CRC-16,
CRC-12, LRC-8
• BISYNC normal and transparent modes
• Automatic or single character accumulation modes
• Character detection - up to 128 characters
• Two character sequence detection; examples: DLE-STX, ACK 0, ACK 1,
WACK, RVI, DISC, WBT
• 6, 7, or 8-bit characters
• VRC generation/checking on data bus
• Four maskable interrupt conditions
• Four classes of characters
• Internal power-on reset
• Maximum character accumulation rate
of 500 kHz (4 Mbps)
• Directly compatible with Signetics
SCN2651, SCN2652 and SCN2661
• No system clock required
• TTL compatible inputs and outputs
• Single 5V supply
• 16-pln dual In line package
APPLICATIONS
• Character oriented data link control:
-dedicated to one USART /USRT
-multiplexed
among
several
USART /USRTs
• Automated BISYNC with 2661 (minimal
software intervention)
• BCC and VRC generation/detection on
a block of memory or peripheral data
• Programmable character array comparator
BLOCK DIAGRAM
The PGC consists of six major sections.
These are the operation control, character
class array, OLE ROM, character register,
BCC and parity generators, and BCC registers. These sections communicate with
each other via an internal data bus and an
internal control bus. The internal data bus
interfaces to the CPU data bus via a data
bus buffer.
ORDERING CODE
PACKAGES
COMMERCIAL RANGES
Vcc=5V ±5%, TA=O·Cto +70·C
Ceramic DIP
SCN2653AC4116
Plastic DIP
SCN2653AC4N16
NOTE:
SCN68653 Is Identical to SCN2653. Order using part numbers shown above.
searches.
PGC operation is half duplex (either receive or
transmit, one way or two way alternate). Full
duplex (two way simultaneous) is achieved by
using two PGCs. The device is directly compatible with the Signetics SCN2651 Programmable Communications Interface (PCI) and
Signetics
1·33
MICROPROCESSOR DIVISION
JANUARY 1983
POLYNOMIAL GENERATOR CHECKER. (PGC)
SCN2653/SCN68653
BLOCK DIAGRAM
DO-D7
<-
~
L
DATA BUS
DATA BUS
BUFFER
I
I
~
r--
DLE
.
R
AU
f=-z
...
-~
MODE REGISTER
•
1
r-
COMMAND REGISTER
1
n
0
STATUS REGISTER
z
iI0
.
0
CHARACTER CLASS
ARRAY
@
DETECT
OPERATION CONTROL
...rnZ
c
s
w
Q
"
W
I
-rl
CE1
PGC
l-
INT
ONE PGC IS TIME·SHARED BY THREE RITa.
THE CPU READS AND RESTORES THE PARTIAL BCC
REMAINDER FOR EACH SERIAL CHANNEL.
Figure 10. PGC Services Multiple Receivers/Transmitters
1·46
Signetics
~EC/XMT
r=
:
TxD
_RxD
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2653/SCN68653
POLYNOMIAL GENERATOR CHECKER (PGC)
1
Tx HOLDING REGISTER AVAILABLE
RE~~~~'II~~~:J~~i~~~CC
CHANNEL POINTER.
READ MODE REGISTER AND
STORE IN SAVE AREA.
CHANNELl
BCC AND
MODE DATA
BCC.1 AND
MODE R~(lISTER
YES
Figure 11. Multiplexed PGC - Transmit to R/T
Rx HOLDING REGISTER READY
NO
READ BCC. 1 AND STORE IN BCC
SAVE AREA SPECIFIED BY
CHANNEL POINTER. READ
MODE REGISTER AND STORE IN
SAVE AREA.
YES
Figure 12. Multiplexed PGC -
5ignetics
Receiver from R/T
1·47
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2653/SCN68653
POLYNOMIAL GENERATOR CHECKER (PGC)
INT
1
I
AO,A1,illw
CEI
poc
1-
r--
H
I-
PERIPHERAL
DEVICE
CPU
DATA BUS
8/
/
H
-
I
~
SLAVE
CPU
lilW
I-
MEMORY
MA,MC
APPLICATIONS I NCLUDE CHARACTER ARRAY
COMPARISIONS, VRC AND/OR BCC CHECKS
ON THE DATA B US.
-
NOTE
• CPU Initiallz•• DMA controller for .ach block trenef.' of
chit••
,~
'!:EO.
DMA'
CONTROLLER
I
Figure 13. PGC Data Bus Monitoring with DMA Transfers
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Operating ambient temperature2
Storage temperature
All voltages with respect to ground3
RATING
UNIT
Oto +70
·65 to +150
·0.5 to +6.0
·C
·C
NOTES
1. Str••a8a above thoa.lilted under "Absolute Maximum Rating." may cause permanent
damage to the device. This is a stre88 rating only and functional operation of the device
at the•• or al any other condition above tho•• indicated In the operation sections of
this specification Is not implied.
2. For operating at elevated temperatures the device must be derated based on
+150°C
maximum Junction tamperatur•.
3. This product include. circuitry specifically designed for the protection of its internal
device. from the damaging effecta of excessive static charge. However. It is suggested that conventional precautions be taken to avoid applying any voltages larger than
the rated maxima.
1·48
Signetics
V
JANUARY 1983
MICROPROCESSOR DIVISION
POLYNOMIAL GENERATOR CHECKER (PGC)
SCN2653/SCN68653
DC ELECTRICAL CHARACTERISTICS TA = o·C to 70·C, vcc = 5.0V ± 5%
LIMITS
TEST CONDITIONS
PARAMETER
Typ
Max
UNIT
V
VIL
VIH
Input voltage
Low
High
VOL
VOH
Output voltage
Low
High
IOL = 2.2mA
IOH = -400/LA
IlL
Input load current
VIN
ILO
ILO
Output leakage current
Data bus
Open drain
ICC
Power supply current
AC CHARACTERISTICS TA =
Min
0.8
2.0
V
a· to +70·C, VCC =
2.4
0.25
2.8
= a to 5.5V
0.45
10
/LA
/LA
= 4.0V
= 4.0V
VOUT
VOUT
10
10
45
75
mA
5V ± 5%',2,3
LIMITS
PARAMETER
Min
Max
UNIT
tCE
Chip enable pulse width
250
ns
tCEO
Chip enable period 0
1750
ns
tCEC 4
Chip enable period C
1750
ns
tAS
Address setup
10
ns
tAH
Address hold
10
ns
tcs
Control setup
10
ns
tCH
Control hold
10
ns
tOS5
Data setup
150
ns
tOH
Data hold
10
ns
tOOB
Data delay time for read
200
ns
tOF 6
Data bus floating time for read
100
ns
tlNTL7
Interrupt low delay
1600
ns
tlNTH7
Interrupt high delay
600
ns
NOTES
1. Parameters are valid over operating temperature range unless otherwise specified.
2. All voltage measurements are referenced to ground. All lime measurements are at 50%
level for inputs and at the O.SV or 2.0V level for outputs. Input levels for testing are
O.45V and 2.4V.
3. Typical values are at +25°C. typical supply voltages and typical processing param-
eters.
4.
5.
6.
7.
=
=
IeEe eOOns during PGC Initialization when no Bee accumulation is in progress.
lOS SOns whenever CEO Is used.
Test conditions: CL = 150 pF.
INT is an open drain output.
5ignetics
1·49
1
JANUARY 1983
MICROPROCESSOR DIVISION
POLYNOMIAL GENERATOR CHECKER (PGC)
SCN2653/SCN68653
ICE---i+--------ICED----------i
AO,A1
iilw
DO-D7
(WRITE)
DO-D7
,(READ)
BUS FLOATING
I-----IINTL----~'-----------+-'l
IINTH
Figure 14. PGC Timing
1·50
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
SCN2661 168661
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
DESCRIPTION
The Signetics SCN2661 EPCI is a universal
synchronous/asynchronous data communications controller chip that is an
enhanced version of the SCN2651. It interfaces easily to all 8-bit and 16-bit microprocessors and may be used in a polled or
interrupt driven system environment. The
SCN2661 accepts programmed instructions from the microprocessor while supporting many serial data communications
disciplines- synchronous and asynchronous-in the full or half-duplex mode.
Special support for BISYNC is provided.
The EPCI serializes parallel data characters received from the microprocessor for
transmission. Simultaneously, it can
receive serial data and convert it into
parallel data characters for input to the
microcomputer.
The SCN2661 contains a baud rate generator which can be programmed to either
accept an external clock or to generate internal transmit or receive clocks. Sixteen
different baud rates can be selected under
program control when operating in the internal clock mode. Each version of the
EPCI (A, B, C) has a different set of baud
rates.
The EPCI is available in two packages: a
28-pin (0.6" wide) DI P and a 24-pin (0.4"
wide) DIP. The following are the differences between the 24-pin and the 28-pin
versions:
1. The 24-pin version provides a single interrupt output (INTR) instead of the
three interrupt outputs (RxRDY, TxRDY,
TxEMT/DSCHG) supplied on the 28-pin
version. INTR will be asserted (low)
when one or more of the status bits
SRO, SRl or SR2 is a logic one.
2. Two modem interface pins, the DTR
output and the DSR input, are eliminated in the 24-pin version. Because of
this, status bit SR7 should be ignored
and the setting of status bit SR2 due to
a data set change (DSCHG) can be
caused only by a change of the DCD in·
put. Since the DTR' output is eliminated, command register bit CRl does
not perform any function, although it
remains writable and readable.
Other than the above, the functional operation, DC electrical characteristics, and
AC electrical characteristics of the 24-pin
version are identical to the 28-pin version.
FEATURES
• Synchronous operation
5 to 8-bit characters plus parity
Single or double SYN operation
Internal or external character
synchronization
Transparent or non·transparent mode
Transparent mode OLE stuffing (Tx)
and detection (Rx)
Automatic SYN or DLE-SYN insertion
SYN, OLE and DLE·SYN stripping
,Odd, even, or no parity
Local or remote maintenance loop back
mode
Baud rate: dc to 1M bps (1X clock)
• Asynchronous operation
5 to 8-blt characters plus parity
" 1 % or 2 stop bits transmitted
Odd, even, or no parity
Parity, overrun and framing error
detection
Line break detection and generation
False start bit detection
Automatic serial echo mode (echoplex,)
Local or remote maintenance loop back
mode
Baud rate: dc to 1M bps (1X clock)
dc to 62.5K bps (16X clock)
dc to 15.625K bps (64X clock)
PIN CONFIGURATIONS
1
D1
DO
vcc
RxC/BKDET
DTR
RTS
DSR
BRCLK
TxD
A1
f'i'E'M'f1'i5"S'C'i1G
CTS
R/W
DCD
ifiRDV
TxROY
TOP VIEW
28·PIN
OTHER FEATURES
•
•
•
•
•
•
•
•
•
•
Internal or external baud rate clock
3 baud rate sets
16 internal rates for each set
Double buffered transmitter and
receiver
Dynamic character length switching
Full or half duplex operation
TTL compatible inputs and outputs
RxC and TxC pins are short circuit protected
Single 5V power SUpply
No system clock required
D2
D1
DO
vcc
Rxc/BKDET
m
RESET
BRCLK
APPLICATIONS
•
•
•
•
•
•
•
TxD
Intelligent terminals
Network processors
Front 'end processors
Remote data concentrators
Computer to computer links
Serial peripherals
BISYNC adaptors
CE
Cf!i
AO
DCD
R/w
INTR
TOP VIEW
24-PIN
ORDERING CODE
Vcc= 5V:!: 5%
COMMERCIAL
AUTOMOTIVE
MILITARY
PACKAGES
O·C 10 +70·C
- 40·C 10 + 85·C
- 55·C to +125·C
Ceramic DIP
28·Pin
0.6" Wide
SCN2661 ACl128
SCN2661 BCl128
SCN2661 CCl128
SCN2661AAl128
SCN2661BAl128
SCN2661 CA 1128
SCN2661AMl128
SCN2661 BMl128
SCN2661CMl128
Plastic DIP
28·Pin
0.6" Wide
SCN2661AC1N28
SCN2661 BCl N28
SCN2661CC1N28
Contact Factory
Not Available
Plastic DIP
24-Pin
0.4" Wide
SCN2661ACl N24
SCN2661 BCl N24
SCN2661 CCl N24
Contact Factory
Not Available
NOTES
1. See table 1 for baud rates. Specify SCN2661A, B, or C depending on baud rate selected.
2. The SCN68661 Is identical to the SCN2661. Order using part numbers above.
Signetics
1·51
MICROPROCESSOR DIVISION
JANUARY 1983
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
SCN2661 168661
BLOCK DIAGRAM
DATA BUS
DO-D7
)
DATA BUS
BUFFER
SNE/DLE CDNTROL
SYN I REGISTER
t
SYN 2 REGISTER
DLE REGISTER
•
RESET
•
AO
•
•
•
AI
RIW
BE
•
BRCLK
TxClSYNC
RxCIBKDET
DSR
•
.
+
MODE REGISTER I
MODE REGISTER 2
COMMAND REGISTER
BAUD RATE
GENERATOR
AND
CLOCK CONTROL
•
•
CTS
RTS
MODEM
CONTROL
+
TxEMT/*
K=
r--
-
STATUS REGISTER
•
•
DCD
DTR
•
OPERATION CONTROL
1- -
--- I
)
I
-
r--
~
--- I
l
TxRDY'
TRANSMITTER
TRANSMIT DATA
HOLDING REGiSTER
TRANSMIT
SHIFT REGISTER
•
I
I
TxD
t
RxRDY"
RECEIVER
RECEIVE DATA
HOLDING REGISTER
RECEIVE
SHIFT REGISTER
I
J
--
TXRDY~
RxRDY.
TxEMT
DSCHG
+
DSCHO
+
+
RxD
IN
NOTE
* Open drain output pin.
+ 28-pin only
++ 24-pin only
BLOCK DIAGRAM
The EPCI consists of six major sections.
These are the transmitter, receiver, timing,
operation control, modem control and
SYN IDLE control. These sections communicate with each other via an internal data bus
and an internal control bus. The internal data
bus interfaces to the microprocessor data
bus via a data bus buffer.
Operation Control
This functional block stores configuration
and operation commands from the CPU and
generates appropriate signals to various internal sections to control the overall device
operation. It contains read and write circuits
to permit communications with the
microprocessor via the data bus and contains mode registers 1 and 2, the command
register, and the status register. Details of
register addressing and protocol are presented in the EPCI programming section of
this data sheet.
1·52
Table 1 BAUD RATE GENERATOR CHARACTERISTICS
SCN2661A (BRCLK = 4.9152MHz)
MR23-20
BAUD
RATE
ACTUAL
FREQUENCY
16X CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1.110
1111
50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200
0.8kHz
1.2
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
Signetics
PERCENT
ERROR
-0.01
-
-
-
0.196
-0.19
-0.26
-
-
DIVISOR
6144
4096
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16
MICROPROCESSOR DIVISION
JANUARY 1983
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
Timing
The EPCI contains a baud rate generator
(BRG) which is programmable to accept external transmit or receive clocks or to divide
an external clock to perform data communications_ The unit can generate 16 commonly
used baud ratas. anyone of which can be
selected for full duplex operation_ See
table 1.
Receiver
The receiver accepts serial data on the RxD
pin. converts this serial input to parallel format. checks for bits or characters that are
unique to the communication technique and
sends an "assembled" character to the
CPU.
Transmitter
The transmitter accepts parallel data from
the CPU. converts it to a serial bit stream.
inserts the appropriate characters or bits
(based on the communication technique)
and outputs a composite serial stream of
data on the TxD output pin.
Table 1 BAUD RATE GENERATOR CHARACTERISTICS
SCN2661 B (BRCLK 4.9152MHz)
=
MR23-20
BAUD
RATE
ACTUAL
FREQUENCY
16XCLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
45.5
50
75
110
134.5
150
300
600
1200
1800
2000
2400
4800
9600
19200
38400
0.7279kHz
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4
SCN2661C (BRCLK
Modem Control
The modem control section provides interfacing for three input signals and three output signals used for "handshaking" and status indication between the CPU and a
modem.
SYN/DLE Control
This section contains control circuitry and
three 8-bit registers storing the SYN 1.
SYN2. and OLE characters providad by the
CPU. These registers are used in the synchronous mode of operation to provide the
characters required for synchronization. idle
fill and data transparency.
SCN2661 168661
MR23-20
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
PERCENT
ERROR
0.005
(Conl'd)
1
DIVISOR
-
6752
6144
4096
2793
2284
2048
1024
512
256
171
154
128
64
32
16
8
PERCENT
ERROR
DIVISOR
-0.01
-0.19
-0.26
=5.0688MHz)
BAUD
RATE
ACTUAL
FREQUENCY
16X CLOCK
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
0.8kHz
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
318-8
0.016
0.253
3.125
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
NOTE
l6X clock is used in asynchronous mode. In synchronous mode, cJock multiplier is 'X and
BRG can be used only for TxC.
Signetics
1·53
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2661 168661
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
Table 2
PIN NAME
RESET
OPERATION
CPU-RELATED SIGNALS
INPUT/
24·
PIN
28·
PIN
OUTPUT
FUNCTION
X
X
I
A high on this input performs a master
reset on the 2661. This signal asynchro·
nously terminates any device activity and
clears the mode, command and status reg·
isters. The device assumes the idle state
and remains there until initialized with the
appropriate control words.
Al- AO
X
X
I
Address lines used to select internal EPCI
registers.
R/W
X
X
I
CE
X
X
I
Read command when low, write command
when high.
Chip enable command. When low, indicates that control and data lines to the
EPCI are valid and that the operation
specified by the R/W, A1 and AO inputs
should be performed. When high, places
the 00-07 lines in the three-state condition.
8-bit, three-state data bus used to transfer
commands, data and status between EPCI
and the CPU. 00 is the least significant bit;
07 the most significant bit.
X
1/0
TxROY
X
0
This output is the complement of status
register bit SRO. When low, it indicates
that the transmit data holding register
(THR) is ready to accept a data character
from the CPU. It goes high when the data
character is loaded. This output is valid
only when the transmitter is enabled. It is
an open drain output which can be used as
an interrupt to the CPU.
RxROY
X
0
This output is the complement of status
register bit SR 1. When low, it indicates
that the receive data holding register
(RHR) has a character ready for input to
the CPU. It goes high when the RHR is read
by the CPU, and also when the receiver is
disabled. It is an open drain output which
can be used as an interrupt to the CPU.
X
0
This output is the complement of status
register bit SR2. When low, it indicates
that the transmitter has completed serialization of the last character loaded by the
CPU, or that a change of state of the OSR
or OCO inputs has occurred. This output
goes high when the status register is read
by the CPU, if the TxEMT condition does
not exist. Otherwise, the THR must be
loaded by the CPU forthis line to go high. It
is an open drain output which can be used
as an interrupt to the CPU.
0
This is an active low output which is the
wire·OR of the TxROY, RxROY, and TxEMTI
OSCHG outputs on the 28-pin version. See
above.
07- 0 0
X
TxEMTI
OSCHG
INTR
1·54
X
Signetics
The functional operation of the 2661 is pro·
grammed by a set of control words supplied
by the CPU. These control words specify
Items such as synchronous or asynchronous
mode, baud rate, number of. bits per charac·
ter, etc. The programming procedure is described in the EPCI programming section of
the data sheet.
After programming, the EPCI is ready to perform the desired communications functions.
The receiver performs serial to parallel conversion of data received from a modem or
equivalent device. The transmitter converts
perallel data received from the CPU to a
serial bit stream. These actions are accom·
plished within the framework specified by
the control words.
Receiver
The 2661 is conditioned to receive data
when the OCO input is low and the RxEN bit
in the command register is true. In the asynchronous mode, the receiver looks for a high
to low (mark to space) transition of the start
bit on the RxO input line. If a transition is
detected, the state of the RxO line is sampled again after a delay of one· half of a bit
time. If RxO is now high, the search for a
valid start bit is begun again. If RxO is still
low, a valid start bit is assumed and the
receiver continues to sample the input line
at one bit time intervals until the proper num·
ber of data bits, the parity bit, and one stop
bit have been assembled. The data are then
transferred to the receive data holding register, the RxROY bit in the status register is
set, and the RxROY output is asserted. If the
character length is less than 8 bits, the high
order unused bitl! in the holding register are
set to zero. The parity error, framing error,
and overrun error status bits are strobed
into the status register on the positive gOing
edge of RxC corresponding to the received
character boundary. If the stop bit is
present, the receiver will immediately begin
its search for the next start bit. If the stop bit
is. absent (framing error), the receiver will
interpret a space as a start bit if it persists
into the next bit time interval. If a break con·
dition is detected (RxO is low for the entire
character as well as the stop bit), only one
character consisting of all zeros (with the
FE status bit SR5 set) will be transferred to
the holding register. The RxO input must reo
turn to a high condition before a search for
the next start bit begins.
Pin 25 can be programmed to be a break
detect output by appropriate selting of
MR27-MR24. If so, a detected break will
cause that pin to go high. When RxO returns
to mark for one RxC time, pin 25 will go low.
Refer to the break detection timing diagram.
JANUARY 1983
MICROPROCESSOR DIVISION
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
Table 3
DEVICE-RELATED SIGNALS
24·
PIN
BRCLK
x
x
RxC/BKDET
x
x
1/0
Receiver clock. If external receiver clock
is programmed, this input controls the rate
at which the character is to be received.
Its frequency is 1X, 16X or 64X the baud
rate, as programmed by mode register 1.
Data are sampled on the rising edge of the
clock. If internal receiver clock is pro·
grammed, this pin can be a lXI 16X clock
or a break detect output pin.
TxC/XSYNC
x
x
1/0
Transmitter clock. If external transmitter
clock is programmed, this input controls
the rate at which the character is transmit·
ted. Its frequency is 1X, 16X or 64X the
baud rate, as programmed by mode regis·
ter 1. The transmitted data changes on the
falling edge of the clock. If internal trans·
mitter clock is programmed, this pin can
be a 1X I 16X clock output or an external
jam synchronization input.
RxD
x
x
TxD
x
x
OUTPUT
FUNCTION
Clock input to the internal baud rate gener·
ator (see table 1). Not required if external
receiver and transmitter clocks are used.
Serial data input to the receiver. "Mark" is
high, "space" is low.
o
Serial data output from the transmitter.
"Mark" is high, "space" is low. Held in
mark condition when the transmitter is dis·
abled.
x
General purpose input which can be used
for data set ready or ring indicator condi·
tion. Its complement appears as status
register bit SR7. Causes a low output on
TxEMT I DSCHG when its state changes if
CR2 or CRO = 1.
x
x
Data carrier detect input. Must be low in
order for the receiver to operate. Its com·
plement appears as status register bit
SR6. Causes a low output on
TxEMT I DSCHG when its state changes if
CR2 or CRO = 1. If DCD goes high while
receiving, the RxC is internally inhibited.
x
x
Clear to send input. Must be low in order
for the transmitter to operate. If it goes
high during transmission, the character in
the transmit shift register will be transmit·
ted before termination.
x
1
When the EPCI is initialized into the synchro· ~~~~~
nous mode, the receiver first enters the hunt
mode on a to 1 transition of RxEN(CR2). In
this mode, as data are shifted into the reo ~~~~~
ceiver shift register a bit at a time, the con·
tents of the register are compared to the
contents of the SYN 1 register. If the two are
not equal, the next bit is shifted in and the
comparison is repeated. When the two reg·
isters match, the hunt mode is terminated
and character assembly mode begins. If sin·
gle SYN operation is programmed, the SYN
DETECT status bit is set. If double SYN op·
eration is programmed, the first character
assembled after SYN 1 must be SYN2 in or·
der for the SYN DETECT bit to be set. Other·
wise, the EPGI returns to the hunt mode.
(Note that the sequence SYN I·SYN I·SYN2
will not achieve synchronization.) When syn·
chronization has been achieved, the EPCI
continues to assemble characters and
transfer them to the holding register, setting
the RxRDY status bit and asserting the
RxRDY output each time a character is
transferred. The PE and OE status bits are
set as appropriate. Further receipt of the
appropriate SYN sequence sets the SYN
DETECT status bit. If the SYN stripping
mode is commanded, SYN characters are
not transferred to the holding register. Note
that the SYN characters used to establish
initial synchronization are not transferred to
the holding register in any case.
a
INPUT/
28·
PIN
PIN NAME
SCN2661 168661
x
o
General purpose output which is the com·
plement of command register bit CR 1. Nor·
mally used to indicate data terminal ready.
x
o
General purpose output which is the com·
plement of command register bit CR5. Nor·
mally used to indicate request to send. If
the transmit shift register is not empty
when CR5 is reset (1 to 0), then RTS will
go high one TxC time after the last serial
bit is transmitted.
Signetics
External jam synchronization can be
achieved via pin 9 by appropriate setting of
MR27·MR24. When pin 9 is an XSYNC input,
the internal SYN1, SYN1·SYN2, and DLE·
SYN 1 detection is disabled. Each positive
going signal on XSYNC will cause the reo
ceiver to establish synchronization on the
rising edge of the next RxC pulse. Character
assembly will start with the RxD input at this
edge. XSYNC may be lowered on the next
rising edge of RxC. This external synchroni·
zation will cause the SYN DETECT status bit
to be set until the status register is read.
Refer to XSYNC timing diagram.
Transmitter
The EPCI is conditioned to transmit data
when the CTS input is low and the TxEN
command register bit is set. The 2661 indio
cates to the CPU that it can accept a char·
acter for transmission by setting the TxRDY
status bit and asserting the TxRDY output.
When the CPU writes a character into the
transmit data holding register, these condi·
tions are negated. Data are transferred from
the holding register to the transmit shift reg·
ister when it is idle or has completed trans·
mission of the previous character. The
TxRDY conditions are then asserted again.
Thus, one full character. time of buffering is
provided.
1-55
MICROPROCESSOR DIVISION
JANUARY 1983
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
In the asynchronous mode, the transmitter
automatically sends a start bit followed by
the programmed numbar of data bits, the
least significant bit being sent first. It then
appends an optional odd or even parity bit
and the programmed number of stop bits. II,
following transmission of the data bits, a
new character is not available in the, trans·
mit holding register, the TxO output remains
in the marking (high) condition and the
TxEMT I OSCHG output and its correspond·
ing status bit are asserted. Transmission
resumes when the CPU loads a new charac·
ter into the holding register. The transmitter
can be forced to output a continuous low
(BREAK) condition by selting the send
break command bit (CR3) high.
Table 4
2661 REGISTER ADDRESSING
CE
A1
AO
R/W
1
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
SCN2661 168661
FUNCTION
Three-state data bus
Read receive holding register
Write transmit holding register
Read status register
Write SYN 11 SYN21 OLE registers
Read mode registers %
Write mode registers %
Read command register
Write command register
NOTE
See AC characteristics section for timing requirements.
INITIAL RESET
In the synchronous mode, when the 2661 is
initially conditioned to transmit, the TxO out·
put remains high and the TxROY condition is
asserted until the first character to be trans·
mitted (usually a SYN character) is loaded
by 'the CPU. Subsequent to this, a continuous stream of characters is transmitted. No
extra bits (other than parity, if commanded)
are generated by the EPCI unless the CPU
fails to send a new character to the EPCI by
the time the transmitter has completed
sending the previous character. Since synchronous communication does not allow
gaps between characters, the EPCI asserts
TxEMT and automatically "fills" the gap by
transmitting SYNls, SYNI-SYN2 doublets,
or OLE-SYN 1 doublets, depending on the
state of MR 16 and MR 17. Normal transmission of the message resumes when a new
character is available in the transmit data
holding register. II the SEND OLE bit in the
command register is true, the OLE character
is automatically transmitted prior to transmission of the message character in the
THR.
NOTE
Mode register 1 must be written before
2 can be written. Mode register 2 need
not be programmed if external clocks
are used.
EPCI PROGRAMMING
Prior to initiating data communications, the
2661 operational mode must be programmed by performing write operations to
the mode and command registers. Inaddition, if synchronous operation is programmed, the appropriate SYN/OLE registers must be loaded. The EPCI can be
reconfigured at any time during program execution. A flowchart of the intialization process appears in figure 1.
The internal registers of the EPCI are
accessed by epplying specific signals to the
CE, Filw, A 1 and AO inputs. The conditions
necessary to sddress each register are
shown In table 4.
The SYN1, SYN2, and OLE registers are
accessed by performing write operations
with the conditions Al = 0, AO = I, and
1·56
Figure 1. 2661 Inltlslization Flow Chart
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
R/ W
= 1. The first operation loads the
SYN 1 register. The next loads the SYN2
register, and the third loads the OLE register. Reading or loading the mode registers is
done in a similar manner. The first write (or
read) operation addresses mode register "
and a subsequent operation addresses
mode register 2. If more than the required
number of accesses are made, the internal
sequencer recycles to point at the first register. The pointers are reset to SYN 1 register and mode register 1 by a RESET input or
by performing a read command register operation, but are unaffected by any other read
or write operation.
The 2661 register formats are summarized
in tables 5, 6, 7 and 8. Mode registers 1 and
2 define the general operational characteristics of the EPCI, while the command register controls the operation within this basic
framework. The EPCI indicates its status in
the status register. These registers are
cleared when a RESET input is applied.
Mode Register 1 (MR1)
Table 5 illustrates Mode Register 1. Bits
MR 11 and MR 10 select the communication
format and baud rate multiplier. 00 specifies
synchronous mode and 1X multiplier. 1X,
16X, and 64X multipliers are programmable
for asynchronous format. However, the multiplier in asynchronous format applies only if
the external clock input option is selected
by MR24 or MR25.
MR13 and MR12 select a character length of
5, 6, 7 or 8 bits. The character length does not
include the parity bit, jf programmed, and
does not include the start and stop bits in
asynchronous mode.
MR 14 controls parity generation. If enabled,
a parity bit is added to the transmitted char-
Table 5
SCN2661 168661
1
To effect 88sembly I disassembly of the next ~~F~.
received/transmitted character, MR12-15
must be changed within n bit times of the
active going state of RxRDY /TxROY. Trans- ~~~~
parent and non-transparent mode changes
(MR 16) must occur within n-l bit times of the
character to be allected when the receiver
or transmitter is active. (n = smaller of the
new and old character lengths.)
acter and the receiver performs a parity
check on incoming data. MR 15 selects odd
or even parity when parity is enabled by
MR14.
In asynchronous mode, MR17 and MR16 select character framing of " 1.5, or 2 stop
bits. (If 1X baud rate is programmed, 1.5
stop bits defaults to 1 stop bits on transmit.)
In synchronous mode, MR 17 controls the
number of SYN characters used to establish
synchronization and for character fill when
the transmitter is idle. SYN 1 alone is used if
MR17 = 1, and SYNI-SYN2 is used when
MR 17 = O. If the transparent mode is specified by MR 16, DLE-SYN 1 is used for character fill and SYN detect, but the normal synchronization sequence is used to establish
character sync. When transmitting, a OLE
character in the transmit holding register will
cause a second OLE character to be transmitted. This OLE stuffing eliminates the software OLE compare and stuff on each transparent mode data character. If the send OLE
command (CR3) is active when a OLE is
loaded into THR, only one additional OLE will
be transmitted. Also, OLE stripping and OLE
detect (with MR14 = 0) are enabled.
Mode Register 2 (MR2)
Table 6 illustrates mode register 2. MR23,
MR22, MR21 and MR20 control the frequency of the internal baud rate generator (BRG).
Sixteen rates are selectable for each EPCI
version (-1, -2, -3). Version 1 and 2 specify a 4.9152 MHz TTL input at BRCLK (pin
20); version 3 specifies a 5.0688 MHz input
which is identical to the Signetics 2651.
MR23-20 are don't cares if external clocks
are selected (MR25-MR24 = 0). The individual rates are given in table 1.
MR24-MR27 select the receive and transmit
clock source (either the BRG or an external
input) and the function at pins 9 and 25. Refer to table 6.
Command Register (CR)
The bits in the mode register affecting character assembly and disassembly (MR 12MR 16) can be changed dynamically (during
active receive/transmit operation). The
character mode register affects both the
transmitter and receiver; therefore in synchronous mode, changes should be made
only in half duplex mode (RxEN = 1 or
TxEN = 1, but not both simultaneously = 1).
In asynchronous mode, character changes
should be made when RxEN and TxEN=O or
when TxEN = 1 and the transmitter is marking in half duplex mode (RxEN = 0).
Table 7 illustrates the command register.
Bits CRO (TxEN) and CR2 (RxEN) enable or
disable the transmitter and receiver respectively. A 0 to 1 transition of CR2 forces start
bit search (a sync mode) or hunt mode (sync
mode) on the second RxC riSing edge. Disabling the receiver causes RxROY to go
high (inactive). "the transmitter is disabled,
it will complete the transmission of the character in the transmit shift register (if any)
prior to terminating operation. The TxO output will then remain in the marking state
MODE REGISTER 1 (MR 1)
MR17
MR16
Sync/Async
Async: Stop Bit Length
00 = Invalid
01 = 1 stop bit
10 = 1% stop bits
11 = 2 stop bits
Sync:
Number of
SYN char
0= Double
SYN
1 = Single
SYN
MR15
Parity Type
0= Odd
1 = Even
MR14
Parity Control
0= Disabled
1 = Enabled
MR13
MR12
MR11
Character
Length
00
01
10
11
=
=
=
=
5
6
7
8
bits
bits
bits
bits
MR10
Mode and Baud
Rate Factor
00
01
10
11
=
=
=
=
Synchronous 1X rate
Asynchronous 1X rate
Asynchronous 16X rate
Asynchronous 64X rate
Sync:
Transparency
Control
0= Normal
1 = Transparent
NOTE
Baud rate factor in asynchronous applies only if external clock is selected. Factor is 16X if
internal clock is selected. Mode must be selected (MR11, MR10) in any case.
Signetics
1·57
MICROPROCESSOR DIVISION
JANUARY 1983
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
Table 6
SCN2661 168661
MODE REGISTER 2 (MR2)
MR27-MR24
0000
0001
0010
0011
0100
0101
0110
0111
NOTES
TxC
RxC
Pin 9
Pin 25
E
E
I
I
E
E
I
I
E
I
E
I
E
I
E
I
TxC
TxC
lX
lX
TxC
TxC
leX
16X
RxC
lX
RxC
lX
RxC
16X
FlxC
16X
MR23-MR20
TxC
RxC
Pin 9
Pin 25
M.oda
E
E
I
I
E
E
I
I
E
I
E
I
E
I
E
I
XSYNC'
TxC
XSYNC'
lX
XSYNC'
TxC
XSYNC'
16X
RxC/TxC
BKDET
RxC
BKDET
RxC/TxC
BKDET
RxC
BKDET
sync
async
sync
async
sync
async
sync
async
1000
1001
1010
1011
1100
1101
1110
1111
Baud Rata Salactlon
Saa baud ratas in table 1
1. When pin 9 is programmed 88 XSYNC input, SYN1, SYN1·SYN2, and DLE-SVN1 datec·
tion Ie dls.bled.
E External clock
I ... Internal clock (BRG)
=
1X and 18X ara clock outputs
Table 7
COMMAND REGISTER (CR)
CR7
CR6
Operating Mode
00 = Normal operation
01 = Async:
'=
Requeat
To Send
R••et Error
serialization
1 - Force ATS
output low
CR2
Sync/Aaync
Recel.e
Control
(RxEN)
1
:iii
CRI
CRO
Data Terminal
R.ady
Tranamlt
Control
(TxEN)
A.ync:
Force break
0= Normal
0= Force RTS
output high
after TxSR
CR3
CR4
one clock time
Automatic
echo mode
Sync: SYN and I or
OLE stripping mode
10 = Local loop back
11
CR5
Reset
error flags
0'· Normal
in status register 1 = Force break
0= Disable
1 = Enable
(FE, OE, PEiDLE
detect.)
0= Force OTR
output high
1 = Force OTR
output low
(Not applicable In
0= Disable
1 = Enable
24-pln version.)
Remote loop back
Sync:
Send DLE
0= Normal
1 = Send DLE
Table 8
STATUS REGISTER (SR)
SR7
SR6
SRS
Data Set
Ready
Data Carrier
Detect
FE/SYN Detect
0= OSR input
0= OCO input Aaync:
is high
is high
0= Normal
1 = OSR input 1 = i5Cli input 1 = Framing
is low
is low
SR4
Overrun
SR3
SR2
SRI
SRO
PE/DLE Detect
TxEMT I DSCHG
RxRDY
TxRDY
0= Normal
Aaync:
1 = Overrun
Error
0= Normal
1 = Parity error
Error
0= Receive
0= Normal
1= Change In DSR
(28-pln version only),
or I5C5; or transmit
shift register Is empty
holding
register empty
1 = Receive
holding register
has data
(Should be
ignored in
24·pln version.)
Sync:
a = Normal
1 = SYN
detected
(high) while TiiRI5Y and rxEMf will go high
(inactive). II the receiver Is disabled, it will
terminate operation Immediately. Any character being aa8embled will be neglecled. A
to 1 transition 01 CR2 will Initiate start bit
search (async) or hunt mode (sync).
o
Bits CR1 (28-pln only) (DTR) and CR5 (RTS)
control the DTR and RTS outputs. Data at the
outputs are the logical complement of the
register data.
1·58
a = Transmit
holding
register busy
1 = Transmit
holding register
empty
Sync:
a = Normal
"1 = Parity error or
OLE received
In asynchronous mode, setting CR3 will
lorce and hold the TxD output low (spacing
condition) at the end of the current transmitted character. Normal operation reaumes
when CR3 Is cleared. The TxD line will go
high lor at least one bit time before beginning transmls.lon 01 the next character in
the transmit data holding reg later. In aynchronoua mode, setting CR3 causes the
tranamlaslon 01 the OLE reg later contenta
prior to sending the character In the transmit
Signetics
data holding register. Since this is a one
time command, CR3 does not have to be
reaet by software. CR3 should be set .when
entering and exiting transparent mode and
lor all OLE-non-OLE character sequences.
Setting CR4 causes the error flags in the
status register (SR3, SR4, and SR5) to be
cleared. This Is a one time command. There Is
no internal latch for this bit.
JANUARY 1983
MICROPROCESSOR DIVISION
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
Table 9
SCN2661 EPCI vs SCN2651 PCI
FEATURE
EPCI
1. MR2 Bit 6,7
Control pin 9, 25
Not used
2. OLE detect-SR3
SR3 = a for OLE-OLE,
OLE-SYNC 1
SR3 = 1 for OLE-OLE,
OLE-SYNC 1
3. Reset of SR3, OLE
detect
Second character after
OLE, or receiver disable,
or CR4 = 1
Receiver disable, or CR4 = 1
PCI
4. Send OLE-CR3
One time command
Reset via CR3 on next TxROY
5. OLE stuffing in
transparent mode
Automatic OLE stuffing when
OLE is loaded except if
CR3 = 1
None
6. SYNC 1 stripping
in double sync
non-transparent
mode
All SYNCI
First SYNCI of pair
7. Baud rate
versions
Three
One
8. Terminate ASYNC
transmission
(drop RTS)
Aeset CA5 in response to
TxAOY changing from 1 to 0
Reset CRO when TxEMT
goes from 1 to O. Then reset
CR5 when TxEMT goes from
a to 1
9. Break detect
10. Stop bit searched
Pin 25'
One
FE and null character
Two
11. External jam sync
Pin 9'
No
12. Oata bus timing
13. Oata bus drivers
Improved over 2651
Sink 2.2mA
Sink 1.6mA
Source 400"A
Source 1OO"A
-
NOTES
1. Internal BRG used tor Rxe.
2. Internal BRG used tor TxC.
When CA5 (RTS) is set, the RTS pin is forced
low. A 1 to 0 transition of CA5 will cause ATS
to go high (inactive) one TxC time after the
last serial bit has been transmitted (if the
transmit shift register was not empty).
The EPCI can operate in one of four submodes within each major mode (synchronous or asynchronous). The operational
sub-mode is determined by CR7 and CR6.
CR7-CR6 = 00 is the normal mode, with the
transmitter and receiver operating independently in accordance with the mode and status register instructions.
In asynchronous mode, CR7-CR6 = 01
places the EPCI in the automatic echo
mode. Clocked, regenerated received data
are automatically directed to the TxO line
while normal receiver operation continues.
The receiver must be enabled (CR2 = I), but
the transmitter need not be enabled. CPU to
receiver communications continues normally, but the CPU to transmitter link is disabled. Only the first character of a break
condition is echoed. The TxO output will go
high until the next valid start is detected.
The following conditions are true while in
automatic echo mode:
1. Oata assembled by the receiver are
automatically placed in the transmit holding register and retransmitted by the
transmitter on the TxO output.
2. The transmitter is clocked by the receive
clock.
3. TxROY output = 1.
4. The TxEMT I OSCHG pin will reflect only
the data set change condition.
5. The TxEN command (CRO) is ignored.
In synchronous mode, CR7-CR6 = 01 places
the EPCI in the automatic SYN/OLE stripping mode. The exact action taken depends
on the setting of bits MR17 and MRI6:
1. In the non-transparent, single SYN mode
(MR17-MRI6 = 10), characters in the
data stream matching SYN 1 are not
transferred to the receive data holding
register (RHR).
2. In the non-transparent, double SYN mode
(MR17-MRI6 = 00), characters in the
data stream matching SYN I, or SYN2 if
immediately preceded by SYN I, are not
transferred to the RHR.
3. In transparent mode (MRI6 = I), characters in the data stream matching OLE, or
SYN 1 if immediately preceded by OLE,
Signetics
SCN2661 168661
are not transferred to the RHA. However,
only the first OLE of a OLE-OLE pair III
stripped.
Note that automatic stripping mode does not
affect the setting of the OLE detect and SYN
detect status bits (SR3 and SR5).
Two diagnostic sub-modes can also be
configured. In local loop back mode (CR7CR6 = 10), the following loops are connected internally:
1. The transmitter output is connected to
the receiver input.
2. OTR is connected to OCO and RTS is connected to CTS.
3. The receiver is clocked by the transmit
clock.
4. The OTR, RTS and TxO outputs are held
high.
5. The CTS, OCO, OSR and RxO inputs are
ignored.
Additional requirements to operate in the local loop back mode are that CRO (TxEN),
CR 1 (OTR), and CR5 (RTS) must be set to 1.
CR2 (RxEN) is ignored by the EPCI.
The second diagnostic mode is the remote
loop back mode (CR7-CR6 = 11). In this
mode:
1. Oata assembled by the receiver are
automatically placed in the transmit holding register and retransmitted by the
transmitter on the TxO output.
2. The transmitter is clocked by the receive
clock.
3. No data are sent to the local CPU, but the
error status conditions (PE, FE) are set.
4. The RxROY, TxROY, and TxEMT IOSCHG
outputs are held high.
5. CR 1 (TxEN) is ignored.
6. All other signals operate normally.
Status Register
The data contained in the status register (as
shown in table 8) indicate receiver and
transmitter conditions and modem I data set
status.
SRO IS the transmitter ready (TxROY) status
bit. It. and its corresponding output, are valid
only when the transmitter is enabled. If equal
to 0, it indicates that the transmit data holding register has been loaded by the CPU and
the data has not been transferred to the
transmit shift register. If set equal to I, it
indicates that the holding register is ready
to accept data from the CPU. This bit is
initially set when the transmitter is enabled
by CRO, unless a character has previously
been loaded into the holding register. It is
not set when the automatic echo or remote
loopback modes are programmed. When
this bit is set, the TxROY output pin is low. In
1·59
1
JANUARY 1983
MICROPROCESSOR DIVISION
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
the automatic echo and remote loop back
modes, the output is held high.
SR1, the receiver ready (RxRDY) status bit,
indicates the condition of the receive data
holding register. If set, it indicates that a
character has been loaded into the holding
register from the receive shift register and is
ready to be read by the CPU. If equal to
zero, there is no new character in the holding register. This bit is cleared when the
CPU reads the receive data holding register
or when the receiver is disabled by CR2.
When set, the RxRDY output is low.
The TxEMT/DSCHG bit, SR2, when set, indicates either a change of state of the DSR
(28-pin only) or DCD inputs (when CR2 or
CRO= 1) orthat the transmit shift register has
completed transmission of a character and
no new character has been loaded into the
transmit data holding register. Note that in
synchronous mode this bit will be set even
though the appropriate "fill" character is
transmitted. TxEMT will not go active until at
least one character has been transmitted. It is
cleared by loading the transmit data holding
register. The DSCHG condition is enabled
when TxEN = 1 or RxEN .; 1. It is cleared
when the status register is read by the
CPU. If the status register is read twice and
SR2 = 1 while SR6 and SR7 remain unchanged, then a TxEMT condition exists.
When SR2 is set, the TxEMT I DSCHG output
is low.
SR3, when set, indicates a received parity
error when parity is enabled by MR 14. In
synchronous transperent mode (MR16 = 1),
with parity disabled, it indicates that a character matching DLE register was received
and the present character is neither SYN 1
nor DLE. This bit is cleared when the next
character following the above sequence is
loaded into RHR, when the receiver is disabled, or by a reset error command, CR4.
The overrun error ststus bit, SR4, indicates
that the previous character loaded into the
receive holding register was not read by the
CPU at the time a new received character
was transferred into it. This bit is cleared
SCN2661 168661
when the receiver is disabled or by the reset
error command, CR4.
In asynchronous mode, bit SR5 signifies that
the received character was not framed by a
stop bit, i.e., only the first stop bit is
checked. If RHR = 0 when SR5 = 1, a break
condition is present. In synchronous nontransparent mode (MR16 = 0), it indicates
receipt of the SYN 1 character in single SYN
mode or the SYN 1-SYN2 pair in double SYN
mode. In synchronous transparent mode
(MR 16 = 1), this bit is set upon detection of
the initial synchronizing characters (SYN 1
or SYN 1-SYN2) and, after synchronization
has been achieved, when a DLE-SYNl pair
is received. The bit is reset when the receiver is disabled, when the reset error command is given in asynchronous mode, or
when the status register is read by the CPU
in the synchronous mode.
SR6 and SR7 (28-pin only) reflect the conditions 01 the DCD and DSR inputs respectively. A low input sets its corresponding status
bit, and a high input clears it.
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER
Operating ambient temperature 2
Storage temperature
All voltages with respect to ground 3
RATING
UNIT
Note 4
-65 to +150
-0.5 to +6.0
°c
°C
V
DC ELECTRICAL CHARACTERISTICS 4 ,5,6
LIMITS
PARAMETER
VIL
VIH
Input voltage
Low
High
VOL
VOH 7
Output voltage
Low
High
IlL
Input leakage current
ILH
3-state output leakage current
Data bus high
ILL
Data bus low
ICC
Power supply current
CAPACITANCE
TEST CONDITIONS
Min
Typ
Max
UNIT
V
0.8
2.0
V
IOL = 2.2mA
IOH = -400/LA
0.4
2.4
VIN = 0 to 5.5 V
10
Vo = 4.0V
Vo = 0.45V
10
10
/LA
/LA
150
mA
TA = 25°C, VCC = OV
LIMITS
PARAMETER
CIN
COUT
CliO
TEST CONDITIONS
Max
20
Ic = lMHz
Unmeasured pins tied to ground
Notes on following page.
1·60
Typ
UNIT
pF
Capacitance
Input
Output
Input I Output
Min
Signetics
20
20
MICROPROCESSOR DIVISION
JANUARY 1983
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
SCN2661 168661
AC ELECTRICAL CHARACTERISTICS 4•5•6
PARAMETER
TEST CONDITIONS
Min
tRES
tCE
Pulse width
Reset
Chip enable
1000
250
tAS
tAH
tcs
tCH
tDS
tDH
tRXS
tRXH
Setup and hold time
Address setup
Address hold
R/W control setup
R/W control hold
Data setup for write
Data hold for write
Rx data setup
Rx data hold
10
10
10
10
150
0
300
350
too
tDF
tCED
Data delay time for read
Data bus floating time for read
CE to CE delay
fRIT 10
Input clock frequency
Baud rate generator
(2661A.B)
Baud rate generator
(2661C)
TxC or RxC
tBRH"
tBRH"
tBRl"
tBRl"
tR/TH
tRITl 10
Clock width
Baud rate high (2661A,B)
Baud rate high (2661C)
Baud rate low (2661A.B)
Baud rate low (2661C)
TxC or RxC high
TxC or RxC low
fBRG
fBRG
tTXD
tTCS
Typ
Max
UNIT
ns
ns
Cl
Cl
= 150pF
= 150pF
200
100
ns
600
MHz
1.0
4.9152
4.9202
1.0
dc
5.0688
5.0738
1.0
ns
75
70
75
70
480
480
TxD delay from falling
edge of TxC
Skew between TxD changing and
falling edge of TxC output 8
Cl
= 150pF
Cl
= 150pF
650
ns
0
NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device, This is a stress rating only and functional operation of
the device at these or at any other condition above those indicated In the opera-
tion section of this specification is not implied.
2. For operating at elevated temperatures, the device must be derated based on
+ 150 D C maximum Junction temperature.
3, This product includes circuitry specifically designed for the protection of Its internal devices from the damaging effects of excessive static charge. Nonetheless,lt
is suggested that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified. See ordering code table for applicable temperature range and operating supply range.
5. All voltage measurements are referenced to ground. All time measurements are at
the 50% level for inputs (except teAH and tBRl) and at 0.8V and 2.0V for outputs.
Input levels swing between 0.4V and 2.4V, with a transition time of 20ns
maximum.
6. Typical values are at + 20°C, typical supply voltages and typical processing
parameters.
7. INTR, TxRDY, 'RXFii5Y and TXEMT/DSCHG outputs are open drain.
8. Parameter applies when internal transmitter clock is used.
9. Undertes1 conditions of 5.0688MHz fBRG (2661 C) and 4.9152MHz fBRG (2661A,B),
leRH and teRl measured at V,H and V,l respectively.
10. In asynchronous local loopback mode, using 1X clock, the following parameters
apply:
fR/T = O.83M Hz max.
tRIll = 700ns min.
Signetics
1·61
1
I
i
MICROPROCE~SOR
JANUARY 1983
DIVISION
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
SCN2661 168661
TIMING DIAGRAMS
RESET
CLOCK
REm-1_IRES_~-----
-TBRH- - t B R L -tRlTH- - I R l T L BRCLK,
TxC, RxC
L-
---J
-1/fBRG-
-l11RIT
TRANSMIT
_
RECEIVE
1 BIT TIME
_
(1,18, OR 84 CLOCK PERIODS)
TiC
(INPUT)
TxD
TxC---'"
(OUTPUT)
READ AND WRITE
C E - -.......
~---ICE~::::~~~~:::L_
1·62
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2661 168661
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
TIMING DIAGRAMS
(Cont'd)
1
TxRDY, TxEMT (Shown for 5-bit characters, no parity, 2 stop bits [in asynchronous model)
TxD
w
c
c
TxEN
:IE
en
::>
oz
o
l:
a:
u
~
en
TxEMT
CEFOR
WRITE
OF THR
DATA 2
DATA 1
DATA 3
_D_AI112131415IB
I
TxD
DATA 1
C
I
DATA 4
AI112 1 3 1 4 1 5
DATA 2
B
1
I
en
::>
~
TxRDY
:MT
A11121314:51B
I.
I
g TXEN~
:IE
c
DATA 3 :
C_D_A~
1
.
DATA 4
I
I
)
CEFORlfWRITE
OFTHA
DATA 1
DATA 2
DATA 3
DATA 4
NOTES
A = Start bit
B
C
= Stop bit
1
= Stop bit 2
o = TxD
marking condition
TxEMT goes low at the beginning of the last data bit, or, if parity IS enabled, at the beginnmg of the parity bit.
Signetics
1·63
MICROPROCESSOR DIVISION
JANUARY 1983
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
TIMING DIAGRAMS
SCN2661 168661
(Cont'd)
EXTERNAL SYNCHRONIZATION WITH XSYNC
1XRxC
les
XSYNC
1-
--1
I
les =XSYNC SETUP TIME =300n.
IH
HOLD TIME = ONE RxC
I
I
---j
= XSYNC
I
I
I
IH
I
RxD
v
CHARACTER ASSEMBLY
BREAK DETECTION TIMING
Rx CHARACTER = 5 BITS, NO PARITY
II
I
I
= LOW (IF RxD IS HIGH, LOOK FOR HIGH TO LOW TRANSITION)
FALS~ START BIT CHECK MADE (RxD LOW)
LOOK FOR START BIT
RxD
I
I
I
MISSING STOP BIT DETECTED, SET FE BIT.
0 ___ RHR, ACTIVATE RxRDY. SET BKDET PIN
RxD INPUT -RxSR UNTIL A MARK TO SPACE
TRANSITION OCCURS.
NOTE
If the atop bit is present, the start bIt search
will commence immediately.
*
1-64
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
TIMING DIAGRAMS
SCN2661 168661
(Cont'd)
1
RxRDY (Shown for 5-bit characters, no parity, 2 stops bits [in asynchronous mode] )
w
o
o
::I!:
III
RxEN
::>
~
~
SYNDET
STATUS:..;B:;.;IT.:-_ _ _ _ _ _ _--'
~
u
z
~
RxRDY
r------,I rl-----
CEFOR---' 1 -
U
U
READ
READ
STATUS
REAO RHR
READ
STATUS
(DATA 1)
READ RHR
(DATA 2)
READ RHR
(DATA 3)
READRHR
(DATA 3)
w
o
o
:IE
RxEN
'"::>o
IL __, _.......;>-__.....
Z
oa:
.iii~
S~A~~~R_"~~~
-
_________________
I
L-----------------~r-~>-----~
~----~------------------------------------~
CEFOR.------------------------~~ ~~----------------------------------~~---, v~----READ
READ RHR
(DATA 3)
READ RHR
(DATA 11
NOTES
A = Start bit
B
C
= Stop bit
1
= SlOp bit 2
o=
TxD marking condition
Only one stop bit is detected.
Signetics
1·65
MICROPROCESSOR DIVISION
JANUARY 1983
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
TYPICAL APPLICATIONS
ASYNCHRONOUS. INTERFACE TO CRT TERMINAL
ADDRESS BUS
CONTROL BUS
DATA BUS
R.D
T.D
SCN2661
BRClK
•
r------,I •
I
EIATOTTL
CONVERT
I
I
(OPT)
I
IL ______
J
i9J)
BAUD RATE CLOCK
OSCILLATOR
CRT
TERMINAL
ASYNCHRONOUS INTERFACE TO TELEPHONE LINES
ASYNC
MODEM
PHONE
LINE
INTERFACE
BAUD RATE CLOCK
OSCILLATOR
TELEPHONE
LINE
1·66
Signetics
SCN2661 168661
JANUARY 1983
MICROPROCESSOR DIVISION
ENHANCED PROGRAMMABLE COMMUNICATIONS INTERFACE
TYPICAL APPLICATIONS
SCN2661 168661
(Cont'd)
1
SYNCHRONOUS INTERFACE TO TERMINAL OR PERIPHERAL DEVICE
\
ADDRESS BUS
I
\
CONTROL BUS
I
I
\
DATA BUS
Ju~
RxD
TxD
RXc
SCN2661
TxC
SYNCHRONOUS
TERMINAL OR
PERIPHERAL
DEVICE
SYNCHRONOUS INTERFACE TO TELEPHONE LINES
PHONE
LINE
INTERFACE
SYNC
MODEM
TELEPHONE
LINE
Signetics
1·67
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2681 SERIES
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
'mil,,''''.'ij
DESCRIPTION
FEATURES
The Signetics SCN2681 Dual Universal
Asynchronous Receiver/Transmitter
(DUART) is a single chip MOS·LSI com·
munications device that provides two in·
dependent full·duplex asynchronous
receiverltransmitter channels in a single
package. It interfaces directly with micro·
processors and may be used in a polled or
Interrupt driven system.
• Dual full·duplex asynchronous receiver/
transmlter
• Quadruple buffered receiver data regis·
ters
• Programmable data format
-5 to 8 data bits plus parity
-Odd, even, no parity or force parity
-1,1.5 or 2 stop bits programmable in
1/16 bit increments
• Programmable baud rate for each r.
ceiver and transmlter selectable from:
-18 fixed rates: 50 to 36.4K baud
-One user defined rate derived from
programmable timer/counter
- External 1x or 16x clock
• Parity, framing, and overrun error detec·
tlon
• False start bit detection
• Line break detection and generation
• Programmable channel mode
-Normal (full duplex)
-Automatic echo
-Localloopback
- Remote loopback
• Multl·functlon programmable 16·blt
counter/timer
• Multi·function 7·bit input port
- Can serve as clock or control Inputs
-Change of state detection on four
inputs
• Multi·functlon 8·blt output port
-Individual bit set/reset capability
-Outputs can be programmed to be
status/interrupt signals
• Versatile Interrupt system
-Single interrupt output with eight
maskable Interrupting conditions
-Output port can be configured to provide a total of up to six separate wire·
OR'able interrupt outputs
• Maximum data transfer: 1X - 1MB/sec,
16X - 125KB/sec
• Automatic wake·up mode for multidrop
applications
• Start·end break Interrupt/status
• Detects break which originates in the
middle of a character
• On·chip crystal oscillator
The operating mode and data format of
each channel can be programmed inde·
pendently. Additionally, each receiver and
transmitter can select its operating speed
as one of eighteen fixed baud rates, a 16x
clock derived from a programmable
counterltimer, or an external 1x or 16x
clock. The baud rate generator and
counterltimer can operate directly from a
crystal or from external clock inputs. The
ability to independently program the
operating speed of the receiver and trans·
mitter make the DUART particularly attrac·
tive for dual·speed channel applications
such as clustered terminal systems.
Each receiver is quadruply buffered to
minimize the potential of receiver overrun
or to reduce interrupt overhead in inter·
rupt driven systems. In addition, a flow
control capability is provided to disable a
remote DUART transmitter when the buf·
fer of the receiving device is full.
Also provided on the SCN2681 are a multi·
purpose 7·bit input port and a multipur·
pose 8·bit output port. These can be used
as general purpose I/O ports or can be
assigned specific functions (such as clock
inputs or status/interrupt outputs) under
program control.
The SCN2681 is available in three package
versions to satisfy various system require·
ments: 40·pin and 28·pin, both 0.6" wide
DIPs, and a compact 24·pin, 0.4" wide,
DIP.
PIN CONFIGURATION
VCC
IP4
IP5
IP6
IP2
CEN
X2
RXOB
OPI
OP3
OP5
OP7
01
03
05
07
GNO
OPS
00
02
04
06
VCC
IP2
CEN
RESET
X2
Xl/ClK
RXOA
OPO
01
DO
02
04
05
07
06
INTRN
AO
Vcc
CEh
Xl/ClK
RXOA
TXOA
00
02
04
06
INTRN
• TIL compatible
• Single + 5V power supply
ORDERING CODE
PACKAGES
Ceramic DIP
Plastic DIP
Vcc=5V ±5%, TA=0'Ct070'C
40 Pin 2
28 Pln 2
24 Pin1
SCN2681AC1128 SCN2681 AC1140
Not available
SCN2681AC1 N24 SCN2681AC1 N28 SCN2681AC1 N40
1400 mil wide DIP
TOP VIEWS
2600 mil wide DIP
1·68
05
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'm""lut-"t
BLOCK DIAGRAM
1
r-....
8/
00-07
;J
BUS BUFFER
•
•
CEN
4/
AO-A3
OPERATION
CONTROL
I
ADDRESS
DECODE
.I
R/W CONTROL
RESET
.--
TRANSMIT
HOLDING REG
TxDA
TRANSMIT
SHIFT REGISTER
.
RON
WRN
CHANNEL A
f;=
f-- t-RECEIVE
I
I
HOLDING REG
(3)
f---
RECEIVE
SHIFT REG
~
•
RxDA
•
RxDB
EiB
CRA
SRA
INTERRUPT
CONTROL
INTRN
1-
~
CHANNEL B
(AS ABOVE)
B8
ISR
I---- t--
TxDB
INPUT PORT
c:
a:
....
TIMING
X1/CLK
X2
..
.
I
BAUD RATE
GENERATOR
I
CLOCK
SELECTORS
I
I
I
z
0
u
,,1-
CHANGE OF
STATE
DETECTORS (4)
z
Sf
;::
71
IPO-IPS
Elli3
I---- t--
ACR
I
OUTPUT PORT
COUNTERI
TIMER
XTAL OSC
I
I
'-FUNCTION
SELECT
LOGIC
V-
r-;;s;;;I~
~
8
OPR
.
.
~
CTUR
OPO-OP7
Vee
·GND
~
Signetics
1·69
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'W""IIe1.'"
PIN DESIGNATION
MNEMONIC
APPLICABLE
TYPE
NAME AND FUNCTION
X
110
Data Bus: Bidirectional3-state data bus used to transfer commands, data and status between
the OUART and the CPU. 00 is the least significant bit.
X
X
I
Chip Enable: Active low input signal. When low, data transfers between the CPU and the
OUART are enabled on 00-07 as controlled by the WRN, RON and AO-A3 inputs. When high,
places the 00-07 lines in the 3-state condition.
X
X
X
I
Write Strobe: When low and CEN is also low, the contents of the data bus is loaded into the
addressed register. The transfer occurs on the rising edge of the signal.
RON
X
X
X
I
Read Strobe: When low and CEN is also low, causes the contents of the addressed register to
be presented on the data bus. The read cycle begins on the falling edge of RON.
40
28
24
DO-D7
X
X
CEN
X
WRN
AO-A3
X
X
X
I
Address Inputs: Select the OUART internal registers and ports for read/write operations.
RESET
X
X
X
I
Reset: A high level clears internal registers (SRA, SRB, IMR, ISR, OPR, OPCR), puts OPO-OP7
in the high state, stops the counterltimer, and puts channels A and B in the inactive state,
with the TxOA and TxOB outputs in the mark (high) state.
INTRN
X
X
X
0
Interrupt Request: Active low, open drain, output which signals the CPU that one or more of
the eight maskable interrupting conditions are true.
X1/CLK
X
X
X
I
Crystal 1: Crystal or external clock input. A crystal or clock of the specified limits must be
supplied at all times. When a crystal is used, a capaCitor must be connected from this pin to
ground (see figure 5).
X2
X
X
0
RxOA
X
X
X
I
Crystal 2: Connection for other side of the crystal. Should be connected to ground if a
,crystal is not used. When a crystal is used, a capaCitor must be connected from this pin to
ground (see figure 5).
Channel A Receiver Serial Data Input: The least significant bit is received first. 'Mark' is high,
'space' is low.
RxOB
X
X
X
I
Channel B Receiver Serial Data Input: The least significant bit is received first. 'Mark' is high,
'space' is low.
TxOA
X
X
X
0
Channel A Transmitter Serial Data Output: The least significant bit is transmitted first. This
output is held in the 'mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. 'Mark' is high, 'space' is low.
TxOB
X
X
X
0
Channel B Transmitter Serial Data Output: The least significant bit is transmitted first. This
output is held in the 'mark' condition when the transmitter is disabled, idle, or when operating in local loopback mode. 'Mark' is high, 'space' is low.
OPO
X
X
0
Output 0: General purpose output, or channel A request to send (RTSAN, active low). Can be
deactivated on receive or transmit.
OP1
X
X
0
Output 1: General purpose output, or channel B request to send (RTSBN, active low). Can be
deactivated on receive or transmit.
OP2
X
0
Output 2: General purpose output, or channel A transmitter 1X or 16X clock output, or channel A receiver 1X clock output.
OP3
X
0
Output 3: General purpose output, or open drain, active low counterltimer output, or channel
B transmitter 1X clock output, or channel B receiver 1X clock output.
OP4
X
0
Output 4: General purpose output, or channel A open drain, active low, RxROYA/FFULLA output.
OP5
X
0
Output 5: General purpose output, or channel B open drain, active low, RxROYB/FFULLB output.
OP6
X
0
Output 6: General purpose output, or channel A open drain, active low, TxRDYA output.
OP7
X
0
Output 7: General purpose output, or channel B open drain, active low, TxRDYB output.
IPO
X
I
Input 0: General purpose input, or channel A clear to send active low input (CTSAN).
I
Input 1: General purpose input, or channel B clear to send active low input (CTSBN).
I
Input 2: General purpose input, or counterltimer external clock input.
I
Input 3: General purpose input, or channel A transmitter external clock input (TxCA). When
the external clock is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock.
IP1
X
IP2
X
IP3
X
1-70
X
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'm",,'n'-",
PIN DESIGNATION (Continued)
MNEMONIC
APPLICABLE
40
28
24
TYPE
NAME AND FUNCTION
1
IP4
X
I
Input 4: General purpose input, or channel A receiver external clock input (RxCA). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock.
IP5
X
I
Input 5: General purpose input, or channel B transmitter external clock input (TxCB). When
the external clock is used by the transmitter, the transmitted data is clocked on the falling
edge of the clock.
IP6
X
I
Input 6: General purpose input or channel B receiver external clock input (RxCB). When the
external clock is used by the receiver, the received data is sampled on the rising edge of the
clock.
Vcc
X
X
X
I
Power Supply:
GND
X
X
X
I
Ground
+ 5V supply input
BLOCK DIAGRAM
Timing Circuits
The 2681 DUART consists of the following
eight major sections: data bus buffer,
operation control, interrupt control, timing, communications channels A and B, input port and output port. Refer to the
block diagram.
The timing block consists of a crystal
oscillator, a baud rate generator, a programmable 16-bit counterltimer, and four
clock selectors. The crystal oscillator
operates directly from a 3.6864MHz crystal connected across the Xl/ClK and X2
inputs. If an external clock of the appropriate frequency is available, it may be connected to Xl/ClK. The clock serves as the
basic timing reference for the baud rate
generator (BRG), the counterltimer, and
other internal circuits. A clock signal
within the limits specified in the specifications section of this data sheet must
always be supplied to the OUART.
Data Bus Buffer
The data bus buffer provides the interface
between the external and internal data
busses. It is controlled by the operation
control block to allow read and write
operations to take place between the controlling CPU and the DUART.
Operation Control
The operation control logic receives
operation commands from the CPU and
generates appropriate signals to internal
sections to control device operation. It
contains address decoding and read and
write circuits to permit communications
with the microprocessor via the data bus
buffer.
Interrupt Control
A single active low interrupt output
(INTRN) Is provided which is activated
upon the occurence of any of eight internal events. Associated with the interrupt
system are the interrupt mask register
(IMR) and the interrupt status register
(ISR). The IMR may be programmed to
select only certain conditions to cause
I NTRN to be asserted. The ISR can be read
by the CPU to determine all currently active interrupting conditions.
Outputs OP3-0P7 can be programmed to
provide discrete interrupt outputs for the
transmitters, receivers, and counterltimer.
The baud rate generator operates from the
oscillator or external clock input and is
capable of generating 18 commonly used
data communications baud rates ranging
from 50 to 38.4K baud. The clock outputs
from the BRG are at 16X the actual baud
rate. The counterltimer can be used as a
timer to produce a 16X clock for any other
baud rate by counting down the crystal
clock or an external clock. The four clock
selectors allow the independent selection,
for each receiver and transmitter, of any of
these baud rates or an external timing signal.
The counter/timer (CfT) can be programmed to use one of several timing sources
as its input. The output of the CfT is available to the clock selectors and can also be
programmed to be output at OP3. In the
counter mode, the contents of the CfT can
be read by the CPU and it can be stopped
and started under program control. In the
timer mode, the CfT acts as a programmable divider.
Signetics
Communications Channels
A and B
Each communications channel of the 2681
comprises a full duplex asynchronous receiverltransmitter (UART). The operating
frequency for each receiver and transmitter can be selected independently from
the baud rate generator, the counter timer,
or from an external input.
The transmitter accepts parallel data from
the CPU, converts it to a serial bit stream,
inserts the appropriate start, stop, and optional parity bits and outputs a composite
serial stream of data on the TxO output
pin. The receiver accepts serial data on
the RxO pin, converts this serial input to
parallel format, checks for start bit, stop
bit, parity bit (if any), or break condition
and sends an assembled character to the
CPU.
Input Port
The inputs to this unlatched 7-bit port can
be read by the CPU by performing a read
operation at address 0 16, A high input results in a logic 1 while a low input results
in a logic O. 0 7 will always be read as a
logic 1. The pins of this port can also serve
as auxiliary inputs to certain portions of
the OUART logic.
Four change-of-state detectors are provided which are associated with inputs
IP3, IP2, IP1, and IPO. A high-to-Iow or lowto-high transition of these inputs lasting
longer than 25-50l's will set the corresponding bit In the input port will change
register. The bits are cleared when the
register is read by the CPU. Any change of
state can also be programmed to generate
an Interrupt to the CPU.
1-71
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'm",,'''i_'',
Output Port
The 8·bit multi·purpose output port can be
used as a general purpose output port, in
which case the outputs are the comple·
ments of the output port register (OPR).
OPR[n]= 1 results in OP[n] = low and vice·
versa. Bits of the OPR can be individually
set and reset. A bit is set by performing a
write operation at address E16 with the ac·
companying data specifying the bits to be
set (1 = set, 0 = no change). Likewise, a bit
is reset by a write at address F16 with the
accompanying data specifying the bits to
be reset (1 = reset, 0 = no change).
Outputs can be also individually assigned
specific functions by appropriate pro·
gramming of the channel A mode registers
(MR1A, MR2A), the channel B mode regis·
ters (MR1B, MR2B), and the output port
configuration register (OPCR).
OPERATION
Transmitter
The 2681 is conditioned to transmit data
when the transmitter is enabled through
the command register. The 2681 indicates
to the CPU that it is ready to accept a
character by setting the TxRDY bit in the
status register. This condition can be pro·
grammed to generate an interrupt request
at OP6 or OP7 and INTRN. When a charac·
ter Is loaded into the transmit holding reg·
ister (THR), the above conditions are
negated. Data is transferred from the hold·
ing register to the transmit shift register
when it is idle or has completed transmis·
sion of the previous character. The TxRDY
conditions are then asserted again which
means one full character time of buffering
is provided. Characters cannot be loaded
into the THR while the transmitter is dis·
abled.
The transmitter converts the parallel data
from the CPU to a serial bit stream on the
TxD output pin. It automatically sends a
start bit followed by the programmed
number of data bits, an optional parity bit,
and the programmed number of stop bits.
The least significant bit is sent first. Fol·
lowing the transmission of the stop bits, if
a new character is not available in the
THR, the TxD output remains high and the
TxEMT bit in the status register (SR) will
be set to 1. Transmission resumes and the
TxEMT bit is cleared when the CPU loads a
new character into the THR. If the trans·
mitter is disabled, it continues operating
until the character currently being trans·
mitted is completely sent out. The trans·
mitter can be forced to send a continuous
1-72
low condition by issuing a send break
command.
The transmitter can be reset through a
software command. If it is reset, operation
ceases immediately and the transmitter
must be enabled through the command
register before resuming operation. If CTS
operation Is en;l.bled, the CTSN input must
be low In order for the character to be
transmitted. if It goes high in the middle of
a transmission, the character In the shift
register is transmitted and TxDA then reo
mains in the marking state until CTSN
goes low. The transmitter can also control
the deactivation of the RTSN output. If
programmed, the RTSN output will be reo
set one b.it time after the character In the
transmit shift register and transmit hold·
ing register (if any) are completely trans·
mitted, if the transmitter has been dis·
abled.
Receiver
The 2681 is conditioned to receive· data
when enabled through the command reg·
ister. The receiver looks for a high to low
(mark to space) transition of the start bit
on the RxD input pin. If a transition is detected, the state of the RxD pin is sampled
each 16X clock for 7·112 clocks (16X clock
mode) or at the next rising edge of the bit
time clock (1X clock mode). If RxD is
sampled high, the start bit is invalid and
the search for a valid start bit· begins
again. If RxD is still low, a valid start bit is
assumed and the receiver continues to
sample the input at one bit time intervals
at the theoretical center of the bit, until
the proper number of data bits and the
parity bit (If any) have been assembled,
and one stop bit has been detected . The
least siglficant bit Is received first. The
data is then transferred to the receive
holding register (RHR) and the RxRDY bit
in the SR is set to a 1. This condition can
be programmed to generate an interrupt at
OP4 or OP5 and INTRN. If the character
length is less than eight bits, the most
significant unused bits in the RHR are set
to zero.
After the stop bit Is detected, the receiver
will immediately look for the next start bit.
However, if a non·zero character was received without a stop bit (framing error)
and RxD remains low for one half of the bit
period after the stop bit was sampled,
then the receiver operates as if a new·start
bit transition had been detected at that
point (one-half bit time after the stop bit
was sampled).
The parity error, framing error, overrun er·
ror and received break state (if any) are
Signetics
strobed.into the SR at the received charac·
ter boundary, before the RxRDY status bit
is set. If a break condition is detected
(RxD is low for the entire character in·
cluding the stop bit), a character con·
sisting of all zeros will be loaded into the
RHR and the received break bit in the SR
is set to 1. The RxD input must return to a
high condition for at least one·half bit time
before a search for the next start bit
begins.
The RHR consists of a first·in·first·out
(FIFO) stack with a capacity of three char·
. acters. Data is loaded from the receive
shift register into the topmost empty posi·
tion of the FIFO. The RxRDY bit in the
status register is set whenever one or
more characters are available to be read,
and a FFULL status bit is set if all three
stack positions are filled with data. Either
of these bits can be selected to cause an
interrupt. A read of the RHR outputs the
data at the top of the FIFO. After the read
cycle, the data FIFO and its associated
status bits (see below) are 'popped' thus
emptying a FIFO position for new data.
In addition to the data word, three status
bits (parity error, framing error, and reo
ceived break) are also appended to each
data character in the FIFO (overrun is not).
Status can be provided in two ways, as
programmed by the error mode control bit
in the mode register. In the 'character'
mode, status is provided on a character·
by·character basis: the status applies only
to the character at the top of the FI FO. In
the 'block' mode, the status provided in
the SR for these three bits is the logical
OR of the status for all characters coming
to the top of the FIFO since the last 'reset
error' command was issued. In either
mode reading the SR does not affect the
FIFO. The FIFO is 'popped' only when the
RHR is read. Therefore the status register
should be read prior to reading the FIFO.
If the FIFO Is full when a new character is
received, that character is held in the reo
ceive shift register until a FIFO position is
available. If an additional character is reo
ceived while this state exits, the contents
of the FIFO are not affected: the character
previously in the shiftreglster is lost and
the overrun error status bit (SR[4]) will be
set upon receipt of the start bit of the new
.
(overruning) character.
The receiver can control the deactivation
of RTS. If programmed to operate in this
mode, the RTSN output will be negated
when a valid start bit was received and the
FIFO is full. When a FIFO position be·
comes available, the RTSN output will be
re-asserted automatically. This feature
can be used to prevent an overrun, in the
JANUARY 1983
MICROPROCESSOR DIVISION
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
':net"""".,,,
receiver, by connecting the RTSN output
to the CTSN input of the transmitting
device.
If the receiver is disabled, the FIFO char·
acters can be read. However, no additional
characters can be received until the receiver is enabled again. If the receiver is
reset, the FI FO and all of the receiver
status, and the corresponding output
ports and interrupt are reset. No additional characters can be received until the
receiver is enabled again.
Multidrop Mode
The DUART is equipped with a wake up
mode used for multidrop applications.
This mode is selected by programming
bits MR1A[4:3] or MR1B[4:3] to '11' for
channels A and B respectively. In this
mode of operation, a 'master' station
transmits an address character followed
by data characters for the addressed
'slave' station. The slave stations, with
receivers that are normally disabled, examine the received data stream and 'wakeup' the CPU (by setting RxRDY) only upon
receipt of an address character. The CPU
compares the received address to its station address and enables the receiver if it
wishes to receive the subsequent data
characters. Upon receipt of another address character, the CPU may disable the
receiver to initiate the process again.
A transmitted character consists of a start
bit, the programmed number of data bits,
an addressldata (AID) bit, and the programmed number of stop bits. The polarity
of the transmitted AID bit is selected by
the CPU by programming bit MR1A[2]1
MR1B[2]. MR1A[2]/MRl B[2] = 0 transmits a
zero in the AID bit position, which identifies the corresponding data bits as data,
while MR1A[2]/MRlB[2]= 1 transmits a
one in the AID bit position, which identifies the corresponding data bits as an address. The CPU should program the mode
register prior to loading the corresponding
data bits into the THR.
In this mode, the receiver continuously
looks at the received data stream, whether
it is enabled or disabled. If disabled, it
sets the RxRDY status bit and loads the
character into the RHR FIFO if the received AID bit is a one (address tag), but
discards the received character if the
received AID bit is a zero (data tag). If
enabled, all received characters are transferred to the CPU via the RHR. In either
case, the data bits are loaded into the data
FIFO while the AID bit is loaded into the
status FIFO position normally used for
parity error (SRA[5] or SRB[5]). Framing
error, overrun error, and break detect oper-
ate normally whether or not the receiver is
enabled.
PROGRAMMING
The operation of the DUART is programmed by writing control words into the appropriate registers. Operational feedback
is provided via status registers which can
be read by the CPU. The addressing of the
registers is described in table 1.
The contents of certain control registers
are initialized to zero on RESET. Care
should be exercised if the contents of a
register are changed during operation,
since certain changes may cause operational problems. For example, changing
the number of bits per character while the
transmitter is active may cause the transmission of an incorrect character. In general, the contents of the MR, the CSR, and
the OPCR should only be changed while
the receiver(s) and transmitter(s) are not
enabled, and certai n changes to the ACR
should only be made while the CIT is
stopped.
Mode registers 1 and 2 of each channel are
accessed via independent auxiliary pointers. The pointer is set to MRlx by RESET
or by issuing a 'reset pointer' command
via the corresponding command register.
Any read or write of the mode register
while the pointer is at MRlx switches the
pointer to MR2x. The pointer then remains
at MR2x, so that subsequent accesses are
always to MR2x unless the pOinter is reset
to MRlx as described above.
Mode, command, clock select, and status
registers are duplicated for each channel
to provide total independent operation
and control. Refer to table 2 for register bit
descriptions.
Table 1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
MRIA is accessed when the channel A MR
pointer pOints to MRI. The pOinter is set
to MRI by RESET or by a 'set pointer' command applied via CRA. After reading or
writing MR1A, the pOinter will point to
MR2A.
MR1A[7] - Channel A Receiver Requestto-Send Control - This bit controls the
deactivation of the RTSAN output (OPO) by
the receiver. This output is normally
asserted by setting OPR[O] and negated by
resetting OPR[O]. MR1A[7] = 1 causes
RTSAN to be negated upon receipt of a
valid start bit if the channel A FIFO is full.
However, OPR[O] is not reset and RTSAN
will be asserted again when an empty
FIFO position is available. This feature
can be used for flow control to prevent
overrun in the receiver by using the
RTSAN output signal to control the CTSN
input of the transmitting device.
MR1A[6] - Channel A Receiver Interrupt
Select - This bit selects either the channel A receiver ready status (RXRDY) or the
channel A FIFO full status (FFULL) to be
used for CPU interrupts. It also causes the
selected bit to be output on OP4 if it is
programmed as an interrupt output via the
OPCR.
MR1A[5] - Channel A Error Mode Select
- This bit selects the operating mode of
the three FIFOed status bits (FE, PE, received break) for channel A. In the 'charac·
ter' mode, status is provided on a character-by-character basis: the status applies
only to the character at the top of the
FIFO. In the 'block' mode, the status provided in the SR for these bits is the ac-
2681 REGISTER ADDRESSING
A3 A2 AI AO
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MR1A - Channel A Mode
Register 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
READ (RON = 0)
WRITE (WRN = 0)
Mode Register A (MR1A, MR2A)
Status Register A (SRA)
* Reserved *
RX Holding Register A (RHRA)
Input Port Change Reg. (IPCR)
Interrupt Status Reg. (ISR)
CounterlTimer Upper (CTU)
CounterlTimer Lower (CTL)
Mode Register B (MR1B, MR2B)
Status Register B (SRB)
* Reserved *
RX Holding Register B (RHRB)
* Reserved *
Input Port
Start Counter Command
Stop Counter Command
Mode Register A (MR1A, MR2A)
Clock Select Reg. A (CSRA)
Command Register A (CRA)
TX Holding Register A (THRA)
Aux. Control Register (ACR)
Interrupt Mask Reg. (IMR)
CIT Upper Register (CTUR)
CIT Lower Register (CTLR)
Mode Register B (MR1B, MR2B)
Clock Select Reg. B (CSRB)
Command Register B (CRB)
TX Holding Register B (THRB)
'Reserved*
Output Port Conf. Reg. (OPCR)
Set Output Port Bits Command
Reset Output Port Bits Command
Signetics
1-73
1
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'm"..n".!"
Table 2
REGISTER BIT FORMATS
BIT7
BIT6
BITS
RX RTS
CONTROL
RXINT
SELECT
ERROR
MODE
O=,no
1 = yes
0= RXRDY
1 = FFULL
0= char
1 = block
BIT7
BIT6
MR1A
MR1B
CHANNEL MODE
~Add
CSRA
CSRB
BIT7
SRA
SRB
BIT2
00= with parity
01 = lorce parity
10 = no parity
11 = multi·drop mode
BITS
BIT4
CTS
ENABLE Tx
O=no
1 = yes
O=no
1 =yes
BIT1
PARITY
TYPE
BITS PER CHAR.
0= even
1 =odd
00=5
01=6
10= 7
11 =8
Bin
BIT2
BIT3
BITO
BITO
STOP BIT LENGTH"
0=0.563
1 = 0.625
2=0.688
3=0.750
4=0.813
5=0.875
6=0.938
7= 1.000
8= 1.563
9= 1.625
A= 1.688
B= 1.750
C= 1.813
0= 1.875
E= 1.938
F=2.000
BIT2
BIT1
BITO
0.5 to values shown for 0-7.f channel IS programmed for 5 bltsfchar.
BIT7
CRA
CRB
BIT3
PARITY MODE
Tx RTS
CONTROL
00= Normal
01 = Auto echo
10= Local loop
11 = Remote loop
MR2A
MR2B
BIT4
not usedmust be 0
BIT6
BITS
BIT4
BIT3
RECEIVER CLOCK SELECT
TRANSMITTER CLOCK SELECT
See text
See text
BIT3
BIT2
BIT1
BITO
MISCELLANEOUS COMMANDS
DISABLE Tx
ENABLE Tx
DISABLE Rx
ENABLE Rx
See text
0= no
1 = yes
O=no
1 = yes
O=no
1 = yes
O=no
1=yes
BIT6
BITS
BIT4
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
BIT1
BITO
RECEIVED
BREAK
FRAMING
ERROR
PARITY
ERROR
OVERRUN
ERROR
TxEMT
TxRDY
FFULL
RxRDY
O=no
1 = yes
O=no
1 = yes
O=no
1 =yes
0= no
1 = yes
O=no
1 = yes
O=no
1 =yes
O=no
1 = yes
0= no
1 =yes
.
-These status bits are appended to the correspondmg data character In the receive FIFO. A read of the status register provides these bits (7:5) from the top of the FIFO
together with bits 4:0. These bits are cleared by a 'reset error status' command. In character mode they are discarded when the corresponding data character is read
from the FIFO.
OPCR
ACR
IPCR
1·74
BIT7
BIT6
BITS
BIT4
OP7
OP6
OP5
OP4
BIT3
OP3
BIT2
BIT1
OP2
BITO
0=OPR[7j
1 = TxRDYB
0=OPR[6j
1 = TxRDYA
0=OPR[5j
1= RxRDYI
FFULLB
0=OPR[4j
1 = RxRDYI
FFULLA
OO=OPR[3j
01 = CIT OUTPUT
10 = TxCB (1X)
11 = RxCB (1X)
00=OPR[2j
01 = TxCA (16X)
10=TxCA(1X)
11 = RxCA (1X)
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
Bin
BITO
BRG SET
SELECT
COUNTERITIMER
MODE AND SOURCE
DELTA
IP31NT
DELTA
IP21NT
DELTA
IP11NT
DELTA
IPO INT
0=set1
1 = set2
See table 4
0=011
1 =on
O=of!
1=on
0=011
1=on
O=of!
1 =on
BIT7
BIT6
BITS
BIT4
BIT3
BIT2
81T1
BITO
DELTA
IP3
DELTA
IP2
DELTA
IP1
DELTA
IPO
IP3
IP2
IP1
IPO
0= no
1 =yes
0= no
1 = yes
O=no
1 =yes
O=no
1 = yes
O=low
1 = high
O=low
1 = high
O=low
1 =high
0= low
1 = high
Signefics
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
'W""""-'"
Table 2
ISR
IMR
SCN2681 SERIES
REGISTER BIT FORMATS (Continued)
BIT7
BITS
BITS
INPUT
PORT
CHANGE
DELTA
BREAK B
0= no
1 = yes
0= no
1 = yes
1
BIT4
BIT3
BIT2
BIT1
BITO
RxRDYI
FFULLB
TxRDYB
COUNTER
READY
DELTA
BREAK A
RxRDYI
FFULLA
TxRDYA
0= no
1 = yes
0= no
1 = yes
O=no
1 = yes
0= no
1 = yes
O=no
1 =yes
0= no
1 =yes
BIT7
BITS
BITS
BIT4
BIT3
BIT2
BIT1
BITO
IN. PORT
CHANGE
INT
DELTA
BREAK B
INT
RxRDYI
FFULLB
INT
TxRDYB
INT
COUNTER
READY
INT
DELTA
BREAK A
INT
RxRDYI
FFULLA
INT
TxRDYA
INT
O=off
1 =on
0= off
1=on
O=off
1=on
0= off
1=on
O=off
1=on
O=off
1=on
0= off
1 =on
0= off
1 =on
CTUR
CTLR
cumulation (logical OR) of the status for
all characters coming to the top of the
FIFO since the last 'reset error' command
for channel A was issued.
MR1AI4:3] - Channel A Parity Mode
Select - If 'with parity' or 'force parity' is
selected, a parity bit is added to the transmitted character and the receiver performs a parity check on incoming data.
MR1A[4:3]= 11 selects channel A to operate in the special multidrop mode de·
scribed in the Operation section.
MR1AI2) - Channel A Parity Type Select
- This bit selects the parity type (odd or
even) if the 'with parity' mode is program·
med by MR1A[4:3], and the polarity of the
forced parity bit if the 'force parity' mode
is programmed. It has no effect if the 'no
parity' mode is programmed. In the special
multidrop mode it selects the polarity of
the AID bit.
MR1AI1:0)-ChanneIABitsperCharacter
Select - This field selects the number of
data bits per character to be transmitted
and received. The character length does
not include the start, parity, and stop bits.
MR2A - Channel A Mode
Register 2
MR2A is accessed when the channel A MR
pointer points to MR2, which occurs after
any access to MR1A. Accesses to MR2A
do not change the pointer.
MR2A[7:S) - Channel A Mode Select Each channel of the DUART can operate in
one of four modes. MR2A[7:6] = 00 is the
normal mode, with the transmitter and reo
ceiver operating independently. MR2A[7:6]
= 01 places the channel in the automatic
echo mode, which automatically retrans·
mits the received data. The following con·
ditions are true while in automatic echo
mode:
1. Received data is reclocked and retransmitted on the TxDA output.
2. The receive clock is used for the trans·
mitter.
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. The channel A TxRDY and TxEMT
status bits are inactive.
5. The received parity is checked, but is
not regenerated for transmission, I.e.,
transmitted parity bit is as received.
Signetics
6. Character framing is checked, but the
stop bits are retransmitted as received.
7. A received break is echoed as received
until the next valid start bit is detected.
8. CPU to receiver communication contino
ues normally, but the CPU to transmit·
ter link is disabled.
Two diagnostic modes can also be configured. MR2A[7:6] = 10 selects local loop·
back mode. In this mode:
1. The transmitter output is internally
connected to the receiver input.
2. The transmit clock is used for the reo
ceiver.
3. The TxDA output is held high.
4. The RxDA input is ignored.
5. The transmitter must be enabled, but
the receiver need not be enabled.
6. CPU to transmitter and receiver com·
munications continue normally.
The second diagnostic mode is the remote
loopback mode, selected by M R2A[7:6] =
11. In this mode:
1. Received data is relocked and retrans·
mitted on the TxDA output.
2. The receive clock is used for the trans·
mitter.
1·75
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'm""liel.iti
3. Received data is not sent to the local
CPU, and the error status conditions
are inactive.
4. The received parity is not checked and
is not regenerated for transmission,
i.e., transmitted parity bit is as' reo
ceived.
5. The receiver must be enabled,
6. Character framing is not checked, and
the stop bits are retransmitted as reo
ceived.
7. A received break is echoed as received
until the next valid start bit is detected.
The user must exercise care when switch·
ing into and out of the various modes. The
selected mode will be activated immedi·
ately upon mode selection, even if this oc·
curs in the middle of a received or trans·
mitted character. Likewise, if a mode is de·
selected, the device will switch out of the
mode immediately. An exception to this is
switching out of autoecho or remote loop·
back modes: if the de·selection occurs
just after the receiver has sampled the
stop bit (indicated in autoecho by asser·
tion of RxRDY), and the transmitter is
enabled, the transmitter will remain in
autoecho. mode until the entire stop bit
has been retransmitted.
MR2A[S) - Channel A Transmitter R.
quest·to·Send Control - This bit controls
the deactivation of the RTSAN output
(OPO) by the transmitter. This output is
normally asserted by setting OPR[O] and
negated by resetting OPR[O]. MR2A[5]= 1
causes OPR[O] to be reset au10matically
one bit time after the characters in the
channel A transmit shift register and in
the THR, if any, are completely transmit·
ted, including the programmed number of
stop bits, if the transmitter is not enabled.
This feature can be used to automatically
terminate the transmission of a message
as follows:
1.
2.
3.
4.
5.
Program auto· reset mode: MR2A[5]= 1.
Enable transmitter.
Assert RTSAN: OPR[O]= 1.
Send message.
Disable transmitter after the last character is loaded into the channel A THR.
6. The last character will be transmitted
and OPR[O] will be reset one bit time
after the last stop bit, causing RTSAN
to be negated.
MR2A[4) - Channel A Clear·ta-Send Control - If this bit is 0, CTSAN has no effect
on the transmitter. If this bit is a 1, the
transmitter checks the state of CTSAN
1-76
(I PO) each time it Is ready to send a charac·
ter. If IPO is asserted (low), the character is
transmitted. If it is negated (high), the
TxDA output remains in the marking state
and the transmission is delayed until
CTSAN goes low. Changes in CTSAN
while a character is being transmitted do
not affect the transmission of that character.
MR2A[3:0) - Channel A Stop Bit Length
Select - This field programs the length of
the stop bit appended to the transmitted
character. Stop bit lengths of 9/16 to 1 and
1-9/16 to 2 bits, in increments of 1/16 bit,
can be programmed for character lengths
of 6, 7, and 8 bits. For a character length of
5 bits, 1-1/16 to 2 stop bits can be pro·
grammed in increments of 1/16 bit. The receiver only checks for a 'mark' condition
at the center of the first stop bit position
(one bit time after the last data bit, or after
the parity bit if parity is enabled) in all
cases.
If an external 1X clock is used for the
transmitter, MR2A[3] = 0 selects one stop
bit and MR2A[3]= 1 selects two stop bits
to be transmitted.
MR1B - Channel B Mode
Register 1
MR1B is accessed when the channel B MR
pointer points to MR1. The pointer is set
to MR1 by RESET or by a 'set pointer' com·
mand applied via CRB. After reading or
writing MR1B, the pointer will point to
MR2B.
The bit definitions for this register are
identical to the bit definitions for MR1A,
except that all control actions apply to the
channel B receiver and transmitter and the
corresponding inputs and outputs.
MR2B - Channel B Mode
Register 2
MR2B is accessed when the channel B MR
pointer points to MR2, which occurs after
any access to MR1B. Accesses to MR2B
do not change the pOinter.
The bit definitions for this register are
identical to the bit definitions for MR2A,
except that all control actions apply to the
channel B receiver and transmitter and the
corresponding inputs and outputs.
CSRA - Channel A Clock Select
Register
CSRA[7:41 - Channel A Receiver Clock
Select - This field selects the baud rate
clock for the channel A receiver as follows:
Signetics
CSRA[7:4)
0
0
0
0
0
0
0
0
000
o 0 1
o 1 0
o 1 1
1 0 0
0 1
1 1 0
1 1 1
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
0
Baud Rate
CLOCK = 3.6864MHz
ACR[7) = 0
ACR[7) = 1
50
110
134.5
200
300
600
1,200
1,050
2,400
4,800
7,200
9,600
38.4K
Timer
IP4-16X
IP4-1X
75
110
134.5
150
300
600
1,200
2,000
2,400
4,800
1,800
9,600
19.2K
Timer
IP4-16X
IP4-1X
The receiver clock is always a 16X clock
except for CSRA[7:4] = 1111.
CSRA[3:0) - Channel A Transmitter Clock
Select - This field selects the baud rate
clock for the channel A transmitter. The
field definition is as per CSRA[7:4] except
as follOWS:
CSRA(3:0)
Baud Rate
ACR[7) = 0
ACR[7) = 1
1 1 1 0
1 1 1 1
IP3-16X
IP3-1X
IP3-16X
IP3-1X
The transmitter clock is always a 16X
clock except for CSRA[3:0] = 1111.
CSRB - Channel B Clock Select
Register
CSRB[7:4) - Channel B Receiver Clock
Select - This field selects the baud rate
clock for the channel B receiver. The field
definition is as per CSRA[7:4] except as
follows:
CSRB[7:4)
Baud Rate
ACR[7) = 0
ACR[7) = 1
1 1 1 0
1 1 1 1
IP6-16X
IP6-1X
IP6-16X
1P6-1X
The receiver clock is always a 16X clock
except for CSRB[7:4]= 11.11.
CSRB[3:0) - Channel B Transmitter Clock
Select - This field selects the baud rate
clock for the channel B transmitter. The
field definition is as per CSRA[7:4] except
as follows:
CSRB[3:0)
Baud Rate
ACR[7) = 0
ACR[7) = 1
1 1 1 0
1 1 1 1
IP5-16X
IP5-1X
IP5-16X
IP5-1X
The transmitter clock is always a 16X
clock except for CSRB[3:0]= 1111.
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'm",,11"·'d
CRA - Channel A Command
Register
CRA is a register used to supply commands to channel A. Multiple commands
can be specified in a single write to CRA
as long as the commands are non-conflicting, e.g., the 'enable transmitter' and
'reset transmitter' commands cannot be
specified in a single command word.
CRA[6:4) - Channel A Miscellaneous
Commands - The encoded value of this
field may be used to specify a single command as follows:
CRA[6:4)
o0
o0
0
1
o10
o1
1
1 0 0
1 0 1
1 1 0
1 1 1
COMMAND
No command.
Reset MR pointer. Causes the
channel A MR pointer to point to
MR1.
Reset receiver. Resets the channel A receiver as if a hardware
reset had been applied. The receiver is disabled and the FIFO
is flushed.
Reset transmitter. Resets the
channel A transmitter as if a
hardware reset had been applied.
Reset error status. Clears the
channel A Received Break, Parity Error, Framing Error, and
Overrun Error bits in the status
register (SRA[7:4]). Used in character mode to clear OE status
(although RB, PE, and FE bits
will also be cleared) and in block
mode to clear all error status
after a block of data has been
received.
Reset channel A break change
interrupt. Causes the channel A
break detect change bit in the interrupt status register (ISR[2]) to
be cleared to zero.
Start break. Forces the TXDA
output low (spacing). If the
transmitter is empty the start of
the break condition will be delayed up to two bit times. If the
transmitter is active the break
begins when~ransmission of the
character is completed. If a character is in the THR, the start of
the break will be delayed until
that character, or any others
loaded subsequently are transmitted. The transmitter must be
enabled for this command to be
accepted.
Stop Break. the TXDA line will
go high (marking) within two bit
times. TXDA will remain high for
one bit time before the next
character, if any, is transmitted.
When this bit is set, the channel A 'change
in break' bit in the ISR (ISR[2]) is set. ISR[2)
is also set when the end of the break condition, as defined above, is detected.
CRA[3) - Disable Channel A Transmitter
- This command terminates transmitter
operation and resets the TxRDY and
TxEMT status bits. However, if a character
is being transmitted or if a character is in
the THR when the transmitter is disabled,
the transmission of the character(s) is
completed before assuming the inactive
state.
The break detect circuitry can detect
breaks that originate in the middle of a
received character. However, if a break
begins in the middle of a character, it must
persist until at least the end of the next
character time in order for It to be detected.
CRA[2) - Enable Channel A Transmitter
- Enables operation of the channel A
transmitter. The TxRDY status bit will be
asserted.
CRA[1) - Disable Channel A Receiver This command terminates operation of
the receiver immediately - a character
being received will be lost. The command
has no effect on the receiver status bits or
any other control registers. If the special
multidrop mode is programmed, the receiver operates even if it is disabled. See
Operation section.
CRA[O] - Enable Channel A Receiver Enables operation of the channel A receiver. If not in the special wakeup mode,
this also forces the receiver into the
search for start-bit state.
CRB - Channel B Command
Register
CRB is a register used to supply commands to channel B. Multiple commands
can be specified in a Single write to CRB
as long as the commands are non-conflicting, e.g., the 'enable transmitter' and
'reset transmitter' commands cannot be
specified in a Single command word.
The bit definitions for this register are
identical to the bit definitions for CRA, except that all control actions apply to the
channel B receiver and transmitter and the
corresponding inputs and outputs.
SRA - Channel A Status
Register
SRA[7) - Channel A Received Break This bit indicates that an all zero character
of the programmed length has been received without a stop bit. Only a single
FIFO position is occupied when a break is
received: further entries to the FIFO are inhibited until the RxDA line returns to the
marking state for at least one-half a bit
time (two successive edges of the internal
or external 1x clock).
Signetics
SRA[6] - Channel A Framing Error -This
bit, when set, indicates that a stop bit was
not detected when the corresponding data
character in the FIFO was received. The
stop bit check is made in the middle of the
first stop bit position.
SRA[S] - Channel A Parity Error - This
bit is set when the 'with parity' or 'force
parity' mode is programmed and the corresponding character in the FIFO was received with incorrect parity.
In the special multidrop mode the parity
error bit stores the received AID bit.
SRAI4) - Channel A Overrun Error - This
bit, when set, indicates that one or more
characters in the received data stream
have been lost. It is set upon receipt of a
new character when the FIFO is full and a
character is already in the receive shift
register waiting for an empty FIFO position. When this occurs, the character in
the receive shift register (and its break
detect, parity error and framing error
status, if any) is lost.
This bit is cleared by a 'reset error status'
command.
SRA[3] - Channel A Transmitter Empty
(TxEMTA) - This bit will be set when the
channel A transmitter underruns, i.e., both
the transmit holding register (THR) and
the transmit shift register are empty. It is
set after transmission of the last stop bit
of a character if no character is in the THR
awaiting transmission. It is reset when the
THR is loaded by the CPU or when the
transmitter is disabled.
SRA[2) - Channel A Transmitter Ready
(TxRDYA) - This bit, when set, indicates
that the THR is empty and ready to be
loaded with a character. This bit is cleared
when the THR is loaded by the CPU and is
set when the character is transferred to
the transmit shift register. TxRDY is reset
when the transmitter is disabled and is set
when the transmitter is first enabled, viz.,
characters loaded into the THR while the
transmitter is disabled will not be trans·
mitted.
1-77
1
JANUARY 1983
MICROPROCESSOR DIVISION
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
'm""II".i"
SRAI1] - Channel A FIFO Full (FFULLA)
- This bit is set when a character is transferred from the receive shift register to the
receive FIFO and the transfer causes the
FIFO to become full, i.e., all three FIFO
positions are occupied. It is reset when
the CPU reads the RHR. If a character is
waiting in the receive shift register because the FIFO is full, FFULL will not be
reset when the CPU reads the AHR.
SRAIO] - Channel A Receiver Ready
(RxRDY.A) - This bit indicates that a character has been received and is waiting in
the FIFO to be read by the CPU. It is set
when the character is transferred from the
receive shift register to the FIFO and reset
when the CPU reads the RHR, if after this
read there are no more characters still in
the FIFO.
SRB - Channel B Status Register
The bit definitions for this register are
identical to the bit definitions for SRA, except that all status applies to the channel
B receiver and transmitter and the corresponding inputs and outputs.
OPCR - Output Port Configur·
ation Register
OPCRI7] - OP7 Output Sel"ct - This bit
programs the OP7 output to provide one of
the following:
- The complement of OPR(7)
- The channel B transmitter interrupt
output, which is the complement of
TxRDYB. When in this mode OP7 acts
as an open collector output. Note that
this output is not masked by the contents of the IMR.
OPCRI6] - OP6 Output Select - This bit
programs the OP6 output to provide one of
the followng:
- The complement of OPR[6]
- The channel A transmitter interrupt
output, which is the complement of
TxRDYA. When in this mode OP6 acts
as an open collector output. Note that
this output is not masked by the contents of the IMR.
OPCRIS] - OPS Output Select - This bit
programs the OP5 output to provide one of
the following:
- The complement of OPR[5]
- The channel B receiver interrupt output, which is the complement of ISR[5].
When in this mode OP5 acts as an open
collector output. Note that this output
is not masked by the contents of the
IMR.
1-78
SCN2681 SERIES
OPCRI4) - OP4 Output Select - This bit
programs the OP4 output to provide one of
the following:
OPCRI1:0) - OP2 Output Select - This
field programs the OP2 output to provide
one of the following:
- The complement of OPR[4]
- The channel A receiver interrupt output, which is the complement of ISR[1].
When in this mode OP4 acts as an open
collector output. Note that this output
is not masked by the contents of the
IMR.
- The complement of OPR[2].
- The 16X clock for the channel A transmitter. This is the clock selected by
CSAA[3:01, and will be a 1X clock if
CSRA[3:0] 1111.
- The 1X clock for the channel A transmitter, which is the clock that shifts the
transmitted data. If data is not being
transmitted, a free running 1X clock is
output.
- The 1X clock for the channel A receiver,
which is the clock that samples the
received data. If data is not being received, a free running 1X clock is output.
OPCRI3:2] - OP3 Output Select - This
field programs the OP3 output to provide
one of the following:
- The complement of OPR[3]
- The counter/timer output, in which
case OP3 acts as an open collector output. In the timer mode, this output is a
square wave at the programmed frequency. In the counter mode, the output remains high until terminal count is
reached, at which time it goes low. The
output returns to the high state when
the counter is stopped by a stop
counter command. Note that this output is not masked by the contents of
the IMR.
- The 1X clock for the channel B transmitter, which is the clock that shifts the
transmitted data. If data is not being
transmitted, a free running 1X clock is
output.
- The 1X clock for the channel B receiver,
which is the ciock that samples the
received data. If data is not being received, a free running 1X clock is output.
Table 3
=
ACR - Auxiliary Control Register
ACRI7] - Baud Rate Generator Set Select
- This bit selects one of two sets of baud
rates to be generated by the BRG:
Set 1: 50, 110, 134.5, 200, 300, 600, 1.05K,
1.2K, 2.4K, 4.8K, 7.2K, 9.6K, and
38.4K baud.
Set 2: 75, 110, 134.5, 150, 300, 600, 1.2K,
1.8K, 2.0K, 2.4K, 4.8K, 9.6K, and
19.2K baud.
The selected set of rates is available for
use by the channel A and B receivers and
transmitters as described in CSRA and
CSRB. Baud rate generator characteristics
are given in table 3.
BAUD RATE GENERATOR CHARACTERISTICS
CRYSTAL OR CLOCK = 3.6864MHz
NOMINAL RATE (BAUD)
ACTUAL 16XCLOCK(KHz)
ERROR (PERCENn
50
75
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
7200
9600
19.2K
38.4K
0.8
1.2
1.759
2.153
2.4
3.2
4.8
9.6
16.756
19.2
28.8
32.056
0
0
-0.069
0.059
0
0
0
0
-0.260
0
0
0.175
0
0
0
0
0
0
NOTE:
Duty cycle of 1SX clock is ·50% ± 1 %.
Signetics
38.4
76.8
115.2
153.6
307.2
614.4
JANUARY 1983
MICROPROCESSOR DIVISION
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'mn"lIrI.',j
ACR[6:4]-CounterlTlmer Mode and Clock
Source Select - This field selects the
operating mode of the counter/timer and
its clock source as shown in table 4.
ACR[3:0] - IP3, IP2, IPi, IPO Change 01
State Interrupt Enable - This field selects
which bits of the Input Port Change register (IPCR) cause the input change bit in
the interrupt status register (ISR[7]) to be
set. If a bit is in the 'on' state, the setting
of the corresponding bit in the IPCR will
also result in the setting of ISR[7), which
results in the generation of an interrupt
output if IMR[7)= 1. If a bit is in the 'off'
state, the setting of that bit in the IPCR
has no effect on ISR[7).
IPCR - Input Port Change
Register
IPCR[7:4) - IP3, IP2, IPi, IPO Change 01
State - These bits are set when a change
of state, as defined in the I nput Port section of this data sheet, occurs at the respective input pins. They are cleared when
the IPCR is read by the CPU. A read of the
IPCR also clears ISR[7), the input change
bit in the interrupt status register.
The setting of these bits can be programmed to generate an interrupt to the CPU.
IPCR[3:0) - IP3,IP2,IPi,IPO Current State
- These bits provide the current state of
the respective inputs. The information is
unlatched and reflects the state of the input pins at the time the IPCR is read.
ISR -
Interrupt Status Register
This register provides the status of all
potential interrupt sources. The contents
of this register are masked by the interrupt
mask register (IMR). If a bit in the ISR is a
'1' and the corresponding bit in the IMR is
also a '1', the INTRN output will be asserted. If the corresponding bit in the IMR
is a zero, the state of the bit in the ISR has
no effect on the INTRN output. Note that
the IMR does not mask the reading of the
ISR - the true status will be provided
regardless of the contents of the IMR. The
contents of this register are initialized to
00 16 when the DUART is reset.
ISR(7) - Input Port Change Status - This
bit is a '1' when a change of state has
occurred at the IPO, IP1, IP2, or IP3 inputs
and that event has been selected to cause
an interrupt by the programming of
ACR[3:0). The bit is cleared when the CPU
reads the I PCR.
Table 4
ACR (6:4J FIELD DEFINITION
ACR[6:4)
MODE
CLOCK SOURCE
000
001
010
011
1 o0
1 o1
11 0
111
Counter
Counter
Counter
Counter
Timer
Timer
Timer
Timer
External (I P2)
TXCA - 1X clock of channel A transmitter
TXCB - 1X clock of channel B transmitter
Crystal or external clock (X1/ClK) divided by 16
External (I P2)
External (IP2) divided by 16
Crystal or external clock (X1/ClK)
Crystal or external clock (XlIClK) divided by 16
ISR[6] - Channel B Change In Break This bit, when set, indicates that the channel B receiver has detected the beginning
or the end of a received break. It is reset
when the CPU issues a channel B 'reset
break change interrupt' command.
ISR(2) - Channel A Change in Break This bit, when set, indicates that the channel A receiver has detected the beginning
or the end of a received break. It is reset
when the CPU issues a channel A 'reset
break change interrupt' command.
ISR(5) - Channel B Receiver Ready or
FIFO Full - The function of this bit is programmed by MR1 B[6). If programmed as
receiver ready, it i nd icates that a character
has been received in channel B and is
waiting in the FIFO to be read by the CPU.
It is set when the character is transferred
from the receive shift register to the FIFO
and reset when the CPU reads the RHR. If
after this read there are more characters
still in the FIFO the bit will be set again
after the FIFO is 'popped'. If programmed
as FIFO full, it is set when a character is
transferred from the receive holding register to the receive FIFO and the transfer
causes the channel B FIFO to become full,
i.e., all three FIFO positions are occupied.
It is reset when the CPU reads the RHR. If
a character is waiting in the receive shift
register because the FIFO is full, the bit
will be set again when the waiting character is loaded into the FIFO.
ISR[1] - Channel A Receiver Ready or
FIFO Full - The function of this bit is programmed by MR1A[6). If programmed as
receiver ready, it indicates that a character
has been received in channel A and is
waiting in the FI FO to be read by the CPU.
It is set when the character is transferred
from the receive shift register to the FI FO
and reset when the CPU reads the RHR. If
after this read there are more characters
still in the FIFO the bit will be set again
after the FIFO is 'popped'. If programmed
as FIFO full, it is set when a character is
transferred from the receive holding register to the receive FIFO and the transfer
causes the channel A FIFO to become full,
i.e., all three FIFO positions are occupied.
It is reset when the CPU reads the RHR. If
a character is waiting in the receive shift
register because the FIFO is full, the bit
will be set again when the waiting character is loaded into the FIFO.
ISR[4] - Channel B Transmitter Ready This bit is a duplicate of TxRDYB (SRB[2]).
ISR[3]- Counter Ready - In the counter
mode, this bit is set when the counter
reaches terminal count and is reset when
the counter is stopped by a stop counter
command.
In the timer mode, this bit is set once each
cycle of the generated square wave (every
other time that the counterltimer reaches
zero count). The bit is reset by a stop
counter command. The command, however, does not stop the counterltimer.
Signetics
ISR[O) - Channel A Transmitter Ready This bit is a duplicate of TxRDYA (SRA[2).
IMR -
Interrupt Mask Register
The programming of this register selects
which bits in the ISR cause an interrupt
output. If a bit in the ISR is a '1' and the
corresponding bit in the IMR is also a '1',
the INTRN output will be asserted. If the
corresponding bit in the IMR is a zero, the
state of the bit in the ISR has no effect on
the INTRN output. Note that the IMR does
not mask the programmable interrupt outputs OP3-0P7 or the reading of the ISR.
1·79
1
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'W""lIeI·"t
CTUR and CTLR - CounterlTimer
Registers
The CTUR and CTlR hold the eight MSBs
and eight lSBs respectively of the value to
be used by the counter/timer in either the
counter or timer modes of operation. The
minimum value which may be loaded Into
the CTUR/CTlR registers Is 0002 18' Note
that these registers are wrlte·only and can·
not be read by the CPU.
In the timer (programmable divider) mode,
the CIT generates a square wave with a
period of twice the value (in clock periods)
of the CTUR and CTlA. If the value in
CTUR or CTlR is changed, the current
half·period will not be affected, but subse·
quent half periods will be. In this mode the
CIT runs continuously. Receipt of a start
counter command (read with A3-AO =
1110) causes the counter to terminate the
The counter ready status bit (lSR[3]) is set
once each cycle of the square wave. The
bit is reset by a stop counter command
(read with A3-AO= 1111). The command,
however, does not stop the CIT. The generated square wave is output on OP3 if it is
programmed to be the CIT output.
and ISR(3) is cleared when the counter is
stopped by a stop counter command. The
CPU may change the values of CTUR and
CTlR at any time, but the new count becomes effective only on the next start
counter command. If new values have not
been loaded, the previous count values
are preserved and used for the next count
cycle.
In the counter mode, the CIT counts down
the number of pulses loaded into CTUR
and CTlR by the CPU. Counting begins
upon receipt of a start counter command.
Upon reaching terminal count (0000 18), the
counter ready interrupt bit (ISR[3]) is set.
The counter continues counting past the
terminal count until stopped by the CPU. If
OP3 is programmed to be the output of the
CIT, the output remains high until terminal
count is reached, at which time it goes
low. The output returns to the high state
In the counter mode, the current value of
the upper and lower a bits of the counter
(CTU, CTl) may be read by the CPU. It is
recommended that the counter be stopped when reading to prevent potential pro·
blems which may occur if a carry from the
lower a-bits to the upper a-bits occurs bet·
ween the times that both halves of the
counter are read. However, note that a
subsequent start counter command will
cause the counter to begin a new count
cycle using the values in CTUR and CTlR.
current timing cycle and to begin a new
cycle USing the values in CTUR and CTlA.
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER
Operating ambient temperature2
Storage temperature
All voltages with respect to ground 3
NOTES:
RATING
UNIT
o to + 70
-65 to + 150
-0.5 to +6.0
'c
'c
V
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these or at any other condition above those,indlcated
in the operation section of this specification is not implied.
2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction
temperature,
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging ef·
fects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid ap·
plying any voltages larger than the rated maxima.
DC ELECTRICAL CHARACTERISTICS TA=O'Cto +70'C, Vcc =5.0V :1:5%4,5.6
PARAMETER
VIL
VIH
VIH
VOL
VOH
IlL
ILL
loc
Icc
NOTES:
Input low voltage
Input high voltage (except X1/ClK)
Input high voltage (X1/ClK)
Output low voltage
Output high voltage (except o.c. outputs)
Input leakage current
Data bus 3-state leakage current
Open collector output leakage current
Power supply current
TEST CON DITIONS
LIMITS
Min
Typ
Max
o.a
2.0
4.0
IOL=2.4mA
10H= -4001tA
VIN=Oto Vcc
Vo=OtoV cc
Vo=OtoV cc
OA
2.4
-10
-10
-10
10
10
10
150
UNIT
V
V
V
V
V
itA
itA
itA
mA
4. Parameters are valid over specified temperature range.
S. AU voltage measurements are referenced to ground (GND). For testing, ali input signals SWing between 0.4V and 2.4V with a transition time of 20ns maximum. All time measure·
ments are referenced at input voltages of 0.8V and 2.0V and output voltages of 0.8V and 2.0V as appropriate.
6. Typical values are at + 2SoC, typical supply voltages, and typical processing parameters.
1·80
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'm""II,ie'ij
AC ELECTRICAL CHARACTERISTICS T A= O·C to + 70·C, Vcc =5.0V
± 5%4,5.6.7
TENTATIVE LIMITS
PARAMETER
Min
Reset Timing (figure 1)
t RES RESET pulse width
Bus Timing (figure 2)8
AO-A3 setup time to RON, WRN low
t AS
AO-A3 hold time from RON, WRN high
tAH
CEN setup time to RON, WRN low
tcs
CEN hold time from RON, WRN high
tCH
tRW WRN, RON pulse width
Data valid after RON low
too
Data bus floating after RON high
tOF
Data setup time before WRN high
tos
Data hold time after WRN high
tOH
tRwo High time between READs and/or WRITEs 9.1o
Typ
I"S
10
0
0
0
225
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100
20
200
0
0
Interrupt Timing (figure 4)
INTRN (or OP3-0P7 when used as interrupts) high from:
tlR
Read RHR (RXRDY/FFUll interrupt)
Write THR (TXRDY interrupt)
Reset command (delta break interrupt)
Stop CIT command (counter interrupt)
Read IPCR (input port change interrupt)
Write IMR (clear of interrupt mask bit)
tTX
f TX
Timing (figure 5)
Xl/ClK high or low time
Xl/ClK frequency
CTClK (IP2) high or low time
CTClK (IP2) frequency
RxC high or low time
RxC frequency (16X)
(lX)
TxC high or low time
TxC frequency (16X)
(lX)
100
2.0
100
0
220
0
0
220
0
0
Transmitter Timing (figure 6)
t TXD TxD output delay from TxC low
t TCS TxC output skew from TxD output data
0
Receiver Timing (figure 7)
t RXS RxD data setup time to RXC high
t RXH RxD data hold time from RXC high
NOTES:
UNIT
1.0
175
100
Port Timing (figure 3)8
Port input setup time before RON low
tps
Port input hold time after RON high
tpH
Port output valid after WRN high
tpo
Clock
tClK
fClK
t CTC
f CTC
tRX
f RX
Max
240
200
3.6864
400
ns
ns
ns
300
300
300
300
300
300
ns
ns
ns
ns
ns
ns
2.0
1.0
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
350
150
ns
ns
4.0
4.0
2.0
1.0
ns
ns
4. Parameters are valid over specified temperature range.
5. All vOltage measurements are referenced to ground (GND). Fortesting, all input signals swing between O.4V and 2.4V with a transition time of 20n5 maximum. All time measure-
ments are referenced at input voltages of a.BV and 2.0V and output voltages of a.BV and 2.0V as appropriate.
6. Typical values are at + 2SoC, typical supply voltages, and typical processing parameters.
7. Test condition for outputs: CL =150pF, except interrupt outputs. Test condition for interrupt outputs: CL = 50pF, RL = 2.7K ohm to Vee.
8. Timing is Illustrated and referenced to theWRN and RDN inputs. The device may also be operated with CEN as the 'strobing' input. In this case, all timing specifications apply
referenced to the falling and riSing edges of CEN.
9. If eEN is used as the 'strobing' input, this parameter defines the minimum high time between one eEN and the next.
10. Consecutive write operations to the same command register require at least three edges of the X1 clock between writes.
Signetics
1·81
1
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'am'''·II''e''i
RESET
A
~~
-J[.
lRES~'
Figure 1. Reset Timing
AO-A3
--X'---_------'I '----__
-.f
----J
lAS
CEN
RON
00-07
FLOAT
(READ)
WRN
00-07
t
...J11.
~
(WRITE) _ _ _ _ _ _ _
'DS
-'
VALID
xr---------
Figure 2. Bus Timing
1·82
Signetics
'D
"
~_ _ _ _ _ _ _ __
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'm"llo".iN
1
""'
--:J
,~.~'-
1
{ ..~
WRN\
OPO·OP7
OLD DATA
NEW DATA
Figure 3. Port Timing
~:\
WRN
{')-
INTRN
OR
OP3·0P7
Figure 4. Interrupt Timing
=[
-I
XlIClK
CTCLK
RxC
TxC
teLK
tCTC
I.,
IT>
------
Cl: 10-15pF + (STRAY < 5pF)
C2: 0-5pF+(STRAY < 5pF)
to..
,I
lK
..... 74LS04
teLK
teTe
I ••
IT.
aT
l-
Xl
Ei
~
CLOCK
TO OTHER
CHIPS
2881
C2f
X2
3.68B4MHz
Figure 5. Clock Timing
Signetics
CRYSTAL SERIES RESISTANCE SHOULD
BE LESS THAN 180 OHMS.
1·83
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN2681 SERIES
'm""iiel_",
(INTxCPUn
-{
TxO
(10~~~~~~~KS)-t
~'"l
~
(IXOT~;pun-------l""~----I------LFigure 6. Transmit
I X RxC
INPUT)
\
A
\'---_
RXO--[~·-1 ~ ~")-Figure 7. Receive
TxO
TRANSMITTER
ENABLED
TxRDY
(SR2)
WRN
CTSN1
IIPOI _ _ _ _.J
I
I
n
~~
10POI
l " L - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - " [olpRIOI='
OPR(O)= 1
NOTES
1. TIMING SHOWN FOR MR2(4) = 1.
2. TIM·NG SHOWN FOR MR2(S) 1.
=
Figure 8. Transmitter Timing
1·84
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2681 SERIES
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
'w""""·,,,
1
RxD
RECEIVER
ENABLED
RxRDY
(SRO) _ _ _ _ _ _---'
-+__________
FFUL
(SR1) _ _ _ _ _ _ _ _ _ _
...1
RxRDY/--------,
FFULL
(OP5)2
RDN
OVERRUN
RESET BY COMMAND
(SR~ ----------------------r---~~
RTS1 - - - - ,
(OPOI
' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....J
OPR(01=1
NOTES
1. TIMING SHOWN FOR MR1(7)= 1.
2. SHOWN FOR OPCR(4) = 1 AND MR(6)=0.
FigurB 9. Receiver Timing
MASTER STATION
BIT9
BIT9
---1; 8
I-.+-_DO--,-:°;JI L'\-\'______
TxD
I
I
cr-,r--
BIT9
IADD#2!
11
I
TRANSMITTER~~
ENABLED
I
I
TxRDY
' I
---;)---1'lL....::>,-------II\
\--\
(SR21
.
_ _ _ _ _ _ _ _-\'
WRN
-
,
MR1(4-31=11 ADD#1 MR1(21=0 DO
MR1(21=1
PERIPHERAL STATION
BIT9
RxD - - - - ,
I
101
MR1(21 = 1
BIT 9
BITS
DO
~~~E~~~~
101::
\~
,ADD#2
BITS
BIT9
IADDM2!11:
I """'"II-,
I
:
:
R~;~~ .------_~~:
LJ
-V- l.rl.r
ADD#1
i , . _____________
:.:-=---,
----------1;-----1
RDN/WRN
MR1(4-31=11
.
I
10 1
rl-I-
~
L
;~
~
ST~S...£ATA
ST~US..!~.ATA
DO
ADD#2
Figure 10. Wake Up Mode
Signetics
1-85
Section 2
Video Display
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
CRT CHIP SET COMPARISON FEATURES
FEATURES
System Configurations
Row buffer mode
Transparent mode
Shared mode
Independent mode
Clock interleaving mode
Screen format
1 to 256 characters per row
1 to 16 lines per row
1 to 128 rows per screen
2672
2674
···
··
··
···
··
···
···
··
·
··
·
···
··
·
···
···
·
··
··
··
·
Vertical synchronization
Programmable front porch
Programmable sync width
Programmable back porch
·
·
··
·
··
Horizontal synchronization
Programmable front porch
Programmable sync width
Programmable back porch
Interlace capability
Non-i nterlace
Interlace
Composite sync
RS170 compatible
·
···
···
Cursor
Readable
Writable
Incrementable
Programmable size and blink
16K addressing limit
4MHz maximum character clock rate
Smooth scrolling
Bidirectional
Automatic
Programmable scroll region
·
Split screen
Screen start reg ister 1
Screen start register 2
Multiple splits
Automatic split
·
·
·
Light pen register
AC line lock (external sync)
Bit mapped graphics hardware support
Double height rows
Tops
Bottoms
Both
·
·
Double width rows control output
Dynamic RAM refresh
Signetics
2
·
2·1
JANUARY 1983
MICROPROCESSOR DIVISION
CRT CHIP SET COMPARISON FEATURES
FEATURES
Attributes
Reverse video
Blank
Blink
Highlight
Light pen strike·thru
Underline
Two general purpose
Eight foreground colors
Eight background colors
Monochrome gray levels
Dot width control
Double width
Field oriented
Character oriented
2675
···
··
·
···
·
··
··
··
3
··
··
Background intensity
Programmable
Composite blank
Automatic
·
·
25MHz video dot rate (See note 1)
Programmable dot stretching
Compatible with 2672, 2674 and 2670
6 to 12 dots
Programmable character clock
NOTES:
1. For faster dot rates, consult factory.
2. Two versions of dots per character:
SCB2675B possible dots are 7, 8, 9, 10.
SCB2675C possible dots are 6, 8, 9, 10.
2·2
2673
Signetics
4
·
··
··
··
See note 2
MICROPROCESSOR DIVISION
JANUARY 1983
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
DESCRIPTION
The Signetics Display Character and
Graphics Generator (DCGG) is a maskprogrammable 11,648-bit line select character generator. It contains 128 10X9 characters placed in a 1OX 16 matrix, and has
the capability of shilling certain characters,
such as i, y, g, p and q, that normally extend
below the baseline. Character shilling, previously requiring additional external circuitry, is now accomplished internally by the
DCGG; effectively, the 9 active lines are
lowered within the matrix to compensate for
the character's position.
Seven bits of an 8-bit address code are
used to select 1 of the 128 available characters. The eighth bit functions as a chip enable signal. Each character is defined by a
pattern of logic Is and Os stored in a 10X9
matrix. When a specific 4-bit binary line address code is applied, a word of 10 parallel
bits appears at the output. The lines can be
sequentially selected, providing a 9-word
sequence of 10 parallel bits per word for
each character selected by the address inputs. As the line address inputs are sequentially addressed, the device will automatically place the 10X9 character in 1 of 2 preprogrammed positions on the 18-line matrix
with the positions defined by the 4-line address inputs. One or more of the 10 parallel
outputs can be used as control signals to
selectively enable functions such as halfdot shill, color selection, etc.
The 2670 DCGG includes latches to store
the character address and line address
data. A control input to inhibit character
data output for certain groups of characters
is also provided. The 2670 also includes a
graphics capability, wherein the 8-bit character code is translated direclly into 256
possible user programmable graphic patterns. Thus, the DCGG can generate data for
384 distinct patterns, of which 128 are defined by the mask programmable ROM. See
figure 1 for a typical applications display.
FEATURES
SCN2670
PIN CONFIGURATION
• 128 10X9 matrix characters
256 graphic characters
• Optional thin graphics for forms
• Character and line address latches
• Internal descend logic
• 200nsec and 300nsec character select
access time versions
• Control character output inhibit logic
• Static operation-no clocks required
• Single 5V power supply
• TTL compatible inputs and outputs
Vcc
LA1
2
LA2
LA3
DO
01
02
03
04
05
CA8
08
GM
07
SCO
08
GNO
09
TOP VIEW
ORDERING CODE
Vcc=5V
PACKAGES
Ceramic DIP
Plastic DIP
::!:
5%, TA = O°C 10 70·C
I CA =200ns
I CA =300ns
SCN2670'C2128
SCN2670'C2N28
SCN2670'C3128
SCN2670'C3N28
NOTE
Substitute letter corresponding to standard font for' *' in part number for standard parts. See back of data sheet. Contact sales office for custom ROM patterns.
BLOCK DIAGRAM
SCO------------------------------,
-4--
Vee
GM - - - - - - - - - - - - - - - - - - ,
CAO-CA7 , - - - - - - - - - - ,
READ ONLY
MEMORY
(128.91)
::>
DO-DB
LAO-LA3
LSTROBE - - - - - - -....
Signetics
2-3
JANUARY 1983
MICROPROCESSOR DIVISION
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
SCN2670
PIN DESIGNATION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
CAO·CA7
3·6,8·11
I
Character Address: Eight bit code specifies the character or graphic pattern for which matrix
data is to be supplied. In character mode (GM=O), CAO thru CA6 select one of the 128 ROMdefined characters and CA7 is a chip enable. The outputs are active when CA7= 1 and are tristated when CA7=0. In graphics mode (GM=l), the outputs are active and CAO thru CA7
select one of 256 possible graphic patterns to be output.
CSTROBE
7
I
Character Strobe: Used to store the character address (CAO thru CAl) and graphics mode
(GM) inputs into the character latch. Data is latched on the negative going edge of CSTROBE.
12
I
Graphics Mode: GM=O (low) selects character mode; GM= 1 (high) selects graphics mode.
LAO-LA3
GM
1,25-27
I
Line Address: In character mode, selects one of the 16 lines of matrix data for the selected
character to appear at the 10 outputs. LAO is the LSB and LA3 is the MSB. The input codes
which cause each of the nine lines of character data to be output are specified as part of the
programming data for both non-shifted and shifted fonts. Cycling through the nine specified
counts at the LAO thru LA3 inputs cause successive lines of data to be output on DO thru 09.
The 7 non-specified codes for both non-shifted and shifted characters cause blanks (logic
zeros) to be output. In graphics mode, the line address gates the latched graphics data
directly to the outputs.
LSTROBE
2
I
Line Strobe: Used to store the line address data (LAO thru LA3) in the line address latch.
Data is latched on the negative going edge of LSTROBE.
SCD
13
I
Selected Character Disable: In character mode, a high level at this input causes all outputs
(regardless of line address) to be blanks (zeros) for characters for which CA6 and CA5 are
both o. A low level input selects normal operation. Inoperative in the graphics mode.
09-00
15-24
0
Data Outputs: Provide the data for the specified character and line.
VCC
28
I
+5V power supply.
GND
14
I
Ground.
P:3.f" t
No.
CP1Z]4
CX9009
A~JIJ-2AI
A
L
E
s
Figure 1. Typical Application
2·4
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
FUNCTIONAL DESCRIPTION
The OCGG consists of nine major sections.
line and character oodes are strobed into
the line and character latches. The oharacter latoh outputs are presented to the three
sources of data; the ROM through an address decoder, the graphics logic, and the
output inhibit control. The output inhibit control (together with the SCO input) suppresses the ROM data for selected character codes. The outputs from the line latch
drive the line address translation ROM
which maps the character ROM data onto 9
of 16 line positions. Finally, the line select
multiplexers route the ROM or graphics data
to the output drivers on DO through 09.
Character Latch
The character latch is a 9-bit edge triggered
latch used to store the character address
(CAO thru CAn and graphics mode (GM)
inputs. The data is stored on the falling edge
of CSTROBE. Seven latohed addresses
(CAO thru CA6) are inputs to the ROM character address decoder. In character mode
(GM=O), CA7 operates as a chip enable.
The output drivers are enabled when CA7= 1
and are tri-stated when CA7=0. In graphics
mode (GM= 1), the output drivers are always
enabled and the CAO thru CA 7 outputs of the
Istch are used to generate graphic symbols.
Character Addre•• Decoder
this oircuit decodes the 7-bit character address from the character latch to select one
Read Only Memory
The 11 ,646-bit ROM stores the fonts for the
128 matrix-defined characters. The data for
each charaoter consists of 91 bits. Ninety
bits represent the 10X9 matrix and one bit
specifies whether the character data is output at the normal (unshifted) lines or at the
descended (shifted) lines. The 90 data bit
outputs are supplied to the line select
multiplexers. The descend control bit is an
input to the line address translation ROM.
The ten line select multiplexers select ROM
data as speoified by the line address translation ROM when GM=O, or graphics data
when GM= 1. The inputs to each mUltiplexer
are the nine line outputs from the ROM, an
output from the graphios logic and a logic
zero (ground).
Output Driver.
Ten output drivers with 3-state oapability
serve as buffers between the line select
multiplexers and external logic. The 3-state
control input to these drivers is supplied
from the CA7 latch when GM=O. When
GM=l, the outputs are always active.
LINE
CAO
CAl
CA2
CA3
5-
8CM
CA5
8810-
Line Select Multiplexer.
A ROM within the graphics logic allows the
specific line numbers for which each pair of
bits is output to be specified by the customer. Figure 2 illustrates the general format for
3-
7-
As a customer speoified option, 16 of the
possible graphic codes (H'80' to H'8F') may
be used to generate the special graphic
characters illustrated in figure 3. For each of
these cheracters, the vertical component
appears on· the 04 output. The horizontal
component occurs on LH which is specified
by the oustomer. The vertical components
specified by CAO and CA2 are output for line
addresses zero thru LH and LH thru fifteen,
respectively.
When the GM input is zero (low), the OCGG
operates in the character mode. When it is
one (high), it operates in the graphica mode.
In graphics mode, output data is generated
by the graphics logic instead of the ROM.
The graphics logic maps the latched character address (CAO thru CAn to the outputs
(DO thru 09) as a function of line address
(LAO thru LA3). For any particular line address value, two of the CA bits are output:
CAO, CA2, CA4 or CA8 is output on DO thru
04 and CAl, CA3, CA5 or CA7 is output on
05 thru 09. The outputs are paired: When
CAO is output on DO thru 04, CA 1 is output
on 05 thru 09 and likewise for CA2-CA3,
CA4-CA5 and CA6-CA7.
2-
4-
Thin Graphic. Option
Graphic. Logic
LF=O1-
graphics symbols and an example where
(CA7 thru CAO) = H'85'. The outputs from
the graphics logic go to the line select
multiplexers. The multiplexers route the
graphic symbol data to the outputs when
GM = 1.
of the 126 character fonts stored in the ROM
section of the OCGG.
LINE ADDRESS
SCN2670
CA6
CA7
LL=ll1-00-04-1-05-09-1
I
I
I
I
0-
GROUP 1
1-
2-
3-
GROUP 2
458-
GROUP 3
78-
I--I--+-+-+I--I--+-+-+-
8-
GROUP 4
lOll-
I
GROUP LINE ADDRESSES ARE SPECIFIED BY THE CUSTOMER
I
I
8QSa!~!~!!
EXAMPLE: CA7-CAD= H'65'
GROUP 1 SPECIFIED FOR LINES 0,1,2
GROUP 2 SPECIFIED FOR LINES 3, 4, 5
GROUP 3 SPEOIFIED FOR LINES 8, 7, B
GROUP 4 SPECIFIED FOR LINES 9, 10, 11
SPACE SPECIFIED FOR LINES 12, 13, 14, 15
Figure 2. Graphics Symbols -
Signetics
General Format
2·5
2
JANUARY 1983
MICROPROCESSOR DIVISION
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
Output Inhibit Control
The output inhibit control logic operates only
if GM-O. It cauaea the output of the line
select multiplexers to be logic zero if the
SCD Input Is high and CA6 and CAS cif the
latched character address are 00. If the
SCD Input is low, normal operation occurs.
(this festure is useful In ASCII coded spplications to selectively disable character
generation for non-displayable characters
such as line feed, carriage return, etc.)
GENERAL FORMAT
10 x 16 CHARACTER BLOCK
Line Address Latch
The line address latch is a 4-bit latch used
to store the line address (LAO-LA3). The
data is stored on the negative edge of the
LSTROBE input.
Line Address Translation ROM
Thia 32X 10 ROM translates the S-blt code
conSisting of the 4 outputs from the line address latch and the descend control bit from
the ROM into a 1-of-l0 code for the line
select multiplexers. Programming information provided by the customer specifies the
address which selects each line of ROM
data for both shifted and non-shifted charactera. Thus, there are nine line addresses
which select ROM data for unshifted characters and nine addresses for shifted characters. These combinations are usually
specified by the customer in either ascend·
ing or descending order. For the remaining
14 codes (7 each for unshifted snd shifted
chsrscters), the trsnslstion ROM forces zeros at the outputs of the line select
multiplexers.
04
00
THIN GRAPHIC FONTS FOR
CA7 - CAO = HEX 80-H EX 8F
This circuitry only operstes if GM=O. When
GM= 1, the line select multiplexers sre
forced to select the outputs from the grsph·
ics logic.
Figure 4 shows an exampla of data outputs
where the customer has specified line 14 as
the first line for unshifted characters, line 11
as the first line for shifted characters and
line address combinations in descending
order.
CUSTOM PATTERN
PROGRAMMING INSTRUCTIONS
A computer-aided technique utilizing
punched computer cards is employed to
specify a custom version of the 2670. This
technique requires that the customer supply
Signetics with a deck of standard SO-column
computer cards describing the data to be
stored in the ROM array, the programmable
line address translation ROM, thin graphics
option, and the graphics line font translation
ROM.
09
80
81
82
83
84
85
86
87
86
89
8A
88
5JBJEdtE
8C
80
8E
8F
Figure 3. Special Graphic Characters
2-6
Signetics
SCN2670
MICROPROCESSOR DIVISION
JANUARY 1983
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
SCN2670
LINE
~~
r---
~
l"oi"<
•
15
14
13
12
11
10
f
6
~
(
•• •
•
•
r('
2
)
;1
rr r\ -
••
K
(
)
~
~
~
X
-
J
' - - - - - - - - - - - C U S T O M E R SPECIFIED _ _ _ _ _ _ _ _ _ _--J
Figure 4. Customer Specified Example
On receipt of a card deck, Signetics will
translate the card deck to a truth table using
the Signetics Computer Aided Design (CAD)
facility. The truth table and font diagrams
will then be sent to the customer for final
approval. On receipt of final approval,
Signetics will produce masks and proceed
with manufacturing.
Programming information can also be input
on TTY 7-level tape as card images. Each
card image must be terminated with a carriage return-line feed. An EOT character
must signify the end of the data set.
Customer identification cards are always
labeled with a C in column 1. For customer
identification, four cards are required. Any
number of additional customer identification
cards are permitted. The following data
should be included:
CUSTOMER ID CARD #2
COLUMN
1
2
3-70
71-80
DATA
C
blank
Customer contact
person name I
phone number
blank
CUSTOMER ID CARD #5 THRU N
COLUMN
1
2
3-70
71-80
DATA
C
blank
Any information desired
blank
CUSTOMER ID CARD #3
COLUMN
1
2
3-70
71-80
DATA
C
blank
Customer address
blank
CUSTOMER ID CARD # 1
COLUMN
1
2
3-9
10-14
15-70
71-60
DATA
C
blank
2670/CP
blank
Company namel
company part number
blank
CUSTOMER ID CARD #4
COLUMN
1
2
3-70
71-80
DATA
C
blank
Customer city, state,
zip code
blank
Signetics
2·7
MICROPROCESSOR DIVISION
JANUARY 1983
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
SCN2670
The following masking information cards must be included:
Mask Information Card # 1:
Shift and Nonshlft Character Translation Data
DATA
COLUMN
1-9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27-29
30-35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53-59
60'
61-64
652
66-80
MASK INFORMATION CARD #2:
Graphics Translation Data
DATA
COLUMN
NONSHIFT=
Line address in hex which outputs the first font
word for nonshifted ROM fonts
1-14
15-17
,
Line address in hex which outputs the second
font word for nonshifted ROM fonts
,
18-19
20-23
24
third
,
25-29
30-45
fourth
,
fifth
,
sixth
,
seventh
,
46-80
eighth
,
ninth
blank
SHIFT=
Line address in hex which outputs the first font
word for shifted ROM fonts
second
,
third
,
fourth
,
fifth
,
sixth
,
seventh
,
eighth
,
ninth
blank
o or 1
blank
o or 1
blank
NOTES
1. Column 60 specifies the font truth table horizontal format. 0 specifies left to right printing of 00 thru 09. 1
specifies 09 thru 00.
2. Column 65 specifies the font truth table vertical printout
MASK INFORMATION CARD #3 THRU #130:
ROM Font Data
DATA
COLUMN
1-2
3
4
5
6-8
9
10-12
13
14-16
17
18-20
21
22-24
25
26-28
29
30-32
33
34-36
37
38-40
41-80
Character address in hex (CA6 thru CAO)'
blank
S for shifted; N for nonshifted.
blank
Data for first ROM font word in hex (09 thru DO).
blank
second
blank
third
blank
fourth
blank
fifth
blank
sixth
blank
seventh
blank
eighth
blank
ninth
blank
NOTE
• A separate card is required for each character address
hex 00 thru hex 7F.
format. 0 specifies top to bottom printing of line address
hex 0 thru F. 1 specifies hex F thru O.
2-8
THIN GRAPHICS=
YES or NO~, where ~ = blank. Specifies whether graphics address hex 80 thru hex 8F will
select the special thin graphics font.
blank
HOR=
The line address in hex for the horizontal segments of line graphics fonts. Leave blank if columns 15 thru 17 are NO
blank
Graphics group number 1 or 2 or 3 or 4 or blank.
Columns 30 thru 45 correspond to line address
hex 0 thru hex F respectively. The group number specified in each column will cause the
graphics data generated by that group to be
output at the corresponding line address. A
blank specifies no data for that address.
blank
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
Printouts
SAMPLE CARD DECK INPUT
Signetics will translate the card deck to the
following printouts to be submitted to the
customer for approval:
THIN GRAPHIC5=YES
HOR=7
1111222233331+1+'+'1
NONSHIFT=l ,2.3 ,It
fu7.lh9
SHIFT=3 ,1+ .5.(,.7.8. 9.A, B
• A repeat of all customer information.
• A separate font drawing for each of the
128 ROM characters and 256 graphics
fonts. The font drawings are positioned on
a lOX 16 matrix as specified by the cus·
tomer's translation data.
SIGN[TICS C
2670,CPIDOOPA
.0;.
2670 TEST RUN
00 N 022 026 02A 032 OAA 088 088 088 070
SCN2670
01+/16179
If 0 N 078 084 OB2 oCA 08A 072 002 081t 078
01 N Ole 002 DOC 010 OBE 086 OF8 085 088
41 NOlO 02a Oil-II- 082 082 OFE 082 082 Ob2
02 N Ole 002 DOC 010 DBE OSO 020 050 088
1f2 N 03E 044 081f 0 .. 4 03e 01f4 0811- 011-4 03E
03 N DIE 002 ODE 002 O'JE 050 020 050 088
43 N 078 084 002 n02 002 002 002 081f 078
0'40 N DIE 002 ODE 002 DIE OF6 020 020 U20
44 N 03E 011-4 084 n84 081f 084 08'1- 044 03E
05 N OlE 002 ODE 002 D6E 0']0 DeJQ ODD 0[0
45 N OFE 002 002 002 03E 002 002 002 OFE
06 N DOC 012 DIE 012 092 050 030 050 090
1t6 N on: 002 002 002 03E 002 002 002 002
07 NODE 012 ODE 012 ODE 010 010 010 OFO
47 N 078 084 002 002 002 OE2 062 Oe4 OB8
08 NODE 012 DOE 012 DEE 010 060 DaD 070
1t8 N 082 082 082 082 OFE 082 082 082 082
09 N 012 012 Olf: n12 012 OF8 (120 020 020
49 N 07C 010 010 010 010 010 (lIe 010 07e
OA N 002 002 002 olE OFO 010 070 010 010
4A N 0[0 01f0 040 (lifO 01+-0 0'+0 Q42 01f2 03C
DB N 022 022 022 014 D08 OFB 020 020 020
Ifa N 082 01f2 022 n12 OOA 016
DC N DIE 002 ODE 002 OF2 010 070 010 010
ItC N 002 002 002 002 002 002 002 002 07E
00 N Ole 002 002 002 07e 090 lila 050 090
11-0 N 082 OC6 OAA 092 092 082 082 082 082
DE N OlC 002 OOC 010 06E 090 090 090 060
4E N 082 082 086 08A 092 OA2 OC2 082 082
:In
0'+2 082
OF N Ole 002 DOC 010 DEE 040 01f0 01f0 OED
4F N 038 Olflf 082 082 082 082 082 041f 038
10 NODE 012 012 012 ODE 010 010 010 OFO
50 N 07E 082 082 oB2 07E 002 002 002 a02
11 N OOE 012 012 012 04[ 060 01f0 01f0 ora
51 N 038 01f4 082 082 082 092 OA2 Olf'+ 088
12 NODE: 012 012 012 06E 090 040 020 OFO
52 N 07E 082 082 082 07E 012 \.122 u'+2
13 N DOE 012 012 012 06[ 080 060 oe-o 010
53 N 078 084 002 00'+ 038 040 080 0l+2 03C
llf NODE 012 012 012 OIfE 060 050 OF8 01t0
OFE 010 010 010 010 010 GI0 cl0 OlC
15 N 012 016 OlA 012 092 050 030 050 090
55 N 082 082 082 082 082 082 0132 Olflf 038
16 N OlC a02 DOC 010 08E 050 020 020 020
56 N 082 082 082 0'+1f Olflf 028 0<'8 010 010
08~
17 N OlE 002 ODE 002 07E 090 010 090 070
57 N 082 082 082 082 082 092
18 N Ole 002 002 002 Ole 090 ('PO (lOO
(19(1
5a N 082 082 044 028 010 028 Olflf 082 082
OA~
068
59 N 082 082 011-4 028 010 010 010 010 010
090 070 00:10 070
5A N OFE 080 011-0 020 010 008 DOli- 002 OFE
19 N DIE 002 OOE 002 OlE 088 ODS
lA N Ole 002 DOC 010
an
~Cj~
OAf\. QIf!j.
lB N DIE 002 ODE 002 OlE OED 010 010 OED
58 N 07e 004 001f n04 DOli- 004 004 004 07C
lC N DIE 002 OOE n02 OE2 010 0 .. 0 080 070
5C N 000 002 00'1 008 010 020 011-0 080 000
10 N OlC 002 alA 012 OEC 010 {Jf,0 080 070
50 N 07e 040 0'10 n40 0'+0 040 011-0 01f0 07C
IE N DOE 012 ODE OOA OF2 010 060 080 070
5E NOlO 036 054 010 010 010 010 010 010
IF N 012 012 012 012 DEC 010 060 DaD 070
SF N 000 000 008 00,," OFE 004 008 000 000
20 N 000 000 000 000 000 000 000 000 000
60 N 018 018 010 020 000 000 000 000 000
21 NOlO 010 010 010 010 000 (JOO 010 010
61 N 000 000 000 03C 011-0 07C 011-2 011-2 OBC
22 N 028 026 028 026 000 000 000 000 000
62 N 002 002 002 03A 046 011-2 01f2 046 03A
23 N 028 026 OF( 026 028 021:1 OFE 028 026
63 N 000 000 000 03C CII-2 002 002 042 03C
24 N 028 OFe 02A 02A 07C 01'16 01\8 07E 028
£Oil- N 040 040 040 05e 062 042 042 062 OSC
25 N 004 081'1 01f4 020 010 006 Oil-II- OA2 040
65 N 000 DOD 000 03C 042 07E 002 002 03C
26 NoDe 012 012 DOC OOC 012 OA2 042 OBC
66 N 030 048 ooa noa 03E 008 008 008 008
27 N 018 018 008 004 000 000 000 000 000
&7 S 000 05C 062 n42 062 OSC 011-0 0'12 03C
28 N 020 010 008 008 008 008 coa 010 020
68 N 002 002 002 03A 011-6 042 011-2 042 042
29 N 008 010 020 020 020 020 020 010 006
69 N 000 010 000 n18 010 010 010 010 038
2A N 000 010 051f 038 OFE 038 054 010 000
6A S 000 060 0110 n40 oil-a 040 011-0 044 038
28 N 000 010 010 OlD OFE: DID 010 DID DOD
6B N 002 002 002 022 012 aDA 016 022 0'+2
2e s 000 ODD DOD 000 000 018 018 008 004
6C N 018 010 010 010 010 010 010 010 038
20 N 000 000 000 noD OFE 000 000 000 000
60 N 000 000 000 06A 096 092 092 092 092
2E N 000 000 000 nOD ODD 000 000 016 018
EiE N 000 000 000 03A 011-6
0~2
0'+2 0'12 042
2F NOaa 080 040 020 010 008 DOl+- 002 000
6F N ODD 000 000 03C 042
0~2
042 042 03C
3D N 038 044 OC2 oA2 092 08A 086 Olfll- 038
70 SODa 03A 046 042 046 03A 002 002 002
31 NOlO 018 014 olD 010 010 010 010 07C
71 S 000 OSc 062 042 062 05c 040 040 040
32 N 07e 082 080 040 038 00'+ 002 002 on:
72 N 000 000 000 03A 04£, 002 002 002 002
33 N 07C 082 080 080 070 080 080 082 07c
73 N 000 000 000 o3C 042 DOC 030 0'12 03C
34 N 040 060 050 olt8 011-4 OFE 011-0 040 040
74 N 000 008 008 OlC 008 008 008 0'18 030
35 N OFE 002 002 n02 OlE 080 08Q 082 07C
7S N 000 000 000 042 042 0It2 042 OEi2 05C
36 N 078 084 002 n02 07A 086 082 082 07C
76 NOaa 000 000 nll-4 044 04'+ 044 028 010
37 N OFE 080 080 0It0 020 010 008 DOlt 002
77 N 000 000 000 082 082 092 092 092 O£,C
on
082 082 Olt4 038 011-4 082 062 07C
78 N 000 ODD 000 0'12 02'1 018 018 02 .. 042
39 N 07C 082 062 nC2 aBC 080 080 0 .. 2 03C
79 S 000 042 0'+2 042 062 OSC 040 042 03C
38 N
3A N 000 000 000 018 018 000 000 018 018
7A N 000 000 000 o7E 020 010 008 DOlt 07E
38 S 000 018 018 nOO 000 018 018 008 004
78 N 030 ooe 008 n08 00 .. 008 008 008 030
3C N 020 010 006 0011 002 DOlt ooa 010 020
7C NOlO 010 010 000 000 000 010 010 010
3D N 000 000 000 oFE 000 000 OFE 000 000
70 NOla 020 020 020 040 020 020 020 018
3E N 008 010 020 01t0 oao 040 020 010 008
7E N 000 000 000 oOc 092 060 000 000 000
3F N 07C 082 082 080 060 010 010 000 010
7F NOAA 0511 OAA oS4- DAA 0511- OAA 054 OAA
Signetics
2
2·9
MICROPROCESSOR DIVISION
JANUARY 1983
SCN2670
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Supply voltage
Operating ambient temperature'
Storage temperature
All voltages with respect to ground 3
RATING
UNIT
6.0
Oto +70
-65 to +150
-0.3 to +6.0
V
·C
·C
V
NOTES
1. Strelaea above tho.e Ilated under AbBolute Maximum Ratings may cau.e permanent
damage to the device. this 18 a atr••• rating only and functional operation of the device
at theae or any other condition above thOle indicated in the operation aection of this
specification i8 not implied.
2. For operating at elevated temperature., the device must be derated based on +160°C
maximum junction temperature and thermal reai.tance of.60°C/W junction to ambient
(ceramic package).
3. This product includes circuitry apeclflcally designed for the protection of its internal
devices from the damaging effects of excessive static charge. Nonetheless it is
suggested that conventional precautions be taken to avoid applying any voltages
larger than the maxima.
DC ELECTRICAL CHARACTERISTICS TA = o·C to 70·C, VCC =
5.0V ± 5% 1.'.3
LIMITS
TEST CONDITIONS
PARAMETER
Min
Typ
Max
UNIT
VIL
Input low voltage
0
0.8
V
VIH
Input high voltage
2.0
VCC
V
VOL
Output low voltage
10 = 1.6mA
0
0.4
V
VOH
Output high voltage
10 = -100"A
2.4
VCC
V
IlL
Input leakage current
VIN = 0 to 4.25V
10
"A
10L
Output leakage current
Vo = 0.4 to 4V
±10
IlA
ICC
Supply current
80
rnA
CIN
Input capacitance
10
pF
COUT
Output capacitance
15
pF
35
VCC = 5.25V
All other pins grounded
AC CHARACTERISTICS TA=O·C to + 70·C , Vcc=5V
-+5%1,2.3.4
LIMITS
PARAMETER
300ns
Min
Min
Max
Unit
tws
Strobe pulse width
100
100
ns
t LAS
Line address setup
50
50
ns
tLAH
Line address hold
25
25
ns
tCAS
Character address setup
25
15
ns
tCAH
Character address hold
25
15
tCA
Character select access
300
200
ns
tLA
Line select access
500
350
ns
tSEL
Chip select delay
250
150
ns
tOES
Chip deselect delay
200
125
ns
tsc
Special character blanklunblank time
300
200
ns
NOTES
1. Parameters are valid over operating temperature range unless otherwise specified.
2. All voltage measurements are referenced to ground. All time measurements are at
the O.BV or 2.0V level for Inputs and outputs. Input levels are OV and 2.4V.
3. Typical values are at + 25°C. typical supply voltages and typical processing
parameters.
4. Test conditions: CL = l00pF and 1 TTL load.
2·10
200ns
Max
Signetics
ns
JANUARY 1983
MICROPROCESSOR DIVISION
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
SCN2670
TIMING DIAGRAMS
LSTROBE
2
LAO-LA3
__________'_._______
IL_A____
DO-D8
--J~~
____
CAS, CA6
DD-D8
NOTE
1. WHEN GM = 1, SCD INPUT IS INACTIVE
CSTROBE
ICAH
CAO-CA7, GM
DO-DB
_
'~
~
_ _
ICA
__
CSTROBE
-ISEL
DO-D8 _ _O;;;U;,;,T;",;PU;,;,TS:..T.:,;,R;;,;I.S;,;,T;;:;AT;,;:E_ _~
NOTE
1. CA7 OPERATES AS OUTPUT ENABLE ONLY IN CHARACTER MODE (GM =0)
Signetics
2-11
JANUARY 1983
MICROPROCESSOR DIVISION
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
2·12
Signetics
SCN2670
JANUARY 1983
MICROPROCESSOR DIVISION
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
SCN2670
2
Signetics
2·13
MICROPROCESSOR DIVISION
JANUARY 1983
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
2·14
Signetics
SCN2670
MICROPROCESSOR DIVISION
JANUARY 1983
DISPLAY CHARACTER AND GRAPHICS GENERATOR (DCGG)
SCN2670
2
Signetics
2·15
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
DESCRIPTION
FEATURES
The Signetics 2671 Programmable Keyboard and Communications Controller
(PKCC) is an MaS LSI device which provides a versatile keyboard encoder and an
independent full duplex asynchronous communications controller. It is intended for use
in microproc!,ssor based systems and provides an eight bit data bus ,interface.
• Kayboard Intarface
Contact or capacltlva keyboard
Up to 128 keys on an 8 X 1S matrix
Encoded or unancoded operaUon
Four coda levels per kay
Latched key optlon-..parate
deprass and release codes
Programmable scan rata and debounce
Oma
Programmabla rollovar modes
Programmabla auto-rapeat for
selactad kays
Tone output-two frequanclas
• Asynchronous communication
Interfaca
Intarnal baud rata ganarator-1S rates
Full duplax oparaUon
Detactlon of start and and of braak
Programmable braak ganardon
Programmabla charactar paramatars
Auto-acho and malntananca loopback
modas
• Pollad or Intarrupt opardon
• Interrupt priority controller and vector
ganarator
• Oparatas dlracUy from crystal or
axtarnal clocks
'
• TTL compaUble
• Singia +5 volt powar supply
• 40 pin dualin-lina packaga
The keyboard encoder handles' the scan·
ning, debounce, and encoding of a keyboard
matrix with a maximum of 128 keys. It pro·
vides four levels of key encoding corresponding to the separate SHIFT and CON·
TROL input combinations. Four keyboard
rollover modes can be programmed including provisions lor up to 16 latched keys.
Control outputs are provided for Interfacing
with contact or capacitive keyboards. An
eight bit keyboard status register provides
status information to the CPU.
The receiver section of the communications
, controller accepts serial data from the RxD
pin and converts it to parallel data characters. Simultaneously; the transmiller section
accepts parallel data from the data bus and
outputs serialized data onto the TxD pin. Received data is checked for parity and fram·
ing errors, and break conditions are flagged.
Character lengths can be programmed as 5,
6, 7, or 8 bits not including parity, start or
stop bits. An internal baud rate generator
(BRG) with 16 divider ratios can be used to
derive the receive and I or transmit clocks.
The BRG can accept an external clock or
operste directly from a crystal. An eight bit
communications status register provides
status information to the CPU.
PIN CONFIGURATION
CRT tarmlnals
Hard copy tarmlnals
Word procasslng systems
Data antry tarmlnals
Small buslnass computer.
FUNCTIONAL DESCRIPTION
The PKCC consists' of six major sections
(see block diagram). These are the transmiller, receiver, timing, operation control,
keyboard encoder, and a priority encoded
interrupt control unit. Thase sections com·
municate with each other via an internal
data bus and an Internal control bus. The
internal data bus Interfaces to the
microprocessor data bus via a bidirectional
data bus buffer.
ORDERING CODE
2-16
XTAL1
RxC
A2
A1
AD
CE
TNTA
07
DO
06
01
05
02
04
INTR
03
vss
XINTR
TOP VIEW
APPLICATIONS
•
•
•
•
•
The PKCC has an interrupt mask register to
selectively enable certain keyboard and
communications status bits to generate In·
terrupts. Priority encoded interrupt
vectoring is available. Upon receipt of an
interrupt acknowledge, an interrupt vector
will be output on 00-07 reflecting the source
of the interrupt. The interrupt source can,
also be read from an Interrupt status regis'
ter.
PACKAGES
SCN2671
COMMERCIAL RANGES
VCC= 5V ±5%, TA= O"C to 7O"C
Ceramic DIP
SCN2671 AC1140
Plastic DIP
SCN2671ACI N40
Signetics
Operation Control
This functional block stores configuration
and operation commands from the CPU and
generates appropriate signals to various Internal sections to control the overall device
operation. It contains read and write circuits
to permit communications with the
microprocessor via the dats bus and contains mode registers KMR and CMR, the
command decoder, and status registers
KSR and CSR. Details of operating modes
and status information are presented in the
Operation section of this data sheet. The
register addressing is specified in table 1.
Timing
The PKCC contains a baud rste generator
(BRG) which is progrsmmable to accept external transmit or receive clocks or to divide
an external clock to perform data communications. The unit can generate 16 baud
rates, any of which can be selected for full
duplex operation. The external clock to the
baud rate generator can be applied directly
to the XTAL2 input (see figure 21) or can be
generated internally by connecting a crystal
across the XTAL I, XTAL2 input pins. The
clock input is also utilized by the keyboard
encoder section. Thus, a clock must be provided even if external transmitter and receiver clocks are used.
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
SCN2671
PIN DESIGNATION
PIN NO.
TYPE
NAME AND FUNCTION
00·07
MNEMONIC
16·19,
23-26
1/0
Data Bu.: 6-bit three-stale bidirectional data bus. All data, command and atatua transfers are
made using this bus. 00 is the least significant bit; 07 is the most significant bit.
AO-A2
31-33
I
Addre•• Line.: Used to select internal PKCC registers or commands.
lID
29
I
Read Strobe: When low, gates the selected PKCC register onto the data bus if CE Is also low.
WR
28
I
Write Strobe: When low, gates the contents of the data bus into the selected PKCC register if
CE is slso low.
CE
30
I
Chip Enable: When high, places the 00-07 output drivers in a three·state condition. If CE is
low, data transfers are enabled in conjuction with the RD and WR inputs.
INTR
22
0
Interrupt Reque.t: Several conditions may be programmed to request an interrupt to the
CPU. It is an active low open-drain output. This pin will be inactive after power on reset or a
master reset command.
INTA
27
I
Interrupt Acknowledge: Used to indicate that an interrupt request has been accepted by the
CPU. When INTA goes low, the PKCC outputs an 8·bit address vector on 00-07 corresponding
to the highest priority interrupt currently active.
XINTR
21
I
External Interrupt: An active low external interrupt input to the PKCC interrupt priority
resolver.
TxC
34
1/0
Tranamltter Clock: The function of this pin depends on bit 7 of the baud rate control register
(BRR7). if external transmitter clock is selected (BRR7 0), It Is an Input for the transmitter
clock. if internal transmitter clock is selected (BRR7
1), this pin is an output which is a
multiple of the sctual baud rate (1X, 16X) as selected by BRR5. The data is transmitted on the
falling edge of TxC. It is an input after power on and after master reset or communications
reset commands.
RxC
35
110
Receiver Clock: The function of this pin depends on BRR6. if external receiver clock is
selected (BRR6 0), it is an input for the receiver clock. If internal receiver clock Is selected
(BRR6
1), this pin is an output which is a multiple of the actual baud rate (1X, 16X) ss
selected by BRR4. The received data is sampled on the rising edge of RxC. It Is an input after
power on and after master reset or communications reset commands.
=
=
=
=
TxD
38
0
Tran8mltter Data: This output is the transmitted serial data; the least significant bit is
transmitted first. This pin is high after power on reset or a reset command that affects the
transmitter.
RxD
39
I
Receiver Data: This input is the serial data input to the receiver. The least significant bit is
received first.
36,37
I
Connections for Crystal: Provides an on-chip clock generator for the Internal baud rate
generator and the keyboard interface logic. if an external clock is provided, use XTAL2 as the
clock input. See figures 20 and 21.
XTAL1
XTAL2/BRCLK
All timing parameters such as keyboard scan time, tone frequency, and baud rate assume a
clock Input at the specified BRG input frequency. If this frequency is different, the timing
parameters will vary proportionately.
KRO-KR2
10-8
0
KCO-KC3
7-4
0
Keyboard Column Scan: Decoded externslly; selects one of 16 columns.
KRET
15
I
Key Return: An active high level indicates that the key being acanned is closed.
SHIFT
12
I
SHIFT Key: Active low input from the SHIFT key. The combination of SHIFT and CONTROL
inputs select one of four possible codes from the internal kay encoding ROM.
CONTROL
13
I
CONTROL Key: Active low Input from the CONTROL key. The combination of SHIFT and
CONTROL inputs select one of four possible codes from the internal key encoding ROM.
Keyboard Row Scan: Decoded externally; selects one of eight rows.
Signetics
2·17
2
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
SCN2671
PIN DESIGNATION (ConI.)
REPEAT
11
I
REPEAT Key: Active low input from the REPEAT key. Causes the key depression currently
active to be repeated at a rate of approximately 15 times per second.
KCLK
3
0
Keyboard Clock: High frequency (approximately 400 kHz) output used to scan capacitive
keyboards.
KDRES
2
0
Key Detect Reset: Resets the analog detector before scanning a key. Used for capacitive
keyboards.
HYS
1
0
Hysteresis Output: Sent to the analog detector for capacitive keyboard applications. A low
indicates the key currently being scanned has been recognized on previous scan cycles.
TONE
14
0
Square Wave Output: Used for tone generation.
VCC
40
I
+5V power supply.
VSS
20
I
Ground.
Receiver
The receiver accepts serial data on the RxD
pin. converts this serial input to parallel format. checks for break conditions. framing
and parity errors. and loads an "assembled"
character in the receive holding register for
acceaa by the CPU.
TransmHter
The tranamitter accepts parallel data loaded by the CPU into the transmit holding regiater and converts it to a serial bit stream
framed by the start bit. calculated parity bit
(if specified). and atop blt(a). The composIte aerial atream of data ia tranamitted on
the TxD output pin.
Keyboard Encoder
The keyboard encoder providea encoded
Table 1
scanning slgnala for a matrix keyboard. Key
depreaalona are detected on the KRET input. The debounced and verified key codes
(or matrix addreaaes) are loaded into the
key holding register for acceaa by the CPU.
Figurea 1 and 2 illuatrate the PKCC Interface
to contact and capacitive keyboarda. reapectively.
Interrupt Control
The interrupt controller unit contains a software programmable interrupt maak regiater
which aelectlvely enables statua conditiona
from the keyboard encoder and communication controller to generate interrupta. The
Interrupta are priority encoded and individually generate an eight bit vector which ia
output on the data bus In responae to a CPU
interrupt acknowledge on the INTA input pin.
2671 REGISTER ADDRESSING
~
A2
A1
AO
li6/WF/
1
0
0
0
X
X
X
X
0
0
0
0
0
0
0
0
1
1m
1m. \Wi
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
0
1
0
1
1
WR
JiD
WR
JiD
JiD.WR
JiD.WR
JiD
1m
WR
\Wi
FUNCTION
Three-atate data bus
Reaet command (see table 6)
Read Interrupt status reglater (lSR)
Read/write communications mode regiatel
(CMR)
Write tranamlt holding regiater (TxHR)
Read receiver holding regiater (RxHR)
Write baud rate mode register (BRR)
Read communications status register (CSR)
Read /write interrupt mask register (IMR)
Read/write keyboard mode register (KMR)
Read keyboard holding register (KHR)
Read keyboard atatua register (KSR)
Miacellaneous commands (aee deacription)
NOTE
x - don', care.
2·18
Signetics
OPERATION
Keyboard Encoder
The keyboard is continuously scanned by
KCO-KC3 and KRO·KR2 which are decoded
externally to handle 128 possible keys (see
figures 1 and 2). KCO-KC3 select one of 16
columns and KRO-KR2 multiplex the eight
row return lines into the KRET pin.
Debouncing is accomplished by remembering a 1 state at the KRET pin when a key is
being addressed and verifying it one scan
later. Once the key is verified, a key code is
loaded into the keyboard data register
(KDR). If the keyboard holding register
(KHR) is empty, the contents of the KDR will
be transferred to the KHR immediately; if the
KHR is full (i.e., the CPU has not read the
previous key code), the transfer will be held
off until the KHR is read. The data transfer to
the KHR causes keyboard data ready
(KRDY) to be set in the keyboard status
register.
For capacitive keyboards, the high frequency output KCLK can be used to gate the
column scsn to the keyboard (see figure 2).
The key detector reset (KDRES) output
resets the analog detector prior to scanning
each key location. The output from the analog multiplexer is sensed and then latched in
the analog detector. The HYS output controls the sense level. A 0 will lower the
sense level causing hysteresis, and a 1 will
raise the sense level with no hysteresis.
The REPEAT input enables the keyboard
logic to recognize any key repeatedly. 15
times per second. Additionally, certain keys
can be programmed to repeat automatically
if depressed for more than one-half second.
A square wave is output on the TONE pin
when the CPU issues a ring tone command
to the PKCC.
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
SCN2671
BLOCK DIAGRAM
DATA
::t
DBO-DB7
K
BUS BUFFER
KEYBOARD ENCODER
2
KCLK
t
OPERATION CONTROL
iiii
I-
KMR
CE
1
f-----
CMR
WR
~ KCO-KC3
KEYBOARD
SCANNER &
ENCODERI
CSR
KSR
AO-A2 )
I
COMMAND DECODER
INTERUPT CONTROL
&
iNTA
I
) KRO-KR2
-
r------i
-
I
!·------i
G
KEYBOARD
DATA
REGISTER
!
I
I
Vee ----.
GNO~
TIMING
TxC
RxC
XTAL1/B RCLK
xTAL2
I
I
SHIFT
4)(128)(8
READ-ONLY
MEMORY
I
I
VECTOR GENERATOR
INTR
KRET
DECODER
I
x-INTR
KDRES
MODE & TIMING
CONTROL
BAUD RATE
GENERATOR
BAUD RATE
CONTROL
REGISTER
I
I
TONE
GENERATOR
I
I
TONE
~
-
TRANSMITTER
TRANSMIT
HOLDING REGISTER
>----
t
KEY HOLDING
REGISTER
TRANSMIT
SHIFT REGISTER
TxD
r
RECEIVER
INTER'i!uPTS
RECEIVE
HOLDING REGISTER
TIMING
CONTROLS
Signetics
RECEIVE
SHIFT REGISTER
RxD
2·19
MICROPROCESSOR DIVISION
JANUARY 1983
SCN2671
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
the code in the KDR Is tranaferred to the
KHR and the KRDY status bit ia set
(KSRO).
N·Key Rollover With Latched Keys: This
mode is the same as regular N·key
rollover, except that the keys which are
assigned to row 0 of the keyboard matrix
(KR2·KRO = 000) produce a code both
when depressed and when released. The
codes are independent of the states of
the Inputs at SHIFT and CONTROL. If one
or more of the latched keys are de·
pressed when the keyboard is enabled
(after a keyboard reset), the corre·
sponding codes will be sent out as the
keys are scanned and debounced. Note
that simultaneous letched keys will not
set KERR (KSR1) and that latched keys
will not be auto·repeat and will not be
affected by the REPEAT input.
KRET
)I
KR2-KRO
DIGITAL MULTIPLEXER
8 ROWS
I
PKCC
16
10F16
DECODE COLUMNS
KC3-KCO
-
~
CONTACT
KEYBOARD
MATRIX
Figure 1. Contact Keyboard Interface
Two·Key Rollover: The first key code Is
loaded into the KDR immediately and the
second code Is loeded only after the first
key Is released. Simultaneous keys will
set KERR (KSR1). If three or more keys
remain closed at any given time, the
KERR bit will also be set. All keys must
then be released before the next KRET
will be processed.
ANALOG
DETECTOR
KRET
~
HYs
KDRES
KR2-KRO
)f
ANALOG MULTIPLEXER
I
8 ROWS
PKCC
roo-KCLK
10F16
DECODE
KC3-KCO
'---
16 COLUMNS
hCAPACITIVE
KEYBOARD
MATRIX
Two·Key Inhibit: All keys must be reo
leased between keystrokes; otherwise,
KERR (KSR1) will be set.
Bit KMR4 specifies the key encoding mode.
Each key is assigned four a·bit codes, cor·
responding to the states of the SHIFT and
CONTROL inputs. If the encoded mode Is
programmed, the row / column address of
the detected key is used to load one of the
four key codes into the KDR. See table 2 for
key code assignments. If the non·encoded
mode is programmed, the row/column ad·
dress is loaded directly into the KDR with
the following format:
Figure 2. Capacitive Keyboard Interface
KDR
Keyboard Mode Register
Operating modes are selected by program·
ming the keyboard mode register (KMR),
whose format is illustrated in figure 3.
Bit KMR7 is used for testing the device. For
normal operation, this bit should always be
written to a O.
2·20
Bits KMR6·KMR5 select the rollover modes
for keyboard processing:
N-key Rollover: In this mode, the code
corresponding to each key depression ia
loaded into the KDR ss soon as that key
is debounced, independent of the reo
lease of other keys. Two or more clo·
sures occurring within one scan cycle
are considered to be simultaneous,
which will set keyboard error in the key·
board status register (KSR 1). As soon as
the keyboard holding register is empty,
Signetics
o-LL
KC3, KC2, KC1, KCO
"0" for momentary keys
"1" for latched keys release
"0" for latched keys depress
MICROPROCESSOR DIVISION
SCN2671
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
Table 2
STANDARD KEY CODES (HEX)
ROW (KR2-KRO)
COLUMN
(KC3-KCO)
0
1
2
3
4
5
6
7
8
9
A
B
C
0
E
F
0
2
1
3
EO
FO
EO
FO
CO
DO
CO
DO
IB
IB
IB
IB
ESC
ESC
ESC
ESC
09
09
09
09
EI
FI
EI
FI
CI
01
CI
01
21
31
21
31
I
11
11
51
71
E2
F2
E2
F2
C2
02
C2
02
22
32
22
32
"
2
"2
E3
F3
E3
F3
C3
03
C3
03
23
33
23
33
#
E4
F4
E.
F4
C4
04
C4
04
2.
34
24
34
$
E5
F5
E5
F5
C5
05
C5
05
25
35
25
35
%
E6
F6
E6
F6
C6
06
C6
06
26
36
26
36
&
E7
F7
E7
F7
C7
07
C7
07
27
37
27
37
E8
F8
E8
F8
C8
08
C8
08
28
38
28
38
(
E9
F9
E9
F9
C9
09
C9
09
29
39
29
39
)
EA
FA
EA
FA
CA
DA
CA
DA
37
37
37
37
EB
FB
EB
FB
CB
DB
CB
DB
EC
FC
EC
FC
S
4
2B
3B
2B
3B
18
18
58
78
CAN
CAN
X
3D
20
3D
20
-
-
2A
3A
2A
3A
0
ETX
ETX
C
IF
IF
7F
5F
US
US
s
03
03
43
63
EDT
EDT
0
d
16
16
56
76
SYN
SYN
V
e
04
04
44
64
DC2
DC2
A
r
06
06
46
66
ACK
ACK
F
f
02
02
42
62
I.
I.
54
74
DC4
DC4
T
t
07
07
47
67
BEL
BEL
G
9
DE
DE
4E
6E
19
19
59
79
EM
EM
Y
y
08
08
48
68
BS
BS
H
h
00
00
40
60
15
15
55
75
NAK
NAK
U
OA
OA
4A
6A
LF
LF
J
j
3C
2C
3C
2C
09
09
49
69
HT
HT
I
DB
DB
4B
6B
VT
VT
K
k
3E
2E
3E
2E
SI
SI
9
OF
OF
4F
6F
DC
DC
4C
8C
FF
FF
L
I
3F
2F
3F
2F
7
7
7
7
34
34
34
34
4
••
4
31
31
31
31
1
1
1
1
30
30
30
30
38
38
38
38
8
8
8
8
35
35
35
35
5
5
5
5
32
32
32
32
2
2
2
2
CC
DC
CC
DC
39
39
39
39
9
9
9
9
36
36
36
36
6
6
6
6
33
33
33
33
3
3
3
3
ED
FD
ED
FD
CD
DO
CD
DO
90
90
90
90
93
93
93
93
82
82
82
82
EE
FE
EE
FE
CE
DE
CE
DE
91
91
91
91
80
80
80
80
EF
FF
EF
FF
CF
OF
CF
OF
92
92
92
92
I
~ Thl. row contain. tho latchod
keys when that mode is selected
(KMR6_ KMRS = 00).
I
IA
IA
5A
7A
DCI
DCI
D
q
01
01
41
81
SOH
SOH
A
17
17
ETB
ETB
57
77
W
13
13
53
73
DC3
DC3
S
05
05
45
65
END
END
E
12
12
52
72
+
;
+;
0
0
0
0
I
US
US
US
US
7
30
30
30
30
1
IF
IF
IF
IF
6
SUB
SUB
Z
1
HT
HT
o HT
o HT
a
,
x
=
0_
:
IE
IE
7E
5E
AS
AS
FS
FS
v
IC
IC
7C
5C
\
IB
IB
7B
58
STX
STX
B
b
08
08
08
08
BS
BS
o BS
o BS
10
10
70
50
GS
GS
SO
SO
N
10
10
50
70
OLE
OLE
P
p
08
08
08
08
BS
BS
BS
o BS
00
00
60
40
NUL
NUL
@
09
09
09
09
o HT
o HT
<
<
7F
7F
7F
7F
DEL
DEL
DEL
DEL
20
20
20
20
>
>
OA
OA
OA
OA
LF
LF
LF
LF
DB
DB
DB
DB
o VT
o VT
?
/
00
00
00
00
CA
CA
CA
CA
OA
OA
OA
OA
o LF
o LF
0
0
0
0
AD
BO
AD
BO
A6
B6
A6
B6
2E
2E
2E
2E
AI
BI
AI
BI
A7
B7
A7
B7
BF
AF
9F
8F
A2
B2
A2
B2
A8
B8
A8
B8
95
95
95
95
A3
B3
A3
B3
84
84
84
84
81
81
81
81
A4
B4
94
94
94
94
83
83
83
83
96
96
96
96
~"""t:
XX
XX
XX
XX
3
#
3
4
$
4
5
%
5
6
&
6
7
7
8
(
8
9
)
(Pin 13 = 0)
Kay cod•• in hox
w
"
I
0
0
0
0
~
Signetics
0
0
0
0
..
yyy
yyy
yyy
yyy
tV
c
"
CA
CA
M
m
/
?
'"
+
:
0
0
A9
B9
A9
B9
0
A4
0
B.
AA
BA
AA
BA
A5
B5
A5
B5
AB
BB
AB
BB
I
0
0
0
2
:
0
• DEL
0
-
ESC
ESC
{
[
I
1
HT
HT
SP
SP
o SP
o SP
VT
VT
LF
LF
0
0
0
0
0
0
SHIFT (Pin 12 = 0)
~ Latched key code fo r
~
relesse
Latched key code for depres
ASCII equivalent (if any)
lL--______ . Indicates Auto-Repeat keys
2·21
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
KMR
T
SCN2671
I I I I I I I I I
7
~
'o"m,'o
1 = Enable
0= Disable
6
5
4
2
3
1
0
~
L
Tone select
0= 1kHz
1 = 2kHz
Rollover modes
00 = N·key with
latched keys
01 = N-Key
10 = Two key
11 = Two key
inhibit
KMR2
KMR1
Key
MATRIX
SIZE
0
0
1
1
0
1
0
1
128
128
80
80
SCAN
TIME
10ms
2.5ms
6Ams
1.6ms
Auto repeat
0= Disable
1 = Enable
a = Encoded
keyboard
1 = Non encoded
keyboard
Figure 3. Keyboard Mode Register Format
Bit KMR3 enables the auto-repeat mode. In
this mode, if a key that is programmed for
auto-repeat is depressed for longer than
one-half second, the key code will be loaded into the KDR approximately 15 times per
second until that key is released. Only the
non-control key codes will auto-repeat, i.e.
CONTROL = 1. Table 2 specifies the autorepeat keys.
KMR2 and KMR 1 select the key matrix size
and debounce time (scan rate). The keyboard row outputs (KR2, KR1, KRO) always
scan from 0 to 7. The column outputs (KC3,
KC2, KC 1, KCO) scan from 0 to 15 for a 128
key mstrix and from 0 to 9 for an 80 key
matrix.
sample. The status bits are the complements of the input levels.
interrupt and is cleared by the reset command with 02 = 1.
KSR5 reflects the state of the internal shift
lock flag which is controlled by the
set! reset shift lock commands.
Keyboard error (KSR 1) is set when the operator depresses more keys than are allowed
in the selected rollover mode, or when keys
are depressed simultaneously (within one
scan cycle). This bit can be specified (by
IMR3) to generate an interrupt and is
cleared by the reset command with 01 = 1.
KSR3 indicates that the keyboard controller
is enabled. It is controlled by the set! clear
keyboard enable command.
Keyboard overrun (KSR2) is set when both
the KHR and KDR are full and a third key is
validated. The original content of the KHR is
preserved and the content of the KDR is
overwritten with the new key code. This bit
can be specified (by IMR 1) to generate an
KMRO selects between a 1kHz and 2kHz frequency to be output on the TONE pin in response to a ring tone command.
Keyboard Status Register
The keyboard status register (KSR) provides operational feedback to the CPU. Its
format is illustrated in figure 4.
KSR7, 6 and 4 reflect the state of the inputs
at the corresponding pins. CONTROL and
SHIFT are latched at the time the key is
accepted. As the verified codes are loaded
into the KDR, the corresponding states of
CONTROL and SHIFT are loaded into the
KSR. REPEAT is updated on every matrix
2·22
KSR
7
I I
6
5
4
CONTROL~~
I
SHIFT-
Keyboard data ready (KSRO) is set when
the key code or address is transferred from
the KOR to the KHR. This bit can be specified (by IMR2) to generate an interrupt. It is
cleared when the CPU reads the KHR.
3
2
11
I I
a
LKRDY
~
LKERR
KOVR
SHIFT LOCK
REPEAT
------------------~
'-------------- Keyboard Enabled
Figure 4. Keyboard Status Register Format
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
Communications Controller
The communications controller section of
the PKCC comprises a full duplex asynchronous receiver /transmitter (UART) with a
baud rate generator. Registers associated
with these elements are the communications mode register (CMR), the baud rate
control register (BRR), and the communications status register (CSR).
Receiver
The receiver accepts serial data on the RxD
pin, converts the serial input to parallel format, checks for start bit, stop bit, parity bit
(if any), or break condition, and presents the
assembled character to the CPU. The receiver looks for a high to low (mark to
space) transition of the start bit on the RxD
input pin. If a transition is detected, the state
olthe RxD pin is sampled again after a delay
of one half of the bit time. If RxD is then high,
the start bit is invalid and the search for a
valid start bit begins again. If RxD is still low,
a valid start bit is assumed and the receiver
continues to sample the input at one bit time
intervals at the theoretical center of the bit,
until the proper number of data bits and the
parity bit (if any) have been assembled, and
one stop bit has been detected. The least
significant bit is received first. The data is
then transferred to the receive holding register (RxHR) and the RxRDY bit in the CSR is
set to a 1. If the character length is less than
eight bits, the most significant unused bits in
the RxHR are set to zero.
After the stop bit is detected, the receiver
will immediately look for the next start bit.
However, if a non-zero character was received without a stop bit (I.e. framing error)
and RxD remains low for one half of the bit
period after the stop bit was sampled, then
the space is interpreted as a start bit.
The parity error, framing error and overrun
error (if any) are strobed into the CSR at the
received character boundary. If a break condition is detected (RxD is low for the entire
character including the stop bit) only one
character consisting of all zeros will be
transferred to the RxHR and the received
break bit in the CSR is set to 1 (RxRDY is not
set when a break is received ). The RxD
input must return to a high condition for one
bit time before a search for the next start bit
begins.
sent first. Following the transmission of the
stop bits, if a new character is not available
in the transmit holding register (TxHR), the
TxD output remains high and the TxEMT bit
in the CSR will be set to 1. Transmission
resumes and the TxEMT bit is cleared when
the CPU loads a new character into the
TxHR. The transmitter can be forced to send
a continous low condition by a transmit
break command.
If the transmitter is disabled, it continues
operating until the character currently being
transmitted is completely sent out.
Communication Mode Register
Figure 5 illustrates the bit format of the
CMR, which controls the operational mode
of the communications controller and the
character parameters.
Bits CMR1-CMRO select a character length
of 5, 6, 7, or 8 bits. The character length
does not include the parity, start, or stop
bits.
CMR2 selects the transmitted character
framing as one or two stop bits. The receiver
always checks for one stop bit.
The parity format is selected by bits CMR4
and CMR3. If parity or force parity is selected, a parity bit is added to the transmitted
character and the receiver performs a parity
check on incoming data. CMR5 selects odd
or even parity and determines the polarity of
the parity bit in the force parity mode.
The bits in the mode register affecting character assembly and disassembly (CMR5CMRO) can be changed dynamically and affect the characters currently being assembled in RxSR and transmitted by TxSR. To
CMRI
7
affect assembly of a received character, the
CMR must be updated within n -1 bit times
of the receipt of that character's start bit. To
affect a transmitted character, the CMR
must be updated within n -1 bit times of
transmitting that character's start bit. (n =
the smaller of the new and old character
lengths).
The UART can operate in one of four modes,
as illustrated in figure 6. The operating
modes are selected by bits CMR7 and
CMRS, which should only be changed when
both the transmitter and receiver are disabled. CMR7-CMRS
00 is the normal
mode, with the transmitter and receiver operating independently. CMR7-CMRS = 01
places the UART in the automatic echo
mode, which automatically retransmits the
received data. The following conditions are
true while in automatic echo mode:
1. Data assembled by the receiver Is automatically placed in the transmit holding
register and retransmitted on the TxD
output.
2. The receive clock is used for the transmitter.
3. The receiver must be enabled, but the
transmitter need not be enabled.
4. Status bit TxRDY is not set. TxEMT operates normally.
5. The received parity Is checked, but Is not
regenerated for tranamission, i.e., transmitted parity bit is as received.
S. Only the first character of a break condition is echoed; the TxD output will go high
until the next received character is assembled.
7. CPU to receiver communication continues normally, but the CPU to transmitter
link is disabled.
=
I I I I I I I I
6
'-v---'
~
Operating mode
00 = Normal
01 = Auto echo
10 = Local loop back
11 = Remote loopback
Parity
o = Odd !force 0
1 = Even/force 1
5
4
3
'-v---'
2
1
0
'--v-'
LCharacter length
00 = 6
01 = 5
10 = S
11 = 7
o = Two stop bits
1 = One stop bit
Parity mode
00 = With parity
01 = Force parity
10 = No parity
11 = Not allowed
Transmitter
The transmitter accepts parallel data from
the CPU and converts it to a serial bit stream
on the TxD output pin. It automatically sends
a start bit followed by the data bits, an optional parity bit, and the programmed number of stop bits. The least significant bit is
SCN2671
Figure 5. Communications Mode Register Format
Signetics
2·23
2
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
SCN2671
Two diagnoatic modes can also be
configured. In local loopback mode (CMR7CMR6 = 10):
1. The transmitter output is internally connected to the receiver input.
2. The transmit clock is used for the receiver.
3. The TxD output Is held high.
4. The RxD input is ignored.
5. The transmitter must be enabled, but the
receiver need not be enabled.
6. CPU to transmitter and receiver communications continue normally.
(8)
The second diagnostic mode is the remote
loopback mode (CMR7-CMR6
11). In this
mode:
=
1. Data assembled by the receiver is automatically placed in the transmit holding
register and retransmitted on the TxD
output.
2. The receive clock is used for the transmitter.
3. No data is sent to the local CPU, but the
error status conditions (parity and framing) are set if required.
4. The received parity is checked, but is not
regenerated for transmission, i.e., transmitted parity bit is as received.
5. The receiver must be enabled, but the
transmitter need not be enabled.
(b)
Baud Rate Control Register
The baud rate control register (BRR) controls the frequency generated by the baud
rate generator (BRG) and the clock source
used by the receiver and transmitter. Its format is illustrated in figure 7.
(e)
BRR3-BRRO select one of sixteen frequencies to be generated by the BRG. See table
3.
BRR7 and BRR6 select the source of the
transmit and receive clocks. If external
clocks are chosen, (BRR7 = 0 or BRR6 =
0), then the clock rate factor is determined
by BRR5 and BRR4. The external clock input(s) should be the desired baud rate multiplied by the clock rate factor.
(d)
(a) Normal operating mode.
(b) Automatic echo mode.
(e) Local loopback mode.
(d) Remote loopback mode.
Figure 6. Operating Modes of the 2671 UART
2·24
Signetics
If internal clock(s) are specified, (BRR7 = 1
or BRR6 = 1). the clock Is supplied by the
internal bsud rate generator at the selected
baud rste. The clock rate factor for internally genersted clocks is always 16. Pins 35
and 34 become outputs for transmit or receive clocks, respectively. See table 4 for
the description and selection of these outputs.
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
tJ
SCN2671
BRR
Tx Clock source
0: External
1 : Internal (BRG)
Rx Clock source
o : External
1 : Internal (BRG)
2
'-v-'~--~
Baud rate select-See table 3
I
Clock rate factor for external
clocks
00: l6X
01 : 32X
10 : 64X
11: 1X
For internal clocks these
bits specify the output
frequency on pin 34 and
pin 35. See table 4.
Figure 7. Baud Rate Control Register Format
Table 3
BAUD RATE GENERATOR CHARACTERISTICS (BRCLK=4.9152MHz)
BRR3-0
BAUD
RATE
ACTUAL
FREQUENCY
16X CLOCK
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
50
110
134.5
150
200
300
600
1050
1200
1800
2000
2400
4800
9600
19200
38400
0.8
kHz
1.7598
2.152
2.4
3.2
4.8
9.6
16.8329
19.2
28.7438
31.9168
38.4
76.8
153.6
307.2
614.4
Signetics
PERCENT
ERROR
-0.01
-
+0.20
-0.20
-0.26
-
-
DIVISOR
6144
2793
2284
2048
1536
1024
512
292
256
171
154
128
64
32
16
8
2·25
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
Table 4
SCN2671
BAUD RATE CONTROL REGISTER
CLOCK SOURCE
BRR7BRR4
TxC
00"
01"
10"
1100
1101
1110
1111
E
E
I
I
I
I
I
PIN FUNCTIONS
RxC
PIN
34
PIN
35
BRR3-BRRO
BAUD RATE SELECTION
E
I
E
I
I
I
I
TxC
TxC
16X
lX
lX
16X
16X
RxC
lX
RxC
lX
16X
IX
16X
The baud rates are
listed in table 3.
NOTES
1. •• = Clock rate factor for external clocks: 00 = leX
01 - 32X
10·64X
11 - IX
2. E .. External clock.
3. I
= Internal clock (BRG).
4. 1X and leX are clock outputs at 1 or 18 time, the actual baud rate. For receive. the 1X output i8 the actual data sample clock.
5. BRR7-BRRB
= 01 or 10 not permiHed in automatic echo or remoteloopback modes unlaas BRR5-BRR4 -
Communications Status Register
Figure a illustrates the bit format of the com·
munications status register (CSR), which
provides UART status to the CPU.
Receiver ready (CSRO) indicates that are·
ceived character is assembled and transferred to the RxHR and is ready to be read
by the CPU. This bit can be specified (by
IMRO) to generate an interrupt and is reset
by reading the RxHR.
Transmitter ready (CSR 1) indicates that the
TxHR is empty and ready to be losded with a
character. This bit will be cleared when the
TxHR is loaded and has not yet transferred
the character to the transmit shift register
(TxSR). TxROY is reset when the transmitter
is disabled. It will be set when the transmitter is enabled, provided that no data was
loaded into the TxHR during the time the
transmitter was disabled. This bit can be
specified (by IMRl) to generate an interrupt.
Transmitter empty (CSR2) indicates that the
transmitter has underrun, i.e., both the TxHR
and TxSR are empty. This bit can only be set
after transmission of at least one character,
and is cleared when the TxHR is loaded by
the CPU. TxEMT is reset when the transmitter is disabled. This bit can be specified (by
IMR6) to generate an interrupt.
CSR3 will be set when the PKCC receives a
command to transmit a break. This bit will be
cleared after the break is completed.
Received break (CSR4) indicates that an all
zero character of the programmed length
has been received without a stop bit. Breaks
originating in the middle of a received character can be detected. This bit is cleared
2·26
00.
when RxO returns to a high state for at least
one bit time.
tus register (ISR) which can be enabled to
generate an active low Interrupt request on
the INTR output. The eight interrupt conditions in the ISR are individually enabled by
writing a 1 into the corresponding bit of the
interrupt mask register (lMR).
Receiver overrun (CSR5) indicates that the
previous character in the RxHR has not been
read by the CPU and that a new character
has been loaded into the RxHR. This bit is
cleared by a reset command with 03.~ 1.
Framing error (CSR6) indicates that the
stop bit has not been detected. The stop bit
check is made in the middle of the first stop
bit position. This bit is cleared by a reset
command with 03 ~ 1.
Parity error (CSR7) indicates that a character was received with incorrect parity when
'with parity' or 'force parity' is enabled. This
bit is cleared by a reset command with 03 ~
1.
Interrupt Controller
The 2671 contains a maskable interrupt sta-
CSR
7
6
5
'"'' ."~~ I
FramlngerrOr~
4
Each of the interrupt conditions is assigned
a priority and a vector. When an enabled ISR
bit is set, ths 2671 asserts the INTR output.
If the CPU activates the INTA input, the 2671
responds by placing the corresponding a-bit
vector on the dsta bus (07-00). If multiple
interrupts are pending, the vector corresponds to the condition with the highest priority. The interrupt will persist until all pending interrupt conditions are cleared.
The ISR can also be polled by reading at
address A2-AO ~ 000. All pending interrupt
conditions which are enabled by the IMR will
be read independent of priority.
3
LRXRDY
~
LTXROY
Overrun error
TxEMT
Received break
Transmit break
Figure 8. Communications Status Register Format
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
The bit assignments of the ISR and IMR and
corresponding vectors and priorities are
listed in table 5.
COMMANDS
In addition to the control exercised by programming of the PKCC control registers,
several functions can be performed by executing command operations. There are two
classes of commands which are initiated by
writing to the 2671 at address A2-AO = 000
(reset command) and address A2-AO = 111
(miscellaneous commands). Individual commands are specified by the bit pattern on the
data bus (07-00).
Reset Commands
The reset command bit format is illustrated
in figure 9 and the detail command descriptions are given in table 6.
TABLE 5
A reset command with 07-00 = l11XXXX1
is a master reset for the 2671. This command must be given following a power on
condition to release the internal power on
reset latch which deactivates the 2671 on
power up.
Miscellaneous Commands
The miscellaneous command format is illustrated in figure 10.
The transmit break commands force a break
(steady low output) on the TxO pin immediately or after the character in the TxSR (if
any) is transmitted. A timed break lasts for
approximately 200ms, and a character
break lasts for one character time including
parity and stop bit time. In either case,
TxROY (CSR1) will be set at the beginning of
SCN2671
the break which can be extended indefinitely (by 200ms or one character time increments) by reasserting the command in response to TxROY. Note that these
commands reset TxROY. When a transmit
break command is asserted, CSR3 will be
set. This bit will be cleared after the break is
completed.
The ring tone commands cause the tone
generator to output a square wave on the
TONE output. The tone durations are specified by the commands:
Ring tone short = 25ms
Ring tone long = 100ms
The tone frequency is either 1kHz or 2kHz,
as specified by KMRO.
INTERRUPT MASK REGISTER (IMR) AND INTERRUPT STATUS REGISTER (ISR)
BIT IN
IMR/ISR
IMROIISRO
IMR1/1SR1
IMR211SR2
IMR311SR3
IMR411SR4
IMR5/1SR5
IMR611SR6
IMR711SR7
INTERRUPT
CONDITION
VECTOR ON 07-00
ttEX
BINARY
I
PRIORITY
RxROY
KOVR
KROY
KERR
XINTI
.1BREAK2
TxEMT
TxRDY
1
2
3
4
5
6
7
6
11001111
11010111
11011111
11100111
11101111
11110111
11000111
11000111
NOTES:
II
I
I
I
I
CF
07
OF
E7
EF
F7
C7
C7
CONDITION RESET BY:
Read RxHR
Reset CMO (02 = 1)
Read KHR
Reset CMD (01 = 1)
External
Reset CMO (04 = 1)
Load TxHR
Load TxHR
1. XINT is an Input from an external interrupt source, active low (pin 21).
2. 4BREAK reters to the change of a received break condition.
4
3
'--v-----'
OOX
No effect _ _ _ _ _ _...JI
010
011
100
101
110
111
Set RxE
Reset RxE
Set TxE
Reset TxE
Set TxE and RxE
Communications reset
Break detect change reset
Keyboard reset
KERR reset
' - - - - - - - - KOVR reset
' - - - - - - - - - Communications error reset
Figure 9. Reset Command Format
Signetics
2-27
2
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
Table 6
SCN2671
RESET COMMAND DESCRIPTION
COMMAND
RESETS
COMMENTS
Keyboard reset
KMR7-KMRO
KSR5, KSR3-KSRO
IMR3-IMRI
The keyboard controller is reset, ignoring the input at
KRET.
KERR reset
KSRI
Keyboard error status bit reset.
KOVR reset
KSR2
Keyboard overrun status bit reset.
Communications error reset
CSR7-CSR5
Resets the receiver overrun, parity, and framing error
status bits.
Break detect changa reset
ISR5
Resets the break detect change bit in the interrupt status register.
Set RxE
See note.
Enables receiver operation.
Reset RxE
CSR7-CSR4, CSRO
See note.
Disables the receiver.
Set TxE
See note.
Enables transmitter operation.
Reset TxE
CSR3-CSRI
See note.
Disables the transmitter. Sets the TxD output to a 1 after
transmitting the character in TxSR.
Communications reset
CMR, CSR, BRR,
TxE, RxE, IMR7-IMR5, IMRO
Resets the communication controller. The RxD input is
ignored and the TxD output is seUo a 1.
Master reset
CMR, CSR, BRR,
TxE, RxE, KMR,
KSR5, KSR3-KSRO,
IMR7-IMRO.
Releases the internally latched power on reset.
Resets the keyboard and communication controllers. Inputs at KRET and RxD are ignored and the TxD output is
set to a 1.
NOTE
Command does not affect the CMR or the BRR.
command, and the current state of the keyboard (key depressions and latched key
states) is preserved internally. When the
keyboard is subsequently enabled, key
processing resumes, old and new keys are
debounced, and latched keys are encoded if
there has been a change in their state.
The sell clear shift lock commands control
the state of the internal shift lock flip flop.
When shifllock is set, the keyboard controller encodes all key depressions as if the
SHIFT input was asserted. The state of the
shift lock flip flop is reflected in KSR5.
The set keyboard enable command enables
the keyboard controller and sets KSR3 in
the keyboard status register. The clear keyboard enable command resets KSR3 and
disables key processing at the KRET input.
The keyboard controller is not reset by this
MASK PROGRAMMABLE OPTIONS
Characteristics of certain portions of the
PKCC are internally programmed by means
of a read only memory. The items which can
be programmed are:
7
C,"" . " " " ,
6
Consult your local Signatics representative
for costs, minimum quantities, and data submission requirements for customized versions of the PKCC.
o
5
'""~
II L,..",m;"'".."" ,,,••
L
Set keyboard enable
Transmit timed break
Clear shift lock - - - - - - - - - - - - '
Ring tone short
Set shifllock _ _ _ _ _ _ _ _ _ _ _...J
' - - - - - - - - - Ring tone long
Figure 10. Miscellaneous Commands Format
2-28
• Key codes
• Auto-repeat keys
• Scan times, tone frequency, and tone
duration
• Baud rates
• Interrupt vectors
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
SCN2671
ABSOLUTE MAXIMUM RATINGS 1
RATING
UNIT
Oto +70
-65 to +150
-0.5 to +6.0
·C
·C
V
PARAMETER
Operating ambient temperature 2
Storage temperature
All voltages with respect to ground 3
DC ELECTRICAL CHARACTERISTICS
PARAMETER
V1l
V1H
VOL
VOH
III
III
Icc
TA = O·C to
Vee=5V ± 5% 4,5,6
LIMITS
TEST CONDITIONS
Min
Typ
Unit
Max
V
0.8
Input low voltage
Input high voltage
XTAL1, XTAL2
All other inputs
Output low voltage
Output high voltage (except INTR)
Input leakage current
XTAL2/BRCLK
All other inputs
Data bus 3·state leakage current
Power supply current
AC ELECTRICAL CHARACTERISTICS
+ lO·C,
2
V
V
V
V
4.0
2.0
IOl = 1.6mA
IOH= -100"A
V1N=0 to Vee
0.4
2.4
-100
TA=O· to
+ 70·C,
"A
"A
10
10
150
-10
-10
Vo=O to Vee
p.A
rnA
Vee=5V ± 5%4,5,6
LIMITS
PARAMETER
TEST CONDITIONS
Read timing 1
Address setup to RD
CE setup to RD
RD pulse width
Address hold from RD
CE hold from RD
Data delay for read
Data bus floating
time for read
Access delay from any
tAD
read to next read or write
Min
Typ
Max
50
50
250
20
0
tAS
tcs
tpw
tAH
tCH
too
tDF
CL = 150pF
CL = 150pF
Write timing 8
Address setup to WR
tAS
CE setup to WR
tcs
WR pulse width
tpw
Address hold from WR
tAH
CE hold from WR
tCH
Data setup
tDS
Data hold
tDH
Access delay from any
tAD
write to next read
or write
Access delay from reset
tAD
command to next read
or write
NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is stress rating only and functional operation of the device
at these or a1 any other condition above those indicated in the operation section of this
specification is not implied.
2. For operating at elevated temperatures. the device must be derated baaed on + 150°C
maximum junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal
devices from damaging effects of excessive static charge. Nonetheless, it is 8uggest·
ed that conventional precautions be taken to avoid applying any voltages larger than
the rated maxima.
10
UNIT
200
ns
ns
ns
ns
ns
ns
100
ns
250
ns
50
50
250
20
0
100
10
ns
ns
ns
ns
ns
ns
ns
250
ns
1.0
f.ts
4. Parameters are valid over operating temperature range unless otherwise specified.
5. All voltage measurements are referenced to ground (VSS). All input signals swing
between 0.4V and 2.4V with a transition time of 20n8 maximum and time measurements
are referenced at input voltages of O.8V, 2.0V and at output voltages of o.av, 2.0V as
appropriate, unless otherwise specified.
6. Typical values are at +25°C, typical supply voltages and typical processing paramo
eters.
7. See figure 11.
8. See figure 12.
Signetics
2·29
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
AC ELECTRICAL CHARACTERISTICS
SCN2671
(Con!.)
LIMITS
PARAMETER
Interrupt acknowledge timing 9
INTA pulse width
tpWI
Data delay time for
tOOl
interrupt vector
Data bus floating
tDFI
time after INTA
INTAto INTA
tADI
access delay
TEST CONDITIONS
Min
Typ
300
CL
= 150pF
CL
= 150pF
10
fR/T
TxC or RxC input frequency
tR/TH
tR/TL
TxC or RxC clock high
TxC or RxC clock low
ns
100
ns
ns
400
400
ns
ns
450
400
300
ns
ns
ns
409
kHz
12.0
55.0
CL
CL
CL
CL
I's
I's
20
80
= 150pF
= 150pF
= 150pF
= 150pF
I's
I'S
400
400
600
400
200
200
CL
= 150pF
CL
= 150pF
Clock rate factor
= 16X, 32X, 64X
Clock rate factor
= IX
350
350
Signetics
ns
ns
ns
ns
ns
ns
300
ns
5.075
ns
ns
ns
MHz
1.3
MHz
1.0
MHz
ns
ns
0
70
70
1.0
NOTES
9. See figure 13.
10. See figure 14.
11. See figure 16 and 16.
12. See figure 17" 18, and 19.
13. See figures 20 and 21 for XTAL1, XTAl2 connections for driving XTAL2 with an
external clock. Input levels for XTAL 1 and XTAl2 are VIL .::s; a.BV, VIH ~ 4.0V, and
teRl and teRH are measured at these levels.
2·30
250
300
Keyboard timing 11
KCLK frequency
fKCLK
KRi, KCi to KRET sample delay:
tKBD
FAST SCAN
SLOW SCAN
Scan time per matrix position:
tpos
FAST SCAN
SLOW SCAN
KDRES delay from KCLK
tKRD
KDRES hold from KCLK
tKRH
HYS delay from KCLK
tHYSD
KRi, KCi delay from KCLK
tRCD
UNIT
ns
INTR reset timing 10
INTR delay from:
tRI
Read RxHR (RxRDY)
Read KHR (KRDY)
Reset commands
(KOVR,KERR,BREAK)
Load TxHR (TxEMT,TxRDY)
Mask bit reset
UART timing 12
RxD setup time
tRXS
RxD hold time
tRxH
TxD delay from falling
tTxD
edge of TxC
Skew between TxD transition
Ircs
and falling edge of TxC output
XTAL 1 clock high 13
tBRH
XTAL 1 clock low 13
tBRL
BRG input frequency
fBRG
TxC or RxC input frequency
fR/T
Max
4.9152
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
SCN2671
2
A2-AO
AD
--"":""""='I.-I.---, pw ---:2t~~===-:::====::::j
·AD----+l'
.00=1""-..;.:......;;.;.,~_ _ _ _ _ _ _ _ _ __
07-00
Figure 11. Read Timing
A2-AO
07-00
--Jl~----------~~
--------~(r;..-_-,~V~A~L~I;O"'_-_"~k"----------Figure 12. Write Timing
iNTA
~OO
(INTR VECTOR)
--.,.,.VI....,H~.PW=ao----- . A O I - - - - - - - < ! K V,L ~Ol ~
'OFI I--~
VALID
)1) ! . - - - - - - - -
Figure 13. Interrupt Acknowledge Timing
Signetics
2·31
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE KEYBOARD & COMM CONTROLLER (PKCC)
SC2671
VIH1(
~",l,e----
' R I - - - - ; L . , ,_ _ _ __
Figure 14. Interrupt Reset Timing
"'I·------'POS
-------1·1
KCLK
400KHz
~I "'KCLK
'KRO
KORES
mrn
-l H I-
'KRH
11..________
-:-0_ _ _ _ _ _ _ _ _ _.......
~--'~HY~S~O-----------~X~--------_--U:-'RCO
~~~:~~~ ~::~:::::::::::::::::::::::::X\.
"'1'---
'KeD
_________________
----+1·1
n..______________________
CONTRO~R&E~ESpH~=i _____________________....
SAMPLE TIME
NOTE
SCAN TIMING SHOWN IS FOR FAST SCAN (KMR1
= 1). FOR SLOW SCAN (KMR1 =O)ALL S'GNALS EXCEPT KCLK RUN AT % THE SHOWN RATES.
Figure 15. Keyboard Scan Timing
2·32
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2671
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
KRO~~~~~~~
•
1 SCAN CYCLE
2~l
KC3!
I
KEY 1
KRET
HYS
I
•
I1
KEY
2~l
KEY 2
2~~
I
KEY 1
KEY 2
KEY 1
~~l-~2~l-----I~~rl---~~'----~2~l_ _IL
--~22-l-------:.1....,222l----22jlL----....,~l
---....,222l-
2l
N-KEY ROLLOVER
...,...... MODES ONLY
"'';----------......
(~:~~----------------+'
-.;:-:::-2:;'';K;;;E'V'Yft.RO;;;L7'LO;;;V';';:E:;;'R--2 KEY INHIBIT
~--------------------,~--------------~~~~READ KHR
(KI)
(~::~-------------------------------~
~----------------,
Figure 16. Keyboard Timing
Clock
Transmit
1 BIT TIME
(1, 16, OR 64 CLOCK PERIODS) ~
TxC
(INPUT)
TxD
'TCS
TxC
(OUTPUT)
Receive
Figure 17.
Signetics
2·33
2
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
SCN2671
TxC
TxD
I I
DATA 2
DATA 1
DATA 3
TxEN
CEFOR
WRITE OF
THR
--+---. r--+--_,
r----+--------....---, ...-----------1--
TxRDY
(CSR1)
TxEMT
(CSR2)
-----------------------....1
TxD _ _ _ _- - _ , A
B CAB CAB
~~~~B~R~EA~K~1~====~==~B~R~EA~K~2~====~.r-l ~DATA3-=3
C -- D
I
TxEN
~~~-~-~&-~~----,r---+----------------~-------
COMMAND
TxRDY
(CSR1)
TRANSIT
BREAK _ _ _ _ _
~
CSR3
~i~~ ---------------------+--~--~~---....I
WRITE OF - - - - - - - - - - - - - - - - - - - ,
THR
A=START BIT
B=lstSTOPBIT
r~------~r_---------IF NO WRITE OF THR
C=2ndSTOPBIT
D=MARK
Figure 18. Transmitter Timing (5·Bit Characters, no Parity, 2 Stop Bits)
2·34
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
SCN2671
RxC
RxD---"'"
2
RxEN
R~rig~-------------+---, ~----------~-------------+-----, r----~r_------~
RHR
~~;~~
R(~~~~)N
----------.......
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - '
A
RXD---~I
BCA
BA
~1--D-AT-A-l-....,---,LI~~~DA~T~A~2~_~_ _---~~D~A~TA~3~~._ _ _ _ _ _~
RxEN
FRAMING
ERROR
(CSR6)
-------------------...1
RECEIVED
~~~~~--------------------------.......
CEFOR-------------------------------------, r---------+-RESET
COMMAND
WITH D4=1
ISR5
(BREAK----------------------------------...I
DETECT
CHANGE)
A = START BIT B = 1ST STOP BIT C = 2ND STOP BIT
Figure 19. Receiver Timing (S·Bit Characters, no Parity, 2 Stop Bits)
2671
4.9152MHz
r
L
2671
XTALI
r------I
XTAL2
Figure 20. Crystal Connections BRG Clock
XTALI
-DoO--*---~-i>:""""-I XTAL2
Figure 21. Connection for External BRG Clock Source
Signetics
2·35
MICROPROCESSOR DIVISION
PROGRAMMABLE KEYBOARD AND COMM CONTROLLER (PKCC)
Table 7
REGISTER FORMAT SUMMARY
I
I
7
1 = Enable
KMR
0= Disable
KSR
CONTROL
I
6
Test mode
00 = N-key with latched
keys
01 - N-key
10" Two keys
11 - Two key inhibit
SHIFT
CMR
BRR
CSR
IMRIISR
Reset
Command
Format
4
3
Keyboard
Auto repeat
5
Rollover modes
Operating Mode
1 = Non en- 1 = Enable
coded
SHIFT LOCK
REPEAT
Parity
00 = Normal
01 = Auto echo
10 = Localloopback
11 = Remote loopback
Tx Clock
source
Rx Clock
source
0= External
0= External
00
01
10
11
1 = Evenl
force 1
=
=
=
=
ooX =
010 =
011 =
100 =
No effect
Set RxE
Reset RxE
Set TxE
TxEMT
BREAK
CHANGE
o
1
Tone select
Key
Matrix Scan 0= 1kHz
KMR2 KMRI Size Time
0
0
128 10ms 1 = 2kHz
0
1
128 2.5ms
0
1
80 6.4ms
1
1
80
1.8ms
KOVR
KERR
Stop Bits
0= Two
With parity
Force parity
No parity
Not allowed
Clock rate factor
for external clocks
Framing error Overrun error
TxRDY
Keyboard
Ensbled
Parity Mode
0= Oddl
force 0
00" 16X
01 = 32X
1 = Internal 1 = Internal 10 = 64X
(BRG)
(BRG)
11 = IX
For Internal clocks these
bits specify the output frequency on pins 34 and 35
(table 4).
Parity error
2
0" Encoded 0= Disable
1 = One
KRDY
Character Length
00
01
10
11
=
=
=
=
8
5
6
7
Baud rate select (BRR3 - BRRO in hex)
0=50
1 = 110
2 = 134.5
3 = 150
4 = 200
5 = 300
8=600
7 = 1050
8=
9=
A=
B=
1200
1800
2000
2400
C=
D=
E=
F=
4800
9600
19200
38400
(BRCLK = 4.9152MHz)
Received
break
Transmit
break
TxEMT
TxRDY
RxRDY
XINT
KERR
KRDY
KOVR
RxRDY
KERR reset
Keyboard
reset
101 = Reset TxE
Break detect Communica- KOVR reset
110 = Set TxE and change reset tions error
RxE
reset
111 = Communications reset
Miscellaneous
Commands
Format
2·36
SCN2671
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
DESCRIPTION
FEATURES
The Signetics SCN2672 Programmable
Video Timing Controller (PVTC) is a programmable device designed for use in
CRT terminals and display systems that
employ raster scan techniques. The PVTC
generates the vertical and horizontal timing signals necessary for the display of interlaced or non-interlaced data on a CRT
monitor. It provides consecutive addressing to a user specified display buffer memory domain and controls the CPU-display
buffer interface for various buffer config·
uration modes. A variety of operating
modes, display formats, and timing profiles can be implemented by programming
the control registers in the PVTC.
A minimum CRT terminal system configuration consists of a PVTC, a SCN2671 Keyboard and Communication Controller
(PKCC), a SCN2670 Display Character and
Graphics Generator (DCSG), a SCN2670
Video and Attributes Controller (VAC), a
single chip microcomputer such as the
8048, a display buffer RAM, and a small
amount of TTL for miscellaneous address
decoding, interface, and control. Typically, the package count for a minimum
system is between 15 and 20 devices; system complexity can be enhanced by upgrading the microprocessor and expanding via the system address and data
busses.
SCN2672
PIN CONFIGURATION
4MHz and 2.7MHz character
rate versions
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Up to 256 characters per row
1 to 16 raster lines per character row
Up to 128 character rows per frame
Programmable horizontal and vertical
sync generators
Interlaced or non-Interlaced operation
Up to 16K RAM addressing for multiple
page operation
Automatic wraparound of RAM
Addressable Incrementable and
readable cursor
Programmable cursor size, pOSition,
and blink
Spilt screen and horizontal scroll capability
Light pen register
Selectable buffer Interface modes
DynamiC RAM refresh
Completely TTL compatible
Single +5 volt power supply
Power on r ••• t circuit
Vcc
A2
2
A1
AO
LPS
INTR
DADDO
DADD1
DADD2
DADD31L1
02
03
04
DADDs/LA1
05
DADII6ILA2
OIl
DADD71LA3
07
DADD81LNZ
cctK
DADD8ILPL
APPLICATIONS
BLANK
DADD101UL
•
•
•
•
HSYNC
DADD1210DD
CRT terminals
Word processing systems
Small business computers
Home Computers
DADD13/LL
GND
TOP VIEW
BLOCK DIAGRAM
I~
CE
RD
CONTROL
INITIALIZATION
AND
DISPLAY
REGISTERS
READI
WRITE
CONTROL
LOGIC
WR
-
AO-2
3
ADDRESS
DECODER
INTR
I
I
DATA
BUS
DRIVERS
00-7
8
I
II
COMMAND
DECODE
LOGIC
~
e-
DISPLAY
MEMORY
HANDSHAKE
LOGIC
CTRL1
CTRL2
CTRL3
~
DISPLAY
INTERRUPT
LOGIC
'-~
AND
STATUS
REGISTER
~
ADDRESS
TIMING
MULTIPLEXERS
CURSOR,
POINTER AND
LIGHT PEN
REGISTERS
CURSOR
AND
COMPARE
LOGIC
-
DADDO-13 I.
14
LIGHT PEN STROBE
CURSOR
Vcc
~
CCLK
CLOCK
BUFFER
HSYNC
~y
TIMING CHAIN
AND
DECODE LOGIC
TIMING
Signetics
I
VSYNC/CSYNC
BLANK
2·37
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
SCN2672
ORDERING CODE
Vcc=5V±5%, TA=O°C to 70°C
PACKAGES
Ceramic DIP
Plastic DIP
4MHz
2.7MHz
SCN2672AC4140
SCN2672AC4N40
SCN2672AC3140
SCN2672AC3N40
PIN DESIGNATION
PIN NO.
TYPE
NAME AND FUNCTION
AO-A2
MNEMONIC
37-39
I
Address LInes: Used to select PVTC internal registers for read Iwrite operations and for
commands.
00-07
8-15
110
8-Blt Bidirectional Three-State Data Bus. Bit 0 is the LSB and bit 7 is the MSB. All data,
command, and status transfers between the CPU and the PVTC takeplace over this bus.
The direction of the transfer is controlled by the RD and WR inputs when the CE input is
low. When the CE input is high, the data bus is in the three-state condition.
RD
1
I
Read Strobe: Active low input. A low on this pin while CE is low causes the contents of the
register selected by AO-A2 to be placed on the data bus. The read cycle begins on the
leading (falling) edge of RD.
WR
3
I
Write Strobe: Active low input. A low on this pin while CE is also low causes the contents
of the data bus to be transferred to the register selected by AO-A2. The transfer occurs on
the trailing (rising) edge of WR.
CE
2
I
CCLK
16
I
Chip Enable: Active low input. When low, data transfers between the CPU and the PVTC
are enabled on 00-07 as controlled by the WR, RD, and AO-A2 inputs. When CE is high,
the PVTC is effectively isolated from the data bus and 00-07 are placed in the
three-state condition.
Character Clock: Timing signal derived from the video dot clock which is used to synchro·
nize the PVTC's timing functions.
HSYNC
19
0
Horizontal Sync: Active high output which provides video horizontal sync pulses. The
timing parameters are programmable.
VSYNC/CSYNC
18
0
Vertical Sync/Composite Sync: A control bit selects either vertical or composite sync
pulses on this active high output. When CSYNC is selected, equalization pulses are
included. The timing parameters are programmable.
BLANK
17
0
Blank: This active high output defines the horizontal and vertical borders of the display.
Display control signals which are output on DADD3 thru DADO 13 are valid on the trailing
edge of BLANK.
CURSOR
7
0
Cursor Gate: This active high output becomes active for a specified number of scan lines
when the address contained in the cursor registers match the address output on DADDO
thru DADDI3. The first and last lines of the cursor and a blink option are programmable.
INTR
35
0
Interrupt Request: Open drain output which supplies an active low interrupt request from
any of five maskable sources. This pin is inactive after power on reset or a master reset
command.
LPS
36
I
LIght Pen Strobe: Positive edge triggered input indicating a light pen hit. Causes the
current value of the display address to be strobed into the light pen register.
CTRLI
4
110
Handshake Control 1: In independent mode, provides an active low writ!;! data buffer
(WDB) output which strobes data from the interface latch into the display memory. In
transparent and shared modes, this is an active low processor bus request (PBREO)
input which indicates that the CPU desires to access the display memory. This pin must
be tied high when operating in row buffer mode.
CTRL2
5
0
Handshake Control 2: In independent mode, provides an active low read data buffer
(ROB) output which strobes data from the display memory into the interface latch. In
transparent and shared modes, this is an active low bus external enable (BEXT) output
which indicates that the PVTC has relinquished control of the display memory
(DADDO-DADD 13 are in the three-state condition) in response to a CPU bus request.
BEXT also goes low in response to a 'display off and float DADO' command. In row buffer
mode, it is an active low bus request (BREO) output which halts the CPU during a line DMA.
2·38
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
SCN2672
PIN DESIGNATION (cant.)
MNEMONIC
CTRL3
DADDO-DADDI3
PIN NO.
TYPE
NAME AND FUNCTION
6
0
Handshake Control 3: In independent mode, provides the active low buffer chip enable
(BCE) signal to the display memory. In transparent and shared modes. provides an active
low bus acknowledge (BACK) output which serves as a ready signal to the CPU in
response to a processor bus request. In row buffer mode, this is an active high memory bus
control (MBC) output which configures the system for the DMA transfer of one row of
character codes from system memory to the row display buffer.
Display Address: Used by the PVTC to address up to 16K of display memory. These
outputs are floated at various times depending on the buffer mode. Various control signals
are multiplexed on DADD3 thru DADO 13 and are valid at the trailing edge of BLANK. These
control signals are:
34-21
0
DADD3/LI
Line Interlace: Replaces DADD4/LAO as the least significant line address for interlaced
sync and video applications. A low indicates an even row of an even field or an odd row of
an odd field.
DADD4-DADD7/LAO-LA3
Line Address: Provides the number of the current scan line within each character row.
DADD8/LNZ
Line Zero: Asserted before the first scan line in each character row.
DADD9/LPL
Light Pen Line: Asserted before the scan line which matches the programmed light pen
line position (line 3, 5, 7, or 9).
DADD10/UL
Underline: Asserted before the scan line which matches the programmed underline posi·
tion (line 0 thru 15).
DADO 11 IBLINK
Blink frequency: Provides an output divided down from the vertical sync rate.
DADD1210DD
Odd Field: Active high signal which is asserted before each scan line of the odd field when
interlace is specified.
DADD13/LL
Last Line: Asserted before the last scan line of each character row.
VCC
40
I
Power Supply: +5 volts ± 5% power input.
GND
20
I
Ground: Signal and power ground input.
FUNCTIONAL DESCRIPTION
As shown on the block diagram, the PVTC
contains the following major blocks:
• Data bus buffer
• Interface Logic
• Operation Control
• Timing
• Display Control
• Buffer Control
Data Bus Buffer
The data bus buffer provides the interface
between the external and internal data bus·
ses. It is controlled by the operation control
block to allow read and write operations to
take place between the controlling CPU and
the PVTC.
Table 1
PVTC ADDRESSING
A2 AI AO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
READ (RD=O)
Interrupt register
Status register
Screen start address lower register
Screen start address upper register
Cursor address lower register
Cursor address upper register
Light pen address lower register
Light pen address upper register
WRITE (WR=O)
Initialization registers'
Command register
Screen start address lower reg.
Screen start address upper reg.
Cursor address lower register
Cursor address upper register
Display pointer address lower reg.
Display pointer address upper reg.
NOTE
1. There are 11 mitialization registers which are accessed sequentially .... ia a Single address. The PVTC mamtains an
internal pointer to these registers which is incremented alter 8ach write at thiS address until the last register OR 10,
the split screen register) is acc881!1ed. The pointer then continues to point to the split screen register. Upon
power-up or a master reset commend, the internal pointer IS reset to point to the first register (lAO) of the
initialization register group. The internal pointer can also be preset to any register of the group via the 'load fA
address pointer' command.
Interface Logic
The interface logic contains address decoding and read and write circuits to permit
communications with the microprocessor
via the data bus buffer. The functions performed by the CPU read and write operations are as shown in table 1.
Signetics
2·39
2
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
Operation Control
Buffer Control
The operation control section decodes configuration and operation commands from the
CPU and generates appropriate signals to
other internal sections to control the overall
device operation. It contains the timing and
display registers which configure the display format and operating mode, the interrupt logic, and the status register which provides operational feedback to the CPU.
The buffer control section generates three
signals which control the transfer of data
between the CPU and the display buffer
memory. Four system configurations requiring four different 'handshaking' schemes
are supported. These are described below.
SYSTEM CONFIGURATIONS
Display Control
Figure 1 illustrates the block diagram of a
typical display terminal using the Signetics
2670, 2671, 2672, and 2673 CRT terminal
devices. In this system, the CPU examines
inputs from the data communications line
and the keyboard and places the data to be
displayed in the display buffer memory. This
buffer is typically a RAM which holds the
data for a single or multiple screen load
(page) or for a single character row.
The display control section generates linear
addressing for up to 16K bytes of display
memory. Internal comparators limit the portion of the memory which is displayed to
programmed values. Additional functions
performed in this section include cursor positioning, storage of light pen 'hit' location,
and address comparisons required for generation of timing signals and the split screen
interrupt.
The PVTC supports four common system
configurations of display buffer memory,
designaied the independent, transparent,
shared, and row buffer modes. The first
three modes utilize a single or multiple page
RAM and differ primarily in the means used
to transfer display data between the RAM
and the CPU. The row buffer mode makes
use of a single row buffer (which can be a
Timing
The timing section contains the counters
and decoding logic necessary to generate
the monitor timing outputs and to control the
display format. These timing parameters are
selected by programming of the initialization
registers.
SCN2672
shift register or a small RAM) that is updated in real time to contain the appropriate
display data.
The user programs bits 0 and 1 of IRO to
select the mode best suited for the system
environment. The CNTRL 1-3 outputs perform different functions for each mode and
are named accordingly in the description of
each mode.
Independent Mode
The CPU to RAM interface configuration for
this mode is illustrated in figure 2. Transfer
of data between the CPU and display memory is accomplished via a bidirectional
latched port and is controlled by the signals
read data buffer (ROB), write data buffer
(WDB), and buffer chip enable (BCE). This
mode provides a non-contention type of operation that doas not require address
multiplexers. The CPU does not address the
memory directly-the read or write operation is performed at the address contained
in the cursor address register or the pointer
address register as specified by the CPU.
The PVTC enacts the data transfers during
blanking intervals in order to prevent visual
disturbances of the displayed data.
2673
MONITOR
VIDEO TIMING & ATTRIBUTES
cPU
. .- - - - - - - DATA COMMUNICATIONS LINE
Figure 1. CRT Terminal Block Diagram
2·40
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2672
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
The CPU manages the data translers by
supplying commands to the PVTC. The commands used are:
REFRESH
RAM
2672
PVTC
DADO
1. Read / Write at pointer address.
2. Read/Write at cursor address (with optional increment 01 address).
3. Write Irom cursor address to pointer address.
ADR
DISPLAY ADDRESS
BCE
CTRl3
CTRll
2
CE
WDB
\iii
DATA 1/0
CTRl2
The operational sequance lor a write operation is:
'--- iiilii
1. CPU checks RDFLG status bit to assure
2.
3.
4.
5.
6.
that any previous operation has been
completed.
CPU loads data to be written to display
memory into the interlace latch.
CPU writes address into cursor or pointer
registers.
CPU issues 'write at cursor with/without
increment' or 'write at pointer' command.
PVTC generates control signals and outputs specilied address to perlorm requested operation. Data is copied Irom
the interlace latch into the memory.
PVTC sets RDFLG status to indicate that
the write is completed.
TO
VIDEO
lOGIC
DISPLAY DATA BUS
-----1~ 74lS364I
J
iiii
{
FROM
cpu
CV!74lS364
WRCPU
FROM
SYSTEM DATA BUS
/
/
Figure 2. Independent Buffer Mode Configuration
Similarly, a read operation proceeds as 101lows:
1. Steps 1 and 3 as above.
2. CPU issues 'read at cursor with/without
increment' or 'read at pointer' command.
3. PVTC generates control signals and outputs specilied address to perform requested operation. Data is copied Irom
memory to the interlace latch and PVTC
sets RDFLG status to indicate that the
read is completed.
4. CPU checks RDFLG status to see il operation is completed.
5. CPU reads data Irom interlace latch.
Loading the same data into a block 01 display memory is accomplished via the 'write
Irom cursor to pointer' command:
1. CPU checks RDFLG status bit to assure
that any previous operation has been
completed.
2. CPU loads data to be written to display
memory into the interlace latch.
3. CPU writes beginning address 01 memory
block into cursor address register and
ending address 01 block into pointer address register.
4. CPU issues 'write Irom cursor to pointer'
command.
5. PVTC generates control signals and outputs block addresses to copy data Irom
the interlace latch into the specified
block 01 memory.
6. PVTC sets RDFLG status to indicate that
the block write is completed.
play window (defined as lirst scan line of the
lirst character row to the last scan line 01
the last character row), the operation takes
place during the next horizontal blanking interval, as illustrated in figure 3. If the command is given during the vertical blanking
interval, or while the display has been commanded blanked, the operation takes place
immediately. In the latter case, the execution time lor the command is approximately
one microsecond plus six (6) character
clocks (see figure 4).
Similar sequences can be implemented on
an interrupt driven basis using the READY
interrupt output to advise the CPU that a
previously requested command has been
completed.
Timing for the 'write Irom cursor to pointer'
operation is shown in ligure 5. The BLANK
output is asserted automatically and remains asserted until the vertical retrace intervallollowing completion 01 the command.
The memory is lilled at a rate 01 one location
per two character times, plus a small
amount 01 overhead.
Two timing sequences are possible lor the
'read/write at cursor/pointer' commands. If
the command is given during the active dis-
Signetics
2·41
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
~
~
~
-;u
2
,~
" 1/
HORtZONTAL BLANKING
Bl ANI<
~
~,
DO
,,"\
LAST
ADDRESS
_no
CURSOR OR
X POINTER ADDRESS X
I
--------------~2
\
INTERVAL
~~ X
DA
SCN2672
---~
X
X
XPYTC CONTROl SIGNALSX ,1ST CHAR.
TO VAC AND DeG
ADDRESS
X
X
/_REFRESHADDRESSES_
~~------------------------------
/ . I I
2~
NOTE
Write waveforms shown in dotted lines.
Figure 3. ReadlWrlte at Cursor/Pointer Command Timing (Command Received During Active Display Window)
-----------------~~~~--------------~-+-------------
Figure 4. ReadlWrite at Cursor/Pointer Command Timing (Command Received While Display Is Blanked)
2·42
Signefics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2672
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
2
BLANK
DADD
BLANK IS SET UNTIL FIRST VBLNK AFTER LAST WRITE
ANY CHAR
ADDRESS
POINTER
ADDRESS - 1
CURSOR ADDRESS
POINTER
ADDRESS
Figure 5. Write from Cursor to Pointer Command Timing
Shared and Transparent Buffer
Modes
In these modes the display buffer RAM is a
part of the CPU memory domain and is ad·
dressed directly by the CPU. Both modes
use the same hardware configuration with
the CPU accessing the display buffer via
three-state drivers (see figure 6). The pro·
cessor bus request (PBREQ) control signal
informs the PVTC that the CPU is requesting
access to the display buffer. In response to
this request, the PVTC raises bus acknowl·
edge (BACK) until its bus external (BEXT)
output has freed the display address and
data busses for CPU access. BACK, which
can be used as a 'hold' input to the CPU, is
then lowered to indicate that the CPU can
access the buffer.
In transparent mode, the PVTC delays the
granting of the buffer to the CPU until a verti·
calor horizontal blanking interval, thereby
causing minimum disturbance of the display.
In shared mode, the PVTC will blank the dis·
play and grant immediate access to the
CPU. Timing for these modes is illustrated in
figures 7, 8, and 9.
REFRESH
2672
PYlC
PBREQ
CPU { BACK
BEXT
t-:=:::::J~~~~==:>I ADR
RAM
I-
CTRL1
CTRL3
CTRL2
SYSTEM DATA BUS
Figure 6. PVTC Shared or Transparent Buffer Modes
Signetics
2·43
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROUER (PVTC)
~~(1)
,------
SCN2672
~;-------------(~----------------.
~~----~----~----~~--------,
BAeK~
\'-------t~2~----J1 ----j------------~~-----------------
(21
BLANK
W
;
00
'/r-------H-OIt1Z-CN-'-...-8LA~~i1-ING-,-NTE-"Y-AL--------.r-----------(~-----\
----~~z_1
.
=C'1-I=
,-----------
SYSTEM ADDRESSES
DADO
NOTES
1. PSREa must be asserted prior to the rising edge of BLANK in order for sequence to
begin during that blanking period.
2. If PBREQ is negated after the next to last CCLK of the horizontal blanking interval, the
next scan line will al80 be blanked.
Figure 7. Transparent Buffer Mode Timing
PiiRm
{<;---------~~-------------\'-----i----+---i-~,~r-------- -- - __
J
mR
I
~2
'-__
1m
BLANK
1
r----
r--------~~-------------
~,~-------J
\n ______
(1)
~2
~---------
NOTE
1. If PBREQ is negated after the next to 188t ~ of the horizontal blanking interval. the
next scan line will also be blanked.
Figure 8. Shared Buffer Mode Timing
2·44
~~---_~
Signefics
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
la)
SCN2672
Ib)
=-..f\J\..J\J\.J\.n..rL
:_----I~ ----\!
2
P!iRElj
----------------~~----------------.
: 1,
/i-II
Il
\'--~I~
Il
Il
Il
VBLANK OR OBLANK
BlANK
~a-----c:x=
~
SYSTEM PROCESSOR HASZJONTINUOUS BUS CONTROl
}-DADD'\.._ _ _ _ _ _~~l~'-------....I
DADO
~
_REFRESH ADDRESSES-
ADDRESSES
a) During Vertical Blank or after 'dl8play off' command
b) After 'dl8play off and 3-8tate' command
Figure 9. Shared and Transparent Mode Timing
Row Buffer Mode
Figures 10 and 11 show the timing and a
typical hardware implementation for the
row buffer mode. During the first scan line
(line 0) of each character row, the PVTC
halts the CPU and DMA's the next row of
character data from the system memory to
the row buffer memory. The PVTC then releases the CPU and displays the row buffer
data for the programmed number of scan
lines. The bus request control (BREQ) signal informs the CPU that character addresses and the memory bus control (MBC)
signal will start at the next failing edge of
BLANK. The CPU must release the address
and data busses before this time to prevent
bus contention. After the row of character
data is transferred to the CPU, BREQ returns high to grant memory control back to
the CPU.
2x 2111
2672
PVTC
~--~~~~~~~~~
ROW
REFRESH
RAM
BREQ
TO CPU
SYSTEM DATA BUS
Figure 10. Row Buffer Mode Configuration
CCLKJ\J\...fV-V-V--V-V~
I..------J......
1
I '~I
BLANK-r
BREQ
MBC
I
1,.--....;..1_ __
(LINE 0 ONLy)
~l
I~
Il
1
Il
1,------
Il
\\.._ _ _ __
Figure 11. Row Buffer Mode Timing
Signetics
2·45
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
groups, the PVTC is ready to control the
monitor screen. Prior to executing the PVTC
commands which turn on the display and
cursor, the user should load the display
memory with the first data to be displayed.
During operation, the PVTC will sequentially
address the display memory within the limits
programmed into its registers. The memory
outputs character codes to the system
character and graphics generation logic,
where they are converted to the serial video
stream necessary to display the data on the
CRT. The user effects changes to the display by modifying the contents of the display
memory, the PVTC display control and command registers, and the initialization registers, if required. Interrupts and status conditions generated by the PVTC supply the
'handshaking' information necessary for the
CPU to effect the display changes in the
proper time frame.
OPERATION
After power is applied, the PVTC will be in an
inactive state. Two consecutive 'master
reset' commands are necessary to release
this circuitry and ready the PVTC for operation. Two register groups exist within the
PVTC: the initialization registers and the display control registers. The initialization registers select the system configuration, monitor timing, cursor shape, display memory
domain, and screen format. These are loaded first and normally require no modification
except for certain special visual effects.
The display control registers specify the
memory address of the base character (upper left corner of screen), the cursor position, and the pOinter address for independent memory access mode. These usually
require modification during operation.
After initial loading of the two register
BIT7
=..,.-,:;"",'T;.'-r-.:;"~"TU''''''FFE: MOB~:O
SELECT
'RO
0001"" 2 LINES
0010;; 3 LINES
NOT
= 5 L.INES
= 7 LINES
0001
0010
USED
.
=
1110
15 LINES
1111'" 16 LINES
INTERLACE
O=NOt.... NT
0= VSYNC
1
CSYNC
=
= 31 LINES
1110
~
= INDEPENDENT
= TRANSPARENT
10 = SHARED
11 = ROW
00
[
EC--'·--
--- --- ---
·FIR~:~NE ~F C~I;:OR
BIT7
OOOO=SCANLINEO
0001 =SCAN LINE 1
[
•
BIT2
•
.__.__._-'----
BIT6
•
BIT5
110=2SCCLK
111
29CCLK
BIT4.
..
.- -.
BITe.
BLINK
0=1/16
VSYNC
1 = 1/32
VSYNC
•
BIT2
•
BITl
•
· .---.
CURSOR
BLINK
J
00
01
10
11
IR7
= SCAN LINE 7
= SCAN LINE 9
•
alT4
•
BIT3
•
alT2
•
ACTIVE CHARACTER ROWS PER SCREEN
00000oo
1 ROW
0000001 = 2 ROWS
1111110
1111111
BITl
•
BI17
•
---
•
BIT2
•
Bin.
UNDERLINE POSITION
0000 - SCAN LINE a
000 1 = SCAN LINE 1
0= NO
•
alT5
•
BIT4
•
BIT3
•
BIT2
•
BITl
•
- - - '""'iiiSiilAYBUF'F'ERFiii'siADoFiESSL~ - H'ooo'
H'OOl'
[
---
•
=1
NOTE; MSB'S ARE IN
IR9[3:0]
BIT6
--- --- --- ---
•
BITS.
Blf4
BIT3.
BIT2
•
Bin.
BITO
DISPLAY"'BuF'F'E'R'FIR~S]SSB'S
SPi:Av"iUFFER"'i:AsT"ADoRISS
0000 - 1.023
0001 = 2,047
BITO
[
1R9:
SEE IRS
1110 = 15.359
1111
16.383
=
._-'--'
= 127 ROWS
= 12SROWS
'-_.
BITe
NOTE
•
BITS
CURSOR
BLINK
1. In Interlace mode with odd lotal character rows per screen the last character
row will be the programmed scan lines per character row minus one.
~
IR10
0 = 1/16
VSYNC
1
1/32
VSYNC
=
•
BIT4
•
alT3
•
BIT2
•
alTl
•
SPLIT SCREEN INTERRUPT ROW
00000oo
ROW a
0000001
ROW 1
=
1111110 = ROW 126
1111111 = ROW 127
L . - - - L_ _ " _ _ • _ _ • _ _ • _ _ • _ _ •
Figure 12. Initialization Register Formats
Signetics
J
__.
' - - _ L . - _ . _ _ ' _ _ • _ _• _ _ • _ _ '
2·46
BITO
.---. . . . .
·
BIT7
a
•
•
H'FFE' = 4,094
H'FFF' = 4.095
IRB
BITO
__.__ .
1110 = SCAN LINE 14
1111 = SCAN LINE 15
BIT6
J
J
. .--.
'---._---'----'----'-_.
BITO
(NOTE]'
:
1110=SCANLINE14
1111 =SCAN LINE 15
DOUBLE
HEIGHT
CHAR.
= SCAN LINE 3
= SCAN LINE 5
11110 = 64 SCAN LINES
11111 = 66 SCAiIIlIi11ES
BITS
BIT3.LA:~TL~NE ~ C~!;OR _J8ITO
1110=SCANLlNEI4
1111 =SCAN LINE 15
B,TO
..
.
.- -.
- -.
--00001 = 6 SCAN LINES
110 = 28 SCAN LINES
111 = 32 SCAN LINIES
~
BIT3
=
PORIH -----vERTic~o~
00000 - 4 SCAN LINES
VERTICAL FRONT
000 4 SCAN LINES
001 = 8 SCAN LINES
=
•
000
1 CCLK
001 = 5 CCLK
=
•
Bin
---
OOOO_SCANLINEO
0001 =SCAN LINE 1
; IRG:
-"'~-I
1110=30CCLK
1111
32CCLK
8117
B1T4
BITJ
0000
2 CCLK
0001 = 4 CCLK
•
•
NOT
USED
-I
= 256 CHARACTERS
---
BIT4
.~.JBITO
.
· . . .---. .---.
1111 ::: UNDEFINED
BITS.
:OwB1T2
',111110 = 255 CHARACTERS
11111111
1111110=127CCLK
1111111 =128 CCLK
BlT6.
There are 11 initialization registers
(lRO-IR 10) which are accessed sequentially via a single address. The PVTC maintains
an internal pointer to these registers which
is incremented after each write at this ad·
dress until the last register (lR 10, the split
screen register) is accessed. The pointer
then continues to point to the split screen
register. Upon power-up or a master reset
command, the internal pointer is reset to
point to the first register (lRO) of the
initialization register group. The internal
pointer can also be preset to any register of
the group via the 'load IR address pointer'
command. These registers are write only
and are used to specify parameters such as
the system configuration, display format,
cursor shape, and monitor timing. Register
formats are shown in figure 12.
00000010 - 3 CHARACTERS
00000011 '" 4 CHARACTERS
'---_.1....-_. _ _ • _ _ • _ _ • _ _ • _ _ •
BIT7
INITIALIZATION REGISTERS
·~·~~AC·TlVEB~~:RA~TE:~T:ER
01
;;:;::' ~~~~~' ~
SCN2672
BITO
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
IR0(6:3]-Scan Lines per
Character Row
Both interlaced and non-interlaced scanning are supported by the PVTC'. For interlaced mode, two dille rent formats can be
implemented,
depending
on
the
interconnection between the PVTC and the
character generator (see IR 1[7]). This field
defines the number of scan lines used to
compose a character row for each technique. As scanning occurs, the scan line
count is output on the LAO-LA3 and LI pins.
IR0(2]-VS/CS Enable
This bit selects either vertical sync pulses
or composite sync pulses on the
VSYNC/CSYNC output (pin 18). The composite sync waveform conforms to EIA
RS 170 standards, with the vertical interval
composed of six equalizinq pulses, six vertical sync pulses, and six more equalizing
pulses.
IR0[1:0]-BuHer Mode Select
Four buller memory modes may be selectively enabled to accommodate the desired
system configuration. See System Configuration.
IR1[7]-lnterlace Enable
Specifies interlaced or non interlaced timing
operation. Two modes of interlaced operation are available, depending on whether
LO-L3 or L1, LO-L2 are used as the line
address for the character generator. The resulting displays are shown in figure 13.
For 'interlaced sync' operation, the same
information is displayed in both odd and
even fields, resulting in enhanced
readability. The PVTC outputs successive
line numbers in ascending order on the
LAO-LA3 lines, one per scan line for each
field.
The 'interlaced sync and video' format doubles the character density on the screen.
The PVTC outputs successive line numbers
in ascending order on the L1, LAO-LA2 lines,
one per scan line for each field, but alternates beginning the count with even and odd
line numbers. This displays the odd field
with even scan lines in even character rows
and odd scan lines in odd character rows,
and the even field with odd scan lines in
even character rows and even scan lines on
odd character rows. This provides balanced
beam currents in the odd and even fields,
thus minimizing character variations due to
dille rent loading of the CRT anode supply
between fields.
IR 1[6:0]-Equalizing Constant
This field indirectly defines the horizontal
front porch and is used internally to generate the equalizing pulses for the RS 170
compatible CSYNC. The value for this field
is the total number of character clocks
(CCLK) during a horizontal line period divided by two, minus two times the number of
character clocks in the horizontal sync
pulse:
SCN2672
IR5[7:0]-Actlve Characters Per
Row
This field determines the number of characters to be displayed on each row of the CRT
screen. The sum of this value, the horizontal ~~~~5
front porch, the horizontal sync width, and
the horizontal back porch is the horizontal
~~~~~
scan period in CCLKs.
2
IR6[7:4], IR6[3:0]-First and Last
Scan Line of Cursor
The definition of the individual parameters
is illustrated in figure 14. The minimum
value of HFP is two character clocks.
Note that when using the 2673 VAC, the
blank pulse is delayed three CCI-Ks relative
to the HSYNC pulse.
IR2[6:3]-Horizontal Sync Pulse
Width
This field specifies the width of the HSYNC
pulse in CCLK periods.
These two fields specify the height and position of the cursor on the character block.
The 'first' line is the topmost line when scanning from the top to the bottom of the
screen.
IR7[7:6]-Light Pen Line Position
This field defines which of four scan lines of
the character row will be used for the light
pen strike-thru attribute by the 2673 VAC.
The timing signal is multiplexed onto the
DADD9 I LPL output during the falling edge
of BLANK.
IR2[2:0]-Horizontal Back Porch
This field defines the number of CCLKs between the trailing edge of HSYNC and the
trailing edge of BLANK.
IR3[7:5]-Vertical Front Porch
Programs the number of scan line periods
between the rising edges of BLANK and
VSYNC during a vertical retrace interval.
The width of the VSYNC pulse is fixed at
three scan lines.
IR3[4:0]-Vertical Back Porch
This field determines the number of scan line
periods between the falling edges of the
VSYNC and BLANK outputs.
IR4[7]-Character Blink Rate
Specifies the frequency for the character
blink attribute timing. The blink rate can be
specified as 1/16 or 1/32 of the vertical
field rate. The timing signal has a duty cycle
of 75% and is multiplexed onto the
DADD 111 BLINK output at the falling edge of
each BLANK.
IR7[5]-Cursor Blink Enable
This bit controls whether or not the cursor
output pin will be blinked at the selected
rate (IR 10(7). The blink duty cycle for the
cursor is 50%.
IR7[4]-Double Height Character
Row Enable
If enabled, the number of each scan line will
be repeated twice in succession, causing
the height of the character row to double.
This bit can be changed at any time but will
only become ellective at the beginning of
the character row following the time it is
changed. This allows selected character
rows to be of double height. The split screen
interrupt can be used to notify the CPU when
to ellectuate changes to this bit. For each
double height row which replaces a normal
row, one row count should be subtracted
from the 'character rows per screen' field
(lR4) to maintain the same total number of
scan lines per field.
IR4[6:0]-Character Rows Per
Screen
This field defines the number of character
rows to be displayed. This value multiplied
by the scan lines per character row, plus the
vertical front and back porch values, and the
vertical sync pulse width (three scan lines)
is the vertical scan period in scan lines.
SigneHcs
IR7[3:0]-Underline Position
This field defines which scan line of the
character row will be used for the underline
attribute by the 2673 VAC. The timing signal
is multiplexed onto the DADD 101 UL output
during the falling edge of BLANK.
2·47
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
.----------------------,-----
SCN2672
l =~:=ll
_ _ _ L2 _ _ _
_ _ _ L3
LIN E ADDRESS
TO CHAR GEN
LINE ADDRESS
TO CHAR GEN
LINE ADDRESS
TO CHAR GEN
ili
o
g iri
7
o
9 SCAN
LINESI
ROW
1 -.-.-.-.-.---
1 -.-.-.-.-.--
2 -.-------
2 -.-------
3 -.--------4
_.-.-.-----
5 -.---------
-.-.-.-.-.
-.----------
0
1-0-0-0-0-0--
-.
2-0========
17 SCAN
LINESI
ROW
4 -
3-0:~~~:::::::::
9SCAN{
LlNESI
ROW
5-0-
4 -e
5-0===
B -.
6-0
7-00000----
8
2
4-000------
-.-.-.-.-e-2-0===
3-0
6-0
5 .
7 -
1
-.-.-.-.-.---
1
-.-------
2 -.
3
4
5
-.-------.-.-.-----
-.-------
B -.------7
-.-.-.-.-.---
'-0~000
4 -
3 -.---------
4-0-0-0-----
5-0
4-.~.
~
5 -.
-.
6-0
7 -0-0-0-0-0--
7 -.-.-.-.-.--
B
5-0
2-0
•••
-e
7-00000
o
;~.~.~.~:::::::
4-000------
1 -.
3 -.
6
NONINTE8LACED
IRO=1000; TOTAL LINESlROW=9
INTERLACED SYNC
IRO=OIII; TOTAL LINESIROW = 17
;~~;=:::::::
•••••
-.3-0
1 -0-0-0-0-0--
2'
•••••
0
3 -. -------
7 -.-.-.-.-.--
7-0-0-0-0-0--
'.~.!..:=====
B -. -------
•••
4 -0 0 0
5 -.-------
1-00000
3-0
2 - . =======::
•
0
•••••
INTERLACED SYNC II VIDEO
IRO=ooll; TOTAL LINES/ROW=9
Figure 13, Interlaced Display Modes
IR9[3:0], IR8[7:0]-Display Buffer
First Address
IR9[7:4]-Display Buffer last Address
These two fields define the area within the
buffer memory where the display data will
reside. When the data at the 'display buffer
last address' is displayed, the PVTe will
wrap-around and obtain the data to be displayed at the next screen position from the
'display buffer first address'. If 'last address' is the end of a character row and a
new screen start address has been loaded
into the screen start register, or if 'last address' is the last character position of the
2·48
screen, the next data is obtained from the
address contained in the screen start
register.
Note that there is no restriction in displaying
data from other areas of the addressable
memory. Normally, the area between these
two bounds is used for data which can be
overwritten (e.g., as a result of scrolling),
while data that is not to be overwritten would
be contained outside these bounds and
accessed by means of the split screen interrupt feature of the PVTe.
IR10[7]- Cursor Blink Rate
The cursor blink rate can ba specified at
1/16 or 1/32 olthe vertical scan frequency.
Signetics
Blink is effective only if blink is enabled by
IR7(5).
IR10[6:0]-Split Screen Interrupt
The split screen interrupt can be used to
provide special screen effects such as a
row of double height characters or to
change the normal addressing sequence of
the display memory. The contents of this
field is compared, in real time, to the current
character row number. Upon a match, the
PVTe sets the split screen status bit, and
issues an interrupt request if so programmed. The status change / interrupt request is made at the beginning of scan line
zero of the split screen character row.
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
SCN2672
I--_____ CH~I~~OW-------i
I~--~
~--~I
HBLANK ----l
'----
--I I-- FRONT PORCH (IR1)
HSYNC
~L--
--1
BACK PORCH (IR2)
---! f--
___________--,n. . ___
r--
HSYNC
2
(IR~~AR ROWS/SCREEN (lR4) - - - j
I
----r-;::=-;CAN LINES PER ROW (IRO)
1-1- - - ' L
BACK PORCH (IR3) --I
I-VSYNC ---I"lL--_____________---'n. . ____
VBLANK
~....----il
--j f-- FRONT PORCH (lR3)
----j
r-
VSYNC (FIXEO AT 3)
EQUALIZING
CONSTANT
LINES/ROW
IRO
I
I
I
HSYNC
WIDTH
I
I
IR2
I
...I..I---L-'--LI. .1. 1_IL...!..--'
IRI 1
....
I
HBACK
PORCH
I
I
VFRONT
PORCH
i
I
I
I
IR3
I
I
I
I
I
.
1.-1-,--I--,1----,-1--,-1--,1----,-1.....1----'
.
.
CHAR ROWS/SCREEN
IR4
VBACK
PORCH
1
CHARACTERS PER ROW
I I
IRS II.-I-,--I--'--....L....JI--L..I--11----,-1--,1
Figure 14. Horizontal and Verlical Timing
Timing Considerations
Normally, the contents of the initialization
registers are not changed during operation.
However, this may be necessary to implement special display features such as multiple cursors, smooth scrolling, horizontal
scrolling, and double height character rows.
Table 2 describes timing details for these
registers which should be considered when
implementing these features.
Table 2
TIMING CONSIDERATIONS
PARAMETER
TIMING CONSIDERATIONS
First line of cursor
last line of cursor
light pen line
Underline
These parameters must be established at a minimum of two character
times prior to their occurence.
Double height characters
Sell reset during the character row
prior to the row which is to be I not to
be double height
Cursor blink
Cursor blink rate
Character blink rate
New values become effective within
one field after values are changed
Split screen interrupt row
Change anytime prior to line zero of
desired row
Character rows per screen
Change only during vertical blanking
period
Vertical front porch
Change prior to first line of VFP
Vertical back porch
Change prior to fourth line after
VSYNC
Screen start register
Change prior to the horizontal
blanking interval of the last line of
character row before row where new
value is to be used
Signetics
2·49
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
The sequential operation described above
will be modified upon the occurence of either of two events. First, if during the incrementing of the memory address counter the
'display buffer last address' (lR9[7:4)) is
reached, the MAC will be loaded from the
'display buffer first address' register
(IR9[3:01, IR8[7:0)) at the next character
clock. Sequential operation will then resume
starting from this address. This wraparound
operation allows portions of the display buffer to be used for purposes other than storage of displayable data and is completely
automatic without any CPU intervention (see
figure 16a).
DISPLAY CONTROL REGISTERS
There are nine registers in this group, each
with an individual address. Their formats are
illustrated in figure 15. The command register is used to invoke one of 16 possible
PVTC' commands as described in the COMMANDS section of this data sheet. The remaining registers in the group store address
values which specify the cursor and buffer
pointer locations, the location of the first
character to be displayed on the screen,
and the location of a light pen 'hit'. With the
exception of the light pen register, the user
initializes these registers after powering on
the system and changes their values to control the data which is displayed.
refreshing continues from the display buffer
first address.
Cursor Address Registers
The contents of these registers defines the
buffer memory address of the cursor. If enabled, the cursor output will be asserted
when the memory address counter matches
the value of the cursor address registers.
The cursor address registers may be read
or written by the CPU or incremented via the
'increment cursor address' command. In independent buffer mode, these registers define a buffer memory address for PVTC controlled access in response to 'read/write at
cursor with/without increment' commands,
or the first address to be used in executing
the 'write from cursor to pOinter' command.
The sequential row to row addressing can
also be modified under CPU control. If the
contents of the screen start register (upper,
lower, or both) are changed during any character row (say row 'n'), the starting address
of the next character row (row 'n + I') will
be the new value of the screen start register
and addressing will continue sequentially
from there. This allows features such as
split screen operation, partial scroll, or status line display to be implemented. The split
screen interrupt feature of the PVTC is useful in contrOlling this type of operation. Note
that in order to obtain the correct screen
display, the screen start register must be
reloaded with the original value prior to the
end of the vertical retrace. See figure 16b.
Screen Start Registers
The screen start registers contain the address of the first character of the first row
(upper left corner of the active display). At
the beginning of the first scan line of the first
row, this address is transferred to the row
start register (RSR) and into the memory
address counter (MAC). The counter is then
advanced sequentially at the character rate
the number of times programmed into the
active characters per row register (IRS),
thus reaching the address of the last character of the row plus one. At the beginning of
each subsequent scan line of the first row,
the MAC is reloaded from the RSR and the
above sequence is repeated. At the end of
the last scan line of the first row, the contents of the MAC is loaded into the RSR to
serve as the starting memory address for
the second character row. This process is
repeated for the programmed number of
rows per screen. Thus, the data in the display memory is displayed sequentially starting from the address contained in the screen
start register. After the ensuing vertical retrace interval, the entire process repeats
again.
Display Pointer Address Registers
These registers define a buffer memory address for PVTC controlled accesses in response to 'read /write at pointer' commands. They also define the last buffer
memory address to be written for the 'write
from cursor to pOinter' command.
Light Pen Address Registers
If the light pen input is enabled, these registers are used to store the current character
address upon receipt of a light pen strobe
input. Several sources of delay between the
display of a character upon the screen and
the receipt of a light pen hit can be expected
to exist in a system environment. These delays include address pipelining in the character generation Circuits, delays in the video
generation circuits, and delays in the light
detection circuitry itself. These delays
cause the value stored in the light pen register to differ from the actual address of the
character at which the light pen hit actually
was detected. Software must be used to
correct this condition.
During vertical blanking the address counter
operation is modified by stopping the automatic load of the contents of the RSR into
the counter, thereby allowing the address
outputs to free-run. This allows dynamic
memory refresh to occur during the vertical
retrace interval. The refresh addressing
starts at the last address displayed on the
screen and increments by one for each character clock during the retrace interval. If the
display buffer last address is encountered,
me7
SCN2672
.~._~~~~.~.~.Jarro
Lo ._____
.
.----_.--"--_.----_.----_.
COWAND REGISTER (WrtIe only)
~~ i~·~~ .~.JBITO"
.....!!!!....2!!!..-.JBlTO
am .-.!!!.... BIT.~~~~
H'OOOO' - 0
H'0001' = 1
[
0 _ _ • _ _• _ _ _ _ _•
SCREEN START REGISTERS
(READ AND WRITE)
CURSOR ADDRESS REGISTERS (READ AND WRITE)
POINTER ADDRESS REGISTER (WRITE ON..Y)
lIGHT PEN ADDRESS REGISTER (READ ONLY)
Figure 15. Display Control Register Formats
2·50
Note:
•••15,OJ
.,.
_lISa'
_
.-----.----.-----.-----.- -.- -.
H'3FFE' = 18,382
H'3FFF' = 18,383
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
SCN2672
INTERRUPT I STATUS REGISTERS
The interrupt and status registers provide
information to the CPU to allow it to interact
with the PVTC to effect desired changes to
implement various display operations. The
interrupt register provides information on
five possible interrupting conditions, as
shown in figure 17. These conditions may be
selectively enabled or disabled (masked)
from causing interrupts by certain PVTC
commands. An interrupt condition which is
enabled (mask bit equal to one) will cause
the INTR output to be asserted and will
cause the corresponding bit in the interrupt
register to be set upon OCCurrence of the
interrupting condition. An interrupt condition
which is disabled (mask bit equal to zero)
has no effect on either the INTR output or
the interrupt register.
_
DISPLAY BUFFER START
BOTTOM OF SCREEN . .
2
SCREEN START . . h~~r<""""'''''~
MONITOR
DISPLAY
_
p..-"-''-''-'>....'-''-'>....~
DISPLAY BUFFER END
16K ' -_ _ _ _ _--'
MEMORY
(a) DISPLAY MEMORY WRAPAROUND
The status register provides six bits of status information: the five possible interrupting
conditions plus the NOT BUSY bit. For this
register, however, the contents are not
effected by the state of the mask bits.
Descriptions of each interrupt I status register bit follow. Unless otherwise indicated, a
bit, once set, will remain set until reset by
the CPU by issuing a 'reset interrupti status
bits' command. The bits are also reset by a
'master reset' command and upon
power-up.
-
DISPLAY BUFFER START
-
BOTTOM OF SCREEN
SR[5] - RDFLG
This bit is present in the status register only.
A zero indicates that the PVTC is currently
executing the previously issued command. A
one indicates that the PVTC is ready to accept a new command.
p..-"-'''-'>-''-'''-''-''"-''-'l -
MONITOR
DISPLAY
DISPLAY BUFFER END
16K ' - - - -_ _---'
MEMORY
I/SR[4] - VBLANK
(b) DISPLAY MEMORY SPLIT SCREEN WITH WRAPAROUND
Indicates the beginning of a vertical blanking
interval. Is set to a one at the beginning of
the first scan line of the vertical front porch.
Figure 16. Display Addressing Operation
I/SR[3] - Line Zero
Is set to a one at the beginning of the first
scan line (line 0) of each active character
row.
I/SR[2] - Spilt Screen
This bit is set when a match occurs between
the current character row number and the
value contained in the split screen interrupt
register, IR 10[6:0). The equality condition is
only checked at the beginning of line zero of
each character row. This bit is reset when
either of the screen start registers is loaded
by the CPU.
I/SR[1] - Ready
Certain PVTC commands affect the display
and may require the PVTC to wait for a
blanking interval before enacting the com·
mand. This bit is set to one when execution
of the command has been completed. No
BIT7
BIT4
BIT3
BIT2
BIT1
BITO
RDFLG
VBLANK
LINE
ZERO
SPLIT
SCREEN
READY
LIGHT
PEN
0= Busy
1 = Ready
0= No
1 = Yes
0= No
1 = Yes
'0 = No
1 = Yes
0= Busy
1 = Ready
0= No
1 = Yes
BIT5
BIT6
I
Not used
always read as 0
I
NOTE
• Status register only. Always 0 when reading interrupt regia.er.
Figure 17. Interrupt and Status Register Format
command should be invoked until the prior
command is complated.
I/SR[O] - Light Pen
register have been updated. This bit will be
reset when either of the light pen registers is
read.
A one indicates that a light pen hit has oc·
curred and that the contents of the light pen
Signetics
2·51
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
COMMANDS
The PVTC commands are divided into two
classes: the instantaneous commands,
which are executed immediately after they
are invoked, and the delayed commands
which may need to wait for a blanking interval prior to their execution_ Command formats are shown in table 3_ The commands
are asserted by performing a write operation to the command register with the appropriate bit pattern as the data byte.
Table 3
This command initializes the PVTC and may
be invoked at any time to return the PVTC to
its initial state. Upon power-up, two
successive master reset commands must
be applied to release the PVTC's internal
power on circuits. In transparent and shared
buffer modes, the CNTRll input must be
high when the command is issued. The command causes the following:
Enable Light Pen
After invoking this command, receipt of a
light pen strobe input will cause the light pen
register to be loaded with the current buffer
memory address and the corresponding interrupt lind status flag to be set. Once losded, further loads are inhibited until either
one of the light pen registers are read or a
reset function is performed.
Disable Light Pen
Light pen hits will not be recognized.
Display Off
Asserts the BLANK output. The DADDO thru
DADO 13 display address bus outputs may
2·52
0
0
0
0
0
0
a
0
0
a
a
a
0
0
1
1
1
1
0
1
d
d
d
d
0
V
d
d
1
1
a
V
d
d
N
N
a
V
1
1
d
d
0
V
0'
12
0'
12
0
0
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
N
N
N
V
B
d
d
N
N
N
L
Z
d
d
N
N
N
S
d
d
N
N
N
R
0
0'
12
N
N
N
L
P
S
Delayed Commands:
Master Reset
This command is used to preset the.
initialization register pointer with the value
'V' defined by 03-00. Allowable values are
o to 10.
COMMAND
Instantaneous Commands:
Instantaneous Commands
Load IR Address
PVTC COMMAND FORMATS
D7 D6 D5 D4 D3 D2 D1 DO
The instantaneous commands are executed
immediately after the trailing edge of the WR
pulse during which the command is issued.
These commands do not affect the state of
the RDFLG or READY interrupti status bits.
However, a command should not be invoked
if the RDFLG bit is low.
1. VSYNC and HSYNC are driven low for the
duration of RESET and BLANK goes high.
BLANK remains high until a 'display on'
command is received.
2. The interrupt and status bits and masks
are set to zero, except for the RDFLG flag
which is set to a one.
3. The transparent mode, cursoroff, display
off, and light pen di~able states are set.
4. The initialization register pointer is set to
address IRa.
SCN2672
Master reset
loa'd IR pointer with value V (V = 0 to 10)
Disable light pen
Enable light pen
Display off. Float DADO bus if N = 1
Display on: Next field (N = 1) or scan line
(N = a)
Cursor off
Cursor on
Reset interrupti status: Bit reset where N = 1
Disable interrupt: Disable where N = 1
Enable interrupt: Enables Interrupts snd resets
the corresponding interrupt/status bits where
N=l
Hex
1
1
1
1
1
1
a
a
a
a
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
a
a
1
0
1
a
1
a
0
1
a
0
0
1
0
0
1
A4
A2
A9
AC
AA
AD
1
0
1
0
1
0
1
1
AB
1
0
1
1
1
a
1
1
BB
Read at pointer address
Write at pointer address
Increment cursor address
Read at cursor address
Write at cursor address
Read at cursor address and increment
address
Write at cursor address and increment
address
Writa from cursor address to pOinter address
NOTES
1. Any combination of these three commands is valid.
2. Any combination of these three commands is valid.
3. d = don't care.
be optionally placed in the three-stals condition by setting bit 2 to a '1' when invoking
the command.
Display On
Restores normal blanking operation either
at the beginning of the next field (bit 2 = 1)
or at the beginning of the next scan line (bit
2 = 0). Also returns the DADDO-DADD13
drivers to their active state.
Cursor Off
Disables cursor operation. Cursor output is
placed in the low state.
Cursor On
Enables normal cursor operation.
Reset Interrupt/Status Bits
This command resets the designated bits in
the interrupt and status registers. The bit
positions correspond to the bit positions in
the registers:
Bit
Bit
Bit
Bit
Bit
012 3 4-
Light pen
Ready
Split screen
Line zero
Vertical blank
Signefics
Disable Interrupts
Sets the interrupt mask to zeros for the designated conditions, thus disabling these
conditions from asserting the INTR output.
Bit position correspondence is as above.
Enable Interrupts
Resets the selected interrupt and status
register bits and writes the associated interrupt mask bits to a one. This enables the
corresponding conditions to assert the INTR
output. Bit position correspondence is as
above.
Delayed Commands
This group of commands is utilized for the
independent buller mode 01 operation, although the 'increment cursor' command can
also be used in other modes. With the exception 01 the 'write Irom cursor to pointer'
and 'increment cursor' commands, all the
commands of this type will be executed immediately or will be delayed depending on
when the command is invoked. II invoked
during the active screen time, the command
is executed at the next horizontal blanking
interval. II invoked during a vertical retrace
interval or a 'display off' state, the command
is executed immediately.
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
The 'increment cursor' and 'write from
cursor to pointer' commands are executed
immediately after they are issued. 'Increment cursor' requires approximately three
eeLK periods for completion. 'Write from
cursor to pointer' asserts the BLANK output
during its execution. BLANK will not be released until the beginning of the vertical
blanking interval following the last write operation. A second 'write from cursor to pointer' command should not be issued until this
time.
In all cases, the PVTe will assert the
READY IRDFLG status to signify completion
of the command. No other commands should
be given until the current command is completed. Therefore, the READY interrupt or
RDFLG status flag should be used for
handshaking control between the PVTe and
CPU when using these commands.
Read/Write at Pointer
Transfers data between the display buffer
and the bus interface latch using the address contained in the pointer register.
SCN2672
Read/Write at Cursor and
Increment
Transfers data between the display buffer
and the bus interface latch using the address contained in the cursor register and
then adds one (modulo 16K) to the cursor
address register.
Write from Cursor to Pointer
Read/Write at Cursor
Transfers data between the display buffer
and the bus interface latch using the address contained in the cursor register.
Increment Cursor
Adds one (modulo 16K) to the cursor address register.
Writes the data contained in the bus interface latch into the block of display memory
designated by the the cursor address and
pointer address registers, inclusive. After
completion of the command, the pointer address will be unchanged, but the cursor register contents will be equal to the pointer
address.
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Operating ambient temperature'
Storage temperature
All voltages with respect to ground'
RATING
UNIT
o to +70
-65 to +150
-0.5 to +6.0
·e
·e
V
DC ELECTRICAL CHARACTERISTICS TA=o·e to + 70·C, Vcc =5.0V
±5"104,5,6
LIMITS
PARAMETER
V,L
V,H
VOL
VOH
"L
'LL
100
ICC
Input low voltage
Input high voltage
Output low voltage
Output high voltage
(except INTR output)
Input leakage current
Data bus 3-state leakage current
INTR open drain output leakage current
Power supply current
TEST CONDITIONS
Min
Typ
Max
0.8
0.4
V
V
V
10
10
10
160
V
!'A
p.A
p.A
mA
2.0
'OL=2.4mA
'OH= -200!,A
V,N = Oto Vee
Vo = Oto Vee
Vo = Oto Vee
2.4
-10
-10
UNIT
NOTES
See next page.
Signetics
2·53
2
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
SCN2672
AC ELECTRICAL CHARACTERISTICS T A= O'C to + 70'C, Vcc = 5.0V ± 5% 4,5,6,7,8
LIMITS
PARAMETER
TEST CONDITIONS
2.7MHz
Min
Bus Timing (Fig. 18)9
AO·A2 setup time to WR, RD low
tAS
AO·A2 hold time from ~, 1'il5 high
tAH
CE setup time to WR, RD low
tcs
CEhold time from WR, RD high
tCH
WR, RD pulse width
tRW
Data valid after AD low
too
Data bus floating after RD high
tOF
Data setup time to WR high
tos
Data hold time from WR high
tOH
High time from CE to CE1D
tcc
Consecutive commands
Other accesses
CCLK
tccp
tCCH
tCCl
tcco
30
0
0
0
250
t lPH
tlRl
IIRH
NOTES
Timing (Fig. 19)
CCLK period
CCLK high time
CCLK low time
Output delay from CCLK edge
DADDO·13, MBC
BLANK, HSYNC, VSYNC/CSYNC,
CURSOR,BEXT, BREa, BACK,
BCE, WDB, RDBll
150
10
150
5
600
300
600
300
ns
ns
370
125
125
250
100
100
ns
ns
ns
200
100
40
175
40
150
ns
40
225
40
200
ns
Iccp
+30
200
200
ns
ns
ns
Iccp
+30
225
225
BACK high from PBREQ low
BEXT high from PBREQ high
Light pen strobe setup time 10
CCLK low
Light pen strobe hold lime from
CCLK low
INTR low from CCLK low
INTR high from WR, RD high9
120
ns
120
-10
-10
225
600
of this speCification is not Implied.
2. For operating at elevated temperatures, the device must be derated based on
+150°C maximum junction temperature.
3. This product includes circuitry specifically dslgned for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is
suggested that conventional precautions be taken to avoid applying voltages
greater than the rated maxima.
4. Parameters are valid over specified temperature range.
5. All voltage measurements are referenced to ground (GND).
UNIT
Max
30
0
0
0
250
200
100
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This Is a stress rating only and functional operation of
the device at these or at any other condition above those In the operation section
2·54
Min
ns
ns
ns
ns
ns
ns
ns
ns
ns
Other Timings (Fig. 20)
t ROl
READY/RDFLG low from WR high 9
tBAK
tBXT
t lPs
4.0MHz
Max
200
600
ns
ns
ns
6. Typical values are at + 25°C, typical supply voltages and typical processing
parameters.
7. For testing, all input signals swing between O.4V and 2.4V with a transition time of
20ns maximum. All time measurements are referenced at Input voltages of 0.8V
and 2.0V and output voltages of 0.8V and 2.0V as appropriate.
8. Test condition for outputs: C L = 150pF.
9. Timing is illustrated and specified referenced to WR and AD inputs. Device may
also be operated with CE as the 'strobing' input. In this case, all timing specifica·
tions apply referenced to falling and rising edges of CE".
10. This specification requires that the CE input be negated (high) between read
and/or write cycles.
11. OCE, Wl'5'B, and ROB delays track each other within 10nsec. Also, these output
delays wlll tend to follow direction (minImax) of DADDO·13 delays.
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
AO-A2
~_~
SCN2672
_ _ _ _ _ _ __
2
1 - - - IRW---l
00-07
(REAO)
r--------
FLOAT
FLOAT
rlOS
.J\A
/IJ
00-07 _ _ _ _ _ _ _ _ _
(WRITE)
VAllO
Figure 18. Bus Timing
NOTES
OUTPUTS
(NOTE 1) _ _ _ _ _ _ _.1
_
_
---.QU!!~!!.TL
WOB. ROB, BCE
e
'---+_____
1. DADDO·DADDI3. BLANK, HSYNC, CSYNC/VSYNC, CURSOR,
MBC, BACK
iiEXT,
BREa,
iiCE,
2. BCE change. state on both CCLK edgea-(aes Figures 3 and 4).
ICCO
Figure 19. CCLK Timing
Signefics
2-55
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
-
... _~r
FIRST HSYNC
OF YBLANK
HaYNC
-
STATUS BIT
BLAN<
DAIID3-
"""3
LlNEZEFIOAND
SPUT SCREEN
STATUS BITS
1T~
LPS
r--
lJGHT PEN
STATUS BIT
-
"""3
......ACTER
ADDRESSn
Figure 20. Other Timings
2·56
SigneHcs
SCN2672
JANUARY 1983
MICROPROCESSOR DIVISION
PROGRAMMABLE VIDEO TIMING CONTROLLER (PVTC)
WiiFORA
DELAYED
COMMAND
READY OR
RDFLG
STATUS BITS
~
,"----
PBREa \
~
SCN2672
-..J
2
2~~
TBAKr-
I
rr________________
/,..------~22
TBXT
________- J
~J
Bffi
r--
WiiORiili~
WHICH RESETS
INTERRUPT
'-------.J I~
TIRH
/~-----
iNTii
Figure 21. Other Timings
EVEN FIELD
LAST
DISPLAYED SCAN
OF PREVIOUS FIELD
1 \
~
VERTICAL FRONT PORCH
hL-IL/
[l./"'PULSES
~
~1
U-.--------------
LAST DISPLAYED SCAN
OF EVEN FIE\D
FIRST DISPLAYED SCAN
OF EVEN FIELD
/
HORIZONTAL SYNC
VERTICAL BACK PORCH---i
~
BLANK
~~
+-
VERTICAL SYNC PULSE
n
L--...J
CSYNC
-+
II-- VERTICAL FRONT PORCH-\'.! H
CSYNC~
VERTICAL BLANKING INTERVAL
----------I~~LfL
-----I
-+
VERTICAL SYNC PULSE+- VERTICAL BACK PORCH-\'.! H
---j \'.! H
I--
\'.! HORIZONTAL SYNC
~'01.J="
"~,~.~..".''''~,,
---ll-
~ FIRST DISPLAYED SCAN
I
OF ODD FIELD
~
I
I H PERIOD
~
HORIZONTAL BLANKING INTERVAL
NOTES
1. In non-interlaced operation the even field is repeated continuously. and the odd field
is not.
2. In interlaced operation the even field alternetea with the odd field.
Figure 22. Composite Sync Timing
Signetics
2-57
JANUARY 1983
MICROPROCESSOR DIVISION
VIDEO ATTRIBUTES CONTROLLER (VAC)
SCB2673
PIN CONFIGURATION
DESCRIPTION
FEATURES
The Signetics 2673A and 2673B Video Attributes Controllers (VAC) are bipolar LSI
devices designed for CRT terminals and
display systems that employ raster scan
techniques_ Each contains a high speed
video shift register, field and character
attributes logic, attribute latch, cursor format logic and half dot shift control.
• 25MHz video dot rate
• Three level current driven (75 ohms)
video output
• Three level encoded TTL video outputs
• CharacterIfleld attribute logic
Reverae video
Character blank
Character blink
Underline
Highlight
Light pen strlke-thru or graphics
control
• Field attributes extend from row to row
• Light or dark field
• Cursor reverse video logic
• Up to 10 dote per character
• CompOSite blanking for light field
retrace
• Optional field graphics control output
• High speed bipolar design
• 40 pin dual In-line package
• TIL compatible
• Compatible with SlgneUcs 2672 PVTC
and 2670 DCGG
The VAC provides control of visual attributes on a field or character by character.
Internal logic preserves field attribute data
from character row to character row so
that an attribute byte is not required at the
beginning of each row. The 2673B provides
for reverse video, blank (non-display),
blink, underline and highlight attributes
and a graphics mode attribute to work in
conjunction with the Signetics 2670 Display Character and Graphics Generator
(DCGG). The 2673A substitutes a light pen
(strike-thru) attribute for the graphics
attribute.
The horizontal dot frequency is the basic
timing input to the VAC. Internally, this
clock is divided down to provide a character clock output for system synchronization. Up to ten bits of video dot data are
parallel loaded into the video shift register
on each character boundary. The video
data is shifted out on three outputs at the
dot frequency. On the VIDEO output, the
data is presented as a three level signal
representing low, medium and high intensities. The three intensities are also encoded on two TIL compatible video outputs. Light or dark screen background can
be selected.
APPLICATIONS
• CRT terminals
• Word processing s,stems
• Small business computers
TOP VIEW
ORDERING CODE
Vcc=5V ::1:5%, TA =O·Ct070·C
GRAPHICS ATTRIBUTE
LIGHT PEN ATTRIBUTE
25MHz
25MHz
PACKAGES
Ceramic DIP
Plastic DIP
18MHz
BLOCK DIAGRAM
VIDEO ATTRIBUTES C()NTROLLER
ceo
-----..r~CH;;.A;:;R~A~C;TE~R;__\
CC1:::::::::::::::::::::::~~C~LOEc~K~~~~----------.CCLK
CC2
COUNTER
DCLK--------~---+_--_,
10
VIDEO
HDOT~~n
CURSOR
ARVID
ABLANK
ABLINK ---_~
~-----CBLANK
AUL ----~ ATTRIBUTE AND
ALTPEN/AGM
CURSOR CONTROL
AFLG
LOGIC AND
AMODE
PIPELINE
ACD
BLINK
UL
1 - - - - -.....- - - - - - - BLANK
t-------------- RESET
LL----.J
LPUGMD
2-58
TTLVID1
TTLVID2
1+----- BKGND
AHILT---_~
::::::::::::::=:1
18MHz
SCB2673BC5140 SCB2673BC8140 SCB2673AC5140 SCB2673AC8140
SCB2673BC5N40 SCB2673BC8N40 SCB2673AC5N40 SCB2673ACBN40
-----o-L____---1
Signetics
Vcc
vBB
GND
JANUARY 1983
MICROPROCESSOR DIVISION
SCB2673
VIDEO ATTRIBUTES CONTROLLER (VAC)
PIN DESIGNATION
PIN NO.
TYPE
DCLK
MNEMONIC
32
I
Dot Clock: Dot frequency input. Video output shift rate.
CCLK
36
0
Character Clock: A submultiple of DCLK. The frequency ranges from one sixth to one twelfth
of DCLK, as determined by the state of the CCO-CC2 inputs.
33-35
I
Character Clock Control: The logic state on these three static inputs determine the internal
divide factor for the CCLK output rate. Character clock rates of 6 thru 12 dots per character
may be specified.
00-09
37-39, 2-8
I
Dot Data Input: These are parallel inputs corresponding to the character I graphic symbol dot
data for a given scan line. These inputs are strobed into the video shift register on the falling
edge of each character clock.
HOOT
27
I
Half Dot Shift: When this input is high, the serial video output is delayed by one half dot time.
This input is latched on the falling edge of each character clock.
CURSOR
14
I
Cursor Timing: This input provides the timing for the cursor video. When high, effectively
reverses the intensities of the video and attributes. Cursor position, shape, and blink rate are
controlled by this input.
BKGND
10
I
Background Intensity: Specifies light or dark video during BLANK and character fields.
Affects the intensities of all attributes.
BLANK
15
I
Screen Blank: When high, this input forces the video outputs to the level specified by the
BKGND input (either high or low intensity). Not effective when CBLANK is high.
CBLANK
31
I
Composite Blank: Used with the TTL video outputs only. When high, this input forces the
video outputs to a low intensity state for retrace blanking. When BKGND input is low, or when
using video outputs, this input may be tied low.
ARVID
22
I
Reverse Video Attribute: The intensity of the associated character or field video is reversed.
All other attributes are effectively reversed.
AHILT
23
I
Highlight Attribute: All dot video (including underline) of the associated character or field is
highlighted with respect to the BKGND input and the reverse video attribute.
ABLANK
26
I
Blank Attribute: Generates a blank space in the associated character or field. The blank
space intensity is determined by the BKGND input, the reverse video attribute, and the
CURSOR input.
ABLINK
25
I
Blink Attribute: The associated character or field video is driven to the intensity determined
by BKGND and the reverse video attribute when the BLINK input is high.
AUL
24
I
Underline Attribute: Specifies a line to be displayed on the character or field. The line is
specified by the UL input. All other attributes apply to the underline video.
ALTPEN/AGM
21
I
Light Pen Attribute (2673A): Specifies a highlighted line to be displayed on the character or
field. The line is specified by the LPL input.
I
Attribute Graphics Mode (2673B): This input is latched and synchronized to provide a
field GMD output for the 2670 DCGG.
CC2-CCO
NAME AND FUNCTION
= 0) or field (AMODE = 1) attributes mode.
AMODE
12
I
Attribute Mode: Specifies character (AMODE
AFLG
13
I
Attributes Flag: The VAC samples and latches the attributes inputs when this input is high. "
field attributes are specified (AMODE = I), the attributes are double buffered on a row basis.
Thus, each scan line of every character row will start with the attributes that were valid at the
end of the previous row.
ACD
11
I
Attribute Control Display: In field attributes mode (AM ODE = I), if ACD = 0, the first
character in each new attribute field (the attribute control character) will be suppressed and
only the attributes will be displayed. " ACD = I, the first character and the attributes are
displayed. This input has no effect in character mode (AMODE = 0).
Signetics
2·59
2
JANUARY 1983
MICROPROCESSOR DIVISION
SCB2673
VIDEO ATTRIBUTES CONTROLLER (VAC)
PIN DESIGNATION (continued)
PIN NO.
TYPE
NAME AND FUNCTION
BLINK
17
I
Blink: This input is sampled on the falling edge of BLANK to provide the blink rate for the
character blink attribute. It should be a submultiple of the frame rate.
UL
16
I
Underline: Indicates the scan line(s) for the underline attribute. Latched on the falling edge of
BLANK.
LPlIGMD
19
I
Light Pen Line (2673A): Indicates the scan line(s) for the light pen strike-thru attribute.
Latched on the falling edge of BLANK.
0
Graphics Mode (2673): This output provides a synchronized, latched, field graphics mode
corresponding to the AGM input. This output can be used to control the GM input on the 2670
DCGG.
MNEMONIC
LL
18
I
Last Line: Indicates the last scan line of each character row. Used internally to extend field
attributes across row boundaries. Latched on the falling edge of BLANK. This input has no
effect in character mode (AMODE = 0).
VIDEO
28
0
Video: A three level serial video output which corresponds to the composite dot pattern of
characters, attributes and cursor.
TTLVIDI
30
29
a
a
TTL Video 1: This output corresponds to the serial, non-highlighted video dot pattern.
TTLVID2
RESET
9
I
Manual Reset: This active high input initializes the internal logic and resets the attribute
latches.
VCC
40
I
Power Supply: +5 Volts ± 5%
VBB
GND
1
I
BlaB Supply: See figure 13.
20
I
Ground: OV reference
TTL Vidao 2: This output corresponds to the highlighted serial video dot pattern. Should be
used with TTLVID 1 to decode a composite video of three intensities.
FUNCTIONAL DESCRIPTION
The VAC consists of four major sections
(see block diagram). The high speed dot
clock input is divided internally to provide
a character clock for system timing. The
parallel dot data is loaded into the video
shift register on each character boundary.
and shifted into the video logic block at
the dot rate. The six attribute inputs are
latched internally and combined with the
serial dot data to provide a three level
video source for the monitor.
A separate BLANK input defines the ac·
tive screen area. When BLANK= 0, the
video levels are derived internally by the
combinations of dot data, attributes, cursor, and the state of the BKGND input.
Either black or white background can be
selected. Symbols (dot data) are normally
gray and can be highlighted to white or
black as shown In figure 1. Note that the
VIDEO output is inverted as referenced to
the TTL video outputs.
During the inactive screen area (BLANK=
I), the video level produced by the TTL outputs is either white (BKGND= 1) or black
(BKGND=O). A separate composite blank
(CBLANK) input is provided to suppress
raster retrace video when white background is specified. During the inactive
screen area (BLANK= 1), the video level
produced by the VIDEO output is either
black (BKGND = 1) or white (BKGND = 0).
2·60
CC[j(
CC2
CCI
ceo
DOTS/CHARACTER
DUTY CYCLE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
6
7
8
9
10
11
12
3/3
3/3
4/3
4/4
5/4
5/5
6/5
6/6
For the latter case, raster retrace video
suppression is accomplished by raising
the BKGND input during horizontal and
vertical retrace intervals. For black background, tie BKGND high. Tie CBLANK input low for both cases.
always shifted out before DO. For 12 dots/
character, a 0 is also shifted out after 09.
The serial dot data is shifted into the video
logic where it is combined with the cursor
and attributes to encode three levels of
video.
Character Clock Counter
Attribute and Cursor Control
The character clock counter divides the
frequency on the DCLK Input to generate
the character clock (CCLK). The divide factor is specified by the clock control inputs
(CCO-CC2) as shown in the table above.
The VAC visual attributes capabilities include: reverse video, character blank,
blink, underline, highlight, and light pen
strike-thru. The six attributes and the
three attribute control inputs (AMODE,
AFLG, and ACD) are clocked into the VAC
on the falling edge of CCLK. If AFLG is
high, the attributes are latched internally
and are effective for either one character
time (AM ODE = 0) or until another set of
attributes is latched (AMODE= 1). The attributes set is double buffered on a row by
row basis internally. Using this technique,
Video Shift Register
On each character boundary, the parallel
data (DO-D9) is loaded into the video shift
register. The data is shifted out least
significant bit first (DO) by the DCLK. If
11 or 12 dots/character are specified
(CC2-CCO = 110 or 111), a 0 (blank dot) is
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
VIDEO ATTRIBUTES CONTROLLER (VAC)
SCB2673
DCLK
CCLK
:
~
I
u=u--t:
2
~
I
I
TTLVID1
TTLVID2
NORMAL
GRAY ON BLACK
NOTE
1. W= White
G = Gray
B = Black
field attributes can extend across character row boundaries thereby eliminating the
necessity of starting each row with an
attribute set.
When field attribute mode is selected,
(AMOOE= 1), the VAC will accommodate
two attribute storage configurations. In
one configuration, the attribute control
data is stored in the refresh RAM, taking
the place of the first character code in the
field to be affected. For this mode, the
ACO input is tied low and blank characters
will be displayed in the screen positions
occupied by the attribute data (see figure
10). In the second configuration, (ACO = 1),
the character codes and attribute data are
presented to the VAC in parallel. In this
mode, dot data is displayed at each
character position (see figure 11).
The CURSOR and the attribute Input signals are pipelined internally to allow for
system propagations (one CCLK for refresh RAM, one CCLK for dot generator).
The attribute timing signals BLINK, UL,
LPL and LL are clocked into the VAC at the
beginning of each scan line by the falling
edge of the BLANK input. Thus, these signals must be in their proper state at the
falling edge of BLANK preceding the scan
line at which they are to be active (see
figure 4).
HIGHLIGHTED
WHITE ON BLACK
REVERSE
GRAY ON WHITE
REVERSE,
HIGHLIGHTED
BLACK ON WHITE
Figure 1_ Encoded Video Outputs
TTLVID2
TTLVID1
0
0
1
0
1
1
1
0
INTENSITY
Black (or CBLANI<)
Gray (on black 8urround)
Gray (on white surround)
White
NOTE
The TTLVID1 output can be u.ed Independently to genera.e 8 two level non-highlighted video.
Video Logic
The serial dot data and the pipelined cursor and attributes are combined to generate the three level current source on the
VIDEO output. The three levels (white,
gray, and black) are also encoded on the
two TTL compatible outputs TTLVIDI and
TTLVID2. The three levels are encoded as
shown above.
The video is normally shifted out on the
leading edge of the OCLK. When the
HOOT input is asserted, the corresponding dot data is delayed by one-half OCLK.
This half dot shifting, when used on
selected lines of character video, can be
used to effect eye-pleasing character
rounding as shown In figure 2.
Attribute Hierarchy
The video of each character block consists of four components as shown in
figure 3.
Signetics
Symbol video is generated from the dot
data inputs 00-09.
Underline video Is enabled by the AUL
attribute and is generated when the UL
timing input Is active. Underline and symbol video are always the same Intensity.
Strike-thru video is enabled by the ALTPEN
attribute and is generated when the LPL
timing input is active. This video is always
highlighted and takes precedence over the
symbol and underline video. This feature
applies to the 2673A only.
Surround video is the absence of symbol,
underline and strlke-thru video or the
presence of the non-display attributes
(ABLANK or ABLINK • BLINK).
The relative intensities of the four video
components are determined by the remaining attributes (AHILT, ABLANK,
ABLlNK, ARVID) and the BKGNO and
CURSOR inputs as illustrated in table 1.
2·61
JANUARY 1983
MICROPROCESSOR DIVISION
SCB2673
VIDEO ATTRIBUTES CONTROLLER (VAC)
1 Jill 1
I I I I I I
0000
0
0
00
0
0
0
0
0 0
0
000000
0
000
H
H
H
H
SYMBOL
VIDEO ---+<"~
0000
0 0 0
0 0
0
0 0
0
0 0
0
0 000
0
0000
H =LINES SHIFTED
"'\.'-"'<'1--- SURROUND
VIDEO
LlClHTPEN
STRILE THRU
VIDEO
(2873A only)
UNDERLINE
VIDEO
Figure 3. Video Components of Character Block
Figure 2. "AT" Symbol with and without Half Dot Shifting
Table 1 ATTRIBUTES HIERARCHY
ATTRIBUTES AND CONTROL INPUTS
d = don't care
NONDISPLAy2
RELATIVE VIDEO INTENSITIES
W = White, B = Black, G = Gray
BKGND5
REVERSE1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
d
0
1
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
NOTES
1
1
1
AHILT
STRIKE
THRU
VIDE03
SYMBOL OR
UNDERLINE
VIDE03,4
W
W
B
B
B
W
B
B
W
W
W
B
G
W
B
G
1
1
d
0
1
d
0
1
d
+ AI!iVm • CURSOR
= ABLANK + ABLINK • BLINK
1. Reverse. ARVID • ~
2. Non·dlsplay
3. See figure 3
4. Symbol and underline video are always the same intensity.
5. Reverse aenS8 for VIDEO output.
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
Operating ambient temperature2
Storage temperature
All voltage. with respect to ground
RATING
UNIT
o to +70
·C
-86 to +150
-0.6 to +8.0
V
·C
NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This Is
a stress rating only and functional operation of the device at these or at any other condition above those indicated
in the operation section of this specification Is not implied.
2. For operating at elevated temperatures, the device must be derated based on
temperature.
2-82
+ 150°C maximum junction
Signetics
B
W
G
B
W
G
W
B
SURROUND
VIDE03
B
B
B
W
W
W
W
W
W
B
B
B
MICROPROCESSOR DIVISION
JANUARY 1983
VIDEO ATTRIBUTES CONTROLLER (VAC)
DC ELECTRICAL CHARACTERISTICS
SCB2673
TA=O·Cto +70·C, Vcc=5V ±5%, VBB=See figure 133 ,4,5
LIMITS
TEST CONDITIONS
PARAMETER
VIL
VIH
Input low voltage
Input high voltage
VOL
Output low voltage
(except VIDEO)
Output high voltage
(except VIDEO)
VOH
VB
VG
Vw
VIDEO black level
VIDEO gray level
VIDEO white level
IlL
Input low current
IIH
Input high current
ICC
IBB
V CC supply current
VBB supply current
Min
Typ
Max
0.8
V
V
0.4
V
2.0
IOL=4mA
2.4
IOH= - 4OOI'A
UNIT
V
RL = 150 ohms to GND
RL = 150 ohms to GND
RL = 150 ohms to GND
V
V
V
0
0.45
O.SO
VIN = 2.4V
-4001
-800 10
20/40 '0
I'A
VIN = OV, VCC = max
VBB = max
80
120
rnA
rnA
VIN = 0.4V
I'A
AC ELECTRICAL CHARACTERISTICS TA=O·C to + 70·C, Vcc=5V ±5%, VBB=See figure 133,4,5
LIMITS
PARAMETER
TEST CONDITIONS
25MHz
VERSION
Min
Max
18MHz
VERSION
Min
UNIT
Max
Dot clock 6
frequency
fo
high
tOH
low
tOL
15
15
22
22
MHz
ns
ns
Setup times to CCLK7
BLANK
t BS
BLINK, UL, LPL, LL (ref to BLANK)
tsc
Attributes
tSA
Dot data DO·DS
tso
CURSOR
tSK
AFLG
t FS
HDOT
tSH
50
20
45
70
50
50
45
50
20
55
70
50
65
55
ns
ns
ns
ns
ns
ns
ns
20
20
30
20
30
20
20
20
30
20
30
20
ns
ns
ns
ns
ns
ns
15
15
15
15
ns
ns
15
15
15
15
ns
ns
25
Hold times from ~7
BLINK, UL, LPL, LL (ref to BLANK)
tHC
Attributes
tHA
Dot data DO·DS
tHO
CURSOR
tHK
AFLG
tFH
HOOT
tHH
Setup times to DCLK8
BKGND
tSG
CBLANK
tSB
Hold times from DCLK B
BKGND
t HG
CBLANK
tHB
Delay times 9
GMD from DCLK
tOGM
CCLK from DCLK
tOC
TILVID1 and TILVID2 from DCLK
tov
VIDEO from DCLK
tov
18
CL = 150pF
'1
45
NOTES
3. Parameters are valid over operating temperature range unless otherwise specified.
4. All voltage measurements are referenced to ground (VSS)' All input signals swing
between O.4V and 2.4V. All time measurements are referenced at Input voltages of
a.8V, 2.0V and at output voltages of a.8V, 2.0V 8S appropriate.
5. Typical values are at + 25°C, typical supply voltages and typical processing parameters.
Signetics
65
65
75
240
45
65
65
80
240
ns
ns
ns
ns
6. See figure 9.
7. See figures 4, 5, 6, and 9.
B. See figure B.
9. See figures 6 and 7.
10. For OCLK input.
11. CL less than 150pF minimum could be faster.
2·63
2
JANUARY 1983
MICROPROCESSOR DIVISION
VIDEO ATTRIBUTES CONTROLLER (VAC)
SCB2673
e.,.....-------------
tBSI--!
BLANK
--.,,=~
p-------t---t-- - -
J
-
BLlNK,UL
LPL,LL _....J.~_ _
......;n._-:-
ATTRIBUTES1
_...J1::..=;;:.:.......".~==r'___
-----~
______
~
tHD
-'"'\J""'"':-::--'-":-:;::::-"""I~r-
'-_~...n~_~7'-_
-
_
~
LAST-l
LAST
CHAR
~
NOTES
1. Attribut•• lnclud.: ABLlNK, ABLANK, ARVID, AUL, AHlLT, and ALTPEN.
2. One CCO<' delay 'or dot data (obtained from delay through character generator).
3. See flgur. 7 for datall timing of VIDEO, TTLVID 1, TTLVID2.
4. Non-actlYe 8can time. VIDEO revert. to polarity 'elected by the BKGND Input.
Figure 4. VAC Pipeline Timing
1-__~\tHK
CURSOR _ _ _ _J
VIDEO
---======
I"
CHARACTER
WITH CURSOR
~
Figure 5. Cursor Pipeline Timing
2·64
Signetics
I
BKGND4
JANUARY 1983
MICROPROCESSOR DIVISION
VIDEO ATTRIBUTES CONTROLLER (VA C)
I
j-tFS-j
AFLG
f
At
SCB2673
I
\
-I
jtFH
A2
\
I
(AMO~~:~ ---'I ~-t-.------II ~.
2
I
GM01 _____________~I--------------------------,
(AMOOE=1).
' - -_____________________
NOTE
1. GMD output in 26738 version only. See figure 7 for detail timing.
Figure 6. Character (AMODE
=0), Field (AMODE =1), and GMD Attribute Timing
OCLK
_~I toc
CCLK
'OH
VOL
~
_________________________________
_
I
_tOY
VIDEO
TTLVI01,2
I
CHARACTER N - 1
GM0 1
(AMOOE=1)
-'l
CHARACTER N
tOGM
'----------'1."14-____________ _
NOTE
1. GMD output in 26738 version only.
Figure 7. Video and GMD Pipeline Timing
Signetics
2·65
JANUARY 1983
MICROPROCESSOR DIVISION
SCB2673
VIDEO ATTRIBUTES CONTROLLER (VAC)
JLJLJl
OCLK
BKGNO
ISG~,-_r-
VIDEO
I
~/
r'HGI
_____
~
GRAY
\
BLACK
u~J
/
nl
IHB~
~ISB
GRAY
t
22
~,
BLACK
Figure 8. BKGND and RBLANK Timing During Inactive Scan Time (Blank = 1)
OCLK
CCLK
~~~1J;.______________
ISH I.
'1'
-= ==IL.______
'IIHH
HDOT~
VIDEO
LAST PIXEL
CHAR N
FIRST PIXEL
CHAR N+1
NOTE
1. Half dot shift feature 18MHz maximum.
Figure 9. Half Dot Shift Timing
2·66
Signetics
-2
I
JANUARY 1983
MICROPROCESSOR DIVISION
SCB2673
VIDEO ATTRIBUTES CONTROLLER (VAC)
To CRT CONTROLLER
61~
OE~-----------------------J
'"~"'-----I74LS244
SELECT
DECODE
\r______________-=Dc;::IS::...PL:::A;.:.Y.;:D::.;AT.:..:A::..:B::.:U:.::S________________v
~
Figure 13. Row Table Mode Configurallon (non·Row Buffer Modes)
IR3(4:0] - Vertical Back Porch
This field determines the number of scan
line periods between the falling edges of
the VSYNC and BLANK outputs..
IR4(7] - Character Blink Rate
Specifies the frequency for the character
blink attribute timing. The blink rate can
be specified as 1164 or 11128 of the vertical
field rate. The timing signal has a duty cy·
cle of 50% and is multiplexed onto the
DADD111BLlNK output at the falling edge
of each BLANK.
IR4(6:0] - Character Rows Per
Screen
This field defines the number of character
rows to be displayed. This value multiplied
by the scan lines per character row, plus
the vertical front porch, the vertical back
porch val ues, and the vertical sync pu Ise
width is the vertical scan period in scan
lines.
2·82
IR5(7:0] Row
Active Characters Per
This field determines the number of char·
acters to be displayed on each row of the
CRT screen. The sum of this value, the
horizontal front porch, the horizontal sync
width, and the horizontal back porch is the
horizontal scan period in CCLKs.
IR6(7:4], IR6(3:0] - First and
Last Scan Line of Cursor
These two fields specify the height and
position of the cursor on the character
block. The 'first' line is the topmost I.ine
when scanning from the top to the bottom
of the screen.
IR7(7:6] Width
Vertical Sync Pulse
This field specifies the width of the
VSYNC pulse in scan line periods.
IR7(5] -
Cursor Blink Enable
This bit controls whether or not the cursor
output pin will be blinked at the selected
Signetics
rate (IR7[4]). The blink duty cycle for the
cursor is 50%.
IR7(4) -
Cursor Blink Rate
The cursor blink rate can be specified at
1132 or 1164 of the vertical scan frequency.
Blink is effective only if blink is enabled by
IR7[5].
IR7(3:0] -
Underline Position
This field defines which scan line of the
character row will be used for the under·
line attribute by the 2675 CMAC. The tim·
ing signal is multiplexed onto the
DADD10lUL output during the falling edge
of BLANK.
IR9(3:0], IR8(7:0] - Display
Buffer First Address
IR9(7:4] - Display Buffer Last
Address
These two fields define the area within the
buffer memory where the display data will
reside. When the data at the 'display buf·
fer last address' is displayed, the AVDC
MICROPROCESSOR DIVISION
JANUARY 1983
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'm"..""··,.,
2
CCLK
lI1JlIlJlflJ1Il
I
I
....._..;;;LA.;;S.;.T.;;LI.;;N.;;E.;;O;..F.;;RO;;.W;;...._......I
BLANK
HSYNCJl
ROW BUFFER
MODE
FIRST LINE OF ROW
n
r---E-C-+2-H-S-W-C-CL-K-S-1~--------~
1JUUUl
I
III
_
L
~-""';;'==;';;";;';"';=;""-"I ~
L __~________________~III_______
1.....----1----+----------1:
BREQ
MBC
----------------------~
DADD
LAST LINE ADDRESSES
FIRST LINE ADDRESSES
CURSOR
DADD
III" I '" I
FIRST LINE ADDRESSES
BREQ
TRANSPARENT
BUFFER MODE
BACK
I
I
I
II
I
3-STATE
I
13-STATE
I
iI
BUS REQUEST
DURING
I I '" I
I
NO FETCH BUS
REQUEST
I~
I
FETCH CYCLE
I
(CURSOR OR POINTER ADDRESSES
FOR DELAYED COMMANDS)
DADD
INDEPENDENT
BUFFER MODE
WDB
FIRSTLINEADDRESSES
u
RDB
u
BCE~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
= MULTIPLEXED CONTROL SIGNALS
EC = EQUALIZING CONSTANT
HSW = HORIZONTAL SYNC WIDTH
.1
Figure 14. Row Table Mode Timing
Signetics
2-83
MICROPROCESSOR DIVISION
JANUARY 1983
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'am""JIeI••"
,
0010
O=OFF
1 =ON
'00
,
,
BIT5
BiTe
BlT4
BIT3
SCAN LINES PER CHARACTER ROW
NON-INTERLACED
INTERLACED
0000 :: 1 LINE
0000 - 2 liNES
()()()1 '" 2 LINES
0001", 4 LINES
Blr7
DOUBLE
HTIWO
'1'0
1'1'
= 3 liNES
0= YSYNC
00
1
01
= INDEPENDENT
= TRANSPARENT
10
=
= CSVNC
1110=30 LINES
1111 = UNDEFINED
t6llNES
•
IR8
j
•
BITS
•
BIT4
.-----.-----.
SHARED
= ROW
11
BIT6
•
BIT3
•
BIT2
•
-----
BllO
Bin.
,s.rs- ---
- - - """"iiiSPLAvOUFFEO FlOST AOOOESS
HOOO' - 0
H'OOl = 1
•
NOTE: MSB'S ARE IN
•
IR9{3:o1
H'FFE = 4,094
H'FFF' == 4,095
SELECT
[
0010=6 LINES
= 15 L.INES
=
BIT7
B~TU~FE~~
BIT2
SYNC
SELECT
J
.- - -.-----.-----.
'BIT7
BIT6
•
BIT5
•
8114
INTERLACE
B1T3
•
BIT2
•
BITl
•
EOUAlIZING CONSTANT
ENABlE
'0'
•
0000000 -1 CCLK
0000001 = 2 CCLK
O=HQN-INT
CALCULATED FROM
:
1111110=127 CCLK
1111111 =128 CClK
1 = INTER.
EC
= 0 5(HACT+HFP+HSYNC+HSP)
BIT7
om
BiTe
ROW
0000
0001
'R2
,
BITS
,
BIT4
BIT2
BIT3
=
= .. CClK
O=OFF
1 =ON
•
Bin.
= 30CCLK
1111 = 32 CCLK
1110
110 = 23 CCLK
111 = 27 CCLK
----- , - - - -----'-----,
~:--!!!!L.
BITS
VERTICAL BACK PORCH
00000 - 4 SCAN LINES
00001 = 6 SCAN LINES
,
,
,
,
103
110 = 28 SCAN LINES
111
32 SCAN LINES
------,-----,
J
BIT7
•
BITO
Bin.
l
.
.---.
-----
SEE IR11
.- - -.- - -.-----.- - - -.-----.----.
~~~ .~. ~I::L;Y p~II:3TE~ AD~::ss·Up:~T~
O=OFF
O=OFF
1 =ON
1 :::ON
"JBITO
H'OOOO':::O
H'0001'= 1
IR11
H 3FFF :: 16,363
'--'--'--'--'
- '
BIT7
•
BIT6
•
BITS
•
BIT4
"
BITJ
"
Blt2
"
BITl
•
BITO
~ - - - - - - - - ----S-PLITREGiSTE-R-,- - - - - - - ~
1:: ON
~
00000010 - 3 CHARACTERS
00000011 = 4 CHARACTERS
~
0000000 = ROW 1
0000001 = ROW 2
ST ART
a = OFF
IR12
~. ~SAC·TlVEB~~:RA~TE:~T:ER ;OWBIT2 .~.JBITO
IRS
•
'~' ~::~'A:P~::~E:AO~';:S:,O;;: '~'JB'TO
BITO
----,---,-----,-----,-----,
[
BIT2
SEE IR8
,---,-----,-----,
BIH
BIT6.
BITS •
BIT4 •
BIT3 •
BI12 •
Bin.
r.C""H."'R':':.C==T:::EO:r'=- ---ACTIVE CHARACTE'R"ROWS PER SCREEN----BLINK
00000oo
1 ROW
RATE
0000001 "" 2 ROWS
1R4
0= 1/64
VSYNC
1 =1/128
1111110 = 127 ROWS
VSYNC
1111111 = 128 ROWS
~--~--
BIT3.
BITO
J
11110 = 64 SCAN LINES
11111 = 66 SCAN LINES
=
IRtO
,
.~.~.~.
BIT4
VERTICAL FRONT P I O R H
000 - 4 SCAN LINES
001 = 8 SCAN LINES
BIT4
BITS.
.-----.----.
B'T'
BITO
000::: NOT ALLOWED
001 =3 CCLK
2 CCL.K
•
1110 = 15,359
1111 = 16,383
- 2(HSYNC)
~'~-I
HORIZONTAL SYNC WIDTH
BIT6
1[ R 9 :
~----~----'-----'-----'-----'-----'-----'
~
•
ISPLAY BUFFER l A S ' T " A D o R IDISPLAY
S S BUFFER FIRST ADDRESS]SB'S
0000 - 1,023
0001 = 2,047
BlTO
____..L_ _ _ , _ _ _ , _____
":"" =
RO~~,
____,
:
'I
11111110 = 255 CHARACTERS
11 1 1 1 111 = 256 CHARACTERS
~.~.~" BIT~p:IT RB~:~sT~R 2BIT2 .~.JBITO
,-----,-----,---,-----,-----,-----,
I ~, '--::. ~ .::::.
OOOO_SCANLINEO
0001 = SCAN LINE 1
BIT4
.- - -.----.
'0'
:
-----
BIT4
CURSOR
BIT3
•
BIT2
•
Bin.
UNDERLINE POSITION J
0000 - SCAN LINE 0
0001 = SCAN LINE 1
,
0=1132
1 = 1164
•
'----'---"--,--,--'--'--'
1110::SCANLINE14
1111=SCANLlNE1S
~~
O=OFF
1 = ON
,:: ON
1111111 = ROW 128
. .---.
1110=SCANLINE14
1111=SCANLINE1S
00=3SCANLN
01=1 SCAN LN
10=5 SCAN LN
11 =7 SCAN LN
LASB;TL~NE ~F C~;~OR .JBITO
0000000 = ROW 1
0000001 = ROW 2
a = OFF
BITJ.
OOOO_SCANLINEO
0001::: SCAN LINE 1
~:
BllS
CURSOR
~
IR13
BIT7
"
BIT6
~:-~-~-,-
BITO
IR14
•
BIT4
•
BIT3
•
BIT2
•
BITl
•
0001 = 2
1110= 15
1111 = 16
'----,---"----- - - - ' - - - " - - ' - - '
Figure 15" Initialization Register Formats
2,84
•
01 = DOUBLE WIDTH 01 = DOUBLE WIDTH
10= DB WD & TOPS 10= DB WO & TOPS
11 = DB WO & BOTS 11 = DB WO & BOTs
1110 = SCAN LINE 14
1111 = SCAN LINE 15
------,-----'-----'-----~----,-----,-----,
BITS
Signetics
BITO
-OO-=-N-D:-RU:-~":'~-2--"'------ -O-':-:O-E~-~""O ~J
MICROPROCESSOR DIVISION
JANUARY 1983
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'm"")"!··,,
2
LINE ADDRESS
TO CHAR GEN
LINE ADDRESS
TO CHAR GEN
LINE ADDRESS
TO CHAR GEN
z
g~
7--------
1
9SCAN
LlNESI
ROW
-e-e-e-e-e---
1
0--------
-e-e-e-e-e--
1-0-0-0-0-0--
-e-------2- 0 - - - - - - - -
2
-e--------
3
-e-------
4
-e-e-e-----
5
-e-------
6
-e-------
5-e=====
-e-e-e-e-e---
7
7
2
3
18SCAN
LINESI
ROW
-e--------
3 - 0--------
4
-e-e-e======
4-0-0-0
5-0
6
-e--------
iii
[
~
10SCAN
LlNESI
ROW
Q
g
:
-e ~~e~=====
1-00000----
-e------3-0-------
4
8
5-0
-e
7-00000----
8
o
1
6 -0--------
-e-e-e-e-e--
00000
e
3-0-------
7 -0-0-0-0-0--
-e~~e~~~~~~
5-0
64
-e-e-e-e-e--
2
-e--------
3
-e-------
4
-e-e-e-----
5
8
-e-------e-------
6
5e
-0======
-
7
-e-e-e-e-e - - -
7
-e-e-e-e-e--
1
7-00000
0---------
1
-e-e-e-e-e--
2-e======
1 -0-0-0-0-0--
1
2-0
3
-e-------3-0-------
4
-e-e-e::=====
4-0-0-0
-e-------
00000
-eee
-e;~======
3-0
42
5-0-------
6
-e~~;_;====
7-00000
2
-e-------
6 -0
7 -0-0-0-0-0--
1-00000----
4
6
NON INTERLACED
IRO=1000; TOTAL LINESIROW=9
-e
INTERLACED SYNC
IRO = 1000; TOTAL LINESIROW = 16
3-0~~~~~~~~
-eee
5-0
-e
INTERLACED SYNC AND VIDEO
IRO=0100; TOTAL LINESIROW.10
Figure 16. Interlaced Display Modes
Signetics
2·85
MICROPROCESSOR DIVISION
JANUARY 1983
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'm""""·'d
~
_________ CH~:~OW __________~
r-----,
I
BACK PORCH (IR2) --1 I-
~----~
HBLANK
--.J
r-
----j
FRONT PORCH (IR1)
IIL.________________---'II. . ____
HSYNC ____.........
----j
VBLANK
I - HSYNC (IR2) CHAR ROWs/SCREEN ( l R 4 ) - - I
~ANLINESPERROW(IRO)
r-----~L
-1 I--1
I-n . . ______________----'nL.____
FRONT PORCH (IR3)
VSYNC _ _.........
--j
r-
EQUALIZING
CONSTANT
IRO
IR2
I I
IR1
HBACK
PORCH
I I
VFRONT
PORCH
IR3
CHAR ROWS/SCREEN
IR4
BACK PORCH (IR3)
VSYNC(IR7)
LINES/ROW
HSYNC
WIDTH
I
Ir - - - - - .
-------.J
I I
VSYNC
WIDTH
VBACK
PORCH
I I
,.......,
IR7
I I I
CHARACTERS PER ROW
,
IRS
I I
Figure 17. Horizontal and Vertical Timing
will wraparound and obtain the data to be
displayed at the next screen position from
the 'display buffer first address'. If 'last
address' is the end of a character row and
a new screen start address has been loaded into the screen start register, or if 'last
address' is the last character position of
the screen, the next data is obtained from
the address contained in the screen start
register.
Note that there is no restriction in displaying data from other areas of the addressable memory. Normally, the area between
these two bounds is used for data which
can be overwritten (e.g., as a result of
scrolling), while data that is not to be overwritten would be contained outside these
bounds and accessed by means of the
automatic split screen or split screen
interrupt feature of the AVDC.
IR10[7:0) - Display Pointer
Address Lower
IR11[5:0) - Display Pointer
Address Upper
These two fields define a buffer memory
address for AVDC controlled accesses in
2·86
response to 'read/write at pointer' commands. They also define the last buffer
memory address to be written for the
'write from cursor to pOinter' command.
IR1117) - Scan Line Zero During
Scroll Down
This field specifies normal scan line count
of all scan line zero counts for the new
characier row that occurs at the top of the
scrolling area during soft scroll down
operation. If the character generator provides blanks during scan line zero, this will
cause the new row to be automatically
blanked on the display. This feature can
be used, if necessary, to blank the new
row until the CPU places 'blank data' into
the display buffer.
IR1116)- Scan Line Zero
During Scroll Up
This field specifies normal scan line count
of all scan line zero counts for the new
character row that occurs at the bottom of
the scrolling area during soft scroll up
operation. See above.
Signetics
IR1217) -
Scroll Start
This bit is asserted. when soft scroll is to
take place. The scrolling area begins at
the row specified in split register 1
(IR12[6:0]). If set, the first row to scroll
scan line count will be reduced by the
value in the lines to scroll register
(IR14[3:0]). The scan line count of this row
will start at the programmed offset value.
When this bit is asserted, scroll end
IR13[7) must be set before split 2.
IR1216:0) - Split Register 1
Split register 1 can be used to provide
special screen effects such as soft (scan
line by scan line) scrolling, double height!
width rows, or to change the normal addressing sequence of the display memory.
The contents of this field is compared, in
real time, to the current row number. Upon
a match, the AVDC sets the split screen 1
status bit, and issues an interrupt request
if so programmed. The status change/
interrupt request is made at the beginning
of scan line zero of the split screen character row. If enabled by the SPL 1 bit of
screen start register 2, an automatic split
screen to the address specified in screen
MICROPROCESSOR DIVISION
JANUARY 1963
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'm",,!"'··',
start register 2 will be made for the desig·
nated character row. During a scroll opera·
tion, this field defines the first character
row of the scrolling area.
IR13[7] -
Scroll End
This field specifies that the row pro·
grammed in split register 2 (IRI3[6:0]) is to
be the last scrolling row of the scrolling
area. Note that this bil must be asserted
for a valid row only when the scroll start
bit IRI2[7] is also asserted.
IR13[6:0] -
Split Register 2
This field is similar to the split register 1
field except for the following:
1. Split screen 2 status bit is set.
2. During a scroll operation, this field
defines the last character row of the
scrolling area. This row will be followed
by a partial row. The LTSR (IRI4) value
replaces the normal scan lines/row
value for the partial row, thus keeping
the total scan lines/screen the same.
3. If enabled by the SPL2 bit of screen
start register 2, an automatic split to
the address contained in screen start
register 2 will occur in one of two ways:
a) If not scrolling an automatic split will
occur for the next character row. b) If
scrolling, the automatic split will occur
after the partial row being scrolled onto
or off the screen.
4. The specified double width and height
conditions (IRI4) are also asserted in
two possible ways: a) Automatic split
will assert the programmed condition
for the current row. b) During soft scroll
operation the programmed conditions
are asserted for the partial row scroll·
ing onto or off the screen.
toggling between tops and bottoms is
disabled.
IR14[S:4]- Double 2
This field specifies the conditions (double
width/height or normal) of the row desig·
nated in split register 2 (I RI3[6:0). Not
used when IRO[7] = 1.
IR14[3:0] -
Lines to Scroll
This field defines the scan line increment
to be used during a soft scroll operation.
This value will only be used when scroll
start (IRI2[7]) and scroll end (IRI3[7]) are
enabled.
Timing Considerations
Normally, the contents of the initialization
registers are not changed during normal
operation. However, this may be neces·
sary to implement special display features
such as multiple cursors and horizontal
scrolling. Table 2 describes timing details
for these registers which should be con·
sidered when implementing these
features.
DISPLAY CONTROL REGISTERS
Double 1
There are seven registers in this group,
each with an individual address. Thei-r for·
mats are illustrated in figure 15. The com·
mand register is used to invoke one of 19
possible AVDC commands as described in
the COMMANDS section of this data
sheet. The remaining registers in the
group store address values which specify
the cursor location, the location of the
first character to be displayed on the
screen, and any split screen address loca·
tions. The user initializes these registers
after powering on the system and changes
their values to control the data which is
displayed.
This field specifies the conditions (double
width/height or normal) of the row desig·
nated in split register 1 (IRI2[6:0]). When
double height tops or bottoms has been
specified, the AVDC will automatically
toggle between tops and bottoms until
another split 1 or 2 occurs which changes
the double height/width condition. If a
double height tops row is specified, the
scan line count will start at zero and incre·
ment the scan line count every other scan
line. If a double height bottom row is
specified, the AVDC will start at one half
the normal scan line total. If double width
is specified, the AVDC will assert the
DADD9/DW output at the falling edge of
blank. This condition will also remain ac·
tive until the next split 1 or 2. When
I RO[7]= 1, the values written into bits 7
and 6 of screen start 1 upper will also be
written into IRI4[7:6] and the automatic
The screen start 1 registers contain the
address of the first character of the first
row (upper left corner of the active
display). At the beginning of the first scan
line of the first row, this address is trans·
ferred to the row start register (RSR) and
into the memory address counter (MAC).
The counter is then advanced sequentially
at the character clock rate for the number
of times programmed into the active char·
acters per row register (IR5), thus reaching
the address of the last character of the
row plus one. At the beginning of each
subsequent scan line of the first row, the
MAC is reloaded from the RSR and the
above sequence is repeated. At the end of
the last scan line of the first row, the con·
tents of the MAC is loaded into the RSR to
serve as the starting memory address for
IR14[7:6] -
Screen Start Registers 1 and 2
Signetics
the second character row. This process is
repeated for the programmed number of
rows per screen. Thus, the data in the
display memory is displayed sequentially
starting from the address contained in the
screen start register. After the ensuing
vertical retrace interval, the entire process
repeats again.
During vertical blanking, the address
counter operation is modified by stopping
the automatic load of the contents of the
RSR into the counter, thereby allowing the
address outputs to free·run. This allows
dynamic memory refresh to occur during
the vertical retrace interval. The refresh
addressing starts at the last address
displayed on the screen and increments
by one for each character clock during the
retrace interval. If the display buffer last
address is encountered, refreshing con·
tinues from the display buffer first
address.
The sequential operation described above
will be modified upon the occurrence of
anyone of three events. First, if during the
incrementing of the memory address
counter the 'display buffer last address'
(lR9[7:4]) is reached, the MAC will be
loaded from the 'display buffer first
address' register (IR9[3:0] and IR8[7:0]) at
the next character clock. Sequential oper·
ation will then resume starting from this
address. This wraparound operation
allows portions of the display buffer to be
used for purposes other than storage of
displayable data and is completely auto·
matic without any CPU intervention (see
figure 19a).
The sequential row to row addressing can
also be modified via split register 1 (IRI2)
and split register 2 (IRI3), under CPU con·
trol, or by enabling the row table address·
ing mode. If bit 6 of screen start register 2
upper (SPL 1) is set, the screen start regis·
ter 2 contents will be loaded automatically
into the RSR at the beginning of the first
scan line of the row designated by split
register 1 (lRI2[6:0]). If bit 7 of screen start
2 upper (SPL2) is set, the screen start reg·
ister 2 contents is automatically loaded
into the RSR at the end of the last scan
line of the row designated by split register
2 (IRI3[6:0]). SPL 1 and SPL2 are write only
bits and will read as zero when reading
screen start register 2.
If the contents of screen start register 1
(upper, lower, or both) are changed during
any character row (e.g., row 'n'), the start·
ing address of the next character row (row
'n + 1') will be the new value of the screen
start register and addressing will continue
2·87
2
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2674
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
'm",,""-'"
Table 2 TIMING CONSIDERATIONS
PARAMETER
sequentially from there. This allows fea·
tures such as split screen operation, par·
tlal scroll, or status line display to be
implemented. The split screen interrupt
feature of the AVDC is useful in control·
ling the CPU initiated operations. Note
that In order to obtain the correct screen
display, screen start register 1 must be
reloaded with the original (origin of dis·
play) value prior to the end of the vertical
retrace. See figure 19b.
TIMING CONSIDERATIONS
First line of cursor
Last line of cursor
Underline line
These parameters must be established at a
minimum of two character times prior to their
occurrence
Double height character rows
Double width character rows
Rows to scroll
Set/reset prior to the row specified in spilt 1
or 2 registers
Cursor blink
Cursor blink rate
Character blink rate
New values become effective within one field
after values are changed
Split register 1
Split register 2
Change anytime prior to line zero of desired
row
Character rows per screen
Change only during vertical blanking period
Vertical front porch
Change prior to first line of VFP
Vertical back porch
Change prior to fourth line after VSYNC
Screen start register 1
Row table mode enable
Change prior to the horizontal blanking
interval of the last line of character row
before row where new value is to be used
When row table addressing mode is en·
abled, the first address of the row table is
designated In SSR2. The AVDC fetches
the next row's starting address from the
table during the blanking interval prior to
the first scan line of each character row
and loads it into SSR1 for use as the start·
ing address of the next row. Since the con·
tents of SSR2 changes as the table entries
are fetched, it must be re·initiallzed to
point to the first table entry during each
vertical retrace interval.
The values in the two MSBs of SSR1 upper
are multiplexed onto the DADD1/DADD14
and DADD2/DADD15 outputs during the
BI17
BIT6
BITS
Sif4
BIT3
BI12
BITO
BIT1
COMMAND CODe
see COMMANDS SECTION FOR COMMAND CODES
COMMAND REGISTERS (WRITE ONLY)
BI17
BI16
BITS
81f4
BI13
BIT2
81T1
BITO
BI17
BITS
BIT6
BIT4
BI13
H'OooO' = 0
DADD15
BIT1
BITO
NOTE: MSS's ARE IN
UPPER REGISTER (5:0]
H'Ooo1' .. 1
THRU
MSS's
DADD14
BIT2
LOWER REGISTER (LSB)
UPPER REOISTER
H'3FFE' _16,382
H'3FFF' '" 16,383
NOTES:
1. Bits 7 and 6 of upper register are not used in the cursor address register.
2. Bits 7 and 6 of upper register are always zero when read by the CPU.
3. When IAO[7] = 1, the values written into bits 7 and 6 of screen start 1 upper will also be written Into IR14[7:B1 to control the double width and double
height attributes of the display as follows:
L
~
Attribute
1
1
0
1
0
1
None
Double width only
Double width and double height tops
Double width and double height bottoms
o
o
SCREEN START 1 REGISTERS (READ AND WRITE)
CURSOR ADDRESS REGISTERS (READ AND WRITE)
BIT7
BITS
BITS
BIT4
BIT3
BIT2
81T1
BITO
BIT7
BITS
BITS
UPPER REGISTER
SPL2
O=OFF
1=ON
SPL1
O=OFF
1=ON
H'OOOO' =0
H'ooo1'-1
MSB's
THRU
H'3FFE' = 16,382
H'3FFF' = 16,363
NOTE:
Bit 7 and bit 6 are always zero when read by CPU.
SCREEN START 2 REGISTERS (READ AND WRITE)
Figure 18. Display Control Register Formats
2·88
BIT4
BIT3
BIT2
BIT1
BITO
LOWER REGISTER (LSB)
Signetics
NOTE: MSB's ARE IN
UPPER REGISTER [5:01
MICROPROCESSOR DIVISION
JANUARY 1983
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'am'"'''''·'''
falling edge of BLANK. If I RO[7] = 0, these
two bits act as memory page select bits
which may be used to extend the display
memory addressing range of the AVDC up
to 64K. In that case, these two bits act as a
two-bit counter which is incremented each
time that 'wraparound' occurs (see above).
Note that the counter is incremented at
the falling edge of BLANK and that for
proper display operation the wraparound
address should be programmed to occur
at the last character position of a row.
Also, the first address accessed in the
new page will be the address contained in
the display buffer first address register
(IR9[3:0] and IR8[7:0]).
-
DISPLAY BUFFER START
2
BOTTOM OF SCREEN.
SCREEN START-
h'""""'....."'"""""'c1
MONITOR
DISPLAY
1-"--"--''""''-'>''''>''''>''''''---''--1- DISPLAY BUFFER END
Cursor Address Registers
16K L-_ _ _ _ _-'
The contents of these registers define the
buffer memory address of the cursor. The
cursor output will be asserted when the
memory address counter matches the
value of the cursor address registers for
the scan lines specified in IR6. The cursor
address registers can be read or written by
the CPU or incremented via the 'increment
cursor address' command. In independent
buffer mode, these registers define a buffer memory address for AVDC controlled
access in response to 'read/write at cursor
with/without i ncremen!' commands, or the
first address to be used in executing the
'write from cursor to pointer' command.
MEMORY
(a) DISPLAY MEMORY WRAPAROUND
. . DISPLAY BUFFER START
-
BOTTOM OF SCREEN
INTERRUPT/STATUS REGISTERS
The interrupt and status registers provide
information to the CPU to allow it to interact with the AVDC to effect desired
changes that implement various display
operations. The interrupt register provides
information on five possible interrupting
conditions, as shown in figure 20. These
conditions can be selectively enabled or
disabled (masked) from causing interrupts
by certain AVDC commands. An interrupt
condition which is enabled (mask bit equal
to one) will cause the INTR output to be
asserted and will cause the corresponding
bit in the interrupt register to be set upon
the occurrence of the interrupting condition. An interrupt condition which is disabled (mask bit equal to zero) has no
effect on either the I NTR output or the
interrupt register.
The status register provides six bits of
status information: the five possible inter·
rupting conditions plus the RDFLG bit.
For this register, however, the contents
are not affected by the state of the mask
bits.
Descriptions of each interrupt/status register bit follow. Unless otherwise indicated, a bit, once set, will remain set until
1-"--"-""">"""---"--'--"--'--'1 -
DISPLAY BUFFER END
MONITOR
DISPLAY
16K L-_ _ _ _ _..J
MEMORY
(b) DISPLAY MEMORY SPLIT SCREEN WITH WRAPAROUND
Figure 19. Display Addressing Operation
reset by the CPU by issuing a 'reset interrupt/status bits' command. The bits are
also reset by a 'master reset' command
and upon power-up.
SR[5] -
RDFLG
This bit is present in the status register
only. A zero indicates that the AVDC is
currently executing the previously issued
delayed command. A one indicates that
the AVDC is ready to accept a new delayed
command.
I/SR[4] -
VBLANK
Indicates the beginning of a vertical blanking interval. Set to one at the beginning of
the first scan line of the vertical front porch.
Signetics
I/SR[3] -
Line Zero
Set to one at the beginning of the first
scan line (line 0) of each active character
row.
I/SR[2] -
Split Screen 1
This bit is set when a match occurs between the current character row number
and the value contained in split register 1,
IR12[6:0]. The equality condition is only
checked at the beginning of line zero of
each character row.
I/SR[1] -
Ready
The delayed commands affect the display
and may require the AVDC to wait for a
2·89
JANUARY 1983
MIC.ROPROCESSOR DIVISION
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'm",,11".'ij
BIT&
81Tt
I
NOT USED
ALWAYS READ AS 0
!
*
BITS
81T4
81T3
81T2
81T1
BITO
LINE
RDFLG
.
O=BUSY
1 = READY
VBLANK
ZERO
SPLIT 1
READY
$PlIT2
O=NO
1=YES
O=NO
1=YES
O=NO
1=YES
('=BUSY
1 = READY
O=NO
1=YES
STATUS REGISTER ONLY. ALWAYS 0 WHEN READING INTERRUPT REGISTER.
IISR[O] -
Split Screen 2
This bit is set when a match occurs between the current character row number
and the value contained in split register 2
(IR13[6:0]) when you are not scrolling. It is
set for the value contained in (split screen
register 2) + 1 when scrolling.
COMMANDS
The AVDC commands are divided into two
classes: the instantaneous commands
which are executed immediately after they
are invoked, and the delayed commands
which may need to wait for a blanking in·
terval prior to their execution. Command
formats are shown in table 3. The commands are asserted by performing a write
operation to the command register with
the appropriate bit pattern as the data
byte.
Instantaneous Commands
The instantaneous commands are ex·
ecuted immediately after the trailing edge
of the WR pulse during which the command is issued. These commands do not
affect the state of the RDFlG or READY
interrupt/status bits and can be invoked at
any time.
Master Reset
This command initializes the AVDC and can
be Invoked at any time to return the AVDC
to Its initial state. Upon power·up, two
successive master reset commands must
be applied to release the AVDC's internal
power on circuits. In transparent and
shared buffer modes, the CNTRl1 input
must be high when the command is issued.
The command causes the following:
1. VSYNC and HSYNC are driven low for
the duration of the command and
BLANK goes high. After command
completion, HSYNC and VSYNC will
begin operation and BLANK will remain
high until a 'display on' command is
received.
2·90
Disables cursor operation. Cursor output
Is placed in the low state.
Cursor On
Enables normal cursor operation .
Reset Interrupt/Status Bits
Figure 20. Interrupt and Status Register Format
blanking interval before enacting the com·
mand. This bit is set to one when execu·
tion of a delayed command has been com·
pleted. No other delayed command should
be invoked until the prior delayed com·
mand is completed.
Cursor Off
2. The interrupt and status bits and
masks are set to zero, except for the
RDFlG flag which is set to a one.
3. The row buffer mode, cursor-off,
display·off, and line graphics disable
states are set.
4. The initialization register pointer is set
to address IRO.
5. IR2[7) is reset.
Load IR Address
This command is used to preset the initialization register pointer with the value 'V'
defined by D3-DO. Allowable values are 0
to 14.
Enable Graphics
After invoking this command, the AVDC
will increment the MAC to the next consecutive memory address for each scan
line even if more than one scan line per
row is programmed. This mode can be
used for bit-mapped graphics where each
location in the display buffer within the
defined area contains the bit pattern to be
displayed. This command is row buffered
and should be asserted during the
character row prior to the row where this
feature is required. This allows the user to
enter and exit graphics mode on character
row boundaries.
To perform split screen operations while
in graphics mode use SSR2 only.
DADDO/lG is asserted during the trailing
edge of BLANK for each scan line while
this mode is active.
Disable Graphics
Normal addressing resumes at the next
row boundary.
Display Off
Asserts the BLANK output. The DADDO
through DADD13 display address bus out·
puts can be optionally placed in the three·
state condition by setting bit 2 to a '1'
when invoking the command.
Display On
Restores normal blanking operation either
at the beginning of the next field (bit 2= 1)
or at the beginning of the next scan line
(bit 2=0). Also returns the DADDO·DADD13
drivers to their active state.
Signetics
This command resets the designated bits
in the interrupt and status registers. The
bit positions correspond to the bit positions in the registers:
Bit 0 - Split 2
Bit 1 - Ready
Bit 2 - Split 1
Bit 3 - Line zero
Bit 4 - Vertical blank
Disable Interrupts
Sets the interrupt mask to zeros for the
designated conditions, thus disabling
these conditions from being set in the interrupt register and asserting the INTR
output. Bit position correspondence is as
above.
Enable Interrupts
This command writes the associated interrupt mask bits to a one. This enables the
corresponding conditions to be set in the
interrupt register and asserts the INTR
output. Bit position correspondence is as
above.
Delayed Commands
This group of commands is utilized for the
independent buffer mode of operation, although the 'increment cursor' command
can also be used in other modes. With the
exception of the 'write from cursor to
pointer' and 'increment cursor' commands, all the commands of this type will
be executed immediately or will be
delayed depending on when the command
is invoked. If invoked during the active
screen time, the command is executed at
the next horizontal blanking interval. If
invoked during a vertical retrace interval or
a 'display off' state, the command is executed immediately.
The 'increment cursor' command is executed immediately after it is issued and reo
quires approximately three CCLK periods
for completion. The 'write from cursor to
pointer' command executes during blanking intervals. The AVDC will execute as
many writes as possible during each
blanking interval. If the command is not
completed during the current blanking in·
terval, the command will be held in suspension during the next active portion of
the screen and continues during the next
blanking interval until the command is
completed.
MICROPROCESSOR DIVISION
JANUARY 1983
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'wn""".,.,
In all cases, the AVDC will assert the
READY/RDFLG status to signify completion of the delayed command. No other
delayed command should be given until
the previous delayed command has completed. Therefore, the READY interrupt
or RDFLG status flag should be used
for handshaking control between the
AVDC and CPU when using the delayed
commands.
Table 3
07
06
AVDC COMMAND FORMATS
05
04
03
02
01
DO
COMMAND
Master reset
Load IR pointer with value V
(V=O to 14)
Disable graphics
Enable graphics
Display off. Float DADO bus if N = 1
Display on: Next field (N = 1) or scan
line (N=O)
Cursor off
Cursor on
Reset interrupt/status: Bit reset
where N= 1
Disable interrupt: Disable where
N=1
Enable interrupt: Enables interrupts
where N= 1
Instantaneous Commands:
0
0
0
0
0
0
0
1
0
V
0
V
0
V
0
V
0
0
0
0
0
0
0
0
1
1
1
1
d
d
d
d
d
d
1
1
d
d
N
N
1
1
d
d
01
12
01
12
Transfers data between the display buffer
and the bus interface latch using the address contained in the pointer registers.
0
0
0
0
0
1
1
1
0
1
1
N
d
d
N
d
d
N
d
d
N
01
12
N
Read/Write at Cursor
1
0
0
N
N
N
N
N
Transfers data between the display buffer
and the bus interface latch using the address contained in the cursor registers.
0
1
1
N
N
N
N
N
V
B
L
Z
S
P
1
R
0
Y
S
P
2
Read/Write at Pointer
Increment Cursor
Adds one (modulo 16K) to the cursor address registers.
Delayed Commands:
Read/Write at Cursor and
Increment
Transfers data between the display buffer
and the bus interface latch using the address contained in the cursor registers
and then adds one (modulo 16K) to the cursor address registers.
Write from Cursor to Pointer
Writes the data contained in the bus interface latch into the block of display memory designated by the cursor address and
pointer address registers, inclusive. After
completion of the command, the pOinter
address will be unchanged, but the cursor
register contents will be equal to the
pointer address.
Interrupt Bit
Assignments
Hex
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
0
1
0
0
0
1
0
0
1
A4
A2
A9
AC
AA
AD
1
0
1
0
1
0
1
1
AB
1
0
1
1
1
0
1
1
BB
1
0
1
1
1
1
0
1
BD
NOTES:
1. Any combination of these three commands is valid.
Read at pointer address
Write at poi nter add ress
Increment cursor address
Read at cursor address
Write at cursor address
Read at cursor add ress and
increment address
Write at cursor address and
increment address
Write from cursor address to pointer
address
Read from cursor address to pointer
address
2. Any combination of these three commands IS valid.
3. d=don't care.
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER
DC ELECTRICAL CHARACTERISTICS
PARAMETER
V IL
V IH
VOL
VOH
IlL
ILL
100
Icc
Input low voltage
Input high voltage
Output low voltage
Output high voltage
(except INTR output)
Input leakage current
Data bus 3-state
leakage cu rrent
INTR open drain output
leakage current
Power supply current
UNIT
RATING
o to
Operating ambient temperature 2
Storage temperature
All voltages with respect to ground 3
+ 70
-65 to + 150
-0.5 to +6.0
'c
'c
V
TA = O'C to + 70'C V ce =5.0V +
- 5%4,5,6
TEST CONDITIONS
LIMITS
Min
Typ
Max
0.8
0.4
V
V
V
2.0
IOL=2.4mA
UNIT
10H = -2001'A
VIN=O to Vec
2.4
-10
10
V
I'A
Vo=O to Vee
-10
10
I'A
10
160
I'A
mA
Vo=O to Vee
Signetics
2·91
2
JANUARY 1983
MICROPROCESSOR DIVISION
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'IfIn""".",
AC ELECTRICAL CHARACTERISTICS TA=O'C to + 70'C, vcc= 5.0V ± 5%4,5,6,7,8
TENTATIVE LIMITS
PARAMETER
TEST CONDITIONS
2.7MHz
Min
Bus Timing (Fig. 21)9
t AS
AO·A2 setup time to WR, Rf5 low
AO·A2 hold time from WR, Rf5 high
tAH
CE setup time to WR, RD low
tcs
CE hold time from WR, RD high
tCH
WR, RD pulse width
tRW
Data valid after RD low
too
Data bus floating after RD high
tOF
Data setup time to WR high
tos
Data hold time from WR high
tOH
High time from CE to CE
tcc
Consecutive commands
Other accesses
30
0
0
0
250
Row Table Input Timing (Fig. 24)
Data setup time to CCLK low
tOSRT
Data hold time from CCLK low
tOHRT
NOTES
1. Stresses above those listed u ndar Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of
the device at these or at any other condition above those In the operation section
of this specification is not implied.
2. For operating at elevated temperatures, the device must be derated based on
+ 15QDC maximum junction temperature.
3. This product Includes circuitry specifically designed forthe protection of its inter·
nal devices from damaging effects of excessive static charge. Nonetheless, it is
suggested that conventional precautions be taken to avoid applying any voltages
larger than the rated maxima.
4. Parameters are valid over specified temperature range.
2·92
30
0
0
0
200
150
10
150
5
tccp
300
tccp
300
ns
ns
200
100
370
125
125
10,000
250
100
100
10,000
ns
ns
ns
40
175
40
150
ns
40
225
40
200
ns
tccp
+30
225
225
225
600
BACK high from PBREQ low
BEXT high from PBREQ high
INTR low from CCLK low
INTR high from WR, RD high 9
ACLL from HSYNC
Max
ns
ns
ns
ns
ns
ns
ns
ns
ns
Other Timings (Fig 23)
t ROl
READY/RDFLG low from WR hlgh 9
tSAK
tSXT
tlRl
tlRH
t AC
Min
200
100
CCLK Timing (Fig 22, 23, 24)
CCLK period
tccp
CCLK high time
tCCH
CCLK low time
tCCl
Output delay from cctR: edge
DADDO·13, MBC
tccOl
BLANK, HSYNC, VSYNC/CSYNC,
tCC02
CURSOR, BEXT, BREQ, BACK,
BCE, WDB, RDB10
UNIT
4.0MHz
Max
tccp
+30
200
200
200
600
3xtccp
3xtccp
ns
ns
ns
ns
ns
ns
100
60
60
60
ns
ns
5. All voltage measurements are referenced to ground (GND).
6. Typical values are at + 25°C, typical supply voltages, and typical processing
parameters.
7. For testing, all input signals swing between O.4V and 2.4V with a transition time of
20ns maximum. All time measurements are referenced at input voltages of O.8V
and 2.0V and output voltages of O.SV and 2.0V as appropriate.
S. Test condition for outputs: CL 150pF.
.9. Timing is Illustrated and specified referenced to WR and RiS inputs. Device may
also be operated with CE as the 'strobing' input. In this case, all timing speciflca·
ti~)I'Js apply referenced to falling and rising edges of CE.
10. BCE, Wi5B, and Ri5B delays track each other within 10nsec. Also, these output
delays will tend to follow direction (minimax) of DADDO-13 delays.
Signetics
=
MICROPROCESSOR DIVISION
JANUARY 1983
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'm",,""··"
AO-A2
~----:-
_ _ __
2
00-07
FLOAT
(READ)
\--IDS
I
C:~il~ ________---J~
I-IDH
VALID
I ~t..
V
CE, RD, WRI
_ _ _ _ __
_ _ _ _ _ _ _ _ _ _ _ _ _...IA-ICC
j
'--_ _
NOTE
1. Any two must be high for
tee.
Figure 21. Bus Timing
ICCD'
ICCD2
OUTPUTS
(NOTE 1)
-------1
I--+l-ICCDI
NOTES
1. DADDO-DADDI3, BLANK, HSYNC, CSYNCIVSYNC, CURSOR, BEXT, BREQ,
MBC, BACK.
2. !roE CHANGES STATE ON BOTH ccrK EDGES-(see Figures 3 and 4)
.Q!UP.!!!§
WDB, RDB, BCE
BCE:
Figure 22.
CCI:K Timing
Signefics
2·93
MICROPROCESSOR DIVISION
JANUARY 1983
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
SCN2674
'm""""··ij
BLANK
r
_ _- - J
VERTICAL
BLANKING
INTERVAL
1st HSYNC
OFVBLANK
HSYNC
VB LANK
STATUS BIT
BLANK
DADDODADD13
LINE ZERO AND SPLIT
SCREEN STATUS BITS
HSYNC~
~~2------------~-----
BLANK
I
u __ _
NORMAL·------------i-I~:~F~p:n~SC~A~N~L~IN~E~~~II~----------________~-----------VSYNC
(ACLL=1)_ _ _ _ _---iI_ _2212~---..
-I
-------+--~~------------~I~------22
-
ACLL_
I
I
DELAYED
VSYNC·_ _ _ _ _ _ _+-~12_-------------~2_2---'VFP= n +3 SCAN LINES
-----i.~1
r-1
._
.
_
Figure 23. Other Timings
2·94
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
SCN2674
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
'mU"nel.i N
WRFORA
DELAYED
COMMAND
READY OR
RDFLG
STATUS BITS
~
\\:.....--
2
.,"~:=~
INTERRUPT
IIRH
iNrR
/
Figure 23. Other Timings (Continued)
I
I
tCCD1-!
_M_B_C____________
CURSOR
I-
-J;'r--------~------------~-------------------
tCCD2~
I-
tCCD1-l
I-
;'---------+----------~--------~\~-----
_DA_D_D_ _ _ _ _ _ _JXr-S-S-R2-A-D-D-RE-S-S-;X SSR2 ADDRESS + 1
X"-________
-JX"-_____
-ltDSRT\- tDHRT-l-ltDSRT\- tDHRT-j
r--------
------------------~
DO-D7
Figure 24. Row Table Fetch 1/0 Timing
Signetics
2·95
MICROPROCESSOR DIVISION
JANUARY 1983
ADVANCED VIDEO DISPLAY CONTROLLER (AVDC)
'Q,tuM'
EVEN FIELD
LAST DISPLAYED
SCAN OF
PREVIOUS FIELD
'\
~
VERTICAL FRONT PORCH
--+
VERTICAL SYNC PULSE
+-
SCN2674
VERTICAL BACK PORCH
CSYNC~
~l
BLANK""U-!""
_ _ _ _ _ _ _ _ _ _ _ _ VERTICAL BLANKING INTERVAL
ODD FIELD
LAST DISPLAYED
SCAN OF
EVEN FIELD
I-- VERTICAL FRONT PORCH-112 H
+
VERTICAL SYNC PULSE
1
CSYNC~
--II
FIRST DISPLAYED SCAN
OF EVEN FIELD
HORIZONTAL
SYNC
/
~SES
__________
l~_LJL
t-
---I
~
VERTICAL BACK PORCH-112 H
112 H
I--
---l
-11-
1/2 HORIZONTAL SYNC ...
~l
B L A N K J ' "__
U
--- - - - - - - - - - V E R T I C A L BLANKING INTERVAL
FIRST DISPLAYED
SCAN OF
ODD FIELD
!
~
I
-I HPERIOD
~
l~
HORIZONTAL BLANKING INTERVAL
NOTES
1. In non-interlaced operation the eve!"! field Is repeated continuously.
2. In Intarlaced operation the even field alternatss with the odd field.
Figure 25. Composite Sync Timing
2·98
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC)
SCB2675
'gm "..IIeI. 'ti
DESCRIPTION
FEATURES
The Signetics SCB2675 Color/Monochrome Attributes Controller (CMAC) is a
bipolar LSI device designed for CRT terminals and display systems that employ
raster scan techniques. It contains a programmable dot clock divider to generate a
character clock, a high speed shift register to serialize input dot data into a video
stream, latches and logic to apply visual
attributes to the resulting display, and
logic to display a cursor on the display.
• 25 and 18MHz video dot rate versions·
• Four video intensities encoded on two
TTL outputs (monochrome mode)
• Eight foreground and background
colors encoded on three TTL outputs
(color mode)
• Internally latched character attributes:
- Reverse video
- Blank
- Blink
- Underline
- Highlight
- Two general purpose
- Eight foreground colors
- Eight background colors
- Dot width control
- Double width characters
• VT100 compatible attributes
• Reverse video cursor with optional
white cursor in color mode
• Up to 10 dots per character
• Light or dark background in
monochrome mode
- Automatic retrace blanking
• Programmable dot stretching
• Compatible with SCN2674 AVDC and
SCN2670 DCGG
• TTL compatible
• 40·pin dual in·line package
The CMAC provides control of visual attributes on a character by character basis for
two operating modes: monochrome and
color. The monochrome mode provides
reverse video, blank, highlight and two
general purpose user definable attributes.
In this mode, the display characters can
be specified to appear on either a light or
dark screen background. Retrace video
suppression can be automatically or externally controlled. The color mode provides
eight colors for foreground (character)
video and eight colors for background
video together with a luminance output for
external color set selection or to simultaneously drive a monochrome monitor.
Additionally, both modes provide double
width, underline, blink, dot stretching and
dot width attributes. In monochrome
mode, the SCB2675 emulates the attribute
characteristics of Digital Equipment Corporation's VT100 terminal.
The horizontal dot frequency is the basic
timing input to the CMAC. This clock is
divided internally to provide a character
clock output for system synchronization.
Up to ten bits of dot data are parallel
loaded into the video shift register on
each character boundary. The two TTL
video data outputs in monochrome mode
are encoded to provide four video intensities (black, gray, white and highlight).
The video data in color mode is encoded
to provide eight foreground colors and
shifted out on three TTL outputs, together
with the luminance output.
PIN CONFIGURATION
Vee
2
DO
D2
D4
D6
C1
CO
CCLK
DCLK
DOrM
DOTS
BLINK
MIC
BLANK
BLUEITTLV2
UL
REDITTLV1
GREENIGP1
ADOUBLE
RESET
LUMIGP2
ABLINK
AGREENFI
BKGND
AGREENBI
ARVID
AUL
AREDFIAHILT
GND
AREDBIAGP1
APPLICATIONS
ADOTM
ABLUEFI
ABLANK
ABLUEB/AGP2
TOP VIEW
• CRT terminals
• Word processing systems
• Small business computers
• For faster versions consult factory.
ORDERING CODE
Vcc
PACKAGES
Ceramic DIP
Plastic DIP
Ceramic DIP
Plastic DIP
DOTS PER
CHARACTER
=5V:!: 5%, O°C to
+ 70 0 C
25MHz
18MHz
7,8,9,10
SCB2675BC5140
SCB2675BC5N40
SCB2675BC8140
SCB2675BC8N40
6,8,9,10
SCB2675CC5140
SCB2675CC5N40
SCB2675CC8140
SCB2675CC8N40
Signetics
2·97
MICROPROCESSOR DIVISION
JANUARY 1983
COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC)
SCB2675
'm",,",'··',
PIN DESIGNATION
MNEMONIC
Vee
PIN NO.
TYPE
40
I
NAME AND FUNCTION
Power Supply: + 5VDC
Vee
1
I
Bias Supply: See figure 5
GND
20
I
Ground: OV reference
DCLK
32
I
Dot Clock: Dot frequency input. Video output shift rate.
CCLK
33
0
Character Clock: An output which is a submultiple of DCLK. The period ranges from 7 to 10
DCLK periods per cycle and is determined by the state of the CO-C1 inputs.
REDITTLV1
28
0
Red/TTL Video 1: In color mode, this output provides the red gun serial video. In
monochrome mode, it should be. used with the bluelTTL video 2 output to decode four video
intensities.
BLUEITTLV2
29
0
Blue/TTL Video 2: In color mode, this output provides the blue gun serial video. In
monochrome mode, it.should be used with the redlTTL video 1 output to decode four video
intensities.
GREENIGP1
27
0
Green/General Purpose 1: In color mode, this output provides the green gun serial video. In
monochrome mode, it' is a general purpose TTL output which Is asserted if the
AREDBIAGP1 input is asserted when the corresponding character dot data is loaded into
the video shift register.
LUMIGP2
26
o
Luminance/General Purpose 2: In color mode, this output is the logical-OR of the RGB fore·
ground video. It is low during a blanking interval and during the foreground portion of the
cursor display. In monochrome mode, it is a general purpose TTL output which is asserted if
the ABLUEB/AGP2 input is asserted when the corresponding character dot data is loaded
into the video shift register.
UL
13
I
Underline Timing: Indicates the scan line(s) for the underline attribute. Latched on the
falling edge of BLANK.
.
BLINK
11
Blink Timing: This input is sampled on the falling edge of BLANK to provide the blink rate
for the blink attribute. Should be a submultiple of the frame rate.
BLANK
12
Screen Blank: When high, this input forces the video outputs to the specified background
color in color mode and to the level specified by the BKGND input (either black or gray) in
monochrome mode.
RBLANK
7
Retrace Blank: This input is used to force the video outputs to a low during retrace periods. If
pulled high, it will automatically suppress video during the retrace periods when BLANK Is
high. The user may also pulse this input while BLANK Is high to selectively suppress raster
video.
AGREENFIBKGND
17
Graen Foreground/Background Intensity: In color mode, this input activates the GREEN/
GP1 output during the foreground (character video) portion of the associated character
block. In monochrome mode, this input specifies gray or black screen background.
ABLUEFIABLANK
23
Blue Foreground/Blank Attribute: In color mode, this input activates the BLUE/TTLV2
output during the foreground (character video) portion of the associated character block. In
monochrome mode, this input generates a blank space for the associated character. The
blank space intensity is controlled by the AGREENFIBKGND input, the reverse video
attribute and cursor input.
AREDFIAHILT
25
Red Foreground/Highlight Attribute: In color mode, this input activates the RED/TTLV1
output during the foreground (character video) portion of the associated character block. In
monochrome mode, this input highlights the associated character (including underline).
CURSOR
8
Cursor Timing: This input provides the timing for the cursor video. In color mode, with
CURSOR and CMODE high, the RGB outputs are driven high (white cursor). if CMODE is low,
or in monochrome mode, this input reverses the intensities of the video and attributes.
Cursor position, shape, and blink rate are controlled by this input.
CMODE
9
Cursor Mode: Used in color mode only. When CURSOR and CMODE are high, the RGB
outputs are driven high (white cursor). When CURSOR is high and CMODE is low, the RGB
outputs are logically inverted (reverse video cursor).
AUL
19
Underline Attribute: Specifies a line to be displayed In the character block. The specific
line(s) are specified by the UL input. All other attributes apply to the underline video.
2·98
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC)
SCB2675
'm""",'··,,
PIN DESIGNATION (Continued)
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
ABLINK
16
Blink Attribute: In color mode, this active high input will drive the foreground RGB com·
bination to the background RGB combination. In monochrome mode, the associated char·
acter or background is driven to the intensity determined by BKGND, reverse video attribute
and the cursor input.
ADOUBLE
14
Double Width Attribute: This active high input causes the associated character video to be
shifted out of the serial shift register at one half the dot frequency (DCLK). The CCLK output
is not affected.
AREDB/AGP1
21
Red Background/General Purpose Attribute 1: In color mode, this input activates the
RED/TTLV1 output during the background portion of the associated character block. In
monochrome mode, it activates the GREEN/GP1 output for the associated character block.
ABLUEB/AGP2
22
Blue Background/General Purpose Attribute 2: In color mode, this input activates the
BLUE/TTLV2 output during the background portion of the associated character block. In
monochrome mode, it activates the LUM/GP2 output for the associated character block.
AGREENB/ARVID
18
Green Background/Reverse Video Attribute: In color mode, this input activates the
GREEN/GP1 output during the background portion of the associated character block. In
monochrome mode, it causes the associated character block video intensities to be
reversed.
DO-D8
36-39,
2-6
I
Dot Data Input: These are parallel inputs corresponding to the character/graphic symbol
dot data for a given scan line. These inputs are strobed into the video shift register on the
trailing (falling) edge of each character clock (CCLK).
CO-C1
34-35
I
Character Clock Control: The states of these two static inputs determine the internal divide
factor for the CCLK output rate.
RESET
15
I
Reset: This active high input initializes the internal logic and resets the attribute latches.
M/C
30
I
Monochrome/Color Mode: This input selects whether the CMAC operates in monochrome or
color mode. A low selects color mode and a high selects monochrome mode.
ADOTM
24
I
Dot Modulation Attribute: When DOTM and this input are high, the active dot width of the
associated character video is one DCLK. When DOTM is high and this input is low, the
active dot width of the associated character video is two DCLKs.
DOTM
31
I
Dot Width Modulation: When this input is high, two DCLKs are used for each dot shifted
through the shift register. When this input is low, one DCLK is used.
DOTS
10
I
Dot Stretching: Sampled at the falling edge of BLANK. When this input is high, one extra
dot is appended to individual dots or groups of dots of the input parallel data and then
transferred through the shift register. When this input is low, normal transfer of input
parallel data results.
Signetics
2·99
2
JANUARY 1983
MICROPROCESSOR DIVISION
SCB2675
COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC)
'm""n,'.'i"
BLOCK DIAGRAM
DCLK - - - - - - - - - - ,
1..- - - - - - - - - - - -
ADOUBLE
co
L..r--~DO~T~--~~----------
"'+--1
DO-DB
DOTM
MODULATION ...- - - - - - - - - - - DOTS
~~L~O:G~IC~~~------------ ADOTM
t--r-----------------~ CCLK
UL
BLINK
CURSOR
CMODE
ABLINK
AUL
MIC
ABLUEFIABLANK
L..r---------,~------------RBLANK
MONOCHROME
AND COLOR
ATTRIBUTE
AND
CURSOR
LOGIC
AREDFIAHILT
ABLUEBIAGP2
AGREENBIARVID
AREDBIAGP1
FUNCTIONAL DESCRIPTION
The CMAC consists of seven major sections (see block diagram). The high speed
dot clock input is applied to a programmable divider to provide a character clock
output for system timing. Parallel dot data
is loaded into the video shift register on
character boundaries and shifted into the
video logic block at the dot rate specified
by the dot modulation section. The appropriate attribute control inputs are selected
by the mode select logic, latched internally on character boundaries, and combined with the serial dot data to provide
monochrome or color video outputs.
The BLANK input defines the active
screen area. I n color mode, the video outputs are forced to the specified background color when this signal is asserted;
in monochrome mode the video outputs
are forced to the states defined by the
BKGND input, i.e_, black if dark background is selected and gray if light background is selected. A separate RBLANK
input allows the user to select the amount
of border around the active area when
operating in color mode or in monochrome mode with light background. This
input can be tied high, in which case the
area outside the active area will be dark, or
it may be pulsed during BLANK periods to
externally control the border widths.
2·100
VIDEO
AND
ATTRIBUTE
HIERARCHY
LOGIC
REDITTLV1
BLUEfTTLV2
GREENIGP1
LUMIGP2
TTL
DRIVERS
...-----~~-------------BLANK
,--+-------------------- RESET
......- Vee
",,-VBB
_GND
In color mode, eight colors for the character (foreground) and eight colors for the
background (area other than character)
can be selected by the attribute inputs. In
monochrome mode, the intensities of
Table 1
foreground and background are a function
of the attribute and BKGND inputs, i.e.,
characters may be black, gray, white, or
highlight (very white) while background
may be black, gray, or white (see Table 1).
MONOCHROME MODE ATTRIBUTE CHARACTERISTICS
REV1
AHILT
ABLINK2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FOREGROUND
VIDEO
BACKGROUND
VIDEO
W
B
B
B
B
G
WIG
H
H/W
B
B/W
B
B/H
G/B
W
W/B
NOTES
1. REV=(BKGND) XOR (ARVID):
BKGND ARVID REV
o
0
2. For blinking, the video outputs are shown as 011, where 0 and 1 are the blink timing Input states.
3. Foreground includes underline when underlining is specified by AUL= 1.
4. When ABLANK= 1, foreground component becomes same as background component.
S. Codes for video outputs are as follows:
CODE TTLV2
B
G
W
H
TTLV1
0
BEAM INTENSITY
Black
Gray
White
Highlight
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC)
SCB2675
'm"..IIe1.iN
Character Clock Counter
The character clock counter divides the
OCLK input to generate the character
clock (CCLK). The divide factor is specified by the clock control inputs (C1-CO) as
follows:
SCB2675B
C1
CO
0
0
1
1
0
1
0
1
DOTSI
CHAR_
CCLK
DUTYCYCLE*
10
7
8
5/5
4/3
4/4
5/4
9
"High/low
SCB2675C
C1
CO
0
0
1
1
0
1
0
1
DOTSI
CHAR_
CCLK
DUTYCYCLE*
10
6
8
5/5
3/3
9
4/4
5/4
"High/low
The number of dot clocks/character is normally the number of dots/character as
listed above. However, when dot width
control is specified, the OCLK input is
divided by two before it is applied to the
character clock counter resulting in the
number of dot clocks/character being
double those listed above, although the
number of displayed dots/character remains the same. See Dot Modulation section ·of this data sheet.
Video Shift Register
On each character boundary, the parallel
input dot data (00-08) is loaded into the
video shift register. The data is shifted out
least significant bit first (~O) at the OCLK
rate. If 10 dots/character are specified
(Cl-CO=OO), the tenth dot will be the
same as 08. The serial dot data from the
video shift register is routed to the video
logic where it is combined with the cursor
and attribute control bits to produce the
video data outputs.
Mode Select, Attribute and
Cursor Control
The mode select logic multiplexes the
monochrome and color attribute inputs
and outputs as specified by the M/C input.
The monochrome mode provides blank,
reverse video, highlight and two general
purpose attributes. The latter may be
used, with external logic, to combine
other attributes (e.g., overscore) into the
video stream. The color mode provides
RGB foreground and background color
attributes. Both modes provide double
width characters, blink, underline, dot
width control and dot stretching.
The cursor and attribute inputs are pipelined internally to allow for system pipeline propagations. The cursor input signal
is delayed internally by two CCLKs (one
for RAM and one for the character generator), while the attribute inputs are delayed
for one CCLK to account for the delay of
the character data through the character
generator latches. The attribute timing
inputs (BLINK, UL and DOTS) are clocked
into the 2675 at the beginning of each
scan line time by the falling edge of
BLANK. Thus, these inputs must be in
their proper state at the falling edge of
BLANK preceding the scan line where
they are required to be active. The BLANK
signal itself is also delayed internally to
provide for the RAM and character generator delays (see figures 6 and 7). Internal
delays cause the video outputs to be
delayed relative to CCLK as illustrated in
figure 8.
foreground and background components
of the character block in monochrome
mode.
In color mode, the colors of the foreground and background components are
specified by the corresponding attribute
inputs; AREDF, AGREENF and ABLUEF
dictate the color of the foreground component while AREDB, AGREENB and
ABLUEB do the same for the background
component. In this mode, the serial dot
data and pipelined cursor and attributes
are combined to generate four video outputs. The RED, GREEN and BLUE outputs
separately contain the corresponding
foreground and background components.
The LUM output is the logical-OR of the
foreground colors and can be used to
drive a separate monochrome monitor or
to select a different set of colors for the
foreground.
VIDEO
Video Logic
Each character block consists of the three
components shown in figure 1. Symbol
video is generated from the dot data inputs 00-08. Underline video is enabled by
the AUL attribute and is generated during
the scan lines for which the UL input is
active. Underline and symbol video are
always the same intensity or color, and
other attributes (e.g., ABLlNK) apply to
them equally. The combination of underline and symbol video is also referred to as
foreground video. Background video is the
area of the character block corresponding
to the absence of foreground video. The
assertion of the non-display attribute
(ABLANK) causes the entire character
block to be displayed as background.
Figure 1_ Character Block Definition
In monochrome mode, the serial dot data
and pipelined cursor and attributes are
combined to generate four video intensities (black, gray, white and highlight)
which are encoded on the TTLV1 and
TTLV2 outputs as follows:
TTLV2
0
0
1
1
TTLV1
0
1
0
1
VIDEO INTENSITY
Black
Gray
White
Highlight
Table 1 describes the relationship between attributes and video intensity of the
Signetics
2·101
2
MICROPROCESSOR DIVISION
JANUARY 1983
COLOR/MONOCHROME ATTRIBUTES CONTROllER (CMAC)
SCB2675
'Rmn"II"·'fA
Dot Modulation Logic
The dot modulation logic controls the
video shift register to supply dot stretching and dot width control.
Dot stretchi ng is controlled by the DOTS
input which is sampled each scan line at
the trailing (falling) edge of BLANK. If
DOTS is asserted at that time, all charac·
ters on the following scan line will have
dot stretching applied. Dot stretching
causes an extra dot to be added to in·
dividual dots or groups of dots as shown
in figures 2 and 3. Dot stretching can be
used to:
1. Compensate for low video bandwidth
monitors (since the minimum active
displayed segment with dot stretching
is two DCLKs).
2. Assure crisp black characters when
operating in white background mode.
3. Provide thick characters as a means of
distinguishing areas of the display.
Dot width is controlled by the DOTM and
ADOTM inputs. DOTM is tied either high,
which enables the feature on the entire
display, or low, which disables the feature.
With ADOTM high, the dot width of
characters can be selectively controlled
by assertion of the ADOTM attribute input.
When operating in this mode, the dot
clock input is divided by two before being
applied to other circuits in the CMAC. This
affects the CCLK output.
1. Make horizontal lines and vertical lines
appear the same brightness on the
display.
2. Provide two different brightness levels
for characters without requiring a moni·
tor with analog brightness inputs.
When dot width control is enabled as
above, two DCLKs are used for each video
dot period. Asserting ADOTM for a partic·
ular character will cause each active video
dot of the displayed character to be turned
on for one DCLK and off for the other
DCLK, while if ADOTM is negated for that
character, the active video dot for that
character will be turned on (black back·
ground) or off (white background) for both
DCLK times (see figures 2 and 4). Only the
character video component of the charac·
ter block is modulated. Underline video
and background are not affected by on·
time modulation. Width control can be
used to:
monitor used.
However, note that the effects prod uced
by this feature are highly dependent on
the video amplifier characteristics of the
Double Width Logic
The double width logic controls the rate at
which dots are shifted through the video
shift register. When the ADOUBLE input is
asserted, the associated character video
will be shifted at one half the DCLK rate,
and the dot information for the next
character will be loaded into the shift
register two CCLKs later. The CCLK output is not affected. If a double width
character is specified at the last location
of a character row, the second half of the
double width character (one CCLK) will ex·
tend into the horizontal front porch.
DOT STRETCHING
DOT CLOCK
-- -- -- -----
STRETCHED~
DISPLAYED ON MONITOR
NORMAL
STRETCHED
DOT WIDTH CONTROL
DOT CLOCK
WIDTH
ADOTM=O
WIDTH
ADOTM=1
DISPLAYED ON MONITOR
WIDTH
ADOTM=O
WIDTH
ADOTM=1
Figure 2. Dot Modulation Timing
2·102
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC)
SCB2675
'am",,""·'·'
CHARACTER AS STORED
ACTUAL CHARACTER DISPLAYED
IN CHARACTER GENERATOR
WITH DOT STRETCHING EMPLOYED
2
Figure 3. Dot Stretching
ACTUAL CHARACTER DISPLAY
WITH WIDTH CONTROL
NORMAL CHARACTER DISPLAY
WITHOUT WIDTH CONTROL
F
Figure 4. Dot Width Control
ABSOLUTE MAXIMUM RATINGS 1
PARAMETER
Operating ambient temperature 2
Storage temperature
All voltages with respect to ground 3
DC ELECTRICAL CHARACTERISTICS TA =
PARAMETER
RATING
o to
+ 70
-65 to + 150
- 0.5 to + 6.0
O·C to
UNIT
·C
·C
V
+ 70·C, Vee= 5V± 5%,
Vss= figure 54 ,5,6
LIMITS
TEST CONDITIONS
Min
V IL
V IH
VOL
VOH
IlL
IIH
Icc
Iss
Input low voltage
Input high voltage
Output low voltage
Output high voltage
Typ
Max
0.8
2.0
IOL=4mA
IOH= -4001'A
Input low current
DCLK
All other inputs
Input high current
DCLK
All other inputs
VIN = O.4V
Vee supply current
Vss supply current
VIN=OV, Vee=max
Figure 5
0.4
2.4
UNIT
V
V
V
V
-800
-400
I'A
I'A
40
20
I'A
I'A
80
120
mA
mA
VIN = 2.4V
Signetics
2·103
MICROPROCESSOR DIVISION
JANUARY 1983
COLORlMONOCHROME ATTRIBUTES CONTROLLER (CMAC)
'm"
..""·'"
AC ELECTRICAL CHARACTERISTICS
TA = O·C to
SCB2675
+ 70·C, vcc= 5V ± 5%, Vee= figure 54,5,6
TENTATIVE LIMITS
PARAMETER
TEST CONDITIONS
25MHz VERSION
Min
Dot clock tlmlng 7
Frequency
fo
High time
IOH
Low time
tOl
Setup
tse
tSA
Iso
tSK
tsc
tSR
tSM
Hold
tHe
tHA
tHO
tHK
t HC
tHR
IHM
Max
18MHz VERSION
Min
25
15
15
times S
BLANK to CCLK
Attributes to CCLK
DO-D9 to CCLK
CURSOR 10 CCLK
CO, C1 10 DCLK
RBLANK to DCLK
BLINK, UL, DOTS to BLANK
timesS
BLANK from CCLK
Attributes from CCLK
DO-D8 from CCLK
CURSOR from CCLK
CO, C1 from DCLK
RBLANK from DCLK
BLINK, UL, DOTS from BLANK
Delay limes 7
CCLK from DCLK
loc
Olher oulputs from DCLK
tov
18
22
22
40
40
60
40
20
20
20
50
MHz
ns
ns
20
20
20
ns
ns
ns
ns
ns
ns
ns
20
20
30
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
50
70
50
20
20
30
20
20
20
20
UNIT
Max
C l =5OpF
30
55
60
35
70
70
ns
ns
NOTES
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at
these or at any conditions other than those described In the AC and DC Electrical Characteristics section of this specification is not implied.
2. For operating at elevated temperatures, the device must be derated based on +15O°C maximum junction temperature.
3. This product includes Circuitry specifically designed for the protection of its Internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested
that conventional precautions be taken to avoid applying voltages greater than the rated maxima.
4. Parameters are valid over operating temperature range unless otherwise specified.
5. All voltage measurements are referenced to ground. For testing, all Input signals swing between O.4V and 2.4V with a transition time of 3ns maximum. All time measurements
are referenced at input voltages of O.BV and 2.0V and at output voltages of O.BV and 2.0V as appropriate.
6. Typical values are at + 25°C, typical supply voltages and typical processing parameters.
7. See figure 8.
8. See figures 6, 7, 9, and 10.
Vee
Vee
40
r----<
31.60
1%,l/2W
Figure 5.
Recommended V BB Test Circuit
2·104
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
SCB2675
COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC)
'W"")uJ_.,,
_ _...... 1--'5B-1
BLANK
-1
-
I
[;='HB
-------------
~
ATTRIBUTE5 1
lsi
2nd
__B_K_G_N_D_4_....L_.::C;.:H;;:A;.:R_..L......:C;.:H;.:A;.:R_..L._ _
_ _
_
_
_
I
I
LAST -1
LAST
4
.....JL-..;C;.:H;;.A;;.R;........L._.::CH;.:A;.:R;.....-,_B_K_G_N_D_
NOTES:
1. Attributes include: ABLlNK, ABLANK, ARVID, AUL, AHILT, ADOUBLE, ADOTM, two general purpose, and foreground/background colors.
One CCLK delay for dot data (obtained from delay through character generator).
See figure 8 for detail timing of video outputs
4. Non-active scan time. VIDEO reverts to polarity selected by the BKGND Input In monochrome mode
Figure 6. CMAC Pipeline Timing
CHARACTER
WITH CURSOR
~
Figure 7. Cursor Pipeline Timing
Signetics
2·105
2
MICROPROCESSOR DIVISION
JANUARY 1983
COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC)
SCB2675
'm''',ii,ie'N
I---'/ID
DCLK
_=!
--l
~tDC
CCLK,
~----------------------------------
--I
OTHER
OUTPUTS
Figure 8. Output Pipeline Timing
MONOCHROME MODE
J.L....JUl
~2 I
rtHAj
I
VIDEO
GRAY
~
\
"~.1
BLACK
I
GRAY
tHR~
t
n
~,
BLACK
I
Figure 9. BKGND and RBLANK Timing During Inactive Scan Time (Blank = 1)
DCLK
CO,C'
J~H~----------------~~---------------------~----------
NOTE
1. The high and low times of
CCCK may be controlled
independently_
Figure 10. Clock Divider Timing
2·106
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
COLOR/MONOCHROME ATTRIBUTES CONTROLLER (CMAC)
SCB2675
'm""ii"e'N
~
I
2
MONITOR
LUM
ATTRIBUTE
RAM
Figure 11. System Block Diagram of SCB2675 in Color Mode
2670
CHARACTER
GENERATOR
TTLV1)
TTLV2 MONITOR
GENERAL
} PURPOSE
OUTPUTS
ATTRIBUTE
RAM
Figure 12. System Block Diagram of SCB2675 in Monochrome Mode
Signe1ics
2·107
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Section 3
Single Chip
Microcomputers
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SINGLE CHIP 8-BIT MICROCOMPUTERS
SCN80 SERIES
'm"")..i••,,
DESCRIPTION
FEATURES
The Signetics SCN80 Series microcomputers are self-contained, 8-bit processors
which contain the system timing, control
logic, RAM data memory, ROM program
memory (8048/49/50 only), and 1/0 lines
necessary to implement dedicated control
functions. All SCN80 Series devices are
pin and program compatible, differing
only in the size of the on-board program
ROM and data RAM, as follows:
• 8·bit CPU, ROM, RAM, 1/0 in a 40'pin
package
TYPE
SCN8048
SCN8049
SCN8050
SCN8035
SCN8039
SCN8040
RAM SIZE
64x8
128x 8
256 x 8
64x8
128x8
256x8
ROM SIZE
1Kx8
2Kx8
4Kx8
-
PIN CONFIGURATION
24 quasi bidirectional 110 lines
Two test inputs
Internal counter/timer
Single·level vectored interrupts: external, counterltimer
• Over 90 instructions, 70% single byte
•
•
•
•
The SCN86 Series processors are designed
to be efficient control processors as well
as arithmetic processors. They provide an
instruction set which allows the user to
directly set and reset individual lines within its 1/0 ports as well as test individual
bits within the accumulator. A large vari·
ety of branch and table look-up instructions make these processors very efficient
in implementing standard logic functions.
Also, special attention has been given to
code efficiency. Over 70% of the instructions are a single byte long and all others
are only 2 bytes long.
An on-chip 8-bit counter is provided which
can count, under program control, either
internal clock pulses (with a divide by 32
prescaler) or external events. The counter
can be programmed to cause an interrupt
on terminal count.
P27
P26
P25
• 1.36"s or 2.5"s instruction cycle, all instructions one or two cycles
•
•
•
•
Expandable memory and 1/0
Low voltage standby
TTL compatible inputs 'and outputs
Single + 5V power supply
-
Program memory can be expanded externally up to a maximum total of 4K bytes
without paging. Data memory can also be
expanded externally. 1/0 capabilities can
be expanded using standard devices or
the 8243 1/0 expander.
Vee
Tl
3
P24
P17
P16
P15
Wii
ALE
P13
DBO
P12
DBl
Pl1
DB2
Pl0
DB3
VDD
DB4
PROG
DB5
P23
FUNCTIONAL DESCRIPTION
DB6
P22
The following is a general functional description of the SCNoo Series microcomputers. Refer to the block diagram.
DB7
P2l
Vss
P20
TOP VIEW
ORDERING CODE
SCN80
IT]
1
AD D D 40 (CPxxxx)
[CUSTOM .0. PAnE.' ,U.B..
Applies to masked ROM versions only. Number will be
assigned by Signetlcs. Contact Signetlcs sales office
for ROM pattern submission requirements.
4O-Pln
' - - - - PACKAGE
N = Plastic DIP
I = Ceramic DIP
' - - - - - SPEED
6 = 6MHz clock
B 11MHz clock
=
' - - - - - - OPERATING TEMPERATURE RANGE
C=O·to +70·C
' - - - - - - - ROM/RAM (bytes)
35= EXT/64
48= 1K164
39 = EXT/128
49 2K1128
40 = EXT/256
50 = 4K1256
=
Signetics
3·1
MICROPROCESSOR DIVISION
JANUARY 1983
SINGLE CHIP 8-BIT MICROCOMPUTERS
SCN80 SERIES
'am""""·"t
PIN DESIGNATION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
DBO-DB7
12-19
1/0
Bus. Bidirectional 1/0 port can be read from or written into using the RD or WR strobes. This port can
also be statically latched.
Contains the 8 lower address bits during an access of external memory and receives the addressed
instruction under control of PSEN. PSEN, ALE, RD, and iiiJ1!i determine whether the access is an in·
struction fetch or a RAM read/write.
P10-P17
27-34
1/0
Port 1. 8-bit quasi·bidirectionall/O port.'
P20-P27
21-24,
35-38
1/0
Port 2. 8·bit quasi·bidirectionall/O port.' P20-P23 contain the 4 higher order address bits during an
access of external program memory and also serve as a 4·bit 1/0 expander bus for the 8243.
25
1/0
Output strobe (active low) for the 8243 1/0 expander.
TO
PROG
1
1/0
Input pin sensed using the JTO and JNTO instructions.
Clock output pin when designated as such by the ENTO ClK instruction.
T1
39
I
Input pin sensed using the JT1 and JNT1 instructions. Can be designated as the timerlcounter input
by the STRT CNT instruction.
INT
6
I
Interrupt input pin. When low causes interrupt if interrupt is enabled. Can also be used as an input
which is testable with the JNI instruction. Interrupt is disabled during and after a RESET.
RESET
4
I
Reset input pin is that used to initialize the microcomputer. Active low. Internal pullup - 75k1l 2.
During program verification the address is latched by a "0" to "1" transition on RESET and the data
at the addressed location is output on BUS.
ALE
11
0
Address latch enable. Occurs each clock cycle and is useful for clocking and sampling.
During external program or data memory access, ALE is used to strobe the address information
multiplexed on the DBO-DB7 outputs.
RD
8
0
Read strobe. Active low strobe used to gate data onto BUS lines when reading from an external
source.
WR
10
0
Write strobe. Active low strobe used to write data from BUS lines to an external destination.
EA
7
I
External access input. When high forces instruction fetches from external memory. Internal pullup
-10MIl.
PSEN
9
0
Program store enable. Active low strobe that occurs only during a fetch from external program
memory.
SS
5
I
Single step. Active low input which is used with ALE to cause the microcomputer to execute a single
instruction. Internal pullup - 300kll.
XTAL1
2
I
One side 01 crystal (or l) input for internal oscillator. Can also be used as an input for an external
timing source 2.
XTAl2
3
I
Other side 01 crystal.
Vss
20
I
Circuit ground.
Vce
40
I
Power input, + 5VDC.
Voo
26
I
RAM power input; low power standby pin.
NOTES
1. Each pin on Ihese ports can be assigned, under program control, to be an input or
an output. A pin is designated as an input by writing a logic "1" to the pin. RESET
sets all pins to the input mode . .Each pin has an internal pullup of approximately
50k!l.
2. Non-standard TTL V ,H .
3·2
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
SINGLE CHIP 8-BIT MICROCOMPUTERS
SCN80 SERIES
'm""""··,,
BLOCK DIAGRAM
P20
P27
3
RESIDENT
ROM
(8048149/50 ONLy)
PORT 1
P10
r-------------------~------------------~~----------~~--_..~--~¥-------~------~~~ B~~:ER
AND
LATCH
REGISTER 2
REGISTER 3
~ RAM SUPPLY
POWER
SUPPLY
B
REGISTER 4
CONDITIONAL
BRANCH
LOGIC
v~ + 5V MAIN SUPPLY
REGISTER 5
ffi
Q
o
V!!..OND
~
REGISTER 6
REGISTER 7
8 lEVEL STACK
(VARIABLE LENGTH)
OPTIONAL SECOND
REGISTER BANK
DATA STORE
RESIDENT
RAM ARRAY
TIMING
OUTPUT
INTERRUPT
INITIALIZE
EXPANDER
STROBE
CPU
MEMORY
SEPARATE
OSCILLATOR
XTAL
PROGRAM SINGLE READ/WRITE
MEMORY
STEP
STROBES
ENABLE
ADDRESS
LATCH
ENABLE
Signetics
3·3
MICROPROCESSOR DIVISION
JANUARY 1983
SINGLE CHIP 8-BIT MICROCOMPUTERS
SCN80 SERIES
'mn"""."J
PROGRAM MEMORY
Resident program memory consists of up
to 4K bytes of ROM. The program memory
is divided Into pages of 256 bytes each. As
shown in the memory map, figure 1, pro·
gram memory is also divided into two
2048·byte banks, MBO and MB1. 4096
bytes can be addressed directly. If more
memory is required, an 1/0 port can be
used to address locations over 4095.
There are three locations in program memo
ory of special importance. These locations
contain the first instruction to be ex·
ecuted upon the occurrence of one of
three events.
LOCATION
EVENT
0
Activation then deactiva·
tion of the RESET line.
Activation of the I NT line
when the external inter·
rupt is enabled.
An overflow of the timerl
counter if the TIC interrupt
is enabled.
3
7
DATA MEMORY
Resident data memory, as shown in figure
2, consists of up to 256 bytes of RAM. All
locations are indirectly addressable by
either of two RAM pointer registers at
locations 0 and 1. The first eight locations
of RAM (0-7) are designated as working
registers and are directly addressable by
several instructions.
By selecting register bank 1, RAM loca·
tions 24-31 become the working registers,
replacing those in register bank 0 (0-7).
RAM locations 8-23 are designated as the
stack. Two locations (bytes) are used per
CALL, allowing nesting of up to eight sub·
routines.
If additional RAM is required, up to 256
bytes may be added and addressed direct·
Iy using the MOVX instructions. If more
RAM is required an 1/0 port can be used to
select one (256·byte) bank of external
memory at a time.
PROGRAM COUNTER AND
STACK
The Program Counter (PC) is a 12·bit
counterlregister that pOints to the loca·
tion from which the next instruction is to
be fetched. The 8048 and 8049 will auto·
matically address exernal memory when
the boundary of their internal memory is
exceeded. All processors access external
memory if EA is high.
-0
-8
"'B
"'--2047
-
8040/8050
USER RAM
128
127
~
z
0
i
0-
;:
8
7
6
1m
j SEL ...
MBO
- r--
5
0
Z
4
0
3
2
1
~
,-0 7 [8[ 5 4 312[1 [0
L-LADDRESS
32
31
64>< 8
803518048
USER RAM
32x 8
BANKI
WORKING
REGISTERS
8x8
I----Rl~---
24
23
LOCATION 3-EXTERNAL
INTERRUPT VECTORS
PROGRAM HERE
RESET VECTORS
PROGRAM HERE
I----iio~---
8 LEVEL STACK
OR
USER RAM
LOCATION7-TIMER
INTERRUPT VECTORS
PROGRAM HERE
16 x 8
8
7
0
Figure 1. Program Memory Map
3·4
128)( 8
8039/8049
USER RAM
64
63
~
0-
;:
The end of a subroutine, which is sig·
nailed by a return instruction (RET or
RETR), causes the stack pointer to be
decremented and the contents of the reo
suiting register pair to be transferred to
the program counter.
255
1023
i
An interrupt or CALL to a subroutine
causes the contents of the program
counter to be stored In one of the 8 regis·
ter pairs of the program counter stack. The
pair to be used is determined by a 3·bit
stack pointer which is part of the Program
Status Word (pSW). Data RAM locations 8
through 23 are available as stack registers
and are used to store the program counter
and 4 bits of PSW. The stack pointer, when
initialized to 000, points to RAM locations
8 and 9. The first subroutine jump or inter·
rupt resulis in fheprogram ·couriter·con·
tents being transferred to locations 8 and
9 of the RAM array. The stack pointer is
then incremented by one to point to loca·
tions 10 and 11 in anticipation of another
CALL. Nesting of subroutines within sub·
routines can continue up to eight times
without overflowing the stack. If overflow
does occur the deepest address stored
(location 8 and 9) will be overwritten and
lost since the stack pointer overflows
from 111 to 000. It also underflows from
000 to 111.
BANKO
WORKING
REGISTERS
8x8
===ffi:::
RO
~
DIRECTLY
ADDRESSABLE
WHEN BANK 1
IS SELECTED
-.J
ADDRESSED
INDIRECTLY
THROUGH
Rl OR RO
(RO' OR Rl ')
~
DIRECTLY
ADDRESSABLE
WHEN BANK 0
IS SELE1CTED
Figure 2. Data Memory Map
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN80 SERIES
SINGLE CHIP 8-BIT MICROCOMPUTERS
'W""lId.'il
OSCILLATOR AND CLOCK
The processor contains its own internal
oscillator and clock driver. A crystal, inductor, or external pulse generator may be
used to determine the oscillator frequency
(see figure 3). The output of the oscillator
is divided by three and can be output on
the TO pin by executing the ENTO ClK instruction. This ClK signal is divided by
five to define a machine (instruction)
cycle. It is available on pin 11 as ALE.
TIMER/EVENT COUNTER
An internal counter is available which can
count either external events or machine
cycles ( ... 32). The machine cycles are
.---.-.,....,.;:..!
C=15-25pF
C
(INCLUDES SOCKET, I
STRAy) -=-
XTALI
XTAL2
SERIES RESONANT, AT CUT CRYSTAL
DRIVING
FROM EXTERNAL
SOURCE
divided by 32 before they are input to the
8-blt counter. External events are input
directly to the counter. The maximum frequency that can be counted is one third of
the frequency of the cycle counter. The
minimum positive duty cycle that can be
detected is 0.2 tCY' The counter is under
program control and can be made to generate an interrupt to the processor when It
overflows.
INTERRUPT
An interrupt may be generated by either an
external input (iNT, pin 6) or the overflow
of the internal counter, when enabled. In
either case, the processor completes execution of the present instruction and then
does a CAll to the interrupt service routine. After service, a RETR instruction
restores the machine to the state it was
prior to the interrupt. The external interrupt has priority over the internal interrupt.
IN PUT/OUTPUT
The processor has 27 lines which can be
used for input or output functions. These
lines are grouped as 3 ports of 8 lines each
which serve as either Inputs, outputs or
bidirectional ports and 3 "test" inputs
which can alter program sequences when
tested by conditional jump instructions.
Ports 1 and 2
Ports 1 and 2 are each 8 bits wide and have
Identical characteristics. Data written to
these ports is statically latched and remains unchanged until rewritten. As input
ports these lines are non-latching, i.e., inputs must be present until read by an input instruction. Inputs are fully TIL compatible and outputs will drive one standard
TTL load.
The lines of ports 1 and 2 are called quasibidirectional because of a special output
circuit structure which allows each line to
serve as an input, an output, or both even
though outputs are statically latched. Figure 4 shows the circuit configuration.
Each line is continuously pulled up to
+ 5V through a resistive device of relatively high impedance (-50K). This pullup
is sufficient to provide the source current
for a TIL high level yet can be pulled low
by a standard TTL gate thus allowing the
same pin to be used for both input and
output. To provide fast switching times In
a "0" to "1" transition a relatively low impedance device (-5kO) is switched In
momentarily (-500ns) whenever a "1" is
written to the line. When a "0" is written to
the line, a low Impedance (-3000) device
overcomes the light pullup and provides
TTL current sinking capability.
+5V
470D
Jo- ( 2 . 0
2.o)C.
2.0
2.0
0.8
0.8
2.4
TEST POINTS
0.45
.,.:0:;:.8:...._ _ _ _ _ _::;0.::,.8
0.45
0.45
Figure 5. ACTestlng Input, Output, Float Waveforms
NOTES:
1. AC testing inputs are dirven at 2.4V for a logic "1" and O.45V for a logic "0".
2. Timing measurements are made at 2.0V for a logic "1" and O.8V for a logic "0",
3. For timing purposes, the float state is defined as the pOint at which a PO pin sinks 3.2mA or sources
400~A
at the voltage test levels.
XTAl2
ALE
---1
PSEN
---1
iffi
ViR
BUS (PO)
INDICATES ADDRESS TRANSITIONS
PORT OUT
PORT IN
~
____________
NEW DATA
OLD DATA
______
~r_l~
~r--
_____________________________________________
SAMPLING TIME OF 110 PORT PINS DURING INPUT (INCLUDING INTO AND INT1)
SERIAL
PORT ClK
(SHIFT MODE)
Figure 6. Timing Waveforms
NOTE
All internal timing is referenced to the internal time states shown at the top of the page. This waveform represents the signal on the X2 input of the oscillator. This
diagram represents when these signals are actually clocked within the chip. However, the time It takes a signal to propagate to the pins Is in the range of 5O-150ns. Propagation delays are dependent on many variables, such as temperature and pin loading. Even the different signals vary. Typically though, AD and WR have propagation
delays of approximately 50ns and the other timing signals approximately 65ns. At room temperature, fully loaded, these differences in propagation delays between
signals have been integrated into the timing specs.
3·22
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SINGLE CHIP 8-BIT MICROCOMPUTERS
SCN8031, SCN8051
Advance Information
TABLE 1
Instruction Set Description
ARITHMETIC OPERATIONS
Mnemonic
A,Rn
ADD
A,direct
ADD
ADD
A,@Ri
A,R#data
ADD
ADDC A,Rn
ADDC A,direct
ADDC
A,@Ri
ADDC
SUBB
SUBB
SUBB
SUBB
INC
INC
INC
INC
DEC
DEC
DEC
DEC
INC
MUL
DIV
DA
A,#data
A,Rn
A,direct
A,@Ri
A,#data
A
Rn
direct
@Ri
A
Rn
direct
@Ri
DPTR
AB
AS
A
Description
Add register to accumulator
Add direct byte to accumulator
Add indirect RAM to accumulator
DATA TRANSFER (Continued)
Byte
1
2
Cycles
1
1
Add immediate data to accumulator
Add register to accumulator with carry
Add direct byte to A with carry flag
Add Indirect RAM to A with carry flag
Add immediate data to A with carry flag
Subtract register from A with borrow
Subtract direct byte from A with borrow
Subtract indirect RAM from A wfborrow
Subtract immed. data from A wfborrow
Increment accumulator
Increment regIster
Increment direct byte
Increment indirect RAM
Decrement accumulator
Decrement register
Decrement direct byte
Decrement indirect RAM
Increment data pointer
Multiply A & B
Divide A by B
Decimal adjust accumulator
Destination
AND register to accumulator
AND direct byte to accumulator
AND indirect RAM to accumulator
AND immediate data to accumulator
AND accumulator to direct byte
AND immediate data to direct byte
OR register to accumulator
OR direct byte to accumulator
OR indirect RAM to accumulator
OR immediate data to accumulator
OR accumulator to direct byte
OR immediate data to direct byte
Exctusive-OR register to accumulator
Exclusive·OR direct byte to accumulator
Exclusive-OR indirect RAM to A
Exclusive-OR immediate data to A
Exclusive-OR accumulator to direct byte
Exclusive·OR immediate data to direct
Clear accumulator
Complement accumulator
Rotate accumulator left
Rotate A left through the carry flag
Rotate accumulator right
Rotate A right through carry flag
Swap nibbles within the accumulator
Byte
1
2
Description
Move register to accumulator
Move direct byte to accumulator
Move indirect RAM to accumulator
Move Immediate data to accumulator
Move accumulator to register
Move direct byte to register
Move immediate data to register
Move accumulator to direct byte
Move register to direct byte
Move direct byte to direct
Move indirect RAM to direct byte
Move immediate data to direct byte
Move accumulator to indirect RAM
Move dIrect byte to indirect RAM
Move immediate data to indirect RAM
Byte
1
2
Cycles
1
Load data pointer with a 16·bit constant
Move code byte relative to DPTR to A
Move code byte relative to PC to A
Move external RAM (B-bit addr) to A
Move external RAM (16-bit addr) to A
Move A to external RAM (B-bit addr)
Move A to external RAM (16-bit addr)
Push dIrect byte onto stack
Pop direct byte from stack
Exchange register with accumulator
Exchange direct byte with accumulator
Exchange indirect RAM with A
Exchange low-order digit indo RAM wfA
Byte Cycles
3
2
3
Mnemonic
CLR
C
CLR
bit
SETS C
SETS bit
CPL
C
CPL
bit
ANL
C,bit
ANL
C,/bi!
C,bit
ORL
ORL
C,Ibit
MOV
C,bit
MOV
bit,C
Description
Clear carry flag
Clear direct bit
Set carry flag
Set direct bit
Complement carry flag
Complement direct bit
AND direct bit to carry flag
AND complement of direct bit to carry
OR direct bit to carry flag
OR complement of direct bit to carry
Move direct bit to carry flag
Move carry flag to direct bit
Byte
Cycles
1
1
Byte
2
Cycles
2
PROGRAM AND MACHINE CONTROL
Mnemonic
ACALL addr11
LCALL addr16
RET
RETI
AJMP addrl1
LJMP addr16
SJMP rei
JMP
@A+DPTR
rei
JZ
JNZ
rei
rei
JC
rei
JNC
bit,rel
JS
bit,rel
JNS
JSG
bit, rei
CJNE A,direct,rel
CJNE A,#data,rel
CJNE Rn,#data,rel
CJNE @Ri,#data,rel
DJNZ Rn,rel
DJNZ direct, rei
NOP
DATA TRANSFER
Mnemonic
MOV A,Rn
MOV A,direct
MOV A,@Ri
MOV A,#data
MOV Rn,A
MOV An,direct
MOV Rn,#data
MOV direct,A
MOV direct,Rn
MOV direct,direct
MOV direct,@Ri
MOV direct,#data
MOV
@Ri,A
@Ri,direct
MOV
MOV @Ri,#data
Description
BOOLEAN VARIABLE MANIPULATION
LOGICAL OPERATIONS
Mnemonic
ANL
A,Rn
A,direct
ANL
ANL
A,@Ri
A,#data
ANL
direct,A
ANL
ANL
direct,#data
A,Rn
ORL
A,direct
ORL
A,@Ri
ORL
ORL
A,#data
direct, A
ORL
direct,#data
ORL
XRL
A,Rn
A,direct
XRL
XRL
A,@Ai
XRL
A,#data
dnect,A
XRL
direct,#data
XRL
CLR
A
CPL
A
RL
A
RLC
A
RR
A
RRC
A
SWAP A
Mnemonic
MOV OPTR,#dataI6
MOVC A,@A+ DPTR
MOVC A,@A+PC
MOVX A,@Ri
MOVX A,@DPTR
MOVX @Ri,A
MOVX @DPTR,A
PUSH direct
direct
POP
XCH
A,Rn
XCH
A,direct
XCH
A,@Ri
XCHD A,@RI
Cycles
1
Description
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative addr)
Jump indirect relative to the DPTR
Jump it accumulator is zero
Jump if accumulator IS not zero
Jump if carry flag is set
Jump if no carry flag
Jump if direct bit set
Jump if direct bit not set
Jump if direct bit is set & clear bit
Compare direct to A & jump if not equal
Camp. immed. to A & jump if not equal
Camp. Immed. to reg. & jump if not equal
Camp. immed. to indo &jump if not equal
Decrement register & jump if not zero
Decrement direct & Jump jf not zero
No operation
Notes on data addressing modes:
-Working register RO-R7
Rn
direct -128 internal RAM locations, any I/O port, control or status register
@RI
-Indirect mternal RAM location addressed by register RO or R1
#data -8-bit constant mcluded in instruction
#data16 -16-bit constant included as bytes 2 & 3 of instruction
-128 software flags, any 1/0 pin, control or status bit
bit
Notes on program addressing modes:
addr16 -Destination address for LCALL & LJMP may be anywhere within the
64-kilobyte program memory address space.
addr11 -Destination address for ACALL & AJMP will be within the same
2-kilobyte page of program memory as the first byte of the following
Instruction.
rei
-SJMP and all conditional jumps include an 8·bit offset byte. Range is
+ 127 - 128 bytes relative to first byte of the following instruction.
Signetics
3·23
JANUARY 1983
MICROPROCESSOR DIVISION
SCC80C31, SCC80C51
CMOS SINGLE CHIP8-BIT MICROCOMPUTERS
PRODUCT BRIEF, contact your 5ignetics sales office for additional information.
DESCRIPTION
FEATURES
The 51gnetlcs 5Cca0C31/80C51 is a standalone, high performance single-chip computer fabricated with 5lgnetics' highlyreliable CM05 technology and packaged
in a 40-pin DIP. It provides the hardware
features, architectural enhancements and
new instructions that are necessary to
make it a powerful and cost effective controller for applications requiring up to 64K
bytes of program memory andlor up to 64K
bytes of data storage.
•
•
•
•
•
The 5CC80C51 contains a 4K x 8 read-only
program memory; a 128 x 8 readlwrite data
memory; 32 1/0 lines; two 16-bit timerl
counters; a five-source, two-priority-Ievel,
nested interrupt structure; a serial 1/0 port
for either multi-processor communications, 1/0 expansion, or full duplex UART;
and on-chip oscillator and clock circuits.
The 5CC80C31 is identical, except that it
lacks the program memory. For ·systems
that require extra capability, the
5CC80C51 can be expanded using standard TIL compatible memories and byte
oriented peripheral controllers.
The 5CC80C51 microcomputer, like Its
5CC80C48 predecessor, is efficient both
as a controller and as an arithmetic processor. It has extensive facilities for
•
•
•
•
•
PIN CONFIGURATION
4K x S ROM (SCNS051)
12SxS RAM
Four S-bit ports, 32 1/0 lines
Two 16-blt timer/event counters
High-performance full-duplex serial
channel
External memory expandable to 12SK
Boolean processor
SCN80 series architecture enhanced
with:
Non·paged jumps
Direct addressing
Four S-reglster banks
Stack depth up to 12S-bytes
Multiply, divide, subtract, compare
Most instructions execute in 11'$
41'S multiply and divide
r
I
I
-----------
PO.3 AD3
PO.4 AD4
PO.5 AD5
PO.6 AD6
PO.7 AD7
EAlVoo
RxD P3.0
TxD P3.1
ALEIPROG
iRTOP3.2
PSEN
Jl'/T1 P3.3
P2.7 A15
TO P3.4
P2.6 A14
Tl P3.5
P2.5 A13
WIi P3.6
P2.4 A12
Ali P3.7
P2.3 All
XTAL2
P2.2 AID
XTAL1
P2.1 A9
vss
P2.0 A8
TOP VIEW
COUNTERS
4096 BYTES
PROGRAM
MEMORY
(8051)
-1
TWO 16·BIT
TIMER/EVENT
COUNTERS
128 BYTES
DATA MEMORY
I
I
I
I
L
.."'
=>
I
I
I
I
I
_.J
I
RSTIVPD
I
I
I
I
I
I
"'
g[RXD-r
(J
CONTROL
PARALLEL PORTS,
ADDRESSIDATA BUS,
AND 1/0 PINS
SERIAL
IN
Signetics
SERIAL
OUT
TxD..-
~ INTO-
CO)
-<
)
FC0-2 )('--_ _ _ _ _ _ _X
<
{
>---<
>
<
X'-_______~
*Internal Signal Only
J..----Word Write---~-- Odd Byte Write-~- Even ByteWrite--..,f
Figure 11. Word and Byte Write Cycle Timing
4·8
Signetics
)
>
MICROPROCESSOR DIVISION
JANUARY 1983
16·811 MICROPROCESSOR
SCN68000 SERIES
'm"n!..J_."
Read-Modify-Write Cycle - The readmodify-write cycle performs a read, modifies the data in the arithmetic-logic unit,
and writes the data back to the same address. In the SCN68000, this cycle is indivisible in that the address strobe is asserted throughout the entire cycle. The test
and set (TAS) instruction uses this cycle
to provide meaningful communication between processors in a multiple processor
environment, and is the only instruction
that uses it. The read·modify·write cycle is
always a byte operation. The flow chart is
given in figure 12 and a timing diagram is
shown in figure 13.
11
21
31
41
51
Bus Arbitration
Bus arbitration is a technique used by
master type devices to request, be
granted, and acknowledge bus mastership. In its simplist form, it consists of:
1. Asserting a bus mastership request.
2. Receiving a grant that the bus is available at the end of the current cycle.
3. Acknowledging that mastership has
been assumed.
Figure 14 is a flow chart showing the
detail involved in a request from a single
SLAVE
Inp! Data
11 Decode Address
2) Place Data on 00-07 or 08-015
3) Assert Data Transfer Acknowledge
IDTACK)
I
1
I
Acquire Data
1) Latch Data
2) Negate UDS or LOS
3) Start Data Modification
,
Terminate Cycle
1) Remove Data from 00-07 or 08-015
2) Negate Di'ACK
l
I
Start Output Transfer
1) Set R/W to Write
2) Place Data on 00-07 or 08-015
31 Assert Upper Data Strobe IUDSI or Lower
Data Strobe ([55)
I
3)
4)
,J"",
1) Store Data on 00-07 or 08-015
2) Assert Data Transfer Acknowledge
(DTACK)
l
1)
2)
The timing diagram shows that the bus request is negated at the time that an
acknowledge is asserted. This type of
operation would be true for a system conSisting of the processor and one device
capable of bus mastership. In systems
having a number of devices capable of
mastership, the bus request line from
each device is wire-ORed to the processor.
In this system, there could be more than
4
BUS MASTER
Address Device
Set R/W to Read
Place Function Code on FCO- FC2
Place Address on A 1-A23
Assert Address Strobe IASI
Assert Upper Data S~e IUDSI or
Lower Data Strobe ILDS)
f
device. Figure 15 is a timing diagram for
the same operations. The technique used
allows processing of bus requests during
data transfer cycles.
I
Terminate Output Transfer
Negate iJDS or LOS
Negate AS
Remove Data from 00-07 or 08-015
Set Riiiii to Read
I
,
Terminate Cycle
I
11 Negate DTACK
I
Start Nel Cycle
Figure 12. Read-Modify·Write Cycle Flow Chart
Signetics
4-9
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68000 SERIES
16·BIT MICROPROCESSOR
'm""lIeI.'"
SO 51 52 S3 S4 55 S6 57 S8 S9S10511 S12513514S15516517S18S19
CLK
A1-A23
AS
DDS or
LDS
--'""'\\\~------~==========~--~I
I
\
I~--
R/iN
\
i5'fAci(
08-015
FC0-2
\
I
\
(
)
:x____________________
~~
j.-------------
~
,
-
(
>____________________
'Indivisible Cycle'
~x:
-----------+1
Figure 13. Read-Modify-Write Cycle Timing
PROCESSOR
REQUESTING DEVICE
Request the Bus
1) Assert Bus Request (SR)
t
Grant Bus Arbitration
1) Assert Bus Grant (BG)
I
I
,
Acknowledge Bus Mastership
1) External arbitration determines next bus
master
2) Next bus master waits for current cycle to
complete
3) Next bus master asserts Bus Grant
Acknowledge (BGACK) to become new
master
4) Bus master negates BR
I
f
Terminate Arbitration
1) Negate BG (and wait for BGACK to be
negated)
,
Operate as Bus Master
1) Perform Data Transfers (Read and Write
cycles) according to the same rules the processor uses.
,
,
Release Bus Mastership
1) Negate BGACK
Re-Arbitrate or Res-_=:_:_=_=_--------__:_::=~==_:_----------_=_----Processor
..
I ...
Bus Inactive
..
I..
Alternate Bus Master
..
I .. Processor ..
Figure 19. Bus Arbitration with Bus Inactive
Signetics
4·13
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68000 SERIES
16-BIT MICROPROCESSOR
'm""lIeI.'"
BR asserted
BR sampled
Bus three stated-------,
Bus released from three state and
Processor starts next bus C Y C l e r n
BGACK negated internal
BGACK samPled===:-l
BGACK negated
t
t
so
SO Sl S2 S3 S4 S5 S6 S7
I
\
BG
)
A1-A23
AS
UOS
FCO-FC3
I
\
BGACK
LOS
S 1 S2 S3 S4 S5 S6 S7 SO S 1
I
BR\
==:x
\
\
f'
\
f'
f'
)
R/W
'---1
OTACK
00-015
..
Processor
-I'"
Alternate Bus Master
Figure 20. Bus Arbitration During Processor Bus Cycle Special Case
AS
\~
_____________________________JI
-.I~---
LOS/Dm; - - - - . \
\'-----
-------\....- - - -
R/W
OTACK----------------------------------------~
00-015
FCO-2
BERR
=~==~(~~~~~~~~~~~~~~~~~~~==j
==x=~==============~-------~ ~-~========
\
~--------------------------~================~
I_Initiate _1_
~ ~ Read
-Response Faliure-
_ 1_
~
--
Bus Error Detection
Figure 21. Bus Error Timing
4·14
\
Signetics
_ I _
Initiate Bus
--~-----
Error Stacking
MICROPROCESSOR DIVISION
JANUARY 1983
16-81T MICROPROCESSOR
SCN68000 SERIES
'mil,,'lei·'fJ
~----------~!
;'---------------------------------------------------------,\\~---------------~!
!~---
\
r-
~==~~~)===============(~~~~
~==~----~x~========================~x====
L.-.._----'/
f.- - -
~--------------------~!
Read-
*- - --
~
Halt--
-
Rerun- -
-.j
Figure 22. Rerun Bus Cycle Timing
ClK
AS
\'-______---.J!
\~_______________...J/
iJ5S/UOS---"""""'\
;,-------------""""1\
;'---
Riw
DTACK
00-015
FC02
r-=====~(;~~~~~==============(~~~~~2}--=x
x:==
\
/
\
\L_ _ _ _ _ _ _ _-J!
HALT
f.-
-Read- -
-
+- - -
Halt -
-
-+ - -
Read-
-.j
Figure 23. Halt Signal Timing
Halt Operation with No Bus Error - The
halt input signal to the SCN68000 can be
used to perform a haltlrun/single·step
function. The halt and run modes are
somewhat self explanatory in that, when
the halt signal is constantly active, the
processor 'halts' (does nothing) and when
the halt signal is constantly inactive, the
processor 'runs' (does something).
The single·step mode is derived from cor·
rectly timed transitions on the halt signal
input. It forces the processor to execute a
single bus cycle by entering the 'run'
mode until the processor starts a bus
cycle, then changing to the 'halt' mode.
Thus, the single step mode allows the
user to proceed through (and therefore
debug) processor operations one bus
cycle at a time.
Figure 23 shows the timing required for
correct single·step operations. Some care
must be exercised to avoid harmful interactions between the bus error signal and
the halt pin when using the single cycle
mode as a debugging tool. This is also
true of interactions between the halt and
reset lines since these can reset the pro·
cessor.
Signetics
When the processor completes a bus
cycle after recognizing that the halt signal
is active, most three·state signals are put
in the high-impedance state. These in·
clude address lines and data lines. This is
required for correct performance of the
rerun bus cycle operation.
While the processor is honoring the halt
request, bus arbitration performs as usual.
That is, halting has no effect on bus arbi·
tration. It is the bus arbitration function
that removes the control signals from the
bus.
4·15
4
MICROPROCESSOR DIVISION
JANUARY 1983
16·811 MICROPROCESSOR
SCN68000 SERIES
'tDSJ""li"eiij
The halt function and the hardware trace
capability allow the hardware debugger to
trace single bus cycles or single instructions at a time. These processor capabilities, along with a software debugging
package, give total debugging flexibility.
execution. If a bus error occurs while
reading the vector table (or at any time
before the first Instruction is executed),
the processor reacts as if a double bus
fault has occurred and it halts. Only an external reset will start a halted processor.
Double Bus Faults - When a bus error exception occurs, the processor will attempt
to stack several words containing information about the state of the processor. If a
bus error exception occurs during the
stacking operation, there have been two
bus errors in a row, which is commonly
referred to as a double bus fault. When a
double bus fault occurs, the processor will
halt. Once a bus error exception has occurred, any bus error exception occurring
before the execution of the next instruction constitutes a double bus fault.
Relationship of DTACK, BERR,
and HALT
Note that a bus cycle which is rerun does
not constitute a bus error exception, and
does not contribute to a double bus fault.
This means that as long as the external
hardware requests it, the processor will
continue to rerun the same bus cycle.
The bus error pin also has an effect on the
processor operation after the processor
receives an external reset input. The processor reads the vector table after a reset
to determine the address to start program
Table 4
In order to properly control termination of
a bus cycle for a rerun or a bus error condition, DTACK, BERR, and HALT should be
asserted and negated on the rising edge
of the SCN68000 clock. This will assure
that when two signals are asserted simultaneously, the required setup time (#47)
for both of them will be met during the
same bus state.
This, or some equivalent precaution,
should be designed external to the
SCN68000. Parameter #48 is intended to
ensure this operation in a totally asynchronous system, and may be ignored if
the above conditions are met.
The preferred bus cycle terminations can
be summarized as follows (case numbers
refer to table 4):
Normal termination: DTACK occurs first
(case 1).
Halt termination: HALT is asserted at the
same time, or precedes DTACK (no BERR)
cases 2 and 3.
Bus error termination: BERR Is asserted In
lieu of, at same time, or preceding DTACK
(case 4); BERR negated at same time, or
after DTACK.
Rerun termination: HALT and BERR
asserted at the same time, or before
DTACK (cases 6 and 7); HALT must be
negated at least one cycle after BERR.
Case 5 indicates BERR can precede HALT
which allows fully asynchronous assertion.
Table 4 details the resulting bus cycle termination under various combinations of
control signal sequences. The negation of
these same control signals under several
conditions Is shown in table 5 (DTACK is
assumed to be negated normally in all
cases; for best results, both DTACK and
BERR should be negated when address
strobe Is negated).
Example A: A system uses a watch-dog
timer to terminate accesses to unpopulated address space. The timer
asserts DTACK and BERR simultaneousl
after time-out (case 4).
DTACK, BERR, HALT ASSERTION RESULTS
Case
No.
1
2
3
4
5
6
7
Asserted on Rising
Edge of State
N+
N
DTACK
A
S
BERR
NA
X
HALT
NA
X
DTACK
A
S
BERR
NA
X
HALT
A
S
DTACK
NA
A
BERR
NA
NA
HALT
A
S
DTACK
X
X
BEAR
A
S
HALT
NA
NA
DTACK
X
NA
BERR
S
A
HALT
A
NA
DTACK
X
X
BERR
A
S
HALT
A
S
DTACK
NA
X
BERR
NA
A
i=iAIT
A
S
Control
Signal
Result
Normal cycle terminate and continue.
Normal cycle terminate and halt. Continue when HALT removed.
Normal cycle terminate and halt. Continue when HALT removed.
Terminate and take bus error trap.
Terminate and re-run.
Terminate and re-run.
Terminate and re-run when HALT removed.
Legend:
N - the number of the current even bus state le.g., S4, S6, etc.)
A - signal is asserted in this bus state
NA - Signal is not asserted ,in this state
X - don't care
S - signal was asserted in previous state and remains asserted in this state
4·16
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
16-BIT MICROPROCESSOR
SCN68000 SERIES
'1A""IIeI.i"
Example B: A system uses error detection
on RAM contents. Designer can (a) delay
DTACK until the data is verified, and return
BERR and HALT simultaneously to rerun
error cycle (case 6), or if valid, return
DTACK; (b) delay DTACK until data is
verified, and return BERR at the same time
as DTACK if data is in error (case 4); (c)
return DTACK prior to data verification, as
described in the previous section. If data
is invalid, BERR is asserted (case 1) in the
next cycle. Error handling software must
know how to recover the error cycle.
Reset Operation
The reset signal is a bidirectional signal
that allows either the processor or an external signal to reset the system. Figure 24
illustrates reset timing. Both the halt and
the reset lines must be applied to ensure
total reset of the processor.
When the reset and halt lines are driven by
an external device, it is recognized as an
entire system reset, including the processor. The processor responds by reading
Table 5
the reset vector table entry (vector number
zero, address $000000) and loads it into
the supervisor stack pointer (SSP). Vector
table entry number one at address
$000004 is read next and loaded into the
program counter. The processor initializes
the status register to an interrupt level of
seven. No other registers are affected by
the reset sequence.
When a RESET instruction is executed,
the processor drives the reset pin for 124
clock pulses. In this case, the processor is
trying to reset the rest. of the system.
Therefore, there is no effect on the internal state of the processor and its internal
registers and the status register are unaf·
fected. All external devices connected to
the reset line should be reset at the completion of the RESET instruction.
Asserting the RESET and HALT pins for
ten clock cycles will cause a processor
reset, except when Vcc is initially applied
to the processor. In this case, an external
reset must be applied for 100 milliseconds.
BERR AND HALT NEGATION RESULTS
Conditions of
Termination in
Table A
Bus Error
Re-run
Re-run
Control
Signal
BERR
HALT
BERR
HALT
BERR
RACT
Normal
BERR
HALT
Normal
mrn
HALT
Negated on Rising
Edge of State
N
N+2
••
••
•
••
•
or
or
or
or
or
••
•
•
•
•
Results - Next Cycle
Takes bus error trap.
Illegal sequence; usually traps to
vector number O.
Re-runs the bus cycle.
PROCESSING STATES
The SCN68000 is always in one of three
processing states: normal, exception, or
halted. The normal processing state is
that associated with instruction execution; the memory references are to fetch
instructions and operands, and to store
results. A special case of the normal state
is the stopped state which the processor
enters when a STOP instruction is executed. In this state, no further memory references are made.
The exception processing state is associated with interrupts, trap instructions,
tracing and other exceptional conditions.
The exception may be internally generated
by an Instruction or by an unusual condition arising during the execution of an instruction. Externally, exception processing can be forced by an interrupt, by a bus
error, or by a reset. Exception processing
is designed to provide an efficient context
switch so that the processor can handle
unusual conditions.
The halted processing state is an indication of catastrophic hardware failure. For
example, if during the exception processing of a bus error another bus error occurs, the processor assumes that the system is unusable and halts. Only an external reset can restart a halted processor.
Note that a processor in the stopped state
is not in the halted state, nor vice versa.
Privilege States
The processor operates in one of two
states of privilege: the 'user' state or the
'supervisor' state. The privilege state
determines which operations are legal, is
used by the external memory management
device to control and translate accesses,
May lengthen next cycle.
If next cycle is started it will
none be terminated as a bus error.
ClK
Plus 5 Volts
VCC
RESEi'
HALT
~~I--------~~----1~----------------------~
1
t - > 100 Milliseconds
,.. -++-t<4
Bus Cycles
y:;.OO«IO()O(X)OOOOIO()O------------{__)(:...::=X
NOTES:
1) Internal start-up time
2) SSP High read in here
3) SSP Low read in here
2
3
4
5
6
4) PC High read in here
Bus State Unknown:)¢OOO(
5) PC low read in here
All Control Signals Inactive.
6) First instruction fetched here. Data Bus In Read Mode:
>---<
Figure 24. Reset Operation Timing
Signetics
4·17
4
MICROPROCESSOR DIVISION
JANUARY 1963
SCN68000 SERIES
16·811 MICROPROCESSOR
'm",,",'·",
and is used to choose between the supervisor stack pointer and the user stack
pointer in instruction references.
The privilege state is a mechanism for providing security in a computer system. Pro-,
grams should access only their own code
and data areas, and ought to be restricted
from accessing information which they do
not need and must not modify.
The privilege mechanism provides security by allowing most programs to execute
in user state. In this state, their accesses
are controlled, and the effects on other
parts of the system are limited. The operating system executes in the supervisor
state, has access to all resources, and performs the overhead tasks for the user
state programs.
Supervisor State - The supervisor state
is the higher state of privilege. For instruction execution, the supervisor state is determined by the S-bit of the status register: it is asserted (high), the processor is in
the supervisor state. All instructions can
be executed in the supervisor state. The
bus cycles generated by instructions exe·
cuted in the supervisor state are classified
as supervisor references. While the processor is in the supervisor privilege state,
those instructions which use either the
system stack pointer implicitly or address
register seven explicitly access the supervisor stack pOinter.
All exception processing is done in the
supervisor state, regardless of the setting
of the S-bit The bus cycles generated during exception processing are classified as
supervisor references. All stacking operations during exception processing use the
supervisor stack pointer.
User State - The user state is the lower
state of privilege. For instruction execution, the user state is dete.rmined by the
S-bit of the status register: it is negated
(low), the processor is executing instructions in the user state.
Most instructions execute the same in
user state as in the supervisor state.
However, some instructions which have
important system effects are made privileged, User programs are not permitted to
execute the STOP instruction, or the
RESET instruction. To ensure that a user
program cannot enter the supervisor state
except in a controlled manner, the instructions which modify the whole status register are privileged. To aid in debugging programs which are to be used as operating
systems, the move to user stack pointer
(MOVE to USP) and move from user stack
4·18
pointer (MOVE and USP) instructions are
also privileged.
The bus cycles generated by an instruction executed in user state are classified
as user state references. This allows an
external memory management device to
translate the address and to control access to protected portions of the address
space. While the processor is in the user
privilege state, those instructions which
use either the system stack pointer implicitly, or address register seven explicity, access the user stack pointer.
Privilege State Changes - Once the processor is in the user state and executing
instructions, only exception processing
can change the privilege state. During exception processing, the current setting of
the S-bit of, the status register is saved
and the S-bit is asserted, putting the processor in the supervisor state. Therefore,
when instruction execution resumes at
the address specified to process the exception, the processor is in the supervisor
privi lege state.
Reference Classification - When the processor makes a reference, it classifies the
kind of reference being made, using the
encoding on the three function code output lines. This allows external translation
of addresses, control of access, and differentiation of special processor states,
such as an interrupt acknowledge. Table 6
lists the classification of references.
Exception Processing General
Description
The processing of an exception occurs in
four steps, with variations for different exception causes. During the first step, a
temporary copy of the status register is
made, and the status register is set for exception processing. In the second step
the exception vector is determined, and
the third step is the saving of the current
processor context In the fourth step a
Table 6
new context is obtained, and the processor switches to instruction processing.
Exception Vectors - Exception vectors
are memory locations from which the processor fetches the address of a routine
which will handle that exception. All exception vectors are two words in length
(see figure 25), except for the reset vector,
which is four words. All exception vectors
lie in the supervisor data space, except for
the reset vector which is in the supervisor
program space. A vector number is an
B-bit number which, when multiplied by
four, gives the address of an exception
vector. Vector numbers are generated internally or externally, depending on the
cause of the exception. In the case of interrupts, during the interrupt acknowledge
bus cycle, a peripheral provides an B-bit
vector number (see figure 26) to the processor on the data bus lines DO through
D7. The processor translates the vector
number into a full 24-blt address, as
shown in figure 27. The memory layout for
exception vectors is given in table 7.
As shown in table 7, the memory layout is
512 words long (1024 bytes). It starts at address 0 and proceeds through address
1023.' This provides 255 unique vectors;
some of these are reserved for traps and
other system functions. Of the 255, there
are 192 reserved for user interrupt vectors,
However, there is no protection on the
first 64 entries, so the user interrupt vectors may overlap at the discretion of the
systems designer.
Kinds of Exceptions - Exceptions can be
generated by either internal or external
causes. The externally generated exceptions are the interrupts and the bus error
and reset requests. The interrupts are requests from peripheral devices for processor action while the bus error and reset inputs are used for access control and processor restart. The internally generated
exceptions come from instructions, or
REFERENCE CLASSIFICATION
Function Code Output
FC2
FC1
FCO
0
a
a
1
a
a
a
1
a
0
1
1
1
a
a
1
a
1
1
1
a
1
1
1
Signetics
Reference Class
(Unassigned)
User Data
User Program
(Unassigned)
(Unassigned)
Supervisor Data
Supervisor Program
Interrupt Acknowledge
MICROPROCESSOR DIVISION
JANUARY 1983
16-81T MICROPROCESSOR
SCN68000 SERIES
'm"..""··"
Word 0
New Program Counter IHighl
AO=O, Al=O
Word 1
New Program Counter ILowl
AO=O, Al=l
Figure 25. Exception Vector Format
D15
4
Ignored
Where:
v7 is the MSB of the Vector Number
vO is the LSB of the Vector Number
Figure 26. Peripheral Vector Number Format
Al0 A9 A8
All Zeroes
I
v71 v61
A7 A6
V5!
A5
A4
A3 A2
v41 v31 v21 vl
! Vol
Al
0
AO
!0
I
Figure 27. Address Translated from 8-Bit Vector Number
from address errors or tracing. The trap
(TRAP), trap on overflow (TRAPV), check
register against bounds (CHK) and divide
(DIV) instructions all can generate exceptions as part of their instruction execution. In addition, illegal instructions, word
fetches from odd addresses and privilege
violations cause exceptions. Tracing behaves like a very high priority, internally
generated interrupt after each instruction
execution.
Exception Processing Sequence - Exception processing occurs in four identifiable steps. In the first step, an internal
copy is made of the status register. After
the copy is made, the S-bit is asserted putting the processor into the supervisor privilege state. Also, the T-bit is negated
which will allow the exception handler to
execute unhindered by traCing. For the
reset and interrupt exceptions, the interrupt priority mask is also updated.
In the second step, the vector number of
the exception is determined. For interrupts, the vector number is obtained by a
processor fetch, classified as an Interrupt
acknowledge. For all other exceptions, internallogic provides the vectored number.
This vector number is then used to generate the address of the exception vector.
The third step is to save the current processor status, except in the case of the
reset exception. The current program
counter value and the saved copy of the
status register are stacked using the
supervisor stack pointer. The program
counter value stacked usually points to
the next unexecuted instruction, however
for bus error and address error, the value
stacked for the program counter is unpredictable, and may be incremented from
the address of the instruction which
caused the error. Additional information
defining the current context is stacked for
the bus error and address error exceptions.
The last step is the same for all exceptions. The new program counter value is
fetched from the exception vector and the
processor resumes instruction execution.
Signetics
The instruction at the address given in the
exception vector is fetched, and the normal instruction decoding and execution is
started.
Multiple Exceptions The following
describes the processing which occurs
when multiple exceptions arise simultaneously. Exceptions can be grouped according to their occurrence and priority. The
group 0 exceptions are reset, bus error,
and address error. These exceptions
cause the instruction currently being exe·
cuted to be aborted and the exception proceSSing to commence at the next minor
cycle of the processor. The group 1 exceptions are trace and interrupt, as well as the
privilege violations and illegal instruc·
tions. These exceptions allow the current
instruction to execute to completion, but
preempt the execution of the next instruction by forcing exception proceSSing to
occur (privilege violations and illegal instructions are detected when they are the
next instruction to be executed). The
group 2 exceptions occur as part of the
4·19
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68000 SERIES
16·BIT MICROPROCESSOR
'pm"""".'"
Table 7
EXCEPTION VECTOR ASSIGNMENT
Vector
Number(s)
0
-
2
3
4
5
6
7
8
9
10
11
12'
13'
14"
15
16-23'
24
25
26
27
28
29
30
31
32-47
48-63'
64-255
Address
Hex Space
SP
000
004
SP
SD
008
OOC
SD
010
SD
014
SD
018
SD
O1C
SD
020
SD
024
SO
40
028
SO
44
02C
SO
48
030
SO
52
034
SO
56
036
SO
60
03C
SO
64
O4C
SO
05F
95
96
060
SO
100
064
SO
104
068
SO
108
06C
SO
112
070
SO
116
074
SO
120
078
SO
124
07C
SO
128
080
SO
191
08F
192
OCO
SO
255
OFF
256
100
SO
1023
3FF
Dec
0
4
8
12
16
20
24
28
32
36
Assignment
Reset: Initial SSP
Reset: Initial PC
8us Error
Address Error
Illegal Instruction
Zero Divide
CHK Instruction
TRAPV Instruction
Privilege Violation
Trace
Line 1010 Emulator
Line 1111 Emulator
(Unassigned, reserved I
(Unassigned, reserved I
(Unassigned, reserved I
Uninitialized Interrupt Vector
(Unassigned, reserved I
Spurious Interrupt
Level 1 Interrupt Autovector
Level 2 Interrupt Autovector
Level 3 Interrupt Autovector
Level 4 Interrupt Autovector
Level 5 Interrupt Autovector
Level 6 Interrupt Autovector
Level 7 Interrupt Autovector
TRAP Instruction Vectors
(Unassigned, reserved I
User Interrupt Vectors
-
'Vector numbers 12, 13, 14, 16 through 23 and 48 through 63 are
reserved for future enhancements. No user peripheral devices
should be assigned these numbers.
normal processing of instructions. The
TRAP, TRAPV, CHK, and zero divide exceptions are in this group. For these exceptions, the normal execution of an instruction may lead to exception processing.
Group 0 exceptions have highest priority,
while group 2 exceptions have lowest priority. Within group 0, reset has highest
priority, followed by bus error and then address error. Within group 1, trace has priority over external interrupts, which in
turn takes priority over illegal instruction
and privilege violation. Since only one in-
4,20
struction can be executed at a time, there
is no priority relation within group 2.
The priority relation between two exceptions determines which is taken, or taken
first, if the conditions for both arise
simultaneously. Therefore, if a bus error
occurs during a TRAP instruction, the bus
error takes precedence, and the TRAP instruction processing is aborted. In
another example, if an interrupt request
occurs during the execution of an instruction while the T-bit is asserted, the trace
exception has priority, and is processed
first. Before instruction processing re-
Signetics
sumes, however, the interrupt exception Is
also processed, and instruction processing commences finally In the interrupt
handler routine. A summary of exception
grouping and priority is given in table 8.
Exception Processing Detailed
Discussion
Exceptions have a number of sources, and
each exception has processing which is
peculiar to it.
Reset -
The reset input provides the
highest exception level. The processing of
the reset signal is designed for system initiation and recovery from catastrophic
failure. Any processing in progress at the
time of the reset is aborted and cannot be
recovered. The processor is forced into
the supervisor state, and the trace state is
forced off. The processor interrupt priority
mask is set at level seven. The vector number is internally generated to reference the
reset exception vector at location 0 in the
supervisor program space. Because no assumptions can be made about the validity
of register contents, in particular the
supervisor stack pointer, neither the program counter nor the status register is
saved. The address contained in the first
two words of the reset exception vector is
fetched as the initial supervisor stack
pointer, and the address in the last two
words of the reset exception vector is
fetched as the initial program counter.
Finally, nstruction execution is started at
the address in the program counter. The
power-up/restart code should be pointed
to by the initial program counter.
The RESET instruction does not cause
loading of the reset vector, but does
assert the reset line to reset external
devices. This allows the software to reset
the system to a known state and then continue processing with the next instruction.
Interrupts - Seven levels of interrupt
priorities are provided. Oevices may be
chained externally within interrupt priority
levels, allowing an unlimited number of
peripheral devices to interrupt the processor. Interrupt priority levels are
numbered from one to seven, level seven
being the highest priority. The status
register contains a three-bit mask which
indicates the current processor priority,
and interrupts are inhibited for all priority
levels less than or equal to the current processor priority.
An interrupt request is made to the processor by encoding the interrupt request
level on the interrupt request lines; a zero
MICROPROCESSOR DIVISION
JANUARY 1983
16·81T MICROPROCESSOR
SCN68000 SERIES
'm""""·"j
Table 8
EXCEPTION GROUPING AND PRIORITY
Group
0
1
2
Exception
Reset
Bus Error
Address Error
Trace
Interrupt
Illegal
Privilege
TRAP, TRAPV,
CHK,
Zero Divide
Processing
Exception processing begins
within two clock cycles.
Exception processing begins before
the next instruction
Exception processing is started by
normal instruction execution
PROCESSOR
INTERRUPTING DEVICE
Request Interrupt
J
t
1)
21
3)
4)
5)
6)
Grant Interrupt
Compare interrupt level in status register
and wait for current instruction to complete
Place interrupt level on A 1, A2, A3
Set R/iN to read
Set function code to interrupt acknowledge
Assert address strobe (AS)
Assert lower data strobe (LOS)
I
Provide Vector Number
1) Place vector number of 00-07
2) Assert data transfer acknowledge
r
(orACK)
Acquire Vector Number
1) Latch vector number
2) Negate LOS
3) Negate AS
1) Negate '5'i'ACR
Start Interrupt Processing
Figure 28. Interrupt Acknowledge Sequence Flow Chart
Signetics
indicates no interrupt request. Interrupt
requests arriving at the processor do not
force immediate exception processing,
but are made pending. Pending interrupts
are detected between instruction execu·
tions. If the priority of the pending interrupt is lower than or equal to the current
processor priority, execution continues
with the next instruction and the interrupt
exception processing Is postponed. (The
recognition of level seven is slighly different, as explained in a following paragraph.)
If the priority of the pending interrupt is
greater than the current processor priority, the exception processing sequence Is
started. First a copy of the status register
is saved, and the privilege state is set to
supervisor, tracing is suppressed, and the
processor priority level is set to the level
of the interrupt being acknowledged. The
processor fetches the vector number from
the interrupting device, classifying the
reference as an interrupt acknowledge
and displaying the level number of the interrupt being acknowledged on the address bus. If external logic requests an
automatic vectoring, the processor internally generates a vector number which is
determined by the interrupt level number.
If external logic indicates a bus error, the
interrupt is taken to be spurious, and the
generated vector number references the
spurious interrupt vector. The processor
then proceeds with the usual exception
processing, saving the program counter
and status register on the supervisor
stack. The saved value of the program
counter is the address of the instruction
which would have been executed had the
interrupt not been present. The content of
the interrupt vector whose vector number
was previously obtained is fetched and
loaded into the program counter, and normal instruction execution commences in
the interrupt handling routine. A flow
chart for the interrupt acknowledge sequence is given in figure 28, a timing
diagram is given in figure 29 and the inter·
rupt exception timing sequence is shown
in figure 30.
Priority level seven is a special case. Level
seven interrupts cannot be inhibited by
the interrupt priority mask, thus providing
a 'non-maskable interrupt' capability. An
interrupt is generated each time the inter·
rupt request level changes from some
lower level to level seven. Note that a level
seven interrupt may still be caused by the
level comparison if the request level is a
seven and the processor is set to a lower
level by an instruction.
4·21
4
~~§~§
=
MICROPROCESSOR DIVISION
JANUARY 1983
16-BIT MICROPROCESSOR
SCN68000 SERIES
'm""II,i.iN
ClK
!------\s-----<
}----I\,-----(
A1-A3J-<
AS
\
~,--_-==========-_--,
'--_-----I
~
\'-_-----JI
~~~========~;--\-~
\
\
~
\
UOS
OTACK
'\ ~
'\
\
08-015
(
>---\,----------~(~=====
00-07
(
~,-----~(
lOS
R/W
~
7
~
~
'\
IPlO-Z
\'------/
P
FCO-Z=X
last 8us Cycle of Instruction
(Read or Write)
I'"
\'----
)>----«
'\
__________~7
Stack
1(
.0
r-
\
PCl
1011(
(SSP).
lACK Cycle
(Vector Number Acquisition)
.10(
Stack and
Vector Fetch
.1
Figure 29. Interrupt Acknowledge Sequence Timing Diagram
last Bus Cycle
of Instruction
(During Which
Interrupt Was
Recognized)
~
Stack
PCl
(SSP)
....--.
lACK
Cycle
(Vector Number
Acquisition)
~
Stack
Status
(SSP)
L-...,.
Read
Vector
High
(A16-A23)
----+
Read
Vector
low
(AO-A15)
~
Fetch First Word
of Instruction
of Interrupt
Routine
Figure 30. Interrupt Exception Timing Sequence
4·22
Signetics
r---+
Stack
PCH
(SSP)
r---.
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68000 SERIES
16-811 MICROPROCESSOR
'm""""··,,
Uninitialized Interrupt - An interrupting
device asserts VPA or provides an interrupt vector during an interrupt acknowledge cycle to the SCN68000. If the vector
register has not been initialized, the responding SCN68000 family peripheral will
provide vector 15, the uninitialized interrupt vector. This provides a uniform way to
recover from a programming error.
Spurious Interrupt - If during the interrupt acknowledge cycle no device responds by asserting DTACK or VPA, the
bus error line should be asserted to terminate the vector acquisition. The processor separates the processing of this error from the bus error by fetching the
spurious interrupt vector instead of the
bus error vector. The processor then proceeds with the usual exception processing.
Instruction Traps - Traps are exceptions
caused by instructions. They arise either
from processor recognition of abnormal
conditions during instruction execution,
or from use of instructions whose normal
behavior is trapping.
Some instructions are used specifically to
generate traps. The TRAP instruction
always forces an exception, and is useful
for implementing system calls for user
programs. The TRAPV and CHK instruc·
tions force an exception if the user program detects a runtime error, which may
be an arithmetic overflow or a subscript
out of bounds. The signed divide (DIVS)
and unsigned divide (DIVU) instructions
will force an exception if a division operation is attempted with a divisor of zero.
Illegal and Unimplemented InstructionsIllegal instruction is the term used to refer
to any of the word bit patterns which are
not the bit pattern of the first word of a
legal instruction. During instruction ex·
ecution, if such an instruction is fetched,
an illegal instruction exception occurs.
STOP
RESET
RTE
MOVE to SR
AND (word) immediate to SR
EOR (word) immediate to SR
OR (word) immediate to SR
MOVE USP
Tracing - To aid in program development,
the SCN68000 includes a facility to allow
instruction by instruction traCing. In the
trace state, after each instruction is ex·
ecuted, an exception is forced allowing a
debugging program to monitor the execution of the program under test.
The trace facility uses the T·bit in the
supervisor portion of the status register. If
the T·bit is negated (off), tracing is disabled and instruction execution proceeds
from instruction to instruction as normal.
If the T·bit is asserted (on) at the begin·
ning of the execution of an instruction, a
trace exception will be generated after the
execution of that instruction is completed. If the instruction is not executed,
either because an interrupt is taken, or the
instruction is illegal or privileged, the
trace exception does not occur. The trace
exception also does not occur if the instruction is aborted by a reset, bus error,
or address error exception. If the instruction is indeed executed and an interrupt is
pending on completion, the trace exception is processed before the interrupt exception. If, during the execution of the instruction, an exception is forced by that
instruction, the forced exception is pro·
cessed before the trace exception.
As an extreme illustration of the above
rules, consider the arrival of an interrupt
during the execution of a TRAP instruc·
tion while tracing is enabled. First the trap
exception is processed, then the trace ex·
ception, and finally the interrupt excep·
tion. Instruction execution resumes in the
interrupt handler routine.
Word patterns with bits 15 through 12
equaling 1010 or 1111 are distinguished as
unimplemented instructions and separate
exception vectors are given to these pat·
terns to permit efficient emulation. This
facility allows the operating system to
detect program errors, or to emulate
unimplemented instructions in software.
Bus Error - Bus error exceptions occur
when external logic requests that a bus
error be processed by an exception. The
current bus cycle which the processor is
making is then aborted. Whether the processor was doing instruction or exception
processing, that processing is terminated,
and the processor immediately begins exception processing.
Privilege Violations - In order to provide
system security, various instructions are
privileged. An attempt to execute one of
the privileged instructions while in the
user state will cause an exception. The
privileged instructions are:
Exception processing for bus error
follows the usual sequence of steps. The
status register is copied, the supervisor
state is entered, and the trace state is
turned off. The vector number is generated to refer to the bus error vector. Since
Signetics
the processor was not between instructions when the bus error exception reo
quest was made, the context of the processor is more detailed. To save more of
this context, additional information is
saved on the supervisor stack. The program counter and the copy of the status
register are of course saved. The value
saved for the program cou nter is advanced
by some amount, two to ten bytes beyond
the address of the first word of the in·
struction which made the reference caus·
ing the bus error. If the bus error occurred
during the fetch of next instruction, the
saved program counter has a value in the
vicinity of the current instruction, even if
the current instruction is a branch, a jump,
or a return instruction. Besides the usual
information, the processor saves its internal copy of the first word of the instruction being processed, and the address
which was being accessed by the aborted
bus cycle. Specific information about the
access is also saved: whether it was a read
or a write, whether the processor was processing an instruction or not, and the classification displayed on the function code
outputs when the bus error occurred. The
processor is processing an instruction if it
is in the normal state or processing a
group 2 exception; the processor is not
processing an instruction if it is process·
ing a group 0 or group 1 exception. Figure
31 illustrates how this information is organized on the supervisor stack. Although
this information is not sufficient in gen·
eral to effect full recovery from the bus
error, it does allow software diagnosis.
Finally, the processor commences in·
struction processing at the address con·
tained in the vector. It is the responsibility
of the error handler routine to clean up the
stack and determine where to continue
execution.
If a bus error occurs during the exception
processing for a bus error, address error,
or reset, the processor is halted, and all
processing ceases. This simplifies the
detection of catastrophic system failure,
since the processor removes itself from
the system rather than destroying all
memory contents. Only the RESET pin can
restart a halted processor.
Address Error
Address error exceptions occur when the
processor attempts to access a word or a
long word operand or an instruction at an
odd address. The effect is much like an internally generated bus error, so that the
bus cycle is aborted, and the processor
ceases whatever processing it is currently
doing and begins exception processing.
4·23
4
MICROPROCESSOR DIVISION
JANUARY 1983
16·81T MICROPROCESSOR
SCN68000 SERIES
'm,n."".",
15
13
14
12
10
11
7
8
9
6
5
4
Lower Address
3
/R/W/I/NI
f- - Access Address - -
-
-
-
-
High
- - - Low
-
-
o
2
Function Code
------------
Instruction Register
Status Register
High
I- - Program Counter -
- - - ---- - -- - ------- --Low
R/W (read/wnte): wnte=O, read = 1. I/N (,nstructIOn/not): instruction =0, not= 1
Figure 31. Supervisor Stack Order
so S1 S2 S3 S4 S5 S6 S7 SO S1 S2 S3 S4 S5 S6 S7
ClK
Al·A23
AS
\
IT5S
Ll5S
R/Vii
DTACK
\
J
\
I
\
I
,,
~
I
\
\
H
I_
Read
·1_
..,
,---'
•
~
I
DO-D15
SO S1 S2 S3 S4 S5
"B Clocks- I_
• I_ Approx.Idle
\
,
LL-
L--
•
Aerr
Write
Write StaCk--.j
Figure 32. Address Error Timing
After exception processing commences,
the sequence is the same as that for bus
error including the information that is
stacked, except that the vector number
refers to the address error vector instead.
Likewise, if an address error occurs during
the exception processing for a bus error,
address error, or reset, the processor is
halted. As show in figure 32, an address
error will execute a short bus cycle fol·
lowed by exception processing.
INTERFACE WITH SYNCHRO·
NOUS PERIPHERALS
To interface synchronous peripherals with
the asynchronous SCN68000, the proces·
sor modifies its bus cycle to meet the syn·
4·24
chronous cycle requirements whenever a
synchronous device address is detected.
Figure 33 is a flow chart of the interface
operation between the processor and syn·
chronous devices.
Data Transfer Operation
Three signals on the processor provide
the synchronous interface. They are:
enable (E), valid memory adilress (VMA),
and valid peripheral address (VPA). The
bus frequency is one tenth of the incom·
ing SCN68000 clock frequency. Enable
has a 60/40 duty cycle; that is, it is low for
six input clocks and high for four input
clocks. This duty cycle allows the pro·
cessor to do successive VPA accesses on
successive E pulses.
Signetics
The synchronous cycle timing diagrams
and corresponding AC electrical characteristics table are located towards the end
of this data sheet. At state zero (SO) in the
cycle, the address bus and function codes
are in the high·impedance state. One half
clock later, in state 1, the address bus and
function code outputs are released from
the high·impedance state.
During state 2, the address strobe (AS) is
asserted to indicate that there is a valid
address on the address bus. If the bus
cycle is a read cycle, the upper and/or
lower data strobes are also asserted in
state 2. If the bus cycle is a write cycle, the
read/write (RIW) signal is switched to low
(write) during state 2. One half clock later,
in state 3, the write data is placed on the
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68000 SERIES
16-BIT MICROPROCESSOR
'w""""·',,
PROCESSOR
Initiate Cycle
11 The processor starts a normal Read or
SLAVE
I
Write cycle
L _ _ _ _ _ _---,
t
Define Synchronous Cycle
11 External hardware asserts Valid Peripheral
Address IVPAI
Synchronize With Enable
1) The processor monitors Enable lEI until it is
low I Phase 1)
21 The processor asserts Valid Memory Address IVMAI
,
LI_ _ _ _ _ _ _...,
1)
Transfer Data
The peripheral waits until E is active and
then transfers the data
I
Terminate Cycle
Read cycle the data is latched as E goes
low internallyl
21 The processor negates VMA
31 The processor negates AS, UDS, and LDS
~
Start Next Cycle
Figure 33. Synchronous Interfacing Flow Chart
The processor now inserts wait states un·
til it recognizes the assertion of VPA. The
VPA input signals the processor that the
address on the bus is the address of a syn·
chronous device (or an area reserved for
synchronous devices) and that the bus
should conform to the synchronous trans·
fer characteristics of the synchronous
bus. Valid peripheral address is derived by
decoding the address bus, conditioned by
the address strobe.
DTACK should not be asserted while VPA
is asserted. The SCN68000 VMA is active
low, while the VMA of the synchronous
device should be active high. This allows
the processor to put its buses in the high·
Impedance state on DMA requests with·
out inadvertently selecting peripherals.
Interrupt Operation
During an interrupt acknowledge cycle
while the processor is fetching the vector,
if VPA is asserted, the SCN68000 will as·
sert VMA and complete a synchronous
read cycle as shown in figure 34. The pro·
cessor will then use an internally gener·
ated vector that is a function of the in·
terrupt being serviced. This process is
known as autovectoring. The seven auto·
vectors are vector numbers 25 through 31
(decimal).
There are six normal interrupt vectors and
one NMI type vector. As with the
SCN68000's normal vectored interrupt, the
interrupt service routine can be located
anywhere in the address space. This is
due to the fact that while the vector
numbers are fixed, the contents of the
vector table entries are assigned by the
user.
11 The processor waits until E goes low. IOn a
data bus, and in state 4 the data strobes
are issued to indicate valid data on the
data bus.
During a read cycle, the processor latches
the peripheral data in state 6. For all
cycles, the processor negates the address
and data strobes one half clock cycle later
in state 7, and the enable signal goes low
at this time. Another half clock later, the
address bus Is put in the high·impedance
state. During a write cycle, the data bus is
put in the high·impedance state and the
read/write signal is switched high at this
time. The peripheral logic must remove
VPA within one clock after address strobe
is negated.
After the recognition of VPA, the pro·
cessor assures that enable (E) is low, by
waiting if necessary, and subsequently
asserts VMA. Valid memory address is
then used as part of the chip select equa·
tion of the peripheral. This ensures that
the synchronous peripherals are selected
and deselected at the correct time. The
peripheral now runs its cycle during the
high portion of the E signal. Cycle timing
diagrams depicting best and worst cases
are located towards the end of this data
sheet. The cycle length is dependent
strictly on when VPA is asserted in rela·
tionship to the E clock.
Signetics
Since VMA is asserted during autovector·
ing, the synchronous peripheral address
decoding should prevent unintended ac·
cesses.
DATA TYPES AND ADDRESSING
MODES
Five basic data types are supported:
•
•
•
•
•
Bits
BCD digits (8·bits)
Bytes (8·bits)
Word (16·bits)
Long words (32·bits)
In addition, operations on other data types
such as memory addresses, status word
data, etc. are provided for in the instruc·
tion set. The 14 addressing modes (see
table 9) include six basic types:
4·25
4
MICROPROCESSOR DIVISION
JANUARY 1983
16·BIT MICROPROCESSOR
SCN68000 SERIES
'm",,!"i·'i'
CLK
A1-A3
A4-A23
AS
UOS
LOS
R/Vii
DTACK
08-015
~
--c=J
00-07
-<::)
FC0-2
X
IPL0-2
y
'C
~
L-
E
VPA
\
"-
VMA
\
I
~ Nor~I_-J..... _ _ _ -Autovector Operation- _ _ _ _-I
~
Cycle
-r-
~
Figure 34. Autovector Operation Timing
• Register direct
• Register indirect
• Absolute
• Immediate
• Program counter relative
• Implied
Included In the register Indirect address·
ing modes is the capability to do post·
incrementing, pre·decrementing, offset·
ting and indexing. Program counter rela·
tlve mode can also be modified via index·
ing and offsetting.
Program/Data References
The SCN68000 separates memory refer·
ences Into two classes: program references and data references. Program references, as the name implies, are references
to that section of memory that contains
the program being executed. Data references refer to that section of memory that
contains data. Generally, operand reads
are from the data space. All operand
writes are to the data space.
Addressing
Instruction Format
Instructions are from one to five words in
length, a shown in figure 35, The length of
the Instruction and the operation to be
performed are specified by the first word
of the instruction which is called the
operation word. The remaining words fur·
ther specify the operands. These words
are either immediate operands or extensions to the effective address modes
specified In the operation word.
4·26
Instructions for the SCN68000 contain two
kinds of information; the type of function
to be performed and the location of the
operand(s) on which to perform the func·
tion. Instructions specify an operand location in one of three ways:
Register specification - the number of
the register Is given in the register field
of the Instruction.
Effective address - use of the different
effective address modes.
Signetics
Implicit reference - the definition of
certain instructions implies the use of
specific registers.
Register Specification
The register field within an instruction
specifies the register to be used. Other
fields within the instruction specify
whether the register selected is an ad·
dress or data register and how the register
is to be used.
Effective Address
Most Instructions specify the location of
an operand by using the effective address
field In the operation word. For example,
figure 36 shows the general format of the
single effective address instruction opera·
tion word. The effective address is com·
posed of two 3·bit fields: the mode field,
and the register field. The value In the
mode field selects the different address
modes. The register field contains the
number of a register.
MICROPROCESSOR DIVISION
JANUARY 1983
16-BIT MICROPROCESSOR
SCN68000 SERIES
'm""JleI.iit
Table 9
The effective address field may require
additional information to fully specify the
operand. This additional information,
called the effective address extension, is
contained in a following word or words
and is considered part of the instruction,
as shown in figure 35. The effective address modes are grouped into three categories: register direct, memory addressing, and special.
DATA ADDRESSING MODES
Mode
Register Direct Addressing
Data Register Direct
Address Register Direct
Generation
EA~Dn
EA~An
Absolute Data Addressing
Absolute Short
Absolute Long
Program Counter Relative Addressing
Relative with Offset
Relative with Index and Offset
EA ~ INext Wordl
EA ~ INext Two Wordsl
EA ~ IPCI + d16
EA ~ IPCI + IXnl + dS
Register Direct Modes
EA~IAnl
These effective addressing modes specify
that the operand is in one of the 16 multifunction registers.
Register Indirect Addressing
Register Indirect
Postincrement Register Indirect
Predecrement Register Indirect
Register Indirect with Offset
Indexed Register Indirect with Offset
EA~IAnl, An-An+N
An-An-N, EA~IAnl
EA ~ IAnl + d16
EA ~ IAnl + IXnl + dS
Immediate Data Addressing
Immediate
Quick Immediate
DATA ~ Next Wordlsl
In herent Data
Implied Addressing
Implied Register
EA~
NOTES:
EA ~ Effective Address
An = Address Register
Dn = Data Register
Xn = Address or Data Register used
as Index Register
SR = Status Register
PC = Program Counter
I I = Contents of
dS = Eight-bit Offset
Idisplacementl
d16 = Sixteen-bit Offset
Idisplacementl
N = 1 for Byte, 2 for
Words and 4 for Long
Words
- = Replaces
15
14
13
12
11
Data Register Direct - The operand is in
the data register specified by the effective
address register field.
Address Register Direct - The operand is
in the address register specified by the
effective address register field.
SR, USP, SP, PC
Memory Address Modes
These effective addressing modes specify
that the operand is in memory and provide
the specific address of the operand.
Address Register Indirect - The address
of the operand is in the address register
specified by the register field. The reference is classified as a data reference with
the exception of the jump and jump to
subroutine instructions.
5
S
7
6
4
Operation Word
IFirst Word Specifies Operation and Modesl
10
9
3
2
o
Immediate Operand
Ilf Any, One or Two Wordsl
Source Effective Address Extension
Ilf Any, One or Two Wordsl
Destination Effective Address Extension
IIf Any, One or Two Wordsl
Figure 35. Instruction Format
5
3
2
o
Effective Address
Mode
Register
Figure 36. Single Effective Address Instruction Operation Word General Format
Signetics
4·27
4
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68000 SERIES
16·811 MICROPROCESSOR
'm",,""·'ij
Address Register Indirect with Postlncre·
ment - The address of the operand is in
the address register specified by the reg·
ister field. After the operand address is
used, it is incremented by one, two, or four
depending on whether the size of the oper·
and is byte, word, or long word. If the ad·
dress register is the stack pointer and the
operand size is byte, the address. is in·
cremented by two rather than one to keep
the stack pointer on a word boundary. The
reference is classified as a data reference.
Address Register Indirect with Predecre·
ment - The address of the operand Is In
the address register specified by the reg·
ister field. Before the operand and the ad·
dress is used, it is decremented by one,
two or four depending on whether the
operand size is byte, word, or long word. If
the address register is the stack pointer
and the operand size is byte, the address
is decremented by two rather than one to
keep the stack pOinter on a word bound·
ary. The reference is classified as a data
reference.
Address Register Indirect with Displace·
ment - This address mode requires one
word of extension. The address of the
operand is the sum of the address in the
address register and the sign·extended
16·bit displacement integer in the exten·
sion word. The reference is classified as a
data reference with the exception of thE!
jump and jump to subroutine instructions.
Address Register Indirect with Index This address mode requires one word of
extension. The address of the operand is
the sum of the address in the address
register, the sign·extended displacement
integer in the low order eight bits of the
extension word, and the contents of the
index register. The reference is classified
as a data reference with the exception of
the jump and jump to subroutine instruc·
tions.
Special Addressing Modes
The special address modes use the effective address register field to specify the
special addressing mode instead of a register number.
Absolute Short Address - This address
mode requires one word of extension. The
address of the operand is in the extension
word. The 16-bit address is sign extended
before it is used. The reference is classi·
fied as a data reference with the exception
of the jump and jump to subroutine in·
structions.
4·28
Absolute Long Address - This address
mode requires two words of extension.
The address of the operand is developed
by the concatenation of the extension
words. The high·order part of the address
is the first extension word; the low order
part of the address is the second exten·
sion word. The reference is classified as a
data reference with the exception of the
jump and the jump to subroutine instruc·
tions.
Program Counter with Displacement This address mode requires one word of
extension. The address of the operand is
the sum of the address in the program
counter and the sign·extended 16·bit
displacement integer in the extension
word. The value in the program counter is
the address of the extension word. The
reference is classified as a program
reference.
Program Counter with Index - This ad·
dress mode requires one word of exten·
sion. The address is the sum of the ad·
dress in the program counter, the sign·
extended displacement integer in the
lower eight bits of the extension word, and
the contents of the index register. The
value in the program counter is the ad·
dress of the extension word. This refer·
ence is classifed as a program reference.
Immediate Data - This address mode
requires either one or two words of extension depending on the size of the opera·
tion.
Table 10
Byte operation - operand is low order
byte of extension word.
Word operation - operand is extension
word.
Long word operation - operand is in
the two extension words, high·order 16
bits are in the first extension word, loworder 16 bits are in the second extension word.
Condition Codes or Status Register - A
selected set of instructions may reference
the status register by means of the effec·
tive address field. These are:
ANDI to CCR
ANDI to SR
EORI to SR
ORI to CCR
ORI to SR
Effective Address Encoding
Summary
Table 10 is a summary of the effective ad·
dressing modes.
Implicit Reference
Some instructions make Implicit refer·
ence to the program counter (PC), the
system stack pointer (SP), the supervisor
stack pointer (SSP), the user stack pointer
(USP), or the status register (SR).
System Stack
The system stack is used Implicitly by
many instructions; user stacks and
EFFECTIVE ADDRESS ENCODING SUMMARY
Addressing Mode
Data Register Direct
Address Register Direct
Address Register Indirect
Address Register Indirect with
Postincrement
Address Register Indirect with
Predecrement
Address Register Indirect with
Displacement
Address Register Indirect with
Index
Absolute Short
Absolute Long
Program Counter with
Displacement
Program Counter with Index
Immediate
Signetics
Mode
000
001
010
Register
register number
register number
register number
011
register number
100
register number
101
register number
110
111
111
register number
000
001
111
111
111
010
011
100
MICROPROCESSOR DIVISION
JANUARY 1983
16·BIT MICROPROCESSOR
SCN68000 SERIES
'm""",I.",
queues may be created and maintained
through the addressing modes. Address
register seven (A7) is the stack pointer
(SP). The SP is either the SSP or the USP,
depending on the state of the S·bit in the
status register. If the S-bit indicates
supervisor state, SSP is the active system
stack pointer, and the USP cannot be
referenced as an address register. If the
S·bit indicates user state, the USP is the
active system stack pointer, and the SSP
cannot be referenced. Each system stack
fills from high memory to low memory.
Table 11
BCC
BCHG
BCLR
BRA
BSET
BSR
BTST
Branch Conditionally
Bit Test and Change
Bit Test and Clear
Branch Always
Bit Test and Set
Branch to Subroutine
Bit Test
CHK
CLR
CMP
Check Register Against Bounds
Clear Operand
Compare
DBCC
Test Condition, Decrement and
Branch
Signed Divide
UnSigned Divide
Description
EOR
EXG
EXT
Exclusive Or
Exchange Registers
Sign Extend
JMP
JSR
Jump
Jump to Subroutine
LEA
LINK
LSL
LSR
MOVE
MOVEM
MOVEP
MULS
MULU
NBCD
NEG
NOP
NOT
OR
Variation
Mnemonic
Description
Load Effective Address
Link Stack
Logical Shift Left
Logical Shift Right
PEA
RESET
ROL
ROR
ROXL
ROXR
RTE
RTR
RTS
Push Effective Address
Reset External Devices
Rotate Left without Extend
Rotate Right without Extend
Rotate Left with Extend
Rotate Right with Extend
Return from Exception
Return and Restore
Return from Subroutine
Move
Move Multiple Registers
Move Peripheral Data
Signed Multiply
UnSigned Multiply
SBCD
SCC
STOP
SUB
SWAP
Subtract Decimal with Extend
Set Conditional
Stop
Subtract
Swap Data Register Halves
Negate Decimal with Extend
Negate
No Operation
One's Complement
TAS
TRAP
TRAPV
TST
Test and Set Operand
Trap
Trap on Overflow
Test
Logical Or
UNLK
Unlink
Instruction
Type
Description
ADD
ADDA
ADDQ
ADDI
ADDX
Ada
Add
Add
Add
Add
AND
AND
ANDI
CMP
CMP
CMPA
CMPM
CMPI
EOR
EORI
Logical And
And Immediate
Compare
Compare Address
Compare Memory
Compare Immediate
Exclusive Or
Exclusive Or Immediate
EOR
Data movement
Integer arithmetic
VARIATIONS OF INSTRUCTION TYPES
Instruction
Type
ADD
The instructions form a set of tools that include all machine functions to perform the
following operations:
4
Mnemonic
Description
Add Decimal with Extend
Add
Logical And
Arithmetic Shift Left
Arithmetic Shift Right
Table 12
The SCN68000 instruction set is summa·
rized in table 11. Some additional instructions are variations, or subsets, of these
and appear in table 12. Special emphasis
has been given to the instruction set's
support of structured high-level languages
to facilitate ease of programming. Each in·
struction, with few exceptions, operates
on bytes, words, and long words, and
most instructions can use any of the 14
addressing modes. Combining instruction
types, data types, and addressing modes,
over 1000 useful instructions are provided.
These instructions include signed and unsigned multiply and divide, 'quick' arithmetic operations, BCD arithmetic and ex·
panded operations (through traps).
INSTRUCTION SET SUMMARY
Mnemonic
A8CD
ADD
AND
ASL
ASR
DIVS
DIVU
INSTRUCTION SET OVERVIEW
Variation
Description
MOVE
MOVEA
MOVEQ
MOVE from SR
MOVE to SR
MOVE to CCR
MOVE USP
Move
Move
Move
Move
Move
Move
Move
NEG
NEG
NEGX
Negate
Negate with Extend
OR
OR
ORI
Logical Or
Or Immediate
Subtract
Subtract Address
Subtract Immediate
Subtract Quick
Subtract with Extend
MOVE
Address
Quick
Immediate
with Extend
SUB
SUB
SUBA
SUBI
SUBQ
SUBX
Signetics
Address
Quick
from Status Register
to Status Register
to Condition Codes
User Stack Pointer
4·29
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68000 SERIES
16·81T MICROPROCESSOR
Imil"""·'fJ
Logical
Shift and rotate
Bit manipulation
Binary coded decimal
Program control
System control
Table 13
DATA MOVEMENT OPERATIONS
Instruction
EXG
LEA
Operand Size
32
32
LINK
-
The complete range of instruction capabilities, combined with the variety of addressing modes described previously, provide a very flexible base for program
development.
MOVE
8,16,32
MOVEM
16,32
Data Movement Operations
MOVEP
16,32
The basic method of data acquisition
(transfer and storage) is provided by the
move (MOVE) instruction. The move instruction and the effective addressing
modes allow both address and data
manipulation. Data move instructions
allow byte, word, and long word operands
to be transferred from memory to memory,
memory to register, register to memory,
and register to register. Address move instructions allow word and long word
operand transfers and ensure that only
legal address manipulations are executed.
In addition to the general move instruction, there are several special data movement instructions: move multiple register
(MOVEM), move peripheral data (MOVEP),
exchange registers (EXG), load effective
address (LEA), push effective address
(PEA), link stack (LINK), unlink stack
(UNLK), and move quick (MOVEO). Table
13 is a summary of the data movement
operations.
MOVEQ
PEA
SWAP
8
32
32
UNLK
-
Integer Arithmetic Operations
The arithmetic operations include the four
basic operations of add (ADD), subtract
(SUB), multiply (MUL), and divide (DIV) as
well as arithmetic compare (CMP), clear
(CLR), and negate (NEG). The add and subtract instructions are available for both address and data operations, with data
operations accepting all operand sizes.
Address operations are limited to legal address size operands (16 or 32 bits). Data,
address, and memory compare operations
are also available. The clear and negate instructions can be used on all sizes of data
operands.
The multiply and divide operations are
available for signed and unsigned operands using word multiply to produce a
long word product, and a long word dividend with word divisor to produce a word
quotient with a word remainder.
Multiprecision and mixed size arithmetic
can be accomplished using a set of extended instructions. These instructions
are: add extended (ADDX), subtract ex-
4-30
Operation
Rx-Ry
EA-An
An-SP@SP-An
SP+d-SP
(EAls-EAd
IEAI- An, On
An,On-EA
(EAI-On
Dn-EA
#xxx- Dn
EA-SP@On[31 :161 - Dn[15:OJ
An-Sp
SP@+-An
NOTES:
s=source
d = destination
[ 1= bit numbers
@@+
tended (SUBX), sign extended (EXT), and
negate binary with extend (NEGX).
A test operand (TST) instruction that will
set the condition codes as a result of a
compare of the operand with zero is available. Test and set (TAS) is a synchronization instruction useful in multiprocessor
systems. Table 14 is a summary of the integer arithmetic operations.
= indirect with predecrement
= indirect with postdecrement
Bit Manipulation Operations
Bit manipulation operations are accomplished using bit test (BTST), bit test and
set (BSET), bit test and clear (BCLR), and
bit test and change (BCHG). Table 17 is a
summary of the bit manipulation operations (bit 2 of the status register is Z).
Logical Operations
Binary Coded Decimal
Operations
Logical operation instructions AND, OR,
EOR, and NOT are available for all sizes of
integer data operands. A similar set of
immediate instructions (ANDI, ORI, and
EORI) provide these logical operations
with all sizes of immediate data. Table 15
is a summary of the logical operations.
Multiprecision arithmetic operations on
binary coded decimal numbers are accomplished using add decimal with extend (ABC D), subtract decimal with extend
(SBCD), and negate decimal with extend
(NBCD). Table 18 is a summary of the
binary coded decimal operations.
Shift and Rotate Operations
Shift operations in both directions are provided by the arithmetic instructions ASR
and ASL and logical shift instructions LSR
and LSL. The rotate instructions (with and
without extend) available are ROXR,
ROXL, ROR, and ROL. All shift and rotate
operations can be performed in either
registers or memory. Register shifts and
rotates support all operand sizes and
allow a shift count specified in the instruction of one to eight bits, or a to 63
specified in a data register. Memory shifts
and rotates are for word operands only
and allow only single-bit shifts or rotates.
Table 16 is a summary of the shift and
rotate operations.
Signetics
Program Control Operations
Program control operations are accomplished using a series of conditional and
unconditional branch instructions and
return instructions (see table 19). The conditional instructions provide setting and
branching for the following conditions:
CC-carry clear
CS-carry set
EO-equal
F-never true
GE-greater or equal
GT -greater than
HI-high
LE-Iess or equal
LS-Iow or same
MICROPROCESSOR DIVISION
JANUARY 1983
16-BIT MICROPROCESSOR
SCN68000 SERIES
'Pm""''''·''j
Table 15
LT-Iess than
MI-minus
NE-not equal
PL-plus
T -always true
VC-no overflow
VS-overflow
LOGICAL OPERATIONS
Instruction
Operand Size
AND
8,16,32
OR
8,16,32
Dn v IEA)- Dn
lEA) v Dn-EA
lEA) v #xxx- EA
EOR
8.16,32
IEAI.Dy-EA
lEA). #xxx- EA
8,16,32
-IEA)-EA
Operation
DnAIEA)-Dn
IEA)ADn-EA
IEA)A#xxx- EA
System Control Operations
System control operations are accomplished by using priviledged instructions,
trap generating instructions, and instructions that use or modify the status register. These instructions are summarized in
table 20.
NOT
Table 16
INSTRUCTION SET
Effective address modes can be categorized by the ways in which they may be
Instruction
16,32
Operation
Dn+ IEA)- Dn
IEA)+Dn-EA
IEAI+#xxx- EA
An+IEA)-An
8,16,32
16,32
Dx+Dy+X-Dx
Ax@-Ay@-+X-Ax@
8.16.32
8,16,32
O-EA
Dn-IEA)
IEAI-#xxx
Ax@+-Ay@+
An-lEA)
ADD
ADDX
ClR
CMP
DIVS
16.32
32+16
DIVU
32+16
EXT
8-16
16-32
MUlS
MUlU
NEG
NEGX
16·16-32
16·16-32
8,16,32
8.16,32
8,16,32
SUB
16,32
lSl
8,16,32
~
LSR
8,16,32
0+/
ROl
8,16,32
ROR
8,16,32
ROXR 8.16,32
Table 17
Dn/IEA)-Dn
Dn/IEA)-Dn
1+0
• 1--+@3
•
rn "
~
ITH·
4iH
1+0
.~
JJ
•~
H:i]J
•~
BIT MANIPULATION OPERATIONS
Instruction
BTST
Operand Size
8, 32
Operation
-bit of IEAI-Z
BSET
8, 32
IDn)8- Dn 16
IDn)16- Dn32
Dn·IEA)-Dn
-bit of IEA)-Z
1-bit of EA
BClR
8, 32
-bit of IEA)-Z
O-bit of EA
Dn·IEA)-Dn
O-IEA)-EA
BCHG
8,32
-bit of IEA)-Z
- bit of IEAI- bit of EA
0- lEA) -X- EA
Dn-IEA)-Dn
IEA)-Dn-EA
IEA)-#xxx-EA
An-IEA)-An
Table 18
SUBX
8,16,32
TAS
8
8,16,32
lEA) - 0, 1- EA[7]
IEA)-O
NDTE: [
d:J
8.16,32
ROXl 8.16,32
Dx-Dy-X-Dx
Ax@--Ay@--X-Ax@
TST
~.
ASR
INTEGER ARITHMETIC OPERATIONS
Operand Size
8,16.32
Operation
ASl 8.16,32
Addressing Categories
4
SHIFT AND ROTATE OPERATIONS
Instruc. Operand
tion
Size
The following provides information about
the addressing categories and instruction
set of the SCN68000.
Table 14
= invert
NOTE: -
BINARY CODED DECIMAL OPERATIONS
Instruction
Operand
Size
ABCD
8
SBCD
8
NBCD
8
] = bit number
Signetics
Operation
DXlO+ DylO+ X- Dx
AX@-10+AY@-10+X-Ax@
DxlO- DylO- X- Dx
AX@-10-AY@-10-X-Ax@
O-IEA)lO- X - EA
4·31
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68000 SERIES
16·81T MICROPROCESSOR
'11"';"'A"i
used. The following classifications are
used in the Instruction definitions:
Data
Memory
If an effective address mode
may be used to refer to data
operands, it Is considered a
data addressing effective address mode.
If an effective address mode
may be used to refer to memory
operands, it is considered a
memory addressing effective
address mode.
Alterable If an effective address mode
may be used to refer to alterable
(writable) operands, it is con·
sldered an alterable addressing
effective address mode.
Control
3. The last fetch from the instruction
stream is made when the operation
word is discarded and decoding is
started on the next instruction.
4. If the instruction is a single word in·
structlon causing a branch, the second
word is not used. But because this
word is fetched by the preceding in·
struction, it is impossible to avoid this
superfluous fetch. In the case of an in·
terrupt or trace exception, both words
are not used.
Table 19
BCC
DBCC
The status register addressing mode Is
not permitted unless It is explicitly mentioned as a legal addressing mode.
Operation
Branch conditionally (14 conditionsl
8- and 18-bit displacement
Test condition, decrement, and branch
16-bit displacement
Set byte conditionally (16 conditionsl
Table 20
SYSTEM CONTROL OPERATIONS
2. In the case of multiword instructions,
as each additional word of the Instruc·
tlon is used internally, a fetch Is made
to the instruction stream to replace It.
Instruction
Privileged
RESET
RTE
STOP
ORI to SR
MOVE USP
ANDI to SR
EORI to SR
MOVE EA to SR
Trap Generating
TRAP
TRAPV
CHK
Status Register
ANDI to CCR
EORI to CCR
MOVE EA to CCR
ORI to CCR
MOVE SR to EA
4·32
Signetics
Instruction Prefetch
The SCN68000 uses a two word tightly
coupled instruction prefetch mechanism
to enhance performance. This mechanism
is described in terms of the microcode
operations involved. If the execution of an
Instruction is defined to begin when the
mlcroroutlne for that Instruction is
entered, some features of the prefetch
mechanism can be described.
1. When execution of an instruction
begins, the operation word and the
word following have already been
fetched. The operation word is in the Instruction decoder.
The following contains listings of the in·
struction execution times in terms of the
external clock (ClK) periods. In this timing
data, It is also assumed that the memory
cycle time is no greater than four periods
SCC
Unconditional
Branch always
BRA
8- and 16-bit displacement
BSR
Branch to subroutine
8- and 18-bit displacement
JMP
Jump
JSR
Jump to subroutine
Raturns
RTR
Return and restore condition codes
RTS
Return from subroutine
Table 21 shows the various categories to
which each of the effective address
modes belongs. Table 22 shows the in·
structlon set.
These categories may be combined, so
that additional, more restrictive, classifications may be defined. For example, the
instruction descriptions use such classifi·
cations as alterable memory or data alterable. The former refers to those address·
ing modes which are both alterable and
memory addresses, and the latter nifers to
addressing modes which are both data
and alterable.
INSTRUCTION EXECUTION
TIMES
PROGRAM CONTROL OPERATIONS
Instruction
Conditional
If an effective address mode
may be used to refer to memory
operands without an associated
size, it is considered a control
addressing effective address
mode.
5. The program counter usually points to
the last word fetched from the instruc·
tion stream.
Operation
Reset external devices
Return from exception
Stop program execution
Logical OR to status register
Move user stack pointer
Logical AN D to status register
Logical EOR to status register
Load new status register
Trap
Trap on overflow
Check register against bounds
Logical AND to condition codes
Logical EOR to condition codes
Load new condition codes
Logical OR to condition codes
Store status register
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68000 SERIES
16-81T MICROPROCESSOR
'Rm""IIeI.iij
Table 21
EFFECTIVE ADDRESSING MODE CATEGORIES
Effective
Address
Modes
Dn
An
An@
An@+
An@An@ldl
An@ld, ixl
xxx.W
xxx.L
PC@ldl
PC@ld, ixl
#xxx
of the external processor clock input,
which prevents the insertion of wait states
in the bus cycle. The number of bus read
and write cycles for each instruction is
also included with the timing data. This
data is enclosed in parenthesis following
the execution periods and is shown as
(r/w), where r is the number of read cycles
and w is the number of write cycles. The
number of periods includes instruction
fetch and all applicable operand fetches
and stores.
Effective Address Operand
Calculation Timing
Table 23 lists the number of clock periods
required to compute an instruction's effective address. It includes fetching of any
extension words, the address computation, and fetching the memory operand.
The number of bus read and write cycles is
shown in parenthesis as (r/w). Note that
there are no write cycles inVOlved in pro·
cessing the effective address.
Move Instruction Clock Periods
Table 24 and 25 indicate the number of
clock periods for the move instruction.
This data includes fetch, operand reads,
and operand writes. The number of bus
read and write cycles is shown in parenthesis as (r/w).
Standard Instruction Clock
Periods
The number of clock periods shown in
table 26 indicates the time required to perform the operations, store the results, and
read the next instruction. The number of
bus read and write cycles is shown in
parenthesis as (r/w). The number of clock
periods plus the number of read cycles
Addressing Categories
Mode
000
Register
Data
Memory
001
010
register number
register number
register number
X
X
X
X
X
X
X
011
100
101
register number
register number
register number
X
X
X
X
X
X
X
X
X
X
110
111
111
register number
000
001
X
X
X
X
X
X
X
X
X
X
X
X
111
111
111
010
011
100
X
X
X
X
X
X
X
X
-
-
-
Control
-
must be added to those of the effective address calculated where indicated.
In table 26, the headings have the follow·
ing meanings: An = address register operand, Dn = data register operand, ea= an
operand specified by an effective address,
and M = memory effective address operand.
Immediate Instruction Clock
Periods
The number of clock periods shown in
table 27 includes the time to fetch immediate operands, perform the operations,
store the results, and read the next operation. The number of bus read and write
cycles is shown in parenthesis as (r/w).
The number of clock periods plus the
number of read and write cycles must be
added to those of the effective address
calculation where indicated.
In table 27, the headings have the follow·
ing meanings: # = immediate operand,
Dn = data register operand, M = memory
operand, and SR = status register.
Single Operand Instruction Clock
Periods
Table 28 indicates the number of clock
periods for the single operand instruc·
tions. The number of bus read and write
cycles is shown in parenthesis as (r/w).
The number of clock periods plus the
number of read and write cycles must be
added to those of the effective address
calculation where indicated.
Shift/Rotate Instruction Clock
Periods
Table 29 indicates the number of clock
periods for the shift and rotate instruc-
Signetics
Alterable
4
-
tions. The number of bus read and write
cycles is shown in parenthesis as (r/w).
The number of clock periods plus the
number of read and write cycles must be
added to those of the effective address
calculation where indicated.
Bit Manipulation Instruction
Clock Periods
Table 30 indicates the number of clock
periods for the bit manipulation instructions. The number of bus read and write
cycles is shown in parenthesis as (r/w).
The number of clock periods plus the
number of read and write cycles must be
added to those of the effective address
calculation where indicated.
Conditional Instruction Clock
Periods
Table 31 indicates the number of clock
periods required for the conditional instructions. The number of bus read and
write cycles is shown in parenthesis as
(r/w). The number of clock periods plus the
number of read and write cycles must be
added to those of the effective address
calculation where indicated.
JMP, JSR, LEA, PEA, MOVEM
Instruction Clock Periods
Table 32 indicates the number of clock
periods required for the jump, jump to
subroutine, load effective address, push
effective address, and move multiple registers instructions. The number of bus
read and write cycles is shown in parenthesis as (r/w).
4·33
MICROPROCESSOR DIVISION
JANUARY 1983
16·811 MICROPROCESSOR
SCN68000 SERIES
'm"..iirl_"j
Table 22
INSTRUCTION SET
Mnemonic
Condition
Codes
Operation
Description
X N Z V C
ABCD
Add Decimal with Extend
!Destination) 10 + (Source)lO- Destination
ADD
Add Binary
(Destination) + (Sourcel- Destination
ADDA
Add Address
!Destination) + (Sourcel- Destination
ADDI
Add Immediate
(Destination) + Immediate Data -
Destination
ADDQ
Add Quick
!Destination) + Immediate Data -
Destination
ADDX
Add Extended
AND
AND)
AND Logical
!Destination) + (Source) + X - Destination
(Destination) A (Source)- Destination
AND Immediate
(Destination) A Immediate Data -
ASL,ASR
Arithmetic Shift
(Destination) Shifted by < count> -
BCC
Branch Conditionally
BCHG
Test a Bit and Change
If CC then PC+d- PC
-«bit number» OF Destination-Z
-«bit number» OF Destination< bit number> OF Destination
BCLR
Test a Bit and Clear
Destination
Destination
-«bit number» OF Destination-Z
0 - < bit number> - OF Destination
PC+d-PC
Branch Always
BSET
Test a Bit and Set
BSR
Branch to Subroutine
Test a Bit
PC-SP@-; PC+d-PC
CLR
Check Register against Bounds
Clear an Operand
If Dn <0 or Dn> «ea» then TRAP
0 - Desiination
CMP
Compare
!Destination) - (Source)
CMPA
Compare Address
!Destination) - (Source)
CMPI
CMPM
Compare Immediate
Compare Memory
!Destination) - Immediate Data
!Destination) - (Source)
DBCC
DIVS
DIVU
Test Condition, Decrement and Branch
Signed Divide
Unsigned Divide
If- CC then Dn-1-Dn; if Dn* -1 then PC+d- PC
!Destinationll (Source) - Destination
!Destinationll (Source) - Destination
EOR
Exclusive OR Logical
(Destination). (Source) -
EORI
EXG
Exclusive OR Immediate
Exchange Register
(Destination). Immediate Data Rx-Ry
EXT
JMP
Sign Extend
(Destination) Sign-extended -
Jump
Destination -
JSR
Jump to Subroutine
LEA
LINK
Load Effective Address
Link and Allocate
PC - SP@-; Destination - PC
Destination - An
An-SP@-; SP-An; SP+d-SP
LSL, LSR
Logical Shift
(Destination) Shifted by < count> -
CHK
-«bit number» OF Destination-Z
1 - < bit number> OF Destination
-«bit number» OF Destination-Z
MOVE
Move Data from Source to Destination
MOVE to CCR Move to Condition Code
MOVE to SR
• affected
- unaffected
4·34
Move to the Status Register
o cleared
(Source) -
Destination
Destination
Destination
PC
Destination
(Source) - CCR
(Source)-SR
U defined
1 set
Signetics
U
U
-
BRA
BTST
·· · ·· · ··
- - ·· ·· ·· ·· ··
·····
- ··
- · ·
·····
- - - - - - · -
Destination
0 0
0 0
-
- - - -
·- ·-
-
- - - - U U U
- 0 1 0 0
- - - - 0
0
0 0
0 0
- - - - 0 0
- - - - - - - - - - - - - - - - -
··
····
····
····
····
···
···
··
··
··
··· ·
··
·····
·····
0
-
0 0
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68000 SERIES
16·81T MICROPROCESSOR
'mnull,j.iti
Table 22
INSTRUCTION SET (Continued)
Description
Mnemonic
Condition
Codes
X N Z V C
- - - - -
Operation
MOVE from SR Move from the Status Register
SR -
MOVE USP
Move User Stack Pointer
USP- An; An- USP
MOVEA
Move Address
(Sourcel- Destination
MOVEM
Move Multiple Registers
MOVEP
MOVEQ
Destination
- - -
-
-
-
-
-
Registers - Destination
(Sourcel- Registers
-
-
-
-
-
Move Peripheral Data
(Sourcel- Destination
-
-
-
-
-
Move Quick
Immediate Data -
-
Destination
-
" 0 0
MULS
Signed Multiply
(Destinationl" (Sourcel- Destination
-
"
0
MULU
Unsigned Multiply
(Destinationl"(Sourcel- Destination
-
"
" 0 0
NBCD
Negate Decimal with Extend
0- (DestinationllO- X -
"
U "
U
NEG
Negate
0- IDestinationl- Destination
"
"
"
"
NEGX
Negate with Extend
NOP
No Operation
0- (Destinationl- X -
"
"
-
-
NOT
Logical Complement
- lDestinationl- Destination
- - -
0
0
OR
Inclusive OR Logical
lDestinationl v (Sourcel- Destination
-
"
"
0
0
ORI
PEA
Inclusive OR Immediate
lDestinationl v Immediate Data- Destination
-
"
" 0 a
Push Effective Address
-
-
-
-
Reset External Devices
Destination- SP@-
-
RESET
-
-
- -
-
ROL, ROR
Rotate (Without Extendl
(Destination) Rotated by
"
" a "
" a "
" " "
Destination
Destination
< count>
< count>
0
"
-
Destination
-
-
Destination
"
"
"
"
-
- - -
-
-
U " U
- - -
-
ROXL, ROXR Rotate with Extend
lDestination) Rotated by
RTE
Return from Exception
SP@+-SR; SP@+-PC
RTR
Return and Restore Condition Codes
RTS
Return from Subroutine
SP@+ -CC; SP@+ SP@+-PC
SBCD
Subtract Decimal with Extend
lDestinationllO- (SourcellO- X -
SCC
STOP
Set According to Condition
Load Status Register and Stop
If CC then 1's - Destination else a's Immediate Data- SR; STOP
SUB
Subtract Binary
lDestination) - (Sourcel- Destination
SUBA
Subtract Address
SUBI
Subtract Immediate
SUBQ
Subtract Quick
PC
Destination
Destination
"
"
"
"
lDestination) - ISourcel- Destination
" "
- - -
-
-
(Destinationl-Immediate Data- Destination
"
"
"
"
lDestinationl-lmmediate Data- Destination
"
"
"
"
SUBX
Subtract with Extend
lDestinationl- (Sourcel- X- Destination
"
"
"
"
"
"
"
SWAP
Swap Register Halves
Register [31:16]- Register [15:0]
-
"
"
a
0
TAS
(Destinationl Tested- CC; 1 - [7] OF Destination
-
TRAP
Test and Set an Operand
Trap
PC-SSP@-; SR-SSP@-; IVector)-PC
-
TRAPV
Trap on Overflow
If V then TRAP
-
" " a a
- - - - - - -
TST
Test an Operand
(Destination 1 Tested- CC
-
"
"
a
UNLK
Unlink
An-SP; SP@+-An
-
-
-
-
[
a
-
] = bit number
" affected
- unaffected
a cleared
1 set
U defined
Signetics
4·35
4
MICROPROCESSOR DIVISION
JANUARY 1983
16-81T MICROPROCESSOR
Table 23
SCN68000 SERIES
EFFECTIVE ADDRESS OPERAND CALCULATION TIMING
Addressing Mode
Byte, Word
Long
010101
010101
010/01
010/01
411/01
411/01
611/01
812/01
1012/01
812101
1213/01
812/01
1012/01
411/01
812/01
812/01
1012/01
1213/01
1413/01
1213/01
1614/01
1213/01
1413/01
812101
Register
On
An
Date Register Direct
Address Register Direct
Memory
Address Register Indirect
Address Register Indirect with Postincrement
An@
An@+
An@An@(dl
Address Register Indirect with Predecrement
Address Register Indirect w~h Displacement
An@ld, ixl*
xxx.W
Address Register Indirect with Index
Absolute Short
xxx.L
PC@ldl
Absolute Long
Program Counter
PC@ld, ixl*
#xxx
Program Counter
Immediate
w~h
Displacement
w~h
Index
'The size of the index register lixl does not affect execution time.
Table 24
MOVE BYTE AND WORD INSTRUCTION CLOCK PERIODS
Source
On
An
An@
An@+
An@An@(dl
An@(d, ixl*
xxx.W
xxx.L
PC@ldl
PC@ld, ixl*
#xxx
On
An
An@
An@+
Destination
An@-
An@ldl
411/01
411101
812/01
812101
1012/01
1213/01
1413/01
1213/01
1614/01
1213/01
1413/01
812101
411/01
411/01
812/01
812/01
1012/01
1213/01
1413/01
1213/01
1614/01
1213/01
1413/01
812/01
811111
811111
1212/11
1212111
1412/11
1613111
1813/11
1613/11
2014111
1613111
1813111
1212/11
811/11
811/11
1212/11
1212/11
1412/11
1613/11
1813111
1613111
2014111
1613/11
1813111
1212111
811/11
811/11
1212/11
1212111
1412/11
1613/11
1813/11
1613/11
2014/11
1613111
1813/11
1212/11
1212/11
1212111
1613/11
1613111
1813111
2014111
2214111
2014/11
2415/11
2014/11
2214111
1613/11
An@(d,ixl*
1412/11
1412/11
1813/11
1813111
2013/11
2214/11
xxx.W
1212111
1212111
1613111
1613111
1813/11
2014111
2214111
2014/11
2415/11
2014111
2214/11
1613/11
xxx.L
1613/11
1613111
2014/11
2014/11
2214111
2415/11
2615/11
241511 I
2816111
2415111
2615/11
2014111
An@ldl An@ld,ix)*
1812/21
1612/21
1812/21
1612/21
2414121
2614/21
xxx.W
1612/21
1612/21
2414121
xxx.L
2013121
2013/21
2815121
2414/21
2614/21
2815121
3015121
2815/21
3216/21
2815121
3015121
2414/21
2414/21
2614/21
2815/21
3015121
2815121
3216/21
2815121
3015121
2414/21
2815121
3015/21
3216121
3416/21
3216/21
3617121
3215/21
3416/21
2815121
2414/11
2214111
2615/11
2214111
2414/11
1813/11
The size of the index register lixl does not affect execution time.
Table 25
MOVE LONG INSTRUCTION CLOCK PERIODS
Source
On
An
An@
An@+
An@An@(dl
An@(d, ix)*
xxx.W
xxx.L
PC@(d)
PC@(d, ix)*
'xxx
On
An
An@
411/01
411101
1213/01
1213/01
1413/01
1614/01
1814/01
1614/01
2015/01
1614/01
1814/01
1213/01
411/01
411/01
1213/01
1213/01
1413/01
1614/01
1814/01
1614/01
2015/01
1614/01
1814/01
1213/01
1211/21
1211/21
2013/21
2013121
2213121
2414/21
2614/21
2414/21
2815/21
2414/21
2614121
2013/21
An@+
1211/21
1211121
2013/21
Destination
An@-
2013/21
2213/21
2414/21
2614/21
2414/21
2815/21
2414/21
2614/21
2013/21
'The size of the index register lixl does not affect execution time.
4,36
Signetics
1411121
1411/21
2013/21
2013/21
2213/21
2414/21
2614/21
2414/21
2815121
2414/21
2614/21
2013/21
2614/21
2814121
3015/21
3215/21
3015/21
3416121
3015/21
3215/21
2614/21
MICROPROCESSOR DIVISION
JANUARY 1983
16-81T MICROPROCESSOR
SCN68000 SERIES
'RA""""·'"
Table 26
STANDARD INSTRUCTION CLOCK PERIODS
Instruction
ADD
Size
op <88>, An
op,Dn
op On,
Byte, Word
8(1/01+
6(1/01+""
4(1/0) +
6(1/0)+""
4(110)+
6(1/01+""
4(1/01+
6(1/01 +
158(1/01 +"
140(1/01 +"
4(1/01"""
8(1/01"""
70(1101 +"
70(1/01+"
4(1101+
6(1/01+""
4(1/01+
6(1/01+""
8(1111 +
12(1/21+
8(1111+
12(1/21+
Long
Long
6(1101+
6(1/01+
Byte, Word
CMP
Long
-
DIVS
-
DIVU
-
-
Byte, Word
-
Long
-
-
-
Byte, Word
-
EOR
MULS
MULU
OR
-
Long
8(1101+
6(1/01+""
Byte, Word
SUB
Long
+ add effective address calculation time
" indicates maximum value
Table 27
-
Byte, Word
AND
-
8(1/11+
12(1/21+
-
4
8(1/11+
12(1/11+
8(1/1)+
1211/21+
"" total of 8 clock periods for instruction if the effective address is register direct
""" only available effective address mode is data register direct
IMMEDIATE INSTRUCTION CLOCK PERIODS
Instruction
Size
op #, On
ADDI
Byte, Word
Long
AD DO
Byte, Word
Long
8(2101
16(3/01
411/01
8(1/01
ANDI
Byte, Word
Long
CMPI
EORI
Byte, Word
Long
Byte, Word
Long
MOVEO
Long
ORI
Byte, Word
Long
SUBI
Byte, Word
Long
SUBO
Byte, Word
Long
8(2101
16(3/01
8(2/01
14(3/01
8(2101
1613/01
4(1/01
8(2/01
op #, An
-
811/01"
8(1/01
8(2/01
14(3/01
-
lti\::J/UI
8(2/01
16(3/01
4(1/01
811/01
8(1/01"
8(1/01
op #, M
1212/11+
2013121 +
811111+
1211/21+
12(2111 +
20(3111 +
8(2/01 +
12(3/0) +
12(2/1) +
2013121 +
1212111+
2013121+
1212/1) +
20(3121+
811/11+
12(1121';-
+ add effective address calculation time
"word only
Signetics
4·37
MICROPROCESSOR DIVISION
JANUARY 1983
16-BIT MICROPROCESSOR
SCN68000 SERIES
'm"..n,I_",
Table 28
SINGLE OPERAND INSTRUCTION CLOCK PERIODS
Instruction
CLR
NBCD
NEG
NEGX
NOT
SCC
Size
Register
Byte, Word
Long
411/01
611/01
Byte
611101
Byte, Word
411/01
Long
611101
Byte, Word
Long
411101
611/01
811/11+
1211/21+
811111+
1211/21+
8(1/1)+
12(112)+
411101
Long
611/01
Byte, False
411101
Byte, True
611/01
4(110)
10(111)+
4(1/0)
411/01
411/01
4(1/0)+
Byte, Word
TST
1211/21+
8(1/1)+
Byte, Word
8yte
TAS
Memory
811111+
Long
8(1/1)+
8(1/1)+
+ add effective address calculation time
Table 29
SHIFT AND ROTATE INSTRUCTION CLOCK PERIODS
Instruction
Size
Register
ASR,ASL
8yte, Word
Long
6 + 2n(1/0)
8 + 2n(1/0)
LSR, LSL
Byte, Word
Long
6 + 2n(1/0)
8 + 2nl1/01
Byte, Word
6 + 2n(1/0)
ROR,ROL
ROXR,ROXL
Table 30
8(111)+
8(111) +
Long
8 + 2n(1/0)
-
Byte, Word
6 + 2nl1/01
8(111) +
Long
8 + 2nl1/01
-
BIT MANIPULATION INSTRUCTION CLOCK PERIODS
Instruction
8CHG
Size
Dynamic
Memory
Register
-
-
811/01*
811111+
-
-
8(111) +
Byte
Long
Static
Register
BCLR
Byte
Long
BSET
Byte
Long
811/01*
-
8yte
-
411101 +
Long
611/01
BTST
1212/01*
-
1011/01*
-
1412/01*
-
8(111)+
-
+ add effective address calculation time
* indicates maximum value
4·38
Memory
8(111) +
Signetics
-
1212/01*
1012/01
Memory
1212111+
12(2/1) +
12(211)+
812101 +
-
MICROPROCESSOR DIVISION
JANUARY 1983
16·BIT MICROPROCESSOR
'm",,""···,
SCN68000 SERIES
Multi·Precision Instruction Clock
Periods
Exception Processing Clock
Periods
Table 33 indicates the number of clock
periods required for the multi-precision in·
structions. The number of clock periods
include the time to fetch both operands,
perform the operations, store the results,
and read the next instructions. The number of bus read and write cycles is shown
in parenthesis as (r/w).
Table 35 indicates the number of clock
periods required for exception processing. The number of clock periods includes
Table 31
CONDITIONAL INSTRUCTION CLOCK PERIODS
Trap or Branch
Not Taken
81110)
Word
Trap or Branch
Taken
1012/0)
1012/0)
BRA
Byte
Word
1012/0)
1012/0)
-
BSR
Byte
Word
1812/21
1812/21
DBCC
CC true
CC false
Displacement
Instruction
Byte
BCC
In table 33, the headings have the following meaning: Dn data register operand
and M = memory operand.
=
Miscellaneous Instructions Clock
Periods
Table 34 indicates the number of clock
periods required for miscellaneous instructions. The number of bus read and
write cycles is shown In parenthesis as
(r/w). The number of clock periods plus the
number of read and write cycles must be
added to those of the effective address
calculation where indicated.
Table 32
Size
JMP
JSR
LEA
PEA
Word
An@
812/01
1612/21
411/01
1211/21
12+4n
Long
MOVEM
Word
R -M
Long
An@+
-
12+8n
12+4n
13 + n/Oi
12+8n
13+ 2n/01
13+ 2n/0i
13+ nlOI
M -R
TRAP
TRAPV
4
-
1212/0)
1413/0)
811/0)+
1012/0)
-
CHK
1212/0)
4015131+
3414/31
3415/31
*
411/01
+ add effective address calculation time
indicates maximum value
*
JMP, JSR, LEA, PEA, MOVEM INSTRUCTION CLOCK PERIODS
Instr
MOVEM
the time for all stacking, the vector fetch,
and the fetch of the first instruction of the
handler routine. The number of bus read
and write cycles is shown in parenthesis
as (r/wi.
8+5n
12/nl
8+ IOn
12/2nl
-
-
An@-
-
8+5n
12/nl
8+10n
12/2nl
An@ldl
1012/01
1812/21
812/01
1612/21
16+4n
14+n/01
16+8n
14+2n/0i
12+5n
13/nl
12+10n
13/2nl
xxx.W
1012/01
1812/21
An@ld, ixl*'
1413/01
2212121
1212/01
2012/21
18+4n
14+ nlOI
18+8n
14+2n/0i
14+5n
13/nl
14+10n
13/2nl
812101
1612/21
16+4n
14+n/01
16+8n
14+ 2n/0i
12+50
13/nl
12+10n
13/2nl
xxx.L
1213/01
2013/21
1213/01
2013121
2O+4n
15 + n/Oi
20+8n
15+2n/0i
16+5n
14/nl
16+10n
14/2nl
PC@ldl
1012/01
1812/21
812101
1612/21
16+4n
PC@ld, ixl*
1413/01
221'-121
12,~/Q)
2012/21
16+8n
14+2n/0i
18+4n
14 + n/Oi
18+8n
14+ 2n/0i
-
-
14+ n/Oi
-
-
-
-
-
n is the number of registers to move
* the size of the index register lixl does not affect the instruction's execution time
Table 33
MULTI·PRECISION INSTRUCTION CLOCK PERIODS
Size
op On, On
ADDX
Byte, Word
Long
4(1/01
8(110)
CMPM
Byte, Word
Long
-
SUBX
Byte, Word
Long
411/01
811101
ABCD
Byte
611/01
SBCD
Byte
611/01
Instruction
Signetics
op M, M
18(3/11
30(5/21
12(3/0)
20(5101
18(3/11
3015/21
1813/11
1813/11
4·39
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68000 SERIES
16·81T MICROPROCESSOR
'm"..Ii,I_"t
Table 34
MISCELLANEOUS INSTRUCTIONS CLOCK PERIODS
Instruction
MOVE from SR
MOVE to CCR
MOVE to SR
MOVEP
EXG
EXT
Size
-
Register
6(1/0)
12(2/01
12(2/0)
Long
-
-
6(110)
-
Word
411101
4(1/01
-
Long
-
MOVE from USP
-
1612/2)
4(1101
MOVE to USP
-
4(1/01
4(1/01
132(1/01
20(510)
NOP
RESET
RTE
RTR
RTS
STOP
SWAP
UNLK
12(2/0)+
-
Word
-
LINK
Memory
8(111) +
12(2/01+
-
-
20(5/01
16(4/0)
-
Address Error
Bus Error
50(4171
441513)*
34(4/3)
Illegal Instruction
Privileged Instruction
Trace
16(4/0)
24(6/01
2412/4)
-
-
-
-
-
410101
4(1/01
-
-
12(3/01
-
-
34(4/3)
34\4131
* The interrupt ac~nowledge bus cycle is assumed
to take four external clock periods
4·40
16(2/2)
-
-
Periods
50(4171
Interrupt
-
-
EXCEPTION PROCESSING CLOCK PERIODS
Exception
Memory -Register
-
-
+ add effectIve address calculatIon tIme
Table 35
Register - Memory
Signetics
-
-
-
-
-
MICROPROCESSOR DIVISION
JANUARY 1983
16·811 MICROPROCESSOR
SCN68000 SERIES
'tIE1""li".Irj
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
RATING
UNIT
Supply voltage
Input voltage3
Operating temperature range 2
Storage temperature
-0.3 to + 7.0
-0.3to + 7.0
o to + 70
-55to +150
V
V
·C
·C
DC ELECTRICAL CHARACTERISTICS
Vcc= 5.0V ± 5%, Vss= OV; TA = O·C to + 70·C (see figures 37-39)4,5
PARAMETER
TEST CONDITIONS
V 1H
Input high voltage
V 1L
Input low voltage
lin
Input leakage current
BERR, BGACK, BR, DTACK, CLK, IPOO-IPL2, VPA
HALT, RESET
I TS1
Three-state (off state) input current
AS, A1-A23, DO-D15, FCO-FC2, LDS, R/W, UDS, VMA
V OH
Output high voltage
E6
AS, A1-A23, BG, 00-015, FCO-FC2, LOS, R/W, UOS, VMA
VOL
PD
Power dissipation
Capacitance
UNIT
Max
2.0
Vcc
V
Vss-0.75
0.8
V
2.5
20
"A
"A
20
"A
5.25V
2.4V/0.4V
10H= -400"A
V
V
Vcc-0.75
2.4
Output low voltage
HALT
A1-A23, BG, FCO-FC2
RESET
E, AS, DO-D15, LOS, R/W, UOS, VMA
Cin
LIMITS
Min
10L= 1.6mA
IOL=3.2mA
IOL=35.0mA
IOL=5.3mA
0.5
0.5
0.5
0.5
V
V
V
V
Clock frequency = ·MHz
1.5
W
Vin=OV, T A =25·C,
frequency = 1MHz
10.0
pF
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device
at these or at any other condition above those indicated in the operation section of this specification is not implied.
2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum Junction temperature.
3. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested
that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
5. All voltage measurements are referenced to ground (GNO). For testing, all input signals swing between O.4V and 2.4V with a transition time of 20ns maximum. All time
measurements are referenced at input voltages of O.BV and 2.0V and output voltages of O.BV and 2.0V as appropriate.
6. With external pullup resistor of 470 ohms.
7. For a loading capacitance of less than or equal to 500pF, subtract 5ns from the values given in these columns.
B. Actual value depends on clock period.
9. If #47 is satisfied for both DTACK and BEAR, #48 can be Ons.
10. After VCC has been applied for lOOms.
11. If the asynchronous setup time (#47) requirements are satisfied, the DTACK low-to-data setup time (#31) requirements can be ignored. The data must only satisfy the data-in to
clock-low setup time (#27) for the following cycle.
Signetics
4·41
4
MICROPROCESSOR DIVISION
JANUARY 1983
16·81T MICROPROCESSOR
'w""""_,,,
AC ELECTRICAL SPECIFICATIONS
VA
SCN68000 SERIES
=5VDC, TA =O·C to 70·C (see figures 41_45)4,5
TENTATIVE LIMITS
NUMBER
CHARACTERISTIC
SYMBOL
8MHz
"MHz
8MHz
lOMHz
Min
Max
Min
Max
Min
Max
Min
Max
UNIT
1
Clock period
teye
250
500
167
500
125
500
100
500
2
Clock width low
tCl
115
250
75
250
55
250
45
250
ns
ns
3
Clock width high
tCH
115
250
75
250
55
250
45
250
ns
4
Clock fall time
tct
10
10
10
10
ns
5
Clock rise time
tcr
10
10
10
10
ns
6
Clock low to address
tCLAV
90
80
70
55
ns
6A
Clock high to FC valid
tCHFCV
90
80
70
60
ns
7
Clock high to address data high
impedance (maximum)
tCHAZx
120
100
80
70
ns
8
Clock high to address/FC invalid
(minimum)
t CHAZn
97
0
0
0
ns
0
Clock high to AS, OS low (maximum)
tCHSlx
10
Clock high to AS, OS low (minimum)
tCHSln
0
0
0
0
ns
11 8
Address to AS, OS (read) low/AS write
tAVSl
55
35
30
20
ns
IFCVSl
80
80
70
60
55
ns
llA8
FC valid to AS, OS (read) low/AS write
127
Clock low to AS, OS high
138
AS, OS high to address/FC Invalid
ISHAZ
60
40
30
20
ns
148
AS, OS width low (read)/AS write
tSl
535
337
240
195
ns
285
170
115
95
ns
285
180
150
105
70
90
tCLSH
60
80
50
70
ns
55
ns
14A8
OS width low (write)
157
AS, OS width high
tSH
16
Clock high to AS, OS high impedance
t CHSZ
178
AS, OS high to R/W high
tSHRH
187
Clock high to R/W high (maximum)
tCHRHx
19
Clock high to RIW high (minimum)
tCHRHn
207
Clock high to R/W low
tCHRl
21 8
Address valid to R/W low
tAVRl
45
25
20
0
21A8
FC valid to R/W low
tFCVRl
80
70
60
50
ns
228
R/W low to OS low (write)
t RlSl
200
140
80
50
ns
120
60
100
40
50
90
20
0
0
ns
ns
60
0
70
80
ns
70
70
80
90
0
80
ns
ns
60
ns
ns
23
Clock low to data out valid
t ClOO
90
80
70
55
ns
24
Clock high to R/W, VMA high Impedance
tCHRZ
120
100
80
70
ns
258
OS high to data out invalid
268
Data out valid to OS low (write)
2711
Data in to clock low (setup time)
288
29
30
31 8
tSHoO
60
40
30
20
tOOSl
55
35
30
20
ns
t DlCl
30
25
15
15
ns
AS, OS high to OTACK high
tSHOAH
0
OS high to data invalid (hold time)
t SHOI
0
AS, OS high to BERR high
tSHBEH
0
DTACK low to data in (setup time)
tOAlOI
t RHrt
240
0
160
0
120
0
0
180
0
32
HALT and RESET input transition time
Clock high to BG low
34
Clock high to BG high
35
BR low to BG low
tBRlGl
1.5
3.0
1.5
3.0
1.5
3.0
35
BR low to BG low (figure 43)
tBRlGl
1.5
3.5
1.5
3.5
1.5
3.5
ns
ns
0
90
33
4·42
90
0
0
120
0
ns
ns
65
ns
200
ns
tCHGl
90
80
70
60
ns
t CHGH
90
80
70
60
ns
1.5
3.0
Clk Per
1.5
3.5
Clk Per
0
Signetics
200
0
200
0
200
0
MICROPROCESSOR DIVISION
JANUARY 1983
16·BIT MICROPROCESSOR
SCN68000 SERIES
'am",,)iel-"j
AC ELECTRICAL SPECIFICATIONS (Continued) VA = 5VDC, TA = O'C to 70'C (see figures 41_45)4,5
TENTATIVE LIMITS
NUMBER
CHARACTERISTIC
SYMBOL
4MHz
8M Hz
Min
Max
Min
8MHz
10MHz
Max
Min
Max
Min
UNIT
Max
36
BR high to BG high
tBRHGH
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
Clk Per
37
BGACK low to BG high
tGALGH
1.5
3.0
1.5
3.0
1.5
3.0
1.5
3.0
Clk Per
38
BG low to bus high Impedance (AS high)
tGLZ
39
BG width high
tGH
40
Clock low to VMA low
tCLvML
90
80
70
70
41
Clock low to E transition
tCLC
100
85
70
55
ns
42
E output rise and fall time
tErt
25
25
25
25
ns
43
VMA low to E high
tVMLEH
325
44
AS, OS high to VPA high
tSHVPH
0
45
E low to addresslVMA/FC Invalid
tELAI
55
35
30
10
ns
46
BGACK width
t BGL
1.5
1.5
1.5
1.5
Clk Per
47 11
Asynchronous Input setup time
t ASI
30
25
20
20
ns
489
BERR low to DTACK low
tBELOAL
50
50
50
50
ns
ns
120
1.5
100
70
1.5
1.5
240
240
80
1.5
200
160
0
0
150
120
ns
Clk Per
ns
4
ns
0
90
ns
49
E low to AS, OS Invalid
tELSI
-80
-80
-80
-80
50
E width high
tEH
900
600
450
350
ns
51
E width low
tEL
1400
900
700
550
ns
52
E extended rise time
tCIEHX
80
80
80
80
ns
53
Data hold from clock high
t CHOO
0
0
0
0
ns
ns
54
Data hold from E low (write)
tELOOZ
80
40
30
20
55
RIW to data bus Impedance change
t RLOO
55
35
30
20
ns
56 10
Halt/RESET pulse width
tHRPW
10
10
10
10
Clk Per
CLOCK TIMING (see figure 40)
CHARACTERISTIC
SYMBOL
4MHz
Min
6MHz
Max
Min
8MHz
Max
Min
10MHz
Max
Min
Max
UNIT
Frequency of Operation
F
2.0
4.0
2.0
6.0
2.0
8.0
2.0
10.0
MHz
Cycle Time
tCYC
250
500
167
500
125
500
100
500
ns
Clock Pulse Width
tCL
tCH
115
115
250
250
75
75
250
250
55
55
250
250
45
45
250
250
ns
Rise and Fall Times
tCr
tCt
-
10
10
-
-
10
10
-
10
10
-
10
10
ns
POWER CONSIDERATIONS
The average chlp·junction temperature, TJ,
in ·C can be obtained from:
TJ = TA + (PO"OJA)
(1)
Where:
TA'" Ambient Temperature, ·C
0JA'" Package Thermal Resistance,
Junction·to·Ambient, 'C/W
Po" P,NT + PliO
(2)
-
P,NT'" Icc x Vcc , Watts - Chip
Internal Power
PliO'" Power DIssipation on Input and
Output Pins - User Determined
For most applications PIIO-CP'NT and can
be neglected.
An approximate relationship between Po
and TJ (If PliO is neglected) is:
Po= K ... (TJ + 273'C)
Signetics
Solving equations 1 and 2 for K gives:
K=P O"(TA+273'C)+OJA"P 0 2
(3)
Where K is a constant pertaining to the
particular part. K can be determined from
equation 3 by measuring Po (at equill·
brium) for a known T A' Using this value of
K the values of Po and TJ can be obtained
by solving equations (1) and (2) Iteratively
for any value of T A'
4·43
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68000 SERIES
16·81T MICROPROCESSOR
'IA""""·""
+5V
R*=7400
+5V
+5V
Q
C
~
I
MM06150
Test
Point
9100
Rl
ClI
130pF
Figure 37. Reset Test Load
I
MM07000
or
Equivalent
70PF
Cl= 130 pF
(Includes all Parasitics)
Rl =6.0 kO for
~, Al-A23, BG, 00-015, E
FCO-FC2, lOS, R/IN, UOS, VMA
*R = 1.22 kO for Al-A23, BG,
E, FCo-FC2
Figure 38. Halt Test Load
Figure 39. Test Loads
All timing diagrams should only be referenced In regard to the edge·to-edge measurement of the timing specifications. They are not
Intended as a functional description of the Input and output signals. ~efer to other functional descriptions and their related diagrams
for device operation.
~-------
tcyc-----+i
Figure 40. Input Clock Timing
4·44
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68000 SERIES
16-81T MICROPROCESSOR
'm""",I_.,,
4
Asynchronous
Inputs
INote 11
-------------+-""\J,:,.--+----+-+I-------
BERR/BR-------------~
INote 21
Data In -
-
-
-
-
-
-
-
-
-
-
-
-
-
NOTES:
1. Setup time for the asynchronous inputs BGi'iCK, ipLo-IPL2, and VPA guarantees their recognition at the next falling edge of the clock.
2. BR need fall at this time only in order to insure being recognized at the end of this bus cycle.
Figure 41. Read Cycle Timing
Signetics
4·45
MICROPROCESSOR DIVISION
JANUARY 1983
16-BIT MICROPROCESSOR
SCN68000 SERIES
'm""UeI.i"
so
CLK
---'
-
A1-A23
-1+
J
J
R/IN
S2
S1
S3
r--,~
~
~6
~ ~--+
f+-® --..
r+- H®
f-
~
S5
'15'
-.:
"
~
---+-
~
f.- ®
.-@+ f.- r-@)---'
1--+ f+-@
-+
'-
....
f0
.-@
,....
14
~
~
-.
~
~@)
@
-II
@ r+--
----+
~®
.X
Asynchronous
Inputs
>~f-
®~ ....
..-@
--+~
~@
®---.
~
..-@+
\
}~
I[-
~
~@
1\_
@
Figure 42. Write Cycle Timing
4·46
I---+-
14
"'"""
Data Out
so ...
/
@)--..
_(7) ~8-+
S7
S6
~ ~ r=---'
r.-@
~
I
FCO-FC2
S4
Signetics
@--+
J r-
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68000 SERIES
16·BIT MICROPROCESSOR
'm",,""·",
Strobes
and RiVii
- - -_ _ _ _---'
I+---@--~
4
ClK
NOTES:
1. Setup time for the asynchronous inputs
edge of the clock.
BEiiR, BGACK, iiR, DTACK, IPlO-IPL2, and VPA guarantees their recognition at the next falling
Figure 43. AC Electrical Timing-Bus Arbitration
Signetics
4·47
of"
I
t
50
51
52
53
54
w
w
w
w
w
w
w
w
w
55
w
56
57
50
~
0-
•
cg
:::;
3:
0;0
0"V
;0
s::
0
:0
0
"1J
:0
0
0
m
~:0
0
~
en
0
Z
0
0m
elK
en
en
Al-A23
A5
@
:::J
/11 III Ii -
b~
E
0;0
@
en
cO·
VPA
::J
m:
0
VMA
en
Dat. Out
Data In
_________________________________________ _
NOTE: This figure represents the best case synchronous timing where VPA falls before the third system clock cycle after the falling edge of E.
en
0
Z
0C»
C
C
C
en
m
Figure 44. Synchronous Timing-Best Case
22
m
en
5;
z
c
»
:0
<
-0
00
'"
II
SO
Sl S2 .S3 S4
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
S5 56 S7 SO
~
s:
~
•
;u
::::j
;u
0;g
0
0
;u
c:g
s:
"V
elK
;g
A1-~ J--(
AS
i
0
""C
0
0m
en
en
0
<:
U5
az
0
0m
If
I
0
en
en
I
0
;g
so.
VPA
CO
:::J
VMA
en
R/W
(Readl
~
®
Data In
UDS/[55
Read
R/WW,ite
®
@)
Data Out
UDS/[55
en
Write
0
Z
~
C»
0
0
0
01:0
~
Figure 45. Synchronous Timing-Worst Case
~
L.
>
Z
en
m
;g
;u
en
m
-<
0>
'"
JANUARY 1983
MICROPROCESSOR DIVISION
16·81T MICROPROCESSOR WITH 8·BIT BUS
SCN68008
PRODUCT BRIEF, contact your Signetlcs sales office for complete information.
DESCRIPTION
The SCN68008 is a member of the S68000
Family of advanced microprocessors. This
device allows the design of cost effective
systems using 8-blt data buses while providing the benefits of a 32-bit microprocessor architecture. The performance
of the SCN68008 is greater than any 8-bit
microprocessor and superior to several
16-bit microprocessors.
The resources available to the SCN68008
user consist of the following:
o 17 32-bit data and a<;tdress registers
o 56 baSic instruction types
o Extensive exception processing
o Memory mapped 1/0
o 14 addressing modes
o Complete code compatibility with the
SCN68000
A system Implementation based on an
8-bit data bus reduces system cost in
comparison to 16-bit systems due to a
more effective use of components and the
fact that byte-wide memories and peripherals can be used much more effectively.
In addition, the non-multiplexed address
and data buses eliminate the need for external demultiplexers, thus further Simplifying the system.
The SCN68008 has full code compatibility
(source and object) with the SCN68000
which allows programs to be run on either
MPU depending on performance requirements and cost objectives.
The programmer's model is Identical to
that of the SCN68000, as shown in figure
1, with seventeen 32-bit registers, a 32-bit
program counter, and a 16-bit status register. The first eight registers (00-07) are
used as data registers for byte (8-bit), word
(16-bit), and long word (32-bit) operations.
The second set of seven registers (AO-A6)
and the system stack pointer (A7) may be
used as software stack pointers and base
address registers. In addition, the
registers may be used for word and long
word operations. All of the 17 registers
may be used as index registers.
FEATURES
o 32-blt data and address registers
o
o
o
o
o
o
o
1-megabyte direct addressing range
56 powerful instruction types
Operations on five main data types
Memory mapped 1/0
14 addressing modes
Source and object compatible with
SCN66000
48-pin DIP
31
16 15
6 7
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-....
31
f-
r
I
r
r-
DO
-
D1
TOP VIEW
D2
-
D3
-
-
D4
EIGHT
DATA
REGISTERS
D5
-
-
D6
-
AD
-
A5
D7
16 15
I
I
I
I
I
I
I
I
I
A1
A2
A3
SEVEN
ADDRESS
REGISTERS
A4
A6
TWO STACK
POINTERS
PROGRAM
COUNTER
15
I
6 7
SYSTEM BYTE:
0
USER BYTE
I
STATUS
REGISTER
Figure 1. Programming Model
4·50
PIN CONFIGURATION
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
16-BIT MICROPROCESSOR WITH 8-BIT BUS
The 1-megabyte non-segmented linear address space of the SCN68008 allows large
modular programs to be developed and executed efficiently. A large linear address
space allows program segment sizes to be
determined by the application rather than
forcing the designer to adopt an arbitrary
segment size without regard to his individual requirements.
Exception processing allows the
SCN68008 to handle interrupts, address
errors, unimplemented instructions, and
other commonly encountered exceptions
while maintaining absolute system integri·
ty. The exception processing state is
associated with interrupts, trap instructions, tracing, and other exceptional conditions. An exception may be generated
internally by an instruction or by an
unusual condition occurring during program execution. Exception processing
provides an efficient context switch to
enable the processor to handle unusual
conditions without degrading system
integrity.
SCN68008
FUNCTIONAL DIAGRAM
,--------------------------------,
Vee
~
--.E!:4
AO·A19
~
BUSY
~
00·07
BUS
AS
R/Vi
FCO
PROCESSOR!
STATUS
FC2
E
OTACK
1
ASYNCHRONOUS
BUS CONTROL
...!Li!G
PERIPHERAL!
CONTROL
)
4
BUS ARBITRATION
CONTROL
VPA
BEliR
SYSTEM!
CONTROL
OS
FCl
IPLO/2
RESET
Signetics
HALT
j
lNTERRUPT
CONTROL
IPLl
4·51
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'm""""·"j
DESCRIPTION
FUNCTIONAL DESCRIPTION
The SCN68120/SCN68121 Intelligent Peripheral Controllers (IPCs) are general purpose, mask programmable peripheral controllers. The IPC provides the interface
between an S68000 or M6800 family micro. processor (or microprocessors with equivalent synchronous interfaces) and the
final peripheral device through a system
bus and control lines. System bus data is
transferred to and from the I PC via a dualport RAM while the software utilizes
semaphore registers to control RAM tasking or any shared resource. Multiple
operating modes range from a single chip
mode with 21 1/0 lines and two control
lines to an expanded mode supporting an
address space of 64K bytes. The
SCN68121 utilizes only the expanded address modes, due to the absence of an onchip ROM.
A serial communications interface, 16-bit
timer, dual-ported RAM and semaphore
registers are available for use by the IPC in
all operating modes.
FEATURES
•
System bus compatible with the asynchronous S68000 family
• System bus compatible with the synchronous M6800 family processorsl
peripherals (or microprocessors with
equivalent synchronous Interfaces)
• Compatible with Motorola 6801 source
and object code
• Upward compatible with Motorola 6800
source and object code
• 2048 bytes of ROM (SCN68120 only)
• 128 bytes of dual-ported RAM
• Multiple operation modes ranging from
single chip to expanded, with 64K byte
address space
• Six shared semaphore registers
• 21 parallel I/O lines and two handshake
lines (five I/O lines on the SCN68121)
• Serial communications interface (SCI)
• 16-blt three-function timer
• 8·bit CPU and internal bus
• Halt/bus available capability control
• 8)( 8 multiply instruction
• TTL compatible inputs and outputs
• External and internal interrupts
PIN CONFIGURATION1
The SCN68120/SCN68121 are 8-bit Intelligent Peripheral Controllers which can be
configured to function in a wide variety of
applications. This flexibility is provided by
its ability to be hardware programmed into
eight different operating modes. These
operating modes allow the IPC to operate
on its local bus and communicate with an
external system bus through the Internal
dual-port RAM. The operating mode con·
trois the configuration of 18 of the 48 pins
on the IPC, the available on-Chip
resources, the memory map, the location
(internal or external) of interrupt vectors,
and the type of local bus. The configura·
tion of the remaining 30 pins is not controlled by the operating mode.
The dual-port RAM provides a vehicle for
devices on two separate buses to exchange data without directly affecting the
devices on the other bus. The dual·port
RAM is accessible from the IPC's CPU and
accessible synchronously or asynchronously to the system bus through
port 1. Semaphore registers are provided
as a software tool to arbitrate shared
resources such as the dual-port RAM. The
semaphore registers are accessible from
both buses In the same way each bus accesses the dual-port RAM.
The remaining ports (2, 3, and 4) are 1/0
ports. Each port is controlled by its data
direction register. The CPU has direct access to the port pins of each port through
Its data register. Port pins are labelled as
Pij' where i identifies one of three ports
and j indicates the particular bit. Port 2 is a
5-bit port which can be configured for 1/0
or for use by the on-chip timer and serial
communications interface (SCI). Ports 3
and 4 may be used as 16-bits of 1/0 or may
form a local address and data bus with
control lines allowing comunications with
external memory and peripherals.
The IPC contains a synchronous MPU
which is upward source and object code
compatible with the Motorola MC6800 and
directly compatible with the MC6801. The
programming model is shown in Figure 1,
where accumulator D is a concatenation
of accumulators A and B.
The SCN68121 has all of the features of
the SCN68120 except for the on-CHIP
ROM. Thus, the SCN68121 operates only
in the modes utilizing external ROM
(modes 2 and 3).
DUAL PORT RAM AND
SEMAPHORE REGISTERS
The dual-port RAM can be accessed from
both the SCN68120/SCN68121 CPU and
the external system bus. The six semaphore registers are tools provided for the
programmer's use in arbitrating simultaneous accesses of the same resource.
For the internal CPU, the dual-port RAM is
located from $0080 through $OOFF in all
modes except 3 and 4. In mode 3, the dualport RAM has been relocated in high
ORDERING CODE
VCC=5V ±5%,TA =0·t070·C
Packages
With ROM
1.0MHz
1.25MHz
Without ROM
1.0MHz
1.25MHz
Ceramic DIP SCN68120Cl148 SCN68120C2148 SCN68121Cl148 SCN68121 C2148
Plastic DIP SCN68120Cl N48 SCN68120C2N48 SCN68121C1 N48 SCN68121C2N48
4·52
Signetics
11n thl, data
she.t, barring lignal nam•• (overseol'l) to
indicate low I, done only for the pin connguratlon
diagram, Ilgnal description heading., tablas and
ligures.
JANUARY 1983
MICROPROCESSOR DIVISION
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'amn"i..i.'*,
/
~--------~~----------~,
~ Ili0d
,~lg~
1.
u en
en en en
en en en en
Q
II)
4
.,
.,:::>
...c
--u
9
DATA
or
0-
..
Il:
0
ADDRESS
g
P40
P41
P42
P43
P44
P4S
P46
P47
A8
AO
A9
A10
A11
A12
A1
A2
A3
A4
A13
A14
AS
A6
A1S
A7
1/0
1/0
1/0
1/0
UO
UO
1/0
1/0
SC1 AS
loS
153
SC2 RiW
P30 AO/DO
P31 AlID1
Rfii
0s3
DO
D1
P32 A2ID2
P33 A3/D3
P34 A4ID4
D2
D3
D4
I TOUT P21
P3S ASIDS
P36 A6ID6
UO TIN P20
P37 A7/D7
DS
D6
D7
110
UO
1/0
UO
1/0
1/0
1/0
110
..Ii:
..g
0
1/0 TDATA P24
1/0 RDATA P23
1/0 SCLK P22
--....
w
III...
5:::>
..
:IE
w
..
z
c
><
w
SigneHcs
.III ..:c
w
.....5
:::>
II!!
z
0
z
u
...w
"zin
..
w
z
::>----tCLK
PRE
0
D
U2.
U2b
'--+---tCLK
01---.......
CLR
Ul, U2 - SN74LS74
U3 - SN74LS02
TIMING
4
'0
01
02
03
J
04~
~_~r
EJ
.AS
II
~
L - -_ _......
0
Figure 6. Clock Clrcuil Example·2 - Schemalic and Timing
4·58
AS
Signetics
10---.0
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""II".iij
Table 3. DUAL PROCESSOR SEMAPHORE BIT TRUTH TABLE
IPC
Original
SEM Bit
0
1
1
1
0
0
1
0
R/W
R
R
W
R
W
R
W
W
~tem
Data
Read
0"
1"
-
1
-
O·
-
Resulting
SEM Bit
1
0
0
1
0
1
0
1
Data
Read
l'
R/W
R
W
R
R
W
W
W
R
l'
l'
O·
PROPER
IMPROPER
"0 - Resource Available
1 - Resource Not Available
An access where both the IPC and system
processors attempt to read or write the
same semaphore register simultaneously
is a contested access. During a contested
access, the hardware decides which pro·
cessor reads a clear semaphore bit and
which reads a set semaphore bit. Table 3
describes contested operation of a semaphore bit.
The IPC always reads the actual
semaphore bit; the system processor
reads the semaphore bit in all cases except the simultaneous read of a clear
semaphore bit. This arbitration during a
simultaneous read ensures that only one
processor reads a clear bit and therefore
controls the resource; that processor Is arbitrarily the IPC.
In Table 3, the first four states are considered proper and they occur in correctly
written software. The last four states are
improper and only exist in improperly written software.
The ownership bit is a read-only bit that indicates which processsor sets the semaphore bit. If the semaphore bit is set, the
ownership bit indicates which processor
set it. If the semaphore bit is not set, the
ownership bit indicates which processor
last set the semaphore bit: OWN = 0, the
other processor set SEM; OWN = 1, this
processor set SEM.
The reset state of the semaphore and
ownership bits Is defined In Table 4. All of
the semaphore bits are set after an I PC
reset. The IPC owns all of them except the
second semaphore which Is owned by the
system processor. This configuration
should prevent the system processor from
reading a clear semaphore and Implying
4
the system processor set it when the IPC
RESET is held low.
FUNCTIONAL PIN
DESCRIPTIONS
PROGRAM STORAGE MEMORY
- ROM
Vee and Vss
The standard SCN68120 comes preprogammed with a monitor in the ROM.
Custom programs are placed in ROM by
special order (see appendix A).
The SCN68120 contains 2048 bytes of onchip, mask programmable read-only
memory (ROM) in memory locations $F800
through $FFFF. The contents of this ROM
allows the IPC to perform a custom function for the user. The interrupt vectors
$FFFO-$FFFF are decoded to provide vectors at the top of resident ROM. Address
lines A12 and A13 of the decoder for the
ROM can be mask programmed as a 0 or 1
to change the ROM starting address from
$F800 to $C800, $0800 or $E800. A12 and
A13 can also be 'don't cares' in this
decoder. Address $FFEF is reserved for
the checksum value for the ROM. This
value is the complement of the exclusive
OR of the 2047 bytes of mask programmed
ROM. An IPC without ROM is also available as the SCN68121. The SCN68121
should only be used in modes 2 and 3 to
access external ROM after reset.
Vcc and Vss provide power and ground to
the IPC.
RESET
Provides the IPC with an orderly and defined start-up procedure from a powerdown condition, returns to start-up conditions without an intervening power-down
condition and provides a control signal to
latch the operating mode.
During reset (low logic level on RESET
pin), execution of the current instruction
is suspended and the CPU enters a 'reset
state'. The register contents are not
pushed onto the stack and their contents
become undefined during reset. The 'reset
state' initializes the IPC as shown in Table 5.
On the positive edge of RESET, the IPC
latches the operating mode from P22, P21
and P20, and then configures port 3, port
4, SC1 and SC2. The restart vector is then
fetched and transferred to the program
counter, and then instruction execution
begins.
Table 4. RESET STATE OF SEMAPHORE REGISTER
SEM
Reg
No.
1
2
3
4
5
6
IPC
Sem
1
1
1
1
1
1
Signetics
System
Own
1
0
1
1
1
1
Sem
1
1
1
1
1
1
Own
0
1
0
0
0
0
4·59
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'mil"ileI.'"
Reset timing is illustrated in Figure 7. The
RESET line must be held low for a
minimum of three E·cycles for the IPC to
complete its entire reset sequence. An ex·
ternal RC network may be used to obtain
the required timing.
negative half·cycle of E and the selected
device must be enabled to the data bus
during the next positive half·cycle. The
data bus is active only while E is high. It
should be noted that this input should
have some provision to obtain the
specified logical high level which is
greater than standard TIL levels.
Enable (E)
The E clock input is required for timing to
synchronize data bus transfers. A 'CPU
E·cycle' (or bus cycle) consists of a
negative half·cycle of E followed by a
positive half·cycle. For any given bus cy·
cle, the address is valid during the
Enable Is the primary IPC system timing
signal and all timing data specified as
cycles is assumed to be referenced to the
clock unless otherwise noted.
Halt/Bus Avaiiable/Nonmaskable
Interrupt (HAL T/BAINMI)
This pin functions as either NMI or
HALT/BA and the function selected is
determined by the halt control (HC, bit 2)
bit of the functional control register (Ioca'
tion $14). If the HC bit is set (to a '1'), then
the NMI function is activated. Alternately,
if HC is cleared (to a '0' as it is during
reset), the HALT/BA function is activated.
An external pullup resistor to Vcc is reo
quired on pin 3 for either function. Typical
pullup resistor values range from 3K to
Table 5. STATE OF IPC DURING RESET
Effective State
Bits or Registers
SCI Transmit/ Receive Control and Status Register
Output Compare Register
Semaphore Bits
Ownership Bit of Semaphore Register 2
All other Ownership Bits
set IIRQl and IRQ2 disabledl
cleared (NMI disabled)
cleared (HALT/BA selected)
cleared
cleared
cleared
cleared
cleared
cleared
cleared
undefined after Power·up Reset; and not changed after
Reset
Preset to $20
Preset to $FFFF
Preset to l's
Preset to System Ownership
Preset to IPC Ownership
All Ports 2 and 3 Lines
All Port 4 Lines
SC1"
SC2
High Impedance !inputs)
High Impedance !inputs) with pull up resistors
High Impedance with pullup resistors
Active High
CPU I·Bit
N M I Interrupt Latch
Halt Control Bit
All Data Direction Registers
SCI Rate and Mode Control Register
Receive Data Register
Timer Control and Status Register
Free Running Counter
Buffer for LS B of Counter
Port 3 Control and Status Register
Port 2. 3, 4 Data Registers
"If in mode 5, SCl will go active high; otherwise it will remain in the high impedance state.
Vcc
RESET
~-----EXTERNAL ESTART.UPTIME------,.,1!:~:!._ _ _ _ _ _ _ __=~
------J\'r------------~;-----r
~;~:~:;~:~~~~~~~SS~~~~~~~~~~~~~~~SS:2;(====~~~===j~====~~=~:~~===:=~=:==~~====i(~~~r---v~-~--BUS
FFFE
INTER~~ §\\\\\\~\\\\\\\\\\\\W
FFFE
FFFE"
FFFP
NEW PC
~~--------------~
INSTRUCTION
~NOTVALID
• Mode 0 - $BFFE, BFFF
Note: Timing measurements are referenced to and from a low voltage of O.B volts and a high voltage of 2.0 volts, unlesS otherwise noted.
Figure 7. Reset Timing
4·60
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm",,",i_",
10K depending on the drive capability of
the external device.
When the NMI function is implemented,
pin 3 is configured as an input. A negative
edge on pin 3 then requests an IPC non·
maskable interrupt sequence, but the cur·
rent instruction will be completed before
responding to this request. To assure an
interrupt under all conditions, NMI must
be held low for at least one E·Cycle. NMI
can be used to cause the IPC to exit the
wait Instruction. For interrupt timing
speCifications, see Interrupts.
VCC
3-1Dkll
When configured to utilize the HALT/SA
function of this pin, such as after reset,
the circuit of Figure 8 is recommended to
detect and supply continuous HALT and
SA signals. Figure 9 shows the ap·
propriate timing diagram for HALT/SA
with the recommended circuit. Le pullup
resistor shown in the circuit maintains a
high logic level when HALT is not active.
During a positive half·cycle of E, pin 3 is
an input sampled to determine if the halt
state is requested (active low). During the
negative half cycle of E, the SA signal is
output through pin 3. After the request for
halt state signal is detected and the pro·
cessor completes its current instruction,
the CPU is halted and the active low SA
signal is output through pin 3 during the
negative half cycle of E. The local bus is
then available for other devices to utilize
until the halt state signal has returned to a
4
SCN881201
SCN88121
PRE
HALT
D
ClK
Hlili'.,iiAlNMi
Q
ClR
Figure 8. HALT/BA Demultlplexlng Circuit
IN
IN/OUT
----'I
~~--~~--~---,
SA
L . . . -_ _ _
R/W~
ADD/DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
ADD
EXEC_..-----HAlT---_.'
Figure 9. HALT/BA Timing
Signetics
4·61
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'm""n,,-",
high level, thus allowing the IPC back on
the local bus. During the halt state, RIW is
high, and the address bus displays the address of the next instruction.
When single instruction operation Is
desired, in program debug for Instance, it
Is advantageous to single step through Instructions. After BA goes low, HALT must
be brought high for one E-cycle and
returned low again to single step through
instructions. Figure 9 illustrates the tim·
ing involved while stepping through a
single byte, two bus cycle instruction,
such as CLRA.
BA is not output in response to the wait instruction. If interrupts are to be utilized in
removing the processor from a walt state
while in the HALT/BA mode, then IRQ1
and IRQ2 are the only interrupts which
may do so; therefore, their masks must be
cleared before entering the wait state.
Maskable Interrupt Request 1
(IRQ1)
This level-sensitive input can be used to
request an Interrupt sequence. The IPC
will complete the current instruction
before It responds to the request. If the interrupt mask bit (I-bit) in the condition
code register is clear, the IPC will begin an
interrupt sequence: a vector is fetched
from $FFF8 and $FFF9, transferred to the
program counter, and instruction execution is continued at the new location (see
Interrupts). IRQ1 typically requires an external resistor (3K to 10K depending on ex·
ternal device's drive capability) to Vcc for
wire-OR applications. IRQ1 has no internal
pullup resistor.
Strobe Control (SC1 and SC2)
The functions of SC1 and SC2 depend on
the operating mode. SC1 is configured as
an output in all modes except the expanded non-multiplexed mode, whereas
SC2 Is always an output. SC1 and SC2 can
drive one Schottky load and 90pF.
Single Chip Modes-In these modes, SC1
and SC2 are configured as an Input and
output, respectively, and both function as
port 3 control lines. SC1 functions as an
input strobe (IS3) and can be used to indicate that port 3 input data is ready or
output data has been accepted. Three options associated with IS3 are controlled by
the control and status register for port 3
(see Port 3 description).
SC2 is configured as an output strobe
(OS3) and can be used to strobe output
data or acknowledge input data for port 3.
It is controlled by output strobe select
(OSS) in the port 3 control and status
register. The strobe is generated by a read
(OSS = 0) or write (OSS = 1) to the port 3
data register. OS3 timing diagram and the
corresponding electrical speCifications
are contained towards the end of this data
sheet.
Expanded Non-multiplexed Mode-In this
mode, both SC1 and SC2 are configured
as outputs. SC1 functions as input/output
select (lOS) and is asserted (active-low)
only when addresses $0100 through
$01 FF are accessed. SC2 is configured as
R/W and Is used to control the direction of
local data bus transfers. An MPU read is
enabled when R/W and E are high.
Expanded Multiplexed Modes-In these
modes, SC1 is configured as an input and
SC2 is configured as an output. In the expanded multiplexed modes, the IPC has
the ability to access a 64K byte address
space. SC1 functions as an input, address
strobe, which controls demultiplexing and
enabling of the eight least significant addresses and the data buses.
By using a transparent latch such as a
74LS373, address strobe (AS) can also be
used to demultiplex the two buses external to the IPC (see Figure 10). SC2 provides the local data bus control signal called read/write (R/W) and is used to control
GND
AS
I I
EN/G
OC
01
01
PORT 3
ADDRESS/DATA
..
SN7.4LS373
(TYPICAL)
08
ADDRESS: AU-A7
08
DATA: DO-D7
Figure 10. Typical Latch Arrangement
4-62
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'am",,""·',.,
the direction of local data bus transfers.
An MPU read is enabled when R/W and E
are high.
System Bus Interface
Port 1 is a mode-independent 8-bit data
port which permits the external system
bus to access the dual-port RAM and
semaphore registers either asynchronous·
Iy or synchronously with respect to the E
clock. In addition to the eight data lines
(SDO-SD7), eight address (SAO-SA7) and
three control lines (SRIW, CS, DTACK) are
used to access the dual-port RAM and
semaphore registers.
Port 1 Data Lines (SOO·S07)-These data
lines are bidirectional data lines which
allow data transfer between the dual-port
RAM or the semaphore registers, and the
system bus. The data bus output drivers
are three-state devices which remain in
the high-impedance state except during a
read of the IPC dual-port RAM or semaphore registers by the system processor.
System Address Lines (SAO·SA7)-The address lines together with the chip select
signal allow any of the 12B bytes of RAM
or six semaphore registers to be uniquely
selected from the system bus. The address lines must be valid before the CS
signal goes low for the asynchronous in·
terface and valid before the E signal goes
high for the synchronous interface. The
system interface must be deselected be·
tween reads or between writes for the
asynchronous operation.
data acknowledge signal for asynchronous data transfers. As an input, it is
sampled on the falling edge of CS by the
IPC to determine if the system bus is be·
ing accessed synchronously or asyn·
chronously with respect to the E clock. If
DTACK is low when sampled, the system
bus is synchronous and data will be
transferred during E high. If DTACK is
high when sampled, the system bus is
asynchronous. In this mode, DTACK
becomes an output that is asserted low
when data is on the bus during a system
read or when a data transfer is completed
during a system write.
DTACK requires an external pullup
resistor when the system bus is run asynchronously since it is then a bidirectional
handshake line for information transfer on
the system data bus.
Single Chip Modes-In these modes, port
3 is an B-bit I/O port where each line is configured by the port 3 data direction"
register. Associated with port 3 are two
lines, IS3 and OS3, which can be used to
control port 3 data transfers.
Three port 3 options, controlled by the
port 3 control and status register and
available only in the single chip modes
are: port 3 input data can be latched using
IS3 as a control signal; OS3 can be
generated by either an I PC read or write to
the port 3 data register; and an IRQ1 interrupt can be enabled by an IS3 negative
edge. Port 3 timing diagram and corresponding electrical specifications are
contained towards the end of this data
sheet.
Port 3 Control and Status Register
4
$OF
DTACK timing diagrams and corresponding electrical specifications are
contained towards the end of this data
sheet.
Bits 0-2
Bit 3
Port 2 (P20·P24)
Port 2 is a mode independent 5-bit I/O port
where each line is configured by its data
direction register. During reset, all lines
are configured as inputs. The TTL compatible three-state output buffers can
drive one Schottky TTL load and 30pF, or
CMOS devices using external pullup
resistors. P20, P21 and P22 must always
be connected to provide the operating
mode.
Bit 4
Port 2 Data Register
System Read/Write (SRiW)-This signal is
generated by the system bus to control
the direction of data transfer on the data
bus. With the IPC selected, a low on the
SR/W line enables the input buffers, and
data is transferred from the system processor to the IPC. When SR/W is high and
the chip is selected, the data output buffers are turned on and data is transferred
from the IPC to the system bus.
Chip Select (CS)- This signal is a TIL
compatible input signal used to activate
the system bus interface and allows
transfer of data between the IPC and the
system processor during synchronous or
asynchronous accesses. CS provides the
synchronizing signal for the semaphore
registers during access by the system
bus.
Data Transfer Acknowledge (OTACK)This bidirectional control line is used to
determine synchronous or asynchronous
system bus accesses and to provide the
0
76543210
1=1~1~1~lmlrnl~I~la
Inputs on P20, P21 and P22 determine the
operating mode which is latched into the
program counter register on the positive
edge of RESET. The mode can be read
from the port 2 data register (PC2 is
latched from pin 45).
Port 2 also provides an interface for the
serial communications interface and
timer. Bit 1, if configured as an output, is
dedicated to the timer output compare
function and cannot be used to provide
output from the port 2 data register.
Port 3 (P30·P37)
Port 3 can be configured as an I/O port, a
bidirectional B·bit data bus, or a multi·
plexed address/data bus depending on the
operating mode. The TIL compatible
three·state output buffers can drive one
Schottky TIL load and 90pF.
Signetics
Bit 5
Bit 6
Bit 7
Not used
Latch enable-This bit controls
the input latch for port 3. If set,
input data is latched by an IS3
negative edge. The latch is
transparent after a read of the
port 3 data register. Latch
enable is cleared by reset.
OSS (output strobe select)This bit determines whether OS3
will be generated by a read or
write of ;;,e port 3 data register.
When clear, the strobe is
generated by a read; when set, it
is generated by a write. OSS is
cleared by reset.
Not used
IS3-IRQ1 enable-When set, an
IRQ1 interrupt will be enabled
whenever IS3 flag is set; when
clear, the interrupt is inhibited.
This bit is cleared by reset.
IS3 flag-This read-only status
bit is set by an IS3 negative
edge. It is cleared by a read of
the port 3 control and status
register (with IS3 flag set) followed by a read or write to port 3
data register or by reset.
Expanded Non·Multiplexed Mode-In this
mode, port 3 is configured as a bidirectional data bus (DO·D7). The direction
of data transfers is controlled by R/W
(SC2). Data transfers are clocked by E
(enable).
Expanded Multiplexed Modes-In these
modes, port 3 is configured as a timemultiplexed address (AO-A7) and data bus
4·63
4
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'ptE1"..IIeI.i'l
(DO-D7). Address strobe (AS) must be Input
on SC1, and can be used externally to
demultiplex the two buses. Port 3 Is held
in a high-impedance state between valid
address and data to prevent potential bus
conflicts.
Port 4 (P40·P47)
Port 4 is configured as an 8-bit I/O port, as
address outputs, or as data inputs
depending on the operating mode. Port 4
can drive one Schottky TIL load and 90pF
and is the only port with internal pullup
resistors.
Single Chip Modes-In these modes, port
4 functions as an 8-bit I/O port where each
line is configured by the port 4 data direction register. Internal pullup resistors
allow the port to directly interface with
CMOS at 5 volt levels. External pullup
resistors to more than 5 volts, however,
cannot be used.
Expanded Non-Multiplexed Mode-In this
mode, port 4 is configured from reset as
an 8-bit input port, where the data direction register can be written to provide any
or all of address lines AO-A7. Internal
pullup resistors are intended to pull the
lines high until the data direction register
is configured.
Expanded Multiplexed Mode-In all of
these modes, except mode 6, port 4 functions as half of the address bus and provides A8 to A 15. In mode 6, the port Is configured from reset as an 8-blt parallel input
port; the port 4 data direction register
must be written to provide any or all of address lines A8 to A15. Internal pullup
resistors are intended to pull the lines
high until the data direction register is
configured (bit 0 controls A8, etc.)
Signal Summary
Table 6 is a summary of all the signals
discussed in the previous paragraphs.
OPERATING MODES
The IPC provides eight different operating
modes which are selectable by hardware
programming and referred to as modes 0
through 7. The operating mode controls
the memory map, configuration of port 3,
port 4, SC1 and SC2, and the address location of the Interrupt vectors.
Table 6. SIGNAL SUMMARY
Signal Name
System Address Bus
System Data Bus
System Read/Write
Chip Select
Data Transfer
Acknowledge
Strobe Control #1
Strobe Control #2
Enable
Reset
Interrupt Request 1
Halt, Bus Available,
Non-maskable Interrupt
I/O Port 2
I/O Port 3
I/O Port 4
Ground
Power Input
Mnemonic
Input/Output
Active State
Three State
SAO-SA7
SDO-SD7
SR/W
input/output
input/output
input
no
yes
CS
DTACK
input
Input/output
high
high
read-high
write-low
low
low
SC1
SC2
E
RESET
IRQ1
output
Input
Input
input
input
high
high
high
low
low
yes
HALT/BA/NMI
P20-P24
P30-P37
P40-P47
Vss
Vee
input/output
input/output
input/output
input/output
Input
Input
low
high
high
high
yes
yes
yes
yes
and expanded multiplexed. Single chip includes modes 4 and 7, expanded nonmultiplexed is mode 5 and the remaining
five are expanded multiplexed modes. A
system utilizing three SC68120's, one in
each of the fundamental operating modes,
Is shown In Figure 11. Table 7 summarizes
the characteristics of the operating
modes.
Single Chip Modes (4, 7)-ln single chip
mode, three of the four IPC ports are configured as parallel Input/output data ports,
as shown in Figure 12. The IPC functions
as a complete microcomputer in these two
modes without external address or data
buses. A maximum of 21 I/O lines and two
port 3 control lines are provided.
In single chip test mode (4), the RAM
responds to addresses $XX80 (X = don't
care) through $XXFF and the ROM is
removed from the internal address map. A
test program must first be loaded into
RAM using modes 0,1,2, or6. If the IPC is
reset and then programmed into mode 4,
execution will begin at $XXFE:XXFF.
Mode 5 can be irreversibly entered from
mode 4 without going through reset by
setting bit 5 of the port 2 data register.
This mode Is used primarily to test port 3
and 4 In the single chip and nonmultiplexed modes.
Fundamental Modes
The eight modes of the IPC can be
grouped Into three fundamental modes
which refer to the type of bus it supports:
single chip, expanded non-multiplexed,
4·64
Expanded Non-Multiplexed Mode (5)-A
modest amount of external memory space
is provided in the expanded nonmultiplexed mode while retaining slgnifi-
Signetics
-
-
yes
-
-
cant on-chip resources. Port 3 functions
as an 8-bit bi-dlrectional data bus and port
4 is configured as an input data port. Any
combination of AO to A7 can be provided
while retaining the remainder as input
data lines. Any combination of the eight
least-significant address lines can be obtained by writing to the port 4 data direction register. Internal pullup resistors are
provided to pull port 4 lines high until it is
configured.
Figure 13 illustrates the external resources available in the expanded nonmultiplexed mode. The IPC interfaces
directly with the Motorola M6800 family
parts (or parts with equivalent interfaces)
and can access 256 bytes of external address space at $100 through $1 FF. lOS
provides an address decode of external
memory ($100-$1 FF) and can be used as
an address or chip select line.
Expanded Multiplexed Modes (0, 1, 2, 3,
6)-ln the expanded multiplexed modes,
the IPC has the ability to access a
64K-byte memory space. Port 3 functions
as a time-multiplexed address/data bus
with the address valid on the negative
edge of address strobe (AS) and the data
bus valid while E is high. In modes 0 to 3,
port 4 provides address lines A8-A15.
However, in mode 6, port 4 can provide any
subset of A8 to A15 while retaining the remainder as Input lines. Writing 1's to the
desired bits In the data direction register
(DDR) will output the corresponding address lines while the remaining bits will remain inputs (as configured from reset or
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm"",u!.iii
SCN66000, M6S000, OR
MICROPROCESSOR
WITH EQUIVALENT
SYNCHRONOUS
INTERFACE
RAM
4
SINGLE CHIP MODE
ROM
EXPANDED
NON·MULTIPLEXED
MODE
SYSTEM BUS
EXPANDED
MULTIPLEXED
MODE
ROM
LOCAL
BUS
'"fa0:
C
c
c
c
~
RAM
PERIPHERALS
Figure 11. IPC Fundamental Operating Modes
Signetics
4·65
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""''''·''t
Table 7" SUMMARY OF IPC OPERATING MODES
Common to all Modes:
System Bus Interface
Reserved Register Area
6 Semaphore Registers
I/O Port 2
Programmable Timer
Serial Communications Interface
128 bytes of Dual Ported RAM
Single Chip Mode"
2048 Bytes of ROM (Internal)
Port 3 is a Parallel I/O Port with Two Control Lines
Port 4 is a Parallel I/O Port
SCl is Input Strobe 3 (IS3)
SC2 is Output Strobe 3 (OS3)
Expanded Non-Multiplexed Mode"
2048 Bytes of ROM (lnternaJ)
256 Bytes of External Memory Space
Port 3 is an 8-Bit Data Bus
Port 4 is an Address Bus
SCl is Input/Output Select (lOS)
SC2 is Read/Write (A/W)
Expanded Multiplexed Modes
Four Memory Space Options (64K Address Space):
(1) MOOS Compatible
(2) No ROM
(3) External Vector Space
(4) ROM with Partial Address Bus"
External Memory Space Accessed Through:
Port 3 as a Multiplexed Address/ Data Bus
Port 4 as an Address Bus (High)
SCl is Address Strobe Bus (AS) Input
SC2 is Read/Write (R/W)
Test Modes
Expanded Multiplexed Test Mode
May be Used to Test RAM and ROM"
Single Chip and Non-Multiplexed Test Mode"
May be Used to Test Ports 3 and 4 as I/O Ports
"SCN68120 only
Vcc
RESET
SCN68120
Hrn/BAliiiMi
IRQ1
PORT3
81/0 LINES
8 SYSTEM
ADDRESS LINES
PORT1
8 SYSTEM
DATA LINES
iSs
SRm
OS3
CS
iifA'Ci(
PORT4
81/0 LINES
PORT 2
5110 LINES
SERIAL 1/0,
16·BIT TIMER
-
VSS
Figure 12. Single Chip Mode
4"66
Signetics
SYSTEM
BUS
JANUARY 1983
MICROPROCESSOR DIVISION
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'pmn"iiel.'4'
vcc
E
RESET
SCN68120
HArf/BAlJiIW
iiml
8 SYSTEM
ADDRESS LINES
PORT3
8 DATA LINES
PORT 1
8 SYSTEM
DATA LINES
Rm
4
SYSTEM
BUS
sRiW
105
CI"
PORT 4
8 ADDRESS LINES
DTACK
PORT2
51/0 LINES
SERIAL I/O,
18·BIT TIMER
vss
Figure 13. Expanded Non·Multiplexed Mode
from O's written to the OOR). Internal
pullup resistors are provided to pull port 4
lines high until software configures the
port. Initialization of port 4 in mode 6 must
be done to obtain any upper address lines
externally.
Figure 14 depicts the external resources
available in the expanded multiplexed
modes. Address strobe can be used to
control a transparent O·type latch to cap·
ture addresses AO·A?, as shown in figure
10. This allows port 3 to function as a data
bus when E is high.
I n mode 0, the reset vector is external at
$BFFE and $BFFF after the positive edge
of RESET. In addition, the internal and ex·
ternal data buses are connected together
so there must be no memory map overlap
(to avoid potential bus conflicts). Mode 0
is used primarily to verify the ROM pattern
and monitor the internal data bus with
automated test equipment.
MODE PROGRAMMING
The operating mode is programmed by the
levels asserted on P22, P21, and P20 duro
ing the positive edge of RESET. These are
latched into PC2, PC1, and PCO of the pro·
gram control register. The operating mode
can be read from the port 2 data register
and programming levels and timing must
be met as shown in Figure 15 and Table 8.
A brief outline of the operating modes in
shown in Table 9.
Circuitry to provide the programming
levels is primarily dependent on the nor·
mal system use of the three pins. If con·
figured as outputs, the circuit shown in
Figure 16 can be used; otherwise, three·
state buffers can be used to provide isola·
tion while programming the mode.
INTERRUPTS
The IPC supports two types of interrupt reo
quests: maskable and non·maskable. A
non·maskable interrupt (NMI) is always
recognized and acted upon at the comple·
tion of the current instruction. Maskable
interrupts are controlled by the condition
code register I·bit and by individual enable
bits. The I·bit controls all maskable inter·
rupts. Of the maskable interrupts, there
are two types: IRQl and IRQ2. The pro·
grammable timer and serial communica·
tions interface use an Internal IRQ2 inter·
rupt line, as shown in the block diagram of
the I PC. External devices (and 153) use
IRQ1. An IRQ1 interrupt is serviced before
an IRQ2 interrupt if both are pending.
MEMORY MAPS
The IPC provides up to 64K bytes of ad·
dress space depending on the operating
mode. A memory map for each operating
mode is shown in Figure 17. In modes lR
and 6R, the R means the ROM has been
relocated by a mask option. The first 32
locations of each map are reserved for the
IPC internal register area, as shown In
Table 10, with exceptions as indicated.
Signetics
All IRQ2 interrupts use hardware priori·
tized vectors. The single SCI interrupt and
three timer interrupts are serviced in a
prioritized order where each is vectored to
a separate location. All IPC vector loca·
tions are shown In Table 11, from highest
(top) to lowest (bottom) priority.
4·67
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'up"""".'"
Vee
~---- E
SCN881201
SCN68121
PORT 3
8 LINES MULTIPLEXED
ADDRESS/DATA
' - - - - - , 8 SYSTEM
ADDRESS LINES
PORT 1
8 SYSTEM
DATA LINES
RIW 4 - - - - - 1
AS
14-----
----41"'1
SR/W
14----~
PORT4
8 ADDRESS LINES
t - - - - - I - 15TACR'
PORT2
5 UO LINES
SERIAL 110,
18·BIT TIMER
VSS
Figure 14. Expanded Multiplexed Mode
Figure 15. Mode Programming Timing
4·68
Signefics
SYSTEM
BUS
MICROPROCESSOR DIVISION
JANUARY 1963
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""n".."
Table 8. MODE PROGRAMMING SPECIFICATIONS
(See Figure 15)
Characteristic
Unit
Symbol
Min
Typ
Max
Mode Programming Input Voltage Low
VMPL
-
-
Mode Programming Input Voltage High
VMPH
4.0
-
1.B
-
Mode Programming Diode Differential lif Diodes are Used)
VMPDD
0.6
RESET Low Pulse Width
PWRSTL
3.0
-
E-Cycles
Mode Programming Setup Time
tMPS
2.0
-
-
E-Cycles
Mode Programming Hold Time
REm Rise Time 2: 1 p,s
RESET Rise Time< 1 P.s
tMPH
0
100
-
-
ns
V
V
V
-
4
Table 9. MODE SELECT SUMMARY
Mode
Pin 45
P22
PC2
Pin 44
P2l
PCl
Pin 43
P20
PCO
ROM
7
H
H
H
6
H
H
L
Operating
Mode
RAM
Interrupt
Vectors
Bus
Mode
I
I
I
I
I
I
I
MUXI5,6)
Single Chip
Multiplexed/Partial Decode (5 )
Non-Multiplexed/ Partial Decode (5 )
5
H
L
H
L
L
I
111)
NMUXI5,6)
H
I
1(2 )
I
4
I
3
L
H
H
E
1(7 )
E
I
MUX(4)
Single Chip Test
Multiplexed/ RAM (4)
2
L
H
L
E
I
E
MUX(4)
M ultiplexed/ RAM 141
1
L
L
H
I
I
MUX(4)
0
L
L
L
I
I
E
E(3)
Multiplexed/RAM and ROM(4)
Multiplexed Test (4 )
Legend:
I - Internal
E - External
MUX - Multiplexed
NMUX - Non-Multiplexed
L - Logic "0"
H - Logic "1"
MUX(4)
Notes:
(1) Internal RAM is addressed at $XXBO
(2) Internal ROM is disabled
(3) Interrupt vectors externally located at $BFFO-$BFFF
(4) Addresses associated with Ports 3 and 4 are considered external in Modes 0, 1, 2, and 3
(5) Addresses associated with Port 3 are considered external in Modes 5 and 6
(6) Port 4 default is user data input; address output is optional by writing to Port 4 Data Direction Register
(7) Internal RAM and registers located at $COXX Ifor use with MDOS)
Table 10. INTERNAL REGISTER AREA
Register
Address****
I Hexadecimal)
Reserved
Port 2 Data Direction Register···
Reserved
Port 2 Data Register
00
01
02
03
Port
Port
Port
Port
05··
06·
Or"
3
4
3
4
Data
Data
Data
Data
Direction Register···
Direction Register···
Register
Register
Register
SCI Rate and Mode Control Register
Transmit/Receive Control and Status Register
SCI Receive Data Register
SCI Transmit Data Register
Address****
( Hexadecimal)
10
11
12
13
04·
Timer Control and Status Register
Counter (High Byte)
Counter (Low Byte)
Output Compare Register (High Byte)
OB
09
OA
DB
Output Compare Register I Low Byte)
Input Capture Register (High Byte)
Input Capture Register (Low Byte)
Port 3 Control and Status Register
OC
OD
OE
OF·
Function Control Register
Counter Alternate Address I High Byte)
Counter Alternate Address (Low Byte)
Semaphore 1
Semaphore 2
Semaphore 3
Semaphore 4
Semaphore 5
Semaphore 6
Reserved
"These external addresses in Modes 0, 1, 2, 3, 5, 6 cannot be accessed in Mode 5 (no lOS),
""These are external addresses in Modes 0, 1, 2, 3.
Signetics
14
15
16
17
18
19
lA
lB
lC
1D-1F
"·"1 = Output, 0= Input
"". "These addresses relocated at $COOO-$COl F in Mode 3.
4·69
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm",,""···,
vcc
R2
REsET
P20
R1
R1
SCN681201
SCN68121
R1
r--'
48
I
43'
I
I
44
P21
P22
I
L __
I
45
J
Rffi'f
P20(PCO)
P21(PC1)
P22(PC2)
OPTIONAL
THREE·STATE
BUFFERS
MODE
CONTROL
SWITCHES
Notes:
1. Mode 7 as shown
2. R2-C =Reset time constant
D
3, R1 = 10k (typical)
4, D= 1N914, 1N4001 (typical)
C
I
Figure 16. Typical Mode Programming Circuit
The interrupt flowchart is shown in Figure
18. The program counter, index register,
accumulator A, accumulator B, and condi·
tion code register are pushed to the stack.
The I·bit is set to inhibit maskable interrupts and a vector is fetched corrresponding to the current highest priority interrupt. The vector is transferred to the program counter and instruction execution is
resumed. The general interrupt timing sequence is shown in Figure 19. The interrupt HALT/BA timing Is illustrated in
Figures 8 and 9.
PROGRAMMABLE TIMER
Timer Control and
Status Register (S08)
The timer control and status register
(TCSR) is an B-bit register of which all bits
are readable, while bits 0-4 can be written.
The three most significant bits provide the
timer status and indicate that a proper
level transition has been detected, or that
a match has been found between the freerunning counter and the output compare
register, or that the free-running counter
has overflowed.
Each of the three events can generate an
IRQ2 interrupt and is controlled by an individual enable bit in the TCSR.
Table 11. MCU VECTOR LOCATIONS*
MSB
LSB
$FFFE
FFFF
RESET"·
Interrupt
NMI
FFFC
FFFD
FFFA
FFFB
Software Interrupt (SWIl
FFFB
FFF9
IRQ1 lor 153)
FFF6
FFF7
ICF (Input Capture)
FFF4
FFF5
OCF (Output Compare)
FFF2
FFF3
TOF ITimer Overflow)
FFFO
FFF1
SCI IRDRF+ ORFE+ TDRE)
The programmable timer can be used to
perform input waveform measurements
while independently generating an output
waveform, Pulse widths can vary from
several microseconds to many seconds. A
block diagram of the timer is shown in
Figure 20.
"These locations are relocated at $BFFO-$BFFF In Mode 0,
""Highest priority,
4·70
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
':Ri1nllll.i.iN
o
SCN68120
MODE
MULTIPLEXED TEST MODE
INTERNAL REGISTERS
SOOIF
EXTERNAL MEMORY SPACE
NOTES
$0080
1. Excludes the following addresses which may be used exter·
nally: $04, $05, $06, $07 and $OF.
INTERNAL RAM
2. The interrupt vectors are externally located at SBFFO$BFFF.
SOOFF
EXTERNAL MEMORY SPACE
$BFFO
EXTERNAL INTERRUPT VECTORS(2)
3. There must be no overlapping of internal and external memory spaces to avoid driving the data bus with more than one
device.
4. This mode is the only mode which may be used to examine
the Interrupt vectors in internal ROM using an external
RESET vector.
4
S. SCN68120 only.
SBFFF
EXTERNAL MEMORY SPACE
$F800
INTERNAL ROM(5)
SCN68120
MODE
SCN68120
MODE
1
MULTIPLEXED/RAM AND ROM
MULTIPLEXED/RAM AND ROM
$0000
$0000
INTERNAL REGISTERS(I)
INTERNAL REGISTERS(I)
$OOIF
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
$0080
S0080
INTERNAL RAM
$OOFF
~"""'''-''-'II
INTERNAL RAM
<
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
$X800
$F800
INTERNAL ROM(2)
b-.,...,,...,...,.....-II ~
SXFFF
INTERNAL ROM
:~~~~ ~""'..L."'-'I
SFFFF ....._ _ _- - '
I-'-"~'-"~I<
EXTERNAL MEMORY SPACE
EXTERNAL INTERRUPT VECTORS(2)
EXTERNAL INTERRUPT VECTORS
$FFFF ....._ _ _- - '
NOTES
NOTES
1. Excludes the following addresses which may be used exter-
1. Excludes the following addresses which may be used externally: $04, SOS, $06, $07 and SOF.
nally: $04, $05, $06, $07 and $OF.
2. Internal ROM addresses $FFFO to $FFFF are not usable.
2. Starting addresses for the internal ROM may be $C800,
$0800 or $E800 as a mask option.
Figure 17. IPC Memory Maps
Signetics
4·71
JANUARY 1983
MICROPROCESSOR DIVISION
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""n"·'i'
MULTIPLEXED/RAM
SCN681201
SCN68121
MODE
2
MULTIPLEXED/RAM, MDOS COMPATIBLE(I)
SCN68120/
SCN68121
MODE
$0000 . - - - - - . ....
3
,.,..~,..,....,..,."
SoooO
INTERNAL REGISTERS(I)
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
INTERNAL RAM
SCOOO
r,...,'"7"7"'7't(
INTERNAL REGISTERS(2)
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
INTERNAL RAM
EXTERNAL MEMORY SPACE
EXTERNAL INTERRUPT VECTORS
SFFFO
t-----t
EXTERNAL INTERRUPT VECTORS
NOTES
SFFFF ....- - -...
NOTES
1. Excludes the following addresses which may be used externally: $04, $05, $06,
$07 and $OF.
SCN68120
MODE
1. Relocating the Internal registers and the internal RAM to high memory allows
processor to run MOOS.
2. Excludes the following addresses which may be used externally: $COO4, $Caa5,
SCOO6, SCOO7 and $COOF.
4
SCN68120
MODE
SINGLE CHIP TES,.(2)
$0000(1)
rrr::M""'7''''\' INTERNAL REClISTERS(5)
$0000
$OOIF ~-,,.,,-....
5
NON.MULTIPLEXED/PARTIAL DECODE(2K3)
.001F
W"~
$0080
~UNUSABLE
f
}
INTERNAL REGISTERS
}
INTERNAL RAM
$OOFF
.0100
EXTERNAL MEMORY SPACE
$OlFF
UNUSABLe'IK4)
UNUSABLE
'FBOO
SXX80(3)
'-""""'"7"'7'1
V-~~"7"'7'I} INTERNAL RAM(4)
,XXFF
INTERNAL INTERRUPT VECTORS
NOTES
1. The internal ROM Is disabled.
2. Mode 4 may be changed to Mode 5 without having to assert RESET by writing a
"I" into bit 5 (PCO) of Port 2 Oata Register.
3. Addresses AS to A15 are treated as "don't cares" to decode internal RAM.
4. Intornal RAM will appoar at $XX80 to $XXFF.
5. MPU read of Port 3 Data Direction Register will access Port 3 Data Register
Instead.
NOTES
1. Excludes the following addresses which may not be used externally: $04, $06
and $OF (no lOS).
2. This mode may be entered without going through Reset by using Mode·4 and
subsequently writing a "1" into bit 5 (PCO) of Port 2 Data Register.
3. Address lines AD to A7 will not contain addresses until the Data Direction Register for Port 4 has been written with "1"8 in the appropriate bits. These address
lines will assert "1"s until made outputs by writing the Data Direction Register.
Figure 17. IPC Memory Maps (Continued)
4·72
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'W""Juie'd
SCN68120
MODE
6
SCN68120
MODE
MULTIPLEXED/PARTIAL DECODE
MULTIPLEXED/PARTIAL DECODE
INTERNAL REGISTERS(1X2)
INTERNAL REGISTERS(1X2)
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
INTERNAL RAM
INTERNAL ROM(3)
4
EXTERNAL MEMORY SPACE
EXTERNAL MEMORY SPACE
INTERNAL ROM(3)
<
$XFFF
f-'o...L"':"'''''-'''-''4
$FFFO
I------H
EXTERNAL MEMORY SPACE
INTERNAL ROM
EXTERNAL INTERRUPT VECTORS
INTERNAL INTERRUPT VECTORS
NOTES
NOTES
1. Excludes the following addresses which may be used externally: $04, $06, $OF.
2. Address lines A8-A15 will not contain addresses until the Data Direction Aegister for Port 4 has been written with "1"5 in the appropriate bits. These address
lines will assert "l"s until made outputs by writing the Data Direction Register.
SCN68120
MODE
1. Excludes the following addresses which may be used externally: $04, $06, $OF.
2. Address lines A8-A15 will not contain addresses until the Data Direction Regis·
ter for Port 4 has been written with "1 "5 in the appropriate bits. These address
lines will assert "l"s until made outputs by writing the Data Direction Register.
3. Starting addresses for the internal ROM may be $CBOO, $DBOO or $EBOO.
7
SINGLE CHIP
$0000
$001F~~
}
INTERNAL REGISTERS(1)
UNUSABLE
$0080~}
~"
1
INTERNAL RAM
NOTES
1. MPU reads of Port 3's Data Direction Register will access
Port 3's Data Register Instead.
UNUSABLE
$FFFF "-"""'''"'''''........
Figure 17. IPC Memory Maps (Continued)
Signetics
4·73
i"
~
I
z
~
m
'$:
o
e3
~
z 8
o
rr-
G>
m
~
"V
m
!!!!
m
;;v
<:
!1i
oz
"V
::l:
m
:;0
:!!
»
ro
oz
c
:;0
~
CI
S0-
l'"
-
or-
sa
o·
en
CD
:;0
Gl
cg
r-
:;
m
2
'9.
"T1
~
..
n
~
:1
SCI = TILTDRI + RIE_IRDRF + ORFE)
en
VECTOR _
MODE 0
PC
MODES.-7
NMI
BFFC-BFFD FFFC-FFFD
Z
0NON-MASKABLE INTERRUPT
SWI
BFFA-BFFB
FFFA-FFFB SOFTWARE INTERRUPT
IRQ.
BFF8-BFF9
FFF8-FFF9
MASKABLE INTERRUPT REQUEST'
ICF
BFF6-BFF7
FFF6-FFF7
INPUT CAPTURE INTERRUPT
OCF
OUTPUT COMPARE INTERRUPT
BFF4-BFF5
FFF4-FFF5
TOF
BFF2-BFF3
FFF2-FFF3
TIMER OVERFLOW INTERRUPT
SCI
BFFO-BFF.
FFFO-FFF'
SCI INTERRUPT (TDRE + RDRF + ORFE)
A
0
C»
..a.
N
C
en
0
Z
0-
C»
N
..a.
..a.
'»
Z
c:
»
;;v
-<
<;
co
w
JANUARY 1983
MICROPROCESSOR DIVISION
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/$CN68121
'm""n"_.,,
I CYCLE
N1
LAST INSTRUCTlON--!
I
N2
OP CODe OP CODE
ADDR
ADDA + 1
SPin)
SPIn 1)
"
'6
"
'8
'0
",0
SP(n.2)
SP(n·3)
SP(n·4)
SP(n·5)
SP(n·6)
SP(n.])
."
'12
VECTOR
VECTOR
NEW PC
MSB ADDR LSB AD DR ADDRESS
\~~-----------------------------------------------------------'PCS
-----1 I--
FIRST INST OF
INTERRUPT ROUTINE
INTERNAL------~r---~,---~,r_----,,----;J----~r_--~~----~----_v----~r_----v_----~r_----v_----"----~I
DATABUS-------r~---J~O-P-C-O-D-E~O-P-C-O-DJE~P-C-O.-7J\-P-C-8.-.5-'·~X-O-.-7~-X-8-.-.5-'·~A-C-C-AJ'--A-C-C-BJ\--C-C-R-''~,R-RE-L-EV-A-NJT'-V-EC-T-O-R'~----~-----'·,
_ _____- - - - - - - - - - - - - - - - - - - -__ + 1
INTERNAL R/W
\~---------------------------'I
DATA
MSB
Figure 19. Interrupt Sequence
SCN681201SCN68121 INTERNAL BUS
a
b7
OUTPUT
LEVEL
REGISTER
TIMER
CONTROL
AND
STATUS
REGISTER
BITI
PORT 2
OOR
$08
OUTPUT COMPARE PULSE
_ _ _ _'
OUTPUT INPUT
LEVEL EDGE
BIT 1
BIT 0
PORT 2 PORT 2
Figure 20. Programmable Timer-Block Diagram
Signetics
4·75
4
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
'm""""··,,
Timer Control and Status Register (TSCR)
7654321,.
IICF I OCF I TOF I EICII EOCII ETOIIIEDGI )lVI I $08
OLVL
IEDG
ETOI
Output level-OLVL is clocked to
the output level register by a suc·
cessful output compare and will
appear at P21 if bit 1 of the port 2
data direction register is set. It is
cleared by reset.
Input edge-IEDG is cleared by
reset and controls which level
transition will trigger a counter
transfer to the input capture
register:
IEDG = 0 transfer on a negative
edge
IEDG = 1 transfer on a positive
edge
Enable timer overflow interruptWhen set, an IRQ2 interrupt is
enabled for a timer overflow; when
clear, the interrupt is inhibited. It
is cleared by reset.
EOCI
Enable output compare interrupt-When set, an IRQ2 interrupt
is enabled for an output compare;
when clear, the interrupt is inhibited. It is cleared by reset.
EICI
Enable input capture interruptWhen set, an IRQ2 interrupt is
enabled for an input capture;
when clear, the interrupt is in·
hibited. It is cleared by reset.
TOF
OCF
ICF
4·76
Timer overflow flag- TOF is set
when the counter contains all 1'so
It is cleared by reading the TCSR
(with TOF set) followed by reading
the highest byte of the counter
($09), or by reset. Reading the
counter at $15 will not clear TOF.
Output compare flag-OCF is set
when the output compare register
matches the free·running counter.
It is cleared by reading the TCSR
(with OCF set) and then writing to
the output compare register ($OB
or $OC), or by reset.
Input capture flag-ICF is set to
indicate a proper level transition.
It is cleared by reading the TCSR
(with ICF set) and then reading the
input capture register high byte
($OD), or by reset.
Counter (S09:0A)
The key timer element is a 16-bit free·
running counter which is incremented by
E (enable). It is cleared during reset and is
a read·only with one exception: a write to
the counter ($Og) will preset it to $FFF8.
This feature, intended for testing, can
disturb serial operations because the
counter provides the SCI internal bit rate
clock. TOF is set whenever the counter
contains all 1'so The counter can also be
read at locations $15 and $16 to avoid the
clearing of the TOF.
Output Compare Register
(SOB:OC)
The output compare register is a 16-bit
read/write register to control an output
waveform or provide an arbitrary timeout
flag. It is compared with the free-running
counter on each E·cycle. When a match is
found, OCF is set and OLVL is clocked to
an output level register. If port 2, bit 1 is
configured as an output, OLVL will appear
at P21. The output compare register and
OLVL can then be changed for the next
compare. The compare function is in·
hibited for one cycle after a write to the
high byte of the counter ($OB) to ensure a
valid compare. The output compare
register is set to $FFFF by reset.
Input Capture Register (SOD:OE)
The input capture register is a 16·bit read·
only register used to store the freerunning counter when a 'proper' input
transition occurs as defined by IEDG. Port
2, bit 0 should always be configured as an
input, but the edge detect circuit always
senses P20, even when configured as an
output. An input capture can occur independently of ICF: the input capture
register always contains the most current
value regardless of whether ICF was
previously set or not. Counter transfer is
inhibited, however, between accesses of a
double byte IPC read. The input pulse
width must be at least two E-cycles to ensure an input capture under all conditions.
SERIAL COMMUNICATIONS
INTERFACE
A full-duplex asynchronous serial communications interface (SCI) is provided
with two data formats and a choice of
baud rates. The SCI transmitter and
receiver are functionally independent, .but
use the same data format and bit rate.
Serial data formats include standard
Signetics
SCN68120/SCN68121
mark/space (NRZ) and bi-phase. Both formats provide one start bit, eight data bits,
and one stop bit. Baud and bit rate are
used synonymously in the following
description.
Wake· Up Feature
In a typical serial loop multiprocessor configuration, the software protocol will
usually identify the addressee(s) at the
beginning of the message. In order to
allow uninterested MPUs to ignore the remainder of the message, a wake-up feature is included whereby all further SCI
receiver flag (and interrupt) processing
can be inhibited until the data line goes
idle. An SCI receiver is reenabled by an
idle string of ten consecutive 1's or by
reset. Software must provide the required
idle string between consecutive messages and prevent it within messages.
Programmable Options
The following features of the SCI are pro·
grammble:
- Format: standard mark/space (NRZ) or
bi-phase
- Clock: External or internal clock source
- Baud rate: One of four per E-clock frequency or one-eighth of the external
clock input to P22
- Wake-up features: enabled or disabled
- Interrupt requests: enabled individually
for transmitter and receiver
- Clock output: internal bit rate clock
enabled or disabled to P22
Serial Communications Registers
The SCI includes four addressable registers as depicted in Figure 21. It is con·
trolled by the rate and mode control
register and the transmit/receive control
and status register. Data is transmitted
and received utilizing a write-only transmit
register and read-only receive register.
The shift registers are not accessible by
software.
Rate and Mode Control Register ($10)The rate and mode control register
(RMCR) controls the SCI baud rate, format, clock source, and under certain conditions, the configuration of P22. The
register consists of four write-only bits
which are cleared by reset. The two least
signficant bits control the baud rate of the
internal clock and the remaining two bits
control the format and clock source.
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'mU';""."j
BIT 7
RATE AND MODE CONTROL REGISTER
BIT 0
I I I I I
CCI
CCO
SSI
sso
SID
TRANSMIT/RECEIVE CONTROL AND STATUS REGISTER
I I I I I I
RDRF
ORFE
TDRE
RIE
RE
TIE
I I
TE
WU
$11
RECEIVE DATA REGISTER
S12
PORTa
4
(NOT ADDRESSABLE)
RECEIVE SHIFT REGISTER
45
!4----E
(NOT ADDRESSABLE)
TRANSMIT SHIFT REGISTER
47
TRANSMIT DATA REGISTER
Figure 21. SCI Registers
Table 12. SCI BIT TIMES AND RATES
SSl:SS0
E
614.4 kHz
1.0 MHz
1.2288 MHz
0 0
+16
161'5/62,500 Baud
13.01'5/76,800 Baud
0 1
+ 128
26 1'5/38.400 Baud
208 1'5/4,800 Baud
1 0
+
1024
1.67 ms/600 Baud
1 1
+4096
6.67ms/150 Baud
1281'5/7812.5 Baud
104.2 1'5/9,600 Baud
1.024 ms/976.6 Baud
4.096 ms/244.1 Baud
833.31'5/1,200 Baud
3.33 ms/300 Baud
Table 13. SCI FORMAT AND CLOCK SOURCE CONTROL
CC1:CCO
Format
Clock
Source
Port 2
Bit 2
0 0
Bi-Phase
Internal
Not Used
0 1
NRZ
Internal
Not Used
1 0
NRZ
Internal
Output
1 1
NRZ
External
Input
Signetics
4·77
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""'''t·'ii
Rate and Mode Control Register (RMCR)
I
76543210
x
x
x
x CCl cco 551 sse
I
I
I
I
I
I
I
I $10
SS1:SS0
Speed Select-These two bits
select the baud rate when using the internal clock. Four
rates may ,be selected which
are a function of the IPC input
frequency (E). Table 12 lists bit
times and rates for three
selected IPC frequencies.
CC1:CCO Clock control and format
select-These two bits control
the format and select the serial
clock source. If CC1 is set, the
data direction register (DDR)
value for P22 is forced to the
complement of CCO and cannot
be altered until CC1 Is cleared.
If CC1 is cleared after having
been set, itsOOR value is unchanged. Table 13 defines the
format, clock source, and the
use of P22.
If both CC1 and CCO are set, an external
TTL compatible clock must be connected
to P22 at eight times (8X) the desired baud
rate, but not greater than E, with a duty cycle of 50% (± 10%). If CC1:CCO= 10, the
internal baud rate clock Is provided at P22
regardless of the values for TE or RE.
NOTE:
The source of the SCI internal baud rate
clock is the free-running counter of the
timer. An IPC write to the counter can
disturb serial operations.
Transmit/Receive Control and Status
Register ($11)-The transmit/receive control and status register (TRCSRj controls
the transmitter, receiver, wake-up
features, and two Individual interrupts and
monitors the status of serial operations.
All eight bits are readable while only bits 0
to 4 are writable. The register is initialized
to $20 by reset.
Transmit/Receive Control and Status
Register (TRCSR)
76543210
IRDRFloRFE ITDREI
WU
4·78
RIE I RE I TIE I
TE
I wu I $11
'Wake-up' on the idle line-When
set, WU enables the wake-up
function; it is cleared by ten consecutive 1's or by reset. WU will
not set if the line is idle.
TE
Transmit enable-When set, the
P24 OOR bit is set, cannot be
changed, and will remain set If TE
is subsequently cleared. When TE
is changed from clear to set, the
transmitter is connected to P24
and a preamble of nine consecutive 1's is transmitted. TE is
cleared by reset.
TIE
Transmit interrupt enable-When
set, an IRQ2 interrupt is enabled
when TORE is set; when clear, the
interrupt Is Inhibited. TIE is
cleared by reset.
RE
Receive enable-When set, the
P23 OOR bit is cleared, cannot be
changed, and will remain clear If
RE is subsequently cleared. While
RE is set, the SCI receiver is
enabled. RE is cleared by reset.
RIE
Receiver interrupt enable-When
set, an IRQ2 interrupt is enabled
when RORF and/or OR FE is set;
when clear, the interrupt is inhibited. RIE is cleared by reset.
TORE Transmit data register emptyTORE is set when the contents of
the transmit data register is
transferred to the output serial
shift register or by reset. It is
cleared by reading the TRCSR
(with TORE set) and then writing
to the transmit data register. Additional data will be transmitted
only if TORE has been cleared.
ORFE Overrun framing error-If set,
OR FE indicates either an overrun
or framing error. An overrun occurs when a new byte is ready to
transfer to the receiver data
register with RORF stili set. A
receiver framing error has occurred when the byte boundaries
of the bit stream are not synchronized to the bit counter. An overrun can be distinguished from a
framing error by the value of
RORF: if RORF is set, then an
overrun has occurred; otherwise,
a framing error has been
detected. Data is not transferred
to the receive data register in an
overrun condition. ORFE is
cleared by reading the TRCSR
(with ORFE set) then reading the
receive data register, or by reset.
RORF Receive data register full-RORF
is set when the contents of the input serial shift register is transferred to the receive data register. It
is cleared by reading the TRCSR
(with RORF set), and then reading
the receive data register, or by
reset.
Signetics
Serial Operations
The SCI is initialized by writing the control
bytes first to the rate and mode control
register and then to the transmit/receive
control and status register. When TE is
set, the output of the transmit shift
register is connected to P24 and serial
output Is initiated by the transmission of a
9-blt preamble of 1's. At this point, if the
transmit data register (TORE) is empty
(TORE= 1), a continuous string of 1's will
be sent indicating an idle line, or if a byte
has been written to the TORE (TORE = 0),
the byte will be transferred to the transmit
shift register (synchronized with the bit
rate clock), TORE will be set and transmission will begin.
The start bit (0), eight data bits (beginning
with bit 0) and a stop bit (1), will be
transmitted. If TORE is still set when the
next byte transfer should occur, 1's will be
sent until more data Is provided. Receive
operation is controlled by RE which configures P23 as an input and enables the
receiver. In bl·phase format, the output
toggles at the start of each bit and 'at half
time when a '1' Is sent. SCI data formats
are Illustrated in Figure 22. In receiving biphase, a '1' Is input when two transitions
occur in less than 3/4 bit-time, and a '0' is
input when more than 3/4 bit-time passes
after a transition on P23.
INSTRUCTION SET
The SCN68120/SCN68121 is upward source
and object code compatible with the
Motorola MC6800 processor and directly
compatible with the M6801 family processors.
Programming Model
A programming model for the SCN68120/
SCN68121 is shown in Figure 1. Accumulator A can be concatenated with accumulator B and jointly referred to as accumulator 0, where A is the most significant byte. Any operation which modifies
the double accumulator will also modify
accumulator A and/or B. Other registers
are defined as follows:
Program Counter-The program counter
is a 16-bit register which always points to
the next Instruction.
Slack Polnler-The stack pointer is a
16-bit register which contains the address
of the next available location in a
pushdown/pullup (LIFO) queue. The stack
resides in random access memory at a
location specified by the software.
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""""·'tI
Index Register-The index register is a
16-bit register which can be used to store
data or provide an address for the indexed
mode of addressing.
Accumulators-The IPC contains two
B-bit accumulators, A and B, which are
used to store operands and results from
the arithmetic logic unit (ALU). They can
also be concatenated and referred to as
the D (double) accumulator.
Condition Code Register-The condition
code register indicates the results of an
instruction and includes the following five
condition bits: negative (N), zero (Z),
overflow (V), carry/borrow from MSB (G),
and half carry from bit 3 (H). These bits are
testable by the conditional branch instructions. Bit 4 is the interrupt mask (I-bit) and
inhibits all maskable interrupts when set.
The two unused bits, b6 and b7, are read
as ones.
in Tables 14, 15, 16 and 17 where execution times are provided in E-cycles. Instruction execution times are summarized
in Table lB. With an input frequency (E) of
lMHz, E-cycles are equivalent to microseconds. A cycle-by-cycle description of
bus activity for each instruction is provided
in Table 19 and a description of selected instructions is shown in Figure 23.
Addressing Modes
Immediate Addressing-The operand is
contained in the following byte(s) of the
instruction where the number of bytes
matches the size of the register. These are
two or three byte instructions.
The SGN6B120/SCN6B121 provides six addressing modes which can be used to
reference memory. A summary of addressing modes for all instructions is presented
NRZ
FORMAT
Direct Addressing-The least significant
byte of the operand address is contained
in the second byte of the instruction and
the most significant byte is assumed to be
$00. Direct addressing allows the user to
access $00 through $FF using two byte instructions and execution time is reduced
by eliminating the additional memory access (see Table 19).
BI·PHASE
FORMAT
In most applications, this 256-byte area is
reserved for frequently referenced data.
Note that no direct addressing of internal
control registers is possible in mode 3.
OUTPUT
CLOCK
IDLE START
BIT
BIT
STOP
Extended Addressing-The second and
third bytes of the instruction contain the
absolute address of the operand. These
are three byte instructions.
DATA: 01001101 ($4D)
Figure 22. SCI Data Formats
Table 14_ INDEX REGISTER AND STACK MANIPULATION INSTRUCTIONS
Condition Codes
Pointer Operations
Immed Direct
Index
Extnd Inherent
Mnemonic OP- # OP- # OP- # OP- # OP- #
Compare Index Reg
Decrement Index Reg
Decrement Stack Pntr
Increment Index Reg
Increment Stack Pntr
Load Index Reg
Load Stack Pntr
Store Index Reg
Store Stack Pntr
Index Reg - Stack Pntr
Stack Pntr - Index Reg
Add
Push Data
CPX
DEX
DES
INX
INS
LDX
LDS
STX
STS
TXS
TSX
ABX
PSHX
Pull Data
PULX
09
34
08
31
2
2
2
2
EE
AE
EF
AF
5
5
5
5
2
2
2
2
FE
BE
FF
BF
5
5
5
5
3
3
3
3
1
1
1
1
3
3
3
3
35
30
3A
3C
3
3
3
4
1
1
1
1
38 5 1
Signetics
Boolean/
Arithmetic Operation
~-M:M+l
BC 4 3 9C 5 2 AC 6 2 BC 6 3
CE 3 3 DE 4
BE 3 3 9E 4
DF 4
9F 4
5 4 3 2 1 0
X-l-X
SP - 1 -SP
X+1 X
1 SP + 1 SP
M -XH. (M + ll-XL
M -SPH. (M + 11 -SPL
XH -M, XL -(M + 11
SPH -M, SPL -(M + 11
X-I -SP
SP + I-X
B+X-X
XL -MSp, SP - 1 -SP
XH -MSp. SP - 1 --SP
SP + 1 -SP, MSp -XH
SP + 1 -SP, MSp -XL
H I N Z V C
• ·ll llU i
• • ." • •
• • ·li
••••
•• ••
••••••
••
•
••
•
••
•
••
•
••••••
••• ••• ••• ••• ••• •••
••••••
R
R
R
R
4·79
4
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'."""iI·''I
Indexed Addreillng-The unsigned offset contained In the second byte of the Instructions is added with carry to the Index
register and used to reference memory
without changing the Index register.
These are two byte Instructions.
Inherent Addreillng-The operand(s) are
registers and no memory reference .is required. These are single byte Instructons.
Relallve Addressing-Relative addressing
Is used only for branch instructions. If the
branch condition is true, the program
counter Is overwritten with the sum of a
signed single byte displacement In the
second byte of the instruction and the current program counter. This provides a
branch range of - 126 to 129 bytes from
the first byte of the Intruction. These are
-two byte instructions.
CYCLE·IY·CYCLE OPERATION
SUMMARY
Table 19 provides a detailed description of
the Information present on the address
bus, data bus, and the RfW line during
each cycle of each Instruction. Thelnformatlon is useful in comparing actual with
expected results during debug of both
software and hardware as the program is
executed. The information Is categorized
in groups according to addressing mode
and number of cycles per Instruction. In
general, Instructions with the same ad·
dressing mode and number of cycles ex-
ecute in the same manner. Exceptions are
indicated in the table.
Note that during MPU reads of Internal
locations, the resultant value will not appear on the external data bus except in
mode O. 'High order' byte refers to the
most significant byte of a HI-bit value.
The coding of the first (or only) byte cor·
responding to an executable instruction is
sufficient to identify the instruction and
the addressing mode. The hexadecimal
equivalents of the binary codes, which
result from the translation of the 82 in·
structlons In all valid modes of address·
ing, are shown In Table 20. There are 220
valid machine codes, 34 unassigned
codes and two reserved for test purposes.
Table 15. ACCUMULATOR AND MEMORY INSTRUCTIONS
Accumulator and
Merncry Operations
Add Acmltrs
AddBtoX
Add with Carry
Add
Add Double
And
Shift Left,
Arithmetic
Shift Left Obi
Shift Right,
Arithmetic
Bit Test
Compare Acmltrs
Clear
Compare
1'5 Complement
Decimal Adj, A
Decrement
Exclusive OR
Immed
MNE Op - #
ABA
ABX
ADCA 89 2 2
ADCB C9 2 2
ADDA 8B 2 2
ADDB CB 2 2
AD DO C3 4 3
ANDA 84 2 2
ANDB C4 2 2
ASL
ASLA
ASLB
ASLD
ASR
ASRA
ASRB
BITA B5 2 2
BITB C6 2 2
CBA
CLR
CLRA
CLRB
CMPA Bl 2 2
CMPB Cl 2 2
COM
COMA
COMB
DAA
DEC
DECA
DECB
EORA BB 2 2
EORB C8 2 2
Index
Extend
Direct
Inher
Condition Codes
Boolean
Op- # Op- # Op - # Op - #
Expression
H I N Z V C
lB 2 1 A+B -A
I
I I , I
3A 3 1 OO:B+X-X
A+M+C-A
99 3 2 A9 4 2 B9 4 3
B+M+C-B
09 3 2 E9 4 2 F9 4 3
A+M-A
9B 3 2 AB 4 2 BB 4 3
B+M-A
DB 3 2 EB 4 2 FB 4 3
0+ M:M + 1-0
03 5 2 E3 6 2 F3 6 3
A'M-A
R
94 3 2 A4 4 2 B4 4 3
04 3 2 E4 4 2 F4 4 3
B'M-B
R
6B 6 2 7B 6 3
4B 2 1
5B 2
05 3 1
67 6 2776 3
47 2 1
57 2 1
95 3 2 A5 4 2 B5 4 3
R
A'M
05 3 2 E5 4 2 F5 4 3
B·M
R
11 2 1 A-B
I
I I
6F 6 2 7F 6 3
OO-M
R S R R
R S R R
4F 2 1 OO-A
6F 2 1 OO-B
R S R R
A-M
91 3 2 Al 4 2 Bl 4 3
I I
01 3 2 El 4 2 Fl 4 3
B-M
I I
63 6 2 73 6 3
M-M
R S
43 2 1 A-A
R S
R S
53 2 1 Ii-B
19 2 1 Adj binary sum to BCD.
I
6A 6 2 7A 6 3
M-l-M
4A 2 1 A·l-A
5A 2 1 B·l -B
A G) M-A
9B 3 2 AB 4 2 B8 4 3
R
B G) M-B
08 3 2 EB 4 2 F8 4 3
I R
• ••• • • • •
••
•• •
••
••
••
••
•••
••
••
••
•• •
•• ••
•• ••
•
•• •••
•
•• ••
••
••
•
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'w""""_,,,
Table 15. ACCUMULATOR AND MEMORY INSTRUCTIONS (Continued)
Accumulator and
Memorv Operations
Increment
Load Acmltrs
Load Double
Logical Shift,
Left
Shift Right.
Logical
Multiply
2's Complement
(Negate)
No Operation
Inclusive OR
Push Data
Pull Data
Rotate Left
Rotate Right
Subtract Acmltr
Subtract with
CarLY.
Store Acmltrs
Subtract
Subtract Double
Transfer Acmltr
Test, Zero or
Minus
MNE
INC
INCA
INCB
LDAA
LDAB
LOO
LSL
LSLA
LSL8
LSLO
LSR
LSRA
LSRB
LSRD
MUL
NEG
NEGA
NEGB
NOP
ORAA
ORAB
PSHA
PSHB
PULA
PULB
ROL
ROLA
ROLB
ROR
RORA
RORB
SBA
SBCA
SBCB
STAA
STAB
STD
SUBA
SUBB
SUBD
TAB
TBA
TST
TSTA
TSTB
Extend
Immed
Direct
Index
Inher
# Op
Op
# Op
# Op - #
# Op
6C 1 6 2 7C 6 3
4C 2 1
5C 2 1
86 2 2 96 3 2 A6 4 2 B6 4 3
C6 2 2 06 3 2 E6 4 2 F6 4 3
CC 3 3 DC 4 2 EC 5 2 FC 5 3
68 6 2 78 6 3
48 2 1
58 2 1
05 3 1
64 6 2 74 6 3
44 2 1
54 2 1
04 3 1
3D 10 1
60 6 2 70 6 3
40 2 1
50 2 1
01 2 1
8A 2 2 9A 3 2 AA 4 2 BA 4 3
CA 2 2 DA 3 2 EA 4 2 FA 4 3
36 3 1
37 3 1
32 4 1
33 4 1
69 6 2 79 6 3
49 2 1
59 2 1
66 6 2 76 6 3
46 2 1
56 2 1
10 2 1
82 2 2 92 3 2 A2 4 2 B2 4 3
C2 2 2 02 3 2 E2 4 2 F2 4 3
97 3 2 A7 4 2 B7 4 3
07 3 2 E7 4 2 F7 4 3
DO 4 2 ED 5 2 FO 5 3
80 2 2 90 3 2 AO 4 2 BO 4 3
CO 2 2 DO 3 2 EO 4 2 FO 4 3
83 4 3 93 5 2 A3 6 2 B3 6 3
16 2 1
17 2 1
60 6 2 70 6 3
40 2 1
50 2 1
-
-
-
Boolesn
Expression
M+ 1-M
A + 1-A
B + 1 -B
M-A
M-B
M:M + 1-0
Condition Codes
H
N Z V C
I
I
I
I
R
R
R
••
••
•
•
R
R
R
R
AXB-D
00 - M-M
00 - A-A
00 - B-B
PC+1-PC
A+M-A
B + M-B
A -Stack
B -Stack
Stack -A
Stack -B
4
•I •I •I
I I
I
• •I •I •I
I
•••
I
••••
•
• •• ••• ••• •••
I I I I
R
R
I I I I
I
I
f
f
I I
I
A- B-A
A - M - C-A
B - M - C-B
A-M
B-M
o -M:M + 1
A-M-A
B - M-B
0- M:M + 1 -0
A-B
B-A
M -00
A - 00
B - 00
R
R
R
I I
I
•
••
I
I
t I
t
R
R
R
R
R
••
R
R
R
The Condition Code Register notes are listed after Table 17.
Signetics
4·81
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""IIeI·"t
Table 16. JUMP AND BRANCH INSTRUCTIONS
Direct
Operations
Mnemonic
Relative
Index
Extnd
Inherent
OP -# OP- # OP- # OP- # OP
20 3 2
21 3 2
24 3 2
25 3 2
27 3 2
2C 3 2
-1#
Branch Test
Branch Always
BRA
Branch Never
BRN
Branch If Carry Clear
BCC
Branch If Carry Set
BCS
Branch If - Zero
BEQ
Branch If :;0. Zero
BGE
Branch If> Zero
BGT
2E 3
2
Z + (N (!)VI = 0
Branch If Higher
BHI
22 3
2
C+Z=O
Branch If Higher or Same
Bra nch If < Zero
Branch If Carry Set
Branch If lower Or Same
BHS
BlE
24 3 2
2F 3 2
BlO
BlS
25 3 2
23 3 2
< Zero
BlT
203
2
N(!)V - 1
Branch If Minus
BMI
2B 3
2
N- 1
Branch If Not Equal Zero
BNE
26 3
2
Z-O
Branch If Overflow Clear
.BVC
28 3
2
V=O
Branch If Overflow Set
BVS
29 3
2
V-1
N=O
Branch If
Branch If Plus
BPl
2A 3
2
Branch To Subroutine
BSR
BO 6
2
Jump
JMP
None
None
CoO
C= 1
Z=1
N(!)V-O
C =0
Z+(N(!)VI-1
C=1
C+Z-1
6E 3 2 7E 3 3
2
AD 6 2 BO 6 3
See Special
Operations Figure 23
See Special
Operations Figure 23
Jump To Subroutine
JSR
No Operation
NOP
01 2
1
RT!
3B 0
Return From Subroutine
RTS
39 5
Software Interrupt
SWI
3F
Wait For Interrupt
WAI
3E 9
!}
Return From Interrupt
905
}
2
Condo Code Reg.
6 4 3 2 1 0
H I N Z V C
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
• •••• •
••••••
••
•• ••••
••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
••••••
I I I I I I
••••••
• ••••
• •••••
S
Table 17. CONDITION CODE REGISTER MANIPULATION INSTRUCTIONS
Inherent
Mnemonic
OP -
#
800lean Operation
Clear Carry
ClC
OC 2
1
O-C
Clear Interrupt Mask
CLI
OE 2
1
0-1
Operations
Clear Overflow
ClV
OA 2
1
O-V
Set Carry
SEC
00 2
1
1 -C
Set Interrupt Mask
SEI
OF 2
1
1-1
Set Overflow
SEV
OB 2
1
1-V
Accumulator A -CCR
TAP
06 2
1
A-CCR
CCR -Accumulator A
TPA
07 2
1
CCR -A
lEGEND
OPOperation Code (Hexadecimal I
- Number of MPU Cycles
MSp Contents of memory location
pointed to by Stack Pointer
# Number of Program Bytes
+ Arithmetic Plus
- Arithmetic Minus
• Boolean AND
X Arithmetic Multiply
+ Boolean Inclusive OR
(!) Boolean Exclusive OR
iiii Complement of M
- Transfer Into
OBit = Zero
00 Byte = Zero
H
I
N
Z
V
C
R
S
I
Signetics
•••••
• ••••
•••• •
•••••
• ••••
•I II• •I I I I
••••••
R
R
R
S
S
•
S •
CONDITION CODE SYMBOLS
•
4·82
Condo Code Reg.
5 4 3 2 1 0
H I N Z V C
Half·carry from bit 3
Interrupt mask
Negative (sign bitl
Zero (byte)
Overflow. 2's complement
Carry/Borrow from MSB
Reset Always
Set Always
Affected
Not Affected
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'm",,""·",
Table 18. INSTRUCTION EXECUTION TIMES IN E·CYCLES
ADDRESSING MODE
ADDRESSING MODE
!co
ABA
ABX
ADC
ADD
AD DO
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BHS
BIT
BLE
BLO
BLS
BLT
BMI
BNE
BPL
BRA
BRN
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
DEX
EOR
INC
INS
..,co
..,c
.
.§
a
w
~
..,co
..,""
.E
.E
••2
••
3
••
••4
2
3
2
4
2
3
5
3
'6
co
E
••
•
•••
••
••
••
•••
2
•••
•••
•••
•••
2
•4
••
•
•
••
2
ti
!!
••
••
••
•••
•3
••
•••
•••
••
•••
••
••3
•5
••
••
3
•
•
CD
4
4
6
4
6
4
6
4
6
••
•••
4
••
••
••
•••
•••
••
•6
•4
•6
•••
•••
•4
••
••
•
••
•••
•••
••6
•4
6
6
6
6
•6
••
•
6
••4
6
•
•6
••4
6
•
c
co
a;
'".!!a:
co
.z:;
•
•••
2
3
2
•••
••
•••
•••
••
•••
•••
•
2
2
2
2
2
•2
•2
2
3
3
••
3
E
.§
ti
..,
..,c
a
w
.E
•••
2
••5
•3
•3
6
4
5
5
5
6
6
4
5
5
5
6
~
>
'6
CD
•••
•••
••
•
3
3
3
3
3
3
3
•3
3
3
3
3
3
3
3
3
6
3
3
••
••
•
••
•••
••
••
•
CD
INX
JMP
JSR
LOA
LDD
LOS
LOX
LSL
LSLD
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI
Signetics
3
3
3
•••
••
••
2
••
••
••
•••
2
••
••
••
•2
••
••
•••
••
4
CD
!
3
4
4
4
:!
"
•••
••
••
3
••
••
•••
••3
••
•3
••
4
••
•4
4
4
4
3
5
5
5
5
4
6
••
•••
•••
•
..,
..,.,"
CD
•••
•
•6
••
6
•
••
••
6
•
•
•6
•
•6
•4
6
6
•••
••
6
••
•
4
6
••4
•••
4
5
5
5
4
6
•••
••
6
••
•
..
.,..
CD
c
.>
CD
.z:;
;;
!!
.E
a:
•••
•••
•2 ••
3
••
2
3
••
10
2
••
2
•3 ••
4
••
4
5
2
•••
2
10
••
5
2
•2 •••
2
•
2
•
••• •••
•• ••
• ••
12
2
•
2
••
2
2
2
•••
3
3
••
9
3
••
•••
4·83
4
JANUARY 1983
MICROPROCESSOR DIVISION
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""lI'!-"j
-
PC
JSR, JUMP TO SUBROUTINE
f----::'''''===----1
INDXD {
f-,-,,==-,.,.,.,~=~
RTNL.:.:=-==='-"'-I
SP . -__S_T_A_C_K_ _- ,
:::;
R: :R: : :c:'~'- - I
1-1_ _
MAIN PROGRAM
PC
$BD=JSR
EXTND
SH =SUBR. ADDR.
{
Sl = SUBR. ADDR.
NEXT MAIN INSTR.
RTN
PC
BSR, BRANCH TO SUBROUTINE
RTN
RTS, RETURN FROM SUBROUTINE
PC
I
SUBROUTINE
$39= RTS
I
q
q
MAIN PROGRAM
SWI, SOFTWARE INTERUPT
R::
I
$3F-SWI
I
c)
-
SP
STACK
SP.21
SP·l r'_ _--;;RT
..NiH.:......_--i
SP ' -_ _ _
RT_N-'l'-_---'
SP
-
STACK
sp~: I
RTNH
~.====~R:T=:N~l====:::;
SP+2
STACK
SP
SP·7
SP·6
CONDITION CODE
SP·5
ACMITRB
SP·4
ACMITRA
SP·3 INDEX REGISTER (XH)
MAIN PROGRAM
q
Iq
INDEX REGISTER (Xl)
SP·2
SP·l
RTNH
I
SP
RTNl
PC INTERRUPT PROGRAM
SP
STACK
$3E-WAI
WAI, WAIT FOR INTERRUPT
R::
I
I
RTI, RETURN FROM INTERRUPT
$3B_RTI
SP
CONDITION CODE
SP+1
ACMITR B
SP+2
SP+3
ACMITR A
SP+4
INDEX REGISTER (XH)
SP+5
INDEX REGISTER (Xl)
SP+6
RTNH
_SP+7
RTNl
MAIN PROGRAM
MAIN PROGRAM
PC
JMP,JUMP
~_.,;$::6:=E:==:=J:.:M":P=--l
.
c
K=OFFSET
EXTENDED
lEGEND:
RTN = Address of next Instruction In Main Program to be executed upon return from subroutine
4·84
Figure 23. Special Operations
Signetics
$7E=JMP
KH - NEXT ADDRESS
Kl - NEXT ADDRESS
KI NEXTINSTRUCTION I
X + K INEXT INSTRUCTION I
RTNH = Most slgnlflcant byte of Return Address
RTNL = Least significant byte of Return Address
{
-
= Stack pointer after execution
K = a·blt unsigned value
JANUARY 1983
MICROPROCESSOR DIVISION
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm",,""··"
Table 19. CYCLE BY CYCLE OPERATION
Address Mode &
Instructions
Address Bus
Data Bus
IMMEDIATE
ADC EOR
ADD LDA
AND ORA
BIT SBC
CMP SUB
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Operand Data
LOS
LDX
LDD
CPX
SUBD
ADDD
3
1
2
Op Code Address
Op Code Address + 1
Op Code Address + 2
Op Code Address
Op Code Address + 1
Op Code Address + 2
Address Bus FFFF
1
1
1
1
1
1
1
Op Code
Operand Data (H igh Order Byte)
Operand Data (Low Order Byte)
Op Code
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
.Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address of Operand
1
1
1
Op Code
Address of Operand
Operand Data
Op Code Address
Op Code Address + 1
Destination Address
1
1
Op Code
Destination Address
Data from Accumulator
Op Code
Address of Operand
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
DIRECT
ADC EOR
ADD LDA
AND ORA
BIT SBC
CMP SUB
STA
3
4
1
2
3
4
3
1
2
3
3
1
2
3
LDS
LDX
LDD
4
1
2
3
4
STS
STX
STD
CPX
SUBD
ADDD
4
1
2
3
5
4
1
2
3
4
5
JSR
5
1
2
3
4
5
Op Code Address
Op Code Address + 1
Address of Operand
Operand Address + 1
Op Code Address
Op Code Address + 1
Address of Operand
Address of Operand + 1
Op Code Address
Op Code Address + 1
Operand Address
Operand Address + 1
Address Bus FFFF
Op Code Address
Op Code Address + 1
Subroutine Address
Stack Pointer
Stack Pointer + 1
Signetics
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
Op Code
Address of Operand
Register Data (High Order Byte)
Register Data (Low Order Byte)
Op Code
Address of Operand
Operand Data (H igh Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code
Irrelevant Data
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
4·85
4
JANUARY 1983
MICROPROCESSOR DIVISION
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm",,""-",
Table 19. CYCLE BY CYCLE OPERATION (Continued)
Address Mode &
Instr.uctions
Address Bus
Data Bus
EXTENDED
JMP
3
ADC EOR
ADD LOA
AND ORA
4
1
2
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
Op Code
Jump Address (High Order Byte)
Jump Address (Low Order Byte)
3
Op Code Address
Op Code Address + 1
Op Code Address + 2
1
1
1
4
Address of Operand
1
Op Code
Address of Operand
Address of Operand
(Low Order Byte)
Operand Data
1
2
Op Code Address
Op Code Address + 1
1
1
3
Op Code Address + 2
1
4
Operand Destination Address
a
1
2
Op Code Address
Op Code Address + 1
1
1
3
Op Code Address + 2
1
4
5
Address of Operand
Address of Operand + 1
1
1
1
2
Op Code Address
Op Code Address + 1
1
1
3
Op Code Address + 2
1
4
5
Address of Operand
Address of Operand + 1
a
a
1
2
Op Code Address
Op Code Address + 1
1
1
CLR ROL
3
Op Code Address + 2
1
COM ROR
DEC TST
INC
4
5
6
Address of Operand
Address Bus FFFF
Address of Operand
1
1
a
1
2
Op Code Address
Op Code Address + 1
1
1
3
Op code Address + 2
1
4
5
6
Operand Address
Operand Address + 1
Address Bus FFFF
1
1
1
1
2
Op Code Address
Op Code Address + 1
1
1
3
Op Code Address + 2
1
4
5
Subroutine Starting Address
Stack Pointer
a
6
Stack Pointer - 1
a
3
BIT SBC
CMP SUB
STA
LOS
LOX
4
5
LDD
STS
STX
5
STD
ASL LSR
ASR NEG
CPX
SUBD
6
6
ADDD
JSR
4·86
6
1
2
Signetics
1
Op Code
Destination Address
(High Order Byte)
Destination Address
(Low Order Byte)
Data from Accumulator
Op Code
Address of Operand
(High Order Byte)
Address of Operand
(Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Address of Operand
(High Order Byte)
Address of Operand
(Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code
Address of Operand
(High Order Byte)
Address of Operand
(Low Order Byte)
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code
Operand Address
(High Order Byte)
Operand Address
(Low Order Byte)
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code
Address of Subroutine
(High Order Byte)
Address of Subroutine
(Low Order Byte)
Op Code of Next Instruction
Return Address
(Low Order Byte)
Return Address
High Order Byt~
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'W""""·"t
Table 19. CYCLE BY CYCLE OPERATION (Continued)
Address Mode &
Instructions
INDEXED
JMP
Address Bus
3
1
2
3
ADC EOR
ADD LDA
AND ORA
BIT SBC
CMP SUB
4
STA
4
1
2
3
4
1
2
3
4
LDS
LDX
LDD
5
STS
STX
STD
5
1
2
3
4
5
1
2
3
4
5
ASL LSR
ASR NEG
CLR ROL
COM ROR
DEC TST (1)
INC
6
CPX
SUBD
ADDD
6
JSR
6
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
6
R/W
Line
Data Bus
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Index Register Plus Offset + 1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register Plus Offset
Address Bus FFFF
Index Register Plus Offset
0
0
1
1
1
1
1
0
Op Code
Offset
Low Byte of Restart Vector
Current Operand Data
Low Byte of Restart Vector
New Operand Data
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Index Register + Offset + 1
Address Bus FFFF
1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
Operand Data (High Order Byte)
Operand Data (Low Order Byte)
Low Byte of Restart Vector
Op Code Address
Op Code Address + 1
Address Bus FFFF
Index Register + Offset
Stack Pointer
Stack Pointer - 1
1
1
1
1
Op Code
Offset
Low Byte of Restart Vector
First Subroutine Op Code
Return Address (Low Order Byte)
Return Address (High Order Byte)
Signetics
0
0
4·87
4
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
Table 19. CYCLE BY CYCLE OPERATION (Continued)
Address Mode &
Instructions
Address Bus
R/W
Line
Data Bus
INHERENT
ABA DAA SEC
ASL DEC SEI
ASR INC SEV
CBA LSR TAB
CLC NEG TAP
CLI NOP TBA
CLR ROL TPA
CLV ROR TST
COM SBA
2
1
2
Op Code Address
Op Code Address + 1
1
1
Op Code
Op Code of Next Instruction
ABX
3
1
2
3
Op Code Address
Op Code Address +1
Address Bus FFFF
1
1
1
Op Code
Irrelevent Data
Low Byte of Restart Vector
ASLD
LSRD
3
1
2
3
Op Code Address
Op Code Address +1
Address Bus FFFF
1
1
1
Op Code
Irrelevant Data
Low Byte of Restart Vector
DES
INS
3
1
2
3
Op Code Address
Op Code Address + 1
Previous Register Contents
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
INX
DEX
3
1
2
3
Op Code Address
Op Code Address +1
Address Bus FFFF
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
PSHA
PSHB
3
1
2
3
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
0
Op Code
Op Code of Next Instruction
Accumulator Data
TSX
3
1
Op Code Address
Op Code Address + 1
Stack Pointer
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
3
Op Code Address
Op Code Address + 1
Address Bus FFFF
1
1
1
Op Code
Op Code of Next Instruction
Low Byte of Restart Vector
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer +1
1
1
1
1
Op Code
Op Code of Next Instruction
Irrelevant Data
Operand Data from Stack
1
1
1
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer -1
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer +1
Stack Pointer +2
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer +1
5
Stack Pointer +2
1
Op Code
Irrelevant Data
Index Register (Low Order Bytej
Index Register (High Order Bytej
Op Code
Irrelevant Data
Irrelevant Data
Index Register (High Order Bytej
Index Register (Low Order Bytej
Op Code
Irrelevant Data
Irrelevant Data
Address of Nexl Instruction
(High Order Bytej
Address of Next Instruction
(Low Order Bytej
1
2
3
4
Op Code Address
Op Code Address + 1
Stack Pointer
Stack Pointer -1
1
1
0
0
5
6
Stack
Stack
Stack
Stack
Stack
0
0
0
0
0
2
3
TXS
3
1
2
PULA
PULB
4
PSHX
4
2
PULX
5
3
4
1
2
RTS
5
3
4
5
1
2
WAI
9
7
8
9
4-88
Pointer
Pointer
Pointer
Pointer
Pointer
-2
-3
-4
-5
-6
Signetics
0
0
1
1
1
1
1
1
1
1
1
Op Code
Op Code of Next Instruction
Return Address (Low Order Bytej
Return Address
(High Order Bytej
Index Register (Low Order Bytej
Index Register (High Order Bytej
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'W"""'!-"A
Table 19. CYCLE BY CYCLE OPERATION (Continued)
Address Mode &
Instructions
Address Bus
R/W
Data Bus
Line
INHERENT
10
MUl
1
1
1
1
1
10
Op Code Address
Op Code Address +1
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
Address Bus FFFF
1
2
3
4
Op Code Address
Op Code Address +1
Stack Pointer
Stack Pointer +1
1
1
1
1
5
Stack Pointer +2
1
6
Stack Pointer +3
1
7
Stack Pointer +4
1
B
Stack Pointer +5
1
1
2
3
4
5
6
7
B
9
10
RTI
12
SWI
1
1
1
1
1
9
Stack Pointer +6
1
10
Stack Pointer +7
1
1
2
3
4
Op Code Address
Op Code Address +1
Stack Pointer
Stack Pointer -·1
1
1
0
0
5
6
7
B
10
11
Stack Pointer -2
Stack Pointer -3
Stack Pointer -4
Stack Pointer -5
Stack Pointer -6
Stack Pointer -7
Vector Address FFFA (Hex)
0
0
0
0
0
1
1
12
Vector Address FFFB (Hex)
1
9
Op Code
Irrelevant
low Byte
low Byte
low Byte
low Byte
Low Byte
low Byte
low Byte
low Byte
Data
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
of Restart
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Vector
Op Code
Irrelevant Data
I rre.leva nt Data
Contents of Condo Code Reg.
from Stack
Contents of Accumulator B
from Stack
Contents of Accumulator A
from Stack
Index Register from Stack
(High Order Byte)
Index Register from Stack
(low Order Byte)
Next Instruction Address from
Stack (High Order Byte)
Next Instruction Address from
Stack (low Order Byte)
Op Code
Irrelevant Data
Return Address (low Order Byte)
Return Address
(High Order Byte)
Index Register (low Order Byte)
Index Register (High Order Byte)
Contents of Accumulator A
Contents of Accumulator B
Contents of Condo Code Register
Irrelevant Data
Address of Subroutine
(High Order Byte)
Address of Subroutine
(low Order Byte)
RELATIVE
BCC
BCS
BEQ
BGE
BGT
BSR
BHT BNE BlO
BlE BPl BHS
BlS BRA BRN
BlT BVC
BMT BVS
3
1
2
3
Op Code Address
Op Code Address +1
Address Bus FFFF
1
1
1
Op Code
Branch Offset
low Byte of Restart Vector
6
1
2
3
4
5
6
Op Code Address
Op Code Address +1
Address Bus FFFF
Subroutine Starting Address
Stack Pointer
Stack Pointer -1
1
1
1
1
0
0
Op Code
Branch Offset
low Byte of Restart Vector
Op Code of Next Instruction
Return Address (low Order Byte)
Return Address(High Order Byte)
Signetics
4·89
4
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""!ui_',,
Table 20. CPU INSTRUCTION MAP
0.
00
MNEM
MODE
-
•
01
02
03
NOP
IN ER
2
1
04
LSRD
3
05
06
07
08
09
OA
OB
DC
ASlD
3
TAP
TPA
2
2
3
3
2
1
1
1
'1
00
OE
elF
10
11
INX
DEX
CLV
SEV
CLC
SEC
Cli
SEI
S8A
C8A
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
12
13
14
15
16
17
,
TAB
TBA
2
1
1
2
1
18
"1A
18
lC
DAA
A8A
INHER
INHEA
2
1
10
1E
IF
20
21
22
23
24
25
26
27
28
29
2A
28
2C
20
2E
2F
30
31
32
33
0.
MNEM
34
35
36
37
38
39
3A
38
3C
3D
3E
3F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
40
4E
4F
50
51
DES
TXS
PSHA
PSHB
PULX
RTS
A8X
RTI
PSHX
MUL
WAI
SWI
NEGA
MODE
lNHE'R
8RA
8RN
BHI
8LS
Bce
8CS
BNE
BEO
BVC
BVS
8Pl
8MI
8GE
8Ll
8GT
8LE
TSX
INS
PULA
PUL8
REl
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
REl
INHER
t
INHEA
3
3
3
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
12
COMA
LSRA
2
2
2
2
FlORA
ASRA
ASlA:
ROLA
,
2
2
OECA
2
2
INCA
TSlA
T
CLRA
NEGB
2
2
,
,,
2
COMB
LSRB
RORB
ASRB
ASLB
ROLB
DECB
COM
LSR
ROR
ASR
INHER
INDXD
I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
,
2
1
1
6
1
2
2
1
•
1
1
1
1
1
2
INCB
TST8
CLAB
NEG
3
3
3
3
5
5
3
10
4
10
9
2
52
53
54
55
56
57
58
59
5A
58
5C
50
5E
SF
60
61
62
63
64
65
66
67
-
,
,
6
6
2
2
6
INDXD 6
2
2
0.
MNEM
68
69
6A
6B
6C
60
6E
6F
70
ASL
ROL
DEC
INC
TST
JMP
CLR
NEG
MODE
INOXD
I
-•
INDXD
EXTND
2
2
2
6
6
3
6
6
2
2
2
2
3
6
6
3
3
71
72
73
74
75
76
77
78
7'
7A
78
7C
70
7E
7F
80
B1
82
83
B4
85
86
87
88
89
8A
8B
BC
80
8E
OF
90
91
92
93
,.
95
96
97
98
99
9A
98
COM
LSR
ROR
ASR
ASL
ROL
DEC
6
6
6
6
6
3
3
3
3
3
INC
TST
JMP
6
6
3
6
3
3
3
3
2
2
2
3
2
2
2
elA
SUBA
CMPA
EXTND
IMMED
seeA
EORA
ADCA
ORAA
ADDA
CPX
BSR
LOS
SUBA
CMPA
SBCA
SUBD
ANDA
BITA
LDAA
STAA
EOAA
ADCA
ORAA
AODA
2
2
2
4
SUBD
ANDA
BITA
LDAA
2
2
2
,,
,,
IMMED
REL
IMMED
DIR
•
6
3
3
3
3
,
3
3
3
3
DIR
NOTES:
1. Addressing Modes
INHERElnherent INDXD=lndexed
IMMED=lmmediate
REL", Relative
EXTND", Extended
DIR-Direct
2. Unassigned opcodes are indicated by"·" and should not be executed.
3. Codes rriarked by "1" force the PC to function as a 16-bit counter.
4·90
6
6
6
Signetics
3
3
3
3
2
2
2
2
3
2
3
2
2
2
2
2
2
2
2
2
2
2
2
0•
MNEM
9C
90
9E
9F
40
A1
A2
A3
A4
A5
A6
A7
A8
CPX
JSR
LOS
STS
SUBA
CMPA
BITA
LDAA
STAA
EORA
B;l
SUBD
ANDA
SlTA
lDAA
STAA
C3
C4
05
C6
C7
C8
C.
CA
C8
CC
CD
CE
CF
DR
INoxa
saCA
sueD
A'
AA
A8
AC
AD
AE
AF
80
81
82
C2
Dlt,
ANDA
ADCA
ORAA
ADOA
CPx
JSR
LOS
STS
SU8A
CMPA
B4
B5
B6
B7
BB
B9
BA
B8
BC
8D
BE
BF
CO
Cl
MODE
,,
6
INDXD
fXTND
·
4
4
6
•
4
4
4
4
4
fORA
ADCA
ORAA
•
4
6
6
EXTND
IMMED
,
,,
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
J
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
2
2
2
3
, ,
,
,
4
2
2
EORB
ADCB
OAAB
ADD8
lOO
lDX
5
5
4
4
4
4
4
6
4
4
4
4
4
4
4
4
6
seeA
AOOA
CPX
JSR
LDS
STS
SUBB
CMPB
SBCB
ADDD
ANDB
BIT8
LDAB
-•
3
2
2
2
2
3
3
3
,
2
IMMED
2
2
0.
DO
01
02
03
04
05
D6
07
MNEM
MODE
SUBS
DIR
CMPB
SI!CB
ADOD
ANOS
BIT8
lDAB
STAB
EORB
08
09
DA
DB
DC
DO
DE
OF
EO
ADOS
LDD
STO
LOX
STX
SUBS
E1
CMPB
E2
E3
E4
E5
E6
S8CB
ADOD
ANDB
BIT8
LOAS
STAB
EORB
E7
EB
E9
EA
EB
EC
ED
EF
EF
FO
F1
F2
f3
F4
"
F6
F7
F8
F9
FA
F8
Fe
FO
FE
FF
ADee
DRAB
DIR
INoxa
3
3
3
5
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
6
4
4
4
4
4
4
4
4
ADes
DRAB
ADDS
LDD
STO
LOX
STX
SUBB
CMPB
SBCB
ADDD
ANDB
BITB
LDAB
STAB
EOAB
ADCB
DRAB
ADDB
LDO
STO
LDX
STX
-•
4
4
4
4
,
,,
,,
3
3
3
3
3
3
3
5
5
5
4
4
4
6
4
•
•
4
EXTND
'UNDfFlNFD OP rODE
,
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
,
INDXQ
ExTND
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
J
3
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'19"..11"-'1'
APPENDIX A
SCN68120 CUSTOM ORDERING INFORMATION
CUSTOM SCN68120 ORDERING
INFORMATION
The custom SCN68120 specifications may
be transmitted to Signetics in EPROM(s)
formatted and packaged as indicated
below, and mailed prepaid and insured
with a cover letter (see figure A·1) to:
notation for address and data), may be
submitted for pattern generation. The
2708s must be clearly marked to indicate
which PROM corresponds to which ad·
dress space ($X800·$XFFF). See figure A·2
for recommended marking procedure.
Signetics Corporation
Microprocessor Marketing
Bin 1276
P.O. Box 409
Sunnyvale, California 94086
Address $FFEF is reserved for the
checksum value for the ROM, to be
generated at the factory.
A copy of the cover letter should also be
mailed separately.
After the EPROM(s) are marked, they
should be placed in conductive IC carriers
and securely packed. Do not use
styrofoam.
EPROMs
2708 and 2716 type EPROMs, programmed
with the custom program (positive logic
CUSTOMER NAME _______________________________________________________
ADDRESS ____________________________________________________________
ST ATE __________________________ CITY ____________________ ZIP __________
PHONE _______________________________ EXTENSION _______________________
CONTACT MS/MR _______________________________________________________
CUSTOMERPART# ______________________________________________________
ROM START ADDRESS OPTION
$C800
$D800
$EBOO
$FOOO
A12 and A13 don't care
o
o
o
o
PATTERN MEDIA 1
02708 EPROM
2716 EPROM
TEMPERATURE RANGE
DO' to 70'C
o
PACKAGE TYPE
Ceramic
o
o
MARKING
Standard
Special
o
o
RAM START ADDRESS OPTION
$0080
o
NOTE: (11 Other Media ReqUire Prior Factory Approval
SIGNATURE ___________________________________________________________
TITLE _______________________________________________________________
Figure A·1. Ordering Information Form
~
~
~
~
xxx = Customer 10
Figure A·2. Recommended Marking
Signetics
4·91
4
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'tlG'I",,'uie'tA
ABSOLUTE MAXIMUM RATINGS1
Parameter
Rating
Unit
Supply voltage
Input voltage3
Operating temperature range 2
Storage temperature
-0.3to + 7.0
-0.3to + 7.0
to + 70
-55to+150
V
V
·C
·C
o
DC ELECTRICAL CHARACTERISTICS
Vee= 5.0V ± 5%, Vss=OV; TA=O·C to + 70·C4,5
Limits
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
Local bus (see Figures 24, 25)
V EIH
Input high voltage
E
Vee - 0.75
Vee
V
VEIL
Input low voltage
E
-0.3
0.6
V
VIH
Input high voltage
RESET
Other inputs6
4.0
2.0
Vee
Vee
V
V
-0.3
0.8
V
0.5
0.8
mA
mA
1.5
2.5
"A
2.0
10.0
10
100
"A
"A
VIL
Input low voltage
All inputs6
lin
Input load current
Port 4
SCl
Yin = 0 to 2.4V
lin
Input leakage current
HALT/NMI,IRQ1,RESET
Vln = 0 to 5.25V
ITSI
Three-state (off state)
input current
SOO-SD7, P30·P37
P20-P24
Output high voltage
P30-P37
P40·P47, SC1, SC2
Other outputs
VOH
VOL
Output low voltage
All outputs
PINT
Internal power dissipation
Cin
Input capacitance
P30·P37, P40-P47, SCl
Other Inputs
Vln = 0.5 to 2.4V
Iload= -205"A, Vee = min
Iload= -145"A, Vee = min
IIOad= -100"A, Vee = min
2.5
2.4
2.4
V
V
V
Iload= 2.0mA, Vee = min
TA=O·C
0.5
V
1200
mW
12.5
10.0
pF
pF
Vln = 0, T A= 25·C, fo= 1.0MHz
System bus (see Figure 26)
V IH
Input high voltage
CS, OTACK, SAD-SA7,
500·507, SR/W
2.0
Vee
V
V IL
Input low voltage
CS, OTACK, SAO·SA7,
500-507, SR/W
-0.3
0.8
V
V OH
Output high voltage
OTACK,SOO·S07
VOL
Output low voltage
OTACK,SOO-S07
Iload = -400"A, Vee=min
Iload= 5.3mA, Vee= min
NOTES;
See AC Electrical Characteristics.
4-92
Signefics
2.4
V
0.5
V
MICROPROCESSOR DIVISION
JANUARY 19S3
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'm""n.I_.,.,
AC ELECTRICAL SPECIFICATIONS Vcc =5VDC
± 5%, Vss=OVDC, TA=O·C to 70·C4,5
Tentative limits
Number
Characteristic
Symbol
Min
Unit
Max
Peripheral port (see Figures 27 through 30)
-
Peripheral data setup time
tposu
200
ns
-
Peripheral data hold time
tpOH
200
ns
-
Delay time, enable positive transition
to OS3 negative transition
tOS01
350
ns
-
Delay time, enable positive transition
to OS3 positive transition
Delay time, enable negative transition
to peripheral data valid (ports 2, 3, 4)
tOS02
350
ns
t pwo
350
ns
2.0
P.s
-
-
-
Delay time, enable negative transition
to peripheral CMOS data valid
Input strobe pulse width
tCMOS
t pWIS
200
ns
Input data hold time
Input data setup time
Input capture pulse width (timer function)
tlH
tiS
t pWIC
50
20
2
ns
ns
Eeye
1.0MHz
Number
Characteristic
Symbol
Min
1.2SMHz
Max
Min
Max
Unit
Local bus (see Figures 7, 9)1
1
Cycle time
tcye
1.0
2.0
O.S
2.0
2
Pulse width, E low
PW EL
430
1000
360
1000
ns
3
Pulse width, E high
PW EH
450
1000
360
1000
ns
4
Clock rise and fall time
tn t f
25
ns
9
Non·muxed address hold time
tAH
11
Address delay from E low
tAO
17
Read data setup time
tOSR
SO
1S
Read data hold time
tOHR
10
19
Write data delay time
toow
21
Write data hold time
tOHW
23
Muxed address delay from AS
tADM
25
Muxed address hold time
tAHL
20
26
Delay time E to AS rise
t ASD
100
SO
27
Pulse width, AS high
PW ASH
220
170
ns
2S
Delay time AS to E rise
t ASED
100
SO
ns
29
Usable access time 'O
t ACC
570
-
Enable rise time extended
tERE
-
Processor control setup time
t pcs
200
Processor control hold time
t pCH
20
25
20
20
260
ns
220
70
20
ns
200
110
20
70
ns
110
ns
ns
435
SO
ns
SO
20
ns
ns
200
40
ns
ns
20
90
ns
ns
10
225
P.s
40
ns
NOTES;
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the davice. This Is stress rating only and functional operation of the device at
these or at any other condition above those Indicated in the operation sBction of this specification Is not Implied.
2. For operating at elevated temperatures. the davice must be derated based on + 150·C maximum junction temperature.
3. This product Includes circuitry specifically designed for the protection of Its Internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested
that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
4. Parameters are valid over specified temperature range.
5. All voltage measurements are referenced to ground (GND). For testing, all Input signals swing between 0.4V and 2.4V with a transition time of 20ns maximum. All time
measurements are referenced at Input voltages of O.BV and 2.0V and output voltages of O.BV and 2.0V as appropriate.
6. Except mode programming levels; see figure 16.
Signetics
4·93
4
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
SCN68120/SCN68121
'am""n"·"t
AC ELECTRICAL SPECIFICATIONS (Continued)
1.0MHz
Number
Characteristic
Symbol
Min
1.2SMHz
Max
Min
Max
Unit
Synchronous system bus
(see Figure 36)7
1
Cycle time
teye
1.0
10
0.80
10
/is
2
Pulse width, E low
PW EL
430
9500
360
9500
ns
PW EH
450
9500
360
9500
ns
25
ns
3
Pulse width, E high
4
Clock rise and fall time
t" t f
9
Address hold time
tAH
10
10
ns
13
Address setup time before E
tAH
80
70
ns
14
Chip select setup time before E
tcs
80
70
ns
15
Chip select hold time
tCH
10
10
18
Read data hold time
tOHR
30
21
Write data hold time
tOHW
10
30
Output data delay time
tOOR
31
Input data setup time
tosw
-
Clock enable rise time extended
tERE
Number
Characteristic
25
100
ns
30
85
290
240
165
80
Min
80
Typ
ns
ns
120
Symbol
ns
ns
10
ns
Max
Unit
2.0
/is
Asynchronous system bus
(see Figures 32 through 35)
-
Cycle time
tcyc
0.8
System address setup
t SAS
30
ns
-
System address hold
tSAH
0
ns
-
System data delay read
Semaphore
tSOOR
tsooR
0.3
RAM
-
System data valid
tsov
0
System data hold read
tSOHR
30
System data delay write
Semaphore 9
RAM
tsoow
tsoow
-
System data hold write
t SOHW ·
0
-
Data acknowledge
Semaphore
tOAL
0.5
RAM
-
8
I's
ns
ns
90
ns
60
ns
ns
ns
0.5+ teye8
I'S
ns
315
tOAL
Data acknowledge high
tOAH
60
ns
Data acknowledge three-state
tOAT
90
ns
Data acknowledge low to CS high
tocs
7. Voltage levels shown are VL :s; O.5V, VH 2:!: 2.4V, unless otherwise specified.
8. Actual values dependent on clock period.
9. Data need not be valid on write to semaphore registers.
10.Usable access time Is computed by: 1 - (4 + 11 + 17).
4·94
0.3 + 'eye
315
Signetics
60
ns
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT PERIPHERAL CONTROLLER
'm",,",,-','
SCN68120/SCN68121
POWER CONSIDERATIONS
The average chip-Iunction temperature, T J, in DC can be obtained from:
(1)
TJ=TA+IPDoOJA)
Where:
T A= Ambient Temperature,
°c
OJA = Package Thermal Resistance, Junction-to-Ambient, °C/W
Po = PINT + PPORT
PINT = ICC x VCe. Watts -
Chip Internal Power
PPORT= Port Power DISSipation, Watts -
User Determined
For most applications PPORT~ PINT and can be neglected. PPORT may become significant if the device is configured to
drive Darlington bases or sink LED loads.
An approximate relationship between Po and T J lif PPORT IS neglected I is
4
(2)
PO=K+ITJ+273°CI
Solving equations 1 and 2 for K gives:
K = PoolT A + 273°C) + OJA o P0 2
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring Po lat equilibrium)
for a known T A. USing thiS value of K the values of Po and T J can be obtained by solving equations III and (2) Iteratively for any
value of T A-
Vee
Rl=2.0kQ
TEST POINT
TEST POINT
O - - - -.....- - . - -...~I--... MMD6150
O~---,
t·"
or Equiv.
MMD7000
or Equiv.
C=90 pF for P30·P37, P40·P47, SC1, SC2
= 30 pF for P20·P24, HJITi'liiAlNMi
R = 16.5 kQ for P40·P47, SC1, SC2
= 12 kQ for P30·P37
= 24 kQ for P20·P24,
Figure 24. CMOS Load
HAI'i'iiiAlNMi
Figure 25, Timing Test Load Ports 2, 3, 4
Signetics
4·95
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'am""II,I.",
~
Vcc
•
RL=750Q
TEST POINTo----......--~-1I4------i MMD6150
" or Equlv.
c
:::r::
,r'r- or Equlv.
•
C=I30 pF
R=6 kS2
P2D·P24
P4D·P47
INPUTS
~~
~R
MMD700D
P3D·P37
INPUTS'
* Port 3 Non-Latched Operation (LATCH ENABLE=O)
Figure 26. Timing Test Load 500·507, DTACK
Figure 27. Data Setup and Hold Times (MPU Read Local Bus)
rMPUWHITE
\
-ICMOS1
_IPWD
_____
1:r-1,' ___-
-D.7VCC
--"\~
ALL DATA
PORT OUTPUTS _ _ _ _ _ _ _ _J
ADDRESS
BUS
DATA VALID
1'-_ _ _ __
NOTES:
1. 10 k Pullup resistor required for Port 2 to reach 0.7 Vee
2. Not applicable to P21
3. Port 4 cannot ba pulled above Vee
Figure 26. Data Setup and Hold Times (MPU Write Local Bus)
4·96
Signetics
Figure 29. Port 3 Latch Timing (Single Chip Mode)
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'm""",,··t,
~ . ~.w"j
iSa
tlH"
P30.P37~
INPUTS
DATA VALID
K
4
Figure 30. Expanded Non·Multiplexed Local Bus Timing
~------------0--~--------------~
tERE
iDs. RIS
--+-+>b...."..T"i".....".."A-l.,---------+t-----------------Hr.t=7<:"70
ADDRESS
.......
INON·MUXED) --+-R=..lL"-"'-L..lL9~--------+lr----------------H-"f"""--
READ DATA MUXED
ADDRIDATA
MUXEO
-++-''P'
~--~'9'---~
WRITE DATA MUXED
ADDRfDATA
MUXED
-::;=::-t-''f=Y
ADDRESS
STROBE (AS)
----""f"
NOTES
1. Address valid on the occurrence of the latest of 11 or 23.
2. Usable access time is computed by 1 - (4 + 11 + 17), see note 1.
Figure 31. Local Bus Timing
Signetics
4·97
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68120/SCN68121
INTELLIGENT PERIPHERAL CONTROLLER
'IDn,,)"'.'ii
~-....~ tSDDR
SDO-SD7
THREE STATE
Figure 32. Asynchronous Read of Semaphore Raglster
Figure 33. Asynchronous Write of Semaphore Register
SAO-SA7
SDO-SD7
----iif+H ~~~--T4r-~-r--~~-+--~~~~t-
4
w
ffi
.,
ffl
I~
II:
C
C
.
.:;:
.
C
C
w
I~
II:
.
:;:C
W
!::
II:
~
Figure 36. Synchronous System Bus Timing
Signetics
4·99
JANUARY 1983
MICROPROCESSOR DIVISION
PARALLEL INTERFACE/TIMER
SCN68230
'mn,,"".',J
DESCRIPTION
The SCN68230 Parallel InterfacelTimer
(PIIT) provides versatile double buffered
parallel interfaces and an operating system oriented timer to S68000 systems. The
parallel interfaces operate in unidirectional or bidirectional modes, either 8 or
16 bits wide. In the unidirectional modes,
an associated data direction register
determines whether the port pins are inputs or outputs. In the bidirectional
modes, the data direction registers are ignored and the direction is determined
dynamically by the state of four handshake pins. These programmable handshake pins provide an interface flexible
enough for connection to a wide variety of
low, medium, or high speed peripherals or
other computer systems. The PitT ports
allow use of vectored or autovectored interrupts, and also provide a DMA request
pin for connection to direct memory access
controllers. The PIIT timer contains a 24-bit
counter and a 5-bit prescaler. The timer
can be clocked by the system clock (PitT
ClK pin) or by an external clock (TIN pin),
and a 5-bit prescaler can be used. It can
generate periodic interrupts, a square
wave or a single interrupt after a programmed time period. Also it can be used for
elapsed time measurement or as a device
watchdog. Table 1 is a summary of the input and output signals and Figure 1 shows
the functional pin assignments. Figure 2
is a PitT system block diagram.
FEATURES
• S68000 bus compatible
• Port modes include:
Bit 110
Unidirectional 8-blt and 16-bit
Bidirectional 8-blt and 16-bit
• Selectable handshaking options
24-Blt programmable timer
• Software programmable timer modes
• Contains interrupt vector generation
logic
• Separate port and timer Interrupt
service requests
• Registers are readtwrite and directly
addressable
• Registers are addressed for MOVEP
(move peripheral) and DMAC compatibility
ORDERING CODE
Packages
Ceramic DIP
Plastic DIP
8 MHz
10 MHz
SCN68230C8148
SCN68230C8N48
SCN68230CAI48
SCN68230CAN48
00-07
PAO-7
PBO-7
RS1·RS5
R/W
H1
H2
H3
SCN68230
PI/T
H4
PC7/iiACi('
PC6/PIACK'
PC5/PiRQ'
PC4/iiM'AiiEci"
PC3/TOUT"
L-__________
PC2lTlN'
PC1
~~--PCO
*Individually Programmable Dual-Function Pin.
Figure 1. Functional Pin Assignment
11n this data sheet, barring signal names (overseare) to indicate low is done only for the pin configuration diagram,
signal description headings, tables and figures.
4·100
Signetics
PIN CONFIGURATION 1
JANUARY 1963
MICROPROCESSOR DIVISION
SCN68230
PARALLEL INTERFACE/TIMER
'm",,",I.'ij
, t , , , , ,, t t t
41
CS
38
a9
40
VSS RESET CLK
~
~
~
42
Di'ACK
43
RiW
44
DO
45
D1
46
D2
47
D3
48
D4
2
D6
D5
DATA BUS INTERFACE AND
INTERRUPT VECTOR REGISTERS
!
PORT
INTERRUPTI
DMA
CONTROL
LOGIC
fr
V"
~
Jl
4
~
.----,./
INTERNAL
DATA BUS
HANDSHAKE
CONTROLLERS
AND
MODE LOGIC
TIMER
-
HANDSHAKE
INTERFACE
LOGIC
I-
,
I---
...
v
~
PORT C AND PIN FUNCTION MULTIPLEXER
PC71
TIACK
37
PC61
:
PC51
PiiCR PiiiQ
36
35
f
PC4I
DMAiiEQ
34
f
f
PC3/
TOUT
33
PC2I
TIN
32
;
PC1
31
Signetics
---
t
l
;
PORT
A
V
~
f
3
D7
,
PCO
30
/
+
RS1
29
---
PORT
B
+
RS2
28
+
RS3
27
+
RS4
26
PAO
PA1
PA2
PA3
PA4
PAS
PA8
PA7
4
5
6
7
8
9
10
11
VCC
12
H1
H2
H3
H4
13
14
15
16
PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7
17
18
19
20
21
22
23
24
+
RS5
25
4·101
JANUARY 1983
MICROPROCESSOR DIVISION
PARALLEL INTERFACE/TIMER
SCN68230
'm""",'·",,
Table 1 SIGNAL SUMMARY
Signal Nama
Input/Output
Active State
Three State
Bidirectional Data Bus
Register Selects
Read/Write Input
00·07
RS1·RS5
RIW
Input/output
input
input
yes
Chip Select
Data Transfer Acknowledge
Reset
Clock Input
Port A and Port B
Handshake
Handshake
Port C
Ground
Power Input
CS
DTACK
RESET
CLK
PA()'PA7, PBO·PB7
H1, H3
H2, H4
PC()'PC7
VSS
VCC
input
output
input
input
input/output
input
input/outpui .
input/output
input'
input
high
high
read·high
write·low
low
low
low
high
high
programmable
programmable
high
Mnemonic
yes
yes
-
yes
yes
-
-
A1·A23
FC2·0
tDS
ADDRESS
AND
lACK
DECODE
PAO·7
PBO·7
PC6/PiAC'K
PC7JfiACK
SCN68000
SCN68230
PC5/PiRO
IPL2
iPi:1
IPLO
LS348
H1
H2
H3
H4
PC41
PC3JTOUT
DMAJ!iEQ
+5V
PC21T1N
PC1
peo
i5'i'ACK
i5'i'ACK
REsET
CLK Vcc Vss
~ ~
Figure 2. PI/T System Block Diagram
4·102
SigneHcs
MICROPROCESSOR DIVISION
JANUARY 1983
PARALLEL INTERFACE/TIMER
GENERAL DESCRIPTION
The PI/T consists of two logically independent sections; the ports and the timer. The
port section consists of port A (PAO-7),
port B (PBO-7), four handshake pins (H1,
H2, H3, and H4), two general I/O pins, and
six dual·function pins. The dual-function
pins can individually operate as a third
port (port C) or an alternate function
related to either ports A and B, or the
timer. The four programmable handshake
pins, depending on the mode, can control
data transfer to and from the ports, or can
be used as interrupt generating inputs, or
I/O pins.
The timer consists of a 24-bit counter,
optionally clocked by a 5-bit prescaler.
Three pins provide complete timer I/O:
PC2/TIN, PC3/TOUT, and PC7IT1ACK. In
specific applications, only the pins
needed for the given configuration per·
form the timer function, while the others
remain port C I/O.
The system bus interface provides for
asynchronous transfer of data from the
PIIT to a bus master over the data bus
(00-07). Data transfer acknowledge
(DTACK), register selects (RS1-RS5), chip
select, the read/write line (RIW), and port
interrupt acknowledge (PlACK) or timer interrupt acknowledge (TIACK) control data
transfer between the PI/T and the
SC68000.
PIN DESCRIPTIONS
00-07
Bidirectional data bus. The data bus pins
DO-D? form an 8-bit bidirectional data bus
to/from the SCN68000 or other bus master. These pins are active high.
RS1-RS5
Register selects. RS1-RS5 are active high,
high-impedance inputs that determine
which of the 25 internal PIIT registers is
being addressed.
RiW
Read/write Input. R/W is the read/write
signal from the SCN68000 or bus master,
indicating whether the current bus cycle
is a read (high) or write (low) cycle.
CS
Chip select input. The CS input selects the
PIIT registers for the current bus cycle.
Address strobe and the data strobe (upper
or lower) of the bus master, along with the
appropriate address bits, must be included in the chip select equation. A low
level corresponds to an asserted chip
select.
SCN68230
OTACK
Data transfer acknowledge output. DTACK
is an active low output that signals the
completion of the bus cycle. During read
or interrupt acknowledge cycles, DTACK
is asserted by the SCN68230 after data
has been provided on the data bus; during
write cycles it is asserted after data has
been accepted at the data bus. Data
transfer acknowledge is compatible with
the SCN68000 and with other bus masters
such as the SCB68430 DMA controller. A
holding resistor is required to maintain
DTACK high between bus cycles.
RESET
Reset input. RESET is used to initialize all
PIIT functions. All control and data direction registers are cleared and most internal operations are disabled by the assertion of RESET (low).
ClK
Clock input. The clock pin is a TTL·
compatible input with the same specifications as the SCN6BOOO. The PIIT contains
dynamic logic throughout, and hence this
clock must not be gated off at any time. It
is not necessary that this clock maintain
any particular phase relationship with the
SCN68000 clock. It can be connected to
an independent frequency source (faster
or slower) as long as all bus specifications
are met.
PAO-PA7 and PBO-PB7
Port A and port B. Ports A and Bare B-bit
ports that can be concatenated to form a
16-bit port in certain modes. The ports can
be controlled in conjunction with the
handshake pins H1-H4. For stabilization
during system power-up, ports A and B
have internal pullup resistors to Vcc. All
port pins are active high.
H1-H4
Handshake pins (110 depending on the
mode and submode). Handshake pins
H1-H4 are multi-purpose pins that (depending on the operational mode) can provide an Interlocked handshake, a pulsed
handshake, an interrupt input (independent of data transfers), or simple 110 pins.
For stabilization during system power-up,
H2 and H4 have internal pullup resistors to
Vcc. Their sense (active high or low) can
be programmed in the port general control
register bits 3-0. Independent of the mode,
the instantaneous level of the handshake
pins can be read from the port status
register.
Port.C
(PCO-PC7/alternate function). This port
can be used as eight general purpose 110
Signetics
pins (PCO-PC?) or any combination of six
special function pins and two general purpose 110 pins (PCO-PC1). (Each dual function pin can be standard 110 or a special
function independent of the other port C
pins.) When used as a port C pin, these
pins are active high. They can be individually programmed as inputs or outputs by the Port C data direction register.
The alternate functions (TIN, TOUT, and
TIACK) are timer 110 pins. TIN can be used
as a rising-edge triggered external clock
input or an external run/halt control pin
(the timer is in the run state if run/halt is
high and in the halt state if run/halt is low).
TOUT can provide an active low timer interrupt request output or a generalpurpose square-wave output, initially high.
TIACK is an active low input used for timer
interrupt acknowledge.
Port A and B functions have an independent pair of active low interrupt request
(PIRQ) and interrupt acknowledge (PlACK)
pins.
The DMAREQ (direct memory access request) pin provides an active low direct
memory access controller (DMAC) request
pulse of three clock cycles.
REGISTER MODEL
A register model that includes the corresponding register selects is shown in
Table 2.
PORT FUNCTIONAL
DESCRIPTION
Port Control Structure
The primary focus of most applications
will be on ports A and B, the handshake
pins, the port interrupt pins, and the DMA
request pin. The ports are controlled by
the port general control register which
contains a 2-bit field that specifies a set of
four operation modes. These govern the
overall operation of the ports and determine their interrelationships. Some
modes require additional information from
each port's control register to further
define its operation. In each port control
register, there is a 2-bit submode field that
serves this purpose. Each port mode/submode combination specifies a set of programmable characteristics that fully
define the behavior of that port and two of
the handshake pins. This structure is summarized in Table 3 and Figure 3.
4-103
4
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68230
PARALLEL INTERFACE/TIMER
7
6
Port Mode
Control
4
5
H12
H34
Enable Enable
2
H3
Sense
Bit
7
Bit
6
Bit
Bit
Bit
6
Bit
7
Bit
7
Bit
6
Bit
5
5
5
H2
Sense
H1
Sense
Port General
Control Register
Port Service
Request Register
Port Interrupt
Priority Control
Interrupt
PFS
SVCRO
Select
*
o
3
H4
Sense
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Port A Data
Direction Register
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Port B Data
Direction Register
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
*
H1
*H1
Interrupt Vector Number
Port C Data
Direction Register
Port Interrupt
Vector Register
Port A
Submode
H2 Control
H2
Int
SVCRO
Enable Enable
Stat
Ctr!.
Port A Control
Register
Port B
Submode
H4 Control
H4
H3
Int
SVCRO
Enable Enable
H3
Stat
Ctrl.
~ort B Control
Register
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Port A Data
Register
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Port B Data
Register
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Port A Alternate
Register
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
Bit
7
H4
Level
Bit
6
H3
Level
Bit
5
H2
Level
Bit
4
H1
Level
Bit
3
Bit
2
Bit
1
Bit
0
H4S
H3S
H2S
H1S
*
*
* TOUTITIACK
*
*
*
Zt)
Control
Bit
6
Ctr!.
Bit
4
*
Bit
7
*
*
*
Bit
5
*
*
*
*
* *
* Clock *
Bit
3
Control
Bit
Bit
2
1
*
*
*
'"
*
*
Timer
Enable
Bit
0
*
Bit
23
Bit
15
Bit
22
Bit
21
Bit
20
Bit
19
Bit
18
Bit
17
Bit
16
Bit
14
Bit
13
Bit
Bit
Bit
Bit
6
Bit
5
Bit
12
Bit
4
Bit
9
Bit
1
Bit
8
Bit
0
7
*
*
*
*
11
10
Bit
3
Bit
2
*
*
*
*
Port B Alternate
Register
Port C Data
Register
Port Status
Register
(nulll
(nulll
Timer Control
Register
Timer Interrupt
Vector Register
(nulll
Counter Preload
Register (Highl
(Midi
(Lowl
(nulll
Bit
23
Bit
22
Bit
21
Bit
20
Bit
19
Bit
18
Bit
17
Bit
16
Count Register
(Highl
Bit
15
Bit
14
Bit
13
Bit
12
Bit
11
Bit
10
Bit
9
Bit
8
(Midi
Bit
8it
6
Bit
5
Bit
4
Bit
3
Bit
2
Bit
1
Bit
0
7
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
* *
*
*
* *
*
*
Signetics
*
*
*
*
*
*
*
*
*
*
*
*
*
ZDS
*
*
*
*
*
(Lowl
Timer Status
Register
(nulll
(nulll
(nulll
(nulll
(nulll
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68230
PARALLEL INTERFACEITIMER
'mn"""·"t
Table 3
PORT MODE CONTROL SUMMARY
Port Generallnlormation and Conventions
Mode 0 (Unidirectional 8-Bit Model
Port A
Submode 00 - Double-Buffered Input
H1
Latches input data
H2 - Status/interrupt generating input, general-purpose
output, or operation with H1 In the interlocked or
pulsed input handshake protocols
Submode 01 - Double-Buffered Output
H1
Indicates data received by peripheral
H2 - Status/interrupt generating input, general-purpose
output, or operation with H1 in the interlocked or
pulsed output handshake protocols
Submode 1X - Bit I/O
H1
Status/interrupt generating Input
H2 -
Status/interrupt generating input or general-purpose
output
Port B, H3 and H4 -
Identical to Port A, Hl and H2
Mode 1 IUnidirectional 16-Bit Model
Port A - Double-Buffered Data IMost significant)
Submode XX (not used)
Hl
Status/interrupt generating input
H2 - Status/interrupt generating input or general-purpose
output
Port B - Double-Buffered Data I Least significant)
Submode XO - Unidirectional 16-Bit Input
H3
Latches input data
H4 - Status/interrupt generating input, general-purpose
output, or operation with H3 in the interlocked or
pulsed input handshake protocols
Submode Xl - Unidirectional 16-Bit Output
H3
Indicates data received by peripheral
H4 - Status/ interrupt generating input, general-purpose
output, or operation with H3 in the interlocked or
pulsed output handshake protocols
Mode 2 (Bidirectional 8-Bit Mode)
Port A - Bit I/O (with no handshaking pins)
Submode XX (not used)
Port B - Bidirectional 8-Bit Data 1D0uble-Buffered)
Submode XX Inot used)
H1
Indicates output data received by peripheral
H2
Operation with Hl in the interlocked or pulsed output
handshake protocols
H3
Latches input data
H4
Operation with H3 in the interlocked or pulsed input
handshake protocols
Mode 3 lBidirectional 16-Bit Mode)
Port A - Double-Buffered Data IMost significant)
Submode XX (not used)
Port B - Double-Buffered Data ILeast significant)
Submode XX (not used)
Hl
Indicates output data received by peripheral
H2
Operation with Hl in the interlocked or pulsed output
handshake protocols
H3
Latches input data
H4
Operation with H3 in the interlocked or pulsed input
handshake protocols
Signetics
The following paragraphs introduce concepts that are generally applicable to the
PI/T ports independent of the chosen
mode and submode. For this reason, no
particular port or handshake pins are mentioned; the notation H1 (H3) indicates that,
depending on the chosen mode and submode, the statement given may be true for
either the H1 or H3 handshake pin.
Unidirectional vs Bidirectional- Figure 3
shows the configuration of ports A and 8
and each of the handshake pins in each
port mode and submode. In modes 0 and
1, a data direction register is associated
with each of the ports. These registers
contain one bit for each port pin to determine whether that pin is an input or an output. Modes 0 and 1 are, thus, called
unidirectional modes because each pin
assumes a constant direction, changeable
only by a reset condition or a programming change. These modes allow double
buffered data transfers in one direction.
This direction, determined by the mode
and submode definition, is known as the
primary direction. Data transfers in the
primary direction are controlled by the
handshake pins. Data transfers not in the
primary direction are generally unrelated,
and single or unbuffered data paths exist.
I n modes 2 and 3 there Is no concept of
primary direction as in modes 0 and 1. Except for port A in mode 2 (bit I/O), the data
direction registers have no effect. These
modes are bidirectional, in that the direction of each transfer (always 8 or 16 bits,
double buffered) is determined dynamically by the state of the handshake pins.
Thus, for example, data may be transferred out of the ports, followed very shortly
by a transfer into the same port pins.
Transfers to and from the ports are independent and may occur in any sequence. Since the instantaneous direction
is always determined by the external
system, a small amount of arbitration
logic may be required.
Control 01 Double Buffered Data Paths-
Generally speaking, the PI/T is a double
buffered device. In the primary direction,
double buffering allows orderly transfers
by using the handshake pins in any of
several programmable protocols. (When
bit I/O Is used, double buffering is not
available and the handshake pins are used
as outputs or status/interrupt inputs.)
4·105
4
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68230
PARALLEL INTERFACE/TIMER
'm",,",i_'"
MODE 0 SUBMODE 1X
MODE 0 SUBMODE 01
MODE 0 SUBMODE 00
___
~
A (B)
DOUBLE.BU:FERED
OUTPUT
BIT 1/0
Hl(H3)
H2(H4)
MODE 1 PORT B SUBMODE XO
A!B)
Hl(H3)
H2(H4)
MODE 1 PORT B SUBMODE Xl
Hl
Hl
H2
AAND B
(16)
H3
H4
MODE2
<=>
<=>
MODE3
A(8)
~AANDB
'\r/
BIDIRECTIONAL 16 BIT
B(8)
-
H3}--INPUT
H4
TRANSFERS
H1)-OUTPUT
H2
TRANSFERS
H3)-INPUT
' -...~- H4
TRANSFERS
Figure 3. Port Mode Layout
Use of double buffering is most beneficial
in situations where a peripheral device
and the computer system are capable of
transferring data at roughly the same
speed. Double buffering allows the fetch
operation of the data transmitter to be
overlapped with the store operation of the
data receiver. Thus, throughput measured
In bytes or words per second can be great·
Iy enhanced. If there is a large mismatch
in transfer capability between the com·
puter and the peripheral, little or no
benefit is obtained. In these cases there Is
no penalty in using double buffering.
Double Buffered Input Transfers-In all
modes, the PIIT supports double buffered
input transfers. Data that meets the port
setup and hold times Is latched on the
asserted edge of H1(H3). H1(H3) is edge
sensitive, and may assume any duty cycle
as long as both high and low minimum
4·106
3. H2(H4) may be a general purpose out·
put pin that Is always asserted. The
H2S(H4S) status bit Is always o.
4. H2(H4) may be an output pin in the interlocked Input handshake protocol. It
is asserted when the port input latches
are ready to accept new data. It is
negated asynchronously following the
asserted edge of the H1(H3) input. As
soon as the Input latches become
ready, H2(H4) is again asserted. When
the input double buffered latches are
full, H2(H4) remains negated until data
is removed. Thus, anytime the H2(H4)
output is asserted, new input data may
be entered by asserting H1(H3). At
other times, transitions on H1(H3) are
ignored. The H2S(H4S) status bit Is
always O. When H12 enable (H34
enable) is 0, H2(H4) is held negated.
(16)
BIT 1/0
BIDIRECTIONAL 8 BIT
2. H2(H4) may be a general purpose out·
put pin that is always negated. The
H2S(H4S) status bit is always O.
5. H2(H4) may be an output pin in the
pulsed Input handshake protocol. It is
asserted exactly as In the Interlocked
input protocol, but never remains
asserted longer than 4 clock cycles.
Typically, a four clock cycle pulse is
generated. But in the case where a
subsequent H1(H3) asserted edge occurs before termination of the pulse,
H2(H4) is negated asynchronously.
Thus, anytime after the leading edge of
the H2(H4) pulse, new data can be
entered In the PlfT double bllffered input latches. The H2S(H4S) status bit is
always O. When H12 enable (H34
enable) is 0, H2(H4) is held negated.
times are observed. The PlfT contains a
port status register whose H1S(H3S)
status bit is set anytime any input data is
present in the double buffered latches
that has not been read by the bus master.
The action of H2(H4) is programmable; it
may indicate whether there is room for
more data in the PI/T latches or it may
serve other purposes. The following options are available, depending on the
mode.
A sample timing diagram Is shown in
Figure 4. The H2(H4) Interlocked and
pulsed input handshake protocols are
shown. The DMAREQ pin is also shown
assuming it is enabled. All handshake pin
sense bits are assumed to be 0 (refer to
Port General Control Register); thus, the
pins are in the low state when asserted.
Due to the great similarity between
modes, this timing diagram Is applicable
to all double buffered input transfers.
1. H2(H4) may be an edge sensitive input
that is independent of H1(H3) and the
transfer of port data. On the asserted
edge of H2(H4), the H2S(H4S) status bit
is set. It is cleared by the direct method
(refer to Direct Method of Resetting
Status), the RESET pin being asserted,
or when the H12 enable (H34 enable) bit
of the port general control register is O.
Double Buffered Output Transfers- The
PlfT supports double buffered output
transfers in all modes. Data, written by the
bus master to the PlfT, is stored In the
port's output latch. The peripheral accepts
the data by asserting H1(H3), which
causes the next data to be moved to the
port's output latch as soon as it is
available. The function of H2(H4) is programmable; it may indicate whether new
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68230
PARALLEL INTERFACE/TIMER
'W""lIel.",
READ
READ
PORT DATA
H1(H3)
H2(H4) INTERLOCKED
H2(H4) PULSE
4
Figure 4. Double Buffered Input Transfers
data has been moved to the output latch
or it may serve other purposes. The
H1S(H3S) status bit may be programmed
for two interpretations. Normally the
status bit is a 1 when there Is at least one
latch In the double buffered data path that
can accept new data. After writing one
byte/word of data to the ports, an interrupt
service routine could check this bit to
determine If It could store another
byte/word; thus, filling both latches. When
the bus master is finished, it is often
useful to be able to check whether all of
the data has been transferred to the
peripheral. The H 1S(H3S) status control
bit of the port A and B control registers
provide this flexibility. The programmable
options of the H2(H4) pin are given below,
depending on the mode.
1. H2(H4) may be an edge sensitive input
pin independent of H1(H3) and the
transfer of port data.. On the asserted
edge of H2(H4), the H2S (H4S) status
bit is set. It Is reset by the direct
method (refer to Direct Method of
Resetting Status), the RESET pin being
asserted, or when the H12 enable (H34
enable) bit of the port general control
register is O.
4. H2(H4) may be an output pin In the In·
terlocked output handshake protocol.
H2(H4) is asserted two clock cycles
after data is transferred to the double
buffered output latches. The data reo
mains stable and H2(H4) remains as·
serted until the next asserted edge of
the H1(H3) Input. At that time, H2(H4) is
asynchronously negated. As soon as
the next data is available, it Is trans·
ferred to the output latches. When
H2(H4) is negated, asserted transitions
on H1(H3) have no effect on the data
paths. As is explained later, however,
in modes 2 and 3 they do control the
three·state output buffers of the
bidirectional portIs). The H2S(H4S)
status bit is always O. When H 12 enable
(H34 enable) is 0, H2(H4) is held
negated.
2. H2(H4) may be a general purpose out·
put pin that Is always negated. The
H2S(H4S) status bit is always O.
5. H2(H4) may be an output pin in the
pulsed output handshake protocol. It is
asserted exactly as in the interlocked
output protocol above, but never reo
mains asserted longer than four clock
cycles. Typically, a four clock pulse is
generated. But in the case where a sub·
sequent H1(H3) asserted edge occurs
before termination of the pulse, H2(H4)
is negated asynchronously shortening
the pulse. The H2S(H4S) status bit is
always O. When H12 enable (H34
enable) is 0, H2(H4) is held negated.
3. H2(H4) may be a general purpose out·
put pin that is always asserted. The
H2S(H4S) status bit Is always O.
A sample timing diagram Is shown in
Figure 5. The H2(H4) interlocked and
pulsed output handshake protocols are
Signetics
shown. The DMAREQ pin is also shown
assuming it Is enabled. All handshake pin
sense bits are assumed to be 0; thus, the
pins are in the low state when asserted.
Due to the great similarity between
modes, this timing diagram is applicable
to all double buffered output transfers.
Requesting Bus Master Servlce- The PI/T
has several means of indicating a need for
service by a bus master. First, the pro·
cessor may poll the port status register. It
contains a status bit for each handshake
pin, plus a level bit that always reflects the
instantaneous state of that handshake
pin. A status bit is 1 when the PI/T needs
serviCing, i.e., generally when the bus
master needs to read or write data to the
ports, or when a handshake pin used as a
simple status input has been asserted.
The interpretation of these bits is depen·
dent on the chosen mode and submode.
Second, the PI/T may be placed in the pro·
cessor's interrupt structure. As mention·
ed previously, the PI/T contains port A and
B control registers that configure the
handshake pins. Other bits in these
registers enable an interrupt associated
with each handshake pin. This interrupt is
made available through the PC5/PIRQ pin,
if the PIRQ function is selected. Three ad·
ditional conditions are required for PIRQ
to be asserted: (1) the handshake pin
status bit is set, (2) the corresponding in·
terrupt (service request) enable bit is set,
and (3) DMA requests are not associated
with that data transfer (H1 and H3 only).
4·107
JANUARY 1983
MICROPROCESSOR DIVISION
PARALLEL INTERFACE/TIMER
SCN68230
'm",,",'··',
WRITE
WRITE
-t________
PORT
DATA::::~~::::~~__~________
-;::::~:::::;
____________________;::::::
H2(H4) INTERLOCKED
H2(H4) PULSE
Hl(H3)
Figure 5. Double Buffered Output Transfers
The conditions from each of the four handshake pins and corresponding status bits
are ORed to determine PIRQ_
The third method of requesting service is
via the PC4/DMAREQ pin_ This pin can be
associated with double buffered transfers
in each mode_ If It Is used as a DMA controller request, It can initiate requests to
keep the PIiT's Input/output double buffering empty/full as much as possible_ It will
not overrun the OMA controller_
Vectored, Prioritized Port Interrupts - Use
of SCN6S000 compatible vectored interrupts with the PI/T requires the PIRQ and
PlACK pins_ When PlACK is asserted, the
PI/T places an S-blt vector on the data pins
00-07_ Under normal conditions, this vector corresponds to highest priority,
enabled, active port Interrupt source with
which the OMAREQ pin is not currently
associated_ The most significant six bits
are provided by the port Interrupt vector
register (PIVR), with the lower two bits
supplied by prioritization logic according
to conditions present when PlACK is
asserted_ It Is important to note that the
only effect on the PI/T caused by Interrupt
acknowledge cycles is that the vector is
placed on the data bus_ Specifically, no
registers, data, status, or other Internal
states of the PI/T are affected by the cycle_
Several conditions may be present when
the PlACK input is asserted_ These conditions affect the PI/T's response and the
termination of the bus cycle_ If the PI/T
has no interrupt function selected, or is
4·108
not asserting PIRQ, the PI/T will make no
response to PlACK (OTACK will not be
asserted)_ If the PI/T Is asserting PIRQ
when PlACK is received, the PI/T will output the contents of the PIVR and the
prioritization bits_ If the PIVR has not been
intialized, $OF will be read from this
register_ These conditions are summarized in Table 4.
The vector table entries for the PI/T appear
as a contiguous block of four vector
numbers whose common upper six bits
are programmed in the PIVR. The following list pairs each interrupt source with
the 2-blt value provided by the prioritization logic, when interrupt acknowledge is
asserted.
H1
H2
H3
H4
source-DO
source-01
source-10
source-11
Autovectored Port Interrupts-Autovectored interrupts use only the PIRQ pin.
The operation of the PIIT with vectored
and autovectored Interrupts Is Identical
Table 4
except that no vectors are supplied and
the PCB/PlACK pin can be used as a port C
pin.
Direct Method of Resetting Status-In
certain modes one or more handshake
pins can be used as edge sensitive Inputs
for the sole purpose of setting bits in the
port status register_ These bits consist of
simple flip flops. They are set (to 1) by the
occurrence of the asserted edge of the
handshake pin input. Resetting a hand·
shake status bit can be done by writing an
S-bit mask to the port status register. This
is called the direct method of resetting. To
reset a status bit that is resettable by the
direct method, the mask must contain a 1
in the bit position of the port status
register corresponding to the desired bit.
Other positions must contain O's. For
status bits that are not resettable by the
direct method In the chosen mode, the
data written to the port status register has
no effect. For status bits that are resettable by the direct method In the chosen
mode, a 0 in the mask has no effect.
Handshake Pin Sense Control- The PI/T
contains exclusive OR gates to control the
RESPONSE TO PORT INTERRUPT ACKNOWLEDGE
Conditions
P)RQ negated OR interrupt
request function not selected
PIVR has not been initialized
since RESET
No response from PIIT.
No DTACK.
PIRQ asserted
PIIT provides $OF. the
Uninitlalized Vector. *
PIVR has been initialized
since RESET
No response from PIIT.
No DTACK.
PIIT provides PIVR contents
with prioritization bits.
*The uninitialized vector is the value returned from an interrupt vector register before it has
been ·initialized.
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
PARALLEL INTERFACE/TIMER
SCN68230
'm""II"·'tA
sense of each of the handshake pins,
whether used as inputs or outputs. Four
bits in the port general control register
can be programmed to determine whether
the pins are asserted in the low or high
voltage state. As with other control
registers, these bits are reset to 0 when
the RESET pin is asserted, defaulting the
asserted level to be low.
EnabUng Ports A and B-Certaln func·
tions Involved with double buffered data
transfers, the handshake pins, and the
status bits, can be disabled by the external system or by the programmer during
initialization. The port general control
register contains two bits, H12 enable and
H34 enable, which control these functions. These bits are cleared to the 0 state
when the RESET pin is asserted, and the
functions are disabled. The functions are
the following:
1. Independent of other actions by the
bus master or peripheral (via the handshake pins), the PIIT's disabled handshake controller is held to the 'empty'
state, i.e., no data is present in the double buffered data path.
2. When any handshake pin is used to set
a simple status flip flop, unrelated to
double buffered transfers, these flip
flops are held reset to 0 (see Table 3).
3. When H2(H4) is used in an interlocked
or pulsed handshake with H1(H3),
H2(H4) is held negated, regardless of
the chosen mode, submode, and
primary direction. Thus, for double buffered Input transfers, the programmer
can signal a peripheral when the PIIT is
ready to begin transfers by setting the
associated handshake enable bit to 1.
The Port A and B Allernale Registers-In
addition to the port A and B data registers,
the PIIT contains port A and B alternate
registers. These registers are read only,
and simply provide the Instantaneous
level of each port pin. They have no effect
on the operation of the handshake pins,
double buffered transfers, status bits, or
any other aspect of the PIIT, and they are
mode/submode independent.
PORT MODES
Mode 0- Unidirectional 8-BII Mode
In mode 0, ports A and B operate independently. Each can be configured in
any of Its three possible submodes:
Submode OO-Double buffered input
Submode 01- Double buffered output
Submode 1X-Blt I/O
Handshake pins H1 and H2 are associated
with port A and configured by programming the port A control register. (The H12
enable bit of the port general control
register enables port A transfers.) Handshake pins H3 and H4 are associated with
port B and configured by programming the
port B control register. (The H34 enable bit
of the port general control register
enables port B transfers.) The port A and B
data direction registers operate in all three
submodes. Along with the submode, they
affect the data read and written at the
associated data register according to
Table 5. They also enable the output buffer
associated with each port pin. The
DMAREQ pin may be associated with
either (not both) port A or port B, but does
not function if the bit I/O submode is programmed for the chosen port.
Port A or B Submode 00 (8-BII Double Buffered Inpull-In mode 0, double buffered
input transfers of up to a-bits are available
by programming submode 00 In the
desired port's control register. The operation of H2 and H4 can be selected by programming the port A and port B control
registers, respectively. All five double buffered input handshake options, previously
mentioned in the Port General Information
and Conventions section, are available.
wanted read cycles. Refer to Figure 4 for a
sample timing diagram.
MODE 0 SUBMODE 00
Pori A or B Submode 01 (8-bll Double Buffered Oulpul)-In mode 0, double buffered output transfers of up to a bits are
available by programming submode 01 In
the desired port's control register. The
operation of H2 and H4 can be selected by
programming the port A and port B control
registers, respectively. All five double buffered output handshake options, previously mentioned in the Port General Information and Conventions section, are
available.
For pins used as Inputs, data written to
the associated data register is double buffered and passed to the initial or final output latch, as usual, but the output buffer is
disabled. Refer to Figure 5 for a sample
timing diagram.
For pins used as outputs, the data path
consists of a single latch driving the output buffer. Data written to the port's data
register does not affect the operation of
any handshake pin, status bit, or any other
aspect of the PIIT. Output pins can be
used Independently of the input transfer.
However, read bus cycles to the data
register do remove data from the port.
Therefore, care should be taken to avoid
processor instructions that perform un-
Table 5
--
MODE 0 SUBMODE 01
A (B)
8
DOUBLE·BUFFERED
OUTPUT
H1(H3)
H2(H4)
MODE 0 PORT DATA PATHS
Mode
Read Port AI B
Data Register
DDR-O
DDR-1
FIL.D.B.
FOL Note 3
Pin
FOL Note 3
Pin
FOL Note 3
Write Port AI B
Data Register
DDR-X
FOL. S.B.
Note 1
IOL/FOL. D.B.
Note 2
FOL. S.B.
Note 1
o Submode 00
o Submode 01
o Submode 1X
Abbreviations:
S.B. - Single Buffered
IOL - Initial Output Latch
FOL - Final Output Latch
D.B. - Double Buffered
DDR - Data Direction Register
FI L - Final Input Latch
Note 1: Data is latched in the output data registers (final output latch) and will be
single buffered at the pin if the DDR is 1. The output buffers will be turned
off if the DDR is O.
Note 2: Data is latched in the double-buffered output data registers. The data in the
final output latch will appear on the port pin if the DDR is a 1.
Note 3: The output drivers that connect the final output latch to the pins are turned
on.
Signetics
4·109
4
JANUARY 1983
MICROPROCESSOR DIVISION
PARALLEL INTERFACE/TIMER
SCN68230
'm""Iui_iri
Pori A or B Submode 1X (BII 1/0)-1 n mode
0, simple bit I/O is available by programming submode 1X In the desired port's
control register. This subrhode Is intended
for applications In which several Independent devices must be controlled or
monitored. Data written to the associated
data register is single buffered. If the data
direction register bit for that pin is a 1 (output), the output buffer is enabled. If it is 0
(input), data written is still latched, but is
not available at the pin. Data read from the
data register Is the instantaneous value of
the pin or what was written to the data
register, depending on the contents of the
data direction register. H1(H3) is an edge
sensitive status input pin only and it controls no data related function. The
H1S(H3S) status bit is set following the
asserted edge of the input waveform. It Is
reset by the direct method, the RESET pin
being asserted, or when the H12 enable
(H34 enable) bit is O.
H2(H4) can be programmed as a simple
status input (identical to H1(H3)), or as an
asserted or negated output. The interlocked or pulsed handshake configurations are not available.
MODE 0 SUBMODE IX
A (B)
8
HI (H3)
H2 (H4)
Mode 1-UnldirectionaI16-Bil Mode
In mode 1, ports A and B are concatenated
to form a single 16-bit port. The port B submode field controls the configuration of
both parts, The possible submodes are:
Port B submode XO-double buffered
input
Port B submode X1-double buffered
output
Handshake pins H3 and H4, configured by
programming the port B control register,
are associated with the 16-blt double buffered transfer. These 16-bit transfers are
enabled by the H34 enable bit of the port
general control register. Handshake pins
H1 and H2 can be used as simple status
inputs not related to the 16-bit data
transfer or H2 can be an output. Enabling
of the H1 and H2 handshake pins is done
by the H12 enable bit of the port general
control register. The port A and B data
4·110
direction registers operate in each submode. Along with the submode, they affect the data read and written at the data
register according to Table 6. They also
enable the output buffer associated with
each port pin. The DMAREQ pin can be
associated only with H3.
Mode 1 can provide convenient, high
speed 16-bit transfers. The port A and B
data registers are addressed for compatibility with the SCN68000 move peripheral
(MOVEP) instruction and with the S68000
DMA controllers. To take advantage of
this, port A should contain the most
significant byte of data and always be read
or written by the bus master first. The interlocked and pu Ised handshake protocols are keyed to accesses to the port B
data register in mode 1. If it is accessed
last, the 16-bit double buffered transfers
proceed smoothly.
Pori B SubmodeXO (16-BII Double Buffered Inpul)-In mode 1 port B submode
XO, double buffered input transfers of up
to 16-bits can be obtained. The level of all
16 pins is asynchronously latched with the
asserted edge of H3. The processor can
check the H3S status bit to determine if
new data is present. The DMAREQ pin can
be used to signal a DMA controller to
empty the input buffers. Regardless of the
bus master, port A data should be read
first. (Actually, port A data need not be
read at all.) Port B data should be read last.
The operation of the internal handshake
controller, the H3S bit, and DMAREQ are
keyed to the reading of the port B data
register. (The S68000 DMA controllers can
be programmed to perform the exact
Table 6
transfers needed for compatibility with
the PIIT.) H4 can be programmed for all
five of the handshake options mentioned
in the Port General Information and Conventions section.
For pins used as outputs, the data path
consists of a single latch driving the output buffer. Data written to the port's data
register does not affect the operation of
any handshake pin, status bit, or any other
aspect of the PIIT. Thus, 'output pins can
be used independently of the Input
transfer. However, read bus cycles to the
port B data register do remove data, so
care should be taken to avoid unwanted
read cycles.
MODE 1 PORT B SUBMODE XO
HI
H3
,--..-~~H4
Pori B Submode X1 (16·Bil Double Buffered Oulpul)- Refer to Figure 4 for a sample.timing diagram. In mode 1 port B submode X1, double buffered output transfers
of up to 16 bits can be obtained. Data is
written by the bus master (processor or
DMA controller) in two bytes. The first
byte (most significant) is written to the
port A data register. It is stored in a temporary latch until the next byte is written
to the port B data register. Then all 16 bits
are transferred to the final output latches
MODE 1 PORT DATA PATHS
Write Port AI B
Register
DDR-O
DDR-1
FOl, S.B.
1, Port B
FOl. S.B.
Submode XO
Note 2
Note 2
1. Port B
IOUFOl,
IOUFOl,
D.B.,
Submode Xl
D.B ..
Note 1
Note 1
Note 1: Data written to Port A goes to a temporary latch. When the Port B data
register is later written, Port A data is transferred to IOUFOl.
Note 2: Data is latched in the output data registers (final output latch) and will be
single buffered at the pin if the DDR is 1 The output buffers will be turned
off if the DDR is O.
Note 3: The output drivers that connect the final output latch to the pins are turned
on.
Abbreviations:
IOl - Initial Output latch
S. B. - Single Buffered
FOl - Final Output latch
D.B. - Double Buffered
Fil - Final Input latch
DDR - Data Direction Reg,ister
Mode
Read Port AlB
Register
DDR-O
DDR-1
Fll, D.B.
FOl
Note 3
Pin
FOl
Note 3
SigneHcs
MICROPROCESSOR DIVISION
JANUARY 1963
SCN68230
PARALLEL INTERFACEITIMER
'm",,""-·"
of ports A and 8. 80th options for inter·
pretation of the H3S status bit, mentioned
in Port General Information and Com·
ments section, are available and apply to
the 16·bit port as a whole. The DMAREQ
pin can be used to signal a DMA controller
to transfer another word to the port output
latches. (The S66000 DMA controllers can
be programmed to perform the exact
transfers needed for compatibility with
the PI/T.) H4 can be programmed for all
five of the handshake options mentioned
in the Port General Information and Con·
ventions section.
For pins used as inputs, data written to
either data register is double buffered and
passed to the initial or final output latch,
as usual, but the output buffer is disabled.
Refer to Figure 5 for a sample timing
diagram.
MODE I PORT B SUBMODE XI
_ _ HI
H2
H3
H4
Mode 2-Bldirectional 8·Bit Mode
In mode 2, port A is used for simple bit 1/0
with no associated handshake pins. Port 8
is used for bidirectional 6·bit double buf·
fered transfers. H1 and H2, enabled by the
H12 enable bit in the port general control
register, control output transfers, while
H3 and H4, enabled by the port general
control register H34 enable bit, control in·
put transfers. The instantaneous direction
of the data is determined by the H1 hand·
shake pin. The port 8 data direction
register is not used. The port A and port 8
submode fields do not affect the PIIT
operation in mode 2.
MODE 2
Double Bullered 110 (Port B)-The only
aspect of bidirectional double buffered
transfers that differs from the unidirec·
tional modes lies in controlling the port 8
output buffers. They are controlled by the
level of H1. When H1 is negated, the port 8
output buffers (all eight) are enabled and
the pins drive the bidirectional bus.
Generally, H1 is negated in response to an
asserted H2 which indicates that new out·
put data is present in the double buffered
latches. Following acceptance of the data,
the peripheral asserts H1 disabling the
port 8 output buffers. Other than con·
trolling the output buffer, H1 is edge sen·
sitive as in other modes. Input transfers
proceed identically to the double buffered
input protocol described in the Port Gen·
eral I nformation and Conventions Section.
In mode 2, only the interlocked and pulsed
handshake pin options are available on H2
and H4. The DMAREQ pin can be associ·
ated with either input transfers (H3) or out·
put transfers (H1), but not both. Refer to
Table 7 for a summary of the port 8 data
register responses in mode 2.
Bit 110 (Port A)-In mode 2, port A performs
simple bit 1/0 with no associated hand·
shake pins. This configuration is intended
for applications in which several indepen·
dent devices must be controlled or
monitored. Data written to the port A data
register is single buffered. If the port A
data direction register bit for that pin is 1
(output), the output buffer is enabled. If it
is 0, data written is still latched but not
available at the pin. Data read from the
data register is either the instantaneous
value of the pin or what was written to the
Table 7
Mode 3-BidirectionaI16·BIt Double Buf·
fered 110
I n mode 3, ports A and 8 are used for
bidirectional 16·bit double buffered
transfers. H1 and H2 control output
transfers, while H3 and H4 control input
transfers. (H1 and H2 are enabled by the
H12 enable bit while H3 and H4 are
enabled by the H34 enable bit of the port
general control register.) The instan·
taneous direction of the data is deter·
mined by the H1 handshake pin, and thus,
the data direction registers are not used.
The port A and port 8 submode fields do
not affect PIIT operation in mode 3.
The only aspect of bidirectional double
buffered transfers that differs from the
unidirectional modes lies in controlling
the port A and 8 output buffers. They are
controlled by the level of H1. When H1 is
negated, the output buffers (all 16) are
enabled and the pins drive the bidirec·
tional bus. Generally, H1 is negated In
response to an asserted H2, which in·
dicates that new output data is present in
the double buffered latches. Following ac·
ceptance of the data, the peripheral
asserts H1, disabling the output buffers.
Other than controlling the output buffers,
H1 is edge sensitive as in other modes. In·
put transfers proceed identically to the
double buffered input protocol described
in the Port General information and Con·
ventions section. Port A and 8 data is
latched with the asserted edge of H3. In
MODE 2 PORT B DATA PATHS
Mode
Read Port B
Data Register
Write Port B
Data Register
2
FIL. D.B.
IOLIFOL. D.B.
Abbreviations:
IOL - Initial Output Latch
FOL - Final Output Latch
FI L - Final Input Latch
W
data register, depending on the contents
of the port A data direction register. This
is summarized in table 6.
D. B. - Double Buffered
A (8)
B)T )/0
\=)B(8)
Table 8
MODE 2 PORT A DATA PATHS
Mode
2
HIL.
OUTPUT
H2r-- TRANSFERS
H 3 ) - )NPUT
L-...r--- H4·
TRANSFERS
Read Port A
Data Register
DDR-O
I DDR-1
Pin
I FOL
Write Port A
Data Register
DDR-1
DDR-O I
FOL
I FOL. S.B.
Abbreviations:
S.B. - Single Buffered
FOL - Final Output Latch
DDR - Data Direction Register
Signetics
4·111
4
MICROPROCESSOR DIVISION
JANUARY 1983
PARALLEL INTERFACE/TIMER
SCN68230
':nsJ""line"i
mode 3, only the interlocked and pulsed
handshake pin options are available to H2
and H4. The DMAREQ pin can be associated with either Input transfers (H3) or output transfers (H1), but not both. H2 Indicates when new data is available in the
port B (and implicitly port A) output
latches, but unless the buffer Is enabled
by H1, the data is not driving the pins.
Mode 3 can provide convenient high speed
16·bit transfers. The port A and B data
registers are addressed for compatibility
with the SCN68000's move peripheral
(MOVEP) instruction and with the S68000
DMA controllers. To take advantage of
this, port A should contain the most significant data and always be read or written
by the bus master first. The interlocked
and pulsed handshake protocols are
keyed to accesses to the port B data regis·
ter in mode 3. If it is accessed last, the
16·bit double buffered transfer proceeds
smoothly. Refer to Table 9 for a summary
of the port A and B data paths In mode 3.
Table 9
MODE 3 PORT A AND B DATA PATHS
II
DATA IN OUTPUT LATCHES
~~~
BUSiRITE
(18)
BIDIRECTIONAL 18·BIT
NO DMA fQUEST
DMA REQUEST
MODE 3
~AANDB
'\r-/
II
Write Port A and B
Read Port A and B
Data Register
Data Register
IOL/FOL. D.B .. Note 1
FIL, D.B.
3
Note 1: Data written to Port A goes to a temporary latch. When the Port B data
register is later written, Port A data is transferred to lOLl FOL.
Abbreviations:
IOL - Initial Output Latch
S.B. - Single Buffered
D.B. - Double Buffered
FOL - Final Output Latch
FIL - Final Input Latch
Mode
PERIPHERAL ACCEPTS DATA
>~<
BUS WRITE
~
DMA REQUEST
t
"-"~e::::::-~'~~"
Figure 6. DMAREQ Associated with Output Transfers
DMA REQUEST OPERATION
The direct memory access request
(DMAREQ) pulse (when enabled) is
associated with output or input transfers
to keep the Initial and final output latches
full or empty, respectively. Figures 6 and 7
show all the possible paths in generating
DMA requests.
DMAREQ is generated on the bus side of
the SCN68230 by the synchronized 1 chip
select. If the conditions of Figures 6 and 7
are met, an access of the bus (assertion of
CS) will cause DMAREQ to be asserted
three PlfT clocks (plus the delay time from
the clock edge) after CS is synchronized.
DMAREQ remains asserted for three clock
cycles (plus the delay time from the clock
edge) and is then negated.
1Synchronized means that the Input signal has been
seen by the PlfT on the appropriate edge of the clock
(rising edge for Hl(H3) and failing edge for CS). (Refer to
the Bus Interface section for the exception concerning
es.) If a bus access (assertion of CS) and a port access
(assertion of H1(H3)) occur at the same time, CS will be
recognized without delay. H1(H3) will be recognized one
DATA IN INPUT LATCHES
~~~
PERIPHERAL PROVIDES DATA
~
t
'O">~-<"~'
PERIPHERAL 10VIDES DATA
DMA REtUEST
'''O"~~-'"~'
Figure 7. DMAREQ AssOCiated with Input Transfers
clock cycle later.
4·112
NO DMA REQUEST
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68230
PARALLEL INTERFACE/TIMER
'm""''''·''t
The OMAREQ pulse associated with a
peripheral or port side of the PI/T is
caused by the synchronized Hl(H3) input.
If the conditions of figures 6 and 7 are
met, a port access (assertion of the Hl(H3)
input) will cause OMAREQ to be asserted
2.5 PI/T clock cycles (plus the delay time
from clock edge) after Hl(H3) is syn·
chronized. OMAREQ remains asserted for
three clock cycles (plus the delay time
from the clock edge) and is then negated.
TIMER
The SCN6S230 timer can provide several
facilities needed by S68000 operating
systems. It can generate periodic inter·
rupts, a square wave, or a single interrupt
after a programmed time period. Also, it
can be used for elapsed time measure·
ment or as a device watchdog.
The PI/T timer contains a 24·bit syn·
chronous down counter that is loaded
from three S·blt counter preload registers.
The 24·bit counter can be clocked by the
output of a 5·bit (divide by 32) prescaler or
by an external timer input TIN. If the
prescaler is used, it can be clocked by the
system clock (ClK pin) or by the TIN exter·
nal Input. The counter signals the occur·
rence of an event primarily through zero
detection. (A zero Is when the value of the
24·bit timer is equal to zero.) This sets the
zero detect status (ZOS) bit in the timer
status register. It can be checked by the
processor or can be used to generate a
timer interrupt. The ZOS bit is reset by
writing a 1 to the timer status register in
that bit position.
The general operation of the timer is flexi·
ble and easily programmable. The timer is
fully configured and controlled by pro·
gramming the S·bit timer control register.
It controls the choice between the port C
operation and the timer operation of three
timer pins, whether the counter is loaded
from the counter preload register or rolls
over when zero detect is reached, the
clock input, whether the prescaler is used,
and whether the timer is enabled.
Run/Halt Definition
The overall operation of the timer is
described In terms of the run or halt
states. The control of the current state is
determined by programming the timer
control register. When In the halt state, all
of the following occur:
1. The prior contents of the counter is not
altered and is reliably readable via the
count registers.
2. The prescaler is forced to $1 F whether
or not It is used.
3. The ZOS status bit is forced to 0,
regardless of the possible zero con·
tents of the 24·bit counter.
The run state is characterized by:
1. The counter is clocked by the source
programmed in the timer control
register.
2. The counter is not reliably readable.
3. The prescaler is allowed to decrement
if programmed for use.
4. The ZOS status bit is set when the
24·bit counter transitions from $000001
to $000000.
Timer Rules
This following set of rules allow easy ap·
plication of the timer.
1. Refer to the run/halt definition above.
2. When the RESET pin is asserted, all
bits of the timer control register go to
0, configuring the dual function pins as
port C inputs.
3. The contents of the counter preload
registers and counter are not affected
by the RESET pin.
4. The count registers provide a direct
read data path from each portion of the
24·bit counter, but data written to their
addresses is ignored. (This results in a
normal bus cycle.) These registers are
readable at any time, but their contents
are never latched. Unreliable data may
be read when the timer is in the run
state.
5. The counter preload registers are
readable and writable at any time and
this occurs independently of any timer
operation. No protection mechanisms
are provided against ill·timed writes.
6. The input frequency to the 24·bit
counter from the TIN pin or prescaler
output must be between 0 and the in·
put frequency at the ClK pin divided by
32 regardless of the configuration
chosen.
7. For configurations in which the
prescaler is used (with the ClK pin or
TIN pin as an input), the contents of the
Table 10
counter preload register (CPR) is
transferred to the counter the first time
that the prescaler passes from $00 to
$1 F (rolls over) after entering the run
state. Thereafter, the counter
decrements or is loaded from the
counter preload register when the
prescaler rolls over.
S. For configurations in which the
prescaler is not used, the contents of
the counter preload registers are
transferred to the counter on the first
asserted edge of the TIN input after
entering the run state. On subsequent
asserted edges the counter
decrements or is loaded from the
counter preload registers.
9. The lowest value allowed In the counter
preload register for use with the
counter is $000001.
Timer Interrupt Acknowledge Cycles
Several conditions can be present when
the timer interrupt acknowledge pin
(TIACK) is asserted. These conditions af·
fect the PIIT's response and the termina·
tion of the bus cycle (see Table 10).
PROGRAMMER'S MODEL
The internal accessible register organiza·
tion is represented in Table 11. Address
space within the address map is reserved
for future expansion. Throughout the PI/T
data sheet, the following conventions are
maintained.
1. A read from a reserved location in the
map results in a read from the 'null
register'. The null register returns all
zeros for data and results in a normal
bus cycle. A write to one of these loca·
tions results in a normal bus cycle but
no write occurs.
2. Unused bits of a defined register are
denoted by'·' and are read as zeros.
3. Bits that are unused in the chosen
mode/submode but are used in others,
are denoted by 'X', and are readable
and writable. Their content, however, is
ignored in the chosen modelsubmode.
RESPONSE TO TIMER INTERRUPT ACKNOWLEDGE
PC3ITOUT Function
PC3 - Port C Pin
TOUT - Square Wave
TOUT Interrupt
TOUT Interrupt
Negated Timer
Request
Asserted Timer
Request
Signetics
Response to Asserted TIACK
No response.
No
No
No
No
No
DTACK.
response.
DTACK.
response.
DTACK
Timer Interrupt Vector Contents
DT ACK Asserted.
4·113
4
MICROPROCESSOR DIVISION
JANUARY 1983
PARALLEL INTERFACE/TIMER
SCN68230
'm""II,I.lli
Table 11
PI/T REGISTER ADDRESSING ASSIGNMENTS
5
Port A Data Register IPADRI
a
a
a
a
a
a
a
a
a
Port 8 Data Reqister IPBDRI
0
Port A Alternate Register IPAARI
Port 8 Alternate Reqister IPBARI
a
Port General Control Register IPGCRI
Port Service Request Register IPSRRI
Port A Data Direction Register IPADDRI
Port 8 Data Direction Register IPBDDRI
Port C Data Direction Register IPCDDRI
Port Interrupt Vector Register IPIVRI
Port A Control Register IPACRI
Port 8 Control Reqister IPBCRI
a
a
a
a
a
a
a
a
a
Port Status Register IPSRI
Timer Control Register ITCRI
0
1
1
1
1
1
1
1
1
1
Timer Interrupt Vector Reqister ITIVRI
Counter Preload Register High ICPRHI
Counter Preload Register Middle ICPRMI
Counter Preload Register Low ICPRLI
Count Register High ICNTRHI
Count Reqister Middle ICNTRMI
Count Register Low ICNTRLI
Timer Status Register ITSRI
a
a
a
RW
1
RW
Ves
No
0
1
1
a
RW
Ves
No
1
RW
Ves
No
a
a
a
R W
1
RW
Ves
Ves
No
No
1
1
0
0
1
1
0
0
0
0
1
a
RW
Ves
No
1
0
1
0
1
0
1
0
1
1
0
1
1
0
1
0
R W
Ves
No
RW
No
RW
No
R
No
No
* *
* *
No
No
a
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0
Port C Data Register IPCDRI
a
a
Affected
by
Reset
Ves
Register
Select Bks
4
3
2
Register
"A write to this register may perform a special status resetting operation.
""Mode dependent.
4. All registers are addressable as 8·bit
quantities. To facilitate operation with
the MOVEP instruction and the DMAC,
addresses are ordered such that cer·
tain sets of registers can also be accessed as words (2 bytes) or long
words (4 bytes).
PORT GENERAL CONTROL REGISTER
(PGCR)
The port general register controls many of
the functions that are common to the
overall operation of the ports. The PGCR
is composed of three major fields: bits 7
and 6 define the operational mode of ports
A and B and affect operation of the handshake pins and status bits; bits 5 and 4
allow a software controlled disabling of
particular hardware associated with the
handshake pins of each port; and bits 3-0
define the sense of the handshake pins.
The PGCR is always readable and writable.
4·114
a
0
1
0
a
1
Accessible
1
R
RW
R W*
RW
5
o
1
The port mode control field should be
altered only when the H12 enable and H34
enable bits are O. Except when mode 0 is
desired, the port general control register
must be written once to establish the
mode, and again to enable the respective
operation(s).
Port General Control Register (PGCR)
7
I
6
5
4
3
2
H34
H12
H4
H3
~nablE Enable Sense Soose
1
0
H2
H1
Sense Sense
Port Mode Control
Mode 0 (unidirectional 8-Bit mode)
Mode 1 (unidirectional 16-blt mode)
1 0 Mode 2 (bidirectional 8-bit mode)
1 1 Mode 3 (bidirectional 16-bit mode)
7 6
o0
o1
Signetics
No
No
Ves
No
Ves
No
No
No
RW
Ves
RW
No
No
No
RW
RW
No
No
R
No
No
R
No
R
No
No
R W*
ves
No
No
No
R = Read
W = Write
All bits are reset to 0 when the RESET pin
is asserted.
Port Mode
Control
Affected
by Read
Cycle
H34 Enable
Disabled
Enabled
H12 Enable
Disabled
1 Enabled
4
o
3-0
o
Handshake Pin Sensa
The associated pin is at the high
voltage level when negated and at
the low voltage level when asserted.
The associated pin is at the low
voltage level when negated and at
the high voltage level when asserted.
PORT SERVICE REQUEST REGISTER
(PSRR)
The port service request register controls
other functions that are common to the
overall operation to the ports. It is composed of four major fields: bit 7 is unused
and is always read as 0; bits 6 and 5 define
whether interrupt or DMA requests are
generated from activity on the H 1 and H3
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68230
PARALLEL INTERFACE/TIMER
'm""II,I.''i
Port Interrupt Vector Register (PIVR)
handshake pins; bits 4 and 3 determine
whether two dual function pins operate as
port C or port interrupt request!
acknowledge pins; and bits 2, 1, and 0 control the priority among all port interrupt
sources. Since bits 2, 1, and 0 affect interrupt operation, it is recommended that
they be changed only when the affected
interrupt(s) is disabled or known to remain
inactive. The PSRR is always readable and
writable.
Port Interrupt Priority Control
210 Highest
000 H1S
H2S
H3S
001 H2S
H1S
H3S
010 H1S
H2S
H4S
011 H2S
H1S
H4S
100 H3S
H1S
H4S
1 0 1 H3S
H4S
H2S
H1S
1 1 0 H4S
H3S
1 1 1 H4S
H3S
H2S
All bits are reset to 0 when the RESET pin
is asserted.
PORT A DATA DIRECTION REGISTER
(PADDR)
The port A data direction register determines the direction and buffering
characteristics of each of the port A pins.
One bit in the PADDR is assigned to each
pin. A 0 indicates that the pin is used as an
input, while a 1 indicates it is used as
an output. The PADDR is always readable
and writable. This register is ignored in
mode 3.
Port Service Request Register (PSRR)
7
6
I
5
SVCRO
*
Select
4
I
3
Interrupt
PFS
2
I I
1
0
Port Interrupt
PrioritY Control
6 5
SVCRQ Select
The PC4IDMAREQ pin carries the
PC4 function; DMA is not used.
1 0 The PC4/DMAREQ pin carries the
DMAREQ function and is associated
with double buffered transfers controlled by H1. H1 is removed from
the PI/T's interrupt structure, and
thus, does not cause interrupt requests to be generated. To obtain
DMAREQ pulses, port A control
register bit 1 (H1 SVCRQ enable)
must be a 1.
1 1 The PC4/DMAREQ pin carries the
DMAREQ function and is associated
with double buffered transfers controlled by H3. H3 is removed from
the PI/l's interrupt structure, and
thus, does not cause interrupt requests to be generated. To obtain
DMAREQ pulses, Port B Control
Register bit 1 (H3 SVCRQ Enable)
must be 1.
oX
4 3
o0
Interrupt Pin Function Select
The PC5/PIRQ pin carries the PC5
function.
The PC6/PIACK pin carries the PC6
function.
o 1 The PC5/PIRQ pin carries the PIRQ
function.
The PCS/PIACK pin carries the PC6
function.
1 0 The PC5/PIRQ pin carries the PC5
function.
The PC6/PIACK pin carries the
PlACK function.
1 1 The PC5IPIRQ pin carries the PIRQ
function.
The PC6/PIACK pin carries the
PlACK function.
Bits 2, 1, and 0 determine port interrupt
priority. The priority is shown in descending order left to right.
Lowest
H4S
H4S
H3S
H3S
H2S
H1S
H2S
H1S
All bits are reset to the 0 (input) state when
the RESET pin is asserted.
PORT B DATA DIRECTION REGISTER
(PBDDR)
The PBDDR is identical to the PADDR for
the port B pins and the port B data
register, except that this register is ignored in modes 2 and 3.
PORT C DATA DIRECTION REGISTER
(PCDDR)
The port C data direction register
specifies whether each dual function pin
that is chosen for the port C operation is
an input (0) or an output (1) pin. The
PCDDR, along with bits that determine the
respective pin's function, also specify the
exact hardware to be accessed at the port
C data register address. (See the Port C
Data Register description for more
details.) The PCDDR is an 8-bit register
that is readable and writable at all times.
Its operation is independent of the chosen
PI/T mode.
From a normal read cycle (CS), there is
never a consequence to reading this
register. Following negation of the RESET
pin, but prior to writing to the PIVR, a $OF
will be read. After writing to the register,
the upper 6 bits may be read and the lower
2 bits are forced to O. No prioritization
computation is performed.
All bits are cleared to 0 when the RESET
pin is asserted. When the port A submode
field is relevant in a mode/submode definition, it must not be altered unless the H12
enable bit in the port general control
register is 0 (see Table 3).
The operation of H1 and H2 and their
related status bits is given below for each
of the modes specified by the port general
control register bits 7 and 6.
Bits 2 and 1 carry the same meaning in
each mode/submode, and thus are
specified only once.
Port A Control Register (PACR)
These bits are cleared to 0 when the
RESET pin is asserted.
PORT INTERRUPT VECTOR REGISTER
(PIVR)
The port interrupt vector register contains
the upper order six bits of the four port interrupt vectors. The contents of this
register can be read two ways: by an ordinary read cycle, or by a port interrupt
acknowledge bus cycle. The exact data
read depends on how the cycle was initiated and other factors. Behavior during
a port interrupt acknowledge cycle is summarized in Table 4.
Signetics
4
PORT A CONTROL REGISTER (PACR)
The port A control register, in conjunction § § § §
with the programmed mode and the port B
submode, control the operation of port A
and the handshake pins H1 and H2. The
port A control register contains five fields:
bits 7 and 6 specify the port A submode;
bits 5, 4, and 3 control the operation of the
H2 handshake pin and H2S status bit; bit 2
determines whether an interrupt will be
generated when the H2S status bit goes to
1; bit 1 determines whether a service request (interrupt request or DMA request)
will occur; bit 0 controls the operation of
the H1S status bit. The PACR is always
readable and writable.
7
I
6
Port A
Submode
5
I I
4
H2 Control
3
2
1
a
H2
Hl
Hl
Inl
SVCRO Slat
Enabll) Enable elrl
2
H2 Interrupt Enable
The H2 interrupt is disabled.
1 The H2 interrupt is enabled.
o
1
o
H1 SVCRQ Enable
The H1 interrupt and DMA request are
disabled.
The H1 interrupt and DMA request are
enabled.
4·115
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68230
PARALLEL INTERFACE/TIMER
Mode 0, Port A Submode 00
o
X
5 4 3
X
1 0 0
1 0 1
1 1 0
oX
o
X
H2 Control
Input pin-status only.
Output pin-always negated.
Output pin-always asserted.
Output pin-interlocked input
handshake protocol.
Output pin-pulsed input handshake protocol.
H1 Status Control
Not used
Mode 2
5 4 3 H2 Control
X X 0 Output pin-interlocked output
handshake protocol.
X X 1 Output pin-pulsed output handshake protocol.
o
o
Mode 0, Port A Submode 01
5 4 3
X
1 0 0
1 0 1
1 1 0
oX
1 1
o
o
H2 Control
Input pin-status only.
Output pin-always negated.
Output pin-always asserted.
Output pin-interlocked output
handshake protocol.
Output pin-pulsed output
handshake protocol.
H1 Status Control
The HIS status bit is 1 when either the
port A initial or final output latch can
accept new data. It is 0 when both latches are full and cannot accept new
data.
The HIS status bit is 1 when both of
the port A output latches are empty. It
is 0 when at least one latch is full.
Mode 0, Port A Submode 1X
5 4 3 H2 Control
X Input pin-status only.
1 X 0 Output pin-always negated.
1 X 1 Output pin-always asserted.
oX
o
H1 Status Control
X Not used.
Mode 1, Port A Submode XX,
Port B Submode XO
5 4 3 H2 Control
X Input pin-status only.
1 X 0 Output pin-always asserted.
1 X 1 Output pin-always asserted.
oX
o
X
H1 Status Control
Not used.
Mode 1 Port A Sub mode XX
Port B Submode X1
5 4 3 H2 Control
X Input pin-status only.
1 X 0 Output pin-always negated.
1 X 1 Output pin-always asserted.
oX
4·116
H1 Status Control
Not used.
H1 Status Control
The HIS status bit Is 1 when either the
port B Initial or final output latch can
accept new data. It is 0 when both latches are full and cannot accept new
data.
The HIS status bit is 1 when both of
the port B output latches are empty. It
is 0 when at least one latch is full.
The operation of H3 and H4 and their
related status bits is given below for each
of the modes specified by the port general
control register bits 7 and 6.
Bits 2 and 1 carry the same meaning in
each mode/submode, and thus are
specified only once.
Port B Control Register (PBCR)
I6
7
Port B
Submode
2
o
1
51
4
I
H4 Control
3
2
H4
Int
Enable
1
o
5 4 3 H2 Control
X X 0 Output pin-interlocked output
handshake protocol.
X X 1 Output pin-pulsed output handshake protocol.
Mode 0, Port B Submode 00
H1 Status Control
The HIS status bit is 1 when either the
initial or final output latch of port A
and B can accept new data. It is 0 when
both latches are full and cannot accept
new data.
The HIS status bit is 1 when both the
initial and final output latches of ports
A and B are empty. It is 0 when either
the initial or final latch of ports A and B
is full.
PORT B CONTROL REGISTER (PBCR)
The port B control register specifies the
operation of port B and the handshake
pins H3 and H4. The port B control register
contains five fields: bits 7 and 6 specify
the port B submode; bits 5, 4, and 3 control the operation of the H4 handshake pin
and H4S status bit; bit 2 determines
whether an interrupt will be generated
when the H4S status bit goes to 1; bit 1
determines whether a service request (interrupt request or DMA request) will occur; bit 0 controls the operation of the H3S
status bit. The PACR is always readable
and writable. There Is never a consequence to reading the register.
All bits are cleared to 0 when the RESET
pin is asserted. When the port B submode
field is relevant in a mode/submode definition, it must not be altered unless the H34
enable bit in the port general control
register is 0 (see Table 3).
Signetics
H3 SVCRQ Enable
The H3 interrupt and DMA request are
disabled.
The H3 interrupt and DMA request are
enabled.
5 4 3
X
1 0 0
1 0 1
1 0
oX
o
o
0
H4 Interrupt Enable
The H4 interrupt is disabled.
The H4 interrupt is enabled.
Mode 3
o
o
1
H3
H3
SVCRQ Stat.
Enable etrl.
H4 Control
Input pin - status only.
Output pin - always negated.
Output pin - always asserted.
Output pin - interlocked input
handshake protocol.
Output pin - pulsed input handshake protocol.
H3 Status Control
Not used.
Mode 0, Port B Submode 01
5 4 3
H4 Control
Input pin-status only.
Output pin-always negated.
Output pin-always asserted.
1 0 Output pin-interlocked output
handshake protocol.
1 1 Output pin-pulsed output handshake protocol.
oX X
o0
o1
o
o
H3 Status Control
The H3S status bit is 1 when either the
port B initial or final output latch can
accept new data. It is 0 when both
latches are full and cannot accept new
data.
The H3S status bit is 1 when both of
the port B output latches are empty. It
is 0 when at least one latch is full.
JANUARY 1983
MICROPROCESSOR DIVISION
PARALLEL INTERFACE/TIMER
'am",,·"'-'"
Mode 0, Port B Submode 1X
o
X
5
o
1
1
4
X
X
X
3 H4 Control
X Input pin-status only.
0 Output pin-always negated.
1 Output pin-always asserted.
o H3 Status Control
X Not used.
Mode 1, Port B Submode XO
5 4 3
X
1 a 0
1 0 1
1 a
oX
H4 Control
Input pin-status only.
Output pin-always negated.
Output pin-always asserted.
Output pin-interloCked input
handshake protocol.
Output pin - pulsed input handshake protocol.
SCN68230
H3 Status Control
Not used.
PORT A DATA REGISTER (PADR)
The port A data register is an address for
moving data to and from the port A pins.
The port A data direction register determines whether each pin is an input (0) or
an output (1), and is used in configuring
the actual data paths. PADR is mode
dependent
This register is readable and writable at all
times. Depending on the chosen model
submode, reading or writing may affect
the double buffered handshake
mechanism. The port A data register is not
affected by the assertion of the RESET
pin.
o H3 Status Control
X Not used.
Mode 1, Port B Submode X1
5 4
oX
1 a
1 0
1 1
o
o
3 H4 Control
X Input pin-status only.
0 Output pin-always negated.
1 Output pin-always asserted.
a Output pin-interlocked output
handshake protocol.
Output pin - pulsed output handshake protocol.
H3 Status Control
The H3S status bit is 1 when either the
initial or final output latch of port A
and B can accept new data. It is 0 when
both latches are full and cannot accept
new data.
The H3S status bit is 1 when both the
initial and final output latches of ports
A and B are empty. 1\ is 0 when neither
the initial or final latch of ports A and B
is full.
Mode 2
5 4 3 H4 Control
X X a Output pin-interlocked input
handshake protocol.
X X 1 Output pin-pulsed input handshake protocol.
o
H3 Status Control
X Not used.
Mode 3
5 4 3 H4 Control
X X 0 Output pin-interlocked input
handshake protocol.
X X 1 Output pin-pulsed input handshake protocol.
PORT B DATA REGISTER (PBDR)
The port B data register is an address for
moving data to and from the port B pins.
The port B data direction register determines whether each pin is an input (0) or
an output (1), and is used in configuring
the actual data paths. PBDR is mode
dependent
This register is readable and writable at all
times. Depending on the chosen model
submode, reading or writing may affect
the double buffered handshake mechanism. The port B data register is not affected by the assertion of the RESET pin.
PORT A ALTERNATE REGISTER (PAAR)
The port A alternate register is an alternate address for reading the port A pins. It
is a read only address and no other PIIT
condition is affected. In all modes, the
instantaneous pin level is read and no input latching is performed except at the
data bus interface (see Bus Interface Connection). Writes to this address are
answered with DTACK, but the data is ignored.
PORT B ALTERNATE REGISTER (PBAR)
The port B alternate register is an alternate address for reading the port B pins. It
is a read only address and no other PI/T
condition is affected. In all modes, the instantaneous pin level is read and no input
latching is performed except at the data
bus interface (see Bus Interface Connection). Writes to this address are answered
with DTACK, but the data is ignored.
Signetics
PORT C DATA REGISTER (PCDR)
The port C data register is an address for
moving data to and from each of the eight
port C/alternate function pins. The exact
hardware accessed is determined by the
type of bus cycle (read or write) and individual conditions affecting each pin.
These conditions are: whether the pin is
used for the port C or alternate function,
and whether the port C data direction
register indicates the input or output
direction. The port C data register is single
buffered for output pins and not buffered
for input pins. These conditions are summarized in table 12.
The Port C data register is not affected by
the assertion of the RESET pin.
The operation of the PCDR is independent
of the chosen PIIT mode.
Note that two additional useful benefits
result from this structure. First, it is possible to directly read the state of a dual function pin while used for the non port C function. Second, it is possible to generate
program controlled transitions on alternate function pins by switching back to
the port C function, and writing to the
PCDR.
This register is readable and writable at all
times.
PORT STATUS REGISTER (PSR)
The port status register contains information about handshake pin activity. Bits 7-4
show the instantaneous level of the
respective handshake pin, and is independent of the handshake pin sense bits in
the port general control register. Bit 3-0
Table 12
PCDR HARDWARE
ACCESSES
Read Port C Data Register
Port C
function
PCDDR=O
PortC
function
PCDDR=1
pin
Porte
output
Alternate
Alternate
function
function
PCDDR=O
PCDDR=1
PortC
pin
output
register
register
Write Port C Data Register
function
PCDDR=O
porte
function
PCDDR=1
Alternate
function
PCDDR=O
Alternate
function
PCDDR= 1
Port C
output
register,
buffer
disabled
Port C
output
register,
buffer
enabled
porte
output
register
Port C
output
register
Porte
4·117
4
JANUARV1983
MICROPROCESSOR DIVISION
PARALLEL INTERFACE/TIMER
'm'''''''!·''1
are the respective status bits referred to
throughout this data sheet. Their Inter·
pretation depends on the programmed
mode/submode of the PIIT. For bits 3'(), a 1
is the active or asserted state.
Port Status Register (PSR)
5
6
7
3
2
1
0
H4S
H3S
H2S
H1S
4
H1
H2
level level Level Level
H4
H3
TIMER CONTROL REGISTER (TCR)
The timer control register determines all
operations of the timer. Bits 7·5 configure
the PC3/TOUT and PC71T1ACK pins for
port C, square wave, vectored Interrupt, or
autovectored interrupt operation; bit 4
specifies whether the counter receives
data from the counter preload register or
continues counting when zero detect is
reached; bit 3 is unused and is read as 0;
bits 2 and 1 configure the path from the
ClK and TIN pins to the counter con·
troller; bit 0 enables the timer. This
register is readable and writable at all
times.
All bits are cleared to 0 when the RESET
pin is asserted.
Timer Control Register (TCR)
7
I I
6
5
TOUTITIACK
Control
4
Z.D.
Ctrl.
I
1
3
2
*
Clock
Control
0
Timer
Enable
request is negated, the PIIT pro·
duces no response, i.e., no data or
DTACK to an asserted TIACK.
Refer to the Timer Interrupt Cycle
section for details. This combination and the 101 state below support vectored timer interrupts.
1 0 1 The dual function pin PC3ITOUT
carries the TOUT function and is
used as a timer interrupt request
output. The timer interrupt is
enabled; thus, the pin is low when
the timer ZDS status bit is 1. The
dual function pin PC7/TIACK car·
ries the TIACK function and is
used as a timer interrupt
acknowledge input. Refer to the
Timer Interrupt Acknowledge Cycle section for details. This combination and the 100 state above
support vectored timer interrupts.
1 1 0 The dual function pin PC3ITOUT
carries the TOUT function. In the
run or halt state it is used as a
timer interrupt request output.
The timer Interrupt is disabled;
thus, the pin is always threestated. The dual function pin
PC7/TIACK carries the PC7 function.
1 1 1 The dual function pin PC3ITOUT
carries the TOUT function and is
used as a timer interrupt request
output. The timer interrupt is
enabled; thus, the pin is low when
the timer ZDS status bit is 1. The
dual function pin PC71T1ACK carries the PC7 function and autovec·
tored interrupts are supported.
4
o
7 6 5 TOUTITIACK Control
o 0 X The dual function pins PC3/TOUT
and PC71T1ACK carry the port C
function.
o 1 X The dual function pin PC3ITOUT
carries the TOUT function. In the
ru n state It is used as a square
wave output and Is toggled on
zero detect. The TOUT pin is high
whfie In the halt state. The dual
function pin PC71T1ACK carries
the PC7 function.
1 0 0 The dual function pin PC3ITOUT
carries the TOUT function. In the
run or halt state it is used as a
timer interrupt request output.
The timer interrupt is disabled;
thus, the pin is always threestated. The dual function pin
PC71T1ACK carries the TIACK
function; however, since interrupt
4·118
SCN68230
Zero Detect Control
The counter is loaded from the counter
preload register on the first clock to
the 24-bit counter after zero detect,
and resumes counting.
The counter rolls over on zero detect,
then continues counting.
Bit 3 is unused and is always read as O.
2 1
o0
o
Clock Control
The PC2ITIN input pin carries the
port C function and the ClK pin and
prescaler are used. The prescaler Is
decremented on the falling transition of the ClK pin; the 24-bit
counter is decremented or loaded
from the counter preload registers
when the prescaler rolls over from
$00 to $1 F. The timer enable bit
determines whether the timer is in
the run or halt state.
1 The PC2/TIN pin serves as a timer input and the ClK pin and prescaler
Signetics
are used. The prescaler Is
decremented on the falling transition of the ClK pin; the 24-bit
counter Is decremented or loaded
from the counter preload registers
when the. prescaler rolls over from
$00 to $1 F. The timer is in the run
state when the timer enable bit is 1
and the TIN pin is high; otherwise
the timer is in the halt state.
1 0 The PC2ITIN pin serves as a timer in·
put and the prescaler is used. The
prescaler is decremented following
the rising transition of the TIN pin
after syncing with the internal clock.
The 24-bit counter Is decremented or
loaded from the counter preload
registers when the prescaler rolls
over from $00 to $1F. The timer
enable bit determines whether the
timer is in the run or halt state.
1 1 The PC2ITIN pin serves as a timer
input and the prescaler is unused.
The 24·bit counter Is decremented or
loaded from the counter preload
registers following the rising edge
of the TIN pin after syncing with the
internal clock. The timer enable bit
determines whether the timer is in
the run or halt state.
o
o
Timer Enable
Disabled.
1 Enabled.
TIMER INTERRUPT VECTOR REGISTER
(TIVR)
The timer interrupt vector register contains the a-bit vector supplied when the
timer interrupt acknowledge pin TIACK Is
asserted. The register is readable and
writable at all times, and the same value is
always obtained from a normal read cycle
and a timer interrupt acknowledge bus cycle (TIACK). When the RESET pin is
asserted, the value of $OF is automatically
loaded into the register. Refer to the Timer
Interrupt Acknowledge Cycle section for
more details.
COUNTER PRELOAD REGISTER
H, M, l (CPRH-l)
The counter preload registers are a group
of three a-bit registers used for storing
data to be transferred to the counter. Each
of the registers is individually addressable, or the group may be accessed
with the MOVEP.l or the MOVEP.W instructions. The address one less than the
address of CPRH is the null register, and
is reserved so that zeros are read in the upper a bits of the destination data register
when a MOVEP.l is used. Data written to
this address is ignored.
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68230
PARALLEL INTERFACE/TIMER
'm",,""·'·,
The registers are readable and writable at
all times. A read cycle proceeds in·
dependently of any transfer to the
counter, which may be occurring
simultaneously.
To insure proper operation of the PIIT
timer, a value of $000000 cannot be stored
in the counter preload registers for use
with the counter.
The RESET pin does not affect the con·
tents of these registers.
Counter Preload Register H, M, L (CPRH·L)
•
7
B"
23
6
B"
22
5
Bit
21
B"
20
B"
19
3
2
Ba
lB
1
Bit
17
0
Ba
16
B"
15
B"
,.
B"
13
B"
12
B"
11
B"
10
B"
9
Ba
B
CPAM
Ba
7
B"
6
B"
5
Sir
B"
3
B"
2
B"
1
B"
0
CPRl
CPRH
edge sensitive flip flop that is set to 1
when the 24·bit counter decrements from
$000001 to $000000. The ZOS status bit is
cleared to 0 following the direct clear
operation (similar to that of the ports), or
when the timer is halted. Note also that
when the RESET pin is asserted, the timer
is disabled and thus enters the halt state.
This register is always readable without
consequence. A write access performs a
direct clear operation if bit 0 in the written
data is 1. Following that, the ZDS bit is O.
This register is constructed with a reset
dominant S·R flip flop 50 that all clearing
conditions prevail over the possible zero
detect condition.
Bits 7·1 are unused and are read as O.
Timer Status Register (TSR)
•
COUNT REGISTER H, M, L (CNTRH·L)
The count registers are a group of three
8·bit addresses at which the counter can
be read. The contents of the cou nter are
not latched during a read bus cycle; thus,
the data read at these addresses is not
guaranteed if the timer is in the run state.
(Bits 2, 1 and 0 of the timer control register
specify the state.) Write operations to
these addresses result in a normal bus cy·
cle but the data is ignored.
Each of the registers 15 Individually ad·
dressable, or the group can be accessed
with the MOVEP.L or the MOVEP.W in·
structions. The address one less than the
address of CNTRH is the null register, and
is reserved so that zeros are read in the up·
per 8 bits of the destination data register
when a MOVEP.L is used. Oata written to
this address is ignored.
then enables the timer. When the 24·bit
cou nter passes from $000001 to $000000,
the ZDS status bit is set and the TOUT (in·
terrupt request) pin is asserted. At the
next clock to the 24·bit counter, it is again
loaded with the contents of the CPRs and
thereafter decrements. In normal opera·
tion, the processor must direct clear the
status bit to negate the interrupt request
(see Figure 8).
Periodic Interrupt Generator
4
Square Wave Generator
In this configuration the timer produces a
square wave at the TOUT pin. The TOUT
pin is connected to the user's circuitry
and the TIACK pin is not used. The TIN pin
may be used as a clock input.
The processor loads the counter preload
registers and timer control register, and
then enables the timer. When the 24·bit
TIMER APPLICATIONS SUMMARY cou nter passes from $000001 to $000000,
the ZOS status bit is set and the TOUT
Periodic Interrupt Generator
(square wave output) pin is toggled. At the
In this configuration the timer generates a next clock to the 24·bit counter, it is again
periodic interrupt. The TOUT pin is con· loaded with the contents of the CPRs and
nected to the system's interrupt request thereafter decrements. In this application
circuitry and the TIACK pin can be used as there is no need for the processor to direct
an interrupt acknowledge input to the clear the ZOS status bit; however, it is
timer. The TIN pin can be used as a clock possible for the processor to sync itself
input.
with the square wave by clearing the ZOS
status bit, then polling it. The processor
The processor loads the counter preload can also read the TOUT level at the port C
registers and timer control register, and address.
TIMER
ENABLE
J
~I·~-------------RUN----------------
$FFFFFF
Count Register H, M, L (CNTRH·L)
24·BIT
COUNTER'
7
6
5
•
3
2
1
0
Ba
23
Ba
22
B"
21
Bit
20
Bit
19
Bit
lB
Ba
17
B"
16
Bit
15
B"
,.
B"
13
Bit
12
Ba
11
Bit
10
B"
9
Bit
Ba
7
Bit
6
B"
5
Bit
B"
3
B"
2
Ba
1
Bit
0
•
B
CNTRH
CNTRM
eNTRl
TIMER STATUS REGISTER (TSR)
The timer status register contains one bit
from which the zero detect status can be
determined. The ZOS status bit (bit 0) is an
$000000
ZDS
TOUT
'ANALOG REPRESENTATION OF COUNTER VALUE
Figure 8. Periodic Interrupt Generator
Signetics
4·119
JANUARY 1983
MICROPROCESSOR DIVISION
PARALLEL INTERFACE/TIMER
SCN68230
'm""·"'·'"
Note that the PC3/TOUTpin functions as
PC3 following the negation of RESET. If
used in the square wave configuration, a
PUIIUP resistor may be ·requlred to keep a
known level prior to programming. Prior to
enabling the timer, TOUT is high (see
Figure 9).
Square Wave Generator
I~_~------------RUN--------~----
TIMER
ENABLE
J
SFFFFFF
24-BIT
COUNTER·
Interrupt After Timeout
In this configuration the timer generates
an interrupt after a programmed time
period has expired. The TOUT pin Is connected to the system's interrupt request
circuitry and the TlACK pin can be an interrupt acknowledge input to the timer.
The TIN pin may be used as a clock input.
soooooo
\'---~/
TOUT
I_
L
SQUAREWAVE----
·ANALOG REPRESENTATION OF COUNTER VALUE.
This configuration is similar to the
periodic interrupt generator except that
the zero detect control bit is set. This
forces the counter to roll over after zero
detect is reached, rather than reloading
from the CPRs. When the processor takes
the interrupt, it can halt the timer and read
the counter. This allows the processor to
measure the delay time from zero detect
(interrupt request) to entering the service
routine. Accurate knowledge of the interrupi latency may be useful In some applications (see Figure 10).
Figure 9. Square Wave Generetor
Interrupt After Timeout
TIMER
ENABLE
J
RUN
L
$FFFFFF
Elapsed Time Measurement
Elapsed time measurement takes several
forms; two are described below. The first
configuration allows time Interval
measurement by software. No timer pins
are used.
The processor loads the counter preload
registers (generally with all 1s) and timer
control register, and then enables the
timer. The counter decrements until the
ending event takes place. When it is
desired to read the time intervat, the processor must halt the timer, then read the
counter. For applications In which the interval could have exceeded that programmable in this timer, interrupts can be
counted to provide the equivalent of additional timer bits. At the end, the timer can
be halted and read (see Figure 11).
4·120
24·BIT
COUNTER·
$000000
ZDS
\
TOUT
·ANALOG REPRESENTATION OF COUNTER VALUE.
u
Figure 10. Single Interrupt After Timeout
Signetics
L
I
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68230
PARALLEL INTERFACE/TIMER
'm""lI"·iii
System Clock
TIMER
ENABLE
J
The second configuration allows measure·
ment (counting) of the number of input
pulses occurring in an interval in which
the counter is enabled. The TIN input pin
provides the Input pulses. Generally the
TOUT and TIACK pins are not used.
~I·r---------RUN--------~·~I
$FFFFFF
ELAPSED
TIME
24·BIT
COUNTER"
4
This configuration is Identical to the ~~F~
elapsed time measurement/system clock
configuration except that the TIN pin is ~~§~§
used to provide the input frequency. It can
be connected to a simple oscillator, and
the same methods could be used. Alter·
nately, it could be gated off and on exter·
nally and the number of cycles occurring
while in the run state can be counted.
However, minimum pulse width high and
low specifications must be met.
=
$000000
"ANALOG REPRESENTATION OF COUNTER VALUE.
External Clock
Figure 11. Elapsed Time Measurement
TIMER
ENABLE
Device Watchdog
This configuration provides the watchdog
function needed in many systems. The
TIN pin is the timer input whose period at
the high (1) level is to be checked. Once
allowed by the processor, the TIN input
pin controls the run/halt mode. The TOUT
pin is connected to external circuitry requiring notification when the TIN pin has
been asserted longer than the programmed time. The TlACK pin (Interrupt
acknowledge) is only needed if the TOUT
pin is connected to interrupt circuitry.
J
TIN
$FFFFFF
======ll
~
~
COU2:~~! ----~I "--1 ~
n
$000000 - - - - - - - '
ZDS
-
==========~
~-TOUT
~
"ANALOG REPRESENTATION OF COUNTER VALUE.
Figure 12. Device Watchdog
SigneHcs
The processor loads the counter preload
register and timer control register, and
then enables the timer. When the TIN Input is asserted (1, high) the timer transfers
the contents of the counter preload
register to the counter and begins counting. If the TIN input Is negated before zero
detect is reached, the TOUT output and
the ZOS status bit remain negated. If zero
detect Is reached while the TIN Input is
still asserted, the ZOS status bit is set and
the TOUT output is asserted. (The counter
rolls over and keeps on counting).
In either case, when the TIN input is
negated, the ZOS status bit is 0, the TOUT
output is negated, the counting stops, and
prescaler is forced to all Is (see Figure 12).
4·121
MICROPROCESSOR DIVISION
JANUARY 1983
PARALLEL INTERFACE/TIMER
SCN68230
'81"..II"·"A
Device Watchdog
BUS INTERFACE CONNECTION
The PI/T has an asynchronous bus Interface, primarily designed for use with the
SCN68000 microprocessor. With care,
however, it can be connected to synchronous microprocessor buses. This section completely describes the PI/T's bus
Interface, and is Intended for the asynchronous bus designer unless otherwise
specified.
In an asynchronous system, the PI/T CLK
can operate at a significantly different frequency, either higher or lower than the
bus master and other system components, as long as all bus specifications
are met. The SCN68230 CLK pin has the
same specifications as the SCN68000
CLK, and must not be gated off at any time.
The following signals generate normal
read and write cycles to the PI/T: CS (chip
select), RIW (read/write), RS1-RS5 (five
register select bits), Do-D7 (the 8-bit
bidirectional data bus), and DTACK (data
transfer acknowledge). To generate Interrupt acknowledge cycles, PC6/PIACK or
PC71T1ACK Is used Instead of CS and the
register select pins are ignored. No combination of the following pins can be
asserted simultaneously: CS, PlACK, or
TIACK.
Read Cycles via Chip Select
This category includes all register reads,
except port or timer Interrupt
acknowledge cycles. When CS Is
asserted, the register select and RlW Inputs are latched Internally. They must
meet small setup and hold time requirements with respect to the asserted
edge of CS (see the AC Electrical
Characteristics table). The PI/T Is not protected against aborted (shortened) bus
cycles generated by an address error or
bus error exception in which It is addressed.
Certain operations triggered by normal
read (or write) bus cycles are not complete
within the time allotted to the bus cycle.
One example is transfers to/from the double buffered latches that occur as a resu It
of the bus cycle. If the bus master's CLK Is
significantly faster than the PI/T's, the
possibility exists that, following the bus
cycle, CS can be negated then reasserted
before completion of these Internal opera-
4·122
tions. In this situation the PI/T does not
recognize the reassertion of CS until
these operations are complete. Only at
that time does It begin the internal sequencing necessary to react to the
asserted CS. Since CS also controls the
DTACK response, this 'bus cycle recovery
time' can be related to the CLK edge on
which DTACK is asserted for that cycle.
The PI/T will recognize the subsequent
assertion of CS three CLK periods after
the CLK edge on which DTACK was
previously asserted.
The register select and RIW inputs pass
through an internal latch that is
transparent when the PI/T can recognize a
new CS pulse (see above paragraph).
Since the internal data bus of the PI/T is
continuously enabled for read transfers,
the read access time (to the data bus buffers) begins when the register selects are
stabilized Internally. Also, when the PI/T is
ready to begin a new bus cycle, the assertion of CS enables the data bus buffers
within a short propagation delay. This
does not contribute to the overall read access time, unless CS Is asserted
significantly after the register select and
R/W Inputs are stabilized (as may occur
with synchronous bus microprocessors).
In addition to chip select's previously
mentioned duties, it controls the assertion of DTACK and latching of read data at
the data bus interface. Except for controlling input latches and enabling the data
bus buffers, all of these functions occur
only after CS has been recognized internally and synchronized with the internal
clock. Chip select is recognized on the
failing edge of the CLK if the setup time is
met, and DTACK is asserted (low) on the
next falling edge of the CLK. Read data Is
latched at the PI/T's data bus Interface at
the same time DTACK is asserted. It is
stable as long as chip select remains
asserted independent of other external
conditions.
From the above diSCUSSion, it is clear that
if the CS setup time prior to the failing
edge of the CLK Is met the PI/T can consistentiy respond to a new read or write
bus cycle every four CLK cycles. This fact
Is especially useful in designing the PI/T's
clock In synchronous bus systems not using DTACK. (An extra CLK period is required In interrupt acknowledge cycles,
see Read Cycles via Interrupt
Acknowledge).
In asynchronous bus systems in which the
PI/T's CLK differs from that of the bus
Signetics
master, generally there Is no way to
guarantee that the CS setup time with
respect to the PI/T CLK is met. Thus, the
only way to determine that the PI/T
recognized the assertion of CS is to wait
for the assertion of DTACK. In this situation, all latched bus inputs to the PI/T
must be held stable until DTACK is
asserted. These include register select,
RIW, and write data inputs (see below).
System specifications impose a maximum
delay from the trailing (negated) edge of
chip select to the negated edge of DTACK.
As system speeds Increase, this becomes
more difficult to meet with a Simple pullup
resistor tied to the DTACK line. Therefore,
the PI/T provides an Internal active pullup
device to reduce the rise time, and a level
sensitive circuit that later turns this
device off. DTACK Is negated asynchronously as fast as possible following
the rising edge of chip select, then threestated to avoid Interference with the next
bus cycle.
The system designer must take care that
DTACK Is negated and three-stated quickly enough after each bus cycle to avoid interference with the next one. With the
SCN68000 this necessitates a relatively
fast external path from the data strobe to
CS going negated.
Write Cycle.
In many ways write cycles are similar to
normal read cycles (see above). On write
cycles, data at the DO-D7 pins must meet
the same setup specifications as the
register select and R/W lines. Like these
signals, write data is latched on the
asserted edge of CS, and must meet small
setup and hold time requirements with
respect to that edge. The same bus cycle
recovery conditions exist as for normal
read cycles. No other differences exist.
Read Cycle. via Interrupt Acknowledge
Special Internal operations take place on
PI/T Interrupt acknowledge cycles. The
port Interrupt vector register or the timer
Interrupt vector register are Implicitly addressed by the assertion of pea/PlACK or
PC7IT1ACK, respectively. The signals are
first synchronized with the failing edge of
the CLK. One clock period after they are
recognized, the data bus buffers are enabled and the vector Is driven onto the bus.
DTACK Is asserted after another clock
period to allow the vector some setup
prior to DTACK. DTACK is negated, then
three-stated as with the normal read or
write cycle when PlACK or TIACK is
negated.
MICROPROCESSOR DIVISION
JANUARY 1983
SCN68230
PARALLEL INTERFACE/TIMER
'am",,""·",
ABSOLUTE MAXIMUM RATINGS 1
Parameter
Supply voltage
Input voltage3
Operating temperature range 2
Storage temperature
DC ELECTRICAL CHARACTERISTICS
Parameter
Rating
Unit
-0.3 to + 7.0
-0.3 to + 7.0
to + 70
-55 to + 150
V
V
"C
"C
o
(V ee =5.0V +5%,
TA=O"C to
Test Conditions
VIH
Input high voltage
V IL
Input low voltage
lin
Input leakage current
H1,H3,R/W,RESET,CLK,
RS1-RS5, CS
Yin = 0 to 5.25V
ITSI
Three-state (off state) input current
OTACK,PCO-PC7,00-07
H2,H4, PAO-PA7,PBO-PB7
Yin = 0.4 to 2.4
V OH
Output high voltage
OTACK, 00-07
H2,H4, PBO-PB7, PAO-PA7
PCO-PC7
VOL
PINT
C in
Output low voltage
PC3/TOUT,PC5/PIRQ
+ 70 "C4,5
Limits
Min
Max
Unit
2.0
Vee
V
-0.3
0.8
V
10.0
p.A
±20
-1.0
p.A
mA
-0.1
ILOAD = - 400p.A, Vee = min
2.4
V
ILOAD= -150mA, Vee=min
I LOAD = -100mA, Vee = min
2.4
2.4
V
00-07, OTACK
I LOAD = B.BmA, Vee= min
I LOAD = 5.3mA, Vee= min
PAO-PA7, PBO-PB7,H2,H4,
PCO-PC2,PC4,PC6,PC7
V
0.5
V
0.5
V
ILOAD= 2.4mA, Vee= min
0.5
V
Power dissipation
TA=O"C
500
mW
Input capacitance
Vin=OV, T A =25"C, f=1MHz
15
pF
NOTES:
1.
2.
3.
4.
5.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is stress rating only and functional operation of the device
at these or at any other condition above those indicated in the operation section of this specification is not implied.
For operating at elevated temperatures, the device must be derated based on + 150~C maximum junction temperature.
This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static charge. Nonetheless, it is suggested
that conventional precautions be taken to avoid applying any voltages larger than the rated maxima.
Parameters are valid over specified temperature range.
All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0.4V and 2.4V with a transition time of 20ns maximum. All time
measurements are referenced at input voltages of O.BV and 2.0V and output voltages of O.BV and 2.0V as appropriate.
Signetics
4-123
4
MICROPROCESSOR DIVISION
JANUARY 1983
PARALLEL INTERFACE/TIMER
SCN68230
':US",,"".'i,
AC ELECTRICAL SPECIFICATIONS
Number
6.
7.
8.
9.
10.
11.
12.
13.
Vee= 5VDC ± 5%, Vss= OVDC, TA = O·V to 70·C (see figures 14-18)4,5
Tentative Limits
8MHz
10MHz
Min
Max
Min
Max
Characteristic
Unit
1
RIW, RS1-RS5 valid to CS low (setup time)
0
0
ns
215
CS low to RIW and RS1-RS5 invalid (hold time)
100
65
ns
36
47
CS low to ClK low (setup time)
30
20
CS low to data out valid (delay)
75
ns
60
ns
100
ns
60
ns
5
RS1-RS5, RIW valid to data out valid (delay)
6
ClK low to DTACK low (read/write cycle) (delay)
0
78
DTACK low to CS high (hold time)
0
0
8
CS or PlACK or TIACK high to data out invalid (hold time)
0
0
9
CS or PlACK or TIACK high to 00-07 high impedance (delay)
50
45
ns
10
CS or PlACK or TlACK high to DTACK high (delay)
50
30
ns
11
CS or PlACK or TlACK high to DTACK high impedance (delay)
100
55
12
Data in valid to CS low (setup time)
0
0
ns
13
CS low to data in invalid (hold time)
100
65
ns
14
Input data valid to H1(H3) asserted (setup time)
100
60
ns
15
H1(H3) asserted to input data invalid (hold time)
20
20
ns
16
Handshake input H1(H3) pulse width asserted
Handshake input H1(H3) pulse width negated
40
40
ns
17
40
40
18
H1(H3) asserted to H2(H4) negated (delay)
150
120
ns
19
ClK low to H2(H4) asserted (delay)
100
100
ns
20 9
H2(H4) asserted to H1(H3) asserted
21 10
22 14,16
ClK low to H2(H4) pulse negated (delay)
125
ns
3.5
clk per
3
clk per
140
70
0
0
2.5
23
elK low DMAREQ is asserted to ClK low on which DMAREQ is
negated
3
24
25 14,16
ClK low to output data valid (delay) (modes 0, 1)
Synchronized H1(H3) to output data invalid (modes 0, 1)
3.5
2.5
3
3
150
1.5
ns
2.5
1.5
ns
ns
0
125
Synchronized H1(H3) to ClK low on which DMAREQ is asserted
(see figures 6 and 7)
ns
ns
120
ns
2.5
clk per
This specification only applies if the PlfT had completed all operations Initiated by the previous bus cycle when CS was asserted. Following a normal read or write bus cycle,
all operations are complete within three elKs after the falling edge of the elK pin on which DTACK was asserted. If CS is asserted prior to completion of these operations,
the new bus cycle, and hence DTACK is postponed;
If all operations of the previous bus cycle were complete when CS was asserted, this specification is made only to insure that DTACK is asserted with respect to the falling
edge of the ClK pin as shown in the timing diagram, not to guarantee operation of the part. If the CS setup time Is violated, DTACK may be asserted as shown, or may be
asserted one clock cycle later.
Assuming the RS1-RS5 to data valid time has also expired.
This specification imposes a lower bound on CS low tIme, guaranteeing that CS will be low for at least 1 ClK period.
This specification assures recognition of the asserted edge of H1(H3).
This specification applies only when a pulsed handshake option is chosen and the pulse is not shortened due to an early asserted edge of H1{H3).
eLK refers to the actual frequency of the eLK pin, not the maximum allowable eLK frequency.
If the setup time on the rising edge of the clock Is violated, H1(H3) may not be recognized until the next rising edge of the clock.
This limit applies to the frequency of the signal at TIN compared to the frequency of the CLK signal during each clock cycle. If any period of the waveform at TIN Is smaller
than the period of the elK signal at that instant, then it is likely that the timer circuit will completely ignore one cycle of the TIN signal.
If these two signals are derived from different sources, they will have different instantaneous frequency variations. In this case the frequency applied to the TIN pin must be
distinctly less than the frequency at the CLK pin to avoid lost cycles of the TIN signal. With signals derived from different crystal oscillators applied to the TIN and CLK pins
with fast rise and fall times, the TIN frequency can approach 80 to 90% of the frequency of the ClK signal without a loss of a cycle of the TIN signal.
14.
15.
16.
If these two signals are derived from the same frequency source, then the frequency of the signal applied to TIN can be 100% of the frequency atthe CLK pin. They may be
generated by different buffers from the same signal or one may be an inverted version of the other. The TIN signal may be generated by an AND function of the clock and a
control signal.
The maximum value is caused by a peripheral access (H1(H3) asserted)) and bus access (CS asserted) occurring at the same time.
See Bus Interface Connection for exception.
Synchronized means that the Input signal has been seen by the PI/T on the appropriate edge of the clock (rising edge for H1(H3)) and failing edge for CS. Refer to Bus
Interface Connection for exception concerning es.
4·124
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68230
PARALLEL INTERFACE/TIMER
'RA""""·'"
AC Electrical Specifications (Continued)
vcc= 5VDC ± 5%, Vss= OVDC, TA = O'V to 70'C (see figures 14·18)4,5
Tentative limits
10MHz
Min
Max
Max
8M Hz
Characteristic
Number
Min
70
Unit
50
ns
70
ns
26
H1 negated to output data valid (modes 2, 3)
27
H1 asserted to output data high impedance (modes 2, 3)
0
28
Read data valid to DTACK low (setup time)
0
29
ClK low to data output valid (interrupt acknowledge cycle)
30 12
H1(H3) asserted to ClK high (setup time)
50
40
ns
31
PlACK or TIACK low to ClK low (setup time)
50
40
ns
32 16
Synchronized CS to ClK low on which DMAREQ is asserted
(see figures 6 and 7)
3
3
3
3
clk per
33 14,16
Synchronized H1(H3) to ClK low on which H2(H4) is asserted
3.5
4.5
3.5
4.5
clk per
60
ns
a
a
120
a
100
ns
120
0
100
ns
34
ClK low to DTACK low (interrupt acknowledge cycle) (delay)
35
ClK low to DMAREQ low (delay)
36
ClK low to DMAREQ high (delay)
70
0
ns
0
120
100
75
ns
A
ClK low to PIRQ low or high impedance
8 13
TIN frequency (external clock)-prescaler used
C
TIN frequency (external clock)-prescaler not used
a
a
0
TIN pulse width high or low (external clock)
55
45
ns
E
TIN pulse width low (run/halt control)
1
1
clk
250
F
ClK low to TOUT high, low, or high impedance
a
G
CS, PlACK, or TIACK high to CS, PlACK, or TIACK low
50
1
1/32
250
225
ns
a
1
Fclk(Hz)11
0
1/32
Fclk(Hz)11
a
30
225
ns
ns
CLOCK TIMING (see Figure 13)
Plrlmeter
f
teye
tCL
tCH
tCr
tCI
Frequency of operation
Cycle time
Clock pulse width
Clock pulse width
Clock rise time
Clock fall time
Min
2.0
125
55
55
8MHz
Max
8.0
500
250
250
10
10
Min
2,0
100
45
45
10MHz
Max
Unit
10,0
500
250
250
10
10
MHz
ns
ns
ns
ns
ns
Signetics
4·125
4
MICROPROCESSOR DIVISION
JANUARY 1983
PARALLEL INTERFACE/TIMER
'm",,""-·',
SCN68230
POWER CONSIDERATIONS
The average chip-junction temperature, TJ, in °c can be obtained from:
TJ=TA+IPDa/lJA)
Where:
(1)
T A'" Ambient Temperature, °c
/lJA" Package Thermal Resistance, Junction-to-Ambient, °C/W
PD iE PINT + PPORT
PINT=ICC x Vce, Watts - Chip Internal Power
PPORT'" Port Power Dissipation, Watts - User Determined
For most applications PpORT
;U
>
rrm
r-
...Z
m
;U
"TI
>
0
CLK
s::
0
'"
0
""C
~
0
en
en
0
m
'"CJ
~
en
0
Z
-...
m
I...
PA(PB)IJ.7
I...
.1
@
I.
@)
~
..J
4 CLOCKS (MAX) 0 MIN
m
---+----------~-===~.I
;U
Hl(H3)
en
i
H2(H4)
(INTL)
0
en
!V ·1'"
I.
@
iiMAiiEa
.1.
I.
@
,
~
.1
(35
"""K
@
.1
H2(H4)
(PULSED)
NOTE:
TIMING DIAGRAM SHOWS HI. H2. H3. AND H4 ASSERTED LOW
en
oZ
0C»
I\)
Figure 17. Peripheral Interlace Input Timing
W
o
~
~
C
-0
CD
'"
I
."
>
;0
>
rrm
r-
Z
.....
m
;0
"n
;;::
0AJ
0
i30"
m
en
en
0
AJ
0
<:
(ji
0
Z
>
0
eLK
-s::
m
.....
PA(PB)O·7
(MDO,1)
m
;0
PA(PB)O·7
(MD 2, 3)
H2(H4)
(PULSED)
H1(H3)
DMAREQ
H2(H4)
(INTL)
NOTE:
TIMING DIAGRAM SHOWS H1, H2, H3, AND H4 ASSERTED LOW.
en
oZ
.:..
N
Figure 18. Peripheral Interlace Output Timing
(\oJ
-<
W
~
z
c
o
co
}>
0C»
.1>0
'-
}>
AJ
-
t
~------------~~-~---"RQN
INTERRUPT
LOGIC &
REGISTER
IACKN
PIN DESIGNATIONS
PIN NO.
TYPE
DESCRIPTION
A1-A7
MNEMONIC
48-42
110
Address Lines: Active high, three·statable. In the MPU mode, these low order address lines spec·
ify which internal register of the DMAI is being accessed, In DMA mode, A1-A7 are outputs which
provide the low order address bits of the location being accessed. Three·stated in IDLE mode.
A8-A231
DO-D15
41-37
35-25
110
Address/Data Lines: Active high, three·statable. These lines are time multiplexed for data and ad·
dress leads. The lines OWNN, RWN, CSN, and DBENN are used to control the demultiplexing of
the address and data using external circuitry. In MPU mode, the bidirectional data lines (DO-D15)
are used to transfer data between the MPU and the DMAI. In DMA mode, A8-A23 provide the high
order address bits of the location being accessed. Three·stated in IDLE mode.
ASN
5
110
Address Strobe: Active low, three·statable. In MPU and IDLE modes, ASN is an input which indio
cates that the current bus master has placed a valid address on the bus. It is monitored by the
DMAI during bus arbitration to ascertain that the previous bus master has completed the current
bus cycle. In DMA mode, it is an output indicating that the DMAI has placed a valid address on the
bus.
UDSN
8
110
Upper Data Strobe: Active low, three·statable. In MPU and IDLE modes, UDSN is an input which
indicates that the upper data byte of the addressed word is being addressed. In DMA mode, it is an
output with the same meaning.
LDSN
6
110
Lower Data Stobe: Active low, three·statable. In MPU and IDLE modes, LDSN is an input which
indicates that the lower data byte of the addressed word is being addressed. In DMA mode, it is an
output with the same meaning.
R/WN
9
110
Read/Write: Active high for read, low for write, three·statable. In MPU mode, R/WN is an input
which controls the direction of data flow through the DMAI's input/output data bus interface and,
if required, through an external data bus buffer. R/WN high causes the DMAI to place the data from
the addressed register on the data bus, while R/WN low causes the DMAI to accept data from the
data bus. In DMA mode, R/WN is an output to memory and 110 controllers indicating the type of bus
cycle. It is held three·stated during IDLE mode.
Signetics
4·131
JANUARY 1983
MICROPROCESSOR DIVISION
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'm"elII"·"i
PIN DESIGNATIONS (Continued)
MNEMONIC
PIN NO.
TYPE
DESCRIPTION
CSN
4
I
Chip Select: Active low. When low, places the DMAI into the MPU mode. This input signal Is used
to select the DMAI for programmed data transfers. These transfers take place over DO-D15 as controlled by the R/WN and A1-A7 inputs. The DMAI is deselected when CSN is high. CSN is ignored
during DMA mode.
DTACKN
3
1/0
Data Transfer Acknowledge: Active low, three-statable. In MPU mode, DTACKN is asserted on a
write cycle to indicate that the data on the bus has been latched, and on a read cycle or interrupt
acknowledge cycle to indicate that valid data is present on the bus. The signal is negated (driven
high) when completion of the cycle is Indicated by negation of the CSN or IACKN input, and
returns to the inactive third state a short time after it is negated. In DMA mode, DTACKN is an input monitored by the DMAI to determine when the addressed device (memory) has latched the data
(write cycle) or put valid data on the bus (read cycle).
RESETN
24
I
Master Reset: Active low. Assertion of this pin clears internal control registers (see table 1), initializes the interrupt vector register to H 'OF', and sets the status register to the default value
B '0000 OOOX', where X is the state of RDYN. All bidirectional 1/0 lines are three-stated and the
DMAI is placed in the IDLE mode.
CLK
17
I
Clock: Active high. Usually the system clock, but may be any clock meeting the electrical specifications. Used by the DMAI to synchronize device functions and external control lines, and may not
be gated off at any time.
IRON
7
0
Interrupt Request: Active low, open collector. This output is asserted, if interrupts are enabled,
upon end of transfer, on occurrence of a bus error, and on receipt of an abort from the MPU. The
CPU can read the status register to determine the interrupting condition(s), or can respond with an
interrupt acknowledge cycle to cause the DMAI to output an interrupt vector on the data bus.
IACKN
10
I
Interrupt Acknowledge: Active low. When asserted, indicates that the current cycle is an interrupt
acknowledge cycle. The DMAI normally responds by placing the contents of the interrupt vector
register on the data bus and asserting DTACKN. IACKN is not serviced if the DMAI has not generated an interrupt request.
BRN
16
0
BGN
11
I
Bus Request: Active low, open collector. BRN is asserted by the DMAI to request ownership of the
bus after a DMA request is sensed on the REON input from the 1/0 device. It is negated when the
bus has been granted (BGN low) and BGACKN has been asserted, or, in burst DMA request mode,
if the 1/0 device negates its request at least one clock cycle before BGACKN is asserted.
Bus Grant: Active low. BGN indicates to the DMAI that it is to be the next bus master. This signal
is originated by the MPU and propagated via a daisy chain or other prioritization mechanism. After
BGN is asserted, the DMAI waits until DTACKN, ASN, and BGACKN have become inactive before
assuming ownership of the bus by asserting BGACKN.
BGOUTN
14
0
Bus Grant Output: Active low. Daisy chain output which is asserted by the DMAI when BGN is
asserted and the DMAI does not have a bus request pending.
BGACKN
15
1/0
Bus Graflt Acknowledge: Active low, three-statable. As an input, BGACKN is monitored by the
DMAI during the bus arbitration cycle to determine when it can assume ownership of the bus
(BGACKN negated). In DMA mode, it is asserted by the DMAI to indicate that it is the bus master.
Three-stated in MPU and IDLE modes.
RERUNN
23
I
Rerun: Active low. This input is asserted by external error detect logic to indicate a bus error. In
DMA mode, the DMAI stops operation and three-states the data, address, and control lines, except
BGACKN. It remains halted until RERUNN becomes inactive, and then re-tries the last bus cycle. If
RERUNN is asserted again, the DMAI sets the ERR bit in the status register, stops DMA operation,
releases the bus, and interrupts the CPU, if interrupts are enabled, responding with a special interrupt vector when IACKN is asserted. Not monitored in MPU and IDLE modes.
REON
22
I
DMA Request: Active low. This input from the 1/0 device requests service from the DMAI and
causes the DMAI to request control of the bus. In burst mode, the input is level sensitive, and the
DMAI releases the bus after REON is negated and the current DMA cycle is completed. In cycle
steal mode, the REON input is negative edge triggered. A negative going edge must occur at least
one clock cycle before DTCN is asserted to accomplish continuous transfer cycles.
ACKN
20
0
DMA Request Acknowledge: Active low. ACKN is asserted by the DMAI to indicate that it has
gained the bus and the requested bus cycle is now beginning. It is asserted at the beginning of
every bus cycle after ASN has been asserted, and is negated at the end of every bus cycle.
4·132
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'1SI""n,I.I'I
PIN DESIGNATIONS (Continued)
PIN NO.
TYPE
DESCRIPTION
RDYN
19
I
Device Ready: Active low. RDYN is asserted by the requesting device to indicate to the DMAI that
valid data has either been stored or put on the bus. If negated, it indicates that the data has not
been stored or presented, causing the DMAI to enter wait states. RDYN can be held low continuo
ously if the device is fast enough so that wait states are not required.
DTCN
21
0
Device Transfer Complete: Active low. In DMA mode, DTCN is asserted by the DMAI to indicate to
the device that the requested data transfer is complete. On a write to memory operation, it indio
cates that the data provided by the device has been successfully stored. On a read from memory
operation, it indicates to the device that the data from memory is present on the data bus and
should be latched.
DON EN
18
I/O
Done: Active low, open collector. As an output, DONEN is asserted by the DMAI concurrent with
the ACKN output to indicate to the device that the transfer count is exhausted and that the DMAl's
operation is completed as a result of that transfer. As an input; if asserted by the device before the
transfer count became zero, it causes the DMAI to abort service and generate an interrupt request,
if interrupts are enabled.
MNEMONIC
OWNN
2
0
Own: Active low, open collector. This output is asserted by DMAI during the DMA mode to indicate bus mastership. It can be used to enable external address/data and control butters. Inactive in
MPU and IDLE modes.
DBENN
1
0
Data Bus Enable: Active low, open collector. Asserted by the DMAI when CSN is asserted orwhen
IACKN is asserted and the DMAI has an interrupt request pending. Can be used to enable bidirectional data butters for DO-D15. Inactive in IDLE mode.
Vec
12
I
Power Supply: + 5 volt power input.
Vee
13
I
Power Supply: + 1.5 volt power input.
Vss
36
I
Ground: Signal and power ground input.
PIN DESCRIPTION
The Pin Designation table describes the
function of each of the pins of the DMAI.
Signal names ending in 'N' are active low.
All other signals are active high. In the
descriptions, 'MPU mode' refers to the
state when the DMAI is chip selected. The
term 'DMA mode' refers to the state when
the DMAI assumes ownership of the bus.
The DMAI is in the 'IDLE mode' at all other
tlmes_
In this data sheet signals are discussed
using the terms 'active' and 'inactive' or
'asserted' and 'negated' independent of
whether the signal is active in the high
(logic one) state or the low (logic zero)
state. Refer to the individual pin descriptions for the definition of the active level
of each signal.
REGISTERS AND COUNTERS
Register Map
The internal accessible register organization of the DMAI is shown in table 1. The
following rules apply to all registers:
1. A read from a reserved location in the
map results in a read from the the 'null
register'. The null register returns all
ones for data and results in a normal
bus cycle_ A write to one of these locations results in a normal bus cycle but
no write occurs.
2. Unused bits of a defined register are
read as indicated in the register
descriptions_
3. All registers are addressable as B-bit
quantities. To facilitate operation with
the 6BK MOVEP instruction, addresses
are ordered such that certain sets of
registers may also be accessed as
words or long words.
The operation of the DMAI is programmed
by writing control words into the appropriate registers. Operational feedback is provided via status registers which can be
read by the CPU. The contents of certain
control and status registers are initialized
on RESET.
To provide compatibility with the other
6BK family DMA controllers, control and
status bits are mapped In bit positions
equivalent to where they are located in the
register map of the other devices. Bits
which are used in the other devices but
not in the DMAI are assigned default values. If upward compatibility to the other
controllers is required, the programmer
should use these default values when
writing the control words to the registers,
although they have no effect in the DMAI.
When a register is read, the default value
is returned regardless of the value used
when the register is programmed. The default value is Indicated by '(x)' in unused
bit positions In the register formats, which
are Illustrated in table 2.
Signetics
Device Control Register (DCR)
/15J External Request Mode. This bit
selects whether the DMAI operates in
burst or cycle steal mode.
o
Burst mode. This mode allows a
device to request the transfer of
multiple operands using consecutive bus cycles. In this mode the
request (REON) line is an active low
input which Is asserted by the
device to request an operand transfer. The DMAI services the request
by arbitrating for the bus, obtaining
the bus, and notifying the peripheral by asserting the acknowledge
(ACKN) output. If the request line is
active when the DMAI asserts
ACKN, and remains active at least
until the DMAI asserts device
transfer complete (DTCN), the
DMAI recognizes a valid request for
another operand, which will be
transferred during the next bus cycle_ If the request line Is negated
before the DMAI asserts DTCN, the
DMAI relinquishes the bus and
walts for the next request.
Cycle steal mode. In this mode, the
device requests an operand transfer by generating a falling edge on
the request (REON) line. The DMAI
services the request by arbitrating
for the bus, obtaining the bus, and
4·133
4
JANUARY 1983
MICROPROCESSOR DIVISION
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'mn"ile'.iii
notifying the peripheral by asserting the acknowledge (ACKN) output. The request line must be in the
inactive state for at least one clock
cycle before a request Is made..
After a request has been asserted,
it must remain at the assertion
level for at least one clock cycle. If
another request is received before
the first operand part of a former
request is acknowledged, the second request is not recognized. Normally, the DMAI will relinquish the
bus after servicing a valid request.
However, if the device generates a
new request before the DMAI asserts DTCN for the last operand
part, the DMAI will retain ownership of the bus and that request
will be serviced before the bus is
relinquished.
[5:4) Operand Size. The programming of
these bits determine whether UDSN,
LDSN, or both are generated during the
transfer cycle and the increment by which
the memory address counter (MAC) is
changed In each transfer cycle.
00
01
Operation Control Register (OCR)
171 Direction
o
Transfer is from memory to device.
Transfer is from device to memory.
1
Byte. The operand size is 8 bits.
. The MAC is incremented by one
after each operand transfer. If the
LSB of the MAC is a '0', UDSN is
asserted during the transfer. If the
LSB of a MAC Is a '1', LDSN is
asserted during the transfer. The
transfer counter decrements by
one before each byte is transferred.
10
11
Word. the operand size is 16 bits.
The MAC is incremented by two
after each operand transfer. The
value of the LSB of the MAC is
Ignored and both UDSN and LDSN
are asserted during the transfer.
The transfer counter decrements
by one before each word is
transferred.
Long word. The operand size is 32
bits. The operand Is transferred as
two 16·blt words. The MAC is incremented by two after each 16-blt
word is transferred. The value of
the LSB of the MAC is ignored and
both UDSN and LDSN are asserted
during the transfer. The transfer
counter decrements by one before
the entire long word Is transferred.
Note that this mode is not implemented in the 68440.
Double word. The operand size is
32 bits. The operand is transferred
as a single 32·bit word. The MAC is
incremented by four after each operand transfer. The value of the two
LSBs of the MAC Is ignored (the A 1
output will always be a zero in this
mode) and both UDSN and LDSN
are asserted during the transfer.
The transfer counter decrements
by one before the double word is
transferred. Note that this mode is
not implemented in the 68440 or
68450; it is included in the DMAI to
support VME bus operations.
Table 1. DMAI ADDRESS MAP
ADDRESS BITS1,2
7
6
5
4
3
2
1
0
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
d
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
d
0
0
0
0
0
1
1
1
1
1
d
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
d
0
1
1
1
1
0
1
1
1
1
d
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
d
d
0
0
1
1
d
0
0
1
1
d
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
d
d
0
1
0
1
d
0
1
0
1
d
ACRONYM
REGISTER NAME
MODE
AFFECTED BY RESET
CSR
CER
Channel Status Register
Channel Error Register
Reserved
Reserved
Device Control Register
Operation Control Register
Sequence Control Register
Channel Control Register
Reserved
Reserved
Memory Transfer Counter High
Memory Transfer Counter Low
Memory Address Counter High
Memory Address Counter Middle High
Memory Address Counter Middle Low
Memory Address Counter Low
Reserved
Reserved
Reserved
Interrupt Vector Register
Reserved
Interrupt Vector Register
Reserved
Reserved
Channel Priority Reg ister
Reserved
Reserved
Reserved
R/W3
R
Yes
Yes
R/W
R/W
R/W4
R/W
Yes
Yes
Yes
Yes
R/W
R/W
R/W
R/W
R/W
No
No
No
No
No
No
R/W
Yes
R/W
Yes
R/W4
No
DCR
OCR
SCR
CCR
MTCH
MTCL
MACH
MACMH
MACML
MACL
IVR
IVR
CPR
RIW4
Notes:
1. AO= a forUDSN asserted, AO= 1 for LDSN asserted.
2. 'd' designates don't care.
3. A write to this register may perform a status resetting operation.
4. This register is a dummy register present only to provide compatibility with other 6SK family DMA controllers. A write to this register has no effect on the DMAI.
4·134
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'am''','',i.'ij
Table 2. REGISTER BIT FORMATS
DEVICE CONTROL REGISTER
BIT1S
EXTERNAL
REQUEST
MODE
DCR
0= BURST
1=CYCLE
STEAL
BIT14
BIT13
BIT12
BIT11
BIT10
BIT09
alTOS
NOT USED
(0)
NOT USED
(1)
NOT USED
(1)
NOT USED
(-)
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
, ,
·Should be programmed as '0 for SIZE (OCR[5:4J)= 00 and as 1 otherwise. When read, the value of thIs bit
is OCR(51.0R.OCR[4[.
OPERATION CONTROL REGISTER (OCR)
BIT07
BITOS
BITOS
DIRECTION
OCR
O=MEM TO
DEY
1=DEVTO
MEM
* Long
BIT04
BIT03
BIT02
BIT01
BITOO
NOT USED
(0)
NOT USED
(0)
NOT USED
(1)
NOT USED
(0)
4
OPERAND SIZE
00= BYTE
01 = WORD (1S BIT)
10=LONG WORD
11 = WORD (32·BIT)
NOT USED
(0)
word and 32-blt word modes are not supported by 68440. 32-blt word mode IS not supported by 68450.
SEQUENCE CONTROL REGISTER (SCR)
SCR
BIT1S
BIT14
BIT13
BIT12
BIT11
BIT10
BIT09
BIT08
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
NOT USED
(1)
NOT USED
(0)
NOT USED
(0)
BIT02
BIT01
BITOO
NOT USED
(0)
CHANNEL CONTROL REGISTER (CCR)
BIT07
BITOS
BITOS
START
CCR
O=NO
1=YES
NOT USED
(0)
NOT USED
(0)
BIT04
BIT03
SOFTWARE
ABORT
INTERRUPT
ENABLE
O=NO
1=YES
O=NO
1=YES
NOT USED
(0)
NOT USED
(0)
BIT10
BIT09
CHANNEL STATUS REGISTER (CSR)
BIT1S
CHANNEL
OPERATION
COMPLETE
CSR
O=NO
1=YES
BIT14
NOT USED
(0)
BIT13
BIT12
BIT11
NORMAL
DEVICE
TERMINATE
ERROR
CHANNEL
ACTIVE
O=NO
1=YES
O=NO
1=YES
O=NO
1=YES
BITOS
BIT04
BIT03
NOT USED
(0)
NOT USED
(0)
BIT02
BIT01
BIT08
READY
INPUT
STATE
O=LOW
1=HIGH
CHANNEL ERROR REGISTER (CER)
BIT07
BITOS
BITOO
ERROR CODE
CER
NOT USED
(0)
NOT USED
(0)
00000 = NO ERROR
01001 = BUS ERROR
10001 = SOFTWARE ABORT
NOT USED
(0)
CHANNEL PRIORITY REGISTER (CPR)
CPR
BIT07
BITOS
BITOS
BIT04
BIT03
BIT02
BIT01
BITOO
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
NOT USED
(0)
Signetics
4·135
MICROPROCESSOR DIVISION
JANUARY 1983
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'm""""·'i.,
Sequence Control Register (SCR)
This register serves no function in the
DMAI. It is Included only to provide com·
patibility with the programming for the
68440 and 68450 DMA controllers.
Channel Control Register (CCR)
successful or not, of any DMAI operation
and indicates that the DMA transfer has
completed. This bit must be cleared to
start another channel operation.
[13] Normal Device Termination. This bit is
set when the device terminates the DMAI
operation by asserting the DONEN line
while the device was being acknowledged.
This bit must be cleared to start another
channel operation.
[71 Start Operation
o
No start pending.
Start operation. The start bit is set
1
to initiate operation of the DMAI.
The memory address counter and
the memory transfer counter should
have been previously initialized,
and all bits of the channel status
register (CSR) should have previ·
ously been reset. The DMAI initio
ates operation by clearing any
pending requests, clearing the
start bit, and setting the channel
active bit in the CSR. The DMAI is
then ready to receive requests for
an operation. The channel cannot
be started if any of the internal
status bits in the eSR (CSR[15:11])
have not been cleared.
[11] Channel Active. This bit is set after the
channel has been started and remains set
until the channel operation terminates.
It is then automatically cleared by the
DMAI. The bit is unaffected by the write
operations.
A pending start cannot be reset by
a write to the register. START can
be cleared only by the DMAI when
it starts operation or by setting the
software abort bit (CCR[4]).
[8] Ready Input State. This bit reflects the
state of the RDYN input at the time the
CSR is read. The bit is a '0' if RDYN is low
and a '1' if RDYN is high. This bit is unaf·
fected by write or reset operations.
[4] Software Abort
o
Do not abort.
1
Abort operation. Setting this bit
terminates the current operation of
the DMAI and places it in the IDLE
state. The channel operation com·
plete and error bits in the CSR are
set, the channel active bit in the
CSR is reset, and an ABORT
ERROR condition is signaled in the
CER. Setting this bit causes a
pending start to be reset.
[3] Interrupt Enable
Interrupts not enabled.
1
Enable interrupts. An interrupt reo
quest is generated if the channel
operation complete bit in the CSR
is set. When the IACKN input is
asserted, the DMAI returns the nor·
mal interrupt vector if the error bit
in the CSR is not set, or the error
interrupt vector if error is set.
o
Channel Status Register (CSR)
A read of this register provides the status
of the OM AI. The COC, NOT, and ERR bits
can be cleared by writing a '1' to the bit
positions of the register which are to be
cleared. Those bit positions which are
written with a '0' remain unaffected.
[15] Channel Operation Complete. This bit
is set following the termination, whether
4·136
[12] Error. This bit is used to report that
the DMAl's operation was terminated due
to the occurrence of an error. The condi·
tion which caused the error can be deter·
mined by reading the channel error regis'
ter (CER). This bit must be cleared to start
another channel operation. When this bit
is cleared, the CER is also cleared.
Channel Error Register (CER)
[4:0] Error Code. This field indicates the
source of error when an error is indicated
in CER[12]. The contents of this register
are cleared when CER[12] is cleared.
00000 No error.
01001 Bus error. A bus error occurred duro
ing the last bus cycle generated by
the DMAI. See rerun description in
OPERATION section.
10001 Software abort. The channel opera·
tion was terminated by a software
abort command. See CCR[4].
Channel Priority Register (CPR)
This register serves no function in the
DMAI. It is included only to provide com·
patiblity with the programming for the
other 68K family DMA controllers.
Only the least significant 24 bits of the
counter (MACMH, MACML, and MACL) are
implemented in the DMAI. The most sig·
nificant byte of the counter, MACH, is pro·
vided only to allow compatibility with pro·
gramming of the 68440 and 68450. Writing
to MACH has no effect on the DMAI opera·
tion. Reading MACH always returns
H'OO'.
Memory Transfer Counter
(MTCH, MTCL)
The 16·bit memory transfer counter pro·
grams the number of operands to be trans·
ferred by the DMAI. The counter must be
initialized prior to beginning the transfer
of a block of data and then decrements
once per operand transfer (regardless of
operand size) until it reaches the terminal
value of zero. Channel operation then ter·
minates and the COC bit in the CSR will be
asserted.
Interrupt Vector Register (IVR)
The IVR contains the value to be placed on
the data bus upon receipt of an interrupt
acknowledge from the MPU. Only the
seven most Significant bits of the pro·
grammed value are used by the DMAI. The
output vector from the DMAI contains a
zero in the least significant bit position if a
normal termination occurred (error bit not
set) and contains a one in the least signifi·
cant bit position if termination was due to
an error (error bit set).
The contents of this register are initialized
to H 'OF' by a reset. The value returned
will be H'OF', regardless of the error
state, until the register is programmed by
the MPU.
To provide compatibility with the other
68K family DMA controllers, the IVR has
two addresses (see table 1). If program
compatibility is required, the value written
at the normal IVR address should have a
zero as its LSB, and the value written at
the error IVR address should be the same
but with the LSB equal to one.
OPERATION
Memory Address Counter
A DMAI operation proceeds In three princi·
(MACH, MACMH, MACML, MACL) pal phases. During the initialization phase,
The 32·bit memory address counter is
used to program the memory location
where the first operand to be transferred
is located or is to be transferred to,
depending on the direction of transfer.
The counter must be initialized prior to
beginning the transfer of a block of data
and then increments automatically de·
pending on the operand length, as de·
scribed in the Operation Control Register
description.
Signetics
the MPU configures the channel control
registers, loads the initial memory ad·
dress and transfer count, and starts the
channel. During the transfer phase, the
DMAI accepts requests for transfers from
the device, arbitrates for and acquires
ownership of the bus, and provides for ad·
dressing and bus controls for the trans·
fers. The termination phase occurs after
the operation Is complete, when the DMAI
reports the status of the operation.
MICROPROCESSOR DIVISION
JANUARY 1983
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'm""IIe1·'tJ
Operation Initiation
After having programmed the control registers, the memory address counter, and
the memory transfer counter, the MPU
sets the start bit (CCR[7]). The DMAI initiates the operation by clearing any pending requests, clearing the start bit, and
setting the channel active bit in the CSR.
The DMAI is then ready to receive valid requests for an operation.
The channel cannot be started if any of the
internal status bits in the CSR (CSR[15:11])
have not been cleared. An error is not signaled if this condition occurs. The only
indication of this state is that the start bit
remains set in the CCR. A pending start
cannot be reset by a write to the register.
START can be cleared only by the DMAI
when it starts operation or by setting the
software abort bit (CCR[4]).
Device/DMAI Communication
Communication between the peripheral
device and the DMAI is accommodated by
five signal lines:
Request (REQN). The device makes a request for service by asserting the request
line. The DMAI can operate in either the
burst request mode or the cycle stealing
request mode, as programmed by the
external request mode bit (DCR[15]).
The burst mode allows a device to request
the transfer of multiple operands using
consecutive bus cycles. In this mode the
request line is an active low input. The
DMAI services the request by arbitrating
for the bus, obtaining the bus, and notifying the peripheral by asserting the
acknowledge (ACKN) output. If the request line is active when the DMAI asserts
ACKN, and remains active at least until
the DMAI asserts device transfer complete (DTCN), the DMAI recognizes a valid
request for another operand, which will be
transferred during the next bus cycle. If
the request line is negated before the
DMAI asserts DTCN, the DMAI relinquishes the bus and waits for the next request. For long word transfers (2 x 16), the
request must be asserted at least until the
acknowledge for the second part of the
operand has been asserted.
In the cycle steal mode, the device requests an operand transfer by generating
a falling edge on the request line. The
DMAI services the request by arbitrating
for the bus, obtaining the bus, and notifying the peripheral by asserting the
acknowledge (ACKN) output. The request
line must be In the inactive state for at
least one clock cycle before a request is
made. After a request has been asserted,
it must remain at the assertion level for at
least one clock cycle. If another request is
received before the first operand part of a
former request is acknowledged, the second request is not recognized. Normally,
the DMAI will relinquish the bus after servicing a valid request. However, if the
device generates a new request before the
DMAI asserts DTCN for the last operand
part, the DMAI will retain ownership of the
bus and that request will be serviced
before the bus is relinquished.
Acknowledge (ACKN). The DMAI asserts
the acknowledge line, which implicitly addresses the device making the request,
during transfers to and from the device.
The line may be used to control buffering
circuits between the data bus and the
MPU bus.
Ready (RDYN). Ready is an active low input which is asserted by the requesting
device to indicate to the DMAI that valid
data has either been stored or put on the
bus. If negated, it indicates that the data
has not been stored or presented, causing
the DMAI to enter wait states until RDYN
is asserted. RDYN can be held low continuously if the device is fast enough so that
wait states are not required. The current
state of the ready input is reflected in
CSR[8j.
Done (DON EN). Done is a bidirectional active low signal. As an output, it is asserted
and negated by the DMAI concurrent with
the ACKN output of the last operand part
to Indicate to the device that the memory
transfer count is exhausted and that the
DMAI's operation is completed as a result
of that transfer.
The DMAI also monitors the state of the
line while acknowledging a device. If the
device asserts DON EN, the DMAI will terminate operation after the transfer of the
current operand. In this case the DMAI
clears the channel active bit and sets the
channel operation complete and normal
device termination bits in the CSR. If both
the DMAI and the device assert DON EN,
the device termination is not recognized,
but the operation does terminate.
Device Transfer Complete (DTCN). DTCN
is an active low output which is asserted
by the DMAI to indicate to the device that
the requested data transfer is complete.
On a write to memory operation, it indicates that the data provided by the device
has been successfully stored. On a read
from memory operation, it indicates to the
device that the data from memory is present on the data bus and should be latched.
DTCN is not asserted if assertion of the
RERUNN input terminates the bus cycle.
Signetics
Bus Arbitration
Upon receiving a valid request for a transfer from the device, the DMAI will arbitrate
for and obtain ownership of the system
bus.
The DMAI indicates that it wishes to
become the bus master by asserting its
bus request (BRN) output. This is a wireORed signal that indicates to the MPU
that some external device requires control
of the bus. The processor is effectively at
a lower priority level than external devices
and will relinquish the bus after it has
completed the last bus cycle it has
started. The processor puts the bus up for
external arbitration by asserting its bus
grant (BGN) output. This signal may be
routed through a daisy chain (such as provided by the DMAI) or through some other
priority-encoded network. When the DMAI
making the bus request receives the bus
grant (indicated by its BGN input being
asserted), it is to be the next bus master. It
waits until address strobe (ASN), data
transfer acknowledge (DTACKN) and bus
grant acknowledge (BGACKN) become inactive and then assumes ownership of the
bus by asserting Its own BGACKN output.
The DMAI then negates the BRN output
and proceeds with the data transfer
phase. After this phase is completed, the
DMAI relinquishes bus ownership by
negating the BGACKN output.
In burst DMA mode, detection of an active
low request input after the DMAI operation has been started will begin the bus
arbitration cycle. However, if the device
negates its request at least one clock
cycle before the DMAI asserts BGACKN,
the DMAI will negate its bus request and
will not assume ownership of the bus.
Data Transfers
The actual transfer of data between the
memory and the device occurs during the
data transfer phase. All transfers occur
during a single cycle except in the case of
long word operands, in which case two
cycles are used to transfer the operand as
two 16-bit words. The transfers take place
using a 'single address' protocol; the
DMAI addresses the memory via the bus
address lines, while the device is implicitly addressed via the acknowledge output.
When a request is generated using the request method programmed in the control
register, the DMAI obtains the bus and
asserts acknowledge to notify the device
that a transfer is to take place. The DMAI
asserts all S68000 bus control signals
needed for the transfer and holds them
until the device responds with ready. The
bus cycle then terminates normally. Ready
4·137
4
JANUARY 1983
MICROPROCESSOR DIVISION
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'm",,""·'"
may be tied low (asserted) if the device is
fast enough.
DONEN,the device termination is not recognized, but the operation does terminate.
When the transfer is from memory to the
device, data is valid when DTACKN is
asserted by the memory and remains valid
until the data strobe(s) are negated. The
assertion of DTCN from the DMAI can be
used to latch the data, as the data strobes
are not removed until one-half clock after
the assertion of DTCN.
Software Abort. The software abort bit
(CCR[4]) allows the MPU to abort the current operation of the DMAI. The COC and
error bits in the CSR are set, the channel
active bit in the CSR is cleared, and an
abort error condition is signaled in the
CER.
When the transfer is from device to
memory, the data must be valid on the bus
before the DMAI asserts the data
strobe(s). The device indicates valid data
by asserting ready. The DMAI then asserts
the strobes and holds them asserted until
the memory accepts the data, indicated by
the assertion of DTACKN. The DMAI then
asserts DTCN and negates the data
strobes.
Flow charts for these operations are
shown in figures 1 and 2. Refer to the timing section for the equivalent timing
diagrams.
Operation Termination
Termination of the block transfer occurs
under the conditions detailed below.
Terminal Count. As part of each transfer of
an operand, the DMAI decrements the
memory transfer counter. If this counter is
decremented to zero, the operand is the
last operand of the block. The DMAI operation is complete and it notifies the device
of completion by asserting the DONEN
output during the last operand transfer
cycle. When the transfer has been completed, the channel active bit in the CSR is
cleared and the COC bit is set.
Device Termination. The DMAI monitors
the state of the DONEN line while acknowledging a device transfer request. If the
device asserts DON EN, the DMAI will terminate operation after the transfer of the
current operand. When the transfer has
been completed, the DMAI clears the
channel active bit and sets the COC and
normal device termination bits in the CSR.
If both the DMAI and the device assert
4·138
Rerun Error. The DMAI provides a rerun input (RERUNN) to indicate a bus exception
condition. RERUNN must arrive prior to or
in coincidence with DTACKN in order to
be recognized, and the OM AI verifies that
the line has been stable for two clock
cycles before acting on it. The occurrence
of a rerun during a DMAI bus cycle forces
it to terminate the bus cycle in an orderly
manner.
When the assertion of rerun is verified, the
DMAI stops operation and three-states the
data, address, and control lines, except
BGACKN, so that it retains ownership of
the bus. It remains halted until rerun
becomes inactive, and then re-tries the
last bus cycle. If rerun is asserted again,
the OM AI stops DMA operation, releases
the bus, sets the error and COC bits in the
CSR, clears the active bit in the CSR, and
sets the error code in the CER to indicate
a bus error.
While stopped due to assertion of rerun,
the DMAI does not generate any bus
cycles and will not honor any requests
until it is removed. However, the OM AI still
recognizes requests.
Error Recovery Procedure. If an error occurs during a DMA transfer such that the
DMAI stops the DMA operation, information is available to the operating system
for an error recovery routine.
The information available to the operating
system consists of the memory address
counter, the memory transfer counter, and
the control, status, and error registers.
The DMAI decrements the memory transfer counter before attempting a DMA operation, so the register will contain the
Signetics
count minus one of the attempted transfer. The memory address counter will contain the address at which the DMA operation was attempted.
Reset. The reset input (RESETN) provides
a means of resetting and initializing the
DMAI from an external source. If the DMAI
is a bus master when reset is received, the
OM AI relinquishes the bus. Reset clears
the control and error registers, sets all bits
of the status register except CSR[8] to
zero, and initializes the interrupt vector
register to H 'OF'.
Interrupts. The interrupt enable bit
(CCR[3]) determines whether the DMAI
generates interrupt requests. When the bit
is set, an interrupt request is generated if
the channel operation complete bit in the
CSR is set. When the IACKN input is
asserted, and the DMAI has an interrupt
request pending, the DMAI returns an
interrupt vector on the data bus.
The interrupt vector issued is the contents
of the IVR. Only the seven most significant bits of the programmed value are
used by the DMAI. The vector from the
DMAI contains a zero in the LSB position
if a normal termination occurred (error bit
not set) and contains a one in the LSB
position if termination was due to an error
(error bit set).
The contents of this register are initialized
to H 'OF' by a reset. The value returned
will be H' OF', regardless of the error
state, until the register is programmed by
the MPU.
To provide compatibility with the other
68K family DMA controllers, the IVR has
two addresses (see table 1). 11 program
compatibility is required, the value written
at the normal IVR address should have a
zero as its LSB, and the val ue written at
the error IVR address should be the same
but with the LSB equal to one.
APPLICATIONS
Figure 3 illustrates a typical interconnection of the DMAI in a 68000 based system.
JANUARY 1983
MICROPROCESSOR DIVISION
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'pmll,,"".'ij
MEMORY
DMAI
DMAI
MEMORY
•
+
Initiate Request
1. Assert REON
Initiate Request
1. Assert REON
I
I
I
+ Bus
Acquire
t
Acquire Bus
1.
2.
3.
4.
5.
DEVICE
DEVICE
•
Address Memory
Set RWN to read
Place address on A1-A23
Assert ASN
Assert UDSN andlor LDSN
Assert ACKN
1.
2.
3.
4.
Address Memory
Set RWN to write
Place address on A1-A23
Assert ASN
Assert ACKN
4
I
t
I
Present Data
1. Place data on
data bus
2. Assert RDYN
•
Present Data
1. Decode address
2. Place data on data bus
3. Assert DTACKN
I
I
t
Enable Data
1. Assert UDSN andlor LDSN
t
Acquire Data
1. Load data
2. Assert RDYN
I
I
Acquire Data
1. Decode address
2. Load data
3. Assert DTACKN
•
Terminate Transfer
1. Assert DTCN
2. Negate UDSN andlor LDSN
and ASN
3. Negate ACKN and DTCN
I
+
Terminate Transfer
1. Assert DTCN
2. Negate UDSN andlor LDSN
and ASN
3. Negate ACKN and DTCN
I
Terminate Cycle
1. Negate DTACKN
I
I
t
Terminate Cycle
1. Negate DT ACKN
+
I
Relinquish Bus
I
+
or
Relinquish Bus
+
+
+ Cycle
Start Next
Start Next Cycle
or
t
Figure 1. Transfer from Memory to Device Flow Chart
Figure 2. Transfer from Device to Memory Flow Chart
Signetics
4·139
JANUARY 1983
MICROPROCESSOR DIVISION
SC868430
DIRECT MEMORY ACCESS INTERFACE (DMAI)
.tmlll"II,I.I"
~WN ~--------~------------------~
00-015
A8-A23
A1-A7
68000
CONTROL
LINES
Figure 3. DMAI Application
ABSOLUTE MAXIMUM RATINGS1
PARAMETER
RATING
UNIT
Supply voltages Vcc and Vee
Input voltage
Operating temperature range2
Storage temperature
-0.5 to +7.0
-0.5 to +5.5
o to +70
-65 to + 150
V
V
·C
·C
DC ELECTRICAL CHARACTERISTICS Vcc =5.0V ±5%, Vee= 1.5V ± 10%, TA=O·C to + 70·C3.4
PARAMETER
VIL
VIH
Input low voltage
Input high voltage
VOL
Output low voltage
VOH
Output high voltage,
all outputs except open collector outputs5
IlL
IIH
loc
Isc
Input low current
Input high current
Open collector off state current 5
Output short circuit current6
Icc
lee
NOTES:
Vee supply current
Vee supply current
TEST CONDITIONS
LIMITS
Min
Max
0.8
V
V
0.4
0.5
V
V
V
-400
20
20
-100
I'A
mA
130
450
mA
mA
2.0
IOUT=4mA
IOUT=8mA
lOUT = - 4OOl'A
VIN =0.4V
VIN=2.7V
VouT=2.4V
Vcc= max
Vcc= max, Vee= max
2.5
-40
UNIT
"A
"A
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. ThIs is stress rating only and functional operation of the device at
these or at any other conditions other than those indicated in the Electrical Characteristics section of this data sheet is not implied.
2. For operating at elevated temperatures, the device must be derated based on + 150°C maximum junction temperature.
3. Parameters are valid over specified temperature range.
4. All voltage measurements are referenced to ground (VSs). For testing, all signals swing between 0.4V and 2.4V with a tranSition time of 20ns maximum. All time measurements
are referenced at Input voltages of O.BV and 2.0V as appropriate.
5. IRaN, BRN, DON EN, and OWNN are open collector outputs.
6. No more than one output should be connected to ground at one time.
4·140
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCB68430
DIRECT MEMORY ACCESS INTERFACE (DMAI)
'W""lIeI.lij
AC ELECTRICAL CHARACTERISTICS Vee = 5.0V
± 5%, Vss= 1.5V ± 10%, TA=O·C to
+ 70·C3,4
TENTATIVE LIMITS
NO.
FIGURE
CHARACTERISTIC
8MHz
Min
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
41
43
44
45
46
47
48
49
50
51
52
53
54
55
56
4
4
4
4
4, 5
4
4
4
4, 5
4
4
4, 5
4, 5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
7
7,10,11
7, 10, 11
7
7
9
9
9
10,11
10,11
10,11
10,11
10,11
10, 11
10,11
10,11
10,11
10, 11
10,11
10,11
10, 11
10, 11
10,11
10,11
10,11
A1-A7, ASN, RWN setup to UDSN, lOSN low
00-015 3-state to invalid data from ASN, CSN,and UOSN or lOSN low
OTACKN 3-state to high from ASN, CSN,and UOSN or lOSN low
CSN low after UOSN or lOSN low
OBENN low after ASN and CSN low
00-015 valid data from ASN, CSN, and UOSN or lOSN low
OTACKN low after 00-015 valid data
A1-A7, ASN, RWN or CSN hold after UOSN and lOSN high
OBENN high from either ASN or CSN high
00-015 to 3·state from UOSN and lOSN high
00-015 to invalid data from UOSN and lOSN high
OTACKN high from UOSN and lOSN high
OTACK 3-state from either CSN or ASN high
A1-A7, ASN, RWN setup to UOSN, lOSN low
CSN setup before UOSN or lOSN low
OTACKN 3-state to high after CSN and ASN low
00-015 valid after UOSN or lOSN low
OTACKN low from UOSN or lOSN low
UOSN and lOSN low time
A1-A7 hold after UOSN and lOSN high
ASN, RWN and CSN hold after UOSN and lOSN high
00-015 hold after UOSN and lOSN high
OBENN low from last low of ASN, IACKN, lOSN
00-07 valid after last low of ASN, IACKN, lOSN
OTACKN 3-state to high after last low of ASN, IACKN, lOSN
OTACKN low after last low of ASN, IACKN, lOSN
OBENN high after first high of ASN, IACKN, lOSN
00-07 hold after first high of ASN, IACKN, lOSN
00-07 3-state after first high of ASN, IACKN, lOSN
OTACKN high after first high of ASN, IACKN, lOSN
OTACKN 3-state after first high of ASN, IACKN, lOSN
BRN high from ClK high
BGACKN low from ClK low
OWNN low from ClK high
BGACKN high from ClK low
OWNN high from ClK high (load dependent)
REQN setup before ClK low
REQN hold after ClK high
BRN low from ClK high
ASN, UOSN, lOSN, RWN 3-state to high from ClK low
A1-A23 3-state to valid from ClK high
ASN low from ClK high
lOSN, UOSN low from ClK high
ACKN low from ClK high
OTACKN setup to ClK high
ROYN setup to ClK low
OTCN low from ClK high
ASN high from ClK high
LDSN, UOSN high from ClK high
OTACKN, ROYN hold after ClK high
ASN, lOSN, UOSN high from OTCN low
ACKN high from ClK high
OTCN high from ClK high
Address valid after ClK low
Address valid after ASN high
OONEN (output) low from ClK low
Signetics
Max
10MHz
Min
0
10
10
0
0
UNIT
Max
25
45
95
30
45
80
10
55
85
50
20
10
35
100
95
0
0
0
65
100
100
110
50
60
80
60
95
45
75
55
75
30
20
75
75
85
50
60
55
30
30
55
75
90
0
0
50
50
10
0
120
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4·141
4
MICROPROCESSOR DIVISION
JANUARY ·1983
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'mn,,""·'fI
AC ELECTRICAL CHARACTERISTICS (Continued)
TENTATIVE LIMITS
NO.
FIGURE
8MHz
CHARACTERISTIC
Min
57
58
59
60
61
62
63
64
65
66
67
68
10,11
10,11
10,11
10,11
10,11
10, 11
11
11
12
12
12
12
DONEN (output) high from CLK high
DON EN (input) setup low before CLK low
DONEN (input) hold low after CLK high
BGACKN, ASN, UDSN, LDSN, RWN to 3·state from CLK low
OWNN high from CLK high
A1-A23 valid to 3·state from CLK high
R/WN low from CLK high
R/WN high from CLK high
RERUNN setup low before CLK high
RERUNN hold low from CLK high
A1-A23 to idle state from CLK low
A1-A23 to valid after CLK low
A1-A7
ASN
---t~
--i
Max
50
75
50
100
50
75
30
20
,
I
),.---
'-I------~I
AWN ____~~------------------------~---------
Figure 4. DMAI Read Timing
4·142
Signetics
UNIT
Max
30
0
__________~ll-----
I
10MHz
Min
100
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
JANUARY 1983
MICROPROCESSOR DIVISION
DIRECT MEMORY ACCESS INTERFACE (DMAI)
A1-A7
ASN
SCB68430
----iti..-----:,-I_ _ _ _-:-1-J+~111
I tr--
I
~1--1~@~
RWN
~
UDSN
LDSN
DBENN
00-015
DTACKN
=~~---,'I® r-
I
h
\ I
I I@r---II
f~-
tl
4
----:--II
II t i tJ ~
ti----'-i
--II- -
I I -\-
~I
-1H®
11""';-1---
I ~
\
iH-®
ff'------
----'-1---'--1---.'t
-------.j~@~,J-
=--i@~
Figure 5. DMAI Write Timing
Signetics
4-143
MICROPROCESSOR DIVISION
JANUARY 1983
SCB68430
DIRECT MEMORY ACCESS INTERFACE (DMAI)
':a"..IId.i'i
-I)-
Al-A7 - - ( ' -_ _ _ _ _ _ _ _ _ _ _ _ _
ASN
IACKN
\
I
~
1
\
__
f
---JI/~
RWN
I
I
UOSN
I
,--1
LOSN
OWNN
OBENN
00-07
DTACKN
I
\'-:----------'1
I
I
~ 't=r~
~
I-
'\
I-
Figure 8. CPU lACK Cycle to DMAI
4·144
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'm""IIe1.iij
ClK
BRN
SLflJ ~ V1 m lJlJlSL
"
.
"--______.....,1 ~ ~i?:--....(n~-------
~(-
BGN'
BGACKN
....J~~ ~~--«l~- - - - -
_ _ _ _ _J;;;...2
\...-----__
-1~
l~
----"""'-Ix
n
,
RWN---.....I
OWNN
------;..,-i~'---r
____i_'l
~~
---1l-@
A1-A23
ACKN
DTACKN
r
l
\~ ref
---~
RDYN - - - - - - - -
DTCN
r------~-
'lL1
',--------,I
u,...----
1~
--------J----bJ1
DONEN(OUT)
~~
------------------,1
DONEN(IN)
----------------~
\
',--------,I
r
1
\lJJ
NOTE:
1. 16-bit transfer illustrated. For a-bit transfer either LDSN or UDSN, but not both, will be asserted each cycle, depending on byte address.
Signetics
lr-®
r-~
r-~_59_ _ __
Figure 10. Read from Memory, Write to Device
4·148
tr---
JANUARY 1983
MICROPROCESSOR DIVISION
SCB68430
DIRECT MEMORY ACCESS INTERFACE (DMAI)
'BfA"eI"".'lj
ClK
BGACKN
1~
1\
ASN
lr-®
t
II J\
I
f--@
UDSN
lDSN
RWN
OWNN
Al-A23
ACKN
1~
I}
1\
\
t
~\@r-
Q1~
fflI'
\
(
,
-lj®
)-
X
,-
1~
I
J\
I
~r
\
~r
\
n
t
~~
t
1~
LJj
j~ 1
4
ihY
-If-®
DTACKN
DTCN
I~
®-1r~~
I-@
RDYN
~
I~
t
--1~
rn
\
It
\
I;
II
\
/
\
DONEN(OUT)
/
~~
1\
IKV
@-1rLJj
1~
DON EN (IN)
,
~
Figure 11. Write to Memory. Read from Device
NOTE:
1. 16-blt transfer Illustrated. For B-blt transfer either LDSN or UDSN, but not both, will be asserted each cycle, depending on byte address.
Signetics
4·149
MICROPROCESSOR DIVISION
JANUARY 1983
DIRECT MEMORY ACCESS INTERFACE (DMAI)
SCB68430
'.""II,I.'ii
ClK
BGACKN
\
\
\
ASN
UOSN
lOSN
L
L
L
/
/
/
\
\
\
/
/
/
RWN
OWNN
Al·A23
- j r-®
- j J--®
(,--------:-,1~r--------,X
/
\
DTACKN
ROYN
OTCN
RERUNN
\
/
LJ
--1
--\\...:....1_65__1---<1
/
L
/
LJ
LJ
\..
\
Figure 12. Rerun Asserted During Read from Memory, Write to Device
NOTES:
1. 16-blt transfer Illustrated. For a·bit transfer either LDSN or UDSN, but not both, will be asserted each cycle, depending on byte address.
2. DMAI will release the bus after a RERUNN if there is no valid request. The next request will then retry the cycle which was terminated by the RERUNN signal.
3. RERUNN must be asserted no later than DTACKN and RDYN.
4. If a cycle is terminated by RERUNN, the transfer count will he one less than the actual data transferred correctly. The double RERUNN signal on the same cycle will terminate the DMAI operation with a status bit set and an Interrupt generated (if enabled).
4·150
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
MEMORY MANAGEMENT UNIT
SCN68451
PRODUCT BRIEF, contact your Signetics sales offices for complete information.
DESCRIPTION
FEATURES
The SCN68451 Memory Management Unit
(MMU) provides address translation and
protection of the 16-megabyte addressing
space of the SCN68000. The MMU can be
accessed by any potential bus master,
such as instruction set processors, or
DMA controllers. Each bus master (or processor) in the SCN68000 family provides a
function code and an address during each
bus cycle. The function code specifies an
address space while the address specifies
a location within that address space. The
function codes are provided by the
SCN68000 to distinguish between program
and data spaces as well as supervisor and
user spaces. This separation of address
spaces provides the basis of protection in
an operating system. By simplifying the
programming model of the address space,
the MMU also increases the reliability of a
complex multiprocess system.
• Separates address spaces of system
and user resources
• Provides write protection
• Increases system reliability
• Provides efficient memory allocation
• Allows interprocess communication
through shared resources
• Simplifies programming model of ad·
dress space
Minimizes operating system overhead
with quick context switches
32 segments with variable segment
sizes
Multiple MMU system capability
• Supports both paging and segmentation
• DMA compatible
• Provides virtual memory support
• SCN68000 bus compatible
FUNCTIONAL DIAGRAM
A8-A23
A1-AS---+-
:~o~_
l
MEMORY
MANAGEMENT
UNIT CONTROL
R/W _ _
cs~
AS~
UDS
DTACK
) MULTIPLEXER
CONTROL
SCN68451
IRQ
} GLOBAL
HANDSHAKE
LINES
BERR
RESET
MAPPING LOGICAL SEGMENTS TO PHYSICAL MEMORY
eLK---+-
FC1
Vcc---""
~FC2
GNO----"
~FC3
READ
ONLY
READ
ONLY
A
READI
WRITE
SHARED
DATA
UNDEFINED
READ
ONLY
A
B
READ
ONLY
UNDEFINED
READI
WRITE
READI
WRITE
PHYSICAL
MEMORY
LOGICAL ADDRESS SPACE
Signetics
4·151
4
MICROPROCESSOR DIVISION
JANUARY 1983
INTELLIGENT MULTIPLE DISK CONTROLLER (IMDC)
SCN68454
PRODUCT BRIEF, contact your 5ignetics sales office for complete information.
00-015
BRN
BGN
BGACKN
IRON
IACKN
RIWN
DTACKN
The IMDe structure utilizes two
sophisticated processing interfaces-a
host interface and a disk drive interface.
The host interface is compatible with the
568000 bus. Included in this interface is a
complete OMA controller capable of
handling all data transfers between the
host system memory and the drives con·
nected to the IMDe. The disk drive inter·
face is designed to conform to different
drive interface requirements, thus giving
the IMOe the ability to control a variety of
drive types. With a minimum of external
hardware, it can control any drive that has
an 5A1000 or 5eagate 5T500 drive inter·
face standard. The IMOe also provides
direct support for double density track for·
mats and standard IBM track formats for
floppy disks.
Data transfers on the host data bus can be
programmed for either 8 or 16·bit parallel
operation. The disk drive interface handles
a serial data rate up to 10Mbits per sec·
ond, a speed which accommodates the
next generation of drives.
Programming of the IMOe is performed
through a powerful set of high level in·
structions. A user can create the required
drive interface by simply altering the con·
tent of drive control memory storage
areas. Included in the instruction set are
commands to format disks to user
specification, multiple sector read/write
operations with implied seeks,
diagnostics, and programmable real time
record processing.
LDSN
UDSN
ASN
Al,A2
CSN
LOCAL
REDAT
DDIR
OWNX
WRGATE
WRCLOCK/RCLOCK
SECTOR/INDEX
RERUN
WRDAT
RESN
SCLK
WRCLK
TICKLER
vee
GND
•
FEATURES
•
Combined control for hard disk and
floppy disk
- Any combination up to 4 drives
- Built·ln logic for floppy disk back·up
• Winchester disk Interface (SA1000 and
ST500)
• Supports MFM, FM and NRZ data for·
mats
• Soft sector and hard sector
Supports programmable hard disk and
standard IBM formats
Supports linked, mapped and sequen·
tial file structures
Multiple sector read/write
Implied seek
Error correction up to 11 bits
32·blt and 4O·bit ECC codes, program·
mabie polynomials
·
·
··
··
The IMOe circuitry Is fully TTL compati·
ble, operates with a single + 5 volt power
supply and is contained in a 48 pin DIP
package.
4·152
SCNB8454
IMDC
Signetics
•
•
•
•
•
•
•
Supports computer generated error
correction code
Control signals for external phase
locked loop
Data rate up to 10Mbits per second
Automatic bad sector handling
Single phase read and write clocks
8/16·bit data bus
DMA control and transfer
High level commands
Controls
Data transfer
Programmable real time record pro·
cessing
Diagnostics
Error correction
JANUARY 1983
MICROPROCESSOR DIVISION
SCB68459
DISK PHASE LOCKED LOOP (DPLL)
PRODUCT BRIEF, contact your Signetics sales office for complete information.
DESCRIPTION
The SCB68459 Disk Phase Locked Loop
(DPLL) is a single chip bipolar digital!
analog circuit designed for hard disK and
floppy disk applications. This circuit offers high performance and reliability unmatched by discrete design. It is ideally
suited for use with the SCN68454 Intelligent Multiple Disk Controller (IMDC).
The SCB68459 DPLL operates by producing
an oscillator frequency to match the fre·
quency of an input signal f i. In this locked
condition, any slight change in fi (jitter)
first appears as a change in phase between fi and the oscillator frequency. This
phase shift then acts as an error signal to
change the frequency of the local DPLL
oscillator to match f i.
The DPLL architecture utilizes two interfaces-a controller interface and a disk
drive interface. Included in the controller
interface are data (read/write), clock (read/
write), tickler (for internal multiplexing
control) and other control signals. These
interface signals are connected directly
to/from the SCN68454 IMDC. On the other
hand, the disk interface consists of
primarily the data (read and write) and
other control signals depending on disk
type.
The VCO is a programmable oscillator pro·
grammed via the use of an external
capacitor. It functions as a current to fre·
quency converter (or voltage to frequency
converter). The VCO provides a read/
write clock to the SCN68454 IMDC.
The prescaler is a divider. If FM modula·
tion is used, the divider performs divide by
2; if MFM then divide by 1. The prescaler
output presents the reference frequency
to the phase detector.
The data regenerator's main function is to
clean up the jittery input signals before
delivering it to the precompensation circuit.
The precompensation circuit will advance
or delay the pulse train before writing onto
the disk in the form of composite data.
The precompensating algorithm is programmed onto the chip.
When the DPLL is used with the
SCN68454 IMDC, the clock and data
separation and address mark detection
are actually performed by the IMDC.
FEATURES
• On chip multiplexer for read/write data
and free-running clock
• Circuit operates from a single + 5V
supply
• Supports composite data rate of 20MHz
• Loop filter bendwidth of 2MHz
• Supports MFM and FM modulation
• Phase detector with
TTL inputs
50% duty cycle for inputs
Adjustable gain
No phase reversal at inputs
Capture range not to exceed lock
range
• Voitage·controlled·osclllator with
Programmable oscillator
Fast slew rate
Minimum drift due to temperature
Minimum phase jitter
Buffered output
• Electrical isolation between digital
logic and high frequency analog circuit
• TTL compatible Inputs and outputs
• External loop gain control
FUNCTIONAL PIN DIAGRAM
For each disk type (i.e. SA1000 Win·
chester, or floppy disk), one DPLL circuit
can be used to support up to four drives. If
a Winchester disk and a floppy disk are
used, two DPLL circuits are required.
The architecture of the DPLL is basically a
feedback system comprised of the following:
• Phase detector (comparator)
• Low pass filter and error amplifier
• Voltage controlled oscillator (VCO)
• Prescaler (or divider)
• Data regenerator
• Precompensation circuit
WRDAT
____ XTAL1
WRCLK
........-- XTAL2
REDAT
RCLOCKIWCLOCK
EARLY DATA
TICKLER
CEN
PRESCALEN
WRITE DATA
READ DATA
Vee
GND
VCO IN
PUMP DOWN
The phase detector compares the phase
and frequency of the incoming signal with
the VCO frequency and generates an error
voltage that is related to the phase and fre·
quency difference between the two
signals.
PUMP UP
FREQPUMP
____ CAP1
CAP2
CENTERFREQ
The low P;;lSS filter serves a dual function:
first, by attenuating the high frequency error components at the output of the phase
comparator, it enhances the interference
rejection characteristics; second, it provides a short-term memory for the PLL and
ensures a rapid recapture of the signal.
Signetics
4·153
4
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL UNIVERSAL SERIAL COMMUNICATIONS CONTROLLER
SCN68562
PRODUCT BRIEF, contact your Signetics sales office for complete information.
DESCRIPTION
The Signetics SCN68562 Dual Universal
Serial Communications Controller
(DUSCC) is a single chip MOS·I.,SI com·
munications device that provides two in·
dependent, multi-protocol, full duplex
receiverltransmitter channels in a single
package. The DUSCC supports bit
oriented and character oriented (byte
count and byte control) synchronous data
link controls as well as asynchronous pro·
tocols. The logic for both channels pro·
vides formats, synchronization, and vali·
dation for data transferred to and from the
channel interface.
The SCN68652 interfaces to the SCN68000
MPU via asynchronous bus control sig·
nals and is capable of program polled, in·
terrupt driven, or DMA data transfers.
DUSCC FUNCTIONAL PINOUT
RXOA
00-07
TXOA
Al-A6
TRXCA
RTXCA
R/WN
OTACKN
CSN
RESET
IRON
CTSAN/LCAN
OCOAN/SYNINA
RTXORQAN/GP01AN
SCN68562
ouscc
TXOROAN/GP02AN/RTSAN
IACKN
RXOB
TXOB
Xl/CLK
TRXCB
X2/IOCN
RTXCB
vee
CTSBN/LCBN
DCDBNfSVNINB
GNO
RTXOROBN/GPOIBN
TX 0 ROB N/G P02BN/RTSB N
RTXOAKAN/GPIIAN
Each channel of the DUSCC consists of a
receiver, a transmitter, a 16·bit multi·
function counterltimer. a digital phase
locked loop (DPLL), a parity/CRC gen·
erator and checker, and associated con·
trol circuits. The operating mode and data
format of each channel can be pro·
grammed independently. The two chan·
nels share a common bit rate generator
(BRG), operating directly from a crystal or
an external clock, which provides sixteen
common bit rates simultaneously. The
receiver and transmitter of each channel
can independently select its operating
rate from the BRG, the DPLL, the
counter/timer, or from an external 1x or
16x clock. making the DUSCC well suited
for dual speed channel applications.
The transmitter and receiver each contain
a four-deep FIFO with appended com·
mand and status bits and a shift register.
This permits reading and writing of up to
four characters at a time, minimizing the
potential of receiver overrun or transmitter
underrun, and reducing interrupt or DMA
overhead. In addition, a flow control
capability is provided to disable a remote
transmitter when the FIFO of the local
receiving device is full.
Two modem control inputs (DCD and CTS)
are monitored by the control logic and
three modem control outputs (RTS and
two general purpose) are controlled by the
CPU. All of the modem control inputs and
outputs are general purpose in nature and
optionally can be used for functions other
than modem control.
The register set for each channel includes
two mode registers, two SYN registers
(also used for the BOP secondary
4-154
RTXOAKBN/GPllBN
TXOAKAN/GPI2AN
48·PIN
VERSION ONLY
TXOAKBN/GPI2BN
OleN
OONEN
SYNOUTAN/RTSAN
SYNOUTBN/RTSBN
address), transmitter parameter and tim·
ing registers, receiver parameter and timing registers, two counter/timer preset
registers, two counter/timer value
registers, counter/timer control register,
output and rniscellaneous register, pin
configuration register, channel command
register, TxFIFO, RxFIFO, three status
registers, and interrupt enable and priority
registers.
FEATURES
General Features
•
•
•
Associated with the logic for both channels is an interrupt control register and a
general status register that can be read
through either channel. A modified vector
register, read through channel B, contains
the programmed interrupt vector with
three bits of prioritized encoded status inserted. An unmodified vector register,
read through channel A, contains the vector as programmed. The vector is programmed by writing to the vector register
through channel A or B and can be programmed to be output on the data bus in
response to receipt of an interrupt
acknowledge cycle.
There are two versions of the DUSCC. The
standard version is packaged in a 48·pin
DIP. A 40-pin version provides all of the
features, but is limited to dual·address
transfers during DMA operation.
Signetics
•
•
•
•
•
•
Dual full-duplex synchronous/asyn.
chronous receiver and transmitter
Multi'protocol operation
BOP: HDLC/ADCCP, SDLC, SDLC
loop, X.25 or X.75 link level, etc.
COP: BISYNC, DDCMP, X.21
ASYNC: 5·8 bits plus parity
Four character receiver and transmitter
FIFOs
Programmable bit rate for eaCh.
receiver and transmitter selectable
from:
16 fixed rates: 50 to 38.4K baud
One user defined rate derived from
programmable counter/timer
External 1x or 16x clock
Digital phase locked loop
Parity and FCS (LRC or CRC) genera·
tion and checking
Programmable data encoding/
decoding: NRZ, NRZI,FMO, FM1, Man·
chester
Programmable channel mode: full/half
duplex, autoecho, or local loopback
Programmable data transfer mode:
polled, interrupt, DMA, wait
DMA interface
Compatible with 568000 DMA
controllers
JANUARY 1983
MICROPROCESSOR DIVISION
DUAL UNIVERSAL SERIAL COMMUNICATIONS CONTROLLER
Hall or full duplex operation
Single or dual address data
transfers
Automatic frame termination on
terminal count or DMA 'DONE'
• Interrupt capabilities
Interrupt daisy chain option
Interrupt vector output (fixed or
modified by status)
Programmable internal priorities
68K, 8080/85, and 8086/88 compatl·
ble modes
• Multi·function programmable 16·bit
counterltlmer
Bit rate generator
Event counter
Count characters received or
transmitted
Delay generator
Automatic bit length measurement
• Modem controls
RTS, CTS, DCD, and up to four
general purpose I/O pins per chan·
nel
CTS and DCD are programmable
auto·enables for Tx and Rx
Programmable interrupt on change
of CTSor DCD
• On·chip oscillator for crystal
• TTL compatible
• Single + 5V power supply
• 4O/48·pin DIP
Asynchronous Mode Features
•
•
Character length: 5 to 8 bits
Odd or even parity, no parity, or lorce
parity
•
Up to two stop bits programmable in
1/16 bit increments
• 1x or 16x Rx and Tx clock lactors
• Parity, overrun, and Iraming error
detection
• False start bit detection
• Start bit search 112 bit time alter Iram·
ing error detection
• Break generation with handshake lor
counting break characters
• Detection 01 start and end 01 received
break
• Character compare with optional inter·
rupt
Character Oriented Protocol
Features
•
•
•
•
•
•
•
•
•
•
•
Character length: 5 to 8 bits
Odd or even parity, no parity, or lorce
parity
LRC or CRC generation and checking
Optional opening PAD transmission at
beginning 01 Irame
Optional auto hunt mode and closing
PAD check alter EOT or NAK
One or two SYN characters
External sync capability
SYN detection and optional stripping
(all or leading SYNs only)
SYN or MARK linenll on underrun
Idle in MARK or SYNs
Handling 01 EBCDIC and ASCII
BISYNC text messages, including CRC
generation, SYN and OLE stripping,
end·ol·message detection, and trans·
parent mode switching. Automatic in
receive and semi·automatic in transmit
Signetics
•
SCN68562
Parity, FCS, overrun, and underrun er·
ror detection
Bit Oriented Protocol Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Character length: 5 to 8 bits with 0 to 7
bits residual character
Detection 01 received residual
character: 0·7 bits
Automatic switch to programmed
character length lor I lield
Zero insertion and deletion
Optional opening PAD transmission at
beginning 01 Irame
Detection and generation of FLAG,
ABORT, and IDLE bit patterns
Detection and generation of shared
(single) FLAG between Irames
Detection 01 overlapping (shared zero)
FLAGs
ABORT, ABORT·FLAGs, or FCS·FLAGs
line fill on underrun
Idle in MARK or FLAGs
Secondary address recognition in·
cluding group and global address
Single or dual octet secondary address
Extended address and control fields
Short frame rejection for receiver
Detection and notification of received
end of message
CRC generation and checking
SDLC loop mode capability
4·155
4
JANUARY 1983
MICROPROCESSOR DIVISION
SCN68681
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
'm",,""··,.,
DESCRIPTION
FEATURES
The Signetics SCN68681 Dual Universal Asynchronous Receiver/Transmitter
(DUART) is a single chip MOS-LSI communications device that provides two independent full-duplex asynchronous
receiver/transmitter channels in a single
package. It is compatible with other
S68000 family devices, and can also interface easily with other microprocessors.
The DUART can be used in polled or interrupt driven systems.
• S68000 bus compatible
• Dual full·duplex asynchronous receiver/
transmiter
• Quadruple buffered receiver data regis'
ters
• Programmable data format
-S to 8 data bits plus parity
-Odd, even, no parity or force parity
-1, 1.S or 2 stop bits programmable in
1116 bit increments
• Programmable baud rate for each reo
ceiver and transmiter selectable from:
-18 fixed rates: SO to 38.4K baud
-One user defined rate derived from
programmable timer/counter
- External 1x or 16x clock
The operating mode and data format of
each channel can be programmed independently. Additionally, each receiver and
transmitter can select its operating speed
as one of eighteen fixed baud rates, a 16x
clock derived from a programmable
counter/timer, or an external 1x or 16x
clock. The baud rate generator and
counter/timer can operate directly from a
crystal or from external clock inputs. The
ability to independently program the
operating speed of the receiver and transmitter make the DUART particularly attrac·
tive for dual-speed channel applications
such as clustered terminal systems.
Each receiver is quadruply buffered to
minimize the potential of receiver overrun
or to reduce interrupt overhead in interrupt driven systems. In addition, a flow
control capability is provided to disable a
remote DUART transmitter when the buf·
fer of the receiving device is full.
Also provided on the SCN68681 are a mUltipurpose 6-bit input port and a mUltipurpose 8-bit output port. These can be used
as general purpose I/O ports or can be
assigned specific functions (such as clock
inputs or status/interrupt outputs) under
program control.
PIN CONFIGURATION
vee
IP4
IPS
IACKN
IP2
CSN
RESETN
X2
XllCLK
RxOA
RxDB
TxOA
TxDB
• Parity, framing, and overrun error detec·
tion
OP1
OPO
• False start bit detection
• Line break detection and generation
OP3
OP2
OPS
OP4
• Programmable channel mode
-Normal (full duplex)
-Automatic echo
- Local loopback
- Remote loop back
• Multi·function programmable 16·bit
counterltimer
• Multi·function 6·bit input port
-Can serve as clock or control Inputs
-Change of state detection on four
inputs
• Multi·function 8-bit output port
-Individual bit set/reset capability
-Outputs can be programmed to be
status/interrupt signals
• Versatile interrupt system
-Single interrupt output with eight
maskable interrupting conditions
-Interrupt vector output on interrupt
acknowledge
OP7
OP6
01
DO
03
02
OS
04
07
06
INTRN
GNO
TOP VIEW
-Output port can be configured to pro·
vide a total of up to six separate wire·
OR'able interrupt outputs
• Maximum data transfer: 1X - 1MB/sec,
16X - 12SKB/sec
• Automatic wake·up mode for multidrop
applications
• Start·end break interrupt/status
• Detects break which originates in the
middle of a character
• On·chip crystal oscillator
• TTL compatible
• Single + SV power supply
ORDERING CODE
PACKAGES
4·156
Vcc =SV:!:S%,T A =0°Ct070°C
Ceramic DIP
SCN68681 C1140
Plastic DIP
SCN68681 C1 N40
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN68681
'm""iI"-"t
BLOCK DIAGRAM
r00-07
8
<
/
~
I
CHANNEL A
K
BUS BUFFER
j.;:::=
r-
TRANSMIT
HOLDING REG
TxDA
4
TRANSMIT
SHIFT REGISTER
OPERATION
CONTROL
RIWN
DTACKN
•
CSN
A1-A4
RESETN
4/
/
I
~
I-RECEIVE
HOLDING REG
I r---
ADDRESS
DECODE
I
RIW CONTROL
(3)
I
RxDA
RECEIVE
SHIFT REG
~
BiB
CRA
SRA
INTERRUPT
CONTROL
INTRN
I
IACKN
1-
~
I
ISR
I
I
IVR
I
II>
.,
INPUT PORT
d
-.J/I
C S N - - - - . \ \ . -_ _ _ _
OPO-OP7 _ _ _ _ _ _ _ _0_L_D_D_A_TA_ _ _ _ _ _
__
j 'r-J~
~
IpD
4
NEW DATA
f-
Figure 5. Port Timing
CSN
(READOR~
WRITE)
\
~
I_=-~-----J-+r"R
INTERRUPT
OUTPUT'
*INTRN or OP3-0P7 when used as interrupt outputs.
Figure 6. Interrupt Timing
+5V
CLOCK
, . . - - - - i : ) o - - - _ T O OTHER
CHIPS
74LS04
CI: 10-15pF + (STRAY < 5pF)
C2: 0-5pF + (STRAY < 5pF)
. . - - -....- - i X I
XlICLK
CT~;~
___
-J
TxC
CJ
68681
L---+---tX2
3.6864MHz
CRYSTAL SERIES RESISTANCE SHOULD
BE LESS THAN 180 OHMS.
Figure 7. Clock Timing
Signetics
4·173
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN68681
'm""",i.!,,
TxC
(INPUT)
---t
h.
(10~~~6L~~KS)
~
-"~ll----_~
'i
Txc_jOo.f-(1X OUTPUT)
/
Figure 8. Transmit Timing
Figure 9. Receive Timing
TxD
TRANSMITTER
ENABLED
TxRDY
(SR2)
CSN
(WRITE)
CTSN1
(IPO) _ _ _- - '
I
I
~~~~~L--------------------------------------------------------~~~----=
=
OPR(O)
1
OPR(O)
NOTES
1. TIMING SHOWN FOR MR2(4) = 1.
2. TIMING SHOWN FOR MR2(5) = 1.
Figure 10. Transmitter Timing
4·174
Signetics
1
MICROPROCESSOR DIVISION
JANUARY 1983
DUAL ASYNCHRONOUS RECEIVER/TRANSMITTER (DUART)
SCN68681
'am""JleI.iti
R,D
RECEIVER
ENABLED
RxRDY
(5RO) _ _ _ _ _ _ _--'
FFULL
(5R1) _ _ _ _ _ _ _ _ _ _ _
-I___________---'
AxRDY/-------.....,
FFULL
(OP4)2
4
CSN
(READ)
ST~US~TA
01
OVERRUN
(5R4) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
-04--
+ ___...:;..---'
"
RESET BY COMMAND
RTS1
(OPO)
OPR(O)=1
NOTES
1. TIMING SHOWN FOR MR1cn= I.
2. SHOWN FOR OPCR(4) = 1 AND MR1(6)=O.
Figure 11. Receiver Timing
MASTER STATION
BIT9
BIT9
IADD"! ,1
DO
I
I
!oI
BIT9
L'I-:'_______-I:I-~--'-...1I-AD-D-#2...1i...J11
I
TRAN5MITTER~'
II
ENABLED
I
T;;~~
I
I
"
CSN
(WRITE)
MR1(4.3)= 11
MR1(2)=1
\-1
-----;)----\11L..,;~\__----'11
--------~,i
ADDN1 MR1(2) =0 DO
PERIPHERAL STATION
BIT 9
r~'--------------
MR1(2)= 1 ADD#2
BIT 9
BIT 9
18
••
LE~ II I' - - - ' -DO-........
10 1:: \~
I -
RECEIVE.R
I
ENABlED _ _ _ _ _ _ _ _ _ _ _ _ _"-'_ _- '
BIT 9
.......
10.. 11
,
~:
I
:
I
I
~r-------'
R,RDY
BIT 9
IADD"! 1I : 1........._
.L....L...__"-' I
1-,- - - - - - - - - - - - - - - - - \ , ', . . -_ _
~
:~:-LJr----------=--,Lt_ u-ttl------:-----::,~
MR1(4:3)", 11
ADD 1t1
ST~S ~TA
STATUS DATA
DO
ADD#2
Figure 12. Wake up Mode
Signetics
4·175
Section 5
Video Games
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
UNIVERSAL SYNC GENERATOR (PAL)
SCN2621 (PAU, SCN2622(NTSC)
PRODUCT BRIEF, contact your Signetics sales offices for complete information.
The Signetics SCN2621 Universal Sync
Generator (USG) provides the timing and
control signals necessary for generating
and displaying TV video information in the
PAL format.
The Signetics SCN2622 Universal Sync
Generator (USG) provides the timing and
control signals necessary for generating
and displaying TV video information in the
NTSC format.
The USG accepts a single 3.55MHz input
clock and generates various timing outputs including vertical, horizontal and
composite blanking, composite sync and
color burst flag. Several auxiliary clock
outputs are also provided.
The USG accepts a single 3.5795MHz input clock and generates various timing
outputs including vertical, horizontal, and
composite blanking, composite sync and
color burst flag. Several auxiliary clock
outputs are also provided. The USG is primarily intended for use in microprocessorcontrolled video games. A typical game
configuration consists of an SCN2622
USG, an SCN2650A microprocessor, an
SCN2636 Programmable Video Interface, a
2616 16K ROM, and digital video summer
circuitry. The SCN2622 is constructed
using Signetics silicon gate N-channel
depletion load technology and operates
from a single + 5 volt power supply.
The USG is primarily intended for use in
microprocessor-controlled video games. A
typical game configuration consists of an
SCN2621 USG, an SCN2650A microprocessor, an SCN2636 Programmable Video
interface, a 2616 16K ROM, and digital
video summer circuitry.
The SCN2621 is constructed using
Signetics silicon gate N-channel depletion
load technology and operates from a
Single +5 volt power supply.
PIN CONFIGURATION
TOP VIEW
5
BLOCK DIAGRAM
L-'::::;:::"'-J:===il--
VRST
CBLANK
VSR
RESET
----------+----------+
CLOCK
----t
r--=~~~~~~~-l=~====~i==::
--I
L -_ _
HORIZONTAL DECODER
L-_________
HRST
CBF
t - - - - - - - OE
j---=::t:~-PCK
CK2
CK4
Signetics
5·1
MICROPROCESSOR DIVISION
JANUARY 1983
PROGRAMMABLE VIDEO INTERFACE (PVI)
SCN2636
PRODUCT BRIEF, contact your Signetics sales offices for complete information.
The Signetics SCN2636 Programmable
Video Interface (PVI) is intended for use in
microprocessor-controlled game systems,
and provides all of the common game circuits on a single chip. Circuits are provided for player inputs, background, moving objects, scoring, and audio signals.
A typical system configuration consists of
five LSI circuits: a PVI, a 2616 16K ROM, a
Digital Video Summer (DVS), a Universal
Sync Generator (USG), and an SCN2650A
microprocessor.
Additional PVls as well as random logic
can easily be interfaced to enhance game
complexity. Since the system is microprocessor based, the actual game itself
need not be "hardwired" into the system.
Game definition is completely contained
in the ROM. To change games, one simply
replaces one ROM with another. Each
ROM can contain several games, depending on game complexity and similarity
between games.
The SCN2636 PVI is constructed using
Signetics' silicon gate N·channel depletion load technology and operates from a
single +5 volt power supply.
PIN CONFIGURATION
FEATURES
• Four general-purpose, RAM-resident
object modules
• Object duplication permitting
generation of up to BD object Images
on the screen
• 2BDns object resolution
• Object size and position under
program control
• Programmable score
• Programmable sound
• Programmable background
• Eight programmable colors with
multiple brightness levels
• 37-byte scratch pad memory
• Chip Enable outputs for system ROMs
and PROMs
• 1/0 facilities for switch scanning and
potentiometer Inputs
• Wire-OR expansion capability to
multiple PVls
• Forty-pin dual-In-line package
APPLICATIONS
•
•
•
•
•
Consumer programmable video games
Arcade games
Simulators
Special purpose graphic displays
Home computer center
GND
INTREQ
RIW
VRST
HRST
Ci
C2
C3
OBJ/SCR
INTACK
A7
DO
Vcc
Dl
At
D2
Al0
D3
All
D4
CEl
Ds
0PACi(
D6
OPREQ
D7
SOUND
CE2
POT2
POT1
TOP VIEW
PVI BLOCK DIAGRAM
BACK·
GROUND
SCORE
CONTROL
Ci
C2
C3
Oi.i/SCR
[~~~~~~g~~~~~
TIMING
AND
CONTROL
~________~~~~~~========~========~====~========~~
ANALOG TO
DIGITAL
CONVERTER
POTl
5·2
POT2
Signetics
DIGITAL
SOUND
SOUND
INTERRUPT
CONTROL &
STATUS
INTREQ
~':T
OPREQ
PCK
OPACK
ADDRESS BUS
CHIP ENABLE
DECODE
VRST
INTACK
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2637
UNIVERSAL VIDEO INTERFACE (UVn
PRODUCT BRIEF, contact your Signetics sales offices for complete Information.
DESCRIPTION
The Signetics SCN2637 Universal Video Inter·
lace (UVI), using a new design approach,
enables a microprocessor based system to
be interfaced more efficiently with a color or
black and white television receiver or moni·
tor. For the first time, the SCN2637 UVI com·
bines an object oriented approach with
character generation (alphanumerics or oth·
er displayable forms) plus RAM·mapped
color graphics.
The UVI's primary use is in microprocessor
controlled home computers or game sys·
tems, however, it may also be used in other
applications where the display of alphanu·
meric and graphics data is desired. In par·
ticular, the UVI has been designed to require
a minimum of support components thereby
allowing a system configuration that is opti·
mized for the user's needs.
The UVI reads data and operational com·
mands from a memory and produces video
signals that result in the generation of alpha·
numeric or graphics color TV displays. Many
of the common display circuits have been
incorporated in a single chip, including:
• Analog to digital converters which accept
potentiometer inputs
• Alphanumeric and special character
generators
• Moving object circuits
• Audio signsl generators
With the SCN2637, a typical system configur·
ation consists of a UVI, a 2616/2632 ROM, an
SCN2622 (NTSC) or SCN2621 (PAL) Universal
Sync Generator (USG), an SCN2650 series
microprocessor, four 2112 RAMs, and video
summing circuitry. Additional UVls, Program·
mabie Video Interfaces (PVls), as well as ran·
dom logic can be interfaced to enhance game
or system complexity.
UVI FUNCTIONAL DESCRIPTION
The SCN2637 UVI Is a bus oriented device
with address and data busses controlling the
flow of data between the user's system and
the UVI (see block diagram). Both the address
and data busses are bidirectional.
The basic clock frequency and the horizon·
tal and vertical reset signals to the UVI drive
vertical and horizontal counters. The two
counters provide the UVI with a Cartesian
coordinate representation of the television
screen, i.e., each counter pair describes a
unique point on the screen. Typically these
clock and reset signals are provided by a
universal sync generator circuit.
PIN CONFIGURATION
FEATURES
• Four general purpose, RAM-resident
objects
• 280nsec object resolution
• Object size and position under program
control
• Programmable multi-level sound and
noise generators
• 16 characters per display row
• 13 or 26 character rows per screen
• 40 alphanumeric characters
• 16 background characters
• 8 program definable characters
• 64 graphics characters
• 8 programmable color codes
• Chip enable outputs for I/O logic
• 1/0 facilities for switch scanning and
potentiometer (RC) Inputs
• Operates with both U.S. and European
standards
• Single +5 volt power supply
• Forty-pin package
D2
D1
DO
PAiiSE
co
C2
5
C1
Ci
SOUND
Riw
APPLICATIONS
VRST
•
•
•
•
•
•
Video games
Home computers
Communications terminals
Educational systems
Process control displays
Medical electronics
HRST
AID Block
Internal Status Block
The AID Block converts the analog potenti·
ometer position information into binary data
which can be read by the system's CPU.
Only two of the four potentiometers are ac·
tive at any given time.
The internal status block accumulates sta·
tus information which can be read by the
CPU; for example, collisions.
Address Block
The address block provides chip enable out·
puts for external RAMs and 1/ 0 buffers.
Sound Block
The sound block is a multi· level square wave
generator sending out pulses at a user
programmable audio frequency. Random
noise is also generated and can be mixed
with the audio frequency for simulating
crowd noise, explosions, etc.
Signetics
Color Mux System
The color multiplexer generates the color
codes for characters, objects, and screen.
ROM Character Generator
The ROM character generator stores the
character fonts.
RAM
The 64 bytes of RAM stores eight pro·
grammable character I object fonts.
5-3
MICROPROCESSOR DIVISION
JANUARY 1983
SCN2637
UNIVERSAL VIDEO INTERFACE (UVI)
BLOCK DIAGRAM
<
HORIZONTAL
COUNTER,
VERTICAL
COUNTER,
TIMING AND
DMACOUNTEA
DHRST DPCLK DVRST
1iIw
RJW
PAUSE
ADEN
OPACK
POT4
pon
POT2
POTI
OPREQ
RCE
CEI
CS
)
8·BIT BUS 00-07
g-
§:=
PROCESSOR
HANDSHAKING
LOGIC
0-
§3
8=
D
DMA ADDRESS BUS
SOUND
11-----------_0 SO
'--------,-""""~~
Y '(-" - - , IK v - - - - - - - - - - - - - ;
"i
RAM ADDRESS
AND DATA BUS
r-------.,.rn
AID BLOCK
2 PAGES
32 BYTES
~~:::~i~
BUFFER
OBJECT
MODULE
1
-
J
L--J...
ROM
~) CHARACTER
I
•
GENERATOR
ADDRESS
DECODER
r-- r.I........_ ...
I
2
3
STATUS
OF
COLLISION
5·BIT VIDEO BUS
--.
~
COLOR
MUX
SYSTEM
0-
INTERNAL 8·BIT BUS
<
+5VOLTS
o
5·4
ADDRESS BUS AO-AS
GND
0
Signe1ics
)
~
~
C1
C2
C3
CO
VIDEO)
MICROPROCESSOR DIVISION
JANUARY 1983
MICROPROCESSOR
SCN2650A
PRODUCT BRIEF, contact your Signetics sales offices for complete information.
DESCRIPTION
FEATURES
The Signetics SCN2650A devices are 8-bit
general purpose microprocessors constructed using Signetlcs N-channel silicon gate MOS technology. The SCN2650
series executes a fixed instruction set,
with each instruction being one to three
bytes in length.
• Static 8 bit parallel NMOS microprocessor
• Single power supply of +5 volts
• TTL level single phase clock
• Tll compatible inputs and outputs
• Variable length instructions of 1, 2 or 3
bytes
• 32K byte addressing range
• Coding efficiency with multiple addressing modes
• Synchronous or asynchronous memory
and I/O interface
• Interfaces directly with industry standard memories
• Single bit serial I/O path
• Seven 8 bit addressable general purpose registers
• Vectored Interrupt
• Subroutine return address stack
The SCN2650A contains a total of seven
general purpose registers which may be
used as a source or destination for arithmetic operations, as index registers, and
for I/O memory transfers. An 8-level subroutine return address stack is included
on the chip.
Addressing range of these processors is
32K bytes of memory and 258 ItO devices.
A single level hardware vectored interrupt
capability is provided.
PIN CONFIGURATION
SENSE
,
FLAG
ADR12
2
Vcc
ADRll
3
CLOCK
PAUSE
ADR 10 4
OPACK
ADR9
5
ADR&
6
RUNIWAIT
ADR7
7
INTACK
ADR&
B
DBUSO
ADR5
9
DBUS 1
ADR4
DBUS2
ADR3 "
DBUS3
ADR2
DB US 4
ADRI
ADRO
5
ADREN
25 DBUSEN
INTREQ 17
ADR 14-DIC 18
ADR 13-ElNE 19
TOP VIEW
MICROPROCESSOR BLOCK DIAGRAM
SUBROUTINE
RETURN
ADDRESS
STACK
<==>
.... 1.1"-------,
DATA BUS
o
II:
!i:
8
!;
ADDRESS BUS
~
o
110
CONTROL
LINES
READ,
WRITE,
INTERRUPT
AND STOP
LOGIC
DECODING
AND
CONTROL
TIMING
LOGIC
CLOCK
Figure 1
Signetics
5-5
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2650A
MICROPROCESSOR
PIN DESIGNATION
MNEMONIC
NUMBER
NAME
TYPE
FUNCTION
ADRO-ADR12
14-2
Address lines
0
ADR13-E/RE
19
Address 13Extended I Non extended
0
ADR14-D/~
18
Address 14Dete I Control
0
AfmER
15
Address enable
I
DBUSO-DBUS7
33-28
Data bus
1/0
~
25
Data bus enable
I
Low order memory address lines for Instruction or openind fetch.
ADRO is the least significant bit and ADR12 is the most significant
bit. ADRO through ADR7 sre also used as the 110 device sddress for
extended 110 instructions.
Low order memory page address line during memory reference
Instructions. For 110 instructions this line discriminates between
extended and non-extended 110 instructions.
High order memory page address line during memory reference
instructions. It also serves as the 110 device address for non-extended 110 instructions.
Active low input allowing 3-state control of the address bus ADROADR12.
These lines provide communication between the CPU, Memory, and
110 devices for instruction and data transfers.
This active low input allows tri-state control of the data bus.
OPREQ
24
Operation request
0
OPACK
38
Operation acknowledge
I
MIlO
R/W
WRP
20
23
22
Memory I input-output
Read I Write
Write pulse
0
0
0
SENSE
1
Sense
I
FLAG
40
Flag
0
INTREQ
17
Interrupt request
I
INTACK
34
Interrupt acknowledge
0
PAUSE
37
Pause
I
RUNIWAIT
35
Run/Wait
0
RESET
18
Reset
I
CLOCK
38
Clock
I
VCC
GND
39
21
+5V supply
Ground
I
I
5-6
Indicates to external devices that all address, data and control
information is valid.
Active low input indicating completion of an external operation. This
allows asynchronous functioning of external devices.
Indicates whether the current operation references memory or 1/0.
Indicates a read or a write operation.
This is a timing signal from the 8CN2650 that provides a positive·
going pulse during each requested write operation (memory or 1/0) and
a high level during read operations.
The sense bit in the PSU reflects the logic state of the sense input to
the processor at pin # 1.
The flag bit in the PSU is tied to a latch that drives the flag output at
pin #40.
This active low input line indicates to the processor that an external
device is requesting service. The processor will recognize this signal at the end of the current instruction if the interrupt inhibit status
bit is zero.
This line indicates that the 8CN2650 is ready to receive the interrupt
vector (relative address byte) from the interrupting device.
This active low input is used to suspend processor operation at the
end of the current instruction.
This output is a processor status indicator. During normal operation
this line is high. If the processor is halted either by executing a halt
Instruction or by a low input on the pause line, the runlwait line will
go low.
Resets the instruction address register to zero. Clears Interrupt
inhibit.
A positive going pulse train that determines the instruction execution
time.
+5V power
Ground
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
SCN2650A
MICROPROCESSOR
FUNCTIONAL DESCRIPTION
The SCN2650 series processors are general
purpose, single chip, fixed instruction set,
parallel 8-bit binary processors. A general
purpose processor can perform any data
manipulations through execution of a stored
sequence of machine instructions. The processor has been designed to closely resemble conventional binary computers, but executes variable length instructions of one to
three bytes in length.
The SCN2650 series contains a total of seven
general purpose registers, each eight bits
long. They may be used as source or destination for arithmetic operations, as index
registers, and for 110 transfers.
The processor can address up to 32,768
bytes of memory in four pages of 8, 192
bytes each. The processor instructions are
one, two, or three bytes long, depending on
the instruction. Variable length instructions
tend to conserve memory space since a
one-or-two byte instruction may often be
used rather than a three byte instruction.
The first byte of each instruction always
specifies the operation to be performed and
the addressing mode to be used. Most
instructions use six of the first eight bits for
this purpose, with the remaining two bits
forming the register field. Some instructions
use the full eight bits as an operation code.
The data bus and address signals are tristate to provide convenience in system design. Memory and 110 interface signals are
asynchronous so that direct memory access
(DMA) and multiprocessor operations are
easy to implement.
The block diagram for the SCN2650 series
(figure 1) shows the major internal components and the data paths that interconnect
them. In order for the processor to execute an
instruction, it performs the following general
steps:
1. The instruction address register provides
an address for memory.
2. The first byte of an instruction is fetched
from memory and stored in the instruction
register.
3. The instruction register (lR) is decoded
to determine the type of instruction and
the addressing mode.
4. If an operand from memory is required,
the operand address is resolved and
loaded into the operand address register.
5. The operand is fetched from memory and
the operation is executed.
6. The first byte of the next instruction is
fetched.
The instruction register holds the first by1e
of esch instruction and directs the subsequent operations required to execute each
instruction. The IR contents are decoded
and used in conjunction with the timing information to control the activation and
sequencing of all the other elements on the
chip. The holding register is used in some
multiple-byte instructions to contain further
instruction information and partial absolute
addresses.
The arithmetic logic unit (ALU) is used to
perform all of the data manipulation operations, including load, store, add, subtract,
AND, inclusive OR, exclusive OR, compare,
rotate, increment and decrement. It contains
and controls the carry bit, the overflow bit,
the interdigit carry and the condition code
register.
The register stack contains six registers
that are organized into two banks of three
registers each. The register select bit picks
one of the two banks to be accessed by
instructions. In order to accommodate the
register-to register instructions, register
zero (RO) is outside the array. Thus, register
zero is always available along with one set
of three registers.
The address adder is used to increment the
instruction address and to calculate relative
and indexed addresses.
The instruction address register holds the
address of the next instruction byte to be
accessed. The operand address register
stores operand addresses and sometimes
contains intermediate results during effective address calculations.
The return address stack (RAS) is a last in,
first out (LIFO) storage which receives the
return address whenever a branch-to-subroutine instruction is executed. When a return instruction is executed, the RAS provides the last return address for the
processor's IAR. The stack contains eight
levels of storage so that subroutines may be
nested up to eight levels deep. The stack
pOinter is a three bit wraparound counter
that indicates the next available level in the
stack. It always points to the current address.
PROGRAM STATUS WORD
The program status word (PSW) is a major
feature of the SCN2650 which greatly increases its flexibility and processing power.
The PSW is a special purpose register within
the processor that contains status and control bits.
It is divided into two bytes called the program status upper (PSU) and program status lower (PSL). The PSW bits may be tested, loaded, stored, preset, or cleared using
the instructions which affect the PSW. The
bits are utilized as shown in table 1.
Table 1 PROGRAM STATUS WORD
PSUO,l,2 SP
PSU3,4
PSU5
II
PSU6
F
PSU7
S
PSLO
C
PSL1
COM
PSL2
PSL3
OVF
WC
PSL4
PSL5
PSL6,7
RS
IDC
CC
Pointer for the return address stack.
Not used. These bits are always zero.
Used to inhibit recognition of additional Interrupts.
Flag is a latch directly driving the flag output.
Sense equals the state of the sense input.
Carry stores any carry from the high-order bit of ALU.
Compare determines if a logical or arithmetic comparison is to be
made.
Overflow is set if a two's complement overflow occurs.
With carry determines if the carry is used in arithmetic and rotate
instructions.
Register select identifies which bank of 3_GP registers is being used.
Inter digit carry stores the bit-3 to bit-4 carry in arithmetic operations.
Condition code is affected by compare, test and arithmetic instructions.
S Sense
F Flag
II Interrupt inhibit
SP2 Stack pointer two
SP 1 Stack pOinter one
SPO Stack pOinter zero
Signetics
CC 1
CCO
IDC
RS
WC
OVF
COM
C
Condition code one
Condition code zero
Interdigit carry
Register bank select
With/without carry
Overflow
Logical arithmetic compare
Carry / borrow
5·7
5
JANUARY 1983
MICROPROCESSOR DIVISION
MICROPROCESSOR
INPUT/OUTPUTINTERFACE
The SCN2650 series microprocessor has a
set of versatile 1/0 Instructions and can perform 1/0 operations in a variety of ways_ One
and two byte I/O instructions are provided, as
well as a special single-bit 1/0 facility. The 1/0
modes provided by the SCN2650 are designated as data, control, and extended 1/0.
Data or control 1/0 Instructions, slso called
non-extended 110 instructions, are one byte
long_ Any genersl purpose regiBter csn be
used aathe source or destination. A special
control line Indicates If either a data or control instruction is being executed.
Extended 1/ 0 is a two-byte read or write
instruction. Execution of an extended I/O
instruction will cause an a-bit address, taken from the second byte of the instruction, to
be placed on the low order eight address
lines. The dsta, which can originate or terminate with sny general purpose register, is
plsced on the data bUB. This type of 110 can
be used to simultaneously select a device
end send data to it.
Memory reference instructions thst sddress
data outside of physical memory may alBo
5·8
SCN2650A
be used for 1/0 operstions. When an instruction is executed, the addresB may be decoded by the 1/ 0 device rsther thsn memory.
MEMORY INTERFACE
The memory interface consists of the address bus, the a-bit data bus and several
signals that operate in an interlocked or
handshaking mode.
The write pulse signal is designed to be
used as s memory strobe signal for any
memory type. It hss been particularly optimized to be used as the chip enable or
read I write signal.
INTERRUPT HANDLING
CAPABILITY
The SCN2650 series has a single level hardware vectored interrupt capability. When an
interrupt occurs, the processor finishes the
current Instruction and sets the Interrupt inhibit bit in the PSW. The processor then executes a branch to subroutine relative to iocation zero (ZBSRl Instruction and sends out interrupt acknowledge and operation request
signals. On receipt of the INTACK Signal, the
interrupt device inputs an 8-blt address,
Signe1ics
the interrupt vector, on the dats bus. The
relstive snd relative indirect sddresslng
modes combined with this a-bit sddress sllow interrupt service routines to begin at sny
sddresssble memory locstion.
INSTRUCTION SET
The 2650 instruction set consists of many
powerful instructions which are all easily
understood and are typical of iarger computers. There are one-, two-, and three-byte
instructions as a result of the multiplicity of
addressing modes.
Automstic incrementing or decrementing of
sn index register is svsilsble in the
arithmetic indexed instructions. All of the
branch instructions except indexed branching can be conditional.
Reglster-Io-register instructions are one
byte; register-to-storage instructions sre
two or three bytes long. The two-byte register-to-memory instructions are either immediate or relative addressing types.
Section 6
Application
Notes
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
INTERFACE TECHNIQUES FOR THE 2651 PCI
AppNoteM22
INTRODUCTION
The Signetics 2651 Programmable Communications Interface (PCI) is a universal synchronous/asynchronous data communications controller chip designed for
microcomputer systems. The 2651 accepts
programmed instructions from a microprocessor and supports many serial data
communication disciplines, synchronous
and asynchronous, in the full or half-duplex
mode.
I-----Ice-----!
Although designed primarily to interface to
a 2650 microprocessor, the 2651 can be
easily integrated into systems employing
other CPUs. This application note describes
methods to interface the PCI to 80BOA,
SC/MP, ZBO, BOB5, and 6800-based microcomputer systems.
INTERFACE SIGNALS
On-D7
The PCI interface signals can be grouped
into two types: the CPU-related signals,
which interface the 2651 to the microprocessor system, and the device-related signals, which are used to interface to the
communications device or system. The
functions of the CPU-related signals of
interest in this application note are detailed
in Table 1. Timing signals for the CPU-PCI
interface are illustrated in Figure 1, with
relevant specifications summarized in Table
2.
Table 1
(R~AD)
_";";;'==+.1
DATA VALID
BUS FLOATING
IDFI-
Figure 1. Read Write Timing Diagram
6
CPU-RELATED INTERFACE SIGNALS
PIN NAME
PIN NO.
INPUT/OUTPUT
FUNCTION
Al-Ao
RIW
CE
10,12
13
11
I
I
I
07-00
B,7,6,5,
2,1,28,27
I/O
Address lines used to select internal PCI registers.
Read command when low, write command when high.
Chip enable command. When low, indicates that control and data linestothe PCI are
valid and that the operation specified by the R/W, A 1 and Ao inputs should be
performed. When high, places the Do-D7 lines in the tri-state condition.
B-bit, three-state data bus used to transfer commands, data and status between PCI
and the CPU. Do is the least significant bit; 07 the most significant bit.
Table 2
AC ELECTRICAL CHARACTERISTICS FOR CPU INTERFACE SIGNALS
LIMITS
PARAMETER
teE
Chip enable pulse width
tAS
tAH
tcs
tCH
tos
tOH
Setup and hold time
Address setup
Address hold
RIW control setup
R/W control hold
Data setup for write
Data hold for write
tOD
tOF
Data delay time for read
Data bus floating time for read
TEST CONDITIONSl
Min
UNIT
Max
300
ns
ns
20
20
20
20
225
0
CL - 100pF
CL = 100pF
250
150
ns
ns
NOTES
1. TA=O°Cto +70°C,VCC=5V ±5%.
2. Parametric values listed are from 2651 data sheet. Consult latest data sheet for
possible changes to specifications.
Signetics
6-1
JANUARY 1983
MICROPROCESSOR DIVISION
AppNoteM22
INTERFACE TECHNIQUES FOR THE 2651 PCI
2650 INTERFACE
The 2651 is designed to interface directly to
the 2650 microprocessor bus. The PCI may
be addressed via the 2650 extended I/O
instructions or it may be memory mapped,
in which case it is addressed using the 2650
memory reference instructions. As shown in
Figure 2, the 2651 chip enable (CE) input is
generated by "NAN Ding" OPREQ with the
appropriate control signals (depending on
the addressing mode used) and the higher
order address lines required to select the
PCI.
The simplest way to accomplish the interface is to utilize an address line from the
8080A for the RIW input and to 'OR' the lOR
and lOW (or MEMR and MEMW) signals for
ultimate use as the 2651 chip enable signal,
as illustrated in Figure4. The only impact on
system design is that the software must
specify a different address to read the PCI
mode or command registers than to write
the same registers. The selection of these
addresses must result in a '0' at the R/W
input for read operations and a '1' for write
operations. The resulting register addressing and function are summarized in Table 3.
An analysis of the timing characteristics for
the recommended configuration shows that
adequate margins exist to satisfy both the
2651 and the 8080A specifications at the
minimum 8080A clock period of 480n8. The
timing waveforms and calculations for the
read and write cycles are shown in Figures 5
and 6.
6·2
Ao
ADR1
A1
RIw
g:~:-
RIW
K
2650
n-:
"--"'0NOTE1
NOTE 2
IJ....
MliO
8080A INTERFACE
With regard to interfacing to the 2651, the
major difference between a 2650 CPU and
an 8080A system consisting of an 8080A
CPU, 8224 Clock Generator, and 8228/38
System Controller (Figure 3) is the absence
of a combined read/write signal suitable for
the 2651 RIW input. Instead, the 8080A system provides separate lOR and lOW (or
MEMR and MEMW) outputs which specify
both the direction of data flow and the data
transfer timing.
ADRO
,..",. / I
ElNE
OPREQ
I
....
/
DBO-DB7
2651
NOTE3
"'Y-
CE
74LS
NAND GATE
1:1
~
HIGH ORDER ADDRESS
LINES FOR CHIP SELECT,
AS REQUIRED
NOTES
1. Inverter required only if 2651 addressing Is by extended 1/0 instructlons(Wrlte, Read).
2. This input required only if 2651 addressing is by extended 1/0 instructions and nonextended addressing is also used in the system.
3. These inputs not required if all I/O addressing is memory mapped.
Figura 2. 2650·2651 Interface
Table 3
PCI REGISTER ADDRESSING FOR 8080A INTERFACE
OPERATION
A2 (A/W)
A1
AO
REGISTER
READ
0
0
0
0
0
0
1
1
0
1
0
1
Receive Holding Register
Status Register
Mode Registers 1/2
Command Register
WRITE
1
1
1
1
0
0
1
1
0
1
0
1
Transmit Holding Register
SYN1/SYN2/DLE Registers
Mode Registers 1/2
Command Register
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
AppNoteM22
INTERFACE TECHNIQUES FOR THE 2651 PCI
GND
-----!.
+5V
25
Ao
20
-5V~
A2
26
+12V-
A3
A2
26
A3
30
A4
31
AS
AS
32
At!
At!
33
A7
A7
34
A8
13
SYSTEM DMA R E Q . - HOLD
AI
27
A4
8080A
CPU
Ao
26
AI
A9
At!
1
Al0
ADDRESS BUS
A8
35
Al0
40
All
SYSTEM INT.
REQ.~
All
37
A12
INT
38
A13
INT. ENABLE
18
INTE
A15
OSC
1/>2 (TTL)
RDYIN
RESIN
+12V
+5V
GND
-
10
~C8
4
1
-
1/>1
DO
23
1/>2
Dl
WAIT
D2
READY
D3
D4
12
RESET
----;;
---7
22
15
~
8224
CLOCK
GENERATOR
DRIVER
21
21 413
~
3
17
DBIN
11
-
A15
18
HDLA
13
-.!.
A14
38
ViR
TANK
A 13
39
A14
~m-rL
14
15
A12
5
19
DS
~-!!
~
r!-r!--
f1---
----!!
~
~ ----!
~~
D8~........!!
D7 ~ ----!
SYNC
+5V~
GND~
r
1
STATUS STROBE
22
BUSEN
DB
8228/8238
BI·DIRECTIONAL
BUS DRIVER
~.
~.
~.
DBI
DB2
~
DB3
f1!-
DBs
23
-------- f!.--
DB7
~
~.
6
DBO
DB4
DATA BUS
DB8
24
SYSTEM
CONTROL
26
: : : } CONTROL BUS
25
1/0
R
27
UOW
Figure 3. 8080A System
Ao
AI
iVw
<
DBg- DB7
v
MRI
MW)
HIGHORDER
ADDR ESB LINES {
FORCH IPBELECT,
AS REQUIRED
--
2851
PCI
~
.
t?-
CE
74 OR 74LS NAND
GATES
Figure 4. 8080A - 2651 Interface
Signetics
6-3
JANUARY 1983
MICROPROCESSOR DIVISION
INTERFACE TECHNIQUES FOR THE 2651 PCI
1
Tl
r--'\
~1--J
,~
----.1
(480)
________
1\
~
________- J1 \
~
I
\
~2---...Ji
r---\
~
~
--------+--------------..1
J
~--
20MIN
r-----------------
eo MAX
--------+-------------+--.1
_
-3~:~
OMIN
3O"i'iAX
I
X
An-AI5
-
200MAX
I-
480 MIN
VALID
DATA FROM 2851
_I
-OMIN
j-30MAX
DATA FROM 8228
~~
eoeoA DATA IN SPEC
-
I -
150MIN
1-(500R DELAY OF DBIN) MIN
~
NOTES
1. All times in nanoseconds.
2. Delay from ¢2 of T1 to Ao. A1. RIW
Delay from cp2. of T1 to CE input
3. Delay from cp2. of T3 to Ao, A1, R/W changing
Delay from rb2 of T3 to BE changing
4. Delay from cp2. of T1 to aDBDA data bus valid
Time from rp2 of T1 to SOSOA data required
200ns MaX} tAs, tes for 2651
310n5 Min
are satisfied
480n5
200n5
690n5
810n5
Min } tAH, tCH for 2651
Max
are satisfied
Max} tOS1. tOS2 for
Max
aOeOA are satisfied
Figure 5. 8080A -
6-4
Tl--
_ _ _ _ __ _
25 MIN
r-____________--__+-__,---l~MAX
lOR
CE
----·1----
\
-------+------------1---------.J1
_
T3
________
\
~.280MI't.-~
320 MAX
DBIN
'1'
T2
~
AppNoteM22
2851 Read Timing
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
INTERFACE TECHNIQUES FOR THE 2651 PCI
,I,
T1
(480)
'I'
T2
n
J\
I
2
1
I
\
App Note M22
"
\
n
I
-
I
\
_
.5MIN
45 MAX
OMIN
-
30MAX
\
,
1 - T1---
T3
...ll!!!!. _
45 MAX
1-
1
~:~x- ·1r120MIN
883 MIN
L-
X
5
1-183MINDATAFROM8080A
~
VALID
5MIN
40 MAX
- ii_
l-
DATAF ROM 8228
MIN
5
40 MAX
)--
VALID
~~
21151 DATAINSPEC
I-
-1100;':
6
50MIN
I-
NOTES
1. All times in nanoseconds.
2. Time prior to WR AQ, A1, RIW valid
Time after WR CE valid
3. Time after WR AQ, A" RIW valid
Delay from WR to CE
683n5 Min} tAS, tes for 2651
5ns Min
are satisfied
120n9 Min} tAH. tCH for 2651
75n5 Min
are satisfied
Figure 6. 8080A -
4. Data available to 2651 prior to CE, therefore tos for 2651 is satisfied
5. Time after WR data avaitable at 2651
125n5 Min} tOH for 2651
Delay from WR to CE
75n5 Max
is satisfied
2651 Write Timing
Z8D INTERFACE
Ao
A1
RIW
<
DBO-DB7
2851
.......
MREQOR IORQ
~
....
L
RFSHORMl
HIGH ORDER {
ADDRESS LINES
FOR CHIP SELECT,
AS REQUIRED
:
V- eE
74 OR 74LS SERIES
NOTE:
MREQ, RFSH used for memory mapped 110
iORO, M1 used for standard I/O
Figure 7. zao -
2651 Interface
Signetics
The zao CPU provides separate RD and WR
signals to indicate read and write operations
respectively. In addition, an MREO signal
(for memory operations) or an 10RO signal
(for I/O operations) are also provided. Although the RD signal could logically be
used as the R/W input for the 2651, with
either MREO or 10RO used as the CE input,
as appropriate, the zao timing specifications are such that the control hold time
specification (tCH) for the 2651 could not be
guaranteed.
To overcome this problem, a technique
utilizing an address line for the RIW input is
recommended, as previously discussed for
the aOaOA interface.
Inter/aces for memory mapped and I/O
mapped operations are shown in Figure 7.
The M1 signal inhibits 2651 operation during interrupt acknowledge cycles. Similarly,
RFSH inhibits operation of the 2651 during
memory refresh cycles. A detailed timing
analysis shows that all pertinent 2651 and
zao timing specifications are satisfied with
the techniques illustrated.
6·5
MICROPROCESSOR DIVISION
JANUARY 1983
AppNoteM22
INTERFACE TECHNIQUES FOR THE 2651 PCI
SC/MP II INTERFACE
The bus interface signals for the SCIMP II
are similar to those previously described for
the B080A and Z80, except that only memory reference operations are available. Again,
a technique using an address line for the
2651 RIW input is recommended, as shown
in Figure B. All timing requirements for the
2651 and SCIMP II are easily satisfied.
Au
Al
RIw
6800 INTERFACE
DBO·DB7
DBO·DB7
The 6800 microprocessor provides a RIW
signal which, when inverted, is suitable for
use by the 2651. The remainder of the interface logic required consists of gating of the
appropriate bus signals to generate the CE
signal for the 2651, as shown in Figure 9.
--
N RDS
NWDS
.
HIGHORDER {
ADDR ESS LINES
FORCH IP SELECT,
AS REQUIRED
The only timing parameter which Is not
easily satisfied is the write data hold time
for the 2651 (t OH )' which is specified at Ons
minimum. The 6800 specifications guarantee only a minimum of 10ns data hold time
with respect to the DBE processor input,
which is normally the <1>2 clock. To guarantee worst-case operation, the DBE signal
should be skewed with respect to <1>2 to
guarantee the minimum data hold time at
the 2651. Consult the M6800 System Design Data Manual for detailed information.
"
:>-
2851
PCI
CE
74 OR 74LS NAND
GATES
Figure 8. SC/MP II -
2651 Interface
8085 INTERFACE
The bus signals of an 8085 microcomputer
system are similar to those olthe B080Asystem shown in Figure 3. The major differences are the multiplexing of the eight least
significant bits of address on the data bus
and the use of an 101M control line to
distinguish between memory and I/O references.
Au
Aiw
6·6
Al
RIW
~
:>
III
:I
DIg.DB7
DBo-DB7
w
~
2851
PCI
II)
~
2
VMA
HIGHORDER {
.
ADDRESS LINES
FORCH IPSELECT,
AS REQUIRED
If 1/0 addressing is used, AO-A2 in Figure 4
can be replaced by the non-multiplexed
higher order address lines AB-A 10, since the
8085 provides the 1/0 address on both AOA7 and AB-A15 during an INPUT and OUTPUT instruction. In addition, the inverted
101M signal must be used as an input to the
final NAND gate.
The BOB5 timing specifications are such that
all 2651 requirements are easily satisfied.
Similarly, the 2651 timing satisfies the BOB5
requirements.
....
II)
Since a single RIW control line is not available, the same addressing technique forthe
2651 registers as described for the 80BOA
interface is recommended. Thus, the interface will be similar to the one shown in
Figure 4.
If memory addressing is used for the 2651,
AO-A2 must be obtained by demultiplexing
from the addressldata bus through an externallatch clocked by the ALE timing signal. If
10 addressing is also used in the system, the
MIlO signal must be used in the final NAND
gate.
Au
Al
t>-
740R 74LS SERIES
Figure 9. 6800 -
REFERENCES
1. Signetics 2651 PCI Specification
2. Signetics MP8080A Microprocessor
Specification
3. Signetics SCIMP II (lSP-BA/600l Microprocessor SpeCification
4.
5.
6.
7.
Zilog ZBO CPU Product Specification
Intel Data Catalog, 1977
Intel MCS B5 User's Manual
Motorola M6800 Microcomputer System
Design Data
Signetics
2651 Interface
CE
JANUARY 1983
MICROPROCESSOR DlVISION
USING THE 2651 PCI WITH BISYNC
The 2651 PCI supports IBM's Binary Synchronous Communications (BISYNC) protocol, with SYN and OLE character stripping,
OLE generation, and a transparent mode of
operation. Please refer to the 2651 data
sheet when reading this application note.
OPERATION IN THE NORMAL
(NON-TRANSPARENT) MODE
Initialization
Initialize the internal PCI mode and command registers as follows:
MR17
0
Double SYN (even
though the same
SYN character is
used).
MR16
0
MR15-12
Non -t ra n spa ren t
mode.
Table 1
App Note M24·A
INITIALIZATION REQUIREMENTS vs CODE SET
FORMAT
CODe seT
EBCDIC
ASCII
SBT1
8 bits, no parity
7 bits, odd parity
6 bits, no parity
MR15
MR14
MR13
MR12
0
1
0
1
1
0
1
0
0
X2
0
X
NOTES
1. Six-Bit Transcode
2. X = Don't care
Table 2
ERROR CHECKING REQUIREMENTS FOR BSC
Transmission
Code
No
Transparency
Transparency
Operating
Transparency
Not Operating
EBCDIC
ASCII
SBT
CRC-16
VRC-LRC
CRC-12
CRC-16
CRC-16
CRC·12
CRC-16
VRC-CRC-16
CRC-12
See table 1.
Synchronous mode,
1X clock.
MR11·10
00
MR25
0 or External/Internal
TxC.
MR24
0
MR23-20
0000 Set for desired baud
thru rate if internal TxC is
1111 used.
CR7-6
00
or
01
External RxC (supplied by modem).
Normal or SYN and
OLE stripping mode
(depends on soHware).
The SYN 1 and SYN2 registers should be
loaded with the appropriate SYN character
for the code set in use. The OLE register
should be loaded if operation in the transparent mode is required.
SYN Character Transmission
and Reception
When the PCI transmitter is initially enabled
(CRO = 1), the TxO output remains high until
the first character to be transmitted (usually
a SYN or PAD) is loaded into the THR. Subsequent to this, the PCI will automatically fill
gaps by transmitting a character pair consisting of the contents of the SYN 1 register
followed by the contents of the SYN2 register (DLE·SYN1 in transparent mode).
The receiver enters the hunt mode on a O-to1 transition of RxEN (CR2). If in the normal
mode (CR7-6 = 00), receipt of a SYN character should be checked by doing a software comparison. If SYN/DLE stripping is
selected (CR7-6 = 01), then SYN detect
(SR5) indicates SYN character reception
since the SYN characters will be stripped.
The processor can read SR5 after RxRDY
goes active to indicate that the first nonSYN character is in the RHR.
Error Checking
The type of error checking depends on the
information code set used: VRC and LRC are
used with non-transparent mode ASCII,
CRC-12 is used with six-bit transcode, CRC16 is used with EBCDIC, and VRC and CRC16 are used with ASCII if a transparent mode
is supported. This is summarized in table 2.
The 2651 PCI is capable of performing VRC
generation, detection and stripping. The
BCC (LRC or CRC) must be computed using
software or external hardware (see section
on BCC Generation/Checking).
Each block of data transmitted is errorchecked at the receiver. The receiving station normally replies with ACK 0 or ACK 1
(data accepted, continue sending) or with
NAK (data not accepted; i.e., a transmission
error was detected, retransmit the block).
There is no error correction.
The three error-checking methods used in
conjunction with BISYNC are VRC, LRC and
CRC. These are defined below.
VRC (vertical redundancy check) is an oddparity check performed on each data character and the LRC character. It is disabled
during operation in the transparent mode.
LRC (longitudinal redundancy check) is a
horizontal parity check on all data bits within
the message block. It is transmitted as a
single BCC (block check ch'aracter) immediately following an ETB, ETX, or ITB character. The receiver compares the transmitted
Signetics
BCC with its accumulated BCC. An equal
comparison indicates a good reception of
the previous block.
CRC (cyclic redundancy check) is a division
performed by the transmitting and receiving
stations using the numeric binary value of
the message as a dividend. The dividend is
initially zero. The constant divisor is either
X16 + X15 + X2 + X1 (CRC-16), or X12 +
X11 + X3 + X2 + X + 1 (CRC-12). The
quotient is discarded and the remainder is
retained as the two-byte BCC.
The BCC accumulation (LRC or CRC) is
reset by the first STX or SOH after line
turnaround. Thereafter, all characters except SYN and OLE (but not the second DLEOLE in transparent mode) are included in the
accumulation. At the end of an intermediate
block (lTB-BCC), the accumulation resets
and starts again with the next received STX
or SOH or DLE-STX in the transparent mode.
OPERATION IN THE
TRANSPARENT MODE
BSC incorporates a submode called "transparent mode." This mode allows communication of pure data (such as binary files)
instead of information code characters. Operation in the transparent mode is initiated
by transmission (reception) of a DLE-STX
sequence and terminated by a closing DLEETX, DLE-ETB, or DLE-ITB sequence. While
in the transparent mode, the following procedures apply:
• Parity (VRC) is disabled and the character
length is changed to 8 bits. This applies
only to ASCII code. For EBCDIC code,
VRC is never enabled.
6·7
6
JANUARY 1983
MICROPROCESSOR DIVISION
USING THE 2651 PCI WITH BISYNC
App Note M24-A
• OLE-SYN is used for line fill instead of
SYN-SYN.
send OLE bit may be used. The sequence of
operations is as follows:
• Any control character transmitted must be
preceded by a OLE.
1) Set CR3 in response to TxROY and then
load THR with the control or OLE character to follow. This ensures that a OLE will
precede the character loaded.
• If a data byte identical to a OLE is to be
transmitted, it must be preceded by another OLE.
Transparent Mode Bit MR 16 = 1 results in:
Receiver: Enables OLE stripping if CR7-6 =
Oland a OLE is received.
Enables OLE detect bit (SR3) if a OLE is
received.
Enables SYN detect bit (SR5) on receipt of
OLE-SYN 1 after synchronization has been
achieved.
Transmitter: OLE-SYN 1 is used as line fill
during underrun.
Initiating the Transparent Mode
Receiver: Oetects OLE-STX sequence in
software and sets MRI6, if desired.
If ASCII code is used, then parity control
(MRI4) should be disabled, and the character length (MR 13-12) should match the
transparent data (usually 6 bits).
If the mode register is changed (as prescribed) % to 1% RxC times after RxROY
goes active, the character being assembled
in the receiver shift register will be of the
new length and parity setting. Otherwise,
the new mode characteristics apply to the
next character to be assembled.
Transmitter: Sends OLE-STX sequence
from THR, and then sets transparent mode
(MRI6). If ASCII code is used, then MR14
will be disabled and MR 13-12 should match
the transparent data character length (usually 8 bits). The mode register may be
changed within n TxC times after TxROY
goes active, where n = the character length
in the non-transparent mode (assuming
transparent mode character length is greater). This ensures that the character loaded
into THR will be transmitted with the new
character length and parity setting.
2) Reset CR3 on the next TxROY, and then
load THR with the next character to ba
transmitted.
Alternatively, the OLE character could be
loaded into THR without using CR3 if there is
no possibility of underrun.
• OLE detect (SR3) Status Bit
The OLE Oetect bit is set when parity is
disabled (MRI4 = 0), the transparent mode
is selected (MRI6 = 1), and a OLE character has been assembled in the receiver shift
register. A reset error command (CR4) must
be issued to clear the OLE detect condition.
If OLE stripping is not selected (CR7 -6 =
00), then OLE detection could be done by
software comparison on a character-bycharacter basis.
• SYN / OLE Stripping Mode
If CR7-6 = 01 in the synchronous mode, then
SYN and odd OLE characters are stripped
from the receiver holding register. The second OLE of a OLE-OLE pair is not stripped.
This mode is not recommended for transparent mode.
Returning to Normal Operation
1) Normal operation is resumed alter a OLEETX, OLE-ETa, or OLE-ITB sequence is
received or transmitted.
2) MRI6, MRI4, and MR13-12 must be
changed if they were altered when entering the tr.ansparent mode. Mode register
1 should be addressed with TxEN RxEN = O.
BCC GENERATION/CHECKING
The 2653 PGC can be effectively used as a
parallel CRC I LRC generator I checker and
also serve as a programmable single and
OLE two character sequence detector. Figure 1 demonstrates the 2651 /2653 bus interface. Consult the 2653 data sheet in order to properly utilize that device.
For BISYNC non-transparent messages, the
2651 can be programmed to strip received
SYN characters which are not usually
stored in main memory. Stripping mode
should be terminated upon the PGC's detection of a BTC (block terminating character)
or a OLE-STX SCC (second search character). In the first case, a block check character could match a SYN; in the second case
the PGC needs to see all received transparent data characters in order to calculate the
CRC/LRC and detect the BTC properly.
R
--
TxRDY, RxRDY, TxEMT/DSCHG
DINTERRUPTS
DB7-DBO
,..",
R/W,Al,AO
~
26511
2681
PCI
I CEO.
+5V
TxD
RxD
TxC
~ RxC
CPU
~
2853
CEO
PGC
CEI
Use of PCI Transparent
Mode Features
• Send OLE (CR3) Command
To ensure that there is no transmitter
underrun between a OLE and the conlrol
character or OLE character to follow, the
6·8
t
I
INT
Figure 1. 2651 or 266112653 Interlace
Signetics
R
+5V
JANUARY 1983
MICROPROCESSOR DIVISION
APPLICATIONS TECHNIQUES FOR THE 2651 PCI
INTRODUCTION
The Signetics 2651 Programmable Communicalions Interface (PC I) is a universal
synchronous I asynchronous data communications controller chip designed for use with
microcomputers and minicomputers. The
2651 accepts programmed instructions from
a CPU and supports many serial data communications disciplines, both synchronous
and asynchronous, in full or half-duplex, including IBM's Binary Synchronous Communications Protocol (BISYNC). The reader is
referred to the 2651 Data Sheet for general
specifications and to applications memo
M22 for interface techniques with such
microprocessors as BOBOA, SC/MP, ZBO,
BOB5, and 6BOO. Techniques for using the
2651 PCI to support BISYNC are detailed in
application memo M24. The purpose of this
applications memo is to assist the designer
by demonstrating various interface and
operational procedures which have been
successful with the 2651. While we have
tried to cover several possibilities in each
procedure, the techniques shown should not
be construed to be constraining and the designer is encouraged to develop whatever
interface techniques best fit his application.
PROCEDURES FOR TERMINATING
TRANSMISSION
FULL DUPLEX (RTS always true)
1. Load last character into THR in response
to TxRDY going active low.
2. Disable TxEN (O-CRO) in response to the
next TxRDY. This will cause TxRDY and TxEMT to remain in the high state after the
last character (in TxSR) is serialized.
HALF DUPLEX (RTS true when transmitting; false otherwise)
Synchronous-use a closing PAD
1. Load an all l's PAD character into THR in
response to TxRDY. At this time the previous (last) data character is in TxSR being serialized.
2. Disable TxEN as above. In this case, the
last data character has been transmitted
when TxRDY goes active.
3_ Drop RTS (O-CRS). One or more bits of
+5V
Rx
TxRDY
RxRDY
+5V
2851
Ry
TxEMTI
==
L-_ _ _ _ _ _ ENBL
}
~~~IC
IR2
DSCHG
Figure 1_ PCllnterrupt Requests IR1 and IR2 When TxEMT/~ Must be
Separated From TxRDY
AppNoteM26
the PAD character will be transmitted on
TxD before the RTS pin (23) goes high.
Asynchronous-wait for TxEMT
1. Load last character into THR in response
to TxRDY.
2. Mask out the TxRDY interrupt condition
by externally disabling it. This can be
done through a gate, interrupt controller
chip, or CPU mask flip-flop. Note that
TxRDY and TxEMT cannot be tied together (see Figure 1).
3. Drop RTS in response to the next TxEMT.
TxEMT going active indicates that the
last character has been transmitted. The
TxD state will be marked hold one bit
time after TxEMT goes active.
DISTINGUISHING BETWEEN
TxEMT AND DSCHG
CONDITIONS
The DSCHG condition goes active on a state
change of either the DCD or DSR pines) provided either RxEN or TxEN = 1 but not in
local loopback mode. The DCD and DSR
status bits (SR6, SR?) reflect the pin status
at the time the status register is read, i.e.,
they are not latched. A Status Read will
clear the DSCHG condition.
The TxEMT condition goes active during
transmitter underrun. The condition is immediately reset when a character is loaded into
THR. It is reset after the linetill is sent once
the transmitter is disabled (TxEN = 0).
Since both of these conditions share a pin
(IB) and a status register bit (SR2), it is
necessary to determine which or both conditions are present when the pin I status bit is
active (Figure 2).
Figure 2_ Flowchart to Distinguish Between TxEMT & DSCHG
Signetics
6-9
6
JANUARY 1983
MICROPROCESSOR DIVISION
App Note M26
APPLICATIONS TECHNIQUES FOR THE 2651 PCI
GENERATING CORRECT
INITIALIZATION STATE
OFTxD
After a power-on or RESET all Mode register
bits will be zero. Specifically, MR25 will select external TxC. The TxO pin requires at
least one high to low transition on TxC for
TxO to go high. Without a TxC input, a break
(all zeros) may be transmitted. This
presents a problem in asynchronous mode
when using the internal BRG (MR25 = 1). To
circumvent the problem, the user may take
one of the following actions:
a) Generate one high to low transition on
TxC during a power on or RESET.
b) Input a system clock or the BRCLK into
TxC through a 1K resistor.
c) Inclusive OR RTS and TxO to produce
the Tx serial data to the modem.
d) Use external logic (Figure 3) to insure
TxO comes up in the" 1" state.
TxD
181----D>o-------r~
2851
Vcc
RESET
Figure 3. Logic to Guarantee TxO == 1 on Power Up or Reset
USING THE PCI BEYOND THE
SPECIFIED SERIAL DATA RATE
If local loopback is not required, the PCI
will operate correctly if the RxC high and
low times are equal to or greater than 500
ns. A 1 Mbps DC baseband link between
two PCI's is therefore quite acceptable.
The only requirement is a synchronizing
flip flop at the transmitter to compensate
for the uncertainty in t Txo, the TxD delay
from the falling edge of TxC. That time can
be anywhere from 150 ns to 650 ns (Fig. 4).
2851
Figure 4. 1Mbps DC Baseband Link
ANALYSIS OF PULL UP RESISTOR
VALUES FOR 2651 PCI WIRE-OR
OF OPEN DRAIN OUTPUTS
This discussion is intended to assist the
user in determining pull up resistor values for
open drain output TxROY, RxROY,
TxEMT IOSCHG shown in Figure 1 (Rx, Ry).
1. Rx min: wish to maintain acceptable "0"
V output.
.
Vee max - VOL max
Rxmln =
-c""=-"._
iOl max + ill ~p
-==-__
(5.25 - .45) volts
(1.6
+ .01)mA
4.8
kl!
1.61
only one output sinking (low) = 3kl!
2. Rx max: wish to maintain acceptable" 1"
V output.
Vee max - VOH min
Rxmax = -'='~--....::::..:.....3 x iOH - ill ~p
all outputs sourcing (high)
6·10
Signetics
(4.75 - 2.4)V
(3x.Ol - .01)mA
=117.5kl!
JANUARY 1983
MICROPROCESSOR DIVISION
USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
INTRODUCTION
per second. The PGC is a device that
monitors parallel data transferred between a CPU or memory and a serial
receiverllransmilter (R/T, UART, USRT,
etc.) or other bus oriented device. Operation is two-way alternate (half-duplex) in
that the PGC is selected to receive
characters either from the R/T or from the
CPU. Full duplex operation is achieved by
using two PGCs. A unique feature of the
2653 is its 'character class array', a 128x2
RAM which is used to classify received
characters into one of four types - normal,
sync/not included, block terminating
character,
and
secondary
search
character. The received characters may
be block checked and/or compared to the
special characters pre loaded into the
character class array. In addition to the
block check character (BCC) generation,
the PGC is capable of single character
detection, two character sequence detection and parity generation and checking.
All operating modes are software
programmable and can be changed for
each application. Figure 1 illustrates the
block diagram of the PGC, while figure 2
describes the formats of the registers
used to program its operation. 1
When transferring data via a data communications link using any protocol, the only
way to ensure a correct transfer is to perform error checking on the messages
being exchanged. Error checking can be
accomplished through vertical, longitudinal and cyclic redundancy checks,
special
character
recognition
and
transparent operating modes. If the error
checking is performed correctly, the
result is an accurate transfer of data from
station to station. The checking technique
can be performed by software only, but
this may result in a reduction of the maximum channel speed, may reduce the
number of channels which can be handled
by the CPU, or may limit the supplementary tasks which can be performed by the
CPU. The most efficient way to accomplish error checking is to use a combination of hardware and software.
The Signetics 2653 Polynomial Generator
and Checker (PGC) is designed to provide
the above error checking capability while
operating with asynchronous, synchronous or parallel receivers or transmitters at a speed of up to 500K characters
00-07
DATA BUS
~
'1
DATA BUS
BUFFER
~
I
I
I
OLE
TNTR
A0
.
-=-....z
.~~
MODE REGISTER
COMMAND REGISTER
•
STATUS REGISTER
0
A1
CE1
iilw
.
r-
"z
....
"~
'"
CE0
C
REC/XMT
READ/WRITE
MEMORY
REC/XMT
TXD
r=TXD
- + - - RxD
D
ADDRESS, DATA, RlW,
i-
~RxD
~
CEO
REC/XMT
~RxD
DATAD~
fEU
CPU
r=TXD
CEl
_CEO
PGC
INT
ONE PGC IS TIME-SHARED BY THREE R/ls.
THE CPU READS AND RESTORES THE PARTIAL
REMAINDER FOR EACH SERIAL CHANNEL.
Bee
6
Figure 8. PGC Services Multiple Receivers/Transmitters
1
'I~LI~
--1
INT
I
AO, Al,liJW
PGC
I
-i
I
CPU
DATA BUS
I
8/
I
I
1--
PERIPHERAL
DEVICE
[
H
H
~
SLAVE
CPU
~CEO
Ii/w
MEMORY
~
~
MA,MC
APPLICATIONS INCLUDE CHARACTER ARRAY
COMPARISIONS, VRC AND/OR BCC CHECKS
ON THE DATA BUS.
NOTE
·CPU Initiallz•• OMA controller for each block tranaf.r of
DMA·
~
CONTROLLER ~
data.
Figure 9. PGC Data Bus Monitoring with DMA Transfers
Signetics
6·19
JANUARY 1983
MICROPROCESSOR DIVISION
AppNote400
USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
TxBE TxU RxDA RxSA
INTERRUPTS
U
11
DB7-DBO
2652
MPCC
A2
Al
AO
RlW
DBEN
CE
CPU
t--
TxD
I--
RxD
I--
TxC
I+-
RxC
DBEBO
--t>
CEO
2663
Al POC
li/W
AO
CEl
.t
f
•
Figure 10. 265212653 Interface -
I
iNf
(OPEN DRAIN)
+5V
Typical Protocols: BiSYNC, OOCMP, SOLC, HOLC
R
+5V
DINTERRUPTS
TxRDY, RxRDY, TxEMT/DSCHO
r-- TxD
DB7-DBO
---l
R/W,Al,AO
~
2651/61
RxD
PCI
--
~
~
TxC
RxC
CPU
~
CEO
2653
POC
CEl
t
iNf
(OPEN DRAIN)
Figure 11. 2651 Dr 2661/2653 Interlace
6-20
Signetics
I
R
+5V
JANUARY 1983
MICROPROCESSOR DIVISION
USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
PGC status flags are utilized to determine
if and when the transmission switches to
transparent mode, and to determine the
receipt of a block terminating character
(BTC). The two characters following the
BTC are the Block Check Character. After
these are received, the PGC status
register is examined to determine if a BCC
error has occured.
The data stored in the buffer will be stripped of all sync characters. DLEs are not
stripped. Although the 2661 includes a
OLE stripping capability, this feature is not
employed because the OLEs must be
'seen' by the PGC in order for it to accumulate the BCC correctly. The CPU
must remove the extraneous OLEs which
may be imbedded in a transparent block of
text.
The transmit flow chart, figure 13, operates on a block of data placed in a buffer
area by the controlling CPU. This data
must include the SYNs to be sent at the
initiation of transmission and the OLEs
that form part of a two character control
sequence. OLEs in a transparent block of
text need not be doubled up - the EPCI will
automatically add a OLE if one is loaded
into its THR while operating in transparent
mode. A character counter assists the
software to determine when a OLE is really
part of a BTC (in transparent mode).
AppNote400
After initialization of the PGC and EPCI
and establishment of the modem connection, the data is pulled from the buffer and
transmitted. If a OLE is detected in the
data stream, and that character is part of a
two character control sequence, the 'send
OLE' feature of the PCI is used to avoid
underrun between the two characters.
Since the OLE is not transferred to the
EPCI via the data bus, this requires that an
extra OLE be accumulated in the PGC.
This is done by use of the PGC's capability
to accumUlate characters loaded via CE1.
When a BTC is detected by the PGC, the
two BCC characters are read from the
BCC registers and transferred to the EPCI
for transmission.
6
Signetics
6·21
MICROPROCESSOR DIVISION
JANUARY 1983
USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
SETTFLAG
WRITE PCI
MR1
DATA =4C
WRITE PGC
MR
DATA=C1
INCREMENT
POINTER AND
STORE
CHARACTER
IN BUFFER
A
Figure 12. Bisync Receive Flow Chart
6·22
Signetics
AppNote400
SWITCH
PGC AND
PCI TO
TRANSPARENT
MODE, SET
TRANSPARENT
MODE FLAG
JANUARY 1983
MICROPROCESSOR DIVISION
AppNote400
USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
BISYNC RECEIVE FLOW CHART NOTES
GET LAST
CHARACTER
FROM BUFFER
1.
TEST
FOR
ITB
FFLAG
= the
first
received
TFLAG
=
non~sync
character
has
been
operating in transparent mode
EFLAG
= BCe or PAD error.
81 FLAG
= Received block terminating character (BTC).
82FLAG
=
Awaiting Bee.
WRITE PCI
MRI
DATA=OC
WRITE PGC
CR
DATA = 02
INITIALIZE
FLAGS FOR
NEXT BLOCK,
RESET BCC,
SWITCH TO
~Ig~~c
NORMAL
1--------,
TEST
RXRDY
Received first
second BCe.
BCe
character.
Awaiting
2.
sse detect is disabled by PGC while in transparent mode.
3.
Pointer is decremented to overwrite previously stored
'OLE' which was part of a 'DLE-SYN' line fill.
4.
Test for closing PAD of at least four ones at end of
message.
5.
If first non-sync character is a 'OLE', the message will start
with 'OLE-STX' (transparent mode), FFLAG is not set in this
case since both these characters are excluded from the
accumulation.
6.
First non-sync character of a new message, or first two if
message starts in transparent mode, are excluded from the
BCC accumulation.
6
(NOTE 4)
READ PCI
RHR
LOGICAL 'OR'
CHARACTER
WITH 'FO'
SET
EFLAG
NEGATE DTR.
DISABLE RX
Figure 12. Bisync Receive Flow Chari (Continued)
Signetics
6·23
JANUARY 1983
MICROPROCESSOR DIVISION
AppNote400
USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
NORMALLY
'SOH'
OR
'STX'
WRITE TO
PGe
CHARACTER
REGISTER
RESET
Bee
USINGffi
(NOTES)
OATA=10
RESET
Bee
(NOTE 3)
(NOTES)
ENABLETX
ASSERTRTS
(NOTE 1J
WRITEPCI
M"
DATA=4C
BISYNC NORMAL
ACCUM. WITH CEl
WRITEPGC
TRANSMIT
CRG16
MR
DATA-CD
INITIALIZE
BUFFER POINTER
AND CHARACTER
COUNTER,
RESET
FFLAG,TFLAG
DRAG
Figure 13. Bisync Transmit Flow Chart
6·24
Signetics
SWITCH PGC
AND PCI TO
TRANSPARENT
MODE,SET
TRANSPARENT
MODE FLAG
ACCUMULATE
'OLE'
INTO THE BCC
MICROPROCESSOR DIVISION
JANUARY 1983
USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
AppNote400
RESET
TRANSPARENT
ANDDlE FLAGS
- - - - - 1 ~~6T~~,~~C
NORMAL MODE.
AESETBCC
ACCUMULATION
WRITETOPGC
CHARACTER
REGISTER
USING
ffi
DATA~
'DLE
INTO Bee
6
10
TEST
TXRDY
READPGC
",e
REGISTER
TRANSMIT
WRITE TO
UPPER
(NOTE 61
'ee
PCITHR
TEST
TXADY
BISYNC TRANSMIT FLOW CHART NOTES
1.
2.
REAOPGC
,ee
REGISTER
TRANSMIT
'ee
LOWER
WRITE TOPCI
3.
T",
4.
5.
6.
Transmitter will not operate until Clear to Send (erS) input is asserted.
A OLE at this point in the transmit sequence can only be followed by an STX, which will place the system in
transparent mode. The 'Send OLE' capability 01 the PCI is used in order to prevent underrun between the OLE and
STX characters, and possible misinterpretation of the sequence by the receiving station.
First non-sync character of a new message, or first two if message starts in transparent mode, are excluded from
the Bee accumulation.
DFLAG is used to indicate that a OLE must precede the next transmitted character.
In transparent mode, the 2661 will automatically send an extra OLE when a OLE is loaded into the THR.
Underrun ot pel is not permitted at pOints shown. Otherwise, received data may be misinterpreted.
Figure 13. Bisync Transmit Flow Chart (Continued)
Signetics
6·25
MICROPRO~ESSOR DIVISION
JANUARY 1983
USING THE 2653 POLYNOMIAL GENERATOR AND CHECKER
~
READ CR
!
RESET
REGISTER
POINTER
WRITECR
DATA=03
I
WRITEMRI
DATA=OC
WRITECR
DATA = 04
EXTERNAL CLOCKS
WRITECR
DATA=08
EBCDIC 'SYN'
SET UP FOR
BTC/SC CLASS
I
WRITE TO
CHARACTER REG
DATA=03
DATA = IF
DATA = 26
DATA=2D
EBCDIC 'SYN'
I
WRITE OLE
REGISTER
DATA = 10
SYN/NI CLASS:
SYN
I
I
WRITESYNC2
REGISTER
DATA = 32
SET UP FOR
SYN/NI CLASS
I
WRITE TO
CHARACTER REG
DATA = 32
I
WRITESYNCI
REGISTER
DATA = 32
MASTER RESET,
PUT INTO START·UP MODE
I
SYNC FORMAT,
8 BITS, NO PARITY,
DOUBLE SYNC,
NON·TRANSPARENT MODE
I
WRITEMR2
DATA=OO
App Note 400
BTC/SC CLASS:
ETX
ITB
ETB
ENQ
I
EBCDIC 'OLE'
WRITECR
DATA=OC
t
SETUP FOR
SSC CLASS
I
WRITE TO
CHARACTER REG
DATA=02
SSCCLASS:
STX
+
Figure 14, 2661 Initialization
6·26
Figure 15, 2653 Initialization
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
INTRODUCTION
Microprocessors and LSI have had a
dramatic impact on the implementation
and capabilities of alphanumeric CRT terminals. The first generation of CRT terminals were little more than 'glass
teletypes'. Current designs, implemented
with microprocessors, are characterized
by an abundance of sophisticated
features that were previously not
economically feasible: a universal hardware design that can adapt to different
user requirements simply by changing
software or firmware; programmability to
provide end users with the flexibility to
execute specialized routines; and local
intelligence and storage which off-loads
the host CPU by permitting data manipulation and verification at the terminal site.
Just as the impact of microcomputers has
been felt in the functional capabilities of
terminals, advances in semiconductor
technology have revolutionized the hardware implementation. Designs that previously consisted of 100 to 200 ICs can
now be realized with a few dozen MSI and
LSI devices. The majority of the LSI
manufacturers' effort with respect to CRT
terminals has been concentrated in the
'CRT controller' area. These circuits provide the character timing, display
addressing, and sync generation functions required by all terminals. However,
these controllers need to be supported by
many other external circuits to implement
a complete terminal.
The purpose of this application note is to
provide information on the use of four new
Signetics CRT terminal products which,
when combined with standard CPUs,
memories, and TTL, allow the implementation of a wide spectrum of CRT terminal
capabilities in as few as 15 total
packages. These devices are:
• 2670 Display Character and
Graphics Generator (DCGG)
• 2671 Programmable Keyboard and
Communications Controller (PKCC)
• 2672 Programmable Video Timing
Controller (PVTC)
• 2673 Video and Attributes Controller (VAC)
MAJOR ELEMENTS OF A CRT
TERMINAL
Figure I shows the major elements of a
typical low-end microcomputer-based
App Note 401
CRT terminal. In this system, the CPU
examines inputs from the data communications line and the keyboard and
places the data to be displayed in a display buffer memory, which is typically a
RAM which holds the data for a Single or
multiple screen load (page) or for a single
character row. High-end ('smart' and
'intelligent') terminals start with the same
base, but append additional circuits to
provide more features and capabilities.
The following sections describe the functions of each of the major blocks.
Character Timing and Sync
Generation
The major function of this block is to
generate the horizontal and vertical timing
signals required to produce the TV raster
on the CRT monitor. Other functions
include the generation of display memory
addresses in synchronism with the monitor scan and in accordance with a defined
screen format (characters per row, scan
lines per row and rows per screen),
generation of a cursor Signal at the
appropriate scan pOSition, and generation
of video blanking signals during retrace
intervals.
Figure 1. CRT Terminal Block Diagram
Signetics
6·27
6
JANUARY 1983
MICROPROCESSOR DIVISION
AppNote401
USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
1/0 Interface
In its simplest form, this block provides an
interface to a keyboard to identify the key
depressed and a serial communications
link, normally operating in an asynchronous format, between the terminal and the
host computer. Although these functions
could be performed programmatically by
the terminal CPU system, removing these
functions to intelligent controllers unburden the system CPU and allow it to
be used more effectively to provide additional features with a relatively small
cost impact.
Character and Graphics
Generation
These circuits convert the data stored in
the display memory to the line by line dot
patterns required to display the data on
the CRT monitor.
Video Timing and Visual
Attributes
This section contains the high speed (dot
rate) circuits necessary to convert the
CE
parallel data from the character and
graphics generation circuits to the serial
video stream required by the CRT. Also
included are circuits to sum visual display
attributes such as blinking, highllow
intensity, reverse video, and underlining
into the video stream.
SIGNETICS' CRT CHIP SET
As mentioned previously, the Signetics
CRT 'set' consists of four circuits. The
functions of these circuits correspond
closely to the four major CRT terminal
blocks described above. The circuits have
been partitioned so as to allow each to be
used independent of the others, allow
several alternative methods of implementing the display memory interface so that
the hardware can be tailored to the system
requirements, provide a full complement of
programmable capabilities, and minimize
the number of support circuits required.
The following sections give a brief
description of each of the circuits. The
reader is referred to the individual data
sheets for full operational details.
I~
RD
'---
COMMAND
DECODE
LOGIC
r--AO-2
3
ADDRESS
DECODER
'--INTR
1 1
DO-7 _L
8
DATA
BUS
DRIVERS
-
The 2672 PVTC, figure 2, is a programmable device designed for use in CRT terminals and display systems that employ
raster scan techniques. The PVTC generates the vertical and horizontal timing signals necessary for the display of interlaced or non-interlaced data on a CRT
monitor. Also, the 2672 provides consecutive addressing to a user specified display
buffer memory domain and controls the
CPU-display buffer interface for various
buffer configuration modes. A variety of
operating modes, display formats, and timing profiles can be implemented by
programming the control registers in the
PVTC.
The CPU initializes the 2672 control and
timing registers for the desired timing
profiles and memory configuration. The
PVTC provides the handshake control for
CPU access to the display buffer. One of
four memory access modes may be
programmed: independent mode, trans-
CONTROL
INITIALIZATION
AND
DISPLAY
REGISTERS
READI
WRITE
CONTROL
LOGIC
WR
2672 Programmable Video
Timing Controller (PVTC)
I
~
r
DISPLAY
MEMORY
HANDSHAKE
LOGIC
CTRL 1
CTRL 2
CTRL3
~
DISPLAY
INTERRUPT
LOGIC
DADDO-DAJ.D 13
~
ADDRESS
~r'
TIMING
MULTIPLEXERS
AND
STATUS
REGISTER
r
CURSOR
POINTER AND
LIGHT PEN
REGISTERS
CURSOR
AND
COMPARE
LOGIC
'14
LIGHT PEN STROBE
CURSOR
vcc
G ND
CCLK
CLOCK
BUFFER
~1
HSYNC
TIMING CHAIN
AND
DECODE LOGIC
TIMING
Figure 2. 2672 Programmable Video Timing Controller
6·28
Signetics
I
VSYNCICSYNC
BLANK
JANUARY 1983
MICROPROCESSOR DIVISION
USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
parent mode, shared mode, and row mode.
These modes are described in the System
Configurations section of this application
note.
In all modes, the PVTC provides
addresses for the display buffer which
outputs the character codes to the 2670
Display Character and Graphics Generator (DCGG) and visual attribute codes to
the 2673 Video Attributes Controller
(VAC>' The DCGG and PVTC supply the
dot data and sync timing to the VAC which
generates the serialized video.
Programmable features of the PVTC
include screen format (characters/row,
rows/screen, scan lines/row), horizontal
and vertical timing parameters, cursor
type (block or underline) and blink rate,
character blink rate, interlaced or noninterlaced operation, and single or double
height characters.
The PVTC is capable of producing interrupts based upon several internal conditions. By using these interrupts (or by polling the equivalent status register) display
features such as non-consecutive buffer
addressing for split screen operation,
multiple cursors, horizontal and vertical
scrolling, and smooth vertical scroll can be
implemented.
2671 Programmable Keyboard
and Communications Controller
(PKCC)
The 2671, figure 3, is an MOS LSI device
which provides a versatile keyboard interface and also functions as an asynchronous communications controller. It is
intended for use in microprocessor based
systems and provides an eight bit data bus
interface.
The keyboard controller handles the scanning, debounce, and encoding of mechanicalor capacitive keyboards with a maximum of 128 keys utilizing any of four
programmable rollover modes. A mask
programmable ROM provides four levels of
key encoding, corresponding to the separate shift and control input combinations.
An eight bit keyboard status register
transmits status information to the CPU.
Programmable features include rollover
mode, scan rate and debounce. time,
coded or uncoded operation, and
automatic repeat operation.
The communications section of the PKCC
is a universal asynchronous receiver and
transmitter (UART). The receiver accepts
serial input data and converts it to parallel
data characters. Simultaneously, the
transmitter accepts parallel data from the
CPU data bus and outputs it in serialized
form. Received data is checked for parity
and framing errors, and break conditions
are flagged. Character lengths can be
programmed as 5, 6, 7, or 8 bits not including parity, start or stop bits. An .internal
baud rate generator (BRG) operating from
an external clock or directly from a crystal
can be used to derive one of sixteen
receive and/or transmit clocks. An eight
bit communications status register provides status information to the CPU.
The PKCC has an interrupt mask register
to selectively enable keyboard and communications status bits to generate interrupts. Priority encoded interrupt vectoring
is available. Upon receipt of an interrupt
acknowledge, a mask programmable interrupt vector will be output on the data bus
reflecting the source of the interrupt. The
mask enabled interrupt sources can also
be read directly.
2670 Display Character and
Graphics Generator (DCGG)
The DCGG, figure 4, is a mask-programmable 11,648-bit line select character
generator. It contains 128 1Ox9 characters
placed in a 10x16 matrix, and has the
capability of shifting certain characters,
such as i, y, g, p and q, that normally
extend below the baseline; effectively, the
9 active lines are lowered within the matrix
to compensate for the character's position.
Seven bits of an 8-bit address code are
used to select 1 of the 128 available
characters. The eighth bit functions as a
chip enable signal. Each character is
defined by a pattern of logic 1s and Os
stored in a 1Ox9 matrix. When a specific 4bit binary line address code is applied, a
word of 10 parallel bits appears to the output. The lines can be sequentially
selected, providing a 9-word sequence of
10 parallel bits per word for each
character selected by the address inputs.
As the line address inputs are sequentially
addressed, the device will automatically
place the 10x9 character in 1 of 2
preprogrammed positions on the 16-line
matrix with the positions defined by the 4line address inputs. One or more of the 10
parallel outputs can be used as control
signals to selectively enable functions
such as half-dot shift, color selection, etc.
Signetics
App Note 401
The 2670 DCGG includes latches to store
the character address and line address
data. A control input to inhibit character
data output for certain groups of characters is also provided. The 2670 also
includes a graphics capability, wherein
the 8-bit character code is translated
directly into 256 possible user programmable graphic patterns. Thus, the DCGG
can generate data for 384 distinct patterns, of which 128 are defined by the
mask programmable ROM.
2673 Video and Attributes
Controller (VAC)
The 2673, figure 5, is a bipolar LSI device
designed for CRT terminals and display
systems that employ raster scan techniques. It contains a high speed video shift
register, field and character attributes
logic, attribute latch, cursor format logic
and half dot shift control, and can be
programmed for a light or dark screen
background.
The VAC visual attribute capabilities are
reverse video, character blank, blink,
underline, highlight, and light pen strikethru or, optionally, graphics. Each attribute
has a separate control input which is
latched internally when the AFLAG input is
asserted. If the AM ODE input is low, the
attributes are valid for one character time.
If AMODE is high, the attributes remain
valid until the field is terminated by strobing in a new attributes set. The attributes
are double buffered on a row by row basis
internally so that field attributes can
extend across character row bou ndaries
thereby eliminating the necessity of starting each row with an attribute set.
The horizontal dot frequency is the basic
timing input element to the VAC; internally,
this clock is divided down to provide a
character clock output for system synchronization. Ten bits of dot data are
parallel loaded into the video shift register
on each character boundary. The video
data is shifted out on three outputs at the
dot frequency. On the video output, the
video is presented as a three level signal
representing low, medium and high intensities, and the three intensities are also
encoded on the two TTL compatible video
outputs.
6·29
6
JANUARY 1983
MICROPROCESSOR DIVISION
App Note 401
USING THE 2670171/72/73 CRT TERMINAL CHIP SET
DATA
)I
DBD-DB7
K
BUS BUFFER
REPEAT
KEYBOARD ENCODER
iiCLK
1
OPERATION CONTROL
iii!
CMR
Wii
KMR
CE
CSR
-- I -
1
KCO·KC3
KEYBOARD
SCANNER"
ENCODERI
DECODER
KSR
AD-A2
I
COMMAND DECODER
I
INTERRUPT CONTROL
)
"
4)( 128x8
I
I
I
-
READ·ONLY
MEMORY
l------i
G
INTR
KRO·KR2
r------1
VECTOR GENERATOR
INTA
KRET
r--
I
X
-INTR
KDRES
MODE" TIMING
CONTROL
KEYBOARD
DATA
REGISTER
!
I
Vee ----....
GND_
I
TIMING
TxC
RxC
XTAL1/BRCLK
XTAL2
I
I
BAUD RATE
GENERATOR
BAUD RATE
CONTROL
REGISTER
I
I
TONE
GENERATOR
I
I
TONE
~f---
TRANSMITTER
TRANSMIT
HOLDING REGISTER
~
f
KEY HOLDING
REGISTER
TRANSMIT
SHIFT REGISTER
TxD
r
RECEIVER
INTERRuPTS
TIMING
CONTROLS
RECEIVE
HOLDING REGISTER
RECEIVE
SHIFT REGISTER
Figure 3. 2671 Programmable Keyboard and Communications Controller
6·30
Signetics
RxD
JANUARY 1983
MICROPROCESSOR DIVISION
App Note 401
USING THE 2670171/72/73 CRT TERMINAL CHIP SET
SCD------------------------------,
GM - - - - - - - - - - - - - - - - - - - ,
~vcc
~QND
CAO-CA7 '--______--,
READDNLY
MEMORY
(128x91)
DO-D9
LAO-LA3
6
LSTROBE ________oJ
Figure 4. 2670 Display Character and Graphics Generator
CCO
CCI
CC2
CHARACTER
CLOCK
CCLK
DCLK
10
DO-DB
VIDEO
HDOT
TTLVIDI
TTLVID2
CURSOR
ARVID
ABLANK
ABLINK
AHILT
AUL
ALTPEN/AGM
AFLG
AMODE
ACD
BLINK
UL
LL
LPL/GMD
BKGND
CBLANK
ATTRIBUTE AND
CURSOR CONTROL
LOGIC AND
PIPELINE
BLANK
ReSEr
VCC
VBB
GND
Figure 5. 2673 Video and Attributes Controller
Signetics
6·31
JANUARY 1983
MICROPROCESSOR DIVISION
AppNote401
USING THE 2670/71172/73 CRT TERMINAL CHIP SET
SYSTEM CONFIGURATIONS
vals in order to prevent visual disturbances of the displayed data.
The PVTC supports four common system
configurations of display buffer memory
interface, designated the independent,
transparent, shared, and row buffer
modes. The first three modes utilize a
single or multiple page RAM and differ primarily in the means used to transfer display data between the RAM and the CPU.
The row buffer mode makes use of a single
row buffer (which can be a shift register or
a small RAM) that is updated in real time to
contain the appropriate display data.
The CPU manages the data transfers by
supplying commands to the PVTC. The
commands used are:
1. Read/Write at pOinter address.
2. Read/Write at cursor address (with
optional increment of address).
3. Write from cursor address to pointer
address.
The operational sequence for a write to
memory operation is:
1. The CPU loads data to be written into
the display memory into the Interface
latch.
2. The CPU writes the destination
address into the PVTC's cursor or
pointer registers.
3. The CPU checks the PVTC 'RDFLG'
status bit to assure that any previous
operation has been completed.
4. The CPU issues a 'write at cursor with/
without increment' or a 'write at pointer'
command to the PVTC.
5. The PVTC negates 'RDFLG', outputs
the specified address, and generates
control signals to perform requested
operation. Data is copied from the
interface latch into the memory.
6. The PVTC sets its 'RDFLG' status to
indicate that the write operation is completed.
Independent Mode
The CPU to RAM interface configuration
for this mode is illustrated in figure 6.
Transfer of data between the CPU and display memory is accomplished via a
bidirectional latched port and is controlled
by the PVTC signals read data buffer
(RDB), write data buffer (WDB), and buffer
chip enable (BCE). This mode provides a
non-contention type of operation that does
not require address multiplexers. The CPU
does not address the memory directly - the
read or write operation is performed at the
address contained in the cursor address
register or the pointer address register as
specified by the CPU. The PVTC enacts
the data transfers during blanking inter-
REFRESH
RAM
2672
PVTC
DADD
ADR
DISPLAY ADDRESS
BeE
CTRL3
CE
WDB
CTRL1
CTRL2
Similarly, a read operation proceeds as
follows:
1. Steps 2 and 3 as above.
2. The CPU issues a 'read at cursor with/
without increment' or 'read at pointer'
command.
3. The PVTC negates 'RDFLG', outputs
the specified address, and generates
control signals to perform the read
operation. Data is copied from the
memory to the interface latch and the
PVTC sets its 'RDFLG' status to indicate that the operation is completed.
4. The CPU checks the 'RDFLG' status to
see if the read is completed.
5. The CPU reads the data from the interface latch.
Loading the same data into a block of display memory is accomplished via the 'write
from cursor to pointer' command:
1. The CPU loads the data to be written
into the display memory into the Interface latch.
2. The CPU writes the beginning address
of the memory block into the PVTC's
cursor address register and the ending
address of the block into the pointer
address register.
3. The CPU checks the 'RDFLG' status bit
to assure that any previous operation
has been completed.
4. The CPU issues a 'write from cursor to
pointer' command to the PVTC.
f---
WR
DATA 1/0
Rffij
TO
> VIDEO
DISPLAY DATA BUS
LOGIC
-----..t~ 74LS364J
(
C~E74LS364
iiii
Viii
FROM CPU
FROM CPU
SYSTEM DATA BUS
I
Figure 6. Independent Buffer Mode ConfIguratIon
6·32
Signetics
JANUARY 1983
MICROPROCESSOR DIVISION
USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
5. The PVTC negates 'RDFLG' and outputs block addresses and control sIgnals to copy the data from the Interface
latch into the specified block of memory.
6. The PVTC sets Its 'RDFLG' status to
indicate that the block write is completed.
Similar sequences can be implemented on
an interrupt driven basis using the READY
interrupt output from the PVTC to inform
the CPU that a previously requested command has been completed.
Two timing sequences are possible for the
'read/write at cursor/pointer' commands.
If the command is given during the active
display window (defined as first scan line
of the first character row to the last scan
line of the last character rowl. the operation takes place during the next horizontal
blanking interval. If the command is given
during the vertical blanking interval, or
while the display has been commanded
blanked, the operation takes place
immediately.
For the 'write from cursor to pointer'
operation, the PVTC's BLANK output Is
asserted automatically and remains
asserted until the vertical retrace inlerval
following completion of the command. The
memory is filled at a rate of one location
per two character times, plus a small
amount of overhead.
Shared and Transparent
Buffer Modes
BACK
liEiff
lowered to indicate that the CPU can
access the buffer.
In transparent mode, the PVTC delays the
granting of the buffer to the CPU until a
vertical or horizontal blanking interval,
thereby causing minimum disturbance of
the display. In shared mode, the PVTC will
blank the display and grant immediate
access to the CPU.
Row Buffer Mode
In these modes the display buffer RAM is a
part of the CPU memory domain and is
addressed directly by the CPU. Both
modes use the same hardware configuration with the CPU accessing the display
buffer via three-state drivers (see figure
7). The processor bus request (PBREQ)
control signal informs the PVTC that the
CPU is requesting access to the display
buffer. In response to this request, the
PVTC raises bus acknowledge (BACK)
until its bus external (BEXT) output has
freed the display address and data busses
for CPU access. BACK, which can be used
as a 'hold' input to the CPU, is then
2672
PVTC
PBRED
cpu ( __
App Note 401
Figure 8 shows the hardware implementation for the row buffer mode. During the
first scan line (line 0) of each character
row, the PVTC halts the CPU and DMA's
the next row of character data from the
system memory to the row buffer memory.
The PVTC then releases the CPU and displays the row buffer data for the programmed number of scan lines. The bus
request (BREQ) control signal informs the
CPU that character addresses and the
memory bus control (MBC) signal will start ~~~~~
at the next falling edge of BLANK. The
CPU must release the address and data
busses before this time to prevent bus ~~~~~
6
REFRESH
I~=::J~~~!.ill=~~
DISPlA
ESS
ADR
RAM
CTRlI
CTRl3
CTRl2
SYSTEM DATA BUS
Figure 7. PVTC Shared or Transparent Buffer Modes
Signetics
6·33
JANUARY 1983
MICROPROCESSOR DIVISION
App Note 401
USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
2)(2111
2872
PVTC
ROW
~--~~~An~~~~~
REFRESH
RAM
BREQ
TO CPU
SYSTEM DATA BUS
Figure 8. Row Buller Mode Configuration
contention. After the row of character data
is transferred to the CPU, BREQ returns
high to grant memory control back to the
CPU.
A MINIMUM CHIP COUNT
TERMINAL IMPLEMENTATION
Figure 9 is the schematic of a minimum
chip count CRT terminal using the four
CRT set devices. Only 15 IC packages are
required for the complete implementation,
including all keyboard encoding and RS232 level conversion for the serial inter-'
face. Despite this low chip count the terminal is capable of providing an
impressive array of features including:
Display Format:
• 24 or 25 character rows
• 80 characters per row
Character Format:
• 7x9 dot matrix character in a
9x12 character block
• 96 ASCII alphanumeric characters
• 32 special symbols
• Block graphics
• Line drawing character set
Cursor:
• Underline or block cursor
• Optional blinking
Keyboard:
• 128 keys maximum
• Non-encoded
6-34
• Cursor control keys
• Numeric keypad
Serial Interface:
• Full or half duplex
• RS-232 compatible
• 16 baud rates with internal baud
rate generator
• Character or block transmission
Operating Modes:
• Normal
• Transparent (displays graphic
and control characters)
• Page or scroll with optional
smooth scroll
Visual Attributes:
• Blink
• Reverse video
• Highlight
• Underline
• Non-display
The system utilizes the independent buffer
mode to minimize hardware requirements.
The dual port interface to the 2Kx8 display
buffer is via a Signetics 8X31 bidirectional
latch. This may be replaced by a unidirectiona I latch such as the 74LS374 if reading
of the RAM's contents by the CPU is not
required.
The operating program for the terminal is
contained in the internal ROM of the 8049
microcomputer, which also provides the
Signetics
RAM required by the system program.
Since the majority of the terminal's
features are tailored by firmware, the ROM
size can be increased, either internally or
externally, to support additional functions. 1
BASIC TERMINAL SOFTWARE
The software for a microcomputer based
terminal is closely tied to the system hardware configuration and its characteristics.
If an interrupt driven mode of operation is
desired, the system hardware/software
design must be capable of prioritizing the
interrupts so that the system will correclly
service interrupts from different sources.
In a typical system, there are three interrupt sources: the keyboard, the communications interface, and the video timing controller. The latter must usually be
assigned the highest priority since failure
to service an interrupt from the video timing controller on a timely basis may result
in visual perturbations on the display. The
keyboard and datacomm interrupts can, in
most cases, absorb some time delay
before they are serviced since they
include one or more levels of data buffers.
lA pre-programmed 8049 microcomputer
containing the operating firmware for this
terminal will be available from Signetics.
fP
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JANUARY 1983
MICROPROCESSOR DIVISION
USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
AppNote401
Often, a multi-level interrupt structure will
be required so that a high priority interrupt
requiring immediate service can be serviced even while the system is in the process of servicing a lower priority interrupt.
A simplified flowchart for the software for
an interrupt driven terminal is shown in
figure 10. After application of power, the
microprocessor first performs a system
initialization routine which consists of five
parts:
1. Clear the microcomputer's scratchpad RAM.
2. Initialize the 2672 PVTC for the
desired screen format, monitor timing parameters, cursor parameters,
and display start address.
3. Clear the CRT display by loading a
non display-code (usually an ASCII
'space', 20 hex) into the buffer
memory.
4. Initialize the 2671 PKCC for t,he
desired keyboard and serial interface modes.
5. Read any mode switches (e.g., full
or half duplex, baud rate, cursor
type, etc.) and set system parameters as required.
6
The processor can now enable its interrupts and wait in a loop until an interrupt is
received. When this happens, the processor first determines the source of the
interrupt and then performs the required
system operation.
An interrupt from the CRT timing controller
usually indicates that some information is
required for proper screen refresh operation. For example, the PVTC may issue a
'split screen' interrupt to indicate that a
new address must be loaded into its
screen start registers in order for the next
character row to be displayed from other
than the next sequential address in memory. The CPU must service this interrupt
within a finite time in order for the display
to operate correctly.
An interrupt from the keyboard interface
may be either a displayable character or a
control function. Displayable characters
are usually transmitted to the host computer and also placed into the buffer
memory for display on the terminal. Certain control characters, such as cursor
control keys or keyboard error codes, may
cause only local actions, while others will
also require transmission to the host.
An interrupt from the data communications
interface may also be a displayable
character or a system control character. In
Basic Terminal Software Flowchafi
either case the microprocessor must
determine the type of character and perform the necessary system operation.
A DESIGN EXAMPLE
could have been included by selecting
another of the numerous microprocessor
devices on the market with greater
program memory capacity. Major features
of the terminal are summarized in table 1.1
A fully operational emUlation of an IBM
3101 terminal was designed and constructed using the Signetics CRT chip set.
The terminal incorporates the majority of
the 3101's functions. Selected functions
were not incorporated due to program
memory limitations. For example, the tabbing functions were developed and tested
but were left out in deference to the block
transmiSSion functions. More features
'A data package for the design, including
details of operation, schematic, and
program listing, is available upon request
by writing to:
Signetics Corporation
Microprocessor Applications Dept.
Mail Station 12-76
P.O. Box 409
Sunnyvale, CA 94086
Signetics
6-37
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c.>
JANUARY 1983
MICROPROCESSOR DIVISION
USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
Table 1 - TERMINAL FEATURES
Display Screen Format
Erase functions: erase EOl, erase
2000 character screen capacity (25
EOS, clear screen
rows x 80 columns)
Operator information area (25th Visual Attributes
Highlighted field
line)
Blinking field
Block-shaped cursor with optional
Non-displayed field
blinking
Underlined field
Displayable Graphic Set
Modes of Operation
- Transmission modes: character or
95 ASCII characters for nonblock (page or line)
transparent mode
128 characters for transparent
- Normal or transparent
mode
7x9 character matrix in 9x 12 field
Line Protocol
Asynchronous
Keyboard
7-bit ASCII with programmable
63-key main keyboard
parity
12-key control key cluster
One or two stop bits
12-key numeric keypad
Full or half duplex
Keyboard lock/unlock under softOnline or local
ware control
Programmable
line
turnaround
Keyboard clicker
character for block mode (EOT/
- Typamatic operation
ETX/CR/XOFF)
EIA RS232 interface
Communication line speed: 50 to
Edit Functions
9,600 baud
Cursor controls: up, down, left, ri9ht,
home
Screen Refresh Rate
Cursor address read and write
- 60 Hz
Terminal Hardware
The block diagram of the 8035 based terminal is illustrated in figure 11. It is an
expanded version of the logic shown in
figure 9, the major difference being a
larger display RAM, to provide up to two
pages of screen data, and the addition of
several input ports to handle the large
number of option and set-up switches. The
terminal's software is contained in 4K of
program storage external to the 8035.
The 2672 PVTC is programmed to operate
in the independent buffer mode with the
CPU isolated from the display RAM by two
74lS364 eight-bit latches, which provide
the path for data transfers between the
CPU and RAM. The PVTC, responding to
commands from the CPU, completely controls the data transfer. To avoid display
interference, the PVTC is instructed to
complete the access during a blanking
interva/. For massive display updates
(clear scr!len, load form, etc.) the PVTC is
Instructed to blank the display and service
the data transfer immediately and continuously. Additional memory contention
circuitry is not necessary since the PVTC
provides all of the timing and addressing
(via cursor and pointer) necessary to complete the transfer. An interrupt from the
PVTC informs the CPU when an operation
is completed.
The PVTC addresses the display buffer
memory, which contains both character
and attribute data. An attribute byte is
identified by the software by setting bit 7
of the byte to a logic 1. The RAM data outputs are applied to the 2670 DCGG, which
provides the character dot data information, and to the 2673 VAC.
The VAC is hardwired to operate in the
field attributes mode for this application.
An attribute character occupies a screen
position but is not displayed unless the
ACD input to the VAC is asserted. Bit 7 of
the character byte identifies a character
as an attribute character if it is a 1. When
bit 7 on the RAM data bus is a 1, the
attribute byte is latched into the VAC to
begin a new attributes field. Since the
attributes are double buffered in the VAC,
only one byte (at any character position) is
required to specify a field.
The bipolar VAC circuit serializes the dot
data from the DCGG into a 17.5 MHz data
stream for the monitor. Two TTL-level
video outputs provide three levels of video:
black, white, and gray.
The PKCC provides the asynchronous
data communications link at one of sixteen
Signetics
App Note 401
selectable baud rates. The PKCC
addresses two 74lS145s which act as a
4-to-16 decoder to drive a 16x8 matrix
keyboard. Key depressions are detected
on the KRET input from a 74lS151 8-to-1
multiplexer. Each key depression is
debounced, encoded according to the
states of the SHIFT and CONTROL inputs,
and presented to the CPU. Repeat and
'typomatic' (auto-repeat) functions are
processed automatically by the PKCC.
Timing Calculations
One of the tasks required in the design
phase of the terminal is the selection of a
suitable monitor and calculation of the
PVTC register values to provide suitable
drive signals for the selected monitor.
The selection process begins with
calculation of the required horizontal scan
frequency. Each character will be contained in a 9 dot by 12 line field. Since
there are 25 display rows, the total number
of active scan lines will be 12 x 25, or 300.
To this we must add some number of scan
lines for the vertical retrace, which is
typically 5 to 10 percent of the active scan
lines. For a screen refresh rate of 60 Hz,
this yields
H frequency = (60)(300)(1.1) =
18,900 Hz.
A Motorola monitor was selected for the
application. The major timing specifications for the monitor are:
Horizontal frequency: 18.72 KHz ±
500 Hz
Horizontal retrace: 8 us max
Horizontal sync width: 4 us min
Vertical frequency: 50/60 Hz
Vertical retrace: 750 us max
Vertical sync width: 50 us min
Monitor timing definitions are shown in
figure 12. The worksheet illustrated in
table 2 can be used to compute the
required timing and associated PVTC
register values. Some rough guesses are
required initially and several iterations
through the worksheet will usually be
required to arrive at final values. For
example, the character clock period must
be known to select the horizontal front
porch (HFP), sync width (HSYNC), and
back porch (HBP) values. An estimate of
the character period can be made initially
as follows:
Horizontal period = 1/18,900 =
52.9 us
Horizontal active = total - blank =
52.9 - 10 = 42.9 us
Character period = 42.9/80 = 0.53 us
approximately
6·39
6
JANUARY 1983
MICROPROCESSOR DIVISION
App Note 401
USING THE 2670/71172173 CRT TERMINAL CHIP SET
I--____ CH~I~~OW-----I
~----~
HBLANK
-----1
I--
---j
HSYNC
~----~
FRONT PORCH (IR1)
L----I I11...._____
BACK PORCH (IR2)
~
r--- r------
----I
HSYNC (IR2)
CHAR ROWs/SCREEN (IR4)
----l
,-----1-; I- SSCAN LINES PER ROW ( l R O ) 1j -_ _ _- ,
VBLANK
--.J
I
--l I-- FRONT PORCH (IRS)
I
BACK PORCH (IRS)
L
--I
I-
---,n,--___
VSYNC ~,--_ _ _ _ _ _ _ _ _ _ _ _
--j j-- VSYNC (FIXED AT S)
EQUALIZING
CONSTANT
LINE~ROW
IRO
.J.......11----,-1-'.1--,--,-1....J.I---,I
LI
HSYNC
WIDTH
HBACK
PORCH
. i
I
\I I 1 1 1 1
IR2
VFRONT
PORCH
I
IRS
.
CHAR ROWs/SCREEN
IR4
1
11111
IR1
VBACK
PO~CH
I
I 11I I 1I 1
CHARACTE~S
1 1 1 1 Iii
IR5
i l l I·
PER ROW
1 1
Iii
Figure 12. Horizontal and Vertical Timing
In calculating horizontal timing, an approximate ratio for the HFP, HSYNC, and HBP
of 1 :2:2 respectively is recommended.
Table 2 contains the final values selected
for the application.
Memory Allocation
The 4K bytes of available buffer memory
were allocated as follows (all addresses
are in hex):
- 0000 to 004F: display data for row
25, status line
- 0050 to 0075: not used
- 0076 to 007F: CPU scratch pad
0080 to 07FF: display data for rows
1 to 24
0800 to OFFF: not used, available for
second page of display data
The PVTC's 'display buffer first address'
and 'display buffer last address' registers
are loaded with the values 0080 and 07FF
respectively so as to cause this portion of
the RAM to act as a circular buffer. Initially
the display data is organized in the RAM
as follows:
0080 to OOCF: row 1 data
0000 to 011 F: row 2 data
··
07BO to 07FF: row 24 data
6·40
When a scroll operation is required, the
CPU changes the value in the PVTC's
'screen start' register from 0080 to 0000.
This effectively Shifts the displayed data
up one row. Upon reaching the specified
last buffer address (which is now the last
character in row 23), the PVTC automatically changes the addressing sequence to resume starting at 0080 for the
24th row. The display data is now
organized:
- 0000 to 011 F: row 1 data
- 0120 to 016F: row 2 data
tialized so as to cause an interrupt to be
issued at the beginning of row 24. The
CPU responds to this interrupt by changing the value in the screen start register to
0000. The PVTC then uses this value as
the starting address of the next (25th) row,
causing the status line to be displayed in
that position. The CPU must re-Ioad the
screen start register before the end of the
vertical blanking interval with the correct
value for the first character to be displayed on the screen.
Terminal Software
-
07BO to 07FF: row 23 data
0080 to OOCF: row 24 data
The CPU can clear the previous data in
0080 to OOCF so that a blank row appears
in the 24th position.
The status line (row 25) data is kept in a
separate section of RAM to eliminate the
necessity of moving the data whenever the
scrolling operation described above
occurs. Thus, the PVTC must be
instructed to change its addressing sequence at the beginning of the 25th row.
This is accomplished by use of the split
screen row interrupt capability. IR10, the
'split screen interrupt row' register, is ini-
Signetics
Because the 8035 microcomputer used in
the terminal provides only a single interrupt level, a totally interrupt driven software design could not be used. The interrupt was assigned to the PVTC to service
the split screen interrupt described above
and the operations required to implement
the smooth scroll feature. The keyboard
and datacomm functions are serviced by
polling the PKCC status register. Both the
keyboard interface and UART receiver are
double buffered in the PKCC, preventing
overrun even if they are not serviced immediately.
The program generally follows the typical
program flow described previously. At
system reset the 8035 interrupts are dis-
Mlcr~OPROCESSOR
JANUARY 1983
DIVISION
USING THE 2670/71/72173 CRT TERMINAL CHIP SET
Table 2 - CRT TIMING WORKSHEET
1.
HORIZONTAL CHARACTER BLOCK (no. of dots) ......... .
9
2.
VERTICAL CHARACTER BLOCK (no. of scan lines) ...... .
12
3.
VERTICAL REFRESH RATE, Hz .......................... .
60
4.
CHARACTERS PER ROW ............................... .
80
(lR5)
(lR4)
5.
CHARACTER ROWS PER SCREEN ...................... .
25
6.
TOTAL ACTIVE VIDEO SCAN LINES (step 2 x step 5) .....
300
(lRO)
7.
VERTICAL FRONT PORCH (no. of scan lines) ............ .
4
(lR3)
8.
VERTICAL BACK PORCH (no. of scan lines) ............. .
12
(lR3)
9.
VERTICAL RETRACE INTERVAL (step 8
+ 3)
............ .
15
10. TOTAL SCAN LINES PER FRAME (add steps 6, 7, and 9)...
319
11.
HORIZONTAL LINE RATE, KHz (step 3 x step 10) .........
12.
HORIZONTAL FRONT PORCH (character time units) ......
5
13.
HORIZONTAL SYNC WIDTH (character time units) ....... .
8
(lR2)
14.
HORIZONTAL BACK PORCH (character time units) ...... .
9
(lR2)
15.
HORIZONTAL RETRACE INTERVAL (step 13
16.
TOTAL CHARACTER TIME UNITS IN ONE HORIZONTAL
17.
18.
CHARACTER CLOCK RATE, MHz (step 16 x step 11) ..... .
+ step 14)
19.14
..
17
SCAN LINE (add steps 4, 12, 13, and 14) .............. .
102
EQUALIZING CONSTANT ([step 16 I 21 - [2 x step 13]) .. .
35
(lR1)
1.95228
19.
CHARACTER PERIOD, us (1 I step 18) .................. .
20.
SCAN LINE PERIOD, us (step 19 x step 16) .............. .
53.27
21.
DOT CLOCK RATE, MHz (step 18 x step 1) ............. ..
17.57052
PARAMETER
0.512
SPEC
ACTUAL
18.72 ± 0.5
19.14
B. HORIZONTAL RETRACE TIME, us
8
8.7
C. HORIZONTAL SYNC WIDTH
4
4.1
50 - 60
60
750
784
50
157
A. HORIZONTAL RATE, KHz
D. VERTICAL RATE, Hz
E. VERTICAL RETRACE TIME, us
F.
VERTICAL SYNC WIDTH, us
abled, data memory and display memory
are cleared to zeroes, and both tha PVTC
and PKCC are master reset through softwara commsnds. The system option
switches are then read and stored and the
PVTC and PKCC internal registers are initiIIzed for the seiected operation. Finally,
the initlai data for the status line Is loaded,
the PVTC, UART, and keyboard are
enabled, and the CPU interrupt is enabled.
The program then enters a loop where the
PKCC is checked for keyboard or UART
entries. If an entry has occurred, the
character is fetched and stored In a software controlled FIFO (first-in-first-out)
memory which Is eight bytes deep for both
receiving or transmitting characters (the
need for the FIFO Is described below). If
either FIFO has an entry, the program proceeds to a character recognition routine
Signetics
AppNote401
which checks for the type of character
(displayable or control) and the appropriate handling subroutine (ESC sequence,
control
sequence,
cursor
control,
character display, etc.) Is called. If the
FIFO's are empty, the polling routine
checks the option switches for any
changes since reset entry and If so reconfigures the system as necessary.
The need from the FIFOs results from the
method used to effect the clear row function required when a scroll Is performed.
Although the PVTC Includes a 'clear from
cursor to pointer' command that can be
used to clear a block of memory rapidly,
the display Is temporarily blanked during
this operation. This would cause undesirable fiashes on the display. Instead, the
program does the function by a repetitive
loop using the 'write at cursor and increment' command. Since the write occurs
only once per scan line during the active
display window, a worst case total of approximately 80 scan line times Is required
to execute the routine. This would limit the
maximum received character rate to approximately one per 80 scan lines or about
240 characters per second (2400 baud).
To overcome this limitation, the PKCC Is
also polled each time through the clear
line subroutine loop, and any entries from
the receiver or keyboard are stored In the
appropriate FIFO. Since the FIFO Is eight
deep, this allows eight characters to be
received In the same time, Increasing the
maximum baud rate to 19,200. (Other
program limitations actually reduce the
maximum baud rate to 9600 baud).
However, this does not Increase the rate at
which characters Which cause a scroll
function to occur, such as a line feed, can
be received. Each character of this type
must be followed by 'fill' characters In
order for data rates higher than 2400 baud
to be used.
An Interrupt from the PVTC will occur
when the display scan reaches the row
count programmed in Its split screen
address register, row address 24 (for the
24th row). In response to the Interrupt, the
CPU loads the screen start registers with
the address of the status line (0000) and
enables the PVTC's line zero interrupt.
This causes another Interrupt at the beginning of display of the status line. At this
time the CPU reloads the screen start
register with the proper address to begin
the next display frsme and disables the
line zero interrupt.
If scrOlling Is required the screen stsrt
register value Is Incremented by 80 (popping off the top row) and the effective bottom row cleared to nulls. If soft scrolling Is
6·41
6
MICROPROCESSOR DIVISION
JANUARY 1983
USING THE 2670/71/72/73 CRT TERMINAL CHIP SET
selected, additional functions are performed during the Interrupt routines. To
begin the operation, the line zero Interrupt
routine adds ten lines to the vertical back
porch. This causes the next active screen
display to begin ten scan lines later than
normal and gives the effect of the display
moving up two scan lines (12 lines per
character row - 10) instead of jumping up
6-42
12 lines. If nothing else were changed,
however, the bottom of the display would
move down ten lines. Thus, during the row
24 Interrupt the number of scan lines per
character row Is changed to two (12-10),
causing only the first two scan lines of that
row to be shown. The next line zero interrupt (at row 25) restores the lines per row
count back to 12 to keep the whole status
Signetics
AppNote401
line showing, and now changes the vertical back porch to 8. The display moves up
two more scan lines and at the next row 24
interrupt four scan lines are shown. The
process continues in this manner, providing the effect of the entire display, except
for the status line, smoothly scrolling up
over a selected interval of six frames, or
one tenth of a second.
MICROPROCESSOR DIVISION
JANUARY 1983
2661 OPERATING MODE SWITCHING PROCEDURES
INTRODUCTION
This application note describes procedures for switching the operating mode
of the Signetics' 2661 Enhanced Programmable Communications Interface (EPCi)
from echoplex or remote loopback mode
to normal operation and vice-versa.
ECHOPLEX (AUTOMATIC
ECHO) MODE TO NORMAL
OPERATION
The echoplex operation is initiated by setting command register bits CR7:CR6 =
01, and CR2 (receiver enable bit) = 1.
Echoplex operation is terminated by
resetting CR2 to zero. To ensure the
proper transmission of the last received
character, no change of operating mode
should be made until the end of that
character. However, if mode switching is
necessary in certain applications, the
following procedure is recommended to
ensure no garbling on the last transmitted
character. Two potential problems may
arise: the calculated parity instead of the
received parity may be transmitted, and
data rate may be shortened or lengthened.
The procedure provides the necessary
handshaking to avoid these potential
problems by making use of the TXEMT I
DSCHG pin or of the status register bit 2,
SR2, to indicate the end of the parity bit or
the first stop bit, depending on whether
one or two stop bits are selected
(MR17:MR16 = 01 or 11). The procedure
causes TXEMTIDSCHG to be driven to its
active state only at the completion of the
last character, as shown in figure 1.
The recommended sequence of operation
is as follows:
1. Wait for RXRDY (either RXRDY interrupt or status read). This is necessary
for the assembly of the last character
to be completed and to ensure the
transfer of this character to the
transmitter.
2. Enable the transmitter by setting CRO
to one.
3. Disable the receiver by setting CR2 to
zero.
4. Wait for TXEMT (either TXEMTI
DSCHG interrupt or status read). At
this pOint, the parity bit or the first stop
bit (if two stop bits are selected) has
been sent out.
5. Change mode from echoplex to normal.
6. Load new character into the transmit
holding register, THR. Further communication between the 2661 chip and
the CPU will resume as normal- that is,
TXRDY is driven active to indicate that
the THR is available for new data and
"1XifI START V2Z2222??2?2?22 PARITY
STOP
BIT
LAST CHARACTER
I
I
I
I
I
I
I
I
====~----------------41---~.
TXEMTIDSCHG
DRIVEN ACTIVE HERE IF ONE
L
j ---+j- - - - - - - STOP BIT IS SELECTED-,
:
I
I
--..:.l
DRIVEN ACTIVE HERE IF TWO
I
STOP BITS ARE SELECTED----'--I
I
Figure 1. TXEMT/DSCHG Operation lor ECHOPLEX Mode SWitching
TXEMT
,~_~.m" .."
!
t'· 1\'U
~
PARITY OR
STOP BIT
r-----
TRAN~~~~~~!
I
CHANGE TO ECHOPLEX OR REMOTE---I
Figure 2. Switching from Normal to ECHOPLEX or Remote Loopback
AppNote402
TXEMT is driven active upon underrun
condition.
Note that the TXEMT pin is not driven
active in echoplex mode. It is optionally
driven active when the above steps are
followed, particularly the transmitter being
enabled as indicated in step 2. Because
the transmitter relies on CRO = 1 and CR2
= 0 to drive TXEMT active, it is necessary
to set CRO to zero in echoplex mode if it is
desired not to drive TXEMT active. CRO,
transmitter enable, is ignored for data
transmission in echoplex mode. It is,
however, used to determine whether
TXEMT should be driven active.
If frequent mode switching is anticipated
and it is desired to drive TXEMT active,
step 2 of the above procedure could be
skipped, provided that the echoplex
operation is initiated by enabling both the
receiver and the transmitter - that is,
CR2:CRO = 11.
The TXEMT timing shown above is only
applicable when switching modes. Note
that in normal operation, TXEMT is driven
active at the beginning of the last data bit
or parity bit upon underrun condition.
REMOTE LOOP BACK MODE TO
NORMAL OPERATION
The procedure is similar to the procedure
for echoplex to normal, with the following
exceptions:
1. No handshaking with RXRDY is
required.
2. During step 3 of the previous procedure, CR2 goes to zero, and
CR7:CR6 should be simultaneously
changed from 11 to 01 (remote to echoplex). This is necessary because the
logic Implemented to drive TXEMT
active relies on echoplex information.
However, this requirement does not
need additional service from the controller because remote-to-echoplex
switching is done at the same time as
disabling the receiver.
NORMAL OPERATION TO
ECHOPLEX OR REMOTE
To avoid garbling the last transmitted
data, a mode switch from normal operation
to echoplex or remote operation should be
performed as follows:
_ __
1. Wait for TXEMT (either TXEMTI
DSCHG interrupt or status read) to be
asserted.
2. Disable the transmitter by setting CRO
to zero.
3. Wait for TXEMT to be negated.
4. Change the mode from normal operation to echoplex or remote.
The timing is illustrated in figure 2.
Signetics
6·43
6
MICROPROCESSOR DIVISION
JANUARY 1983
2670171/72/73 CRT SET APPLICATION BRIEFS
INTRODUCTION
The Signetics CRT chip set consists of
four LSI devices which, when combined
with standard microcomputer, memory,
and TTL products, permit the Implementa·
tlon of a CRT terminal In as few as 15 total
packages. The four LSI devices are:
2870 Display Charaetir and Oraphici
Oenerator (DCOO)
The 2670 Is a mask programmable line
select character generator which contains
the dot patterns for 12810x9 characters. It
also provides a seml·graphlcs capability
wherein the 8·blt character code Is
translated directly Into 256 graphic pat·
terns useful for presenting data such as
graphs and forms on the CRT display. Ad·
dltlonal features of the DCGG Include
character and line address latches and In·
ternal descend logic.
2871 Programmable Keyboard and Com·
munlcatlons Controller (PKCC)
The 2671 provides a versatile keyboard In·
terface and an asynchronous communlca·
tlons Interface In a single package. The
keyboard section handles the scanning,
debounce, and encoding of mechanical or
capacitive keyboards with up to 128 keys
utilizing any of four programmable rollover
modes. An Internal ROM provides any of
four key codes for a depressed key. The
communications section Is a universal
asynchronous receiver and transmitter
(UART) with programmable character
length, parity, and stop bits. A baud rate
generator providing 16 standard com·
munlcatlons frequencies which operates
directly from a crystal Is also Incorporated
In the 2671.
talns the high speed timing circuits reo
qulred In CRT terminal systems. Included
on the 2673 are a dot clock counter, video
shift register, field and character at·
tributes logiC, and cursor display circuits.
The 2673 attributes capabilities are
reverse video, character blank, blink,
underline, highlight, light pen, and
graphics. The device provides both TTL
and analog video outputs and operates at
dot frequencies up to 25M Hz.
IndiVidual data sheets are available which
describe each of the devices In full detail.
A previously published application note
entitled "Using the 2670/71/72173 CRT Ter·
mlnal Chip Set" (App Note 401), describes
the Implementation of CRT terminals us·
Ing the chip set. The purpose of this ap·
plication note Is to provide Information on
the Implementation of special end·
product feetures.
SMOOTH (SOFT) SCROLLING
2872 Programmable Video Timing Con·
troller (PYTC)
The 2672 Is designed for use In CRT ter·
mlnals and other display systems that
employ raster scan techniques. It
generates the vertical and horizontal tim·
Ing for the CRT monitor, and provides the
addressing for the display buffer memory.
The CPU to display buffer Interface can be
programmed for several different modes
of operation, Including full screen buffer,
multiple page buffer, or row buffer, as reo
qulred by the application. Programmable
features of the PVTC Include screen for·
mat (characters per row, scan lines per
row, rows per screen), horizontal and ver·
tical timing parameters,cursor type, Inter·
laced or non·lnterlaced operation, and
character and cursor blink timing.
Scrolling Is used In CRT terminals to pro·
vide the effect of an 'endless page' on
which the data can be written. I n normal
Implementations, once the screen fills up,
the space for the next row of data Is pro·
vlded by removing the top row and moving
all the remaining rows up by one row, thus
creating a blank data row at the bottom of
the screen Into which the new Information
Is placed. (The process may be reversed If
the new data Is to be written at the top of
the screen). This technique creates a
readability problem when viewing data
which Is being received at a relatively high
speed, Since the rows are Jumping up (or
down) at a fast rate. Smooth or soft scroll·
Ing Improves readability by moving the
data In scan line Increments Instead of In
whole row jumps, thus creating the effect
of a sheet of paper slowly being moved
through the viewing area. One system
restriction of providing the smooth scroll·
Ing feature Is that the rate at which new
rows of data can be received is limited to
the rate at which the display Is being
moved. Thus, successive line feeds must
be separated by a minimum number of real
or dummy 'fill' characters In order to allow
the display to keep up with the received
data. The number of fill characters will be
a function of the number of scan lines per
character row, the scroll rate, and the
communications line speed, and may also
be effected by the Incl uslon of software
and/or hardware features such as a data
buffer In the system design.
2873 Video and Attributes Controller
The 2673 Is a bipolar LSI device that con·
When using the CRT chip set, smooth
scrolling can be Implemented In software
6·44
Signetics
AppNote403
only, or with a combination of hardware
and software.
Soltware Only Method
The software only method of smooth
scrolling uses the 2672's capability to pro·
gram the scan lines per row and the ver·
tical back porch, and the ability to pro·
gram an Interrupt to occur at any row by
programming the row value Into the spilt
screen register, IR10. Three limitations 01
this method are:
1. Scrolling must be In an upward dlrec·
tlon.
2. The screen area that Is scrolled must
start at the top of the display but can
end at any row.
The minimum scrolling Increment Is
3.
two scan lines.
The flow chart In Figure 1 shows the steps
necessary for scrolling starting at the top
of the screen and ending at character row
231, with an additional non·scroiling row at
row 24. The IR10 value Is set to 23, to
cause an Interrupt to occur at row 23. This
Interrupt routine then enables the line
zero Interrupt, so that another Interrupt
occurs at row 24. The line zero (row 24) In·
terrupt routine disables the line zero Inter·
rupt so that another line zero Interrupt Is
not asserted until the split screen (row 23)
Interrupt routine enables It again.
When a scroll Is desired, the system soft·
ware changes the screen start address to
the new value (normally an address 'n'
characters higher than the previous value,
where 'n' Is the number of characters per
row) and sets a scroll flag. The top row
disappears and normally the display
would jump up by one row. However, the
line zero Interrupt routine notes that the
scroll flag Is set and adds the value 's·2'
(s= scan lines/row) to the vertical back
porch (IR3). This causes the next active
screen display to begin 's·2' lines later
than normal and gives the effect of the
display moving up two scan lines Instead
of Jumping a lull row. If nothing else were
changed, however, the bottom of the
display would move down the same
number of scan lines. Thus, during the
split screen Interrupt routine the number
of scan lines per character row (I RO) Is
changed to two, causing only the first two
scan lines of that row (which Is the new
1Rows are numbered consecutively start·
Ing with row O. Thus, row 23 Is the twenty·
fourth row of characters.
MICROPROCESSOR DIVISION
JANUARY 1983
2670171/72/73 CRT SET APPLICATION BRIEFS
AppNote403
INTERRUPT ENTRY
NO
FIRST ROW OF STATUS REGION
YES
LAST ROW OF SCROLLING REGION
WRITE REQUIRED SCAN
LINES/ROW INTO PVTC
IRO FROM (XXX)
RESTORE SCAN LINES/ROW
IRO TO NORMAL VALUE
WRITE SCREEN START REGS
TO FIRST ADDRESS OF 25th
STATUS ROW
WRITE SCREEN START REGS TO
FIRST ADDRESS OF DISPLAY
FROM ffYV)
6
YES
SET (XXX) TO TWO
SCAN LINES/ROW
INCREMENT (XXX)
BY TWO SCAN LINES
PER ROW
INCREMENT (YYY) BY NUMBER
OF CHARACTERS IN A ROW
INCREASE VERTICAL BACK
PORCH BY NORMAL NUMBER OF
SCAN LINES/ROW - (XXX)
RESET INTERRUPTS AND
RETURN
~~
I
INTERNAL CPU REGISTERS
Figure 1. Smooth Scroll Flow Chart
Signetics
6·45
MICROPROCESSOR DIVISION
JANUARY 1983
2670171/72/73 CRT SET APPLICATION BRIEFS
row) to be displayed and maintaining the
proper value for the total scan lines. The
next line zero interrupt restores the lines
per row value back to its normal state to
display the whole of the last character
row, and now decreases the vertical back
porch increment by two. The display
moves up two more scan lines and at the
next split screen interrupt four scan lines
are allowed. The process continues in this
manner until the scroll is completed.
Note that the CPU must complete the split
screen interrupt routine within two scan
line times.
Hardware/Software Method
The hardware/software method of smooth
scroll removes the restrictions of the soft·
ware only method. The scrolling region
can begin and end at any character row,
scrolling can be performed in either the up
or down direction, and the minimum scroll
increment can be one scan line.
A block diagram of the required hardware
for the case of full screen scroll is il·
lustrated in Figure 2. When scrolling is reo
quired, the CPU writes the number of scan
AppNote403
lines to scroll into the 4·blt latch during
the vertical retrace Interval. The scan line
adder detects when the sum of the offset
and the scan line address is greater than
the programmed number of scan lines per
row and causes the RAM address to be
automatically offset to the next character
row by the n·bit RAM address adder. The
CPU adjusts the value in the scan lines to
scroll latch at desired intervals, e.g., each
vertical retrace, to effect the smooth
scroll. When the scroll is completed, the
screen start address is changed to the
new value required for the top character
row.
If only a partial screen scroll is required,
the hardware must be modified to cause
the offset to be applied only during the
scrolling area. The lines to scroll latch of
Figure 2 is replaced by the circuit shown
in Figure 3. The software is written with
split screen interrupts at the row before
the first row which is to be scrolled (inter·
rupt 1) and at the last scrolled row (inter·
rupt 2). The required program actions are
as follows:
1. During vertical retrace, the screen start
FULL
ADDER
address for the non·scrolled region at
the top of the screen is loaded and IR10
is loaded with the row number required
for interrupt 1.
2. During interrupt 1, a new screen start
address for the scrolled region is
loaded (if required), IR10 is loaded with
the value required for interrupt 2, and
the lines to scroll latch is loaded with
five bits of data consisting of the four·
bit lines to scroll value plus an
asserted 'scroll' bit. The hardware will
cause the scan line offset to be applied
to the adder at the beginning of the
next character row, as required.
3. During interrupt 2, a new screen start
address for the non·scrolled region at
the bottom of the screen is loaded (if
required), and the 'scroll' bit is
negated. The hardware will cause the
scan line offset to be removed from the
adder at the beginning of the next
character row, as required. If the scroll
region extends to the bottom of the
visible screen, this interrupt is not reo
quired. Note that the time required to
service this Interrupt will determine the
minimum number of scan lines per
scrolling increment.
RAM
14
VAC
VIDEO
ATTRIBUTE
DATA
BLANK:-----i
PVTC-~=-:-::-'
ADDRESSES _.=;D,-,AD::.:DO=....-1:;:3_ _-:'Ir-v
CARRY
LOGIC
(NOTE 2)
DO-D9
DATA
BUS
NOTES:
1. Hardwlre adder inputs to number of characters per row.
2. Carry logic asserts output when output of adder exceeds normal scan lines/row.
Figure 2. Smooth Scroll Hardware Block Diagram
6·46
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
2670/71/72/73 CRT SET APPLICATION BRIEFS
AppNote403
~-------------,
BLANK----ICLK
74LS74
DADD8
D
l:I
D4
D3
TO SCAN
LINE ADDER
(FIGURE 2)
D2
FROM
CPU
D1
6
Figure 3. Partial Screen Smooth Scroll Modification
HORIZONTAL SCROLL
Horizontal scrolling allows the terminal to
be used to read or write pages which are
wider than the actual screen width. For ex·
ample, If an actual page width of 132
characters is to be displayed on a terminal
with a capacity of 80 characters per row,
horizontal scrolling can be used to display
any desired 80·character 'window' of the
132·character row. The window can be
moved in response to operator keyboard
commands, allowing all 132 columns to be
observed.The CRT set capabilities allow
horizontal scrolling in single or multiple
character increments to be Implemented
using software only. As described in the
2672 data sheet, changing the contents of
the screen start address register during a
particular row, say row 'n', will cause the
display of the next row, 'n + 1', to begin
from the new address. This feature,
together with the capability to interrupt at
every row via the line zero Interrupt, can be
used to update the contents of the screen
start register once each row to effect the
horizontal scroll. The software operations
required are as follows (see Figure 4):
INTERRUPT
NO (VB LANK INTERRUPT)
ADD ACTUAL CHARACTERS
PER ROW TO PREVIOUS
SCREEN START REGISTERS
VALUE AND WRITE INTO
SCREEN START REGISTERS
WRITE PAGE START
ADDRESS PLUS HORIZONTAL
SCROLL INTO SCREEN
START REGISTERS
RESET VBLANK
INTERRUPT
RETURN
1. During the vertical retrace interval, the
screen start register is Initialized with
the starting memory address of the
display page plus the desired horizon·
tal scroll (in characters).
Figure 4. Horizontal Scroll
Signetics
6·47
MICROPROCESSOR DIVISION
JANUARY 1963
2670/71/72/73 CRT SET APPLICATION BRIEFS
41. The line zero Interrupt is enabled. Dur·
AppNote403
through the latches to the delay of the
video data from the VAC.
ing each interrupt service the value in
the screen start address Is In·
cremented by the actual (not display)
page width. This may be done either by
referencing a table of starting ad·
dresses or by performing the required
addition.
crement once every two scan lines. The
external flip·flop toggles each scan line to
provide a fifth bit of scan line count Infor·
mation for the character generator. The
technique permits any even value of scan
lines per character row from 2 to 32 to be
obtained.
EXTERNAL VIDEO SYNC
Some applications require overlaying of
characters on an existing video display.
An example of this Is the addition of sub·
titles to a picture display. Figure 6 iI·
lustrates a simple technique of externally
synchronizing the 2672 PVTC to an exter·
nal video source. The dot clock to the 2673
VAC is stopped (character clock falling
edge) at the start of the PVTC's sync inter·
val and restarted upon occurrence of the
external sync signal. The sync timing pro·
grammed in the 2672 must be slightly
faster than the external sync rate.
COLOR DISPLAY INTERFACE
Figure 5 illustrates the block diagram of a
color monitor Interface. Eight colors for
foreground and background with three at·
tributes are supplied. The system
operates in the character attribute mode
with a 16·blt word of data for each
character: seven bits for character select,
six bits for color select, and three bits for
other attributes.
BIT MAPPED GRAPHICS
Figure 6 Illustrates an implementation of a
bit mapped display with the chip set. In
this configuration, the contents of the
memory will be displayed without char·
acter generator translations. Thus, each
bit in the memory corresponds to a single
pixel on the display. Each horizontal scan
line is defined by a contiguous set of
bytes in the RAM. The data is written in
groups of a bits by the CPU and is ac·
cessed by the PVTC in groups of a bits.
The character generator of a normal alpha·
numeric configuration is replaced by an
a·bit latch to implement the one CCLK
delay normally provided by the 2670. The
PVTC can be programmed for one scan
line/row to cause the memory addressing
to proceed without repetition of ad·
dresses in each row.
SCAN LINE COUNT GREATER
THAN 16
The two 74LS374s delay the color informa·
tlon by two CCLKs to allow for the two
CCLK delays of dot data through the
DCGG and VAC. The video output of the
VAC selects foreground or background
color (active dot or not) for each character
cell via the 74LS157 multiplexer. A variable
CCLK delay may be required to syn·
chronlze the delay of the color Information
Certain applications may require more
scan lines than the 16 scan lines per
character row (non·interlaced) which the
2672 can provide. Figure 7 shows the hard·
ware required to obtain up to 32 scan lines
per character row. The PVTC must be pro·
grammed for double height character
rows. This causes the scan line count out·
puts from the 2672 (DADD4·DADD7) to in·
TTLVID1
MEMORY
AODRESSES
FROM
pVTe
-
r--Y
7
CHARACTER
RAM
10
"
/
DCOG
/
VAC
em<
~
ATTRIBUTES
I
ADJUSTABLE
DELAY
2
/
L---"..
L....-,..!
COLOR
ATTRIBUTE
RAM
'1
FOREGROUND
COLOR
\
\
R
G
I
B
., L
L
CK
A1
B1
74LS374
C1
74LS374
~
G
I
B
I,
C2
r
BACKGRO~~J
COLOR
r
h
Figure 5. Color Display Block Diagram
6·48
Signetics
Y3-.., BLUE
E
t
I
Y1-.., RED
Y2-.., GREEN
74LS157
A2
B2
I
BLANK
MUX
SELECT
CK
I
R
I
I
TO
MONITOR
MICROPROCESSOR DIVISION
JANUARY 1983
2670/71/72/73 CRT SET APPLICATION BRIEFS
AppNote403
EXTERNAL
HSYNC
VSYNC
VSYNC
HSYNC
7474
HSYNC
VSYNC
1-.........:C::;H::::A::;RA::::C;.:.T:::ERc..C:::L:.:Oc::C""K----I~
PVTC
2672
PVTC HSYNC/vSYNC
DCLK
VAC
2673
----~I
6
1
EXTERNAL HSYNC/VSYNC - - - - - - - - - - - - - - - - - - - -...
DOT CLOCK
~
CHARACTER CLOCK
.J
________________________
~r__
Figure 6. Externel Sync Lock
The PVTC can be programmed to a max·
Imum of 256 characters/row and 128
rows/screen. Thus, a 2048 by 128 bit map
Is possible. If more than 128 dots are reo
qulred vertically, the PVTC can be pro·
grammed for more than one scan line/row
and the scan line outputs can be used as
part of the RAM address, creating several
segments of memory. For example, If 256
lines are required, the PVTC must be pro·
grammed for two lines/row. The use of
LAO as part of the memory address
creates two segments. The CPU writes the
data for odd scan lines in one segment of
the memory and the data for even scan
lines In the other. As the PVTC accesses
the RAM the scan line count will go from 0
to 1 addressing the even and then odd por·
tlon of the RAM for each character row.
Figure 8 shows the DCGG as optional. By
using the 2672's spilt screen capability
and changing 2672 parameters, the CPU
can enable the DCGG to be active for a
portion of the screen thereby Incor·
poratlng both blt·mapped and alpha·
numeric sections on the same display.
BLANK
CHARACTER
GENERATOR
AND
C LATCHES
DADD7
L4
DADD6
L3
DADDS
L2
DADD4
L1
PVTC
,-- J
HSYNC I--
VSYNC
r-
Q I - - - LO
CK
~K
-=
TWO 2670', OR
EQUIVALENT
...
-"
Figure 7. Greater Than 16 Scan Lines Per Row
Signetics
6·49
MICROPROCESSOR DIVISION
JANUARY 1983
AppNote403
2670171/72/73 CRT SET APPLICATION BRIEFS
SYSTEM
DECODE
LOGIC
;..
I
I
I
I
'TT
.....
~
L
DCGG
-:v
CCLK
~
8·BIT
LATCH
I'
CE
PVTC
~
---v
VtI'<
RAM
.8
"
PVTe CONTROL
BIDIRECTIONAL
LATCH
I
V
CPU
.t.
..(";>.
"..
L.
:l..
"" 7-
A
CPU
CONTROL
CPU DATA BUS
Figure 8. Implementation of Bit Mapped Display
6·50
Signetics
.J
CHARACTER
DATA
7j,.
VAC
DOT DATA"
DISPLAY
ADDRESSES
CPiJAD~
~
r-r
Section 7
Microsystems
Signetics
JANUARY 1983
Signetics
SMDEV10000
568000 USER WORK STATION (UWS)
PRODUCT BRIEF
7
FEATURES
DESCRIPTION
•
The Signetics User Work Station (UWS) is a low cost, but powerful, tool
designed to work with Signetics language translators in a cross development environment. The UWS provides the capabilities required to
execute and debug software for the SCN68000 microprocessor. Software is first entered via the host computer text editor and then assembled or compiled utilizing Signetics cross development software tools.
The generated object code is downloaded to the UWS via a serial communications link. The engineer proceeds to test and debug the software
using the UWS ROM resident debugger to set execution breakpoints,
examine and modify registers, and make changes to the software utilizing the resident line oriented assembler/disassembler. The debugging
process may be accomplished entirely within the UWS or the available
UWS memory may be mapped into the system under development. The
connection to the system under development is accomplished with the
emulation cable and FootprinPM probe which makes all pins of the
SCN68000 available for connection of oscilloscope and logic analyzer
probes in addition to providing full 8MHz hardware emulation of the
SCN68000.
Permits existing support
equipment to be utilized
• 8MHz Hardware in·circuit
emulation via Signetics
Footprint
• Includes ROM resident
debugger and confidence
lests
• 8MHz SCN68000
microprocessor
• 64Kb of the lolal RAM
complement mappable to the
system under development
• 4 serial communications ports
as well as serial and
Centronics parallel printer
interfaces
• Designed to function wilh
Signetics cross software
producls
™Footprint is a trademark of Signetics Corporation.
Signetics
7·1
JANUARY 1983
MICROPROCESSOR DIVISION
sMDEV10000 568000 USER WORK STATION (UWs)
PERIPHERAL SUPPORT
ASSEMBLER/DISASSEMBLER
The UWS firmware supports a variety of
peripheral devices that are normally required in the development process. The
primary peripheral device supported by
the UWS is the console terminal. It can be
of nearly any type but must transmit serial
data in the speed range of 110 to 19,200
bits per second and have an interface
which conforms to the RS-232 interface
definition. The UWS supports a serial
printer interface and a Centronics parallel
printer interface. These hard copy devices
may be used to maintain a permanent
record of trace data, breakpoint lists,
PROM contents, and other information
that the UWS firmware can provide. A
serial port connection is provided for a
PROM programmer interface. The firmware contains drivers for the DATA 1/0
Model 19 and Kontron PROM programmers. In addition, commands are present
to allow reading, writing, and verifying of
PROMs. The host computer interface is
deSigned to be compatible with standard
modems or short distance line drivers that
support the RS·232 interface. The UWS
firmware supports transparent terminal to
host operation, downloading of object
code from the host to the UWS and up·
loading of debugged or partially debugged
object code from the UWS to the host.
One of the most useful features of the
Signetics UWS is a resident line oriented
assembler and disassembler. This feature
facilitates the debugging process by permitting the engineer to translate existing
Hex va.lues of the machine code into readable mnemonics, or to create and insert
new SCN68000 instructions into the routine being tested. The assemble (AS) command causes the UWS debugger to enter a
li.ne assembler mode at a user specified
address. the engineer may begin entering
SCN68000 assembler instructions from
the keyboard. The instructions will be
assembled and stored at consecutive
CONFIDENCE TESTS
A set of ROM resident confidence tests
are included in the UWS. These tests are
intended to provide a set of known opera·
tions on the serial and the parallel interfaces that the UWS may be commanded to
execute to aid in the installation of the
unit. In addition, a test of the RAM
memory is executed each time the UWS
power is turned on. If any errors are
encountered in RAM memory, the "Power
Fail" LEO on the front panel will remain lit
and the UWS will halt. The execution of
the confidence tests is controlled by
switch settings in the UWS and is not
dependent on a functioning console terminal or other peripheral devices.
7·2
address locations until a null line or a con·
trol Z is entered. Each 'instruction is
verified as it is stored in memory. As each
line is entered, both the relative and absolute addresses of the generated code,
as well as the resultant machine code, is
displayed on the CRT. The disassemble
(01) command allows the UWS to accept a
range of addresses where code is to be
disassembled. As a result of this operation, the engineer will be able to display
the relative and absolute instruction
address, a Hex translation of the machine
code, the instruction mnemonic, and the
instruction operands within the specified
range.
The following is an example of the assemble command:
MA 1
>AS 10000
"CLR.L 00
010000010000 INS = 4280
"CLR.L 01
010002010002 INS = 4281
"CRL.L 02
010004010004 INS = 4282
"MOVEA.L 10200,AO
010006010006 INS = 207900010200
"MOVEA.L 10204,A1
01000C 01000C INS = 227900010204
"MOVEA.L 10208,A2
010012010012 INS= 247900010208
"MOVE.L OO,[AO]
010018010018 INS = 2080
"MOVE L 01,[A1]
01001A 01001A INS= 2281
"MOVE.L 02,[A2]
01001C 01001C INS= 2482
"AOO.L #1,[AO]
01001E 01001E INS=5290
"AOO.L #2,[A1]
010020010020 INS= 5491
"AOOO.L #3,[A2]
010022010022 INS = 5692
"JMP 100001\.L
010024010024 INS = 4EF900010000
Signetics
CLR.L 00
CLR. L 01
CLR.L 02
MOVEA.L 102001\.L,AO
MOVEA.L 102041\.L,A1
MOVEA.L 102081\.L,A2
MOVE.L OO,[AO]
MOVE L 01,[A1]
MOVE.L 02,[A2]
AOOO.L #1 ,[AO]
AOOO.L #2,[A1]
AOOO.L #3,[A2]
JMP.L 100001\.L
MICROPROCESSOR DIVISION
JANUARY 1983
SMDEV 10000 568000 USER WORK STATION (UWS)
COMMAND SUMMARY
Abort
Assemble
Auto Dtack
Clock
Configure
Delete Breakpoint
Delete Offset
Delete Trace
Disassemble
Display Memory
Display Registers
Download
Go
Host
List Breakpoint
List History
List Offset
List Trace
Manual Breakpoint
Map
Mode
Patch Memory
Patch Registers
Read PROM
Record
Set Breakpoint
Set Offset
Set Trace
Single Step Mode
Single Step
Start Output
Stop Output
Trigger
Upload
Verify PROM
Write PROM
FEATURES
• The UWS is designed to allow software
development to occur on mainframes
or minicomputers
• Does not restrict the user to one
specific peripheral device
• Uses an established 68000 format
• The results of a debug session can be
stored and retrieved at a later time
• Offers increased timing flexibility and
permits debugging to occur with or
without a target system
• Gives a user greater control of the
debugging environment
• The UWS has incorporated the most
desirable features of more expensive
emulation systems
OPERATING ENVIRONMENT
• The UWS provides the capability for
both hardware emulation and
software execution
One asynchronous CRT terminal with EIA
RS·232 interface.
• Both the serial and parallel ports may
be reconfigured to match available
peripherals
One modem or suitable substitute that
provides an EIA RS·232 interface for asyn·
chronous communication with the host
computer.
• The UWS upload/download utility
accepts object records in Motorola
S·record format
User Supplied Optional Hardware
• The UWS permits object code to be
either downloaded or uploaded
• The UWS can use an internal or
external clock
User Supplied Required Hardware
One Data I/O Model 19 PROM programmer
or Kontron PROM programmer.
One asynchronous
RS·232 interface.
serial
printer with
Centronics Parallel Printer Cable
Emulation Cable
Footprint™ probe
Coaxial Clock Cable
Physical Characteristics
Height:
Width:
Depth:
Weight:
Shipping weight:
5.22 inches
16.88 inches
22 inches
21 pounds
31 pounds
Electrical Requirements
117 Volts AC± 10%, 60Hz± 15%
7
Environmental Characteristics
Operating temperature range: O· to 40·C
Operating humidity range: 0 to 95%
relative humidity with no condensation.
ORDERING INFORMATION
SMDEV10000 S68000 User Work
Station (UWS), 110·120 volt
60Hz
SMDEV10010 S68000 UWS
Footprint™ probe, spare
One Centronics parallel interface printer.
• Up to 10 concurrent breakpoints are
supported
SMDEV10015 S68000 UWS 8M Hz
Emulation Cable, spare
Required Software
SMDEV10020 S68000 UWS Cable Set,
spare. Includes:
Power Cable
CRT Cable
Test/PROM
Programmer Cable
Centronics Parallel
Printer Cable
Coaxial Clock Cable
BENEFITS
One or more
translators.
• Hardware which already exists in the
work environment can continue to be
used and shared for software
development
Host resident upload/download software
(included with Signetics language
translators).
• Provides a low cost solution for
68000 code development
Equipment Supplied
• Reduces development and debugging
time and increases user
productivity
Signetics
UWS with power cord
User Manual
CRT Cable
Test/PROM Programmer Cable
Signetics
language
DOCUMENTATION ORDERING
INFORMATION
SMMAN3100 S68000 UWS User Manual
SMMAN7100 S68000 UWS Reference
Card
7·3
JANUARY 1983
Signetics
SMSFT10000
S68000 CROSS SOFTWARE
MACRO ASSEMBLER
PRODUCT BRIEF
FEATURES
DESCRIPTION
• Powerful, Motorola-compatible
assembly language
• Interfaces directly to
Signetics 68000 Pascal
• Unambiguous source
language definition
• Registers may have symbolic
names
• Highly flexible constant
definition
• Both symbolic and mnemonic
logical operators are
supported
• Jump instruction format is
optimized automatically
• Full complement of assembler
directives
• "Section" directive allows
complete control of code and
data placement
• Record and Field capabilities
for highly structural data
definitions
• Structured conditional
assembly directives
• Modular programming support
• Source library facility
• Powerful macro facility
• Linkage editor and download
software included
The Signetics 68000 Macro Assembler is a powerful assembler that
combines the convenience of Motorola compatible instruction mnemonics with an unambiguous language definition and many useful constructs usually found only in high level languages. The Signetics 68000
Macro Assembler is a perfect complement to high level languages and
an excellent implementation language with capabilities such as modular programming support, record and field data definition ability, a
source library facility that includes source only when referenced, and
assembler directives that minimize the task of parameter passing to
subroutines. The Signetics macro facility offers normal macro features
such as parameter substitution and nesting but is not a character oriented facility and does not support concatenation of symbols. The
linkage editor for linking separately assembled modules is included in
the package. This linkage editor may also be used with the object modules generated by the Pascal cross compiler, or to link Pascal and
assembler generated modules together. The upload and download software that allows host communication is also included in the package. It
is designed to interface with the Signetics User Work Station (UWS) and
allows transfer of object code between the host computer and the UWS
as well as between the UWS and the host computer.
7-4
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
SMSFT10000 568000 CROSS SOFTWARE MACRO ASSEMBLER
BENEFITS
•
The Signetics 68000 Macro Assembler
is Motorola instruction compatible, so
no extensive retraining is required for
software engineers.
•
The modular programming support
allows sharing of program modules
generated by the assembler or by
high level languages such as Pascal.
•
Sections of source code identified as
libraries by the "LIB" and "ENDUB"
assembler will process automatically
if they are referenced.
•
The conditional and duplicated
assembly capabilities allow maximum
flexibility in source code structure.
•
The use of subroutines is encouraged
by the availability of assembler direc·
tives that support the definition and
manipulation of parameter lists.
OPERATING ENVIRONMENT
Operating System
Requirements
Computer
any VAX-11 computer
VMS
(a.) VMS V2.4 or later
(b.) 64Kb of real memory per active assembler user
(c.) 10Mb of disk storage
RSX-11M
any PDp-11 computer;
any LSI-11/23 series computer
(a.) RSX·11M V3.2 or later
(b.) minimum 128Kb total system memory to support one assembler user;
64Kb for each additional assembler user
(c.) 10Mb of disk storage
Contact Rikki Kirzner for further product information on computers, operating systems, media, or formats not shown.
ORDERING INFORMATION
Order No.
Product
Operating System
Media
SMSFT10000
S68000 Macro Assembler'
VMS
Half·inch magnetic tape 800 BPI
SMSFT10300
S68000 Macro Assembler'
RSX-11M
Half·inch magnetic tape 800 BPI
SMSFT10390
S68000 Macro Assembler'
RSX·11M
8-inch double density diskette
DOCUMENTATION ORDERING INFORMATION
Order Number
Product
SMMAN5205
S68000 Macro Assembler Reference Manual
SMMAN7211
S68000 Macro Assembler Installation Guide, RSX·11M Operating
System
SMMAN7210
S68000 Macro Assembler Installation Guide, VMS Operating System
SMMAN3231
S68000 Macro Assembler User Guide
'Requires software license agreement.
Signetics
7·5
7
JANUARY 1983
Signetics
SMSFT16000
S68000 CROSS SOFTWARE
PASCAL CROSS COMPILER
PRODUCT BRIEF
FEATURES
DESCRIPTION
• High level structured
programming language
• Structured data types
- Array, string, record,
boolean, character
- User·defined data types
• Modular programming
extensions
• Assembly language program
interface
• Complies with IEEE 770·81
standard
• Generates 68000 native code
• PROM·able run·time code
• Full listing format control
• Flexible compiler option
control
• Cross linkage editor and
upload/download software
included
The Signetics 68000 Pascal Cross Compiler is a powerful, flexible, high
level programming language. It complies with the IEEE 770-81 standard
which is based on the Pascal language developed by Niklaus Wirth in
1968. The compiler provides a highly structured environment that
simplifies program development, produces more reliable code, and in·
creases the productivity of the software engineer. Programming errors
are minimized by complete checking of data types within modules including user defined data types.
7·6
The Signetics 68000 Pascal Cross Compiler is designed to be extremely
modular with an emphasis on portability. The compiler, itself, is a result
of utilizing truly state-of-the-art compiler design techniques to produce
a superior language translator.
The Pascal Cross Compiler allows the mass storage and development
tools available on minicomputers and mainframes to be used in the
creation of microprocessor software. It is not necessary to purchase expensive, special purpose computers that are typically used only for
microprocessor software development. The upload/download software
provides a convenient path for object code to be sent from the host
computer to the Signetics User Work Station (UWS) and for partially or
completely debugged object code to be saved on the disk of the host
computer. All object code is sent utilizing a protocol that includes error
detection and control facilities to insure the validity of the transmitted
data.
Signetics
MICROPROCESSOR DIVISION
JANUARY 1983
SMSFT16000 568000 CROSS SOFTWARE PASCAL CROSS COMPILER
SIGNETICS PASCAL EXTENSIONS
- Allows modular programming and facilitates sharing of routines by multiple programs and projects.
Separate Compilation
Assembly Language Interface - Permits mixing Pascal and assembly language routines for maximum performance and ease of direct
hardware control.
INCLUDE Facility
- Facilitates sharing of source code and declarations of constants and variables by multiple programs
and projects.
Compile Time Switches
- Provides control of compiler options such as array index checking.
Assembly Code Generation
- Simplifies performance tuning of critical program modules.
EXAMPLE
The following Pascal program is an example of the structure of a Pascal program. This program is designed to eliminate all trailing blanks
from the end of each line within a file such that the line termination character occurs after the last non-blank character in the line. It illustrates the use of subroutines, typing of variables, and loop structures. The actual implementation of input and output routines is system
dependent, but the read and write statements used are those of the IEEE 770·81 standard.
program compact (source, destination);
const
BLANK=' ';
LlNESIZE= 140;
type
linerange= 1.. LlNESIZE;
linetype = packed array[linerange] of char;
var
source, destination: text;
line: linetype;
length, cur, lastnonblank : linerange:
c: char;
7
procedure getsourceline;
begin
length:= 1;
line[length] := BLANK;
while not (eoln (source)) and (length
begin
< LlNESIZE) do
read (source, c);
line[length] := c;
length := length + 1
end;
readln (source);
if length> 1 then length := length - 1
end;
begin
reset (source);
rewrite (destination);
while not eof(source) do
begin getsourceline;
lastnonblank:= 1;
for cur:= 1 to length
do
if IIne[cur] < > BLANK
then lastnonblank := cur;
for cur := 1 to lastnonblank
do
write (destination, line[curl]);
writeln (destination)
end
end.
Signetics
7·7
MICROPROCESSOR DIVISION
JANUARY 1983
SMSFT16000 S68000 CROSS SOFTWARE PASCAL CROSS COMPILER
BENEFITS
• Signetlcs Pascal provides a standard·
ized environment for developing soft·
ware for the 68000.
• It allows individuals familiar with
Pascal to be immediately productive.
• It is easy to learn since the IEEE
770·81 standard it adheres to is based
on the Niklaus Wirth software engi·
neerlng teaching vehicle.
• It has few machine specific extensions
to maximize portability.
• It improves productivity by allowing
multiple programs and projects to
share both source and object code.
• An assembly language interface is pro·
vided to allow direct manipulation of
hardware and maximize the perfor·
mance of time critical modules.
• The Pascal compiler can optionally
generate assembly language with
source code interlisted as comments
to minimize the task of performance
tuning in real time systems.
• A full range of listing controls is pro·
vided to enhance maintainability of the
source code.
• The compiler generated code is opti·
mized in constant and sub·expresslon
usage, array indexing, jumps, and
storage allocation for maximum use of
target system resources.
• An object module .Iinker with library
capability is included with the Pascal,
which links together Pascal and
assembly language modules and
allows specification of starting
addresses of all modules.
OPERATING ENVIRONMENT
Operating
System
VMS
Computers
Requirements
any VAX·ll computer
(a.) 64Kb of real memory per active compiler user
(b.) VMS V2.4 or later
(c.) 10Mb of disk storage
RSX·llM
any PDp·l1 computer;
any LSI·11/23 series computer
(a.) RSX·llM operating system V3.2 or later
(b.) minimum 128Kb total system memory to support one compiler user;
64Kb for each additional compiler user
(c.) 10Mb of disk storage
ORDERING INFORMATION
Operating System
Product
SMSFT16000
PASCAL 68000'
S68000 Macro Assembler'
VMS
Half·inch magnetic tape 800 BPI
SMSFT16300
PASCAL 68000'
S68000 Macro Assembler'
RSX·llM
Half·inch magnetic tape 800 BPI
SMSFT16390
PASCAL 68000'
S68000 Macro Assembler'
RSX·llM
8·inch double density diskette
Other host
comp~ters,
operating systems, or alternate media contact factory.
DOCUMENTATION ORDERING INFORMATION
Order Number
Product
SMMAN5200
S68000 Pascal Language Reference Manual
SMMAN5205
S68000 Macro Assembler Reference Manual
SMMAN7200
S68000 Pascal Installation Guide, VMS Operating System
SMMAN7210
S68000 Macro Assembler Installation Guide, VMS Operating
System
SMMAN7201
S68000 Pascal Installation Guide, RSX·l1 M Operating System
SMMAN7211
S68000 Macro Assembler Installation Guide, RSX·llM
Operating System
SMMAN3230
S68000 Pascal Compiler User Guide
SMMAN3231
S68000 Macro Assembler User Guide
• Requires software license agreement.
7.8
Media
Order Number
Signetics
Section 8
Appendices
Signetics
I
I
I
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I
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I
I
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I
I
I
I
I
I
I
I
I
I
I
I
I
I
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I
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JANUARY 1983
MICROPROCESSOR DIVISION
PACKAGES-GENERAL INFORMATION
Plastic Only
INTRODUCTION
The following information applies to all
packages unless otherwise specified on individual package outline drawings.
General
1_ Dimensions shown are metric units (millimeters), except those in parentheses
which are English units (inches).
2. Lead spacing shall be measured within
this zone.
a. Shoulder and lead tip dimensions are to
centerline of leads.
3. Tolerances non-cumulative
4. Thermal resistance values are deter·
mined by utilizing the linear temperature
dependence of the forward voltage drop
across the substrate diode in a digital
device to monitor the junction temperature rise during known power application across VCC and ground. The values
are based upon 120 mils square die for
plastic packages and a 90 mils square
die in the smallest available cavity for
hermetic packages. All units were solder mounted to P.C. boards, with standard stand-off, for measurement.
5. Lead material: Alloy 42 (Nickeiliron AI·
loy) Olin 194 (Copper Alloy) or equiv'
alents, solder dipped.
6. Body material: Plastic (Epoxy)
7. Round hole in top corner denotes lead
No.1.
8. Body dimensions do not include molding
flash.
HermetiC Only
9. Lead material
a. ASTM alloy F'15 (KOVAR) or equivalentgold plated, tin plated. or solder dipped.
b. ASTM alloy F-30 (Alloy 42) or equivalenttin plated, gold plated or solder dipped.
c. ASTM alloy F-15 (KOVAR) or equivalentgold plated.
11. Lid Material
a. Nickel or tin plated nickel. weld seal.
b. CeramiC, gl.s. 8eal.
c. ASTM alloy F·15 or equivalenl. gold plated,
alloy seel.
d. BeO Ceramic with glas8 seal.
12. Signetics symbol, angle cut, or lead tab
denotes Lead No.1.
13. Recommended minimum offset before
lead bend.
14. Maximum glass climb .010 inches.
15. Maximum glass climb or lid skew is .010
inches.
16. Typical four places.
17. Dimension also applies to seating plane.
10. Body Material
a. Eyelet, ASTM alloy F-15 or equivalentgold or tin plated. gla .. body.
b. Ceramic with glass seal at leads.
c. BeO ceramic with glass s8al at leads.
d. Ceramic with ASTM alloy F·30 or equivalent.
THERMAL RESISTANCE
NO. OF LEADS
8 JA
8 JC
Plastic DIP
14
16
24
28
40
150
160
106
116
70
65
75
49
53
50
Ceramic DIP
14
16
28
40
95
90
60
55
25
25
25
25
8
For other ratings not listed here, contact
your nearest Signetics sales office.
Signetics
8·1
MICROPROCESSOR DIVISION
JANUARY 1982
PACKAGE OUTLINES
N PACKAGE - PLASTIC
(ill-PIN)
I PACKAGE - HERMETIC
(is·PIN)
I~[~~]~~
I
20,10 tB1S)
19.93 (.7861
I
7.371.290
J:;~~~~1~~~.~51~.5~'0!1~~.~r;~~~~~~::r~~~5~:~~1~8.~'3~1~.3~~~1~
0.31 (.0121
- - f - - j 0.20 (.OOB)
I 8.741.3441.'
7.111.2801
2.79(.110)
2.291.0801
NON·
CUMULATIVE
8·2
Signetics
~
NOTE 2
T
MICROPROCESSOR DIVISION
JANUARY 1982
PACKAGE OUTLINES
N PACKAGE - PLASTIC SLIM LINE
(24·PIN)
LEAD NO. 1
r-
10.41(.410)
"9.§'i'T.39o')
0.38(.015)
0.25(.010)
I~I
2.79(.110)
I-' 10.16(.400)--1
2.29T.ii9O)
NONCUMULATIVE
8
Signetics
8·3
JANUARY 1982
MICROPROCESSOR DIVISION
PACKAGE OUTLINES
N PACKAGE - PLASTIC
(28·PIN)
~
1.12(.0441
~
0.38 (.0151
2.161.0861
1.65 (.0651
2.79 (.110)
2.2iT.09Oi
NON·
CUMULATIVE
I PACKAGE - HERMETIC
(28·PIN)
rlEADNO.1
. . . . . . . .O.........-.
. . . . . . . . . (JI
.
~~~..~..~~~~~~~l j(.
580
14.n
I
36.32 (1.4301----11.78 (.070tt'15.74 (.6201
35.05(1.3801~
14.98 (.5901
~
13.46(.5301
12.95 (.5101
-.l..-
J1
~
0.31 (.01~!~
0.20 (.0081
:-r-
1,13.46(.530I
12.95 (.5101
NOTE 2
1.65 (.065)
0.76 (.030)
~~ 0.53 (.0211
1.52 (.0601
1.14(.0451
8·4
.--l
I'
0.38(.0151 2.79 (.1101
2.29 (.0901
~
2.03 (.OSOI
NON·
CUMULATIVE
Signetics
16.36 (.6441-1
14.n (.5801 -I
4.45(.1751
3.18 (.1251
JANUARY 1982
MICROPROCESSOR DIVISION
PACKAGE OUTLINES
N PACKAGE - PLASTIC
(40·PIN)
LEAD NO. 1
17.651.665)
15.2iT.6Ooi
I PACKAGE - HERMETIC
(40·PIN)
8
D
I
~15'741'620)
14.981.5901-
3'05l'ZO)
2.031.060)
~~;:n:i'iJ~dii::R:i;a:EFi:1b=U;U=;:ru;:r;:;;l ....l_ _ _ _......_ _
-.------~f~lr
•
l
-:....-----.,;-f-
13'461'530)
.-.L-.
~~1.012)
"'1 95 51
16.361.644)
l- i4.13T.68Oi -I
NOTE 2
0.201.0081
4.451.175)
NON
CUMULATIVE
Signetics
3.i'iT.'i25i
8·5
MICROPROCESSOR DIVISION
JANUARY 1983
PACKAGE OUTLINES
I PACKAGE -
HERMETIC
(48·PIN)
'.:::::::::[~:::J:::::::::{~
_
'
m
.
.
..
jt
80.35 (2.3781
•
_.1
[=fl~~=W1fiDiifiDFilliViiFinFniiiT'i1ir'm~=""""--~
,~~~
4.32(0.1801
1.524 (0.0801
~~_II~
0.100Bse
~
I
3.05 (0.1201
~
~~.
~~pq
~~~
I..
_1-1-
4.19(0.1651
2.54(0.1001
15.65(0.6161
14.99(0.590}
0.361 (0.0151
I PACKAGE - HERMETIC
(84·PIN)
l.:::::::::::::[:;:;j:::::::::::::i~
I
80.52 (3.170}
4.32 (0.1701
1.&2 (O.D8Ol
C=UU[jD[j~f~fWm"1friFt~inIi'illFiIIi9IIFiIIi"illi"ilIIi"3Il'~:==-t=.
~
.; ~~
.. FJ=E:I ~
nnnnnnnnnnnnnnnn
~L
I I
jt
3.05(0.1201
0.78(0.030}
2.&4BSC
0.100 Bse -
0.53 (0.0211
~
NOTE:
1. If solder dipped terminals used, terminal dimension tolerances may beine,eased by.OO1.
Signetics
-
(~.1851 I'
4.19
2.&4(0.1001
TO.2O(O.o08l
-I
23.11
22.81 (0.910}
(0.8901
MICROPROCESSOR DIVISION
JANUARY 1983
SALES OFFICES
SIGNETICS
MICHIGAN
Farminaton HHis
Phone: (313) 476-1610
HEADQUARTERS
MINNESOTA
Edina
Phone: (612) 835-7455
811 East Arques Avenue
P.O_ Box 409
Sunnyvale, California 94086
Phone: (408) 739-7700
ARIZONA
Phoenix
Phone: (602) 265-4444
CALIFORNIA
Canoga Park
Phone: (213) 340-1431
cu~ertino
hone: (408) 725-8100
In~ewood
PENNSYLVANIA
Horsham
Phone: (215) 443-5500
COLORADO
Aurora
Phone: (303) 751-5011
TENNESSEE
Greeneville
Phone: (615) 639-0251
Li~thouse Point
hone: (305) 782-8225
GEORGIA
Atlanta
Phone: (404) 953-{)067
IOWA
Cedar Rapids
Comstrand Inc_
Phone: (319) 377-1575
NORTH CAROLINA
Raleigh
Phone: (919) 851-2013
San Diego
Phone: (714) 560-{)242
FLORIDA
Clearwater
Phone: (813) 796-7086
ILLINOIS
Schaumburg
Micro-Tex, Inc_
Phone: (312) 885-ll31
NEW YORK
liverpool
Phone: (315) 451-5470
Melville
Phone: (516) 752-0130
Wa,~ingers Falls
one: (914) 297-4074
OHIO
Worthinaton
Phone: (614) 888-7143
CONNECTICUT
Danbury
Phone: (203) 748-3722
CONNECTICUT
Yalesville
Kanan Associates
Phone: (203) 265-2404
NEW JERSEY
Parsippany
Phone: (201) 334-4405
hone: (213) 670-1101
Irvine
Phone: (71~ 833-8980
(213) 588-3 81
CANADA
Etobicoke
Tech-Trek, ltd_
Phone: (416) 626-6676
Pointe Claire
Tech-Trek, Ltd_
Phone: (514) 697-3385
KANSAS
Kansas City
B_ C. Electronic Sales
Phone: (913) 342-1211
MASSACHUSETTS
Reading
Kanan Associates
Phone: (617) 944-8484
MICHIGAN
Bloomfield Hills
Enco Marketing
Phone: (313) 642-{)203
TEXAS
Austin
Phone: (512) 458-2591
Richardson
Phone: (214) 644-3500
MINNESOTA
Minnea~olis
High Technolofl Sales
Phone: (612) 8 8-8088
CANADA
SIGNETICS CANADA, lTD_
Etobicoke, Ontario
Phone: (416) 626-6676
SIGNETICS CANADAblTD.llTEE,
Pointe-Claire, lIfe ec
Phone: (514) 6 7-3385
ILLINOIS
SChaumbu~
Phone: ( 12) 843-7805
INDIANA
Kokomo
Phone: (317) 453-6462
KANSAS
Overland Park
Phone: (913) 341-8181
MARYLAND
Glen Burnie
Phone: (301) 787-0220
MASSACHUSETTS
Woburn
Phone: (617) 938-1000
REPRESENTATIVES
ALABAMA
Huntsville
Electronic Sales, Inc.
Phone: (205) 533-1735
ARIZONA
Thorn luke Sales, Inc.
Phone: (602) 941-1901
CALIFORNIA
los Gatos
Sierra TeChnOlon
Phone: (408) 3 -1626
San Diego
Mesa En~neerinl
Phone: ( 14) 27 -8021
MISSOURI
Bridgelon
B. C. Electronic Sales
Phone: (314) 291-1101
NEW JERSEY
East Hanover
Emtec Sales, Inc.
Phone: (201) 428-0600
NEW MEXICO
PENNSYLVANIA
PiltsbUfJ
Cove & Newman Co_
Phone: (412) 531-2002
UTAH
Salt Lake City
Electrod~ne
Phone: 01) 486-3801
WASHINGTON
Bellevue
Western Technical Sales
Phone: (206) 641-3900
Spokane
Western Technical Sales
Phone: (509) 922-7600
WISCONSIN
Waukesha
Micro-Tex, Inc_
Phone: (414) 542-5352
FOR SIGNETICS
PRODUCTS
WORLDWIDE:
ARGENTINA
Philips Argentina S_A.
Buenos Aires
Phone: 541-7141
AUSTRALIA
Philips Industries Holdings Ltd_
lane-Cove, N.S,W.
Phone: 61-2-427-{)888
AUSTRIA
Osterrichische Philips Bauelemente
Wien
Phone: 43-222-93-26-2
BELGIUM
N, V, PhHips & MBlE
Bruxelles
Phone: 32-02-242-7400
BRAZIL
Ibrape
Sao Paulo
Phone: 55-{)1l-211-2600
Albuquer~ue
CHILE
Philips Chilena S,A,
Santiago
Phone: 56-2-39-4001
NEW YORK
Ithaca
Bob Dean, Inc.
Phone: (607} 257-1111
Melville
Emiec Sales, Inc.
Phone: (516) 752-1630
COLOMBIA
Sadape S,A,
Bogota D.E_
Phone: 600 600
Power nterrrises
Phone: (505 298-1918
OREGON
Hillsboro
Western Technical Sales
Phone: (503) 640-4621
Signefics
DENMARK
Miniwatt AIS
Kobenhavn N.V.
Phone: 45-{)1-69-1622
FINLAND
Oy PhHips Ab
Helsinki
Phone: 358-l-7271
8·7
8
JANUARY 1983
MICROPROCESSOR DIVISION
SALES OFFICES
FRANCE
R.T.C..La RadIotechniqu.compelec
Pans
Phone: 33-1·355-4499
GERMANY
ITALY
Phllip's S.p.A.
Milano
Phone: 39·2-6994
JAPAN
~etics Japan, Ltd.
okyo
Phone: 813-230-1521
PERU
Cadesa
. lima
Phone: 326070
GREECE
Phlire $.A. Hellenlque
At ens
Phone: 9215111
KOREA
PhiUps Elect Korea LId.
seoul
Phone: 7944202
PHILIPPINES
Philips Industrial Dev., Inc.
Makati.ftizal
Phone: 868951
PORTUGAL
PhHips Portuguesa SARL
lisboa
Phone: 35H9-68-3121
HONG KONG
Philips Honl KOIII. Ltd.
Kwai chunf
Phone: 85 .(1·245121
MALAYSIA
Philips Malaysia $dn. Berhad
Kuala lumpur
Phone: 77 44 11
SINGAPORE
Philips Project Dev. Pte., Ltd.
Sinl8Pore
Phone: 65-253-8811
INDIA
Pelco Electronics & Elect. Ltd.
Bombay
Phone: 91·22·221.(112
MEXICO
Electronica S.A. de C.V.
Mexico OJ.
Phone: 905·533·1180
SOUTH AFRICA
E.D.A.C. (PTY~ Ltd.
Johannesburg
Phone: 27-11-614-2362
INDONESIA
P.T. Philips-Ralill Electronics
Jakarta
Phone: 716 131
IRELAND
Philips Electrical Ltd.
Dublin
Phone: 353-1-69-3355
ISRAEL
Ra~C Electronics. Ltd.
elAviv
Phone: 972·3-47715
NETHERLANDS
Nederland B.V.
Eindhoven
Phone: 31-4()'79-3333
SPAIN
Miniwall U.
Barcelona
Phone: 301 63 12
Valvo
Hambu1
Phone: 9-4()'3296-19
8·8
p.
NEW ZEALAND
Philips Eleetricallnd. Ltd.
Auckland
Phone: 64·9-894-160
NORWAY
Norsk A/S PhHips
Oslo
Phone: (02) 680200
SWEDEN
A.B. Elcoma
Stockholm
Phone: 46.(18-67·9780
SWITZERLAND
PhHips U.
Zurich
Phone: 41-01-988-2211
Signetics
TAIWAN
Philips Taiwan, LId.
Taipei
Phone: 886-2·563-1717
THAILAND
PhH~S Electrical Co.
T ailand LId.
Bangkok
Phone: 233-6330-9
0'
TURKEY
Turk Phili§S
Ticaret A..
Istanbul
Phone: 43 59 10
UNITED KINGDOM
Mullard, LId.
london
Phone: 44-01·580-6633
UNITED STATES
Signetics International Corp.
Sunnyvale. California
Phone: (408) 739-7700
URUGUAY
Luzilectron S.A.
Montevideo
Phone: 91 43 21
VENEZUELA
Industrias Venezolanas
Philips S.A.
Caracas
Phone: 58-2·36-0511
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