1983_Toshiba_MOS_Memory 1983 Toshiba MOS Memory

User Manual: 1983_Toshiba_MOS_Memory

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TOSHIBA AMERICA INC.

DATA BOOK

'83-4

WeStem Microtechnology
10040 Bubb Road
Cupenino, CA 95014
P~oDe (408) 72SeI660
TWX 910-338-0013

TOSHIBA AMERIC

INC.

TOSHIBA
MOS MEMORY PRODUCTS
DATA BOOK

TOSHIBA

TABLE OF CONTENTS
Memory Product Guide . . . . . .
Byte-Wide Memory Pin Out Table .
Cross Reference . . . . . . . . . . .

1
12
. . . . . . . 13

Dynamic Random Access Memories
TMM416P. . . . . . . . . .. . . . . . .
. ..........
TMM4164P . . . . . . . . . ..
. .... .
TMM4164AP . . . . . . . . . .
*TMM41256C . . . . . . . . . .
Static Random Access Memories
TMM314AP/APL . . . . . . . . . . . . . .
TMM2114AP . . . . . . . . . . . . . . . . . . . . .
TMM315D . . .
. ............
TMM2016P/D . . . . . . . . . . . . . . . . . . .
TMM2016AP . .
. ............
TMM2015AP . . . . . . . . . . . . . .
TMM2018D . . . . . . . . . . . . . . . . .

.
.
.
.

17
29
37
45

. . . . . . . 55
61
67
71
77
83
89

CMOS Static Random Access Memories
4K Bit CMOS RAM TC5514!TC5513 Comparison Table.
16K Bit CMOS RAM TC5516/TC5517/TC5518
Comparison Table . . . . . . . . . . .. . . .
CMOS RAM Data Retention Characteristics ..
TC5501 P . . . . . . . . . . . . . . . . . . . . . .
. ..
TC5047AP . . . . . . . . . . . . . . . . . . . . .
. ......
TC5504AP/AD . . . , . . . . . .
. ............
TC5513AP/AD . . . , . . . . . .
. ............
TC5514AP/AD. . . .
. ............
TC5514P . . . . . . . . . . . . . .
TC5516AP/AD/AF .
. ............
TC5517AP/AD/AF .
. ................
TC5517BP/BD/BF . ..
. ....................
TC5518BP/BD/BF . . . . . . . . . . . . . . . . . . . . . . . . . .
*TC5564P . . . . . . . . . . . . . . . . . . . . . .
. . . . .
TC5565P .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

97
98
99
101
109
117
123
131
139
145
157
165
173
181
189

Erasable/Programmable Read Only Memories
TMM2764D . . . . . . . . . . . . . . . . . . . . . . . . . . .
TMM2764DI .. '.' . . . . . . . . . . . . . . . . . .
TMM27128D . . . . . . . . . . . . . . . . , . . . . . . . . .

.199
·207
·215

Mask Programmable Read Only Memories
TMM334P. . . . . . . . . . . . . .
. ..... .
TMM333P . . . . . . . . . . . . . . . . . . . . .
TMM2332P . . . . . . . . . . . . . . . . . . . . . . . . .
TMM2364P . . . . . . . . . . . . . . . . . . . . . . . . .
TMM2365P . . . . . . . . . . . . .
TMM2366P . . . . . . . . . . . . . . .
*TMM23128P . . . . . . . . . . . . . . . . . . . .
TMM23256P . . . . . . . . . . . . . . . . . . . .

·225
·229
·233
·237
·245
·249
·253
·255

·
·
·
·

.
.
.
.

CMOS Mask Programmable Read Only Memories
32K Bit CMOS Mask ROM Comparison Table . . . . . . . . . . 263
TC5332P .. . . . .
. . . . . .
. . . . . . . . . 265
TC5333P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 273
TC5334P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
TC5335P . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285
*TC5364P
. . . . . . . .
. . . . ..
. . . . . . . 291
*TC5365P
. . . . . .
. ... "
. . . . . .. 295
*TC5366P
. . . . . .
. . . . . .
. . . . . . . 299
*TC53256P . . . .
. . . . . .
. . . . . . . . . . . . . . . 303
*: PRELIMINARY

MEMORY

PRODUCT
GUIDE ~

.,.,. ......

.

~~

-

1 -

TOSHIBA
1. Dynamic RAM

=To

Device Number

Capacity

1-----

I
I

64K B;,

TMM416P-3

16.384 x 1

NMOS

150

100

320

+5

200

135

375

-5

[TMM4164P-3

I'

I TMM4164P-4

1

I

TMM41~

TMM4164AP-15
TMM4164AP-20

150

65,536 x 1

1

1

NMOS

L

~oo
_ ~

256KB;~:rTM~M4i256c~121262144X1 I NM~"ITMM41256C-15

I')

150
200

Max. (mW)

Pins

Alternate
Source

16

MK4116-3

i

Standby

MK4116-2

~~~

+12

100

260

+5

135
60

330

~

75
100

260
330

+5

220
260

+5

-'20---60
150 __ ~~._I

I

Powe~ Dissipation

S~:=I~~

_'-:;R:c:A,C~'--f--,'Cco:A~C,--+-M_;ocn'",(c-ns_)+_(c;Vc-)_+--A_ctive

1:~

1

~y~:

(os)

~~:;:;~:i-~-- -~ ~~~

1

[

Process

I

1-----+cTc-Mc·M~-c416P-2
16K B;'

Access Time Max.

Organization

462

20

II

MK4116-4
1
I

275

1

27~5

1

I

16

1

I

I

1

i

_

J

275

I

22

1

16

27.5

1

16

I

_3:JO----!
275

Note; TMM41256C : Page Mode Parts

2. Static RAM
Alternate

Pins

Source

12114-2
550
TMM314AP

I

450
450
NMOS 1----c=-=0C:C-+---::ZOO-2 0

__

'TMM-:l14APL-1

1 1,024 x 4

rnv,M314AP L -3
4K Bit

300
450

TMM314APL

~MtJl2~1~P-121

TMM2114AP-15.

1 024 x 4
'

NMOS

~M~1t5D=1---1-4~;;;'~--::-O~
TMM315D
TMM2016P/D-1

c-----

I '

f--------,
TMM2016P/D

:

120
150
55

70
- - - 1 - 100--

300
450

i2114L-3

120

+5

330

_

880
660

18
12147-3
110
8''"3---+-----4-----1

i2114A
18
150 I
f-~--+-5-+--9C-9:-:0--+---1~:-:,
5 - - + - - + - - - - - -1

70

1

--:,00-1--- +5

_ _5

50 __ +_~_.Jl~ __

l2~~~AP-10

1 2048 x 8
ITMM2016AP=i2l'

f------~

I

90

90

: NMOS
I

100
120

100
120

+5

NMOS

120

120

+5

150
45

150
45

II--~!.---i
358

I

I

LT'''1M201.6!,P~~~! _____ -+-_L_~
150
1. 358
*1 TMM2015AP-90 t i '
90
-90----' --;;;;0-'-1
*1 -rMM2015AP~
I
1-- 1'00 -1'00--358-----1

1

*ITMM2015AP-=12-

1

*1TMM2~
'TMMwiSD=4;,'----------+

I

16K B;'

2,048x8

'j'

I

38.5

I
I

1

1 24
1
358
1
1
1
-+--==---+-1-----+--1------1I

TMM2016AP 0.6 inch width 01 P
TMM2Q15AP: 0.3 inch width DIP
TMM2018D: 0.3 inch width 01 P

Note; Package Material P: Plastic C: Ceramic 0: Cerdip F: Plastic Flat
*Preliminary: These are target specifications and are subject to change without notice.

3 -

(HM6116i

24

1
---------1--+-----

358

1

38.5

24
1~____~M3.-0-18-D-55-~-,,-~l:~ClS ~_55=I_-----'=----J_55_J_~_ _ _ _ _7_8_8_ _1__1_0_5_ _~
I
Note; Package

(HM6116)

24

t-----+- 20~~ I--~~---- f-_7_70:_ _+--__1c.:6c::5_ _+--_-+___-J

1~~~26~~

I

i2114

----:-12114L-2
i2114L

1

I TMMW16P/D.::::z1

I

18

385

NMOS ~ r--~

2,048 x 8

;2114-3

-----+------1

+5

I
1

-

I

TOSHIBA
3. CMOS Static RAM
Organization

Device Number

Capacity

TC5501P
TC5501 P-l
TC5047AP-l

1 K Bit

TC5047AP-2
TC5504AP/AD-2
TC5504AP/AD-3
TC5504APl/ADl-2
TC5504APl/ADl-3
TC5514AP/AD-2
TC5514AP/AD-3
TC5514APl/ADl-2
TC5514APl/ADl-3
TC5513AP/AD-20
TC5513APl/ADl-20
TC5514P
TC5514P-l
TC5516AP/AD/AF-2
TC5516AP/AD/AF
TC5516APl/AOl/AFl-2
TC5516APl/AOl/AFl
TC5517AP/AD/AF-2
TC5517AP/AD/AF
TC5517APl/AOl/AFl-2
TC5517APl/ADl/AFl
TC5517BP/BD/BF-20
TC5517BPl/BOl/BF l-20

4K Bit

16K Bit

TC5518BP/BD/BF -20
TC5518BPl/BDl/BF l-20

64K Bit

•
•
•
•

TC5564P-1O
TC5564P-15
'Tc5564P l- 10
TC5564Pl-15
TC5565P-12
TC5565P-15
'Tc5565Pl-12
TC5565Pl-15

Note Package Material

P: Plastic

256 x 4

CMOS

1.024 x 4

CMOS

4.096 x·l

CMOS

1.024 x 4

CMOS

1.024 x 4

CMOS

1.024 x 4

CMOS

2.048 x 8

CMOS

2.048 x 8

CMOS

2.048 x 8

CMOS

2.048 x 8

CMOS

8.192x8

CMOS

8,192x8

C: Ceramic

Cycl.

Max. Ins)

Time
Min. (ns)

450
650
550
800

450
650
650
1000

200
300
200
300
200
300
200
300
200
200
450
650
200
250
200
250
200
250
200
250
200
200
200
200
100
150
100
150
120

300
420
300
420
200
300
200
300
200
200
450
650
200
250
200
250
200
250

150
120
150

CMOS/
NMOS

D: Cerdip

Access

Time

Process

200
250
200
200
200
200
100
150
100
150
120
150
120
150

F: Plastic Flat

*Preliminary: These are target specifications and are subject to change without notice.

-

4 -

Power Dissipation
Max. (mW)

Power
Supplies
(VI

Active

Standby

+5

83

0.055

22

+5

110

0.11

20

J,tP0445

18

iHM65041

27.5

0.11

27.5

0.005

27.5

0.11

27.5

0.005

27.5

0.11
0.005

18

0.11

18

+5

18

+5

+5
+5

138

r--;,o
385

0.165

385

0.005

385

0.165

385

0.005

+5

24

0.165

i5101l-1
i5101l

I
iHM6514)

24

+5

Alternate
Source

Pins

+5

55

---0:005

24

+5

55

.~ 24

+5

55

r------

0.165

iTMM20161
iHM6116l)

iTMM2016)
iHM6116L)

-

0.11
28

-

28

-

0.005
5.5
+5

55

r-----0.55

TOSHIBA
4.

Erasable Programmable ROM

Time

Cycle
Time

Supplies

Max. (ns)

Min. (ns)

(V)

200

200

250

250

Access

Capacity

Process

Organization

Device Number

TMM2764D-2
TMM2764D

64K Bit

TMM2764DI-2
I

128K Bi.

Note;

5

8,192<8

NMOS

200

200

TMM2764DI

250

250

TMM27128D-20

200

200

250

250

16,384 < 8

TMM27128D-25

NMOS

Power Dissipation
Max. (mW)

Power

Active

Standby

630

184

Alternate
Source

Pins

i2764

+5

28

+5

683

210

630

184

28

i27128

TMM2764DI/DI-2: (Operating temperature range: _40°C ,",-,85°C)

Mask Programmable ROM

Capacity

Device Nnumbe,

I O'9ani,a'ion

Process

f~!,1t.,1~~~4P_ _ _~,04~><.~

~~Bit

TMM333P

32K Bit

r-- ___ ~1v1fIt12332~---

4,096 < 8

TMM2365P

NMOS
I

, TMM2364P
64K Bit

NMOS

8,192<8

I

NMOS

I

TMM2366P

Access

Cycle

Power

Time

Time

Supplies

Max. (ns)

Min. (nsl

(V)

450

450

+5

450

450

350

350

250

350

+5

~-- -~j
200

200

+5

I Power Dissipation
Max. (mW)

I Active
I 440

-

525

I

Source

24

i2316E

24

TMS4732

550

83

24

i2332

220

83

28

i2364

~
550

138

28

(12364)

138

24

MK36000

-

128K Bit * . TMM23128P

16,384 < 8

NMOS

200

200

+5

I

440

110

28

TMM23256P

32.768 < 8

NMOS

150

230

+5

I

220

55

28

256K Bit

Alternate

Pins

Standby

6, CMOS Mask Programmable ROM

!
i

I

Capacity

Organization

Process

.
*

256K Bit *

Access
Time

:

Cycle
Time

I Min, (ns)
I

450

540
450

TC5335P

~O
.
450
450

TC5364P

250

350

250

250

250

250

350

450

! TC5334P
~--

4,096 x 8

8,192 < 8

CMOS

CMOS

TC5366P

Note

I

: Max. (ns)
;
450

TC5332P
[TC5333P

32K Bit

64K Bit

Device Number

TC53256P

32,768 < 8

CMOS

I
I

5

Max. (mW)

(V)

+5

540

Package Material P: Plastic C: Ceramic D: Cerdip F: Plastic Flat
*Preliminary: These are tartet specifications and are subject to change without notice.

Power Dissipation

Power

Supplies

I
I
I

Active

Standby

39

0.11

39

0.11

Pins

TMM2332
24

28
+5
+5

Alternate
Source

83

0.11

I
I

(TMM2332)
TM~~
(TMM333)

, TMM2364

28

TMM2365

24

TMM2366

28

(TMM23256)

TOSHIBA DYNAMIC RAM

S

TMM416P-2

TMM416P-3

(150 ns)

DYNAMIC RAM

TMM4164P-3

TMM4164P-2

H

(120 ns)

TMM41256C-12

TMM4164AP-15
(150 ns)

H

(250 ns)

TMM4164P-4

(150 ns)

(120 ns)

TMM4164AP-12

(200 ns)

TMM416P-4

(200 ns)

H

TMM4164AP-20
1200 ns)

TMM41256C-15

0">

(120 ns)

(150 ns)

*: PRELIMINARY

-m
2:

J:a

TOSHIBA STATIC RAM (NMOS STATIC RAM, CMOS STATIC RAM)

190 nsl

(90 ns)

!

I

I

-l

*: PRELIMINARY

...

o(II

::I:

=

TOSHIBA EPROM

~

TMM2764D-2

TMM2764D

TMM2764DI-2

TMM2764DI

(200 ns)

(250 ns)

TMM27128D-20

TMM27128D-25

:c

r:-

(250 ns)
(200 ns)
DI version: Operating Temperature = -40 ~ 85°C

TOSHIBA MASK ROM (NMOS MASK ROM, CMOS MASK ROM)

00

CMOS

TC5332P. TC5333P
TC5334P. TC5335P

I-----.--li 32 K BIT

*.-.-----,

(450 ns)

TC5364P
TC5365P
TC5366P
(250 ns)

*r,-------------,
TC53256P
lCl50 nsl

*: PRELIMINARY

MEMORY SELECTION GUIDE 1.

Note; *: Preliminary

BOO
TC5047AP-2

700

TC5501 P

TC5514P-l

600

TC5047AP-l
500

TC5501P

.:0

TMM314AP
TC5514P

--- -

TC5332P
TC5333P
TC5334P
TC5335P
TMM333P

TMM334P

400

UJ

:;;

>=

1<0
,

Ul
Ul

UJ
U

TMM2332P

• TC53256P

300

u

«

TMM314AP-3
TC5514AP-3
TC5504AP-3
TMM2764D
TMM2364P

TC5516AP
TC5517AP

TMM416P-4

'lf

TC5364P

TMM27128D-25

*TC5365P
'lfTC5366P

ji

TMM4164P-4
TMM27640-2

"

200
TMM314AP-l
TC5514AP-2
TC5513AP-20

TMM2114AP-12
TMM2114AP-15

TMM2016P-2
TMM416P-3
TC5516AP-2

TCC5517AP-2
*TC5517BP-20
*TC551BBP-20

TMM2365P

TMM2366P
TMM4164AP-20
TMM4164P-2/3
TMM4164AP-12/15

*TMM2015AP-12
TMM2016P
TMM2016AP-12 *TMM2015AP-15
TMM2016AP-15 TMM416P-2

*TC5564P-15

i

TMM2712BD-20
*TMM2312BP

I!

:.1
TMM23256P

*TMM41256C-12
*TMM41256C-15

TC5565P-12/15

aen

100
TMM315D
TMM315D-1

TMM2016P-1
*TMM2015AP-l0
TMM2016AP-10 *TMM2015AP-90
TMM2016AP-9Q TMM2018D-55

*TC5564P-10

:z:

TMM201BD-45

lK Bit

4K Bit

16K Bit

32K Bit

64K Bit

128K Bit

256K Bit

-I:

i:z:

MEMORY SELECTION GUIDE (2)

-

Memory Capacity
Memory

Type
1 K Bit

4K Bit

Dynamic RAM

TMM2114AP

Nch Static RAM

TMM315D

RAM

TC5047AP
CMOS Static RAM

32K Bit

TC5501P

TC5514P
TC5514AP
TC5513AP

128K Bit

TMM2016P
TMM2016AP
*TMM2015AP
TMM2018D
TC5517AP/AF
TC5516AP/AF
*TC5564P
TC5565P

*TC5517BP/BF
*TC5518BP/BF

TMM2764D

TMM27128D

TMM2764DI

TMM334P

TMM333P
TMM2332P

ROM

TMM2364P
TMM2365P

*TMM23128P

TMM23256P

TMM2366P

TC5332P
CMOS MASK ROM

TC5333P
TC5334P
TC5335P

*TC5364P
*TC5365P

*TC53256P

*TC5366P

I
*PRELIMINARY

256K Bit

*TMM41256C

TMM4164AP

EPROM

Nch MASK ROM

64K Bit

TMM4164P

TMM416P

TMM314AP

.....
<:>

16K Bit

=

MEMORY SELECTION GUIDE (3)
Bit
----~~

1

~~~~_

Word

I

~

4

8

I

+

~i
256

TC5501P

I----

---1

TMM314AP TMM2114AP
1,024

TC5047AP

TC5514P

TC5514AP

TC5513AP

I

TMM2016P

TMM2016AP

I

*TMM2015AP

TMM2018D

!

TC5516AP/AF

TC5517AP/AF

I
I

*TC5517BP/BF

*TC5518BP/BF

I

2,048

TMM334P

--1----------:

.....
.....

1----------4,096

I

i

TMM315D

-r-_

TC5504AP

I

8,192

m n

-~-----

1

.

I

!

I

!

L-~-~~--+-~16,384

---JI

I

I

•

-----------j
r

I
I

I

t-=~---~

I

II
I

- - - - -

TMM2332P

TMM333P

TC5332P

TC5333P

TC5334P

TC5335P

*TC5564P

TC5565P

*TC5364P

TMM2364P

*TC5365P

TMM2365P

*TC5365P

TMM2366P

TMM2764D

_-"1_ __

I

TMM27128D
*TMM23128P
TMM23256P

32,768

*TC53256P

a
In

65,536

262,144
*PRELIMINARY

TMM4164P
TMM4164AP
*TMM41256C

-:..:z:
I II

TOSHIBA

MROM (TMM23250)

1) I~
~
IWo
I~
~~ ~E~PR~O~M~(T_M_M_2~7_12~8~)__~~>~~-~_~~~
__+-_<{~"__~_~__=-__~-+--+---r--r~

~

MROM (TMM23128)

I<:

~

li£ .(

<{

I~

16'6'

~C_R_A_M_(_TC_5_5_64_/_65_)____~_~~_~~~ ~~~_.~i__+-_<{_"___I~__~I___I~_:__~-+__+-__~~~
£~ £~

MROM (TMM2365)

~!~

~

MROM (TMM2364)

en
w
:;;

EPROM (TMM2764)
CMOS MROM (TC5333)

(,)

w

Cl

w

Q)

I<:

CMOS MROM (TC5332)

N

M

a::

MROM (TMM2332)

::>
f::>

CRAM (TC5517)

~

I~

I~

Cl

CRAM (TC5516/18)

~

1£

16'

u.

z

«

SRAM (TMM2016/15)

fZ

w

MROM (TMM334)

a::
a::
2

~ [:

I

f-

::>

o

~

Q.

>a::

o

::!E
w
::!E

---+--+--4--~--~

i

·---:Ie-.--------.·.
i

.:, .:. .:, ~ ~~ -2r~.r ~ ~

MROM (TMM334)
.;
.;(
.,'£ .; .,'£
r--.----------~------.~~~~~--~~
SRAM (TMM2016/15)

w
Cl

CRAM (TC5516/18)

3F
w

CRAM (TC5517)

.£ .?

~ ~ ~ ~
0

r5

a 13

f-

>CIl

«
CIl
:t:

en

MROM (TMM2332)

a;
~
N

M

~

CMOS MROM (TC5332)
CMOS MROM (TC5333)
EPROM (TMM2764)

~

<1i

cj

MROM (TMM2364)

z

MROM (TMM2365)

~

~

CRAM (TC5564/65)

z

cj

z
~

~~ ~M_R_O_M~(_TM
__
M_23_1_2_8)__~__~z~+-~__-+__+--4__~__~-+__+--+__+-__~~~
~ ~

~~ iii

EPROM (TMM27128)

~

I MROM (TMM23256)
-

12 -

TOSHIBA
CROSS REFERENCE

1.

16 K Bit Dynamic RAM
Access Tim

------------

150 ns

Toshiba

TMM416P-2

F16K-2
MB8116H
~716A-2
2117-2

Fairchild
Fujitsu
Hitachi
Intel
Intersil
Mitsubishi
Mostek
Motorola
National Semi.
NEe
TI

2.

M5K4116-2
MK4116-2
MCM4116C-2
NM5290-2
j.! PD416C/D-3
TMS4116-15

250 ns
TMM416P-4

F16K-3
MBB116E
f--- HM4716A-3
2117-3
IM7116-3
M5K4116-3
MK4116-3
-MCM4116C-3
-iiM5290-3
j.!PD416C/D-2
TMS4116-20

F16K4
MB8116N
HM4716A-4
2117-4
IM7116-4
M5K4116-4
MK4116-4
MCM4116C-4

~-

~-

~_.

j.!PD416C/D-1
TMS4116-25

64K Bit Dynamic RAM.

Toshiba
Fujitsu
Hitachi
Intel
Mitsubishi
Motorola
NEe
OKI
TI

3.

200ns
TMM416P-3

120ns

150 ns

200 ns

TMM4164P-2

TMM4164P-3

TMM4164P-4

MB8264-15
HM4864-2
2164-15
M5K4164N-15
MCM6665-15
j.!PD4164-3
MSM3764-15
TMS4164-15

MSM3764-12

MB8264-20
HM4864-3
2164-20
M5K4164N-20
MCM6665-20
j.!PD4164-2
MSM3764-20
TMS4164-20

4K Bit Static RAM
1,024 x 4

Access Time
Toshiba
AND
AMI
Fujitsu
Hitachi
Intel
Intersil
Mitsubishi
Motorola
National
NEe
SYNERTEK
TI

4,096 x 1

200ns

300 ns

450ns

55 ns

70ns

TMM314AP·1/APL-1

TMM314AP·3/APL-3

TMM314AP/APL

TMM315D-1

TMM315D

Am9114EPC
S2114-2
MB8114EL
HM472114AP-2
2114-2/L2
IM7114-2/L2
M5L2114LP, S-2
MCM2114-20
MM2114-21-2L
j.!PD2114LC/D-3

Am9114CPC
S2114-3
MB8114NL
HM472114AP-3
2114-3/L3

TMS4045-20

M5L2114LP, S-3
MCM2114-30
MM2114-3/-3 L
j.!PD2114LC/D-1

Am9114BPC
MB8147H
HM6147-3
2147-3

HM472114AP-4
2114/L
IM7114L
M5L2114LP,S
MCM2114-45
MM2114/-L
j.!PD2114LC/D

MCM2147-55
MM2147-3
j.!PD2147D-3

TMS4045-45~

TMS2147-5

- 13 -

S2147
MB8147E
HM6147
2147

MCM2147-70
MM2147
j.!PD2147D-2
SY2147
TMS2147-7

TOSHIBA
4. 1K/4K Bit CMOS RAM
4 K Bit

1 K Bit

Toshiba

256x4

1,024 x 4

1,024 x4

4,096 x 1

TC5501P

TC5047AP

TC5514P
TC5514AP/TC5513AP

TC5504P
TC5504AP

MB8414
HM6514
HM4334

MB8404
HM6504
HM4315

IM6514
M58981S-45
!t PD444
MSM5114
MWS5114

IM6504

Fujitsu

Harris
Hitachi
Intel
Intersil
Mitsubishi
NEC
Oki
RCA

HM6501
HM435101
i5101 L
M5L5101P-1
!tPD5101

!t PD445

MSM5104

5. 16 K Bit NMOS/CMOS S1atic RAM
16 K Bit
CMOS

NMOS
Toshiba
Fujitsu
Hitachi
Mitsubishi
NEC
OKI

TMM2016P
TMM2016AP

MB8128
(HM6116l
M58725
!t PD4016
MSM2128

TC5516AP

TC5517AP/BP

TC5518BP

MB8417

TM8416
(HM6116)

MB8418
(HM6117)

!t PD447
MSM5127

!t PD446
MSM5128

!t PD449
MSM5129

6. ROM (EPROM & MROM)
MROM

EPROM
64 K Bit
Toshiba

TMM2764D

Fujitsu
Hitachi
Intel
Mitsubishi
Mostak
Motorola
NEC

MB2764
HN482764
i2764

Oki
TI

MSM2764AS

64 K Bit

32 K Bit
TMM333P
TC5334P
TC5335P

TMM2332P
TC5332P
TC5333P

MB8332
HM46332P

TMM2364P
TMM2365P

MB8333
i2332
M58735

M58333
MK32000

TMM2366P

MB8364
HN48364
i2364
MK37000

M58334
MK36000

!t PD2332

!t PD2364

TMS4732

TM54754

- 14 -

Dynamic Random Access Memories

-

15 -

TOSHIBA MOS MEMORY PRODUCTS
TMM416P-2, TMM416P-3,
TMM416P-4

16384 WORD x 1 BIT DYNAMIC RAM
NCHANNEL SILICON GATE MaS

DESCRIPTION
The TMM416P is a 16,384 words by 1 bit MOS
random access memory circuit fabricated with
TOSHIBA's double poly N-channel silicon gate process for high performance and high functional density.
The TMM416P uses a single transistor dynamic
storage cell and dynamic control circuitry to achieve

high speed and low power dissipation. Multiplexed
address inputs permit the TMM416P to be packaged
in a standard 16 pin plastic 01 P. This package size
provides high system bit densities and is compatible
with widely available automatic testing and insertion
equipment.

FEATURES
• 16,384 words by 1 bit organization
• Fast access time and cycle time
DEVICE

tRAC

tRC

TMM416P-2
TMM416P-3
TMM416P-4

150 ns
200 ns
250 ns

320 ns
375 ns
410 ns

• Industry standard 16 Pin plastiC DIP
• Standard ± 10% power supply (+12V, ± 5V)
• Lower power: 462mW operating (max.)
20mW standby (max.)

PIN CONNECTIONS

• Output unlatched at cycle end allows two-dimensional chip select
• Common 1/0 capability using "Early Write" or:eration
• Read-Modify-Write, RAS-only refresh, and PageMode capability
• All inputs and output TTL compatible
• 128 refresh cycles I 2 msec
• Compatible with MK4116

BLOCK DIAGRAM

(TOP VLEW)
WRITEo---------------------~~

r;;;";:;~r-------O

A,
A,
A'~
A,
A,
A,
A,

PIN NAMES
AO-A6

Address Inputs

CAS

Column Address Strobe

D,N

Data In

DOUT

Data Out

RAS

Row Address Strobe

WAITE

Read/Write Input

Vee

Power (-5V)

Vce
VDD

Power (+5V)

vss

Ground

Vooo-MEMORY ARFIAY
(128 II 64)

A,

Power (+12V)

17 -

D,"

TOSHIBA
ABSOLUTE MAXIMUM RATINGS

i-

RATING

RECOMMENDED DC OPERATING CONDITIONS

(Ta

I

VALUE

= 0 ~ 70°C)

PARAMETER

--·---__l_~

VCC
VSS

VSS
VIH

",--_ _ _
Input High Voltage, RAS, CAS, WR ITE
Input High Voltage, except RAS, CAS ,WR ITE

VIL

Input Low Voltage, all inputs

VIHC

----~-

--

0

13.2

1

5.0

0

V

1

5.5

V

1

0 i-v-'-

2~

3

1-

3,4

3

~

I

2.4'

i

•

....':I..~3--!

7.0
7.0

3

V

--i---=10:l...-=-~-0-.8

..- -

NOTES jl

-1

---+_-4.5--=5-:o~i-~51-v-l- 31

----'~

-----

12.0

4.5

Supply Voltage

_+-~AX_~.
UNITS I

_.TYP.

~~

Voo

I

NOTES

(Note 21

-----

-SYMBOL!

UNITS

I

V--t-~I

DC ELECTRICAL CHARACTERISTICS

-r

(V oo = 12.0V ± 10%, VCC = 5.0V ± 10%, Vss = OV, Vss = -5.0V ± 10%, Ta = O°C ~ 70°CI (Note 21
SYMBOL

,------

--

1001

'---c-_ .ICCl
_c'--

- -ISSl
- _...

,

OPERATING CURRENT

-

Average power supply operating curren

(RAS, CAS cycling: tRC = minimum valuel
----

STANDBY CURRENT

ICC2

Power supply standby current

ISS2

(RAS = VIHC, DOUT = High Impedan eel

ICC3

L_I!3..SL
\
1004
I
ICC4
PS4

__

--1~-MIN~'
-- -- -

--- -

1002

~~

:

PARAMETER

------

----

---

-

-- -------

---

-

REFRESH CURRENT

200

-

15

-

,

(RAS=VIL,CAScycling: tpc =mini mumvaluel

27

-'0

~lf1lum~__~_____ 1

Average power supply current, page m ode operation

I

I

'

mA

- 200=--t---;;-A

___
-10

+

200

1

10

-

(Iou T = -5mAI

Il A

\

"1

-

18 -

__

I

~

I

--l'----

--Il-A

___ _
. - . __I

(lOUT = 4.2mAI

~__

,

I

'

I

___

F3~~~

----T -10-----~ -+-,

(DOUT is disabled, OV <;; VOUT <;; +5.5VI
OUTPUT LEVE'~'-----

5

.

---';-;;--1---1

~ 1= ~7 -l-:- mA=1- ~--:

INPUT LEAKAGE CURRENT

~O_L_---'L....0_u_t_p_ut "L" level voltage

-I

Il A

------. - - - - - - - mA
I
I
~1011o____r IlA
I
--

0

Average power supply current, refresh mode.

Output "H" level voltage
Ir-----r-O~U=T~P~U=T-LEVELS-VOH

NOTESl.S
____
5 ___1

.ur=--+-_100-~L-_ /1A~___ J

Input leakage current, any input (Vss=-5V
OV <;; VIN <;; +7.oV, all other pins not under test = OVI
OUTPUT LEAKAGE CURRENT
10 ILl

UNITS

6

--=-=1
--

(RAS cycling, CAS = VIHC : tRC = mi
-PAGE-M'OD-ECURRENf---'-

M-Ax'-

3~~

2.4

~,4

_V
V

_J

ji4

1

TOSHIBA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(VDD = 12.0V± 10%; VCC = 5.0V± 10%, VSS = OV, VB B = -5.0V ± 10%, Ta = oDe -70°C)

(NOTES2,7,8,1O)

NOTES

9

9

15
-~--

--

ns

ns

tcp
tR EF

mode cycle only)

60

80

100

ns

ms
2
2
2
Refresh pe_r_io_d~~ ____ ---cc-~~~+--=-+~~~-+----ccc-+-__~-+---c-c-+--~~-+~~~-+~-=~-i
WRITE command set-up time
-20
'CAS to WR ITE delay
-~~+-co60-

-20

-20

ns

tCWD

80

90

ns

17

tRwD

RAS to WRITE delay

145

175

ns

17

twcs

110

r--

-

19 -

17

TOSHIBA
TIMING WAVE ...un'....
•

READ CYCLE
VIHC

tRC

-:------,l1\I-_____t:.!A~R:!__~_~_1

VILtCSH

ADD'RESSES

tCAC

DOUT

~~: -------------OPEN ---------<1

VALID DATA

~----'I

~Don'tCarB

• WRITE CYCLE (EARLY WRITE)
tRAS

FOOl

VIHCVIL-

tAR

tCSH

CAS

VIHC
VIL

ADDRESSES

WRiTE

VIHC

°OUT

VOL

VOH-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

OPEN

- 20 -

m

Don't Care

TOSHIBA
•

READ-WRITE/READ-MODIFY-WRITE CYCLE

RAS

tAR

v'HCV,L -

tASH

~--------------1------+--------tCSH--------------~

tCAS--------------~ J---~----~-CAS

V'HCV'L-

ADDRESSES

WRITE

V'HCV'L-

DOUT

VOHVOL_

D,N

~

Don'tCare

• "RAS-ONLY" REFRESH CYCLE

ADDRESSES

DOUT

VOH-

VOL

OPEN - - - - - - - - - - - - - - - -______________________

-------------------------------

~
Note: CAS = V,HC. WRITE

= Don'teare

- 21 -

Don'teare

TOSHIBA
•

PAGE MODE READ CYCLE

ADDRESSES

DOUT

WRITE

~Don'tCare

•

PAGE MODE WRITE CYCLE

tAR
RAS

VIHC -

V,L

teAs

CAS

V'HC-

V,L

ADDRESSES

V,H
V,L

WRITE

V,HC
V,L

D,N

V,H
V,L

-

f?J

- 22 -

Don't Care

TOSHIBA
CAPACITANCE
(VDD = 12.0V ± 10%, Vee = 5.0V ± 10%, Vss = OV, VBB = -5.0V± 10%, f = 1MHz, Ta = O°C - 70°C)
SYMBOL

PARAMETER

Ci l

Input Capacitance (Ao·A.). DIN

Ci,

Input Capacitance RAS, CAS, WRITE

Co

Output Capacitance (DOUT)

TYP.

MAX.

UNIT

4
8
5

5

pF

10

pF

7

pF

POWER DERATING CHARACTERISTICS

. I . - - j - . t-+-

;.I(MUo)

f-+-I-

r--

60t--t- -

\

lSI-

(--411-3)

Cvcle Ra.e (MHd ~ 10JltRC (no)

,

I
II

o

,

.I

"00

Fig. 3

I< t;-7"}"'-~

.0v~~',J'...."
,

I-~ +,0//1'.
f,~~

J~

~"t'.(~'.-1""1
i

1
I

,.

,.

"

I

1

J.e1 ,/
,{

1

1
I ,.,

CycOllFlnt1MHzl_l0l /'FtC

..

•.,
Cvcle fI.t\O (M+iz) m 10'/tPC
Fig. 4 'PC".I 004

(n.)

Flg.2 'Re".IDOI

NOTES

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
2. T a
is specified here for operation at freq~encies to
tAC ~tRC (min.). Operation at higher cycle rates With reduced
ambient temperatures and higher power dissipation is permissible,
however. provided AC operating parameters are met. See Fig. 1
for derating curve.

3.
4.

5.
6.

7.

8.
9.

10.

'flC ".1003

CvcleTime 'PC (n.)

All voltages are referenced to VSS.
Output voltage will swing from Vss to V CC when activated with
no current loading. For purposes of maintaining data in standby
mode, VCC may be reduced to Vss without affecting refresh
operations or data retention. However, the VOH (min.) specification Is not guaranteed in this mode.
IOO~' 1003 and 1004 depend on cycle rate. See figures 2. 3 and
4 for 100 limits at other cycle rates.
ICC1 and ICC4 depend upon output loading. During readout of
high level data VCC Is connected through a low Impedance to data
out. At all other times ICC consists of leakage currents only.
After the application of supply voltages or after axtanded parlods
of bias (greater than tREF: 2ms) without clocks. the davice must
perform about eight initialization cycles prior to normal operation.
AC measurements assume tT = 5ns.
The spe~ifiC8tions for tAC (min.). tAMW (min.) and tAWC (min.)
are used only to indicate cy<;le !ime at which proper operation
ove~the full temperature range (0 C:e;;;Ta :e;;;70oC) is assured.
VIHC (min.) or VIH (min.) and VIL (max.) are reference lavelsfor

11.

12.
13.
14.

15.

16.

17.

measuring timing of input signals. Also. transition times are measured between VIHC or VIH and VIL.
Assumes that tACO ~tRCD (max.). If tACO is greater than the
maximum recommended value shown in this table, tRAC will increase by the amount that tACO exceeds the value shown.
Assumes that tRCo ~tRCD (max.)
Measured with a load equivalent to 2 TTL loads and 100pF.
tOFF (max.) defines the time at which the output achieves the
open circuit condition and is not referenced to output voltage
lavels.
Operation within the tRCo (max.) limit insures that tAAC (max.)
can be met. tRCO (max.) is specified as a reference point only: if
tRCo is greater than the specified tRCO (max.) limit, then access
time is controlled exclusively by tCAC'
These parameters are referenced to CAS leading edge in early write
cycles and to WRITE leading edge in delayed write or reedmodify-write cycles.
twCS. tCWD and tAWD are not restrictive operating parameters.
They are included In the data sheet as elactrical characteristics
only.
If twcs ~ twcs (min.). the cycle is an aarly write cycle and the
data out pin will remain open circuit (high impedance) throughout
the entire cycle:
If tCWD ~ tCWD (min.) and tAWD ~tRWD (min.1. the cycle is a
read-write cycle and the data out will contain data read from the
selected cell: If neither of the above sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.

23 .-_.-

-

---

----~---

---

--~ ~-~----------

-

TOSHIBA
APPLICATION INFORMATION
ADDRESSING
The 14 address bits required to decode 1 of the
16.384 cell locations within the TMM416P are
multiplexed onto the 7 address inputs and latched
into the on-chip address latches by externally applying two negative going TTL-level clocks.
The first clock. the Row Address Strobe (RAS).
latches the 7 row address bits into tbe chip. The
second clock. the Column Address Strobe (CAS).
subsequently latches the 7 column address bits into
the chip. Each of these signals. RAS and CAS. triggers a sequence of events which are controlled by different delayed internal clocks.
The two clock chains are linked together logically
in such a way that the address multiplexing operation
is done outside of the critical path timing sequence
for read data access. The later events in the CAS
clock sequence are inhibited until the occurence of a
delayed signal. derived from the RAS clock chain.
This "gated CAS" feature allows the CAS clock to be
externally activated as soon as the Row Address Hold
Time speCification (tR AH) has been satisfied and the
address inputs have been changed from Row address
to Column address information.
DATA INPUT/OUTPUT
Data to be written into a selected cell is latched
into an on-chip register by a combination of WR ITE
and CAS while RAS is active. The later of the signals
(WRITE or CAS) to make its negative transition is the
strobe for the Data In (DIN) register. This permits
several options in the write cycle timing. In a write
cycle. if the WR ITE input is brought low (active)
prior to CAS. the 01 N is strobed by CAS and the setup and hold times are referenced to CAS. If the
input data is not available at CAS time or if it is
desired that the cycle be a read-write cycle the
WRITE signal wi II be delayed unti I after CAS has
made its negative transition. In this "delayed write
cycle" the data input set-up and hold times are
referenced to the negative edge of WR ITE rather than
CAS. (To illustrate this feature. 01 N is referenced to
WR ITE in the timing diagrams depicting the readwrite and page-mode write cycles while the "early
write" cycle diagram shows DIN referenced to CAS).

Data is retrieved from the memory in a read cycle
by maintaining WRITE in the inactive or high state
throughout the portion of the memory cycle in which
CAS is active (low). Data read from the selected cell
will be available at the output within the specified
access time.
DATA OUTPUT CONTROL
The normal condition of the Data Output (DO UT)
of the TMM416P is the high impedance (opencircuit) state. That is to say. anytime CAS is at a high
level. the DOUT pin will be floating. The only time
the output will turn on and contain either a logic 0 or
logic 1 is at access time during a read cycle. Do UT
will remain valid from access time until CAS is taken
back to the inactive (high level) condition.
If the memory cycle in progress is a read. readmodify write. or a delayed write cycle. then the data
output will go from the high impedance state to the
active condition. and at access time will contain the
data read from the selected cell. This output data is
the same polarity (not inverted) as the input data.
Once having gone active. the output will remain valid
until CAS is taken to the precharge (logic 1) state.
whether or not RAS goes into precharge.
If the cycle in progress is an "early-write" cycle
(WRITE active before CAS goes active) .. then the
output pin will maintain the high impedance state
throughout the entire cycle. Note that with this type
of output configuration. the user is given full control
of the DOUT pin simply by controlling the plaoament
of WRITE command during a write cycle. and the
pulse width of the Column Address Strobe during
read operations. Note also that even though data is
not latched at the output. data can remain valid from
access time until the beginning of a subsequent cycle
without paying any penalty in overall memory cycle
time (stretching the cycle).

PAGE MODE OPERATION
The "Page-Mode" feature of the TMM416P allows for successive memory operations at mu Itiple column locations of the same row address with increased
speed without an increase in power. This is done by

- 24 -

TOSHIBA
rent waveforms in Fig. 5) In system applications
requiring lower power dissipation, the operating
frequency (cycle rate) of the TMM416P can be reduced and the (guaranteed maximum) average power
dissipation of the device will be lowered in accordance with the ID D 1 (max.) spec limit curve illustrated
in Fig. 2.
It is possible to operate certain versions of the
TMM416P family (-2 and 3 speed selections for
example) at frequencies higher than specified, provided all AC operati~g parameters are met. Operation at
shorter cycle times « tRe min.) results in higher
power dissipation and, therefore, a reduction in
ambient temperature is required. Refer to Fig. 1 for
derating curve.

strobing the row address into the chip and maintaining the RAS signal at a logic 0 throughout all successive memory cycles in which the row address is common. This "page-mode" of operation will not dissipate the power associated with the negative going
edge of RAS. Also, the time required for strobing in
a new row address is eliminated, thereby decreasing
the access and cycle times.

REFRESH
Refresh of the dynamic cell matrix is accomplished
by performing a memory cycle at each of the 128
row addresses within each 2 millisecond time interval.
Although any normal memory cycle will perform the
refresh operation, th is function is most easily accomplished with "RAS-only" cycles, RAS only refresh
results in a substantial reduction in operating power.
This reduction in power is reflected in the IDD3
specification.

POWER UP
The TMM416P requires no particular power supply sequencing so long as the Absolute Maximum
Rating Conditions are observed. However, in order to
insure compliance with the Absolute Maximum Rillings, TOSHIBA recommends sequencing of POWei
supplies such that VBB is applied first and rernov,,,1
last. VBB should never be more positive than V,;,;
when power is applied to VD D.

POWER CONSIDERATIONS
Most of the circuitry used in the TMM416P is
dynamic and most of the power drawn is the result of
an address strobe edge. (refer to the TMM416P cur-

TYPICAL CURRENT WAVEFORMS
LONG RAIl/CAS CYCLE

RAS/CAS CYCLE

,

,-

"RASONLYCYCLE

r- . . r-r--

1\

Voo
V"
TS

+JIi

H- I-

100

-

..

(mAl

~ -\

0-·

1~

,

I"

(rnA)

,
,

~

V

\j

-

-)'

~

tEl \
II

11

~IJ

/\

f-

A
11'1
\I-'~

111

-v

"

j

ft

A

I

JI\

.L

I

III
I rv V

-

I

.A-

I'--

-

25°C

Lill

I~

1/

,
,

,

A~
IIr,

V-

I"
(rnA)

I·····

lJ.2V
- -4.5V
=

1\

/

ltv 1/

A I'
~ ~I-'

25 -

/1\

IV \1--

If'I'l

/1\
l!'-'

~

TOSHIBA
TYPICAL CHARACTERISTICS

Normalized AccllllS Time tRAC
III V DO S UPPV
I V gtage
I

Normalized A<:"eIlTlma tRAe

Normalized Ac.::8n Time tRAe

vs Ves Sl,Ipply Voltage

VI Vee Supply Voltage

,.4r--,---"'r-'T-F-,-----,

4
TJ -50"<:

TJ "50"<=

.

,

"

...... r--...

.......

0

t0,O';-3--'---;--L--!---L---!~--L--:!

O
Vas IV)

Voo IV)

Normalized AC>Ce$S Time

1001 (Allersglt)

VIT' Junction Temperatura

v,;

.

,

V

f;u "
<

~

;

0

/

/

Vee (V)

1001 (Average)

VI TJ Junction Temperature

VOO Supply Voltage

1/

~

VSS- --4.5V

Voo

TJ ",soge

Ves "'4.5V

tRC·- 3 'Sna

tAC -375",

13.2V

-,

60

Veo IV)

TJ ("cl

1002 (Standby)

1002 (Stendbyl

',4r--,'-·':..V'-'0"0'-'".":;.""-"-'-v.;,.",,.'"::,_ _ _ _-,

VII VOO Supply Voltllglt

Vss

VBS = --4.5V
Tj

1003 (RAS Only)

VI Tj JunctIon Temperatura

",sooe

~

Ves - -4.5V

--4.5V

Tj

VOO '" 13.2V

-sooe

tRC=375nl

°"

Ii

--

-1--1--'

,0
Voo

(V)

"

'0
Voo

- 26 -

(V)

TOSHIBA

1003 (R"AS Only)
vs Tj Junction Temperatur&

'004 (Page Mode)

1004 (Page Mod.. )

vi Tj Junction Temperatur.

vs VOO Supply Voltal/8

Ves ~ -4.SV

¥as

Vao ~ 13.2V

Tj _ 50°C

tRC

~

375 ns

= -4.5V

.....----t----- - ---f----

¥as -

-4.5V

VOO

13.2V

=

tpc = 225 n.

tpc - 225 ns

-

-1---1-Vao (V)

V,HC,V,LC Input Le"els

V,H. V,L Input Levels

VIHC. VILe Input Levels

v< VOP Supply Voltage

us Yao Supply VoltaGo

V5

¥as

Supply Voltage

I
I

t-

1--n=1=~.

Vss

¥as - -S.5V for V,HC
Ves = -4.5V for V, LC

Tj = 50°C

~

-S.5V for V,H

Voo = 13.2V for VrfJr

Ves - -4.5V for VIL

Vap ~ lO.8V for V'Le

Tj _ 50°C

Tj = 50°C

O~8--L-~--~~~~~7-~~
Vao

(V)

V'H' V'L Input L .. " .. ls
vs

Vas

Supply Voltage

Vss

(V)

V'HC_ VII.. C Input L .. vels

V,H. VII. Input Levels

vs Tj Junction Temperature

vs Tj Junction Temperature

J

I

I

;;
i

;;

I

-

Voo = 13.2V for V IH
Voo

~

13.2V. Vee

~

-S.5V for VIHC

VOO ~ 10.SV for VIL
Tj ~ SOoC

VOO ~ 10.8V. Ves ~ -4.5V for VILC

Vee (V)

- 27

-

Voo ~ 13.2V, Vee ~ -5.SV for VIH
VOO = 10.8V. Vee ~ -4.SV forVIL

TOSHIBA
OUTLINE DRAWING
16

15

14

13

12

11

10

Unit in rnm

9

!I!~~:~;}
12345678

C~;;~

19.9 MAX.
SO

..

X.--+;~------------------'I

:!'

o

ui

1.4 ±O.15
2.54 ±O.25

SO

L~~~

0.2 MAX.

I

7.62 _ B.BO

I
Note: Each lead pitch is 2.54mm. All leads are located within O.26mm.
of their longitudinal position with respect to No.1 and No. 16 leads,

0.5 ±O.15

Note: Toshiba does not assume any responsibility for use of any circuitry described; no circuit patent IIcellses ara Implied, and Toshiba reserves
the right, at any time without notice, to change said circuitry,
©Mar.,1980 Toshiba Corporation

- 28 -

TOSHIBA MOS MEMORY PRODUCTS
65,536 WORD X , BIT DYNAMIC RAM

TMM4164~~

N-CHANNEL SILICON GATE MOS

TMM4164P-4

TMM4164~3

Multiplexed address inputs permit the TMM4164P
to be packaged in a standard 16 pin plastic DIP.
This package size provides high system bit densities
and is compatible with widely available automated
testing and insertion equipment.
System oriented features include single power supply
of 5V ±10% tolerance, direct interfacing capability
with high performance logic families such as Schottky

DESCRIPTION
The TMM4164P is the new generation dynamic
RAM organized 65,536 words by 1 bit, it is successor
to the industry standard TMM416P.
The TMM4164P utilizes TOSHIBA's double poly
N·channel Silicon gate process technology as well as
advanced circuit techniques to provide wide operating
margins, both internally and to the system user.

TTL.

FEATURES
• 65,536 words by 1 bit organization
• Fast access time and cycle time
DEVICE
tRAc
tRC
TMM4164P·2
120 ns
260 ns
TMM4164P·3
150 ns
260 ns
TMM4164P-4
200 ns
330 ns
• Single power supply of 5V± 10% with a bUllt·ln
Vee generator
• Low power; 275mW operating (MAX.)
27.5mW standby (MAX.)

PIN CONNECTION

• Industry standard 16 pin plastic DIP
• Output unlatched at cycle end allows two-dimensional chip selection
• Common I/O capability using "EARLY WRITE"
operati;:m
• Read·Modify-Write, RAS-only refresh and Page
Mode capability
• All inputs and output TTL compatible
• 128 refresh cycles/2ms

(TOP VIEW)
NC

BLOCK DIAGRAM
.----a

Vss
CAS

D,N

WRITE
RAS
.A o
A,

DOUT

A.
A3

A.

AI

As

Vce

A,
A,

A,
A,
A,
A,
A,

PIN NAMES
Ao -A,
CAS

~-

Address Inputs
Column Address Strobe

Data In

A,
A,

NC

No - Connection

DOUT
RAS
WRITE

Data Out
Row Address Strobe
Read/Write Input
Power (+5V)
Ground

Vcc
Vss

- 29
- - - - ---

-~-~-

--

----- ----

---

Vee

TOSHIBA
ABSOLUTE MAXIMUM RATINGS
ITEM

SYMBOL

Input and Output Voltage

RATING

UNITS

NOTES

VIN. VOUT

-1-7

V

1

Power Supply Voltage

Vcc

-1-7

V

1

Operating Temperature

TOPR

·C

1

Storage Temperature

TSTG

-55-150

·C

1

TSOlDER

260 . 10

°C· sec

1

PD

600

mW

1

lOUT

50

mA

1

Soldering Temperature· Time
Power Dissipation
Short Circuit Output Current

0-70

RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 - 70°C)
SYMBOL

PARAMETER

TYP.

MAX.

UNITS

NOTES

5.0

5.5

V

2

2.4

6.5

V

2

-1.0

0.8

V

2

MIN.

Vcc

Supply Voltage

4.5

VIH

Input High Voltage

Vll

I nput Low Voltage

DC ELECTRICAL CHARACTERISTICS (Vee
SYMBOL
ICC I

ICCl

Icc3

Icco

II (ll

= 5V± 10%,. Ta = 0 -

PARAMETER

MAX.

UNITS

NOTES

50

mA

3,4

5

mA

40

mA

3

40

mA

3,4

-10

10

JJ.A

-10

10

JJ.A

MIN.

OPERATING CURRENT
Average Power Supply Operating Current
(RAS, CAS Cycling: tRC =tRC MIN.)
STANDBY CURRENT
Power Supply Standby Current
(RAS = VIH. DOUT = High Impedance)
REFRESH CURRENT
Average Power Supply Current, Refresh Mode
(RAS Cycling. CAS = VIH: tRC = tRC MIN.)
PAGE MODE CURRENT
Average Power Supply Current. Page Mode
(RAS = Vll, CAS Cycling: tpc = tpc MIN.)
INPUT LEAKAGE CURRENT
Input Leakage Current. any Input (OV ~ VIN ~ 6.5V
All Other Pins Not Under Test =OV)

10 (ll

OUTPUT LEAKAGE CURRENT
(DcUT is disabled. OV ~ VO UT ~ +5.5V)

VOH

OUTPUT LEVEL
Output "H" Level Voltage (lOUT

= -5mA)

VOL

OUTPUT LEVEL
Output "L" Level Voltage (lOUT

=4.2mA)

70·C)
TYP.

V

2.4
0.4

- 30 -

V

TOSHIBA

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vee = 5V ± 10%, Ta = 0 - 70°C) (Notes 5, 6, 7)
SYMBOL

PARAMETER

tRC

Random read or write cycle time

tRWC

Read-write cycle time

tRMW

Read-modify-write cycle time

tpc

Page mode cycle ti me

TMM4164P-2
MIN.

MAX.

I 260

TMM4164P-3
MIN.

MAX.

TMM4164P-4
MIN.

MAX.

UNITS

260

330

ns

260

270

335

ns

265

310

390

ns

140

170

225

ns

NOTES

tRAC

Access time from RAS

120

150

200

ns

8,10

tCAC

Access time from CAS

80

100

135

ns

9,10

tOFF

OutpJt buffer turn-off delay

0

35

0

40

a

50

ns

11

tT

Transition time (rise and fall)

3

35

3

35

3

50

ns

6

tRP

RAS precharge time

tRAS

RAS pulse width

tRSH
tCSH

RAS hold ti me

80

100

135

CAS hold ti me

120

150

200

tCAS

CAS pulse width

80

10,000

100

10,000

135

10,000

ns

tRCO

RAS to CAS delay time

25

40

25

50

30

65

ns

tCRP

CAS to RAS precharge time

90
120

100
10,000

150

ns

120
10,000

200

10,000

ns
ns
ns

a
a

a
a

a
a

ns

15

15

20

ns

0

a

0

ns

12 ___

tASR

Row Address set-up time

tRAH

Row Address hold time

tASC

Column Address set-up time

tCAH

Column Address hold time

40

45

55

ns

tAR

Colurnn Address hold time
referenced to RAS

80

95

120

ns

tRCS

Read command set-up time

ns

Read command hold time

a
a

0

tRCH

a
a

a

ns

tWCH

Write command hold time

40

45

55

ns

tWCR

Write command hold time
referenced to ~

80

95

120

ns

twp

Write command pulse width

40

45

55

ns

tRWL

Write command to RAS lead time

40

45

ns

tcwL

Write command to CAS lead time

40

45

55
55

tos

Data-in set-up time

0

0

0

ns

13

tOH

Data-in hold time

40

45

55

ns

13

tOHR

Data-in hold time referenced to RAS

80

95

120

ns

ICp

CAS precharge time (for pagemode cycle only)

50

tREF

Refresh period

twcs

Write command set-up time

-10

-10

-10

ns

tCWD

CAS to WR ITE delay

50

60

80

ns

14

tRWO

RAS to WR I TE delay

90

110

145

ns

14

60
2

- 31 -

ns

--

ns

ns

80
2

--

2

ms

14

TOSHIBA
TIMING WAVEFORMS
• READ CYCLE
tRAS

AAS
tCSH
tACO

CAS

I tRSH

----------~!:======~~==:-~-----t~~--------~~r---~---------------

VIH ___
VIL

___

ADDRESSES

DOUT

VOH - - -

OPEN

VOL ___------------------------~~-----------------<~I-V-A-L-'D--D-A-T-A-J

~

Don't Care

• WRITE CYCLE (EARLY WRITE)
'AC

AAS
tCSH

tAP

ADDRESSES

WAITE

VDH---~________________________________________
VOL---

-

32 -

DPEN---------------

rza

Don't Care

TOSHIBA
•

READ-WRITE/READ-MODIFY-WRITE CYCLE

AAS

CAS

VIHADDRESSES

WRITE

DOUT

O'N

V'L-

VIH-

VIL-

VOH -

VIH -

VIL -

~

Don'teare

• "RAS·ONLY" REFRESH CYCLE
tAC

RAs
tASA
ADDRESSES

VIH-

VIL--~~~~~~~~

ROW ADDRESS

VOH-

°OUT

VOL

--------------------------------~OPEN-------------------------------------

Note: CAS = VIH, WAITE = Don't Care, A7 = Don't Care

- 33 -

E22l

Don't Care

TOSHIBA
•

PAGE MODE READ CYCLE

cAs

ADDRESSES

VIH ~
VIL-

DOUT

~ Don'teare

•

PAGE MODE WRITE CYCLE

RAS

tRAS
V1H_
V1L-

CAS

ADDRESSES

V,H
V,L

V,H
V,L

WAITE

V,H
V,L

D'N

V,H
v,L

~ Don't Care

-

34 -

TOSHIBA
CAPACITANCE
(Vee= 5V ± 10%,

f = 1MHz, Ta = 0 - 70°C)

SYMBOL
CI I
CI2
Co

PARAMETER

MIN,

Input Capacitance lAo - A" DIN I
Input Capacitance IRAS, CAS, WRITEI
Output Capacitance I DOUT I

TYP,
4
8

5

MAX,
5
10
7

UNITS
pF
pF
pF

NOTES:
1.
2.

3.

Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

All voltages are referenced to Vss,
Icc I , Icc>, Icc. depend on cycle rate.

4.

Icc 1, ICC4 depend on output loading. Specified values are obtained with the output open.

5.

An initial pause of 200,us is required after power-up followed by any 8 8AS cycles before proper device operation is achieved.

6.

AC measurements assume tT == 5ns.

7.

V1H (min.) and V1L (max.) are reference levels for measuring timing of input signals. Also, transition times are measured between V1H and V 1L .

8.

Assumes that tRCD ~ tRCD (max.). If tRCD is greater than the maximum recommended value shown in this table, tRAC will
increase by the amount that tRCO exceeds the value shown.

9,
10.

Assumes that tRCD ~ tRCD Imax.l.
Measured with a load equivalent to 2 TTL loads and 100pF.

11.

tOFF (max.) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage
levels.

12.

Operation within the tRCO (max.) limit insures that tRAC (max.) can be met. tRCO (max.) is specified a reference point only:

13.

These parameters are referenced to CAS leading edge in early write cycles and to WRITE leading edge in read-write or readmodify-write cycles.

14.

twcs, tCWD and tRWO are not restrictive operating parameters. They are included in the data sheet as electrical characteristics

If tRco is greater than the specified tRCO (max.) limit, then access time is controlled exclusively by tCAC

only. If twcs ~ twcs Imin.I, the cycle is an early write cycle and the data out pin will remain open circuit Ihigh impedancel
throughout the entire cycle:
If tCWD ~ tCWD (min.) and tRWD ~ tRWD (min.), the cycle is read-write cycle or read-modify-cycle and the data out will
contain data read from the selected cell: If neither of the above sets of conditions is satisfied, the condition of the data out
(at access time) is indeterminate.

APPLICATION INFORMATION
ADDRESSING

delayed internal clocks.
The two clock chains are linked together logically
in such a way that the address multiplexing operation
is done outside of the critical path timing sequence
for read data access. The later events in the CAS
clock sequence are inhibited untfl the occurence of a
delayed signal derived from the RAS clock chain.
This "gated CAS" feature allows the CAS clock to be
externally activated as soon as the Row Address Hold
Time specification (tRAH) has been satisfied and the
address inputs have been changed from Row address
to Column address information.

The 16 address bits required to decode 1 of the
65,536 cell locations within the TMM4164P are
multiplexed onto the 8 address inputs and latched
into the on-chip address latches by externally applying two negative going TTL-level clocks.
The first clock, the Row Address Strobe (RAS),
latches the 8 row address bits into the chip. The second clock, the Column Address Strobe (CAS)' subsequently latches the 8 column address bits into the
chip, Each of these signals, RAS, and CAS, triggers a
sequence of events which are controlled by different

-

35

TOSHIBA
cuit) state. That is to say, anytime CAS is at a high
level, the DouT pin will be floating. The only time
the output will turn on and contain either a logic 0 or
logic 1 is at access time during a read cycle. DouT
will remain valid from access time until CAS is taken
back to the inactive (high level) condition.

DATA INPUT/OUTPUT
Data to be written into a selected cell is latched
into an on-chip register by a combination of WR ITE
and CAS while RAS is active. The later of the signals
(WR ITE or CAS) to make its negative transition is the
strobe for the Data In (DIN) register. This permits
several options in the write cycle timing. In a write
cycle, if the WR ITE input is brought low (active)
prior to CAS, the i:1N is strobed by CAS and the setup and hold times are referenced to CAS. If the input
data is not available at CAS time or if it is desired
that the cycle be a read-write cycle, the WR ITE signal
will be delayed until after CAS has made its negative
transition. In this "delayed write cycle" the data
input set-up and hold times are referenced to the
negative edge of WR ITE rather than CAS. (To illustrate this feature, DIN is referenced to WRITE in the
timing diagrams depicting the read-write and page
mode write cycles while the "early write" cycle diagram shows DIN referenced to CAS).
Data is retrieved from the memory in a read cycle
by maintaining WR ITE in the inactive or high state
throughout the portion of the memory cycle in which
CAS is active (low). Data read from the selected cell
will be available at the output within the specified
access time.

PAGE MODE
The "Page-Mode" feature of the TMM4164P allows for successive memory operations at multiple
column locations of the same row address with
increased speed without an increase in power. This is
done by strobing the row address into the chip and
maintaining the RAS signal aLa logic 0 throughout all
successive memory cycles in which the row address is
common. This "Page-Mode" of operation will not
dissipate the power associated with the negative going
edge of RAS. Also, the time required for strobing in
a new row address is eliminated, thereby decreasing
the access and cycle times.
REFRESH
Refresh of the dynamic cell matrix is accomplished
by performing a memory cycle at each of the 128 row
address (AD - A,) within each 2 millisecond time
interval. Although any normal memory cycle will
perform the refresh operation, this function is most
easily accomplished with "RAS-only" cycles, RAS
only refresh results in a substantial reduction in
operating power. This reduction in power is reflected
in the Icc 3 specification.

DATA OUTPUT CONTROL
The normal condition of the Data Output (C\oUT)
of the TMM4164P is the high impedance (open cirOUTLINE DRAWINGS

16

15

14

13

12

11

10

9

Unit in mm

l[t:~:: ::-)
12345678

199 MAX

7.62±O.25

8'

+0.1

0.25-0.05

-

1.4±O.15

2.54±O.25

0.2 MAX. 1--,7.:0.60=2,--.:;.8",.8.:;.°--1

O.5±O.15

Note:

Each lead pitch is 2.54 mm. All leads are located within 0.25 mm of their true longitudinef position with respect to No.1 and No. 16 leads.
All dimensions are in millimeters.
Note: Toshiba does not assume any responsibilitY for US,", of any circuitry described; no circuit patent licenses are implied, and Toshiba reserves

the right, at any time without notice, to change said circuitry.
©Apr .. 1982 Toshiba Corporation

-

36 -

TOSHIBA MOS MEMORY PRODUCTS
TMM4 I 64AP- I 2
TMM4 I 64AP- I 5
TMM4164AP-20

65,536 WORD X 1 BIT DYNAMIC RAM
N-CHANNEl SILICON GATE MOS

* This is advance information and specifications are subject
to change without notice.

Multiplexed address inputs permit the TMM4164AP
to be packaged in a standard 16 pin plastic DIP. This
package size provides high system bit densities and
is compatible with widely available automated testing
and insertion equipment.
System oriented features include single power
supply of 5V ±10% tolerance, direct interfacing capability with high performance logic families such as
Schottky TTL.

DESCRIPTION
The TMM4164AP is the high speed, low power
dynamic RAM organized 65,536 words by 1 bit, it
is successor to the industry standard TMM4164P.
The TMM4164AP utilizes TOSHIBA's double poly
N-channel Silicon gate process technology as well as
advanced circuit techniques to provide wide operating
margins, both internally and to the system user.

FEATURES
• 65,536 words by 1 bit organization
• Fast access time and cycle time
DEVICE
TMM4164AP·12
TMM4164AP-15
TMM4164AP-20

tRAC
120 ns
150 ns
200 ns .

tCAC
60 ns
75 ns
100 ns

• Industry standard 16 pin plastic DIP
• Output unlatched at cycle end allows two-dimensional chip selection
• Common I/O capability using ;'EARLYWRITE"
operation
• Read·Modify-Write, RAS-only refresh and Page
Mode capability
• All inputs and output TTL compatible
• 128 refresh cycles/2ms

tRC
220 ns
260 ns
330 ns
.---;~

• SIngle power supply of 5V ± 10% with a bullt'ln
Vss generator
• Low power; 275mW operating (MAX.)
22mW standby (MAX.)

PIN CONNECTION

(TOP VIEW)

BLOCK DIAGRAM

NC

Vss

DIN

CAS

WRITE
RAS
Ao
A,

----0

DOUT

A,

Al

A3
A4
As

Vce

A,
A,

A,

PIN NAMES
I

A,

Ao - A,

A,

Address Inputs

!-1_C=A~S~_--r__C_o_lu_m_n~AddressS=-t'--ro.:...b_e_ _ _ _ __

L.0N
'NC
~

A,
I

--"

Data I,."n"----_ _ _ _ _ _ _ _ _ _-iI
-+II-C""NC-o - Connection
I
I

I

A,
A,
A,

Data Out

f-~~RA=S~-+--.Rco=-w,,-,A-,dc.:::drc.:ce=ss--=S:..:ctr-o-,-b-,-e--. _. ____ _
WRITE
,
Read/Write Input
~Vcc--'-~P-ow-e--r (+5V)

: Vss

Ground

-

37 -

Vee

TOSHIBA
ABSOLUTE MAXIMUM RATINGS
ITEM

SVMBOL

RATING

UNITS

NOTES

V IN , VOUT

-1-7

V

1

Power Supply Voltage

Vcc

-1-7

V

1

Operating Temperature

TOPR

1

Input and Output Voltage

Storage Temperature
Soldering Temperature . Time

Power Dissipation

Short Circu it Output Current

TSTG

-55-150

°c
°c

TSOLOER
Po

260 . 10

°C . sec

1

600

mW

1

lOUT

50

mA

1

0-70

1

RECOMMENDED DC OPERATING CONDITIONS (Ta = 0 - 70°C)

DC ELECTRICAL CHARACTERISTICS (Vee = 5V± 10% .. Ta = 0 - 70°C)
rl-cMcB,OL;II-::ERATING

-r

CURR::~AMETER--------- -MIN-~:TVP

I

MA_X_ :- UNITS

Average Power Supply Operating Current
:
50
1--_ _ _I--''--R_A_S--',_C_A.. _S__Cyciing: tRC ~ tRC MIN.I
I
I
STANDBV CURRENT
I
!
Icc,
I Power Supply Stahdby Current
I
4
'-..-.
I (RAs ~ VIH, DOUT ~ High Imped_a_n_ce_I__________+--_ _ _+--____l--

I

,RAS Cycling, CAS

Current, Refresh Mode
VIH: tRC ~ tRC MIN.I

i--r----r-.---

40

-----------1

II III
I

r-_IO_I_L_I
VOH
VOL

OUTPUT LEAKAGE CURRENT

I

34

I
mA

I
I

I

i

40

PAGE MODE CURRENT
Average Power2!Pply Current, Page Mode
(RAS ~ VIL,CASCycllng: tpc ~tpc MIN.I
INPUT LEAKAGE CURRENT
Input Leakage Current, any Input 'OV~VIN ~6.5V,
All Other Pins Not Under Test ~ OVI

NOTEs_I

I

i

~~::g~Sp~;~~~~~~~

!

mA

mA

I

mA

I

pA

I

3

I

I

i

I'

1I
:
:

3,4

---i-----i-.-----i

!

I

-10

10

II

!
i

I

-j1-'"D"OorU"T'iiorS,d,is"ab"l",ed_,_0_V_~_V..:O:cU:..T,--~_+_5_.5_V_I_ _ _ _ _--+__-_1_0_-+-~_+0_~I~_P_A_--I_ _ _

I
1

OUTPUT LEVEL
1--11
Output "H" Level Voltage (lOUT ~ -5mAI
2.4
I
V
OUTPUT LEVEL
--~~--------r---~---~I----r---I----~I
Output "L" Level Voltage 'lOUT

~4.2mAI

--'.i__O_.4__

_____ -'-_ _ _--"_ _ _

- 38 -

V
_ _.L..._ _ _

-1.I'_ _

J

TOSHIBA
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Vee = 5V ± 10%, Ta = 0 ~ 70°C) (Notes 5, 6, 7)
SYMBOL

PARAMETER

TMM4164AP-12

TMM4164AP-15 TMM4164AP-20

MIN.

MIN.

MAX.

MAX.

MIN.

MAX.

UNITS

NOTES

tRC

Random Read or Write Cycle Time

220

260

330

ns

tRWC

Read-Write Cycle Time

240

285

350

ns

tRMW

Read-Modify-Write Cycle Time

260

310

390

ns

tpc

Page Mode Cycle Ti me

120

145

190

tRAC

Access Time from RAS

120

150

200

ns

8,10

tCAC

Access Time from CAS

60

75

100

ns

9,10

ns

tOFF

Output Buffer Turn-Off Delay

0

35

0

40

0

50

ns

11

tT

Transition Time IRise and Fall)

3

35

3

35

3

50

ns

6

tRP

R AS Precharge Ti me

tRAS

RAS Pulse Width

120

tRSH

RAS Hold Time

60

75

100

ns

tCSH

CAS Hold Time

120

150

200

ns

90

100
10,000

150

120
10,000

200

ns
10,000

ns

tCAS

CAS Pulse Width

60

10,000

75

19,000

100

10,000

ns

tRCO

RAS to CAS Delay Time

25

60

25

75

30

100

ns

tCRP

CAS to RAS Precharge Time

tASR

Row Address Set-Up Time

tRAH

Row Address Hold Time

lAse

Column Address Set-Up Time

tCAH

0

0

0

ns

0

0

0

ns

15

15

20

ns

0

0

0

ns

Column Address Hold Time

35

45

55

ns

12

tAR

Column Address Hold Time
Referenced to RAS

95

120

155

ns

tRCS

Read Command Set-Up Time

0

0

0

ns

tRCH

Read Command Hold Time

0

0

0

ns

tWCH

Write Command Hold Time

35

45

55

ns

tWCR

Write Command Hold Time
Referenced to RAS

95

120

155

ns

twp

Write Command Pulse Width

35

45

55

ns

tRWL

Write Command to RAS Lead Time

35

45

55

ns

tCWL

Write Command to CAS Lead Time

35

45

55

ns

tos

Data-In Set-Up Time

0

0

0

ns

13

tOH

Data-In Hold Time

35

45

55

ns

13

tOHR

Data-In Hold Time Referenced to RAS

95

120

155

ns

tcp

CAS Precharge Time Ifor Page
Mode Cycle Only)

50

tREF

Refresh Period

twcs

Write Command Set-Up Time

tcwo
tRWO

60
2

80
2

ns
2

ms

-10

-10

-10

ns

14

CAS to WRITE Delay

40

50

60

ns

14

RAS to WRITE Delay

100

125

160

ns

14

39 -

TOSHIBA
TIMING WAVEFORMS
• READ CYCLE
tRAS

RAS
tCSH
I tRSH

ADDRESSES

WAITE

V1H-

VIH -

V IL

DOUT

tCRP

~LLLL~'-.LLLL.Lr'"-'CL./

VOH -

OPEN

VOL _------------------------~~-----------------<~I-V-A-L-'D--D-A-T-A-/I

tz2J Don't Care
• WRITE CYCLE (EARLY WRITE)
tRC

RAS

VrHVIL-

CAS

VtH_

VIL_

VrH_
ADDRESSES

VrL-

WAITE

VrH_
VIL-

D,N

V'H_
Vll-

DOUT

VOH_

VOL

------------------------------------------OPEN---------------

- 40 -

TOSHIBA
•

READ-WRITE/READ-MODIFY-WRITE CYCLE
tAwcltRMW

AAS

VtL-

CAS

VIHADDRESSES

WAITE

DOUT

D,N

VtL-

VIHV1L-

VOH-

VtH V1L -

~ Don't Care

•

"RAS-ONLY" REFRESH CYCLE
tAC

VIH-

ROW ADDRESS

ADDRESSES
V I L -'-'-.LI--U-.l...L.L.i-c.L.W-l.IJ

DOUT

VOH-

VOL ----------------------------------'DPEN----------------------------------Note: CAS

~

V 1H , WRITE

~

41 -

Don't Care, A7

~

Don't Care

E:Zl

Don't Care

TOSHIBA

•

PAGE MODE READ CYCLE
tRAS

CAS

ADDRESSES

V'HV,L -

DOUT

WAITE

~ Don'tCare

• PAGE MODE WRITE CYCLE
tAR
RAS

ADDRESSES

WRITE

fZ3

- 42 -

Don't Care

TOSHIBA

CAPACITANCE