1983_Western_Digital_Components_Catalog 1983 Western Digital Components Catalog
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1983
Components
Handbook
WESTERN DIGITAl.
CORPORA
TID
N
Western Di'gital
1983 Components
Handbook
ii
Making The Leading Edge
Work For You"
This handbook is designed for you, the design engineer. It's in·
tended to be a useful tool, to enable you to make a preliminary
evaluation of our products and, later, with samples in hand, to
design our products into your own systems.
The data in these pages have been reviewed by our Marketing,
Engineering, Manufacturing and Quality groups. Now we would like
you to review the information we've provided and tell us how we
can improve it. Please feel free to suggest any changes, additions,
or clarifications that occur to you. And don't hesitate to call to our
attention any sins of omission or commission we may have made.
We're eager to help upgrade the quality of information our industry
provides to its customers. So, please, help us. Direct your com·
ments to:
Director of Corporation Communications
WESTERN DIGITAL CORPORATION
2445 McCabe Way
Irvine, CA 92714
(714) 557-3550
iii
iv
Western Digital: Update '83
Western Digital is on the move, growing and expanding to meet
your needs. This year's Components Handbook includes a number
of significant new products. Our leadership in file management is
reinforced by the many innovations this year in both floppy disk
and Winchester disk controllers, and the introduction of the first
LSI controller for SMD drives. We've expanded our large data
communications product line with the addition of a new, ultra fast
SDLC controller. And, there are a number of important introductions in our Network, Security and Special Products categories.
That's just half the story, though. This handbook is for our component products only (including board-level solutions based on our
LSI disk controllers). Separate handbooks and literature are available for our systems products. We urge you to use order forms at
the front of this book to order your copies of the following:
Industrial Automation Handbook: Introduces The WEDGET~ our
new 100 module family of Eurocord microcomputer systems based
on 8085A18088l8086 processors and designed for command and
control applications in an automated factory environment.
SuperMicro1600 Systems Brochure: Our 16-bit desktop computers,
designed to improve programmer efficiency by functioning as low
cost, high performance Pascal and Ada development systems, are
explained in detail.
v
vi
Table of Contents
Functional Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Numerical Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quality/Reliability to Leading Edge Technology ................................................
Announcing Burn-In Program AvailabilitylWarranties ............................................
Hi-Rei "K" Testing Program ................................................................
File Management Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CRT Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Communications ....................................................................
Security Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microcontrollers ........................... '..............................................
Special Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory Products .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Arrays ............................................................................
Network Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information ......................................................................
Package Diagrams .......................................................................
Pin Compatibility Chart ....................................................................
High Reliability Relpak Plastic Package Specification ............................................
Terms and Conditions .....................................................................
vii
ix
xi
1
7
9
11
261
305
537
561
611
629
679
691
7~5
727
731
733
735
viii
Functional Index
FILE MANAGEMENT PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Part Number
11
Page
Hard Disk Controllers
WD1000
WD1001
WD1002
WD1100
WD1010
Winchester Disk Controller ...........................................
Winchester Disk Controller ...........................................
Winchester Disk Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Winchester Controller Chips .........................................
Winchester Disk Controller ..........................................
"
"
..
"
"
13
21
31
33
77
Hard Disk Support
WD1011
WD1012
WD1014
WD1050
Winchester Data Separator Device ...... "...............................
Write Precompensation Device ....................................... "
Buffer Manager/ Error Correction Device ................................ "
SMD Controller/Formatter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
83
85
87
93
Floppy Disk Controllers
FD176X-02
FD1771-0'1
FD1771-0'1
FD1781/FD1781-01
FD179X-02
FD179X
WD279X-02
Floppy Disk Formatter/Controller Family .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Floppy Disk Formatter/Controller .... , ................................ "
Application Notes ................................ , ..................
Floppy Disk Formatter/Controller .......................... , .......... "
Floppy Disk Formatter/Controller Family .................................
Application Notes ...................................................
Floppy Disk Formatter/Controller Family .................................
99
123
143
151
173
195
211
Floppy Disk Support
WD1691
DM1883 A/B
WD2143-03
WD9216-00/9216-01
Floppy Support Logic (F.S.L.) ...........................................
Direct Memory Access Controller .......................................
Four Phase Clock Generator ...........................................
Floppy Disk Data Separator - FDDS ....................................
233
241
253
257
CRT CONTROLLERS ..................................................................... 261
Part Number
Page
WD8275 .............................................................................. 263
WD8276 .............................................................................. 287
DATA COMMUNICATIONS ................................................................. 305
Part Number
TR1402/TR1602
TR1863/TR1865
TR1402/TR1602/
TR1863/TR1865
WD1983
WD8250
WD2123
BR1941
WD1943/WD1945
PR1472
PT1482
Page
Data Communication Protocol Definitions ................................ 307
Universal Asynchronous Receiver/Transmitter (UARn ....................... 311
Universal Asynchronous Receiver/Transmitter (UARn ....................... 321
I
Application Notes ...................................................
(BOARn Bus Oriented Asynchronous ReceiverlTransmitter ..................
Asynchronous Communications Element .................................
DEUCE Dual Enhanced Universal Communications Element ..................
Dual Baud Rate Clock ................................................
Dual Baud Rate Clock ................................................
(PSAR) Programmable Synchronous & Asynchronous Receiver ...............
(PSAn Programmable Synchronous & Asynchronous Transmitter ............ "
ix
333
345
357
373
389
397
405
419
UC1671
WD1931
WD193X
WD1931/WD1933
WD1993
WD1984
ASTRO ............................................................
Asynchronous/Synchronous Receiver/Transmitter .........................
Synchronous Data Link Controller Family .................................
Compatibility Application Notes ........................................
Arinc 429 Receiver/Transmitter and Multi·Character Receiver/Transmitter .......
Multi·Character Synchronous/ Asynchronous Receiver/Transmitter ............
433
447
467
485
509
525
SECURITY PRODUCTS . ................................................................... 537
Page
Part Number
WD2001/WD2002
WD2001/WD2002
Data Encryption Devices .............................................. 539
Applications Note ................................................... 551
Cipher Feedback Cryptography Technical Note ............................ 559
MICROCONTROLLERS ................................................................... 561
Page
Part Number
WD51
Irrigation Controller ..................................................
WD55
Industrial Timer/Controller .............................................
WD4200IWD4210 and
WD4320/WD4321 Single Chip N·Channel Microcontrollers ..................................
4 Bit Microcomputers ................................................
563
571
585
609
SPECIAL PRODUCTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611
Page
Part Number
WD1801
WD1802
WD2412
Octal Comparator .................................................... 613
Octal Comparator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617
Time of Day Clock ................................................... 621
MEMORY PRODUCTS .................................................................... 629
Page
Part Number
FR1502
WD1510-00,01
WD1511
WD501 0
WD5869
WD74HC200
WD8206
WD8207
First·ln/First·Out Buffer Register ........................................
LIFO/FIFO Buffer Register ............................................
LIFO/FIFO Support Device ............................................
Single/Dual Read Content - Addressable Memory .........................
Dynamic Shift Register ...............................................
256 x 1 CMOS Static RAM .............................................
Error Detection and Correction Unit .....................................
Advanced Dynamic RAM Controller .....................................
631
637
641
645
649
653
657
677
LOGIC ARRAYS ......................................................................... 679
Page
Part Number
WD1820
WD1840
Logic Array Device ........................................ : ... '. . . . . . . 681
Logic Array Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687
NETWORK PRODUCTS ................................................................... 691
Part Number
WD2501/2511
WD2520
WD2840
WDK25001
Page
Packet Network Interface (LAP/LAPB) ....................................
CCITT #7 Data Link Controller ..........................................
Local Network, Token Access Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PACKIT ............................................................
x
693
705
707
719
Numerical Index
Part Number
Page
WD51 ..................................
WD55 ..................................
WD1000 ................................
WD1001 ................................
WD1002 ................................
WD1010 .. " .............................
WD1011 .. ".............................
WD1012 .. ".............................
WD1014 .. " .............................
WD1050 ................................
WD1100 ................................
TR1402/1602 .............................
PR1472 .................................
PT1482 .................................
WD1502 ................................
WD1510 ................................
WD1511 ................................
UC1671 .................................
WD1691 ................................
FD176X ... " . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
FD1771 .................................
FD1781 .................................
FD179X .................................
WD1801 ................................
WD1802 ................................
WD1820 ................................
WD1840 ................................
TR1863/1865 .............................
DM1883 .. " .............................
Part Number
Page
WD1931 ................................
WD193X ................................
BR1941 ................................ ,
WD1943/1945 ............................
WD1983 ................................
WD1984 ................................
WD1993 ................................
WD2001/2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
WD2123 ................................
WD2143 ................................
WD2412 ................................
WD K2500 1 ..............................
WD2501 ................................
WD2511 ................................
WD2520 ................................
WD279X ................................
WD2840 ................................
WD4200/4210 . . . . . . . . . . . . . . . . . . . . . . . . . . ..
WD4320/4321 ............................
WD5010 ................................
WD5869 ................................
WD74HC200 .............................
WD8206 ................................
WD8207 ................................
WD8275 ................................
WD8276 ................................
WD8250 ................................
WD921&o0/921&01 .......................
563
571
13
21
31
77
83
85
87
93
33
311
405
419
631
637
641
433
233
99
123
151
173
613
617
681
687
321
241
447
467
389
397
345
525
509
539
373
253
621
719
693
693
705
211
707
585
585
645
649
653
657
677
263
287
357
257
4 Bit Microcomputers ..................... 609
xi
)!.ii
WESTERN DIGITAL
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Quality/Reliability To Leading Edge Technology
QUALITY PROGRAM DESCRIPTION
The Quality Organization shown in Figure 2 assures
compliance to design control, quality and reliability
specifications, pursuant to corporate policy.
CORPORATE QUALITY POLICY
It is the policy of Western Digital Corporation that
every employee be committed to quality excellence
in producing products/processes which conform to
acceptable requirements. The total quality program is
managed and monitored by the quality assurance
organization. Quality assurance is chartered to
review marketing product requirements, qualify
hardware and software designs, certify manufacturing operations and monitor performance/control
conformance to product specifications.
Primary responsibility for execution for the quality
program rests with functional organizations to
design, produce and market high quality and high
reliability products specified to our customers.
Purchased FAB and assembly operations are
individually qualified and are certified against
standard specifications during vendor qualification and monitored against reliability
criteria.
Defect control within the process assures the
highest levels of built-in reliability.
• Quality audits and gates are located throughout
the manufacturing process in order to assure a
stable process and thus, a quality product to our
customers. Figure 1 illustrates the manufacturing/
screening/inspection flow diagram and identifies
the steps as they relate to the production of LSI
devices.
• Testing assures quality margins through 100%
testing by manufacturing and, in addition, all
products must pass a specified AQL sample test
performed by QA at maximum operating temperature as follows:
Outgoing Quality Levels
SUBGROUPS
LSI QUALITY ASSURANCE PROGRAM
HIGHLIGHTS
• LSI manufacturing assurance provisions are
derived in part from MIL-M-38510 and MIL-STD883B as applied to high grade commercial components.
• All process raw materials used in the Mask/Wafer
fabrication and assembly operations are
monitored by Material Assurance.
• Material Assurance maintains a thorough control
of incoming material and has developed unique
"use/stress tests" (look ahead sample build acceptance) which critical material must pass before
acceptance.
• The Product Assurance Department continuously
monitors the internal and external manufacturing
flow (shown in Figure 1) and issues process
control reports displaying detailed data and trends
for the associated areas.
Document control is an integral part of Product
Assurance. All specifications are issued and
controlled by this activity.
The Western Digital Malaysian assembly
operation uses specifications and quality
control provisions controlled by Document
Control. Indicators of Malaysia quality are
reviewed weekly.
INSPECTION LEVEL
Subgroup 1 - Final 100% Electrical
0.5 AQL*
Audit @ Max °C
Subgroup 2 - Visual (Marking, Lead
Integrity, Package, Verify customer
1.0 AQL
shipper)
1.0 AQL
Subgroup 3 - Shipping Visual Audit
"The double sampling techniques used allow considerably
better AQL's in most all cases.
• LSI devices are 100% tested on industry standard
test systems like that shown below. Quality
outgoing testing (auditing) is done on the Fairchild
Sentry Series 20 where possible to allow better
correlation with customers.
Optional
Offshore
Assembly
Starting Material
Receiving Inspection
Final Assembly
Inspection
Design and Mask
Fabrication
Outgoing
Inspection
100% Stabilization Bake
Plastic 125°C, 24 hrs.
Ceramic 150°C, 24 hrs.
100% Temperature Cycle
Plastic - 55°C to + 125°C
10 cycles
Ceramic - 65°C to + 150°C
10 cycles
Gross Leak (.65 AQL)
Ceramic
Wafer In-Process Audits!
Defects Control
(See Table 1)
Fine Leak Test
(.65% AQL)
Solder Dip Leads
Lead Inspection
Ceramic
Cut and Form Inspection
Base Seal Inspection
Assembly
Incoming
Inspection
100% Electrical Test
Wire Bond Inspection
Final Test Audit - 0.5 AQL
Precap Inspection
~
~-5Ptlonal-
.
Reliability Monitors
(Table 3 & 4)
- - --;:.:
I
StaticlDynamlc
Burn-In
100% Electrical
Test
I
Burn-In Brand
I
I
I
Shipping Audit
I
I
-----------~
Ship By Customer
Specified Carrier
LEGEND
o
Figure 1
Manufacturing operation
o
o
Quality Assurance Audit
'\J
Quality Assurance Gate
Manufacturing Inspection Gate
LSI PRODUCTION FLOW
2
Reliability Means Lasting Value
• DESIGNING FOR RELIABILITY
The production release procedure for an LSI device is
designed to assure maximum reliability With a
Quality checklist for:
[B'" Test program qualifications
lB'"' Characterization report
lB'"' Field test (Beta Test) report
lB'"' Reliability Ufetest Qualifications
lB'"' Infrared Thermal Analysis
IB" Static Protection
All new devices and major process changes must
pass reliability qualification before incorporation into
production using the criteria defined in Tables 2-4.
The infrared microscope shown on the right assures
optimum burn-in temperatures and margins of safety.
The dynamic burn-in system shown on the right is
one of two custom designed systems which assure
protective device isolation during burn-in.
• MAINTAINING RELIABILITY IN PRODUCTION
Process defects control are defined to continually
measure built-in reli'ability, as measured by the
following criteria:
TABLE 1
PROCESS RELIABILITY CONTROL
Subgroup 1 - Defects Control
a. Oxide Integrity
b. Polysilicon Integrity
Subgroup 2 - Electro-Migration Control
Metal Step Coverage
Subgroup 3 - Defect Density
Subgroup 4 - Passivation/Insulation
Integrity
METHOD
Non-destructive
bubble test
SEM Analysis
CONDITION
Pinhole defect density
5 wafers
Visual
5 wafers
SEM Analysis
5 wafers
M IL-STD-883
Method 2018
Critical layers
Field
Gate
Contact
Metal
Visual of Photo defects
(Defects/in2)
MIL-STD-883 Method
2021
Visual of Pinhole
defect density
'Inspection intervals are defined by the in·line process control data reviewed on a lot·by-Iot basis.
3
SAMPLE*
8 wafers
each layer
Final Silox
5 wafers
Intermediate
5 wafers
o
C
• PROGRAMS TO ASSURE OPTIMUM RELIABILITY
Improved levels of reliability are available under custom reliability programs using static and dynamic burn·in to
further improve reliability. These programs focus on MaS failure mechanisms as follows:
~
::
~
:IJ
~
iii"
~
'<
FAILURE MECHANISMS IN MaS
FAILURE
MECHANISM
Slow Trapping
Contamination
Surface Charge
Polarization
Electromigration
Microcracks
Contacts
Oxide Defects
Electron Injection
EFFECT ON
DEVICE
ESTIMATED
ACTIVATION ENERGY
Wearout
Wearout!
Infant
Wearout
Wearout
Wearout
Random
Wearout!
Infant
Infant!
Random
Wearout
SCREENING
METHOD
1.0eV
1.4eV
Static Burn·ln
Static Burn·ln
0.5-1.0eV
1.0eV
1.0eV
Static Burn·ln
Static Burn·ln
Dynamic Burn·ln
100% Temp. Cycling
Dynamic Burn·ln
0.3eV
Dynamic Burn·ln
at max. voltage
Low Temp. Voltage
Operating Life
-
Temperature Acceleration of Failure
The Arrhenius Plot defines a failure rate propor·
tional to exp( - Ea/kt) where Ea is the activation
energy for the failure mechanism. The figure on
the right indicates that lower activation energy
failures are not effectively accelerated by tem·
perature alone; hense, maximum voltage operation
is selectively applied to optimize the burn·in
process.
10'·
10'
10·
en
a::
10 1
;s
10'
::::>
0
Static Bum-In (125°C - 48 hours or 160 hours)
Provided on a sample basis for process
1.0 eV failure
monitor/control of 0.5 eV mechanisms. 100% static burn·in may be
specified at an additional cost. However, static
burn·in is considered only partially effective for
internal LSI gates at logic "0" levels.
w
a::
::::>
..J
10'
0
10'
«
u.
IW
~
i=
10'
10'
Dynamic Burn-In (Pattern test/125°C - 8 hours to
160 hours)
Accelerated functional dynamic operating life
effectively controls internal MaS gate defects
buried from external pin access. The input pattern
is optionally pseudo-random or fixed pattern
programmable to simulate 1000-3000 hours of field
operation at maximum operating voltage(s).
10'
50
75
100
125 150 175 200
TEMPERATURE (0C)
High-Rei "K" Testing Program
General conformance to MIL·STD-883B method
5004.4, Class B with static Burn·ln (Dynamic Burn·
In may be specified as an option).
4
250
lSI RELIABILITY STANDARDS
TABLE 2
TEST
STANDARD RELIABILITY LEVELS
METHOD
Infant
Mortality
(see note)
Long Term
Failure Rate
CONDITION
FAILURE
Static
Burn-In
125°C - 160 hrs.
<0.5%
Dynamic
Life Test
125°C -
<.05%/1000 hrs.
@ 55°C
60% Confidence
1000 hrs.
"NOTE: Devices failing the infant mortality target remain on burn-in until acceptable failure rates are obtained.
TABLE 3
GROUP A DEVICE RELIABILITY MONITORS
TEST
METHOD
Subgroup 1
a. Internal Visual
b. Thermal Shock
c. Bond Strength
d. Die Shear Strength
.------
1014
1005
-
b. Electrical Parameters
TABLE 4
TEST
1011
1010
-
d. Seal - Fine Leak (ceramic)
e. Electrical Parameters
f. 85/85 Moisture Resistance
(plastic only)
g. Electrical Parameters
---~--------------------
Subgroup 2
a. High Temp. Storage
b. Mechanical Shock
c. Seal - G ross Leak
b. Seal - G ross Leak
c. Seal - Fine Leak
(ceramic)
1014
c-----
1008
2002
-
d. Seal - Fine Leak
(ceramic)
e. Electrical Parameters
-~-----~-
---------_ ....
-
1014
- --
"--~-----"-
-
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
------
..-
15
. - - - - - - - - - ----
Static 160 hr. Burn-In 125°C
plus 125°C Lifetest - 1000 hrs.
Final electrical @ 25°C (with data @
70°C)
-
1014
5
LTPD
Test Condition B or C
Test Condition B or C
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
Electrical at max -C
85% RH/85°C for 1000 hours
PDA = 10%
Final electrical @ 25°C
"-----
15
-------
Test Condition B or C
Test Condition B
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
- -
---
15
Final electrical @ 25°C/max. C
--------------- e-------------- - - -
2004
--
-.--.-~
GROUP B PACKAGE RELIABILITY MONITORS
METHOD
CONDITIONS
Subgroup 1
a. Thermal Shock
b. Temperature Cycling
c. Seal - Gross Leak
Subgroup 3
a. Lead Integrity
--
- - - ----------
----"-". .
Subgroup 3
a. Rotating Steady State Life Test
-------_.
Test Failure Used (cond. B orC)
Test Failures (cond. B)
Test Failures
---------
b. Seal - Fine Leak
-
LTPD
15
1011
2011
2019
Subgroup 2
a. Seal- Gross Leak
!--
CONDITIONS
---.-----------~-------.-
Test Condition B2
(Lead Fatigue)
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
5
15
WESTERN DIGITAL CORPORATION
CHIEF EXECUTIVE
• Systems Quality
• New Product
Qualification
• System Test
Qualification
• Software
Qualification
"Systems DeSign
Control"
• LSI Qualification
• Burn-In/Stress
Requirements
• Reliability Monitor
Data
• Reliability Testing
•
•
•
•
Document Control
Wafer Defects Control
Subsidiary/Offshore QC
Process Qualification
"LSI DeSign Control"
Figure 2
•
•
•
•
•
•
•
•
•
Incoming QC
Vendor Quality
LSI Burn-In
LSI Package Monitors
Precap Visuals (883 optional)
100% Test Audit
Failure Analysis
Package Qualification
Calibration Control
"Manufacturing Assurance"
QUALITY ORGANIZATION
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
6
Prmted In U.S.A
WESTERN DIGITAL
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Announcing Burn-In Program Availability/Warranties
Western Digital now supports customer burn-in
requirements for both static and dynamic burn-in
under the strict control of the QA-Reliability
organization.
This burn-in provides high performance 125°C static
and dynamic burn-in for 8-160 hours to eliminate
infant mortality and improve reliability. This process
is executed using custom modified 32Bit AEHR test
commercial burn-in equipment which provide monitored fixed pattern or pseudorandom burn-in with
power supply and resistor device pin isolation.
LSI dynamic burn-in is verified in all cases by the
design engineer for proper functioning. LSI Chip sets
are also individually burned-in with dynamic equivaIlency to assure high performance bundled reliability.
The warranty on the program will optionally provide
certificate of compliance to standard or custom designed bum·in programs and guarantee <.05%/Khrs
failure rate.
CAUTION
Using outside burn-in methods not certified as acceptable by Western Digital may result in voided warranty, due to mishandling, junction temperature
stress, or electrical damage. Further, since most
burn-in houses do not support testing, catastrophic
system condition can result in substantial damage
before a problem is identified.
One consistent problem experienced with outside
LSI burn-in houses can cause reliability problems;
namely, parallelling totem pole MOS outputs, where
the output states are not predictable, can cause a
single (or a few) device(s) to sink all the current from
the other devices on the burn-in tray - electromigration or current zaps are both possible.
Western Digital burn-in diagrams, dated after 1/1/82,
must be used exactly as shown and will be provided
upon request.
SEE YOUR LOCAL REPRESENTATIVE FOR COSTS
AND ORDERING INFORMATION ON THIS NEW
PROGRAM.
7
InformatIon furnIshed by Western DIgItal CorporatIon IS believed to be accurate and relIable. However, no responSIbilIty IS assumed by Western DIgital
CorporatIon for Its use: nor for any Infflngements of patents or other fights of thIrd partIes whIch may result from ItS use. No lIcense is granted by
implicatIOn or otherWIse under any patent or patent rIghts of Western DIgItal CorporatIon Western DIgItal CorporatIon reserves the fight to change
specifIcatIons at anytIme wIthout notIce
8
Prlnled In USA
WESTERN DIGITAL
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Hi-Rei "K" Testing Program
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rGENERAL DESCRIPTION
Western Digital's Hi-Rei "K" program is designed to
provide high reliability devices for extended temperature environments. Individual enhancements may be
specified to meet a customer's requirements.
FEATURES
GENERAL CONFORMANCE TO MIL-STD-883B,
METHOD 5004.4, CLASS B (SEE COMPARISON ON
FOLLOWING PAGES)
• INCLUDES:
PRECAP VISUALS
SEAL INTEGRITY
POWER CONDITIONING
ENHANCEMENT OPTIONS
INITIATE
LOT
PACKAGE PROBED WAFERS TRAVELER
OC
AUDIT
FINE LEAK
SCRIBE/SAW
GROSS LEAK
BREAK/SORT
CUT/FORM LEADS
INSPECT
PRE BURN·IN
ELECTRICALS
CHIPBOND
BURN-IN
160 HRS @ 125°C
INSPECT
FINAL TEST
WIRE BOND
FINAL TEST
0.5% AOL
INSPECT
CLEAN/BAKE/SEAL
CERTIFICATE
OF
CONFORMANCE
TEMP CYCLE
10 CYCLES
- 65'/ + 150'C
STABAKE
24 HRS 150'C
BRAND
MOVETO
FINISHED
GOODS
PACK
SHIP VIA
CUSTOMER
SPECIFIED
CARRIER
HI-REL "K" PROGRAM FLOW DIAGRAM
9
.
COMPARISON OF MIL·STD·883
AND HI·REL "K" TEST PROGRAM
:l:
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MIL·STD·883B, METHOD 5004.4, CLASS B
r-
3.1.1 Internal Visual
Method 2010.3
Test condition B
m
HI·REL "K" TEST
All Hi·Rel "K" devices receive 100% inspections
prior to lid seal. These inspections together com·
prise criteria comparable to Mil·Std·883, method
2010.3, test condition B.
3.1.2 Stabilization Bake
Method 1008.1
Test condition C
24 hours at 150°C
Same
3.1.3 Temperature Cycling
Method 1010.2, Test condition C
- 65°C to 150°C for 10 cycles, with 10 minutes
dwell and 5 minutes maximum transfer time
Same
3.1.4 Constant Acceleration
Method 2001.2, Test condition E. 30,000 G stress
level
Not Done Unless Specified
3.1.5 Visual Inspection
Visual inspection for catastrophic failures after
screens
Same
3.1.6 Seal Method 1014.2
(a) Helium fine leak - Test condition A1. Bomb
condition 2 hours at 60 psig. Reject limit 5 x 10- 8
torr
(b) Flourocarbon gross leak - Test condition C
3.1.9 Interim (pre·burn·in) Electricals
Per applicable device specification
Same
Same
Preburn·in test at 25°C. Must meet requirements of
device data sheets.
3.1.10 Burn·in Test
Method 1015.2160 hours @ 125°C
Same
3.1.13 Interim (Post burn·in) electricals
Per applicable device specification
Burn·in equipment isolate failures automatically to
assure no harmful interaction.
3.1.15 Final Electrical Test
(a) Static Tests
(1) 25°C
(2) Minimum and Maximum Operating
Temperatures
(b) Dynamic and Switching Tests at 25°C
(c) Functional Tests at 25°C
Same
3.1.17 Qualification or Quality Conformance
Inspection and Test Sample Selection
Not done unless defined using method 5005 as a
guide.
3.1.18 External Visual
Method 2009.2
Same
WESTERN DIGITAL RELIABILITY ENHANCEMENT
OPTIONS
Extended High Temperature Storage
100% Temperature Testing
+ 150°C for 24 hours standard, other time/tempera·
ture storage requirements available as required .
Level ....................... - 40° to + 85°C
. . . . . . . . . . . . . . . . . . . . . . - 55° to + 125°C
Thermal, Shock (Liquid to Liquid)
Level. ............... 0° to + 100°C, 15 cycles
. . . . . . . . . . . . . . . . . . . . . . - 55° to + 125°C
...................... - 65° to + 150°C
Dynamic Bum·ln
Per note previously supplied .
10
Printed In U.S.A
File Management Products
Part Number
Page
Hard Disk Controllers
WD1000
WD1001
WD1002
WD1100
WD1010
Winchester Disk Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Winchester Disk Controller ........................................... ,
Winchester Disk Controller ........................................... ,
Winchester Controller Chips . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Winchester Disk Controller ........................................... ,
13
21
31
33
77
Hard Disk Support
WD1011
WD1012
WD1014
WD1050
Winchester Data Separator Device ......................................
Write Precompensation Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Buffer Manager/Error Correction Device ................................. ,
SMD Controller/Formatter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
83
85
87
93
Floppy Disk Controllers
FD176X-02
FD1771-01
FD1771-0'1
FD1781/FD1781-01
FD179X-02
FD179X
WD279X-02
Floppy Disk Formatter/Controller Family ................................ ,
Floppy Disk Formatter/Controller ...................................... ,
Application Notes ...................................................
Floppy Disk Formatter/Controller ...................................... ,
Floppy Disk Formatter/Controller Family ................................ ,
Application Notes ...................................................
Floppy Disk Formatter/Controller Family .................................
123
143
151
173
195
211
Floppy Disk Support
WD1691
DM1883A/B
WD2143-03
WD9216-00/9216-01
Floppy Support Logic (F.S.L.) ...........................................
Direct Memory Access Controller .......................................
Four Phase Clock Generator ...........................................
Floppy Disk Data Separator - FDDS ....................................
233
241
253
257
11
99
12
WESTERN DIGITAL
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WD1000 Winchester Disk Controller
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- FEATURES
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•
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•
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•
•
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•
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C;ENERAL DESCRIPTION
BUILT-IN DATA SEPARATOR
BUILT-IN WRITE PRECOMPENSATION LOGIC
DATA RATES UP TO 5 MBITS/SEC
CONTROL FOR UP TO 4 DRIVES
CONTROL FOR UP TO 8 R/W HEADS
1024 CYLINDER ADDRESSING RANGE
256 SECTOR ADDRESSING RANGE
CRC GENERATIONIVERIFICATION
AUTOMATIC FORMATIING
128, 256, OR 512 BYTES PER SECTOR (ROM
SELECTABLE)
UNLIMITED SECTOR INTERLEAVE CAPABILITY
OVERLAP SEEK CAPABILITY
IMPLIED SEEK ON ALL COMMANDS
AUTOMATIC RETRIES ON ALL ERRORS
AUTOMATIC RESTORE AND RE-SEEK ON SEEK
!:RROR
8-BIT HOST INTERFACE
O°C to 50°C OPERATION
ORGANIZATION
The WD1000 has seven on board connectors. These connectors consist of a power connector, host interface connector, drive control connector, and four high speed data
cable connectors.
The WD 1000 is a stand-alone, general purpose Winchester
controller board designed to interface up to four Winchester disk drives to a host processor. The drive signals
are based upon the floppy look-alike interface available on
the Shugart Associates' SA 1000, the Seagate Technology
8T506, the Quantum Q2000, and other compatible drives.
All necessary buffers and receivers/drivers are included on
the board to aUow direct connection to the drive. Either a 34
pin (5%" drive) or 50 pin (8" drive) connector is provided, as
well as four 20 pin data connectors.
The drive control cable is daisy-chained to each of the four
drives. Although there is space for two drive control
connectors, only one would normally be used for any
particular configuration.
The drive data connectors carry differential signals and are
radially connected. Up to four drives can be accommodated by the WD1000.
Communications to and from the host computer are made
via a separate computer access port. This port consists
mainly of an 8 bit bi-directional bus and appropriate control
signals. All data to be written to or read from the disk, status
information, and macro cammands are transferred via this 8
bit bus. An on board sector buffer allows data transfers to
the host computer independent of the actual data transfer
rate of the drive.
The host interface connector provides interface signals
that are compatible with most microprocessors and minicomputers.
WD1100
For those who want to design their own board around the
WD1100 chip set, Western Digital can provide schematics,
artwork, and programming information. Western Digital
also has a complete staff of Applications Engineers to
provide additional support. For further information please
contact your local representative, or our main plant listed
on page 8.
The WD 1000 is based upon a proprietary chip set, the
VVD 1100, specifically designed for Winchester Control.
.
13
;iii • : ... : - ;','
~" _~,
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WD1000 BLOCK DIAGRAM
HOST INTERFACING
SPECIFICATIONS
Encoding method:
Cylinders per Head:
Sectors per Track:
Heads:
Drive Selects:
Step rate:
Data Transfer Rate:
Write Precomp Time:
Sectoring:
Host Interface:
Drive Capability:
Drive Cable Length:
Host Cable Length:
Power Requirements:
Ambient Temperature
Operating:
Relative Humidity:
MTBF:
MTTR:
Length:
Width:
Height:
Mounting Centers:
MFM
Up to 1024
Up to 256 (512 byte sec)
8
4
10 uS to 7.5 mS
(0.5 mS increments)
4.34 Mbits/sec or
5.000 Mbits/sec
10 nanoseconds
Soft
8 Bit bi-directional bus
10 ilLS" Loads
10 ft. (3 M) max.
3 ft. (1 M) max.
+ 5V ± 5%, 3.0A Max. (2.5A
typ.) - 8 to -18V, 50 rnA *
The WD1 000 is designed to easily interface to most micro
computers and mini-computers. All interfacing is done
through the Host Interface Connector (J5). The interface is
very similar to Western Digital's family of Floppy Disk
Controllers. The only exception is the inclusion of the WAIT
line.
Walts
The WAIT control line goes true whenever' either of the
following are true:
• The WD1000 is accessing data internally to send to the
host during a read operation
• The WD1000 has not accepted the data from the host
during a write operation.
The definition of the WAIT line is very similar to the WAIT
signal found on many popular processors. WAIT is also
similar to the REPLY signal on Western Digital and other
processors.
O°C to 50°C (32 F to 122 F)
20% to 80%
10,oooPOH
30 minutes
9.9 in. (24.9 cm)
6.8 in. (17.1 cm)
0.75 in. (1.9 cm)
6.375 x 9.375 in. (16 x 23.6 cm)
WAIT will not necessarily make a transition for each access
to the WD 1000. When the WD 1000 can return the requested
data within 100 nS, there will be no transition of the WAIT
line. This should be interpreted as an instant REPLY on
Western Digital Processors.
* Optional - V Supply Available.
14
If the WD1000 cannot return the requested data within 100
nS, it will assert its WAIT line. The period of the WAIT signal
will vary from 750 nS to 6 uS with 1.25 uS being about
average. The, period of the WAIT only approaches 6 uS
during a read or write which happens immediately after a
command is written to the command register. This means
that longer waits may be encountered during the first read
or write to any WD1000 register if that first read or write
happens within approximately 6 uS of a command being
issued.
The user can modify the timing of the wait signal by select·
ing a jumper. The WD1000 is shipped with a jumper (or
trace) between E4 and E5. This enables waits as soon as
the CS signal is asserted. This timing is a requirement for
some processors and compatible with most. If the host
system requires the WAIT signal to be asserted only when
RE or WE are asserted in conjunction with CS, the trace at
E4 and E5 should be cut and a jumper should be installed
between E4 and E3.
The Host Interface connector (J5) consists of an eight bit
bi·directional bus, three bit address bus, and seven control
lines. All commands, status, and data are transferred over
this bus. See Table 1:
During the time that WAIT is asserted, the host system
must hold all of its strobe and address lines stable. On
write operations, the DAL lines must also be held stable.
HOST INTERFACE CONNECTOR
TABLE 1
SIGNAL GROUND
SIGNAL PIN
SIGNAL NAME
DESCRIPTION
2
4
6
DALO
DAL1
DAL2
DAL3
DAL3
DAL5
DAL6
DAL7
8 bit bi·directional Data Access Lines. These lines
remain in a high·impedance state whenever the CS line
is inactive.
10
12
14
16
1
3
5
7
9
11
13
15
18
20
22
17
19
21
AO
A1
A2
These three Address Lines are used to select one of
eight registers in the Task File. They must remain
stable during all read and write operations.
24
23
CS
When Card Select is active along with RE or WE, Data
is read or written via the DAL bus. CS must make a
transition for each byte read from or written to the task
file.
26
25
When Write Enable is active along with Cs, the host
may write data to a selected register of the WD1000.
28
27
When Read Enable is active along with Cs, the host
may read data from a selected register of the WD1000.
30
29
Upon receipt of a Cs, the WAIT line may go active. It
returns to the inactive state when the DAL lines are
valid on a read, or data has been accepted on a write.
32
31
Not Connected
34
33
-v
Optional - V input from host supplies - 8 to -15V to
the on·board - 5 Volt regulaton (VRI). This power input
is also available on J6, pin 2. - V is not required if
DC/DC convertor (PSI) is used.
36
35
INTRQ
The INTerrupt ReQuest Line is activated whenever a
command has been completed. It is reset to the
inactive state when the Status Register is read, or a
new command is loaded via the DAL lines.
8
•
15
:ec
.....
§
HOST INTERFACE CONNECTOR (Continued)
~
SIGNAL GROUND
SIGNAL PIN
SIGNAL NAME
37
DRO
The Data ReOuest line is activated whenever the sector
buffer contains data to be read by the host, or is
awaiting data to be loaded by the host. This line is
reset whenever the Data Register is read from or
written to. The DRO line will continue to toggle until
the buffer is exausted or until a write or read is performed on the Cylinder Low register.
39
MR
The Master Reset line initializes all internal logic on the
logic on the WD1000. Sector Number, Cylinder Number
and SDH are cleared, stepping rate is set to 7.5 mS,
Write Precomp is set to cylinder 128 and Sector Count
is set to 1. The DRO line is reset and the INTRO line
is set.
41
42
43-50
Not Connected
Not Connected
DESCRIPTION
I
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38
o
8
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40
I
+ 5V 8 power pins for regulated + 5 volts. This power
input is also available on J6, pin 3.
I
Note: Grounds
Even numbered pins (2-40) are to be used as signal
grounds. Power ground is available on J6, pin 1.
DRIVE CONTROL CONNECTORS
The drive control connector is a (relatively) low speed bus
that is daisy chain connected to each of the drives (up to
four) in the system. To properly terminate each TTL level
output signal from the WD1000, the last drive in the daisy
chain should have a 220/330 ohm line termination resistor
pack installed. All other drives should have no termination.
See Tables 2 and 3:
34 PIN DRIVE CONTROL CONNECTOR
SIGNAL
GROUND
SIGNAL
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
1/0
0
0
0
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0
0
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0
0
0
0
0
0
50 PIN DRIVE CONTROL CONNECTOR FOR SA1000
TYPE INTERFACE
TABLE 3
TABLE 2
SIGNAL
NAME
RWC
Head Select 2"
Write Gate
Seek Complete
TROOO
--Write Fault
Head Select '0
NC
Head Select 1"
Index
Ready
Step
Drive Select 1"
Drive Select 2"
Drive Select 3
Drive Select 4"
Direction Tn
16
SIGNAL
GROUND
SIGNAL
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
1/0
0
0
I
0
0
I
I
0
0
0
0
0
0
0
I
I
SIGNAL
NAME
RWC
Head Select 2"
NC
Seek Complete
NC
NC
Head Select (5
NC
Head Select 1"
Index
Ready
NC
Drive Select 1"
Drive Select 2"
Drive Select· 3"
Drive Select 4"
Direction Til
Step
NC
Write Gate
TROOO
Write Fault
NC
NC
NC
•
DRIVE CONTROL SIGNAL DESCRIPTIONS
DS1DS4
RWC
These four Drive Select lines are used to select one of four
possible drives.
When the Redluce Write Current line is activated with write
gate, a lower write current is used to compensate for greater bit packing density on the Inner cylinders. The RWC line
Is activated when the cylinder number is greater than or
equal to four times the contents of the Write Precomp Register. This output is valid only during Write and Format
commands.
DRIVE DATA CONNECTOR
Four data connectors (J1-4) are provided for clock Signals
and data between the WD1000 and each drive. All lines associated with the transfer of data between the drive and the
WD1000 system are differential in nature and may not be
multiplexed. The data connectors are 20 pin vertical
headers on tenth-Inch centers that mate with Burndy
#FRS2OBS. The cable used should be flat ribbon cable or
twisted pair with a length of less than 10 feet. The cable
pin-outs are per Table 4:
Write Gate
This output signal allows data to be written on the disk.
Seek Complete
Informs the WD1000 that the head of the selected drive has
reached the desired cylinder and has stabilized. Seek Complete is not checked after a SEEK command, thus allowing
overlapped seeks.
DATA CONNECTIONS AND DESCRIPTIONS
SIGNAL
GROUND
SIGNAL
PIN
2
4
6
8
1
3
5
7
9
10
0
0
13
14
0
0
17
18
I
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Track 000
Indicates that the R/W heads are positioned on the outermost cylinder. This line is sampled immediately before
each step is issued.
Write Fault
15
16
HSOHS2
Head Select lines are used by the WD1000 to select a specific R/W head on the selected drive.
19
index
20
Is used to indicate the index point for synchronization during formatting and as a time out mechanism for retries.
This signal should pulse once each rotation of the disk.
SIGNAL
NAME
- Drive Selected
NC
NC
NC
+ Timing Clock
- Timing Clock
GND
GND
+ MFM Write Data
- MFM Write Data
GND
GND
+ MFM READ DATA
- MFM READ DATA
GND
GND
DIFFERENTIAL DATA DRIVER/RECEIVER
Roady
In'forms the WD1000 that the desired drive is selected and
that its motor is up to speed. The WD1000 will not execute
commands unless this line is true.
HIIlH
HIIlH
TRUE
TftUE
AMD28LS31
or 15110A
NOTE: ANY RS 422
DRIVER/RECEIVER PAIR
WILL INTERFACE
Step
This line is pulsed once for each cylinder to be stepped.
The direction of the step will be determined by the DIRECTION line. The step pulse period is determined by the internal stepping rate register during implied seek operations or
explicitly during Seek and Restore commands. During auto
restore, the step pulse period is determined by the SEEK
COMPLETE time from the drive.
Z,10512
FLAT RIBBON OR TWISTED PAIR
MAX 10 FT.
1. Open for AMD 21LS31 (8T&08)
Clo..d lor76110A(SA10001
POWER CONNECTOR
A three pin molex connector (J6) is provided for power Input to the board. The customer supplied mating connector
housing Is Molex 03-09-1032. The pin-outs are as shown in
Table 5:
TABLES
Tn
PIN
1
2
3
Determines the direction of motion of the R/W head when
thE~ step line is pulsed. A high on this line defines the direction as out and a low defines direction as in.
-
I
11
12
Informs the WD1000 that some fault has occurred on the
selected drive. The WD1000 Will not execute commands
when this signal is true.
Direction
110
TABLE 4
17
SIGNAL NAME
GROUND
- 8 to -15 V unregulated
+ 5 V regulated
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COMMANDS
TYPE I COMMANDS
The WD1000 executes five easy to use macro commands.
Most commands feature automatic 'implied' seek, which
means the host system need not tell the WD1000 where the
RJW heads of each drive are or when to move them. The
controller automatically performs all needed retries on all
errors encountered including data CRC errors. If the RJW
head mis-positions, the WD1000 will automatically perform
a restore and a re-seek. If the error is completely unrecoverable, the WD1000 will simulate a normal completion
to simplify the host system's software.
These commands simply position the RJW heads of the selected drive. Both commands have explicit stepping rate
fields. The lower four bits of these commands form the
stepping rate.
RESTORE
The Restore command is used to calibrate the position of
the RJW head on each drive by stepping the head outward
until the TRooo line goes true. Upon receipt of the Restore
command, the Busy bit in the Status Register is set. Cylinder High and Cylinder Low Registers are cleared. The lower
four bits of the command byte are stored in the stepping
rate register for subsequent implied seeks. The state of
Seek Complete, Ready and Write Fault are sampled, and if
an error condition exists, the Aborted command bit in the
Error Register is set, the Error bit in the Status Register is
set, an interrupt is generated and the Busy bit is reset.
If no errors are encountered thus far, the internal head position register for the selected drive is cleared. The TRooo
line is sampled. If TRooo is true, an interrupt is generated
and the Busy bit is reset. If TRooo is not true, stepping
pulses at a rate determined by the stepping rate field are
issued until the TRooo line is activated. When TRooo is activated, the Busy bit is reset and an interrupt is issued. If the
TRooo line is not activated within 1023 stepping pulses, the
TRooo Error bit in the Error Register and the Error bit in the
Status Register are set, the Busy bit is reset and an interrupt is issued.
Commands are executed by loading the command byte
into the Command Register while the controller is not
busy. (Controller will not be busy if it has completed the
previous command.) The task file must be loaded prior to
issuing a command. No command will execute if the Seek
Complete or Ready lines are false or if the Write Fault line
is true. Normally it is not necessary to poll these signals
before issuing a command. If the WD1000 receives a command that is not defined in the following table, undefined
results will occur.
For ease of discuSSion, commands are divided into three
types which are summarized in Table 6:
TABLES
TYPE COMMAND
7
6
5
BITS
4
3
2
1
0
I
Rastore
0
0
0
1
r3
r2
r1
rO
I
Seek
0
1
1
1
r3
r2
r1
ro
II
Read Sector
0
0
1
0
0
0
0
0
III
Write Sector
0
0
1
1
0
0
0
0
III
Format Track
0
1
0
1
0
0
0
0
1-.
ra-ro -
STEPPING RATE
0000
0001
0010
0011
0100
0101
0110
0111
o=
SEEK
The Seek command positions the RJW head to a certain cylinder. It is primarily used to start two or more concurrent
seeks on drives that support buffered stepping. Upon receipt of the Seek command, the Busy bit in the Status
Register is set. The lower four bits of the command byte
are stored in the stepping rate register for subsequent
implied seeks. The state of Seek Complete, Ready and
Write Fault are sampled, and if an error .condition exists,
the Aborted command bit in the Error Register is set, the
Error bit in the Status Register is set, an interrupt is
generated and the Busy bit is reset.
If no errors are encountered thus far, the internal head position register for the selected drive is updated, the direction
line is set to the proper direction and a step pulse is issued
for each cylinder to be read and an interrupt is issued. Note
that the Seek Complete line is not sampled after the Seek
command, allowing multiple seek operations to be started
using drives with buffered seek capability.
= 10uS
=
=
=
=
=
O.SmS
1.0mS
1.SmS
2.0mS
2.SmS
= 3.0mS
= 3.5mS
1000
1001
1010
1011
1100
1101
1110
1111
= 4.0mS
= 4.5mS
= 5.0mS
= 5.5mS
= 6.0mS
= 6.5mS
= 7.0mS
= 7.5mS
DMA Read Mode
TYPE II COMMANDS
o = Programmed 110 Mode
1 = DMAMode
This type of command is characterized by a transfer of a
block of data from the WD1000 buffer to the host. This command has an implicit stepping rate as set by the last Restore or Seek command.
The Read Sector command is used to read a sector of data
from the disk to the host computer. Upon receipt of the
Read command, the Busy bit in the Status register is set.
The state of Seek Complete, Ready and Write Fault are
sampled, and if an error condition exists, the Aborted
Command bit in the Error Register is set, the Error bit in the
Status Register is set, and a normal completion is
simulated.
NOTE:
The DMA bit is used to position INTRa in relation to
DRas during the read sector command. If the DMA bit
is reset (0 = 0), the interrupt will occur before the first
ORO. This allows the programmed 110 host to intervene
and transfer the data from the sector buffer. If the DMA
bit Is set (0 = 1), then the interrupt will occur only after
the system OMA controller has transferred the entire
buffer of data.
18
If no errors are encountered so far, a Seek command is executed. The Seek Complete line is sampled. If the Seek
Complete line does not go true within 128 Index pulses, the
Aborted command bit in the Error Register is set, the Error
bit in the Status Register is set, and a normal completion is
simulated.
Once the head has settled over the desired cylinder, the
WD1000 will attempt to read the sector. The WD1000 performs all retries necessary to recover the data during the
read command. The controller attempts to read the desired
sector up to 16 times. It will attempt a retry if it does not
find an ID, if the ID of that sector has a bad CRC, if the Data
Address Mark (DAM) couldn't be found or even if the data
was actually read from the disk but incurred a data CRC
error.
Every time the controller encounters an error, it records the
occurance of that error in an internal register. If, after 16
retries, the controller was not able to get a match on the ID
field, it assumes that the head was possibly mis-positioned
and executes an auto-restore. During the auto-restore, the
stepping rate is implied to be equal to the Seek Complete
period. After the auto-restore has been successfully completed, the controller re-seeks and attempts to read the
sector once again. An auto-restore will be performed only
once per read or write sector command.
If the controller encounters a non-recoverable error, the
controller examines its internal error history register. It then
sets the bit in the Error Register of the highest severity
error incurred. If the Data CRC Error bit is set, the data that
last produced that error will be available in the sector
buffer. The Error bit in the Status Register is set and a
normal completion is simulated.
all retries necessary to recover the ID during the write command. The controller attempts to read the ID of the desired
sector up to 16 times. It will attempt a retry if it doesn't find
an ID or if the ID of that sector has a bad CRC.
Every time the controller encounters an error, it records the
occurrence of that error" in an internal register. If, after 16
retries, the controller was not able to get a match on the ID
field, it assumes that the head was possibly mis-positioned
and executes an auto-restore. During the auto-restore, the
stepping rate is implied to be equal to the Seek Complete
period. After the auto-restore has been successfully completed, the controller re-seeks and attempts to write the
sector once again.
If the controller encounters a non-recoverable error, the
controller examines its internal error history register. It then
sets the bit in the Error Register of the highest severity
error incurred. The Error bit in the Status Register is set, an
Interrupt is generated and the Busy bit is reset.
If the proper sector is located, the sector buffer is written to
the disk, an interrupt is generated and the Busy bit is reset.
FORMAT TRACK
The Format command is used for initializing the ID and
data fields on a particular disk. Upon receipt of the Format
command, the controller generates DROs for each byte of
the interleave table to be written to the buffer. In all cases,
the number of bytes transferred to the buffer must correspond to the current sector size.
After all data has been sent to the buffer, the Busy bit in the
Status Register is set. The state of Seek Complete, Ready
and Write Fault lines are sampled. If an error condition
exists, the Aborted command bit in the Error Register is
set, the Error bit in the Status Register is set, an interrupt is
generated and the Busy bit is reset.
TYPE III COMMANDS
This type of command is characterized by a transfer of a
block of data from the host to the WD1000 buffer. These
commands have implicit stepping rates as set by the last
Restore or Seek command.
WRITE SECTOR
NOTE:
1) When MSB of head byte
1, bad block is detected.
2) Write Gate turn-on is 3 bytes after the ID field's CRC bytes.
3) Write Gate turn-off Is 3 bytes after the Data Field's CRC
bytes.
4) 12 bytes of zeroes are re-written on a Data Field update.
5) The 2 LSB's of the IDENT byte are used for Cylinder high
These values are:
FE
0 to 255 cylinders
FF
256 to 511 cylinders
FC
512 to 767 cylinders
FD
768 to 1023 cylinders
6) GAP 4 values are:
=
The Write Sector command is used to write a sector of data
from the host computer to the disk. Upon receipt of the
Write command, the controller generates DROs for each
byte to be written to the buffer. (Note: It is recommended
that programmed I/O transfers should take place as a block
move without consulting the DRO bit in the Status
Register.)
=
=
=
=
Atter all data has been sent to the sector buffer, the Busy
bit in the Status Register is set. The state of Seek Complete, Ready and Write Fault are sampled, and if an error
condition exists, the Aborted command bit in the Error
Register is set, the Error bit in the Status Register is set, an
Interrupt is generated and the Busy bit is reset.
If no errors are encountered so far, a Seek command is executed. The Seek Complete line is sampled. If the Seek
Complete line doesn't go true within 128 Index pulses, then
the Aborted command bit in the Error Register is set, the
Error bit in the Status Register is set, an Interrupt is
generated and the Busy bit is reset.
Once the head has settled over the desired cylinder, it will
attempt to read the ID of the sector. The WD1000 performs
-
SECTOR LENGTH
GAP 3
GAP 4
SECTOR COUNT
128
256
512
15
15
30
356
352
800
54
32
17
If no errors are encountered so far, a Seek command is executed. No verification of track positioning accuracy is performed because the track may not have any ID fields
present. After the Seek operation has been performed, the
Seek Complete line is sampled. If the Seek Complete line is
not asserted within 128 Index pulses, the Aborted com-
19
=E
c
-'"
o
o
o
SOH REGISTOR
BIT
FUNCTION
mand bit in the Error Register is set, an Interrupt is
generated and the Busy bit is reset.
Once the head has settled over the desired cylinder, the
controller starts writing a pattern of 4E's until the index is
encountered. Once the index is found, a number of 10
fields and nulled data fields are written to the disk. The
number of sectors written is equal to the contents of the
Sector Count Register. As each sector is written, the Sector
Count Register is decremented, and consequently, must
be updated before each format operation.
After the last sector is written, the controller back-fills the
track with 4E's. When the next index pulse after the last
sector is written is encountered, the format operation is terminated, an Interrupt is generated and the Busy bit is reset.
SETIING UP TASK FILES
Before any of the five commands may be executed, a set of
parameter registers called the Task File must be set up. For
most commands, this informs the WD1000 of the exact location on the disk that the transfer should take place. For a
normal read or write sector operation, the Sector Number,
the Size/Drive/Head, Cylinder Number, and Command
registers (usually in that order) will be written.
X
X
X Deselected
0
0
0
0
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
Data Register
Error Register
Sector Count
Sector Number
Cylinder Low
Cylinder High
Size/Drive/Head
Status Register
1
2
3
0
0
1
0
1
1
256 Bytes
512 Bytes
128 Bytes
BIT4
BIT3
DRIVE SELECTED
0
0
1
1
0
1
DriveSelO
Drive Sel1
DriveSel2
DriveSel3
BIT2
BIT1
BITO
HEAD SELECTED
0
0
0
0
1
1
0
0
1
1
0
1
Head 0
Head 1
Head 2
Head 3
Head 4
Head 5
Head 6
Head 7
0
1
0
1
0
1
0
1
0
Head
Select
STATUS AND ERROR REGISTER BITS
5
4
3
STATUS REGISTER
Busy
Ready
Write Fault
Seek Complete
Data Request' "
-
2
1
°i
Error
ERROR REGISTER
\
. ~ Bad Block Detect
!
.' j eRC Error Data Field
I CRC Error 10 Field
10 Not Found
Aborted Command
TROOO Error
DAM not found
PROGRAMMING
Users familiar with floppy disk systems will find programming the WD1000 a pleasant surprise. A substantial
amount of intelligence that was required by the host computer has been incorporated into the WD1000. The WD1000
performs all needed retries, even on data CRC and head
positioning errors. Most commands feature automatic
'implied' seek which means that seek commands need not
be issued to perform basic read/write functions. The
WD1000 keeps track of the position of up to four read/
write head assemblies, so the host system does not have
to maintain track tables. All transfers to and from the disk
are through an on-board full sector buffer. This means that
data transfers are fully interruptable and can take place at
any speed that is convenient to the system designer. In the
event of an unrecoverable error, the WD1000 simulates a
normal completion so that special error recovery software
is not needed.
REGISTER SELECTION ARRAY
A2 A1 AO RE
4
Drive
Select
SECTOR SIZE
BIT
7
6
Since most hard disk drives contain more than one head
per positioner, it is more efficient to step the R/W head assemblies of most disk drives by cylinders, not tracks. In
other words, the disk driver software should be designed to
read or write all data that is directly accessable by all the
heads on a positioner before stepping toa new cylinder.
1
Sec
Size
BITS
0
1
1
1
1
Since the WD1000 can recall all the Task File parameters
sent to it, it is recommended that Task File parameters be
stored in the WD1000 as they are calculated. This will save
the programmer a few instructions by not maintaining two
copies of the same information.
ts
6
BIT6
0
Note that most of these registers are readable as well as
writable. These registers normally are not read from, but
this feature is provided so that error reporting routines can
determine physically where an error occurred without recalculating the sector, head and cylinder parameters.
5
7
0
WE
Deselected
Data Register
Write Precomp
Sector Count
Sector Number
Cylinder Low
Cylinder High
Size/Drive/Head
Command Register
See page 725 for ordering information.
20
Printed," U.S A
WESTERN DIGITAL
c
o
R
P
o
R
A
T
/
o
N
WD1001 Winchester Disk Controller
FEATURES
• SINGLE + 5V SUPPLY
• BUILT-IN DATA SEPARATOR
• BUILT-IN WRITE PRECOMPENSATION LOGIC
• DATA RATES UP TO 5 MBITS/SEC
• CONTROL FOR UP TO 4 DRIVES
• CONTROL FOR UP TO 8 R/W HEADS
• 1024 CYLINDER ADDRESSING RANGE
• 256 SECTOR ADDRESSING RANGE
• 32 BIT ECC FOR BURST ERROR CORRECTION
• ERROR CORRECTION ON DATA FIELD
ERRORS
• DIAGNOSTIC READS AND WRITES FOR
CHECKING ERROR CORRECTION
• BAD BLOCK MAPPING CAPABILITY
• AUTOMATIC FORMATTING
• 128, 256, OR 512 BYTES PER SECTOR
(SOFTWARE SELECTABLE)
• UNLIMITED SECTOR INTERLEAVE CAPABILITY
• MULTIPLE SECTOR READS AND WRITES
• OVERLAP SEEK CAPABILITY
• IMPLIED SEEK ON ALL COMMANDS
• AUTOMATIC RETRIES ON ALL ERRORS
• AUTOMATIC RESTORE AND RE-SEEK ON
SEEK ERROR
• 8-BIT HOST INTERFACE
• O°C TO 50°C OPERATION
GENERAL DESCRIPTION
The WD 1001 is a stand-alone, general purpose
Winchester controller board designed to interface up
to four Winchester disk drives to a host processor.
The drive signals are based upon the floppy lookalike interface available on the Shugart Associates'
SA 1000, the Seagate Technology ST506, the Quantum Q2000, and other compatible drives. All necessary buffers and receivers/drivers are included on the
board to allow direct connection to the drive. Either a
34 pin (51/4" drive) or 50 pin (8" drive) connector is provided, as well as four 20 pin data connectors.
ORGANIZATION
The WD1001 has seven on-board connectors. These
connectors consist of a power connector, host interface connector, drive control connector, and four
high speed data cable connectors.
Communications to and from the host computer are
made via a separate computer access port. This port
consists mainly of an 8 bit bi-directional bus and appropriate control signals. All data to be written to or
read from the disk, status information, and macro
commands are transferred via this 8 bit bus. An on
board sector buffer allows data transfers to the host
computer independent of the actual data transfer rate
of the drive.
The drive data connectors carry differential signals
and are radially connected. Up to four drives can be
accommodated by the WD1 001.
The WD1001 is based upon a proprietary chip series,
the WD1100, specifically designed for Winchester
Control.
The host interface connector provides interface signals that are compatible with most microprocessors
and mini-computers.
The drive control cable is daisy-chained to each of
the four drives. Although there is space for two drive
control connectors, only one would normally be used
for any particular configuration.
The WD1001 provides dual burst detection and single
5-bit burst correction ECC circuitry. The ECC
polynomial has been computer generated for optimum error correction on Winchester Disks.
21
y,
SUPPORT SIGNALS
-1°1'
SUPPORT SIGNALS
CONTROL
&
SUPPORT
LOGIC
CONTROL SIGNALS
TIMING SIGNALS
J7.J8
INTERNAL BUS
DRIVE CONTROL
LATCH
J5
I
F
C.
SIMPLIFIED SYSTEM BLOCK DIAGRAM - WD1001
SPECIFICATIONS
Encoding method:
Cylinders per Head:
Sectors per Track:
Heads:
Drive Selects:
Step rate:
Data Transfer Rate:
Write Precomp Time:
Sectoring:
Host Interface:
Drive Capability:
Drive Cable Length:
Host Cable Length:
Power Requirements:
Ambient Temperature
Operating:
Relative Humidity:
MTBF:
MTTR:
Length:
Width:
Height:
Mounting Centers:
HOST INTERFACING
The WD1001 is designed to easily interface to most
micro computers and mini-computers. All interfacing
is done through the Host Interface Connector (J5).
The interface is very similar to Western Digital's
family of Floppy Disk Controllers. The only exception
is the inclusion of the WAIT line.
MFM
Up to 1024
Up to 256 (512 byte sec)
8
4
10 lAS to 7.5 mS
(0.5 mS increments)
4.34 Mbits/sec or
5.000 Mbits/sec
12 nanoseconds
Soft
8 Bit bi-directional bus
10 "LS" Loads
10 ft. (3M) max.
3 ft. (1 M) max.
+ 5V ± 5%, 3.0A Max. (2.5A
typ.)
WAITS
The WAIT control line goes true whenever either of
the following are true:
• The WD1001 is accessing data internally to send
to the host during a read operation.
• The WD1001 has not accepted the data from the
host during a write operation.
The definition of the WAIT line is very similar to the
WAIT signal found on many popular processors.
WAIT is also similar to the REPLY signal on Western
Digital and other processors.
O°C to 50°C (32 F to 122 F)
20% to 80%
10,000 POH
30 minutes
9.9 in. (24.9 cm)
6.8 in. (17.1 cm)
0.75 in. (1.9 cm)
6.375 x 9.375 in.
(16 x 23.6 cm)
WAIT will not necessarily make a transition for each
access to the WD1001. When the WD1001 can return
the requested data within 100 nS, there will be no
transition of the WAIT line. This should be interpreted
as an instant REPLY on Western Digital Processors.
If the WD1001 cannot return the requested data
22
within 100 nS, it will assert its WAIT line. The period
of the WAIT signal will vary from 750 nS to 6/AS with
1.25/AS being about average. The period of the WAIT
only approaches 6 /AS during a read or write which
happens immediately after a command is written to
the command register. This means that longer waits
may be encountered during the first read or write to
any WD1001 register if that first read or write happens within approximately 6/AS of a command being
issued.
During the time that WAIT is asserted, the host system must hold all of its strobe and address lines stable. On write operations, the DAL lines must also be
held stable.
The Host Interface connector (J5) consists of an
eight bit bi-directional bus, three bit address bus, and
seven control lines. All commands, status, and data
are transferred over this bus. See Table 1:
TABLE 1
HOST INTERFACE CONNECTOR
SIGNAL GROUND SIGNAL PIN
SIGNAL NAME
DESCRIPTION
2
4
6
8
10
12
14
16
18
20
22
1
3
5
7
9
11
13
15
DALO
DAL1
DAL2
DAL3
DAL4
DAL5
DAL6
DAL7
8 bit bi-directional Data Access Lines. These
lines remain in a high-impedance state whenever the CS line is inactive.
17
19
21
AO
A1
A2
24
23
CS
26
25
WE
28
27
RE
30
29
WAIT
. These three Address Lines are used to select
one of eight registers in the Task File. They
must remain stable during all read and write
operations.
When Card Select is active along with RE...Q!'
WE, Data is read or written via the DAL bus. CS
must make a transition for each byte read from
or written to the task file.
When Write Enable is active along with CS, the
host may write data to a selected register of the
WD1000.
When Read Enable is active along with CS, the
host may read data from a selected register of
theWD1001.
Upon receipt of a CS, the WAIT line may go active. It returns to the inactive state when the
DAL lines are valid on a read, or data has been
accepted on a write.
32
34
36
31
33
35
Not Connected
Not Connected
INTRQ
38
37
DRQ
The INTerrupt ReQuest Line is activated whenever a command has been completed. It is reset
to the inactive state when the Status Register is
read, or a new command is loaded via the DAL
lines.
The Data ReQuest line is activated whenever
the sector buffer contains data to be read by the
host, or is awaiting data to be loaded by the
host. This line is reset whenever the Data Register is read from or written to. The DRQ line will
continue to toggle until the buffer is exhausted
or until a write or read is performed on the
Cylinder Low register.
23
TABLE 1
HOST INTERFACE CONNECTOR
=e
c.....
8
.....
SIGNAL GROUND
SIGNAL PIN
SIGNAL NAME
DESCRIPTION
40
39
MR
The Master Reset line initializes all internal
logic on the logic on the WD1001. Sector Number, Cylinder Number and SOH are cleared,
stepping rate is set to 7.5 mS, Write Precomp is
set to cylinder 128 and Sector Count is set to 1.
The ORa and INTRa lines are reset.
41
42
43-50
Not Connected
Not Connected
8 power pins for regulated + 5 volts. This power
input is also available on J6, pin 3.
All even numbered pins (2 through 40) are to be
used as signal grounds. Power ground is available on J6, pin 1.
+5V
Note: Grounds
DRIVE CONTROL CONNECTORS
The drive control connector is a (relatively) low speed
bus that is daisy chain connected to each of the
drives (up to four) in the system. To properly terminate each TTL level output signal from the
WD1001, the last drive in the daisy chain should have
a 220/330 ohm line termination resistor pack installed. All other drives should have no termination.
See Tables 2 and 3:
34 PIN DRIVE CONTROL CONNECTOR
SIGNAL
GROUND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
SIGNAL
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
I
I
I
0
I
0
I
I
32
0
0
0
0
0
34
0
30
SIGNAL
GROUND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
TABLE 2
SIGNAL
NAME
I/O
0
0
0
50 PIN DRIVE CONTROL CONNECTOR FOR
TABLE 3
SA1000 TYPE INTERFACE
i1WC
Head Select 2'
Write Gate
Seek Complete
TROOO
Write Fault
Head Select (5
Sector
Head Select l'
Index
Ready
Step
_
Drive Select 1
Drive select '2
Drive select 3'
Drive select 4'
Direction In
SIGNAL
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
0
0
I
0
I
0
I
I
RWC
Head Select '2
NC
Seek Complete
NC
NC
Head Select (5
Sector
Head Select l'
Index
Ready
NC
Drive Select T
Drive Select 2"
Drive Select :3
Drive Select 4"
Direction Tn
0
0
0
0
0
0
step
0
NC
Write Gate
38
40
42
44
46
48
50
SIGNAL
NAME
I/O
I
I
TROOO
Write Fault
NC
NC
NC
DRIVE CONTROL SIGNAL DESCRIPTIONS
Write Gate
This output signal allows data to be written on the
disk.
RWC
When the Reduce Write Current line is activated with
Write Gate, a lower write current is used to compensate for greater bit packing density on the inner
cylinders. The RWC line is activated when the
cylinder number is greater than or equal to four times
the contents of the Write Precomp Register. This
output is valid only during Write and Format commands.
Seek Complete
Informs the WD1001 that the head of the selected
drive has reached the desired cylinder and has
stabilized. Seek Complete is not checked after a
SEEK command, thus allowing overlapped seeks.
24
•
with a length of less than 10 feet. The cable pin-outs
are per Table 4:
Track 000
Indicates that the R/W heads are positioned on the
outer-most cylinder. This line is sampled immediately
before each step is issued.
=e
C
•
8•
Write Fault
DATA CONNECTIONS
AND DESCRIPTIONS
SIGNAL
SIGNAL
PIN
GROUND
2
1
4
3
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Informs the WD1001 that some fault has occurred on
the selected drive. The WD1001 will not execute
commands when this signal is true.
HSOHS2
Head Select lines are used by the WD1001 to select a
specific R/W head on the selected drive.
fndex
Is used to indicate the index point for synchronization during formatting and as a time out mechanism
for retries. This signal should pulse once each rotation of the disk.
f\eady
Informs the WD1001 that the desired drive is selected
and that its motor is up to speed. The WD1001 will
not execute commands unless this line is true.
I/O
I
0
0
0
0
I
I
TABLE 4
SIGNAL
NAME
- Drive Selected
NC
NC
NC
+ Timing Clock
- Timing Clock
GND
GND
+ MFM Write Data
- MFM Write Data
GND
GND
+ MFM Read Data
- M FM Read Data
GND
GND
Step
This line is pulsed once for each cylinder to be
Btepped. The directiQD of the step will be determined
by the DIRECTION IN line. The step pulse period is
determined by the internal stepping rate register
during implied seek operations or explicitly during
Seek and Restore commands. During auto restore,
the step pulse period is determined by the SEEK
COMPLETE time from the drive.
DIFFERENTIAL DATA DRIVER/RECEIVER
HIGH
TRUE
AMD 26LS31
or 75110A
Direction in
Determines the direction of motion of the R/W head
when the step line is pulsed. A high on this line
defines the direction as out and a low defines
direction as in.
NOTE: ANY RS 422
DRIVER/RECEIVER PAIR
WILL INTERFACE
Zx= 1052
FLAT RIBBON OR TWISTED PAIR
MAX 10 FT.
iDS1 DS4
These four Drive Select lines are used to select one
of four possible drives.
POWER CONNECTOR
A three pin molex connector (J6) is provided for
power input to the board. The customer supplied
mating connector housing is Molex 03-09-1032. The
pin-outs are as shown in Table 5:
DRIVE DATA CONNECTOR
Four data connectors (J1-4) are provided for clock
signals and data between the WD1001 and each
drive. All lines associated with the transfer of data
between the drive and the WD1001 system are differential in nature and may not be multiplexed. The
data connectors are 20 pin vertical headers on tenthinch centers that mate with Burndy #FRS20BS. The
cable used should be flat ribbon cable or twisted pair
TABLES
I
25
S_IG_N_A_L~N~A_M_E
Ground
P2:IN ____
Not Connected____________
+ 5 V Regulated
~
:ec
.....
o
o.....
NOTE:
The DMA bit is used to position INTRa in relation to
DROs during the read sector command. If the DMA
bit is reset (D = 0), the interrupt will occur before the
first DRO. This allows the programmed 1/0 host to
intervene and transfer the data from the sector buffer.
If the DMA bit is set (D = 1), then the interrupt will
occur only after the system DMA controller has
transferred the entire buffer of data.
COMMANDS
The WD1001 executes five easy to use macro
commands. Most commands feature automatic
'implied' seek, which means the host system need
not tell the WD1001 where the RIW heads of each
drive are or when to move them. The controller
automatically performs all needed retries on all
errors encountered including data ECC errors. If the
R!W head mis-positions, the WD1001 will automatically perform a restore and a re-seek. If the error is
completely unrecoverable, the WD1001 will simulate
a normal completion to simplify the host system's
software.
TYPE I COMMANDS
These commands simply position the RIW heads of
the selected drive. Both commands have explicit
stepping rate fields. The lower four bits of these
commands form the stepping rate.
Commands are executed by loading the command
byte into the Command Register while the controller
is not busy. (Controller will not be busy if it has
completed the previous command.) The task file
must be loaded prior to issuing a command. No
command will execute if the Seek Complete or
Ready lines are false or if the Write Fault line is true.
Normally it is not necessary to poll these signals
before issuing a command. If the WD1001 receives a
command that is not defined in the following table,
undefined results will occur.
RESTORE
The Restore command is used to calibrate the
position of the R!W head on each drive by stepping
the head outward until the TROOO line goes true.
Upon receipt of the Restore command, the Busy bit
in the Status Register is set. Cylinder High and
Cylinder Low Registers are cleared. The lower four
bits of the command byte are stored in the stepping
rate register for subsequent implied seeks. The state
of Seek Complete, Ready and Write Fault are sampled, and if an error condition exists, the Aborted
command bit in the Error Register is set, the Error bit
in the Status Register is set, an interrupt is generated
and the Busy bit is rest.
For ease of discussion, commands are divided into
three types which are summarized in Table 6:
TABLE 6
I
I
II
III
III
ra-ro -
BITS
4 a 2
COMMAND
7
6
5
Restore
Seek
Read Sector
Write Sector
Format Track
0
0
0
0
0
0
1
0
0
1
0 1
1 1
1 0
1 1
0 1
TYPE
STEPPING RATE
0000 = 10/-lS
0001 = 0.5mS
0010 = 1.0mS
0011 = 1.5mS
0100 = 2.0mS
0101
2.5mS
0110 = 3.0mS
0111 = 3.5mS
=
1000
1001
1010
1011
1100
1101
1110
1111
r3
r3
D
0
0
r2
r2
M
M
0
1
r1 ro
r1 ro
L 0
L 0
0 0
SEEK
The Seek command positions the R!W head to a
certain cylinder. It is primarily used to start two or
more concurrent seeks on drives that support buffered stepping. Upon receipt of the Seek command,
the Busy bit in the Status Register is set. The lower
four bits of the command byte are stored in the
stepping rate register for subsequent implied seeks.
The state of seek Complete, Ready and Write Fault
are sampled, and if an error condition exists, the
Aborted command bit in the Error Register is set, the
Error bit in the Status Register is set, an interrupt is
generated and the Busy bit is reset.
= 4.0mS
= 4.5mS
=
=
=
=
5.0mS
5.5mS
6.0mS
6.5mS
= 7.0mS
= 7.5mS
=
L = Long ReadlWrite
=
o = Normal ReadlWrite
1 = Long ReadlWrite
D
DMA Read Mode
o = Programmed 1/0
Mode
DMA Mode
1
If no errors are encountered thus far, the internal
head positio~ister for the selected drive is
cleared. The TROOO line is sampled. If TROOO is true,
an interrupt is generated and the Busy bit is reset. If
TROOO is not true, stepping pulses at a rate determined by the stepping rate field are issued until the
TROOO line is activated. When TROOOis activated, the
Busy bit is reset and an interrupt is issued. If the
TROOO line is not activated within 1023 stepping
pulses, the TROOO Error bit in the Error Register and
the Error bit in the Status Register are set, the Busy
bit is reset and an interrupt is issued.
0
If no errors are encountered thus far, the internal
head position register for the selected drive is updated, the direction line is set to the proper direction
and a step pulse is issued for each cylinder to be read
M = 1 = Multiple Sector ReadlWrite
o
Single Sector ReadlWrite
=
26
and an interrupt is issued. Note that the Seek
Complete line is not sampled after the Seek command, allowing multiple seek operations to be
started using drives with buffered seek capability.
error will be available in the sector buffer. The Error
bit in the Status Register is set and a normal completion is simulated.
TYPE II COMMANDS
This variation of the Read command allows the user
to read the ECC check bits directly. The check bits
are placed in the data buffer immediately behind the
data. This increases the effective buffer length by
four bytes.
READ LONG
This type of command is characterized by a transfer
of a block of data from the WD1 001 buffer to the host.
This command has an implicit stepping rate as set by
the last Restore or Seek command.
READ SECTOR
The Read Sector command is used to read a sector of
data from the disk to the host computer. Upon receipt
of the Read command, the Busy bit in the Status
register is set. The state of Seek Complete, Ready
and Write Fault are sampled, and if an error condition
exists, the Aborted Command bit in the Error Register is set, the Error bit in the Status Register is set,
and a normal completion is simulated.
TYPE III COMMANDS
This type of command is characterized by a transfer
of a block of data from the host to the WD1oo1 buffer.
These commands have impliCit stepping rates as set
by the last Restore or Seek command.
WRITE SECTOR
The Write Sector command is used to write a sector
of data from the host computer to the disk. Upon
receipt of the Write command, the controller
generates DROs for each byte to be written to the
buffer. (Note: It is recommended that programmed
110 transfers should take place as a block move
without consulting the DRO bit in the Status
Register.)
If no errors are encountered so far, a Seek command
is executed. The Seek Complete line is sampled. If
the Seek Complete line does not go true within 128
Index pulses, the Aborted command bit in the Error
Register is set, the Error bit in the Status Register is
set, and a normal completion is simulated.
After all data has been sent to the sector buffer, the
Busy bit in the Status Register is set. The state of
Seek Complete, Ready and Write Fault are sampled,
and if an error condition exists, the Aborted command bit in the Error Register is set, the Error bit in
the Status Register is set, an Interrupt is generated
and the Busy bit is reset.
Once the head has settled over the desired cylinder,
the WD100'l will attempt to read the sector. The
WD1001 performs all retries necessary to recover the
data during the read command. The controller attempts to read the desired sector up to 16 times. It
will attempt a retry if it does not find an ID, if the ID of
that sector has a bad CRC or if the Data Address
Mark (DAM) couldn't be found or even if the data was
actually read from the disk but incurred an uncorrectable error.
If no errors are encountered so far, a Seek command
is executed. The Seek Complete line is sampled. If
the Seek Complete line doesn't go true within 128
Index pulses, then the Aborted command bit in the
Error Register i~ set, the Error bit in the Status
Register is set, an Interrupt is generated and the
Busy bit is reset.
Every time the controller encounters an error, it records the occurrence of that error in an internal register. If, after 16 retries, the controller was not able to
get a match on the ID field, it assumes that the head
was possibly mis-positioned and executes an autorestore. During the auto-restore, the stepping rate is
implied to be equal to the Seek Complete period.
After the auto-restore has been successfully completed, the controller re-seeks and attempts to read
the sector once again. An auto-restore will be performed only once per read or write sector command.
Once the head has settled over the desired cylinder,
it will attempt to read the ID of the sector. The
WD1oo1 performs all retries necessary to recover the
ID during the write command. The controller attempts to read the ID of the desired sector up to 16
times. It will attempt a retry if it doesn't find an ID or if
the ID of that sector has a bad CRC.
If the WD1001 encounters an ECC error, it will attempt to correct the data in its sector buffer. If it can
correct the data, the Corrected bit in the Status
register will be set, if not, the Uncorrectable Error bit
is set.
Every time the controller encounters an error, it
records the occurrence of that error in an internal
register. If, after 16 retries, the controller was not able
to get a match on the ID field, it assumes that the
head was possibly mis-positioned and executes an
auto-restore. During the auto-restore, the step~ing
rate is implied to be equal to the Seek Comp ete
period. After the auto-restore has been successfully
completed, the controller re-seeks and attempts to
write the sector once again.
If the controller encounters a non-recoverable error,
the controller examines its internal error history
register. It then sets the bit in the Error Register of
the highest severity error incurred. If the Uncorrectable bit is set, the data that last produced that
27
If the controller encounters a non-recoverable error,
the controller examines its internal error history
register. It then sets the bit in the Error Register of
the highest severity error incurred. The Error bit in the
Status Register is set, an Interrupt is generated and
the Busy bit is reset.
After all data has been sent to the buffer, the Busy bit
in the Status Register is set. The state of Seek
Complete, Ready and Write Fault lines are sampled.
If an error condition exists, the Aborted command bit
in the Error Register is set, the Error bit in the Status
Register is set, an interrupt is generated and the
Busy bit is reset.
If the proper sector is located, the sector buffer is
written to the disk, an interrupt is generated and the
Busy bit is reset.
WRITE LONG
This variation of the write command allows the user
to introduce various error patterns to check correction capability. The check bits follow the data in the
sector buffer. This increases the effective buffer
length by four bytes.
If no errors are encountered so far, a Seek command
is executed. No verification of track positioning
accuracy is performed because the track may not
have any 10 fields present. After the Seek operation
has been performed, the seek Complete line is
sampled. If the Seek Complete line is not asserted
within 128 Index pulses, the Aborted command bit in
the Error Register is set, an Interrupt is generated and
the Busy bit is reset.
FORMAT TRACK
The Format command is used for initializing the 10
and data fields on a particular disk. Upon receipt of
the Format command, the controller generates ORQs
for each byte of the interleave table to be written to
the buffer. In all cases, the number of bytes transferred to the buffer must correspond to the current
sector size.
Once the head has settled over the desired cylinder,
the controller starts writing a pattern of 4E's until the
index is encountered. Once the index is found, a
number of 10 fields and nulled data fields are written
to the disk. The number of sectors written is equal to
the contents of the Sector Count Register. As each
sector is written, the Sector Count Register is
decremented, and consequently, must be updated
before each format operation.
,
/'
\GAP
(4~)
J
GAP3 14 BYTES (A1)
(4E)
(¢l¢l)
UH
(IDENT) CYL SH
LOW
t
12
SEC CRC 3B BYTES (A1) (F8) DATA ECC 3 BYTES
(¢l¢l)
-2- (¢l¢l) (¢l¢l)
FIELD -4-
-
~.--
~':
ID FIELD------
I
WRITE GATE _____
NOTE:
1) When MSB of head byte
1, bad block is detected.
2) Write Gate turn-on is 3 bytes after the ID field's CRC bytes.
3) Write Gate turn-off is 3 bytes after the Data Field's ECC or
CRC bytes.
4) 12 bytes of zeroes are re-written on a Data Field update.
5) The 2 LSB's of the IDENT byte are used for Cylinder high
These values are:
FE = 0 to 255 cylinders
FF
256 to 511 cylinders
FC = 512 to 767 cylinders
FD
768 to 1023 cylinders
6) GAP 3 values are:
=
=
=
SECTOR LENGTH
128
256
512
GAP3
15
15
30
28
LDATA FIELD-
I
I
~I-------------iL..-_ _
I
200 nS. MIN. INDEX PULSE
I
I
After the last sector is written, the controller backnils the track with 4E's. When the next index pulse
after the last sector is written is encountered, the format operation is terminated, an Interrupt is generated
and the Busy bit is reset.
SETTING UP TASK FILES
Before any of the five commands may be executed, a
set of parameter registers called the Task File must
be set up. For most commands, this informs the
WD1001 of the exact location on the disk that the
transfer should take place. For a normal read or write
sector operation, the Sector Number, the SizelDrive/
Head, Cylinder Number, and Command registers
(usually in that order) will be written.
Note that most of these registers are readable as well
as writable. These registers normally are not read
from, but this feature is provided so that error reporting routines can determine physically where an error
occurred without recalculating the sector, head and
c:yl i nder parameters.
Since the WD1001 can recall all the Task File
parameters sent to it, it is recommended that Task
File parameters be stored in the WD1001 as they are
calculated. This will save the programmer a few
instructions by not maintaining two copies of the
same information.
SOH REGISTER
BIT
7
FUNCTION
Sec
Ext
6 5
Sec
Size
WE
Deselected
Data Register
Write Precomp
Sector Count
Sector Number
Cyl i nder Low
Cylinder High
SizelDrive/head
Command
Register
4 3
Drive
Select
BIT 5
0
1
1
SECTOR SIZE
256 Bytes
512 Bytes
128 Bytes
BIT 4
0
0
1
1
BIT 3
0
1
0
1
DRIVE SELECTED
Drive Sel 0
Drive Sel1
Drive Sel 2
Drive Sel3
BIT 2
0
0
0
0
1
1
1
1
BIT 1
0
0
1
1
0
0
1
1
BIT
7
6
5
4
3
2
1
0
Since most hard disk drives contain more than one
head per positioner, it is more efficient to step the
FlIW head assemblies of most disk drives by cylinders, not tracks. In other words, the disk driver
software should be designed to read or write all data
that is directly accessible by all the heads on a
positioner before stepping to a new cylinder.
REGISTER SELECTION ARRAY
CS A2 A1 AO RE
1 X X X Deselected
0 0 0 0 Data Register
0 0 0 1 Error Register
0 0 1 0 Sector Count
0 0 1 1 Sector Number
0 1 0 0 Cylinder Low
0 1 0 1 Cylinder High
0 1 1 0 SizelDrive/head
0 1 1 1 Status Register
BIT 6
0
0
1
BIT 0
0
1
0
1
0
1
0
1
--
HEAD SELECTED
Head 0
Head 1
Head 2
Head 3
Head 4
Head 5
Head 6
Head 7
STATUS AND ERROR REGISTER BITS
STATUS REGISTER
ERROR REGISTER
Busy
Bad Block Detect
Ready
Uncorrectable
Write Fault
CRC Error - ID Field
ID Not Found
Seek Complete
Data Request
Corrected
Aborted Command
TROOO Error
Error
DAM not found
PROGRAMMING
Users familiar with floppy disk systems will find
programming the WD1001 a pleasant surprise. A
substantial amount of intelligence that was
required by the host computer has been incorporated into the WD1001. The WD1001 performs
all needed retries, even on data ECC and head
positioning errors. Most commands feature
automatic 'implied' seek which means that seek
commands need not be issued to perform basic
read/write functions. The WD1001 keeps track of
the position of up to four read/write head
assemblies, so the host system does not have to
maintain track tables. All transfers to and from the
disk are through an on-board full sector buffer. This
means that data transfers are fully interruptable and
can take place at any speed that is convenient to
the system designer. In the event of an
unrecoverable error, the WD1001 simulates a
normal completion so that special error recovery
software is not needed.
2
1 0
Head
Select
SECTOR EXTENSION
Selects CRC for data field
Selects ECC for data field
See page 725 for ordering information .
•
29
~
C
.....
o
o.....
=E
c.....
o
o.....
This is a preliminary specification with tentative device parameters and may be subject to change after final product characterization is completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
30
P"nted," USA
WESTERN DIGITAL
c
o
R
P
0
R
A
T
/
o
N
WD1002 Winchester Disk Controller
FEATURES
• SINGLE 5V SUPPLY
• FLOPPY DISK BACKUP
• ECC/CRC
• ST506 OR SA1000 INTERFACE
• COMPACT SIZE
• SECTOR SIZES TO 1024
• DATA RATES TO 5MBS
• AUTOMATIC FORMATTING
• . WD1000 COMPATIBILITY
GENERAL DESCRIPTION
The WD1002 is next generation of Winchester
Controllers. It utilizes the WD1010 Winchester
controller chip, and provides for floppy disk back up
using the WD279X series of single chip floppy
controllers.
Incorporated in this controller is all the circuitry
needed for Hard disk control with floppy backup.
The firmware is incorporated in the WD1010 and the
controller is compatible with previous WD1000 and
WD1001. Additional software is needed for the floppy
disk backup. Users of the WD1 000/WD1 001 need not
use the floppy controller.
See page 725 for ordering information .
•
31
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility Is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
32
PonIed In U.S.A
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
WD1100 Series Winchester Controller Chips
DESCRIPTION
FEATURES
The WD1100 Chip series provides a low cost alternative for
developing a Winchester Controller. These devices have
been designed to read and convert an MFM data stream
into 8-bit parallel bytes. During a write operation, parallel
data Is converted back into MFM to be written on the disk.
Address Marks are generated and detected while CRC
bytes can be appended and checked on the data stream.
The WD1100 is fabricated in N-channel silicon gate technology and is available in a 20-pin Dual-In-Line package.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
WD11()()'01
WD11()()'02
WD11()()'12
WD11()()'03
WD11()()'04
WD11()()'05
WD11()()'06
WD1100-07
WD11()()'09
APPLICATIONS
Winchester Controllers For:
•
•
•
•
•
•
•
SERIPARALLEL CONVERTER
MFM GENERATOR
IMPROVED MFM GENERATOR
AM DETECTOR
CRC GENERATORICHECKER
PARISERIAL CONVERTER
ECC/CRC LOGIC
HOST INTERFACE LOGIC
DATA SEPARATION SUPPORT LOGIC
Vee
CLK
EN
NC
jijRz
AO
SHUGART ASSOCIATES
SEAGATE TECHNOLOGY
QUANTUM CORP.
TANDON MAGNETICS
MINISCRIBE
RMS
CMI ... AND OTHERS
Vee
NRZ
Vee
SKPEN
SA1000/ST506 COMPATIBLE
SINGLE 5V SUPPLY
TRI-STATE DATA LINES
5 MBITS/SEC TRANSFER RATE
SIMPLIFIED INTERCONNECT
SKPEN
AO
EiCL'R
NAZ
WCLK
A1
WCLK
A1
TEsT
ST
WcL'K
MR
wm<
~
DOO
DOUT
RWC
MFM
AWC
cs
iN'i'RO
MFM
~
DiN
ACLK
~
NC
AMDET
NC
OOUT
SHFciJ<.
D03
D07
iN'i'CL'K
EARLY
i'ES'f1
D04
D06
NC
LATE
2XDR
LATE
ENDET
Vss
D05
Vss
NOM
Vss
NOM
Vss
iN'fCIJ(
EAALY
AMDET
i5RQ
BDONE
DRQCLK
NC
DOUT
D01
DAO
CP
CLKIN
D02
i5ROc[R
Vee
FiST
ACLK
NC
DCLK
TEST 2
WD1100-01
WD1100-02
WD1100-12
WD1100-03
SERIAUPARALLEL
CONVERTER
MFM GENERATOR
IMPROVED MFM GENERATOR
AM DETECTOR
Vec
DO
Vee
A/iN
VCC
DOCK
NC
D1
EN
RCP
~
SHFciJ<.
NC
D2
NC
WCP
RBS
~
~
NC
NC
D3
TEST
DCSS
CSAEN
WAE1iI
NC
CFi'Cci'K
D4
BDONE
EDOUT
AMDET
MODE
ewE
TIMCLK
D5
DOUT
!mD'F
TIMCLK
DOCE
WCLK
D6
SHFCLK
R'Ern
.nmTI'f
CR6Ti
CACOK
D7
ill
DiN
SKPCLK
NC
00uT
vss
ADAT
iiViSAf
SEL
m56
Vee
WA6
WCLK
ECCIZ
FBD
ACLK
NC
~
SHFCLK
WCLK
ECCEN
vss
i5CLi<
vss
iNl5EX
CSAC
BS
~
WA1T
fiiiijCp
vss
LINDEX
WD1100-04
WD1100-05
WD1100-06
WD1100-07
CRC GENERATOR/CHECKER
PARALLEUSERIAL
CONVERTER
ECC/CRC
LOGIC
HOST INTERFACE
LOGIC
33
+
.015
MIN
1.020
f.4-.. ---MAX~l
.100MA)<~..I...+
t
~
.100 TYP-...I
uuuu
~ ~ ~
'L .
I.--.j
.:~~
U
[T12OMIN
m.s
- leT
.055 -J I -
.310
MAX
.155 MAX
1
F:1
1...
1.040
i
.015 MIN
_
I
.320
I
~wmwvw t~~~
t=j
325.. 1
.100TYP-J
.021
20 lEAD CERAMIC "U"
r--"
~~Ij..- fs~~1 .
.. ...
.014
.021
«-
-J :~~% ~
20 LEAD PLASTIC 'V"
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
34
Printed 1M U.S.A
Western Digital
WD1100-01 Serial/Parallel Converter
~
C
.....
.....
8
IDESCRIPTION
The WD1100-01 is implemented in NMOS silicon gate
technology and is available in a 20 pin plastic or ceramic
dual-in-line package.
The WD11()()-01 Serial/Parallel Converter allows the user to
convert NRZ (non-return to zero) data from a Winchester
disk drive into a bit parallel form. Additional inputs are provided to signal the start of the parallel process, as well as
Byte Strobes to signify the end of the conversion. The
device contains two sets of a-bit registers; one register may
be read (in parallel), while data is being shifted into the
other register. This double-buffering allows the Host to read
data from the disk drive at one-eighth the actual data rate.
FEATURES
• SINGLE + 5V SUPPLY
• DOUBLE BUFFERING
• BYTE STROBE OUTPUTS
• 5MBITS/SEC SHIFT RATE
• SERIAL IN/SERIAL-PARALLEL OUT
• 20 PIN DIP PACKAGE
Sf
+5V
S
TEST
8
Bit
Counter
a
BOONE
EN
cp
BClR
elK
20
Vee
NC
19
EN
BClR
18
NRZ
TEST
17
ST
000
16
OOUT
001
15
BOONE
OOUT
NRZ
8 Bit
Shift Register
elK
002
14
SHFClK
003
13
007
004
12
006
VSS
11
005
cp
8 Bit Register
000 001 002 003 004 005 006 007
WD1100-01
Figure 2. Block Diagrams
WD1100-01
Figure 1. Pin Connections
35
SHFClK
PIN
NUMBER
1
2
SYMBOL
FUNCTION
NAME
NRZ data is entered into the 8-bit shift register on the lowto-high transition of clock.
ClK
CLOCK
NC
NO CONNECTION
No connection. This pin is to be left open by the user.
BYTE CLEAR
When this line is at a logic 0, the BDONE (Pin 15) line is held
reset.
3
BClR
4
TEST
TEST INPUT
This pin must be left open by the user.
000-007
DATAO-DATA7
8 bit parallel data outputs.
10
VSS
GROUND
Ground.
14
SHFClK
SHIFT CLOCK
Inverted copy of CLOCK (pin 1) which is active when EN
(pin 19) is at a logic 1.
15
BDONE
BYTE DONE
This signal is forced to a logic 1 signifying 8 bits of data
have been assembled. BDONE remains in a logic 1 state
until reset by a logic 0 on the BClR (pin 3) line.
16
DOUT
DATA OUT
Serial Data Output from the 8th stage of the internal shift
register. DOUT is in a high impedance state whenever EN
(pin 19) is at a logic O.
17
ST
START
This line enables the byte counter and is used for synchronization. It must be held to a logic 1 prior to first data
bit on the NRZ (Pin 18) line.
18
NRZ
NRZDATA
NRZ serial data is entered on this pin and clocked by the
low to high transition of ClK (pin 1).
19
EN
ENABLE
When this signal is at a logic 0, DOUT, SHFClK, and
BDONE outputs are in a high impedance state.
20
VCC
VCC
+ 5V
5-9,
11-13
--
DEVICE DESCRIPTION
Prior to shifting data through the device, the WD1100-01
must be synchronized to the data stream. The ST line (Pin
17 high) is used to hold the internal bit counter in a cleared
state until valid data (NRZ) and clocks (ClK) are entered.
The Sf line is a synchronous input and therefore requires
one full cycle of the ClK line (Pin 1) to occur in order to accept a ST condition. After this happens, the device is ready
to perform serial to parallel conversions.
Data is entered on the NRZ line and clocked into the 8-bit
shift register on the low-te-high transition of ClK. The ST
line must be set low during the low time of ClK. Data is accepted on low-to-high transition of the clock while the highto-low transition of ClK increments the bit counter. After 8
data bits have been entered the final high-to-Iow transition
of ClK sets an internal latch tied to the BDONE line (Pin
15). At the same time, the contents of the shift register are
parallel loaded into an 8 bit register making the parallel data
available on the DOO-D07 outputs. BDONE will remain in a
latched state until the BClR is set to a logic 0, clearing off
the BDONE signal. BClR is a level triggered input and
must be set back to a logic 1 before the next 8 bits are
shifted through the register. BClR has no effect on the
serial shifting process. When the next 8 bits are received,
BDONE will again be set and the operation continues.
± 10% power supply input.
._-
When interfacing to a microprocessor, BDONE is used to
indicate a parallel byte is ready to be read. As the processor
reads the data out of the DOO-D07 lines, the BClR line
should be strobed to clear off BDONE in anticipation of the
next assembled byte. An address decode signal generated
at the host may be used for this purpose. During a powerup condition, the state of BDONE is indeterminant. It is
recommended that BClR be strobed low after power-up to
insure that BDONE is cleared.
The serial output line from the last stage of the shift
register is available on the DOUT pin. An inverted copy of
ClK is available on the SHFClK pin. Both DOUT (Pin 16)
and SHFClK (Pin 14) can be used to drive another shift
register external to the device.
The three signals BDONE, DOUT, and SHFClK can be
placed in a high impedance state by setting EN (Pin
19) to a logic O. Likewise, EN must be at a logic 1 in
order for these signals to be active.
The TEST pin is internally OR'ed with the ST line to inhibit
the bit counter. It is recommended that TEST be left open
by the user. An internal pull-up resistor is tied to this pin to
satisfy the appropriate logic level required internally for
proper device operation.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias ........... O°C to 50°C
Voltage on any pin
with respect to VSS .................. - 0.2V to + 7.0V
Power Dissipation ............................ 1 Watt
STORAGE TEMPERATURE
PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . - 55°C to + 125°C
CERAMIC ........................ - 55°C to + 150°C
DC Electrical Characteristics TA
Vil
= O°C to 50°C; VCC = + 5V ±
PARAMETER
SYMBOL
-0.2
2.0
VIH
Input High Voltage
Vo
Output low Voltage
VOH
Output High Voltage
2.4
VCC
Supply Voltage
4.5
ICC
Supply Current
MAX
UNIT
CONDITION
0.8
V
0.4
V
IOl = 3.2mA
V
IOH = -200J.lA
V
5.5
V
100
mA
5.0
All Outputs Open
= 0° to 50°C, VCC = 5V ± 10%, VSS = OV
PARAMETER
SYMBOL.
= OV
10%, VSS
Typl
MIN
Input low Voltage
AC Electrical Characteristics TA
NOTE: Maximum ratings indicate operation where permanent device damage may occur. Continuous operations at these limits is not intended and should be
limited to those conditions specified in the DC
electrical characteristics.
Typl
MIN
MAX
UNITS
5.25
MHZ
fCl
ClK FREQUENCY
0
tlS
~ClK toST
0
nsec
tHS
t ClK toST
0
nsec
tDS
Data set-up to t ClK
15
nsec
tVB
BDONE valid from t ClK
65
tRS
BDONE reset from BClR
tBW
BClR Pulse Width
CONDITION
= 1 (min 2oonsec)
ST = 1 (min 2oonsec)
ST
110
nsec
EN
110
nsec
EN
nsec
EN
50
tsc
t ClK to ~ SH FClK
90
nsec
EN
tcs
~
ClK to t SHFClK
100
nsec
EN
tSD
Data delay from t SHFClK
55
nsec
EN
tFO
Enable to DOUT ACTIVE
90
nsec
tDH
Data Hold w.r.t. t ClK
NOTES: 1. Typical Values are forTA
nsec
25
= 25°CandVcc = +5.0V
37
=1
=1
=1
=1
=1
=1
:ec
...a.
...a.
8
:ec
ClK
8
NRZ
ST
.....
.....
JuVulSLfLfuVlILJ~
t §....: : t~~s
: ,:~~OH l::, _',I
-----11
tD~
I
1
::
:
i
! . ,,1__...,-__...,-__...,---...
l
L
fel
1
____ ,:
I
4--
I
___
. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
!
I
OOX
byte 1 or n
BOONE -~
BClR
------------U: --
lAS
__ : l~w
,
--I
OOUT
~~~~X~_-_~~I\_~, '------' '--.-J'--.-J'--.-J'--.-J'----''---.-J'--..-J'-----''----''
----=r--------I
EN
!.!fo
.--~-.---------.
WD11()()'01
Figure 3.
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
38
Western Digital
WD1100-02 MFM Generator
~
C
.....
.....
8
DESCRIPTIONI
The WD11()()..Q2 is fabricated in NMOS silicon gate
technology and is available in a 20 pin plastic or ceramic
dual·ln-line package.
The WD11()()"02 MFM Generator converts NRZ data into an
MFM (Modified Frequency Modulated) data stream. The
derived MFM signal containing both clocks and data can
then be used to record information on a Winchester Disk
Drive utilizing this recording technique. In addition to an
MFM output, the device generates first level Write
Precompensation signals for use with inner track densities.
A unique feature of the WD11()()"02 is the ability to delete a
clock pulse in the outgoing MFM stream in order to record
Address Marks.
FEATURES
•
•
•
•
•
SINGLE + 5V SUPPLY
·5 M BIT/SEC DATA RATE
WRITE PRECOMPENSATION
ADDRESS MARK GENERATION
20 PIN DIP PACKAGE
RWC
I
-
E
4 BIT
SHIFT
REG.
WCLK
NRZ
WRITE
PRECOMP
GEN.
MFM GEN
I
vCC
SKPEN
AO
WCLK
A1
WcLK
MR
IE "SKIP"
LOGIC
SKPEN
I
MFM
RWC
cs
1
WD1100-02
Figure 2. Block Diagram MFM Generator
iNTRQ
000'
DRCiCtK
iNi'C'IT<
EARLY
NC
LATE
vSS
NOM
AO
A1
_~J'----""
DECODE
l.OGIC
WD1100-02
WD1100-02
Figure 1. Pin Connections
Figure 3. Block Diagram Interrupt Control Logic
•
39
EARLY
NOM
LATE
MFM
~
PIN
NUMBER
c
.....
.....
8
SYMBOL
NRZ
FUNCTION
NAME
NON-RETURN-TO
ZERO
NRZ data input that is strobed into the MFM generator by
WCLK(~).
2
SKPEN
SKIP ENABLE
This input arms the SKIP logic for recording Address Marks
when set to a logic 1.
3
WCLK
WRITE CLOCK
4
WCIT<
WRITE CLOCK
Complimentary clock inputs. NRz data is clocked into the
MFM Generator on the high-to-Iow transition of
WCLK (pin 3).
5
RWC
REDUCED WRITE
CURRENT
This signal when high, enables EARLY, LATE and NOM
outputs.
9
NC
No Connection
No Connection.
10
VSS
VSS
Ground.
11
NOM
NOMINAL
Output signal from the Write Precompensation Logic used
to signify that data is to be written nominal.
12
LATE
LATE
Output signal from the Write Precompensatlon Logic used
to signify that data is to be shifted LATE before writing.
13
EARLY
EARLY
Output signal from the Write Precompensation Logic used
to signify that data Is to be shifted EARLY before writing.
16
MFM
MFM DATA
This output contains the MFM encoded data derived from
the NRZ (pin 1) line.
6
CHIP SELECT
Low input Signal used to enable the Address decode logiC.
8
INTERRUPT
REQUEST CLOCK
A high-te-Iow transition on this line will latch the
INTRQ (pin 15) at a logic O.
DATA REQUEST
A high-to-Iow transition on this line will latch the DRQ (pin
14) at a logic O.
15
INTERRUPT
REQUEST
This output is latched at a logic 0 when INTCLK (pin 8)
makes a high-to-Iow transition while the decode logic is
disabled.
14
DATA REQUEST
This output is latched at a logic 0 when DRQCLK (pin 7)
makes a high·te-Iow transition while the decode logiC is
disabled.
17
MASTER RESET
A low level on this line causes DRQ and INTRQ to set at a
logic 1.
7
CI:OcK
18,19
Ao.A1
ADDRESS 1,0
When CS is low and the address lines are high, INTRQ is
cleared; if the address lines are low then DRQ gets cleared.
(i.e. set at a logic 1).
20
VCC
VCC
+5V ±10% power supply input.
DEVICE DESCRIPTION
The WD1100-02 is divided into two sections: MFM
Generator and Interrupt Logic. The MFM Generator converts NRZ data into MFM data and provides Write
Precompensation signals. The Interrupt Logic is used
specifically on the WD1000 Winchester Controller Board
and may be used in similar designs to generate Interrupt
signals. The two sections of the device are isolated and
have no common input or output signals.
Prior to entering data, the SKPEN line must be set to a logic
o to enable only clocks in the data stream. Data Is entered
on the NRZ line and strobed on the high·to-Iow transition of
WCLK. The encoded NRZ data appears on the MFM (pin 16)
output lagging by one clock cycle.
Write Precompensation signals EARLY, LATE, and NOM are
generated as each data or clock pulse becomes available at
the input when RWC is logic 1. The algorithm used is on
PageS.
40
---
LAST DATA SENT
SENDING
TO BE SENT
NEXT
EARLY
LATE
NOM
1
0
H
L
L
X
1
X
0
1
1
L
H
L
0
0
0
1
H
L
L
1
0
0
0
L
H
L
L
L
H
ANY OTHER PATIERN
DEVICE DESCRIPTION (CONTINUED)
The SKPEN signal is used to record a unique data/clock
pattern as an Address Mark, using A1 16 data with OA 16
clock. This pattern is used for synchronization prior to data
or 10 fields that are read from the disk.
When the SKPEN signal is set to a logic 1, the internal skip
logic is enabled. As long as zeroes are being shifted into
the NRZ line, the device generates normal MFM data. On
receipt of the first non-zero bit (typically the MSB of the
A 116 the skip logic begins to count WCLK cycles. When the
MFM generator tries to produce a clock between data bits 2
and 3, the skip logic disables the MFM generator during
that time. The result for A 116 data is a clock pattern of OA 16
instead of OE 16' Although other data patterns may be used,
the MSB of the pattern must be a 1 (8016 or higher) in order
to enable the skip logic at the proper time. After the skip
logic has performed, it then disables itself and MFM data
is recorded normally starting with the succeeding byte.
To re-enable the skip logic again, the SKPEN line must be
strobed.
MR
A1
Ao
CS
DRQ
INTRQ
0
X
X
X
H
H
1
X
X
1
ON
ON
1
0
0
0
H
ON
1
1
1
0
ON
H
1
1
0
0
ON
ON
1
0
1
0
ON
ON
X
= Don't care
ON
= remains at previous state
ORO and INTRO can be set to a logic 0 only on the high-to·
low transition of OROCLK and INTCLK respectively. The
signal will remain at a logic 0 until cleared by a MR or pro·
per address selection via CS, A1, and Ao.
The Interrupt Logic is used to clear Data Requests (ORO)
and Interrupt Requests (INTRO) by selecting CS (pin 6) in
combination with Ao and A 1• The MR (Master Reset) signal
is used to clear both i5FiQ and INRO simultaneously.
41
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias ............ O°c to 50 °c
Voltage on any pin with respect to VSS .. - 0.2V to + 7.0V
Power Dissipation ............................ 1 Watt
STORAGE TEMPERATURE:
PLASTIC ......................... - 55°C to
CERAMIC ........................ - 55°C to
DC Electrical Characteristics T A
SYMBOL
+ 125°C
+ 150 °c
= O°C to 50°C, VCC = + 5V
PARAMETER
Input Low Voltage
-0.2
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
VOC
Supply Voltage
4.5
ICC
Supply Current
SYMBOL
± 10%, VSS
TYp1
MIN
VIL
AC Electrical Characteristics T A
NOTE: Maximum ratings indicate operation when permanent device damage may occur. Continuous operation at these limits is not intended and should be
limited to those conditions specified in the DC Electrical Characteristics.
MAX
UNIT
0.8
V
0.4
5.0
I
WCLK FREQUENCY
tDS
Data Setup w.r.t. +WCLK
10
25
10%; VSS
TYp1
MIN
twc
CONDITION
V
= O°C to 50°C; VCC = + 5V ±
PARAMETER
= OV
V
IOL = 3.2mA
V
IOH = -2oo~A
5.5
V
100
mA
All outputs open
= OV
MAX
UNIT
5.25
MHZ
CONDITION
nsec
tDH
Data hold w.r.t. +WCLK
tMF
t WCLK to t MFM delay
160
nsec
nsec
Pin 1 LOW
tFM
+ WCLK to + M FM delay
180
nsec
twN
Data delay to NOM from
+WCLK
190
nsec
tWE
Data delay to EARLY from
+WCLK
180
nsec
Pin4
= LOW
tWL
Data delay to LATE from
-I-WCLK
180
nsec
Pin4
= LOW
tMR
Master reset pulse width
tMD
-I-MRtot DRQ
nsec
50
150
42
nsec
Pin 1 LOW
I
Pin4 = LOW
SYMBOL
PARAMETER
Typl
MIN
MAX
UNIT
tMI
+MR to t INTRO
too
OROCLK pulse width
50
tlO
INTCLK pulse width
50
too
.j. OROCLK to ORO
120
nsec
til
.j.INTCLK to INTRO
120
nsec
tAD
.j.AXtotORO
145
nsec
tAl
t AX to t INTRO
160
nsec
tco
J.CStot ORO
145
nsec
tCI
.j. CS to t INTRO
180
nsec
tRN
tRWC to +NOM
115
nsec
150
nsec
nsec
nsec
NOTES: 1. TypicalValuesareforTA = 25°CandVcc = +5.0V.
3
4
I
NRZ
6
7
;
I
0
---+-----1
,
MFM
5
~
:~:
i
L___--'
WCLK
r-"LFLJDlSl
1
tWE_i
:__
EARLY----------~!~~-------~------~fclh----I
NOM
LATE
!
:
~
tWN--J
:--
,
--i
~ tWL
____________~:-----------~l---'~~
tRN_:
r--
Ir' ~---------------------------------
------------~
WD1100·02
Figure 4. M FM Generator Timing
-\tMRI __
CSorAX~ ___
MR~---
_,,_t MD
tc~I~ __ -
OR~---
_, _IMI
ORQ
-..J ,..-Ici
wma-~---
INTR~---
WD'1100·02
Figure 6
WD1100·02
Figure 5
--11 10 i -
~iIDOI-
INTCL~
ORQCL~
INTRQ-~-t"
ORQ~
WD1100·02
Figure 8.
WD1100·02
Figure 7.
See page 725 for ordering information.
43
CONDITION
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
44
Printed on U.S.A
Western Digital
WD1100-12 Improved MFM Generator
DESCRIPTION
The WD1100-12 improved MFM Generator converts NRZ
data into an MFM (Modified Frequency Modulated) data
stream_ The derived MFM signal containing poth clocks
and data can then be used to record information on a
Winchester Disk Drive utilizing this recording technique. In
addition to an MFM output, the device generates first level
Write Precompensation signals for use with inner track
densities. A unique feature of the WD1100-12 is the ability
to delete a clock pulse in the outgoing MFM stream in
order to record Address Marks.
The WD1100-12 is fabricated in NMOS silicon gate
technology and is available in a 20 pin plastic or ceramic
dual-in-line package.
FEATURES
SINGLE + 5V SUPPLY
5 M SIT/SEC DATA RATE
WRITE PRECOMPENSATION
ADDRESS MARK GENERATION
•
•
•
•
RWC .____---------------,
4 BIT
WCLK ._-----CJ SHIFT
REG.
WRITE
PRECOMP
GEN.
EARLY
NOM
LATE
MFM
VCC
AO
WCLK
WCCR
RWe
CS
2XDR
VSS
A1
MR
MFM
INTRQ
DRQ
EARLY
LATE
NOM
SKPEN----------~
WD1100·12
• Figure 2. Block Diagram MFM Generator
DRQCLK ~------------------~
~----------------~----I-AO
A1
cs
DECODE
LOGIC
MR~----------------
WD1100·12
Figure 1. Pin Connections
__--~
WD1100·12
Figure 3. Block Diagram Interrupt Control Logic
45
~
....c
....
o
o
PIN
NUMBER
SYMBOL
FUNCTION
NAME
1
NRZ
NON-RETURN-TO
ZERO
NRZ data input that is strobed into the MFM generator by
WCLK(~) .
2
SKPEN
SKIP ENABLE
This input arms the SKIP logic for recording Address Marks
when set to a logic 1.
3
WCLK
WRITE CLOCK
4
WCLK
WRITE CLOCK
Complimentary clock inputs. NRZ data is clocked into the
MFM Generator on the high-to-Iow transition of WCLK
(pin 3).
5
RWC
REDUCED WRITE
CURRENT
This signal when high, enables EARLY, LATE and NOM
outputs.
9
2XDR
2TIMES
DATA RATE
This input is used to latch EARLY, LATE, NOM and MFM
outputs.
10
VSS
VSS
Ground.
11
NOM
NOMINAL
Output signal from the Write Precompensation Logic used
to signify that data is to be written nominal.
12
LATE
LATE
Output signal from the Write Precompensation Logic used
to signify that data is to be shifted LATE before writing.
13
EARLY
EARLY
Output signal from the Write Precompensation Logic used
to signify that data is to be shifted EARLY before writing.
16
MFM
MFM DATA
This output contains the MFM encoded data derived from
the NRZ(pin 1) line.
6
CS
CHIP SELECT
Low input signal used to enable the Address decode logic.
8
INTCLK
INTERRUPT
REQUEST CLOCK
A low on this line will latch the INTRQ (pin 15) at a logic o.
7
DRQCLK
DATA REQUEST
CLOCK
A low on this line will latch the DRQ (pin 14) at a logic o.
15
INTRQ
INTERRUPT
REQUEST
This output is latched at a logic 0 when INTCLK (pin 8)
goesl is low.
14
DRQ
DATA REQUEST
This output is latched at a logic 0 when DRQCLK (pin 7)
goes/is low.
17
MR
MASTER RESET
A low level on this line causes DRQ and INTRQ to set at a
logic 1.
18, 19
AO.A1
ADDRESS 0, 1
When CS is low and the address lines go high, INTRQ is
cleared; if the address lines go low then DRQ gets cleared.
(Le. set at a logic 1).
20
VCC
VCC
+ 5V ± 10% power supply input.
DEVICE DESCRIPTION
The WD11OQ-12 is divided into two sections: MFM
Generator and Interrupt Logic. The MFM Generator converts NRZ data into MFM data and provides Write
Precompensation Signals. Tl=le Interrupt Logic is used
specifically on the WD1000 Winchester Controller Board
and may be used in similar designs to generate Interrupt
signals. The two sections of the device are isolated and
have no common input or output signals.
Prior to entering data, the SKPEN line must be set to a logic
o to enable only clocks in the data stream. Data is entered
on the NRZ line and strobed on the high-to-Iow transition of
WCLK. The encoded NRZ data appears on the MFM (pin 16)
output lagging by one clock cycle.
Write Precompensation signals EARLY, LATE, and NOM
are generated as each data or clock pulse becomes
available at the input when RWC is logic 1. The algorithm
used is on Page 4.
46
LAST DATA SENT
SENDING
TOBESENT
NEXT
EARLY
LATE
NOM
X
1
1
0
H
L
L
X
0
1
1
L
H
L
0
0
0
1
H
L
L
1
0
0
0
L
H
L
L
L
H
ANY OTHER PATTERN
DEVICE DESCRIPTION (CONTINUED)
The SKPEN signal is used to record a unique data/clock
pattern as an Address Mark, using A 116 data with OA 16
clock. This pattern is used for synchronization prior to data
or ID fields that are read from the disk.
When the SKPEN signal is set to a logic 1, the internal skip
logic is enabled. As long as zeroes are being shifted into
the NRZ line, the device generates normal MFM data. On
receipt of the first non-zero bit (typically the MSB of the
A 116 the skip logic begins to count WCLK cycles. When the
MFM generator tries to produce a clock between data bits 2
and 3, the skip logic disables the MFM generator during
that time. The result for A 116 data is a clock pattern of OA 16
instead of OE 16. Although other data patterns may be used,
the MSB of the pattern must be a 1 (80 16 or higher) in order
to enable the skip logic at the proper time. After the skip
logic has performed, it then disables itself and MFM data
is recorded normally starting with the succeeding byte.
To re·enable the skip logic again, the SKPEN line must be
strobed.
X
MR
A1
Ao
CS
DRa
INTRa
0
X
X
X
H
H
1
X
X
1
ON
ON
1
0
0
0
H
ON
1
1
1
0
ON
H
1
1
0
0
ON
ON
1
0
1
0
ON
ON
= Don't care
ON = remains at previous state
DRO and INTRa can be set to a logic 0 only by a low level
or DROCLK and INTCLK respectively. The signal will
remain at a I~c 0 until cleared by a MR or proper address
selection via 08, A 1, and Ao.
The Interrupt Logic is used to clear Data Requests (DRO)
and Interrupt Requests (INTRa) by selecting CS (pin 6) in
combination with Ao and A 1 . The MR (Master Reset) signal
is used to clear both DRO and INRO simultaneously.
47
:e
C
::
8
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
NOTE: Maximum ratings indicate operation when permanent device damage may occur. Continuous
operation at these limits is not intended and should
be limited to those conditions specified in the DC
Electrical Characteristics.
Ambient Temperature under Bias ........... 0° C to 50° C
Voltage on any pin with respect to VSS ... - 0.2V to + 7.0V
Power Dissipation ............................ 1 Watt
STORAGE TEMPERATURE:
PLASTIC ......................... - 55°C to
CERAMIC ........................ - 55°C to
DC Electrical Characteristics TA
SYMBOL
VIL
+ 125°C
+ 150°C
= O°C to 50°C; VCC = + 5V
PARAMETER
-0.2
2.0
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
VCC
Supply Voltage
4.5
ICC
Supply Current
SYMBOL
TYp1
MIN
Input Low Voltage
AC Electrical Characteristics TA
± 10%; VSS
= OV
MAX
UNIT
0.8
V
0.4
V
CONDITION
V
V
5.0
5.5
V
100
mA
= 3.2mA
IOH = -200/AA
IOL
All outputs open
= O°C to 50°C; VCC = + 5V ± 10%; VSS = OV
PARAMETER
TYp1
MIN
MAX
UNIT
5.25
MHZ
CONDITION
tFR
WCLK FREQUENCY
tDS
Data Setup w.r.t. • WCLK
10
nsec
tDH
Data hold w.r.t. +WCLK
25
nsec
tMF
t WCLK to t MFM delay
210
nsec
Pin 1 LOW
tFM
+WCLK to. MFM delay
230
nsec
Pin 1 LOW
tWN
Data delay to NOM from
.WCLK
240
nsec
tWE
Data delay to EARLY from
+WCLK
230
nsec
tWL
Data delay to LATE from
+WCLK
230
nsec
tMR
Master reset pulse width
tMD
.MRtotDRQ
50
nsec
150
48
nsec
SYMBOL
PARAMETER
TYp1
MIN
tMI
~
too
OROCLK pulse width
50
50
MR to t INTRO
tlO
INTCLK pulse width
too
~
OROCLK to ORO
INTCLK to INTRO
til
~
tAO
~AX
MAX
UNIT
150
nsec
nsec
nsec
120
nsec
120
nsec
145
nsec
tAl
t AX to t INTRO
160
nsec
tco
~CS
145
nsec
tCI
~ CS to t INTRO
180
nsec
tRN
tRWCto~NOM
145
nsec
tTE
~
75
nsec
trN
~ 2XOR
to t NOM
75
nsec
tTL
~ 2XOR
to t LATE
75
nsec
tot ORO
tot ORO
2XOR to t EARLY
NOTES: 1. Typical Values are forTA
CONDITION
= 25°CandVcc = +5.0V.
WD11 00-12 Figure 4
MFM GENERATOR TIMING
.....................................................................
49
:e
c
.....
.....
8
-I t MRj4Ml!i ~--
CSor~ __
- ' :-- tMO
:
-~__ tMI
INTR02r---
tcoortAO--:
I5'm:}
ORO
INTRa
WD1100·12 Figure 5
--
--.:.r---
WD1100·12 Figure 6
--I too I-
-ItiO
I-
INTCL~
OROCLK~
ORO
I
- : :-tCI
--~
INTRa
- ' , t oo
WD1100·12 Figure 7
WD1100·12 Figure 8
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from Its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
50
Pronted on U.S.A
Western Digital
WD1100-03 AM Detector
=e
c
.....
.....
8
DESCRIPTION
The WD1100-03 Address Mark Detector provides an efficient means of detecting Address Mark Fields in an MFM
(NRZ) data stream. MFM (NRZ) clocks and data are fed to
the device along with a window clock generated by an external data separator. The WD1100-03 searches the data
stream for a DATA = A1, ClK = OA pattern and produces
an AM DET signal when the pattern has been found. NRZ
data is an output from the device, which can be used to
drive a serial/parallel converter. An uncommitted latch is
also provided for by the data separator circuitry, if required.
CP
RST
RCIK
Vee
i5iN'
RSr
RClK
eLKiN
FEATURES
•
•
•
•
•
SINGLE + 5V SUPPLY
5 MBITS/SEC DATA RATE
DECODES A 116-DA16
SYNCHRONOUS ClOCKIDATA OUTPUTS
20 PIN DIP PACKAGE
+5V:Q
:
DIN
NC
AMDET
NC
AMDET
NC
QOu'f
.
Q
D
000f
DOUT
B BIT
SHIFT REG
CP
DOUT
C
RClK
R
TEST 1
DClK
R
ENDET
i'ESf1
NC
ENDET
DClK
Vss
The WD1'IOO-03 Address Mark Detector is fabricated in
NMOS silicon gate technology and is available in a 20 pin
dual-in-line package.
DETECT A1
DETECT OA
AMDET
AMDET
TEST 2
TEST2
R
ClK IN
D
RClK
C
Q
BBIT
SHIFT REG
WD11()()'03
Figure 2. Block Diagr~m
WD1100-03
Figure 1. Pin Connections
•
51
I
:ec
........
o
o
I
PIN
NUMBER
SYMBOL
FUNCTION
NAME
1
3
RClK
RClK
READ CLOCK
READ CLOCK
Complimentary clock inputs used to clock DIN and ClK IN
into the AM detector.
2
DIN
DATA INPUT
MFM data pulses from the external Data Separator are connected on this line.
4
ClKIN
CLOCK INPUT
MFM clock pulses from the external Data Separator are
connected on this line.
5
DOUT
DATA OUTPUT
Data Output from the internal Data Shift register, synchronized with DClK.
NC
No Connection
To be left open by the user
8
11
TEST 1
TEST 2
TEST 1
TEST 2
To be left open by the user.
9
ENDET
ENABLE
DETECTION
A logic 1 on this line enables the detection logic to search
for a data A 116 and clock.
VSS
VSS
GROUND.
12
DClK
DATA CLOCK
Clock output that is synchronized with DATA OUT (Pin 5).
14
QOUT
lATCH OUTPUT
Signal output from the uncommitted latch.
15
AMDET
16
AMDET
ADDRESS MARK
DETECT
ADDRESS MARK
DETECT
Complimentary Address Mark Detector output. These
signals will go active when a Data = A1 16 Clock = OA 16
pattern is detected in the data stream.
18
CP
CLOCK PULSE
A low-to-high transition on this line will cause the QOUT
(Pin 14) to be latched at a logic O.
19
RST
RESET
A logic 0 on this line will cause the QOUT (Pin 14) signal to
be set at a logic 1.
20
VCC
VCC
+ 5V
6, 7, 13, 17
10
± 10% power supply input.
DEVICE DESCRIPTION
Prior to shifting data through the device, the internal logic
must be initialized. While the ENDET (Pin 9) line is at a logic
0, shifting of data will be inhibited and AMDET, AMDET,
ClK, and DATA OUT will remain inactive.
When an AM is detected, DClK will begin to toggle. Data
present on the DOUT line may then be clocked into an external serial/parallel converter. DClK will remain inactive
when ENDET is held at a logic O.
When ENDET is at a logic 1, shifting is enabled. NRZ data is
entered on the DIN line (Pin 2) and shifted on the high-tolow transition of RClK (Pin 1). NRZ clocks are entered on
the ClK IN line, and shifted on the high-to-Iow transition of
RClK (Pin 3)_ The DOUT line (Pin 5) is tied to the last stage
of the internal Data Shift register and will reflect information clocked into the DIN line delayed by 8 bits.
An uncommitted edge-triggered flip/flop has been provided
to facilitate the detection of high frequency by the data
separator, but may be used for any purpose_ The low-tohigh transition of CP (Pin 18) will set the QOUT (Pin 14) to a
logic O. QOUT may be reset back to a logic 1 by a low level
on the RST line (Pin 19).
TEST1 and TEST2 are output lines. TEST1 is an active low
pulse when an A1 16 is detected, and TEST2 is active low
pulse when a OA 16 is detected. These signals are
used for test points and therefore should be left open by
the user if not required.
While each bit is being shifted, a 16 bit comparator is continuously checking the parallel contents of the shift
registers for the DATA = A1 16, ClK = OA 16 pattern. When
this pattern is detected, AMDET will be set to a logic 0 and
AMDET will be set to a logic 1. AMDET and AMDETwili remain latched until the device is re-initialized by forcing
ENDET to a logic O.
52
SPECIFICATIONS
STORAGE TEMPERATURE
PLASTIC ......................... - 55°C to
CERAMiC ........................ -55°Cto
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under bias ........... O°C to 50°C
Voltage on any pin with respect to VSS ... - 0.2V to + 7.0V
Power dissipation ............................ 1 Watt
DC Electrical Characteristics TA
SYMBOL
NOTE: Maximum ratings indicate operation where permanent device damage may occur. Continuous operations at these limits is not intended and should be
limited to those conditions specified in the DC electrical characteristics.
= O°C to 50°C; VCC = + 5V
PARAMETER
+ 125°C
+ 150°C
± 10%, VSS
Typ1
MIN
= OV
MAX
UNIT
0.7
V
CONDITION
----
Input Low Voltage
-0.2
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
VCC
Supply Voltage
4.5
ICC
Supply Current
VIL
AC Electrical Characteristics TA
SYMBOL
V
0.4
5.0
= O°C to 50°C; VCC = + 5V
PARAMETER
V
IOL = 3.2mA
V
IOH = -200JAA
5.5
V
100
mA
All outputs open
± 10%, VSS == OV
Typ1
MIN
MAX
UNIT
5.25
MHZ
CONDITION
---
fRC
RCLK Frequency
tST
Data Setup time
40
tHT
Data Hold time
10
tDD
DOUT to DCLK DELAY
110
nsec
tRD
+ RCLK to t DCLK
120
nsec
tRA
+RCLK to t AMDET
115
nsec
tRM
+RCLK to + AMDET
125
nsec
tRO
+RCLK to DOUT
135
nsec
tEA
+ENDET to +AMDET
130
nsec
110
nsec
tRO
+ RST to t OOUT
tRW
Pulse width of RST
50
tcw
CP Pulse width
90
tco
t CPto+OOUT
nsec
nsec
nsec
nsec
106
nsec
----
NOTES: 1. Typical Values are for TA = 25°C and VCC = + 5V.
53
:ec
.....
.....
g
ENDET
~
RClK
DIN
tSl..,
o
0
0
:..
I_I'
JU-
,t HT
,_0
1
I
0
1
f RC
1
:- -:
1_
I
:1
-------~
i
I
1
I
TEST 2
I
1
1
I
I
I
'I
.: 1
::
0
I
~~r~~~
i:
Ii
II~'>----------OA
TEST 1
RD
i
LJLrLhJ-:u-nru
I
o
ClKIN
-:
--A1 -~----~-------+-----I'
RClK
:--t
,
I
I:
---.~
1Amr'Tl
:
;
i~;
:
I
I
:
1
~rT:~-----~-------
10ADET)
: tRM
"I
:...
AMDET
,
:
: tRA
L I_ _ _ _ _ _ _ _
1
~----~
_II~
I
AMDET __________________________________~~--~ri----~----start of A1
t RO
DOUT
'I
~II""'"
-------------~
-----~_1~_
tD~:
_____ '
DClK
:__
:
I
,
LJLJLJLJl
WD1100·03
Figure 3. Functional Timing
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable, However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use, No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
54
Printed ,n U S.A
Western Digital
WD1100-04 CRC Generator/Checker
=e
c
.....
.....
o
o
DESCRIPTION
FEATURES
The WD1100-04 CRC Generator/Checker is designed to
!~enerate a Cyclic Redundancy Checkword from a serial
data stream, and to check a data stream against a known
CRC word. Complimentary latched "CRCOK" outputs are
provided to indicate CRC errors in check mode. Additional
logic has been included to shift the CRC checkword out of
the device by signals generated on other WD1100 family
devices.
• GENERATES/CHECKS CRC
• SINGLE + 5V SUPPLY
• LATCHED ERROR OUTPUTS
• X16 + KI2 + X5 + 1 (CCITT-16)
• AUTOMATIC PRESET
• 20 PIN DIP PACKAGE
The WD1100-04 is fabricated in NMOS silicon gate
technology and is available in a 20 pin dual-in-line package.
GRCIZ
SKPCLK
DIN
20
50CiZ
SHFcTi<
19
VCC
NC
18
NC
NC
17
NC
15
TIMCLK
NC
CWE
POLYNOMIAL GEN
+ X12 + X5 + 1
Q
X 16
DOUT
C
SHFCLK
CRCOK
DOCE
WCLK
CRCiZ
CRCOK
NC
VSS
i5
DIN
DOCE
CWE
DOCK
SKPCLK
11
DOUT
CRCOK
CRCOK
WCLK
-:- 16
)
WD1100-04
Figure 1. Pin Connections
WD1100-04
Figure 2_ Block Diagram
55
~
TIMCLK
PIN
NUMBER
SYMBOL
DIN
2
3
4,5
SHFCLK
FUNCTION
NAME
DATA INPUT
Active low serial input data stream
generate/check the 2 byte CRC word.
is
used
to
DATAORCRC
WORD CLOCK
After a byte of data has been transferred in, this input
signal is used to latch the state of DOCE in an internal
D flop with a high to low transition.
SHIFT CLOCK
The falling edge shifts data bits into the CRC
generator/checker. It also transfers the CRC check word to
DOUT in the write mode (DOCE = LOW). The rising edge
also activates the CRCOK lines in the read mode when no
error is found.
N.C.
NO CONNECTION
6
CWE
CHECK WORD
ENABLE
This active low output indicates that the CRC checkword is
being output on the DOUT line. When CWE is high, data is
being output on DOUT.
7
DOCE
DATAORCRC
ENABLE
Initially, this input line is held high to direct input data (pin
1) to the output data (pin 11). After the next to the last BYTE
Is transmitted but before the last BYTE occurs DOCE must
be low to direct the 2 CRC check bytes to DOUT (pin 11).
DOCE must be maintained low for a minimum of 2 byte
times. DOCE is used only in the write mode.
8
REDUNDANCY
CHECK INITIALIZE
When this line is at a logic 0, the SKPCLK output line is
held high and the CRC generator is held preset to hex
"FFFF."
9
N.C.
NO CONNECTION
10
VSS
GROUND
GROUND.
11
DOUT
DATA OUTPUT
In the write mode, this line outputs the unmodified data
stream along with the 2 byte CRC word appended to the
end of the stream.
12
SKPCLK
SKIP CLOCK
The first high-to-Iow transition on DIN (pin 1) resets
SKPCLK low and enables the CRC to either generate or
check the CRC word.
13
CRCOK
CYCLIC
REDUNDANCY
CHECK OKAY
In the read mode, after the 2 byte CRC word is entered
on DIN and no error has been detected, this line is set
high to indicate no errors have occurred. This line will
then remain high as long as DIN is maintained high.
14
WCLK
WRITE CLOCK
This input clock is divided by 16 to produce TIMCLK
(pin 15) and has no effect on the rest of the internal circuitry.
15
TIMCLK
TIMING CLOCK
See above.
16
CRCOK
CYCLIC
REDUNDANCY
CHECK OKAY
Complementary output version of CRCOK (pin 13).
17-19
N.C.
NO CONNECTION
20
Vec
VCC
+ 5V ± 10% power supply input.
DEVICE DESCRIPTION
operation. At the end of the data stream, if no errors were
detected the CRCOK (pin 13) is set high. Accordingly the
complimentary output (pin 16) is set low. These output
states will be maintained as long as DIN is held high and
CRCIZ (pin 8) is not strobed. If the CRCOK lines do not
become active, an error has been detected and a re-try is in
order. If successive re-tries fall, an error flag may be set to
determine a further course of action as desired by the user.
Prior to shifting data thru the device (either in the read or
write modes) the CRC generator/checker is initialized by
strobing the CRCIZ (pin 8) low. This forces the SKPCLK (pin
12) line to the high state. The first low gOing transition on
DIN (pin 1), namely the most significant bit of an address
mark, resets the SKPCLK line. The WD1100-04 has now
been properly initialized and is ready to generate/check the
CRC bytes. The CRCOK and CRCOK lines should be set to
their inactive states.
WCLK is divided by 16 to produce TIMCLK which may be
used as a buffered step clock for SA1000 compatible
drives.
In the write mode, initially the DaCE (pin 7) is held high and
a pseudo DOCK is produced by supplying a string of zeros
before the address mark. This ensures the proper state of
the internal D flip flop to gate input data to the output line
DOUT (pin 11). As shown in the block diagram the eWE (pin
6) will be set high. Sometime between the next to the last
and the last DOCK that indicates the end of the data
stream, DaCE (pin 7) is lowered to ensure the smooth transition of the 2 byte CRC checkword to the output line
DOUT (pin 11).
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Sias ............ O°c to 50°c
Voltage on any pin with respect to VSS ... - 0.2V to + 7.0V
Power Dissipation ............................ 1 Watt
STORAGE TEMPERATURE
PLASTIC. . . . . . . . . . . . . . . . . . . . . . . . . - 55°C to
CERAM IC. . . . . . . . . . . . . . . . . . . . . . . . - 55°C to
DaCE must be maintained low for a minimum of 2 byte
times. After the CRC word is generated, DOUT will produce
a string of zeros (I.e., held high). This portion of the circuitry
Is dormant in the read mode.
SYMBOL
=O°C to 50°C; VCC = + 5V ±
PARAMETER
Input Low Voltage
-0.2
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
VCC
Supply Voltage
4.5
ICC
Supply Current
AC Electrical Characteristics TA
SYMBOL.
10%, VSS
= OV
Typ1
MIN
VIL
+ 150 °c
NOTE: Maximum ratings indicate operation where permanent device damage may occur. Continuous operations at these limits is not intended and should be
limited to those conditions specified in the DC Electrical Characteristics.
After proper initialization, input data is entered on DIN (pin
1) along with the 2 byte CRC word for the read mode of
DC Electrical Characteristics TA
+ 125°C
MAX
UNIT
0.8
V
CONDITION
V
0.4
5.0
V
IOL
V
IOH
5.5
V
100
mA
MAX
UNIT
= 3.2mA
= -200jAA
All outputs open
= 0° to 50°C, VCC = 5V ± 10%, VSS = OV
PARAMETER
Typ1
MIN
tWT
t WCLK to ~ TIMCLK
95
nsec
twR
t WCLK to t TIMCLK
85
nsec
tzs
~
CRCIZ to t SKPCLK
120
nsec
tZK
CRCIZ pulse width
90
nsec
tss
DOCE set up time w.r.t.
20
nsec
40
nsec
CONDITION
~DOCK
tSH
DaCE hold time w.r.t.
-l-DOCK
tDD
DIN to DOUT delay
105
57
nsec
CWEset high
~
C
..a.
..a.
8
:e
c
SYMBOL
PARAMETER
Typ1
MIN
I
MAX
120
miN to.\. SKPCLK
tDK
I
UNIT
tDW
DIN P.w. to reset SKPCLK
o
tiC
~
DOCK to .\. CWE
120
nsec
tac
+DOCK to t CWE
120
nsec
nsec
50
fSC
SHFCLK frequency
5.25
MHZ
tSR
t SH FCLK to t CRCOK
85
nsec
tsc
t SHFCLK to +CRCOK
+DOCK to +DIN
90
nsec
90
nsec
tiN
Notes: 1. Typical values are for T A
I
CONDITION
nsec
.....
.....
o
I
= 25°C and VCC = + 5.0V
- : fsc:____ I
SHFCLK
,
I
I
~
~
:------tsH------:--tss--:
DaCE
l
,
n = last data byte
:
'
'
Remains lOW!:! 2
i~e times
--,
I
tSA_:I_
I'
________________________
CRcaK
~:
t sc - - :
CRCaK
r l- - - - - - - -
I-
i
~
,.,d mod.
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
WD1100·04
Figure 3. Write Mode
CRCIZ
L
Ij-I
ZK
1.-----
--I 1:;:= tzs
SKPCLK _ _ _ r--~I
-----
-
....
l - t DK
I tow r=
WD1100·04
Figure 4. Initialize
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
58
PrInted
In
U S.A
:ec
Western Digital
WD1100-05 Parallel/Serial Converter
.....
.....
8
DESCRIPTION
FEATURES
The WD 1100-05 Parallel/Serial Converter allows the user to
convert a byte of data to a serial stream when writing to a
disk or any serial device. Parallel data is entered via the DOD? lines on the rising edge of DCLK. A synchronous BYTE
counter is used to signify that 8 bit~ of data have been
shifted out and that the 8 bit latch is ready to be reloaded.
The double buffering of the data permits another byte to be
loaded while the previous byte is in the process of being
shifted.
• SINGLE + 5V SUPPLY
• DOUBLE BUFFERING
• BYTE STROBE OUTPUTS
• 5 M BITS/SEC SHIFT RATE
• TRI-STATE OUTPUT CONTROL
• PARALLEL IN/SERIAL OUT
• 20 PIN DIP PACKAGE
The WD1100-05 is implemented in NMOS silicon gate
technology and is available in a 20 pin plastic or ceramic
dual-in-line package.
DO
20
VCC
01
19
EN
02
18
NC
03
17
TEST
04
16
BOONE
05
15
OOUT
06
14
07
13
SH"FCLi<
Li5
SHFCLK
12
WCLK
Vss
11
OCLK
WD1100·05
Figure 1. Pin Connections
--------.
DO·D7
,
/8
1
Q
D
8
,
,8
I
8 BIT
LATCH
Q~r--~
D
C
DOUT
8 BIT SHIFT
REG
c
1
!
+5V
+L
D
BYTE
COUNTER
C
LD
6
r-+-
SHFCLK
~
SHFCLK
>-
BDONE
R
Q
C
EN
LD
't
T
)lL5
WD1100·05
Figure 2. Block Diagram
59
PIN NUMBER
=e
C
.....
.....
0
0
SYMBOL
FUNCTION
NAME
DO-D7
DATA O-DATA 7
8 bit parallel data inputs (bit 7 = MSB),
SHFCLK
SHIFT CLOCK
Inverted copy of WCLK (pin 12) which is active when
ENABLE (pin 19) is at a logic O.
10
VSS
GROUND
GROUND.
1'1
DCLK
DATA CLOCK
Active low input signal resets the BDONE (pin 16) latch.
The low-to-high (trailing edge) clocks the input data into the
internal 8 bit latch.
12
-WCLK
WRITE CLOCK
The high-to-Iow (~) edge of this clock signal is used to shift
the data out serially. The low-to-high (t) edge is used to update the internal byte counter (module 8).
13
LD
LOAD
This active low signal indicates that the Byte Counter is being preset to 1. Normally left open by the user.
14
SHFCLK
SHIFT CLOCK
Delayed copy of WCLK (pin 12) which is active when EN
(pin 19) is at a logic O.
15
DOUT
DATA OUT
Serial data output enabled by EN (pin 19).
16
BDONE
BYTE DONE
This output signal is forced to a logic 1 whenever 8 bits
of data have been shifted out. BDONE remains in this
state unless reset by the loading of another byte of
data.
17
TEST
TESTINPUT
This pin must be left open by the user.
1-8
9
---
--
18
NC
No Connection
19
EN
ENABLE
This active low signal enables DOUT, SHFCLK,
SHFCLK, and BDONE outputs, When high, these output signals are in a high impedance state.
20
VCC
VCC
+ 5 ± 10% power supply input.
~--------~-----------~----------------~------------------------------------
WClK cycles unless the next byte to be transmitted is the
same as the previous byte.
DEVICE DESCRIPTION
Prior to loading the WD11(}(}05, it is recommended that
OOH (or FF) be loaded into the input buffers to ensure that
DOUT is at a fixed level. EN (pin 19) is set to a logic 0 to
enable the device outputs.
Four signals, BDONE, DOUT, SRF-C[K~ and SHFCLK, can
be placed in a high impedance state by setting EN (pin 19)
to a logic 1. Likewise, EN must be at a logic 0 in order for
these signals to drive any external device.
Data is entered on the 00-D7 input lines and is strobed into
the data latches on the rising edge of DCLK (pin 11), DCLK
also resets BDONE (pin 16). The first BDONE that comes
up simply means that the WD1100-05 is ready to accept
another byte of data and that the previous byte entered is in
the process of being shifted out. If the BDONE is serviced
prior to every 8th WRITE CLOCK pulse the output data will
represent a co'ntiguous block of the bytes entered. Due to
the asynchronous nature of the WD1100-05, the input data
will be available in serial form at the output anywhere from
8 to 16 write clock cycles later.
The TEST pin is internally OR'ed with the counter output to
produce the LD (pin 13) signal. This is used to inhibit the bit
counter by external means for test purposes. It is recommended that TEST be left open by the user. An internal
pullup register is tied to this pin to satisfy the appropriate
logic level required for proper device operation.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias ......... , . O°C to 50°C
Voltage on any pin with respect to VSS ... - 0.2V to + 7.0V
Power Dissipation ............................ 1 Watt
STORAGE TEMPERATURE
PLASTIC .............. , . . . . . . . . . . - 55°C to + 125°C
CERAMICS .......... , .... , . , ..... - 55°C to + 150°C
Data is shifted out on the high-to-Iow (~) transition of the
12). The low-to-high (t) transition of WCLK increments a byte counter which in turn sets the BDONE
signal high after 8 bits of data have been shifted out. The
low-to-high transition of BDONE also causes the loading of
the data buffer into the shift register. The data buffer is now
ready to be reloaded with the next byte.
wcuf (pin
NOTE: Maximum ratings indicate operation where permanent device damage may occur. Continuous operations at these limits is not intended and should be
limited to those conditions specified in the DC electrical characteristics.
The loading of the next byte automatically clears the
BDONE signal. The entire process as outlined above is
repeated. BDONE always needs to be serviced within 8
60
DC Electrical Characteristics: TA :::;;: O°C to 50°C; Vee:::;;:
+ 5V
= OV
± 10%, Vss
-"--
SYMBOL
PARAMETER
Input Low Voltage
-0.2
VOH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
VCC
Supply Voltage
4.5
ICC
Supply Current
VIL
PARAMETER
MAX
UNIT
0.8
V
CONDITION
------_._-
5.0
0.4
V
IOL = 3.2mA
V
IOH = -200/AA
5.5
V
100
mA
All Outputs Open
10%; VSS = OV
Typ1
MIN
MAX
UNIT
5.25
MI-.IZ
CONDITION
fWC
WCLK frequency
tDW
DCLK pulse width
50
nsec
tDS
Data set-up W.r.t. t DCLK
30
nsec
tDH
Data hold time w.r.t. t DCLK
30
tDB
~
DCLK to ~ BDONE
130
nsec
EN= 0
tDO
~
WCLK to DOUT
130
nsec
EN= 0
tSH
~
WCLK to ~ SHFCLK
75
nsec
EN= 0
tHS
t WCLK to t SH FCLK
70
nsec
EN= 0
tWB
t WCLK to t BDONE
180
nsec
tES
~
25
nsec
tCL
tWCLK
50
nsec
nsec
75
EN to BDONE. DOUT
SHFCLK ACTIVE
to~
LD
NOTES: 1. Typical Values are for TA = 25°C and VCC =
+ 5.0V
........... fwe :.....
_lULfLrr~~~fL
l_tow
:!
I:
'
, ,
I
,--:------;'--------,
U::
LJ:
U-tD~ l~DH ; )
:!
L,--~~~~__L_:__ ~~
_ _ 'I
----i
__
07-00
toa _:
BONE
I~ ~
I
I
I
~
::
L
teL
I
---+:
--tL[
I
,
~
I
DATA
II
I,
too
C~~ J
SHFELK
r==·:ttLjLJ1SLJL
U
I
I
--------i------------
t
SHFCLK
:",,!WB
'
I
-i :-
"
I:
n=·~~~A~D
- .... 1
___-'-,--,Ir----~~
::
L--~i_:
.--~-r::'
~rs
DOUr
' :
:; r-----
____ +~
II
t
uLlrhnSLJLJLfLnsu--u-tJLJLJL
WD1100·05
Figure 3. Functional Timing Diagram
61
:ec
.....
.....
8
V
+5 ±
AC Electrical Characteristics: TA = O°C to 50°C; VCC =
SYMBOL
Typ1
MIN
--
Information furnished by Western Digital Corporation is believed to be aCGurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
62
Printed In USA
Western Digital
WD1100-06 ECC/CRC Logic
DESCRIPTION
FEATURES
The WD1100-06 EGG/GRG logic chip gives the user of
the WD1100 series of chips easy EGG or GRG implementation. With proper software, it will provide single
burst correction up to 8 bits and double burst detection. The computer selected polynomial has been optimized for Winchester 5114" and 8" drives with sector
sizes up to 512 bytes.
• 32 bit computer selected polynomial
• Single burst correction up to 8 bits
• Multiple burst detection
• Programmable correction/detection span
• GRG or EGG software selectable
• Data transfer rates to 5.25 Mbits/sec
• Serial check/syndrome bit processing
• 128,256,512 byte sector sizes
• Single
+ 5V supply
• TTL, MOS compatible
• 20 pin DIP package
SEL •
ECCIZ
DCSS
R/Vii
R/Vii
DOUT
EDOUT
CSE
WBS
wOP
RBS
RDAT
RDAT
DCSS
WDAT
EDOUT
SEL
DOUT
FBD
NC
ECCEN
VSS
CONTROL
RCP
WCP
RCP
MUX
VCC
WDAT
BS
RBS
ECCEN
WBS
FBD
CSE
i3S
L-----------------~----+_--~RWCP
RWCP
S
SHIFT REGISTER
DO
WD1100·06
Figure 2.
BLOCK DIAGRAM
WD1100·06
Figure 1.
PIN CONNECTIONS
63
WD1100·06 ECC/CRC DEVICE PIN DESCRIPTION
PIN
NUMBER
PIN NAME
1
READIWRITE
2
READ CLOCK
PULSE
3
WRITE CLOCK
FUNCTION
SYMBOL
Input line used to select the data, clock and
GRG/EGG strobe during read/write operations.
When low input signals WDAT, WCP, and WBS
are selected. When high input signals RDAT,
~, and RBS are selected.
Input pulse used by the internal shift registers
to compute the 4 syndrome bytes.
R/W
Input pulse used by the internal shift registers
to compute the 4 check bytes.
PUI:SE
4
READ DATA
RDAT
Serial data Input during a read operation.
5
WRITE DATA
WDAT
Serial data Input during a write operation.
6
SELECT
SEL
This input is used to select either the GRC or
the EGC polynomial for error detection/correction. SEL = 0 ECC polynomial
selected. SEL = 1 CRC polynomial selected.
7
ECC INITIALIZE
8
9
ECC ENABLE
10
GROUND
11
READIWRITE
CLOCK PULSE
12
BYTE SYNC
The input signals RBS and WBS are gated with
the appropriate clocks and multiplexed as an
output on the byte sync line. Normally not used
by the user.
13
CLOCK SELECT
ENABLE
When high, this output indicates that the device
is in the process of com~ the
check/syndrome bytes and that ~DCJOT and
OOUT lines contain data information. When
low, the device puts GRC or EGG check/syndrome bits on the output data lines.
14
FEEDBACK
The feedback line to the shift registers is
brought out as an output line for test purposes.
Normally left open by the user.
15
DATA OUTPUT
Output data line carries data or CRC/EGG information depending upon the state of DCSS.
16
EARLY DATA
OUTPUT
Unlatched output data line available 1 clock
period earlier than DOUT.
NO CONNECTION
Input used to preset all the internal shift
~sters. Output lines FBD, EDOUT, DOUT, and
CSE will be in their inactive h~tates. The
first low going edge of either RDAT or WDAT
signals the activation of all internal circuitry.
No connection.
N/C
ECGEN
When low, the ECG/CRC process is enabled.
When high, this output signal indicates that the
process is disabled.
Ground
VSS
RWGP
Output clock pulse during read or write
wcwtions. The input clock pulses RCP and
are multiplexed on this output line for use
by any support logic.
64
WD1100-06 ECC/CRC PIN DESCRIPTION (CONTINUED)
PIN
NUMBER
PIN NAME
SYMBOL
17
DATA/CHECK
SYNDROME SELECT
DCSS
18
READ BYTE
RBS
19
WRITE BYTE
WBS
20
+5V
VCC
FUNCTION
Data or check/syndrome select input line. When
high, data is output on the data lines; when low,
CRC or check syndrome bits are output
depending upon which polynomial is selected.
DCSS goes low sometime between the last and
the next to the last data byte transferred to/from
the disk provided all set-up and hold-times have
been met. DCSS must stay low for at least 2
byte times when the CRC polynomial selected
and it must stay low for at least 4 byte times if
the ECC polynomial is selected.
Input used to latch the state of DCSS during the
read mode.
Input used to latch the state of DCSS during the
write mode.
+5V ±'10%
within the bad sector. To protect the integrity of the
10 field only a CRC check should be performed over
this field. No attempt ought to be made to correct
data in the 10 field. The CRC polynomial implementedisthestandardCCITT(X16 + X12 + X5 + 1.)
Although either polynomial may be used for both
fields, the use of the CRC polynomial for the 10 fields
is recommended since it only requires 2 bytes instead of 4.
DEVICE DESCRIPTION
To ensure correct operation of the WD1100-06 device,
the ECCIZ line is strobed to preset the polynomial
generator shift register, and reset the Data/CheckSyndrome select flip-flop. The 32 bit shift register
string is preset to avoid all zero check bytes. The
DCSS line is held high and appropriate signals are
then applied to the rest of the inputs. Since most disk
media use an Address mark of A1 (or M.S.B. set),
advantage is taken of this feature to start off the
ECC/CRC calculation on the data/ID fields automatically. The first active low going edge on the input
data lines releases the internal SET Flip-Flop. The
ECCEN output line is set low indicating that the
internal circuitry is ready to begin the computation of
the ECC/CRC bytes. Immediately following the
Address mark, data is supplied in a serial fashion.
Sometime before the last byte of data and after the
next to the last byte of data is' transferred through
this device, the DCSS line is set low. Since data is
generally serial ized/deserial ized before/after processing by the WD1100-06 device, the byte-sync pulses
can be easily obtained from those devices marking
the byte boundaries. The byte-sync pulses are internally ANDED with the RWCP line to ensure the
smooth transition of check/syndrome bytes on the
DOUT output line only after the last bit of data has
been entered into the device. A one bit time dolay
through a 0 Flip-Flop has been added on the 0 UT
line to deglitch this output line.
During a WRITE operation, the input data stream is
divided by the polynomial X32 + X28 + X26 + X19
+ X17 + X10 + X2 + 1 and the 32 bit remainder obtained is used as the 4 check syndrome bytes. If the
syndrome is zero, no errors occurred. Otherwise, the
non-zero syndrome is used by a software algorithm to
compute the displacement and the error vector
POLYNOMIAL SELECTION
For disk media, polynomial selection has a significant influence on data accuracy. Fire code
polynomials have been widely used on OEM disk
controllers, but provide less accuracy than properly
selected computer generated codes.
For fixed, guaranteed correction and detection
spans, data accuracy may be highly dependent on
polynomial selection. Some polynomials, fire codes
for example, are particularly susceptible to miscorrection on common disk type errors, while others,
computer generated polynomials for example, can be
selected to be less susceptible. Computer generated
codes do not have the pattern sensitivity of the fire
code and the miscorrection patterns are more random in nature.
More than 20,000 computer generated random
polynomials of degree 32, each with 8 feedback
terms, were evaluated in order to find the polynomial
described in this specification.
SELECTING THE CORRECTION SPAN
The code described in this document can be used to
correct up to 8 bits.
Any correction span from 1 to 8 may be selected.
However, for best data accuracy, the lowest correction span should be used that meets the correction
65
:ec
.....
.....
~
o0)
SOFTWARE REQUIREMENTS
The software algorithm, developed by the user, uses
the syndrome to detect an error, generate a correc·
tion pattern and a displacement vector or to deter·
mine if uncorrectable. In the correction algorithm, a
simulated shift register is used to implement the
reciprocal polynomial. The simulated shift register is
loaded with the syndrome and shifted until a correct·
able pattern is found or the error is determined to be
uncorrectable. Both forward and reverse displace·
ments are computed.
Either the serial or the parallel algorithm may be
implemented by the user. In almost all cases the
serial software algorithm is the most applicable.
Additionally, 1K of table space is required if the
parallel software algorithm is selected. It is assumed
that the highest order bit of a byte is serialized and
deserialized first.
requirements for the disk drives supported.
For most Winchester media, a 5 bit correction span is
adequate.
The correction span may have to be longer if the drive
uses a read/write modulation method that maps a
single media bit in error into several decoded bits in
error. Examples of read/write modulation methods of
this type would be GCR and 2,7 code.
PROPERTIES OF THE POLYNOMIAL
The following polynomial was computer selected for
insensitivity to short double bursts, good detection
span and 8 feedback terms.
Forward polynomial is:
X32 + X28 + X26 + X19 + X17 + X10 + X6 + X2
+0
Reciprocal polynomial is:
X32 + X30 + X26 + X22 + X15 +x13 + X6 + X4
CORRECTION TIME PERFORMANCE
All real time operations are performed with error cor·
rection hardware. The software algorithms used get
involved only after an error has been detected.
The following correction times are for a serial type
algorithm such as that used on the WD1 001:
a) Standard microprocessor = 30 to 60 milliseconds
b) Bit slice = 6 to 12 milliseconds
c) 8X3OO (used on WD1001) = 15 to 30 milliseconds
+ XO
Properties *
1. Maximum record length (r) = 526x8 bits (including
check bits)
2. Maximum correction span (b) = 8 bits
3. Degree of polynomial (m) = 32
4. Single burst detection span without correction =
32 bits. (Detection span when the code is used for
detection only)
5. Single burst detection span with correction (d) (Detection span when the code is used for correc·
tion)
= 19 bits for b = 5 and r= 526x8
= 14 bits for b = 8 and r= 526x8
= 20 bits for b = 5 and r = 270x8
= 14 bits for b = 8 and r+ 270x8
6. Double burst detection span without correction (Doule burst detection span when code is used for
correction)
= 3 bits for b = 5 and r= 526x8
= 2 bits for b = 8 and r = 526x8
= 4 bits for b = 5 and r= 270x8
= 2 bits for b = 8 and r = 270x8
7. Non·detection probability = 2.3 E·10.
8. Miscorrection probability= 1.57 E·5 for b = 5 and r= 526x8
= 1.25 E·4 for b = 8 and r= 526x8
= 8.00 E-6 for b = 5 and r = 270x8
= 6.40 E·5 for b = 8 and r = 270x8
NOTE:·
You should not use this polynomial for a record
length or correction span beyond the maximum
specified above.
DATA ACCURACY
ERP (Error Recovery Procedure) strategies have a
significant influence on data accuracy. An ERP
strategy requires data to be re·read before applying
correction and results in much better data accuracy.
The WD1OO1 employs such a strategy. This strategy
reduces the possibility of passing undetected erron·
eous data by rereading until the error goes away, or
until there has been a consistant error syndrome over
two previous rereads.
Another technique that can be used to give data a
higher probability of recovery is write check: read
back after write. Since write check affects per·
formance, it should be optional. Alternate sector
assignment and defect skipping are some of the
other techniques that may be implemented by the
user if so desired.
66
•
SELF-CHECKING WITH MICROCODE
the induced error does not exceed the correction
span of the polynomial generator.
3. WRITELONG: Write the data and check bytes
supplied by the host to the disk. Prevent WD11?O06 from generating check bits by not ass~rtlng
DCSS during transfer. No check bytes WIll be
recorded.
Periodic microcode and/or software checking is
another approach that can be used to limit the
amount of undetected erroneous data transferred in
case of an ECC circuit failure. Microcode or software
diagnostics could be run on subsystem power up
and during idle times. These diagnostics would force
ECC errors and check for the proper syndrome and
proper decoding of the syndrome by the correction
routine of the operational microcode.
To do this, simply use a long bit in the READ and
WRITE commands to the disk. This bit can then be
used to suppress the transfer of checklsyndro~e
bytes on the output data line by letting the DCSS line
stay high during ECC TIME. The complete procedure
is summarized below .
.1. WRITE: Pass all data to the disk and generate 4
check bytes at the end of the data field.
:2. READLONG: Do not generate the syndrome, ihstead copy the 4 check bytes as data and pa~s
them unaltered to the host. Now the host may induce errors anywhere in the data stream as long as
4. READ: Read data and generate the syndrome in a
normal manner. The software algorithm can now
be invoked to correct the induced error.
To aid in detection of certain hardware failures, it is
desirable to have non-zero check bytes for an all
zeros record. This feature has been incorporated into
the circuit defined in this specification.
67
=E
c
.....
.....
8
6
en
NOTE:
Maximum ratings indicate operation where permanent device damage may occur. Continuous
operations at these limits is not intended and should
be limited to those conditions specified in the DC
electrical characteristics.
SPECIFICATIONS
:e
c
.....
.....
o
o
6
en
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under bias ...... O°C to 50°C
Voltage on any pin with
respect to VSS ............... - 0.2V to + 7.0V
Power dissipation ...................... 1 Watt
Storage Temperature
Plastic ................. " - 55°C to + 125°C
Ceramic .................. - 55°C to + 150°C
DC Electrical Characteristics TA
SYMBOL
= O°C to 50°C; VCC ~
PARAMETER
10%, VSS
TYp1
MAX
UNIT
0.8
V
0.4
V
IOL = 3.2 mA
V
IOH = -200jAA
MIN
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Output High Voltage
2.4
VCC
Supply Voltage
4.5
ICC
Supply Current
= OV
+ 5V ±
-0.2
2.0
CONDITION
V
5.0
5.5
V
75
150
mA
All outputs open
ECCIZ PULSE WIDTH
R/W=>C~____H_IG_H__FO_R_R_E_A_D______________LO_,W
__F_O_R_W_R_IT_E_______________________~
ECCIZ~IZ
-.j
~
ECCEN
tiE
~r----------~~
_______________________________________________
RDAT -----------.
:
WDAT
tST
-.~
,
--1
I
I
RCP
WCP
AC Electrical Characteristics TA
SYMBOL
= O°C to 50°C; VCC
PARAMETER
=.;
+ 5V ± 10%, VSS
TYp1
MIN
Clock Frequency
fCp
tlZ
tiE
tST
ECCIZ Pulse Width
ECCIZ ! to ECCEN 1
RlWDAT Setup Time
50
tHT
RlWDAT Hold Time
0
MAX
UNIT
5.25
MHZ
nSec
nSec
nSec
100
1 Clock
Period
50
nSec
See page 725 for ordering information.
68
CONDITION
Western Digital
WD1100-07 Host Interface Logic
DESCRIPTION
FEATURES
The WD1100-07 Host Interface Logic chip simplifies
the design of a Winchester Hard Disk Controller
using the WD1100 chip series. It does this by performing logic functions that would otherwise require
considerable discrete logic. Additionally, there are
signals provided for ECC implementation.
• SINGLE +5V SUPPLY
• WAIT SIGNAL GENERATION
c......
• TIMING CLOCK GENERATION
8
WRS
WAEN
WCL1
vcc
WCL2
2
WCLK
RESET
3
cs
cs
SAGEN
SACEN
4
WHEN
5
RCP
WCLK
TIMCLK
6
RCLK
7
RBS
AfVfOUi
RESET
WR3
INDEX
8
CSAC
UNR
9
WAIT
Vss
6
""-.I
• CARD ACCESS CONTROL
• COMPLIMENTS ECC ARCHITECTURE
• 20 PIN DIP PACKAGE
..
.
.
I"'"
~
...
~
CONTROL
LOGIC
'"
~
......
CSAC
...
~
AMDET
LlNDEX
......
• INDEX PROPAGATION
The WD1100-07 is implemented in NMOS silicon gate
technology and is available in a 20 pin plastic or
ceramic Dual-in-Line package.
RD6
=e
INDEX
RCLK
AMDET
-....
-+-
-
TIMCLK
-
LlNDEX
.......
-...
RBS
-
..
16
v
:
--
~
!
S
LATCH
Q
R
-
...'"
.......
...
BYTE COUNTER
AND
DELAY
V
WD1100-07 Figure 1.
PIN CONNECTIONS
WD1100·07 Figure 2.
BLOCK DIAGRAM
69
-....
RCP
AMOUT
:E
PIN
NUMBER
PIN NAME
C
.....
.....
9
WAIT CLEAR 1
WCL1
0
2
WAIT CLEAR 2
WCL2
.......
3
RESET
RESET
4
SELECT ADDRESS
ENABLE
ADDRESS MARK
SACEN
0
5
This input presets a WAIT latch to a non-WAIT
condition on the falling edge.
This input presets a WAIT latch to a non-WAIT
condition on the falling edge.
An input us~o set TIMCLK & reset WAIT,
AMOUT and RBS.
This is an input signal that is used to enable
card select for host access.
An input that must go active when a
DATA=A1(HEX) or clock=OA(HEX) pattern is
detected in the data stream
An output used to provide reference timing signals to SA 100 type drives
This input, the same as used to clock in data
and clocks to the AM detector, is used to
produce AMOUT.
This input is provided by the drive once each
revolution of the disk
An input used to reset UNDEX.
Ground
An output that is INDEX delayed by one clock
time.
This output goes true when controller is internally accessing data or has not accepted data
from the host during a WRITE.
An output that is the result of CS qualified with
SACEN.
This output is a delayed version of AMDET.
AMDET
DETECT
6
TIMING CLOCK
TIMCLK
7
READ CLOCK
RCLK
8
INDEX PULSE
INDEX
9
10
11
UNDEX RESET
GROUND
LATCHED INDEX
UNR
VSS
UNDEX
12
WAIT
WAIT
13
CSAC
AMOUT
15
CARD SELECT
ADDRESS
ADDRESS MARK
DELAYED OUTPUT
READ BYTE STROBE
16
READ CLOCK PULSE
RCP
17
WAIT ENABLE
WAEN
18
19
CARD SELECT
WRITE CLOCK
CS
WCLK
20
+5VDC
VCC
14
FUNCTION
SYMBOL.
1
This output strobes once for each byte of READ
data. Initialized by AMDET.
This output is delayed from RCLK through propagation. Not normally used.
An input that is used to enable the internal
WAIT circuitry.
An input from host that selects controller.
This input is used to produce TIMCLK on low to
high transitions.
+5V ± 10%
RBS
DEVICE DESCRIPTION
Timing Clock
TIMCLK (pin 6) is a divided by sixteen version of
WCLK (pin 19). It is used with SA 1000 type drives.
Upon power up or reset, WAIT, AMOUT, and RBS are
reset and TIMCLK is set. This is the only interactive
signal between the four sections of the chip. Each
section will be described separately.
Index Pulse
Lindex (pin 11) is a delayed version of INDEX (pin 8). It
remains high until reset by UNR (pin 9).
Read Byte Sync
RBS (pin 15) will go true on the eighth negative going
transition of RCLK (pin 7) after AMDET (pin 5) goes
true. RBS will remain true for one clock cycle.
Control Logic
This section provides WAIT (pin 12) and CSA~
13). WAIT is set in its active low state when WAEN
(pin 17) is active low by the falling edge of CS (pin 18).
WAIT is reset by the falling edge of either WCL 1 or
WCL2 depending on whether in a read or write mode.
CSAC (pin 13) is enabled by setting SACEN (pin 4)
low ~fter WAIT has been enabled. CSAC is reset by
WCL 1 or WCL2.
Read Clock Pulse
RCP (pin 16) is a delayed version of RCLK and is
normally left open by the user.
70
Address Mark Delayed Output
AMOUT (pin 14) is the same as AMDET delayed by
two clock times.
These circuits were developed to work with the other
chips in the WD1100 series. They are used on the
WD1oo1 the timing relationships must be observed.
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias ...... O°C to 50°C
Voltage on any pin with
respecttoVsS ............... -0.2Vto +7.0V
Power Dissipation ....................... 1 Watt
Storage Temperature Plastic
- 55°C to + 125°C
Ceramic - 55°C to + 150°C
DC Electrical Characteristics TA
VIL
VIH
VOL
VOH
VCC
ICC
SYMBOL
5.0
MIN
UNIT
50
170
MHZ
nSec
nSec
nSec
nSec
nSec
nSec
nSec
nSec
nSec
nSec
tAM
AMDEn to AMOUT~
50
30
30
50
2 CLOCK
CYCLES
tBS
RCLK~
8 CLOCK
CYCLES
tRB
"RBS Period
50
5
45
1 CLOCK
CYCLE
= 25°C and VCC = + 5V
71
CONDITION
IOL
IOH
= 3.2mA
= - 2oo/AA
All outputs open
= OV
5.25
160
195
CS~toWAIT~
RBS~
V
V
V
V
V
mA
MAX
WCL 1~ orWCL2~ to WAiTt
WAEN Setup Time
SACEN~ to CSACt
WCL1~ or WCL2~ to CSAC~
WCLKt to TIMCLKt
INDEX~ to UNDEXt
UNR~ to UNDEX~
RCLK~ to RCP~
AMDET Setup Time
30
UNIT
TYp1
WCLK FREQUENCY
NOTE: Typical Values are for TA
5.5
100
10%;VSS
twc
tcw
tws
tsu
tsc
tcs
tWT
tu
tLW
tpc
tRA
to
MAX
0.8
0.4
2.4
4.5
= 0°Cto50°C;VCC = +5V ±
PARAMETER
= OV
10%; VSS
TYp1
MIN
-0.2
2.0
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current
ACElectricalCharacteristicsTA
1
= O°C to 50°C; VCC = + 5V ±
PARAMETER
SYMBOL
NOTE:
Maximum ratings indicate operation when permanent device damage may occur. Continuous operation at these limits is not intended and should be
limited to those conditions specified in the DC Electrical Characteristics.
70
155
250
100
100
75
2 CLOCK
CYCLES
+45
8 CLOCK
CYCLES
+165
CONDITION
WAIT TRUE
WAif" TRUE
nSec
f!Sec
------
--"
=e
c
••
~
0
......
WAEN
tsu-':
CS
tcw
WAIT
!---
I
-.f:.-
t--
tws-.i
I. . ________,__~i--~~I-----------------------
----------~~
!
U
WCL1orWCL2
I
I
I
SACEN
tsc~
I
I
tcs ---:
1
~
I
:.I
CSAC
WCLK
1
tWT""':
\.4-
....J
1
fWC
:---
TIMCLK
tu-...!
,I
:.1
UNDEX _ _ _ _ _.......1
tLW---':
~ -------------------------------------------------------~LJ
1
~
RCP
RCLK
tRA -.:
1.-
,!
~I~I--~I-------------------------------------------------~tAM-+j
1
1
I
I~--------------------------------------------
I
,
LJ
I
I
:~,.~-----------------tBS - - - - - - - -.. . . I. . . . tRB..j
See page 725 for ordering information.
72
Western Digital
WD1100-09 Data Separator Support Logic
technology and is available in a 20 pin plastic or
ceramic package.
GENERAL DESCRIPTION
The WD1100-09 Data Separator Support Logic, when
used with the other chips in the WD1100 series,
greatly reduces the external discrete logic required to
design a Winchester hard disk data separator. The
chip provides the pump signals to an external error
amplifier, control signals to an internal bus and a
special drive selection signal also to an internal bus.
The WD1100·09 is fabricated in NMOS silicon gate
FEATURES
•
•
•
•
DRS1
~
DRS3
DRS4
DATA
1
VCC
REF
2
RGATE
DIN
3
DMR
OSC
4
DRS4
DRS1
5
WRTi'E
RTFl10
6
~
DRS2
7
DS
DRUN
8
WDAT
DOUT
9
DOWN
VSS
10
11
.-
,.
....
,.
---
..
,.
DRIVE
SELECTED
LOGIC
OSC
DMR
....
-
OS
-......
UP
...
-
-.....
DIN
SINGLE + 5V SUPPLY
DRUN GENERATION
DATA SEPARATION CONTROL SIGNALS
20 PIN DIP PACKAGE
....
PUMP
LOGIC
-
DOWN
I
DATA
RGATE
UP
WDAT
WRITE
REF
-
-...
......
-..
f"
DATA
SEPARATOR
CONTROL
LOGIC
--
WD1100·09 Figure 1.
WD1100·09 Figure 2.
PIN CONNECTIONS
BLOCK DIAGRAM
73
I'"
-... Dour
--.
-
DRUN
RTFRQ
~
c-"
-"
o
o
6co
PIN
NUMBER
PIN NAME
2
DATA
REF
3
DELAYED DATA IN
DIN
4
OSCILLATOR
OSC
5,7,
15,17
FUNCTION
SYMBOL
READ DATA
REFERENCE
1
6
DRIVE SELECT 1DRIVE SELECT 4
HIGH FREQUENCY
8
DATA RUNNING
9
DATA OUT
DOUT
10
11
GROUND
UP PUMP
VSS
UP
12
DOWN PUMP
DOWN
13
14
WRITE DATA
DRIVE SELECTED
WDATA
DS
16
WRITE MODE
WRITE
18
DATA MASTER
RESET
DMR
19
READ GATE
RGATE
20
+5VDC
VCC
Input that is used in DRUN generation.
An input that is 2 times the data rate that keeps
the VCO on center frequency during non-read
times.
This input is a delayed version of DOUT. An
external delay line is used. The signals are
compared to provide pumps.
An input from the external VCO that is used in
pump development
Input signals indicating which drive has been
selected.
Output to controller microprocessor that indicates 16 ones or zeros have been entered on
the DATA line.
Output that indicates to the controller
microprocessor the completion of 16 ones or
zeros on the data line. Used to switch from REF
to DATA via firmware.
Output data line. Can be REF or DATA or WDATA
depending on the condition of WRITE, DMR and
RGATE.
Ground
An output that indicates REF is leading DATA.
Goes to error amp. Open collector.
An output that indicates DATA is leading REF.
Goes to error amp. Open collector.
MFM Write data input. Output appears at DOUT.
An output that indicates that one of four drives
have been selected.
This input is active during a write operation and
enables WDAT.
This~s used to provide time-out for DRUN
and HIFRQ in the event that 16 ones or zeros are
not present.
This input, usually provided by the controller
microprocessor, places chip in read mode.
+5VDC ± 10%
a crystal oscillator clock and will hold the VCO on
frequency.
DEVICE DESCRIPTION
The WD1100-09 is divided into three sections. Each
section will be described separately.
Data Separator Control Logic
Read Mode
In order to prevent the external VCO from locking
onto a harmonic of its operating frequency, REF (pin
2) is provided with a signal twice the data rate that is
crystal controlled. With WRITE (pin 6) and RGATE (pin
19) inactive, this signal will appear at DOUT (pin 9).
This signal is applied to the pump logic (see above).
Drive Select Logic
DS (pin ~ill go active high if any input DSR1
through DRS4 (pins 5,7,15,17) are active low.
Pump Logic
Internal logic causes the UP (pin 11) and the DOWN
(pin 12) to be set, initially to their inactive states. DIN
(pin 3) is the delayed data developed by passing
DOUT through a delay line. OSC (pin 4) is the output
of the data separator VCO. Whichever reaches the
pump logic first will determine whether UP PUMP or
DOWN PUMP is produced. These signals are then
sent to an external error amplifier and used for VCO
correction. During a write, the DIN must be locked to
The switching function is initiated immediately after
RGATE goes true. DMR (pin 18) will be set active as a
result of high frequency pulses applied to an external
one shot whose pulse width is such that its output is
a single stretched pulse. The high frequency pulses
are applied to the DATA (pin 1) line and after 16
consecutive pulses, DRUN (pin 8) and HIFRQ (pin 6)
74
.
go true. At this point REF is switched out and the
DATA stream is switched in and appears at OOUT.
DRUN is reset when RGATE goes inactive and
FilFRQ goes inactive when OMR goes inactive.
Write Mode
When WRITE (pin 16) goes active, REF is switched
out and WOAT (pin 13) will appear at OOUT. Since
WOAT is a crystal controlled signal (usually the MFM
write data); the VCO is held locked and will not drift
(see pump logic above).
:ec
.....
.....
o
o
6
CO
REAO MOOE
OMR - - - - '
~--~{S'"- - -
s-fUL-
OATA
too ....;:..
L....-....;..--~,~
.....j
:
RGATE - - - - '
~ tOR
$~L._ _ __
I
....: ,.......-tHO
~Sl
--------........:1·.....1 - - - -
OATA
I
OOUT
",-4--REF
truiru1Jl
WRITE
WRITE MOOE
OMR ___________________________________________________________________
OATA ___________________________________________________________________
ORUN
AC Electrical Characteristics TA
SYMBOL
10%; VSS
TYp1
UNIT
170
nSec
RGATE+ to ORUNt
90
nSec
OMR-I- to HIFRQt
90
nSec
10
MHz
OATA-I- to ORUN+
tOR
tHO
REF frequency
MIN
= OV
MAX
PARAMETER
too
fRE
= O°C to 50°C; VCC = + 5V ±
2TiMES
OATA RATE
75
CONDITION
SPECIFICATIONS
NOTE:
Maximum ratings indicate operation when permanent device damage may occur. Continuous operation at these limits is not intended and should be
limited to those conditions specified in the DC Electrical Characteristics.
ABSOLUTE MAXIMUM RATINGS
Ambieht Temperature under Bias ...... O°C to 50°C
Voltage on any pin with
respect to VSS ............... - 0.2V to + 7.0V
Power Dissipation ....................... 1 Watt
Storage Temperature Plastic
- 55°C to + 125°C
Ceramic - 55°C to + 150°C
DC Electrical Characteristics TA
SYMBOL
VIL
VIH
VOL
VOH
VCC
ICC
= O°C to 50°C; VCC :=
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Voltage
Supply Current
+ 5V
MIN
± 10%; VSS
TYp1
-0.2
2.0
= OV
MAX
UNIT
CONDITION
0.8
V
V
V
V
V
mA
IOL = 3.2mA
IOH = -200/AA
0.4
2.4
4.5
5.0
5.5
100
All outputs open
NOTE: UP and DOWN are open collector outputs and provide 12mA IOL @ .5V.
See page 725 for ordering information.
76
Printed In U S.A
WESTERN DIGITAL
c
o
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/
o
N
WD1010 Winchester Disk Controller
•
FEATURES
• Compatible with most 8- and 16-bit processors
• Data rate up to 5 Mbits per second
• Multiple sector read/write commands
• Unlimited interleave capability
• Automatic formatting
• Software selectable sector size
(128,256,512, or 1024 bytes per sector)
• CRC generation/verification
• Automatic retries on all errors
• Automatic restore on seek errors
• Single + 5V supply
• Provision tor external ECC capability
BCS
SCR
INTRQ
NC
MR
RE
WE
CS
AO
A1
A2
D7
D6
D5
90
32
10
11
12
31
30
29
28
04
D3
D2
D1
DO
VSS
APPLICATIONS
• Seagate ST506, ST512
• Shug(irt SA 1000, SA 1100, SA600
• Tandon 600 Series
• Texas Instruments 506
• RMS 500 Series
• Ouantum 02000 Series
• Miniscribe
... and others
DESCRIPTION
The WD1010 is a MOS/LSI device designed for use
with the drives listed above as well as other drives
compatible with the SA 1000 or ST506 interface. The
controller requires only a single + 5 volts supply. It is
designed to operate with an external sector buffer
memory and to interface directly with TTL logic.
The WD1010 is fabricated in NMOS Silicon-gate
technology and is available in a 40-pin, Dual-in-line
ceramic or plastic package.
FUNCTIONAL DESCRIPTION
The WD1010 is software compatible with the WD1000
controller board. Programming is very similar to that
of the Western Digital FD179X floppy disk controller:
Data bytes are transferred to or from the buffer every
1.6JAsec., with a 5Mbitlsec drive. The buffer may be
either the Western Digital WP1510 128x9 FIFO
memory (Fig. 1) or a combination of a 256x8 static
RAM and a 9 bit resettable counter (Fig. 2). The
WD1010 generates control signals to minimize external gating. Buffer to processor transfers are made
via programmed I/O or DMA. The controller also
generates handshake signals to control DMA
operations for multiple sector transfers. The WD1010
interfaces to the Western Digital DM1883 and other
DMA controllers.
VCC
RC
RG
RD
BDRQ
BRDY
DRUN
RWC
SC
TKOOO
WF
INDEX
DRDY
STEP
DIR
WC
WG
EARLY
LATE
WD
PIN CONNECTIONS
•
77
=E
c-L
o-L
o
TABLE 1. INTERFACE SIGNALS
=E
c.....
o.....
o
PIN NUMBER
SYMBOL
FUNCTION
PIN NAME
Eight bit bidirectional bus used for transfer of
commands, status, and data.
Tristate bidirectional line, used as an input for
6
RE
READ ENABLE
reading the task register and an output when
WD1010 is reading the buffer.
Tristate bidirectional line used as an input for
7
WE
WRITE ENABLE
writing into the task register and as an output
when the WD1010 is writing to the buffer.
These three inputs select the register to
9-11
AO-A2
ADDRESSOreceive/transmit data on DO-D7.
ADDRESS 2
A logic low on this input enables both WE and
CHIP SELECT
8
CS
RE signals.
INTERRUPT
Active high output which is set to a logic high in
3
INTRQ
the completion of any command.
REQUEST
A logic low in this input will initialize all internal
MASTER RESET
5
MR
logic.
BUFFER CHIP
Active low output used to enable reading or
1
BCS
SELECT
writing of the external sector buffer.
This input is used to inform the controller that
BUFFER READY
35
BRDY
the sector buffer is full or empty.
2
BCR
BUFFER COUNTER
Active low output that is strobed by the WD1010
RESET
prior to read/write operations.
36
BDRQ
BUFFER DATA
This output is set to initiate data transfers
to/from the sector buffer.
REQUEST
+ 5V ± 5% Power supply input.
+ 5 volt
40
VCC
Ground.
GROUND
20
VSS
This pin must be left open by the user.
4
NC
NO CONNECTION
This output contains the MFM clock and data
WRITE DATA
21
WD
pulses to be written on the disk.
4.34 or 5.0 MHz clock input used to derive all
25
WC
WRITE CLOCK
internal write timing.
This output is set to a logic high before writing
WRITE GATE
24
WG
is to be performed on the disk.
Precompensation outputs used to delay the WD
EARLY, LATE
EARLY, LATE
23,22
pulses externally.
Data input from the Drive. Both MFM clocks and
READ DATA
37
RD
data pulses are entered on this pin.
A normal square wave clock input derived from
39
RC
READ CLOCK
the external data recovery circuits.
This output is set to a logic high when data is
38
RG
READ GATE
being inspected from the disk.
This input informs the WD1010 when a field of
39
DRUN
DATA RUN
one's or zeroes have been detected.
This output generates a pulse for the stepping
STEP PULSE
27
STEP
motor.
This output determines the direction of the
26
DIR
DIRECTION
stepping motor.
This input must be at a logic high in order for
DRIVE READY
28
DRDY
commands to execute.
An error input to the WD1010 which indicates a
30
WF
WRITE FAULT
fault condition at the drive.
An input to the WD1010 which indicates that
TRACK 000
31
TKOOO
the RIW heads are positioned over the outer~_______--L__________~'________________-L_m_o_s_tc~y~l_in_d_e_r.________________________~
12-19
D7-DO
Data 7 - Data 0
78
-
TABLE 1. INTERFACE SIGNALS
PIN
NUMBER
SYMBOL
-_ .. -
PIN NAME
FUNCTION
:ec
o.....
o
.....
29
INDEX
INDEX PULSE
A logic high on this input informs the WD1010
when the index hole has been encountered.
33
RWC
32
SC
REDUCED WRITE
CURRENT
SEEK COM PLETE
This output can be programmed to reduce write
current on a selected starting cylinder.
This input informs the WD1010 when head
settling time has expired.
~
PROCESSOR INTERFACE DESCRIPTION
The WD1010 controller interfaces to a host or 110
processor via an 8 bit bidirectional data bus. The
buffer memory is also connected to the data bus. The
WD1 01 0 is designed for use with buffer memory and
external bus transceivers. One anticipated system
configuration is shown in Figure 1. In this system,
the processor starts a disk operation by writing task
information into the register file in the controller. The
task information includes the disk cylinder, head,
SElctor numbers, drive number, track number for start
of write precompensation, sector size, and number of
sectors to be transferred. After the task information
has been written, the processor writes the command
into the command register. In the case of a write
sector command, the processor can then read the
controller status register to inspect the buffer data
request flag, and write data into the buffer memory.
When the buffer becomes full, it activates the BRDY
input of the controller. The controller then deac·
tivates the buffer data request (BDRQ) line and activates the BCS line. The buffer chip select (BCS) line
is used both for buffer memory control and for
disabling the data bus, RE and WE buffers. The
controller thus has a direct bus to the buffer memory
which is isolated from the processor data bus. When
the buffered data is transferred to disk and the buffer
memory is empty, the controller enables the tristate
buffers, thus reconnecting the two busses. The
processor can then write more data into the buffer
memory.
The WD1 01 0 disk controller generates control signals for RAM-counter control, data bus control, ECC
processor and DMA control.
TABLE 3. SOH REGISTER
SECTOR
EXTENSION
J
SECTOR DRIVE*
HEAD*
SIZE
NUMBER, NUMBER
BIT7
6
5
1 = ECC
0= CRC
1
0
0
1
1
0
1
0
4
I
3 12
I1 I0
128 byte data field
256 byte data field
512 byte data field
1024 byte data field
* Drive Number and Head Number must be externally
decoded and latched.
DRIVE INTERFACE DESCRIPTION
The WD10'10 disk controller is designed to interface
to SA1000 Winchester disk drives. Winchester drives
with similar interfaces, such as the Seagate
Technology ST506, can also be controlled.
The WD1010 contains MFM encoder/decoder, address mark detector, and high speed shift register
circuitry. Signals are provided to control write
precompensation and write splice avoidance. External Circuitry must provide a phase locked MFM
read clock and high frequency detection. Figure 1
shows a typical controller-drive interface for a system
with two Winchester disk drives.
WD1010 inputs are TTL compatible unless otherwise
noted. WD1010 outputs will drive one TTL unit load.,
STATUS BIT DESCRIPTION
Busy - Active when controller is accessing the disk.
Activated by start of command (writing into comREAD
WRITE
A2 A1 AO
mand register). Deactivated at end of all except read
sector. For read sector, Busy is deactivated when a
0 0 0 Data
Data
sector of data has been transferred to buffer.
Write Precomp Cyl.
0 0 1 Error Flags
Drive Ready - Normally reflects the state of DRDY
Sector Count
0 1 0 Sector Count
pin. After an error interrupt, the state of DRDY is
Sector Number
0 1 1 Sector Number
frozen until the status register is read. The DRDY bit
1 0 0 Cylinder No. Low Cylinder No. Low
then reflects the state of the DRDY pin. An interrupt
1 0 1 Cylinder No. High Cylinder No. High
is generated when reset.
SDH
1 1 0 SOH
Write Fault - Reflects the state of the WF pin. An
Command
1 1 1 Status
interrupt is generated when set.
_1__________________________________________________________
TABLE 2. TASK REGISTER FILE
79
o
,...
o,...
C
~
10 Not Found - Occurs when cylinder, head, sector,
or size parameters cannot be found after 16 index
pulses have been encountered.
TKOOO Error - Occurs when track 0 not found in a
Restore command after 1024 stepping pulses.
Aborted Command - Set if command was started
and one of the following conditions occurred:
1. Drive not ready
2. Write fault
3. Seek complete not active within 16 index pulses
4. Illegal command code
Seek Complete - Reflects the state of the SC pin.
Data Request - Reflects the state of the BDRQ pin.
When active, indicates that a buffer data transfer is
desired. The data request flag is used for programmed 110 while the BDRQ pin is used for DMA
controlled 1/0.
Command in Progress is in progress.
Indicates that a command
Error - Indicates that a bit in the error register has
been set.
ERROR BIT DESCRIPTION
Data AM Not Found - During a read command,
the 10 field for the desired sector has been
found, but the data field address mark was not
found. The data AM should be found within 15
bytes after the 10 field. Refer to Figure 3 for
track format.
Bad Block - A bad block address mark has been
detected when trying to read or write that sector.
Data Field CRC Error - An error in the data field has
been detected. The sector can be re-read to attempt
recovery from a soft error. The data contained in the
buffer can be read but contains errors.
, - - - - - - - - - - - - - - - - - REPEATED N TIMES - - - - - - - - - - - - - .
:
~ ,s.
I
t
I
I
1
MIN. INOEX'-P-UL-S-E--WRITE GATE - - - - - '
L
4) 12 bytes of zeroes are re-written on a Data
Field update.
NOTE:
1) When MSB of head byte = 1, bad block is
detected.
2) Write Gate turn-on is 3 bytes after the 10
field's CRC bytes.
3) Write Gate turn-off is 3 bytes after the Data
Field's CRC bytes.
5) The 2 LSB's of the IDENT byte are used for
Cylinder high. These values are:
FF = 0 to 255 cylinders
FF = 256 to 511 cylinders
FC = 512 to 767 cylinders
FD 768 to 1023 cylinders
6) GAP 3 length is programmable and may range
from 3 bytes to 255 bytes.
FIGURE 3
TRACK FORMAT
TABLE 4. STATUS/ERROR REGISTERS
STATUS
REGISTER
BIT
MSB7
6
5
4
3
2
1
I LSB 0
BUSY
DRIVE READY
WRITE FAULT
SEEK COMPLETE
DATA REQUEST
RESERVED (= 0)
COMMAND IN
PROGRESS
I ERROR
I
I
ERROR
REGISTER
Bad Block
Data Field CRC
Reserved ( = 0)
10 Not Found
Reserved ( = 0)
Aborted Command
TKOOO Error
Data AM Not Found
80
TABLE 5. COMMAND REGISTER
MSB
7 6
COMMAND
RESTORE
SEEK
READ SECTOR
WRITE SECTOR
SCAN 10
WRITE FORMAT
0
1
0
0
1
1
0
0
0
0
0
0
~
o ==
5
4
3
2
1
0
0
1
1
1
0
0
1
1
0
1
0
1
R3
R3
0
0
0
0
R2
R2
M
M
0
0
R1
R1
0
0
0
0
RO
RO
0
0
0
0
1 for DMA; 0 for Programmed 110
M == 1 for multiple sector read or write
R3 R2 R1 RO == 0000
Step time ==
0001
Step time ==
0010
Step time ==
0011
Step time ==
1111
Step time ==
for 5 MHz write clock
C
.....
20 us
.5 ms
1.0 ms
1.5 ms
7.5 ms
2XDR
~ I TRI_S~E BumR
~
H
o
S
T
P
R
o
C
E
S
S
DATA
WD:tUl
~
~--------~~----~ WE
~~~;ERN .-
8
EARLY
~
RWC
WRITE
RECOM
07
RD
RC
DRUN
RG
~kJ;- I- BCS
11
PHASE
LOCK
LOOP
WC f..-I--
C§
IrECODE..1l
o
L1
DATA
RATE
OSC
L(> ./ I---<
INDEX
L:
R
5C~1---<
[RE
DATA_.
WE F I F 0
TKOOO
EMPTY
I ~CS FULL~BRDY
...J--1-!-L-L..,)~=~=W=D=1=5=10=fL/
___-I INTRQ
L
l--------Ba}-i-rt----------------1~
.......... 1---<
-_.---f
..
~
HEADNR
~
WRITE GATE
WGf-~~--~
WD 1010 f-...V""""">-----4
_ _-..
STEP
1--.......-1-+-1,91 DECODER
I'
IL..-_---J
~-~~------------~D
~------~~--.... ~~I~i g~C~ TO
Q hl/H7
1----1 C
(HOLDS DRIVE AND HEAD
~SELECTS)
DATA LATCH
FIGURE 1 .
•
81
o
.....
o
RE~-----~~>---~~----.---------.---'----------------------~~RE
K
WE
fb
WE
H
DATA~---1~~~~-'-+4-----------------__---+--14---------------__,-~/8--~~DO-D7
~I
1
P
R
o
C
E
S
~
~ H::fswE D~_L.._- -_-_-_-"-_-_-....J+----if---IBCR
I
___
WD1010
,h
BRDY
IlDECODE~ I
S
o
R
·~L-----------~--------~~scs
r..
~
ADDR~--~--------------------------------------------------+-T~--~/2----~A~A2
INT
I
~________MR~
I
INTRQ
~M_R________~
TO DATA LATCH
FIGURE 2.
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
82
Printed In U.S.A
WESTERN DIGITAL
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WD1011 Winchester Data Separator Device
FEATURES
II
4.34 OR 5.0 MBIT/SEC DATA RATE
INTERNAL CRYSTAL OSCILLATOR
•
•
•
•
•
SINGLE +5VSUPPLY
FM OR MFM OPERATION
COMPATIBLE WITH THE WD1010
WRITE CLOCK GENERATOR
HIGH FREQUENCY DETECTION
II
GENERAL DESCRIPTION
The WD1011 Winchester Data Separator has been
designed to replace the complex analog/digital circuitry required for data recovery by Winchester disk
drives. Directly interfacing to the WD1010 Winchester
Controller device, an on-Chip crystal oscillator allows
operation of 4.34 Mbitlsec or 5.0 Mbitlsec transfer
rates. In addition to data recovery, the device
provides Write Clock signals for the WD1010 as well
as high frequency detection for pre-amble search.
Output levels on data pins swing close to the supply
rails for increased noise immunity and to minimize
layout restrictions.
The WD1011 operates from a single 5 volt supply and
is available in a 16 pin plastic or ceramic Dual-in-Line
package.
PIN DESIGNATION
See page 725, for ordering information.
83
~
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o
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Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
Implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
84
Printed
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WESTERN DIGITAL
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WD1 012 Write Precompensation Device
FEATURES
• DIRECT INTERFACE TO THE WD1010
• 12 NS. TYP. DELAY FROM EARLY
• PROVIDES TIMCLK FOR SA1000 TYPE DRIVES
• SINGLE + 5V SUPPLY
• TTL COMPATIBLE INPUT/OUTPUTS
• COMPANION CHIP TO THE WD1011 DATA
SEPARATOR
GENERAL DESCRIPTION
The WD1012 Write Precompensation device provides
delayed data necessary for inner cylinder recording
on Winchester disk drives. It is a companion chip to
the Western Digital WD1010, utilizing signals from
both the WD1010 and WD1011 data separator device.
The WRITE DATA output, as well as EARLY, LATE,
and RWC are applied to produce a pre-determined bit
shift. Assertion of EARLY or LATE will cause a 12 ns.
typo shift of data based upon the precompensation
algorithm internal to the WD1010. In addition, a
divide-by-sixteen timing clock output is available for
use by the SA1000 and other drives requiring a
TIMCLK input.
PIN DESIGNATION
The WD1012 operates from a single 5 volt supply and
is available in a 14 pin plastic or ceramic package.
See page 725 for ordering information.
85
:IE
c
......
o......
I\)
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
86
Printed In U S.A
WESTERN DIGITAL
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WD1014 Buffer Manager/Error Correction Device
•
FEATURES
• DIRECT INTERFACE TO THE WD1010
• 32 AND 56 BIT ECC POLYNOMIALS
• 128,256,512, OR 1024 BYTE SECTORS
• BUFFER SIZE UP TO 32K BYTES
• CONTROL FOR 4 DRIVES/8 HEADS EACH
• AUTOMATIC RETRY ON ECC ERRORS
• TRANSPARENT ECC CORRECTION
• MULTI·SECTOR READIWRITE CAPABILITY
• DMA OR PROGRAMMED I/O OPERATION
• 8·BIT TRI·STATE DATA BUS
• EXECUTES 11 MACRO·COMMANDS
• SINGLE + 5V SUPPLY
OAl7
GENERAL DESCRIPTION
The WD1014 is a single chip Buffer Manager/ECC
device designed for use with the Western Digital
Corp. WD1010 Hard Disk Controller. The device
implements all of the logic required for a variable
length sector buffer, ECC correction and Host in·
terface circuitry. Use of the BMEC greatly reduces
the complexity of the interface design, device count,
board size requirements and increases system
reliability.
The WD1014 operates from a single + 5V supply and
is available in a 40 pin plastic or ceramic Dual·in·Line
package.
•
ADO
OAl5
AD1
DAl4
AD2
DAl3
AD3
DAl2
AD4
DAl1
AD5
DAlO
AD6
CS
AD7
RE
WE
I WO'D"I
XCS
XVVE"
Xl!iE"
MR
AO
RCS
A1
ALE
A2
BRDY
INTRa
SBSY
DRa
BING
ClK
XAO
HDS
XA1
VSS
XA2
PIN DESIGNATIONS
87
vcc
OAl6
:ec
.....
PIN
NUMBER
1-8
SYMBOL
DAl7-0
o
.....
~
9
10
11
12
CS
RE
WE
MR
13-15
AO-2
--
16
INTRQ
17
DRQ
18
19
20
21-23
24
ClK
HDS
VSS
XA2-0
BCINC
25
BBSY
26
BRDY
27
ALE
28
RCS
29
XRE
30
XWE
31
32-39
XCS
AD7-0
---
DESCRIPTION
Data Access Lines. Commands, status, and data to and from buffer are
transferred over this tristate bidirectional data bus controlled by the host.
DAl7 is MSB .
Chip Select must be active for all communications with the BMEC.
Read Enable. For reading data and status information from the BMEC.
Write Enable. For writing commands and data to the BM EC.
Master Reset. Initializes the BMEC and clears the status flags when activated.
Address inputs. Used to select task file registers and data buffer. A2, A 1, AO
000 selects buffer. A2 is MSB.
INTerrupt ReQuest. Activated whenever a command has been completed. It
is reset when the status register is read, or when a new command is loaded
via DAl7-0.
Data ReQuest. Set whenever the buffer contains data to be read by the host
or is awaiting data to be written by the host.
Clock signal input used for all internal timing.
Head & Drive Select for setting HSO-3 and DS1-4.
GROUND
These address lines are used to address the disk controller when XCS O.
Buffer Counter INCrement. Increments the external buffer counter. Each
negative transition is a one byte count.
Buffer BuSY. Signals the BMEC that the buffer is being accessed by the
disk controller. It is also used to control ADO-7 bus switching and tristate
XWE, and XRE when it is active.
Buffer ReaDY output. Signals the disk controller when the buffer memory is
ready for controller data transfers. It is active when the buffer memory is
full or empty.
Address latch Enable. Used to set the external buffer address whenever
the buffer is not being accessed by the WD1010 processor.
Ram Chip Select. Asserted when the BMEC or host accesses the external
buffer.
Tristate line activated only when BBSY high. When XCS is low, information is read from the selected WD1010 task files registers.
When RCS is low, data is read from the buffer.
Tristate line activated only when BBSY high. When XCS is low, command
or task file information is written into the disk controller.
When RCS is low data is written into the buffer.
This Chip Select is used to access the disk controller.
Address or Data bus shared by the buffer, BMEC and the WD1010. While
ALE is active a new buffer address is latched in an external counter, where
AD7 A14 and ADO A7. This allows buffer sizes from 128 bytes to 32K
bytes.
+ 5 ± 5% volt power supply.
=
=
=
=
=
40
VCC
=
which is also shared by the WD1010 and drive/head
control latches. The WD1014 manages the external
sector buffer so that it can support all WD1010 sector
sizes in single and multiple sector operations. All
buffer control signals required by the WD1010 are
produced by the BMEC so that no external logic is
required to interface the WD1010 to the BMEC.
FUNCTIONAL DESCRIPTION
The BMEC is designed to interface directly with
industry standard static RAM chips and common
TTLllS latches and counters. The sector buffer, an
integral part of the WD1010 system architecture, is
addressed by a multiplexed data/address bus (ADO-7),
88
During sector reads and writes, the BMEC produces
an Error Correction Code (ECG) as data is transferred
to and from the buffer. The user may select either a
32 or 56 bit polynomial depending upon his needs.
Errors are detected and corrected without intervention by the host. The BMEC controls all retries
on data ECC errors for the host as well. Corrected
errors are reported as a status to the host. Uncorrectable errors are reported by setting the error bit
in the status register with the appropriate descriptor
bit set in the error register.
register. Command execution starts immediately
after the command register is loaded and subsequent register loads are ignored until the command is done. The commands are as follows:
COMMAND
MSB 7 6
Restore
0 0
Seek
0 1
Read Sector
0 0
Write Sector
0 0
ScanlD
0 1
Write Format
0 1
Read Copy
1 0
Write Copy
1 0
Read Long
0 1
Write Long
0 1
Set Parameters
1 1
D = 1: Interrupt for DMA mode
D = 0: Interrupt for programmed 110 mode
M = 1: Multiple Sector Read or Write
E = 1: Select 56 bit ECC polynomial
E = 0: Select 32 bit ECC polynomial
R3 R2 R1 RO
0000
Step time
0001
Step time
0010
Step time
0011
Step time
TASK FILE
A2 A1 AO READ
1 1 1 Status
0 0 1 Error flags
1
1
0
0
1
0
1
0
1
1
1
o
WRITE
Command
Write Precomp
Cylinder
Sector Cou nt
Sector Count
Sector Number
Sector Number
Cylinder Number
Cylinder Number
(low)
(low)
Cylinder Number
Cylinder Number
(high)
(high)
SD H*
SD H*
*S D H bytes specifies sector size, drive
number and head number.
=
I
Br
1
R1
R1
0
0
0
0
0
0
1
1
0
0
RO
RO
E
E
0
0
E
E
E
E
0
= 20l-ls
= .5ms
= 1.0ms
= 1.5ms
1111 : Step time = 7.5ms
for 5 M Hz write clock
THE STATUS AND ERROR REGISTERS
The Status Register indicates to the host the status
of the system. If the Error bit in the Status Register is
set, one or more bits in the Error Register will be set.
The meaning of the these bits is shown below:
The SDH register is coded as follows:
Bit 7 (MSB) is set for a 7 byte sector extension (used
for ECC bytes).
Bits 6 and 5 contain the sector size.
The possible sector sizes and their selection codes
are:
BITS
1
0
1
0
C
.....
o.....
~
BIT CODE
5 4 3 2
0 1 R3 R2
1 1 R3 R2
1 0 D M
1 1 o M
0 0 0 0
0 1 0 0
1 0 o M
1 1 o M
1 0 D 0
1 1 D 0
0 1 0 0
The task file is a set of registers which contain
commands, status, track, sector and other task information. Nine registers are accessed via A2 to AO
during read and write modes. Depending on the
command from the host and the status of the
system, the proper information is stored to or read
from the task file.
0
0
1
~
BIT
MSB 7
6
5
SECTOR SIZE
128 byte data field
256 byte data field
512 byte data field
1024 byte data field
4
3
2
1
LSB 0
Bits 4 and 3 specify Drive Number. These bits are
decoded internally and latched externally to perform
the select function.
Bits 2, 1 and 0 specify Head Number.
STATUS
REGISTER
Busy
Drive ready
Write fault
Seek complete
Data request
Data Error
Corrected
Command in
progress
Error
ERROR
REGISTER
Bad Block Detect
Uncorrectable
CRC Error - ID
Field
ID Not Found
--
Aborted Command
TROOO Error
DAM Not Found
COMMAND DESCRIPTIONS
The BMEC passes on all information between the
host and the WD1010. Some commands are modified
by the BMEC and some are simply echoed. The
following is a list of the commands and their formats
and descriptions.
COMMAND REGISTER
The command register is accessed by writing into
register 7. All other task information should be
loaded into the task file before loading the command
89
COMMAND
RESTORE
SEEK
SCAN 10
READ SECTOR
WRITE SECTOR
READ LONG
WRITE LONG
WRITE COPY
L. _ _ _ _ _ _ _ _ _ _ L
FORMAT
o 0 0 0 R3
DESCRIPTION
Pass on task information and command and initiates a
read status after the command is completed. The
command is echoed. Stepping rate (RO-R3) is set.
Pass on task information and command and initiates a
o 1 1 0 R3 R2 R1 RO
read status after the command is completed. The
command is echoed. Stepping rate (RO-R3) is set.
Passes command to W01010 which scans 10 headers on
01000000
current track. Updates cylinder number in task file and
command and initiates a read status after the command
is completed. The command is echoed.
Write the buffer with data from W01 01 O. If ECC is
00100MOE
enabled, ECC bytes are recomputed by the BMEC. After
the buffer is full, the recorded ECC bytes are compared
to the generated bytes to generate the syndrome bytes.
If thEl syndrome is non-zero, errors have occurred and
error correction is invoked by the BMEC. If the error is
not correctable the BMEC retries the sector read. If the
data is correctable the BMEC corrects the data and
passes the data in the buffer to the host. Read status is
requested by the BMEC and is sent from the W01010 to
the host. If, after a specified number of retries, the error
is still uncorrectable, the BMEC sends an error status to
the host along wtih the status from the W01010.
Write the buffer with data bytes from the host. Pass the
00110MOE
task information and command to the W01010. The
W01010 seeks track if necessary, then writes the sector
from the buffer to disk. Generate the ECC polynomial,
selected by E, as the buffer is written to disc. Write the
total number of sectors specified by the sector count if
M = 1 in format. If M = 0 then the sector count is ignored
and only one sector is written. After the sector data is
-written to the disc, the BMEC sends the W01010 the
ECC bytes. The BMEC requests status from the W01010
and passes on this information to the host at the host's
request.
Similar to Read Sector except the ECC operation
0110001E
producing a syndrome is inhibited in the BMEC. Instead,
the BMEC copies the recorded ECC bytes from disc and
passes them unaltered to the host.
The Write Long command functions similarly to the Write
0111001E
Sector command except the ECC operation of computing
the ECC word is inhibited in the BMEC.lnstead, the BMEC
accepts a 32, or 56 bit appendage from the host and
passes it unaltered to the W01010 to be written on the disc
after the data.
The Write Copy command is similar to the Write Sector
10110MOE
command, except the BMEC does not send a data
request (ORO) to the host at the beginning of the
command. The BMEC assumes it has a full buffer to
write to the disc. The buffer could have been filled by
another device other than the host, such as a back-up
tape or data from another disc. This commands allows
the copying of data from one disc to another with
minimal host intervention.
_ _ _ _ _ _ _ _ _ _ _---.1_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- '
R2 R1 RO
90
COMMAND
FORMAT
DESCRIPTION
READ COPY
10100MOE
The Read Copy command is similar to the Read Sector
command, except the BMEC does not send a data
request (ORO) to the host at the end of the command.
This command, when used with the Write Copy command, allows the copying of data from one disk to
another with minimal host intervention.
The buffer size parameter is specified by the value held in
the sector size task register. The buffer size corresponds
to the sector size task register value multiplied by 128.
(E.G. if the sector size task register value = 1, then it specifies a buffer size of 128 bytes. A 32768 (32K) byte length
buffer is specified by a sector size register value = 0.)
SET PARAMETERS
11010000
ADO·?
--.--
DO·?
RCS
WD1010
Winchester
Controller
......-------+------I~CS
.--------+----I~
RE
.--------~~----I~WE
~------------I~AO
~-----------~~AI
~------------~~A2
~------------~BCS
~-------------~~BRDY
HSO·3
DSO·3
WD1010IWD1014 WINCHESTER CONTROLLER
See page 725 for ordering information.
91
DRIVE
INTERFACE
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Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
£12
Prlnled In U S.A
WESTERN DIGITAL
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WD1050 SMD Controller/Formatter
DESCRIPTION
The WD1050 SMD controller/formatter is aMOS/LSI
device designed to interface an SMD compatible
rigid disk drive to a host processor. The device is
compatible with all rigid disk drives adhering to
Control Data Corporation's flat cable interface for
SMD, MMD, FHT, FMD, LMD and CMD families (CDC
specification 64712400 Rev H). It is TTL compatible
on all inputs and outputs, with interface capability for
8 or 16 bit data busses.
the WD1050 contains a powerful set of macrocommands for read/write and control functions. An
internal 16 bit task file is used to process a selected
command based upon parameter information in the
file.
FEATURES
16 BIT HOST INTERFACE
II
9.677 MBITS/SEC DATA RATE
II
SINGLE/MULTIPLE SECTOR TRANSFERS
II
HARD SECTOR FORMAT
II TTL COMPATIBLE INPUT/OUTPUTS
• SINGLE 5V SUPPLY
• 64 PIN JEDEC CHIP CARRIER PACKAGE
• COMPATIBLE WITH SMD, MMD, FHT, LMD,
AND CMD FAMILIES
II
The WD1050 operates from a single + 5V supply and
is available in a 64 pin J EDEC chip-carrier package.
DATA
110
BUFFER
DO·
D15
CONTROL
PORT
CPOCP9
UNITSEL
PORT
USOUS3
RC
RDS
RD
AO-A2
RDH
'--"--.,/1
C§
FiE ----.
WE--..
BC'S.---t
BCR.---t
BRDY ----i~
BDRO....----t
INTRO....----t
WDH
HOSTI
BUFFER
CONTROL
WDS
CONTROL
UNIT
DRIVE
CONTROL
PORT
Figure 1
BLOCK DIAGRAM
93
WD
SC
TAG 1TAG3
.......-INDEX
.......-SECTOR
.......-FAULT
.......-SKER
.......-ONCYL
-+-URDY
.......-WDROT
""'-UBUSY
.......-USEL
USTAG
ECC
:e
c
PIN
NUMBER
1
Vec
o
2
=RE=-A=-=D:-:E=N-'-A--B-'-L=E
VCC
RE
3
WRITE ENABLE
WE
4
CHIP SELECT
es
5·7
ADDRESS 0-2
AO-A2
8·23
DATA BUSO·15
DO·D15
24
WRITE DATA
WD
25
READ CLOCK
RC
26
SERVO CLOCK
SC
27
READ DATA
RD
28
INDEX PULSE
IP
29
SECTOR
SEC
30
UNIT SELECT
USEL
31
UNIT READY
URDY
32
UNIT BUSY
UBSY
33
34
GROUND
FAULT
VSS
FAULT
35
SEEK ERROR
SKERR
36
ONCYUNDER
ONCYL
37
WRITE PROTECT
WPROT
-""
PIN NAME
CI1
SYMBOL
FUNCTION
+ 5V ± 5% power supply input
Tri·state bidirectional line, used as an input
when reading the task file and an output when
the WD1050 is reading from the buffer.
Tri·state bidirectional line used as an input
when writing to the task file and an output when
the WD1050 is writing to the buffer.
A logic low on this input enables both WE and
RE signals.
These three inputs select a task file register to
receive/transmit data.
Sixteen bit bidirectional bus used for transfer of
commands, status, and data.
Open Drain, NRZ data output which is syn·
chronized to the Servo Clock input.
Input clock from the drive which is syn·
chronized with the Read Data Input.
A nominal 9.677 MHz clock input from the drive.
This clock must be valid when Unit Ready (Pin
31) is active and Fault (Pin 34) is inactive.
NRZ data input from the drive which must be
synchronized to the Read Clock (Pin 25) input.
Active high input used to monitor the Index
signal from the drive.
Active high input used to monitor sector pulses
from the drive.
Active high output pulse used to strobe USO·
US2lines.
Active high input used to inform the WD1050 of
a READY condition on a selected drive. If this
line is made inactive during any command
(except RTZ or FAULT CLEAR), current com·
mand execution is terminated.
Active high input used to monitor drive status
during a unit selection. If the unit had previously
been selected and/or reserved prior to issuing a
USTAG, the UBSY must be made active within
one microsecond of the USTAG selection. This
signal is used for dual·channel access ap·
plications and should be tied to ground when
not used.
Ground.
Active high input used to detect a fault con·
dition at the drive. Command execution is
terminated if fault is made active during any
command. Only the FAULT CLEAR command
may be issued while this line is ascerted.
Active high input used to detect a seek error at
the drive.
Active high input used to inform the WD1050
when the heads are settled and positioned over
the desired cylinder.
Active high input used to monitor the Write
Protect signal from the drive.
o
94
PIN
NUMBER
38
PIN NAME
SYMBOL
ERROR
CORRECTION
UNIT SELECT TAG
USTAG
40-42
TAG1-TAG3
TAG1-TAG3
43-46
UNIT SELECT 0-3
USO-US3
47-56
CONTROL PORT
BITS 9-0
CP9-CPO
57
BACK-BIAS
VBB
58
BUFFER CHIP
SELECT
BUFFER COUNTER
RESET
39
59
ECC
BCS
BCR
BDRQ
62
INTERRUPT
REQUEST
INTRQ
63
MASTER RESET
64
CLOCK
61
---
--
Substrate generator. Must be left open by the
user.
Active low output used to enable reading or
writing to the external buffer.
Active low output that is strobed prior to
read/write commands. Used to clear an external
buffer counter.
This output is set to initiate data transfers
to/from the external buffer.
This input informs the WD1050 that the buffer is
full or empty.
Active high output which is set at the completion of any command, providing the 'I' bit is
also set in the command word.
Active low input used to initialize the WD1050,
usually after a power-up condition.
2 MHz Master Clock from which all timing is
derived.
-
BUFFER DATA
REQUEST
BUFFER READY
60
FUNCTION
Active high output used to synchronize external
ECC logic to the Data Field.
Active high output used for selection of a unit
on USO-US3Iines.
Active high outputs used to strobe specific data
out on the Control Port Lines. Tag definitions
are:
TAG1 -- Cylinder address
TAG2·- Head/volume select
TAG3 - Control Tag
These four outputs reflect the contents of the
unit address field of the task file, and are used
to select one of four drives.
Ten bit output bus used to issue tag parameters
to the selected drive.
BRDY
-
MR
CLK
ORGANIZATION
The Block Diagram of the WD1050 is shown in Figure
1. Data transfers to and from the host, as well as the
sector buffer, are transferred via the DO-D15 lines. An
internal control unit is used to process all commands
and generate drive control signals in the SMD
protocol. With the use of an external sector buffer,
the WD1050 directly transfers data from the buffer to
the read/write lines by the host/buffer control logic.
Four buffer control signals are used to manipulate
the data off.,line from the host processor.
TASK FILE
Inidividual registers within the task file are accessed
via the ~AO lines in conjunction with either Read
Enable (RE) or Write Enable (WE) signals. C..bl2. Select
(CS) must also be made active during an RE or WE
sequence.
The MSB of the address lines (A2) can be used for 8bit operations when interfacing to 8-bit microprocessors. When A2 = 0, 16 bit programming is in effect as
shown in Figure 1. When A2 is toggled, 8-bit
selection is enabled, with data entered on D8-D15
illustrated in Table 2.
95
:ec
....
o
gJ
TABLE 1
:e
c
.....
o
C1I
o
R/W
WE
RE
A2
vvvv-
vvv-
0
0
0
0
0
v-
TASK FILE (16 BIT PROGRAMMING)
ADDRESS
A1
AO
0
1
0
0
0
1
1
1
1
1
WE
RE
vvvvvvvv-
vvvvvv-
vv-
ADDRESS
A2
A1
AO
1
0
1
0
1
0
1
0
1
0
0
0
0
0
1
1
1
1
TASK REGISTER
07
Head Number
Sector Address
Upper Cylinder
Lower Cylinder
Sector Count
Sector Length/Unit Address
Upper Command
Lower Command
Upper Status
Lower Status
0
0
1
1
0
0
1
1
1
1
1
1
COMMAND SET
The W01050 can execute eight macro-commands.
The appropriate task registers are first loaded with
parameter information, then the macro-command is
written into the command register. Table 3 shows the
eight commands, plus a summary of the various flags
used to modify the execution of each command. The
STATUS Register, illustrated in Table 4 allows the
host to monitor key signals and command progress.
Note that the status register is a "Read-Only"
COMMAND
Fault Clear
Return to Zero
Seek Cylinder
Read 10 Field
Read Sector
Write Sector
Format
Verify
LSB
15 14
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
TASK FILE REGISTER
DO
08 07
Sector Address
Lower Cylinder
Section Length/Unit Address
Lower Command
Lower Status
TASK FILE (8 BIT PROGRAMMING)
TABLE 2
R/W
015
Head Number
Upper Cylinder
Sector Count
Upper Command
Upper Status
13
0
0
12
0
1
1
0
0
1
1
0
1
0
1
1
0
1
11
0
V
V
0
R
0
0
0
DO
register, while the command register is a "Write
Only" register. Both these registers share the same
addres~ an~e differentiated by the ascertion of
either RE or WE.
When programmed for the 8-bit mode, two consecutive reads must be accomplished to fetch the
entire status word from the task file. When A2 = 1,
status bits 08-015 are read; when A2
0, status bits
00-07 are read.
=
COMMAND REGISTER BITS
"10
8
7
6
5
9
I
0
0
0
0
0
L
I
0
0
0
0
I
L
0
Z
H
C
L
I
Z
H
0
C
L
I
H
0
Z
C
L
I
H
Z
0
C
p
I
0
Z
H
C
I
P
H
Z
C
0
96
4
0
M
M
M
M
M
M
M
3
U
U
U
U
U
U
U
U
2
S
S
S
S
S
S
S
S
MSB
1
0
E
L
E
L
E
L
E
L
E
L
E
L
E
L
E
L
COMMAND AND FLAG SUMMARY
TABLE 3
:ec
FLAG SUMMARY
v
=
R =
L =
P =
o =
=
=
E
L
Verify
CRC Enable
Logical Sectoring
Programmable Sectors
On Cylinder
Priority Release/Early
Unit DeselecULate
I
Z
C
H
M
U
S
TABLE 4
BIT
15
14
13
12
11
10
U
P
P
E
R
~
o
CJ'I
o
= Head selection
= Marginal data recovery
= Unit Sel/Servo Minus
= Priority Sel/Servo Plus
STATUS WORD SUMMARY
STATUS DESCRIPTION
BUFFER CHIP SELECT STATUS
COMMAND IN PROGRESS
UNIT BUSY
UNIT SELECTED
WRITE PROTECT
UNIT READY
ON CYLINDER
SEEK ERROR
9
8
7
BUFFER CHIP SELECT STATUS
FAULT CONDITION
BUFFER DATA REQUEST STATUS
NOT USED
DATA FIELD CRC ERROR
DATA SYNCH MARK NOT FOUND
ID CRC ERROR
ID NOT FOUND
6
L
0
W
E
R
= Interrupt Enable
= Volume/Head change
= Cylinder Addr
5
4
3
2
1
0
--
FIXED SECTOR FORMAT
HEAD
SCATTER
PLO
SYNC
SYNC
CHAR
10
FIELD
WRITE
SPLICE
PLO
SYNC
SYNC
CHAR
DATA
CRC
1
CRC
2
16
BYTES
11
BYTES
1
BYTE
6
BYTES
2
BYTES
11
BYTES
1
BYTE
128TO
1024 BYTES
1
BYTE
1
BYTE
'00'
'00'
'FE'
'00'
'00'
'FE'
/
- --- ---
, '"
/
/ "
(AIIID Field divisions are 1 byte each)
/
UPPER
CYLADDR
LOWER
CYLADDR
'00'
--- --- --
SECTOR
ADDR
HEAD
See page 725 for ordering information.
97
END
OF
RECORD
2
BYTES
CRC
1
I
CRC
2
I
ENDOF
SECTOR
7
BYTES
(MIN.)
'00'
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
98
Printed In USA
WESTERN DIGITAL
CORPORATION
FD176X-02
Floppy Disk Formatter/Controller Family
•
FEATURES
• 1 MHZ VERSION OF FD179X
• TWO VFO CONTROL SIGNALS - RG & VFOE
• SOFT SECTOR FORMAT COMPATIBILITY
• AUTOMATIC TRACK SEEK WITH VERIFICATION
• ACCOMMODATES SINGLE AND DOUBLE DENSITY
• READ MODE
Single/Multiple Sector Read with Automatic Search or
Entire Track Read
Selectable 128, 256, 512 or 1024 Byte Sector Lengths
• WRITE MODE
Single/Multiple Sector Write with Automatic Sector
Search
Entire Track Write for Diskette Formatting
• SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional Bus for
Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
On-Chip Track and Sector Registers/Comprehensive
Status Information
• PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Side Select Compare
• WRITE PRECOMPENSATION
• WINDOW EXTENSION
• INCORPORATES ENCODING/DECODING AND
ADDRESS MARK CIRCUITRY
• INTERFACES TO WD1691 DATA SEPARATOR
176X·02 FAMILY CHARACTERISTICS
FEATURES
I
DAL 2
DAL3
DAL 4
DAL 5
HLD
RAW READ
DIRC
EARLY
··
____
~~-~s~
AO
I
N
T
E
R
F
A
C
E
~lAT~_
AI
-
CS
RE
P
U
T
E
R
DAL I
WD
+5
WE
r--
~
?
-
S
WPRT
K
WG
-----
?10K
~
L
P
P
Y
D
I
WF/VFOE
-
-
+5V
~
f..
F
0
10K
179X
FLOPPY DISK
CONTROLLER
FORMATTER
10K>
-
EARLY
MR
LATE
-.
iP
TROO
READY
-
TG43
DRa
STEP
INTRa
DIRC
-
I
N
T
E
R
F
A
C
E
~
MR
ClK
Vee (+5VI
',.,6113 = RG;176517
"176317 TRUE BUS
I-~---
-~
~A!,,~
>
DATA (8)
0
M
"DALO
·
51/4" MINI FLOPPY CONTROLLER
SINGLE OR DOUBLE DENSITY
CONTROLLER/ FORMATTER
C
RE
1767
APPLICATIONS
INTRQ
cs
1765
•
•
--•
• - -•
• --------- - -•- -----•
•
•
•
·
•
·
True Data Bus
Inverted Data Bus
Write Precomp
Side Selection Output
40 1 vDDI + 12VI
WE
1763
•
Double Density (MFM)
k
NC [
1761
Single Density (FM)
:~
r
= SSO
~
PIN CONNECTIONS
DDEN
HLD
Hl T
Vss
VDD
VCC
1 I I
+12
FD176X SYSTEM BLOCK DIAGRAM
1_
~
----T
_
-
lONE SHOT
(IF USED)
I
+5V
+5V
..................................................................
99
PIN OUTS
PIN
NUMBER
1
PIN NAME
NO CONNECTION
19
MASTER RESET
20
21
40
POWER SUPPLIES
FUNCTION
SYMBOL
NC
Pin 1 is internally connected to a back bias generator and
must be left open by the user.
A logic low (50 microseconds min.) on this input resets the
device and loads HEX 03 into the command register. The Not
Ready (Status Bit 7) is reset during MR ACTIVE. When MR is
brought to a logic high a RESTORE Command is executed,
regardless of the state of the Ready signal from the drive.
Also, HEX 01 is loaded into sector register.
Vss
Ground
Vee
+5V ±5%
Voo
+ 12V ±5%
WE
A logic low on this input gates data on the DAL into the
selected register when CS is low.
COMPUTER INTERFACE:
2
WRITE ENABLE
A logic low on this input selects the chip and enables
computer communication with the device.
3
4
5,6
READ ENABLE
RE
A logic low on this input controls the placement of data from a
selected register on the DAL when CS is low.
REGISTER SELECT LINES
AO, A1
These inputs select the register to receive/transfer data on the
DAL lines under RE and WE control:
CS
A1
AO
000
o
0
1
010
o 1 1
RE
Status Reg
Track Reg
Sector Reg
Data Reg
WE
Command Reg
Track Reg
Sector Reg
Data Reg
Eight bit Bidirectional bus used for transfer of data, control,
and status. This bus is receiver enabled by WE or transmitter
enabled by RE. Each line will drive 1 standard TTL load.
7-14
24
CLOCK
ClK
This input requires a free-running 1 MHZ ± 1% 50% duty
cycle square wave clock for internal timing reference.
38
DATA REQUEST
DRQ
This open drain output indicates that the DR contains
assembled data in Read operations, or the DR is empty in
Write operations. This signal is reset when serviced by the
computer through reading or loading the DR in Read or Write
operations, respectively. Use 10K pull-up resistor to + 5.
39
INTERRUPT REQUEST
INTRQ
This open drain output is set at the completion of any command and is reset when the STATUS register is read or the
command register is written to. Use 10K pull-up resistor to
+5.
FLOPPY DISK INTERFACE:
15
STEP
STEP
The step output contains a pulse for each step.
16
DIRECTION
DIRC
Direction Output is active high when stepping in, active low
when stepping out.
17
EARLY
EARLY
Indicates that the WRITE DATA pulse occuring while Early is
active (high) should be shifted early for write precompensation.
18
LATE
LATE
Indicates that the write data pulse occurring while Late is
active (high) should be shifted late for write precompensation.
---------~------------------~-----------~-----------------------------------------~
100
-
PIN
NUMBER
22
23
PIN NAME
TEST
HEAD LOAD TIMING
SYMBOL
TEST
HLT
FUNCTION
This input is used for testing purposes only and should be tied
to + 5V or left open by the user unless interfacing to voice coil
actuated steppers.
When a logic high is found on the HLT input the head is
assumed to be engaged. It is typically derived from a 1 shot
triggered by H LD.
25
READ GATE
(1761,1763)
RG
This output is used for synchronization of external data
separators. The output goes high after two Bytes of zeros in
single density, or 4 Bytes of either zeros or ones in double
density operation.
25
SIDE SELECT OUTPUT
(1765,1767)
SSO
The logic level of the Side Select Output is directly controlled
by the'S' flag in Type II or III commands. When U
1, SSO is
set to a logic 1. When U
0, SSO is set to a logic 0. The SSO
is compared with the side information in the Sector 1.0. Field.
If they do not compare Status Bit 4 (RNF) is set. The Side
Select Output is only updated at the beginning of a Type II or
III command. It is forced to a logic upon a MASTER RESET
condition.
=
=
°
26
READ CLOCK
RCLK
A nominal square-wave clock signal derived from the data
stream must be provided to this input. Phasing (Le. RCLK
transitions) relative to RAW READ is important but polarity
(RCLK high or low) is not.
27
RAW READ
RAW READ
The data input signal directly from the drive. This input shall
be a negative pulse for each recorded flux transition.
28
HEAD LOAD
HLD
The HLD output controls the loading of the Read-Write head
against the media.
29
TRACK GREATER THAN 43 TG43
This output informs the drive that the ReadlWrite head is
positioned between tracks 44-76. This output is valid only
during Read and Write Commands.
30
WRITE GATE
WG
This output is made valid before writing is to be performed on
the diskette.
31
WRITE DATA
WD
A 400 ns (MFM) or 1000 ns (FM) output pulse per flux transition. WD contains the unique Address marks as well as data
and clock in both FM and MFM formats.
32
READY
READY
This input indicates disk readiness and is sampled for a logic
high before Read or Write commands are performed. If Ready
is low the Read or Write operation is not performed and an
interrupt is generated. Type I operations are performed
regardless of the state of Ready. The Ready input appears in
inverted format as Status Register bit 7.
33
WRITE FAULT
VFO ENABLE
WFIVFOE
This is a bi-directional signal used to signify writing faults at
the drive, and to enable the external PLO data separator. When
WG
1, Pin 33 functions as a WF input. If WF
0, any write
0, Pin
command will immediately be terminated. When WG
33 functions as a VFOE output. VFOE will go low during a read
operation after the head has loaded and settled (HLT
1). On
the 1765/7, it will remain low until the last bit of the second
CRC byte in the 10 field. VFOE will then go high until 8 bytes
(MFM) or 4 bytes (FM) before the Address Mark. It will then go
active until the last bit of the second CRC byte of the Data
Field. On the 1761/3, VFOE will remain low until the end of the
Data Field. This pin has an internal100K Ohm pull-up resistor.
34
TRACK 00
=
TRoo
=
=
=
This input informs the FD176X that the ReadlWrite head is
positioned over Track 00.
101
'TI
C
.....
......
0')
><
6
N
"..........
C
~
PIN
NUMBER
35
FUNCTION
PIN NAME
INDEX PULSE
IP
SYMBOL
This input informs the FD176X when the index hole is encountered on the diskette.
36
WRITE PROTECT
WPRT
This input is sampled whenever a Write Command is received.
A logic low terminates the command and sets the Write
Protect Status bit.
37
DOUBLE DENSITY
DDEN
This input pin selects either single or double density
operation. When ODEN = 0, double density is selected. When
ODEN = 1, single density is selected.
6N
GENERAL DESCRIPTION
When executing the Seek command the Data Register
holds the address of the desired Track position. This
register is loaded from the DAL and gated onto the
DAL under processor control.
The FD176X are N-Channel Silicon Gate MOS LSI
devices which perform the functions of a Floppy Disk
Formatter/Controller in a single chip implementation.
The FD176X is IBM 3740 compatible in single density
mode (FM) and System 34 compatible in Double
Density Mode (MFM). The FD176X contains all the
features of its predecessor the FD1771, plus the added
features necessary to read/write and format a double
density diskette. These include address mark detection,
FM and MFM encode and decode logic, window extension, and write precompensation. In order to
maintain compatibility, the FDi771, FD1781, and
FD176X designs were made as close as possible with
the computer interface, instruction set, and I/O
registers being identical. Also, head .Ioad control is
identical. In each case, the actual pin assignments vary
by only a few pins from anyone to another.
Track Register - This 8-bit register holds the track
number of the current Read/Write head position. It is
incremented by one every time the head is stepped in
(towards track 76) and decremented by one when the
head is stepped out (towards track 00). The contents of
the register are compared with the recorded track
number in the ID field during disk Read, Write, and
Verify operations. The Track Register can be loaded
from or transferred to the DAL. This Register should
not be loaded when the device is busy.
Sector Register (SR) - This 8-bit register holds the address
of the desired sector position. The contents of the register
are compared with the recorded sector number in the ID
field during disk Read or Write operations. The Sector
Register contents can be loaded from or transferred to the
DAL. This register should not be loaded when the device is
busy.
The processor interface consists of an 8-bit bi-directional bus for data, status, and control word transfers.
The FD176X is set up to operate on a multiplexed bus
with other bus-oriented devices.
Command Register (CR) - This 8-bit register holds the
command presently being executed. This register should
not be loaded when the device is busy unless the new
command is a force interrupt. The command register can
be loaded from the DAL, but not read onto the DAL.
The FD176X is TIL compatible on all inputs and
outputs. The outputs will drive ONE TIL load or three
LS loads. The 1763 is identical to the 1761 except the
DAL lines are TRUE for systems that utilize true data
busses.
Status Register (STR) - This 8-bit register holds device
Status information. The meaning of the Status bits is a
function of the type of command previously executed. This
register can be read onto the DAL, but not loaded from the
DAL.
The 1765/7 has a side select output for controlling
double sided drives.
ORGANIZATION
CRC Logic - This logic is used to check or to generate the
16-bit Cyclic Redundancy Check (CRC). The polynomial is:
G(x) = X'6 + X'2 + x' + 1.
The Floppy Disk Formatter block diagram is illustrated
on page 5. The primary sections include the parallel
processor interface and the Floppy Disk interface.
The CRC includes all information starting with the address
mark and up to the CRC characters. The CRC register is
preset to ones prior to data being shifted through the
circuit.
Data Shift Register - This 8-bit register assembles
serial data from the Read Data input (RAW READ)
during Read operations and transfers serial data to the
Write Data output during Write operations.
Arithmetic/Logic Unit (ALU) - The ALU is a serial comparator, incrementer, and decrementer and is used for
register modification and comparisons with the disk
recorded ID field.
Data Register - This 8-bit register is used as a
holding register during Disk Read and Write operations.
In Disk Read operations the assembled data byte is
transferred in parallel to the Data Register from the
Data Shift Register. In Disk Write operations information is transferred in parallel from the Data
Register to the Data Shift Register.
Timing and Control - All computer and Floppy Disk Interface controls are generated through this logic. The internal device timing is generated from an external crystal
clock.
102
r---~--~~--~---------l--~--~-.---------J-4------<~
WRITE DATA
(TO OISK!
'---------------------------«
RCLK
TG43
~O~_ _ _
COMPUTER
INTERFACE
CONTROL
CONTROL
PLA
CONTROL
CONTROL
(230 X 16)
DISK
INTERFAce
REAOY
CONTRu~
STEP
EARLY
..
..
I----=---~RGlSSQ
FD176X BLOCK DIAGRAM
The FD176X has two different modes of operation according to the state of DDEN. When DDEN = 0 double
density (MFM) is assumed. When DDEN = 1, single
density (FM) is assumed.
combined with the signals RE during a Read operation or
WE during a Write operation are interpreted as selecting
the following registers:
A1 - AO
AM Detector - The address mark detector detects 10, data
and index address marks during read and write operations.
°
PROCESSOR INTERFACE
The interface to the processor is accomplished through the
eight Data Access Lines (DAL) and associated control
signals. The DAL are used to transfer Data, Status, and
Control words out of, or into the FD176X. The DAL are three
state buffers that are enabled as output drivers when Chip
Select (CS) and Read Enable (RE) are active (low logic state)
or act as input receivers when CS and Write Enable (WE)
are active.
0
0
1
1
1
0
1
READ(RE)
Status Register
Track Register
Sector Register
Data Register
WRITE (WE)
Command Register
Track Register
Sector Register
Data Register
During Direct Memory Access (DMA) types of data
transfers between the Data Register of the FD176X and the
processor, the Data Request (DRO) output is used in Data
Transfer control. This signal also appears as status bit 1
during Read and Write operations.
On Disk Read operations the Data Request is activated (set
high) when an assembled serial input byte is transferred In
parallel to the Data Register. This bit is cleared when the
Data Register is read by the processor. If the Data Register
is read after one or more characters are lost, by having new
When transfer of data with the Floppy Disk Controller is
required by the host processor, the device address is
decoded and CS is made low. The addres~ bits A1 and AO,
103
During read operations (WG = 0), the VFOE (Pin 33) is
provided for phase lock loop synchronization. VFOE will go
active low when:
a) Both HLT and HLD are True
b) Settling Time, if programmed, has expired
c) The 176X is inspecting data off the disk
data transferred into the register prior to processor readout,
the Lost Data bit is set in the Status Register. The Read
operation continues until the end of sector is reached.
On Disk Write operations the data Request is activated
when the Data Register transfers its contents to the Data
Shift Register, and requires a new data byte. It is reset
when the Data Register is loaded with new data by the
processor. If new data is not loaded at the time the next
serial byte is required by the Floppy Disk, a byte of zeroes
is written on the diskette and the Lost Data bit is set in the
Status Register.
If WFIVFOE is not used, this pin may be left open, as it has
an internal pull-up resistor.
GENERAL DISK WRITE OPERATION
When writing is to take place on the diskette the Write Gate
(WG) output is activated, allowing current to flow into the
ReadlWrite head. As a precaution to erroneous writing the
first data byte must be loaded into the Data Register in
response to a Data Request from the FD176X before the
Write Gate Signal can be activated.
At the completion of every command an INTRa is
generated. INTRa is reset by either reading the status
register or by loading the command register with a new
command. In addition, INTRa is generated if a Force
Interrupt command condition is met.
Writing is inhibited when the Write Protect input is a logic
low, in which case any Write command is immediately
terminated, an interrupt is generated and the Write Protect
status bit is set. The Write Fault input, when activated,
signifies a writing fault condition detected in disk drive
electronics such as failure to detect write current flow
when the Write Gate is activated. On detection of this fault
the FD176X terminates the current command, and sets the
Write Fault bit (bit 5) in the Status Word. The Write Fault
input should be made inactive when the Write Gate output
becomes inactive.
The 176X has two modes of operation according to the
state of DDEN (Pin 37). When DDEN = 1, single density is
selected. In either case, the CLK input (Pin 24) is at 1 MHz.
GENERAL DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 are obtainable in
either FM or MFM formats. For FM, DDEN should be
placed to logical "1." For MFM formats, DDEN should be
placed to a logical "0." Sector lengths are determined at
format time by the fourth byte in the "ID" field.
For write operations, the FD176X provides Write Gate (Pin
30) and Write Data (Pin 31) outputs. Write data consists of a
series of 1000 ns pulses in FM (DDEN = 1) and 400 ns
pulses in MFM (DDEN = 0). Write Data provides the unique
address marks in both formats.
Sector Length Table*
Sector Length
Field (hex)
00
01
02
03
Number of Bytes
in Sector (decimal)
128
256
512
1024
Also during write, two additional signals are provided for
write precompensation. These are EARLY (Pin 17) and
LATE (Pin 18). EARLY is active true when the WD pulse
appearing on (Pin 30) is to be written EARLY. LATE is active
true when the WD pulse is to be written LATE. If both
EARLY and LATE are low when the WD pulse is present,
the WD pulse is to be written at nominal. Since write
precompensation values vary from disk manufacturer to
disk manufacturer, the actual value is determined by
several one shots or delay lines which are located external
to the FD176X. The write precompensation signals EARLY
and LATE are valid for the duration of WD in both FM and
MFM formats.
*1765/67 may vary - see command summary.
The number of sectors per track as far as the FD176X is
concerned can be from 1 to 255 sectors. The number of
tracks as far as the FD176X is concerned is from 0 to 255
tracks.
For read operations in 5%" double density the FD176X
requires RAW READ Data (Pin 27) signal which is a 400 ns
pulse per flux transition and a Read clock (RCLK) signal to
indicate flux transition spacings. The RCLK (Pin 26) signal
is provided by some drives but if not it may be derived
externally by Phase lock loops, one shots, or counter
techniques. In addition, a Read Gate Signal is provided as
an output (Pin 25) on 1761/63 which can be used to inform
phase lock loops when to acquire synchronization. When
reading from the media in FM, RG is made true when 2
bytes of zeroes are detected. The FD176X must find an
address mark within the next 10 bytes; otherwise RG is
reset and the search for 2 bytes of zeroes begins all over
again. If an address mark is found within 10 bytes, RG
remains true as long as the FD176X is deriving any useful
information from the data stream. Similarly for MFM, RG is
made active when 4 bytes of "00" or" FF" are detected. The
FD176X must find an address mark within the next 16
bytes, otherwise RG is reset and search resumes.
READY
Whenever a Read or Write command (Type II or III) is
received the FD176X samples the Ready input. If this input
is logic low the command is not executed and an interrupt
is generated. All Type I commands are performed regardless of the state of the Ready input. Also, whenever a
Type II or III command is received, the TG43 signal output
is updated.
COMMAND DESCRIPTION
The FD176X will accept eleven commands. Command
words should only be loaded in the Command Register
when the Busy status bit is off (Status bit 0). The one
104
exception is the Force Interrupt command. Whenever a
command is being executed, the Busy status bit is set.
When a command is completed, an interrupt is generated
and the Busy status bit is reset. The Status Register
indicates whether the completed command encountered
an error or was fault free. For ease of discussion,
commands are divided into four types. Commands and
types are summarized in Table 1.
."
.........
C
0')
TABLE 1.
Bits
~-ype Command
Restore
Seek
Step
Step-in
Step-out
Read Sector
Write Sector
Read Address
Read Track
Write Track
Force Interrupt
6I\)
B Commands for Models: 1765, 1767
A Commands for Models· 1761 1763
I
I
I
I
I
II
II
III
III
III
IV
><
COMMAND SUMMARY
Bits
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
T
T
T
m
m
0
0
1
11
h
h
h
h
h
S
S
0
0
0
13
V
V
V
V
V
E
E
E
r1
r1
r1
r1
q
C
C
0
0
0
11
E
E
12
0
rO
rO
ro
rO
ro
0
ao
0
0
0
10
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
T
T
T
m
m
0
0
1
1
h
h
h
h
h
L
L
0
0
0
13
V
V
V
V
V
E
E
E
E
E
12
r1
rO
ro
rO
ro
rO
0
aO
0
0
0
10
q
r1
r1
r1
U
U
U
U
U
11
TABLE 2. FLAG SUMMARY
FLAG SUMMARY
Command
Type
Bit
No(s)
I
0,1
I
2
V = Track Number Verify Flag V = 0, No verify
V = 1, Verify on destination track
I
3
h = Head Load Flag
h = 1, Load head at beginning
h = 0, Unload head at beginning
I
4
T = Track Update Flag
T = 0, No update
T = 1, Update track register
11&111
0
aO = Data Address Mark
aO = 0, FB (DAM)
ao = 1, F8 (deleted DAM)
II
1
C = Side Compare Flag
C = 0, Disable side compare
C = 1, Enable side compare
11&111
1
U = Update
11&111
2
E = 30 MS Delay
E = 0, No 30 MS delay
E = 1,30 MS delay
II
3
S = Side Compare Flag
S = 0, Compare for side 0
S = 1, Compare for side 1
II
3
L = Sector Length Flag
Description
r1 rO = Stepping Motor Rate
See Table 3 for Rate Summary
sse
U = 0, Update
U = 1, Update
I
IL =0
IL = 1
105
sse to 0
sse to 1
LSB's Sector Length in ID Field
01
10
00
11
512
256
1024
128
256
512
1024
128
FLAG SUMMARY
Command
Type
Bit
No(s)
II
4
IV
0-3
Description
m
= Multiple Record
Ix
10
11
12
13
13.11
Flag
m
m
= 0, Single record
= 1, Multiple records
= Interrupt Condition Flags
= 1 Not Ready To Ready Transition
= 1 Ready To Not Ready Transition
= 1 Index Pulse
= 1 Immediate Interrupt, Requires A Reset
= Terminate With No Interrupt (INTRa)
°
* NOTE: See Type IV Command Description for further information.
status bit is set (Status bit 3), and the next encountered 10
field is read from the disk for the verification operation.
TYPE I COMMANDS
The Type I Commands include the Restore, Seek, Step,
Step-In, and Step-Out commands. Each of the Type I
Commands contains a rate field (rO r1), which determines
the stepping motor rate as defined in Table 3.
The FD176X must find an 10 field with correct track number
and correct CRC within 5 revolutions of the media;
otherwise the seek error is set and an INTRa is generated.
If V = 0, no verification is performed.
A 4 /-As (MFM) or 8 /-AS (FM) pulse is provided as an output to
the drive. For every step pulse issued, the drive moves one
track location in a direction determined by the direction
output. The chip will step the drive in the same direction it
last stepped unless the command changes the direction.
The Head Load (HLD) output controls the movement of the
read/write head against the media. HLD is activated at the
beginning of a Type I command if the h flag is set (h = 1), at
the end of the Type I command if the verify flag (V = 1), or
upon receipt of any Type II or III command. Once HLD is
active it remains active until either a Type I command is
and V
0); or if the FD176X is in an
received with (h
idle state (non-busy) and 15 index pulses have occurred.
The Direction signal is active high when stepping in and
low when stepping out. The Direction signal is valid 24 /-AS
before the first stepping pulse is generated.
=
The rates (shown in Table 3) can be applied to a StepDirection Motor through the device interface.
0
A1 AO
TEST =1
TEST=1
TEST=O
368!,-s
0
0
6 ms
6 ms
0
1
12 ms
12 ms
380!,-s
1 0
20 ms
20 ms
396!,-s
1
30 ms
30 ms
416!,-s
1
=
Head Load timing (HLT) is an input to the FD176X which is
used for the head engage time. When H LT = 1, the FD176X
assumes the head is completely engaged. The head
engage time is typically 30 to 100 ms depending on drive.
The low to high transition on HLD is typically used to fire a
one shot. The output of the one shot is then used for H LT
and supplied as an input to the FD176X.
TABLE 3_ STEPPING RATES
DDEN
°
HLDIt-- - - - - '
~50T0100mS_____1
f- - -
-1/
i-- - - - - -
HL T (FROM ONE SHOT)
After the last directional step an additional 30 milliseconds
of head settling time takes place if the Verify flag is set in
Type I commands. If TEST = 0, there is zero settling time.
There is also a 30 ms head settling time if the E flag is set in
any Type II or III command.
HEAD LOAD TIMING
When both HLD and HLT are true, the FD176X will then
read from or write to the media. The "and" of HLD and HLT
appears as status Bit 5 in Type I status.
When a Seek, Step or Restore command is executed an
optional verification of Read-Write head position can be
performed by settling bit 2 (V = 1) in the command word to
a logic 1. The verification operation begins at the end of thEl
30 millisecond settling time after the head is loaded against
the media The track number from the first encountered 1[1
Field is compared against the contents of the Track
Register. If the track numbers compare and the 10 Field
Cyclic Redundancy Check (CRG) is correct, the verify
operation is complete and an INTRa is generated with no
errors. If there is a match but not a valid CRC, the CRC error
=
°
=
In summary for the Type I commands: if h
and V
0,
HLD is reset. If h
1 and V
0, HLD is set at the
beginning of the command and HLT is not sampled nor is
there an internal 30 ms delay. If h = and V = 1, HLD is
set near the end of the command, an internal 30 ms occurs,
and the FD176X waits for HLT to be true. If h = 1 and V =
1, HLD is set at the beginning of the command. Near the
end of the command, after all the steps have been issued,
an internal 30 ms delay occurs and the FD176X then waits
for HLT to occur.
=
=
°
106
For Type II and III commands with E flag off, HLD is made
active and HLT is sampled until true. With E flag on, HLD is
made active, an internal 30 ms delay occurs and then HLT
is sampled until true.
be loaded at the start of command. Note that the Restore
command is executed when MR goes from an active to an
inactive state and that the ORO pin stays low.
RESTORE (SEEK TRACK 0)
SEEK
Upon receipt of this command the Track 00 (TROO) input is
sampled. If TRaa is active low indicating the Read-Write
head is positioned over track a, the Track Register is loaded
with zeroes and an interrupt is generated. If TROO is not
active low, stepping pulses (pins 15 to 16) at a rate specified
by the r1 ra field are issued until the TRaa input is activated.
At this time the Track Register is loaded with zeroes and an
interrupt is generated. If the TRaa input does not go active
low after 255 stepping pulses, the FD176X terminates
operation, interrupts, and sets the Seek error status bit
providing the V flag is set. A verification operation also
takes place if the V flag is set. The h bit allows the head to
This command assumes that the Track Register contains
the track number of the current position of the Read-Write
head and the Data Register contains the desired track
number. The FD176X will update the Track register and
issue stepping pulses in the appropriate direction until the
contents of the Track register are equal to the contents of
the Data Register (the desired track location). A verification
operation takes place if the V flag is on. The h bit allows the
head to be loaded at th~ start of the command. An interrupt
is generated at the completion of the command. Note:
When using multiple drives, the track register must be
updated for the drive selected before seeks are issued.
TYPE I COMMAND FLOW
TYPE I COMMAND FLOW
-
107
."
C
....
~
6
I\)
."
..........
C
~
oI\)
STEP
STEP·OUT
Upon receipt of this command, the FD176X issues one
stepping pulse to the disk drive. The stepping motor
direction is the same as in the previous step command .
After a delay determined by the r1 ro field, a verification
takes place if the V flag is on. If the U flag is on, the Track
Register is updated. The h bit allows the head to be loaded
at the start of the command. An interrupt is generated at
the completion of the command.
Upon receipt of this command, the FD176X issues one
stepping pulse in the direction towards track O. If the U flag
is on, the Track Register is decremented by one. After a
delay determined by the r1 rO field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.
EXCEPTIONS
On the 176517 devices, the SSO output is not affected
during Type 1 commands, and an internal side compare
does not take place when the (V) Verify Flag is on.
STEp·IN
Upon receipt of this command, the FD176X issues one
stepping pulse in the direction towards track BO. If the U
flag is on, the Track Register is incremented by one. After a
delay determined by the r1 ro field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.
VERIFY
SEQUENCE
* NOTE: IF 'i'ESTo, THERE IS N030 MS DELAY
NOTE: IF TEST 0, THERE IS NO 30 MS DELAY
IF TEST 1, THERE IS A 30 MS DELAY
IFTEST 1, THERE IS A 30 MS DELAY
TYPE I COMMAND FLOW
TYPE II COMMAND
108
lYPE II COMMANDS
The 1765/7 READ SECTOR and WRITE SECTOR commands include a 'L' flag. The 'L' flag, In conjunction with
the sector length byte of the ID Field, allows different byte
lengths to be implemented in each sector. For IBM
compatability, the 'L' flag should be set to a one.
The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command
into the Command Register, the computer must load the
Sector Register with the desired sector number. Upon
receipt of the Type II command, the busy status Bit is set. If
the E flag = 1 (this is the normal case) HLD is made active
and HLT is sampled after a 30 msec delay. If the E flag is 0,
the head is loaded and HLT sampled with no 30 msec
delay. The ID field and Data Field format are shown on page
16.
"....
C
........
~
6I\)
When an ID field is located on the disk, the FD176X
compares the Track Number on the ID field with the Track
Register. If there is not a match, the next encountered ID
field is read and a comparison is again made. If there was a
match, the Sector Number of the ID field is compared with
tile Sector Register. If there is not a Sector match, the next
encountered ID field is read off the disk and comparisons
again made. If the ID field CRC is correct, the data field is
tllen located and will be either written into, or read from
depending upon the command. The FD176X must 'find an
ID field with a Track number, Sector number, side number,
and CRC within four revolutions of the disk; otherwise, the
Record not found status bit is set (Status bit 3) and the
command is terminated with an interrupt.
Each of the Type II Commands contains an (m) flag which
determines if multiple records (sectors) are to be read or
written, depending upon the command. If m = 0, a single
sector is read or written and an interrupt is generated at the
completion of the command. If m = 1, multiple records are
read or written with the sector register internally updated
so that an address verification can occur on the next
mcord. The FD176X will continue to read or write multiple
mcords and update the sector register in numerical
ascending sequence until the sector register exceeds the
number of sectors on the track or until the Force Interrupt
command is loaded into the Command Register, which
terminates the command and generates an interrupt.
For example: If the FD176X is instructed to read sector 27
and there are only 26 on the track, the sector register exceeds the number available. The FD176X will search for 5
disk revolutions, interrupt out, reset busy, and set the
record not found status bit.
The Type II commands for 1761-63 also contain side select
compare flags" When C = (Bit 1) no side comparison is
made. When C = 1, the LSB of the side number is read off
the ID Field of the disk and compared with the contents of
the (S) flag (Bit 3). If the S flag compares with the side
number recorded in the ID field, the FD176X continues with
the ID search. If a comparison is not made within 5 index
pulses, the interrupt line is made active and the RecordNot-Found status bit is set.
°
TYPE II COMMAND
READ SECTOR
Upon receipt of the Read Sector command, the head is
loaded, the Busy status bit set, and when an ID field is
encountered that has the correct track number, correct
sector number, correct side number, and correct CRC, the
data field is presented to the computer. The Data Address
Mark of the data field must be found within 30 bytes in
single density and 43 bytes in double density of the last ID
field CRC byte; if not, the ID field is searched for and
verified again followed by the Data Address Mark search. If
after 5 revolutions the DAM cannot be found, the Record
Not Found status bit is set and the operation is terminated .
The Type II and III commands for the 1765-67 contain a side
select flag (Bit 1). When U = 0, SSO is updated to 0.
Similarly, U = 1 updates SSO to 1. The chip compares the
SSO to the 10 field. If they do not compare within 5
revolutions the interrupt line is made active and the RNF
status bit is set.
•
109
WRITE SECTOR
SEQUENCE
READ SECTOR
SEQUENCE
INTRQ. RESET BUSY
SET CRe ERROR
TYPE II COMMAND
TYPE II COMMAND
When the first character or byte of the data field has been
shifted through the DSR, it is transferred to the DR, and
DRO is generated. When the next byte is accumulated in
the DSR, it is transferred to the DR and another DRO is
generated. If the Computer has not read the previous
contents of the DR before a new character is transferred
that character is lost and the Lost Data Status bit is set.
This sequence continues until the complete data field has
been inputted to the computer. If there is a CRC error at the
end of the data field, the CRC error status bit is set, and the
command is terminated (even if it is a multiple record
command).
WRITE SECTOR
Upon receipt of the Write Sector command, the head is
loaded (H LD active) and the Busy status bit is set. When an
ID field is encountered that has the correct track number,
correct sector number, correct side number, and correct
CRC, a DRO is generated. The FD176X counts off 11 bytes
in single density and 22 bytes in double density from the
CRC field and the Write Gate (WG) output is made active if
the DRO is serviced (Le., the DR has been loaded by the
computer). If DRO has not been serviced, the command is
terminated and the Lost Data status bit is set. If the DRO
has been serviced, the WG is made active and six bytes of
zeroes in single density and 12 bytes in double density are
then written on the disk. At this time the Data Address
Mark is then written on the disk as determined by the ao
field of the command as shown below:
At the end of the Read operation, the type of Data Address
Mark encountered in the data field is recorded in the Status
Register (Bit 5) as shown below:
STATUS
BIT5
1
o
Deleted Data Mark
Data Mark
110
ao
Data Address Mark (Bit 0)
1
o
Deleted Data Mark
Data Mark
TYPE III COMMANDS
The F0176X then writes the data field and generates ORa's
to the computer. If the ORO Is not serviced In time for
continuous writing the Lost Data Status Bit Is set and a
byte of zeroes Is written on the dlsk~The command Is not
terminated. After the last data byte has been written on the
disk, the two-byte CRC Is computed Internally and written
on the disk followed by one byte of logic ones In FM or In
MFM. The WG output Is then deactivated. For a 1 MHz
clock the INTRa will set 16 to 24 ",sec after the last CRC
byte Is written.
READ ADDRESS
."
Upon receipt of the Read Address command, the head
Is loaded and the Busy Status Bit Is set. The next
encountered 10 field Is then read In from the disk, and
the six data bytes of the 10 field are assembled and
transferred to the DR, and a ORO Is generated for each
byte. The six bytes of the 10 field are shown below:
~
TRACK
ADDR
*If partial sectors are to be written, the proper method Is to write the data and fill the
balance of the secte,r with zeroes. Do not let the chip supply the filler by not ser·
vlclng the DROs. Doing this will mask any errors by the lost data status and the
CRC's may be Incorrect.
1
111
SIDE
SECTOR
NUMBER ADDRESS
2
3
SECTOR CRC CRC
LENGTH
1
2
4
5
6
....C
"......
C
...I.
Q')
><
6
Although the CRC characters are transferred to the
computer, the FD176X checks for validity and the CRC
error status bit is set if there is a CRC error. The Track
Address of the ID field is written into the sector
register so that a comparison can be made by the
user. At the end of the operation an interrupt is
generated and the Busy Status is reset.
loaded and the Busy Status bit is set. Writing starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse, at which time the
interrupt is activated. The Data Request is activated immediately upon receiving the command, but writing will not
start until after the first byte has been loaded into the Data
Register. If the DR has not been loaded by the time the
index pulse is encountered the operation is terminated
making the device Not Busy, the lost Data Status Bit is set,
and the Interrupt is activated. If a byte is not present in the
DR when needed, a byte of zeroes is substituted. See note
on page 12.
N
READ TRACK
Upon receipt of the READ track command, the head is
loaded, and the Busy Status bit is set. Reading starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse. All Gap, Header, and
data bytes are assembled and transferred to the data
register and DRO's are generated for each byte. The accumulation of bytes is synchronized to each address mark
encountered. An interrupt is generated at the completion of
the command.
This sequence continues from one index mark to the next
index mark. Normally, whatever data pattern appears in the
data register is written on the disk with a normal clock
pattern. However, if the FD176X detects a data pattern of
F5 thru FE in the data register, this is interpreted as data
address marks with missing clocks or CRC generation.
This command has several characteristics which make it
suitable for diagnostic purposes. They are: the Read Gate
is not activated during the command; no CRC checking is
performed; gap information is included in the data stream;
the internal side compare is not performed; and the address mark detector is on for the duration of the command.
Because the A.M. detector is always on, write splices or
noise may cause the chip to look for an A.M. If an address
mark does not appear on schedule the lost Data status flag
is set.
The CRC generator is initialized when any data byte from
F8 to FE is about to be tranferred from the DR to the DSR in
FM or by receipt of F5 in MFM. An F7 pattern will generate
two CRC characters in FM or MFM. As a consequence, the
patterns F5 thru FE must not appear in the gaps, data
fields, or ID fields. Also, CRC's must be generated by an F7
pattern.
Disks may be formatted in IBM 3740 or System 34 formats
with sector lengths of 128, 256, 512, or 1024 bytes.
The ID A.M., ID field, ID CRC bytes, DAM, Data, and Data
CRC Bytes for each sector will be correct. The Gap Bytes
may be read incorrectly during write-splice time because
of synchronization.
TYPE IV COMMANDS
The Forced Interrupt command is generally used to terminate a multiple sector read or write command or to insure Type I status in the status register. This command can
be loaded into the command register at any time. If there is
a current command under execution (busy status bit set)
the command will be terminated and the busy status bit
reset.
WRITE TRACK FORMATIING THE DISK
(Refer to section on Type III commands for flow diagrams.)
Formatting the disk is a relatively simple task when
operating programmed 110 or when operating under DMA
with a large amount of memory. Data and gap information
must be provided at the computer interface. Formatting the
disk is accomplished by positioning the RJW head over the
desired track number and issuing the Write Track command.
The lower four bits of the command determine the conditional interrupt as follOWS:
10 = Not-Ready to Ready Transition
11 = Ready to Not-Ready Transition
12 = Every Index Pulse
13 = Immediate Interrupt
Upon receipt of the Write Track command, the head is
CONTROL BYTES FOR INITIALIZATION
DATA PATIERN
IN DR (HEX)
00 thru F4
F5
F6
F7
F8 thru FB
FC
FD
FE
FF
FD176X INTERPRETATION
IN FM (DDEN
1)
=
Write 00 thru F4 with ClK ~ FF
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write F8 thru FB, Clk C7, Preset CRC
Write FC with Clk
D7
Write FD with Clk
FF
Write FE, Clk
C7, Preset CRC
Write FF with Clk
FF
=
=
=
=
=
* Missing clock transition between bits 4 and 5
FD176X INTERPRETATION
IN MFM (DDEN
0)
=
Write 00 thru F4, in MFM
Write A1* in MFM, Preset CRC
Write C2* * in MFM
Generate 2 CRC bytes
Write F8 thru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM
* *Missing clock transition between bits 3 & 4
112
READ TRACK
SEQUENCE
."
o
.....
......,
0)
><
6I\)
INTRQ
RESET BUSY
SHIFT ONE BIT
INTO DSR
SET INTRQ
RESET BUSY
SET HLD
YES
DELAY 30 MS'
TG43
UPDATE
[
.~
<
NO
READ
ADDRESS
'II' TEST= ~, NO DELAY
TYPE III COMMAND
IITEST = 1,30 MS DELAY
Read Track/Address
•
113
"T1
The conditional interrupt is enabled when the corresponding bit positions of the command (13 - 10) are set to
a 1. Then, when the condition for interrupt is met, the INTRa line will go high signifying that the condition specified
has occurred. If 13 - 10 are all set to zero (HEX DO), no interrupt will occur but any command presently under
execution will be immediately terminated. When using the
immediate interrupt condition (13 = 1) an interrupt will be
immediately generated and the current command terminated. Reading the status or writing to the command
register will not automatically clear the interrupt. The HEX
DO is the only command that will enable the immediate
interrupt (HEX 08) to clear on a subsequent load command
register or read status register operation. Follow a HEX 08
with DO command.
READ ADDRESS
SEQUENCE
C
......
......
0)
~
o
N
RESET BUSY
SET INTRa
SET RNF
Wait 16 micro sec (double density) or 32 micro sec (single
density before issuing a new command after issuing a
forced interrupt. Loading a new command sooner than this
will nullify the forced interrupt.
Forced interrupt stops any command at the end of an internal micro-instruction and generates INTRa when the
specified condition is met. Forced interrupt will wait until
ALU operations in progress are complete (CRC calculations, compares, etc.).
More than one condition may be set at a time. If for
example, the READY TO NOT-READY condition (11 = 1)
and the Every Index Pulse (12 = 1) are both set, the
resultant command would be HEX "DA". The "OR" function is performed so that either a READY TO NOT- READY
or the next Index Pulse will cause an interrupt condition.
SET ORa
STATUS REGISTER
Upon receipt of any command, except the Force Interrupt
command, the Busy Status bit is set and the rest of the
status bits are updated or cleared for the new command. If
the Force Interrupt Command is received when there is a
current command under execution, the Busy status bit is
reset, and the rest of the status bits are unchanged. If the
Force Interrupt command is received when there is not a
current command under execution, the Busy Status bit is
reset and the rest of the status bits are updated or cleared.
In this case, Status reflects the Type I commands.
The user has the option of reading the status register
through program control or using the ORO line with DMA or
interrupt methods. When the Data register is read the ORO
bit in the status register and the ORO line are automatically
reset. A write to the Data register also causes both ORa's
to reset.
The busy bit in the status may be monitored with a user
program to determine when a command is complete, in
lieu of using the INTRa line. When using the INTRa, a busy
status check is not recommended because a read of the
status register to determine the condition of busy will reset
the INTRa line.
TYPE III COMMAND
Read Track/Address
114
The format of the Status Register is shown below:
NUMBER
OF BYTES
~
Status varies according to the type of command executed
as shown in Table 4.
.
Because of internal sync cycles, certain time delays must
be observed when operating under programmed I/O. They
are:
Operation
Next Operation
Write to
Command Reg.
Read Busy Bit
(Status Bit 0)
Write to
Command Reg.
Read Status
Bits 1·7
Write Any
Register
Read From Ditt.
Register
- - - - - - " - -" - ' - - - - - - - - - - - - -
RECOMMENDED -
Delay Req'd.
I
FM
MFM
I
24/As
I
I
12/As
r----__~-I_ _ _ _
56/As
:
28/As
40
~
1
1
1
1
1
1
11
6
1
128
1
~
369··
4E
00
F5 (Writes A 1)
FE (10 Address Mark)
Track Number (0 thru 4C)
Side Number(O or 1)
Sector Number (1 thru 1A)
01 (Sector Length)
F7 (2 CRCs written)
4E
00
F5 (Writes A 1)
FB (Data Address Mark)
DATA
F7 (2 CRCs written)
4E
4E
I
0
I
I
I
0
*Write bracketed field 16 times
• *Continue writing until FD176X interrupts out.
Approx. 668 bytes.
128 BYTES/SECTOR
Shown below is the recommended single·density format
with 128 bytes/sector. In order to format a diskette, the user
must issue the Write Track command, and load the data
register with the following values. For every byte to be
written, there is one Data Request.
NUMBER
OF BYTES
12
3
1
1
1
1
1
1
22
12
3
1
256
1
~
718**
HEX VALUE OF
BYTE WRITIEN
1. NON·STANDARD FORMATS
Variations in the recommended formats are possible to a
limited extent if the following requirements are met:
1) Sector size must be 128, 256, 512 of 1024 bytes.
2) Gap 2 cannot be varied from the recommended format.
HEX VALUE OF
BYTE WRITIEN
3) 3 bytes of A1 must be used in MFM.
FF(orOO)'
00
FE (10 Address Mark)
Track Number
Side Number (00 or 01)
Sector Number(1 thru 1A)
00 (Sector Length)
F7 (2 CRC's written)
FF (or 00)'
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF(oroo)'
FF(oroo)'
In addition, the Index Address Mark is not required for
operation by the FD176X. Gap 1, 3, and 4 lengths can be as
short as 2 bytes for FD176X operation, however PLL lock up
time, motor speed variation, write-splice area, etc. will add
more bytes to each gap to achieve proper operation. It is
recommended that the recommended format be used for
highest system reliability.
·Write bracketed field 16 times
• ·Continue writing until FD176X interrupts out.
Approx. 324 bytes.
·'·Optiona"oo' on 1765/7 only.
256 BYTES/SECTOR
Shown below is the recommended dual·density format
with 256 bytes/sector. In order to format a diskette the user
must issue the Write Track command and load the data
register with the following values. For every byte to be
written, there is one data request.
FM
MFM
Gapl
16 bytes FF
32 bytes4E
Gap/l
11 bytes FF
22 bytes4E
*
*
6 bytes 00
12 bytes 00
3 bytes A1
Gap 111**
10 bytes FF
4 bytes 00
24 bytes4E
8 bytes 00
3 bytes A1
Gap IV
16 bytes FF .
16 bytes4E
* Byte counts must be exact.
* * Byte counts are minimum, except exactly 3
must be written.
115
byte~
of A 1
-n
131
C
.....
CRC
BYTE 2
DATA FIELD
RECORD
.......
~16
0)
~
CRC
BYTE 1
130
0
N
GAP 2
(HEX
00)
126 BYTES
2-129
DATA FIELD
RECORD
83
GAP 2
10
RECORD
~3
GAP 3
OF USER
DATA
DATA FIELD
BYTE
~
(HEX
FF)
T
6 BYTES
t
WRITE TURN-OFF
FOR UPDATE OF
PREVIOUS DATA FIELD
10 BYTES
1
'''''"''''
~ ""'"
ADDRESS MARK
DATA FIELD
RECORD
82
CRC
BYTE 2
GAP 2
(HEX 00)
10
RECORD
H2
CRC
BYTE 1
GAP 3
DATA GAP
16 BYTES
DATA FIELD
RECORD
H1
-t=
- --
SECTOR
LENGTH
(HEX
FF)
GAP 2· 10
GAP 17
BYTES
10
RECORD
81
--
SECTOR
NUMBER
10 RECORD
BYTE
GAP 1
POST
INDEX
BYTES
46
SIDE
NUMBER
T
6 BYTES
t\
1
GAP 4
PRE-INDEX
369 BYTES
PHYSICAL INDEX
10
ADDRESS
MARK
(HEX
00)
(HEX FF)
T
6 BYTES
t
40 BYTES
1
RECOMMENDED SINGLE DENSITY FORMAT
116
TURN-ON FOR UPDATE
OF NEXT DATA FIELD
11 BYTES
TRACK
NUMBER
46 BYTES
W",TE GATE
."
GAP 4
254
CRC
BYTE 2
255
CRC
BYTE 1
C
~
.......
DATA FIELD
RECORD
~
o
N16
GAP 2
~
T
__
A1_--1
N
~F
12 BYTES
(HEX 00)
WRITE GATE
TURN·ON FOR UPDATE
OF NEXT DATA FIELD
256 BYTES
OF USER
DATA
DATA FIELD
RECORD
BYTE
#3
GAP2
10
~
24 BYTES
(HEX 4E)
RECORD
N3
~
DATA OR
DELETED DATA
ADDRESS MARK
1
GAP 3
"----.11
DATA FIELD
RECORD
#2
T
CRC
BYTE 2
GAP 2
(HEX
00)
10
12 BYTES
RECORD
#2
CRC
BYTE 1
DATA FIELD
RECORD
N1
GAP 3
DATA GAP
39 BYTES
RECORD
#1
SECTOR
NUMBER
f
PHYSICAL INDEX
WRITE TURN·OFF
FOR UPDATE OF
PREVIOUS DATA FIELD
,--_{H_E_X_4E_)---'
I~
BYTE
A1"
3 BYTES
72 BYTES
\
SECTOR
LENGTH
GAP 2
10
GAP 34
BYTES
10
-- - --
SIDE
NUMBER
GAP 1
POST
INDEX
72 BYTES
TRACK
NUMBER
GAP 4
PRE·INDEX
718 BYTES
T
10
ADDRESS
MARK
HEX FE
t-_{H_E_X_00_)
~ t~
____(_HE_X_4E_)- . I
RECOMMENDED DOUBLE DENSITY FORMAT
117
T'
TIMING CHARACTERISTICS
TA
= O°C to 70°C, VDD = + 12V ±
.6V, Vss
= OV, Vee = + SV ±
.2SV
READ ENABLE TIMING (See Note 4, Page 22)
SYMBOL
TSET
THLD
TRE
TORR
TIRR
TDACC
TDOH
CHARACTERISTIC
MIN.
Setup ADDR & CS to RE
Hold AD DR & CS from RE
RE Pulse Width
ORO Reset from RE
INTRa Reset from RE
Data Access from RE
Data Hold from RE
50
10
400
TYP.
400
1000
50
MAX.
UNITS
500
6000
350
150
nsec
nsec
nsec
nsec
nsec
nsec
nsec
CONDITIONS
CL
= 50 pf
CL
CL
= 50 pf
= 50 pf
VOH
TIRR'-"--~
~
t15AIT
ISERVICE
-----+---1
NOTE
,
CS MAY
NOTE: , CS MAY BE PERMANENTLY TiED LOW IF
DESIRED 2 WHEN WRITING DATA INTO
SECTOR TRACK OR OATA REGISTER USER
CANNOT READ THIS REGISTER UNTIL AT
LEAST 8 ,..SEC IN MFM AFTER THE RISING
BE PERMANENTl Y TIED LOW IF DESIRED
t SERVICE (WORST CASE)
t SERVtCE (WORST CASEl
'FM
'FM = 235 uS
"MFM ~ 11 SuS
275 uS
'MFM - 135uS
ORa RISING eDGE: INDICATES THAT THE DATA REGISTER HAS ASSE-MBLED
eDGE OF WE WHEN WRITING INTO THE
COMMAND REGISTER STATUSJS NOT VALID
~Z;~~.SOME 56 "SEC IN FM. 28 ".SEC IN MFM
ORO RISING EDGE: INDICATES THAT THE DATA REGISTER IS EMPTY
ORO FALLING EDGE: INDICATES THAT THE DATA REGISTER IS LOADED
INTRa RISING EDGE: INDICATE THE END OF A COMMAND
INTRQ FALLING EDGE: INDICATES THAT THE COMMAND REGISTER
IS WRlnEN TO
DATA.
ORO FALLING EDGE: tNDICATES THAT THE DATA REGISTER WAS READ
INTRa RISING EDGE: OCCURS AT END OF COMMAND
INTRQ FALLING EDGE: INDICATES THAT THE STATUS REGISTER WAS READ
READ ENABLE TIMING
WRITE ENABLE TIMING
WRITE ENABLE TIMING (See Note 4, Page 22)
SYMBOL
TSET
THLD
TWE
TORR
TIRR
TDS
TDH
CHARACTERISTIC
MIN.
Setup ADDR & CS to WE
Hold ADDR & CS from WE
WE Pulse Width
ORO Reset from WE
INTRa Reset from WE
Data Access from WE
Data Hold from WE
50
10
350
TYP.
400
1000
250
70
118
MAX.
500
6000
UNITS
nsec
nsec
nsec
nsec
nsec
nsec
nsec
CONDITIONS
INPUT DATA. TIMING (See Note 4, Page 21)
SYMBOL
CHARACTERISTIC
MIN.
Tpw
tbc
Tc
Raw Read Pulse Width
Raw Read Cycle Time
RClK Cycle Time
TX1
TX2
RClK hold to Raw Read
Raw Read hold to RClK
tDW
RAWFiEAi5"
RCLK
--1
~
TXt
100
3000
3000
U
1==
200
4000
4000
(IMHZ)
r
I
WD
--l
-I"
---------l
Tb
CONDITIONS
nsec
nsec
nsec
See Note 1
3600 ns @ 70 D C
36OOns@
70 D C, See Note
2
See Note 1
See Note 1
r--
ClK
Lf
UNITS
nsec
nsec
TXL----I
I_To
I"
MAX.
40
40
",
I----I I-
TYP.
la.._____....t,
500 NS--1
L
_~~~ I L.....-'-~~01L..___
-1 1 rTwdl
Twd2
Te
WD MUST HAVE RISING EDGE IN FIRST SHADED AREA AND
TRAILING EDGE IN SECOND SHADED AREA.
NOMINAL
MODE
DDEN
ClK
Ta
Tb
To
MFM
FM
0
1
1 MHz
1 MHz
2 JAs
4 JAs
2 JAs
4 JAs
4 JAs
8 JAs
WRITE DATA/CLOCK RELATIONSHIP IN DOUBLE DENSITY (DDEN = 0)
WRITE DATA TIMING
INPUT DATA TIMING (See Note 3, Page 22)
WRITE DATA TIMING (See Note 4, Page 22)
SYMBOL
CHARACTERISTICS
Twp
Write Data Pulse Width
Twg
Write Gate to Write Data
Tbc
Ts
Th
Twf
Write data cycle Time
Early (late) to Write Data
Early (late) From
Write Data
Write Gate off from WD
Twdl
Twd2
WD Valid to Clk
WD Valid after ClK
MIN.
TYP.
MAX.
1000
400
4
2
4,6, or 8
250
250
4
2
100
100
UNITS
CONDITIONS
nsec
nsec
JAsec
JAsec
JAsec
nsec
nsec
FM
MFM
FM
MFM
±ClK Error
MFM
MFM
JAsec
JAsec
nsec
nsec
FM
MFM
-MISCELLANEOUS TIMING (See Note 4, Page 22)
SYMBOL
TCD1
TCD2
TSTP
TDIR
TMR
TIP
TWF
CHARACTERISTIC
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Clock Duty (low)
Clock Duty (high)
Step Pulse Output
Dir Setupt to Step
Master Reset Pulse Width
Index Pulse Width
Write Fault Pulse Width
460
400
4 or 8
500
500
20000
20000
nsec
nsec
JAsec
JAsec
JAsec
JAsec
JAsec
± ClK ERROR
24
50
10
20
119
-<-_.--
'TI
C
.....
iP
S
WF
s
""
CD
X
NOTES:
5
VIH
l
1. Pulse width on RAW READ (Pin 27) is normally 100-300
ns. However, pulse may be any width pulse is entirely
within window. If pulse occurs in both windows, then
pulse width must be less than 600 ns for MFM at ClK =
1 MHz and 1200 ns for FM at 1 MHz.
2. tbc should be 4/As, nominal in MFM and B /As nominal in
FM.
3. RClK may be high or low during RAW READ (Polarity is
unimportant).
4. All timing readings at VOL
.BV & VOH
2.0V.
!--T1P-l
0
N
5
VIH
!--TWF-!
SVIH
MR
=
j--TMR--i
=
!-TCYC"'"
CLK~
-fTC01~
-
I---
TC0
2
MISCELLANEOUS TIMING
'FROM STEP RATE TABLE
Table 4. STATUS REGISTER SUMMARY
BIT
S7
S6
S5
S4
S3
S2
S1
SO
ALL TYPE I
COMMANDS
READ
ADDRESS
NOT READY
WRITE
PROTECT
HEAD LOADED
SEEK ERROR
CRC ERROR
TRACK 0
INDEX PULSE
BUSY
READ
SECTOR
READ
TRACK
NOT READY
0
NOT READY
0
NOT READY
0
0
RNF
CRC ERROR
LOST DATA
DRO
BUSY
RECORD TYPE
RNF
CRC ERROR
LOST DATA
DRO
BUSY
0
0
0
LOST DATA
DRO
BUSY
WRITE
SECTOR
NOT READY
WRITE
PROTECT
WRITE FAULT
RNF
CRC ERROR
LOST DATA
DRO
BUSY
WRITE
TRACK
NOT READY
WRITE
PROTECT
WRITE FAULT
0
0
LOST DATA
DRO
BUSY
STATUS FOR TYPE I COMMANDS
BIT NAME
MEANING
S7 NOT READY
S6 PROTECTED
S5 HEAD LOADED
S4 SEEK ERROR
S3CRC ERROR
S2TRACKOO
S11NDEX
SO BUSY
This bit when set indicates the drive is not ready. When reset it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and logically 'ored' with MR.
When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.
When set, it indicates the head is loaded and engaged. This bit is a logical "and" of
HLD and HLTsignals.
When set, the desired track was not verified. This bit is reset to 0 when updated.
CRC encountered in ID field.
When set, indicates ReadlWrite head is positioned to Track O. This bit is an inverted
copy of the TROO input.
When set, indicates index mark detected from drive. This bit is an inverted copy of the
IPinput.
When set command is in progress. When reset no command is in progress.
120
STATUS FOR TYPE II AND III COMMANDS
MEANING
BIT NAME
87 NOT READY
This bit when set indicates the drive is not ready. When reset, it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and 'ored' with MR. The Type II
and III Commands will not execute unless the drive is ready.
86 WRITE PROTECT On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a Write
Protect. This bit is reset when updated.
85 RECORD TYPE!
On Read Record: It indicates the record-type code from data field address mark. 1
WRITE FAULT
Deleted Data Mark. 0
Data Mark. On any Write: It indicates a Write Fault. This bit is
reset when updated.
84 RECORD NOT
When set, it indicates that the desired track, sector, or side were not found. This bit is
FOUND (RNF)
reset when updated.
83 CRC EFtROR
If 84 is set, an error is found in one or more 10 fields; otherwise it indicates error in data
field. This bit is reset when updated.
82 L08TDATA
When set, it indicates the computer did not respond to DRQ in one byte time. This bit
is reset to zero when updated.
81 DATA REQUE8T
This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read
Operation or the DR is empty on a Write operation. This bit is reset to zero when updated.
80 BU8Y
When set, command is under execution. When reset, no command is under execution.
=
=
ELECTRICAL CHARACTERISTICS
CIN & COUT = 15 pF max with all pins grounded except
one under test.
Operating temperature = O°C to 70°C
Storage temperature = - 55°C to + 125°C
Absolute Maximum Ratings
V 00 with repect to V ss (ground): + 15 to - 0.3V
Voltage to any input with respect to Vss = + 15 to - 0.3V
lee = 60 MA (35 MA nominal)
100 = 15 MA (10 MA nominal)
OPERATING CHARACTERISTICS (DC)
TA
= O°C to 70°C, Voo = + 12V ±
SYMBOL
IlL
10L
VIH
VIL
VOH
VOL
Po
.6V, Vss
= OV, Vee = + 5V ±
CHARACTERISTIC
Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Dissipation
.25V
MIN.
MAX.
UNITS
10
10
I1A
I1A
V
V
V
V
2.6
0.8
2.8
0.45
0.6
W
CONDITIONS
VIN
VOUT
= Voo**
= Voo
--
= -100I1A
= 1.0 mA
10
10
-
• * Leakage conditions are for input pins without internal pull-up resistors. Pins 22, 23, 33, 36, and 37 have pullup resistors. See
Tech Memo #115 for testing purposes.
See page 725 for ordering information.
121
'TI
C
.....
......
en
~
o
N
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rigtlts of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
122
Pnnled
In
U S.A
WESTERN DIGITAL
c
o
R
p
o
A
R
T
/
o
N
"
C
-a.
FD1771-01 Floppy Disk Formatter/Controller
......
.......
•
-a.
FEATURES
6-a.
APPLICATIONS
•
SOFT SECTOR FORMAT COMPATIBILITY
•
FLOPPY DISK DRIVE INTERFACE
4.
AUTOMATIC TRACK SEEK WITH VERIFICATION
•
•
READ MODE
Single/Multiple Sector Write with Automatic
Sector Search or Entire Track Read
Selectable 128 Byte or Variable Length Sector
SINGLE OR MULTIPLE DRIVE
CONTROLLER/FORMATTER
•
NEW MINI-FLOPPY CONTROLLER
~.
I.
•
GENERAL DESCRIPTION
The FD1771 is a MOS/LSI device that performs the
functions of a Floppy Disk Controller/Formatter.
The device is designed to be included in the disk
drive electronics, and contains a flexible interface
organization that accommodates the interface signals from most drive manufacturers. The FD1771 is
compatible with the IBM 3740 data entry system
format.
WRITE MODE
Single/Multiple Sector Write with Automatic
Sector Search
Entire Track Write for Diskette Formatting
PROGRAMMABLE CONTROLS
Selectable Track-to-Track Stepping Time
Selectable Head Settling and Head Engage
Times
Selectable Three Phase or Step and Direction
and Head Positioning Motor Controls
The processor interface consists of an 8-bit bidirectional bus for data, status, and control word
transfers. The FD1771 is set up to operate on a multiplexed bus with other bus-oriented devices.
SYSTEM COMPATIBILITY
Double Buffering of Data 8-Bit Bi-Directional
Bus for Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
The FD1771 is fabricated in N-channel Silicon Gate
MOS technology and is TTL compatible on all inputs
and outputs. The A and B suffixes are for ceramic
and plastic packages, respectively.
k
vaa (- 5V)
WE
CS
F'iE
AO
A1
DALO
DAI::1
DAL2
DAL3
DAL4
DAI~
DAI::6
DAL7
PH1/STEP
PH21DIRC
PH3
3PM
MR
(GND)VSS
VDD(+ 12V)
INTRQ
DRQ
DINT
WPRT
DATA 161
FD DATA
~
~rDClOCK
AO
Al
cs
COMPUTER
INTERFACE
FiE
-5V
--
WE
iP
~
-~
FLOPPY DISK
CONTROllER
FORMATTER
WD
MR
TROO
WF
READY
WD
WG
TG43
HlD
--
WG
WPI1T
Vir' ----
---
Il'
il'fC)()
-w
FD1771
.
TEST
VC(+5V)
.-
-_.---
TG 48
10K:
FDDATA
FDClK
XTDS
ClK
HlT
READY
10K
I------_PJ:i~_._
PH2 DIRC
DRO
.
PH8
INTRO
ClK 12MHZI
:WM
61ID
-----
-~
-~
"
HLD
Vss V BB VDD Vec
PIN CONNECTIONS
1- I5 -12I -5r
FD1771 SYSTEM BLOCK DIAGRAM
123
1
~_~
HLT _ _
ONE
SHOT
(IF
USED)
1
FLOPPY
DISK
DRIVE
PIN OUTS
c.....
'......""
......
.....
Pin Name
Pin No.
1
19
Power Supplies
MASTER RESET
~/NC
6.....
20
21
40
Function
Symbol
VSS
VCC
VOO
-5V
A logic low on this input resets the device and loads
"03" into the command register. The Not Ready
(Status bit 7) is reset during MR ACTIVE. When Kim
is brought to a logic high, a Restore Command is
executed. regardless of the state of the Ready signal
from the drive.
Ground
+5V
+12V
Computer Interface
2
WRITE ENABLE
WE
A logic low on this input gates data on the OAL into
the selected register when CS is low.
3
CHIP SELECT
CS
A logic low on this input selects the chip and enables
computer communication with the device.
4
READ ENABLE
RE
A logic low on this input controls the placement of
data from a selected register on the OAL when CSis
low.
5, 6
REGISTER SELECT
LINES
Ao, A1
These inputs select the register to receive/transfer
data on the OAL lines under RE and WE control:
A1 Ao
RE
WE
o 0 Status Register
Command Register
o 1 Track Register
Track Register
0
Sector Register
Sector Register
1
1
1
Data Register
Data Register
7-14
DATA ACCESS LINES
::"O-:"A-:-L""'0"""'-O""""A""'L':.7' Eight bit inverted bidirectional bus used for transfer
of data, control, and status. This bus is a receiver
€lnabled by WE or a transmitter enabled by RE.
24
CLOCK
CLK
This input requires a free-running 2 MHz± 1% square
wave clock for internal timing reference.
38
DATA REQUEST
ORQ
This open drain output indicates that the DR contains assembled data in Read operations, or the DR
is empty in Write operations. This signal is reset
when serviced by the computer through reading or
loading the DR in Read or Write operation, respectively. Use 10K pull-up resistor to +5.
39
INTERRUPT REQUEST INTRQ
This open drain output is set at the completion or
termination of any operation and is reset when a
new command is loaded into the command register.
Use 10K pull-up resistor to +5.
Floppy Disk Interface:
15
Phase 1/Step
PH1/STEP
16
Phase 2/0irection
PH2/0lRC
17
Phase 3
PH3
18
3-Phase Motor Select
3PM
If the 3PM input is a logic low the three-phase motor
control is selected and PH1, PH2, and PH3 outputs
form a one active low signal outofthree. PH1 is active
low after MR. If the 3PM input is a logic high the step
and direction motor control is selected. The step
output contains a 4 usec high signal for each step
and the direction output is active high when stepping
in; active low when stepping out.
124
Pin No.
Pin Name
Symbol
Function
."
22
TEST
TEST
This input is used for testing purposes only and
should be tied to +5V or left open by the user.
23
HEAD LOAD TIMING
HLT
The HL T input is sampled after 10 ms. When a logic
high is sampled on the HLT input the head is assumed
to be engaged.
25
EXTERNAL OAT A
SEPARATION
XTDS
A logic low on this input selects external data
separation. A logic high or open selects the internal
data separator.
26
FLOPPY DISK CLOCK
(External Separation)
FDCLOCK
This input receives the externally separated clock
when XTDS = O. If XTDS =1, this input should be tied
to a logic high.
27
FLOPPY DISK OAT A
FDDATA
This input receives the raw read disk data if XTDS=1 ,
or the externally separated data if XTDS=O.
28
HEAD LOAD
HLD
The HLD output controls the loading of the ReadWrite head against the media.
29
Track Greater than 43
TG43
This output informs the drive that the Read-Write
head is positioned between tracks44-76. This output
is valid only during Read and Write commands.
30
WRITE GATE
WG
This output is made valid when writing is to be performed on the diskette.
31
WRITE DATA
WD
This output contains both clock and data bits of
500 ns duration.
32
Ready
READY
This input indicates disk readiness and is sampled
for a logic high before Read or Write commands are
performed. If Ready is low, the Read or Write operation is not performed and an interrupt is generated.
A Seek operation is performed regardless of the state
of Ready. The Ready input appears in inverted format
as Status Register bit 7.
33
WRITE FAULT
WF
This input detects wiring faults indications from the
drive. When WG=1 and WF goes low, the current
Write command is terminated and the Write Fault
status bit is set. The WF input should be made inactive
(high) when WG becomes inactive.
34
TRACK 00
TROO
This input informs the FD1771 that the Read-Write
head is positioned over Track 00 when a logic low.
35
INDEX PULSE
if>
Input, when low for a minimum of 10 usec, informs
the FD1771 when an index mark is encountered on
the diskette.
36
WRITE PROTECT
WPRT
This input is sampled whenever a Write command is
received. A logic low terminates the command and
sets the Write Protect status bit.
37
DISK INITIALIZATION
DINT
The iput is sampled whenever a Write Track command is received. If DINT=O, the operation is terminated and the Write Protect status bit is set.
125
....
.....
.....
C
....
....
6
loaded from or transferred to the DAL. This Register
should not be loaded when this device is busy.
ORGANIZATION
."
.........
C
......
.....
6
...
The Floppy Disk Formatter block diagram is illustrated on page 4. The primary sections include the
parallel processor interface and the Floppy Disk
interface.
Data Shift Register: This 8-bit register assembles serial data from the Read Data input (FDDATA) duriing
Read operations and transfers serial data to the
Write Data output during Write operations.
Sector Register (SR): This 8-bit register holds the
address of the desired sector position. The contents
of the register are compared with the recorded sector number in the 10 field during disk Read or Write
operations. The Sector Register contents can be
loaded from or transferred to the DAL. This register
should not be loaded when the device is busy.
Data Register: This 8-bit register is used as a holding
register during Disk Read and 'write operations. In
Disk Read operations the assembled data byte is
transferred in parallel to the Data Register from the
Data Shift Register. In Disk Write operations information is transferred in paralle'l from the Data Register to the Data Shift Register.
Command Register (CR): This 8-bit register holds
the command presently being executed. This register should not be loaded when the .device is busy
unless the execution of the current command is to be
overridden. This latter action results in an interrupt.
The command register can be loaded from the DAL,
but not read onto the DAL.
When executing the Seek command, the Data Register holds the address of the desired Track position.
This register can be loaded from the DAL and gated
onto the DAL under processor control.
Status Register (STR): This 8-bit register holds
device Status information. The meaning of the Status bits are a function of the contents of the Command Register. This register can be read onto the
DAL, but not loaded from the DAL.
Track Register: This 8-bit register holds the track
number of the current Read/Write head position. It is
incremented by one every time the head is stepped in
(towards track 76) and decremented by one when
the head is stepped out (towards track 00). The contents of the register are compared with the recorded
track number in the 10 field during disk Read, Write,
and Verify operations. The Track Register can be
CRC Logic: This logic is used to check or to generate
the 16-bit Cyclic Redundancy Check (CRC). The
polynomial is: G(x) = X 16 + X12 + x 5 + 1.
The CRC includes all information starting with the
address mark and up to the CRC characters. The
CRC register is preset to ones prior to data being
shifted through the circuit.
}
(DAL)
~
•
BUFFERS
•I
r
l
DATA
REG\
t
H
~
ICOMMAND
REG
,
DATA
REG
SHIFT
t
REG~
r-1 TRACK
REG
l
.....~
,
I
4-
f.-t
INTRa
..fs
-~
AO
Al
t
STATUS
CRC LOGIC
L
DATA
SEPARATOR
-.--~
WF
DISK
INTERFACE
CONTROL
TIMING AND
CONTROL
CONTROL
-.
CONTROL
~
jl:i
TROO
READY
PH1/STEP
PH2/DIRC
PH3
3 PM
rnm
~
HLD
HLT
--
CLK (2 MHZ)
FD1771 BLOCK DIAGRAM
126
FD CLOCK
XTDS
We;.
TG43
Wl5R'
COMPUTER
INTERFACE
CONTROL
;\
REG
~"
U
ORO
MR
I
AM
DETECTOR
WRITE DATA
(TO DISK)
i
t
T
r-1SECTOR
Arithmetic/Logic Unit (ALU): The ALU is a serial
comparator, incrementer, and decrementer and is
used for reg~ster modification and comparisons with
the disk recorded 10 field.
at the time the next serial byte is required by the
Floppy Disk, a byte of zeroes is written on the
diskette and the Lost Data bit is set in the Status
Register.
AM Detector: The Address Mark detector is used to
detect 10, Data, and Index address marks during
Read and Write operations.
The Lost Data bit and certain other bits in the Status
Register will activate the interrupt request (INTRa).
The interrupt line is also activated with normal completion or abnormal termination of all controller
operations. The INTRa signal remains active until
reset by reading the Status Register to the processor
or by the loading of the Command Register. In addition, the INTRa is generated if a Force Interrupt
command condition is met.
Timing and Control: All computer and Floppy Disk
Interface controls are generated through this logic.
The internal device timing is generated from a 2.0
MHz external crystal clock.
PROCESSOR INTERFACE
The interface to the processor is accomplished
through the eight Data Access Lines (DAL) and
associated control signals. The DAL are used to
transfer Data, Status, and Control words out of, or
into the FD1771. The DAL are three-state buffers that
are enabled as output drivers when Chip Select (CS)
and Read Enable (RE) are active (low logic state) or
act as input receivers when CS and Write Enable
(WE) are active.
FLOPPY DISK INTERFACE
The Floppy Disk interface consists of head positioning controls, write gate controls, and data transfers.
A 2.0 MHz ± 1% square wave clock is requred at the
CLK input for internal control timing (may be 1.0
MHz for mini floppy).
HEAD POSITIONING
Four commands cause pOSitioning of the ReadWrite head (see Command Section). The period of
each positioning step is specified by the rfield in bits
1 and 0 of the command word. After the last directional step, an additional 10 milliseconds of head settling time takes place. The four programmable
stepping rates are tabulated below.
When transfer of data with the Floppy Disk Controller is required by the host processor, the device
address is decoded and CS is made low. The leastsignificant address bits A 1 and AO, combined with
the signals RE during a Read operation orWEduring
a Write operation are interpreted as selecting the following registers:
A1·AO
0 0
0 1
1 0
1 1
READ (RE)
Status Register
Track Register
Sector Register
Data Register
The rates (shown in Table 1) can be applied to a
Three-Phase Motor or a Step-Direction Motor through
the device interface. When the ~ input is connected to ground, the device operates with a threephase motor control interface, with one active low
Signal per phase on the three output signals PH1,
PH2, and PH3. The stepping sequence, when stepping in, is Phases 1-2-3-1, and when stepping out,
Phases 1-3-2-1. Phase 1 is active low after Master
Reset. Note: PH3 needs an inverter if used.
WRITE (WE)
Command Register
Track Register
Sector Register
Data Register
During Direct Memory Access (DMA) types of data
transfers between the Data Register of the FD1771
and the Processor, the Data Request (ORa) output is
used in Data Transfer control. This signal also
appears as status bit 1 during Read and Write
operations.
The Step-Direction Motor Control interface is activated by leaving input 3PM open or connecting it to
+5V. The Phase 1 pin PH1 becomes a Step pulse of 4
microseconds width. The Phase 2 pin PH2 becomes
a direction control with a high voltage on this pin
indicating a Step In, and a low voltage indicating a
Step Out. The Direction output is valid a minimum of
24 /-Ls prior to the activation of the Step pulse.
On Disk Read operations the Data Request is activated (set high) when an assembled serial input byte
is transferred in parallel to the Data Register. This bit
is cleared when the Data Register is read by the processor. If the Data Register is read after one or more
characters are lost, by having new data transferred
into the register prior to processor readout, the Lost
Data bit is set in the Status Register. The Read operation continues until the end of sector is reached.
When a Seek, Step or Restore command is executed,
an optional verification of Read-Write head position
can be performed by setting bit 2 in the command
word to a logic 1. The verification operation begins at
the end of the 10 millisecond settling time after the
head is loaded against the media. The track number
from the first encountered 10 Field is compared
against the contents of the Track Register. If the
track numbers compare and the 10 Field Cyclic
Redundancy Check (CRC) is correct, the verify
operation is complete. If track comparison is not
On Disk Write operations the Data Request is activated when the Data Register transfers its contents
to the Data Shift Register, and requires a new data
byte. It is reset when the Data Register is loaded with
new data by the processor. If new data is not loaded
•
127
."
C
.....
......
......
.....
6
.....
data, as supplied by methods such as Phase Lock
loop, One Shots, or variable frequency oscillators.
This is accomplished by grounding the External
Data Separator (XTDS) INPUT. When the Read Data
input makes a high-to-Iow transition, the information input to the FDDATA line is clocked into the
Data Shift Register. The assembled 8-bit data from
the Data Shift Register are then transferred to the
Data Register.
made but the CRC checks, an interrupt is generated,
the Seek Error status (Bit 4) is set and the Busy status
bit is reset.
Table 1. STEPPING RATES
r1 rO
0 0
0 1
1 0
1 1
1771-X1
1771-X1
1771 or - X1 1771 or -X1
ClK=2MHz ClK= 1 MHz ClK= 2 MHz ClK= 1 MHz
TEST= 1
TEST = 1
TEST=O
TEST=O
6ms
12ms
Approx.
Approx.
6ms
12ms
400/1s'
800/1s'
10ms
20ms
20ms
40ms
The normal sector length for read or Write operations with the IBM 3740 format is 128 bytes. This format or binary multiples of 128 bytes will be adopted
by setting a logic 1 in Bit 3 of the Read and Write
commands. Additionally, a variable sector length
feature is provided which allows an indicator recordea
in the 10 Field to control the length of the sector. Variable sector lengths can be read or written in Read or
Write commands, respectively, by setting a logic 0 in
Bit 3 of the command word. The sector length indicator specifies the number of 16 byte groups or 16 x N,
where N is equal to 1 to 256 groups. An indicator of all
zeroes is interpreted as 256 sixteen byte groups.
• For exact times consult WDC.
The Head Load (HLD) output controls the movement
of the read/write head against the disk for data
recording or retrieval. It is activated at the beginning
of a Read, Write (E Flag On) or Verify operation, or a
Seek or Step operation with the head load bit, h, a
logic one remains activated until the third index
pulse following the last operation which uses the
read/write head. Reading or Writing does not occur
until a minimum of 10 msec delay after the HLD signal is made active. If executing the type 2 commands
with the E flag off, there is no 10 msec delay and the
head is assumed to be engaged. The delay is determined by sampling of the Head Load Timing (HL T)
input after 10 msec. A high state input, generated
from the Head Load output transition and delayed
externally, identifies engagement of the head
against the disk_ In the Seek and Step commands,
the head is loaded at the start of the command execution when the h bit is a logic one. In a verify command the head is loaded after stepping to the
destination track on the disk whenever the h bit is a
logic zero.
DISK WRITE OPERATION
After data is loaded from the pr:>cessor into the Data
Register, and is transferred to the Data Shift Register,
data will be shifted serially through the Write Data
(WD) output. Interlaced with each bit of data is a positive clock pulse of 0.5 JJ.sec duration. This signal
may be used to externally toggle a flip-flop to control
the direction of Write Current flow_
When writing is to take place on the diskette the
Write Gate (WG) output is activated, allowing current to flow into the Read/Write head. As a precaution to erroneous writing, the first data byte must be
loaded into the Data Register in response to a Data
Request from the FD1771 before the Write Gate signal can be activated.
DISK READ OPERATION
The 2.0 MHz external clock provided to the device is
internally divided by 4 to form the 500 kHz clock rate
for data transfer. When reading data from a diskette
this divider is synchronized to transitions of the Read
Data (FDDATA) input. When a transition does not
occur on the 500 kHz clock active state, the clock
divider circuit injects a clock to maintain a continuous 500 kHz data clock. The 500 kHz data clock is
further divided by 2 internally to separate the clock
and information bits. The divider is phased to the
information by the detection of the address mark.
Writing is inhibited when the Write Protect input is a
logic low, in which case any Write command is
immediately terminated, an interrupt is generated
and the Write Protect status bit is set. The Write Fault
input, when activated, signifies a writing fault condition detected in disk drive electronics such as failure
to detect write current flow when the Write Gate is
activated. On detection of this fault the FD1771 terminates the current command, and sets the Write
Fault bit (bit 5) in the Status Word. The Write Fault
input should be made inactive when the Write Gate
output becomes inactive.
In the internal data read and separation mode the
Read Data input toggles from one state to the opposite state for each logic one bit of clock or information. This signal can be derived from the amplified,
differentiated, and sliced Read Head signal, or by the
output of a flip-flop toggling on the Read Data
pulses. This input is sampled by the 2 MHz clock to
detect transitions.
Whenever a Read or Write command is received the
FD1771 samples the READY input. If this input is
logic low the command is not executed and an interrupt is generated. The Seek or Step commands are
performed regardless of the state of the READY
input.
The chip can also operate on externally separated
128
COMMAND DESCRIPTION
Table 4. FLAG SUMMARY
The FD1771 will accept and execute eleven commands. Command words should only be loaded in
the Command Register when the Busy status bit is
off (status bit 0). The one exception is the Force
Interrupt command. Whenever a command is being
executed, the Busy status bit is set. When a command is completed, an interrupt is generated and the
Busy status bit is reset. The Status Register indicates
whether the completed command encountered an
error or was fault-free. For ease of discussion, commands are divided into four types. Commands and
types are summarized in Table 2.
8"laO =
a1 ao
a1aO
a1ao
a1 ao
TYPE 1 COMMANDS
The Type 1 Commands include the RESTORE,
SEEK, STEP, STEP-IN, and STEP-OUT commands.
Each of the Type 1 Commands contain a rate field
(rOr1), which determines the stepping motor rate as
defined in Table 1, page 4.
--
=
5 = 0, Synchronize to AM
5 = 1, Do Not Synchronize to AM
TYPE IV
= Interrupt Condition flags (Bits 3-0)
= 1, Not Ready to Ready Transition
= 1, Ready to Not Ready Transition
= 1, Index Pulse
= 1, Immediate interrupt
E = Enable H LD and 10 msec Delay
E = 1, Enable HLD, HLT and 10 msec
Delay
E = 0, Head is assumed Engaged and
Ii
10
11
12
13
BITS
7 654 3 2 1 0
Table 3. FLAG SUMMARY
-
TYPE III
s
Synchronize flag (Bit 0)
Table 2. COMMAND SUMMARY
o 0 0 0 h V r1 ro
o 0 0 1 h V r1 ro
o 0 1 u h V r1 ro
o 1 0 u h V r1 ro
o 1 1 u h V r1 ro
1 0 0 m b E 0 0
1 0 1 m b E a1 ao
1 1 000 E 0 0
1 1 100 1 0 5
11110100
1 1 0 1 13 12 11 14
Note: Bits shown in TRUE form.
Data Address Mark (Bits 1-0)
= 00, FB (Data Mark)
= 01, FA (User defined)
= 10, F9(Userdefined)
= 11, F8 (Deleted Data Mark)
c
.....
.......
.......
.....
6
.....
Table 5. FLAG SUMMARY
The Type 1 Commands contain a head load flag (h)
which determines if the head is to be loaded at the
beginning of the command. If h=1, the head is
loaded at the beginning of the command (HLD
output is made active). If h=O, HLD is deactivated.
TYPE COMMAND
I
Restore
I
Seek
I
Step
I
Step In
I
Step Out
II
Read Command
II
Write Command
III
Read Add ress
Read Track
III
III
Write Track
IV
Force Interrupt
-n
TYPE II
m = Multiple Record flag (Bit 4)
m = 0, Single Record
m = 1, Multiple Records
b = Block length flag (Bit 3)
b = 1, IBM format (128 to 1024 bytes)
b = 0, Non-IBM format
(16 to 4096 bytes)
there is no 10 msec Delay
Once the head is loaded, the head will remain
engaged until the FD1771 receives a command that
specifically disengages the head. If the FD1771
does not receive any commands after two
revolutions of the disk, the head will be automatically disengaged (HLD made inactive). The
. Head Load Timing Input is sampled after a 10 ms
delay, when reading or writing on the disk is to
occur.
TYPE I
The Type 1 Commands also contain a verification
(V) flag which determines if a verification operation
is to take place on the destination track. If V=1, a verification is performed; if V=O, no verification is
performed.
h = Head Load flag (Bit 3)
h
1, Load head at beginning
h
0, Do not load head at beginning
V = Verify flag (Bit 2)
V = 1, Verify on last track
V = 0, No verify
r1 ro = Stepping motor rate (Bits 1-0)
Refer to Table 1 for rate summary
u = Update flag (Bit 4)
u = 1, Update Track register
u = 0, No update
=
=
During verification, the head is loaded and after an
internal 10 ms delay, the HL T input is sampled. When
HL T is active (logic true), the first encountered ID
field is read off the disk. The track address of the ID
Field is then compared to the Track Register; if there
is a match and a valid ID CRC, the verification is
complete, an interrupt is generated and the BUSY
status bit is reset. If there ;s not a match but there is
129
'TI
C
""""
......
......
6""""
""""
valid 10 CRC, an interrupt is generated, the Seek
Error status bit (Status Bit 4) is set and the BUSY status bit is reset. If there is a match but not a valid CRC,
the CRC error status bit is set (Status Bit 3), and the
next encountered 10 Field is read from the disk for the
verification operation. If an 10 Field with a valid CRC
cannotbe found after two revolutions of the disk, the
FD1771 terminates the operation and sents an interrupt (INTRQ).
Register is loaded with zeroes and an interrupt is
generated. If TROO is not active low, stepping pulses
(pins 15 to 17) at a rate specified by the r1 ro field are
issued until the TROO input is activated. At this time
the TR is loaded with zeroes and an interrupt is generated. If the TROO input does not go active low after
255 stepping pulses, the FD1771 terminates operation, interrupts, and sets the Seek error status bit.
Note that the RESTORE command is executed when
MR goes from an active to an inactive state. A verification operation takes place if the V flag is set. The h
bit allows the head to be loaded at the start of
command.
The STEP, STEP-IN, and STEP-OUT commands
contain an UPDATE flag (U). When U=1, the track
register is updated by one for each step. Whe U=O,
the track register is not updated.
S.EEK
RESTORE (SEEK TRACK 0)
Upon receipt of this command the Track 00 (TROO)
input is sampled. If TROO is active low indicating the
Read-Write head is positioned over track 0, the Track
This command assumes that the Track Register contains the track number of the current position of the
Read-Write head and the Data Register contains the
desired track number. The FD1771 will update the
TYPE I COMMAND FLOW
TYPE I COMMAND FLOW
130
Track register and issue stepping pulses in the
appropriate direction until the contents of the Track
register are equal to the contents of the data register
(the desired track location). A verification operation
takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the
command.
interrupt is generated at the completion of the
command.
STEP-IN
Upon receipt of this command, the FD1771 issues
one stepping pulse in the direction towards track
76. If the u flag is on, the Track Register is incremented by one. After a delay determined by the r1 ro
field, a verification takes place if the V flag is on. The
h bit allows the head to be loaded at the start of the
command. An interrupt is generated at the completion of the command.
STEP
Upon receipt of this command, the FD1771 issues
one stepping pulse to the disk drive. The stepping
motor direction is the same as in the previous step
command. After a delay determined by the r1 r ofield,
a verification takes place if the V flag is on. It the u
flag is on, the TR is updated. The h bit allows the
head to be loaded at the start of the command. An
STEP-OUT
Upon receipt of this command, the FD1771 issues
one stepping pulse in the direction towards track 0. If
the u flag is on, the TR is decremented by one. After a
delay determined by the r1 ro field, a verification
takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the
command.
TYPE II COMMANDS
The Type II Commands include the Read Sector(s)
and Write Sector(s) commands. Prior to loading the
Type II command into the COMMAND REGISTER,
the computer must load the Sector Register with the
desired sector number. Upon receipt of the Type II
command, the Busy status bit is set. If the E flag=1
(this is the normal case), HLD is made active and
HL T is sampled after a 10 msec delay. If the E flag is
0, the head is assumed to be engaged and there is no
10 msec delay. The ID field and the Data Field format
are shown below.
When an ID field is located on the disk, the FD1771
compares the track number of the ID field with the
Track Register. If there is not a match, the next
encountered ID field is read and a comparison is
again made. If there was a match, the Sector Number
of the ID field is compared with the Sector Register.
If there is not a Sector match, the next encountered
ID field is read off the disk and comparisons again
made. If the ID field CRC is correct, the data field is
then located and will be either written into, or read
from depending on the command. The FD1771 must
find an ID field with a track number, Sector number,
and CRC within two revolutions of the disk; otherwise, the Record Not Found status bit is set (Status
bit 3) and the command is terminated with an
interrupt
Each of the Type II Commands contain a (b) flag
which in conjunction with the sector length field
contents of the ID determines the length (number of
characters) of the Data field.
NOTE, IF TEST
IF TEST
0 THERE IS NO 10 MS DELAY
I AND elK I MHz THERE IS A 20MS DELAY
For IBM :3740 compatibility, the b flag should equal1.
The numbers of bytes in the data field (sector) is then
128 x 2n where n =: 0,1,2,3.
TYPE I COMMAND FLOW
•
131
."
.........C
.........
....6
IDAM ':: ID Address Mark Data AM
= Data Address
DATA = (FE)16 ClK = (C7)16
Mark - DATA
= (F8.
F9. FA. or FB). elK = ( C7 h6
For b = 1
Sector Length
Field (Hex)
Number of Bytes
in Sector (Decimal)
00
01
02
03
128
256
512
1024
When the b flag equals zero, the sector length field
(n) multiplied by16 determines the number of bytes
in the sector or data field as shown below.
For b = 0
Sector Length
Field (Hex)
Number of Bytes
in Sector (Decimal)
01
02
03
04
16
32
48
64
•
•
•
•
•
•
FF
00
4080
4096
Each of the Type II commands also contain a (m) flag
which determines if the multiple records (sectors)
are to be read or written, depending upon the command. If m=O a single sector is read or written and an
interrupt is generated at the completion of the command. If m=1, multiple records are read or written
with the sector register internally updated so that an
address verification can occur on the next record.
The FD1771 will continue to read or write multiple
records and update the sector register until the sector register exceeds the number of sectors on the
track or until the Force Interrupt command is loaded
into the command register, which terminated the
command and generates an interrupt.
READ COMMAND
NOTE IF TeST
IF iEsT
Upon receipt of the Read command, the head is
loaded, the BUSY status bilset, and when an ID field
is encountered that has the correct track number,
correct sector number, and correct CRC, the data
field is presented to the computer. The Data Address
Mark of the data field must be found within 28 bytes
of the correct field; if not, the Record Not Found status bit is set and the operation is terminated. When
the first character or byte of the data field has been
0 THERE IS NO 10 MS DELA Y
1 AND elK
1 MHI THERE IS A 20MS DELAY
TYPE II COMMAND FLOW
shifted through the DSR, it is transferred to the DR,
and DRO is generated. When the next byte is accumulated in the DSR, it is transferred to the DR and
another DRO is generated. If the computer has not
read the previous contents of the DR before a new
character is transferred that character is lost and the
132
'TI
INTRQ, RESET BUSY
SET RECORD-NOT FOUND
INTRQ, RESET eusy
SET CRC ERROR
TYPE II COMMAND FLOW
TYPE II COMMAND FLOW
Lost Data status bit is set. This sequence continues
until the complete data field has been input to the
computer. If there is a CRC error at the end of the
data field, the CRC error status bit is set, and the
command is terminated (even if it is a mulltiple
record command).
WRITE COMMAND
Upon receipt of the Write command, the head is
loaded (HLD active) and the BUSY status bit is set.
When an 10 field is encountered that has the correct
track number, correct sector number, and correct
CRC, a ORO is generated. The FD1771 counts off 11
bytes from the CRC field and the Write Gate (WG)
output is made active if the ORO is serviced (Le., the
DR has been loaded by the computer). If ORO has
not been serviced, the command is terminated and
the Lost Data status bit is set. If the ORO has been serviced, the WG is made active and six bytes of zeros
are then written on the disk. At this time the Data
Address Mark is then written on the disk as determined by the a1 ao field of the command as shown
on next page-
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is recorded in the Status Register (Bits 5 and 6) as shown
below.
Status
Bit 6,
Status
BitS
0
0
0
1
1
0
1
1
Data AM
(Hex)
FB
FA
F9
F8
The FD1771 then writes the data field and generates
DROs to the computer. If the ORO is not serviced in
133
C
.....
.....
6
.....
~
~
a1
ao
0
0
0
1
1
0
1
1
Data Mark
(Hex)
FB
FA
F9
Fa
TYPE III COMMANDS
Clock Mark
(Hex)
C7
C7
C7
C7
READ Address
Upon receipt of the Read Address command, the
head is loaded and the BUSY Status bit is set. The
next encountered 10 field is then read in from the
disk, and the six data bytes of the 10 field are
assembled and transferred to the DR, and a ORO is
generated for each byte. The six bytes of the 10 field
are shown below.
time for continuous writing the Lost Data status bit is
set and a byte of zeros is written on the disk. The
command is not terminated. After the last data byte
has been written on the disk, the two-byte CRC is
computed internally and written on the disk followed
by one byte gap of logic ones. The WG output is then
deactivated.
TRACK
AD DR
SIDE
NUMBER
1
2
IADDRESS
SECTOR I SECTOR
LENGTH
I
3
I
4
CRC CRC
1
5
2
6
Although the CRC characters are transferred to the
computer, the FD1771 checks for validity and the
CRC error status bit is set if there is a CRC error.
The Sector Address of the 10 field is written into the
Sector Register. At the end of the operation an interrupt is generated and the BUSY Status is reset.
READ TRACK
Upon receipt of the Read Track command, the head
is loaded and the BUSY status bit is set. Reading
starts with the leading edge of the first encountered
index mark and continues until the next index pulse.
As each byte is assembled it is transferred to the
Data Register and the Data Request is generated for
each byte. No CRC checking is performed. Gaps are
included in the input data stream. If bit O(S) of the
command is a 0, the accumulation of bytes is synchronized to each Address Mark encountered. Upon
completion of the command, the interrupt is
activated.
WRITE TRACK
Upon receipt of the Write Track command, the head
is loaded and the BUSY status bit is set. Writing
starts with the leading edge of the first encountered
index pulse and continues until the next index pulse,
at which time the interrupt is activated. The Data
Request is activated immediately upon receiving the
command, but writing will not start until after the first
byte has been loaded into the Data Register. If the
DR has not been loaded by the time the index pulse is
encountered the operation is terminated making the
device Not Busy, the LostData status bit is set, and
the Interrupt is activated. If a byte is not present in
the DR when needed, a byte of zeros is substituted.
Address Marks and CRC characters are written on
the disk by detecting certain data byte patterns in the
outgoing data stream as shown in the table below.
The CRC generator is initialized when any data byte
from Fa to FE is about to be transferred from the DR
to the DSR.
TYPE II COMMAND FLOW
134
"T1
C
.....
......
......
.....
6
.....
WRITE 2 CRG
CHARS eLK FF
WRITE Fe
eLK
07
WRITE FO FE'
Fe - FBCLK C7
wRnE BYTE OF ZEROS
SE.T DATA lOST
TYPE III COMMAND WRITE TRACK
The Write Track Command will not execute if the
DINT input is grounded; instead, the Write Protect
status bit is set and the interrupt is activated. Note
that one F7 pattern generates two CRC characters.
TYPE IV COMMAND
Force Interrupt
This command can be loaded into the command register at any time. If there is a current command under
execution (BUSY status bit set), the command will
be terminated and an interrupt will be generated
when the condition specified in the 10 through 13
field is detected. The interrupt conditions are shown
below:
10= Not-Ready-To-Ready Transition
11 = Ready-To-Not-Ready Transition
12 = Every Index Pulse
13 = Immediate Interrupt (Requires reset,
see Note)
TYPE III COMMAND WRITE TRACK
CONTROL BYTES FOR INITIALIZATION
DATA
PATTERN
(HEX)
F7
F8
F9
FA
FB
FC
FD
FE
INTERPRETATION
Write CRC Character
Data Address Mark
Data Address Mark
Data Address Mark
Data Address Mark
Index Address Mark
Spare
ID Address Mark
CLOCK
MARK
(HEX)
FF
C7
C7
C7
C7
D7
C7
NOTE: If 10 - 13 =0, there is no interrupt generated but the current
command is terminated and busy is reset. This.is the only
command that will clear the immediate interrupt.
135
reset and the rest of the status bits are updated or
cleared. I n this case, Status reflects the Type I
commands.
STATUS DESCRIPTION
"T1
C
...10.
.....
.....
...10.
6...10.
Upon ieceipt of any command, except the Force
Interrupt command, the Busy Status bit is set and
the rest of the status bits are updated or cleared for
the new command. If the Force Interrupt Command
is received when there is a current command under
execution, the Busy status bit is reset, and the rest of
the status bits are unchanged. If the Force Interrupt
command is received when there is not a current
command under execution, the Busy Status bit is
The format of the Status Register is shown below .
(BITS)
I
7 161 5
S7 I S6 I S5
I
4
S4
I
I
3
S3
I
I
2
82
I
I
1
81
I
I
0
80
Status varies according to the type of command
executed as shown in Table 6.
Table 6. STATUS REGISTER SUMMARY
BIT
S7
S6
S5
S4
ALL TYPE I
COMMANDS
NOT READY
WRITE PROTECT
HEAD ENGAGED
SEEK ERROR
ID NOT FOUND
S3
S2
S1
SO
CRC ERROR
TRACKO
INDEX
BUSY
CRC ERROR
LOST DATA
DRO
BUSY
READ ADDRESS
NOT READY
0
0
READ
NOT READY
RECORD TYPE
RECORD TYPE
RECORD NOT
FOUND
CRC ERROR
LOST DATA
DRO
BUSY
READ TRACK
NOT READY
0
0
0
0
LOST DATA
DRO
BUSY
WRITE
NOT READY
WRITE PROTECT
WRITE FAULT
RECORD NOT
FOUND
CRC ERROR
LOST DATA
DRO
BUSY
WRITE TRACK
NOT READY
WRITE PROTECT
WRITE FAULT
0
0
LOST DATA
DRO
BUSY
STATUS FOR TYPE I COMMANDS
NAME
MEANING
This bit when set indicates the drive is not ready. When reset it
indicates that the drive is ready. This bit is an inverted copy of
the READY input and logically "ored" with MR.
BIT
S7
NOT READY
86
PROTECTED
When set, indicates Write Protect is activated. This bit is an
inverted copy of WRPT input.
85
HEAD LOADED
84
8EEK ERROR
83
CRC ERROR
S2
TRACK 00
81
INDEX
SO
BU8Y
When set, it indicates the head is loaded and engaged. This bit
is a logical "and" of HLD and HLT signals.
When set, the desired track was not verified. This bit is reset to
o when updated.
When set, there was one or more CRC errors encountered on
an unsuccessful track verification operation. This bit is reset
to 0 when updated.
When set, indicates Read-Write head is positioned to Track O.
This bit is an inverted copy of the TROO input.
When set, indicates index mark detected from drive. This bit is
an inverted copy of the IP input.
When set, command is in progress. When reset, no command
is in progress.
136
STATUS BITS FOR TYPE" AND III COMMANDS
BIT
S7
NAME
NOT READY
MEANING
This bit when set indicates the drive is not ready. When reset, it
indicates that the drive is ready. This bit is an inverted copy of
the READY input and "ored" with MR. The TYPE II and III
Commands will not execute unless the drive is ready.
S6
RECORD TYPE/
WRITE PROTECT
On Read Record: It indicates the MSB of record-type code from
data field address mark. On Read Track: Not Used. On any
Write Track: It indicates a Write Protect. This bit is reset when
updated.
S5
RECORD TYPE/WRITE FAULT
S4
RECORD NOT FOUND
On Read Record: It indicates the LSB of record-type code from
data field address mark. On Read Track: Not Used. On any
Write Track: It indicates a Write Fault. This bit is reset when
updated.
When set, it indicates that the desired track and sector were
not found. This bit is reset when updated.
S3
CRC ERROR
S2
LOST DATA
S1
DATA REQUEST
This bit is a copy of the DRQ output. When set, it indicates the
DR is full on a Ready operation or the DR is empty on a Write
operation. This bit is reset to zero when updated.
SO
BUSY
When set, command is under execution. When reset, no
command is under execution.
If S4 is set, an error is found in one or more ID fields; otherwise
it indicates error in data field. This bit is reset when updated.
When set, it indicates the computer did not respond to DRQ in
one byte time. This bit is reset to zero when updated.
instance, an FE pattern will be interpreted as an ID
address mark (DATA-FE, CLK-C7) and the CRC will
be initialized. An F7 pattern will generate two CRC
characters. As a consequence, the patterns F7
through FE must not appear in the gaps, data fields,
or I D fields. Also, CRCs must be generated by an F7
pattern.
FORMATTING THE DISK (Refer to section on Type
ItI Commands for flow diagrams.)
Formatting the disk is a relatively simple task when
operating programmed I/O or when operating under
DMA control with a large amount of memory. When
operating under DMA with limited amount of
memory, formatting is a more difficult task. This is
because gaps as well as data must be provided at the
computer interface.
Disks may be formatted in IBM 3740 formats with sector lengths of 128,256,512, or 1024 bytes, or may be
formatted in non-I BM format with sector lengths of 16
to 4096 bytes in 16-byte increments. IBM 3740 at the
present time only defines two formats. One format
with 128 bytes/sector and the other with 256 bytes/sector. The next section deals with the IBM 3740 format with 128 bytes/sector followed by a section of
non-IBM formats.
Formatting the disk is accomplished by positioning
the R/W head over the desired track number and
issuing the Write Track command. Upon receipt of
the Write Track command, the FD1771 raises the
Data Request signal. At this point in time, the user
loads the Data Register with desired data to be written on the disk. For every byte of information to be
written on the disk, a Data Request is generated. This
sequence continues from one index mark to the next
index mark. Normally, whatever data pattern
appears in the Data Register is written on the disk
with a clock mark of (FF)16' However, if the FD1771
detects a data pattern on F7 through FE in the Data
Register, this is interpreted as data address marks
with missing clocks or CRC generation. For
IBM 3740 Formats - 128 Bytes/Sector
The IBM format with 128 bytes/sector is depicted in
the Track Format figure on the following page. In
order to create this format, the user must issue the
Write Track command, and load the data register with
the following values. For every byte to be written,
there is one data request.
137
"--.......
C
--..
.....
6
.....
Number
of Bytes
."
C
..........
......
....
6....
*
40
6
1
26
6
1
1
1
1
1
1
11
6
1
·128
1
27
247 **
Non-IBM Formats
Hex Value of
Byte Written
Non-IBM formats are very similar to the IBM formats
except a different algorithm is used to ascertain the
sector length from the sector length byte in the 10
field. This permits a wide range of sector lengths
from 16 to 4096 bytes. Refer to Section V, Type II
commands with b flag equal to zero. Note that F7
through FE must not appear in the sector length byte
of the 10 field.
00 or FF
00
FC (Index Mark)
00 or FF
00
FE (10 Address Mark)
Track Number (0 through 4C)
00
Sector Number (1 through 1A)
00
F7 (two CRCs written)
00 or FF
00
FB (Data Address Mark)
Data (IBM uses ES)
F7 (two CRCs written)
00 or FF
00 or FF
In formatting the FD1771 , only two requirements
regarding GAP sizes must be met. GAP 2 (Le., the
gap between the 10 field and data field) must be 17
bytes of which the last 6 bytes must be zero and that
every address mark be preceded by at least one byte
of zeros. However, it is recommended that every
GAP be at least 17 bytes long with 6 bytes of zeros.
The FD1771 does not require the index address mark
(Le., DATA =FC, ClK =07) and need not be present.
References:
1) I BM Diskette OEM Information GA21-9190-1.
2) SA900 IBM Compatibility Reference Manual Shugart Associates.
*Write bracketed field 26 times.
**Continue writing until FD1771 interrupts out.
Approximately 247 bytes.
INDEX ADDRESS MARK
128 BYTES OF USER
DATA
GAP 3
00 OR FF
FF
1 BYTE
L
32 BYTES
-----l
' - WAITE GATE rURN·OFF FOA UPOATE
OF PREVIOUS DATA FIELD
TRACK FORMAT
138
ELECTRICAL CHARACTERISTICS
OPERATING CHARACTERISTICS (DC)
Maxium Ratings
VOO with respect to VBB (Ground)
+20 to -03V
Max Voltage to any input with
+20 to -03V
respect to VBB
Operating Temperature
0° C to 70° C
Storage Temperature
-55° C to +125° C
TA::: O°C to 70°C. VOO::: +12.0V ± .6V.
VBB ~ -·5.0 ±5V. VSS = OV. VCC = +5V ± .25V
I DO = 10 ma Nominal. ICC = 30 ma Nominal.
I BB .., 0.4 !J. a Nominal
Symbol
Characteristic
'TI
Min.
Typ.
Max.
Units
Conditions
III
Input Leakage
10
p.A
ILO
Output Leakage
10
p.A
= VOo
VOUT = Voo
VIH
Input High Voltage
VIL
Input Low Voltage (All Inputs)
VOH
Output High Voltage
VOL
Output Low Voltage
2.6
V
0.8
2.8
0.45
TIMING CHARACTERISTICS
VIN
V
V
10
V
10
= -100 uA
=1.0 mA
NOTE Timings are given for 2 MHz Clock. For those
timings noted. values will double when chip is operated at 1 MHz. Use 1 MHz when using mini-floppy.
TA ::: O°C to 70°C. VOO : : +12V ± .6V.
V BB ::: -5V ± .25V. VSS ::: OV. VCC = +5V + .25V
Read Operations
Symbol
Characteristic
Min.
TSET
Setup AooR and CS to RE
THLo
Hold AOoR and CS from
TRE
TORR
RE
RE Pulse Width
Typ.
Max.
Units
100
nsec
10
nsec
450
nsec
ORO Reset from RE
750
nsec
Conditions
CL
= 25
pf
=25
=25
pf
TIRR
INTRa Reset from RE
3000
nsec
ToACC
Data Access from RE
450
nsec
CL
150
nsec
CL
Max.
Units
Conditions
ToOH
Data Hold from RE
50
pf
Write Operations
Symbol
TSET
THLo
TWE
TORR
Characteristic
Min.
Setup AooR and CS to
WE
Hold AooR and CS from WE
WE
Pulse Width
ORO Reset from
Typ.
100
nsec
10
450
nsec
nsec
300
M
750
nsec
TIRR
INTRa Reset from ~
TDS
Data Setup to WE
350
nsec
TDH
Data Hold from WE
150
nsec
3000
nsec
See Note
External Data Separation (XTDS = 0)
Symbol
Characteristic
TPWX
Pulse Width Read Data & Read Clock
TCX
Clock Cycle External
TDEX
Data to Clock
ToDX
Data to Data Cycle
Min.
150
Typ.
Max.
Units
350
nsec
2500
nsec
500
nsec
2500
nsec
•
139
Conditions
C
.....
~
.....
6
.....
~32·uS
"c...........
"
~--~""'3'US---I·1
-,.....; 1-_+-...,'--TORR
ORQVOl ~
\
L -_ _ _ _ _ _ _ _ _ _ _ _- - '
I
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......
.....
THLDI ~
6.....
1
..._ _ _ _ __
AO AI CS'
~±t~3
~i3fo.E;lt':~~TEDI
t.c) --J ~------T DOH
NOTE
1 B MAY BE PERMANENTLY TIED lOW IF DESIREO
2 FOR REAO TRACK COMMAND. THIS TIME MAY BE 12' TO 32' uSEe WHEN 5
3.
0
'''!'\lice WORST CASE26USEC
3. 'aervice WORST CASE 24 ",SEC
• TIME OOUBLES WHEN eLK = 1 MHZ
•
TIME DOUBLES WHEN elK
READ ENABLE TIMING
I MHZ
WRITE ENABLE TIMING
;~~;R~~L
OAT A
SEPARATION
r-
TPWX
MISSING
CLOCK
I
NOTE
1 ABOVE TIMES ARE DOUBLED WHEN elK 1 MHZ
2 CONTACT woe FOR EXTERNAL CLOCK/DATA SEPARATOR CIRCUITS
3 FDClKANDFDOATAMAYBEREVERSEO FOI77! DECIDES WHAT IS CLOCK AND WHAT IS DATA
READ TIMING (XTDS = 0)
Internal Data Separation (XTDS = 1)
Symbol
TPWI
TCI
Characteristic
Pulse Width Data and Clock
Clock Cycle Internal
Min.
Typ.
Max.
Units
150
1000
nsec
3500
5000
nsec
Max.
Units
Conditions
Write Data Timing
Symbol
TWGD
Characteristic
Min.
Write Gate to Data
TPWW
Pulse Width Write Data
TCDW
TCW
TWGH
Clock to Data
Clock Cycle Write
Write Gate Hold to Data
Typ.
500
600
nsec
2000
nsec
4000
nsec
0
Conditions
nsec 300 nsec ± ClK tolerance
1200
± ClK tolerance
± ClK tolerance
100
nsec
Max.
Units
Conditions
nsec
2MHz ± 1% See Note
Miscellaneous Timing
Symbol
Characteristic
TCD1
Clock Duty
TCD2
TSTP
Clock Duty
Step Pulse Output
TDIR
Direct Setup to Step
Master Reset Pulse Width
TMR
TIP
TWF
Min.
Typ.
175
210
3800
24
10
4200
nsec
nsec
nsec
Index Pulse Width
10
nsec } These limes doubled
when ClK = 1 MHz
nsec
Write Fault Pulse Width
10
nsec
140
l
I--
T 'P
--1
l
XTDS 1
INTERNAL DATA
SEPARATION FDCLOCK
MUST BE TIED HIGH
I-- TWF---l
I----
f---Tcl~-t---1_.
' 'us
"~
_~
[
--1
eve
1 MH
----l
I--
~
LEADING EOGEO'
DATA PULSE
MUST OCCUR IN
SHADED AREA
~
TCD'--/
--l
~
'""'
1
f--l CD,
NOTE
INTERNAL DATA SEPARATION MAY WORK FOR SOME APPLICATIONS HOWEVE'R
FOR APPLICATIONS REOUIRING HIGH DATA AECOVERY RELIABILITY
woe RECOMMENDS EXTERNAL DATA SEPARATION 8E useD
READ TIMING (XTDS
WG
= 1)
MISCELLANEOUS TIMING
«~
--l
~TWGo--1
T
pww--j
~
T
~
T PWW
f--
-1JcL
f--
cow--L cw _
------+---~-T ---jI
cw--
C
r-,
(t---JJ' L 0
LAST DATA BIT
TO BE WRITTEN
WRITE DATA TIMING
See page 725 for ordering information.
•
141
f--T WGH
f--
--j
Viti
VIH
"T1
C
.....
.....
.....
.....
6
.....
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
"142
Prrnted in U.S.A
WESTERN DIGITAL
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1771·01 Application Notes
•
INTRODUCTION
define the type of data i.e., "object" or "text" data,
alternate sector data, or any other purpose the user
chooses.
The FD1771··01 Floppy Disk Formatter/Controller is
a MaS/LSI device designed to ease the task of interfacing the 8" or 5'/4 (mini-floppy) disk drive to a host
processor. It is ideally suited for a wide range of
microprocessors, providing an 8-bit bi-directional
interface to the CPU for all control and data
transfers. Requiring standard + 12, ±5V power supplies, the 1771 is available in ceramic or plastic40 pin
dual-in-line packages.
PROCESSOR INTERFACE
The 1771 contains five internal registers that can be
accessed via the 8-bit DAL lines by the CPU. These
registers are used to control the movement of the
head, read and write sectors, and perform aLI. other
functions at the drive. Regardless of the op~ration
performed, it must be initiated through one or more
of these registers. They are selected by a proper
binary code on the AO, A1 lines in conjunction with
the RE and WE lines when the device is selected.
The registers and their addresses are:
The 1771 has been designed to be compatible with the
IBM 3740 standard. This single-dens)ty Frequency
Modulated (FM) recording technique, records a
clock bit between a data bit serially on each track.
Figure 1 illustrates how a HEx' "D2" is recorded.
Note that when the data bit to be written is zero, no
pulse or flux transition is recorded. For the 8" drive,
there are 77 tracks, with 26 sectors on each track.
Each sector contains 128 bytes of data. Although
there is no "standard" format for the mini-floppy,
most manufacturers utilize either 35 or 40 tracks per
side, wtih 16 sectors of 128 bytes each per track.
Both the 8" and 5W' formats must be soft-sectored,
i.e., there are no physical holes to denote sector
locations. The hard-sectored disk has been losing
popularity, mainly due to the fact that the sector
lengths cannot be increased.
Description
Data
Index Address Mark
ID Address Mark
Data Addmss Mark
User defined
User Defined
Deleted Address Mark
FC
FE
FB
FA
F9
F8
D7
C7
C7
C7
C7
C7
Al
Ao
RE = 0
WE=O
0
0
0
0
1
0
0
1
1
0
1
0
1
X
X
STATUS REG
TRACK REG
SECTOR REG
DATA REG
Deselected
COMMAND REG
TRACK REG
SECTOR REG
DATA REG
Deselected
Command Register: This is a write-only register
used to send all commands to the 1771.
Status Register: This is a read-only register that
must be read at the completion of every command to
determine whether execution was successful. It
may also be used to monitor command execution,
and to sense when data is required by the drive for
read or write operations.
Being soft-sector compatible, the 1771 must know
where each sector begins on the track. This is performed by using Address Marks. These bytes are
recorded on the disk with certain clock pulses missing, and are unique from all other data and gap bytes
recorded on the track. Six distinct Address Marks
can be used:
Clock
Pattern
CS
Track Register: This R/W register holds the current
position of the R/W head.
Sector Register: This R/W register holds the desired
sector number for read and write commands.
Data Register: This R/W register contains the data
to be read or written to a particular sector.
INTERRUPTS
There are two INTERRUPT lines for CPU use. These
are the DRO (Data Request) and INTRa (Interrupt
Request). These are active high, open drain outputs
and require a pull-up resistor of 10K or greater to
+5V. Both of these signals also appear in the status
register as the Busy (INTRa) and the data request
(DRO) bits. The user has the option of utilizing these
hardware lines for system interrupts, or through
The two "User Defined" Address Marks are unique
to the 1771, and do not appear in the IBM 3740
standard. These Address Marks can be used to
143
......
......
......
......
6......
software by polling the status register. The choice is
dependent upon the particular microprocessor and
support hardware of the system .
contain an "m" flag for accessing multiple sectors.
The sector register is incremented internally after
each sector is read or written to. Eventually the sector register will exceed the physical number of sectors on the track. The user can either issue the
Forced Interrupt command after the last sector, or
wait for the 1771 to interrupt out. In the latter case,
the RECORD-NOT -FOUND status bit will be set.
INTRa: This line is used to signify the completion of
any command. It is reset low when a new command
is loaded into the command register, or when the
status register is read.
ORa: This line is active high whenever the data reg-
FLOPPY DISK INTERFACE
ister requires servicing. During a read command, it
signifies that the data register contains a byte of
data from the disk and may be read by the CPU. During a write command, it signifies that the data register is empty and may be loaded with the next byte to
be written on the disk. The ORO line is reset whenever the data register is read or written to. It is also
reset when a new command is loaded into the command register, providing the new command is not a
Forced Interrupt, and the 1771 is not busy (Busy Bit = 0).
For the most part, the actual Floppy Disk Interface
will consist mainly of Buffer/Drivers. Most drives
manufactured today require an open collector TTL
interface, with appropriate resistor terminal networks. Figure 2 shows the interface of the 1771 to a
. Shugart SA400 Drive. Aside from the data seperator,
the interface consists mainlyof7438'sand7414 TTL
gates. A 9602 one-shot is used for the desired head
load delay. In this illustration, the 6800 microprocessor is used via a 6820 Peripheral Interface Adapter to control all functions of the 1771. Similarly,
other parallel port devices (such as the 8255 for 8080
systems) can be used for the interface, or the 1771
may simply be tied directly to the systems data bus
and control lines, providing TTL loading factors are
observed.
WRITE SECTOR
With the use of the WRITE SECTOR command, the
CPU can access any desired sector(s) in a track.
Prior to loading this command, the R/W head of the
drive must be positioned over the specific track.
This can be first accomplished with the use of any of
the Type I commands. Once positioned, the CPU
must load the desired sector number into the sector
register, then issue the command. The head will
load, and the 1771 will begin searching for the correct 10 field. If the correct sector and track is not
found within 2 revolutions of the disk, the RECORDNOT -FOUND bit will be set in the status register,
and the command will be terminated. Once found,
the 1771 will issue a ORO in request of the first data
byte to be written. Once the data register is loaded,
the 1771 will issue a ORO for each byte to be
recorded, until the entire sector is written. For the 8"
drive, the user must load the data register 24
microseconds after a DRQ is generated. Failure to
meet this time will cause the lost data bit to be set,
and a byte of zeros substituted and written on the
disk.
DATA SEPERATION
The internal OAT A SEPERATOR of the 1771 can be
used by tying the XTDS line high, and supplying the
combined clock and data pulses on the FD data line.
In order to maintain an error rate better than 1 in 10 8 ,
and external data seperator is recommended.
Since the 1771 system clock is at 2 MHz, this allows
for a 500 ns resolution. The internal data window will
move 500 ns with respect to the incoming data bit.
On the inner tracks of the drive, the bit shift is more
severe and may occasionally cause a data or clock
bit to fall outside of this data window. Since the 1771
will perform up to 5 retries, this error rate may be
acceptable for some applications.
When the XTDS line is forced low, the 1771 will
accept seperated clock and data on the FDCLOCK
and FDDATA lines. Figure 3 illustrates the timing of
these signals. The actual FDCLOCK and FDDATA
lines may be reversed; the 1771 will determine which
line is clock and which is data when an Address
Mark is detected. This feature greatly simplifies the
design of the data seperator.
Figure 4 illustrates the Phase-Lock Loop method for
data seperation. The circuit operates at8 MHz, or32
times the frequency of a received bit cell. The
MC4024 VCO is used to supply the nominal clock
frequency. The first 74LS161 counter provides a
divide by 16 frequency and a carry to one side of the
MC4044 phase detector. The other input of the
MC4044 is tied to another 74LS161 counter which is
affected by the incoming data stream. The output of
READ SECTOR
The READ SECTOR command functions in much
the same way as the WRITE SECTOR command.
The sector register must again be loaded with the
desired sector number, before the read command
can be loaded. After the 10 field has been found, the
1771 will begin generating ORO's, with the data register being loaded with each byte of the sector field.
For the 8" drive, the user must read the data register
at least 26 microseconds after the ORO is
generated. Failure to meet this time will cause the
lost data bit to be set in the status register, while the
next assembled byte will overwrite the contents of
the data register.
Both the Read and Write sector commands also
144
the phase detector is a signal proportional to the differences of the incoming pulses. This is then fed
through a low pass filter, and to the input of the
MC4024 to adjust the output frequency. Figures 5
thru 8 illustrate other types of data seperators.
BIT 1
BIT 2
These employ the "Counter Seperator" techniques
and are quite different from the Phase-Lock:"Loop
method. With the addition of "One-Shot" delay element or an input clock, most of the complexity of the
PPL circuit can be eliminated.
BIT 3
BIT 5
BIT 4
BIT 7
BIT 6
HEX
'02'
FIGURE 1. FM RECORDING.
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FIGURE 2. 1771 TO SHUGART SA400 DRIVE
•
145
......
.......
.......
......
6......
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EXTERNAL DATA
SEPARATION
f-
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TpWX
~~~:-
__T_P_W_X____________
~_~ ~ ~I~_G
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TP_W_X_______
__________
FDClOCK
+-________....J
FDDATA ______________....l..._______
T PWX
TCX
~
=
150 NS MIN
3000 NS MAX
NOTE
1 ABOVE TIMES ARE DOUBLED WHEN ClK = 1 MHZ
3500,5000 NS
FIGURE 3. EXTERNAL DATA SEPERATOR TIMING.
RAW
DATA
SOFT5
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N/C
Cl
0
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Z
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FIGURE 4. CIRCUIT PROVIDED COURTESY OF MOTOROLA AND ICOM CORPS.
146
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.......
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10
11
UNSEPERATED DATA
6
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41'S
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7
12
C 6
13
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2
14
A 3
15
-=
CD
4MHz CLK
RESYNC
FIGURE 5. CIRCUIT PROVIDED COURTESY OF PROCESSOR APPLICATIONS LTD.
10
0
UNSEPARATED
DATA FROM
DRIVE
0
Q
7474
74175
>
9>
Q
TOGGLE
LOAD PULSE
7404
11
QD~--~
4MHZCLK
(USE 2MHZ CLK FOR MINI-DRIVES)
FIGURE 6 .
.
147
------------------4
__
.....
.....
.....
.....
6.....
+5
RAW
DATA
lO!-,SEC
~----------------------------4----'SEPClK
b----4-----------------------------~--~SEPDATA
+5V
L...S
C
*
*
*
C
C
RAWDATA~~_
SEPDATA
~LJUUL
SEP ClK
H6-6
H6-9
FIGURE 7. CIRCUIT PROVIDED COURTESY OF ACUTEST CORP.
148
r-----~------_.------------------_;--_r--------_.~--~~v_~~+5V
D
+
e
D
e
D
e
- SEP elK
- SEP DATA
D
D
D
D
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~--~~----I~--~~.~
READ DATA
---u
lJ
U
U
u
U
U
u
U
SS1 (0)
SS2 (0)
SS3 (15)
A2-6 (Q,)
FIGURE 8. CIRCUIT PROVIDED COURTESY OF SHUGART ASSOCIATES.
149
.....
.......
.......
.....
6.....
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
150
Printed In U.S.A
WESTERN DIGITAL
c
o
R
o
p
R
A
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o
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C
.....
FD1781/FD1781·01 Floppy Disk Formatter/Controlier
.....
CO
FEATURES
APPLICATIONS
~~
FLOPPY DISK DRIVE INTERFACE
SINGLE OR MULTIPLE DRIVE CONTROLLER!
FORMATTER
NEW MINI-FLOPPY CONTROLLER
~~
~~
I~
It
SOFT SECTOR FORMAT COMPATIBILITY
AUTOMATIC TRACK SEEK WITH
VERIFICATION
ACCOMMODATES SINGLE AND DOUBLE
DENSITY FORMATS
READ MODE
Single/Multiple Record Read with Automatic
Sector Search or Entire Track Read
Selectable 128 Byte or Variable Length Record
WRITE MODE
Single/Multiple Record Write with Automatic
Sector Search
Entire Track Write for Diskette Initialization
GENERAL DESCRIPTION
The FD1781 is a MOS/LSI device that performs the
functions of a Floppy Disk Controller/Formatter. The
device is designed to be included in the disk drive
electronics, and contains a flexible interface organization that accommodates the interface signals from
most drive manufacturers. When in the single density
mode the FD1781 is fully IBM-3740 compatible. In the
double density mode, the type of encoding scheme
is a function of the user's data recovery circuits. In
this manner both M2FM or MFM is obtainable.
" PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Selectable Head Settling and Head Engage Times
In Double Density Mode, the FD1781 allows 17 bytes
for CAP2, while the FD1781-01 allows 34 bytes for
this field. All other gap lengths can be fully defined
by the user.
The FD1781 is fabricated in N-channel Silicon Gate
MOS technology and is TTL compatible on all inputs
and outputs.
" SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional Bus
for Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TTL Compatible
On-chip Track and Sector Registers Comprehensive Status Information
-A
C
0
NC
WE
cs
RE
AO
--.fu
DAlO
DAl1
[)A[2
~
DAl4
DAl5
bA[6
DAL7
STEP
DIRe
OTSTR
AMOT
MR
(GND)VSS
VDD(+ 12V)
INTRQ
DRQ
DDEN
WPRT
fP
TROO
WF
READY
OTDATA
WG
TG43
HlD
INDATA
INSTR
AMIN
ClK
HlT
TEST
VCC(+5V)
, DATA (8)
M
P
U
T
E
R
I
N
T
E
R
F
A
C
E
.....
:;;
C
.....
~
.....
6.....
..
r----
AO
A1
cs
RE
WE
MR
FLOPPY DISK
CONTROllERI
FORMATTER
~n
FD1781
ClK
0
I
S
K
0
1
Vcc ~-
R
I
V
E
'-----
HlD
.~
VSS
VDD
ONE SHOT
(IF USED)
1 I I
':"
+ 12
+5
PIN CONNECTIONS
Figure 1.
151
P
P
Y
WG
READY
TG43
STEP
DIRC
'----
-------
F
l
0
WPRT
man
>
INTRa
1
AM
DETECTI
GEN
Wf!
Jl5'
: ~OK
10K
ORa
ENCODE!
DECODE
OTDATA
INDATA
INSTR
AMIN
OTSTR
AMOT
1781 SYSTEM BLOCK DIAGRAM
PIN OUTS
'TI
C
.....
......
-.....
00
.....
'TI
C
PIN
NUMBER
20
21
40
19
PIN NAME
POWER SUPPLIES
SYMBOL
Vss
VCC
VDD
MASTER RESET
MR
......
00
.....
6.....
~-----'--.--------------
COMPUTER INT==E7::R::=:-F:....:AC.::;,:E::;:=:;:-;-;-;~
7-14
DATA ACCESS LINES
3
5,6
--_. __.__ ... _---.. _--
DALO-DAL7
CHIP SELECT
REGISTER SELECT
LINES
AO,A1
4
READ ENABLE
2
WRITE ENABLE
38
DATA REQUEST
39
INTERRUPT REQUEST INTRQ
24
CLOCK
FLOPPY DISK INTERFACE:
25
ADDRESS MARK
DETECT IN
DRQ
CLK
FUNCTION
Ground
+5V
+12V
A logic low on this input resets the device and
clears the command register. The Not Ready
@!.atus Bit 7) is reset during MR ACTIVE. When
MR is brought to a logic high a Restore Command is executed, regardless of the state of the
Ready signal from the drive. --.- - - - - - - - - - - - -
-----=----"~--------
Eight bit inverted Bidirectional bus used for
transfer of data, control, and status. This bus is
a receiver enabled by WE or a transmitter
enabled by RE.
A logic low on this input selects the chip and
enables computer communication with the
device.
These inputs select the register to receivel
transfer data on the DAL lines under RE and WE
control:
A1
AO
RE
WE
o
0 Status Reg
Command Reg
o
1 Track Reg
Track Reg
1
0 Sector Reg
Sector Reg
1
1 Data Reg
Data Reg
A logic low on this input controls the placement
of data from a selected register on the DAL
when CS is low.
A logic low on this input gates data on the DAL
into the selected register when CS is low.
This open drain output indicates that the DR
contains assembled data in Read operations, or
the DR is empty in Write operations. This signal
is reset when serviced by the computer through
reading or loading the DR in Read or Write
operation, respectively. Use 10K pull-up resistor
to +5.
This open drain output is set at the completion
or termination of any operation and is reset
when a new command is loaded into the command register. Use 10K pull-up resistor to + 5.
This input requires a free-running square wave
clock for internal timing reference.
Indicates to the FD1781 that an address mark
has been detected. The FD1781 assumes the
next three data bits defines the type of address
mark encountered.
Indicates that INDATA is VALID.
26
INPUT STROBE
INSTR
The external data recovery circuits present
INDATA
27
INPUT DATA
INDATA as an input to the FD1781. INDATA
must be valid when INSTR is active, see timing.
The FD1781 presents output data and is valid
31
OUTPUT DATA
OTDATA
when OTSTR is active.
28
HEAD LOAD
HLD
The HLD output controls the loading of the
_ _ _ _ _ .______ ._____._____-+-_ _ _ _ ---I-_R_e-'-ac....:d_-W_ri.......:te_h_-'-ea_d_a""-ga_i_nst the media. The HLT
AMIN
152
PIN
NUMBER
23
PIN NAME
HEAD LOAD TIMING
SYMBOL
input is sampled every 15 nsec. When a logic
high is found on the HLT input the head is
assumed to be engaged.
Step and direction motor control. The step output contains a 2/Asec high signal for each step
and the direction output is active high when
stepping in, active low when stepping out.
OTSTR when active indicates when the Output
data is valid. The leading edge of OTSTR is
centered about the data. (See timing) OTSTR
becomes Write Data (WD) when DDEN = 1.
AMOT when active informs the external data
recovery circuits to write a unique data mark in
double density mode. AMOT is valid for three
data bits if CLK mark = C7.
This output informs the drive that the ReadWrite head is positioned betwee"n track 44-76.
This output is valid only during Read and Write
Commands.
This output is made valid when writing is to be
performed on the diskette.
This input indicates disk readiness and is
sampled for a logic high before Read or Write
commands are performed. If Ready is low the
Read or Write operation is not performed and an
interrupt is generated. A Seek operation is
performed regardless of the state of Ready. The
Ready input appears in inverted format as
Status Register bit 7.
This input detects writing faults indications
from the drive. When WG = 1 and Wt: goes low
the current Write command is terminated and
the Write Fault status bit is set. The WF input
should be made inactive (high) when WG
becomes inactive.
This input informs the FD1781 that the ReadWrite head is positioned over Track 00 when a
logic low.
Input, when low for a minimum of 10 /Asec,
informs the FD1781 when an index mark is
encountered on the diskette.
This input is sampled whenever a Write·
Command is received. A logic low terminated
the command and sets the Write Protect Status
bit.
This pin selects either single or double density
operation. When [)[)EN = 0, double density is
selected. When DDEN = 1, single density is
selected.
This input is used for testing purposes only and
should be tied to + 5V or left open by the user.
HLT
15
STEP
STEP
16
17
DIRECTION
OUTPUT STROBE
DIRC
OTSTR
18
ADDRESS MARK OUT
AMOT
29
TRACK GREATER
THAN 43
TG43
30
WRITE GATE
WG
32
READY
READY
33
WRITE FAULT
34
TRACK 00
35
INDEX PULSE
36
WRITE PROTECT
37
DOUBLE DENSITY
FUNCTION
22
153
'T1
C
.....
......
-..........
Q)
'T1
C
......
.....
Q)
6
.....
ORGANIZATION
-n
c
.....
......
Q)
.....
:;;
c
.....
......
Q)
.....
6.....
The CRC includes all information starting with the
address mark and up to the CRC characters. The
CRC register is preset to ones prior to data being
shifted through the circuit.
The Floppy Disk Formatter block diagram is illustrated above. The primary sections include the
parallel processor interface and the Floppy Disk
mterface.
Arithmetic/Logic Unit (ALU) - The ALU is a serial
comparator, incrementer, and decrementer and is
used for register modification and comparisons with
the disk recorded ID field .
Data Shift Register - This 8-bit register assembles
serial data from the Read Data input (INDATA) during
Read operations and transfers serial data to the Write
Data output during Write operations.
Timing and Control - All computer and Floppy Disk
Interface controls are generated through this logic.
The internal device timing is generated from an
external crystal clock.
Data Register - This 8-bit register is used as a
holding register during Disk Read and Write
operations. In Disk Read operations the assembled
data byte is transferred in parallel to the Data
Register from the Data Shift Register. In Disk Write
operations information is transferred in parallel from
the Data Register to the Data Shift Register.
The FD1781 has two different modes of o~eration
according to the state of DDEN. When DD N = 0
double density is assumed. When DDEN = 1, Single
density is assu~ed. During disk read operations, the
user must provide both data recovery and address
mark detection circuits external to FD1781 in both
Single and double density modes. Thus for disk read
operations, the user must provide as an input to the
FD1781 Data (INDATA) a strobe to indicate when the
data is valid (INSTR) and address mark detect (AMIN).
During disk write operations and in the double
density mode, the FD1781 provides as outputs Data
(OTDATA), a strobe to indicate validity (OTSTR) and
Address Mark Out (AMOT). During disk write operation and in the single density mode, OTSTR becomes
Write Data (WD) which is exactly the same as in the
FD1771.
When executing the Seek command the Data
Register holds the address of the desired Track
position. This register can be loaded from the DAL
and gated onto the DAL under processor control.
Track Register - This 8-bit register holds the track
~umber of the current Read/Write head position. It is
Incremented by one every time the head is stepped in
(towards track 76) and decremented by one when the
head is stepped out (towards track (0). The contents
of the register are compared with the recorded track
number in the ID field during disk Read Write and
Verify operations. The Track Register ca~ be lo~ded
from or transferred to the DAL. This Register should
not be loaded when this device is busy.
PROCESSOR INTERFACE
Sector Register (SR) - This 8-bit register holds the
address of the desired sector position. The contents
of the register are compared with the recorded sector
number in the ID field during disk Read or Write
operations. The Sector Register contents can be
loaded from or transferred to the DAL. This register
should not be loaded when the device is busy.
The interface to the processor is accomplished
through the eight Data Access Lines (DAL) and
associated control signals. The DAL are used to
transfer Data, Status, and Control words out of or
into the FD1781. The DAL are three state buffers that
are enabled as outQ!!t drivers when Chip Select (CS)
and Read Enable (RE) are active (low logic state) or
act as input receivers when CS and Write Enable
(WE) are active.
Command Register (CR) - This 8-bit register holds
the command presently being executed. This register
should not be loaded when the device is busy unless
the execution of the current command is to be
overridden. This latter action results in an interrupt.
The command register can be loaded from the DAL,
but not read onto the DAL.
When transfer of data with the Floppy Disk Controller
is required by the host processor, the device address
is decoded and CS is made low. The least-significant
addres~ bits A 1 and AO, ~ombined with the signals
RE dUring a Read operation or WE during a Write
operation are interpreted as selecting the following
registers:
Status Register (STR) - This 8-bit register holds
device Status information. The meaning of the Status
bits are a function of the contents of the Command
Register. This register can be read onto the DAL, but
not loaded from the DAL.
A1·AO
0
0
1
1
0
1
1
°
CRC Logic - This logic is used to check or to
generate the 16-bit Cyclic Redundancy Check (CRG).
The polynomial is: G(x) = X16 + X12 + x5 + 1.
154
READ(RE)
Status Register
Track Register
Sector Register
Data Register
WRITE (WE)
Command Register
Track Register
Sector Register
Data Register
"T1
..........
....
:;;
C
..........
....
6....
C
()C)
v(DAL)
/
()C)
DATA OUT
BUFFERS
,
+
I
COMMAND
REG
DATA
REG
+
+
t
-
~
-
TRACK
REG
H:;-
STATUS
REG
t
.-
INDATA
L-
DATA
SHIFT
REG
A
L
.1-.
W RITE DATA ...........
(TO DISK)
U
1-
~
..
i
t
I
SECTOR
REG
INSTR
CRCLOGIC
DRQ
WG
TG43
.. INTRQ
WPRT
WJ5
MR
~
At
WE
AO
COMPUTER
INTERFACE
CONTROL
CONTROL
PLA
CONTROL
(190x16)
CONTROL
..
A1
DISK
INTERFACE
CONTROL
j15
TROD
READY
STEP
DIRC
AMIN
AMOT
iJDEN
HLD
HLT
CLK
Figure 3.
FD1781 BLOCK DIAGRAM
155
-
."
C
.....
......
00
.....
-.....
."
C
......
00
.....
6.....
During Direct Memory Access (DMA) types of data
transfers between the Data Register of the FD1781
and the processor, the Data Request (DRa) output
is used in Data Transfer control. This signal also
appears as status bit 1 during Read and Write
operations.
Step - A 2 JJs pulse is provided as an output to the
drive. For every step pulse issued, the drive moves
one track location in a direction determined by the
direction output.
Direction (DIRC) - The Direction signal is active high
when stepping in and low when stepping out. The
Direction signal is valid 12 JJs before the first stepping
pulse is generated .
On Disk Read operations the Data Request is activated (set high) when an assembled serial input
byte is transferred in parallel to the Data Register.
This bit is cleared when the Data Register is read by
the processor. If the Data Register is read after one or
more characters are lost, by having new data transferred into the register prior to processor readout, the
lost Data bit is set in the Status Register. The Read
operation continues until the end of sector is
reached.
When a Seek, Step or Restore command is executed
an optional verification of Read-Write head position
can be performed by setting bit 2 in the command
word to a logic 1. The verification operation begins at
the end of the 15 millisecond settling time after the
head is loaded against the media. The track number
from the first encountered ID Field is compared
against the contents of the Track Register. If the
track numbers compare and the ID Field Cyclic
Redundancy Check (CRG) is correct, the verify
operation is complete. If track comparison is not
made but the CRC checks, an interrupt is generated,
the Seek Error status (Bit 4) is set and the Busy status
bit is preset.
On Disk Write operations the Data Request is activated when the Data Register transfers its contents
to the Data Shift Register, and requires a new data
byte. It is reset when the Data Register is loaded with
new data by the processor. If new data is not loaded
at the time the next serial byte is required by the
Floppy Disk, a byte of zeroes is written on the
diskette and the lost Data bit is set in the Status
Register.
TABLE 1
STEPPING RATES
elK
The lost Data bit and certain other bits in the Status
Register will activate the interrupt request (INTRa).
The interrupt line is also activated with normal
completion or abnormal termination of all controller
operations. The INTRa Signal remains active until
reset by reading the Status Register to the processor
or by the loading of the Command Register. In addition, the INTRa is generated if a Force Interrupt
command condition is met.
--
2MHz
1 MHz
1 MHz 1/2 MHz 2MHz
1 MHz
0
1
1
PDEN _ _
0
A1 AO TEST= 1 TEST= 1 TEST= 1 TEST= 1 TEST=O TEST=O
0 0
3ms
3ms
6ms
6ms Approx. Approx.
0 1
6ms
12 ms
12ms
6ms
400/Js
aoo/Js
1 0 10ms
10ms
20 ms
20ms
1 1 20ms
20 ms
40ms
40ms
The Head load (H Dl) output controls the movement
of the read/write head against the disk for data
recording or retrieval. It is activated at the beginning
of a Read, Write (E Flag On) or Verify Operation, or a
Seek or Step operation with the head load bit, h, a
logic one, and remains activated until the 15th index
pulse following the last operation which uses the
read/write head. Reading or Writing does not occur
until a minimum of 15 msec delay after the HDl
signal is made active. If executing the type 2 commands with the E flag off, there is no 15 msec delay
and the head is assumed to be engaged. The delay is
determined by sampling of the Head Load Timing
(HLT) input every 15 msec. A high logic state input,
generated from the Head load output transition and
delayed externally, identifies engagement of the head
against the disk. In the Seek and Step commands,
the head is loaded at the start of the command
execution when the h bit is a logic one. In a verify
command the head is loaded after stepping to the
destination track on the disk whenever the h bit is a
logic zero.
FLOPPY DISK INTERFACE
The Floppy Disk interface consists of head positioning controls, write gate controls, and data
transfers. The Clock (ClK) input is normally a freerunning 2 MHz ± 1% when in the double density
mode and 1 MHz ± 1% when in the Single density
mode. However when using a mini-floppy, the ClK is
normally 1 MHz when in double density mode and 1/2
MHz when in the single density mode.
HEAD POSITIONING
Four commands cause positioning of the Read-Write
head (see Command Section). The period of each
positioning step is specified by the r field in bits 1
and 0 of the command word. After the last directional
step an additional 15 milliseconds of head settling
time takes place. The four progammable stepping
rates are tabulated below.
DISK READ OPERATION
The rates (shown in Table 1) can be applied to a StepDirection Motor through the device interface.
The normal sector length for Read or Write operations with the IBM 3740 format is 128 bytes. This
156
TABLE 2
COMMAND SUMMARY
format or binary multiples of 128 bytes will be
adopted by setting a logic 1 in Bit 3 of the Read Track
and Write Track commands. Additionally, a variable
sector length feature is provided which allows an
indicator recorded in the ID Field to control the
length of the sector. Variable sector lengths can be
read or written in Read or Write commands respectively by setting a logic 0 in Bit 3 of the command
word. The sector length indicator specifies the
number of 16 byte groups or 16 x N, where N is equal
to 1 to 256 groups. An indicator of all zeroes is interpreted as 256 sixteen byte groups.
TYPE COMMAND
I
Restore
I
Seek
I
Step
I
Step In
I
Step Out
1/
Read Command
/I
Write Command
1/1
Read Address
11/
Read Track
1/1
Write Track
IV
Force Interrupt
X = Don't care
IDISK WRITE OPERATION
When writing is to take place on the diskette the
Write Gate rNG) output is activated, allowing current
to flow into the ReadlWrite head. As a precaution to
erroneous writing the first data byte must be loaded
into the Data Register in response to a Data Request
from the FD1781 before the Write Gate signal can be
activated.
Writing is inhibited when the Write Protect input isa
logic low, in which case any Write command is
immedi\1el Y terminated, an interrupt is generated
and the rite Protect status bit is set. The Write Fault
input, when activated, signifies a writing fault condition detected in disk drive electronics such as
failure to detect write current flow wHen the Write
Gate is activated. On detection of this fault the
FD1781 terminates the current command, and sets
the Write Fault bit (bit 5) in the Status Word. The
Write Fault input should be made inactive when the
Write Gate output becomes inactive.
7
0
0
0
0
0
1
1
1
1
1
1
6
0
0
0
1
1
0
0
1
1
1
1
5
0
0
1
0
1
0
1
0
1
1
0
BITS
4 3 2
0
1
u
u
u
m
m
0
0
1
1
h
h
h
h
h
b
b
0
0
0
13
TABLE 3
FLAG SUMMARY
TYPE I
h = Head Load Flag (Bit 3)
h = 1, Load head at beginning
h = 0, Do not load head at beginning
V = Verify flag (Bit 2)
V = 1, Verify on last track
V = 0, No verify
r1 ro = Stepping motor rate (Bits 1-0)
Refer to Table 1 for rate summary
u = Update flag (Bit 4)
u = 1, Update Track register
u = 0, No update
Whenever a Read or Write command is received the
FD1781 samples the Ready input. If this input is logic
low the command is not executed and an interrupt is
generated. The Seek or Step commands are performed regardless of the state of the Ready input.
COMMAND DESCRIPTION
The FD1781 will accept and execute eleven commands. Command words should only be loaded in
the Command Register when the Busy status bit is
off (Status bit 0). The one exception is the Force
Interrupt command. Whenever a command is being
executed, the Busy status bit is set. When a command is completed, an interrupt is generated and the
Busy status bit is reset. The Status Register indicates
whether the completed command encountered an
error or was fault free. For ease of discussion,
commands are divided into four types. Commands
and types are summarized in Table 2.
TABLE 4
FLAG SUMMARY
TYPE 1/
m = Multiple Record flag (Bit 4)
m = 0, Single Record
m = 1, Multiple Records
b = Block length flag (Bit 3)
b = 1, IBM format (128 to 1024 bytes)
b = 0, Non-IBm format (16 to 4096 bytes)
ao = Data Address Mark (Bit 0)
ao = 0, FB (Data Mark)
ao = 1, F8 (Deleted Data Mark)
TYPE I COMMANDS
The Type I Commands include the Restore, Seek,
Step, Step-In, and Step-Out commands. Each of the
Type I Commands contain a rate field (ror1), which
determines the stepping motor rate as defined in
Table 1, page six .
•
157
V
V
V
V
V
E
E
1
1
1
12
1
r1
r1
r1
r1
r1
0
X
0
0
0
11
0
ro
ro
ro
ro
ro
0
ao
0
S0
10
TABLES
FLAG SUMMARY
-n
c.....
......
0)
.....
:;;
c
.....
......
.....
6.....
0)
TYPE III
s Synchronize flag (Bit 0)
S 0, Synchronize to AM
5 1, Do Not Synchronize to AM
TYPE IV
Ii
Interrupt Condition flags (Bits 3-0)
10
1, Not Ready to Ready Transition
11
1, Ready to Not Ready Transition
12
1, Index Pulse
13
1, Immediate interrupt
E Enable HLD and 10 msec Delay
E 1, Enable HLD, HLT and 15 msec Delay
E
0, Head is assumed Engaged and there is no
15 msec Delay
=
=
=
=
=
=
=
=
=
=
=
NO
The Type I Commands contain a head load flag (h)
which determines if the head is to be loaded at the
beginning of the command. If h = 1, the head is
loaded at the beginning of the command (HLD output
is made active). If h = 0, HLD is deactivated. Once
the head is loaded, the head will remain engaged
until the FD1781 receives a command that specifically disengages the head. If the FD1781 does not
receive any commands after two revolutions of the
disk, the head will be automatically disengaged (HLD
made inactive). The Head Load Timing Input is
sampled after a 15 ms delay, when reading or writing
on the disk is to occur.
RESET HLD
SET
DIRECTION
RESET
DIRECTION
The Type I Commands also contain a verification (V)
flag which determines if a verification operation is to
take place on the destination track. If V = 1, a
verification is performed, if V = 0, no verification is
performed.
During verification, the head is loaded and after an
internal 15 ms delay, the HLT input is sampled. When
HLT is active (logic true), the first encountered 10
field is read off the disk. The track address of the 10
field is then compared to the Track Register; if there
is a match and a valid 10 CRC, the verification is
complete, an interrupt is generated and the Busy
status bit is reset. If there is not a match but there is
valid 10 CRC, an interrupt is generated, the Seek Error
status bit (Status bit 4) is set and the Busy status bit
is reset. If there is a match but not a valid CRC, the
CRC error status bit is set (Status bit 3), and the next
encountered 10 field is read from the disk for the
verification operation. If an 10 field with a valid CRC
cannot be found after four revolutions of the disk, the
FD1781 terminates the operation and sends an interrupt, (INTRQ).
YES
B
The Step, Step-In, and Step-Out commands contain
an Update flag (U). When U = 1, the track register is
updated by one for each step. When U = 0, the track
register is not updated.
Figure 4.
158
TYPE I COMMAND FLOW
BESTORE (SEEK TRACK 0)
Upon receipt of this command the Track 00 (TRoo)
input is sampled. If TRoo is active low indicating the
I~ead-Write head is positioned over track 0, the Track
Register is loaded with zeroes and an interrupt is
generated. If TRoo is not active low, stepping pulses
(pins 15 to 16) at a rate specified by the r1ror field are
issued until the TRoo input is activated. At this time
the TR is loaded with zeroes and an interrupt is
!Jenerated. If the TRoo input does not go active low
after 255 stepping pulses, the FD1781 terminates
operation, interrupts, and sets the Seek error status
bit. Note that the Restore command is executed
when MR goes from an active to an inactive state. A
verification operation takes place if the V flag is set.
The h bit allows the head to be loaded at the start of
command.
SEEK
This command assumes that the Track Register
contains the track number of the current position of
the Read-Write head and the Data Register contains
the desired track number. The FD1781 will update the
Track register and issue stepping pulses in the appropriate direction until the contents of the Track
register are equal to the contents of the data register
(the desired track location). A verification operation
takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the
command.
STEP
Upon receipt of this command, the FD1781 issues
one stepping pulse to the disk drive. The stepping
motor directilon is the same as in the previous step
command. After a delay determined by the r1 ro field,
a verification takes place if the V flag is on. If the u
flag is on, the TR is updated. The h bit allows the
head to be loaded at the start of the command. An
interrupt is generated at the completion of the
command.
STEp·IN
Upon receipt of this c.ommand, the FD1781 issues
one stepping pulse in the direction towards track 76.
If the u flag is on, the Track Register is incremented
by one. After a delay determined by the r1 ro field, a
verification takes place if the V flag is on. The h bit
allows the head to be loaded at the start of the
command. An interrupt is generated at the completion of the command.
o
STEP·OUT
FigureS.
Upon receipt of this command, the FD1781 issues
one stepping pulse in the direction towards track O. If
159
TYPE I COMMAND FLOW
".....c
~
.....
:;;
c.....
......
(X)
.....
6.....
the u flag is on, the TR is decremented by one. After a
delay determined by the r1 ro field, a verification takes
place if the V flag is on. The h bit allows the head to
be loaded at the start of the command. An interrupt is
generated at the completion of the command.
TYPE II COMMANDS
The Type II Commands include the Read Sector (s)
and Write Sector (s) commands. Prior to loading the
Type II Command into the Command Register, the
computer must load the Sector Register with the
desired sector number. Upon receipt of the Type II
Command, the busy status Bit is set. If the E flag = 1
(this is the normal case) HLD is made active and HLT
is sampled after a 15 msec delay. If the E flag is 0, the
head is assumed to be engaged and there is no 15
msec delay. The ID field and Data Field format are
shown on page 11.
When an ID field is located on the disk, the FD1781
compares the Track Number of the ID field with the
Track Register. If there is not a match, the next encountered ID field is read and a comparison is again
made. If there was a match, the Sector Number of the
ID field is compared with the Sector Register. If there
is not a Sector match, the next encountered ID field
is read off the disk and comparisons again made. If
the ID field CRC is correct, the data field is then
located and will be either written into, or read from
depending upon the command. The FD1781 must
find an ID field with a Track number, Sector number,
and CRC within four revolutions of the disk; otherwise, the Record not found status bit is set (Status bit
3) and the command is terminated with an interrupt.
Each of the Type II Commands contain a (b) flag
which in conjunction with the sector length field
contents of the ID determines the length (number of
characters) of the Data field.
For IBM 3740 compatibility, the b flag should equal 1.
The numbers of bytes in the data field (sector) is then
128 x 2n where n
0,1,2,3.
=
For b = 1
Sector Length
Field (hex)
00
01
02
03
Number of Bytes
in Sector (decimal)_
128
256
512
1024
When the b flag equals zero, the sector length field
(n) multiplied by 16 determines the number of bytes
in the sector or data field as shown on page 11.
NOTE: IF TEST·D, THERE IS NO 15MS DELAY.
IF TEST·1 ANC CLK·1 MHz. THERE IS 3DMS DELAY.
FigureS_
160
TYPE I COMMAND FLOW
For b =
a
Sector Length
Field (hex)
At the end of the Read operation, the type of Data
Address Mark encountered in the data field is
recorded in the Status Register (Bits 5) as shown
below:
Number of Bytes
in Sector (decimal)
01
16
02
32
03
48
04
64
•
•
•
STATUS
BIT5
1
a
1
1
CO
a
a
.......
......
Upon receipt of the Write command, the head is
loaded (HLD active) and the Busy status bit is set.
When an ID field is encountered that has the correct
track number, correct sector number, and correct
CRC, a DRO is generated. The FD1781 counts off 11
bytes in single density and 22 bytes in double density
from the CRC field and the Write Gate (WG) output is
made active if the DRO is serviced (Le., the DR has
been loaded by the computer). If DRO has not been
serviced, the command is terminated and the lost
Data status bit is set. If the DRO has been serviced
the WG is made active and six bytes of zeros i~
single density and 12 bytes in double density are
then written on the disk. At this time the Data Ad·
dress Mark is then written on the disk as determined
by the aO field of the command as shown below:
1
a
I
I
TRACK
SECTOR SECTOR ICRC ICRC I
NUMBER ZEROS NUMBER LENGTH
1
2
GAP
ID FIELD
IDAM
= ID Address Mark
Data Address Mark
Data AM
DATA
DATA
DATA 1
DATA 2
DATA 3
a
a
a
a
1
1
The FD1781 then writes the data field and generates
DRO's to the computer. If the DRO is not serviced in
time for continuous writing the lost Data Status Bit
is set and a byte of zeros is written on the disk. The
command is not terminated. After the last data byte
has been written on the disk, the two-byte CRC is
computed internally and written on the disk followed
by one byte gap of logic ones. The WG output is then
deactivated.
When the first character or byte of the data field has
been shifted through the DSR, it is transferred to the
DR, and DRO is generated. When the next byte is
accumulated in the DSR, it is transferred to the DR
and another DRO is generated. If the Computer has
not read the previous contents of the DR before a
new character is transferred that character is lost and
the Lost Data Status bit is set. This sequence con·
tinues until the complete data field has been inputted
to the computer. If there is a CRC error at the end of
the data field, the CRC error status bit is set, and the
command is terminated (even if it is a multiple record
command).
I
a
a
C
......
WRITE COMMAND
Upon receipt of the Read command, the head is
loaded, the Busy status bit set, and when an ID field
is encountered that has the correct track number
correct sector number, and correct CRC the dat~
field is presented to the computer. The Data Address
Mark of the data field must be found within 30 bytes
in single density and 43 bytes in double density of
the last ID field CRC byte; if not, the Record Not
Found status bit is set and the operation is ter·
minated.
I
."
DATA 3
6......
READ COMMAND
10
AM
-
DATA 2
4080
I I
.......
DATA 1
4096
Each of the Type II Commands also contain a (m) flag
which determines if multiple records (sectors) are to
be read or written, depending upon the command. If
m = a a single sector is read or written and an in·
terrupt is generated at the completion of the com·
mand. If m= 1, multiple records are read or written
with the sector register internally updated so that an
address verification can occur on the next record.
The FD1781 will continue to read or write multiple
records and update the sector register until the
sector register exceeds the number of sectors on the
track or until the Force Interrupt command is loaded
into the Command Register, which terminated the
command and generates an interrupt.
GAP
C
......
CO
......
•
•
•
FF
00
."
(FE)16 ClK = (C7)16
(F8 or FB), ClK = (C'7)16
161
DATAl
AM
DATA FIELD
DATA FIELD
I I
1
2
."
C
.....
...."
()C)
.....
-.....
."
C
...."
()C)
.....
6
.....
NO
NO
NO
BRING IN SECTOR LENGTH FIELD
COMPUTE LENGTH FROM B FLAG
STORE LENGTH IN INTERNAL REGISTER
:.READ
It
'NOTE: IF TEST·O, THERE IS NO 15MS DELAY.
IF TEST·1 AND CLK·1 MHz. THIS IS A 30MS DELAY.
Figure 7.
Figure 8.
TYPE II COMMAND
162
TYPE II COMMAND
SET DATA
LOST
WRITE BYTE
OF ZEROS
Figure 9.
TYPE II COMMAND
Figure 10.
163
TYPE II COMMAND
."
C
.....
.....
00
.....
."
C
.....
.....
00
.....
6.....
NOTE: IF TEST-O, THERE IS NO 15MS DELAY,
IF irn-1 AND CLK-1 MHz. THIS IS A 30MS DELAY.
Figure 11.
TYPE III COMMAND WRITE TRACK
TYPE III COMMANDS
READ ADDRESS
Upon receipt of the Read Address command, the
head is loaded and the Busy Status Bit is set. The
next encountered 10 field is then read in from the
disk, and the six data bytes of the 10 field are
assembled and transferred to the DR, and a ORO is
generated for each byte. The six bytes of the 10 field
are shown below:
SECTOR
TRACK
ADDR ZEROS ADDRESS
1
2
3
SECTOR CRC CRC
LENGTH 1
2
4
5
6
Although the CRC characters are transferred to the
computer, the F01781 checks for validity and the
CRC error status bit is set if there is a CRC error. The
Track Address of the 10 field is written into the sector
register. At the end of the operation an interrupt is
generated and the Busy Status is reset.
READ TRACK
Upon receipt of the Read Track command, the head
is loaded and the Busy Status bit is set. Reading
starts with the leading edge of the first encountered
index mark and continues until the next index pulse.
164
As each byte is assembled it is transferred to the
Data Register and the Data Request is generated for
each byte. No CRC checking is performed. Gaps are
included in the input data stream. If bit 0 (S) of the
command is a 0, the accumulation of bytes is synchronized to each Address Mark encountered. Upon
completion of the command, the interrupt is activated.
."
C
.....
........
CO
.....
."
C
.....
.....
........
CO
WRITE TRACK
6.....
Upon receipt of the Write Track command, the head
is loaded and the Busy Status bit is set. Writing starts
with the leading edge of the first encountered index
pulse and continues until the next index pulse, at
which time the interrupt is activated. The Data
Request is activated immediately upon receiving the
command, but writing will not start until after the first
byte has been loaded into the Data Register. If the DR
has not been loaded by the time the index pulse is
encountered the operation is terminated making the
device Not Busy, the Lost Data Status Bit is set, and
the Interrupt is activated. If a byte is not present in
the DR when needed, a byte of zeros is substituted.
Address marks and CRC characters are written on
the disk by detecting certain data byte patterns in the
outgoing data stream as shown in the table below.
The CRC generator is initialized when any data byte
from F8 to FE is about to be transferred from the DR
to the DSR.
CONTROL BYTES FOR INITIALIZATION
DATA
PATTERN INTERPRETATION
(HEX)
CLOCKMARK*
(HEX)
F7
Write CRC Char.
F8 r Deleted Data Addr. Mark
Data Addr. Mark
FB
FC
Index Addr. Mark
FD
Spare
FE
10 Addr. Mark
*Single density only
DATA
1
DATA
2
DATA
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
3
0
1
1
FF
C7
C7
07
Figure 12.
C7
TYPE OF
ADDRESS MARK
Deleted Data Mark
Data Mark
Index Address Mark
Undefined
10 Address Mark
Undefined
165
TYPE III COMMAND WRITE TRACK
~
....
......
~
:;;
C
....
......
~
6
....
TYPE IV COMMAND
STATUS DESCRIPTION
FORCE INTERRUPT
Upon receipt of any command, except the Force
Interrupt command, the Busy Status bit is set and the
rest of the status bits are updated or cleared for the
new command. If the Force Interrupt Command is
received when there is a current command under
execution, the Busy status bit is reset, and the rest of
the status bits are unchanged. If the Force Interrupt
command is received when there is not a current
command under execution, the Busy Status bit is
reset and the rest of the status bits are updated or
cleared. In this case, Status reflects the Type I
commands.
This command can be loaded into the command
register at any time. If there is a current command
under execution (Busy Status Bit set), the command
will be terminated and an interrupt will be generated
when the condition specified in the 10 through 13 field
is detected. The interrupt conditions are shown
below:
=
10
Not-Ready-To-Ready Transition
11 = Ready-To-Not-Ready Transition
12 = Every Index Pulse
13 = Immediate Interrupt
The format of the Status Register is shown below:
NOTE: If 10-13 = 0, there is no interrupt generated
but the current command is terminated and
busy is reset.
I ;7 I
S~
I ;5 I S~ I :3 I :2
1;1
I S~ I
Status varies according to the type of command
executed as shown in Table 6.
ALL TYPE I
READ
BIT COMMANDS
ADDRESS
S7 NOT READY
NOT READY
S6 WRITE
0
PROTECT
S5 HEAD
0
ENGAGED
S4 SEEK ERROR IDNOTFOUND
S3
S2
S1
SO
CRCERROR
TRACK 0
INDEX
BUSY
CRCERROR
LOST DATA
DRO
BUSY
TABLE 6
STATUS REGISTER SUMMARY
READ
READ
TRACK
NOT READY
NOT READY
0
0
RECORD TYPE
0
RECORD NOT
FOUND
CRCERROR
LOST DATA
DRO
BUSY
0
0
LOST DATA
DRO
BUSY
WRITE
NOT READY
WRITE
PROTECT
WRITE FAULT
RECORD NOT
FOUND
CRCERROR
LOST DATA
DRO
BUSY
WRITE
TRACK
NOT READY
WRITE
PROTECT
WRITE FAULT
0
0
LOST DATA
DRO
BUSY
STATUS FOR TYPE I COMMANDS
BIT NAME
MEANING
S7 NOT READY
This bit when set indicates the drive is not ready. When reset it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and logically 'ored' with MR.
S6 PROTECTED
When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.
S5 HEAD LOADED
When set, it indicates the head is loaded and engaged. This bit is a logical "and" of
HLD and HLT signals.
S4 SEEK ERROR
When set, the desired track was not verified. This bit is reset to 0 when updated.
S3CRC ERROR
When set, there was one or more CRC errors encountered on an unsuccessful track
verification operation. This bit is reset to 0 when updated.
S2 TRACK 00
When set, indicates Read Write head is positioned to Track O. This bit is an invertecl
copy of the T"ROO input.
S11NDEX
When set, indicates index mark detected from drive. This bit is an inverted copy of the
jj5 input.
SO BUSY
When set command is in progress. When reset no command is in progress.
166
STATUS BITS FOR TYPE II AND TYPE III COMMANDS
BIT NAME
MEANING
S7 NOT READY
This bit when set indicates the drive is not ready. When reset, it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and 'ored' with MR. The Type II
and III Commands will not execute unless the drive is ready.
CO
S6 WRITE PROTECT
On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a Write
Protect. This bit is reset when updated.
:;;
S5 RECORD TYPE/
WRITE FAULT
On Read Record: It indicates the record-type code from data field address mark. On
Read Track: Not Used. On any Write: It indicates a Write Fault. This bit is reset when
updated.
84 RECORD NOT
FOUND
When set, it indicates that the desired track and sector were not found. This bit is reset
when updated.
S3CRCERROR
If S4 is set, an error is found in one or more ID fields; otherwise it indicates error in data
field. This bit is reset when updated.
S2 LOST DATA
When set, it indicates the computer did not respond to DRQ in one byte time. This bit
is reset to zero when updated.
S1 DATA REQUEST
This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read
operation or the DR is empty on a Write operation. This bit is reset to zero when updated.
SO BUSY
When set, command is under execution. When reset, no command is under execution.
the present time only defines two formats. One
format with 128 bytes/sector and the other with 256
bytes/sector. The next section deals with the IBM
3740 format with 128 bytes/sector and the following
section details non-IBM formats.
FORMATTING THE DISK
(Refer to section on Type III commands for flow
diagrams.)
Formatting the disk is a relatively simple task when.
operating programmed 110 or when operating under
DMA control with a large amount of memory. When
operating Ulnder DMA with limited amount of
memory, formatting is a more difficult task. This is
because gaps as well as data must be provided at the
computer interface.
IBM 3740 FORMATS - 128 BYTES/SECTOR
Shown in Figure 13, is the IBM format with 128
bytes/sector. In order to format this format, the user
must issue the Write Track command, and load the
data register with the following values. For every byte
to be written, there is one data request.
Formatting the disk is accomplished by positioning
the RIW head over the desired track number and
issuing the Write Track command. Upon receipt of
the Write Track command, the FD1781 raises the data
request signal. At this point in time, the user loads
the data register with desired data to be written on
the disk. For every byte of information to be written
on the disk, a data request is generated. This
sequence continues from one index mark to the next
index mark. Normally, whatever data pattern appears
in the data register is written on the disk with a clock
mark of (FFh6. However, if the FD1781 detects a data
pattern on F7 thru FE in the data register, this is
interpreted as data address marks with missing
clocks or CRC generation. For instance, an FE
pattern will be interpreted as an ID address mark
(DATA-FE, CLK-C7) and the CRC will be initialized. An
F7 pattern will generate two CRC characters. As a
consequence, the patterns F7 thru FE must not
appear in the gaps, data fields, or ID fields. Also,
CRC's must be generated by a F7 pattern.
NUMBER
HEX VALUE OF
BYTE WRITTEN
OF BYTES
40
OOorFF
6
00
1
FC (Index Mark)
26
OOor FF
6
00
1
FE (ID Address Mark)
1
Track Number
1
00
1
Sector Number(1 thru 1A}
1
00
1
F7 (2 CRG's written)
11
00 or FF
6
00
1
FB (Data Address Mark)
128
Data (IBM uses E5)
1
F7 (2 CRC's written)
27
00 or FF
00 or FF
247* *
*Write bracketed field 26 times
* *Continue writing until FD1781 interrupts out.
Approx. 247 bytes.
Disks may be formatted in IBM 3740 formats with
sector lengths of 128, 256, 512, or 1024 bytes, or may
be formatted in non-IBM 3740 with sectors length of
16 to 4096 bytes in 16 byte increments. IBM 3740 at
167
."
C
......
~
......
c
......
~
CO
......
6
......
IL_____________________________
PHYSICAL
' ' '" "'' ~ f '"' ""'" "'"'
DATA
FIELD
RECORD
26
GAP1
POST
INDEX
32
BYTES
CAP4
PRE INDEX
320 BYTES
NOMINAL
GAP2
10
10
RECORD
N01
GAP
17
BYTES
GAP3
DATA FIELD
DATA
RECORD
GAP
N02
33 BYTES
10
10
RECORD
N02
RECORD
N026
I
GAP 2
DATA FIELDI GAP 4
RECORD
N026
131
I
10
TRACK
ADDRESS ADDRESS
MARK
I
I
SECTOR
ZEROES ADDRESS
I
ZEROES
I
CRC
BYTE 1
CRC
BYTE 2
1+--11 BYTES-/-6BYTES--j
WRITE GATE TURN ON FOR UPDATE
OF NEXT DATA FIELD
~
Figure 13.
FD1781/FD1781-01
DATA OR
DELETED
DATA
ADDRESS
MARK
- 1 1 BYTE
128 BYTES OF USER
DATA
I-
32 BYTES
~WRITE
TURN OFF FOR UPDATE
OF PREVIOUS DATA FIELD
IBM 3740 TRACK FORMAT
_I
-I
CRC
CRC
8YTI; 1
8YTIO?
co
co
NON·IBM FORMATS
The F01781 does not require the index address mark
(Le., DATA
FC, CLK
07) and it need not be
present.
=
Non-IBM formats are very similar to the IBM formats
except a diHerent algorithm is used to ascertain the
sector length from the sector length byte in the 10
field. This permits a wide range of sector lengths
from 16 to 4096 bytes. Refer to Section V, Type II
Commands with b flag equal to zero. Note that F7
thru FE must not appear in the sector length byte of
the 10 field.
=
REFERENCES:
1.
2.
.....
:nc
.....
......
Q)
In formatting the F01781, only two requirements
regarding GAP sizes must be met. GAP 2 (Le., the gap
between the 10 field and data field) must be 17 bytes
of which the last 6 bytes must be zeros in single
density mode, and 34 bytes of which the last 12 bytes
must be zeros in double density mode. For the
F01781-01, these byte counts for GAP2 are doubled.
=
=
=
.....
6.....
MAXIMUM RATINGS
VOO With Respect to VSS (Ground) .. + 15 to - 0.3V
Max. Voltage to Any Input With
Respect to VSS ................ + 15 to - 0.3V
Operating Temperature .............. O°C to 70 DC
Storage Temperature .......... - 55°C to + 125°C
=
=
TA
O°C to 70°C, VOO
+ 12.0V ± .6V, VSS
OV, VCC
+ 5V ± .25V
VOO
10 ma Nominal, VCC
30 ma Nominal
DC characteristics TA
ODC to 50°C; VOO
12V ± .6V, VSS
OV, VCC
=
SYMBOL
=
CHARACTERISTIC
=
=
MIN
TYP
= 5V ± .25V
MAX
Input Leakage
III
10
Output Leakage
10
ILO
Input High Voltage
2.6
VIH
Input Low Voltage (All Inputs)
0.8
VIL
Output High Voltage
2.8
VOH
Output Low Voltage
V·OL
0.45
NOTE: Vol ~ .4V when mterfaclng with low Power Schottky parts (10 < 1 ma)
• except WG, where VOL ~.5 volts.
UNITS
IJA
IJA
V
V
V
V
CONDITIONS
=
VIN
VOO
VOUT
VOO
10
10
=
= -100IJA
= 1.6mA
TIMING CHARACTERISTICS
TA
= 0°Ct050°C,VOO = +12V ±.6V,VSS = OV,VCC =
+5V ±.25V
NOTE: Timings are given for 2 MHz Clock. For those timings noted, values will double when chip is
operated at 1 MHz.
READ OPERATIONS
--
SYMBOL
TSET
THLO
TRE
TORR
TIRR
TOACC
TOOH
CHARACTERISTIC
Setup AOOR & CS to RE
Hold AOOR & CS from RE:
RE Pulse Width
ORa Reset from RE
INTRa Reset from RE
Data Access from RE
Data Hold From RE
C
Q)
IBM Diskette OEM Information GA21-9190-1
SA900 IBM Compatibility Reference Manual Shugart Associates.
ELECTRICAL CHARACTERISTICS
OPERATING CHARACTERISTICS (DC)
"...........
MIN
TYP
MAX
UNITS
500
3000
350
150
nsec
nsec
nsec
nsec
nsec
nsec
nsec
100
10
500
500
50
169
CONDITIONS_._--
CL
= 25 pf
CL
CL
= 25 pf
= 25 pf
READ ENABLE TIMING
-n
c.....
I~
......
CO
.....
·1
::::16j.1 s 2',
j..-TDRR
,VOLT
-n
c.....
DRQVOL
......
.....
6.....
CO
..I
.TIRR'
INTRQ
I
VOL
1
'---------"VIL
AO, A1, CS - - - - '
RE
---+--~___ ~r-----------
VIH
j r'--------
DATA VALID (DAL)
READ DATA
(BUFFERS TRI-STATED)
TOOH
NOTE: 1. CS MAY BE PERMANENTLY TIED LOW IF DESIRED.
2. FOR READ TRACK COMMAND. THIS TIME MAY BE
6' TO 16' j.lSEC WHEN S o.
'TIME DOUBLES WHEN CLK-1 MHz.
=
WRITE OPERATIONS
SYMBOL
TSET
THLD
TWE
TDRR
TIRR
TDS
TDH
CHARACTERISTIC
Setup ADDR & CS to WL
Hold ADDR & CS from WE
WE Pulse Width
DRO Reset from WE
I NTRO Reset from WE
Data Setup to
Data Hold from WE
wr=.
MIN
TYP
MAX
100
10
350
500
500
250
20
"170
3000
UNITS
nsec
nsec
nsec
nsec
nsec
nsec
nsec
CONDITIONS
See Note
•
WRITE ENABLE TIMING
DRQVOL
INTRQ ~------~----------~
' - - - - - - - - - VOL
AO,A1,CS
1
' - - - - - - - - - - - - VI L
.....-TWE
WE - - 1 - -.....,
~I- - - - - - V I H
I
-.~~
TSET
DATA VALID DAL
WRITE DATA
----1----
L..._ _ _ _ __
DESIR~TDS
NOTE: 1. CS MAY BE PERMANENTLY TIED LOW IF
2. WHEN WRITING DATA INTO SECTOR, TRACK, OR
DATA REGISTER, USER CANNOT READ THIS
REGISTER UNTIL AT LEAST 8 ~SEC AFTER THE
RISING EDGE OF WE. WHEN WRITING INTO THE
COMMAND REGISTER STATUS IS NOT VALID
UNTIL SOME 12~SEC LATER. THESE TIMES ARE
DOUBLED WHEN CLK = 1 MHz.
-TIME DOUBLES WHEN CLOCK
1 MHz.
.;:}----
=
INPUT DATA TIMING
DEFINES TYPE
OF ADDRESS MARK
)4
!
- -.... '"D-C...... 'D-C......
INDATA VIL
I
•.
AMIN
VIL
-+-1
tp
r-
- lSi L,
~
11
VIL _____________-1
=
tpw
500 ns
50 ns
t s ;a.100ns
th ;a. 300 ns
1 2~s < tp < 1/2 ms
•
~
I
INSTR
BEGINNING OF ID FIELD
OR DATA FIELD
-
-+- tsj..j.l
-J t .....-
1.._ _ _ _ _ _ _ _ _ _ _ _ __
NOTE: INSTR MUST BE FREE RUNNING AS INDICATED BY THE tp
SPECIFICATION. ALSO, THERE MUST BE AT LEAST 2
INSTR PULSES DURING MASTER RESET.
171
'TI
i
OUTPUT DATA TIMING
C
.....
.......
00
.....
'TI
OTDATA
C
.....
.......
00
.....
6.....
VOL
BYTE BOUNDARY-DEFINES TYPE
BEGINNING OF ID FIELD
OF ADDRESS MARK
OR DATA FIELD
.,
OTSTR
Ir--------,I
C7CLOCK
------------~I
AMOT
~------------------VOL
I
I
D7 CLOCK (WRITE TRACK ONLY) 1Ls-l'--________________ VOL
DDEN
tA
tB
tc
1
SEE NOTE
~
DDEN 0
2 lAs
1 lAs
1 lAs
CLK 2 mHz
NOTE:
WHENEVER DDEN O. OTSTR IS FREE RUNNING AS SHOWN
ABOVE.
WHEN i5i5'EN' 1 & WG 0, OTSTR IS A SERIES OF FM CLOCK
PULSES.
WHEN DDEN 1 & WG 1, OTSTR BECOMES WD AS IN THE
FD1771 (Le. CONTAINS FM CLOCK & DATA PULSES).
MISCELLANEOUS TIMING:
."-
SYMBOL
TCD1
TCD2
TSTP
TDIR
TMR
TIP
TWF
CHARACTERISTIC
Clock Duty
Clock Duty
Step Pulse Output
Dir Setup to Step
Master Reset Pulse Width
Index Pulse Width
Write Fault Pulse Width
TYP
MIN
175
210
2000
12
5
5
5
MAX
CONDITIONS
UNITS
nsec 2 MHz ± 1% See Note
nsec
nsec
/-tsec
>These times doubled
/-tsec
when ClK = 1 MHz
/-tsec
/-tsec
MISCELLANEOUS TIMING
iPJ
{VIH
I
~TIP-.j
WF;
JVIH
I---TWF~
MRj
VOH
DIRC VOL
STEP
VOL
jVIH
-.J
STEP IN
-1 ~
STEP OUT
I:DIR...1STPI....jTSTP\.- I~Dlf!,. ?TPr---Joo.jTSTP1'--Jf--
~~J--
See page 725 for ordering information.
172
WESTERN DIGITAL
CORPORATION
FD179X-02
Floppy Disk Formatter/Controller Family
"......""""
c
co
><
FEATURES
6
•
PROGRAMMABLE CONTROLS
Selectable Track to Track Stepping Time
Side Select Compare
• INTERFACES TO WD1691 DATA SEPARATOR
• WINDOW EXTENSION
• INCORPORATES ENCODING/DECODING AND
ADDRESS MARK CIRCUITRY
• FD179214IS SINGLE DENSITY ONLY
• FD1795/7 HAS A SIDE SELECT OUTPUT
•
•
•
•
TWO VFO CONTROL SIGNALS - RG & VFOE
SOFT SECTOR FORMAT COMPATIBILITY
AUTOMATIC TRACK SEEK WITH VERIFICATION
ACCOMMODATES SINGLE AND DOUBLE DENSITY
FORMATS
IBM 3740 Single Density (FM)
IBM System 34 Double Density (MFM)
Non IBM Format for Increased Capacity
'. READ MODE
Single/Multiple Sector Read with Automatic Search or
Entire Track Read
Selectable 128, 256, 512 or 1024 Byte Sector Lengths
" WRITEMODE
Single/Multiple Sector Write with Automatic Sector
Search
Entire Track Write for Diskette Formatting
.. SYSTEM COMPATIBILITY
Double Buffering of Data 8 Bit Bi-Directional Bus for
Data, Control and Status
DMA or Programmed Data Transfers
All Inputs and Outputs are TIL Compatible
On-Chip Track and Sector Registers/Comprehensive
Status Information
NC
WE
~recomp
P
A,
5ALT
33
) WFNFOE
DAl4
l'
J READY
1 WD
30 J WG
5AL5
12
29
9032
10
31
TG43
5AC7
] RCLK
DIRC
EARLY
1795
1797
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
~~_R_E~_
>
DATA (8)
r---~ClK_
AO
c---- RG/~S()___--+
A1
c----- ----- --
CS
~~~-+
F
WD
0
lATE
-~
-
WE
..
179X
FLOPPY DISK
CONTROLLER
FORMATTER
f'-"
WPRT
IP
(>10K
LATE
--
K
I
N
T
E
R
F
TG43
?
A
C
E
STEP
INTRa
MR
..
READY
?
DRO
D
I
S
WFNFOE
TROO
.>
L
P
P
Y
WG
+5V
10K.~
---
+5
MR
I
N
T
E
R
A
C
E
1794
X
X
X
APPLICATIONS
T
E
R
F
STEP
1793
X
8" FLOPPY AND 51/4" MINI FLOPPY CONTROLLER
SINGLE OR DOUBLE DENSITY
CONTROLLER/ FORMATIER
U
"DAlO
1792
X
Side Selection Output
0
M
1791
X
X
Inverted Data Bus
C
RE
DAl3
FEATURES
Single Density (FM)
Double Density(MFM)
True Data Bus
INTRQ
cs
DAl2
179X-02 FAMILY CHARACTERISTICS
K
1 YDDI+12YI
40
I\)
DIRe
elK
IGNDIYSS
21
) VCCI+5VI
'----------'
+5V
=
'179113 RG
1795/7
"179317 TRUE BUS
"'179214 OPEN
.~
r
=
= SSO
PIN CONNECTIONS
DDEN
lONE SHOT
VSS
VDD
l!! Jv
+12
FD179X SYSTEM BLOCK DIAGRAM
•
173
I
Vee r--H_lT
.......---L....:(_IF_U_SE_D..:.,).JJ
+5V
X
X
PIN OUTS
PIN
NUMBER
.
PIN NAME
FUNCTION
SYMBOL
NO CONNECTION
NC
Pin 1 is internally connected to a back bias generator and
must be left open by the user.
19
MASTER RESET
MR
A logic low (50 microseconds min.) on this input resets the
device and loads HEX 03 into the command register. The Not
Ready (Status Bit 7) is reset during MR ACTIVE. When MR is
brought to a logic high a RESTORE Command is executed,
regardless of the state of the Ready Signal from the drive.
Also, HEX 01 is loaded into sector register.
20
POWER SUPPLIES
1
Vss
Ground
21
Vee
+5V ±5%
40
Voo
+12V ±5%
COMPUTER INTERFACE:
2
WRITE ENABLE
WE
A logic low on this input gates data on the DAL into the
selected register when CS is low.
3
CHIP SELECT
CS
A logic low on this input selects the chip and enables
computer communication with t~e device.
4
READ ENABLE
RE
A logic low on this input controls the placement of data from a
selected register on the DAL when CS is low.
REGISTER SELECT LINES
AO,A1
These inputs select the register to receive/transfer data on the
DAL lines under RE and WE control:
5,6
CS
A1
AO
RE
0
0
0
0
0
0
1
1
0
1
0
1
Status Reg
Track Reg
Sector Reg
Data Reg
WE
Command Reg
Track Reg
Sector Reg
Data Reg
DATA ACCESS LINES
DALO-DAL7
Eight bit Bidirectional bus used for transfer of data, control,
and status. This bus is receiver enabled by WE or transmitter
enabled by RE. Each line will drive 1 standard TTL load.
24
CLOCK
CLK
This input requires a free-running 50% duty cycle square wave
clock for internal timing reference, 2 MHz ± 1% for 8" drives,
1 MHz ± 1% for mini-floppies.
38
DATA REQUEST
DRQ
This open drain output indicates that the DR contains
assembled data in Read operations, or the DR is empty in
Write operations. This Signal is reset when serviced by the
computer through reading or loading the DR in Read or Write
operations, respectively. Use 10K pull-up resistor to + 5.
39
INTERRUPT REQUEST
INTRQ
This open drain output is set at the completion of any command and is reset when the STATUS register is read or the
command register is written to. Use 10K pull-up resistor to
+5.
7·14
FLOPPY DISK INTERFACE:
15
STEP
STEP
The step output contains a pulse for each step.
16
DIRECTION
DIRC
Direction Output is active high when stepping in, active low
when stepping out.
17
EARLY
EARLY
Indicates that the WRITE DATA pulse occuring while Early is
active (high) should be shifted early for write precom- \
18
LATE
LATE
Indicates that the write data pulse occurring while Late is
active (high) should be shifted late for write precompensation.
~~~
174
J
PIN
NUMBER
PIN NAME
22
TEST
SYMBOL
TEST
FUNCTION
This input is used for testing purposes only and should be tied \
to + 5V or left open by the user unless interfacing to voice coil I
actuated steppers.
23
HEAD LOAD TIMING
HLT
When a logic high is found on the HLT input the head is
assumed to be engaged. It is typically derived from a 1 shot
triggered by HLD.
25
READ GATE
(1791,1792,1793,1794)
RG
This output is used for synchronization of external data
separators. The output goes high after two Bytes of zeros in
single density, or 4 Bytes of either zeros or ones in double
density operation.
25
SIDE SELECT OUTPUT
(1795, 1797)
SSO
The logic level of the Side Select Output is directly controlled
by the'S' flag in Type II or III commands. When U = 1, SSO is
set to a logic 1. When U = 0, SSO is set to a logic 0. The SSO
is compared with the side information in the Sector I.D. Field.
If they do not compare Status Bit 4 (RNF) is set. The Side
Select Output is only updated at the beginning of a Type II or
III command. It is forced to a logic upon a MASTER RESET
condition.
°
26
READ CLOCK
RCLK
A nominal square-wave clock signal derived from the data
stream must be provided to this input. Phasing (I.e. RCLK
transitions) relative to RAW READ is important but polarity
(RCLK high or low) is not.
27
RAW READ
RAW READ
The data input signal directly from the drive. This input shall
be a negative pulse for each recorded flux transition.
28
HEAD LOAD
HLD
The HLD output controls the loading of the Read·Write head
against the media.
29
TRACK GREATER THAN 43 TG43
This output informs the drive that the ReadlWrite head is
positioned between tracks 44·76. This output is valid only
during Read and Write Commands.
30
WRITE GATE
WG
This output is made valid before writing is to be performed on
the diskette.
31
WRITE DATA
WD
A 200 ns (MFM) or 500 ns (FM) output pulse per flux transition.
WD contains the unique Address marks as well as data and
clock in both FM and MFM formats.
32
READY
READY
This input indicates disk readiness and is sampled for a logic
high before Read or Write commands are performed. If Ready
is low the Read or Write operation is not performed and an
interrupt is generated. Type I operations are performed
regardless of the state of Ready. The Ready input appears in
inverted format as Status Register bit 7.
33
WRITE FAULT
VFOENABLE
WFIVFOE
This is a bi·directional signal used to signify writing faults at
the drive, and to enable the external PLO data separator. When
WG = 1, Pin 33 functions as a WF input. If WF = 0, any write
command will immediately be terminated. When WG = 0, Pin
33 functions as a VFOE output. VFOE will go low during a read
operation after the head has loaded and settled (HLT = 1). On
the 179517, it will remain low until the last bit of the second
CRC byte in the ID field. VFOE will then go high until 8 bytes
(MFM) or 4 bytes (FM) before the Address Mark. It will then go
active until the last bit of the second CRC byte of the Data
Field. On the 1791/3, VFOE will remain low until the end of the
Data Field. This pin has an internal100K Ohm pull·up resistor.
34
TRACK 00
TRoo
This input informs the FD179X that the ReadlWrite head is
positioned over Track 00.
175
PIN NUMBER
"
C
.....
.....
CD
PIN NAME
INDEX PULSE
IP
This input informs the FD179X when the index hole is encountered on the diskette.
36
WRITE PROTECT
WPRT
This input is sampled whenever a Write Command is received.
A logic low terminates the command and sets the Write
Protect Status bit.
37
DOUBLE DENSITY
DDEN
This input pin selects either single or double density
operation. When DDEN = 0, double density is selected. When
ODEN = 1, single density is selected. This line must be left
open on the 179214.
~
o
N
FUNCTION
SYMBOL
35
GENERAL DESCRIPTION
The FD179X are N-Channel Silicon Gate MOS LSI
devices which perform the functions of a Floppy Disk
Formatter/Controller in a single chip implementation.
The FD179X, which can be considered the end result
of both the FD1771 and FD1781 designs, is IBM 3740
compatible in single density mode (FM) and System 34
compatible in Double Density Mode (MFM). The
FD179X contains all the features of its predecessor the
FD1771, plus the added features necessary to
read/write and format a double density diskette. These
include address mark detection, FM and MFM encode
and decode logic, window extension, and write precompensation. In order to maintain compatibility, the
FD1771, FD1781 , and FD179X designs were made as
close as possible with the computer interface, instruction set, and I/O registers being identical. Also, head
load control is identical. In each case, the actual pin
assignments vary by only a few pins from anyone to
another.
The processor interface consists of an 8-bit bi-directional bus for data, status, and control word transfers.
The FD179X is set up to operate on a multiplexed bus
with other bus-oriented devices.
The FD179X is TTL compatible on all inputs and
outputs. The outputs will drive ONE TTL load or three
LS loads. The 1793 is identical to the 1791 except the
DAL lines are TRUE for systems that utilize true data
busses.
The 1795/7 has a side select output for controlling
double sided drives, and the 1792 and 1794 are "Single
Density Only" versions of the 1791 and 1793 respectively. On these devices, DDEN must be left open.
When executing the Seek command the Data Register
holds the address of the desired Track pOSition. This
register is loaded from the DAL and gated onto the
DAL under processor control.
Track Register - This 8-bit register holds the track
number of the current Read/Write head position. It is
incremented by one every time the head is stepped in
(towards track 76) and decremented by one when the
head is stepped out (towards track 00). The contents of
the register are compared with the recorded track
number in the 10 field during disk Read, Write, and
Verify operations. The Track Register can be loaded
from or transferred to the DAL. This Register should
not be loaded when the device is busy.
Sector Register (SR) - This 8-bit register holds the address
of the desired sector pOSition. The contents of the register
are compared with the recorded sector number in the 10
field during disk Read or Write operations. The Sector
Register contents can be loaded from or transferred to the
DAL. This register should not be loaded when the device is
busy.
Command Register (CR) - This 8-bit register holds the
command presently being executed. This register should
not be loaded when the device is busy unless the new
command is a force interrupt. The command register can
be loaded from the DAL, but not read onto the DAL.
Status Register (STR) - This 8-bit register holds device
Status information. The meaning of the Status bits is a
function of the type of command previously executed. This
register can be read onto the DAL, but not loaded from the
DAL.
CRC Logic - This logiC is used to check or to generate the
16-bit CycliC Redundancy Check (CRC). The polynomial is:
G(x) = x16 + X12 + x5 + 1.
The CRC includes all information starting with the address
mark and up to the CRC characters. The CRC register is
preset to ones prior to data being shifted through the
circuit.
ArithmetiC/Logic Unit (ALU) - The ALU is a serial comparator, incrementer, and decrementer and is used for
register modification and comparisons with the disk
recorded 10 field.
Timing and Control - All computer and Floppy Disk Interface controls are generated through this logic. The internal device timing is generated from an external crystal
clock.
The FD179X has two different modes of operation according to the state of DDEN. When DDEN =
double
density (MFM) is assumed. When bDEN = 1, single
ORGANIZATION
The Floppy Disk Formatter block diagram is illustrated
on page 5. The primary sections include the parallel
processor interface and the Floppy Disk interface.
Data Shift Register - This 8-bit register assembles
serial data from the Read Data input (RAW READ)
during Read operations and transfers serial data to the
Write Data output during Write operations.
Data Register - This 8-bit register is used as a
holding register during Disk Read and Write operations.
In Disk Read operations the assembled data byte is
transferred in parallel to the Data Register from the
Data Shift Register. In Disk Write operations information is transferred in parallel from the Data
Register to the Data Shift Register.
°
176
."
C
....
~
TG43
~-
_ _C_S _ _
~-
__
WE__ _
__
AO__ _
COMPUTER
INTERFACE
CONTROL
CONTROL
PLA
CONTROL
CONTROL
(230 X 16)
DISK
INTERFACE
CONTROL
--~-
~~-AEADY
I--_....::.S.:..:;TE,--P_
DIRe
EARLY
..
1-----_
LATE
~"--
RGlSSO
ClK (2 OR 1 MHz)
---~
D5EN'
--:·NOT USED ON 179214
FD179X BLOCK DIAGRAM
density (FM) is assumed. 1792 & 1794 are single density
only.
A1 - AO
0
0
1
1
AM Detector - The address mark detector detects ID, data
and index address marks during read and write operations.
PROCESSOR INTERFACE
The interface to the processor is accomplished through the
eight Data Access Lines (DAL) and associated control
signals. The DAL are used to transfer Data, Status, and
Control words out of, or into the FD179X. The DAL are three
state buffers that are enabled as output drivers when Chip
Select (CS) and Read Enable (RE) are active (low logic state)
or act as input receivers when CS and Write Enable (WE)
are active.
0
1
0
1
READ (RE)
Status Register
Track Register
Sector Register
Data Register
WRITE (WE)
Command Register
Track Register
Sector Register
Data Reg ister
During Direct Memory Access (DMA) types of data
transfers between the Data Register of the FD179X and the
processor, the Data Request (DRO) output is used in Data
Transfer control. This signal also appears as status bit 1
during Read and Write operations.
On Disk Read operations the Data Request is activated (set
high) when an assembled serial input byte is transferred in
parallel to the Data Register. This bit is cleared when the
Data Register Is read by the processor. If the Data Register
Is read after one or more characters are lost, by having new
data transferred into the register prior to processor readout,
the Lost Data bit is set In the Status Register. The Read
operation continues until the end of sector is reached.
When transfer of data with the Floppy Disk Controller is
required by the host processor, the device address is
decoded and CS is made low. The address bits A1 and AO,
combined with the signals RE during a Read operation or
WE during a Write operation are interpreted as selecting
the following registers:
On Disk Write operations the data Request is activated
when the Data Register transfers its contents to the Data
177
a)
b)
c)
Shift Register, and requires a new data byte. It is reset
when the Data Register is loaded with new data by the
processor. If new data is not loaded at the time the next
serial byte is required by the Floppy Disk, a byte of zeroes
is written on the diskette and the Lost Data bit is set in the
Status Register.
At the completion of every command an INTRa is
generated. INTRa is reset by either reading the status
register or by loading the command register with a new
command. In addition, INTRa is generated if a Force
Interrupt command condition is met.
The 179X has two modes of operation according to the
state of DDEN (Pin 37). When DDEN = 1, single density is
selected. In either case, the CLK input (Pin 24) is at 2 MHz.
However, when interfacing with the mini-floppy, the CLK
input is set at 1 MHz for both single density and double
density.
Both HLT and HLD are True
Settling Time, if programmed, has expired
The 179X is inspecting data off the disk
If WFIVFOE is not used, leave open or tie to a 10K resistor
to +5.
GENERAL DISK WRITE OPERATION
When writing is to take place on the diskette the Write Gate
(WG) output is activated, allowing current to flow into the
Read/Write head. As a precaution to erroneous writing the
first data byte must be loaded into the Data Register in
response to a Data Request from the FD179X before the
Write Gate signal can be activated.
Writing is inhibited when the W""""-:r""ite--"'P=-=
ro:c7te-c:-it input is a logic
low, in which case any Write command is immediately
terminated, an interrupt is generated and the Write Protect
status bit is set. The Write Fault input, when activated,
signifies a writing fault condition detected in disk drive
electronics such as failure to detect write current flow
when the Write Gate is activated. On detection of this fault
the FD179X terminates the current command, and sets the
Write Fault bit (bit 5) in the Status Word. The Write Fault
input should be made inactive when the Write Gate output
becomes inactive.
For write operations, the FD179X provides Write Gate (Pin
30) and Write Data (Pin 31) outputs. Write data consists of a
series of 500 ns pulses in FM (DDEN = 1) and 200 ns
pulses in MFM (DO EN = 0). Write Data provides the unique
address marks in both formats.
Also during write, two additional signals are provided for
write precompensation. These are EARLY (Pin 17) and
LATE (Pin 18). EARLY is active true when the WD pulse
appearing on (Pin 30) is to be written EARLY. LATE is active
true when the WD pulse is to be written LATE. If both
EARLY and LATE are low when the WO pulse is present,
the WD pulse is to be written at nominal. Since write
precompensation values vary from disk manufacturer to
disk manufacturer, the actual value is determined by
several one shots or delay lines which are located external
to the FD179X. The write precompensation signals EARLY
and LATE are valid for the duration of WD in both FM and
MFM formats.
GENERAL DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 are obtainable in
either FM or MFM formats. For FM, DDEN should be
placed to logical "1." For MFM formats, DDEN should be
placed to a logical "0." Sector lengths are determined at
format time by the fourth byte in the "ID" field.
Sector Length Table*
Number of Bytes
Sector Length
in SectorJdecimal)
Field(he&
128
00
256
01
02
512
1024
03
* 1795/97 may vary - see command summary.
The number of sectors per track as far as the FD179X is
concerned can be from 1 to 255 sectors. The number of
tracks as far as the FD179X is concerned is from 0 to 255
tracks. For IBM 3740 compatibility, sector lengths are 128
bytes with 26 sectors per track. For System 34 compatibility (MFM), sector lengths are 256 bytes/sector with 26
sectors/track; or lengths of 1024 bytes/sector with 8
sectors/track. (See Sector Length Table)
For read operations in 8" double density the FD179X
requires RAW READ Data (Pin 27) signal which is a 200 ns
pulse per flux transition and a Read clock (RCLK) signal to
indicate flux transition spacings. The RCLK (Pin 26) signal
is provided by some drives but if not it may be derived
externally by Phase lock loops, one shots, or counter
techniques. In addition, a Read Gate Signal is provided as
an output (Pin 25) on 1791/92193194 which can be used to
inform phase lock loops when to acquire synchronization.
When reading from the media in FM. RG is made true when
2 bytes of zeroes are detected. The FD179X must find an
address mark within the next 10 bytes; otherwi~e RG is
reset and the search for 2 bytes of zeroes begins all over
again. If an address mark is found within 10 bytes, RG
remains true as long as the FD179X is deriving any useful
information from the data stream. Similarly for MFM, RG is
made active when 4 bytes of "RC)" or "FF" are detected. The
FD179X must find an address mark within the next 16
bytes, otherwise RG is reset and search resumes.
During read operations (WG = 0), the VFOE (Pin 33) is
provided for phase lock loop synchronization. VFOE will go
active low when:
READY
Whenever a Read or Write command (Type II or III) is
received the FD179X samples the Ready input. If this input
is logic low the command is not executed and an interrupt
Is generated. All Type I commands are performed regardless of the state of the Ready input. Also, whenever a
Type II or III command is received, the TG43 signal output
is updated.
COMMAND DESCRIPTION
The FD179X will accept eleven commands. Command
words should only be loaded in the Command Register
when the Busy status bit is off (Status bit 0). The one
exception is the Force Interrupt command. Whenever a
command is being executed, the Busy status bit is set.
When a command is completed, an interrupt is generated
and the Busy status bit is reset. The Status Register
indicates whether the completed command encountered
an error or was fault free. For ease of discussion,
commands are divided into four types. Commands and
types are summarized in Table 1.
178
TABLE 1
COMMAND SUMMARY
B. Commands for Models: 1795(f79f)
A. Commands for Models: 1791, 1792, 1793, 1794
Bits
Type Command
I
I
I
I
I
II
1/
• lIT
II/
11\
IV
Restore
Seek
Step
Step-In
SteD-out
Read Sector
Write Sector
""Read Address
Read Track
Write Track
~orce Interrupt
Bits
7
6
5
4
3
2
0
0
0
0
0
1
1
0
1
T
T
T
m
m
u
0
V
V
V
V
V
1
1
0
0
1
0
1
0
1
u
1
1
h
h
h
h
h
1
0
0
0
1
1
0
0
-,
, ,
, ,
u
,
1
1
r1
r1
r1
r1
r1
S
E
C
S
0
0
0
13
E
E
E
E
12
C
0
0
0
11
0
rO
ro
rO
rO
rO
0
ao
-'0
0
0
10
7
6
5
4
3
2
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
1
0
0
1
T
T
T
m
m
0
0
h
h
h
h
h
L
L
0
0
0
13
V
V
V
V
V
1
r1
r1
r1
r1
r1
E
u
E
U
U
U
U
11
1
1
1
1
t
E
E
12
TABLE 2. FLAG SUMMARY
FLAG SUMMARY
Command
Type
Bit
No(s)
I
0,1
I
2
V
= Track Number Verify Flag
V
V
I
3
h
= Head Load Flag
h
h
I
4
T
= Track Update Flag
T
T - 1, Update track register
1/
0
aO
II
1
C
Description
=
r1 rO
Stepping Motor Rate
See Table 3 for Rate Summary
!-
= Data Address Mark
= 0, No verify
= 1, Verify on destination track
= 1, Load head at beginning
= 0, Unload head at beginning
= 0, No update
aO
aO
= Side Compare Flag
C
C
11&111
1
U
= Update SSO
U
U
11&111
2
E
= 15 MS Delay
E
E
II
3
S
= Side Compare Flag
S
S
II
3
L
= Sector Length Flag
1, Enable side compare
= 0, Update SSO to 0
= 1, Update SSO to 1
= 0, No 15 MS delay
= 1,15 MS delay
= 0, Compare for side 0
= 1, Compare for side 1
L
L
II
4
IV
0-3
....
m
= Multiple Record Flag
Ix
10
11
12
13
13-10
= 0, FB (DAM)
= 1, F8 (deleted DAM)
= 0, Disable side compare
m
m
LSB's Sector Length in 10 Field
11
01
10
00
512
128
256
1024
256
512
1024
128
= O.
=1
= 0, Single record
= 1, Multiple records
- Interrupt Condition Flags
1 Not Ready To Ready Transition
1 Ready To Not Ready Transition
1 Index Pulse
1 Immediate Interrupt, Requires A Reset
0 Terminate With No Interrupt (INTRQ)
=
=
=
=
=
* NOTE: See Type IV Command Description for further inforr~ation.
179
0
ro
rO
ro
ro
ro
u
eo
0
0
Q
10
Head Load timing (HLT) is an input to the FD179X which is
used for the head engage time. When HLT = 1, the FD179X
assumes the head is completely engaged. The head
engage time is typically 30 to 100 ms depending on drive.
The low to high transition on HLD is typically used to fire a
one shot. The output of the one shot is then used for HLT
and supplied as an input to the FD179X.
TYPE I COMMANDS
-n
C
..".
....CD
x
6
N
The Type I Commands include the Restore, Seek, Step,
Step-In, and Step-Out commands. Each of the Type I
Commands contains a rate field (ro q), which determines
the stepping motor rate as defined in Table 3.
A 2 /As (MFM) or 4 /As (FM) pulse is provided as an output to
the drive. For every step pulse issued, the drive moves one
track location in a direction determined by the direction
output. The chip will step the drive in the same direction it
last stepped unless the command changes the direction.
HLOfI-- - - - - '
The Direction signal is active high when stepping in and
low when stepping out. The Direction signal is valid 12/As
before the first stepping pulse is generated.
~50 TO
!f----
The rates (shown in Table 3) can be applied to a StepDirection Motor through the device interface.
elK
2 MHz
0
R1 RO
TEST=1
2 MHz
1 MHz
HEAD LOAD TIMING
1 MHz
2 MHz
TEST=1
TEST=O
1 MHz
TEST=1
TEST=O
0
0
3 ms
3 ms
6 ms
6 ms
184JlS
368Jls
0
1
6 ms
6 ms
12 ms
12 ms
190Jls
380Jls
1 0
10 ms
10 ms
20 ms
20 ms
198Jls
396Jls
1
15 ms
15 ms
30 ms
30 ms
208Jls
416Jls
1
When both HLD and HLT are true, the FD179X will then
read from or write to the media. The "and" of HLD and HLT
appears as status Bit 5 in Type I status.
0
TEST=1
1
HL T (FROM ONE SHOT)
TABLE 3. STEPPING RATES
DDEN
i-I------
10omS--1
=
°
=
In summary for the Type I commands: ifh
and V
0,
HLD is reset. If h = 1 and V = 0, HLD is set at the
beginning of the command and HLT is not sampled nor is
there an internal 15 ms delay. If h
and V
1, HLD is
set near the end of the command, an internal 15 ms occurs,
and the FD179X waits for HLT to be true. If h = 1 and V =
1, HLD is set at the beginning of the command. Near the
end of the command, after all the steps have been issued,
an internal 15 ms delay occurs and the FD179X then waits
for HLT to occur.
=
After the last directional step an additional 15 milliseconds
of head settling time takes place if the Verify flag is set in
Type I commands. Note that this time doubles to 30 ms for
a 1 MHz clock. If TEST = 0, there is zero settling time.
There is also a 15 ms head settling time if the E flag is set in
any Type II or III command.
°
=
For Type II and III commands with E flag off, HLD is made
active and HLT is sampled until true. With E flag on, HLD is
made active, an internal 15 ms delay occurs and then HLT
is sampled until true.
When a Seek, Step or Restore command is executed an
optional verification of Read-Write head position can be
performed by settling bit 2 (V = 1) in the command word to
a logic 1. The verification operation begins at the end of the
15 millisecond settling time after the head is loaded against
the media. The track number from the first encountered 10
Field is compared against the contents of the Track
Register. If the track numbers compare and the 10 Field
Cyclic Redundancy Check (CRG) is correct, the verify
operation is complete and an INTRa is generated with no
errors. If there is a match but not a valid CRC, the CRC error
status bit is set (Status bit 3), and the next encountered 10
field is read from the disk for the verification operation.
RESTORE (SEEK TRACK 0)
The EllHox mllst find an 10 field with correct t@ck number
and correct CRC within 5 rOllO" l!jons., of the media;
otherwise the seek error is set"and an INTRa is generated.
If V = 0, no verification is performed.
Upon receipt of this command the Track 00 (TROO) input is
sampled. If TROO is active low indicating the Read-Write
head is positioned over track 0, the Track Register is loaded
with zeroes and an interrupt is generated. If TROO is not
active low, stepping pulses (pins 15 to 16) at a rate specified
by the q rO field are issued until the TROO input is activated.
At this time the Track Register is loaded with zeroes and an
interrupt is generated. If the TROO input does not go active
low after 255 stepping pulses, the FD179X terminates
operation, interrupts, and sets the Seek error status bit,
providing the V flag is set. A verification operation also
takes place if the V flag is set. The h bit allows the head to
be loaded at the start of command. Note that the Restore
command is executed when MR goes from an active to an
inactive state and that the DRO pin stays low.
The Head Load (HLD) output controls the movement of the
read/write head against the media. HLD is activated at the
beginning of a Type I command if the h flag is set (h = 1), at
the end of the Type I command if the verify flag (V = 1), or
upon receipt of any Type II or III command. Once HLD is
active it remains active until either a Type I command is
received with (h = and V = 0); or if the FD179X is in an
idle state (non-busy) and 15 index pulses have occurred.
This command assumes that the Track Register contains
the track number of the current position of the Read-Write
head and the Data Register contains the desired track
number. The FD179X will update the Track register and
issue stepping pulses in the appropriate direction until the
contents of the Track register are equal to the contents of
SEEK
°
180
TYPE I COMMAND FLOW
TYPE I COMMAND FLOW
the Data Register (the desired track location). A verification
operation takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An interrupt
is generated at the completion of the command. Note:
When using multiple drives, the track register must be
updated for the drive selected before seeks are issued.
flag is on, the Track Register is incremented by one. After a
delay determined by the r1 ra field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.
STEP
STEP·OUT
Upon receipt of this command, the FD179X issues one
stepping pulse to the disk drive. The stepping motor
direction is the same as in the previous step command.
After a delay determined by the r1 ra field, a verification
takes place if the V flag is on. If the U flag is on, the Track
Register is updated. The h bit allows the head to be loaded
at the start of the command. An interrupt is generated at
the completion of the command.
Upon receipt of this command, the FD179X issues one
stepping pulse in the direction towards track a. If the U flag
is on, the Track Register is decremented by one. After a
delay determined by the r1 ra field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.
STEP·IN
On the 1795/7 devices, the SSO output is not affected
during Type 1 commands, and an internal side compare
does not take place when the (V) Verify Flag is on.
EXCEPTIONS
Upon receipt of this command, the FD179X issues one
stepping pulse in the direction towards track 76. If the U
181
then located and will be either written into, or read from
depending upon the command. The F0179X must find an
10 field with a Track number, Sector number, side number,
and CRC within four revolutions of the disk; otherwise, the
Record not found status bit is set (Status bit 3) and the
command Is terminated with an interrupt.
"T1
C
.....
~
VERIFY
SEQUENCE
N
NOTE:
II! mT' = 0, THERE IS NO 1~MS DELAY
~~ = 1 AND eLK = 1 MHz, THERE IS A 30MS DELAY
TYPE I COMMAND FLOW
TYPE II COMMANDS
The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command
into the Command Register, the computer must load the
Sector Register with the desired sector number. Upon
receipt of the Type II command, the busy status Bit is set. If
the E flag = 1 (this is the normal case) HLO is made active
and HLT is sampled after a 15 msec delay. If the E flag is 0,
the head is loaded and HLT sampled with no 15 msec
delay. The 10 field and Data Field format are shown on page
13.
When an 10 field is located on the disk, the F0179X
compares the Track Number on the 10 field with the Track
Register. If there Is not a match, the next encountered 10
field is read and a comparison Is again made. If there was a
match, the Sector Number of the 10 field Is compared with
the Sector Register. If there is not a Sector match, the next
encountered 10 field is read off the disk and comparisons
again made. If the 10 field CRC is correct, the data field is
TYPE II COMMAND
Each of the Type II Commands contains an (m) flag which
determines if multiple records (sectors) are to be read or
written, depending upon the command. If m
0, a single
sector Is read or written and an Interrupt is generated at the
completion of the command. If m = 1, multiple records are
read or written with the sector register internally updated
so that an address verification can occur on the next
=
182
record. The FD179X will continue to read or write multiple
records and update the sector register in numerical
ascending sequence until the sector register exceeds the
number of sectors on the track or until the Force Interrupt
command is loaded into the Command Register, which
terminates the command and generates an interrupt.
The Type II and III commands for the 1795-97 contain a side
select flag (Bit 1). When U = 0, SSO is updated to O.
Similarly, U = 1 updates SSO to 1. The chip compares the
SSO to the ID field. If they do not compare within 5
revolutions the interrupt line is made active and the RNF
status bit is set.
For example: If the FD179X is instructed to read sector 27
and there are only 26 on the track, the sector register exceeds the number available. The FD179X will search for 5
disk revolutions, interrupt out, reset busy, and set the
record not found status bit.
The 1795/7 READ SECTOR and WRITE SECTOR commands include a 'L' flag. The 'L' flag, in conjunction with
the sector length byte of the ID Field, allows different byte
lengths to be implemented in each sector. For IBM
compatability, the 'L' flag should be set to a one.
The Type II commands for 1791-94 also contain side select
compare flags. When C = 0 (Bit 1) no side comparison is
made. When G = 1, the LSB of the side number is read off
the ID Field of the disk and compared with the contents of
the (S) flag (Bit 3). If the S flag compares with the side
number recorded in the ID field, the FD179X continues with
the ID search. If a comparison is not made within 5 index
pulses, the interrupt line is made active and the RecordNot-Found status bit is set.
Upon receipt of the Read Sector command, the head is
loaded, the Busy status bit set, and when an ID field is
encountered that has the correct track number, correct
sector number, correct side number, and correct CRC, the
data field is presented to the computer. The Data Address
READ SECTOR
READ SECTOR
SEQUENCE
INTRa, RESET BUSY
SET CRe ERROR
TYPE II COMMAND
TYPE II COMMAND
183
STATUS
BITS
WRITE SECTOR
SEQUENCE
Deleted Data Mark
Data Mark
o
WRITE SECTOR
Upon receipt of the Write Sector command, the head is
loaded (HLD active) and the Busy status bit is set. When an
10 field is encountered that has the correct track number,
correct sector number, correct side number, and correct
CRC, a ORO is generated. The FD179X counts off 11 bytes
in single density and 22 bytes in double density from the
CRC field and the Write Gate (WG) output is made active if
the ORO is serviced (Le., the DR has been loaded by the
computer). If ORO has not been serviced, the command is
terminated and the Lost Data status bit is set. If the ORO
has been serviced, the WG is made active and six bytes of
zeroes in single density and 12 bytes in double density are
then written on the disk. At this time the Data Address
Mark is then written on the disk as determined by the aO
field of the command as shown below:
aO
Data Address Mark (Bit 0)
1
Deleted Data Mark
Data Mark
o
The FD179X then writes the data field and generates ORa's
to the computer. If the ORO is not serviced in time for
continuous writing the Lost Data Status Bit is set and a
byte of zeroes is written on the disk. The command is not
terminated. After the last data byte has been written on the
disk, the two-byte CRC is computed internally and written
on the disk followed by one byte of logic ones in FM or in
MFM. The WG output is then deactivated. For a 2 MHz
clock the INTRO will set 8 to 12 ~sec after the last CRC byte
is written. For partial sector writing, the proper method is to
write the data and fill the balance with zeroes. By letting the
chip fill the zeroes, errors may be masked by the lost data
status and improper CRC Bytes.
NO
TYPE III COMMANDS
TYPE II COMMAND
Mark of the data field must be found within 30 bytes in
single density and 43 bytes in double density of the last 10
field CRC byte; if not, the 10 field is searched for and
verified again followed by the Data Address Mark search. If
after 5 revolutions the DAM cannot be found, the Record
Not Found status bit is set and the operation is terminated.
When the first character or byte of the data field has been
shifted through the DSR, it is transferred to the DR, and
ORO is generated. When the next byte is accumulated in
the DSR, it is transferred to the DR and another ORO is
generated. If the Computer has not read the previous
contents of the DR before a new character is transferred
that character is lost and the Lost Data Status bit is set.
This sequence continues until the complete data field has
been inputted to the computer. If there is a CRC error at the
end of the data field, the CRC error status bit is set, and the
command is terminated (even if it is a multiple record
command).
At the end of the Read operation, the type of Data Address
Mark encountered in the data field is recorded in the Status
Register (Bit 5) as shown:
READ ADDRESS
Upon receipt of the Read Address command, the head
is loaded and the Busy Status Bit is set. The next
encountered 10 field is then read in from the disk, and
the six data bytes of the 10 field are assembled and
transferred to the DR, and a ORO is generated for each
byte. The six bytes of the 10 field are shown below:
TRACK
ADDR
SIDE
NUMBER
SECTOR
ADDRESS
SECTOR
LENGTH
1
2
3
4
CRC CRC
1
2
5
6
Although the CRC characters are transferred to the
computer, the FD179X checks for validity and the CRC
error status bit is set if there is a CRC error. The Track
Address of the 10 field is written into the sector
register so that a comparison can be made by the
user. At the end of the operation an interrupt is
generated and the Busy Status is reset.
184
READ TRACK
is not activated during the command; no CRC checking is
performed; gap information is included in the data stream;
the internal side compare is not performed; and the address mark detector is on for the duration of the command.
Because the A.M. detector is always on, write splices or
noise may cause the chip to look for an A.M. If an address
mark does not appear on schedule the Lost Data status flag
is set.
Upon receipt of the READ track command, the head is
loaded, and the Busy Status bit is set. Reading starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse. All Gap, Header, and
data bytes are assembled and transferred to the data
register and ORO's are generated for each byte. The accumulation of bytes is synchronized to each address mark
encountered. An interrupt is generated at the completion of
the command.
This command has several characteristics which make it
suitable for diagnostic purposes. They are: the Read Gate
The 10 A.M., 10 field, 10 CRC bytes, DAM, Data, and Data
CRC Bytes for each sector will be correct. The Gap Bytes
may be read incorrectly during write-splice time because of
synchronization.
TYPE III COMMAND WRITE TRACK
TYPE III COMMAND WRITE TRACK
185
"'TI
C
~
~
o
N
CONTROL BYTES FOR INITIALIZATION
."
C
......
DATA PATTERN
IN DR (HEX)
~
CD
~
o
N
00 thru F4
F5
F6
F7
F8 thru FB
FC
FD
FE
FF
FD179X INTERPRETATION
IN FM (DDEN
1)
=
Write 00 thru F4 with ClK = FF
FD1791/31NTERPRETATION
IN MFM (DO'E"N
0)
=
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write F8 thru FB, Clk = C7, Preset CRC
Write FC with Clk
D7
Write FD with Clk
FF
Write FE, Clk
C7, Preset CRC
Write FF with Clk
FF
=
=
=
=
Write 00 thru F4, in MFM
Write A1 * in MFM, Preset CRC
Write C2* * in MFM
Generate 2 CRC bytes
Write F8 thru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM
* * Missing clock transition between bits 3 & 4
* Missing clock transition between bits 4 and 5
sure Type I status in the status register. This command can
be loaded into the command register at any time. If there is
a current command under execution (busy status bit set)
the command will be terminated and the busy status bit
reset.
WRITE TRACK FORMATIING THE DISK
(Refer to section on Type III commands for flow diagrams.)
Formatting the disk is a relatively simple task when
operating programmed 110 or when operating under DMA
with a large amount of memory. Data and gap information
must be provided at the computer interface. Formatting the
disk is accomplished by positioning the RJW head over the
desired track number and issuing the Write Track command.
The lower four bits of the command determine the conditional interrupt as follows:
10
11
12
13
Upon receipt of the Write Track command, the head is
loaded and the Busy Status bit is set. Writing starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse, at which time the
interrupt is activated. The Data Request is activated immediately upon receiving the command, but writing will not
start until after the first byte has been loaded into the Data
Register. If the DR has not been loaded by the time the
index pulse is encountered the operation is terminated
making the device Not Busy, the Lost Data Status Bit is set,
and the Interrupt is activated. If a byte is not present in the
DR when needed, a byte of zeroes is substituted.
=
=
=
=
Not-Ready to Ready Transition
Ready to Not-Ready Transition
Every Index Pulse
Immediate Interrupt
The conditional interrupt is enabled when the corresponding bit positions of the command (13 - 10) are set to
a 1. Then, when the condition for interrupt is met, the INTRQ line will go high signifying that the condition specified
has occurred. If 13 - 10 are all set to zero (HEX DO), no interrupt will occur but any command presently under
execution will be immediately terminated. When using the
immediate interrupt condition (13 = 1) an interrupt will be
immediately generated and the current command terminated. Reading the status or writing to the command
register will not automatically clear the interrupt. The HEX
DO is the only command that will enable the immediate
interrupt (HEX 08) to clear on a subsequent load command
register or read status register operation. Follow a HEX 08
with DO command.
This sequence continues from one index mark to the next
index mark. Normally, whatever data pattern appears in the
data register is written on the disk with a normal clock
pattern. However, if the FD179X detects a data pattern of
F5 thru FE in the data register, this is interpreted as data
address marks with missing clocks or CRC generation.
Wait 8 micro sec (double density) or 16 micro sec (single
density before issuing a new command after issuing a
forced interrupt (times double when clock = 1 MHz).
Loading a new command sooner than this will nullify the
forced interrupt.
The CRC generator is initialized when any data byte from
F8 to FE is about to be transferred from the DR to the DSR
in FM or by receipt of F5 in MFM. An F7 pattern will
generate two CRC characters in FM or MFM. As a consequence, the patterns F5 thru FE must not appear in the
gaps, data fields, or 10 fields. Also, CRC's must be
generated by an F7 pattern.
Forced interrupt stops any command at the end of an internal micro-instruction and generates INTRQ when the
specified condition is met. Forced interrupt will wait until
ALU operations in progress are complete (CRC
calculations, compares, etc.).
Disks may be formatted in IBM 3740 or System 34 formats
with sector lengths of 128, 256, 512, or 1024 bytes.
More· than one condition may be set at a time. If for
example, the READY TO NOT-READY condition (11 = 1)
and the Every Index Pulse (12 = 1) are both set, the
resultant command would be HEX "DA". The "OR" function is performed so that either a READY TO NOT- READY
or the next Index Pulse will cause an interrupt condition.
TYPE IV COMMANDS
The Forced Interrupt command is generally used to terminate a multiple sector read or write command or to in-
-:86
.1__________________________________________________________
READ TRACK
SEQUENCE
"C
...&.
.....
CD
X
6
N
INTRO
RESET BUSY
SET INTRO
RESET BUSY
YES
DELAY ISMS'
SET
DRO
READ
ADDRESS
." TEST= ~, NO DELAY
If TEST=1 and elK=1 MHZ, 30 MS DELAY
TYPE III COMMAND
Read Track!Address
187
STATUS REGISTER
Upon receipt of any command, except the Force Interrupt
command, the Busy Status bit is set and the rest of the
status bits are updated or cleared for the new command. If
the Force Interrupt Command is received when there is a
current command under execution, the Busy status bit is
reset, and the rest of the status bits are unchanged. If the
Force Interrupt command is received when there is not a
current command under execution, the Busy Status bit is
reset and the rest of the status bits are updated or cleared.
In this case, Status reflects the Type I commands.
READ ADDRESS
SEQUENCE
."
C
.....
-...
CD
~
o
N
RESET BUSY
SET INTRQ
SET RNF
The user has the option of reading the status register
through program control or using the ORO line with OMA or
interrupt methods. When the Data register is read the ORO
bit in the status register and the ORO line are automatically
reset. A write to the Data register also causes both ORa's
to reset.
The busy bit in the status may be monitored with a user
program to determine when a command is complete, in
lieu of using the INTRa line. When using the INTRa, a busy
status check is not recommended because a read of the
status register to determine the condition of busy will reset
the INTRa line.
The format of the Status Register is shown below:
TRANSFER
BYTE TO DR
o
7
S7
SO
Status varies according to the type of command executed
as shown In Table 4.
Because of internal sync cycles, certain time delays must
be observed when operating under programmed 1/0. They
are: (times double when clock = 1 MHz)
Operation
Write to
Command Reg.
Write to
Command Reg.
Next Operation
Read Busy Bit
(Status Bit 0)
Read Status
Bits 1-7
Delay Req'd.
I
MFM
FM
I
12J..1s
28J..1s
Wr!teAny
Register
Read From Oitt.
Register
IBM 3740 FORMAT -
I
6J..1s
I
14J..1s
I
~
YES
I
I
I
~-
0
T---······
I
-
0
I
128 BYTES/SECTOR
Shown below is the IBM single-density format with 128
bytes/sector. In order to format a diskette, the user must
issue the Write Track command, and load the data register
with the following values. For every byte to be written, there
is one Data Request.
TYPE III COMMAND
Read Track/Address
188
IBM 3740 FORMAT -
128 BYTES/SECTOR
IBM SYSTEM 34 FORMAT· 256 BYTES/SECTOR
Shown below is the IBM single·density format with 128
bytes/sector. In order to format a diskette, the user must
issue the Write Track command, and load the data register
with the following values. For every byte to be written, there
is one Data Request.
NUMBER
OF BYTES
*
40
6
1
26
6
1
1
1
1
1
1
11
6
1
128
1
27
247**
HEX VALUE OF
BYTE WRITIEN
Shown below is the IBM dual·density format with 256
bytes/sector. In order to format a diskette the user must
issue the Write Track command and load the data register
with the following values. For every byte to be written, there
is one data request.
.
NUMBER
OF BYTES
80
12
3
1
*50
12
3
1
1
1
1
1
1
22
12
3
1
256
1
54
598**
FF (or 00)'
00
FC (I ndex Mark)
FF (or 00)'
00
FE (ID Address Mark)
Track Number
Side Number (00 or01)
Sector Number(1 thru 1A)
00 (Sector Length)
F7 (2 CRC's written)
FF (or 00)'
00
FB (Data Address Mark)
Data (IBM uses E5)
F7 (2 CRC's written)
FF(orOO)'
FF (or 00)'
*Write bracketed field 26 times
**Continue writing until FD179X interrupts out.
Approx. 247 bytes.
1·0ptional '00' on 1795/7 only.
HEX VALUE OF
BYTE WRITIEN
4E
00
F6 (Writes C2)
FC (Index Mark)
4E
00
F5 (Writes A 1)
FE (ID Address Mark)
Track Number(O thru 4C)
Side Number(O or 1)
Sector Number(1 thru 1A)
01 (Sector Length)
F7 (2 CRCs written)
4E
00
F5 (Writes A 1)
FB (Data Address Mark)
DATA
F7 (2 CRCs written)
4E
4E
*Write bracketed field 26 times
**Continue writing until FD179X interrupts out.
Approx. 598 bytes.
PHY.'C~I,---_ _ _ __
:mm~~"
f--l
IN MFM ONLY, lOAM AND DATA AM
ARE PRECEDED BY THREE BYTES OF
AI WITH CLOCK TRANSlTIONBEfWEEN
BITS 4 AND 5 MISSINQ
'"MISSINQCLOCKTAANSITION
aETWEENBITS3AN04
--32BYTe8~O
\_
-
IBM TRACK FORMAl
189
~'~=E'J:~~.O~:T~~~E~~OATE
3
"TI
C
.....
......
CD
~
o
N
1. NON·IBM FORMATS
"T1
C
-'"
Variations in the IBM formats are possible to a limited
extent if the following requirements are met:
~
1) Sector size must be 128, 256, 512 or 1024 bytes.
~
2) Gap 2 cannot be varied from the IBM format.
~
3) 3 bytes of A 1 must be used in MFM.
In addition, the Index Address Mark is not required for
operation by the FD179X. Gap 1, 3, and 4 lengths can be as
short as 2 bytes for FD179X operation, however PLL lock up
time, motor speed variation, write-splice area, etc. will add
more bytes to each gap to achieve proper operation. It is
recommended that the IBM format be used for highest
system reliability.
FM
MFM
Gap I
16 bytes FF
32 bytes4E
Gap II
11 bytes FF
22 bytes4E
*
*
6 bytes 00
12 bytes 00
3 bytes A1
Gap 111**
10 bytes FF
4 bytes 00
24 bytes 4E
8 bytes 00
3 bytes A1
16 bytes FF
16 bytes4E
RE
---1----,
1i)Ali
-----+----1
NOTE
1
CS MAY BE PERMANENTLY TIED lOW IF DESIRED
"TIME DOUBLES WHEN CLOCK
t SERVICE (WORST CASEl
'FM 275 uS
'MFM
135 uS
ORO RISING EOGE: INDICATes THAT THE DATA REGISTER HAS ASSEMBLED
DATA
Gap IV
ORO FALLING EDGE: INDICATES THAT THE DATA REGISTER WAS READ
INTRQ RISING EOGE: OCCURS AT END OF COMMAND
INTRa FALLING EDGE: INDICATES THAT THE STATUS REGISTER WAS READ.
* Byte counts must be exact.
* * Byte counts are minimum, except exactly 3 bytes of A 1
must be written.
READ ENABLE TIMING
TIMING CHARACTERISTICS
TA = OOC to 70°C, VDD = + 12V ± .6V, Vss = OV, Vee =+5V ± .25V
READ ENABLE TIMING (See Note 6, Page 21)
SYMBOL
TSET
THLD
TRE
TORR
TIRR
TDACC
TDOH
CHARACTERISTIC
Setup ADDR & CS to R~
Hold ADDR & CS from RE
RE Pulse Width
ORO Reset from RE
INTRa Reset from RE
Data Access from RE
Data Hold From RE
MIN.
TYP.
MAX.
UNITS
400
500
500
3000
350
150
nsec
nsec
nsec
nsec
nsec
nsec
nsec
See Note 5
CL = 50 pf
CL = 50 pf
TYP.
MAX.
UNITS
CONDITIONS
50
10
400
50
CONDITIONS
CL = 50 pf
WRITE ENABLE TIMING (See Note 6, Page 21)
SYMBOL
TSET
THLD
TWE
TORR
TIRR
TDS
TDH
CHARACTERISTIC
Setup ADDR & CS to WE
Hold ADDR & CS from WE
WE Pulse Width
ORa Reset from WE
INTRa Reset from WE
Data Setup to WE
Data Hold from WE
MIN.
50
10
350
400
500
250
70
190
500
3000
,nsec
nsec
nsec
nsec
nsec
nsec
nsec
See Note 5
\----
--""I
..
'PW-..-j ~
RAW READ
-1
RCLK
LJ
U
I==TX?--J
TXI
~
I
I
1---T8 ~--+
I--~··
--Te
---- Tb
.--1
---1
------
NOMINAL
DISKETTE
8"
8"
5"
5"
NOTE 1 CS MAY BE PERMANENTLY TIED LOW IF DESIRED
2 WHEN WRITING DATA INTO SECTOR TRACK OR DATA
REGISTER USER CANNOT READ THIS REGISTER UNTil
AT lEAST 4 ~SEC IN MFM AFTER THE RISING EDGE OF WE
WHEN WRITING INTO THE COMMAND REGISTER STATUS
t SERVICE (WORST CASEI
IS NOT VALID UNTIL SOME 28 p.SEC IN FM. 14 ,uSEe IN MFM
'FM - 235 uS
lATER. THESE TIMES ARE DOUBLED WHEN ClK
1 MHz
'MFM
11 ~us
'TIME DOUBLES WHEN CLOCK
1MHz
MODE
MFM
FM
MFM
FM
DDEN
0
1
0
1
elK
2 MHz
2 MHz
1 MHz
1 MHz
T.
1 JJ.S
2 JJ.S
2JJ.s
4 JJ.S
Tb
1 JJ.S
2JJ.s
2JJ.s
4 JJ.S
T,
2 JJ.S
4JJ.s
4 JJ.S
8 JJ.S
INPUT DATA TIMING
ORO RISING EDGE: INDICATES THAT THE DATA REGISTER IS EMPTY
ORO FALLING EDGE: INDICATES THAT THE DATA REGISTER IS LOADED
INTRa RISING EDGE: INDICATE THE END OF A COMMAND
INTRQ FALLING EDGE: INDICATES THAT THE COMMAND REGISTER
IS WAITTEN TO
WRITE ENABLE TIMING
INPUT DATA TIMING:
SYMBOL
CHARACTERISTIC
MIN.
TYP.
MAX.
UNITS
CONDITIONS
Tpw
Raw Read Pulse Width
100
200
nsec
See Note 1
tbc
Raw Read Cycle Time
1500
2000
nsec
1800 ns @ 70°C
Tc
RCLK Cycle Time
1500
2000
nsec
1800 ns @ 70°C
TX1
RCLK hold to Raw Read
40
nsec
See Note 1
Raw Read hold to RCLK
40
nsec
See Note 1
TX2
WRITE DATA TIMING: (All TIMES DOUBLE WHEN elK = 1 MHz) (See Note 6, Page 21)
SYMBOL
CHARACTERISTICS
Twp
Write Data Pulse Width
Twg
Write Gate to Write Data
Tbc
Ts
Th
Twf
Write data cycle Time
Early (Late) to Write Data
Early (Late) From
Write Data
Write Gate off from WD
Twdl
WD Valid to Clk
Twd2
WD Valid after CLK
MIN.
TYP.
MAX.
UNITS
CONDITIONS
500
200
2
1
2,3, or 4
650
350
nsec
nsec
J,Lsec
J,Lsec
J,Lsec
nsec
nsec
FM
MFM
FM
MFM
±CLK Error
MFM
MFM
J,Lsec
J,Lsec
FM
MFM
125
125
2
1
100
50
100
30
191
nsec
nsec
nsec
nsec
CLK=1
CLK=2
CLK=1
CLK=2
MHZ
MHZ
MHZ
MHZ
."
C
.....
.....
~
o
~
r---250NS--------:)Io~1
ClK
(2MHZ)
DDEN=1
WD
L
--,L-____
I
L
~
_~~~
Twdl - ,
Iw&]
1~
r--
ClK
125
WD
)lor
125----1
L
__
"
"
(2MHZ)
- - ,....._ _ _ _ _-...1
(DDEN= 0)
1
l
Twd2
----.F0Wj~~ I ~
Twdl
-----1 I
~
Twd2
WD MUST HAVE RISING EDGE IN FIRST SHADED AREA AND TRAiliNG
EDGE IN SECOND SHADED AREA,
WRITE DATNCLOCK RELATIONSHIP
WRITE DATA TIMING
MISCELLANEOUS TIMING: (TImes Double When Clock
SYMBOL
TCD1
TCD2
TSTP
TDIR
TMR
TIP
TWF
CHARACTERISTIC
Clock Duty (low)
Clock Duty (high)
Step Pulse Output
Dir Setup to Step
Master Reset Pulse Width
Index Pulse Width
Write Fault Pulse Width
= 1 MHz)
(See Note 6, Page 21)
MIN.
TYP.
MAX.
230
200
2or4
250
250
20000
20000
12
50
10
10
192
UNITS
CONDITIONS
nsec
nsec
ILsec
ILsec
ILsec
ILsec
ILsec
See Note 5
±CLKERROR
See Note 5
1P5-~
J
I
I
I-:---
NOTES:
1. Pulse width on RAW READ (Pin 27) is normally
100-300 ns. However, pulse may be any width if
pulse is entirely within window. If pulse occurs in both
windows, then pulse width must be less than 300 ns
for MFM at CLK = 2 MHz and 600 ns for FM at 2
MHz. Times double for 1 MHz.
2. A PPL Data Separator is recommended for 8" MFM.
3. tbc should be 2 p.,s, nominal in MFM and 4 p.,s nominal
in FM. Times double when CLK = 1 MHz.
4. RCLK may be high or low during RAW READ (Polarity
is unimportant).
5. Times double when clock = 1 MHz.
Vlt-:
TIP _ _
WF}-~
J
I
VIH
I-TwF--!
MR~
j
I
I
1-----
TMR
VIH
-I
f-Tcyc-j
LJL
-':t-
6. Output timing readings are at VOL
TCD2
-+-
R1RO'
, STEP IN
~g~ - '
~
YOH
=
Jh
1 1 . - .-
-
-
-
I_
~
11--~t-----lL
TOIR _/TSTPI ___ ---ITSTP
STEP
= O.8v and
2.0v.
1__ --
TOIR --ITSTP
MISCELLANEOUS TIMING
"FROM STEP RATE TABLE
Table 4. STATUS REGISTER SUMMARY
BIT
S7
S6
S5
S4
S3
ALL TYPE I
READ
COMMANDS
ADDRESS
NOT READY
NOT READY
WRITE
0
PROTECT
HEAD LOADED
0
SEEK ERROR RNF
READ
SECTOR
NOT READY
0
READ
TRACK
NOT READY
0
WRITE
SECTOR
NOT READY
WRITE
PROTECT
WRITE FAULT
WRITE
TRACK
NOT READY
WRITE
PROTECT
WRITE FAULT
RECORD TYPE
RNF
0
0
0
LOST DATA
LOST DATA
0
LOST DATA
ORO
BUSY
ORO
BUSY
ORO
BUSY
CRC ERROR
S2
CRC ERROR
TRACK 0
LOST DATA
CRC ERROR
LOST DATA
S1
SO
INDEX PULSE
BUSY
ORO
BUSY
ORO
BUSY
RNF
CRC ERROR
0
STATUS FOR TYPE I COMMANDS
BIT NAME
MEANING
S7 NOT READY
This bit when set indicates the drive is not ready. When reset it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and logically 'ored' with MR.
S6 PROTECTED
When set, indicates Write Protect is activated. This bit is an inverted copy of WRPT
input.
S5 HEAD LOADED
When set, it indicates the head is loaded and engaged. This bit is a logical "and" of
HLD and HLT signals.
S4 SEEK ERROR
S3 CRC ERROR
S2 TRACK 00
When set, the desired track was not verified. This bit is reset to 0 when updated.
CRC encountered in 10 field.
When set, indicates Read/Write head is positioned to Track O. This bit is an inverted
copy of the TRrn:5 input.
S1 INDEX
~hen
SO BUSY
-
set, indicates index mark detected from drive. This bit is an inverted copy of the
IP input.
When set command is in progress. When reset no command is in progress.
193
-n
C
~
.....
CD
~
0
I\)
."
C
.....
......
CO
~
o
N
STATUS FOR TYPE II AND III COMMANDS
BIT NAME
MEANING
S7 NOT READY
This bit when set indicates the drive is not ready. When reset, it indicates that the drive
is ready. This bit is an inverted copy of the Ready input and 'ored' with MR. The Type II
and III Commands will not execute unless the drive is ready.
S6 WRITE PROTECT On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a
Write Protect. This bit is reset when updated.
S5 RECORD TYPE/ On Read Record: It indicates the record-type code from data field address mark.
WRITE FAULT
1 Deleted Data Mark. 0 Data Mark. On any Write: It indicates a Write Fault. This bit
is reset when updated.
S4 RECORD NOT
When set, it indicates that the desired track, sector, or side were not found. This bit is
FOUND (RNF)
reset when updated.
S3 CRC ERROR
If S4 is set, an error is found in one or more ID fields; otherwise it indicates error in
data field. This bit is reset when updated.
S2 LOST DATA
When set, it indicates the computer did not respond to DRQ in one byte time. This bit is
reset to zero when updated.
S1 DATA REQUEST This bit is a copy of the DRQ output. When set, it indicates the DR is full on a Read
Operation or the DR is empty on a Write operation. This bit is reset to zero when updated.
SO BUSY
When set, command is under execution. When reset, no command is under execution.
=
=
ELECTRICAL CHARACTERISTICS
=
CIN & COUT
15 pF max with all pins grounded except
one under test.
Operating temperature = O°C to 70°C
Storage temperature = - 55°C to + 125°C
Absolute Maximum Ratings
Voo with repect to Vss (ground): + 15 to - 0.3V
Voltage to any input with respect to Vss = + 15 to - 0.3V
Icc = 60 MA (35 MA nominal)
100 = 15 MA (10 MA nominal)
OPERATING CHARACTERISTICS (DC)
TA
= O°C to 70°C, Voo = + 12V ±
SYMBOL
IlL
10L
VIH
VIL
VOH
VOL
Po
.6V, Vss
= OV, Vee = + 5V ±
CHARACTERISTIC
Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Dissipation
.25V
MIN.
MAX.
UNITS
10
10
fAA
fAA
V
V
V
V
W
2.6
0.8
2.8
0.45
0.6
CONDITIONS
VIN
VOUT
10
10
= Voo**
= Voo
= -100fAA
= 1.6mA*
* 1792 and 1794 10 = 1.0 mA
**Leakage conditions are for input pins without internal pull-up resistors. Pins 22,23,33,36, and 37 have pull-up resistors.
See Tech Memo #115 for testing procedures.
See page 725 for ordering information.
194
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
'"T1
FD179X Application Notes
INTRODUCTION
SYSTEM DESIGN
Over the past several years, the Floppy Disk Drive has
become the most popular on-line storage device for
mini and microcomputer systems. Its fast access time,
reliability and low cost-per-bit ratio enables the Floppy
Disk Drive to be the solution in mass storage for microprocessor systems. The drive interface to the Host
system is standardized, allowing the OEM to substitute
one drive for another with minimum hardware/ software
modifications.
The first consideration in Floppy Disk Design is to determine which type of drive to use. The choice ranges
from single-density single sided mini-floppy to the 8/1
double-density double-sided drive. Figure 2 illustrates
the various drive and data capacities associated with
each type. Although the 8/1 double-density drive offers
twice as much storage, a more complex data separator
and the addition of Write Precompensation circuits are
mandatory for reliable data transfers. Whether to go
with 8/1 double-density or not is dependent upon PC
board space and the additional circuitry needed to accurately recover data with extreme bit shifts. The byte
transfer time defines the nominal time required to
transfer one byte of data from the drive. If the CPU
used cannot service a byte in this time, then a DMA
scheme will probably be required. The 179X also needs
a few microseconds for overhead, which is subtracted
from the transfer time. Figure 3 shows the actual service times that the CPU must provide on a byte-by-byte
basis. If these times are not met, bytes of data will be
lost during a read or write operation. For each byte
transferred, the 179X generates a ORO (Data Request) signal on Pin 38. A bit is provided in the status
register which is also set upon receipt of a byte from
the Disk. The user has the option of reading the status
register through program control or using the ORO Line
with DMA or interrupt schemes. When the data register
is read, both the status register ORO bit and the ORO
Line are automatically reset. The next full byte will
again set the ORO and the process continues until the
sector(s) are read. The Write operation works exactly
the same way, except a WRITE to the Data Register
causes a reset of both ORa's.
Since Floppy Disk Data is stored and retrieved as a
self-clocking serial data stream, some means of separating the clock from the data and assembling this
data in parallel form must be accomplished. Data is
stored on individual Tracks of the media, requiring control of a stepper motor to move the Read/Write head
to a predetermined Track. Byte sychronization must
also be accomplished to insure that the parallel data
is properly assembled. After all the design considerations are met, the final controller can consist of 40 or
more TTL packages.
To alleviate the burden of Floppy Disk Controller design, Western Digital has developed a Family of LSI
Floppy Disk controller devices. Through its own set of
macro commands, the FD179X Controller Family will
perform all the functions necessary to read and write
data to the drive. Both the 8/1 standard and 5%/1 minil:loppy are supported with single or double density recording techniques. The FD179X is compatible with
the IBM 3740 (FM) data format, or the System 34
(MFM) standards. Provisions for non-standard formats
and variable sector lengths have been included to provide more storage capability per track. Requiring standard +5, +12 power supplies the FD179X is available
in a standard 40 pin dual-in-line package.
RECORDING FORMATS
The FD179X Family consists of 6 devices. The
differences between these devices is summarized in
Figure 1. The 1792 and 1794 are "single density only"
devices, with the Double Density Enable pin (DDEN)
left open by the user. Both True and inverted Data bus
devices are available. Since the 179X can only drive
one TIL Load, a true data bus system may use the
1791 with external inverting buffers to arrive at a true
bus scheme. The 1795 and 1797 are identical to the
1791 and 1793, except a side select output has been
added that is controlled through the Command Register.
The FD179X accepts data from the disk in a Frequency-Modulated (FM) or Modified-Frequency-Modulated (MFM) Format. Shown in Figures 4A and 4B are
both these Formats when writing a Hexidecimal byte
of '02'. In the FM mode, the 8 bits of data are broken
up into "bit cells." Each bit cell begins with a clock
pulse and the center of the bit cell defines the data. If
the data bit = 0, no pulse is written; if the data = 1,
a pulse is written in the center of the cell. For the 8/1
drive, each clock is written 4 microseconds apart.
195
C
..;L
.......
co
><
The Ao, A1, Lines used for register selections can be
configured at the CPU in a variety of ways. These lines
may actually tie to CPU address lines, in which case
the 179X will be memory-mapped and addressed like
RAM. They may also be used under Program Control
by tying to a port device such as the 8255, 6820, etc.
As a diagnostic tool when checking out the CPU interface, the Track and Sector registers should respond
like "RAM" when the 179X is idle (Busy = INTRa =
0).
Because of internal synchronization cycles, certain
time delays must be introduced when operating under
Programmed I/O. The worst case delays are:
In the MFM mode, clocks are decoded into the data
stream. The byte is again broken up into bit cells, with
the data bit written in the center of the bit cell if data
= 1. Clocks are only written if both surrounding data
bits are zero. Figure 4B shows that this occurs only
once between Bit cell 4 and 5. Using this encoding
scheme, pulses can occur 2, 3 or 4 microseconds
apart. The bit cell time is now 2 microseconds; twice
as much data can be recorded without increasing the
Frequency rate due to this encoding scheme.
The 179X was designed to be compatible with the IBM
3740 (FM) and System 34 (MFM) Formats. Although
most users do not have a need for data exchange with
IBM mainframes, taking advantage of these well studied formats will insure a high degree of system
performance. The 179X will allow a change in gap
fields and sector lengths to increase usable storage
capacity, but variations away from these standards is
not recommended. Both IBM standards are soft-sector
format. Because of the wide variation in address marks,
the 179X can only support soft-sectored media. Hard
sectored diskettes have continued to lose popularity,
mainly due to the unavailability of a standard and the
limitation of sector lengths imposed by the physical
sector holes in the diskette.
OPERATION
NEXT
OPERATION ---WRITE TO
READ STATUS
COMMAND REG REGISTER ---WRITE TO
READ FROM A
!ANY REGISTER DIFFERENT REG
_._---
DELAY REa'D
--~-~-----
MFM = 14jLs*
FM = 28jLs.
NO DELAY
---~-----
Other CPU interface lines are ClK, MR and DDEN.
The ClK line should be 2M Hz (8" drive) or 1MHz (5%"
drive) with a 50% duty cycle. Accuracy should be ±1%
(crystal source) since all internal timing, including stepping rates, are based upon this clock.
The MR or Master Reset Line should be strobed a
minimum of 50 microseconds upon each power-on
condition. This line clears and initializes all internal registers and issues a restore command (Hex '03') on the
rising edge. A quicker stepping rate can be written to
the command register after a MR, in which case the
remaining steps will occur at the faster programmed
rate. The 179X will issue a maximum of 255 stepping
pulses in an attempt to expect the TROO line to go
active low. This line should be connected to the drive's
TROO sensor.
The DDEN line causes selection of either single density (DDEN = 1) or double density operation. DDEN
should not be switched during a read or write operation.
The Interface of the 179X to the CPU consists of an
8-bit Bi-directional bus, read/write controls and optional
interrupt lines. By selecting the device via the CHIP
SELECT Line, each of the five internal registers can
be accessed.
Shown below are the registers and their addresses:
PIN 4
RE=d
STATUS REG
TRACK REG
SECTOR REG
DATA REG
H1-Z
~--------~--
*NOTE: Times Double when ClK = 1MHz (5%" drive)
PROCESSOR INTERFACE
PIN 3 PIN 6 PIN 5
CS
A1
Ao
0
0
0
1
0
0
1
0
0
1
1
0
1
X
X
- ..
PIN 2
WE=A5
COMMAND
REG
TRACK REG
SECTOR REG
DATA REG
H1-Z
Each time a command is issued to the 179X, the Busy
bit is set and the INTRQ (Interrupt Request) Line is
reset. The user has the option of checking the busy bit
or use the INTRa Line to denote command completion. The Busy bit will be reset whenever the 179X is
idle and awaiting a new command. The INTRQ Line,
once set, can only be reset by a READ of the status
register or issuing a new command. The MR (Master
Reset) Line does not affect INTRa.
'196
FLOPPY DISK INTERFACE
The Floppy Disk Interface can be divided into three
sections: Motor Control, Write Signals and Read Signals. All of these lines are capable of driving one TTL
load and not compatible for direct connection to the
drive. Most drives require an open-collector TTL interface with high current drive capability. This must be
done on all outputs from the 179X. Inputs to the 179X
may be buffered or tied to the Drives outputs, providing
the appropriate resistor termination networks are used.
Undershoot should not exceed -0.3 volts, while integrity of V1H and VOH levels should be kept within spec.
With the 8" drive, Precompensation may be specified
from TRACK 43 on, or in most cases, all TRACKS. If
the recommended Precompensation is not specified,
check with the manufacturer for the proper configuration required.
The amount of Precompensation time also varies. A
typical value will usually be specified from 100-300ns.
Regardless of the parameters used, Write Precompensation must be done external to the 179X. When
DDEN is tied low , EARLY or LATE will be activated at
least 125ns. before and after the Write Data pulse. An
Algorithm internal the 179X decides whether to raise
EARLY or LATE, depending upon the previous bit pattern sent. As an example, suppose the recommended
Precomp value has been specified at 150ns. The following action should be taken:
MOTOR CONTROL
Motor Control is accomplished by the STEP and DIRC
Lines. The STEP Line issues stepping pulses with a
period defined by the rate field in all Type I commands.
The DIRC Line defines the direction of steps (DIRC =
1 STEP IN/DIRC = 0 STEP OUT).
Other Control Lines include the TP or Index Pulse. This
Line is tied to the drives' Index L.E.D. sensor and
makes an active transition for each revolution of the
diskette. The TROO Line is another L.E.D. sensor that
informs the 179X that the stepper motor is at its furthest position, over Track 00. The READY Line can be
L1sed for a number of functions, such as sensing "door
open", Drive motor on, etc. Most drives provide a pro~Jrammable READY Signal selected by option jumpers
on the drive. The 179X will look at the ready signal prior
to executing READ/WRITE commands. READY is not
inspected during any Type I commands. All Type I
commands will execute regardless of the Logic Level
on this Line.
EARLY
LATE
o
o
0
1
ACTION TAKEN
delay WD by 150ns (nominal)
delay WD by 300ns (2X value)
~~1~__~_0~__
do~n_ot_d_e_l-,aY,---W_D~_______~ __
There are two methods of performing Write
Precompensation:
1) External Delay elements
2) Digitally
Shown in Figure 6 is a Precomp circuit using the Western Digital 2143 clock generator as the delay element.
The WD pulse from the 179X creates a strobe to the
2143, causing subsequent output pulses on the.6'1,'o2
and .0'3 signals. The 5K Precomp adjust sets the desired Precomp value. Depending upon the condition of
EARLY and LATE,,0'1 will be used for EARLY, Rf2 for
nominal (EARLY = LATE = 0), and.03 for LATE. The
use of "one-shots" or delay line in a Write Precompensation scheme offers the user the ability to vary the
Precomp value. The.0'4 output resets the 74LS175
Latch in anticipation of the next WD pulse. Figure 7
shows the WD-EARLY/LATE relationship, while Figure
8 shows the timing of this write Precomp scheme.
Another method of Precomp is to perform the function
digitally. Figure 9 illustrates a relationship between the
WD pulse and the CLK pin, allowing a digital Precomp
scheme. Figure 10 shows such a scheme with a preset Write Precompensation value of 250ns. The synchronous counter is used to generate 2MHz and 4MHz
clock signals. The 2MHz clock is sent to the CLK input
of the 179X and the 4MHz is used by the 4-bit shift
register. When a WD pulse is not present, the 4MHz
clock is shifting "ones" through the shift register and
maintaining Q D at a zero level. When a WD pulse is
present, a zero is loaded at either A, B, or C depending
upon the states of LATE, EN PRECOMP and EARLY.
The zero is then shifted by the 4MHz clock until it
reaches the QD output. The number of shift operations
determines whether the WRITE DATA pulse is written
early, nominal or late. If both FM and MFM operations
is a system requirement, the output of this circuit should
be disabled and the WD pulse should be sent directly
to the drive.
WRITE SIGNALS
Writing of data is accomplished by the use of the WD,
WG, WF, TG43, EARLY and LATE Lines. The WG or
Write Gate Line is used to enable write current at the
drive's R/W head. It is made active prior to writing data
on the disk. The WF or WRITE FAULT Line is used to
inform the 179X of a failure in drive electronics. This
signal is multiplexed with the VFOE Line and must be
logically separated if required. Figure 5 illustrates three
methods of demultiplexing.
The TG43 or "TRACK GREATER than 43" Line is
used to decrease the Write current on the inner tracks,
where bit densities are the highest. If not required on
the drive, TG43 may be left open.
WRITE PRECOMPENSATION
The 179X provides three signals for double density
Write Precompensation use. These signals are WRITE
DATA, EARLY and LATE. When using single density
drives (eighter 8" or 5114"), Write Precompensation is
not necessary and the WRITE DATA line is generally
TTL Buffered and sent directly to the drive. In this
mode, EARLY and LATE are left open.
For double density use, Write Precompensation is a
function of the drive. Some manufacturers recommend
Precompensating the 5114" drive, while others do not.
•
197
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X
Shown in Figure 11 is a 2112 IC Counter/Separator. The
74lS193 free runs at a frequency determined by the
CRYClK input. When a RAW READ pulse occurs, the
counter is loaded with a starting count of '5'. When the
RAW READ Line returns to a logic 1, the counter
counts down to zero and again free runs. The 74lS74
insures a 50% duty cycle to the 179X and performs a
divide-by-two of the Q D output.
Figure 12 illustrates another Counter/Separator utilizing a PROM as the count generator. Depending upon
the RAW READ phase relationship to RClK, the PROM
is addressed and its data output is used as the counter
value. A 16MHz clock is required for 8" double density,
while an 8M Hz clock can be used for single density.
Figure 13 shows a Phase-lock-loop data recovery
circuit. The phase detector (U2, Figure 2) compares
the phase of the SHAPED DATA pulse to the phase
of VFO ClK -;- 2. If VFO ClK ..;.. 2 is lagging the
SHAPED DATA pulse an output pulse on #9, U2 is
generated. The filter/amplifier converts this pulse into
a DC signal which increases the frequency of the VCO.
DATA SEPARATION
The 179X has two inputs (RAW READ & RClK) and
one output (VFOE) for use by an external data separator. The RAW READ input must present clock and
data pulses to the 179X, while the RClK input provides
a "window" or strobe signal to clock each RAW READ
pulse into the device. An ideal Data Separator would
have the leading edge of the RAW READ pulse occur
in the exact center of the RClK strobe.
Motor Speed Variation, Bit shifts and read amplifier
recovery circuits all cause the RAW READ pulses to
drift away from their nominal positions. As this occurs,
the RAW READ pulses will shift left or right with respect to RClK. Eventually, a pulse will make its transition outside of its RClK window, causing either a
CRC error or a Record-not-Found error at the 179X.
A Phase-lock-loop circuit is one method of achieving
synchronization between the RClK and RAW READ
signals. As RAW READ pulses are fed to the Pll,
minor adjustments of the free-running RClK frequency
can be made. If pulses are occurring too far apart, the
RClK frequency is decreased to keep synchronization. If pulses begin to occur closer together, RClK is
increased until this new higher frequency is achieved.
In normal read operations, RClK will be constantly
adjusted in an attempt to match the incoming RAW
READ frequency.
Another method of Data Separation is the CounterSeparator technique. The RClK signal is again freerunning at a nominal rate, until a RAW READ pulse
occurs. The Separator then denotes the position of the
pulse with respect to RClK (by the counter value), and
counts down to increase or decrease the current RClK
window. The next RClK window will occur at a nominal
rate and will continue to run at this frequency until another RAW READ pulse adjusts RClK, but only the
present window is adjusted.
Both PPl and Counter/Separator are acceptable
methods of Data Separation. The PPl has the highest
reliability because of its "tracking" capability and is recommended for 8" double density designs.
As a final note, the term "Data Separator" may be
misleading, since the physical separation of clock and
data bits are not actually performed. This term is used
throughout the industry, and can better be described
as a "Data Recovery Circuit" rather than a Data
Separator.
The VFOE signal is an output from the 179X that signifies the head has been loaded and valid data pulses
are appearing on the RAW READ line. It can be used
to enable the Data Separator and to insure clean RClK
transitions to the 179X. Since some drives will output
random pulses when the head is disengaged, VFOE
can prevent an erratic RClK signal during this time. If
the Data Separator requires synchronization during a
known pattern of one's or zero's, then RG (READ
GATE) can be used. The RG signal will go active when
the 179X is currently over a field of zeros or ones. RG
is not available on the 1795/1797 devices, since this
signal was replaced with the SSO (Side Select Output)
Line.
If, correspondingly, ClK -;- 2 is leading the SHAPED
DATA pulse, an output pulse on #5, U2 is generated.
This pulse is converted into a DC signal which decreases the frequency of the VCO. These two actions
cause the VCO to track the frequency of the incoming
READ DATA pulses. This correction process to keep
the two signals in phase is constantly occurring because
of spindle speed variation and circuit parameter
variations.
The operating specifications for this circuit are as
follows:
Free Running Frequency
Capture Range
lock Up Time
2M Hz
± 15%
50 microsec. "1111" or
"0000" Pattern
100 Microsec "1010" Pattern
The RAW READ pulses are generated from the falling
edge of the SHAPED DATA pulses. The pulses are
also reshaped to meet the 179X requirements. VFO
ClK -;- 2 OR 4 is divided by 2 once again to obtain
VFO ClK OUT whose frequency is that required by the
179X RClK input. RClK must be controlled by VFOE
so VFOE is sampled on each rising edge of VFO ClK
OUT. When VFOE goes active EN RClK goes active
·in synchronization with VFO ClK OUT preventing any
glitches on the RClK output. When VFOE goes inactive EN RClK goes inactive in synchronization with
VFO ClK OUT, again preventing any glitches on the
RClK output.
Figure 14 illustrates a PPl data recovery circuit using
the Western Digital 1691 Floppy Support device. Both
data recovery and Write Precomp logic is contained
within the 1691 allowing low chip count and Pll reliability. The 74S124 supplies the free-running VCO
output. The PUMP UP and PUMP DOWN signals from
the 1691 are used to control the 74S124's frequency.
f
198
COMMAND USAGE
Whenever a command is successfully or unsuccessfully completed, the busy bit of the status register is
reset and the INTRa line is forced high. Command termination may be detected either way. The INTRa can
be tied to the host processor's interrupt with an appropriate service routine to terminate commands. The
busy bit may be monitored with a user program and
will achieve the same results through software. Performing both an INTRa and a busy bit check is not
recommended because a read of the status register to
determine the condition of the busy bit will reset the
INTRa line. This can cause an INTRa from not
occurring.
FORCED INTERRUPT COMMAND
The Forced Interrupt command is generally used to
terminate a multiple sector command or to insure Type
I status in the status register. The lower four bits of the
command determine the conditional interrupt as follows:
10
11
12
13
NOT-READY TO READY TRANSITION
READY TO NOT-READY TRANSITION
EVERY INDEX PULSE
iMMEDIATE INTERRUPT
Regardless of the conditional interrupt set, any command that is currently being executed when the Forced
Interrupt command is loaded will immediately be terminated and the busy bit will be reset indicating an idle
condition.
Then, when the condition for interrupt is met, the INTRa
line will go high signifying that the condition specified
has occurred.
The conditional interrupt is enabled when the corresponding bit positions of the command (13 -10) are set
to a 1. If 13 -10 are all set to zero, no interrupt will occur,
but any command presently under execution will be
immediately terminated upon receipt of the Force Interrupt command (HEX DO).
As usual, to clear the interrupt a read of the status register or a write to the command register is required.
The exception is when using the immediate interrupt
condition (13 = 1). If this command is loaded into the
command register, an interrupt will be immediately
generated and the current command terminated.
Reading the status or writing to the command register
will not automatically clear the interrupt; another forced
interrupt command with 13 -10 = 0 must be loaded into
the command register in order to reset the INTRa from
this condition.
More than one condition may be set at a time. If for
example, the READY TO NOT-READY condition (11 =
1) and the Every Index Pulse (12 = 1) are both set, the
resultant command would be HEX "DA". The "OR"
function is performed so that either a READY TO NOTREADY or the next Index Pulse will cause an interrupt
condition.
RESTORE COMMAND
On some disk drives, it is possible to position the R/W
head outward past Track 00 and prevent the TROO
line from going low unless a STEP IN is first performed.
If this condition exists in the drive used, the RESTORE
command will never detect a TROO. Issuing several
STEP IN pulses before a RESTORE command will
remedy this situation. The RESTORE and all other
Type I commands will execute even though the READY
bit indicates the drive is not ready (NOT READY = 1).
READ TRACK COMMAND
The READ TRACK command can be used to manually
inspect data on a hard copy printout. Gaps, address
marks and all data are brought in to the data register
during this command. The READ TRACK command
may be used to inspect diskettes for valid formatting
and data fields as well as address marks. Since the
179X does not synchronize clock and data until the Index Address Mark is detected, data previous to this 10
mark will "not be valid. READ GATE (RG) is not actuated during this command.
READ ADDRESS COMMAND
In systems that use either multiple drives or sides, the
read address command can be used to tell the host
processor which drive or side is selected. The current
position of the R/W head is also denoted in the six
bytes of data that are sent to the computer.
DATA RECOVERY
Occasionally, the R/W head of the disk drive may get
"off track", and dust or dirt may get trapped on the
media. Both of these conditions will cause a RECORD
NOT FOUND and/or a CRC error to occur. This "soft
error" can usually be recovered by the following
procedure:
1. Issue the command again
2. Unload and load the head and repeat step
3. Issue a restore, seek the track, and repeat step 1
The READ ADDRESS command as well as all other
Type II and Type III commands will not execute if the
READY line is inactive (READY = 0). Instead, an interrupt will be generated and the NOT READY status
bit will be set to a 1.
If RNF or CRC errors are still occurring after trying
these methods, a "hard error" may exist. This is usually caused by improper disk handling, exposure to
high magnetic fields, etc. and generally results in destroying portions or tracks of the diskette.
199
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FIGURE 1.
DEVICE
DEVICE CHARACTERISTICS
SNGL DENSITY DBLE DENSITY
1791
1792
1793
1794
1795
1797
X
X
X
X
X
X
INVERTED BUS
X
TRUE BUS
DOUBLE-SIDED
X
X
X
X
X
X
X
X
X
X
X
FIGURE 2. STORAGE CAPACITIES
UNFORMATTED
CAPACITY (NOMINAL)
SIZE
DENSITY
SIDES
PER TRACK
PER DISK
5%/1
5%/1
5%/1
5%/1
8/1
8/1
8/1
8/1
SINGLE
DOUBLE
SINGLE
DOUBLE
SINGLE
DOUBLE
SINGLE
DOUBLE
1
1
2
2
1
1
2
2
3125
6250
3125
6250
5208
10,416
5208
10,416
109,375*
218,750
218,750
437,500
401,016
802,032
802,032
1,604,064
*Based on 35 Tracks/Side
**Based on 18 Sectors/Track (128 byte/sec)
***Based on 18 Sectors/Track (256 bytes/sec)
200
BYTE
TRANSFER
TIME
64JLs
32JLs
64JLs
32JLs
32JLs
16JLs
32JLs
16JLs
FORMATTED
CAPACITY
PER TRACK
2304**
4608***
2304
4608
3328
6656
3328
6656
PER DISK
80,640
161,280
161,280
322,560
256,256
512,512
512,512
1,025,024
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FIGURE 3. NOMINAL VS. WORSE CASE SERVICE TIME
SIZE
DENSITY
NOMINAL TRANSFER
TIME
5%/1
5%/1
8/1
8/1
SINGLE
DOUBLE
SINGLE
DOUBLE
64JLs
32JLs
32JLs
16JLs
WORST-CASE 179X SERVICE TIME
READ
WRITE
55.0JLs
27.5JLs
27.5JLs
13.5JLs
47.0JLs
23.5JLs
23.5JLs
11.5JLs
FIGURE 4A. FM RECORDING
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT6
BIT 7
HEX
'D2'
RULE:
1) WRITE DATA BITS AT CENTER
OF BIT CELL IF A "1"
2) WRITE CLOCK BITS AT LEADING
EDGE OF THE BIT CELL
FIGURE 4B. MFM RECORDING
BITO
BIT 1
BIT 2
BIT 3
BIT 4
HEX
'02'
RULE:
1) WRITE DATA BITS AT CENTER
OF BIT CELL IF A "1"
2) WRITE CLOCK BITS AT LEADING
EDGE OF BIT CELL IF:
A) NO DATA BIT HAS BEEN WRITTEN LAST
-ANDB) NO DATA BIT WILL BE WRITTEN NEXT
201
BIT 5
BIT 6
BIT 7
.......
~
FIGURE 5. WFNFOE DEMULTIPLEXING CIRCUITRY
"'T1
C
+5
.....
+5
a:t
><
10K
33 t-"-.--~~~r----+-~
PRECOMP.
ADJUST
FIGURE 6. 179X WRITE PRE-COMP
202
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f'4-
...A.
~
2, 4/Ls ± CLK TOL
X
500 NS ± 50
WD
WD
I
I
-------------~
EARLY
OR LATE
EARLY
OR LATE
n
DOUBLE TIMES FOR 5" (MINI-FLOPPY)
250 NS MIN.
125 NS MIN. VALID
FOR DURATION OF
WD PULSE
DOUBLE TIMES FOR 5" (MINI-FLOPPY)
450 NS MIN.
VALID BEFORE LEADING EDGE OF WD
WRITE PRE-COMP TIMING FOR MFM
WRITE PRE-COMP TIMING FOR FM
FIGURE 7. WRITE PRE·COMP TIMING
BIT CELL 0
,tf
I
BIT CELL 1
If
I
W[~.JclI....-_ _....1d
BIT CELL 2
".
I
BIT CELL 3
BIT CELL 4
BIT CELL 5
Jj
I
> 1~'Mt->-:--_ _ _-'ro1
fJ
--Lnl..._______ n
n
EARLY _ _ _ _ _ _ _ _
LATE _ _ _ _ _ _ _ _ _ _ _ _ _ _
C-EARLY
C-LATE
C-NOMINAL
BIT IELL 6
I
BIT tELL 7
I ~ 200NS
rc1
---I
~
______________. .r-l~_______________~J l
11
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....
n
n
I
BIT CELL 8
fa
P
I
rc1
n
n
.~'--_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____'
FIGURE 8. PRECOMP TIMING FOR CIRCUIT IN FIGURE 6
203
BIT CELL 9
I
'T1
....
.....,.
C
500ns
500ns
ClK
@1MHz
CD
><
l~~1
I
WD
= 0)
(DDEN
~!m
---....I~~J-L..L..o<.f.
I
~----
I
1·i·~\
;;.100ns
;;.1OOn5
250n5
250n6
ClK
@2MHz
125ns
WD
(DDEN = 0)
""SOns
;;.30n5
FIGURE 9. WD/CLK RELATIONSHIP FOR WRITE PRECOMP USE
74lS161
3
8MHz
A
4
B
5
6
C
0
7
9
ill
10
T
D--------1f---'2:...j
D.
C
13
P
2MHz
(TO 1791)
4MHz
a.
74lS195
ClK
10
ClK
1Kn
+5
we
(FROM 1791)
~~_ _ _ _ _ _ _ _--'----:-I' ~
K
74lS04
~
V
_ _---;
70
~
9SHFT/Cll"
LATE
(FROM 1791)
me
4
A
TG43 (EN PRECOMP)
NoM
5
B
b--_~_ _ _ _",Ei\",RI;Y
B
C
EARLY
(FROM 1791)
1:1,~
FIGURE 10. DIGITAL WRITE PRECOMP CIRCUIT
(PROVIDED COURTESY OF MPI. OKLAHOMA CITY. OK 73112
204
WRITE
DATE
(TO DRIVE)
."
C
+5
R, C
RAW READ
FROM DRIVE
= 150 NS
ca"""""
><
± 50
~___~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,______
27~
~
1791/1793
26
LD
+5 r----..----"7-1 A
B
C
D
4CD
0 0 1-'-----1
CU
C
5
N.U.
74LS74'
+5
11.._
74LS193
CRYCLK
TYPE
CRYCLK
8" FM
8 MHz
5"MFM
8 MHz
5" FM
4 MHz
FIGURE 11. COUNTER/SEPARATOR
205
RCLK
RG
+5
745288 PROGRAMMING TABLE
ADDRESS
DATA
00
01
01
01
02
02
03
03
04
05
03
04
06
05
07
06
OS
OB
09
OD
OA
OC
OS
OC
OD
OE
I
OE
~
74LS04
RETARD BY 2 COUNTS
27
READ DATA
FROM
DRIVE
26
ADVANCE BY 1 COUNT
00
01
01
12
13
03
14
05
15
06
16
07
17
08
FREE RUN
+5
02
04
+5
09
OA
1A
OB
1B
1C
OD
OC
10
OE
1E
OF
1F
00
_1
FIGURE 12. 179X DATA SEPARATOR
(PROVIDED COURTESY OF ANDROMEDA SYSTEMS, PANORAMA CITY, CA 91402)
FD179X
RAW READ
ADVANCE BY 2 COUNTS
OF
10
11
~
NONE
RETARD BY 1 COUNT
OF
OF
18
ACTION TAKEN
L
co
o
N
-12 0
.,,,.
R16
10KO
Rl1
1400
1%
+5
R25
1600
1/2W
Rla
2700
1j2W
R21
lOKO
1%
VR2
5.6V
5%
R12
8060
+5
1%
TPl
31 26502
6
Ul
S
11 J
12 K
14 R
+5 ~~~"
~r--1
~)TP2
0
~
I
L
I
1<..9
R30
C89
5.1KO
82ILF
R33
3.48Kf1
1%
VFOCLK
STEERING 2
IL.........!..!. ..
R29
lKf1
II
1.2Kf1
+5
R32
2.2Kf1
13 CLK
R23
741C
U2
I\)
CR2
IN914
VFOCLK
STEERING 1
ClR
~
R20
3.48KfI
1%
R19
2.2KfI
U3
CRl
1N914
C72
.1ILF
C83
.047ILF
C82
1300ILF
R34
10Kfl
2"/0
1%
-12
VFOCLK :20R4
RAWREAD
<
See page 725 for ordering information .
•
209
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CD
X
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no restnsibility is assumed by Western Digital
Corporation for its use; nor for any Infringements of patents or other rights of third parties which may res t from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
210
Printed
In
U.S.A
WESTERN DIGITAL
c
o
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p
o
R
A
T
/
o
N
WD279X·02 Floppy Disk Formatter/Controller Family
The WD279X Family are MOS/LSI devices which perform
the functions of a Floppy Disk Controller/Formatter. Software compatible with its predecessor, the FD179X, the
device also contains a high performance Phase-lock-Loop
Data Separator as well as Write Precompensation Logic.
FEATURES
ON-CHIP PLL OAT A SEPARATOR
o
t. ON-CHIP WRITE PRECOMPENSATION LOGIC
SINGLE +5V SUPPLY
o
ACCOMMODATES SINGLE AND DOUBLE DENSITY
FORMATS
IBM 3740 (FM)
IBM 34
(MFM)
tJ
When operating in Double Density mode, Write Precompensation is automatically engaged to a value programmed
via an external potentiometer. An on-chip veo and phase
comparator allows adjustable frequency range for 51/4" or
8" Floppy Disk interfacing.
• AUTOMATIC SEEK WITH VERIFY
•
The WD279X is fabricated in NMOS silicon gate technology
and available in a 40 pin dual-in-line ceramic or plastic
package.
MULTIPLE SECTOR READ/WRITE
• TTL COMPATIBLE
•
PROGRAMMABLE CONTROL
SELECTABLE TRACK-TO-TRACK ACCESS
HEAD LOAD TIMING
,..-;;--
• SOFTWARE COMPATIBLE WITH THE FD179X SERIES
• SOFT SECTOR FORMAT COMPATIBILITY
APPLICATIONS
8" FLOPPY AND 51/4" MINI FLOPPY CONTROLLER
FEATURES
2791
2793
Single Density (FM)
Double Density (MFM)
True Data Bus
Inverted Data Bus
Side Select Out
I nternal eLK Divide
X
X
X
X
X
X
X
X
X
X
X
X
X
X
---
2795 \ 2797/
X
X
SINGLE OR DOUBLE DENSITY
CONTROLL.ER/FORMATTER
-
ENP
WE
HLT
ORa
FiE
DDEN
AO
WPRT
A1
DALO
1 - - - - - - - . . . - 1 WE
INTRa
cs
HOST
PROCESSOR
iP
DAL1
WPW
READY
DAL3
WD
DAL4
WG
DAL5
TG43
DAL6
HLD
DAL7
'RAWR6
14---------1
~14---------~
r043
I---J--------+-I
;
I
'NP~
wo
~m!
~
1m
f-----~;;;;;
TROO
DAL2
,.
~=::::==========:::
~~--------~
WPRr
ENMF
I---
PUMP~~
~
'::0
14---------~
vcb
CENTERFRE~~~
~
iEsT-
STEP
VCO
DIRC
SSO/ENMF
5"/8
RPW
MR
GND
CLK
+SV_Vcc
PUMP
::: ~
~
~OND
'fESi'
Vec
Figure 1.
•
211
8"
DISK
DRIVE
PIN OUTS
:eC
I\)
......
PIN
NUMBER
PIN NAME
ENABLE PRECOMP
ENP
A Logic high on this input enables write precompensat ion to be performed on the Write Data output.
19
MASTER RESET
MR
A logic low (50 microseconds min.) on this input
resets the device and loads HEX 03 into the command register. The Not Ready (Status Bit 7) is reset
during MR ACTIVE. When MR is brought to a logic
high a RESTORE Command is executed, regardless
of the state of the Ready signal from the drive. Also,
HEX 01 is loaded into sector register.
20
POWER SUPPLIES
VSS
Ground
vcc
+5V ±5%
(C
><
6
I\)
FUNCTION
SYMBOL
1
21
COMPUTER INTERFACE:
A logic low on this input gates data on the DAL into
the selected register when CS is low.
2
WRITE ENABLE
3
CHIP SELECT
4
READ ENABLE
A logic low on this input controls the placement of
data from a selected register on the DAL when CS is
low.
REGISTER SELECT LINES AO, A1
These inputs select the register to receive/transfer
data on the DAL lines under RE and WE control:
5,6
A logic low on this input selects the chip and enables
computer communication with the device.
CS
-
CS
A1
AO
0
0
0
0
0
0
1
1
0
1
0
1
-
RE
Status Reg
Track Reg
Sector Reg
Data Reg
WE
Command Reg
Track Reg
Sector Reg
Data Reg
DATA ACCESS LINES
DALO-DAL7
Eight bit bi-directional bus used for transfer of commands, status, and data. These lines are inverted
(active low) on WD2791 and WD2795.
24
CLOCK
CLK
This input requires a free-running 50% duty cycle
square wave clock for internal timing reference, 2
MHz ± 1% for 8" drives,.1 MHz ± 1% for minifloppies.
38
DATA REQUEST
DRQ
This output indicates that the Data Register contains
assembled data in Read operations, or the DR is
empty in Write operations. This signal is reset when
serviced by the computer through reading or loading
the DR.
39
INTERRUPT REQUEST
INTRQ
7-14
ji
This output is set at the completion of any command
and is reset when the Status register is read or the
Command register is written to.
FLOPPY DISK INTERFACE:
15
STEP
STEP
The step output contains a pulse for each step.
16
DIRECTION
DIRC
Direction Output is active high when stepping in,
active low when stepping out.
17
51/4," 8" SELECT
5i8
This input selects the internal VCO frequency for use
with 51/4" drives or 8" drives.
18
READ PULSE WIDTH
RPW
An external potentiometer tied to this input controls
the phase comparator within the data separator.
212
•
PIN
NUMBER
PIN NAME
FUNCTION
SYMBOL
22
TEST
l'ES'f
A logic low on this input allows adjustment of external resistors by enabling internal signals to appear on
selected pins.
23
PUMP
PUMP
High-Impedance output signal which is forced high
or low to increase/decrease the VCO frequency.
25
ENABLE MINI-FLOPPY
(2791, 2793)
ENMF
A logic low on this inpu!.. enables an internal + 2 of
the Master Clock when 5/8 is also at a logic O. This
allows both 51/4" and 8" drive operation with a single
2 MHz clock. For a 1 MHz clock on Pin 24, this line
must be left open or tied to a Logic 1.
25
SIDE SELECT OUTPUT
(2795, 2797)
SSO
The logic level of the Side Select Output is directly
controlled by the'S' flag in Type II or III commands.
When U
1, SSO is set to a logic 1. When U
0,
SSO is set to a logic O. The SSO is compared with the
side information in the Sector I.D. Field. If they do not
compare Status Bit 4 (RNF) is set. The Side Select
Output is only updated at the beginning of a Type II or
III command. It is forced to a logic 0 upon a MASTER
RESET condition.
26
VOLTAGE-CONTROLLED
OSCILLATOR
VCO
An external capacitor tied to this pin adjusts the VCO
center frequency.
27
RAW READ
RAW READ
The data input signal directly from the drive. This
input shall be a neg'ative pulse for each recorded flux
transition.
~-.r--
28
HEAD LOAD
HLD
The HLD output controls the loading of the ReadWrite head against the media.
29
TRACK GREATER
THAN 43
TG43
30
WRITE GATE
WG
31
WRITE DATA
WD
32
READY
READY
TQis input indicates disk readiness and is sampled
for~ logic high before Read or Write commands are
performed. If Ready is low the Read or Write
operation is not performed and an interrupt is
generated. Type I operations are performed regardless of the sta~e of Ready. The Ready input appears in
inverted format as Status Register bit 7.
33
WRITE PRECOMP
WIDTH
WPW
An external potentiometer tied to this input controls
the amount of delay in Write precompensation mode.
34
TRACK 00
TROO
This input informs the WD279X that the Read/Write
head is positioned over Track 00.
35
INDEX PULSE
fi5
This input informs the WD279X when the index hole
is encountered on the diskette.
=
,."/\
=
This output informs the drive that the Read/Write
~ head is positioned between tracks 44-76. This output
is valid only during Read and Write Commands.
This output is made valid before writing is to be
~~rtorm~d on the diskette.
250ns (MFM) or 500 ns (FM) output pulse per flux
t ~nsition. WD contains the unique Address marks as
Well as data and clock in both FM and MFM formats.
!
213
PIN NUMBER
PIN NAME
SYMBOL
FUNCTION
36
WRITE PROTECT
WPRT
This input is sampled whenever a Write Command is
received. A logic low terminates the command and
sets the Write Protect Status bit.
37
DOUBLE DENSITY
DDEN
This input pin selects either single or double density
operation. When DDEN
0, double density is
selected. When DDEN
1, single density is
selected.
=
=
40
HEAD LOAD TIMING
HLT
When a logic high is found on the HLT input the head
is assumed to be engaged. It is typically derived from
a 1 shot triggered by HLD.
register is loaded from the DAL and gated onto the DAL
under processor control.
Track Register - This 8-bit register holds the track number
of the current Read/Write head position. It is incremented
by one every time the head is stepped in (towards track 76)
and decremented by one when the head is stepped out
(towards track 00). The contents of the register are compared with the recorded track number in the ID field during
disk Read, Write and Verify operations. The Track Register
can be loaded from or transferred to the DAL. This Register
should not be loaded when the device is busy.
Sector Register (SR) - This 8-bit register holds the address
of the desired sector position. The contents of the register
are compared with the recorded sector number in the ID
field during disk Read or Write operations. The Sector
Register contents can be loaded from or transferred to the
DAL. This register should not be loaded when the device is
busy.
GENERAL DESCRIPTION
The WD279X are N-Channel Silicon Gate MOS LSI devices
which perform the functions of a Floppy Disk Formatter/Controller in a single chip implementation. The
WD279X, which can be considered the end result of both
the FD1771 and FD179X designs, is IBM 3740 compatible in
single density mode (FM) and System 34 compatible in
Double Density Mode (MFM). The WD279X contains all the
features of its predecessor the FD179X plus a high performance Phase-lock-Loop Data Separator as well as Write
Precompensation Logic. In Double Density mode, Write
Precompensation is automatically engaged to a value
programmed via an external potentiometer. In order to
maintain compatibility, the FD1771, FD179X and WD279X
designs were made as close as possible with the computer
interface, instruction set, and I/O registers being identical.
Also, head load control is identical. In each case, the actual
pin assignments vary by only a few pins from anyone to
another.
Command Register (CR) - This 8-bit register holds the
command presently being executed. This register should
not be loaded when the device is busy unless the new
command is a force interrupt. The command register can
be loaded from the DAL, but not read onto the DAL.
Status Register (STR) - This 8-bit register holds device
Status information. The meaning of the Status bits is a
function of the type of command previously executed. This
register can be read onto the DAL, but not loaded from the
DAL.
CRC LogiC - This logic is used to check or to generate the
16-bit Cyclic Redundancy Check (CRC). The polynomial is:
G(x) = x16 + x 12 + x5 + 1.
The processor interface consists of an 8-bit bi-directional
bus for data, status, and control word transfers. The
WD279X is set up to operate on a multiplexed bus with
other bus-oriented devices.
The WD279X is TTL compatible on all inputs and outputs.
The outputs will drive one TTL load or three LS loads. The
2793 is identical to the 2791 except the DAL lines are TRUE
for systems that utilize true data busses.
The 2795/7 has a side select output for controlling double
sided drives.
ORGANIZATION
The CRC includes all information starting with the address
mark and up to the CRC characters. The CRC register is
preset to ones prior to data being shifted through the
circuit.
Arithmetic/Logic Unit (ALU) - The ALU is a serial comparator, incrementer, and decrementer and is used for register
modification and comparisons with the disk recorded ID
field.
Timing and Control - All computer and Floppy Disk interface controls are generated through this logic. The internal device timing is generated from an external crystal
clock.
AM Detector - The address mark detector detects ID, data
and index address marks during read and write operations.
Write Precompensatlon - enables write precompensation
to be performed on the Write Data output.
The Floppy Disk Formatter block diagram is illustrated on
page 5. The primary sections include the parallel processor
interface and the Floppy Disk interface.
Data Shift Register - This 8-bit register assembles serial
data from the Read Data input (RAW READ) during Read
operations and transfers serial data to the Write Data
output during Write operations.
Data Register - This 8-bit register is used as a holding
register during Disk Read and Write operations in Disk
Read operations the assembled data byte is transferred in
parallel to the Data Register from the Data Shift Register. In
Disk Write operations information is transferred in parallel
from the Data Register to the Data Shift Register.
When executing the Seek command the Data Register
holds the address of the desired Track position. This
214
=f~
WRITE DATA
(TO DISK)
Sis
veo
PUMP
PLA
CONTAOL
(230 X 16)
COMPUTER
INTERFACE
CONTROL
DISK
If'IITEAFA,-:e
CONTR0~
WD279X BLOCK DIAGRAM
Data Separator - a high performance Phase-Lock-Loop
Data Separator with on-chip VCO and phase comparator
allows adjustable frequency range for 5%" or 8" Floppy
Disk interfacing.
During Direct Memory Access (DMA) types of data transfers between the Data Register of the WD279X and the
processor, the Data Request (DRQ) output is used in Data
Transfer control. This signal alSo appears as status bit 1
during Read and Write operations.
IPROCESSORINTERFACE
On Disk Read oper.ations the Data Request is activated (set
,high) when an assembled serial input byte is transferred in
parallel to the Data Register. This bit is cleared when the
Data Register is read by the processor. If the Data Register
is read after one or more characters are lost, by having new
data transferred into the register prior to processor readout,
the Lost Data bit is set in the Status Register. The Read
operation continues until the end of sector is reached.
The interface to the processor is accomplished through the
eight Data Access Lines (DAL) and associated control
signals. The DAL are used to transfer Data, Status, and
Control words out of, or into the WD279X. The DAL are
three state buffers that are enabled as output drivers when
Chip Select (CS) and Read Enable (RE) are active (low logic
state) or act as input receivers when CS and Write Enable
(WE) are active.
On Disk Write operations the data Request is activated
when the Data Register transfers its contents to the Data
Shift Register, and requires a new data byte. It is reset when
the Data Register is loaded with new data by the processor.
If new data is not loaded at the time the next serial byte is
required by the Floppy Disk, a byte of zeroes is written on
the diskette and the Lost Data bit is set in the Status
Register.
When transfer of data with the Floppy Disk Controller is
required by the host processor, the device address is
decoded and CS is made low. The address bits A1 and AO,
combined with the signals RE during a Read operation or
WE during a Write operation are interpreted as selecting
the following registers:
A1 - AO
\7
°0
1
1
0
1
0
1
READ (RE)
Status Register
Track Register
Sector Register
Data Register
WRITE (WE)
Command Register
Track Register
Sector Register
Data Register
At the completion of every command an INTRQ is
generated. INTRQ is reset by either reading the status
register or by loading the command register with a new
command. In addition, INTRQ is generated if a Force Interrupt command condition is met.
215
The 279X has two modes of operation according to the
state of DDEN (Pin 37). When DDEN = 1, Single Density
(FM) is selected. When DDEN = 0, Double Density (MFM)
is selected. In either case, the ClK input (Pin 24) is set at 2
MHz for8" drives or 1 MHz for 51/4 " drives.
Sector length Table*
Number of Bytes
Sector length
in Sector (decimal)
Field (hex)
128
00
256
01
512
02
1024
03
On the 2791/2793, the ENMF input (Pin 25) can be used for
controlling both 51/4" and 8" drives with a single 2 MHz
clock. When ENMF = 0, an internal + 2 of the ClK is
performed. When ENMF = 1, no divide takes place. This
allows the use of a 2 MHz clock for both 5V4" and 8"
configurations.
The internal VCO frequency must also be set to the proper
value. The 518 input (Pin 17) is used to select data separator
operation by internally dividing the Read Clock. When 5/8
= 0, 51/4" data separation is selected; when 5/8 = 1, 8"
drive data separation is selected.
CLOCK (24)
ENMF(25)
5/8 (17)
DRIVE
2MHz
2MHz
1 MHz
1
0
1
1
0
0
8"
51/4"
51/4"
* 2795/97 may vary - see command summary.
placed to a logical "0." Sector lengths are determined at
format time by the fourth byte in the "10" field.
The number of sectors per track as far as the 279X is concerned can be from 1 to 255 sectors. The number of tracks
as far as the 279X is concerned is from 0 to 255 tracks. For
IBM 3740 compatibility, sector lengths are 128 bytes with 26
sectors per track. For System 34 compatibility (MFM),
sector lengths are 256 bytes/sector with 26 sectors/track; or
lengths of 1024 bytes/sector with 8 sectors/track.
GENERAL DISK WRITE OPERATION
When writing is to take place on the diskette theW rite Gate
(WG) output is activated, allowing current to flow into the
ReadlWrite head. As a precaution to erroneous writing the
first data byte must be loaded into the Data Register in
response to a Data Request from the 279X before the Write
Gate signal can be activated.
Note: All other conditions invalid.
FUNCTIONAL DESCRIPTION
The WD279X-02 is software compatible with the FD179X-02
series of Floppy Disk Controllers. Commands, status, and
data transfers are performed in the same way. Software
generated for the 179X can be transferred to a 279X system
without modification.
Writing is inhibited when the Write Protect input is a logic
low, in which case any Write command is immediately
terminated, an interrupt is generated and the Write Protect
status bit is set.
In addition to the 179X, the 279X contains an internal Data
Separator and Write precompensation circuit. The TEST
(Pin 22) line is used to adjust both data separator and precompensation. ~ben TESf = ~ the WD (Pin 31)~
internally connected to the output of the write reco
one-sho .
u
n
e
In 3 line can then
accompjiShed. A second one-shot tracks the precom[}...S~
ting at approxin'ilitely 3:1 to insure adequate Write Data
Rulse widths to meet drive speclfication~.
For write operations, the 279X provides Write Gate (Pin 30)
and Write Data (Pin 31) outputs. Write data consists of a
series of pulses set to a width approximately three times
greater than the precomp adjustment. Write Data provides
the unique address marks in both formats.
READY
Similarly, Data....separation is also adjusted with fEST - 0
The TG43 (Pin 2m line is internally connected to the oujQ,y!
of the read data one~ wbich is adjusted via the~PW
(Pin 18) line. The DIRC (\in 16) line contains the Read Clock
output (.5 MHz for 8" drives). The VCO Trimming capacitor
tei!i1§L!~""aQjlJ~J~r center frequency.
Whenever a Read or Write command (Type II or III) is
received the 297X samples the Ready input. If this input is
logic low the command is not executed and an interrupt is
generated. All Type I commands are performed regardless
of the state of the Ready input. Also, whenever a Type II or
III command is received, the TG43 signal output is updated.
TG43 may be tied to ENP to enable write precompensation
on tracks 44-76.
Internal timing Signals are used to generate pulses during
the adjustment mode so that these adjustments can be
made while the device is in-circuit. The TEST line also
contains a pull-up resistor, so adjustments can be performed simply by grounding the 'i"E'Si pin, overriding the
pull-up. The TEST pin cannot be used to disable stepping
rates during operation as its function is quite different from
the 179X.
COMMAND DESCRIPTION
The WD279X will accept eleven commands. Command
words should only be loaded in the Command Register
when the Busy status bit is off (Status bit 0). The one exception is the Force interrupt command. Whenever a
command is being executed, the Busy status bit is set.
When a command is completed, an interrupt is generated
and the Busy status bit is reset. The Status Register indicates whether the completed command encountered an
error or was fault free. For ease of discussion, commands
are divided into four types. Commands and types are
summarized in Table 1.
Other pins on the device also include pull-up resistors and
may be left open to satisfy a logic 1 condition. These are:
ENP, 5/8, ENMF, WPRT, and DDEN.
GENERAL DISK READ OPERATIONS
Sector lengths of 128, 256, 512 or 1024 are obtainable in
either FM or MFM formats. For FM, DDEN should be
placed to logical "1." For MFM formats, DDEN should be
216
/'..«('( (
TABLE 1.
Bits
I
I
I
I
7
Restore
Seek
Step
Step-in
t
0
0
0
0
0
III
III
IV Force Interrupt
6
5
0
0
0
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
4
0
1
T
T
T
II
1(7
COMMAND SUMMARY
B. Commands for Models: 2795, 2797
A. Commands for Models: 2791, 2793
Type Command
( l ),
:E
Bits
3
2
h
h
h
h
h
r1
r1
r1
r1
V
V
V
V
V
q
0
rO
rO
ro
ro
rO
7
0
0
0
0
0
6
0
0
4
0
1
T
3
h
h
h
2
r1
r1
r1
(~
(f)
r1.
1
T.
r1
U-C
U
U
U ~.
"b
0
0
ro
ro
ro
ro
ro
0
aO
0
0
I\)
-....
CD
><
6I\)
TABLE 2. FLAG SUMMARY
FLAG SUMMARY
Command
Type
Bit
No(s)
I
0,1
I
2
V = Track Number Verify Flag V = 0, No verify
V = 1, Verify on destination track
I
3
h = Head Load Flag
h = 0, Unload head at beginning
h = 1, Load head at beginning
I
4
T = Track Update Flag
T = 0, No update
T
1, Update track register
11&111
0
aO = Data Address Mark
II
1
C = Side Compare Flag
C = 0, Disable side compare
C = 1, Enable side compare
11&111
1
U = Update SSO
U = 0, Update SSO to 0
U = 1, Update SSO to 1
11&111
2
E = 15 MS Delay
E = 0, No. 15 MS delay
E = 1,15 MS delay (30 MS for 1 MHz)
II
3
S = Side Compare Flag
S = 0, Compare for side 0
S = 1, Compare for side 1
II
3
L = Sector Length Flag
Description
r1 ro = Stepping Motor Rate
See Table 3 for Rate Summary
II
4
IV
0-3
=
=
=
=
=
=
LSB's Sector Length in ID Field
01
10
11
256
512
1024
128
128
256
512
1024
00.
m = Multiple Record Flag
Ix
IO
11
12
13
13-10
i.1¢¢
, ao = 0, FB (DAM)
aO = 1, F8 (deleted DAM)
L =0
L = 1
m = 0, Single record
m - 1, Multiple records
Interrupt Condition Flags
1 Not Ready To Ready Transition
1 Ready To Not Ready Transition
1 Index Pulse
1 Immediate Interrupt, Requires A Reset*
0 Terminate With No Interrupt (INTRQ)
* NOTE: See Type IV Command Description for further information.
217
t." )
r-
Write Precompensation
inhibit over-responsiveness to jitter and to prevent an
extremely wide lock-up response, leading to PUMP runaway. The filter affects these two reactions in mutually
opposite directions.
When operating in Double Density mode (DDEN = 0), the
279X has the capability of providing a user-defined
precompensation value for Write Data An external
potentiometer (10K) tied to the Wpyv signal (Pin 33) allows a
setting of 100 to 300 ns from nominal.
Setting the Write precomp value is accomplished by forcing the TEST line (Pin 22) to a logic O. A stream of pulses
can then be seen on the Write Data (Pin 31) line. Adjust the
WPW Potentiometer for the desired pulse width. This
adjustment may be performed in-circuit since Write Gate
(Pin 30) is inactive while TEST = O.
The Source Impedance for a PUMP UPIDOWN condition is
6001120 ohms, respectively, therefore the change in bias
voltage for each pump can be approximated:
dt t::" V
dt = 250 ns. (set by RPW)
dV = ~
C = 0.1",f
R=RS+R
t::"V = 2.6VforPUMPUP
0.9V for PUMP DOWN
Data Separation
-beok-up response (TL) is the transient till'je for the loop to
lock from center frequency (FO) to maximum lock range:
\.J:JCX-
The 279X can operate with either an external data separator
or its own internal recovery circuits. The condition of the
fEST line (Pin 22) in conjunction wit - Pin 1 will select
~internal orexterna mo e.
-
-~-
To program the 279X for external VCO, a MR pulse must be
applied while TEST = O. A clock equivalent to eight times
the data rate (e.g., 4.0 MHz for 8" Double Density) is applied
to the VCO input (Pin 26). The feedback reference voltage is
available on the Pump output (Pin 23) for external integration to control the VCO. TEST is returned to a logic 1
for normal operation. ~Qle'~ maintain this mode. fESi
must be held low whenever MR is applied
For
inferMI
Tl = 10% FlXKOXt::"P
Where:
KO = VCO Conversion Gain = 3.7KHz/mV
Fl = lock Range = 4.00 MHz
t::"P = Change in Bias for each Pump = 4mV/PUMP
\leo
opemtjon tl::1Q
lm
liRQ
FR' 'Si he
400 KHz x 3.7 KHz x 4 mV = 27 pumps
27 pumps
= 54 ",sec = 3.4 Byte times (8" Double Density)
The following Filter Circuit is recommended for 8"
FM/MFM:
PUMP
(PIN 23)
•
-.1/-1f...L
lKQP'N914
l::1igb.
~ring the MR pulse, then set to a logic 0 for the adjustment.l2rocedure.
~
~
Since 5!,' ~~~eQ ~~rate at e~~ on~~~lhe data rate
(250 KblseC)thA ;h(;\U; capa'ifnr;hOllld t;;;;;;lJbled to.2or
A 50K Potentiometer tied to the RPW input (Pin 18) is used
to set the internal Read Data pulse for proper phasing. With
a scope on Pin 29 (TG43), adjust the RPW plJlse.lor 1/8 of
the data rate (250 ns for 8" Double Densit . An external
variable capacitor 0
pf is tied to the VCO input (Pin 26)
for adjusting center frequency. With a frequency counter
on Pin 16 (DIRC) adjust the trimmer cap to yield the appropriate Data Rate (500 KHz for 8" Double Density);- The
line must be low while the 5/8 line is held high o(l[e·
adjustment times above will be doubled.
~
TYPE I COMMANDS
The Type I Commands include the Restore, Seek, Step,
Step-in, and Step-Out commands. Each of the Type I
Commands contains a rate field (ro r1), which determines
the stepping motor rate as defined in Table 3.
iIDFN
A 4tS (MFM) or 4 "'S (FM) pulse is provided as an output to
the drive. For every step pulse issued, the drive moves one
track location in a direction determined by the direction
output. The chip will step the drive in the same direction it
last stepped unless the command changes the direction.
~ adjustments
have been made, the TEST pin is
returned to a logic 1 and the device is ready for operation.
Adjustments may be made in-circuit since the DIRC and
TG43 lines may toggle without affecting the drive.
The Direction signal is active high when stepping in and
low when stepping out. The ~ction signal is valid ~
~forE1.. the ~ stepping gul~ generated.
The PUMP output (Pin 23) consists of positive and negative
pulses, which their duration is equivalent to the phase
difference of incoming Data vs. VCO frequency. This signal
is internally connected to the VCO input, but a Filter is
needed to connect these pulses to a slow moving DC
voltage.
The rates (shown in Table 3) can be applied to a StepDirection Motor through the device interface.
TABLE 3. STEPPING RATES
The internal phase-detector is unsymmetrical for a random
distribution of data pulses by a factor of two, in favor of a
PUMP UP condition. Therefore, it is desirable to have a
PUMP DOWN twice as responsive to prevent run-away
during a lock attempt.
ClK
A first order lag-lead filter can be used at the PUMP output
(Pin 23). This filter controls the instantaneous response of
the VCO to bit-shifted data Oitter) as well as the response to
normal frequency shift, i.e., the lock-up time. A balance
must be accomplished between the two conditions to
R1
RO
o
0
o
1
1
1
0
1
2 MHz
TEST = 1
3 ms
6ms
10 ms
15ms
1 MHz
TEST = 1
C-· ~iD$:?
T2ms
20 ms
30ms )
_~ft~r the last directional step an \ddbYonal iSmrfii;eccmds
of tiead settling time takes place if the Verify flag is set in
Type I commands. Note lhat this time doubles to 30 ms for
218
a 1 MHz clock. There is also a 15 ms head settling time if
the E flag is set in any Type II or III command.
RESTORE (SEEK TRACK 0)
Upon receipt of this command the Track 00 (TROO) input is
sampled. If TROO is active low indicating the Read-Write
head is positioned over track 0, the Track Register is loaded
with zeroes and an interrupt is generated. If TRoo is not
active low, stepping pulses (pins 15 to 16) at a rate specified
by the r1 rO field are issued until the TROO input is activated.
At this time the Track Register is loaded with zeroes and an
interrupt is generated. If the TRoo input does not go active
low after 255 stepping pulses, the 279X terminates
operation, interrupts, and sets the Seek error status bit. A
verification operation takes place if the V flag is set. The h
bit allows the head to be loaded at the start of command.
Note that the Restore command is executed when MR
goes from an active to an inactive state.
When a Seek, Step or Restore command is executed an
optional verification of Read-Write head position can be
performed by setting bit 2 (V = 1) in the command word to
a logic 1. The verification operation begins at the end of the
15 millisecond settling time after the head is loaded against
the media. The track number from the first encountered 10
Field is compared against the contents of the Track
Flegister. If the track numbers compare and the 10 Field
Cyclic Redundancy Check (CRG) is correct, the verify
operation is complete and an INTRQ is generated with no
errors. If there is a match but not a valid CRC, the CRC error
status bit is set (Status bit 3), and the next encountered 10
field is read from the disk for the verification operation.
SEEK
The W0279X must find an 10 field with correct track
number and correct CRC within 5 revolutions of the media;
otherwise the seek error is set and an INTRQ is generated.
If V = 0, no verification is performed.
This command assumes that the Track Register contains
the track number of the current position of the Read-Write
head and the Data Register contains the desired track
number. The WD279X will update the Track register and
issue stepping pulses in the appropriate direction until the
The Head Load (HLO) output controls the movement of the
read/write head against the media. HLO is activated at the
beginning of a Type I command if the h flag is set (h = 1), at
the end of the Type I command if the verify flag (V = 1), or
upon receipt of any Type II or III command. Once HLO is
active it remains active until either a Type I command is
received with (h = and V = 0); or if the 279X is in an idle
state (non-busy) and 15 index pulses have occurred.
°
Head Load timing (HLT) is an input to the 279X which is
used for the head engage time. When HLT = 1, the 279X
assumes the head is completely engaged. The head
engage time is typically 30 to 100' ms depending on drive.
The low to high transition on HLO is typically used to fire a
one shot. The output of the one shot is then used for HLT
and supplied as an input to the 279X.
LD~
[
1 - - 5 0 TO 100ms--!..--_ _ __
jr---;
I
Hl T (FROM ONE SHOT)
HEAD LOAD TIMING
When both HlO and HLT are true, the 279X will then read
from or write to the media. The "and" of HLO and HLT appears as status Bit 5 in Type I status.
=
°
=
In summary for the Type I commands: if h
and V
0,
HLO is reset. If h = 1 and V = 0, HLO is set at the
beginning of the command and HLT is not sampled nor is
and V
1, H LD is set
there an internal 15 ms delay. If h
near the end of the command, an internal 15 ms occurs,
1 and V
1,
and the 279X waits for HLT to be true. If h
HLO is set at the beginning of the command. Near the end
of the command, after all the steps have been issued, an
internal 15 ms delay occurs and the 279X then waits for HLT
to occur.
=°
=
=
=
For Type II and III commands with E flag off, HLD is made
active and HLT is sampled until true. With E flag on, HLD is
made active, an internal 15 ms delay occurs and then HLT is
sampled until true.
TYPE I COMMAND FLOW
219
:ec
N
.....,.
<0
X
6
N
VERIFY
SEQUENCE
NOTE
I MHl THERE IS A 10M" DEI AY
TYPE I COMMAND FLOW
contents of the Track register are equal to the contents of
the Data Register (the desired track location). A verification
operation takes place if the V flag is on. The h bit allows the
head to be loaded at the start of the command. An interrupt
is generated at the completion of the command. Note:
When using multiple drives, the track register must be
updated for the drive selected before seeks are issued.
STEP
Upon receipt of this command, the 279X issues one
stepping pulse to the disk drive. The stepping motor
direction is the same as in the previous step command.
After a delay determined by the r1 rO field, a verification
takes place if the V flag is on. If the T flag is on, the Track
Register is updated. The h bit allows the head to be loaded
at the start of the command. An interrupt is generated at
the completion of the command.
TYPE I COMMAND FLOW
delay determined by the r1 rO field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.
STEP·OUT
Upon receipt of this command, the 279X issues one
stepping pulse in the direction towards track O. If the T flag
is on, the Track Register is decremented by one. After a
delay determined by the r1 rO field, a verification takes place
if the V flag is on. The h bit allows the head to be loaded at
the start of the command. An interrupt is generated at the
completion of the command.
EXCEPTIONS
On the 2795/7 devices, the SSO output is not affected
during Type I commands, and an internal side compare
does not take place when the (V) Verify Flag is on.
STEP·IN
TYPE II COMMANDS
Upon receipt of this command, the 279X issues one
stepping pulse in the direction towards track 76. If the T
flag is on, the Track Register is incremented by one. After a
The Type II Commands are the Read Sector and Write
Sector commands. Prior to loading the Type II Command
into the Command Register, the computer must load the
that character is lost and the Lost Data Status bit is set.
This sequence continues until the complete data field has
been inputted to the computer. If there is a eRe error at the
end of the data field, the eRe error status bit is set, and the
command is terminated (even if it is a multiple sector
command).
At the end of the Read operation, the type of Data Address
Mark encountered in the data field is recorded in the Status
Reg ister (Bit 5) as shown:
STATUS
BIT5
Deleted Data Mark
Data Mark
o
WRITE SECTOR
Upon receipt of the Write Sector command, the head is
loaded (HLD active) and the Busy status bit is set. When an
10 field is encountered that has the correct track number,
correct sector number, correct side number; and correct
CRe, a ORO is generated. The 279X counts off 11 bytes in
single density and 22 bytes in double density from the eRC
field and the Write Gate (WG) output is made active if the
DRO is serviced (Le., the DR has been loaded by the
computer). If ORO has not been serviced, the command is
terminated and the Lost Data status bit is set. If the ORO
has been serviced, the WG is made active and six bytes of
zeroes in single density and 12 bytes in double density are
then written on the disk. At this time the Data Address
Mark is then written on the disk as determined by the ao
field of the command as shown below:
ao
Data Address Mark (Bit 0)
Deleted Data Mark
Data Mark
1
o
The 279X then writes the data field and generates ORO's to
the computer. If the ORO is not serviced in time for continuous writing the Lost Data Status Bit is set and a byte of
zeroes is written on the disk. The command is not terminated. After the last data byte has been written on the
disk, the two-byte eRe is computed internally and written
on the disk followed by one bye of FE in FM or in MFM. The
WG output is then deactivated. For a 2 M Hz clock the
INTRO will set 8 to 12 /Asec after the last CRe byte is
written. For partial sector writing, the proper method is to
write the data and fill the balance with zeroes. By letting the
chip fill the zeroes, errors may be masked by the lost data
status and improper eRe Bytes.
TYPE III COMMAND WRITE TRACK
TYPES III COMMANDS
READ ADDRESS
Upon receipt of the Read Address command, the head is
loaded and the Busy Status Bit is set. The next encountered 10 field is then read in from the disk, and the six
data bytes of the 10 field are assembled and transferred to
the DR, and a ORO is generated for each byte. The six bytes
of the 10 field are shown below:
TRACK
ADDR
1
SIDE
SECTOR SECTOR
NUMBER ADDRESS LENGTH
2
3
4
computer, the 279X checks for validity and the eRe error
status bit is set if there is a eRe error. The Track Address of
the 10 field is written into the sector register so that a
comparison can be made by the host. At the end of the
operation an interrupt is generated and ~he Busy Status is
reset.
READ TRACK
Upon receipt of the READ track command, the head is
loaded, and the Busy Status bit is set. Reading starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse. All Gap, Header, and
data bytes are assembled and transferred to the data
register and ORO's are generated for each byte. The ac-
CRC
1
5
Although the CRe characters are transferred to the
•
223
cumulation of bytes is synchronized to each address mark
encountered. An interrupt is generated at the completion of
the command.
This command has several characteristics which make it
suitable for diagnostic purposes. They are: no CRC
checking is performed; gap information is included in the
data stream; the internal side compare is not performed;
and the address mark detector is on for the duration of the
command. Because the A.M. detector is always on, write
splices or noise may cause the chip to look for an A.M. If an
address mark does not appear on schedule with the lost
Data status flag being set.
The ID A.M., ID field, ID CRC bytes, DAM, Data and Data
CRC Bytes for each sector will be correct. The Gap Bytes
may be read incorrectly during write-splice time because of
synchronization.
WRITE TRACK FORMATIING THE DISK
(Refer to section on Type III commands for flow diagrams.)
Formatting the disk is a relatively simple task when operating programmed I/O or when operating under DMA with a
large amount of memory. Data and gap information must be
provided at the computer interface. Formatting the disk is
accomplished by positioning the RlW head over the desired track number and issuing the Write Track command.
Upon receipt of the Write Track command, the head is
loaded and the Busy Status bit is set. Writing starts with
the leading edge of the first encountered index pulse and
continues until the next index pulse, at which time the
interrupt is activated. The Data Request is activated immediately upon receiving the command, but writing will not
start until after the first byte has been loaded into the Data
Register. If the DR has not been loaded by the time the
index pulse is encountered the operation is terminated
making the device Not Busy, the lost Data Status Bit is set,
and the interrupt is activated. If a byte is not present in the
DR when needed, a byte of zeroes is substituted.
This sequence continues from one index mark to the next
index mark. Normally, whatever data pattern appears in the
data register is written on the disk with a normal clock
pattern. However, if the 279X detects a data pattern of F5
thru FE in the data register, this is interpreted as data address marks with missing clocks or CRC generation.
The CRC generator is initialized when any data byte from
Fa to FE is about to be transferred from the DR to the DSR
TYPE III COMMAND WRITE TRACK
CONTROL BYTES FOR INITIALIZATION
DATA PATIERN
IN DR (HEX)
00 thru F4
F5
F6
F7
Fa thru FB
FC
FD
FE
FF
WD279X INTERPRETATION
IN FM (DDEN = 1)
=
Write 00 thru F4 with ClK
FF
Not Allowed
Not Allowed
Generate 2 CRC bytes
Write Fa thru FB, Clk
C7, Preset CRC
Write FC with Clk
D7
Write FD with Clk
FF
Write FE, Clk
C7, Preset CRC
Write FF with Clk ~. FF
=
=
=
=
WD279X INTERPRETATION
IN MFM (DDEN
0)
=
Write 00 thru F4, in MFM
Write A 1* in MFM, Preset CRC
Write C2** in MFM
Generate 2 CRC bytes
Write Fa thru FB, in MFM
Write FC in MFM
Write FD in MFM
Write FE in MFM
Write FF in MFM
* * Missing clock transition between bits 3 and 4
* Missing clock transition between bits 4 and 5
224
•
or by receipt of F5 in MFM. An F7 pattern will generate two
CRC characters in FM or MFM. As a consequence, the
patterns F5 thru FE must not appear in the gaps, data
fields, or ID fields. Also, CRC's must be generated by an F7
pattern.
reset.
The lower four bits of the command determine the condi·
tional interrupt as follows:
10
11
12
13
Disks may be formatted in IBM 3740 or System 34 formats
with sector lengths of 128, 256, 512, or 1024 bytes.
TYPE IV COMMANDS
= Not-Ready to Ready Transition
= Ready to Not-Ready Transition
= Every Index Pulse
= Immediate Interrupt
The conditional interrupt is enabled when the corresponding bit positions of the command (13 - 10) are set to a 1.
Then, when the condition for interrupt is met, the INTRQ
line will go high signifying that the condition specified has
occurred. If 13 - 10 are all set to zero (HEX DO), no interrupt
will occur but any command presently under execution will
be immediately terminated. When using the immediate
The Forced Interrupt command is generally used to ter·
minate a multiple sector read or write command or to insure Type I status in the status register. This command can
be loaded into the command register at any time. If there is
a current command under execution (busy status bit set)
the command will be terminated and the busy status bit
TYPE III COMMAND
Read Track/Address
225
interrupt condition 13 = 1), an interrupt will be immediately
generated and the current command terminated. Reading
the status or writing to the command register will not automatically clear the interrupt. The HEX DO is the only com·
mand that will enable the immediate interrupt (HEX 08) to
clear on a subsequent load command register or read sta·
tus reg ister operation. Follow a HEX 08 with DO command.
STATUS REGISTER
Upon receipt of any command, except the Force Interrupt
command, the Busy Status bit is set and the rest of the
status bits are updated or cleared for the new command. If
the Force Interrupt Command is received when there is a
current command under execution, the Busy status bit is
reset, and the rest of the status bits are unchanged. If the
Force Interrupt command is received when there is not a
current command under execution, the Busy Status bit is
reset and the rest of the status bits are updated or cleared.
In this case, Status reflects the Type I commands.
Wait 8 micro sec (double density) or 16 micro sec (single
density) before issuing a new command after issuing a
forced interrupt (times double when clock = 1 MHz).
Loading a new command sooner than this will nullify the
forced interrupt.
Forced interrupt stops any command at the end of an in·
ternal micro-instruction and generates INTRa when the
specified condition is met. Forced interrupt will wait until
ALU operations in progress are complete (CRC
calculations, compares, etc.)
The user has the option of reading the status register
through program control or using the ORa line with DMA or
interrupt methods. When the Data register is read the ORa
bit in the status register and the ORa line are automatically
reset. A write to the Data register also causes both ORa's
to reset.
More than one condition may be set at a time. If for
example, the READY TO NOT·READY condition (11 = 1)
and the Every Index Pulse (12 = 1) are both set, the
resultant command would be HEX "DA." The "OR" func·
tion is performed so that either a READY TO NOT·READY
or the next Index Pulse will cause an interrupt condition.
The busy bit in the status may be monitored with a user
program to determine when a command is complete, in lieu
of using the INTRa line. When using the INTRa, a busy
status check is not recommended because a read of the
status register to determine the condition of busy will reset
the INTRa line.
The format of the Status Register is shown below:
READ ADDRESS
SEQUENCE
7
o
S7
SO
Status varies according to the type of command executed
as shown in Table 4.
Because of internal sync cycles, certain time delays must
be observed when operating under programmed 110. They
are: (times double when clock = 1 MHz)
\ '
Operation
Next Operation
Delay Req'd.
. FM
I MFM
Write to
Command Reg.
Read Busy Bit
(Status Bit 0)
12,.ts
Write to
Command Reg.
Read Status
Bits 1·7
28,As
Write Any
Register
Read From Diff.
Register
I
I
I
I
I
..
~s
1~s
I
0
I
I
0
:
IBM 3740 FORMAT - 128 BYTES/SECTOR
Shown below is the IBM single·density format with 128
bytes/sector. In order to format a diskette, the user must
issue the Write Track command, and load the data register
with the following values. For every byte to be written, there
is one Data Request.
TYPE III COMMAND
Read Track/Address
226
NUMBER
OF BYTES
40
')\
6"
t '//
... _" ~_
~
1
issue the Write Track command and load the data register
with the following values. For every byte to be written, there
is one data request.
HEX VALUE OF
BYT"E'WRITTEN
FF (or 00)3 ,,'
00 IFC (I ndex Mark)
FF (or 00)
NUMBER
OF BYTES
(~Jd Address Mark)
80
12
Track Number
1
Side Number (OOor01)
t' j Sector Number (1 thru 1A)
1 ,- ,~Secto[ Length)
l~(. "t If, t F7 (2 CRC's written) 11 ,:~;Z.' FF (or 00)
6,
1 ;, FB (Data Address Mark)
Data (IBM uses ES)
1'
F7 (2 CRC's written)
___ ~
FF (or 00)
-~,;Il 2472
FF (or 00)
HEX VALUE OF
BYTE WRITTEN
4E
00
3
F6 (Writes C2)
FC (Index Mark)
l~* 50
4E
00
12
3
FS (Writes A 1)
1
FE (ID Address Mark)
1
Track Number (0 thru 4C)
1 (,' Side Number (0 or 1)
1
Sector Number (1 thru 1A)
1
01 (Sector Length)
1 .'
F7 (2 CRCs written)
22 'C, 4E
12
00
,
3
FS (Writes A1)
1,
FB (Data Address Mark)
256 ' ; -: DATA
1,- , ", F7 (2 CRCs written)
i
54 ~;!
4E
:', ~ ,'I
S98*i:,~ ,4E
'
!
1
{---
PO
PU
RCLK
vssC
--'"
10
11
ROD
WG
--
EARLY
--
LATE
Iff
LATCH
DECODE
J
PRECOMP
LOGIC
E
L
N
f
WDOUT
I
Figure 2 WD1691 BLOCK DIAGRAM
Figure 1 WD1691 PIN CONNECTIONS
233
WDIN
STB
c
.....
0')
co
.....
PIN
FUNCTION
SYMBOL
NAME
1
WRITE DATA
INPUT
WDIN
Ties directly to the FD179X WD pin.
2, 3, 4, 19
PHASE
2,3,1,4
@"200(b1(li4
4 Phase inputs to generate a desired Write Precompensation
delay. These signals tie directly to the WD2143 Clock
Generator.
5
STROBE
STB
Strobe output from the 1691. Strobe will latch at a high level
on the leading edge of WDIN and reset to a low level on the
leading edge of 04.
6
WRITE DATA
OUTPUT
WDOUT
Serial, pre-compensated Write data stream to be sent to the
disk drive's WD line.
7
WRITE GATE
WG
Ties directly to the FD179X WG pin.
8
VFO ENABLE/
WRITE FAULT
-VFOE/WF
Ties directly to the FD179X VFOE/WF pin.
9
TRACK 43
TG43
---
Ties directly to the FD179X TG43 pin, If Write Precompensation is required on TRACKS 44-76.
10
VSS
11
READ DATA
-ROD
12
READ CLOCK
RCLK
RCLK signal generated by the WD1691, to be tied to the
FD179X RCLK pin.
13
PUMP UP
PU
Tri-state output that will be forced high when the WD1691
requires an increase in VCO frequency.
14
PUMP DOWN
PO
Tri-state output that will be forced low when the WD1691 required a decrease in VCO frequency.
15
Double Density
Enable
16
Voltage
Controlled
Oscillator
VCO
A nominal 4.0MHz (8/1 drive) or 2.0MHz (5.25/1 drive) master
clock input.
17, 18
EARLY
LATE
EARLY
LATE
EARLY and LATE signals from the FD179X, used to determine Write Precompensation.
20
VCC
VSS
DO EN
Vee
Ground
Composite clock and data stream input from the drive.
Double Density Select input. When Inactive (High), the VCO
frequency is internally divided by two.
+ 5V
± 10% power supply
I
Table 1 PIN DEFINITIONS
234
I
WG
VFOE/WF
RDD
PU+PD
1
0
0
0
X
1
0
0
X
X
1
0
HI-Z
HI-Z
Hl-Z
Enable
I
I
RCLK
I
-------.,.-..,-i--,UiI
I
I
1
--7----
HI-Z
UI-....!I--:-!--;---::
I
---'!~LJi-~!~---I
:
i
I
I
Figure 3
I
:
I
U
:ec
...L
PU
HI-Z
HI-Z
Figure 4
DATA RECOVERY LOGIC
HI-Z
HI-Z
I'
I!
PUMP SIGNAL TIMING DIAGRAM
Low, the PU or PD signals will become active. See Figure
4. If theRDD line has made its transition in the beginning of
the RCLK window, PU will go from a HI-Z state to a Logic
I, requesting an increase in VCO frequency. If the RDD line
has made its transition at the end of the RCLK window, PU
will remain in a HI-Z state while PD will go to a logic zero,
requesting a decrease in VCO frequency. When the leading
edge ofROl) occurs in the center of the RCLK window, both
PU andPD will remain tri-stated, indicating that no adjustment of the VCO frequency is needed. See Figure 3. The
RCLK signal is a divide-by-16 (DDEN=1) or a divide-by-8
(DDEN=O) of the VCO frequency.
The minimum Voh level on PU is specified at 2AV, sourcing 200ua. During PUMP UP time, this output will go from a
tri-state to AV minimum. By tying PU and PD together, a
PUMP signal is created that will be forced low for a decrease
in VCO frequency and forced high for an increase in VCO
frequency. To speed up rise times and stabilize the output
voltage, .a resistor divider can be used to set the tristate level
to approximately 1AV. This yields a worst case swing of
± 1V; acceptable for most VCO chips with a linear voltageto-frequency characteristic.
Both PU and PD signals are affected by the width of the
RAW READ (RDD) pulse. The wider the RAW READ pulse,
the longer the PU or PD signal (depending upon the phase
relationship to RCLK) will remain active. If the RAW READ
pulse exceeds 250ns, (VCO = 4MHz, DDEN = 0) or 500ns.
(VCO = 2MHz, DDEN = 1), then both a PU and PD will occur
in the same window. This is undesirable and reduces the
accuracy of the external integrator or low-pass filter to convert the PUMP signals into a slow moving D.C. correction
voltage.
Eventually, the PUMP signals will have corrected the VCO
input to exactly the same frequency multiple as the RAW
READ signal. The leading edge of the RAW READ pulse will
then occur in the exact center of the RCLK window, an ideal
condition for the FD179X internal recovery circuits.
DEVICE DESCRIPTION
The WD1691 is divided into two sections:
1) Data Recovery Ci rcuit
2) Write precompensation Circuit
The Data Separator or Recovery Circuit has four inputs:
-ODEN, VCO,' RDD, and VFOE/WF; and three outputs: PU,
PD and RCLK. The VFOE/WF input is used in conjunction
with the Write Gate signal to enable the Data recovery circuit.
When Write Gate is high, a write operation is taking place,
and the data recovery circuits are disabled, regardless of the
state on any other inputs.
.
The Write Precompensation circuit has been designed to
be used with the WD2143-03 clock generator. When the
WD1691 is operated in a "single density only" mode, write
precompensation as well as the WD2143-03 is not needed.
In this case,"¢,f. 1>2, 1>3, 1>4, and STB should be tied together,
DDEN left open, and TG43, WDIN, Early, and Late tied to
nround.
__
In the double-density mode (DDEN=O), the signals Early
and Late are used to select a phase input (1)1 - 1>4) on the
leading edge of WDIN. The STB line is latched high when
this occurs, causing the WD2143-03 to start its pulse generation. 1>2 is used as the write data pulse on nominal
(Early=Late=1»,¢1 is used for early, and 1>3 is used for late.
The leading edge of 1>4 resets the STB line in anticipation
of the next write data pulse. When TG43=0 or DDEN=1,
Precompensation is disabled and any transitions on the WDIN
line will appear on the WDout line. If write precompensation
is desired on all tracks, leave TG43 open (an internal pull-up
will force a Logic I) while DDEN=O.
The signals, DDEN, TG43, and RDD have internal pull-up
resistors and may be left open if a logic I is desired on any of
these lines.
When VFOE/WF and WRITE GATE are low, the data recovery circuit is enabled. When the RDD line goes Active
235
0')
CO
...L
SPECIFICATIONS
~
C
....
fB
....
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias ........... -25° to 70°C
Voltage on any pin with respect
to Ground (vss) ........................... -0.2 to + 7V
Power Dissipation .................................. 1W
DC ELECTRICAL CHARACTERISTICS
TA = 0 to 70°C; VCC = 5.0V ± 10%; VSS = OV
SYMBOL
PARAMETER
MIN
VIL
Input Low Voltage
-0.2
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
Storage Temp.-Ceramic-65°C to + 150°C
Plastic-55°C to + 125°C
NOTE: Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits is not intended and should be limited to those conditions specified in
the DC Electrical characteristics.
+O.B
V
V
+0.45
VOH
High Level Output Voltage
2.4
Vee
Supply Voltage
4.5
lee
Supply Current
TEST CONDITIONS
UNIT
MAX
TYP
V
IOL=3.2MA
V
IOH=-200p,a
5.0
5.5
V
40
100
MA
All outputs open
NOTE: For AC and functional testing purposes, a Logic '0' is measured at O.BV, and a Logic '1' at 2.0V.
AC ELECTRICAL CHARACTERISTICS
T A = 0° to 70°C; Vee = 5V ± 10%; Vss = OV
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
.5
4
6
MHz
DDEN=O
.5
2
6
MHz
DDEN=1
100
200
FIN
VCO Input Frequency
Rpw
ROD Pulse Width
Wei
EARLY (LATE) to WDIN
100
P on
PUMP UP/ON Time
Wpi
WDIN to WDOUT
Inr
Internal Pull-up Resistor
ns.
ns.
0
4.0
6.5
250
ns.
BO
ns.
10
KO
I
'-Vee
FIN
DDEN=1
I
~
veo
PINS
1 - - - - + - - - - - ; - - - - 8,9, 11, 15
u
RDD
only
I
~I
ReLK~
I
I~
URpw
--II
L - -_ _
.......
- - - - - - Veo -;- 16
Figure 6
Figure 5 INTERNAL PULL-UP RESISTOR
236
ROD AND RCLK PULSE DIAGRAMS
Wei
WDIN
~
---.
........ 11-
:n
n
I
EARLY
n
Wpw
n
LATE
@1
iD2
00
0i4
STS
WDOUT
NOM
EARLY
LATE
NOM
TG43 = "1"
DDEN =, "0"
Figure 7 WRITE DATA TIMING (MFM)
WDIN
WDOUT
-n
04----
Wpw
I
n
1
:n
:'1
II
II
II
---to'11_
TG43 = "0"
DDEN = "1"
Figure 8 WRITE DATA TIMING (FM)
237
Wpi
:e
c
.....
m
.....
C
==
.....
en
RAW
DATA
1771-01
CD
.....
25
1691
ROD
RCLK
11
XTDS
74LS08
12
27
26
FDDATA
FDCLOCK
N.C.
Figure 9 WD1691 to FD1771-01 INTERFACE
TYPICAL APPLICATIONS
tiometer for 1.4V on pin 2 of the 74S124. Then adjust the
range control to yield 4.0MHZ on pin 7 of the 74S124.
Figure 9 illustrates the 1691 to FD1771-01 floppy disk controller. The RCLK signal is used to gate the RAW data pulses
which are inverted by the 74LS04 inverter. Since RCLK will
be high during data and low during clock a 74LS08 is used
to switch the proper clock or data pulse to the FD1771.
Shown in Figure 10 is a Phase-Lock Loop data separator
and the support logic for a single and double-density 8" drive.
The raw data (Both clock and data bits) are fed to the
WD1691 and FD179X. The WD1691 outputs its PU or PD
signal, which is integrated by the .33uf capacitor and 330hm
resistor to form a control voltage for the 74S124 VCO device.
The 4.0MHZ nominal output of the VCO then feeds back to
the WD1691 completing the loop. The WD2143-03 is also
used, providing write precompensation when in double-density, from tracks 44-77. The DDEN line can either be controlled by a toggle switch or a logic level from the host
system.
SUBSTITUTING VCO's
There are other VCO circuits available that may be substituted for the 74S124. The specifications required are:
1) The VCO must free run at 4.0MHz with a 1.4V control
signal. The WD1691 will force this voltage 1 Volt in
either direction (i.e., .4V = decrease frequency, 2.4V
= increase frequency). If a ± 15% capture range is
desired, then a 1 Volt change on the VCO input should
change the frequency by 15%. Capture range should
be limited to about ± 25%, to prevent the VCO from
breaking into oscillation and/or losing lock because of
noise spikes (causing abnormally quick adjustments of
the VCO frequency). Jitter in the VCO output frequency
may further be reduced by increasing the integration
capacitor/resistor, but this will also decrease the final
capture range and lock-up time.
ALIGNMENT
2) The sink output current of the WD1691 is 3.2ma minimum. The source output current is -200ua. Therefore,
source current is the limiting factor. Insure that the input
circuitry of the VCO does not require source current in
excess of -200ua.
To adjust write precompensation, issue a command to
the FD179X so that write data pulses are present. T~can
be done with a 'WRITE TRACK' command and the IP line
open, or a continuous 'WRITE SECTOR' operation. With a
scope on pin 4 of the WD1691, adjust the precomp pot for
the desired value. This will range from 100 to 300 ns typically.
The pulse width set on pin 4 (.01) will be the desired precomp delay from nominal.
Another alternative is to use a voltage follower/level
shifter circuit to match the input requirements of the VCO
chosen. A more complex filter can be used to convert the
PUMP UP/PUMP DOWN pulses to the varying DC voltage
signal required by the VCO, achieving an optimum condition
between lock-up time and high frequency rejection.
--I.h.!L9,ata separator must be adjusted with the RDD or
VFOE/WF line at a Logic I. Adjust the bias voltage poten-
238
en
m
"0
~
CD
-
j:j
+- 200 NS
:!:
25
I
NOTE 4
II
CJ1
Q
RAW DATA
FROM DRIVE
o
~
271 RAW READ
+5
a.
I SINGLE
~
.,~ DENSITY
::J
• "?DOUBLE
-bDENSITY
5'
eo
0'
FD179X
~
+5V
3
+5
ao·
?
50K
(,.)
4.0MHZ
111 VCO
11
I
3
74LS629 12
or
FC
S124
RNG
VCC
WDOUT
I ~
C2
F2
-=I\)
4
Cli
~~
+5V
~
ROD
co
~
E
WD
14 PO
5 ___
47K
RCLK
WG
ADJ
~LY~
LATE
18
LATE
TG43
~
TG43
:-==
8
EARLY
VFOEJWF
1-
!M
19
-=+12V
11
I
DoEN
15
12
7
WDIN
BIAS 1~
VOLTAGE ~
13 PU
8f6T
RCLK I
~ CLK,MR
WD1691 WG
+5V
4~
DDEN
li
CPU
INTERFACE
-t:
WPRT
r----=1 ___
-35
IP
04 03 02 01
STBIN
WD2143-03
I 9
PPW
VSS
1) ALL RESISTORS 'I.W :!: 5%
2) SPECIFICATIONS =
2K
CAPTURE RANGE: :!:2O"/o
LOCK-UP TIME: 25jLS9C
PRECOMPADJ
(ALL ONE'S PATTERN, MFM)
10K
3) FOR 5 1/4"
8
.68p.' -.33p.1
Figure 10
68{l
33!l
8" SINGLE/DOUBLE DENSITY FLOPPY INTERFACE
82Pf
47Pf
4) ROD = ONE EIGHTH RCLK WIDTH MAXIMUM
250ns for 4MHz
AXlns lor 2MHz
-=-
16
15
DIRC
STEP
TROO~
READY
FROM
DRIVE
32
~69U]M
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
240
Printed In USA
WESTERN DIGITAL
c
o
R
o
p
R
A
T
o
/
N
DM1883A/B' Direct Memory Access Controller
fEATURES
It
It
It
It
It
..
..
..
It
It
It
It
It
It
It
It
It
It
It
GENERAL DESCRIPTION
AUTOMATIC DAISY CHAINING OF BUS AND
INTERRUPT ACKNOWLEDGE SIGNALS
AUTO LOAD OPTION
SINGLE +5 VDC POWER SUPPLY
8 BIT BI-DIRECTIONAL DATA BUS
TRUE OR COMPLEMENT DATA BUS
8 C.PU ADDRESSABLE DMAC REGISTERS
8 CPU ADDRESSABLE DEVICE REGISTERS
AUTOMATIC GENERATION OF DEVICE CS
DURING DMA AND CPU DEVICE ACCESSES
256K MEMORY ADDRESSING
64K PROGRAMMABLE PAGE PROTECTION
BYTE OR WORD DMA TRANSFERS
INTERRUPT AND BUS REQUEST CAPABILITIES
END-OF-BLOCK SHUT OFF BY DMAC
TIME-OUT INTERRUPT CAPABILITY
SINGLE CLOCK INPUT
CS, RE, WE, AO-A3 ADDRESSING
STOP REQUEST INPUT TO DELAY INTERRUPT OR BUS REQUESTS
COMPATIBLE WITH OUR FLOPPY DISC
CONTROLLERS
8 BIT PROGRAMMABLE INTERRUPT
IDCODE
AE8
VSS
DRO
REPLY
BACKi
A3
BUSR
cs
BACKo
5CS
RE
MR
DAL7
DAL6
The DM1883 Direct Memory Access Controller
(DMAC) is packaged in a 40 pin standard dual inline package. The chip requires a single +5 power
supply input and a single clock input. The device
contains 8 CPU addressable registers, and allows
for up to 8 CPU addressable device registers if the
automatic device chip select feature is used. Byte or
word transfers can be programmed, and all memory
DMA operations are handshaked for compatibility
with a variety of bus structures. Up to 256K bytes of
memory can be accessed directly with 64K page
protection and nonexistent memory interrupt as
options. Bus and Interrupt Acknowledge signals are
internally daisy chained, and a STOP REQUEST
input prevents new requests while a current request
is active. Device accesses are not handshaked, and
a BUS HOLD feature is present for high speed
devices. Device interrupt input, end-of-block
output, and 110 read/write output pins simplify
hardware interfacing to the device and the CPU bus.
The AUTO LOAD feature allows automatic bootloading of up to 64K bytes or words into memory
starting at location zero. An 8 bit interrupt 10 code is
also provided.
DAL5
DAL4
INTR
DINTR
EOB
AUTLD
BOW
DALD
DAL1
DAl2
DAL3
DAL4
DAL5
DAL6
DAL7
AEB
TDB
A1
AD
ViI
Si'Qi5R
iACKl
A2
IAGKO
VGG(+5)
PIN CONNECTIONS
DM1883 BLOCK DIAGRAM
.
241
DAL3
DAL2
DAL1
DALO
INTERFACE SIGNALS DESCRIPTIONS
PIN
NUMBER
SIGNAL NAME
FUNCTION
SYMBOL
1
GROUND
VSS
Ground
2
DATA REQUEST
DRQ
Data service request input from the peripheral device. A
DMA transfer is initiated when this signal goes high.
3
REPLY
REPLY
Active low bi-directional handshake signal for both CPU
and DMA transfers.
4
BACK IN
BACKI
Bus acknowledge in. An active low input signal from the
CPU or a previous device in the BACien
DMAC
1883
+5
Q..
-.-5
MR
CS
DINTR
INTR
ORO
ORO
WE
WE
RE
RE
ClK
FDC
1771
1781
179X
AO
MR
DMAIP
ClK
7404
WE
\
r
I
,....---..... DMAIP
I~ I~ I~ @I~
DCS
CS
DMAIP
L
"'EiDS"R
DMAIP
---,
DMAREO
8097
CS
CONTROL BUS
TYPICAL DMAC TO FOC APPLICATION
247
Once an interrupt condition sets its corresponding
bit in the status register the bit stays set until a CPU
write to the status register occurs with a zero in the
bit position." If anyone (or more) of the three interrupt condition bits in the Status Register is set then
IACKI will not be gated out to IACKO even if the
interrupt is not enabled.
by a MASTER RESET and loaded by the program
during system initialization, can be used by the
system to create a JUMP or VECTOR address for the
device interrupt routine. Note tha~active CS
during a DMAC select via an active IACKI will cause
unspecified results. Note also that no condition can
activate INTR unless its corresponding enable bit is
set and STOPR is high. If STOPR is active when the
interrupt condition occurs then the DMAC will hold
INTR inactive until STOPR goes inactive. At that
time the DMAC will activate INTR automatically.
NOTE: For a transfer-count-equals-zero interrupt condition to be
cleared the Transfer Count Register must be loaded with
a non-zero count.
The three interrupt conditions are as follows:
DMA PRIORITY SYSTEMS
Fixed Priority
1.) DEVICE INTERRUPT (DINT)
A device interrupt condition occurs when the
DINTR input is made ~ This sets SR1 and, if
CR1 is set, it activates INTA. The RUN bit is also
reset thus terminating all subsequent DMA
transfers. A device interrupt could be generated
by a number of causes, and the program will
have to test the device's Status Reg ister to determine the cause of the interrupt. The DINT status
bit in the DMAC Status Register must be cleared
by the program as a part of the interrupt service
routine.
A fixed priority can be established in two ways:
through a parallel request-grant system or through
a CPU controlled daisy chain system. A typical
asynchronous parallel DMA priority system is
shown. In this system any request generates an
active STOPR, which is gated to all devices, and an
active DMA request to the CPU. The CPU DMA
grant generates a grant to the requesting device
with the highest priority. If more than one request is
received at the same time then the grants are
honored from the highest to the lowest priority. In
most cases, however, grants are not received simultaneously. The highest priority devices, therefore,
will receive most of the immediate grants with the
others being delayed by an active STOPA.
2.) TRANSFER COUNT EQUALS ZERO
INTERRUPT (TCZI)
When the TCR is incremented to zero after a
DMA transfer the TCZI status bit (SR3) is set and
the RtJN bit (CRO) is reset. This terminates all
DMA operations and, if CR3 is set, activates
INTA. SR3 can be cleared only by loading a nonzero value into the TCA. The EOB output pin is
high whenever SR3 is set.
REQUEST
I N PUTS r----L.;.;'---,
Si'OPR
DMi'iJ!r0 4
(TO ALL DMACs)
DMAR1
_ _ 32
GRANT
r - - - - - - , 7OUTPUTS
__
DMAR2
_1
DMAR3
6MAR4 13
12
DMAR5
11
3.) TIME-OUT INTERRUPT (TOI)
During any DMA transfer the leading edge of
MSYNC triggers an internal time delay of
approximately 5 microseconds. If the DMAC
does not receive an active low REPLY input
within that time delay then the DMA operation is
terminated, the RUN bit is reset, and the Tal
status bit (SR2) is set. If CR2 is set then INTR is
activated. SR2 can only be cleared by writing a
zero into that position of the Status Register.
6MAR6
DMiiR7
74138
.5V
10
L...---r--...J
5.8
DMA GRANT
(FROM CPU)
6.16
4
5.8
9 ~O
10 DMAG1
__
DMAG2
11 DMAG3
12 _ _
DMAG4
_
13 _
14~5
DMAG6
15 _
_
DMAG7
ASYNCHRONOUS PARALLEL
DMA PRIORITY SYSTEM
Establishing a fixed priority system through a daisy
chain approach requires the CPU monitor a "DMA
IN PROGRESS" signal on the bus. This signal can
be generated from DCS during a DMA transfer (i.e.,
DCS·CS). In this mode the CPU activates BACKI
and STOPR in response to some bus request.
STOPR is tied to all DMA controllers to prevent new
bus requests while BACKI is propagating through
all non-requesting DMAC devices. When the
requesting DMAC gains control over the bus and
activates DCS the CPU drops BACKI". When DCS is
deactivated the CPU deactivates STOPR to allow
new requests. In this manner the device phYSically
INTERRUPT OPERATION
When the DMAC activates INTR the CPU responds
by activating lACK!. This signal can be daisy
chained through all devices. The first device in the
chain that has any bit in SR1-SR3 set will block the
gating of IACKI out to IACKO. In addition, if INTR is
active an IACKI will select the DMAC. An active RE
after an IACKI select will gate the contents of the
interrupt ID code register onto the DAL lines. The ID
code stays active on the DAL lines as long as IACKI
and RE are active. This code, which is cleared to zero
248
closest to the CPU on the daisy chain has highest
priority for all request cycles.
the last DMAC in the chain goes back to the CPU to
reset its BACKI output. In this mode the first device
cannot request again until all other requesting
devices in the chain have also been serviced.
NOTE: BACKI and STOPR can be dropped at the same time with
no effect on the priority scheme, but the CPU may have
to capture new requests until /jCS goes high.
In any case, if the CPU has to have the DMA request
held active throughout the DMA cycle then the user
will have to create this signal on the controller thusly:
DMAREQ = BUSR + (DCS·CS). If the device and
DMAC chip selects are generated on the controller
separately then the CS can be eliminated from the
equation. It is needed only to distinguish a CPU chip
select from a DMA cycle chip select. Note that in
either case the second term in theequation isequivalent to "DMA CYCLE IN PROGRESS" (DMAIP).
Rotating Priority
This is a daisy chain approach that prevents one
device from getting most of the bus grants if multiple
devices are active at the same time. In this mode any
device requesting the bus causes the CPU to activate
BACKI. This signal is tied to the BACKI and STOPR
inputs of the first DMAC. The BACKO output of the
first DMAC goes to the BACKI and STOPR inputs of
the second DMAC, and so on. The BACKO output of
SPECIFICATIONS
Absolute Maximum Ratings
Ambient Temperature Under Bias ... 0° C to +70° C
Voltage on Any Pin with Respect
to Ground ........................ -0.5V to +7V
Power Dissipation ...................... 0.6 Watt
NOTE: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these
limits is not intended and should be limited to those conditions specified under dc electrical characteristics.
DC Electrical Characteristics
TA = O°C to +70°C; VCC = 5.0V ±5%; GND =OV
--~~---~-.
r----
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT TEST CONDITIONS
-~
Input Low Voltage
--0.5
0.8
V
VIH
Input High Voltage
2.4
VOL
Output Low Voltage
VCC
0.45
V
10L
VOH
Output High Voltage
V
10H = -100 JJA
V,L
'DL
',L
2.4
=
1.6 mA
Data Bus Leakage
-50
10
)JA
)JA
V IN = 0.45V
VIN = VCC
Input Leakage
10
)JA
VIN = VCC
90
mA
Power Supply Current
ICC
V
45
--~--.~---
NOTE: VOL
~~O.4V
_._-
when interfacing with low power Schottky parts (lOL <1 mAl
Capacitance
TA = 25°C; VCC = GND = OV
--
SYMBOL.
PARAMETER
MIN.
TYP.
MAX.
UNIT TEST CONDITIONS
= 1 MHz
C,N
Input Capacitance
10
pF
fC
C,iO
1/0 Capacitance
20
pF
Unmeasured pins
returned to GND.
System Clock (ClK) Characteristics
Maximum Frequency
Minimum Pulse Width
Maximum Pulse Width
= 2.0 MHz
= 250 ns
= 50% of duty cycle
249
c
3:
.....
I
00
00
R
W
E
~
TAR
ADDRESS BUS
-I
1._
1TCR_J
CS
--J
~-
----4
PW
¢3
4PW
3
3PW
2
2PW
2
1PW
¢1
NC
1
GND
STBIN
NC
PIN CONNECTIONS
Figure 1 WD2143-03 PIN CONNECTIONS AND BLOCK DIAGRAM
DEVICE OPERATION
STROBE IN (pin 11) is driven by a TTL square wave. Each of
the four phase outputs provide both true and inverted
signals, capable of driving 1 TTL load each.
Each of the phase outputs can be controlled individually by
typing an external resistor from (/>1 PW-¢4PW to a +5V supply. When it is desired to have ¢1 through ¢4 outputs the
same width, the (/>1 PW-(/>4PW inputs should be left open and
an external resistor tied from the ¢PW (Pin 17) input to
+12V.
253
PIN NUMBER
DESCRIPTION
SYMBOL
1,3,5,7
-;j;1-qA
Four phase clock outputs. These outputs are inverted (active low).
2,4,6,8
l/J1-l/J4
Four Phase clock outputs. These outputs are true (active high).
9
GND
Ground
10
NC
No connection
11
STB IN
Input signal to initiate four-phase clock outputs.
12
NC
No connection
13-16
l/J1PW-l/J4PW
External resistor inputs to control the individual pulse widths of each output.
These pins can be left open if l/JPW is used.
17
l/JPW
External resistor input to control all phase outputs to the same pulse widths.
18
Vee
+ 5V ± 5% powor supply input
Table 1
PIN DESCRIPTIONS
TY~CALAPPUCAnONS
Oi
4
0;
2
00
iii
19
STBIN
3
WD1691
WD2143-03
STS
2K
Figure 2 WRITE PRECOMP OPERATION WITH F.S.L.
WD1691
Figure 3
TTL SQUARE WAVE OPERATION
+5
+12
~
11
13
11
2K
10K
STS IN
8
01PW
"'1
"'1
02PW
"'2
cb2
03PW
"'3
,1>3
04PW
"'4
,1>4
STS IN
17
WD2143-03 ,b1
,b1
"'2
,b2
,bPW
WD2143-03
,b3
"'3
,b4
14
2
15
,b4
16
10K
Figure 4
EQUAL PULSE WIDTH OUTPUTS
Figure 5
254
INDIVIDUAL PULSE WIDTH OUTPUTS
_------...tL
t_ _
f_
- S_ -
'" ---:;;t
I- tpD
7~
1'----------------------
-----JI~tpw
'h'--~
----------~~-----------------
P,eComp
""----/
AOJu<;(
----------------~-----------
"---/
Figure 6
WRITE PRECOMP FOR FLOPPY DISK
----------------------~-----," ----------------------.."----1
Figure 7
WD2143·03 TIMING DIAGRAM
SPECIFICATIONS
Absolute Maximum Ratings
Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits
is not intended and should be limited to the DC electrical characteristics specified.
Operating Temperature
Voltage on any pin with
respect to Ground"
-0.5 to +7V
* Pin 17 = --0.5V to
+ 12V.
Increasing voltage on Pin 17 will
decrease T pw.
Power Dissipation
Storage Temperature
1 Watt
plastic
- 55° to
ceramic - 65° to
+ 125° C
+ 150°C
DC ELECTRICAL CHARACTERISTICS
Vcc = 5V ± 5%, GND = OV, TA = 0° to 70°C.
SYMBOL
PARAMETER
VOL
TTL low level output
VOH
TTL high level output
VIL
STB in low voltage
VIH
STB in high voltage
iCC
Supply Current
MIN.
MAX.
UNITS
CONDITIONS
0.4
V
iOL = 1.6mA
2_0
V
0.8
2.4
V
mA
DC ELECTRICAL CHARACTERISTICS
255
= -100IJA
V
80
Table 2
iOH
All outputs open
SWITCHING CHARACTERISTICS
::e
Vcc =5V ± 5%, GND = OV TA =00 to 70 0 C
C
I\)
...&.
,t.
w
6
SYMBOL
PARAMETER
MIN.
MAX.
UNITS
140
ns
CONDITIONS
w
tPD
STB IN t001
tpw
Pulse Width (any output)
300
ns
tPR
Rise Time (any output)
30
ns
tPF
Fall Time (any output)
25
ns
fS
STROBE PULSE WIDTH
1.0
lAS
= 30pf
= 30pf
CL = 30pf
combined tpw = 400 ns
tDPW
Pulse Width Differential
± 10
0/0
Referenced to 01,100·300 ns.
Table 3
100
CL
CL
SWITCHING CHARACTERISTICS
NOTE: Tpw measured at 50% VOH Point; VOL = 0.8V, VOH
=:
2.0V.
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
256
PrInted ,n U S.A
WESTERN DIGITAL
CORPORATION
WD9216·00/WD9216·01
Floppy Disk Data Separator -
•
FDDS
FEATURES
GENERAL DESCRIPTION
• PERFORMS COMPLETE DATA SEPARATION
FUNCTION FOR FLOPPY DISK DRIVES
• SEPARATES FM OR MFM ENCODED DATA
FROM ANY MAGNETIC MEDIA
• ELIMINATES SEVERAL SSI AND MSI DEVICES
NORMALLY USED FOR DATA SEPARATION
• NO CRITICAL ADJUSTMENTS REQUIRED
• COMPATIBLE WITH WESTERN DIGITAL 179X,
176X AND OTHER FLOPPY DISK
CONTROLLERS
• SMALL 8-PIN DUAL-IN-LiNE PACKAGE
• + 5 VOLT ONLY POWER SUPPLY
• TTL COMPATIBLE INPUTS AND OUTPUTS
The Floppy Disk Data Separator provides a low cost
solution to the problem of converting a single stream
of pulses from a floppy disk drive into separate Clock
and Data inputs for a Floppy Disk Controller.
The FDDS consists primarily of a clock divider, a
long-term timing corrector, a short-term timing
corrector, and reclocking circuitry. Supplied in an 8pin Dual-In-Line package to save board real estate,
the FDDS operates on + 5 volts only and is TTL compatible on all inputs and outputs.
The WD9216 is available in two versions; the
WD9216-00, which is intended for 5114" disks and the
WD9216-01 for 5114 " and 8" disks.
PIN CONFIGURATION
REFCLK ---+CDO ----.
- +5V
-GND
CLOCK
DIVIDER
CD1----
DATA/CLOCK
SEPARATION
LOGIC
DSKD ____
PULSE
REGENERATION
LOGIC
EDGE
DETECTION
LOGIC
FLOPPY DISK DATA SEPARATOR BLOCK DIAGRAM
•
257
SEPCLK
SEPo
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS*
Operating Temperature Range ....... O°C to + 70°C
Storage Temperature Range ....... - 55°C to 125°C
Positive Voltage on any Pin,
with respect to ground ................. + 8.0V
Negative Voltage on any Pin,
with respectto ground. . . . . . . . . . . . . . . . . - 0.3V
NOTE: When powering this device from laboratory or
system power supplies, it is important that the
Absolute Maximum Ratings not be exceeded or
device failure can result. Some power supplies
exhibit voltage spikes or "glitches" on their outputs
when the AC power is switched on and off. In addition, voltage transients on the AC power line may
appear on the DC output. If this possibility exists it is
suggested that a clamp circuit be used.
* Stresses above those listed may cause permanent
damage to the device. This is a stress rating only
and functional operation of the device at these or at
any other condition above those indicated in the
operational sections of this specification is not
implied.
OPERATING CHARACTERISTICS (TA = O°C to 70°C, VCC =
MIN.
PARAMETER
D.C. CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low Level VIL
High Level VIH
OUTPUT VOLTAGE LEVELS
Low Level VOL
High Level VOH
INPUT CURRENT
Leakage IlL
INPUT CAPACITANCE
All Inputs
POWER SUPPLY CURRENT
IDD
A.C. CHARACTERISTICS
Symbol
REFCLK Frequency
fCY
REFCLK Frequency
fCY
REFCLK High Time
tCKH
REFCLK Low Time
tCKL
REFCLK to SEPD "ON" Delay
tSDON
tSDOFF REFCLK to SEPD "OFF" Delay
REFCLK to SEPCLK Delay
tSPCK
DSKD Active Low Time
tDLL
DSKD Active High Time
tDLH
+ 5V ± 5%, unless otherwise noted)
TYP.
MAX.
UNITS
0.8
V
V
0.4
V
V
10
JAA
10
pF
50
rnA
4.3
8.3
2500
2500
MHz
MHz
ns
ns
ns
ns
ns
100
100
liS
JAs
2.0
2.4
0.2
0.2
50
50
100
100
100
0.1
0.2
REFCLK
SEPD
SEPCLK -------------------------------------------
DSKD-{tDW-}~
Figure 3.
AC CHARACTERISTICS
258
COMMENTS
IOL
IOH
= 1.6mA
= -1oo1iA
O~VIN ~VDD
WD9216-OO
WD9216-01
•
DESCRIPTION OF PIN FUNCTIONS
PIN
NUMBER
PIN NAME
SYMBOL
1
Disk Data
DSKD
2
Separated Clock
SEPCLK
3
4
5,6
Reference Clock
Ground
Clock Divisor
REFCLK
GND
CDO,CD1
Separated Data
Power Supply
SEPD
7
8
FUNCTION
Data input signal direct from disk drive. Contains combined clock and data waveform.
Clock signal output from the FDDS derived
from floppy disk drive serial bit stream.
Reference clock input.
Ground.
COO and CD1 control the internal clock divider
circuit. The internal clock is a submultiple of the
REFCLK according to the following table:
CD1
COO
Divisor
1
0
0
1
2
0
0
4
1
1
1
8
SEPD is the data output of the FDDS
+ 5 volt power supply
VCC
4 M Hz CRYSTAL
OSCILLATOR
J
·1
REFCLK
FLOPPY
DISK
DRIVE
SEPD
+4
I
REGENERATED DATA
DISK DATA
DSKD
WD9216-00,01
SEPCLK
CD1
1MHz
I
DERIVED CLOCK
COO
l
CLK
RAW READ
WD179X, 176X or Equiv.
FLOPPY DISK
CONTROLLER
RCLK
+ GND
+
GND
Figure 1.
TYPICAL SYSTEM CONFIGURATION
(5114 " Drive, Double Density)
Separate short and long term timing correctors
assure accurate clock separation.
The internal clock frequency is nominally 16 times
the SEPCLK frequency. Depending on the internal
timing correction, the internal clock may be a
minimum of 12 times to a maximum of 22 times the
SEPCLK frequency.
The reference clock (REFCLK) is divided to provide
the internal clock according to pins COO and CD1.
OPERATION
A reference clock (REFCLK) of between 2 and 8 MHz
is divided by the FDDS to provide an internal clock.
The division ratio is selected by inputs COO and CD1.
The reference clock and division ratio should be
chosen per table 1.
The FDDS detects the leading edges of the disk data
pulses and adjusts the phase of the internal clock to
provide the SEPARATED CLOCK output.
259
TABLE 1:
CLOCK DIVIDER SELECTION TABLE
DRIVE
(8" or 5%")
DENSITY
(DO or SO)
REFCLK
MHz
CD1
COO
8
8
8
DO
SO
SO
8
8
4
0
0
0
0
0
5V4
5%
DO
DO
8
4
0
0
0
5%
5%
5V4
SO
SO
SO
8
4
2
1
0
0
0
0
1
1
1
REMARKS
}
}
}
Select either one
Select either one
Select anyone
INTCLK
~_________________J
SEPCLK
-1
SEPD --------~LJ~------------~LI------------------~LJ~---------------I
I
I
W
always two internal clock cycles
Figure 2.
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However. no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rl'Jhts of third parties which may result from its use. No license Is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
260
Pronted in U.S.A
CRT Controllers
Part Number
WD8275
WD8276
::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::p;
261
262
WESTERN DIGITAL
c
o
R
o
p
R
A
T
/
o
N
WD8275 Programmable CRT Controller'
FEATURES
• PROGRAMMABLE SCREEN AND CHARACTER
FORMAT
GENERAL DESCRIPTION
The WD8275 Programmable CRT Controller is a
single chip device to Interface CRT raster scan
displays with microcomputer systems. Its primary
function is to refresh the display by buffering the
information from main memory and keeping track of
the display position of the screen. The flexibility
designed into the WD8275 will allow simple interface
to almost any raster scan CRT display with a minimum of external hardware and software overhead.
• 6 INDEPENDENT VISUAL FIELD ATTRIBUTES
• 11 VISUAL CHARACTER ATTRIBUTES (GRAPHIC
CAPABI LlTY)
• CURSOR CONTROL (4 TYPES)
• LIGHT PEN DETECTION AND REGISTERS
• DUAL ROW BUFFERS
• PROGRAMMABLE DMA BURST MODE
• SINGLE + 5V SUPPLY
• 40-PIN PACKAGE
CHARACTER
COUNTER
LC3
LC2
L. C 1
LCo
DRQ
vcc
LAO
DATA
BUS
BUFFER
CCo·e
RVV
VSP
HRTC
GPA1
VRTC
GPAo
AD
HLGT
DBO
DBO·?
LA1
LTEN
DACK
WR
LPEN
-4---CCLK
IRQ
CCLK
DB1
CCe
CC5
DB2
CC4
DB3
CC3
DB4
DB5
CC2
CC1
DBe
CCo
DB?
C§
GND
AO
DRQ
LCO·3
i5ACK
IRQ
AD
LAO·1
HRTC
VRTC
HLGT
RVV
LTEN
VSP
GPAO.1
WR
AO
cs
LPEN
Figure 1.
Figure 2.
PIN CONFIGURATION
263
BLOCK DIAGRAM
TABLE 1. PIN DESCRIPTIONS
:eC
PIN
NO.
1
2
3
4
00
N
......
CJ1
I
TYPE
PIN NAME
SYMBOL
FUNCTION
Output from the line counter which is used to
address the character generator for the line
positions on the screen.
0
LINE COUNT
5
0
DMAREQUEST
LC3
LC2
LC1
LCO
DRQ
6
I
DMA ACKNOWLEDGE
DACK
7
0
HORIZONTAL
RETRACE
HRTC
8
0
VERTICAL RETRACE
VRTC
9
10
I
I
READ INPUT
WRITE INPUT
RD
WR
11
I
LIGHT PEN
LPEN
12
13
14
15
16
17
18
19
20
21
I/O
BIDIRECTIONAL
THREE-STATE DATA
BUS LINES
DBO
DB1
DB2
DB3
DB4
DB5
DB6
DB7
Ground
The outputs are enabled during a read of the C
or P ports.
AD
A high input on AO selects the "C" port or
command registers and a low input selects the
"P" port or parameter registers.
The read and write are enabled by CS.
Output from the row buffers used for character
selection in the character generator.
I
22
I
23
24
25
26
27
28
29
30
31
32
0
I
0
0
GROUND
PORT ADDRESS
CHIP SELECT
CHARACTER CODES
CHARACTER CLOCK
INTERRUPT REQUEST
HIGHLIGHT
Output signal to the DMA controller
requesting a DMA cycle.
Input signal from the DMA controller
acknowledging that the requested DMA cycle
has been granted.
Output signal which is active during the
programmed horizontal retrace interval. During
this period the VSP output is high and the
LTEN output is low.
Output signal which is active during the
programmed vertical retrace interval. During
this period the VSP output is high and the
LTEN output is low.
A control signal to read registers.
A control signal to write commands into the
control registers or write data into the row
buffers during a DMA cycle.
Input signal from the CRT system signifying
that a light pen signal has been detected.
CS
CCo
CC1
CC2
CC3
CC4
CC5
CC6
CCLK
IRQ
HLGT
From dot/timing logic.
Interrupt request.
Output signal used to intensify the display at
particular positions on the screen as specified
by the character attribute codes or field attribute codes.
264
TABLE 1. PIN DESCRIPTIONS (Continued)
PIN
NO.
TYPE
SYMBOL
FUNCTION
G PA 1
GPAO
VSP
Outputs which are enabled by the general
purpose field attribute codes.
Output signal used to blank the video signal to
the CRT. This output is active:
-during the horizontal and vertical retrace
intervals.
-at the top and bottom lines of rows if underline is programmed to be number 8 or
greater.
-when an end of row or end of screen code is
detected.
-when a DMA underrun occurs.
-at regular intervals (1/16 frame frequency for
cursor, 1132 frame frequency for character
and field attributes) - to create blinking
displays as specified by cursor, character
attribute, or field attribute programming.
Output signal used to indicate the CRT circuitry
to reverse the video signal. This output is active
at the cursor position if a reverse video block
cursor is programmed or at the positions
specified by the field attribute codes.
Output signal used to enable the video signal to
the CRT. This output is active at the
programmed underline cursor position, and at
positions specified by attribute codes.
33
34
35
0
GENERAL PURPOSE
ATTRIBUTE CODES
VIDEO SUPPRESSION
36
0
REVERSE VIDEO
RVV
37
o
LIGHT ENABLE
LTEN
38
o
LINE ATTRIBUTE
CODES
LA1
+ 5V POWER SUPPLY
VCC
39
40
0
PIN NAME
LAo
These attribute codes have to be decoded
externally by the dot/timing logic to generate
the horizontal and vertical line combinations for
the graphic displays specified by the character
attribute codes.
+ 5V power supply.
CPU is reading data or status information from the
WD8275.
FUNCTIONAL DESCRIPTION
Data Bus Buffer
This 3-state, bidirectional, 8-bit buffer is used to
interface the WD8275 to the system Data Bus.
This functional block accepts inputs from the System Control Bus and generates control signals for
overall device operation. It contains the Command,
Parameter, and Status Registers that store the
various control formats for the device functional
definition.
TI
o
o
1
1
OPERATION
REGISTER
Read
Write
Read
Write
PREG
PREG
SREG
CREG
WR(WRITE)
A "low" on this input informs the WD8275 that the
CPU is writing data or control words to the WD8275.
CS (CHIP SELECT)
A "low" on this input selects the WD8275. No reading
or writing will occur unless the device is selected.
When CS is high, the Data Bus in the float state and
RD and WR will have no effect on the chip.
DRQ (DMA REQUEST)
A "high" on this output informs the DMA Controller
that the WD8275 desires a DMA transfer.
DACK (DMA ACKNOWLEDGE)
A "low" on this input informs the WD8275 that a DMA
cycle is in progress.
RD(READ)
A "low" on this input informs the WD8275 that the
265
=e
c00
N
......
en
IRQ (INTERRUPT REQUEST)
Line Counter
A "high" on this output informs the CPU that the
WD8275 desires interrupt service.
The Line Counter is a programmable counter that is
used to determine the number of horizontal lines
(Sweeps) per character row. Its outputs are used to
address the external character generator ROM.
Row Counter
The Row Counter is a programmable counter that is
used to determine the number of character rows to
be displayed per frame and length of the vertical
retrace interval.
DATA
BUS
BUFFER
DBO_7
CCO-6
Light Pen Registers
ORO ~------,
The Light Pen Registers are two registers that store
the contents of the character counter and the row
counter whenever there is a rising edge on the LPEN
(Light Pen) input.
LCO_3
NOTE:
Software correction is required.
AD
WR
AO
READ!
WRITEt
DMA
CONTROL
LOGIC
LAO_l
HRTC
VRTC
HLGT
RVV
LTEN
VSP
GPAO_l
cs
LPEN
DBO_7
DATA
BUS
BUFFER
CCO_6
Figure 3.
WD8275 BLOCK DIAGRAM SHOWING DATA BUS
BUFFER AND READIWRITE FUNCTIONS
ORO ~------,
Ao
RD
\m
CS
0
0
0
1
1
0
1
1
0
1
1
1
0
1
0
0
0
0
0
X
X
1
X
X
Write WD8275 Parameter
Read WD8275 Parameter
Write WD8275 Command
Read WD8275 Status
Three-State
Three-State
LCO_3
AD_
READ!
WRITE!
DMA
CONTROL
AO ---...
LOGIC
WR
cs--~
Character Counter
LAO_l
HRTC
VRTC
HLGT
RVV
LTEN
VSP
GPAO_l
LPEN
The Character Counter is a programmable counter
that is used to determine the number of characters to
be displayed per row and the length of the horizontal
retrace interval. It is driven by the CCLK (Character
Clock) input, which should be a derivative of the
external dot clock.
Figure 4.
WD8275 BLOCK DIAGRAM SHOWING COUNTER
AND REGISTER FUNCTIONS
266
Raster Timing and Video Controls
Buffer Input/Output Controllers
The Raster Timing circuitry controls the timing of the
HRTC (Horizontal Retrace) and VRTC (Vertical
Retrace) outputs. The Video Control circuitry controls
the generation of LAo-1 (Line Attribute), HGLT
(Highlight), RVV (Reverse Video), LTEN (Light Enable),
VSP (Video Suppress), and GPAo-1 (General Purpose
Attribute) outputs.
The Buffer Input/output Controllers decode the
characters being placed In the row buffers. If the
character is a character attribute, field attribute or
special code, these controllers control the appropriate action. (Examples: An "End of Screen-Stop
DMA" special code will cause the Buffer Input
Controller to stop further DMA requests. A
"Highlight" field attribute will cause the Buffer
Output Controller to activate the HGLT output.)
Row Buffers
The Row Buffers are two 8O-character buffers. They
are filled from the microcomputer system memory
with the character codes to be displayed. While one
row buffer is displaying a row of characters, the other
is being filled with the next row of characters.
SYSTEM OPERATION
The WD8275 is programmable to a large number of
different display formats. It provides raster timing,
display row buffering, visual attribute decoding,
cursor timing, and light pen detection.
It is designed to interface with a DMA Controller and
standard character generator ROMs for dot matrix
decoding. Dot level timing must be provided by
external circuitry.
FIFOs
There are two 16 character FIFOs in the WD8275.
They are used to provide extra row buffer length in
the Transparent Attribute Mode (see Detailed Operation section).
I
It;
.
'" DBO_7
?
..
AO
~-7
I!m"
cs
O§
.
HRO
"" HACK
IRO
I-
ORO
DMA
CONTROLLER
U
I
SYSTEM BUS
MEMR
iOW
MEMW
iOR
.
MEMORIES
LCO-3
CHARACTER
GENERATOR
DACK
WD8275
CRT
CONTROLLER
CCo_a
r
CCLK
VIDEO SIGNAL
r
DOT
TIMING
AND
INTERFACE
HORIZONTAL SYNC
VERTICAL SYNC
INTENSITY
VIDEO CONTROLS
Figure 5.
WD8275 SYSTEMS BLOCK DIAGRAM SHOWING SYSTEMS OPERATION
267
GENERAL SYSTEMS OPERATIONAL
DESCRIPTION
The WD8275 provides a "window" into the
microcomputer system memory.
Display characters are retrieved from memory and
displayed on a row-by-row basis. The WD8275 has
two row buffers. While one row buffer is being used
for display, the other is being filled with the next row
of characters to be displayed. The number of display
characters per row and the number of character rows
per frame are software programmable, providing easy
interface to most CRT displays. (See Programming
Section.)
The WD8275 requests DMA to fill the row buffer that
is not being used for display. DMA burst length
and spacing is programmable. (See Programming
Section.)
The WD8275 displays character rows one line at a
time.
The number of lines per character row, the underline
position, and blanking of top and bottom lines are
programmable. (See Programming Section.)
The WD8275 provides special' Control Codes which
can be used to minimize DMA or software overhead.
It also provides Visual Attribute Codes to cause
special action or symbols on ~he screen without the
use of the character generator (see Visual Attributes
Section).
The WD8275 also controls raster timing. This is done
by generating Horizontal Retrace (HRTC) and Vertical
Retrace (VRTC) signals. The timing of these signals
is programmable.
The WD8275 can generate a cursor. Cursor location
and format are programmabl'e. (See Programming
Section.)
The WD8275 has a light pen input and registers. The
light pen input is used to load the registers. Light pen
registers can be read on command. (See Programming Section.)
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
OO • • • • OOO.OO~O.OO • • • • • OOOOOOOOO • • • • OOOO • • • OOO.OOO.O
First Line of a Character Row
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
00 • • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 0 0 0 . 0 0 0 . 0
o.oooO.OO • • O~D.OO.OODOOOOOOODUO.OOO.oO.OOO.OO.DOO.O
Second Line of a Character Row
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
00 • • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 0 0 0 . 0 0 0 . 0
o.ooOO.OTI • • DOO.OO.ooooooooooooo.oOO.OO.ODO.OO.Ooo.o
0.0000.00.0000.00.0000000000000.000.00.000.00.000.0
Third Line of a Character Row
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
~~~,.-I"-.~~~
00 • • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 0 0 0 . 0 0 0 . 0
0.0000.00 • • 0 0 0 . 0 0 . 0 0 0 0 0 0 0 0 0 0 0 0 0 . 0 0 0 . 0 0 . 0 0 0 . 0 0 . 0 0 0 . 0
0.0000.00.0.00.00.0000000000000.000.00.000.00.000.0
o.oooo.oo.oooo.oo • • • • oooooooooO • • • • OOTI.ooO.OO.O.D.O
0.0000.00.00.0.00.0000000000000.0.0000.000.00.0.0.0
0.0000.00.000 •• 00.0000000000000.00.000.000.00.0.0.0
00 • • • • 000.0000.00 • • • • • 000000000.00.0000 • • • 0 0 0 0 . 0 . 0 0
Seventh Line of a Character Row
Figure 6.
DISPLAY OF A CHARACTER ROW
268
DISPLAY ROW BUFFERING
Before the start of a frame, the WD8275 requests
DMA and one row buffer is filled with characters.
After all the lines of the character row are scanned,
the roles of the two row buffers are reversed and the
same procedure is followed for the next row.
DBO·7
CCO·s
DRQ
LCO·3
LCO·3
LAO·1
HATC
VRTC
HLGT
RVV
LTEN
VSP
GPAO·1
AO
cs
LAO·1
HRTC
VRTC
HLGT
RVV
LTEN
vSP
GPAO·1
WRAO -
cs
LPEN
LPEN
Figure 7.
FIRST ROW BUFFER FILLED
Figure 9.
When the first horizontal sweep is started, character
codes are output to the character generator from the
row buffer just filled. Simultaneously, DMA begins
filling the other row buffer with the next row of
characters.
FIRST BUFFER FILLED WITH THIRD ROW,
SECOND ROW DISPLAYED
This is repeated until all of the character rows are
displayed.
DISPLAY FORMAT
DBO·7
Screen Format
The WD8275 can be programmed to generate from 1
to 80 characters per row, and from 1 to 64 rows per
frame.
CCO·s
123456789 .................... 80
2
3
4
5
6
7
8
9
LCO·3
DACK - - - ,
IRQ - ,
Ao~
WR
Ao
t
READI
WRITEI
DMA
CONTROL
LOGIC
LA~.1
HRTC
VRTe
HLGT
RVV
LTEN
VSP
GPAO·1
cs--
64
LPEN
FigureS.
Figure 10.
SECOND BUFFER FILLED,'FIRST ROW DISPLAYED
SCREEN FORMAT
269
The WD8275 can also be programmed to blank
alternate rows. In this mode, the first row is displayed, the second blanked, the third displayed, etc.
DMA is not requested for the blanked rows.
Line
Number
0000000000
10000.0000
2000.0.000
300.000.00
40.00000.0
50.00000.0
123456789 .................... 80
2
6
3
0
••••••• 0
70.00000.0
80.00000.0
90.00000.0
10 0 0 0 0 0 0 0 0 0
11 0 0 0 0 0 0 0 0 0
12 0 0 0 0 0 0 0 0 0
13 0 0 0 0 0 0 0 0 0
14 0 0 0 0 0 0 0 0 0
15 0 0 0 0 0 0 0 0 0
Figure 12.
4
5
6
7
8
9
64
Line
Counter
Mode 0
000
000 1
001 0
001 1
o
o1 0
o1 0
0
1
o1 1 0
Line
Counier
Mode 1
1 1 1 1
000
000 1
001 0
001 1
o
o1
o1
0 0
0 1
011 1 o 1 1 0
1 000
011 1
1 0 0 1 1 000
101 0
101 1
101 0
100 1
1 1 0 0
101 1
1 1 0 0
1 1 1 0 1 101
1 1 1 1 1 1 1 0
1 1 0 1
EXAMPLE OF A 16-LlNE FORMAT
Figure 11.
BLANK ALTERNATE ROWS MODE
Row Fonnat
Line
Number
0
o 0
1
o 0
2
o 0
3
o •
4
o •
5
o •
6
o •
7
o •
8
o 0
9
o 0
The WD8275 Is designed to hold the line count stable
while outputting the appropriate character codes
during each horizontal sweep. The line count is incremented during horizontal retrace and the whole
row of character codes are output again during the
next sweep. This is continued until the entire character row is displayed.
The number of lines (horizontal sweeps) per character row is programmable from 1 to 16.
The output of the line counter can be programmed to
be in one of two modes.
0
0
•
0
0
•
0
0
0
0
0
•
0
0
0
•
0
0
0
0
0 0 0
0 0 0
• 0 0
0 • 0
0 • 0
• • 0
0 • 0
0 • 0
0 0 0
0 0 0
Figure 13.
Line
Counter
Mode 0
000 0
000 1
001 0
001 1
1 0 0
1 0 1
1 1 0
1 1 1
100 0
1 0 0 1
o
o
o
o
Line
Counter
Mode 1
100 1
000
000 1
001 0
001 1
1 0 0
1 0 1
1 1 0
011 1
1 000
o
o
o
o
EXAMPLE OF A 1o.LlNE FORMAT
In mode 0, the output of the line counter is the same
as the line number.
In mode 1, the line counter is offset by one from the
line number.
Mode 0 is useful for character generators that leave
address zero blank and start at address 1. Mode 1 is
useful for character generators which start at address zero.
NOTE:
In mode 1, while the first line (line number 0) is being
displayed, the last count is output by the line counter
(see examples).
Underline, placement is also programmable (from line
number 0 to 15). This is independent of the line
counter mode.
If the line number of the underline is greater than 7
(line number MSB = 1), then the top and bottom
lines will be blanked.
270
Line
Number
0 o
1 o
2 o
3 o
4 o
5 o
6 o
7 o
8 o
9 o
10 •
11 o
Line
Counter
Mode 0
0
o
0
0
0
0
0
0
00.
o
0
0
0
0
0
•
0
•
0
0
0
0
•
0
00.00
•
0
0
0
o
0
•
0
.00 0
0
o •
0
• • • •
• •
• 0 0 0 00.
• 0 o 0 o 0 •
• 0 0 0 00.
0
0
•
0
0
0
••••••••
0
0
0
0
0
0
0
0
000
000
001
o0 1
o1 0
o1 0
o1 1
o1 1
100
100
101
10 1
0
1
0
1
0
1
0
1
0
1
0
1
Line
Counter
Mode 1
101 1
o0 0 0
000 1
001 0
001 1
o1 0 0
o1 0 1
o1 1 0
011 1
1 000
100 1
101 0
VIDEO
Figure 16.
TYPICAL DOT LEVEL BLOCK DIAGRAM
Dot width is a function of dot clock frequency.
Character width is a function of the character generator width.
Top and Bottom
Lines are Blanked
Figure 14.
UNDERLINE IN LINE NUMBER 10
Horizontal character spacing is a function of the shift
register length.
NOTE:
Video control and timing signals must be synchronized with the video signal due to the character
generator access delay.
If the line number of the underline is less than or
equal to 7 (line number MSB = 0), then the top and
bottom lines will not be blanked.
Line
Counter
Mode 0
Line
Number
0
1
2
3
4
5
6
7
o
o
o
o
o
o
o
0
0
0
0
0
0
0
0
•
0
0
0
0
•
0
•
0
0
• 0 00.
• 0 0 0 •
• • • • •
• 0 0 0 •
0
0
0
0
•••••••
Top and Bottom
o0 0
000
001
001
o1 0
o1 0
o1 1
o1 1
Line
Counter
Mode 1
RASTER TIMING
The character counter is driven by the character
clock input (CCLK). It counts out the characters
being displayed (programmable from 1 to 80). It then
causes the line counter to increment, and it starts
counting out the horizontal retrace interval (programmable from 2 to 32). This is constantly repeated.
0 o1 1 1
1 o0 0 0
0 000 1
1 001 0
0 001 1
1 o1 0 0
0 o1 0 1
1 o1 1 0
Lines are not Blanked
Figure 15.
UNDERLINE IN LINE NUMBER 7
CCLK
HRTC
If the line number of the underline is greater than the
maximum number of lines, the underline will not
appear.
Blanking is accomplished by the VSP (Video Suppression) signal. Underline is accomplished by the
LTEN (Light Enable) signal.
LCO-3
PRESENT LINE COUNT
NEXT
LINE COUNT
Figure 17.
LINE TIMING
Dot Format
The line counter is driven by the character counter. It
is used to generate the line address outputs (LCo-3)
for the character generator. After it counts all of the
lines in a character row (programmable from 1 to 16),
it increments the row counter, and starts over again.
(See Character Format Section for detailed description of Line Counter functions.)
Dot width and character width are dependent upon
the external timing and control circuitry.
Dot level timing circuitry should be designed to
accept the parallel output of the character generator
and shift it out serially at the rate required by the CRT
display.
271
=E
c
co
the burst counter. No more DMA requests will occur
until the beginning of the next row. At that time, DMA
requests are activated as programmed until the other
buffer is filled.
The first DMA request for a row will start at the first
character clock of the preceding row. If the burst
mode is used, the first DMA request may occur a
number of character clocks later. This number is
equal to the programmed burst space.
If, for any reason, there is a DMA underrun, a flag in
the status word will be set.
The row counter is an internal counter driven by the
line counter. It controls the functions of the row
buffers and counts the number of character rows
displayed.
N
.....
ONE CHARACTER ROW
c.n
f I '~lhJ
I
HRTC
LCO·3
PRESENT Rb
INTERNAL
ROW COUNTER
~
NEXT~
INTERNAL
ROW·
COUNTER
VRTC
FIRST
~
______
~'I~
________
OISPLAYROW
_______
JP~
-----------E,.....------_
PROGRAMMABLE 1 TO 16
LINE COUNTS
Figure 18.
ORO
ROW TIMING
-------------f,.
~/\.
'-y----'.
NEXT
ROW BUFFER
FILLED
After the row counter counts all of the rows in a
frame (programmable from 1 to 64), it starts counting
out the vertical retrace interval (programmable from 1
to 4).
ONE FRAME
______
________
A~
~6~R~~~NTE0Q<::xxxx:XXX
I of~~tlY
OIS~t~~ ~~RTS:ACE RE'r~~TCE
~ RO~lW:
PROGRAMMABLE
1 TO 64 ROW COUNTS
Figure 20.
\W
DMA TIMING
The DMA controller is typically initialized for the next
frame at the end of the current frame.
PROGRAMMABLE
1 TO 4 ROW COUNTS
INTERRUPT TIMING
The WD8275 can be programmed to generate an
interrupt request at the end of each frame. This can
be used to reinitialize the DMA controller. If the
WD8275 interrupt enable flag is set, an interrupt
request will occur at the beginning of the last display
Figure 19.
FRAME TIMING
The Video Suppression Output (VSP) is active during
horizontal and vertical retrace intervals.
Dot level timing circuitry must synchronize these
outputs with the video signal to the CRT Display.
row.
IRQ will go inactive after the status register is read.
DMATIMING
A reset command will also cause IRQ to go inactive,
but this is not recommended during normal service.
Another method of reinitializing the DMA controller
is to have the DMA controller itself interrupt on
terminal count. With this method, the WD8275 interrupt enable flag should not be set.
NOTE:
Upon power-up, the WD8275 Interrupt Enable Flag
may be set. As a result, the user's cold start routine
should write a reset command to the WD8275 before
system interrupts are enabled.
The WD8275 can be programmed to request burst
DMA transfers of 1 to 8 characters. The interval
between bursts is also programmable (from 0 to 55
character clock periods ± 1). This allows the user to
tailor his DMA overhead to fit his system needs.
The first DMA request of the frame occurs one row
time before the end of vertical retrace. DMA requests
continue as programmed, until the row buffer is
filled. If the row buffer is filled in the middle of a
burst, the WD8275 terminates the burst and resets
272
INTERNAL
the character generator with 7 bits of address. The
Most Significant Bit is the extra bit and it is
used to determine if it is a normal display character
(MSB = 0), or if it is a Visual Attribute or Special
Code (MSB = 1).
There are two types of Visual Attribute Codes. They
are Character Attributes and Field Attributes.
LAST
DISPLAY
ROW
-:::-v---v
ROWCOUNT~
VRTC
~ t----6--..J
Character Attribute Codes
Character attribute codes are codes that can be used
to generate graphics symbols without the use of a
character generator. This is accomplished by selectively activating the Line Attribute outputs (LAO-1),
the Video Suppression output (VSP), and the Light
Enable output. The dot level timing circuitry can use
these signals to generate the proper symbols.
Character attributes can be programmed to blink or
be highlighted individually. Blinking is accomplished
with the Video Suppression 0l1tput (VSP). Blink frequency is equal to the screen refresh frequency
divided by 32. Highlighting is accomplished by activating the Highlight output (HGLT).
IRQ
Figure 21.
BEGINNING OF INTERRUPT REQUEST
Character Attributes
MSB
LSB
1
CCCCBH
I LHighlight
L - Blink
L.....------·Character Attribute
Code
Figure 22.
END OF INTERRUPT REQUEST
VISUAL ATTRIBUTES AND SPECIAL CODES
The characters processed by the WD8275 are 8bit quantities. The character code outputs provide
I
HORIZ. RIGHT
HALF
SHIFT
REGISTER
05~------4-~~~-+__+--+__~~
WD8275
06 ~------4-~~~-+__+--+___L~
OUT
VIDEO
LAO
VSP
Figure 23.
TYPICAL CHARACTER AlTRIBUTE LOGIC
273
TABLE 2.
CHARACTER ATTRIBUTES
Character attributes were designed to produce the following graphics:
CHARACTER ATTRIBUTE
CODE "CCCC"
DESCRIPTION
0000
Top Left Corner
0001
Top Right Corner
0010
Bottom Left Corner
0011
Bottom Right Corner
0100
Top Intersect
0101
Right Intersect
0110
Left Intersect
0111
Bottom Intersect
1000
Horizontal Line
1001
Vertical Line
1010
Crossed Li nes
1011
Not Recommended·
1100
Special Codes
1101
Illegal
1110
Illegal
1111
Illegal
274
* Character Attribute Code 1011 is not recommended
for normal operation. Since none of the attribute
outputs are active, the character Generator will not
be disabled, and an indeterminate character will be
generated.
Field Attributes
The field attributes are control codes which affect
the visual characteristics for a field of characters,
starting at the character following the code up to, and
including, the character which precedes the next
field attribute code, or up to the end of the frame. The
field attributes are reset during the vertical retrace
interval.
There are six field attributes:
1. Blink - Characters following the code are
caused to blink by activating the Video Suppression output (VSP). The blink frequency is
equal to the screen refresh frequency divided by
32.
2. Highlight - Characters following the code are
caused to be highlighted by activating the
Highlight output (HGLT).
3. Reverse Video - Characters following the code
are caused to appear with reverse video by
activating the Reverse Video output (RVV).
4. Underline - Characters following the code are
caused to be underlined by activating the Light
Enable output (LTEN).
5,6. General Purpose - There are two additional
WD8275 outputs which act as general purpose,
independently programmable field attributes.
GPAO-1 are active high outputs.
Character Attribute Codes 1101, 1110, and 1111 are
illegal.
Blinking is active when B = 1.
Highlight is active when H = 1.
Special Codes
Four special codes are available to help reduce
memory, software, or DMA overhead.
SPECIAL CONTROL CHARACTER
MSB
o
0
S
LSB
S
Lspecial Control Code
S
S
0
0
1
1
0
1
0
1
FUNCTION
End of Row
End of Row-Stop DMA
End of Screen
End of Screen-Stop DMA
The End of Row Code (00) activates VSP and holds it
to the end of the line.
FIELD ATTRIBUTE CODE
MSB
1 0
The End of Row-Stop DMA Code (01) causes the
DMA Control Logic to stop DMA for the rest of the
row when it is written into the Row Buffer. It affects
the display in the same way as the End of Row Code
(00).
U
R
II
LSB
H
TL...----~~~~ral
G
G
B
~Hi9hli9ht
Purpose
.
Reverse Video
'---------Underline
The End of Screen Code (10) activates VSP and holds
it to the end of the frame.
H
B
R
U
GG
The End of Screen-Stop DMA Code (11) causes the
DMA Control Logic to stop DMA for the rest of the
frame when it is written into the Row Buffer. It affects
the display in the same way as the End of Screen
Code (10).
=
=
=
=
=
1 for highlighting
1 for blinking
1 for reverse video
1 for underline
GPA1, GPAO
NOTE:
More than one attribute can be enabled at the
same time. If the blinking and reverse video attributes are enabled simultaneously, only the
reversed characters will blink.
The WD8275 can be programmed to provide visible
or invisible field attribute characters.
If the WD8275 is programmed in the visible field
attribute mode, all field attributes will occupy a
position on the screen. They will appear as blanks
caused by activation of the Video Suppression
output (VSP). The chosen visual attributes are
activated after this blanked character.
If the Stop DMA feature is not used, all characters
after an End of Row character are ignored, except for
the End of Screen character, which operates normally. All characters after an End of Screen character
are ignored.
NOTE:
If a Stop DMA character is not the last character in a
burst or row, DMA is not stopped until after the next
character is read. In this situation, a dummy
character must be placed in memory after the Stop
DMA character.
275
:ec
ABC D E
00
N
Since the FIFO is 16 characters long, no more than 16
field attribute characters may be used per line in this
mode. If more are used, a bit in the status word is set
and the first characters in the FIFO are written over
and lost.
NOTE:
Since the FIFO is 7 bits wide, the MSB of any
characters put in it are stripped off. Therefore, a
Visual Attribute or Special Code must not immediately follow a field attribute code. If this
situation does occur, the Visual Attribute or Special
Code will be treated as a normal display character.
F G H I J K L M
N 0 P Q R STU V
......
CJ1
1 2 3 4 5
6 789
Figure 24.
EXAMPLE OF A VISIBLE FIELD ATIRIBUTE
MODE (UNDERLINE ATIRIBUTE)
ABC D E F G H
J
K L M
N 0 P Q R STU V
If the WD8275 is programmed in the invisible field
attribute mode, the WD8275 FIFO is activated.
1 234 5 6 789
Figure 26.
EXAMPLE OF THE INVISIBLE FIELD ATIRIBUTE
MODE (UNDERLINE ATIRIBUTE)
CCO·6
DRO----,
Wii
cs
Field and Character Attribute Interaction
Character Attribute Symbols are affected by the
Reverse Video (RVV) and General Purpose (GPAO-1)
field attributes. They are not affected by Underline,
Blink or Highlig~t field attributes; however, these
characteristics can be programmed individually for
Character Attribute Symbols.
LCO·3
LAO·1
HRTC
VRTC
HLGT
RVV
LTEN
VSP
GPAO·1
Cursor Timing
The cursor location is determjned by a cursor row
register and a character position register which are
loaded by command to the controller. The cursor can
be programmed to appear on the display as:
1. a blinking underline
2. a blinking reverse video block
3. a non-blinking underline
4. a non-blinking reverse video block
The cursor blinking frequency is equal to the screen
refresh frequency divided by 16.
If a non-blinking reverse video cursor appears in a
non-blinking reverse video field, the cursor will appear as a normal video block.
If a non-blinking underline cursor appears in a nonblinking underline field, the cursor will not be visible.
LPEN
Figure 25.
BLOCK DIAGRAM SHOWING FIFO ACTIVATION
Each row buffer has a corresponding FIFO. These
FIFOs are 16 characters by 7 bits in size.
When a field attribute is placed in the row buffer
during DMA, the buffer input controller recognizes it
and places the next character in the proper FIFO.
When a field attribute is placed in the Buffer Output
Controller during display, it causes the controller to
immediately put a character from the FIFO on the
Character Code outputs (CC0-6). The chosen Visual
Attributes are also activated.
276
Light Pen Detection
AD
A light pen consists of a micro switch and a tiny light
sensor. When the light pen is pressed against the
CRT screen, the micro switch enables the light
sensor. When the raster sweep reaches the light
sensor, it triggers the light pen output.
0
0
1
1
If the output of the light pen is presented to the
WD8275 LPEN input, the row and character position
coordinates are stored in a pair of registers. These
registers can be read on command. A bit in the status
word is set, indicating that the light pen signal was
detected. The LPEN input must be a 0 to 1 transition
for proper operation.
OPERATION
Read
Write
Read
Write
REGISTER
PREG
PREG
SREG
CREG
The WD8275 expects to receive a command and
a sequence of 0 to 4 parameters, depending on
the command. If the proper number of parameter
bytes are not received before another command is
given, a status flag is set, indicating an improper
command.
INSTRUCTION SET
NOTE:
Due to internal and external delays, the character
position coordinate will be off by at least three
character positions. This has to be corrected in
software.
The WD8275 instruction set consists of 8 commands.
COMMAND
Reset
Start Display
Stop Display
Read Light Pen
Load Cursor
Enable Interrupt
Disable Interrupt
Preset Counters
Device Progll'amming
The WD8275 has two programming registers, the
Command Register (CREG) and the Parameter
Register (PREG). It also has a Status Register (SREG).
The Command Register can only be written into and
the Status Registers can only be read from. They are
addressed as follows:
NO. OF PARAMETER BYTES
4
0
0
2
2
0
0
0
In addition, the status of the WD8275 (SREG) can be
read by the CPU at any time.
'I. Reset Command
OPERATION
Write
Write
Write
Wrjte
Write
Command
Parameters
C/P
DESCRIPTION
Reset Command
Screen Comp Byte 1
Screen Comp Byte 2
Screen Comp Byte 3
Screen Comp Byte 4
1
0
0
0
0
DATA BUS
MSB
LSB
o0 0 0 0 0 0 0
S H H H H H H ~ __
V V R R R R R R
UUUULLLL
M FCC Z Z Z Z__
Parameter-HHHHHHH Horizontal Characters/Row
NO. OF CHARACTERS
HHHHHHH
PERROW
o0 0 0 0 0 0
1
o0 0 0 0 0 1
2
o 000 0 1 0
3
Action
After the reset command is written, DMA requests
stop, WD82'75 interrupts are disabled, and the VSP
output is used to blank the screen. HRTC and VRTC
continue to run. HRTC and VRTC timing are random
on power-up.
As parameters are written, the screen composition is
defined.
Parameter-S Spaced Rows
s=~
FUNCTIONS
Normal Rows
Spaced Rows
277
1 001 1 1 1
1 o 1 0 000
80
Undefined
1 1 1 1 1 1 1
Undefined
Parameter-VV Vertical Retrace Row Count
V V
NO. OF ROW COUNTS PER VRTC
1
0 0
0 1
2
1 0
3
1 1
4
Parameter-M Line Counter Mode
LINE COUNTER MODE
M
Mode 0 (Non-Offset)
0
Mode 1 (Offset by 1 Count)
1
Parameter- F Field Attribute Mode
FIELD ATTRIBUTE MODE
F
Transparent
0
1
Non-Transparent
Parameter-RRRRRR Vertical Rows/Frame
R R R R R R NO. OF ROWS/FRAME
1
0 0 0 0 0 0
2
0 0 0 0 0 1
0 0 0 0 1 0
3
1
1
1
1
1
1
Parameter-CC Cursor Format
CURSOR FORMAT
C C
Blinking reverse video block
0 0
Blinking underline
0 1
Non-blinking reverse video block
1 0
1 1
Non-blinking underline
64
Parameter-UUUU Underline Placement
LINE NO. OF UNDERLINE
U U U U
1
0 0 0 0
2
0 0 0 1
0 0 1 0
3
1
1
1
1
Parameter-ZZZZ Horizontal Retrace Count
NO. OF CHARACTER COUNTS
PER HRTC
Z Z Z Z
2
0 0 0 0
4
0 0 0 1
6
0 0 1 0
16
1
Parameter-LLLL
Number of Lines per Character Row
NO. OF LINES/ROW
L L L L
1
0 0 0 0
2
0 0 0 1
0 0 1 0
3
1
1
1
1
1
1
1
32
NOTE:
uuuu MSB determines blanking of top and bottom
lines (1 = blanked, 0 = not blanked).
16
2. Start Display Command
Command
S
0
0
0
0
1
1
1
1
S
0
0
1
1
0
0
1
1
S
0
1
0
1
0
1
0
1
OPERATION
Write
No parameters
DESCRIPTION
Start Display
Ao
1
SSS Burst Space Code
NO. OF CHARACTER CLOCKS
BETWEEN DMA REQUESTS
0
7
15
23
31
39
47
55
B
0
0
1
1
B
0
1
0
1
DATA BUS
MSB
LSB
001SSSBB
BB Burst Count Code
NO. OF DMA CYCLES PER
BURST
1
2
4
8
Action
WD8275 interrupts are enabled, DMA requests begin,
video is enabled, Interrupt Enable and Video Enable
Status flags are set.
278
3. Stop Display Command
~
mand
OPERATION
Write
No Qarameters
Ao
DESCRIPTION
Start Display
1
DATA BUS
MSB
LSB
o
1 000 0 0 0
Action
Disables video, interrupts remain enabled, HRTC and
VRTC continue to run, Vid~o Enable status flag is
reset, and the "Start Display" command must be
given to re-enable the display.
4. Read Light Pen Command
OPERATION
Write
Read
Read
Command
Parameters
Ao
DESCRIPTION
Read Light Pen
Char. Number
Row Number
1
0
0
DATA BUS
MSB
LSB
o
1 1 0 0 0 0 0
(Char. Position in Row)
(Row Number)
Action
The WD8275 is conditioned to supply the contents of
the light pen position registers in the next two read
cycles of the parameter register. Status flags are not
affected.
NOTE:
Software correction of light pen position is required.
5. Load Cursor Position
OPERATION
Write
Write
Write
Command
Parameters
Ao
DESCRIPTION
Load Cursor
Char. Number
Row Number
1
0
0
DATA BUS
MSB
LSB
1 000 0 000
(Char. Position in Row)
(Row Number)
Action
The WD8275 is conditioned to place the next two
parameter bytes into the cursor position registers.
Status flags not affected.
6. Enable Interrupt Command
~
d
OPERATION
Write
No parameters
Ao
DESCRIPTION
Enable Interrupt
1
DATA BUS
MSB
LSB
10100 0 0 0
Action
The interrupt enable flag is set and interrupts are
enabled.
7. Disable Interrupt Command
~
d
OPERATION
Write
No parameters
DESCRIPTION
Disable Interrupt
Ao
1
Action
Interrupts are disabled and the interrupt enable
status flag is reset.
279
DATA BUS
MSB
LSB
1 1 000 0 0 0
8. Preset Counters Command
Command
OPERATION
Write
No parameters
DATA BUS
MSB
LSB
1 1 1 000 0 0
DESCRIPTION
Preset Counters
Ao
1
Action
The internal timing counters are preset, cor·
responding to a screen display position at the top left
corner. Two character clocks are required for this
operation. The counters will remain in this state until
any other command is given.
This command is useful for system debug and
synchronization of clustered CRT displays on a
single CPU.
STATUS FLAGS
OPERATION
Read
Command
IE
IR
LP
IC
DESCRIPTION
Status Word
Ao
1
-(Interrupt Enable) Set or reset by command. It
enables vertical retrace interrupt. It is
automatically set by a "Start Display" command and reset with the "Reset" command.
-(Interrupt Request) This flag is set at the
beginning of display of the last row of the
frame if the interrupt enable flag is set. It is
reset after a status read operation.
- This flag is set when the light pen input
(LPEN) is activated and the light pen
registers have been loaded. This flag is
automatically reset after a status read.
-(Improper Command) This flag is set when a
command parameter string is too long or too
VE
DU
FO
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ..... O°C to 70°C
Storage Temperature ......... - 65°C to + 150°C
Voltage On Any Pin
With Respect to Ground ........ - 0.5V to + 7V
Power Dissipation ...................... 1 Watt
=
DC Characteristics (TA O°C to 70°C; VCC
SYMBOL
PARAMETER
Input Low Voltage
V,L
Input High Voltage
V,H
VOL
VOH
IlL
IOFL
ICC
Output Low Voltage
Output High Voltage
Input Load Current
Output Float Leakage
VCC Supply Current
DATA BUS
MSB
LSB
o IE IR LP IC VE OU FO
short. The flag is automatically reset after a
status read.
-(Video Enable) This flag indicates that video
operation of the CRT is enabled. This flag is
set on a "Start Display" command, and reset
on a "Stop Display" or "Reset" command.
-(DMA underrun) This flag is set whenever a
data underrun occurs during DMA transfers.
Upon detection of DU, the DMA operation is
stopped and the screen is blanked until after
the vertical retrace interval. This flag is reset
after a status read.
-(FIFO Overrun) This flag is set whenever the
FIFO is overrun. It is reset on a status read.
*NOTICE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied.
= 5V ± 5%)
MIN
-0.5
2.0
MAX
0.8
VCC
+0.5V
0.45
2.4
±10
±10
160
280
UNITS
V
V
V
V
/AA
/AA
mA
TEST CONDITIONS
=
==
=
IOL 2.2mA
IOH
400 /AA
Y,N
VCC to OV
VOUT
VcctoOV
Capacitance (TA
SYMBOL
CIN
CI/O
= 25°C; VCC = GND = OV)
PARAMETER
Input Capacitance
I/O Capacitance
MIN
MAX
10
20
I
UNITS
TEST CONDITIONS
pF
fC = 1 MHz
Unmeasured pins returned to
pF
VSS·
AC Characteristics (TA = O°C to 70°C; VCC = 5.0V ± 5%; GND = OV)
BUS PARAMETERS
Read Cycle
SYMBOL
tAR
tRA
tRR
tRD
tDF
PARAMETER
Address Stable Before
READ
Address Hold Time for
READ
READ Pulse Width
Data Delay from READ
READ to Data Floating
MIN
20
PARAMETER
Address Stable Before
WRITE
Address Hold Time for
WRITE
WRITE Pulse Width
Data Setup Time for
WRITE
Data Hold Time for
WRITE
MIN
MAX
UNITS
0
ns
0
250
200
100
ns
ns
ns
ns
MAX
UNITS
TEST CONDITIONS
CL = 150pF
CL min. = 20 pF; CL max. =
150 pF
Write Cycle
SYMBOL
tAW
tWA
tww
tDW
tWD
0
ns
0
250
ns
ns
150
ns
0
ns
TEST CONDITIONS
Clock Timing
SYMBOL
tCLK
tKH
tKL
tKR
tKF
PARAMETER
Period
High
Low
Rise
Fall
MIN
480
240
160
5
5
MAX
PARAMETER
Character Code Output
Delay
Horizontal Retrace
Output Delay
Line Count Output Delay
Controll Attribute Output
Delay
Vertical Retrace Output
Delay
INn from Rot
DROt from WRt
DROt from WRt
DACKt to WRt
WRt to DACKt
LPEN Rise
LPEN Hold
MIN
Clock
Clock
Clock
Clock
Clock
TEST CONDITIONS
30
30
UNITS
ns
ns
ns
ns
ns
MAX
UNITS
TEST CONDITIONS
150
ns
CL = 50 pF
200
400
ns
ns
CL = 50 pF
CL = 50 pF
275
ns
CL = 50 pF
275
250
250
200
ns
ns
ns
ns
ns
ns
ns
ns
CL
CL
CL
CL
Other Timing
SYMBOL
tcc
tHR
tLC
tAT
tVR
tRI
two
tRO
tLR
tRL
tPR
tPH
0
0
50
100
281
=
=
=
=
50
50
50
50
pF
pF
pF
pF
I
AC Testing Load Circuit
AC Testing Input, Output Wave Form
I N PUT/OUTPUT
2'=>(
0.45
2.2
< )C
DEVICE
UNDER
TEST
2.2
~ TEST POINTS
0.8
0.8
'lCL
AC TESTING: INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1" AND
0.45V FOR A LOGIC "0" TIMING MEASUREMENTS ARE MADE AT
2.2V FOR A LOGIC "1" AND 0.8V FOR A LOGIC "0."
WAVEFORMS
Typical Dot Level Timing
EXT DOT CLK·
CCLK*
CCO·6
CHARACTER
GENERATOR
OUTPUT
l . ._____---'
SECOND CHARACTER CODE
FIRST CHARACTER CODE
FIRST CHARACTER
ATTRIBUTES
& CONTROLS
VIDEO
(FROM SHIFT
REGISTER)
ATTRIBUTES
& CONTROLS
(FROM
SYNCHRONIZER)
ATTRIBUTES & CONTROLS
FOR FIRST CHAR.
* CCLK IS A MULTIPLE OF THE DOT CLOCK AND AN INPUT TO THE 8275.
282
SECOND CHARACTER
WAVEFORMS (Continued)
Line Timing
~rf-tlC
lCO·3
-+__P_R_E_S_E_NT_l_IN_E_C_O_U_N_T_ _--In~~-------------J)Jf
NEXT LINE COUNT
* lAO·1 , VSP, lTEN, HGlT, RVV, GPAO.1'
Row Timing
CClK
HRTC
lC0-3
PROGRAMMABLE FROM 1 TO 16 UNES~
INTERNAL
ROW
COUNTER
PRESENT
ROW:
Frame Timing
283
NEXT ROW
WAVEFORMS (Continued)
Intenupt Timing
~r-r - - - - - - -
CCLK
CCo-a
LAST RETRACE
CHARACTER
X
------.,.
FIRST RETRACE
CHARACTER
RD
IRQ
WR
LPEN
284
WAVEFORMS (Continued)
Write Timing
Read Timing
AO, CS
WR
DBO·7
Clock Timing
.....---tcv----I..-t
CCLK
See page 725 for ordering information .
•
285
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility Is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from Its use. No license Is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
286
Printed in U.S.A.
WESTERN DIGITAL
c
o
R
p
o
A
R
T
/
o
N
WD8276 Small System CRT Controller
FEATURES
GENERAL DESCRIPTION
• PROGRAMMABLE SCREEN AND CHARACTER
FORMAT
The WD8276 Small System CRT Controller is a single
chip device intended to interface CRT raster scan
displays with Intel microcomputers in minimum
device-count systems. Its primary function is to refresh the display by buffering character information
from main memory and keeping track of the display
position of the screen. The flexibility designed into
the WD8276 will allow simple interface to almost any
raster scan CRT display with a miniml!Jm system IC
count.
• 6 INDEPENDENT VISUAL FIELD ATTRIBUTES
• CURSOR CONTROL (4 TYPES)
• DUAL ROW BUFFERS
• SINGLE
+ 5V SUPPLY
• 40-PIN PACKAGE
CHARACTER
COUNTER
vcc
CCLK
NC
NC
LCo
LTEN
BRDY
RVV
as
VSP
DBo·7
HRTC
GPA1
VRTC
GPAo
ADI
HLGT
WR"I
NC I
DBO I
CCLK
Bs'
CC6
INT
DB1
CC5
DB2
CC4
DB3
CC3
DB4
CC2
INT
DATA
BUS
BUFFER
CCO·6
LINE
COUNTER
BRDY
ROW
COUNTER
RD
WR
RASTER TIMING
AND
VIDEO CONTROL
CC1
CCo
Cs
CS
C/P
Figure 2.
Figure 1.
LCO·3
PIN CONFIGURATION
287
BLOCK DIAGRAM
HRTC
VRTC
HLGT
RVV
LTEN
VSP
GPAO·1
TABLE 1. PIN DESCRIPTIONS
PIN
NO.
1
2
3
4
5
TYPE
PIN NAME
0
LINE COUNT
0
BUFFER READY
LC3
LC2
LC1
Leo
BRDY
6
I
BUFFER SELECT
BS
7
0
HORIZONTAL
RETRACE
HRTC
8
0
VERTICAL RETRACE
VRTC
9
10
I
I
READ INPUT
WRITE INPUT
RD
WR
NO CONNECTION
BIDIRECTIONAL
DATA BUS
NC
11
FUNCTION
SYMBOL
--
Output from the line counter which is used to
address the character generator for the line
positions on the screen.
Output signal indicating that a Row Buffer is
ready for loading of character data.
Input signal enabling WR for character data into
the Row Buffers.
Output signal which is active during the programmed horizontal retrace interval. During this
period the VSP output is high and the LTEN
output is low.
Output signal which is active during the programmed vertical retrace interval. During this
period the VSP output is high and the LTEN
output is low.
A control signal to read registers.
A control signal to write commands into the
control registers or write data into the row
buffers.
No connection
Three-state lines. The outputs are enabled
during a read of the C or P ports.
12
13
14
15
16
17
18
19
20
21
I/O
I
GROUND
PORT ADDRESS
22
I
CHIP SELECT
CS
23
24
25
26
27
28
29
, 30
31
0
CHARACTER CODES
I
CHARACTER CLOCK
INTERRUPT OUTPUT
Ceo
CC1
CC2
CC3
CC4
CC5
CGa
CCLK
Character clock (from dot/timing logic).
INT
Interrupt output.
HIGHLIGHT
HLGT
Output Signal used to intensify the display at
particular positions on the screen as specified
by the field attribute codes.
GENERAL PURPOSE
ATTRIBUTE CODES
GPA 1
GPAQ
32
33
34
0
0
0
DBO
DB1
DB2
DB3
DB4
DB5
DBa
DB7
Ground
C/P
A high input on this pin selects the "C" port or
command registers and a low input selects the
"P" port or parameter registers.
Enables RD of status or WR of command or
parameters.
Output from the row buffers used for character
selection in the character generator.
I
288
Outputs which are enabled by the
purpose field attribute codes.
general
-1
\
TABLE 1. PIN DESCRIPTIONS
PIN
NO.
TYPE
PIN NAME
SYMBOL
35
0
VIDEO SUPPRESSION
VSP
36
0
REVERSE VIDEO
RVV
37
0
UGHTENABLE
LTEN
NO CONNECTION
NO CONNECTION
+ 5V POWER SUPPLY
NC
NC
38
39
40
FUNCTION
Output signal used to blank the video signal to
the CRT. This output is active:
-during the horizontal and vertical retrace
intervals.
-at the top and bottom lines of rows if underline is programmed to be number 8 or
greater.
-when an end of row or end of screen code is
detected.
-when a Row Buffer underrun occurs.
-at regular intervals (1/16 frame frequency fgr
cursor, 1/32 frame frequency for attributes) to create blinking displays as specified by
cursor or field attribute programming.
Output signal used to activate the CRT circuitry
to reverse the video Signal. This output is active
at the cursor position if a reverse video block
cursor is programmed or at the positions
specified by the field attribute codes.
Output signal used to enable the video signal to
the CRT. This output is active at the programmed underline cursor position, and at
positions specified by attribute codes.
No connection.
No connection.
+ 5V power supply.
VCC
FUNCTIONAL DESCRIPTION
CS (CHIP SELECl)
A "low" on this input selects the WD8276 for RD or
WR of Commands, Status, and Parameters.
Data Bus Buffer
This 3-state, bidirectional, 8-bit buffer is used to
interface the WD8276 to the system Data Bus.
This functional block accepts inputs from the System Control Bus and generates control signals for
overall device operation. It contains the Command,
Parameter, and Status Registers that store the
various control formats for the device functional
definition.
BRDY (BUFFER READY)
A "high" on this output indicates that the WD8276 is
ready to receive character data.
BS (BUFFER SELECl)
A "low" on this input enables WR of character data to
the WD8276 row buffers.
I Cg~/P I__
INT (lNTERRUPl)
A "high" on this output informs the CPU that the
WD8276 needs interrupt service.
Read
RESERVED
Write
PARAMETER
O_P_ER_A_J_IO_N_--,-__
R_E_G_IS_T_E_R_--,
Read
STATUS
Wri~
COMMAND
C/P RD WR CS
1
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
X
0
1
1
RD(READ)
A "low" on this input informs the WD8276 that the
CPU is reading status information from the WD8276.
WR(WRITE)
A "low" on this input ·informs the WD8276 that the
CPU is writing data or control words to the WD8276.
X
X
289
1
X
1
X
X
1
BS
Reserved
Write WD8276 Parameter
Read WD8276 Status
Write WD8276 Command
0 Write WD8276 Row
Buffer
X High Impedance
1 High Impedance
1
1
1
1
to be displayed per frame and length of the vertical
retrace interval.
'
Character Counter
The Character Counter is a programmable counter
that is used to determine the number of characters
Raster Timing and Video Controls
The Raster Timing circuitry c;ontro)8 the timing of
the HRTC (Horizontal Retrace) and VRlC (Vertical
Retrace) outputs. The Video Control circuitry
controls the generation of HGLT (Highlight), RVV
(Reverse Video), LTEN (Light Enable), VSP (Video
Suppress), and GPAO-1 (General Purpose Attribute)
outputs.
to be displayed per row and the length of the
horizontal retrace interval. It is driven by the CCLK
(Character Clock) input, which should be derived
from the external dot clock.
Line Counter
The Line Counter is a programmable counter that is
used to determine the number of horizontal lines
(Raster Scans) per character' row. Its outputs are
used to address the external character generator.
Row Buffers
The Row Buffers are two 80-character buffers. They
are filled from the microcomputer system memory
with the character codes to be displayed. While
one row buffer is displaying a row of characters,
Row Counter
The Row Counter is a programmable counter that
is used to determine the number of character rows
INT
BRDY
8088
MICRO·
PROCESSOR
.
;:.
'EiS"
I
~
LCO·3
..
CCO-6
CHARACTER
" GENERATOR
..
(ROM OR
RAM)
WD8276
CRT
CONTROLLER
.
r
"
I
CCLK
8205
DECODER
VIDEO CONTROLS
VIDEO SIGNAL
..
..
HIGH
SPEED
DOT
TIMING
LOGIC
AND
INTERFACE
HORIZONTAL SYNC
TO CRT
VERTICAL SYNC
INTENSITY
a
r
~
SYSTEM BUS
.t.
;:.
..
~
•
..
8253·5
COUNTERI
TIMER
;:.
... ;:.
....... ;:.
~
.
.
PROGRAMI
DISPLAY
MEMORY
WD1983
UART
t
~
~
SERIAL
COMMUNICATIONS
CHANNEL
Figure 3.
CRT SYSTEM BLOCK DIAGRAM
290
~
8255A·5
KEYBOARD
CONTROLLER
n
KEYBOARD,
I
STATUS
I
the other is being filled with the next row of
characters.
Buffer Input/Output Controllers
The Buffer Input/Output Controllers decode the
characters being placed in the row buffers. If the
character is a field attribute or special code, they
control the appropriate action. (Example: A "Highlight" field attribute will cause the Buffer Output
Controller to activate the HGLT output.)
SYSTEM OPERATION
The WD8276 is programmable to a large number of
different display formats. It provides raster timing,
display row buffering, visual attribute decoding and
cursor timing.
It is designed to interface with standard character
generators for dot matrix decoding. Dot level timing
must be provided by external circuitry.
GENERAL SYSTEMS OPERATIONAL
DESCRIPTION
Display characters are retrieved from memory and
displayed on a row-by-row basis. The WD8276 has
two row buffers. While one row buffer is being
used for display, the other is being filled with the
next row of characters to be displayed. The number
of display characters per row and the number of
character rows per frame are software programmable, providing easy interface to most CRT
displays. (See Programming Section.)
The WD8276 uses BRDY to request character data
to fill the row buffer that is not being used for
display.
The WD8276 displays character rows one scan line
at a time. The number of scan lines per character
row, the underline position, and blanking of top and
bottom lines are programmable. (See Programming
Section.)
The WD8276 provides special Control Codes which
can be used to minimize overhead. It also provides
Visual Attribute Codes to cause special action on
the screen without the use of the character
generator. (See Visual Attributes Section.)
The WD8276 also controls raster timing. This is
done by generating Horizontal Retrace (HRTC) and
Vertical Retrace (VRTC) signals. The timing of these
signals is also programmable.
The WD8276 can generate a cursor. Cursor location
and format are programmable. (See Programming
Section.)
2nd
3rd
4th
5th
6th
7th
1st
Character Character Character Character Character Character Character
~~------~--.-----~--~--,--~-~
00 • • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
First Line of a Character Row
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
~~~~~
00 • • • • 000.0000.00 • • • • • 000000000 • • • • 0000 • • • 000.000.0
0.0000.00 • • 000.00.0000000000000.000.00.000.00.000.0
Second Line of a Character Row
1st
2nd
3rd
4th
5th
6th
7th
Character Character Character Character Character Character Character
~~~~'-V_ _A_-..~~
oo •••• ooo.oooo.OO ••• A.ooooooooo •••• oooo ••• ooo.ooo.o
0.0000.00 • • 000.00.0000000000000.000.00.000.00.000.0
0.0000.00.0000.00.0000000000000.000.00.000.00.000.0
Third Line of a Character Row
Figure 4.
DISPLAY OF A CHARACTER ROW
291
DISPLAY ROW BUFFERING
Before the start of a frame, the WD8276 uses BRDY
and BS to fill one row buffer with characters.
When the first horizontal sweep is started, character
codes are output to the character generator from the
row buffer just filled. Simultaneously, the other row
buffer is fi lied with the next row of characters.
After all the lines of the character row are scanned,
the buffers are swapped and the same procedure is
followed for the next row.
This process is repeated until all of the character
rows are displayed.
Row Buffering allows the CPU access to the display
memory at all times except during Buffer Loading
(about 25%). This compares favorably to alternative
approaches which restrict CPU access to the display
memory to occur only during horizontal and vertical
retrace intervals (80% of the bus time is used to
refresh the display.)
Figure 7.
FIRST ROW BUFFER FILLED WITH
THIRD ROW, SECOND ROW DISPLAYED
DISPLAY FORMAT
Screen Format
The WD8276 can be programmed to generate from 1
to 80 characters per row, and from 1 to 64 rows per
frame.
CCO-6
123456789 .................... 80
2
Figure 5.
3
4
5
6
FIRST ROW BUFFER FILLED
7
8
9
64
DBO·
~.
DATA
-'-WS'"
BUFFER
Figure B.
SCREEN FORMAT
The WD8276 can also be programmed to bl
alternate rows. In this mode, the first
played, the second blank d t h '
Figure 6.
SECOND ROW BUFFER FILLED
FIRST ROW DISPLAYED
'
Display data is not reqUeSfed
292
row
. a~k
IS dIS·
to; /hh''''bdl
displayed, etc.
e anked rows.
In mode 1, the line counter is offset by one from the
line number.
NOTE:
123456789 .................... 80
In mode 1, while the first line (line number O) is being
displayed, the last count is output by the line counter
(see examples).
2
3
4
5
Line
Number
0
1
2
3
64
4
5
Figure 9.
BLANK ALTERNATE ROWS MODE
Row Format
0
[J
o
[]
[J
0
0
•
3 o
[J
•
0
2
0
o
• LJ
o •
o 0
o 0
0
LJ
0
•
o
o
o
o
0
0
0
0
4 LJ .. 0 0
0 • 0
5 o H 0 o 0 0 o • 0
6 o .1 •
0
7 l] HOD o 0 0 • 0
8 o H 0 o 0 0 0 • 0
9 o noD o 0 o • 0
10 o [J 0 0 0 0 0 0 0
11 o [J 0 o 0 0 0 0 0
•••••
12
13
[j
[J
0
o
0
o
DOD
[J
[]
0
0
o
o
0
0
14 [J lJ 0 0
15 o [] [] o
0
0
0
o 0 [J
o [] [] LJ
0
o
o
o
[]
[]
[J
[]
[]
[]
[J
[]
•
•
LJ •
lJ
lJ
[]
[] 0
[J
[]
U
•
0
LJ LJ [] [] 0
0
[]
[]
[]
[J
[J
o
o
o
o
o
[]
[J
Line
Number
Line
Line
Counter Counter
Mode 1
Mode 0
000 1 1 1 1
000 1
0 0 0
001 0 000 1
001 1 001 0
1 0 0 001 1
1 0 1
1 0 0
1 1 0
1 0 1
011 1
1 1 0
1 000
1 1 1
1 0 0 1 1 000
101 0 1 0 0 1
101 1 101 0
1 1 0 0 1 0 1 1
1 1 0 1 1 1 0 0
1 110 1 1 0 1
1 1 1 1 1 110
o
0
[]
•
o
0
o
o
o
o
Underline placement is also programmable (from line
number 0 to 15). This is independent of the line
counter mode.
If the line number of the underline is greater than 7
(line number MSB = 1), then the top and bottom
lines will be blanked.
In mode 0, the output of the line counter is the same
as the line number.
0
......
.
o LJ
o •
[J
0
o • [J [] []
• o • [] []
Mode 0 is useful for character generators that leave
address zero blank and start at address 1. Mode 1 is
useful for character generators which start at address zero.
The output of the line counter can be programmed to
be in one of two modes.
[J
[] [] 0
Figure 11.
EXAMPLE OF A 10·LlNE FORMAT
The number of lines (horizontal sweeps) per character row is programmable from 1 to 16.
Line
Number
0 o
1 o
[]
[] 0
[]
6
7
8
9
The WD8276 is designed to hold the line count stable
while outputting the appropriate character codes
during each horizontal sweep. The line count is incremented during horizontal retrace and the whole
row of character codes are output again during the
next sweep. This is continued until the entire
character row is displayed.
[]
Line
Line
Counter Counter
Mode 0
Mode 1
0 0 0 100 1
000 1
0 0 0
001 0 000 1
001 1 001 0
1 0 0 001 1
1 0 1
1 0 0
1 1 0
1 0 1
1 1 1
1 1 0
1 000
1 1 1
100 1 100 0
o
I] [J 0
0
0
0
[] [] []
1 I] [] [] [] • 0 CJ [J LJ
21][][].o.[Jt:JO
o
3
IJ
0
IJ
•
•
LJ [] [] •
LJ 0 0 [] 0
0
4
•
0
[J
•
l]
•
L.J
5
6
7
o
o
o
o
8
9
0
0
0
0
[J
I]
•••••••
I]
•
LJ
[]
[]
[]
0
•
0
0
I]
•
[]
[]
0
0
[]
•
[]
IJ
•
[]
[]
LJ
[J
U
•
[J
10 • • • • • • • • •
11
IJ
0
0
0
0
rJ
l I
IJ
LJ
Line
Counter
Mode 0
o0 0 0
000 1
001 0
001 1
o1
o1
o1
o1
0 0
0 1
1 0
1 1
1 000
100 1
101 0
1 0 1 1
Line
Counter
Mode 1
101 1
o0 0 0
000 1
001 0
001 1
o1 0 0
o10 1
o1 1 0
011 1
100 0
1 0 0 1
101 0
Top and Bottom
Lines are Blanked
Figure 12.
UNDERLINE IN LINE NUMBER 10
If the line number of the underline is less than or
equal to 7 (line number MSB = O), then the top and
bottom lines will not be blanked.
Figure 10.
EXAMPLE OF A 16·LINE FORMAT
293
Line
Counter
Mode 0
Line
Number
0
1
2
3
4
5
6
7
o
o
0
0
.
0
LJ 0
0
0
0
•
0
0
0
o • 0
0 o •
Ll • 0 0 o •
o • • • • •
o • 0 0 o •
[]
[]
[J
•
0
0
0
0
0
Ll
•••••••
Top and Bottom
o0 0
000
001
001
o1 0
o1 0
o1 1
o1 1
RASTER TIMING
The character counter is driven by the character
clock input (CCLK). It counts out the characters
being displayed (programmable from 1 to 80). It then
causes the line counter to increment, and it starts
counting out the horizontal retrace interval (programmable from 2 to 32). This process is constantly
repeated.
Line
Counter
Mode 1
0 o1 1 1
1 o0 0 0
0 000 1
1 001 0
0 o0 1 1
1 o1 0 0
0 o1 0 1
1 o1 1 0
CCLK
Lines are not Blanked
Figure 13.
UNDERLINE IN LINE NUMBER 7
HRTC
If the line number of the underline is greater than the
maximum number of lines, the underline will not
appear.
Blanking is accomplished by the VSP (Video Suppression) signal. Underline is accomplisheq by the
LTEN (Light Enable) signal.
LCO-3
_ _ _ PRESENT
_ _ _ _ LINE
_ _ COUNT
_ _ _ _ _- J
NEXT
LINE COUNT
Figure 15.
LINE TIMING
Dot Format
Dot width and character width are dependent upon
the external timing and control circuitry.
Dot level timing circuitry should be designed to
accept the parallel output of the character generator
and shift it out serially at the rate required by the CRT
display.
The line counter is driven by the character counter. It
is used to generate the line address outputs (LCO-3)
for the character generator. After it counts all of the
lines in a character row (programmable from 1 to 16),
it increments the row counter, and starts over again.
(See Character Format Section for detailed description of Line Counter functions.)
The row counter is an internal counter driven by the
line counter. It controls the functions of the row
buffers and counts the number of character rows
displayed.
ONE CHARACTER ROW
VIDEO
1 - - - - - - 1 SYNCHRONIZER
I----~
Figure 14.
TYPICAL DOT LEVEL BLOCK DIAGRAM
HRTC~U-ULCO-3
Dot width is a function of dot clock frequency.
Character width is a function of the character generator width.
Horizontal character spacing is a function of the shift
register length.
NOTE:
Video control and timing signals must be synchronized with the video signal due to the character
generator access delay.
INTERNAL
ROW COUNTER
PROGRAMMABLE 1 TO 16
LINE COUNTS
Figure 16.
ROW TIMING
294
After the row counter counts all of the rows in a
'frame (programmable from 1 to 64), it starts counting
out the vertical retrace interval (programmable from 1
~~
A reset command will also cause INT to go inactive,
but this is not recommended during normal service.
NOTE:
Upon power-up, the WD8276 Interrupt Enable Flag
may be set. As a result, the user's cold start routine
should write a reset command to the WD8276 before
system interrupts are enabled.
,
ONE FRAME
VISUAL ATTRIBUTES
AND SPECIAL CODES
~
__
~
____
~/'~
____
~
The characters processed by the WD8276 are 8bit quantities. The character code outputs provide
the chara.cter generator with 7 bits of address. The
Most Significant Bit is the extra bit and it is
used to determine if it is a normal display character
(MSB = 0), or if it is a Field Attribute or Special Code
(MSB = 1).
_ _- J
PROGRAMMABLE
PROGRAMMABLE
1 TO 64 ROW COUNTS 1 TO 4 ROW COUNTS
Special Codes
Figure 17.
FRAME TIMING
Four special codes are available to help reduce bus
usage.
The Video Suppression Output (VSP) is active during
horizontal and vertical retrace intervals.
SPECIAL CONTROL CHARACTER
Dot level timing circuitry must synchronize these
outputs with the video signal to the CRT Display.
MSB
o
INTERRUPT TIMING
S
LSB
S
Lspecial Control Code
The WD8276 can be programmed to generate an
interrupt request at the end of each frame. If the
WD8276 interrupt enable flag is set, an interrupt
request will occur at the beginning of the last display
row.
S
0
0
1
1
=xx
INTERNAL
ROW
COUNTER _
S
0
1
0
'1
End
End
End
End
of
of
of
of
FUNCTION
Row
Row-Stop Buffer Loading
Screen
Screen-Stop Buffer Loading
The End of Row Code (00) activates VSP and holds it
to the end of the line.
LAST
FIRST
DISPLAY RETRACE
ROW
ROW
The End of Row-Stop Buffer Loading (BRDY) Code
(01) causes the Buffer Loading Control Logic to stop
buffer loading for the rest of the row upon being
written into the Row Buffer. It affects the display in
the same way as the End of Row Code (00).
The End of Screen Code (10) activates VSP and holds
it to the end of the frame.
INT
The End of Screen-Stop Buffer Loading (BRDY) Code
(11) causes the Row Buffer Control Logic to stop
buffer loading for the rest of the frame upon being
written. It affects the display in the same way as the
End of Screen Code (10).
Figure 18.
BEGINNING OF INTERRUPT
INT will go inactive after the status register is read.
INT
0
r
If the Stop Buffer Loading feature is not used, all
characters after an End of Row character are ignored,
except for the End of Screen character, which
operates normally. All characters after an End of
Screen character are ignored.
r-
NOTE:
If a Stop Buffer Loading is not the last character in a
row, Buffer Loading is not stopped until after the next
character is read. In this situation, a dummy
character must be placed in memory after the Stop
Buffer Loading character.
RD-\'---------J
Figure 19.
END OF INTERRUPT
295
=e
cco
N
......
0')
Field Attributes
The field attributes are control codes which affect
the visual characteristics for a field of characters,
starting at the character following the code up to, and
including, the character which precedes the next
field attribute code, or up to the end of the frame. The
field attributes are reset during the vertical retrace
interval.
The WD8276 can be programmed to provide visible
field attribute characters; all field attribute codes will
occupy a position on the screen. These codes will
appear as blanks caused by activation of the Video
Suppression output (VSP). The chosen visual attributes are activated after this blanked character.
There are six field attributes:
1. Blink - Characters following the code are
caused to blink by activating the Video Suppression output (VSP). The blink frequency Is
equal to the screen refresh frequency divided by
32.
2. Highlight - Characters following the code are
caused to be highlighted by activating the
Highlight output (HGLT).
3. Reverse Video - Characters following the code
are caused to appear with reverse video by
activating the Reverse Video output (RVV).
4. Underline - Characters following the code are
caused to be underlined by activating the Light
Enable output (LTEN).
5,6. General Purpose - There are two additional
WD8276 outputs which act as general purpose,
independently programmable field attributes.
GPA0-1 are active high outputs.
ABCDE
N 0
FGHIJKLM
P Q R STU V
FIELD ATTRIBUTE CODE
MSB
1 0
Figure 20.
EXAMPLE OF A VISIBLE FIELD ATTRIBUTE
(UNDERLINE ATTRIBUTE)
G
II T
.
B
LSB
H
I L-Highlight
L--Blink
.
General Purpose
Reverse Video
Underline
H = 1 for highlighting
B = 1 for blinking
R = 1 for reverse video
U = 1 for underline
GG = GPA1, GPAO
NOTE:
More than one attribute can be enabled at the
same time. If the blinking and reverse video attributes are enabled simultaneously, only the
reversed characters will blink.
Cursor Timing
The cursor location is determined by a cursor row
register and a character position register which are
loaded by command to the controller. The cursor
can be programmed to appear on the display as:
1. a blinking underline
2. a blinking reverse video block
3. a non-blinking underline
4. a non-blinking reverse video block
The cursor blinking frequency is equal to the
screen refresh frequency divided by 16.
If a non-blinking reverse video cursor appears in a
non-blinking reverse video field, the cursor will
appear as a normal video block.
If a non-blinking underline cursor appears in a nonblinking underline field, the cursor will not be
visible.
Device Programming
The WD8276 has two programming registers, the
Command Register and the Parameter Register. It
also has a Status Register. The Command Register
can only be written into and the Status Register
can only be read from. They are addressed as
follows:
0
0
6 789
R G
_
CIP
1 2 3 4 5
U
1
1
OPERATION
Read
Write
Read
Write
REGISTER
Reserved
Parameter
Status
Command
The WD8276 expects to receive a command and
a sequence of 0 to 4 parameters, depending on
the command. If the proper number of parameter
bytes are not received before another command is
given, a status flag is set, indicating an improper
command.
INSTRUCTION SET
The WD8276 instruction set consists of 7 commands.
NO. OF PARAMETER BYTES
4
0
0
2
0
0
0
COMMAND
Reset
Start Display
Stop Display
Load Cursor
Enable Interrupt
Disable Interrupt
Preset Counters
In addition, the status of the WD8276 can be read by
the CPU at any time.
1. Reset Command
Command
Parameters
OPERATION
Write
Write
Write
Write
Write
C/P
1
0
0
0
0
DESCRIPTION
Reset Command
Screen Comp Byte 1
Screen Comp Byte 2
Screen Comp Byte 3
Screen Comp Byte 4
Action
After the reset command is written, BRDY goes
inactive, WD8276 interrupts are disabled, and the
VSP output is used to blank the screen. HRTC and
VRTC continue to run. HRTC and VRTC timing are
random on power-up.
As parameters are written, the screen composition is
defined.
Parameter-RRRRRR Vertical Rows/Frame
NO. OF ROWS/FRAME
R R R R R R
1
0 0 0 0 0 0
2
0 0 0 0 0 1
3
0 0 0 0 1 0
E~
1 1 1 1 1 1 1
Undefined
1
1
1
1
64
Parameter-UUUU Underline Placement
LINE NO. OF UNDERLINE
U U U U
1
0 0 0 0
2
0 0 0 1
3
0 0 1 0
Parameter-HHHHHHH Horizontal Characters/Row
NO. OF CHARACTERS
PERROW
HHHHI-IHH
1
o0 0 0 0 0 0
2
o0 0 0 0 0 1
3
0000010
80
Undefined
1
1
Parameter-S Spaced Rows
FUNCTIONS
Normal Rows
Spaced Rows
1 001 1 1 1
1 o 1 0 0 0 0
DATA BUS
MSB
LSB
o0 0 0 0 0 0 0
SHHHHHHH
V V R R R R R R
UUUULLLL
M1CCZZZZ
1
1
1
1
16
Parameter-LLLL
Number of Lines per Character Row
L L
NO. OF LINES/ROW
L l
1
0 0 0 0
2
0 0 0 1
3
0 0 1 0
1
Parameter-W Vertical Retrace Row Count
NO. OF ROW COUNTS PER VRTC
V V
1
0 0
2
0 1
3
1 0
4
1 1
1
1
1
16
Parameter-M Line Counter Mode
LINE COUNTER MODE
o
Mode 0 (Non-Offset)
1
Mode 1 (Offset by 1 Count)
IT
297
Parameter-CC Cursor Format
C
C
0
0
1
1
0
1
0
1
Parameter-ZZZZ Horizontal Retrace Count
NO. OF CHARACTER COUNTS
PERHRTC
Z Z Z Z
2
0 0 0 0
4
0 0 0 1
0 0 1 0
6
CURSOR FORMAT
Blinking reverse video block
Blinking underline
Non-blinking reverse video block
Non-blinkin_g underline
NOTE:
uuuu MSB determines blanking of top and bottom
blanked, 0
not blanked).
lines (1
=
=
1
1
1
1
32
2. Start Display Command
Command
OPERATION
Write
No parameters
C/P
1
DESCRIPTION
Start Display
DATA BUS
MSB
LSB
001 000 0 0
Action
WD8276 interrupts are enabled, BRDY goes active,
video is enabled, Interrupt Enable and Video Enable
status flags are set.
3. Stop Display Command
Command
OPERATION
Write
No parameters
cip
1
DESCRIPTION
Start Display
DATA BUS
MSB
LSB
o
1 000 000
Action
Disables video, interrupts remain enabled, HRTC and
VRTC continue to run, Video Enable status flag is
reset, and the "Start Display" command must be
given to reenable the display.
4. Load Cursor Position
OPERATION
Write
Write
Write
Command
Parameters
cip
1
0
0
DESCRIPTION
Load Cursor
Char. Number
Row Number
DATA BUS
MSB
LSB
1 000 0 0 0 0
(Char. Position in Row)
(Row Number)
Action
The WD8276 is conditioned to place the next two
parameter bytes into the cursor position registers.
Status flag not affected.
5. Enable Interrupt Command
Command
OPERATION
Write
No parameters
cip
1
Action
The interrupt enable flag is set and interrupts are
enabled.
DESCRIPTION
Enable Interrupt
DATA BUS
MSB
LSB
101 0 0 0 0 0
6. Disable Intenupt Command
Command
OPERATION
Write
No parameters
citS
1
DESCRIPTION
Disable Interrupt
DATA BUS
MSB
LSB
1 1 0 0 0 0 0 0
DESCRIPTION
Preset Counters
DATA BUS
MSB
LSB
1 1 1 000 0 0
Action
Interrupts are disabled and the interrupt enable
status flag Is reset.
7. Preset Counters Command
Command
OPERATION
Write
No parameters
cifS
1
Action
The internal timing counters are preset, corresponding to a screen display position at the top left
corner. Two character clocks are required for this
operation. The counters will remain in this state until
any other command is given.
This command Is useful for system debug and
synchronization of clustered CRT displays on a
single CPU.
STATUS FLAGS
OPERATION
Read
Command
IE
fR
IC
cifi
DESCRIPTION
Status Word
1
-(Interrupt Enable) Set or reset by command. It
enables vertical retrace interrupt. It is
automatically set by a "Start Display" command and reset with the "Reset" command.
-(Interrupt Request) This flag is set at the
beginning of display of the last row of the
frame If the interrupt enable flag is set. It is
reset after a status read operation.
-(Improp$r Command) This flag is set when a
command parameter string Is too long or too
short. The flag is automatically reset after a
status read.
VE
BU
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS*
Ambient Temperature Under Bias ..... O°C to 70°C
Storage Temperature ......... - 65°C to + 150°C
Voltage On Any Pin
With Respect to Ground ........ - 0.5V to + 7V
Power DiSSipation . . . . . . . . . . . . . . . . . . . . .. 1 Watt
=
DC Characteristics (TA O°C to 70°C; VCC
PARAMETER
SYMBOL
Input Low Voltage
V,L
Input High Voltage
V,H
VOL
VOH
IlL
10FL
ICC
Output Low Voltage
Output High Voltage
Input Load Current
Output Float Leakage
VCC Supply Current
DATA BUS
LSB
MSB
o IE IR X IC VE BU X
-(Video Enable) This flag indicates that video
operation of the CRT is enabled. This flag is
set on a "Start Display" command, and reset
on a "Stop Display" or "Reset" command.
-(Buffer Underrun) This flag is set whenever a
Row Buffer is not filled with character data in
time for a buffer swap required by the display.
Upon activation of this bit, buffer loading
ceases, and the screen is blanked until after
the vertical retrace interval.
* NOTICE:
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied.
= 5V ± 5%)
MAX
MIN
-0.5
2.0
0.8
VCC
+0.5V
0.45
2.4
±10
±10
160
299
UNITS
V
V
V
V
JJA
JJA
mA
TEST CONDITIONS
=
==
=
10L 2.2mA
IOH
400JJA
VIN
VCC to OV
VOUT VCC to 0.45V
T
Capacitance (TA
= 25°C; VCC = GND = OV)
SYMBOL
CIN
CliO
PARAMETER
MIN
Input Capacitance
1/0 Capacitance
AC Characteristics (TA
MAX
UNITS
TEST CONDITIONS
10
20
pF
pF
fC = 1 MHz
Unmeasured pins returned to VSS.
UNITS
TEST CONDITIONS
= O°C to 70°C; VCC = 5.0V ± 5%; GND = OV)
BUS PARAMETERS (Note 1)
Read Cycle
SYMBOL
tAR
tRA
tRR
tRD
tDF
PARAMETER
MIN
Address Stable Before
READ
Address Hold Time for
READ
READ Pulse Width
Data Delay from READ
READ to Data Floating
MAX
0
ns
0
250
20
200
100
ns
ns
ns
ns
MIN
MAX
UNITS
CL
= 150pF
Write Cycle
SYMBOL
tAW
twA
tww
tDW
tWD
Clock Timing
SYMBOL
tCLK
tKH
tKL
tKR
tKF
PARAMETER
Address Stable Before
WRITE
Address Hold Time for
WRITE
WRITE Pulse Width
Data Setup Time for
WRITE
Data Hold Time for
WRITE
PARAMETER
Other Timing
SYMBOL
tcc
tHR
tLC
tAT
tVR
tRI
two
tRO
tLR
tRL
ns
0
250
ns
ns
150
ns
0
ns
MIN
Clock Period
Clock High
Clock Low
Clock Rise
Clock Fall
NOTE 1: AC timings measured at VOH
0
480
240
160
5
5
MAX
UNITS
30
30
ns
ns
ns
ns
ns
TEST CONDITIONS
TEST CONDITIONS
= 2.0, VOL = 0.3, VIH = 2.4 VIL = 0.45.
PARAMETER
Character Code Output
Delay
Horizontal Retrace
Output Delay
Line Count Output Delay
Controll Attribute Output
Delay
Vertical Retrace Output
Delay
INn from RDt
BRDYt from WRt
BRDY-l- from WR-lBS-l- to WR-lWRt to BSt
MIN
0
0
300
MAX
UNITS
150
ns
200
400
ns
ns
275
ns
275
250
250
200
ns
ns
ns
ns
ns
ns
TEST CONDITIONS
= 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL = 50 pF
CL
WAVEFORMS
Typical Dot Level Timing
EXT DOT CLK
CCLK'
CCO·6
l. ______. . . .
FIRST CHARACTER CODE
SECOND CHARACTER CODE
ROM ACCESS
CHARACTER ------------------~IJ~--------------------------~
GENERATOR
FIRST CHARACTER
SECOND CHARACTER
OUTPUT __________________'I'~--------------------------J~--------------------
ATTRIBUTES
& CONTROLS
ATTRIBUTES & CONTROLS
FOR FIRST CHAR.
SHIFT REGISTER SETUP
VIDEO
(FROM SHIFT
REGISTER)
y
ATTRIBUTES
& CONTROLS
(FROM
SYNCHRONIZER)
----y-
FIRST CHARACTER
SECOND CHARACTER
ATTRIBUTES & CONTROLS
FOR FIRST CHAR.
ATTRIBUTES & CONTROLS
FOR SECOND CHAR.
• CCLK IS A MULTIPLE OF THE DOT CLOCK AND AN INPUT TO THE 8276.
ILine Timing
):
LC~3 ~~~~_P_R_ES_E_N_T_L_I_N_E_C_O_U_N_T~__~,.~____________~____________~~XTUNECOUNT
VIDEO
CONTROLS
AND ATTRIBUTES'
VSP, LTEN, HGLT, RVV, GPi\O.1
301
Row Timing
CCLK
LCO-3
INTERNAL
ROW
COUNTER
Frame Timing
CCLK
INTERNAL
ROW
COUNTER
Intenupt Timing
\r~--------------
CCLK
CC~6
LAST RETRACE
CHARACTER
lX
C/P7
\
CS~
/
FIRST RETRACE
CHARACTER
--------~-----¥ ~------------
..
LCO-3
FIRST LINE COUNT
AD
--------------~~---------------
HRTC
INT
INTERNAL
ROW
----------1-----------LAST DISPLAY ROW
COUN~~: --------------:J--~---r------t-IR-------
--J-+-~
302
\
ttAl
Timing for Buffer Loading
BS
WR
Write Timing
BS,C/P
CS
Read Timing
CIP,
INVALID
eo
--X____
VA_L_'D
_ _ __
~AR
WR
DBO·7
DBO·.,
INVALID
Input and Output Waveforms for A.C. Tests
Clock Timing
2.4
0.45
J
....g.o
TEST
2.%r
~.8 POINTS 0.8
~
FOR A.C. TESTING, INPUTS ARE DRIVEN AT 2.4V FOR A LOGIC "1"
AND 0.45V FOR A LOGIC "0." TIMING MEASUREMENTS FOR INPUT
AND OUTPUT SIGNALS ARE MADE AT 2.0V FOR A LOGIC "1" AND
0.8V FOR A LOGIC "0."
See page 725 for ordering information.
303
Information furnished by Western Digital Corporation Is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from Its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
:304
Printed
In
U S.A
Data Communications
Part Number
TR1402ITR1602
TR1863/TR1865
TR1402ITR16021
TR1863ITR1865
WD1983
WD8250
WD2123
BR1941
WD1943IWD1945
PR1472
PT1482
UC1671
WD1931
WD193X
WD1931IWD1933
WD1993
WD1984
Page
Data Communication Protocol Definitions .............................. , 307
Universal Asynchronous ReceiverlTransmitter (UARl) ..................... , 311
Universal Asynchronous Receiver/Transmitter (UARl). . . . . . . . . . . . . . . . . . . . .. 321
Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
(BOARl) Bus Oriented Asynchronous Receiver/Transmitter. . . . . . . . . . . . . . . ..
Asynchronous Communications Element .............................. ,
DEUCE Dual Enhanced Universal Communications Element. . . . . . . . . . . . . . . ..
Dual Baud Rate Clock .............................................. ,
Dual Baud Rate Clock .............................................. ,
(PSAR) Programmable Synchronous & Asynchronous Receiver ............. ,
(PSAl) Programmable Synchronous & Asynchronous Transmitter ............
ASTRO ...........................................................
Asynchronous/Snychronous ReceiverlTransmitter ........................ ,
Synchronous Data Link Controller Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Compatibility Application Notes ...................................... ,
Arinc 429 Receiver/Transmitter and Multi-Character Receiver/Transmitter. . . . ..
Multi-Character Synchronous/Asynchronous Receiver/Transmitter ........... ,
305
333
345
357
373
389
397
405
419
433
447
467
485
509
525
306
DATA COMMUNICATION FAMILIES
UART PSAT PSAR USART BOART DLC
-
Universal Asynchronous Receiver-Transmitter
Programmable Synchronous/Asynchronous Transmitter
Programmable Synchronous/Asynchronous Receiver
Universal Synchronous/Asynchronous Receiver-Transmitter
Bus Oriented Asynchronous Receiver-Transmitter
Data Link Controller
PROTOCOL DEFINITIONS
r
Marking Line - ,
• START and STOP Bits
• 5,6,7,8 Bits/Character
• Plus option of Parity (Even or Odd)
Multiple Character Asynchronous
•
•
•
•
5,6,7, or 8 bits/character
Up to 8 characters/word
Start and Stop bits
Parity inside or outside of word
5
3
7
Parity
2 eight bit characters with start stop bits and parity
Start bit
Stop Bit(s)
8/P Iss
~
J
l
Parity outside data Character
if programmed
Programmed stop bits
Marking line or
next transmission
1st 8 bit Character
2nd 8 bit Character
Previous Fi II or
Data Charac ters
Data or Fill Character
2
Fill or Null
3
4
5
6
,
~
0
- Start of Header
- Synchronization Character
- Start Text
- End of Text
- Block Check Character
Line Marking
----~~~~~~~~~~~~~r.r,-------
• No START and STOP Bits
• 5,6,7,8 Bits/Character
• Plus option of Parity Bit
1
(Even or Odd)
Bisync Characte r(Byte)
Transmission
SOH
SYN
STX
ETX
BCC
2
' - Data Bits
Marking line or ....,
end of previous
character
Synchronous
(Byte Oriented)
r
Start Bit
t r1
Asynchronous
(Character Oriented)
S
0
H
S
Y
N
Data or Fill Character
7
P
2
3
,
4
5
__
6
7
Data or
Fill Characters
P
X~Ft '"--~-T_~_~_
Header
BCC
Synchronous Data Link Control (SDLC)
1
.
Field-------t~
....- - - - - - S D L C Frame-------t..
Flag::: 7E (Hex)
Packet Switching (X.25)
Data Link Control
(Bit Oriented)
14_ _ _ _ _ _ _ _ _ _ _ 1·Frame(Packet) _ _ _ _ _ _ _ _ _ _ _..
~I
Flag
""___- - - - X.25 Level 2 ----~ X.25 Level 3
•
307
User
t.-..
-'-..X.25 Level 2
I~Data·"--·
FUNCTIONALITY COMPATIBILITY GUIDE (PARTIAL
WD
WD1931
WD1933
WD1993
WD2001
FR1502
SIGNETICS
2651
2661
2652
Llsn
AMI
SMC HARRIS
FAIRCHILD
INTEL
MOTOROLA
6852
6854
6856
8251A
H852
6852 8251 A
8273
H854
6854
5025
ZILOG
MOSTEK
SIO
3884
SIO
3884
3282
94141
33512
8294
6859
6894
PLEASE CONTACT FACTORY FOR APPLICATIONS ASSISTANCE.
NOTES: 1. Four chip set.
PIN COMPATIBLE REPLACEMENT GUIDE
WD
TR1402
TR1602
TR1863
SMC
COM2502
COM2502H
COM2017
COM2017H
COM1863
COM8017
COM8018
TR1865
PR1472
PT1482
UC1671 COM1671
WD8250
WD19831
BR1941 2 COM5016
COM50363
WD1943 COM8116
WD1945 COM8136
GI
AY-5-1013A
AY-6-1013
NAT
11
AMI
INTEL SIGNETICS HARRIS INTERSIL
TMS60HY' S1757
2536
TMS6011 4
AY-3-1014A
AY-3-1015D
AY-3-1472B4
AY-3-1482B4
HD6402
INS1671
I NS8250
I NS8251A
IM6402
8251 A
PLEASE CONSULT FACTORY FOR MAXIMUM OPERATING FREQUENCIES AND HIGH-RELIABILITY
SCREENING.
NOTES: 1. WD1983 is ASYNC only.
2. Many frequency selections available. Consult factory for details.
Frequency selection is mask programmable - consult factory for details.
3. Pin 10 on BR1941 is a "no connection".
4. Discontinued product.
308
PRODUCT SELECTION CHART
GENERAL DATA
COMMUNICATIONS
PRODUCTS
PROTOCOL
FEATURES
ARINC429
ASYNCH
ISOCH
SYNCH (BI·SYNC)
SDLC
HDLC
ADCCP
FULL DUPLEX
MAXIMUM 100 kHz
320 kHz
500 kHz
640 kHz
1000 kHz
1500 kHz
2500 kHz
3500 kHz
SELECTABLE CLOCK
BOTH TRANSMIT AND
RECEIVE
INDEPENDENT TRANSMIT
AND RECEIVE
1X
4X
16X
32X
64X
128X
256X
WORD LENGTH SELECT
5,6,7,8 BIT
STOP BIT SELECT 1,1.5,2
PARITY SELECT 0001
EVEN
MATCH/SYN GENERATE
MATCH/SYN DETECT
BREAK DETECT
DOUBLE BUFFERING
TTL COMPATIBLE
ARINC UARTS BOARTS PSARIPSAT USART DLC
W
T T WWWW
P
P
U W W
R
C 0
0
T
0
R R DODD
1
1
1 128 1
1
1
1
1
1
8 9 1 2 9
4
4
6
9
9
9
6
7
3
9
6 8 2 5 8
7
3
8
0
%
2
1
1
2
3
2 % 3 3 0 4
•
•
•
•
•
• • • • •
• • • •
•
•
•
•
•
•
•
• • • • •
•
•
•
•
•
•
•
•
•
•
•
•
•
• • •
•
•
•
•
•
•
•
•
•
• • • •
• • • •
•
• • • •
•
•
•
•
•
•
•
• • •
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • • •
• • • • •
•
•
•
•
•
•
•
•
•
•
• • • • •
•
•
•
•
•
•
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PRODUCT SELECTION CHART
ARiNC UARTS BOARTS PSARIPSAT USART DLC
P
U W W
W
T T WWWW P
GENERAL DATA
COMMUNICATIONS
PRODUCTS
[)
ERROR CHECKING
FRAMING
OVERRUN
UNDERRUN
CRC GENERATE AND
CHECK
R
1
'1
9
6
9
:3
0
2
.)
f)
•
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It
D
1
9
8
4
R
• • • • •
• •
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R D D D
1 1 2 8
8 9 1 2
6 8 2 5
% 330
1
4
7
2
T
1
4
8
2
C
1
7
1
D
1
9
3
1
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6
D
1
9
3
:r5
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PROCESSOR INTERFACE
UNIDIRECTIONAL
BIDIRECTIONAL
CONTROL
PROGRAMMING
DEVICE PINS
BIDIRECTIONAL BUS
MODEM INTERFACE
NUMBER OF SIGNALS 8
..
•
..
• •
6
•
4
2
SPECIAL
FEATURES
SELF LOOP TEST
NRZIOPTION
DIGITAL PHASE LOCK
LOOP
ON BOARD BAUD RATE
GENERATOR
EXTENDED WORD SIZE
TWO FULL DUPLEX
CHANNELS
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Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other riQhts of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
:310
Printed In U.S.A
WESTERN DIGITAL
o
c
R
P
0
R
A
T
I
o
N
TR1402/TR1602
Universal Asynchronous Receiver/Transmitter (UART)
FEATURES
• FULL DUPLEX OR HALF DUPLEX OPERATION
• AUTOMATIC INTERNAL SYNCHRONIZATION
OF DATA AND CLOCK
• AUTOMATIC START BIT GENERATION
• EXTERNALLY SELECTABLE
Word Length
Baud Rate
Even/Odd Parity (ReceiverlVerification Transmitter/Generation)
Parity Inhibit
One, One and One-Half, or Two Stop Bit
Generation (1 V2 at 5 Bit Level for TR1602)
• AUTOMATIC DATA RECEIVED/TRANSMITTED
STATUS GENERATION
Transmission Complete
Buffer Register Transfer Complete
Received Data Available
Parity Error
Framing Error
Overrun Error
• BUFFERED RECEIVER AND TRANSMITTER
REGI~TERS
• THREE-STATE OUTPUTS
Receiver Register Outputs
Status Flags
VCC
vGG
VOO
RRO
RRB
RR7
RR6
RR5
RR4
RR3
RR2
RR1
PE
FE
OE
SFO
RRC
ORR
DR
RI
2
• TTL COMPATIBLE
• PULL-UP RESISTORS ON ALL INPUTS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
APPLICATIONS
PERI PH ERALS
TERMINALS
MINI COMPUTERS
FACSIMILE TRANSMISSION
MODEMS
CONCENTRATORS
ASYNCHRONOUS DATA MULTIPLEXERS
CARD AND TAPE READERS
PRINTERS
DATA SETS
CONTROLLERS
KEYBOARD ENCODERS
REMOTE DATA ACQUISITION SYSTEMS
ASYNCHRONOUS DATA CASSETTES
TRC
EPE
WLS1
WLS2
SBS
CRL
TRB
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TRO
TRE
THRL
THRE
MR
PIN CONNECTIONS
THRL
TRO
RECEIVER
TIMING AND
CONTROL
CONTROL
REGISTER
VCC~
VGG(-12V) ..
VOO(GNO) ..
TR1602/TR1402 BLOCK DIAGRAM
311
TRANSMITTER
TIMINGANO
CONTROL
TRC
THRE
TRE
GENERAL DESCRIPTION
The Universal Asynchronous Receiver/Transmitter
(UART) is a general purpose, programmable or
hardwired MOS/LSI device. The UART is used to
convert parallel data to a serial data format on the
transmit side, and converts a serial data format to
parallel data on the receive side.
The serial format in order of transmission and
reception is a start bit, followed by five to eight
data bits, a parity bit (if selected I) and one, one
and one-half (1602 bit data format only) or two stop
bits.
Three types of error conditions are available on
each received character: parity error, framing error
PIN DEFINITIONS
PIN
NUMBER
NAME
(no valid stop bit) and overrun error.
The transmitter and receiver operate on external
16X clocks, where 16 clock times are equal to one
bit time. The receiver clock is also used to sample
in the center of the serial data bits to allow for line
distortion.
Both transmitter and receiver are double buffered
allowing a one character time maximum between
a data read or write. Independent handshake lines
for receiver and transmitter are also included. All
inputs and outputs are TTL compatible with threestate outputs available on the receiver, and error
flags for bussing multiple devices.
FUNCTION
SYMBOL
1
POWER SUPPLY
VSS
2
POWER SUPPLY
VGG
-12 volts supply
3
POWER SUPPLY
VDD
Ground = OV
4
RECEIVER REGISTER
DISCONNECT
RRD
A high level input voltage, VIH, applied to this line
disconnects the RECEIVER HOLDING REGISTER
outputs from the RR1-8 data outputs (pins 5-12).
5-12
RECEIVER HOLDING
REGISTER DATA
RRaRR1
The parallel contents of the RECEIVER HOLDING
REGISTER appear on these lines if a low-level input
voltage, VIL, is applied to RRD. For character formats of fewer than eight bits received characters
are right-justified with RR1 (pin 12) as the least significant bit and the truncated bits are forced to a low
level output voltage, VOL.
13
PARITY ERROR
PE
A high level output voltage, VOH, on this line indicates that the received parity differ from that which
is programmed by the EVEN PARITY ENABLE
control line (pin 39). This output is updated each
time a character is transferred to the RECEIVER
HOLDING REGISTER. PE lines from a number of
arrays can be bussed together since an output disconnect capability is provided by Status Flag Disconnect line (pin 16).
14
FRAMING ERROR
FE
A high-level output voltage, VOH, on this line indicates that the received character has no valid stop
bit, i.e., the bit (if programmed) is not a high level
voltage. This output is updated each time a character
is transferred to the Receiver Holding Register. FE
lines from a number of arrays can be bussed together
since an output disconnect capability is provided by
the Status Flag Disconnect line (pin 16).
+5 volts supply
312
PIN
NUMBER
NAME·
SYMBOL
FUNCTION
A high-level output voltage, VOH, on this line indicates that the Data Received Flag (pin 19) was not
reset before the next character was transferred to
the Receiver Holding Register. OE lines from a
number of arrays can be bussed together since an
output disconnect capability is provided by the
Status Flag Disconnect line (pin 16).
15
OVERRUN ERROR
OE
16
ST ATUS FLAGS
DISCONNECT
SFD
17
RECEIVER REGISTER
CLOCK
RRC
18
DATA RECEIVED RESET
DRR
A low-level input voltage, VIL, applied to this line
resets the DR line.
19
OAT A RECEIVED
DR
A high-level output voltage, VOH, indicates that an
entire character has been received and transferred
to the RECEIVER HOLDING REGISTER.
20
RECEIVER INPUT
RI
Serial input data. A high-level input voltage, VIH,
must be present when data is not being received.
21
MASTER RESET
MR
This line is strobed to a high-level input voltage, VIH,
to clear the logic. It resets the TRANSMITTER and
RECEIVER HOLDING REGISTERS, the TRANSMITTER REGISTER, FE, OE, PE, DR and sets TRO,
THRE, and TRE to a high-level output voltage, VOH.
THRE
A high-level output voltage, VOH, on this line indicates the TRANSMITTER HOLDING REGISTER
has transferred its contents to the TRANSM ITTER
REGISTER and may be loaded with a new character.
22
TRANSMITTER HOLDING
REGISTER EMPTY
A high-level input voltage, VIH, applied to this pin
disconnects the PE, FE, OE, DR and THRE allowing
them to be buss connected.
The receiver clock frequency is sixteen (16) times
times the desired receiver shift rate.
23
TRANSMITTER HOLDING
REGISTER LOAD
THRL
A low-level input voltage, VIL, applied to this line
enters a character into the TRANSMITTER HOLDING REGISTER. A transition from a low-level input
voltage, VIL. to a high-level input voltage. VIH, transfers the character into the TRANSMITTER REGISTER if it is not in the process of transmitting a character. If a character is being transmitted, the transfer
is delayed until its transmission is completed. Upon
completion, the new character is automatically
transferred simultaneously with the initiation of
the serial transmission of the new character.
24
TRANSMITTER REGISTER
EMPTY
TRE
A high-level output voltage, VOH, on this line indicates that the TRANSMITTER REGISTER has
completed serial transmission of a full character
including STOP bit(s). It remains at this level until
the start of transmission of the next character.
313
PIN
NUMBER
25
26-33
NAME
TRANSMITTER REGISTER
OUTPUT
SYMBOL
TRO
FUNCTION
The contents of the TRANSMITTER REGISTER
(START bit, DATA bits, PARITY bit, and STOP bits)
are serially shifted out on this line. When no data is
being transmitted, this line will remain at a high-level
output voltage, VOH. Start of transmission is defined
as the transition of the START bit from a high-level
output voltage VOH, to a low-level output voltage, VOL·
TRANSMITTER REGISTER
DATA INPUTS
TR1-TRa
The character to be transmitted is loaded into the
TRANSMITTER HOLDING REGISTER on these
lines with the THRL Strobe. If a character of less
than 8 bits has been selected (by WLS 1 and WLS 2),
the character is right justified to the least significant
bit, TR1, and the excess bits are disregarded. A
high-level input voltage, VIH, will cause a highlevel output voltage, VOH, to be transmitted.
34
CONTROL REGISTER
LOAD
CRL
A high-level input voltage, VIH, on this line loads the
CONTROL REGISTER with the control bits (WLS"
WLS 2 , EPE, PI, SBS). This line may be strobed or
hard wired to a high-level input voltage, VIH·
35
PARITY INHIBIT
PI
A high-level input voltage, VIH, on this line inhibits
the parity generation and verification circuits and
will clamp the PE output (pin 13) to VOL. If parity is
inhibited, the STOP bit(s) will immediately follow
the last data bit of transmission.
36
STOP BIT(S) SELECT
SBS
This line selects the number of STOP bits to be transmitted after the parity bit. A high-level input voltage
VIH, on this line selects two STOP bits, and a lowlevel input voltage, VIL, selects a Single STOP bit.
The TR1602 generates 1 V2 stop bits when word
length is 5 bits and SBS is High VIH.
WORD LENGTH SELECT
WLS1-WLS2
These two lines select the character length (exclusive of parity) as follows:
37-38
WLS2
39
EVEN PARITY ENABLE
40
TRANSMITTER REGISTER TRC
WLS1
Word Length
5 bits
VIL
VIL
6 bits
VIH
VIL
7 bits
VIH
VIL
8 bits
VIH
VIH
This line determines whether even or odd PARITY
is to be generated by the transmitter and checked
by the receiver. A high-level input voltage, VIH,
selects even PARITY and a low-level input voltage,
VIL, selects odd PARITY.
EPE
The transmitter clock frequency is sixteen (16) times
the desired transmitter shift rate.
314
u
THAL
THAE
-----.U
15 CLOCK TIMES
AFTEA STAAT OF _
LAST STOP BIT ~
--.I
nI II
rAE
I+- Y2 CLOCK
--.I~~------------I+- 1/2 CLOCK
TAO - - - - - - .
CA1
CA3
CA2
CF1
CF2
TRC I - -
-
; ...... END OF LAST STOP
BIT (COUNT 16)
~
t----
CR4
CF3
~
t----
CA5
CF4
~
CF5
I-f--
t----
~
,I----
l~ ~A
I(
I
CASE I
......
I"--'
TRE
/'
f:\.{~
~THAE L
t---
lV
--., tpd r--
f:\
~
~raJ
V
TAE
I CA4
Lf:\{~
---I j.~
L
tpd
Cf0
/'
TRO
CF4
~
DETAIL II
TAO
f--""
THAL
THRE
CASE I:
....--...
li ~~
-
I
CASE II
TRE
TRO
IF THE POSITIVE TRANSITION OF
THRL OCCURS >500ns PRIOR TO ANY
CLOCK FALLING EDGE (CF3 IN
SAMPLE) THE A, B, C, AND D SIGNALS
WILL BE GENERATED AS SHOWN IN
DETAIL II.
CASE II: IF THE POSITIVE TRANSITION OF
THRL OCCURS ..;500ns PRIOR TO ANY
CLOCK FALLING EDGE (CF3 IN
SAMPLE), THE B, C, AND D SIGNALS
MAY BE GENERATED ON THE
FOLLOWING CLOCK TIME I.E. THE B,
C, AND D SIGNALS AS SHOWN IN
DETAIL II MAY CHANGE AS FOLLOWS:
CF3TOCF4
CF4 TOCF5
CR4 TOCR5
DETAIL I
TRANSMITTER TIMING
315
-I
START (1)
....
:D
STOP
START
STOP
-R-I------~II~------D-A-TA------~I--li~------D-A-T-A------~-----------
~
o
~
FL_A_G_S_P_E_,_F_E,_0_E_(5_)~[~ _____________________X~
....
:D
_R_R_1-_R_R8_A_N_D
__
E_RR_0_R
__
0)
oI\)
________
r
L
DR
-------'
(2)U
DRR
LJ
DETAIL:
o
2
3
4
5
6
7
8
10
9
11
12
13
14
15
0
RRC
NOMINAL
RI
--ll
I...........
~ ~~~~SITION
l~oMINAL
BIT CENTER
1
-i~
PE, FE(3)
I----------------------------....I.... ,...----------1
X
1---------
-u
-i~
(5)
RR1·RR8,OE(3)
-11
r-I---------------
~:
.~.---------------
~ tP~r----
~(
DRR~-------------------,Imlnlr
\~
---1----------------------
~~~--------------(2)-~~~rt---___---___------
LV
M~
I
A ....
(1) SEE APPLICATION FLAGS REPORT NO.1 FOR DESCRIPTION OF START BIT DETECTION
(2) THE DELAY BETWEEN DRR AND DR = td = 500 ns
(3) DR. ERROR FLAGS, AND DATA ARE VALID AT THE
NOMINAL CENTER OF THE FIRST STOP BIT
(4) DRR SHOULD BE HIGH A MINIMUM OF "A" NS (ONEHALF CLOCK TIME PLUS tpd) PRIOR TO DR RISING EDGE
(5) DATA AND OE PRECEDES DR, PE, AND FE FLAGS BY
V2 CLOCK
(6) DATA FLAGS WILL REMAIN SET UNTIL A GOOD CHARACTER IS RECEIVED OR MASTER RESET IS APPLIED.
RECEIVER TIMING
316
(4)
WLS1, WLS2, SSS, PI, EPE
TR8-TR1
r------,
X=---=--==-=-_-._y20V
__ J
/
----- --_
j-------~
\ a.8V
~
__ _
CRLSTf~OSE
tSET
DATA INPUT LOAD CYCLE
CONTROL REGISTER LOAD CYCLE
RRD
SFD
RR1-RR8
"RR1-RR3, ARE DISCONNECTED AT
TRANSITION OF RRD FROM a.8V TO 2.av.
"OUTPUTS PE, FE, cE, DR, THRE ARE DISCONNECTED AT THANSITION OF SFD
FROM a.8V TO 2.aV.
DATA OUTPUT DELAYS
STATUS FLAG OUTPUT DELAYS
317
c
NO
c
TRANSMITTER FLOW CHART
318
1. TURN ON POWER
2. PULSE MASTER
RESET
3. SELECT BAUD
RATE 16XCLK
TRANSFER DATA BITS FROM
RECEIVER REGISTER TO
RECEIVER HOLDING REGISTER
ANDSETOETO
PROPER STATE
SET DR. PE & FE FLAGS TO PROPER STATES
YES
RESET DR
OPERATOR)
ACTION
C
RECEIVER FLOW CHART
319
ORR
'--_ _ _ _ _--1
= VOL
DR-VOL
ABSOLUTE MAXIMUM RATINGS
NOTE: These volta{Jes are measured with respect to GND
Storage Temperature
Plastic ................... - 55°C to + 125°C
Ceramic ................ " - 65°C to + 150°C
VSS Supply Voltage ............. - 0.3V to + 7.0V
Input Voltage at any pin .......... - 0.3V to + 7.0V
Operating Free-Air Temperature
TA Range ....................... O°C to 70°C
Lead Temperature (Soldering, 10 sec.) ....... 3OQ°C
ELECTRICAL CHARACTERISTICS
(VSS
= 5V ± 5%, VDD = OV, VGG = -12V ± 5%)
SYMBOL
ICC
IGG
VIH
VIL
VOH
VOL
IOC
IlL
PARAMETER
OPERATING CURRENT
Substrate Supply Current
Gate Supply Current
LOGIC LEVELS
Logic High
Logic Low
OUTPUT LOGIC LEVELS
Logic High
Logic Low
Output Leakage
(High Impedance State)
Low Level Input Current
TR1602fTR1402
MAX
MIN
60ma
-10ma
CONDITIONS
VSS
VGG
VSS-1.5V
= 5.25V
= -12.6V
= 4.75V
VSS = 4.75V, IOH = 100jAa
VSS = 5.25V, IOL = 1.6 ma
VOUT = OV, VOUT = 5V
SFD = RRD = VIH
VIN = 0.4V
O.BV
VSS
VSS -1.0V
0.4V
± 10jAa
1.6ma
SWITCHING CHARACTERISTICS
(See "Switching Waveforms")
SYMBOL
f clock
tpw
tc
t hold
t set
tpdO
tpdl
PARAMETER
Clock Frequency
Pulse Widths
CRL
THRL
DRR
MR
Coincidence Time
Hold Time
Set-upTime
OUTPUT PROPAGATION
DELAYS
To Low State
To High State
CAPACITANCE
Cin
Inputs
Co
Outputs
* All Iterations
TR1402·*
TR1602-01
MIN.
MAX.
DC
320 KHz
200ns
200ns
200ns
500ns
200ns
20ns
0
TR1602·QO
MIN.
MAX.
DC
320KHz
CONDITIONS
200ns
200ns
200ns
500ns
200ns
20ns
0
650ns
650ns
500ns
500ns
20 pf
20 pf
20 pf
20 pf
See page 725 for ordering information.
320
=
{CL
20pf,
plus one TIL load
f
= 1MHz,
Vin = 5V
WESTERN DIGITAL
CORPORATION
TR1863/TR1865
Universal Asynchronous Receiver/Transmitter (UARn
-I
::D
.....
00
-.....
0)
CN
FEATURES
., SINGLE POWER SUPPLY - +5VDC
., D.C. TO 1 MHZ (64 KB) (STANDARD PART)
TR1863/5
., FULL DUPLEX OR HALF DUPLEX OPERATION
., AUTOMATIC INTERNAL SYNCHRONIZATION
OF DATA AND CLOCK
., AUTOMATIC START BIT GENERATION
., EXTERNALLY SELECTABLE
Word Length
Baud Rate
Even/Odd Parity (ReceiverIVerification Transmitter/Generation)
Parity Inhibit
One, One and One-Half, or Two Stop Bit
Generation (1112 at 5 Bit Level)
.' AUTOMATIC DATA RECEIVEDITRANSMITTED
STATUS GENERATION
Transmission Complete
Buffer Register Transfer Complete
Received Data Available
Parity Error
Framing Error
Overrun Error
• BUFFERED RECEIVER AND TRANSMITTER
REGISTERS
VCC
NC
vSS
RRD
RR8
RR7
RRa
RR5
RR4
RR3
RR2
RR1
PE
FE
OE
SFD
RRC
DRR
DR
RI
2
• THREE·STATE OUTPUTS
Receiver Register Outputs
Status Flags
• TTL COMPATIBLE
• TR1865 HAS PULL-UP RESISTORS ON ALL
INPUTS
APPLICATIONS
• PERIPHERALS
• TERMINALS
• MINI COMPUTERS
• FACSIMILE TRANSMISSION
• MODEMS
• CONCENTRATORS
• ASYNCHRONOUS DATA MULTIPLEXERS
• CARD AND TAPE READERS
• PRINTERS
• DATASETS
• CONTROLLERS
• KEYBOARD ENCODERS
• REMOTE DATA ACQUISITION SYSTEMS
• ASYNCHRONOUS DATA CASSETTES
TRC
EPE
WLS1
WLS2
SSS
CRL
TR8
TR7
TRa
TR5
TR4
TR3
TR2
TR1
TRO
TRE
THRL
THRE
MR
PIN CONNECTIONS
THRL
TRO
RECEIVER
TIMING AND
CONTROL
CONTROL
REGISTER
VCC~
VSS(GND) ...
TR18631TR1865 BLOCK DIAGRAM
321
TRANSMITTER
TIMINGAND
CONTROL
TAC
THRE
TRE
-I
::D
~
en
GENERAL DESCRIPTION
The Universal Asynchronous Receiver/Transmitter
(UARl) is a general purpose, programmable or
hardwired MaS/LSI device. The UART is used to
convert parallel data to a serial data format on the
transmit side, and converts a serial data format to
parallel data on the receive side.
The serial format in order of transmission and
reception is a start bit, followed by five to eight data
bits, a parity bit (if selected) and one, one and onehalf, or two stop bits.
Three types of error conditions are available on each
received character: parity error, framing error (no valid
stop bit) and overrun error.
PIN DEFINITIONS
PIN
NUMBER
1
2
3
NAME
SYMBOL
POWER SUPPLY
NC
GROUND
RECEIVER REGISTER
DISCONNECT
VCC
NC
VSS
RRD
RECEIVER HOLDING
REGISTER DATA
RRaRR1
13
PARITY ERROR
PE
14
FRAMING ERROR
FE
4
5-12
The transmitter and receiver operate on external 16X
clocks, where 16 clock times are equal to one bit
time. The receiver clock is also used to sample in the
center of the serial data bits to allow for line
distortion.
Both transmitter and receiver are double buffered
allowing a one character time maximum between a
data read or write. Independent handshake lines for
receiver and transmitter are also included. All inputs
and outputs are TTL compatible with three-state
outputs available on the receiver, and error flags for
bussing multiple devices.
FUNCTION
+ 5 volts supply
No Internal Connection
Ground = OV
A high level input voltage, VIH, applied to this
line disconnects the RECEIVER HOLDING
REGISTER outputs from the RR1-a data outputs
(pins 5-12).
The parallel contents of the RECEIVER
HOLDING REGISTER appear on these lines if a
lOW-level input voltage, VIL, is applied to RRD.
For character formats of fewer than eight bits
received characters are right-justified with RR1
(pin 12) as the least significant bit and the
truncated bits are forced to a low level output
voltage, VOL.
A high level output voltage, VOH, on this line
indicates that the received parity differ from
that which is programmed by the EVEN PARITY
ENABLE control line (pin 39). This output is
updated each time a character is transferred
to the RECEIVER HOLDING REGISTER. PE
lines from a number of arrays can be bussed
together since an output disconnect capability
is provided by Status Flag Disconnect line
(pin 16).
A high-level output voltage, VOH, on this line
indicates that the received character has no
valid stop bit, i.e., the bit (if programmed) is not
a high level Voltage. This output is updated each
time a character is transferred to the Receiver
Holding Register, FE lines from a number of
arrays can be bussed together since an output
disconnect capability is provided by the Status
Flag Disconnect line (pin 16).
322
PIN DEFINITIONS
PIN
NUMBER
NAME
SYMBOL
15
OVERRUN ERROR
OE
16
STATUS FLAGS
DISCONNECT
SFD
17
RRC
19
RECEIVER REGISTER
CLOCK
DATA RECEIVED
RESET
DATA RECEIVED
DR
20
RECEIVER INPUT
RI
21
MASTER RESET
MR
22
TRANSMITTER
HOLDING REGISTER
EMPTY
THRE
23
TRANSMITTER
HOLDING REGISTER
LOAD
THRL
24
TRANSMITTER
REGISTER EMPTY
TRE
18
FUNCTION
A high-level output voltage, VOH, on this line
indicates that the Data Received Flag (pin 19)
was not reset before the next character was
transferred to the Receiver Holding Register.
OE lines from a number of arrays can be bussed
together since an output disconnect capability
is provided by the Status Flag Disconnect line
(pin 16).
A high-level input voltage, VIH, applied to this
pin disconnects the PE, FE, OE, DR and THRE
allowing them to be buss connected.
The receiver clock frequency is sixteen (16)
times the desired receiver shift rate.
A low-level input voltage, VIL, applied to this
line resets the DR line.
A high-level output voltage, VOH, indicates that
an entire character has been received and
transferred to the RECEIVER HOLDING
. REGISTER.
I Serial input data. A high-level input voltage, VIH,
must be present when data is not being
received.
This line is strobed to a high-level input voltage,
VIH, to clear the logic. It resets the TRANSMITTER and RECEIVER HOLDING REGISTERS, the TRANSMITTER REGISTER, FE, OE,
PE, DR and sets TRO, THRE, and TRE to a
high-level output voltage, VOH.
A high-level output voltage, VOH, on this line
indicates the TRANSMITTER HOLDING REGISTER has transferred its contents to the
TRANSMITTER REGISTER and may be loaded
with a new character.
A low-level input voltage, VIL, applied to this
line enters a character into the TRANSMITTER
HOLDING REGISTER. A transition from a lowlevel input voltage, VIL. to a high-level input
voltage, VIH, transfers the character into the
TRANSMITTER REGISTER if it is not in the
process of transmitting a character. If a
character is being transmitted, the transfer is
delayed until its transmission is completed.
Upon completion, the new character is
automatically transferred simultaneously with
the initiation of the serial transmission of the
new character.
A high-level output voltage, VOH, on this line
indicates that the TRANSMITTER REGISTER
has completed serial transmission of a full
character including STOP bit(s). It remains at
this level until the start of transmission of the
next character.
ORR
...................................................................
323
PIN DEFINITIONS
PIN
NUMBER
25
26-33
TRANSMITTER
REGISTER OUTPUT
FUNCTION
SYMBOL
NAME
TRO
TRANSMITTER
REGISTER DATA
INPUTS
34
CONTROL REGISTER
LOAD
CRL
35
PARITY INHIBIT
PI
36
STOP BIT(S) SELECT
SBS
WORD LENGTH
SELECT
WLS2-WLS1
EVEN PARITY
ENABLE
EPE
TRANSMITTER
TRC
37-38
39
40
I REGISTER
324
The contents of the TRANSMITTER REGISTER
(START bit, DATA bits, PARITY bit, and STOP
bits) are serially shifted out on this line. When
no data is being transmitted, this line will
remain at a high·level output voltage, VOH. Start
of transmission is defined as the transition of
the START bit from a high·level output voltage
VOH, to a low·level output voltage VOL.
The character to be transmitted is loaded into
the TRANSMITTER HOLDING REGISTER on
these lines with the THRL Strobe. If a character
of less than 8 bits has been selected (by WLS1
and WLS2), the character is right justified to the
least significant bit, TR1, and the excess bits
are disregarded. A high·level input voltage, VIH,
will cause a high·level output voltage, VOH, to
be transmitted.
A high·level input voltage, VIH, on this line
loads the CONTROL REGISTER with the
control bits (WLS1, WLS2, EPE, PI, SBS). This
line may be strobed or hard wired to a high·level
input voltage, VIH.
A high·level input voltage, VIH, on this line
inhibits the parity generation and verification
circuits and will clamp the PE output (pin 13) to
VOL. If parity is inhibited, the STOP bit(s) will
immediately follow the last data bit of trans·
mission.
This line selects the number of STOP bits to be
transmitted after the parity bit. A high·level
input voltage VIH, on this line selects two STOP
bits, and a low-level input voltage, VIL, selects a
single STOP bit. The TR1863 and TR1865
generate 1112 stop bits when word length is 5
bits and SBS is High VIH.
These two lines select the character length
(exclusive of parity) as follows:
WLS1
Word Length
WLS2
5 bits
6 bits
7 bits
8 bits
This line determines whether even or odd
PARITY is to be generated by the transmitter
and checked by the receiver. A high·level input
voltage, VIH, selects even PARITY and a low·
level input voltage, VIL, selects odd PARITY.
The transmitter clock frequency is sixteen (16)
times the desired transmitter shift rate.
THRL
THRE----...,U
TRE
~
~ V2 CLOCK
-.l
15 CLOCK TIMES
AFTER START OF
_________________L_A_S_T_S_T_O_P_B_IT___
I
_________________
(_1)_::fl~~_I
~ f..--
TRO
V2 CLOCK
~_____ END OF LAST STOP
L-_ _ _....;;._ _ _ _ _ _ _ _ _
,----1
..
BIT (COUNT 16)
(1) NOT VALID FOR 5.0 MHZ OPTION
CR1
TRC r---
-
~
I--
I--
CF5
r--
i--
r---'1
~
"""--
CF4
CF3
CF2
CR5
CR4
CR3
CR2
CF1
I--
I----
L~ ~A
THRE
(
I
CASE I
.......
i'--"
TRE
f:\{~
~
L
/"
~
Is)
~
r--...
lV
--.., tpd r--
f::\
~
.-/
~~
I CR4
Lf:\ {~
....jtPd~
TRE
/"
TRO
CF4
DETAIL II
\.V
TRO
L
.-/
THRL
THRE
CASE I:
..---.
U~~
~
I
CASE II
TRE
TRO
IF THE POSITIVE TRANSITION OF
THRL OCCURS >250ns PRIOR TO ANY
CLOCK FALLING EDGE (CF3 IN
SAMPLE) THE A, 8, C, AND D SIGNALS
WILL 8E GENERATED AS SHOWN IN
DETAIL II.
CASE II: IF THE POSITIVE TRANSITION OF
THRL OCCURS .. 250ns PRIOR TO ANY
CLOCK FALLING EDGE (CF3 IN
SAMPLE), THE 8, C, AND D SIGNALS
MAY 8E GENERATED ON THE FO~
LOWING CLOCK TIME I.E. THE 8, C,
AND D SIGNALS AS SHOWN IN
DETAIL MAY CHANGE AS FOLLOWS:
CF3TOCF4
CF4 TO CF5
CR4 TOCR5
NOTE: IT IS ADVISA8LE TO CONSIDER
CASE II FOR fCLOCK > 4.0 MHZ.
DETAIL I
TRANSMITTER TIMING
325
START (1)
-R-I------~I
STOP
STOo START
~1------D-A-TA-------rI~11~------D-A-T-A------~-----------
F_LA_G_S_P_E~,_F_E,_O_E~(5~)~r-~.
_R_R_1-_R_R8_A_N_D
__
E_RR_O_R
__
__________________
~X~
_________
L
_D_R(~19~)______________________~r-
(2)U
DRR(18)
LJ
DETAil:
6
2
7
8
10
9
11
12
13
14
15
0
RRC
NOMINAL
RI
~
"N
----l,..1__.L~~~
---H
-
11
STOP BIT
TRANSITION
---t:
PE'F~~
:OMINAL BIT CENTER
I~
I
____________________________
~~X:~~~~~~~~~~~~~~~~~~~=
I
I
~~
~I
RR1-R';f~_E(_3)_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ~"';""-------------------
-----,0------
~ll-
-;"'ltP~~
DRR
~~~---_ _-------------(2)-~__ ~rt~---D~
~
I
A ....
(1) SEE APPLICATION FLAGS REPORT NO.1 FOR DESCRIPTION OF START BIT DETECTION
(2) THE DELAY BETWEEN DRR AND DR
td
500 NS
(3) DR. ERROR FLAGS, AND DATA ARE VALID AT THE
NOMINAL CENTER OF THE FIRST STOP BIT
(4) DRR SHOULD BE HIGH A MINIMUM OF "A" NS (ONEHALF CLOCK TIME PLUS tpd) PRIOR TO THE RISING
EDGEOF DR
(5) DATA AND OE PRECEDES DR, PE, AND FE FLAGS BY
V2 CLOCK
(6) DATA FLAGS WILL REMAIN SET UNTIL A GOOD CHARACTER IS RECEIVED OR MASTER RESET IS APPLIED.
= =
RECEIVEFl TIMING
326
(4)
_____--_
WLS1, WLS2, SBS, P1, EPE
TRB-TR1
r------,
-X=-----==~---y2.0V
__ J /
--------
,j'--------t
\ '-O.BV
__ _
tsat
CONTROL REGISTER LOAD CYCLE
DATA INPUT LOAD CYCLE
RRD
SFD
*RR1-RRB
"OUTPUTS PE, FE, OE, DR, THRE ARE DISCONNECTED AT TRANSITION OF SFD
FROM O.BV TO 2.0V.
"RR1-RR3, ARE DISCONNECTED AT
TRANSITION OF RRD FROM O.8V TO 2.0V.
DATA OUTPUT DELAYS
STATUS FLAG OUTPUT DELAYS
327
c
NO
c
TRANSMITTER FLOW CHART
328
1. TURN ON POWER
2. PULSE MASTER
RESET
3. SELECT BAUD
RATE 16XCLK
4. SET CONTROL BITS
TRANSFER DATA BITS FROM
RECEIVER REGISTER TO
RECEIVER HOLDING REGISTER
ANDSETOETO
PROPER STATE
SET DR. PE & FE FLAGS TO PROPER STATES
YES
RESET DR
OPERATOR)
ACTION
C
RECEIVER FLOW CHART
329
L..-_ _ _ _ _---1
DRR = VOL
DR-VOL
ABSOLUTE MAXIMUM RATINGS
NOTE: These voltages are measured with respect to GND
Storage Temperature
Plastic. . . . . . . . . . . . . . . . . .. - 55°C to + 125°C
Ceramic .................. -65°Cto +150°C
VCC Supply Voltage ............. - 0.3V to + 7.0V
Input Voltage at any pin .......... - 0.3V to + 7.0V
Operating Free-Air Temperature
TA Range ....................... O°C to 70°C
Lead Temperature (Soldering, 10 sec.) ....... 300°C
ELECTRICAL CHARACTERISTICS
(VCC
= 5V ±
SYMBOL
5%, VSS
= OV)
IlL
PARAMETER
OPERATING CURRENT
Supply Current
LOGIC LEVELS
Logic High
Logic Low
OUTPUT LOGIC LEVELS
Logic High
Logic Low
Output Leakage
(High Impedance State)
Low Level Input Current
IIH
High Level Input Current
ICC
VIH
VIL
VOH
VOL
IOC
MIN
TR1863/5
MAX
35ma
CONDITIONS
VCC = 5.25V
2.4V
0.6V
2.4V
0.4V
± 10Ila
100lla
1.6ma
10lla
-101la
3:30
VCC = 4.75V
VCC = 4.75V, IOH = 100 Ila
VCC = 5.25V, IOL = 1.6 ma
VOUT = OV, VOUT = 5V
SFD = RRD = V1H
VIN = 0.4V TR 1865 only
VIN = VIL, TR 1863 only
VIN = VIH, TR 1863 only
SWITCHING CHARACTERISTICS
(See "Switching Waveforms")
SYMBOL
fclock
tpw
PARAMETER
MIN
MAX
TR1863-00
DC
1.0 MHz
TR1863-02
DC
2.5 MHz
TR1863-04
DC
3.5 MHz
5.0 MHz
Clock Frequen"cy
CONDITIONS
VCC
= 4.75V
TR1863-06
DC
TR1865-00
DC
1.0 MHz
with internal pull-ups on all inputs
TR1865-02
DC
2.5 MHz
with internal pull-ups on all inputs
TR1865-04
DC
3.5 MHz
with internal pull-ups on all inputs
TR1865-06
DC
5.0 MHz
with internal pull-ups on all inputs
Pulse Widths
CRL
200ns
THRL
200ns
DRR
200ns
MR
500ns
tc
Coincidence Time
200ns
thold
Hold Time
tset
Set Time
OUTPUT PROPAGATION
tpdO
To Low State
250ns
tpd1
To High State
250ns
20 ns
0
DELAYS
CL
= 20 pf, plus one TTL load
CAPACITANCE
Cin
Co
Inputs
20 pf
f
Outputs
20 pf
f
= 1 MHz, VIN = 5V
= 1 MHz, VIN = 5V
See page 725 for ordering information.
331
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any Infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
332
Printed In U S.A
WESTERN DIGITAL
CORPORATION
TR1602/TR1863/TR1865 MOS/LSI Application Notes
Asynchronous Receiver/Transmitter
INTRODUCTION
The start element is a single logic zero (space) data
bit that is added to the front of each character. The
stop element is a logic one (mark) that is added to the
end of each character. The stop element is maintained until the' next data character is ready to be
transmitted. (Asynchronous transmission is often
referred to as start-stop transmission for obvious
reasons). Although there is no upper limit to the
length of the stop element, there is a lower limit that
depends on the system characteristics. Typical lower
limits are 1.0, 1.42 or 2.0 data bit intervals, although
most modern systems use 1.0 or 2.0. The negative
going transition of the· start element defines the
location of the data bits in one character. A clock
source at the receiver is reset by this transition and is
used to locate the center of each data bit.
The rate at which asynchronous data is transmitted is
usually measured in baud, where a baud is defined to
be the reciprocal of the shortest signal element
(usually one data bit interval). It is interesting to note
that the variable stop length is what makes the baud
rate differ from the bit rate. For synchronous transmission, each element is one bit in'length so that the
baud rate equals the bit rate. The same is true for
The transfer of digital data over relatively long
distances is generally accomplished by sending the
data in serial form thru a single communications
channel using one of two general transmission
techniques; asynchronous or synchronous. Synchronous data transmission requires that a clock
signal be transmitted with the data in order to mark
the location of the data bits for receiver. A specified
clock transition (either rising or falling) marks the
start of each data bit interval as shown in Figure 1. In
addition, special synchronization data patterns are
added to the start of the transmission in order for the
receiver to I ocate the first bit of the message. With
synchronous transmission, each data bit must follow
contiguously after the sync word, since one data bit
is assumed for every clock period.
With asynchronous transmission, a clock signal is
not transmitted with the data and the characters
need not be contiguous. In order for the receiver to
properly recover the message, the bits are grouped
into data characters (generally from 5 to 8 bits in
length) and synchronizing start and stop elements
are added to each character a$ shown in Figure 2.
ONE
DATA
BIT
INTERVAL
CLOCK SIGNAL
-----~
TYltlCAL •
----------
BIT
SYNC ItATTERN
,
DATA SIGNAL
FIRST DATA
BIT
Figure 1. Synchronous Data
FIRST DATA BIT
STOP ELEMENT
STOP ELEMENT
J
+
J
, ----------\
START
ELEMENT
FIRST
DATA
BIT
LAST
DATA
BIT
Figure 2. Asynchronous Data
333
ONE. BIT
CHARACTER
(00100000)
/ "
FIRST
LAST
DATA
DATA
BIT
BIT
LAST
DATA
BIT
asynchronous transmission if the stop element is
always one bit in duration (this is referred to as
isochronous transmission). However, when the stop
code is longer than one bit, as shown in Figure 3, the
baud rate differs from the bit rate.
baud rates (10K baud or higher depending on the
length of the wire, type of line drivers, etc.) while it is
generally limited to approximately 2K baud over the
telephone network. When operating over the
telephone network, a modem is required to convert
the data pulses to tones that can be transmitted
through the network.
One of the major limiting factors in the speed of
asynchronous transmission is the distortion of the
signal elements. Distortion is defined as the time
placement between the actual signal level transItion and the nominal transition (.6. t), divided by the
nominal data bit interval (See Figure 4).
The nominal data bit interval is equal to the reciprocal
of the nominal transmission baud rate and all data
transitions should ideally occur at an integer number
of intervals from the start bit negative going transition. Actual data transitions may not occur at these
nominal points in time as shown in the lower
waveform of Figure 4. The distortion of any bit
transition is equal to.6. t x NOMINAL BAUD RATE.
This distortion is generally caused by frequency jitter
and frequency offset in the clock source used to
generate the actual waveform as well as transmission channel, noise, etc. Thus, the amount of
distortion that can be expected on any asynchronous
signal depends on the device used to generate the
Signal and the characteristics of the communication
channel over which it was sent. Electronic signal
generators can be held to less than 1% distortion
while electromechanical devices (such as a teletype)
typically generate up to 20% distortion. The transmission channel may typically add an additional 5%
to 15% distortion.
Each character in Figure 3 is 11 data bit intervals in
length, and if 15 characters are transmitted per
second, then the shortest signal element (one data
bit interval) is 66.6 ms/11 = 6.06 ms; giving a rate of
116.06 ms = 165 baud. However, since only 10 bits of
information (8 data bits, one start bit and 1 stop bit)
are transmitted every 66.6 msec, the bit rate is 150
bit/sec. (Even though the stop element lasts for two
data intervals, it still is only one bit of information.)
There are several reasons for using asynchronous
transmission. The major reason is that since a clock
signal need not be transmitted with the data, transmission equipment requirements are greatly simplifieq. (Note, however, that an independent clock
source is still required at both the transmitter and
receiver). Another advantage of asynchronous transmission is that characters need not be contiguous in
time, but are transmitted as they become available.
This is a very valuable feature when transmitting data
from manual entry devices such as a keyboard. The
major disadvantage of asynchronous transmission is
that it requires a very large portion of the communication channel bandwidth for the synchronizing
start and stop elements (a much smaller portion of
the bandwidth is required for the sync words used in
synchronous transmission).
Asynchronous transmission over a simple twisted
wire pair can be accomplished at moderately high
START ELEMENT
(ONE DATA BIT INTERVAL)
STOP ELEMENT
...
~ ==~B~T~H~:~T~R====]
AT l!i CHARACTER/SEC = 66.6 ms
6.06 msec
Figure 3.
334
.I
NOMINAL DATA
BIT INTERVAL
Figure4A
r
r
I £
STOP
START ELEMENT
ELEMENT
START ELEMENT
~~==~:~~=======~~==~~:~======
I
I
CHARACTER INTERVAL
4
•
Figure4B
The distortion previously described referred only to a
single character as all measurements were referenced to the start element transition of that character. However, there may also be distortion between
characters when operating at the maximum possible
baud rate (Le., stop elements are of minimum length).
This type o'f distortion is usually measured by the
minimum character interval as shown in Figure 4B.
start bit negative going transition. However, due to
receiver inaccuracies, the exact center may not be
properly located. In electromechanical devices such
as teletypes, the inaccuracy may be due to
mechanical tolerances or variations in the power line
frequency. With electronic receivers, the inaccuracies are due to frequency offset, jitter and
resolution of the clock source used to find the bit
centers. (The bit centers are located by counting
clock pulses). For example, even if the receiver clock
had no jitter or offset, and it was 16 times the baud
rate, then the center of the bit could only be located
within 1/16 of a bit interval (or 6.25%) due to clock
resolution. However, by properly phasing the clock,
this tolerance can be adjusted so that the sample will
always be within ± 3.125% of the bit center. Thus,
signals with up to 46.875% distortion could be
received. This number (the allowable receiver input
distortion) is often referred to as the receiver
distortion margin. Electromechanical receivers have
distortion margins of 25 to 30%. The receiver must
also be prepared to accept a new character after the
minimum character interval. Most receivers are
specified to operate with a minimum character interval distortion of 50%.
The minimum character interval distortion is generally specified as the percentage of a nominal data bit
interval that any character interval may be shortened
from its nominal length. Since many of the same
parameters that cause distortion of the data bits are
also responsible for the character length distortion,
the two distortions are often equal. However, some
systems may exhibit character interval distortions of
up to 50% of a data bit interval. This parameter is
important when operating at the maximum baud rate
since the receiver must be prepared to detect the
next start bit transition after the minimum character
interval.
Asynchronous receivers operate by locating the
nominal center of the data bits as measured from the
335
TR1602 OPERATION··
format with the start, parity and stop bits removed.
Three error flags are also provided to indicate if the
parity was in error, a valid stop bit was not decoded or
the last character was not unloaded by the external
device before the next character was received (and
therefore the last character was lost). The receiver
clock is set at 16 times the transmitter baud rate.
Both the transmitter and receiver have double
character buffering so that at least one complete
character interval is always available for exchange of
the characters with the external devices. This double
buffering is especially important if the external
device is a computer, since this provides a much
longer permissible interrupt latency time (the time
required for the computer to respond to the interrupt).
The status of the transmitter buffer and the receiver
buffer (empty or full) is also provided as an output.
Another feature of the TR1602 is that the control
information can be strobed into the transmitter and
receiver and stored internally. This allows a common
bus from a computer to easily maintain the controls
for a large number of transmitter/receivers.
The WDC TR1602 is designed to transmit and receive
asynchronous data as shown in Figure 5. Both the
transmitter and the receiver are in one MOS CHIP,
packaged in a 40 lead ceramic DIP. The array is
capable of full duplex (simultaneous transmission
and reception) or half duplex operation.
The transmitter basically disassembles parallel data
characters into a serial asynchronous data system.
Control lines are included so that the characters may
be 5, 6, 7 or 8 bits in length, have an even or odd parity
bit, and have either one or two* stop bits. Furthermore, the baud rate can be set anywhere between DC and 20K baud by providing a transmit clock
at 16 times the desired baud rate.
* 1-1/2 with 5 bit code
** All references to the TR1602 operation also apply
to the TR1863/TR1865 operation.
The receiver assembles the asynchronous characters
into a parallel data character by searching for the
start bit of every character, finding the center of every
data bit, and outputting the characters in a parallel
RECEIVER
STATUS
TRANSMITTER
STATUS
DATA ERROR FLAGS
TRANSMITTER
TR1602
-
i
I
CLOCK
I
TRANSMITTER
I
r-~----------.-~
I
I
IASYNCHRONOUS'
CONTROL--~----~
L
J
DATA
ERROR
FLAGS
1 - -....-.. OUT
18
I
~_ _I-+-_ CONTROL
I
Is
I
I
I
PARALLEL DATA
I+-;"";--IN
8
1
1
I
TRANSMITTER
........- - - - C L O C K
1
--
RECEIVER CLOCK
PARALLEL DATA
RECEIVER
I SERIAL
1
~~~~~VER_.:.....I_ - - - '
fAlso2l
l
IDATA
I
I
OUT
-
J
_ _ _ _I
- - _-.J
TRANSMITTER
STATUS
RECEIVER
STATUS
Figure 5
336
The TR1602 data and error flag outputs are designed
for direct compatibility with bus organized systems.
This feature is achieved by providing completely TTL
compatible Three-state outputs (no external components are required). Three-state outputs may be set
to a logic ollie or logic zero when enabled, or set to an
open circuit (very high impedance) when disabled. A
separate control line is provided to enable the data
outputs and another one to enable the error flags so
that the data outputs can be tied to a separate bus
from the flag outputs.
Table 1.
CONTROL DEFINITION
CHARACTER FORMAT
CONTROL WORD
WW
L L
PES
S
2
I
S
1
000
000
000
000
001
001
010
010
010
010
011
011
100
100
100
100
The TR1602 inputs are also directly compatible with
TTL logic elements without any external components. TR1863 require pullups on inputs.
'TR1602 DESCRIPTION
Figure 6 is a block diagram of the transmitter portion
of the TR1602. Data can be loaded into the
Transmitter Holding Register whenever the Transmitter Holding Register Empty (THRE) line is at a logic
one, indicating that the Transmitter Holding Register
is empty. The data is loaded in by strobing the
Transmitter Holding Register Load (THRL) line to a
logic zero. The data is automatically transferred to
the Transmitter Register as soon as the Transmitter
Register becomes empty. The desired start, stop and
parity bits are then added to the data and serial
transmission is started. The number of stop bits and
the type of parity bit is under control of the Control
Register. The state of the control lines is loaded into
the Control Register when the Control Register Load
(CRL) line is strobed to a logic one. The 5 control
lines allow 24 different character formats as shown in
Table 1. These 24 formats cover almost all of the
transmission schemes presently in use.
A Master Reset (MR) input is provided which sets the
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
P
B START DATA PARITY STOP
E
S
o 0
o
1
1
1
0
1
x 0
x
1
o
0
1
1
0
1
o
1
x 0
x 1
o 0
BIT
BITS
BIT
BITS
5
5
5
5
5
5
6
6
6
6
6
6
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
1
1.5
1
1.5
1
1.5
1
7
o
1
7
1
1
x
x
0
1
7
0
7
7
1
o 0
o 1
1
1
x
x
7
8
8
0
1
8
0
8
8
1
8
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
The TR1602 Transmitter output will have less than
1 % Distortion at baud rates of up to 20K baud
(assuming the Transmitter Register Clock is perfect)
and is, therefore, compatible with virtually all other
asynchronous receivers.
transmitter to the idle state whenever this line is
strobed to a logic one. In addition, a Status Flag
Disconnect (SFD) line is provided. When this signal is
at a logic one, the THRE output is disabled and goes
to a high impedance. This allows the THRE outputs
of a number of arrays to be tied to the same data bus.
Figure 8 is a block diagram of the Receiver portion of
the TR1602. Serial asynchronous data is provided to
the Receiver Input (RI). A start bit detect circuit
continually searches for a logic one to logic zero
transition while in the idle state. When this transition
is located, a counter is reset and allowed to count
until the center of the start bit is located. If the input
is still a logic zero at the center, the signal is
assumed to be a valid start bit and the counter
continues to count to find the center of all subsequent data and stop bits. (Verification of the start
bit prevents the receiver from assembling an
erroneous data character when a logic zero noise
spike is presented to the Receiver Input). The Receiver is under control of the Control Register described in the previous paragraph. This register
Figure 7 illustrates the relative timing of the transmitter signals. After power turn-on, the master reset
should be strobed to set the circuits to the idle state.
The external device can then set the transmitter
register data inputs to the desired value and after the
data inputs are stable, the load pulse is applied. The
data is then automatically transferred to the
Transmitter Register where the start, stop and parity
(if required) bits are added and transmission is
started. This process is then repeated for each
subsequent character as they become available. The
only timing requirement for the external device is that
the data inputs be stable during the load pulse (and
20 nsec after).
337
salON UO!IB:>UddV 598 ~HJ.1£98 ~HJa09 ~H!
~
TRANSMITTER REGISTER OUT
(25) (TRO)
STATUS FLAG DISCONNECT (16) (SFD)
)~
TRANSMITTER
HOLDING REG-
4
MASTER RESET (21) (MR)
ISTER EMPTY
(22) (THRE)
START
TRANSMITTER REGISTER CLOCK (40) (TRC)
4
TRANSMITTER REGISTER EMPTY (24) (TRE)
TRANSMITTER REGISTER
DATA INPUTS
(26-33) (TRI TO TRa)
TRANS
8----'-' ~~~D
TRANS
REG
14 PARITY
I
~
(.,)
..
INHIBIT (35) (PI)
(X)
4
TRANSMITTER HOLDING REG-
CONTROL
CONTROL
REG
ISTER LOAO (23) (THRL)
(EPE)
STOP BIT(S) SELECT (36)
4
4
STOP
BIT(S)
EVEN PARITY ENABLE (39)
(SBS)
WORD LENGTH SELECT (37-38)
2 (WLSI-WLS2)
i
CONTROL REGISTER LOAD (34)
(CRL)
Figure 6. Transmitter Block Diagram
---.Jr~11---_ _ _ _ _ _ _ __
MASTER RESET
__________________~X~__________~X~_______
T_R_A_N_S_M_IT_T_E_R_R_E_G_I_ST_E_R
__
D_A_T_A_I_N_PU_T_S_____________ _
u
u
TRANSMITTER HOLDING REGISTER LOAD
U
1r
ITRANSMITTER HOLDING REGISTER EMPTY
~
1
-----,1 I
1/2 EXTERNAL CLOCK
START
j
1/2 EXTERNAL CLOCK
-1 ~,
1/2 EXTERNAL CLOCK
START
DATA
*
I
EXTERNAL CLOCK>
jL j
L . . . -. L . . . - - I_ D A T A - - - - - - I
~
STOP
TRANSMITTER REGISTER OUTPUT
[l,_ _-----'I
------>1
TRANSMITTER REGISTER EMPTY
Figure 7. Transmitter Timing Diagram
As each received character is transferred to the
Holding Register, the Data Received (DR) line is set to
a logic one indicating that the external device may
sample the data output. When the external device
samples the output, it should strobe the Data
Received Reset (ORR) line to a logic zero to reset the
DR line. If the DR line is not reset before a new
character is transferred to the Holding Register (Le., a
character is lost) the Overrun Error line will be set to a
logic one and held until the next character is loaded
into the Holding Register: The timing for all of the
Receiver functions is obtained from the external
Receiver I~egister Clock which should be set at 16
times the baud rate of the transmitter:
controls the number of data bits, number of stop bits,
and the type of parity as described in Table 1. The
word length gating circuit adjusts the length of the
Receiver Register to match the length of the data
characters. A parity check circuit checks for even or
odd parity if parity was added by the Transmitter: If
parity does not check a Parity Error signal wi II be set
to a logic one and this signal will be held until the
next character is transferred to the Holding Register:
A circuit is also provided that checks the first stop bit
of each character: If the stop bit is not a logic one, the
Framing Error line will be set to a logic one and held
until the next character is transferred to the Holding
Register: This feature permits easy detection of a
break character (null character with no stop element).
339
salON uoneonddv S98 ~klJJ&98 ~kI.lre09 ~kI!
INTERNAL CONTROLS
FROM CONTROL REGISTER
~
RECEIVER REGISTER
CLOCK (RRC)
RECEIVER REGISTER
1
(17)
1
DISCONNECT (RRD)
[l
WORD
LENGTH
GATING
RECEIVER
REG
r
8
RECEIVER INPUT
(Rl)
(20)
START/STOP
DETECT &
BIT COUNTER
~
(4)
CEIVER
HOLDING
REG
RECEIVER
HOLDING REG
DATA
DATA
(RR1-RRB)
(5-12)
~
o
FRAMING ERROR
(FE)
PARITY
CHECK
(14)
DATA
RECEIVED
DETECT
•
PARITY ERROR
(PE)
(13)
•
DATA RECEIVED
RESET
(ORR)
(18)
END OF
CHARACTER
DATA RECEIVED
(DR)
(19)
OVERRUN ERROR (15)
(OE)
STATUS FLAG DISCONNECT
(SFD) (16)
Figure 8. Receiver Block Diagram
•
Figure 9 illustrates the relative timing of the Receiver
signals. A Master Reset strobe places the unit in the
idle mode and the Receiver then begins searching for
the first start bit. After a complete character has been
decoded, the data output and error flags are set to
the proper level and the Data Received (DR) line is set
to a logic one. Although it is not apparent in Figure 9,
the data outputs are set to the proper level one half
clock period before the DR and error flags, which are
set in the center of the first stop bit. The Data
Heceived Reset pulse resets the DR line to a logic
z.ero. Data can be strobed out at any time before the
next character has been disassembled.
The TR1602 Receiver uses a 16X clock for timing
purposes. Furthermore, the center of the start bit is
defined as clock count 7-1/2. Therefore, if the receiver
clock is a symmetrical square wave as shown in
Figure 10, the center of the bits will always be
located within ± 3.125% (assuming a perfect input
clock) thus giving a receiver margin of 46.875%.
'l
In Figure '10, the start bit could have started as much
as one complete clock period before it was detected,
as indicated by the shaded area of the negative going
transition. Therefore, the exact center is also
unknown by the shaded area around the sample
point. This turns out to be ± 1/32 = ± 3.125%.
If the receiver clock is not perfect, then the receiver
distortion margin must be further reduced. For
example, if the clock had 1.0% jitter, 0.1 % offset and
the positive clock pulse was only 40% of the clock
cycle; then, for a 10 element character, the clock
would add:
1.0% + (0.1% x 10) + 0.1 (1116)
(Jitter)
(Offset)
= 2.3% Distortion
(Non-symmetrical
Clock)
(The frequency offset was multiplied by the number
of elements per character since the offset is
cumulative on each element.
~~---------MASTER RESET
START
STOP
START
DATA
DATA
STOP
RECEIVER DATA INPUT
DATA RECEIVED
L_
(DR)
__R_E_C_EI_V_E__
R_H_O_L_D_IN_G__
RE_G_I_ST_E_R__
DA_T_A__
O_U_T______
_________
~!'
AN_D.__E_R_R_O_R_F_L_A_G_S__
u
DATA RECEIVED RESET
"NOTE:
DATA OUT AND OVER·
RUN ERROR PRECEDES
DR & ERROR FLAGS BY
1/2 CLOCK
Figure 9. Receiver Timing Diagram
341
-J)(~_____________
DETECT START INTERVAL
RECEIVER CLOCK (1IiX)
TRUE CENTER OF START
RECEIVER INPUT
SAMPLE POINT
Figure 10.
Since a clock with these characteristics is very easy
to obtain, it is apparent that a receiver operating
margin of slightly over 45% is very easy to achieve
when using the TR1602. Furthermore, this margin is
sufficient for virtually all existing transmitters and
modems presently in use.
The TR1602 also begins searching for the next start
bit exactly in the center of the first stop bit so that
minimum character distortions of up to 50% can be
accepted.
A break character (null character without a stop bit)
will lock the receiver up since it will not begin looking
for the next start bit until a stop bit has been
received.
it also greatly reduces the micro-computer load, thus
freeing it for other functions.
Since the TR1602 inputs and outputs are TTL compatible, the TR1602 interfaces directly with virtually
all micro-computer I/O busses. In Figure 12, the
micro-computer Data Output Bus is connected to the
Transmitter Register (TR) inputs and the Control
Register inputs. When the micro-computer has a
character to transmit, the character is placed on the
Data Output bus and the address of the appropriate
TR1602 is placed on the Device Address Bus. The
Address Decode circuit will output a THRL load
pulse under control of the Data Out Strobe from the
micro-computer: When the control register should be
changed, a new 5 bit control word is placed on the
Data Output Bus and along with an appropriate
device address which is converted to a CRL load
pulse in the Address Decode circuits, again under
control of the Data Out Strobe. A THRE Pulse to the
Interrupt Request circuit will notify the microcomputer when a new character may be provided to
the TR1602 for transmission.
When a character has been received, a DR signal to
the Interrupt Request circuit will request an interrupt
from the micro-computer: The micro-computer will
respond by setting the proper device address and
provide a Data in Strobe pulse. The Address-Decode
circuit then sets the RRD line and SFD line to the
appropriate receiver to enable the Data Outputs onto
the mini Data Input Bus. The Data in Strobe from the
micro-computer then resets the DR signal with a
ORR pulse from the Address Decode circuit.
The TR1602 Transmitter Output (TRO) and Receiver
Input (RI) must generally be converted to RS232
levels if they interface with a modem as shown in
Figure 12. RS232 is a standard that has been
established by the Electronic Industries Association
for the interface between data terminals and data
communications equipment. RS232-C defines a
space as greater than 3 volts and a mark as less than
negative 3 volts at the Receiver input. A transmitter
output of between 5 and 15 volts is a space while a
TYPICAL TR1602 APPLICATION
The TR1602 is ideally suited for use in distributed
computer networks such as is illustrated in Figure
11. One of the primary purposes of the communications controller is to assemble and disassemble the
asynchronous characters (required for communication with the data terminals) to/from the parallel data
format required by the host computer: Often the communications controller is a micro-computer and character assembly/disassembly is performed by the
software. When this is the case, the micro-computer
must be interrupted at a rate equal to 8 to 16 times
the baud rate of all terminals being handled by the
controller: (The actual interrupt rate depends on the
amount of distortion that can be experienced on the
received characters). When the number of terminals
exceeds 8 to 16, even the most powerful micro-computers become overloaded due to the high interrupt
rate and the complex algorithms required by the
software.
The TR1602 greatly reduces this problem by performing the character assembly/disassembly functions in external hardware as shown in a typical
configuration in Figure 12. This solution not only
reduces the interrupt rate by a factor of up to 176, but
342
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CD
UI
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•
•
•
•
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HOST
COMM
COMP
CON·
TROL
Figure 11.
level between - 5 and -15 is a mark. The input/output impedances and signal rise and fall times are
also specified by RS232. Fairly simple discrete level
translators can be used to convert from the TTL
levels to the RS232 levels, or monolithic IC's are also
available.
It should be noted that the typical application
illustrated in Figure 12 is only one of many and it
does not take advantage of many of the TR1602
features. For example, the Status Flags could be tied
to a separate interrupt request bus or the TRE output
could be used to implement half-duplex operation.
See page 725 for ordering information.
343
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MICRO-PROCESSOR
COMPUTER
TR1602
COMMUNICATION
CONTROLLER
ASYNC
MODEM
1----......~S~-;21
TO TTL
CONV
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RI
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Figure 12. Typical Minicomputer Interface
3:
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TR1602fTR18631TR1865 Application Notes
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REQUEST
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WESTERN DIGITAL
COR
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RAT
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N
WD1983 (BOARn
Bus Oriented Asynchronous Receiver/Transmitter
F:EATURES
BAUD RATE-DC TO 36K BITS/SEC (16X)
SELECTABLE CLOCK RATES
ASYNCHRONOUS MODE
II
I'
II
II
II
II
II
..
..
I'
I'
II
• 1X, 16X, 64X, BAUD RATE CLOCK INPUTS
• UP TO 47% DISTORTION ALLOWANCE
WITH 64X CLOCK
FULL DUPLEX OPERATION
SELECTABLE 5,6,7, & 8 BIT CHARACTERS
LINE BREAK DETECTION AND GENERATION
1, 1'12, or 2 STOP BIT SELECTION
FALSE START BIT DETECTION
OVERRUN AND FRAMING ERROR DETECTION
DC TO 36K BITS/SEC (16X)
DC TO 600K BITS/SEC (1X)
8251/8251 A ASYNCHRONOUS ONLY REPLACEMENT
REQUIRES NO ASYNCHRONOUS SYSTEM CLOCK
28 PIN PLASTIC OR CERAMIC
+5 VOLT ONLY
APPLICATIONS
ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL INTERFACE
GENERAL DESCRIPTION
SYSTEM COMPATIBILITY
n DOUBLE BUFFERING OF DATA
II 8 BIT BI-DIRECTIONAL BUS FOR DATA, STATUS, AND
CONTROL WORDS
.. ALL INPUTS AND OUTPUTS TTL COMPATIBLE
.. CHIP SELECT, RE, WE, C/O INTERFACE TO CPU
.. ON-LINE DIAGNOSTIC CAPABILITY
o THREE STATE DATA BUS
27
D3
RXD-
D4 -
26
Vcc(+5V)
25
5
24
AXe
t5'i'R
D5
23
RTS
Ds
22
~
21
MR
WD1983
D7
TXD
AXD
i'XC
WE-
The WD1983 is a fully programmable microprocessor I/O peripheral with two control registers and a status register. It is
capable of full duplex operations.
Do
3
(GND)Vss
The WD1983 is an N channel silicon gate MOS/LSI device
that interfaces a digital asynchronous channel with a parallel
channel. It is available in a ceramic or plastic standard 28 pin
dual in line package.
10
~
11
e/o
12
~
13
RXRDY
14
15
TXRDY
FIGURE 1 WD1983 PIN-OUT
FIGURE 2 WD1983 BLOCK DIAGRAM
345
PIN
NUMBER
1,2,5,
6,7,8,
27,28
PIN NAME
FUNCTION
SYMBOL
DATA BUS
DOTHRU 07
These are input/output pins. Data on the DATA BUS is
written into the selected register during a WRITE
operation. During a READ operation, the DATA BUS is
driven by data in the selected register. When not
selected, (CS high), these pins are in a high impedance state.
RXD
This input is the received serial data.
3
RECEIVE DATA
4
POWER GND
VSS
Ground
9
TRANSMIT CLOCK
TXC
This input is the source clock for transmission.
MODE INSTRUCTION word bits MRO & MR1, control
1X, 16X, or64X, times the transmitted bit rate.
10
WRITE ENABLE
This input, when low, writes the data on the DATA
BUS into the addressed register.
11
CHIP SELECT
This input, when low, enables READ or WRITE
operations.
12
CONTROL/DATA
13
READ ENABLE
14
RECEIVER READY
RXRDY
This output is set low after MASTER RESET. When
set high it indicates that the receiver has assembled
a character and transferred it to the RECEIVER
HOLDING REGISTER. It is automatically reset when
the RECEIVER HOLDING REGISTER is read.
15
TRANSMIT READY
TXRDY
This output is set high after MASTER RESET. It indicates that the transmitter is ready to accept a
character and is automatically reset whenever a
character is written into the TRANSMITTER
HOLDING REGISTER.
16
BREAK DETECT
BRKDET
This output is reset after MASTER RESET. It is set
high when the receiver detects a string of zeros equal
to the programmed character length including start,
parity and stop bits. Upon detecting a valid one data
bit it's reset. Assembly of the next character is begun
after detecting a valid start bit.
C/O
This input selects the CONTROL or DATA register. It
is used in conjunction with a READ or WRITE enable.
This input, when low, accesses the contents of the
addressed register.
346
PIN
NUMBER
PIN NAME
SYMBOL
FUNCTION
17
CL!=AR TO SEND
18
TRANSMIT EMPTY
TXE
This output is set high after MASTER RESET and is
automatically reset when a character is written into
the TRANSMITTER HOLDING REGISTER. It returns
high at the end of a transmitted character indicating
the end of transmission If the TRANSMIT HOLDING
REGISTER has not been loaded.
19
TRANSMIT DATA
TXD
This output is the transmit serial data. When no data
is being transmitted or after MASTER RESET, this
output is high (a marking condition). COMMAND
CONTROL word bit 3 is used to program a break
condition by forcing the TXD output to a low (spacing
condition).
NC
No internal connection, pin not used.
21
MASTER RESET
MR
This input, when high, initializes the device and
clears the COMMAND and MODE REGISTERS.
22
DATA SET READY
This is a general purpose input which is sensed in
STATUS REGISTER bit #7.
23
REQUEST TO SEND
This is a general. purpose output which is set and
cleared by COMMAND word bit CR5. It is reset after
MASTER RESET.
.
24
DATA TERMINAL READY
25
RECEIVE CLOCK
26
POWER SUPPLY
20
This input is set low to enable the transmitter. When
set high it disables transmission. If the transmitter is
transmitting a character, it will terminate transmission after the TRANSMITTER REGISTER is
empty.
DTR
This is a general purpose output which is set and
cleared by COMMAND word bit CR1. It is reset after
MASTER RESET.
This input is the receiver clock. MODE INSTRUCTION word bits MRO & MR1 control whether
this input is 1X, 16X or64X times the received bit rate.
+ 5 Volts
VCC
347
ORGANIZATION
OPERATING DESCRIPTION
The WD1983 Block Diagram is illustrated on Page 1. The
WD1983 (BOART) is an eight bit bus-oriented device. Communication between the BOART and the controlling CPU occurs via the 8 bit DATA BUS. There are 2 accessible DATA
REGISTERS, which buffer Transmit and Receive DATA. They
are the TRANSMIT HOLDING REGISTER and the RECEIVE
HOLDING REGISTER. There is a parallel-to-serial shift register (the TRANSMIT REGISTER) and a serial-to-parallel shift
register (the RECEIVE REGISTER).
The WD1983 (BOART) is primarily designed to operate in an
8 bit microprocessor environment, although other control logic
schemes are easily implemented. The DATA BUS and the Interface Control Signals (CS, C/O, RE and WE) should be connected to the microprocessor's data bus and system control
bus. The appropriate ill and RXC clock frequencies should
be selected for the particular application using a programmable baud rate generator such as the BR1941.
Operational control and monitoring of the BOART is performed by two CONTROL REGISTERS (the COMMAND INSTRUCTION REGISTER and the MODE INSTRUCTION
REGISTER) and the STATUS REGISTER.
For typical data communication applications, the RXD and
TXD input/outputs can be connected to RS-232C interface circuits or a modem.
A READ/WRITE control circuit allows monitoring/programming or reading/loading in the CONTROL, STATUS or HOLDING REGISTE:RS by activating the appropriate control lines:
Chip Select (CS), Read Enable (RE), Write Enable (WE) and
Control or Data Select (C/O).
Internal control of the BOART is by means of two internal MICROCONTROLLERS; one for transmit and one for receive.
The CONTROL REGISTERS, MODEM CONTROL LOGIC,
READ/WRITE CONTROL LOGIC and various counters provide inputs to the MICROCONTROLLERS, which generate the
necessary control signals to send and receive serial data accord ing to the programmed asynchronous format.
READ/WRITE OPERATIONS
The WD1983 must be initialized after a MASTER RESET
pulse by first writing the MODE INSTRUCTION word and then
the COMMAND INSTRUCTION word. Thereafter, every control write to the device is interpreted as a COMMAND word. If
it is desired to re-program the MODE REGISTER, a COMMAND REGISTER bit, INTERNAL RESET (CR6), allows the
next control write data to be entered into the MODE
REGISTER.
The WD1983 registers are accessed according to the following table:
The TXRDY, RXRDY, TXE and BRKDET Flags may be connected to the microprocessor system as interrupt inputs or the
STATUS REGISTER can be periodically read in a polled environment to support BOART operations.
MODEM CONTROL SIGNALS can be configured several
ways as the DTR, RTS and DSR signals are controlled and
sensed by the CPU through the COMMAND and STATUS
REGISTERS. The CTS input is used to synchronize the transmitter to external events.
The SBRK bit of the COMMAND REGISTER (CR3) is used to
send a Break Character. (A break character is defined as a
start bit, and all zero data, parity and stop bits). When the CR3
bit is set to a "1 ", it causes the transmitter output, TXD, to be
forced low after the last word is transmitted.
The receiver is equipped with logic to look for a break character. When a break character is received, the BREAK DETECT (BRKDET) FLAG and STATUS bit are set to logic "1".
When the receiver input I ine goes high again for the least "one
data bit time," the receiver resets the BREAK DETECT FLAG
and resumes its search for a start bit.
C/o= H
C/o= L
(
-
MODE INSTRUCTION WORD
COMMAND INSTRUCTION WORD
DATA
CHARACTER(S)
COMMAND INSTRUCTION WORD
CS C/O RE WE REGISTERS SELECTED
C/D= L
L
L
L
L
H
L
L
H
H
X
Note:
L
H
L
H
X
H
L
H
L
X
Read RECEIVE HOLDING REGISTER
Write TRANSMIT HOLDING REGISTER
Read STATUS REGISTER
Write CONTROL REGISTER
OAT A BUS tri-stated
C/D= H
-
DATA
CHARACTER(S)
COMMAND INSTRUCTION WORD
TYPICAL DATA BLOCK TRANSFER
"L" means V I L at pins
"H" means V IH at pins
"X" means don't care
348
MODE INSTRUCTION CONTROL WORD FORMAT
MR7
MR6
I
'\.
/
No. of STOP bits:
00 = invalid
01 = 1 bit
10 = lV. bits
11 = 2 bits
I
MR5
I
EVEN
PARITY
GENERATION/
check:
1 = even
0= odd
MR4
MR3
I
I
\
PARITY
ENABLE:
1 = enable
o = disable
MR2
= 5
=.6
= 7
= 8
~
CO
CO
I
BAUD RATE
FACTOR:
00 = invalid
bits
bits
bits
bits
01 = Xl
10 = X16
11 = X64
COMMAND INSTRUCTION CONTROL WORD FORMAT
CR7
CR6
CR5
CR4
CR3
CR2
DON'T
INTERNAL
RESET
(IR)
REQUEST
TO SEND
(RrS):
ERROR
RESET
(ER):
SEND
BREAK
CHARACTER
(SBRK):
RECEIVE
ENABLE
(RXE):
CARE
FiTs
1 = forces
1 = returns
output low
WD1983 to
mode instruction
word format
o = forces
i"ii'S output
high
1 = resets PE,
OE & FE error 1 = forces TXD
output low
flags
o = normal
operation
0= normal
operation
CRO
CR1
DATA
TERMINAL
READY
TRANSMIT
ENABLE
TXEN:
(DTRj:
1 = enable
receiver
o = disable
receiver
'DTR
1 = forces
output low
o = forces
ll'm output
1 = enable
transmitter
o = disable
transmitter
STATUS WORD FORMAT
SR7
SR6
SR5
SR4
SR3
SR2
SR1
DsR
BRKDET
(SEE NOTE)
FRAMING
ERROR
(FE):
OVERRUN
ERROR
(OE):
PARITY
ERROR
(PE):
TXE
(SEE NOTE)
RXRDY
(SEE NOTE)
1 = parity error
detected
(SEE NOTE)
1 = invalid
1 = CPU
stop bit detected
did not read
at the end
the character
before the
of the character
o=
next one
o = No
framing error
detected
(Reset by CR4)
SRO
TXRDY
(SEE NOTE)
No
Parity error
became
detected
available
(Reset by CR4)
o = No
overrun error
detected
(Reset by CR4)
FIE, OE & PE FLAGS DO NOT INHIBIT OPERATION.
THESE FLAGS ARE STATUS ONLY.
NOTE:
SRO, SR1, SR2, SR6, and SR7
HAVE IDENTICAL MEANINGS AS THE
EXTERNAL OUTPUT PINS.
349
-
(.r.)
,\
CHARACTER
LENGTH:
00
01
10
11
:eC
MRO
MR1
to
~
:::D
d
ABSOLUTE MAXIMUM RATINGS
VDD with Respect to VSS (Ground)
Max. Voltage to any
Input with Respect to VSS
+
15 to -0.3V
+
20 to -0.3V
Power Dissipation
Storage Temp.
Ceramic -65°C to + 150°C
Plastic -55°C to + 125°C
('E' Package)
('F' Package)
1000 MW
OPERATING CHARACTERISTICS
TA = O°C to 70°C, Vee =
SYMBOL
+ 5.0V ±
.25V, VSS = OV
CHARACTERISTIC
MIN
TYP
MAX
UNITS
CONDITIONS
III
Input Leakage
10
IlA
VIN = Vee
IDL
Data Bus Leakage
SO
IlA
Data Bus is
in high impedence
state
80
mA
S.25 VDC/f elK =
600 kHz No Loads.
0.8
V
ICC
VCC Supply Current
VIH
Input High Voltage
VIL
Input Low Voltage (All Inputs)
VOH
Output High Voltage
VOL
Output Low Voltage
AVE
45
2.4
-0.3
V
2.4
V
10 = - 100llA
(source)
V
10 = 1.6 mA
(sink)
0.45
TABLE 1 WD1983 DC CHARACTERISTICS
VOH _ _ _ _ _ _ _- . ,
~ 2.0
TeST POINTS
2.0)(
VOL _ _ _ _ _ _ ~~0._8_ _ _ _ _ _ _ _ _ _ _ _ _ _ _0_.8_J
,-._ _ _ _ _ __
FIGURE 3 INPUT WAVEFORMS FOR AC TESTS
NOTE: ALL WAVEFORMS ARE MEASURED AT 2.0V IF RISING EDGE, AND 0.8V IF FALLING EDGE.
350
VOH
DATA BUS
VOL
C/O
CS
VIH
-"t=
...A.
CO
Q)
(a)
-
OJ
~
VIL
RE
:eC
VIH
::tI
..::I
VIL
FIGURE 4 READ TIMING
DATA BUS
VIH
VIL
~
ToS
VIH
CS
C/O
VIL
VIH
WE
VIL
FIGURE 5 WRITE TIMING
NOTE:
8251A COMPATIBILITY
The WD1983 (BOART) is an asynchronous only device, which Is compatible with the
8251A. However, in test evaluation and application, the following differences should be noted:
(1) The WD1983 utilizes the transmit and receive baud clocks in their respective internal logic sections instead of the system clock normally applied
to Pin 20 on the 8251A. This Pin on the WD1983 is not used.
(2) As a result of the above condition, timings referenced to the system clock
period in the 8251A specification are now specified in absolute time units
or with respect to the transmit or receive baud clock.
351
AC Electrical Characteristics
TA
= O°C to +
70°C; Vee
SYMBOL
=
5.0 V ± 5%; GND
=
0 V
PARAMETER
MIN
MAX
UNIT
TEST
CONDITIONS
BUS PARAMETERS
READ CYCLE
tAR
Address Stable Before RE (CS,C/O)
50
ns
tRA
Address Hold Time for RE (~,c/o)
5
ns
tRE
RE Pulse Width
350
ns
tRO
Data Delay from RE
tROH
RE to Data Floating
25
tAW
Address Stable Before WE
20
ns
tWA
Address Hold Time for WE
20
ns
tWE
WE Pu Ise Width
350
ns
tos
Data Set-Up Time for WE
200
ns
tWOH
Data Hold Time for WE
40
ns
= 50pF
200
ns
CL
200
ns
CL (Max)
CL (Min)
= 50pF
= 15pF
WRITE CYCLE
OTHER TIMINGS
ns
CL
= 100pF
200
ns
CL
= 100pF
RX Data Hold Time to Sampling Pulse
100
ns
CL
=
Transmitter Input Clock Frequency
1X Baud Rate
16X and 64X Baud Rate
DC
DC
Transmitter Input Clock Pulse Width
1X Baud Rate
16X and 64X Baud Rate
1.0
500
tOTX
TXD Delay from Falling Edge of TXC
tSRX
RX Data Set-Up Time to Sampling Pulse
tHRX
fTX
1
tTPW
TABLE 2
200
500
600
kHz
kHz
fLs
ns
WD1983 AC CHARACTERISTICS (CONTINUED)
352
100pF
SYMBOL
tTPD
fRX
tRPW
tRPD
PARAMETER
MIN
Transmitter Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate
1.0
800
Receiver Input Clock Frequency
1X Baud Rate
16X and 64X Baud Rate
DC
DC
Receiver Input Clock Pulse Width
1X Baud Rate
16X and 64X Baud Rate
1.0
500
I.LS
Receiver Input Clock Pulse Delay
1X Baud Rate
16X and 64X Baud Rate
1.0
800
I.LS
MAX
UNIT
I.LS
ns
500
600
kHz
~kHz
ns
ns
tTX
TXRDY Delay from Center of Data Bit
8
tRXC
tRX
RXRDY Delay from Center of Data Bit
1/2
tRXC
tiS
Internal BRKDET Delay from Center of
Data Bit
1
tRXC
tTRD
TXRDY Delay from Falling Edge of WE
1
tTXC
tTOD
TXD Output from Falling Edge of WE
2
tTXC
twc
C..Q!l!.roL.Q.2lay from Rising Edge of WE
(DTR, RTS)
400
ns
tCR
Control to RE Set-Up Time (DSR, CTS)
500
ns
TABLE 2 WD1983 AC CHARACTERISTICS
At f TX (max), the duty cycle should be 50%. At less than f TX
(max), the minimum pulse width for the high or low half is
1
2- f TX (max)
Hence, at frequencies less than f TX (max), the required duty
cycle will be less stringout than 50%.
353
TEST
CONDITION
CL = 50pF (16X)
~lJ
U
wilJ
U
~
~trRD
f---
~
tTRD
tTOD
I
----~IL._________________S_~_RT_B_IT______. ________________________________~D~A
TXD
FIGURE 6
TRANSMITTER OUTPUT TIMINGS WITH RESPECT TO TRANSMIT CLOCK
354
READ
AND
WRITE
TIMING
CA)-
es _____
(READ
AND
WRITE
TIMINGS
ARE NOT
RELATED
TO ANY
CLOCKS)
,r -- -- --- - ----Xy.:7\...._____________________
_ -- - - -1L-
\
~
'----~-k_
twc
--..I
¥".C:::::::::::::::::::::::::::::::::::::
TXE.i5TR.RTs _ _ _ _ _ _ _ _._ _ _ _ _ _ _ _
L '" =i""-----J,.-----TRANSMITTER
CLOCK
AND
DATA
TIMING
TX<--
r--
I
DISTR/DISTR
O·R
~
~tDS+tDH__l
---------------«
VALIDDATA
)--
FIGURE 6. WRITE CYCLE TIMING
•
369
ACTIVE
XTAL1
BAUD OUT
H-2)
---I
--I I- t BLD --I I-- t BHD
tLW
BAUD OUT
(-+ 3)
~
BAUDOUT
(+N.N>3)
I-- t BLD --I f-- t BHD
~
_n
•
r--sS
~
-I
I.
t HW
= (n -2) XTAL1 CYCLES
.~I-----'I~
~----....-'""I t LW
= 2 XTAL 1 CYCLES
FIGURE 7. BAUDOUT TIMING
RCLK
~~S
I-
SAMPLECLK
LJ
8CLK~ -------I-.-j
---II-- tSCD
------Ir
u
JI--rl--r--~I-r--..,.-1USAMPLECLK
--l
INTERRUPT
DISTR/DISTR'
(READ REC DATA
BUFFER)
Notes:
'See Write Cycle Timing
'See Read Cycle Timing
FIGURE 8. RECEIVER TIMING
370
Ti~0~~ OUT _ _ _ _ _~
PARITY
~TARi
D
INTERRUPT (THRE)
DATA (5-8)
~TA_Ri,--_ _ _ _ _ __
\
~\.....--~~~-----,A ~'H'
DOSTR/DOSTR'
(WR THR)
DISTR/DISTR'
(RD fiR)
1 ,~,~-~\..
I
----------------~
Noles:
'See Write Cycle Timing
'See Read Cycle Timing
FIGURE 9. TRANSMITTER TIMING
DOSTR/DOSTR'
(WR MCR)
/1
INTR
_~/.
-i 1-tSIM
f5TSil'l/DISTR'
(RD MSR)
________
\'"""------
\1/\
~ I.: -l
J~RIM
tSIM
-I
---------\
Noles:
'See Write Cycle Timing
'See Read Cycle Timing
FIGURE 10. MODEM CONTROLS TIMING
•
371
/
~r--tSIM~
~~R_IM I_______
f-
__
},..---
ORDERING INFORMATION
Part Number
Max Clock
Rate 1
Bits/Character
WD8250*·00
WD8250*·20
WD8250*·30
3.1 MHz
3.1 MHz
500 kHz
5,6,7,8
6,7,8
5,6,7,8
NOTES:
1. This is the maximum clock rate that can be ap·
plied to pins16 or 17.
* Consult your local Western Digital Sales Repre·
sentative for information regarding package
availability, price, and delivery.
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
372
Printed In U S.A
WESTERN DIGITAL
c
o
R
o
p
R
A
T
/
o
N
WD2123 DEUCE
Dual Enhanced Universal Communications Element
• COMPATIBLE WITH 8251 A (ASYNC ONLy) AND WD1983
DEVICES
• DIAGNOSTIC LOCAL LOOP-BACK MODE
• RXD INITIALIZATION UPON MASTER RESET
• ON-BOARD OSCILLATOR FOR EASE OF USE WITH A
CRYSTAL
• VERSATILE CLOCK SELECT OPTIONS FOR INDEPENDENT TRANSMIT AND RECEIVE RATES
IFEATURES
• TWO INDEPENDENT ASYNCHRONOUS FULL DUPLEX
DATA COMMUNICATION CHANNELS (2 BOARTS)
• TWO INDEPENDENT BAUD RATE GENERATORS (ONE
PER CHANNEL)
• EACH CHANNEL WITH FOLLOWING FEATURES:
• SELECTABLE 5 TO 8 BIT CHARACTERS
1X, 16X, 64X CLOCK RATES
• 16 SELECTABLE BAUD RATE CLOCK FREQUENCIES
(INTERNAL)
• LINE BREAK DETECTION AND GENERATION
• 1, 1V2, OR 2 STOP BIT SELECTION
• FALSE START BIT DETECTION
• ODD OR EVEN PARITY GENERATE AND DETECTION
• OVERRUN AND FRAMING DETECTION
• DOUBLE BUFFERING OF DATA
• TTL COMPATIBLE INPUTS AND OUTPUTS
I.
INTRODUCTION
The Western Digital WD2123 Dual Enhanced Universal
Communications Element (DEUCE) is a single chip MOS/LSI
Data Communications Controller Circuit that contains two
independent full-duplex asynchronous RECEIVER/TRANSMITTER CHANNELS and two independent BAUD RATE
GENERATORS. The WD2123 is fabricated in N-Channel silicon gate technology and is packaged in a 40 pin plastic or
ceramic package. All inputs and outputs are TTL compatible.
WE
CS2
FiE
c/i5
MR
CSi
NC
40
TXO-B
39
RXROY-B
RXO-B
TXE-B
BRKOET-B
~
38
37
~
36
cm'
35
DO
34
SELCLK-B
01
33
XCIfBCO-B
02
32
XTAL2
RTS-A
RTS-B
CTS-A
Ci"S-B
WD2123
TXRDY-A
VSS
10
31
XTAL1
03
11
30
VCC
04
12
29
MR
05
13
28
XCIIBCO-A
06
14
27
SELCLK-A
07
15
16
26
crs:A
CS2
25
rm:A
~
17
24
BRKOET-A
CS3
18
TXE-A
RXO-A
19
23
22
TXO-A
20
21
TXROY-A
CHANNEL
RXRDY-A
TXD-B
RXD-B
CHANNEL
___
TXRDY-B
RXRDY-B
B
TXE-B
TXE-A
BRKDET-B
BRKDET-A
SELCLK-A
BAUD RATE
BAUD RATE
GENERATOR
GENERATOR
SELCLK-B
XCI/BCO-B
XCI/BCO-A
RXROY-A
GND
+5V
Figure 1. WD2123
___
TXD-A
RXD-A
Figure 2. WD2123
PINOUT DIAGRAM
373
BLOCK DIAGRAM
PIN
NUMBER
PIN NAME
SYMBOL
FUNCTION
10
GROUND
VSS
Ground
30
POWER SUPPLY
VCC
+5VDC power supply input.
7
8
9
11
12
13
14
15
DATA BUS
DO
01
02
03
04
05
06
07
This is the 8 bit Bidirectional Data Bus. It is the means of
communication between the WD2123 and the CPU. Data,
control, mode and status registers are accessed via this bus.
5
CHIP SELECT ONE
CS1
V IL on this input selects Channel A and enables computer
communications with Channel A Data, control and status
registers.
16
CHIP SELECT TWO
CS2
V I L on this input selects Channel B and enables computer
communications with Channel B Data, control and status
registers.
18
CHIP SELECT THREE
CS3
VIL on this input select the Baud Rate registers for programming.
6
CONTROL or DATA
SELECT
c/D
This input is used in conjunction with the appropriate Chip
Select and an active read or write operation to determine
register access via the Data Bus.
4
READ ENABLE
RE
V I L on this input allows the CPU to read data, or status information from the selected register.
17
WRITE ENABLE
WE
VIL on this input allows the CPU to write data or control information into the selected register.
29
MASTER RESET
MR
V I H on this input resets both channels to the idle state and
resets the status, command, mode and Data registers.
31
CRYSTAL OSCILLATOR
INPUT
XTAL1
This is the input side of the on-chip oscillator. It can also be
driven by an external clock source.
32
CRYSTAL OSCILLATOR
OUTPUT
XTAL2
This is the output side of the on-chip oscillator.
27
SELECT CLOCK
(Channel A)
SELCLK-A
This input is used in conjunction with the Clock Select bit
(CR1) in the command register to determine the baud clock
source for Channel A.
34
SELECT CLOCK
(Channel B)
SELCLK-B
This input is used in conjunction with the Clock Select bit
(CR1) in the command register to determine the baud clock
source for Channel B.
28
EXTERNAL CLOCK
INPUT/BAUD
CLOCK OUTPUT(Channel A)
XCI/BCO-A
This is a bidirectional port, which is used as the externally
applied baud clock input or the internal baud rate generator
output depending on the states of SELCLK and CR1 command bit. (Channel A)
33
EXTERNAL CLOCK
INPUT/BAUD CLOCK
OUTPUT-(Channel B)
XCI/BCO-B
This is a bidirectional port, which is used as the externally
applied baud clock input or the internal baud rate generator
output depending on the states of SELCLK and CR1 command bit. (Channel B)
26
CLEAR-TO-SEND
(Channel A)
CTS-A
V I L on this input enables Channel A to transmit serial data if
the Transmitter is enabled.
374
PIN
NUMBER
PIN NAME
FUNCTION
SYMBOL
CLEAR-TO-SEND
(Channel B)
CTS-B
20
TRANSMIT DATA
(Channel A)
TXD-A
This is the Serial Data Output from Channel A.
2
TRANSMIT DATA
(Channel B)
TXD-B
This is the Serial Data Output from Channel B.
19
RECEIVE DATA
(Channel A)
RXD-A
This is the Serial Data Input for Channel A.
3
RECEIVE DATA
(Channel B)
RXD-B
This is the Serial Data Input for Channel B.
21
TRANSMITTER READY
(Channel A)
TXRDY-A
This output, when high (V OH),alerts the CPU that Channel A
is ready to accept a new data character. The TXRDY output
is automatically reset whenever a character is written into
the Transmit Holding Register and can be used as an interrupt to the system.
40
TRANSMITTER READY
(Channel B)
TXRDY-B
This output, when high (VOH),alerts the CPU that Channel B
is ready to accept a new data character. The TXRDY output
is automatically reset whenever a character is written into
the Transmit Holding Register and can be used as an interrupt to the system.
22
RECEIVER READY
(Channel A)
RXRDY-A
This output, when high (V OH), alerts the CPU that Channel B
contains a data character that is ready to be input. This output is automatically reset whenever the new character is
read from the Receive Holding Register and can be used as
an interrupt to the system.
39
RECEIVER READY
(Channel B)
RXRDY-B
This output, when high (V OH), alerts the CPU that Channel B
contains a data character that is ready to be input. This output is automatically reset whenever the new character is
read from the Receive Holding Register and can be used as
an interrupt to the system.
23
TRANSMITTER EMPTY
(Channel A)
TXE-A
This output, when high (V OH), indicates that Channel A
Transmitter has no new characters to send and is waiting in
an idle state.
38
TRANSMITTER EMPTY
(Channel B)
TXE-B
This output, when high (V OH), indicates that Channel B
Transmitter has no new characters to send and is waiting in
an idle state.
24
BREAK DETECT
(Channel A)
BRKDET-A
This output, when high (V OH), indicates that the Receiver for
Channel A has detected a break condition.
37
BREAK DETECT
(Channel B)
BRKDET-B
This output, when high (VOH),indicates that the Receiver for
Channel B has detected a break condition.
25
REQUEST-TO-SEND
(Channel A)
RTS-A
A general purpose output that is controlled by the command
register bit CR5 for Channel A.
36
REQUEST -TO-SEND
(Channel B)
RTS-B
A general purpose output that is controlled by the command
register bit CR5 for Channel B.
NC
No Internal Connection.
35
1
=E
N
.....
c
VIL on this input enables Channel B to transmit serial data if
the Transmitter is enabled.
Table 1 WD2123 PIN DESCRIPTIONS
375
N
W
GENERAL DESCRIPTION
The WD2123 also provides a local loop-back test mode of
operation for each channel. This diagnostic mode is independently controlled via the LB(CR?) bit of the COMMAND
REGISTER. When LB is logic 1, the channel is programmed
for Local Loop-Back. In this diagnostic mode, the TXD output
is set to the marking (logiC "1 ") state; the output of the
TRANSMIT REGISTER is "looped-back" into the RECEIVER REGISTER input; RTS output is held high; the CTS
and RXD inputs are ignored. An additional requirement is
that the TEN(CRO) command bit and the REN(CR2) be logic
1. The status and output flags operate normally.
The WD2123 Block Diagram is shown in Figure 2. The
WD2123 is a merger of two WD1983s and one WD1941 from
WDC's line of communications devices on one piece of silicon. The 1983 is an asynchronous only version of the 8251A
and the 1941 is a baud rate generator. In this manner, 8251A
compatibility is maintained with the WD2123 with the added
features of 2 channels and 2 baud rate generators on a single
chip.
As depicted from the block diagram, the channels are referred to as CHANNELS A and B. CHANNEL A, which is an
asynchronous 8251 A, is addressed or controlled by the input
signal ~. CHANNEL B is Similarly controlled by~. Finally, the BAUD RATE GENERATORS are controlled by
CS3.
Each channel is also provided with break character generation and detection. (A break character is defined as all zero
data bits, parity bit and stop bits after a valid start bit.) For
break character generation, SBRK (CR3) command bit is set
to a logic 1. This causes the TXD output to be forced low
(spaCing) for as long as SBRK is programmed high. The
break detect output and status bit (SR6) is set to logic 1, indicating that the receiver has detected a break character.
The framing error flag is also set to 1 for this condition.
Each channel of the WD2123 can be programmed to receive
and transmit asynchronous serial data. The WD2123 performs s.erial-to-parallel conversion on data characters received from an input/output device or a MODEM, and parallel-to-serial conversion on data characters received from the
CPU. The CPU can read the status of either channel at any
time. Status information on a per channel basis reported includes the type and the condition of the transfer operations
being performed by the WD2123 as well as any transmission
error conditions (parity, overrun, or framing). Programming
the WD2123 is identical to the 8251A in the asynchronous
mode, remembering that CS1, when low, selects CHANNEL
A and when CS2 is low, selects CHANNEL B.
ORGANIZATION
The WD2123 is an eight bit bus-oriented device. Communication between the controlling CPU and the two RECEIVER/
TRANSMITTER CHANNELS or the two BAUD RATE GENERATORS occurs via the 8 bit data bus through a common
set of bus transceivers.
A diagram of one of the two communication controllers is
shown in Figure 3. There are two accessible data registers,
which buffers transmit and receive data. They are the
TRANSMIT HOLDING REGISTER and the RECEIVE
HOLDING REGISTER. There is a parallel-to-serial shift register, the TRANSMIT REGISTER and a serial-to-parallel
shift register, the RECEIVE REGISTER.
The WD2123 BAUD RATE GENERATORS may be selected
either internally or externally. The clock select logic includes
a clock select control bit CR1 (CS) in each COMMAND INSTRUCTION REGISTER. This control bit allows selection of
the internal baud clock or an externally applied clock and
works in conjunction with the select clock pin, "SELCLK" and
the external clock input/baud clock output pin, "XCI/BCO".
When CS is logic 1, the external clock select mode is selected. This means that the transmit and receive clocks (TXC
and RXC) are internally tied together and the select clock
pin, SELCLK, will determine whether those clocks are driven
from the internal baud rate generator (SELCLK is high) or
from the external clock input pin, "XCI/BCO", (SELCLK is
low).
Operational Control and monitoring of the CHANNEL is performed by two CONTROL REGISTERS (the COMMAND INSTRUCTION REGISTER and the MODE INSTRUCTION
REGISTER) and the STATUS REGISTER.
A read/write control circuit allows programming/monitoring
or loading/reading of data in the CONTROL, STATUS and
HOLDING REGISTERS by activating the appropriate control
lines: Chip Select (CS1, CS2, CS3), READ ENABLE (RE),
WRITE ENABLE (WE) and CONTROL or DATA SELECT
(C/O).
If the internal BRG clock is selected, (SELCLK is high) then
the external clock input pin becomes a BRG clock output.
Hence, the mnemonic, "XCI/BCO".
Internal control of each channel is by means of two internal
microcontrollers: one for transmit and one for receive. The
control registers, various counters and external signals provide inputs to the microcontrollers, which generate the necessary control signals to send and receive serial data according to the programmed protocol.
When CR1 (CS) is logic 0, then internal clock select mode is
selected. The transmit clock (TXC) is driven by the internal
BRG clock and the receive clock is driven by the select clock
pin, (SELCLK). The XCI/BCO pin becomes the baud clock
output (the same signal that is being applied to TXC).
376
A diagram of one of the two BAUD RATE GENERATORS is
shown in Figure 4. The 4 low order DATA BUS bits, 00-03,
are used to program the desired rate by loading the RATE
REGISTER. Control signals~, WE and C/O are used to
select and load the appropriate register.
The contents of the RATE REGISTER is decoded and addresses a FREQUENCY SELECT ROM for the proper frequency, which is generated by the DIVIDER circuitry and the
control logic.
LB
TXRDY
RECEIVE AND
TRANSMIT
MICRO CONTROLLERS
TXE
1 - - - -.. RXRDY
1 - - - -.. BRKDET
FiTS
r-----Ci'S
READ/WRITE
CONTROL
LOGIC
RXC
Figure 3.
TXC
RECEIVE/TRANSMIT COMMUNICATIONS CONTROLLER DIAGRAM
377
S
INTERNAL DATA BUS (00-03)
~~----------------------~~------~
~)~ ----~:~I~_c_f_£_i_~i_L__Ji~-------------------~~~~--------~~
(B)
cifS
FREQUENCY
SELECT
ROM
L ____-.--______..J-------[:::::> Fa
DIVIDER
XTAL1
XTAL2
Figure 4 WD2123 BAUD RATE GENERATOR DIAGRAM
The WD2123 registers are addressed by the following table:
I
m
C/O
FiE
WE
CS1
CS2
L
L
H
L
H
H
RECEIVE HOLDING REG.
-
CHA
L
H
L
L
H
H
TRANSMIT HOLDING REG.
-
CHA
H
L
H
L
H
H
STATUS REG.
-
CHA
H
H
L
L
H
H
MODE AND COMMAND REG.
-
CHA
L
L
H
H
L
H
RECEIVE HOLDING REG.
-
CHB
L
H
L
H
L
H
TRANSMIT HOLDING REG.
-
CHB
H
L
H
H
L
H
STATUS REG.
-
CHB
H
H
L
H
L
H
MODE and COMMAND REG.
-
CHB
L
H
L
H
H
L
RATE REG.
-
CHA
H
H
L
H
H
L
RATE REG.
-
CHB
X
X
X
H
H
H
DATA BUS IN HIGH IMPEDANCE MODE
REGISTER SELECTED
Table 2 WD2123 REGISTER ADDRESSING
Note:
"L" means VIL at pins.
"H" means VIH at pins.
"X" means don't care.
~178
The WD2123 contains two MODE REGISTERS-one for
each channel. The format and definition of the
MODE REGISTERS are shown below:
The WD2123 contains two COMMAND REGISTERS-one
per channel. The format and definition of the
COMMAND REGISTERS are shown below:
:e
c
N
.....
N
W
BAUD RATE FACTOR
B2
B1
0
0
0
1
1
0
1
Undefined
1X
16X
64X
L2
L1
CHARACTER LENGTH
1
0
0
0
1
1
0
1
1
5
6
7
8
Bits
Bits
Bits
Bits
TEN
,~
1
0
CS
1-
1
0
REN
fI
r
1
0
TRANSMIT ENABLE
Enable
Disable
CLOCK SELECT
External Clock Select Mode
Internal Clock Select Mode
RECEIVE ENABLE
Enable
Disable
PARITY ENABLE
PEN
SBK
Disable Parity
Enable Parity
0
1
PARITY SELECT
EP
3
1
0
ER
Odd Parity
Even Parity
0
1
S2
S1
0
0
0
1
1
0
NUMBER OF STOP BIT-.a
If
1
0
RTS
1
1
Invalid
1 Bit
1V2 Bits
2 Bits
Table 3 WD2123 MODE REGISTERS
./
')
1
0
IR
1
6
0
LB
7
0
1
~END
BREAK CHARACTER
Force TXD Low
Normal Operation
ERROR RESET
Reset Error Flags
No Reset
REQUEST TO SEND
Force RTS pin = o 010d
Force RTS pin = 1 01 OH)
INTERNAL RESET
Next Write to Mode Register
Next Write to Command
Register
LOOP BACK ENABLE
Normal Operation Mode
Local Loop-Back Mode
Table 4 WD2123 CONTROL REGISTERS
379
The WD2123 contains two STATUS REGISTERS-one per channel. The STATUS REGISTER is a read-only register. The format and definition of the STATUS REGISTERS are shown below:
SR?
SR6
SR5
SR4
CTS
BRK
DET
FE
OE
TXRDY
1
0
RXRDY
1
0
TXE
1
0
PE
1
0
OE
1
0
FE
1
0
BRKDET
1
0
CTS
1
0
SR3
SR2
SR1
SRO
RX
RDY
TX
RDY
TRANSMITTER READY
Denotes THR is empty and ready for a
new character
THR not empty. (Reset when THR is
loaded by CPU)
RECEIVER READY
Denotes that the RHR contains a valid
character
RHR does not contain a valid character.
(Reset when the CPU reads the RHR)
TRANSMITTER EMPTY
Denotes that the TR is empty
Denotes that the TR is not empty
PARITY ERROR
Denotes Parity Error
No Parity Error. (Reset by ER bit of command register)
OVERRUN ERROR
Denotes Overrun Error
No Overrun Error. (Reset by ER bit of
command register)
FRAMING ERROR
Denotes Framing Error
No Framing Error. (Reset by ER bit of
command register)
BREAK DETECT
Indicates that the receiver has detected a
line break condition. (FE will also be set)
No Break Cond ition detected for at least
one bit time
CLEAR-TO-SEND
Indicates that the CTS pin is active (V IL)
Indicates that the CTS pin is not active
(V,H)
Table 5 WD2123 STATUS REGISTERS
380
•
The WD2123 contains two RATE REGISTERS that are used to select 16 BAUD rates when CR1 = 1 and
SELCLK = 1. The Format of the RATE REGISTERS is shown below. Note that the Receiver and the Transrnitter of any channel run off the same Baud clock except when CR1 = 0, then the Transmitter runs off the
Baud Clock and the Receiver runs off an externally applied signal input on the SELCLK pin.
DO
D7
x
RA3
RB3
x
x
RA2
RB2
RA1
RB1
RAO
RBO
When CID = 0, RA3 to RAO are loaded.
When c/15 = 1, RB3 to RBO are loaded.
The CIDline is used in conjunction with CS3 and wg to program the desired BAUD rate. When Cln is low, Channel
A is selected, and when C/l5 is high, Channel B is selected. The low order 4 bits of the DATA BUS are loaded into
the selected rate register, and the high order 4 bits are ignored.
When the crystal frequency equals 1.8432 MHz the following baud rates may be programmed.
R3
R2
R1
RO
BAUD RATE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
50
75
110
134.5
150
200
300
600
1200
1800
2400
3600
4800
7200
9600
19,200
FREQUENCY
.800 KHZ
1.200
1.760
2.150
2.400
3.200
4.800
9.600
19.200
28.800
38.400
57.600
76.800
115.200
153.600
307.200
Table 6 WD2123 BAUD RATE REGISTERS
OPERATING DESCRIPTION
The WD2123 is primarily designed to operate in an 8 bit microprocessor environment, although other control logic
schemes are easily implemented. The DATA BUS and the interface control signals (~, CS2, CS3, C/O, RE, WE) should
be connected to the microprocessor's data bus and system
control bus. A 1.8432 MHz crystal should be connected to
the WD2123 as shown in figure 5. The appropriate TXC
(RXC) clock frequencies should be programmed via system
software. Different Baud clock configurations are possible,
such as separate transmit and receive frequencies, and are
outlined in thet general description.
For typical data communication applications, the RXD and
TXD inpuVoutputs can be connected to RS-232C interface
rn
circuits. Interface control signals,
and RTS, are controlled and sensed by the CPU through the COMMAND and
STATUS REGISTERS and can be configured in several
ways. The CTS input can be used to synchronize the transmitter to external events.
The TXRDY, RXRDY, TXE and BRKDET FLAGS may be
connected to the microprocessor system as interrupt inputs
or the STATUS REGISTER can be periodically read in a
polled environment to support data communication control
operations.
The SBRK bit of the COMMAND REGISTER (CR3) is used
to send a Break Character. (A Break Character is defined as
a start bit, and all zero data, parity and stop bits.) When the
CR3 bit is set to a "1 ", it causes the transmitter output, TXD,
•
381
operating in the system). The programming sequence differs, in that, after a master reset, the chip is set to expect the
first control write operation (C/O = 1) to contain a mode instruction. Any subsequent control write operations will be
transferred to the command instruction register.
to be forced low after the last bit of the last character is
transmitted.
The Receiver is equipped with logic to look for a break character. When a break is received, the BREAK DETECT
(BRKDET) FLAG and STATUS bit are set to "1". When the
receiver input line goes high (II IH) for at least one clock period, the receiver resets the BRKDET FLAG and resumes its
search for a start bit.
Now when it is desired to change the mode instruction
register contents, the following re-programming sequence
should be performed. A Command Control word of "40" Hex
is written to the Chip. This turns off the Receiver and Transmitter and sets the IR (Internal Reset) bit. This bit causes the
read/write control logic to expect the next control write operation to be a new mode instruction. After the new mode
instruction is written to the chip, all subsequent control write
operations will again be interpreted as command instructions. Therefore, after the new mode instruction is performed, the next command would turn the receiver and
transmitter back on and resume normal Data operations.
PROGRAMMING PROCEDURE
The programming sequence of the two channels will be different, depending on whether it is an initialization sequence
(that is, one performed right after a hardware master reset
occurs) or a re-programming sequence (that is, one performed to change the protocol characteristics (Parity, rate,
character length, etc.) after the device has been previously
1.6432 MHz
+5V
30
vee
XTAL1
DO-D7
DATA BUS
FiE
READ
WRii'E
17
29
RESET
WE
MR
INTR
WD2123
ei5
21
23
24
40
38
37
TXRDY-A
RXRDY-A
TXE-A
BRKDET-A
TXRDY-B
RXRDY-B
TXE-B
BRKDET-B
INTRA
AO
• RS232 INTERFACE
ADDRESS BUS
Figure 5 WD2123 MICROPROCESSOR APPLICATION
382
ABSOLUTE MAXIMUM RATINGS
VOO with respect to VSS ........................................... O.SV to +12V
Voltage on Any Pin with Respect to Ground .......................... -O.SV to + 7V
Power Dissipation ................................................. 500Mw.
STORAGE TEMPERATURE:
Ceramic: -65°C to +150°C
Plastic: -55°C to + 125°C
Note: Maximum ratings indicate limits beyond which permanent damage may occur. Continuous operation at these limits is not
intended and should be limited to those conditions specified under dc electrical characteristics.
DC ELECTRICAL CHARACTERISTICS
TA
= O°C to + 70°C; Vee = 5.0V ±5%; GND = OV
SYMBOL
MIN
PARAMETER
TYP
MAX
UNIT
TEST CONDITIONS
--VIL
Input Low Voltage
-0.5
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
IOL
Data Bus Leakage
(High Impedance State)
IlL
Input Leakage
Icc
Power Supply Current
0.8
V
Vee
V
0.45
V
IOL
= 1.6 mA
V
IOH
= -100 uA
-50
10
uA
uA
VOUT
VOUT
10
uA
VIN
125
mA
Vee - 5.25V
No Load
MAX
UNIT
TEST CONDITIONS
2.4
100
= 0.4SV
= Vee
= Vee
Table 7 WD2123 D.C. PARAMETERS
CAPACITANCE
SYMBOL
PARAMETER
MIN
TYP
CIN
Input Capacitance
10
pF
fe = 1MHz
CliO
1/0 Capacitance
20
pF
Unmeasured pins
returned to
GND.
Table 8 WD2123 CAPACITANCE LEVELS
383
AC ELECTRICAL CHARACTERISTICS
=e
Table 9 WD2123 A.C. PARAMETERS
TA = O°C to
+ 70C; Vee
=
5.0V ±5%; GND = OV
C
N
~
SYMBOL
PARAMETER
N
W
BUS PARAMETERS
Read Cycle
I
MIN
MAX
UNITS
tAR
Address Stable Before READ (CS,C/D)
50
ns
tRA
Address Hold Time for READ (CS,C/D)
50
ns
tRE
READ Pulse Width
230
ns
tRO
Data Delay from READ
tROH
READ to Data Floating
25
tAW
Address Stable Before WRITE
50
ns
tWA
Address Hold Time for WRITE
50
ns
tWE
WRITE Pulse Width
230
ns
tos
Data Set-Up Time for WRITE
TWE
ns
tWOH
Data Hold Time for WRITE
100
ns
1.6
us
200
ns
200
ns
CONDITIONS
CL = 50 pF
CL (Max)
CUMin)
= 50 pF
= 15 pF
Write Cycle
OTHER TIMINGS
tTxe
·tOTX
Transmit Clock Period
TxD Delay from Falling Edge of TxC
1000
ns
CL = 100 pF
tSRX
Rx Data Set-Up Time to Sampling Pulse
200
ns
CL = 100 pF
tHRX
Rx Data Hold Time to Sampling Pulse
200
ns
CL = 100 pF
fTX
Transmitter Input Clock Frequency
1x Baud Rate
16x and 64x Baud Rate
DC
DC
Transmitter Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate
1.0
800
us
ns
Transmitter Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
1.0
800
us
ns
500
ns
tTPW
tTPO
tMR
Master Reset
384
500
600
kHz
kHz
Clock
50% Duty
Cycle
Table 9 WD2123 A.C. PARAMETERS
SYMBC
PARAMETER
fRX
tRPW
tRPD
MIN
MAX
Receiver Input Clock Frequency
1x Baud Rate
16x and 64x Baud Rate
DC
DC
500
600
Receiver Input Clock Pulse Width
1x Baud Rate
16x and 64x Baud Rate
1.0
800
us
ns
Receiver Input Clock Pulse Delay
1x Baud Rate
16x and 64x Baud Rate
1.0
800
us
ns
tTX
TxRDY Delay from Center of Stop Bit
tRX
RxRDY Delay from Center of Stop Bit
tiS
Internal BRKDET Delay from Center
of Data Bit
tTRD
tTOD
twc
kHz
kHz
8
tRXC
V2
tRXC
RXe
1
TxRDY Delay from Falling Edge of
WRITE
450
ns
TXD Output from Falling Edge of
WRITE
1V2
tTXC
Control Delay from Rising Edge of
WRITE (RTS)
200
ns
1
Control to READ Set-Up Time (CTS)
tCR
UNIT
tTXC
f----
tMR
Master Reset
[
ns
500
X::
::X
VHAC
VLAC
Figure 6 A.C. TEST POINTS
'''~
DATA BUS
CS, c7D
VHAC
VLAC
l
"00
VLAC
RE
VLAC
tAR
tRE
Figure 7 WD2123 READ TIMING
385
TEST
CONDITION
Clock
50% Duty
Cycle
CL = 50pF (16X)
DATA BUS
CS,
em
Figure 8 WD2123 WRITE TIMING
\~----4~C
r,-
Iwc
_
--------------------------------~~~~,
----------~~~~g
.:::
~-----------------------------~
~v~,
ICR
/
-------~.
Figure 9 WD2123 INTERFACE CONTROL TIMING
ITPW
TXC (1 x CLOCK)
16 Txe PERIODS
x---
TXD
Figure 10 WD2123 TRANSMITTER CLOCK AND DATA TIMING
386
RXD
tSRX
F~XC
(1 x CLOCK)
tRPW
RXD
-t-
tRPD
t
START BIT
-
1st DATA BIT
RXC (16 x CLOCK)
r-
8 Rxe
PERIODS
-1
16 Rxe PERIODS
-1-
n
INTERNAL
SAMPLING PULSE
~
Figure 11 WD2123 RECEIVER CLOCK AND DATA TIMINGS
Txe
es, em
u
tTRD
TXRDY
TXD
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
START BIT
DATA
Figure 12 WD2123 TRANSMITTER OUTPUT TIMINGS WITH RESPECT TO TRANSMIT CLOCK
!
RXD----,I-~S~TA_R_T
~
BIT
__
~~\~-------------L~~-----J
________ DA~ BITS
-1r
RXRDY
RE
tRX
-------1"""L\\..------------------------------------------------------------~~~-
Figure 13 WD2123 RXRDY TIMING
387
TXE
i
-----l·"fL-
TXRDv-GL..--:
VLAC
WE~r-------LJ
TXD--------~~I_~_~_A_RT____~________D_A~~~------------~--~-~-R-ITY--~
I.
lSI DATA BYTE
STOP
BIT(S)
I ~~ART C
---+t+--..I.I
r
2nd DATA
BYTE
Figure 14 WD2123 TXRDY TIMING
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
388
Printed
In
USA
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
BR1941(5016) Dual Baud Rate Clock
FEATURES
GENERAL DESCRIPTION
• 16 SELECTABLE BAUD RATE CLOCK FREQUENCIES
• SELECTABLE 1X, 16X OR 32X CLOCK OUTPUTS FOR
FULL DUPLEX OPERATIONS
• OPERATES WITH CRYSTAL OSCILLATOR OR
EXTERNALLY GENERATED FREQUENCY INPUT
• ROM MASKABLE FOR NON-STANDARD FREQUENCY
SELECTIONS
• INTERFACES EASILY WITH MICROCOMPUTERS
• OUTPUTS A 50% DUTY CYCLE CLOCK WITH 0.01 %
ACCURACY
• 6 DIFFERENT FREQUENCY/DIVISOR PAIRS
AVAILABLE
• TTL, MOS COMPATIBILITY
The BR1941 is a combination Baud Rate Clock Generator and Programmable Divider. It is manufactured in
N-channel MOS using silicon gate technology. This davice is capable of generating 16 externally selected
clock rates whose frequency is determined by either a
single crystal or an externally generated Input clock.
The BR1941 is a programmable counter capable of
generating a division from 2 to (215 -1).
The BR1941 is available programmed with the most
used frequencies in data communication. Each
frequency is selectable by strobing or hard wiring each
of the two sets of four Rate Select inputs. Other
frequencies/division rates can be generated by
reprogramming the internal ROM coding through a
MOS mask change. Additionally, further clock division
may be accomplished through cascading of devices.
The frequency output is fed into the XTAUEXT Input
on a subsequent device.
• PIN COMPATIBLE WITH COM5016
FREQUENCY
SELECT
ROM
XTAUEXT 1
XTAUEXT 2
vCC
fT
fR
TA
RA
TS
RS
TC
RC
TO
RO
STT
STR
GNO
vOO
NC·
DIVIDER
fT
DIVIDER
fR
RC
RD
*INTERNALLY SONOED. DO NOT CONNECT
ANYTHING TO THIS PIN.
PIN CONNECTIONS
BR1941 BLOCK DIAGRAM
389
PIN DESCRIPTION
PIN NUMBER
SYMBOL
1
XTALlEXT 1
Crystal or
External Input 1
2
VCC
Power Supply
+ 5 volt Supply
3
fR
Receiver Output
Frequency
This output runs at a frequency selected by the
Receiver Address inputs.
Receiver Address
The logic level on these inputs as shown in Tables 1
through 6, selects the receiver output frequency, fA-
Strobe-Receiver
Address
A high-level input strobe loads the receiver address
(RA, RB, RC, RO) into the receiver address register.
This input may be strobed or hard wired to + 5V.
4-7
This input receives one pin of the crystal package or
one polarity of the external input.
8
STR
9
Voo
Power Supply
+ 12 volt Supply
10
NC
No Connection
Internally bonded. Do not connect anything to this
pin.
11
GNO
Ground
Ground
12
sn
Strobe-Transmitter
Address
A high-level input strobe loads the transmitter address
(TA, TB, TC, TO) into the transmitter address register.
This input may be strobed or hard wired to + 5V.
TO, TC, TB, TA
Transmitter
Address
The logic level on these inputs, as shown in Tables 1
through 6, selects the transmitter output frequency, fr-
Transmitter
Output
Frequency
This output runs at a frequency selected by the
Transmitter Address inputs.
Crystal or
External
Input 2
This input receives the other pin of the crystal
package or the other polarity of the external input.
13-16
17
XTALlEXT 2
18
NOTE 1
r-r----TpW·~
VIH
lr--~------------~I
STROBE
I
(STRISTT)
VIL __--L_--' I
~_-
TSET.UPI _ _
VIH~
ADDRESS
VIL
FUNCTION
NAME
EXTERNAL INPUT OPERATION
BR1941
BR1941
l' IDrl ~'>- u~[') ~1JJ
.BV
5.0688 MHz
-1
__--,t=-
______
~
CRysm
LD
-THO
.
~~~V
CRYSTAL OPERATION
.------------~
·ADDRESS NEED ONLY BE VALID DURING THE LAST
TPW TIME OF THE INPUT STROBE
74XX -
CONTROL TIMING
TOTEM POLE OR OPEN COLLECTOR OUTPUT
CRYSTAUCLOCK OPTIONS
ABSOLUTE MAXIMUM RATINGS
Positive Voltage on any Pin, with respect to ground
+ 20.0V
Negative Voltage on any Pin, with respect to ground
- 0.3V
(plastic package) - 55°C to + 125°C
(cerdip package and ceramic package) - 65°C to + 150°C
Storage Temperature
Lead Temperature (Soldering, 10 sec.)
• Stresses above those listed may cause permanent damage to the device. This is a stress
rating only and Functional Operation of the device at these or at any other condition
above those indicated in the operational sections of this specification are not implied.
390
+ 325°C
ELECTRICAL CHARACTERISTICS
(TA
= O°C to + 70°C, Vee = + 5V ± 5%, Voo = + 12V ± 5%, unless otherwise noted)
PARAMETER
MIN
TYP
MAX
UNIT
COMMENTS
0.8
VCC
V
V
See Note 1
0.4
V
V
IOL
IOH
= 3.2 rnA
= 1ool-lA
0.3
rnA
VIN
= GNO, excluding XTAL inputs
10
pf
VIN
= GNO, excluding XTAL inputs
KQ
Resistance to ground for
Pin 1 and Pin 18
DC CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VIL
High-level, VIH
VCC-1.5
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
VCC-1.5
4.0
INPUT CURRENT
Low-level, IlL
INPUT CAPACITANCE
All Inputs, CIN
INPUT RESISTANCE
Crystal Input, RXTAL
5
1.1
POWER SUPPLY CURRENT
ICC
100
20
20
60
70
rnA
rnA
= +25°C
AC CHARACTERISTICS
TA
CLOCK FREQUENCY
See Note 2
PULSE WIDTH (TPW)
Clock
Receiver strobe
Transmitter strobe
150
150
INPUT SET-UP TIME (TSET-UP)
Address
50
ns
OUTPUT HOLD TIME (THOLO)
Address
50
ns
50% duty cycle ± 10%. See Note 2
OC
OC
ns
ns
See Note 3
NOTE 1: BR1941 - XTAUEXT inputs are either TTL compatible or crystal compatible. See crystal specification in Applications Information section.
All inputs except XTAUEXT have internal pull-up resistors.
NOTE 2: Refer to frequency option tables for maximum input frequency on XTAUEXT pins.
Typical Clock Pulse width is 1/2xCL.
NOTE 3: Input set-up time can be decreased to ;.:0 ns by increasing the minimum strobe width by 50 ns to a total of 200 ns.
OPERATION
Non-Standard Frequencies
Standard Frequencies
To accomplish non-standard frequencies do one of the
following:
Choose a Transmitter and Receiver frequency from the
table below. Program the corresponding address into TATO and RA-RD respectively using strobe pulses or by hard
wiring the strobe and address inputs.
1. Choose a crystal that when divided by the BR1941
generates the desired frequency.
2. Cascade devices by using the frequency outputs as an
391
3. Consult the factory for possible changes via ROM mask
reprogramming.
input to the XTAUEXT inputs of the subsequent
BR1941.
FREQUENCY OPTIONS
TABLE 1. CRYSTAL FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
B
C
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud
Rate
Theoretical
l16X Clock) Fre~. (kHz)
50
0.8
75
1.2
110
1.76
134.5
2.152
150
2.4
300
4.8
600
9.6
1200
19.2
1800
28.8
2000
32.0
2400
38.4
3600
57.6
4800
76.8
7200
115.2
9600
153.6
19,200
307.2
= 5.0688 MHZ
Actual
Freq. (kHz)
0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
Percent
Error
0.016
0.253
-
-
-
3.125
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
48/52
50/50
Divisor
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
Divisor
3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
Divisor
7523'
5015'
3420
2797*
2508
1881'
1254
627'
31.3'
209'
188
157*
104
78
39'
20
BR1941-00
TABLE 2. CLOCK FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
B
C
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud
Rate
Theoretical
(16X Clock) Freq. (kHz)
50
0.8
75
1.2
110
1.76
134.5
2.152
150
2.4
200
3.2
300
4.8
9.6
600
1200
19.2
1800
28.8
32.0
2000
2400
38.4
3600
57.6
4800
76.8
153.6
9600
19,200
307.2
2.76480 MHZ
Actual
Freq. (kHz)
0.8
1.2
1.76
2.152
2.4
3.2
4.8
9.6
19.2
28.8
32.15
38.4
57.6
76.8
153.6
307.2
Percent
Error
-
-
-0.006
- 0.019
-
-
+ 0.465
-
-
-
BR1941-02
TABLE 3. CRYSTAL FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
C
B
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud
Rate
Theoretical
(16X Clock) Freq. (kHz)
50
0.8
75
1.2
110
1.76
134.5
2.152
150
2.4
200
3.2
300
4.8
600
9.6
1200
19.2
1800
28.8
2000
32.0
2400
38.4
3600
57.6
4800
76.8
153.6
9800
19,200
307.2
BR1941-03
:392
6.018305 MHZ
Actual
FrElg. (kH&
.7999
1.2000
1.7597
2.1517
2.3996
3.1995
4.7993
9.5986
19.2279
28.7959
32.0125
38.3334
57.8687
77.1583
154.3166
300.9175
Percent
Error
0
0
0
0
0
0
0
0
+0.14
0
0
-0.17
+0.46
+0.46
+0.46
-2.04
TABLE 4. CLOCK FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
C
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
5.52960 MHZ
A
Baud
Rate
(16X Clock)
Theoretical
Freq. (kHz)
Actual
Freq. (kHz)
Percent
Error
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800
9600
19,200
1.6
2.4
3.52
4.304
4.8
6.4
9.6
19.2
38.4
57.6
64.0
76.8
115.2
153.6
307.2
614.4
1.6
2.4
3.52
4.303
4.8
6.4
9.6
19.2
38.4
57.6
64.3
76.8
115.2
153.6
307.2
614.4
-
-0.006
- 0.019
-
+0.465
-
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
Divisor
3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9
BR1941-04
TABLE 5. CRYSTAL FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
C
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
4.9152 MHZ
A
Baud
Rate
(32X Clock)
Theoretical
Freq. (kHz)
Actual
Freg. ~kHz!
Percent
Error
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19,200
0.8
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
57.8258
76.8
114.306
153.6
307.2
-
-0.01
-
Duty
Cycle
%
50/50
50/50
·
-
50/50
50/50
50/50
50/50
50/50
-
50/50
50/50
-
-
-0.19
-0.26
0.39
-0.77
-
·
·
·
50/50
50/50
50/50
Divisor
6144
4096
2793
2284
2048
1024
512
256
171
154
128
85
64
43
32
16
BR1941-05
TABLE 6. CRYSTAL FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
·When
Transmit/Receive
Address
C
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
the duty cycle IS not
A
Baud
Rate
(32X Clock)
Theoretical
Freq. (kHz)
1.6
0
50
0
75
1
2.4
0
110
1
3.52
0
134.5
4.304
1
1
150
4.8
0
0
200
6.4
0
1
9.6
1
300
0
600
19.2
1
1
1200
38.4
0
0
1
1800
57.6
0
1
2400
76.8
0
115.2
1
1
3600
4800
153.6
0
0
1
7200
230.4
0
1
307.2
9600
0
19,200
614.4
1
1
exactly 50% It IS 50% ± 10%
BR1941-06
393
5.0688 MHZ
Actual
Freg. ~kHz!
1.6
2.4
3.52
4.303
4.8
6.4
9.6
19.2
38.4
57.6
76.8
115.2
153.6
230.4
298.16
633.6
Percent
Error
.026
-
-
-
2.941
3.125
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
Dlvlso!___
3168
2112
1440
1178
1056
792
528
264
132
88
66
44
33
22
17
8
Bliley Electric Co.
2545 Grandview Blvd.
Erie, Pennsylvania 16508
(814) 838-3571
CRYSTAL SPECIFICATIONS
User must specify termination (pin, wire, other)
Frequency - See Tables 1-6.
Temperature range O°C to + 70°C
Series resistance E;; 50Q
Series resonant
Overall tolerance ± .01 %
CRYSTAL MANUFACTURERS (Partial List)
M-tron Ind. Inc.
P.O. Box 630
Yankton, South Dakota 57078
(605) 665-9321
American Time Products Div.
Frequency Control Products, Inc.
61-20 Woodside Ave.
Woodside, New York 11377
(212) 458-5811
Erie Frequency Control
453 Lincoln St.
Calisle, Pennsylvania 17013
(714) 249-2232
APPLICATIONS INFORMATION
OPERATION WITH A CRYSTAL
a. parallel ground lines
The BR1941 Baud Rate Generator may be driven by either a
crystal or TTL level clock. When using a crystal, the waveform that appears at pins 1 (XTALlEXT 1) and 18 (XTALlEXT
2) does not conform to the normal TTL limits of VIL E;; 0.8V
and VIH ~ 2.0V. Figure 1 illustrates a typical crystal
waveform when connected to a BR1941.
b. evenly spaced ground lines crossing the trace on the
opposite side of PC board
c. an inner plane of ground, e.g., as in a four layered PC
board.
In the event that ringing exists on an already finished
board, several techniques can be used to reduce it. These
are:
Since the D.C. level of the waveform causes the least
positive point to typically be greater than 0.8V, the BR1941
is designed to look for an edge, as opposed to a TTL level.
The XTALlEXT logic triggers on a rising edge of typically 1V
in magnitude. This allows the use of a crystal without any
additional components.
1. Add a series resistor to match impedance as shown in
Figure 3.
2. Add pull-up/pull-down resistor to match impedance, as
shown in Figure 4.
3. Add a high speed diode to clamp undershoot, as shown
in Figure 5.
OPERATIONS WITH TTL LEVEL CLOCK
With clock frequencies in the area of 5 MHz, significant
overshoot and undershoot ("ringing") can appear at pins 1
and/or 18. The BR1941, may, at times, be triggered on a
rising edge of an overshoot or undershoot waveform,
causing the device to effectively "double-trigger." This
phenomenon may result as a twice expected baud rate, or
as an apparent device failure. Figure 2 shows a typical
waveform that exhibits the "ringing" problem.
The method that is easiest to implement in many systems
is method 1, the series resistor. The series resistor will
cause the D.C. level to shift up, but that does not cause a
problem since the BR1941 is triggered by an edge, as
opposed to a TTL level.
The BR1941 Baud Rate Generator can save both board
space and cost in a communications system. By choosing
either a crystal or a TTL level clock, the user can minimize
the logic required to provide baud rate clocks in a given
design.
The design methods required to minimize ringing include
the following:
1. Minimize the P.C. trace length. At5 MHz, each inch of
trace can add significantly to overshoot and undershoot.
2. Match impedances at both ends of the trace. For
example, a series resistor near the BR1941 may be
helpful.
3. A uniform impedance is important. This can be accomplished through the use of:
POWER LINE SPIKES
Voltage transients on the AC power line may appear on the
DC power output. If this possibility exists, it is suggested
that one by-pass capacitor is used between + 5V and GND
and another between + 12V and GND.
394
m
:D
.....
CD
+ 5.0
5.0
~
.....
+ 4.0
VOLTS
VOLTS
3.0
"§
.....
+3.0
+ 2.0
2.0
+ 1.0
.9
1.0
2T
3T
4T
0
----
-1.0
Time
Time
Figure 1 TYPICAL CRYSTAL WAVEFORM
Figure 2 TYPICAL "RINGING" WAVEFORM
-{>o-R1
f">----I\/\/\/'__~
R2
~
18~~
1
Typical Values
R1 = R2 = 33!l
BR1941
Figure 3 SERIES RESISTOR TO MATCH IMPEDANCE
r5V
]
Typical Values
R1 = R3 = :>.7K
R2 = R4 = 3.3K
Figure 4 PULL-UP/PULL-DOWN RESISTORS TO MATCH IMPEDANCE
Figure 5 HIGH-SPEED DIODE TO CLAMP UNDERSHOOT
See page 725 for ordering information.
395
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
396
Pronled
In
U S.A
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
WD1943(8116)IWD1945(8136) Dual Baud Rate Clock
FEATURES
GENERAL DESCRIPTION
-16 SELECTABLE BAUD RATE CLOCK FREQUENCIES
The WD1943/45 is an enhanced version of the BR1941 Dual
Baud Rate Clock. The WD1943/45 is a combination Baud
Rate Clock Generator and Programmable Divider. It is
manufactured in N-channel MOS using silicon gate
technology. This device is capable of generating 16 externally selected clock rates whose frequency is determined by either a single crystal or an externally generated
input clock. The WD1943/45 is a programmable counter
capable of generating a division by any integer from 4 to
215 - 1, inclusive.
-OPERATES WITH CRYSTAL OSCILLATOR OR EXTERNALLY GENERATED FREQUENCY INPUT
- ROM MASKABLE FOR NON-STANDARD FREQUENCY
SELECTIONS
-INTERFACES EASILY WITH MICROCOMPUTERS
- OUTPUTS A 50% DUTY CYCLE CLOCK WITH 0.01 %
ACCURACY
- 6 DIFFERENT FREQUENCYIDIVISOR PAIRS
AVAILABLE
- SINGLE
The WD1943/45 is available programmed with the most
used frequencies in data communication. Each frequency
is selectable by strobing or hard wiring each of the two sets
of four Rate Select inputs. Other frequencies/division rates
can be generated by reprogramming the internal ROM
coding through a MOS mask change. Additionally, further
clock division may be accomplished through cascading of
devices. The frequency output is fed into the XTAUEXT
Input on a subsequent device.
+ 5V POWER SUPPLY
- COMPATIBLE WITH BR1941
- TTL, MOS COMPATIBILITY
- WD1943IS PIN COMPATIBLETOTHECOM8116
- WD1915IS PIN COMPATIBLE TO THE COM~136 AND
COM5036 (PIN 9 ON WD1945IS A NO CONNECT)
The WD1943/45 can be driven by an external crystal or by
TTL logic.
TATBTC-
FREQUENCY
SELECT
ROM
TD-
XTALlEXT 1
XTALlEXT 2
+5V
fT
fR
TA
XTAU
EXT 1
RA
TS
XTAU_
EXT 2
Rs
TC
Rc
TO
Ro
STT
DIVIDER
f/4
(1945)
DIVIDER
STR
GNO
NC
'T
NC (1943)
f/4(1945)
PIN CONNECTIONS
BLOCK DIAGRAM
397
'R
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
NAME
1
XTAUEXT1
2
VCC
Power Supply
+ 5 volt Supply
3
fR
Receiver Output
Frequency
This output runs at a frequency selected by the Receiver
Address inputs.
RA, RS, RC, RO
Receiver Address
The logic level on these inputs as shown in Table 1 thru 6,
selects the receiver output frequency, fRo
STR
Strobe-Receiver
Address
A high-level input strobe loads the receiver address (RA, RB,
RC, RO) into the receiver address register. This input may be
strobed or hard wired to + 5V.
4-7
8
This input receives one pin of the crystal package or one
polarity of the external input.
Crystal or
External Input 1
9
NC
No Connection
No Internal Connection
10
NC(1943)
f/4 (1945)
No Connection
freq/4 Output
No Internal Connection
XTAL 1 input freq divided by four.
11
GNO
Ground
Ground
12
STT
Strobe-Transmitter
Address
A high-level input strobe loads the transmitter address (TA,
TS, TC, TO) into the transmitter address register. This input
may be strobed or hard wired to + 5V.
TO, TC, TS, TA
Transmitter
Address
The logic level on these inputs, as shown in Table 1 thru 6,
selects the transmitter output frequency, fT.
17
fT
Transmitter
Output
Frequency
This output runs at a frequency selected by the Transmitter
Address inputs.
18
XTA LI EXT 2
Crystal or
External
Input 2
This input receives the other pin of the crystal package or the
other polarity of the external input.
13-16
CRYSTAL OPERATION
WD1943145
EXTERNAL INPUT OPERATION
WD1943/45
~;,;r,.~~ ,«,~
~
IT.
~
IT.
~
74XX TOTEM POLE OR OPEN COLLECTOR OUTPUT
• ADDRESS NEED ONLY BE VALID DURING THE LAST
TPW TIME OF THE INPUT STROBE
CONTROL TIMING
CRYSTAUCLOCK OPTIONS
ABSOLUTE MAXIMUM RATINGS
Positive Voltage on any Pin, with respect to ground
+ 7.0V
Negative Voltage on any Pin, with respect to ground
- 0.3V
(plastic package) - 55°C to
(Cerdip package and Ceramic package) - 65°C to
Storage Temperature
+ 125°C
+ 150°C
+ 325°C
Lead Temperature (Soldering, 10 sec.)
* Stresses above those listed may cause permanent damage to the device. This is a stress
rating only and Functional Operation of the device at these or at any other condition
above those indicated in the operational sections of this specification are not implied.
398
ELECTRICAL CHARACTERISTICS' (TA
PARAMETER
= O°C to + 70°C, VCC = + 5V ± 5% standard.)
MIN
TYP
COMMENTS
MAX
UNIT
0.8
VCC
V
V
See Note 1
0.4
V
V
IOL = 3.2mA
IOH = 10q..IA
INPUT CURRENT
High-level, IIH
Low-level, IlL
-10
10
300
jAA
jAA
jAA
Low-level, IlL
10
jAa
VIN = VCC STR (8) and STT (12)
VIN = GND Only
VIN = GND (All inputs except
XTAL, STR and STT)
VIN = GNDSTR,STT
pf
DC CHARACTERISTICS
INPUT VOLTAGE LEVELS
Low-level, VIL
High-level, VIH
OUTPUT VOLTAGE LEVELS
Low-level, VOL
High-level, VOH
2.0
VCC-1.5
4.0
INPUT CAPACITANCE
All Inputs, CIN
5
10
EXT. INPUT LOAD
4
5
INPUT RESISTANCE
Crystallnpllt, RXTAL
KQ
1.1
40
POWER SUPPLY CURRENT
ICC
80
VIN = GND, excluding XTAL inputs
Series 7400 unit loads
Resistance to ground for
Pin 1 and Pin 18
mA
AC CHARACTERISTICS
TA = +25°C
CLOCK FREQUENCY
See Note 2
PULSE WIDTH (TpW)
Clock
Receiver strobe
Transmitter strobe
150
150
INPUT SET-UP TIME (TSET-UP)
Address
OUTPUT HOLD TIME (THOLD)
Address
ns
ns
50% Duty Cycle ± 10%. See Note 2
See Note3
See Note3
50
ns
See Note 3
50
ns
DC
DC
STROBE TO NEW FREQUENCY
DELAY
6
CLK
--
NOTE1: XTAUEXT inputs are either TTL compatible or crystal compatible. See crystal specification in
Applications Information section.
All inputs except XTAL, STR and STT have internal pull-up resistors.
NOTE 2: Refer to frequency option tables for maximum input frequency on XTAUEXT pins.
Typical clock pulse width is 1/2 x CL
NOTE 3: Input set-up time can be decreased to >0 ns by increasing the minimum strobe width (50 ns) to a total of 200 ns.
T A-D and RA-D have internal pull-up resistors.
OPERATION
Non-Standard Frequencies
Standard Frequencies
To accomplish non-standard frequencies do one of the
following:
Choose a Transmitter and Receiver frequency from the
table below. Program the corresponding address into TA-TD
and RA-RD respectively using strobe pulses or by hard
wiring the strobe and address inputs.
1. Choose a crystal that when divided by the WD1943
generates the desired frequency.
2. Cascade devices by using the frequency outputs as an
input to the XTAUEXT inputs of the subsequent
WD1943/45.
3. Consult the factory for possible changes via ROM mask
reprogramming.
399
FREQUENCY OPTIONS
TABLE 1. CRYSTAL FREQUENCY
--
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
B
C
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud
Theoretical
Rate
(16X Clock) FreQ. (kHz)
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
5.0688 MHZ
Actual
FreQ. (kHz)
Percent
Error
0.8
1.2
1.76
2.1523
2.4
4.8
9.6
19.2
28.8
32.081
38.4
57.6
76.8
115.2
153.6
316.8
-
0.8
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2
0.016
-
0.253
-
-
3.125
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
48/52
50/50
Divisor
6336
4224
2880
2355
2112
1056
528
264
176
158
132
88
66
44
33
16
WD1943-00 orWD1945·00
TABLE 2. CLOCK FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
C
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud
Rate
Theoretical
(16X Clock) Freq. (kHz)
50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800
9600
19200
2.76480 MHZ
Actual
Freq. {kHz)
Percent
Error
0.8
1.2
1.76
2.152
2.4
3.2
4.8
9.6
19.2
28.8
32.15
38.4
57.6
76.8
153.6
307.2
-
0.8
1.2
1.76
2.152
2.4
3.2
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
153.6
307.2
-
-0.006
-0.019
-
+0.465
-
-
-
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
Divisor
3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9
WD1943-02 or WD1945-02
TABLE 3. CRYSTAL FREQUENCY = 6.018305 MHZ
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
C
B
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud
Theoretical
Rate
(16X Clock) FreQ. (kHz)
50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800
9800
19200
0.8
1.2
1.76
2.152
2.4
3.2
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
153.6
307.2
Actual
FreQ. (kHz)
Percent
Error
.7999
1.2000
1.7597
2.1517
2.3996
3.1995
4.7993
9.5986
19.2279
28.7959
32.0125
38.3334
57.8687
77.1583
154.3166
300.9175
0
0
0
0
0
0
0
0
+0.14
0
0
-0.17
+0.46
+0.46
+0.46
-2.04
WD1943-03 or WD1945-03
400
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
Divisor
7523*
5015*
3420
2797*
2508
1881*
1254
627*
31.3*
209*
188
157*
104
78
39*
20
TABLE 4. CLOCK FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
B
C
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud
Rate
(32X Clock)
50
75
110
134.5
150
200
300
600
1200
1800
2000
2400
3600
4800
9600
19200
5.52960 MHZ
Theoretical
Freq. (kHz)
1.6
2.4
3.52
4.304
4.8
6.4
9.6
19.2
38.4
57.6
64.0
76.8
115.2
153.6
307.2
614.4
Actual
Freq. (kHz)
1.6
2.4
3.52
4.303
4.8
6.4
9.6
19.2
38.4
57.6
64.3
76.8
115.2
153.6
307.2
614.4
Percent
Error
-
-0.006
-0.019
+0.465
-
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
Divisor
3456
2304
1571
1285
1152
864
576
288
144
96
86
72
48
36
18
9
WD1943-04 or WD1945-04
TABLE 5. CRYSTAL FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Transmit/Receive
Address
B
C
0
0
0
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
0
1
1
1
1
1
A
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Baud
Rate
(16X Clock)
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
Theoretical
Freq. (kHz)
0.8
1.2
1.76
2.152
2.4
4.8
9.6
19.2
28.8
32.0
38.4
57.6
76.8
115.2
153.6
307.2
4.9152 MHZ
Actual
Freq. (kHz)
0.8
1.2
1.7598
2.152
2.4
4.8
9.6
19.2
28.7438
31.9168
38.4
57.8258
76.8
114.306
153.6
307.2
Percent
Error
-0.Q1
-
-0.19
-0.26
-0.77
0.39
Duty
Cycle
%
50/50
50/50
*
50/50
50/50
50/50
50/50
50/50
*
50/50
50/50
*
50/50
*
50/50
50/50
Divisor
6144
4096
2793
2284
2048
1024
512
256
171
154
128
85
64
43
32
16
Duty
Cycle
%
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
50/50
*
50/50
*
50/50
Divisor
3168
2112
1440
1178
1056
792
528
264
132
88
66
44
33
22
17
8
WD1943-050rWD1945-05
TABLE 6. CRYSTAL FREQUENCY
D
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
*When
Transmit/Receive
Baud
Address
Rate
(32X Clock)
B
A
C
0
0
0
50
0
0
1
75
110
1
0
0
134.5
1
1
0
1
0
0
150
1
1
200
0
300
1
1
0
1
1
1
600
1200
0
0
0
1
1800
0
0
1
0
2400
0
1
1
3600
0
0
4800
0
1
1
7200
1
0
1
1
0
9600
1
1
1
19200
the duty cycle Is not exactly 50% It is 50% ± 10%
5.0688 MHZ
Theoretical
Actual
Freq. (kHz) . FreJi. (kH&
1.6
1.6
2.4
2.4
3.52
3.52
4.303
4.304
4.8
4.8
6.4
6.4
9.6
9.6
19.2
19.2
38.4
38.4
57.6
57.6
76.8
76.8
115.2
115.2
153.6
153.6
230.4
230.4
307.2
298.16
614.4
633.6
WD1943-06 or WD1945-06
•
401
Percent
Error
-
2.941
.026
3.125
:IE
c.....
i
.....
.....
-:cIE
.9
.....
~
~
.....
$
APPLICATIONS INFORMATION
The method that is easiest to implement in many systems
is method 1, the series resistor. The series resistor will
cause the D.C. level to shift up, but that does not cause a
problem since the OSC is triggered by an edge, as opposed
to a TTL level.
OPERATION WITH A CRYSTAL
The WD1943/45 Baud Rate Generator may be driven by
either a crystal or TTL level clock. When using a crystal, the
waveform that appears at pins 1 (XTALlEXT 1) and 18
(XTALlEXT 2) does not conform to the normal TTL limits of
VIL ~ 0.8V and VIH ~ 2.0V. Figure 1 illustrates a typical
crystal waveform when connected to a WD1943/45.
The 1943/45 Baud Rate Generator can save both board
space and cost in a communications system. By choosing
either a crystal or a TIL level clock, the user can minimize
the logic required to provide baud rate clocks in a given
design.
Since the D.C. level of the waveform causes the least
positive pOint to typically be greater than 0.8V, the
WD1943/45 is designed to look for an edge, as opposed to a
TIL level. The XTAUEXT logic triggers on a rising edge of
typically 1V in magnitude. This allows the use of a crystal
without any additional components.
POWER LINE SPIKES
OPERATIONS WITH TTL LEVEL CLOCK
With clock frequencies in the area of 5 MHz, significant
overshoot and undershoot ("ringing") can appear at pins 1
and/or 18. The clock oscilator may, at times be triggered on
a rising edge of an overshoot or undershoot waveform,
causing the device to effectively "double-trigger." This
phenomenon may result as a twice expected baud rate, or
as an apparent device failure. Figure 2 shows a typical
waveform that exhibits the "ringing" problem.
Voltage transients on the AC power line may appear on the
DC power output. If this possibility exists, it is suggested
that a by-pass capacitor is used between + 5V and GND.
CRYSTAL SPECIFICATIONS
User must specify termination (pin, wire, other)
Frequency - See Tables 1-6.
Temperature range O°C to + 70°C
Series resistance ~ 50Q
Series resonant
Overall tolerance ± 0.01 %
The design methods required to minimize ringing include
the following:
1. Minimize the P.C. trace length. At 5 MHz, each inch of
trace can add Significantly to overshoot and undershoot.
2. Match impedances at both ends of the trace. For
example, a series resistor near the device may be
helpful.
3. A uniform impedance is important. This can be accomplished through the use of:
a parallei ground lines
b. evenly spaced ground lines crossing the trace on the
opposite side of PC board
c. an inner plane of ground, e.g., as in a four layered PC
board.
CRYSTAL MANUFACTURERS (Partial List)
American Time Products Div.
Frequency Control Products, Inc.
61-20 Woodside Ave.
Woodside, New York 11377
(213) 458-5811
Bliley Electric Co.
2545 Grandview Blvd.
Erie, Pennsylvania 16508
(814) 838-3571
In the event that ringing exists on an already finished
board, several techniques can be used to reduce it. These
are:
M-tron Ind. Inc.
P.O. Box 630
Yankton, South Dakota 57078
(605) 665-9321
1. Add a series resistor to match impedance as shown in
Figure 3.
2. Add pull-up/pull-down resistor to match Impedance, as
shown in Figure 4.
3. Add a high speed diode to clamp undershoot, as shown
in Figure 5.
Erie Frequency Control
453 Lincoln St.
Calisle, Pennsylvania 17013
(714) 249-2232
402
+5.0
5.0
VOLTS
+4.0
4.0V',-- A A A
A
_
V ""v V
\J V
VOLTS
+3.0
3.0
+2.0
2.0
+ 1.0
1.0
-"-+---------\---f-~...",..-L----
.. -_.
-1.0
2T
3T
4T
Time
Time
Figure 1. TYPICAL CRYSTAL WAVEFORM
Figure 2. TYPICAL "RINGING" WAVEFORM
from TTL INPUT
R2
~D- ~A~R1~_______~1~1-------~--1~'~
...
____
Typical Values
R'1-;';-R2~:l3Q
WD1943145
Figure 3. SERIES RESISTOR TO MATCH IMPEDANCE
+ 5V
R3b
+5V
R1.
~I>----~~--
1
__-I
~
1
R4
18
r---'
Typical Values
R2
WD1943145
=
=
R1
R3
2.7K
R2 = R4 = 3.3K
Figure 4. PULL·UP/PULL·DOWN RESISTORS TO MATCH IMPEDANCE
Figure 5. HIGH·SPEED DIODE TO CLAMP UNDERSHOOT
See page 725 for ordering information.
403
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from Its use. No license Is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
404
Printed on U S.A
WESTERN DIGITAL
CORPORATION
•
PR1472 (PSAR)
Programmable Synchronous & Asynchronous Receiver
GENERAL DESCRIPTION
FEATURES
• SYNCHRONOUS, ASYNCHRONOUS OR
ISOCHRONOUS OPERATION
• DC TO 640K BITS/SEC (1X CLOCK) PR1472-01;
DC TO 100K BITS/SEC PR1472
• PROGRAMMABLE MATCH (FILL) CHARACTER WITH MATCH DETECT FLAG.
• INTERNAL OR EXTERNAL CHARACTER
SYNCHRONIZATION
• NINE BIT WIDE RECEIVER HOLDING
REGISTER
• SELECTABLE 5, 6, 7 OR 8 BITS PER
CHARACTER
• EVEN/ODD OR NO PARITY SELECT
• PROGRAMMABLE CLOCK RATE; 1X, 16X, 32X
OR 64X
., AUTOMATIC START AND STOP BIT STRIPPING
II
AUTOMATIC CHARACTER STATUS AND
FLAG GENERATION
" THREE STATE OUTPUTS - BUS STRUCTURE
CAPABILITY
" DOUBLE BUFFERED
" TTL & DTL COMPATIBLE - INTERNAL
ACTIVE PULLUP
CI
COMPATIBLE TRANSMITTER, PT1482
The Western Digital PR1472 (PSAR) is a programmable receiver that interfaces variable length serial
data to a parallel data channel. The receiver converts a serial data stream into parallel characters
with a format compatible with all standard Synchronous, Asynchronous, or Isochronous data
communications media.
Contiguous synchronous serial characters are
compared to a programmable Match-Character
Holding Register, character synchronized and
assembled. Programming the Asynchronous or
Isochronous Mode provides assembly of characters
with start and stop bit(s) which are stripped from
the data. Four internal registers, in conjunction
with Three-State Outputs provide full system
versatility.
The PSAR is a TTL compatible device. The use of
internal active pull-up devices and push-pull
output drivers, provides direct compatibility with
all forms of current sinking logic. Western Digital
also offers a Compatible Transmitter, the PT1482.
(-SV)V55
RM53
MHR5
MHR7
WLS,
CD
RRg
MR
RR8
RR7
MR
RR6
RRC
RR5
MDET
RR4
PE
RFI3
FE;55
CD
MDET
RFl2
RFll
(12V) VGG
SFR
MHI~l
WLS2
PI
(GND) V[lD
PIN CONNECTIONS
PR1472 BLOCK DIAGRAM
405
PIN
NUMBER
!
1/0 NAME
1
POWER SUPPLY
37,39,2
RECEIVER MODE
SELECT
FUNCTION
SYMBOL
+ 5 Volt Supply
A low-level input voltage, VIL, applied to CD (pin
6) enables RMS1, RMS2, and RMS3 inputs. The
Receiver Mode Select Inputs, in conjunction with
the Control Register Load and Chip Disable,
select the Receiver operating mode. RMS1, RMS2,
and RMS3 may be strobed or hard-wired to the
appropriate input voltage.
RMS3
RMS2
RMS,
0
0
0
0
0
1
0
1
0
0
1
1
1
X
0
1
X
1
Selected Operating Mode
ASYNCH OR ISOCH,
1XCLOCK
ASYNCH OR ISOCH,
16X CLOCK
ASYNCH OR ISOCH,
32X CLOCK
ASYNCH OR ISOCH,
64X CLOCK
SYNCH-EXTERNAL
CHARACTER
SYNCHRONIZATION
SYNCH-INTERNAL
CHARACTER
SYNCHRONIZATION
NOTE: When operating in asynchronous or
isochronous mode with 1X clock there is
no protection against false start bits.
A high-level input voltage, V1H , applied to CD disables RMS" RMS2 and RMS3.
18,22
MATCH-CHARACTER
17,36,3, HOLDING REGISTER
38,4,40 DATA
5,23
WORD LENGTH
SELECT
MHR2,
MHR4,
MHRe,
MHRs
A low-level input voltage, VIL, applied to CD (pin
6) enables the inputs to the Match-Character
Holding Register Load, MHRL. Parallel8-bit characters are input into the Match-Character Holding
Register with the MHRL Strobe (pin 34). If a character of less than 8 bits has been selected (by
WLSl and WLS2), only the least significant bits are
accepted. These inputs may be strobed or hardwired to the appropriate input voltage. A highlevel input voltage, VIL, applied to CD disables
MHR1 and MHRa.
WLS" WLS2
A low-level input voltage, VIL, applied to CD (pin 6)
enables the inputs of the Control Register Load,
CRL. Parallel 8-bit characters are input into the
Control Register with the CRL Strobe
(pin 4),
WLS, and WLS2 select the transmitted character
length from five (5) to eight (8) bits defined by the
Truth Table below:
MHR"
MHR3,
MHR5,
MHR7,
WLS2 WLSI
Selected Word Length
V1L
V 1L
5 BITS
V 1L
V 1H
6 BITS
V1H
V 1L
7 BITS
V 1H
8 BITS
V1H
WLS, and WLS2 may be strobed or hard-wired to
the appropriate input voltage. A high-level input
voltage, V 1H , applied to CD disables WLS, and
WLS2.
406
PIN
NUMBER
6
7-15
1/0 NAME
CHIP DISABLE
SYMBOL
CD
RECEIVER HOLDINGREGISTER DATA
OUTPUT
RR9-RRI
16
POWER SUPPLY
VGG
19
PARITY INHIBIT
PI
FUNCTION
This line controls the disable associated with busable inputs and Three-State outputs. A high-level
input voltage, V 1H , applied to this line disables
inputs and removes drive from push-pull output
buffers causing them to float. Drivers of disables
outputs are not required to sink or source current. The 1/0 Lines controlled by Chip Disable are
defined below:
Input Lines
Three-State Output Lines
PE
RR1-RRe
ORR
CRL
EPE
SFR
FE
MHRL
OE
PI
WLS1WLS2
MHR1-MHRe
RMSI-RMS3
A low-level input voltage, V1L, applied to CD (pin
6) enables the Receiver Holding Register outputs, RR1-RA9. The parallel data character, including parity (RR9), appears on these lines.
Program control selection of a word length less
than eight (8) bits will cause the most significant
bits of the character to be forced to a low-level
output voltage, VOL' The character will be right
justified. RRI (pin 15) is the least significant bit
of the character. A high-level input voltage, V 1H ,
applied to CD disables RR1-RR9.
- 12 Volts Supply.
A low-level input voltage, V 1L , applied to CD (pin
6) enables the EPE and PI inputs.
20
POWER SUPPLY
Voo
Ground
21
EVEN PARITY ENABLE
EPE
The Even Parity Enable Input and the Parity
Inhibit Input to the Control Register, in conjunction with the Control Register Load and Chip Disable, select even, odd or no parity to be verified by
the receiver. A high-level input voltage, VIH, applied to EPE selects even parity and a low-level
input voltage, VIL, select odd parity if a low-level
input voltage is applied to Parity Inhibit and Chip
Disable. PI and EPE may be strobed or hard-wired
to the appropriate input voltage.
PI
EPE
Selected Parity
Comments
::=
OV
V 1L
V 1L
Odd
V 1L
V 1H
Even
V 1H
X
None
NOTE: If CD ::= V1H , no programming
since inputs are disabled.
CD ::= V 1L
CD ::= V 1L
CD ::= V 1L
is performed
X - either V 1L or V 1H . When programmed, the
appropriate parity is verified following the last
data bit of a character, immediately preceding
the stop element of asynchronous and isochronous characters.
.
A high-level input voltage, V1H , applied to CD disables EPE, PI, and CRL.
29
PARITY ENABLE
PE
A high-level input V I H enables parity. A low level
input V I H disables parity.
407
PIN
NUMBER
I/O NAME
24
STATUS FLAG RESET
25
DATA RECEIVED
RESET
FUNCTION
SYMBOL
SFR
A low-level in~ voltage, V1L , applied to CD (pin 6)
enables the SFR input. A low-level input voltage,
V 1L , applied to this line resets the PE, FE and
OE Status Flags.
A low-level input voltage, V1L , applied to CD (pin
6) enables the DRR input. A lOW-level input volt-
age, V 1L , applied to this line resets the DR Flag.
A high-level input voltage, V1H , applied to CD disables DRR.
26
DATA RECEIVED
FLAG
DR
A high-level output voltage, VOH , indicates that
an entire character has been received and transferred to the Receiver Holding Register. When
operating in the synchronous mode, the first
SYN character, when located and transferred to
the Receiver Holding Register, will not cause DR
to go to a high-level output voltage, VOH , but
will cause MDET to go to a high-level output
voltage. Character transfer to the Receiver Holding Register occurs in the center of the last bit
of a synchronous character or the center of the
first STOP element of an asynchronous or isochronous character at which time this flag is
updated.
27
OVERRUN ERROR
FLAG
OE
A lOW-level input voltage, V 1L , applied to CD (pin
6) enables the OE input. A high-level output
voltage, VOH , indicates that the prevously received
character was not read (DR line not reset) and
was, therefore, lost before the present character
was transferred to the Receiver Holding Register.
This transfer occurs in the center of the last bit
of a received synchronous character or in the
center of the first STOP element of an asynchronous or isochronous character at which
time this flag is updated.
A high-level input voltage, VOH , applied to CD
disables OE.
28
FRAMING ERROR!
SYN SEARCH
FE!SS
FE!SS is a two-way (110) bus. If programmed for
the ASYNCHRONOUS or ISOCHRONOUS MODE,
a lOW-level input voltage, V 1L , applied to CD (pin
6) enables the FRAMING ERROR FLAG output
which indicates the status of the STOP BIT
detection circuit. A high-level output voltage,
VOH , indicates that the character transferred to
the Receiver Holding Register has no valid STOP
BIT; i.e., the bit following the PARITY BIT is not
a high-level input voltage, V1H . This transfer
occurs in the center of the first stop element at
which time this flag is updated.
When programmed for the SYNCHRONOUS
MODE, this line is an input and is not under
control of CD. This line should be driven by a
tri-state or an open collector device.
If programmed for INTERNAL CHARACTER
SYNCHRONIZATION, a transition from a lowlevel input voltage, V 1L , to a high-level input
voltage, V1H , initiates the automatic internal
"SYN" CHARACTER search operation.
408
PIN
NUMBER
28
I/O NAME
FRAMING ERRORI
SYN SEARCH
SYMBOL
FE/SS
FUNCTION
Prior to initiation of this operation, the Receiver
Holding Register is "transparent" so that its contents are identical to that of the RECEIVER REGISTER. Upon receipt of a SYN character, (previously loaded into the Match-Character Holding
Register during initialization), the Receiver Holding Register becomes non-transparent, the
MATCH DETECT output (MDET) goes to a highlevel output voltage. VOH ' but, the Data Received
(DR) FLAG does not assume a high-level output
voltage, VOH . The P/SAR is now in character
synchronization. Subsequent SYN or data character will be transferred to the RECEIVER HOLDING REGISTER as they are assembled (at the
center of the last bit) and the DR FLAG will be
raised. A transition from a high-level input voltage, V1H , to a low-level input voltage, V 1L , causes
the P/SAR to lose character synchronization
and forces the Receiver Holding Register to
become "transparent."
If programmed for EXTERNAL CHARACTER SYNCHRONIZATION, the system external to the
P/SAR examines the data stream for "SYN"
characters when SYN SEARCH is a low-level
input voltage, V1L • The Receiver Holding Register
is "transparent" which allows the contents of
the RECEIVER REGISTER tQ be monitored as it
ripples through the shift register. When the external logic locates a "SYN" CHARACTER, indicated by a high-level input voltage, V OH ' on
MDET, the SYN SEARCH line is externally raised
to a high-level input voltage, V 1H . This high-level
input voltage causes character synchronization
to be initiated, returns the Receiver Holding
Register to a "non-transparent" condition, causing subsequent characters to be transferred to
the RECEIVER HOLDING REGISTER (when the
center of the last bit of a character is recognized)
and raises the DR FLAG.
30
MATCH DETECT
FLAG
MDET
A high-level output voltage, VOH , indicates that
the contents of the Transmitter Register are
identical to the contents of the Match-Character
Holding Register. This flag is set to a high-level
output voltage, VOH , at the center of the first
STOP ELEMENT of an asynchronous or isochronous character.
31
RECEIVER REGISTER
CLOCK
RRC
This fifty (50) percent duty cycle clock provides
the basic receiver timing. The negative transition
from a high-level input voltage, V1H , to a low-level
input voltage, V1L , shifts data into the RECEIVER
REGISTER at a rate determined by RMS"
RMS2 and RMS3. Synchronous operation requires that this negative transition occur at
the center of each data bit.
409
PIN
NUMBER
I/O NAME
SYMBOL
FUNCTION
32
MASTER RESET
MR
A high-level input voltage, VIH , applied to this line
resets timing and control logic to an idle state,
sets the contents of the Receiver Holding Register
to a high-level output voltage, VOH , resets the
contents of the Match-Character Holding Register, the MDET, DR, PE, FE, and OE outputs to
a low-level output voltage, VOL, but does not
effect the contents of the control register.
33
CONTROL REGISTER
LOAD
CRL
A low-level inp~oltage, VIL , applied to CD (pin
6) enables the CRL input. A low-level input voltage, V IL , applied to this line enables inputs to
DC "0 Type" Latches of the Control Register
and loads it with Control Bits (EPE, PI, RMS"
RMS2, RMS3, WLS" WLS2). A high-level input
voltage, VIH , applied to this line disables the
Control Register. This line may be strobed or
hard-wired to a low-level input voltage, VIL . A highlevel input voltage, VIH , applied -to CD disables
CRL.
34
MATCH CHARACTER
HOLDING REGISTER
LOAD
MHRL
A low-level input voltage, V IL , applied to CD (pin
6) enables the MHRL input. A lOW-level input
voltage, VIL , applied to this line enables input
to DC "0 Type" Latches of the Match-Character
Holding Register and loads it with the MatchCharacter Holding Register. This line may be
strobed or hard-wired to a low-level input voltage,
VIL·
A high-level input voltage, VIH , applied to CD disables MHRL.
35
RECEIVER INPUT
RI
The serial input data stream received on this
line enters the Receiver Register determined by
the character length, parity and the number of
stop bits programmed. A high-level input voltage,
VIH , must be present when no ASYNCHRONOUS
data is being received.
receiver register to establish character synchronization.
Timing & Control - The Timing and Control Logic
generates the required control signals to assemble
characters, match comparison, bit stripping, and
generation of status/flag signals.
ORGANIZATION
PR1472 block diagram is illustrated on page 1.
Control Register - Programming of the PSAR is
accomplished by loading the 7 Bit Control register.
Mode selection, clock division, word length, and
parity are selected when the Control Register Load
(CRL) signal is activated.
SYNCHRONOUS MODE OPERATION
Receiver Register - The Receiver Register is used
to store the incoming data stream. The contents
of this register can be gated to the Holding register
during the transparent mode, or compared with
the Match Holding Register. When a character is
assembled it is transferred to the Receiver Holding Register.
Synchronous data appears as a continuous bit
stream of contiguous characters at the input to
the receiver with no Start or Stop bits. Character
synchronization (the "framing" of this continuous
bit stream into characters of a predetermined fixed
length), must be accomplished by a comparison
of this bit stream and a synchronization sequence.
The P/SAR is designed to accommodate internal
or external character synchronization by program
control.
Receiver Holding Register - The Receiver Holding
Register, a buffer register, is used to store the
assembled character.
Match Holding Register - The Match Holding
Register is used to store the match character. The
contents of this register are compared with the
Referring to the Block Diagram of the Receiver, the
Chip Disable (CD) enables or disconnects various in-
410
.
puts and outputs of the P/SAR. This feature provides the device with the capability of being disconnected from the system bus. The inputs to the
Control Register and Match-Character Hol~~~:..;:,~.:..;~>..1o.~~~..:.."'~lolo~..:...;~>..1o.~.:..;~~1,.;;.1a..;;12.....
lSJ
--I~~~~~~~
...
~
....
~
....._ _ _ _ _....@~~
...
~
....~
....~....
~
....~
....~....
~
....~.w~,__, f\~~~
~
u
*CLOCK SHOWN IS BIT RATE CLOCK (1X)
(INTERNAL SYNCHRONIZATION)
MR----1l~--------------_____________________________________
RRC ..
,,
II I I ! !
RI
I'
SS
DR
------------------'~~------------LI~
u
CD
RR 1-RRg
~~)J
I I I I I I I I I I I I I I I I I I I I I I I I I II I
l
CONTENTS OF
RECEIVER REGISTER CHARACTER
SYNCHRONIZATION
ESTABLISHED
"CLOCK SHOWN IS BIT RATE CLOCK (1X)
(EXTERNAL SYNCHRONIZATION)
SYNCHRONOUS TIMING DETAIL
412
i'
CONTENTS OF
CHARACTER
RECEIVER REGISTER
SYNCHRONIZATION
LOST
ASYCHRONOUS & ISOCHRONOUS MODE
tion rates except 1X. A low-level input voltage at
the Receiver Input at the theoretical center of the
start bit causes timing and control circuitry to
sample the theoretical center of succeeding data
bits. This data is shifted through the Receiver
Register. When an entire character (as defined by
the Control Register) is assembled in the Receiver
Register, the line is "tested" for a valid stop bit at
its theoretical center. This character is also compared with the contents of the Match-Character
Holding Register at the center of the stop bit
and its parity is verified. A parallel transfer occurs
loading the contents of the Receiver Register (Ies~
~tart and stop bits) into the Receiver Holding RegIster. The status of the parity verification, framing
error, and overrun error circuitry are also loaded
into their approriate registers to provide output
error flags when the Data Received Flag is set. If
the Data Received Flag had not been reset prior to
the assembly of the current character, the previous
character is lost and this is indicated by a high-level
output voltage on the Overrun Error Flag.
The completed assembly of a parallel character, by
the P/SAR, from a serial data stream and buffered
by its Receiver Holding Register is indicated by the
status of the Data Received (DR) Flag. The assembly
of character from a serial data stream consisting
of a start bit, data, parity (if programmed), and a
stop interval is initiated by the Start bit transition.
Verification of parity and receipt of a valid stop bit
is accomplished prior to the character transfer to
th~ Rece.iver Holding Register. Simultaneously,
this data IS compared with a preprogrammed character in the Match-Character Holding Register.
Status Flags, Data Received, Parity Error, Framing
Error, Overrun Error and Match Detect are loaded
into status registers during character transfer to
the Receiver Holding Register.
Referring to the Block Diagram of the Receiver the
Chip Disable enables or disconnects various inputs
and outputs of the P/SAR. This feature provides
the device with the capability of being disconnected
from the system bus. The inputs to the Control
Register and Match-Character Holding Re~~WL
and their respective load strobes, CAl and
are under CD control. In addition, ORR, SFR, PE,
FE, .OE and the outputs of the Receiver Holding
Register are also controlled by CD. It is necessary
that CD enable these lines to allow strobing information into these registers and to allow examination of these output data and flags.
Table 2. ASYNCHRONOUS OR ISOCHRONOUS
MODE CONTROL DEFINITION
-.-~~--"
.. ~
-"-
R W W
L
L
E
S S
S
P P
2
1
I
a a
0
0
0
1
1
1
M
3
0
0
Device operation is programmed subsequent to
being forced into its "idle" state. The P/SAR will
enter a defined "idle" state when the Master
Reset (MR) line, is strobed to a high-level input
voltage. In this state, all timing and control logic
are reset, the contents of the Receiver Holding
Flegister is set to a high-level output voltage, and
all output flags are reset to a low-level output
voltage. The Master Reset also causes the contents of the Match-Character Holding Register to
be reset to a low-level output voltage.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
~ Set
VYhen the R~ceiver is enabled by CD, loading the
Contr@eg!ster by strobing the Control Register
L.oad (CRL) line to a low-level input voltage defines
the mode of operation and clock rate selection
character length and selected parity if required'
Table 2 illustrates all the programmable asynchro:
nous formats.
Added
Start
Data
Parity
Stop
E
Bit
Bits
Bit
Elements
0 0
0 1
1 X
1
5
5
5
Odd
1
1
Even
1 or more
1 or more
1 or more
1 or more
1 or more
1
None
6
Odd
Even
1
6
1
None
6
1
Odd
7
0 0
0 1
1
7
Even
1 X
1
7
None
1
8
0 0
Odd
1
0 1
8
Even
1 X
1
None
8
to ASYNC or ISOC Mode
0 0
0 1
1 X
1 or more
1 or more
1 or more
1 or more
1 or more
1 or more
1 or more
When RMS3 is 0 (ASYNC or ISOC Mode), RMS2 and
RMS3 determine the clock frequency according to
the following table:
':' .~a~k to space transition on the receiver input
initializes the clock counter causing it to count to
the theoretical center of the start bit. At this time
the input is sampled. A high-level input voltage at
the R.e~eiver Inp~t causes the first mark to space
transition to be Interpreted as a noise spike and
resets all timing and control logic. This provides
one-half data bit, noise immunity on all clock selec-
I
•
413
RM~~S2
Clock FrequenCij
1X Baud Rate
16X Baud Rate
o
32X Baud Rate
_-'----_-----'--_-----.1_ _~64X Baud Rate
RMSl
o
"'C
J:J
......
.c.
......
MR
---Il
CRL
---u
"'C
MHRl
~
:t>
RRC*
-en
I\)
~
11121314151
RI
I IMIAffICIETl
,,
121 314151 I',
!'
U
U
U
'---__..."r-
CD
------------------.~
~~\\-~'@
RR1-RRg
OE
11
n
11
U--
DR
MDET
STOP
__
~~~~.~~~~~~~~~~~~
____
~~~~~~~~»,~~~~.~~~~.~~~~.~~~~
__
..."r----1~
____________
u---u
FE
tr
--~~~~~~~~~~~~~~~~~~----~~~~~~~~~~~~~~~~~~~~~~~~~~~----------~~
*CLOCK SHOWN IS BAUD RATE CLOCK (1X)
ASYNCHRONOUS & ISOCHRONOUS TIMING EXAMPLE
EPE. PI. WLS1. WLS2. RMS1-RMS3.
MHR1-MHR a
\--DR
PE. FE. OE
DATA INPUT LOAD CYCLE
RESET DELAY
SWITCHING WAVEFORMS
414
1. SHIFT RI INTO PROPER POSI·
TION OF RECEIVER REOISTER
8ASEDON THE SEl.ECTEO
WORDLENOTHANDPARITY
INHIBIT
2.8HIFTRI!CEIVERREOISTERTO
THE RIOHTONE BIT
3.DUPUCATECONlENTSOFRE·
CEIVER REOIBTER IN THE RE·
CEIVER HOLDINO REOl8TER
1. SHIFTRIINTOPROPERPOSI·
TION OF RECEIVER REGISTER
8ASEDON THE SELECTED
WORD LENGTH AND PARITY
INHIBIT
2. SHIFT RECEIVER REGISTER TO
THE RIOHT ONE SIT
3.DUPLICATECONTENTSOFRE·
CEIVER REGISTER IN THE RE·
CEIVER HOLDING RE(3]STER
/ARE"
JCONTENTBOF ..
..... ·RECEIVERHOLDING, ...
~?::TE~R~~~~5l~~~~ ~...
'REOIS~~/
NO
... UPDATE MDET
5. BeT DR
PR1472 SYNCHRONOUS ASYNCHRONOUS RECEIVER FLOW CHART
415
RCC
c:[J
II
:II
NOMINAL
IA
RI
NOMINAL BIT CENTER
CD
I
I
_CD___.J.&.~~":"~~~~~":"~~~";";~:":"~~~";";~:":"~~--+I.....off
PE. FE. OE
$~,-----
s"''-___ r
I
-J
I
CD
RR1- RR a
I
____--""~.:..;~..:..:..;..:..:..;..:..:..;..:..:..;..:.~~_~k=-----------___1),~'r---\---"""'---I
>,
I
--------~--------~;~
TPW -.I
I
MR
~
MIN -=1
DRR--------~,
~r-~~--I~I---------------------
~II
______________~~
~_T~d~~r------------------------------
DR
@
1.
2.
3.
4.
L
-i
A-I
\--200nS
®
DATA AND ERROR FLAGS ARE VALID ATTHE TlMENALCENTER OFTHE FIRST STOP BIT + V2 CLOCK.
DR IS DELAYED 200ns FROM DATA AND ERROR FLAGS
THE DELAY BETWEEN ORR AND DR
Td
500ns
ORR SHOULD BE HIGH A MINIMUM OF "A" ns (T d + V2 CLOCK + 200ns) PRIOR TO THE NEXT RISING EDGE OF DR.
= =
TIMING DETAIL
RRC
RRC
= 1X, 16X, 32X or64X
o
I
I
RR1·RR9
Q
~~:_.8_V________________________2-,'~'-----------------I
I
'~2.0V
----------------------------,-------'A,0.8V
I~------------I-4-TDR~
I
DR
DELAY
I
1 _ _-
_____________________________"'/2.0V
NOTES:
1. THE FALLING EDGE SHOWN REPRESENTS THE CENTER OF THE FIRST STOP BIT.
2. THE RISING EDGE SHOWN REPRESENTS THE FIRST RISING EDGE OF RRC AFTER THE CENTER OF THE FIRST STOP BIT.
Figure 1
PR1472 TIMING DETAIL
416
-
MAXIMUM RATINGS
vGG Supply Voltage
VDD Supply Voltage
Clock Input Voltage*
Logic Input Voltage*
Logic Output Voltage*
Storage Temperature Ceramic
Plastic
Operating Free-Air
Temperature TA Range
Lead Temperature
(Soldering, 10 sec)
+ 0.3V to
+ 0.3V to
+ 0.3V to
+ 0.3V to
+ 0.3V to
-
20V
20V
20V
20V
20V
-65°C to + 150°C
- 55° C to + 125° C
ELECTRICAL CHARACTERISTICS
(VSS
Vce
5V ± 5%, VDD
OV, VGG
specified.)
=
=
=
*VGG = V DD = OV
NOTE: These voltages are measured with respect to
Vss (Substrate).
= -12V
± 5%, TA
+ 50°C unless otherwise
MAX.
CONDITIONS
O.BV
VSS
= 4.75V
0.5V
VSS
IOL
VSS
IOH
= 5.25V
= 1.6mA
= 4.75V
= -100",A
VIL
VIH
PARAMETER
INPUT LOGIC LEVELS1
Low-level Input Voltage
High-level Input Voltage
VOL
OUTPUT LOGIC LEVELS2
Low-level Output Voltage
VOH
High-level Output Voltage
IlL
INPUT CURRENT1
Low-level Input Current
(each input)
-1.6mA
ILO
Output Leakage Current
10",A
SYMBOL
MIN.
= O°C to
VSS-1.5V
VSS-1.0V
=
VSS
5.25V
VIN
0.4V
=
NOTE: 1) Inputs under Chip Disable control when disabled, (VIH applied to CD), are logically disabled and
appear as a single TTL Load.
2) Outputs under Chip Disable control when disabled (V 1H applied to CD), are logically and electrically
disconnected and caused to float. The Three-State Output has three stages;
(1) Low impedance to Vee (2) Low impedance to GND (3) High impedance OFF ~ 10 Megohm.
SWITCHING CHARACTERISTICS
(VSS-VCC
5V, VDD
OV, VGG
=
SYMBOL
FC
=
= -12V, TA = 25°C, CL = 20 pf)
MIN.
PARAMETER
Clock Frequency
DC
DC
PULSE WIDTH
HoldTime
Control Register Load
Match-Character
Holding Register Load
Data Received Reset
TDRR
Status Flag Reset
TSFR
Master Reset
TMR
Output Enable Delay
TPD
RiseTime
TR
Fall Time
TF
TDR DELAY Data Ready Delay Time
MAX.
100 KHz
640 KHz
20 nsec
250 nsec
THOLD
TCRL
TMHRL
250 nsec
200 nsec
200 nsec
500 nsec
500 nsec
150 nsec
150 nsec
200 nsec
417
CONDITIONS
PR1472-00
PR1472-01
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from Its use. No license Is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
418
Printed In U S.A
WESTERN DIGITAL
COR
P
0
R
A
.r
/
0
N
PT1482 (PSAT)
Programmable Synchronous & Asynchronous Transmitter
........................................................................................................
FEATURES
GENERAL DESCRIPTION
The Western Digital PT1482 (PSAT) is a programmable transmitter that interfaces variabLe length
parallel data to a serial data channel. The transmitter converts parallel characters into a serial
data stream with a format compatible with all
standard Synchronous, Asynchronous or Isoschronous data communications media.
Contiguous serial characters are transmitted in
the Synchronous Mode with the automatic insertion of a programmable Fill (Idle) Character during
the absence of parallel input data. Programming
the
Asynchronous
Mode
selects
serial
transmission with automatic insertion of Start and
Stop Bits. Isoschronous mode selects transmission with automatic fill character insertion during
the absence of parallel input data. Four internal
registers and a multiplexer, in conjunction with
Three-State Output Lines, provide full system
versatility.
• SYNCHRONOUS, ASYNCHRONOUS OR
ISOCH RONOUS OPERATION
•
•
•
•
•
•
•
•
•
•
•
•
•
DC TO 640K BITS/SEC, 1X CLOCK PT1482-01
DC TO 100K BITS/SEC, 1X CLOCK PT1482-00
PROGRAMMABLE MATCH (FILL) CHARACTER
SELECTABLE 5,6,7, OR 8 BIT PER CHARACTER
EVEN/ODD PARITY GENERATOR. PARITY INHIBIT
PROGRAMMABLE CLOCK RATE 1X, 16X, 32X,
OR 64X.
AUTOMATIC START & STOP BIT GENERATION IN
ASYNCHRONOUS & ISOCHRONOUS MODES
PROGRAMMABLE 1 AND 2 STOP BITS, (1 V2 IN
5 LEVEL MODE)
AUTOMATIC CHARACTER STATUS AND DELIMITING SIGNAL GENERATION
THREE STATE OUTPUTS - BUS STRUCTURE
COMPATIBILITY
DOUBLE BUFFERED
TTL AND DTL COMPATIBLE
INTERNAL
ACTIVE PULL UP
COMPATIBLE RECEIVER, PR1472.
The PSAT is a TTL compatible device. The use of
internal active pull-up devices and push-pull
output drivers, provides direct compatibility with
all forms of current sinking logic. Western Digital
also offers a compatible Receiver, PR1472.
PIN CONNECTIONS
PT1482 BLOCK DIAGRAM
419
PIN OUTS
PIN
NUMBER
1/0 NAME
2
Vss POWER SUPPLY
EVEN PARITY ENABLE
Vss
EPE
3
PARITY INHIBIT
PI
1
FUNCTION
SYMBOL
+ 5 Volt Supply
A low-level input voltage, V'L, applied to CD (pin
22) enables the EPE and PI Inputs.
The Even Parity Enable Input and the Parity
Inhibit Input to the Control Register, in conjunction with the Control Register Load and Chip
- Disable, select even, odd or no parity to be
generated by the Transmitter. A high-level input
voltage, V'H, applied to EPE selects even parity
and a low-level input voltage, V'L, selects odd
parity if a low-level input voltage is applied to
Parity Inhibit and Chip Disable.
PI
V'L
V'L
V'H
EPE
V'L
V'H
X
SELECTED PARITY COMMENTS
ODD
CD = V1L
EVEN
CD
V'L
NONE
CD = V'L
=
NOTE: IF CD = V'H, NO PROGRAMMING IS
PERFORMED SINCE INPUTS ARE DISABLED.
X - either V'L or V1H
When programmed, the
appropriate parity is generated following, and is
contiguous with, the last data bit of a character,
immediately preceding the stop element of asychronous and isochronous characters.
A high-level input vo~e, V'H, applied to CD
disables EPE, PI, and CRL
4
CONTROL REGISTER
LOAD
CRL
A low-level input voltage, V'L, applied to CD (pin
22) enables the CRL input.
A low-level input voltage, V'L, applied to this
line enables DC Latches of the Control Register
and loads it with Control Bits (EPE, PI, CS 1 , CS 2 ,
MS h MS 2 , WLS 1, WLS 2). A high-level input
voltage, V'H, applied to this line disables the
Control Register. This line may be strobed or
hard-wired to a lOW-level input voltage, V 1L . A
high-level input voltage, V'H, applied to CD,
disables CAl.
5
6-7
TRANSMITTER
REGISTER CLOCK
TRC
This is a fifty (50) percent duty cycle clock. The
positive going edge of this Clock shifts data out
of the Transmitter Register at a rate determined
by the Control Bits CS 1 and CS 2 , and provides
the basic time reference for all device functions.
CLOCK RATE SELECT
CS 1-CS 2
A low-level input voltage, V'L. applied to CD
enables the CS 1 and CS 2 inputs. These two
lines select the internal clock rate divider ratio
to produce the transmitter bit rate defined by
the Truth Table below:
CS 1 SELECTED CLOCK INPUT RATE
CS 2
V'L
V'L
1X BIT RATE
V'L
V'H
16X BIT RATE
V'H
V'L
32X BIT RATE
V'H
V 1H
64X BIT RATE
420
PIN
NUMBER
1/0 NAME
SYMBOL
FUNCTION
A high-level input voltage, V 1H , applied to CD
disables CS 1 and CS 2 •
MODE SELECT
8-9
MS 1-MS 2
These lines may be strobed or hard-wired to the
appropriate input voltage.
A low-level input voltage, V 1L, applied to CD (pin
22) enables the MS 1 and MS 2 inputs. These
lines select the transmitter operating mode.
MS2 MS 1
MODE
V 1L V1L ASYNCHRONOUS - ONE STOP BIT
V1L * V1H*ASYNCHRONOUS - TWO STOP BITS
V1H V 1L SYNCHRONOUS
V 1H V 1H ISOCHRONOUS
*Selects 1.5 stop bits for 5-level codes.
I
A high-level input voltage, V1H , applied to CD
disables MS 1 and MS 2 •
I
10
DATA NOT AVAILABLE
RESET
DAR
A low-level input voltage, V1L, applied to CD (pin
22) enables the DAR input. A low-level input
voltage, V1L, applied to this line resets the Data
Not Available Flag. A [)~~r-Ievel Input, V1H ,
applied to CD disables
. This input is not
used during asynchronous operation.
11
TRANSMITTER
CLOCK OUTPUT
TCO
This output is a clock at the transmitted bit rate.
The negative going edge of this clock corresponds to the center of each transmitted data
bit. The positive going edge corresponds to the
start of each data bit transmission. All waveforms in this specification are referenced to
TCO.
12
DATA NOT AVAILABLE
FLAG
DA
A low-level input voltage, V1L, applied to CD (pin
22) enables the DA input. A high-level output
voltage, VOH , on this line indicates that a FillCharacter has been transmitted, since a character was not loaded into the Transmitter Holding
Register by the center of the last bit of a Synchronous Character or the center of the Stop
Element of an Isochronous character. A highlevel input voltage, V 1H , applied to CD disables
DA. This input is not used during asynchronous
operation.
13
DATA DELIMITI
END OF CHARACTER
DD/EOC
During asynchronous operation, a high-level
output voltage, VOH , indicates data is being
transmitted. A low-level output voltage, VOL,
indicates that a Start or Stop Element is being
transmitted.
A low-level output voltage during synchronous
operation indicates that the last bit of a character is being transmitted.
421
."
-I
.....
&
-en
I\)
."
E;
PIN
NUMBEFi
1/0 NAME
SYMBOL
FUNCTION
14
TRANSMITTER
HOLDING REGISTER
EMPTY
THRE
15
TRANSMITTER
REGISTER OUTPUT
TRO
16
VGG POWER SUPPLY
17
CLEAR-TO-SEN 0
CTS
The Clear-To-Send Control initiates or disables
transmission as a function of the state of this
line. A high-level input voltage, V1H , initiates
serial data transmission provided a character
has been loaded into the Transmitter Holding
Register. A low-level input voltage, V1L, applied
to this line during transmission allows completion of that character only, after which the
output will continue to mark until a high-level
input voltage is applied.
18
MASTER RESET
MR
The rising edge of a high-level input voltage,
V1H , applied to this line resets timing and
control logic to an idle state, sets THRE, the
contents of the Fill-Character Holding Register,
and TRO to a high-level output voltage, VOH .
19
TRANSMITTER
HOLDING REGISTER
20
A low-level input voltage applied to GO (pin 22)
enables the THRE input. A high-level output
voltage, VOH , on this line indicates the Trans. mitter Holding Register is empty and has transferred its contents to the Transmitter Register
and may be loaded with a new character. This
line goes to a low-level output voltage, VOL,
when THRL goes to a low-level input voltage,
V 1L. A high-level input voltage, V 1H , applied to
CD disables THRE.
The contents of the Transmitter Holding
Register are serially shifted out as an NRZ
waveform on this line provided that a character
was loaded into the Transmitter Holding Register prior to OA Flag (in Synchronous or Isochronous Modes). If a character was not loaded
prior to a OA Flag, the contents of the FillCharacter Register are transmitted as the next
character.
- 12 Volts Supply.
A low-level input voltage, V1L, applied to CD (pin
22) enables the THRL input. A low-level input
C6A5
voltage, V1L, applied to this line enables DC
Latches of the Transmitter Holding Register
and loads it with the Transmitter Holding
Register data and forces THRE to a lOW-level
output voltage, VOL. A high-level input voltage,
V1H , applied to this line disables the Transmitter
Holding Register. A high-level input voltage,
V1H , applied to CD disables THRL.
FI LL-CHARACTER
HOLDING REGISTER
LOAD
A low-level input voltage, V1L, applied to CD (pin
FHm. input. A lOW-level input
voltage, V1L, applied to this line enables DC
Latches of the Fill-Character Holding Register
and loads it with the Fill-Character Register
data FR 1-FR a. A high-level input voltage, V 1H ,
applied to this line disables the FHRL Register.
This line may be strobed or hard-wired to a low22) enables the
422
PIN
NUMBER
"0 NAME
FUNCTION
SYMBOL
level input voltage, V'L. This input is not used
during asynchronous operation.
A high-level input voltage, V'H, applied to CD
disables FHRL.
21
Voo POWER SUPPLY
Voo
Ground.
22
CHIP DISABLE
CD
This line controls the disconnect associated
with busable inputs and Three-State outputs. A
high-level input voltage, V'H, applied to this line
removes drive from push-pull outputs causing
them to float. Drivers of disabled inputs are
required to sink or source current. The 110 Lines
controlled by Chip Disable are defined below:
INPUT LINES
TRI-STATE OUTPUT LINES
CRL
TI-IRL
DA
EPE
FHRL
THRE
PI
FR1-FRa
CS 1-CS 2 TR,-TR s
MS 1-MS 2 WLS,WLS2
DAR
23,25
27,29
31,33
35,37
FI LL-CHARACTER
HOLDING REGISTER
DATA INPUTS
A low-level input voltage, V'L, applied to CD (pin
22) enables the inputs of the Fill-Character
Holding Register and associat~d Load Strobe,
FHRL. Parallel 8-bit characters are input into
the Fill-Character Holding Register with the
FHRL Strobe (pin 20). If a character of less than
8 bits has been selected (by WLS 1 and WLS 2)
only the least significant bits are accepted.
These lines may be strobed or hard-wired to the
appropriate input voltage. These inputs are not
used during asynchronous operation.
During Synchronous or Isochronous transmission, the Fill-Character is transmitted if a character was not loaded into the Transmitter Holding Register prior to a DA Flag; i.e., the Transmitter Holding Register did not contain a
character at the center of the last bit being
transmitted from the Transmitter Register. A
high-level input voltage, V'H, will cause a highlevel output voltage, VOH , to be transmitted,
Least Significant Bit (FR 1) to Most Significant
Bit (FRn) order.
A high-level input voltage, V'H, applied to CD
disables FR 1-FR a.
24,26
28,30
32,34
36,38
TRANSM ITTER
HOLDING REGISTER
DATA INPUTS
A low-level input voltage, V'L, applied to CD (pin
22) enables the inputs to the Transmitter Hold-
!..!:!.LRegister
and associated Load Strobe,
THRL If a character of less than 8 bits has been
selected (by WLS 1 and WLS 2), only the least
significant bits are accepted. A high-level input
423
PIN
NUMBER
I/O NAME
FUNCTION
SYMBOL
voltage, VIH , will cause a high-level output
voltage to be transmitted, Least Significant Bit
(TR 1) to Most Significant Bit (TRn) order. A highlevel input voltage, V 1H , applied to CD disables
TR 1-TR a·
39-40
WORD LENGTH
WLS 1-WLS2
A low-level input voltage, VIL, applied to CD (pin
22) enables the inputs of the Control Register
and Load, CRL. Parallel a-bit characters are
input into the Control Register with the CRL
Strobe (pin 4), WLS 1 and WLS 2 select the transmitted character length from five (5) to eight (8)
bits defined by the Truth Table below:
WLS 2
V1L
VIL
VIH
VIH
WLS 1
V1L
V1H
V1L
VIH
SELECTED WORD LENGTH
5 BITS
6 BITS
7 BITS
8 BITS
A high-level input voltage, VIH • applied to CD
disables WLS 1 and WLS 2 , forcing them to float.
(programmably variable from 5 to 8 data bits plus
parity) are contiguous with no start or stop bits.
Since the requirement that characters are contiuous does not imply that the system servicing the
transmitter always has ample time to load the
Transmitter Holding Register, it is necessary that
a character be transmitted when data has not
been loaded into the Transmitter Holding Register.
This character is defined as the Fill or Idle Character and a separate register has been provided to
load this character upon initialization. The FillCharacter Holding Register is loaded by strobing
the Fill-Character Holding Register Load (FHRL)
line or hard-wiring it to a low-level input voltage.
ORGANIZATION
PT1482 block diagram is illustrated on page 1.
Control Register - Programming of the PSAT is
accomplished by loading the 8 Bit Control Register.
Mode selection, clock divisor, word length, and
parity are selected when the Control Register
Load signal is activated.
Transmitter Register - The Transmitter Register
is used to store the outgoing data stream. The
contents of this register are derived from either
the Transmitter Holding Register or the Fill
(Match) Character Holding Register with the
Control and Timing Logic automatically adding
the required start and stop bits during Asynchronous and Isoschronous Modes.
Transmitter Holding Register - The Transmitter
Holding Register, a buffer register, is used to
store the parallel character to be serially transmitted.
Fill Character Holding Register - The Fill Character Holding Register is used to store the Fill
(Match) Character which is transmitted during the
absence of characters in the Transmitter Holding
Register.
Timing and Control - The Timing and Control
Logic generates the required control signals to
transmit Data and Fill Characters. Character transmission status signals are also derived from this
logic.
Referring the Block Diagram of the Transmitter, it
can be seen that the Chip Disable (CD) enables or
disconnects various inputs and outputs of the
P/SAT. The inputs to the Control Register, Transmitter Holding Register, Fill-Character Holding
~HWLter and their respective load strobes, CRL,
, and F'RlfL are under CD control. In addition, the Transmitter Holding ~gister Empty
(THRE) Flag, Data Not Available (DA) Flag, and the
Data Not Available Reset (DAR) are also controlled
by CD. It is necessary that CD enable these lines
to allow strobing information into these registers
and to allow examination of these output flags.
The P/SAT will enter a defined "idle" state when
the Master Reset (MR) is strobed to a high-level
input voltage. In this state, all timing and control
logic are reset, the Transmitter Register Output
continues to mark, the Transmitter Holding
Register Flag is set to a high-level output voltage,
the Data Delimit/End of Character (DD/EOC) Flag
SYNCHRONOUS MODE OPERATION
Synchronous transmission requires that characters
424
is set to a low-level output voltage, and the
c()ntents of the Fill-Character Holding Register
are forced to a high-level output voltage.
Table 1. SYNC MODE CONTROL DEFINITION
CONTROL WORD
CHARACTER FORMAT
WW
When the P/SAT is enab~ed by CD, loading the
Control Register by strobing the Control Register,
Load (CRL) line to a low-level input voltage,
defines the mode of operation, character length,
selected parity if required, and the clock rate
selection. Table 1 illustrates a" the programmable
synchronous character formats.
M
M
L
L
S
S
S
S
P
P
DATA
PARITY
2
1
2
1
I
E
BITS
BIT
1
0
0
0
1
0
1
X
0
0
1
0
0
0
0
0
0
0
5
5
5
6
6
6
ODD
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
7
ODD
1
1
To initialize transmission the CTS signal must be
SE~t to a high state and the transmitter holding
register must be loaded with a character to be
transmitted. The transmitter wi" remain in an idle
state until this is accomplished.
1
1
Tine character transferred into the Transmitter
Register (from the Transmitter Holding Register or
the Fi"-Character Holding Register) is determined
at the center of the last bit of the character being
transmitted. If, at this time, no character has been
loaded into the Transmitter Holding Register, the
Fi"-Character is loaded 'into the Transmitter
Register at the end of the bit being transmitted
1
1
1
1
1
0
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
1
1
1
1
ADDED
E
1
1
X
0
1
EVEN
NONE
ODD
EVEN
NONE
1
7
EVEN
X
0
7
NONE
8
8
8
ODD
1
X
EVEN
NONE
t
Sets to SYNC Mode
TCO
MR
JlL________________________________________________________
CD
TR 1·TR S
r---1L_________________________________________________
::x=:::x_________________--.JX'-_________--y.--J'-------------------u
CTS
U
--.J
TRO
DD/EOC ____---'
u
u
u
'CLOCK SHOWN IS BIT RATE CLOCK (1X)
u
NOTE:
~ ~~6~~I~SG
PI = V 1L
MS 1 = V 1L
MS 2 = V 1H
WLS 1 = V 1H
WLS 2 ;" V 1H
SYNCHRONOUS TIMING EXAMPLE
•
425
and a Data Not Available (DA) Flag is set to a highlevel output voltage. This Fill-Character will be
repeatedly transmitted until a character is loaded
into the Transmitter Holding Register, at which
time, the Data Not Available Flag is reset, the FillCharacter will be completed and the newly loaded
synchronous character will follow contiguously.
Referring to the Block Diagram of the Transmitter,
it can be seen that the Chip Disable enables or
disconnects various inputs and outputs of the
P/SAT. The inputs to the Control Register, Transmitter Holding Register, Fill-Character Holding
Register and their respective load strobes, CRL,
THRL and FHRL are under CD control. In addition,
the Transmitter Holding Register Empty Flag
(THRE), the Data Not Available Flag (DA), and the
Data Not Available Reset (DAR) are also controlled
by CD. It is necessary that CD enable these lines
to allow strobing information into these registers
and to allow examination of these output flags. It
should be noted that the Fill-Character Holding
Register and its associated load strobe,
the Data Not Available Flag and its associated
reset, DAR, play no role in asynchronous communications and are only mentioned here for
completeness.
A high-level output voltage, on the THRE Flag
indicates that the Transmitter Holding Register is
empty and may be loaded with a character. Data
on the inputs of the Transmitter Holding Register
is loaded when the Transmitter Holding Register
Load (THRL) line is strobed to a low-level input
voltage, forcing the THRE Flag to a low-level
ouWt voltage. This data must be stable prior to
TH
going to a high-level input voltage since this
register is a set of DC latches which are enabled
byTRRL.
rnm.,
If the Clear-To-Send (CTS) line is at a low-level
input voltage, or if the Transmitter Register is in
the process of transmitting a character, the
character in the Transmitter Holding Register will
not be transferred down to the Transmitter Register and the THRE Flag will remain at a low-level
output voltage. Raising the CTS line to a high-level
input voltage or completion of transmission of a
character from the Transmitter Register causes
the automatic transfer of the character in the
Transmitter Holding Register to the Transmitter
Register which forces the THRE Flag to be set to
high-level output voltage. The selected parity is
added to the data during the transfer to the Transmitter Register and serial transmission is initiated
as an NRZ waveform. A low-level input voltage
applied to CTS during transmission allows
completion of that character only, after which the
device enters the idle state and the output will
continue to mark until a high-level input voltage is
applied.
The P/SAT will enter a defined "idle" state when
the Master Reset (MR) line is strobed to a highlevel input voltage. In this state, all timing and
control logic are reset, the Transmitter Register
Output continues to mark, the Transmitter
Holding Register Empty Flag is set to a high-level
output voltage, VOH , and the Data Delimit/End of
Character (DD/EOC) Flag is reset to a lOW-level
output voltage.
When the transmitter is enabled by CD, loading
the Control Re~er by strobing the Control
Register Load (CRl) line to a low-level input
voltage, V1L , defines the mode of operation,
character length, selected parity if required and
the clock rate selection. Table 2 illustrates all the
programmable asynchronous formats.
Continuous transmission, transmission of characters with the minimum number of stop bits programmed, is accomplished by loading the
Transmitter Holding Register within a character
time of when its "Empty Flag" becomes a highlevel output voltage. A high-level output voltage,
VOH , on the Transmitter Holding Register Empty
(THRE) Flag indicates that the Transmitter Holding Register is empty and may be loaded with a
character. Data on the inputs of the Transmitter
Holding Register is loaded when the Transmitter
Holding Register Load (THRL) line is strobed to a
low-level input voltage, V1L , forcing the THRE Flag
to a low-level output voltage, VOL' This data must
be stable prior to THRL going to a high-level input
voltage since this register is a set of DC latches
which are enabled by THRL. If the Clear-To-Send
(CTS) line is at a low-level input voltage or if the
Transmitter Register is in the process of transmitting a character, the character in the Transmitter
Holding Register will not be transferred down to
the Transmitter Register and the THRE Flag will
remain at a low-level output voltage. RaiSing the
CTS line to a high-level input voltage or comple-
The Data Delimit/End of Character Flag has been
provided to indicate the transmission of serial
data on the Transmitter Register Output. The Data
Delimit/End of Character Flag is defined as a lowlevel output voltage during transmission of the
last bit of a synchronous character and when the
.P/SAT is in the "idle" state.
ASYNCHRONOUS MODE OPERATION
An asynchronous character consisting of a start
bit, followed by data (programmably variable from
5 to 8 data bits), parity (if so programmed), and a
stop "element" is serially transmitted, in that
order, as an NRZ waveform by the P/SAT. The stop
interval is referred to as an "element" since its
minimum length is under program control and
may be 1 or 2 bits in length. When programmed for
2 stop bits, a 5-level (bit) code will be transmitted
with 1.5 stop bits.
426
tion of transmission of a character from the Transmitter Register causes the automatic transfer of
the character in the Transmitter Holding Register
to the Transmitter Register and the THRE flag will
be set to a high-level output voltage.
addition of a start and a single stop bit added to
each character.
Table 2. ASYNC MODE CONTROL DEFINITION
CHARACTER FORMAT
CONTROL WORD
WW
M M L L
E
S S S S P P
2 1 2 1 I E
The start bit, selected parity and stop bit(s), determined by the Control Register programming, are
added to the data during the transfer to the Transmitter Register and serial transmission is initiated
as an N RZ waveform.
A low-level input voltage, applied to CTS during
transmission, allows completion of that character
only, after which the output will continue to mark
until a high-level input voltage is applied.
The Data Delimit/End of Character Flag has been
provided to indicate the transmission of serial
data on the Transmitter Register Output. Data
Delimit is a low-level output voltage during start
and stop bits and is a high-level output voltage
during transmission of data and parity. Neither
TRO, CTS nor DD/EOC is under control of Chip
Disable.
START
BIT
DATA
BITS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
5
5
5
5
0 o 0 000
o 1 000 0
00000 1
o 1 0 00 1
o 000 1 X
o10 0 1X
000 1 0 0
o10 10 0
000 1 0 1
o10 10 1
000 1 1 X
o10 1 1X
001 000
o 1 1 000
00100 1
011001
00101 X
01101X
001 100
011100
001101
011101
00111X
01111X
ISOCHRONOUS MODE OPERATION
In the Isochronous Mode of operation all (Synchronous Mode) definitions apply with the exception of those for the Data Delimit/End of Character
(DD/EOC) Flag and the Data Not Available Flag
(DA).
•
This is the case since Isochronous Data Transmission requires contiguous characters with the
1
1
1
1
6
6
6
6
6
6
7
7
7
7
7
7
8
8
8
8
8
8
ADDED
PARITY
BIT
STOP
ELEMENTS
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
ODD
ODD
EVEN
EVEN
NONE
NONE
1
1.5
1
1.5
1
1.5
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
Sets to ASYNC Mode
TCO'
MR
CD
11
---,
XL -_ _ _ _
TR 1 • TRB
THRL
~X~
________________
x:::::x~
u--u
U
U
_______________________
CTS
THRE
TRO
~
.J
~
___
r1~
______________
11 121 314151 6171 P I
~n
STOP
Uilll314 1516171 p I I 11 1213141516171 pi
LJ
DD/EOC
'CLOCK SHOWN IS BAUD RATE CLOCK (1X)
~OUTPUTS
NOTE: ~ FLOATING
PI = V 1L
MS 1
V1L
MS 2
V1L
WLS 1 = V 1L
WLS 2 = V 1H
=
=
ASYNCHRONOUS TIMING EXAMPLE
427
....~
~
-~
-a
.::t
The Data Delimit/End of Character Flag is a low·
level output voltage during start and stop bits and
is a high·level output voltage during transmission
of data and parity. The Data Not Available Flag
(DA) is set to a high·level output voltage at the end
of the stop bit if a character has not been loaded
into the Transmitter Holding Register at the
center of the stop bit. The contents of the Fill·
Character Holding Register will be transferred
into the Transmitter Register and repeatedly
transmitted until a character is loaded into the
Transmitter Holding Register. At this time, the
Fill·Character will be completed and the newly
loaded isochronous character will follow contigu·
ously.
Table 3. ISOC MODE CONTROL DEFINITION
CHARACTER FORMAT
CONTROL WORD
WW
M M L L
E
S S SSP P
2 1 2 1 I E
1
1
1
1
1
1
1
1
1
1
1
1
Table 3 illustrates all the programmable isochron·
ous character formats.
1
1
1
1
1
1
1
1
1
1
1
1
o
o
o
o
o
0 0 0
000 1
0 1 X
1 0 0
1 0 1
1 1 X
1 000
100 1
101 X
1 100
1 1 0 1
1 1 1 X
+ to ISOC Moqe
Sets
START
BIT
DATA
BITS
1
1
1
1
1
1
1
1
1
1
1
1
5
5
5
6
6
6
7
7
7
8
8
8
ADDED
PARITY
BIT
STOP
ELEMENTS
ODD
EVEN
NONE
ODD
EVEN
NONE
ODD
EVEN
NONE
ODD
EVEN
NONE
1
1
1
1
1
1
1
1
1
1
1
1
TCO'
MR
jl~---------------------------------------------------------------------------------------------------------
____
~r---l~
_______________________________________________
CD
TR,-TRe
=:::x:::::::x__________>C_____
x'-___________
---J
u
'------~.----
CTS
L-_______~rI~:--------------~r-L--
TRO
DD/EOC
LJ
LJ
~OUTPUTS
NOTE: ~ FLOATING
• CLOCK SHOWN IS BIT RATE CLOCK (1 X)
PI = V 1L
MS, = V1H
MS 2 = V 1H
WLS, = V1H
WLS2 = V1H
ISOCHRONOUS TIMING EXAMPLE
428
EPE, PI, CS 1, CS 2, MS 1, MS 2, WLS 1, WLS2
TR1" TR a
FR1" FR a
CRL
THRL
FHRL
CD
ALL THREE-STATE
V 1H
----
- - - - - -- - - -
OUTPUT LINES
DATA INPUT LOAD CYCLE
OUTPUT ENABLE DELAYS
SKEW TIMES
SWITCHING WAVEFORMS
429
2. PULSE MASTER flESET
3. SELECT CONTROL 81TI
4. SET CHIP Dl8A8LE ",VIL
5. PULSI! CONTRO'.REOI8TER LO .... O
45.SElECT8AUOI=ATE-ClK
PT1482 SYNCHRONOUS ASYNCHRONOUS TRANSMITTER FLOW CHART
430
TCO
CD
>500ns
r-
CTS
L-+-___
THRE
TRO
>
\
TIMING DETAIL
•
431
~
__ .1
500ns
500ns
ABSOLUTE,MAXIMUM RATINGS
+ 0.3V to
+ 0.3V to
+ 0.3V to
+ 0.3V to
+ 0.3V to
VGG Supply Voltage
V DD Supply Voltage
Clock Input Voltage*
Logic Input Voltage*
Logic Output Voltage*
Storage Temperature
Ceramic
Plastic
Operating Free-Air Temperature T A Range
Lead Temperature (Soldering, 10 sec.)
- 20V
- 20V
- 20V
- 20V
- 20V
-165° C to +150° C
-55°C to +125°C
O°C to + 50°C
300°C
=
=
·VGG
VDD
OV
NOTE: These voltages are measured
with respect to V ss (Substrate)
ELECTRICAL CHARACTERISTICS
(VSS = VCC = 5V ± 5%, VOD = OV, VGG = -12V ± 5%, TA = O°C to + 50°C
unless otherwise specified)
SYMBOL
MIN.
PARAMETER
VIL
VIH
INPUT LOGIC LEVELS1
Low-level Input Voltage
High-level Input Voltage
VOL
OUTPUT LOGIC LEVELS2
Low-level Output Voltage
VOH
High-level Output Voltage
IlL
INPUT CURRENT Low-level Input Current
(each input)
ILO
Output Leakage CurrenP
MAX.
CONDITIONS
O.BV
VSS = 4.75V
0.5V
VSS =
IOL =
VSS =
IOH =
VSS-1.5V
VSS-1.0V
-1.6mA
5.25V
-1.6mA
4.75V
- 1OOIi A
VSS = 5.25V
VIN = O.4V
10liA
•• Not more than one output should be shorted at a time.
NOTES: 1) Inputs under Chip Disable control when disabled (VIH applied to CD), are logically disabled and
appear as a single TTL load.
2) Outputs under Chip Disable control when disabled (V 1H applied to CD) are logically and electrically disconnected and caused to float.
3) All switching characteristics are measured at O.BV and 2.OV.
SWITCHING CHARACTERISTICS
(VSS = VCC = 5V ± 5%, VDD = OV, VGG = -12V ± 5%, TA = O°C to + 50°C, CL = 20pf)
SYMBOL
MIN,
PARAMETER
Fc
Clock Frequency
THOLD
TCRL
TTHRL
T FHRL
TOAR
TMR
T PO
TSKEW
TR
TF
PULSE WIDTH
HoldTime
Control Register Load
Transmitter Holding Register Load
Fill-Character Holding RegisterLoad
Data Not Available Reset
Master Reset
Output Enable Delay
Skew Time
RiseTime
Fall Time
DC
DC
See page 725 for ordering information.
432
MAX.
100 KHz
640 KHz
20 nsec
250 nsec
250 nsec
250 nsec
200 nsec
500 nsec
500
250
150
150
nsec
nsec
nsec
nsec
CONDITIONS
1482B-OO
14828-01
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
UC1671 ASTRO
FEATURES
8 SELECTABLE CLOCK RATES
• Accepts 1X Clock and Up to 4 Different 32X
Baud Rate Clock Inputs
• Up to 47% Distortion Allowance with
32X Clock
SYNCHRONOUS AND ASYNCHRONOUS
• Full Duplex Operations
SYNCHRONOUS MODE
• Selectable 5-8 Bit Characters
• Two Successive SYN Characters Sets
Synchron ization
• Programmable SYN and OLE Character
Stripping
• Programmable SYN and DLE-SYN Fill
ASYNCHRONOUS MODE
• Selectable 5-8 Bit Characters
• Line Break Detection and Generation
• 1-, 1V2-, or 2-Stop Bit Selection
• False Start Bit Detection Automatic Serial
Echo Mode
SYSTEM COMPATIBILITY
• Double Buffering of Data
• 8-Bit Bi-Directional Bus For Data, Status,
and Control Words
• All Inputs and Outputs TTL Compatible
• Up to 32 ASTROS Can Be Addressed On Bus
• On-Line Diagnostic Capability
TRANSMISSION ERROR DETECTION-PARITY
• Overrun and Framing
BAUD RATE -
APPLICATIONS
SYNCHRONOUS COMMUNICATIONS
ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL COMMUNICATIONS
GENERAL DESCRIPTION
The UC1671 (ASTRO) is a MOS/LSI device which
performs the functions of interfacing a serial data
communication channel to a parallel digital system.
The device is capable of full duplex communications
(receiving and transmitting) with synchronous or
asynchronous systems. The ASTRO is designed to
operate on a multiplexed bus with other bus-oriented
devices. Its operation is programmed by a processor
or controller via the bus and all parallel data transfers
with these machines are accomplished over the bus
lines.
The ASTRO is fabricated in n-channel silicon gate
MOS technology and is TTL compatible on all inputs
and outputs.
DC TO 1M BIT/SEC
40
(-5V) VBB
voo (+12V)
FiE
iAcKi
Os
WE
'ii\CKo
RPIY
iNTR
lXIiC
RTs(CA)
IXTC
ToATA(BA)
R4
CTs(CB)
35
R2
iXRc(oO)
R1
6ALo
R4
i5A[i'
R3
i5AL2
i5AC3
i5AL.4
R2
R1
om
28
R3
iXi'C (DB)
CARR (CF)
DsR (CC)
~
~
DAti
i5AL7
oTR(Co)
16
IDs
107
R'i'NG (CE)
MIsC
Wi
22
iD8
(GNo)VSS
ROArA
PIN CONNECTIONS
UC1671 BLOCK DIAGRAM
433
c:
(")
...&.
~
...&.
plemented to allow for an inversion when converting
to EIA RS232C levels. The names and symbols
assigned to the Data Set interface signals follows
EIA standard nomenclature.
A bar over a signal (SIGNAL), means active low (set
= low).
PIN OUTS
The device is packaged in a 40-pin plastic or ceramic
cavity package. The interface signals are defined
below with all input/output signals complemented to
facilitate bussing and interfacing with TTL. The Data
Set controls and Status signals are also comPIN
NUMBER
1
21
40
20
23
8-15
PIN NAME
POWER SUPPLIES
SYMBOL
MASTER RESET
VBB
VCC
VDD
VSS
MR
DATA ACCESS LINES
DALO-DAL7
17,22,24, SELECT CODE
25,26
3
CHIP SELECT
39
READ ENABLE
4
WRITE ENABLE
7
INTERRUPT
2
INTERRUPT
ACKNOWLEDGE IN
5
INTERRUPT
ACKNOWLEDGE OUT
6
REPLY
30-33
37
IACKO
CLOCK RATES
R1-R4
TRANSMITTED DATA
TDATA
(BA)
42i4
FUNCTION
-5V
+5V
+ 12V
Ground
The Control and Status Registers and other
controls are cleared when this input is low.
Eight-b!t bi-directional bus used for transfer of
data, control, status, and address information.
Five input pins which when hard-wired assign the
device a unique identification code used to select
the device when addressing and used as an identification when responding to interrupts.
The low logic transition of CS identifies a valid
address on the DAL bus during Read and Write
operations.
This signal, when low, gates the contents of an
addressed register from a selected ASTRO onto
the DAL bus.
This signal, when low, gates the contents of the
DAL bus into the addressed register of a selected
ASTRO.
This open drain output is made low when one of
the communication interrupt conditions occur.
This input becomes low when polling takes place
on the bus by the Controller to determine the
interrupting source. When this signal is received,
the ASTRO places its 10 code on the DAL if it is
requesting interrupt, otherwise it makes IACKO a
low.
This output is made a logic low in response to a
low IACKI if the ASTRO receiving an IACKI input
is not the interrupting device.
This open drain output is made low when the
ASTRO is responding to being selected by an
address on the DAL during read or write operations or in affirming that it is the interrupting
source during interrupt polling.
These four inputs accept four different local 32X
data rate Transmit and Receive clocks. The input
on R4 may be divided down into a 32X clock from a
32X, 64X, 128X, or 256X clock input. The clock
used in the ASTRO is selected by the Control
Register.
This output is the transmitted serial data from the
ASTRO. This output is held in a Marking condition
when the transmitter section is not enabled.
PIN
NUMBER
PIN NAME
27
RECEIVED DATA
38
REQUEST TO SEND
36
CLEAR TO SEND
28
DATA SET READY
SYMBOL
RDATA
(BB)
RTS
(CA)
CTS
(CB)
DSR
(CC)
16
DATA TERMINAL READY DTR
18
RING INDICATOR
RING
(CE)
29
CARRIER DETECTOR
CARR
(CF)
35
TRANSMITTER TIMING
IXTC
(DB)
34
RECEIVER TIMING
IXAC
(DO)
19
M ISCELLAN EOUS
MISC
(rn5)
FUNCTION
This input receives serial data into the ASTRO.
This output is enabled by the Control Register and
remains in a low state during transmitted data
from the ASTRO.
This input, when low, enables the transmitter
section of the ASTRO.
This input generates an interrupt when going On
or Off while the Data Terminal Ready signal is On.
It appears as a bit in the Status Register.
This output is generated by a bit in the Control
Register and indicates Controller readiness.
This input from the Data Set generates an interrupt when made low with Data Terminal Ready in
the "Off" condition.
This input from the Data Set generates an interrupt when going On or Off if Data Terminal Ready
is On. It appears as a bit in the Status Register.
This input is the Transmitter 1?( Data Rate Clock.
Its use is selected by the Control Register. The
transmitted data changes on the negative transition of this signal.
This input is the Receiver 1X Data Rate Clock. Its
use is selected by the Control Register. The
Received Data is sampled by the ASTRO on the
positive transition of this signal.
This output is controlled by a bit in the Control
Register and is used as an extra programmable
signal.
RECEIVER REGISTER - This 8-bit shift register
inputs the received data at a clock rate determined by
the Control Register. The incoming data is assembled to the selected character length and then
transferred to the Receiver Holding Register with
logic zeroes filling out any unused high-order bit
positions.
SYN REGISTER - This 8-bit register is loaded from
the DAL lines by a Write operation and holds the
synchronization code used to establish receiver
character synchronization. It serves as a fill character
when no new data is available in the Transmitter
Holding Register during transmission. This register
cannot be read onto the DAL lines. It must be loaded
with logic zeroes in all unused high-order bits.
OLE REGISTER - This 8-bit register is loaded from
the DAL lines by a Write operation and holds the
"OLE" character used in the Transparent mode of
operation in which an idle transmit period is filled
with the combination DLE-SYN pair of characters
rather than a single SYN character. In addition the
ASTRO may be programmed to force a single OLE
character prior to any data character transmission
while in the transmitter transparent mode.
TRANSMITTER HOLDING REGISTER - This 8-bit
parallel buffer register holds parallel transmitted data
transferred from the DAL lines by a Write operation.
This data is transferred to the Transmitter Register
when the transmitter section is enabled and the
Transmitter Register is ready to send new data.
RECEIVER HOLDING REGISTER - This 8-bit
parallel buffer register presents assembled receiver
characters to the DAL bus lines when requested
through a Read operation.
COMPARATOR - The 8-bit comparator is used in
the Synchronous mode to compare the assembled
contents of the Receiver Register and the SYN
register or OLE register. A match between the
registers sets up stripping of the received character,
when programmed, by preventing the data from
being loaded into the Receiver Holding Register. A bit
in the Status Register is set when stripping is performed. The comparator output also enables
character synchronization of the Receiver on two
successive matches with the SYN register.
435
c:
(")
......
......
......
0')
In the Asynchronous mode the character transmission occurs when information contained in the
Transmitter Holding Register is transferred to the
Transmitter Register. Transmission is initiated by the
Insertion of a Start bit, followed by the serial output
of the character least significant bit first with parity, if
enabled, following the most significant bit· then the
insertion of a 1-,1.5-, or 2-bit length Stop c~ndition. If
the Transmitter Holding Register is full, the next
character transmission starts after the transmission
of the Stop bit of the present character in the
Transmitter Register. Otherwise, the Mark (logic high)
condition is continually transmitted until the Transmitter Holding Register is loaded.
In order to allow re-transmission of data received at a
slightly faster character rate, means are provided for
shortening the Stop bit length to allow transmission
of characters to occur at the same rate as the
reception of characters. The Stop bit is shortened by
1/16 of a bit period for 1-Stop bit selection and 3/16
of a bit period for 1.5-, or 2-Stop bit selection, if the
next character is ready in the Transmitter Holding
Register.
TRANSMITTER REGISTER - This 8-bit shift register
is loaded from the Transmitter Holding Register, SYN
register, or DLE register. The purpose of this register
is to serialize data and present it to the transmitted
Data output.
CONTROL REGISTERS - There are two 8-bit
Control Registers which hold device programming
signals such as mode selection, clock selection,
interface signal control, and data format. Each of the
Control Registers can be loaded from the DAL lines
by a Write operation or read onto the DAL lines by a
Read operation. The registers are cleared by a Master
Reset.
STATUS REGISTER - This 8-bit register holds information on communication errors, interface data
register status, match character conditions, and
communication equipment status. This register may
be read onto the DAL lines by a Read operation.
DATA ACCESS LINES - The DAL is an 8-bit bidirectional bus port over which all address, data,
control, and status transfers occur. In addition to
transferring data and control words the DAL lines
also transfer information related to addressing of the
device, reading and writing requests, and interrupting
information.
SYNCHRONOUS MODE
Framing of characters is carried out by a speCial
Synchronization Character Code (SYN) transmitted at
the beginning of a block of characters. The Receiver,
when enabled, searches for two continuous characters matching the bit pattern contained in the SYN
regist~r. During the time the Receiver is searching,
data IS not transferred to the Receiver Holding
Register, status bits are not updated, and the Receiver interrupt is not activated. After the detection of
the first SYN character, the Receiver assembles
subsequent bits into characters whose length is
determined by contents of the Control Register. If,
after the first SYN character detection, a second SYN
chara?ter. is present, t~e Receiver enters the SynchrOnization mode until the Receiver Enable Bit is
turned off. If a second successive SYN character is
not found, the Receiver reverts back to the Search
mode.
In the Synchronous mode a continuous stream of
characters are transmitted once the Transmitter is
enabled. If the Transmitter Holding Register is not
loaded at the time the Transmitter Register has
completed transmission of a character, this idle time
will be filled by a transmission of the character
contained in the SYN register in the Nontransparent
mode, or the characters contained in the DLE and
SYN registers respectively while in the Transparent
mode of operation.
ASTRO OPERATION
ASYNCHRONOUS MODE
Framin~ of a~ynchronous characters is provided by a
Start bit (logiC low) at the beginning of a character
and a Stop bit (logic high) at the end of a character.
Reception of a character is initiated on recognition of
the first Start bit by a positive transition of the
receiver clock, after a preceding Stop bit. The Start
and Stop bits are stripped off while assembling the
serial input into a parallel character.
~he character as~embly is completed by the reception of the Stop bit after reception of the last charac~er or pari~y bit. If this bit is a logic high, the character
IS determmed to have correct framing and the ASTRO
i~ ~repare~ to receive the next character. If the Stop
bit IS a logiC low the Framing Error Status flag is set
and the Receiver assumes this bit to be the Start bit
of the next character. Character assembly continues
from this point if the input is still a logic low when
sampled at the theoretical center of the assumed
Start bit. As long as the Receive input is spacing, all
zero characters are assembled and error flags and
data received interrupts are generated so that line
breaks can be determined. After a character of all
zero~s is asse~bled along with a zero in the Stop bit
location, the first received logic high is determined
as a Stop bit and this resets the Receiver circuit to a
Ready state for assembly of the next character.
DETAILED OPERATION
Receiver - The Receiver Data input is clocked into
the Receiver Register by a 1X Receiver Clock from a
modem Data Set, or by a local 32X bit rate clock
selected from one of four externally supplied clock
436
inputs. When using the 1X clock, the Receiver Data is
sampled on the positive transition of the clock in
both the Asynchronous and Synchronous modes.
When using a 32X clock in the Asynchronous mode,
the Receive Sampling Clock is phased to the MarkTo-Space transition of the Received Data Start bit and
defines, through clock counts, the center of each
received Data bit within + 0%, - 3% at the positive
transition 16 clock periods later.
In the Synchronous mode the Sampling Clock is
phased to all Mark-To-Space transitions of the
Heceived Data inputs when using a 32X clock. Each
transition of the data causes an incremental correction of the Sampling Clock by 1/32nd of a bit period.
The Sampling Clock can be immediately phased to
I3very Mark-To-Space Data transition by setting Bit 4
of Control Register 1 to a logic high, while the
Receiver is disabled.
When the complete character has been shifted into
the Receiver Register it is then transferred to the
Receiver Holding Register; the unused, higher number bits are filled with zeroes. At this time the Receiver Status bits (Framing Error/Sync Detect, Parity
ErrorlDLE Detect, Overrun Error, and Data Received)
are updated in the Status Register and the Data
Received interrupt is activated. Parity Error is set, if
encountered while the Receiver parity check is
enabled in the Control Register. Overrun Error is set if
the Data Received status bit is not cleared through a
Read operation by an external device when a new
character is ready to be transferred to the Receiver
Holding Register. This error flag indicates that a
character has been lost, as new data is lost and the
old data and its status flags are saved.
The characters assembled in the Receiver Register
that match the contents of the SYN or DLE register
are not loaded into the Receiver Holding Register,
and the DR interrupt is not generated, if Bit 3 of
Control Register 2 (CR23 = SYN Strip) or Bit 4 of
Control Register 1 (CR14 = DLE Strip) are set
respectively, the SYN-DET and DLE-DET status bits
are set with the next non SYN or DLE character.
When both CR23 and CR14 are set (Transparent
mode), the DLE-SYN combination is stripped. The
SYN comparison occurs only with the character
received after the DLE character. If two successive
DLE characters are received only the first DLE
character is stripped. No parity check is made while
in this mode.
Register when the latter has completed transmission
of a character. However, information in the DLE
register may be transferred prior to the information
contained in the Transmitter Holding Register if the
Force DLE signal condition is enabled (Bit 5 = Force
DLE and 6 = TX Transparent Control Register 1 set to
a logic one). The control bit CR15 must be set prior to
loading of a new character in the transmitter holding
register to insure forcing the OLE character prior to
transmission of the data character. The Transmitter
Register output passes through a flip-flop which
delays the output by one clock period. When using
the 1X clock generated by the Modem Oata Set, the
output data changes state on the negative clock
transition and the delay is one bit period. When using
a local 32X clock the transmitter section selects one
of the four selected rate inputs and divides the clock
down to the baud rate. This clock is phased to the
Transmitter Holding Register empty flag such that
transmission of characters occurs within two data bit
times of the loading of the Transmitter Holding Register when the Transmitter Register is empty.
When the Transmitter is enabled, a Transmitter interrupt is generated each time the Transmitter Holding Register is empty. If the Transmitter Holding
Register is empty when the Transmitter Register is
ready for a new character the Transmitter enters an
idle state. During this idle time a logic high will be
presented to the Transmitted Data output in the
Asynchronous mode or the contents of the SYN
register will be presented in the Synchronous Nontransparent mode (CR16 = 0). In the Synchronous
Transmit Transparent mode (enabled by Bit 6 of
Control Register 1 = Logic 1), the idle state will be
filled by a OLE-SYN character transmission in that
order. When entering the Transparent mode the OLESYN fill will not occur until the first forced DLE.
If the Transmitter section is disabled by a reset of the
Request to Send, any partially transmitted character
is completed before the transmitter section of the
ASTRa is disabled. As soon as the CTS goes high
the transmitted data output will go high.
When the Transmit parity is enabled, the selected
Odd or Even parity bit is inserted into the last bit of
the character in place of the last bit of the
Transmitted Register. This limits transfer of character
information to a maximum of seven bits plus parity or
eight bits without parity. Parity cannot be enabled in
the Synchronous Transparency mode.
DEVICE PROGRAMMING
Transmitter - Information is transferred to the
Transmitter Holding Register by a Write operation.
Information can be loaded into this register at any
time, even when the Transmitter is not enabled.
Transmission of data is initiated only when the
Request To Send bit is set to a logic one in the
Control Register and the Clear To Send input is a
logic low. Information is normally transferred from
the Transmitter Holding Register to the Transmitter
The two 8-bit Control Registers of the ASTRa determine the operative conditions of the ASTRa chip.
Control Register 1 is shown in the following table.
437
BIT7
c:
o.....
0)
......
.....
7
6
SYNC/ASYNC
~
O-LOOPMODE
1-NORMAL
MODE
O-NON BREAK
MODE
1-BREAK MODE
5
ASYNC~TRANS.
~
0-1 1/2 or 2 STOP BIT
SELECTION
1-SINGLE STOP BIT
ASYNC !TRANS.
DISABLED
O-MiSCOUi'RESET
1- MiSC01J'1' SET
SYNC (CR16
= 0)
O-NO PARITY
GENERATED
1-TRANSMIT PARITY
ENABLED
2
1
0
ASYNC
~
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
O-NON ECHO
MODE
1-AUTO ECHO
MODE
O-NO PARITY
ENABLED
1-PARITY CHECK
ENABLEDON
RECEIVER PARITY
GENERATION
ENABLED ON
TRANSMITTER
O-RECEIVER
DISABLED
1-RECEIVER
ENABLED
O-RTS RESET
O-DTR RESET
1-RTSSET
1-DTR SET
§Y!:!.f
O-NON TRANSMITTER TRANSPARENT MODE
1-TRANSMIT
TRANSPARENT
MODE
3
4
SYNC !CR12
= 11
O-DLE
STRIPPING
NOT
ENABLED
1-DLE
STRIPPING
ENABLED
SYNC!CR12
= Ql.
2:!!:!£
O-RECEIVER PARITY
CHECK IS DISABLED
1-RECEIVER PARITY
CHECK IS ENABLED
o-M'iSC RESET
SYNC !CR16 - 11
1-MlSCSET
O-NO FORCE OLE
1-FORCE OLE
CONTROL REGISTER 1
Register when CR15 is a logic one in the sync mode.
Bit 5 - In the Asynchronous mode a logic 1, with the
Transmitter enabled, causes a single Stop bit to be
transmitted. A logic 0 causes 2-Stop bit transmission
for character lengths of 6, 7, or 8 bits and one-and-ahalf Stop bits for a character length of 5 bits.
With the Transmitter disabled this bit controls the
Miscellaneous output on Pin 19, which may be used
for Make Busy on 103 Data Sets, Secondary Transmit
on 202 Data Sets, or dialing on CBS Data Couplers.
In the Synchronous mode a logic 1 combined with a
logic 0 on Bit 6 of control Register 1 enables Transmit
parity; if CR15 =0 or CR15 =1 no parity is generated.
When set to a logic 1 with Bit 6 also a logic 1, the
contents of the DLE register are transmitted prior to
the next character loaded in the Transmitter Holding
Register as part of the Transmit Transparent mode.
Bit 4 - In the Asynchronous mode a logic 1 enables
the Automatic Echo mode when the receiver section
is enabled. In this mode the clocked regenerated
data is presented to the Transmit Data output in place
of normal transmission through the Transmitter
Register. This serial method of echoing does not
present any abnormal restrictions on the transmit
speed of the terminal. Only the first character of a
Break condition of all zeroes (null character) is
echoed when a Line Break condition is detected. For
all subsequent null characters, with logic zero Stop
bits, a steady Marking condition is transmitted until
normal character reception resumes. Echoing does
not start until a character has been received and the
Transmitter is idle. The Transmitter does not have to
be enabled during the Echo mode.
In the Synchronous mode a logic 1, with the Receiver
enabled, does not allow assembled Receiver data
matching the DLE register contents to be transferred
to the Receiver Holding Register; also, parity checking is disabled.
Control Register 1
Bit 7 - A logic 0 configures the ASTRa into an Internal Data and Control Loop mode and disables the
Ring interrupt. In this diagnostic mode the following
loops are connected internally:
a. The Transmit Data is connected to the Receive
Data with the TD pin held in a Mark condition and
the input to the RD pin disregarded.
b. With a 1X clock selected, the Transmitter Clock
also becomes the Receive Clock.
c. The Data Terminal Ready (OTR) is connected to the
Data Set Ready (DSR) input, with the DTR output in
held in an Off condition (logic high), and the DSR
input pin is disregarded.
d. The Request to Send Control bit is connected to
the Clear To Sef!2lCiS) and Carrier Detector inputs, with the RTS output pin held in an Off
condition (logic high), and the CTS and Carner
Detector input pins are disregarded.
3. The Miscellaneous pin is held in an Off (logic high)
condition.
A logic 1 on Bit 7 enables the Ring interrupt and
returns the ASTRa to the normal full duplex configuration.
Bit 6 - In the Asynchronous mode a logic 1 holds
the Transmitted Data output in a Spacing (Logic 0)
condition, starting at the end of any current transmitted character, when the Transmitter is enabled.
Normal Transmitter timing continues so that this
Break condition can be timed out after the loading of
new characters into the Transmitter Holding Register.
In the Synchronous mode a logic 1 sets the Transmitter in a transparent transmission which implies
that idle transmitter time will be filled by DLE-SYN
character transmission and a DLE can be forced
ahead of any character in the Transmitter Holding
438
When the Receiver is not enabled this bit controls
the Miscellaneous output on Pin 19, which may be
used for New Sync on a 201 Data Set. When
operating with a 32X clock and a disabled Receiver a
logic 1 on this bit also causes the Receiver timing to
synchronize on Mark-To-Space transitions.
When parity is enabled it must be conside.red a~ a bit
when making character length selection, I.e. 5
character bits plus parity = 6 bits.
Bit 3 - In the Asynchronous mode a logic 1 enables
check of parity on received characters and generation of parity for transmitted characters.
Bit 5 - A logic 1 selects the Synchronous Character
mode. A logic 0 selects the Asynchronous Character
mode.
~n
the Synchronous mode a logic 1 bit enables check
of parity on received characters only. Note: Transmitter parity enable is controlled by CR15.
Bit 4 - A logic 1 selects odd parity and a logic 0
selects even parity, when parity is enabled by CR13
and/or CR15.
Bit 2 - A logic 1 enables the ASTRO to receive data
into the Receiver Holding Register, update Receiver
Status Bits 1 2, 3, and 4, and to generate Data
Received inte;rupts. A logic 0 disables the Receiver
and clears the Receiver Status bits.
Bit 1 -
Bit 3 - In the Asynchronous mode a logic 0 selects
the rate 1(-32X) clock input (pin 30) as the Receiver
Clock rate and a logic 1 selects the same clock rate
for the Receiver as selected by Bits 2-0 for the
Transmitter. This bit must be a logic 1 for the 1X clock
selection by Bits 2-0.
Controls the Request To Send output on.Ei!!
38 to control the CA circuit of the Data Set. The RTS
output is inverted from the state of CR11. A logic 1
combined with a low logic Clear To Send input
enables the Transmitter and allows THRE interrupts
to be generated. A logic 0 disables the Transmitter
and turns off the external Request To Send signal.
Any character in the Transmitter Register will be
completely transmitted before the Transmitter is
turned off. The Request To Send output may be used
for other functions such as "Make Busy" on 103 Data
Sets.
In the Synchronous mode a logic 1 causes all DLESYN combination characters in the Transparent
mode when DLE strip CR14 is a logic 1, or all SYN
characters in the Non·transparent mode to be
stripped and no Data Received interrupt to be
generated. The SYN Detect status bit is set with
reception of the next assembled character as it is
transferred to the Receiver Holding Register.
Bits 2·0 - These bits select the Transmit and
Receive clocks. The Input Clock to the Rate 4 pin
may be divided down to form the 32X clock from a
multiple clock as shown:
Bit 0 - Controls the Data Terminal Ready output on
Pin 16 to control the CD circuit of the Data Set. A
logic 1 enables the Carrier and Data Set Ready. interrupts. A logic 0 enables only the telephone Ime
Ring interrupt. The DTR output is inverted from the
state of CR10.
Clock
1X clock for Transmit and Receive
(Pins 35 and 34 respectively)
32X clock - Rate 1 input (Pin 30)
32X clock - Rate 2 input (Pin 31)
32X clock - Rate 3 input (Pin 32)
32X clock - Rate 4 input + 1 (Pin 33)
32X clock - Rate 4 input + 2 (Pin 33)
32X clock - Rate 4 input + 4 (Pin 33)
32X clock - Rate 4 input + 8 (Pin 33)
Bits 2·0
000
Control Register 2
Control Register 2, unlike Control Register 1, cannot
be changed at any time. This register should be
changed only while both the receiver and transmitter
sections of the ASTRO are in the idle state.
Bits 7·6 follows:
Character Length
8 bits
7 bits
6 bits
5 bits
Bits 7·6
00
01
10
11
001
010
011
100
101
110
111
These bits select the character length as
-BIT
7
6
SYNC/ASYNC
CHARACTER LENGTH SELECT
00
01
10
11
= 8 BITS
= 7 BITS
= 6 BITS
= 5 BITS
5
1
4
3
2
MODE SELECT
SYNC/ASYNC
~
SYNC/ASYNC
O-ASYNCHRONOUS
MODE
1-SYNCHRONOUS
MODE
1-0DD PARITY
SELECT
O-EVEN PARITY
SELECT
1-RECEIVER CLOCK
DETERMINED BY
BITS 2-0
0- RECEIVER CLK
= RATE 1
SYNC (CR14
= 0)
O-NO SYN STRIP
1-SYN STRIP
SYNC (CR14
= 11
O-NO DLE-SYN STRIP
1-DLE-SYN STRIP
CONTROL REGISTER 2
439
0
CLOCK SELECT
000 - IX CLOCK
001 - RATE 1 CLOCK
010 - RATE 2 CLOCK
011 - RATE 3 CLOCK
100 - RATE 4 CLOCK
101 - RATE 4 CLOCK ... 2
110-RATE4CLOCK ... 4
111 - RATE 4 CLOCK ... 8
c:
o......
CD
"'i
......
Received is not reset, at the time a new character is
to be transferred to the Receiver Holding Register.
This bit is cleared when no Overrun condition is
detected, i.e., the next character transfer time or
when the Receiver is disabled.
Bit 1 - A logic 1 indicates that the Receiver Holding
Register is loaded from the Receiver Register, if the
Receiver is enabled. It is cleared to a logic 0 when the
Receiver Holding Register is read onto the Data
Access Lines, or the Receiver is disabled.
Bit 0 - A logic 1 indicates that the Transmitter
Holding Register does not contain a character while
the Transmitter is enabled. It is set to a logic 1 when
the contents of the Transmitter Holding Register is
transferred to the Transmitter Register. It is cleared to
a 0 bit when the Transmitter Holding Register is
loaded from the DAL, or when the Transmitter is
disabled.
Status Register
The data contained in the Status Register define
Receiver and Transmitter data conditions and status
of the Data Set. The Status word is shown and
defined below.
Bit 7 - This bit is set to a logic 1 whenever there is a
change in state of the Data Set Ready or Carrier
Detector inputs while Data Terminal Ready (Bit 0 of
Control Register 1) is a logic 1 or the Ring Indicator is
turned on, with DTR a logic O. This bit is cleared when
the Status Register is read onto the Data Access
Lines.
Bit 6 - This bit is the logic complement of the Data
Set Ready input on Pin 28. With 202-type Data Sets it
can be used for Secondary Receive.
Bit 5 - This bit is the logic complement of the
Carrier Detector input on Pin 29.
Bit 4 - In the Asynchronous mode a logic 1 indicates that received data contained a log 0 bit after
the last data bit of the character in the stop bit slot,
while the Receiver was enabled. This indicates a
Framing error. This bit is set to a logic 0 if the proper
logic 1 condition for the Stop bit was detected.
In the Synchronous mode a logic 1 indicates that the
contents of the Receiver Register matched the contents of the SYN Register. The condition of this bit
remains for a full character assembly time. If SYN
strip (CR23) is enabled this status bit is updated with
the character received after the SYN character: In
both modes the bit is cleared when the Receiver is
disabled.
Bit 3 - When the DLE Strip is enabled (Bit 4 of
Control Register 1) the Receiver parity check is
disabled and this bit is set to a logic 1 if the previous
character to the presently assembled character
matched the contents of the DLE register, otherwise
it is cleared. The DLE DET remains for one character
time and is reset on the next character transfer or on
a Status Register Read. If DLE Strip is not enabled,
this bit is set to a logic 1 when the Receiver is
enabled, Receiver parity (Bit 3 of Control Register 1)
is also enabled, and the last received character has a
Parity error. A logic 0 on this bit indicates correct
parity. This bit is cleared in either of the above modes
when the Receiver is disabled.
Bit 2 - A logic 1 indicates an Overrun error which
occurs if the previous character in the Receiver
Holding Register has not been read and Data
BIT 7
• DATA
SET
CHANGE
INPUT/OUTPUT OPERATIONS
All Data, Control, and Status words are transferred
over the Data Access Lines (DAL 0-7). Additional
input lines provide controls for addressing a particular unit, and regulating all input and output
operations. Other lines provide interrupt capability to
indicate to a Controller than an input operation is
requested by the ASTRO. All input/output terminology below is referenced to the Controller so that a
Read or Input takes data from the ASTRO and places
it on the DAL lines, while a Write or Output places
data from the DAL lines into the ASTRO.
Read
A Read Operation is initiated by the placement of an
eight-bit address on the DAL by the Controller. When
the Chip Select signal goes to a logic low state, the
ASTRO compares Bits 7-3 of the DAL with its hardwired ID code (Pins 17, 22, 24, 25, and 26) and
becomes selected on a Match condition. The ASTRO
then sets its REPLY line low to acknowledge its
readiness to transfer data. Bits 2-0 of the address are
used to select ASTRO registers to read from as
follows:
Selected Register
Bits 2-0
Control Register 1
000
Control Register 2
010
Status Register
100
Receiver Holding Register
110
6
5
4
3
2
1
0
• DATA
SET
READY
• CARRIER
DETECTOR
• FRAMING
ERROR
• SYN
DETECT
• OLE
DETECT
., PARITY
ERROR
• OVERRUN
ERROR
• DATA
RECEIVED
• TRANSMITTER
HOLDING
REGISTER
EMPTY
STATUS REGISTER
440
When the Read Enable (RE) line is set to a logic low
condition by the. Controller the ASTRO gates the
contents of the addressed register onto the DAL. The
Read operation terminates, and the devices becomes
unselected, when both the Chip Select and Read
Enable return to a logic high condition. Reading of
the Receiver Holding Register clears the DR Status
bit. Bit 0 DALO must be a logic high in read or write
operations.
Write
A Write operation is initiated by the placement of an
eight-bit address or the DAL by the Controller. The
ASTRO compares Bits 7-3 of the DAL with its ID code
when the Chip Select input goes to a logic low state.
If a Match condition eXists, the device is selected
and makes it RPLY line low to acknowledge its readiness to transfer data. Bits 2-0 of the address are used
to select ASTRO registers to be written into as
follows:
Bits 2·0
000
010
100
110
3. Carrier On - Indicates Carrier Detector input
goes iow when DTR is on.
4. Carrier Off - Indicates Carrier Detector input
goes high when DTR is on.
5. DSR On - Indicates the Data Set Ready input
goes low when DTR is on.
6. DSR Off - Indicates the Data Set Ready input
goes high when DTR is on.
7. Ring On -Indicates the '=R"""in-g'""':I""'n-:'d"-ic-a"""to-r input goes
low when DTR is off.
Each time an Interrupt condition exists the INTR
output from the ASTRO is made a logic low. The
following interrupt procedure is then carried out even
if the interrupt condition is removed.
The Controller acknowled~ the Interrupt request by
setting the Chip Select (CS) and the Interrupt Acknowledge Input (lACRl) to the ASTRO to a Low
state. On this transition all non-interrupting devices
receiving the IACKI set their Interrupt Acknowledge
Output (~) low, enabling lower priority daisychained devices to respond to the Interrupt request.
The highest priority device that is interrupting will
then set its RPLY low. This device places its ID code
on Bit Positions 7-3 of the DAL when a low RE signal
is received. In addition Bit 2 is set to a logic one if any
of the interrupt numbers 1 and 3-7 above occurred,
and remains a logic zero if the THRE has caused the
interrupt (see note).
To reset the Interrupt condition (INTR) Chip Select
(CS) and (IACKI) must be received by the ASTRO. A
setup time must exist between CS and the liE or WE
signals to allow chip selection prior to read/write
operations and deselection control through the latter
~nals" The data is removed from the DAL when the
RE signal returns to the logic high state.
Selected Register
Control Register 1
Control Register 2
SYN and DLE Register
Transmitter Holding Register
When the Wnte Enable (WE) line is set to a logic low
condition by the copntroller the ASTRO gates the
data from the DAL into the addressed register. If data
is written into the Transmitter Holding Register, the
THRE Status bit is cleared to a logic zero.
The 100 address loads both the SYN and DLE registers. After writing into the SYN register the device is
conditioned to write into the DLE if followed by
another Write pulse with the 100 address. Any intervening Read or Write operation with other addresses resets this condition such that the next 100
will address the SYN register.
Interrupts
The following conditions generate interrupts:
1. Data Received (DR) - Indicates transfer of a new
character to the Receiver Holding Register while
the Receiver is enabled.
2. Transmitter Holding Register Empty (THRE) Indicates that the THR register is empty while the
Transmitter is enabled. The first interrupt occurs
when the Transmitter becomes enabled if there is
an empty THR, or after the character is transferred
to the Transmitter Register making the THR empty.
MAXIMUM RATINGS
VDD With Respect to VSS
(Ground)
+ 20 to - 0.3V
Max Voltage To Any Input With
Respect to VSS
+ 20 to - 0.3V
Operating Temperature
Storage Temperature
Power Dissipation
441
0° C to 70° C
Plastic
Ceramic
- 55° C to + 125 0 C
-65°Cto +150°C
1000 mW
c:
o
.....
0)
......
.....
OPERATING CHARACTERISTICS
~
....
...........
TA
= 0°Ct070°C, VDD = + 12.0V ±5%, VBB = -5.0V ±5%, VSS = OV, VCC = +5V ±5%
0)
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
CONDITIONS
UNITS
III
Input Leakage
10
ILO
Output Leakage
10
JJ.A
IBB
VBB Supply Current
1
mA
ICCAVE VCC Supply Current
80
mA
IDDAVE VDD Supply Current
10
mA
VIH
Input High Voltage
VIL
Input Low Voltage
(All Inputs)
VOH
Output High Voltage
VOL
Output Low Voltage
JJ.A
= VDD
VOUT = VDD
VBB = -5V
VIN
V
2.4
V
.8
= -100 JAA
10 = 1.6 mA
V 10
2.8
V
.4
AC CHARACTERISTICS
=
TA
O°C to 70°C, VDD
CLMAX = 20pf
= + 12.0V ± 5%, VBB = - 5.0V ± 5%, VCC = + 5.0 ± 5%, VSS = OV
CHARACTERISTIC
MIN
TAS
Address Set-Up Time
0
ns
150
ns
tah
TARL
TCS
Address Hold Time
Address to RPL Y Delay
CSWidth
TYP
UNITS
SYMBOL
MAX
400
0
ns
ns
250
TCSRLF GS to Reply OFF Delay
CONDITIONS
250
ns
RL
= 2.7 KQ
READ
TARE
Address and RE Spacing
250
ns
20
ns
TRECSH RE and CS Overlap
TRECS
TRED
TRE
RE to CS Spacing
ns
250
RE to Data Out Delay
RE Width
200
Address to WE Spacing
250
180
ns
1000
ns
WRITE
TAWE
ns
TWECSH WE and CS Overlap
20
TWE
WEWidth
200
TDS
Data Set-Up Time
150
ns
Data Hold Time
100
ns
WE to CS Spacing
250
ns
TDH
TWECS
442
ns
1000
ns
CL
= 20 pf
c:
o
......
0)
cs----+------.I
1
2
3
4
= VIH(min) = 2.4V
= VIL (max) = O.BV
= VOH (min) = 2.BV
= VOL (max) = O.4V
NOTE1:
NOTE 2:
......
......
ID DECODE is the major factor in
TARE and TARL timing.
If changing the Control Registers
while processing data the WE pulse
width must be contained within the
Data Valid envelope to insure correct
data processing.
WRITE CYCLE TIMING DIAGRAM
READ CYCLE TIMING DIAGRAM
INTERRUPT
CHARACTERISTIC
TCSI
TCSRE
TCSREH
CS to IACKI Delay
CS to RE Delay
CS and RE Overlap
MIN
TYP
MAX
UNITS
0
ns
250
ns
20
ns
TRECS
RE to CS Spacing
250
ns
Tpi
IACKI Pulse Width
200
ns
TIAD
IACKI to Valid 10
250
ns
180
ns
CONDITIONS
See Note 1.
Code Delay
TRED
TIARL
TCSRLF
TIAIH
RE OFF to DAL Open Delay
250
ns
250
ns
300
ns
IACKI to IACKO Delay
200
ns
IACKO OFF Delay
250
ns
IACKI to RPLY Delay
CS to RPLY OFF Delay
0
IACKI ON to INTR OFF
RL = 2.7 KQ
Delay
Til
TIOFF
From CS OFF, RE OFF, or
IACKI HIGH.
Note1: If RE goes low after IACKI goes low, the delay will be from the falling edge offiE.
Note 2: IACKO goes false after the last one of the following three signals go false: CS, "REand
lACK!. TIOFF is measured from the last signal going false.
443
See Note 2.
c:
0
.....
0)
......
.....
DAL
cs
RPLY
Note1:
FiE
DATIi must be a logic low during CS to form
an Interrupt Cycle Address during Daisy Chain
Interrupt Response.
INTR
iAcKT
IACKO
INTERRUPT CYCLE TIMING DIAGRAM
444
RECEIVER SECTION
•
445
c:
o.....
en
.....
.....
SYNCHRONOUS
ASYNCHRONOUS
See page 725 for ordering information.
TRANSMITIER SECTION
446
WESTERN DIGITAL
c
o
R
p
o
R
A
T
o
/
N
WD1931 & WD193X Family Data Sheets
:ec
......
CD
ColI)
......
Part 1
WD1931 Asynchronous/Synchronous Receiver/Transmitter ....................................... . 449
Part 2
WD1933
WD1935
WD193X Sync Data Link Controller. ................................................ 467
......
Application Note
CD
WD1931IWD193X Compatibility Application Note . .............................................. . 485
(1933) - NC
(1935) - REOM
1
CD
EOB
2
RE
CS
NC
VCC( + 5)
NC
FiE
R4
Cs
R3
MlSC OUT
R2
INTRa
R1
WE
Ai
MiSCOOi'
INTRa
WE
D1
D2
RTS
1xTC
DT
l52
D3
00
D4
RSCLK
D4
D5
Os
TBOC
00
1xRC
TO
:eC
6
......
7
CD
ColI)
C1'I
MR
OTR
ORao
ORal
VSS (GNO)
VDD(+ 12V)
ORao
Ai"
ORal
AO
NC
FEATURES
H LDC, SDLC }
ADCCP, X.25
Asynchronous Operation
Character Synchronous Operation
Programmable Syn and DLE Character
8 Selectable Clock Rates
.
Compatible
SDLC Loop Mode
NAZI and Digital Phase Lock Loop
447
ColI)
ColI)
J
07
RO
D7
VSS(GNO)
.
CTS·
MR
OTR
:ec
ORDERING INFORMATION
..:e
Table 5. WD193X ORDERING INFORMATION
C
CD
W
><
loop Mode
Maximum
Data Rate
Temp. Range
WD193X *.()()
WD193X *·10
no
yes
500KBPS
500KBPS
O°Cto + 70°C
O°Cto + 70°C
WD193X *·01
WD193X *·11
no
yes
1.0MBPS
1.0MBPS
O°Cto + 70°C
O°C to + 70°C
WD193X *·02
WD193X *·12
no
yes
1.5MBPS
1.5MBPS
O°Cto + 70°C
O°Cto + 70°C
WD193X *·03
no
2.0MBPS
O°Cto + 70°C
Part No.
* Please contact your local Western Digital Sales Representative for package availability and price information.
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
448
Pnnted on U S.A
-
WD1931 Asynchronous/Synchronous Receiver/Transmitter
FEATURES
SYNCHRONOUS AND ASYNCHRONOUS
• Full Duplex Operations
• Selectable Character Length (5, 6, 7 or 8 Bits)
SYNCHRONOUS MODE
• Two Successive SYN Characters Sets
Synchronization
• Programmable SYN and DLE Character
Detection and Stripping
• Programmable SYN and DLE-SYN Fill
• Transparent BI-SYNC Operation
• DDCMP Compatible
ASYNCHRONOUS MODE
• Line Break Detection and Generation
• 1-, 1V2-, or 2-Stop Bit Selection
• False Start Bit Detection
• Automatic Serial Echo Mode
• Overrun and Framing Error Detection
SYSTEM COMPATIBILITY
• Double Buffering of Data
• 8-Bit Bi-Directional Bus for Data, Status, and
Control Words
• All Inputs and Outputs TTL Compatible
• Chip Select, RE, WE, AO, A 1 Interface to CPU
• On-Line Diagnostic Capability
• Data Set, Carrier Detect, and Ring Interrupts
BAUD RATE - DC TO 1M BIT/SEC
8 SELECTABLE CLOCK RATES
• Accepts 1X Clock and Up to Four Different 32X
Baud Rate Clock Inputs
• Up to 47% Distortion Allowance with 32X Clock
PINOUT COMPATIBLE TO WD193X FOR
MULTIPROTOCOL BOARD APPLICATIONS
APPLICATIONS
SYNCHRONOUS COMMUNICATIONS
ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL COMMUNICATIONS
GENERAL DESCRIPTIONS
The WD1931 is a MOS/LSI device which performs the
functions of interfacing a serial data communications channel to a parallel digital system. This
device is capable of full duplex communications with
asynchronous and/or synchronous systems. Western
Digital has made device pin assignments for the
WD1931 to make it compatible with the WD193X
(Synchronous Data Link Controller). This pin out
allows the user to implement a one-board multiprotocol design. For character-oriented asynchronous and/or synchronous (bi-sync) protocols, the
WD1931 is used, and for bit-oriented SDLC, HDLC
and ADCCP protocols the WD193X is used (see
WD193X data sheets and WD1931IWD193X compatibility application notes).
VCC(+5)
CD
R4
R3
R2
AI
OSR
FiTS
1xTC
COMPARISON
REGISTER
RSCLK
I
CTS"
"'-~----TBOC
I
TBOC
RO
VOO(+ 12V)
Ai"
ORal
AD
_VSS (GNO)
AO
A1
CS
MODEM
INTERFACE
CONTROL
~
CLOCK
CONTROL
-VCC (+6)
-
RE
VSS(GNO)
::. ::.
lUlU"
c") N
~
cr:f-cr:cr:cr:cr:
PIN CONNECTIONS
Figure 1.
Figure 2.
WD1931 PIN CONNECTIONS
449
WD1931 BLOCK DIAGRAM
VOO (+ 12)
DESCRIPTION OF PIN FUNCTIONS
~
C
......
The WD1931 is packaged in a 40 pin DIP. The following is a functional description of each pin. A bar over a
signal (SIGNAL), means active Low.
~
Table 1.
DESCRIPTION OF WD1931 PIN FUNCTIONS
......
PIN
NUMBER
PIN NAME
SYMBOL
No connection allowed to this pin. Used internally only.
No connection.
This input, when low (and CS is active), gates
the content of addressed register onto the
Data bus.
This input, when low, selects the WD1931 for
a read or write operation to/from the Data bus.
This output is an extra programmable output
signal for the convenience of the user. Is
controlled by the CR4 bit (sync. mode) or CR5
bit (async mode).
This output is high whenever any of the interrupt conditions occur. Reading the status
register resets this signal (see Note 1).
This input when low (and CS is active), gates
the content of the Data bus into the addressed register.
Bidirectional three-state Data Bus. Bit 7 is
MSB.
This input, when low, initializes all the registers, and forces the WD1931 into an idle state.
The WD1931 will remain idle until a command
is issued by the CPU.
Modem Control Signal. This output when low,
indicates to the Data Communication Equipment (DCE) that the WD1931 is ready to transmit or receive data.
This output, when high, indicates that the
Transmitter Holding Register (THR) is empty
and ready to receive a data character from the
Data bus for a transmit operation. Loading
THR resets this signal.
This output, when high, indicates that Receiver Holding Register (RHR) contains a newly received data character, available to be read
onto the Data bus. Reading RHR resets this
signal.
Ground. No connection.
NC
3
READ ENABLE
NC
RE
4
CHIP SELECT
CS
5
MISC OUTPUT
MISC OUT
6
INTERRUPT
REQUEST
INTRQ
7
WRITE ENABLE
WE
DATA BUS
DO-D7
16
MASTER RESET
MR
17
DATA TERMINAL
READY
18
DATA REQUEST
OUTPUT
DRQO
19
DATA REQUEST
INPUT
DRQI
20
VSS
VSS
ADDRESS LINES
NC, AO,
2
8·15
21,22,23
om
24
VDD
VDD
25
TRANSMIITED DATA
TD
26
RECEIVE CLOCK
IXRC
FUNCTION
A1
These inputs are used to address the CPU
interface registers for read/write operations.
+ 12V.
This output transmits the serial data to the
Data Communications Equipment/Channel.
IX Receive Clock. This input is used to
synchronize the received data. Data is sampled on the positive transition of this signal.
450
Table 1.
PIN
NUMBER
PIN FUNCTIONS (Continued)
PIN NAME
SYMBOL
FUNCTION
27
RECEIVED DATA
RD
This input receives the serial data from the
Data Communication Equipment/Channel.
28
TRANSMITTER BYTE
OUTPUT COM PLETE
TBOC
29
CLEAR TO SEND
CTS
30
RECEIVER
SAMPLE CLOCK
TRANSMIT CLOCK
1X TRANSMIT CLOCK
RSCLK
This output goes high after the last bit of a
byte is transmitted including parity if enabled,
and is valid for one bit period.
Modem Control Signal. This input when low,
indicates that the DCE is ready to accept data
from the WD1931.
This output goes high when the receiver data
is sampled, and is valid for one clock period.
This input is used to synchronize the trans·
mitted data. The falling edge of this signal
generates new transmitted data.
Modern Control Signal. This output, when low,
indicates to the DCE that the WD1931 is ready
to transmit data.
If Bit 1 of Control R~ster 1 is reset during a
transmission then RTS will go high on the
falling edge of the transmitter clock that
follows the last bit of the current transmission
character.
Modem Control Signal. This input, when low,
indicates that the DCE is ready to receive or
transmit data.
Modem Control Signal. This input generates
an interrupt when made low with DTR off.
These four rate inputs are used for 32X Local
Transmit and Receive clocks. The rate is
selected by the Control Register. R1 is
common to both Transmitter and Receiver. R2·
R4 are clock rates for the Transmitter only.
Modem Control Signal. This input appears as
Status Bit 5 and generates interrupts when
going on or off if DTR is on.
+5V
31
1XTC
32
REQUEST TO SEND
RTS
33
DATA SET READY
DSR
34
RING INDICATOR
R1
CLOCK RATES
R1·R4
39
CARRI ER DETECT
CD
40
VCC
VCC
35-38
451
COMPARATOR - The 8-bit comparator is used in
the Synchronous mode to compare the assembled
contents of the Receiver Register to the SYN register
or OLE register. A match between the registers sets
up stripping of the received character, if so programmed, by preventing the data from being loaded
into the Receiver Holding Register. A bit in the Status
Register is set when stripping is performed. The
comparator output also enables character synchronization of the Receiver on two successive
matches with the SYN register.
DATA BUS - The Data Bus is an 8-bit inverted bidirectional bus port over which all data, control, and
status transfers occur.
ORGANIZATION
The WD1931 block diagram is illustrated on page 1.
The primary sections include the control, buffer,
status, receiver, transmitter, comparison and sync
registers.
CONTROL REGISTERS - There are two 8-bit Control Registers which hold device programming signals such as mode selection, clock selection, interface signal control, and data format. Each of the Control Registers can be loaded from the Data Bus by a
Write operation or read onto the Data Bus by a Read
operation. The registers are cleared by a Master
Reset.
RECEIVER HOLDING REGISTER - This 8-bit parallel buffer register presents assembled received characters to the Data Bus when requested through a
Read operation.
STATUS REGISTER - This 8-bit register holds information on communication errors, interface data
register status, match character conditions, and communication equipment status. This register may be
read onto the Data Bus by a Read operation.
OLE REGISTER - This 8-bit register is loaded from
the Data Bus by a Write operation and holds the DLE
character used in the Transparent mode of operation
in which an idle transmit period is filled with the
combination DLE-SYN pair of characters rather than
a single SYN character. In addition the WD1931 may
be programmed to force a single DLE character prior
to any data character transmission while· in the
transmitter transparent mode. This register cannot be
read onto the Data Bus. It must be loaded with logic
zeroes in all unused high-order bits.
SYN REGISTER - This 8-bit register is loaded from
the Data Bus by a Write operation and holds the
synchronization code used to establish receiver
character synchronization. It serves as a fill character
when no new data is available in the Transmitter
Holding Register during transmission. This register
cannot be read onto the Data Bus. It must be loaded
with logic zeroes in all unused high-order bits.
TRANSMITIER HOLDING REGISTER - This 8-bit
parallel buffer register holds parallel transmitted data
transferred from the Data Bus by a Write operation.
This data is transferred to the Transmitter Register
when the transmitter section is enabled and the
Transmitter Register is empty.
RECEIVER REGISTER - This 8-bit shift register
inputs the received data at a clock rate determined by
the selected receiver clock. This incoming data is
assembled to the selected character length and then
transferred to the Receiver Holding Register with
logic zeroes filling out any unused high-order bit
positions.
TRANSMITIER REGISTER - This 8-bit shift register
is loaded from the Transmitter Holding Register, SYN
register, or DLE register. The purpose of this register
is to serialize data and present it to the transmitted
Data output.
WD1931 OPERATION
ASYNCHRONOUS MODE
Framing of asynchronous characters is provided by a
Start bit (logic zero) at the beginning of a character
and a Stop bit (logic one) at the end of a character.
Reception of a character is initiated on recognition of
the first Start bit after a preceding Stop bit. The Start
and Stop bits are stripped off while assembling the
serial input into a parallel character. If enabled, the
parity bit is checked and then stripped off.
The character assembly is completed by the reception of the Stop bit after reception of the last character or parity bit. If this bit is a logic one, the character
is determined to have correct framing and the
WD1931 is prepared to receive the next character. If
the Stop bit is a logic zero, the Framing Error Status
flag is set and the Receiver assumes this bit to be the
Start bit of the next character. Character assembly
continues from this point if the input is still a logic
zero when sampled at the theoretical center of the
assumed Start bit. As long as Received Data is
spacing, all zero characters are assembled and error
flags and data received interrupts are generated so
that line breaks can be determined. After a character
of all zeroes is assembled along with a zero in the
Stop bit location, the first received logic one is
determined as a Stop bit and this resets the Receiver
circuit to a Ready state for assembly of the next
character.
In the Asynchronous mode the character transmission occurs when information contained in the Transmitter Holding Register is transferred to the Transmitter Register. Transmission is initiated by the
insertion of a Start bit, followed by the serial output
of the character (least significant bit first) with parity,
if enabled, following the most significant bit, then the
insertion of a 1-, 1.5-, or 2-bit length Stop bit. If the
Transmitter Holding Register is full, the next character transmission starts after the transmission of the
Stop bit(s) of the present character in the Transmitter
Register. Otherwise, the Mark (logic one) condition is
continually transmitted until the Transmitter Holding
Register is loaded.
In order to allow re-transmission of data received at a
slightly faster character rate, means are provided for
452
shortening the Stop bit length to allow transmission
of characters to occur at the same rate as the
reception of characters. The Stop bit may be shortened a maximum of 1/16 of a bit period for 1-Stop bit
selection and 3/16 of a bit period for 1.5- *, or 2-Stop
bit selection. To shorten the Stop bit the user must
load the Transmitter Holding Register exactly (X + 2)
16ths of a bit period before the end of a stop bit
transmission, where X = the number of 16ths the user
wishes to strip. If X + 2 exceeds the maximum then
no shortening occurs. This feature does not work in
1X clocking mode.
* NOTE: As a special case, the 1.5 stop bit mode can
be shortened from 1/24 to 11/24 of the whole
period if the Transmitter Holding Register is
loaded (X + 2) 24ths (of the whole period)
before the end of the stop bit transmission.
periods later.
In the Synchronous mode the Sampling Clock is
phased to all Mark-To-Space transitions of the Received Data inputs when using a 32X clock. Each
transition of the data causes an incremental correction of the Sampling Clock by 1/32nd of a bit period.
The Sampling Clock can be immediately phased to
every Mark-To-Space Data transition by setting Bit 4
of Control Register 1 to a logic one while the Receiver is disabled.
After a complete character has been shifted into the
Receiver Register, this is transferred to the Receiver
Holding register. The unused higher number bits are
filled with zeroes. At this time the Receiver Status
bits (Framing ErrorlSyn Detect, Parity ErrorlDLE
Detect, Overrun Error and DROI) are updated in the
Status Register and the DROI interrupt is activated.
Parity Error is set, if encountered and if the Receiver
parity check is enabled in the Control Register.
Overrun Error is set if the DROI bit is not cleared
through a Read operation when a new character is
ready to be transferred to the Receiver Holding
Register. This error flag indicates that new data is
lost and the old data character and its status flags are
saved.
The characters assembled in the Receiver Register
that match the contents of the SYN or DLE registers
are not loaded into the Receiver Holding Register
and the DROI is not set if Bit 3 of Control Register 2
(CR23 = SYN Strip) or Bit 4 of Control Register 1
(CR14 = DLE Strip) are set respectively. The SYN
DETECT and DLE DETECT status bits are then set
with the next non-SYN or OLE character. When both
CR23 and CR14 are set (Transparent mode), the DLESYN combination is stripped. The SYN comparison
occurs only with the character received after the OLE
character. If two successive DLE characters are
received only the first DLE character is stripped. No
parity check is made while in this mode.
SYNCHRONOUS MODE
Framing of characters is carried out by a special
Synchroniza.tion Character Code (SYN) transmitted at
the beginning of a block of characters. The Receiver,
when enabled, searches for two continuous characters matching the bit pattern contained in the SYN
register. During the time the Receiver is sea.rching,
data is not transferred to the Receiver Hqlding Register, status bits are not updated, and the DROI is not
activated. After the detection of the first SYN character, the Receiver assembles subsequent bits into
characters whose length is determined by contents
of the Control Register. If, after the first SYN
character detection, a second SYN character is
present, the Receiver enters the Synchronization
mode until the Act Rec bit is turned off. If a second
successive SYN character is not found, the Receiver
reverts back to the Search mode.
In the Synchronous mode a continuous stream of
characters are transmitted once the Transmitter is
enabled. If the Transmitter Holding Register is not
loaded at the time the Transmitter Register has
completed transmission of a character, this idle time
will be filled by a transmission of the character
contained in the SYN register in the Non-transparent
mode, or the characters contained in the DLE and
SYN registers respectively while in the Transparent
mode of operation.
Transmitter - A character is transferred to the
Transmitter Holding Register by a Write operation.
This can be done at any time, even when the
Transmitter is not enabled. Transmission of data is
initiated only when the ACT TRAN bit is set in the
Control Register and the Clear To Send input is Low.
A character is normally transferred from the Transmitter Holding Register to the Transmitter Register
when the latter has completed transmission of an
earlier character. However, information in the DLE
register may be transferred prior to this character
contained in the Transmitter Holding Register if the
Force DLE signal condition is enabled (CR15 and
CR16 are set). The control bit CR15 must be set prior
to loading of a new character in the transmitter
holding register to ensure forcing the DLE character
prior to transmission of this new data character. The
Transmitter Register output passes through a flipflop which delays the output by one serial data bit
time. When using the 1X clock the output data
changes state on the negative clock transition. When
DETAILED OPERATION
Receiver - The Received Data input is clocked into
the Receiver Register by a 1X Receive Clock from a
modem Data Set, or by a local 32X bit rate clock
selected from one of four externally supplied clock
inputs (R1-R4). When using the 1X clock, the
Received Data is sampled on the positive transition
of the clock in both the Asynchronous and Synchronous modes. When using a 32X clock in the
Asynchronous mode, the Receive Sampling Clock is
phased to the Mark-To-Space transition of the
Received Data Start bit and defines, through clock
counts, the center of each received Data bit within
+ 0%, - 3% at the positive transition 16 clock
453
:ec
......
co
(,.)
......
The transmitter divides the selected rate input down
to the baud rate. This clock is phased to the DRaa so
that character transmission starts within two clocks
of the THR loading when the transmitter is idle.
using a local 32X clock the transmitter section
selects one of the four selected clock rate inputs (R1R4) and divides the clock (by 32) down to the baud
rate. This clock is phased to the Transmitter Holding
Register empty flag (DRaa) such that transmission
of characters occurs within two data bit times of the
loading of the Transmitter Holding Register when the
Transmitter Register is empty.
When the Transmitter is enabled, the DRaa will set
each time the Transmitter Holding Register is empty.
If the Transmitter Holding Register still is empty
when the Transmitter Register is ready for a new
character, the Transmitter enters an idle state. During
this idle time a logic one will be presented to the
Transmitted Data output in the Asynchronous mode
or the contents of the SYN register will be presented
in the Synchronous Non-transparent mode (CR16
= 0). In the Synchronous Transmit Transparent mode
(CR16 is set), the idle state will be filled by a DLE-SYN
character transmission in that order. When entering
the Transparent mode the DLE-SYN fill will not occur
until the first forced DLE.
If the ACT TRAN bit is reset while a character is
currently being transmitted, this character will be
completed before the transmitter goes idle. When
CTS goes high however, the transmitter (TD) immediately goes idle.
When the Transmit parity is enabled, the selected
Odd or Even parity bit is inserted between the character and the Stop-bit/s. Parity cannot be enabled in the
Synchronous Transparency mode.
AUTO ECHO FEATURE
The device is capable of serially echoing the received
data with a one bit delay when in the Asynchronous
mode and the Receiver on. This causes the clocked
regenerated received data to be presented to the
Transmit Data output rather than the output of the
Transmitter Register and a steady marking on TD output. This serial method of echoing does not present
any abnormal restrictions on the transmit speed of
the terminal. Breaks are not echoed back. When the
device detects a Zero Stop bit and a character of all
zeroes, the echoing stops and a steady marking is
transmitted until such time as normal character
reception resumes. Because echoing is taking place
during determination of a break condition, a single
character of all zeroes (Null character) is echoed
when a break is initiated at the terminal. The Echoing
is enabled by setting Bit 4 of Control Register 1.
Echoing does not start until the start of a receive
character at a time when the transmitter is idle and
CTS is low. If the Transmitter is forced out of the idle
mode while a character is being echoed transmission
of that character is halted. The Transmitter is idle
when CR11 is a zero or the Transmitter is waiting for
the THR to be loaded in the Asynchronous mode.
LOOP FEATURE
The device has on-line diagnostic capability. When
bit CR17 is a zero (LOOP), the data and data set
controls are appropriately looped as follows:
• Transmit Data is connected to Receive Data, with
the TD output pin held in a MARK condition and
the RD input pin disregarded.
CLOCKING
Two clocking schemes are used. In one case a 1X
Receiver Timing and Transmitter Timing are used to
clock their respective data. In the second case a 32X
clock is used to clock the data. The device is capable
of selecting from four externally supplied clock-rates
(R1-R4).
The use of the 1X clock is the same for the receiver
and the transmitter in both the Synchronous and
Asynchronous Character modes.
The use of the 32X clock in the receiver differs
depending on mode. In the Asynchronous Character
mode the receive sampling clock is phased to the
mark-space transition of Received Data input at the
beginning of the Start bit, causing the Sampling
clock to be approximately in the middle of the bit.
The accuracy of sampling is + 0%, - 3%. In the
Synchronous Character mode the Receive Sampling
clock is phased to all the mark-space transitions on
the Received Data input. Each such transition of the
data causes an incremental correction of the
Sampling clock of 1/32 of the bit period. The Sampling clock can be immediately phased with the data
transitions by setting Bit 4 of Control Register 1 to a 1
bit with the receiver disabled. As long as this bit is a
one the Sampling clock is locked to every markspace data transition.
• Transmitter clock is connected to the Receive
clock.
• The Data Terminal Ready output is connected to
output pin
the Data Set Ready input with the
held in an OFF condition and the DSR input pin
disregarded.
• The Request To Send output is internally connected to the Clear To Send input and Carrier
Detect inputs, with the RTS output..£!..n held in an
OFF condition and the CTS and CD input pins
disregarded.
• MISCELLANEOUS output is also held in an OFF
condition.
om
INPUT/OUTPUT OPERATIONS
All data, control, and status information is when
needed transferred to the Data bus. Control and
address lines provide for controlling and addressing
of input and output operations. In addition, other
lines provide interrupt capability for alerting a CPU
that input/output is required. Input/output terminology is referenced to the CPU; therefore, a Read or In-
454
put receives data from the device and places"it on the
Data bus, while a Write or Output places data from
the Data bus into the device.
Table 2. REGISTER ADDRESS FOR
READ/WRITE OPERATIONS
Read
_
_
A read operation is initiated when both CS and RE go
low. When the Read Enable (RE) line goes low, the
device gates the contents of the addressed register
onto the Data bus. The device becomes unselected
when either the CS or RE go high. When the Receiver
Holding Register is read, the ORal is reset.
A1
AD
Read
Write
LO
LO
Control Register 1
Control Register 1
LO
HI
Control Register 2
Control Register 2
HI
LO
Status Register
SYN & OLE Register
HI
HI
Receiver Holding
Register
Transmitter Holding
Register
DEVICE PROGRAMMING
Programming, operating and monitoring of the
WD1931 is done via two Control Registers, one
Status Register, a SYN/DLE Register, and the Transmit and Receive Holding Registers. The two Control
Registers are referred to as CR1 and CR2. The bits
within CR1 are referred to as CR10 through CR17,
and the bits within CR2 are referred to as CR20
through CR27. For any register bit 0 is the LSB.
Two general modes of operation exist for the
WD1931, Asynchronous and Synchronous. Both
modes of operation are discussed separately. BISYNC is a special case of Synchronous mode and is
not treated separately.
Following figures below show CR1, CR2, and the
Status Register bit definitions. The meaning of each
bit in each register is described twice: once for
Asynchronous mode and again for Synchronous
mode. The figures combine and summarize both
modes.
W~
_
_
A Write operation is initiated when both CS and WE
go low. When the Wi1't9 ~ (WE) line goes low, the
device gates the data from the DataJ2..us into the
addressed register. When either the CS or WE go
high the device becomes unselected. When the
Transmitter Holding Register is written into, the
DROO is reset.
After first writing into SYN the device is conditioned
to write into OLE if followed by another Write to that
same address. Any intervening Read or Write to other
addresses reset this condition.
AD and A1 address device registers for ReadlWrite
operations are shown here:
See page 725 for ordering information.
455
TRANSMITTER SECTION (ASYNCHRONOUS)
Figure 5.
TRANSMITTER SECTION (SYNCHRONOUS)
TRANSMITTER FLOW CHART
456
•
Figure 6.
RECEIVER FLOW CHART
457
=e
ASYNCHRONOUS MODE
Control Register 1
C
-"
CO
CN
-"
BIT
NAME
0
DATA TERMINAL READY
(DTR)
1
ACTIVATE TRANSMITTER
(ACTTRAN)
2
ACTIVATE RECEIVER
(ACTREC)
3
PARITY ENABLE
4
ECHO MODE
5
STOP BIT
SELECTION/MISCELLANEOUS
6
BREAK
7
LOOP/NORMAL
FUNCTION
This bit controls the data Terminal Ready (DTR) signal to the
data set. When CR10 is a logical 0, DTR is off. When CR10 is
~icaI1, DTR is on. When the Self·Test mode is selected,
DTR signal is forced to an off state
This bit when set, enables the transmitter and sets RTS
signal. When this bit is reset, the Transmitter is disabled and
the RTS output turned off, but not till the end of any current
character being transmitted. The RTS output may be used
for other functions such as "Make Busy" on 103 data sets.
When set, enables the receiver, allowing received charac·
ters to be placed in the Receiver Holding Register, Status
Bits 1, 2, 3 and 4 to be updated, and the Data Request input
to be generated. When reset, the above status bits are
cleared. After this bit is set, character reception starts with
the first bit after a valid start bit.
When set, enables check of parity on received characters
and generation of parity for transmitted characters.
When set, and the RECEIVER is enabled, the clocked
regenerated data is presented to the Transmitted Data
output. The transmitter does not have to be enabled.
When set, with the transmitter enabled, causes a single
stop bit to be transmitted. When reset, causes two stop bits
to be transmitted for character lengths of 6, 7, or 8 bits and
1.5 stop bits for a character length of 5 bits. When the
transmitter is not enabled, this bit controls the MISCELLAN·
EOUS output on Pin 5 to be used for Make Busy on 103 Data
Sets, Secondary Transmit on 202 Data Sets, or dialing on
CBS Data Couplers.
When set, and the transmitter is enabled, the Transmitted
Data is held in a spacing condition starting with the end of
any current character. Normal transmitter timing continues
so that the break can be timed out by loading characters
into the THR, i.e., DRaOs are generated and the transmitter
operates normally except for the output which remains low
while this bit is a one.
When this bit is reset, the device is configured to provide an
internal data and control loop and the Ring Indicator in·
terrupt is disabled. When this bit is set, the device is in
normal full duplex configuration and the Ring Indicator
interrupt is enabled.
458
Control Register 2
BIT
2-0
NAME
CLOCK SELECT
FUNCTION
Selects Transmit and Receive clock as follows:
(IX) Transmitter Clock and if RX = 0, also
Receive Clock
1 - Rate 1 (32X)
2 - Rate 2 (32X)
3 - Rate 3 (32X)
4 - Rate 4 (32X)
} Transmitter Clock
Only
5 - Rate 4 (64X)
6 - Rate 4 (32X) (128X)
7 - Rate 4 (32X) (256X)
o-IXRC/IXTC
3
ALTERNATE RECEIVER
X CLOCK
When reset, selects Rate 1 as the Receiver clock rate. When
set, provides the same rate as Transmitter Clock (R1-R4).
This bit must be set if 1X clocking is selected in bits 2-0.
4
PARITY ODD/EVEN
When set, selects Odd Parity and reset selects Even Parity,
when Parity is enabled.
5
CHARACTER MODE
When reset, selects Asynchronous Character Mode.
When set selects Synchronous Character Mode.
CHARACTER LENGTH
Selects number of bits per character as follows (excluding
parity bit):
0-8 bits
1-7 bits
2-6 bits
3-5 bits
7-6
SYNCHRONOUS MODE
Control Register 1
BIT
FUNCTION
NAME
0
DATA TERMINAL READY
(OTR)
This bit controls the data Terminal Ready (OTR) signal to the
data set. When CR'IO is a logical 0, OTR is off. When CR10 is
~icaI1, OTR is on. When the Self-Test mode is selected,
OTR signal is forced to an off state
1
ACTIVATE TRANSMITTER
(ACTTRAN)
This bit when set, enables the transmitter and sets RTS
signal. When this bit is reset, the Transmitter is disabled and
the RTS output turned off, but not .!!..!!..!he end of any current
character being transmitted. The RTS output may be used
for other functions such as "Make Busy" on 103 data sets.
2
ACTIVATE RECEIVER
(ACTREC)
When set, enables the receiver, allowing received characters to be placed in the Receiver Holding Register, Status
Bits 1, 2, 3 and 4 to be updated, and the Data Request input
to be generated. When reset, the above status bits are
cleared. After this bit is set, character reception starts after
two matches to the contents of SYN Register:
459
~
C
.....
CO
.....
W
Control Register 1 (Sync Mode continued)
=e
c......
CO
CN
......
BIT
FUNCTION
NAME
3
PARITY ENABLE
When set, enables check of parity on received characters
only.
4
OLE STRIP/MISCELLANEOUS
When set, and the receiver is activated, received characters
which match the contents of the OLE Register are stripped
out. Also parity checking is disabled. When the receiver is
not activated, this bit controls the MISCELLANEOUS output
on Pin 5 to be used for New Sync on a 201 Data Set. When
operating with a 32X clock and the receiver is not activated,
this bit set also causes the receiver bit timing to syn·
chronize on mark·space transitions.
5
TX PARITY ENABLE/
FORCE OLE
When set, with Bit 6 of Control Register 1 reset, Transmit
Parity is enabled, otherwise no parity is generated. When
set, with Bit 6 set, it causes the contents of the OLE
Register to be transmitted prior to the next character loaded
in the Transmitter Holding Register. (See description of
Transparency)
6
TX TRANSPARENT
When set, the transmitter is conditioned for transparent
transmission, which implies that idle fill will be DLE·SYN
and a DLE can be forced ahead of any character in the THR
by use of Bit 5. (See description of Transparency)
7
LOOP/NORMAL
When this bit is reset, the device is configured to provide an
internal data and control loop (see Loop feature) and the
Ring Indicator interrupt is disabled. When this bit is set, the
device is in normal full duplex configuration and the Ring
Indicator interrupt is enabled.
Control Register 2
BIT
2·0
NAME
CLOCK SELECT
FUNCTION
Selects Transmit and Receive clock as follows:
-IXRCIIXTC (IX) Transmitter CloCk, and if RX = 0, also
Receive Clock
1 - Rate 1 (32X)
2 - Rate 2 (32X)
3 - Rate 3 (32X)
4 - Rate 4 (32X)
Transmitter Clock
5 - Rate 4 (64X)
Only
6 - Rate 4 (128X)
7 - Rate 4 (256X)
o
}
3
STRIP SYN
4
PARITY ODD/EVEN
5
CHARACTER MODE
When reset, selects Asynchronous Mode.
When set, selects Synchronous Mode.
CHARACTER LENGTH
Selects number of bits per character as follows (excluding
parity bit):
0-8 bits
1-7 bits
2·6 bits
3·5 bits
7·6
When set, and the receiver is enabled, received characters
which match the contents of theSYN Register are stripped
out. Also the SYN Detect status bit will be set for the next
input character. No SYN stripping occurs when reset.
When set, selects Odd Parity, when reset, selects Even
Parity, when parity is enabled.
460
TRANSPARENCY
The Transmit Transparency mode causes Idle Fill to
be the pair of characters DLE-SYN rather than a
single SYN, and provides for preceding a character
loaded into the THR with a DLE without the possibility of an intervening DLE-SYN fill. Transparency is
enabled by Bit 6 of Control Register 1, which allows
force DLE to be controlled by Control Register 1, Bit
5, but the DLE-SYN fill is not activated until after the
first forced DLE. All aspects of Transparency are
disabled when Bit 6 is reset. When forcing transmission of a DLE, Bit 5 should be set prior to loading the
Transmitter Holding Register, otherwise the character
in the Transmitter Holding Register may be transferred to the Transmitter Register prior to the setting
of the Control Bit.
STATUS
The Status Register contains the following status
information:
.-
BIT
0
NAME
DATA REQUEST OUTPUT
(DRQO)
1
DATA REQUEST INPUT
(DRQI)
2
OVERRUN ERROR (OE)
3
PARITY ERROR (PE)I
DLE DETECT
4
FRAMING ERROR (FE)/SYN
DETECT (SD)
5
CARRIER DETECTOR (CD)
6
DATA SET READY (DRS)
7
DATA SET CHANGE (DSC)
!
FUNCTION
When set, indicates a Data Request Output, meaning THR
is empty and CPU is allowed to load the new character to be
transmitted into the THR register. This bit is a mirror image
of DPQO signal (pin 18). Loading of THR resets DRQO.
When set, indicates a Data Request Input meaning RHR is
loaded with a new received character, and CDU is allowed to
read RHR register. This bit is a mirror image of DRQI signal
(pin 19). Reading RHR, resets DRQI.
This bit is set, when the previous character in the Receiver
Holding Register has not been read at the time a new
character is ready to be transferred to the Receiver Holding
Register. The bit is reset when a character is transferred to
the Receiver Holding Register. It is also reset when the
receiver is deactivated.
This bit is set, when the receiver is activated and Receive
parity is enabled and the last received character has a parity
error, and is reset if the character has correct parity. When
the DLE strip is enabled, the Receiver parity check is
disabled and this bit is set if the previous character matched the contents of the DLE Register and was stripped,
otherwise it is reset. This bit is reset when the receiver is
deactivated.
In the asynchronous mode this bit is set if the bit after the
last data bit, in the stop-bit slot, is a zero and the receiver is
enabled. This bit is reset if the. stop-bit is a one. In the
synchronous mode this bit is set when the contents of the
Receiver Register matches the contents of the SYN
Register and SYN strip is not enabled. In both modes the bit
is reset when the receiver is deactivated. If SYN strip is
enabled this status bit is updated when a character is
received after the SYN character.
This bit is a mirror image of CD signal. When this signal is
set, SR5 is set.
This bit is a mirror image of DSR signal. When this signal is
set SR6 is set. With 202-type data sets it can be used for
Secondary Receive.
This bit is set when there is a change in the state of the Data
Set Ready or Carrier Detect inputs when DTR is on, or when
the Ring Indicator goes on and DTR is off. This bit is reset
when the Status Register is read.
461
Control Registers 1, 2 and STATUS Bit Assignments
CONTROL REGISTER 1
(See Note 1 and 2)
BIT
6
7
SYNC/ASYNC
ASYNC
O-LOOPMODE
1-NORMAL
MODE
O-NON BREAK
MODE
1-BREAK MODE
5
SYNC
0-11/2 or 2 STOP BIT
SELECTION
1-SINGLE STOP BIT
SELECTION
ASYNC (TRANS.
DISABLED)
ASYNC
SYNC/ASYNC
SYNC/ASYNC
SYNC/ASYNC
a-NON ECHO
MODE
1-AUTOECHO
MODE
a-PARITY
DISABLED
1-PARITY CHECK
ENABLED ON
RECEIVER PARITY
GENERATION
ENABLED ON
TRANSMITTER
a-RECEIVER
DEACTIVATED
1-RECEIVER
ACTIVATED
0- TRANSMITTER
DEACTIVATED
1-TRANSMITTER
ACTIVATED
O-RESETS DTR
O-DLE
STRIPPING
NOT
ENABLED
1-DLE
STRIPPING
ENABLED
0- MiSc"CiIiT RES ET
1-
~r~) OUT SET
(=LO)
0
ASYNC
SYNC (CR12 = 1)
a-NON TRANS·
MITTER TRANS·
PARENT MODE
1-TRANSMIT
TRANSPARENT
MODE
1
2
3
4
ASYNC (TRANS.
ENABLED)
1-~~J~~
OUT (LO)
SYNC
a-RECEIVER PARITY
CHECK DISABLED
1-RECEIVER PARITY
CHECK ENABLED
SYNC (CR16 = 0)
SYNC(CR12 = 0)
a-NO PARITY
GENERATED
1-TRANSMIT PARITY
GENERATED
O-MISCOUT
RESET
1-~rgOUT
SYNC (CR16 = 1)
SET(= LO)
a-NO FORCE DLE
1-FORCE DLE
(See Note 1 and 2)
BIT
7
6
SYNC/ASYNC
CHARACTER LENGTH SELECT
00
01
10
11
=
=
=
=
8 BITS
7 BITS
6 BITS
5BITS
CONTROL REGISTER 2
5
4
3
2
MODE SELECT
SYNC/ASYNC
ASYNC
SYNC/ASYNC
a-ASYNCHRONOUS
MODE
1-SYNCHRONOUS
MODE
1-0DD PARITY
SELECT
a-EVEN PARITY
SELECT
1- RECEIVER CLOCK
DETERMINED BY
BITS 2·0
a-RECEIVER CLK
= RATE 1
1
CLOCK SELECT
000· IX CLOCK
001· RATE 1 CLOCK (32X)
010· RATE 2 CLOCK (32X)
011 . RATE 3 CLOCK (32X)
100· RATE 4 CLOCK (32X)
101· RATE 4 CLOCK (64X)
110· RATE 4 CLOCK (128X)
111 . RATE 4 CLOCK (256X)
a-NO SYN STRIP
1-SYN STRIP
NOTE 1.
As a result of the WD1931 's inverted data bus, to set a bit in above registers, the respective data bus line is to be set to low
(VIIJ·
STATUS REGISTER
(See Note 2)
6
5
4
3
2
1
0
• DATA
SET
READY
(DSR)
• CARRIER
DETECTOR
(CD)
• FRAMING
ERRORI
SYN
DETECT
(FE/SD)
• DLE
DETECTI
PARITY
ERROR
(DLE/PE)
• OVERRUN
ERROR
(OE)
• DATA
REQUEST
INPUT
(DRQI)
• DATA
REQUEST
OUTPUT
(DRQO)
BIT 7
• DATA
SET
CHANGE
(DSC)
NOTE 2.
a
As a result of the WD1931 's inverted data bus, when reading above registers, a data bus line set to low (VILl, indicates the
respective bit in the addressed register is set (logical 1).
REGISTER ADDRESS
Reg
A1
AO
Read
Write
0
LO
LO
Control Register 1
LO
= VIL at pins
1
LO
HI
Control Register 2
Control Register 2
HI
= VOH at pins
2
HI
LO
Status Register
SYN & DLE Register
3
HI
HI
Receiver Holding
Register
Transmitter Holding
Register
462
Control Register 1
DATA SET CHANGE INTERRUPTS
Ring Indicator On
The Ring Indicator On interrupt occurs when the Ring
Indicator input (Ri) goes low and DTR is off.
The following interrupts can be generated.
Carrier Detect On
When an interrupt condition exists, the INTRQ output
is set. Readi~ the Status Register or activating
Master Reset (MR) will reset INTRQ.
The Carrier Detect On interrupt occurs when the
Carrier Detect input (CD) goes low and DTR is on.
Carrier Detect Off
DATA BUS CONTROLS
The Carrier Detect Off interrupt occurs when the
Carrier Detect input (CD) goes high and
is on.
om
The following Data Bus controls can be generated.
DSR On
Data Request Output
The DSR On interrupt occurs when the Data Set
Ready input (DS1~) goes low and DTR is on.
This control signal occurs when the THR is empty
while the transmitter is enabled.
DSROff
Data Request Input
The DSR Off interrupt occurs when the Data Set
F~eady input (DSR) goes high and nTR is on.
This control signal occurs when the RHR is full while
the receiver is enabled.
HIGHIMP.S.~ATE
.
VALID
-
VIH
AO,A1,CS
VIL
FiE
t
--
, - - - _.....
VOL
TDOH
DAC
-------------- ----,. ,V
\,'- -----
____ J'I\.
J' '-- ---TCS
VIH
\
VIL
1\
I
I - - TSET--- •
Figure 3.
V
THLD-
TRE
READ TIMING
f;-
.
- V I L_ t ; _ V A _ U D
TDS
VIH
AO,A"i,CS
\I
TDH
- - --, I(
r - - - -- - - -- - - - - - - - - --
\
J\ '- -- --
I
VIL ___ _ ..J \
TCS
VIH
\
VIL
f--- TSET
/
\
J
.
Figure 4.
TWE
WRITE TIMING
•
463
THLD-
MAXIMUM RATINGS
=e
c
.....
CD
(I.)
.....
VDD With Respect to VSS
(Ground)
Max. Voltage To Any Input With
Respect to VSS
Operating Temperature
Power Dissipation
Storage Temperature Ceramic
Plastic
Table 3.
TA
+20to -0.3V
O°C to + 70°C
600mW
-65°Cto +150°C
- 55°C to + 125°C
WD1931 DC CHARACTERISTICS
= O°C to
SYMBOL
+70°C, VDD
= + 12.0V
± 0.6V, VCC :::: +5.0V ± 0.25V, VSS
CHARACTERISTIC
MIN
TYP
= OV
MAX
UNITS
CONDITIONS
= VDD
= VCC
III
Input Leakage
10
IJ.A
VIN
ILO
Output Leakage
10
IJ.A
VOUT
ICCAVE
VCC Supply Current
80
mA
10
mA
0.8
V
IDDAVE
VDD Supply Current
VIH
Input High Voltage
VIL
Input Low Voltage (All Inputs)
VOH
Output High Voltage
VOL
Output Low Voltage
Table 4.
TA
2.4
V
2.8
V
0.45
V
=
10
-1oo1J.A
10 = 1.6mA
WD1931 AC CHARACTERISTICS
= 0° C to
SYMBOL
I
+ 15 to -0.3V
+ 70° C, VDD
= + 12.0V
± 0.6V, VSS :; OV, VCC
CHARACTERISTIC
MIN
= + 5.0
TYP
± 0.25V
MAX
UNITS
5
ns
AO, A 1 & CS Width
495
ns
AO,A1 & CSSet·Up time
240
ns
1000
ns
MR Pulse Width
450
ns
TRE
REWidth
250
ns
TDACC
Data Access from RE
TDOH
Data Hold from RE
THLD
AO, A 1 & CS Hold Time
TCS
TSET
TCYCLE
Cycle Time
TMR
CONDITIONS
READ
50
300
ns
CL
150
ns
CL
WRITE
TWE
WE Width
250
ns
TDS
Data Set·Up Time
250
ns
TDH
Data Hold Time
100
ns
464
= 25 pf
= 25 pf
:ec
.....
.....
CO
W
HOST
PROCESSOR
IoATA=-
- - ..,
~XPA~ED
BELOWlj
I COMMUNICATIONS I
I CONTROLLER
ORDER ENTRY
PURCHASING
CRT
CARD
READER
LEASED OR DIAL UP LINES
BUY/SELL
TRANSACTION
ENTRY TERMINAL
(CRT)
FACSMILE
DATA COMMUNICATIONS SYSTEMS FOR STOCK BROKERAGE FIRM
--------l
r-
DATA COMMUNICATIONS CONTROLLER
I
I
I
I
I
I
I
PORT
SDLC
PROTOCOL
LINK
..,-.-'----r""""T'-....
I
I
I
CONTROUDATA/ADDRESS BUS
71
I'
SYNCHRONOUS
BISYNC
PROTOCOL
LINK
'--~--r----'
I
~----'I
MODEM 0
MODEM 3
MODEM 7
I
L ____________________'---_-_-::.J
TO REMOTE
TERMINAl.
TO REMOTE
TERMINAL
TO REMOTE
TERMINAL
DETAIL OF DATA COMMUNICATION CONTROLLER
DIGITAL COMMUNICATIONS SYSTEM
branch banks, or department stores and individual
cash registers. The exploded diagram of the DataCommunications Controller exemplifies the use of
one common circuit board design with eight multiprotocol circuits. When the Port requires a characteroriented protocol (synchronous, asynchronous, or
synchronous-bisync), the W01931 is plugged into the
appropriate socket. For SOLC, HOLC or AOCCP, the
W0193X is used.
The diagrarns above illustrate a typical digital system
employing several processing levels and digital
protocols. It is flexible enough to satisfy several
applications. For example. the host processor and
remote terminals could be located respectively in
airline reservation offices and ticket counters, travel
centers and travel agencies, central bank offices and
465
Information furnished by Western Digital Corporation Is believed to be accIJrate and reI/able. However, no responsibility is assumed by Western Digital
Corporation for Its use; nor for any infringements of patents or other rigtlts of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
466
WESTERN DIGITAL
CORPORATION
WD193X
Synchronous Data Link Controller
IFEATURES
• PROGRAMMABLE MODEM CONTROL INTERRUPTS
" HDLC, SDlC, ADCCP AND CCID X.25 COMPATIBLE
• DOUBLE BUFFERING OF DATA
" SDLC LOOP DATA LINK CAPABILITY
• DMA COMPATABILITY
" FULL OR HALF DUPLEX OPERATION
• END OF BLOCK OPTION
.. DC TO 2.0 MBITS/SEC DATA RATE
• VARIABLE CHARACTER LENGTH (5, 6, 7 OR 8 BITS)
" PROGRAMMABLE/AUTOMATIC FCS (CRC) GENERATION AND CHECKING
It
PROGRAMMABLE NRZI ENCODE/DECODE
It
FULL SET OF MODEM CONTROL SIGNALS
4.
DIGITAL PHASE LOCKED LOOP
It
FULLY COMPATIBLE WITH MOST CPU'S
It
MINIMUM CPU OVERHEAD
It
ASYNCHRONOUS/SYNCHRONOUS
MULTI-PROTOCOL BOARD CAPABILITY (PIN COMPATIBLE WITH WD
1931)
• RESIDUAL CHARACTER CAPABILITY
• ADDRESS COMPARE
• GLOBAL ADDRESS RECOGNITION
• EXTENDABLE ADDRESS FIELD
• EXTENDABLE CONTROL FIELD
• AUTOMATIC ZERO INSERTION AND DELETION
• MAINTENANCE MODE FOR SELF-TESTING
It
FULLY TTL COMPATIBLE
It
SINGLE +5V SUPPLY
APPLICATIONS
It
ERROR DETECTION: CRC, UNDERRUN, OVERRUN,
ABORTED OR INVALID FRAME ERRORS
• TERMINAL COMMUNICATIONS
STRAIGHT FORWARD CPU INTERRUPTS
• COMPUTER TO MODEM INTERFACING
It
(1933) (1935) -
• COMPUTER COMMUNICATIONS
NC
REOM
'
Too
2
INTF1Q
6
WE
7
151
152
153
04
155
156
13
[>7
MR
DTR
DROO
DRQI
VSS (GND)
Figure 1.
WD193X PIN CONNECTIONS
Figure 2.
467
WD193X BLOCK DIAGRAM
Loop configuration. An End of Block option is supplied to
minimize CPU time. A full set of modem control signals are
supplied to minimize external hardware.
• LINE CONTROLLERS
:ec
......
co
w
><
• FRONT END COMMUNICATIONS
• NETWORK PROCESSORS
A BRIEF DESCRIPTION OF HDLC, SDLC AND
ADCCP PROTOCOLS
• TELECOMMUNICATION SWITCHING NETWORKS
• MESSAGE SWITCHING
The WD193X is compatible with HDLC, SDLC and ADCCP
standard communication Link Protocols. These are bit-oriented, code independent, and ideal for full duplex communication. A single communication element is called a FRAME,
which can be used for both link control and data transfer
purposes.
The elements of a frame are the beginning eight bit FLAG
(F) consisting of one logical "0," six 1's and a 0, an eight bit
ADDRESS-FIELD(A), an eight bit CONTROL-FIELD (C), a
variable (N bits) INFORMATION-FIELD, a sixteen bit FRAMECHECK-SEQUENCE (FCS), and an eight bit end FLAG (F),
having the same bit-pattern as the beginning flag.
In HDLC, the address (A) and control (C) characters are
extendable (more than one character). An important characteristic of a frame is that its contents are made code transparent by use of a zero bit insertion and deletion technique.
Thus, the user can adapt any format or code suitable for his
system. The frame is bit-oriented, meaning that, bits not
characters in each field have specific meanings. The Frame
Check Sequence (FCS) is an error detection scheme similar
to the Cyclic Redundancy Checkword (CRC) widely used in
magnetic disk storage devices. The frame format is shown
in Figure 4.
• PACKET SWITCHING
• MULTIPLEXING SYSTEMS
• DATA CONCENTRATOR SYSTEMS
• SDLC LOOP DATA LINK SYSTEMS
• DMA APPLICATIONS
• COMMUNICATION TEST EQUIPMENT
• LOCAL NETWORKS
• MULTIDROP LINE SYSTEMS
GENERAL DESCRIPTION
The WD193X is a MOS/LSI microcomputer peripheral device which performs the functioning of interfacing a
parallel digital system to a synchronous serial data communication channel employing ISO's HDLC, IBM's SDLC or
ANSI's ADCCP line protocol. These protocols are referred
to as Bit-Oriented Protocols (BOP).
The chip is fabricated in N-channel depletion load MOS
technology and is TTL compatible on all inputs and outputs. This controller requires a minimum of CPU software
by supporting a comprehensive frame-level instruction set
and by hardware implementation of the low level tasks
associated with frame assembly/disassembly and data integrity. It can be programmed to encode/decode NRZI data.
The internal clock is then derived from the NRZI data using
a digital phase locked loop.
The receiver and transmitter logic operates as two total
independent sections with a minimum of common logic.
The frames are automatically checked for errors during reception by verifying correct Frame Check Sequence (FCS).
In transmit mode, the FCS is automatically generated by
this controller and sent before the final Flag. It also continuously checks for other errors. In case of an error, the CPU
is interrupted.
The controller recognizes and can generate Flag, Abort,
Idle and GA characters. WD193X can be used in an SDLC
Figure 4. WD193X SDLC/HDLC/ADCCP
FRAME FORMAT
Where:
FLAG = 01111110
Address field-One or more 8-bit characters defining the
particular station
Control field-One or two 8-bit characters
Information field-Any number of bits (may be zero bits)
.,
COMPUTE A
55-07
DTA
DSA
ATS
CS
~
WE
MA
Frame Check Sequence-16-bit error checking field
TIS_
SDLC
WD1933
AO
Al
A2
TO
AD
The following features are also part of these protocols.
AI
MODEM
ZERO INSERTION/ZERO DELETION-Zero insertion/deletion is performed within the 2 Flags of a frame. If there are
more than five 1's in a row, a 0 is automatically inserted after
the fifth 1 and it is deleted upon reception by the receiver.
A
TC
MlSC:lN
EOB
DAOI
DAao
INTAQ
MiSCOUT
~.s
M
F~ 1
lX132X
FRAME CHECK SEQUENCE (FCS)-A 16 bit cyclic redundancy check (CRC) calculation is performed during transmission of the data in between the 2 flags of the frame. The
CRC is then transmitted after the I-field and before the final
FLAG. Upon reception the receiver also performs a CRC
calculation on the incoming data. If there were no transmission error, the Receiver CRC equals FOB8 (hex).
+5
~d
.5~
~
5
I
. 5
Figure 3_ WD193X TYPICAL SYSTEM INTERFACE
468
•
DESCRIPTION OF PIN FUNCTIONS
The WD193X is packaged in a 40 pin DIP. The following is a functional description of each pin. A bar over a signal (SIGNAL),
means active low.
Table 1. DESCRIPTION OF WD193X PIN FUNCTIONS
PIN
NAME
PIN
SYMBOL
FUNCTION
NUMBER
1
No Connect
NC
WD1933 No Connection Allowed
Received End
of Message
REOM
Received End of Message with no Errors. Output on WD1935.
2
End of Block
EOB
This input, when low, function as an FCS command. Is independent
of CS.
3
Read Enable
RE
This input, when low (and CS is active), gates the content of addressed register onto the Data bus.
4
Chip Select
CS
This input, when low, selects the WD193X for a read or write operation
to/from the Data bus.
Misc Output
MISC OUT
This output is an extra programmable output signal for the convenience of the user. Is controlled by the CR10 bit.
6
Interrupt
Request
INTRa
This output is high whenever any of the interrupt register bits IR7·IR3
are set.
7
Write Enable
WE
This input when low (and CS is active), gates the content of the Data
bus into the addressed register.
5
I
8-15
Data Bus
00-07
Bidirectional three-state Data Bus. Bit 7 is MSB.
16
Master Reset
MR
This input, when low, initializes all the registers, and forces the
WD193X into an idle state. The WD193X will remain idle until a
command is issued by the CPU.
17
Data Terminal
Ready
DTR
Modem Control Signal. This output when low, indicates to the Data
Communication Equipment (DCE) that the WD193X is ready to transmit or receive data.
18
Data Request
Output
DRaO
This output, when high, indicates that the Transmitter Holding Register
(THR) is empty and ready to receive a data character from the Data
bus for a transmit operation.
19
Data Request
Input
DRal
This output, when high, indicates that Receiver Holding Register
(RHR) contains a newly received data character, available to be read
onto the Data bus.
20
VSS
VSS
Ground
21,22,23
Address Lines
A2,AO,A1
These inputs are used to address the CPU interface registers for read/
write operations.
24
Misc
Input
MISC IN
This input is an extra input signal for the convenience of the user. The
state is shown by the SR4 bit.
25
Transmitted Data
TD
This output transmits the serial data to the Data Communications
Equipment/Channel.
26
Receive Clock
RC
This input is used to synchronize the received data.
27
Received Data
RD
This input receives the serial data from the Data Communication
Equipment/Channel.
28
NRZI
NRZI
This input, when low, sets the WD193X in NRZI mode.
29
Clear to Send
CTS
Modem Control Signal. This input when low, indicates that the DCE
is ready to accept data from the WD193X.
30
DPLL Select
1X132X
This input controls the internal clock. When high (1X clock), the external clock has the same frequency as the internal clock. When low
(32X clock), the external clock is 32 times faster than the internal clock
and the DPLL Logic is enabled.
31
Transmit Clock
TC
This input is used to synchronize the transmitted data.
469
=e
c.....
CD
CN
><
Table 1.
PIN
NUMBER
PIN NAME
DESCRIPTION OF WD193X PIN FUNCTIONS (Continued)
SYMBOL
FUNCTION
32
Request to Send
RTS
Modem Control Signal. This output, when low, indicates to the DCE
that the WD193X is ready to transmit data.
33
Data Set Ready
DSR
Modem Control Signal. This input, when low, indicates that the DCE
is ready to receive or transmit data.
34
Ring Indicator
AI
Modem Control Signal. This input, when low, indicates a ringing signal
being received on the communication channel.
35,36
Ring Indicator
Interrupt Control
RIT,
37,38
Carrier Detect
Interrupt Control
CD1, CDO
These inputs are used to program Carrier Detect Interrupts.
39
Carrier Detect
CD
Modem Control Signal. This input, when low, indicates there is a carrier signal received by the local DCE from a distant DCE.
40
Vee
Vee
+5VDC
RIO
These inputs are used to program Ring Indicator interrupts.
Table 2. WD193X TERMINOLOGY
TERMINOLOGY
TERM
DEFINITION/DESCRIPTION
BOP
Bit~oriented
ABORT
11111111 (seven or more contiguous 1's)
protocols: SDLC, HDLC, and ADCCP
GA
Go-ahead pattern. 01111111 (O(LSB) followed by seven 1's)
LSB
First transmitted bit and first received bit. (Least significant bit)
MSB
Last transmitted bit and last received bit. (Most significant bit)
IDLE
11111111 11111111 (15 or more contiguous 1's)
FLAG
01111110. Starts and ends a Frame.
A-FIELD
Address-field in the Frame. Consists of one or more 8-bit characters. Defines the address
of a particular station.
C-FIELD
Control field in the Frame. Consists of one or two 8-bit characters.
I-FIELD
Information field in the Frame. Consists of any number of bits.
FCS
Frame Check Sequence. A 16-bit error checking field sequence.
FRAME
A communication element, consisting of a minimum of 32 bits, and delimited by FLAGS.
GLOBAL ADDRESS
An A-field character of eight 1·s. When this is compared and matched in the Address comparator, the DROI will be set, indicating a valid address
RESIDUAL
CHARACTER
The last I-field character, consisting of a lesser amount of bits than the other I-field characters in the Frame.
DATA SET
Data Communication Equipment (DCE). May be a modem.
BIT TIME
Length in time of a serial data bit.
470
HARDWARE ORGANIZATION
Various Internal Circuits
The WD193X block diagram is illustrated in Figure 2 and
described below.
ADDRESS COMPARATOR This 8-bit comparator is used
to compare the contents of the Address Register with the first
address character of the incoming frame. This feature is enabled by a bit in the Command Register. If enabled and there
is a match, the received frame is valid and DROls are generated for every character received (including the A-field). If
enabled and there is not a match or there is no Global Address, the received frame is discarded. If not enabled, all received frames are valid and DROls are generated.
ZERO INSERTION The transmitted data stream is
continuously monitored by this logic. A zero is automatically
inserted following five contiguous 1 bits anywhere between
the beginning FLAG and the ending FLAG of a frame. The
insertion of the zero bit thus applies to the contents of the
Address, Control, Information Data, and the FCS field.
ZERO DELETION The received data stream is continuously monitored by this logic. Upon receiving five contiguous
1 bits, the sixth bit is inspected. If the sixth bit is a 0, it is
automatically deleted from the data stream. If the sixth bit is
a 1, the seventh bit inspected; if it is a 0, a FLAG is recognized; if it is a 1 an ABORT or GO AHEAD is recognized.
DATA BUS (07-00) This is an inverted 8-bit bidirectional data bus.
SDLC l.OOP-MODE CONTROL This logic supervises
the WD193X running in SDLC Loop mode. It monitors the
received data for a GO-AHEAD pattern in the case when
SDLC LOOP MODE bit (CR22) and ACT TRAN bit (CR16)
are set. When GO-AHEAD pattern is received, this logic suspends the repeater function and initiates the transmitter function. For more details, see functional description of SDLC
Loop Mode.
NRZI ENCODER/DECODER When this mode is selected, the NRZI Encoder encodes the "normal" transmitted
data to NRZI formatted data and the NRZI Decoder decodes
the received NRZI data to "normal" data.
CPU Interfac:e Registers
All of these registers are addressable and to be read from
and/or written into by the CPU via the Data bus. These are
8-bit registers and have to be enabled via Chip Select (CS)
before any data transfer can be done.
CONTROL REGISTER 1,2,3 (CR1, 2, 3) Operations are
initiated by writing the appropriate commands into these registers. CR1 should be programmed last.
RECEIVER HOLDING REGISTER (RHR) When Data
Request Input is set (DROI= 1), contains received assembled character.
ADDRESS REGISTER (AR) Contains the address of this
WD193X which is to be compared to the received address
character (A-field).
INTERRUPT REGISTER (lR) Contains the cause of the
current interrupt request.
TRANSMITTER HOLDING REGISTER (THR) Is to be
loaded with the next in line character to be transmitted, when
Data Request Output is set (DROO= 1).
STATUS REGISTER (SR) Contains the overall status of
the WD193X plus some information of the last received
frame.
Non-Addressable, Internal Registers
These registers are transparent to the user, but is mentioned in these data sheets to help the understanding of the
WD193X
TRANSMITTER REGISTER (TR) This 8-bit register
functions as a buffer between the THR and the TO output.
It is loaded from the THR (if Data Command) with the next
character to be transmitted. A FLAG character may also be
loaded into this register under program control. This
character is automatically shifted out to the Transmit Data
output. When the last bit of the current transmitted character has left the TR register, a new character will be loaded
into this register, setting DROO (Data command) or INTRO
(Abort, Flag or FSC command). If at the time when only one
bit remains left in the TR register, and the THR is not loaded
or a new command is not programmed (Data command), an
underrun error will occur.
RECEIVER REGISTER (RR) The received data is, via
the Zero-Deletion logic shifted into this 8-bit register. The
data is here assembled to a 5, 6, 7 or 8-bit character length
and then, under the right conditions, parallel transferred to
the RHR register.
FCS RECEIVE REGISTER AND FCS XMIT REGISTER
The WD193X contains a 16-bit CRC check register (FCS
REC. REG.) and a 16-bit CRC generation register (FCS XMIT
REG.). The generating polynomial is:
G(X) = X16 + X12 + X5 + 1
A binary 1 for "normal data" is TO = high.
A binary 1 for NRZI data is TO = no change.
A binary 0 for "normal data" is TO = low.
A binary 0 for NRZI data is TO = change of state.
COMPUTER INTERFACE CONTROL This logic interfaces the CPU, to the WD193X. It supervises the read and
write functions to the addressable registers, generates data
requests and interrupts, decodes and initiates commands,
monitors the status of WD193X etc.
MODEM INTERFACE CONTROL This logic interfaces
and supervises the modem control signals to/from the
WD193X. It provides both dedicated (EIA Standard) and user
defined control functions.
CLOCK CONTROL This logic interfaces the transmit and
receive clocks to the WD193X. It converts the external clocks
to the necessary internal clocks.
The transmitter and receiver initialize the remainder value
to all ones before CRC accumulation starts. The data is
multiplied by X16 and is divided by G(X). Inserted O's are not
included in the accumulation. Under program control, the
complement called the frame check sequence (FCS) is sent
with high order bit first.
FUNCTIONAL DESCRIPTION
SDLC Loop Mode
The diagram below shows an SDLC Loop Data Link System. WD193Xcan be used in any of these stations.
471
:ec
.....
CD
(,.)
X
cycle is completed. The Primary Station may then transmit
or initiate another cycle as described above. As a repeater,
the transmitted data is delayed by 4 bits (NRZI=5 bits) relative to the received data.
1Xl32X Clock Option
When 1X clock is selected, the data rate equals the external clock (receiver and transmitter).
When 32X clock is selected, the external clock rate is 32
times faster than the data rate.
Figure 5. WD193X SDLC LOOP DATA LINK
Digital Phase Locked Loop (DPLL)
Each secondary station is normally a repeater in Receive
mode. The primary station is the loop controller. Signals sent
out on the loop by the primary station are relayed from station
to station, then back to the Primary. Any secondary station
finding its address in the A-field captures the frame for action
at that station. All received frames are relayed to the next
station on the loop.
If anyone of the secondary stations wants to transmit a
message, it sets its ACT TRAN bit and waits for a GOAHEAD (GA) pattern. The WD193X recognizes seven or
more contiguous logical 1's as a GO-AHEAD pattern. Until
GA pattern is received, this secondary station continues operating as a repeater. When primary station is done transmitting, it may send a continuous stream of GA patterns
down the Loop. This may be accomplished by going Idle.
When the first in turn secondary station, with the ACT TRAN
bit set, receives the GA pattern, it suspends the repeater
function and immediately goes into transmit mode. It transmits its message and when completed, it resets the ACT
TRAN bit. This converts the secondary station back to
repeater mode. The GA-patterns still transmitted by the Primary Station, gets relayed down the Loop to the next secondary station. The next down-loop secondary station has
the opportunity to transmit in the same manner. When the
primary station receives the GA-pattern, all the secondary
stations have been able to transmit their messages, and the
This feature is particularly useful in NRZI mode and/or
when asynchronous modem is used. The purpose of the
DPLL is to synchronize the internal1X clock to the received
data, thus insuring that this data is sampled in the middle
of the incoming serial data bit. DPLL is automatically in operation when 32X clock is selected.
The DPLL Logic is initiated at the first received data
transition in a frame. Corrections, if needed, are then made
for each received data tranSition. A 32-counter is used for
this operation. At the beginning of each frame and at the
first received data transition, this 32 counter is reset. From
this time on, the counter increments with one count for
each external clock pulse. At count 16 the internal1X clock
is forced to change state to high (this transition = sampling time). At count 32, the counter resets itself. This
forces the internal 1X clock again to change state back to
low.
At each received data transition, if the internal clock and
the received data is out of synchronization, a correction is
automatically made by ± 1 external clock period. See DPLL
Timing Diagram in Figure 6.
End Of Block (EOB)
This is an FCS command. The main purpose of EOB is to
allow the user to initiate FCS and FLAG without the need of
TC
(32X) ,
--I
AD
------~I~
(DATA)
~,5TC
NOTE 3
NOTE 4
_____________________________
L
~R:~~~~~~~~~ 1)
---r~
INTERNAL CLOCK
__________~1
!
l
SAMPLE
DATA
SAMPLE
DATA
NOTE 1. FIRST DATA TRANSITION (FIRST FLAG) SETS THE DPLL COUNTER TO 01.
NOTE 2. DATA TRANSITION IN BETWEEN HERE, OR NO D/\TA TRANSITION AT ALL, CAUSES NO CORRECTION OF THE
DPLL COUNTER.
NOTE 3. DATA TRANSITION IN BETWEEN HERE, WILL INCREMENT ONE COUNT TO THE DPLL COUNTER (ADD 01 TO
WHAT IS SHOWN).
NOTE 4. DATA TRANSITION IN BETWEEN HERE, WILL DEcnEMENT ONE COUNT TO THE DPLL COUNTER (SUBTRACT 01
TO WHAT IS SHOWN),
Figure 6. WD193X DPLL TIMING DIAGRAM
472
using extra computer time. This is particularly practical in
IDMA applications. At the end of a frame, when the last information data character has already been loaded into the
THR and once again DRQO is set, either a regular FCS command is written into CR1 Register, or EOB is to be activated.
_At the end of FCS, when INTRQ is set (XMIT OPCOM), the
EOB if activated is to be reset again.
PROGRAMMING
Controlling Operation
The serial data is synchronized by the externally supplied Transmit Clock (i(5) and Receive Clock (RC). When 1X
clock is selected, the falling edge of TC generates new
transmitted data and the rising edge of RC is used to sample the received data. When 32X clock is selected, a 32counter (in the DPLL Logic) is used to synchronize the internal clock. At time 0, when the counter is reset to 0, the
new transmitted data is generated. At time 16 (counter =
16) the received data is sampled, insuring that sampling is
done in the middle of the received serial data bit. At count
32, the counter is reset to again.
Prior to initiating data transmission or reception, CONTROL REGISTER 1-3 (CR1-3) must be loaded with control
information from the CPU. The contents of these registers
will configure the WD193X for the user's specific data communication environment. These registers should be loaded
during power-on initialization and after a reset operation.
They can be changed at any time that the respective transmitter or receiver is deactivated. The CR1-3 dictate what the
transmitter will send: the type of character (DATA, ABORT,
FLAG or FCS), the number of bits per character, and the
number of bits in the residual character. Similarly, they tell
the receiver the types of frames to look for: the number of
bits per I-field character, whether to perform an address compare, and whether to watch for an extended address. The
Control Register also control Data Terminal Ready (DTR),
Misc Out and the activation of both the transmitter and the
receiver. For more detailed information, see Register Formats.
Self Test (Diagnostic) Mode
Monitoring Operation
This feature is a programmable Loop back of data, enabling the user to make a complete test of the WD1933 with
a minimum of external circuitry. In this mode, transmitted
data to the TD pin, is internally routed to the received data
input circuitry, thus allowing a CPU to send a message to
itself to verify proper operation of the WD193X. The modem
control signals DTR and RTS are deactivated (off) to insure
no interference to/from the Data Communication Equipment
(DCE). DS~~d CTS are internally activated for proper input
conditions. TC and RC should be supplied by the same
source if 1X clock is selected.
Monitoring is done by use of the Interrupt Register (IR) and
Status Register (SR). The IR register indicates when a frame
is completed (transmitted or received), if there was an error
and if there is a Data Set Change. It also monitors the states
of INTRQ, DRQO and DRQI.
The SR register indicates if an error is recognized by IR,
what type of error. It also monitors the modem control
signals; Ring Indicator (RI), Carrier Detect (CD), Data Set
Ready (DSR) and Misc iii.
Furthermore, the SR register monitors if the Receiver is
idle, and also if in receive mode if the user has programmed
the Receiver Character Length to be 8 bits per character, this
register indicates the number of residual bits received. For
more detailed information, see Register Formats.
Serial Data Synchronization
°
Auto Flag
If this is selected and Data Command is executed, continuous Flags will be sent between frames. This eliminates the
need to execute the Flag Command. In DMA applications in
particular, this is very practical.
Extended Addressing
This type of addressing means, that there is more than one
address character in the A-field. In receive mode, the first
address character is compared in the Address Comparator
of the WD193X. The other address character/s is to be compared by the CPU. The last address character is recognized
by the fact that the LSB (bit 2°) is a 1.
Read/Write Control Of CPU Interface Registers
These registers are directly accessible from the CPU bus
(D7-DO) by a read and/or write operation by the CPU.
_The CPU must set up the WD193X register address (A2AO), Chip Select (CS), Write Enable (WE) or Read Enable
(RE) before each data bus transfer operation.
During a write operation, the falling edge of WE will initiate
a WD193X write cycle. The addressed register will then be
loaded with the content of the Data Bus (D7-DO). During a
read operation, the falling edge ofRE will initiate a WD193X
read cycle. The addressed register will then place its content
473
need Transmit Clock (TC) or Receive Clock (RC) to set
various bits, and are read-only.
All these registers will get initialized by a Master Reset. A
read operation of RHR resets the ORal. A write operation
to THR, resets the DROO. A read operation of IR, resets IR
bits 0 and 3-7. A read operation of SR, resets SR bits 0-2.
For addressing and external clocks needed, see figure
below.
onto the Data Bus (07-00). The read/write operation is completed, when CS or RE/WE is brought high.
For more detailed information, timing, etc., see Read/Write
Timing diagram.
For read and write operation, the CR1-3 registers normally need no external clock. After reset of CR1-3, TC clock is
required. The AR and THR registers need no external clock,
and can only be written into. The RHR, IR and SR registers
CS
A2
AT
AO
Read
Write
L
L
L
L
L
L
H
H
H
H
H
L
L
X
H
H
L
L
H
H
X
H
L
H
L
H
L
X
CR1
CR2
CR3
RHR
IR
SR
X
CR1
CR2
CR3
AR
THR
L
H
X
External Clock
None"
None"
None"
RHR=RC. AR=None
IR=TC". THR=None
SRO-3=RC. SR4-7=None.
X
= VIL at pins
= VIH at pins
= Don't care
" 2.5 TC clock cycles are required
after a Master Reset to be able to
read and write.
REGISTER FORMATS
Below shows a short form register format.
BIl_
17
16
15
14
13
CRl
26
27
24
25
23
22
21
20
CR2
37
35
36
34
33
32
31
30
CR3
RHR
AR
XMIT
XMIT
REOMI REOM PPCOM OPCC»
wi
W/NO~rROR~
RROR
WI
OSC
ORQI
ORQO
INTRQ
WI
IR
UNOEfi
NO
ERROR RUN
THR
RI
SR
Figure 7.
WD19~-IX
BIT ASSIGNMENTS
A more detailed description is shown here of each bit location. It should be known, that because the Data Bus Lines
(07-00) has inverted logic, a logic 1 (set) means low state.
Also, a modem control signal which is inverted (example
-DTR), is in on-state (set) when low.
Activate Transmitter (CR 16) This bit when set, enables
the transmitter and sets RTS signal. If in SDLC Loop Mode
(CR22 = set), the transmitter waits for a Go-Ahead pattern
before the transmitter is enabled.
Activate Receiver (CR 17) This bit when set activates
the receiver, which begins shifting in frames one character
at a time into RR register for inspection.
Control Register 1 (CR1)
When initiating a transmit/receive operation, this should be
the last register programmed.
Miscellaneous Output (CR10) This bit controls the Miscellaneous Output signal to the data set. When CR10 is a
logical 0, Misc Out is off, when it is a logical 1, Misc Out
is on.
OTR Command (CR11) This bit controls the data Terminal Ready (DTR) Signal to the data set. When CR11 is a
logical 0, DTR is off. When CR11 is a logical 1, DTR is on.
When the Self-Test mode is selected, DTR signal is forced
to an off state.
Transmitter Character Length (CR13, 12) These bits
control the transmitted I-field data character lenQth. The
data character may be 5, 6, 7 or 8 bits long.
CR13 (TCL1)
CR12 (TCLO)
Bits Per
Character
0
0
1
1
0
1
0
1
8
7
6
5
CONTROL REGISTER 2 (CR2)
Auto Flag (CR20) When set, Flags (without INTROs) will
be continuously transmitted in between frames, when otherwise the transmitter would be in idle state.
Self-Test Mode (CR21) When set, the Transmitter Data
Output is internally connected to the Receiver Data input
circuitry. The modem control output signals are deactivated
(off state). The modem control input signals are internally
activated. This mode allows off-line diagnostic.
SOLC Loop Mode (CR22) When set, the WD193X is
conditioned to operate in an SDLC Loop Data Link system
(see SDLC Loop Mode).
Receiver Character Length (CR24, 23) These bits indicate to tile receiver how many bits per character there are
to assemble for the I-field. The I-field characters may be 5,
6, 7 or 8 bits long. The unused bits read from RHR will be
10gical0.
Transmitter Commands (CR15, 14) These bits control
the transmission of DATA (A-field, C-field and I-field), ABORT,
FLAG, and FCS (FCS plus FLAG). When these commands
are programmed, the previous command currently still in
progress, will complete the transmission of its character.
When this is done, a new character generated by this new
command, will be transmitted.
If DATA is programmed, the new character to be transmitted will be the character loaded (or still to be loaded) in
the THR register. If ABORT is programmed, the new character will be eight logical I's. If FLAG is programmed, the
new charactm will be 01111110. If FCS is programmed, three
new characters will be transmitted; first the 16-bit content of
the FCS XMIT REGISTER, then a FLAG. One serial data bit
time ahead of the first bit (LSB) of this new character ( =
FLAG character when FCS command) being transmitted, the
CPU is signalled that the WD193X is again ready to receive
a new command. This signal is an INTRa (XMIT OPCOM),
if the now current command is ABORT, FLAG or FCS. This
signal is a DROO, if the current command is DATA. However,
in this latter case (DATA), the user has two choices; 1.
Change the command. 2. Keep the DATA command and
load a new character into the THR register. For more information, please see the Transmission Timing diagram, Figure
8.
Programming, see figure below.
CR15 (TC1)
CR14 (TCO)
o
o
o
1
-
1
o
1
CR24
(RCL1)
CR23
(RCLO)
Bits Per
Character
0
0
1
0
1
8
7
0
6
5
Extended Address (CR25) When set, this bit indicates
to the receiver that there is more than one address character
in the A-field. The receiver will expect another address character if the LSB in the current address character is a logical
O. The purpose of this bit: If a non-8-bit I-field character
length is expected, the ORals will get out of synchronization
if the WD193X does not know exactly when the I-field will
start. Not used in transmit mode.
Address Compare (CR26) When set, the first address
character will be inspected in the Address Comparator. If
there is a match with the AR register, or if the address compared is a Global Address (eight 1's) the frame is considered
valid, causing ORals to be generated. Otherwise, the receiver does not react, and will continue comparing for a new
valid address. If not set, all frames are considered valid.
Extended Control (CR27) When set, indicates that there
are two control characters per frame. If not set, there is only
one control character per frame. The purpose of this bit: If
a non-8-bit I-field character length is to be received, the
ORals will get out of synchronization if the WD193X does
not know when the I-field will start. Not used in transmit
mode.
Command
DATA
ABORT
FLAG
FCS
475
Character/s Transmitted
Signal to CPU
Content of THR
1111 1111
0111 1110
FCS + 01111110
DROO
INTRa
INTRa
INTRa
=e
C
-"
CO
W
><
CR32
(TRES 2)
CR31
(TRES 1)
CR30
(TRES 0)
0
0
0
0
1
0
0
0
1
0
1
0
1
0
'1
0
0
• Transmit Residual Character Length (CR32, 31,
30) These bits inform the transmitter what bit-length the
residual character will be. If no residual character is to be
sent, these bits must be set to logical O.
These bits are not used, and are
INTERRUPT REGISTER (IR)
This register contains the information why an interrupt
(INTRa) was generated. An IR register read operation, will
reset bits 0, and 3-7.
Loading the THR register, will reset DROO (bit 1). Reading
the RHR register, will reset ORal (bit 2). A new interrupt will
occur if one is pending.
If a new interrupt is generated while the CPU is reading
the IR register, this new interrupt will set the respective bit
in the IR register one bit time later (this to avoid losing any
interrupt). The status of bits 3-7 will accumulate until the IR
register is read by CPU.
INTRa (IRO) When set, indicates an interrupt and that
there are one or more bits set in positions 3 through 7 of this
register. This bit is a mirror image of INTRa signal (pin 6).
CD1
COO
LO
LO
HI
HI
LO
HI
LO
HI
No residual char. sent
1 bit
2 bits
3 bits
4 bits
5 bits
6 bits
7 bits
DRao (IR1) When set, indicates a Data request output.
This bit is a mirror image of DROO signal (pin 18) .
ORal (IR2) When set, indicates a Data Request input.
This bit is a mirror image of ORal signal (pin 19).
Data Set Change (IR3) When set, indicates a change of
state of the Data Set (Data Communication Equipment). This
is a change of state of DSR, CD orRI. The type of change
of CD and"Ri that this bit will react to, is programmed by use
of input signals CD1/CDO and"Ri1/RIO and is shown below.
XMIT Operation Complete with Underrun Error
(IR4) When set, indicates that the transmitter command
has been completed and there was an Underrun error. An
Underrun error occurs when the Data Request Output
(DROO) is set, but THR register is not loaded in time.
XMIT Operation with No Error (IRS) When set, indicates that the transmitter command has been completed and
there was no error.
Received End of Message With Errors (IR6) When set,
indicates that a Received End of Message is detected, and
there was an error. Errors include CRC, Overrun, Invalid
Frame and Aborted Frame.
The SR Register bits 0-2 will indicate the exact type of
error.
Received End Of Message With No Error (IR7) When
set, indicates that a Received End of Message is detected,
and there was no error.
CONTROL REGISTER (CR3)
Unused (CR33-37)
always a logical O.
Residual Char. Length
Interrupting edge of CD
RTf
RiO
Interrupting edge of"Ri
Rising and falling
Falling
Rising
None
LO
LO
HI
HI
LO
HI
LO
HI
Rising and falling
Falling
Rising
None
476
BTATUS REGISTER (SR)
mit data, it responds by activating the Clear to Send (CTS)
signal.
The WD193X is now conditioned to transmit. Now DRQO
gets set, indicating to the CPU (or DMA) to load the first character (Address) into the THR. When this is done, DRQO will
reset. As soon as the WD193X is ready to be loaded with the
next character to be transmitted, DRQO is again set. When
the THR register is again loaded with a character, DRQO will
again reset.
This same sequence continues until the last I-field character to be transmitted is loaded into the THR. If CRC checking is to be used, the next time when DRQO is set, an FCS
command has to be programmed. This is accomplished bv
either setting CR15, 14 to both logical 1's or by activating the
EOB signal.
At the end of the FCS being transmitted, INTRQ will set
indicating XMIT Operation Complete. The IR register is to be
read to find out whether the frame was sent with or without
error. Also the FCS Command which was used as described
above has to be changed. If CR15, 14 were set, these have
to be reset (to Data Command), or if EOB was activated, this
signal has to be deactivated. At this same time, the ACT
TRAN bit is allowed to be reset, causing the TO output to go
idle after the end Flag is sent. If the ACT TRAN bit is kept
set, continuous Flags will be sent following the FCS.
If a new frame is to be sent right after this first frame, only
one Flag is needed in between frames, meaning the frames
have one common Flag character. In this case, the second
frame Address character may be loaded at the same time
the FCS command is programmed during the first frame.
Also, the ACT TRAN bit should be kept set in between
frames. Every time DRQO gets set, the user must load the
THR register before the last loaded character only has 1.5
bits left to be transmitted. In other words, when DRQO gets
set, the user may wait (if 8-bit characters) up to 7.5 serial
data bits before loading the THR. If THR is not loaded within
this time, an Underrun error will occur.
If Auto Flag is not selected (CR20 = logical 0) the sequence
will be a little different than described below. When the first
DRQO is set, and after the Address character is loaded into
THR, a Flag command is also programmed (CR15, 14 = 10).
This will set an interrupt (INTRQ), which indicates that the
IR register must be read. Now, the Data Command is reprogrammed (CR15, 14 =00).
For more information, see Transmission Timing diagram.
This register contains the status of the receiver and some
rnodem control signals. It also indicates (if REOM w/Errors)
exactly what type of errors. If the Receiver Character Length
is 8 bits, this register indicates the amount of Residual bits
that was received. A read operation will reset bits 0-2.
Received Error/Received Residual Character Length
(SR 2-0) If REOM wiNO ERROR (IR7) is set, and the
I~eceiver, Character Length (CR24, 23) is 8 bits, these bits
(SR 2-0), indicate the number of residual bits received.
If REOM WITH ERROR (IR 6) is set, these bits indicate
the type of error that occurred, as shown in figure below.
Bit Set
Error
SRO
SRl
SR:2
CRC
Overrun
Aborted or
Invalid frame
Receiver Idle (SR 3) When set, indicates that the receiver is currently IDLE.
Miscellaneous Input (SR4) This is a mirror image of
MISC IN signal. When this signal is set, SR4 bit is set.
Data Set Ready (SRS) This is mirror image of DSR signal. When this signal is set, SR5 bit is set.
Carrier Detect (SR6) This is a mirror image of CD signal.
When this signal is set, SR6 bit is set.
Ring Indicator (SR7) This is a mirror image of AI signal.
When this signal is set, SR7 bit is set.
TRANSMITTER OPERATION
Prior to this operation, the programmable inputs and the
transmit mode related register bits need to be programmed
according to the user's specific data communications environment. The last bit to be set is always the ACT TRAN
(CR16) bit.
Before this, the INTRQ has to be cleared, which can be
done by reading the IR register. For more detailed information how to program the WD193X, see Programming.
As an example of how to program the WD193X, let's assume a 24-bit information is to be transmitted. The I-field
would then consist of three 8-bit characters with no residual
bits. CR3 should then be 00 (Hex).
If Auto Flag is selected, CR20 has to be set, CR21 and
CR22 should be logical O's, as this example is no Self-test
a!l.d no SDLC Loop Mode.
Bits CR23-CR27 are for reception only (see Receiver
Operation). The last register to be programmed is CR1. If
MISC OUT is not used, this may be ignored. If a modem is
used, DTR (CR11) is to be set. CR13 and CR12 should be
logical O's (8-bit char. length). CR15 and CR14 should be
logical O's (Data Command). ACT TRAN (CR16) bit is to be
set. The ACT REC (CR17) is for reception only.
The DTR bit, when set, activates the DTR signal, indicating
to the modem to prepare for communication. When the mod(:lm is ready, it sends back a Data Set Ready (DSR) to the
WD1933. This causes the DSC (IR3) bit to set, which in turn
activates INTRQ. The IR register is now read. Simultaneously, when the ACT TRAN (CR16) bit is set, this activates
the Request to Send (RTS) signal, instructing the modem to
enter into transmit mode. When the modem is ready to trans-
ABORT CONDITIONS
The function of prematurely terminating a data link is
called an "Abort." The transmitting station aborts by sending eight consecutive 1'So Unintentional Abort caused by
1's in the A-C- or I-field is prevented by zero insertion. Intentional Abort may be sent by programming an Abort command. Abort will also be sent in the case where THR is not
loaded in time or FCS command is not programmed in time
(= underrun). This means that after the DRQO is set, to
avoid Abort; THR must be loaded, EOB activated or FCS
command programmed before there is only 1.5 bits left of
the last character to be transmitted.
If this is not done, INTRQ (XMIT OPCOM w/underrun) is
set and Aborts are transmitted until, either the command is
changed or the THR is loaded. If in this same case, Auto
.......................................................................
477
indicate the type of errors (see Receiver Error Indication).
When all characters including the A-field and the FCSfield are read, and when the REOM interrupt is recognized,
it is up to the user to disassemble these mentioned characters from the received data. If non-8-bit characters are received, the amount of residual bits have to be calculated by
the CPU after masking out the part of the ending Flag
showing up in the last read character.
After end of frame, the receiver begins searching for a
new frame.
For more information, see Reception Timing diagram.
Flag was programmed, one Abort (with INTRa) would be
generated, and thereafter continuous Flags (with no INTROs)
will be sent.
RECEIVER OPERATION
Prior to this operation, the programmable inputs and the
receive mode related register bits have to be programmed
according to the user's specific data communication environment. Also, the INTRa has to be cleared. The last bit to be
set is always the ACT REC (CR17) bit.
For more detailed information how to program the WD193X
see Programming. As an example, let's assume a 26-bit information is to be received, and the I-field is made up by
S-bit characters. The CR3 register is only for transmit mode,
and may be ignored here. CR20 and CR 12-16 bits are also
for transmit mode only, and therefore may also be ignored.
CR21 and CR22 are to be logical Os (no Self-Test and no
SDLC Loop Mode). CR24,23 are to be logical O's (S-bit
character I-field). If only one A-field and one C-field character
is expected, and this WD193X has a specific address, CR25
should be a logical 0, CR26 should be a 1, and CR27 should
be a O. The address to which the A-field should compare
should be loaded into the AR register.
The status of the modem is monitored by the SR register,
and it may be useful to read it at this time. CR1 is loaded as
the last register. CR10 (Misc In) bit is optionable to the user.
CR11 (DTR) is to be set if modem is used. CR17 (ACT REC)
is now set, starting the input of frame characters into the
Receiver Register (RR). When a Flag is detected, the next
S-bit character (address-character), when received, is compared to the character in the AR register. If these match, or
if the received character is a Global address, this frame is
valid, and the DROI gets set. If the Address Comparator
(CR26) bit is not set, all frames would be considered valid
and generate DROls. When the RHR register is read, DROI
will be reset. All characters in a valid frame which are input
into the RR register will set DROI, and every time RHR is
read by the CPU, DROI will be reset.
During reception, the receiver also performs a CRC calculation on the incoming data. When the end Flag is received, INTRa will get set, indicating Received End of
Message. If the reception is completed with no error, IR7
(REOM wino Error) bit will be set. When 8-bit characters are
received SR 0-2 bits indicate the number of residual bits, in
this case two. If IR6 (REOM w/Error) was set, SR 0-2 bits
RECEIVER ERROR INDICATION
When a frame is received, and REOM w/Error (IR6) is set,
the type of error is indicated by the SR bits 0-2.
CRC Error (SRO) If the CRC calculation performed on
the incoming data does not equal to FOBS (HEX), this bit will
be set.
Overrun Error (SR1) After DROI is set, if the RHR is not
read within one character minus one bit time, this bit will be
set.
Aborted or Invalid Frame Error (SR2) If the frame is
aborted, or it consists of less than 32 bits between flags, this
bit will be set.
NOTES
1. TC-command-If two or more contiguous ABORTS or
FLAGS are executed, the ACT TRAN (CR16) bit has to be
reset before DATA-command can be executed.
2. Master Reset (MR)-Needs no clock during activation of
MR. However, 2.5 clock cycles are required to reset the
WD193Xafter the falling edge of MR.
3. IR-register-Immediately when IR register is read, bit 0
will reset. Bits 3-7 are reset one bit time later.
4. SR-register-Bits 0-2 are reset one bit time after SR register is read.
5. SDLC Loop mode-Go-ahead pattern may be sent by
either sending IDLE or ABORT after Flag.
6. TC and RC clocks are completely independent of each
other.
7. It is recommended to verify that the INTRa Signal (pin 6)
is set prior to reading the IR register.
478
TC
(lX CLOCK)
TO
--4I
'~
~
C
.....
0 1 1
~ 111
•
PATABITS
0
1:
I
I
tf
ADDAESS
t
I,
. 1,
CONTROL
INF. DATA
(NOTE 4)
.1 •
FCS
)
I
0 1 1 1 1 1 1 0
(
FLAG
)
I
- 1 1 - 1 DATA
BIT
I
CD
w
IDLE
I
DAQO
I~I
L
THA
LOADED
2.5
DATA
BITS
INTRa
t
~- ~
I8 2~ ~~
\I
--~
gj
~~~
-L
~~~
!H~
~~ffi
~~~
~9G
g:! ~ ~~~
1.
2.
3.
4.
-L
5
t~[[
NOTE
NOTE
NOTE
NOTE
IA
AEAD
r
=
~51!1i
~95
=
~
w
1:::0
~~N
~c
~ g~~
~
~ ~~~
~~
~~
?:ll
h
a:
I-
~~
=
CR3
OOH, CR2
01H, CR1
02H (FOR THIS EXAMPLE ONLY)
WRITE FCS COMMAND, OR ACTIVATE ~.
WRITE DATA COMMAND, OR DEACTIVATE"E<5B.
INF. DATA MAY CONSIST OF ANY NUMBER OF BITS.
Figure 8. WD193X TRANSMISSION TIMING DIAGRAM
IDLE
D;TArBITS
DAal
INTAa
----i
-f'
0
<:-
~~
8~
ll'!
~
~
~
I
I
l
--gj
~~~
o5l~
~~~
a:a:ll
1ci~a:
~§~
i~~
l
--«
.1-
~~~
o~~
i~~
a:a:ll
1- 1~~ffi~
<
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Absolute Maximum· Ratings
Storage Temperature
Storage Temperature
Voltage on any pin
with respect to GND (Vss)
Power Dissipation
- 55°C to + 125°e (plastic package)
-65°C to +150oe (ceramic package)
-0.3 to + 7.0V
1W
DC Characteristics
TA = ooe to +70°
VSS
OV, Vee
+ 5 ± 0.25V
=
=
Table 3. WD193X DC CHARACTERISTICS
III
ILO
VIH
VIL
VOH
VOL
ICC
Min
Parameter
Symbol
Typ
Max
Units
p.A
p.A
V
V
V
V
ma
10
10
Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Supply Current
2.4
0.8
2.4
0.4
210
70
Conditions
= Vee
= VCC
VIN
VOUT
or VSS
All Inputs
-100p.A
10
10
1.6mA
=
=
AC Characteristics
TA = O°C to +70°
VSS
OV, VCC
+ 5 ± 0.25V
=
=
Table 4. WD193X AC CHARACTERISTICS
-00,
Symbol
Parameter
TAS
TAH
TCSS
TCSH
READ & WRITE
Address Set-Up
Address Hold
Chip Select Set-up
Chip Select Hold
TRED
TDV
TDROIR
TINTROF
TRE
READ
Data Delay from RE
Data Valid from RE
DROI Reset Delay
INTRO Reset Delay
RE Pulse width
WRITE
DataSet-up
TDS
Data Hold
TDH
TDROOR DROO Reset Delay
WE Pulse width
TWE
Min
-10
-~01,
Max
Min
-02,
-12
-03,
-13
Max
Min
Max
Min
Max
20
20
20
20
20
20
20
20
0
-11
315
140
280
280
0
290
140
0
280
265
140
0
280
280
325
300
275
250
200
20
180
20
160
20
140
20
330
330
330
180
200
ns
ns
ns
ns
20
20
20
20
20
20
20
20
160
240
140
280
280
330
CLOCK
1XCIock
.5
1.0
1.5
2.0
32xFc
32XCIock
1.0
1.5
2.0
2.5
TR
TF
RISE & FALL
Rise Time
Fall Time
20
20
20
20
20
20
20
20
480
ns
ns
ns
ns
ns
ns
ns
ns
140
1xFc
NOTE: All A.C. Timing Measurements made at 0.8V and 193X .
Units Conditions
MHz at 50% duty
cycle
MHz at 50% duty
cycle
ns
ns
See figure 1
_
_ _ _H_IG_H_I_M_P_S_T_Al_"E_ _-<
Part No.
WD193X*·OO
WD193X*·10
WD193X*·01
WD193X*·11
WD193X*·02
WD193X*·12
WD193X*·03
WD193X*·13
Loop Mode
Maximum
Data Rate
no
yes
no
yes
no
yes
no
yes
500KBPS
500KBPS
1.0MBPS
1.0MBPS
1.5MBPS
1.5MBPS
2.0MBPS
2.0MBPS
Temp. Range
O°Cto
O°C to
O°C to
O°C to
O°C to
O°C to
O°Cto
O°C to
+ 70°C
+ 70°C
+ 70°C
+ 70°C
+ 70°C
+ 70°C
+ 70°C
+ 70°C
* Please contact your local Western Digital Sales Representative for package availability and price information.
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
484
Printed
In
U S.A
WESTERN DIGITAL
o
c
R
p
o
R
A
T
/
o
N
WD1931/WD1933 Compatibility Application Notes
and reception. The only work that the computer is required
to do is to initialize and write data characters to/from the
WD1931 or WD1933. These devices will take care of the
serialization or deserialization of this data, plus control and
timing.
INTRODUCTION
The purpose of this document is to provide the reader with
information about the WD1931 and WD1933 devices, and
how to take advantage of their compatibility. Various applications examples are given showing flowcharts and timing
diagrams. As the devices are designed for use in a very large
range of applications, many different features are described
and illustrated for the benefit of the reader.
Some control signals on the computer side of the devices are
needed for read, write, and control purposes. Additional signals can also be used for special purposes or modes for the
convenience of the user. Typically, these other control signals are used to enable communication with a modem or
DCE (Data Communications Equipment).
For detailed product information such as A.C. and D.C. parameters, please refer to the respective data sheets.
Interrupt outputs are provided to inform the microcomputer
when to retrieve from, or to provide data to the hold ing registers. Also, interrupts can be generated to provide status information such as changes in modem control lines, or that
events such as Transmission Complete or Received End of
Message have occurred.
GENERAL DESCRIPTION
The WD1931 and the WD1933 are MOS/LSI devices which
interface a parallel digital system to a serial data communication channel (and vice versa). Both circuits are
capable of simplex, half duplex, and full duplex operation.
The WD1931 is designed for character-oriented asynchronous and/or synchronous (BI-SYNC) protocols. The WD1933
is designed for bit-oriented SDLC, HDLC and ADCCP protocols. The devices are programmable and compatible to
most a-bit microcomputers on the market. The pin assignments of these two devices have been chosen to allow the
user to implement a one-board multiprotocol design. This
board may then be used for any of the above mentioned protocols, by choosing the proper device (WD1931 or WD1933)
and connecting some jumpers (see paragraph entitled "Multiprotocol Board Design"). The purpose of these circuits are
to convert parallel data from a computer or terminal to a serial data stream at one end of a communication channel. At
the other end of the channel, the data is converted back to
the original parallel data.
SYSTEM APPLICATIONS
WD1931/33 may be used in the following applications:
Switched network
Multipoint network
Non-switched point to pOint network
Simplex, half-duplex, or full duplex
Asynchronous or synchronous communication
Message switching
Multiplexing systems
Data concentrator systems
Loop data link systems
DMA applications
Parallel to serial data conversion (and vice versa)
Local Networks
Packet Switching
X.25
Multidrop line systems
Serial data communications minimizes the number of physical channels required to transfer data and therefore reduces
the cost to send data between two (or more) distant points.
A microcomputer could perform the same serial/parallel
conversion function as these devices, but at much slower
speeds. However, using the WD1931 and WD1933 devices
to do this function is much more efficient. This makes the
computer free to perform other tasks during transmission
A typical block diagram of a data link is shown in Figure 1.
The communication media used could be a direct communication channel (such as a leased telephone line), a switched
telephone line, or one of many other possibilities. Typically
these applications would require the use of a modem.
MUL TIPROTOCOL
MUL TIPROTOCOL
BO
BO
(W01931/1933)
(W01931/1933)
'---____________
,~------------~v~--------------~
~~---------------J
STATION B
STATION A
Figure 1. DATA LINK BLOCK DIAGRAM
485
:E
c
......
<0
CN
......
~
C
......
<0
CN
CN
The applications that these devices could be used in would
be a combination of the previously mentioned. A modem
would be needed for long distance communication lines. For
shorter distance, line drivers/receivers may be sufficient. In
some very well contralled environments, such as a laboratory, two devices may be connected without line drivers and
receivers.
between a 280 microcomputer and a modem. This is called
a multiprotocol board, which is described later in this
document.
Some examples of various WD1931/WD1933 systems are
shown here by use of block diagrams. The station shown in
Figure 3 consists of a computer or terminal, a multiprotocol
board, and a modem. A station may consist of only the computer or terminal, and one WD1931 or WD1933 device.
Whether the modem, Iine drivers and receivers, or CPU buffers are needed depends on the details of the particular design situation.
The WD1931 or WD1933 may be connected directly to a microcomputer bus, but buffers would normally be recommended. Figure 2 shows a typical schematic of an interface
EIA RS·422
LINE DRIVER/RECEIVER
BUFFERS
W01!'33/W01931
~
Dffi~17~________-G~~~-----
t------:-I ~
8
DO
01
02
03
RfS
t-----'~7-i~ ~
TO
OTR
1-3::::;2_ _ _ _ _--1
RTS
25
TO
MTsCouf 1-"-5- - - - - - - - 1
04
05
06
07
12
13
D5
15
DB
i5'i
,.
CPU
BUS
22
23
21
AD
Al
A2
D'
GNO
DSR
33
CTS
29
RO
27
Ai
34
A
B'
A
B'
B'
A'
A
AD
.ill
A2
We
16
CD
M-R
(, 12V)
l·BO
COMPUTER
OR EOUIV
MiSe TN
RC
------------------",;H: ~;~~
PIO
PORTS
r
l
RSCLK o--«,.5B
:=f@~
4B
5
lA
6
2A _
CLOCK
INPUTS
18
~B
i~~~
A'
TC
30
B
1X,32X (RSCLK)
fifo (R2)
35
FIf; (R')
38
eOOIF14)
.....----'3"-7~
CDl
RE
Cs
36
.::::D-
Rev
Ifl3)
CS
cs
Figure 2. WD1931/1933 AND MICROCOMPUTER. (MULTIPROTOCOL BOARD)
486
CD
RC
'NRZI(rBOC)
~~
,SA
RI
MISC IN
GNO
EOB
TBOCOo-&el?
RO
A
B'
A
r=--------I
PBO
PBl
_ _ _ _ _ _ _ _ _ _ _ _ _ _';.;;.9-/0ROI
PB2
PAD
OSR
CTS
GNO
RE
RO
WR
RESET
MISC OUT
TO MODEM
(OCE)
........................................................................
TELEPHONE
END
OFFICE
A
~
STATION
A
\~
_IL_
'-'
TELEPHONE
END
OFFICE
r+-+
STATION
B
B
________~y~________---J
TELEPHONE/DATA COMM.
SWITCHING NETWORK
SWITCHED NETWORK
~ ST._~_~~_N ~~I·~
__
__
____________________~~~~__ST._A~_IO_N ~
__
~
______
~·~I~ S_T._~_IO_N ~
__
__
MULTIPOINT NETWORK
~----------G
STA!IONI....
NONSWITCHED POINT TO POINT NETWORK
Figure 3. TYPICAL NETWORKS
487
LOOP DATA LINK SYSTEM
DATA COMMUNICATIONS EXAMPLE NO.1
The Loop Mode is used in SDLC only. A loop data link system consists of one primary station (Loop Controller), and a
number of secondary stations all functioning normally as repeaters. Figure 4 illustrates a typical Loop Data Link system.
The diagrams below (Figures 5 and 6) illustrate a typical digital system employing several processing levels and digital
communications protocols. It is flexible enough to satisfy
several applications. For example, the host processor and
remote terminals could be located in airline reservation offices and ticket counters, travel centers and travel agencies,
central bank offices and branch banks, or department stores
and individual cash registers. The exploded diagram of the
Data Communications Controller exemplifies the use of one
common circuit board design with eight multiprotocol circuits. When one port requires a character-oriented protocol
(asynchronous, character oriented synchronous, or bisync),
the WD1931 is installed into the appropriate socket. For
SDLC, HDLC or ADCCP, the WD1933 is used.
Any secondary station finding its address in the address field
captures the frame for action at that station. All received
frames are relayed to the next station down the loop.
A secondary station is allowed to suspend the repeater function and initiate its transmission when a Go-Ahead pattern is
received.
PRIMARY
STATION
SEC.
STATION
SEC.
STATION
A
N
SEC.
STATION
SEC.
STATION
D
B
SEC.
STATION
C
Figure 4. LOOP DATA LINK SYSTEM
488
LINE
PRINTER
DATA
CONCENTRATOR
.•
•
DISK
:.
ti
-..II.-
NOTE 1
-ftj-'
't!8~
~~b ~~
-
O~~
ii:
t
.... a:
~~ ~
I
I
t
~
!!z
8
a:
j!:
~ti~
t
« ....
Offlt)
«~
~a:
~b
11([<11(
°~
NOTE 1. COMPUTER TIME MAINLY.
NOTE 2. DATA SET READY RESPONSE TIME PLUS TIME TO NEXT
. NEGATIVE TRANSITION 0I'""'rn.
NOTE 3. COMPUTER TIME PLUS TIME TO NEXT NEG. TRANS. OF""TC.
NOTE 4. MODEMS WITH DSR PERMANENTLY ON, WILL NOT SET INTRa
HERE.
NOTE 5. THIS TIME - 2 TC (2 CLOCK PULSESI, IF CTS RESPONSE", ¥J TC.
Figure 16. TIMING DIAGRAM OF FRAME TRANSMISSION
WD1933 TRANSMISSION EXAMPLE 2
(DMA APPLICATION)
The WD1933 Is very efficient for DMA applications. The
control registers are loaded to initiate the WD1933 for DMA
mode in the same way as in Transmission Example 1. The
Auto Flag bit is set, and the Transmitter Command is
"DATA" (CR14 and CR15 bits = (0). The procedure to set
up the link (initiate transmit mode and data set ready) is the
same as in Transmission Example 1. When INTRa is set
and the Transmitter is activated, the DMA Controller Board
takes over the control. From this time on, the DMA Con·
troller Board responds on every DRaO (Data Request Out).
When the last character is transmitted and the INTRa is
received, the control is switched back over to the CPU.
A very important feature of the WD1933 is the EOB (End of
Block) input. Instead of using the normal (time-consuming)
method of writing into a control register to start the FCS
(Frame Check Sequence), the EOB input is activated at this
time. At the next occurrence of INTRa, the EOB signal is
deactivated.
An example of a schematic/block diagram is shown in
Figure 17, and a timing diagram is shown in Figures 18
through 20.
498
~~.--~--.
DATA BUS
DATA BUS
DATA BUS
1------"iAO
Al
00·07
(NOTE)
OTA
1-------JA2
--
~=:===::::~ ~~~O
I+---_ _ _--I
r--
r---
AD f - - AO f - - tc f - - Alf--CO
MISCIN f - - -
0AOI
f-
, - - - - - - . . / NAZI
,------.,1>1
..-_ _-..I
"XXl32X
A10
MiSC out
-;:=:
~O
----+-
ADDRESS BUS
CONTROL SIGNALS
r---
OSA
ATS
cfS f - - -
At
I------~WE
TO
LINE
DRIVERSI
RECEIVERS
I---I----
CDl
r l....M_A_ _ _ _--J
I~--------------~
NOTE: IF ACTIVE HIGH (1 = HIGH) TYPE DATA BUS.
USE DATA BUS INVERTERS
Figure 17. BLOCK DIAGRAM OF DMA APPLICATION
1ST FRAME
f,",enod"O
~
~
___~.~I~.~___.'~I~I_C_O_NT_A_~'~1~1~1N_F_O_~A
100100011111010100001111110
_ _.~r------
-!
' -_ _- - - I ' -_ _
J:
l-
cc
cc
•
1=
cc
a
ac(
I-
L-_ _--!
~F~CS_ _ _ _~'~l~i
___~.1
~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _
____'fL
I
n
I
I
I
I
I
I
I
•
cc
Z
8
Figure 18. DMA TIMING OF FIRS'r FRAME
499
:e
c......
FRAMES BnWEEN
1ST AND LAST FRAME
CC
(,,)
......
IL
~
c......
I.
-.I
.Ie
.1.
n
L-
I
I
I
I
I
1
CC
(,,)
(,,)
DfR
-i.I
JL
AOOR
INF DATA
---u---L
.j
.\
.
·1·
Il
I
I
!
l
l
Ita
r::ii
a:.-'.
IW
t
I~ t ~
r~
t~
w
en
w
a:
~~i
u.
a:_
Iw
r
Iwa: r
~
0
I
I
I
a:
I
r
I
n
~~
~~
U
;!;
Figure 19. DMA TIMING OF MIDDLE FRAMES
END FRAME
TO
I
•
"_
AoDR
I
m---u---
L.S
'I
INF OATA
I
________
...I
.1.
I
~~~I~~NTA
••
__--In'--_---J
__________
I
~
_________________
I
~n~
.,
CPU
TIME
_____
I
__
I --:-_____I_---'r -~
l
Figure 20. DMA TIMING OF LAST FRAME
:500
.......................................................................
WD1933 RECEPTION EXAMPLE 1
character, and two residual bits. This example may not be a
typical frame, but it shows how the WD1933 works in a wide
range of frame structures.
A sequence of events is shown in illustrating how to receive
a message with the WD1933 device. For simplicity, the same
SDLC frame structure is used as in Transmission Example
1. Also, please refer to the same interface circuitry shown in
Figure 2.
The first FLAG and FCS are not shown in detail, and are not
critical to this example.
Figure 23 illustrates the functional flow, and Figure 24 contains the timing information.
Figure 21 illustrates the functional flow, and Figure 22 contains the timing information.
WD1933 LOOP DATA LINK EXAMPLE
This example shows how to program a secondary station
to function in SDLC Loop mode. The functional flow is
illustrated in Figure 25, and the interface circuit is shown in
Figure 2.
WD1933 RECEPTION EXAMPLE 2
This example shows a frame with two ADDRESS characters,
two CONTROL characters, one 5-bit INFORMATION DATA
FLOWCHART
INITIATE
DATA SET READY
RECEIVE MODE
1ST INTERRUPT
DTE AND DeE
IDLE
PORT A
PORT B
~
~
OUTPUT
INTERRUPT
INPUT
ACTIVATE
MR MOMENT.
CONFIGURE
PIO.
READ IR.
ENABLE
INTERRUPT
PA,., ~ 01111111
PBO/PB2 (INTRQ/DRQI)
~ INTERRUPT
NO
ERROR
ADDRESS--->AR
WRITE
ADDRESS INTO
AR REG.
EXAMPLE: AR
~
33H
DATA SET READY
DATA TERM. FlEADY
COMPUTER
DOING OTHER
TASKS
SET ADDR.
COMPARE
AND DTR
CR2 ~ 01000000
CRl ~ 00000010
ACTIVATE RECEIVER
COMPUTER
DOING OTHER
TASKS
Figure 21. FLOW DIAGRAM OF FRAME
RECEPTION (EXAMPLE NO.1)
501
SET
ACT REC
BIT
CRl
~
10000010
::e
c
.....
.....
~
CD
CN
C
.....
CD
CN
CN
RECEIVE DATA
INTERRUPT NO. 2-N
(ADDRESS MATCH)
READIR.
ENABLE
INTERRUPT.
NO
(ERROR)
READ SR REG.
BITS 0-2
TO FIND
OUT WHAT
TYPE OF
ERROR
COMPUTER
DOING OTHER
TASKS
REMOVE
LAST TWO
CHAR. RECEIVED
READ SR
REGISTER
BITS 0-2
YES
SAVE RESIDUAL
BITS, BUT
MASK OUT THE
OTHERS IN
LAST CHAR.
NOT REMOVED
Figure 21. FLOW DIAGRAM OF FRAME RECEPTION
~i02
11(:
(IX CLOCK)
n
L-----.fI
I
I
I
I
I
I
j
I
I
~~~
~l'lli
a:!!'
n~
a:!!'
NOTE 1. DATA SET CHANGE INTERRUPT
NOT SHOWN HERE.
NOTE 2. PROGRAMMED ADDRESS (IN AA REG) "" 33H
Figure 22. TIMING DIAGRAM OF FRAME RECEPTION (EXAMPLE NO.1)
503
:ec
.....
FLOWCHART
INITIATE
RECEIVE MODE
CD
CN
.....
~
C
.....
CD
CN
CN
PORT A = OUTPUT
PORT B = INTERRUPT
INPUT
ADDRESS 1 INTO AR
MOMENTARILY
ACT:V. F:m.
CONf'IGURE
PIO
WRITE
ADDRESS 1
INTO AR
REGISTER
PA7~O = 0111 1111
PBO/PB2 (INTRQ/DRQI) = INTERRUPTS
EXAMPLE: AR = 1CH
PROGRAM
EXTENDED CONTROL
ADDRESS COMPARE
EXTENDED ADDRESS
RECEIVE CHAR. LENGTH
= 5 BITS
DATA TERM. READY
SET EXT
CONTR, ADDR.
COMP, EXT
ADDIl AND
RCL = 5
SET
DTR
CR2 = 11111000
CRl
=
00000010
COMPUTER
DOING OTHER
TASKS
DATA SET READY
1ST INTERRUPT
(DATA SET CHANGE)
ACTIVATE
RECEIVER
COMPUTER
DOING OTHER
TASKS
SEE DATA SET
READY IN
RECEPTION EXAMPLE 1
d~
Figure 23. FLOW DIAGRAM OF FRAME RECEPTION (EXAMPLE NO.2)
504
•
:ec
.....
INTERRUPT NO. 2-N
(ADDRESS MATCH)
CD
W
.....
i:c
.....
READ IR.
ENABLE
INTERRUPT
YES
CD
W
W
NO
READ RHR
(ERROR)
EX.
IS
B3H
RECONFIGURE
COMPUTER
PIO TO IGNORE
ORal (ADDR.
2 MISMATCH)
CALCULATE
NO. OF RESIDUAL BITS
(SEE RESIDUAL
BIT CALCULATION NEXT
PAGE)
COMPUTER
DOING
OTHER
TASKS
Figure 23. FLOW DIAGRAM OF FRAME RECEPTION
505
=e
c......
co
CN
......
~
RESIDUAL BIT CALCULATION
THIS CALCULATION
NEEDED ONLY WHEN
RESIDUAL BITS MAY BE
RECEIVED IN A
NON-8-BIT CHARACTER
SUBTRACT
THE FLAGBITS IN THE
LAST RECEIVED
CHARACTER
C
......
co
CN
CN
ADD THE
REMAINDER
OR SUM
WITH THE
CHARACTER
BIT LENGTH
NO
THIS REMAINDER
IS THE NO. OF
RESID. Bll'S
Figure 23. FLOW DIAGRAM OF FRAME RECEPTION
••
{lCHI
•
I
I
n
(B3HI
I
'I
n
«
I
•I
I
~
I
:,T:
I
I
__~~____~L
_ _~L_ _~L_ _~L_ _~I_ _~
__~I~I~I_~~~~~l
!
l
l
l
Figure 24. TIMING DIAGRAM OF FRAME RECEPTION (EXAMPLE NO.2)
!i06
=e
FLOWCHART
INITIATE LOOP
c....
MODE
(
CD
W
START)
....
~
ADDR---+o AR
Km.
PA,_o = 01111111
PB,_o = INTERRUPT (DROI, DRQO, INTRa)
CONFIGURE
PIO.
AR = 00110011
CR3 = 00000000
CR2 = 01000101
SET DTR
BIT
CR1 = 00000010
(
~
)
WAIT
RECEIVE DATA (ACT TRAN BIT
1ST INTERRUPT
INTERRUPT 2-N
(ADDRESS COMPARED
AND MATCHED)
( INTET'" )
=0)
INTERRUPT)
(
SEE TIMING
DIAGRAM FIG. 22
SEE DATA SET
ACTIVATE
RECEIVER
COMPUTER
DOING OTHER
TASKS
READY IN
RECEPTION EXAMPLE 1
FLOWCHART
cb
CR1
=
1000 0010
SEE RECEIVE DATA
IN RECEPTION EXAMPLE 1
FLOWCHART
REPEA'ER MODE
(
END OF RE-)
CEIVE DATA
Figure 25. FLOW DIAGRAM OF SOLe LOOP MODE OPERATION
507
....C
CD
W
W
WRITE ADDRESS
INTO AR REG.
SET ADDR. COMP,
LOOP MODE,
AUTO FLAG
DATA TERM READY
COMPUTER
DOING OTHER
TASKS
~
MOM. ACTIV.
PORT A = OUTPUT
PORT B = INTERRUPT
INPUT
TRANSMISSION""
REQUEST
V
ACTIVATE TRANSMITTER
(SECONDARY STATION IS STILL FUNCTIONING AS A REPEATER,
RECEIVING DATA WHEN ADDRESSm, BUT IT IS NOW ALSO
WAITING FOR A GO-AHEAD PATTEFiN FROM PRIMARY
STATION TO BE ALLOWED TO TRANSMIT)
INTERRUPT 2 - N
(ACT TRAN BIT = 1).
NO
(REOM
ERROR)
READ SR REG.
BITS 0·2
TO FIND
OUT WHAT
TYPE OF
REOM ERROR
YES
SAVE RESIDUAL
BITS, BUT
MASK OUT THE
OTHERS IN
LAST CHAR.
NOT REMOVED
Figure 25. FLOW DIAGRAM OF SDLC LOOP MODE
APPENDIX
CONCLUSION
RELATED DOCUMENTS
The WD1931 and WD1933 devices are highly compatible, which allows the design of a multi protocol
communications board. This compatibility allows the
use of asynchronous, character oriented synchronous,
and bit oriented synchronous communications protocols with the same 40 pin socket.
WD1931 Data Sheet, Western Digital Corporation
WD1933 Data Sheet, Western Digital Corporation
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
508
Printed In USA
WESTERN DIGITAL
CORPORATION
WD1993 Arinc 429 Receiver/Transmitter
and Multi-Character Receiver/Transmitter
FEATURES
•
PRESENT UPON MASTER RESET FOR ARINC 429
PROTOCOL
•
PROGRAMMABLE WORD LENGTH FROM 1 CHARACTER TO 8 CHARACTERS
•
PROGRAMMABLE CHARACTER LENGTH, 5, 6, 7,
OR 8 BITS
•
• SINGLE +5 VOLT SUPPLY
• TEMPERATURE RANGES O°C to 70°C, - 1993-03,
- 40°C to + 85°C - 1993-02, - 55°C to + 125°C 1993-01
INTRODUCTION
The Western Digital WD1993 Avionic Receiver/Transmitter
is designed to handle digital data transmission, according to
the Avionic Arinc 429 protocol. Also, the word length is programmable from one to eight characters of 5, 6, 7, or 8 bits.
Parallel data is converted into a serial data stream during
transmission. and serial to parallel during reception. The
WD1993 is packaged in a 28 pin plastic or ceramic package
and is available in three temperature ranges: Commercial,
Industrial and Military.
RETURN TO ZERO (RZ) OUTPUT
• AUTO SPACE GENERATION
• DOUBLE BUFFERED RECEIVER AND TRANSMITTER
• UNDERRUN ERROR DETECTION FOR TRANSMISSION
• OVERRUN, FRAMING AND PARITY ERROR DETECTION ON RECEIVER
• WORD ERROR FLAG FOR COMPREHENSIVE
ERROR REPORTING
GENERAL DESCRIPTION
The WD1993 is a bus-orientated MOS/LSI device designed
to provide the Avionics Arinc 429 Data Communication Protocol, along with programmable character length capabilities.
• FIRST CHARACTER OF WORD FLAG FOR SINGLE
INTERRUPT APPLICATIONS
• DIAGNOSTIC LOCAL LOOP-BACK TEST MODE
•
Also, the WD1993 contains a local loop-back test mode of
operation, which is controlled by the Loop Test Enable (LTE)
bit in the command register. In this diagnostic mode, the
transmitter output is "looped-back" into the receiver input.
The REN and TEN control bits must also be active ("1") and
the CTS input must be low. The status and output flags operate normally.
DC TO 200 KILOBITS PER SECOND OPERATION
• TTL COMPATIBLE INPUTS AND OUTPUTS
vss
RE
WEF
c/o
rn
Cs
TXC
WE
N.C.
07
MR
06
TXE
05
RXROY
04
TXROY
03
TXDO
02
TXOI
01
RXC
00
FCR
RXOI
RXDO
VCC
os
Ae
WE
Figure 1 PIN DIAGRAM
REAON'RITE
GONTAOI..
cli5
Figure 2 WD1993 BLOCK DIAGRAM
509
:E
C
.....
CD
CD
~
PIN NO.
SYMBOL
FUNCTION
SIGNAL NAME
1
VSS
GROUND
Ground
2
WEF
WORD ERROR
FLAG
This pin is an output, which when active indicates an error
in either the transmitter or receiver has been detected. It
reflects an underrun, overrun, parity or framing (receive
word) error and is intended as an error interrupt. The
Status Register should be read to determine the specific
error.
3
CTS
CLEAR·TO-SEN D
This input is activated (VIU to enable the transmitter
logic.
4
TXC
TRANSMIT CLOCK
This input is the source clock for transmission. The data
rate is a function of this clock frequency.
ARINC MODE = 4 x bit rate
5
N.C.
6
MR
MASTER RESET
When active (VIH), presets the WD1993 mode and
command registers to the ARINC protocol. Master Reset
also resets the data registers and places the WD1993
transmitter and receiver into idle states. After MR, the
command register is set to 00100101 and the mode
register is set to 00111100.
7
TXE
TRANSM ITTER
EMPTY
This output goes high to indicate the end of a transmit
operation. TXE is automatically reset after the Transmit
Holding Register is loaded.
8
RXRDY
RECEIVER READY
This output, when high, alerts the CPU that the Receiver
Holding Register contains a data character that is ready
to be input. This output is automatically reset whenever a
character is read from the WD1993. RXRDY is enabled
unless inhibited by setting command bit CR3 (RXRDYIN)
to a logic "1." It is automatically enabled again after a
receive sequence is completed.
9
TXRDY
TRANSMITTER
READY
This output, when high, alerts the CPU that the Transmit
Holding Register is ready to accept a data character. The
TXRDY output is automatically reset whenever a character is written into the WD1993 and can be used as an
interrupt to the system.
10
TXDO
TRANSMIT DATA
ZERO
This output drives the VIZ circuit when a logic zero is to
be transmitted and is active for one-half bit time.
11
TXD1
TRANSMIT DATA
ONE
This output drives the VIZ circuit when a logic one is to be
transmitted and is active for one'half bit time.
No Internal Connection
510
•
PIN NO.
SYMBOL
SIGNAL NAME
FUNCTION
12
RXC
RECEIVE CLOCK
This input is the source clock for reception. The data rate
characteristics are the same as the transmit clock.
13
FCR
FIRST CHARACTER
READY
This output goes high after the receiver has completed
reception of the first character in a multi-character
sequence.
14
RXDO
RECEIVE DATA ZERO
RXDO is driven by the line VIZ receiver circuit. When the
VIZ circuit detects a logic zero, a TTL logic one (active for
one-half bit time) is provided to the WD1993.
15
VCC
POWER SUPPLY
+5VDC
16
RXD1
RECEIVE DATA ONE
The RXD1 input is driven by the VIZ line receiver. Each
time the VIZ circuit detects a logic one, a TTL level logic
one (active for one-half bit time) is provided to this input.
17
18
19
20
21
22
23
24
DO
D1
D2
D3
D4
D5
D6
D7
DATA BUS
This is the bi-directional data bus. It is the means of
communication between the WD1993 and the CPU.
Control, Mode, Data and Status Registers are accessed
via this bus.
25
WE
WRITE ENABLE
When active (VIU, allows the CPU to write into the
selected register.
26
CS
CHIP SELECT
When active (VIU, the device is selected. This enables
communication between the WD1993 and a microprocessor.
27
C/O
CONTROL/DATA
This input is used in conjunction with an active read or
write operation to determine register access via the DATA
BUS.
28
RE
READ ENABLE
When active (VIU, allows the CPU to read data or status
information from the WD1993.
_1________________________________________________________________
511
ORGANIZATION
:ec
......
co
co
w
A block diagram of the WD1993 is shown in figure 2.
As mentioned, the WD1993 is an eight bit bus-oriented
device. Communication between the WD1993 and the controlling CPU occurs via the a bit data bus through the bus
transceivers. There are 2 accessible data registers, which
buffer transmit and receive data. They are the Transmit Holding Register and the Receive Holding Register. There is a
parallel-to-serial shift register (parallel in-serial out), the
transmit register and a serial-to-parallel shift register (serial
in-parallel out), the receive register.
Operational control and monitoring of the WD1993 is performed by two control registers (the command instruction
register and the mode instruction register) and the status
register.
The Command Register is used to select features such as
parity options, loop test capability, RXRDY flag enabling,
transmitter and receiver enabling, and may also cause the
WD1993 to return to the Mode instruction.
The Mode Register is used to select features such as bits/
character and characters/word.
The Status Register contains information such as Transmitter Ready, Transmitter Empty, Receiver Ready, error conditions, and First Character Ready.
OPERATING DESCRIPTION
The WD1993 is primarily designed to operate in an a bit
micro-processor environment, although other control logic
schemes are easily implemented. The DATA BUS and the Interface Control Signals (CS, RE, WE and C/O) should be
connected to the microprocessor's data bus and system control bus.
A read/write control circuit allows programming/monitoring
or loading/reading of data in the control, status or holding
registers by activating the appropriate control lines: Chip Select (CS), Read Enable (~E), Write Enable (WE),and Control
or Data Select (C/O).
The appropriate TXC and RXC clock frequencies should be
selected for the particular application, using a programmable
baud rate generator such as a BR1941. A master reset pu Ise
initializes the WD1993 and presets the control registers to
the ARINC protocol.
Internal control of the WD1993 is by means of two internal
microcontrollers; one for transmit and one for receive. The
control registers, null detect logic and various counters,
provide inputs to the microcontrollers which generate the
necessary control signals to send and receive serial data ac-·
cording to the Arinc 429-1 protocol, along with the programmable multicharacter capabilities.
The RXD1/RXDO inputs are interfaced to the DITS data line
via external level translators that provide TTL (5V) logic levels to the WD1993. The TXD1/TXDO outputs are connected
to high voltage (± 10V) driver circuits. Figures 16 and 17
show some typical ± 10V translator and driver circuits.
The TXRDY, RXRDY, FCR and WEF Flags may be connected to the microprocessor system as interrupt inputs. The
status register can be periodically read in a polled environment to support WD1993 operations.
OPERATION
Upon master reset (MR), the device is programmed to transmit and receive four a-bit contiguous characters with the
32nd bit odd parity. (ARINC protocol.)
rn
input can be used to synchronize the transmitter to
The
external events.
A minimum four bit time space is automatically inserted after
the character transmission. Two receiver inputs, RXD1/RXDO
and two transmitter outputs, TXD1ITXDO, are provided to interface with voltage-impedance (VIZ) circuits to translate
± 10 volt ARINC line levels to 5 volt TTL logic levels. The
transmit clock (TXC) and receive clock (RXC), in ARINC
mode, are four times (4X) the bit rate desired.
The WD1993 is designed such that a control register write
operation accesses the command instruction register.
The RXRDYIN bit of the command register is used to inhibit
the RXRDY output pin for ARINC operations.
The receiver monitors the received data input to detect a four
bit time nUll, which delimits the word. If the communications
link is broken during a word reception, the receiver will generate a word error flag to (WEF) to notify the CPU to request
retransmission. When a null is detected, the receiver logic is
reset and returned to an idle state awaiting the next word.
MULTI-CHARACTER OPERATIONS
The WD1993 may also be programmed to support a multiple
character word consisting of from one to eight characters.
Also, the character length is programmable from 5 to a bits,
and the parity bit if parity is used, may be either inside or outside the word.
512
As discussed above, the WD1993 is equipped with a multicharacter option which provides the user with the means of
transmitting and receiving multiple contiguous characters
of data within one set of delimiters-4 bit nulls for ARINC
429. Since the WD1993 is an a bit bus-oriented device, the
controlling processor must read the WD1993 data from its
holding register before the subsequent characters are assembled. This situation also exists on the transmit side, i.e.,
the Transmit Holding Register must be loaded before the
previous a bits are completely shifted out of the transmit
register.
Several "flags" are provided for interrupt purposes so that
continuity is maintained and data integrity is preserved.
These flags are First Character Ready (FCR), Receiver Ready
(RXRDY), Transmitter Ready (TXRDY) and Transmitter
Empty (TXE).
The Transmitter operates as follows:
a) With the mode and command registers programmed
as desired, the transmitter is enabled, TEN (CRO) =
"1" .
b) The TXE and TXRDY flags are "1" (active).
c) The external CTS signal = "0".
d) The CPU loads data into the Transmitter Holding Register, TXE and TXRDY go Low.
e) The data is loaded into the transmit register and TXRDY
goes high. This indicates the first data word is being
sent and a character can be loaded into the holding
register. If the WD1993 is programmed for more than
one character (multi-character) then an underrun error
will be generated if the next character is not loaded before the previous word is completely shifted out, unless
the current character is the last character in a sequence.
f) If the last character is transmitted and no more new
data is to be sent, the transmitter will indicate its status
by raising the TXE flag. (No error is generated as a result of this condition.)
LOOP TEST MODE
As mentioned, the WD1993 is equipped with a diagnostic
test mode, local loop-back. This mode is activated by setting
the LTE command bit to a "1". The TEN and REN bits shou Id
be "1" and CTS should be "VIL" The receiver inputs are ignored and the transmitter outputs are sending nulls. The
transmitter is internally "looped-back" to the receiver and the
error and status flags operate normally.
For basic testing, failing to reload the Transmit Holding Register in the middle of a data send sequence will cause an underrun error in the transmitter and a word error in the receiver. Failure to read the Receive Holding Register after a
FCR or RXRDY flag will cause an overrun error to be
generated.
For Loop-Back test operations, the user should be sure that
the TXC and RXC clock frequencies are the same. This is
normally implemented by placing the same clock signal on
both pins (TXC and RXC).
ARINC BACKGROUND
Aeronautical Radio Inc. (ARINC) publishes the ARINC 429
specification. This document defines the air transport industries standards for the transfer of digital data between avionics systems elements. This specification was adopted by The
Airlines Electronic Engineering Committee April 11 ,1978. By
the adoption of this specification the foundation is set for a
standard protocol governing all intersystems equipment (Line
Replaceable Units).
The Receiver operates similarly:
a) With the control registers suitably programmed, the receiver is enabled, REN (CR2) = "1 ".
b) The RXRDY and FCR flags are "0". (Inactive).
c) The incoming data word activates the receive logic and
the data begins to be assembled in the receive register.
d) When the first character is completely assembled, the
data is loaded into the Receive Holding Register, the
FCR (First Character Ready) and RXRDY (Receiver
Ready) flags become active, "1". The CPU should
read the data prior to the reception of the next character or an overrun error will be generated as the receiver
will ove·rwrite the old data with the new data character
just received.
The exception to this is in the ARINC mode, where the
first character in the ARINC protocol contains a label.
The FCR and RXRDY Flags become active to indicate
the reception of the first character of data. The CPU
reads the first character and decides whether or not it
wants to acquire the subsequent characters. If not,
then the CPU performs a "control write" to the COMMAND REGISTER, setting the RXRDYIN (CR3) bit to
a "1". This bit in ARINC mode, inhibits the RXRDY flag
from interrupting the CPU during the reception of the 3
remaining characters. The RXRDYIN bit is then automatically reset upon completion of the receive sequence and RXRDY is enabled again.
.513
MARK 33 DIGITAL INFORMATION TRANSFER
SYSTEM (DITS)
Basic Philosophy
Transmit from a designated output port over a single
twisted and shielded pair of wires to designated receiver.
Bidirectional data flow not permitted on a given pair.
Data Transfer
Numeric
Iso Alphabet # 5
Graphic
Data Format
32 bits or less (unused bit positions should be filled with
binary zeros or valid data pad bits).
Bit #32 is assigned to parity.
=e
C
.....
~
W
:ec
.....
co
co
w
Modulation
Return to Zero (RZ)
Transmit Voltage levels
high
+ 10
null
0
low
-10
Data Rate
100 kilo bit per second ± 1%
Low speed 12 to 14.5 kilo bit per second ± 1%
Word Synchronization
All zero gap of a minimum of 4 bit times
±O.SV
±O.SV
±O.SV
Receiver Voltage Levels:
(in absence
(noisy
of noise)
environment)
high +6.0V to + 10V
+S.OV to +13V
low
-6.0V to + 10V
-S.OV to -13V
No damage to receiver up to 20 vac rms between A &
B; +28, A to Gnd; -28, B to Gnd.
REGISTER DEFINITIONS
The format and definition of the Command Register is shown below:
CR7
CR6
CRS
CR4
CR3
CR2
EPS
IR
PEN
LTE
RXRDYIN
REN
TEN
PIA
TEN
Transmit ENable
1
0
Enabled
Disabled
PIA
Parity Inside or After
1
0
After the data word
Inside (the last data bit) of word
REN
Receive ENable
1
0
Enabled
Disabled
RXRDY Inhibit
RXRDYIN
Inhibit RXRDY output flag
0
Normal transmitter ooeration
enable RXRDY output flag
LTE
Loop Test ENable
1
0
Local loop-back mode
Normal Operation
PEN
Parity ENable
1
0
Enabled
Disabled
IR
Internal Reset
1
0
Returns WD1993 to mode instruction
format
-----
EPS
Even Parity Select
Even parity
Odd parity
1
0
514
The format and definition of the Mode Register is shown below:
=E
c
MR7
MR6
MR5
MR4
X
N3
N2
N1
MR3
MR2
MR1
CLS2
CLS1
X
MRO
...A.
CD
CD
W
Len~th
X
CLS2
CLS1
0
0
0
1
1
0
N3
N2
N1
Characters Per Word Select
0
0
0
0
0
0
0
1
1
0
1
1
1
1
0
0
1 character
2 characters
3 characters
4 characters
5 characters
6 characters
7 characters
8 characters
Character
5
6
7
8
1
1
Select
bits
bits
bits
bits
1
1
0
1
0
1
1
1
The WD1993 registers are addressed according to the following table:
CS
C/D
RE
WE
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
H
L
H
L
X
Registers Selected
Read Receive Holding Register
Write Transmit Holding Register
Read Status Register
Write Control Registers
Data Bus Tri-Stated
L = VIL at pins
H
VIH at pins
X = don't care
515
The format of the Status Register is shown below:
:E
c
.....
CD
CD
(,.)
SR?
SR6
SR5
SR4
SR3
SR2
UE
FCR
WEF
OE
PE
TXE
TXRDY
1
o
RXRDY
1
o
Receiver Ready
Active (RHR should be read)
Inactive
Transmitter Empty
Transmitter idle
Transmittor active
Parity Error
o
Error reported
No error
OE
Overrun Error
1
1
o
WEF
TXRDY
Active (THR can be reloaded)
Inactive (transmitter is busy)
1
PE
RXRDY
SRO
Transmittor Ready
TXE
o
SR1
RHR has been overwritten
No error
Word Error Flag
Indicates improper receive sequence (word error),
overrun error, parity error, framing error or underrun
error.
a
FCR
a
UE
a
No error
First Character Ready
This bit indicates the receiver has just completed assembly of the 1st character in a multi-character sequence and that the data is contained in the RHA.
First character not ready.
Underrun E.!:!:2!.
Indicates that the THR has not been loaded with a new
character in time for a contiguous data transmission
sequence.
No error
516
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
- 55°C to + 125D C (Plastic Package)
-65°C to +150°C (Ceramic Package)
Voltage on any Pin with Respect to Ground .. -0.3V to + 7V
Power Dissipation ............................. 400 MW
=E
c......
CD
CD
C".)
Note:
Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous
operation at these Iimits is not intended and shou Id
be limited to those conditions specified under DC
Electrical Characteristics.
DC ELECTRICAL CHARACTERISTICS
T A = O°C to + 70°C; VCC = 5.0V ± 5%; GND
SYMBOL
OV
PARAMETER
MIN
VIL
Input Low Voltage
-0.3
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VOH
Output High Voltage
IDL
MAX
TYP
IlL
Input Leakage
ICC
Power Supply Current
45
TEST CONDITIONS
0.8
V
VCC
0.45
V
IOL
V
10H
2.4
Data Bus Leakage
UNIT
V
50
uA
10
uA
10
uA
80
mA
= 1.6mA
= -100M-A
Data Bus is in
High Impedence
State
VIN = VCC
Vee = 5.25V
No Load
CAPACITANCE
TA = 25"C; Vee = GND = 0V
MAX
UNIT
Input Capacitance
10
pF
fC = 1MHz
I/O Capacitance
20
pF
Unmeasured pins
returned to GND
SYMBOL
PARAMETER
CIN
CI/O
MIN
TYP
+20
en
-S
+10
V
>-
«
-l
w
0
0
/
V
I-
:::>
a..
I-
:::>
0
-10
<1
-20
-100
/
I/
SPEC.
o
-50
~
/
+50
+100
CAPACITANCE (pF)
Figure 3 OUTPUT DELAY vs CAPACITANCE
517
TEST CONDITIONS
A.C. TIMIt~G PARAMETERS
SYMBOL
PARAMETER
MIN
MAX
UNIT
TEST CONDITIONS
BUS PARAMETERS
Read Cycle
(Reference Figure 6)
tAR
Address Stable before RE. (CS. C/O)
50
ns
tRA
5
ns
tRE
Address Hold Time for RE, (CS, C/O)
RE Pulse Width
tRD
Data Delay from RE
tRDH
RE to Data Floating
WRITE CYCLE
ns
350
200
ns
CL = 50pF
200
ns
CL = 50pF
25
ns
CL = 15 pF
ns
(Reference Figure 7)
tAW
Address Stable before WE
20
tWA
Address Hold Time for WE
20
ns
tWE
WE Pulse Width
350
ns
tDS
Data Set-Up Time for WE
200
ns
40
ns
tWDH
OTHER TIMINGS
Data Hold Time for WE
(Reference Figures 8, 9)
tOTX
TXD Delay from Falling Edge of TXC
ns
CL = 100pF
tSAX
Rx Data Set-up Time to Sampling Pulse
200
ns
CL = 100pF
tNAX
Rx Data Hold Time to Sampling Pulse
100
ns
CL = 100 pF
tTX
Transmitter Input Clock Frequency
tTPW
Transmitter Input Clock Pulse Width
tTPD
Transmitter Input Clock Pulse Delay
tAX
Receiver Input Clock Frequency
tRPW
Receiver Input Clock Pulse Width
tRPD
Receiver Input Clock Pulse Delay
500
4x
DC
4x
4x
4x
4x
kHz
500
ns
500
ns
DC
4x
800
800
kHz
500
ns
500
ns
ns
tTX
112
TXRDY Delay from center of Data Bit
518
tTXC
•
A.C. TIMING PARAMETERS
PARAMETER
SYMBOL
MIN
tTX
TXRDY Delay from Center of Data Bit
tRX
RXRDY Delay from Center of Data Bit (FCR
Delay from Center of Data Bit)
200ns
TXE Delay from Center of Data Bit
MAX
UNIT
TEST CONDITION
tTXC
2
1/2
RRXC
V2
tTxC
(4x)
CL = 50 pF
4 x Rate
-------~-.:-~~~~:-:-:-----------------~~~--------Figure 4 TEST POINTS FOR A.C. TIMING
DATA
BUS
cs
c/o
Figure 5 READ CYCLE TIMING
Note: AC timings measured at VOH = 2.0V, VOL = 0.8V and with test load circuit.
Figure 6 WRITE CYCLE TIMING
519
I
tSRX
RXD
tHRX
1/
\~
---If\
J
...
4 RXe periods
RXe
(4 x baud)
~
\
\
I
1\
Figure 7 RECEIVER CL.OCK AND DATA TIMINGS
TXC
(4x)
cs,c7D
U
TXRDY - - - - - - - - . \ \ . . . ._ _ _ _ _ _ _ _-'
TXE
-------------~\~-------_1---------~---------r_---
TXD1
----------------------.-4
TXDO----------------------·~-------~
Figure 8 TRANSMITTER TIMINGS (ARINC MODE)
1520
~
C
......
RXD1,O
(Arinc)
15t Data Character
null
3rd Data Character
2nd Data Character
4th Data Character
p
I
null
n
FCR
n
n
RXRDY
RD
n
LJ
U
Figure 9
rL
U
LJn
TXRDY - - - ,
I~
U
RXRDY AND FCR TIMING
r
TXE-~
______________
n______________
~
~
n ______________
~I~~
~
u
TXD1
I
<0
<0
W
15t Data Character
Figure 10
2nd Data Character
3rd Data Character
RXRDY AND TXE TIMINGS (4 Character Sequence)
521
4th Data Character
4 eight bit character with 4 bit minimum space
Last bit of last character IS parity
I - - - - o n e transmission/reception consist; of lour eight bit character and 4 bit (min.) null.
4 bit space (null)
Delimiter
I
End of previous
character
1st Character
4th Character
2nd Character
3rd Character
4 bit null followed
by next character
or continued space
Note Delimiter IS transml"ed at
the end of the TX sequence
Figure 11
ARINC 429
The VIZ Receiver converts ± 10 volt levels to TTL logic levels. It is composed of logic one and zero comparators. A logiC one
(RXD1) TTL output is derived when voltage rising to 1 (VR1) threshold is crossed and terminated at voltage falling to 1 (VF1). A
logic zero (RXDO) TTL output is generated between voltage falling to zero (VFO) and voltage rising from zero (VRO). When input
thresholds are not exceeded, neither output is active. The VIZ output can drive one TTL input.
The return to zero (RZ) format is shown below
r-----.
RXD1
VIZ
Ree
RXDO
:!:10V
Line
WD1993
VR1
Gnd----'il
i
i
Null
II
L~IC 0
Logic 1
I Logic 1 I Logic 1
Null
Logic 0
I
I
--fl
__~__--__~~~_____
I
I
RXD1
RXDO
Derived
Internal D~--'
. ._______
Figure 12
ARINC
~ECEIVER
..J
CIRCUIT
The VIZ Driver convert TTL logic levels into ± 10 volt levels. The TXD1 and TXDO outputs of the WD1993 are used to drive the
line drivers. Each output can drive one TTL load. When the outputs are not active, the line Driver should return to zero.
TXD1
WD1993
----II
TXD1
T?--,-----..--4-~.._--JVV\.-__I_"\o""_ __.
12
15K
RXOl
3
~
!
·5V
LM3190
OR EOUIV
lOOK
500l!
15K
lOOK
RXOO
LOW
C>--.----~~---~-~-----~
LF356
OR EOUIV.
330K
1
4.7
ILl
200K
12V
01
1'1
Nole:
Figure 14
01 - 04 -- IN4001
All caps: 35V
ARINC 429 LINE LEVEL TRANSLATOR (RECEIVER)
.5V
4.7K
1M
·12V
lOOK
SDK
4.7K
lOOK
511!
HIGH
TXD1
lOOK
LH0002C
OR EOUIV,
lOOK
5111
LOW
..~
TXDO C>------6-------JV~-----lOOK
":"
Figure 15
-12V
ARINC 429·1 LINE DRIVER
523
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other riqhts of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
!;24
Pnnled In USA
WESTERN DIGITAL
COR
P
0
RAT
/
0
N
WD1984 Multi-Character
Synchronous Asynchronous Rec'eiver Transmitter
FEATURES
• DIAGNOSTIC LOCAL LOOP-BACK TEST MODE
• TWO OPERATING MODES: SYNCHRONOUS & ASYNCHRONOUS
• DC TO 1M BITS/SEC (1x) OPERATION
• TTL COMPATIBLE INPUTS AND OUTPUTS
• 1 TO 8 CHARACTERS OF 5, 6, 7, OR 8 BITS PER CHARACTER TRANSMISSION
• SINGLE +5 VOLT SUPPLY
• SELECTABLE PARITY INSERTION IN OR AFTER LAST
BIT OF WORD
• 28 PIN CERAMIC OR PLASTIC PACKAGE
• TEMPERATURE RANGES O°C to 70°C, -40°C TO +85°C
• EVEN/ODD PARITY SELECT OR NO PARITY
• DOUBLE BUFFERED RECEIVER & TRANSMITTER
INTRODUCTI°ti
The Western Digital WD1984 is designed to handle digital
data transmission, according to two protocols. These are the
Synchronolls and Asynchronous protocols. Parallel data is
converted into a serial data stream during transmission and
serial to parallel during reception.
• ASYNCHRONOUS SELECTABLE CLOCK RATES (1 x, 16x)
• UNDER RUN ERROR DETECTION FOR TRANSMISSION
" OVERRUN, FRAMING AND PARITY ERROR DETECTION ON RECEIVER
The device can be programmed to transmit and receive
words that are 1 to 8 characters in length; 5, 6, 7 or 8 bits
per character. Error flags and control signals have been
provided to broaden the appl ication range of the device. The
WD1984 is packaged in a 28 pin plastic or ceramic package
and is available in twp temperature ranges: Commercial and
Industrial.
• LINE BREAK GENERATION AND DETECTION (ASYNC
MODE)
" FIRST CHARACTER OF WORD FLAG FOR SINGLE INTERRUPT APPLICATIONS
VSS
BDET/SDET
CTS
TXC
WE
N.C.
D7
MR
D6
TXE
D5
RXRDY
D4
TXRDY
D3
AEC6IVE/TAAN8MIT
N.C.
D2
TXD
Dl
RXC
~CONTROLlERS
DO
FCRfTlP
RXD
N.C.
VCC
READ/WAITE
TXC
CONTROL
Figure 1 WD1984 PIN-OUT
TXE
Axe
FeR
N.C. No Internal Connection
BOETI
SYNC DEl
Figure 2 WD1984 BLOCK
•
525
DIAGRA~
PIN NO.
SYMBOL
1
VSS
GROUND
Ground
2
BDET/
SDET
BREAK DETECT/
SYNC DETECT
This pin is a bi-directional port.
In ASYNC, it is an output, which goes high when the receiver
logic detects a break character.
FUNCTION
SIGNAL NAME
In the SYNC mode, it is an input which causes the receiver to
begin assembling data bytes as programmed.
3
CTS
CLEAR-TO-SEND
This input is activated (Vld to enable the transmitter logic.
4
TXC
TRANSMIT CLOCK
This input is the source clock for transmission. The data rate
is a function of this clock frequency.
ASYNC MODE = 1 x or 16 x bit rate
SYNC MODE = 16 x bit rate
5
N.C.
6
MR
MASTER RESET
When high (V IH), presets the WD1984. The command register
is set to 00100101 and the mode register is set to 00111100.
7
TXE
TRANSMITTER
EMPTY
This output goes high to indicate the end of a transmit operation. TXE is automatically reset after the Transmit Holding
Register is loaded.
8
RXRDY
RECEIVER READY
This output, when high, alerts the CPU that the Receiver Holding Register contains a data character that is ready to be input.
This output is automatically reset whenever a character is read
from the WD1984.
9
TXRDY
TRANSMITTER
READY
This output, when high, alerts the CPU that the Transmit Holding Register is ready to accept a data character. The TXRDY
output is automatically reset whenever a character is written
into the WD1984 and can be used as an interrupt to the
system.
10
N.C.
11
TXD
TRANSMIT OAT A
ONE
This output is the serial data output.
12
RXC
RECEIVE CLOCK
This input is the source clock for reception. The data rate characteristics are the same as the transmit clock.
13
FCR/TIP
FIRST CHARACTER
READY/TRANSMISSION IN
PROGRESS
In the ASYNC mode, this output goes high after the receiver
has completed reception of the first character in a multi-character sequence.
No internal connection.
14
N.C.
15
VCC
POWER SUPPL Y
+5V DC
16
RXD
RECEIVE DATA ONE
This input is the serial data input.
17
18
19
20
21
22
23
24
DO
01
02
03
04
05
06
07
DATA BUS
This is the bi-directional data bus. It is the means of communication between the WD1984 and the CPU. Control, Mode,
Data and Status Registers are accessed via this bus.
!j26
PIN NO.
SYMBOL
FUNCTION
SIGNAL NAME
25
WE
WRITE ENABLE
When low (V Id, allows the CPU to write into the selected
register.
26
CS
CHIP SELECT
When low (Vld, the device is selected. This enables communication between the WD1984 and a microprocessor.
-
27
C/O
CONTROL/DATA
This input is used in conjunction with an active read or write
operation to determine register access via the DATA BUS.
28
RE
READ ENABLE
When low (Vld, allows the CPU to read data or status information from the WD1984.
GENERALDESCmPTION
2) Asynchronous clock rate select (1 x or 16x clock rate),
which describes resolution and bit rate characteristics.
The WD1984 is a bus-oriented MOS/LSI device designed to
provide two data communication protocols:
1. Asynchronous
2. Synchronous
The WD1984 also contains a local loop-back test mode of
operation, which is controlled by the Loop Test Enable (L TE)
bit in the command register. In this diagnostic mode, the
transmitter output is "looped-back" into the receiver input.
The REN and TEN control bits must also be active ("1") and
the CTS input must be low ("0"). The status and output flags
operate normally.
The control registers are used to select the desired protocol
and provide programmable format options within each protocol, as outlined below.
The WD1984 contains two control registers needed to specify formal options within each protocol. These registers are
the command instruction register and the mode instruction
register.
ORGANIZATION
The format options available to the user are:
A block diagram of the WD1984 is shown in figure 1.
1) Parity Enable (PEN)
As mentioned, the WD1984 is an eight bit bus-oriented
device. Communication between the WD1984 and the controlling CPU occurs via the 8 bit data bus through the bus
transceivers. There are 2 accessible data registers, which
buffer transmit and receive data. They are the Transmit Holding Register and the Receive Holding Register. There is a
parallel-to-serial shift register (parallel in-serial out), the
transmit register and a serial-to-parallel shift register (serial
in-parallel out), the receive register.
2) Parity Position (PIA)
TheParity bit (when enabled) can either be appended to the data word After the data bits or
it can be Inside the data word in the last bit
position.
3) Odd or Even Parity Select (EPS)
4) Character Length Select 5,6,7 or 8 Bits/Character) (CLS2 and CLS2)
The Asynchronous mode has the option of selecting the
number of contiguous characters per transmission and receive sequ€!nce. This multicharacter option may facilitate
data handling between peripheral devices with a non-standard number of data bits. Therefore, the user can change
the mode register to transmit and receive any combination
of one to eight characters per word and 5, 6, 7 or 8 bits per
character.
Operational control and monitoring of the WD1984 is performed by two control registers (the command instruction
register and the mode instruction register) and the status
register.
A read/write control circuit allows programming/monitoring
or loading/reading of data in the control, status or holding
registers by activating the appropriate control I ines: Chip Select (CS), Read Enable (RE), Write Enable (WE) and Control
or Data Select (ClD).
Additionally, the Asynchronous mode has two options which
determine the operational characteristics of the protocol:
Internal control of the WD1984 is by means of two internal
microcontrollers; one for transmit and one for receive. The
control registers, null detect logic and various counters,
provide inputs to the microcontrollers which generate the
necessary control signals to send and receive serial data according to the programmed protocols.
1) Stop Bit Selection-(SPS)
This control bit selects 1 or 2 stop bits (1 or 1V2 bits in 5
bit characters) at the end of the word, which is part of the
character delimiting definition.
527
REGISTER DEFINITIONS
The format and definition of the Command Register is shown below:
TEN
1
0
CR7
CR6
CRS
CR4
CR3
CR2
CR1
EPS
IR
PEN
LTE
TXSM
REN
PIA
Transmit ENable
LTE
Enabled
Disabled
PIA
1
0
REN
1
0
TXSM
1
0
Loop Test ENable
Local loop-back mode
Normal Operation
1
0
PEN
Parity Inside or After
TEN
Parity ENable *
After the data word
Inside (the last data bit) of word
0
Receive ENable
IR
Internal Reset
Enabled
Disabled
1
Returns WD1984 to mode instruction format
Enabled
Disabled
1
0
EPS
Transmit Space or Mark
Even Parity Select
1
0
Send break character (force TXD low)
Normal transmitter operation
Even parity
Odd parity
*Internally disabled in Synchronous mode.
The format of the Status Register is shown below:
TXRDY
1
0
RXRDY
1
0
SR7
SR6
SRS
SR4
SR3
SR2
UE
BRKDET
FE
OE
PE
TXE
Transmitter
Read~
RH R has been overwritten
No error
Receiver Read:t
FE
Framing Error
Active (RHR should be read)
Inactive
Transmitter Empty
Transmitter idle
Transmitter active
1
0
Parity Error
Error reported
No error
1
SRO
TXRDY
Overrun Error
1
0
1
PE
RXRDY
Active (THR can be reloaded)
Inactive (transmitter is busy)
TXE
0
OE
SR1
Indicates a framing error has been detected.
No error
0
BRKDET
o
UE
Break Character Detect
In ASYNC mode, this bit indicates the receiver has detected
a break character.
Inactive
Underrun Error
In multi-character transmissions, indicates that the
THR has not been loaded with a new character in
time for a contiguous data transmission sequence.
No error
o
528
The format and definition of the Mode Register is shown below:
[MR7
SBS
I
MR6
MR5
MR4
N3
N2
N1
MR3
MR2
MR1
MRO
CLS2
CLS1
MS2
MS1
MS2
MS1
X
0
0
1
X
0
1
X
CLS2
CLS1
0
0
1
1
0
1
0
1
N3
N2
N1
Characters Per Word Select
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
1
0
1 character
2 characters
3 characters
4 characters
5 characters
6 characters
7 characters
8 characters;
Mode Selected
Undefined
Asynchronous mode (16X)
Asynchronous mode (1 X)
Synchronous mode (16X)
Character Len9th Select
5 bits
6 bits
7 bits
8 bits
1
1
SBS
1
1
1
Stop Bit Select
1
2 stop bits (1-1/2 bits in 5 bit characters)
1 stop bit
o
The WD1984 registers are addressed according to the following table:
CS
C/O
RE
WE
L
L
L
L
H
L
L
H
H
X
L
H
L
H
X
H
L
H
L
X
Registers Selected
Read Receive Holding Register
Write Transmit Hold ing Register
Read Status Register
Write Control Registers
Data Bus Tri-Stated
L = Vll at pins
H
VIH at pins
X = don't care
ASYNCHRONOUS OPERATION
When the Asynchronous mode is selected, start, stop and
parity bits are inserted as programmed. The receiver and
transmitter clocks can be programmed as 1X or 16X. The
transmitter output, TXD line will mark or space after transmission depending on command register programming. A
line break condition can be programmed by setting the
TXSM bit (command register bit CR3) to a logic "1". The
TXD line will bE~ forced to a low as long as this bit is logic "1".
When the receiver detects the input line (RXD) low for a period equal to the word length including start, parity and stop
bits, the break detect flag will become active.
The multi-character option is available to the Asynchronous
protocol. The user can select any combinati9n of one to eight
characters per word and 5, 6, 7 or 8 bits per character. This
allows a minimum word length of 5 bits and a maximum of 64
bits, plus parity, if enabled.
SYNCHRONOUS OPERATION
When the Synchronous mode is selected, start and stop bits
are not transmitted. Parity is not available in Synchronous
mode. The multi-character option is not available; however,
the transmitter will continuously shift out data as long as the
transmit holding register is buffered by the CPU. Two I/O sig-
•
529
mode instruction register is accessed by performing a control
write operation setting the internal reset bit high, which allows the next control write operation to program the mode
register. Subsequent control write operations will again
access the command register until another internal reset is
performed. Internal reset commands should also disable the
receiver and transmitter until the new mode instruction is programmed. The next command should then reactivate the receiver and transmitter to resume operations. This minimizes
any errors that may be generated as a result of an active receive line during reprogramming.
nals are provided for synchronization, TIP (transmission in
progress), an output which indicates that the transmitter is
actively sending data and SYNCDET (SYNC detect), an input which notifies the receiver logic when to begin assembling characters.
Synchronization is obtained when the TIP signal from the
transmitter is brought to the SYNCDET input of the associated receiver. Completion of a data transmission sequence
occurs when the last character in the transmit register is sent
and no further data is loaded into the transmit holding register. The TIP signal goes low. The receiver monitors the
SYNCDET line and assembles data characters until it goes
low, at which time it goes to an idle state.
The TXSM bit of the command register causes the transmitter output to be forced low after the last word is transmitted.
This is also used in Asynchronous mode to send a break
character (all zero data and parity bits).
PARITY MODES
The WD1984 is provided with some unique parity options as
discussed above. If parity is enabled and the word length is
eight bits, the parity is added to the transmitted word and
stripped from the received word. When programmed for 5,6
or 7 bits per character, the receiver checks and makes available the parity bit on the bus next to the MSB of data. Unused
bits in an assembled character are zero when the receive
holding register is read.
The receiver is equipped with logic to look for a break character in the Asynchronous mode. When a break character is
received, the receiver activates the break detect flag and status bit. When the receiver input line goes high again for at
least "one bit time", the receiver resets the break detect flag
and resumes its search for a start bit.
MULTI-CHARACTER OPERATIONS
For example, in Asynchronous mode when two 8 bit characters are programmed with parity after the Data Word and two
stop bits, 20 bits are transmitted. These are the Start bit, 16
Data bits, Parity and the 2 Stop bits. The Parity will be
stripped off at the receiver since the character length is 8.
As discussed above, the WD1984 is equipped with a multicharacter option which provides the user with the means of
transmitting and receiving multiple contiguous characters of
data within one set of start and stop bits. Since the WD1984
is an 8 bit bus-oriented device, the controlling processor must
read the WD1984 data from its holding register before the
subsequent characters are assembled. This situation also
exists on the transmit side, i.e., the Transmit Holding Register must be loaded before the previous 8 bits are completely shifted out of the transmit register.
In Synchronous mode, Parity is not available and it is suggested the user provide his own software CRC as the last
characters of his transmission.
OPERATING DESCRIPTION
Several "flags" are provided for interrupt purposes so that
continuity is maintained and data integrity is preserved.
These flags are First Character Ready (FCR), Receiver Ready
(RXRDY), Transmitter Ready (TXRDY) and Transmitter
Empty (TXE).
The WD1984 is primarily designed to operate in an 8 bit
micro-processor environment, although other control logic
schemes are easily implemented. The DATA BUS and the Interface Control Signals (CS, RE, WE and c75) should be
connected to the microprocessor's data bus and system control bus. The appropriate TXC and RXC clock frequencies
should be selected for the particular application, using a programmable baud rate generator such as a BR1941. A master
reset pulse initializes the WD1984 and presets the control
registers to transmit and receive four 8-bit contiguous characters with the 32nd bit odd parity. If other protocols are desired, then the mode and command registers should be programmed as discussed previously.
The Transmitter operates as follows:
For typical data communication applications, the RXD and
TXD input/outputs can be connected to RS-232C interface
circuits or a modem.
a)
With the mode and command registers programmed
as desired, the transmitter is enabled, TEN (CRO)
"1 ".
b)
The TXE and TXRDY flags are "1" (active).
c)
The external CTS signal = "0".
d)
The CPU loads data into the Transmitter Holding Register, TXE and TXRDY go Low.
e)
The data is loaded into the transmit register and TXRDY
goes High. This indicates the first data word is being
sent and the character can be loaded into the holding
register. If the WD1984 is programmed for more than
one character (multi-character) then an underrun error
will be generated if the next character is not loaded before the previous word is completely shifted out, unless
the current character is the last character in a sequence.
f)
If the last character is transmitted and no more new
data is to be sent, the transmitter will indicate its status
The TXRDY, RXRDY, FCR and FE/BRKDET Flags may be
connected to the microprocessor system as interrupt inputs.
The status register can be periodically read in a polled environment to support operations.
The CTS input can be used to synchronize the transmitter to
external events.
The WD1984 is designed such that a control register write
operation accesses the command instruction register. The
530
a transmit sequence in "mid-stream", since setting the TXSM
bit to a "1" while the transmitter is currently sending data will
immediately cause zeroes to be sent until the TXSM bit is reprogrammed to a "0". This can only be done when in the
loop-test mode, else the TXSM command is recognized only
after the current transmission is complete.
by raising the TXE flag. (No error is generated as a resu It of this cond ition.)
The Receiver operates similarly:
a)
With the control registers suitably programmed, the receiver is enabled, REN (CR2) = "1".
b)
The RXRDY and FCR flags are "0". (Inactive).
c)
The incoming data word activates the receive logic and
the data begins to be assembled in the receive register.
d)
When the first character is completely assembled, the
data is loaded into the Receive Holding Register, the
FCR (First Character Ready) and RXRDY (Receiver
Ready) flags become active, "1 ". The CPU should
read the data prior to the reception of the next character or an overrun error will be generated as the receiver
will overwrite the old data with the new data character
just received.
For multicharacter operations, failing to reload the Transmit
Holding Register in the middle of a data send sequence will
cause an underrun error in the transmitter and a word error
in the receiver. Failure to read the Receive Holding Register
after a FCR or RXRDY flag will cause an overrun error to be
generated.
For Loop-Back test operations, the user should be sure that
the TXC and RXC clock frequencies are the same. This is
normally implemented by placing the same clock signal on
both pins (TXC and RXC).
ILOOP TEST MODE:
ABSOLUTE MAXIMUM RATINGS
As mentioned, the WD1984 is equipped with a diagnostic
test mode, loc:alloop-back. This mode is activated by setting
the LTE command bit to a "1". The TEN and REN bits should
be "1" and eTS shou Id be "0". The receiver in puts are ignored and the transmitter outputs are held high V OH. The
transmitter is internally "looped-back" to the receiver and the
error and status flags operate normally.
Storage Temperature
Plastic (" F" package) . . . . . . . . . . . . . . .. - 55°C to + 125°C
Ceramic ("E" package) .............. - 65°C to + 150°C
Voltage on any Pin with respect to ground ... -0.5V to + 7V
Power Dissipation ............................. .400MW
Absolute ratings indicate limits beyond which permanent
damage may occur. Continuous operation at these limits is
not intended and should be limited to those conditions specified under DC Electrical Characteristics.
It is possible to program a test routine using the loop-back
mode so that one can simulate "line breaks" and parity errors. This can be done using the TXSM command to interrupt
DC ELECTRICAL CHARACTERISTICS
T A=O°C to
+ 70°C; Vee =5.0V
SYMBOL
± 5%; GND= OV
PARAMETER
MIN
TYP
MAX
UNIT
VIL
Input Low Voltage
-0.5
.08
V
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
VCC
0.45
V
VOH
Output High Voltage
IDL
Data Bus Leakage
IlL
Input Leakage
ICC
Power Supply Current
V
10L = 1.6mA
V
10H = -100J..tA
-50
uA
VOUT = 0.45V
10
uA
VOUT = V
10
uA
VIN = VCC
80
mA
2.4
45
TEST CONDITION
CAPACITANCE
TA = 25°C: Vec = GND = OV
SYMBOL
PARAMETER
CIN
CI/O
TYP
MAX
UNIT
Input Capacitance
10
pF
fC = 1MHz
I/O Capacitance
20
pF
Unmeasured pins
returned to GND
MIN
531
TEST CONDITION
+20
:ec
(j)
.....
.s
~
«
...J
CO
+10
/~
>-
w
/
0
0
I~
a..
I-
~
-10
0
"'1
-20
-100
/
V
/
SPEC.
o
-50
+50
+100
6 CAPACITANCE (pF)
Figure 3 OUTPUT DELAY VS CAPACITANCE
A.C. TIMING PARAMETERS
SYMBOL
PARAMETER
MIN
MAX
UNIT
CONDITION
BUS PARAMETERS
Read Cycle
(Reference Figure 5)
tAR
Address Stable before RE. (CS, Cm)
50
ns
tRA
Address Hold Time forRE, (CS, Cm)
5
ns
tRE
RE Pu Ise Width
tRD
Data Delay from RE
tRDH
RE to Data Floating
WRITE CYCLE
350
25
ns
200
ns
200
ns
(Reference Figure 6)
tAW
Address Stable before WE
20
tWA
Address Hold Time for WE
20
ns
tWE
WE Pu Ise Width
350
ns
tDS
Data Set-Up Time for WE
200
ns
tWDH
Data Hold Time for WE
40
ns
OTHER TIMINGS
CL = 50 pF
CL (Max) = 100 pF
CL(Min) = 50 pF
ns
(Reference Figure 7, 8, 9)
tOTX
TXD Delay from Falling Edge of TXC
ns
CL = 100 pF
tSRX
RX Data Set-Up Time to Sampling Pulse
200
ns
CL=100pF
tNRX
RX Data Hold Time to Sampling Pulse
100
ns
CL = 100 pF
tTX
Transmitter Input Clock Frequency
tTPW
500
1 x Baud Rate
DC
500
kHz
4x, 16x Baud Rate
DC
750
kHz
Transmitter Input Clock Pulse Width
1 x Baud Rate
16 x Baud Rate
!j32
1.0
us
500
ns
SYMBOL
PARAMETER
tTPD
MIN
MAX
UNIT
CONDITION
Transmitter Input Clock Pulse Delay
tRx
1 x Baud Rate
1.0
us
16 x Baud Rate
700
ns
Receiver Input Clock Frequency
tRPW
1 x Baud Rate
DC
500
kHz
4x. 16x Baud Rate
DC
750
kHz
Receiver Input Clock Pulse Width
tRPD
1 x Baud Rate
1.0
us
16 x Baud Rate
500
ns
1 x Baud Rate
1.0
us
16 x Baud Rate
700
Receiver Input Clock Pulse Delay
I
ns
ns
tTX
TXRDY Delay from center of Data Bit
112
200 ns
tTXC
(1x or 16x)
A.C. TIMING PARAMETERS
-----
SYMBOL
tRX
PARAMETER
MIN
MAX
UNIT
RxRDY Delay from Center of Data Bit (FCR
Delay from Center of Data Bit)
'/2
RRXC
Internal BRKDET Delay from Center of Data Bit
1
tRXC
External SynDet Set-up time before rising
edge of RXC
200
TXEMPTY Delay from Center of Data Bit
ns
V2
tTXC
-------~-:-~~~~:-:-:-----------------~~-------Figure 4 TEST POINTS FOR A.C. TIMING
DATA
BUS
cs c."15
Figure 5 READ CYCLE TIMING
Note: AC timings measured at VOH = 2.0V, VOL = O.BV
533
TEST CONDITION
CL = 50 pF
(1 x Rate)
----
DATA
BUS
~
VHAC
_ _-...,;.V~LA~C_ __
TOS
Figure 6 WRITE CYCLE TIMING
Txe
....- - - - - tTPW
..
-------!.~I I------- tTPD
1X BAUD
...._ _ _ _ _ _ _ _ _ _ _ 16 Txe PERIODS _ _ _ _ _ _ _ _ _ _ _
~
Txe
16X BAUD
f
_T;.;.X.;.;;D_ _ _ _ _
1m.
Figure 7 TRANSMITTER CLOCK AND DATA TIMINGS
....-------tSRx-------~4_-----tHRX------~
AXD
...._ _ _ _ _ _ tRPW _ _ _ _ _ _ _............_ _ _ _ _ tRPD - - - - - - - I . - t
Axe
1X BAUD
....- - - - - - - - - - - - 1 6 Rxe
PERIODS-----------~
Axe
16X BAUD
Figure 8 RECEIVER CLOCK AND DATA TIMINGS
~i34
Rxe
(16x)
SDET - - - - - - - - - - - - {
RXD ________________________~)(~_______________1_st_d_a_ta__B_it________________________
Txe
(16x)
es em
---------,U
u
WE-----U
tTX
U
l-
-~
TXRDY
~~tTX
,'-------
\'--------',
TXE-------------------\~___________________________________
TtP---------------------~1
TXD---------------T---------------------1st data bit
\~-------------------------------------Figure 9 SYNCHRONOUS MODE TIMINGS
Start Bit
RXD
(Async)
RXD
(Synch)
FCR
RXRDY
t st Data Character
1st Data Character
2nd Data Character
2nd Data Character
3rd Data Character
3rd Data Character
Stop bits
4th Data Character
------------~~-----------------------------------
____________
~n~
_______r_L____
u
Lf
Figure 10 RXRDY AND FCR TIMING
535
~r--l~
u
_______~
------'ri
--Jn. . _____----'n. . _____----'
~~-----------------
TxE
-u-l______
TXADY
u
TXD
I
~
1st Data Character
2nd Data Chara.;ter
3rd Data Character
4th Data Character
~·A~·----------~----------~--------~----------~
Start bit
Figure 11 TXRDY AND TXE TIMINGS (4 CHARACTERS SEQUENCE)
2 eight bit characters with start/stop bits and parity
Parity outside data Character
if programroled ~
Start bit
Marking line or .
end of previous
character
I
1,1,
1\
i
1'~5161
(
Programmed stop bits
,1'1'1,,1,,1,,1,,1"1,,1,,1 p);,
Marking line or
next transmission
V
1sl 8 bit Character
2nd 8 bit Character
Flgure12 16 BIT ASYNCHRONOUS
4 Five bit characters with start/stop
bits and parity (Parity programmed inside last data character)
Parity inside the last bit
of the last Character ~
Single stop bit
~~
\ ~
----------~~
I 1, I 21 31 I 51 61 71 81 91,0 1,,1,21,31,41,51,61,71,81,91 ~pI L-I____
Marking line or
previous character
-1
r
l~~
1
1st Character
2nd Character
3rd Character
Marking line or
next transmission
4th Character
Figure 13 20 BIT ASYNCHRONOUS
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
536
Pronted
In
U.S.A
Security Products
Page
Part Number
WD2001 fWD2002
WD2001/WD2002
Data Encryption Devices ......................... . . . . . . . . . . . . . . . . . . . . . 539
Applications Note ................................................... 551
Cipher Feedback Cryptography Technical Note ............................ 559
537
5~18
WESTERN DIGITAL
c
o
p
R
o
R
A
T
o
/
N
=e
c
N
WD2001/WD2002 Data Encryption Devices
FEATURES
8
.....
ic
APPLICATIONS
• SECURE BROKERAGE TRANSACTIONS
• CERTIFIED
DARDS.
BY
NATIONAL
BUREAU
OF
8
• ELECTRONIC FUNDS TRANSFERS
STAN·
• SECURE BANKINGIBUSINESS ACCOUNTING
• TRANSFER RATE:
WD200112-05 300Kbs with 500KHz clock
WD200112·20 1.3 Mbs with 2MHz clock
WD200112·30 1.8 Mbs with 3MHz clock
• MAINFRAME COMMUNICATIONS
• ENCRYPTSIDECRYPTS 64 BIT DATA WORDS USING
56 BIT KEY WORD
• SECURE AID
• SECURE DISK OR MAG TAPE DATA STORAGE
• SINGLE PORT 28 PIN PACKAGE WD2001 OR DUAL
PORT 40 PIN PACKAGE WD2002
• SECURE PACKET SWITCHING TRANSMISSION
• REMOTE AND HOST
COMMUNICATIONS
GENERAL DESCRIPTION
The Western Digital WD2001 and WD2002 Data
Encryptionl Decryption devices are designed to encrypt
and decrypt 64-bit blocks of data using the algorithm
specified in the Federal Information Processing Data
Encryption Standard (#46). These devices encrypt a
64-Bit clear text word using a 56-Bit user-specified key
to produce a 64-Bit cipher text word. When reversed,
the cipher text word is decrypted to produce the
original clear text word.
The DE200112 are fabricated in N-channel silicon gate
MOS technology and are TTL compatible on all inputs
and outputs.
• COMMAND BIT PROGRAMMING VIA DAL BUS OR
INPUT PINS
• DMA COMPATIBLE
OM 1883)
(SEE
WESTERN
DIGITAL
• PARITY CHECK ON KEY WORD LOADING
• STANDARD 8 BIT MICROPROCESSOR INTERFACE
• INPUTS AND OUTPUTS TTL COMPATIBLE
• KEY STORED
ACCESSIBLE
ON
CHIP
IS
NOT
EXTERNALLY
SEPARATE CLEAR AND CIPHER BUS STRUCTURE
ON WD2002
NC [
1
KA [
2
NC [
3
l5iA[
4
i'iCiA[
5
NC [
6
(+51 VCC [
7
(.12IVOO [
8
COMPUTER
1
6
t t
M[9
_(+12IVnD
_(+!»Vee
_IGND1VSS
OAL1 [
17
OAL3 [
18
OAL5.[
19
OAL7 [
20
KA
WD2001/WD2002 BLOCK DIAGRAM
539
DIR
DIA
DOR
DOA ACT
EID CRPS KEOE
is
N
PIN OUTS
PIN NO.
PIN NAME
SYMBOL
FUNCTION
WD2001 WD 2002
11-18
17-24
DATA LINES
DALO ....
DAL 7
Eight active true three-state bi-directional I/O lines
used for information transfer to and from the DES
chip's registers. During single port operation, all
COMMAND/STATUS, KEY WORD and DATA WORD
transfers are via this bus. During dual port operation,
all COMMAND/STATUS, KEY WORD and clear DATA
WORD transfers are via this bus. (Cipher DATA WORD
transfers are via the CIPHER DATA PORT (COP) bus.)
N/A
11-14
27-30
CIPHER DATA PORT
CDPO
CDP 7
~
Eight active true three-state bi-directional I/O lines
used only in dual port operation. Cipher DATA WORD
transfer:sare via this bus. These pins are available on
the WD2002 40 pin package version Q..!JJy.
8
POWER SUPPLY
VDD
+ 12v
7
POWER SUPPLY
VCC
+ 5v
25
36
GROUND
VSS
GROUND
9
15
CLOCK
CLK
System clock input.
21
32
MASTER RESET
MR
MR active low resets the COMMAND/STATUS
REGISTER and resets internal circuitry. (Requires
active clock for reset operation.)
10
16
CHIP SELECT
CS
CS is made low to access registers within the device.
8
10
READ ENABLE
RE
The contents of the selected register are placed on the
DAL (or COP) bus lines when CS and RE are made low.
7
9
WRITE ENABLE
WE
Information on the DAL (or COP) bus lines is written
into the selected DES register when CS and WE are
made low.
19
26
AO
AO
When this input is active high (during CS active) the
COMMAND/STATUS REGISTER is addressed. (AO
active high will override internally generated addressing of the KEY and DATA REGISTERS as described
on page 6.) This input is ignored when CRPS is active.
26
38
KEY REQUEST
KR
This output is active high when the DES chip is
requesting that a byte of the KEY WORD be written into
the KEY REGISTER. (The KEY REGISTER is automatically addressed when KR is active, unless
overriden by AO.)
2
2
KEY ACKNOWLEDGE
KA
This output is active low when WE is made low while
the KEY REGISTER is addressed. (Can be used for
handshake.)
27
39
DATA-IN REQUEST
DIR
This output is active high when the DES chip is
requesting that a byte of the DATA WORD be written
into the DATA REGISTER. (The DATA REGISTER is
automatically addressed when DIR is active, unless
overriden by AO.)
3
4
DATA-IN
DIA
This output is active low when WE is made low while
the DATA REGISTER is addressed. (Can be used for
handshake.)
6
5
ACKNOWLEDGE
540
PIN NO.
PIN NAME
SYMBOL
WD2001
WD2002
28
40
4
5
22
33
KEY PARITY ERROR
20
31
COMMAND REGISTER
PIN SELECT
23
34
ACTIVATE
ACT
N/A
37
KEY ERROR
OUTPUT ENABLE
KEOE
24
35
ENCRYPTIDECRYPT
EID
N/A
25
DUAL PORT SELECT
DATA-OUT REQUEST
FUNCTION
This output is active high when the DES chip is
requesting that a byte of the DATA WORD be read from
the DATA REGISTER. (The DATA REGISTER is
automatically addressed when the DOR is active, unless
overridden by AO.)
This output is active low when RE is made low while the
DATA REGISTER is addressed. (Can be used for handshake.)
This output is active low when enabled via the COMMAND/STATUS REGISTER BIT 2 (KEOE) and a parity error
has been detected during loading of the KEY REGISTER.
This input selects DAL bus or input pin programming of
the COMMAND/STATUS REGISTER. CRPS high or open
selects DAL bus programming. CRPS low selects input
pin programming.
When CRPS is high or open, this pin is an output
reflecting the status of the ACTIVATE bit (bit 1) of the
COMMAND/STATUS REGISTER. When CRPS is low, this
pin is an input that overrides the ACTIVATE bit of the
COMMAND/STATUS REGISTER.
This output indicates the status of the KEY ERROR
OUTPUT ENABLE bit (bit 2) of the COMMAND/STATUS
REGISTER. This output is active when input pin
programming is selected (CRPS low). This pin is available
on the WD2002 40 pin package version ~
When CRPS is high or open, this pin is an output
reflecting the status of the ENCRYPTIDECRYPT bit (bit 3)
of the COMMAND/STATUS REGISTER. When CRPS is
low, this pin is an input pin that overrides the ENCRYPTIDECRYPT bit of the COMMAND/STATUS
REGISTER.
When this input is high or open, single port operation is
selected and all DES chip transfers are via the DAL bus.
When DPS is low, dual port operation is selected and both
the DAL bus and the CDP bus are used [separate busses
for clear data (DAL bus) and cipher data (CDP bus)]. This
pin is available on the WD2002 40 pin package version
only.
DOR
DATA-OUT
ACKNOWLEDGE
NOTE: The WD2001 28 pin package version does not have the following pins:
The 8 CDP pins, the KEOE pin, and the DPS pin.
541
ORGANIZATION
The Data Encryption Standard chip consists of a 56-bit KEY
REGISTER, a 64-bit DATA REGISTER, an 8-bit COMMAND/STATUS REGISTER, plus the necessary logic to
check KEY parity and implement the NBS algorithm. A
typical system implementation is shown on page 10 and
the block diagram is shown on page 1. Although the DES
chip interfaces to a wide variety of processors including
mini-computers, the interface is tailored to the 8080A class
microprocessor.
.•
BIT
55
BIT
•
0
KEY REGISTER
(LOAD ONLy)
Data Register
GENERAL OPERATING DESCRIPTION
The user programs the DES chip for encryption or
decryption, and single or dual port operation. * Data is
encrypted/decrypted with a 64-bit user defined KEY WORD.
Data encrypted with a given KEY WORD can be decrypted
only using that KEY WORD. The KEY REGISTER is loaded
by the computer with. eight successive 8-bit bytes. Parity is
checked on each byte of the KEY WORD as it is loaded into
the KEY REGISTER (The 8th bit (DALO) of each 8-bit byte is
reserved for odd parity for that byte and is not used in the
algorithm calculation.) Similarly the DATA REGISTER is
loaded with eight successive 8-bit bytes. The DATA
REGISTER is read by reading eight successive 8-bit bytes.
This 64-bit register contains plain or cipher text. When in
the encrypt mode, the DATA REGISTER is loaded with plain
text, and when read contains cipher text. When in the
decrypt mode, the DATA REGISTER is loaded with cipher
text, and when read contains plain text. The DATA
REGISTER is always read or loaded with eight successive
byte transfers. The DATA REGISTER can be loaded only
when there is a DATA-IN REQUEST (status bit and output);
similarly the DATA REGISTER can be read only when there
is a DATA-OUT REQUEST (status bit and output).
When the DES chip is programmed for encryption, the
DATA REGISTER is loaded with eight bytes of plain or clear
text. The DES chip encrypts the data, then the encrypted
data may be read from the DATA REGISTER (64-bits of
encrypted text). When the DES chip is programmed for
decryption, the DATA REGISTER is loaded with eight bytes
of encrypted or cipher text. The DES chip decrypts the data,
then the plain text may be read from the DATA REGISTER
(64-bits of plain text). Note that all transfers to and from the
KEY REGISTER and/or DATA REGISTER must occur in
eight successive 8-bit bytes.
.• .
BIT
63
BIT
0
DATA REGISTER
CommandlStatus Register (CIS R)
* Note: Dual port operation available with WD2002 40 pin
package version only. (Single and dual port
operation is described in detail under PART V.
OPERATION.)
This 8-bit register controls the operation of the DES
chip and monitors its status. Bits 7, 6, 5 and 4 are
status-only bits (read only). Bits 3, 2 and 1 are
COMMAND/STATUS bits (read/write). Bit 0 is not
used. The COMMAND/STATUS bits (bits 3, 2, and 1)
are normally loaded only once for an entire encrypt or
decrypt process.
REGISTER DESCRIPTION
The following describes the KEY, DATA, and COMMAND/STATUS REGISTERS of the DES chip.
7
DOR
Key Register
This 56-bit register contains the KEY by which the Data
Encryption Algorithm operates. Eight successive bytes are
needed to load the KEY REGISTER. The KEY REGISTER
can be loaded only when there is a KEY REQUEST (Status
bit and output). THIS REGISTER IS LOAD ONLY AND
CANNOT BE READ.
6
DIR
5
4
3
KPE
KR
EID
STATUS BITS
(READ ONLy)
2
KEOE
1
ACT
COMMAND STATUS
BITS[ READ]
WRITE
COMMANDISTATUS REGISTER
:342
0
N/U
COMMAND/STATUS REGISTER (C/S R)
Bit
Name
Function
C/SRO
NOT USED
CIS R1
ACTIVATE
This bit must be set from '0' to '1' to initiate loading the KEY
REGISTER. This bit must be '1' for encrypt/decrypt operation. This is
a read/write bit.
CIS R2
KEY ERROR OUTPUT ENABLE
When '0', the KEY PARITY ERROR output pin (KPE) remains inactive
regardless of the status of the KEY PARITY ERROR bit (bit 5). When
'1', the KEY PARITY ERROR output pin is active when the KPE bit
(bit 5) is '1 '. This bit is set to '1' upon a MASTER RESET. This is a
read/write bit.
(KEOE)
--
CIS R3
ENCRYPT/DECRYPT (E/D)
When '0' data is to be encrypted. When '1' data is to be decrypted.
This is a read/write bit.
C/SR4
KEY REQUEST (KR)
This bit is set one clock period after the ACTIVATE bit is set (from
'0' to '1 '). It is reset upon loading of the 8th and final byte of the KEY
REGISTER. This Is a read only bit.
CIS R5
KEY PARITY ERROR (KPE)
This bit is set internally upon detection of a parity error during
loading of the KEY REGISTER. It is reset when the ACTIVATE bit is
programmed from '1' to '0' (I.e., chip is deactivated). This is a read
only bit.
CIS R6
DATA-IN REQUEST (DIR)
This bit is set upon either:
a) Completion of KEY REGISTER loading - or b) Completion of DATA REGISTER reading, (ie, the last DATA-OUT
REQUEST has been serviced by an 8-byte read and the DATA
REGISTER is now empty and ready to be loaded with the next
DATA WORD).
It is reset upon loading of the 8th and final byte of the DATA
REGISTER. This is a read only bit.
CIS R7
DATA-OUT REQUEST (DOR)
This bit is set upon completion of the internal encrypt / decrypt
calculation of a DATA WORD. It is reset upon reading of the 8th and
final byte of the DATA REGISTER. This is a read only bit.
Note: All bits of the COMMAND/STATUS REGISTER are reset to '0' upon MASTER RESET, except bit 2 (KEOE)
which is set to '1' and bit 0 (not used) which will read '1' by default during a COMMAND/STATUS REGISTER
read.
543
Again, for both data-in and data-out, further
activations of the DIR, DOR and DIA, DOA outputs,
after the first request, can be ignored and the DATA
REGISTER loaded (read) by 8 successive activations
of WE (RE).
DETAILED OPERATING DESCRIPTION
The DES chip is initiated by programming a '1' in the
ACTIVATE bit of the COMMAND/STATUS REGISTER.
The DES chip will respond by activating the KEY
REQUEST (KR) bit (bit 4) of the STATUS REGISTER
and the KEY REQUEST output.
After the last (8th) byte of the DATA REGISTER has
been read, the DES chip will reactivate the DATA-IN
REQUEST. This cycle of loading the DATA REGISTER,
internal algorithm calculation, and reading the new
data from the DATA REGISTER can continue indefinitely until all desired data has been encrypted or
decrypted with the current KEY WORD.
The user must deactivate AO (allowing the chip to
internally address the KEY REGISTER), and load the
KEY REGISTER with the 64-bit KEY WORD. The KEY
REGISTER is loaded with a consecutive a-bit bytes by
activating WE a times (with CS active).
When WE is made active, the DES chip deactivates the
KR output. When WE is deactivated, the KR output is
again activated. The DES chip will activate a KEY
REQUESTs in this fashion until the KEY REGISTER is
full.
Also, when WE is made active, the DES chip responds
by activating the KEY ACKNOWLEDGE (KA) output.
Thus, 8 KA activations will be made.
After all desired data has been encrypted / decrypted
with the current KEY WORD, the ACTIVATE bit of the
COMMAND/STATUS REGISTER should be programmed to '0'. When the ACTIVATE bit has been reset to
'0', an unauthorized user will not have access to the
last KEY loaded into the DES chip since to resume
operation, the ACTIVATE bit must be programmed to
'1' which activates KEY REQUEST and a new KEY must
be loaded before access to the DATA REGISTER is
possible.
The KR and KA outputs can be used for asynchronous
handshaking (as in DMA control) or further activations
following the first KR can be ignored and the KEY
REGISTER can be loaded in a synchronous (programmed I/O) manner via 8 successive activations of
WE.
To encrypt plain data, plain data is loaded into the
DATA REGISTER, and encrypted data is read from the
DATA REGISTER. (The ENCRYPT/DECRYPT bit (bit 3
of the COMMAND/STATUS REGISTER) must have
been previously programmed to '0'.)
To decrypt encrypted data, encrypted data is loaded
into the DATA REGISTER, and plain data is read from
the DATA REGISTER. (The ENCRYPT/DECRYPT bit
must have been previously programmed to '1 '.)
Each byte of the KEY WORD is checked for odd parity
as it is loaded. If a parity error is found, the chip will
set the KEY PARITY ERROR (KPE) bit (bit 5) of the
COMMAND/STATUS REGISTER. If the KEY ERROR
OUTPUT ENABLE bit (bit 2) of the COMMAND/
STATUS REGISTER has been set, the DES chip will
also activiate the KPE output. The KPE bit will be reset
when the ACTIVATE bit is re-programmed to a '0'.
Note: If it is desired to switch from encrypt to decrypt
(or vice versa) under the same KEY WORD, this
can be accomplished before a DATA WORD
transfer is initiated. By making AO high, the
DES chip will override the internal addressing of
the DATA REGISTER, and address the COMMAND/STATUS REGISTER. The COMMAND/
STATUS REGISTER can be re-programmed.
When AO is returned to a low state, the
DES chip will internally address the DATA
REGISTER awaiting loading of the next DATA
WORD.
After loading the last (8th) byte of the KEY WORD into
the KEY REGISTER, the DES chip will set the DATA-IN
REQUEST bit (bit 6) of the STATUS REGISTER and
activate the DATA-IN REQUEST (DIR) output. The
64-bit DATA WORD must then be loaded into the DATA
REGISTER. The DATA REGISTER is loaded in the same
manner as the KEY REGISTER via 8 successive
activations of DATA-IN REQUEST (DES output), WE
(DES input, and DATA-IN ACKNOWLEDGE (DES
output) .
DUAL PORT OPTION
(Available on WD2002 40 Pin Version Only)
When the DUAL PORT SELECT (DPS) input is high or
left open (ie., single port operation is selected), all
transfers to/from the DES chip are via the DAL bus.
The COP bus is not used and remains three-stated.
After the last (8th) byte of the DATA WORD has been
loaded, the chip begins the internal calculation of the
NBS algorithm. Upon completion of the calculation,
the new data is internally loaded into the DATA
REGISTER, and the DES chip sets the DATA-OUT
REQUEST bit (bit 7) of the STATUS REGISTER and
activates the DATA-OUT REQUEST (DOR) output. The
DATA WORD must then be read from the DATA
REGISTER. The DATA REGISTER is read in the same
manner as it was loaded via a successive activations of
DATA-OUT REQUEST (DES output), RE (DES input),
and DATA-OUT ACKNOWLEDGE (DES output).
When DPS is made low (ie., dual port operation is
selected), all transfers to/from the COMMAND/
STATUS REGISTER, and transfers to the KEY
REGISTER are still via the DAL bus. ~ DATA
WORDS are also transferred via the DAL bus. However,
cipher DATA WORDS are now transferred via the COP
bus. This provides separate busses for clear and
ciphered text.
544
Encryption during dual port operation requires loading
clear data via the DAL bus, and reading cipher data via
the CDP bus.
Decryption during dual port operation requires loading
cipher data via the CDP bus, and reading clear data via
the DAL bus.
COMMAND SELECT OPTION
When the COMMAND REGISTER PIN SELECT(CRPS)
input is made low, the ACT and E/ D pins are
enabled as inputs. These inputs override bits 1 and 3
(respectively) of the COMMAND/STATUS REGISTER.
This allows input pin control of the DES chip. The
KEOE bit (bit 2) of the COMMAND/STATUS REGISTER
will be held to '1'.
Input AO will be disregarded in this mode of operation,
and the COMMAND/STATUS REGISTER cannot be
accessed via the DAL lines.
Note that the ACT pin must be toggled from '1' to a '0'
to clear a parity error detection in this mode of
operation.
All other operation remains as described previously.
WD2001/WD2002 FLOW CHARTS
545
MAXIMUM RATINGS
Storage Temp. Ceramic -65°C to + 150°C
Plastic-55°Cto +125°C
VOO with Respect to VSS (Ground)
+ 15 to - 0.3V
Max. Voltage to any Input with Respect to VSS + 15 to - 0.3V
Operating Temperature
O°C to 70°C
Power Dissipation
1 W
OPERATING CHARACTERISTICS
TA = O°C to 70°C, VOO = + 12.0V
SYMBOL
±
.6V, VCC
= + 5.0V
CHARACTERISTIC
±
.25V, VSS
MIN.
= OV
TYP.
MAX.
UNITS
CONDITIONS
III
Input Leakage
10
uA
VIN
ILO
Output Leakage
10
uA
VOUT
ICCAVE
VCC Supply Current
68
100
rnA
IOOAVE
VOO Supply Current
17
25
rnA
VIH
Input High Voltage
VIL
Input Low Voltage (All Inputs)
VOH
Output High Voltage
VOL
Output Low Voltage
2.4
= VOO
= VCC
V
.8
V
V
10
.4
V
10
2.8
= -100uA
= 1.6 rnA
2001/2002·05 500KHz CLOCK
AC CHARACTERISTICS
TA = O°C to 70°C, VOO = + 12.0V ± 0.6V, VSS
SYMBOL
= OV, VCC = + 5.0 ± .25V
CHARACTERISTIC
MIN.
TYP.
MAX.
UNITS
CONDITIONS
READ
TACS
AO, CS Set up to RE+
TROV
RE + to OAL (COP) Valid
TRO
RE Pulse Width
TOF
RE t to OAL Float
TACH
AO, CS Hold From RE t
100
ns
500
500
ns
CLOAO
= 50PF
CLOAO
= 50PF
ns
250
50
ns
0
ns
ns
WRITE
TACS
AO,
CS Set up to WE +
100
TOVW
OAL (COP) Set up to WE t
300
ns
TWR
WE Pulse Width
300
ns
TOH
OAL (COP) Hold From WE t
90
ns
TACH
AO, CS Hold From WE t
0
HAND·
SHAKE
TO
KR (OIR) +, KA (OIA) + From WE +
KR (OIR) t, KA (OIA) t From WE t
OOR +, OOA + From RE +
DOR t, OOA t From RE t
450
NOTE: All output timing specifications reflect the following: High Output 2.0V
Low Output 0.8V
546
700
ns
2001/2002·20 2MHz CLOCK
AC CHARACTERISTICS
o
TA
ooe to 70 e, VDD
=
= + 12.0V ± 0.6V, Vss = OV, Vee = + 5.0 ±
SYMBOL
CHARACTERISTIC
MIN.
TYP.
.25V
MAX.
UNITS
CONDITIONS
READ
TACS
TRDV
TRD
TDF
TACH
AO. CS Set up to FiE+
FiE +to DAL (CDP) Valid
80
FiE Pulse Width
FiE t to DAL Float
AO, CS Hold From FiE t
330
ns
330
ns
CLOAD
= 50PF
CLOAD
= 50PF
ns
30
200
°
ns
ns
WRITE
CS Set up to WE +
TACS
AO,
80
ns
TDVW
DAL (CDP) Set up to WE t
200
ns
TWR
WE Pulse Width
200
ns
TDH
DAL (CDP) Hold From WE t
90
ns
TACH
AO,
CS Hold From WE t
°
HAND·
SHAKE
TD
KR (DIR) +, KA (DIA) +From WE +
KR (DIR) t, KA (DIA) t From WE t
DOR +, DOA +From FiE +
DOR t, DOA t From FiE t
300
450
ns
NOTE: All output timing specifications reflect the following: High Output 2.0V
Low Output O.SV
2001/2002·30 3MHz CLOCK
AC CHARACTERISTICS
o
TA
ooe to 70 e, VDD
=
= + 12.0V ± 0.6V, VSS = OV, Vee = + 5.0 ±
SYMBOL
CHARACTERISTIC
MIN.
TYP.
.25V
MAX.
UNITS
CONDITIONS
READ
CS Set up to R8
TACS
AO,
TROV
RE +to DAL (COP) Valid
ns
TRD
FiE Pulse Width
TOF
RE t to DAL Float
TACH
AO,
CS Hold From FiE t
TACS
AO,
CS Set up to WE +
50
ns
TDVW
DAL (CDP) Set up to WE t
130
ns
TWR
WE Pulse Width
175
ns
TDH
DAL (COP) Hold From WE t
60
ns
TACH
AO,
50
220
ns
CLOAO = 50PF
ns
300
20
130
°
ns
ns
WRITE
CS Hold From WE t
°
HAND·
SHAKE
TO
KR (DIR) +, ~ (OIA) +From WE +
KR (DIR) t, KA (OIA) t From WE t
DOR +, OOA +From FiE +
DOR t, DOA t From FiE t
150
NOTE: All output timing specifications reflect the following: High Output 2.0V
Low Output O.SV
547
~
300
ns
CLOAD = 50PF
=e
c
N
8
6
0
0
.....
KR(OIR) .
i:C
r--
CS
:+-TOH
N
0
0
N
WE
OAL(COP)
KA(OIA)
TYPICAL KEY OR DATA REGISTER LOAD
OOR
cs
OAL(COP)
-----I(
"
""
TYPICAL DATA REGISTER READ & TIMING
A0
CS
RE
I+=- TRO - Ir-;!--,- TACH
--~I~~
TACS - :
I
OAL
(COP)
_________Jb____
---i,
-i, , ~CH
----(:~;
~~;----------~p------i
rI
.,
: -
-----+i----<
FLOPPY
DISK
DRIVE
MODEM
1-----+
I+--
:ec
8
......
ic
8
N
See page 725 for ordering information.
:e
c
8.....
~
C
N
8N
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Di{lital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
550
Printed In USA
WESTERN DIGITAL
CORPORATION
WD2001/2 Applications Note
"One Bit Cipher Feedback In A Synchronous System"
~NTRODUCTION
WD2001/2 TIMING REQUIREMENTS
The WD2001/2 Data Encryption device interfaces easily to
both microcomputer and hard-wired logic circuits. This Applications Note provides suggestions for the implementation
of a synchronous circuit to perform system timing in a one bit
cipher feedback application.
The WD2001/2 may be operated from a 2 MHZ clock. This
provides a fundamental time period of 500 nSec that easily
fits into the timing requirements for the device. For example,
the minimum pulse width for a read (RD) or write (WR) pulse
is 450 nSec.
SYSTEM TIMING CONSIDERATIONS
Generation of the RD or WR pulse can be directly obtained
from a synchronous device that transitions at each edge of
the synchronous clock (SYNCLK). Figure 1 illustrates the
timing relationship between SYNCLK and RD or WR.
The synchronous operation of a digital circuit often leads to
both minimal hardware count and simple, easy to understand
timing relationships. In addition, the concern over individual
device characteristics become non-critical through the use
of a worst case design approach. Common problems such
as race conditions and temperature sensitivity can be virtually eliminated by synchronizing all logical events to a well
defined clock edge.
T
=
Once the timing relationship is understood, the implementation becomes quite straightforward. The circuit of Figure 2
suggests a possible method of RD or WR generation.
PERIOD
(2M HZ)
SYNCLK
RDORWR~J
T
T1
L~
T3
T2
T1
T2
STATES
T1
T2
r~
---.J
r--I
~
Figure 1 SYNCLK, RD, AND WR TIMING RELATIONSHIPS.
551
+5V
SYNCLK
RIPPLE OUT I-------DC)--'
ENABLE T
LOAD 0 - - - - - - '
ENABLE P
SYNCIIRONOUS
CLOCK COUN"TER
2.2K
OA
74163
1--_ _----1
OB I----{;(>-----I
A
OC
OD
C
D
CLEAR
T STATE
COUNTER STATE
T1
13
T2
14
T3
15
Figure 2 RD AND
OB
OA
RD OR WR
wn TIMING GENERATION
FUNDAMENTAL TIMING SEQUENCES
The Load Key, Load Data, and Unload Data sequences are
highly similar. Figure 4 shows the logical flow associated
with the Key Load or Data Load, or Data Unload. The Data
Encryption Algorithm sequence can be derived from the timing associated with the other three sequences. For simplicity,
the DES timing is accomplished by counting groups of three
clock periods in a fashion similar to the method shown in
Figure 4. The logical flow for the DES timing is shown in Figure 5.
Any cryptographic implementation using the Data Encryption
Standard (DES) can be broken down into four fundamental
timing sequences. First, the key is loaded into the WD2001/
2 (Load Key). Second, the data to be encrypted or decrypted
is loaded into the device (Load Data). Next, the DES is executed. Finally, the result of the DES is unloaded from the
WD2001/2 (Unload Data). Figure 3 lists the timing requirements for each timing sequence.
SEQUENCE
NUMBER OF CLOCK PERIODS
Load Key
8 bytes x 3 clocks
Load Data
8 bytes x 3 clocks
24
DES
17 x 3 clocks
51
Unload Data
8 bytes x 3 clocks
24
Figure 3 FUNDAMENTAL TIMING SEQUENCES
552
TOTAL
24
•
T1
T2
T3
'>--_ _ _ _ _
)--_ _ _ _ _ DONE
Figure 4 KEY LOAD, DATA LOAD,
AND DATA UNLOAD FLOW
DONE
Figure 5 DES LOGICAL FLOW
and also highlights the three I/O operations. Note that the
Key Load sequence is outside of the tight loop.
SYSTEM TIMING OVERVIEW
The normal operation of a cryptographic system would require three classes of input/output (I/O) operations with the
WD2001/2. First, the key is loaded (Key Load) through eight
consecutive write cycles. Second, the data to be encrypted
or decrypted is loaded (Load Data) in a similar fashion. After
the Data Encryption standard is completed, the data is unloaded (Unload Data) through eight consecutive read cycles.
Typically, the Key Load sequence would occur much less
frequently than the Load Data or Unload Data sequences.
Using the four fundamental timing sequences as logical
building blocks, a functional block diagram of system timing
can be designed. Figure 7 illustrates the overall system timing functions.
An implementation of the functions shown in Figure 7 is suggested in Figure 8. Note that all timing transitions are synchronous with the rising edge of SYNCLK.
Figure 9 details the timing of the Load Key sequence, and is
similar to the Load Data, Unload Data, and DES sequences
also.
The flow diagram of Figure..6 shows the relationship between
the four fundamental timing sequences defined previously,
553
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o
o.....
N
I/O
1/0
YES
1/0
DONE
NO
YES
Figure 6 FUNDAMENTAL TIMING SEQUENCES INTERRELATIONS
-CONTROL lOGIC
(S x 3)
T
STATE
GENERATOR
T1, T2, T3
3
I
t
I
f
(17 x 3)
(S x 3)
j
RD
GENERATION
It
I II
WR
GENERATION
+
DES
COUNTER
!
t
Figure 7 SYSTEM TIMING BLOCK DIAGRAM
554
DATARQ
WIIll!I
!5rnlIJ
=
1. KEYLOAD RQ AND DATA RQ DO NOT OCCUR
SIMULTANEOUSLY.
2. ALL J·K PRESETS TO +5V.
3. ALL J·K CLEARS TO "RESET".
4. RESET SHOULD LOAD ALL 74LS163 COUNTERS.
Figure 8 SYSTEM TIMING IMPLEMENTATION
KEYLOADRO
iY~\\\'\\\\\
~
(NK)11
(1)
(2)
(3)
(8)
"
~n~ -1[----------1/J/-_ _ __
(a)
KEYON
(K)
KEYDONE
SYNCLK
~L---------------1~
----------------AFigure 9 SINGLE KEYLOAD SEQUENCE
555
of data, and hence the WD2001/2 can be used in a mUltichannel communications environment.
ONE BIT CIPHER FEEDBACK
The one bit cipher feedback (OBCFB) architecture is widely
used in Data Communications. The WD2001/2 device, when
operated with a 2 MHZ clock, will run at an effective bit rate
of over 19,200 bits/second, which is the practical upper limit
of many communications links.
In OBCFB, the WD2001/2 is always set to encrypt mode.
The selection of either the SOl as the feedback element to
the shift register, or the SDO as the feedback element, determines whether the incoming data is encrypted or
decrypted.
FUNDAMENTAL LOGICAL CoMPONENTS OF OBCFB
Another factor involved with OBCFB is the propagation of errors through a 64 bit block of data. Because of the 64 bit shift
register that feeds the INV, a single bit error will cause the
following 63 bits to be in error also. After the last bit of the 64
erred bits, the data will become resynchronized and the effect of the shift register will no longer cause bad data.
A one bit cipher feedback system can be broken down into
nine logical components, as listed in Figure 10.
NAME
DESCRIPTION
KEY
56 bit number that maps INV to OV
IV
Initialization Vector
INV
Input Vector
DES
Data Encryption Standard
OV
Output Vector
SOl
Serial Data In
SDO
Serial Data Out
SR
Shift Register (used with INV)
MOD2
Modulo 2 Adder
msb
DES (WD2001/2)
msb
of
OV
Figure 10
NINE FUNDAMENTAL COMPONENTS OF OBCFB
SOO
SOl
FUNCTIONAL DESCRIPTION OF OBCFB
Modulo 2
Adder
The OBCFB algorithm operates on a one bit wide data input,
hence it is ideally suited to seriai Data Communications applications. In encryption mode, the serial data in is added
modulo 2 with the most significant bit (msb) of the 64 bit output vector. The result of this operation is then fed into the
least significant bit (Isb) of a 64 bit shift register, and also is
used as the serial data output. The shift register is then
shifted from the Isb to the msb, and the result becomes the
next input vector. After the Data Encryption Standard is
completed, the process is repeated again for the next single
bit of serial input data. Because each serial data bit requires
an entire 64 bit INV and OV, the effective bit rate of this operation is 64 times less than that of a operation which uses
all 64 bits of the OV, such as Code Book. Figure 11 shows a
block diagram of a OBCFB circuit operating in encryption
mode.
Figure 11
OBCFB ENCRYPTION BLOCK DIAGRAM
msb
DES (W02001/2)
msb
of
OV
To decrypt, the operation is changed in one way. Instead of
feeding the result of the modulo 2 adder to the shift register;
the unmodified serial data is used. All other operations are
identical. Figure 12 shows a circuit which supports both encryption and decryption.
SOl
Because the OBCFB algorithm uses a 64 bit shift register on
the INV, each SDO bit is a function of its corresponding SOl
bit and the 64 previous operations. This implies that the past
history of the encryption operation is necessary to initialize
a system. The IV is used to supply the history required to allow immediate use of the OV from the DEA. Typically, the IV
is either a predefined value, or the last 64 SDO bits from the
data stream being encrypted or decrypted. This allows the
encryption process to be accomplished with discrete blocks
r-~--------------+---- SOO
SOO if ENCRYPT
SOl if OECRYPT
Figure 12
OBCFB ENCRYPTION/DECRYPTION BLOCK DIAGRAM
~i56
ONE BIT CIPHER FEEDBACK IMPLEMENTATION
Digital FR1502 FIFO and some common TTL logic.
Since the WD2001/2 is a byte input/output oriented device,
the implementation of a OBCFB circuit can be accomplished
without the 64 bit shift register shown in Figures 11 and 12.
Through the use of a 9 bit wide FIFO, a "virtual" 64 bit shift
register can be built. Figure 13 illustrates this with a Western
Once the modulo 2 adder, the encrypt/decrypt selector, and
th~ shift register are defined, the overall circuit can be generated by combining these pieces along with the logic shown
in Figure 8. The overall block diagram of the one bit cipher
feedback system !s given in Figure 14.
WRON ·T2
r-
IRO
!!'
:3
IR3
ORO
OR2
FR1502
IR4
OTHER
!
LU
o
OR3
WR
2:1 MUX
OR1
IR1
IR2
TO
~
SDI
OR
SDO ON WR #7
~b
Fii50N·T1
SR
A
.
B
C
OR4
D
OR5
E
IR6
OR6
F
(31
IR7
OR7
G
GO
IRB
ORB
H
74LS299
IR5
DEVICES
FIFO
r
WRON • T2
SI
OPERATION
T1
UNLOAD SHIFT REG
T2
LOAD SHIFT REG FROM FIFO
T3
SHIFT RIGHT
(msb)
D7
D6
D5
D4
D3
D2
D1
DO
(Isb)
WD2001/2
'VIRTUAL" 64 BIT SHIFT REGISTER
Figure 13 "VIRTUAL" 64 BIT SHIFT REGISTER
557
WRON . T1
I
WRON· T1
WR
SO
---.J
--
RD
OPERATION
T1
LOAD FIFO FROM WD 200112
T2
NO OP
T3
NOOP
WR#7
ENCRYPT/DECRYPT _
2: 1
2: 1
MUX
MUX
LSB
SDO
SDI
SR
SHIFT
REGISTER
FR1502
FIFO
D7, MSB
T1
T2
DATA
BUS
T3
RD #1 (MSB)
SYSTEM
TIMING
WR #7 (LSB)
WD2001/2
Figure 14 OBCFB SYSTEM BLOCK DIAGRAM
CONCLUSION
RELATED DOCUMENTS
The WD2001/2 device lends itself readily to the most common of all Data Communications encryption techniques, The
one bit cipher feedback algorithm can be implemented easily
through the use of synchronous timing generation and circuit
design techniques,
WD2001/2 Data Sheet, Western Digital Corporation
FIPS 46
Federal Information Processing Standard
National Bureau Of Standard
Department of Commerce
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from Its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
558
Printed In U.S.A
WESTERN DIGITAL
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Cipher Feedback Cryptography Technical Note
Q
."
:E:
m
:0
This output is stored in a shift register(S) with the most significant bit (MSB), to the left and the least significant bit on
the right.
CIPHER FEEDBACK CRYPTOGRAPHY
The United States Government in proposed Federal Standard 1026 describes three different approved ways of using
the National Bureau of Standard's Data Encryption Standard
(DES): Electronic Codebook; Cipher Feedback; and Cipher
Block Chaining. Western Digital's WD2001 and WD2002, as
delivered, implement the DES in Electronic Codebook Mode.
This Technical Note will describe how to build an "N" bit
Cipher Feedback (CFB) circuit using the WD2001.
The MSB of S is added modulo 2 to the first bit of plain text
to produce the first cipher bit. The contents of R are shifted
1 bit to the left and the just created cipher bit is inserted as
the least significant bit (LSB) in R. The cipher bit is now available for buffering, transmission, etc.
WHAT IS CIPHER FEEDBACK?
The above procedure is repeated until the entire message
text is encrypted, one bit at a time.
-n
m
m
c
CD
The new contents of R are now loaded into the WD2001 as
data, encrypted, and the new output placed in S.
Cipher feedback cryptography produces, as a function of
previous cipher text, a pseudorandom bit stream which is
added modulo 2 to the plain text to produce the next cipher
toxt.
»
o
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:0
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:E:
DECRYPTION
Decryption is accomplished in a similar manner: the IV is
stored in R; loaded into the WD2001 as data; ENCRYPTED
(even though the operation on the message text is to be
decrypted); the results stored in S; and R shifted 1 bit to the
left. Now, because the unit is receiving cipher rather than
creating it, the first received bit is placed in the LSB of R. This
cipher bit is also added, modulo 2, to the leftmost bit in S to
reproduce the original plain text.
DES IN CIPHER FEEDBACK (CFB)
Obviously, both the receiver and transmitter must start their
cryptographic operation with the same cryptographic keys to
be able to acquire and maintain crytographic synchronization, i.e. produce the same pseudorandom bit stream at the
same point in time.
For DES this means that both the 64 bit cryptographic variable (56 bit key) and the initial input to the algorithm must be
identical at both ends. The initial input to DES in CFB is
called the Initializing Vector (IV). Its format and generation
are described in detail in Federal Standard 1026.
NOTES
Of particular significance is that the DES chip is in the
ENCRYPT mode for CFB cryptography regardless whether
the operation is to be performed to create cipher text or to
recreate plain text. This is because the DES is being used to
generate a pseudorandom bit stream. It is the exclusive OR
operating on that bit stream and the received text which
accomplishes the actual encryption/decryption of data.
The functional description of using the WD2001 in CFB
mode below assumes that communication synchronization
has been achieved; that identical decrypted IV's and cryptographic keys are available to both the transmit and receive
ends of the link; that encryption is to be a 1 bit Cipher feedback; and that the plain text character size (1 in the example)
equals the transmitted character size (Method A in proposed
Federal Standard 1026).
S was nominally defined to be 64 bits long. It need be no
longer than the number of text bits to be exclusive OR'd at
one setting of the pseudorandom stream. In the example it
was one bit. In reality it could be any character or block size
from 1 to 64 bits long.
ENCRYPTION
The convention used in this note is to organize a shift register
with the MSB to the left. In practice, what is important is to
use the MSB of S for the MOD 2 add ition and to shift the R
register content, so that the MSB is dropped and the cipher
bit becomes the LSB. It is also important to perform the shift
and generate a new pseudorandom block after each character has been encrypted or decrypted .
At time 0, the 64 bit cryptographic variable is loaded into the
WD2001 with the key load sequence. A 64 bit block consisting of not more than 16 leading O's and the 48 bit (or longer)
IV is loaded into a 64 bit shift register (R) and into the input
register, as if it were data, and encrypted. The WD2001 will
automatically encrypt the IV under control of the cryptovariable and present a 64 bit block, 8 bits at a time as output.
•
559
-<
Q
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::I:
m
OTHER CIPHER FEEDBACK METHODS
APPLICATIONS OF CFB
Cipher Feedback can be done for any feedback size of 1
through 64 bits. One bit cipher feedback has the overall advantage of being transparent to the data being protected.
In the data communications world error extension and selfsynchronization are not important because of the excellent
conditions of the lines and the protocols and error correcting
codes used to insure proper receipt of data. In some applications, these properties of CFB cryptography can be turned
to the user's benefit. This is especially true in situations
where the data stream contains highly redundant information, where an incorrect recovery of 64 bits is hardly
noticed-particularly when compared with the overall communications benefit of having the cryptography automatically
resynchronize itself.
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CHARACTERISTICS OF CFB
CFB has two properties which must be considered when selecting it for data encryption: 1) error extension and 2) self
synchronization. Both of these properties exist because the
encryption process synchronizes on the received cipher to
produce the pseudorandom bit stream.
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WD2001 CHARACTERISTICS IN CFB
In the case of DES in one bit CFB, a one bit error in the received cipher message will affect the next 64 pseudorandom
blocks-it will take 64 iterations to shift the one "bad" bit out
of the 64 bit register above. If 8 bit CFB is used, then only 8
blocks will be affected, but that will still represent 64 bits used
to decrypt incoming data.
The WD2001 is rated as having 1.304 megabits per second
throughput when driven by a 2 MHZ clock. This figure is
based on processing 64 bits of data at each operation. Using
the WD2001 in an 8 bit cipher feedback circuit will reduce
that to 163 kilobits per second. A 1 bit cipher feedback circuit
would further reduce effective throughput to 20.385 kilobits
per second. This is true of any DES implementation. The algorithm is designed to process 64 bits of plain (cipher) text at
a time to produce 64 bits of cipher (plain) text; cipher feedback is designed to operate on a basic character size and
shift after that character has been encrypted. In the 1 bit
case, the user "throws away" 63/64ths throughput capacity
for each encryption.
::I:
-<
In the same way, receiving 64 consecutive good bits of
cipher will have filled the data-in register on the receiver end
with the same 64 bits of data as in the transmit unit and
proper decryption can again take place, assuming both ends
have the same cryptographic key. This is what is meant by
self-synchronizing.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility Is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
560
Pronted
In
u.s A
Microcontrollers
Part Number
Page
WD51
Irrigation Controller ..................................................
WD55
Industrial Timer/Controller .............................................
WD4200IWD4210 and
WD4320/WD4321 Single Chip N·Channel Microcontrollers ..................................
4 Bit Microcomputers ................................................
561
563
571
585
609
!;62
WESTERN DIGITAL
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--
WD51 Irrigation Controller
.................................................................
FEATURES
GENERAL DESCRIPTION
o CONTROLS UP TO 6 IRRIGATION STATIONS
o PUMP CONTROUMASTER VALVE OUTPUT
Preprogrammed Controller for Irrigation Applications.
The WD-51 is a single-chip controller preprogrammed to
operate a 6 station irrigation system. It is implemented
using P-channel silicon gate MOS/LSI technology and
requires minimal support circuitry. All program and data
storage are on-chip, as well as input switch matrix scan, 7
segment display decode and drive, and output control
logic.
o USER PROGRAMMABLE FOR UP TO 3 WATERING
CYCLES DURING A 24 HOUR DAY
4. USER PROGRAMMABLE RUN TIMES OF 1 TO 99 MINUTES FOR EACH STATION
4. USER SELECTION OF WATERING DAYS OF 0 TO 7
DAYS PER WEEK
4. TIME OF DAY AND DAY OF WEEK CONTINUOUSLY
FUNCTIONAL DESCRIPTION
The logic symbol and block diagram of the WD-51 is
shown in Figure 1.
DISPLAYED
4. RAIN INHIBIT MODE
It
EASY TO DESIGN IN
VSS
40
SEG F
SEG E
39
SEGG
SEG 0
38
07
SEG C
37
06
SEG B
36
05
SEG A
35
04
34
03
33
RESET
02
ROM
7 SEGMENT
OUTPUTS
SCAN
INPUTS
01
10
WD51
O~
OMUX
INS
11
IN3
12
IN2
13
IN1
14
50 Hz
IN~
15
60 Hz
CPU
CONTROL
OUTPUTS
16
STN3
17
PUMP
STN2
18
STN6
STN1
19
STNS
VOO
20
STN4
RAM
[
LATCHED
INPUTS
FIGURE 1 BLOCK DIAGRAM
563
SCAN
OUTPUTS
PIN DESCRIPTION
:ec
en
.....
FUNCTION
PIN NO.
SYMBOL
VSS
1
Voo
20
Positive Supply voltage
Negative Supply voltage
2-6,39-40
Seg A,B,C,
D,E,F,G
--RESET
Decoded 7-Segment Multiplexed outputs,
15 mA source.
A low-level input voltage resets internal logic and
initializes RAM data.
8
12-15
INO, 1N1, 1N2,
1N3
Scanned inputs, 1N3 is MSB
Station Output control for solenoid drivers.
17-19,21-23
STN 1,2,3,
4,5,6
PUMP
24
Pump control output- a high-level output indicates
a manual or automatic cycle is in progress.
60HZ
26
60 HZ time base input
50HZ
27
50 HZ time base input
DMUX
30
4-digit display control output
DO-D7
31-38
Digit scan outputs, (D7= MSD, DO = LSD)
I
1
t - - - TCYC ~
INTERNAL
I !
CLOCK
1
i
1
1
!
I
- - - - - : . , 1 1d
INS, 00.0 7
I~
I
-j
1_
f'l.
t, 2, 3,
1
- l I-- ld
Id
it=-----t------=.=.:.""'---
-'N-O_'N3---ni*~L~O
~~~
I
VALID F(J-A-4X-C-LO-CK-T-,M-E---i----'-='-'.:::.::.:.:..--y_
I x ..
1 I
I
II
~~~_r:~:~~~TC~HF=.D~IN~TE~A=NA~L~LY~O=N=AI~S,=NG~E~DG=E~A~TA~N~Y~TI~ME~~
_________~!-~I I
___
VIH
I
:
--"'--_ _ _ _ _ _- + : _ - t : G , T l O N OCCUAS ON ANY
CLOC~
I
I
I
I
I
___
TIME
I
~-rl----(,~)-----~I-~
I
-----'1----11
_S=EG~ME=NT~SI=NO~TE~21_ _ _ _~:~1----------------h:I~
Ii
-l
r-
-j
ld
FIGURE 2
NOTE 2 SEGMENT OUTPUTS ARE VALID DURING CLOCK TIMES 1 TO 3 ONLY
THEY ARE LOWATTIMEO
TIMING DIAGRAM
564
(NOTE
1)
Vil
___________
I-
ld
INPUTS
IINPUT SWITCH MATRIX-The WD-51 may be used with
any switch configuration which is matrix compatible, such as
a keyboard, rotary switch, slide switch, or combinations of
both. All multiplexing and decoding is performed on-chip,
thus requiring no external components, other than the switch
matrix.
07
(38)
06
(37)
SETTING DAY OF WEEK-If SET DAY is depressed in conjunction with ADVANCE, the Day digit (04) will increment,
with rollover from 7 to 1. Note that since the day is numerically displayed (as opposed to alphanumeric), the numbering
is arbitary, i.e., if Sunday is considered to be "1", then
Wednesday is "4", Friday is "6", etc.
DIGIT SCAN TIME OUTPUTS
05
04
03
(34)
(36)
(35)
02
(33)
DO
(31)
01
(32)
- - - - - ,._--.<---
INO
(15)
ADVANCE
3-STATION
STRAP
IN2
(13)
ACTIVE
DAY
3
START
TIME
#1
RUN TIME RUNTI ME
#2
#5
ACTIVE
DAY
3
START
TIME
#3
RUN TIME RUNTI ME
#3
#6
ACTIVE
DAY
5
SET DAY
ACTIVE
DAY
6
SKIP
-A-DAY
ACTIVE
DAY
7
SET
HOURS
--
RUN TIME RUNTI ME
#4
#1
ACTIVE
DAY
1
- - - - - - - - r----------
IN1
SCANNED (14)
INPUTS
START
TIME
#1
ACTIVE
DAY
4
SET
MINUTES
- - - - - r----------
--1--
-~
----
IN3
(12)
FIGURE 3
MANUAL
OFF
----
MANUAL
ON
---
--
RU N
INPUT SWITCH MATRIX
The basic functions of the Irrigation Controller are selected by one or more switches as defined in Figure 2.
Inputs INO-IN3 form a 4 bit wide input port which is
scanned by the Digit Scan Outputs 00-07, forming an 8
x 4 matrix which connects to the user-supplied keyboard/
switches.
SETTING START TIMES-There are up to 3 automatic
watering cycle times available in a 24 hour period. To examine them, START TIME 1, 2, or 3 is selected and displayed in hours on digits 07 and 06. If it is desired to change
the data, the ADVANCE key is depressed. The rollover is
from 24 to 00, with 00 being a start-time "skip" value. Thus
1, 2, or 3 cycles per day may be selected.
SWITCH FUNCTIONS-The switch functions shown in Figure 3 are defined as follows:
SETTING RUN-TIMES-Each one of 6 stations may be set
to a run time of 0 to 99 minutes, with 00 being a "skip station"
value. To examine the stored data, the desired station RUN
TIME key (1-6) is selected with the time in minutes being
displayed on digits 07 and 06. To change the data, the ADVANCE key is depressed. The selected run time will then
increment with rollover from 99 to 00 minutes.
ADVANCE-For all setting operations, a common key is
used to increment the selected data (time, day, start-time, or
run-time). Immediately after the detection of the advance
switch, the data increments by 1, waits 1% seconds, then
begins incrementing at the rate of 3 per second. This allows
the operator to move rapidly to the desired value without
"overshooting" and then "tapping" the advance key when
close to the find value.
SETTING ACTIVE DAYS-The WD51 reads active day information from the switch matrix, with typically slide, toggle,
or "DIP" switches being used. An automatic watering cycle
may be set for 0 to 7 days a week simply by closing the
switch for the respective day. An ALTERNATE DAY switch
position is provided, which, when activated, causes the controller to ignore the 7 active-day switches and to run an
automatic cycle every other day.
SETTING TIME OF DAY-Two separate switch inputs for
setting hours and minutes in conjunction with the ADVANCE
key. If SET MINUTES is selected while ADVANCE is depressed, the minutes dig!is (DO & 01) will increment. Minutes
rollover is from 59 to OO..vith no carry into the hours. If SET
HOURS is selected whii;) ADVANCE is depressed, the hours
digits (02 & 03) will advance. Hours rollover is from 24
to 01, with midnight equal to 2400.
MANUAL ON-This switch position immediately activates
a timed watering cycle beginning with station No.1, regardless of the setting of the start-times or active days. The run
times programmed for stations 1-6 are automatically run.
565
:ec
en
......
The selected station (1-6) is shown in digit 05. The station
number is displayed when a RUN-TIME key is depressed or
the controller is active during a manual or automatic watering
cycle; otherwise a zero is displayed.
The cycle may be terminated anytime with the MANUAL OFF
key. If it is desired to start with a specific station other than
station No.1, that station ONE-TIME-key should be depressed first, then the manual key. The cycle will then begin
at the selected station and continue through station NO.6.
The start time and run times are displayed in digits 06
and D7. When any of the start-time switches are selected,
the D6 and D7 digits display the hour of the day the
watering cycle is to start. If a run-time switch is activated,
the selected station run-time is displayed in a minutes
format. During a manual or automatic watering cycle, the
time remaining for the currently active station is displayed
in minutes. Otherwise, 00 is displayed.
RUN MODE-This is the normal automatic operating mode
of the Irrigation Timer. When in this mode, the START and
RUN-TIME data cannot be displayed or modified, preventing
accidental erroneous entry of data.
RAIN INHIBIT (MANUAL OFF)-This switch is used to cancel or prevent a watering cycle, either manual or automatic.
When activated during a current cycle, it immediately turns
off all station outputs and returns to a time-keeping mode
only. With external signal conditioning circuitry, this input
could be used to interface with a moisture or rain sensor.
This function is normally implemented by paralleling a toggle
switch ("rain") with a momentary key ("manual off").
STN1-STN6-The station outputs are latched logic outputs
designed to control the solenoid drives in an irrigation system. These outputs are normally a low-level voltage (solenoid drive is off). When a manual or automatic watering cycle
occurs, the appropriate station output goes to a logic "high"
voltage for the selected run-time interval. Station-to-station
switching is essentially instantaneous. It is recommended
that these outputs be buffered by a current driver to supply
sufficient current for triacs, relays, or other high-power
switching devices.
3 STATION OPTION-By connecting IN3 to 05 through a
diode, run times for Stations 4, 5 and 6 will be continuously
set to zero, thus they will always be skipped. Also, if switch
positions for Run Times 4, 5 and 6 are not provided to the
user, these stations cannot be examined.
PUMP CONTROL OUTPUT-This output is a latched logic
output which is normally a logic "low" voltage for the pump
off condition. It goes to a logic "high" voltage at the beginning
of a watering cycle, either manual or automatic, and remains
high until the last station goes off. With suitable buffering, this
output may be used to turn a pump motor on and off when
needed or simply to drive a "cycle on" LED status indicator,
or to act as a "master valve" output.
RESET-This is the reset input of the micro-controller. An
external capacitor of approximately 2 p.,f is recommended
between 8 and VOO to generate a reset signal when power
is first applied.
OUTPUTS
DISPLA V SEGMENT OUTPUTS (SEG A-SEG F)-The
WO-51 is designed to directly drive vacuum flourescent
(V-F) displays or common-cathode LED displays up to 0.3
DMUX OUTPUT-This output, in conjunction with minimal
external logic, provides a means of using a 4 digit display
with the W051. It is a logic high when a RUN-TIME, START-
DIGIT SCAN TIME
D7
START/RUN
TIME
(MSD)
D6
D5
D4
D3
START/RUN
TIME
(LSD)
STATION
NUMBER
DAVOF
WEEK
10's
D2
T
FIGURE 4
HOURS
I
HOURS
I
DO
Dl
I
M
E
10's
MINUTES
MINUTES
I
DISPLAY REGISTER
inches. The seven segment outputs are high current outputs
and are multiplexed in synchronization with DO - 07 with sufficient interdigit blanking to prevent "ghosting". The display
register is shown in Figure 4.
TIME, or SET-DAY key is depressed and a logic low voltage
at all other times, hence it may be used to externally select
digit times 04-07 when high and 00-04 when low.
The time of day is displayed as a four digit number in 24
hourformat(9AM = 0900,5PM = 1700, MIDNIGHT =
2400, etc.} and the day of the week is displayed as a
number between 1 and 7. The time and day are continuously displayed regardless of the mode selection. Zero
blanking is not provided for any of the digits.
DEFAULT INITIALIZATION-Upon the occurrence of a
RESET the micro-controller defaults to the following: Time
of day to 12:00; day to 1; start time 1 to 0200 hours; start
times 2 and 3 to 00; and run time 1-6 to 10 minutes each.
Thus if power is lost to the microcomputer, a default program
will be executed without user intervention.
E66
SPECIFICATIONS
Absolute max.imum ratings indicate limits beyond which
damage to the device may occur. DC and AC electrical
specifications are not ensured when operating the device
at absolute maximum ratings.
ABSOLUTE MAXIMUM RATINGS
Power Dissipation 2.5 Watt at 25°C
Positive Voltage on any Pin with Respect to
VSS: +O.3V
Negative Voltage on any Pin with Respect to
VSS: -20.0V
Operating Free-Air Temperature
TA Range ............................... O°C to 70°C
l.ead Temperature (Soldering, 10 sec.) ............ 300°C
Storage Temperature ...... -65°C to + 150°C (Ceramic)
-55°C to +125°C (Plastic)
E:LECTRICAL CHARACTERISTICS
TA
= 25°C, VSS-VOO = 13.2V unless noted otherwise
PARAMETER
Operating Voltage
(VSS-VOO)
Operating Current
Input Voltage Levels
All Inputs Except INO-IN3
Logic High (VIH)
Logic Low (V/u
Inputs INO-IN3
Logic High (V/SH)
Logic Low (VISL)
Output Voltage Levels
All Outputs Except 00-07
and SEG A-SEG G
Logic High (VOH)
Logic Low (VOL)
00-07 Outputs
Logic High (VOOH)
VOOl
Seg Outputs Seg A-G
Segment Output Current
Seg A-G IOSH
MIN
CONDITIONS
All inputs and
outputs open
11.5
Note 1
TYP
13.2
MAX
UNITS
14.5
V
6
15
mA
'Vss-1.0
VOO
Vss
Vss-4.2
V
V
Vss-3.75
VOO
Vss
VSS-9.0
V
V
Note 2
IOH = +100 flA Min.
IOl = -1.6 mA Min.
Vss-1.0
VOO
VSS
Vss-4.6
V
V
IOOH = 1.5 mA+1 Input
(lNO-IN3)
IOOH = 5.0 mA+1 Input
Note 3
IOSH=16 mA
VSS-1.5
VSS-3.0
VSS
VSS
V
V
Vss-3.5
Vss
Vss-6.0
V
V
Note 3
10
40
mA
500
flsec
flsec
msec
HZ
AC Electrical
TCYC
Instruction Cycle Time
td/tw
t~
TBase
15
10
5.0
15
0
60
Note 1: Internal Pullup Resistors of Approximately 6K to VSS Across Each Input.
Note 2: Internal Pulldown Resistors of Approximately 12K to VOO Across Each Input.
Note 3: Single Transistor to Vss Output Only.
567
IN4002
7812
115VAC
SO/60
----L
07
05
02
---1~
01
,[ ;?~
MSO
LSO
1----.1
1511•..,
.""V SS
IrtJj ::1'
--ii------tIB
=
VSS
~I-
L
10K
RESET
2
-..j...-~j~~~~RON I
OAY7
D4
=
~
19
OVR1
I
.
STN1
!
L-----,
co
CO
ioO
w'v'::J5~
.
011'
OVR2
SAO
-1
-:-
~8ISTN2
~I
05-0·
+11'F
IN3
rfl
__
II:
:~
021
oo~
D4
35
05
36
D6
37
07
38
[~~
ETC.
PUMP
24
~ Sv~
=~
0.1
4.7K
-:-
220
1~'?
-=-
FIGURE 5 COMPLETE 6-STATION IRRIGATION CONTROLLER
WD51
COM CATHOOE
LEOS
I
SEG a
SEG b
SEG c
SEG d
SEG e
SEGf
SEG 9
Y
SS
6
uD
5
0:0 DdJ be
oCJaDc;=JD
O~D ~D
rl
2
40
39
c::>
W051
Y
ss
ULN2004
01 32
B1
02
02 33
03
A2
34
05 36
37
06
38
07
30
c---
OMUX
Y
03
A3
PUMP
"-
4019
B2
04 35
24
./
{>:~
~1
K
A1 a
O~ 31
B3
04
A4
---~-
1./"'"
,.----'
I~
FIGURE 6
.-.-~
WD51 WITH 4-DIGIT DISPLAY OPTION
I
VSS
SEG a
SEG b
SEG c
SEG d
SEG e
SEG I
SEG 9
6
5
4
3
2
40
39
MULTIPLEXED
___ (J~~~L!~_LL~""~'
(
r----'"",---'
WD51
""'----
t-...
,-~~~
I)
./'
VF1L
DO 31
----
··
·
Dl 32
IIC=~
D5 36
D6 37
D7 38
~
... ~
~
~
...
Vz
~
~
10-SO K
-:-
.~--~---~-
V
DD
r
FIGURE 7
WD51!VACUUM FLOURESCENT
(V-F) DISPLAY INTERFACE
569
RS
~VGG
~
C
(J'I
.....
See page 725 for ordering information.
:ec
UI
.....
Information furnished by Western Digital Corporation is believed to be ac'~urate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
fi70
Printed
In
U.S.A
WESTERN DIGITAL
c
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P
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WD55 Industrial Timer/Controller
FEATURES:
APPLICATIONS:
• LOW COST PRE PROGRAMMED MICROCONTROLLER
• USEABLE WITH KEYBOARD OR DISCRETE
SWITCHES
• HIGH CURRENT LED OUTPUTS OR DIRECT
DRIVE OF VACUUM FLUORESCENT (V-F)
DISPLAYS
• UP TO 7 SEQUENTIAL OUTPUTS
• SYNCHRONIZED WITH 50/60 HZ TIME BASE OR
EXTERNAL OSCILLATOR
• SINGLE TIME OPTION
• CONTINUOUS OR SEMI-AUTOMATIC OPTION
• DEDICATED TIMER OPTION-WORKS WITHOUT
KEYBOARD OR DISPLAY
• RESOLUTIONS OF FROM 0.1 SEC. TO 999
HOURS WITH DIGITAL ACCURACY
• ALARM OUTPUT FOR AUDIBLE BUZZER
• RELAY AND TRIAC OUTPUTS
• AUDIBLE FEEDBACK FOR USE WITH MEMBRANE SWITCHES
• 100 MW TYPICAL POWER CONSUMPTION
•
•
•
•
•
•
•
•
•
•
•
•
•
•
en
en
DARKROOM TIMER
PROCESS CONTROLLER
PROCESS SEQUENCER
TIME DELAY RELAY
APPLIANCE TIMERS
DEFROST CONTROLLERS
"DRIP" AND "MIST" IRRIGATION CONTROLLERS
ON/OFF TIMER
DIGITALLY CONTROLLED TIME DELAY
TRAFFIC LIGHT SEQUENCER
SECURITY SYSTEMS
LIGHTING CONTROL
INTERVAL TIMER
RECYCLING TIMER
VSS
40
SEG F
SEG E
39
SEG G
SEG 0
38
07
SEG C
37
06
SEG B
36
05
SEG A
35
04
34
GENERAL DESCRIPTION
The WD-55 is a versatile, self-contained digital timer/
controller/sequencer designed to replace many of the
timing and control functions currently being performed
by gears, cams, levers, and motors. It is another in a
series of "silicon software" preprogrammed microcontrollers based on the WD40 family of 4-bit microprocessors. The WD-55 may be used in conjunction with
a matrix keyboard and numeric display to implement
a programmable timer/sequencer or with suitable
"strap" options, may be used as a dedicated, standalone on/off controller. It is implemented in P-channel
Silicon Gate MOS and is available in 40 pin plastic and
ceramic DIP packages.
f:iEsET
32
ClK
03
02
10
01
31
iNs'
11
30
SEQ5
IN3
12
29
E,E06
IN2
13
28
~;E07
IN1
14
27
TRIG
INO
15
26
T BASE
03
16
25
ALARM
02
17
24
SEQ4
OUT
18
23
t;EQ3
OUT
VOO
19
22
8EQ2
20
21
SEQ1
FIGURE 1.
WD-55 PIN CONNECTION
571
WD-55 PIN DESCRIPTION
:e
PIN NO.
c
(J1
(J1
I
SYMBOL
FUNCTION
1
VSS
+-V
2
SEG E
One of 7 high current (20 MA source) outputs for
direct lED drive
3
SEG D
One of 7 high current (20 MA source) outputs for
direct lED drive
4
SEG C
One of 7 high current (20 MA source) outputs for
direct lED drive
5
SEG B
One of 7 high current (20 MA source) outputs for
direct lED drive
6
SEG A
One of 7 high current (20 MA source) outputs for
direct lED drive
8
RESET
Power turn-on reset input, active low
10
ClK
Internal RC clock oscillator output, approx. 100
KHZ
11
INS
Input select, not used in this application
12
IN3
Scanned input, MSB
13
IN2
Scanned input
14
IN1
Scanned input
15
INO
Scanned input, lSB
16
Q3
Latched output, not used in this application
17
Q2
Latched output, not used in this application
18
OUT
Timer output, active low
19
OUT
Timer output, active high
20
VDD
-V
21
SEQ1
One of 7 sequencer outputs, active high during
preset timing interval 1
22
SEQ2
One of 7 sequencer outputs, active high during
preset timing interval 2
23
SEQ3
One of 7 sequencer outputs, active high during
preset timing interval 3
24
SEQ4
One of 7 sequencer outputs, active high during
preset timing interval 4
25
ALARM
Audible alarm control output, active high
26
TBASE
Time base input, used as reference for all timing
modes
27
TRIG
Trigger input, used in on/off mode, rising edge
sensitive
28
SEQ7
One of 7 sequencer outputs, active high during
preset timing interval 7
29
SEQ6/TIM2
One of 7 sequencer outputs, active high during
preset timing interval 6
~i72
WD-55 PIN DESCRIPTION (Continued)
PIN NO.
SYMBOL
:ec
FUNCTION
30
SEQ5/TIM1
One of 7 sequencer outputs, active high during
preset timing intervalS
31
DO
Digit output, LSD
32
D1
Digit output
33
D2
Digit output
34
D3
Digit output
35
D4
Digit output
36
D5
Digit output
37
D6
Digit output
38
D7
Digit output, MSD
39
SEG F
One of 7 high current (20 MA source) outputs for
direct LED drive
40
SEGG
One of 7 high current (20 MA source) outputs for
direct LED drive
FUNCTIONAL DESCRIPTION
which have little or no tactile feel. The debounce time
is approximately 100 ms using a 60HZ timebase.
The WD-55 is a versatile digital timing element designed to replace mechanical timing devices of the
synchronous motor, cams, and lever variety. It is a
preprogrammed mask-ROM single chip 4-bit microcontroller wilth different features determined by external strap options. It has essentially two distinct
modes of operation: a keyboard programmable
timer/sequencer using on-chip RAM for data storage
and a 4-digit 7-segment display for data recall, or as
an on/off timer which uses thumbwheel switches or
even diodes for data storage and recall and does not
require a display. These two different modes are
selected by the absence or presence of a diode between the D7 digit output (38) and the INO scanned
input (15). If the diode is absent, upon the occurrence
of a reset pulse at pin (8), the device enters the
keyboard programmable timer/sequencer mode. If
the diode is present, a reset forces the device into
the on/off timer mode.
INO
(15)
IN1
(14)
IN2
(13)
IN3
(12)
00(31)
1
2
3
StarV
Stop
01(32)
4
5
6
Manual
On/Off
02(33)
7
8
9
1 Seq.
Strap
03(34)
Set!
Clear
0
Advance
50 HZ
Strap
Automatic
Autocontinuous
Scanned Input...
Digit Time,
04(35)
05(36)
06(37)
In the timer/sequencer mode, the WD-55 operates
with a matrix keyboard and a 4 digit numeric display to
form a simple but flexible digital timing device for use
in applications such as a dark room timer or programmable sequencer. The configuration table shown in
Figure 1 provides the definition of keys, display digits,
and strap options.
07(38)
OUTPUTS
Digit Time ...
Seg. a-I
NC
.1 sec
Strap
OUT (19)
OUT (18)
ALARM (25)
03
SEQ1
SEQ2
SEQ3
SEQ4
(21)
(22)
(23)
(24)
SEQ5 (30)
SEQ6 (29)
SEQ? (28)
02
1se~u~~ce I-
MSO
DISPLAY REGISTER
t(eyboard: The WD-55 is useable with a standard
4x4 matrix keyboard (or 3x4 with two off-board
switches) of the electromechanical or "membrane"
type; audible feedback through the alarm output is
provided for use with membrane or other switches
FIGURE 1. CONFIGURATION TABLE
PROGRAMMABLE TIMER/SEQUENCER
573
C1I
C1I
:ec
CJ1
CJ1
KEY DEFINITIONS
STRAP CONFIGURATION
ADVANCE: The key is used to access the 7 storage
locations in RAM. Each time this key is depressed,
the sequence number (digit 3) is incremented by one
and the current value of the respective sequence is
fetched and displayed in digits 00-02 (least to most
significant). If the current sequence number is 7,
depressing the advance key will rollover to sequence
#1. If the "1 sequence" strap is present (see strap
options), this key is not required.
Considerable versatility is accomplished with the
WO-55 by the use of strap options in the form of
diodes to select or delete specific functions. In the
timer/sequencer mode, the following options ar~
available.
SET/ CLEAR: This key enables the entry of data
into the RAM location currently being displayed by
digit 3. When depressed, it enables the "SET" mode
and clears display digits 00-02 to zero as well as the
respective memory location. Successive entry of data
with the numeric keys (0 through 9) is then allowed.
The set mode is terminated by depressing any nonnumeric key. Note that there is no need for an "enter" or "store" key since the data displayed on digits
00-02 is always automatically stored. If "SET /
CLEAR" has not been depressed prior to a numeric
key, the numeric key is ignored, preventing the accidental or unwanted entry of data.
MANUAL ON/OFF: This key acts as a push on/
push off switch ~manually force the output pins
(OUT (19) and OUT (18)} to toggle. This is used to
manually force an output on, such as in a darkroom
timer application where the enlarger needs to be
turned on and adjusted before proceeding with a
timed interval. These outputs will remain in their current state indefinitely until either the manual key is
depressed again or a timed interval is initiated. It has
no effect on any of the sequencer outputs, SEQ1-7.
50 HZ STRAP: The W055 uses an external time
base to accomplish its timing functions. It is optimized for use with 50 or 60 HZ AC line applications.
For operation with 60HZ, no strap is necessary. For
50HZ applications, a diode should be connected between 03(34} and IN3(12}.
1 SEQ STRAP: This strap (a diode between 02(33)
and IN3(12} } forces the device to operate as though
it had only 1 time available. At the end of the timed
sequence, the SEQ digit does not advance and the
SEQ1 data is restored to digits 0-2. When this strap
is employed, the advance key should not be used
and the sequence digit (Oigit 3) is always a "1" and
hence could be eliminated.
.1 SEC STRAP: Without this strap, the basic resolution of the 7 sequences is 1 sec. That is, intervals of
from 1 to 999 seconds are possible. With a diode (or
diode plus SPST switch for variable applications) be. tween 07(38) and IN1(14), the minimum resolution is
decreased to .1 seconds; that is, the intervals are
now from .1 to 99.9 seconds.
"AUTOMATIC" STRAP: With a diode between
07(38) and IN2(13), the automatic mode is enabled.
In this mode, once the START key is depressed,
sequences 1 through 7 are executed without further
intervention. The cycle stops at the conclusion of
sequence 7; that is, SEQ 1 data is being displayed
and the keyboard is again being scanned. This is
useful when the WO-55 is being used as a sequencer to cycle a complete 7 -event sequence.
START/STOP: This key is used to initiate or terminate a timed sequence. If a timing cycle is not being
performed, depressing this key will initiate a cycle
beginning with the sequence currently being displayed in digit 3. If a cycle is currently running, it will
terminate it, returninq the two complementary outputs
(OUT and OUT) to their normal state and incrementing
the sequence digit by 1. In fact, when a timing
sequence is currently active, this is the only key
which is scanned. This key may be paralleled with an
external start/stop or footswitch if dictated by the application.
"AUTOCONTINUOUS" STRAP: This is used in
conjunction with the "automatic" strap mentioned
previously. If a diode is connected between 07(38)
and IN3(12}, the device will operate continuously
once triggered by the start/stop key. This strap must
be connected through a switch, since there is no
means of terminating the sequence once initiated.
Sequence 7 will be followed immediately by sequence 1. Oepressing the start/stop key during the
cycle will only terminate the current sequence in
progress and begin execution of the next. This mode
would typically be used in process control, machine
sequencer, "moving lights" displays, etc.
NUMERIC KEYS (0-9): These keys are used to
enter numeric data when in the "SET" mode. Oata
entry is accomplished by right to left entry; that is,
digits 0 to 2 are left-shifted by 1 digit (with the old
value of digit 2 discarded) and the most recently depressed numeric key data entered into digit zero.
There is no limit to the number of numeric keys
which are entered, but only the most recent 3 are
displayed and stored. If the "SET/CLEAR" key has
not been previously depressed, these keys are ignored.
INITIALIZATION
A low going pulse of sufficient duration (see Electrical
Oata) on the RESET pin (8) will force an initialization
state, usually as the result of a power-turn-on reset. All 7 sequence times are set to zero and the
sequence number digit (Oigit 3) is set to "1". The
complementary outputs OUT and OUT are set to logic
LOW and logic HIGH respectively, and all sequencer
outputs are logic LOW.
574
STOPWATCH/ELAPSED TIME CONTROLLER: If
a nonzero time is entered into any sequence location, the WO-55 will count that time down to zero before advancing to the next sequence. However, if the
stored data iis already zero, depressing the START /
STOP key will initiate an "UP" count mode starting
from zero. The outputs (OUT and SEQ) function as
before. If the START/STOP key is activated during
this count cycle, the count will stop, the elapsed time
will be displayed, the outputs will return to their "off"
state, but the sequence number will not advance. This
allows the W055 to act as a "stopwatch" with a cumulative time capability and as an elapsed time controller
to time and control a variable event.
Scanned Input..
:~
IN1
(14)
IN2
(13)
IN3
(12)
BCDO
(LSD)
BCD2
(LSD)
BCD4
(LSD)
BCD8
(LSD)
:IE
cen
Digit Time,
DO (31)
en
DIGIT 1} TIME 1
ALARM OP'ERATION
The alarm output (Pin 25) serves several functions in
the timer/sequencer mode. First, it provides a .1 sec
pulse, active HIGH ("BEEP") whenever a valid key
closure is detected. This provides audio feedback for
use with non-tactile membrane keyboards. When
counting down in a sequence mode, a single "BEEP"
is enabled when the count reaches 10.0 seconds,
giving an early warning of the end of cycle. When the
count reaches zero, two "BEEPS" are output to give
audible indication of end of cycle. This output can be
buffered and used with self contained buzzers such
as a Mallory Sonalert or may be used in conjunction
with piezoelectric transducers (see Figure 9).
D1 (32)
BCDO
BCD2
BCD4
BCD8
DIGIT 2
D2 (33)
BCDO
(MSD)
BCD2
(MSD)
BCD4
(MSD)
BCD8
(MSD)
DIGIT 3
D:J (34)
Minutes
Strap
Stop
Cant
Strap
50 HZ
Strap
D4 (35)
BCDO
(LSD)
BCD2
(LSD)
BCD4
(LSD)
BCD8
(LSD)
DIGIT 1 }
TIME 2
D5 (36)
BCDO
BCD2
BCD4
BCD8
DIGIT 2
INPUT
SETTING
D6 (27)
BCDO
(MSD)
BCD2
(MSD)
BCD4
(MSD)
BCD8
(MSD)
DIGIT3
D7 (38)
On/Off
Strap
.1 sec
Strap
1 Time
Strap
Hours
Strap
TIM1 (30)
TIM2 (29)
ALARM (25)
OUTPUTS
Digit Time..
INPUT
SETTING
D2(33)
01(32)
00(31)
OISPLA Y REGISTER
FIGURE 2. CONFIGURATION TABLE ON/OFF
TIMER MODE
ON/OFF TIMER MODE
In the ON/OFF timer mode, the WO-55 is programmed
to act as a digital programmable timer with one or
two time periods which may vary from. 1 sec to 999
hours. The data is input to the device by means of
switches, thumbwheels, or even diodes. The use of a
display is optional, which if employed, will show the
current time remaining during each timing cycle. The
timebase reference is again externally provided, usually from the 50 or 60 HZ AC line. Strap options are
available to instruct the device as to whether it is to run
one or two times, whether it is to be operated continuously or in the triggered mode, and whether the
BCD switch data is to be interpreted as hours, minutes, or seconds. This mode is intended for use as
a digital time delay relay, on/off timer/controller, set
point timer, digital one-shot, etc. The timing is performed with digital accuracy and repeatability; it is
not dependent upon bulky resistor/capacitor components and their inherent tolerance and temperature
problems. For example, the WO-55 can generate a
time delay of 999 hours with an accuracy of a fraction of a second with only a handful of diodes as external components, over a temp range of 0 to 55° C, a
difficult feat to accomplish by analog means.
ON/OFF STRAP: A diode MUST be connected between 07(38) and INO(15) to inform the WO-55 that it
is to operate in this mode. This strap is scanned at
the time a reset occurs and causes the microprocessor to access the ON/OFF timer program. Without the
strap, the WO-55 will operate as a programmable
timer/sequencer as described before.
50 HZ STRAP: As described before, the WO-55 is
optimized to use a 50 or 60 HZ timebase. No strap is
required for 60 HZ operation. If 50HZ is used, a
diode should be connected between 03(34) and
IN3(12).
.1 SEC STRAP: If this strap is present (diode between 07(38) and IN1 (14)), the input data is evaluated
as XX.X secs; that is, times of from .1 to 99.9 seconds are attainable. If this strap is absent and there
are no minutes or hours straps present, the data is
evaluated as XXX. seconds.
MINUTES STRAP: If a diode is connected between
03(34) and INO(15), the data is evaluated as XXX
minutes. That is, times of from 1 to 999 minutes are
attainable .
The configuration table shown in Figure 2 defines the
strap and switch options required in this mode of
operation.
•
575
:ec
CJ1
CJ1
TRIGGER (PIN27): If the triggered mode is
selected, a positive going transition at this input will
initiate a timing cycle. This input is edge sensitive
and has an internal pull-up resistor so that a momentary pushbutton switch may be used to manually trigger an event. Since this is not a scanned input, interface to other external logic is simple.
HOURS STRAP: If a diode is connected between
07(38) and IN3(12), the data is evaluated as XXX
hours. That is, times of from 1 to 999 hours are attainable.
TIME 1 STRAP: There are normally two time
periods available with the WO-55 which are executed
in sequence. If a diode is present between 07(38)
and IN2(13), the device will act on only time 1. In other
words, when triggered it will count down time 1 to
zero, stop, and reload time 1 rather than advancing
and loading time2.
OUTPUTS
CONTINUOUS STRAP: If this strap is not present,
the WO-55 will operate in the "triggered mode". A rising edge (low to high transition) at the trigger input
(Pin 27) will initiate a timing cycle beginning with the
current time (one or two). At the end of the cycle, the
outputs return to their active low state, the next time is
loaded and displayed, and the device waits for another
trigger input. If a diode is connected between 03(34)
and IN2(13), continuous operation is selected. Here
the trigger input is ignored. This strap allows the
WO-55 to operate as a dedicated purpose timer, such
as a defrost controller, which begins operation upon
application of power.
TIM1
cycle
TIM2
cycle
(30): This output is active HIGH when timing
1 is active, and LOW otherwise.
(29): This output is active HIGH when timing
2 is active, and LOW otherwise.
ALARM (25): This output is logic LOW when a timing
cycle (1 or 2) is in progress and is logic HIGH otherwise. It may be buffered to drive an audible alarm or
it may be used as a third timing output to turn a
single device on for two different intervals.
STOP INPUT: If an input is detected between
03(34) and IN1(14) during a timing cycle, the cycle
will terminate immediately. This can allow a manual
overide to stop a cycle in progress. However, if the
"CONTINUOUS" strap is present, this input serves
only to stop the current timing cycle and cause an
advance to the next time.
INITIALIZATION
A logic low of sufficient duration on Pin 8 (RESET)
will cause initialization of the W055. In the on/off
timer mode, TIM1, TIM2, and alarm will be logic low,
and the first time (TIME 1) data is loaded into the
display register. If the CONTINUOUS mode is selected,
the device will immediately begin counting down time
1, else it will wait for a trigger pulse to occur.
DATA INPUTS: The time data is input during digit
times DO to 02 (LSD to MSO) for time 1 and during 04
to 06 (LSD to MSO) for time 2 (if used), as shown in
the configuration table. The data may be input by
means of encoded switches, thumbwheels, or even
discrete diodes. The WO-55 has on-chip pull-down
resistors across inputs INO-IN3, so that with the
absence of an input during a given digit time is interpreted as a "0". Thus it would be possible to set a time
of 080 hours by using only one diode. The data format
APPLICATIONS CIRCUITS
The following are several circuits designed to give
the user an idea of the range of applications that the
WO-55 is capable of being utilized.
must be 8421 BCD, with BCD8 connected to IN3 and BCD1
connected to INO.
576
:ec
+'2
MSD
~~~/NO.l
'OK
SEQal-;:~--.,-I
b 4
~ ~
~
~-----~26;;iTBASE
REMOTE
FOOTSWITCH
--L
o
0 -
T
-
-
40
SEQ 91"3:!-9- - - " - I
38 D7
S-3
TIME
r - j _ _-L1_ _ _L-,Sf
I
_
I
-I ___
_
II
C1I
C1I
0.3 IN.
g~~~g~E
LEDS
-. -.
~~~---~~C~DP~A---C~DPA
0--------.
L ____ 0 - - - - - - - ,
WD 55
...._ _ _ _ _ _ _ _-+-+-_+---+-----:''''''5 INO
.--_ _ _ _---+--+_--+_ _-':-,;.t4 IN'
..-----+-+---------:~*l~ IN2
r-'-~--t__--------'." IN3
D31-"~::-3- -__H
D2i*3*""2--.---t-I
D1 t=37-,-....-t---t-I
ALA~~t;267;-\--+_t___1__1
V DD
9 1--+--+--+--I
OUT ....iH
'
OUT
20
COL 1
)-',
L:',
-t--_ _ _ _----trI..__----J
FOCUS I-'-R=-2-+_ _
R3
SETI
CLEAR
ADV
ANCE
R4
4 X 4 MATRIX
KEYBOARD
+12
FIGURE 3. DARKROOM TIMER
DARKROOM TIMER
Figure 3 shows a complete schematic (except for
power supply) of a dark room timer/controller using
the WO-55. Note that the only external components
required are a display, a digit driver, keyboard, and
output switching devices. A 4-digit common-cathode
LED display is used since their inherently red radiation is desirable for dark room environments. Note
that the high current sourcing capability of the WO-55
segment outputs allows easy drive of instrument-size
LEOS. The time base is provided by shaping up the
50/60HZ AC line input to Pin 26 (TBASE). A complete
matrix keyboard is used to allow access to all 7
memory locations. A OPOT switch (S1) is used to'
select a resolution of .1 or 1 seconds and to simultaneously move the decimal point.
is not active and is "off" when the enlarger is printing. The circuit shown makes use of the complementary outputs OUT (19) and rnJT (18) to allow solid-state
switching in the form of optically-isolated triacs by buffering
them through two unused sections of the high-current digit
driver. The value of "snubber" components depends upon
the load, which in the case of enlargers and safe lamps is
often inductive. If desired, a single SPOT relay may be used
in place of the triacs and opto-isolators shown.
The buzzer shown is of the self-contained oscillator
variety and operates with DC drive. The WO-55 may
also be used with piezoelectric elements (see Figure
9). A switch is provided to disable the beeper when
not desired. Another switch (S-3) is used to enable
the automatic mode for making up to 7 sequential
timed prints by depressing the start key only once. If
the possibility of depressing two keys exists, the
keyboard should be diode isolated to avoid "sneak"
paths.
A good dark room timer/controller normally has two
switched AC outlets, one for the enlarger and one for
the "safe" light. They are the complements of each
other in that the safe light is "on" when the enlarger
577
+12
=e
c
!
\1
a
VSS
(J1
(J1
10K
8
b
~ RESET
1
~F
=:t
c
26 T
6
r2--- r---------4
z--.......
...,...-r
BASE
f
v-
9
-=
7
I
OO~
r-2
1
4
02+t--
7
39
--/\
>
I
I
3
START
03
Si'OP
02
6
5
DO
34
03+1---
SETI
CLR
i
0
AOV
)
J.N3
CONTINuous
9
AUTOMATIC
i
lN2
!
31
RYI
50K
T-VB
38
L
9 +12
~
ULN
2002
0_1 sec
Vz
-Va
33
iL=
1 SEC)
f"] ~
--
32
21
SeQl
22
SeQ2
SeQ3
SeQ4
seQS
SEQ6
se07
lNl
[...J}
~-VB
<
8
L
50K
lNO
lNl
lN2
lN3
01
01~
40
WO-55
15
14
13
12
r---
d~ r - - - - - SEG e
60 H
....L
r--------=r - - -
07
+12
:,
I
I
I
L_
--
VOO
OUT 1
r---o
OUT
--0
+12
20-=1=8
RY7
FIGURE 4. SEQUENCER WITH V-F DISPLAY
application. Toggle switches are provided to allow
strap options for .1 sec resolution and user-selectable
continuous operation. In the auto-continuous mode,
once set up, the 7 sequencer outputs will operate in
succession to cycle up to 7 processes. The sequencer
outputs are buffered by a high current driver interface
to 7 relays which perform the output switching task.
Figure 4 shows the WO-55 used to implement a
keyboard programmable sequencer with 7 outputs. It
features a vacuum-fluorescent (V-F) display which
takes advantage of the fact that the WO-55 can drive
it directly with no high voltage buffers - only external pull-down resistors are required. A conventional
matrix keyboard is used as in the dark room timer
Ej78
'v
BCO THUMBWHEEL
SWITCHES
:IE
C
c.n
c.n
10K
0.3 iNCH
LEOS
00
l/lF
~
50/60 Hz
TIME 1
TIME 2
26 TBASE
27
"-8
~'PU"
TRIG
-I
START
"'-O~"
".-0
"'-0
".-0
J.
WO-55
34
03
MINS
12
13
14
IN3.
02
33
IN2
01
32
IN1
00
OUTPUT 1
15 INO
TIM1
TIM2
ALARM
38
31
30
+V
29
25
07
VOO
20
M,"
FIGURE 5. THUMBWHEEL PROGRAMMABLE INTERVAL TIMER
Figure 5 shows the WD-55 in its second mode of operation, that of a switch programmable on/off or interval timer. The circuit shown has three relay
switched outputs, labelled one, two, and three. Output one is active for the duration of time 1, output two
is active for the duration of time 2, and output three
is active for the duration of both one and two.
Timing data is input through 6 BCD-encoded
thumbwheel switches. Three SPST switches inform
the WD-55 to interpret this data as NN.N seconds.
NNN seconds, NNN minutes, or NNN hours. The
LED display will show the time remaining and the
countdown when operating. Since the data is input
through switches, the display may be deleted if this
feature is not desired. Also, since the timing information is read from switches, the data is non-volatile
and no battery backup would be required of the device.
579
=e
c
tV
c.n
c.n
33
32
31
34
VSS
D2
RESET
D1
111lF
DO
D3
V
START
T
O~
TRIG 27
,,0
WD-55
MINUTES STRAP I
'0
i 12
IN3
TBASE
26
60Hz
1
i
+V
i 13
14
IN2
10K
30
TIM
IN1
2N2907
15
INO
RELAY N.O.
-11-- -
0.1SEC~
STRAP
I
HDURS STRAP
,
I
NC CONTACTS
,-
I
"---+-<
SELECTSI
DN/OFF
MODE
i
OUTPUT
RY1
I 38
D7
V
DD
20
FIGURE 6. DIGITAL TIME DELAY RELAY
Figure 6 shows a digital programmable time delay
relay using the WD-55 to give "ON" or "OFF" time
delays of from .1 S to 999 hours. the "Time 1 only"
strap option is used here so that when triggered, the
device loads and counts down only one time and
then resets. Simple screw-driver slot programmable
DIP switches are used here for low cost. Note that a
display is not required, but could be added to produce a unique time delay relay with digital readout of
time remaining.
!>80
•
1
IN4004
120VAC
60 Hz
, W'"'
Vss
26
TBASE
RESET
I"'
8
11~F
2N2222
IN4004
34
38
D3
D7
HOURS
CONTINOUS
OPERATION
ONI
OFF
WD·55
12
13
14
15
TIM1
IN3
ON"8 HRS
OFF"20 HRS
30
IN2
Vss
IN1
INO
TIM2
NC
T1"008 HRS
3-'--11
L . -_ _....::
1 N4148
DO
T2"020 HRS
36
D5
20
FIGURE 7. ON/OFF CONTROLLER
Figure 7 is an AC line-operated on/off controller. In
this application, the WO-55 is programmed simply by
diodes and does not require a keyboard, switches, or
a display. It is a simple, reliable solid-state alternative
to a motor driven cam switch. In this application the
non-triggered, two-time mode is selected. Time 1 and
Time 2 are programmed by diodes to be 8 hours and
20 hours respectively. The TIM1 output is buffered by
a transistor to supply gate current to a triac which
switches the output load. When power is applied to
the circuit, the output load is switched "ON" for 8
hours then "OFF" for 20 hours repeatedly.
581
=E
c
CJ1
CJ1
:E
c(J'I
(J'I
D7
D7
.--
D7
INO
INO
-L.-
INO
D7
INO
TRIG TIM1
TIM1
OUT 1
OUT 2
OUT 3
OUT N
FIGURE 8. DAISY-CHAIN N-SEQUENTIAL INTERVAL CONTROLLER
Finally, Figure 8 shows how multiple, independent
WD-55's may be configured for triggered mode operation may operate in daisy chain fashion to produce
an N-sequential programmable interval controller.
These are but a few of the many applications for the
WD-55. For custom versions, please contact the factory.
IV
WD-55
D3
D4
D5
34
35
10K
10K
36
10K
37
10K
D6
ALARM
t
(251
F "'3.3 kHz
~
1
'O"'"""'~
117ULN2002
PIEZOELECTRIC BUZZER
(GUL TON, KYOCERA, ETC)
(H" ONI
FIGURE 9. WD-55 USED WITH PIEZOELECTRIC BUZZER
ABSOLUTE MAXIMUM RATINGS
Negative Voltage on any Pin with Respect to
Vss:
20.0V
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC
electrical specifications are not ensured when operating the device at absolute maximum ratings.
Storage Temperature .... -65°C to + 150°C Ceramic
-55°C to + 125°C Plastic
Operating Free-Air Temperature
T Range ........................... O°C to 70°C
Lead Temperature (Soldering, 10 sec.) ....... 300°C
Power Dissipation 2.5 Watt at 25°C
Positive Voltage on any Pin with Respect to
Vss:
+0.3V
PARAMETER
Operating Voltage
(Vss-Voo)
Operating Current
Input Voltage Levels
All Inputs Except INO-IN3
Logic High (VIH)
Logic Low (VIL)
Inputs INO-IN3
Logic High (VISH)
Logic Low (VISL)
Output Voltage Levels
All Outputs Except DO-D7
and SA-SG
Logic High (VOH)
Logic Low (VOL)
DO-D7 Outputs
Logic High (VOOH)
VOOL
Seg Outputs Seg a-f
Segment Output Current
Seg a-f IOSH
ELECTRICAL CHARACTERISTICS
TA = 25°C, Vss-Voo = 13.2V unless noted otherwise
CONDITIONS
All inputs and outputs
open
MIN
TYP
MAX
UNITS
11.5
13.2
14.5
V
6
VSS-1
VDO
Note 1
mA
Vss
VOO-4.2
V
V
Vss-3.75
VDO
Vss
Vss-9.0
V
V
VSS-2
VOO
Vss
VSS-4.6
V
V
·Vss-1.5
Vss-3.0
Vss
Vss
V
V
Vss-3.5
Vss
V
1.0
V
40
mA
Note 2
IOH= + 100 JLA Min.
IOL= -1.6 mA Min.
looH=1.5 mA
looH=1.5 mA+1 Input
(INO-IN3)
looH=5.0 mA+ 1 Input
Note 3
losH=16 mA
Note 3
10
AC Electrical
TcYC
Reset
TBase
Timing error (TOUT)
15
15
10
15
0
Note 4
Note 1: Internal Pullup Resistors of Approximately 6K
to Vss Across Each Input.
Note 2: Internal Pulldown Resistors of Approximately
12K to VOO Across Each Input.
Note 3: Single Transistor to Vss Output Only.
Note 4: TBase = 60.000 HZ.
583
60
JLs
500
±1
msec
HZ
ms
:ec
en
en
~
c
(J1
(J1
ONE SCAN TIME = 4 CLOCK TIMES
I
II
h
--CL-K---"
I
~:.;'~~ n
I~----'I
::
I
:
!
I
I--TCYC
--1
I
I
VIH
CLOCK TIME
I
I
,
VOH,VODH
INS, 00-0
I:X~
7
I
I
I I
I I
-I
I
I --I I - Td
t- Td
!I
_N_O_-_N~J _¥i~~i~-t-~-~-D-----!----~:X~i--------
______
y-
VALID Fan 4X CLOCK TIME
'I
____________
~I~~X~=~1,~2~,~J~, ~~~~__________~________V~O~L~,~V~O~D~L~____~fl
__
VIH, VISH
________________
~------~V~IL~,~V~IS~L----------
II
F(65 n~=! _+.-+._______.______________________......;.___________
~:~' _
___
_ _ _ _ _ _ _--'.
TRIG, T BASE
~
_O.; .U ; . T ;.:, . ;S. ;E. ;Q~,
MIN.)
,-,
I
-+i__
,
I
A....;;.LA_R_M
__________
,:
II
I
-+'i~
LATCHED INTERNALLY ON RISING EDGE AT ANY TIME
VOH
TRANSmON OCCURS ON ANY CLOCK TIME
'
I
/I
VOL
VIH
i!
VOSH
NOTE 1: RISING EDGE OF RESET GENERATES SCAN TIME 0 WITHIN 4 CLOCK TIMES
Nola 2: Id = /J.s MAX
WD-55 TIMING DIAGRAM
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other ri!]htsof third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
speCifications at anytime without notice.
See page 725 for ordering information.
584
WESTERN DIGITAL
CORPORATION
WD4200/WD421 0 and WD4320/WD4321
Single·Chip N·Channel Microcontrollers
FEATURES
I.
I.
I.
..
..
I.
I.
..
..
•
•
•
•
•
•
•
GENERAL DESCRIPTION
The WD4200/4320 and WD4210/4321 Single Chip
N-Channel Microcontrollers are members of the
Control Oriented Processor family, fabricated
using N-channel, silicon gate MOS technology .
They are complete microcomputers containing all
system timing, internal logic, ROM, RAM and I/O
necessary to implement dedicated control functions in a variety of applications. Features include
single supply operation, a variety of output configuration options, with an instruction set, internal
architecture and I/O scheme designed to facilitate
keyboard input, display output and BCD data
manipulation. The WD421 0/4321 is identical to the
WD4200/4320, except with 19 I/O lines instead of
23. They are an appropriate choice for use in
numerous human interface control environments.
Standard test procedures and reliable highdensity fabrication techniques provide the
medium to large volume ,customers with a customized Control Oriented Processor at a low endproduct cost.
Low cost
Powerful instruction set
1K x 8 ROM, 64 x 4 RAM
23 I/O lines
True vectored interrupt, plus restart
Three-level subroutine stack
4.0/As instruction time
Single supply operation (4.5V to 6.3V)
Internal time-base counter for real-time
processing
Internal binary counter register with serial I/O
capability
General purpose and TRI-STATE® outputs
TTUCMOS compatible in and out
LED direct drive outputs
MICROBUSTM compatible
Software/hardware compatible with other
members of WD4200 family
Extended temperature range device available
(- 40°C to + 85°C) WD4320/4321
°3
0,
0,
-- ---,
I
I
I
I
Figure 1
PIN CONNECTIONS
L-.--------JI--l---+-+----L.-.j-----j,--t--+-+--+--+-+-- ,----,-----'
2010
Figure 2
9
19
5
6
7
8
12
13
14
15
WD42OO14210 AND 4320/4321 BLOCK DIAGRAM
585
and lower 4 bits (Bd) select one of 16 4-bit digits in
the selected data register. While the 4-bit contents
of the selected RAM digit (M) is usually loaded into
or from, or exchanged with, the A register (accumulator), it may also be loaded into or from the
a latches or loaded from the L ports. RAM
addressing may also be performed directly by the
LDD and XAD instructions based upon the 6-bit
contents of the operand field of these instructions.
The Bd register also serves as a source register for
4-bit data sent directly to the D outputs.
PIN DESCRIPTION
L7-LO 8 bidirectional 1/0 ports with
TRI-STATE®
G3-GO 4 bidirectional I/O ports
03- 0 0 4 general purpose outputs
IN3-INO 4 general purpose inputs (WD4200 only)
SI Serial input (or counter input)
SO Serial output (or general purpose
output)
SK Logic-controlled clock (or general
purpose output)
CKI System oscillator input
CKO System Oscillator output (or general
purpose input or RAM power supply)
RESET System reset input
VCC Power supply
GND Ground
Internal Logic
The 4-bit A register (accumulator) is the source and
destination register for most 1/0, arithmetic, logic and
data memory access operations. It can also be used to
load the Br and Bd portions of the B register, to load
and input four bits of the 8-bit a latch data, to input four
bits of the 8-bit L 1/0 port data and to perform data exchanges with the SIO register.
FUNCTIONAL DESCRIPTION
A block diagram of the WD4200 is given on page 1.
Data paths are illustrated in simplified form to depict
how the various logic elements communicate with
each other in implementing the instruction set of the
device. Positive logic is used. When a bit is set, it is
logic "1" (greater than 2 volts). When a bit is reset, it
is a logic "0" (less than 0.8 volts).
A 4-bit adder performs the arithmetic and logic
functions of the WD4200/4210, storing its results in
A. It also outputs a carry bit to the 1-bit C register,
most often employed to indicate arithmetic
overflow. The C register, in conjunction with XAS
instruction and the EN register, also serves to
control the SK output. C can be outputted directly to
SK or can enable SK to be a sync clock each
instruction cycle time (see XAS instruction and EN
register description below).
Program Memory
Program Memory consists of a 1,024-byte ROM. As
can be seen by an examination of WD4200/4210
instruction set, these words may be program
instructions, program data or ROM addressing data.
Because of the special characteristics associated
with the JP, JSRP, JID and LaiD instructions, ROM
must often be thought of as being organized into
16 pages of 64 words each.
Four general-purpose inputs,
IN3-INO'
are
provided; IN1, IN2 and IN3 may be selected, by
a mask-programmable option, as Read Strobe,
Chip Select and Write Strobe inputs, respectively,
for use in MICROBUST". applications.
The 0 register provides four general-purpose outputs
and is used as the destination register for the 4-bit contents of Bd.
ROM addressing is accomplished by a 10-bit PC
register. Its binary value selects one of the 1,024
8-bit words contained in ROM. A new address is
loaded into the PC register during each instruction
cycle. Unless the instruction is a transfer of control
instruction, the PC register is loaded with the next
sequential 10-bit binary count value. Three levels of
subroutine nesting are implemented by the 10-bit
subroutine save registers, SA, sa and SC, providing a last-in, first-out (LIFO) hardware subroutine
stack.
ROM instruction words are fetched, decoded and
executed by the Instruction Decode, Control and
Skip Logic circuitry.
The Q register is an internal, latched, 8-bit register,
used to hold data loaded to or from M and A, as well
as 8-bit data from ROM. Its contents are output to
the L 1/0 ports when the L drivers are enabled under
program control (see LEI instruction). With the
MICROBUS™ option selected, a can also be loaded
with the 8-bit contents of the L 1/0 ports upon the
occurrence of a write strobe from the host CPU.
Data Memory
Data Memory consists of a 256-bit RAM, organized
as four data registers of 16 4-bit digits. RAM addressing is implemented by a 6-bit a register whose
upper two bits (Br) select one of four data registers
The eight L drivers, when enabled, output the
contents of latched a data to the L 1/0 ports. Also,
the contents of L may be read directly into A and M.
As explained above, the MICROBUSTM option
allows L 1/0 port data to be latched into the Q
The G register contents are outputs to four generalpurpose bidirectional 1/0 ports. GO may be maskprogrammed as an output for MICROBUS™
appl ications.
~i86
rupt input. Immediately following an interrupt,
EN1 is reset to disable further interrupts.
register. L I/O ports can be directly connected to the
segments of a multiplexed LED display (using the
LED Direct Drive output configuration option) with
Q data being outputted to the Sa-Sg and decimal
point segments of the display.
3.
The SIO register functions as a 4-bit serial-in/serialout shift reg lister or as a binary counter depend ing on
the contents of the EN register (see EN register
description below). Its contents can be exchanged
with A, allowing it to input or output a continuous
serial data stream. SIO may also be used to provide
additional parallel I/O by connecting SO to external
serial-in/serial-out shift registers. For example of
additional parallel output capacity, see Application
No.2.
4.
EN3, in conjunction with ENO, affects the SO
output. With ENO set (binary counter option
selected) SO will output the value loaded into
EN3. With ENO reset (serial shift register option
selected), setting EN3 enables SO as the output
of the SIO shift register, outputting serial shifted
data each instruction time. Resetting EN3 with
the serial shift register option selected disables
SO as the shift register output: data continues to
be shifted through SIO and can be exchanged
with A via an XAS instruction but SO remains
reset to "0". The table below provides a summary
of the modes associated with EN3 and ENO.
Interrupt
The EN register is an internal 4-bit register loaded under program control by the LEI instruction. The state of
each bit of this register selects or deselects the particular feature associated with each bit of the EN register
(EN 3- EN O)·
1.
2.
The least significant bit of the enable register,
ENO, s€,lectes the SIO register as either a 4-bit
shift register or a 4-bit binary counter. With ENO
set, SID is an asynchronous binary counter,
decrementing its value by one upon each lowgoing pulse ("1" to "0") occurring on the SI input.
Each pulse must be at least two instruction cycles
wide. SK outputs the value of C upon execution
of XAS and remains the same until the execution
of another XAS instruction. The SO output is
equal to the value of EN3. With ENO reset, SIO is
a serial shift register shifting left each instruction
cycle time. The data present at SI goes into the
least significant bit of SIO. SO can be enabled to
output the most Significant bit of SIO each cycle
time (see 4 below). The SK output becomes a
logic-controlled clock, providing a SYNC signal
each instruction time. It will start outputting a
SYNC pulse upon the execution of an XAS
instruction with C =1, stopping upon the execution of a subsequent XAS with C = O.
The following features are associated with the IN1
interrupt procedure and protocol and must be considered by the programmer when utilizing
interrupts.
a. The interrupt, once acknowledged as explained
below, pushes the next sequential program
counter address (PC + 1)onto the stack, pushing
in tu rn the contents of the other subroutine-save
register to the next lower level (PC+1 ~ SA ~ SB
-+ SC). Any previous contents of SC are lost. The
program counter is set to hex address OFF (the
last word of page 3) and EN 1 is reset.
b. An interrupt will be acknowledged only after the
following conditions are met:
1) EN1 has been set.
2) A low-going pulse ("1" to "0") of at least two
instruction cycles wide occurs on the IN1
input.
3) A currently executing instruction has been
completed.
With EN 1 set the IN 1 input is enabled as an inter-
ENABLE REGISTER MODES EN3
With EN2 set, the L drivers are enabled to output
the data in Q to the L 1/0 ports. Resetting EN2
disables the L drivers, placing the L 1/0 ports in a
high-impedance input state. If the MICROBUSTM
option is being used, EN2 does not affect the L
drivers.
BITS EN3 AND ENO
ENO
SIO
SI
SO
0
0
Shift Register
Input to Shift Register
0
1
0
Shift Register
Input to Shift Register
Serial Out
0
1
Binary Counter Input to Binary Counter
0
1
1
Binary Counter Input to Binary Counter
1
587
SK AFTER XAS
= 1, SK = SYNC
= 0, SK = 0
If C = 1, SK = SYNC
If C = 0, SK = 0
If C = 1, SK = 1
If C = 0, SK = 0
If C = 1, SK = 1
If C = 0, SK = 0
If C
If C
4) All successive transfer of control instructions
and successive LBls have been completed
(e.g., if the main program is executing a JP
instruction which transfers program control
to another JP instruction, the interrupt will not
be acknowledged until the second JP instrubtion has been executed.
LSI CPUs and interfacing devices. (See MICROBUSTM,
National Publication.) The functioning and timing
relationships between the WD4200 signal lines affected
by this option are as specified for the MICROBUSTM
interface, and are given in the AC electrical characteristics and shown in the timing diagrams (figures 11
and 12). Connection of the WD4200 to the MICROBUSTM
is shown in MICROBUSTM Option interconnect
illustration.
c. Upon acknowledgemeht of an interrupt, the skip
logic status is saved and later restored upon the
execution of a subsequent RET instruction. For
example, if an interrupt occurs during the execution of ASC (Add with Carry, Skip on Carry)
instruction which results in carry, the skip logic
status is saved and program control is transferred to the interrupt servicing routine at hex
address OFF. At the end of the interrupt routine,
a RET instruction is executed to "pop" the stack
and return program control to the instruction
following the original ASC. At this time, the skip
logic is enabled and skips this instruction because of the previous ASC carry. Since, as
explained above, it is the RET instruction which
enables the previously saved status of the skip
logic, subroutines should not be nested within
the interrupt servicing routine since their RET
instruction will enable any previously saved
main program skips, interfering with the orderly
execution of the interrupt routine.
Initiaiizatlon
The Reset Logic, internal to the WD4200/4210 will
initialize (clear) the device upon power-up if the
power supply rise time is less than 1 ms and greater
than 1 Il s. If the power supply rise time is greater
than 1 ms, the user must provide an external RC network and diode to the RESET pin as shown below.
The RESET pin is configured as a Schmitt trigger
input. If not used it should be connected to VCC.
Initialization will occur whenever a logic "0" is
applied to the RESET input, provided it stays low for
at least two instruction cycle times.
Upon initialization, the PC register is cleared to 0
(ROM address 0) and the A, B, C, 0, EN, and G registers are cleared. The SK output is enabled as a
SYNC output, providing a pulse each instruction cycle
time. Data Memory (RAM) must be cleared by the
user's program. The first instruction at address 0 must
be a CLRA.
d. The first instruction of the interrupt routine at
hex address OFF must be a NOP.
e. A LEI instruction can be put immediately before
the RET to re-enable interrupts.
POWER
SUPPL Y
CLOCK
MICROBUSTM Interface
The WD4200 has an option which allows it to be
used as a peripheral microprocessor device, inputting and outputting data from and to a host microprocessor (ILP). IN1, IN2, and IN3 general purpose
inputs become MICROBUS 1M compatible readstrobe, chip-select, and write-strobe lines, respectively. IN 1 becomes RD - a logic "0" on this input
will cause Q latch data to be enabled to the L ports
for input to the ILP. IN3 becomes CS - a logic "0"
on this line selects the WD4200 as the ILP peripheral
device by enabling the operation of the RD and WR
lines and allows for the selection of one of several
periopheral components. IN3 becomes WR - a logic
"0" on this line will write bus data from the L ports to
the Q latches for input to the WD4200. Go becomes
INTR a "ready" output, reset by a write pulse from
the ILP on the WR line, providing the "hand-shaking"
capability necessary for asynchronous data transfer
between the host CPU and the WD4200.
This option has been designed for compatibility with
National's MICROBUSTM - a standard interconnect
system for a-bit parallel data transfer between MOS/
MICRO PROCESSOR
Figure 3
MICROBUSTM OPTION
INTERCONNECT
POWER
' SUPPLY
I
RC>5 X POWER SUPPLY RISE TIME
Figure 4
588
POWER-UP CLEAR CIRCUITS
Oscillator
put of another WD4200/4210 with CKI connected
as shown. In this configuration, the SK output
connected to CKO must provide a SYNC (instruction cycle) signal to CKO, thereby allowing
synchronous data transfer between the WDs
using only the SI and SO serial I/O pins in conjunction with the XAS instruction. Note that on
power-up SK is automatically enabled as a
SYNC output (see Functional Description, Initialization, above).
There are four basic clock oscillator configurations
available as shown below.
a. Crystal Controlled Oscillator. CKI and CKO
are connected to an external crystal. The instruction cycle time equals the crystal frequency divided
by 16 (optional by 8).
b. External Oscillator. CKI is configured as a TTL
compatible input accepting an external clock
signal. The external frequency is divided by 16
(optional by 8 or 4) to give the instruction cycle
time. CKO is now available to be used as the
RAM power supply (VR) or as a general purpose
input.
CKO Pin Options
In a crystal controlled oscillator system, CKO is used
as an output to the crystal network. As an option
CKO can be a general purpose input, read into bit
2 of A (accumulator) upon execution of an INIL instruction. As another option, CKO can be a RAM power
supply pin (VR), allowing its connection to be a
standby/backup power supply to maintain the integrity
of RAM data with minimum power drain when the main
supply is inoperative or shut down to conserve power.
Using either option is appropriate in applications where
the WD4200/4210 system timing configuration does
not require use of the CKO pin.
c. RC Controlled Oscillator. CKI is configured as a
single pin RC controll~q Schmitt trigger oscillator. The instruction cycle equals the oscillation
frequency divided by 4. CKO is available for nontiming functions.
.
d. Externally Synchronized Oscillator. Intended for
use in multi-WD systems, CKO is programmed to
function as an input connected to the SK out-
CRYSTAL OSCILLATOR
RC CONTROLLED OSCILLATOR
EXTERNAL OSCILLATOR
(SYNC)
CKO
D
WD4200/4210
WD4200/4210
SO
SI
SI
SO
EXTERNALLY SYNCHRONIZED OSCILLATOR
Crystal Oscillator
Crystal
Value
R1
4 MHz
3.58 MHz
2.09 MHz
1K
1K
1K
RC Controlled Oscillator
Component Values
R2
C
1M
1M
1M
R (kg)
27 pF
27 pF
56 pF
C (pF)
12
6.8
8.2
22
Figure 5 WD4200/4210 OSCILLATOR
589
100
220
300
100
Instruction
Cycle Time
in liS
5±20%
5.3 ± 23%
8 ±29%
8.6 ± 16%
I/O Options
f. An on-Chip depletion load device to VCC'
WD4200/4210 outputs have the following optional
configurations, illustrated below.
g. A Hi-Z input which must be driven to a "1" or "0"
by external components.
a. Standard. An enhancement-mode device to ground
in conjunction with a depletion-mode device to VCC
compatible with TLL and CMOS input requirements.
b. Open-Drain. An enhancement-mode device to
ground only, allowing external pull-up as required
by the user's application.
c. Push-Pull. An enhancement-mode device to ground
in conjunction with a depletion-mode device paralleled by an enhancement-mode device to VCeThis configuration has been provided to allow for
fast rise and fall times when driving capacitive
loads.
d. LED Direct Drive. An enhancement-mode device
to ground and to VCC' meeting the typical current
sourcing requirements of the segments of an LED
display. The sourcing device is clamped to limit
current flow. These devices may be turned off under program control (see Functional Description,
EN Register), placing the outputs in a high-impedance state to provide required LED segment blanking for a multiplexed display.
The above input and output configurations share
common enhancement-mode and depletion-mode
devices. Specifically, all configurations use one or
more of six devices (numbered 1-6, respectively).
Minimum and maximum current (lOUT and VOUT)
curves are given on figure 7 for each of these devices
to allow the designer to effectively use these I/O configurations in designing a WD4200/4210 system.
The SO, SK outputs can be configured as shown in
A, B, or C. The D and G outputs can be configured
as shown in A or B. Note that when inputting data to
the G ports, the G outputs shou Id be set to "1". The L
outputs can be configured as A, B, 0, or E.
An important point to remember if using configuration A or D with the L drivers is that even when the L
drivers are disabled, the depletion load device will
source a small amount of current.
WD4210
e. Three·State Push· Pull. An enhancement-mode
device to ground and VCC intended to meet the
requirements associated with the MICROBUSTM
option. These outputs are TRI-STATE® outputs,
allowing for connection of these outputs to a
data bus shared by other bus drivers.
WD4200/4210 inputs have the following optional
configurations:
If the WD4200 is bonded as a 24-pin device, it becomes the WD4210, illustrated in figure 1, WD4200/
4210 Connection Diagrams. Note that the WD4210
does not contain the four general purpose IN inputs
(lN3-INO)' Use of this option precludes, of course use
ofthe IN options, interruptfeature, and the MICROBUS™
option which uses IN1-IN3' All other options are available for the WD4210.
B. OPEN-DRAIN
A. STANDARD
C. PUSH-PULL
VCC
dg}
( .... IS DEPLETION DEVICE)
D. LED
E. THREE·STATE·· PUSH·PULL
'''"'~~
INPUT~{
G. HI-Z INPUT
F. INPUT WITH LOAD
Figure 6 OUTPUT CONFIGURATIONS
590
DEPLETION LOAD OFF SOURCE CURRENT
0.4
OUTPUT SINK CURRENT
-25 I--+'--++--+-+---+--i---I
0.3
;(
;( -20
.§.
.§.
5
f-
::J
-15 I--I-II--I---+---".-I""'--+-+----l
2
2
-10 1-H'-t--7IL--t--+-.\---+---l
0.2
01
\
\MAX
f\
\
~IN
VOUT (VOLTS)
2.00
VOUT (VOLTS)
DEVICE 1
DEVICE 2
PUSH-PULL SOURCE CURRENT
STANDARD OUTPUT SOURCE CURRENT
.---.--..---,--"'T'"'""--r--,----,
175 I---t--+--+-+---+--+---I
1.50 k--b..c-t'-'--+...c.c..+'-""+--i---I
;(
.§. 1.25 1--.......-+--+-+---+--+---1
f-
.§
1 0 k--t-"'~--r--r-':""';'-'--i---I
0.75
t-c-.3k--~rt-/-+---t"':""+--I
0.25 1---t"__
t#--"'II~I'f-'""d---+---I
VOUT (VOLTS)
DEVICE 2
VOUT (VOLTS)
LED OUTPUT SOURCE CURRENT
;(
;
18
16
14
12
.§
101---t-~+-~~+--+--+---I
18
~-t-~~-+-+--+--i---I
DEVICE 3
LED OUTPUT DIRECT LED DRIVE
16 HI-+-+-+--t--+-+--+---:I..:.t
14 I--I--+-+--+--t--+_M+AX~V---l'---l
I---t-~~-+-+--+--+---I
~~-~-+-+--+--+---I
12
1--~-~~-~"'T'"'""--t~4r--l
10
r-t---l~~I--~~~~~~~
VOUT= 2.0V , /
1--1--+-+~---l~~I--+-+-+-~
V
MIN
...... ~5.5
4.5
VOUT (VOLTS)
DEVICE 4
Vee (VOLTS)
6.5
DEVICE 4
TRI-STATE" OUTPUT SOURCE CURREN1'
INPUT LOAD SOURCE CURRENT
1.5 I-'Io-+---t-+-- ---I-__-+----l
;(
.§.
5
1.0 P-&--W7'f--/-I---+-+--l
2
0.5 1::--i--/-I-7"'d---"t.--t--+--l
2
VOUT (VOLTS)
VOUT (VOLTS)
DEVICE 5
Figure 7
WD4200/4210 OUTPUT CHARACTERISTICS
591
DEVICE 6
DEPLETION OFF SOURCE CURRENT
OUTPUT SINK CURRENT
30r--n~-r--~~~-r~
;( -0.4
.s
~ -0.3
15~f-I--+-
9
-0.2
-0.1
N.,
~
2
VOUT(VOLTS)
STANDARD OUTPUT SOURCE CURRENT
- 1. 75
DEVICE 2
_ _ _......,,.....,.--.......__.
- 2.5 ~-+\----+--++-h'+--+----I
-1.5
1.0
4
PUSH PULL SOURCE CURRENT
- 3.0 _ _-
,....--.-""T"--...-.....,--""T"--~--.
-1.25
l -
3
VOUT (VOLTS)
DEVICE 1
;(
- 2.0 ~-+-+--+l--I-+--I-
E
~ -1.5
1--'~(-li,,-+--+----1---+-+--I
9
I-
.9 - 0.75 I---I-~-Po~+--+--+--+-~
-1.0
-0.5
-0.5
- 0.25 .....,"""tl:---+-/--Pl.c---"lo.----+-+_~
VOUT(VOLTS)
DEVICE 2 AND 3
4
VouT
:::>
9
/ MAX
-10
-15
;(
.s
/
-12
-20
9
-8
-8
IT
-6
V P
-2 f - - MIN
4
VOUT (VOLTS)
VOUT = 2.0V
,,"
-4
-4
o ... -
DEVICE 4 AND 2
4.0
4.5
5.0
Vee (VOLTS)
~
5.5
6.0
DEVICE 4 AND 2
TRISTATE OUTPUT SOURCE CURRENT
INPUT LOAD SOURCE CURRENT
- 15 ~~---+1f---""
- 1.0 ~-l--....J.--+--+-....J.----l
l-
-0.8
10 Ir---\l--l-
;(
I-
E
:::>
~ -0.6
9
o
-
- 5 1----4...--+
- 0.4
I---+~..h{-"ri-
- 0.2
I---\---+-~
2
VOUT (VOLTS)
Figure 8
VouT RAM(B)
Q3:0 -. A
None
Copy Q to RAM, A
RAM(EI) ~ A
BREII r ~ Br
None
Load RAM into A,
Exclusive-OR Br with r
RAM(r.d)
None
Load A with RAM pointed
to directly by r, d
None
Load Q Indirect (Note 3)
None
Reset RAM Bit
None
Set RAM Bit
MEMORY REFERENCE INSTRUCTIONS
CAMQ
CQMA
LD
LDD
r
r, d
5MB
10 0 1 1 10 0 1 11
33
10 0 1 1 11 1 0 g
10 1 1 010 1 1 11
2C
10 0 1 011 1 0 01
_5
10 0 1 r
23
10010100 1 11
-
10 0 1 r Id
I
1
0
1
1
1
11
11
11
-
BF
LQID
RMB
33
3C
0
4C
1
45
2
42
3
43
0
40
1
47
2
46
3
4B
10 1 0 1!
~
A
ROM(pC9:8, A, M)
SB ~ SC
o ~ RAM(B)O
o ~ Ri\M(Bh
q o ~ RAM(B)2
11 o ~ R/\M(B)3
10 1 0 01 1 1 0 01
10 1 0 010 1 0 11
10 1 o 010 0 1
10 1 0 01 0 0 1
10 1 o 011 1 0 11
10 1 0 010 1 1 11
10 1 0 010 1 1 ~
10 1 0 01 1 0 1 11
1
~
Ri\M(B)O
1
~
Ri\M(B)1
1
~
.RI\M(B) 2
1
~
RI\M(B)3
594 .
~
Q
Mnemonic fPerand
Machine Language
Code (Binary)
Hex
Code
Data Flow
Skip Conditions
MEMORY REFERENCE INSTRUCTIONS (Continued)
STII
y
7_
y
y ---+ RAM(B)
10 1 1 1
Bd + 1 ---+ Bd
I
X
XAD
Ir
I
Description
None
Store Memory Immediate and Increment Bd
None
Br E9 r ---+ Br
RAM(r,d) ++ I-
Exchange RAM with A,
Exclusive OR Br with r
None
Exchange A with RAM
pointed to directly by r, d
1 1 11
RAM(B) H A
Bc - 1 -+ Bd
BrQ) r ---+ Br
Bd decre- Exchange RAM with A
ments
and Decrement Bd,
past 0
Exclusive-OR br with r
10 1 0 Ql
RAM(B) +-+ A
Bd + 1 ---+ Bd
Br Q) r ---+ Br
Bd increments
past 15
Exchange RAM with A
and Increment Bd,
Exclusive-OR Br with r
None
Copy A to Bd
None
Skip
until not
a LBI
Copy Bd to A
Load B Immediate with
r, d (Note 6)
None
Load EN Immediate
(Note 7)
None
Exchange A with Br
g
r
_6
10 0
r, d
23
1001010
o
1 11
--
11
d
I
10 1 1
XDS
r
_7
10
Ir I
o I r 10
XIS
r
_4
\0
oIr
0
RAM(B)
H
A
REGISTER REFERENCE INSTRUCTIONS
CAB
50
\0 1 0 1 I 0 0 0 01
A
CBA
LBI
4E
--
10 1 0 011 1 1 01
\0 o I r I (d
I
BD
r, d
Bd
---+
r,d
-+
---+
A
B
(d = 0,9:15)
or
33
--
10 0 1 110 0 1 11
d
11 0 I r I
I
(any d)
LEI
Y
XABR
33
10
0 1 110
o
6_
10 1 1 01
10 0 0 11 0
y
I
o
1 ~
12
1 11
y
A
---+
++
EN
Br (0, 0
---+
A3, A2)
TEST INSTRUCTIONS
SKC
20
~010 0001
SKE
21
SKGZ
33
10 0 1 010 0 0 11
10 0 1 1 10 0 1 11
SKGBZ
33
21
0
SKMBZ
SKT
01
\0 0 1 010 0 0
10 0 1 1 10 0 1
10 0 0 01 0 o 0
10 0 0 1 10 o 0
C = "1"
G3:0 =0
11
11
GO = 0
'1
11
03
3
13
1\
1
0
o
0
0
010
11
1
\0 0 0 1 10 o 1 11
0
1
01
10 0 0 0 I 0 0 0 11
11
10 0 0 110
0 11
RAM(B)1 = 0
2
03
13
10 0 0 0 I 0 0 1 11
10 0 0 110 0 1 11
10 1 0 0\0 0 0 11
RAM(B)2 = 0
3
41
Skip if G is Zero
(all 4 bits)
Skip if G Bit is Zero
1st byte
11
2
o
Skip if C is True
A = (RAM(B) Skip if A Equals RAM
2nd byte
G1=0
G2 = 0
G3 = 0
RAM(B)O = 0 Skip if RAM Bit is Zero
RAM(B)'3 =0
A time-base Skip on Timer
counter carry (Note 3)
has occurred
since last test
595
Hex
Mnemonic Operand Code
Machine Language
Code (Binary)
Skip
Conditions
Oata Flow
Description
INPUTIOUTPUT INSTRUCTIONS
ING
33
2A
ININ
33
28
INIL
33
29
INL
33
2E
OBD
33
3E
OGI
y
33
5OMG
33
3A
XAS
4F
A
None
A
None
10 0 1 1 10 0 1 11
10 0 1 011 0 1 01
G-~
10 0 1 1 10 0 1 11
10 0 1 011 0 0 01
IN
10 0 1 1 10 0 1 11
10 0 1 01 1 0 0 11
IL3, CKO, "0", ILO
10 0 1 1 10 0 1 11
10 0 1 011 1 1 01
L7:4
10 0 1 1 10 0 1 11
10 0 1 1 11 1 1 01
Bd
10 0 1 1 10 0 1 11
10 1 0 1 1 y
I
y~
10 1 1 010 1 1 11
10 0 1 1 11 0 1 01
10 1 0 01 1 1 1 11
RAM(B)
~
Input G ports to A
Input IN inputs to A
(Note 2)
~
~
A
RAM (B)
None
Input IL Latches to A
(Notes 2 and 3)
None
Input L Ports to RAM, A
None
Output Bd to D Outputs
None
Output to G Ports
Immediate
None
Output RAM to G Ports
None
Exchange A with SIO
(Note 3)
L3:0 ~ A
A
~
D
G
H
~
G
SIO, C
~
SK
Note 1: All subscripts for alphabetical symbols indicate bit numbors unless explicitly defined (e.g., Sr and Sd are explicitly defined)
Bits are numbered a to N where a signifies the least significant bit (low-order, right-most bit). Forexample, A3 indicates the most significant (left-most) bit of the 4-bit A register.
Note 2: The IN IN and INIL instructions are not available on the 24-pin WD4210 since this device does not contain the IN inputs.
Note 3: For additional information on the operation of the XAS, .J/D, LQID, INIL. and SKT instructions, see below.
Note 4: The JP instruction allows a jump, while in subroutine pages 2 or 3, to any ROM location within the two-page boundary of page
2 or 3. The JP instruction, otherwise, permits a jump to a ROM location within the current 64-word page. JP may not jump to the last
word of a page.
Note 5: A JSRP transfers program control to sUbroutine page 2 (0010 is loaded into the upper 4 bits of Pl. A JSRP may not be used
when in pages 2 or 3. JSRP may not jump to the last word in page 2.
Note 6: LSI is a single-byte instruction if d = O. 9,10,11.12,13,14. or 15. The machine code forthe lower 4 bits equals the binary view of
the "d" data minus 1, e.g., to load the lower four bits of B (Sd) with the value 9 (10012), the lower 4 bits of the LSI instruction equal S
(10002). To load 0, the lower 4 bits of the LSI instruction should equal 5 (11112).
Note 7: Machine code for operand field y for LEI instruction should equal the binary value to be latched into EN, where a "1" or "0" in
each bit of EN corresponds with the selection of deselection of a particular function associated with each bit (see Functional Description, EN Register).
The following information is provided to assist the
user in understanding the operation of several
unique instructions and to provide notes useful to
programmers in writing WD4200/4210 programs.
nary counter. (See Functional Description, EN
Register, above). If SIO is selected as a shift register,
an XAS instruction must be performed once every 4
instruction cycles to effect a continuous data
system.
XAS Instruction
JID Instruction
JID (Jump Indirect) is an indirect addressing
instruction, transferring program control to a new
ROM location pointed to indirectly by A and M. It
loads the lower 8 bits of the ROM address register PC
with the contents of ROM addressed by the 10-bit
word, PC9:8, A, M. PC9 and PC8 are not affected by
this instruction.
XAS (Exchange A with SIO) exchanges the 4-bit
contents of the accumulator with the 4-bit contents
of the SIO register. The contents of SIO will contain
serial-in/serial-out shift register or binary counter
data, depending on the value of the EN register. An
XAS instruction will also affect the SK output, providing a logic controlled clock if SIO is selected as a
shift register or C -~ SK if SIO is selected as a bi-
Note that JID requires two instruction cycles.
596
•
INILlnstruction
SKT Instruction
INIL (Input IL Latches to A) inputs two latches, IL3
and ILO (see figure 8 ) and CKO into A. The IL3 and
I La latches are set if a low-going pulse ("1" to "a") has
occurred on the IN3 and INO inputs since the last
INIL instruction, provided the input pulse stays low
for at least two instruction times. Execution of an INIL
inputs IL3 and ILO into A3 and AO respectively, and
resets these latches to allow them to respond to subsequent low-going pulses on the IN3 and INa lines. If
CKO is mask programmed as a general purpose
input, an INIL will input the state of CKO into A2. If
CKO has not been so programmed, a "1" will be
placed in A2. A "0" is always placed in Al upon the
execution 01: an INIL. The general purpose inputs
IN3-INO are input to A upon the execution of an ININ
instruction (see table 2, ININ Instruction). INIL is useful in recognizing pulses of short duration or pulses
which occur too often to be read conveniently by an
ININ instruction.
The SKT (Skip on Timer) instruction tests the state
of an internal la-bit time-base counter. This counter
divides the instruction cycle clock frequency by
1024 and provides a latched indication of counter overflow. The SKT instruction tests this latch, executing the
next program instruction if the latch is not set. If the
latch has been set since the previous test, the next
program instruction is skipped and the latch is reset.
The features associated with this instruction, therefore, allow the WD4200/4210 to generate its own
time-base for real-time processing rather than relying on an external input signal.
L.OID Instruction
Instruction Set Notes
L.alD (Load a Indirect) loads the a-bit a register with
the contents of ROM pointed to by the 10-bit word
Pcg, PCa, A, M. LaiD can be used for table look-up or
code conversion such as BCD to seven-segment. The
L.alD instruction "pushes" the stack (PC + 1 - SASB - SC) and replaces the least significant a bits of
PC as follows: A - PC7:4, RAM(B) - PC3:0, leaving
PCg and PCa unchanged. The ROM data pointed to
by the new address is fetched and loaded into the a
latches. Next, the stack is "popped" (SC - SB - SA
-.. PC), restoring the saved value of PC to continue
sequential program execution. Since LaiD pushes
SB - SC, the previous contents of SC are lost. Also,
when LaiD pops the stack, the previously pushed
contents of SB are left in SC. The net result is that the
contents of SB are placed in SC (SB - SC). Note that
LaiD takes two instruction cycle times to execute.
a.
The first word of a WD4200/4210 program
(ROM address 0) must be a CLRA (Clear A)
instruction.
b.
Although skipped instructions are not executed, one instruction cycle time is devoted to
skipping each byte of the skipped instruction.
Thus all program paths take the same number
of cycle times whether instructions are skipped
or executed.
c.
The ROM is organized into 16 pages of 64
words each. The Program Counter is a 10-bit
binary counter, and will count through page
boundaries. If a JP, JSRP, JID, or LaiD instruction is located in the last word of a page, the
instruction operates as if it were in the next
page. For-example: a JP location in the last
word of a page will jump to a location in the next
page. Also, a LaiD or JID located in the last
word of pages 2, 7, 11, or 15 will access data in
the next group of four pages.
For example, using a 2.097 MHz crystal as the timebase to the clock generator, the instruction cycle
clock frequency will be 131 kHz (crystal frequency-:-16) and the binary counter output pulse frequency
will be 128 Hz. For time-of-day or similar real-time
processing, the SKT instruction can call a routine
which increments a "seconds" counter every 128
ticks.
WD4200
OPTION LIST
IN IN
-.l
The WD4200/421 a mask-programmable options are
assigned numbers which correspond with the
WD4200 pins.
TABLE 3 is a list of WD4200 options. When
specifying a WD4210 chip, Options 9, 10, 19, 20, and
29 must all be set to zero. The options are
programmed at the same time as the ROM pattern to
provide the user with the hardware flexibility to interface to various I/O components using little or no
external circuitry.
INIL
Figure 9
INIL HARDWARE IMPLEMENTATION
597
TABLE 3
Option 1
Option
= 0:
= 1:
= 2:
= 3:
= 4:
Option
= 0:
= 1:
= 2:
= 3:
= 4:
= 0:
Ground Pin -
WD4~~OO
MASK OPTIONS
no options available
Option 15: LO Driver
Same as Option 5
2: CKO Pin
clock generator output to crystal
pin is RAM power supply (VR input)
general purpose input, load device to VCC
multi-COP SYNC input
general purpose input, Hi-Z input
3: CKI Input
crystal input divided by 16
crystal input divided by 8
TTL external clock input divided by 16
TTL external clock input divided by 8
single-pin RC controlled oscillator
Option 16: SI Input
Same as Option 9
Option
= 0:
= 1:
= 2:
Option 18: SK Driver
Same as Option 17
Option 19: INO Input
Same as Option 9
Option 4: RESET Pin
= 0: load devices to VCC
= 1: Hi-Z input
Option
= 0:
= 1:
= 2:
= 3:
17: SO Driver
Standard output (Figure 6A)
Open-Drain output (Figure 68)
Push-Pull output (Figure 6C)
Option 20: IN3 Input
Same as Option 9
Option 21: GO I/O Port
=0: Standard output (A)
= 1: Open-Drain output (B)
5: L 7 Driver
Standard output (Figure 6A)
Open-Drain output (Figure 68)
LED direct drive output (Figure 60)
TRI-STATE®push-pull output (Figure 6E)
Option 22: G1 I/O Port
Same as Option 21
Option 23: G2 I/O Port
Same as Option 21
Option 6: L6 Driver
Same as Option 5
Option 24: G3 I/O Port
Same as Option 21
Option 7: L5 Driver
Same as Option 5
Option 8: L4 Driver
Same as Option 5
Option 25: 03 Output
= 0: Standard output (A)
= 1: Open-Drain output (B)
Option 9: IN1 Input
=0: load device to VCC (Figure 6F)
= 1: Hi-Z input
Option 26: 02 Output
Same as Option 25
Option 10: IN2 Input
Same as Option 9
Option 27: 01 Output
Same as Option 25
Option 11
= 0:
VCC Pin -
Option 28: DO Output
Same as Option 25
no options available
Option 12: L3 Driver
Same as Option 5
Option 29: COP Function
= 0: normal operation
= 1: MICROBUS™ option
Option 13: L2 Driver
Same as Option 5
Option 30: COP Bonding
= 0: WD4200 (28-pin device)
= 1: WD4210 (24-pin device)
Option 14: L 1 Driver
Same as Option 5
TEST MODE (Non-Standard Operation)
a. RAM and Internal Logic Test Mode (SI
The SO output has been configured to provide for
standard test procedures for the customprogrammed WD4200. With SO forced to logic "1",
two test modes are provided, depending upon the
value of SI:
b. ROM Test Mode (SI
= 1)
= 0)
These special test modes should not be employed by
the user; they are intended for manufacturing test
only.
!598
•
APPLICATION NO.1: WD4200 General Controller
APPLICATION NO.2
The diagram below shows an interconnect diagram
for a W04200 used as a general controller.
Operation of the system is as follows:
Provides an interconnect diagram for a versatile
application of the WD4200 as a keyboard/display
interface to a microprocessor (J1. P). Generally,
operation of the WD4200 in this configuration is as
follows:
1.
The L7-LO outputs are configured as LED
Direct Orive outputs, allowing direct connection to the segments of the display.
2.
The D3·DO outputs are buffered by transistors
to drive the digits of the multiplexed display
and to scan the columns of the 4x4 keyboard
matrix rows.
3.
The IN~HNO inputs are used to input the four
drives of the keyboard matrix. Reading the IN
lines in conjunction with the current value of
the D outputs allows detection, debouncing,
and decoding of anyone of the 16 keyswitches.
4.
CKI is configured as a single-pin oscillator
input allowing system timing to be controlled
by a single pin RC network. CKO is therefore
available for use as a VR RAM power supply
pin. RAM data integrity is thereby assured
when the main power supply is shut down.
5.
6.
SI is selected as the input to a binary counter
input. With SIO used as a binary counter, SO
and SK may be used as general purpose
outputs.
The four bidirectional G I/O ports (G3-Go) are
available for use as required by the user's
application.
1.
The MICROBUSTM option has been selected.
2.
System timing is provided by an external crystal. The time base for the real-time (counter and
clock) modes is provided by the internal timebase counter, tested by the SKT instruction.
3.
The SIO register is used as a serial-in/serial-out
shift register. In this configuration, however, SI
is sh ifted into S I0 to be tested as one of the fou r
row lines tied to the keyboard matrix. SO is
used to output display segment data (loaded
into SIO with an XAS instruction) to the cascaded 74C164s (8-bit parallel out serial shift
registers). SK functions as a logic-controlled
clock, sending a SYNC signal to clock serial
data into the 74C164s.
4.
The 16 bits of data shifted into the 74C164s are
buffered through the DS8867s (8-segment LED
drivers) to the 16 segments of the alphanumeric LED displays.
5.
The DO-01 outputs are decoded by the DS8664
(14-digit decoder/driver) and used to select
one of the 14digits ofthe multiplexed display as
well as to scan the 13 columns of the keyboard
matrix and the strap switch scan line (014).
3.3V
LO~-=e:~~~
L~I-----,
GND
GND
WD4200
DO
D1
D2
D3
4 GENERAL I/O
EVENT
COMPUTER
INPUT
INO
~O
G'
IN1
3
IN2
4x4
KEYSWITCH
MATRIX
IN3
SI
SK
SO
2 GENERAL OUTPUTS
Figure 10
WD4200 KEYBOARD/DISPLAY INTERFACE
599
6.
The G1-G lines together with SI are connected to the four rows of the keyboard matrix
and the four strap switch lines to input key or
strap switch data to the WD4200. The strap
switches can be used to select one of several of
the system modes listed below.
7.
The LOL7 THREE-STATE bidirectional 110
ports are connected to the microprocessor
data bus to allow for input or output of data
to and from the microprocessor and the
WD4200.
8.
The various operations which can be performed by the system include the following
"handshaking" and WD4200 "stand-alone"
modes:
a. keyboard to J..tP (7-bit ASCII)
b. keyboard to WD4200 buffer to J..tP (7-bit
ASCII)
c. J..tP to display
d. display to J..tP
e. J..tP to clock
f. clock to J..tP
g. J..tP to timer
h. timer to J..tP
i. keyboard to display
j. clock to display
k. timer to display
rO~358MHZ
XTAL
~L
'v
CKO
CK1
0_
LO
1-L1
2-L2
3 - L3
4 - L4
5 - Ls
a-L6
7-L7
INT A _ Go
TO
MICROBUS'M
CONNECTOR
INO ' - SPARE INPUT
vCC ,..-vCC
SK
WD4200
WA - IN1
j'W"
rs
VCC
1 A
s-
CLEAR
74C164
I A
2 B
IN2
D - IN3
~-
8
Iil'- """
O'O"~'OOO'''''~ ,,00,,00""" 0"
CLEAR
W
3 4
56110 111213
12345678
D3
D2
-D1
DO
088867
D88867
GND~
51
G3
G2
G1
OUT
1 2
_
3
,
4
a
7
OUT
1 2
OUT
•
3
2
I
3
9 l' 9 l'
17
6 10
3
7
6
(VCC - PIN 18.
GND - PIN 9)
L
M
TOEACHDL416
.\-16
4
3
OUT
8
1
1rTo
5
16Jl~
TOEACHDL416
.},.i
4
14 13 12
1.17,1
1 1
K
A2 D2 H I J
117,1161151:4,1131121.11,1:0
A1 B C Dl E F Gl G2
TO KEYBOARD (
CONNECTOR
~1
(VCC -PIN 14.
GND - PIN 7)
34
51610 11T12T13
12345678
IN11N2 IN3 IN41Ns IN6 IN71N8
IN1 IN21N31N41N511~a1N71N8
r---r---
74C164
2 B
..1-16
.1-16
I
17 6
3
10
17 6
I
10
SEE SEGMENT
CON FIGURATION
FOR PINOUTS OL416(4)
3
1716 110
~131
STRAPS
20 19
5
D2
SEGMENT PIN
A1 19
A2 15
B
18
C
20
Dl 11
4
D2
E
7
F 222
D1
6
D13 D14
VCC
EN
p:r-
088664
GND~
A2
:~:~:
7
8
D9 D 1O D 11D12
D5 D6 D7 D8
~IIZ
ALPHANUMERIC DISPLAY
SEGMENT CONFIGURATION
Al
11 10 9
16 15 14 13
8 17
4
DI D2 D, D4
3 AIN
2 BIN
1
2
.
KEYBOARD LAYOUT
S
%
&
(
)
(1i>
lea ...
3
4
5
6
7
8
9
0
II~
W
E
R
T
Y
U
I
0
SI
~SPA RE
....
ALT Q
P
I~
LF
D1
~CTR
I ....
SEGMENT PIN
G1
1
G2 14
H
21
I
16
12
J
K
9
L
5
M
8
DP
2
Figure 11
A
S
D
F
G
H
J
Z
x
C
V
B
N
M
K
~~e
L
II~
AET
G2
~SHI FT
I ....
/
spll~
BS
~SHI
WD4200 KEYBOARDIDISPLAY INTERFACE
1300
G1
G3
FT
D1· D 13
TO KEYBOARD
CONNECTOR
Absolute maximum ratings indicate limits beyond
WD4200/421 0
ABSOLUTE MAXIMUM RATINGS
which damage to the device may occur. DC and AC
electrical specifications are not ensured when
Voltage at Any Pin Relative to GND - 0.5V to + 7V
operating the device at absolute maximum ratings.
Ambient Operating Temperature (Note 1)
O°C to + 70°C
Ambient Storage Temperature
- 65°C to + 150°C
Ceramic Plastic
- 55°C to + 125°C
DC ELECTRICAL CHARACTERISTICS
Lead Temperature (Soldering, 10 sec.)
300°C
0° C,,:;TAd70°C, 4.SV,,;VCC,,:;6.3V unless otherwise
Power Dissipation
0.75 Watt at 25°C
noted.
0.4 Watt at 70°C
TABLE 4
PARAMETER
Operating Voltage (VCC)
Operating Supply Current
CONDITIONS
MAX
UNITS
4.S
6.3
35
mA
0.4
V
V
0.8
V
V
0.6
V
V
0.6
V
V
VCC = SV, TA = 2SoC
(all inputs and outputs open)
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (VIH)
Logic Low (VIU
TTL Input
Logic High (VIH)
Logic Low (VIU
MIN
2.0
VCC
= SV ± S%
2.0
Schmitt Trigger Input
Logic High (VIH)
Logic Low (VIL)
0.7 VCC
RESET Input Levels
Logic High
Logic Low
0.7 VCC
RESET Hysteresis
1.0
SO Input Level (Test Mode)
2.0
All Other Inputs
Logic High
Logic High
Logic Low
Output Voltage Levels
Standard Output
TTL Operation
Logic High (VOH)
Logic Low (VoU
CMOS Operation
Logic High (VOH)
Logic Low (VoU
Output Current Levels
LED Direct Drive Output
Logic High (IOH)
VCC = Max
VCC = SV ± S%
0.8
V
V
V
0.4
V
V
0.2
V
V
2.S
14
mA
-10
+10
J.lA
3
mA
3.0
2.0
= 10J.lA
VCC-1
VCC
VOH
= 6V
= 2.0V
TRI-STATE® Output
Leakage Current
CKO Output
VR Power Saving Option
Power Requirements
V
2.4
= -1011A
VR
V
3.0
VCC = SV ± S%
10H = 100 J.lA)
10L = -1.6 mA
10H
10L
V
= 3.3V
601
WD4200/4210
AC Electrical Characteristics
ooe,,;; TA,,;; +70 oe,4.5V,,;; VCC";; 6.3Vunless otherwise stated.
PARAMETER
Instruction Cycle Time -tc
CKI Using Crystal (figure SA)
Input Frequency - f1
Duty Cycle (Note 2)
TABLES
CONDITIONS
10
J.1S
--;-16 mode
-:- 8 mode
figure 13b
1.6
0.8
30
4
2
55
MHz
MHz
%
1.6
0.8
30
4
2
60
60
40
MHz
MHz
%
ns
ns
0.5
4
1.0
8
MHz
R = 15K ± 5%, C = 100 pF ± 10%
CKO as SYNC Input (figure 50)
tSYNO
Inputs (figure13a):
figure 13b
IN3-INO, G3-GO, L7-LO
tSETUP
tHOLD
SI
tSETUP
D3-DO, G3-GO
tPD1
tPDO
L7-LO (Standard)
tPD1
tPDO
L 7-LO (LED Direct Drive)
tPD1
tPDO
COP to TTL Propagation Delay
UNITS
4
CKI Using RC (figure 5C)
Frequency
Instruction Cycle Time
SK as a Logic-Controlled Clock
tPD1
tpDO
SO, SK as a Data Output
tPD1
tPDO
tPD1
MAX
figure 13a
CKI Using External Clock (figure 58)
Input Frequency
-:-16 mode
-:- 8 mode
Duty Cycle (Note 2)
Rise Time
f1 =: 4 MHz
Fall Time
f1 = 4 MHz
tHOLD
Outputs:
COP to CMOS Propagation Delay
MIN
J.1S
50
ns
1.7
100
ns
0.3
J.1S
100
ns
J.1S
4.5V..;:;VCC,;;6.3V, CL = 50 pF,
VOH = 0.7 Vec, VOL = 0.3 Vce
VOH = 2V
VOH = 2V
1.1
0.3
J.1S
J.1S
1.4
0.3
0.7
J.1S
J.1S
J.1S
1.6
0.6
J.1S
J.1S
1.4
0.3
J.1S
J.1S
2.4
0.4
I1S
J.1S
0.8
0.8
J.1S
J.1S
fanout = 1 Standard TTL Load
Vec = 5V ±5%, CL = 50 pF,
VOH = 2.4V, VOL = O.4V
SK as a Logic-Controlled Clock
tPD1
tPDO
602
TABLE 5 Continued
PARAMETER
MAX
UNITS
SK as a Data Output, SO
tPD1
tPDO
1.0
1.0
}J.S
}J.S
D3-DO, G3-GO
tPD1
tPDO
1.3
1.3
}J.s
J.1.S
L7- L o
tpD1
tpDO
1.4
0.4
}J.S
}J.S
L 7-LO (Push-Pull)
tpD1
tpDO
0.4
0.3
J.1.S
}J.S
CKO (figure 13C)
tPD1
tpDO
0.2
0.2
J.1.S
}J.S
250
200
ns
ns
ns
ns
ns
700
ns
ns
ns
ns
ns
ns
CONDITIONS
MIN
Outputs (continued):
MICROBUSTM Timing
Read Operation (figure11)
Chip Select Stable Before RD - tCSR
Chip Select Hold Time for RD - tRCS
.
RD Pulse Width - tRR
Data Delay from RD - tRD
RD to Data Floating - tDF
CL
= 50 pF,
VCC
= 5V ± 5%
50
5
300
Write Operation (figure 12)
Chip Select Stable Before WR - tcsw
Chip Select Hold Time for WR - twcs
WR Pulse Width - tww
Data Set-Up Time for WR - tDW
Data Hold Time for WR - tWD
INTR Transition Time from WR - tWI
20
20
300
200
40
Note 1: Duty Cycle = tW1/(tW1 + two").
Note 2: See figure 7 for additional I/O characteristics.
603
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC
electrical specifications are not ensured when
operating the device at absolute maximum ratings.
WD4320/43421
ABSOLUTE MAXIMUM RATINGS
Voltage at Any Pin Relative to GND - 0.5V to + 7V
Ambient Operating Temperature (Note 1)
- 40°C to + 85°C
Ambient Storage Temperature
Ceramic - 65°C to + 150°C
Plastic - 55°C to + 125°C
Lead Temperature (Soldering, 10 sec.)
300°C
Power Dissipation
0.75 Watt at 25°C
0.25 Watt at 85 ° C
DC ELECTRICAL CHARACTERISTICS
- 40°C ~ TA ~ + 85°C, 4.5V ~ VCC ~ 5.5V unless
otherwise noted.
TABLE 6
PARAMETER
CONDITIONS
Operating Voltage (VCC)
Operating Supply Current
MIN
MAX
UNITS
4.5
5.5
40
V
mA
0.3
V
V
0.6
V
V
0.4
V
V
0.1
V
V
(all inputs and outputs open)
Input Voltage Levels
CKI Input Levels
Crystal Input
Logic High (VIH)
Logic Low (VIU
TTL Input
Logic High (VIH)
Logic Low (VIL)
2.2
VCC = 5V ± 5%
2.2
Schmitt Trigger Input
Logic High (VIH)
Logic Low (VIU
0.7 VCC
RESET Input Levels
Logic High
Logic Low
0.7 VCC
RESET Hysteresis
0.5
SO Input Level (Test Mode)
2.2
All Other Inputs
Logic High
Logic High
Logic Low
Output Voltage Levels
Standard Output
TTL 'Operation
Logic High (VOH)
Logic Low (VOL)
CMOS Operation
Logic High (VOH)
Logic Low (VoU
Output Current Levels
LED Direct Drive 'Output
Logic High (I'OH)
VCC = Max
VCC = 5V ± 5%
Vce = 5V ±5%
10H = -75/AA
IOL = -1.6 mA
10H = 10pA
I'OL = -10pA
V
0.6
V
V
V
0.4
V
V
0.2
V
V
1.0
12
mA
-10
+10
pA
4
mA
3.0
2.2
2.4
VCC-1
VCC = 5V
VOH = 2.0V
THREE-STATE Output
Leakage Current
CK'O Output
VR Power Saving Option
Power Requirements
V
3.0
VR = 3.3V
604
WD4320/4321
AC Electrical Characteristics
40°C ~ TA ~ + 85°C, 4.5V ~ VCC ~ 5.5V unless
otherwise stated.
TABLE 7
PARAMETER
Instruction Cycle Time -tc
CKI Using Crystal (figure SA)
Input Frequency - f1
Duty Cycle (Note 2)
CONDITIONS
10
J1S
-:-16 mode
-:- 8 mode
figure 13b
1.6
0.8
40
4
2
55
MHz
MHz
%
1.6
0.8
40
4
2
60
60
40
MHz
MHz
%
ns
ns
0.5
4
1.0
8
MHz
R
CKO as SYNC Input (figure 5D)
tSYNO
Inputs (figure 13a):
figure 13b
= 15K ± 5%,
C
= 100 pF ± 10%
IN3-INO, G3-GO, L7-LO
tSETUP
tHOLD
SI
tSETUP
03- 0 0, G3-GO
tPD1
tPDO
L7-LO (Standard)
tPD1
tPDO
L7-LO (LED Direct Drive)
tPD1
tPDO
COP to TTL Propagation Delay
UNITS
4
CKI Using RC (figure 5C)
Frequency
Instruction Cycle Time
SK as a Logit-Controlled Clock
tpD1
tpDO
SO, SK as a Data Output
tPD1
tPDO
tPD1
MAX
figure 13a
CKI Using External Clock (figure 58)
Input Frequency
-:-16 mode
-7- 8 mode
Duty Cycle (Note 2)
Rise Time
f1 =: 4 MHz
Fall Time
f1 = 4 MHz
tHOL.D
Outputs:
COP to CMOS Propagation Delay
MIN
J1S
50
ns
1.7
100
ns
J1S
0.3
J1S
250
ns
4.5V ~ VCC ~ 5.5V, CL = 50pF,
VOH = 0.7 VCC, VOL = 0.3 VCC
VOH
VOH
= 2V
= 2V
1.3
0.4
J1S
1.6
0.4
.75
/lS
J1S
/lS
2.0
1.0
/lS
/lS
2.0
1.0
J1S
/lS
3.0
1.0
/lS
1.0
1.0
JJ.S
J1S
J1S
/lS
fanout = 1 Standard TTL Load
Vec = 5V ± 5%, CL = 50 pF,
VOH = 2.4V, VOL = O.4V
SK as a Logic-Controlled Clock
tPD1
tPDO
605
MAX
UNITS
SK as a Data Output, SO
tPD1
tPDO
1.2
1.2
I1S
f.1S
03-00, G3-GO
tpD1
tpDO
1.5
1.5
f.1s
I1S
L7- L O
tpD1
tpDO
1.6
0.5
f.1S
I1S
L 7-LO (Push-Pull)
tpD1
tpDO
0.5
0.5
/1S
CKO (figure 13C)
tpD1
tPDO
0.25
0.25
/1S
/1S
350
250
ns
ns
ns
ns
ns
800
ns
ns
ns
ns
ns
ns
PARAMETER
CONDITIONS
MIN
Outputs (continued):
MICROBUSTM Timing
Read Operation (figure11)
Chip Select Stable Before RD - tCSR
Chip Select Hold Time for RD - tRCS
RD Pulse Width - tRR
Data Delay from RD - tRD
RD to Data Floating - tDF
CL
= 50 pF,
VCC
= 5V ± 5%
60
10
400
Write Operation (figure 12)
Chip Select Stable Before WR - tcsw
Chip Select Hold Time for WR - twcs
WR Pulse Width - tww
Data Set-Up Time for WR - tow
Data Hold Time for WR - two
INTR Transition Time from WR - tWI
I1S
100
50
400
350
50
Note1: Exercise great care not to exceed maximum power dissipation limits when direct driving LEOs or
similar loads at high temperatures.
Note 2: Duty Cycle = tW1/(tW1 + tWO).
Note 3: See figure 8 for additional 110 characteristics.
(306
"e
CS
(IN2)
tRR
(L7- LO)
L"i"D1
AD
(INt)
07-00
cs
(IN 3)
WR
(L7-LO)
07- 0 0
(GO)
INTR
~
I\)
1-tDF=3-
MICROBUS™ READ OPERATION TIMING
Figure 12
(IN2)
:IE
C
~
..~
0
C»
::::s
Q,
:IE
I.
WI
t
Figure 13
~
==={
W
MICROBUSTM WRITE OPERATION TIMING
~
C
~
w
I\)
..
I----INSTRUCTION CYCLE TIME ( t C ) - - j
CKI
---l
tPDt
I--
~~&~t _..!L::Jl-vOH
I' .r---~
I--
---I
tPDO
IN3-INO _ _ _ _ _ _ _ _..:-""""'\
t SETUP
X
G 3_Go L7-LO
I
1
/,.---/-r-----oT'""""
--l 1-- t HOLD
X'-____
I-- t PDt .~
I /
JVOH
CKO & 51
G3-GOI:~~~
1-
t,\PDO?VOL
~ ~
L 7 -LO. SO. SK
OUTPUTS
Figure 14A
__I
INPUT/OUTPUT TIMING DIAGRAM (CRYSTAL
I--two
CKI~
--I
eKO
(INPUT)
I-- tWt
\
Sll--
CKI~
t SYNCO
I
I
tPDt~tPDO
' -_ _ _~----_-
Figure 148
+ 16 MODE)
SYNCHRONIZATION
Figure 14C
Figure 14
See page 725 for ordering information.
607
TIMING
CKO OUTPUT TIMING
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other ri9hts of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
(iOB
Printed In U S.A
WESTERN DIGITAL
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4 Bit Microcomputers
J::a,
m
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3:
Western Digital Components Group offers both
PMOS and NMOS single chip microcomputers for
dedicated controller applications. Both of these
families are true microcomputers in that they have
on-chip mask ROM, RAM, I/O, and clock generation
.- all of the elements required to implement a
programmable microcontroller solution for your
dedicated control problem.
WD·55 TIMER/CONTROLLER
The WD-55 is a general purpose timing element for
use as a dark room timer, process sequencer, appliance timer, time·delay relay, recycling timer, etc. It
may be configured for two different modes of
operation: one mode utilizes a conventional matrix
keyboard for data entry, in conjunction with a 4-digit
LED or V-F display for generating up to seven timed
sequential outputs. Another mode allows data entry
through BCD-encoded switches for triggered or
continuous control of 2 outputs.
PREPROGRAMMED MICROCONTROLLERS
Western D~gital offers several preprogrammed
rnicrocontrollers which were developed to solve
timing and control problems which previously had
been implemented by electromechanical systems
conSisting of motors, cam switches, levers, etc. or for
which a large number of random-logic IC's were
required. Several more devices are being developed;
for customized versions of these standard products,
please contact the factory.
WD4200/421 0
These devices are fabricated using N·channel
technology, and are hardware and software compatible with National Semiconductor's COP 420/421
devices. The WD4200 is available in a 28-pin package
and features 23 I/O lines. The WD4210 is a bonding
option which deletes the 4-bit IN-port and is available
in a 24-pin package. They both feature 1K x 8 ROM, 64
x 4 RAM, a 4.0j.Ls instruction cycle time, 4.5 to 6.3V
operation, a 3·level subroutine stack, single-level
interrupt, serial I/O plus sync, on-chip counter/timer,
and a high current 8-bit bidirectional port capable of
directly driving LED displays.
WD·51 IRRIGATION CONTROLLER
The WD-51 performs all of the timing and control
functions required by a 6·station irrigation (sprinkler)
control system for residential and commercial applications.
The only support circuitry required is a simple power
supply, display, keyboard/switch matrix, and triac or
other high-current solenoid driver. The device is fully
programmable for a 7-day week and each station
output is programmable from 0 to 99 minutes
duration. Up to 3 complete watering cycles per 24
hour period are available, as well as a pump/master
valve output and a rain-inhibit switch input.
WD4320/4321
These devices are functionally identical to the
WD4200/4210, but operate over an extended temperature range of - 40°C to + 85°C.
609
o
::D
oo
o
3:
"'0
C
-I
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::D
en
object code. Western Digital will review and duplicate
the media submitted and will return copies to the
customer.
Upon written confirmation as to the correctness of
the data, masks are generated and an engineering
pilot run is commenced. At the completion of the
pilot run, approximately 10 devices are submitted to
the customer for verification and approval. Upon
written verification by the customer, the remainder of
the pilot run (usually several hundred devices) are
shipped as part of a pre-production delivery, and the
production wafers are started for predetermined,
scheduled delivery.
SUBMISSION OF MASK ROM CODE
To submit mask ROM code for the WD4200/4210, or
WD4320/4321 two items need to be received:
(1) Completed 110 options list describing the desired
configured of the mask-programmable options.
(2) The object code itself.
The object code may be in the form of a diskette
containing the XXX.TRT and XXX.LM files generated
by a COP400 PDS development system, or EPROMS
(5204,2708,2716, etc.), paper tape, etc. (we prefer the
diskette or EPROMS), and a hard copy printout of the
MASK OPTION CONFIGURATION TABLE
FOR WD4200/4210 and WD4320/4321
MASK
OPTION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SELECTED*
OPTION
MASK
OPTION
COMMENT
Ground Pin
CKO Pin
CKI Input
RESET Pin
L7 Driver
L6 Driver
L5 Driver
L4 Driver
IN1 Input
NA 4210
IN2 Input
NA 4210
VCC Pin
L3 Driver
L2 Driver
L1 Driver
LO Driver
SI Input
SO Driver
SK Driver
19
20
21
22
23
24
25
26
27
28
29
30
SELECTED*
OPTION
COMMENT
INO Input
NA 4210
IN3 Input
NA 4210
GO 110 Port
G1 110 Port
G2 110 Port
G3 110 Port
03 Output
02 Output
01 Output
DO Output
Function
Bonding
Customer. _____._ _ _ _ _ _ _ _ _ _ _ _ __
WDC P/N: _ _ _ _ _ _ _ _ _ _ _ _ __
Customer PIN: _ _ _ _ _ _ _ _ _ _ _ __
* Note: Refer to the data sheet for a description of the available options.
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
610
Printed on U.S.A
Special Products
Page
IPart Number
WD1801
WD1802
WD2412
Octal Comparator .................................................... 613
Octal Comparator .................................................... 617
Time of Day Clock ................................................... 621
611
n12
WESTERN DIGITAL
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WD1801 Octal Comparator
FEATURES
GENERAL DESCRIPTION
• +5
The WD1801 Is an 8 bit wide comparator. It has been designed to minimize the logic required to implement address decoding or break point Indications. It Is capable of
comparing two 8-bit words and Is easily expanded by using
the external enable Input E1N.
•
•
•
•
•
VOLT ONLY
CASCADABLE USING EIN
N-MOS SILICON GATE TECHNOLOGY
20 PIN PLASTIC OR CERAMIC DIP
TTL COMPATIBLE
BUILT IN PULL-UP RESISTORS ON A INPUTS
The matching of two 8 bit Inputs plus a logic low on EIN produces an active low on output EOUT.
APPLICATIONS
The A bank Inputs are Implemented with internal pull-up
resistors to facilitate programming with Inactive devices
such as DIP switches
• ADDRESS COMPARATOR
• BUS COMPARATOR
• STATUS LINE DECODER
• BREAK POINT GENERATOR
Vcc~
The logic expression for EouT active Is:
EOUT = EIN(A00BO)(A10S1)thru(~)
Aa o
Bao-------I
Vcc~
A70------'---~
B7 0 - - - - - - - - {
EIN
0-------1
.)0-----------'
FIGURE 1
LOGIC DIAGRAM
613
=e
c
.....
co
0
.....
Vee
fiN
BO
AO
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
Ba
Aa
B7
A7
Vss
EOUT
FIGURE 2
PIN CONNECTIONS
PIN DEFINITIONS TABLE I
PIN DEFINITIONS
NAME
PIN
SYMBOL
FUNCTION
2-9
B Inputs
-E1N
Bo- B7
10
Vss
Vss
Ground
11
Equal Out
Eour
Active Low Output for A
A Inputs
A7-AQ
Vee
8 Bit A input to Comparator
1
12-19
20
External Enable
Vee
614
Active Low Input Enable
8 Bit B Input to Comparator
=B
+5V ± 10% PowerSupply
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Ambient Temperature under Bias ........ - 40°C to 70°C
Voltage on any pin with respect
to Ground (Vss)......................... - 0.2 to + 7V
Power Dissipation ............................. 0.5W
Storage Temp. - Ceramic - 65°C to + 150°C
Plastic - 55°C to + 125°C
NOTE: Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits is not
intended and should be limited to those conditions
specified in the DC Electrical characteristics.
TABLE 2
DC ELECTRICAL CHARACTERISTICS
TA = 0° to 70°C; Vee = 5.0V ± 10%; Vss = OV;
PARAMETER
SYMBOL
MIN
V1L
V1H
Input High Voltage
VOL
Output Low Voltage
VOH
High Level Output Voltage
2.4
Vee
Supply Voltage
4.5
Icc
Supply Current
MAX
TYP
Input Low Voltage
UNIT
TEST CONDITIONS
V
+0.8
V
2.2
0.45
V
IOL = 3.2MA
V
IOH = -200JAa
5.0
5.5
V
40
100
MA
TYP
MAX
UNIT
TEST CONDITIONS
All outputs open
TABLE 3
DC ELECTRICAL CHARACTERISTICS
TA = 0° to 70°C; Vee = 5V ± 10%; Vss = OV; CL = 50pF
MIN
PARAMETER
SYMBOL
t pHL
AI or BI to EOUT Active
55
70
nsec
EINActive
t pLH
AI or BI to EOUT Inactive
45
60
nsec
E1NActive
EIN to EOUT
40
50
nsec
Ai = Bi
te
NOTE: A.C. Timing Measurements at VOH = 2.0V and VOL = 0.8V.
~IN~
I
AI
I
ORW~/~
~I.....BI
EOUT
:~
_ _ _ _ _ _ _ _ _ _-.J_
I
:
I
I
I
I
I
---4:----;.:---""'
~I ------~~
I
Ie
I
l
I
~
~:-----~~~:----------------:
_________
I
IpHL
-
I
~
-----:
FIGURE 3
TIMING DIAGRAM
615
I
I
PLH
!..-: -
:eC
.....
00
.....
0
TYPICAL APPLICATIONS
A
D
D
TYPICAL APPLICATIONS
A
D
D
+5
E
S
S
B
U
S
+5
ENABLE
R
ENABLE
E
S
S
R
BO
B1
EOUT
B
U
S
AO
B2
A1
B3
A2
B4
A3
B5
A4
B6
A5
B7
A6
DIP
DIP
SWITCH
SWITCH
A7
-=
FIGURE 4
8 BIT PROGRAMMABLE ADDRESS
BUS COMPARATOR
DIP
SWITCH
EXi'ERNAL
~
EIN
VSS
FIGURE 5
16 BIT PROGRAMMABLE ADDRESS
BUS COMPARATOR
See page 725 for ordering information.
This is a preliminary specification with tentative device parameters and ma'i be subject to change after final product characterization is completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor any infringements of patents or other rights of third parties which may result from Its use. No license is granted by implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change said
circuitry at any time without notice.
616
WESTERN DIGITAL
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WD1802 Octal Comparator
=E
c.....
co
o
I\)
FEATURES
GENERAL DESCRIPTION
• + 5 VOLT ONLY
The WD1802 is an 8 bit wide comparator. It has been designed to minimize the logic required to implement address decoding or break point indications. It is capable of
comparing two 8-bit words and is easily expandable using
the external enable input E1N.
•
•
•
•
•
•
CASCADABLE USING EIN
N-MOS SILICON GATE TECHNOLOGY
20 PIN PLASTIC OR CERAMIC DIP
TTL COMPATIBLE
BUILT IN PULL-UP RESISTORS ON A INPUTS
EQUATES FOR COMPLEMENTARY INPUTS
The WD1802 is implemented with exclusive - OR (XOR)
gates. It equates when the A inputs are complementary to
the B inputs. The combination of complementary 8 bit inputs plus a logic low on EIN produces an active low on the
output E OUT '
APPLICATIONS
• ADDRESS COMPARATOR
• BREAK POINT GENERATOR
• BUS COMPARATOR
• STATUS LINE DECODER
The A bank inputs are implemented with internal pull-up
resistors. The pull-up resistors plus the complementary
logic make this device extremely easy to use with inactive
devices such as DI P switches.
The logic expression for EOUT active is:
EOUT
= EIN(AoeBO),(A1eB1),
(A2 eB2), (A3 eB3), (A4 eB4)
(A5 eB5), (A6 eB6), (A7 eB7)
AsO
B50~------I
Vcc~
A6o----~--~
B6o-------~
Vcc~
A7o-·----~----~)
B7o-·----------~1
EIN 0
[»1----------------'
F.IGURE 1.
LOGIC DIAGRAM
617
:ec
~
()C)
0
N
vee
EIN
BO
AO
B1
A1
B2
A2
B3
A3
B4
A4
B5
A5
Ba
Aa
B7
A7
Vss
EOUT
FIGURE 2
PIN CONNECTIONS
PIN DEFINITIONS TABLE I
PIN
NAME
1
External Enable
Enable Active Low
8 Bit B Input to Comparator
Vss
Bo-B7
Vss
Equal Out
EOUT
Active Low Output for A
A Inputs
A7-Ao
8 Bit A Input to Comparator
Vee
Vee
+ 5V ±
B Inputs
10
11
20
FUNCTION
fiN
2-9
12-19
SYMBOL
Ground
=
10% Power Supply
B
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Storage Temp. - Ceramic - 65°C to + 150°C
Plastic - 55°C to + 125°C
AmbientTemperature under Bias ........ - 40°C to 70°C
Voltage on any pin with respect
to Ground (vss) ......................... - 0.2 to + 7V
Power Dissipation ............................. 0.5W
NOTE: Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits is not
intended and should be limited to those conditions
specified in the DC Electrical characteristics.
'TABLE 2
DC ELECTRICAL CHARACTERISTICS
TA
= 0° to 70°C; Vee = 5.0V± 10%; Vss = OV
SYMBOL
PARAMETER
MIN
V1L
Input Low Voltage
V 1H
Input High Voltage
VOL
Output Low Voltage
VOH
High Level Output Voltage
2.4
Vee
Supply Voltage
4.5
lee
Supply Current
TYP
MAX
UNIT
+0.8
V
2.2
TEST CONDITIONS
V
0.45
V
IOL
V
IOH
5.0
5.5
V
40
100
MA
TYP
MAX
UNIT
= 3.2MA
= -2oo",a
All outputs open
'TABLE 3
AC ELECTRICAL CHARACTERISTICS
TA
= 0° to 70°C; Vee = 5V ± 10%; Vss = OV; CL = 50 pF
SYMBOL
MIN
PARAMETER
t pHL
TEST CONDITIONS
Ai or Bi to EOUT Active
55
70
nsec
EIN Active
t pLH
Ai or Bi to EOUT Inactive
45
60
nsec
EIN Active
tE
EIN to EOUT
40
50
nsec
Ai = Bi
NOTE: A.C. Timing Measurements at VOH
= 2.0V and VOL = 0.8V.
~IN~
I
~~ ~~--------------------~~
I
I
EOUT
I
I
I
I
I
I
I
:
I
I
I
I
~ l------~~________________~;______~~~I-----------------~
tE
:
:
:
--.:
I
I
tpHL
I
:
~
-----:
FIGURE 3
TIMING DIAGRAM
619
tpLH
I I
:e
C
.....
00
0
I\)
TYPICAL APPLICATIONS
A
D
D
R
E
+5
TYPICAL APPLICATIONS
A
D
D
R
E
ENABLE
+5
ENABLE
S
S
S
S
B
U
AO
S
A1
B
U
S
A2
A3
A4
DIP
SWITCH
AS
AS
A7
-=
FIGURE 4
8 BIT PROGRAMMABLE ADDRESS
BUS COMPARATOR
DIP
SWITCH
EXTERNAL
rnAEIU
EIN
VSS
FIGURE 5
16 BIT PROGRAMMABLE COMPARATOR
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other right3 of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
620
Printed In
u.s A
WESTERN DIGITAL
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WD2412 Time of Day Clock
FEATURES
• DISPLAYED TIME CAN BE IN 12 OR 24 HOUR
FORMATS
• POWER FAIL FLAG
• INPUTS AND OUTPUTS ARE TTL/CMOS
COMPATIBLE
• SINGLE + 4.5 TO + 6.3 VOLT SUPPLY
• 28 PIN CERAMIC OR PLASTIC PACKAGE
• TEMPERATURE RANGES: 0° TO + 70°C, - 40°
TO +85°C
• SELF CONTAINED TIMEBASE USING COMMON
BAUD RATE CRYSTAL
• SOFTWARE SELECTABLE EXTERNAL 50 AND
60 Hz TIMEBASES
• PROVIDES HOURS, MINUTES, SECONDS, DAY,
MONTH, DATE, AND YEAR
• TIME OF DAY IS AVAILABLE IN 12 AND 24
HOUR BCD AND BINARY
• BINARY TIME IS INTERNALLY CALCULATED
FROM BCD TIME
I)
INTERRUPT AT ABSOLUTE TIME OF DAY OR
TIME AND DATE
I)
INTERRUPT AT RELATIVE TIME
I)
AUTO RELOAD FOR PERIODIC INTERRUPTS
PERIODIC INTERRUPTS CAN BE SET FROM 0.1
SEC TO 1 DAY
e TIME, DATE AND INTERRUPT REGISTERS MAY
BE READ ON THE FLY
u TIME, DATE OR USER CAN BE DISPLAYED ON
6 DIGIT BY 7 SEGMENT DISPLAY
u AM, PM, DATE, AND TIME DISPLAY MODE
INDICATORS
GENERAL DESCRIPTION
The WD2412 Time of Day clock (TDC) is a complete
timekeeping system offering hours, minutes,
seconds, day of week, month, date and year. Time of
day is available in both 24 and 12 hour BCD and
straight binary formats. The BCD calendar automatically corrects for leap years up to the year 2100. The
WD2412 can be programmed to provide relative or absolute real time interrupts with resolutions to a tenth
of a second. Absolute interrupts can be based on
time or time and date. The relative interrupt down
counter can be read on the fly and reloads itself after
an interrupt. 12 or 24 hour time of day, date, or user
registers can be output to an external 6 digit by 7 segment display. Also TIME, DATE, AM and PM status indicators are provided. A flag is available to inform the
host system that a catastrophic power failure has occurred. The WD2412 includes an 8 bit bi-directional
bus so that it may be easily interfaced to most popu-
I)
1KQ
TO INTRQ,
LATCH
1MQ
CKI
INTRQ
CKO
8
HOST
r- - - - - - - - - - - -
~4
-
- - - - - - - - - - - -
-
- -
- - - - ---
6 DIGIT X 7 SEG
BCD
DAL
- - - -
WD2412
TDC
RD
3
4
------.a cs
DS
MR
VCC 50/60
I
I
Tl
L_ ~P!19~A~_l
VSS
Figure 1 WD2412 SYSTEM BLOCK DIAGRAM
+4.5
TO
lar microcomputers. It is fabricated on a single
NMOS LSI chip including all bus interface logiC and
crystal timebase oscillators. All inputs and outputs
are TTL compatible.
+6.3V
r------------,
:AC
I
I
3
74LS145:
I
L______________ ~P.!I~~!:... ______________ J
j-- -- - ' - - ,
I
AM
I
4.8V
ZENER
TIMEBASE
Timebase is generated by a common 4.0960 MHz
baud rate generator crystal or an external 50 or 60 Hz
:
I
L.9'=.T!.0~~l:. ______ J
621
:e
C
I\)
~
...A.
I\)
signal. On power up, the timebase defaults to the
internal crystal, but a software command can be
issued to the WD2412 to change its timebase over to
50 or 60 Hz or back to crystal again. Due to the fact
that the 50/60 Hz timebase is not synchronized to the
crystal oscillator, there may be a slight timebase error
incurred when switching from internal to external
timebases or back again. This timebase error is
guaranteed not to exceed 0.1 second per timebase
switch. When operating the WD2412 from an external
timebase, it is not necessary to provide a crystal
oscillator. Internal timing needs of the WD2412 can
be satisfied by injecting a 4 MHz TTL level signal into
the CKI terminal.
GND
BCDO
CKO
CKI
BCD1
BCD2
BCD3
~
DAL7
DS2
DAL6
DAL5
DAL4
RD
CS
DS1
DSO
TST1
WR50/60 Hz
VCC
DAL3
XTLTST
DAL2
INTRQ
TSTO
DAL1
DALO
Figure 2
PIN DESIGNATIONS
PIN DESIGNATIONS
PIN
NUMBER
PIN NAME
SYMBOL
1
2
3
4
POWER SUPPLY
CLOCK OUT
CLOCK IN
MASTER RESET
VDD
CKO
CKI
MR
11
16
18
POWER SUPPLY
TESTO
CRYSTAL TEST
VCC
TSTO
XTLTST
19
EXT. TIMEBASE
50/60 Hz
21
TEST1
TST1
FUNCTION
Ground
Crystal osci Ilator output.
Crystal oscillator input.
A logic low on this input clears all internal logic
after power up. If rise time of power supply is
less than 1 mS, then the external RC is optional.
Normally, this line should not be tied to the
system reset.
+ 4.5 to + 6.3 VDC
Test pin. User leave open.
When MR is held true this output toggles at CKI
divided by 16.
This optional input provides the timebase if the
50 or 60 Hz external timebases are selected. The
input signal should be of TTL levels with a rise
time of better than 1J,ls and a low time of greater
than 20J,ls. If this line is not used, it should be
tied high or left open.
Test pin. User leave open.
COMPUTER INTERFACE
PIN NUMBER
5-8
12-15
PIN NAME
DATA LINES
9
READ ENABLE
10
CHIP SELECT
20
WRITE ENABLE
17
INTERRUPT REO.
SYMBOL
DALO-7
FUNCTION
Eight active true three state bi-directional data
110 lines used for information transfer to and
from the combined status/data register.
A low on read enable in conjunction with CS
gates the contents of the status/data register
onto the DAL lines.
A low on chip select enables access to internal
status/data register.
A low on write enable in conjunction with CS
writes the state of the DAL lines to the
status/data register.
Makes a low to high transition when the interrupt register needs servicing.
INTRa
622
()PTIONAL DISPLAY INTERFACE
PIN
NUMBER
22·24
25·28
PIN NAME
DIGIT SELECT
BCD OUT
SYMBOL
OS 0·2
BCD 0·3
Digit select for multiplexed display.
BCD data for multiplexed display.
COMMAND DESCRIPTION
The WD2412 will accept and execute 24 commands.
Command words should· only be loaded onto the
status/data register when the command ready status
word appears on the status/data register. The com·
mand ready byte is EEH. Whenever a data transfer
takes place, the receiving device (either the TDC or
the host) must acknowledge the transfer by sending
a FFH. For ease of discussion, commands are divided
into three types.
SET RELATIVE INTERRUPT
(Interrupts are enabled)
COMPUTER DIALOG WITH TDC FOR
TYPE II COMMANDS
TDC
COMPUTER
STATUS 1
if TDC ready:
TDC
COMPUTER
COMMAND
TDC
COMPUTER
STATUS 2
if TDC ready:
TDC
COMPUTER
BYTE 1
TDC
COMPUTER
STATUS 2
if TDC ready:
TDC
COMPUTER
BYTE 2
TDC
COMPUTER
STATUS 2
if TDC ready:
TDC
COMPUTER
BYTE 3
F2H
Type I Commands
Type I commands set internal flags and operating
modes. They are all considered completed after
transfer of the command.
EOH
DISPLAY OFF
E1 H
DISPLAY 12 HOUR TIME
E2H
DISPLAY 24 HOUR TIME
E3H
DISPLAY DATE'
E4H
DISPLAY USER
E5H
SELECT CRYSTAL TIMEBASE
E6H
SELECT EXTERNAL 50 Hz TIMEBASE
E7H
SELECT EXTERNAL 60 Hz TIMEBASE
E8H
DISABLE INTERRUPTS
COMPUTER DIALOG WITH TDC FOR
TYPE I COMMANDS
COMPUTER
STATUS 1
if TDC ready:
COMPUTER
COMMAND
FUNCTION
Type III Commands
Type III commands read internal registers. They are
all followed by three bytes of data. They are con·
sidered completed after transfer of data. All type III
commands are non interruptable.
The commands are:
F3H
READ 12 HOUR BCD TIME
F4H
READ 24 HOUR BCD TIME
F5H
READ BINARY TIME
F6H
READ DATE/POWER FAIL FLAG
F7H
READ DAY OF WEEK
F8H
READ RELATIVE INTERRUPT
COMPUTER DIALOG WITH TDC FOR
TYPE III COMMANDS
COMPUTER
STATUS 1
if TDC ready:
COMPUTER
COMMAND
COMPUTER
STATUS 3
if TDC ready:
COMPUTER
BYTE 1
COMPUTER
ACKNOWLEDGE
COMPUTER
STATUS 4
if TDC ready:
COMPUTER
BYTE 2
COMPUTER
ACKNOWLEDGE
COMPUTER
STATUS 4
if TDC ready:
COMPUTER
BYTE 3
COMPUTER
ACKNOWLEDGE
TDC
TDC
lype II Commands
Type II commands set internal registers. They are all
followed by three bytes of data. They are considered
completed after transfer of data. All type II com·
mands are non interruptable.
The commands are:
E9H
SET 12 HOUR BCD TIME (BIN and BCD24
also set)
EAH
SET 24 HOUR BCD TIME (BIN and BCD12
also set)
EBH
SET DATE
ECH
SET DAY OF WEEK
EDH
SET USER
EFH
SET ABSOLUTE 12 HOUR TIME INT
(Interrupts are enabled)
FOH
SET ABSOLUTE 24 HOUR TIME INT
(Interrupts are enabled)
F1 H
SET ABSOLUTE DATE INTERRUPT
(Interrupts are enabled)
•
623
TDC
TDC
TDC
TDC
TDC
TDC
TDC
TDC
TDC
TDC
TDC
CKI
CKO
XTLTST
CRYSTAL
TEST
AND
RESET
LOGIC
RESET>r------------------------------~
50/60 Hz
TIMEBASE
SELECT
) r - - - - - - - - - - - - - - - - - - - - - - - - - - -__
BCD12
DAY
I NT RO .....- - - - - - I
3
DSO-2
DISPLAY
MULTIPLEXER
BCDO-3
DISPLAY
SELECT
USER
LATCH
CS--~
WE--~
RE--~
HOST
INTERFACE
AND
CONTROL
LOGIC
TIME
SAMPLE
AND
SET
11'-----'\ TO ALL INTERNAL
REGISTERS
LATCHES
DALO-7
WD2412 FUNCTIONAL BLOCK DIAGRAM
t324
Bin Register
This read only register also holds the present time of
day, but in a straight binary format. The format is in
one-tenth second ticks since midnight. The value of
this 20 bit register can vary from 0 through 863,999
decimal. Data is arranged in a seven bit per byte
format with the most significant bit of the byte
always set to zero.
Master Reset
Upon receipt of a Master Reset, the WD2412 defaults
to the following values:
00:00:00 (Midnight)
BCD24
BCD12
12:00:00 AM
BIN
o
DATE
00/00/00
DAY
o (Sunday)
RELATIVE INT
o
Crystal
TIMEBASE
Off
DISPLAY
INTERRUPTS
Disabled
POWER FA.IL FLAG
Set
byte 3
~3
H10
I ~~ I
M10
I
I
S10
I
H
Hl0
I~
I
Ml0
I
I~ I
byte 3
I
010
!
01
II
Yl0
!
Yl
05
I
04
byte 2
I
I
D3!
02
byte 1
I
I
Dl!
DO
I
765432107654321076543210
Day Register
This read/write register holds the day of the week as
a binary integer ranging in value from 0 to 6. Sunday
is usually considered 0, but this is a completely
arbitrary designation. For software simplicity, set day
and read day are standard Type II and Type III commands respectively. On set day, the unused fields can
be set to anything that won't interfere with the
command protocol. On read day, the unused fields
are zeroed.
S1
BCD12 Register
This read/write register holds the present time of day
in a 12 hour BCD format. Data are arranged in a
packed BCD format with two digits per byte. An
AM/PM indicator is available on the most significant
bit of the most significant byte. This bit is reset for
AM and set for PM.
byte3
UNUS~
7 6 5 4
byte 1
byte 2
Ml0
byte 1
User Display Register
This write only register is used for user programmable outputs to the optional six digit display. Valid
characters are 0-9 and blank. Blanks are entered as
10's.
765432107654321076543210
bvte3
bits 0·6
765432107654321076543210
byte 1
~ I
IH
byte 2
byte3
BCD24 Register
This read/write register holds the present time of day
in a 24 hour BCD format. Data are arranged in a
packed BCD format with two digits per byte.
I
bits 7·13
Date Register
This read/write register holds the present date in a
BCD format. Again, data is arranged in a packed BCD
format with two digits per byte.
ORGANIZATION
The WD2412 includes eight 3-byte user addressable
registers. These registers are 12 hour BCD Time of
Day (BCD12), 24 hour BCD Time of Day (BCD24)
Binary Time of Day (BIN), Date (DATE), Day (DAY),
User (USR), Time of Day Absolute and relative interrupt register (INT) are extended (Date Absolute)
interrupted register (XI NT).
byte 2
01
byte 1
765432107654321076543210
Power Fail Flag
When power is restored to the WD2412, it initiates a
master reset. As part of this, the Power Fail Flag is
set. Normally, at the end of a day, the DAY and DATE
registers are incremented. When the Power Fail Flag
is set, the DATE register remains at 00/00/00 to indicate that the power failed although the DAY register
is still incremented. Elapsed time since WD2412
power up can be determined by reading any time of
day register in conjunction with the DAY register.
byte3
1
byte 2
Ml
765432107654321076543210
625
321 0
byte 2
UNUSED
byte 1
IUNUSED!
DAY
7654321076543210
INT and XINT Registers
These registers have three modes, depending on
how they are set. In the relative mode, a binary
countdown value is loaded into the INT register and
an interrupt is generated when this value is
decremented to zero. When the terminal value is
reached, the register is automatically re-Ioaded,
unless specifically disabled by the interrupt service
routine. This feature allows periodic interrupts with
no software overhead. The period can be set
anywhere from 100 mS to 1 day.
If the INT register is read while in the relative mode,
the number of ticks until interrupt will be returned.
The data pattern is in the same format as in the BIN
register.
In the absolute time mode, a time of day in the same
format as the BCD24 register is loaded into the INT
register. When this time is matched, a single interrupt
will be produced and then the interrupts will be
disabled. To enter the absolute time/date mode, load
the INT register with the absolute time then load the
XI NT register with the absolute date. An interrupt will
only be generated when both time and date match.
NAME
SEG
AM
e
PM
c
TIME
d
DATE
b
DESCRIPTION
Lit only when displaying 12 hour
time
Lit only when displaying 12 hour
time
Lit when displaying 12 or 24 hour
time
Lit when displaying date
ABSOLUTE MAXIMUM RATINGS
Voltage at Any Pin Relative to GND ... - 0.5V to + 7V
Ambient Operating Temperature
(Note 1) ....................... O°C to + 70°C
Ambient Storage Temperature
Ceramic .................. - 65°C to + 150°C
Plastic .................... - 55°C to + 125°C
Lead Temperature (Soldering, 10 sec.) ....... 300°C
Power Dissipation .............. 0.75 Watt at 25°C
0.4 Watt at 70°C
Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC
electrical specifications are not ensured when
operating the device at absolute maximum ratings.
OPTIONAL DISPLAY
The WD2412 can interface to a seven segment by six
digit display and four status indicators. 12 or 24 hour
time, date, or user defined numeric message can be
displayed. Four status indicators are provided as
follows:
NOTE 1: An extended temperature range WD2412 is
available which will operate within an
ambient temperature range of - 40°C to
+85°C.
DC ELECTRICAL CHARACTERISTICS
O°C ~TA~ + 70°C, 4.5V~VCC~6.3V unless otherwise noted.
PARAMETER
Operating Voltage (VCC)
Operating Supply Current
Input Voltage Levels
CKllnput Levels
Crystal Input
Logic High (VIH)
Logic Low (VIU
All Other Inputs
Logic High
Logic High
Logic Low
Output Voltage Levels
Standard Output
TTL Operation
Logi~ High (VOH)
Logic Low (VOU
THREE-STATE Output
Leakage Current
CONDITIONS
=
MIN
MAX
UNITS
4.5
6.3
40
V
mA
0.4
V
V
0.8
V
V
V
0.4
V
V
+10
/AA
=
VCC
5V, TA
25°C
(all inputs and outputs open)
2.0
= Max
= 5V ± 5%
3.0
2.0
= 5V ± 5%
= 1oo/AA)
= -1.6mA
2.4
VCC
VCC
VCC
IOH
IOL
-10
626
AC ELECTRICAL CHARACTERISTICS
MIN/MAX
UNITS
50 min
5min
300 min
250 max
200 max
ns
ns
ns
ns
ns
Write Operation (Figure 3)
Chip Select Stable Before WR - tcsw
Chip Select Hold Time forWR - twcs
WR Pulse Width - tww
20 min
20 min
300 min
ns
ns
ns
Data Set-Up Time for WR - tow
Data Hold Time for WR - two
2QOmin
40 min
ns
ns
PARAMETER
CONDITIONS
Read Operation (Figure 4)
Chip Select Stable Before RD - tCSR
Chip Select Hold Time for RD - tRCS
RD Pulse Width - tRR
Data Delay from RD - tRD
RD to Data Floating - tDF
CL = 5Opf; VCC = 5V ± 5%
Figure 5 INPUT/OUTPUT TIMING DIAGRAM (CRYSTAL + 16)
I CSW
'i
- WCS
tww
,
J
If
I..-tDW--....
-.... tWD~
X
DAL
I.-
INTR
tWI
Figure 3 WRITE OPERATION TIMING
CS--~I
R5 _ _ _
I.
+-_-J"~--tRR--""I~~tR!2C§:S~~
tCSR
_ __
}I'--~-----'I
~---II'*"";-tR-D"'"'·v
DAL--------~~,~
/ . . - - tDF------_ _ _ _ _ _ _ _ _ _~
Figure 4 READ OPERATION TIMING
~ INSTRUCTION CYCLE T I M E 4
CKI~
BCDO·BCD3
DSO·DS2
~-
Figure 5 INPUT/OUTPUT TIMING DIAGRAM (CRYSTAL ... 16)
See page 725 for ordering information.
627
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rig,ts of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notir:e.
628
Prlnled In USA
Memory Products
Page
Part Number
FR1502
WD1510-00,01
WD1511
WD5010
WD5869
WD74HC200
WD8206
WD8207
First-In/First-Out Buffer Register ........................................
LIFO/FIFO Buffer Register ............................................
LIFO/FIFO Support Device ............................................
Single/Dual Read Content - Addressable Memory .........................
Dynamic Shift Register ...............................................
256 x 1 CMOS Static RAM .............................................
Error Detection and Correction Unit .....................................
Advanced Dynamic RAM Controller .....................................
629
631
637
641
645
649
653
657
677
630
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
."
FR1502 First·ln/First·Out Buffer Register
XI
.....
CJ1
o
N
FEATURES
• 40 CHARACTERS BY 9 BITS
EXPANDABLE CHARACTER AND BIT SIZE
(CASCADE CAPABILITY)
DC TO 1 MHz ASYNCHRONOUS I/O ACCESS
GENERAL DESCRIPTION
The FIFO (First-ln/First-Out) Storage Chip is an asynchronous memory organized in a nine-bit by forty-character stack.
Characters are loaded at the top of the stack and then "sink"
to the bottom of the stack, or to the level of previously entered data, without external clocks being applied. As a character is taken from the bottom of the stack, all of the previously loaded characters will automatically propagate toward
the output (bottom of stack).
I.
I.
'. INPUT/OUTPUT READY STATUS FLAGS
'. THREE STATE OUTPUTS
'. SEPARATE INPUT AND OUTPUT ENABLES
Data can be entered whenever the INPUT REGISTER
EMPTY line is high by strobing INPUT STROBE. The INPUT
ENABLE line must also be high while strobing. The INPUT
STROBE resets INPUT REGISTER EMPTY and latches the
input data. As soon as this data is latched, INPUT REGISTER EMPTY will again go high and additional data can be
loaded.
'. DIRECTLY TTL AND DTL COMPATIBLE
MASTER RESET
I.
I.
NO EXTERNAL CLOCKS REQUIRED
• AVAILABLE IN REL-PAC (F) OR CERAMIC (E)
PACKAGES
When data reaches the FIFO output, the OUTPUT DATA
READY line will go high. The data is then valid at the outputs
(providing the OUTPUT ENABLE line is high). The falling
edge of the OUTPUT STROBE causes the OUTPUT DATA
READY line to go low and to shift new data into the output
register. When the new data is available, the OUTPUT DATA
READY signal again goes high.
APPLICATIONS
POINT OF SALE TERMINALS
DATA TRANSMISSION BUFFER
LINE PRINTER INPUT BUFFER
KEY-TO-TAPE/KEY-TO-DISC EQUIPMENT
The FIFO output data lines are in high impedance state
whenever the OUTPUT ENABLE line is low.
CARDIT APE READERS
The logic conventions and internal delays designed into the
FIFO allow direct expansion of the memory without extemal
hardware (Cascade Mode).
AUTO DIALERS
CRT BUFFER MEMORY
CONTROL STACK SILO ORIENTED MACHINES
-.
COMPUTERITERMINALS I/O INTERFACE
BUFFER
TELEPRINTER BUFFER
Vss
IRa
IR.
IR,
IR,
IR,
IR.
IRo
IR7
MR
IRa
IE
OS
IS
OE
VDD(GND)
VGG
IRE
ODR
ORo
ORa
OR,
OR7
OR,
OR.
ORa
OR,
OR.
PIN CONNECTIONS
631
"en.....
:xl
o
N
INTERFACE SIGNALS DESCRIPTIONS
PIN
NUMBER
SIGNAL NAME
SYMBOL
FUNCTION
25-28,
2-6
INPUT REGISTER
IROIR8
Input datalines. These are input (but not latched) to the
FIFO independently of the INPUT ENABLE or INPUT
STROBE.
20
INPUT REGISTER
EMPTY
IRE
Wilen high, indicates that data can be loaded into the FIFO. It is
reset to a low by falling edge of the Input Strobe.
22
INPUT STROBE
IS
Latches INPUT DATA in the FIFO on rising edge.
24
MASTER RESET
MR
When high, clears the FIFO control registers. This leaves the
OUTPUT REGISTER DATA (ORO-OR8) in an undefined state,
sets INPUT REGISTER EMPTY (IRE) to high and resets OUTPUT DATA READY (ODR) to low.
OUTPUT REGISTER
DATA
OROOR8
Thiee state data outputs. When OE is low, the outputs are in the
high impedance state. When OE is high, these lines present the
prEvious latched data in a first-in/first-out manner.
OUTPUT DATA
READY
ODR
ODR is high when data is latched and available at the data output
lin.3s. Is reset to low by the falling edge of OUTPUT STROBE
(OS) if OUTPUT ENABLE (OE) is high.
OUTPUT STROBE
OS
A tailing edge of this signal resets the OUTPUT DATA READY
(OOR) line and then shifts the data one step towards the output
if OUTPUT ENABLE (OE) is high.
INPUT ENABLE
IE
WI-en high, enables the input control logic. At any state of
IE or IS, the INPUT DATA will be transferred into the FIFO,
but can not be latched unless IE is high.
8
OUTPUT ENABLE
OE
When low, OE puts the output lines (ORO-OR8) in high impedance state. When high, the output lines present the output data.
1
VSS POWER
SUPPLY
Vss
+5VDC
21
VOO POWER
SUPPLY
Voo
o \/olt-GND
9
VGG POWER
SUPPLY
19-11
10
7
23
-12VDC
(i32
( . . - fiRST STAGE HAS
:--J-l
~~~TTy ~~~E!-------,--_ _ _
.
Yl
-,NPUT STROBE IGNORED
SINCE IE IS LOW
~
INPUT STROBE
!lSI
f
AGAIN BECOME EMPTY
LATCHES DATA AND RESETS IRE
1---1L
____________ ~
(SEE NOTE)
DATA MUST
DATA MUST
INPUT ENABLE
HEI
_ NEW DATA
0-l
OUTPUT DATA - - - - - - - - , I -_ _ _
READY IODRI
OUTPUT STROBE
10SI
-w=
•
OUTPUT STROBE
IGNORED SINCE
DE IS LOW
OUTPUTS
FLOATING
•
AVAILABLE
'---------I
RESETS ODR AND
(
SHIFTS DATA
~r+---------,U
OLD DATA
VALID
DATA CHANGING
STATE
NEW DATA
VALID
DATA CHANGING
STATE
NEW
DATA VALID
~-------~
OUTPUT ENABLE _ _ _ __
SWITCHING CHARACTERISTICS
SWITCHING WAVE FORMS
IS
_ _ _J
(SEENO~E)
TOIS
•
::~"
IRE
TOIH
=
~I
___-'I
TISL
.'
=:XW/ll&
INPUT
DETAIL
---D-AT-A-VA-U-D-""'\I~II/II/7IZX~~_-_-D:AT:A=VA=U=D
~~------'""f
\_--
OUTPUT
DETAIL
SWITCHING WAVE FORMS
633
ABSOLUTE MAXIMUM RATINGS
'T1
+O.3V to -20V
V GG Supply Voltage
::D
-"
CJ1
o
N
VDD Supply Voltage
+O.3V to -20V
Clock Input Voltage*
Logic Input Voltage*
+O.3V to -20V
+O.3V to -20V
Logic Output Voltage*
+O.3V to -20V
Storage Temperature (Ceramic)
Storage Temperature (Plastic)
*VGG
= VDD = OV
NOTE: These voltages are measured with respect to V SS (Substrate)
ELECTRICAL CHARACTERISTICS
(Vss = +5V ± 5%; Voo = OV; VGG =-12V ± 5%; TA = O°C to +70°C unless otherwise specified)
SYMBOL
PARAMETER
MIN
VSS-1.5V
VOL
INPUT LOGIC LEVELS
Low-level Input Voltage
High-level Input Voltage
OUTPUT LOGIC LEVELS
Low-level Output Voltage
VOH
High-level Output Voltage
Vss-1.0V
III
ISS
INPUT CURRENT
Low-level Input Current
(each pin)
SUBSTRATE SUPPLY CURRENT
IGG
GATE SUPPLY CURRENT
Vil
VIH
MAX
CONDITIONS
0.8V
VSS = 4.75V
(NOTE 1)
(NOTE 2)
VSS = 5.25V
IOl = -1.6mA
VSS = 4.75V
IOH = +200 uA
O.4V
-1.6mA
65 mA
-30mA
VSS = 5.25V
VIN = O.4V
VSS = 5.25V
VGG = -12.6V
VIN = O.4V
NOTE 1: All inputs have pull-up resistors. This allows unloadt3d TIL outputs of 2.0V to be connected and operate properly.
When connected, this voltage (2.0V) will become VSS -1.5V.
NOTE 2: VOland VOH when OE = VIH (low impedance output). High impedance (OE
6:34
=
Vld = 10 Mohm.
:SWITCHING CHARACTERISTICS (Vss = +5V, VDD
SYMBOL
=
OV, VGG
=
See "Switching Waveforms"
-12V, TA = O°C to +70°C, CLOAD
PARAMETER
=
10 pf)
MIN
CONDITIONS
MAX
TIES
Input Enable Setup Time
TIEH
T OIS
Input Enable Hold Time
' Data Input Setup Time
o ns
o ns
o ns
TOIH
Data Input Hold Time
250 ns
TIRl
Input Register load Time
TIRE
TISl
T ISH
Input Register Empty Time
Input Strobe low Time
Input Strobe High Time
TOES
Output Enable Setup Time
TOEH
Output Enable Hold Time
50 ns
TOSl
Output Strobe low Time
150 ns
TOOR
Output Data Ready Time
200 ns
TOR
Data Reset Time
600 ns
TpO
Output Propagation Delay Time
250 ns
TOORl
Output Data Ready low
TOSH
Output Strobe High Time
TOOV
TR
Maximum Ripple Time
10,us
(NOTE 2)
TB
Maximum Bubble Time
25,uS
(NOTE 3)
TMR
Master Reset Pulse Time
1 MHz
(NOTE 4)
fO
"-
250 ns
800 ns
450 ns
150 ns
50 ns
(NOTE 1)
600 ns
500 ns
Output Data Valid Time
200 ns
500 ns
Maximum Data Rate
NOTE 1: T rise = Tfall = 10nS.
NOTE 2: Ripple Time-time required for a single data character to propagate from the input to the output of an empty FIFO (IS
strobing edge to ODR rising edge).
NOTE 3: Bubble Time- time required for a "hole" to propagate from the output to the input of a full FIFO (falling edge of OS to
rising edge of IRE).
NOTE 4: The maximum data rates for a "single" FIFO (not cascaded) and for FIFO's cascaded together are the same.
GENERAL NOTE: All A.C. test points are at O.BV or 2.0V.
635
ORDERING INFORMATION
'TI
:c
.....
en
o
MAX.
PART NO.
PACKAGE
TYPE
CASCADABLE
DATA
RATE
E·10
F·10
E·11
F·11
CERAMIC
PLASTIC
CERAMIC
PLASTIC
YES
YES
NO
NO
1.0 MHz
1.0 MHz
500 KHz
500 KHz
I\)
V55
INPUT
STROBE
V55
INPUT
ENABLE
.R,
.R,
9.",
FIFO
.R,
.R,
.R,
EXPANSIOI" EXAMPLE
FR1502E1F·10
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Dig.tal Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
See page 725 for ordering information.
636
WESTERN DIGITAL
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WD1510·00,.01,.02 LIFO/FIFO Buffer Register
IFEATURES
It WORD LENGTH SELECTABLE: 128 OR 132
It 9 BIT WORD WIDTH
41
DC TO 650 KHZ (- 00),1 MHz (- 01), 1.2 MHz (- 02)
.. EMPTY AND FULL FLAGS
.. THREE-STATE DATA LINES
.. 5-VOLT ONLY
41
NO EXTERNAL CLOCKS REQUIRED
41 TTL COMPATIBLE ON ALL INPUTS AND
OUTPUTS
41 28 PIN PLASTIC OR CERAMIC DIP
41 CASCADABLE WITH WD1511 SUPPORT CHIP
tI
FULLY ASYNCHRONOUS DUAL PORT
OPERATION
......
......
C1I
specify the data flow direction. The WD1510 is
fabricated in 5-volt only N-channel technology.
APPLICATIONS
• POINT OF SALE TERMINALS
• COMPUTER-TO-PERIPHERAL BUFFER
• CRT BUFFER MEMORY
• LINE PRINTER BUFFER
• INTERRUPT STACK (LIFO MODE)
Vss
EMPTY
eSA
FULL
eSB
sse
DIR
PB8
PA8
PB7
PA7
PB6
PA6
PB5
PA5
Vee
PB4
3
128/132
MR
PBa
PA1
PB1
PA2
PB2
PA3
PB3
PA4
GENERAL DESCRIPTION
The WD1510 is an MOS/LSI Memory Buffer which is
organized as a 9-bit by 128 or 132 word stack. The
chip has 2 bidirectional data ports and may be read
from or written into either port. Thus, the chip can
function as a LIFO from either port or it can function
as a FIFO, with data flow from either port A to port B
or vice versa. The DIRECTION input pin is used to
PIN DEFINITIONS
."--
PIN NUMBER
1
2
3
VSS
EMPTY
CHIP SELECT PORT A
SYMBOL
VSS
EMPTY
CSA
4
1280R 132
128/132
5
MASTER RESET
MR
6,8,10,12,114,
17,19,21,23
7,9,11,13,15
18,20,22,24
16
25
PORT A DATA LINES
PAO-PA8
Ground
Indicates when there is no data in the buffer
Used to select Port A for either a Read or Write
operation
Used to set word length. When low word length
128, when high word length
132
When pulsed will clear the buffer and set the
EMPTY pin
Bidirectional DATA Port for reading or writing
PORT B DATA LINES
PBO-PB8
Bidirectional DATA Port for reading or writing
VCC
DIRECTION
VCC
DIR
SSC
27
SYSTEM SENTINELTM'
CHECKOUT
CHIP SELECT PORT B
+ 5 volts ± .25V
When low DIR specifies that Port A may be read
from and Port B may be written into. When high
DIR specifies that Port A may be written into
and Port B may be read from.
No connection (For future use)
CSB
28
FULL
FULL
26
NAME
FUNCTION
=
"--_._"._-
=
Used to select Port B for either a Read or Write
Operation
Indicates that all 132 or 128 words of memory
are loaded with data
637
9
~
6......
6I\)
:ec
.....
PORT
A
en
.....
o
6
p
6.....
9
PORT
B
9 BITS
BITS
WDI510
C S A - - - - - - -__~
~~--------CSB
6I\)
DIR---....J
MR-------'
L--_--I~
128/132 - - - - - -
OPERATION
The WD1510 contains a 132 x 9 buffer which may be
programmed for 128 x 9 operation. Setting the
128/132 pin to a Logic 0 enables the EMPTY and
FULL lines to be activated when 128 bytes are read or
written. When the 128/132 line is set to a Logic 1 or
left open, the 132 byte operation is enabled. This line
contains an internal pull-up resistor of approximately
5KQ.
PORTA
WRITE
READ
EMPTY
1, then data is written into Port A and read out of Port
B. Reading/Writing to the two ports can be done
asynchronously.
In the LIFO mode only one port is used. For example,
if using Port A, the DIRECTION line is set to a Logic
1 to enter data, and is reset to a Logic 0 to read data.
Reading <2!:...writing is performed by setting the appropriate CS (Chip Select) line to a Logic O. After the
specified hold time has expired, data ~ be entered
or read on the rising edge of CSA or CSB. In a Read
mode, data is valid as long as CS remains active.
Both Ports return to the high impedance state when
CS is returned to a Logic 1.
When the Master Reset line (pin 5) is set to a Logic 1,
all internal counters are reset and the EMPTY Flag is
set. Prior to reading or writing data, the DIRECTION
Line (pin 25) must be set to select the desired
operation:
DIR
1
0
'------~
FULL
The EMPTY Line (Pin 2) and the FULL line (Pin 28)
are used as status or interrupt lines to determine the
status of the buffer. When both EMPTY and FULL are
at a Logic 0, the buffer contains 1 thru 127 bytes
(128/132 = 0) or 1 thru 131 bytes (128/132 = 1).
PORTB
READ
WRITE
To operate the device in the FIFO mode, both Ports
must be used. If the DIRECTION line is set to a Logic
ELECTRICAL CHARACTERISTICS _ _ _ _ _ _. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Storage Temperature
Plastic ................... - 55°C to + 125°C
Ceramic .................. -65°Cto +150°C
ABSOLUTE MAXIMUM RATINGS
VCC with respect to VSS
(Ground ............................. + 7V
Max Voltage on any Pin with
respect to VSS . . . . . . . . . . . . . . .. - 0.5V to + 7V
Operating Temperature ............. O°C to 70°C
SYMBOL
III
ILO
VIH
VIL
VOH
VOL
ICC
CHARACTERISTIC
Input Leakage
Output Leakage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Power Supply Current
OPERATING CHARACTERISTICS,(DC)
TA = O°C to 70°C, VSS = OV, VCC = + 5V ± .25V
MIN
TYP
MAX
10
10
2.2
0.8
2.4
125
£j38
.4
200
UNITS
IJA
IJA
V
V
V
V
mA
CONDITIONS
VIN = VCC
VOUT = VCC, VSS
10 = -100IJA
10 = 1.6mA
All outputs open
A.C. TIMING CHARACTERISTICS
D
TA ODC to 70 C, VSS
OV, VCC
=
=
= + 5V ± .25V, VOH = 2.0V, VOL = 0.8V
WD1510·00
CHARACTERISTICS
Master Reset Time
Data Valid from CS
Data Hold from CS
DIR Setup Time
EM PTY Val id from CS
FULL Valid from CS
CS Pulse Width Low
CS Pulse Width High
CS Cycle Time
Data Setup Time
Data Transfer Rate
SYMBOL
TMR
TDV
TDH
TDIR
TEV
TFV
TCSL
TCSH
TCY
TDS
FMAX
WD1510·01
MAX
MIN
400
MIN
250
WD1510·02
MIN
250
MAX
550
350
150
1500
300
80
834
100
1000
550
550
350
350
600
600
1540
80
MAX
250
250
417
417
834
50
500
500
1000
50
.65
1.0
1.2
UNITS
NS.
NS.
NS.
NS.
NS.
NS.
NS.
NS.
NS.
NS.
MHZ
1....
..1 - - - TesL - - - - 1...
~1
eSA
or
!4-- TDS --"1
eSB
I
I
:
"""""l!lI"""7"Z-rZ-rZ-rZ-r/-rL-rZ......,.Z......,.l/I~'
....,.....,~/I'""'IIZX
DATA PORT
-+!
DIR
~TDIR
"
I
:-41- TDH
DATAv~BYJ BE WIIIII
~
WRITE OPERATION
II40Il..t - - eSA
or
---I"'~I
TeSL
eSB
Z/IOIIIIIZZIZ7IIXDATA VALIDX!IIIIIZI
DATA PORT
READ OPERATION
MR
eSA
or
eSB
___
~~TMR~~_______
J..=1..
'--------114TeSL
...
TEV
-...J TeSH
_ _+-_ _ _ _ _ _ _T~F~V~
EMPTY or FULL
--JX
D _VA_L_U_E_ _ _
O_L _
_ _- t - _
...
11-------I
NEW' VALUE :
I
--------IJo... :
I......f - -_ _ _ _ _ Tey
I
MiSe TIMING
I
See page 725 for ordering information.
639
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....
....
CJ'I
C?
8
'6
....
6
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6......
6I\)
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rigllts of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
640
Printed
In
USA
WESTERN DIGITAL
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WD1511 LIFO/FIFO Support .Device
FEATURES
DESCRIPTION
• CASCADES UP TO 4 ASYNCHRONOUS RAM
BASED LlFO'S/FIFO'S
The WD1511 is designed to cascade RAM based
FIFO's without resorting to 'bucket brigade' architectures. Cascading is implemented by logically
demultiplexing sequential data bytes into two (or
four) FIFO's. Data read out of the FIFO's is logically
multiplexed, restoring the original order.
The WD1511 provides all of the necessary data
strobe steering logic to demultiplex/multiplex the
data stream for both FIFO and LIFO applications.
This technique is also employed in implementing
2-to-1 or 4-to-1 bus conversion.
Normally, data strobes are routed through the
WD1511. However, in applications where data hold
times are critical, grounding the EXT. STROBE pin
makes it possible to reduce propagation delays by
gating the strobes externally to the WD1511.
The WD1511's cascading technique reduces the duty
factor for each FIFO device and may make higher
throughput possible.
• CONTROLS 2-TO-1 OR 4-TO-1 BUFFERED BUS
CONVERSION
• PIN SELECTABLE OPERATING MODES
• LOGICALLY TRANSPARENT TO HOST
INTERFACE
• ALL INPUTS AND OUTPUTS TTL COMPATIBLE
• SINGLE + 5V SUPPLY
• 20 PIN DUAL-IN-LiNE PACKAGE
• DIRECT COMPATIBILITY WITH THE WD1510
LIFO/FIFO
RESET
VCC
CSAO
CLKA
CSA1
CLK B
CSA2
EMPTY
em
FULL
CSBO
DIR
CSB1
FIFO/LIFO
CSB2
EXT. STROBE
CSB3
2/4A
VSS
2/4B
2/4A
COUNTERA
STEERING
LOGIC A
CLKA -r----------~~~CLK
CSAO
'CSA1
PIN DESIGNATION
FULL
CSA2
EMPTY
CSA3
DIR
FIFO/LlFO-+~L.....r----trl---'"
DIRECTION
CONTROL
EXT. STROBE
COUNTER B
UPIDN
'--1-+...1INHIBIT
CLK B -r-----~+-i~gt~AR
RESET-r----------~~--~
2/4B
-t-------------'
FUNCTIONAL BLOCK DIAGRAM
641
CSBO
CSB1
CSB2
CSB3
ORGANIZATION
The WD1511 is organized as a pair of synchronous
up/down Gray counters with fully decoded outputs.
Clocking occurs on low-to-high transitions of the
clock inputs. FULL and EMPTY FIFO status inputs
are gated with DIR to inhibit counting during FIFO
overflow or underflow. A logic one on either DIR or
FIFO/LIFO causes the counters to increment when
clocked and the decoders to decode for N. A logic
zero on both the DIR and FIFO/LIFO inputs causes
the counters to decrement when clocked and the
decoders to decode for N -1. A2/4 and B2/4 determine
the number of active discrete outputs for each
decoder. A logic one on EXT. STROBE causes both
decoders' active low outputs to be "OR-ED" with the
counter clocks. Reset forces the counters to
asynchronously clear.
WD1511 PIN DEFINITIONS
PIN NUMBER
FUNCTION
PIN NAME
SYMBOL
RESET
RESET
2,3,4,5
CHIP SELECT
'A' OUTPUTS
CSAO-CSA3
6,7,8,9
CHIP SELECT
'B' OUTPUTS
CSBO-CSB:3
10
11
VSS
2/4B
VSS
2/4B
12
2l4A
2/4A
13
EXTERNAL
STROBE
00.
FIFO/LIFO
FIFO/LIFO
14
STROBE
642
Active high input. Asynchronously clears
counter A and counter B.
Active low, 1-of-4 CSA steering logic outputs.
CLKA or EXT. STROBE must be low to enable
the active output.
Active low, 1-of-4 CSB steering logic outputs.
CLKB or EXT. STROBE must be low to enable
the active output.
Ground
This input selects the number of active CSB
outputs. When 2/4B is open or held high, 1-of-2
deco~ is performed on counter 'B'; CSB2
and CSB3 are inactive and remain high, independently of the state of counter 'B'. When 2/4B
is low, 1-of-4 decoding is performed on counter
'B'. This input includes an internal pull-up
resistor of approximately 6.5KQ.
This input selects the number of active CSA
outputs. When 2/4A is open or held high, 1-of-2
decoding is performed on counter 'A'; CSA2
and CSA3 are inactive and remain high, independently of the state of counter 'A'. When 2/4A
is low, 1-of-4 decoding is performed on counter
'A'. This input includes an internal pull-up
resistor of approximately 6.5KQ.
This active low input enables the CSA and CSB
outputs independently of the levels of CLKA
and CLKB. With EXT. STROBE low, several options are available; the chip select outputs can
be clocked externally with a 74LS02 or equivalent to generate active high data strobes; a
74LS32 or equivalent can be used to generate
active low data strobes; WD1511's can be cascaded without additive propagation delays; the
WD1511 can be used as a dual, 4-output Johnson counter. This input includes an internal pullup resistor of approximately 6.5KQ.
When this input is open or held high, or when
the DIR input is high, the active steering logic
outputs are equal to the current states of the
counters and the counters will increment when
clocked. When both the FIFO/LIFO and DIR inputs are low, the active steering logic outputs
are equal to the current states of the counters,
logically minus one, and the counters will decrement when clocked. This input includes an internal pull-up resistor of approximately 6.5KQ.
PIN NUMBER
PIN NAME
SYMBOL
FUNCTION
15
DIRECTION
DIR
16
FULL
FULL
17
EMPTY
EMPTY
18
CLOCK B
19
CLOCK A
This active high input is used to prevent the
data pointers (chip selects) from being invalidated during underflow conditions. When both
the EMPTY and DIR inputs are high, counter 'B'
is inhibited or frozen at its current count. When
EMPTY is high and the DIR input is low, counter
'A' is inhibited. This input must be held low if
unused.
This input clocks counter 'B' on the low-to-high
transition. The active 1-of-4 CSB output is
enabled when either CLKB or EXT. STROBE is
low.
This input clocks counter 'A' on the low-to-high
transition. The active 1-of-4 CSA output is
enabled when either CLKA or EXT. STROBE is
low.
20
VCC
VCC
+5VDC ±5%
This input determines which counter shall be inhibited when the full or empty~ts are active.
It is also gated with the FIFO/lTFO input to control steering logic decoding and provide counter
up/down control.
This active high input is used to prevent the
data pointers (chip selects) from being invalidated during overflow conditions. When both
the FULL and DIR inputs are high, counter 'A' is
inhibited or frozen at its current count. When
FULL is high and the DIR input is low, counter
'B' is inhibited. This input must be held low if
unused.
16 x 256 TO 8 x 512 BIDIRECTIONAL FIFO BUFFER
8
Example 'A' shows the WD1511 used to convert a 16
bit data bus to an 8 bit data bus. With the availability
of 4 steering logic outputs, the implementation
shown also utilizes the cascade feature providing a
256x16 to 512x8 FIFO Buffer. By placing a logic high
on 214B of the WD1511, decoding would be reduced
to 1 of 2 allowing a reduced buffer of 128x16 to 256x8.
A key feature of this implementation is the ability to
obtain a speed enhancement for both sides of the
data bus. As shown with the WD1510-01, the 8 bit
data may be read out at a 2MHz rate. This is due to
the FIFO's TCSH time being met during the access
times of the other devices. Another key feature with a
WD1510 implementation is the completely asynchronous 16 and 8 bus clocks, thereby allowing
bidirectional reads and writes asynchronously.
The basic system shown is easily modified to provide
many variations. Some of these are: 16 to 16 bit FIFO,
264x18 to 512x9 conversion, 512x9 to 512x9 FIFO, all
of which can be bidirectional.
16 BIT
BUS ClK.
WD
8 BIT 1511
BUS ClK.
EXAMPLE 'A'
643
9
x
528 LIFO
BUFFER
EMPTY
~
c
.....
(J1
.....
.....
CSAO r-----t-----\
C'CK'A
WD
1510
CSBO r-----------\
CSB 1 J...----4-----\
74LS32
WD1511
1~~r------------------------J
EXAMPLE 'C'
EXAMPLE 'B'
Example 'B' illustrates the simplicity in implementing
fourWD1510s cascaded for a 528x9 LIFO. This circuit
provides the same speed enhancement as Example
'A'. With the WD1510-01, a 2MHz byte rate transfer
can be obtained.
Example 'c' is shown with EXTSTROBE enabled.
This feature reduces the propagation delay of the
WD1511 to zero. This feature is required for systems
unable to meet data hold times. It is also recommended for use where WD1511 s are cascaded for
large buffer size applications.
It also is easily modified to provide many reduced
variations such as 256x8 org, or 512x8 org.
- - - - - - - - - - - - - - SPECIF~CATIONS - - - - - - - - - - - - - ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Ceramic .................. - 65°C to + 150°C
Ambient Temperature Under Bias. . . . .. 0 to 70°C
Plastic .................... - 55°C to + 125°C
Voltage On Any Pin With Respect
NOTE: Maximum limits indicate where permanent
device damage occurs. Continuous operation at
these limits is not intended and should be limited to
those conditions specified in the DC Electrical
characteristics.
to Ground (VSS) ................. - 0.5 to + 7V
Power Dissipation ........................ 0.5W
DC ELECTRICAL CHARACTERISTICS
TA = 0 to 70°C; VCC = 5.0V ± 10%; VSS = OV
SYMBOL
VIL
VIH
VOL
VOH
VCC
ICC
PARAMETER
Input Low Voltage
Input High Voltage
Output Low Voltage
High Level Output Voltage
Supply Voltage
Supply Current
MIN
TYP
·-0.5
2.2
MAX
UNITS
TEST CONDITIONS
+0.8
V
V
V
V
V
mA
IOL=4.0mA
IOH= -200J.lA
0.4
2.4
4.5
5.0
70
5.5
100
All outputs open
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Di~ital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
644
Printed
In
U S.A
WESTERN DIGITAL
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WD501 0 Single/Dual Read Content - Addressable Memory
A Content Addressable Memory (CAM) is a memory
device in which all memory cells are selected by
contents rather than by addresses. The CAM's
function is to compute local variable addresses from
global addresses by means of a fully associative
memory.
FEATURES
• DUAL READ CAPABILITY
16x64 BIT WORDS
TWO LOCAL VARIABLE ADDRESSES
• SINGLE READ CAPABILITY
32x32 BIT WORDS
ONE LOCAL VARIABLE ADDRESS
• WRITEABLE CONTENT WORDS
• VERTICAL CASCADING CAPABILITY
• REPLACES CACHE ADDRESSING SYSTEMS
WRITE
ADDRESS A
CAM A DATA OUTI
WRITE ADDR. IN
CAM A MATCH "'--~----I
T.S. ENABLE A&B
_......;;;2~_ _--..I
WRITE PULSE A&B _ _""'2'---_~
APPLICATIONS
Cache Memory Replacement
Cache Disk Controller
Pattern Recognition
Station Address Recognition
Primary Key Locater
Programmable PLA
COMPARE
ADDRESS A
COMPARE
ADDRESS B
ADDRESS
COMPUTATION
16 x64
DUAL READ
OR
32 x 32
SINGLE READ
CAM
WRITE
ADDRESS B
CAM B DATA OUT.
WRITE ADDR IN
1------. CAM B MATCH
......- - - - - SYSCLK
\-4------
32 BIT CAM MATCH
DUAL CAMI
SINGLE CAM
VCC
Figure 1 -
CAM ENABLE
GND
WD5010 CAM OVERVIEW BLOCK DIAGRAM
645
=E
c
..
c.n
0
0
VCC
SYSCLK
CAMEN
CAAO
CAA1
CAA2
CAA3
CAA4
CAA5
CAA6
CAA7
CABO
CAB1
CAB2
CAB3
CAB4
CAB5
CAB6
CAB7
GND
GND
D/WAO
D/WA1
D/WA2
D/WA3
D/WA4
D/WA5
CMA
CBM
D/WBO
D/WB1
D/WB2
D/WB3
D/WB4
D/WB5
DIS
ViJI5'lj
WPA
TSEA
TSEB
PIN CONNECTIONS
FUNCTIONAL DESCRIPTION
In the dual read mode, the CAM compares the
contents within itself and the Compare Address. If a
match occurs between the Compare Address and
one of the content words, then the data associated
with that content word will appear on the CAM Data
Out lines and a CAM Match signal will occur. In the
single CAM read mode, the Compare Addresses A
and B concatenate to form a 32 bit word. This word is
compared with a 32 bit CAM word formed by two
consecutive 16 bit content words. If a match occurs
the associated CAM data appears at both the CAM
data A and B lines and both A&B CAM Match signal
occurs.
The central component of the CAM is a RAM cell
with dual compare logic. When the address computation is in dual read configuration 6 bits of CAM
data are provided when the Compare Address is
matched with one of the 64 content words in the
CAM. The 6 bit CAM Data Out numbers range from
0000002 to 1111112 and are non-volatile. A CAM
Match signal is provided for each of the Compare A
and Compare B Addresses and indicates if the
content words of the CAM match the Compare
Address. See Figure 1.
Each content word address inside the CAM is
directly related to the Data Out number. By enabling
the Write Address Enable and providing a Write Pulse
and the desired Write Address on the DATA
OUTIWRITE ADDRESS IN LINES, the contents of the
CAM related to that Data Out number are written.
During write mode, the Compare Address is the
information which will be written into the content
word. The CAM has two sets of Compare Address
and Write Address lines which allows two content
words to be written at the same time.
646
PIN NUMBER
1
PIN NAME
POWER SUPPLY
SYMBOL
VCC
+ 5 Volt
2
3
SYSTEM CLOCK
SYSCLA
Provides clock to CAM.
FUNCTION
CAM ENABLE
CAMEN
Enables CAM operation.
4·11
COMPARE
ADDRESS A
CAAO-CAA7
During a dual read operation two 16 bit ad·
dresses are latched into the CAM through these
two 8 bit ports.
12-19
COMPARE
ADDRESS B
CA BO·CA B7
The CAM then compares the contents within
itself and outputs the data if a match occurs. In
the single read mode, the Compare Addresses
A and B concatenate to form a 32 bit word for
comparison with a 32 bit content word. If a
match occurs both the CMA and CMB lines will
be active. During a write mode, the Compare
Address is the data which will be written into
the content word indicated by the Write Ad·
dress In.
20
GROUND
VSS
Ground
21
3-STATE ENABLE B
TSEB
A logic low indicates the DIWA is in the 3-state
mode.
22
3·STATE ENABLE A
A logic low indicates the DIWB is in the 3-state
mode.
WRITE PULSE A
WRITE PULSE B
RESPECTIVE
A logic low pulse used to write the Compare
Address A or B information into the content
word A or B of the CAM. WP A or B is only effective when TSEA or TSEB are enabled.
23,24
25
26-31
DUALCAMI
SINGLE CAM
DIS
This signal is used to configure the CAM from a
dual read 16x64 CAM to a single read 32x32
CAM.
CAM DATA
OUTBI
WRITE ADDRESS
IN B
DIWB5·
DIWBO
In dual read configuration 6 bits of data are out·
put when the Compare Address B is
matched with one of the 64 content words in
the CAM. Each content word in the CAM is di·
rectly related to the Data Out number 0000002
to 1111112. During a write mode, Compare
Address B is written into the word selected by
the 6 bit Write Address B when TSEB is enabled
and WPB occurs.
32
CAM MATCH B
A logic low during a read mode indicates a
match has occurred between the Compare
Address B and a content word within the CAM.
33
CAM MATCH A
A logic low during a read mode indicates a
match has occurred between the Compare
Address A and a content word within the CAM.
34-39
CAM DATA OUT
AIWRITE
ADDRESS IN A
DIWA5·
DIWAO
In dual read configuration 6 bits of data are
output when the Compare Address A is
matched with one of the 64 content words in
the CAM. Each content word in the CAM is
directly related to the Data Out number 0000002
to 1111112. During a write mode, Compare
Address A is written into the word selected by
the 6 bit Write Address A when TSEA is enabled
and WPA occurs.
GROUND
VSS
Ground
40
647
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Dio;Jital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
648
Printed In USA
WESTERN DIGITAL
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WD5869 Dynamic Shift Register
FEATURES
e
e
e
e
tI
GENERAL DESCRIPTION
The WD5869 Dual 640 Bit Dynamic Shift Register is a monolithic MOS integrated circuit designed for use in computer
display peripherals. The clocks and recirculate logic are internal to reduce system component count, and 3 state output
buffers provide bus interface. The WD5869 is available in a
16 pin molded plastic package, or a 16 pin ceramic package.
DUAL 640 BIT
ADDITIONAL TAPS AT 512 ON EACH REGISTER
INTERNAL CLOCKING
HIGH SPEED
3 STATE OUTPUT BUFFER
APPLICATIONS
tI
tI
e
CRT DISPLAYS
COMPUTER PERIPHERALS
CRYPTOGRAPHY
PERIPHERAL
VIDEO
INTERFACE
INTERFACE
DUAL IN·LlNE PACKAGE
512A
NC
640A
Voo
OUTA
NC
VGG
512B
640B
NC
OUTB
v
NC
I
!lIN
!lOUT
o
VSS
NC
o
Figure 1
WD5869 PIN CONNECTIONS
SYNC
VERTICAL
ENABLE
SYSTEM CONTROL BUS
~
~
Figure 2 WD5869 TYPICAL APPLICATION BLOCK DIAGRAM
649
o
U
T
P
E
U
T
SPECIFICATIONS
=e
ABSOLUTE MAXIMUM RATINGS
Data and Clock Input Voltage and Supply
Voltages with respect to VSS
+0.3V to -20V
~
CO
Power Dissipation
800mW at TA = 25°C
Storage Temperature
-55°C to +125°C (Plastic Package)
-65°C to + 150°C (Ceramic Package)
~
TABLE 1 D.C. PARAMETERS
ELECTRICAL CHARACTERISTICS (DC)
TA = O°C to + 50°C, VSS = +5V ± 5%, VOO = -5V + 5%, VGG = -12V ± 5%
SYMBOL
100
PARAMETER
MIN
MAX
-50
POWER SUPPLY CURRENT
UNITS
CONDITIONS
mA
DATA INPUT LEVELS
Vll
Logical Low Level
VSs-17.9
VSS-4.2
V
VIH
Logical High Level
VSS-1.7
Vss+0.3
V
III
DATA INPUT LEAKAGE
10
/LA
Cdi
DATA INPUT CAPACITANCE
10
pf
V IN = -5V; All other Pins GND
V IN = OV; f = 1MHZ, All other Pins
GND
CLOCK INPUT LEVELS
VOH
Logical High Level
VOL
Logical Low Level
VSS-1.0
VSS+0.3
V
VSS-179
VSS-14.5
V
ICl
CLOCK INPUT LEAKAGE
10
Cci
CLOCK INPUT CAPACITANCE
200
/LA
Vo = -17.9V; All other Pins GND
pf
V 0 = OV; f = 1MHZ, All other Pins
GND
V
I Source = -50mA
V
I Sink = 1.6 mA
DATA OUTPUT LEVELS
VOH
Logical High Level
VOL
Logical Low Level
24
VSs-O.4
650
•
I
TABLE 2 A.C. PARAMETERS
.---
---
-
MIN
PARAMETER
SYMBOL
.-.--MAX
UNITS
CONDITIONS
=
~tf
= 20 ns
0f
CLOCK FREQUENCY
0pw in
CLOCK PULSE WIDTH, In
0pwout
CLOCK PULSE WIDTH, Out
0d
CLOCK PHASE DELAY TIME,
from rising edge
10
ns
~d
CLOCK PHASE DELAY TIME,
from falling edge
10
ns
0tr
CLOCK TRANSITION TIME,
rising edge
1.0
us ~tf + ~pw + 0tr ~ 3.0 uS
0tf
CLOCK TRANSITION TIME,
falling edge
1.0
us
tds
DATA INPUT SET-UP TIME
80
ns
tdh
DATA INPUT HOLD TIME
40
ns
tpdl
DATA OUTPUT PROPAGATION DELAY,
to low level
200
ns
tpdh
DATA OUTPUT PROPAGATION DELAY,
to high level
200
ns
10
2000
0.15
1.0
1
1
KHz 0tr
:e
c
en
(X)
en
uS 0tf + ~pw
VSS-~10V
CLOCK
Vss-14.5V
0 pw
Olr
in
Vss - 1.0V
00UT
CLOCK
DATA OUTPUT
Figure 3 WD5869 TIMING DIAGRAM
•
651
~tr ~ 3.0 uS
~pw in
DATA INPUT/
LOAD INPUT
01N
+
CO
See page 725 for orderi ng information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
()52
Printed
In
USA
WESTERN DIGITAL
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WD74HC200 256
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1 CMOS Static RAM
•
FEATURES
• PIN COMPATIBLE WITH 74LS200
• LOW POWER DISSIPATION .48 MW/BIT TYPICAL
• BATTERY-BACK UP/STANDBY MODE
A1
-1
16
vCC
• COMPLETELY STATIC
AO
2
15
A2
• SINGLE + 5V SUPPLY
• FULLY TTL COMPATIBLE
E1
3
14
A3
E2
4
13
DIN
E3
5
12
WE
DOUT
6
11
A7
A4
7
10
A6
GND
8
9
A5
• 35 ns TYPICAL ACCESS TIME
GENERAL DESCRIPTION
The WD74HC200 256x1 RAM is both pin and speed
compatible to the SN74LS200 and AM27LSOO. The
device is fabricated in CMOS, offering a dramatic
decrease in power dissipation and increased noise
immunity. It is well suited for high-speed buffer
memories in digital systems and bit-slice designs.
The memory is organized as a 256-word by 1-bit width
with an 8 bit binary address field and separate data in
and data output lines. It has 3 active low chip selects
and a three-state output.
The WD74HC200 operates from a single + 5 volt
supply and is available in a dual-in-line plastic or
ceramic pack.age.
PIN DESIGNATION
r r r r
4 TO 16 COLUMN DECODER
r---
~:;
..........
,.."
......
'--:;
.j>.
-t
0
"
......
c;)
:lJ
0
~
16 x 16
MEMORY ARRAY
.....
...,
,...
,..
......
-.
...... DIN
0
"......
m
(')
0
0
m
......
"......
......
"......
r-
:lJ
....
......
r'---
BLOCK DIAGRAM
•
653
PIN
NUMBER
SYMBOL
FUNCTION
PIN NAME
1,2,7,
9-11,14-15
3-5
AO-A7
ADDRESS 0-7
E1-E3
ENABLE 1-3
6
DOUT
DATA OUT
8
12
GND
WE
GROUND
WRITE ENABLE
13
16
DIN
DATA IN
VCC
VCC
8-bit address input used to select one of 256
memory bits.
Three active-low inputs which must be at a logic
zero to perform RIW functions.
Inverted data output from a selected memory
address.
Ground
Active low input used to write data into the
device.
Data Input Line used in conjunction with WE.
+ 5V ± 5% power supply input.
To retain d~ta JD a stand-by or battery back-up
mode, the E1, E2 or E3 line should be held at a
Logic 1, while WE and the address lines are at a
Logic O. At nominal supply voltage, power consumption will be less than 1 milliampere D.C. in
this configuration.
FUNCTIONAL DESCRIPTION
When any of the Enable inputs are high (E1, E2,
or E3) the DOUT (Pin 6) line will remain in a h~
impedance state. During this condition, the WE
(Pin 12) Write line is a "don't care" state and will
not affect the high impedance state of DOUT.
To perform a Write function, an address is placed
on the address lines, with WE and all three
Enable Lines at a Logic O. Data is entered into
the selected memory bit specified by the address
inputs.
A read operation is performed in a similar fashion. Address Lines and the three Enable lines are
made active, while WE is held high. The complement of the selected data bit then appe~rs on
the DOUT (Pin 6) line.
ABSOLUTE MAXIMUM RATINGS
VCC With Respect to Ground ...... - 0.3 to + 7V
Voltage On Any Input With
Respect to Ground ............. - 0.3 to + 7V
Storage Temperature
Ceramic .................. - 65°C to + 150°C
Plastic .................... - 55° to + 125°C
Operating Temperature ........... O°C to + 75°C
Power Dissipation ..................... 125 mW
NOTE: Maximum ratings indicate limits which permanent device damage may occur. Continuous operation at these ratings is not intended and should be
limited to the DC electrical characteristics listed
below.
DC ELECTRICAL CHARACTERISTICS
TA = O°C to 75°C, VCC = 5V + 5%
SYMBOL
VIH
VIL
VOH
VOL
IlL
IIH
ICC
ILK
CHARACTERISTIC
MIN
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Low Current
Input High Current
Power Supply Current
Output Leakage Current
MAX
2.0
0.8
2.4
.45
.8
20
25
30
654
UNIT
V
V
V
V
mA
IJA
mA
IJA
CONDITIONS
IOH = -2.6mA
IOL = 16.0mA
All Outputs Open
Three-state
......................................................................
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (Unless Otherwise Noted)
VCC
= 5V ± 5%; CL = 50pF
PARAMETERS
tPLH(A)
tPHUA)
tPZH(CS)
tpzUCS)
tPHZ(CS)
tpLZ(CS)
trec (WE)
tPZH(WE)
tPZL(WE)
tPHZ(WE)
tPLZ(WE)
ts(A)
th(A)
ts(DI)
th(DI)
tpw(WE)
rrA =
25°C
TYP.
DESCRIPTION
TA =
OOCto
75°C
MIN.
MAX.
UNITS
Delay from Address to Output
See Fig.2
35
15
45
ns
Delay from Chip Select to Active
Output and Correct Data
See Fig.2
15
5
25
ns
Delay from Chip Select to Inactive
Output
See Fig. 2
15
5
25
ns
Delay from Write Enable (HIGH)
to Correct Output Data
See Fig. 1
25
45
ns
Delay from Write Enable (HIGH)
to Active Output
See Fig. 1
Delay from Write Enable (LOW)
to Inactive Output
See Fig. 1
Set-up Time Address
Hold Time Address
Set-up Time Data Input
Hold Time Data Input
Write Enable Pulse Width
See Fig. 1
See Fig. 1
See Fig. 1
See Fig. 1
5
20
0
0
20
0
20
ns
30
0
0
30
0
30
ns
ns
ns
ns
ns
ns
~-
SWITCHING WAVEFORMS
ADDRESS
AO·7
~----.l-tpzUWE)
MAX
Write Cycle Timing. The cycle is initiated by an address change. After ts (A) max, the write enable may begin. The
c:hip select must also be LOW for writing. Following the write pulse, th (A) max must be allowed before the
address may be changed again. The output will be floating while the write enable is LOW. Ordinarily, the chip
select should be LOW during the entire write pulse.
Figure 1
655
:E
c
......
.c:.
ADDRESS
AO-7
--ADDRESS j ---+---·---------ADDRESS k---------Ir--ADDRESS 1 -
::I:
o
N
o
o
---~------~-------------------~--------+---------~---------------
'--v-----'
~--___..~----'
OUTPUT READ A HIGH
DISABLED IN ADDRESS j
READA LOW IN
ADDRESS k
DISABLE
OUTPUT
ENABLE
OUTPUT
READA HIGH
IN ADDRESS I
Switching delays from address and chip select inputs to the data output Disabled output is floating when
"OFF," and represented by a single center line.
Figure 2
See page 725 for ordering information.
This is a preliminary specification with tentative device parameters and may be subject to change after final product characterization is completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
said circuitry at anytime without notice.
656
Printed In U S.A
WESTERN DI'GITAL
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WD8206 Error Detection and Correction Unit
FEATURES
• Detects and Corrects All Single Bit Errors.
• Detects All Double Bit and Most Multiple Bit
Errors
• 52 ns Maximum for Detection; 67 ns Maximum
for Correction (16 Bit System)
• Expandable to Handle 80 Bit Memories
• Syndrome Outputs for Error Logging
• Separate Input and Output Busses - No Timing
Strobes Required
• Supports Reads With and Without Correction,
Writes, Partial (Byte) Writes, and Read-ModifyWrites
• HMOS Technology for Low Power
• 68 Pin Leadless JEDEC Package
• Single + 5V Supply
GENERAL DESCRIPTION
The HMOS 8206 Error Detection and Correction Unit
is a high-speed device that provides error detection
and correction for memory systems (static and
dynamic) requiring high reliability and performance.
Each 8206 handles 8 or 16 data bits and up to 8 check
bits. 8206's can be cascaded to provide correction
and detection for up to 80 bits of data. Other 8206
features include the ability to handle byte writes,
memory initialization, and error logging.
16
01 0-15
STB
----;3~
1I'---,'-2-----,POSO-1,--_ _ _ _--t 1--_ _----1.- ERROR
,...------1
CBI/SYI0-7
16
SYO/CBO/PPOO_7'\r-_~_-I
PPI/POS/NSL
1 - - - -.....
DATA
CORREC
-TION
-+------1'"
16
MIS
GND +5V
11
Vss Vcc
Figure 1. 8206 BLOCK DIAGRAM
657
WZ
BMO-1
CE
DO/WDI0-15
Table 1. PIN DESCRIPTION
PIN
NUMBER
SYMBOL
TYPE
NAME AND FUNCTION
01 0-15
I
CBIISYIO
I
6
7
8
9
10
11
12
51
50
49
48
47
46
45
44
42
41
40
39
38
37
36
35
23
24
25
27
28
29
30
31
13
14
CBIISYI1
CBIISYI2
CBII SYI 3
CBIISYI4
CBIISYI5
CBIISYI6
CBIISYI7
DO/WDIO
DO/WDI1
DO/WDI2
DO/ WDI 3
D0 /WDI 4
DO/WDI5
DO/WDI6
DO/WDI7
DO/WDI8
DO/ WDI 9
DO/WDI 10
DO/WD I11
DO/WDI12
DO/ WDI 13
DO/WD I14
DO/WDI15
SYO/CBO/PPOO
SYO/CBO/PP01
SYO/CBO/PP02
SYO/CBO/PP03
SYO/CBO/PP04
SYO/CBO/PP05
SYO/CBO/PP06
SYO/CBO/PP07
PPIO/POSO
PPI1/POS1
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0
0
0
0
0
0
0
0
I
I
Data In: These inputs accept a 16 bit data word from RAM
for error detection and/or correction.
Chec:k Bits In/Syndrome In: In a single 8206 system, or in
the master in a multi-8206 system, these inputs accept the
check bits (5 to 8) from the RAM. In a single 8206 16 bit
system, CB10-5 are used. In slave 8206's these inputs
accept the syndrome from the master:
15
16
PPI2/NSLQ
PPI3/NSL1
I
I
17
PPI4ICE
I/O
18
19
20
PPI5
PPI6
PPI7
I
I
I
1,68-61,
59-53
5
..
~
-
Data Out/Write Data In: In a read cycle, data accepted by
010-15 appears at these outputs corrected if CRCT is low,
or uncorrected if CRCT is high. The BM inputs must be
high to enable the output buffers during the read cycle. In
a write cycle, data to be written into the RAM is accepted
by these inputs for computing the write check bits. In a
partial-write cycle, the byte not to be modified appears at
either 000-7 if BMO is high, or 008-15 if BM1 is high, for
writing to the RAM. When WZ is active, it causes the 8206
to output all zeroes at 000-15, with the proper write check
bits on CBO.
Syndrome Out/Check Bits Out/Partial Parity Out: In a
single 8206 system, or in the master in a multi-8206
system, the syndrome appears at these outputs during a
read. During a write, the write check bits appear: In slave
8206's the partial parity bits used by the master appear at
these outputs. The syndrome is latched (during readmodify-writes) by R/W going low.
Partial Parity In/Position: In the master in a multi-8206
system, these inputs accept partial parity bits 0 and 1 from
the slaves. In a slave 8206 these inputs inform it of its
position within the system (1 to 4). Not used in a single
8206 system.
Partijal Parity In/Number of Slaves: In the master in a multi8206 system, these inputs accept partial parity bits 2 and 3
from the slaves. In a multi-8206 system these inputs are
used in slave number 1 to tell it the total number of slaves
in the system (1 to 4). Not used in other slaves or in a
single 8206 system.
Partijal Parity In/Correctable Error. In the master in a multi8206 system this pin accepts partial parity bit 4. In slave
number 1 only, or in a single 8206 system, this pin outputs
the correctable error flag. CE is latched by R/W going low.
Not used in other slaves.
Partial Parity In: In the master in a multi-8206 system these
pins accept partial parity bits 5 to 7. The number of partial
parity bits equals the number of check bits. Not used in
single 8206 systems or in slaves.
{i58
•
Table 1. PIN DESCRIPTION (CONTINUED)
[
PIN
NUMBER
TYPE
NAME AND FUNCTION
22
. ERROR
0
52
CRCT
I
2
STB
I
Error: This pin outputs the error flag in a single 8206
system or in the master of a multi-8206 system. It is
latched by R/W going low. Not used in slaves.
Correct: When low this pin causes data correction during a
read or read-modify-write cycle. When high, it causes error
correction to be disabled, although error checking is still
enabled.
Strobe: STB is an input control used to strobe data at the
01 inputs and check-bits at the CBIISYI inputs. The signal
is active high to admit the inputs. The signals are latched
by the high-to-Iow transition of STB.
33
32
BMO
BM1
I
I
21
R/W
I
34
WZ
I
4
MIS
I
3
SEOCU
I
VCC
VSS
VSS
I
I
I
60
26
43
SYMBOL
Byte Marks: When high, the Oata Out pins are enabled for a
read cycle. When low, the Oata Out buffers are tristated for
a write cycle. BMO controls OOO-?, while BM1 controls
008-15. In partial (bytes) writes, the byte mark input is low
for the new byte to be written.
Read/Write: When high this pin causes the 8206 to perform detection and correction (if CRCT is low). When low,
it causes the 8206 to generate check bits. On the high-tolow transition the syndrome is latched internally for readmodify-write cycles.
Write Zero: When low this input overrides the BM0-1 and
R/W inputs to cause the 8206 to output all zeros at 000-15
with the corresponding check bits at CBOO-? Used for
memory initialization.
Master/Slave: Input tells the 8206 whether it is a master
(high) or a slave (low).
Single EDC Unit: Input tells the master whether it is
operating as a single 8206 (low) or as the master in a multi8206 system (high). Not used in slaves.
Power Supply: + 5V
Logic Ground
Output Driver Ground
IFUNCTIONAL DESCRIPTION
The 8206 Error Oetection and Correction Unit provides greater memory system reliability through its
ability to detect and correct memory errors. It is a single chip device that can detect and correct all single
bit errors and detect all double bit and some higher
multiple bit errors. Some other odd multiple bit errors
(e.g., 5 bits in error) are interpreted as single bit
c~rrors, and the CE flag is raised. While some even
multiple bit errors (e.g., 4 bits in error) are interpreted
as no error, most are detected as double' bit errors.
This error handling is a function of the number of
check bits used by the 8206 (see Figure 2) and the
specific Hamming code used. Errors in check bits are
not distinguished from errors in a word.
A single 8206 handles 8 or 16 bits of data, and up to 5
8206's can be cascaded in order to handle data paths
of 80 bits. For a single 8206 8 bit system, the 018-15,
00/W018-15 and BM1 inputs are grounded. See the
Multi-Chip systems section for information on 24-80
bit systems.
The 8206 has a "flow through" architecture. It supports two kinds of error correction architecture: 1)
Flow-through, or correct-always; and 2) Parallel, or
check-only. There are two separate 16-pin busses,
one to accept data from the RAM (01) and the other to
deliver corrected data to the system bus (OO/WOI).
The logic is entirely combinatorial during a read
cycle. This is in contrast to an architecture with only
one bus, with bidirectional bus drivers that must first
read the data and then be turned around to output the
corrected data. The latter architecture typically
requires additional hardware (latches and/or transceivers) and may be slower in a system due to timing
skews of control signals.
659
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o0')
DATA WORD BITS
CHECK BITS
8
16
24
32
40
48
56
64
72
80
5
6
6
7
7
8
8
8
8
8
In a partial write, part of the data word is overwritten,
and part is retained in memory. This is accomplished
by performing a read-modify-write cycle. The complete old word is read into the 8206 and corrected,
with the syndrome internally latched by R/W going
low. Only that part of the word not to be modified is
output onto the DO pins, as controlled by the Byte
Mark inputs. That portion of the word to be overwritten is supplied by the system bus. The 8206 then
calculates check bits for the new word, using the
byte from the previous read and the new byte from
the system bus, and writes them to the memory.
Figure 2: NUMBER OF CHECK BITS
USED BY 8206
READ·MODIFY·WRITE CYCLES
Upon detection of an error the 8206 may be used to
correct the bit in error in memory. This reduces the
probability of getting multiple-bit errors in subsequent read cycles. This correction is handled by
executing read-modify-write cycles.
The read-modify-write cycle is controlled by the R/W
input. After (during) the read cycle, the system
dynamic RAM controller or CPU examines the 8206
ERROR and CE outputs to determine if a correctable
error occurred. If it did, the dynamic RAM controller
or CPU forces R/W low, telling the 8206 to latch the
generated syndrome and drive the corrected check
bits onto the CBO outputs. The corrected data is
available on the DO pins. The DRAM controller then
writes the corrected data and corresponding check
bits into memory.
The 8206 may be used to perform read-modify-writes
in one or two RAM cycles. If it is done in two cycles,
the 8206 latches are used to hold the data and check
bits from the read cycle to be used in the following
write cycle. The WD8207 Advanced Dynamic RAM
controller allows read-modify-write cycles in one
memory cycle. See the System Environment section.
READ CYCLE
With the R/W pin high, data is received from the RAM
outputs into the 01 pins where it is optionally latched
by the STB signal. Check bits are generated from the
data bits and compared to the check bits read from
the RAM into the CBI pins. If an error is detected the
ERROR flag is activated and the correctable error flag
(CE) is used to inform the system whether the error
was correctable or not. With the BM inputs high, the
word appears corrected at the DO pins if the error
was correctable, or unmodified if the error was
uncorrectable.
If more than one 8206 is being used, then the check
bits are read by the master. The slaves generate a
partial parity output (PPO) and pass it to the master.
The master 8206 then generates and returns the
syndrome to the slaves (SYO) for correction of the
data.
The 8206 may alternatively be used in a "check-only"
mode with the CRCT pin left high. With the correction facility turned off, the propagation delay from
memory outputs to 8206 outputs is significantly
shortened. In this mode the 8206 issues an ERROR
flag to the CPU, which can then perform one of several options: lengthen the current cycle for correction, restart the instruction, perform a diagnostic
routine, etc.
A syndrome word, five to eight bits in length and
containing all necessary information about the existence and location of an error, is made available to
the system at the SY00-7 pins. Error logging may be
accomplished by latching the syndrome and the
memory address of the word in error.
INITIALIZATION
A memory system operating with ECC requires some
form of initialization at system power-up in order to
set valid data and check bit information in memory.
The 8206 supports memory initialization by the write
zero function. By activating the WZ pin, the 8206 will
write a data pattern of zeros and the associated
check bits in the current write cycle. By thus writing
to all memory at power-up, a controller can set
memory to valid data and check bits. Massive
memory failure, as signified by both data and check
bits all ones or zeros, will be detected as an uncorrectable error.
WRITE CYCLE
For a full write, in which an entire word is written to
memory, the data is written directly to the RAM,
bypassing the 8206. The same data enters the 8206
through the WDt pins where check bits are generated. The Byte Mark inputs must be low to tristate the
DO drivers. The check bits, 5 to 8 in number, are then
written to the RAM through the CBO pins for storage
along with the data word. In a multi-chip system, the
master writes the check bits using partial parity
information from the slaves.
MULTI·CHIP SYSTEMS
A single 8206 handles 8 or 16 bits of data and 5 or 6
check bits, respectively. Up to 5 8206's can be
cascaded for 80 bit memories with 8 check bits.
When cascaded, one 8206 operates as a master, and
all others as slaves. As an example, during a read
cycle in a 32 bit system with one master and one
'660
externally. Figure 3 shows the necessary external
logic for multi-chip systems. Write and read-modifywrite cycles are carried out analogously. See the
System Operation section for multi-chip wiring
diagrams.
There are several pins used to define whether the
8206 will operate as a master or a slave. Tables 2 and
3 illustrate how these pins are tied.
slave, the slave calculates parity on its portion of the
word - "partial parity" - and presents it to the
master through the PPO pins. The master combines
the partial parity from the slave with the parity it
calculated from its own portion of the word to
generate the syndrome. The syndrome is then
returned by the master to the slave for error
correction. In systems with more than one slave the
above description continues to apply, except that the
partial parity outputs of the slaves must ~e XOR'd
3a. 48 BIT SYSTEM
SLAVE 2
PPO
8
3b. 64 BIT SYSTEM
SLAVE 3
PPO
MASTER
PPI
8
3c. 80 BIT SYSTEM
L
IMASTER
PPI
SLAVE 3
PPO
8
SLAVE 4
PPO
8
Figure 3. EXTERNAL LOGIC FOR MULTI·CHIP SYSTEMS
........................................................................
661
Table 2. MASTER/SLAVE PIN ASSIGNMENTS
PIN NO.
PIN NAME
MASTER
SLAVE 1
SLAVE 2
SLAVE 3
SLAVE 4
4
3
13
14
15
16
MIS
SEDCU
PPIO/POSO
PPI1/POS1
PPI2/NSLO
PPI3/NSL1
+5V
+5V
PPI
PPI
PPI
PPI
Gnd
+5V
Gnd
Gnd
*
*
Gnd
+5V
+5V
Gnd
+5V
+5V
Gnd
+5V
Gnd
+5V
+5V
+5V
Gnd
+5V
+5V
+5V
+5V
+5V
* See Table 3.
NOTE:
Pins 13,14,15,16 have internal pull-up resistors and may be left as N.C. where specified as connecting to + 5V.
Table 3. NSL PIN ASSIGNMENTS FOR SLAVE 1
NUMBEFl OF SLAVES
PIN
1
PPI2/NSLO
PPI3/NSL1
Gnd
Gnd
~+~v
Gnd
3
4
Gnd
+5V
+5V
+5V
I
The timing specifications for multi-chip systems
must be calculated to take account of the external
XOR gating in 3, 4, and 5-chip systems. Let tXOR be
the delay for a single external TTL XOR gate. Then
the following equations show how to calculate the
relevant timing parameters for 2-chip (n = 0), 3-chip
(n
1), 4-chip (n
2), and 5-chip (n
2) systems:
Data-in to corrected data-out (read cycle) =
TDVSV + TPVSV + TSVaV + ntXOR
Data-in to error flag (read cycle) =
TDVSV + TPVEV + ntXOR
Data-in to correctable error flag (read cycle) =
TDVSV + TPVSV + TSVCV + ntXOR
Write data to check-bits valid (full write cycle) =
TaVaV + TPVSV + ntXOR
Data-in to check-bits valid (read-mod-write cycle) =
TDVSV + TPVSV + TSVaV + TaVaV +
TPVSV + 2ntXOR
Data-in to check-bits valid (non-correcting readmodify-write cycle) =
TDVaU + TaVaV + TPVSV -I- ntXOR
=
=
through logic levels than any other one, and hence no
one device becomes a bottleneck in the parity
operation. However, one or two levels of external TTL
XOR gates are required in systems with three to five
chips. The code appears in Table 4. The check bits
are derived from the table by XORing or XNORing
together the bits indicated by "X's in each row
corresponding to a check bit. For example, check bit
o in the MASTER for data word 1000110101101011
will be "0." It should be noted that the 8206 will
detect the gross-error condition of all lows or all
highs.
=
Error correction is accomplished by identifying the
bad bit and inverting it. Table 4 can also be used as an
error syndrome table by replacing the "X's with '1's.
Each column then represents a different syndrome
word, and by locating the column corresponding to a
particular syndrome the bit to be corrected may be
identified. If the syndrome cannot be located then
the error cannot be corrected. For example, if the
syndrome word is 00110111, the bit to be corrected is
bit 5 in the slave one data word (bit 21).
The syndrome decoding is also summarized in Table
5, which can be used for error logging. By finding the
appropriate syndrome word (starting with bit zero, the
least significant bit), the result is either: 1) no error; 2)
an identified (correctable) single bit error; 3) a double
bit error; or 4) a multi-bit uncorrectable error.
HAMMING CODE
The 8206 uses a modified Hamming code which was
optimized for multi-chip EDCU systems. The code is
such that partial parity is computed by all 8206's in
parallel. No 8206 requires more time for propagation
662
Table 4. MODIFIED HAMMING CODE CHECK BIT GENERATION
Check bits are generated by XOR'ing (except for the CBa and CB1 data bits, which are XNOR'ed in the Master)
the data bits in the rows corresponding to the check bits. Note there are 6 check bits in a 1&bit system, 7 in a
32-bit system, and 8 in 48-or-more-bit systems.
BYTE NUMBER
1
0
OPERATION
BIT NUMBER o 1 2 3 4 567 o 1 234 5 6 7
XNOR
CBa = XX-X-XX- X--X-X-XNOR
CB1 = X-X--X-X -X-XX-XXOR
CHECKCB2 = ~XX-X-XX --X-X--X
XOR
CB3 = XXXXX--- XXX----XOR
BITS CB4 = ,..---XXXXX -----XXX
XOR
CB5 = ' - - - - - - - - XXXXXXXX
XOR
CB6 = r - - - - - - - - - - - - - - - XOR
CB7 = - - - - - - - - - - - - - - - a a 0 a a a a 1 1 1 1 1 1
DATA BITS aa a1 a234
567 8 9 a 1 234 5
16 BIT OR MASTER
I
I
2
3
o 1 2 3 4 567 o 1 2 3 4 5 6 7 OPERATION
XOR
XOR
XOR
XOR
XOR
XOR
XOR
XOR
-XXX-XX- -XX--X-XXX--X-X XX-----X
-XXX-XXX --XX---XX--X-XX X--XX--XX--XXXX ----X-X---XXXXX -----XXX
-------- XXXXXXXX
----------------
I
1 1 1 1 222 2 2 2 2 2 2 233
6 7 8 9 a 1 2 3 4 5 6 789 a 1
SLAVE #1
I
0>
0>
(,)
4
BYTE NUMBER
5
7
8
6
9
OPERATION
BIT NUMBER o 1 2 3 4 5 6 7 o 1 2 3 4 5 6 7 o 1 234 5 6 7 o 1 2 345 6 7 o 1 2 3 4 5 6 7 o 1 234 5 6 7
CBa = XX-X-XX- X--X-X-- X-X-XX-- X-XX--X- -XXX-XX- -XX--X-XOR
CB1 = X-X--X-X -X-XX-X- -XX---XX X X X - - - X -1- X X X - X X X --x X----' XOR
CHECKCB2 = -XX-X-XX --X-X--X -XXX-XX- -x X--X--IX--X-X X- -XX--X-X
XOR
CB3 = XXXXX--- XXX----- X-X--XX- x x -- x x
x x x x -- x XX--X--- XOR
BITS CB4;:: ---XXXXX -----XXX ---XXXXX -----XXX-XX---XX XXX---XXOR
CB5 = XXXXXXXX - - - - - - - - - - - - - - - - XXXXXXXX X-XXXX-X ---X---X
XOR
CB6 = XXXXXXXX - - - - - - - - XXXXXXXX -------- XX--XXXX ----X-XXOR
CB7 = -------- XXXXXXXX -------- XXXXXXXX - - - - - - - - XXXXXXXX
XOR
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
666
6
6
6
6
6
6
7
7
7
7
777
7
7
7
DATA BITS 2 3 4 5 6 7 8 9 a 1 2 3 4 5 6 7 8 9 a 1 234 5 6 7 8 9 a 1 2 3 456 7 8 9 a 1 2 3 4 5 6 7 8 9
--1-
I
SLAVE #2
II
SLAVE #3
II
SLAVE #4
I
90~8aM
TableS. SYNDROME DECODING
o0
7
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
N
CBX
X
D
U
Syndrome
Bits
S
6
0
0
0
0
1
0
1
0
1
0
1
0
1
1
1
1
0
0
0
0
1
0
1
0
1
0
0
1
1
1
1
1
1
1
0
0
D
5
11
D
25
D
D
37
43
D
D
62
D
U
U
D
1
0
1 0
0
1
2 0
0
0
0
3 0
0
N
CBO CB1
CB4
D
D
CB5
D
D
14
13
D
CB6
D
D
D
55
52
D
31
29
D
D
30
CB7
D
D
D
45
46
D
75
59
D
63
D
D
U
U
D
D
78
D
U
D
U
D
U
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
1
0
CB2
D
D
15
D
51
64
D
D
47
79
D
U
D
D
U
0
1
1
0
D
7
12
D
49
D
D
39
44
D
D
U
D
U
U
D
0
1
0
D
£i
19
D
26
[)
D
38
n
D
D
U
D
U
U
D
= No Error
= Error in Check Bit X
=
= Uncorrectable Multi-Bit Error
32 BIT
DATA
BUS
DATA MEMORY
16 BITS
~
x
C
v
R
DO
DI
A
...
CB3
D
D
20
D
28
68
D
D
72
60
D
76
D
D
U
1
0
0
1
D
3
8
D
48
D
D
35
40
D
D
U
D
U
U
D
0
1
0
1
D
16
9
D
24
D
D
71
41
D
D
U
D
U
U
D
1
1
0
1
0
D
D
66
D
65
32
D
D
U
56
D
U
D
D
U
0
0
1
1
D
4
10
D
27
D
D
1
0
1
1
1
D
D
22
D
53
33
D
D
73
U
D
U
D
D
U
36
42
D
D
61
D
U
U
D
0
1
1
1
2
D
D
23
D
54
34
D
D
U
57
D
U
D
D
U
1
1
1
1
D
17
67
D
50
D
D
U
U
D
D
U
D
U
U
D
SYSTEM ENVIRONMENT
Error in Data Bit X
~
0
0
0
1
The 8206 i nteriace to a typical 32 bit memory system
is illustrated in Figure 4. For larger systems, the
partial parity bits from slaves two to four must be
XOR'ed externally, which calls for one level of XOR
gating for three 8206's and two levels for four or five
8206's.
= Double Bit Error
OE
1
1
1
0
18
D
D
21
D
70
69
D
D
74
58
D
U
D
D
U
CHECK]
DATA MEMORY
16 BITS
BITS
7 BITS
DI
DO
DI
DO
,..
<~
~
I---
..-.--
I---
1
I-I--
"--
T
• p
DO/WDI
~
I.
!.
DI
11
)-
SYOI CB1O-13
CBO
SYIO-6
...
PPIO-6
PPOO-6
'Y
PPI7
CBI7
CRCT
CO NTROL {
L INES
wz
STB
R/W
8206
MASTER
MIS
SEDCU
Pv
BYTE {
,..---...
II
ERROR
MARKS
CRCT
Ir--+ wz
~ STB
~o+v l.--+
BMO
BM1
8206
SLAVE
DI
pOSo
POS1
NSLO
NSL1
R/W
MIS
BMO
BM1
PP15-7
SEDCU
SYI7
ERROR
S IGNALS
Figure 4. 32·BIT 8206 SYSTEM INTERFACE
664
:,
P
DO/WDI
CE
I
~~
,+
14-
1-4'
9-
0 + 5V
•
The 8206 is designed for direct connection to the
WD8207 Advanced Dynamic RAM Controller, due to
be sampled in the first quarter of 1983. The 8207 has
the ability to perform dual port memory control and
Figure 5 illustrates a highly integrated dual port RAM
implementation using the 8206 and 8207. The
8206/8207 combination permits such features as
1
ACKB
..
...
.
CMD/PEB
ADDRB
CMD/PEA
-
--
ACKB
ADDR
RAS
CAS
...
CMDI
WE
-{>o-o
PEB 8207
MUX ADRC
wz
CMDI
PEA
ClK>-+ ClK
MUX
-
..
r--t'
automatic scrubbing (correcting errors in memory
during refresh), extending RAS and CAS timings for
Read-Modify-Writes in single memory cycles, and
automatic memory initialization upon reset. Together
these two chips provide a complete dual-port, errorcorrected dynamic RAM subsystem.
ADDR
ACKA
PSEN
CE
ERROR
DBM
R/W
PSEl
DYNAMIC
RAM
32 BITS +
7CHECKBITS
y
WE
DI
.~
,..
DOl
CBO
I-
r-
L
L
h
I
l-
II-
.--
~
L J.
~.
ERROR
DI/CBI
R/W SYOI
CBO PPI
+5V- STB
ADDRA
ACKA
CBI
BM
wz
DO/WDI
~
II~
BYTE
MARK
DECODER
wz
~
v--n ...
I
~
PORTA
11
.11
L.....--
.
~
XCVR
'&
_ISTB OEI
IlATCH
-RD
PORTB
Figure 5. DUAL PORT RAM SUBSYSTEM WITH 8206/8207 (32-BIT BUS)
665
BM
DO/WDI
Q
II
----
STB
CRCT 8206
SLAVE
Q
~~~
DI
R/W
PPO
..
CRCT 8206
MASTER
~
SVI
I
4
,
r-+ 5V
MEMORY BOARD TESTING
The 8206 lends itself to straightforward memory
board testing with a minimum of hardware overhead.
The following is a description of four common test
modes and their implementation.
Mode a - Read and write with error correction.
Implementation: This mode is the normal
8206 operating mode.
Mode 1 - Read and write data with error correction
disabled to allow test of data memory.
Implementation: This mode is performed
with CRCT deactivated.
Mode 2 - Read and write check bits with error cor·
rection disabled to allow test of check bits
memory.
Implementation: Any pattern may be writ·
ten into the check bits memory by judi·
ciously choosing the proper data word to
generate the desired check bits, through
the use of the 8206 Hamming code. To
read out the check bits it is first necessary
to fill the data memory with all zeros,
which may be done by activating WZ and
incrementing memory addresses with WE
to the check bits memory held inactive,
and then performing ordinary reads. The
check bits will then appear directly at the
SYO outputs, with bits CBa and CB1
inverted.
Mode 3 - Write data, without altering or writing
check bits, to allow the storage of bit
combinations to cause error correction
and detection.
Implementation: This mode is imple·
mented by writing the desired word to
memory with WE to the check bits array
held inactive.
PACKAGE
The 8206 is packaged in a 68·pin, leadless JEDEC
type A hermetic chip carrier. Figure 6 illustrates the
package, and Figure 7 is the pinout.
.066
(1.68)
.050
(1.27)
rl~
L
.800
(20.32)
I
.960
(24.38)
(~~~Il
~PIN NO.18
.130
(3.30)
.960 _ _ _ _ _ ~
(24.38)
Figure 6. 8206 JEDEC TYPE A PACKAGE
666
~-
10
co
TOP
I'-
0
0
0
0
0
0
0
0
0
0
0
0
~
~
~
~
u) 0
~ ~I
~
'J
WZ
BMO
BM1
15
Dig
VSS
VCC
01 8
SY02[
SYOO
ERROR
R/W
PPI7[
PPI5
'
01
:::E
0 u) 0
.9
I'-
0
a.
~
0
w
u)
BOTTOM
0
I'-
0
0
0
u) 0
0
0
I~
0
0
~
~
0
0
~
co
0
0
~
~
I
WZ
BMO
BM1
CRCT
T
011T
V0
7
Dig
SY03
VCC
VSS
SY0
J
DiS
2
SYOO
ERROR
R/W
PPI
]
01 1
oo cot; 1=>1u)
g~
W
U)
I L
I'-
0
co
o
co
0
.9
a.
a.
Figure 7. 8206 PINOUT DIAGRAM
667
I
'(
0.45
-
o.? p6~~:::s
2.0
< 0.•
x=
A.C. TESTING INPUTS ARE DRIVEN AT 2.4V FOR A
LOGIC 1 and 0.45V FOR A LOGIC O. TIMING MEASURE·
MENTS ARE MADE AT 2.0V FOR A LOGIC 1 AND O.BV
FOR A LOGIC O.
A.C. TESTING LOAD CIRCUIT
DEVICE
UNDER
TEST
CL INCLUDES JIG CAPACITANCE
668
A.C. CHARACTERISTICS (TA
nsec.)
= O°C to 70°C, VCC = +5V
± 10%, VSS
8206
~
SYMBOL
TRHEV
TRHCV
TRHQV
TRVSV
TDVEV
TDVCV
TDVQV
TDVSV
TBHQV
TDXQX
TBLQZ
TSHIV
TIVSL
TSLIX
TPVEV
TPVQV
TPVSV
TSVQV
TSVCV
TQVQV
TRHSX
TRLSX
TQXQX
TSVRL
TDVRL.
TDVQU
TTVQV
TWLQL
TWHQX
PARAMETER
ERROR Valid from R/Wt
CE Valid from R/Wt (Single 8206)
Corrected Data Valid from R/Wt
SYO/CBO/PPO Valid from R/W
ERROR Valid from Data/Check Bits In
CE Valid from Data/Check Bits In
Corrected Data Valid from
Data/Check Bits In
SYO/PPO Valid from Data/Check Bits In
Corrected Data Access Time
Hold Time from Data/Check Bits In
Corrected Data Float Delay
STB High to Data/Check Bits in Valid
Data/Check Bits In to STBi- Set-up
Data/Check Bits In from STBi- Hold
ERROR Valid from Partial Parity In
Corrected Data (Master) from Partial
Parity In
Syndrome/Check Bits Out from
Partial Parity In
Corrected Data (Slave) Valid from
Syndrome
CE Valid from Syndrome (Slave
number 1)
Check Bits/Partial Parity Out from
Write Data In
Check Bits/Partial Parity Out from
R/W, WZ Hold
Syndrome Out from R/W Hold
Hold Time from Write Data In
Syndrome Out to R/Wi- Set-up
Data/Check Bits In to R/W Set-up
Uncorrected Data Out from Data In
Corrected Data Out from CRCn
WZi- to Zero Out
Zero Out from WZt Hold
MIN.
MAX.
25
44
54
42
52
70
67
= OV, CL = 100pF; all times are in
8206-8 ------MIN.
MAX.
34
59
66
56
28
90
74
43
0
0
40
5
30
38
1
1
2
30
61
40
76
1
43
51
1
51
69
48
65
64
80
0
0
0
0
17
39
0
0
22
46
32
30
30
0
1
1
70
94
55
37
0
0
30
5
25
NOTES
1
1
1
1
43
40
40
0
NOTES:
1. A.C. Test Levels for CBO and DO are 2.4V and 0.8V.
2. TSHIV is required to guarantee output delay timings: TDVEV, TDVCV, TDVSV. TSHIV + TIVSL guarantees
a min STB pulse width of 35 ns (45 ns for the 8206-8).
•
669
WAVEFORMS
:ec
00
I\)
C
en
READ - 16 BIT ONLY
Ni
STBA
....
I.HIJ~I~.-------TIVSL
~
_I
TSHIV~
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,
,I
>0----1
LV$
Enable
I
3-state
InpuUOutput Inverting Buffer
Quantity: 16
Input Options:
Pull-up Resistor
Pull-down Resistor
Output Options:
Totem-Pole
Open Collector
Three-state*
>--[>
Vss
I
y
~
~'I-
open col
push/pull
....
--.
I
}-
I
Vcc~
*
ENABLE
0
0
1
1
Figure 3
6f12
IN
0
1
0
1
OUT
HI-Z
HI-Z
1
0
outpuU
input
INTERNAL LOGIC ELEMENTS
1)
The Internal Logic Elements consist of the following:
2)
Table 2
QTY
37
38
19
4
12
10
10
Gates that are unused do not draw any power (except
for leakage currents).
All of the above gates may be "Wire-Or'ed" to produce
ANO·OR·INVERT gates, N·input NOR gates, or
complex boolean functions.
FLIP/FLOPS
Inverters
2·lnput NOR gates
2·lnput NAND gates
2·lnput XOR gates
D type Flip-Flops
JK type Flip-Flops
Non·lnvertlng Drivers
Both the '0' and 'JK' types have edge-triggered inputs with
programmable low·te-high or high·te-Iow transition trig·
gering. The 'JK' types may be programmed to perform as
'0' types, providing the user with 22 '0' type Flip/Flops. In·
dependent SET, RESET, Q, and Q signals are available on
each type.
GATES
NON·INVERTING DRIVERS
Inverters, NOR, NAND, and XOR gates comprise the Ran·
dom Logic elements. The outputs of these gates are con·
Ten Non·lnverting Drivers provide high·fanout capability for
nected to a "load device" which applies power to the gate
internal logic. These drivers may be used for common
CLOCK or SET/RESET lines on heavily loaded nodes of
and performs the logic inversion. This method achieves
two key features:
other logic elements.
Random Logic Elements
[>-
Inverting Buffer
Quantity: 37
[>-
2·lnput NOR GATE
Quantity: 38
=DlD---
2·lnput XOR GATE
Quantity: 4
Non·lnverting Driver
Quantity: 10
C>
o Flip/Flop
Quantity: 12
Options: Positive Edge-triggered
Negative Edge-triggered
S
--SET
-0
--0
-
CK
CK
Q-
-Q ..--
,
R
~RESET
JK Flip/Flop
Quantity: 10
Options: Positive Edge-triggered
Negative Edge-triggered
Can be '0' programmed
.....
00
N
o
LOGIC ELEMENT
2·lnput NAND GATE
Quantity: 19
:ec
Q
--
Q
Q
-...
Q
S
~
-..
-..
683
~
R
•
:ec
.....
co
N
o
ABSOLUTE MAXIMUM RATINGS
Operating Temperature ................ O°C to + 70°C
Voltage on any pin with
respect to Vss .................... - 0.5V to + 7.0V
Storage Temperature ........ - 55°C to + 125°C plastic
- 65°C to + 150°C ceramic
DC ELECTRICAL CHARACTERISTICS TA
NOTE: Maximum ratings indicate limits beyond which permanent device damage may occur. Continuous operation
at these ratings is not intended and should be limited to the
DC electrical characteristics.
= O°Cto +70°C,Vcc = +5V ±
10%,Vss
= OV
Maximum Power Ratings ..................... 1.0 watt
Tabla 3
SYMBOL
PARAMETER
MIN
VIH
High Level Input Voltage
2.2V
VIL
Low Level Input Voltage
-0.5
IIH
TYP
MAX
UNIT
CONDITIONS
V
.8
V
High Level Input Current
20
ua
No resistor
IlL
Low Level Input Current
-200
ua
No resistor
CL
Input Capacitance
10
pf
PR
Programmable Resistor
3.3
10
KQ
VOH
Output High Voltage
2A
VOL
Output Low Voltage
Po
IL
6.5
V
.4
V
Power Dissipation
Input Buffer
Logic Gate
Driver
I/O Buffer
o Flip/Flop
JK Flip/Flop
6.5
3.2
10.0
30.0
17.6
17.6
mw
mw
mw
mw
mw
mw
Output Leakage
10
ua
()84
= -200ua
IOL = 4.0ma
IOH
50% duty cycle
50% duty cycle
liMING CHARACTERISTICS
TA
= O°Cto + 70°C, Vee +5V ±
10%, Vss
= OV
Table 4
PARAMETER
MIN
Logic Gate Delay (NOR, NAND, Inverter)
Delay to Low Level (tPHL)
Delay to High Level (tPLH)
Input Buffer Propagation Delay
Delay to Low Level (tpHq
Delay to High Level (tPLJ-1)
Output Buffer Propagation Delay
Delay to Low Level (tPHL)
CONDITIONS
18 ns
21 ns
Figure 7
Figure 7
6ns
19_5 ns
Figure 7
Figure 7
45 ns
Delay to High Level (tPLH)
Output Enable Time to High Level (tPZH)
40 ns
65ns
Output Enable Time to Low Level (tpZL)
Output Disable Time from Low Level (tpLZ)
65 ns
50 ns
Output Disable Time from High Level (tPHZ)
60ns
C L = 75pf
Figure 7
Figure 7
C L = 75pf
Figure9
Figure 9
C L = 5pf
Figure 9
Figure 9
55 ns
50 ns
45 ns
Figure 7
Figure 7
Figure 7
65 ns
60 ns
55 ns
Figure 7
Figure 7
Figure 7
Flip-Flop, Positive Going Edge
TypeD
Delay to High Level (tPLH)
Delay to Low Level (tPH L)
Set, Reset Propagation Delay
Type JK
Delay to High Level (tPLH)
Delay to Low Level (tPHL)
Set, Reset Propagation Delay
Type Dand JK
Data Set-Up Time (ts)
Data Hold Time (th)
CLK, Set, Reset Pulse Width (tw)
l
MAX
30ns
5 ns
100ns
Flip-Flop, Negative Going Edge
TypeD
Delay to High Level (tPLH)
Delay to Low Level (tPH L)
Set, Reset Propagation Delay
TypeJK
Delay to High Level (tPLH)
Delay to Low Level (tPH L)
Set, Reset Propagation Delay
Type D and JK
Data Set-up Time (ts)
Data Hold Time (th)
CLK, Set, Reset Pulse Width (tw)
30 ns
5 ns
100 ns
685
Figure 6
Figure 6
Figure 8
55 ns
60ns
45 ns
Figure 7
Figure 7
Figure 7
65 ns
70ns
55 ns
Figure 7
Figure 7
Figure 7
Figure 6
Figure 6
Figure 8
Parameter Measurement Information
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Load Circuit
INPUT
~8V-----~
/2.0V
!~PLI~ I
IN-PHASE I
OUTPUT:
~PH~ I
I----VOH
VOL
I
/2.0V
tPHL~:
OUT-OF-PHASE "J
OUTPUT
UNDER
:
.~
°
I 'O.8V
I~
tPLH
I
~---VOH
~.OV
8V
~"-: _ _
OUTPUT
--1L"__ VOL
TEST
Figure 7
5KQ
VOLTAGE WAVEFORMS
PULSE WIDTHS
SWITCH POSITIONS
SYMBOL
SW1
SW2
tPZH
OPEN
CLOSED
tpZL
CLOSED
OPEN
tPL2
CLOSED CLOSED
tPHZ
CLOSED CLOSED
HIGH-LEVEL'/'
\.....(
./I2.0V
7\.0.8V
PULSE
';"""';"'-""";;;;"""---' 14-- tw------..t ' - - - - - -
*--tw-+l
--------
LOW-LEVEL
PULSE
FigureS
O.~
~.OV
Figure 8
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, THREE-STATE OUTPUTS
OUTPUT·
CONTROL
TIMING
......:.:.IN~P...:U:..:.T_ _ _ _
(hig~:!e~~1 . /
e~ 2.0V
I4--tpZL~
/,
---I4 ~O!
~A;UAT
~
'O.8V-----.
2.0V
I
j\O.8V
_1_ -
WAVEFORM l'
-:::::o4.5V I
I
52 closed
,S1 closed,
O.8V
lr--t--:::::01.5V
!52 open
I
r--+-·'-~\5.iv--f-VOL
r--tpZHtPHZ~ t O.5V
S1open,
I
~::;:-~"-~VO~15V
WAVEFORM 2 S2 closed
2.0V
_.
~- .
- - - - - :::::0 OV
S2 closed
- - __ - OV
t5etup ~ thold
----.:.:....:..:....::....:... _ _-J.
\.
~ t'-PLZ-..-----"S-1-an""'d-
OV
!
Figure 9
Figure 6
See page 725 for ordering information.
H86
Pronted 'n U S.A
WESTERN DIGITAL
c
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WD1840 Logic Array Device
FEATURES
• SINGLE +5V SUPPLY
• REPLACES 74LSXX LOGIC
• MASK PROGRAMMABLE
• 35 PROGRAMMABLE THREE-STATE OPEN
COLLECTOR, OR TOTEM POLE OUTPUTS
• OVER 400 LOGIC ELEMENTS
• 2 ON-CHIP MULTIVIBRATORS
• ON CHIP PLA FOR STATE MACHINE
IMPLEMENTATION
• TTL COMPATIBLE
• QUICK TURNAROUND
• AVAILABLE IN EITHER 40 OR 28 PIN DUAL-IN
LINE PACKAGE
Zo
40
VCC
Z1
39
Z32
38
Z31
37
Z30
Z3
36
Z29
Z4
35
Z28
10
3
Z2
Z5
34
Z27
Z6
gEl'
Z26
8
33
Z8
10
31
Z24
Z9
11
30
Z23
Z10
12
29
Z22
Z11'
13
28
Z21
Z12
14
27
Z20
Z13
15
26
Z19
Z14
16
25
12
Z15
17
24
Z18
11
18
23
Z17
Z33 /RC '1
19
22
Z16
VSS
20
21
Z34 /RC 2
Z7
WD1840
DEVICE DESCRIPTION
The WD1840 Logic Array Device contains over 400
uncommitted logic elements that can be interconnected to replace a large amount of discrete MSI
logic functions. It is an addition to the WD1820
family, offering the designer extended 1/0 capability
and more logic elements. The device also contains
dual monostable multivibrators and a general purpose PLA configured as a state machine.
Unlike a cell matrix or gate array, this mask
programmable device contains prefabricated logic
elements such as NAND, NOR, XOR, and Invertor
gates, plus '0' and 'JK' or 'JK' Flip/Flops. Gates and
Flip/Flops are interconnected using a special coding
sheet, which is easily prepared from the user's
schematic. This coding sheet is then digitized at the
factory to produce a two-level mask. The mask is
then applied to a prefabricated wafer, producing
qualified samples typically 6 weeks after receipt of
the coding form.
The WD1840 is implemented in N-channel silicon
gate technology operating from a single + 5V power
supply. It is available in either plastic or ceramic DIP.
TABLE 1
PIN
NUMBER
SYMBOL
DESCRIPTION
1,2,4-17, ZQ-Z32
Programmable I/O pins
22-24,
with 3-state, open
26-39
collector, or push pull
capability.
3,18,25
Input only pins.
10-12
19 and 21 Z331RC1
Programmable I/O pins
which at So can function
Z34fRC2
as the external RC inputs
for one-shot operations.
20
Ground
VSS
40
+ 5V ± 10% power
VCC
supply input.
Z25
LOGIC ELEMENTS
The WD1840 contains thirty-five input/output buffers
and three input only buffers. The I/O buffers are high
current inverting drivers and receivers used to interface an external pin to the internal logic elements.
These 35 pins may be programmed for either threestate, totem pole, or open collector operation. When
programmed for three-state operation an active high
PIN DESIGNATION
687
enable signal may be controlled by internal logic, or
externally by connecting to an adjacent input pin.
The three inverting input only buffers are used to
interface directly to TTL logic. All 38 inputs/outputs
have programmable pull-up, pull-down, or no resistor
options.
Two input-output pins can be programmed as the RC
input for selected one-shot control.
GATES
Inverters, NOR, NAND, and XOR gates comprise the
Random Logic elements. The outputs of these gates
are connected to a "load device" which applies
power to the gate and performs the logic inversion.
This method achieves two key features:
1) Gates that are unused do not draw any power
(except for leakage currents).
2) All of the above gates may be "Wire-Or'ed" to
produce AND-OR-INVERT gates, N-input NOR
gates, or complex boolean functions.
INTERNAL LOGIC ELEMENTS
The Internal Logic Elements consist of the followjng:
FLIP/FLOPS
Both the '0' and 'JK' types have edge-triggered clock
inputs with programmable low-to-high or high-to-Iow
transition triggering. The 'JK' types may l2..e programmed to perform as '0' types..Qr as 'JK.' Independent SET, RESET, 0, and 0 signals are
available on each type.
TABLE 2
QTY
LOGIC ELEMENT
112
112
Inverters
2-lnput NOR gates
2-lnput NAND gates
2-lnput XOR gates
o type Flip-Flops
JK type Flip-Flops
Non-Inverting Drivers
24x24x16 PLA
88
22
62
5
17
1
NON-INVERTING DRIVERS
Seventeen Non-Inverting Drivers provide high-fanout
capability for internal logic. These drivers may be
used for common CLOCK or SET/RESET lines on
heavily loaded nodes of other logic elements.
33
Zo
Z1
1
N
P
10
12
U
1
N
11
T
P
U
T
0
N
L
0
Y
B
U
U
T
P
F
F
E
U
T
R
----~
Z33 /RC 1
B
U
F
F
E
Z34 /RC 2
R
S
Z30
Figure 2
WD1840 BLOCK DIAGRAM
E88
•
INTERFACE ELEMENTS
Input Inverting Buffer
Quantity: 3
Options: Pull-up Resistor
Pull-down Resistor
(6.5KQ Typical)
Input/Output Inverting Buffer
Quantity: 35
Input Options:
Pull-up Resistor
Pull-down Resistor
Output Options:
Totem-Pole
Open Collector
Three-state*
Input
r
VGG
~o----4
~VSS
Enable - - - - - - - - - . . . ,
vss~
~.-----"
vcc~
GENERA~PURPOSEPLA
The general-purpose PLA consists of two internally
connected gate matrices. The upper "AND" matrix is
a 24x24 array with synchronizing flip/flop inputs. The
lower "OR" matrix is a 24x16 array with internal state
counter. In addition, a 2 phase clock generator has
been included to generate appropriate clocks to keep
synchronism between the two matrices.
Twenty-four sub-term outputs (SO, S2, ... S23) are
available for further interconnect throughout the
WD1840. Sixteen independent term outputs (00 015) can be user defined to create any type of control
signal desired.
To program the PLA, the user simply "circles" a
cross point in the matrix to enable that transistor.
RANDOM LOGIC ELEMENTS
Inverting Buffer
Quantity: 112
2-lnput NOR GATE
Quantity: 112
2-lnput NAND GATE
Quantity: 88
2-lnput XOR GATE
Quantity: 22
Non-Inverting Driver
Quantity: 17
ABSOLUTE MAXIMUM RATINGS
Operating Temperature ........... O°C to + 70°C
Voltage on any pin with
respect to VSS. . . . . . . . . . . . . .. - 0.5V to + 7.0V
Storage Temperature
Ceramic .................. - 65°C to + 150°C
Plastic .................... - 55°C to + 125°C
Maximum Power Dissipation . . . .. 1.5 watt ceramic;
1.0 watt plastic
D Flip/Flop
Quantity: 63
Options: Positive Edge-triggered
Negative Edge-triggered
DC ELECTRICAL CHARACTERISTICS
TA = O°Cto + 70°C, VCC = +5V ± 10%, VSS = OV
JK Flip/Flop
Quantity: 5
Options: Positive Edge-triggered
Negative Edge-triggered
Can be 'D' programmed
Can be 'JK' programmed
NOTE:
Maximum ratings indicate limits beyond which permanent
device damage may occur. Continuous operation at these
ratings is not intended and should be limited to the DC
electrical characteristics.
Figure 4
689
TABLE 3
SYMBOL
VIH
VIL
IIH
IlL
CL
PR
VOH
VOL
PD
IL
PARAMETER
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Programmable Resistor
Output High Voltage
Output Low Voltage
Power Dissipation
Input Buffer
Logic Gate
Driver
I/O Buffer
D Flip/Flop
JK Flip/Flop
D Flip/Flop Reduced Power
Output Leakage
MIN
2.2V
3.0
TYP
6.5
MAX
.8
20
-200
10
10
pf
mw
mw
mw
mw
mw
mw
mw
9
3
4
7
10.0
30.0
14.0
17.0
7.0
4.5
No resistor
No resistor
.4
6
9
9
CONDITIONS
V
V
J.tA
J.tA
KQ
V
V
2.4
20
UNIT
±10
= -200J.tA
= 4.0ma
10H
10L
50% duty cycle
50% duty cycle
J.tA
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other riuhts of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
690
Printed In U S.A
Network Products
Page
Part Number
WD2501/2511
WD2520
WD2840
WDK25001
Packet Network Interface (LAP/LAPS) ....................................
CCITI #7 Data Link Controller ..........................................
Local Network, Token Access Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PACKIT ............................................................
691
693
705
707
719
692
WESTERN DIGITAL
o
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/
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WD2501/2511 Packet Network Interface (LAP/LAPB)
FEATURES
• Packet switching controller, compatible with
CCITT recommenda.tion X.25, level 2, LAP (2501) or
LAPB(2511)
• TTL compatible
• 48 pin dual in-line packages
• Higher bit rates available by special order
• Programmable primary timer (T1) and retransmission counter (N2)
• Programmable A-field which provides a wider
range of applications than defined by X.25. These
include: DTE-to-DTE connection, multipoint and
loop-back testing
APPLICATIONS
X.25 PACKET SWITCHING CONTROLLER
PART OF DTE OR DCE
PRIVATE PACKET NETWORKS
LINK LEVEL CONTROLLER
• Direct memory access (DMA) transfer. two
channels; one for transmit and one for receive.
Send/receive data accessed by indirect addressing
method. Sixteen output address lines.
• Zero bit insert and delete
• Automatic appending and testing of FCS field
• Computer bus interface structure: 8 bit bidirectional data bus. CS, WE, RE and four input
address lines
GENERAL DESCRIPTION
The WD2501/2511 is a MOS/LSI device which handles
bit-oriented, full-duplex serial data communications
with DMA, which conforms to CCITT X.25 with
programmable enhancements.
The device is fabricated in N-Channel silicon gate
MOS technology and is TTL compatible on all inputs
and outputs.
• DC to 1.1 MBPS data rate
NO CONNECTION
1
REPLY
WE
cs
Cs
FiE
IA3
INTR
VOO(+ l2V)
A5
elK
Wi
OAlO
OAll
DAl2
OAl3
DAL4
DAl5
DAl6
DAl7
RD
WE
liE
IAO-IA3
rFmI
A3
A2
+12V~
+5V~
A13
A12
RC
GND_
<~--
~
WE
DALO·DALl
---->r----(
DALO·DAL7
CPU READ TIMING (CS IS LOW)
i T D D . , r - -_ _ _
"-----~
I .,------..)1>----------i
'-,----j ---------- ---;,
AO·A15
(ADRV = O J - ! - · - - - - - + < :
DROI
VALID
.___
'--..---1
5ACi<--
------::;;,1T;;~ I-
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'----.--<
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TDMW
DATA VALID
~ ITDDj/~
_ _ __
\t:,ow~
>----
I-4---TDAO
f--
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DATA VALID
)>----
\--TRD-l
DMA IN (AO·A15 SAME AS DMA OUT)
DMA OUT TIMING
703
WD2501111 ORDERING INFORMATION
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PART NO.
WD25XX-01
WD25XX-05
WD25XX-11
MAX. DATA RATE
100 KBPS
500 KBPS
1.1 MBPS
See page 725 for ordering information .
...L
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license Is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
704
Printed In U.S.A
WESTERN DIGITAL
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WD2520 CCITT #7 Data Link Controller
FEATURES
• Performs most of the controls of the Message
Transfer part of CCITT #7.
• Dual Channel DMA for full-duplex operation.
• Unique memory access method for buffer
management.
• All formatting of bit-oriented control included: zero
bit insertion and deletion. Automatic appending
and testing of flags and FCS Fields.
• Automatic control of sequence numbers FSN and
BSN, and of control bits FIB and BIB.
• Optional selection of either "Basic" error
correction method or the preventive cyclic retransmission error correction method.
• Computer bus interface structure: 8-bit bidirectional data bus. 16-bit address bus for DMA. 4bit input address bUis (may be tied to lower 4 bits of
16 bit address). CS, RE, WE.
• 48-pin dual in-line package. Pin assignment compatible with the WD2501 and WD2511 packet network interface chips.
GENERAL DESCRIPTION
The WD2520 is a MOS LSI device which is compatible with the CCITT Recommendation #7 (Signalling System Number 7). The overall objective of
Signalling System #7 is to provide one internationally
standardized general purpose common channel signalling system for information transfer within telecommunications networks. (Le. signalling from one
central office switch to another).
The WD2520 performs most of the controls of the
Message Transfer Part of CCITT#7. The device includes a unique buffer management scheme with
dual channel DMA.
The WD2520 is pin-for-pin compatible with the
WD2501/2511 popular Level 2 X.25 controller.
See page 725 for ordering information.
• TTL compatible.
• Speeds to 1.1 MBit/Sec Transmit-Receive Rate.
• Telephone central office signalling.
48
NO CONNECTION
REPLY
WE
g§'
RE
CLK
i'N"fR
Kim
DALO
DAL1
DAL2
DAL3
DAL4
DAL5
DAL6
DAL7
RD
WD2520
Rc
(GND)VSS
i'C
TD
Rrs"
CTS
'DRao
DRal
VCC(+5V)
IA1
lAO
IA2
IA3
24
VDD(+ 12V)
A5
A4
A3
A2
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
AO
A1
DACK
I/O
REGISTERS
16x8
;;1M
--
iNTR
+ 12V-..
+5V-a.-.
M'R------.
CLK--....
GND---..
RC~
F:igure 1.
PIN CONNECTION
Figure 2. BLOCK DIAGRAM
705
DMA
CONTROL
LOGIC
i5FiQi
=
0=
This is a preliminary specification with tentative device parameters and may be subject to change after final product characterization is completed.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
706
Printed .n U.S.A
WESTERN DIGITAL
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WD2840 Local Network, Token Access Controller
protocol allows the sharing of one bus by up to 254
nodes. 2840's will be designed into process control
equipment, micro-computers, mini-computers, personal computers, proprietary micro-processor based
applications, intelligent terminals, front-end processors, and similar equipment.
The great advantage for the design engineer is the
ease with which he can implement a local network
function. The 2840 handles autonomously all major
communcations tasks as they relate to the local
network function.
fEATURES
•• Broadcast Medium Oriented (Coax, RF, CATV, IR,
etc.)
•• Up to 254 nodes/1.1 Mbps
•• Dual OMAlHighly efficient Memory Block
Chaining
•• Token based protocol
.. Acknowledge option on each datagram
•• Adjustable fairness, stations may be prioritized
•• Frame format similalr to industry standard HOLC
•• Supports Global Addressing
•• Diagnostic Support: Self-Tests, System and
Network
•• TTL Compatible
GENERAL DESCRIPTION
The W02840 is a MOS/LSI device intended for local
network applications, where reliable data communications over a shared medium is required. The
device uses a buffer chaining scheme to allow efficient memory utilization. This scheme minimizes
the host CPU time requirements for handling packets
of data. The W02840 frees the host CPU from extensive overhead by performing network initialization, addressing, coordination, data transmission, acknowledgements and diagnostics.
APPLICATIONS
The 2840 is a general purpose Local Network Token
Controller applicable to virtually all types of multipoint communications applications. The token
~-------------------------------------------------I
DNC
CD'
I
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DALO·7,IAO·3
REGISTER
FILE
(16 HOST
VISABLE)
DAL3
DAL7
RD
RC'
(GND)VSS
TC'
TD
RTS'
CTS'
I
I
DMA REGS
(2 CHAN)
I
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,------------------------~---------------------
BLOCK DIAGRAM
PIN CONNECTIONS
707
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The WD2840 is packaged in a 48 pin DIP. The
following is a functional description of each pin. An
asterisk after a signal name (SIGNAL *) means active
Low.
PIN
NUMBER
PIN NAME
FUNCTION
SYMBOL.
+ 5VDC power supply input
+ 12VDC power supply input
48
POWER SUPPLY
VCC
42
POWER SUPPLY
VDD
18
GROUND
6
CLOCK
VSS
CLK
Ground
Clock input used for internal timing. Must be
square wave and 1.0-2.5 MHz.
7
MASTER RESET
MR*
4
CHIP SELECT
CS*
Initialize on active low for at least 10 ms. All
registers reset to zero, except control bits ISOL
and ALONE are set to 1. DACK* must be stable
high before MR* goes high.
Active low chip select for CPU control of I/O
registers.
DATA ACCESS LINES
DALO-7
5
READ ENABLE
RE*
3
WRITE ENABLE
WE*
The data on the DAL are written into the
selected register when CS* and WE* are low.
RE* and WE* must not be low at the same time.
43
INTERRUPT REQUEST
INTR*
An active low interrupt service request output.
Returns high when Interrupt Register is read.
ADDRESS LINES IN
IAO-IA3
Four address inputs to the 2840 for CPU controlled read/write operations with registers in
the 2840. If ADRV 0, these may be tied to
AO-A3.
Sixteen address outputs from the 2840 for DMA
operation. If the output control bit ADRV 1,
the outputs are TIL driven at all times. If
ADRV 0, the outputs are tri-state, and are H 1-2
whenever DACK* is high.
8-15
44-47
An 8-bit bi-directional three-state bus for CPU
and DMA controlled data transfers.
The content of the selected register is placed
on DAL when CS* and RE* are low.
=
26-41
ADDRESS LINES OUT
AO-A15
=
=
An active low output Signal to initiate CPU bus
request so the 2840 can output onto the bus.
An active low output Signal to initiate CPU bus
requests so that data may be input to the 2840.
23
DMA REQUEST OUT
DRQO*
24
DMA REQUEST IN
DRQI*
25
DMA ACKNOWLEDGE
DACK*
An active low inputfrom the CPU in response to
DRQO* or DRQI*. DACK* must not be low if
CS* and RE* are low or if CS* and WE* are low.
20
16
19
TRANSMIT DATA
RECEIVE DATA
Transmitted serial data output.
TRANSMIT CLOCK
TD
RD
TC*
17
RECEIVE CLOCK
RC*
21
REQUEST-TO-SEND
RTS*
Receive serial data input.
A 1X clock input. TD changes on the falling
edgeofTC*.
This is a 1X clock input, and RD is sampled on
the rising edge of RC*.
An open collector output which goes low when
the 2840 is ready to transmit either data or flags.
May be hardwired to ground.
708
•
PIN
NUMBER
PIN NAME
SYMBOL
22
CLEAR-TO-SEND
CTS*
2
CARRIER DETECT
CD*
1
DO NOT CONNECT
DNC
FUNCTION
An active low input which signals the 2840 that
transmission may begin. May be hardwired to
ground.
An active low input which signals the WD2840
that a frame may be received. CD* should
remain active throughout the received frame.
The modem may negate this signal if its receive
signal quality is below a reliability threshold,
ensuring that the 2840 will not accept the frame.
Leave pin open.
CPU BUS
MEDIUM
AO-15
TD
TC
WD2840
MODEM
RTS
CTS
DALO-7
RD
RC
CD
IAO-3
TYPICAL SYSTEM CONNECTION
DATA:
ACCESS CONTROL:
TOKEN:
1
1
I
F
TC
DA
F
DA
AC
F
TC
FCS
1
1
SA
FCS
I> :1
1
F
1
FCSG
I
F
I
FRAME FORMATS
.1..................................................................... .
709
FRAME FORMAT
REGISTER DEFINITION
The frame format the 2840 uses to transmit all data
and control frames is similar to the industry standard
HDLC. A 16 bit CRC is implemented and standard
zero insertion is used for framing. This framing
method allows the use of standard network monitoring and diagnostic equipment such as data scopes
and logic analyzers.
The WD2840 is controlled
sixteen 8 bit I/O registers:
REG (1\ NAME
Additional address fields and control points are
defined as required to support the protocol.
Normal Frame Format:
F - TC F
TC
DA
SA
I
DA - SA -
I-
FCS -
F
= Flag, binary pattern 01111110
~
= Token Control (8 bit)
= Destination Address (8 bit)
A
B
C
D
E
F
= Source Address (8 bit)
Information Field (0 to 2048 bytes) or 16
buffers, whichever is less.
FCS = Frame Check Sequence (16 bit)
Access Control Format:
F-
DA -
AC -
FCS -
CRO
CR1
SRO
IRO
SR1
SR2
CTRO
NA
TA
TD
CBPH
CBPL
NAR
AHOLT
TXLT
MA
0
1
2(2)
3(2)
4(2)
5(2)
6(2)
7(2)
(1)
(2)
F
= Flag, Bi nary pattern 01111110
F
DA = Destination Address (8 bit)
AC = Access Control Field (8 bit)
FCS = Frame Check Sequence (16 bit)
and
monitored
by
DESCRIPTION
Control Register 0
Control Register 1
Status Register 0
Interrupt Type Register
Status Register 1
Status Register 2
Counter Register 0
Next Address
ACK Timer
Net Dead Timer
Control Block Pointer (MSByte)
Control Block Pointer (LSByte)
Next Address, Request
Access Hold-Off Limit
Transmit Limit
My Address
= Hexadecimal representation of IAO-IA3.
= CPU read only, write not possible.
Control, status, and interrupt bits will be referred to
as CR, SR, or IR, respectively, along with two digits.
For example, SR21 refers to status register #2 and bit
1, which is "STATE."
Token Pass Format:
F-TC-FCS-F
F
TC
FCS
= Flag, binary pattern 01111110
= Token Control (8 bit)
= Frame Check Sequence (16 bit)
SUMMARY - CONTROL, STATUS, INTERRUPT REGISTERS
I
BIT#
REGISTER
CRO
CR1 (2)
CR1 (4)
SRO
SR1
SR2
IRO(2,3)
7
TXDEN
DIAGC
DIAGC
LASTF
TAOUT
NXTTO
ITUR
5
6
TXEN
PIGT
0
SENDACK
IRTS*
NXTRO
IRUR
RXEN
INIT
0
L2
RECIDL
TR
INS
3
2
1
ILOOP
GIRING
DMAT
BSZ3 .....
0
RETRY
IREC
COPY
0
LOOP
BSZ2 .....
0
TSENT
ITOK
NOINT
0
RAMT
BSZ1 .....
0
STATE
ITA
4
TOFF
ADRV
0
0
0
ACKRQ
ITRAN
NOTE: Zero bits (0) shown above are reserved and should not be used.
FOOTNOTES:
(1)
Is set to 1 on power-up or master reset.
(2)
Network mode only (CR17 - DIAGC cleared).
(3)
Any bit set causes host interrupt (INTR* goes true)
when Master Interrupt Suppress (CR01) is clear. All bits
, are cleared when register is read by the host.
(4)
Diagnostic mode only (CR17 DIAGC set). See
diagnostic section for register usage in diagnostic
mode.
710
0
ISOL(1)
NEWNA
NUDIAG
BSZO
0
INRING
ITD/M
CONTROL REGISTER 0 DEFINITIONS
BIT
NAME
DESCRIPTION
CROO
ISOL
Isolate. Is set after a master reset. Will get reset when the Control Block and other
WD2840 registers have been set. When ISOL set, the WD2840 will logically disconnect from the network.
CR01
NOINT
CR02
CR03
COpy
Master Interrupt Suppress. When clear, the 2840 will generate host interrupt requests
(lNTR* low) if any bit in the 2840 interrupt request register (IRO) is set. When set, only
the interrupt request is suppressed, not the setting of bits in IRO.
Enables COPY mode, (a diagnostic.)
CR04
TOFF
CR05
RXEN
Receiver Data Enable - When set allows the receiver to DMA appropriate frames into
memory.
CR06
TXEN
CR07
TXDEN
Master Transmit Enable - When set allows at least non memory referenced transmissions (e.g. ACK and NAK). Must normally be set when TXDEN is set.
Transmit Data Enable - When set allows transmitter to DMA information from
memory and transmit it when access rights (token) are received.
ILOOP
Instructs the 2840 to loop data internally from transmitter to receiver: Used with the
LOOP diagnostic. Must NOT be set while in network mode.
When set causes 2840 to ignore timers. This is NOT intended to be used in an
operational network but is provided to support network diagnosis. CAUTION: This
control bit disables all automatic network error recovery.
CONTROL REGISTER 1 DEFINITIONS (NETWORK MODE)
BIT
NAME
DESCRIPTION
CR10
NEWNA
CR11
CR12
CR13
GIRING
CR14
ADRV
Address Driver Enable. Enables the sixteen output address (AO-A15). If ADRV = 0, the
outputs are tri-state and are in HI-Z, except when DACK* is low. If ADRV = 1, the
outputs are always TTL levels.
CR15
INIT
CR16
PIGT
Network Initialization Enable. When set, TO timer expiration causes the WD2840 to
enter SCAN mode.
Piggy Back Token. If set, instructs the WD2840 to piggy back token on last frame
transmitted.
CR17
DIAGC
-
Update NA register: When set causes 2840 to copy the contents of register NAR into
register NA. The 2840 clears this bit after the function is complete.
(Not used, Reserved.)
(Not used, Reserved.)
Get in logical ring. Instructs the 2840 to gain entry into the logical ring at the next
opportunity (Le. respond to a token pass).
Enables diagnostic mode. In network mode this bit should be zero.
CONTROL REGISTER 1 DEFINITIONS (DIAGNOSTIC MODE)
NAME
DESCRIPTION
BIT
CR10
NUDIAG
CR11
RAMT
LOOP
DMAT
CR12
CR13
CR14
CR15
CR16
CR17
-
DIAGC
Perform a new diagnostic. When set causes 2840 to perform one of the four
diagnostics. The host initializes the appropriate registers for the particular diagnostic
and by setting this bit can initiate the test. The 2840 clears this bit after completion of
the diagnostic.
Selects internal RAM test when in diagnostic mode.
Selects Loop Test if in diagnostic mode.
Selects DMA Test if in diagnostic mode.
(Not used, Reserved.)
(Not used, Reserved.)
(Not used, Reserved.)
Enables diagnostic mode.
711
STATUS REGISTER DEFINITION
BIT
NAME
SROOSR03
DESCRIPTION
BSZOBSZ3
Buffer Size, multiples of sixty-four bytes (the multiple ranges from 0 to 15, meaning
buffers are 64 to 1024 bytes).
Not used.
An internal flag set during frame transmission if the length value of the current frame
is equal to eight.
An internal flag set during data frame reception to indicate that the incoming frame
should be acknowledged (send acklnak frame). This flag is cleared when the
acknowledgement has been transmitted.
SR04
-
SR05
L2
SR06
SENDACK
SR07
LASTF
An internal flag set during data frame transmission to indicate that the current frame
will be the last to be transmitted during this access period.
SR10-
-
(Not used, Reserved.)
SR15
RECIDL
SR16
IRTS*
Receiver Idle.
Internal Request To Send. Indicates the transmitter is attempting (successful or not)
to send either data or flags. If..!!~RTS* pin is not tied to ground or WIRE-ORED with
another signal, then IRTS* = RTS.
SR17
TAOUT
SR20
INRING
SR21
STATE
SR22
TSENT
SR23
RETRY
SR24
ACKRQ
An internal flag set during data frame transmission if an acknowledgement is
requested for the specific framE!.
SR25
TR
An internal flag set when the 2840 receives a token passed to it. It is cleared when the
token is passed (or if it is ignored for any reason).
SR26
NXTRO
SR27
NXnO
Internal Receive Buffer Pointer State. When set it indicates the 2840 has the address
of the next buffer and that all prior frames (denoted by posted FSB's) can be removed
from the chain for received frame processing by the host. When NXTRO is clear it
indicates that the 2840 has advanced to a zero link (end of cha~n}.
Internal Transmit Buffer Pointer State. When NXnO is set it indicates that the 2840
has the address of the next frame to transmit in its internal register. However when
clear, it indicates that the transmit chain internal register points to the link field of the
last buffer of the last transmitted frame.
SR14
TimerTA expired.
In logical ring. Indicates the node has had the token and has successfully passed it at
least once (therefore it is included in a logical ring of at least two nodes).
Mode confirmation. Depending on DIAGC (CR17), the 2840 is either in Isolate or
Diagnostic state. When ISOL (CROO) is set, STATE set confirms the 2840 is not in
Network State. When ISOL is clear, STATE clear confirms Network State.
An internal flag. TSENT is set when the 2840 passes the token. It may have been
either a piggyback or explicit token pass frame. TSENT is cleared when the next
frame is received.
An internal flag which is set when either a data frame or a token pass frame must be
retransmitted.
INTERRUPT REGISTER DEFINITION
The setting of any bit in this register by the 2840 causes an interrupt (INTR = true). The reading of this register
clears all bits.
DESCRIPTION (1)
BIT
NAME
IROO
IR01
ITD/M
Network dead. TimerTD expired.
ITA
Data Frame Transmission unsuccessful. NAK or no response after two tries. Exact
cause is determined by reading appropriate FSB.
IR02
ITOK
The token has been received.
'--
112
BIT
NAME
IR03
IR04
IREC
ITRAN
-.
DESCRIPTION
Indicates data frame(s) have been received with address destined for this 2840.
Indicates data frames have been transmitted. The number of frames transmitted and
the status of each (e.g. ACKINAK Retry Count) is determined by following the trans·
mit chain and interrogating the FSB's.
IR05
INS
New successor. The 2840 has identified a new successor in the logical ring.
IROO
IROR
Receiver over·run.
ITUR
IR07
Transmitter under·run.
[1] = Non diagnostic mode only.
DIAGNOSTIC MODES
The WD2840 has been designed to support (3) three
levels of diagnostics. These levels shown in the
diagram can be used separately or together to per·
form such varied tasks as receiving inspection to
nHtwork fault isolation. As is shown in the diagram,
each level is actually composed of modules which
test particular areas of each level.
NETWORK LEVEL
• DUPLICATE STATION DETECTION
• COPY MODE
• NAK RESPONSE
LEVEL3
SYSTEM LEVEL
• DMA TEST
• LOOp·BACK TEST
LEVEL2
DEVICE LEVEL
I
I
• INTERNAL RAM TEST
• INTERRUPT TEST
Diagnostic Mode Control
eROO CR17 SR21
ISOL DIAGC STATE
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
0
0
1
1
0
0
1
1
LEVEL 1, DEVICE SELF·TESTING
There are two self·test features: 1) Internal Ram Test,
and 2) Interrupt Test. Both tests are suitable for
manufacturing testing and user incoming inspection
testing .
These self tests may be instigated by the user
anytime the 2840 is in diagnostic mode. This mode
may be entered after power·up or from network mode
by manipulation of the mode control bits. The mode
transition is confirmed by the 2840 via the DIAG
status bit.
LEVEL 1
MEANING
Internal RAM Test
There are eleven eight bit registers in the 2840 which
are not directly accessable by the users CPU. This
test provides a means to check those registers. The
contents of register A are placed in six even internal
registers, and the contents of register B in five odd
internal registers. The eleven registers are then
added together without carry and the result is placed
in registers 2, 5, 6, 7.
Use the following procedure to initiate the RAM test:
1. Enter diagnostic mode.
2. Set up registers A and B
3. Set RAMT.
4. SetCR1---
r
~~MU
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~RE~PL~Y---~--~I--TR-P1~t: -----~-T-R-P2~
CPU WRITE (CS IS LOW)
CPU READ (Cs IS LOW)
•
717
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00
,J:::.
0
AO.A15
(ADRV =
I
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0)-...1
TDA1
AO·A15
(ADRV
1)
=
TOOj
;/
(AO·A 15 SAME AS DMA DUll
<
1
~~ TDAO~
':-----j-----------------------r
'~----i-----------~--;;A~:' I.-
DACK--------~~
DACK - - - - - . .
r-
~DATA VALID
TOMW
OALO.DAL7_ _ _ _ _ _ _ _ _ _-«
)>-_____ _
r------
,,~----~~-~~~~
)/r--~----------
I
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~TDW~
DALO.DAL7-----------«
D~
LTRD~
DMA OUT
DMAIN
0.115 MAX
A
..II.. o· + 15"
_0'
WD2840 CERAMIC PACKAGE
See page 725 for ordering information.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other riQhts of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
~'18
Printed
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WESTERN DIGITAL
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WDK25001 PACKIT
FEATURES
• X.25 (WD2501
CONTROLLER
OR
WD2511)
NETWORK
• BAUD RATE GENERATOR
• RS-423INTERFACE
• 8 SOCKETS FOR OPTIONAL USER RAM, ROM,
EPROM
• WIRE-WRAP HOST INTERFACE AREA
ORGANIZATION
• INTERNAL DATA RATE TO 64 KBPS
• +5°CTO +50°COPERATION
The WDK25001 "PACKIT", is composed of two major
physical areas. The printed circuit area contains
factory installed circuitry which handles the Packet
Network Interface device, programmable bit rate
generator, memory address decoder, and the EIA RS423 interface. The wire-wrap area is set up to allow
the user to design and implement their own host
interface and or level 3 and higher modules.
GENERAL DESCRIPTION
The Western Digital WDK25001 PACKIT is a preconfigured breadboard designed to be an instant
development tool for the implementation of bitoriented, full duplex, serial X.25 data communication
systems. Most of the hardware interfacing (Level 1/2
interfacing) is already done on the board. Level 2/3
interfacing is described in the long form specification. To perform Link Control (Level 2) functions, the
PACKIT utilizes the Western Digital LSI Packet
Network Interface Device. Two versions of the LSI
Packet Network Interface Device are available for use
with the PACKIT: the WD2501 and the WD2511. The
WD2501 LSI device handles the LAP (Link Access
Procedure). The WD2511 LSI device handles LAPB
(Link Access Procedure Balanced).
The PACKIT is composed of two major physical
areas. One side of the printed circuit board contains
the factory installed circuitry required to perform X.25
Link Level operations: the other side of the circuit
board contains the wire-wrapping area for user implementation of the individual system design.
INTERFACES
The PACKIT interfacing (Level 1/2) is divided into two
classifications: the user interface and the serial
communications interface.
USER INTERFACE
Voltage Levels:
TTL
Architecture:
Microprocessor interface oriented. 16 Address lines,
8 data lines, 10 control lines.
SERIAL COMMUNICATIONS
INTERFACE
Electrical Characteristics:
The wire-wrapping area of the circuit board is
designed to accommodate any industrial standard IC
package. IC width is defined in 0.15 inch increments,
with IC pin separation of 0.1 inch. The wire-wrap area
is large enough to permit the installation of approximately one hundred 16-pin IC's.
RS-423
Mode:
Synchronous, Bit stuffing oriented, full-duplex, X.25
Asynchronous Response Mode (WD2501) or X.25
Asynchronous Balanced Mode (WD2511).
Clock Rates:
Independent transmit and receive clocks. Either
internal or external clock source, selected by jumper
strapping. Internal clock rates selectable by DIP
switches or under user program control via the User
Interface .
•
719
=e
c
BR1941
BAUD
RATE GEN
"
N
(J1
o
o......
WD2501/WD2511
X.25 PACKIT NETWORK
INTERFACE
RIBBON
CONN
RS-423
INTERFACE
RAM/ROM/EPROM
SOCKETS
PROTOTYPING ARJ
PACKIT BLOCK DIAGRAM
ELECTRICAL SPECIFICATIONS
PHYSICAL DIMENSIONS
Voltage Requirements:
Size:
Single printed circuit board, B inches by 14 inches
(203.2 by 355.6mm)
+5v, +/- 5%
+ 12v, +/- 5%
-5v, +/- 5%
Weight:
Maximum Voltage Ripple:
2 Pounds (0.907Kg).
100mv, PTP
THE LSI PACKIT NETWORK INTERFACE DEVICE
The Packit Interface Device is a 4B-pin, n-channel
silicon-gate, MaS chip designed to perform CCITT
X.25 Level 2 (link control), with selected enhancements. In addition to the link control functions
required by X.25, the Device eliminates the need for
separate DMA circuits, timing chips, and the system
software previously required to perform the link
control between a data terminal equipment (DTE) and
a data circuit-terminating equipment (DCE).
The WD2501IWD2511 interfaces directly with the onboard memory (when installed) or with the user's
memory data and address lines. The WD2501/
WD2511 is controlle.Q....through nine user interface
lines: Master Reset (MR), REPLY, DMA Request Out
(DRQO), DMA Request In (~R~~, DMA Acknowledge
(DACK), Interr~t Request (N ), Write Enable (WE),
Read Enable (RE), and Chip Select (CS).
Additionally, the WD2501IWD2511 is driven by the 1
MHz system clock.
Factory·lnstalled Circuitry Power Requirements:
+ 5v @ .76A (max.)
(No memory device) + 12v @ .20A (max.)
- 5v @ .04A (max.)
MEMORY SPECIFICATIONS
Maximum Size Allowable:
64KxB.
Memory Type:
B·bit wide RAM, ROM, EPROM
Package Type:
24-pin or 2B-pin
ENVIRONMENTAL SPECIFICATIONS
Operating Temperatures:
+ 5 to + 50 °C (Maximum temperature is reduced by
1.B degree centigrade per 1000 meters altitude above
sea level.)
THE PROGRAMMABLE BIT RATE GENERATOR
Circuit board IC location U3 contains a Western
Digital BR1941 Programmable Bit Rate Clock. This nchannel MaS silicon·gate device is capable of
generating sixteen externally selected clock rates,
where-of six are standard rates.
The bit rate for both transmit and receive frequencies
may be selected independently through the on-board
Relative Humidity:
10 to 95%, maximum wet bulb of 32 degrees Centigrade and a minimum dew-point of 2 degrees
Centigrade (90 degrees and 36 degrees Farenheit,
respectively.)
720
DIP switch, S1, or through the user's program via the
TA, TB, TC, TO, RA, RB, RC, and RD user interface
control lines.
THE EIA RS·423 INTERFACE
The communications link between the Western
Digital PACKIT and the Data Communications
Equipment (DCE) is provided through the EIA RS-423
interface. This interface contains a subset of the
RS449 signals. The interface signals are supplied to a
40-pin ribbon cable connector. Each of the RS-449
signals are buffered by 26LS29-type RS-423 line
drivers and 26LS32 RS-423 line receivers.
If RS-232-C interfacing is desired, instead of RS449
interfacing, the ribbon connector may be jumpered to
provide RS-232-C signal compatability. However, due
to differences in signal voltage levels, certain
precautions must be taken when converting to RS232·C interfacing.
To further increase PACKIT flexibility, the bit rate
generator is installed in an IC socket to enable easy
removal for specialized user bit rates not conforming
to those available from the BR1941.
PACKIT MEMORY
Located on each PACKIT printed circuit board are
eight 28-pin IC sockets designed for optional userinstalled RAM, ROM, or EPROM memory chips.
These sockets present the user with the option of
either using the system memory or off-loading the
PACKIT memory functions to on-board memory of
the user's choice. Once the optional memory is installed it may be accessed by both the user's
computer and by the WD2501IWD2511 Network
Interface Device via DMA.
BIT RATE GENERATOR - PROGRAMMING AND
STRAPPING
The Western Digital BR1941 Bit Rate Generator, on
board the PACKIT, may be programmed for receive
and transmit bit rate, by on-board switch setting or by
program command from the user circuitry. The
selection between these two options is controlled by
the S1 switchpack. To use program control all
switches of S1 must be in the "OFF" position
otherwise the bit rate is the "wired-and" of the
program control and the setting of the switches.
Transmit and receive bit rates are independently
selected.
Program control of the bit rate, when enabled, is
received by th'e PACKIT via the TA, TB, TC, and TD
jumper pads, for the transmit bit rate, and via the RA,
RB, RC, and RD jumper pads, for the receive bit rate.
(Each of these control lines is tied to + 5v via a 2.2K
resistor pull-up.)
NOTE:
All memory devices installed on the PACKIT board
must be 8-bit wide devices. Total memory installed
must not exceed 64K-bytes.
The design of the memory sockets permits the user a
wide range of RAM, ROM, and EPROM selectability.
Memories such as the 4802 (2K x 8 RAM), 4118 (1 K x 8
RAM), and the 2716 (2K x 8 EPROM), allow the user to
select the type, capacity, and expense of memory
desired for each individual application.
Also, the design of the sockets provides for the use
of either 28·,pin or 24-pin memory circuits. If a 24-pin
Circuit is to be installed, the chip is simply inserted in
a manner that places pin 1 of the memory chip in IC
socket posiltion 3. Pol~rization of the sockets is indicated by a white dot, on the PC board, adjacent to
both Pin 1 and Pin 3 of the socket.
When calculating the size of on-board memory, for a
particular application, it is imperative that the user
remember that the on-board memory must be large
enough to contain five major arrays.
1.
2.
3.
4.
5.
THE PACKIT USER INTERFACE
The Western Digital PACKIT user interface defines all
of the signals available to the user. These signals
include: the microprocessor oriented address, data,
and control lines, the RS-423 communications interface signals, the programmable bit rate generator
control lines and on-board strapping.
The data to be transmitted,
The data received,
The transmit-data look-up table (TLOOK),
The receive-data look-up table (RLOOK),
The PACKIT error counters.
USER INTERFACE SIGNALS
The user designed circuitry interfaces with the
PACKIT through the interface signal jumper pads
located at the center of the PACKIT PC board. The
signals are listed in the table on following page.
Signals are defined as "IN", "OUT", or "BI", to denote
input from or output to the user interface, or bidirectionality, respectively. RS-449 mnemonics are presented in parenthesis.
For a detailed description of the use of memory by
the Packit Network Interface Device, refer to the
WD2501IWD2511 Long Form Specification.
Industrial standard memory types like 4118 or 4801
(1 K x 8),4802 or 2716 (2K x 8), and 37000 or 2764 (8K x
8) can be used in the PACKIT.
721
USER INTERFACE SIGNALS
SIGNAL NAME
DIR
AO-A15
BI
DO-D7
BI
TMI(TM)
OUT
RDY REC(RR)
OUT
IN
SIGNAL DEFINITION
The sixteen memory address lines. These lines may be connected to the user's
memory address bus or to the PACKIT on-board optional memory chips, when
installed. These lines also carry the memory address outputs of the Packit Network Interface Device for DMA operations.
The eight bit data lines used to transmit and receive byte-oriented data between
the interface chip and the user circuitry. These lines also carry data between the
WD25011WD2511 and thE! optional on-board memory (when installed).
Test mode Indication. Signal returned from the RS-423 communications interface indicating that the local DCE is in the test mode. This signal is propagated to the user interface.
Ready to receive. Signal returned from the RS-423 communications interface
indicating that the communications link is ready to receive data. This signal is
propagated to the user interface.
DMA Acknowledge. The CPU signal generated in response to the
WD25011WD2511 transmitted DRaa or DROI DMA request signals. An active
low, sent to the PACKIT, on this line informs the PACKIT that the DMA request
is acknowledged and the CPU has relinquished control of the system bus.
DROI
OUT
DMA Request IN. The WD25011WD2511 requests a DMA bus access. A DROI is
a request for a transmission of data FROM the memory TO the
WD2501IWD2511. This signal is active low.
DRaa
OUT
MR
OUT
INTR
OUT
DMA Request OUT. The WD2501IWD2511 initiated signal requesting access for
a DMA data transfer. The, DRaa signal requests a DMA cycle to enable transfer
of data FROM the WD2501IWD2511 TO the memory. This signal is active low.
Master Reset. The master reset, generated by the on-board RESET momentary
closure switch, clears all of the WD2501IWD2511 control and status registers,
with the exception of two internal control bits (refer to the WD2501IWD2511
Long Form Data Sheet, sheet 2). This signal is active low.
Interrupt Request. The WD25011WD2511 issues INTR to request an interrupt.
This signal is active low.
IN
Chip Select. CS is driven low, by the user's circuitry to enable the
WD2501IWD2511 for programmed I/O read or write operations. CS may be
permanently activated by jumpering pad location S11 to ground.
DATA MODE
(DM)
OUT
REPLY
OUT
The DATA MODE signal is returned from the communications link, over the RS423 interface, to inform the PACKIT that the data link is in the data mode.
Reply. An active low signal, generated by the WD2501IWD2511 to indicate that it
is selected (CS is low) and it is either read enabled (RE is low) or it is write
enabled (WE is low).
CS
MWE
IN
An active low signal generated by the user's system to enable the PACKIT onboard memory chips for a memory-write operation. Not applicable on 24-pin
memories. All 24-pin memories are enabled through the J2'() through J2-7 interface signal lines. This signal is connected to pin 27 of all 28-pin memories.
J2-Oto J2-7
IN
User activated signal lines to individually enable each of the PACKIT on-board
memory sockets. Each active low signal enables the Write Enable (WE) input of
the respective memory socket where:
J2-0 write-enables memory socket U13
J2-1 write-enables memory socket U14
J2-2 write-enables memory socket U15
J2-3 write-enables memory socket U16
J2-4 write-enables memory socket U17
J2-5 write-enables memory socket U18
J2-6 write-enables memory socket U19
J2-7 write-enables memory socket U20
Each signal is connected to Pin 23 of the corresponding memory socket.
722
•
CONTINUED
SIGNAL NAME
DIR
USER INTERFACE SIGNALS
SIGNAL DEFINITION
TA, TB, TC, TD
IN
These four inputs combined select the Transmit bit rate to be generated by the
Western Digital BR1941 Programmable Bit Rate Clock. The values presented to
the bit rate clock generator, over these lines, may be determined either by the
user program or by on-board switch setting, as determined by switch-pack S1.
REMOTE LOOP
TEST (RL)
IN
TERM RDY (fR)
IN
When activated, the REMOTE LOOP TEST line forces the communications link
into a diagnostic test. Data is transferred from the memory, to the communications link, to the remote DCE, and back to the PACKIT for verification.
Terminal Ready. Input line to the PACKIT, from the user circuitry, informing the
DCE that the PACKIT is ready to set-up the communications link.
This signal is optionally generated, on a permanent basis, by the PACKIT when
jumper S12 is connected to ground.
LOCAL LOOP
TEST (LL)
IN
The LOCAL LOOP TEST performs a diagnostic operation similar to that of the
REMOTE LOOP TEST with the exception that the data being tested is transmitted to the local DCE and then returned to the PACKIT for verification.
MOE
IN
Memory Output Enable. A user supplied low active signal used to enable the
3-state output of the optional on-board PACKIT memory, when installed. This
signal is connected to pin 22 (28-pin) and pin 20 (24-pin) of the memory devices.
See page 725 for ordering information.
723
Information furnished by Western Digital Corporation is believed to be ac.curate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
724
Printed," U.S A
ORDERING INFORMATION
The following listing indicates the available packages for each product. The letter designation refers to
the package diagrams, beginning on page 727.
Part No.
WD1100·01
WD1100·02
WD1100·12
WD1100·03
WD1100·04
WD1100·05
WD1100·06
WD1100·07
WD1100·09
WD1010
WD1011
WD1012
WD1014
WD1050
FD1761
FD1763
FD1765
FD1767
FD1771
FD1781
FD1791
FD1973
FD1795
FD1797
FD279X
WD1691
DM1883
WD2143
WD2001·05
WD2001·20
WD2001·30
WD2002·05
WD2002·20
WD2002·30
TR1402·00
TR1602·00
TR1602·01
TR1863·00
TR1863·02
TR1863·04
TR1865·00
TR1865·02
TR1865·04
WD8250·00
WD2123·00
BR1941·XX
Total
Encapsulated
V
V
V
V
V
V
V
V
V
PL
PD
PC
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
PL
U
M
Ceramic
AL
AD
AC
AL
DS
A
A
A
A
A
A
A
A
A
A
AL
V
A
Cer·Dip
BL
BD
BC
BL
CL
CD
CC
CL
B
B
B
B
B
B
CL
CL
CL
CL
CL
B
CL
CL
CL
CL
CL
CE
CL
CD
B
B
B
BL
B
I:E
E
E
A
P
P
P
P
P
P
P
P
P
P
P
M
Rel·Pak
U
U
U
U
U
U
U
U
U
A
A
A
A
A
A
A
A
A
A
A
A
A
L
725
F
F
F
B
B
B
B
B
B
B
B
B
B
B
B
B
B
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
CD
Total
Encapsulated
Part No.
WD1943·XX
WD1945·XX
PR1472-00
PR1472-01
PT1482-00
PT1482-01
UC1671-00
WD1931-00
WD1933-00
WD1933-01
WD1933-02
WD1933·03
WD1933-10
WD1933-11
WDt933-f2
WDf9~3-01
WD1993:02
WD1993-03
WD1983-00
WD1984-00'
WD2501
WD2511
WD2520
WD2530
WD2840
WD51
WD55
WD4200
WD4210
WD4320
WD4321
FR1502-10
FR1502-11
WD1510-00
WD1510-01
WD1511
WD1801
WD1802
WD2412
WD5869
WD74HC200
WD1820
WD1840
WD8206
WD8207
WD9216·001
9216-01
WD8275
WD8276
M
M
Ceramic
Rel·Pak
Cer·Dip
...
N/A
N/A
B
B
B
B
B
B
B
B
B
B
B
B
B
F
F
F
F
F
CD
CD
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
CL
,
~
II-
A
A
A
A
A
A
A
A
A
A
A
A
A
E
E
E
E
E
.~
CH
T
T
T
T
T
T
PH
PG
PH
PH
V
V
V
PH
K
PC
PE
PLIPH
1\
E
C
E
C
E
E
E
E
U
U
U
B
B
F
F
F
F
F
F
CH
CH
CH
J
CC
AE
AllAH
DS
DS
BLlBH
PA
PL
PL
AL
AL
BL
BL
CL
CL
•
Package Diagrams
.100 MAX
.015
'" I~
1.425
___--1 MIN
~~MAX~--,-
1..-.610 ..-1
A
t4-.610~
I_MAX_I
T~{t ~
-...II.-~~ :g~~~ f.-' f ~
~~
.625
.100TYP
.014
.625
.120 MIN
.021
40 lEAD CERAMIC "A" or "Al"
+I
..
"'-1
.100MA),~..I....'
t
.100TYP~~
I.-.!~
II
~MIN
1I---:=-+
.035 .055
-J
~~
.310
MAX
.015
MI
1.020
MAX
28 lEAD CERAMIC "E" or "AH"
r--
.015
~mnmIlJ~;r
~:j
F:1
1..
·32~1
.100TYP
~-I'" I-J I....-jl ''''\:':
.055
.325
.014
.120
MIN
m1 ...
.021
20 lEAD CERAMIC "U" or "AE"
.100
MAX
t
.015
MI
.820
rc--MAX---~
T'~-fl
.100 TYP--1
~I
.014
.021
.035
.055
...
_I
-J
r----
.295
.325
.015 MIN
"'MAX
T
\...-
WWV\PJ41 ~
~
y
T'i'2QMIN
.100TYP-....j .0':-11
~J...-
1:oi5
~
.390
'
.055
16 lEAD PLASTIC "K" or "PC"
r
.155 MAX
1 I
-r~ ~~~
.100TYP
.320
.015
or "AC"
1
or "AD"
J..-,-c--J!~~MIN
1
.120MIN
.920~J
iJ
.310
MAX
F9
I~I -...\
r--
16 lEAD CERAMIC "J"
.155 MAX
~I
18 lEAD CERAMIC "l"
.320
L
...
1.040
.015MIN
MAX ~l
TWW\AAAJW
~ .320
~~
MAX
A
I
-.-
-.J~I....-~g:H I-~ ~: I- "OTyp--lh-IIg:;~ ~~ -I: I-~~
.014
.021
20 lEAD PLASTIC 'V" or "PE"
18 lEAD PLASTIC "M" or "PD"
727
Package Diagrams
.155MAX
J
L
1 460
~- MAX
----...jl
.-.j
.015 MIN
rwmvwtAAAJW-!I
.620
MAX
.120 I
MIN
.11 ~ i
11.c~
TWJ®1J\J\iJWwwww#~~ ~
f--
.1 55 MAX
.015 MIN
.620
______ 2.080
I
~
:!l ~---J
,oo",-J~l055~ 1--",
~ ~.100~YP
.035
.014
MAX
L
.035~ ~
I~~
.055
.690
.021
40 LEAD PLASTIC "P" or "PL"
28 LEAD PLASTIC "R" or "PH"
Ji~
re·
2080
.040 MIN
MAX
"'Jif20MIN 1
-,
1
~;~ I~·
~~A
L
~ 1~.100jYP :~;~~~ T
.014
.021
I...
:::~ .1
.175MAX
,
I
.100TYP-.!
rT~UMINFIl
-.J
Lc-.10~L
np
·~1
.048 - II -
~~~~
.1;t! .610MAX
-+t
I~I
.035_~
~
11.-4
1
r
~
I... ..690
640 .1
.055
.014
.021
.620
MAX
........
28 LEAD RELPACK "F" or "BH"
.015MIN
~----~o:~
--.,
TWW\MMMPUW#.OMIN
40 LEAD RELPACK "B" or "BL"
·150MAX
.040 MIN·
~-~-~;:~=-11
.015
1
.150T~¥
r--.6.10~
J. ,~
1.460
MIN
--I-'------ MAX - _...-j
1---
• - 1
~
I ... .640 ... 1
~oo
1= MAX~I
~
I...
~L.048-....jj.-~
.062
.100TYP
.640
.690
.120MIN
.014
.014
.021
.021
40 LEAD CERDIP "CL"
28 LEAD CERDIP "CH"
J.
.900
--I-r---- MAX--~
1
.015
MIN
k
.310-.1
I , MAX -, I
"Pwwwm+.t"A
k-1~048-.J k--~ ~
.100TYP
-...j
.062
---.
20 LEAD CERDIP "CE"
.014
-:021
18 LEAD CERDIP "CD"
728
.390
...
1
I
. . . . .1
PIN 111
.055
~-.100MAX
-...1
-ml5
It II
.040--.1 ~
TYP
. - r
~
1.-.100 MAX
I
~'-TYP
.020
48 l.EAD CERAMIC CHIP CARRIER "ON"
40 LEAD CERAMIC CHIP CARRIER "DL"
1....- - .720 ± .020----J~
100
MAX
--'- r--
.
2.430
MAX
.015
~ I MIN
.610
MAX
I~
+~f-t-~
.035
.055
L
Jl-I ~.100
-II....014'
--r
~
TYP
J,I"'::~:~I
.
MIN
.021
48 LEAD CERAMIC "T" or "AN"
64 LEAD CERAMIC CHIP CARRIER "OS"
See page 725 for ordering information.
729
730
WESTERN DIGITAL
c
o
R
o
p
R
A
T
o
/
N
Pin Compatibility Chart
AMO
TR1402
TR1602
TR1863
TR 1865
PR 1472
F'T 1482
UC 1671
\NO 8250
f-\NO 1983 1
BR 1941 2
WO 1943
WO 1945
WOlOlO
FD 1771-01
FO 179X
WO 4200
\NO 4210
WO 4320
WO 4321
w 74HC200 AM27LSOO
AMI
S1757
S1883
S1602
FUJITSU
W88868A
GI
AY-5-1013A
AY-6-l013
AY-3-1014A
AY-3-1015D
AY-3-14728 4
AY-3-14828 4
HARRIS
HUGHES
INTEL
INTERSIL
HM6402
HM6403
IM6402
IM6405
HCMP1854
- -f - - - - - - - --"--
-- ----
8251A1
"---
82062 "
------
-
-"--"------
----
-.---~-
--_.-
NITRON
RCA
SIEMENS
SIGNETICS
TR1402
2536
TR1602
t-
TR 1863
-- ---
_..- -
o
NATIONAL
-----~--
MM5303
COP1854
TI
SMC
COM2502
TMS6010 4
COM2502H_ 1--------"---COM2017
TMS6011 4
COM2017H
COM8502
COM8017
COM1863 COM8018
----
---~----~--
TR1865
PR 1472
I-
NC2259
NC2257
NC2260
PT1482
UC 1671
WO 8250
WO 1983 1
---
_."-
--~-
INS1671
INS8250
INS8251A1
COM1671 "-1----"------COM8251A
COM5016
COM5036 3
COM8016 -COM8036
COM8116
COM8136
BR 19412
WO 1943
-----"--"-WO 1945
- - - - " - - - - - - - 1---WOlOlO
INSl771-1
FD 1771-01
FD 179X
COPS420
WO 4200
WO 4210
~_ COPS421
WO 4320
COPS320
WO 4321
COPS321
o 74HC200
----"------~
-------
---------
SA8179X
"-
-"-
---------
- f-- ---------"--
w
•
731
c----
---=-~_~N74LS20Q_
732
Printed
In
USA
WESTERN DIGITAL
COR
P
0
RAT
/
0
N
High Reliability Relpak
Plastic Pack~ge Specificatio~
IFEATURES
41
41
41
41
41
41
41
41
II
AVAILABILITY
WDC has been supplying satisfied customers for
over nine years with this package. Because this
package was developed in-house, we have a completely self-sustained production line with very little
dependence on suppliers. The package was developed alongside the ceramic package, which means
equipment interchangeability on the assembly line.
This production versatility has enabled WDC customers to benefit from quick turn around times. We
patented this package in 1973 because of its reliability similarities to ceramic packages.
LOW COST CERDIP ALTERNATIVE
RELIABILITY ADVANTAGES OF A CERAMIC
PACKAGE
SUPERIOR MECHANICAL QUALITIES
OUTSTANDING ELECTRICAL
CHARACTERISTICS
CONSTRUCTION MATERIALS ELIMINATE
SOURCES OF RUST AND CORROSION
ELIMINATES HOT INTERMITIENT OPEN
PROBLEMS
ELIMINATES DEVICE INSTABILITY DUE TO
IONIC CONTAMINATION
MOISTURE 85/85 PERFORMANCE
DRAMATICALLY IMPROVED
SUPERIOR THERMAL PERFORMANCE
RELIABILITY AT LOW COST
Western Digital Corporation's RELPAK Plastic Package is unique to the industry in that it contains many
of the cost advantages of the industry accepted total
encapsulated package while it also contains many of
the reliability advantages of a ceramic package.
CONSTRUCTION DETAILS
The RELPAK is a cavity approach which allows the
use of aluminum wire for cost purposes and direct
aluminum-aluminum bond, while the plastic will
never come in contact with the active circuit and
wires. This eliminates the Hot Intermittent Open HIO
problems associated with industry standard plastic
packages and also eliminates device instability due
to ionic contamination caused by plastic being in
direct contact with the device.
90% ALL METAL CAVITY
DOUBLE LlDIDOUBLE BASE
0----
PLASTIC LID
~---ALLOY 42 SHIELD
~
\..&
PLASTIC PACKAGE
COPPER LEAD FRAME
50ll in. GOLD PLATED OR 100il in.
EVAPORATED AI PLATED
TERMINALS _
TIN DIPPED LEADS
The die is attached to its metal base separately from
the plastic package body. This allows for a true AuSi
Eutectic die attachment prior to the marriage with the
plastic body. This process design again eliminated
the chance for ionic contamination upon the active
circuit areas.
0 - - - MOS/LSI
DIE
GOLD SILICON EUTECTIC'
KOVAR OR ALLOY 42 BASE
~ GOLD STRIP PLATED
~
PLASTIC BASE
~
~
The package structure is such that 90% of the internal surface area is composed of metal. The
possible paths for moisture penetration are confined
to the parameters of the cavity, thereby increasing
the mean distance of moisture paths to its maximum.
STARTING MATERIAL
This package is constructed using a proprietary high
thermal conduction copper lead frame material,
which eliminates sources of rust or corrosion. Our
proprietary molding process allows WDC to mold
without the lead frame bonding surface ever making
contact with the molding material, again eliminating
possible sources for ionic contamination.
RECEIVING INSPECTION
MOLDING
Q.A. QUAL SAMPLES
100% INSPECTION
Q.A. FINAL INSPECTION
We use an Ortho Creasol Novolac Epoxy resin and a
Phenolic Novolac curing agent as the base transfer
molding compound. Together with our proprietary
STOCK ROOM
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Using standard stress acceleration factors, the
projected life expectancy of the WDC RELPAK
Package is well in excess of 100 years.
The basic RELPAK design employes a "see thru"
construction. The lead frames are stamped from 10
mil thick sheets of copper into strips of four, which
are then spot Ni spot Au plated or evaporated AI
plated. The quality levels of the lead frames and
molding powders are rigorpusly controlled by incoming Q.C. The lead frames and molding powders
are controlled by lot numbers. Each incoming lot is
individually assessed by W.D.C. material assurance.
."
ADVANTAGES OF THE RELPAK
The most obvious is its lower cost compared to its
ceramic counterpart without any reduction in reliability - by retaining the premolded cavity package
concept, essentially all the problems of a total encapsulated package are avoided such as work damage to
the bonding wires during the molding operation,
concern for adverse effects from direct contact of the
molding epoxy with the die surface, and the hot
intermittent open reliability problem. The use of a
solid metal lead frame coupled with the gold plated
Kovar (or Alloy 42) base to which the die is eutectically attached provide excellent thermal paths for
power dissipation, a primary reliability consideration .
~
See page 725 for ordering information.
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Careful adherence to sound engineering design
practices during package development coupled with
the use of a metallurgical bond at chip bond and
conventional aluminum wire bonding has resulted in
a plastic cavity package which can be subjected to
the same product assurance screening operations as
its ceramic counterparts without adversely affecting
the package or device parameters.
lead frame material we have achieved a true chemical
mechanical bond during the molding process. This
bond is so strong, we are able to place a device prior
to lid seal upside down on a helium leak detector and
pass a 1 x 10- 8 std cc/sec open face leak test.
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Information furnished by Western Digital Corporation is believed to be aCGurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
734
Printed In U S.A
Component Products
Terms and Conditions
1.
ACCEPTANCE: Unless otherwise provided, it is agreed that sales are made on the terms, conditions and warranties contained herein and that to
the extent of any conflict, the same take precedence over any terms or conditions which may appear on Buyer's order form. Seller shall not be
bound by Buyer's terms and conditions unless expressly agreed to In writing. In the absence of written acceptance of these terms, acceptance of
or payment for any of the articles covered hereby shall constitute an acceptance of these terms and conditions.
2.
F.O.B. POINT: All sales are made F.O.B. point of shipment. Seller's title passes to Buyer and Seller's liability as to delivery ceases upon making
delivery of articles purchased hereunder to carrier at shipping point In good condition; the carrier acting as Buyer's agent. All claims for damages
must be filed with the carrier. Unless specific instructions from Buyer specify which method of shipment is to be used, the Seller will exercise his
own discretion.
3.
DELIVERY: Shipping dates are approximate only. Seller shall not be liable for any loss or expense (consequential or otherwise) incurred by Buyer
if Seller falls to meet the specified delivery schedule because of unavoidable production or other delays. Seller may deliver the articles in installments, Seller shall not be liable for any delay In delivery or for non-delivery, in whole or in part, caused by the occurrence of any contingency
beyond the control either of Seller or Seller's suppliers, including, by way of Illustration but not limitation, war (whether an actual declaration
thereof is made or not), sabotage, Insurrection, riot or other act of civil disobedience, act of a public enemy, failure or delay in transportation, act
of any government or any agency or subdivision thereof, judicial action, labor dispute, accident, fire, explosion, flood, storm or other act of God,
shortage of labor, fuel, raw material or machinery or technical failure where Seller has exercised ordinary care in the prevention thereof. If any
contingency occurs, Seller may allocate production and deliveries among Seller's customers.
4.
TERMS AND METHODS OF PAYMENT: Where seller has extended credit to Buyer, terms of payment shall be net thirty (30) days from date of
invoice. The amount of credit or terms of payment may be changed or credit withdrawn by Seller at any time. If the articles are delivered in installments, Buyer shall pay for each Installment In accordance with the terms hereof. Payment shall be made for the articles without regard to
whether Buyer has made or may make any inspection of the articles. If shipments are delayed by Buyer, payments are due from the date when
Seller is prepared to make shipments. Articles held for Buyer are at Buyer's sole risk and expense.
5.
TAXES: All prices are exclusive of all federal, state and local excise, sales, use, and similar taxes. Such taxes; when applicable to this sale or to
the articles sold, will appear as separate additional items on the invoice unless Seller receives a properly executed exemption certificate from
Buyer prior to shipment.
6.
PATENTS: The Buyer shall hold the Seller harmless against any expense or loss resulting from Infringement of patents or trademarks arising from
compliance with Buyer's designs or specifications or Instructions. The sale of products by the Seller does not convey any license, by implication,
estoppel, or otherwise, under patent claims covering combinations of said products with other devices or elements. Except as otherwise
provided in the preceding paragraph, the Seller shall defend any suit or proceeding brought against the Buyer so far as based on a claim that any
product, or any part thereof, furnished under this contract constitutes an infringement of any patent of the United States, If notified promptly in
writing and given authority, Information and assistance (at the Seller's expense) for the defense of same, and the Seller shall pay all damages and
costs awarded therein against the Buyer. In case said product, or any part thereof, Is In such suit held to constitute Infringement and the use of
said product or part Is enjoined, the Seller, shall at Its own expense, either procure for the Buyer the right to continue using said product or part,
or replace same with non-Infringing product, or modify it so It becomes non-infringing, or remove said product and refund the purchase price and
the transportation and installation costs thereof. The foregoing states the entire liability of the Seller for patent Infringement by the said products
of any part thereof.
7.
ASSIGNMENT: The Buyer shall not assign his order or any interest therein or any rights thereunder without the prior written consent of Seller.
8.
WARRANTY: Seller warrants articles of its manufacture against defective materials or workmanship for a period of one year from date on which
Seller delivers said articles. The liability of Seller under this warranty Is limited at Seller's option, solely to repair, replacement with equivalent
articles, or an appropriate credit adjustment not to exceed the original sales price of articles returned to the Seller provided that (a) Seller Is
promptly notified in writing by Buyer upon discovery of defects, (b) the defective article is returned to Seller, transportation charges prepaid by
Buyer, and (c) Seller's examination of such article disclosed to Its satisfaction that defects were not caused by negligence, misuse, improper
Installation, aCCident, or unauthorized repair or alteration by the Buyer. In the case of equipment articles, this warranty does not Include
mechanical parts failing from normal usage nor does It cover limited life electrical components which deteriorate with age. In the case of accessories, not manufactured by Seller, but which are furnished with the Seller's equipment, Seller's liability is limited to whatever warranty is
extended by the manufacturers thereof and transferable to the Buyer. This Warranty Is expressed in lieu of all other Warranties, expressed or
Implied, including the Implied Warranty of fitness for a particlar purpose, and of all other obligations or liabilities on the Seller's part, and it
neither assumes nor authorizes any other person to assume for the Seller any other liabilities. This Warranty should not be confused with or
construed to imply free preventative or remedial maintenance, calibration or other service required for normal operation of the equipment articles.
These Warranty provisions do not extend the original Warranty period of any article which has either been repaired or replaced by Seller. In no
event will Seller be liable for any incidental or consequential damages.
9.
TERMINATION: Buyer may terminate this contract In whole or from time to time in part upon 60 days written notice to Seller. In such event Buyer
shall be liable for termination charges which shall include a price adjustment based on the quantity of articles actually delivered, and all costs,
direct and indirect, Incurred and committed for this contract together with a reasonable allowance for pro-rated expenses and profits. Any termination or back off In scheduling will not be allowed on shipments scheduled for the month In which the request is made and for the month
following.
10.
GOVERNMENT CONTRACTS: If the articles to be furnished under this contract are to be used in the performance of a Government contract or
subcontract and a Government contract number shall appear on Buyer's purchase order, those clauses of the applicable Government
procurement regulation which are mandatorily required by Federal Statute to be Included in Government subcontracts shall be incorporated
t1ereln by reference.
11.
ORIGIN OF ARTICLES: Seller engages In off·shore production, assembly and/or processing and makes no warranty or representation, expressed
or Implied, that the articles delivered hereunder are United States articles or of U.S. origin for the purpose of any statute, law, rule, regulation or
case thereunder. If Buyer ships the articles hereunder out of the U.S. for assembly, then at Buyer's request In writing, Seller shall provide information applicable to identification of any articles not of U.S. origin.
735
Corita Kent, the cover artist, is an American whose work presents an optimistic,
yet philosophical view of the world we live in. A former Catholic nun and
teacher, Corita now devotes her life and energies to her artwork and the "human
needs she feels transcend national and religious barriers." A true "citizen of the
world," Corita's philosophy positions her "on the positive side of hope." Her
depiction of the Western Digital mission . .. "Making the leading edge work for
you" ... dramatizes the spectrum of solutions we provide our customers.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
736
Printed
In
USA
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