1983_Western_Digital_Network_Products_Handbook 1983 Western Digital Network Products Handbook
User Manual: 1983_Western_Digital_Network_Products_Handbook
Open the PDF directly: View PDF 
.
Page Count: 224
| Download | |
| Open PDF In Browser | View PDF |
'
.~
-
,
·.-'
.'
~ ."
1983
Network Products
Handbook
WESTERN DIGITAL
CORPORA
TIO
N
Western Digital
1983 Network Products
Handbook
ii
1983 Network Products Handbook
Western Digital is on the move, growing and expanding to meet
your needs. This handbook, our first dedicated to network
products, underscores our commitment to provide you with advanced, innovative solutions to your communication challenges.
From the early UARTS we pioneered over a decade ago, to the
products described herein, our mission has remained unchanged:
to extend the leading edge in communications technology.
The pin-compatible family of products described in this Handbook
represents the foundation for a growing selection of intelligent,
high level protocol products. These products enable you to quickly
and easily add popular protocols, such as X.25, to your systems.
And pin compatability simplifies system expansion and protocols,
such as local networking. Variations of these off-the-shelf protocol
solutions are also available for custom applications.
In 1983 we'll be expanding this family of devices, and announcing
additional LSI products and board level solutions, as well.
We encourage you to review the information in this handbook and,
when you begin your design, to call our Network Products Hotline
for design assistance at 714/966-7828.
iii
iv
Making The Leading Edge
Work For You.
This handbook is designed for you, the design engineer. It's intended to be a useful tool, to enable you to make a preliminary
evaluation of our products and, later, with samples in hand, to
design our products into your own systems.
The data in these pages have been reviewed by our Marketing,
Engineering, Manufacturing and Quality groups. Now we would like
you to review the information we've provided and tell us how we
can improve it. Please feel free to suggest any changes, additions,
or clarifications that occur to you. And don't hesitate to call to our
attention any sins of omission or commission we may have made.
We're eager to help upgrade the quality of information our industry
provides to its customers. So, please, help us. Direct your comments to:
Director of Corporation Communications
WESTERN DIGITAL CORPORATION
2445 McCabe Way
Irvine, CA 92714
(714) 557-3550
v
vi
Table of Contents
TECHNICAL INFORMATION
WD2501 X.25 Packet Network Interface (LAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
WD2511 X.25 Packet Network Interface (LAPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 31
WD2520 CCID #7 Data Link Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 67
WD2840 Local Network, Token Access Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 87
WD25001 PACKIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 115
RELATED PRODUCTS
TR1402lTR1602 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
TR1863/TR1865 ......................................................................
WD1983 ...........................................................................
WD8250 ...........................................................................
WD2123 ...........................................................................
BR1941 ............................................................................
WD1943IWD1945 ....................................................................
UC1671 ............................................................................
WD1931 ...........................................................................
WD1933IWD1935 ....................................................................
WD1993 ...........................................................................
WD2001IWD2002 ....................................................................
DM1883 ............................................................................
121
123
125
127
129
131
133
135
137
139
141
143
145
APPLICATIONS NOTES
WD2501IWD2511 Applications Note .................. " ..................................
LSI ready to make a mark on packet-switching networks .....................................
WD2511 LSI circuit simplifies packet-network connection ....................................
Local network access tradeoffs .......................................•.................
Token passing cashes in with controller chip ..............................................
Token-access controller minimizes network complexity ......................................
147
173
179
185
189
197
QUALITY I RELIABILITY
Quality/Reliability To Leading Edge Technology ............................................ 203
Burn-In Program Availability ............................................................ 209
PACKAGE OUTLINE
48 Lead Package Ceramic Side Braze .................................................... 211
TERMS & CONDITIONS .................................................................. 213
vii
viii
WESTERN DIGITAL
o
R
p
o
R
A
T
o
/
N
WD2501 X.25 Packet Network Interface (LAP)
FEATURES
• Packet switching controller, compatible with
CCITT recommendation X.25, level 2, LAP
(WD2501)
• Programmable primary timer (T1) and retransmission counter (N2)
• Programmable A-field which provides a wider
range of applications than defined by X.25. These
include: DTE-to-DTE connection, multipoint and
loop-back testing.
• Direct memory access (DMA) transfer: two
channels; one for transmit and one for receive.
Send/receive data accessed by indirect addressing
method. Sixteen output address lines.
• Zero bit insert and delete
• Automatic appending and testing of FCS field
• Computer bus interface structure: 8 bit bidirectional data bus. CS, WE, RE and four input
address lines
• DC to 1.1 MBPS data rate
• TTL compatible
• 48 pin dual in-line packages
• Higher bit rates available by special order
APPLICATIONS
X.25 PACKET SWITCHING CONTROLLER
PART OF DTE OR DCE
PRIVATE PACKET NETWORKS
LINK LEVEL CONTROLLER
GENERAL DESCRIPTION
The WD2501 is a MOS/LSI device which handles bitoriented, full-duplex serial data communications with
DMA, which conforms to CCITT X.25 with programmable enhancements.
The device is fabricated in N-Channel silicon gate
MOS technology and is TTL compatible on all inputs
and outputs.
8BIT DAL
NO CONNECTION
REPLY
cs
RE
WE
CLK
l'ft
ROM
CENTRAL
MICRO·
CONTROLLER
IAO·AI3
MR
DALO
DROO
ORal
i5ACK
AO·A15
iNffi
DAl1
DAL2
A3
DAL3
A2
DAL4
A15
RD
All
DATA/CONTROL BUS
+12V - - - . .
+ 5V ----+GND_
CLK_
MR_
RC
(GND) Vss
IT
PIN ASSIGNMENTS
RD
TO
WD2501 BLOCK DIAGRAM
INTERFACE SIGNALS DESCRIPTION (All signals are TTL compatible.)
PIN NUMBER
SYMBOL
1
2
PIN NAME
No Connection
Reply
3
WE
Write Enable
4
CS
Chip Select
5
RE
Read Enable
6
ClK
7
MR
8-15
DAlO-DAl7
16
RD
RC
Receive Data
Receive Clock
19
VSS
TC
Ground
Transmit Clock
20
21
TD
RTS
Transmit Data
Request-To-Send
22
CTS
Clear-To-Send
23
DROO
DMA Request Out
24
DROI
DMA Request In
25
DACK
DMA Acknowledge
26-41
AO-A15
Address Lines Out
(See front page for
Pin Assignments)
42
VDD
17
18
FUNCTION
leave pin open
An active low output to indicate the WD2501
has either a CS.RE or a CS.WE input.
The data on the DAl are written into the
selected register when CS and WE are low.
Active low chip select for CPU control of I/O
registers.
The contents of the selected register are placed
on DAl when CS and RE are low.
Clock input used for internal timing. Must be
square wave, and greater than 250 KHz.
Initialize on active low. All registers reset to
zero, except control bits MDISC and LINK are
set to 1. DACK must be stable high before MR
goes high.
An 8-bit bi-directional three-state bus for CPU
and DMA controlled transfers.
Receive serial data input.
This is a 1x clockJ!!put, and RD is sampled on
the rising edge of RC. RD changes occur on the
fall i ng edge of RC.
Clock
Master Reset
Data Access Lines
Ground.
A 1x clock input. TD changes on the falling
edgeofTC.
Transmitted serial data output.
An open collector (drain) output which goes low
when the WD2501 is ready to transmit either
flags or data.
An active low input which signals the WD2501
that transmission may begin. If high, the TD
output is forced high. May be hard-wired to
ground.
An active low output signal to initiate CPU bus
request so the WD2501 can output onto the
bus.
An active low output Signal to initiate CPU bus
request so that data may be input to the
WD2501. DRQO and DROI will not be low at the
same time.
An active low input from the CPU in response to
DRQI or DRQO. DACK must not be low if CS
and RE are low or if CS and WE are low.
Sixteen address outputs from the WD2501 for
DMA operation. If the control bit ADRV is 1, the
outputs are TTL drives at all times. If ADRV is 0,
the outputs are three-state, and are HI-Z
whenever DACR is high. (ADRV is in Control
Register #1.)
+ 12VDC power supply input.
Power Supply
2
INTERFACE SIGNALS DESCRIPTION CONTINUED
PIN NUMBER
SYMBOL
43
INTR
Interrupt Request
An active low interrupt service request output,
and returns high when Status Register #1 is
read.
44-47
IAO-IA3
Address Lines In
(See front page for
Pin Assignments)
Four address inputs to the WD2501 for CPU
controlled read/write operation with registers in
the WD2501. If ADRV = 0, these may be tied to
AO-A3. (ADRV is in Control Register#1.)
48
VCC
Power Supply
+ 5VDC power supply input.
PIN NAME
FUNCTION
ORGANIZATION
A detailed block diagram of the WD2501 is shown in
Figure 1.
Mode control and monitor of status by the user's
CPU is performed through the ReadlWrite Control
circuit, which reads from or writes into registers
addressed by IAO-IA3.
Parallel transmit data are entered into the Transmitter
Holding Register (THR), and then presented to the
Transmitter Register (TR) which converts the data to a
serial bit stream. The Cyclic Redundancy Check
(CRG) is computed in the 16-bit CRC register, and the
results become the transmitted Frame Check
Sequence (FCS).
Parallel receive data enter the Receiver Holding
Register (RHR) from the 24-bit serial Receiver
Register (RR). The 24-bit length of RR prevents
received FCS data from entering the RHR (unless
residual bits are received). The receiver CRC register
is used to test the validity of the received FCS. A 3stack FIFO is included in the receiver.
Transmit and receive data are accessed through the
DMA control. Serial data is generated and received by
the bit-oriented controllers.
Internal Control of the WD2501· is by means of three
internal microcontrollers; one for transmit, one for
receive, and one for overall control.
8 BIT OAL
MICRO
C
I/O
REGISTERS
16x 8
0
IAO·IA3
N
T
R
REPLY
0
L
L
E
R
OMA
A
0
0
R
E
S
S
OMA
CONTROL
LOGIC
E
S
OACK
AO·A15
+12V_
+5V_
TRANSMITTER
MICRO·CONTROLLER
MR CLK_
GNO-
RO
TO
Figure 1.
WD2501 BLOCK DIAGRAM - DETAILED
3
FRAME FORMAT
The WD2501 performs "bit-oriented" data communications control. According to the bit-oriented
procedures (HDLC, SDLC, ADCCP), each serial block
of data is called a frame.
Each frame starts and ends with a Flag (01111110). A
single flag may be used both as the closing flag of
one frame and the opening flag of the next frame. In
between flags, data transparency is provided by the
insertion of an 0 bit after all sequences of 5 contiguous 1 bits. The receiver will strip the inserted 0
bits. The last 16-bits before the closing flag is in the
Frame Check Sequence (FCS). Each frame also
includes address and control fields (A and C fields).
The FCS calculation includes all data between the
opening flag and the first bit of the FCS, except for
O's inserted for transparency. The 16-bit FCS has the
following characteristics:
Polynomial = X16 + X12 + X5 + 1
Transmitted Polarity -Inverted
Transmitted Order -High Order Bit First
Preset Value
-AliI's
I~
After the frame is received, if there were no errors,
then the remainder in the CRC register (internal in the
WD2501) will be:
1111000010111000 FOB8
The WD2501 generates and tests the Flag, FCS, AField, C-Field, and performs zero bit insertion and
deletion. According to the X.25 protocol, there are
three types of frames: supervisory (S-frame), unnumbered (U-frame), and information (I-frame).
The WD2501 performs frame level (level 2) link access
control. All S- and U-frames are automatically
generated and tested by the WD2501. The user need
only be concerned with the I-frames, which are
packets.
The WD2501 will transmit contiguous flags for interframe time fill.
~I
I-FRAME (PACKET)
IFLAG
~
ADDRESS CONTROL
X.25LEVEL2
APPENDED
I-FIELD (PACKET DATA)
PACKET
CONTROL
INFORMATION
X.25LEVEL3
·1
USER DATA
FLAG
FCS
~~6~~l~EN4X.25LEVEL2~
--~.-----
DMA ACCESSED
•
APPENDED
BY
BY
WD2501
WD2501
X.25 MODE
NOTE: X.25 Level 1, is the Physical Interface
4
MODEM
CONTROLS
CPU BUS
(DTR, DSR, ETC.)
00
~I
OJ
::j
0
»
r
~I
~I gl
~
~I ~I r"
()
<;:>
~
(..)
~
DRao
TC
TD
DRal
MEMORY
-
r-
WD2501
DACK
CTS
RTS
AO·A15
16
RC
LEVEL 1
INTERFACE
MODEM
RD
1 1
b
+ 12VDC + 5VDC GND
Figure 2.
SYSTEM CONNECTION
Control, status, and error bits will be referred to as
CR, SR, or ER, respectively, along with two digits. For
example, SR16 refers to status register #1 and bit 6,
which is "XBA."
II. PROGRAMMING THROUGH REGISTERS
The WD2501 is controlled and monitored by sixteen
I/O registers.
REGISTER DEFINITION
REG
#
IA3
1A2
IA1
lAO
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
CRO
CR1
*SRO
*SR1
*SR2
*ERO
7
0
0
1
1
1
1
0
1
*CHAIN MONITOR
*RECEIVED C-FIELD
8
9
1
1
0
0
0
0
0
1
T1
N2/T1
A
B
C
D
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
TLOOKHI
TLOOKLO
CHAIN/LIMIT
NOT USED
E
F
1
1
1
1
1
1
0
1
XMT COMMAND "E"
XMT RESPONSE "F"
0
1
2
3
4
5
6
REGISTER
REGISTER
GROUPING
OVERALL CONTROL
AND
MONITOR
RECEIVER
MONITOR
TIMER
*CPU READ ONLY. (Write Not Possible)
NOTE:
1. Registers Eand F should be set-up only with MDISC = 1.
5
DMASET-UP
"A" FIELD
CONTROL, STATUS, ERROR REGISTERS
BIT #
4
3
2
1
0
READY
BUT
IDLE
ACTIVEI
PASSIVE
LOOP
TEST
2RAMT
RECR
MDISC
0
0
ADRV
0
0
0
SEND
NA2
NA1
NAO
RNRR
NB2
NB1
NBO
RNRX
SR1
1PKR
1XBA
1ERROR
0
NE2
NE1
NEO
0
SR2
T10UT
IRTS
REC
IDLE
0
0
0
0
ERO
ER07
EROS
ER05
ER04
ER03
ER02
ER01
EROO
CR02
CR01
CROO
RAMT
RECR
MDISC
REGISTER
7
6
5
CRO
0
0
CR1
0
SRO
LINK
1 Causes Interrupt (INTR Goes Low).
2 RAMT is used to initiate a self-test feature (see section on Self-Test).
For normal operation, program to O.
REGISTER
CR07
CROS
CRO
o
o
CONTROL REGISTER 0
CR05
CR04
CR03
READY
BUT
IDLE
ACTIVEI
PASSIVE
BIT
LOOP
TEST
DESCRIPTION
CROO
MDISC is a mandatory disconnect command. MDISC will cause a logical disconnect in
the link. No DMA accessed data will be transferred as long as MDISC = 1. After Master
Reset (MR pin transition from low to high), MDISC will be set. The WD2501 will neither
transmit nor accept received data until MDISC = O.
CR01
This bit is RECR which defines the CPU's receiver buffer as initially Ready (CR01 = 1). If
RECR = 1, this bit indicates that the WD2501 may begin receiving I-frames. (See SROO)
CR02
RAMT - This bit activates an internal register test. See Section on Self tests for
description.
CR03
The LOOP TEST bit will connect the transmitted data output to the receiver input. The
receiver input pins RD and RC are logically disconnected. The "E" and "F" registers of
the A-field should be equal.
CR04
This bit will cause the WD2501 to initiate link set-up if CR04 = 1, or to wait for a link-setup from the remote device if CR04 = O.
CR05
RBI bit. For compatibility with the 2511, let RBI =
CR7,CR6
Unused control bits, like CR07, should be O.
6
o.
REGISTER
CR1
I
I
I
I
CR17
0
CR16
0
I
CONTROL REGISTER 1
CR15
CR14
CR13
0
J
I
I
I
I
ADRV
0
I
I
CR12
0
I
I
CR11
0
I
I
CR10
SEND
N
en
DESCRIPTION
BIT
o
.....
The SEND bit (CR10) is used to command the WD2501 to send the next packet or
packets. If SEND
1, the WD2501 will read from TLOOK the BRDY bit of the next
segment for transmission. If BRDY
0, the WD2501 will clear SEND and no action
1, the WD2501 will then read TSADR and TCNT, followed by the
occurs. If BRDY
transmission of that buffer: After transmission, the WD2501 clears BRDY of the segment
just transmitted, and reads BRDY of the next segment. If 1, the next segment is transmitted. If 0, the SEND bit is cleared, and transmission of packets is stopped. As a matter
of good practice, the CPU should set SEND each time one of the BRDY bits is set.
CR10
=
=
=
CR11-13
Unused bits, write in O's.
CR14
0,
The ADRV bit (CR14) is the control for the 16 bit output addresses (AO-A 15). If ADRV
the outputs are tri-state and are in HI-Z, except when DACK goes low. If ADRV
1, the
outputs are always low impedance (TTL), and are high-level when DACK is high.
CR15-17
Unused bits, write in O's.
=
REGISTER
SRO
I
I
SR07
I
I
NA2
SR06
NA1
I
I
STATUS REGISTER 0
SR04
SR03
SR05
NAO
I
I
RNRR
BIT
SROO
I
I
NB2
I
I
SR02
NB1
I
I
SR01
NBO
I
I
=
SROO
RNRX
DESCRIPTION
RNRX. An RNR has been transmitted, or will be at next opportunity. The CPU should set
RECR, when receive buffers are available.
SR03-SR01
NB2-NBO. Next block to be transmitted.
SR04
RNRR. This bit is set when an RNR frame is received. Once set, it is cleared when an RR,
REJ, or UA is received.
SR07-SR05
NA2-NAO. Next block of transmitted data to be Acknowledged.
REGISTER
SR1
I SR17 I
I 1PKR I
STATUS REGISTER 1
SR14
SR15
SR13
SR16
I
1X BA
11ERROR
I
I
I
BIT
SR10
I
o
NE2
I
SR12
I
NE1
I
I
SR11
I
SR10
NEO
I
0
DESCRIPTION
o
SR13-SR11
NE2-NEO. Next Expected packet segment number of RLOOK.
SR14
o
SR151
The ERROR bit indicates: 1) An error has occurred which is not recoverable by the
WD2501, or 2) A significant event has occurred. The "Significant events" are: change in
link status (link-up or down), the WD2501 is progressing to the next segment in a
chained receive buffer, or one direction of the link has been reset.
The exact nature of the reason for the ERROR bit is given in ERO.
The XBA bit means that a previously transmitted Block, or Blocks, have been
acknowledged by the remote device. Upon acknowledgement, the ACK'ED bit is set to
"1" for each segment in TLOOK which was acknowledged.
SR171
The PKR bit stands for Packet Received. This means that a packet has been received
error-free and in correct sequence according to the received N (S) count. The data (I-field)
has been placed in the CPU's RAM memory. NE is advanced.
NOTE 1: The three interrupt-causing bits are SR17, SR16,
and SR15. Any of the three will cause an interrupt
7
:ec
request (INTR goes low). After SR1 is read, all
three bits are reset to 0, and INTR returns high.
REGISTER
SR27
SR26
SR2
T10UT
IRTS
STATUS REGISTER 2
SR24
SR23
SR2S
REC
IDLE
0
0
SR22
SR21
SR20
0
0
LINK
DESCRIPTION
BIT
SR20
If the link is established, LINK = O.lf the link is logically disconnected, LINK = 1.
SR24-21
Unused Bits - 0
SR25
REC IDLE indicates that the WD2501 has received at least 15 contiguous 1's.
SR26
IRTS stands for the Internal Request-To-Send bit, and indicates that the transmitter is
attempting (successful or not) to send either data or fla~f the RTS pin is not tied to
ground orWIRE-ORED with another signal, then IRTS = RTS.
SR27
T10UT bit means that timer T1 has timed-out. This bit returns to 0 when T1 is re-started.
When T10UT = 1, T1 is not running. NOTE: This bit could be a 1 for a few microseconds in between intervals when T1 stops and is restarted.
ERROR REGISTER (ERO)
ER07 ER06 EROS
0
0
0
ER01 = ROR
ER02 = TUR
ER04 = RLNR
0
0
ER04
ER03
ER02
ER01
EROO
0
1
0
0
0
0
0
0
1
0
LINK is up. (Was down)
Received DISC while LINK up, or partially
up.
0
0
1
0
0
0
0
0
1
0
DISC sent, since SARM sent N2 times
without UA. (Note 3).
DISC sent, REC IDLE forT1xN2.
1
CHAIN STATUS
0
1
1
0
0
ERoo = GNCS
ER01 = CNR
LINK RESET RECEIVED if ER05-EROO = 000000
LINK RESET TRANSMITTED if ER05-EROO = non-zero
EROO similar to W
ER01 similar to X
ER02 similar to Y
ER03 similartoZ
ER05 means received F = 1, but did not send P = 1
ER04 - I-frame was sent N2 times without acknowledge
1
1
COMMAND REJECT
RECEIVED if ER05-EROO = 000000
TRANSMITTED if ER05-EROO = non-zero
ERoo = W
ER01 = X
ER02 = Y
ER03 = Z
Unassigned bits are always O.
8
TERMS USED IN ERROR REGISTER
GNCS
RLNR
ROR*
TUR*
CNR
Going to Next Chain Segment.
=
RLOOK Not Ready. REC ROY bit of next segment is 0, but RECR
1. This interrupt will
not occur if RECR = O.
Receiver Over-Run. The Receiver Register (RR) had a character to load into the FIFO, but
the FIFO was full.
Transmitter Under-Run. The Transmitter Register (TR) needed a character from the
Transmitter Holding Register (THR), but the THR was not ready. The frame being transmitted is ABORTed.
Next Chain Segment of Receiver was Not Ready.
* TUR and ROR means that the bit rate clocks (TC and RC) are either too fast for the WD2501, or the DACK
response to ORal and DROO is too slow, or both.
w, X, Y, Z OF CMDR
TLOOK
A command reject (CMDR) contains a three byte
I-field. The first byte is the rejected frame control
field. The second byte contains the current N (S) and
N (R) counts of the terminal reporting the rejection
condition. The third byte contains W-X-Y-Z-Z1-0-0-0
where W is the LSB.
W set to 1 indicates that the control field received
and returned in the first I-frame byte was invalid.
X set to 1 indicates the rejected frame contained an
I-field which is not permitted with this command. Bit
W must be set to 1 when X = 1.
Y set to 1 indicates the I-field exceeded the total limit
established. Y is mutually exclusive with W.
Z set to 1 indicates the control field contained an
invalid N(R). Z is mutually exclusive with W. Since the
WD2501 is LAP, only, a CMDR will not be sent to an
invalid N (R). A link reset (SARM) is sent. Thus, Z is
not used.
Upon receiving a CMDR, the WD2501 will place the 3
byte I-field in memory by DMA, just as if the CMDR
were a packet. However, NE is not advanced, and the
next received packet will over-write the CMDR I-field.
Therefore, the CPU should "quickly" use the 3 byte
I-field in the received CMDR.
RLOOK
These tables contain address and control
formation for individual send/receive packets.
in-
To access TLOOK and RLOOK only the starting
address of TLOOK is loaded into the WD2501 in
registers A' and B'.
REG A
A15 A14 A13 A12 A11 A10 A9
A8
REG B
A7
AO
A6
A5
A4
A3
A2
A1
AO-A1516 bit TLOOK starting address
The TLOOK and RLOOK tables are each divided into
8 segments and each segment contains 8 bytes.
Figure 3 illustrates the segmentation of TLOOK and
RLOOK. Figure 5 and 6 illustrate the contents of a
single TLOOK and RLOOK segment.
In transmit, the WD2501 will have read from TLOOK
the starting address and length of the first packet to
be transmitted. The WD2501 will automatically
transmit the flag, address, and control fields. Next,
the information field data will be transmitted using
DMA from the "SEND #0 PACKET" memory. At the
end of the information field, the WD2501 will
automatically send the FCS and closing Flag. The
WD2501 will then move on to the next packet.
If retransmission of one or more (up to seven)
packets becomes necessary, the WD2501 will automatically retrace the previous transmissions through
the TLOOK table. The user's CPU software does not
become involved in the retransmission. However, an
ERROR COUNTER is incremented. (See Error
Counter Section.)
To receive, each frame is checked for correct address
and FCS fields and for type of control field. If the
frame is a packet, the information field is placed in
the assigned memory location in a method similar to
that used in transmit. After the packet is received
error-free and in proper N(S) sequence count, an
When the WD2501 transmits a CMDR, the command
reject condition is entered. Only a received SARM or
DISC will clear this condition. If any other command
is received, the WD2501 will re-transmit the CMDR.
However, valid responses received will be acted upon
accordingly. Also, the WD2501 may transmit packets
while in the command reject condition.
MEMORY ACCESS METHOD
The WD2501 memory access is accomplished by the
use of DMA and two look-up tables. These tables are
set-up to allow up to 71-frames to be outstanding in
each direction of the communications link. The lookup tables are divided into two areas (T-LOOK and
R-LOOK) and are in memory external to the WD2501.
9
Figure 4 shows a "store-and-forward" example that is
useful in a network node.
interrupt is generated, and the WD2501 is ready for
the next packet which will be placed in the next
location.
o L..-------.~I
1-------1
'--_,,",--_...J
r
CNT
#0
SEND
PACKET #1
(SECOND PART)
SEND
PACKET
#1
(FIRSTPARn
FOR THIS EXAMPLE,
TCNT #1 IS
GREATER THAN
LIM. THUS,
SECOND PART
OF #1 IS
CHAINED.
XFRADR
--r
R~~~y~R
LIM
1
BUFFER
~_I----L
XFR ADR
ERROR
COUNTERS
XFR ADR
Figure 3. MEMORY ACCESS SCHEME
r------ MEMORY-"'I
I
-- -- - - - -
LO~K~UP
I
TABLE
TLOOK
- -
-
-
-
-C;B -
-
-
---,
LOOK·UP
TABLE
o
TLOOK
I
I
3
I
t-----:..,
1-_ _ _ _4..,
I
I
7
RLOOK
I
3
I
I
!------4--i
I
1------:..,
I
I
L __
I
RSADR #3
'- ~
TSADR~
:
I
B
;
T
3
"1 ~~~~ I
RCNT #3
RECEIVED
6~R~
7
TCNT #6
B
RLOOK
4
:
/------ ~"~- ------~=- ~ I
"'--W-D-2-5--01-L,
CH A
+
4
C
I
I
1/
_.....
I-----;..,) cr B~~~~R "
I
I
/_-- _
SERIAL
RECEIVE
CHANNEL A
Afte, the Data Buffe, Is ,"ool'ed by CH A, the length (RCNT) is WD2501
in RLOOK segment #3. The CPU interrogates the packet header
CH B
(at the beginning of the Data Buffer), and concludes that the _
buffer must be send out of CH B. RSADR, RCNT, and the
residual information are transferred from #3 segment to next
SERIAL
available TLOOK segment in CH B which is #6 in this example.
TRANSMIT
CHANNELB
Figure 4. STORE·AND·FORWARD EXAMPLE
10
TLOOK AND RLOOK
After receiving an error-free packet with correct N(S),
the WD2501 will, in order: 1) Set FRCML (Frame Complete), clear REC RDY, and store received residual
count. 2) Store the received length, in characters, of
the I-field in RCNT HI and RCNT LO. 3) Advance the
NE count, and generate a packet received interrupt.
4) Acknowledge the received packet at the first
opportunity.
Figures 5 and 6 detail the individual segments for
TLOOK and RLOOK.
BRDY means that the transmit buffer is ready. The
WD2501 will send the block only after the CPU makes
1. (BRDY is used in conjunction with the
BRDY
SEND bit.) At the completion of the transmission, the
WD2501 will make BRDY = 0, and then read the
BRDY of the next segment.
=
The addresses (TSADR and RSADR) are 16-bit binary
addresses. HI represents the upper 8-bits and LO
represents the lower 8-bits. The counts (TCNT and
RCNT) are 12-bit binary numbers for the number of
characters in the I-field.
After transmitting a packet, an acknowledgement
must be received from the remote device. The
acknowledgement is contained in the received N(R)
count of an I-frame or S-frame. Upon acknowledgement, the WD2501 will make ACK'ED = 1, and
generate a block-acknowledged interrupt. Before
assigning a new block to a segment in TLOOK, the
CPU must make sure that the previous block which
used that segment number has been acknowledged.
TSADR is the starting address of the buffer to
transmit, and TCNT is the binary count of the number
of bytes to transmit.
RSADR is the starting address of the receive buffer.
After successfully receiving the packets, the WD2501
will write the value of RCNT which is the binary
length of the received packet.
REC RDY informs the WD2501 that the receive buffer
is ready. The WD2501 will not receive a packet into a
buffer referenced by a particular segment until REC
RDY
1. If the WD2501 progresses to a segment
which has REC RDY = 0, an error interrupt will be
generated.
Whether the WD2501 accesses a look-up table or a
memory block, a DMA Cycle is required for each
access.
=
Figure 5. TLOOK SEGMENT
BIT#
BYTE # IN
SEGMENT
7
6
5
4
3
2
1
0
1
ACK'ED
NS
NS
NS
NS
NS
NS
BRDY
2
TSADR HI
3
TSADR LO
4
NS
SPARE
TCNT HI
5
TCNT LO
6
SPARE FOR USER DEFINITION
7
SPARE
8
SPARE
= Not Spare
11
:i:
c
I\)
en
o
.....
Figure 6. RLOOK SEGMENT
BITH
BYTEHIN
SEGMENT
7
6
5
4
3
2
1
0
1
FRCML*
NS
NS
NS
RES2
RES1
RESO
REC
RDY
2
RSADR HI
3
RSADR LO
4
NS
=
NOT SPARE
RCNT HI
5
RCNT LO
6
SPARE FOR USER DEFINITION
7
SPARE
8
SPARE
Not Spare (NOTE: The "not spare" bits may be either 1 or 0).
* FRCML
=
Frame Complete
The control bits in TLOOK(BRDYand ACK'ED) and in
RLOOK (FRCML and REC RDY) define various states
for each segment. These states are shown below:
TLOOK STATES
ACK'ED
a
a
STATE
BRDY
1
1
a
a
1
1
Ready To Transmit (CPU set BRDY, cleared ACK'ED)
*Transmitted and Awaiting Acknowledge (WD2501 cleared BRDY)
Received Acknowledge (WD2501 set ACK'ED)
This state not allowed
* State 0-0 could also occur whenever there is no data ready to send.
CPU
CLEARS
ACK'ED
CPU SETS
BRDY
RECEIVED
ACKNOWLEDGE
1·0
CPU CLEARS ACK'ED
AND SETS BRDY
DATA HAS BEEN
SENTWAITING
FOR ACKNOWLEDGE
0·0
WD2501 SETS
ACK'ED
WD2501 CLEARS
BRDY
TLOOK SEGMENT STATE FLOW
2. At start-up, the CPU should set all ACK'ED bits.
(Since this would only be a start-up procedure, this
would not violate the "deadly embrace" rule.)
Notice that in a TLOOK segment, the 0-0 state could
have two meanings. Due to control internal to the
WD2501 , this will not pose an ambiguity to the
WD2501. However, if it is a difficulty to the CPU, the
CPU could do two things:
As another alternative, the CPU could use one or
more of the SPARE bits for additional state control.
1. Avoid ever entering the "NO DATA TO SEND"
In the "WAITING FOR ACKNOWLEDGE" state, one
or more re-transmissions could occur:
12
REG
=C
CHAIN
~
LIMIT
Bit
7
I
Bit
6
I
LIMIT
Bit
5
1
Bit
4
Bit
Bit
2
I
3
I
Bit
1
Bit
0
a XFR ADR on the receiver, there will be an Error
Interrupt code 42 if XRF ADR = all O's. Otherwise,
there will be an Interrupt code 41 which is a status
indication that the WD2501 is going to the next
segment.
CHAINING
The WD2501 includes a chained·block feature which
allows the user more efficient use of memory par·
ticularly in situations where the maximum packet
size is much larger than the average packet size.
On the receiver, Register 6 upper 4 bits gives a status
of which chain segment is currently being used.
Register C is used to program the chaining feature.
The upper 4 bits define CHAIN which is the number
of chain segments allowed in addition to the first
segment. (If this feature is not used, make CHAIN
aIlO's).
The transmitter chaining works just like the receiver
with the following exceptions:
The lower 4 bits of Register C defines LIMIT which is
the size of the buffer in multiples of 64 bytes in·
cluding the transfer address (XFR ADR). If LIMIT is
0000, the size is 64. For 0001, the size is 128, and
soon.
2. There is no interrupt when going from one
segment to another.
1. XFR ADR
not ready.
3. There is no status of the current segment being
used.
For example, suppose that the LIMIT defines a
segment size of 128 and that CHAIN defines 8 ad·
ditional segments in addition to the first. (Note:
Register C would be hex 81 in this example.) When
126 bytes of I·field have been received, the WD2501
will take the next two bytes as a transfer address
(XFR ADR) pointing to another segment. At the end
of that segment is another XFR ADR, and so on, up to
a maximum of 9 total segments.
The total receiver limit is given by the expression:
TOTAL RECEIVER LIMIT
= (64 X (1 + LIMIT) - 2) X
(1 + CHAIN)
Also, note that the transmitter and receiver counts
are modified by 2 for each time a chain boundary is
crossed. For example, if LIMIT = 0001 (segment size
= 128 including XFR ADR), and if an I·field of 270
bytes is to be transmitted, then there will be two
times that a chain boundary is crossed. The TCNT
must be made 274 to send 270 bytes. The same is
true for RCNT.
On the receiver, a XFR ADR of all O's will mean that
the next segment is not ready. If the WD2501 reaches
RLOOK STATES
FRCML
=- all O's will not indicate next segment
REC ROY
STATE
0
1
Ready To Receive (CPU set REC RDY, cleared FRCML)
1
0
Received Packet (WD2501 set FRCML, cleared REC RDY)
0
0
Not Ready (CPU cleared FRCM L)
1
1
This state not allowed
CPU SETS
REC ROY ~:_ _ _____
CPU
CLEARS
FRCML""
CPU CLEARS
FRCML, AND
SETS
REC ROY
READY TO
RECEIVE
0·1
W02501 CLEARS REC ROY
AND SETS FRCML
RLOOK SEGMENT STATE FLOW
13
:eC
I\)
~
-a.
"DEADLY EMBRACE" PREVENTION
ERROR COUNTERS
A "deadly embrace" can occur when two processors
reach a state where each is waiting for the other. In
this case, the two processors are the user's CPU and
the micro-controller inside the WD2501. Therefore, to
prevent the "deadly embrace," the following rule is
obeyed by the WD2501 and should also be obeyed by
the user's CPU. This rule applies to TLOOK, RLOOK
and to the 1/0 registers. The Error Counters do not
apply to this rule.
Following contiguously after RLOOK are six a-bit
error counters. The WD2501 will increment each
counter at the occurrence of the defined event.
However, the WD2501 will not increment past 255 (all
1's). The CPU has the responsibility of clearing each
counter. The first counter past RLOOK is #1, etc.
ERROR
COUNTER
RULE: If a bit is set by the CPU, it will not be set
by the WD2501, and vice versa. If a bit is
cleared by the WD2501, it will not be
cleared by the CPU, and vice versa.
* Received Frames with FCS Error
(includes frames ABORTed in the
I-field).
2
As an example, the BRDY bit in the TLOOK segments
is set by the CPU, only, but cleared by the WD2501,
only.
3
TLOOK AND RLOOK POINTERS
4
There are three 3-bit counters for the status of the
segments in TLOOK and RLOOK. Status Register #0
(SRO) contains counters NA and NB which are used
in conjunction with TLOOK. NB is the segment
number of the next block to be transmitted, and is
advanced at the end of each block transmission. NA
is the value of the segment of the next block which
will be acknowledged. If all transmitted blocks have
been acknowledged, then NA = N B.
5
6
NB
NE = Next Expected to be Received
T1
ran-out
Number of I-Frame Retransmissions due to 11 completing
* REJ Frames Received
REJ Frames Transmitted
RECEIVED C·FIELD
Register 7 is the C-field of the last received frame,
provided the A-field of the frame was equal to either
register E or F, the FCS was good, and the frame
contained 32 or more bits, and the WD2501 is not
waiting for a SARM or DISC in response to a transmitted CMDR.
The WD2501 will send a bits per character, only. Also
all transmitted frames will be integer multiples of
bytes.
The WD2501 may receive a packet with, or without,
an integer multiple of bytes. The "RES" bits in the
RLOOK tables shows the number of residual bits.
The residual bits occupy the lower portion of the last
received character.
0
0
1
1
0
0
1
1
times
OTHER 110 REGISTERS
VARIABLE BIT LENGTH
AND RESIDUAL BITS
0
0
0
0
1
1
1
1
* * Number of
(completed)
The Error Counters are accessed by the WD2501
transmitter DMA channel. Therefore, if multiple
errors are received while the WD2501 is transmitting
a long frame, only the last error will be counted. The
only Counters which could miss counts because of
this are Counters #1, #2, and #5. The error Counters
are incremented only when the link is up (LINK = 0).
= Next to be Acknowledged
= Next Block to be Transmitted
RES2 RES1
Received Short Frames (less than
32-bits)
*These counters are incremented only if the
received A-field is equal to either Register E or F.
* * Incremented only when attempting to transmit a
command.
In SR1 is a 3-bit counter, NE, used with RLOOK. NE is
the value of the segment number where the next
received packet will be placed.
NA
COUNT
RESO
Received Residual Bits
0
1
0
1
0
1
0
1
0
7
6
5
TIMER
Registers a and 9 define a 1O-bit timer (T1), and a 6-bit
Maximum Number of Transmissions and Retransmissions counter (N2).
REGISTER
716151413121110
N2
9
4
MSB
3
2
1
MSB = Most Significant Bit
LSB = Least Significant Bit
14
LSB
T1
a
LSBIMSB
T1 provides the value of a delay in waiting for a
response and/or acknowledgement. The delay is the
binary count of clock CT where:
CT =
Once the CPU establishes T1 and N2, there is no
need to write into T1 and N2 again unless a master
reset (MR) has occurred, there is a power loss, or the
CPU needs to change T1 or N2. If a time-out occurs,
the WD2501 will still retain T1 and N2.
16,384
ClK
The conditions for starting, stopping, or restarting T1
are shown below: ("Re-start" means starting T1
before it ran-out).
Thus, if ClK = 1 MHz, then T1 may be set in increments 16.384 milliseconds, to a maximum delay
of 16.78 seconds. All ones in T1 is maximum delay.
START T1
RE-START T1
1. * I-frame sent if T1 not already
in progress due to previous 1frame
2.
3.
-
4.
Receiver Idle (REC IDLE
RR or RN R sent because
RRT1 = 1
to some, but not all, I-frames.
Acknowledgement received for
all I-frames.
* RNR received while link up.
SARM or DISC sent. (N2
restarted at first occurrence)
5.
* Acknowledgement received
STOPT1
-
UA Received for SARM, UA or
OM Received for DISC.
= 1)
Detect REC IDLE
=0
-
* N2 is restarted where shown by asterisk (*).
NOTE: Reason 4 and 5 (above) are overridden by reasons 1, 2 and 3. On reason 2, T1 is stopped if the received
RNR acknowledged all outstanding packets.
"A" FIELD REGISTERS
Registers E and F provide a programmable A-field.
This allows the WD2501 to be a super-set of the X.25
document. That is, the WD2501 can handle a wider
range of application than the DTE-DCE links defined
in X.25. These wider ranges include: DTE-to-DTE
connection, multipoint, and loop-back testing.
If the WD2501 is strictly in an X.25 DTE-DCE link, use
the values shown below:
DTE Register E = 01
Register F = 03
DCE Register E = 03
Register F = 01
If performing a loop-back test either internal
(CR03 =1) or external, registers E and F should be the
same.
15
v~
LAP PROCEDURE
The individual commands and responSes are shown
in Figure 7.
Tha Link Access Procedure (LAP) is described in
CCITT Recommendation X.25 as the Level 2 protocol
for the Asynchronous Response Mode (ARM). LAPB
is the Level 2 protocol for the Asynchronous
Balanced Mode (ABM). This section describes how
the WD2501 performs LAP. (The WD2511 performs
LAPB.)
The Poll bit (P) is used in conjunction with Time-Out
Recovery. Time T1 is started at the beginning of a
transmitted command provided it has not been
previously started. If T1 runs out (completes), the
command will be retransmitted with P = 1. If T1 runs
out again, the command will again be retransmitted,
with P= 1 up to N2 times. At N2 + 1, an error interrupt will occur. If the command was an I-frame, the
WD2501 will reset the link by transmitting a SARM. If
a SARM (either for link set-up or link reset), the
WD2501 will send a DISC, If a DISC, the WD2501 will
continue to send a DISC.
Zero bit insertion/deletion, use of flags and FCS are
part of Level 2, and have been discussed in this
document.
The DTE is the Data Terminal Equipment and the DCE
is the Data Circuit Termination Equipment, and is the
network side of the DTE-DCE connection. X.25
defines the protocol in the DTE-DCE link. The link is
symmetric iii that both the "primary" and "secondary" functions are included within the DTE and
DCE. Commands and responses are differentiated by
the A-field as shown below:
If an RN R has been received, and at least one packet
needs transmission, the WD2501 will send the next
packet at T1 intervals with P = 1. As long as subsequent transmissiohs of the next packet receives an
RNR, the WD2501 will not stop after N2 times.
DCE
A·FIELD ADDRESS
PRIMARY
A (03)
SECONDARY
8(01)
DTE
COMMAND
SECONDARY
RESPONSE
COMMAND
PRIMARY
RESPONSE
SYMMETRIC DTE-DCE LINK USED IN LAP
Figure 7. LAP COMMANDS AND RESPONSES
(Bit 0 is transmitted first)
Only the CMDR and I-frame contain I-fields.
NOTE:The WD2501 will accept a DM response to a transmitted DISC.
FRAME TYPE
COMMAND
RESPONSE
81TH
7
6
5
4
3
2
0
1
INFORMATION
(I)
I-FRAME
OR PACKET
UNNUMBERED
(U)
SARM
0
0
0
P
1
1
1
1
DISC
0
1
0
P
0
0
1
1
UA
0
1
1
F
0
0
1
1
CMDR
1
0
0
F
0
1
1
1
SUPERVISORY
(S)
16
N(S)
P
N(R)
0
RR
N(R)
F
0
0
0
1
RNR
N(R)
F
0
1
0
1
REJ
N(R)
F
1
0
0
1
TRANSMISSION OF ABORT
An ABORT (a a followed by at least seven 1's) is
transmitted to terminate a frame in such a manner
that the receiving station will ignore the frame. There
are three conditions which will cause the W02501 to
transmit an ABORT:
1. An ABORT is sent when there is a Transmitter
Under-Run
2. While transmitting a packet, if a REJ S-frame is
received, the packet is ABORTed.
3. If T1 times-out while a packet is being transmitted,
the packet is ABORTed. Caution: If a packet is
longer (in time) than T1, the packet will always be
ABORTed.
the loop-Back Test. This test provides a means to
check the other four registers.
The contents of Register A are placed in two even
internal registers, and the contents of Register B in
two odd internal registers. The four registers are then
added together without carry and the result is placed
in Registers 2, 5, 6 and 7. This test is initiated when
RAMT (CR02)
1. Use the followi ng procedure:
1. Set-up Registers A and B.
2. Set RAMT.
3. Wait at least 50 times the ClK period.
4. Read Registers 2,5, 6 and 7.
=
To repeat the test for new values in Registers A
and B:
5. Clear RAMT.
6. Wait at least 100 times the ClK period.
7. Go back to step 1.
SELF-TESTS
There are two self-test features: 1) Internal RAM
Register Test and 2) Loop-Back Test. Both tests are
suitable for manufacturing testing, user incoming
inspection testing, or system diagnostics and
trouble-shooti ng.
LOOP-BACK TEST
The loop-back may be internal (CR03 = 1) or external
(CR03 = 0). Of course, if external, RO and TO must be
tied together either directly or remotely.
INTERNAL RAM REGISTER TEST
There are eleven 8-bit registers internal to the
W02501 which are not directly accessible by the
user's CPU. Seven of these registers can be tested by
=
If CR03
1, TO is internally tied to RO, and the pin at
RO (16) is internally disconnected. Also, TC is internally tied to RC, and the pin at RC (17) is internally
disconnected.
17
:ec
N
(J1
o...I.
WD2501 ELECTRICAL SPECIFICATIONS:
ABSOLUTE MAXIMUM RATINGS:
Voltages referenced to VSS
High Supply Voltage (VOO) . . . . . . . . . .. - 0.3 to 15V
Voltage at any Pin .................. - .03 to 15V
Operating Temperature-Range ...... O°C to + 70°C
Storage Temperature Range .~ ... : ·:... ::55°C to·+ 125°C
NOTE:
Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits
is not intended and should be limited to those
conditiens specified in the DC Electrical charac ..
teristics.
Operating DC Characteristics: VSS
SYMBOL
100
ICC
VOO
VCC
VIH
VIL
VOH
VOL
ILH
IOZH
IOZL
= OV, VCC = 5.0V ±
PARAMETER
VOO Supply Current
VCC Supply Current
High Voltage Supply
Low Voltage Supply
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Source or Sink
Input Leakage High
Impedance
Output Leakage High
Impedance
MIN
11.4
4.75
2.4
.25, VSS
= 12.0V ±
MAX
UNIT
20
200
12
5
70
280
12.6
5.25
0.4
10
mA
mA
V
V
V
V
V
V
uA
10
uA
10
uA
0.8
18
= 0° to 70°C
TYP
2.8
t
.6V TA
CONDITIONS
10
10
= -0.1mA
= 1.6mA
= VCC
Vin = VSS
Vin
AC Timing Characteristics: VCC
SYMBOL
= 5V ±
.25; VDD
PARAMETER
= RV ±
MIN
.6V, VSS
= OV, TA = 0° to 70°C
TYP
MAX
UNIT
2.0
MHz
CONDITIONS
ClK
Clock Frequency
RC
Receive Clock Range
0
MHz
Note 3, 4
TC
Transmit Clock Range
MHz
Note 4
0.5
MR
Master Reset Pulse Width
0
1"0
TAR
Input Address Valid to RE
0
TRD
Read Strobe (or DACK
Read) to Data Valid
375
ns
THD
Data Hold Time From Read
to Strobe
80
nS
THA
Address Hold Time From
Read Strobe
80
ns
TAW
Input Address Valid to
Trailing Edge of WE
200
nS
Note 1,2
mS
nS
Note 5
TWW
Minimum WE Pulse Width
200
nS
TDW
Data Valid to Trailing Edge
of WE or Trailing Edge of
DACK for DMA Write
100
nS
TAHW
Address Hold Time After
WE
80
nS
TDHW
Data Hold Time After WE or
After DACK for DMA Write
100
nS
TDA1
Time From DROO (or DROI)
to Output Address Valid if
ADRV = 1
80
nS
TDAO
Tjme From DACK to Output
Address Valid if ADRV = 0
400
nS
Note 5
TOD
Time From leading Edge of
DACK to Trailing Edge of
DROO (or DROI)
400
nS
Note 5
TOAH
Output Address Hold Time
From DACK
100
nS
TDMW
Data Hold Time From DACK
For DMA Read
100
nS
TRP1
REPLY Response Time
(leading edge)
240
nS
Note 5
TRP2
REPLY Response Time
(trailing edge)
260
nS
Note 5
NOTES:
Clock must have 50% duty cycle.
Buffer chaining is not guaranteed when ClK is greater than 1.5 MHz.
Residual bit detection logic not guaranteed when RC is greater than 50Kbps.
See "Ordering Information" for maximum serial rates.
C(load) = 100pf
1.
2.
3.
4.
5.
19
·
"
DMA TIMING
DMA OUT
DMAIN
AO-A15
(ADRV = 0)
AO-A15
(ADRV = 1)
(AO-A15 SAME AS DMA READ)
I
rTD?
DRQO
DRQI~
I ~
"
~-1 ------------7
~TDAO
I
(I
DACK
DACK
~-
~--------~-~ I--- TOAH
I
DALO-DAL7
<
=--1
TDMW
TDD
Sf
--"
~
DALO-DAL7
!
I
--l TDW \.-T DHW...
(
DATA VALID
>---
r-
DATA VALID )
~TRD--I
CPU READ/WRITE TIMING
CPU READ
CPU WRITE (CS
('CS IS LOW)
X
~"------II'----
IS LOW)
v---
IAO-IA3- - V
IAO- IA3- - V
__ ~.~----~T~AW-----------~
FiE
WE----~~-----TWW----~~=_----
DALO-D_A.:.-L7_ _ _ _ _ _--t_ _--<
REP~----------
L7C.--_ _---'r_-<
DALO-D:.:....A=
'---------
__ f
REPLY------..It
I--TRP2~
"NOTE: There must not be a CPU read or write (CS-RE or CS-WE) within 500 nanoseconds after the trailing
(rising) edge of DACK.
There must not be the leadingjf.alling) edge of DACK allowed within 500 nanoseconds after the
completion of a CPU write (CS-WE).
RE and WE must not be low at the same time_
20
APPENDIX A
STATES OF THE WD2501
Link Down Flow ..........................................................................
Link Up Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
State Table I, Link Down, but Going Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
State Table II, Link Going Down ..............................................................
Use of Flags by the WD2501 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Definitions of Command and Response ........................................................
Sending I-Frames (Packets) .................................................................
Receiving a Null Packet ....................................................................
Sending a REJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Receiving a REJ ..........................................................................
Definition of Valid Received N(R) .............................................................
Sending an RNR (RNRX) ....................................................................
Receiving an RNR (RNRR) ..................................................................
Conditions for Sending Link Reset ............................................................
Sending a CMDR ..........................................................................
Receiving a CMDR ........................................................................
Protocol Significance of TLOOK/RLOOK Pointers ...............................................
21
22
23
24
24
25
25
25
26
26
26
26
27
28
28
28
28
29
APPENDIX A
:ec
LINK DOWN
N
CJ1
o
~
INTERRUPT
ERO
21
=
CLEAR N E, V(R)
SEND UA
INTERRUPT
ERO = 80
o
=
1
SET LINK
SEND DISC
=
SET LINK
1
INTERRUPT
ERO
30
SEND UA
SEND DISC
INTERRUPT
ER07
1
ER06 = 0
SEND SARM
P
1
=
=
=
INTERRUPT
ERO
CO
=
ALSO,
SEE "RECEIVING A CMDR"
22
SEE
"SENDING A
CMDR"
LINK UP
CONDITIONS FOR RESET OR DISCONNECT
:ec
N
- CJ'1
o.....
SEND IDLE.
RECEIVER
IGNORED.
SEND
UA
SEND UA
SENDSARM
*ONCE A FRAME IS SENT, INTERFRAME TIME-FILL IS
FLAGS EVEN IF RBI = 1. ALSO, ONCE FLAGS ARE
STARTED, IDLE IS NOT SENT AGAIN UNTIL A
COMPLETE DISCONNECT SEQUENCE OR MASTER
RESET (MR LOW).
23
STATE TABLE I
=E
LINK DOWN, BUT GOING UP
C
(Column 2 also applies to link-up, but reset transmitted.)
I\)
C11
o.....
2.
3.
DISC sent. Waiting for
UA or DM.
SARM sent. Waiting for
UA.
SARM sent. UA RECVD.
Waiting for SARM.
=1
Re-send DISC P = 1
Re-send SARM P
1.
T1 runs out, but not N2
N2 runs out
Re-send DISC P
=1
-
Send DISC. I NTR. ERO
24. To column 1.
Send DISC. INTR. Error
Code 24. To column 1.
=
RECVD UA
Send SARM To
column 2.
Clear NA, NB, V(S). If
SARM RECVD and UA
sent. To link-up flow.
Else, to column 3.
Disregard
RECVD DISC
Send UA
Send UA
Send UA
RECVD SARM
Disregard
Send UA Clear N E, V(R).
Clear N E, V(R). Send UA.
To link-up flow.
RECVD something, but
not UA, DISC, SARM,
nor DM.
Disregard
Disregard
Disregard
RECVD DM
Send SARM. To
column 2.
Disregard
Disregard
STATE TABLE II
LINK GOING DOWN (WAS UP)
1.
2.
3.
DISC sent. Waiting
forUA.
MDISC (CROO) set.
DISC sent. UA or DM
RECVD. Sending flags.
Link is down.
T1 runs out
Re-send DISC. P = 1
Send DISC to column 1
-
RECVD UA or DM
If DISC RECVD and UA
send to link down flow.
If not, to column
column 3.
-
Disregard
RECVD SARM
Disregard
-
Send UA. Send SARM.
To Table I.
RECVD DISC
Send UA
-
Send UA. To link down
flow.
RECVD something but
not UA, DISC, SARM,
nor OM.
Disregard
-
Disregard
NOTE: If while the link is up, the MDISC bit is set, the WD2501 will send a DISC and wait for a UA. After
receiving the UA, the WD2501 does not require a DISC to be received. The link is considered down.
If while the link is up, a DISC is received, but MDISC = 0, the WD2501 will send a UA immediately
followed by a DISC being sent. Appropriate action shown in column 1 above is taken.
24
USE OF FLAGS BY THE WD2501
DEFINITIONS OF COMMAND AND RESPONSE
The WD2501 will send interframe time fill flags, and
will send flags when the link is down if RBI = 0
and/or ACTIVE
1 (see Link Down Flow). The
WD2501 does not require the remote station to send
flags nor interframe time fill of flags. The chip will
accept idle or flags. However, if the receiver is idle for
T1xN2, the WD2501 will disconnect the link.
A transmitted or received command or response is a
frame with the A-field as defined below:
=
I\)
The chip will send contiguous flags of:
011111100111111001111 ...
FRAME
A-FIELD
Transmitted Command
Received Command
Transmitted Response
Received Response
Register E
Register F
Register F
. Register E
Only command frames or response frames are
transmitted. If a received frame is neither a command
nor response, it is disregarded ("thrown-away") at the
receiver:
The chip will accept either the above sequence as
contiguous flags or:
011111101111110111 ...
SENDING I·FRAME (PACKETS)
NOTE: In all subsequent pages, the link is considered UP (LINK
RNRR(2)
0
T1 RUNS
OUT(1)
BUT NOT
N2
RECVD
REJ(2)
= 0)
SEND
(CR10)
BRDY OF
TLOOK #NB
NA
AND
NB
1
0
Don't Care
0
No
No
ClearSEND (CR10)
1
1
Don't
Care
0
No
No
Send next packet
with N(S)
NB.
After transmission
complete, increment
N B. Exception: if
NB + 1
NA, do
not send next
packet. There are 7
outstanding packets.
=
=
0
10rO
Equal
1
No
No
No packets to send.
0-1
1
Equal
1
No
No
Send next packet
with N(S)
NB.
After transmission
complete, increment
N B, but do not send
next packet.
1
10rO
Not Equal
1
No
No
Do not send packet.
1 orO
10rO
Not
Equal
10rO
Yes
No
Retransmit packet
with N(S)
NA and
P
1. When transmission complete,
do not ao to next
packet. 4)
Not
Equal
0
10rO
10rO
:ec
=
=
No
Yes
=
=
Make NA
received N(R). Start
sequential retransmission of packets
with N(S)
NA.
=
NOTES:
1. This table applies to T1 running out only if started due to at least one packet being outstanding.
2. Received S-frames shown in this table are taken to have valid N(R)'s.
3. When an acknowledgement is received, NA is made equal to the received N(R). All TLOOK segments from the
25
en
o.....
NOTES CONTINUED:
old value of NA up to N(R) -1 are acknowledged and the appropriate TLOOK segments will have the ACKED
bit set. After setting the ACKED bit(s), an XBA interrupt is generated.
4. Assuming appropriate TLOOK segments are ready, packets are sent sequentially without waiting for an
acknowledgement with three exceptions:
a Seven outstanding (unacknowledged) packets have been transmitted.
b. The remote station has indicated a busy condition as noted by the receiving of an RNR. The next
unacknowledged packet is transmitted, if not previously transmitted, and T1 is started.
c. If T1 expires (runs-out), the last unacknowledged packet is retransmitted with P = 1. This is the timer
recovery condition and remains in effect until an S-frame with F = 1 and acknowledging that at least one
packet is received, or until a link reset is transmitted, or until a DISC is received.
If an acknowledgement is not received after N2 tries, a SARM is transmitted with P = 1. An interrupt is
generated with ERO = 90.
RECEIVING A NULL PACKET
RECEIVING A REJ
If a REJ is received error-free with no I-field:
If an error-free packet is received with no I-field but
with an in-sequence N(S), it will be treated the same
as a packet with an I-field. RCNT will be all O's.
1. If the N(R) is invalid, an interrupt is generated with
ERO = 88, and a SARM is transmitted to reset the
link. (See Table I, column 2.)
2. If the N(R) is valid and greater than NA, at least one
transmitted I-frame is acknowledged. An XBA
interrupt is generated with the appropriate ACKED
bits in TLOOK set.
3. If the N(R) is valid and less than NB, or equal to NB
but an I-frame is being transmitted, the WD2501
will begin sequential re·transmission starting with
V(S) = received N(R). If an I-frame is in transmission when the REJ was received, it is aborted.
4. If the N(R) is valid and equal to NB and there is no
I-frame being transmitted, no further action is
taken. In this case, the REJ has the same effect as
an RR.
The packet will be acknowledged at the next opportunity just as if the I-field was present.
The received N(R) of the null packet is recognized as
an acknowledgement of a previously transmitted
packet(s).lf the N(R) is not valid, the link will be reset.
The WD2501 will not transmit a null packet. TCNT
must not be all O's.
SENDING A REJ
1. The reject condition is entered any time an errorfree I-frame with an out-of-sequence N(S) is
received.
2. A REJ frame with N(R) = V(R) is transmitted
immediately if the WD2501 is not sending an 1frame, or immediately after the completion of the
I-frame. There are two exceptions to this in notes 3
and 4 below.
3. If a link resetting SARM needs to be transmitted,
the SARM is sent ahead of the REJ. Immediately
after the SARM, the REJ is sent. As an example, if
an I-frame is received with out-of-sequence N(S)
and invalid N(R), a SARM will be sent followed by
an REJ.
4. If the receiver is not ready (RNRX = 1), the REJ is
not sent until RNRX is cleared.
5. Once the reject condition is entered, only one REJ
is sent. Another REJ is not sent unless the reject
condition is cleared and re-entered. The reject
condition is cleared if an I-frame is received with
an in-sequence N(S) [Le., received N(S) = V(R)] , or
if a SARM is received.
When the REJ is sent, error counter #6 is incremented.
DEFINITION OF VALID RECEIVED N(R)
Reference:
X.25 paragraph 2.4.8.1 and paragraph
2.3.4.10
DEFINITION: A valid received N(R) is greater than or
equal to NA and less than or equal to
NB. An invalid received N(R) is one
which does not conform to this rule.
NOTES: 1. This must be understood in a circular
sense. 0 could be greater than 7, depending on the values of NA and NB.
2. If NA = NB, there is only valid
possibility for N(R).
3. If NB + 1
NA, there are seven outstanding packets, and it is impossible to
receive an invalid N(R).
4. Basically, an invalid N(R) is one which
acknowledges a packet which was never
sent.
=
26
SENDING AN RNR (RNRX)
LINK
RECR
(CR01)
REC
ROY
(NE)
ACTION
-
-
No S-frame transmitted when link down.
1-0
1
1
RLOOK ready. No S-frame sent immediately.
1-0
1
a
Interrupt: RLNR. RNR sent immediately. (2) RNRX set.
1-0
a
-
RNR sent immediately. RNRX set.
a
a
a
a
1
1
Receiver ready to accept I-frames.
1-0
1
Receiver ready to accept I-frames.
1
Interrupt: RLNR. RNR sent. RNRX set.
0-1
a
a
a
0-1
1
Next received I-frame not brought into memory. Immediately
after frame received, RNRX cleared. After that, an RR or REJ is
sent.
a
a
1-0
a
a
Interrupt: RLNR. RNR sent. RNRX was previously set.
1
a
Next received I-frame not brought into memory. If P
1. RN RX was previously set.
send RN R with F
=
= 1, will
RNRX set. RNR sent. There is no RLNR interrupt.
NOTES ON RNRX:
1. The arrows (-) indicate a change in state from the value on the left to the value on the right.
2. If an RNR is sent "immediately," it means immediately after link is brought up.
3. After the link is up, if an RR, RNR or REJ is sent, it is sent at the next opportunity. This means immediately if
no I-frame is being sent, or at the end of the current I-frame being transmitted.
4. The RNRX (SROO) status bit is set at the time the receiver-not-ready condition was established. The RNR may
be sent later according to note 3 above.
5. When a received I-frame is brought into memory, it may be accepted provided the FCS and N(S) are good and
the I-field is not too long. The N(R) mayor may not be correct, but is checked separately. If the N(R) is bad, a
link reset is transmitted.
6. Whenever RNRX
1, the I-field of received I-frames is not brought into memory. The received N(S) and N(R)
are checked as usual. (See note 9 below.)
7. If, while RNRX = 1, a link resetting SARM is received, a UA will be transmitted. However, an RNR will not be
1, then an RNR will be sent with F = 1.
sent immediately after the UA. If an I-frame is received with P
8. If a link resetting SARM is transmitted when RNRX = 1, RNRX will be cleared when the UA is received. If the
condition which caused received-not-ready still exists, an RNR is sent and RNRX is set according to the
RNRX table. If the receiver is ready, I-field data may be brought into memory.
9. If, while RNRX = 1, an out-of-sequence N(S) is received, the WD2501 will not immediately send an REJ. After
RNRX is cleared, an REJ will be transmitted at the next opportunity.
=
=
27
RECEIVING AN RNR (RNRR)
SEND
(CR10)
NA
AND
NB
RECVD
ACK?
RECVD
RNR
RECVD
RR,
REJ
OR
UA
11
EXPIRES
1
Not
Equal
YES
YES
NO
NO
Set RNRR. Restart T1
and N2. Update NA.
0
Not
Equal
YES
YES
NO
NO
Set RNRR. Restart T1
and N2. Update NA. If
after update NA
N B,
stop T1.
0
Equal
NO
YES
NO
NO
Set RNRR.
10rO
Not
Equal
NO
NO
NO
YES
Re-transmit last unacknowledged I-frame
with P
1. Start T1. If
RN R subsequently received restart T1 and N2.
Not
Equal
YES
10rO
Don't
Care
Don't
Care
0-+1
Equal
NO
10rO
=
=
NO
YES
(but not UA)
NO
Clear RNRR. Restart T1
and N2. Update NA. If
after update NA
N B,
stop T1.
NO
YES
NO
Clear RNRR.
NO
NO
NO
Send next I-frame. Increment N B after transmission. (Then, NB does
not NA). Start T1 and N2.
=
NOTES:
1. If SEND = 1, it is assumed that BRDY (NA) is set. Otherwise, SEND is cleared.
2. If RNRR = 1, only one I-frame is sent perT1 interval.
CONDITIONS FOR SENDING LINK RESET
and I-field data may again be brought into memory by
the receiver DMA (provided RECR = 1 and REC RDY
of segment #0 is set to 1). If a DISC is received, the
WD2501 will send a UA followed by a DISC and go to
State Table II, column 1.
1. CMDR received.
2. Received response, other than CMDR, which
contained an I-field.
3. Received I-frame or S-frame with invalid N(R).
If a supervisory response is received, the WD2501 will
accept any acknowledgements contained in the
received frames N(R), and the CMDR is retransmitted.
4. Received response with unsolicited F-bit.
5. Have sent I-frame N2 times without acknowledgement. Exception: An RNR frame received
will reset the N2 counter.
RECEIVING A CMDR
Upon the reception of a CMDR:
1. The CMDR I-field will be in the memory referenced
by the current NE segment, provided the receiver
was ready.
SENDING A CMDR
A CMDR may be sent for any of the reasons indicated
in X.25. If an invalid N(R) is received, the link is reset
whether the frame was a command or response.
2. The SEND (CR10) bit is cleared.
3. No more I-field data will be brought into memory
by the receiver.
Upon sending a CMDR, the WD2501 will not allow
I-field data to come into the receiver DMA. However, it
may send I-frames (packets). If an I-frame is received,
the WD2501 will re-transmit the CMDR. If a SARM is
received, the WD2501 will send a UA and clear NE,
4. A link resetting SARM is transmitted and an error
interrupt is generated at the beginning of the
SARM. The hexidecimal value of ERO is CO.
28
5. When a UA is received to the SARM, NA and NB
are cleared to O. I-field data may not come into
memory provided RECR = O. If RECR goes from 0
to 1, and after an I-frame is received, the next I-field
may be brought into memory.
TLOOK pOinter NB =
retransmission
X when
in
TLOOK pointer NA
last unacknowledged packet. When a
frame with a valid N(R) is
received, NA is made equal to
the N(R). If NA changed, an XBA
interrupt is generated.
NOTE: The reason for step 5 is to allow the CPU time
to initialize the transmitter in such a manner
so as to not duplicate I-frames. The CPU
should set-up the next transmission according to the received V(R) in the received
I-field. The reason for step 2 is to prevent outof-sequence transmissions.
PROTOCOL SIGNIFICANCE OF TLOOKIRLOOK
POINTERS
The NE, NA, and NB pointers have a relationship with
the sequence counters used in the LAPB protocol.
Let Vc(R) = V(R) in I-field of received CMDR.
If Vc(R) > NA, a transmitted block or blocks have
been acknowledged from NA and up to Vc(R) - 1.
Vc(R) is found in the current RLOOK buffer.
The RLOOK pointer NE is equal to V(R) at all times if
TRCV = O. However, when TRCV = 1 when the link is
UP, there is no guaranteed relationship between NE
andV(R).
TLOOK pointer NB is the Next Block to be transmitted. If not in packet retransmission, NB is equal to
the V(S) of the next new packet to be transmitted.
NOTE: After receiving a CMDR, the CPU has a
certain amount of time to read the current
values of NA and NB. This minimum time is
the time it takes to send a SARM and receive
a UA. Immediately after the UA is received,
NA and NB are cleared.
TLOOK pointer NA is the Next packet to be
Acknowledged. It represents the V(S) number for the
oldest packet in the retransmission buffer.
The CPU should take the packet referenced by Vc(R)
and puts its address and count information in TLOOK
segment #0. Vc(R) + 1 goes into segment #1 and so
on up to NB -. The CPU should await for NA and NB
to clear before setting the SEND (CR10) control bit.
USE OF THE RECR BIT
The RECR (CR01) bit should be understood as an
instruction to the WD2511 to initialize the receiver
memory. The WD2511 will test RECR as soon as
MDISC is cleared, and will test RECR after each link
set-up and each link reset. Once the receiver memory
is ready, the WD2511 will not test RECR again unless
there is a link set-up, link reset, or a receiver-not-ready
condition.
EXAMPLE: Suppose four packets are outstanding
with N(S) counts 3,4,5 and 6. Number 3
is a Data Packet on Logical Channel (LC)
14. Number 4 is a Call Request Packet on
LC 220. Number 5 is a Reset Packet on
LC 7. Number 6 is a Data Packet on LC 9.
A CMDR is received, and the V(R) in the 1field is 5. Thus, numbers 3 and 4 are
acknowledged. At this point NA = 3 and
NB = 7. The CPU will put the Reset
Packet on LC 7 in #0, and the Data
Packet on LC 9 in #1. After NA and NB
are cleared, the CPU may set SEND
(CR10) and transmission will start with
N(S) = 0, which is the Reset Packet on
LC7.
After the link is UP, and at least one packet has been
received as indicated by the PKR interrupt, the user
should clear RECR. This is an advantage, because if a
link reset is either transmitted or received, the
WD2511 will enter a receiver-not-ready condition.
This will prevent packets received after the link reset
from appearing to have arrived before some packets
received prior to the link reset.
The receiver-not-ready condition is indicated by
RNRX= 1. This condition is cleared after the user
makes RECR = 1 with RECRDY = 1 (in RLOOK #0),
and after either a packet or an S-frame is received.
PROT COL SIGNIFICANCE
TLOOK/RLOOK POINTERS
If RECRDY of the next RLOOK is 0, but RECR = 0,
there will not be an RLNR interrupt, but RNRX will be
set. If RECR = 1, but the RECRDY bit of the next
RLOOK segment is 0, there will be an RLNR interrupt
(error code 10), and RNRX will be set.
In addition to the use of the TLOOK/RLOOK pointers
as used in the Memory Access Method, the pointers
have a significance with the link level protocol.
RLOOK pointer NE = V(R) at all times
TLOOK pointer NB = V(S) when not in
retransmission due to time-out
recovery or received REJ.
29
ORDERING INFORMATION
Maximum Rate
Order Number
r-100 Kbps
WD2501T-01
500 Kbps
WD2501T-05
1.1 Mbps*
WD2501T-11
* Higher speeds available on special order.
The following devices have a tighter power supply
specification and meet all other parameters in this
data sheet.
Power Supply Range + 51 - 2%:
Maximum Rate
Order Number
100 Kbps
WD2501T-91
500 Kbps
WD2501T-92
1.1 Mbps
WD2501T-93
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
30
Printed in U.S.A
WESTERN DIGITAL
c
o
R
p
o
R
A
T
o
/
N
~
WD2511 X.25 Packet Network Interface (LAPB)
FEATURES
• Packet switching controller, compatible with
CCITT recommendation X.25, level 2, LAPB
(WD2511)
• TTLcompatible
• 48 pin dual in-line packages
• Higher bit rates available by special order
• Programmable primary timer (T1) and retransmission counter(N2)
APPLICATIONS
X.25 PACKET SWITCHING CONTROLLER
PART OF DTE OR DCE
PRIVATE PACKET NETWORKS
LINK LEVEL CONTROLLER
• Programmable A-field which provides a wider
range of applications than defined by X.25. These
include: DTE-to-DTE connection, multipoint and
loop-back testing.
• Direct memory access (DMA) transfer: two
channels; one for transmit and one for receive.
Send/receive data accessed by indirect addressing
method. Sixteen output address lines.
GENERAL DESCRIPTION
The WD2511 is a MOS/LSI device which handles bitoriented, full-duplex serial data communications with
DMA, which conforms to CCITT X.25 with programmable enhancements.
The device is fabricated in N-Channel silicon gate
MOS technology and is TTL compatible on all inputs
and outputs.
• Zero bit insert and delete
• Automatic appending and testing of FCS field
• Computer bus interface structure: 8 bit bidirectional data bus. CS, WE, RE and four input
address lines
• DC to 1.1 MBPS data rate
8 61T DAL
ROM
cs
CENTRAL
MICRO·
CONTROLLER
WE
Ill'
IAO·AI3
DMA
INTR _ - - - - - - - '
DATAl CONTROL 6US
+12V - - - . .
+5V-..
GND_
CLK_
MR_
BLOCK DIAGRAM
PIN DESIGNATION
31
AO·A15
C
I\)
.....
.....
C11
INTERFACE SIGNALS DESCRIPTION (All signals are TTL compatible.)
=e
C
PIN
NUMBER
SYMBOL
PIN NAME
FUNCTION
I\)
c.n
-'"
-'"
1
No Connection
leave pin open
Reply
An active low o.!:!!,put t2..Jndicate the WD2511
has either a CS. RE or a CS.WE input.
WE
Write Enable
The data on the OAl are written into the
selected register when CS and WE ar~ low.
4
CS
Chip Select
Active low chip select· for CPU control of I/O
registers.
5
RE
Read Enable
The contents of the selected register are placed
on OAl when CS and RE are low.
6
ClK
Clock
Clock input used for internal timing. Must be
square wave, and greater than 250 KHz.
7
MR
Master Reset
Initialize on active low. All registers reset to
zero, excePbcontrol bits MDISC and LINK are
set to 1. DA K must be stable high before MR
goes high.
Data Access Lines
An 8-bit bi-directional three-state bus for CPU
and DMA controlled transfers.
2
REPLY
3
8-15
16
17
18
19
OAlO-DAl7
RO
RC
Receive Dat;:l
Receive Clock
VSS
TC
Ground
Ground.
Transmit Clock
A 1x clock input. TO changes on the falling
edge ofTC.
Receive serial data input.
This is a 1x clock J.Qput, and RD is sampled on
the rising edge.2!. RC. RO changes occur on the
falling edge of RC.
20
TD
Transmit Data
Transmitted serial data output.
21
RTS
Request-Ta-Send
An open collector (drain) output which goes low
when the WD2511 is ready to transmit either
flags or data.
22
CTS
Clear-Ta-Send
An active low input which signals the WD2511
that transmission may begin. If high, the TD
output is forced high. May be hard-wired to
ground.
23
DROO
DMA Request Out
An active low output signal to initiate CPU bus
request so the WD2511 can output onto the
bus.
24
DROI
DMA Request In
An active low output signal to initiate CPU bus
request so that data may be input to the
WD2511. DRaa and DROI will not be low at the
same time.
25
DACK
DMA Acknowledge
An active low input from the CPU in response to
DROI or DRaa. OACK must not be low if CS
and RE are low or if CS and WE are low.
26-41
AO-A15
Address Lines Out
(See front page for
Pin Assignments)
Sixteen address outputs from the W02511 for
DMA operation. If the control bit ADRV is 1, the
outputs are TTL drives at all times. If ADRV is 0,
the outputs are three-state, and are HI-Z
whenever DACK is high. (ADRV is in Control
Register #1.)
42
VDD
Power Supply
+ 12VDC power supply input.
32
INTERFACE SIGNALS DESCRIPTION CONTINUED (All signals are TTL compatible.)
::ec
PIN
NUMBER
SYMBOL
43
INTR
Interrupt Request
An active low interrupt service request output,
and returns high when Status Register #1 is
read.
44-47
IAO-IA3
Address Lines In
(See front page for
Pin Assignments)
48
VCC
Four address inputs to the WD2511 for CPU
controlled. read/write operation with registers in
the WD2511. If ADRV = 0, these may be tied to
AO-A3. (ADRV is in Control Register #1.)
+ 5VDC power supply input.
PIN NAME
FUNCTION
Power Supply
Parallel transmit data are entered into the Transmitter
Holding Register (THR), and then presented to the
Transmitter Register (TR) which converts the data to a
serial bit stream. The Cyclic Redundancy Check
(CRC) is computed in the 16-bit CRG register, and the
results become the transmitted Frame Check
Sequence (FCS).
Parallel receive data enter the Receiver Holding
Register (RHR) from the 24-bit serial Receiver
Register (RR). The 24-bit length of RR prevents
received FCS data from entering the RHR (unless
residual bits are received). The receiver CRC register
is used to test the validity of the received FCS. A 3stack FIFO is included in the receiver.
ORGANIZATION
A detailed block diagram of the WD2511 is shown in
Figure 1.
Mode control and monitor of status by the user's
CPU is performed through the Read/Write Control
circuit, which reads from or writes into registers
addressed by IAO-IA3.
Transmit and receive data are accessed through the
DMA control. Serial data is generated and received by
the bit-oriented controllers.
Internal Control of the WD2511 is by means of three
internal microcontrollers; one for transmit, one for
receive, and one for overall control.
8 BIT DAL
DMA
A
D
D
R
E
READ·
WE IAO.IA3 4
C6'~~~~L
LOGIC
S
REPLY
DMA
. CONTROL
LOGIC
S
E
S
AO·A15
+12V_
+5V_
TRANSMITTER
MICRO·CONTROLLER
MR CLK_
GND-
RD
TD
Figure 1
WD2511 BLOCK DIAGRAM -
33
DETAILED
I\)
(J'I
.....
.....
:ec
........
I\)
(J"I
FRAME FORMAT
The WD2511 performs "bit-oriented" data communications control. According to the bit-oriented
procedures (HDLC, SDLC, ADCCP), each serial block
of data is called a frame.
Each frame starts and ends with a Flag (01111110). A
single flag may be used both as the closing flag of
one frame and the opening flag of the next frame. In
between flags, data transparency is provided by the
insertion of an 0 bit after all sequences of 5 contiguous 1 bits. The receiver will strip the inserted 0
bits. The last 16-bits before the closing flag is in the
Frame Check Sequence (FCS). Each frame also
includes address and control fields (A and C fields).
The FCS calculation includes all data between the
opening flag and the first bit of the FCS, except for
D's inserted for transparency. The 16-bit FCS has the
following characteristics:
After the frame is received, if there were no errors,
then the remainder in the CRC register (internal in the
WD2511) will be:
1111000010111000 FOB8
The WD2511 generates and tests the Flag, FCS, AField, C-Field, and performs zero bit insertion and
deletion. According to the X.25 protocol, there are
three types of frames: supervisory (S-frame), unnumbered (U-frame), and information (I-frame).
The WD2511 performs frame level (level 2) link access
control. All S- and U-frames are automatically
generated and tested by the WD2511. The user need
only be concerned with the I-frames, which are
packets.
The WD2511 will transmit contiguous flags for interframe time fill.
Polynomial = X16 + X12 + X5 + 1
Transmitted Polarity -Inverted
Transmitted Order -High Order Bit First
Preset Value
-Alii's
~I
I·FRAME (PACKET)
14
I·FIELD (PACKET DATA)
14
FLAG
~
ADDRESS CONTROL
X.25LEVEL2
PACKET
CONTROL
INFORfv1ATION
X25LEVEL3
·1
USER DATA
FLAG
FCS
~~~~l~E4X'25LEVEL2~
APPENDED --~__- - - - DMA ACCESSED
~
APPENDED
~
~
WD2511
WD2511
X.2S MODE
NOTE: X.25 Level 1, is the Physical Interface
34
MODEM
CONTROLS
CPU BUS
(DTR, DSR, ETC.)
00
~I
(Jl
=i
0
>
r
~I
~I
5>
~I ~I
~I 5>
w
<;'
0
r
;>;
w1f
DROO
TC
TD
DROI
,----
WD2511
DACK
MEMORY
CTS
LEVEL 1
AO·A15
RTS
16
INTERFACE
~ MODEM
RC
RD
1 1 1
+12VDC +5VDC
Figure 2.
GND
SYSTEM CONNECTION
II. PROGRAMMING THROUGH REGISTERS
Control, status, and error bits will be referred to as
CR, SR, or ER, respectively, along with two digits. For
example, SR16 refers to status register #1 and bit 6,
which is "XBA."
The WD2511 is controlled and monitored by sixteen
I/O registers.
REGISTER DEFINITION
REG
#
IA3
1A2
IA1
lAO
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
1
1
1
0
1
1
0
0
0
0
0
9
A
B
C
D
1
1
1
1
0
0
1
1
0
1
1
0
0
0
E
F
1
1
1
1
1
1
0
0
1
2
3
4
5
6
7
8
1
1
1
1
1
1
1
REGISTER
CRO
CRl
*SRO
*SR1
*SR2
*ERO
REGISTER
GROUPING
OVERALL CONTROL
AND
MONITOR
*CHAIN MONITOR
*RECEIVED C-FIELD
T1
N2/Tl
RECEIVER
MONITOR
TIMER
TLOOKHI
TLOOKLO
CHAIN/LIMIT
NOT USED
XMT COMMAND "E"
XMT RESPONSE "F" (Note 1)
* CPU READ ONLY. (Write Not Possible)
NOTE:
1. Registers E and F should be set-up while MDISC
= 1.
35
DMASET-UP
"A" FIELD
CONTROL, STATUS, ERROR REGISTERS
BIT#
4
3
2
1
0
H/F
ACTIVEI
PASSIVE
LOOP
TEST
2RAMT
RECR
MDISC
TRCV
XI
AORV
0
0
0
SENO
NA2
NA1
NAO
RNRR
NB2
NB1
NBO
RNRX
SR1
1PKR
1XBA
1ERROR
0
NE2
NE1
NEO
0
SR2
T10UT
IRTS
REC
IOLE
0
0
0
0
ERO
ER07
ER06
ER05
ER04
ER03
ER02
ER01
EROO
CONTROL REGISTER 0
CR05
CR04
CR03
CR02
CR01
CROO
ACTIVEI
PASSIVE
RAMT
RECR
MOISC
REGISTER
7
6
5
CRO
ADISC
0
CR1
TXMT
SRO
LINK
1 Causes Interrupt (INTR Goes LOw).
2 RAMT is used to initiate a self-test feature (see section on Self-Test).
For normal operation, program to O.
REGISTER
CR07
CR06
CRO
AOISC
o
H/F
LOOP
TEST
DESCRIPTION
BIT
CROO
MOISC is a mandatory disconnect command. MOISC will cause a logical disconnect in
the link. No DMA accessed data will be transferred as long as MOISC = 1. After Master
Reset (MR pin transition from low to high), MDISC will be set. The W02511 will neither
transmit nor accept received data until MOiSe = O.
CR01
This bit is RECR which defines the CPU's receiver buffer as initially Ready (CR01 = 1). If
RECR
1, this bit indicates that the WD2511 may begin receiving I-frames. (See SROO)
CR02
RAMT - This bit activates an internal register test. See Section on Self tests for
description.
CR03
The LOOP TEST bit will connect the transmitted data output to the receiver input. The
receiver input pins RO and RC are logically disconnected. The "E" and "F" registers of
the A-field should be equal.
CR04
This bit will cause the W02511 to initiate link set-up if CR04 = 1, or to wait for a link setup from the remote device if CR04 = O.
=
= 0, and half duplex if CR05 = 1. (See Appendix A).
CR05
H/F selects full duplex if CR05
CR06
Unused control bits, like CR06, should remain at O.
CRO?
AOISC is used when CR04 = 1 (ACTIVE). When the WD2511 actively initiates link set-up,
a DISC will be transmitted and acknowledged prior to transmission of the SABM if CRO?
= O. Otherwise, the W02511 will send the SABM for link set-up, but not preceed the
SABM with a DISC if CRO? = 1.
36
REGISTER I
I
CR1
CR17
I
TXMT
I
CR16
I
TRCV
I
CONTROL REGISTER 1
I CR13
CR15 I CR14
XI
I
I
ADRV
BIT
0
I
I
CR12
I
CR11
o
I
o
I
I
CR10
SEND
c.n
.....
DESCRIPTION
CR10
The SEND bit (CR10) is used to command the WD2511 to send the next packet or
packets. If SEND = 1, the WD2511 will read from TLOOK the BRDY bit of the next
0, the WD2511 will clear SEND and no action
segment for transmission. If BRDY
occurs. If BRDY = 1, the WD2511 will then read TSADR and TCNT, followed by the
transmission of that buffer: After transmission, the WD2511 clears BRDY of the segment
just transmitted, and reads BRDY of the next segment. If 1, the next segment is transmitted. If 0, the SEND bit is cleared, and transmission of packets is stopped. As a matter
of good practice, the CPU should set SEND each time one of the BRDY bits is set.
=
CR11-13
Unused bits, write in O's.
CR14
The ADRV bit (CR14) is the control for the 16 bit output addresses (AO-A 15). If ADRV = 0,
the outputs are tri-state and are in HI-Z, except when DACK goes low. If ADRV = 1, the
outputs are always low impedance (TTL), and are high-level when DACK is high.
CR15
Xi -
Used when TXMT = 1
Xi = 0 Frame ~ 3 bytes excluding FCS
Xi = 1 Frame < 3 bytes excluding FCS
Receive all frames including unknown frames. See Appendix A.
CR16
TRCV -
CR17
TXMT - Transparent transmit. See Appendix A.
REGISTER
I
SR07
SRO
I
NA2
I
SR06
I
I
NA1
I
STATUS REGISTER 0
SR05
SR04
SR03
I
I
NAO
I
RNRR
BIT
SROO
I
NB2
I
SR02
I
SR01
I
SROO
I
NB1
I
NBO
I
RNRX
DESCRIPTION
RNRX. An RNR has been transmitted, or will be at next opportunity. TheCPU should set
RECR, when receive buffers are available.
SR03-SR01
NB2-NBO. Next block to be transmitted.
SR04
RNRR. This bit is set when an RNR frame is received. Once set, it is cleared when an RR,
REJ, or UA is received.
SR07-SR05
NA2-NAO. Next block of transmitted data to be Acknowledged.
37
:ec
N
.....
:ec
REGISTER
........
I
SR17
I
I
SR1
I\)
en
I
SR16
1XBA
I
I
STATUS REGISTER 1
SR14
SR13
SR15
I
I
1ERROR
I
o
BIT
I
NE2
SR12
SR11
NE1
NEO
I
I
SR10
o
DESCRIPTION
SR10
o
SR13-SR11
NE2-NEO. Next Expected packet segment number of RLOOK.
SR14
o
SR151
The ERROR bit indicates: 1) An error has occurred which is not recoverable by the
WD2511, or 2) A significant event has occurred. The "significant events" are: change in
link status (link-up or down), the WD2511 is progressing to the next segment in a
chained receive buffer, or one direction of the link has been reset.
The exact nature of the reason for the ERROR bit is given in ERO.
SR161
The XBA bit means that a previously transmitted Block, or Blocks, have been
acknowledged by the remote device. Upon acknowledgement, the ACK'ED bit is set to
"1" for each segment in TLOOK which was acknowledged.
SR171
The PKR bit stands for Packet Received. This means that a packet has been received
error-free and in correct sequence according to the received N (S) count. The data (I-field)
has been placed in the CPU's RAM memory. NE is advanced.
NOTE 1: The three interrupt-causing bits are SR17,
SR16, and SR15. Any of the three will cause
an interrupt request (INTR goes low). After
REGISTER
SR27
SR26
SR2
T10UT
IRTS
SR1 is read, all three bits are reset to 0, and
INTR returns high.
STATUS REGISTER 2
SR25
SR24
SR23
REC
IDLE
0
BIT
0
SR22
SR21
SR20
0
0
LINK
DESCRIPTION
SR20
If the link is established, LINK
SR24-21
Unused Bits - 0
= O.lf the link is logically disconnected, LINK = 1.
SR25
REC IDLE indicates that the WD2511 has received at least 15 contiguous 1'so
SR26
IRTS stands for the Internal Request-To-Send bit, and indicates that the transmitter is
attempting (successful or not) to send either data or flags. If the RTS pin is not tied to
ground orWIRE-ORED with another Signal, then IRTS
RTS.
SR27
T10UT bit means that timer T1 has timed-out. This bit returns to 0 when T1 is re-started.
1, T1 is not running. NOTE: This bit could be a 1 for a few microWhen T10UT
seconds in between intervals when T1 stops and is restarted.
=
=
38
ERROR REGISTER (ERO)
ER07
0
0
ER06 EROS
0
0
0
= ROR
= TUR
ER04 = RLNR
ER01
ER02
ER04
0
1
ER03
0
0
ER02
0
0
ER01
0
0
EROO
1
0
0
0
1
0
0
0
0
0
1
0
LINK is up. 0Nas down)
Received DISC or DM while LINK up (See
Note 3)
1
DISC sent, since sent N2 times without
UA. (Note 3).
DISC sent, REC IDLE forT1xN2.
CHAIN STATUS
0
1
1
0
0
EROO
ER01
= GNCS
= CNR
=
000000
LINK RESET RECEIVED if ER05-EROO
LINK RESETTRANSMITIED if ER05-EROO
non-zero
=
EROO similarto W
ER01 similar to X
ER02 similarto Y
ER03 similar to Z
1, but did not send P
1
ER05 means received F
ER04 -I-frame was sent N2 times without acknowledge
=
1
1
=
FRAME REJECT (See Note 1)
RECEIVED if ER05-EROO
000000
TRANSMITIED if ER05-EROO
non-zero
EROO
W
ER01
X
ER02
Y
Z (See Note 2)
ER03
=
=
=
=
=
=
NOTES: 1. Whenever a frame reject (FRMR) is received, the I-field will have been placed in appropriate memory
by DMA, and a link reset SABM will be transmitted. The NB is not advanced.
2. Definitions of W, X, Y, Z as stated in CCITI X.25.
3. DISC transmitted if DM received while link up.
Assigned bits are always O.
TERMS USED IN ERROR REGISTER
GNCS
Going to Next Chain Segment.
RLNR
RLOOK Not Ready. REC RDY bit of next segment is 0, but RECR
not occur if RECR = O.
ROR*
Receiver Over-Run. The Receiver Register (RR) had a character to load into the FIFO, but
the FIFO was full.
TUR*
Transmitter Under-Run. The Transmitter Register (TR) needed a character from the
Transmitter Holding Register (THR), but the THR was not ready. The frame being transmitted is ABORTed.
CNR
Next Chain Segment of Receiver was Not Ready.
= 1. This interrupt will
* TUR and ROR means that the bit rate clocks (TC and RC) are either too fast for the WD2511, or the DACK
response to DROI and DROO is too slow, or both.
39
w, x, Y, Z OF FRMR
These tables contain address and control information for individual send/receive packets.
To access TLOOK and RLOOK only the starting
address of TLOOK is loaded into the WD2511 in
registers A' and B'.
A frame reject (FRMR) contains a three byte I-field.
The first byte is the rejected frame control field. The
second byte contains the current N(S) and N(R)
counts of the terminal reporting the rejection condition. The third byte contains W-X-Y-Z-Z1-0-0-0 where
Wisthe LSB.
W set to 1 indicates that the control field received
and returned in the first I-frame byte was invalid.
X set to 1 indicates the rejected frame contained an
I-field which is not permitted with this command.
X 1 in conjunction with W 1.
Y set to 1 indicates the I-field exceeded the total limit
established. Y is mutually exclusive with W.
Z set to 1 indicates the control field contained ali
invalid N(R). Z is mutually exclusive with W.
Upon receiving a FRMR, the WD2511 will place the 3
byte I-field in memory by DMA, just as if the FRMR
were a packet.
=
REG A
A15 A14 A13 A12 A11 A10 A9
A8
REG B
A7
AO
A6
A5
A4
A3
A2
A1
AO-A1516 bit TLOOK starting address
=
The TLOOK and RLOOK tables are each divided into
8 segments and each segment contains 8 bytes.
Figure 3 illustrates the segmentation of TLOOK and
RLOOK. Figure 5 and 6 illustrate the contents of a
single TLOOK and RLOOK segment.
In transmit, the WD2511 will have read from TLOOK
the starting address and length of the first packet to
be transmitted. The WD2511 will automatically
transmit the flag, address, and control fields. Next,
the information field data will be transmitted using
DMA from the "SEND #0 PACKET" memory. At the
end of the information field, the WD2511 will
automatically send the FCS and closing Flag. The
WD2511 will then move on to the next packet.
If retransmission of one or more (up to seven)
packets becomes necessary, the WD2511 will automatically retrace the previous transmissions through
the TLOOK table. The user's CPU software does not
become involved in the retransmission. However, an
ERROR COUNTER is incremented. (See Error
Counter Section.)
When the WD2511 transmits a FRMR, the frame
reject condition is entered. Only a received SABM or
DISC will clear this condition. If any other command
is received, the WD2511 will re-transmit the FRMR.
However, valid responses received will be acted upon
accordingly. Also, the WD2511 may not transmit
packets while in the frame reject condition.
In the FRMR I-field, bit #4 of the second byte is a "1"
if the rejected frame was a response, and a "0" if the
frame was a command.
MEMORY ACCESS METHOD
The WD2511 memory access is accomplished by the
use of DMA and two look-up tables. These tables are
set-up to allow up to 7 I-frames to be outstanding in
each direction of the communications link. The lookup tables are divided into two areas (T-LOOK and
R-LOOK) and are in memory external to the WD2511.
To receive, each frame is checked for correct address
and FCS fields and for type of control field. If the
frame is a packet, the information field is placed in
the aSSigned memory location in a method similar to
that used in transmit. After the packet is received
error-free and in proper N(S) sequence count, an
interrupt is generated, and the WD2511 is ready for
the next packet which will be placed in the next
location.
Figure 4 shows a "store-and-forward" example that is
useful in a network node.
TLOOK
RLOOK
40
TSADR#O
'------'--'--_....J
r
~
CNT
#0
C
I\)
(J1
......
......
SEND
PACKET #1
(SECOND PART)
FOR THIS EXAMPLE,
TCNT #1 IS
GREATER THAN
LIM. THUS,
SECOND PART
OF #1 IS
CHAINED.
SEND
PACKET
#1
(FIRST PART)
XFRADR
-r
R~~~y;R
LIM
~
BUFFER
XFR ADR
LIM
~I-------i
XFR ADR
ERROR
COUNTERS
Figure 3. MEMORY ACCESS SCHEME
r--------------
LOC~/uP
I
MEMORY--..
-
-
-
-
-
-
-C~B
-
-
-
-,
I
LOOK·UP
TABLE
TABLE
TLOOK
0
I
TLOOK
I
2
f - - - - - --i
5
6
f - - - - - --i
7
RLOOK
j
I
/ ./" -
+
SERIAL
RECEIVE
CHANNELA
-...... -......
I
I
5
. . . .1 - - - - -6-1
/ RSADR #3
CHA
TSADR #6 . /
RECEIVED
--
~
RLOOK
I
~
I
I
I
I
------~--
Figure 4. STORE·AND·FORWARD EXAMPLE
:
I
~
After the Data Buffer is received- by CH A, the length (RCNT) is
in RLOOK segment #3. The CPU interrogates the packet header
(at the beginning of the Data Buffer), and concludes that the
buffer must be send out of CH B. RSADR, RCNT, and the
residual information are transferred from #3 segment to next
available TLOOK segment in CH B which is #6 in this example.
41
I
7
CH~f--------i
T
I
R~T ~~:; IB~
~--./-----WD2511
CHA
-
I
f------~-i ! T B~~;~R
f-------:~:-V//J
I
I
__
4
I
I
~
,
WD2511
CHB
SERIAL
TRANSMIT
CHANNEL B
After receiving an error-free packet with correct N(S),
the WD2511 will, in order: 1) Set FRCML (Frame
Complete), clear REC ROY, and store received
residual count. 2) Store the received length, in
characters, of the I-field in RCNT HI and RCNT LO. 3)
Advance the NE count, and generate a packet
received interrupt. 4) Acknowledge the received
packet at the first opportunity.
The addresses (TSADR and RSADR) are 16-bit binary
addresses. HI represents the upper 8-bits and LO
represents the lower 8-bits. The counts (TCNT and
ReNT) are 12-bit binary numbers for the number of
characters in the I-field.
TLOOK AND RLOOK
=e
cN
....
....
(J'1
Figures 5 and 6 detail the individual segments for
TLOOK and RLOOK.
BRDY means that the transmit buffer is ready. The
WD2511 will send the block only after the CPU makes
BRDY = 1. (BRDY is used in conjunction with the
SEND bit.) At the completion of the transmission, the
WD2511 will make BRDY = 0, and then read the
BRDY of the next segment.
After transmitting a packet, an ac~nowledgement
must be received from the remote device. The
acknowledgement is contained in the received N(R)
count of an I-frame or S-frame. Upon acknowledgement, the WD2511 will make ACK1ED = 1, and
generate a block-acknowledged interrupt. Before
assigning a new block to a segment in TLOOK, the
CPU must make sure that the previous block which
used that segment number has been acknowledged.
REC ROY informs the WD2511 that the receive buffer
is ready. The WD2511 will not receive a packet into a
buffer referenced by a particular segment until REC
ROY = 1. If the WD2511 progresses to a segment
which has REC ROY = 0, an error interrupt will be
generated.
TSADR is the starting address of the buffer to
transmit, and TCNT is the binary count of the number
of bytes to transmit.
RSADR is the starting address of the receive buffer.
After successfully receiving the packets, the WD2511
will write the value of ReNT which is the binary
length of the received packet.
Whether the WD2511 accesses a look-up table or a
memory block, a DMA Cycle is required for each
access.
Figure 5. TLOOK SEGMENT
BIT#
BYTE # IN
SEGMENT
1
7
6
5
4
3
2
1
0
ACK'ED
NS
NS
NS
NS
NS
NS
BRDY
2
TSADR HI
3
TSADR LO
4
TCNT HI
SPARE
5
TCNT LO
6
SPARE FOR USER DEFINITION
7
SPARE
8
SPARE
NS = Not Spare
42
Figure 6. RLOOK SEGMENT
=e
BITH
BYTEHIN
SEGMENT
7
6
5
4
3
2
1
0
1
FRCML*
NS
NS
NS
RES2
RES1
RESO
REC
RDY
2
RSADR HI
3
RSADR LO
4
NS
NOT SPARE
RCNT HI
5
RCNT LO
6
SPARE FOR USER DEFINITION
7
SPARE
8
SPARE
= Not Spare (NOTE: The "not spare" bits may be either 1 orO).
= Frame Complete
* FRCM L
The control bits in TLOOK (BRDY and ACK'ED) and in
RLOOK (FRCML and REC RDY) define various states
for each segment. These states are shown below:
TLOOK STATES
ACK'ED
BRDY
STATE
0
1
0
0
Ready To Transmit (CPU set BRDY, cleared ACK'ED)
1
0
Received Acknowledge (WD2511 set ACK'ED)
1
1
This state not allowed
*Transmitted and Awaiting Acknowledge (WD2511 cleared BRDY)
* State 0-0 could also occur whenever there is no data ready to send.
CPU SETS
BRDY
CPU
CLEARS
ACK'ED
CPU CLEARS ACK'ED
AND SETS BRDY
RECEIVED
ACKNOWLEDGE
1-0
DATA HAS BEEN
SENT WAITING
FOR ACKNOWLEDGE
WD2511 SETS
ACK'ED
a-a
WD2511 CLEARS
BRDY
TLOOK SEGMENT STATE FLOW
Notice that in a TLOOK segment, the 0-0 state could
have two meanings. Due to control internal to the
WD2511, this will not pose an ambiguity to the
WD2511. However, if it is a difficulty to the CPU, the
CPU could do two things:
2. At start-up, the CPU should set all ACK'ED bits.
(Since this would only be a start-up procedure, this
would not violate the "deadly embrace" rule.)
As another alternative, the CPU could use one or
more of the SPARE bits for additional state control.
1. Avoid ever entering the "NO DATA TO SEND"
In the "WAITING FOR ACKNOWLEDGE" state, one
or more re-transmissions could occur.
43
cN
.....
.....
CJ1
:ec
I\)
........
CJ1
REG = C
CHAIN
C~
IMIT
Bit
7
Bit
6
LIMIT
Bit
5
Bit
4
Bit
Bit
2
3
Bit
1
Interrupt code 42 if XRF ADR = all O's. Otherwise,
there will be an Interrupt code 41 which is a status
indication that the WD2511 is going to the next
segment.
On the receiver, Register 6 upper 4 bits gives a status
of which chain segment is currently being used.
The transmitter chaining works just like the receiver
with the following exceptions:
CHAINING
The WD2511 includes a chained-block feature which
allows the user more efficient use of memory particularly in situations where the maximum packet
size is much larger than the average packet size.
Register C is used to program the chaining feature.
The upper 4 bits define CHAIN which is the number
of chain segments allowed in addition to the first
segment. (If this feature is not used, make CHAIN
aIlO's).
The lower 4 bits of Register C define limit which is
the size of the buffer in multiples of 64 bytes including the transfer address (XFR ADR). If LIMIT is
0000, the size is 64. For 0001, the size is 128, and
soon.
For example, suppose that the LIMIT defines a
segment size of 128 and that CHAIN defines 8 additional segments in addition to the first. (Note:
Register C would be hex 81 in this example.) When
126 bytes of I-field have been received, the WD2511
will take the next two bytes as a transfer address
(XFR ADR) pointing to another segment. At the end
of that segment is another XFR ADR, and so on, up to
a maximum of 9 total segments.
On the receiver, a XFR ADR of all O's will mean that
the next segment is not ready. If the WD2511 reaches
a XFR ADR on the receiver, there will be an Error
RLOOK STATES
1. XFR ADR = all O's will not indicate next segment
not ready.
2. There is no interrupt when going from one
segment to another.
3. There is no status of the current segment being
used.
The total receiver limit is given by the expression:
TOTAL RECEIVER LIMIT
= (64 X (1
(1
+ LIMIT) - 2) X
+ CHAIN)
Also, note that the transmitter and receiver counts
are modified by 2 for each time a chain boundary is
crossed. For example, if LIMIT = 0001 (segment size
= 128 including XFR ADR), and if an I-field of 270
bytes is to be transmitted, then there will be two
times that a chain boundary is crossed. The TCNT
must be made 274 to send 270 bytes. The same is
true for RCNT.
STATE
FRCML
REC ROY
0
1
0
Ready To Receive (CPU set REC RDY, cleared FRCML)
Received Packet (WD2511 set FRCML, cleared REC RDY)
0
1
0
1
Not Ready (CPU cleared FRCML)
This state not allowed
1
NOT
READY
0-0
Bit
0
CPU SETS
REC R D Y - - - - - .
r - - = - - - -.......
CPU CLEARS
FRCML, AND
SETS
REC ROY
READY TO
RECEIVE
0-1
WD2511 CLEARS REC ROY
AND SETS FRCML
RLOOK SEGMENT STATE FLOW
44
"DEADLY EMBRACE" PREVENTION
A "deadly embrace" can occur when two processors
reach a state where each is waiting for the other. In
this case, the two processors are the user's CPU and
the micro-controller inside the WD2511. Therefore, to
prevent the "deadly embrace," the following rule is
obeyed by the WD2511 and should also be obeyed by
the user's CPU. This rule applies to TLOOK, RLOOK
and to the 1/0 registers. The Error Counters do not
apply to this rule.
ERROR COUNTERS
Following contiguously after RLOOK are six a-bit
error counters. The WD2511 will increment each
counter at the occurrence of the defined event.
However, the WD2511 will not increment past 255 (all
1's). The CPU has the responsibility of clearing each
counter. The first counter past RLOOK is #1, etc.
ERROR
COUNTER
* Received Frames with FCS Error
(includes frames ABORTed in the
I-field).
RULE: If a bit is set by the CPU, it will not be set
by the WD2511, and vice versa. If a bit is
cleared by the WD2511, it will not be
cleared by the CPU, and vice versa.
As an example, the BRDY bit in the TLOOK segments
is set by the CPU, only, but cleared by the WD2511,
only.
Received Short Frames (less than
32-bits)
3
**Number of times T1 ran-out
(completed)
Number of I-Frame Retransmissions due to T1 completing
5
6
= Next Expected to be Received
OTHER 1/0 REGISTERS
RECEIVED C-FIELD
VARIABLE BIT LENGTH
AND RESIDUAL BITS
The WD2511 will send a bits per character, only. Also
all transmitted frames will be integer multiples of
bytes.
Register 7 is the C-field of the last received frame,
provided the A-field of the frame was equal to either
register E or F, the FCS was good, and the frame
contained 32 or more bits, and the WD2511 is not
waiting for a SARM or DISC in response to a transmitted CMDR.
The WD2511 may receive a packet with, or without,
an integer multiple of bytes. The "RES" bits in the
RLOOK tables shows the number of residual bits.
The residual bits occupy the lower portion of the last
received character.
TIMER
Registers a and 9 define a 10-bit timer (T1), and a 6-bit
Maximum Number of Transmissions and Retransmissions counter (N2).
Received Residual Bits
REGISTER
0
1
1
1
1
0
0
1
1
0
1
0
0
0
1
1
0
0
1
1
1
REJ Frames Transmitted
The Error Counters are accessed by the WD2511
transmitter DMA channel. Therefore, if multiple
errors are received while the WD2511 is transmitting
a long frame, only the last error will be counted. The
only Counters which could miss counts because of
this are Counters #1, #2, and #5. The error Counters
are incremented only when the link is up (LINK = 0).
=
0
0
0
* REJ Frames Received
* These counters are incremented only if the
received A-field is equal to either Register E or F.
* * Incremented only when attempting to transmit a
command.
NA
Next to be Acknowledged
NB = Next Block to be Transmitted
RES2 RES 1 RESO
2
4
TLOOK AND RLOOK POINTERS
There are three 3-bit counters for the status of the
segments in TLOOK and RLOOK. Status Register #0
(SRO) contains counters NA and NB which are used
in conjunction with TLOOK. NB is the segment
number of the next block to be transmitted, and is
advanced at the end of each block transmission. NA
is the value of the segment of the next block which
will be acknowledged. If all transmitted blocks have
been acknowledged, then NA = NB.
In SR1 is a3-bit counter, NE, used with RLOOK. NE is
the value of the segment number where the next
received packet will be placed.
NE
COUNT
0
7
6
5
4
3
2
1
o
7
a
T1
9
N2
MSB
MSB = Most Significant Bit
LSB = Least Significant Bit
45
LSB
T1 provides the value of a delay ih waiting for a
response and/or acknowledgement. The delay is the
binary count of clock CT where:
CT
_
-
Once the CPU establishes T1 and N2, there is no
need to write into T1 and N2 again unless a master
reset (MR) has occurred, there is a power loss, or the
CPU needs to change T1 or N2. If a time-out occurs,
the WD2511 will still retain T1 and N2.
16,384
ClK
The conditions for starting, stopping, or restarting T1
are shown below: ("Re-start" means starting T1
before it ran-out).
Thus, if ClK = 1 MHz, then T1 may be set in increments 16.384 milliseconds, to a maximum delay
of 16.78 seconds. All ones in T1 is maximum delay.
1.
2.
3.
4.
STARTT1
RE·START T1
STOP T1
* I-frame sent if T1 not already
in progress due to previous
I-frame
* Acknowledgement received
to some, but not all, I-frames.
Acknowledgement received for
all I-frames.
-
* RNR received while link up.
SARM or DISC sent. (N2
restarted at first occurrence)
Receiver Idle (REC IDLE
-
UA or DM Received
= 1)
Detect REC IDLE
=0
-
5. S - command sent
* N2 is restarted where shown by asterisk (*).
NOTE: Reason 4 and 5 (above) are overridden by reasons 1, 2 and 3. On reason 2, T1 is stopped if the received
RNR acknowledged all outstanding packets.
"A" FIELD REGISTERS
Registers E and F provide a programmable A-field.
This allows the WD2511 to be a super-set of the X.25
document. That is, the WD2511 can handle a wider
range of application than the DTE-DCE links defined
in X. 25. These wider ranges include: DTE-to-DTE
connection, multipoint, and loop-back testing.
If the WD2511 is strictly in an X.25 DTE-DCE link, use
the values shown below:
DTE
Register E = 01
Register F = 03
DCE
Register E = 03
Register F = 01
If performing a loop-back test either internal
(CR03 = 1) or external, registers E and F should be the
same.
46
V.
LAPB PROCEDURE
Commands from DTE to DCE and responses from
DCE to DTE are address B (hex 01).
The Link Access Procedure Balanced (LAPB) is
described in CCITI Recommendation X.25 as the
Level 2 protocol for the Asynchronous Balanced
Mode (ABM).
The individual commands and responses are shown
in Figure 7.
One use of the Poll bit (P) is in conjunction with TimeOut Recovery. Timer T1 is started at the beginning of
a transmitted command provided it has not been
previously started. If T1 runs out (completes), the
command will be retransmitted with P = 1. If T1 runs
out again, the command will again be retransmitted,
with P= 1 up to N2 times. At N2 + 1, an error interrupt will occur. If the command was an I-frame, the
WD2511 will reset the link by transmitting a SABM. If
a 8ABM (either for link set-up or link reset), the
WD2511 will send a DISC. If a DISC, the WD2511 will
continue to send a DISC.
Zero bit insertion/deletion, use of flags and FCS are
part of Level 2, and have been discussed in this
document.
The OTE is the Data Terminal Equipment and the DCE
is the Data Circuit Termination Equipment, and is the
network side of the DTE-DCE connection.
The OTE and DCE are each "combined" stations in
that each can transmit and receive commands and
responses. Commands and responses are defined by
the A-field. Commands from DCE to DTE and
responses from DTE to DCE are address A (hex 03).
Figure 7
LAPB Commands and Responses (Bit 0 is transmitted first)
Only the CMDR and I-frame contain I-fields
FRAME TYPE
COMMAND
RESPONSE
BIT#
7
6
5
4
3
P
N(8)
1
1
0
1
1
0
1
1
INFORMATION
(I)
I-FRAME
OR PACKET
UNNUMBERED
(U)
8ABM
0
0
1
P
DISC
0
1
0
P
0
1
1
F
1
0
0
N(R)
UA
SUPERVISORY
(8)
2
1
0
0
1
FRMR
1
0
0
F
0
1
1
1
DM
0
0
0
F
1.
1
1
1
RR
RR
N(R)
J?
F
0
0
0
1
RNR
RNR
N(R)
fl-
O
1
0
1
*REJ
REJ
N(R)
3
1
0
0
1
F
F
*The WD2511 will not send a REJ command (will send REJ response, only), but may receive either a REJ
command or REJ response.
47
:ec
~
(J1
......
......
:ec
N
c.n
......
......
TRANSMISSION OF ABORT
An ABORT (a 0 followed by at least seven 1's) is
transmitted to terminate a frame in such a manner
that the receiving station will ignore the frame. There
are three conditions which will cause the W02511 to
transmit an ABORT:
1. An ABORT is sent when there is a Transmitter
Under-Run
2. While transmitting a packet, if a REJ S-frame is
received, the packet is ABORTed.
3. IfT1 times-out while a packet is being transmitted,
the packet is ABORTed. Caution: If a packet is
longer (in time) than T1, the packet will always be
ABORTed.
the loop-Back Test. This test provides a means to
check the other four registers.
The contents of Register A are placed in two even
internal registers, and the contents of Register B in
two odd internal registers. The four registers are then
added together without carry and the result is placed
in Registers 2, 5, 6 and 7. This test is initiated when
RAMT (CR02) = 1. Use the following procedure:
1. Set-up Registers A and B.
2. Set RAMT.
3. Wait at least 50 times the ClK Period.
4. Read Registers 2,5,6 and 7.
To repeat the test for new values in Registers A
and B:
5. Clear RAMT.
6. Wait at least 100 times the ClK period.
7. Go back to step 1.
SELF·TESTS
There are two self-test features: 1) Internal RAM
Register Test and 2) loop-Back Test. Both tests are
suitable for manufacturing testing, user incoming
inspection testing, or system diagnostics and
trouble-shooting.
LOOP·BACK TEST
The loop-back may be internal (CR03 = 1) or external
(CR03 = 0). Of course, if external, RO and TO must be
tied together either directly or remotely.
INTERNAL RAM REGISTER TEST
There are eleven 8-bit registers internal to the
W02511 which are not directly accessible by the
user's CPU. Seven of these registers can be tested by
If CR03 = 1, TO is internally tied to RO, and the pin at
RO (16) is internally disconnect~ Also, TC is internally tied to RC, and the pin at RC (17) is internally
disconnected.
48
NOTE:
Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits
is not intended and should be limited to those
conditions specified in the DC Electrical characteristics.
WD2511 ELECTRICAL SPECIFICATIONS:
ABSOLUTE MAXIMUM RATINGS:
Voltages referenced to VSS
High Supply Voltage (VDD) . . . . . . . . . .. - 0.3 to 15V
Voltage at any Pin .................. - .03 to 15V
Operating Temperature Range ...... O°C to + 70°C
Storage Temperature Range .... - 55°C to + 125°C
Operating DC Characteristics: VSS = OV, VCC = 5.0V ± .25, VSS = 12.0V ± .6V TA = 0° to 70°C
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
IDD
VDD Supply Current
20
70
mA
ICC
200
280
mA
VDD
VCC Supply Current
High Voltage Supply
11.4
12
12.6
V
VCC
Low Voltage Supply
4.75
5
5.25
V
VIH
Input High Voltage
2.4
VIL
Input Low Voltage
0.8
V
CONDITIONS
V
VOH
Output High Voltage
VOL
Output Low Voltage
0.4
V
V
ILH
Input Leakage Source or Sink
10
uA
10ZH
Input Leakage High
Impedance
10
uA
Yin = VCC
10ZL
Output Leakage High
Impedance
10
uA
Yin = VSS
2.8
49
10= -0.1mA
1.6mA
10=
==
C
I\)
(J1
......
......
AC Timing Characteristics: VCC
SYMBOL
= 5V ±
.25; VDD
PARAMETER
= RV ±
MIN
0.5
.6V, VSS
= OV, TA = 0° to 70°C
TYP
MAX
UNIT
2.0
CONDITIONS
elK
Clock Frequency
MHz
Note 1, 2
RC
Receive Clock Range
0
MHz
Note 3, 4
TC
Transmit Clock Range
0
MHz
Note 4
MR
Master Reset Pulse Width
10
mS
TAR
Input Address Valid to RE
0
TRD
Read Strobe (or DACK
Read) to Data Valid
375
ns
THD
Data Hold Time From Read
to Strobe
80
nS
THA
Address Hold Time From
Read Strobe
80
ns
TAW
Input Address Valid to
Trailing Edge of WE
200
nS
nS
Note 5
TWW
Minimum WE Pulse Width
200
nS
TDW
Data Valid to Trailing Edge
of WE or Trailing Edge of
DACK for DMA Write
100
nS
TAHW
Address Hold Time After
WE
80
nS
TDHW
Data Hold Time After WE or
After DACK for DMA Write
100
nS
TDA1
Time From DROO (or DROI)
to Output Address Valid if
ADRV
1
80
nS
TDAO
Time From DACK to Output
Address Valid if ADRV
0
400
nS
Note 5
TDD
Time From leading Edge of
DACK to Trailing Edge of
DROO (or DROI)
400
nS
Note 5
TDAH
Output Address Hold Time
From DACK
100
nS
TDMW
Data Hold Time From DACK
For DMA Read
100
nS
TRP1
REPLY Response Time
(leading edge)
240
nS
Note 5
TRP2
REPLY Response Time
(trailing edge)
260
nS
Note 5
=
=
NOTES:
Clock must have 50% duty cycle.
Buffer chaining is not guaranteed when ClK is greater than 1.5 MHz.
Residual bit detection logic not guaranteed when RC is greater than 50Kbps.
See "Ordering Information" for maximum serial rates.
C(load) = 100pf
1.
2.
3.
4.
5.
50
DMA TIMING
DMA OUT
DMA IN
(AO-A15 SAME AS DMA READ)
DRQI~
AO-A 15 -:--f----=----1~
(ADRV = 0)
'------------'
AO-A15
(ADRV
1)
=
DACK
I
---J
DALO-DAL7
-------~<
~
-
TDMW
DATA VALID
A~-------
-------'\V~_=-----'/.,----
-.j T DW/.-TDHW-l
M~MU
-------------/1
DACK---~
-TDD----.j
I
-------------«
TDAH
DATA VALID
>---
~
)>------
f--TRD---j
CPU READ/WRITE TIMING
CPU READ
CPU WRITE (CS
(CS IS LOW)
IAO-IA3==><_ _ _ _ _ _ _ _~r==
IAO-IA3==><
~
. _
14~--~T~AW------
I
FiE
IS LOW)
WE--~~---TWW----~~-----
DALO-DAL7
DALO-D~A=L7~_ _ _+_~
----~-r---~
R E P L y - - - - -_____ 1t
REPLy----"""'p
* NOTE: There must not be a CPU read or write (CS--RE or CS--WE) within 500 nanoseconds after the trailing
(rising) edge of DACK_
There must not be the leadinQ.j!alling) edge of DACK allowed within 500 nanoseconds after the
completion of a CPU write (CS--WE).
RE and WE must not be low at the same time.
51
52
APPENDIX A
Transparent Modes ....................................................................... .
Features of the Transparent Modes .......................................................... .
How the Transparent Modes Work ........................................................... .
Transparent Transmit ...................................................................... .
Transparent Receive ...................................................................... .
Table I, Packet Received ................................................................... .
Table II, UFI Received ..................................................................... .
APPENDIX B
Half Duplex Option ....................................................................... .
APPENDIX C
State Descriptions ....................................................................... .
Link Down Flow ......................................................................... .
Link Up Flow ................................................................. " ......... .
State Table I, Link Down, But Going Up ....................................................... .
State Table II, Link Going Down rNas Up) ...................................................... .
Use of Flags by the WD2511 ................................................................ .
Definitions of Command and Response ....................................................... .
State Table III, Sending I-Frames and S-Commands .............................................. .
Receiving and Transmitting a Null Packet ..................................................... .
Sending a REJ (Response) ................................................................. .
Receiving a REJ (Response or Command) ..................................................... .
Definition of Valid Received N(R) ............................................................ .
State Table IV, Sending an RNR (RNRX) ....................................................... .
State Table V, Receiving an RNR (RNRR) ...................................................... .
Sending S-Frames Commands ................................................ , ............. .
Conditions For Sending Link Reset .......................................................... .
Unsolicited UA or Unsolicited F Bit .......................................................... .
Sending an FRMR ........................................................................ .
Receiving an FRMR ...................................................................... .
Protocol Significance of TLOOK/RLOOK Pointers .............................................. .
Use of the RECR Bit ...................................................................... .
53
:e
cI\)
CJ'1
.....
.....
54
APPENDIX A
cleared, but the BRDY bit will not be cleared. The NB
pointer will not be incremented. To send another
transparent frame, set SEND. To resume packet
transmission, clear TXMT and set SEND. (Of course,
the TLOOK segment must be set-up prior to setting
SEND.)
If SEND is set while the link is down, a transmission
will occur even if TXMT = O. Under this condition, a
packet will be transmitted from current TLOOK
segment, and NB and V(S) will be incremented, and
the chip will go on to the next TLOOK segment just
as if the link were UP. However, the WD2511 will
expect no acknowledgment to the packet(s). If the
link is brought UP later, NB and V(S) are cleared to 0
at the time the link comes UP.
The bit XI (CR15) is used only when TXMT= 1. Xi
stands for Transmit I-field. If the frame contains three,
or more bytes, not counting FCS, make Xi = O. If the
frame contains two bytes not counting FCS, make
Xi = 1. When Si 1, only two frame bytes will be
transmitted regardless of TCNT. DO NOT attempt to
transmit a frame with TXMT = 1 and XI = 0 if TCNT is
2,1, orO.
TRANSPARENT MODES
The WD2511 was originally intended to be a link level
controller meeting the requirements of X.25 LAPB,
and this has been accomplished. However, there has
been an increasing demand from potential WD2511
users for additional frame types not included in the
LAPB frame type repertoire.
For example, the Bell System standard, BX.25, calls
for the use of XID (exchange identification) in LAPB
connections of DTE-to-DTE. (Of course, DTE-to-DTE
is not X.25 in the strictest sense.) Also, Western
Digital has received several requests for the use of a
SIM (set initialization mode). Also, there has been one
request to allow "unknown" frames to pass thru the
chip for the purpose of teleloading.
Therefore, to the WD2511 we have added two
selectable modes: transparent transmit and transparent receive. Basically, these two modes allow the
user the option to pass non-LAPB frames thru the
chip without controlling these frames according to
the LAPB protocol.
=
1_2 TRANSPARENT RECEIVE
FEATURES OF THE TRANSPARENT MODES
• May transmit any A and C field under transparent
control.
For the purposes of this discussion, it is necessary to
define an "unknown frame." That is, a frame which is
"unknown" to the WD2511.
Unknown Frame: A U-frame (unnumbered) frame
which is not part of the LAPB repertoire. The U-frame
repertoire in LAPB is SABM, DISC, DM, UA, and
FRMR. For the purposes of this discussion, "UF" will
refer to an unknown frame without an I-field, and
"UFI" will refer to an unknown frame with a I-field.
• May receive any U-frame not part of the LAPB
repertoire if transparent-receive enabled.
• Transparent modes are link state independent.
• Software to control WD2511 is backward compatible with the WD2501 (LAP chip).
1.0 HOW THE TRANSPARENT MODES WORK
A received SREJ (Selective REJect), which is an Sframe, is not considered an unknown frame by the
WD2511. If the link is DOWN and an SREJ command
is received, a DM response will be sent. If the link is
DOWN and a SREJ response is received, the SREJ is
disregarded. If the link is UP and a SREJ command or
response is received, a FRMR will be sent with W = 1.
The WD2511 will treat a received SREJ the same
whether TRCV is 0 or 1.
A received packet (I-frame) response is not considered an unknown frame by the WD2511. If the link
is DOWN, the frame is disregarded. If the link is UP, a
FRM R wi II be sent with W = 1 and X = 1. The received
packet response is treated the same whether TRCV
isOor1.
Whether TRCV is 0 or 1, the WD2511 will check all
received frames to insure that the A-field equals
either Register E or F, and that the FCS is correct,
and that the frame contains 32 bits, or more. If
TRCV 0, and if a UF or UFI is received, and if the
link is UP, the WD2511 will send a FRMR with W = 1
(Wand X are 1 in the case of a UFI). See "States of the
WD2511."
Two control bits have been added. TXMT (CR17) is the
bit to enable the Transparent Transmit, and TRCV
(CR16) will enable the Transparent Receive.
1.1 TRANSPARENT TRANSMIT
When TXMT = 1, the WD2511 will transmit the frame
in the next TLOOK segment provided SEND (CR10)
= 1, and BRDY of that TLOOK segment is 1. The link
may be either UP or DOWN. The WD2511 will not add
the A and C fields to the Transparent Transmitted
frame. The user's CPU must add these fields as the
first two bytes in the transmit buffer. Thus, the
significance of the transmit count (TCNT) is different
from packet transmission. In packet transmission,
TCNT is the count of the I-field. In transparent transmission, TCNT is the I-field plus the A and C fields (1field plus two bytes).
The timer, T1, will be disabled in transparent transmission. Therefore, if using this feature while the link
is UP, it is advised that TXMT be set only when there
are no outstanding (unacknowledged) packets which
is indicated whenever NA = NB.
At the end of the transparent transmission, there will
be an interrupt with XBA = 1. The SEN D bit wi II be
=
When TRCV = 1, the WD2511 will be enabled to
receive all frames. If the frame is "known" by the
55
WD2511, it will be treated according to the protocol
just as if TRCV = O. However, if the frame is a UF or
UFI, it will be passed on to the user's CPU.
When an unknown frame is received, and when
TRCV = 1, there will be an interrupt with ERROR= 1,
and the Error Register (ERO) will contain one of the
following hexidecimal values:
ERO
60
61
62
63
FRAME RECEIVED
UFI Response
UFICommand
UF Response
UFCommand
The C-field of the received frame is contained in
Register #7. If the frame had an I-field, the frame will
be placed in the next RLOOK segment, and the value
of RCNT will represent the count of bytes in the
I-field (not including the A and C fields). The RLOOK
pointer, NE, will be incremented. Therefore, the
relationship between NE and V(R) will not be
guaranteed if transparent receive is used while the
link is UP. However, this will not cause a sequence
problem in the protocol since the actual V(R) is
maintained in an internal register in the WD2511.
Note that NE is cleared when the link is brought UP.
Thus, if transparent receive is used only when the
link is DOWN, then NE will be equal to V(R).
A word of caution. If the next RLOOK segment is not
ready when a UFI is received, the Error Register (60 or
61) will be overwritten almost immediately with an
error code 10 (RLNR), and the user will not know if
the received UFI was a command or response.
If RECR is set while the link is DOWN, the WD2511
will prepare to receive I-fields, whetherTRCV is 0 or 1.
If a packet command is received, there will be a PKR
interrupt, and the NE and V(R) will be incremented. Of
course, NE and V(R) are cleared once the link is
brought up.
The following tables show what action the WD2511
will take when various frames are received.
56
TABLE I. PACKET RECEIVED (command, not response)
LINK
DOWN
RLOOKREADY
NO
TRCV
00r1
ACTION BY WD2511
DISREGARD
DOWN
YES
00r1
If N(S) = V(R), PKR interrupt. V(R) and NE
incremented. No ack transmitted. If N(S) not
= V(R), DISREGARD.
UP
NO
oor 1
If N(S) = V(RT), RNR sent. Else, REJ condition
entered.
UP
YES
oor 1
If N(S) = V(R), PKR interrupt. V(R) and NE
incremented. Acknowledgement sent at next
opportunity. If N(S) not = V(R), enter REJ
condition.
RLOOKREADY
TRCV
ACTION BY WD2511
TABLE II. UFI RECEIVED
LINK
DOWN
NO
oor1
DISREGARD
DOWN
YES
0
DISREGARD
DOWN
YES
1
Error interrupt 60 or61. NE incremented.
UP
NO
0
FRMR sent. W= 1 X= 1
UP
NO
1
DISREGARD
UP
YES
0
FRM R sent. W = 1 X
UP
YES
1
Error interrupt 60 or 61. NE incremented.
If TRCV = 1 and UF (no I-field) is received, there will
be an Error interrupt 62 or 63, independent of the link
state or the readiness of RLOOK.
Of course, the received C·field of any frame will be in
Register #7 provided the A-field matched either
Register E or F, the FCS was good, and the frame
contained 32, or more, bits.
57
=1
APPENDIX B
HALF DUPLEX OPTION
The WD2511 is basically a full duplex device. The
receiver is maintained in an "always ready" condition
even if the receive buffer is not ready. Thus, whether
the received frame came from a full or half duplex
system is of no consequence to the WD2511.
Therefore, the half duplex option affects only th~
WD2511 transmitter. Half duplex is enabled when H/F
(CR05) = 1.
The WD2511 will transmit one frame at a time according to the following procedure:
A. Enable RTS (RTS goes low).
B. Wait for CTS (CTS input goes low).
C. Transmit frame.
D. Remove RTS (RTS goes high 2Y2 bits of time
after the last 0 of the trailing flag.)
NOTES:
The leading flag will be transmitted somewhere
between 5 and 13 bits after CTS goes low.
RTS returns high after about 3 bits of the second
trailing flag has been transmitted.
If T1 is started, it is started when RTS goes low.
After RTS ~ low, the frame will not begin transmission until CTS goes low. After the frame has started,
the transmission of that frame is completed even if
CTS returns high during the frame.
58
APPENDIX C
STATE DESCRIPTIONS
~
The State Descriptions consists of flow charts,
tables, and verbal definitions to show how the
WD2511 will react to various external conditions. The
State Descriptions contain the following topics:
C
I\)
en
.....
.....
Link Down Flow
Link Up Flow
State Table I. Link Down, but Going Up
State Table II. Link Going Down
Use of Flags by the WD2511
Definitions of Command and Response
State Table III. Sending I-Frames (Packets) and
S-Commands
Receiving and Transmitting a Null Packet
Sending a REJ
Receiving a REJ
Definition of Valid Received N(R)
State Table IV. Sending an RNR (RNRX)
State Table V. Receiving an RNR (RNRR)
Sending S-Frame Commands
Conditions for Sending Link Reset
Unsolicited UA and Unsolicited F Bit
Sending an FRMR
Receiving an FRMR
Protocol Significance of TLOOKIRLOOK Pointers
Use of the RECR Bit
59
'\
LINK DOWN
SEND IDLE.
RECEIVER
IGNORED.
CLEAR
SEND
BIT
SEND
TRANSPARENT
FRAME
SEND
DISC
N
SEND DM
TRANSPARENT
RECEIVE
60
LINK UP
CONDITIONS FOR RESET OR DISCONNECT
LINK GOES UP
FROM STATE TABLE I.
INTERRUPT
ERO=21
CLEAR NE,
NA, N B, V(R), V(S),
SEND UA.
INTERRUPT
ERO=80
INTERRUPT
ER07= 1
ER06=O
INTERRUPT
ERO=CO
N
INTERRUPT
ERO=30
SEND UA
INTERRUPT
ERO=30
SEND
DISC
SET LINK = 1
o
61
SEE
"SENDING A
FRMR"
~
'STATE TABLE I
LINK DOWN, BUT GOING UP
(Column 2 also applies to link reset)
I\)
(II
ACTION BY WD2511
C
........
Stimulus:
Column 1:
DISC sent. WaitinQ for UA or DM.
Column 2:
SABM sent. Waiting for UA.
=1.
T1 runs out
Re·send DISC. P = 1.
Re·send SABM. P
T 1 and N2 run out
Re·send DISC. P = 1.
Send DISC. Interrupt ERO = 24. Go
to column 1
Received UA
Send SABM. Go to column 2.
Clear NA, N B, N E, V(R), V(S). Go to
link up flow.
Received DISC
Send DM.
Send DM.
Received SABM
Send DM.
Send UA. Clear NA, NB, NE, V(R),
V(S). Keep waiting for UA.
Received DM
Send SABM. Go to column 2.
Send DISC. Go to column 1.
Received something
other than UA, DM,
DISC, or SABM
Disregard.
Disregard.
STATE TABLE II
LINK GOING DOWN rNAS UP)
ACTION BY WD2511
Column 1:
DISC sent. Waiting for UA.
Column 2:
MDISC (CROO) set.
T1 runs out
Re·send DISC. P = 1.
Send DISC. Go to column 1.
Received UA or DM
Go to Link Down Flow
Stimulus:
Received SABM
Disregard
Received DISC
Send UA. Go to Link Down Flow
Received something
other than DISC,
SABM, UA, or DM
Disregard.
DEFINITIONS OF COMMAND AND RESPONSE
A transmitted or received command or response is a
frame with the A·field defined below:
USE OF FLAGS BY TH E WD2511
The WD2511 will send interlrame flags whenever full
duplex is selected (CR05 = 0), and point ST of the
Link Down Flow point has been entered. In half
duplex (CR05 = 1), interframe fi II wi II be all l' s.
FRAME
A·FIELD
=
The WD2511 does not require the interlrame time fill
flags. Either idle (all 1's) or flags will be accepted.
However, if the receiver detects idle for time T1 X N2,
the WD2511 will send a DISC.
Transmitted Command
Register E
Received Command
Register F
Transmitted Response
Register F
When sending continuous flags, the WD2511 will
send:
Received Response
Register E
For non·transparent transmitted frames, only com·
mands or responses are transmitted. A transparent
transmitted frame (TXMT = 1) may have any A·field
the user chooses.
011111100111111001111110011 ...
The WD2511 will accept either the above sequence
as continuous flags, or the "shared zero" pattern:
011111101111110111111011111 ...
All received frames must be either commands or reo
sponses, or the frame is disregarded ("thrown
away"), even if transparent receive is enabled
(TRCV= 1).
62
STATE TABLE III
SENDING I-FRAMES (PACKETS) AND S-COMMANDS
NOTES:
In all subsequent pages, the link is considered Up (LINK = 0) unless otherwise stated. X = don't care. TXMT = a
for Table III.
SEND
BRDY
NAANDNB
1
a
1
X
a
No
No
Clear SEND (CR10)
X
a
No
No
Send next packet with
N(S) = N B. After transmission complete. Increment NB. Exception: If
NB + 1 = NA, do not send
next packet. There are 7
outstanding.
X
X
X
X
not=
not=
1
X
a
Yes
No
No
Yes
Send S-command, P = 1.
Send S-command, P= 1.
1
X
X
X
RNRR
T1 EXPIRES RCVDREJ
Yes
No
NOTES ON STATE TABLE III
1. Received S-frames in Table III are assumed to have
valid N(R)'s.
Make NA = received N(R).
Start sequential retransmission of packets beginning
with N(S) = NA. See Note 3.
RECEIVING AND TRANSMITTING A NULL PACKET
If an error-free (FCS good) packet is received with a
correct N(S), but has no I-field, that packet will be
treated the same as a packet with an I-field. The fact
that there was no I-field is shown by RCNT equal to
alia's.
The WD2511 will not transmit a null packet. TCNT
must not be allowed to be all a's.
2. When an acknowledgement of one, or more,
previously transmitted packets is received, NA is
made equal to the received N(R). All TLOOK
segments from the old value of NA up to N(R) - 1
are acknowledged, and the appropriate ACKED
bits in the TLOOK segments will be set. After
setting the ACKED bits, an XBA interrupt is
generated.
SENDING A REJ (RESPONSE)
1. The REJ condition is entered any time an error-free
packet is received with an out-of-sequence N(S).
Exception: If the received N(S) + 1 = V(R), then the
received N(S) has been acknowledged, and either
an RR or RNR is transmitted.
3. Assuming appropriate TLOOK segments are
ready, packets are transmitted sequentially
without waiting for an acknowledgement with
three exceptions:
a. There are seven outstanding (unacknowledged) packets. (NB + 1 = NA)
b. The remote station has indicated a busy
condition, because an RNR was received. T1 is
started, and an S-command will be transmitted
with P = 1 when T1 expires.
c.
ACTION BY WD2511
2. When the REJ condition is entered, the REJ frame
with N(R) = V(R) is transmitted immediately if a
packet is not being transmitted, or at the completion of the current packet. There are two exceptions, as noted in 3 and 4 below.
3. If a link resetting SABM needs to be transmitted,
the SABM is sent ahead of the REJ. However,
when the UA is received for the SABM, the REJ
condition is cleared.
4. If the receiver is not ready (RNRX = 1), the REJ is
not sent until RNRX is cleared.
5. Once the REJ condition is entered, only one REJ
will be transmitted. Another REJ is not transmitted
unless the REJ condition is cleared and reentered. The REJ condition is cleared if a packet is
received with correct N(S), or if a SABM is
received, or if a SABM is transmitted and a UA
received.
If T1 expires, and there are one, or more,
outstanding packets, an S-command will be
transmitted with P = 1.
4. If an S-frame command is received, the WD2511
will transmit an S-frame response at the next
opportunity.
5. If SEN D = 1 and TXMT = 1, a frame wi II be transmitted from the next TLOOK segment if BRDY = 1.
After transmission, SEND is cleared by the
WD2511.
6. When the REJ is transmitted, error counter #6 is
incremented.
63
mand, the WD2511 will transmit a RR or RNR
response at the next opportunity.
RECEIVING A REJ (RESPONSE OR COMMAND)
Suppose a REJ has been received error-free with no
I-field, then:
DEFINITION OF VALID RECEIVED N(R)
Reference
CCITT Recommendation X.25 paragraphs 2.4.10 and
2.3.4.10.
Definition
A valid received N(R) is greater than or equal to NA,
and less than or equal to NB.
1. If the N(R) is not valid, an interrupt is generated
with ERa = ca, and a FRMR is transmitted.
2. If the N(R) is valid, and greater than NA, at least
one transmitted packet is acknowledged. The
appropriate ACKED bits in TLOOK are set, and an
XBA interrupt is generated.
3. If the N(R) is valid and less than NB, the WD2511
will begin sequential retransmission starting with
V(S) = received N(R). If a packet is being transmitted when the REJ was received, that packet is
aborted. If the N(R) is valid and equal to NB, and a
packet is being transmitted, that packet (which will
be #NB) is aborted, and retransmission will begin.
1. The "greater than" and "less than" relationships
must be understood in a circular sense. a could be
greater than 7 depending on the values of NA and
NB.
2. If NA = NB, there is only one possible valid
received N(R).
3. If NB + 1 = NA, there are seven outstanding
packets, and any received N(R) will be valid.
4. If the N(R) is valid and equal to NB, and there is no
packet being transmitted, there is no retransmission initiated. In this case the REJ has the same
effect as an RR.
4. Basically, a received N(R) which is not valid is one
which acknowledges a packet, or packets, never
transmitted.
5. If in 2, 3, or 4 above, the received REJ is a comSTATE TABLE IV
SENDING AN RNR (RNRX) (RESPONSt: OR COMMAND)
LINK
RECR
REC ROY
1
X
X
ACTION
1-0
1
1
RLOOK ready. No S-frame sent immediately.
1-0
1
a
Interrupt RLNR. RNR response sent immediately after link Up. RNRX set.
1-0
a
X
RNR response sent immediately after link
Up. RNRX set.
Receiver ready to accept packets.
No S-frame transmitted when link down.
a
1
1
a
1-0
1
Receiver ready to accept packets.
a
1
a
Interrupt RLNR. RNR response sent. RNRX
set.
a
0-1
1
If RNRX was set, then RNRX will be cleared
after the next received packet or Scommand. After that, an RR or REJ
response is sent.
a
a
a
RNR response sent. RNRX set. There is no
RLNR interrupt.
4. Whenever RNRX= 1, the I-field of all received
frames is not brought into memory. For received
packets, the N(S) and N(R) are checked as usual. If
the N(S) is out-of-sequence, the REJ will be
transmitted after RNRX is cleared.
NOTES ON STATE TABLE IV
1. The arrows (-) indicate a change in state from the
value on the left to the value on the right.
2. The RNRX status bit is set at the time the receivernot-ready condition was established. The RNR
frame will be sent immediately if no packet is
being sent, or after the end of the current packet.
5. If a link resetting SABM is transmitted when
RNRX= 1, RNRX will be cleared when the UA is
received. If the condition which caused receivernot-ready still exists, an RNR is sent and RNRX is
set. However, if the receiver is now ready, I-field
data may be brought into memory.
3. When a received packet is brought into memory
with RNRX = 0, the packet will be accepted
provided the FCS and N(S) are correct, and the
I-field i~ not too long. The N(R) may, or may not, be
correct, but is checked separately. If N(R) is not
valid, a FRMR is transmitted.
The same also applies is a link resetting SABM is
received, and a UA transmitted when RNRX= 1.
64
STATE TABLE V
RECEIVING AN RNR (RNRR)
SEND
NA AND NB
RECVD
ACK?
RECVD
RNR
RECVD RR,
REJ OR UA
X
not =
Yes
Yes
No
==
C
T1 EXPIRES ACTION
No
N
Set RN RR. Restart T1 and N2.
Update UA.
Set RNRR.
0
Equal
No
Yes
No
No
X
not =
No
No
No
Yes
Send S-command (P= 1). If
RNR subsequently received
restart T1 and N2.
X
not =
Yes
No
Yes, but not UA
No
Clear RNRR. Restart T1 and N2.
Update NA.
X
X
X
No
Yes
No
ClearRNRR.
0-1
Equal
No
No
No
No
Send next packet. Increment
NB after transmission. (Then,
NB does not = NA). Start T1
and N2.
2. NOTES OF TABLE V
If an S or I-frame is received which acknowledges a
previously transmitted packet(s), the acknowledgement(s) is accepted, and the appropriate ACKED
bit(s) in TLOOK is set, and there is an XBA interrupt.
1. If SEN D = 1, it is assumed for this table that BRDY
of the next TLOOK segment is set.
2. If RNRR= 1, an RR or RNR command is transmitted at T1 intervals.
While in the FRMR condition, the WD2511 will act as
shown below:
SENDING S·FRAME COMMANDS
FRAME RECEIVED
When an S-frame command is to be transmitted, an
RR command is transmitted if RNRX=O, or an RNR
command is transmitted if RNRX 1. If RNRX 0,
and a REJ is waiting to be transmitted, a REJ
command is transmitted.
=
SABM
Send UA. Clear FRMR
condition. Enter information transfer
phase.
DISC
Send UA. Clear FRMR
condition. Enter logical
disconnect state.
Packet with good N(R)
Retransmit FRMR
=
For all transmitted S-commands, the P bit is set to 1.
An S-command will be transmitted at T1 intervals if
an RNR is received (RNRX = 1), or if T1 has expired
due to waiting for an acknowledgement to one, or
more, previously transmitted packets.
ACTION BY WD2511
S-frame with good N(R) Retransmit FRMR
(command or response)
CONDITIONS FOR SENDING LINK RESET
1. FRM R received.
2. Have sent an S-command N2 times with P= 1, and
at T1 intervals, without receiving an S-response
with F= 1.
Packet or S-frame
with bad N(R)
Transmit new FRMR
(Z= 1)
Any frame with
violation W, X, Y
Transmit new FRMR
RECEIVING AN FRMR
UNSOLICITED UA OR UNSOLICITED F BIT
After a FRMR has been received:
If an unsolicited UA or an unsolicited F bit is received
with the link up, a FRMR will be transmitted with
W=1.
1. The FRMR I-field will be in the memory referenced
by the current NE segment, provided the receiver
was ready.
SENDING AN FRMR
2. The SEND bit is cleared.
An FRMR may be transmitted for any of the reasons
indicated in X.25 (W, X, Y, Z). An FRMR is transmitted
only if the link is up.
3. No more I-field data is allowed to come into
memory until the user makes the receiver memory
ready.
Upon sending a FRMR, the WD2511 will not send a
packet until the FRMR condition is cleared. The
WD2511 will also discard any received I-field. The
FRMR condition is cleared when either a SABM or
DISC is received.
4. A link resetting SABM is transmitted, and an error
interrupt, ERO = CO, is generated at the beginning
of the SABM.
5. After the UA is received for the SABM, then NA,
NB, NE, V(R), and V(S) are all cleared toO.
65
en
.....
.....
:ec
N
U'I
......
......
PROTOCOL SIGNIFICANCE OF TLOOKIRLOOK
POINTERS
ORDERING INFORMATION
The NE, NA, and NB pointers have a relationship with
the sequence counters used in the LAPB protocol.
Order Number
Maximum Rate
WD2511T-01
WD2511T-05
WD2511T-11
100 Kbps
SOO Kbps
1.1 Mbps*
* Higher speeds available on special order.
The RLOOK pOinter NE is equal to V(R) at all times if
TReV = O. However, when TRCV = 1 when the link is
UP, there is no guaranteed relationship between NE
andV(R).
TLOOK pointer NB is the Next Block to be transmitted. If not in packet retransmission, NB is equal to
the V(S) of the next new packet to be transmitted.
The following devices have a tighter power supply
specification and meet all other parameters in this
data sheet.
TLOOK pointer NA is· the Next packet to be
Acknowledged. It represents the V(S) number for the
oldest packet in the retransmission buffer.
Power Supply Range
Order Number
WD2511T-91
WD2511T-92
WD2511T-93
USE OF THE RECR BIT
The RECR (CR01) bit should be understood as an
instruction to the WD2511 to initialize the receiver
memory. The WD2511 will test RECR as soon as
MDISC is cleared, and will test RECR after each link
set-up and each link reset. Once the receiver memory
is ready, the WD2511 will not test RECR again unless
there is a link set-up, link reset, or a receiver-not-ready
condition.
+ 5/- 2%:
Maximum Rate
100 Kbps
500 Kbps
1.1 Mbps
After the link is UP, and at least one packet has been
received as indicated by the PKR interrupt, the user
should clear RECR. This is an advantage, because if a
link reset is either transmitted or received, the
WD2511 will enter a receiver-not-ready condition.
This will prevent packets received after the link reset
from appearing to have arrived before some packets
received prior to the link reset.
The receiver-not-ready condition is indicated by
RNRX = 1. This condition is cleared after the user
makes RECR = 1 with RECRDY 1 (in RLOOK #0),
and after either a packet or an S-frame is received.
=
=
If RECRDY of the next RLOOK is 0, but RECR 0,
there will not be an RLNR interrupt, but RNRX will be
set. If RECR = 1, but the RECRDY bit of the next
RLOOK segment is 0, there will be an RLNR interrupt
(error code 10), and RNRX will be set.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
66
Pronted in U.S.A
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
WD2520 Signalling Link Controller
FEATURES
• Performs most of the controls of the Signalling
Link Control for Signalling System No. 7.
APPLICATIONS
TELEPHONE SIGNALLING
SATELLITE LINKS
PBX SWITCHING/ROUTING
HIGH RELIABILITY COMMUNICATIONS
• Selectable window sizes (8,32,128).
• Dual channel DMA for full-duplex operation.
• Unique memory access method for buffer
management.
• All formatting of bit-oriented control included:
Zero bit insertion and deletion. Automatic appending and testing of flags and FCS fields.
• Automatic control of sequence numbers FSN and
BSN, and of control bits FIB and BIB.
• Selectable" Basic" error correction method or the
preventive cyclic retransmission error correction
method.
• 48-pin dual in-line package. Pin compatible with
the WD2501 and WD2511 X.25 link level controllers.
• DC to 1.1 M bit/sec transmit-receive rate. (Higher
bit rates available.)
GENERAL DESCRIPTION
Signalling System Number 7 is an international
standard for common channel signalling systems,
and is used within digital telecommunications
networks for call control, remote control,
management and maintenance signalling.
The flexible nature of the device allows more general
application in systems that have long round-trip
delays; notably satellite systems. As with other
members of the Western Digital family of Protocol
Controllers, all real-time protocol functions are fully
handled by the WD2520. Thus, high speed, high
efficiency communications are easily integrated into
new and existing designs.
• TTL compatible.
OMA
ADDRESSES
OMA
CONTROL
LOGIC
iNTR_----'
PIN DESIGNATION
LOOP BACK
TEST
WD2520 BLOCK DIAGRAM
67
:ec
~
c.n
~
o
INTERFACE SIGNALS DESCRIPTION (All signals are TTL compatible.)
PIN NUMBER
SYMBOL
PIN NAME
FUNCTION
1
2
No Connection
leave pin open
REPLY
Reply
An active low output to indicate the WD2520
has either a CS-RE or a CS-WE input.
3
WE
Write Enable
4
CS
Chip Select
5
RE
Read Enable
6
ClK
Clock
The data on the DAl are written into the
selected register when CS and WE are low.
Active low chip select for CPU control of 1/0
registers.
The contents of the selected register are placed
on DAl when CS and RE are low.
Clock input used for internal timing. Must be
square wave, and greater than 250 KHz.
Initialize on active low. All registers reset to
zero, except control bits MDISC and LINK are
set to 1. DACK must be stable high before MR
goes high.
An 8-bit bi-directional three-state bus for CPU
and DMA controlled transfers.
7
Master Reset
DAlO-DAl7
Data Access Lines
17
RD
RC
Receive Data
Receive Clock
Receive serial data input.
This is a 1x clock J.Qput, and RD is sampled on
the rising edge of RC. RD changes occur on the
falling edge of RC.
18
19
VSS
TC
Ground
Transmit Clock
20
TD
21
FITS
Transmit Data
Request-To-Send
Ground.
A 1x clock input. TD changes on the falling
edge ofTC.
Transmitted serial data output.
An open collector (drain) output which goes low
when the WD2520 is ready to transmit either
flags or data.
An active low input which signals the WD2520
that transmission may begin. If high, the TD
output is forced higQ. May be hard-wired to
ground.
An active low output signal to initiate CPU bus
request so the WD2520 can output onto the
bus.
An active low output signal to initiate CPU bus
request so that data may be input to the
WD2520. DRaa and DRal will not be low at the
same time.
An active low input from the CPU in response to
DRal or DRaa. DACK must not be low if CS
and RE are low or if CS and WE are low.
8-15
16
22
Clear-To-Send
23
DMA Request Out
24
DMA Request In
25
DMA Acknowledge
26-41
42
AO-A15
Address Lines Out
(See front page for
Pin Assignments)
Sixteen address outputs from the WD2520 for
DMA operation. If the control bit ADRV is 1, the
outputs are TTL drives at all times. If ADRV is 0,
the outputs are three-state, and are HI-Z
whenever DACK is high. (ADRV is in Control
Register #1.)
VDD
Power Supply
+ 12VDC power supply input.
68
INTERFACE SIGNALS DESCRIPTION CONTINUED
PIN NUMBER
43
44-47
48
SYMBOL
PIN NAME
FUNCTION
INTR
Interrupt Request
An active low interrupt service request output,
and returns high when Status Register #1 is
read.
IAO-IA3
Address Lines In
(See front page for
Pin Assignments)
VCC
Power Supply
Four address inputs to the WD2520 for CPU
controlled read/write operation with registers in
the WD2520. If ADRV = 0, these may be tied to
AO-A3. (ADRV is in Control Register #1.)
+ 5VDC power supply input.
TABLE OF CONTENTS
1.0
WD2520 Organization .................................................................. .
2.0
Programming Thru Registers ............................................................ .
3.0
Transmitting and Receiving Procedures .................................................... .
4.0
"Basic" Error Correction Method ......................................................... .
5.0
Error Correction by Preventive Cyclic Retransmission (PCR) .................................... .
6.0
Summary of Conditions for Transmission ................................................... .
7.0
Self Tests ............................................................................ .
8.0
Glossary of Terms ..................................................................... .
9.0
WD2520 Electrical Specifications ......................................................... .
REFERENCE:
CCITT Yellow Book, Volume VI - Fascicle V1.6, Q.703, Vllth Plenary Assembly, Geneva, 10-21 November 1980.
CPU BUS
Ii
:
M
I~ I~ I~ ~o 1:=z I~
~
-
I
~
t)
Figure 1
SYSTEM CONNECTION
r--M
TC
MEMORY
DROO
TO
ORal
CTS'
DACK
Ri'S
WD2520
AO-A15
RC
J
/
RD
16
1 1 1
+ 12VDC
+ 5VDC
69
GND
PHYSICAL
LEVEL
INTERFACE
~
.......
~
MODEM
before the closing flag is the FCS.
The transmitter of the WD2520 will always send at
least 2 flags between SU's, so that each SU has its
own opening and closing flag. However, the WD2520
receiver may receive as few as one flag between
SU's.
The FCS calculation includes all data between opening flag and the first bit of the FCS, except for O's inserted for transparency. The 16 bit FCS has the
following characteristics:
Polynomial: X16 + X12 + X5 + 1
Transmitted Polarity: Inverted
Transmitted Order: High order bit first
Preset Value: All 1's
FCS Register Value: 0001110100001111
if Received Correct (high order bit shown in LSB)
The WD2520 generates and tests Flags, FCS, inserted zeroes, FSN, BSN, FIB, BIB, and LI.
The WD2520 performs signalling link control. All
FISU's are automatically generated and tested by the
WD2520. The user need only be concerned with the
SF field of LSSU's and the SI and SIF fields of MSU's.
If the WD2520 has no outstanding MSU's or LSSU's,
it will transmit contiguous FISU's.
The user may control the two extra bits in the LI field
for MSU's and LSSU's. See paragraphs 3.1 and 3.2.
1.0 ORGANIZATION
A detailed block diagram of the WD2520 is shown on
the front page.
Mode control and monitor of status by the user's
CPU is performed thru the 16110 registers.
SF, SIO, and SIF data are accessed thru DMA control.
Serial data is generated and received by the bitoriented transmitter and receiver. (See Table 1.0).
(See section 8.0 for a GLOSSARY of terms.)
Internal control of the WD2520 is by means of 3
microcontrollers: one for receive, one for transmit,
and one for the internal LSI system.
Parallel transmit data is entered into the Transmitter
Holding Register (THR), and then presented to the
Transmitting Register (TR) which converts the data
into a serial bit stream. A five bit serial buffer
facilitates zero bit insert under control of the
Transmitter Microcontroller. The 16 bit FCS is calculated and transmitted from the FCS register.
Parallel receive data enter the Receiver Holding
Register (RHR) from a 3-stack FIFO. The FIFO input
is from a 24 bit serial Receiver Register (RR). This 24
bit register prevents received FCS data from entering
the RHR. The receiver FCS register is used to test the
correctness of the received FCS.
Serial data is defined in blocks called Signal Units
(SU). An SU may be a Fill-In Signal Unit (FISU), a Link
Status Signal Unit (LSSU), or a Message Signal Unit
(MSU). See Table 1.0. Each SU starts and ends with a
unique Flag (01111110). In between flags, data
transparency is maintained by the insertion of a 0 bit
after each sequence of 5 contiguous 1's. Inserted 0
bits are stripped-off by the receiver. The last 16 bits
TABLE 1.0
Numbers under SU show number of bits
,
,
,
,
BSN
7
BIB
1
Link Status Signal Unit (LSSU)
,
,
FLAG
8
I
I
BSN
7
I
BSN
7
- FISU's completely controlled by WD2520FSN
FIB
LI
00
, 7
2
1
6
J
1
I
I
I
I
FCS
16
FLAG
8
I
LI = 1 or 2
I
,I
,I
LI
6
I
I
-DMASF
80r16
XX*
2
-appendedbyWD2520
FCS , FLAG
16
,
8
LI>2
- appended by WD2520 , BIB
FSN
FIB
1
7
1
I
,I
1,
- appended by WD2520 BIB
FIB
FSN
, 7
1
1
Message Signal Unit (MSU)
FLAG'
8
The Three Signal Unit (SU) Types
LI = 0
Fill In Signal Unit (FISU)
FLAG
8
The WD2520 will discard all received SU's which do
not meet all the minimum conditions:
1. FCS Correct.
2. A multiple of 8 bits.
3. There must be at least 5 bytes between flags.
4. The LI (Length Indicator) must be correct. (See
paragraph 3.6 for the definition of a "correct" LI.)
I
I
I
I
-DMA-
1,
LI
6
I
I
*Where the "X" bits are controlled by the user.
70
XX*
2
SIO
8
I
I
SIF
8n, n>2
-appendedbyWD2520
FCS
16
1FLAG
I
8
When this document refers to an SU as "received,"
that SU is understood to meet all the above minimum
conditions. (In some cases an error counter may be
2.0
incremented, but the SU is not considered as received unless all minimum conditions are met. See
paragraph 3.3 and Figure 5.)
PROGRAMMING THRU REGISTERS
The WD2520 is programmed by six write/read
registers, and is monitored by six status, read-only
registers.
REGISTER NUMBER
0
1
2*
3*
4*
5*
6*
7*
8
9
A
B
C
D
E
F
IA3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1A2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
IA1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
lAO
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
REGISTER NAME
CRO Control Register 0
CR1 Control Register 1
SR2 Status Register 2
SR3 Status Register 3
SR4 Status Register 4
SR5 Status Register 5
SR6 Status Register 6
SR7 Status Register 7
TIMER'
BUFFER HI
BUFFER LO
(not used)
*NOTE: SR2 thru SR7 may only be read by the CPU.
CONTROUSTATUS REGISTERS SUMMARY
REG
7
6
5
BIT NUMBER
4
3
CRO
PCRI
BASIC
0
0
0
0
X
0
0
ADRV
SR2
SR3
MSUR
XMA
ATTN
NAKR
IRTS
REC
IDLE
IRECR
CR1
SR4
X
2
1
0
LOOP
TEST
RAMT
RECR
RESET
0
K2
K1
SEND
FSNO
SR5
RECEIVER STATE
X
ATTENTION REGISTER
SR6
FIBT
FSNT
SR7
BIBT
BSNT
NOTES:
Whenever any of the three bits MSUR, XMA, or ATTN
is a 1, INTR will go low. After SR3 is read, all three
bits will return to 0, and INTR will return high.
"X" represents a bit used by the WD2520's internal
microcontroller. At any time these bits may be "1" or
"0", and are to be disregarded by the user's CPU.
Unused control bits must be left at "0".
71
PCRS
X
NL1
NLO
REGISTER
CR07
CROS
CRO
PCR/BASIC
o
CONTROL REGISTER 0
CR04
CR03
CR05
o
o
CR01
CROO
RAMT
RECR
RESET
DESCRIPTION
NAME
BIT
LOOP
TEST
CR02
CROO
RESET
This bit, when set, commands the WD2520 to reset SR2 thru SR5
to all O's, and set SR6 and SR7 to all 1's. The WD2520 will not
transmit nor accept serial data until RESET = O. RESET will go to 1
when MR is enabled.
CR01
RECR
Defines the CPU's receiver memory as initially ready (RECR 1) or
initially not ready (RECR = 0). The CPU should set RECR as part of
its initialization procedure, and clear RECR when either IRECR
(SR44) is set or when the first MSUR interrupt occurs. See
paragraph 3.1.4.
CR02
RAMT
Enables a self test for registers internal to the WD2520. (See
section 7.0 on SELF-TESTS.)
CR03
LOOP TEST
InternaliXlies TO back to RD, and TC to RC. The normal inputs of
RD and RC are logically disconnected. There will still be an output
at TO, and TC needs the transmitter clock. (See 7.0)
CR04-CROO
o
Unused control bits, like CR04, must be left at O.
CR07
PCR/BASIC
This bit selects one of two error correction procedures.
=
If CR07 = 0, the "basic" error correction method is employed
which uses retransmission, positive acknowledge, and negative
acknowledge. (See section 4.0)
If CR07 = 1, the Preventive Cyclic Retransmission (PCR) error control method is used. PCR is essentially a noncompelled forward
error correction method. (See section 5.0)
72
REGISTER
CR1
I
I
CR17
0
I
I
CR16
I
0
I
BIT
CONTROL REGISTER 1
CR15
CR14
CR13
0
I
I
CR12
I
CR11
I
I
K2
I
K1
ADRV
NAME
CR10
SEND
0
I
I
CR10
SEND
DESCRIPTION
Used to command the WD2520 to transmit the next MSU, MSU's,
or LSSU. If SEND = 1, the WD2520 will read from the next TLOOK
segment the value of RTX (See Table 3.1). If RTX 0, the WD2520
will clear SEND, and no transmission occurs. If RTX = 1, the
WD2520 will then read TSADR and LIT from the TLOOK segment,
and the buffer (either an MSU or LSSU) is transmitted. After
transmission, the WD2520 will clear RTX of the segment just
transmitted. If an MSU has been transmitted, the RTX of the next
TLOOK segment is now read, and the procedure above is repeated.
(See section 3.0) As a matter of good practice, the user's CPU
should set SEND each time a new MSU or LSSU is ready to
transmit.
=
CR12 and CR11
K2,K1
Used to define the window size. The window defines the maximum
number of outstanding (unacknowledged) MSU's allowed. The window also defines the size of TLOOK and RLOOK.
SIZE OF
TLOOKJRLOOK
(K+ 1)
NUMBER OF
OUTSTANDING
MSU'S(K)
K2
K1
o
0
8
7
1
32
128
31
127
o
1
0
CR14
ADRV
The ADRV bit is the control for the 16 bit output addresses
(AO-A15). If ADRV=O, the outputs are three-state, and are in HI-Z,
except when DACK goes low. If ADRV = 1, the outputs are always
low impedance (TTL), and are high level when DACK is high.
CR13, 15, 16, 17
o
Unused control bits.
REGISTER
I
SR27
I
SR2
I
X
I
BIT
SR26-SR20
STATUS REGISTER 2
SR26-SR20
FSNO
NAME
FSNO
DESCRIPTION
Represents the FSN value of the next transmitted MSU to be
acknowledged. FSNO relates to the particularTLOOK segment for
that MSU.
Notice that if the retransmission buffer is empty; FSNO (SR2) =
FSNT (SR6) + 1.
SR27
X
Used internally, may be 1 orO.
73
=e
C
N
REGISTER
SR3
(J1
I
SR36
I MSUR I
XMA
SR37
BIT
N
0
I
NAME
X
I
I
STATUS REGISTER 3
SR33
SR35
SR34
ATTN
I
I
X
X
SR32
X
I
I
SR31
SR30
X
X
DESCRIPTION
Used internally may be 1 or O.
SR30toSR34
SR35
ATTN
The ATTN (Attention) bit indicates that either: 1) An error
has occurred which is unrecoverable by the WD2520, or 2) A
significant event has occurred, and the CPU must be informed.
The ATTN Register (SR5) will contain the coded reason for the
ATTN interrupt.
SR36
XMA
Means that a previously transmitted, or retransmitted, MSU, or
MSU's, has been acknowledged.
SR37
MSUR
Stands for Message Signal Unit Received. This means that an MSU
was received has met the minimum conditions of section 10 and
that the received FSN was equal to BSNT + 1. (Where the BSNT
referred to is the value of BSNT before the MSU was received.)
Also, the receiver memory had to have been ready. This interrupt
also means that the SIO and SIF fields are already in RAM, the
BSNT has been incremented, and an acknowledge will be
transmitted at the next opportunity. (The "next opportunity" to
acknowledge an MSU received is with the transmission of the BSN
in the next transmitted SU.)
REGISTER
SR47
SR46
SR4
X
IRTS
BIT
NAME
STATUS REGISTER 4
SR45
SR44
SR43
REC
IDLE
IRECR
X
SR42
SR41
SR40
PCRS
NL1
NLO
NLO, NL1
DESCRIPTION
Represent a binary number for the segment where the next
received LSSU will be placed in the RLSSU (See 3.2).
SR42
PCRS
Used for internal control.
SR43
X
Used internally may be 1 orO.
SR44
IRECR
A status bit which informs the CPU that the receiver memory
through RLOOK has been set·up. The CPU should clear RECR
either when IRECR = 1, or after the first MSUR interrupt. After the
WD2520 sets IRECR, the WD2520 will not test RECR again until a
reset condition, or IJntii a C3 interrupt (see paragraph 2.3.2). Also
see paragraph 3.1.4.
SR45
RECIDLE
Indicates that the WD2520 has received at least 15 contiguous 1's.
When at least one 0 is received. REC IDLE goes to 0, and remains 0
until 15 contiguous 1's.
SR40, SR41
SR46
Stands for the Internal Request·Ta-Send bit, and indicates that the
transmitter is attempting (successful or not) to send data. If the
RTS pin (pin~is not tied to ground or WIRED·ORED to another
signal, then IRTS
RTS.
Used internally may be 1 or O.
=
SR47
X
74
REGISTER
SR5
I
I
I
STATUS REGISTER 5
SR57-SR50
AnN
BIT
NAME
SR57-SR50
AnN
DESCRIPTION
The Register shows the coded reason for the AnN interrupt. See
Table XX for description of AnN codes.
TABLE XX
ATTN Register Codes
HEXIDECIMAL
CODE
REASON
TUR. Transmitter Under-Run.
C1
C2
ROR. Receiver Over-Run.
C3
RLNR. RLOOK not ready. The RTR bit of the next RLOOK segment is O.
01
LOST LSSU. An LSSU was received, but temporarily lost, because the RTR bit of
the next RLSSU segment was O. See Table 3.1.
02
At least two out of three consecutively received FIB's indicate start of
retransmission when no retransmission was requested. OR, at least two out of
three consecutively received BSN's are not valid. A valid received BSN is defined
as less than or equal to FSNT and greater than or equal to FSNO-1.
04
The current TLOOK segment for MSU has an illegal byte count. The illegal count is
all O's, and the WD2520 will not attempt to transmit a null MSU.
20
An LSSU has been received and is in the RLSSU.
40
80
An LSSU has been transmitted.
No SU has been received within time T1.
REGISTER
SR67
(SR77)
SR6
(SR7)
FIBT
(BIBT)
STATUS REGISTERS 6 & (7)
SR66-SR60
(SR76 - SR70)
FSNT
(BSNT)
BIT
SR66-SR60
(SR76-SR70)
DESCRIPTION
NAME
FSNT
(BSNT)
The current value of transmitted FSN. SR6 is incremented prior to
the transmission of the next new MSU. SR6 applies only to new
MSU's, and not MSU's which may be retransmitted_
The expected value of the FSN of the next received MSU is SR7
plus one. SR7 (BSNT) also represents the current value of the
transmitted BSN.
FSNT and BSNT are initialized to aIl1's.
SR67
(SR77)
FIBT
(BIBT)
The current values of the transmitted FIB and BIB, respectively.
The WD2520 will invert FIBT and initiate retransmission of MSU's
in response to a received inverted BIB. If the WD2520 receives an
incorrect FSN, BIBT will be inverted on the next transmitted SUo
(NOTE: A correct received FSN is equal to FSNO for an MSU, or
FSNO-1 for an FISU or LSSU.)
FIBT and BIBT are each initialized to 1.
75
REGISTER
TR7
(0)
TR6
(0)
TIMER lSB
TIMERMSB
T7
(0)
T6
(0)
BIT
TIMER REGISTER lSB & MSB
TR5
TR4
TR3
(0)
(0)
(0)
T5
(0)
T4
(0)
T3
(0)
NAME
TR9-TRO
T9-TO
TR2
(0)
TR1
(TR9)
TRO
(TRS)
T2
(0)
T1
(T9)
TO
(T8)
DESCRIPTION
Registers 8 and 9 define a 10 bit value for timer T1. The lSB is
in Register 8, Bit 0, and the MSB is in Register 9, Bit 1. The upper
six bits of Register 9 are not used. The time of T1 is given by the
expression:
T1
where ClK
N
= 16,384 N/ClK
= Frequency of ClK input (pin 6)
= Binary value of T1 in Registers 8 and 9.
The timer is re·started each time an SU is received. If no SU is
received within T1, and AnN interrupt is generated with AnN
code 80.
REGISTER
7
6
BUFFER HI
BUFFER lO
B15
B7
B14
B6
BIT
B15-B8
B7-BO
BUFFER HI-REGISTER A
BUFFER lO-REGISTER B
4
3
5
B13
B5
B12
B4
B11
B3
1
0
B10
B2
B9
B1
B8
BO
DESCRIPTION
NAME
BUFFER HI
BUFFER lO
2
Registers A and B represent the 16 bit starting address of the 24
byte buffer. TlOOK follows that buffer. RlOOK follows TlOOK,
RlSSU follows RlOOK, and the Error Counters follow RlSSU.
(See Figure 3.) RlOOK and RlOOK will each have either 8,32, or
128 segments according to the values of K2 and K1.
Regarding the TUR and ROR errors; an ROR means
that the receiver Register (RR) had a byte to load into
the receiver FIFO, but the FIFO was full. TUR means
that the Transmitting Register (TR) needed a byte·
from the Transmitter Holding Register (THR), but the
TH R was empty. Either TUR or ROR may be caused
by one of two conditions, or both.
3.0
TRANSMITTING AND RECEIVING
PROCEDURES
Referring to Table 1.0, notice that the SF of lSSU's
and the SIO and SIF of MSU's are DMA accessed.
The DMA is part of the Memory Access Method (buf·
fer management) shown in Figure 3.
The starting address of a TlOOK (Transmitter look·
Up) table follows the 24 byte buffer which starts at
the address given in Registers A and B. TlOOK has
K + 1 segments, and each segment consists of four
bytes. TlOOK is followed contiguously by RlOOK
(Receiver look·Up) which also has K + 1 segments of
four bytes each. The value of K + 1 is programmed by
control bits CR12 and CR11.
1) The bit rate clock, TC or RC, is too fast for the
WD2520.
2) The DACK response is too slow for the bit rate.
In addition to the above, an ROR could be caused as
a result of an RlNR condition. If there is an RlNR
condition, and an MSU or lSSU is received before the
RlNR is cleared, there will be an ROR interrupt which
will override the RlNR.
RlSSU (Received lSSU's) is a four segment table
which follows RlOOK. Each segment has four bytes.
........ F
76
=e
c
r
~
CI1
ADDRESS FROM
REGAANDB
24
BYTE
WORK AREA
TLOOK
MSU #0
OR
LSSU
0
MSU #1
OR
LSSU
•
•
•
K + 1
T
LIT #0
1
LIT #1
~
RSADR #0
T
320
BYTE
LIMIT
•
•
•
1
K + 1
RLSSU(
~
TSADR #0
0
RSADR
#1
T
320
BYTE
LIMIT
~
ERROR
COUNTERS
(5 BYTES)
Figure 3
MEMORY ACCESS METHOD
NOTES:
1. ALL RAM IN THE FIGURE IS EXTERNAL TO THE WD2520.
2. K + 1
8,32, OR 128. (SEE CONTROL BITS K2 AND K1).
=
77
Lastly, there are five error counters of one byte each.
These error counters represent errors recoverable by
the WD2520, whi Ie those error conditions reported by
the ATTN Register are not recoverable by the
WD2520.
After a previously transmitted, or retransmitted,
MSU(s) is acknowledged, the XMA bit (SR36) is set
and an interrupt is generated. The ACK'ED bit in each
TLOOK segment acknowledged will have been set
prior to the XMA interrupt.
The 24 byte buffer ahead of TLOOK is to be reserved
for the WD2520 for internal control. The beginning of
this work area is defined by Registers A and B. The
WD2520 will use that work area as follows:
For all transmitted MSU's and LSSU's, TL6 and TL7
are placed in the SU's byte #3, bits 6 and 7, without
alteration.
The length of the MSU is determined as follows: If
ELFT (Extended Length Field for Transmitter), EX7,
and EX6 are all 0, the MSU will send the length equal
to LIT. Also, the LI field in the transmitted MSU will be
equal to the TLOOK segment, byte #3 (TL7, TL6, and
LIT).
OFFSET BYTE
NUMBER USE
0,1
Retransmission pointer address
2, 3
FSNO address
4,5
FSN address
6, 7
BSN address
8,9
RLOOK starting address
A, B
LSSU pointer address
C, D
E thru 17
If either ELFT, EX7, or EX6 are set to 1, an MSU with
length greater than 62 bytes will be transmitted. The
lower 6 bits of LI will be all 1'so The length of the
transmitted MSU will be the combination of EX7, EX6,
and LIT. If the MSU length is to be greater than 255
bytes, than ELFT is set to 1.
LSSU starting address
NOTE:
The WD2520 will not send an MSU with length
greater than 320 bytes. If the user attempts to put a
value greater than 320, the WD2520 will send the 320
bytes, and ABORT. However, this will allow more than
272 bytes as stated in Q.703, paragraph 2.3.8.
Reserved
Note that the WD2520 will compute the above addresses, and the user's CPU need only reserve the
space. The CPU may read the 24 byte buffer, but must
not write into that buffer.
3.1
To receive MSU's, the WD2520 will test the RTR
(Ready To Receive) bit in the next RLOOK segment
(as determined by the value of SR7 plus one). If
RTR = 1, the WD2520 will prepare to receive beginning at address RSADR (Receiver Starting Address)
with maximum buffer size of 320 bytes. If an MSU is
received (LI>2), and if the MSU meets all the conditions stated under the description of SR37, then the
WD2520 will store the received length in the lower 6
bits of byte #3 of the applicable RLOOK segment.
The RTR is cleared to 0 and MRCVD (MSU ReCeiVeD)
is set to 1 by the WD2520. After this, an interrupt is
generated with MSUR (SR37) set to 1. The WD2520
will go on to the next RLOOK segment.
Sending and Receiving MSU's
The segment number in TLOOK maintains a relationship with the transmitted FSN. The segment number
will correspond with the least significant bits of
FSNT. For example, if K + 1 = 32, the segment
numbers vary from 0 to 1F (hexidecimal) and equal
the 5 LSB's of the transmitted FSN. Thus, segment
#3 could correspond to transmitted FSN 03, 23, 43, or
63 (hexidecimal).
In like manner, the RLOOK segment has a relationship to the expected value of the received FSN, and
the actual expected FSN of the next MSU is maintained is SR7 (BSNT + 1).
For all received MSU's and LSSU's, the values of the
received SU's byte #3, bits 6 and 7, are placed in RL6
and RL7 without alteration.
To transmit an MSU, the SEND bit (CR10) must first
be set. After SEND is set, the WD2520 will go to the
next segment (as determined by the value of SR6)
and test bit RTX (Ready To Transmit). See Table 4. If
RTX= 1, the WD2520 will transmit the MSU with
length determined by LIT, ELFT, EX7 and EX6. Prior to
the transmission, FSNTwili be incremented. The SIO
and SIF fields are found in a memory block beginning
at address TSADR (Transmitter Starting ADdRess). Of
course, LI>2 for an MSU. After sending the MSU,
the WD2520 will clear RTX, and go on to the next
segment.
The received length is determined as follows: If ER7,
ER6, and ELFR are all 0, the length is contained in the
six bit number LlR, and the received length is less
than, or equal to, 63.
If an MSU of length greater than 63 bytes is received,
the received LI field will be all 1'so However, under
this condition, at least one of the bits ER7, ER6, or
ELFR will be set to 1. The LlR will contain the lower
six bits of the received length byte count. ER6 and
ER7 are added directly to LlR. If ELFR is set, an MSU
greater than 255 bytes has been received.
For example, suppose an MSU of length 70 (hex 46)
bytes is received. The LI field in the MSU will be all
1'so In the RLOOK segment, the bits ELFR and ER7
will be 0, and ER6 will be 1. LlR will be 6 (000110).
When the WD2520 reaches a segment whose
RTX=O, the WD2520 clears the SEND bit. Then, the
WD2520 will begin retransmission of the oldest MSU
(as determined by FSNO) if PCR is selected
(CR07 = 1), or the WD2520 will transmit FISU's if
BASIC is selected (CR07 = 0).
78
Like the transmitter, the WD2520 will not receive an
MSU of length greater than 320 bytes. The WD2520
will not write into received memory past 320 received
bytes per MSU.
the WD2520 would perform nearly constant DMA's
while testing RTR. To prevent this, the CPU should
set RECR after a reset, but clear RECR after either
IRECR (SR44) is set to 1, or after the first MSUR interrupt. Then, if an ATTN code C3 interrupt happens, the
CPU has the opportunity to set-up the next RLOOK
before setting RECR, and the WD2520 will not tie-up
the DMA channel.
If the WD2520 reaches an RLOOK segment with
RTR = 0, an ATTN interrupt is generated with ATTN
code C3. The WD2520 will not test that RTR again until the user's CPU sets RECR (CR01) to a 1. Therefore,
if RECR is set, but the RTR of the next RLOOK is 0,
Segment Descriptions (Note: S = Spare)
TABLE 4
7
Byte 0
ACKED
6
1
1
1
5
S
I
1
4
S
1
1
3
TSADR HI
Byte 2
TSADR LO
I TL6
Byte 3
TL7
Byte 0
MRCVD
I
1
6
S
I
I
1
5
S
I
1
4
S
1
I
3
Byte 2
RSADR LO
Byte 0
LRCVD
S
Byte 1
RL7
RL6
1
RL6
I
1
1
ELFX
I
0
RTX
1
I
2
1
ER6
1
1
1
ELFR
0
RTR
1
RLOOK
Segment
LlR (length> 2)
1
6
7
1
EX6
TLOOK
Segment
ER7
RSADR HI
RL7
I
2
LIT
Byte 1
Byte 3
1
EX7
Byte 1
7
3.2
I
S
5
S
I
I
4
S
I
I
I
I
3
S
2
1
S
I
1
1
S
1
0
RTR
LlR (1 or2)
Byte 2
First SF byte received
Byte 3
Second SF byte received
Sending and Receiving LSSU's
3.3
If an LSSU is ready to transmit, the same initial
procedure will be followed as for an MSU except that
the LIT value is 1 or 2, and ENLF, EX7, and EX6 are all
O. After the LSSU is transmitted, the SEND bit (CR10)
is cleared, and RTX is cleared. FSNT of SR6 is not
incremented, and the WD2520 does not go on to the
next segment. After transmission of the LSSU, an
ATTN interrupt with code 40 is generated.
RLSSU
Segment
Error Counters
Following contiguously after RLSSU are five a-bit
error counters. The WD2520 will increment each
counter at the occurrence of each defined event.
However, the WD2520 will not increment past 255 (all
1's). The CPU has the responsibility of clearing each
counter. The first counter past RLSSU is #0, etc.
ERROR
COUNTER
NUMBER
When an LSSU is received, the LlR will be either 1 or
2. In addition to the minimum conditions for received
SU's (see 1.0), the WD2520 will test the received FSN
to be equal to the value of SR7. If it is, the LI and SF
fields are placed in the next RLSSU segment as
determined by NL1 and NLO (SR41 and SR40)
provided that the RLSSU's segment RTR = 1. (If that
RTR = 0, an ATTN interrupt with code 01 is
generated.) The WD2520 will then set LRCVD (LSSU
ReCeiVeD) and clear RTR, and generate an ATTN
interrupt with code 20. The NL1/NLO pointer is incremented.
o
EVENT DESCRIPTION
Received SU's with FCS error
(includes ABORTed SU's where an
ABORT is 7 contiguous 1's).
Number of SU's received which
were not a multiple of a bits.
Bits TR7 and TR6 are transmitted in byte #3 bits 7 and
6 without alteration. The received bits 7 and 6 in byte
#3 are placed in ER7 and ER6 without alteration.
79
2
Received short SU's (less that 5
bytes between flags).
3
Number of SU's received incorrect
LI.
4
Number of SU's received with incorrect FSN.
:ec
N
(J1
N
o
SU
RECEIVED
INCREMENT
ERROR
COUNTER
N
#0
INCREMENT
ERROR
COUNTER
#1
N
INCREMENT
ERROR
COUNTER
N
#2
INCREMENT
ERROR
COUNTER
N
#3
Figure 5
RECEIVER FUNCTIONAL FLOW
The error counters will not be incremented unless
the received SU had a correct FCS.
3.4 Deadly Embrace Prevention
A "deadly embrace" is defined here as a state where
the user's CPU and the WD2520 are both waiting for
an action from the other. This situation could exist
unless control bits shared by the WD2520 and the
CPU are handled properly. A shared control bit is
defined as one which is either set by the CPU and
cleared by the WD2520, or is set by WD2520 and
These counters are intended for statistical purposes,
only, and are not guaranteed to be incremented at
each occurrence of the defined event.
80
cleared by the CPU. They must both not be allowed
to set or clear the same bit. The shared control bits
are shown below:
WD2520 receives a NACK, the WD2520 will begin
retransmission of MSU's with the transmitted FSN
equal to the received BSN plus one, and the transmitted FIB equal to the received BIB. However, if the
received NACK refers to an FSN not in the retransmission buffer, the NACK is discarded, but the next
transmitted FIB will still be made equal to the
received BIB. If 2 out of 3 consecutively received
BSN's reference FSN's of MSU's not in the retransmission buffer, an ATTN interrupt is generated with
code 02.
When a valid NACK is received, the WD2520 will
begin sequential retransmission starting with the
oldest MSU even if there are more new MSU's ready.
SET CLEARED
BIT
NAME
WHERE FOUND
BY
BY
SEND CR10
CPU
WD2520
RTX
each TLOOK segment
CPU
WD2520
CPU
ACK'ED each TLOOK segment WD2520
each RLOOK segment
CPU
WD2520
RTR
CPU
MRCVD each RLOOK segment WD2520
RTR
each RLSSU segment
LRCVD each RLSSU segment
CPU
WD2520
WD2520
CPU
A received NACK may also acknowledge one, or
more, previously transmitted MSU's.
Any of these bits may be set to any value by the CPU
at initialization. However, after initialization, the
deadly-embrace rule must be followed.
3.5
All previously transmitted MSU's may be
acknowledged by a received NACK. In this case, a
received NACK will have cleared the retransmission
buffer. This is an acceptable condition, and the
acknowledgements are accepted. The FIBT is inverted. However, there will be no retransmission of
MSU's.
The retransmission buffer is defined as those MSU's
awaiting acknowledgement from FSNO to FSNT.
In BASIC, retransmission will not begin unless a
NACK is received.
If the WD2520 receives an MSU with an FSN not
equal to the BSNT + 1, or if an FISU or LSSU is received with an FSN not equal to BSNT, the WD2520 will
transmit a NACK.
Initialization Procedure
Initialization begins after either the RESET bit is
cleared after having been set, or after the CFB bit is
cleared after having been set.
At initialization, transmitted FSN's and BSN's are all
1'so Transmitted FIB's and BIB's are 1.
The first transmitted MSU will have FSN = 0, and the
expected value of the FSN of the first received MSU
willbeO.
3.6
Definition of Correct LI
The LI field is found in each SU as the lower 6 bits in
the third byte following the leading flag.
5.0
LI is the byte count for the length of the SUo The
length of the SU is the number of bytes following the
LI field, but preceding the FCS.
ERROR CORRECTION BY PREVENTIVE
CYCLIC RETRANSMISSION (PCR)
In the PCR procedure, previously transmitted, but
unacknowledged, MSU's are sequentially retransmitted whenever there are no new MSU's or LSSU's
to transmit. This procedure is employed if CR07 = 1.
For an FISU, LI = 0, and a correct LI means that the
FCS field will immediately follow the LI field.
The absence of new MSU's or LSSU's is determined
if the RTX bit of the next TLOOK segment is 0, or if
SEND (CR10) is 0, or if there are K outstanding MSU's
(K= 7, 31, or 127 depending on control bits K2 and
K1). If there are no new MSU's or LSSU's to transmit,
and if the retransmission buffer is not empty, the
WD2520 will begin retransmission with the oldest
MSU. If there are no new MSU's or LSSU's, and if the
retransmission buffer is empty, the WD2520 will
transmit continuous FISU's.
PCR does not require a NACK to be received before
beginning retransmission. However, received
NACK's are treated the same in PCR as in BASIC.
Also, the WD2520 may send a NACK in PCR just as in
BASIC.
The CPU must determine when the maximum
number of bytes available for retransmission (NMAX)
has been reached. NMAX, measured in bytes, is the
total of the lengths of the MSU's in the retransmission buffer. When NMAX is reached, the CPU
For an LSSU, LI = 1 or 2, and a correct LI means that
there are 1 or 2 bytes in the SF field (corresponding to
LI).
A correct LI for an MSU wi II meet either one of two
conditions:
For MSU's with lengths from 3 to 63, the LI must
equal the number of bytes in the length of the MSU.
For MSU's which are 63 bytes, or longer, the LI will be
maintained at a value of 63 (six 1's).
4.0 "BASIC" ERROR CORRECTION METHOD
In the basic method, previously transmitted, but
unacknowledged, MSU's are not retransmitted
unless a NACK (Negative ACKnowledge) is received.
The WD2520 will employ this procedure when
CR07=0.
A NACK is defined as an SU with the BIB inverted
from the previously transmitted SUo When the
81
must not allow new MSU's to be transmitted by insuring that the RTX bit of those new MSU's is zero.
However, new LSSU's may be transmitted. When the
CPU has determined that new MSU's may be transmitted (because some of the retransmission buffer
has been removed by received acknowledgements),
then the CPU may add new MSU's.
are sequentially retransmitted beginning with FSNO.
A. NACK received with received BSN greater than or
equal to FSNO, but less than FSNT.· Notice that
this condition requires that the retransmission
buffer is not empty. (The retransmission buffer is
empty when FSNT + 1 = FSNO).
B. PCR procedure, and no new MSU's nor LSSU's
ready, and retransmission buffer not empty.
C. PCR procedure, and there are K outstanding
MSU's.
SUMMARY OF CONDITIONS FOR
TRANSMISSION
No SU's will be transmitted until RESET (CROO) and
CFB (CR17) are both 0, and CTS (pin 22) is low. Given
these conditions, the WD2520 will always be
transmitting SU's. If there are no MSU's nor LSSU's
to send, the WD2520 will send FISU's.
The following conditions require that RESET = 0 and
that CTS is low. In the following paragraphs, the
following conventions are used: X means "don't
care." (N) refers to the applicable TLOOK segment.
6.0
7.0
INTERNAL RAM TEST
There are eleven 8-bit registers in the WD2520 which
are not directly accessible by the user's CPU. Four of
these cannot be completely tested by using loopback. Therefore, this test was created as a means to
test those four internal registers. The contents of
Register A are placed in two even internal registers,
and the contents of Register B are placed in two odd
internal registers. The four registers are then added
together, without carry, and the results are placed in
Registers SR2, SR5, SR6, and SR7. This test is initiated when RAMT (CR02) is set to 1 provided RESET
(CROO) is also set to 1. Use the following procedure:
1. Insure RESET = 1
2. Set RAMT
3. Set-Up Registers A and B
4. Wait at least 150 times the CLK period
5. Check the results in Registers SR2, SR5, SR6, SR7
To repeat the test for new values in Registers A
and B:
6. Clear RAMT
7. Wait at least 120 times the CLK period
8. Go back to step 1
During the execution of this test, the ROM 10 code of
the WD2520 will be displayed in the lower 5 bits of
SR4.
CONDITIONS FOR SENDING AN LSSU
SEND = 1
CR07 = X
RTX(N) = 1
LlR(N) = 1 or 2
After sending the LSSU, RTX(N) and SEND are
cleared to O.
CONDITIONS FOR SENDING AN FISU
Either condition A or B below will cause an FISU to
be transmitted.
A. "Basic" procedure selected, and no new MSU's
nor LSSU's ready for transmission, and no retransmission in progress.
B. PCR procedure selected, and no new MSU's nor
LSSU's ready for transmission, and the retransmission buffer is empty.
SEND = 0
CR07 = 1
FSNT (SR6)
SELF TESTS
There are two self tests: 1) An internal RAM test, and
2) A loop-back test. Both tests are suitable for
manufacturing testing, user incoming inspection
testing, diagnostics, and trouble-shooting.
+ 1 = FSNO (SR2)
CONDITIONS FOR SENDING AN MSU FOR THE
FIRSTTIME
In either "basic" or PCR, the conditions below will
cause an MSU to be transmitted for the first time.
After the transmission is complete, RTX(N) is cleared
to O. FSNT (SR6) is incremented prior to the transmission of that MSU.
CONDITIONS FOR RETRANSMITTING AN MSU
LOOP-BACK TEST
The internal loop-back condition exists whenever
CR03 = 1. TD is tied back to RD and TC is tied to RC.
The inputs, RD and RC are gated-out, but the TO
output is still present.
When running this test, it is recommended that
MSU's be transmitted and received and the SIO and
SIF fields be checked. The transmitted and received
SIO and SIF fields should be identical. When this is
done, the entire DMA and buffer management is
tested as well as the transmitter and receiver.
Retransmission of one or more MSU's will occur
whenever conditions A, B or C below are met. MSU's
LSSU's may also be transmitted and received in loopback.
SEND = 1
CR07 = 0
RTX(N) = 1
LlR(N) >2
There are less than K outstanding MSU's
Il
82
8.0
GLOSSARY OF TERMS
BASIC
BIB
BIBT
BSN
BSNT
F
FCS
FIB
FIBT
FISU
FSN
FSNO
LI
LSSU
MSU
NACK
NMAX
PACK
PCR
SF
SIF
SIO
SU
SU length
The "basic" error correction method
Backward Indicator Bit (1 bit)
BIB to be transmitted
Backward Sequence Number (7 bits)
BSN to be transmitted
Flag
Frame Check Sequence
Forward indicator Bit (1 bit)
FIB to be transmitted
Fill In Signal Unit(L=O)
Forward Sequence Number (7 bits)
FSN of next transmitted MSU to be acknowledged (Also called FSN of oldest MSU in retransmission buffer)
Length Indicator (1 byte field)
Link Status Signal Unit (L = 1 or 2)
Message Signal Unit (L>2)
Negative ACKnowledgement
A procedure which complements PCR, and is used to limit the number of bytes available for
retransmission.
Positive ACKnowledgement
Preventive Cyclic Retransmission (one of two error correction methods)
Status Field (1 or 2 byte field in an LSSU)
Signalling information Field (2 or more byte field in an MSU)
Service Indicator Octet (1 byte field in an MSU)
Signal Unit (may be FISU, LSSU, or MSU)
The number of bytes in an SU after the LI field, but before the FCS.
83
9.0
WD2520 ELECTRICAL SPECIFICATIONS:
ABSOLUTE MAXIMUM RATINGS:
Voltages referenced to VSS
High Supply Voltage (VDD) . . . . . . . . . .. - 0.3 to 15V
Voltage at any Pin .................. - .03 to 15V
Operating Temperature Range ...... O°C to + 70°C
Storage Temperature Range. . .. - 55°C to + 125°C
NOTE:
Maximum limits indicate where permanent device
damage occurs. Continuous operation at these limits
is not intended and should be limited to those
conditions specified in the DC Electrical characteristics.
Operating OC Characteristics: VSS
SYMBOL
100
lee
VOD
Vee
VIH
Vil
VOH
VOL
ILH
10ZH
10Zl
= OV, VCC = 5.0V ±
PARAMETER
VOO Supply Current
Vee Supply Current
High Voltage Supply
low Voltage Supply
Input High Voltage
Input low Voltage
Output High Voltage
Output low Voltage
Input leakage Source
orSink
Input leakage High
Impedance
Output leakage High
Impedance
MIN
11.4
4.75
2.4
.25, VSS = 12.0V ± .6V TA = 0° to 70°C
TYP
MAX
UNIT
20
200
12
5
70
280
12.6
5.25
0.4
mA
mA
V
V
V
V
V
V
10
uA
10
uA
Vin = Vec
10
uA
Vin = VSS
0.8
2.8
84
CONDITIONS
10= -0.1mA
1.6mA
10 =
AC Timing Characteristics: VCC = 5V ± .25; VDD = RV ± .6V, VSS = OV, TA = 0° to 70°C
SYMBOL
PARAMETER
TYP
MIN
MAX
2.0
UNIT
MHz
ClK
Clock Frequency
RC
Receive Clock Range
0
MHz
Note 3, 4
TC
Transmit Clock Range
MHz
Note 4
0.5
Note 1, 2
MR
Master Reset Pulse Width
0
10
TAR
Input Address Valid to RE
0
TRD
Read Strobe (or DACK
Read) to Data Valid
375
ns
THO
Data Hold Time From Read
to Strobe
80
nS
THA
Address Hold Time From
Read Strobe
80
ns
TAW
Input Address Valid to
Trailing Edge of WE
200
nS
TWW
Minimum WE Pulse Width
200
nS
TDW
Data Valid to Trailing Edge
of WE or Trailing Edge of
DACK for DMA Write
100
nS
TAHW
Address Hold Time After
WE
80
nS
TDHW
Data Hold Time After WE or
After DACK for DMA Write
100
nS
TDA1
Time From DROO (or DROI)
to Output Address Valid if
ADRV = 1
80
nS
TDAO
Time From DACK to Output
Address Valid if ADRV = 0
400
nS
Note 5
TDD
Time From leading Edge of
DACK to Trailing Edge of
DROO (or DROI)
400
nS
Note 5
TDAH
Output Address Hold Time
From DACK
100
nS
TDMW
Data Hold Time From DACK
For DMA Read
100
nS
TRP1
REPLY Response Time
(leading edge)
240
nS
Note 5
TRP2
REPLY Response Time
(trailing edge)
260
nS
Note 5
mS
nS
NOTES:
1.
2.
3.
4.
5.
CONDITIONS
Clock must have 50% duty cycle.
Buffer chaining is not guaranteed when ClK is greater than 1.5 MHz.
Residual bit detection logic not guaranteed when RC is greater than 50Kbps.
See "Ordering Information" for maximum serial rates.
C(load) = 100pf
85
Note 5
DMA TIMING
DMAIN
DMA OUT
rTD?
DRQO
AO-A15
(ADRV
0)
=
AO-A15
(ADRV
1)
=
(AO-A15 SAME AS DMA READ)
I
I
;;
DRQI~
I!DA~I-1 J~~~"-A~
'
't~
_____ }
y ________
DACK
I
DALO-DAL7
<
~-.J
~
TDMW
Y
DACK
DALO-DAL7
1_ TDAH
iTDD-j
~/
/
-.j T DW~TDHW-I
(
DATA VALID
>--
r-
DATA VALID )
~TRD--l
I
CPU READ/WRITE TIMING
CPU READ
CPU WRITE (CS IS
(CS IS LOW)
IAO-IA3==><~_ _ _ _ _ _ _----.Jr,--___
I
RE
LOW)
v---
---v
IAO-IA3
_ -t4~-----:T=-/!I.-W------~
WE---~~r----TWW--~~r-=---
t=TDW-1
DALO-D:..:..A=L_7_ _ _ _ _+----<
DALO-DAL7
-------+----~
'----=----REPLY------~r
REPLY------~~
~TRP1~
~---------------------~---------------------~
* NOTE: There must not be a CPU read or write (CS-RE or CS-WE) within 500 nanoseconds after the trailing
(rising) edge of DACK.
There must not be the leading (falling) edge of DACK allowed within 500 nanoseconds after the
completion of a CPU write (CS-WE)_
RE and WE must not be low at the same time_
ORDERING INFORMATION
ORDER NUMBER
WD2520T-01
WD2520T-05
WD2520T-11
MAXIMUM RATE
100 Kbps
500 Kbps
1_1 Mbps
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
speCifications at anytime without notice.
86
Printed in US.A
WESTERN DIGITAL
c
o
R
p
o
A
R
T
/
o
N
WD2840 Local Network Token Access Controller
FEATURES
• Broadcast Medium Oriented (Coax, RF, CATV, IR,
etc.)
nodes. WD2840's will be designed into process
control equipment, micro-computers, mini-computers, personal computers, proprietary micro-processor based applications, intelligent terminals, frontend processors, and similar equipment.
The great advantage for the design engineer is the
ease with which he can implement a local network
function. The WD2840 handles autonomously all
major communications tasks as they relate to the
local network function.
• Up to 254 nodes
• Dual DMA/Highly efficient Memory Block
Chaining
• Token based protocol
• Acknowledge option on each datagram
• Adjustable fairness, stations may be prioritized
• Frame format similar to industry standard HDLC
• Supports Global Addressing
• Diagnostic Support: Self-Tests, System and
Network
GENERAL DESCRIPTION
The WD2840 is a MaS/LSI device intended for local
network applications, where reliable data communications over a shared medium is required. The device
uses a buffer chaining scheme to allow efficient
memory utilization. This scheme minimizes the host
CPU time requirements for handling packets of data.
The WD2840 frees the host CPU from extensive
overhead by performing network initialization, addressing, coordination, data transmission, acknowledgements and diagnostics.
• TTL Compatible
APPLICATIONS
The WD2840 is a general purpose Local Network
Token Controller applicable to virtually all types of
multi-point communications applications. The token
protocol allows the sharing of one bus by up to 254
r- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - :
I
DALO-7,IAO-3
--------1
ROM
1
1
I
!
REGISTER
~--~
FILE
(16 HOST
VISABLE)
TC
CONTROL
DMA
I
I
DMAREGS
(2 CHAN)
IL _________________________________ - _____ - --II
PIN DESIGNATION
BLOCK DIAGRAM
Figure 1_1
87
=e
c
N
8
CONTENTS
Introduction ............................................................................ .
Scope................................................................................. .
1.0
General Description ...................................................................... .
1.1
Pin Definitions .................................................................... .
1.2
Device Architecture ................................................................ .
1.3
Register Definitions ................................................................ .
1.4
Diagnostic Aids ................................................................... .
1.4.1
Self Tests .................................................................. .
1.4.2 System Diagnostics .......................................................... .
1.4.3
Network Diagnostics ......................................................... .
2.0
Interfaces .............................................................................. .
2.1
Host ............................................................................ .
2.1.1
Event Counters ............................................................. .
2.1.2
Transmit Memory Interface .................................................... .
2.1.3
Receive Memory Interface ..................................................... .
2.2
Modem Interface .................................................................. .
3.0
Network Protocol ....................................................................... .
3.1
Data Transmission ................................................................. .
3.2
Access Method .................................................................... .
3.2.1
Initilization/Error Recovery .................................................... .
3.2.2
Station Removal ............................................................ .
3.2.3
Interaction of the Sub-Protocols ................................................ .
3.3
Frame Format ..................................................................... .
4.0
Electrical Specification ................................................................... .
5.0
Timing Characteristics ................................................................... .
6.0
Ordering Information ..................................................................... .
RELATED DOCUMENTS
Consult Western Digital Corporation for current application notes and related documents.
WD2840 LOCAL NETWORK
TOKEN ACCESS CONTROLLER
The WD2840 is designed to logically interconnect 2
to 254 user devices over a shared communications
medium. Examples of expected mediums include
coax cable, twisted pair bus, RF, and CATV. All
network control functions, such as data framing and
error checking, destination filtering, fair and adjustable transmission scheduling, and network
initialization and fault recovery (caused by noise for
example) are handled completely by the WD2840.
The protocol implemented allows guaranteed station
access intervals allowing applications in factory
automation and other critical communications environments where "statistical delays" are not acceptable. The WD2840 token protocol also allows the
addition and/or removal of stations to a network at
anytime, including while operating.
INTRODUCTION
The WD2840 is a single LSI device which gives
systems designers the ability to include networking
capabilities into their unique products simply and
economically.
A general and fundamental advantage to the use of
complex LSI in a given system is the partitioning of
required technical expertise. A successful user of the
WD2840 need not be a data-communications expert,
and further, he need not be at all concerned with low
level network details (though these details are documented and available to him if he is interested). The
potential user of the WD2840 must simply evaluate
the communications facilities provided by the device
to determine its suitability for the intended use.
88
tails of the communications protocol implemented
by the WD2840 Token Access Controller.
The document is organized into three main sections:
SECTION ONE is much like a traditional data sheet
including register descriptions, pin definitions, and
hardware architecture.
SECTION TWO describes the interfaces to the
WD2840. The network side is conventional, the host
side consists of an elaborate DMA interface with
control blocks and WD2840/host handshaking.
SECTION THREE details the network protocol implemented by the device. Normal operation, initialization, and the handling of error conditions are
described.
Serious attention has also been given to the user's
interface to the device. The interface is a combination of conventional 1/0 registers and an
elaborate DMA buffer chaining interface. This
chaining feature allows the user much more efficient
use of his system memory, particularly in situations
where the maximum message sent over the network
is much longer than the average size. This feature
also allows the automatic queueing of messages
independently of the user's consumption rate, in
effect, speed decoupling the user's CPU and
processing requirements from the network.
The WD2840 has several parameters (registers) that
allow tailoring to the user's requirements. In this way,
network priority and access ordering, to name two,
can be manually set if desired.
Using an integrated version of these network
algorithms saves not only the development costs
already mentioned, but further, the total processing
power required for the user's application is not increased. In other words, a CPU upgrade can likely be
avoided by "distributing" the network processing
task into LSI devices such as the WD2840.
SCOPE
This document differs from traditional LSI data
sheets in that it details not only the LSI implementation of a function, but also defines the overall function in detail. Specifically, this document includes de-
MEDIUM
CPU BUS
TO
AO·15
ORal
WD2840
TC
DRao
RTS
DACK
CTS
DALO-?
RD
cs
RC
WE
so
FiE
IAO-3
INTR
MR
TYPICAL SYSTEM CONNECTION
89
MODEM
1.1
PIN DEFINITIONS
PIN NUMBER
SYMBOL
PIN NAME
FUNCTION
1
DNC
DO NOT CONNECT
Leave pin open.
2
SQ
SIGNAL QUALITY
An active low input which signals the WD2840
that a frame may be received. The modem may
negate this signal if its receive signal quality is
below a reliability threshold, ensuring that the
WD2840 will not accept the frame.
3
WE
WRITE ENABLE
The data on the DAL are written into the
selected register when CS and WE are low. RE
and WE must not be low at the same time.
4
CS
CHIP SELECT
Active low chip select for CPU control of 1/0
registers.
5
RE
READ ENABLE
The content QL!he selected register is placed
on DAL when CS and RE are low.
6
CLK
CLOCK
Clock input used for internal timing.
7
MR
MASTER RESET
Initialize on active low. All registers reset to
zero, except control bit ISOL is set to 1. DACK
must be stable high before MR goes high.
DALO·7
DATA ACCESS LINES
An 8-bit bi-directional three-state bus for CPU
and DMA controlled data transfers.
16
RD
RECEIVE DATA
Receive serial data input.
17
RC
RECEIVE CLOCK
This is a 1X clockJ!!put, and RD is sampled on
the rising edge of RC.
18
VSS
TC
GROUND
Ground.
19
TRANSMIT CLOCK
A 1X clock input. TD changes on the falling
edge ofTC.
20
TD
TRANSMIT DATA
Transmitted serial data output.
21
RTS
REQUEST-TO-SEND
An open collector output which goes low when
the WD2840 is ready to transmit either data or
flags.
22
CTS
CLEAR-TO-SEND
An active low input which signals the WD2840
that transmission may begin.
23
DRQO
DMA REQUEST OUT
An active low output si9ral to initiate CPU bus
request so that the WD2840 can output onto the
bus.
24
DRQI
DMA REQUEST IN
An active low output signal to initiate CPU bus
requests so that data may be input to the
WD2840.
25
DACK
DMA ACKNOWLEDGE
An active low input from the CPU in response to
DRQO or DRQI. DACK must not be low if CS
and RE are low or if CS and WE are low.
26-41
AO-A15
ADDRESS LINES OUT
Sixteen address outputs from the WD2840 for
DMA operation.
VDD
INTR
POWER SUPPLY
+ 12VDC power supply input.
INTERRUPT REQUEST
An active low interrupt service request output.
Returns high when Interrupt Register is read.
IAO-IA3
ADDRESS LINES IN
Four address inputs to the WD2840 for CPU
controlled read/write operations with registers
in the WD2840. If ADRV = 0, these may be tied
to AO-A3.
VCC
POWER SUPPLY
+ 5VDC power supply input.
8·15
42
43
44-47
48
90
terrupt Event Register, a Counter Register and a
variety of Parameter Registers. In general the host is
responsible for defining these registers (except certain host read-only registers: SRO-2, IRO, CTRO and
NA) to contain proper and meaningful values prior to
entering Network Mode from Isolate State. Furthermore, while the WD2840 is in Network Mode, the
CBP (H,L) and MA registers must not be changed by
the host. Register NAR may be changed arbitrarily
but will only be considered by the WD2840 in
response to the NEWNA (CR10) control bit being set.
The two Control Registers and the TA, TD, AHOLT,
TXLT registers may change dynamically to control
the behavior of the WD2840.
1.2 DEVICE ARCHITECTURE
A detailed block diagram of the WD2840 is shown in
Figure 1.1.
Mode control and monitor of status by the user's
CPU is performed through the Read/Write Control
circuit, which reads from or writes into registers
addressed by IAO-IA3.
Transmit and receive data are accessed through DMA
control. Serial data is generated and received by the
bit-oriented controllers.
Internal control of the WD2840 is by means of three
internal micro-controllers; one for transmit, one for
receive, and one for overall control.
Parallel transmit data is entered into the Transmitter
Holding Register (THR), and then presented to the
Transmitter Register (TR) which converts the data to a
serial bit stream. The Frame Check Sequence (FCS)
is computed in the sixteen bit CRC register, and the
results become the transmitted FCS.
REG
Parallel receive data enters the Receiver Holding
Register (RHR) from the 24 bit serial Receive Register
(RR). The 24-bit length of RR prevents received FCS
data from entering the RHR. The receiver CRC
register is used to test the validity of the received
FCS. A three level FIFO is included in the receiver.
The WD2840 sends all information, network control
and user data, in blocks called frames. Each frame
starts and ends with a single flag (binary pattern
01111110). In between flags, data transparency is
provided by the insertion of a zero bit after all
sequences of five contiguous one bits. The receiver
will strip the inserted zero bits. (See section on frame
format for location of address, control, and FCS
fields.)
[1]
0
1
2[2]
3[2]
4[2]
5[2]
6[2]
7[2]
8
9
A
NAME
DESCRIPTION
CRO
CR1
SRO
IRO
SR1
SR2
CTRO
NA
TA
TD
CBPH
B
C
D
E
F
CBPL
NAR
AHOLT
TXLT
MA
Control Register 0
Control Register 1
Status RegisterO
Interrupt Event Register
Status Register 1
Status Register 2
Counter Register 0
Next Address
ACKTimer
Net Dead Timer
Control Block Pointer
(MSB)
Control Block Pointer (LSB)
Next Address, Request
Access Hold-off Limit
Transmit Limit
My Address
=
[1]
Hexadecimal representation of IAO-IA3.
[2] = CPU read only, write not possible.
1.3 REGISTER DEFINITION
Control, status, and interrupt bits will be referred to
as CR, SR, or IR, respectively, along with two digits.
For example, SR21 refers to status register #2 and bit
1, which is "STATE."
The WD2840 is controlled and monitored by sixteen 8
bit registers. This set of registers consists of two
Control Registers, three Status Registers, an In-
91
SUMMARY -
CONTROL, STATUS, INTERRUPT REGISTERS
REGISTER
7
6
5
BIT #
4
3
2
1
0
CRO
TXDEN
TXEN
RXEN
TOFF
ILOOP
COpy
NOINT
ISOL[1J
CR1[2J
CR1[4J
DIAGC
DIAGC
PIGT
0
INIT
0
ADRV
ADRV
GIRING
DMAT
0
LOOPT
0
RAMT
NEWNA
NUDIAG
SRO
LASTF
SENDACK
L2
0
BSZ3
SR1
TAOUT
IRTS
RECIDL
1
1
1
1
1
SR2
NXTTO
NXTRO
TR
ACKRQ
RETRY
TSENT
STATE
INRING
IRO[3J
ITUR
IROR
INS
ITRAN
IREC
ITOK
ITA
ITD/M
.. .
BSZ2
.. .
BSZ1
...
BSZO
NOTE: ZERO BITS (0) SHOWN ABOVE ARE RESERVED AND SHOULD NOT BE USED.
NOTES:
[1J = Set to 1 on power-up or master reset.
[2J = Non diagnostic mode only (CR17 -DIAGC cleared).
[3J = Any bit set causes host interrupt (INTR goes true) when Master Interrupt Suppress (CR01) is clear: All
bits are cleared when register is read by the host.
[4J
=Diagnostic State only (CR17-DIAGC set). See diagnostic section for register usage in diagnostic mode.
CRO -
CONTROL REGISTER 0 DEFINITION
REGISTER
CR07
CROS
CR05
CR04
CR03
CR02
CR01
CROO
CRO
TXDEN
TXEN
RXEN
TOFF
ILOOP
COPY
NOINT
ISOL
BIT
NANIE
DESCRIPTION
CROO
ISOL
Isolate. Set true on power up or master reset. Host clears this bit after the host
memory based WD2840 control block and other WD2840 registers have been set
up. May be set by the host at any time (will be ignored if WD2840 is in diagnostic
state). There is some delay for the WD2840 to respond to any state change request.
A state change to network mode is acknowledged by the state confirmation status
bit (SR21-STATE) being cleared. Setting ISOL while the WD2840 is in Network State
will cause a state change to Isolate State, confirmed by an interrupt event (IROOITM) and the STATE status bit (SR21) being set. This transaction will be delayed
until the node does not possess the token. Any in-progress frame transmission will
be completed normally (at the current frame, regardless of queue length), followed
by a normal token pass sequence.
CR01
NOINT
Master Interrupt Suppress. When clear, the WD2840 will generate host interrupt
requests (INTR low) if any bit in the WD2840 interrupt request register (IRO) is set.
When set, only the interrupt request is suppressed, not the setting of bits in IRO.
Note that any interrupt request will be dropped by the WD2840 when IRO is read
since this will clear IRO.
CR02
COPY
Enables COPY mode. When set causes all received data frames to be accepted
and DMA'ed into memory regardless of destination address. (See description in
Diagnostics Section.)
CR03
ILOOP
Instructs the WD2840 to loop data internally from transmitter to receiver: Used with
the LOOP diagnostic. Must NOT be set while in network mode (CROO-ISOL clear).
CR04
TOFF
When set causes WD2840 to ignore timers. This is NOT intended to be used in an
operational network but is provided to support network diagnosis. CAUTION: This
control bit disables all automatic network error recovery.
92
BIT
NAME
DESCRIPTION
CR05
RXEN
Receive Data Enable. When clear, the WD2840 still makes normal responses to
supervisory frames (scan, token pass), but will not DMA any data frames into
memory and ignores the receiver buffer chain. However any data frame which is
addressed to this node and for which an ACK is requested, will be NAK'ed with a
"receiver not enable" Nak code. When RXEN is set, it allows the receiver to DMA
appropriate data frames into memory. RXEN may be arbitrarily set and reset while
in Network State but changes will not affect any frames in progress.
CR06
TXEN
CRO?
TXDEN
NOTE: Even when RXEN is clear, the WD2840 is "following" the receiver buffer
chain with an internal register pointing either to the next available buffer (NXTRO
set) or, if the chain is exhausted, to a link field of zero (NXTRO clear). The constraints on host manipulation of the receiver buffer chain are the same regardless
of the state of RXEN. See the subsequent section on Receiver Memory Interface
for more details.
Master Transmit Enable. When clear no transmissions will occur and the transmit
buffer chain will be ignored. When set, transmission activity is further dependent
upon TXDEN (CRO?).
NOTE: Even when TXEN is clear, the WD2840 is "following" the transmitter buffer
chain with an internal register pointing either to the next frame to transmit (NXTTO
set) or, if the chain is exhausted, to a link field of zero (NXTTO clear). The constraints on host manipulation of the transmitter buffer chain are the same regardless of the state of TXEN. See the subsequent section on Transmitter Memory
Interface for more details.
Data Transmit Enable. Has no meaning unless TXEN is set. When set in conjunction with TXEN, normal WD2840 transmission of data and supervisory frames
will occur. When clear and with TXEN set, only data frame transmission will be
suppressed. That is, token pass and Ack/Nak supervisory frames will still be
transmitted when appropriate.
NOTE: The note above forTXEN applies.
CR1 - CONTROL REGISTER 1 DEFINITION
REGISTER
CR17
CR16
CR15
CR14
CR13
CR12
CR11
CR10
CR1
CR1
DIAGC
DIAGC
PIGT
0
INIT
0
ADRV
ADRV
GIRING
DMAT
0
LOOPT
0
RAMT
NEWNA
NUDIAG
BIT
NAME
DESCRIPTION (CR17 = 0, Network mode)
CR10
NEWNA
Update NA register. When set causes WD2840 to copy the contents of register
NAR into register NA. The WD2840 clears this bit after the function is complete.
This mechanism allows the host to define the WD2840's successor in the logical
ring. The node's next token pass will be to the new NA node.
NOTE: The normal token pass recovery applies. If the token pass to the new NA is
not successful, a normal scan sequence will occur where the WD2840 attempts a
single token pass to each node address in numerical sequence until a successful
pass occurs or the node's address itself is reached.
(Not used, Reserved.)
(Not used, Reserved.)
Get in logical ring. Instructs the WD2840 to gain entry into the logical ring at the
next opportunity (Le. respond to a token pass). The INRING status bit (SR20) is
confirmation; when INRING is set, it indicates that the WD2840 is participating in a
logical ring of at least two nodes. If the host clears GIRING while INRING is set,
the WD2840 will not accept the next token pass to it at which time INRING will be
cleared as confirmation.
CR11
CR12
-
CR13
GIRING
93
BIT
NAME
DESCRIPTION (CR17 = 0, Network mode)
CR14
ADRV
Address Driver Enable. Enables the sixteen output address (AO-A 15). If ADRV
0,
the outputs are tri-state and are in HI-Z, except when DACK goes low. If ADRV
1, the outputs are always TTL levels.
CR15
INIT
Network Initialization Enable. When clear, the WD2840 will not attempt to
(re)initialize the network if the net dead timer (TO) expires. When set, TO timer
expiration causes the WD2840 to enter Scan Mode. In this mode it transmits a
token pass frame to each node numerically higher in address, one after another,
until either network activity occurs (another node responds) or until the node's own
address is reached. When Scan Mode begins, the first node address used is the
then current NA (Next Address) node address. This value is derived from and is
affected by the following actions:
=
1.
2.
3.
=
At transition into Network State it defaults to MA + 1.
It may be set by the host using the NAR register and the NEWNA (CR10)
control flag.
Upon receipt of a Scan Mode frame, NA is redefined to MA + 1.
The successful initialization of the network by Scan Mode causes NA to be defined
as the first responding node (hence, this node's successor).
All node address computations are ascending and circular within the valid node
address range of 1-254.
NOTE: Since this network initialization activity comes about because of a timer
expiration, TOFF (CR04) must be clear.
CR16
PIGT
CR17
DIAGC
CR1 -
If set, instructs WD2840 to piggy back token on last data frame transmitted. This
request is honored if the last frame is determined as a result of limit TXLT or the
LAST bit set in the TFSB, but not if transmission ends due to the reaching of the
end of the chain.
Enables diagnostic mode. In network mode this bit should be zero.
CONTROL REGISTER 1 DEFINITIONS
BIT
NAME
DESCRIPTION (CR17 = 1, Diagnostic mode)
CR10
NUDIAG
Perform a new diagnostic. When set causes WD2840 to perform the selected
diagnostics. The host initializes the appropriate registers for the particular
diagnostiC and by setting this bit can initiate the test. The WD2840 clears this bit
after completion of the diagnostic.
CR11
RAMT
Selects internal RAM test if in diagnostic mode.
CR12
LOOPT
Selects Loop Test if in diagnostic mode.
CR13
DMAT
Selects DMA Test if in diagnostic mode.
CR14
ADRV
Address Driver Enable. Enables the sixteen output address (AO-A15). If ADRV
0,
the outputs are tri-state and are in HI-Z, except when DACK goes low. If ADRV
1, the outputs are always TTL levels.
CR15
-
CR16
CR17
DIAGC
=
=
(Not used, Reserved.)
(Not used, Reserved.)
Enables diagnostic mode. Confirmation of diagnostic mode is via status bit STATE
(SR21). When DIAGC and STATE are both set, diagnostiC functions of CR1 apply.
When DIAGC is cleared, after the selected set of diagnostics in progress complete, the WD2840 will transition to the Isolate state. This transition will cause an
interrupt event (ITM).
94
SRO - STATUS REGISTER 0 DEFINITION
REGISTER
SR07
SR06
SR05
SR04
SR03
SR02
SR01
SROO
SRO
LASTF
SENDACK
L2
0
BSZ3
BSZ2
BSZ1
BSZO
BIT
NAME
DESCRIPTION
SROO
BSIZ
Buffer Size, multiples of sixty-four bytes (the multiple ranges from a to 15, meaning
buffers are 64 to 1024 bytes). This is an indication only (Le. read only). The value is
obtained from the host memory-based WD2840 control block which is read when
the WD2840 transitions from Isolate State to Network State (see ISOL-CROO). See
the subsequent section on memory interface for more details.
....
SR03
SR04
-
Not used.
SR05
L2
An internal flag set during frame transmission if the length value of the current
frame is equal to eight. For normal data frame transmission this means the frame
has no data field and for transparent frame transmission this means the frame is an
access control frame.
SR06
SENDACK
An internal flag set during data frame reception to indicate that the incoming frame
should be acknowledged (send ack/nak frame). This flag is cleared when the
acknowledgement has been transmitted.
SRO?
LASTF
An internal flag set during data frame transmission to indicate that the current
frame will be the last to be transmitted during this access period. Five situations
can cause this to occur: 1) ISOL (CROO) becoming set, 2) TXDEN (CRO?) becomes
clear, 3) current frame flagged (via FSB) to be "last frame," 4) the current token
frame count reaching the TXLT limit, 5) transmitter under-run detection. Note in
particular that the last frame in the transmit queue will not cause LASTF to set
since it's being last is not known until frame end. Also if a piggy-back token is permitted (CR16 set) and no acknowledge is requested (via FSB), the token will be piggybacked on the current (last) data frame. LASTF is not cleared until the next data
frame transmission begins.
SR1 - STATUS REGISTER 1 DEFINITION
REGISTER
SR17
SR16
SR15
SR14
SR13
SR12
SR11
SROO
SR1
TAOUT
IRTS
RECIDL
1
1
1
1
1
BIT
NAME
SR10
....
-
DESCRIPTION
(Not used, reserved.)
SR14
SR15
RECIDL
SR16
IRTS
SR1?
TAOUT
Receiver Idle. Indicates the WD2840 has received at least 15 contiguous ones.
Internal Request To Send. Indicates the transmitter is attempting (successful or
not) to send either data or flags. If the RTS pi n is not tied to ground or WI RE-ORED
with another signal, then IRTS = RTS.
Timer TA expired.
95
SR2 - STATUS REGISTER 2 DEFINITION
BIT
NAME
DESCRIPTION
SR20
INRING
In logical ring. Indicates the node has had the token and has successfully passed it
at least once (therefore it is included in a logical ring of at least two nodes). See
GIRING (CR13) for other comments.
SR21
STATE
SR22
TSENT
Mode confirmation. Depending on DIAGC (CR17), the WD2840 is either in Isolate or
Diagnostic state. When ISOL (CROO) is set, STATE set confirms the WD2840 is not
in Network State. When ISOL is clear, STATE clear confirms Network State. Note
any state transition into Isolate State causes an interrupt event to occur (ITM).
An internal flag. TSENT is set when the WD2840 passes the token. It may have
been either a piggyback or explicit token pass frame. TSENT is cleared when the
next frame is received.
SR23
RETRY
SR24
ACKRQ
SR25
TR
An internal flag set when the WD2840 receives a token passed to it. It is cleared
when the token is passed (or if it is ignored for any reason. For example, piggyback
token on a bad data frame, TXEN clear, or detection of duplicate tokens in the
logical ring).
SR26
NXTRO
Internal Receive Buffer Pointer State. Because of the linked list approach used in
the buffer chains, the WD2840 internal register used to follow the list is either
pOinting to the next buffer in the chain or at the address of the next buffer in the
chain (prior buffer's link field). The WD2840 will always advance along the chain so
that it has the address of the next buffer to be used. However, when a zero link is
encountered, the WD2840 retains the link field address expecting eventually that
the chain will be extended by the host making the link some non-zero value. When
the WD2840 actually needs the next buffer, it looks again at the contents of the link
field expecting it to have been changed (chain extended) to the address of an
available buffer. The NXTRO bit differentiates between these two situations. When
set it indicates the WD2840 has the address of the next buffer and that all prior
frames (denoted by posted FSB's) can be removed from the chain for received
frame processing by the host. When NXTRO is clear it indicates that the WD2840
has advanced to a zero link (end of chain).
NOTE: In this situation, the last posted frame CANNOT be removed from the chain
for processing since it is the link field of his last buffer that must be set in order to
extend the receiver buffer chain.
SR27
NXnO
Internal Transmit Buffer Pointer State. The comments for NXTRO (SR26) apply (in an
analogous manner) to NXnO since the transmit buffer chain is handled by the
WD2840 using an identical scheme. When NXnO is set it indicates that the
WD2840 has the address of the next frame to transmit in its internal register.
However when clear, it indicates that the transmit chain internal register points to
the link field of the last buffer of the last transmitted frame. This link field contained zero when first read. For the transmit case, this is a normal situation
corresponding to no data frames to transmit.
An internal flag which is set when either a data frame or a token pass frame must
be retransmitted. Data frames are only retransmitted if they have an acknowledge
request and no response at all occurred. Token pass frames (except Scan) are
retransmitted if no network activity was detected. Both of these situations are
detected as a result of a TA timeout.
An internal flag set during data frame transmission if an acknowledgement is
requested for the specific frame. If this is the case, the WD2840 pauses to await
the ACK/NAK response frame; if the TA timer expires before the response, a single
retry will occur (see RETRY-SR23). ACKRQ is not cleared until the beginning of the
next data frame transmission.
NOTE: As in the receive case, when NXnO is set, all previously transmitted frames
(denoted by posted FSB's) can be removed from the chain for reuse. However,
when NXnO is clear it indicates that the transmit chain must be extended by the
host before removing the very last frame that has been transmitted (posted).
96
IRO -
INTERRUPT REGISTER DEFINITION
REGISTER
IR07
IRoa
IROS
IR04
IR03
IR02
IR01
IROO
IRO
ITUR
IROR
INS
INTRAN
IREC
ITOK
ITA
ITO/M
The setting of any bit in this register by the W02840 causes an interrupt request (INTR
is clear. The reading of this register by the host clears all bits (and any interrupt request).
= low)
if NOINT (CR01)
BIT
NAME
DESCRIPTION (1)
IROO
ITO/M
Network dead or mode change (dual use). When in Network mode, timer TO expiring (with TOFF clear) causes this bit to be set to indicate no network activity has
occurred within the timeout period. Also INRING (SR20) is cleared and, if INIT
(CR15) is set, the WD2840 will enter Scan Mode (see INIT - CR15 for details).
Transition from Network or Oignostic State to the Isolate State will be confirmed by
this interrupt. The choice between the ITO and ITM interpretations is easily made
based on the ISOL (CROO) bit.
IR01
ITA
Date Frame Transmission Unsuccessful. This interrupt indicates that a transmitted
data frame with an acknowledge request was not successfully acknowledged.
Either a NAK or no response after two transmissions will cause this. The exact
cause can be determined by inspecting the appropriate FSB.
IR02
IR03
ITOK
IREC
IR04
INTRAN
Indicates that at least one data frame has been transmitted. The number of frames
transmitted and the status of each (Le. ACKINAK, retry count) is determined by
following the transmit chain and inspecting frame status bytes (FSB). All transmitted frames up to but NOT including the last posted may be freely removed. The
last one posted may only be removed if the W02840 NXnO (SR27) is set. For more
details see the explanation for NXnO.
IR05
INS
New successor. The W02840 has identified a new successor in the logical ring.
This happens when the prior suocessor either failed to respond to a token pass or
as instigated by a network scan frame.
!R06
IROR
Receiver over-run. The W02840 ran out of buffers or access to the OMA channel
was delayed by the host so long as to cause loss of received data.
IR07
ITUR
Transmitter under-run. The W02840 was delayed access to the OMA channel by the
host long enough to cause loss of transmitted data (an abort was sent). The frame
is not retried and the token is passed.
The token has been received.
Data Frame Received. This interrupt signifies that a good data frame has been
properly received and DMA'ed into the buffer chain. Frames that have been
received can be identified by following the buffer chain noting the W02840 frame
status bytes (FSB). A non-zero FSB (host must clear when queuing free buffers)
indicates a properly received frame. The host may freely remove all received
frames from the chain up to but NOT necessarily including the last one posted.
The last one posted may only be removed if the W02840 NXTRO (SR26) is set. For
more details see the explanation for NXTRO.
(1) = Non diagnostic mode only. See diagnostic section for register usage for diagnostics.
97
:ec
I\)
~
OTHER REGISTER DEFINITIONS
NAME
DESCRIPTION
CTRO
Running Limit Counter: Used by the WD2840 for Access Hold-Off Limit (AHOll) checking and
Transmit Limit (TXll) checking. When transmitting data frames CTRO is used for TXlT
counting; otherwise it is used for AHOlT counting. The counter runs from zero to the 8-bit
limit value.
Next Address. This register shows the current (instantaneous) successor node in the network
logical ring. For validity, the WD2840 should be "in the ring" (see GIRING - CR13 and INRINGSR20 for more detailS). The successor node may be changed for a variety of reasons:
NA
1. Any attempted token pass that fails twice will cause the WD2840 to attempt to locate a
new successor by sequentially trying token passes to successively higher node addresses beginning with NA+ 1.
2. A received Scan frame will cause NA to be set to MA + 1. If the next token pass fails
case 1 applies.
3. The host may arbitrarily redefine NA by using the NAR register and the NEWNA (CR10)
control bit. At a convenient pOint the WD2840 recognizes NEWNA, copies NAR into NA,
then clears NEWNA as confirmation. If the next token pass fails case 1 applies.
TA
Acknowledgement Timer. Value of maximum allowed time between frame transmission and
ACKINAK (if requested), or between token sent and network activity. The delay is in increments of 64 times the period of the clock ClK. Thus, if ClK = 2 MHz, then TA may be set
in increments of 32 microseconds (range of 32/As to 8.2 ms).
TD
Network Dead Timer: Value of maximumtime interval between received valid frames on the
network. Same clock source and range as TA. TD must be >TA.
CBP(H,l)
Control Block Pointer. A sixteen bit pointer to the WD2840 control block in the user's memory.
Must not be modified while the WD2840 is in network mode.
NAR
Next Address, Request. Used in conjunction with the NEWNA (CR10) control bit to cause the
WD2840 to update the NA register. This redefines the node's successor in the network logical
ring. It MUST be an address in the range 1-254. The acceptance of this update is confirmed
when the NEWNA control bit is cleared. On the next token pass, if the redefined successor
fails to accept the token, this WD2840 enters Scan mode where it sequentially attempts a
token pass to successively higher nodes.
AHOlT
This register is set at a value indicating the number of access cycles (tokens received) that
must be skipped before a data frame may be transmitted. (A token pass frame will be sent
even if a data frame may not be sent at a given access cycle.) Initialized to zero at power up.
TXlT
This register is set at the maximum number of consecutive data frames the WD2840 may
transmit during one access cycle. A value of zero allows the WD2840 to transmit all frames
queued up to 256. Initialized to zero at power up.
MA
My Address. The WD2840 receives only frames with this destination address (along with the
broadcast address) and inserts this address into the SA field of any transmitted frame. Must
be set by the host (range is 1 to 254).
98
1.4 DIAGNOSTIC AIDS
There are three levels of diagnostics supported by
the WD2840; those that are associated with the
network as a whole, those associated with the inDIAGNOSTIC
MODE CONTROL
CROO CR17 SR21
ISOL DIAGC STATE
1
0
0
0
1
0
0
0
1
1
1
0
1
1
1
0
0
0
0
1
0
1
1
1
dividual node, and those that are limited to the
WD2840 as a device. These tests are Network
Diagnostics, System Diagnostics and Self Diagnostics respectively. The Network Diagnostics can be
performed while the WD2840 is in the logical ring, but
the System Diagnostics and the Self Diagnostics
may be used only while the WD2840 is in the
diagnostic mode.
Diagnostic mode may be entered after power-up or
from the network mode by manipulation of the mode
control bits. The mode transition is confirmed by the
WD2840 via the STATE status bit.
Once in diagnostic mode, the desired test is selected
via CR1. Because most of registers 8 through Fare
interpreted differently for each test, only one of the
diagnostic test bits should be set at a time. In
conjunction with setting the diagnostic bits, the
NUDIAG (CR10) bit must be set to perform the
diagnostic test requested.
At the completion of the selected test NUDIAG is
cleared by the WD2840. Therefore the host can initiate a diagnostic by entering the diagnostic mode, initializing the proper registers, setting the desired
diagnostic bit, and setting NUDIAG. The host then
moniters CR1 for NUDIAG going to zero, indicating
the completion of the requested diagnostic.
DEFINITION
WD2840 "Isolated." Powerup condition or isolate
request.
WD2840 active.
Isolate request function
confirmed.
Host request to enter
diagnostic mode.
Diagnostic mode confirmed. Diagnostic functions of CR1 apply.
Illegal.
Illegal.
Illegal.
DIAGNOSTIC STATE FLOW CHART
ISOL = 17
(CROO)
~N~O~_ TO NETWORK STATE
INTRPIN43
GOES LOW
YES
YES
~_ _~
o-_ _ _ _ _ _ _ _ _...:...YE::.::S=_<
DIAGC=17
(CR17)
NUDIAG = 17'>N'-'-O=----_ _ _ _ _ _~
(CR1O)
NO
Poll CR1 for 0 in
NUDIAG for test
complete, process
results, then clear
DIAGC in CR1 to exit or
set NUDIAG and NEXT
TEST to continue
diagnostics.
99
POWER UP
Figure 1.3
FUNCTIONAL STATES
match. The same is true for registers D and 6 and
memory location N + 1.
Loop-Back Test
The host can test the WD2840 parallel to serial, serial
to parallel converters, CRC, and framing logic by
setting LOOPT (CR12) bit of the WD2840, while in the
diagnostic mode. The host has t~e responsibility of
initializing a transmit buffer with a known pattern and
then verifying its correct reception. The pattern is
looped internally to the device if ILOOP (CR03) = 1,
or may be looped externally (with outside logic) if
ILOOP = O.
The following procedure should be followed in order
to run the loop-back test:
1.4.1 SELF DIAGNOSTICS
Internal Ram and Interrupt Test
There are nine eight bit registers in the WD2840
which are not directly accessable by the users CPU.
This test provides a means to check those registers
and the interrupt register. The contents of register A
are placed into the interrupt register and five even
internal registers, and the contents of register B in
four odd internal registers. The nine registers are
then added together without carry and the result is
placed in registers 2, 5, 6, 7.
Use the following procedure to initiate the RAM test:
1. Enter diagnostic mode.
1. Enter diagnostic mode.
2. Set up register A and B to point to a buffer that is
initialized with a pattern for transmission.
2. Set up registers A and B
3. Set RAMT.
4. Set NUDIAG (can be set with RAMT bit together).
3. Set up register C and D to point to a buffer to
receive the frame. (It is a good practice to initialize
this buffer with all '00' or all 'FF' value bytes.)
4. Set up the buffer size in bits 3-0 of register E.
(NOTE: In this test the last two bytes of the buffer
will not be transmitted.)
5. Wait for NUDIAG to be cleared.
6. Read registers 2, 5, 6, 7. Clear RAMT.
Note that the setting of any bit in the interrupt
register while NOINT is clear will generate a hardware interrupt (INTR , pin 43 goes true).
5. Set ILOOP bit (CR03). (This is optional, if internal
loop-back test is desired.)
6. Set LOOPT bit (CR12).
7. Set NUDIAG (CR10).
8. Wait for NUDIAG (CR10) to be cleared.
9. Compare the two buffers to verify correct
reception of the frame.
NOTE:
If this test frame is allowed onto the network, transmission collisions may occur. Further, the first three
bytes of the transmit buffers will be interpreted as
TC, DA and SA, respectively, by the other stations.
Therefore in case this test is initiated while this node
is in the logical ring, care should be taken for
choosing these three values for external loop-back
test.
1.4.2 SYSTEM DIAGNOSTICS
DMATest
This test verifies proper operation of the DMA subsystem by reading the value from a register and
writing it into the user memory. The test continues by
reading the value from the same location in memory
and writing it into another register.
The value is read from register C. Using the transmitter DMA sub-system, it is written into memory location addressed by register A and B (location N;
register A is the MSB). The receiver DMA sub-system
is used and contents of the same address is read and
it is stored into the register 7. Next the receiver dma
is used and the contents from register D is written
into location N + 1. The transmitter dma reads the
value from location N + 1 and stores it into register 6.
For proper operation of the internal loop-back test the
CTS and sa pins of the WD2840 should be either tied
to ground or tied to RTS pin of the WD2840.
It is the host's responsibility to check if the contents
of registers C and register 7 and memory location N
100
several circumstances. The NAK prevents the
transmitting node from wasting bandwidth retrying
indiscriminately, and further, lends visibility to individual network node problems. The NAK includes a
reason code which is available to the transmitter's
software (via the TFSB).
Each data frame to be transmitted can be specifically
marked (via the FCB) by the host to require an
ACKINAK response from the receiving WD2840. In
the absence of errors, an acknowledge (ACK) frame
will be returned to the transmitter as confirmation.
However, several circumstances cause a Negative
Acknowledge (NAK) to be returned:
1. Insufficient buffer space
2. Receiver not enabled (RXEN - CR05 cleared)
3. Receiver overrun
4. Frame exceeded 16 buffers in length
This information is placed in the transmitted
frames's FSB. See section 2.1.2 for more details on
the Transmit Frame Status Byte (TFSB).
1.4.3 NETWORK DIAGNOSTICS
Duplicate Station Detection
Dupl icate stations (more than one station with the
same address) can result from the faulty programming of internal register MA (due to wrong address
switch settings on the user's device, for example).
This is expected to occur often enough to warrant the
addition of a detection algorithm in the users
WD2840 initialization procedure.
After initializing all required parameters, the user
places the WD2840 in network mode (by setting ISOL
false). The WD2840 monitors all frames on the network, and, if one is observed as having been transmitted by its address (source address of the frame
equals the value in register MA) an event counter is
incremented.
The user should monitor the SA = MA event counter
at least long enough for the token to have circulated
all the way around the access ring (time is configuration dependent) before enabling the WD2840's
transmitter:
It is useful to note that this constraint requiring each
node which is participating in the network logical
ring to have a unique address does not extend to
nodes which are "listening" but not "in the ring." It
might be useful to a network designer to have groups
of receive only nodes which have the same node
address but do not participate in the network token
passing (see GIRING - CR13). Data frames transmitted to such clusters must not request acknowledgement since all nodes in the cluster would
simultaneously respond.
2.0 INTERFACES
There are two interfaces to the WD2840: the host
computer side, and the network side. The network
side is conventional from an electrical point of view,
the WD2840 performs all logical functions required to
ensure communications capability on broadcast
media (such as coax or RF).
The host interface involves two separate functional
interfaces: the status/control registers described in
section one, and a DMA interface that is described in
the following subsection.
Copy Mode
The COPY Mode is selected by setting the COPY
control bit (CR02). Normally the WD2840 receives
(DMA's into the receive buffer chain) data frames only
if they contain the general broadcast destination
address or if they are specifically addressed to the
WD2840. This occurs when the frame's destination
address (DA) matches the WD2840 my address (MA,
set by the host).
However, when COPY mode is selected data frames
which are specifically addressed to other nodes will
be treated as broadcast frames by this node. The
COPY mode allows a specific node to "evesdrop" on
data frame traffic on the network.
2.1 HOST
The WD2840 uses a complex memory buffer architecture allowing it to respond in real time to its network
obligations (e.g., to meet network data rate and processing delay requirements). These memory structures are managed cooperatively by the host and the
WD2840.
Memory management functions requiring real time
response (e.g., traversing chains) are completely
handled by the WD2840. Other important, but not
time critical operations are the responsibility of the
host software (such as removing used buffers from
the transmit chain).
All memory references by the WD2840 are pointed to
by memory locations (and internal registers) initially
defined and set up by the host software. Initial values
and memory based registers are grouped together
and called the WD2840 Control Block.
Nak Response
The WD2840 sends negative acknowledgements
(NAK's) on response to received frames under
101
it is expected that the host will maintain both a FIRST
and a LAST address for each chain. On transition into
Network State, the chain origin information in the
WD2840 control block is the same as FIRST. In fact,
since the WD2840 does not change these control
block entries, they can be maintained directly as
FIRST by the host. An explicit LAST could be placed
in an extended control block section.
The location of this control block is written into the
registers CBPH and CBPl anytime the WD2840 i~ in
Isolate State. This control block has the followmg
structure:
CBP- +0
NXTR(H)
+1
NXTR (l)
+2
NXTT (H)
+3
NXTT (l)
+4
BSIZE
+5
+6
EVTO
EVT1
+F
EVT10
Receive Buffer Chain
(MSByte)
Receive Buffer Chain
(lSByte)
Transmit Buffer Chain
(MSByte)
Transmit Buffer Chain
(lSByte)
Buffer Size /16 (O-F = 641024 bytes)
The WD2840 "follows" the linked buffer chains by
maintaining a NEXT address internally for each
chain. This NEXT address can be in one of two
states: 1) it can be the address of the next buffer in
the chain, or 2) at the chain end (zero link), it can be
the address of the buffer containing the zero link. The
WD2840 uses a status bit for each chain, NXTRO
(receive) and NXTTO (transmit), to differentiate t~e
two states. When set they indicate the WD2840 cham
NEXT address is in state 1 above; when clear they
indicate state 2 above. This is an important distinction since it indicates whether the last buffer posted
in a chain can be removed by the host (because the
WD2840 has advanced to the buffer beyond) or must
be left until the chain can be extended so the
WD2840 can advance.
Eleven separate Event
Counters, see section
2.1.1 for details
As the WD2840 transitions to Network State, it reads
and uses the first five bytes of the control block. The
remaining eleven bytes of event counters are accessed by the WD2840 only when each specific event
condition occurs.
The host software monitors the progress of the NEXT
pointer: and updates FIRST and LAST as it adds (and
remov~s) buffers to (from) the chains as required. The
WD2840 provides Interrupt Events (see IRO) and
NXTRO, NXTTO status bits to indicate when it advances along the two chains and exactly what state
its NEXT address registers are in. The operation of
these chains will be explained by example in later
sections.
Either the Receive (NXTR) or Transmit (NXTT) chain
entries in the control block may initially be zero; in
such a case the WD2840 expects the chain to be
extended by the host's changing the zero link field in
the control block. Thereafter any such zero link would
be in a buffer.
The WD2840 uses constant size buffers; their length
is set by the value in location BSIZE. The buffer size
is indicated by a 4-bit count in the least significant 4
bits of the BSIZE byte in the WD2840 control block.
The buffer sizes available are multiples of 64;
(BSIZE + 1) 64 is the buffer size used by the WD2840.
Thus a BSIZE range of 0-15 corresponds to actual
buffer sizes of 64 through 1024 bytes. This buffer
length is inclusive of control bytes and buffer link
pointers.
"Deadly Embrace" Prevention
A "Deadly Embrace" can occur when two processors
reach a state where each is waiting for the other: In
this case, the two processors are the user's CPU and
the micro-controller inside the WD2840. Therefore, to
prevent the "deadly embrace," the following rule is
obeyed by the WD2840 and should also be obeyed by
the user's CPU. This rule applies to the WD2840
memory registers and to the I/O registers. The Event
Counters are an exception to this rule.
The WD2840 includes a chained-block feature which
allows the user more efficient use of memory, particularly in situations where the maximum packet
size is much larger than the average packet size. One
or up to 16 buffers may make up a frame but a buffer
may not contain more than one frame.
Rule:
If a bit is set by the CPU, it will not be set by the
WD2840 and vice versa. If a bit is cleared by the
WD2840: it will not be cleared by the CPU, and vice
versa.
As an example, the NEWNA (CR10) control bit is only
set by the host and is only cleared by the WD2840.
Byte counters are associated with each frame (at the
memory interface, not actually transmitted within the
frame) so that frames on the network need not be
integer multiples of buffers. The byte counters include all buffer management overhead. Therefore, a
frame consisting of 100 transmitted data bytes,
occupying two 64-byte buffers, would have a byte
count of 108 (six bytes per frame + 2 bytes per buffer
boundry).
DualDMA
The WD2840 may, for effiCiency, interleave frame data
fetch/store operations with fetches and stores. of
pointers and flags in memory. In all cases, operation
sequencing is such as to prevent deadlocks and
ambiguities between the WD2840 and software.
Since the WD2840 receive and transl11it buffer chains
are linked lists (see section 2.1.2 and 2.1.3) and are
"followed" by the WD2840 but managed by the host;
102
2.1.1 EVENT COUNTERS
Several non-fatal logical events are tabulated by the
WD2840 and made visible to the host via memory
based event counters (see WD2840 control block
organization for specific locations). The WD2840 will
increment each counter at the occurance of the
specified event. Note that the WD2840 will not increment past 255. The host has the responsibility of
initializing each counter:
COUNTER
DESCRIPTION
EVTO
"Set scan mode" frame received from the network. The NA register was redefined to
MA + 1 at the time.
Transmission error first attempt, second try successful. Can only occur for frames
requiring an acknowledgement. It indicates no response was received for the first
transmission; however, the second transmission was either ACK'ed or NAK'ed.
Transmission error: Attempt aborted due to either transmitter underrun or frame
length exceeding 16 buffers.
TimerTD (network dead) expired.
Access Control Frame Reception Error: A one or two byte supervisory frame
(ACKINAK, Token Pass, Scan Mode) has been received in error: This may be due to an
FCS error, frame abort, or carrier loss detection.
Data Frame Reception Error: An incoming data frame was incorrectly received due to
an FCS error, frame abort, carrier loss detection, or receiving a data frame when expecting an ACKINAK frame.
EVT1
EVT2
EVT3
EVT4
EVT5
EVT6
NAK sent. Can occur for any of the following reasons:
1. Insufficient buffers in chain
2. Receiver not enabled (RXEN clear)
3. Receiver overrun
4. Frame length exceeded 16 buffers
EVT?
Invalid frame received. Caused by the detection of certain abnormal network conditions such as receiving an ACKINAK frame when not expecting one, receiving a
Scan mode frame when expecting an ACKINAK frame, or receiving an invalid
supervisory frame.
Duplicate token detected. This counter will be incremented when the WD2840
determines that more than one token exists in the logical ring. This happens if a
token pass is received when the WD2840 already has the token, or a data frame is
received when the WD2840 is waiting for an acknowledgement frame.
EVT8
EVT9
EVT10
Not used.
Duplicate node address. This counter will be incremented when a data frame being
DMA'd into memory has a source address (SA) equal to the WD2840 node address
(MA). This counter when used with COPY mode (CR02) is one way for detecting other
nodes with the same node number (MA).
2.1.2 TRANSMIT MEMORY INTERFACE
When the token is received, data transmission is
enabled (TXEN - CR06 and TXDEN - CRO? both set),
and if the access hold-off counter has reached its
limit, the WD2840 will determine whether any data
frames are pending in the transmit chain. If so, it will
transmit the first data frame in the chain. Otherwise
the token will be passed. A given data frame will be
the last frame transmitted for this token if any of
several conditions occur:
1. ISOL (CROO) is set indicating the host has
requested a transition to Isolate State.
4. The running frame counter has reached its limit
(TXLT).
5. No further frames are pending in the transmit
chain.
If any of the first four reasons above are true a token
pass will occur: If the last frame does not require an
acknowledgement, the WD2840 will piggyback the
token pass if that is permitted (CR16). If the token
cannot be piggybacked or if the last frame transmitted is the last frame pending (condition #5 above),
an explicit token pass will occur: A piggyback token
will not occur for the last pending frame because, for
the general multiple buffer case, it is not known to be
the last pending frame until after the transmission is
complete.
2. TXDEN (CRO?) is clear indicating the host has
changed data frame transmission rights.
3. The frame FSB indicates this frame should be the
last transmitted for this token.
103
The WD2840 will read and evaluate the address of the
next frame at two specific points in time:
1. At the end of the prior frame, even if the prior
frame is the last to be transmitted for this token.
2. When the token is received .and data frame
transmission is permitted.
If a non-zero frame address is found at time 1 above,
it is kept and used without being re-read at time 2
above. However, if no pending frame is found at time
1, this is noted with the NXTTO flag clear and the
chain re-inspected on each occurrence of time 2
above.
As frame transmission commences, the WD2840
reads the address of the next buffer, the frame
control byte, (FCB) and the frame length. It then
starts reading bytes from the buffer and sending
them until the frame length count or the end of the
buffer is reached. The new buffer is read and data
transmitted as before. (See Figure 2.1)
When the frame length is finally reached, the
WD2840 pauses if an acknowledgement has been
requested. The frame status byte (FSB) is updated
when the frame is completed; its posting indicates
frame completion and gives information about the
success or failure of the frame transmission. At
frame completion, the WD2840 attempts to advance
along the transmission chain to identify the next
frame regardless of whether it will be transmitted
with this token or later.
The host may add frames to the end of the transmit
chain at any time by changing the zero link in the last
buffer. Also buffers of all posted frames up to but
NOT including the last buffer of the most recently
posted, may be arbitrarily removed from the chain.
The last posted frame (more specifically, the last
buffer of the last frame) may only be removed and
reused if NXTTO is set. This indicates that the
WD2840 has advanced its NEXT address to the next
frame but that its transmission has not been completed (in fact, perhaps not even started).
NOTE:
The WD2840 checks only the most significant byte of
the link field for zero link detection. This has the
following implications:
The frame length provided in the LENGTH field must
include all overhead bytes (LINK, FSB, FCB,
LENGTH) in all buffers used for the frame. For
example LENGTH = 8 implies DA, SA but no data
bytes. If buffer size is 64 then LENGTH = 67 implies
DA, SA, and 57 data bytes (one data byte in an
overflow buffer. As a result of this convention, certain
LENGTH values are not valid (e.g., 65, 66 in the
second example).
1. When writing into a zero link field, the host must
write the LSB of the new link field first, followed by
the corresponding MSB.
2. All buffers must have a starting address greater
than or equal to Hex '0100'.
TRANSMIT FRAME STATUS BYTE (WRITTEN BY WD2840)
o
2
VAL2
VAL1
VALO
BIT
NAME
DESCRIPTION
7
DONE
WIRING
Set to guarantee a non-zero value for the posted FSB.
Value of the corresponding bit in received ACK frame.
Reserved.
When set, indicates the ACKINAK code appears in the value field (bit 2-0) of this
FSB is assigned by the WD2840 transmitter routine. When clear, indicates value
resulted from ACKINAK code from receiving station.
An encoded field whose interpretation depends upon the SELF flag (bit 3) in this
FSB.
a. SELF clear
o 0 0 - No receive error ( = ACK when DON E is set).
001 - Insufficent buffers for frame.
o 1 0 - Receiver not enabled at frame start.
o 1 1 - Receiver over-run.
1 0 0 - Frame exceeded 16 receive buffers.
b. SELF set
000 - No transmit error.
001 - Transmitter under-run.
o 1 0 - End of chain reached.
o 1 1 - Frame exceeded 16 transmit buffers.
1 0 0 - Transmission failed. Two attempts occurred.
6
5-4
3
2-0
SELF
VAL
104
Transmit Frame Status and Control Bytes
Each frame has two bytes reserved, one for host
control information needed by the WD2840, the other
for status information posted by the WD2840 at frame
transmission completion. The frame control byte
(FCB) is only read by the WD2840, never changed; the
frame status byte (FSB), is written (posted) by the
WD2840 with no regard for its prior contents. On
completion, the FSB value will always be non-zero; it
is important that the host zero the FSB byte in order
to be able to recognize a posted frame.
NOTE:
Specifically note in Figure 2.1 that the first buffer of
each frame has a different structure than any overflow buffers for that frame. In particular, each frame
has only one set of FSB, FCB, and LENGTH fields
regardless of the number of buffers required by the
frame.
TRANSMIT FRAME CONTROL BYTE (WRITIEN BY HOST)
o
x
2
x
I
x
BIT
NAME
DESCRIPTION
7
WACK
Wait for Acknowledgement. Instructs the WD2840 to wait for an ACKINAK
response from the receiver for this particular frame only. The token control (TC)
byte in the frame is automatically set to cause the destination node to respond.
This bit must NOT be set if the frame uses the broadcast destination address.
Inadvertently doing so will cause the frame to be posted "Transmission failed, due
to max retries."
6
FCBLF
Last Frame. This bit will cause the WD2840 to pass the token either piggybacked
with this frame (if possible) or explicitly after the frame transmission completes.
5
TRANSP
Transparent Frame. This bit will cause the WD2840 to interpret the buffer contents
to be the exact sequence of bytes to be transmitted. The normal token control (TC)
byte and source address (SA) byte generation is suppressed. Note that for a nontransparent data frame the TC byte must NOT appear in the buffer.
4-0
-
Reserved.
-NXTT(L)
- - -NXTT(H)
INTERNAL REGISTERS
LINK (H)
-----L1NK(L)
.-
LINK (H)
LINK (H)
----- --..-------!II!i" --- --L1NK(L)
0
----.---.~ ~-----
L1NK(L)
FSB
XX
FSB
--- ----
-------
FCB
FCB
LENGTH (H)
LENGTH (H)
LENGTH (L)
LENGTH(L)
------
-------
DA
DA
SA
SA
D
A
D
A
T
T
A
A
TRANSMITTED BUFFERS, TO BE REFILLED
ANDR&QUEUEDBYTHEHOST
TO BE TRANSMITTED
Figure 2.1 TRANSMIT BUFFER CHAIN
105
END
OF
CHAIN
2.1.3 Receive Memory Interface
2. Current buffer capacity exhausted. If 16 buffers
have been used for the current frame, an event
occurs with the frame being dropped and the
chain reset. Otherwise the WD2840 attempts to
advance to the next buffer in the receiver buffer
chain. The frame data will be continued in this
subsequent buffer. If the end of the receiver
buffer chain is reached an event counter is
incremented, the frame is dropped, and the
chain reset.
After the third byte of an incoming data frame is
detected, the WD2840 will begin to place frame data
into memory if several conditions are satisfied:
1. Receiver Enabled (RXEN-CR05 set).
2. There is an available buffer in the receive buffer
chain.
3. The frame is addressed to this node specifically,
it is a broadcast frame, or COpy mode has been
selected by the host.
3. Frame ends. If the FCS is not corrected an
event counter is incremented, the frame is
dropped, and the chain is reset. If corrected
however, the frame length is placed in the
LENGTH field and the Frame Status Byte (FSB)
is posted "done, no error:'
As the frame continues, it may completely fill its
buffer. If this happens the WD2840 reads and inspects the link field of the current buffer. If this link is
zero, an error occurs and the receive chain is reset to
reuse from the first buffer used by the dropped frame.
However, if another buffer is available, the incoming
frame is continued beginning in the third byte of that
buffer. This continues until one of several things
happen:
If the frame is addressed to this node and indicates
an acknowledgement is required (TC = 255), whether
or not an error occurs, the WD2840 responds with an
ACK/NAK supervisory frame indicating either
success or failure. In case of receiver over-run, bad
FCS, and SA = MA acknowledgement request will be
ignored. (See section 1.4.3 for details)
1. Receiver overrun. The WD2840 has a four byte
FIFO to buffer incoming frame data; however, if
the host DMA responds too slowly a receiver
overrun will occur. If this happens an event
counter is incremented, the frame is dropped,
and the receiver buffer chain is reset to reuse
buffers of the dropped frame.
It is the host's responsibility to ensure that buffers
are available, initialized (FSB zero'ed), and attached
to the end of the receive buffer chain.
RECEIVE FRAME STATUS BYTE (WRITIEN BY WD2840)
81T#
7
6
5
4
3
2
Name
DONE
x
x
x
x
x
BIT
NAME
7
DONE
DESCRIPTION
Set to indicate the frame reception is complete.
-
6-0
x
o
x
Reserved.
RECEIVE FRAME CONTROL BYTE (WRITIEN BY HOST)
I
81T#
7
6
5
4
3
2
Name
X
X
X
X
X
X
BIT
I
7-0
NAME
DESCRIPTION
IReserved.
106
0
X
X
_.
NXTR(H)
-- --
NXTR(L)
INTERNAL REGISTERS
LlNK(H)
-- ---LlNK(L)
..
LlNK(H)
------
---..... ----.,..
LlNK(L)
LlNK(H)
------
----.-- ..
0
~ ~----
LlNK(L)
XX
FSB
r---- ---FCB
LENGTH(H)
r------LENGTH(L)
DA
SA
D
A
T
A
AVAILABLE FOR WD2840 USE
FILLED BUFFERS, TO BE EVALUATED BY THE HOST
Figure 2.2
RECEIVE BUFFER CHAIN
2.2 MODEM INTERFACE
The modem interface is the conventional half duplex
NRZ type with separate data and clock (Figure ~
When the WD2840 desires to transmit, it asserts RTS
and awaits CTS. RTS is generally used to enable the
modem transmitter. After a system dependent
preamble is generated, the modem asserts CTS
which allows the WD2840 to ~n the actual trans·
mission of the frame. (Note: CTS may be asserted
permanently if the transmission system does not
need to generate a preamble).
The sa input is used on receive to indicate a valid
carrier. If this term is negated anytime during a
receive message, the' WD2840 will presume the
message is in error and treat it as an abort. This
signal is used to augment message integrity beyond
that of the CRC by allowing a modem to detect and
report low level faults (such as out·of·frequency
carrier or missing clock).
107
-
END
OF
CHAIN
I
I
I
fC
RC
I
TO
DATAl
CLOCK
ENCODER
TRANSMISSION
J
""""
L--~""
,
.-.
) )
MEDIUM
DATAl
CLOCK
ENCODER
RD
sa
RTS
CTS
OPTIONAL
PREAMBLE
DELAY
TRANSMIT
Figure 2.3
RECEIVE
CONCEPTUAL MODEM
3.0 NETWORK PROTOCOL
To enable operation on a broadcast medium without
the need for a central controller performing device
polling, the WD2840 implements a media access
protocol. The particular access protocol designed
into the WD2840 prevents self-induced transmission
collisions and ensures a fair and guaranteed
distribution of transmission time among attached
controllers.
This design-out of collisions allows the WD2840 a
greatly expanded selection of transmission media,
since no physical characteristics of a particular
medium are relied upon for proper network operation.
Another benefit of this lack of collisions is the
visibility of network faults. If a collision is detected, it
is treated consistently in a error recovery mode by
the WD2840 and is also unambiguously visible to
service personnel as a fault.
Secondly, the WD2840 can ensure that a transmitted
message was correctly received and buffered by
requiring acknowledgement of its receipt. This is
sometimes called "acknowledging datagrams"
where the sender awaits a predefined period after a
frame is sent for a reply from its destination. With
this method, no sequence counters nor multi-frame
retransmission buffering is required. The scheme is
efficient since local network applications such as the
WD2840 address do not encounter extremely long
transmission delays (such as satellite links) as in
conventional data networks (such as X.25).
Both functions are parameterized, allowing tuning
and optimization by the user to his unique application. These parameters may be adjusted in real
time by the user's software, allowing a dynamic
network, responsive to constantly changing
requirements.
The two functions; access control and data transmission, function Simultaneously though independently.
Thus they are described separately as subprotocols
for clarity.
3.1 Data Transmission
The data transmission cycle is entered after the
token has been received and data transmission rights
validated (see section 3.2 "access method"). The
WD2840 determines if there is a frame to be sent and,
if not, simply sends the token to the next station.
If something is queued for transmit, the WD2840
DMA's it from memory and sends it. After the
complete frame has been sent, the WACK (Wait for
ACK) bit is tested in the TFSB (Transmit Frame Status
Byte). If set, the WD2840 waits for, and expects, an
acknowledgement from the frames recipient. A timer
(TA) is started. In the normal case, the ACK is
received before TA expires which causes the WD2840
to send the next frame queued, repeating this
procedure. Thus, the WD2840 sends multiple frames
to various destinations until the transmit queue is
emptied or a programmed limit (register TXLT) is
exceeded.
108
which does respond. rhe responding station
number is written into register NA so that this
scanning procedure need not be repeated on subsequent access cycles.
In the event TA expires, the frame is re-transmitted
once. (Note: it is the responsibility of higher level
protocol operating in the host to protect against the
possibility of duplicate frame reception.) If TA expires
again, usually indicating the destination node is offline, the FSB is updated to reflect the unsuccessful
transmission, interrupt bit ITA is set, and the frame is
skipped.
A frame is also skipped and tagged if the destination
station sends a NAK, indicating it cannot presently
process the frame.
NOTE: 1. Node numbers 0 and 255 are reserved and
cannot be used. Consequently scanning
occurs circularly in the range 1-254.
2. During Scan mode token passing each
node is only tried once.
Anytime a station cannot successfully pass a token
within two attempts, register NA is updated to
NA + 1, and a new" next" station is searched for. The
result is the removal of non-responding station(s)
from the access ring. An interrupt (INS) is generated
indicating a network exception caused a change to
NA.
TRANSMISSION OF ABORT
An ABORT is transmitted by the WD2840 to terminate a frame in such a manner that the receiving
station will ignore the frame. An ABORT is sent when
there is a Transmitter Under-Run. The abort sequence
is a zero, followed by seven ones, after which RTS is
set false.
The above description covers network recovery from
station failure and purposeful removal of stations
during on-line network operation. Setting stations in
the scan mode can also be accomplished by sending
control frames (a Scan frame redefines NA = MA + 1)
over the network. The control frame may be directed
to a single station, or all stations simultaneously
(using the broadcast address). It is this scanning for
new stations that permits on line addition to the
access ring.
3.2 ACCESS METHOD
The WD2840 network access method is based on the
use of tokens, the specific granting of transmission
rights passed from station to station. At any given
time, exactly one station has the right to transmit
(this right is called the token) and is obligated to pass
it on when finished with it.
This can be clarified by referring to Figure 3.1. We
assume in this figure that the network has already
been initialized (meaning that the linkages in the
access ring have already been established) and the
token is held at this instant by station 4 (the station
whose MA register = 4).
When station 4 is ready to pass his access right on,
he sends a message to the station number called out
in his internal register NA, in this case 11. The
message, and thus the token, are received by station
11 who can now transmit its message(s). When
station 11 is ready to pass the token, it sends a
message to station 19, as directed by its internal
register NA and the cycle continues, in a circular
fashion, from station 4 to 11 to 19 to 54 to 4 ...
Notice that the station numbers need not be contiguous. This relatively arbitrary station numbering (in
the example) poses no inefficiency to the access
method. The value of this is the ability to add and
remove stations (re-configure) to the network without
re-arranging everyone elses addresses. (See section
3.2.2 for an example.)
In this way, the token is passed from one station to
the next in a logical ring.
NOTE:
The policy of the SCAN frame is redefined by the
user software as required by the application. For
example: in a process control environment where
stations are not often added while the network is in
use, this procedure would be initiated rarely if at all.
3.2.2 REMOVING A STATION
There are two ways a station can be removed from
the access ring: non-response due to station failure
and non-response due to host commanded transition
to the Isolate State. Both are treated identically from
a network point of view.
Referring to Figure 3.1, assume that station 19 is
removed from the network (either physically or
logically). In this example, station 11 would detect a
network fault when trying to pass the token to 19
(time TA would expire since station 19 will not
respond). Station 11 detects this and finds the next
station in the access ring by using the "scan" function (similar to initialization). The next attempt at
passing the token would be to station 20, register
NA+1.
By starting the token ring recovery procedure at the
intended station plus one (station 20) rather than
MA + 1 (station 12) as is done in initialization,
recovery delays are minimized (since fewer stations
are tested for presence, 8 less in this example).
The next station found would be number 54 in the
example which station 11 writes into his register NA
(now "patching out" dead station 19). The next time
station 11 is finished with the token, it directly sends
it to 54, making the sequence now 11 to 54 to 4 to 11
to 54 ...
3.2.1 ACCESS INITIALIZATIONI ERROR RECOVERY
When the WD2840 is commanded into Network
State, the Next Address Request (NAR) register and
the NEWNA (CR10) flag must be used to define the
Next Address (NA) register. When it is necessary to
pass the token, it is passed to the current node
number in register NA. If station NA is not on-line,
determined by its lack of response, station NA + 1 is
tried. This process continues until a station is found
109
3.2.3 INTERACTION OF THE SUB·PROTOCOLS
After a station is given the token, it will send an in·
formation frame, a token frame, or a combination of
both. It is this combination frame, referred to as a
"piggy back" token, that causes the sub-protocols to
interact slightly.
In the case of a combination frame, the SENDer
resets his timer TA on transmission complete and
waits for the NA station to transmit something valid,
to verify his reception of the piggy back token. If the
timer expires, the sender sends an explicit token (the
data from the combination frame is assumed to have
been accepted) and enters the normal token subprotocol.
In the normal case (no time-out), the SOURCE may
transmit a combination frame to the DATASINK when
his access period is over. All stations on the network
observe this; after the reception of the current frame
is complete, the one whose MA register matches the
token address in the frame (TC) knows it has the
token.
The user is prevented from sending a combination
frame and requesting an acknowledgement at the
same time to prevent possible network state confusions under time-out conditions.
----,
I
1
1
I
MEDIUM
1
I
I
I
1_ _ -
MA = Node ("My") Address
NA
Next (Successor) Address
does not apply
_
Figure 3.1
=
•• =
TOKEN PASSING ON A LOGICAL RING
3.3 FRAME FORMAT
The frame format the WD2840 uses to transmit all
data and control frames is similar to the industry
standard HDLC. A 16 bit CRC is implemented and
standard zero insertion (CRC16-CCITT) is used for
framing. This framing method allows the use of
standard network monitoring and diagnostic
equipment such as data scopes and logic analyzers.
Access Control Format:
F-DA-AC-FCS-F
F
= Flag, binary pattern 01111110
DA = Destination Address (8 bit)
AC = Access Control Field (8 bit)
FCS = Frame Check Sequence (16 bit)
Additional address fields and control points are
defined as required to support the protocol.
Token Pass Format:
F-TC-FCS-F
Normal Frame Format:
F
= Flag, binary pattern 01111110
TC = Token Control (8 bit)
FCS = Frame Check Sequence (16 bit)
F - TC- DA-SA-I- FCS- F
F
TC
DA
SA
I
= Flag, bi nary pattern 01111110
= Token Control (8 bit)
FCS
= Frame Check Sequence (16 bit)
= Destination Address (8 bit)
= Source Address (8 bit)
= Information Field (0 to 2048 bytes or 16
buffers, whichever is less).
110
FIELD DESCRIPTIONS AND ENCODING
TC
The token control byte has the dual purpose of transferring access control between
stations and conveying a request for immediate acknowledgement of the frame by its
intended receiver.
There is no interaction between the TC field and the DA or SA fields. Thus the token
may be transferred to one station and data sent to the same or a different station, with
one single frame. The value entered into the TC field is determined by the WD2840
and does not appear in the buffer (except for transparent frames). See WD2840 state
document for details.
TC Value
Meaning
a
1-254
Token not affected at this time.
After current frame, the token belongs to station TC.
(The sending station has recovery responsibility).
Immediate ACK requested. Token not affected.
255
NOTE:
The sharing of this field prevents the passing of the token with data (piggy-back) and
acknowledgement requests on the same frame. This combination is specifically
disallowed because of its undesirable characteristics in network error situations.
Destination address. Value of zero is reserved, 1 to 254 indicates the destination
address of the frame. The value 255 is the global (or broadcast) address.
Source address. The values of 0 and 255 are reserved. A value of 1 thru 254 is the
address of the sender of the frame.
Information Field. User defines format and content.
Frame Check Sequence. The FCS calculation includes all data between the opening
flag and the first bit of the FCS, except for a's inserted for transparency. The sixteen
bit FCS is compatible with the standard HDLC FCS.
Access Control. Conveys supervisory information. May be sent as a command using
transparent mode or received in response to an ACK/NAK request. Its format is
shown below:
DA
SA
I
FCS
AC
ACCESS CONTROL FIELD
BIT#
7
6
5
4
3
Name
SCANF
WIRING
a
a
a
2
1
0
NVAL2 - NVAL1 - NVALO
BIT
NAME
DESCRIPTION
7
SCANF
Scan Mode (Command). Indicates that the addressed node(s) must redefine NA =
MA + 1 for use on its next token pass.
6
WIRING
5-3
2-0
NVAL
Wants in ring (Response). This bit indicates the node that transmitted the frame is
not in the logical ring but would like to be. It is the logical function of the transmitting node's GIRING .AND. INRING. (see CR13 and SR20) The WD2840 does not
act on this information but merely passes it to the host via the ACK'ed frame's
FSB.
Reserved.
An encoded NAKI ACK value (Response). The receiving node will set one of the
following codes depending upon the state of the last received frame:
-
oa
oa
o1
o1
01011 a 0-
No error
Insufficient buffers for frame
Receiver not enabled at frame start
Receiver overru n
Frame exceeded 16 receive buffers
111
4.0 ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS:
NOTE:
Absolute maximum ratings indicate limits beyond
which permanent damage may occur. Continuous
operation at these limits is not intended and should
be limited to those conditions specified under DC
Electrical Characteristics.
Voltages referenced to VSS
High Supply Voltage (VDD) . . . . . . . . . .. - 0.3 to 15V
Voltage at any Pin .................. - .03 to 15V
Storage Temperature Range .... - 55°C to + 125°C
Electro-static voltage at any pin ...... 400V (Note 6)
OPERATING CHARACTERISTICS (DC):
Operating Temperature Range ...... O°C to
SYMBOL
IDD
ICC
VDD
VCC
VIH
Vil
VOH
VOL
10ZH
10Zl
IIH
III
PARAMETER
VDD Supply Current
VCC Supply Current
High Voltage Supply
los Voltage Supply
Input High Voltage
Input low Voltage
Output High Voltage
Output low Voltage
Three-State leakage
Three-State leakage
Input Current
Input Current
+ 70°C
MIN.
11.4
4.75
2.4
TYP.
MAX.
UNIT
18
160
12
5
30
220
12.6
5.25
0.4
50
50
10
1.6
mA
mA
V
V
V
V
V
V
I1A
I1A
I1A
mA
MAX_
UNIT
CONDITIONS
2.05
Note 1
Note 4
Note 4
375
MHz
MHz
MHz
mS
nS
nS
80
nS
0.8
2.8
CONDITIONS
10
10
VIN
VIN
VIN
VIN
= -0.1mA
= 1.6mA
= VCC
= O.4V
= VCC
= 0.4V
5_0 TIMING CHARACTERISTICS (AC):
SYMBOL
PARAMETER
MIN_
ClK
RC
TC
MR
Clock Frequency
Receive Clock Range
Transmit Clock Range
Master Reset Pulse Width
Input Address Valid to RE
Read Strobe (or DACK
Read) to Data Valid
Data Hold Time From
Read to Strobe
Address Hold Time
From Read Strobe
Input Address Valid
to Trai ling Edge of WE
MinimumWE Pulse Width
Data Valid to Trailing
Edge of WE or Trai Ii ng
Edge of DACK for DMA
Write
0.5
0
0
10
0
TAR
TRD
THD
THA
TAW
TWW
TDW
TYP.
80
nS
200
nS
200
100
nS
nS
112
Note 5,2
Note 2, 3
TIMING CHARACTERISTICS (AC):
SYMBOL
PARAMETER
TYP.
MIN.
UNIT
MAX.
CONDITIONS
,-
TAHW
TDHW
TDA1
Address Hold Time
After WE
Data Hold Time After WE
or After DACK for DMA
Write
Time From DROO (or
DROI) to Output
Address Valid if
1
ADRV
Time From DACK to
Output Address Valid if
ADRV
Time From Leading Edge
of DACK to Trailing
EdgeofDROO
(orDROI)
Output Address Hold
Time From OACK
Data Hold Time From
DACK For OMA Read
80
nS
100
nS
80
nS
400
nS
Note5
400
nS
Note5
100
nS
100
nS
=
TDAO
=a
TDO
TOAH
TDMW
Note 2
NOTES:
1.
Clock must have 50% duty cycle.
2. There must not be a CPU read or write (CS-RE or CS-WE) within 500 nanoseconds after the trailing (rising)
3.
4.
5.
6.
edge of DACK.
There must not be the leading (falling) edge of DACK allowed within 500 nanoseconds after the completion
of a CPU write (CS-WE).
See "Ordering Information" for maximum serial rates.
C(load) = 100pf
Measured by discharging a 100pf capacitor to each pin through a 1K ohm resistor.
113
~
c
X
I\)
()C)
~
F
IAO. IA3
I
0
RE
"\,
~TAR·I
DALO·DAL7
-.1/
THA
~
DATA"
~TRo~~VA~:o/~
WE
• • A15
(ADRV = 0)
II
1
TDD
DACK
(
DATA VALID
-1
j.-TAHW
>r-
TDHW
CPU WRITE (CS IS LOW)
!.-
I~-
(AO·A15 SAME AS DMA OUT)
I
I.-
r-- TDAO
j- -- --- ---- ----- -- - - -.~-----',-·--I--------~-TDA~
~
I
DACK
·~r~~----
,
---.1 TDMW I-DALO·DAL7
I----------« DATA VALID />-----
"''--_ _--..J/
I~DH:!
I.. >
(
-TDW..
DALO·DAL7
l-TRD~I
~---------.(
~ATA VALI~
DMAIN
DMAOUT
6.0
I:-=TDW
<,,--------)>-____
, . _I
~TDA1~ ~
= 1)
"I
T_
I
y--------
AO·A1::-5---,~--- (ADRV
;;r
TAW
t
DALO·DAL7
CPU READ (CS IS LOW)
DRQO~
X
f..
IAO·IA3
ORDERING INFORMATION
ORDER NUMBER
WD2840T-01
WD2840T-05
WD2840T-11
MAXIMUM RATE
100 Kbps
500 Kbps
1.1 Mbps
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
114
Printed in U.S.A
WESTERN DIGITAL
c
o
p
R
o
R
A
T
/
o
N
WDK25001 PACKIT
FEATURES
• X.25 (WD2501
CONTROLLER
OR
WD2511)
NETWORK
• BAUD RATE GENERATOR
• RS-423INTERFACE
• 8 SOCKETS FOR OPTIONAL USER RAM, ROM,
EPROM
• WIRE-WRAP HOST INTERFACE AREA
• INTERNAL DATA RATE TO 64 KBPS
ORGANIZATION
• + 5°C TO + 50°C OPERATION
The WDK25001 "PACKIT", is composed of two major
physical areas. The printed circuit area contains
factory installed circuitry which handles the Packet
Network Interface device, programmable bit rate
generator, memory address decoder, and the EIA RS423 interface. The wire-wrap area is set up to allow
the user to design and implement their own host
interface and or level 3 and higher modules.
GENERAL DESCRIPTION
The Western Digital WDK25001 PACKIT is a preconfigured breadboard designed to be an instant
development tool for the implementation of bitoriented, full duplex, serial X.25 data communication
systems. Most of the hardware interfacing (Level 1/2
interfacing) is already done on the board. Level 213
interfacing is described in the long form specification. To perform Link Control (Level 2) functions, the
PACKIT utilizes the Western Digital LSI Packet
Network Interface Device. Two versions of the LSI
Packet Network Interface Device are available for use
with the PACKIT: the WD2501 and the WD2511. The
WD2501 LSI device handles the LAP (Link Access
Procedure). The WD2511 LSI device handles LAPB
(Link Access Procedure Balanced).
INTERFACES
The PACKIT interfacing (Level 1/2) is divided into two
classifications: the user interface and the serial
communications interface.
USER INTERFACE
Voltage Levels:
TTL
Architecture:
The PACKIT is composed of two major physical
areas. One side of the printed circuit board contains
the factory installed circuitry required to perform X.25
Link Level operations: the other side of the circuit
board contains the wire-wrapping area for user implementation of the individual system design.
Microprocessor interface oriented. 16 Address lines,
8 data lines, 10 control lines.
SERIAL COMMUNICATIONS
INTERFACE
Electrical Characteristics:
The wire-wrapping area of the circuit board is
designed to accommodate any industrial standard IC
package. IC width is defined in 0.15 inch increments,
with IC pin separation of 0.1 inch. The wire-wrap area
is large enough to permit the installation of approximately one hundred 16-pin IC's.
RS-423
Mode:
Synchronous, Bit stuffing oriented, full-duplex, X.25
Asynchronous Response Mode (WD2501) or X.25
Asynchronous Balanced Mode (WD2511).
Clock Rates:
Independent transmit and receive clocks. Either
internal or external clock source, selected by jumper
strapping. Internal clock rates selectable by DIP
switches or under user program control via the User
Interface.
115
~
c
BR1941
BAUD
RATEGEN
"c.n
I\)
WD2501/WD2511
X.25 PACKIT NETWORK
INTERFACE
RIBBON
CONN
RS·423
INTERFACE
8.....
RAM/ROM/EPROM
SOCKETS
PROTOTYPING AREA
J
PACKIT BLOCK DIAGRAM
ELECTRICAL SPECIFICATIONS
PHYSICAL DIMENSIONS
Voltage Requirements:
Size:
Single printed circuit board, 8 inches by 14 inches
(203.2 by 355.6mm)
+5v, +/- 5%
+ 12v, +/- 5%
-5v, +/- 5%
Weight:
Maximum Voltage Ripple:
2 Pounds (0.907Kg).
100mv, PTP
THE LSI PACKIT NETWORK INTERFACE DEVICE
Factory-Installed Circuitry Power Requirements:
The Packit Interface Device is a 48-pin, n-channel
silicon-gate, MaS chip designed to perform CCITT
X.25 Level 2 (link control), with selected enhancements. In addition to the link control functions
required by X.25, the Device eliminates the need for
separate DMA circuits, timing chips, and the system
software previously required to perform the link
control between a data terminal equipment (DTE) and
a data circuit-terminating equipment (DCE).
+ 5v @ .76A (max.)
(No memory device) + 12v @ .20A (max.)
- 5v @ .04A (max.)
MEMORY SPECIFICATIONS
Maximum Size Allowable:
64Kx8.
The WD2501IWD2511 interfaces directly with the onboard memory (when installed) or with the user's
memory data and address lines. The WD2501/
WD2511 is controlle.QJhrough nine user interface
lines: Master Reset (MR), REPLY, DMA Request Out
(DROO), DMA Request In (DROI), DMA Acknowledge
(DACK), Interr~t Request (INTR), Write Enable (WE),
Read Enable (RE), and Chip Select (CS).
Memory Type:
8-bit wide RAM, ROM, EPROM
Package Type:
24-pin or 28-pin
ENVIRONMENTAL SPECIFICATIONS
Additionally, the WD2501/WD2511 is driven by the 1
MHz system clock.
Operating Temperatures:
+ 5 to + 50 °C (Maximum temperature is reduced by
1.8 degree centigrade per 1000 meters altitude above
sea level.)
THE PROGRAMMABLE BIT RATE GENERATOR
Circuit board IC location U3 contains a Western
Digital BR1941 Programmable Bit Rate Clock. This nchannel MOS silicon-gate device is capable of
generating sixteen externally selected clock rates,
where-of six are standard rates.
Relative Humidity:
10 to 95%, maximum wet bulb of 32 degrees Centigrade and a minimum dew-point of 2 degrees
Centigrade (90 degrees and 36 degrees Farenheit,
respectively.)
The bit rate for both transmit and receive frequencies
may be selected independently through the on-board
116
DIP switch, S1, or through the user's program via the
TA, TB, TC, TO, RA, RB, RC, and RD user interface
control lines.
THE EIA RS-423 INTERFACE
The communications link between the Western
Digital PACKIT and the Data Communications
Equipment (DCE) is provided through the EIA RS-423
interface. This interface contains a subset of the
RS449 signals. The interface signals are supplied to a
40-pin ribbon cable connector. Each of the RS-449
signals are buffered by 26LS29-type RS-423 line
drivers and 26LS32 RS-423 line receivers.
If RS-232-C interfacing is desired, instead of RS-449
interfacing, the ribbon connector may be jumpered to
provide RS-232-C signal compatability. However, due
to differences in signal voltage levels, certain
precautions must be taken when converting to RS232-C interfacing.
To further increase PACKIT flexibility, the bit rate
generator is installed in an IC socket to enable easy
removal for specialized user bit rates not conforming
to those avai lable from the BR1941.
PACKIT MEMORY
Located on each PACKIT printed circuit board are
eight 28-pin IC sockets designed for optional userinstalled RAM, ROM, or EPROM memory chips.
These sockets present the user with the option of
either using the system memory or off-loading the
PACKIT memory functions to on-board memory of
the user's choice. Once the optional memory is installed it may be accessed by both the user's
computer and by the WD2501IWD2511 Network
Interface Device via DMA.
BIT RATE GENERATOR STRAPPING
The Western Digital BR1941 Bit Rate Generator, on
board the PACKIT, may be programmed for receive
and transmit bit rate, by on-board switch setting or by
program command from the user circuitry. The
selection between these two options is controlled by
the S1 switchpack. To use program control all
switches of S1 must be in the "OFF" position
otherwise the bit rate is the "wired-and" of the
program control and the setting of the switches.
Transmit and receive bit rates are independently
selected.
NOTE:
All memory devices installed on the PACKIT board
must be 8-bit wide devices. Total memory installed
must not exceed 64K-bytes.
The design of the memory sockets permits the user a
wide range of RAM, ROM, and EPROM selectability.
Memories such as the 4802 (2K x 8 RAM), 4118 (1 K x 8
RAM), and the 2716 (2K x 8 EPROM), allow the user to
select the type, capacity, and expense of memory
desired for each individual application.
Program control of the bit rate, when enabled, is
received by the PACKIT via the TA, TB, TC, and TO
jumper pads, for the transmit bit rate, and via the RA,·
RB, RC, and RD jumper pads, for the receive bit rate.
(Each of these control lines is tied to + 5v via a 2.2K
resistor pull-up.)
Also, the design of the sockets provides for the use
of either 28-pin or 24-pin memory circuits. If a 24-pin
circuit is to be installed, the chip is simply inserted in
a manner that places pin 1 of the memory chip in IC
socket position 3. Polarization of the sockets is indicated by a white dot, on the PC board, adjacent to
both Pin 1 and Pin 3 of the socket.
When calculating the size of on-board memory, for a
particular application, it is imperative that the user
remember that the on-board memory must be large
enough to contain five major arrays.
1.
2.
3.
4.
5.
PROGRAMMING AND
THE PACKIT USER INTERFACE
The Western Digital PACKIT user interface defines all
of the signals available to the user. These signals
include: the microprocessor oriented address, data,
and control lines, the RS-423 communications interface signals, the programmable bit rate generator
control lines and on-board strapping.
The data to be transmitted,
The data received,
The transmit-data look-up table (TLOOK),
The receive-data look-up table (RLOOK),
The PACKIT error counters.
USER INTERFACE SIGNALS
The user designed circuitry interfaces with the
PACKIT through the interface signal jumper pads
located at the center of the PACKIT PC board. The
signals are listed in the table on following page.
Signals are defined as "IN", "OUT", or "BI", to denote
input from or output to the user interface, or bidirectionality, respectively. RS-449 mnemonics are presented in parenthesis.
For a detailed description of the use of memory by
the Packit Network Interface Device, refer to the
WD2501IWD2511 Long Form Specification.
Industrial standard memory types like 4118 or 4801
(1 K x 8), 4802 or 2716 (2K x 8), and 37000 or 2764 (8K x
8) can be used in the PACKIT.
117
USER INTERFACE SIGNALS
SIGNAL NAME
DIR
SIGNAL DEFINITION
AO-A15
BI
The sixteen memory address lines. These lines may be connected to the user's
memory address bus or to the PACKIT on-board optional memory chips, when
installed. These lines also carry the memory address outputs of the Packit Network Interface Device for DMA operations.
DO-D7
BI
The eight bit data lines used to transmit and receive byte-oriented data between
the interface chip and the user circuitry. These lines also carry data between the
WD2501 IWD2511 and the optional on-board memory (when installed).
TMI (TM)
OUT
Test mode Indication. Signal returned from the RS-423 communications interface indicating that the local DCE is in the test mode. This signal is propagated to the user interface.
RDYREC(RR)
OUT
Ready to receive. Signal returned from the RS-423 communications interface
indicating that the communications link is ready to receive data. This signal is
propagated to the user interface.
IN
DMA Acknowledge. The CPU signal generated in response to the
WD2501IWD2511 transmitted DRaa or DRal DMA request signals. An active
low, sent to the PACKIT, on this line informs the PACKIT that the DMA request
is acknowledged and the CPU has relinquished control of the system bus.
OUT
DMA Request IN. The WD25Q1IWD2511 requests a DMA bus access. A DRal is
a request for a transmission of data FROM the memory TO the
WD2501IWD2511. This signal is active low.
OUT
DMA Request OUT. The WD2501IWD2511 initiated signal requesting access for
a DMA data transfer. The DRaa signal requests a DMA cycle to enable transfer
of data FROM the WD2501IWD2511 TO the memory. This signal is active low.
OUT
Master Reset. The master reset, generated by the on-board RESET momentary
closure switch, clears all of the WD2501IWD2511 control and status registers,
with the exception of two internal control bits (refer to the WD2501IWD2511
Long Form Data Sheet, sheet 2). This signal is active low.
OUT
Interrupt Request. The WD2501IWD2511 issues INTR to request an interrupt.
This signal is active low.
IN
Chip Select. CS is driven low, by the user's Circuitry to enable the
WD2501IWD2511 for programmed 1/0 read or write operations. CS may be
permanently activated by jumpering pad location S11 to ground.
DATA MODE
(DM)
OUT
The DATA MODE signal is returned from the communications link, over the RS423 interface, to inform the PACKIT that the data link is in the data mode.
REPLY
OUT
Reply. An active low signal, generated by the WD2501IWD2511 to indicate that it
is selected (CS is low) and it is either read enabled (RE is low) or it is write
enabled 0NE is low).
MWE
IN
An active low signal generated by the user's system to enable the PACKIT onboard memory chips for a memory-write operation. Not applicable on 24-pin
memories. All 24-pin memories are enabled through the J2-O through J2-7 interface signal lines. This signal is connected to pin 27 of all 28-pin memories.
J2-0to J2-7
IN
User activated signal lines to individually enable each of the PACKIT on-board
memory sockets. Each active low signal enables the Write Enable 0NE) input of
the respective memory socket where:
INTR
CS
J2-0 write-enables memory socket U13
J2-1 write-enables memory socket U14
J2-2 write-enables memory socket U15
J2-3 write-enables memory socket U16
J2-4 write-enables memory socket U17
J2-5 write-enables memory socket U18
J2-6 write-enables memory socket U19
J2-7 write-enables memory socket U20
Each signal is connected to Pin 23 of the corresponding memory socket.
118
CONTINUED
SIGNAL NAME
TA, TB, TC, TD
DIR
IN
USER INTERFACE SIGNALS
~
SIGNAL DEFINITION
These four inputs combined select the Transmit bit rate to be generated by the
Western Digital BR1941 Programmable Bit Rate Clock. The values presented to
the bit rate clock generator, over these lines, may be determined either by the
user program or by on-board switch setting, as determined by switch-pack S1.
REMOTE LOOP
TEST (RL)
IN
When activated, the REMOTE LOOP TEST line forces the communications link
into a diagnostic test. Data is transferred from the memory, to the communications link, to the remote DCE, and back to the PACKIT for verification.
TERM RDY (TR)
IN
Terminal Ready. Input line to the PACKIT, from the user circuitry, informing the
DCE that the PACKIT is ready to set-up the communications link.
This signal is optionally generated, on a permanent basis, by the PACKIT when
jumper S12 is connected to ground.
LOCAL LOOP
TEST (LL)
IN
The LOCAL LOOP TEST performs a diagnostic operation similar to that of the
REMOTE LOOP TEST with the exception that the data being tested is transmitted to the local DCE and then returned to the PACKIT for verification.
MOE
IN
Memory Output Enable. A user supplied low active signal used to enable the
3-state output of the optional on-board PACKIT memory, when installed. This
signal is connected to pin 22 (28-pin) and pin 20 (24-pin) of the memory devices.
119
C
"
I\)
(J'I
o
o......
120
WESTERN DIGITAL
o
c
R
P
o
R
A
T
/
o
N
TR1402/TR1602
Universal Asynchronous Receiver/Transmitter (UART)
~
FEATURES
• FULL DUPLEX OR HALF DUPLEX OPERATION
• AUTOMATIC INTERNAL SYNCHRONIZATION
OF DATA AND CLOCK
• AUTOMATIC START BIT GENERATION
• EXTERNALLY SELECTABLE
Word Length
Baud Rate
Even/Odd Parity (ReceiverlVerification Transmitter/Generation)
Parity Inhibit
One, One and One-Half, or Two Stop Bit
Generation (1112 at 5 Bit Level for TR1602)
• AUTOMATIC DATA RECEIVEDITRANSMITTED
STATUS GENERATION
Transmission Complete
Buffer Register Transfer Complete
Received Data Available
Parity Error
Framing Error
Overrun Error
• BUFFERED RECEIVER AND TRANSMITTER
REGISTERS
:c
.....
en
oI\)
• TTL COMPATIBLE
• PULL-UP RESISTORS ON ALL INPUTS
APPLICATIONS
•
•
•
•
•
•
•
•
•
•
•
•
•
•
PERIPHERALS
TERMINALS
MINI COMPUTERS
FACSIMILE TRANSMISSION
MODEMS
CONCENTRATORS
ASYNCHRONOUS DATA MULTIPLEXERS
CARD AND TAPE READERS
PRINTERS
DATA SETS
CONTROLLERS
KEYBOARD ENCODERS
REMOTE DATA ACQUISITION SYSTEMS
ASYNCHRONOUS DATA CASSETTES
• THREE-STATE OUTPUTS
Receiver Register Outputs
Status Flags
VCC
vGG
VDD
RRD
RRS
RR7
RR6
RRS
RR4
RR3
RR2
RR1
PE
FE
OE
SFD
RRC
DRR
DR
RI
TRC
EPE
WLS1
WLS2
SBS
THRL
CRL
TAs
TR7
TR6
TRS
TR4
TR3
TR2
TR1
TRO
TRE
THRL
THRE
MR
PIN CONNECTIONS
-t
:c
.....
~
oI\)
TRO
RECEIVER
TIMING AND
CONTROL
CONTROL
REGISTER
VCC~
VGG(~
VDD.i~
TR1602/TR1402 BLOCK DIAGRAM
121
TRANSMITTER
TIMING AND
CONTROL
TRC
THRE
TRE
122
WESTERN DIGITAL
r:
(7
R
P
0
RAT
/
0
N
TR1863/TR1865
Universal Asynchronous Receiver/Transmitter (UART)
FEATURES
• THREE-STATE OUTPUTS
Receiver Register Outputs
Status Flags
• SINGLE POWER SUPPLY - + 5VDC
• D.C. TO 1 MHZ (64 KB) (STANDARD PART)
TR1863/5
• TTL COMPATIBLE
• TR1865 HAS PULL-UP RESISTORS ON ALL
INPUTS
• FULL DUPLEX OR HALF DUPLEX OPERATION
• AUTOMATIC INTERNAL SYNCHRONIZATION
OF DATA AND CLOCK
• AUTOMATIC START BIT GENERATION
• EXTERNALLY SELECTABLE
Word Length
Baud Rate
Even/Odd Parity (ReceiverlVerification Transmitter/Generation)
Parity Inhibit
One, One and One-Half, or Two Stop Bit
Generation (1 V2 at 5 Bit Level)
• AUTOMATIC DATA RECEIVEDITRANSMITTED
STATUS GENERATION
Transmission Complete
Buffer Register Transfer Complete
Received Data Available
Parity Error
Framing Error
Overrun Error
• BUFFERED RECEIVER AND TRANSMITTER
REGISTERS
VCC
NC
vss
RRD
RRS
RR7
RR6
RR5
RR4
RR3
RR2
RR1
PE
FE
OE
SFD
RRC
DRR
DR
RI
APPLICATIONS
•
•
•
•
PERIPHERALS
TERMINALS
MINI COMPUTERS
FACSIMILE TRANSMISSION
•
•
•
•
MODEMS
CONCENTRATORS
ASYNCHRONOUS DATA MULTIPLEXERS
CARD AND TAPE READERS
•
•
•
•
•
•
PRINTERS
DATASETS
CONTROLLERS
KEYBOARD ENCODERS
REMOTE DATA ACQUISITION SYSTEMS
ASYNCHRONOUS DATA CASSETTES
TRC
EPE
WLS1
WLS2
SBS
CRL
TA8
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TAO
TRE
THRL
THRE
MR
PIN CONNECTIONS
TRO
RECEIVER
TIMINGAND
CONTROL
CONTROL
REGISTER
VCC(+5V) ..
VSS(GND) ...
TR1863ITR1865 BLOCK DIAGRAM
123
TRANSMITTER
TIMING AND
CONTROL
TRC
THRE
TRE
124
WESTERN DIGITAL
CORPORATION
WD1983 (BOART)
Bus Oriented Asynchronous Receiver/Transmitter
BAUD RATE-DC TO 36K BITS/SEC (16X)
SELECTABLE CLOCK RATES
FEATURES
ASYNCHRONOUS MODE
•
•
•
•
•
•
•
•
•
•
•
•
• 1X, 16X, 64X, BAUD RATE CLOCK INPUTS
• UP TO 47% DISTORTION ALLOWANCE
WITH 64X CLOCK
FULL DUPLEX OPERATION
SELECTABLE 5,6,7, & 8 BIT CHARACTERS
LINE BREAK DETECTION AND GENERATION
1, 1V2, or 2 STOP BIT SELECTION
FALSE START BIT DETECTION
OVERRUN AND FRAMING ERROR DETECTION
DC TO 36K BITS/SEC (16X)
DC TO 600K BITS/SEC (1 X)
8251/8251 A ASYNCHRONOUS ONLY REPLACEMENT
REQUIRES NO ASYNCHRONOUS SYSTEM CLOCK
28 PIN PLASTIC OR CERAMIC
+5 VOLT ONLY
APPLICATIONS
ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL INTERFACE
GENERAL DESCRIPTION
SYSTEM COMPATIBILITY
• DOUBLE BUFFERING OF DATA
• 8 BIT BI-DIRECTIONAL BUS FOR DATA, STATUS, AND
CONTROL WORDS
• ALL INPUTS AND OUTPUTS TTL COMPATIBLE
• CHIP SELECT, RE, WE, C/O INTERFACE TO CPU
• ON-LINE DIAGNOSTIC CAPABILITY
• THREE STATE DATA BUS
The WD1983 is an N channel silicon gate MOS/LSI device
that interfaces a digital asynchronous channel with a parallel
channel. It is available in a ceramic or plastic standard 28 pin
dual in line package.
The WD1983 is a fully programmable microprocessor I/O peripheral with two control registers and a status register. It is
capable of full duplex operations.
D2
27
D3
Do
26
Vcc(+5V)
(GND)Vss
25
AXe
D4
24
D5
23
DTR
RTs
RXD-
3
D6
WD1983
D7
TXC
WE
22
i'5SR
21
MR
20
NC
10
19
TXD
cs
11
18
TXE
C/D
12
17
-CTs
FiE
13
16
BRKDET
RXRDY
14
15
TXRDY
FIGURE 1 WD1983 PIN-OUT
TXD
RXD
FIGURE 2 WD1983 BLOCK DIAGRAM
125
126
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
WD8250 Asynchronous Communications Element
FEATURES
• Designed to be Easily Interfaced to Most Popular Microprocessors (Z-80, 8080A, 6800, etc.)
• Full Prioritized Interrupt System Controls
• Single
GENERAL DESCRIPTION
• Full Double Buffering
• Independently Controlled Transmit, Receive,
Line Status, and Data Set Interrupts
The WD8250 is a programmable Asynchronous
Communication Element (ACE) in a 40-pin package. The device is fabricated in N/MOS silicon
gate technology.
• Programmable Baud Rate Generator Allows
Division of Any Input Clock by 1 to (2 16 - 1)
and Generates the Internal 16x Clock
The ACE is a software-oriented device using a
three-state 8-bit bi-directional data bus.
• Independent Receiver Clock Input
• Fully Programmable Serial-Interface
Characteristics
-5-, 6-, 7-, or 8-Bit Characters
-Even, Odd, or No-Parity Bit Generation and
Detection
-1-, 1112 -, or 2-Stop Bit Generation
-Baud Rate Generation (DC to 56K Baud)
The ACE is used to convert parallel data to a serial
format on the transmit side, and convert serial
data to parallel on the receiver side. The serial
format, in order of transmission and reception, is
a start bit, followed by five to eight data bits, a
parity bit (if programmed) and one, one and one
half (five bit format only) or two stop bits. The
maximum recommended data rate is 56K baud.
Internal registers enable the user to program
various types of interrupts, modem controls, and
character formats. The user can read the status of
the ACE at any time monitoring word conditions,
interrupts and modem status.
An additional feature of the ACE is a programmable baud rate generator that is capable of
dividing an internal XTAL or TTL Signal clock by a
division of 1 to 216 - 1.
The ACE is designed to work in either a polling or
interrupt driven system, which is programmable
by users software controlling an internal register.
• False Start Bit Detector
• Complete Status Reporting Capabilities
• THREE-STATE TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection
• Internal Diagnostic Capabilities
-Loopback Controls for Communications
Link Fault Isolation
-Break, Parity, Overrun, Framing Error
Simulation
DO
D,
D,
+ 5-Volt Power Supply
Vee
AI
RLSO
D3
D,
37
5SR
36
CTS
34
OUT 1
DYR
D5
D6
D7
WD8250
SOUl
11
csa
12
33
32
31
30
29
CS1
=
B"AUDOUT
27
'6
25
XTAL2
17
DOSTR
18
SEAIALIN
DATA
}
TO FROM
PERIPHERAL
MODEM OA
OATAsn
SYSTEM
PROCESSOR
SERIAL
DATA OUT
INTRPT
NC
MODEM·CONTAOl
AD
FUNCTIONS
TO FROM MODEM
OR DATA SET
A,
A,
ADS
SYSTEM
DOSTR
OISTR
Vss
OIS'(R
INTERRUPT
PIN DESIGNATION
WD8250 GENERAL SYSTEM CONFIGURATION
127
128
WESTERN DIGITAL
c
o
R
o
p
R
A
T
/
o
N
WD2123 DEUCE
Dual Enhanced Universal Communications Element
FEATURES
• TWO INDEPENDENT ASYNCHRONOUS FULL DUPLEX
DATA COMMUNICATION CHANNELS (2 BOARTS)
• TWO INDEPENDENT BAUD RATE GENERATORS (ONE
PER CHANNEL)
• EACH CHANNEL WITH FOLLOWING FEATURES:
• SELECTABLE 5 TO 8 BIT CHARACTERS
• 1X, 16X, 64X CLOCK RATES
• 16 SELECTABLE BAUD RATE CLOCK FREQUENCIES
(INTERNAL)
• LINE BREAK DETECTION AND GENERATION
• 1, 1V2, OR 2 STOP BIT SELECTION
• FALSE START BIT DETECTION
• ODD OR EVEN PARITY GENERATE AND DETECTION
• OVERRUN AND FRAMING DETECTION
• DOUBLE BUFFERING OF DATA
• TTL COMA6.TIBLE INPUTS AND OUTPUTS
• COMA6.TIBLE WITH 8251 A (ASYNC ONLy) AND WD1983
DEVICES
• DIAGNOSTIC LOCAL LOOP-BACK MODE
• RXD INITIALIZATION UPON MASTER RESET
• ON-BOARD OSCILLATOR FOR EASE OF USE WITH A
CRYSTAL
• VERSATILE CLOCK SELECT OPTIONS FOR INDEPENDENT TRANSMIT AND RECEIVE RATES
INTRODUCTION
The Western Digital WD2123 Dual Enhanced Universal
Communications Element (DEUCE) is a single chip MOS/LSI
Data Communications Controller Circuit that contains two
independent full-duplex asynchronous RECEIVERITRANSMITTER CHANNELS and two independent BAUD RATE
GENERATORS_ The WD2123 is fabricated in N-Channel silicon gate technology and is packaged in a 40 pin plastic or
ceramic package_ All inputs and outputs are TTL compatible.
DATA
BUS
WE
FiE
c/o
MR
BUS TRANSCEIVERS
TXROY-B
NC
39
TXO-B
CS2
(8)
CSi
RXROY-B
RXO-B
38
TXE-B
~
37
BRKOET-B
TXD-A
CS1
36
RTS-B
RXD-A
C/rl"
35
Ci'S-B
DO
34
SELCLK-B
01
33
XCI/BCQ-B
___
TXRDY-A
CHANNEL
RXRDY-A
TXD-B
RXD-B
TXRDY-B
CHANNEL
RXRDY-B
B
TXE-B
TXE-A
BRKDET-B
BRKDET-A
32
XTAL2
RTS-A
RTS-B
VSS
10
31
XTAL1
ffi-A
ffi-B
03
11
30
VCC
02
WD2123
04
12
29
MR
05
13
28
XCI/BCQ-A
06
14
27
SELCLK-A
07
15
26
C'fS-A
Cs2
WE
16
25
R'I'S-A
17
24
BRKOET-A
CS3
18
23
TXE-A
RXO-A
19
22
RXROY-A
TXO-A
20
21
TXROY-A
SELCLK-A
BAUD RATE
BAUD RATE
GENERATOR
GENERATOR
XCI/BCO-B
XCI/BCO-A
GND
+5V
Figure 1. WD2123
SELCLK-B
PINOUT DIAGRAM
Figure 2. WD2123
129
BLOCK DIAGRAM
130
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
BR1941(5016) Dual Baud Rate Clock
FEATURES
GENERAL DESCRIPTION
• 16 SELECTABLE BAUD RATE CLOCK FREQUENCIES
• SELECTABLE 1X, 16X OR 32X CLOCK OUTPUTS FOR
FULL DUPLEX OPERATIONS
• OPERATES WITH CRYSTAL OSCILLATOR OR
EXTERNALLY GENERATED FREQUENCY INPUT
• ROM MASKABLE FOR NON-STANDARD FREQUENCY
SELECTIONS
• INTERFACES EASILY WITH MICROCOMPUTERS
• OUTPUTS A 50% DUTY CYCLE CLOCK WITH 0.Q1 %
ACCURACY
• 6 DIFFERENT FREQUENCY/DIVISOR PAIRS
AVAILABLE
• TTL, MOS COMPATIBILITY
The BR1941 is a combination Baud Rate Clock Generator and Programmable Divider. It is manufactured in
N-channel MOS using silicon gate technology. This device is capable of generating 16 externally selected
clock rates whose frequency is determined by either a
single crystal or an externally generated input clock.
The BR1941 is a programmable counter capable of
generating a division from 2 to (215 - 1).
The BR1941 is available programmed with the most
used frequencies in data communication. Each
frequency is selectable by strobing or hard wiring each
of the two sets of four Rate Select inputs. Other
frequencies/division rates can be generated by
reprogramming the internal ROM coding through a
MOS mask change. Additionally, further clock division
may be accomplished through cascading of devices.
The frequency output is fed into the XTALlEXT input
on a subsequent device.
• PIN COMPATIBLE WITH COM5016
FREQUENCY
SELECT
ROM
DIVIDER
fT
DIVIDER
fR
*INTERNALLY BONDED. DO NOT CONNECT
ANYTHING TO THIS PIN.
BR1941 BLOCK DIAGRAM
PIN CONNECTIONS
131
132
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
WD1943(8116)IWD1945(8136) Dual Baud Rate Clock
FEATURES
GENERAL DESCRIPTION
-16 SELECTABLE BAUD RATE CLOCK FREQUENCIES
The WD1943/45 is an enhanced version of the BR1941 Dual
Baud Rate Clock. The WD1943/45 is a combination Baud
Rate Clock Generator and Programmable Divider. It is
manufactured in N-channel MOS using silicon gate
technology. This device is capable of generating 16 externally selected clock rates whose frequency is determined by either a single crystal or an externally generated
input clock. The WD1943/45 is a programmable counter
capable of generating a division by any integer from 4 to
215 - 1, inclusive.
- OPERATES WITH CRYSTAL OSCILLATOR OR EXTERNALLY GENERATED FREQUENCY INPUT
- ROM MASKABLE FOR NON-STANDARD FREQUENCY
SELECTIONS
-INTERFACES EASILY WITH MICROCOMPUTERS
- OUTPUTS A 50% DUTY CYCLE CLOCK WITH 0.Q1 %
ACCURACY
- 6 DIFFERENT FREQUENCY/DIVISOR PAIRS
AVAILABLE
The WD1943/45 is available programmed with the most
used frequencies in data communication. Each frequency
is selectable by strobing or hard wiring each of the two sets
of four Rate Select inputs. Other frequencies/division rates
can be generated by reprogramming the internal ROM
coding through a MOS mask change. Additionally, further
clock division may be accomplished through cascading of
devices. The frequency output is fed into the XTAUEXT
input on a subsequent device.
-SINGLE +5V POWER SUPPLY
- COMPATIBLE WITH BR1941
- TTL, MOS COMPATIBILITY
- WD1943IS PIN COMPATIBLE TO THE COM8116
- WD1945IS PIN COMPATIBLE TO THE COM8136 AND
COM5036 (PIN 9 ON WD1945IS A NO CONNECl)
The WD1943/45 can be driven by an external crystal or by
TTL logic.
TA
TS
TC
FREQUENCY
SELECT
ROM
TO
XTALlEXT 1
XTALlEXT 2
+5V
IT
IR
TA
AA
TS
AS
TC
AC
TO
Ao
STT
STR
fT
1/4
(1945)
fR
GNO
NC(1943)
NC
RA
1/4 (1945)
RS
RC
RD
BLOCK DIAGRAM
PIN CONNECTIONS
133
134
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
UC1671 ASTRO
8 SELECTABLE CLOCK RATES
• Accepts 1X Clock and Up to 4 Different 32X
Baud Rate Clock Inputs
• Up to 47% Distortion Allowance with
32X Clock
FEATURES
SYNCHRONOUS AND ASYNCHRONOUS
• Full Duplex Operations
SYNCHRONOUS MODE
• Selectable 5-8 Bit Characters
• Two Successive SYN Characters Sets
Synchronization
• Programmable SYN and DLE Character
Stripping
• Programmable SYN and DLE-SYN Fill
ASYNCH RONOUS MODE
• Selectable 5-8 Bit Characters
• Line Break Detection and Generation
• 1-, 1V2-, or 2-Stop Bit Selection
• False Start Bit Detection Automatic Serial
Echo Mode
APPLICATIONS
SYNCHRONOUS COMMUNICATIONS
ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL COMMUNICATIONS
GENERAL DESCRIPTION
The UC1671 (ASTRO) is a MOS/LSI device which
performs the functions of interfacing a serial data
communication channel to a parallel digital system.
The device is capable of full duplex communications
(receiving and transmitting) with synchronous or
asynchronous systems. The ASTRO is designed to
operate on a multiplexed bus with other bus-oriented
devices. Its operation is programmed by a processor
or controller via the bus and all parallel data transfers
with these machines are accomplished over the bus
lines.
SYSTEM COMPATIBILITY
• Double Buffering of Data
• 8-Bit Bi-Directional Bus For Data, Status,
and Control Words
• All Inputs and Outputs TTL Compatible
• Up to 32 ASTROS Can Be Addressed On Bus
• On-Line Diagnostic Capability
TRANSMISSION ERROR DETECTION-PARITY
• Overrun and Framing
BAUD RATE -
The ASTRO is fabricated in n-channel silicon gate
MOS technology and is TTL compatible on all inputs
and outputs.
DC TO 1M BIT/SEC
(-5V) VBB
IAcKi
IXRC
cs
IXTC
WE
IACKO
R3
RPLY
R2
INTR
OALO
R4
OAL1
R3
OAL2
R2
OAL3
R1
m
OAL4
CARR (CF)
g
U)
:::>
I)AL5
OAL6
OAL7
OTR(CO)
MR
INTii
107
RPLY
RING (CE)
IACKO
MISC
IACKI
(GNO)VSS
WE
PIN CONNECTIONS
19 19 1919 19
UC1671 BLOCK DIAGRAM
135
136
WESTERN DIGITAL
o
c
p
R
o
A
R
T
/
o
N
WD1931 Asynchronous/Synchronous Receiver/Transmitter
FEATURES
8 SELECTABLE CLOCK RATES
• Accepts 1X Clock and Up to Four Different 32X
Baud Rate Clock Inputs
• Up to 47% Distortion Allowance with 32X Clock
SYNCHRONOUS AND ASYNCHRONOUS
• Full Duplex Operations
• Selectable Character Length (5, 6, 7 or 8 Bits)
SYNCHRONOUS MODE
• Two Successive SYN Characters Sets
Synchron ization
• Programmable SYN and OLE Character
Detection and Stripping
• Programmable SYN and DLE-SYN Fill
• Transparent BI-SYNC Operation
• DDCMP Compatible
ASYNCHRONOUS MODE
• Line Break Detection and Generation
• 1-, 1112-, or 2-Stop Bit Selection
• False Start Bit Detection
• Automatic Serial Echo Mode
• Overrun and Framing Error Detection
PINOUT COMPATIBLE TO WD193X FOR
MULTIPROTOCOL BOARD APPLICATIONS
APPLICATIONS
SYNCHRONOUS COMMUNICATIONS
ASYNCHRONOUS COMMUNICATIONS
SERIAL/PARALLEL COMMUNICATIONS
GENERAL DESCRIPTIONS
The WD1931 is a MOS/LSI device which performs the
functions of interfacing a serial data communications channel to a parallel digital system. This
device is capable of full duplex communications with
asynchronous and/or synchronous systems. Western
Digital has made device pin assignments for the
WD1931 to make it compatible with the WD193X
(Synchronous Data Link Controller). This pin out
allows the user to implement a one-board multiprotocol design. For character-oriented asynchronous and/or synchronous (bi-sync) protocols, the
WD1931 is used, and for bit-oriented SDLC, HOLC
and ADCCP protocols the WD193X is used (see
WD193X data sheets and WD1931IWD193X compatibility application notes).
SYSTEM COMPATIBILITY
• Double Buffering of Data
• 8-Bit Bi-Directional Bus for Data, Status, and
Control Words
• All Inputs and Outputs TTL Compatible
• Chip Select, RE, WE, AO, A1 Interface to CPU
• On-Line Diagnostic Capability
• Data Set, Carrier Detect, and Ring Interrupts
BAUD RATE - DC TO 1M BIT/SEC
CD
R4
R3
R2
Ai
OSR
RTS
1xTC
COMPARISON
REGISTER
RSCLK
I
CTS·
! > - - - t - - - - - TBOC
I
TBOC
RO
VO O (+ 12V)
A1
_VSS (GNO)
AD
A1
CS
WE
RE
MOOEM
INTERFACE
CONTROL
CLOCK
CONTROL
....- VCC (+6)
-
PIN CONNECTIONS
Figure 1.
WD1931 PIN CONNECTIONS
Figure 2.
137
WD1931 BLOCK DIAGRAM
VOO (+ 12)
138
WESTERN DIGITAL
CORPORATION
WD1933IWD1935
Synchronous Data Link Controller
FEATURES
• PROGRAMMABLE MODEM CONTROL INTERRUPTS
• HDLC, SDLC, ADCCP AND CCID X.25 COMPATIBLE
• DOUBLE BUFFERING OF DATA
• SDLC LOOP DATA LINK CAPABILITY
• DMA COMPATABILITY
• FULL OR HALF DUPLEX OPERATION
• END OF BLOCK OPTION
• DC TO 2.0 MBITS/SEC DATA RATE
• VARIABLE CHARACTER LENGTH (5,6,7 OR 8 BITS)
• PROGRAMMABLE/AUTOMATIC FCS (CRC) GENERA·
TION AND CHECKING
• RESIDUAL CHARACTER CAPABILITY
• ADDRESS COMPARE
• PROGRAMMABLE NRZI ENCODE/DECODE
• GLOBAL ADDRESS RECOGNITION
• FULL SET OF MODEM CONTROL SIGNALS
• EXTENDABLE ADDRESS FIELD
• DIGITAL PHASE LOCKED LOOP
• EXTENDABLE CONTROL FIELD
• FULLY COMPATIBLE WITH MOST CPU'S
• AUTOMATIC ZERO INSERTION AND DELETION
• MINIMUM CPU OVERHEAD
• MAINTENANCE MODE FOR SELF·TESTING
• ASYNCHRONOUS/SYNCHRONOUS
MULTI-PROTOCOL BOARD CAPABILITY (PIN COMPATIBLE WITH WD
1931)
• FULLY TTL COMPATIBLE
APPLICATIONS
• SINGLE +5V SUPPLY
COMPUTER COMMUNICATIONS
• ERROR DETECTION: CRC, UNDERRUN, OVERRUN,
ABORTED OR INVALID FRAME ERRORS
TERMINAL COMMUNICATIONS
• STRAIGHT FORWARD CPU INTERRUPTS
COMPUTER TO MODEM INTERFACING
(1933) (1935) -
NC
REOM
1
EOB
2
INTRa
WE
6
7
D1
D2
D3
D4
os
TC
1XJ32X
13
D6
D7
17
CTS
NRZI
RD
RC
MR
DTR
ORaD
24
MISC IN
ORal
VSS (GND)
Figure 1.
WD193X
Figure 2.
PIN DESIGNATION
139
WD193X BLOCK DIAGRAM
140
WESTERN DIGITAL
C
0
,R
P
0
RAT
/
0
N
WD1993 Arinc 429 Receiver/Transmitter
and Multi-Character Receiver/Transmitter
FEATURES
•
PRESENT UPON MASTER RESET FOR ARINC 429
PROTOCOL
•
PROGRAMMABLE WORD LENGTH FROM 1 CHARACTER TO 8 CHARACTERS
•
PROGRAMMABLE CHARACTER LENGTH, 5, 6, 7,
OR 8 BITS
•
• SINGLE +5 VOLT SUPPLY
• TEMPERATURE RANGES O°C to 70°C, - 1993-03,
- 40°C to + 85°C - 1993-02, - 55°C to + 125°C 1993-01
INTRODUCTION
The Western Digital WD1993 Avionic Receiver/Transmitter
is designed to handle digital data transmission, according to
the Avionic Arinc 429 protocol. Also, the word length is programmable from one to eight characters of 5, 6, 7, or 8 bits.
Parallel data is converted into a serial data stream during
transmission and serial to parallel during reception. The
WD1993 is packaged in a 28 pin plastic or ceramic package
and is available in three temperature ranges: Commercial,
Industrial and Military.
RETURN TO ZERO (RZ) OUTPUT
• AUTO SPACE GENERATION
•
DOUBLE BUFFERED RECEIVER AND TRANSMITIER
•
UNDERRUN ERROR DETECTION FOR TRANSMISSION
• OVERRUN, FRAMING AND PARITY ERROR DETECTION ON RECEIVER
• WORD ERROR FLAG FOR COMPREHENSIVE
ERROR REPORTING
•
FIRST CHARACTER OF WORD FLAG FOR SINGLE
INTERRUPT APPLICATIONS
•
DIAGNOSTIC LOCAL LOOP-BACK TEST MODE
•
DC TO 200 KILOBITS PER SECOND OPERATION
GENERAL DESCRIPTION
The WD1993 is a bus-orientated MOS/LSI device designed
to provide the Avionics Arinc 429 Data Communication Protocol, along with programmable character length capabilities.
Also, the WD1993 contains a local loop-back test mode of
operation, which is controlled by the Loop Test Enable (LTE)
bit in the command register. In this diagnostic mode, the
transmitter output is "looped-back" into the receiver input.
The REN and TEN control bits must also be active ("1") and
the CTS input must be low. The status and output flags operate normally.
• TIL COMPATIBLE INPUTS AND OUTPUTS
TXC
RE
c/o
Cs"
WE
N.C.
07
MR
06
TXE
05
RXROY
04
TXROY
03
TXOO
02
VSS
WEF
CTS
TX01
01
RXC
DO
FCR
RXOO
RX01
VCC
Os
Ai:
AEADIWRtTE
WE
Figure 1 PIN DIAGRAM
CONTROL
en
Figure 2 WD1993 BLOCK DIAGRAM
141
142
WESTERN DIGITAL
c
o
p
R
o
R
A
T
o
/
:ec
N
N
WD2001/WD2002 Data Encryption Devices
o
o
~
FEATURES
ic
APPLICATIONS
• SECURE BROKERAGE TRANSACTIONS
• CERTIFIED
DARDS.
BY
NATIONAL
BUREAU
OF
N
o
o
• ELECTRONIC FUNDS TRANSFERS
STAN-
• SECURE BANKING/BUSINESS ACCOUNTING
• TRANSFER RATE:
WD2001/2-05 300Kbs with 500KHz clock
WD2001/2-20 1.3 Mbs with 2MHz clock
WD200112-30 1.8 Mbs with 3MHz clock
• REMOTE AND HOST COMPUTER
COMMUNICATIONS
• ENCRYPTS/DECRYPTS 64 BIT DATA WORDS USING
56 BIT KEY WORD
• SECURE DISK OR MAG TAPE DATA STORAGE
• MAINFRAME COMMUNICATIONS
• SECURE AID
• SECURE PACKET SWITCHING TRANSMISSION
• SINGLE PORT 28 PIN PACKAGE WD2001 OR DUAL
PORT 40 PIN PACKAGE WD2002
GENERAL DESCRIPTION
The Western Digital WD2001 and WD2002 Data
Encryption / Decryption devices are designed to encrypt
and decrypt 64-bit blocks of data using the algorithm
specified in the Federal Informa.~ion Processing Data
Encryption Standard (#46). These devices encrypt a
64-Bit clear text word using a 56-Bit user-specified key
to produce a 64-Bit cipher text word. When reversed,
the cipher text word is decrypted to produce the
original clear text word.
The DE2001/2 are fabricated in N-channel silicon gate
MOS technology and are TTL compatible on all inputs
and outputs.
• COMMAND BIT PROGRAMMING VIA DAL BUS OR
INPUT PINS
• DMA COMPATIBLE
DM1883)
(SEE
WESTERN
DIGITAL
• PARITY CHECK ON KEY WORD LOADING
• STANDARD 8 BIT MICROPROCESSOR INTERFACE
• INPUTS AND OUTPUTS TTL COMPATIBLE
• KEY STORED
ACCESSIBLE
ON
CHIP
IS
NOT
EXTERNALLY
SEPARATE CLEAR AND CIPHER BUS STRUCTURE
ON WD2002
_ ( + 12IVOD
_(+51 Vee
_IGNDlVSS
KA
WD2001/WD2002 BLOCK DIAGRAM
143
OIR
DiA
OOR
OOA
ACT
EIO
CAPs
KEOE
DPs
N
144
WESTERN DIGITAL
o
c
R
o
p
R
A
T
/
o
N
DM1883A/B Direct Memory Access Controller
FEATURES
GENERAL DESCRIPTION
•
The DM1883 Direct Memory Access Controller
(DMAC) is packaged in a 40 pin standard dual inline package. The chip requires a single +5 power
supply input and a single clock input. The device
contains 8 CPU addressable registers, and allows
for up to 8 CPU addressable device registers if the
automatic device chip select feature is used. Byte or
word transfers can be programmed, and all memory
DMA operations are handshaked for compatibility
with a variety of bus structures. Up to 256K bytes of
memory can be accessed directly with 64K page
protection and nonexistent memory interrupt as
options. Bus and Interrupt Acknowledge signals are
internally daisy chained, and a STOP REQUEST
input prevents new requests while a current request
is active. Device accesses are not handshaked, and
a BUS HOLD feature is present for high speed
devices. Device interrupt input, end-of-block
output. and I/O read/write output pins simplify
hardware interfacing to the device and the CPU bus.
The AUTO LOAD feature allows automatic bootloading of up to 64K bytes or words into memory
starting at location zero. An 8 bit interrupt 10 code is
also provided.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
AUTOMATIC DAISY CHAINING OF BUS AND
INTERRUPT ACKNOWLEDGE SIGNALS
AUTO LOAD OPTION
SINGLE +5 VDC POWER SUPPLY
8 BIT BI-DIRECTIONAL DATA BUS
TRUE OR COMPLEMENT DATA BUS
8 CPU ADDRESSABLE DMAC REGISTERS
8 CPU ADDRESSABLE DEVICE REGISTERS
AUTOMATIC GENERATION OF DEVICE CS
DURING DMA AND CPU DEVICE ACCESSES
256K MEMORY ADDRESSING
64K PROGRAMMABLE PAGE PROTECTION
BYTE OR WORD DMA TRANSFERS
INTERRUPT AND BUS REQUEST CAPABILITIES
END-OF-BLOCK SHUT OFF BY DMAC
TIME-OUT INTERRUPT CAPABILITY
SINGLE CLOCK INPUT
CS, RE, WE, AO-A3 ADDRESSING
STOP REQUEST INPUT TO DELAY INTERRUPT OR BUS REQUESTS
COMPATIBLE WITH OUR FLOPPY DISC
CONTROLLERS
8 BIT PROGRAMMABLE INTERRUPT
IDCODE
AEB
vss
INTR
DRQ
DINTR
REPLY
EOB
BACKI
AUTLD
A3
BOW
BUSR
DAlD
cs
DAL2
DCS
DAL3
FiE
DAl4
WE
DAL5
MEMR
DAl6
MEMW
MR
DAl7
AE8
ClK
TOB
MYSNC
A1
RiW
AD
LAL
IACKI
DAL6
DAL1
BACKO
STOPR
OAL7
A2
IACKO
VCC(+5)
MEMR
MEMW
BOw -------MSYNC
fiE
WE
OINTR - DRQ
5CS
REPLY
EOB
PIN CONNECTIONS
DM1883 BLOCK DIAGRAM
145
146
WESTERN DIGITAL
CORPORATION
Application Note
Using The WD2501/2511
This application note provides an introduction to the
X.25 communication protocol and introduces the ISO
reference model. The link layer of X.25 is highlighted
as it can today be implemented with a single LSI
device, the WD2501/WD2511.
The bulk of this document provides details of the
hardware and software interfaces that a user typically
encounters when using the WD2501. Schematic and
timing diagrams for a typical Z80 interface along with
high level flowcharts for initialization and operation
are given.
Three appendices cover a glossary, a discussion of
X.25 LAP vs LAPB, and using the WD2501/WD2511 in
multi-point configuration.
NOTE:
Unless otherwise noted in this document, all
references to the WD2501 should be assumed to
pertain to the WD2511 as well.
In addition to the traditional parallel/serial converters
and FCS logic, the WD2501 incorporates a highly
efficient micro-programmed processor that fully
handles the required link set-up and frame sequenc·
ing operations conventionally delegated to a "user
defined" processor. The WD2501 also contains an
intelligent two-channel DMA controller to further
simplify its integration into a user's system.
2.0 THE WD2501 AND THE ISO MODEL
The CCITT X.25 recommendation comprises three
levels of protocols (Level 1 to 3). See Figure 1.
Level 1 is the physical level, which concerns the
actual means of bit transmission across a physical
medium.
Level 2 is the link level which includes frame formatting, error control and link control.
Level 3 is the packet (network) level which controls
the traffic of the different virtual calls and multiplexes these for passage over the physical line.
These three levels are completely independent of
each other, which allows changes to be made to one
level without disrupting the operation of any other
level. An adjacent level is affected only if the changes
affect the interface to that level.
Each level performs one well defined set of functions, using only a well defined set of services
provided by the level below. These functions im·
plement a set of services that can be accessed only
from the level above. Each level is strictly controlled
by the systems engineer according to formal functional and interface specifications.
The WD2501 implements level 2. Without additional
logic, it generates the frame, performs error checking, performs link management (set up/disconnect)
and ensures reliable data transmission by evaluating
the sequence numbers associated with each I-frame.
The device automatically acknowledges received 1frames and fully supports up to 7 outstanding
(unacknowledged) frames, including retransmission
if required.
CONTENTS
1.0 The WD2501/2511 General Description
2.0 The WD2501 and the ISO Model
3.0 Hardware
4.0 Software
Appendix A Glossary
Appendix B LAP vs LAPB
Appendix C Using the WD2501/2511 in a Multipoint
Configuration
RELATED DOCUMENTS
WD2501 Specification
WD2511 Specification
"LSI Ready to Make a Mark on Packet-Switching
Networks," Geary Leger, Electronics, December 20,
1979.
"LSI Circuit Simplifies Packet-Network Connection,"
Geary Leger, Electronics, December 20, 1979.
1.0 THE WD2501/2511 General Description
The WD2501 and WD2511 are LSI devices that fully
handle the link level (level 2) of the CCITT X.25
communications protocol. They are pin·compatible
with each other and with other members of the
Western Digital Network Controller Family.
The distinction between the WD2501 and the
WD2511 lies in their internal firmware: the WD2501
implements LAP (Link Access Procedure) whereas
the WD2511 implements LAPB (Link Access
Procedure Balanced). The protocol differences
between LAP and LAPB are described in Appendix B.
147
:eC
LEVEL
I\)
(J1
....
-........
0
USER
PROCESS
4·7
USER
PROCESS
I \)
(J1
LEVEL 3/4 INTERFACE
PACKET
LEVEL
------.
PACKET
LEVEL
t
LEVEL 2/3 INTERFACE
LINK
LEVEL
LINK
LEVEL
LEVEL1~INTERFACE
PHYSICAL
LEVEL
PHYSICAL
LINK
PHYSICAL
LEVEL
DTEIDCE
DTE
Figure 1. LAYERED ARCHITECTURE FOR COMPUTER NETWORKS
The only real physical connection between the two
stations (DTE to DTEJDCE) is the Physical Link
between the two physical layers. The other connections shown between two of the same layers
(peer to peer interface) is not a physical but rather a
logical connection made up by the respective
protocols for that particular level.
Each level n "interfaces" to the corresponding level n
on the other side of the Data Communication
Link through the level n-1, then n-2 etc., via the
physical link and up through the levels to n-2, n-1 and
to level n.
3.0 HARDWARE
The WD2501 must be connected to the Physical
Level (level 1). This generally amounts to simple line
drivers/receivers.
A typical X.25 DTEJDCE station block diagram is
shown in Figure 2. Figure 3 shows a circuit diagram
of the actual X.25 hardware interface of this same
station. Table 1 is a description of signal functions for
this circuit diagram. This is to be connected directly
to a Z80 microprocessor on one side and an EIA RS422 interface on the other side.
Figures 4 and 5 are DMA cycle timing diagrams for
this particular station.
General notes to this interface:
• A modem would be needed for long-distance
communication lines.
• The hardware interface in Figure 3 includes all
hardware options. Simpler interfacing is possible.
• The function of the CPU Bus Driver Control Circuit
(CBDCC) is to control the direction and/or timing
of the data-line transceivers and the two address
latches.
• If the CPU clock frequency is not higher than the
WD2501 ClK maximum frequency, the High
Speed Control Circuit (HSCC) is not needed. The
function of the HSCC circuit is to divide an high
speed CPU clock signal (0) down to half the
frequency (01 A). It also delays the reset of
BUSRQ with one additional 01 clock cycle when
a high speed CPU clock is used. These functions
are needed to establish a time window of at least
500ns between DACK being active and a CPU
Write/Read function.
148
During a read operation, the falling edge of RE will
initiate a WD2501 read cycle. The addressed register
will then place its content onto the Data Bus.
To insure that all six status registers (registers 2 thru
7, inclusive) are read correctly, either rule A or rule B
must be followed (or both):
A) Enable CS • RE only while the ClK input is high.
B) Read the status registers only after an interrupt,
and read within one frame time of the interrupt.
If rule A) is used, the high ClK may (at the user's
option) be extended by skippin9..i?ne~nd only one,
negative going ClK whenever a CS • RE is executed.
This is shown below:
• When a high speed CPU clock is used, connect
0bA signal to 01 signal and BUSRQA signal to
B SRQ signal. When a low speed CPU clock is
used, connect CPU clock (0) direct to 01 signal and
BUSRQ2 signal to BUSRQ signal.
• The ClK circuit is needed in all applications. Its
purpose is to stop the ClK signal from going lO
during a CPU read cycle. This logic will avoid any
possible interference between an internal updating of a status register while the CPU reads this
same register.
• The DMA I/O circuit matches the timing between
the Z80 and the WD2501.
• The RTS open collector output needs a pull-up
resistor.
• In this particular example, line drivers/receivers are
of type EIA RS-422. However, RS-232C or RS-423
can also easily be used.
• Port A of a Pia in this example is programmed to
be an output. In this case, the CPU controls the
DTR output to the modem. Port B of the Pia is
programmed to be interrupt controlled inputs; the
CPU can be interrupted by DSR and/or INTR as
programmed.
• The WD2501 ClK input is derived from the Z80
CPU clock. The ClK may be supplied from an
independent clock generator. In that case, instead
of connecting the 01 clock to the ClK circuit,
connect the independent clock to where the 01
clock is shown in the ClK circuit in Figure 3.
• MRW (Memory Read/Write) signal enables the
output of the memory address decoder for the
computer system memory chips. As an example, if
a PROM type 28S42 is used as the memory address decoder, MRW is connected direct to E
(Pin 15) input.
ClK
One negative ClK
is skipped
As a reminder, the long form speCification already
states that ClK must be a square wave.
Non-conformance to the Rule above could mean that
the CPU will at rare times read incorrect values of NA,
N B, N E, ERa, or any other status.
The CPU must set-up all transmit data, TSADR HI and
la, TCNT HI and la, and residual bits before setting
BRDY in the applicable TlOOK segment.
The CPU must set aside receiver memory (at least
one chain segment with transfer address), and set-up
RSADR HI and lO before setting REC RDY in the
applicable RlOOK segment.
3.2 DMA INIOUT OPERATION
The Direct Memory Access (DMA) operation is
completely controlled by the WD2501. During a DMA
cycle, the CPU sets its address bus, data bus and
three-state control signals to their high impedance
states.
(See DMA In/Out timing diagrams, Figures 4 and 5.)
In this application example, the data bus transceivers
are permanently enabled (low impedance state).
When the CPU has control, the direction of these
transceivers is pointing from the CPU bus towards
the WD2501. During a DMA In cycle, this is not
changed. During a DMA Out cycle however, the
direction is reversed (WD2501 towards the CPU bus).
The address bus latches are in high impedance state
while the CPU has control of the bus. When the
WD2501 has control of the CPU bus, the address
latches are in the low impedance state. During the
DMA Out cycle, these latches function as regular bus
drivers. During the DMA In cycle however, the address gets latched to assure enough data hold time
for the WD2501.
• The WD2501 CS input is to be connected to a port
address decoder (or mem..2!}' address decodeO.
MWE is connected to all WE inputs, and MOE
is connected to all OE inputs of the system
memory chips.
• REPLY output is not used in this application.
3_1 READIWRITE CONTROL OF 1/0 REGISTERS
The sixteen I/O registers are directly accessible from
the CPU data bus (DAlO-DAl7) by a read and/or write
operation by the CPU. The CPU must activate the
WD2501 register address (IAO-IA3), 9:!!P Select (CS ),
Write Enable (WE ) or Read Enable (RE ) before each
data bus transfer oRe ration. The read/write operation
is completed when CS or RE /WE is brou9.!n high.
During a write operation, the falling edge of WE will
initiate a WD2501 write cycle. The addressed register
will then be loaded with the content of the Data Bus.
The rising edge of WE will latch that data into the
addressed register.
149
3.2.1 DMA IN
3.2.2 DMA OUT
During a DMA In cycle, the task of transferring one
byte of I-field data from memory into the WD2501 is
performed. The CPU time (in the example described
in this paragraph to execute this task) is five T-states
for a low speed CPU clock system and ten T-states
for a high speed CPU clock system.
The DMA In function starts when the WD2501 is
ready to receive a byte from memory to be transmitted out to the remote station. This condition
causes the DRQI signal to go La, which in turn
activates the BUSRQ (Bus Request) signal. Also at
this time (ADRV bit = 1), the WD2501 presents the
address (on AO-A15) of the data byte to be retrieved
from memory.
The BUSRO signal is sampled by the CPU with the
rising edge of the last CPU clock (0) period of any
machine cycle. In this case, because the BUSRO
signal is active, the CPU goes into high impedance
state with the rising edge of the next CPU clock
pulse. At this time, the CPU also switches the control
over to the WD2501 by activating the BUSAK signal.
This causes DACK to go La at the following rising
edge of 01 clock. This is the actual indication for the
WD2501 to start the DMA In cycle. DACK also
causes DROI to return to the HI state.
At the next rising edge of the 01 clock, MOE
(Memory Output Enable) is activated. This causes the
memory to output the addressed data byte onto the
Data Bus. Also, the address is now latched into the
address bus latches (74LS373) at this time.
At the next falling edge of the 01 clock, DACK gets
deactivated, causing the WD2501 to latch the data
byte (DALO-DAL7) and to set its address lines (AOA 15) to logical HI state (ADRV bit set). The address
bus latches hold the address active until DMOE
signal is deactivated.
At the next rising edge of the 01 clock (low speed
CPU clock), BUSRO gets deactivated. When high
speed CPU clock is used, BUSRO is deactivated
after an additional 01 clock cycle.
At the next following rising edge of 01 clock,
BUSRO is sampled by the CPU. This causes
BUSAK and MOE to become deactivated, but not
until the next falling edge of the CPU (0) clock. This is
the end of the DMA In cycle. At the next rising edge
of the CPU clock, the CPU again controls the CPU
bus.
This operation is very similar to the DMA In function.
During this cycle, one byte of I-field data is transferred from the WD2501 to the memory. The CPUtime in this example described to perform this task is
the same as for the DMA In cycle.
The DMA Out function starts when the WD2501 is
holding a received I-field byte and is ready to transfer
this to the memory. This condition activates the
DROO signal, which in turn sets the BUSRO to La.
Also at this time (ADRV bit = 1), the WD2501
presents the address to the memory location to
where the respective data byte is to be loaded.
The BUSRQ signal is sampled by the CPU \AJith the
rising edge of the last CPU clock period of any
machine cycle. Since the BUSRO signal is active,
the CPU goes into high impedance state with the
rising edge of the following CPU clock pulse. Now
the CPU also switches the control over to the
WD250~ activating the BUSAK
signal. This
causes DACK to go La at the next rising edge of 01
clock, which indicates to the WD2501 to start the
DMA Out cycle. This causes DROO to reset back to
HI state and to load the data byte to be transferred
onto the data-bus.
At the next rising edge of the 01 clock, MWE
(Memory Write Enable) is activated. This causes the
memory to input the addressed data byte.
At the following rising edge of the 01 clock, MWE
goes HI, latching the data into the memory. Also at
this time (low speed CPU clock), BUSRO signal gets
deactivated. When high speed CPU clock is used,
BUSRO is deactivated after an additional 01 clock
cycle.
At the next rising edge of 01 clock, the BUSRO
signal is sampled by the CPU.
DACK goes HI half a 01 clock cycle after MWE
goes HI. This ends the DMA Out cycle by the
WD2501 setting its data-lines in high impedance
state and the address-lines (AO-A15) to logical HI
state (ADRV bit set).
After CPU has sampled and detected BUSRO being
deactivated, it resets BUSAK to HI at the next falling
edge of the CPU clock.
At the next rising edge of the CPU clock, the CPU
again controls the bus.
150
TABLE 1
SIGNAL NAMES FOR THE HARDWARE INTERFACE (See Note)
NAME
RECEIVE
SYMBOL
FUNCTION
RCV
When activated (LO), sets the direction of the
data bus transceivers from WD2501 towards the
CPU bus. This is done only during CPU Read or
DMA Out cycle.
DRM TRANSFER
When activated (LO), enables the output of the
address bus latches. This is done during a DMA
In/Out Gycle.
DMA MEMORY OUTPUT ENABLE
Is activated during a DMA In cycle. Generates
the MOE signal and latches the DMA In addresses.
MEMORY OUTPUT ENABLE
Is activated during a DMA In or a CPU Read
cycle. Enables the memory outputs. Is to be
connected to the OE pin of the memory circuits.
MEMORY WRITE ENABLE
Is activated during a DMA Out or a CPU Write
Cycle. Enables the memory write function. Is to
be connected to the WE input of the memory
circuits.
MEMORY READIWRITE
MRW
Is activated during a DMA In/Out function or a
Memory ReadIWrite cycle by the CPU. Enables
the output of the Memory Address decoder.
DMA OUT
DMAOUT
Is activated during a DMA Out function.
DMAIN
DMAIN
Is activated during a DMA In function.
INTERNAL LOOP
ILOOP
Is activated during an internal loop-back test.
Keeps the RTS signal to the modemJ.!Loff
condition and logically connects RTS to CTS .
BUS ACKNOWLEDGE 1
BUSAK1
When active, indicates that the CPU has
switched bus control over to the WD2501.
Compared to BUSAK signal, this is delayed
one 01 clock cycle when going LO to allow a
time window of at least 500 ns before DACK
becomes activated.
BUS REQUEST 1
When active, requests the CPU via BUSRQ2
and BUSRQ (low speed CPU clock) to switch
control over to the WD2501.
BUS REQUEST 2
BUSRQ2
BUS REQUEST A
BUSRQA
Same function as BUSRQ1 , except that
BUSRQ2 is delayed one 01 cycle when going
HI. The delay allows a time window of at least
500 ns between DACK being active and a CPU
ReadIWrite function.
Same function as -=B~U:=S-=R-::::Q-=2 , except is delayed
an additional 01 cycle when going HI. This delay
allows the necessary 500 ns time window
between DACK being active and a CPU
ReadIWrite function when an high speed CPU
clock is used. This is then directly driving the
BUSRQ signal.
151
:ec
I\)
en
....
....
o
N
....en
TABLE 1 (Continued)
SIGNAL NAMES FOR THE HARDWARE INTERFACE (See Note)
NAME
SYMBOL
FUNCTION
CLOCK
ClK
Clock used for internal timing of WD2501. Is
synchronous with 01 clock with the exception
that when the CPU is performing a read function, ClK signal will not go to lO state. This
function avoids an internal up-date of a status
register while the CPU is reading this same
register.
01
01
01A
01A
+ 5 RESISTIVE
+5R
Clock used for timing of this hardware interface. The 01 frequency is not allowed to be
hiaher than the ClK max. frequency of the
WD2501. When a low speed CPU·clock is used,
01 signal is connected directly to the CPU clock
(0). When an high speed CPU clock is used, this
is connected to the 01A Signal.
Clock Signal with half the CPU clock frequency.
This is driving the 01 clock when an high speed
CPU clock is used. Toggles only during DMA
In/Out cycles.
+ 5V through a resistor.
NOTE: Signals described in this paragraph are Signals generated by this circuitry only. Other Signals are
described in either the WD2501 device specification or in the Z80 CPU data sheets.
COMPUTER
COMPUTER
INTERFACE
~
i-'-+
WD2501
~
LINE
DRIVERS
RECEIVERS
_----- ----------')
\.......
y
FIGURE 3
Figure 2. DTE/DCE STATION BLOCK DIAGRAM
152
MODEM
~
TO/FROM
REMOTE
STATION
r------CE
SA
OR01
OROl
DRao
DRCO
RTS
A'N
B OTR
BUSRQ
245
BliSAi
I
BUSRQ2
BUSRQl
, - - - - - - - - - 1 , - - - - - - - - - - ---------,
VCC
VSS
:::c
"T1
I
BUSAKl
All
ill
Ms
C
I
I
1
A14
:::c
I
I
1
1_ _ -
~
l>
I
1
BE
74LS
373
MRW
DMA
1/0
I
6SR
AS
C11
-a.
MREQ
;:;;WE
I
2511
I\)
I
I
A'
I
I
DACK
I
74LS
I
aUSAKl
~:~~=i)
I
I
RTS
B TD
i'i2
Do
~
I
:
BO
Dl
I
~
ACV
---------1
,
'I
01
CI
-------- -,
ClK
1
I
I
II
1'----------1-----'
01AINOTE)
BUSRQA (NOTE)
NOTE
_ _ __
Connect 0 to 01 and BUSRQ2 to BUSRQ if following conditions
are true:
1. WD2501/2511 ClK max. frequency ~ CPU frequency.
2. CPU frequency.;;;; 2.5 MHz.
If above conditions are not true, connect 01A to 01 and
BUSRQA to BUSRQ.
_______ ~
+""1"2V'GND
--+12
~ ~S~/~os~aM
=e
c
N
en
o.....
N
en
.....
CPUO
(NOTE 1)
01
(NOTE 1)
ORQ1
.....
BUSRQ
--,
I
- - - - - - - - - - - - - - - - - - - - -_ _ _ _... _ _ _ _ _ _ J
I
(NOTE 1)
]__________________________-''- J
BUSAK
DACK
t
T
AO-A15 - (W02501/2511).
TOAH
I
~
VALID
"
C - _ _ _ _ _ _ _ _ _-(
~_ _ _
_ _ _ _.....,~
~
I
~TOA1
(NOTE 3)
(~------V-A-L-ID------...II : ; - - - -
OALO-OAL7
(W02501/2511)
MOE
I
---.j
j+-
DA0.:'1
(NOTE 1)
-+-I J----------------------;1
MEMORY OUTPUT
I
ENABLE
_I--~-----'___
_ _ ACCESS
_ _ _TIME
_ _ _ _ _~I_J
(NOTE 1)
NOTE:
1_ These dashed lines show the respective signals when a fast
CPU 0 clock is used. Solid lines show same signals for a
slow CPU 0 clock (CPU 0 = 01).
2. Propagation delay is omitted in this diagram unless timing
symbol is shown.
3. Data would become non-valid after the address becomes
non-valid if address latches were not used.
Figure 4. DMA IN TIMING
01
(NOTE 1)
ORao - - ,_______________~~I
.
TOO
~~
BUSRQ
1 ________________________'- _____ l
(NOTE 1)
......___________________________.1_ j
BUSAK
_ H __
TOAO
AO-A15
(W02501/2511)
(NOTE 1)
--ll-~----------'I
-~I
---+i J.-= TOAH
I+--
:-i'-~-~~~~~=_=:=:~~~_:_.~-:-«======~Q£=====::::)!r~=:..:::..:=-:=--=:..=:..:=.
c:
.~ _
VALID
.-
---i
hOA1
TRO-+\
OALO-OAL7
<~
~
VALID
NOTE:
1. These dashed lines show the respective signals when a fast
CPU 0 clock is used. Solid lines show same signals for a
slow CPU 0 clock (CPU 0
01).
2. Propagation delay is omitted in this diagram unless timing
symbol is shown.
=
Figure 5. DMA OUT TIMING
154
f..-TOMW
)
3.3 SERIAL INTERFACE
The receiver and transmitter sUb-systems are
completely independent of each other, the CPU
Read/Write functions and the DMA In/Out functions.
The serial data is synchronized by the externally
su2.Qlied TC clock and RC clock. The falling edge
of TC ~erates new transmitted data and the rising
edge of RC is used to sample the received data.
After initialization and before the first frame is sent,
the TD output sends Idles (continuous 1s).
After the first frame is sent or the ACTIVE/""PA"""'S="S"""'I"""V=E
bit is set, continuous flags are sent in between
frames.
For detailed information on what type of frames are
sent for certain conditions, see the WD2501 or
WD2511 specifications.
4.0 SOFTWARE
Initialization of the WD2501 and I-field data
processing (level 3) is accomplished by user written
software. This software need not be realtime, since
the WD2501 responds to link exceptions and
overhead functions on its own.
Configuring the WD2501 to certain test functions,
modes, timer values, location of initial memory
pointers, chain buffer lengths and link level addresses is performed via the sixteen I/O registers.
All buffer management support, buffer chaining and
free/busy flags, occur in user memory. Here two lookup tables (TLOOKIRLOOK), located in the user
memory, contain pointers/counters for up to eight
outstanding transmit/receive packets. The WD2501
contains only one address pointer, which is the
starting address of Segment #0 in the TLOOK table.
Segment #0 in the RLOOK table always begins
40(Hex) bytes after TLOOK, Segment #0, byte #0. See
section "Memory Access Scheme" in the WD2501
specifications.
Link monitoring is done by use of the I/O registers
and the memory buffers. The WD2501 indicates to
the system CPU that a certain event has occured by
setting a bit in status register 1 and setting the interrupt flag. This indicates whether a packet has been
received, a transmitted packet has been acknowledged, a non-recoverable error condition or some
other condition needs the attention of the CPU.
In this section, a flow-chart is given to show the user
how to program the WD2501. For more details refer
to the data sheets.
The flow for programming/monitoring the WD2501
for transmitting or receiving a packet(s) or for a loopback test is shown in the flowchart below. The flow
starts at START1 if a power-up was just done and/or if
no data communication environment programming
(initialization) has been done.
If initialization is complete, the flow starts at START2
when the WD2501 is to be enabled to receive a
packet(s).
If a packet/s is to be transmitted and initialization is
complete, the flow starts at START3.
155
WD2501/2511 PROGRAMMING FLOWCHART
IN ITIALIZAnON
START1
MR
MOMENTARILY ~ 10MS
RESET WD25011
2511
PROGRAM THE
WD2501/2511,
FOR THE USER'S
ENVIRONMENT
PROGRAM 1/0
REG. 1,8,9,
A AND B.
YES
YES
SEE PARA·
GRAPH
"INTERNAL
LOOP·BACK
TEST"
NO
SET RTS OFF TO
MODEM.
ENABLE CTS
INPUT
(DCE)
(DTE)
RESET RECEIVE
DATA BUFFERS
XMIT
COMMANDI
RESPONSE
ADDRESS
SET REG. E
SET REG. F
= 01
= 03
SET REG. E
SET REG. F
= 03
= 01
SET
REG. E = REG. F
156
:ec
I\)
CJ'1
ENABLE RECEPTION
OF PACKET(S)
9
START2
II
NO
RLOOK
PROGRAM THE
LOOK·UP TABLES
FOR THE RECEIVE
DATA BUFFERS
REC RDY AND
RSADR
NO
SET CONTROL
BITS
COMPUTER DOING
OTHER TASKS
SET ACTIVE AND
RECR BIT
WAIT
157
o
.....
i\5
CJ'1
.....
.....
START
TRANsMr'i'i'iNGPACKET(S)
(DATA IS ALREADY LOCATED
IN THE TRANSMIT DATA
BUFFER(S))
LOAD DATA INTO
THE TRANSMIT
DATA BUFFERS
START3
6
TLOOK
NO
PROGRAM THE
LOOK·UP TABLES
FOR THE TRANSMIT
DATA BUFFERS
BRDY, TSADR AND
TCNT
YES
LINK UP?
SET CONTROL
BITS
SET SEND BIT
COMPUTER
DOING OTHER
TASKS
WAIT
158
SET ACTIVE,
LOOP·TEST AND
RECR BIT
~
C
N
C1I
o
.....
CHAINING TRANSMIT
DATA SEGMENTS
N
C1I
.....
.....
CHAIN
LIMIT
=
PROGRAM THE
AMOUNT OF CHAIN
SEGMENTS
(REG. C, UPPER 4 BITS)
REG. C
Y~(HEX)
Y
NUMBER OF CHAIN
SEGMENTS PLUS ONE
PROGRAM THE
CHAIN· BUFFER
SIZE
(REG. C, LOWER 4 BITS)
REG. C = Yr(HEX)
BUFFER SIZE = r:
64 x (1 + ~) BYTES
=
YES
NO
YES
XFR ADR
SET ALL THE
TRANSMIT XFR
ADR POINTERS
159
INTERRUPT
==
C
I\)
(J1
-..........
0
.....
I \)
READ SRI
(REG. 3)
READ
STATUS
(J1
YES
NO
THE PACKET HAS BEEN RECEIVED
ERROR-FREE AND IN CORRECT
SEQUENCE. THE I-FIELD
DATA HAS BEEN PLACED IN
THE USER'S MEMORY
RESET
RECR BIT
YES
NO
END
READ ERRORREGISTER
(REG. 5)
NO
CHAINING
RECEIVE
DATA
SEGMENTS
ESTABLISH BY
CODING THE ERRORREGISTER (REG. 5), IF
ANY ACTION IS NEEDED
C__
EN_D____
)
160
A PREVIOUSLY TRANSMITTED
BLOCK(S) HAS BEEN
ACKNOWLEDGED BY THE
REMOTE STATION
CHAINING RECEIVE
Q..ATA SEGM~NT§'
YES
NO
SET RECEIVE
XFR ADR POINTER
IN SEGMENT #0
NO
YES
READ REG. 6 TO
ESTABLISH WHICH
CHAIN SEGMENT IS
CURRENTLY
BEING LOADED
LOAD XFR ADR
POINTER INTO
CURREN; SEGMENT
(COMPUTER DOING
OTHER TASK)
C
WAIT
)
"'------
161
8
CHECK RESULT OF
LOOp·BACK T EST
(DATA TRANSFER CO MPLETED)
CHECK
1/0 REGISTERS
VERIFY CORRECT
INDICATIONS OF
THE 1/0 REGISTERS
CHECK
TLOOK SEGMENTS
VERIFY TRANSMITTER
LOOK·UP TABLES
ARE CORRECT
CHECK
RLOOK SEGMENTS
VERIFY RECEIVER
LOOK·UP TABLES
ARE CORRECT
VERIFY CORRECT
DATA
VERIFY RECEIVED
DATA IS CORRECT
END
162
=
REG. 1
00/10
REG. 2 = NN (UPPER 4
BITS
LOWER 4 BITS)
REG. 3/BITS 3·1
REG. 2/BIT 3·1
=
=
ACK'ED = 1
BRDY
0
=
FRCML = 1
REC ROY
0
RCNT = TCNT
=
CONTENT OF TRANSMIT
DATA BUFFERS
CONTENT OF RECEIVE
DATA BUFFERS
=
4.1 INTERNAL LOOp·BACK TEST (Example 1)
Chaining is used in this example. The 1024 bytes are
divided into 256 byte chain segments. Five segments
are needed for this operation with 254 bytes of I-field
data and two XFR ADR bytes per segment in the first
four chain-segments. The rest of the I-field data (8
bytes) are located in the fifth chain-segment.
The loop-back test feature is an internal programmable loop-back of data, enabling the user to make
an almost complete test of the WD2501. It allows
d~ag~ostic te~ting of the WD2501 and the interfacing
?lr~Ultry. In this mode, transmitted data to the TD pin
IS Internally routed to the received data input circuitry, thus allowing this WD2501 to set-up a link,
send a number of packets to itself and then reset the
link.
Programming:
= = number of CHAI N segments - 1
= = (number of bytes per segment divided
CHAI N
4
LIMIT
3
by 64) -1
The RC clock is internally connected to TC clock.
CTS input however, must be connected externally to
GND or the RTS output.
For buffer management programming, see memory
access scheme in Figure 7.
XMIT Command Address and XMIT Response Address (REG. E and F) must be the same value.
The loop-back test allows the verifying of proper
operation of practically all the various functions of
the WD2501. The features tested here, the addresses
and values of the variables chosen are only used as
examples and are as follows:
In some applications, it is necessary to keep the
RTS signal to the modem in the Off condition during
internal loop-back test. Also, to accomplish the most
complete test, RTS output should be connected to
CTS input externally (not done internally). Figure 6
shows one example of how to implement these two
functions. The ILOOP signal is connected directly to
a Pia output.
TLOOK segments starting address = 0800H
Transmit Data buffer no.O starting address = 1000H
Received Data buffer no.O starting address = 1800H
Number of packets transferred = 1
Number of I-field bytes per packet = 1024
Number of residual bits = 0
T1
101 H
N2 = 20H
In the loop-back test example shown in this section,
the logic in Figure 6 is used and contains the
Z80 CPU, programmable 1/0 (Pia) etc., as shown in
Figure 3.
=
+5
DRIVER
WD2501/
2511
r---------------------~ A
RECEIVER
PIO/A1-ILOOP
Figure 6. LOGIC FOR INTERNAL LOOP·BACK TEST
163
=e
C
TRANSMITTER
CHAINSEGMENT
I\)
en
0
#0
#2
#1
~
1300
1180
N
en
~
~
DATA
XFR ADR
#0
. TLOOK 0800
/
0
XFR ADR
#1
c:
1
2
1480
3
4
DATA
TRANSMIT
DATA BUFFERS
/
DATA
XFR ADR
#2
#4
+-------1#3 / 1 6 0 0 •
DATA
DATA
5
XFR ADR
#3
6
7
RLOOK 0840
0
1
2
3
4
5
~
RECEIVER
CHAIN
SEGMENT
#0
DATA
6
7
0880
#1
#2
1980
XFR ADR
#0
/
1 BOO
DATA
XFR ADR
#1
/
DATA
XFR ADR
#2
ERROR
COUNTERS
#4
#3
1EOO
DATA
RECEIVE
DATA BUFFERS
XFR ADR
#3
/
Figure 7. MEMORY ACCESS SCHEME FOR LOOp·BACK TEST
(Example 1)
s
164
DATA
APPENDIX A
GLOSSARY OF DATA COMMUNICATIONS TERMS
The following is a list of industry-accepted data communications terms that are applicable to this specification.
ABM
Asynchronous Balanced Mode
ADCCP
Advanced Data Communications Control Procedure (ANSI BSR X3.66)
ANSI
American National Standards Institute
ARM
Asynchronous Response Mode
CCITT
International Consultative Committee for Telegraphy and Telephony
CMDR
Command Reject. AU-Frame
DCE
Data Circuit Termination Equipment (the network side of the DTE/DCE link)
DISC
Disconnect. AU-Frame
DTE
Data Terminal Equipment
DM
Disconnect Mode. AU-Frame (LAPB, only)
ECMA
European Computer Manufacturers Association
FCS
Frame Check Sequence
FDX
Full Duplex (also called "two way simultaneous")
FRAME
Basic Se,ial Block of Bit-Oriented Data. Includes leading and trailing flags, address field, control
field, FCS field, and an optional information field.
FRMR
Frame Reject. AU-Frame (LAPB, only)
HDLC
High-Level Data Link Control (ISO 3309)
HDX
Half Duplex (also called "two way alternate")
HOST
Another name for a DTE
I-Frame
Information Frame. Control field bit 0 is O. In X.25 an I-frame is a packet.
ISO
International Standards Organization
LINK
The logical and physical connection between two data terminals
LAP
Link Access Procedure
LAPB
Link Access Procedure Balanced
N2
Maximum number of retransmissions of a frame. (Also called retransmission count variable.)
NODE
Another name for a DCE.
N(R)
Sequence number of next frame expected to be received.
N(S\
Sequence number of current frame being transmitted.
OCTET
An 8-bit byte
P(R)
Receive Data, Packet count of next packet expected to be received
P(S)
Send Data, Packet count of current packet being transmitted
PACKET
An I-Frame in X.25
PAD
Packet Assembly/Disassembly
REJ*
Reject. An S-Frame
RNR*
Receiver Not Ready. An S-Frame
RR*
Receiver Ready. An S-Frame
S-Frame
Supervisory Frame. Control field bit 0
SARM
Set Asynchronous Response Mode. (LAP, only)
=1 and bit 1 =0
SABM
Set Asynchronous Balanced Mode. (LAPB, only)
SDLC
Synchronous Data Link Control (IBM document GA27-3093)
SNAP
Standard Network Access Protocol (Trans-Canada)
165
T1
A Primary Timer for a delay in waiting for a response to a fra~e
U-Frame
Unnumbered Frame. Control Field bit 0
UA
Unnumbered Acknowledge. AU-Frame
X.25
X.3, X.28, X.29
Recommendations by CCITT involving PAD facilities
ACS
Advanced Communications Service (AT&1)
=1 and bit 1 =1
Recommendation by CCITT on Packet Switching Networks
*There are also RR, RNR, and REJ packets which are not the same as the S-frame RR, RNR and REJ discussed
in this document.
166
APPENDIX B
3_0 Link Down
In LAP, if a link is down, a station may respond only to
received SARM's or DISC's. The response is a UA.
Any other received command is disregarded.
In LAPB, a down station may respond to a SABM or
DISC with a UA. When receiving any other command
frame with the P-bit set to 1, the DCE will transmit a
DM response with the F bit set to 1. This is an advantage in a down station which does not initiate link
set-up. If the other station "thinks" the link is up, it
will eventually send a packet with P= 1. When this
happens, it is informed, by the DM response, that the
link is down.
THE DIFFERENCE BETWEEN LAP AND LAPB
In March 1976, the CCITT adopted Recommendation
X.25 as an interface standard for public packetswitching networks. The link level procedure adopted
was called Link Access Procedure (LAP) and used
the HDLC Asynchronous Response Mode (ARM).
However, LAP was not fully in conformity with HDLC
(ADCCP is essentially the same. See ANSI X3.66,
1979). Therefore, in 1977, when Provisional Recommendation X.25 was adopted, a procedure called
LAPB was added. LAPB is Link Access ProcedureBalanced and operates under the HDLC Asynchronous Balanced Mode (ABM). Unfortunately, the
1977 LAPB lacked good symmetry between the DTE
and DCE, and was unworkable.
4_0 Supervisory Commands
In LAP, S-frames are responses, only.
In LAPB, an S-frame may be a command or response.
Suppose two stations are operating over a set-up link
(station A and station B). Suppose B sends an RNR.
In LAP, the only way that A can test B to see if B is
ready again is to send the last unacknowledged
I-frame with P = 1 at T1 intervals. This forces B to
reply with either an RNR or RR (F = 1). An I-frame is
used here as a request for status, and it could be a
long I-frame.
In the April 1979 CCITT meeting, the LAPB was
greatly enhanced, especially in the DTE/DCE symmetry. This enhanced version was approved in the
February 1980 Plenary meeting of the CCITT. We now
have a good, workable LAPB standard.
The LAP, because of not fully complying with HDLC,
has subtle problems. LAPB is a superior procedure.
The usage of LAP will eventually be replaced with
LAPB.
LAP and LAPB are different only in the link set-up,
disconnect, reset and receiver-not-ready procedures.
In LAPB, station A could send an RR command with
P = 1 at T1 intervals. B would respond with either
an RNR or RR (F = 1), and this procedure is more
efficient.
1.0 Link Set-Up
In LAP, a link is set-up when both ends exchange a
SARM and UA. In LAPB, only one end will send a
SABM, and when the other end sends a UA, the link
is up.
5_0 CMDRlFRMR
Suppose a command or response is received errorfree (FCS good), but there is an invalid condition. This
could be an acknowledgment to a packet never sent,
an unrecognized command or response, an I-field
where one is not allowed, etc.
2_0 Link Reset
A link, which is up, may be reset.
In LAP, a link may be reset in one I-frame direction by
sending a SARM. When the other end acknowledges
the SARM with a UA, the end that send the SARM
clears its send sequence number. However, I-frames
coming from the other direction are not reset. This
could be a problem. Suppose a link is up, but one end
momentari Iy loses power. When that end tries to setup the link by sending a SARM, the other end sends a
UA, but "thinks" the SARM was a link reset. Thus, a
SARM is never returned. (The WD2501 gets around
this by sending a DISC before trying to bring a link
up.)
In LAPB, a link reset SABM resets the link in both
directions. The ambiguity between a reset command
and a link set-up command is much less than for LAP.
(It is still a good practice to send a DISC before trying
to bring a link up in LAPB. This will insure that Level 3
software is fully aware of a disconnect situation, as
opposed to a reset.)
In LAP, received invalid commands may be rejected
except for packets with an invalid N(R). The receiving
station would send a command reject (CMDR) along
with the rejecting cause and its current V(R) and V(S)
counts. These counts allow for re-initialization at a
higher level to prevent duplicate packet transmission
(Le., sending an already acknowledged packet).
However, invalid responses or packets with an invalid
N(R) may not be rejected. Only a link resetting SARM
may be sent. Thus, the reason for the reject is not
communicated to the other end. Even worse,
duplicate packets could be exchanged since the
V(R), V(S) counts are not transferred.
In LAPB, all invalid responses and commands are
rejected with a frame reject (FRMR). An FRMR is the
same as a CMDR except for one bit which tells
whether the rejected frame was a response or
command. Thus, the rejecting cause and V(R), V(S)
counts are communicated for both invalid commands and responses.
167
~
t3
I\)
en
o
"""'"
i\5
en
"""'"
"""'"
:e
LAP COMMANDS AND RESPONSES
(Bit 0 is transmitted first) Only the CMDR and I-frame contain I-fields
C
N
CJ1
o
.....
FRAME TYPE
COMMAND
I-FRAME
I-FRAME
i\5
CJ1
.....
.....
S-FRAME
RESPONSE
N(R)
P
N(S)
0
0
RR
N(R)
F
0 0 0
1
RNR
N(R)
F
o
1 0
1
NCR)
F
P
1 0 0
000
1 1 1
1
1
UA
0 1 0
0 1 1
P
F
0 0 1
0 0 1
1
1
CMDR
1 0 0
F
0 1 1
1
REJ
SARM
U-FRAME
CONTROL FIELD
81T#
321
765
4
DISC
RECEIVER
READY
RECEIVER
NOT
READY
REJECT
SET ASYNCHRONOUS
RESPONSE
MODE
DISCONNECT
UNNUMBERED
ACKNOWLEDGE
COMMAND
REJECT
LAPB COMMANDS AND RESPONSES
FRAME TYPE
COMMAND
I-FRAME
I-FRAME
S-FRAME
U-FRAME
RESPONSE
CONTROL FIELD
81T#
321
765
4
N(R)
P
N(S)
0
0
RR
RR
N(R)
P/F
0 0 0
1
RNR
RNR
N(R)
P/F
0 1 0
1
REJ
SABM
REJ
N(R)
001
P/F
P
1 0 0
1 1 1
1
1
DM
0 1 0
0 0 0
P
F
0 0 1
1 1 1
1
1
UA
0 1 1
F
0
o
1
1
FRMR
1 0 0
F
0 1 1
1
DISC
Only the FRMR and I-frame contain I-fields
P Poll Bit
F = Final Bit
=
168
RECEIVER
READY
RECEIVER
NOT
READY
REJECT
SET ASYNCHRONOUS
BALANCED
MODE
DISCONNECT
DISCONNECT
MODE
UNNUMBERED
ACKNOWLEDGE
FRAME
REJECT
APPENDIX C
OPERATING THE WD2501 OR
MULTIPOINT CONFIGURATION
WD2511
IN
in each secondary, but unique for that secondary. The
primary would modify Registers E and F for each
session with a given secondary. Neither of the above
methods appears to have an advantage over the
other.
A
A typical multipoint consists of a primary station
controller connected to one, or more, secondary
controllers by means of a four wire connection as
shown in Figure 1. One wire pair carries serial data
from the primary for broadcast to all secondaries.
One wire pair carries serial data from all secondaries
to be received by the primary. Thus, the primary
communicates with secondaries, and secondaries
never communicate directly with one another. Also,
the primary can only "talk" to one secondary at a
time.
By way of example, suppose the second method is
chosen, and suppose there are five secondaries.
Register E and F for the five will be 1, 3, 5, 7, and 9.
Each secondary will be in an idle state with CRO bits
5 and 1 set (hex 22). The RTS pin will be off for the
secondaries. As soon as a secondary receives a DISC
with A field which matches Register F, RTS will be
asserted. If the A field does not match Register F, the
frame is discarded, and RTS remains off.
When the primary needs to communicate to #1,
Register E and F in the primary are set to 1. The
primary will set CRO bits 4 and 1 (hex 12). The primary
will initiate a link set-up procedure wih #1. After the
link is brought up with #1, there will be a link-up
interrupt with ERO = hex 21 in both the primary and
secondary. If, however, #1 is off-line, there will be no
link-up time-out from the WD2501/2511 for failure to
bring-up a link. The user must provide this time-out.
After the link is up, if a WD2511 is being used, the
user may wish to clear CRO bit 5 (does not need to do
so for the WD2501). For the WD2511, this is a half
duplex bit, and will become full duplex when the bit
is cleared.
ADCCP (Advanced Data Communication Control
Procedures, ANSI X3.66) specified three modes:
Normal Response Mode (NRM), Asynchronous
Response Mode (ARM), and Asynchronous Balanced
Mode (ABM). NRM is strictly an association between
a primary and one, or more, secondaries. Therefore,
N RM has been specifically designed for use with
multipoint, and is the best choice for multipoint.
ABM and ARM are not as well suited for multipoint as
NRM, but can none-the-Iess be used in multipoint.
The WD2501 is LAP which is an application of ARM.
The WD2511 is LAPB which is an application of ABM.
For multipoint, the primary will establish a link with
one secondary, and communicate I-frames with that
secondary. After this "session," the primary will
initiate link disconnect, and go on to another
secondary.
The control of the WD2501 and WD2511 is by means
of Registers E and F which control the command/response definitions for the A field. This may
be handled in one of two ways: First, make Register E
the same for all secondaries, and this value will be
used in Register F of the primary. Register F will be
unique for each secondary, and the primary will
modify Register E for each session with an individual
secondary. Second, Register E and F could be equal
To discontinue a session, the primary will set bit 0 in
CRO (hex 01). This will cause a DISC to be generated
to the secondary. The user may change Registers E
and F for the next second~fter waiting a few
mill iseconds (2 or 3) after the LI NK bit becomes set.
When the secondary receives the DISC, the
secondary will generate a disconnect interrupt (ERO
= hex 30), and transmit a UA.
SECONDARY
SECONDARY
#1
#3
PRIMARY
Figure 1. TYPICAL MULTIPOINT CONFIGURATION
169
SECONDARY
#N
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
170
Printed in U.S.A
WD2511 LSI circuit simplifies
packet-network connection
by Geary L. Leger,
Western Digital Corp., Newport Beach, Calif.
Technical articles_ _ _ _~------
LSI ready to make a mark
on packet-switching networks
New chip's link-control capabilities
ease connection to terminals: Part I
by Geary L. Leger,
Western Digital Corp., Newport Beach, Calif.
o Packet-switching networks are prime targets for the
application of large-scale-integrated circuit technology.
In fact, sometime during the first quarter of next year,
this useful and expanding approach to data communicaThis is the first oj two articles. It deals with the overall
characteristics oj packet-switching networks. Part 2, which
starts on page 95, describes an LSI chip being developed Jor
Level 2 control per the X. 25 protocolJor packet networks.
...
LEVEL 7
tions will have its first dedicated LSI circuit, one
designed to take advantage of LSI'S potential for lower
cost and greater reliability.
The circuit is the Micro Packet Interface chip, or
,uPAC, being developed by Western Digital. It will handle
Level 2 control of the link between a data terminal and a
network node as set forth in the X.25 protocol established by the Consultative Committee for International
Telephony and Telegraphy (CCITT). Because these
-----------~
PROCESS
CONTROL
...------------+
PRESENTATltltj
LEVEL 5
...-------------.
SESsiON
CONTl'laL
LEVEL 4
...-------------+
ENO·TO·END
CONTROL
LEVEL 6
PRESENTATrON
CONTROL
CONTROL
TRANSPORT
PEER-TO-PEER INTERFACES
LEVEL 3
...-------------.
LEVE L 2
...------------
LEVEL 1
.-------------.
NETWO.RJ<
CONTRal
t
LEVEL-TOLEVEL
INTERFACE
...
1. Layered architecture. Independence among system levels allows changes to be made to one level without disrupting the operation of
other levels; and adjacent level is affected only if the changes affect the interface to that level. Standards apply to peer-to-peer interfaces_
172
Recent efforts in packet switching
The security, survivability, and economic advantages of
packet-switching data-communications networks have not
gone unnoticed in either the military or the corporate
sectors. Though still in its infancy, this type of communication is growing rapidly.
According to Defense Advanced Research Project
Agency director Eugene H. Kopf, the latest military packet
effort aims to find the optimum architecture for a
command and control network of 5,000 to 10,000 small
packet radio relay terminals whose purpose would be to
insure survivable control over strategic weapons. The
network voice and data-packet radios would provide lineof-sight communications throughout the continental U. S.
after an attack.
The civilian sector has continued the development of
packet networks from their modest beginnings. In 1972,
Bolt Beranek & Newman Inc. founded Telenet, a public
packet-switching network taken over this year by General
Telephone & Electronics Corp. GTE Telenet Communications Corp., Vienna, Va., completed installation this month
of a packet-switching exchange in San Juan, Puerto Rico,
for ITT World Communications Inc. The new service allows
businesses and industrial organizations to link to the ITT
gateway and transmit and receive data over shared transmission lines 'to data terminals or computers on the U. S.
mainland.
Tymnet Inc., Cupertino, Calif., is the largest public packet-switching network in the U. S. It has so many customers
that it issues a 34-page directory describing 200 data
bases accessible through its network. Tymnet now serves
250 computers in the U. S.; it recently added New Zealand
networks are relatively new, familiarity with the Level 2
link control and other details of their operations is not
widespread. Yet the purpose of the ,uPAC is intelligible
only in the context of such an understanding.
To date, most data-communications systems use
circuit-switching techniques. A physical circuit is
assigned either permanently (a private, leased line) or
for the duration of the call (a dial-up line). But of a
given line's total available time, only a small percentage
is actually taken up by data transmission. A system for
dynamic allocation of the physical circuits, in contrast to
static circuit-switching allocation, requires the logic and
memory capabilities of computers.
Prior to the late 1960s, static circuit allocation was
more economical than using computers in a dynamic
allocation system. The low cost of today's minicomputers
and micFoprocessors and the dramatic drop in the cost of
memory, however, make dynamic allocation more
economically feasible in many cases. It is most suitable
in multipurpose applications-digital communications
systems linking various types of data terminals such as
facsimile machines, computerized data bases, interactive
keyboard printers, or cathode-ray-tube terminals.
Historically, communications systems have been
developed to satisfy one application at a time. The wide
variety of computers, terminals, and technologies has led
to the development of many incompatible networks. A
time-sharing network may connect many asynchronous
interactive keyboard printers on dial-in lines at 110 or
to its list of countries served, bringing the total to 26.
The Japanese have not been idle in adapting packet
technology to their needs. Nippon Telegraph and Telephone Public Corp. started work on its digital dataexchange system in 1971 and had installed packetnetwork equipment in seven cities by late 1978. This
commercial packet-switching network (called 050) is
expected to go into full service this year. 050 conforms
fully to Recommendation X.25 of the Consultative
Committee for International Telephony and Telegraphy.
The packet network industry has come a long way since
the first operational system (Arpanet) was installed by the
Defense Advanced Research Projects Agency in 1969. In
1976, the CCITT adopted X.25 as a standard three-level
protocol for interfacing terminals to public packet
networks-a major step for the industry. Even though it
has been criticized as being too complicated, X.25 has
stimulated interest in packet networks.
However, packet switching is not the answer to all data
and voice communications problems, as some have
claimed. Gino J. Coviello of the Defense Communications
Agency in Arlington, Va., concluded in a recent study that
the number of channels traversing a particular transmission link and the network topology and architecture have a
significant impact on the cost-effectiveness of a packetswitching network. Ray W. Sanders, president of Computer Transmission Corp., says, "Packet switching will take
its rightful place alongside circuit switching." A hybrid
approach combining features of both circuit and packet
switching "provides the best of all possible worlds,"
according to Sanders.
-Harvey J. Hindin
300 bits per second. A clustered CRT application such as
IBM's 3270 may operate synchronously at 1,200, 2,400,
or 4,800 b/s.
The incompatibility of different types of equipment
and the protocols they use for communicating greatly
reduces the reliability and efficiency of data communications as a whole. A single corporation may, for example,
use several incompatible networks.
Security and survivability
The technique of sending a digital data in short packets, rather than in a continuous stream, was first
suggested by Paul Baran of the Rand Corp. more than a
decade ago. The packets are transmitted between intermediate points in the network, called nodes, or DCEs, for
data-circuit-terminating equipment (see table).
This dynamic-allocation technique has two major
inherent advantages over circuit-switching methods. It
increases data security, since the message is broken up:
all the packets would have to be picked up and combined
by an intruder before he could use the data. And system
survivability and reliability are enhanced by the large
number of linked nodes. Alternate routes will get a
message through if some of. the nodes or links are
malfunctioning or destroyed. The security and survivability are of great interest to the military. The commercial sector is also developing this type of system (see
"Recent efforts in packet switching," above).
The problem of equipment and communication-proto-
173
col incompatibility is an international one, since data
communications is international. This question is
addressed at the global level by the CCITT (see "Setting
the standard," p. 93).
The difficulty of expanding, modifying, or upgrading
existing data-communications networks is another problem that is tackled by the new packet-switching systems.
Any communications system represents a large capital
investment, and down time can be disastrously expensive. A user cannot simply tear down an old network and
substitute a new one with the latest advances. New
terminals and technologies must be phased into the
existing structure without interrupting operation. This
calls for a degree of system flexibility.
PACKET-SWITCHING NETWORK TERMINOLOGY
ADCCP
Layered architecture
Packet-switching n'!tworks achieve this flexibility
through layered (;r multilevel) architecture [Electroni~s
May 24, 1979, p. Ill]. Several standards organizations
have been working on the specifics of this concept.
The importance of layered structure is easy to understand. Suppose Mr. Jones, an executive, wishes to talk to
Ms. Smith, another executive. Jones (level 4) tells his
secretary (level 3) to get Smith on the line. Jones'
secretary dials the number (level 2). An electromechanical switching mechanism connects the two phones (level
1). Smith's phone rings (level 2). The two secretaries
converse (level 3) and pass on the information that the
call is ready to their bosses. Smith and Jones now
communicate (level 4).
Jones was never concerned with the electromechanical
switching mechanism, nor with Smith's telephone'
number; he was primarily concerned with talking to
Smith (peer to peer) and secondarily with talking to his
secretary to get the call set up.
Multilevel communications systems are structured in a
similar fashion. The protocol standards are prepared for
connection in the peer-to-peer layer. Standards do not
define the interface between adjacent layers. This is
intentional: terminal manufacturers are thus left free to
design the adjacent-layer interface in their own way.
This enhances system flexibility. If a layer is changed or
upgraded, nonadjacent layers are not affected.
X.25 defines and standardizes three levels. There are
as many as four more definable levels (Fig. 1), but much
work remains to be done to standardize these higher
levels. Level 1 may be viewed as a data-exchange mechanism serving Level 2. Level 2 is a data-exchange mechanism serving Level 3, and so on.
Three standardized levels
Level 1 concerns itself with the link's physical interfaces. Level 2 deals with link control. It includes setting
up and disconnecting a link, the control of flow between
data generators and data receivers, and bit-oriented
frame structure. The JLPAC from Western Digital is
designed to perform the Level 2 functions. Level 3,
network control, includes the procedures for establishing
and disconnecting the virtual circuit and for controlling
the flow of data packets in the network.
In a packet network, the sender or receiver has a
terminal (commonly called DTE, for data-terminal equip-
Advanced Data-Communications Control Procedure
(ANSI X3,66)
ANSI
American National Standards Institute
ATOM
asynchronous time-division multiplexing
BOP
bit-oriented protocol
CCITT
Consultative Committee for International Telephony
and Telegraphy
DCE
data-circuit-terminating equipment (network node)
DTE
data-terminal equipment (user's terminal)
FCS
frame check sequence
HDLC
High-level Data-Link Control protocol (ISO 3309)
ISO
International Standards Organization
ITU
International Telecommunications Union
I frame
information frame, known as a packet under X,25
LAP
Link-Access Procedure (X,25)
LAPB
Link-Access Procedure, Balanced (X.25)
Link
control
X,25 Level 2 control for linking DTE and DCE,
including link initialization, establishment, and
disconnection, and control of data flow on the link
Network
control
X.25 Level 3 control of virtual circuits in network,
including circuit establishment, disconnection, and
reset, and the control of packet flow
N1
maximum number of bits in a packet
N2
maximum number of command retransmissions
PAD
Packet Assembly/Disassembly facility (defined in
CCITT recommendations X,3, X,28, and X,29)
Physical
interface
X,25 Level 1 specifications for the physical connection
of DTE and DCE, including electrical parameters
and transmission rate
S frame
supervisory frame
SDLC
Synchronous Data-Link Control protocol
T1
time minimum before retransmission of
unacknowledged command
U frame
unnumbered frame
X,25
CCITT recommendation for packet-switching network
protocols (others include X,3, X,28, and X.29)
ment) with a distinct address. Part of the gear at a
network node might also be called data-terminal equipment. The packets of data are transferred from node to
node and finally to the receiver's terminal.
When a node receives a packet, it stores the packet,
decides where and when to forward it on the basis of the
packet's destination and priority and the load conditions
of the network, and then does so. This store-and-forward
facility is the key to the network's ability to allocate
circuits dynamically. Packets going from terminal A to
terminal B in Fig. 2 could follow the node path
7-12-11-10,7-5-3-1-10, or any of a number of others.
Dynamic routing within the network is transparent to
the users at their terminals. The path data takes is called
a virtual circuit between A and B: the terminals communicate as if a dedicated circuit joined them. In order to
174
r - - - - - - VI RTUAL CIRCUIT (A TO B) - - - - - -__
IElETYPE'
WRfTl!R
CATHODERAY-TUBE
TERMINAL
NO.1
TERMINAL
EQUIPMENT t - - i - { )
A
CRT
TERMINAL
NO.2
2. Many possible paths. The user of a packet-switching network at his terminal sees no difference between the virtual circuit and an ordinary
phYSical link. Network control may send the data packets through a changing series of nodes as system traffic conditions change.
establish a virtual circuit, terminal A transmits a callrequest packet that includes the caller's address and the
address of terminal B, the destination. Terminal B
accepts the request by returning a call-accepted packet
to A, and the virtual circuit is set up.
Circuit sharing
Several simultaneously active virtual circuits can be
set up by interleaving packets. This asynchronous timedivision multiplexing (ATOM) exploits the fact that a
typical virtual circuit carries data for only a small
percentage of the time it is set up. It differs from other
time-division multiplexing schemes in that a dedicated
NODE
TERMINAL
COMMAND
SECONDARY
FUNCTION
PRIMARY
FUNCTION
RESPONSE
COMMAND
PRIMARY
FUNCTION
SECONDARY
FUNCTION
RESPONSE
3. Addressable functions. A terminal or node has a primary function that sends commands and receives responses. Its secondary
function, which has a different address, responds to received
commands. Arrows represent system logic, not phYSical wires.
175
time slot is not provided for each virtual circuit being
multiplexed.
In the multilevel packet-switching architecture, Level
2 (also known as the link level or the frame level)
involves the point of contact between the subscriber's
terminal and the network node it is linked to directly.
Each station, be it terminal or node, has two logical
functions needed for addressing and signal implementation, called primary and secondary (Fig. 3). The primary
function transmits commands and receives responses; the
secondary function does the reverse- it receives commands and transmits responses.
The structure of the data frames used for this communication is common to all bit-oriented protocols (BOPS)High-level Data-Link Control (HOLC), the essentially
similar Advanced Data-Communication Control Procedures (AOCCP), and the Synchronous Data-Link Control
(SOLC) protocol worked out by IBM [Electronics, Jan. 18,
1979, p. 137]. The Level 2 protocol defined by X.25 is an
outgrowth of HOLC.
The frame is simply a block of serial data exchanged
between two terminals or a terminal and a node. It
consists of a flag, an address field (or A field), a control
field (or C field), an information field (or I field), a
frame-check sequence (FCS), and another flag. Depending on the frame type, the information field mayor may
not be included.
There is a flag at either end of a frame; a single flag
may close one frame and open the next. Data transparency is provided within the frame by the transmitting
station: a logic 0 is inserted after all sequences of 5
contiguous logic 1 bits, so that no transmitted data is
inadvertently read as a flag, which has the binary form
Setting the standard
International interface standards are vital to the development and growth of packet-switching networks. Standards
lead to lower costs for equipment bought by network
users, since this equipment can be manufactured in much
larger quantities. The user also benefits from the interchangeability of gear from different vendors. Manufacturers reap the rewards of a global market rather than a local
one, and network organization is made vastly easier.
A number of U. S. and international standards organizations are working together to set up interface rules. The
International Telecommunications Union (ITU), formed in
1865, operates under the auspices of the United Nations.
Under the ITU is the Consultative Committee for International Telegraphy and Telegraphy (CCITT), which is
primarily an organization of carriers.
Study Group VII is a CCITT organization that handles
i
public data networks. SG VII is responsible for publishing a
number of standards or recommendations for packetswitching networks. The best known of these is Recommendation X.25.
The International Standards Organization (ISO), which is
composed of representatives from the manufacturing and
user community, works closely with the CCITT; the ISO
also has a group under its wing with responsibility for
public data networks.
In the U. S., the American National Standards Institute
(ANSI) is a clearinghouse that coordinates activity for
voluntary standards. Its X3S37 committee, which has the
responsibility for public data networks, does liaison work
as well as coordination. This committee represents a cross
section of U. S. industry: manufacturers, users, and
carriers. It offers inputs to both the ISO and the CCITT.
· I - - - - - - - - - - - - - - - - - - I N F O R M A T I O N FRAME (PACKET)
-----------------+1_1
Ioofl.f------INFORMATION FIELD (PACKET DATA)
FLAG
1-0_1------\
ADDRESS
PACKET
CONTROL
INFORMATION
CONTROL
LEVEL 2 - - - - - - ;•.-t-\....-
FLAG
ADDRESS
UNNUMBERED FRAME (LEVEL 2)
CONTROL
I·FIELD
f--------SUPERVISORy FRAME (LEVEL2)
ADDRESS
CONTROL
FCS
FLAG
SOFTWARE----II.-r\~--- LEVEL 2 - - - - l
-------~.I
FLAG
FCS
1. .
FLAG
FRAME
CHECK
SEOU ENCE
(FCS)
USER DATA
LEVEL 3 -••....
\ c - - - - APPLICATION
1-01.1----------
---~_I
-----.-t.1
FLAG
4. Standard frames. Three types of data frames may be sent over a packet network. All data except the user data in the information field of
ali information frame is system overhead required for synchronization, data checking, verification, and bookkeeping functions.
01111110. The receiving station automatically deletes
the inserted Os from the data.
The frame-check sequence is the last 16 bits before the
closing flag. They are produced by a calculation that
checks all data between the opening flag and the first bit
of the FCS. The logic Os inserted for data transparency
are not checked.
A frame may be one of three types (Fig. 4): a supervisory frame (or S frame), an unnumbered frame (or U
frame), or an information frame (or I frame).
Level 2 control does not involve itself with the data
within the information field of an information frame. It
simply encloses the packet data in an HDLC frame and
sends it out onto the network.
Supervisory frames are used to perform supervisory
control of a link, such as acknowledging packets,
requesting retransmission of packets, and requesting
temporary suspension of transmission. Unnumbered
frames are used to set up, disconnect, and reset links.
The Level 2 protocol may take one of two forms:
Link-Access Procedure (LAP) and Link-Access Procedure, Balanced (LAPB). When it was originally written in
1976, Recommendation X.25 contained LAP only. LAPB
has been added since that time, offering some improve-
176
)(28
\
\
CATHOOE·RAY·TUBE
TERMINAL
\
",').'0
X.3 \
K29 I
I
J
i-').~
TERMINAL
CONCENTRATOR
(PACKET
ASSEMBLY!
OISASSEMBL Y
FACILITY)
X.25
CENTRAL
PROCESSING
UNIT
PUBLIC
PACKET
NETWORK
I
X.75
",').S
CPU
CRT TERMINAL
PUBLIC
PACKET
NETWORK
5. Multiterminal connection. A Packet Assembly/Dissassembly
(PAD) facility allows various types of interactive terminals to communicate with each other using the interface standards indicated. PAD
equipment may belong to either the user or the network.
ments. Some changes in frame types were made, but the
primary differences between LAP and LAPB are in the
functions that set up, disconnect, and reset links. (Two
models of the J.l,PAC, the WD 2501 and the WD 2511, are
geared to the LAP and the LAPB, respectively.)
There are four system parameters defined by the X.25
Level 2 protocol: T1, N2, N I, and k. T I is the time limit
set for the primary timer; when TI runs out, an unacknowledged command may be retransmitted. N2 is the
limit set for a counter that is incremented each time a
command is retransmitted because time TI ran out
without its being acknowledged. N I is the maximum
number of bits in a packet; it depends on the maximum
length of the information field. And k is the maximum
number of sequential packets that a terminal or node
may have outstanding (transmitted but unacknowledged) at any given time. In the J.l,PAC, TI, N2, and Nl
are programmable. The number k can never exceed
seven under X.25, and it is fixed at seven in the J.l,PAC.
Multiplexing terminals
Since each user of the packet network typically has
many different types of data generators and receivers,
multiplexers must connect the network to the existing
equipment. This multiplexer has been defined by the
CCITT as the Packet Assembly/Disassembly (PAD)
circuit (Fig. 5). The PAD is specifically for use with
asynchronous terminals; it combines or separates the
multiple signals that are sent to or received from the
network.
CCITT protocol standards X.3, X.28, and X.29 are
used together to define a PAD interface. A PAD facility
may be viewed as a terminal concentrator that connects
several asynchronous terminals to a single X.25 link. The
PAD circuit is sometimes called an interactive-terminal
interface because in practice most terminals connected
to PAD interfaces require human interaction via
keyboards and CRT displays or printing equipment.
CPU
When a PAD interface is used between the packet
network and the terminals, two stations that are incompatible by themselves can communicate. They need only
be able to talk to the PAD. The J.l,PAC chips will allow
them to do this. Another advantage of this approach is
that new types of equipment added at a terminal are
transparent to the network.
On the other hand, changes and improvements within
the packet network are transparent to the user. These
improvements could include increasing node-to-node
communication speed, increasing the number of nodes,
and changing node-to-node connections to fiber optics.
Variations on the theme
Many packet systems are available; they vary according to the network organization. Several networks, such
as Montreal-based Bell Canada's Datapac, offer (in
addition to the standard virtual circuit) a permanent
virtual circuit that requires no call for link establishment
anrl is continually available.
Another possible service, Datagram, when made available, will not require the initial establishment of a virtual
circuit. In this approach a packet is merely put out on
the line- typically by users of so-called transactionbased networks. There is no call procedure, and duration
of connection is not of concern for billing purposes.
Users may, for example, pay a flat fee. Short, independent data bursts will ultimately work their way through
the network to their destinations.
A closed user group, available from Datapac and
others, is like a private network. Users in a group,
actually connected to a public network, can communicate with one another, but access is barred to and from
all other users of the network. AT&T'S proposed
Advanced Communications Service includes this feature;
the company calls it a virtual subnetwork.
0
177
178
WD2511 LSI circuit simplifies
packet-network connection
48-pin chip replaces entire board
and thousands of lines of software
by Geary L. Leger,
Western Digital Corp.. Newport Beach. Calif.
D Packet-switching data-communications technology
can now claim its first dedicated large-scale integrated
circuit. Called the Micro Packet Network Interface chip,
or ,uPAC for short, it is a complete X.25 Level 2 controller with on-chip bidirectional direct-memory-access
facilities. This n-channel silicon-gate MOS chip in a
48-pin package replaces a board full of electronics.
The ,uPAC goes way beyond the functions performed
by the bit-oriented-protocol (BOP) control chips currently in widespread use. It includes the circuitry of a BOP
chip. But it handles many other operations, eliminating
the need for separate OMA circuits and associated
address latches, timing chips, and the system software
(more than 1,000 lines of code) required until now to
perform Level 2 control of the link between a data
terminal and a node of a packet-switching network. It
has an II-K read-only memory and the equivalent of
three microprocessors: one to handle data-transmission
operations, another for dealing with received data, and a
third central processor to coordinate all chip functions.
Sample quantities of the controller will be available from
SYNCHRONOUS OATA·LlNK
CONTROL (SOLC) PROTOCOL
J.lPAC X 25
ENHANCEMENTS \
:~
Western Digital Corp. in the first quarter of 1980.
The data-link controllers already on the market
(Western Digital 1933, Signetics 2652, Intel 8273, Zilog
SIO, and others) handle BOP frame structure in a broad
range of applications. For example, the WD 1933 can be
used with the High-level Data Link Control (HOLC) and
Synchronous Data-Link Control (SOLC) protocols,
including the SOLC loop mode. This chip and others like
it handle zero-bit insertion and deletion, the frame-check
sequence (FCS), and the flags that define the beginning
and end of a data frame.
The ,uPAC trades some of this protocol flexibility for
the sake of greatly enhanced usefulness within its area of
application (Fig. I). It is restricted to the Level 2 packetswitching protocol defined in Recommendation X.25
from the Consultative Committee for International Telephony and Telegraphy (CCITT), a protocol developed
from HOLe. But other BOP chips do not set up, disconnect, or reset the link; they do not automatically retransmit up to seven information frames (I frames); nor do
they have a timer for retransmission control. These are
:
~
\
:
X.25
-PROTOCOL ~
I
I
I
I
I
I
I
LINK SET·UP
AND DISCONNECTION.
DATA FLOW CONTROL
I
I
I
I
I
I
HIGH·LEVEL DATA·LlNK
CONTROL (HDLC) PROTOCOL
I
FRAME
{
STRUCTURE
I
I
LINK CONTROL
I
~I
I
I
I
I
I
,I
J.lPAC AREA OF APPLICATION
SDLC
LINK
MODE
I
I
I
o
\
o
APPLICATION AREA OF BIT'ORIENTED'PROTOCOL CHIPS
1. Targeted. The Micro Packet Interface (ILPAC) chip is the first large-scale integrated circuit deSigned specifically for packet-switching
applications. The application range of other chips that handle bit-oriented frame structure is wider, but the ILPAC does much more in its area.
179
TABLE l' COMPARISON OF FEATURES OF BIT-ORIENTED-PROTOCOL CHIPS
H D L C / ADCCP protocol featu re
X.25 Level 2
Bit-oriented-protocol chips
J.lPAC
Basic bit-oriented frame structure
yes
yes
yes
Retransmission of up to 7 I frames (modulo 8)
yes
no
yes
Asynchronous response mode
yes, LAP
no
yes, 2501
Asynchronous balanced node
yes, LAPB
no
yes, 2511
Control of S, U frames
yes
no
yes
yes
Link set·up, disconnect, and reset procedures
yes
no
Time-out recovery
yes, T1/N2
no
yes, T1/N2
Multipoint operation
no
no
yes
f\Jorma! response mode (f\J R~.~)
no
no
no
Level 2 modu 10 128
FS
no
no
FS = item for further study by the CCITT
all features of the J.LPAC chip (see Table 1).
Two versions of the J.LPAC will be made available. One,
the WD 2501, uses the Link-Access Procedure (LAP)
defined in the first version of X.25. The WD 2511 is for
networks using the Link-Access Procedure, Balanced
(LAPB) added to X.25 subsequently. The two chips differ
only in the program stored in ROM. They are pincompatible and interchangeable without hardware br
software modifications. Both may be used either in a
terminal (DTE, data-terminal equipment) or in a network
node (DCE, data-circuit-terminating equipment).
Direct memory access
Because of the HDLC feature that allows up to seven
packets (I frames) to be outstanding (transmitted but
unacknowledged) at any time, the J.LPAC has information-field data (the 1 field of an information frame)
buffered for up to eight packets both when transmitting
and when receiving. In other words, the J.LPAC may have
to retransmit up to seven packets. It must therefore be
able to retrace its steps through as many as seven of its
eight buffers.
DMA circuitry, included in the J.LPAC, is the best way to
achieve this. A number of other control chips (floppydisk controllers and data-link controllers) are DMAcompatible, but they do not actually include DMA.
General-purpose microprocessors that have their own
DMA, such as the Intel 8089, are not in the same category as the J.LPAC.
DMA control on the J.LPAC is simple, requiring only
three pins (DRQW, DROR, and DACK) for handshaking
with the central processing unit's bus (Fig 2.). There are
16 address-output pins (AO through A 15) that are separate from the eight da.ta pins (DALO through DAL7).
This means that the DMA transfers are fast-they occur
in a single cycle. Unlike the J.LPAC, DMA chips such as
Western Digital's 1883 or Intel's 8257 require external
address latches. This means that some or all of the
address must come through the data bus and two or
three cycles are required for data transfer.
In general, DMA control is either of the block-transfer
type or the transparent type. In block-transfer DMA
control, the DMA controller transfers several bytes of
data while the CPU is disabled from using the bus. If
transparent, the DMA control is imbedded in the cPU's
clock cycle in such a way that the transfers are invisible,
or transparent, to the CPU. Since the J.LPAC must be able
to transmit and receive data on two DMA channels at
once (for full-duplex operation), the only logical choice
for the J.LPAC is transparent DMA, since block-transfer
DMA would restrict operation to half-duplex.
All Level 2 data is appended and checked automatically by the J.LPAC. The I-field data is accessed via DMA
channel. All supervisory frames (S frames) and unnumbered frames (U frames) are automatically transmitted
and checked by the J.LPAC. The user's CPU operates only
on the I field of I frames.
Keeping track of packets
The DMA uses two lookup tables-one for transmitted
frames (TLOOK) and another for received frames
(RLOOK). These contain addresses and control bytes for
the individual packets. Thus packet data is addressed
indirectly. This method is best suited for most software
applications.
The 16-bit starting address for TLOOK is loaded into
the J.LPAC by the CPU. RLOOK must follow immediately,
and both TLOOK and RLOOK are stored in random-access
memory external to the J.LPAC.
There are a total of eight segmented control sections
for each table. Each section contains 8 bytes, 4 of which
are used for memory starting address and length. The'
rest are for control.
In the transmit mode, the J.LPAC reads (from TLOOK)
the starting address and length of the first packet to be
transmitted. The chip then automatically transmits the
flag, address, and control fields. Next, the informationfield data is transmitted using DMA and the memory
location called "send #0 packet." At the end of the
information field, the J.LPAC automatically sends the FCS
and closing flag. It then moves on to the next packet.
If retransmission of one or more (up to seven) packets
becomes necessary, the chip automatically retraces the
previous transmissions through the TLOOK table. The
user's CPU software does not become involved in the
retransmission. An error counter is incremented.
180
REPL Y
8'BIT DATA ADDRESS LINE
CS
READ'ONL Y MEMORY
WE
DROR
CENTRAL
MICROCONTROLLER
RE
DROW
IAO-IA3
DACK
iNfR
DATA/CONTROL BUS
AO-A15
MR--
t-----,r---~TD
RD ----y----I~
_TC
_CTS
-RTS
LOOPTEST
2. Ina ide the J.lPAC. The Level 2 controller has its own timer and direct-memory-access circuitry and is the logical equivalent of three
microprocessors. Routines stored on the chip allow it to relieve the network user's central processor of a large software overhead burden.
Each received frame is checked for correct address
and FCS fields and for type of control field. If the frame
is an I frame, the I field is placed in the assigned
memory location using a method similar to that used in
transmission. After the packet is received error-free and
in proper sequence, an interrupt is generated and the
p.PAC is ready for the next packet, which will be placed
in the next location.
Ten 8-bit error counters follow RLOOK in the external
RAM. These counters do not cause an error interrupt, but
maintain a running count of error activity. The contents
of the counters include: the number of frames received
with FCS error; the number of times Tl (the time minimum set for a timer that allows retransmission of an
unacknowledged packet) ran out; and the number of
packet retransmissions.
Control bits are included in TLOOK, RLOOK, and the
p.PAC to ensure orderly transfer of data blocks. For
example, the control bits are designed to prevent what is
known as "deadly embrace," a situation in which the
p.PAC and the user's computer are waiting for one another to start.
Self-testing
Self-testing features are critical to proper operation.
The p.PAC does a comparison test, an internal RAM
register test, and a loop-back test. All three are suitable
for use during manufacturing and inspection. The internal RAM and loop-back tests are also useful for system
diagnostics and troubleshooting.
The comparison test requires a device known to be
good or a stored list of known good responses. The
program location counter (PLC) for the main ROM is
halted so it may be incremented under external control.
TABLE 2 MICRO PACKET INTERFACE CHIP (IlPAC)
TERMINOLOGY
ABM
asynchronous balanced mode
ARM
asynchronous response mode
CMDR
command reject (U frame, LAP only)
DISC
disconnect (U frame)
OM
disconnect mode (U frame, LAPB only)
F RM R
frame reject (U frame, LAPB only)
R EJ
reject (5 frame)
RN R
receiver not ready (5 frame)
RR
receiver ready (5 frame)
SABM
set asynchronous balanced mode (LAPB only)
SARM
set asynchronous response mode (LAP only)
UA
unnumbered acknowledgement (U frame)
All jumps stored in ROM are disabled so that each
location of the PLC may be counted. As the PLC is
incremented, the responses of the output pins and status
registers are compared to the known good responses.
There are 11 8-bit registers in the p.PAC that are not
directly accessible by the user's CPU, which complicates
testing somewhat. The internal RAM register test
provides a means of checking these registers. The
contents of register A are placed in six even internal
registers and the contents of register B in five odd
internal registers. The 11 registers are then added
together without carry and the result is placed in status
registers. This test is initiated by a control bit in the
p.PAC. The loop-back test is discussed later.
For the purposes of discussing link establishment
procedures, it will be assumed that there is a 2501 p.PAC
at each end of the link. In practice, the 2501 can
181
..................................
~
THOUSAND
FEET
tERMINA~B
3. Off the network. The ,uPAC is also useful in non-network applications that use bit-oriented protocols. It provides full-duplex capability.
does error detection and recovery. and gives systems the option of hooking directly to a packet-switching network at some future date.
communicate with any device meeting X.25 Level 2
specifications.
When a link is set up, it is said to be in the information-transfer phase. This means that the terminal and
node will accept and transmit I and S frames. When a
link is logically disconnected, only U frames- DISC,
SARM, or UA (disconnect, set asynchronous response
mode, and unnumbered acknowledge; see Table 2) -will
be accepted or transmitted.
Link supervision
A link-connect frame is not the same as a link-reset
frame. A link in the information-transfer phase may be
reset in one direction by a SARM transmission. A link is
up after both ends send a SARM command and receive a
UA response.
Since a SARM can be either a command to reset or set
up a link, misinterpretation by the receiver of a SARM is
possible. This could happen when a link is established if
one end momentarily loses power. When that end tries to
bring the link up by sending a SARM, the other end may
interpret the command as a link-reset.
There are two ways to get around this problem.
Suppose a terminal or node attempting to bring a link up
sends a SARM command and receives a UA. After time
Tl, if the station does not receive SARM, it assumes that
the other end considered the link up. It will then disconnect the link by sending DISC and receiving a UA, and
attempt to set up a link a second time.
The other way around the problem is the method used
by the 2501. The 2501 will always send DISC and receive
a UA before attempting to bring the link up. This will
assure a logically disconnected link so that it may
attempt to set one up. Immediately after the link is up,
the 2501 generates an interrupt.
It is possible to recover a single error on a packet with
J,tPAC control. The error makes the received FCS bad, so
B does not recognize A's first transmission of frame 1.
When B receives frame 2, something is wrong since the
last successfully received packet was frame O. Thus, at
the next opportunity, B sends a REJ (reject-an S frame)
asking A to retransmit frame 1. This opportunity comes
after B completes sending its frame 2.
When A receives the REJ frame, it is sending frame 3.
There is no need to continue with frame 3, so A aborts
transmission of frame 3 and goes back and retransmits
frame 1. After retransmitting frame 1, A will retransmit
frames 2 and 3. Finally, A will continue transmitting
other frames.
Loop-back
A loop-back condition exists when a station receives
the same serial information it has transmitted. In the
loop-back test, the serial-transmit output is connected to
the serial-receive input in order to test the transmitter
and receiver channels. Each station has both primary
and secondary functions, so there are two logical primary-to-secondary associations on a terminal-to-node link,
and each association is identified by a different address
field. This makes loop-back testing impossible when a
strict X.25 connection is made. Commands will have the
A field of a response and vice versa. One way around this
is to make the A fields of the two associations equal for
the duration of the loop-back test. (The A fields are
programmable in the J,tPAC.)
Another problem with loop-back testing is the actual
182
detection of the condition and the detection of the condition's removal. There is no simple way around this
problem, and the ~PAC gives only limited assistance.
First, detecting the existence of a loop-back condition
is the responsibility of the CPU driving the ~PAC. If the
CPU sees that a link cannot be brought up, or if a link is
up and suddenly has excessive link resets and CMDRS
(command reject, a U frame), the CPU could assume the
presence of a loop-back condition. After making the two
A fields the same, if a disconnected link is successfully
brought up, then the loop-back condition exists.
To detect the removal of this condition, a particular
control bit (RRTI) in the ~PAC may be used. It causes
the ~PAC to send an RR (receiver ready, an S frame) or
an RNR (receiver not ready, also an S frame). These
frames are sent at TI intervals as long as the ~PAC is not
commanded to send a packet. As long as the ~PAC
receives those S frames, the loop-back condition exists.
However, if the ~PAC fails to receive an S frame for a
time equal to TI X N2, an interrupt is generated, signalling that the loop-back condition has been removed.
TERMINALS
AD3
'\
AD5
UJ
>
~
C =8·BIT HEXADECIMAL ADDRESS
FO R TRANSMITTED COMMAND
AND EXPECTED RECEIVED
RESPONSE
AD7
UJ
>
~
AD9
UJ
>
~
R = 8·BIT HEXADECIMAL ADDRESS
FO R TRANSMITTED RESPO NSE
AND EXPECTED RECEIVED
COMMAND
4. Multipoint line. The programmed features of the ILPAC chip enhance the flexibility of a system comprising one master terminal and
up to 128 slave terminals. Hardware and software savings are possi-!
ble when the ILPAC is used in this off-network context.
Suppose that AD3 wishes to communicate with AD7.
AD3 will first make sure that its receiving line is idle (a
status bit in the ~PAC). Next, AD3 will change its
transmitted command and response A fields to be the
reverse of AD7 (command field is set to 07, response
field is set to 01). Then AD3 will initiate link establishment by setting a control bit, called "active," in the
~PAC. Once the link has been established (the ~PAC
generates an interrupt when the link is first set up), AD3
and AD7 may exchange I frames. To discontinue the
session, either AD3 or AD7 will set the mandatorydisconnect control bit in its ~PAC. This will cause that
terminal to initiate a logical-disconnect procedure.
Modified X.2S
The original design intention was to use the ~PAC in a
strict X.25 terminal-to-node application, the only application covered by X.25. However, by taking advantage
of the terminal-node symmetry of the ~PAC (the fact
that it can be used in both DTE and DCE), other applications are possible that use its built-in features.
For instance, the user does not need to develop the
software for error recovery since this is a ~PAC feature.
For another, using a ~PAC makes it possible to connect a
non-packet terminal to an X.25 link at a future time.
And lastly, the chip's protocol is bit-oriented. It has a
number of advantages over older, character-oriented
protocols, such as code transparency, full-duplex capability, flexibility, and modularity [Electronics, Jan. 18,
1979, p. 137].
One possible application is the connection of two
terminals at Levels 1 and 2 (Fig. 3). How much of Level
3 is used would depend upon the individual application;
the more of Level 3 used, the better standardized the
interface is. One of the terminals in Fig. 3 could be a
terminal concentrator (a Packet Assembly/Disassembly
facility, or PAD, as defined by Recommendations X.3,
X.28, and X.29) on a factory floor, and the other could
be a host computer in a data-processing center.
Modified X.25 could also be used in a multipoint
system (Fig. 4). Idle terminals in this type of system
must transmit an "idle" sequence, not continuous flags.
The terminal addresses (AD3, AD5, AD7, and so on)
correspond to the transmitted response A field. The
transmitted command A field is the same for all terminals and is chosen to be hexadecimal Olin this case. All
A fields are selected with odd values (least-significant bit
transmitted first) to conform to the extended-address
format of the Advanced' Data-Communication Control
Procedures (ADCCP).
Two terminals on the multipoint line may establish
and discontinue communications by exercising X.25
procedures for setting up and disconnecting a link. But
only two terminals can communicate at anyone time.
A
/
Contention and roll-call methods
#
The multipoint system may be implemented by either
contention or roll-call polling. In the roll-call method,
the master terminal will initiate link establishment with
one of the slave terminals, communicate with that slave,
discontinue the session (disconnecting the link), and go
on to the next slave. This process continues until all
slaves are polled and then starts over. One advantage of
the roll-call method is that the master has tight control
over the line for efficient operation.
A disadvantage is that slaves must be queried (polled)
before sending data, and the more slaves on the line, the
longer it takes for the master to poll them. Therefore it is
essential that each slave be designed to exchange a
relatively small amount of data with the master in a
single session, lest it tie up the line for long periods.
Large amounts of data should be broken up and
exchanged in more than one session. This method is
suited to applications where the multipoint line has a
high usage.
In the contention method, any terminal may initiate a
session at any time. This is similar to a party telephone
line and is suited to applications where line usage is low.
All sessions are between the master and one of the
slaves, but unlike the roll-call method, a slave may
initiate the session. The terminal that initiates a session
must send an I frame with its unique address immediately after the link is set up.
0
Reprinted from ELECTRONICS, December 20, 1979, copyright 1979 by McGraw-Hili, Inc., with all rights reserved.
183
184
LOCAL NETWORK
ACCESS TRADEOFFS
Cost/complexity tradeoffs are examined in CSMA/CD and
token passing techniques for accessing local area networks
by Mark Stieglitz
ocal networks are characterized by problems that
are very similar to those encountered in conventional data communications networks. I Local networks, however, generate new problems and opportunities that require reconsideration of tradeoffs in
system cost/complexity. A fundamental point of decision in local network design is the choice of access
method. Chief contenders among access techniques are
carrier sense mUltiple access and token passing.
l
What is a local network?
The current controversial nature of local area networks
(LANS) is highlighted by their many definitions. A common theme in these is that the LAN be privately owned
and/or administered by the user. An LAN need not be
considered only as a high speed data transfer
mechanism; current private branch exchanges also meet
the definition of a private system. The opportunity to
optimize the network for a particular user's application,
therefore, becomes a key feature of the network. In this
discussion we assume the following: that a local network is a privately owned communication system; it
usually runs at data rates of lOOk bits/s and above; and
it is usually restricted geographically (100 to 25,000 m).
It is often asked if the X.25 protocol can be used in
LAN applications, especially now that X.25 large scale integration (LSI) controllers are available. This question
Mark Stieglitz is local networks program manager at
Western Digital Corp, 2445 McCabe Way, Irvine, CA
92714. He is responsible jor planning and developing
the company's LSI and system level local network
products. Active in IEEE standards activities, he is
currently chairman oj the IEEE-802 Token Access
Working Group.
can be more readily answered by comparing LAN
and X.25 protocol functions
using the International
Standards Organization
Open Systems Interconnection (ISO/OSI) reference
model. 2,3 The model was
developed to help conceptualize the relationships of
various elements in a communications protocol. The access function resides between physical and link level functions, often referred to
as a link layer sub-layer (Fig 1). The primary difference
is that the concept of a shared medium is foreign to X.25.
Addresses at the link level are actually command/response indicators, since it is assumed that pairs
of stations have point to point links between them.
The local network access layer implements both the
device arbitration and addressing necessary for shared
medium operation. Once this layer is chosen and implemented, it is expected that the remaining layers may
be used in this new application with little change.
Network topologies
In simple terms, topology is the way in which networks
are tied together (Fig 2). Many networks are wired in
ring or star configurations in order to eliminate the contention problems that occur when more than one connected device tries to send data at the same time. The
primary advantage of the bus topology is easy reconfigurability, more important, perhaps, than its reliability advantage. Costs of improving reliability in a star
or ring network, eg, adding redundant subsystems, can
be much less than reconfiguration costs of the same network over its lifetime. Reconfiguration is labor intensive, and the cost of labor is increasing at a faster rate
than that of reliable electronics.
The security of a broadcast bus system is often questioned by users who are apprehensive of the party line
COMPUTER DESIGN
OCTOBER 1981
"Reprinted with permission from Computer
Design - October, 1981 issue. CopYright
.,
1981 Computer DeSign Publishing Company
185
APPLICATION
PRESENTATION
S.ESSION
TRANSPORT
NETWORK
~------~~
r-
The production release procedure for an LSI device is
designed to assure maximum reliability with a
Quality checklist for:
~
:J:J
m
r-
[t'I" Test program qualifications
5>
[t'I" Characterization report
[t'I" Field test (Beta Test) report
!:!!
[t'I" Reliability Lifetest Qualifications
~
r-
[t'I" Infrared Thermal Analysis
[B" Static Protection
All new devices and major process changes must
pass reliability qualification before incorporation into
production using the criteria defined in Tables 2-4.
The infrared microscope shown on the right assures
optimum burn-in temperatures and margins of safety.
The dynamic burn-in system shown on the right is
one of two custom designed systems which assure
protective device isolation during burn-in.
• MAINTAINING RELIABILITY IN PRODUCTION
Process defects control are defined to continually
measure built-in reliability, as measured by the
following criteria:
TABLE 1
PROCESS RELIABILITY CONTROL
Subgroup 1 - Defects Control
a. Oxide Integrity
b. Polysilicon Integrity
Subgroup 2 - Electro-Migration Control
Metal Step Coverage
Subgroup 3 - Defect Density
Subgroup 4 - Passivationllnsulation
Integrity
METHOD
Non-destructive
bubble test
SEM Analysis
CONDITION
Pinhole defect density
5 wafers
Visual
5 wafers
SEM Analysis
5 wafers
MIL-STD-883
Method 2018
Critical layers
Field
Gate
Contact
Metal
Visual of Photo defects
(Defects/in2)
MIL-STD-883 Method
2021
Visual of Pinhole
defect density
·Inspection intervals are defined by the in-line process control data reviewed on a lot-by-Iot basis.
205
SAMPLE*
8 wafers
each layer
Final Silox
5 wafers
Intermediate
5 wafers
• PROGRAMS TO ASSURE OPTIMUM RELIABILITY
gl>
Improved levels of reliability are available under custom reliability programs using static and dynamic burn-in to
further improve reliability. These programs focus on MaS failure mechanisms as follows:
~::D
FAILURE MECHANISMS IN MaS
r-
m
r-
:;
2!
r-
~
FAILURE
MECHANISM
Slow Trapping
Contamination
Surface Charge
Polarization
Electromigration
Microcracks
Contacts
Oxide Defects
Electron Injection
EFFECT ON
DEVICE
ESTIMATED
ACTIVATION ENERGY
Wearout
Wearout!
Infant
Wearout
Wearout
Wearout
Random
Wearout!
Infant
Infant!
Random
Wearout
1.0eV
1.4 eV
Static Burn-In
Static Burn-In
0.5-1.0eV
1.0eV
1.0 eV
Static Burn-In
Static Burn-In
Dynamic Burn-In
100% Temp. Cycling
Dynamic Burn-In
0.3eV
Dynamic Burn-In
at max. voltage
Low Temp. Voltage
Operating Life
-
Temperature Acceleration of Failure
--
------
10"
The Arrhenius Plot defines a failure rate proportional to exp( - Ea/kt) where Ea is the activation
energy for the failure mechanism. The figure on
the right indicates that lower activation energy
failures are not effectively accelerated by temperature alone; hense, maximum voltage operation
is selectively applied to optimize the burn-in
process.
10'
10'
en
a::
10'
0
~
10'
::J
Static Bum-In (125°C - 48 hours or 160 hours)
w
a::
Provided on a sample basis for process
1.0 eV failure
monitor/control of 0.5 eV mechanisms. 100% static burn-in may be
specified at an additional cost. However, static
burn-in is considered only partially effective for
internal LSI gates at logic "0" levels.
Dynamic Burn-In (Pattern testl125°C 160 hours)
SCREENING
METHOD
::J
...J
10'
~
LL
0
IW
~
i=
10'
10'
10'
8 hours to
10'
Accelerated functional dynamic operating life
effectively controls internal MaS gate defects
buried from external pin access. The input pattern
is optionally pseudo-random or fixed pattern
programmable to simulate 1000-3000 hours of field
operation at maximum operating voltage(s).
50
75
100
125 150175200
250
TEMPERATURE (0C)
' - - - - - - - - - - - - _ . _ - - - - - - - - _ .__ ._-
High-Rei "K" Testing Program
General conformance to MIL-STD-883B method
5004.4, Class B with static Burn-In (Dynamic BurnIn may be specified as an option).
206
LSI RELIABILITY STANDARDS
TABLE 2
STANDARD RELIABILITY LEVELS
TEST
METHOD
CONDITION
Infant
Mortality
(see note)
Static
Burn-In
Long Term
Failure Rate
Dynamic
Life Test
125°C -
125°C -
160 hrs.
1000 hrs.
o
c:
FAILURE
l>
r-
~::D
<0.5%
m
r-
<.05%/1000 hrs.
@55°C
60% Confidence
TABLE 3
Subgroup 1
a. Internal Visual
b. Thermal Shock
c. Bond Strength
d. Die Shear Strength
GROUP A DEVICE RELIABILITY MONITORS
METHOD
CONDITIONS
Test Failure Used (cond. B or C)
Test Failures (cond. B)
Test Failures
b. Seal- Fine Leak
1014
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
Subgroup 3
a. Rotating Steady State Life Test
1005
Subgroup 2
a. Seal - Gross Leak
-
b. Electrical Parameters
TABLE 4
TEST
Subgroup 1
a. Thermal Shock
b. Temperature Cycling
c. Seal- Gross Leak
d. Seal - Fine Leak (ceramic)
e. Electrical Parameters
f. 85/85 Moisture Resistance
(plastic only)
g. Electrical Parameters
Subgroup 2
a. High Temp. Storage
b. Mechanical Shock
c. Seal- Gross Leak
d. Seal - Fine Leak
(ceramic)
e. Electrical Parameters
Subgroup 3
a. Lead Integrity
b. Seal - Gross Leak
c. Seal - Fine Leak
(ceramic)
LTPD
15
1011
2011
2019
Static 160 hr. Burn-In 125°C
plus 125°C Lifetest - 1000 hrs.
Final electrical @ 25°C (with data @
70°C)
GROUP B PACKAGE RELIABILITY MONITORS
CONDITIONS
METHOD
1011
1010
1014
1008
2002
1014
Test Condition B or C
Test Condition B or C
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
Electrical at max -C
85% RH/85°C for 1000 hours
PDA = 10%
Fi nal electrical @ 25 ° C
Test Condition B or C
Test Condition B
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
-
Final electrical @ 25°C/max. C
2004
Test Condition B2
(Lead Fatigue)
Fluorocarbon detection 10 - 3
atm/cc/sec
Test Condition A
1014
207
r-
~
"NOTE: Devices failing the infant mortality target remain on burn-in until acceptable failure rates are obtained.
TEST
»~
15
5
LTPD
15
15
15
WESTERN DIGITAL CORPORATION
CHIEF EXECUTIVE
• Systems Quality
• New Product
Qualification
• System Test
Qualification
• Software
Qualification
• LSI Qualification
• Burn-In/Stress
Requirements
• Reliability Monitor
Data
• Reliability Testing
•
•
•
•
Document Control
Wafer Defects Control
Subsidiary/Offshore QC
Process Qualification
•
•
•
•
•
•
•
•
•
Incoming QC
Vendor Quality
LSI Burn-In
LSI Package Monitors
Precap Visuals (883 optional)
100% Test Audit
Failure Analysis
Package Qualification
Calibration Control
,,---------,II'---_ I 1'---_ _ _-----'
"Systems DeSign
Control"
"LSI Design Control"
Figure 2
"Manufacturing Assurance"
QUALITY ORGANIZATION
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
208
Printed in U.S.A
WESTERN DIGITAL
c
o
R
p
o
R
A
T
/
o
N
Announcing Burn-In Program Availability/Warranties
Western Digital now supports customer burn-in
requirements for both static and dynamic burn-in
under the strict control of the QA-Reliability
organ ization.
This burn-in provides high performance 125°C static
and dynamic burn-in for 8-160 hours to eliminate
infant mortality and improve reliability. This process
is executed using custom modified 32Bit AEHR test
commercial burn-in equipment which provide monitored fixed pattern or pseudorandom burn-in with
power s4Pply and resistor device pin isolation.
LSI dynamic burn-in is verified in all cases by the
design engineer for proper functioning. LSI Chip sets
are also individually burned-in with dynamic equivalency to assure high performance bundled reliability.
The warranty on the program will optionally provide
certificate of compliance to standard or custom designed burn-in programs and guarantee <.05%/Khrs
fai lure rate.
CAUTION
Using outside burn-in methods not certified as acceptable by Western Digital may result in voided warranty, due to mishandling, junction temperature
stress, or electrical damage. Further, since most
burn-in houses do not support testing, catastrophic
system condition can result in substantial damage
before a problem is identifi~d.
One consistent problem experienced with outside
LSI burn-in houses can cause reliability problems;
namely, parallelling totem pole MOS outputs, where
the output states are not predictaple, can cause a
single (or a few) device(s) to sink all the current from
the other devices on the burn-in tray - electromigration or current zaps are both possible.
Western Digital burn-in diagrams, dated after 1/1/82,
must be used exactly as shown and will be provided
upon request.
.
SEE YOUR LOCAL REPRESENTATIVE FOR COSTS
AND ORDERING INFORMATION ON THIS NEW
PROGRAM.
209
210
r-
INDEX MARK
PIN I INDICATOR
I
oiO
T"""C\I
~!
T"""~
10
.095 ±.005
(2.40 ± 0.13)
.600 ± .005
(15.24 ± 0.13)
COLO
·s
2.400 +.025
~
I
(60.96 + .64)
•
I-
.050 ±.005
(1.27 ± .13)
.050
(1.27
~
-
-
-
~I
.1
L-
'g;l)
t
.100 ± .010(2.54 ± .25)
.155 ~g~;
(3.94 ~)
NON ACCUMULATIVE
AT SEATING PLANE
48 LEAD PACKAGE
CERAMIC SIDE BRAZE
NOTE:
(
) DENOTES METRIC VALUE IN MM
(0.25 ± 0.05)
.010 ± .002
212
Component Products
Terms and Conditions
1.
ACCEPTANCE: Unless otherwise provided, it is agreed that sales are made on the terms, conditions and warranties contained herein and that to
the extent of any conflict, the same take precedence over any terms or conditions which may appear on Buyer's order form. Seller shall not be
bound by Buyer's terms and conditions unless expressly agreed to in writing. In the absence of written acceptance of these terms, acceptance of
or payment for any of the articles covered hereby shall constitute an acceptance of these terms and conditions.
2.
EO.B. POINT: All sales are made F.O.B. point of shipment. Seller's title passes to Buyer and Seller's liability as to delivery ceases upon making
delivery of articles purchased hereunder to carrier at shipping point in good condition; the carrier acting as Buyer's agent. All claims for damages
must be filed with the carrier. Unless specific instructions from Buyer specify which method of shipment is to be used, the Seller will exercise his
own discretion.
3.
DELIVERY: Shipping dates are approximate only. Seller shall not be liable for any loss or expense (consequential or otherwise) incurred by Buyer
if Seller fails to meet the specified delivery schedule because of unavoidable production or other delays. Seller may deliver the articles in in·
stallments, Seller shall not be liable for any delay in delivery or for non·delivery, in whole or in part, caused by the occurrence of any contingency
beyond the control either of Seller or Seller's suppliers, including, by way of illustration but not limitation, war (whether an actual declaration
thereof is made or not), sabotage, insurrection, riot or other act of civil disobedience, act of a public enemy, failure or delay in transportation, act
of any government or any agency or subdivision thereof, judicial action, labor dispute, accident, fire, explosion, flood, storm or other act of God,
shortage of labor, fuel, raw material or machinery or technical failure where Seller has exercised ordinary care in the prevention thereof. If any
contingency occurs, Seller may allocate production and deliveries among Seller's customers.
4.
TERMS AND METHODS OF PAYMENT: Where seller has extended credit to Buyer, terms of payment shall be net thirty (30) days from date of
invoice. The amount of credit or terms of payment may be changed or credit withdrawn by Seller at any time. If the articles are delivered in in·
stallments, Buyer shall pay for each installment in accordance with the terms hereof. Payment shall be made for the articles without regard to
whether Buyer has made or may make any inspection of the articles. If shipments are delayed by Buyer, payments are due from the date when
Seller is prepared to make shipments. Articles held for Buyer are at Buyer's sole risk and expense.
5.
TAXES: All prices are exclusive of all federal, state and local excise, sales, use, and similar taxes. Such taxes; when applicable to this sale or to
the articles sold, will appear as separate additional items on the invoice unless Seller receives a properly executed exemption certificate from
Buyer prior to shipment.
6.
PATENTS: The Buyer shall hold the Seller harmless against any expense or loss resulting from infringement of patents or trademarks arising from
compliance with Buyer's designs or specifications or instructions. The sale of products by the Seller does not convey any license, by implication,
estoppel, or otherwise, under patent claims covering combinations of said products with other devices or elements. Except as otherwise
provided in the preceding paragraph, the Seller shall defend any suit or proceeding brought against the Buyer so far as based on a claim that any
product, or any part thereof, furnished under this contract constitutes an infringement of any patent of the United States, if notified promptly in
writing and given authority, information and assistance (at the Seller's expense) for the defense of same, and the Seller shall pay all damages and
costs awarded therein against the Buyer. In case said product, or any part thereof, is in such suit held to constitute infringement and the use of
said product or part is enjoined, the Seller, shall at its own expense, either procure for the Buyer the right to continue using said product or part,
or replace same with non·infringing product, or modify it so it becomes non·infringing, or remove said product and refund the purchase price and
the transportation and installation costs thereof. The foregoing states the entire liability of the Seller for patent infringement by the said products
of any part thereof.
7.
ASSIGNMENT: The Buyer shall not assign his order or any interest therein or any rights thereunder without the prior written consent of Seller.
8.
WARRANTY: Seller warrants articles of its manufacture against defective materials or workmanship for a period of one year from date on which
Seller delivers said articles. The liability of Seller under this warranty is limited at Seller's option, solely to repair, replacement with equivalent
articles, or an appropriate credit adjustment not to exceed the original sales price of articles returned to the Seller provided that (a) Seller is
promptly notified in writing by Buyer upon discovery of defects, (b) the defective article is returned to Seller, transportation charges prepaid by
Buyer, and (c) Seller's examination of such article disclosed to its satisfaction that defects were not caused by negligence, misuse, improper
installation, accident, or unauthorized repair or alteration by the Buyer. In the case of equipment articles, this warranty does not include
mechanical parts failing from normal usage nor does it cover limited life electrical components which deteriorate with age. In the case of ac·
cessories, not manufactured by Seller, but which are furnished with the Seller's equipment, Seller's liability is limited to whatever warranty is
extended by the manufacturers thereof and transferable to the Buyer. This Warranty is expressed in lieu of all other Warranties, expressed or
implied, including the implied Warranty of fitness for a particlar purpose, and of all other obligations or liabilities on the Seller's part, and it
neither assumes nor authorizes any other person to assume for the Seller any other liabilities. This Warranty should not be confused with or
construed to imply free preventative or remedial maintenance, calibration or other service required for normal operation of the equipment articles.
These Warranty provisions do not extend the original Warranty period of any article which has either been repaired or replaced by Seller. In no
event will Seller be liable for any incidental or consequential damages.
9.
TERMINATION: Buyer may terminate this contract in whole or from time to time in part upon 60 days written notice to Seller. In such event Buyer
shall be liable for termination charges which shall include a price adjustment based on the quantity of articles actually delivered, and all costs,
direct and indirect, incurred and committed for this contract together with a reasonable allowance for pro·rated expenses and profits. Any ter·
mination or back off in scheduling will not be allowed on shipments scheduled for the month in which the request is made and for the month
following.
10.
GOVERNMENT CONTRACTS: If the articles to be furnished under this contract are to be used in the performance of a Government contract or
subcontract and a Government contract number shall appear on Buyer's purchase order, those clauses of the applicable Government
procurement regulation which are mandatorily required by Federal Statute to be included in Government subcontracts shall be incorporated
herein by reference.
11.
ORIGIN OF ARTICLES: Seller engages in off·shore production, assembly and/or processing and makes no warranty or representation, expressed
or implied, that the articles delivered hereunder are United States articles or of U.S. origin for the purpose of any statute, law, rule, regulation or
case thereunder. If Buyer ships the articles hereunder out of the U.S. for assembly, then at Buyer's request in writing, Seller shall provide in·
formation applicable to identification of any articles not of U.S. origin.
213
Corita Kent, the cover artist, is an American whose work presents an optimistic,
yet philosophical view of the world we live in. A former Catholic nun and
teacher, Corita now devotes her life and energies to her artwork and the "human
needs she feels transcend national and religious barriers." A true "citizen of the
world," Corita's philosophy positions her "on the positive side of hope." Her
depiction of the Western Digital mission . .. "Making the leading edge work for
you" ... dramatizes the spectrum of solutions we provide our customers.
Information furnished by Western Digital Corporation is believed to be accurate and reliable. However, no responsibility is assumed by Western Digital
Corporation for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of Western Digital Corporation. Western Digital Corporation reserves the right to change
specifications at anytime without notice.
214
Printed ,n U.S.A
IIVESTERN DIGITAL
COR
PO
RA
T
/
2445 McCabe Way, Irvine, CA 92714
(714) 557-3550· TWX 910-595-1139
0
N
Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2012:12:14 17:42:23-08:00 Modify Date : 2012:12:14 21:10:11-08:00 Metadata Date : 2012:12:14 21:10:11-08:00 Producer : Adobe Acrobat 9.52 Paper Capture Plug-in Format : application/pdf Document ID : uuid:f935f28e-97d2-4709-80cf-cbd769e236be Instance ID : uuid:1c5545b6-2b08-424e-af5f-f37a2200e205 Page Layout : SinglePage Page Mode : UseNone Page Count : 224EXIF Metadata provided by EXIF.tools