1983_Zilog_Microprocessor_Applications_Reference_Book_Volume_2 1983 Zilog Microprocessor Applications Reference Book Volume 2

User Manual: 1983_Zilog_Microprocessor_Applications_Reference_Book_Volume_2

Open the PDF directly: View PDF .
Page Count: 391

Download
Open PDF In Browser	View PDF

MICROPROCESSOR APPLICATIONS
REFERENCE BOOK
VOLUME 2
August 1983

COPYrIght 1983 by Zllog, Inc. All rIghts reserved. No part
of th,s pubhcahon may be reproduced, stored In a retrIeval
system, or transmItted, In any form or by any means, electromc, mechanIcal, photocopymg, recordmg, or otherwIse,

wIthout the pnor WrItten permlSSlOn of Zllog.
The mformatIon contaIned herem IS subJect to change

wIthout nohce. Zllog assumes no responslblhty for the use of
any cIrcuItry other than cIrcuItry embodIed In a Zllog product No other cIrcuIt patent hcenses are lmphed.

Introduction
Zilog's name has become synonymous with logic
innovation and advanced microprocessor architecture since the introduction of the ZBOe CPU in
1975.
The Zilog Family of microprocessors and
microcomputers has grown to include the products
listed in the table below. Each product exhibits
special features that ma~e it stand above similar
products in the semiconductor marketplace. These
special features have proven to be of substantial
aid in the solution of microprocessor design
problems.

This reference book contains a collection of
application information and Zilog microprocessor
products. It includes technical articles, application notes, concept papers, and benchmarks.
This book is the second of an expected series of
such volumes. We at Zilog believe that designing
innovative microprocessor
integrated
circuit
products is only half the key that unlocks the
future of microprocessor-based end products; the
other half is the creative application of those
products.
Advanced microprocessor products and
their creative applications lead to end product
designs
with
more
features,
more
simply
implemented, and at a lower system cost. It is
hoped that this reference book will stimulate new
product design ideas as well as fresh approaches
to the design of traditional microprocessor-based
products.
The material in this book is believed to be accurate and up-to-date.
If you do find errors, or
would like to offer suggestions for future application notes, we would appreciate hear ing from
you. Correction inputs should be directed to Components Oivision Technical Publications, and

application suggestions should be directed to Components Division Application Engineering.

FAMILY

B-Bit Single-Chip Microcomputer, 2K/4K Bytes
ROM and 144 Bytes RAM

ZB601/ZB603/ZB6L01 MCU
ZB611/2/3 MCU
Z8671 MCU

Microcomputer Unit
Microcomputer Unit
Microcomputer Unit with
BASIC Debug
ZB6B1/2
ROMless
Z8090/4 & ZB590/4 Z-UPC Universal Peripheral
Controller

zao

FAMILY

ZB400 CPU
Z8410 DMA
Z8420 PIO
Z8430 CTC
ZB440/1/2 SIO
ZB470 DART

8-Bit General-Purpose
Microprocessor
Central Processing Unit
Direct Memory Access
Parallel I/O Controller
Counter/Timer Circuit
Serial I/O Controller
Dual Asynchronous
Receiver/Transmitter

Z80L FAMILY

Low-Power B-Bit GeneralPurpose Microprocessor

ZB300
ZB320
Z8330
Z8340

Central Processing Unit
Parallel Input/Output
Counter/Timer Circuit
Serial Input/Output

CPU
PIO
CTC
SIO

Z800D FAMILY

Z8001/2 CPU
Z80m/4 Z-VMPU
Z8010 Z-MMlJ
Z8015 Z-PMMU
Z8016 Z-DTC
Z8030 Z-SCC
Z8031 Z-ASCC

Z8036 Z-CIO
Z8038 Z-FIO
Z8060 Z-FIFO
Z8065 Z-BEP
Z8068 Z-OCP

16-Bit General-Purpose
Microprocessor

Z8500 FAMILY

Central Processing Unit
Virtual Memory Processing
Unit
Memory Managemsnt Unit
Paged Memory Management
Unit
Direct Memory Access
Tranafer Controllar
Serial Communicationa
Controller
Asynchronous Serial
Communications
Controller
Counter/Timer and
Parallel I/O Unit
FIFO I/O Interface Unit
Z-FIFO Buffer Unit and
FlO Expander
Burst Error Processor
Data Ciphering Processor

Z8536 CIO
Z8581 CGC

Universal Peripherals

Z8530 SCC

Serial Communications
Controller
Asynchronous Serial
Communications
Controller

Z8531 ASCC

8/16-Bit General-Purpoas
Microprocessors

Z8108
ZB208
Z8116
Z8216

Microprocessing
Microprocessing
Microprocessing
Microprocessing

MPU
MPU
MPU
MPU

Z80,OOO FAMILY

Z80 , 000 CPU

Counter/Timer and
Parallel I/O Unit
Clock Generator and
Controller

Z800 FAMILY

Z8070 APU
Z8500 FAMILY

Universal Peripherals
(Continued)

Unit
Unit
Unit
Unit

32-Bit General-Purpose
Microprocessor and 80-Bit
Arithmetic Processor
Arithmetic Processing
Unit
Central Processing Unit

....bl. of CoDI.DIs
ZS f..tly
Z8 Subroutine Library • • • • • •
Z8 MCU Test Mode • • • • • • • •
Build a Z8-Based Control Computer with BASIC
Z8671 Seven-Chip Computer • • • • • • • • • •
A Single-Bosrd Terminsl Using the Z8590 Universal
Peripheral Controller • • • • • • • • • • •

1-3
1-53
1-57
1-77
1-B5

ZSD faaily
Z80 CPU vs. 6502 CPU Benchmark Report • • • • • • •
Integrating 8-Bit DMA to 16-Bit System Tutorial • •
Interfacing Z80 CPUa to the Z8500 Peripheral Family

2-3
2-23
2-29

Z800 f..tly
ZBO Memory Expaneion for the ZBOO • • • • • • • • • • • •
On-Chip Memory Management Comes to B-Bit Microprocessors.
8- and 16-Bit Processor Family Keeps Pace with Fast RAMs.

3-3
3-15
3-25

Z800D f..tly
Coat-Effective Memory Selection for Z8000 CPUs
Benchmark Report: Z8000 vs. 68000 vs. 80B6 • •
Operating System Support - The Z8000 Way
A Performance Comparison of Three Contemporary 16-Bit Microprocessors
16-Bit Microprocessors Get a Boost from Demand-Paged MMU • • • • • •
Segmentation Advances Microcomputer Memory AddreSSing •
• • • • •
Initializing the Z8001 CPU for Segmented Operation with the Z8010 MMU
Nonsegmented Z8001 CPU Programming • • • • • • •
Calling Conventions for the Z8000 Microprocessor
Fast Block Moves with the Z8000 CPU • • • • • • •
Character String Translation: Z8000 vs. 6BOOO vs. 8086
Z8002 CPU Small Single-Board Computer • • • • • • •
Interfacing the Z8500 Peripherals to 68000. • • • •
Interfacing the Z-BUS Peripherals to the 8086/8088.
Z8016/Z8000 DTC DMA Transfer Controller
Initializing the CIO • • • • • • • • •
Using SCC with Z8000 in SDLC Protocol •
SCC in Binary Synchronous Communication
Z8530/Z8030 SCC Initialization: A Workaheet and Example
The Z-FIO in a Data Acquisition Application • • • • • • •

4-3
4-9
4-21
4-27
4-39
4-45
4-53
4-59
4-67
4-75
4-79
4-79
4-93
4-105
4-113
4-139
4-153
4-165
4-175
4-183

iii

Z8™Singie Chip Microcomputer Family

Z8® Subroutine Library
ApplicalioD
Nole

Zilog

April 1982
INTRlDJCTlON

This application note describes a preprogrammed
Z8601 MCU that contains a bootatrap to external
program memory and a collection of general-purpose
subroutines.
Routines in this applicstion note
can be implemented with s Z8 Protopack and a 2716
EPROM programmed with the bootstrap and subroutine
librsry.
In s system, the user's software resides in
external memory beginning at hexidecimal sddress
0800.
This software can use any of the

Table 1.
Control Register
N.e
Addrees

subroutines in the library wherever appropriate
for a given applicstion. This application example
makes certain assumptions sbout the environment;
the reader should exercise caution when copying
these programs for other cases.
Following RESET, software within the subroutine
library is executed to initialize the control
registers (Table 1) •
The control register
selections can be subsequently modified by the
user's program (for example, to use only 12 bits
of Ports 0 and 1 for addressing externsl memory).
Following control register initializstion, an El

Control Register Initialization

Heming

Initial Value

TMR

F1H

OOH

TO and T1 dissbled

P2M

F6H

FFH

P2 0-P27 : inputs

P3M

F7H

10H

P2 pull-ups open drain;
PJO-PJJ
inputs;
PJ5-PJ7
outputs;
PJ4
OM

P01M

F8H

07H

P10-P17
AOO-A07 ;
POO-P07
AB-A15;
normal memory timing;
internal stack

IRQ

FAH

OOH

no interrupt requests

IMR

FBH

OOH

no interrupts enabled

FDH

OOH

working register file
OOH-OFH

SPL

FFH

65H

1st byte of stack is
register 64H

1-3

instruction is executed to enable interrupt
processing, and a jump instruction is executed to
transfer control to the user's program at location
OB12 H•
The interrupt vectors for IRQO through
IRQ5 are rerouted to locations OBOOH through
OBOF H, respectively, in three-byte increments,
allowing enough room for a jump instruction to the
appropriate interrupt service routine.
That is,
IRQO is routed to locat ion OBOOH' IRQ1 to
OB03 H, IRQ2 to OB06H' IRQ3 to OB09 H, IRQ4 to
OBOCH' and IRQ5 to OBOFH.
Figure 1 illustrates the allocation of ZB memory as defined by
this application note.
The subroutines available to the user are referenced by a jump table beginning at location
001BH. Entry to a subroutine is made via the jump
table. The 32 subroutines provided in the library
are grouped into six functional classifications.
These classifications are described below, each
with a brief overview of the functions provided by
each category. Table 2 defines one set of entry
addresses for each subroutine in the library.

•

Binary Arithmetic: Multiplication and division
of unsigned B- and 16-bit quantities.

•

BCD Arithmetic:
Addition and subtraction of
variable-precision floating-point BCD values.

FF
FO

•

Conversion Algorithms: BCD to and from decimal
ASCII, binary to and from decimal ASCII, binary
to and from hex ASCII.

•

Bit Manipulations:
Packs selected bits into
the low-order bits of a byte, and optionally
uses the result as an index into a jump table.

•

Serial I/O: Inputs bytes under vectored interrupt control, outputs bytes under polled interrupt control. Options provided include:
odd or even parity
BREAK detection
echo
input editing (backspace, delete)
auto line feed

•

Maintains a time-oF-day clock
Timer /Counter:
with a variable number of ticks per second,
generates an interrupt after a speciFied delay,
generates variable width, variable frequency
pu lse output.

The listings in the "Canned Subroutine Library"
provide a specification block prior to each subroutine, explain the subroutine's purpose, lists
the input and output parameters, and gives pertinent notes concerning the subroutines. The following notes provide additional information on data
formats and algorithms used by the subroutines.
PROGRAM

FFFF

CONTROL
REGISTERS

EXTERNAL DATA

FFFFr--"";;====--.,

EF
UNIMPLEMENTED

80
7F
1
78

7A
2

USER

DEFINED

80
3.
85
84
STACK

----------0812
081 1
USER

START
INTERRUPT VECTORS
(3 BYTElIRQx)

080 0
07F F

DEFINED

INTERNAL
SUBROUTINES

O'
03
110 PORTS

0000 ...._ _ _ _ _ _ _ _..

000 0

00
REGISTERS USED BY SUBROUTINES:

i. USED BY MOST ROuTINES
2. USED BY SERIAL ROUTINES ONLY
3. useD BY TIMER/COUNTER ROUTINES ONLY

Figure 1.

"ROMless Z8" Subroutine library M90ry Usage Map

1-4

Although the user is free to modify the conditions selected in the Port 3 Mode register
(P3M, F7H)' P3M is a write-only register.
This subroutine library maintains an image of
P3M in its register P3M __save (7F H) •
If
software outside of the subroutine package is
to modify P3M, it should reference and modify
P3M save prior to modi ficabon of P3M. For
example, to select P32/P35 for handshake, the
following instruction sequence could be used:

Digits are packed two per byte with the mostsignificant digit in the high-order nibble of
byte 1 and the least-significant digit in the
low-order nibble of byte n. Byte 0 is organized as two f1elds:
Bit 7 represents sign:
1 negative;
o = positlVe.
B1ts 0-6 represent post-decimal digit count.

OR
LD

P3M__save, H04H
P3M, P3M save

For example:
byte 0

4.
•

•

For many of the subroutines in this library,
the location of the operands (source/destination) is flexible between register memory,
external memory (code/data), and the serial
channel (if enabled). The description of each
parameter in the specification blocks tells
what the location options are.
The location designation "in reg/ext
memory" implies that the subroutine allows
the operand to exist in register or in
external data memory. The address of such
an operand is contained 1n the designated
register pair.
If the high byte of that
pa1r is 0, the operand is in register
memory at the address held in the low byte
of the register pair.
Otherwise, the
operand is in external data memory
(accessed via LDE).

= positive, with five
decimal digits
negative, with no
BOH
decimal digits
90H = negative, with 16
dec imal d 19itS

05H

postpostpost-

The format of the decimal ASCII character
string expected as input to the conversion
routines "dascbcd" and "dascwrd" is defined
as:
( + 1 - ) ( ) ]

in which
( )
[ ]

The location designabon "in reg/ext/ser
memory" implies the same considerations as
above with one enhancement: if both bytes
of the register pair are 0, the operand
exists in the serial channel.
In this
case, the reg1ster pair is not modified
(updated). For example, rather than storing a destination ASCII string in memory,
it might be desirable to output the string
to the serial line.

Parentheses mean that the enclosed
times or can be omitted.
Brackets denote that the enclosed
element is optional.

Table 3 illustrates how var10US input strings
are interpreted by the conversion routines.

The format of the decimal ASCII character
string output from the conversion routine
"bcddasc" operating on an input BCD string of
2n digits is
sign of character ( + 1 - )
2n-x pre-decimal dig1ts
1 decimal point if x does not equal 0
x post-decimal d1gits

The BCD format supported by the following
arithmetic and conversion routines allows representation of signed variable-precision BCD
numbers. A BCD number of 2n digits is represented in n+ 1 consecutive bytes, where the
byte at the lowest memory address (byte 0)
represents the sign and post-decimal digit
count, and the bytes in the n higher memory
locations (bytes 1 through n) represent the
magnitude of the BCD number. The address of
byte O,and the value n are passed to the subroutines in specified working registers.

The format of the decimal ASCII character
string output from the conversion routine
"wrddassc tl is

1 sign character (determined by bit 15 of
input word)
6 pre-decimal digits
no decimal point
no post-decimal digits
1-5

Table 2.

Description

Address

Binary

001B
001E
0021
0024
BID

0027
002A

Subroutine Entry Points

Arit~tic

Routines

divide
div 16
multiply
mult 16

16/8 unsigned binary division
16/16 unsigned binary division
8x8 unsigned binary multiplication
16x16 unsigned binary multiplication

Routines

Arit~ic

bcdadd
bcdsub

BCD addition
BCD subtraction

COnversion Routines

0020
0030
0033
0036
0039
003C
003F
0042
0045

bcddasc
dascbcd
bcdwrd
wrdbcd
bythasc
wrdhasc
hascwrd
wrddasc
dascwrd

BCD to decimal ASCII
Decimal ASCII to BCD
BCD to binary word
Binary word to BCD
Binary byte to hexadecimal ASCII
Binary word to hexadecimal ASCII
Hexadecimal ASCII to binary word
Binary word to decimal ASCII
Decimal ASCII to binary word

Bit Manipulation Routines

0048
004B

c1b
tmj

Collect bits in a byte
Table jump under mask

Serial Routines

004E
0051
0054
0057
005A
0050
0060
0063
0066
0069

ser init
ser_input
ser rlin
ser rabs
ser break
ser flush
ser wHn
ser wabs
ser_wbyt
ser disable

T~r/COunter

006C
006F
0072
0075
0078

Initialize serial I/O
IRQ3 (receive) service
Read line
Read absolute
Transmit BREAK
Flush (clear) input buffer
Write line
Write absolute
Write byte
Disable serial I/O

Routines

tod i
tod
delay
pulse_i
pulse

Initialize for time-of-day clock
Time-of-day IRQ service
Initialize for delay interval
Initialize for pulse output
Pulse IRQ service

1-6

rhe register pair SERhtime, SER1time was
initialized during ser
Init to equal the
product of the prescaler and the counter
selected for the baud rate clock. That is,

Procedure name: ser___input
The conclusion of the algorithm for BREAK
detection requires the Serial Receive Shift
register to be cleared of the character
currently being collected (i f any).
This
requires
a software wait
loop of a
one-character duration.
The
following
explains the algorithm used (code lines 464
through 472, Part II):

SERhtime, SER1time = PREO x TO
The instruction sequence
inlop: ld
lpl:

1 character time = (128xPREOxTO) sec 10 ~
XT AL
iiIT x
char

1280xPREOxTO sec
XTAL
Ch8r

rSERtmpl, lpl

(12/10 cycles
tsken/not taken)

6 + (52 x 12) + 10 cycles

1 character time =.2.... ~ x n cyc Ie
XTAL cycle
loop
sec
loop

Solve for n:
(1280 x PREO x TO)
XTAL

(6 cycles)

executes in

A software loop equal to one character time is
needed:

2n
= Xfj['

djnz

rSERtmpl, 153

=Xfj['

640 cycles

BREAK detection on the serial input line
requires that the receive interrupt service
routine be entered within a half-a-bit time,
since the routine reads the input line to
detect a true (= 1) or false (=0) stop bit.
Since the interrupt request is generated
halfway through reception of the stop bit,
half-a-bit time remaina in which to read the
stop bit level.
Interrupt priorities and
interrupt nesting should be established
appropriately to ensure this requirement.

n = 640 x PREO x TO
1/2 bit time = (128 x PREO x TO)
XTAL x 2

Table}.

Input String

+1234.567,

Decillal ASCII ll'Iara:ter String Interpretation
- - - - - Result - - - - - PrlH)ecillal
Poat-Decillal

Sign

Digits

1234

567
789

+---+.789+
1234 ••

4976-

NOTE:

leninator

1234
4976

The terminator can be any ASCII character that ia not a valid ASCII string
character.

1-7

sec

ROMLESS Z8 SUBROUTINE LIBRARY PART I
Z8ASM
LOC

3.02
OBJ CODE

STMT SOURCE STATEMENT
1

3 PART I
4

MODULE

5
6 I'ROMLESS Z8'
7
8 Initialize:

9
10
11

12
13
14
15
16
17
18
19
20 Note:
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

40
41
42

SUBROUTINE LIBRARY

PART I

a) Port 0 & Port 1 set up to address
64K external memory;
b) internal stack below allocated
RAM for subroutines;
c) normal memory timing;
d) IMR, IRQ, TMR, RP cleared;
e) Port 2 inputs open-drain pull-ups;
f) Data Memory select enabled;
g) EI executed to 'unfreeze' IRQ;
h) Jump to %0812.

The user is free to modify the initial
conditions selected for a, b, and c above,
via direct modification of the Port 0 & 1
Mode register (P01M, %F8).
The user is free to modify the conditions
selected in the Port 3 Mode register (P3M, %F7).
However, please note that P3M is a write-only
register. This subroutine library maintains
an image of P3M in its register P3M save (%7F).
If software outside of the subroutine package
is to modify P3M, it should reference and modify
P3M save, prior to modification of P3M. For
example, to select P32/P35 for handshake, use
an instruction sequence such as:
OR
LD

P3M save,n04
P3M-;P3M_ save

This is important if the serial and/or timerl
counter subroutines are to be used, since these
routines may modify P3M.

1-8

44 IAccess to GLOBAL subroutines in this library should
45 be made via a CALL to the corresponding entry in the
46 jump table which begins at address SOOOF. The jump
47 table should be referenced rather than a CALL to the
48 actual entry point of the subroutine to avoid future
49 conflict in the event such entry pOints change in
50 potential future reviSions.
51

52
53
54
55
56
57
58
59
60

Each GLOBAL subroutine in this listing is headed by a
comment block specifying its PURPOSE and calling
sequence (INPUT and OUTPUT parameters). For many of
the subroutines in this library, the location of the
operands (sources/destinations) is quite flexible
between register memory, external memory (code/data),
and the serial channel (if enabled). The description
of each parameter specifies what the location choices
are:

62
63
64
65
66
67
68
69
70

- The location designation 'in reg/ext memory'
implies that the subroutine allows that the operand
exist in either register or external data memory
The address of such an operand is contained
in the designated register pair. If the high byte of
that pair is zero, the operand is in register memory
at the address given by the low byte of the register
pair. Otherwise, the operand is in external data
memory (accessed via LDE).

72
73
74
75
76
77
78
79

- The location designation
'in reg/ext/ser memory' implies the same
considerations as above with one enhancement: if both
bytes of the reg. pair are zero, the operand exists
in the serial channel. In this case, the register
pair is not modified (updated). For example, rather
than storing a destination ASCII string in memory, it
might be desirable to output such to the serial line.

80 I

1-9

82 CONSTANT
83 !Register Usage!
84
85 RAM START
%7F
86
RAM START
87 P3M save
:=
88 TEM1i 3
P3M- save-1
:=
89 TEMP-2
TEMl'" 3-1
90 TEMP-1
TEMP-2-1
:=
TEMP-1-1
91 TEMP-4
:=
92
93 !The following registers are modified/referenced
94 by the Serial Routines ONLY. They are
95 available as general registers to the user
96 who does not intend to make use of the
97 Serial Routines!
98
99 SER char
·_
TEMP 4-1
100 SER-tmp2
:=
SER char-1
101 SER-tmp1
._
SER-tmp2-1
102 SER-put
:=
SER-tmp1-1
103 SER-len
:=
SER-put-1
104 SER-buf
:=
SER-len-2
105 SER-imr
:=
SER-buf-1
106 SER-c fg
!=
SER-imr-1
107 !Serial Configuration Data
108 bit 7
=1 => odd parity on
109 bit 6 ! =1 => even parity on
110 (bit 6,7 = 11 => undefined)
111 bit 5
undefined
undefined
112bit4
113 bit 3
=1 => input editting on
=1 => auto line feed enabled
114 bit 2
115 bit 1
=1 => BREAK detection enabled
116 bit 0
=1 => input echo on
117 !
118 op
%80
119 ep
%40
120 ie
%08
121 al
%04
·
122 be
%02
:=
123 ec
%01
SER cfg-1
124 SER get
125 SER-flg
SER=get-1
:=
126 ! Serial Status Flags
127 bit 7
=1 => serial I/O disabled
undefined
128 bit 6
129 bit 5
undefined
=1 => parity error
130 bit 4
131 bit 3
=1 => BREAK detected
=1 => input buffer overflow
132 bit 2
133 bit 1
=1 => input buffer not empty
=1 => input buffer full
134 bit 0
135 !
136 sd
%80
137 pe
%10
138 bd
%08
139 bo
%04
=
140 bne
%02
=
141 bf
%01
142
143 RAM TMR
RAM_START-%10
:=
144
145 SERl time
SER_flg-1
-

·
·

1-10

146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169

SERhtime

SERltime-1

IThe following registers are modified/referenced
by the Timer/Counter Routines ONLY. They are
available as general registers to the user
who does not intend to make use of the
Timer/Counter Routinesl
TOO tic
TOO-imr
TOO-hr
TOO-min
TOO-sec
TOO-tt
PLS-1
PLS-tmr
PLS-2

RAM TMR-2
TOO-tic-1
TOO-imr-1
TOOnr-1
TOO-min-1
TOO-sec-1
TOO-tt-1
PLS-1-1
PLS-tmr-1

:=
:=
:=

RAM END
STACK
IEquivalent working register equates
for above register layoutl

170 Iregister file S70 - S7FI
171 RAM STARTr
:=
%70
172
R15
173 rP3Msave
:=
174 rTEMP 3
R14
R13
175 rTEMP-2
R12
176 rTEMP-1
RR12
177 rrTEMP 1
:=
rTEMP
lh
178
R12
rTEMP-ll
R13
179
:=
180 rTEMP-4
R11
:=
R10
181 rSERchar
182 rSERtmp2
R9
R8
183 rSERtmp1
:=
184 rrSERtmp
RR8
185 rSERtmpl
R9
:=
186 rSERtmph
R8
rSERput
R7
187
:=
188 rSERlen
R6
RR4
189 rrSERbuf
:=
190 rSERbufh
R4
R5
191 rSERbufl
192 rSERimr
:=
R3
R2
193 rSERcfg
:=
194 rSERget
R1
RO
195 rSERflg
:=
196
197
198 !register file %60 - %6FI
199 RAM TMRr
%60
200 rTO!5tic
!=
R13
R12
201 rTOOimr
202 rTOOhr
R11
:::
R10
203 rTODmin
204 rTOOsec
:=
R9
205 rTOOtt
R8
206 rPLS 1
R7
R6
207 rPLStmr
:=
208 rPLS 2
R5
:=

1-11

I for SRPI

P
P
P
P
P
P

0000
0002
0004
0006
0008
OOOA

0800
0803
0806
0809
OBOC
OBOF

210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242

EXTERNAL
ser in it
ser=input
ser rlin
ser-rabs
ser-break
ser-flush
ser-wlin
ser-wabs
ser-wbyt
ser-disable
ser:get
ser output
tod-i
toddelay
pulse i
pulse-

GLOBAL

PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE
PROCEDURE

$SECTION PROGRAM

IInterrupt vectorsl
IRQ 0
ARRAY
[ 1 word]
IRQ-1
ARRAY
[1 word]
IRQ-2
[ 1 word]
ARRAY
IRQ-3
ARRAY
[ 1 word]
IRQ-4
[ 1 word]
ARRAY
ARRAY
[ 1 word]
IRQ=5

1-12

=
=
=
=
=
=

[J0800]
[~0803]
[~0806]
[~0809]
[~080C]
[~080F]

----~-------

oooe

P OOOC 80
P OOOF

007B'

P
P
P
P

43
39
5A
4F

OOOF
0012
0015
0018

28
31
30
4C

29
38
49
47

P 001B

P 001B 80

0099'

P 001E 80

00B7'

P 0021 80

00E2'

P 0024 80

00F6'

P 0027 80

011A'

P (102A 80

0117'

P 0020 80

0205'

P 0030 80

0363'

P 0033 80

0284'

P 0036 80

02CD'

P 0039 80

025C'

P 003C 80

0257'

P 003F 80

0319'

P 0042 80

03BE'

P 0045 80

0340'

P 0048 80

04A l'

P 004B 80

04B9'

P 004E 80

0000-

244
245
246
247
248
249
250
251
252
253

254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304

GLOBAL
!Jump Table!
ENTER
PROCEDURE
ENTRY
INIT
JP
END
ENTER
copyright ARRAY [- BYTE] : = ' ( C) 198 OZ ILOG '

!Subroutine Entry Points!
PROCEDURE
JUMP
ENTRY
!Binary Arithmetic Routines!
JP

divide

div 16

multiply

mult 16

!16/8 unsigned binary
division!
!16/16 unsigned binary
division!
!8x8 unsigned binary
multiplication!
!16x16 unsigned binary
multiplication!

!BCD Arithmetic Routines!
JP

bcdadd

!BCD addition!

bcdsub

! BCD subtraction!

! Conversion Routines!
JP

bcddasc

!BCD to decimal ASCII!

dascbcd

! Decimal ASCII to BCD!

bcdwrd

!BCD to binary word!

wrdbcd

!binary word to BCD!

bythasc

! Bin. byte to Hex ASCII!

wrdhasc

! Bin. word to hex ASCII!

hascwrd

! Hex ASCII to bin word!

wrddasc

! Bin. word to dec ASCII!

dascwrd

! dec ASCII to bin word!

!Bit Manipulation Routines!
JP

clb

!collect bits in a byte!

tjm

!Table Jump Under Mask!

! Serial Routines!
JP

ser init

1-13

!initialize serial I/O!

P 0051 80

0000·

0054 80

0000·

P 0057 80

0000·

P 005A 80

0000·

P 0050 80

0000·

P 0050 80

0000·

P 0053 80

0000·

P 0056 PO

0000·

P 0069 80

0000·

006C 80

0000·

P 006F llD

0000·

0072 80

0000·

0075 80

0000·

0078 80

0000·

007B

P 007B E6

P 007E E6

E4
E5
BO
E5
BO
BO
BO
E6
9F

7F
FF
F1
F6
FA
FB
FD
70

F7
55

P
P
P
P
P
P
P
P
P

0081
0084
0087
0089
008C
008E
0090
0092
0095

P 0095 8D
P 0099

0812

305
JP
ser_input
305
307
ser rlin
JP
308
309
ser rabs
JP
310
311
ser break
JP
312
313
ser flush
JP
314
315
ser wlin
JP
315
317
JP
ser wabs
318
319
JP
ser_wbyt
320
321
JP
ser disable
322
323
324 !Timer/Counter Routinesl
325
tad i
JP
326
327
tad
JP
328
329
delay
JP
330
331
pulse i
JP
332
333
pulse
JP
334
335
JUMP
336 END
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
355
357
358
359
350
361
362
363
354

!IRQ3 (receive) service!
Iread liner
tread absolute I
!transmit BREAKI
! flush (clear)

input bufferl
!write linel

Iwrite absolutel
Iwrite byte!
Idisable serial I/OI

linit for time of dayl
!tod IRQ servicel
linit for delay interval
linit for pulse output I
Ipulse IRQ servicel

IInitializationl
PROCEDURE
INIT
ENTRY
LD

LD
LD
CLR
LD
CLR
CLR
CLR
LD
EI
JP
END

P01M,#$(2)11010111
linternal stack;
ADO-A15;
normal memory
timing I
P3M_save,#$(2)00010000
!P3M is write-only,
50 keep a copy in
RAM for later
reference I
P3M,P3M save
! set up Port 3
I stack pointer
SPL,#S1'J:CK
Ireset timersl
TMR
I all inputs I
P2M,UFF
IRQ
!reset into requests I
Idisable interrupts I
IMR
Iregister pointerl
RP
Iserial disabledl
SER_flg, U80
I globally enable
interrupts I
$0812

IN!T

1-14

--~~~~

Binary

Ar~thmetic

P 0099

P 0099 A9
P 009B AC

7C
08

P 009D A2
P 009F BB

BC
02

P OOAl DF
P 00A2 AF
P
P
P
P
P
P
P
P

00A3
OOA5
00A7
00A9
OOAB
OOAD
OOAF
OOBO

10
10
7B
A2
BB
22
DF
AA

ED
EC
04
BC
03
CB
Fl

P 00B2 10

P 00B4 A8
P 00B6 AF
P 00B7

~~.

Rouhnes
397
398
399
400
401
402
403
11011
1105
1106
1107
408
1109
1110
1111
1112
413
11111
1115
416
417
1118
1119
420
421
1122
1123
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442

CONSTANT
div LEN
=
DIVTsOR
=
dividend HI
dividend-LO
GLOBAL
divide PROCEDURE

Rl0
Rll
R12
R13

I·····················································
Purpose =
To perform a 16-bit by 8-bit unsigned
binary division.

Input
Output

=
=

Rll = 8-bit divisor
RR12 = 16-bit dividend
R13 = 8-bit quotient
R12 = 8-bit remainder
Carry flag = 1 if overflow
= 0 if no overflow
R11 unmod 1fi ed

·····················································1
ENTRY
ld
ld

TEMP 1,div LEN
div_tEN,118-

I save caller's Rl01
!LOOP COUNTER I

ICHECK IF RESULT WILL FIT IN 8 BITSI
cp
DIVISOR,dividend HI
TCARRY
UGT,LOOP
jr
loverflow!
SCF
!CARRY
ret
LOOP:

subt:
next:
IALL

0 (FOR RLC)!

= 11

RLC
RLC
jr
cp
jr
SUB
SCF
djnz

dividend LO
!DIVIDEND • 21
dividend=HI
c,subt
DIVISOR,dividend_HI
UGT,next
ICARRY = 01
dividend_HI,DIVISOR
ITO BE SHIFTED INTO RESULTI
Ino flags affectedl
div_LEN,LOOP

DONEI
RLC

dividend LO

Id
ret
END divide

div_LEN,TEMP_

1-15

!CARRY = 0: no over flow I
Irestore caller's Rl01

P 00B7

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

00B7
00B9
OOBB
OOBC
OOBE
OOCO
00C2
00C4
00C6
00C8
OOCA
OOCC
OOCE
OODO
00D2
0004
0006
0008
00D9
OODB
OODD
OODF
OOEl
00E2

79
7C
CF
BO
BO
10
10
10
10
7B
A2
BB
7B
A2
BB
22
32
DF
7A
10
10
78
AF

7C
10
EA
EB
ED
EC
EB
EA
OA
8A
OB
04
9B
05
B9
A8
E5
ED
EC
7C

P 00E2

P
P
P
P
P
P
P
P
P

P
P
P

OOE2
00E4
00E6
00E8
00E9
OOEB
ODED
OOEF
OOFl
00F3
00F5
00F6

A9
AC
BO
CF
CO
CO
FB
02
AA
A8
AF

7C
09
EC
EC
ED
02
CB
F6
7C

444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489

CONSTANT
d16 LEN
dvsr hi
dvsr-lo
rem hi
rem-lo
quot hi
quot-lo
GLOBAL
div 16 PROCEDURE

491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520

CONSTANT
MULTIPLIER
PRODUCT LO
PRODUCT-HI
mul LENGLOB1iL
multiply

R7
R8
R9
Rl0
Rll
R12
R13

! •• T ••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose =

To perform a 16-bit by 16-bit unsigned
binary division.

Input =

RR8 = 16-bit divisor
RR12 = 16-bit dividend

Output

RR12 = 16-bit quotient
RR10
16-bit remainder
RR8 unmodified

•••••••••••••••••••••••••••••••••••••••••••••••••• *•• !
ENTRY
Id
Id
rcf
clr
clr
dlp_16: rIc
rIc
rIc
rIc
jr
cp
jr
jr
cp
jr
subt 16: sub
sbc
scf
skp_16: djnz
rIc
rIc
Id
ret
END div_16

TEMP 1,d16 LEN
d16_LEN,#10
rem hi
rem-lo
quot 10
quot-hi
rem To
rem-hi
c,stibt 16
dvsr hI,rem hi
ugt,skp 16 ult,subt 16
dvsr lo,rem 10
ugt,skp 16rem lo,avsr 10
rem=hi, dvsr =hi
d16 LEN,dlp 16
quol: 10
quot-hi
d16_1:EN,TEMP_l

!save caller's Rl0!
ILOOP COUNTER!
!carry = O!

!no flags affected!

Rll
R13
R12
Rl0
PROCEDURE

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose =

To perform an 8-bit by 8-bit unsigned
binary multiplication.

Input =

R11 = multiplier
R13 = multiplicand

Output

RR12 = product
Rll unmodified

••••••••••••••••••••••••••••••••••••••••••••••••••••• !

ENTRY

LOOP1:

NEXT:
END

Id
TEMP 1,mul LEN !save caller's Rl01
mul 1:EN, 119! 8 BITS I
Id
clr
PRODUCT HI
!INIT HIGH RESULT BYTEI
RCF
!CARRY = 01
RRC
PRODUCT HI
PRODUCT-LO
RRC
jr
NC,NEXT
PRODUCT HI,MULTIPLIER
ADD
djnz
mul LEN-;-LOOPl
mul=LEN,TEMP_l !restore caller's Rl01
Id
ret
multiply
1-16

P 00F6

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

00F6
00F8
OOFA
OOFC
OOFE
OOFF
0101
0103
0105
0107
0109
010B
0100
010F
0111
0113
0116
0117

79
7C
BO
BO
CF
CO
CO

CO
FB
02
12
7A
78
A9
44
AF

7C
11
EA
EB
EA
EB
EC
ED
04
B9
A8
FO
7C
7C
EB

522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563

CONSTANT
m16 LEN
plier hi
plier-lo
prod hi
prod-lo
mult-hi
mult-lo
GLOBAl:
mult 16 PROCEDURE

R7
R8
R9
R10
R11
R12
R13

I···T.................................................
Purpose

To perform an 16-bit by 16-bit unsigned
binary multiplication.

In put =

RR8 = multiplier
RR12 = multiplicand

Output

RQ10 = product (R10, R11, R12, R13)
RR8 unmodified
Zero FLAG = 0 if result> 16 bits
= 1 if result fits in 16
(unsigned) bits (RR12 = result)

·····················································1
ENTRY
Id
Id
clr
clr
rcf
100p16: rrc
rrc
rrc
rrc
jr
add
adc
next16: djnz
Id
Id
or
ret
mult 16
END

TEMP 1,m16 LEN
m16 LEN,111'T
prod hi
prod:lo

Isave caller's R7!
116 BITSI
linit product!
ICARRY = 01

prod hi
prod-lo
Ibit 0 to carry!
mult-ni
Imultiplicand / 21
mult-lo
nc,next16
prod lo,plier 10
prod-hi,plier-ni
m16 LEN,100p16 Inext bit!
m16-LEN,TEMP 1 !restore caller's R71
TEMP 1,prod hi Itest product ... !
TEMP:1,prod:lo I •.. bits 31 - 16!

1-17

BCD Ar1thmet1c Rout1nes
593 !The BCD format supported by the following arithmetic
594 and conversion routines allows representation
595 of signed magnitude variable precision BCD
596 numbers. A BCD number of 2n digits is
597 represented in n+1 consecutive bytes where
598 the byte at the lowest memory address
599 ('byte 0') represents the sign and post600 decimal digit count, and the bytes in the
601 next n higher memory locations ('byte l'
602 through 'byte n') represent the magnitude
603 of the BCD number. The address of 'byte 0'
604 and the value n are passed to the subroutines
605 in specified working registers. Digits are
606 packed two per byte with the most
607 significant digit in the high order nibble
608 of 'byte l' and the least significant digit
609 in the low order nibble of 'byte n'. 'Byte 0'
610 is organized as two fields:
611
bit 7 represents sign:
612
= 1 => negative
613
= 0 => positive
614
bit 6-0 represent post-decimal digit
615
count
616 For example:
617 'byte 0'= %05 => positive, with 5 post-decimal digits
61e
= %80 => negative, with no post-decimal digits
619
= %90 => negative, with 16 post-decimal digits
620

P 0117

P 0117 B7
P 011A

622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651

CONSTANT
bcd LEN := R12
bcd-SRC '- R14
bcd-DST := R15
GLOBl"L
bcdsub PROCEDURE

I·····················································
Purpose =
To subtract two packed BCD strings of
equal length.
dst <-- dst - src

Input =

R15
R14
R12

Output

address of destination BCD
string (in register memory).
address of source BCD
string (in register memory).
BCD digit count / 2

Destination BCD string contains the
difference.
Source BCD string may be modified.
R12, R14, R15 unmodified if no error
R13 modified.
Carry FLAG = 1 if underflow or format
error.

·····················································1
ENTRY
xor

!complement sign of
subtrahend!

!fall into bcdaddl
END
bcdsub

1-18

P 011A

653 GLOBAL
6511 bcdadd PROCEDURE
655
To add two packed BCD strings of
656 Purpose =
equal length.
657
dst
<-- dst + src
658
659
R15
address of destination BCD
660 Input =
string (in register memory).
661
R111 = address of source BCD
662
string (in register memory).
663
R12
BCD digit count / 2
6611
665
Destination BCD string contains the sum.
666 Output =
Source BCD string may be modified.
667
668
R12, R111, R15 unmodified if no error
R13 modified.
669
Carry FLAG = 1 if overflow or format
670
error.
671
672
673 ENTRY
674 Idelete all leading pre-decimal zeroesl
ld
TEMP 3,#2
675
ld
R13,bcd SRC
676
ld
TEMP lI,ocd LEN
677
add
TEMP-4,TEMP
II
!total digit countl
678
ld
TEMP-2,@R13Iget sign/post dec 01
679
lisolate post dec #1
and
TEMP-2,0~7F
680
Ipre-dec digit cntl
sub
TEMP-II, TEMP 2
681
jp
ult,oa err 682
! format error I
Ino pre-dec. digitsl
jr
z,ba 1683
push
R12 Isavel
6811
Ileading
by tel
ld
R12,1(R13)
685
!test leading digiti
tm
R12,UFO
686
Irestorel
pop
R12
687
jr
nz,ba 1
!no more leading O'sl
688
clr
TEMP T
689
call
rdl
Irotate leftl
690
!update post dec #1
inc
@R13
691
jp
ov,ba err
!oopsl
692
Idec pre-dec #1
dec
TEMP 11"
693
jr
nz,bs 2
Iloopl
6911
ld
R13,bcd OST
695 ba 1:
dec
TEMP
3
ISRC and OST done?1
696
Ido OSTI
jr
nz,bs_3
697
698 Ileading zero deletion complete I
699 linsure OST is > or = SRC; exchange if necessaryl
ld
R13,@bcd OST
700
!isolate post dec #1
and
R13,0~7F701
ld
TEMP 2,@bcd SRC
702
lisolate post dec #1
and
TEMP-2,#~7F703
cp
R13,TEMP 2
7011
R13
Isavel
push
705
jr
ult,ba II
lOST> SRCI
706
jr
ugt,ba-5
lOST < SRCI
707
708 Idecimal points in same position.
709 must compare magnitudel
ld
R13,bcd LEN
710
ld
TEMP 1,DCd SRC
711
ld
TEMP-II,bcd-OST
712
inc
TEMP-1
713
inc
TEMP-II
7111
ld
TEMP-3,@TEMP
1 Iget SRC by tel
715
cp
TEMP=3,@TEMP=1I Icompare OST by tel
716

I·····················································

·····················································1

P011AE6
P 0110 08
P 011F C9
P 0121 011
P 01211 E5
P 0127 56
P 012A 211
P 0120 70
P 0130 6B
P 0132 70
P 0134 C7
P 0137 76
P 013A 50
P 013C EB
P 013E BO
P 0140 06
P 0143 21
P 0145 40
P 01118 00
P 0111A EB
P 0111C 08
P 0111E 00
P 0150 EB

7E 02
EE
7B
7B 7B
ED 70
70 7F
70 7B
0203'
1A
EC
CD 01
EC FO
EC
OE
7C
01163 '
ED
0203 '
7B
E6
EF
7E
CD

P
P
P
P
P
P
P
P

0152
0154
0157
015A
0150
0160
0162
01611

E3
56
E5
56
All
70
7B
BB

OF
ED
EE
70
70
ED
39
18

0166
0168
016A
016C
016E
P 0170
P 0173

Oil
E9
F9
20
20
E5
A5

EC
7C
7B
7C
7B
7C
7B

P
P
P
P
P

7F
70
7F
ED

7E
7E

1-19

P
P
P
P

0176
0178
017A
017C

BB
7B
OA
8B

06
23
FO
1F

P
P
P
P
P
P
P
P
P
P
P
P
P
P

017E
0180
0181
0183
0185
0187
0189
018C
018F
0192
0195
0197
0199
019B

08
OE
02
02
00
00
E5
E5
F5
F5
OA
08
50
70

EC
EO
FO
EE
EF
EE
EF
7B
7C
EE
70
70
EO

P 0190 50

P 019F 24
P 01A2 CO
P 01A4 FB

EO
70
09

P
P
P
P

EE
EO
7C
0485'

01A6
01A8
01AA
01AC

08
01
BO
06

P 01AF E5
P 01B2 B5

EE
EF

P
P
P
P
P

01B5
01B7
01BA
01BC
01BE

08
24
6B
02
02

EC
70
45
EO
FC

P
P
P
P
P
P
P
P
P
P
P
P

01CO
01C1
01C4
01C7
01C9
01CC
01CE
0101
0103
0106
0108
010A

CF
E5
76
6B
35
IlB
15
40
F5
00
00
OA

EF
7B
05
EE
03
EE
7C
7C
EF
EE
E5

P
P
P
P
P
P
P
P

010C
010E
010F
01E1
01E3
01E6
01E8
OlEA

08
OE
OA
8B
17
41
00
OA

7C
7B
EE
EF

7B
7B
EO

7C
80
7C
7C
EF

70
02
09
EF
EF
EF
F7

717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779

jr
ugt,ba_5
!SRC > OSTI
jr
ult,ba II
!SRC < OST!
! loopl
djnz
R13,ba:6
jr
ba II
lOST> or = SRCI
Iswap source and destination operands I
ba_5:
ld
R13,bcd_LEN
linclude flag/size by tel
inc
R13
add
bcd SRC,R13
bcd-OST,R13
add
bcd-SRC
dec
ba_7:
bcd-OST
dec
ld
TEMP 1,@bcd SRC
TEMP-4,@bcd-OST
ld
@bcd-SRC,TEMP 4
ld
@bcd-OST,TEMP-1 lone byte swappedl
ld
djnz
R13,oa 7
R13,TEHP_2
ld
pop
TEMP 2
R13 push
lexchange complete I
!restore!
pop
R13
ba 4:
IR13 = OST post decimal digit count
TEMP 2 = SRC post decimal digit count
R13
TEMP 2
sub TEMP 2,R13
TEMP-2
rrc
!alignment offsetl
!digits word aligned!
nc,ba 8
jr
Irotate out least significant SRC post decimal digiti
R13,bcd_SRC
ld
! dec post dec digit II!
dec
@R13
TEMP 1
clr
call
rdr
!determine if addition or subtraction!
TEMP 4,@bcd SRC ! sign of SRCI
ba_8:
ld
TEMP-4,@bcd-OST ! sign of OSTI
xor
Iget starting addresses I
ld
R13,bcd LEN
sub
R13,TEM'Ji 2
z,ba 14 !done alreadyl
jr
add
bcd SRC,R13
bcd:OST,bcd_ LEN
add
Ireadylll
rcf
!carry = 01
TEMP 1,@bcd OST
ba 11: ld
TEMP-4,1I~80tm
ladd or sub?1
z ,ba-9
!addl
jr
TEMP-1,@bcd_SRC
sbc
jr
ba 1~
adc
TEMP 1,@bcd SRC
ba 9:
TEMP-1
ba-10: da
@bcd-OST,TEMP
1
ld
bcd 'UST
dec
bcd-SRC
dec
djnz
R13~a 11
Ipropagate carry thru ~EMP 2 bytes of OSTI
R13,TEMP_2ld
inc
Imay be zerol
R13
R13,ba_12
djnz
jr
ba 13
@bed OST,IIO
ba 12: adc
@bcd-OST
da
dec
bcd 'UST
djnz
R13-;-ba_12

1-20

-------

P 01EC FB
P
P
P
P
P
P
P
P
P

01EE
01Fl
01F4
01F7
01FA
01FC
01FF
0201
0202

E5
56
6D
E6
D8
D6
01
CF
AF

P 0203 DF
P 0204 AF
P 0205

EF 7C
7C 7F
0203'
7C 10
EF
0485'
EF

780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796

!carry propagate complete I
ba 13: jr
nc,ba 14
Idonel
!Rotate out least significant post decimal DST
digit to make room for carry at high endl
TEMP l,@bcd DST
ld
TEMP-l,II1.7Fand
z,ba-err
I no post dec digitsl
jp
TEMP-l,Ul0
ld
R13,Dcd_DST
ld
call
rdr
Idec digit cntl
@bcd_DST
dec
ba 14: rcf
ret
ba err: scf
ret
END
bcdadd

1-21

Conversion

Rout~nes

P 0205

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0205
0208
020B
020D
0210
0213
0216
0218
021A
021D
021F
0221
0224
0226
0229
022B
022E
0230
0231
0234
0236
0239
023C
023F
0241
0244
0247
0249
024B
024D
0250
0253
0255
0256
0257

E6
77
EB
E6
E5
56
02
70
24
50
7B
D6
7B
A6
6B
76
EB
DE
E5
FO
Ell
56
A6
BB
06
D6
00
6B
CA
E6
D6
8B
DF
AF

7C 2D
ED 80
03
7C 2B
ED 7E
7E 7F
CC
EC
7E EC
7E
35
03F4'
30
EC 00
22
7E 01
04
ED 7D
7D
7D 7C
7C OF
7C 09
14
7C 30
03F4'
7E
OB
DE
7C 2E
03F4'
D6

P 0257

P 0257 D6
P 025A C8
P 025C

025C'
ED

821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896

CONSTANT
bca LEN
:=
bca-SRC
:=
GLOBiL
bcddasc PROCEDURE

R12
R13

I·····················································
Purpose =
To convert a variable length BCD
string to decimal ASCII.

Input

Output

RR14

= address

of destination ASCII
string (in reg/ext/ser memory).
R13 = address of source BCD
string (in register memory).
R12 = BCD digit count / 2

ASCII string in designated
destination buffer.
Carry FLAG = 1 if input format error
or serial disabled,
= 0 if no error.
R12, R13, R14, R15 modified.
Input BCD string ummodified.

·····················································1
ENTRY
Id
tm
jr
Id
Id
and
add
push
sub
pop
jr
call
jr
cp
jr
tm
jr
inc
Id
swap
Id
and
cp
jr
add
call
dec
jr
djnz
Id
call
jr
scf
ret
bcddasc

bcd d1:

bcd d4:

bcd_d3:

bcd_d6:

TEMP 1,#'-'
@bca-SRC,U80
nz,bed d1
TEMP 1711'+'
TEMP-3,@bca SRC
TEMP-3, U7F'bca LEN,bca_LEN
bca-LEN
bca-LEN,TEMP 3
TEM'P" 3
ul t, licd d2
put dest
c,bed d2
bca Li:N,1I0
z,bed d6
TEMP J,'1
nz,bed d3
bca SR~
TEMP 2,@bca SRC
TEMP-2
TEMP-1,TEMP 2
TEMP-1,nOr
TEMP-1, '9
ugt,licd d5
TEMP 1, 71J30
put aest
TEMP 3
z,bcd d2
bca LEN, bed d4
TEMP 1,#'. ,put dest
bcd-d4

bcd d5:
bcd-d2:
ENDGLOBAL
wrdhasc PROCEDURE

Iminus sign I
I src negat i ve? I
Iyesl
I positive signl
lisolate post dec cntl
Itotal digit count I
Ipre-dec digit cntl
Itotal digit countl
Iformat errorl
ISign to dest.1
!serial error I
lany pre-dec digits?1
Ino. start with '.'1
Ineed next byte?1
Inot yet.1
lupdate pOinterl
Iget next by tel
lisolate digiti
Iverify bcdl
Ino goodl
Iconvert to ASCIII
Ito destination!
Idigit countl
I all donel
Inext digiti
Itime for dec. pt.1
Ito destinationl
Icontinuel
Iset error returnl

I·····················································
To convert a binary word to Hex ASCII.
Purpose =
Input

Note

=
=

RR12
RR14

= source binary word.
= address of destination

ASCII
string (in reg/ext/ser memory).

All other details same as for bythasc.

·····················································1
ENTRY
call
bythasc
R12,R13
Id
I fall into bythascl
wrdhasc
END

1-22

!convert R121

P 025C

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

025C
025E
0261
0263
0265
0268
026B
026E
0270
0271
02711
0276
0279
027C
027E
0280
0282
0283
02811

BO
E6
FO
C9
56
06
A6
7B
DF
76
EB
06
D6
7B
00
EB
CF
AF

7E
7D
EC
7C
7C
7C
7C
09

02
OF
30
3A

7E 01
OD
7C 07
03FII'
05
7D
DF

898
899
900
901
902
903
9011
905
906
907
908
909
910
911
912
913
9111
915
916
917
918
919
920
921
922
923
9211
925
926
927
928
929
930
931
932
933

CONSTANT
bna SRC
GLOBAL
bythasc PROCEDURE

R12

I·····················································
Purpose
To convert a binary byte to Hex ASCII.
Input =

RRlll = address of destination ASCII
string (in reg/ext/ser memory).
R12 = Source binary byte.

Output =

ASCII string in designated
destination buffer.
Carry = 1 if error (serial only).
Rll1, R15 modified.

·····················································1
ENTRY
clr
bca go: ld
bca-gol: SWAP
ld
and
ADD
cp
jr
SCF
TM
JR
ADD
skip:
call
jr
dec
jr
RCF
bca ex: ret
ENDbythasc

MODE
Iflag => binary to ASCIII
TEMP 2,112
bna 'S"RC
Ilook at next nibblel
TEMY 1, bna SRC
TEMP-l , /I~OF
lisolate low nibblel
Iconvert to ASCIII
TEMP-l , /IS 30
TEMP-l , /IS 3 A
1>9?1
ult,Skip
Inol
lin case errorl
linput is BCD? I
MODE,Il
I yes. error. I
NZ,bca ex
linput hex. adjust I
TEMP 1-; n07
put dest
Iput byte in destl
c,boa ex
lerrorl
TEMP ~
!loop till done I
nz,boa_gol
Icarry = 0: no errorl
Idonel

1-23

935
936
937
938
939
940
941
942
943
944
945
946
947
948
949

P 0284

950

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

P
P
P

0284
0286
0288
028B
028E
0290
0293
0295
0298
029B
029C
029F
02A2
02A4
02A6
02A9
02AC
02AE
02BO
02B2
02B4
02B6
02B7
02BA
02BC
02BF
02C1
02C3
02C5
02C8
02CB
02CC
02CD

BO
BO
E5
56
02
24
7B
E5
E6
EE
E5
A6
6B
FO
E4
D6
7B
00
00
EB
8B
DF
76
EB
76
6B
60
60
06
16
CF
AF

EC
ED
EE
7B
FF
7B
37
EE
7E

7B
7F
EF
7B
02

EE 7D
EF 00
12
7D
7D 7C
042C'
1E
EF
7E
EB
E2
EC
10
7B
OA
EC
ED
ED
EC

80
80

01
00

CONSTANT
bcd adr
!=
bcd-cnt
GLOBAL
b"cdwrd PROCEDURE

R14
R15

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose =

To convert a variable length BCD
string to a signed binary word. Only
pre-decimal digits are converted.

Input =

R14 = address of source BCD
string (in register memory).
R15 = BCD digit count / 2

Output

RR12 = binary word
Carry FLAG = 1 if input format error
or dest overflow,
= 0 if no error.
R14,R15 modified.

951
952
953
954 ••••••••••••••••••••••••••••••••• *••••••••••••••••••• !
955 ENTRY
clr
R12
linit destination!
956
clr
R13
957
ld
TEMP 4,@bcd adr !get sign/post length I
958
TEMP-4, fI'1,7F!isolate post Tength!
and
959
add
960
bcd cnt,bcd cnt 1/1 bcd digitsT
bcd-cnt,TEM15" 4 !# pre-dec digitsl
sub
961
jr
ult-;bcd w2 !format error!
962
TEMP 4,lbcd adr !remember signl
ld
963
TEMP-3,1I2 Id
Idigits per by tel
964
Isrc address I
bcd adr
inc
965
ld
TEM1' 2,@bcd adr !get next src by tel
966
bcd cnt,IIO !digit count = O?!
967 bcd w1: cp
jr
z,bcd w4
!conversion complete I
968
swap
Inext digitI
TEMP "2"
969
TEMP-1,TEMP 2
ld
970
bcd Din
call
laccumulate in binary I
971
jr
c,bcd w2
loverflow or format err!
972
lupdate
digit countl
dec
bcd
cnt
973
dec
Inext byte?!
974
TEM15 3
jr
Ino. same.1
nz,bcd w1
975
jr
bcd_wr
!next by tel
976
lin casel
977 bcd w4: scf
tm
R12,U80
!result > 15 bits?1
978
jr
nz,bcd w2
!overflow!
979
!source negative?!
TEMP 4-;11%80
980 bcd_w5: tm
!no. done.!
jr
z,bca w6
981
R12
com
982
com
R13
983
add
R13,1I1
984
!RR12 two's complement!
R12,110
adc
985
!carry = 01
986 bcd w6: rcf
987 bcd-w2: ret
bcdwrd
988 END-

1-24

-~--~~

P 02CD

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

02CD
02CF
02D2
02D4
02D7
02D9
02DB
02DE
02El
02E3
02E5
02E6
02ES
02EA
02ED
02EF
02Fl
02F2
02F4
02F7
02F9
02FB
02FD
02FF

Bl
76
6B
47
60
60
06
16
10
10
EE
E9
F9
04
00
Bl
EE
FA
E6
70
10
10
E8
FS

P
P
P
P
P
P
P
P
P
P
P
P

0301
0304
0307
0309
030C
030E
0310
0312
0314
0316
0318
0319

E5
15
40
F5
00
FA
50
7B
00
EB
AF

EE
EC
OD
EE
ED
EC
ED
EC
ED
EC
7C
7D
EF
7C
EE
FB
7E
7E
ED
EC
7C
7D
EE
EE
7E
7E
EE
Fl
7E
04
7E
DF

SO
SO
01
00

7E
7E
EE

990
991
992
993
994
995
996
997
99S
999
1000
1001
1002
1003
1004
1005
1006
1007
100S
1009
1010
1011
1012
1013
1014
1015
1016
1017
101S
1019
1020
1021
1022
1023
1024
1025
1026
1027
102S
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043

GLOBAL
wrdbcd

PROCEDURE

I·····················································
To convert a signed binary word
Purpose
to a variable length BCD string.
Input

Output

= address of destination BCD
string (in register memory)
RR12 = source binary word
R15 = BCD digit count / 2
R14

BCD string in destination buffer
Carry FLAG = 1 if dest overflow
= 0 if no error.
R12,R13,R14,R15 modified.

••••••••••••••••••••••••••••••••••••••••••••••••••••• !

ENTRY
clr
!init sign/post dec cntl
@bcd adr
lis input word nega~ive?
tm
R12,nSO
jr
z,wrd bO
!set result negative!
or
@bcd_adr,II%SO
com
R13
R12
com
add
R13,nl
!RR12 two's complement!
ade
R12,110
wrd bO: rle
R13
!bit 15 not magnitude!
R12
rlc
!update dest pointer!
inc
bcd adr
TEMl'"_l,bed_adr
ld
ld
TEMP 2,bcd ent !dest byte count!
add
TEMP=l, bcd=cnt
!= bed end addrl
dec
TEMP 1
@bed-adr
linitialize destl
wrd bl: elr
inc
bed adr
djnz
bed=cnt,wrd_bl
Isouree bit count!
ld
TEMP 3,1115
wrd_b3: push
TEMP=3
rle
R13
!bit 15 to carry!
R12
rle
!start at end!
bed adr,TEMP
ld
ld
bed-cnt,TEMP-2 !dest byte count I
!(dest bed string) <-- (dest-bed string • 2) + carry!
TEMP_3,@bed_adr
wrd b2: ld
adc
TEMP 3,@bed adr !. 2 + carry!
TEMP-3
da
@bed-adr,TEMP 3
ld
bed
adr
- !next two digits!
dec
bed-cnt,wrd b2 !loop for all digits I
djnz
TEM~ 3
!restore src bit ent!
pop
!dest. overflow!
jr
e,wrd ex
dec
TEMP J
!next bit!
jr
nz,wrd_b3
wrd ex: ret
ENOwrdbcd

1-25

P 0319

P
P
P
P
P
P
P
P
P
P

0319
031B
0310
031F
0322
03211
0327
0329
032C
032E

BO
BO
BO
06
7B
06
7B
A6
3B
26

7E
EC
EO
030A'
28
01100'
22
7C 39
03
7C 37

P
P
P
P
P
P
P
P
P
P
P
P
P

0331
0333
0335
0338
033B
033E
03110
03113
03116
03119
034B
034C
0340

FO
09
56
56

EO
70
EO
7C
7C
EC
EC
70
70
04

UII

FO
56
56
1111
8B
CF
AF

FO
OF
EO
FO
OF
EC

1045
1046
1047
10118
10119
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
10711
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092

GLOBAL
hascwrd PROCEOURE

I·····················································
Purpose =
To convert a variable length Hex
ASCII string to binary.
Input =

RR14 = address of source ASCII
string (in reg/ext/ser memory).

Output =

RR12 = binary word (any overflow
high order digits are truncated
without error).
Carry FLAG = 1 if input error
(serial only)
(SER flg indicates cause)
=-0 if no error
R14, R15 modified

Note =

The ASCII input string processing is
terminated with the occurrence of a
non-hex ASCII character.

·····················································1
ENTRY
clr
TEMP 3
clr
R12 linit output!
clr
R13
has c1: call
get src
!get input!
terror!
jr
c,has_ex1
call
ver asc
Iverify hex ASCII!
lend conversion!
jr
c,has ex
cp
TEMP 1,n~39
jr
ule,nas c2
sub
TEMP 1,#~37
IShift left one nibbTel
IInsert new nibble in least significant nibblel
has c2: swap
R13
Id
TEMP 2,R13
R13,1/"%FO
and
and
TEMP 1,n~OF
R13,TEMP 1
or
R12
swap
and
R12,UFO
and
TEMP 2,UOF
R12,TEMP 2
or
has_c1 jr
!loop I
!no error!
has ex: rcf
has-ex 1 : ret
ENOhascwrd

1-26

P 034D

P
P
P
P
P
P
P
P
P
P

034D
034F
0351
0354
0357
0359
035B
035E
0360
0363

CC
DC
04
D6
7B
EC
04
FC
8D

03
08
FD ED
0363'
F3
08
FD EE
03
0284'

1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132

GLOBAL
dascwrd PROCEDURE

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose

To convert a variable length decimal
ASCII string to signed binary.

In put =

RR14 = address of source ASCII
string (in reg/ext/ser memory).

Output

RR12 = binary word
R8,R9,R10,R11 holds the packed BCD
version of the result.
Carry FLAG = 1 if input error
(serial only)
(SER fIg indicates cause)
or dest overflow
= 0 if no error
R14, R15 modified

Note

The ASCII input string processing is
terminated with the occurrence of a
non-decimal ASCII character.
Decimal ASCII string may be no more
than 6 digits in length, else Carry
will be returned.
Post decimal digits are not included
in the binary result.

·····················································1
ENTRY
Id
Id
add
call
jr

Id
add
Id
jp

END

dascwrd

R12,1I3
R13,118
R13,RP
dascbcd
c,has ex1
R14,1I'B"
R14,RP
R15,113
bcdwrd

1-27
------

~~---

16 digitsl
I temp addr = I
IR8 thru R111
Iconvert to bcdl
lerrorl

!convert to binary I

P 0363

P
P
P
P
P
P
P
P
P
P

0363
0365
0367
0369
036A
036C
036E
0370
0372
0375

70
70
B1
DE
CA
B1
50
50
E6
BO

FB
ED
ED
EC
7E
7B

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0377
037A
037C
037F
0382
0384
03B7
0389
038C
038E
0391
0393
0395
0398
039A
039D
039F
03A2
03A4
03A7
03AA
03AC
03AF

D6
78
56
76
EB
A6
68
A6
EB
B7
88
5B
A6
EB
46
8B
D6
78
46
D6
EB
76
68

03DA'
41
7C 7F
7B 03
OF
7C 2B
EE
7C 2D
07
ED 80
E4
OA
7C 2E
05
7B \03
D8
OIlOD'
16
7B 01
0463'
09
7B 02
C6

EC
ED
ED

1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197

CONSTANT
dab LEN
:=
dab-DST
GLOBAL
dascbcd PROCEDURE

R12
R13

I·····················································
Purpose
To convert a variable length decimal
ASCII string to BCD.

Input =

R13 = address of destination BCD
string (in register memory).
RR14 = address of source ASCII
string (in reg/ext/ser memory).
R12 = BCD digit count / 2

Output =

BCD string in designated destination
buffer (any overflow high order
digits are truncated without error).
Carry FLAG = 1 if input error
(serial only)
(SER fIg indicates cause)
or overflow
R14, R15 modified.

Note =

The ASCII input string processing is
terminated with the occurrence of a
non-decimal ASCII character.

·····················································1
ENTRY

push
push
das_g1: clr
inc
djnz
clr
pop
pop
ld
clr

dab LEN
dab-DST
@dab DST
dab UST
dab-LEN,das g1
@dao DST
dab OST
dab-LEN
TEMlS 3,'1
TEMP:4

das_g2: call
jr
and
tm
jr
cp
jr
cp
jr
xor
jr
das g5: jr
das:g4: cp
jr
or
jr
das_g6: call
jr
or
call
jr
tm
jr

get src
c,dab ex1
TEMP 1,U7F
TEMP-4,U03
nz,das g5
TEMP 1-;-11'+'
z,das g2
TEMP 1,11'-'
nz,das g4
@dab D'ST, U80
das g2
mi,das g6
TEMP 1";"# I.'
nz,d'is g6
TEMP 4";"U03
das_g2
ver asc
c,d'ib ex
TEMP ii,U01
rdl nz,das g7
TEMP 4-;-U02
z,das_g2

1-28

Isavel
!init. destination I
I init.1
Irestorel
Ifor ver asc I
Ibit o => digit seen;
bit 1 => dec pt seen;
bit 7 => overflowl
Iget input by tel
I serial error I
17-bit ASCIII
!check status I
ISign char not valid I
I posi tive? I
Iyes. no affectl
Inegative?1
I not sign char I
Icomplement signl
Iget next inputl
Idec pt has been seenl
lis char dec pt?1
Inope.1
Idec pt and digit seenl
Iget next inputl
lis bcd digit?1
lend conversion.1
Idigit seenl
Inew digit to destl
loverflowl
Ipost dec digit?1
Ino. get next inputl

P
P
P
P

21
8B
46
8B

ED
C2
7B
BD

P 03BA E4
P 03BD AF
P 03BE

03Bl
03B3
03B5
03B8

P 03BE

P
P
P
P
P
P
P
P
P
P
P
P
P

03BE
03CO
03C2
03C4
03C7
03C9
03CC
03CE
03DO
03D2
03D4
03D7
03DA

70
70
EC
04
FC
D6
50
50
CC
DC
04
8D

EF
08
FD EE
03
02CD'
EF
EE
03
08
FD ED
0205'

1198
1199
1200
1201
1202
1203
1204
1205
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235

inc
jr
das_g7: or
jr

@dab DST
das g2
TEMP 4, U80
das_g2

dab ex: ld
FLAGS,TEMP_4
dab-exl: ret
ENDdascbcd

linc
Iget
Iset
!get

post dec cntl
next inputl
overflow I
next inputl

!carry

or 11

GLOBAL
wrddasc PROCEDURE

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose

To convert a signed binary word to
decimal ASCII

Input

RR12
RR14

Output

= source binary word.
= address of dest (in

reg/ext/ser

memory) .

Decimal ASCII in dest buffer.
R8,R9,Rl0,Rll holds the packed BCD
version of the result.
R12, R13, R14, R15 modified.

·····················································1
ENTRY

END

push
push
ld
add
ld
call
pop
pop
ld
ld
add
jp
wrddasc

R14
R15
R14,118
R14,RP
R15,113
wrdbcd
R15
R14
R12,113
R13,118
R13,RP
bcddasc

1-29

!save dest addrl
!R8,9,10 & 11 tempi
!temp byte length!
Iconvert input wordl
!restore dest addr!
!length of temp!
! addr of temp!
!convert to ASCII!

P 03DA

P
P
P
P

P
P
P
P
P
P
P
P
P
P

03DA
03DB
03DC
03DE
03DF
03E1
03E4
03E6
03E8
03EA
03EC
03EE
03EF
03F2
03F3
03F4

CF
EE
EA
FE
FA
80
70
82
B9
50
AO

AF
E5
FE
AF

06
OE
0000'
EB
BE
7C
EB
EE
EF

P 03F4

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

03F4
03F5
03F7
03F8
03FA
03FD
03FF
0401
0403
0405
0407
0408
040B
040C
0400

EE
EA
FE
FA
80
70
B8
q2
50
AO
AF
F5
FE
AF

06
OE
0000'
EB
7C
BE
EB
EE
7C

1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289

GLOBAL
!for PART II onlyl
get src PROCEDURE

I··T ••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose

Output

To get source byte from
reg/ext/ser memory into TEMP_1.
Carry FLAG

if error (serial)

0 i f all ok

TEMP 1 = source byte.
RR14-updated.

··················*··**···*··························1
ENTRY

END

rcf
inc
djnz
inc
djnz
jp
push
Ide
ld
pop
incw
ret
ld
inc
ret
get_src

GLOBAL
put dest

R14
R14,get s1
R15
R15,get s2
ser getR11R11,@RR14
TEMP 1, R11
R11 RR14

Iset good return codel
Itest R14 = 01
Isrc in ext memoryl
Itest R15 = 01
!src in reg memoryl
Isrc in ser memoryl
Isave user'sl
!get by tel
!move to commonl
!restore user'sl
! update src ptr I

TEMP 1,@R15
R15 -

Iget by tel
!update src ptrl

!for PART I I only!
PROCEDURE

! •• T.* •••••••••••••••••••••••••••••••••• ~ •••••••••••••

Purpose
Output

To store destination byte from TEMP 1
into reg/ext/ser memory

RR14 updated.

·····················································1
ENTRY

END

inc
R14
R14,put s1
djnz
R15
inc
djnz
R15,put s2
jp
ser output
R11push
Id
R11,TEMP 1
@RR14,R1T
Ide
pop
R11
RR14
incw
ret
@R15,TEMP
Id
R15
inc
ret
put_dest

1-30

Itest
Idest
I test
Idest
!dest
Isave

R14 = 01
in ext memoryl
R15 = 0 I
in reg memory!
in ser memoryl
user'sl

Irestore user'sl

P 0400

P
P
P
P
P
P
P
P
P
P
P

0400
0410
0413
0415
0418
041A
0410
041F
0422
0425
0427

56
A6
7B
A6
7B
76
EB
56
A6
7B
A6

7C
7C
16
7C
10
7E
OB
7C
7C
04
7C

7F
30
3A
01
OF
41
47

P 042A EF
P 042B AF
P 042C
P 042C

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

042C
042F
0432
0434
0436
0438
043A
043C
043E
0440
0442
0444
0446
0448
044A
0440
0450
0452
0454
0457
0459
045C

56
A6
BB
02
12
7B
70
70
02
12
7B
02
12
7B
04
16
7B
50
04
50
14
AF

7C
7C
20
00
CC
27
EC
EO
00
CC
19
00
CC
13
7C
EC
OB
7C
7C
7C
7C

P
P
P
P
P

0450
045F
0461
0462
0463

50
50
OF
AF

7C
7C

OF
09

EO
00
EO
EC

1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361

CONSTANT
MOOE
TEMP 3
:=
TEMP-l
char
INTERNAL
ver asc PROCEOURE
I··T ••••••••••••••••••••••••••••••••••••••••••••••••••
Purpose
To verify input character as valid
hex or decimal ASCII.

Input

TEMP 1 = 8-bit input
TEMP=3 = 0 => test for hex,
1 => test for decimal

Output =

Carry FLAG = 0 if no error
1 if error.

·····················································1
ENTRY
and
cp
jr
cp
jr
tm
jr
and
cp
jr
cp

ver ok:
ver erc: ccf
ver-err: ret
ENOver asc

char,II'f,7F
17-bit ASCII I
!range start: '0' !
char,II'O'
ult,ver err
Ino good!
!dec range end: '9' !
char, II '9' +1
ult,ver ok
I all' s we 111
MOOE,111Idec or hex?!
nZ,ver erc
Ino goodl
char,UtNOT('a'-'A') linsure upper case!
Icheck A-F range!
char, II' A'
!no goodl
ult,ver err
char ,11'1="+1
lend hex range!
Icomplement carry I

INTERNAL
bcd bin PROCEOURE
! ••T••••••••••••••••••••••••••••••••••••••••••••••••••
Purpose =
To convert next bcd digit to binary.
Input =

TEMP 1 = digit

Output =

RR12 = RR12 • 10 + digit

·····················································1
ENTRY
and
cp
jr
add
adc
jr
push
push
add
adc
jr
add
adc
jr
add
adc
jr
pop
add
pop
adc
ret

TEMP 1, II'f,OF
TEMP-l ,119
ugt,ocd bl
R13,R13R12,R12
c,bcd bl
R12 R13
R13,R13
R12,R12
c,bcd b2
R13,RT3
R12,R12
c,bcd b2
R13,TEMP
R12,110 c ,bcd b2
TEMP T
R13,TEMP 1
TEMP 1 R12,TEMP_l

TEMP 1
bcd b2: pop
TEMP-l
pop
bcd b 1 : scf
ret
bcd bin
ENO

1-31

!isolate digitI
!verify validl
lerrorl
12xl
!overflow!

!4xl
loverflow!
! 8x!
!overflow!
18x + dl
!overflow!

! lOx + d!

!restore stack!
!errorl

P 0463

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0463
0465
0467
0469
046C
046F
0472
0475
0478
047B
047D
047F
0482
0484
0485

70
02
Fl
E5
57
56
45
F5
E4
00
CA
56
50
AF

EC
DC
ED
ED
ED
7C
ED
7C
7D
ED
E8
7C
EC

7D
FO
OF
7C
ED
7C
OF

P 0485

P
P
P
P
P
P
P
P
P
P
P
P
P

0485
0487
0488
048A
048D
0490
0493
0496
0499
049G
049E
04AO
04Al

70
DE
Fl
E5
57
56
45
F5
E4
CA
50
AF

EG
ED
ED
ED
7G
ED
7G
7E
E9
EC

7E
OF
FO
7G
ED
7G

1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396
1397
1398

CONSTANT
s len
:=
s-adr
INTERNAL
rdl
PROCEDURE

1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423
1424
1425
1426
1427
1428

INTERNAL
PROCEDURE
rdr

R12
R13

1**'***································**··****···*···
Rotate Digit Left
Input

Output

=
=

R12 = BCD string length
R13 = BCD string address
TEMP 1 bit 3-0 = new digit
BCD string rotated left one digit·
new digit inserted in units position.
TEMP_l bit 3-0 = digit rotated out
of high order digit position
bit 7-4 = 0
Zero FLAG = 1 if TEMP_l <> 0
R12, R13 unmodified

"""""'*"'*"*"""""*"'***"***""'*"""1
ENTRY
push
add
rdl 01: swap
ld
and
and
or
ld
ld
dec
djnz
and
pop
ret
rdl
END
! •••

s len
s-adr,s len
@s adr TEMP 2,@s adr
@s aar,UF"O
TEMP 1,UOF
TEMP:l,@s_adr
@s adr,TEMP 1
TERP 1, TEMP:2
s adr
s-len,rdl 01
tEMP 1,UDF
s len

!address of units placel
!isolate digit!
lisolate new digiti
I save new byte I
!back-up pointer!
!loop till done!
fold high order digiti
!restore R12!

,.* ••••• *,.""", •••• "" •••• *, •• ,.*, ••••••• *••••

Rotate Digit Right
Input

Output

=
=

R12 = BCD string length
R13 = BCD string address
TEMP_l bit 7-4 = new digit
BCD string rotated right one digit;
new digit inserted in high order
position.
R12 unmodified
R13 mOdified

*•••••• •••••• *•• ** ••• ·.*··*··*····***···*·····,'··*"1
ENTRY

push
rdr 01: inc
swap
ld
and
and
or
ld
ld
djnz
pop
ret
rdr
END

s len
s-adr
@s adr
TEMP 3,@s adr
@s aar,/I%1iF
TEMP 1, U'f,FO
TEMP:l,@s_adr
@s adr,TEMP 1
TEHp _1, TEMP=3
s len,rdr 01
s-len

1-32

!isolate digit!
lisolate new digiti
! save new byte!
Iloop till done!
!restore R12!

B1t Man1pulation Rout1nes

P 04A1

P 04A1 E6

04A4
04A6
04A8
04AA
04AC
04AE
04BO

BO
90
90
FB
EO
90
10

7C
7D
EC
ED
06
EC
EC
7D

P
P
P
P
P

04B2
04B4
0486
04B8
04B9

00
EB
C8
AF

7C
FO
7D

P
P
P

P
P

1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497

CONSTANT
tjm bits
tjm-mask

R12
R13

GLOBAL

PROCEDURE
,....................................................
.

clb

Purpose

Input

Output

To collect selected bits in a byte
into adjacent bits in the low order
end of the byte. Upper bits in byte
are set to zero.
R12
R13

Note =

R12

input byte
mask. Bit = 1 => corresponding
input bit is selected.

= collected

bits

For example:
Input: R12
R13

%(2)01110110
%(2)10000101

Output : R12

= %(2)00000010

••••••••••••••••••••••••••••••••••••••••••••••••••••• !

ENTRY
ld
clr
next 1 : rl
rl
jr
rr
rl
rlc
no select:
dec
jr
ld
ret
END
clb

TEMP 1 ,118
TEMP-2
tjm bits
tjm:mask
nC,no select
tjm_blts
tjm bits
TEMlf 2
TEMP 1
nz,next1
R12,TEMP_2

1-33

!bit count!
!bits collected herel
!bit 7 to bit O!
!bit 7 to carry!
!don't use this bit!
!bit 7 to 0 and carry!
! collect source bit!
Irepeat!

P 0llB9

P
P
P
P
P
P
P
P
P

0llB9
OIlBC
OUBE
0llC1
0llC3
0llC6
0llC8
OIlCA
OIlCC

06
02
16
02
16
C2
AO
C2
E8

P OIlCE 30

OIlA l'
CC
EE 00
FC
EE 00
DE
EE
FE
ED
EE

P 01100

11199
1500
1501
1502
1503
15011
1505
1506
1507
1508
1509
1510
1511
1512
1513
15111
1515
1516
1517
1518
1519
1520
1521
1522
1523
15211
1525
1526
1527
1528
1529
1530
1531
1532
1533
15311
1535
1536

CONSTANT
tjm tabh
=
tjm-tabl
=
tjm-tab
=
GLOBAL
tjm
PROCEDURE

R111
R15
RR14

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose

Input =

To take a jump to a routine address
determined by the state of selected
bits in a source byte. A bit
is 'selected' by a one in the
corresponding position of a mask.
The 'selected' bits are packed into
adjacent bits in the low order end of
the byte. This value is then doubled,
and used as an index into the jump
table.
RR111 = address of jump table in
program memory.
R12 = input data
R13 = mask

·····················································1

ENTRY

call
add
adc
add
adc
ldc
incw
ldc
ld

clb
!collect selected bitsl
tjm bits,tjm bits Icollected bits • 21
tjm-tabh,IO lin case carry I
tjm-tabl,tjm bits
tjm-tabh,IO Itjm tab pOints to ••• 1
tjm-mask,@tjm tab 1.7.table entryl
tjm-tab
tjm-tabl,@tjm tab Iget table entry ••• !
tjm=tabh,tjm_mask I ••• into tjm_tab!
Ibyel

jp
END
tjm
END PART I

o errors
Assembly complete

1-34

ROMLESS Z8 SUBROUTINE LIBRARY PART II
Z8ASM
LOC

3.02
OBJ CODE

STMT SOURCE STATEMENT
1

3 PART II MODULE
4
5
6 !'ROMLESS Z8'

SUBROUTINE LIBRARY

PART II

7 I

9
10
11
12
13
14
15

CONSTANT
IRegister Usagel
RAM START

P3M save
TEMP 3
TEMP-2
TEMP-1
TEMP-4

RAM START
P3M-save-1
TEM"F 3-1
TEMP-2-1
TEMP-1-1

16
:=
17
18
19
20 IThe following registers are modified/referenced
21 by the Serial Routines ONLY. They are
22 available as general registers to the user
23 who does not intend to make use of the
24 Serial Routines!
25

26
27
28
29
30
31
32
33
34
35
36
37
38

40
41
42
43
44

SER char
.TEMP 4-1
SER-tmp2
:=
SER char-1
SER-tmp1
.SER-tmp2-1
SER-put
'SER-tmp1-1
SER-len
.SER-put-1
SER-buf
._
SER-len-2
SER-imr
:=
SER-buf-1
._
SER-imr-1
SER-cfg
! Serial Configuration Data =1 => odd parity on
bit 7
bit 6 : =1 => even parity on
(bit 6,7 = 11 => undefined)
undefined
bit 5
bit 4
undefined
bit 3
=1 => input editting on
=1 => auto line feed enabled
bit 2
bit 1
=1 => BREAK detection enabled
=1 => input echo on
bit 0

45 op

46 ep
47 ie
118 al
49 be
50 ec
51 SER get
52 SER-flg
53 !Serial
54 bit 7
55 bit 6
56 bit 5
bit 4
~~ bit 3
59 bit 2
60 bit 1
61 bit 0
62 I
63 sd
64 pe
65 bd
66 bo
67 bne
68 bf
69

···: -=
··-

J80
J40
J08
J04
J02
J01

..Flags

SER cfg-1
SER::::get-1

Status
=1 => serial I/O disabled
undefined
undefined
=1 => parity error
=1 => BREAK detected
=1 => input buffer overflow
=1 => input buffer not empty
=1 => input buffer full

:=
:=

·:::··-

J80
J10
J08
J04
J02
J01

1-35

RAM_START-%10
70 RAM TMR
71
SER flg-l
72 SERI time
SERltime-l
73 SERhtime
74
75 IThe following registers are modified/referenced
76 by the Timer/Counter Routines ONLY. They are
77 available as general registers to the user
78 who does not intend to make use of the
79 Timer/Counter Routines!
80
81

TOO tic

82 TOO-imr

RAM TMR-2
TOO-tic-l
TOO-imr-l
TOOnr-l
TODmin-l
TOO-sec-l
TOO-tt-l
PLS-l-l
PLS-tmr-l

TOO-hr
TOO-min
TOO-sec
TOO-tt
87 PLS-l
88 PLS-tmr
89 PLS-2
90
91 RAM END
PLS 2
92 STACK
RA~ENO
93
94 IEquivalent working register equates
95 for above register layout!
96
97 !register file %70 - %7FI
._
%70
I for SRP!
98 RAM STARTr

83
84
85
86

100
101
102
103
104
105
106
107
108

109
110
111
112
113
114
115
116
117
118

rP3Msave
rTEMP 3
rTEMP-2
rTEMP-l
rrTEMP 1
rTEMP 1h
rTEMP-n
rTEMP-4
rSERcnar
rSERtmp2
rSERtmpl
rrSERtmp
rSERtmpl
rSERtmph
rSERput
rSERlen
rrSERbuf
rSERbufh
rSERbufl
rSERimr
rSERcfg
rSERget
rSERflg

R15
R14
R13
R12
RR12
R12

R13

R 11

Rl0
R9
R8
RR8
R9
R8
R7
R6
RR4
R4
R5

119
R3
120
R2
:=
121
R1
122
RO
123
124
125 Iregister file %60 - %6F!
'f26 RAM TMRr
%60
:=
127 rTO'Dtic
R13
:=
128 rTOOimr
R12
:=
129 rTOOhr
Rll
130 rTODmin
Rl0
131 rTOOsec
R9
132 rTOOtt
R8
:=
133 rPLS 1
:=
R7
134 rPLStmr
R6
:=
135 rPLS_2
R5

137 EXTERNAL
get src
PROCEDURE
139 put-dest
PROCEDURE
140 multiply
PROCEDURE
141
$SECTION PROGRAM

138

1-36

I for SRP!

Serial Routl.nes

P 0000

P
P
P
P
P
P
P
P
P

0000
0001
0003
0005
0007
0009
OOOB
0000
OOOF

EE
EA
EC
FC
BC
DC
C3
DA
56

04
00·
51·
72
05
BE
FC
73 F7

164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227

CONSTANT
si PTR
sCTMPl
sCTMP2
GLOBAL
ser init

RR14
R11
R13
PROCEDURE

! ••T ••••••••••••••••••••••••••••••••••••••••••••••••••

serial initialize
Purpose =

To initialize the serial channel and
RAM flags for serial I/O. Serial
input occurs under interrupt control.
Serial output occurs in a polled mode.

Input =

RR14

= address

byte
byte
word
byte
byte
byte

of parameter list in
program memory (if R14 = 0,
use defaults):
= Serial Configuration Data
(see definition of SER cfg)
= IMR mask for nestable
interrupts
= address of circular input
buffer (in reg/ext memory)
= Length of input buffer
= Baud rate counter value
= Baud rate prescaler value
(un shifted )

Output

Serial I/O operations initialized.
R11, R12, R1 3, R1 4, R15 modified.

Note =

Defaults:
In put echo on
Input editting on
BREAK detection enabled
No parity
Auto line feed on
Input Buffer Address = SER char
Input buffer length = 1 byte
Baud Rate = 9600 (assuming
XTAL = 7.3728 MHz)
The instruction at %0809 must result
in a jump to the jump table entry for
ser _input.
If BREAK detection is disabled, and a
BREAK occurs, it will be received as a
continuous string of null characters.
The parameter list is not referenced
following initialization.

••••••••••••••••••••••••••••••••••••••••••••••••••••• !

ENTRY

si 1:
si 2:

inc
djnz
ld
ld
ld
ld
ldci
djnz
and

R14
fuse defaults?!
R14,si 1
!no. given by caller.!
R14,UHI ser def !address of default ••. !
R15,ULO ser-def ! .•• parameter list. !
si TMP1, IISEl" cfg
sCTMP2,115 @sT TMP1,@Si PTR !get initialization ••• !
si TMP2,si 2! ••. parameters!
SER_imr,U%F7
!insure no self-nesting!

1- 37

P
P
P
P
P
P

0012
0015
0017
001A
0010
0020
0023

56
B8
56
46
56
44
E4

P
P
P
P
P
P
P
P
P
P
P

0026
0028
002A
002C
002E
0031
0033
0035
0037
0038
003A

BC
C2
C3
C2
06
C9
09
90
OF
10
B9

F4
DE
BE
BE
DODO·
6E
6F
EB
EB
F5

P
P
P
P

003C
0030
003F
0041

8F
BO
BO
BO

71
77
70

P
P
P
P

0043
0046
0049
004C

56
56
46
9F

FA
FB
FB

E7
EF
08

P 0040 46
P 0050 AF
P 0051

EB
EB
7F
EB
7F

P 0051 OF 00
P 0053 007A 01
P 0056 02 03

80
40
3F
7F
F7

228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273

linitialize Port 3 Mode Register for serial I/O!
!disable TOI
TMR,II%FC
AND
ld
si TMP1, SER cfg Iconfiguration data!
lodd parity select I
AND
sCTMP 1,11%80
OR
si-TMP1,11%40
!P30/7 = Sin/Soutl
!mask
off old settings I
AND
P3R save,/I%3F
OR
P3~save,si TMPl Inew selection!
P3M~P3M_save
Ito write-only registerl
LD
! initialize TOI
ld
ldc
ldci
ldc
call
ld
ld
rl
scf
rIc
ld
linitialize RAM
01
clr
clr
clr

si TMP1, liTO
si-TMP2,@si PTR Isave counter!
@sT TMP1,@sT PTR linit counterl
si YMP1,@si ~TR Iget prescalerl
multiply
!TO x PREOI
!save for BREAK ••. !
SERhtime,R12
SERltime,R13
I ••• detection
si TMPl
! SHL 11
!continuous mode!
s i TMP 1
! SHL 21
PRt:O,si TMPl
flags and pointers!
Idisable interrupts!
!input buffer ••• 1
SER_get
SER put
I •.• empty!
Ino errorsl
SER=flg

! initialize interrupts I
AND
IRQ,II%E7
and
IMR,II%EF
or
IMR,1I%08
EI
!go!
or
TMR,II%03
ret
END
ser init

Iclear IRQ3 & 41
Idisable IRQ4 (xmt)1
lenable IRQ3 (rcv)1
Iload/enable TOI

! De faul ts for serial initializationl
ser def RECORD

[cfg

- , imr-

buf
len -

- , ctr_, pre_

BYTE
WORD
BYTE]

[ec+al+ie+be, %00, SER_char, 1 , %02, %03]

1-38

P 0058

275 CONSTANT
276 rli len
277 GLOBAL
278 ser rlin
279
280 read line
281
282 Purpose =
283
284
285
286 Input =
287
288
289
290 Output
291
292
293
294
295
296
297 Note =
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327 ENTRY
clr
328
329 ser read:
push
330
push
331
push
332
333 rli 4: call
jr
334
tm
335
jr
336
tm
337
jr
338

R13

PROCEDURE

I··y··················································
To return input from serial channel
up to 'carriage return' character or
maximum length requested or BREAK.
RR14 = address of destination buffer
(in reg/ext memory)
R13 = maximum length
Input characters is destination buffer.
RR14 = unmodified
R13 = length returned
Carry Flag = 1 if any error,
= 0 if no error.
R12 indicates read status
1. Return will be made to the calling
program only after the requisite
characters have been received from
the serial line.
2. If input editting is enabled, a
'backspace' character will cause
the previous character (if any) in the
the destination buffer to be deleted;
a 'delete' character will cause all
previous characters (if any) 1n the
destination buffer to be deleted.
3. If parity (odd or even) is enabled,
the parity error flag (R14) will be set
if any character returned had a parity
error. (Bit 7 of each character may
then be examined if it is desirable to
know which character(s) had the error).
4. The status flags 'BREAK detected',
'parity error', and 'input buffer
overflow' will be returned
as part of R12, but will be cleared in
SER_stat.
5. The staus flags: 'input buffer full'
and 'input buffer not empty' will be
updated in SER stat •

..............................T······················I

P 0058 BO

P
P
P
P
P
P
P
P
P

EE
EF
ED
0170'
48
72 CO
08
7C 80
03

005A
005C
005E
0060
0063
0065
0068
006A
006D

70
70
70
D6
7B
76
6B
76
6B

TEMP_3

!flag => read linel

R14
!save original •.• 1
I ••• dest. pointerl
R15
rli len
I ••• and length I
ser-get
Iget input character I
c ,rli 3
lerrorl
SER cTg,lIop LOR ep Iparity enabled?1
z,rTi 1
Inol
Iparity error?1
TEMP .." U80
z,rlI_1
Inol

1-39

P
P
P
P
P
P
P

006F
0072
0075
0078
007A
007D
0080

46
D6
A6
EB
56
76
6B

70 10
0000·
7E 00
31
7C 7F
72 08
21

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0082
0085
0087
008A
008C
008E
0090
0093
0095
0096
0099
009A
009C
009E
OOA 1

A6
6B
A6
EB
50
70
A4
6B
DE
26
EE
EA
8B
36
8B

7C
3E
7C
17
7C
7C
ED
30

P
P
P
P
P
P
P
P
P
P

00A3
00A5
00A8
OOAA
OOAB
OOAD
OOAF
00B2
00B4
00B6

00
A6
6B
DE
DA
50
24
DB
CB
56

P
P
P
P
P
P
P

00B9
OOBA
OOBD
OOBF
OOCO
00C2
00C4

CF
76
6B
DF
50
50
AF

P
P
P
P
P

00C5
00C7
00C9
OOCB
OOCD

50
50
50
8B

7F
08

02
C2
EE
BD

ED
7C
03

B3
7C
ED
7C
70
70
EC
01

7C
E3
9C

EF
EE
ED
EF
EE
8D

P OOCD

P OOCD E6
P OODO 8B
P 00D2

7E
88

339
340
3111
342
343
31111
3115
3116
347
348
349
350
351
352
353
3511
355
356
357
358
359
360
361
362
363
3611
365
366
367
368
369
370
371
372
373
3711
375
376
377
378
379
380
381
382
3B3
384
385
386
388
389
390
391
392
393
3911
395
396
397
398
399
1100
1101
402
403
11011

or
SER flg,Hpe
call
put-dest
cp
TEM1 3,10
jr
nz,rl"i 2
and
TEMP 1~1~7F
tm
SER cfg,Hie
jr
z,rl"i 9
linput edittingl
cp
TEMP 1,H~7F
jr
z,rlT 6
TEMP 1,H~OB
cp
jr
nz,rli 9
pop
TEMP 1push
TEMP-l
cp
TEMP-l,rli len
jr
eq,rl"i 6 inc
rli Ieii'
sub
R15~H2
inc
R14
djnz
Rll1,rli 7
jr
rli II rli_7: sbc
R14~HO
jr
rli II
rli 1:

rli_9:

rli 2:
rli=3:

rli_5:

rli 6:

END

dec
cp
jr
inc
djnz
pop
sub
ld
ld
and
rcf
tm
jr
scf
pop
pop
ret

!char = delete?1
Iyes!
Ichar = backspace?1
!no. continue I
Iget original lengthl
lany characters?!
Inonel
!undo last decrementl
Ibackspace & previous I
Ireg or ext mem?1
lext!
Iregl

rli len
lin case crl
TEMP 1,#~OD
Icarriage return?1
z,rlT 3
lend inputl
rli len
Irestorel
rli-Ien,rli II
Iloop for max lengthl
TEMV 1
loriginal length!
TEMP-1,rli len 1# chars returned I
rli l"en,TERp 1 Itell caller I
R12~SER fIg Ireturn read status I
SER flg~HLNOT (pe LOR bd LOR bo)
Ireset for next timel
Igood return codel
R12,Hpe LOR bd LOR bo LOR sd
z,rli_5
Ino error I
!set error return I
R15
R14
loriginal buffer addr!

pop
rli len
pop
R15pop
R111
jr
ser read
ser rlin

GLOBAL
ser rabs

Iyes. set error flagl
Istore in bufferl
I read line?!
Inol
!ignore parity bit!
!input editting on?1
Ino .1

Istart overt

PROCEDURE

I··~··················································

read absolute
Purpose

To return input from serial channel
of maximum length requested. (Input
is not terminated with the receipt of
a 'carriage return'. BREAK will
terminate read.)

.................................................T···I
Note =

ENTRY
END

All other details are as for 'ser rlin'.

ld
TEMP 3,#1
jr
ser read
ser rabs

1-40

Iflag => read absolutel

P 0002

406 GLOBAL
PROCEDURE
407 ser input
408 ! ••*••••••••••••••••••••••••••••••••••••••••••••••••••
409 Interrupt service - Serial Input
410
411 Purpose =
To service IRQ3 by inputting current
character into next available position
412
in circular buffer.
413
414
None.
415 In put =
416
New character inserted in buffer.
417 Output
SER stat, SER_put updated.
418
419
420 Note =
1. If even parity enabled, the software
replaces the eigth data bit with a
421
parity error flag.
422
423
424
2. If BREAK detection is enabled, and
the received character is null,
425
the serial input line is monitored to
426
detect a potential BREAK condition.
427
BREAK is defined as a zero start bit
428
followed by 8 zero data bits and a
429
zero
stop bit.
430
431
3. If 'buffer full' on entry, 'input
432
buffer overflow' is flagged.
433
434
4. If input echo is on, the character is
435
immediately sent to the output serial
436
channel.
437
438
5. IMR is modified to allow selected
439
nested interrupts (see ser init).
440
441
442 ENTRY
Iread stop bit levell
ld
SER tmp1,~03
443
imr!save entry imrl
444
push
imr,SER_imr
! allow nesting I
445
and
ei
446
push
rp
! save user's!
447
IIRAM STARTr
srp
448
ld
rSERchar,SIO
Icapture inputl
449
!break detect enabled?1
tm
rSERcfg,llbe
450
jr
!nope .1
451
z,ser 30
r SERtiiip2
clr
452
tm
rSERcfg ,llop
todd parity enabled?1
453
!no .1
jr
z,ser 23
454
r SERtiiip2, 11%80
ld
455
rSERchar,rSERtmp2 18 received bits = O? 1
456 ser_23: cp
jr
ne,ser 30
!no!
457
rSERtmp1,#1
Itest stop bitl
tm
458
jr
nZ,ser 30
!not BREAK I
459
460 lis BREAK. Wait for markingl
rSERflg,#bd
!set BREAK flagl
461
or
~03,#1
Imarking yet?1
462 ser 24: tm
jr
z,ser 24
Inot yetI
463
464 !wait 1 char time to Tlush receive shift register!
465
push
SERhtime
1save PREO x TO I
push
SERltime
466
467 in loop: ld
rSERtmp1, #53
!delay
640 cyclesl
djnz
rSERtmp1,lp1
468 lpl:
469
decw
SERhtime

··········································*··········1

P 0002 E4
P 0005 70

P 0007 54

P OODA 9F

P
P
P
P

78
FB

70
31
A8
76
6B
BO
76
6B
9C
A2
EB
76
EB

FD
70
FO
E2
2F
E9
E2
02
80
A9
22
E8
10

P 00F8 46
P OOFB 76
P OOFE 6B

EO
03
FB

08
01

P 0100 70
P 0102 70
P 0104 BC
P 0106 BA
P 0108 80

6E
6F
35
FE
6E

P
P
P
P
P
P
P

P
P

OODB
0000
OODF
00E1
00E4
00E6
00E8
OOEB
OOED
OOEF
00F1
00F3
00F6

03
FB
73

1-41

P 010A EB

P
P
P
P

010C
010E
0110
0113

50
50
56
8B

6F
6E
FA
49

P
P
P
P
P
P
P
P
P
P

0115
0118
011A
011D
011F
0121
0124
0126
0129
012C

76
EB
76
6B
A9
66
EB
56
76
6B

EO
4A
E2
OA
FO
FA
FB
FA
E2
14

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

012E
0130
0132
0134
0137
0139
013C
013E
0140
0142
0144
0146
0148
0149
014B
014D
0150
0151
0153
0155
0157
0159
015B
015E
0160
0161
0163

8C
BO
CO
16
8A
56
B2
CO
CO
88
98
02
8E
8A
F3
46
7E
A2
EB
BO
A2
EB
46
50
BF
50
BF

07
E9
EA
E9
F9
E9
A9
EA
EA
E4
E5
97

P 0164 46
P 0167 8B

EO
F5

P
P
P
P

E8
A8
DD

0169 16
016C 92
016E 8B
0170

1E
9A
EO
76
02
E7
71
03
EO
FD

F7
01
01
10
EF
40

00
01

470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523

nz ,in_loop

pop
pop
and
jr

SERltime
SERhtime
IRQ,IILNOT
ser_i5

! delay (128x10xPREOxTO)1
I
----------------1
I
2
I
~08

I restore PREO x TOI
Iclear int reql
Ibyel

ser_30: tm
rSERflg,lIbf
I buffer full? I
jr
nZ,ser i1
Iyes.overflowl
tm
rSERc fg, /lec
!echo on?1
jr
Inol
z,ser iO
ld
SIO,r"SERchar
lechol
I poll I
ser i6: tcm
IRQ,/lJ10
jr
nZ,ser i6
!loop I
Iclear Irq bitl
and
IRQ,/lLllOT ~10
ser iO: tm
rSERcfg ,ilep
leven parity?1
Ino parityl
jr
z,ser 22
Icalculate parity error flagl
rSERtmp1,/17
ld
clr
rSERtmp2
Icount 1 's herel
rrc
rSERchar
Ibit to carry I
ser_20:
adc
rSERtmp2,aO
lupdate 1's countl
djnz
r SERtmp 1 ,ser 20 Iloop till donel
and
rSERtmp2,a1 11's count even or odd?1
rSERchar,rSERtmp2
xor
rrc
rSERchar
Iparity error flag ••• 1
rrc
rSERchar
t. .. to bit 71
ser 22: ld
rSERtmph,rSERbufh
rSERtmpl,rSERbufl
ld
add
rSERtmpl,rSERput Inext char address I
!in external memory?1
inc
rSERtmph
djnz
rSERtmph,ser i2 lyes.1
@rSERtmpl,rS~Rchar Istore char in bufl
ld
ser_i 3: or
rSERflg ,lIbne
Ibuffer not emptyl
inc
rSERput
lupdate put ptrl
cp
rSERput,rSERlen Iwrap-around?1
jr
Ino!
ne,ser i4
clr
rSERpu"E"
Iset to startl
ser i4: cp
rSERput,rSERget lif equal, then full I
jr
ne,ser i5
r SE Rflg, IIbf
or
ser_i5: pop
rp
Irestore user'sl
di
pop
imr
Irestore entry imrl
iret
ser 11: or
jr

rSERflg ,abo
ser_i5

Ibuffer overflowl

rSERtmph,IIO
ser 12: adc
lde
@rrSERtmp,rSERchar I store in bufl
jr
ser_i 3
END
ser _input

1-42

------

----~~--

P 0170

P
P
P
P

0170
0172
0174
0175

70
31
DF
76

FD
70

P
P
P
P
P
P
P
P
P

0178
017A
017D
017F
0181
0183
0184
0186
0187

EB
76
6B
D8
C8
8F
02
CE
CA

24
EO
F6
E5
E4

P
P
P
P
P
P
P
P
P
P
P
P
P

0189
018B
018E
018F
0191
0193
0195
0197
0199
019C
019D
019E
01AO

E3
56
1E
A2
EB
BO
A2
EB
56
CF
9F
50
AF

CD
EO

16
02
E1
17
03
EO

P
P
P
P

01A1 16
01A4 82
01A6 8B
01A8

EC
CC
E3

D1
18

FD
00

525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577

GLOBAL
I for PART II
ser get PROCEDURE

' •• T ••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose =

To return one serial input character.

Input =

None.

Output =

Carry FLAG =

Note =

This routine will not return control
until a character is available in the
input buffer or an error is detected.

if BREAK detected or
serial not enabled
or buffer overflow
= 0 otherwise
TEMP 1 = character

·····················································1
ENTRY
push
srp
scf
ser _g1 : tm

jr
tm
jr
ld
ld
di
add
inc
djnz
ld
ser_g4: and
inc
cp
jr
clr
ser_g2: cp
jr
and
ser _g5: rcf
ei
ser_g6: pop
ret

rp
IIRAM STARTr

Isave caller's rpl
!point to subr. RAMI
lin case errorl
r SERflg, I/sd LOR bd LOR bo
Iserial disabled or
BREAK detected or
buffer overflow? I
I yes.1
nZ,ser g6
rSERflg ,llbne
Ibuffer not empty? I
I empty. waitl
z,ser_g1
rTEMP 1l,rSERbufl
rTEMP=1h,rSERbufh
Iprevent IRQ3 conflictl
rTEMP _ll,rSERget !next char addressl
linput buffer in ... 1
rTEMP 1h
rTEMP=1h,ser_g3 I •.• external memoryl
I ••• register memoryl
rTEMP 1,@rTEMP 11 Iget charI
rSERfIg,ULNOT bf Ibuffer not fulll
rSERget
!update get pointer I
rSERget,rSERlen ! wrap-around? I
Ino .1
ne,ser g2
Iyes. set to startl
rSERget
r SERget ,rSERput !buffer empty if get ••. 1
! .•. and put =I
ne,ser g5
rSERflg,ULNOT bne Ibuffer empty nowl
Iset good returnl
Ire-enable interrupts I
rp
Irestore caller's rpl

rTEMP_1h,110
!rrTEMP 1 has char addr!
ser_g3: adc
rTEMP 1,@rrTEMP 1 !get charI
lde
ser_g4
-Iclean upl
jr
ser_get
END

1-43

P 01A8

P 01AS BO
P 01AA 80
P 01AC EB

P 01AE 80
P 01B1

0238'

FO
FA

P 01B1

P 01B1 8F
P
P
P
P
P
P

01B2
01B4
01B6
01B9
01BA
01BB

BO
BO
56
9F
AF

71
77

579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613

GLOBAL
ser break

PROCEDURE

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

break transmission
Purpose =

To transmit BREAK on the serial line.

Input =

RR14 = break length

Output =

None.

Note =

BREAK is defined as:
serial out (P37) = 0 for
2
x 28 cycles/loop x RR14 loops
XTAL
RR14 should yield at least 1 bit time
so that the last 'clr SIO' will
have been preceded by at least 1 bit
time of spacing. Therefore, RR14 should
be greater than or equal to
4 x 16 x PREO x TO
28

•••••••••••••••••••••••••••••••••••••••••••••••••••• '!

ENTRY
ser b 1:
clr
SIO
dec,",
RR14
jr
nz,ser b1
!wait for last null to-be fully transmitted!
jp
ser 01
END
ser break

615 GLOBAL
PROCEDURE
616 ser flush
617 I··T ••••••••••••••••••••• *••••••••••••••••••••••••••••
618 input flush
619
620 Purpose
To flush (clear) the serial input
buffer of characters.
621
622
None
623 Input =
624
Empty input buffer.
625 Output =
626
627 Note =
This routine might be useful to clear
all past input after a BREAK has been
628
detected on the line.
629
630 '*""""'*"""'*""""""""""""""""'1
631 ENTRY
632
di
Idisable interrupts I
!(to avoid collision with
633
serial input) I
634
clr
SER_get !buffer startl
635
clr
SER put != buffer end!
636
SER-flg,H%80
!clear statusl
and
637
ei
Ire-enable interrupts!
638
ret
639
640 END
ser flush

1-44

P 01BB

P 01BB BO
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

01BD
01BE
01C1
01C3
01C5
01C8
01CB
01CD
01DO
01D2
01D5
01D/\
01DA
01DC
01DF
01E1
01E4
01E7
01E9
01EB
01ED
01FO
01F2
01F3
01F4

DF
76
EB
70
D6
D6
7B
A6
EB
56
A6
EB
00
76
6B
E6
D6
8B
DA
50
24
D8
CF
AF

7E
70 80
30
ED
0000·
020B'
1E
7E 00
17
7C 7F
7C OD
OF
ED
72 04
OA
7C OA
020B'
02
DA
7C
ED 7C
7C

642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696

CONSTANT
wli len

R13

GLOBAL

ser wlin

PROCEDURE

! •• y •••••••••••••••••••••••••••••••••••••••••••

wri te line

*.*** ..

Purpose =

To output a character string to serial
line, ending with either a 'carriage
return' character or the maximum length
specified.

Input

RR14
R13

= address of source buffer
(in reg/ext memory)
= length

Output

RR14 = updated
Carry Flag = 1 if serial not enabled,
= 0 if no error.
R13 = # bytes output (not including
auto line feed)

Note

If auto line feed is enabled, a
line feed character will be output
following each carriage return
(ser wlin only).

*·**··*·························*···············*····1
ENTRY
wr i te:

wli 4:

wli 1:
END-

clr

Iflag => write linel

scf
SER flg,l/sd
tm
jr
nz,wli 1
wli len
push
get-src
call
ser-output
call
jr
c ,wTi 2
cp
TEMP j , I/O
jr
nz,wli 5
and
TEMP 1~1/$7F
TEMP-1,1/$OD
cp
jr
nz,wTi 5
wli len
dec
SER-c fg, I/al
tm
jr
z,wli 2
TEMP 1,UOA
Id
call
ser output
wlC2
jr
wI
i-len, wli 4
djnz
TEMP 1
pop
TEMP-1,wli len
sub
wli_Ten,TE'Rp_1
Id
rcf
ret
ser wlin

lin case errorl
Iserial disabled?1
I yes. error I

1-45

Iwrite the character I
!serial disabled I
Iwrite line?1
I no, absolute. I
!mask off parityl
lline done?1
I yes. I
lauto line feed?!
!disabledl
loutput line feedl
Iloopl
loriginal lengthl
Ireturn output countl
Ino errorl

P 01F4

P 01F4 E5
P 01F7 88
P 01F9

7E
C4

P 01F9

P
P
P
P

01F9
01F8
01FE
0201
P 0203
P 0206
P 0208

P 0208

C9
05
75
58
A5
E8
E6

7C
0208'
72 04
3E
EC 00
39
7C OA

698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713

GL08AL
ser wabs

PROCEDURE

!**T********* ••••• *••• ** ••• *•••• * •••••••••••••••••••••

write absolute
Purpose

Note

To output a character string to serial
line for the length specified. (Output
is not terminated with the output of
a 'carriage return').
All other details are as for 'ser wlin'.

•••••• *.*** ••• *•••••• *•• *•••••••••••••••••••••••• T••• !
ENTRY
END

Id
TEMP 3,#1
jr
write
ser wabs

PROCEDURE
715 ser wbyt
716 I*·T •• *.*.*.* ••••••••••••• ****.*.**.* •••••••• ****.** ••
717 write byte
718
To output a given character to the
719 Purpose =
serial line. If the character is a
720
carriage return and auto line feed
721
is enabled, a line feed will be output
722
as well.
723
724
R12 = character to output
725 In put =
726
Equivalent to ser wlin with length = 1.
727 Note =
728 .* ••• *•• *.* ••• ***.* •• *•• *********T**.******* •• ** ••• *.!
729 ENTRY
Id
TEMP 1,R12
730
call
ser output
!output it!
731
tm
SER-cfg,llal
!auto line feed?!
732
jr
z,ser 05
!not enabled!
733
!char = car. ret?!
cp
R12,IIIOD
734
jr
nz,ser 05
!nope!
735
!output line feed!
Id
TEMP l~#%OA
736
737 ! fall into ser out puc!
ser_wbyt
738 END

1-46

P 020B

P
P
P
P
P

020B
020C
020F
0211
0214

DF
76
EB
76
6B

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0216 70
0218 E6
021B BO
021 D CO
021F 16
0222 00
0224 EB
0226 56
0229 56
022C 44
022F CO
0231 CO
0233 50
0235 E4
0238 66
023B EB
023D 56
0240 CF
0241 AF
0242

70
30
72
IF
7E
7E
7D
7C
7D
7E
F7
7D
7C
7D
7C
7C
7E
7C
FA
FB
FA

80
40

07
00
01
FE
7C

FO
10
EF

P 0242

P 0242 8F
P 0243 46

P 0246 56

P 0249 56

P 024C 56

024F E4
0252 9F
0253 AF
0254

P
P
P
P

740
741
742
743
744
745
746
747
748
74 9
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773

774
775
776
777
778
779
780
781
782
783
784
785
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811

GLOBAL
ser output

!for PART I!
PROCEDURE

! •• T ••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose

To output one character to the serial
line.

In put =

TEMP_l

Output

Carry

= character
FLAG = 1 if serial disabled
= 0 otherwise.

1. If even parity is enabled, the eigth
data bit is modified prior to character
output to SIO.

Note

2. IRQ4 is polled to wait for completion
of character transmission before control
returns to the calling program .

••••••••••••••••••••••••••••••••••••••••••••••••••••• !

ENTRY

scf
tm
SER flg,#sd
jr
nz,ser 05
tm
SER cfg,#ep
jr
z sar 02
!calculate parity!
push
TEMP 3
ld
TEMP-3,#7
clr
TEMP-2
ser 04: rrc
TEMP-l
adc
TEMP-2,#0
dec
TEMP-3
jr
nz,ser 04
and
TEMP 2~#01
and
TEMP-l, II\lFE
or
TEMP-l,TEMP 2
rrc
TEMP-l
rrc
TEMP-l
pop
TEMp_3
ser 02: ld
SIO,TEMP
ser-ol: tcm
IRQ,#\l10jr
nz,ser 01
and
IRQ, Ut:F
rcf
ser 05: ret
ENDser_output
GLOBAL
ser disable

!in case errorl
Iserial disabled?!
I yes. error I
leven parity enabled?1
!no. just outputl

Icharacter bit to carry!
!count 1'51
! next bit I
11's count odd/even!

Iparity bit in DOl
!parity bit in D7!
!output character!
!check IRQ4!
!wait for complete!
Iclear IRQ4!
! all okl

PROCEDURE

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

disable
To disable serial 1/0 operations.

Purpose

None.
=
Output =
Serial 1/0 disabled •
••••••••••••••••••••••••••••••••••••••••••••••••••••• !
Input

ENTRY

di
or
and
and
and

END

!avoid IRQ3 conflict!
SER flg,Hsd
Iset serial disabledl
TMR,UFC
!disable TOI
IMR,UE7
!disable IRQ3,41
P3M save,#\lBF
!P30/7 normal i/o pins!
P3M,P3M save
-Ire-enable interrupts I

ld
ei
ret
ser disable

1-47

T~mer/Counter

Routines

P 0254

P
P
P
P
P
P

0254
0256
0258
025A
0250
0260

DC
C3
C3
E6
80

6C
DE
DE
7B 6C
02B2'

840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897

CONSTANT
R13
TMP
PTR
RR14
R14
PTRh
=
GLOBAL
tod i
PROCEDURE
!'*~""*""""""""'*""*""""""""*"*"

time of day

initialize

Purpose

To initialize TO or T1 to function as
a time of day clock.

Input

RR14

= address of parameter list
program memory:
byte = IMR mask for nestable

interrupts
# of clock ticks per second
counter # : = %F4 => TO
= %F2 => T1
Counter value
byte
byte
Prescaler value (unshifted)
byte
byte

TOO hr, TOO min, TOO sec, TOO tt
inItialized to the starting time of
hours, minutes, seconds, and ticks
respectively.
Output

Note

Selected timer is loaded and
enabled; corresponding interrupt
is enabled.
R13, R14, R15 modified.

The cntr and prescaler values provided
are those values which will generate an
interrupt (tick) the designated # of
times per second.
For example:
for XTAL = 8 MHZ, cntr = 250 and
prescaler = 40 yield a .01 sec interval;
the 2nd byte of the parameter list
should = 100 •
For TO the instruction at %080C or
for T1 the instruction at %080F must
result in a jump to the jump table entry
for 'tod'.
The parameter list is not referenced
following initialization.

······················*······························1

ENTRY

END

ld
ldci
ldci
ld
jp
tod i

TM P , IITOD imr

@TMP,@PT~

!imr maskl
@TMP,@PTR
!ticks/secondl
TEMP 4,IITOD imr
pre_ctr
Ictr & prescaler!

1-48

---"~

- " - - - - - - - _.. -----

P 0260

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0260
0262
0265
0266
0268
026A
026B
0260
026F
0271
0272
0275
0277
0279
027A
0270
027F
0281

70
54
9F
70
31
8E
A2
EB
BO
9E
A6
EB
BO
AE
A6
EB
BO
BE

P
P
P
P
P

0282
0284
0285
0287
0288

50
8F
50
BF

FB
6C

FD
60
80
13
E8
E9
OB
E9

EA
03
EA

FD
FB

-----~-

899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930

GLOBAL
tod

PROCEDURE

1·····················································

Interrupt service - time of day
Purpose =

To update the time of day clock.

·····················································1
ENTRY
push
and
ei
push
srp
inc
cp
jr
clr
inc
cp
jr
clr
inc
cp
jr
clr
inc

tod ex: pop
di
pop
iret
END
tod

imr
imr,TOD_imr

rp
IIRAM TMRr
rTODtt
rTODtt,rTODtic
ne,tod ex
rTODttrTODsec
rTODsec,1I60
ne,tod ex
rTODsec
rTODmin
rTODmin,1I60
ne,tod ex
rTODmfii
rTODhr

Isave entry imrl
lallow nested interrupts
lenable interrupts 1
! save rpl
!point to our setl
Iticks/secondl
!second complete?1
Inope .1

!secondsl
Iminute complete?!
Inope .1
!minutesl
1hour complete? 1
Inope.1
!hoursl
Irestore rpl
Idisable interrupts 1
Irestore entry imrl

rp
imr

1-49

P 0288

P
P
P
P
P
P
P
P
P
P
P
P

0288
028A
028C
028E
0290
0292
02911
0297
029A
029D
02AO
02A3

DC
C3
C3
C3
80
80
56
56
Ell
E6
8D

65
DE
DE
DE
EE
EE

F 1 3F
7F DF
7F F7
7B 01
02B2 '

P 02A3

P 02A3 BII
P 02A6 BII
P 02A9 BII

65
67
65

67
65
67

P 02AC F5
P 02AF BF
P 02BO

932
933
9311
935
936
931
938
939
9110
9111
9112
9113
91111
9115
9116
9111
9118
9119
950
951
952
953
9511
955
956
951
958
959
960
951
952
963
9611
955
966
961
958
969
910
911
912
913
9111
915
916
911
918
919
980
981
982
983
9811
985
985
981
988
989

GLOBAL
pulse i PROCEDURE

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose =

To initialize one of the timers
to generate a variable frequencyl
variable pulse width output.

Input

RR111 = address of parameter list in
program memory:
byte
cntr value for low interval
byte
counter n : = %FII => TO
= %F2 => Tl
cntr value for high interval
byte
prescaler
(unshifted)
byte

Output

Selected timer is loaded and
enabled; corresponding interrupt
is enabled. P36 1s enabled as Tout.
R13, Rll1, R15 modified.

Note =

The parameter list is not referenced
following initialization.
The value of Prescaler x Counter
must be > 26 (=%lA) for proper
operation.

...................... *.............................. !
ENTRY

TMP,IIPLS_2
@TMP,@PTR
@TMP,@PTR
@TMP,@PTR
PTR
PTR
TMR,II%3F
P3M save, UDF
P3W;P3M save
TEMP 11,#%1
pre_ctr

END

LD
ldci
ldci
ldci
decw
decw
and
and
ld
ld
jp
pulse- i

GLOBAL
pulse

PROCEDURE

flow interval cntrl
!timer addr!
thigh interval cntr!
Iback to flagl
twill be modifying TMRI
! P36 = Toutl
! flag for pre ctr!
Iset up timerT

I·····················································
Purpose =
To modify the counter load value

to continue the pulse output generation.

·························**·*················*·*·····1
ENTRY
lexchange values I
xor
PLS 1,PLS 2
xor
PLS-2,PLS-l
xor
PLS-l,PLS-2
!exchange completelld
@PLS_tmr,PLS_l
iret
END
pulse

1-50

Iload new valuel

P 02BO

P 02BO BO
P 02B2

991
992
993
9911
995
996
997
998
999
1000
1001
1002
1003
10011
1005
1006
1007
1008
1009
1010
1011
1012
1013
10111
1015
1016
1017
1018
1019
1020
1021
1022
1023
10211

GLOBAL
delay

PROCEDURE

! •••••••••••••••••••••••••••••••••••••••••••••••••••••

Purpose

To generate an interrupt after a
designated amount of time.

Input

RR111

Output

Selected timer is loaded and
enabled; corresponding interrupt
is enabled.
R13, R111, R15 modified.

Note

This routine will initialize the timer
for single-pass or continuous mode
as determined by bit 0 of byte 3 in
the parameter list.
The caller is responsible for providing the interrupt service routine.

= address of parameter list in
program memory:
byte = counter U : = SFII => TO
= SF2 => T1
byte = Counter value
byte = Prescaler value and count mode
(to be loaded as is into
PREO or PRE1).

The parameter list is not referenced
following initialization.

·····················································1
ENTRY
clr
TEMP II
!fall into pre ctrl END
delay -

1-51

P 02B2

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

02B2
02B4
02B6
02B9
02BC
02BF
02C1
02C4
02C7
02C9
02CB
02CE
0200
0201
0203
0204
0206
0209
02DB
0200
02EO
02E2
02E5
02E7
02EA
02EB
02EE
02EF
02FO

C2
AO
E6
E6
A6
6B
E6
E6
C3
C2
A6
6B
OF
10
OF
10
A6
EB
60
54
60
56
F3
44
BF
44
9F
AF

DE
EE
70
7E
ED
06
70
7E
DE

BC
20
F2
43
10

7B
12

EE
EE
7B
OA
7E
7E
7E
70
DE
70

6C
6C
OF

1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067

INTERNAL
pre ctr PROCEDURE

!**y ••• ** •••••••••••••• ****.****.** •••• ***.**.** ••••••

Purpose =

To get counter and prescaler values
from parameter list and modify control
registers appropriately.

Input

TEMP 4

= 0 => for 'delay'
= 1 => for 'pulse'
= TOO imr => for 'tod'

.............................
T·······················I
ENTRY
ldc
incw
ld
ld
cp
jr
ld
ld
pre 1: ldci
ldc
cp
jr
scf
rIc
scf
rIc
cp
jr
com
and
com
pre 2: and
pre=3: ld
or
di
or
ei
ret
pre ctr
END
PART
IIEND

TMP ,@PTR
PTR
TEMP 2, 11%8C
TEMP-3,U20
TMP, #T 1
eq,pre_1
TEMP 2,11%43
TEMP-3,U10
@TMP-;-@PTR
PTRh,@PTR
TEMP_4,nO
eq,pre_2
PTRh

ITO or T1I
! for TMR!
! for IMRI

i.s for T1 I
! for TMR!
I for IMRI
linit counter I
Iprescaler!
!shift prescaler?!
!nol
!internal clock I
!

Icontinuous mode!
PTRh
TEMP_ 4, IITOO imr
ne,pre_3
TEMP 3
TOO lmr, TEMP 3
TEMP 3
TEMP-2,UOF
@TMP-;-PTRh
TMR,TEMP_2
imr,TEMP_3

! for 'pulse'l
!insure no self-nesting I
Ino Tout mode modI
!init prescaler!
! init tmr model
tenable interrupt!

o errors
Assembly complete

1·52

00-2160-01

Z8® MCU Test Mode
Application
Note

Zilog

June 1982
The second problem is:
since the Test Mode
requires that Port
operate only in the
Address/Data bus mode, how are the other Port 1
modes of operation tested? To solve this problem,
an on-chip Test ROM is provided for execution
while in Test Mode. The program in the Test ROM
checks the other modes of Port 1: input, output,
with handshake control, and without handshake control.

This application note is intended for use by those
with either a ZB601 or a ZB611 Microcomputer
device. It is assumed that the reader is familiar
with both the ZB and its assembly language, as
described in the following documents:

•

ZB Technical Manual (Reset Section)
( 03-3047-02)

•

ZB ramily ZB601, ZB602, ZB603 Product Spec
(00-2037-AO)

•

ZB ramily ZB611, ZB612, ZB613 Product Spec
(00-203B-AO)

•

ZB PLZ/ASM Assembly Language Programming
Manual (03-3023-03)

rigure 1 compares normal and Test Mode operations
in the ZB. (In both normal and Test Mode, program
execution begins at address OOCH.)

This note briefly discusses the operation of Test
Mode, which is a special mode of operation that
facilitates testing of both Z8 devices that incorporate an internal program ROM (Z8601, Z8611).
There are two problems associated with testing a
ZB with an internal program ROM; the solutions are
presented below.

NORMAL

MODE

Z8801

The first problem is:
how can the device be
tested with standard microprocessor automatic test
equipment?
To solve this problem, Test Mode
causes the ZB to fetch instruct ions from Port 1
while it is in the external Address/Data bus mode,
instead of fetching instructions from the internal
Program ROM.
Diagnostic test routines are then
forced onto this external bus from the test equipment in the same manner as with microprocessor
testing.

Z8811
ON·CHIP

PROGRAM
ROM

TEST MODE

1-._ _.....IooCH

figure 1.

1-53

Comparison of Nona1
and Test !tides

Test Mode can be entered immediately after reset
by driving the RESET input (pin 6) to a voltage of
Vee + 2.5 V.
(See the Reset section of the
ZB Technical Manual for a description of the Reset
procedure.) figure 2 shows the voltage waveform
needed for Test Mode. After entering Test Mode,
inst ructions are fetched from the internal Test
ROM, which is programmed with Port 1 diagnostic
routines.
The Z8 stays in Test Mode until a
normal reset occurs.

The program listing in the ROM is included at the
end of this document. Program Listing A (Internal
Test ROM Program) is mask programmed into the
internal Test ROM of the Z8601. Program Listing B
(External Test Program) is an example of a program
that could be executed while in Test Mode. It was
written as a compliment to the internal Test ROM
program, to check the Port input and output functions. To test the other functions of the Z8, the
user must execute other programs developed for
testing.
The interrupt vectors in the Z8601 Test ROM point
to the locations in external memory %800, 1.803,
%806, %809, %80e, 1.80r. The interrupt vectors in
the ZB611 Test ROM point to the locations in
external memory 1.1000, 1.1003, %1006, %1009, %100e,
%100r. This allows the external program to have a
2- or 3-byte jump instruction to each interrupt
service routine.

RESET PIN

v,,----"1

Programs that are run in Test Mode can use an LDE
instruction for accessing the Test ROM. The LDe
instruction can be used for accessing the program
ROM.

Note the maximum ramp for application of
+ 7,5 VDC to mET pin. After a minimum 01
6 XTAL eLK cycles, the RESET voltage can be
relaxed to VRH.

rigure 2.
Program Listing A.

Z8ASM
LOC

Test MOde Wave rorm
Internal Test ROM Program

4.0
OBJ CODE

P 0000 0800
P 0004 0806
P 0008 080C

oooc

P
P
P
P
P
P
P
P

OOOC
OOOF
0012
0014
0016
001P
001A
001C
ODiE
0020
0022
0024
0026

P
P
P
P

E6
8D
99
A9
48
F3
61
58
E3
E3
88
C9
8D

0803
0809
080F

F8 96
0812
F8
F7
E3
DE
ED
E3
68

7B
E3
F8
0831

STMT SOURCE STATEMENT
Z8 TEST ROM ROUTINE FOR VERIFYING
1
PORT 1 I/O, WITH AND WITHOUT H.S.
2
3
4
5 TESTROM MODULE
6
7
8 $SECTION PROGRAM
9 $ABS 0
INTERNAL
10
RUPT VECTOR ARRAY [6 WORD):=
11
12
a800 1803 1806 1809 180C 180F)
13 $SDEFAULT
14
15
16 INTERNAL
17 TEST
18 PROCEDURE ENTRY $ABS SOOC
19
Pl&PO=EXT MEM,STK=IN,NORMAL !
LD P01M U96
20
JUMP TO EXTERNAL TEST CODE !
JP EXT
21
START OF Pl I/O TEST I
22 STARTl : LD P01M R9
SET
H.S.& P2 PU ACTIVE
LD P3M Rl0
23
TEST RDY=l,DAV=l I
24
LD R4 IE3
WRITE PORT I
LD @R13 R14
25
WRITE PORT I
COM @R13
26
TEST RDY=O,DAV=l I
LD R5 IE3
27
READ PORT & STUFF DATA
LDR6@R11
2B
DITTO I
LD R7 @Rll
29
TEST RDY=l,DAV=l I
LD R8 IE3
30
CONFIGURE FOR EXT !
LD P01M R12
31
JUMP TO VERIFY ROUTINE
JP VERIFYl
32
33

1-54

2242-002

~----------

Program Listing A.

P
P
P
P
P
P
P
P
P

0029
002B
002D
002E
0030
0031
0033
0035
003fl

B9
99
lE
F9
1E
9e
C9
8D

Internal Test ROM ProgrlB

F7
F8

35
36
37
38
39

F8
El
F8
086D

~O
~

112

Program Listing B.

0800
0803
0806
0809
080C
OSOF

flD
SD
8D
8D
8D
8D

P
P
P
P
P
P

OS12
0813
OS15
0817
OS19
081C

SF
31
2C
3C
E6

P
P
P
P
P
P
P
P
P
P
P
P

oelE 5C
0820 9C
0822 AC
082~ BC
0826 CC
082fl DC
082A FC
082C EC
082E E6
0831 E6
0831l 8D
0837

0800
0~03

Ofl06
0809
080C
080F
00
FF
FF
F6
88

00
86
39
02
96
01
86
AA
10 10
1 1 110
0012

P 0831
P
P
P
P

0831
0833
0835
01'38

DC
BC
E6
66

START TEST NO H.S.
SET Pl TO INPUT I
READ & WRITE Pl AS INPUT
SET Pl TO OUTPUT!
READ & WRITE PI AS OUTPUT
SAVE RESULTS IN R9 I
Pl&PO=EXT,STK IN,NORMAL I
JUMP TO VERIFY 82 ROUTINE

External Test Program

P 0800
P
P
P
P
P
P

(continued)

START2: LD P3M R11
LD P01M R9
INC Rl
LD P01M R15
INC Rl
LD R9 ~El
LD P01M R12
JP VERIFY2
END TEST

02
01
F6
Ell

00
50

48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
71l
75
76
77
7S
79
SO
81
82
83
Sil
S5
86
87
88
89

INTERNAL
SETUP
PROCEDURE ENTRY $ABS
VECT1
VECT2
VECT3
VECT4
VECT5
VECT6

JP
JP
JP
JP
JP
JP

EXT:

DI
SRP #~OO
LD R2 UFF
LD R3 UFF
LD P2M UFF
LD R4 U8S
LD
LD
LD
LD
LD
LD
LD
LD
LD

~800

VECTl
VECT2
VECT3
VECT~

VECT5
VECT6

INITIALIZE P2 I
DITTO I
SET P2 TO INPUT I
SET P2<>Pl MUX,P3 GRP B MUX !
ALSO DUMMY ADDRS HIGH BYTE !
DUMMY ADDRS LOW BYTE !
Pl OUTPUT MODE VALUE I
Rl0 SETS H.S.MODE & P2 PULLUPS
Rll POINTS TO P2 FOR PASS1 I
R12 SETS P01M TO EXT MEM,ETC.
R13 POINTS TO P1 FOR PASS1 !
SAME AS R9 !
DATA LOADED TO TEST PORT !
RDY/DAV RESULT PASS 1 !
DITTO I
END SETUP--JUMP TO TEST START

R5 UOO
R9 US6
Rl0 U39
Rll U02
R12 U96
R13 U01
R15 n86
Rlll UAA
~10 U10

LD~11

n~o

JP STARTl
END SETUP
INTERNAL
VERIFY
PROCEDURE ENTRY $ABS
VERIFY1:LD R13
LD Rll
LD P2M
TCM Ril

n02
nOl
UOO
U50

1-55

~831

R13 POINTS TO P2 FOR PASS2 !
Rll POINTS TO P1 FOR PASS 2 !
SETS P2 FOR OUTPUT I
FROM HERE TO THERE WE VERIFY !
TEST RESULTS FOR 1/0 WITH H.S.
BOTH PASS 1&2 !

-~---

Progr_ Listing B.

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

083B
083E
08111
081111
0847
0811A
0840
0850
0853
0856
OF59
OS5C
085F
0862
0865
0867
086A
0860

ED
611
ED
711
ED
A6
ED
A6
ED
66
ED
A6
E6
E6
9C
60
80
A6

P 0870 60
P 0873

External Test Progr_

0880
10 E5
0880
11 E5
0880
E6 AA
0880
E7 55
0880
E8 50
0880
E9 86
10 110
11 10
8E
0012
0029
E9 57
0890

P 0890
0890 8B

0892

oe80
0880 8B
0882

90
91
92
93
911
95
96
97
98
99
100
101
102
103
1011
105
106
107
108
109
110
111
112
113
1111
115
116
117
118
119
120
121
122
123
1211
125
126
127
128
129
130
131
132

(continued)

JP NZ FAIL
TCM R5 "0
JP NZ FAIL
TM R5 '"
JP NZ FAIL
CP R6 "AA
JP NZ FAIL
CP R7 '155
JP NZ FAIL
TCM R8 "50
JP NZ FAIL
CP R9 '186
LD "0 '1110
LD "1
LD R9 "8E
JP EO STARTl
JP START2
VERIFY2:CP R9 '157

"'0

IS THIS PASS1? I
RDYIDAV RESULT PASS 2 !
DITTO I
Pl IS GOING TO BE AN OUTPUT
PASSl SUCCESSFUL--TRY PASS2
PASS2 SUCCESSFUL--TEST NO H.S.
CHECK RESULT OF 1/0 NO H.S.TES

JP EO PASS
END VERIFY
INTERNAL
TPASS
PROCEDURE ENTRY $ABS '890
PASS:JR PASS
END TPASS
INTERNAL
TFAIL
PROCEDURE ENTRY $ABS '880
FAIL:JR FAIL
END TFAIL
END TESTROM

1-56

00-2042-01

Build a Z8-Based Control
COlllputer with BASIC, Part 1
Steve Ciarcia
POB 582

Glastonbury CT 06033

I hope you believe me when I say
that I have been waiting years to present this project. For what has seemed
an eternity, I have wanted a microcomputer with a specific combination
of capabilities. Ideally, it should be
inexpensive enough to dedicate to a
specific application, intelligent
enough to be programmed directly in
a high-level language, and efficient
enough to be battery operated.
My reason for wanting this is purely selfish. The interfaces I present
each month are the result of an
overzealous desire to control the
world. In lieu of that goal, and more
in line with BYTE policy, I satisfy this
urge by stringing wires all over my
house and computerizing things like
my wood stove.
There are many more places I'd like
to apply computer monitoring and
control. I want to modify my homesecurity system to use low-cost
distributed control rather than central
control. I want to try my hand at a
little energy management, and, of
course, I am still trying to find some
reason to install a microcomputer in a
car. (How about a talking dashboard?)
Generally, the projects I present
each month are designed to be attached to many different commercially available microcomputers through
CopYright © J 98 J by Steven A ClarCIa
All rights reserved

existing lIO (input! output) ports.
Most of my projects are applicable
for use on the small (by IBM standards) computers owned by many
readers, but, unfortunately, a typical
home-computer system cannot be
stuffed under a car seat.

The Za-BASIC
Microcomputer is a
milestone in low-cost
microcomputer
capability.
The time has come to present a versatile "Circuit Cellar Controller"
board for some of these more ambitious control projects. I decided not
to adapt an existing single-board
computer, which would be larger,
more expensive, and generally limited
to machine-language programming.
Instead, I started from scratch and
built exactly what I wanted.
The microcomputer/controller I
developed is called the Z8-BASIC
Microcomputer. Its design and application will be presented in a twopart article beginning this month. In
my opinion, it is a milestone in lowcost microcomputer capability. It can
be utilized as an inexpensive tinyBASIC computer for a variety of
changing applications, or it can be
dedicated to specialized tasks, such as

Reprinted with permission of Byte Publications. Inc, 1981

I-57

security control, energy management, solar-heating-system monitoring, or intelligent-peripheral control.
[Editor's Note: We are using the term
"tiny BASIC" generically to denote a
small, limited BASIC interpreter. The
term has been used to refer to some
specific commercially available products based on the Tiny BASIC concept promulgated by the People's
Computer Company in 1975 .... RSSj
The entire computer is slightly
larger than a 3 by 5 file card, yet it includes a tiny-BASIC interpreter, 4 K
bytes of program memory, one RS232C serial port and two parallelllO
ports, plus a variety of other features.
(A condensed functional specification
is shown in the "At a Glance" text
box.) Using a Zilog Z8 microcomputer integrated circuit and Z6132
4 K by 8-bit read/write memory
device, the Z8-BASIC Microcomputer circuit board is completely selfcontained and optimized for use as a
dedicated controller.
To program it for a dedicated
application, you merely attach a user
terminal to the DB-25 RS-232C connector, turn the system on, and type
in a BASIC program using keywords
such as GOTO, IF, GOSUB, and
LET. Execution of the program is
started by typing RUN. If you need
higher speed than BASIC provides, or
if you just want to experiment with
the Z8 instruction set, you can use the

GO@ and USR keywords to call the Z80 or the Intel 8080 require sup- intensive applications. Under proport circuitry to make a functional gram control, the Z8 can be conmachine-language subroutines.
Once the application program has computer system. A single-chip figured as a stand-alone microcombeen written and tested with the aid microcomputer, on the other hand, puter using 2 K to 4 K bytes of internal ROM, as a traditional microproof the terminal, the finished program can function solely on its own.
The concept is not new. Single-chip cessor with as much as 120 K to
can be transferred to an EPROM
(erasable programmable read-only microcomputers have been around 124 K bytes of external memory, or
memory) via a memory-dump pro- for quite a while, and millions of as a parallel-processing unit working
gram and the terminal disconnected. them are used in electronic games. with other computers. The Z8 could
Next, the 2S-pin Z6132 memory com- The designers of the Z8, however, be used as a controller in a
ponent is removed from its socket raised the capabilities of single-chip microwave oven or as the processor
and either a type-2716 (2 K by 8-bit) microcomputers to new heights and in a stand-alone data-entry terminal
or type-2732 (4 K by S-bit) EPROM provided many powerful features complete with floppy-disk drives.
is plugged into the lower 24 pins. usually found only in generalGetting Specific: The Z8671
(The choice of EPROM depends upon application microprocessors.
The member of the Z8 family used
Typically, single-chip microcomthe length of the program.) When the
ZS board is powered up, the stored puters have been designed for in this project is the Z8671. This component differs from the
program is immediately
garden-variety Z8601
executed. The EPROM
chiefly in the contents
devices and the Z6132
of the ROM set at the
read/write memory
factory. The pinout
device
are
pinspecification of the
compatible. Permanent
Z8671 is shown in
program storage is
figure 1b, and the
simply a matter of
package is shown in
plugging an EPROM
photo 2 on page 41.
into the Z6132's socket.
The Z8671 package
There is much more
contains the processor
power on this board
circuitry, 2 K bytes of
than is alluded to in this
ROM (preprogrammed
simple description.
with a tiny-BASIC inThat is why I decided
terpreter and a debugto use a two-part article
ging monitor), 32 lIO
to explain it. This
lines, and 144 bytes of
month, I'll discuss the
programmable (read/
design of the system
Photo 1: A prototype of the versatile "Circuit Cellar Controller, " forwrite) memory.
and the attributes of the
mally called the Z8-BASIC Microcomputer. The printed-circuit board
The operational arZ8 and Z6132. Next
measures 4 by 4th inches and has a 44-pin (two-sided 22-pin) edge conrangement of memorymonth, I'll describe exnector with contacts on O.156-inch centers. A 2716 or 2732 EPROM
address space is shown
ternal interfacing
can be substituted for the Z6132 Quasi-Static memory, plugging into
in figure 1c. The intertechniques, a few apthe same socket.
nal read/write memory
plications, and the
steps involved in transferring a pro- microcontroller applications and op- is actually a register file (illustrated in
gram into an EPROM.
timized for lIO processing. On a figure 2) composed of 124 general40-pin dual-inline package, as many purpose registers (R4 thru R127), 16
Single-Chip Microcomputers
as 32 of the pins can be lIO related. A status-control registers (R240 thru
The central component in the ROM-programmed single-chip R255), and 4 lIO-port registers (RO
Z8-BASIC Microcomputer is a microcomputer used in an electronic thru R3). Any general-purpose
member of the Zilog Z8 family of chess game might offer a thousand register can be used as an accumuladevices. The specific component variations in game tactics, but it tor, address pointer, index register, or
used, the Z8671, is just one of them. could not be reprogrammed as a as part of the internal stack area. The
Unlike a microprocessor, such as the word processor. The ability to significance of these registers will be
well-known Zilog Z80, the Z8 is a reorient processing functions and explained when I describe the tinysingle-chip microcomputer. It con- reallocate memory has generally been BASIC/Debug interpreter/monitor.
The 32 lIO lines are grouped into
tains programmable (read/write) the province of microprocessors, with
memory, read-only memory, and their memory-intensive architecture.
four separate ports and treated interlIO-control circuits, as well as cirThe Z8 architecture (shown in nally as 4 registers. They can be concuits to perform standard processor figure 1a on page 40) allows it to figured by software for either input or
functions. Microprocessors such as serve in either memory- or lIO- output and are compatible with

1-58

OUTPUT

INPUT

Vee

XTAL

GND

As Os

R /W

RESEi'

! !

PROGRAM
MEMORY
2048 8Y 8-BI T

110
IBIT PROGRAMMABLE I

ADDRESS OR 110
INY8BLE PROGRAMMABLEI

P36

P31

XTALI

P27

P37

P26

P30

P2s

RESET

P24

R/W

P23

P22

P21

P3s

P20

GND

P33

P32

P34

POo

PI7

POI

Pl6

P02

PiS

P03

PI4

P04

PI3

POs

PI2

P06

PII

P07

PI O

ADDRESS/DATA OR 110
IBYTE PROGRAMMABLE I

Figure la: Block diagram of the Zilog Z8-family single-chip microcomputers. Their architecture allows these devices to serve in either memory- or IIO-intensive applications.
This figure and figures Ib, lc, 2, 3, and 4 were provided through the courtesy of Zilog
Inc.

LSTTL (low-power Schottky transistor-transistor logic). In addition, port
1 and port 0 can serve as a multiplexed address/data bus for connection of external memory and
peripheral devices.
In traditional nomenclature, port 1
transceives the data-bus lines DO thru
D7 and transmits the low-order
address-bus signals AO thru A7. Port
o supplies the remaining high-order
address lines A8 thru A1s, for a total
of 16 address bits. This allows 62 K
bytes of program memory (plus 2 K
bytes of ROM) to be directly addressed. If more memory is required,
one bit in port 3 can be set to select
another memory bank of 62 K bytes,
which is referred to as data memory.
In the Z8-BASIC Microcomputer
presented here, a separate datamemory bank is not implemented,
and program and data memory are
considered to be the same.
The Z8 has forty-seven instructions, nine addressing modes, and six
interrupts. Using a 7.3728 MHz

Vee
XTAL2

crystal (producing a system clock rate
of 3.6864 MHz) most instructions
take about 1.5 to 2.5 /lS to execute.
Ordinarily, you would not be concerned about single-chip-microcomputer instruction sets and interrupt
handling because the programs are
mask-programmed into the ROM at
the factory. In the Z8671, however,
only the BASIC/Debug interpreter is
preprogrammed. Using this interpreter, you can write machinelanguage programs that can be executed through subroutine calls written in BASIC. This feature greatly
enhances the capabilities of this tiny
computer and potentially allows the
software to control high-speed
peripheral devices. (A complete
discussion of the Z8 instruction set
and interrupt structure is beyond the
scope of this article. The documentation accompanying the Z8-BASIC
Microcomputer Board describes the
instruction set in detail.)
The final area of concern is communication. The Z8 contains a full-

I-59

Figure lb: Pinout specification of the
Zilog Z8671 microcomputer. The Z8671 is
a variant of the basic Z8601 component of
the Z8 family. The Z8671 is used in this
project because it contains the
BASIC/Debug interpreter/monitor in
read-only memory. Other members of the
Z8 family are supplied in different
packages, chiefly to support systemdevelopment work.

duplex UART (universal asynchronous receiver/transmitter) and
two counter/timers with prescalers.
One of the counters divides the
7.3728 MHz crystal frequency to one
of eight standard data rates. With the
Z8671, these rates range between 110
and 9600 bps (bits per second) and
are switch- or software-selectable.
A block diagram of the serial-1I0
section is shown in figure 3. Serial
data is received through bit 0 of port
3 and transmitted from bit 7 of port 3.
While the Z8 can be set to transmit
odd parity, the Z8671 is preset for 1
start bit,-8 data bits, no parity, and 2
stop bits. Received data must have 1
start bit, 8 data bits, at least 1 stop
bit, and no parity (in this configuration).

Quasi-Static Memory
A limiting factor in small controller

LOCATION

IDENTIFIERS

255 STACK POINTER IBITS 7-01

IDECIMAL)
EXTERNAL
ROM OR
PROGRAMMABLE
IR/WI MEMORY

t-------i~g:~
ON-CHIP
ROM

PROGRAM MEMORY

EXTERNAL
PROGRAM MABLE
IR/WI MEMORY

r-------t~g:~
NOT
ADDRESSABLE

DATA MEMORY

CONTROL AND
STATUS REGISTERS

SPH

253 REGISTER POINTER

255

252 PROGRAM CONTROL FLAGS

FLAGS

240

25 1 INTERRUPT MASK REGISTER

I MR

250 INTERRUPT REQUEST REGISTER

I RQ

1 27

249 INTERRUPT PRIORITY REGISTER

I PR

248 PORTS 0-1 MODE

POIM

NOT
IMPLEMENTED

GENERAL
REGISTERS

110 PORT
REGISTERS

SPL

254 STACK POINTER IBITS 15-81

247

4
3

PROGRAMMABLE
REGI STER MEMORY
ION CHIPI

PORT 3 MODE

P3M

246 PORT 2 MODE

P2M

245 TO PRESCALER

PREO

244 TIMER/COUNTER 0
243

Tl PRESCALER

TO
PREI

242 TI MER /COUNTER 1

241

TIMER MODE

TMR

240

SERIAL 110

SIO

Figure Ie: The operational arrangement of memory-address space in the 28 family. The

regions labeled "program memory" and "data memory" may map to the same physical
memory, or two separate banks may be used, selected through one bit of I/O port 3.
The internal programmable (read/write) memory is a register file containing 124
general-purpose registers, 16 status-control registers, and 4 I/O-port registers.

designs has always been the trade-off
between memory size and power consumption. To keep the number of
components down and simplify construction, a designer generally selects
a limited quantity of static memory.
Frequently, the choice is to use two
type-2114 1 K by 4 NMOS
(negative-channel metal-oxide
semiconductor) static-memory
devices. In practice, however, the
1 K-byte memory size thereby provided is rather limited. It would be
much better to expand this to at least
4 K bytes. Unfortunately, eight 2114
chips require considerably more
circuit-board space and consume
about 0.7 amps at +5 V. Not only
would this make the design ill suited
for battery power, it could never fit
on my 4- by 4V,-inch circuit board.
Another approach is to use
dynamic memory, as in larger computers. Dynamic memory costs less,
bit for bit, than static memory and
consumes little power. Unfortunately, most dynamic-memory components require three separate
operating voltages and special refresh
circuitry. Adding 4 K bytes of
dynamic memory would probably
take about twelve chips. The advantages gained in reduced power consumption hardly justify the expense
and effort.
The solution to this problem, sur-

prisingly enough, also comes from
Zilog, in the form of the Z6132
Quasi-Static Memory. The Z6132,
shown in photo 4 on page 43, is a
32 K-bit dynamic-memory device,
organized into 4 K 8-bit (byte-size)
words. It uses single-transistor
dynamic bit-storage cells, but the
device performs and controls its own
data-refresh operations in a manner
that is completely invisible to the user
and the rest of the system. This
eliminates the need for external
refresh circuitry. Also, the Z6132 requires only a +5 V power supply.
The result is a combination of the
design convenience of static memory
and the low power consumption of
dynamic memory. All 4 K bytes of
memory fit in a single 28-pin dual-inline package, which typically draws
about 30 milliamps.
An additional benefit in using the
Z6132 is that it is pin-compatible with
standard type-2716 (2 K by 8-bit)
and type-2732 (4 K by 8-bit)
EPROMs. This feature is extremely
beneficial when you are configuring
this Z8 board for use as a dedicated
controller. As previously mentioned,
the Z6132 can be removed and an
EPROM inserted in the low-order 24
pins of the same socket. Thus, any
program written and operating in the
Z6132 memory can be placed in a
nonvolatile EPROM. (There are some

1-60

NOT IMPLEMENTED

127

GENERAL PURPOSE
REGISTERS

4
3 PORT 3

PORT 2

PORT 1

PORT 0

Figure 2: An

expanded view of the
register-memory section of figure 1c,
showing the organization of the register'
file. Any general-purpose register can be
used as an accumulator, address pointer,
index register, or as part of the internal
stack area.

Photo 2: The 2ilog 28671 single-chip
microcomputer. a member of the 28
family of deVices. This dual-mline
package contains the processor cir. cuitry, 2 K bytes of ROM, 32 1I0
lines, and 144 bytes of programmable
memory.

Photo 3: A photomicrograph of the silicon chip containing the working parts of a 28 microcomputer.

The following items are avatlable
from.
The MicroMmt Inc
917 Midway
Woodmere NY 11598
Telephone.
(800) 645-3479 (for orders)
(516) 374-6793 (for techmcal informatiOn)

Z8-BASIC Microcomputer
Documentation Includes:
Z8 Techmcal Manual. Z8 Product
SpeCIfication
Z6132 Product Specification
BASIC/Debug Manual
Z8-BASIC MIcrocomputer Construction/Operator's Manual
Assembled and tested ... $170
Kit ... $140

Z8-BASIC Microcomputer power supply
(Size: 2% by 4% inches)
Provides: + 5 V. 300 rnA
+12 V. 50 rnA
-12 V. 50 rnA
Assembled and tested .... $35
Kit ... $27

All prlnted-CircUlt boards are solder-masked and silk-screened,
The documentatiOn supplied with the Z8 board includes approximately 200 pages of materials. It is available separately for $25. This
charge will be credited toward any subsequent purchase of the Z8 board
Please mclude $4 for shippmg and handlmg. New York residents please mclude 7% sales tax.

1-61

_At a Glance _ _ _ _---t
Name
Z8-BASIC Microcomputer

Processor
Zilog Z8-family Z8671 8-bit microcomputer with programmable (read/write)
memory, read-only memory, and I/O in a
single package. The Z8671 includes a
2 K-byte tiny-BASIC/Debug resident interpreter in ROM, 144 bytes of scratchpad memory, and 32 I/O lines. System
uses 7.3728 MHz crystal to establish clock
rate. Two internal and four external inter-

rupts.

Memory
Uses Z6132 4 K-byte Quasi-Static
Memory (pin-compatible with 2716 and
2732 EPROMs); 2 K-byte ROM in Z8671.
Memory externally expandable to 62 K
bytes of program memory and 62 K bytes
of data memory.

Photo 4: The Zilog Z6132 Quasi-Static Memory device, shown with the hood up.
This component stores 32 K bits in the form of 4 K bytes in invisibly refreshed
dynamic-memory cells.

Input/Output
Serial port: RS-232C-compatible and
switch-selectable to 110, 150, 300, 1200,
2400, 4800, and 9600 bps.
Parallel I/O: two parallel ports; one
dedicated to input, the other bitprogrammable as input or outputi pro-

grammable interrupt and handshaking
lines; LSTTL-compatible.
External I/O: 16-bit address and 8-bit
bidirectional data bus brought out to expansion connector.

BASIC Keywords
GOTO, GO@, USR, GOSUB,
IP ... THEN, INPUT, LET, LIST, NEW,
REM, RETURN, RUN, STOP, IN,
PRINT, PRINT HEX. Integer
arithmetic/logic/operators: +, -, /, "
and AND; BASIC can call machinelanguage subroutines for increased execu-

tion speed; allows complete memory and
register interrogation and modification.

Power-Supply Requirements
+5 V ±5% at 250 rnA
+12 V ±10% at 30 rnA
-12 V ±10% at 30 rnA
(The 12 V supplies are required only for
RS-232C operation.)

Dimensions and Connections
4- by 4Y,-inch board; dual 22-pin
(0.156-inch) edge connector. 25-pin RS232C female D-subminiature (DB-25S)

Photo 5: The Z8-BASIC Microcomputer Board attached to a power supply. Power
can be supplied either through the separate power connector, as shown, or through
the edge connector.

1-62

connector; 4-pole DIP-switch data-rate
selector.

Operating Conditions
Temperature: 0 to 50°C (32 to 122°P)
Humidity: 10 to 90% relative humidity
(noncondensing)

INTERNAL DATA BUS
--------~~-----.

TO INTERRUPT
LOGIC

limitations placed on the number of
subroutine calls and variables allowed by this substitution because
variable data and return addresses
must be stored in the Z8's register
area instead of in external read/write
memory.)

ZS-BASIC Microcomputer

Figure 3: Block diagram of the serial-lIO section of the 28-family microcomputers. The

28 contains a full-duplex UART (universal asynchronous receiver/transmitter). The
data rates are derived from the clock-rate crystal frequency. Serial data is received
through bit a of port 3 and is transmitted from bit 7 of port 3. An interrupt is generated
within the 28 whenever transmission or reception of a character has been completed.

Photo 6: The 28-BASIC Microcomputer in operation, communicating with a video
terminal (here, a Digital Equipment Corporation VT8E). A memory-dump routine,
written using the BASIC/Debug interpreter, is shown on the display screen. The
starting address of the dump is the beginning of the user-memory area; the hexadecimal values displayed are the ASCII (American Standard Code for Information
Interchange) values of the characters that make up the first line of the memory-dump
program.

1-63

Figure 5 on pages 46 and 47 is the
schematic diagram of the seven-integrated-circuit Z8-BASIC Microcomputer Board, shown in prototype
form, with a power supply, in photo
5. ICI is the Z8671 microcomputer,
the member of the Z8 family that contains Zilog's 2 K-byte BASIC/Debug
software in read-only memory. IC2 is
the Z6132 Quasi-Static Memory, and
IC3 is an 8-bit address latch. Under
ordinary circumstances, the Z6132 is
capable of latching its address internally, but IC3 is included to allow
EPROM operation. IC4 and IC5 form
a hard-wired memory-mapped input
port used to read the data-rateselection switches. IC6 and IC7 provide proper voltage-level conversion
for RS-232C serial communication.
The seven-integra ted-circuit computer typically takes about
200 milliamps at +5 V. The +12 V
and -12 V supplies are required
only for operating the RS-232C interface. Power required is typically
about 25 milliamps on each.
The easiest way to check out the
Z8-BASIC Microcomputer after assembly is to attach a user terminal to
the RS-232C connector (}2) and set
the data-rate-selector switches to a
convenient rate. I generally select
1200 bps, with SW2 closed and SWl,
SW3, and SW4 open. After applying
power, simply press the RESET push
button.
Pressing RESET starts the Z8's initialization procedure. The program
reads location hexadecimal FFFD in
memory-address space, to which the
data-rate-selector switches are wired
to respond. When it has acquired this
information, it sets the appropriate
data rate and transmits a colon to the
terminal. At this point, the Z8 board
is completely operational and programs can be entered in tiny BASIC.

A8 THRU All

REFRESH
ADDRESS
COUNTER

I":lt
r.-;-I

>--

MULTIPLEX
INPUT
ADDRESS
BUFFERS

,..

MEMORY ARRAY

---

ROW
DECODER
(J OF 1281

128 SENSE AMPLIFIERS
MEMORY ARRAY

:
Al
TH RU
A7

COLUMN DECODER
(J OF

'-\

----'\

gkZ~~ATOR

t-'v--

•~

ADDRESS
BUFFERS

CLOCK
GENERATOR

SENSE
AMPLIFIERS
AND
1/0
DRIVERS

,.....

........
--'\

DATA
1/0
BUFFERS

DO
THRU

MEMORY ARRAY

'--I

..
..

161

BY 8 DATA BUS

MULTI PLEX
INPUT
ADDRESS
BUFFERS

---

ROW
DECODER
II OF 1281

128 SENSE AMPLI FIERS
MEMORY ARRAY
REFRESH
DEMAND
LOGIC
ICYCLE
COUNTERI

1
Figure 4: Block diagram of the 2ilog 26132 Quasi-Static Memory component. This innovative part stores 32 K bits in the form of
4 K bytes, using single-transistor dynamic random-access bit-storage cells, but all refresh operations are controlled internally. The
memory-refresh operation is completely invisible to the user and the other components in the system. The 26132 draws about 30
milliamps from a single +5 V power supply.

(With the simple address selection
employed in this circuit, the data-rate
switches will be read by an access to
any location in the range hexadecimal
COOO thru FFFF. This should not unduly restrict the versatility of the
system in the type of application for
which it was designed.)

BASIC/Debug Monitor
I'll go into the features of the tinyBASIC interpreter in greater detail
next month, but I'm sure you are
curious about the capabilities present
in a 2 K-byte BASIC system.
Essentially an integer-math dialect
of BASIC, Zilog's BASIC/Debug
software is specifically designed for
process control. It allows examination and modification of any memory
location, 110 port, or register. The
interpreter processes data in both
decimal and hexadecimal radices and
accesses machine-language code as
either a subroutine or a user-defined
function.

BASIC/Debug recognizes sixteen
keywords: COTO, CO@, USR,
COSUB, IF ... THEN, INPUT, IN,
LET, LIST, NEW, REM, RUN,
RETURN, STOP, PRINT, and
PRINT HEX. Standard syntax and
mathematical operators are used.

The ZS board is
not my idea of what
should be available;
it is available now.
Twenty-six numeric variables,
designated by the letters A thru Z, are
supported. Variables can be used to
designate program line numbers. For
example, COSUB B*100 and COTO
A*B*C are valid expressions.
In my opinion, the 2 K-byte interpreter is extremely powerful. Because
it operates easily on register and
memory locations, arrays and blocks
of data can be easily manipulated.
1-64

(Full appreciation of the Z8-BASIC
Microcomputer comes after a complete review of the operating manuals
and a little experience. Documentation approximately 200 pages long is
supplied with the unit; the documentation is also available separately.)

In Conclusion
It's easy to get spoiled using a large
computer as a simple control device. I
have heard of many inexpensive interfaces that, when attached to any
computer, supposedly perform control and monitoring miracles. Frequently overlooked, however, is the
fact that implementation of these interfaces often requires the softwaredevelopment tools and hardwareinterfacing facilities of relatively large
systems. The Z8-BASIC Microcomputer, with its interpretive language,
virtually eliminates the need for costly development systems with memory-consuming text editors, assemblers, and debugging programs.

i-{
1M)

'"
0-

=--

SERIAL OUT ITTL!
SERIAL IN ITTL!
C4

[[)

1
I .h.1

1 13
1

o
11.

I IE:
1
[i!;:

I ,.,..

..."..

d::

:IE:
II[::

[[;::
[L:.
'U"
t-

o11.

10pF

0
2
XTALZ

VCC

3
XTALI
RESET
SERIAL OUT 1P37)

33 PZ2

P2 3

ICI
Z 8671

34 P23

PZ 4

SERIAL IN 1P30)

2S MICROCOMPUTER
WITH BASIC 10EBUG

35 P2 4

P2 s

.L r

!....
Lo-,--

36 P2S

P2 6

37 P26

P2 7

3S PZ7

P07
20

AIS

P06

POs

P04

P03
16

POo R/W

P02 POI
15

Plo PII
ZI

PIZ
23

PI3
24

PI 4
25

PiS
26

PI6 PI7
27

AI4
AI3

Ail

AIO

:;.

CRYSTAL
7.372SMH,

10pF

32 P21

P22

AI2

~
'IT

30 129
P33 P3 4

31 P2 0

PZ I

W-

l[)

50:

P2 0

.:t-

+5V

I 'P'
I

A9
A8
R/W
OS
AS

"
'9'
'IO"

Ill::
4

11.

AD/OO
AIIOI
A2I02
A3/03

[[)

A4/D4

'6'
;;:.
.L..

AS/OS
A6/06
A7/07
+SV
21
AIO

24
25
27
11
12
13
15
16
17
18 19
22 t28
A8
A9
WE OS
VCC 00
01
02
04
05 06 07 CS ~
03
Ao
IC2
26132
4K BY 8
PROGRAMMABLE 1R/W) MEMORY

+ 12V
SUPPLY

A2tL--

A3~
A4

:tC7

'T' ~'tvF

IK:::

:<
o

11.

:r:::

C8~+

TYPICAL
FOR 3

-1~V

SUPPLY

'2'

::--~

L
J1

All
+~v SUPPLY

JUMPERS

f rh

1
~RAM 1.\32K

16K

-BUSY

VSS
14

RAM tEPROM

1'.'7

CONNECTOR

1-65

---------------_•.

iL-

AstL---

f1.L--

AltL-

__ .--..._

......

__...._-----

+~v

VBB A7 A6

I~c/

;1 C6
O.II'F

fL--

J2
RS-232C
CONNECTOR

MCI488

r----,
I

I
I

,-------------1
I
I

I
I
I

L __
th L
__ --1

~
b

6 I

IC5
74LSI0

I
I
I
I

41
5

9
10
II

Next Month:
I will elaborate on interfacing and
applications for the Z8-BASIC
Microcomputer .•

L ______________ -1

+5V

+5V
19 f20
2G

I
IG
2Y4
5 2Y3

V~~ 17

~~~S244

7 2Y2

2A213
2AI II

@f
2 IC 5 Q
13 74LSI0

--1.

50
70

B5
B4
B2

IA36

BI
BO

GROUND

)i0

+5V

SW 3
SW4

:;:'%\.F

GND

IA24
2
IAI

I
I

GJ
<:!!I
I
::::::II
I
Gl
I
.::::Q;

I
~
I
I "-'"
I '-='
L
___ ...J

Acknowledgment
Special thanks to Steve Walters and Peter
Brown of Zilog Inc for help in production of
this artic/e.

Editor's Note: Steve often refers to prevIOus
Circuit Cellar artzcles as reference material for
the articles he presents each month. These
articles are available in reprint books from
BYTE Books. 70 Main St. Peterborough NH
03458. Ciarcia's Circuit Cellar covers articles
appearing in BYTE from September 1977 thru
November 1978 Ciarcia's Circuit Cellar,
Volume II presents artic/es from December
1978 thru June 1980.

DATA-RATE
SELECTOR

-1.§. 80

r-- -,

IC3
74LS373
ADDRESS
LATCH

--1.! 60
-1Z.

VCC ~

-.! 40
----ll

IA48

II
EG

-2 10
--.! 20

I
R I (SIP)
4.7K
TYPICAL FOR 8
2

2A3 15

9 2YI
12 IY4
14 1Y3
16 I Y2

If you need a proportionai motorspeed control for your solar-heating
system, you don't have to dedicate
your Apple II or shut off your heating
system when you balance your
checkbook. From now on, there is a
small, cost-effective microcomputer
specifically designed for such applications. The Z8 board described in this
article is not my idea of what should
be available; it is available now.

Figure 5: Schematic diagram of the Cir-

10 20 30 4 Q SO 60 70 8Q
9 12 15 16 19
2 15
6

Number

Type

IC1
IC2
IC3
IC4
IC5
IC6
IC7

Z8671
Z6132
74LS373
74LS244
74LS10
MC1488
MC1489

+5V GND
1
28
20
20
14
14

11
14
10
10
7
7
7

-12V

+12V

1-66

cuit Cellar Z8-BASIC Microcomputer.
Five jumper connections are provided so
different memory devices can be used. For
general-purpose use and program
development, the 4 K-byte Z6132
read/write memory device will be used;
for dedicated applications, two kinds of
EPROMs can be substituted in the same
integrated-circuit socket. Standard 450 ns
type-2716 or type-2732 EPROM chips can
be used. The connection labeled "32 K"
should be closed if a type-2732 EPROM is
installed; the connection labeled "16 K"
should be closed for use of a type-2716
EPROM.
The pull-up resistors adjacent to IC4
(the 74LS244 buffer) are contained in a
SIP (single-inline package).

Build a Z8-Based Control
Contputer with BASIC, Part 2
Steve Ciarcia
POD 582

Glastonbury CT 06033

The Z8-BASIC Microcomputer ROM (read-only memory) within the
system described in this two-part Z8671 is officially called the Zilog
article is unlike any computer pre- BASIC/Debug monitor. It is essensently available for dedicated control tially a 2 K-byte integer BASIC which
applications. Based on a single-chip has been optimized for speed and
Zilog Z8 microcomputer with an on- flexibility in process-control applicaboard tiny-BASIC interpreter, this tions.
unit offers an extraordinary amount
of power in a very small package. It is
no longer necessary to use expensive
program-development systems. Computer control can now be applied to
many areas where it was not
previously cost-effective.
The Z8-BASIC Microcomputer is
intended for use as an intelligent controller, easy to program and inexpensive enough to dedicate to specific
control tasks. It can also serve as a
low-cost tiny-BASIC computer for
general interest. Technical specifications for the unit are shown in the "At
a Glance" box.
Last month I described the design
of the Z8-BASIC Microcomputer
hardware and the architectures of the
Z8671 microcomputer component
and Z6132 32 K-bit Quasi-Static
Memory. This month 1'd like to continue the description of the tinyBASIC interpreter, discuss how the
BASIC program is stored in memory,
and demonstrate a few simple applications.
Process-Control BASIC
The BASIC interpreter contained in
CopYright © 1981 by Steven A CiarCia.
All rights reserved

There are 15 keywords: GOTO,
GO@, USR, GOSUB, IF ... THEN,
INPUT, IN, LET, LIST, NEW, REM,
RUN, RETURN, STOP, PRINT (and
PRINT HEX). Twenty-six numeric
variables (A through Z) are supported; and numbers can be ex-

Photo 1: Z8-BASIC Microcomputer. With the two "RAM" jumpers installed, it is
configured to operate programs residing in the Z6132 Quasi-Static Memory. A
four-position DIP (dual-in line pin) switch (at upper right) sets the serial data rate
for communication with a user terminal connected to the DB-25S RS-232C connector on the top center. The reset button is on the top left.

1-67

pressed in either decimal or hexadecimal format. BASIC/Debug can
directly address the Z8's internal
registers and all external memory.
Byte references, which use the "@"
character followed by an address,
may be used to modify a single
register in the processor, an I/O port,
or a memory location. For example,
@4096 specifies decimal memory
location 4096, and @%F6 specifies
the port-2 mode-control register at
decimal location 246. (The percent
symbol indicates that the characters
following it are to be interpreted as a
hexadecimal numeral.) To place the
value 45 in memory location 4096,
the command is simply, @4096=45
(or @%1000=%2D).
Command abbreviations are standard with most tiny-BASIC interpreters, but this interpreter allows some
extremes if you want to limit program
space. For example:
IF 1> X THEN GOTO 1000
can be abbreviated
IF l>X 1000
PRINT"THE VALUE IS ";S

can be abbreviated
"THE VALUE IS ";S
IF X=Y THEN IF Y=Z
THEN PRINT "X = Z"
can be abbreviated
IF X=Y IF Y=Z "X=Z"
One important difference between
most versions of BASIC and Zilog's
BASIC/Debug is that the latter
allows variables to contain statement
numbers for branching, and variable
storage is not cleared before a program is run. Statements such as
GOSUB X or GOTO A*E-Z are
valid. It is also possible to pass values
from one program to another. These
variations serve to extend the capabilities of BASIC/Debug.
In my opinion, the main feature
that separates this BASIC from others
is the extent of documentation supplied with the Z8671. Frequently, a
computer user will ask me how he can
obtain the source-code listing for the
BASIC interpreter he is using. Most
often, I have to reply that it is not
available. Software manufacturers
that have invested many man-years

Name
28-BASIC Microcomputer
Processor
2ilog 28-family 28671 8-bit microcomputer with programmable (read/write)
memory, read-only memory, and 110 in a
single package. The 28671 includes a
2 K-byte tiny-BASIC/Debug resident interpreter in ROM, 144 internal 8-bit
registers, and 32 110 lines. System uses
7.3728 MHz crystal to establish clock
rate. Two internal and four external interrupts.
Memory
Uses 26132 4 K-byte Quasi-Static
Memory (pin-compatible with 2716 and
2732 EPROMs); 2 K-byte ROM in 28671.
Memory externally expandable to 62 K
bytes of program memory and 62 K bytes
of data memory.
Input/Output
Serial port: RS-232C-compatible and
switch~electable to 110, 150, 300, 1200,
2400, 4800, and 9600 bps.
Parallel 110: two parallel ports; one
dedicated to input, the other bitprogrammable as input or output; programmable interrupt and handshaking
lines; LSTTL-compatible.
External 110: 16-bit address and 8-bit
bidirectional data bus brought out to expansion connector.

BASIC Keywords
COTO, CO@, USR, COSUB,
IF ... THEN, INPUT, LET, LIST, NEW,
REM, RETURN, RUN, STOP, IN,
PRINT, PRINT HEX. Integer
arithmetic/logic operators: +. -, /, "
and AND; BASIC can call machinelanguage subroutines for increased execution speed; allows complete memory and
register interrogation and modification.
Power-Supply Requirements
+5 V ±5% at 250 rnA
+12 V ±10% at 30 rnA
-12 V ±10% at 30 rnA
(The 12 V supplies are required only for
RS-232C operation.)

Photo 2: The Z81Micromouth demo'1strator. A Z8-BASIC Microcomp!lter is
configured to run a ROM-resident program that exercises the Micromouth speech
synthesizer presented in the June Circuit Cellar article. A Micromouth board
similar to that shown on the left is mounted inside the enclosure. Six pushbutton
switches, connected to a parallel input port on the Z8 board, select various
speech-demonstration sequences. The Micromouth board is driven from a second
parallel port on the Z8 board.

1-68

Dimensions and Connections
4- by 4'/,-inch board; dual 22-pin
(0.156-inch) edge connector. 25-pin RS232C female D~ubminiature (DB-25S)
connector; 4~pole DI1"-swiich dai:a~rai:e

selector.

Operating Conditions
Temperature: 0 to 50°C (32 to 122 OF)
Humidity: 10 to 90% relative humidity
(noncondensing)

in a BASIC interpreter are not easily
persuaded to give away its secrets.
In most cases, however, a user
merely wants to know the location of
the GOSUB ... RETURN address stack
or the format and location of stored
program variables. While the source
code for BASIC/Debug is also not
available (because the object code is
mask-programmed into the ROM,
you couldn't change it anyway), the
locations of all variables, pointers,
stacks, etc, are fixed, and their storage formats are defined and described
in detail. The 60-page BASIC/Debug
user's manual contains this information and is included in the 200 pages

of documentation supplied with the
Z8-BASIC Microcomputer board.
(The documentation is also available
separately. )

Memory Allocation

Z8-family microcomputers distinguish between four kinds of memory:
internal registers, internal ROM, external ROM, and external read/write
memory. (A slightly different distinction can also be made between
program memory and data memory,
but in this project this distinction is
unnecessary.) The register file resides
in memory-address space in hexadecimal locations 0 through FF (decimal 0
through 255). The 144 registers include four I/O- (input! output) port
registers, 124 general-purpose regisFFFF
ters, and 16 status and control regisFFFD - - Data-rate switches
ters. (No registers are implemented in
hexadecimal addresses 80 through EF
Remainder
[decimal addresses 128 through 239]).
undefined
The 2 K-byte ROM on the Z8671
COOO
chip contains the BASIC/Debug interpreter, residing in address space
BFFF
from address 0 to hexadecimal 7FF
User-memory and 1/0(decimal 0 to 2047). External memory
expansion area
starts at hexadecimal address 800
(decimal 2048). A memory map of the
8000
Z8-BASIC Microcomputer system is
7FFF
shown in figure 1.
When the system is first turned on,
undefined
BASIC/Debug determines how much
external read/write memory is avail2000
able, initializes memory pointers, and
checks for the existence of an auto17FF
start-up program. In a system with
On-board 4 K bytes of readlwrite
external read/write memory, the top
memory or EPROM
page is used for the line buffer,
program-variable storage, and the
800
GOSUB ... RETURN address stack.
Program execution begins at hexadec7FF
imallocation 800 (decimal 2048).
When BASIC/Debug finds no exBASICIDebug ROM
ternal read/write memory, the internal registers are used to store the vari100
ables, line buffer, and GOSUB ... REFF
TURN stack. This limits the depth of
the stack and the number of variables
Z8 registers
tRat can be used simultaneously, but
the restriction is not too severe in
00
most control applications. In a system without external memory, autoFigure 1: A simplified hexadecimal matic program execution begins at
memory map of the Z8-BASIC Micro- hexadecimal location 1020 (decimal
4128).
computer.

1-69

In a system that uses an external
2 K-byte EPROM (type 2716), wraparound addressing occurs, because
the state of the twelfth address line on
the address bus (A11) is ignored. (A
4 K-byte type-2732 EPROM device
does use A11.) A 2716 EPROM device inserted in the Z6132's memory
socket will read from the same memory cells in response to accesses to
both logical hexadecimal addresses
800 and 1000. Similarly, hexadecimal
addresses 820 and 1020 will be treated
as equivalent by the 2716 EPROM.
Therefore, when a 2 K-byte 2716
EPROM is being used, the auto-start
address, normally operating at hexadecimal 1020, will begin execution of
any program beginning at hexadecimal location 820. For the purposes of
this discussion, you may assume that
programs stored in EPROM use type2716 devices and that references to
hexadecimal address 820 also apply
to hexadecimal address 1020.

Program Storage
The program-storage format for
BASIC/Debug programs is the same
in both types of memory. Each
BASIC statement begins with a line
number and ends with a delimiter. If
you were to connect a video terminal
or teletypewriter to the RS-232C
serial port and type the following
line:
100 PRINT "TEST"
it would be stored in memory beginning at hexadecimal location 800 as
shown in listing 1.
The first 2 bytes of any BASIC
statement contain the binary equivalent of the line number (100 decimal
equals 64 hexadecimal). Next are
bytes containing the ASCII (American Standard Code for Information
Interchange) values of characters in
the statement, followed by a delimiter
byte (containing 00) which indicates
the end of the line. The last statement
in the program (in this case the only
one) is followed by 2 bytes containing
the hexadecimal value FFFF, which
designates line number 65535.
The multiple-line program in listing
2 further illustrates this storage format.

One final example of this is illustrated in listing 3. Here is a program written to examine itself. Essentially, it is a memory-dump routine
which lists the contents of memory in
hexadecimal. As shown, the IS-line
program takes 355 bytes and occupies
hexadecimal locations 800 through
963 (decimal 2048 through 2499). I
have dumped the first and last lines of
the program to further demonstrate
the storage technique.
I have a reason for explaining the
internal program format. One of the
useful features of this computer is its
ability to function with programs residing solely in EPROM. However,
the EPROMs must be programmed

The first application I had for the
unit was as a demonstration driver
for the Micromouth speech-processor
board I presented two months ago in
the June issue of BYTE. (See "Build a
Low-Cost Speech-Synthesizer Interface," in the June 1981 BYTE, page
46, for a description of this project,
which uses National Semiconductor's
Digitalker chip set.) It's hard to discuss a synthesized-speech interface
without demonstrating it, and I didn't
want to carry around my big computer system to control the Micromouth board during the demonstration. Instead, I quickly programmed
a Z8-BASIC Microcomputer to perform that task. While I was at it, I set

Listing 1: Simple illustration of BASIC program storage in the Z8-BASIC Microcom-

puter.
P

100
aoo
BOA

00
E
45

R
52

T
20

Listing 2: A multiple-line illustration of BASIC program storage.
100 A=5
200 B=6
3005 "A 'B = ";A 'B

800

100
00
64

814

36
3B

5
35

3D
3005
OB
BD

•

8
aOA

A
41

200
00

•

B
42

six pushbuttons are attached to 7 input bits of the Z8 board's input port
mapped into memory-address space
at hexadecimal address FFFD
(decimal 65533).
The most significant 3 bits of port
FFFD are normally reserved for the
data-rate-selector switches, but with
no serial communication required,
the data rate is immaterial and the
switches are left in the open position.
This makes the 8 bits of port FFFD,
which are brought out to the edge
connector, available for external inputs. In this case, pressing one of the
six pushbuttons selects one of six
canned speech sequences.
Coherent sentences are created by
properly timing the transmission of
word codes to the speech-processor
board. This requires nothing more
than a single handshaking arrangement and a table-lookup routine (but
try it without a computer sometime).
The program is shown in listing 4a.
The first thing to do is to configure
the port-2 and port-3 mode-control
registers (hexadecimal F6 and F7, or
decimal 246 and 247). Port 2 is bitprogrammable. For instance, to configure it for 4 bits input and 4 bits output, you would load FO into register
F6 (246). In this case, I wanted it configured as 8 output bits, so I typed in
the BASIC/Debug command @246=0
(set decimal location 246 to 0).

it up to demonstrate itself as well.
The result (see photo 2) has three
basic functional components. On top
of the box is a Z8-BASIC Microcomputer (hereinafter called the "Z8
board") with a 2716 EPROM installed
in the memory integrated-circuit
socket, the Z8-board power supply
(the wall-plug transformer module is
out of view), and six pushbutton
switches. Inside the box is a prototype version of the Micromouth
speech-processor board (a final-version Micromouth board is shown on
the left).

The data-ready strobe is produced
using one of the options on the Z8's
port 3. A Z8 microcomputer has
data-available and input-ready handshaking on each of its 4 ports. To set
the proper handshaking protocol and
use port 2 as I have described, a code
of hexadecimal 71 (decimal 113) is
placed into the port-2 mode-control
register. The BASIC/Debug command is @247= 113. The RDY2 and
DAV2 lines on the Z8671 are connected together to produce the dataavailable strobe signal.
Lines 1000 through 1030 in listing
4a have nothing to do with demon-

tested and debugged using a terminal,

The t\1icrcmouth board is jumper-

strating the ?v1icromouth board. They

the control program can be written
into an EPROM. When power is applied to the microcomputer, execution of the program will begin automatically.

programmed for parallel-port operation (8 parallel bits of data and a
data-ready strobe signal) and connected to lIO port 2 on the Z8 board.
The Micromouth BUSY line and the

form a memory-dump routine that illustrates how the program is stored in
memory. You notice from the memory dump of listing 4b that the first
byte of the program, as stored in the

externally. While I will explain how
to serially transmit the contents of the
program memory to an EPROM programmer, some of you may have only a manual EPROM programmer or
one with no communication facility.
But if you are willing to spend the
time, it is easy to print out the contents of memory and manually load
the program into an EPROM device.

Dedicated-Controller Use
The Z8-BASIC Microcomputer can
be easily set up for use in intelligent
control applications. After being

1-70

ROM, begins at hexadecimal location
820 (actually at 1020, you remember)
rather than 800 as usual. This is to
help automatic start-up. The program
could actually begin anyplace, but
you would have to change the program-pointer registers (registers 8 and
9) to reflect the new address. The 32
bytes between 800 and 820 are re-

served for vectored addresses to optional user-supplied 110 drivers and
interrupt routines.
Programming the EPROM
The first EPROM-based program I
ran on the Z8-BASIC Microcomputer
was manually loaded. I simply
printed out the contents of the Z6132

Listing 3: A program (listing 3a) that examines itself by dumping the contents of memory in printed hexadecimal form. Listing 3b shows the first and last lines of the program
as dumped during ex~cution.

(3a)

100 PRINf'ENf~R SrART ADDRESS fOR HEX DUMP ';:INPUT X
102 PRINI'rH~ LISr IS HOW MANY BYfES LONG ';:INPUf C
103 PF----------------,

INPUT CHANNELS
I NOI-'2"'6____________-<:::J

-<,

IN 1...2,,-7____________

I N21-'2"'S-------------<:::J
ANALOG
INPUTS
o TO SV

IN31-'1-------------CJ

IN4t"2~-----------CJ
INSp3'------------_CJ
IN6p4'------------_CJ

In
A9

+12V

IN7I-'S'-------------CJ

lly:>-:-____---..:1~12'4
I

ICS
ADCOSOS

I SK

II
:>o__

LM329B
69V

SK
-'I"i1 ENABLE

.:..I_ _ _ _

IC4
74LS373

L ___ --1

7 3D
.--____--'-1

3QI"6'-------=2""3 ADD C

.--1-____....;4"120

2QfS'-------=2,4 ADD B

.---1HI-----...;3"110

IQ 2

2S ADD A

---------c:(

14 01

AI/OI
A2I02

IC7
74LSOO

17 DO

AO/OO

O
CLOCKfl.:.

IS 02

<=n-----------------------------------~S03

IS 04

:---iC7-- --------,

19 OS

20 06

I
I I

21 07

GNO

-VREF

74LSOO

,L ______________ JI
6S0pF
"'SOOkHz

Number
IC1
IC2
IC3

1C4
IC5

1C6
IC7

Type

+5V

GND

+12V

7
74LS04
14
74LS30
14
7
74LS02
14
7
74LS373
20
10
ADC0808 see schematic diagram
LM301
4
7
74LSOO
14
7

which I used to attach a high-speed
computer to a very slow printer. The
host computer transmitted data to the
Z8 beard at 4800 bps. Since the receiving serial port used had to be bidirectional to handshake with the host
computer, I added another serial output to the Z8 board for transmitting
characters to the printer. Only three

Figure 2: Schematic diagram of an A/D

converter. This B-bit, eight-channel unit
has a unipolar input range of 0 to +5 V,
with the eight output channels addressed
as I/O ports mapped into memoryaddress space at hexadecimal addresses
BFOO through BF07.

integrated circuits were required to signal for the desired data rate. Of
add a serial output port. A schematic course, the UART could have been
diagram is shown in figure 3. The attached to the data and address
Up.RT (universal asynchronous re- buses directly, but this \vas easier.
ceiver/transmitter, shown as ICI) is
Transmitting a character out of this
driven directly from port Z on the Z8 serial port requires setting the port-Z
board (port Z could also be used to and port-3 mode-control registers as
directly drive a parallel-interface before. After that, any character sent
printer), and ICZ supplies the clock to port Z will be serially transmitted.

1-74

IC3
MCI4B8

OB-25
CONNECTOR
I

23 TOS

I
3

TSO 25
ICI
COM2017
UART

+5V

} RS-232C
OUTPUT

CS 34
NP 35
TSB

NB2 37
26
P20~1~2>_------------------~

TOI

NBI

2B
P22U£>_------------------~

T03

29
P23~>_------------------~

T04

EPS 39

27 T02
P2IUI~3>_------------------~

XR 21
GNO 3

30 T05
P24~1!>------------------~;
31 T06
TCP 40

32 T07
P26~>_------------------~
33
P27l~>_------------------~

Number
IC1
IC2

1C3

Type

+5V

GND

COM2017
COMS016
COM1488

1
2

3
11
7

TOB

-12V +12V
2

9
14

CRYSTAL
506BBMH.

Figure 3: SchemAtic diAgrAm of An RS-232C seriAl output port for the "blAck box" communicAtion ApplicAtion of the Z8-BASIC
Microcomputer. The Z8671 must be configured by softwAre to provide the proper signAls: one such signAl,
DA V2, is derived from two bits of I/O port 3 on the Z8671. The pin numbers shown in the schemAtic diAgrAm for P3 1 And P3. Are
pins on the Z8671 device itself, not pins or sections on the cArd-edge connector, liS Are P2. through P2, .

The minimum program to perform
this is shown in listing 6. This circuit
can also be used for downloading
programs to the EPROM programmer.

In Conclusion
It is impossible to describe the full
potential of the Z8-BASIC Microcomputer in so few pages. For this
reason, considerable effort has been
taken to fully document its characteristics. I have merely tried to given an
introduction here.
I intend to use the Z8-BASIC
Microcomputer in future projects. I
am interested in any applications you
might have, so let me know about
them, and we can gain experience
together.
Photo 5: When the Z8-BASIC Microcomputer is used with A ROM-resident progrAm, the two jumpers used with the Z6132 Are removed, And the EPROM
jumper is instAlled insteAd. When using A type-2716 16 K-bit (2 K-byte) EPROM
device, the "16 K" jumper is instAlled. If A type-2732 32 K-bit (4 K-byte) EPROM
is used insteAd, the "32 K" jumper is instAlled. The EPROM is inserted in the
lower 24 pins of the 28-pin Z6132 socket (IC2) liS shown.

Special thanks to Steve Walters and Peter
Brown of Zilog Inc for their aid in producing
these articles.

BASIC/Debug is a trademark of Zilog lnc.

1-75
-~--------------~--~-.---.---~-

Z8671 Seven Chip
Computer
Bardware
Application Note

Zilog

September 1981
INTRODUCTION

One advantage to programming in Bas1c/Debug lS the
interactive programming approach realized because
Bas1c/Debug 1S 1nterpreted, not assembled or compiled. Modules are tested and debugged using the
interactlve monltor provided wlth Basic/Debug.
USlng Basic/Debug saves program development time
by providing hlgher-level language statements that
simpllfy program development. Using the INPUT and
PRINT statements slmplify debugging.

The Z8601 is a single-chip microcomputer with four
8-bit I/O ports, two counter/timers with associated prescalers, asynchronous serial communication interface with programmable baud rates, and
sophisticated interrupt facilities. The Z8601 can
access data in three memory spaces: 2K bytes of
on-chip ROM and 62K bytes of external program
memory, 144 bytes of on-chip Register, and 62K
bytes of external data memory.

The Z8671 Microcomputer

The Z8671 is a Z8601 with a Basic/Debug Interpreter and Debug monitor preprogrammed into the 2K
bytes of on-chip ROM. This application note
discusses some considerations in designing a
low-complexity board that runs the Basic/Debug
Interpreter and Debug monitor with an external 4K
bytes of RAM and 2K bytes of ROM. The board
st ands alone, allowing users to connect it with a
terminal via an RS232 connector and run the
Basic/Oebug Interpreter.

Baslc/Debug controls the memory interface, serlal
port, and other housekeeping functions performed
by the assembly language programmer.
The Z8671 uses ports 0 and 1 for communicating
wi th external memory. Port 1 provides the multiplexed address/data lines (AD O-AD 7 ); port 0 supplies the upper address bits (AB-A15). The Z8671
also uses the serial communications port for communicatlng wlth a terminal. Serlal communication
takes two pins from port 3, leaving six I/O pins
from port 3 available to the user. The serial
communicatlon interface uses one of the two
counter/timers on the Z8671 chip.

The user of this board can run Basic/Debug with
little knowledge of the ZB601. The board, however, derives its power through its ability to
execute assembly language programs. To use the
board to its full potential, the Z8 Technical
Manual (document #03-3047-02) and the Z8 PLZ/ASM
Manual (document n03-3023-03) should be read. The
~ic/Debug Software Reference Manual (document
#03-3134-00) provides general information, statement syntax, memory allocations, and other material regarding Basic/Debug and the Debug monitor
provided by the Z8671. There are also two documents describing the Z6132; these are the Z6132
Product Specification (document nOO-2028-A), and
the Interfacin to the Z6132 Intelli ent Memor
Application Note document #00-2102-A).

All other functions and features on the Z8601 are
available with the Z8671. The user may reconfigure the Z8671 in software as a Z8601 if
desHed.
Applying the Z8671
Applications of the ZB671 range from a lowcomplexity home microcomputer that is memory
intensive to an lnexpensive, I/O-orlented microcontroller.

Basic/Oebug

For home computer users, Baslc/Debug is used like
other available Basic interpreters. The ZB671,
however, has many advantages over other computers.
For example, the programmer can use the available
funct ions such as int er rupts to perform sophisticated tasks that are beyond the scope of other
computer products. There is also a counter/timer

Basic/Debug is a subset of D~rtmouth Basic, which
interprets Basic statements and executes assembly
language pro,qrams located in memory. Basic/Debug
can implement all the Dartmouth Basic commands
directly or indirectly.

1-77

751-1927-0002

'--",--

----~-~--'-

--~------~----',-'-

6/18/81

',-.--,-------------

that ia uaed as s watchdog counter, a tlme-of-day
clock, a variable pulse width generator, a pulse
width measurement device, and a random number
generator.

tsched at any time to monitor the subroutines
running on the board.
This proposed board meets the design requirements
of simpliCIty and of allowing the user to write
and debug programs In BaSIC while maintaIning
access to the Z8671 on-chip features.

As an inexpensive microcontroller, Basic/Debug
speeds program development time by calling assembly language subroutinea (for time critical
applications) and by supplying high-level Basic
language statements that SImplIfy the programming
of noncritIcal subroutines.

Interfacing the Z8671 with External Memory
Both RAM and ROM are used in this application for
program development and to demonstrate the use of
components with and without address latches.

ARCHITECTURE
Two major design goals were set for this Z8671
Basic board. First, the board was to be simple.
Second, the board needed to allow the user to
write Basic programs and to utIlize the features
of the Z8601.

The RAM interface is easy to implement when using
a Z6132 (Figure 1). No external address latch is
needed because the Z6132 latches the address
internally. The Z6132 signals WE (Write Enable),
55 (Data Strobe), and AC (Address Clock) are wired
direct ly to the Z8671 signsls R/W (Read/ Write),
OS (Data Strobe), and AS (Address Strobe). The
only other signal required is Cs (ChIp Select).
Cs is prOVIded by the Z8671 by decoding the upper
address bIt of port O. ThIS board uses address
bit 15 to select the chip. Since there are two
memory ChIPS on thIS board, the upper address bit
ensures that the Z6132 is selected for addresses
800-7FFF (Hex) snd thst the 2716 is selected by
sddresses 8000-FFFF (Hex).

Overview
The board has aeven IC packages:
• Z8671
•
•
•
•
•
•

Z6132
2716
1488
1489
74LS04
74LS373

(Z8601 preprogrammed with
Basic/Debug)
(4K bytes of paeudo-static RAM)
(2K bytes of EPROM)
(RS232 line driver)
(RS232 line receiver)
(Hex inverter)
(octal latch)

There are two msjor advantages to using the
Z6132. The interface to the Z8671 is uncomplicated because both components sre Z_BUS™ compatible, and it provides 4K bytes of RAM in one
package.

With these chips, a complete microcomputer system
can be built with the following features:

The ROM interface is not as simple as the interface to the Z6132. Nevertheless, the circuit is
common in microcomputer applications. The ROM
does not latch the address from the Z8671 and
therefore needs an externsl address latch. The
74LS373 latches the address for the 2716 EPROM.
The Enable pin on the 74LS373 is driven by the AS
signal via an inverter.
The EPROM is also
selected by the upper address nibble of port O.
Figure 2 shows the Z8671-to-2716 interface.

• 2K byte Basic/Debug interpreter in the internal ROM.
• 4K bytes of uaer RAM.
• 2K bytes of user-programmable EPROM.
• Full-duplex serial operation with programmable
baud rates.
• RS232 Interface.
• 8-bit counter/timer with associeted 6-bit
prescalers.
• 124 general-purpose registers internal to the
Z8671.
• 14 I/O lines available to the user.
• 3 lines for external interrupts.
• 3 sources of internal interrupts.
• Sophisticated, vectored interrupt etructure
with progrsmmable priority levels. Each can
be individually enabled or disabled, and sll
interrupts csn be globally ensbled or
disabled.
• External memory expsnsion up to 124K bytes.
• Memory-mapped I/O capabilities.

Interfacing the Z8671 with RS232 Port
The Z8671 uses its serial communication port to
communIcate with the RS232 port. Driver and
receiver circuits are required to supply the
proper signals to the RS232 interface. The circuit
of Figure 3 shows the interface between the Z8671
and the 1488 and 1489 for serial communication via
the RS232 interface.
The serial interface does not use the control
signals Clear to Send, Date Set Ready, etc. It
uses only Serisl In, Serisl Out and Ground, so it
is a very simple interface.

This microcomputer csn be used as S microcontroller, in which csse a terminal is sttached,
via the RS232 interface, and Basic/Debug is used
to create, test, and debug the system. When the
system is debugged, the program is put into the
EPROM, the termInal disconnected, and the board
run standIng slone. The terminal can be reat751-1927-0002

The Z8671 uses one timer and its sssociated prescaler for baud rate control. When the Z8671 is
reset, it resds locatIon FFFD and uses the byte

1-78

6/18/81

Z8132

za871
PORT 10 21
PORT 11 22

ADo
ADI

9 AI

PORT 12 23
PORT 13 24

AD2

8 A2

AD3

7 A3

PORT 14 25
PORT 15 28

AD4

8 A4

ADS

PORT 1a 27
PORT 17 28

ADs

4 Aa

Ds 17
Ds 18

AD7

3 A7

D7 19

PORT 00 13
PORT 01 14

PORT 02 15
PORT 03 18

Al0

21 Al0

All

23 All

PORT 07 20

AIS

RNi
DS

DO 11
Dl 12
D2 13

D3 15
D4 18

As
As

WE
OS
AC

Vaa

2 *0.1I'F CERAMIC

Figure 1.

The Z8671 and Z61'2 Interface

za871

120
OE

74LS373
PORT 10
PORT 11
PORT 12
PORT 13
PORT 14
PORT 15
PORT 1a
PORT 17

PORT Or
PORT 00
PORT 01
PORT 02

ADo

3 Ao

ADI

4 AI

AD2

AD3

AD4

LAo 2
LAI 5

8
7

LA2 8 -

LA3 9

LA4 12
LAs 15

ADs

13 A4
14 As

ADa

LAs 18

AD7

18 A7

LA7 19

As
As

Al0

Figure 2.
751-1927-0002
-~-- ----------~---

A15

20
13

ENABLE

03
04
05
08
07

9
10
11
13
14
15
18
17

2718

CE
23

22 As
19 Al0

The Z8671 and 2716 Interface
6/18/81

1-79
---

--.-~~-~--~~~----

-------

---~ --~~~~~~--~-~~--~------

---

stored there to seled the baud rate. The board
descrlbed 1n this app11catlon note uses EPROM to
seled the baud rate. On reset, the Z8671 reads
FFFD, which is in the EPROM, and decodes the baud
rate from the contents of that location. The baud
rate can be changed 1n software.

1488
2 INPUT

80 •

Z8671

RS·232
CONNECTOR

Figure 4 shows the full board design implemented
for this applicat10n note.

1489
3 OUTPUT

INPUT

Uncommitted I/O Pins and Other Pins
Using the above design, port 2 is available for
use r appl1cat ions. Any of the port 2 pins can be
individually configured for input or output. There
are also six pins in port 3 ava1lable to the user.
The port 3 input pins can be used for interrupts.

73728 MHz

figure 3. Z8671 Interface
for Serial Communications

SOFTWARE

The RS232 port can interface to any ASCII terminal
1 f the baud rate settmg is matched to the value
programmed into the EPROM. With power supplied to
the board and the terminal connected to it, the
reset button resets the Z8671 and the prompt character appears (":").

Getting Started
The Z8671 board needs +5 V and ground to run all
components on the board except the 1488 EIA line
dr1ver. The 1488 needs +12 V and -12 V in addition
to the +5 V and ground. (If using no terminal, the
EIA dr1ver/rece1ver circuit 1S disconnected.
Consequently, the +12 V and -12 V lines are not
required.) The test board ran at 200 mAo

The board is ready for a 8asic command when the
":" appears. The following sequence is a simple
I/O example:

+5V

Vee

VEE

CS 20

14 Vee

t
~

D,
D,

1488
EIA
DRIVER

OND

INPUT

OUTPUT

L-

Z6132

800·7FFF
RAM

BUSY

V"
GND

~
~
~

~
~
~
D, ~

we OS AC Aa

D,
As AiD All Ao A1 A2 A3 A4 As A6 Ar
7
5 4 3
::: 8 08
~~t!i

2722 2625 2421 23109

I~ l:g I::~ ~;

8 •
aJ
~

ADo-ADr

> >

1621 22 23 2425 26 2728
4 RIW OS AS POOP01P02P03P1oP11P12P13P14P1sP16P11

14 Vee

8 913 1415

OUTPUT 3

GND

1489

EIA
RECEIVER

~
.W

73728
MHz

INPUT

SO
51

ADo-ADr

P21

XTAL1

P22

P2,

Z8871
MICROCOMPUTER

P2,
P2,

XTAL.2

P2e

+5V

P2,
Vee
20 19

7- - 3 _ _ 2_

+i1:

RS·232
CONNECTOR

r--1 A2

r---!' Aa

74LS373
OCTAL
LATCH

t-E ..

~
;-

t-Y As

f------! ..

"....

.....t1 ENABL.E
GND

~
P-

OarlL

LA,

f1L------!

2718
8000·PFFF

j1!-----!

o,f1!-

L.As

ROM

Osf1i-.

06~
Orr!!-

1'8

GND

I
I
:f'"~ I
RESET

"...

74LS04
INVERTER
OND

figure 4.

02r!L

L.Ar~Ar

...-1§ Ar

L.A6~A6

~A6

!4.

Vee

OE As As A10VPPVCC

LAo

LA1~ A1
L.A2~A2
L.Aa~Aa

~A1

J ----i

751-1927-0002

~
;...
;...

20 23 22 19 21 24

Vee

r--J Ao

•

1 .,81"

;..

R'EsET

P07 POs POs P04

GND

I~J,~I:~J,~U, ,f,

+i:o

The Z8 System with Basic/Debug
1-80

6/18/81

:10 input a

value 255 lnto register 4096 dsclmal (1000H). The
pr1nt commands wrlte to the terminal the values
that were put ln wlth the first two instructions.

:20 "a=u;8

:run
?5

a=5
: list
10 lnput a
20 "a=";a

Memory Environment
Table 1 gives the memory configuratlon for the
Z8671 apphcation example. Chip Select is controlled by the MSB (most slgOlflcant blt or A15)
of port O. Therefore, the RAM is selected for all
addresses between 800H (2048 declmaI) and 7FFFH
(32767 decimal). Addresses 8FF, 18FF, 28FF, 38FF,
and 78FF address the same location in RAM in this
applicatlon because of Modulo 4K.
EPROM is
select ed for all addresses from 8000H to FFFFH
and, like the RAM, several addresses point to the
same location in the PROM.

When a number is entered as the first character of
a line, the Baslc monitor stores the line as part
of a program. In thlS example, "10 input a" is
entered. Basic stores this instructlon in memory
and prints another ":" prompt. The Run command
causes execut10n of the atored program. In thia
example, BSS1C asked for input by print ing "?". A
number (5) 1S typed at the terminal. Baslc
accepts the number, stores it in the variable "a",
and executes the next lnstruction. The next
instruction (20 "a="; a) is an implied print statement; wnting an actual "prlnt" command is not
necessary here. This line of code produced the
output "a=5". The command "list" caused Basic to
display the program stored in memory on the terminal.

Table 1
The Memory Environment
Decimal

Reading Directly from Memory
Baslc lets the user directly read any byte or word
in memory uSlng the Punt command and "1Ir' for byte
references or "." for word references:

Hex

Contents

0-2047

(0-7FF)

2048-32767
32768-65536

(800-7FFF)
( 8000-FFFF)

Internal ROM
(BASIC/DEBUG)
RAM (Z6132)
EPROM (2716)

Switching from RAM to EPROM

:print 1!!8
10
:pnnthex(l!!8)

Register 8 and Register 9 contain the address of
the fnst byte of a user program or, if there is
no program, the address where the Z8671 will put
the first byte of a user progrsm. In this application example, when the Z8671 is reset, Register
8 and Register 9 contain 800H, which pOlnts into
RAM. EPROM is selected by changing the contents
of reglster 8 from 08H to 80H (See Table 2).

:printhex( .8)
AF6
The first statement prints the decimal value of
Register 8. The next statement prints the hexadecimal value of Register 8 and the last statement
prints the hexadecimal value of Register 8 (OAH)
and Register 9 (F6H).

Table 2
The Registers
Decimsl

Hex

22-23
8-9

(16-17)
(8-9)

Contents

Writing Directly to Memory
Basic lets the user write directly to any register
or RAM location in memory uSlng the Let command
and elther "cr' or ".".

Current Line Number
Address of the First
Byte of User Progrsm

:ga=1.:ff
: .4096=255
:printli1 0
255
:printhex(. %1000)
FF

For more details on the register assignments,
refer to the Pointer Registers-RAM System section
of the Z8 Basic/Debug Software Reference Manual.

The Let command is lmplled to save memory space
but can be included. The first statement loads
the hexadecimal value FF into register 10 declmal
(AH). The next instructlon loads the decimal

The example below shows how to switch from RAM to
EPROM. The example uses two separate programs,
one in RAM and one in EPROM. The RAM program is
listed first, then the EPROM.

After the instruction ".8=%8000" is executed, the
Z8671 accesses the EPROM on the Bssic/Debug Board.

1-81

751-1927-0002
~~--------

--~------'-

6/18/81

301
302
310
320
330
331
340
341
350
351
352
360
363
366
367
368
370
380
390
400

1=0
r=O:p=O
lf + j=. kp=p+l
j=j+2:k=k+2:1=1+1:lf 4 > 1310
J=%7f22:k=%7f2a
1=0
if. j=+ kr=r+l0:. j=. j+10:1=3
j=j+2
1=1+1:if4 > 1340
j=%7f22
1=0
k=k+2:if%7f31>k340
j=%7f22:k=%7f2a
if. j>9. j=. j-l0
j=j+2
if1.l7f29>j366
"right ";r;" place ";p
if4>pl00
y=999
"right in ";i;" guesses;";"play another
y/n":inputx
410 ifx=yl0

:printhex( • B)
800
: list
10 "executIng out of RAM"
: .8=%BOOO
:pnnthex( + B)
BOOO
:list
10 "executlng out of EPROM"

Baud Control
The baud rate is selected automatIcally by reading
location FFFDH and decoding the contents of that
location when the ZB671 is reset (the ZB Basic/
Debug Software Reference Manual contains the baud
rate switch settings in Appendix B). This application example holds the baud rate settIngs in ltS
EPROM. The least significant bits of location FFFD
hex wlil provide baud rates as follows:
Baud Rate

Value Read

110
150
300
1200
2400
4800
9600
19200

110
000
111
101
100
011
010
001

Lines 10 through 50 comprlse the random number
generator for the program. The three lines:
10 ®243=7
20 ®242=10
30 ®241=14
initlalize counter/tlmer 1 to operate in modulo-l0
count. Refer to the Z8 Technical Manual for complete information on initializing timers.
The "usr( 84)" function waits for keyboard input,
the ASCII value of the key is returned in a
variable with the following command:

After a reset, the baud rate is programmed by
loading a new value into counter/timer 0 (see the
Z8 Technical Manual, sectlon 1.5.7). A Reset
always changes the baud rate back to the rate
selected from the contents of location FFFD.

:10 x=usr(84) :""
:15 printhex(x)
:run
5

Burning an EPROM

The EPROM contains the baud rate selection byte in
location 7FDH. The other locations in memory are
used for program storage. See section 6.3 of the
Basic/Debug Manual for the format used to store
programs in memory. This format is used to store
programs In EPROM.

In the above example, the program waits at line 10
until keyboard input, in this case the number 5.
The input value is stored in ASCII format in the
variable "x". The line:
40 x=usr(84):a=®242-1:x=usr(84):b=®242-1

Example
The following is a printout
Mastermind written in Basic/Debug.

the

wai ts for input, reads the current value of timer
1, subtracts 1 (to get a number between 0 and 9),
and stores the number in variable a. Then it
waits for keyboard input at the second user funct ion call, reads the current value of timer 1,
subtracts 1, and stores the number in variable b.
Line 50 of the exa~p18 program gets two more random numbers and stores them in variables c and d.
The four-digit random number is located in
variables a, b, c, and d.

game

10 @243=7
20 ®242=10
30 1!11241=14
40 x=usr(84):a=®242-1:x=usr(B4):b=@242-1
50 x=usr(84):c=®242-1:x=usr(84):d=®242-1
55 "":i=O
100 "guess ",:in e,f,g,h
110 i=i+l
300 j=%7f22:k=%7f2a
751-1927-0002

Line 300 assigns the locat ion of variable a to
variable j and the location of variable e (the
1-82

6/18/81

fust variable In the guess string} lo the
variable k. The atrategy is to access these
variablea IndIrectly and to increment pOinters j
and k to access the vsriables.

CONCLUSION
The design of thIS spplication exsmple met the
major design goals of simplicity and functionality. The first goal is accomplished by prudent
selection of support components, excluding any
unnecessary chlps. The board allows the user to
exercise the full power snd flexibility of the
festures of the the Z8601 not used by Basic/Debug.
The user csn write snd debug Basic programs without detaIled knowledge of the Z8601.

A colon is used to separate commsnds on the ssme
line. This is useful in packing the progrsm into
a smsll amount of memory space. The code, however,
is harder to read. See section 5 of the Basic/
Debug manual for more InformatIon on memory
packing technIques.

The Basic application example demonstrates a
memory interface that is applicable for all Z8
Family members. The csse where there is no
address latch on the memory ChIP was discussed,
and an example of how to interface the multiplexed
address/data bus of the Z8 Family through an
address latch was shown.

Below IS a sample run of the MastermInd program: .
: run
on the
times here)
guess? 0, 1, 2, 3
right 2 place 0
guess ? 4, 5, 6, 7
right 2 place 1
guess ? 0, 2, 4, 6
right 3 place 2
guess? 4, 2, 1, 6
right 4 place 4
right in 4 guesses
play another? yin
?n
«RETURN>

keyboard is entered

QO.2151-02

~~~~~---------"--'---'.----

four

The software section explaIns the memory environment and gives several examples of Basic/Debug.
These examples are a good introduction to the
board and to Basic/Debug.
The Z8671 is a customlZed extension of the Z8601
single-chip microcomputer. The simplicity of the
Basic sppllcatlon example demonstrates the flexibility of the Z8601 microcomputer in an expsnded
memory environment.

6/18/81

1-83

.. --- ,--'.-

"','-

A Single Board Terminal
Using the Z8590 Universal
Peripheral Controller

Zilog

AppUcation Note

October 1981
INTRODUCTION

interface circu1t that was des1gned and built by
the Zilog Applicat10ns Group using the ZB590 IJ'C
l.n a ZBO system environment.
The CRT display
functJ.on was chosen due to the widespread use of
CRT displays in the data processing environment.
For further informatJ.on on the ZB590 UPC refer to
the
Zilog
Data
Book,
pUblication
number
00-2034-01.

The Zilog ZB590 Urn versal Peripheral Controller
(UPC) opens up a wide vauety of appllcations for
distnbuted processing.
One of the most useful
funct10ns of the UPC is to off-load routine process1ng tasks, such as I/O processwg, from the
CPU.
The advantages of such a distributed processing approach 1nclude greater system throughput,
more efficient use of system resources, and protocol converters that make different peripherals
look the same to the system software.
The last
advantage is particularly useful where d1fferent
hardware conf1gurations may be used with the same
software.
So long as the UPC handles the CPU
interface in the same way, the peripheral devices
attached to the UPC are transparent to the CPU.

FUNCTIONAL DESCRIPTION
This paper describes the Input/Output (I/O) part
of a computer system in l.ts most rudimentary
form. D1stributed processIng is the theme used l.n
this design so that as much of the low-level processing for I/O as possIble is performed by the
UPC.
Figure 1 shows a block dl.agram of the UPC
I/O system.

Th1s paper descubes a CRT display and keyboard
Z80 BUS

Z80
CPU

V L - - - - - - - - - - - - - - - - - - - - - , ASCII KEYBOARD
~r-------------------~INPUT

MEMORY
DISPLAY

RAM

8MC
963648

COMPOSITE
VIDEO

Figure 1. Block Diagra. of the UPC
Single Board Terlllinal

1-85

The display interfaces to a standard video monitor
by way of a composite video signal.
Charactel's
are repl'esented by dots on a l'astel' scan display
in the form of a 5 x 7 matrix. The CPU intel'face
to the UPC can hansfer characters on a single
byte basis or by a block move. So far as the CPU
loS concerned, the UPC looks like a serial port
when used in single byte mode.
This permits the
system software to remain virtually the same for a
serially-linked terminal or for the UPC. The UPC
also provides for programmable cursor control,
like that available on a standard terminal, with
the control characters being optionally selected
by the system software. When the UPC is initialized by the CPU, a bit in the mode control
word can be set to indicate that cursor control
characters will follow.
The keyboard input is
from an ASCII-encoded keyboard that has a strobe
to signal a valid character present.

A/D is High the register cUl'l'ently addressed by
the addl'ess pointer is being accessed.
The Z8590 UPC coordinates operation of the display
sect ion and the keyboal'd input with the zao CPU.
Six bits fl'om Port 1 al'e used to transfer data
from the UPC to the CRT refresh memory. The ather
two bits are used with bit 7 of Port 2 to form the
three bit command ward for the CRT controller.
Seven bits of Port 2 are used to input ASCII dat a
from the keyboal'd. Since four of the bits on Port
3 are used for lnterrupt contl'ol, the other foul'
al'e used for I/O control. Bit 3 of Port 3 is used
for the keyboal'd input stl'obe. This input generates an intel'l'upt within the UPC when the stl'obe
input goes Low, indicating valid data at the keyboard inputs. Bit 4 of Port 3 is used to control
the RAM write pulse coming from the CRT Controller
(CRTC) and going to the RAM.
When this bit is
Low, RAM wl'ites al'e inhibited for operations such
as CUl'SOl' home and CUl'SOl' retul'n. Bit 6 of Port 3
is used to genel'ate the Data Strobe (DS) for the
CRTC.
When OS goes fl'om Low to High, the three
command bits al'e latched into the CRTC. Figul'e 2
shows the UPC and interface cifcuitl'Y used.

The standard 7-bit ASCII code is supported Wloth
the negative-going strobe pulse indicating valid
data. The keyboard input loS TTL compatible and is
nat buffered into the UPC.

SYSTEM DESIGN

The heal't of the display circuit is the Standard
Microsystems CRT-96364B CRTC ChIp.
The basic
design was del'ived from the CRT -963648 data sheet
by Standal'd Micl'osystems COl'P. The CRTC contains
all the circuitry necessal'Y to genel'ate the video
timing pulses and memory address and conhol signals fol' the display RAM. The display format is
64 characters per line by 16 lines. This l'equil'es
a 1024 charactel' memol'Y which is supplied by the
2102 RAM devices. Since 64 ASCII chal'actel's are
displayed, only six bits of memory are requil'ed to
store character lnfol'mation.
The memory addl'ess
and write signals are generated by the CRTC under
control of the UPC. Data is entered into the display memory by writIng a command to the CRTC along
with the data. FIgure 3 shows the logic used with
the CRTC.

The UPC I/O project is designed to fit within an
existIng ZBO-based test bed.
Therefore, the
interface requirements include a ZBO-type interface with interrupt capabilIty. other specifications include:
•
•
•
•
•
•
•
•
•
•

Display format of 16 lines by 64 characters
5 x 7 dot matrix characters
Composite video output
ASCII character lnput from CPU
Programmable cursor control
ASCII keyboard input
Single +5V operation
Character or black transfer mode
Pl'ogrammable CPU interrupts
Programmable enable for CRT and keyboard

Within an 8 x 8 dot character cell prOVIded by the
CRT timing, only a 5 x 7 dot chal'acter is used.
The charactel's are formed using a 2716 EPROM character generator.
The lowest three bits of the
2716 EPROM address inputs fl'om the character row
count and come from the CRTC. The next SIX bits
form the character address.
Each chal'acter is
stored In EPROM as eight cont iguous bytes.
The
1'0W count addresses a row (equivalent to a byte)
within the character block. Thel'efol'e, the chal'acter addresses are modulo 8 and take a total of
512 bytes. The CRY output of the CRTC is used to
select the CUl'sor pattern in EPROM. When CRY is
Low characters are normally displayed. When CRY

HARDWARE DESIGN

The hardware desIgn encompasses three basic elements: the ZB590 UPC and processor interface section, the CRT display section, and the keyboard
input section.
The ZB590 UPC is treated as a peripheral by the
master CPU, in this case a Z80A CPU, and is
accessed using the standard Z80 I/O instructions
via two parts. One of the two parts is selected
dependIng an the state of the "A/D line. If "A/D is
Low the address pointer is being written to.
If
751-1809-0007

1-86

74LSOO.1

IACK~
lEI

L-I"

13L)

,.
198
19A

....,

1
~

14 D6

15 Ds

16 D4

2.C

208

20A

21C

12C

74LS245

15
16

c'o

P17
P"
P"

20 Do

1
2

14S04

74LS10
12"

P14

7Ao

P"
P"

74LS08
11

18 IOWAIT

iNT

ViR

P10

WAIT

A,
A,

3 C

1 A

25A

6 G1

5 G2B

26C

4 G2A

24A
25C

S'
~...

258

....~

...

7A
78

P1>l

J2·21
J2·18
K8
INPUT

Pelk.

5 ,

2"
3
~
4 :::'SOO

J2·5

Y-

3.054 MH1

8 po,

Vss

~'
8

J2·20

J2·17

9 D/A

J2·19
J2·6

P,.

~0
5J"

J2·25

lEO

118 lORa

J2·7

P,. 33
32
P21
31

3 P3l

ST8

P,. 34

4 Po.

4.7K

+5V---

r: I 1-Co

C21

CRT DATA

--]

K8 DATA

p'l I I I Is~~1 I I xl
P"

lEI

+5V

DDO

INTACK

P2tl 37

44 L n _ 6

P2S 36
35

+5V

47K#2

003
002
001

74LS138

004

24
23

+5V

2 •

:;,

lOA

~ Sht
DDS

Z8590
UPC

14804

26A

P3,

,K .4

248

P2
12

7407

4.7K 113
tV

7407

...~

P1S 26

18 0.

ViR

P27 38

19 D1

P,. 3.

4
3

1A RESET

Vee

'i"

'-l

13 D7

S;
n

DOUT

+5V

DOUT

188
18A

'U~

1/0 ADDRESS

PCLK-SHT.3

It""

,
1
·1
1·
·1
1 ·• 1
1··1
lx
1·
11 1
1 ··1
Xl

0= ADDRESS
1", DATA

1• .

DO' --1!
12
DO.
{

SHT.1

003

=:}

DD2

---.!

lK
.2

81LS97

lK
#3

lK
#•

-1-

••

•

001 ~

DDO ~

II l'.

..,

,.
1

. ,.
N2

~n
00
00

5il
....
6'

!.1

.. ""

• ••

A2 A1

CRT 96364B

S·

SHT.3

{

CRT elK

Dec

DCC

•

DCE

•3

___

--r--r--

#•

r-r--

~i- "T-1T-Tr~
12

N2 ' - 8

iil111.r.

.,"

R1 12

..I.

CRY
CSYN

..~

[' r

·r
1

+'V

05 14

Vpp

O£

••

MM2716

04 13

C.
C,

03"

02 '0

•

CSYN

DCE
DeVICE

81 LS97
2102
CRT 96364
2716
74LS174

,.•
12
8

AoAaAtAsA6 A7Ae

AID

10 [

A2 Al

-1._ -1.

•

74LS174

"' 13
15

...~

..l.-L _r"'" U

22 21 20 1• 18117

7 8
1. DS As As A7 A6 A5 A4

{

...

....

4 .......... 74LSOO

8HT.1

2102A1

.,~

=
....

~'~

r-L-L

DE _

•
• , -•
-

,,",

SHT. :

SPARES

~
74LSOO.,

~5
74LS02

4
•

~
~3

CSYN

(SHT.2)

11. A

..,
~

'i"
s;;

+6.8 F

330

"*"

~'i

COMPOSITE

Jo"'---~W---f------1II(f---------------74LS08

VIDEO OUT

jo<'

I ..

J2·4
J2·1.2.3,24

4 F
3 E

C3
C,

74LS165

14 D
+5Y

,.C

12 B

LDJSHT

or---

660

1K #7
~+5V

17 110 11

~11-2-_--~n~S04---~~----~----------

Qc RoilS

DCC} SHT.2

00
<

.
u

. ..
" ..
.

u
0

"
figure 5.

u
u

..
..

.. >

"0:
IOU
0: •

"
N
,,0:

•"

..c
C

..
0:

""
C

II!
0

CRT 963648 Ti.dng WaveforMS
1-90

.
c

"II!0
0:

.
"
"
c

is High the character 1S replaced by an underscore.

ble registers withIn the UPC, 22 (addresses 96FO
through %FF and 9600 through 9605) are specialpurpose control registers defined by the hardware.
The remaining 214 registers are generalpurpose in nature and are allocated as shown in
F1gure 6.

Five b1tS of the EPROM output are fed wto the
74LS165 Sh1ft reg1ster. This Shlft register converts the fi ve column dots wto a bit stream for
the video output signal.
Composite video is
generated by merging the video dot stream w1th the
Composite Sync (CSYN) output of the CRTC through a
resistor summing network.

CONTROL REGISTERS
%FO

STACK &
DATA AREA

The remaining circuitry supplies clocks to various
parts of the circu1t. Three elements of the 74504
form an oscillator. The output of the osci llator
goes to three places. It is d1vided by twelve by
the 74LS92 to form the 1.018 MHz clock required by
the CRT-96364B. It is also divided by four by the
74LS73 to provide the 3.054 MHz clock for the UPC.
The oscillator output is also ANDed with the Dot
Clock Enable (DCE) output of the CRTS and fed into
the 7415161 to form the Dot Character Clock (DCC)
pulses.
SInce a character cell time is e1ght
clock pulses long, the DCC 1S derived from a
divide-by-eight counter.
The d1Vl.de-by-eight
counter also loads the shl.ft register at each
character time. Figures 4 and 5 show the circuitry and waveforms for the timing and video output
circuitry.

%CO

KEYBOARD
BUFFER

%80

PARAMETER
AREA

%60

CRT
BUFFER

%20
CPU ACCESS

%10
%0

Figure 6.
The UPC emulates CRT terminal operat ions by providing keyboard data input to the master CPU as
well as CRT output. The keyboard inputs are 7-bit
ASCII encoded with TTL level signals. The Strobe
Input (s'i"B) is active Low to indicate a valid
character at the keyboard data inputs.
When STB
goes Low, an interrupt is generated within the UPC
and the data inputs are read.

~RAM
SPECIAL

UPC Internal Register Allocation

The Program (PGM) registers (registers %06 through
%OF) are general-purpose data manipulat ion registers. These are the working-set registers used to
hold data temporarily and to perform vanous comparison and calculatIon functions within the program.
The CPU access registers (%10 through 961F) are
used to facilitate communication between the UPC
and master CPU. Two bits in the status register,
CRT Busy (CRTBSY) and CPU Data Available (CPDAV),
are actually semaphores that form the key mechanisms for data interchange. The CRTBSY bit can be
set only by the master CPU and can be cleared only
by the UPC. The CPDAV bit can be cleared only by
the master CPU and can be set only by the UPC.
These will be discussed in detail 1n the master
CPU access section.

With this hardware a complete CRT terminal can be
constructed at minimal cost to the user with no
sacrifice in performance.

SOFTWARE DESIGN
The software design encompasses two areas:
the
UPC programming and the master CPU interface. The
former includes the UPC internal register organization and program initialization.
The latter
includes the data transfer protocol used between
the UPC and the master CPU.

A line of data on the CRT screen is 64 bytes
long. Therefore registers 9620 through %5F form a
64 byte line buffer for the CRT display. This is
used only in Block Transfer mode, since the UPC
receives a block of data before outputting it to
the CRT.

UPC Programming
The specif1cs of this CRT project will now be discussed, as it is assumed that the reader is familiar with the UPC in general. Of the 256 accessi-

The parameter area (registers %60 through %7F)
contains the cursor control characters and corre-

1-91

sponding informatwn.
Flgure 7 illustrates the
format of the parameter area.
SlOce there are
eight cursor control characters and each occupies
four bytes of control block information, there are
a total of 32 bytes allocated for this purpose.
Most lncoming control characters are compared with
the ASCII codes 1n thlS table, and lf a match is
found the software determlOes what to do based on
the other values in the cursor control block.

Ase 1\ CHARACTER CODE
CRT CODE*

BYTE 3

}

DELAY VALUE (MULTIPLE OF 4.2 ns)

BYTe 4

Table 1.

Internal Data Area

(CURSOR FUNCTIONS)

PARAMETER BLOCK
BYTE 1

(OTC) reglster.
ThlS enables communication with
the master CPU to take place, and indicates to the
master CPU that the UPC lS ready for operatlon.
If the EDX bit is cleared, data transfers to or
from the UPC are inhibited. At this point the UPC
waits for the Mode register to be set by the master CPU before contlnuing.

UPC
ADDRESS

CURSOR CONTROL

VAlUE

BLOCK

%CO

%C1
%C2
%C3
%C4
%C5
%C6
%C7

FLAG
UBPTR
CBCNT
COlCNT
TIMER
KBPTR
KBBPTR
CHAR

·CRT CODE
CRT COMMAND

Appendlx A contains the UPC program listing used
for thlS project. The UPC program structure conSlSts of constants declaratlOn, the main program
body, and data tables.
Withln the main program
body are routlnes for inltializatlon, the main
program loop, CRT output, keyboard input, interrupt service, and other support routlnes.

PARAMETER BLOCK IS MADE OF 8 CURSOR CONTROL BLOCKS OF 4 BYTES
EACH FOR A TOTAL OF 32 BYTES THESE OCCUPY REGISTERS %60-%7F

figure 7.

lFC Parameter Block Definition

The keyboard buffer (registers %80 through %BF)
temporanly stores data coming from the keyboard
within the UPC until the master CPU reads the
data. The keyboard buffer is used ln both character and block modes SlOce keyboard input is actually done by interrupts.
In character mode, the
buffer is simply a circular buffer that accumulates keyboard data unt il it is processed by the
master CPU.
One pointer, the Keyboard Buffer
Pointer (KBBPTR), is used to indlCate into which
location the next keyboard character will go. The
other pOlOter, the Keyboard Pointer (KBPTR), lS
used to indicate which location the next character
will be read from by the master CPU.

Master CPU Interface
The master CPU communicates with the UPC through
20 special registers.
These registers are
accessed directly by the I/O instruct ion address
in the Z8090 Z-UPC and indirect ly by a register
pointer ln the Z8590 UPC.
To read or write data
for a particular register in the Z8590, the
register pointer is fust written (ii;D line is
low) and then data (A/D line is High) is written.
Thus, a reglster access operation involves two I/O
transactions.
The register pointer is latched
within the UPC so multiple reads of a particular
reglster (such as the status register) need not
have the pointer written each time.
This is
useful when poll1ng the status bits or using a
block move lnstruction for data transfers.

Fmally, the stack and data areas (registers %CO
through %EF) are used for variable storage.
The
stack grows down from locat ion %FO and occupies
about ten bytes maximum.
The lnternal data area
contains various run-bme variables used by the
UPC program, as shown ln Table 1.

Of the twenty posslble registers accessible to the
master CPU only ten are actually used.
Figure 8
shows eight of these registers and their meanings. The Mode register (register pointer address
%00), end-of-Ilne edit character (EOl, %04), backspace edit character (BS, %05), delete-line edit
character (Dl, %06), and interrupt vector (VECT,

On power-up the UPC initlalizes the necessary
van ables, all the control registers, and loads
the default parameters lnto the parameter area.
When all this is done the UPC sets the Enable Data
Transfer (EDX) blt in the Data Transfer Control

1-92

%07) are 1nitialized once by the master CPU. The
status, CRT data (CROAT), and keyboard data
(KBDAT) registers are used to control data flow
into and out of the UPC.

OTHER MASTER CPU REGISTERS'
3

CPU ADDRESS

DTC"" %18

(INDIRECT DATA)

UPC TERMINAL

DIND = %15

CPU ADDRESS
MIV = %10

INTERRUPT VECTOR
MODE REGISTER

= %00
,E*I,US*I,P*

STATUS REGISTER

ASC II DATA

CRDAT:c %02

ASC II DATA

KBDAT

= %01

07
IE

06
IUS

DATA

BS", %05

DATA

Dl:: %06

NUll
RESET IP AND IUS
SET IUS
RESET IUS
SET IP
RESET IP
SET IE
RESET lEI

Figure 9.

VECTOR

VECT

DlC I DISwl EOM

MIC

%1E

D,
I.

= %04

EOl

*FOR CPU READ, THESE BITS REFLECT IE, IP, AND IUS INTERNAL lATCHES
FOR WRITE, THESE BITS MEAN:

= %03

DATA

NV I EOX

Note: These are accessible to
the master CPU according to
UPC specifications.

other IFC Control Registers

Next comes the mode control byte. The lower four
bits determine the operation of the UPC environment.
If CRT Enable (bit 0) is set, then data
transfers can occur from the master CPU to the CRT
display. If KB Enable (bit 1) is set, then data
transfers are enabled from the keyboard to the
master CPU. The block mode bit (bit 2) indicates
block transfer mode. This applies to both the CRT
output and keyboard input.
Block mode is used
with the powerful ZBO block I/O instructions or
with DMA.

%07

NOTE: THESE ARE ACCESSIBLE TO THE MASTER CPU
FOR READ OR WRITE OPERATIONS.

Figure 8. II'C Progra. Status
and Control Registers

The master interrupt control reg1ster (MIC) is
used by the master CPU to control the UPC interrupt condition. The upper three bits (D 7 , D6 , and
DS) correspond to Interrupt Enable (IE), Interrupt
Under Service (IUS), and Interrupt Pending (IP),
respectively, by a master CPU read. When the CPU
wr1tes these bits, their meanings change as illustrated in the table of Figure 9. The EDX bit (bit
3) is monitored by the CPU after power-up so the
CPU can determine when to initialize the UPC.

The Parameters Follow bit (bit 3) indicates whether or not eight cursor control parameter bytes
will follow. If the Parameters Follow bit is set,
then the next eight bytes sent to the UPC are the
eight cursor control characters in the following
sequence:
cursor home, cursor forward, cursor
back, cursor down, erase page, cursor return, cursor up, and erase line.
These eight bytes are
written via the DIND register. The DIND register
eight cursor control bytes are sent to the UPC
data port by a block move instruction (OTIR) on
the ZBO.

The data indirection register (DIND) is used for
block data transfers.
The next section expla1ns
this in greater detail.

This completes initializstion of the UPC by the
master CPU. Listings found in Appendix B can be
used as an example of how the master CPU uses the
UPC.

Initializing the II'C
If vectored interrupt structure is supported, the
first byte to write to the UPC 1S the interrupt
vector. This is be the B-bit vector returned by
the UPC when the master CPU generates an interrupt
acknowledge in response to an interrupt request by
the UPC. The vector register is accessed by writing a 07 hex to the UPC address port, and the
vector to the UPC data port.

Using the IFC
Of the ten registers utilized by the master CPU,
four or five are actually used for data transfer.
The status register (address 01 hex) contains two
bits that ind1cate the internal UPC status. These

1-93

bits are monitored and controlled by the master
CPU under the definition of the UPC interface protocol. The CRTBSY (bit 0) can be set only by the
master CPU and cleared only by the UPC. When the
master CPU writes data into the CRT Data register
(CRDAT, address 02 hex), it also sets the CRTBSY
bit in the status register.
This does two
things. First, it indicates to the UPC that there
is data available in the CRDAT register ready to
output to the CRT display.
Second, the busy bit
remains set and prevents further character transfers until the UPC clears the busy bit. Figure 10
shows the data flow for character mode transfers
into and out of the UPC.

The above description applies to character transfers when polling the status register continuously. Interrupts can be used with the UPC to indicate s chsnge in either status bit. If CPDAV goes
from a 0 to a 1 (set) or CRT busy goes from a 1 to
a 0 (cleared) the UPC generates an interrupt. The
interrupt service routine must poll the status
register to determine the cause of the interrupt,
however, since there is only one vector returned
in vectored interrupt mode.
If interrupts are used, then the master CPU interrupt service routine must perform several operations in addition to the data transfer(s). These
operstions involve the Master Interrupt Control
(MIC) register (sddress 1E hex).
After the dsts
transfer condition has been sstisfied in the UPC
the master CPU must reset the IP and IUS latches
within the UPC. This restores the dsisy chain to
its normal state. Then, to allow further interrupts from the UPC, the IE latch must be set.
Using bits D7 , D6' and D5 of the MIC register
(shown in Figure 9), IP and IUS are cleared by
writing 001.
IE is then set by writing 110 to
these bits.
IE is cleared by the UPC on powerup, thus the set IE command must be written to the
UPC during the initislization phase by the master
CPU so that interrupts can occur. The interrupt
operation applies to both character mode transfers
and block mode transfers.

Similar to the CRT data transfer is the keyboard
data transfer. The keyboard data register (KBDAT,
address 03 hex) contains the keyboard data loaded
by the UPC, and the CPDAV bit in the status register (bit 1) indicates keyboard data is available.
The CPDAV bit can be set only by the UPC and
cleared only by the msster CPU. When the master
CPU reads KBDAT, it also clears CPDAV in the status register.
This is also shown in Figure 10.
The sequence of events depicted in Figure 10 is
important. The order in which the registers are
accessed should be adhered to or the UPC may
chsnge or lose data unexpectedly.

Block mode data transfers are faster and more
efficient than character mode transfers.
These
transfers access the status register, as do character transfers, but the data is exchanged via the
DIN) register. DII\{) is a location pointed to by
another regiater within the UPC. Master CPU accesses to DIND automatically increment the pointer
register by one so that several consecutive register locations can be written to or read from. The
number of bytes to transfer by DIND is written by
the master CPU into CRDAT for CRT block transfers,
and read from KBDAT for keyboard block transfers.
Thus, protocol exists for CTR block data transfers, as Figure 11 illustrates.
Up to 64 bytes
may be sent or received at one time in this mode.
Both the zao .and zaooo block move instructions
work very well with this method of data transfer,
resulting in superior sytem throughput.

Character IMIde - mT IkJtput
CPU

UPC

r-Read CRTBSY" SlAT
Loop if set ....1---''---

CRDAT ..
STAT ~

Write data
Set CRTBSY

CR~BSY

= 0, IP = 1

CRTBSY

) Process data

(Begin next transfer)

Character IMIde - KB input

~CPDAV = 0
Wait in
loop or
exit

Branch if clear

CPDAV

= 1, IP = 1

.. KBDAT
Clear CPDAV

Using the Z8090 Z-II'C

STAT~ CPDAV = 0
Implementing the single board terminal on a zaooo
or za processor-based system is very easy with the
Za090 Z-UPC. The software in the Z-UPC is identical to the software in the Za590 UPC. The hardware interface to the keyboard and display cir-

(exit)

figure 10.

Character Mode Data Transfer

1-94

Block MOde (transfer handshake)
CPU

cuitry is also the same.
The only difference is
the hardware interface to the CPU and the CPU
software. The protocol and register functions are
unchanged.

UPC

Read CRTBSY
If set, Loop

CRTBSY
CRTpSY

CRDAT

Write block
length
Set CRTBSY

Read CRTBSY
Loop if set

Block output
data

STAT

(IP set 1f
CRTBSY was 1)

This paper describes the use of the Z8590 UPC in a
distributed processing environment.
System performance can be most effectively improved by dividing CPU tasks into logical functions.
Such a
task, as has been illustrated here, is a fundamental I/O operation that facilitates communication
between the user and the computer.
Other functions may include such peripheral operations as a
flexible disk controller, a PROM programmer, a D/A
or A/D converter, or a communications protocol
controller.

CRT.BSY

.. S~AT

Set CRTBSY

CRTBSY
DIND

0, set IP

STAT ~

Coupled with the powerful instruction set of the
Zilog fsmily CPUs, the Z8090 Z-UPC and Z8590 UPC
find many uses in virtually any system environment.

CRT.BSY

(begin next transfer)

Figure 11.

CONCLUSION

Block MOde Data Output to II'C

1-95

APPENHX A

UPC CRT Controller Program listing
Z8ASM
LOC

3.03
OB" CODE

STMT SOLRCE STATEMENT
1
2
3

UPC CRT TERMINAL DRIVER PROGRAM!
CRTC MODULE

4
5 COIIBTANT

6
7
8
9

10
11

12
13
14

OTC: =0
P1: =1
P2: =2
P3: =3
LC: =4
DIND: =5
lMRVAL: .%28
Il3C: =%10

50
51
52

MODE:"DSC
CRTEN:=1
KBEN:=2
BLOK:=4
PARMS:=8
STAT:=MODE+1
CRTBSY:=1
CPDAV:=2
KBOVF:=4
CRDAT:=STAT+1
KBDAT:=CRDAT+l
EOL:-KBDAT+l
BS:=EOL+l
DL:=BS+l
VECT:=DL+l
9JFF: =%20
PARAM: =%60
IoQ3UFF: "%80
STOR: "%CO
FLAG:=STOR
KBB:=l
KBDAV:=2
CRTXFR:=4
KBXFR:=8
TMRFLG:=%80
UBPTR:=FLAG+l
CBCNT:"UBPTR+1
COLCNT:=CBCNT+1
KBPTR:=COLCNT+l
KBBPTR:=KBPTR+l
TIMER: =KBBPTR+l
CHAR: =TIMER+1
MIV: =%FO
MIC: =%FE
EDX:=8
IP:=%20
lEOL: =%OD
ms: =%08
IDL: =%18

53
54

$SECTION PROGRAM

15
16
17

18
19

20
21
22
23
24
25
26

28
29

30
31
32
33

34
35
36
37

38
39

40
41
42
43
44
45
46
47

48
49

!DATA XFER CONTROL REG!
!PORT 1!
!PORT 2!
!PORT 3!
!LIMIT COUNT REG!
!DATA INDIRECTION REG!
!TIMER COUNT VALUE!
!CPU ACCESS AREA!
!MODE REGISTER!
!CRT ENABLE BIT!
! KB ENABLE BIT!
!BLOCK XFER!
!PARAMETERS FOLLOW!
!STATUS REGISTER!
!CRT BUSY FLAG!
!CPU KB DATA AVAIL!
!KB BUFFER OVERFLOW'
!CRT DATA AREA!
!KB DATA AREA!
!END OF LINE CHARACTER!
!BACKSPACE CHARACTER!
!DELETE LINE CHARACTER!
!CPU INTERRUPT VECTOR!
!CRT BUFFER AREA!
!PARAMETER TABLE AREA'
!KEYBOARD INPUT BUFFER!
!RAM STORAGE AREA!
!FLAG BYTE!
!KB BUFFER OVF FLAG!
!KB DATA AVAIL!
!CRT XFER FLAG!
!KB XFER FLAG!
!TIMER ACTIVE FLAG!
!UPC CRT BUFFER POINTER!
!CPU CRT BYTE COUNT!
!CRT COLUMN COUNT!
!KB OUTPUT BUFFER PTR!
!KB INPUT BUFFER PTR'
! TIMER VALUE!
!KB CHARACTER STORAGE (KLUGE)!
!CPU INTERRUPT VECTOR REG!
!MASTER INTERRUPT CTRL'
!ENABLE DATA XFER BIT'
! SET IP BIT!
!DEFAULT EOl!
!DEFAULT BACKSPACE!
!DEFAULT DEL LINE!

55 GLCBAL

P 0000 0290
P 0002 0219
P 0004 0293
P 0006 0293
P 0008 0206
P OOOA 0218

59
60
61

P OOOC
P OOOC 8F
P OOOD BO

.ABS
WVAL
WVAL
WVAL
WVAL
WVAL
WVAL

0
ERROR
KBINT
DUMMY
DUMMY
TIMERO
TIMER1

63
64
MIIIN PROCEDURE
65
ENTRY
66 BEGIN:
67
DI
68
CLR
RP

1-97

!ClEAR REGISTER POINTER

P
P
P
P
P
P
P

P
p
P
P
P

P
P
P

OOOF
0011
0013
0015
0017
0019
001C
001F
0022
0025
0028
002B
0020
002F
0031

130

BO
BO
BO
BO
E6
E6
E6
E6
E6
E6
6C
7C
8C
9C

p 0033 C3

CO
C7
C6
10
11
C5
C4
14
15
16
00
60
20
02
A4

8C
9C
6C
7C

68
FC
02
94
FO
10

P 003F C3
P 0041 7A

68
FC

p
P
P
P
P
P
P

44
6B
E4
76
6B
E6
E6

10
FB
17
10
lB
05
04

P 0056 44
p 0059 EB
p 005B 6C
P 005D 7C
P 005F 8C

04
FB
08
60
20

P
P
P
P
P

98
79
E7

P 0035 7A

P 0037
P 0039
P 003B
P 003D

0043
0046
0048
004B
004E
0050
0053

0061
0063
0065
0068
0069

E3
F3
06
8E
6A

80
80
00
08
18
10

10
FO
08
20
08
04

p 006B 9F

p 006C 76

P 006F 6B
p 0071 76

10
08

p 0074 6B
P 0076 06

03
0094

P
P
P
P
P

76
6B
76
6B
06

10 02
EE
CO 02
03
0008

P 0086 44
P 0089 6B
P 008B 68
p 008D 06
P 0090 BO
P 0092 8B

C7 C7
El
C7
014C
C7
D8

0079
007C
007E
0081
0083

69
70
71
72
73
74
75
76
77

78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144

CLR
CLR
CLR
CLR
CLR
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD

FLAG
CHAR
TIMER
MODE
STAT
KBBPTR.!lKBUFF
KBPTR.!lKBUFF
EOL.!lDEOL
BS.!lDBS
DL.!lDDL
DTC.!lDSC
R6.!lPARAM
R7.!lX20
R8.!lHI CCTABL
R9.!lLO CCTABL

CLEAR FLAG BYTE!
CLEAR CHARACTER!
CLEAR TIMER!
CLEAR MODE!
CLEAR STATUS!
INlT KBBPTR!

LOCI
D.JNZ
LD
LD
LD
LD

C!R6.C!RR8
R7.CLOOP
R8.!lHI TABLE
R9.!lLO TABLE
R6.!l7.FO
R7.!lXl0

!POINT TO REGS. !
!LOAD 16 REGISTERS!

LOCI
D.JNZ

C!R6.C!RR8
R7.ILOOP

!MOVE INIT CODES
! TO REG I STERS. !

OR
.JR
LD
TM
.JR
LD
LD

MODE. MODE
Z.ML
MIV.VECT
MODE.!lPARMS
Z.SKIP
DIND.!lBUFF
LC.!l8

!MODE WORD SET?!
!NO. LOOP!
!SAVE CPU INT VECTOR!
!CHECK PARAMS BIT!
!SKIP IF CLEAR!

OR
.JR
LD
LD
LD

LC.LC
NZ, MLl
R6.!l8
R7.!lPARAM
R8.!lBUFF

!WAlT FOR LC=O!

LD
LD
ADD
INC
D.JNZ

R9.C!R8
@R7.R9
R7.!l4
R8
R6.ML2

!DEFAULT EOL=CR!
!DEFAULT BS=BS!
!DEFAULT DEL LINE=CAN!
! LOAD DTC REG. !
!PTR TO CCTABLE!
!MOVE 32 BYTES!
!SOURCE!

CLCDP:
!MOVE BYTES'
!LOAD INlT TABLE!

ILCDP:

ML:

MLl:
!MOVE 8 BYTES!

ML2:

SKIP:
EI
THIS IS THE MAIN PROGRAM LOOP.
UPC ARRIVES HERE AFTER INIT AND
MODE ARE DEFINED.
LOCP:
TM
.JR
TM
.JR
CALL

MODE.!lCRTEN
Z. L1
STAT.!lCRTBSY
Z.Ll
CRT

TM
.JR
TM
.JR
CALL

MODE.!lKBEN
Z. LOOP
FLAG.!lKBDAV
Z.L2
KB

OR
.JR
LD
CALL
CLR
.JR

CHAR. CHAR
Z.LOOP
R6.CHAR
OAT OUT
CHAR
LOOP

!CRT ENABLED?!
!NO. BRANCH!
!CRT DATA AVAIL?!

Ll:
!KB DATA AVAIL?!
!NO. BRANCH!
!CHECK KB DATA!

L2:
!ECHO CHAR?!
!NO • BRANCH!

THIS ROUTINE PROCESSES CRT CHARACTERS THAT
ARRIVE FROM THE MASTER CPU.

1-98

P
P
P
P
P
P
P
P
P

0123
0124
0127
0129
012C
012F
0131
0134

EB
SF
A4
6B
56
76
6B
46
56

C4
IE
11
CO
06
11
CO

P
P
P
P
P
P

0137
013A
013C
013F
0142
0145

E5
20
56
46
46
8B

C4
C4
C4
C4
11
C1

0121

P 0147 56

C5
FB
01
04
FE
13
3F
80
02
FD

P 014A 9F
P 014B AF

P
P
P
P
P
P

014C
014F
0151
0154
0156
0156

A6
FB
A6
6B
9C
AC

E6
53
E6
41
60
08

P
P
P
P
P
P

015A
015C
015E
0161
0163
0165

A3
6B
06
00
EB
AF

69
06
E9
EA
F5

20
09

P
P
P
P
P
P
P
P
P
P
P
P
P

0166
0167
0169
016A
016C
0160
0170
0172
0174
0177
0179
017B
017E

9E
E3
9E
E3
9E
76
6B
20
56
EB
E3
46
8B

E7
OE
C3
C3
1A
89
E7
13

P
P
P
P

0180
0183
0185
0187

76
6B
BO
8B

E7
04
C3
OA

P
P
P
P

0189
018C
018E
0190

76
6B
00
56

E7
05
C3
C3

P 0193 6C
P 0195 8B

00
27

P 0197 6C
P 0199 D6
P 019C 68

79
89

20
01A4
C3

40
3F
06

221
222
223
224
225
226
227
226
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
246
249
250
251
252
253
254
255
256
257
256
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
276
279
280
281
282
283
284
285
286
287
268
269
290
291
292
293
294
295
296

JR
DI
CP
JR
AND
TM
JR
OR
AND

NZ,KB4

!YES, BRANCH!

KBBPTR,KBPTR
Z,KB32
STAT,4IXFF-KBOVF
FLAG,4IKBB
Z,KB31
STAT,4IKBOVF
FLAG,4IXFF-KBB

!COMPARE KB PTRS'
!BRANCH IF EGUAL!
!CLEAR KB OVF!
!KBB SET?!
!NO, BRANCH!
!SET KB OVF!
!CLEAR KBB!

LD
INC
AND
OR
OR
JR

KBDAT,eKBPTR
KBPTR
KBPTR,4IX3F
KBPTR,4IKBUFF
STAT,4ICPDAV
KBll

!LOAD KB DATA!
!BUMP KB PTR!

AND

FLAG,4IXFF-KBDAV !CLEAR KB DAV!

KB31:

!SET CP DAV!

KB32:
KB4:
EI
RET
THIS ROUTINE OUTPUTS DATA TO THE CRT,
IF DISPLAYABLE, ELSE TRANSLATES THE CODE INTO
CONTROLLER FUNCTION.
INPUTS: XR6-ASCII DATA
XR7-XR10 USED
OUTPUTS: NONE
DAlOUT:
CP
JR
CP
JR
LD
LD

R6,4IX20
NC,CHROUT
R6,4I9
Z,DAT2
R9,4IPARAM
Rl0, 418

!CTRL CHAR ?!
!NO, BRANCH!
!TAB ?!
!YES, BRANCH!
!POINT TO PARAM TABLE!

CP
JR
ADD
DEC
JR
RET

R6,eR9
Z, DATl
R9,4I4
RIO
NZ,DATO

!CHECK DATA AGAINST ...
! ... CTRL TABLE VALUES'

INC
LD
INC
LD
INC
TM
JR
INC
AND
JR
LD
OR
JR

R9
R7,eR9
R9
RS,eR9
R9
R7,4IX40
Z,DAT11
COLCNT
COLCNT,4IX3F
NZ,DAT5
R8,@R9
R7,4I8
OATS

TM
JR
CLR
JR

R7,4IX10
Z,DAT12
COLCNT
DAT5

!CLEAR COLCNT ?!
!NO, BRANCH!

TM
JR
DEC
AND

R7,4IX20
Z,DAT5
COLCNT
COLCNT,4I'Yo3F

!DECR COLCNT?!
!NO, BRANCH!

LD
JR

R6,4I0
OUTP

LD
CALL
LD

R6,4IX20
CHROUT
R6,COLCNT

DAlO:

DAT1:

DAT11:

!LOOP UNTIL ... !
!EXIT IF NO MATCH!
!GET CRTC!
!GET NO SCROLL VALUE!
!POINT TO SCROLL VALUE'
!INCR COLCNT ?!
!NO, BRANCH!
!EOL ?!
!NO, BRANCH!
!LOAD SCROLL DELAY VAL'
!SET WRITE ENABLE'
!OUTPUT CTRL CODE!

DAT12:

DATe:
DAr.!:

1-100

!MODULO 64!
!OUTPUT TO CRTC!
LOAD SPACE!
DATA TO CRTC!
CHECK COLUMN COUNT!

P 019E 56
P 01Al EB
P 01A3 AF

P
P
P
P
P
P
P
P
P

01A4
01A6
01A8
01AB
01AD
OlAF
01B2
01B4
01B7

E6
F4

BO
20
56
EB
BC

EB
C3
C3
02
04

26
7C
D6
BC

E6 20
OF
01BE
07

P 01B9 00
P 01BB EB
P 01BD AF

EB
FC

P
P
P
P
P
P

01BE
01Cl
01C3
01C6
01C9
01CB

76
EB
56
76
6B
46

CO
FB
03
E7
03
03

P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

01CE
01Dl
01D3
01D6
01DB
01DA
01DC
01DF
01El
01E3
01E5
01EB
01EB
01EE
01Fl
01F4
01F6
01FB
01FA
01FD
0200
0203

56
9B
56
EO
EO
A8
56
42
69
EO
56
56
44
B6
B6
42
6B
B9
46
E6
46
00

E6
E7
E9
E9
E9
E9
EA
6A
01
E9
E9
02
E9

03
03
BB
OD
C6
CO
F4
Fl
C6

BO
EF
OB
10
3F
07

BO
7F
02
40
40

BO
2B
03

P 0205 AF

P 0206 44
P 0209 6B
P 020B E6
P 020E 46

C6
09
F4
Fl

C6
2B
03

297
29B
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
31B
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372

R6 ••7
NZ.DAT2

AND
.JR
RET

!MODUlO B?!
!NO. lOOP!

THIS ROUTINE OUTPUTS A DISPLAYABLE CHARACTER
TO THE CRT. IF COlCNT • EOl (64) THEN DELAYS
FOR SCROll. ELSE. NO DELAY.
CHRJUT:

CRQJTl:

CRQJT2:

ClR
INC
AND
.JR
LD

RB
COlCNT
COlCNT •• X3F
NZ.CROUTl
RB •• 4

! INIT DELAY VALUE!

!SCROll DELAY VALUE!

SUB
LD
CALL
lD

R6 •• X20
R7 •• XOF
OUTP
Rll •• 7

!REMOVE ASCII BIAS!
!CRTC COMMAND!
!DATA TO CRT!
!DElAY CHAR TIME!

DEC
.JR
RET

Rll
NZ.CROUT2

!MODUlO 64!

THIS ROUTINE DOES THE ACTUAL DATA WRITE TO
THE CRT CONTROLLER CHIP.
INPUTS: XR6-ASCII DATA
XR7-CRT COMMAND
XR8=TIMER DELAY VALUE
XR9-Rl0 USED
OUTPUTS: NONE
OU1P:
TM
.JR
AND
TM
.JR
OR

FLAG ••TMRFLG
NZ.OUTP
P3 •• XEF
R7 ••B
Z.OUTl
P3 •• Xl0

!CHECK TIMER FLAG!
!lOOP IF BUSY!
!ClEAR WRITE ENABLE!
! WR ITE ENABLE?!
!NO. BRANCH!
!RAM WRITE ENABLE!

AND
lD
AND
RR
RR
lD
AND
OR
lD
RR
AND
AND
OR
XOR
XOR
OR
.JR
LD
OR
LD
OR
DEC

R6 •• X3F
R9.R7
R9 ••7
R9
R9
Rl0.R9
Rl0 •• lC.CO
R6.Rl0
Pl. R6
R9
R9 ••7.BO
P2 •• lC.7F
P2.R9
P3 •• lC.40
P3 ••lC.40
RB.RB
Z.OUT2
TIMER. RB
FLAG ••TMRFLG
TO ••THRVAL
TMR ••3
TIMER

!MASK UPPER BITS!

OUT1:

!MASK lOWER 3 BITS!
!MERGE COMMAND BITS!
!OUTPUT DATA Ir CMD!
!GET UPPER CMD BIT!
!ClEAR COMMAND BIT!
!WRITE UPPER CMD BIT!
!GENERATE DS!
!ZERO TIMER VALUE?!
!YES. SKIP!
! LOAD TI MER!
!FLAG TIMER BUSY!
!LOAD TIME CONSTANT!
!START TO!

OU1'2:
RET

INTERRUPT ROUTINES

TII'ERO:
OR
.JR
LD
OR

TIMER. TIMER
Z.DElAYl
TO •• TMRVAL
TMR ••3

!SEE IF TIME DONE!
!BRANCH IF DONE!
!ELSE. RESET TIMER!
!LOAD Ir ENABLE TIMER!

1-101
-~-

.. ---.-

._"=---.. -."'. . .

--.-.~--

""'---~-~-.-~

P 0211 00
P 0213 BF

P 0214 56
P 0217 BF

P 0218 BF
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P

0219
021B
021E
0221
0223
0226
0228
022B
022D
022F
0232
0234
0237
0239
023C
023E
0241
0243
0246
0249
024C
024E

F8
56
76
EB
76
6B
76
EB
F9
A4
6B
A4
6B
A4
6B
F5
20
56
46
A4
EB
46

02
EF
CO
33
10
33

P 0251 46
P 0254 8B

CO
39

P 0256 46
P 0259 8B

CO
34

P
P
P
P
P
P
P
P

025B
025E
0260
0263
0266

F5
20
56
46
46
0269 A4
026C 6B
026E 8B

EF
C5
C5
C5
CO
C4
E3
IF

P
P
P
P
P

0270
0273
0275
0278

F5
20
56
46
027B SB

EF
C5
C5
C5
D9

P
P
P
P
P
P

027D A4
0280 6B
0282 00
0284 56
0287 46
028A 8B

C4
OD
C5
C5
C5
03

P 028C E6

24
C7
14
3C
15
44
16
4E
EF
C5
C5
C5
C4
41
CO

P 028F BF
P 0290 E8
P 0292 BF
P 0293 BF

P 0294 0000

7F
01
04
02
EF
EF
EF
C5
3F
80
C5
02

3F
SO
02
C5

C5
3F
80
C5
3F
80
80

373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429

!BUMP TIME COUNT!

DEC
IRET

TIMER

AND
IRET

FLAQ ••XFF-TMRFLG!CLEAR TIMER BUSY FLAG!

DELAY1:

TII'ER1 :
IRET
KBINT:
LD
AND
TM
.JR
TM
.JR
TM
.JR
LD
CP
.JR
CP
.JR
CP
.JR
LD
INC
AND
OR
CP
.JR
OR

R15.P2
R15 •• X7F
FLAG ••KBB
NZ. KBII
MODE •• BLOK
Z.KBI3
STAT ••CPDAV
NZ. KBI2
CHAR.RI5
R15.EOL
Z. KBI4
R15.BS
Z.KBI5
R15.DL
Z. KBI6
.KBBPTR.R15
KBBPTR
KBBPTR •• X3F
KBBPTR •• KBUFF
KBBPTR.KBPTR
NZ.KBI7
FLAG •• KBDAV

!QET KB CHAR!
! MASK UPPER BIT!
!KBB SET?!
!YES. BRANCH!
!BLOCK MODE?!
!NO. BRANCH!
!CP DAV?!
!YES. BRANCH!
!ECHO TO CRT!
!EOL?!
!YES. BRANCH!
!BACKSPACE?!
!YES. BRANCH!
! DELETE L1 NE? !
!YES. BRANCH!
!STORE CHAR!
!BUMP KBBPTR!

OR
.JR

FLAG ••KBB
KBI7

!SET KBB!

OR
.JR

FLAG ••KBDAV
KB17

!SET KB DAV!

LD
INC
AND
OR
OR
CP
.JR
.JR

eKBBPTR.RI5
KBBPTR
KBBPTR •• X3F
KBBPTR •• KBUFF
FLAG ••KBDAV
KBBPTR.KBPTR
Z.KBI2
KBI7

!STORE CHAR!

LD
INC
AND
OR
.JR

.KBBPTR.R15
KBBPTR
KBBPTR •• X3F
KBBPTR •• KBUFF
KBI1

!STORE CHAR!

CP
.JR
DEC
AND
OR
.JR

KBBPTR.KBPTR
Z.KBI7
KBBPTR
KBBPTR •• X3F
KBBPTR •• KBUFF
KBI7

!EOB?!
!YES. SKIP!

KBBPTR •• KBUFF

!RESET KBBPTR!

!EOB?!
!NO. BRANCH!
!SET KB DAV!

KBI2:
KBU:
KBI3:

!SET KB DAV!
!EOB?!
!YES. BRANCH!

KBI4:

KBI5:

430

431
432
433 KB16:
434
435 KB17:
436
437
438 ERROR:
439

IRET

R14.DTC
!CLEAR ERROR BITS!
LD
IRET
441
442 DUI't1Y:
443
IRET
444
445 ! REGISTER DATA TABLE FOR INITIALIZATION!
446
447 TALE:
448
WVAL
XOOOO

440

1-102

P
P
P
P
P
P
P

0296
0298
029A
029C
029E
02AO
02A2

OOA2
OOAO
7FC7
0007
0033
0000
08FO

P 02A4 01
P 02A5 10
P 02A6 4000
P 02A8 06
P 02A9 47
P 02AA 0004
P 02AC 08
P 02AD 24
P 02AE 0000
P 02BO OA
P 0281 OA
P 02B2 0400
P 02B4 OC
P 02B5 18
P 02B6 4000
P 02B8 00
P 02B9 11
P 02BA 0200
P 02BC 1A
P 02BD 06
P 02BE 0000
P 02CO OB
P 02C1 10
P 02C2 0400
P 02C4

449
WVAL
"00A2
450
WVAL
"OOAO
WVAL
451
"7FC7
452
WVAL
"0007
453
WVAL
"0033
454
WVAL
"0000
455
WVAL
"08FO
456
CURSOR CONTROL DEFAULT PARAMETER TABLE
457
458
SETUP AS FOLLOWS:
459
BYTE 1 - ASCII CHAR CODE
460
2 - CRT CODE
3 - NOT EOL DELAY VALUE
461
462
4 - EOL DELAY VALUE (FOR SCROLL) !
463
464 CCTABL:
! CURSOR HOME!
465
BVAL
"1
466
BVAL
"10
467
WVAL
"4000
468
469
BVAL
!CURSOR FORWARD!
"6
470
BVAL
"47
471
WVAL
"0004
472
!CURSOR BACK!
473
BVAL
"8
474
BVAL
"24
475
WVAL
"0000
476
477
BVAL
! CURSOR DOWN!
"OA
478
BVAL
"OA
479
WVAL
"0400
480
!PAQE ERASE!
481
BVAL
"OC
482
BVAL
"18
483
WVAL
"4000
484
BVAL
! CURSOR RETURN!
485
"00
486
BVAL
"11
487
WVAL
"0200
488
489
BVAL
!CURSOR UP!
"lA
490
BVAL
"6
491
WVAL
"0000
492
!ERASE LINE!
493
BVAL
"OB
494
BVAL
11:10
495
WVAL
"0400
496
497
END MAIN
498 END CRTC

° e1'1'01'Scomplete

A$sembl~

1-103

APPOOIX B

zao
LOC

OB.J CODE M STMT

Test Progr811 Listings for SBT

SOU~E

UPC.INIT
STATEMENT

ASM 5.9

Z80 CODE TO TEST UPC CRT CONTROLLER

2
3

4
5

60
7
8
9

10
11

12
13
14
15
160

17
18
19
20
21
22
23
24
25
0000

KBEN
CR1'EN
IN1'EN
BLOCK
PRI'S

EOU
EOU
EOU
EOU
EOU

RAM
CPCRT
OPCRT
OTC
01110
MIC
MOlE
STAT
CRJli!IT
KBJli!IT
EOL
BS
OL

EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EOU
EGU
EOU
EOU
EOU

2000H
10H
CPORT+l
lSH

MOOE+l
STAT+l
CRDAT+l
KBDAT+l
EOL+l
BS+l

I UPC PORT AD DR
I UPC DATA PORT
IDTC CONTROL REGISTER
IDATA INDIRECTION REG
IMASTER INT CONTROL
I MODE REG
I STATUS REG
I CRT DATA REG
I KB DATA REG
lEND OF LINE CHAR
I BACKSPACE EDIT CHAR
lDELETE LINE EDIT CHAR

CPJli!IV
CRTBSY

EOU
EOU

2
1

ICP DATA AVAIL FLAG
ICRT BUSY FLAG

ORG

LD
LO
OUT

SP,RAM+b4
A.MIC
(CPORT), A

s INIT SP
IPOINT TO EOX BIT

IN
BIT
.JR

A. (DPORT)
3.A
Z.BON

sLOOP IF NOT SET

LD
OUT
XOR

A.MOOE
(CPORT), A

I WRITE MODE

260

0000
0003
0005

314020
3E1E
D310

0007
0009
OOOB

DB 11
CB5F
28FA

0000
OOOF
0011

3EOO
0310
AF

27
28
29
30
31
32
33
34
35

-1
-1

o
-1
-1

15H

lEH

KB INPUT ENABLE SW.
CRT OUTPUT ENABLE SW.
INTERRUPT ENABLE SW.
BLOCK MOVE ENABLE SW.
PARAMTERS TEST SW.

BEGIN:

BGN:

360

37
38

0012
0014
00160

Fb02
FbOl
Fb04

42
43
48
49
54

001A

*L ON

!!is

600

0018

*L ON
*L ON

F60S

9311

605
6060

I SET KB ENABLE BIT
I SET CRT ENABLE BIT

lSET BLOCK MOVE BIT

OUT

(DPORT),A

LD
OUT
LD
LD
LD
OTIR

A, DIND
(CPORT).A
C.OPI:lII!T

CALL

KBIN

lREAD KB DATA

LD
OUT

A.STAT
(CPORT) , A

lCHECK CP DAV

A. (OPORT)

*L ON
*L ON

001C
001E
0020
0023
0025
0027

3£15
9310
21B1Q0
eE11
06008

EDB3

0029
002B

3EOl

0020

DB 11

D310

70
71
72
73
74
7S

760

80
81
84
85
90
91
92

*L ON

LOCP1:

l WRITE PARAMTERS

HL,P~8LK
B,PftMEND-P~MBLK

LOCP:
*L ON
*L ON

1-105

002F
0031
0033
0035
0037
0039
003A
003B
003D
003F
0041
0044
0046
0048
004A
004C
004E
0050
0052
0053
0054

E602
2BFA
3E03
D310
DB 11
47
57
3E15
D310
OEll
21BAOO
EDB2
360A
3EOl
0310
0B11
E6FD
D311
42
04
04

0055
0058
005A

C07900
3EOl
D310

005C
005E
0060
0062
0065
0067
0069
006B
006D
006F
0071
0073
0075

OBll
E601
20FA
21B900
OEll
3E15
D310
EDB3
3E01
0310
DB 11
F601
D311

0077

18BO

0079
007B
0070
007F
0081
0083
00B5
00B7
OOBB
OOBA
OOBC
OOBE
0090

3EOl
0310
DB 11
E601
20FA
3E02
0310
78
D311
3EOl
D310
0B11
F601

95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
120
121
126
127
128
133
134
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
159
160
161
162
165
166
167
168
169
170
171
172
173
176
177
178
179
180
181
182
183
184
185
IB6
IB7
18B
IB9
190
191
192

*L ON

AND
.JR
LD
OUT
IN
LD
LD
LD
OUT
LD
LO
INIR
LO
LD
OUT
IN
AND
OUT
LD
INC
INC

CPDAV
Z,LOOP1
A,KBDAT
(CPORTl, A
A, (DPORTl
B,A
D,A
A,DIND
(CPORTl, A
C,OPORT
HL,HSSG+l

CALL

CRTOUT

LO
CALL

HL. HSSG
SO

B,HSGEND-HSSG

CALL
LD
OUT

CRTOUT
A,STAT
(CPORTl. A

IN
AND
.JR
LD
LD
LD
OUT
OTIR
LD
OUT
IN
OR
OUT

A, (DPORTl
CRTBSY
NZ,DELAY
HL,HSSG
C,DPORT
A,DIND
(CPORTl, A

.JR

LOOP

LD
CP
RET
LD
CALL
INC
.JR

A, (HL)
B,A
CRTOUT
HL
SO

LO
OUT

A,STAT
(CPORTl, A

IN
AND
.JR
LD
OUT
LO
OUT
LO
OUT
IN
OR

A, (DPORTl
CRTBSY
NZ, CRTl
A,CROAT
(CPORTl, A
A,B
(OPORTl, A
A,STAT
(CPORTl, A
A, (OPORTl
CRTBSY

*L ON
*L ON

(HL),OAH
A,STAT
(CPORTl, A
A, (OPORT)
OFFH-CPOAV
(DPORTl, A
B,O
B
B

*L ON

DELAY:

A,STAT
(CPORTl, A
A, (DPORTl
CRTBSY
(DPORTl, A

• LOOP UNTI L SET
.GET BYTE COUNT
SAVE IN B
• COPY TO D
I READ DATA LINE
I

• THEN CLEAR CPDAV

RESTORE BYTE COUNT
• ALLOW LF CHAR
I

,OUTPUT CRT DATA

,WRITE BLOCK LENGTH
I WAIT FOR CRT

,WRITE TO DIND
,THEN SET CRT BUSY

*L ON

*L ON
SO:

'.'

*L ON
CRlOUT:
CRT1:

1-106

,REAO CRT

, LOOP IF BUSY
, THEN OUTPUT DATA

THEN FLAG CRT BUSY

0092
0094

D311
C9

0095
0097

3EOl
D310

0099
009B
009D
009F
OOAl
00A3
00A5
00A6
00A8
OOAA
OOAC
OOAE
OOBO

DB 11
E602
2BFA
3E03
D310
DB 11
47
3EOl
D310
DB 11
E6FD
D311
C9

0081
00B2
00B3
00B4
00B5
00B6
00B7
OOBB

01
02
03
04
05
06
07
08

00B9
OA
OOBA
OD
OOBB
54484520
DOGS TAIL'
OOED
24

193
194
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236

OUT
RET

(DPORTl. A

LD
OUT

A.STAT
(CPORTl. A

READ UPC STATUS

IN
AND
.JR
LD
OUT
IN
LD
LD
OUT
IN
AND
OUT
RET

A. (DPORTl
CPDAV
Z. KBI1
A.KBDAT
(CPORTl. A
A. (DPORTl
B.A
A.STAT
(CPORTl. A
A. (DPORTl
OFFH-CPDAV
(DPORTl.A

CP DAV?

NO. LOOP
ELSE. READ DATA

CLEAR CP DAV

*L ON
KBIN:
KBI1:

*L ON
PRI'IILK: DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
DEFB
PRI'END: EQU

1
2
3
4
5
6
7
8

•

HOME
FORW
BACK
DOWN
ERASE PAGE
RETURN
UP
ERASE LINE

MSsg:
DEFB
DEFB
DEFM
MSCEND: DEFB
END

OAH
ODH
'THE QUICK BROWN FOX .JUMPED OVER THE LA

'.'
BEGIN

1-107

APPEH)lX C
Internal UPC Organization

PORT 1

PORT 2

v
KEYBOARD DATA
PORT 3

FF
CHAR

CTRL REGS.

FO
TIMER

STACK & STORAGE

KBBPTR
KBPTR

KB BUFFER
COLCNT

CBCNT

PARAMETER AREA

UBPTR

FLAG
CRT BUFFER

20
DSC

1
W. REGS. & PORTS

figure C-1.

Port and Data Definitions for UPC

FLAG

CRT COMMAND
CC TABLE
ASCII

ASCII CHARACTER

CRTC

CRT CODE

NOT

EOl
EOL

Figure C-2.

}

1 CURSOR CONTROL
CHARACTER ENTRY

} DELAY VALUE

UPC Status Bytes and Cursor Control Table

1-109

1-110

00-2163-01

ZSO®S·Bit Microprocessor Family

Z80® CPU

Zilog

VI.

6502 CPU

Benchmark Report

July 1981
INTRODUCTION

verify without much effort. The programs have been
optimized for each processor.

With the variety of microprocessors available
today, it is often difficult for users to know
which one best suits their needs. The choice can
be based on a number of factors, such as unit
cost, throughput, code density, ease of programming, compatibility, software and hardware support, and availability of second sources.

COMMON CHARACTERISTICS Of THE l80 AND THE 6502
The zao and the 6502 are 40-pin microprocessors.
The two processors are clearly similar in many
respects. They transfer data to and from external
components on an a-bit data bus. Memory is
addressed by a 16-bit address bus. Each processor
has various registers that are used for specific
functions, such as a 16-bit Program Counter, an
a-bit status register, a Stack Pointer, and an
accumulator. The zao and 6502 both have mask able
and nonmaskable interrupt capabilities, both have
on-chip clocks, and they can both interface to
asynchronous as well as synchronous external
devices.

In high-volume applications (with quantities
exceeding 10,000), the cost of parts, especially
of memory, is extremely critical. The right
microprocessor should be able to interface to
low-cost memory components and should be efficient
in its use of memory. In other applications where
a large software development effort is required,
the cost of such an effort may be of more consequence than the cost of parts. Therefore, in
software intensive applications, a microprocessor
should be evaluated for its ease of programming.
In some applications, a particular task must be
done very rapidly, or a large number of tasks must
be executed in a small amount of time. Some processors perform particular tasks much faster than
others, whereas some might not be as fast at a
particular task, but are generally faster than
others when a large group of tasks is executed.
Unfortunately, a user might have to choose a
particular processor because it is the only one
that can perform a particular task fast enough,
even though it may be less memory' efficient and
more difficult to program than other processors.

DISTINGUISHING CHARACTERISTICS OF THE l80
AND THE 6502
Table 1
zao and
appears
than the
examined

Table 1. Distinguishing Architectural Features

This report compares the capabilities of two
microprocessors: the zao and the 6502. aoth have
many characteristics in common, but they also have
a number of very significant differences. These
differences will be discussed in detail, and their
significance in terms of memory usage, number of
lines of code (ease of programming), and execution
speed will be measured by a group of benchmark
programs.

1•
2.
3.

4.
5.
6.
7.
a.

Ten different benchmark programs are presented
here. They represent many tasks commonly performed by microprocessors, yet are short and
simple enough for the reader to understand and
751-1955-0002

lists the distinguishing features of the
the 6502. At fi rst glance, the zao
to have significantly greater resources
6502. Each of these resources should be
to determine their relative importance.

2-3

Number of a-bit general-purpose
registers
Number of 16-bit general-purpose
registers
Number of functionally distinct
instructions
Number of addressing modes
Vectored interrupt capability
Separate I/O addressing space
Stack space
Dynamic memory refresh capability

l80

6502

7
yes
yes
64K
yes

10
no
no
256
no
6/12/a1

MAIN REOISTER S.,.

ALTERNATE REGISTER SET

ACCUMULATOR

GENERAL PURPOSE

C' GENERAL PURPOSE

•

ACCUMULATOR

F FLAG REGISTER

•

QENERAL PURPOSE

C GENERAL PURPOSE

GENERAL PURPOSE

E GENERAL PURPOSE

GENERAL PURPOSE

H GENERAL PURPOSE

L GENERAL PURPOSE

GENERAL PURPOSE

-+--

.'
L'

FLAG REGISTER

OENERAL PURPOSE

GENERAL PURPOSE

8 BITS - - - - .

Z-80

16 SITS

ACCUMULATOR

INDEX REGISTER

IX INDEX REGISTER

IV INDEX REGISTER

SPECIAL PURPOSE REGISTERS

SP STACK POINTER

STACK POINTER

PC PROGRAM COUNTER

P
I INTERRUPT VECTOR

R MEMORY REFRESH

" 4 - - - 8BITS~

Z-80

PROGRAM COUNTER

...t - - - - - - - 1 6 · B I T S - - - - - -••

Figure 1.

6502 Register ConfIguration

One of the most striking differences between the
Z80 and the 6502 is the number of registers each
hss (Figure 1). Excluding the Program Counter,
Stack Pointer, and Status (Flag) register, the zeo
has 14 general-purpoae registera and four
apecial-purpose regiaters, and the 6502 has one
accumulator and two index registers.

The Z80 can pair its general-purpose 8-bit registers, forming six 16-bit registers in addition
to its two 16-bit index registers. The term
"index" used to describe the Z80 registers IX and
IV is somewhat of a misnomer. The real usefulness
of registera IX and IV is in base regiater
addressing. Benchmark program number 10 (See
Appendix B) illustratea the use of register IX in
acceasing specific bytea within a variably located
(dynamic) memory block.

Regiaters in the CPU can be acceased much more
rapidly than external memory; therefore, the more
data that can be kept and manipulated in regiters,
the faater a program can execute. A program,
however, consists of instructiona that are located
in external memory, and all data muat, at one time
or another, be transferred to or from external
memory.
If a CPU could be designed to work
rapidly and efficiantly with external memory, the
importance of a large regiater set would be
diminished.

Tha 6502 index registers are very useful in
indexing small data structures. Being only 8-bits
long, however, the 6502 index registers cannot be
used in data structures of more than 256 bytes,
except by breaking larger structures down into 256
byte sections (pages), aa illustrated in benchmark
programs 4, 5 and 9 (see Appendix C).
The 6502 design concentrates on quick and efficient exchanges between registers and external
memory. This ia evident in the large number of
addreasing modes.
Nearly all of the 6502
instructions can address memory directly (absolute
addressing), and many instructions have indexed
addressing. A number of 6502 instructions have a
special form of pre- and post-indexed indirect
addressing as well.

The most disturbing aspect of the 6502 register
set is not the number of registers, but the size
of each. All of the programmer sccessible registers in the 6502 are eight bits long. This is a
problem because the 6502 has 16-bit sddressing
just like the Z80 has, and without 16-bit registers, the 6502 provides no convenient mechsnism
for manipulating addreases.
751-1955-0002

STATUS REGISTER

2-4

6/12/81

modes increases. Instructions whose opcodes imply
the operands, as in Register and Indirect Register
Addressing, need only be one byte long, whereas
instructions with other addressing modes, such as
Direct, Indirect, Base Page, and Indexed, must
further contain the address itself and so are two
or three bytes long. A comparison of the ZBO and
the 6502 is a perfect example of this point: when
operand combinations are considered, the ZBO has
202 different one-byte instructions, and the 6502
has only 29 one-byte instructions (see Table 2).

An interesting feature of the 6502 is its Base
Page (or Page Zero) Addressing mode. In Base Page
Addressing, the upper B-bits of the 16-bit address
are assumed to be zero. This mode is therefore
onl y applicable to the first 256 bytes of memory.
The advantage of Base Page Addressing is that only
one byte is needed to specify an address. With
single-byte addressing, instructions can be
shorter in length and therefore can e,xecute faster
than instructions containing 16-bit addresses.
The base page assumption is also available in the
indexed addressing modes.
In the pre- and
post-indexed indirect addresssing modes referred
to above, the location of the indirect address is
always assumed to be in page zero. Pre-indexed
indirect addressing works only with index register
X, and post-indexed indirect addressing works only
with index register V. All of these addressing
modes are very important and very useful,
especially when dealing with the first 256 bytes
of memory.

Table 2.

zao
Average number of bytes
per instruction
Number of instructions
taking
1 byte
2 byte
3 byte
4 byte

Another interesting characteristic of the 6502 is
that its Stack Pointer is only eight bits long.
An B-bit Stack Pointer allows 256 bytes of stack
space, which is sufficient for many applications.
However, there are applications that require more
stack space, and these applications would not be
able to use the 6502. The 6502 stack space is
dedicated to page one (the second lowest 256 byte
area of memory). As with base page addressing,
the upper byte of the 16-bit stack address is
implied and need not be computed during stack
accesses. Instructions in the 6502 that deal with
the stack, however, use the Stack Pointer
indirectly, so no savings in the length of the
address field can be attributed to the stack
limitation.

29
74
4B
0

The number of instructions a processor has and the
usefulness of those instructions are important
factors in the number of instructions required to
perform a particular task.
Other important
factors are the addressing modes and the number of
accumulators or registers capable of being the
destination of arithmetic operations. The more
accumulators a processor has, the fewer extraneous
instructions are needed to move data to where it
can be manipulated. The 6502 has one B-bit
accumulator through which every add and subtract
operation must pass. The zao, on the other hand,
has two B-bit accumulators (A and A') and four
16-bit registers that can be the destination of
arithmetic operations (Hl, HL', IX, and IV).
Both the ZBO and the 6502 have interrupts. The
ZBO has the additional capability of automatically
vectoring to up to 12B different programmable
locations when interrupts occur. An B-bit jump
table vector is automatically asserted by Zilog
2-5

202
344
74
76

2.13

In the ZBO, 16-bit registers are useful not only
in addressing but also in manipulating 16-bit
data. The ZBO provides instructions to add, subtract, increment, decrement, load, store, and
exchange 16-bit registers. The 6502 has no 16-bit
data manipulation instructions. Manipulating
16-bit data with the 6502 usually requires several
more instructions than equivalent operations with
the ZBO.

Addressing modes are not realized without cost.
Every instruction a processor has must be represented by an opcode. One of the most fundamental
factors affecting the efficiency of a processor is
its instruction encoding. It is important to keep
instructions as short as possible, because the
length of instructions affects the amount of
memory used by a program and the program execution
time. If the opcode size is held to a fixed
length, such as one byte, the number of possible
instructions decreases as the number of addressing

~---~------~-.,----.

2.03

6502

*Instruction counts here include permutations of
operand possibilities including registers and
addressing modes but not permutations of memory
addresses.

The ZBO has one very important addressing mode not
found in the 6502, referred to as Indirect Register Addressing. In this mode, the operand is in
a memory location speci Hed by the address
residing in a 16-bit register pair. With a 16-bit
address, this mode can cover the entire memory
space of the ZBO. Since the register holding the
address is a pair of B-bit registers, the upper
and lower halves can be manipulated independently
to access different bytes within a page or the
same byte in di fferent pages. Another important
quality of Indirect Register Addressing is that
instructions using this mode need to specify only
the register pair and not the address itself. This
allows instructions to be shorter than instructions using other addressing modes.

751-1955-0002

Instruction length Data*

6/12/B1

Z80 peripherals. Vectoring reduces interrupt
response time by eliminating the need for software
polling to determine the source of an interrupt in
multiple interrupt systems. The Z80 also has nonvectoring interrupt modes for use in less complex
systems. The 6502 has no interrupt vectoring
capability.

ZBO to add discrete clock cycles to its access
t1m1ng. The 6502 can interface to slower components by controlling the clock directly, but doing
so requires much more critical timing considerations than the method used with the Z80, and it
defeats the usefulness of the 6502's internal
clock circuitry. Moreover, variations in the main
clock might not be tolerable to other devices in
the system.

Another important difference between the two CPUs
in question is the way they address input and
output. The 6502 has no special provisions for
I/O addressing and simply interfaces to input and
output devices as part of its memory space. This
is referred to as memory-mapped I/O. The Z80 has
specific I/O instructions and a specific I/O
address space of 256 bytes in addition to its
memory addressing space.
Keeping I/O in a
separate addressing space keeps the main memory
map clear and reduces the chances of an output
device being erroneously written to by runaway
programs.
If the need for memory-mapped I/O
addressing ever arises, the Z80 can accommodate
the need in the same manner as the 6502.

Interfacing the 6502 to program memory that cannot
respond at full speed ~s futile, because 90 percent of the 6502 clock cycles are typically program memory accesses and little would be gained by
extending those cycles. It is, however, quite
productive to use a high-speed l80 with program
memory that cannot respond at full speed, because,
typically, less than 25 percent of the Z80 clock
cycles are program memory accesses and extending
those cycles would have relatively little effect
on overall execution speed.
BENCHMARK RESULTS

Dynamic memory is used in many microprocessor
applications. The Z80 can refresh dynamic memory
automatically without special refresh circuitry.
This feature can reduce the cost of a board by
decreasing the number of components needed. The
6502 has no refresh capability. Moreover, it is
particularly difficult to interface the 6502 with
dynamic RAM because of the critical nature of its
memory access timing.

There are so many factors involved in ascertaining
a processor's capabilities that it is difficult
to determine speci fic figures without actually
writing benchmark programs. When evaluating a
processor for use in a particular application, the
user should use programs representative of his or
her application. This report is intended for a
general audience of users and presents a wide
variety of program types (see Appendix A for the
benchmark program spec1fications).

The Z80 and the 6502 are available in various
versions, specified by a letter appended to the
root name, for example, Z80A or 65028. The version, in the case of both of these microprocessors
is closely related to its memory access timing
(see Table 3). Notice that the memory access
timing for a Z80A is very close to the memory
timing for a 6502A. Notice also that the clock
frequency of the Z80A is twice that of the 6502A.

Three di fferent aspects of performance are
measured by the benchmark programs here:
1.
2.
3.

Memory utilization is often the most important
criterion in measuring the performance of a
processor. It measures the amount of memory
(usually program memory) used by the processor in
performing various tasks.
It is important,
because the cost of memory is often one of the
dominating costs of a microprocessor application.
Table 4 lists the number of bytes of program
memory used by the l80 and the 6502 in each of the
benchmark programs.

Table 3. Memory Access Ti_s
for Various Clock Rates
Memory Access Time
Z80
6502
l80A
6502A
l80B
6502B

575
650
325
310
190
170

ns
ns
ns
ns
ns
ns

Clock frequeFICy
2.5
1.0
4.0
2.0
6.0
3.0

MHz
MHz
MHz
MHz
MHz
MHz

The ease of programming is a somewhat subjective
issue, but very important nonetheless. Software
development costs are enormous and can outweigh
many other considerations made by microprocessor
users. One measure of the ease of programming is
the number of inst ructions (lines of code)
required to perform a given task. This measure is
used in this report because of its simplicity and
objectivity. The number of lines of source code
in the benchmark programs for each of the microprocessors is shown in Table 5.

The memory access timing of a microprocessor is
import ant when evaluating the overall speed and
the cost of a particular application. faster
memory components are much more expensive and
difficult to obtain than slower ones. The Z80 has
a built-in provision for interfacing with components that cannot respond in the normal access
time. The ZBO has an input pin called WAii' that
can be activated whenever a slow device is
addressed. Activating the WAiT input causes the
751-1955-0002

Memory Utilization
Ease of Programming
Execution Speed

2-6

6/12/81

Table 4.

NUlllber of Bytee of Progr.. Metnory Used

Program Description
Computed GO TO Implementation
8 x 8 Bit Multiply Routine
16 x 16 Bit Multiply
Block Move
Linear Search
Insert into Linked Liat
Bubble Sort
Interrupt Handling
Character String Tranalation
Dynamic Memory Acceas

zao

6502

Ratio
6502/Z80

9
26
20
11
8
12
23
6
17
11

27
41
44
51
41
19
31
11
48
24

3.00
1.58
2.20
4.64
5.13
1.58
1.35
1.83
2.82
2.18

Average ratio 6502/Z80

Table 5.

2.63

Hmlber of Linea of Source Code

Progr.. Description
Computed GOTO Implementation
8 x 8 Bit Multiply Routine
16 x 16 Bit Multiply
Block Move
Linear Search
Insert into Linked List
Bubble Sort
Interrupt Handling
Chsrscter String Translation
Dynamic Memory Access

zao

6502

8
14
11
4
3
6
15
6

17
20
23
27
22
10
15
7
26
13

Average ratio 6502/Z80

Table 6.

ProgrUl Execution Tinles far the Lowest Speed Versions*
usec
Z80

Computed GOIO Implementation
8 x 8 Bit Multiply Routine
16 x 16 Bit Multiply
Block Move
Linear Search
Insert into Linked List
Bubble Sort
Interrupt Handling
Dynamic Memory Access

20.27
160.80
405.20
16138.00
8406.00
24.80
250718.00
17.2
27.60

Average ratio 6502/Z80

751-1955-0002

2.13
1.43
2.09
6.75
7.33
1.67
0.00
1.17
2.60
4.33
3.05

Progr.. Description

*
*

Ratio
6502/zaO

6502

Ratio
6502/Z80

46.33
196.00
713.00
31816.00
13011.00
34.00
280474.00
32.00
47.00

2.29
1.22
1.76
1.97
1.55
1.37
1.12
1.86
1.70

I18BC

1.65

Z80 maximum clock frequency is 2.5 MHz. Memory access time is 575 ns.
6502 maximum clock frequency is 1.0 MHz. Memory access time is 650 ns.
2-7

6/12/81

Execution speed can be important in several ways.
A computer product that has a human interface,
such as a keybord and display, will be more
productive and enjoyable to use if it responds
quickly. A microprocessor being evaluated for use
in controlling a high-speed device might have to
be rejected i f i t cannot meet very rigid timing
requirements.

of code used varies dramatically from one program

to another, but none of the programs have fewer
lines of 6502 code than Z80 code. Comparing versions of equivalent speed (Table 7l, the Z80 executes eight of the ten programs in less time than
the 6502.
In all three measures of performance (Tables 4, 5,
and 7), the program that yields the best results
for the 6502 is the bubble sort. The bubble sort
program, as specified in Appendix A, operates on
an array of less than 256 bytes, so one of the
8-bit index registers in the 6502 can be used very
effectively.
In applications that primarily use
short byte-oriented data structures, the 6502 is
worthy of consideration.

Execution time varies significantly depending on
which version of Z80 or 6502 is used, so a comparison of different versions is important. Table
6 lists the execution times of the benchmark programs for the lowest speed versions of the two
microprocessors.

Some of the benchmark programs reveal outstanding
results in favor of the Z80. For example, the
linear search program and the dynamic memory block
access program have only three Z80 instructions,
and the block move program uses only eight bytes
of program memory. The reason for such outstanding results with the Z80 is that it has many
exceedingly powerful instructions. The Block Move
and Block Search instructions illustrated in the
benchmark programs are only a subset of the many
block-oriented instructions of the Z80. The
ability to access and manipulate bytes in dynamic
memory blocks spans nearly the entire Z80 instruction set and is greatly appreCiated by programmers
who deal with multi-tasking software.

The most relevant comparison of execution times is
shown in Table 7, where the data is calculated
from versions of the Z80 and 6502 that can operate
in systems of similar speeds. One should not be
confused by the higher clock rate of the Z808,
because even at twice the clock rate of the 6502B,
the Z80B has a longer external component access
time than the 6502B (see Table 3).

CONCLUSION
The results of the benchmark programs presented in
this report show the Z80 performing signi ficantl y
better than the 6502 in nearly every aspect. In
six of the ten programs, the 6502 used more than
twice the amount of program memory than the Z80.
In the bubble aort program, the 6502' s best relative performance, it used 35 percent more
program memory than the Z80.
The number of lines
Table 7.

In applications that require data structures
longer than 256 bytes or that manipulate 16-bit
data, the Z80 is likely to be more efficient than
the 6502, particularly in terms of memory utilization and programmer productivity.

Execution Times for Versions with Equivalent Memory Aceeas Time*
Program Description

Computed GOTO Implementation
8 x 8 Bit Multiply Routine
16 x 16 Bit Multiply
Block Move
Linear Search
Insert into Linked List
8ubble Sort
Interrupt Handling
Character String Tranalation
Dynamic Memory Access

usec
ZeOB
8.45
67.00
168.83
6724.17
3502.50
10.33
104465.83
7.17
5678.33
11.50

Average ratio 6502B/Z808

usec
6S02B
15.44
65.33
237.67
10605.33
4337.00
11.33
93491.33
10.67
7356.00
15.67

Ratio
65028/Z80B
1.83
0.98
1.41
1.58
1.24
1.10
0.89
1.49
1.30
1.36
1.32

* Z808 maximum frequency is 6 MHz. Memory access time is 190 ns.
* 6502B maximum clock frequency is 3 MHz. Memory access time is 170 ns.
751-1955-0002

2-8

6/12/B1

APPENDIX A.

BENCHMARK PROGRAM SPECIfICATION

Insert into Linked liat,

The linked list exists

in RAM (not page zero) and has 160 bit forward

Computed GO TO implementation. A byte is tested
for three states: negative, zero, and positive.
The processor branches to a di fferent variable
address for each state.

pointers. The root (pointer to top entry) may be
in page zero.
The address of the entry to be inserted 1S specified wherever is most efficient. Insert the entry
into the top position.

The byte is in a register, and the three 16-bit
addresses are on the stack.

Bubble sort. Using a standard bubble sorting
algorithm, arrange an array of bytes (length 256)
into descending order.

8 l( 8 Bit Unsigned Multiply Routine. Two a-bit
unsigned integers (INT1, INT2) located randomly in
memory (RAM or ROM) are multiplied together to
form a 16-bit product (INT3) to be stored in RAM.

To calculate the timing, use a length of 100 and
assume that the array is in ascending order before
sorting.

16 l( 16 Bit Unsigned Multiply.
Two 16-bit
unsigned integers, located wherever is most
efficient, are multiplied together to form a
32-bit product.

Interrupt Handling. Respond to an interrupt, save
processor status, save registers, restore registers, restore processor status, and return.
Response time does not include the time for an
executing instruction to complete.

Block Move. Move a block of memory from one
location to another. The source and destination
addresses and the block size are known at assembly
time, but no restriction on their values are
allowed.

Character String Translation. A string of ASCII
characters of known length is translated into
EBCDIC according to an existing 256 byte translation table.

Use a block size of 1920 bytes (a typical CRT
screen) for time calculation.

Use a length of 1000 for time calculations.

linear Search. Search for the f1rst occurrence of
a certain byte in a string of bytes. The string
address and length are known at assembly time, but
no restrictions on their values are allowed.

Dynamic Memory Aeceas. The following operations
are performed on bytes within a 256 byte dynamic
memory block (dynamic means the block address is a
variable) •

Use string length equal to 1000 with no find for
time calculations.

Set bit 5 of byte 151, increment byte 70, and
shift byte 205 left.

751-1955-0002

2-9

6/12/81

APPENDIX BI

Z80 PROGRAM LISTINGS

Z80 Computed GOTO implementation

bytes

cycles
10
10
4
11/5
10
12/7
4
4

Lines = 8
Bytes = 9
Cycles = 50.67

COMPUTED GOTO (REG A CONTAINS THE BYTE TO BE TESTED)
COGOTO

POP
POP
OR
RET
POP
JR
EX
CoG01o JP
END

DE
HL
A
M
BC
Z,COG01o
DE, HL
(HL)

!DE = JUMP ADDRESS IF POSITIVE
!HL = JUMP ADDRESS IF ZERO
!TEST THE BYTE
!JUMP TO ADDRESS FOR NEGATIVE
!DISCARD ADDRESS FOR NEGATIVE
!JUMP IF BYTE ZERO
!HL = ADDRESS FOR POSITIVE
!JUMP TO APPROPRIATE ADDRESS

%. 180 B x 8 Bit Unsigned Multiply Routine

bytes

cycles

13
4

13
17

PREPARE ARGUMENTS FOR SUBROUTINE
LD
A, (INT1)
LD
E,A
LD
A,(INT2)
CALL MULT8

!RANDOM LOCATION
!REG E = MULTIPLICAND
!REG A = MULTIPLIER
!CALL SUBROUTINE

8 X 8 UNSIGNED MULTIPLY ROUTINE
2

2
2
1
2

7
4
4
7
11
12/7

11
13/8
10

MULT8

LD
LD
LD
LD
MUL TI10 ADD
JR
ADD
MULT20 DJNZ
RET

D,o
H,D
L,A
B,8
HL,HL
NC,MULT2o
HL,DE
MUL T10

!EXTEND MULTIPLICAND TO 16 BIT
!INITIALIZE MULTIPLIER/PRODUCT
!INITIALIZE LOOP COUNTER
!SHIFT MULTIPLIER/PRODUCT LEFT
!JUMP IF MSB OF MULTIPLIER WAS 0
!ADD MPCAND TO PRODUCT
!DEC LOOP CNTR & JMP IF NOT 0
!RETURN

STORE PRODUCT
3

LD
END

(INT3),HL

Lines = 14
Bytes = 26
Cycles = 402 average

751-1955-0002

2-10

6/12/81

J. 289 16 x 16 Bit Unsigned Multiply
16 x 16 BIT UNSIGNED MULTIPLY

bytes

cycles

2
3
1
2
2
2

7
10
11
8

BC
DE
I HL

= MULTIPLICAND
= MULTIPLIER /
= PRODUCT LSW

MUL T16
MULT30

12/7
11
12/7

2
1

Iii

4
10

LD
LD
ADD

MULT40

RL
JR
ADD
JR
INC
DEC
JP
END

PRODUCT MSW

A,16
HL,O
HL,HL
E

!A = LOOP COUNT
!INIT PRODUCT LSW
!SHIFT MULTIPLIER/PRODUCT LEFT

!MSB OF MULTIPLIER TO CARRY
!JUMP IF MSB WAS 0
IMULTIPLICAND + PRODUCT LSW
!HANDLE CARRY TO MSW

NC,MULTJO
HL,BC
NC,MULT40
DE
A

NZ,MULT30

IDEC LOOP COUN T
!LOOP TILL DONE

Lines = 11
Bytes = 20
Cycles = 1013 average
4.

280 Block Move

bytes
3
3
3
2

cycles
10
10
10
21/16

Move a block of memory.
BLKMOV

LD
LD
LD
LDIR
END

HL,SOURCE
DE ,DESTIN
BC,BLKSIZ

!SET UP POINTERS & COUNT

!MOVE BLOCK

Lines = 4
Bytes = 11
Cycles = 40345
5.

Z80 linear Search

bytes
3
3
2

cycles
10
10
21/16

SEARCH FOR THE BYTE IN REG A
SEARCH

LD
LD
CPIR
END

HL,STRING
BC,LENGTH

!HL = ADDRESS OF STING
!BC = LENGTH OF STRING
!SEARCH STRI NG

Lines = 3
Bytes = 8
Cycles = 21015

151-1955-0002

2-11

6/12/81

lBO Insert into

bytes

cycles

linked List

INSERT THE ENTRY POINTEO TO BY (HL)
INSERT

7
3
3

16
6
7

LD
LD
LD
LD
INC
LD
END

A, (ROOT)
(HL),A
A,(ROOT+1)
(ROOT) ,HL
HL
(HL) ,A

!XfER OLD TOP ENTRY PTR
!ROOT POINTS TO NEW ENTRY

Lines = 6
Bytes = 12
Cycles = 62
7.

Z80 Bubble Sort

bytes

cycles

3
3

10
10
7
6
7

BUBBLE SORT ARRAY INTO DESCENDING ORDER
SORT
SDRT20

2
2

12/7
7
7
6
7
6

13/8
4

12/7

SORT30

LD
LD
LD
INC
LD
CP
JR
LD
LD
DEC
LD
INC
DJNZ
DEC

HL,ARRAY
BC,PAIRCT*256
A, (HL)
HL
E,(HL)
E
NC,SORT30
C,l
(HL) ,A
HL
(HL),E
HL
SORT20
C

!INIT ARRAY POINTER
!INIT PAIR CNTR & ENCHANGE fLAG
!GET fIRST BYTE Of PAIR
IADDRESS NEXT BYTE
!GET SECOND BYTE Of PAIR
!COMPARE fIRST & SECOND BYTE
!JUMP If fIRST> = SECOND
!SET EXCHANGE fLAG
IEXCHANGE THE PAIR

ILOOP TILL ALL PAIRS EXAMINED
!CHECK EXCHANGE fLAG
IJUMP If EXCHANGE OCCURED

END
Lines = 15
Bytes = 23
Cycles = 626795

751-1955-0002

2-12

6/12/81

18o Interrupt Handling

bytes

cycles
4
4
4
4
4
10

INTERRUPT OVERHEAD (ADD 13 CYCLES RESPONSE TIME)
INTRPT

EX
EXX
EXX
EX
EI
RET
END

AF,AF'

!SAVE REGISTERS AND STATUS
!RESTORE REGISTERS AND STATUS

AF,AF'
!RETURN TO INTERRUPTED PROGRAM

Lines = 6
Bytes = 6
Cycles = 43
9.

ISO Character String Tranalation

TRANSLATE STRING FROM ASCII TO EBCDIC
bytes
3
2
2
2

1
2
2

cycles
10
7
7
7
7
7
7
13/8
4
12/7

TRANSLATION TABLE MUST BE AT A PAGE BOUNDARY.
TRANSL

TRAN10

Lines = 10
Bytes = 17
Cycles = 34070
10.

bytes

LD
LD
LD
LD
LD
LD
LD
DJNZ
DEC
JR
END

HL,STRING
D,HI TABLE
B,LO LENGTH
C,HI LENGTH+1
E, (HL)
A, (DE)
(HL) ,A
TRAN10
C
NZ1TRAN10

!HL = STRING ADDRESS
!D = HIGH BYTE OF XLATIDN TALBE
!B = LOOP COUNTER LOW BYTE
!C = LOOP COUNTER HIGH BYTE
!GET AN ASCII CHARACTER
fUSE IT TO INDEX EBCDIC TABLE
!STORE EBCDIC CHAR IN STRING
!DEC AND TEST LOOP COUNT
!JUMP IF NOT DONE

18o Dynamic Memory Acceas

cyc les

REG IX

= MEMORY

BLOCK ADDRESS

!
4

3
4

23
23
23

DYNACC
DONE

SET
INC
SLA
END

5, (IX+151)
(IX+70)
(IX+205)

!SET BIT 5 OF BYTE 151
!INCREMENT BYTE 70
!SHIFT BYTE 205 LEFT

Lines = 3
Bytes = 11
Cycles = 69

751-1955-0002

2-13

6/12/81

APPENDIX C. 6502 PROGRAM LISTINGS
6502 CDllputed GOlO illlpl_ntation

bytes

cycles

2
1
2

! COMPUTED GOTO (REG X CONTAINS THE BYTE TO BE TESTED)
COGOTO

3
4

2
1
2
2
1

3
4

3
2
3/2
6
4
4

2
3
3

2
3/2
5
5

COG010

COG020

PLA
STA
PLA
STA
PLA
STA
PLA
STA
TXA
BPL
RTS
PLA
PLA
TXA
BNE
JMP
JMP
END

!POSADR=ADDRESS FOR POSITIVE
POSADR
POSADR+1
ZERADR

!ZERADR=ADDRESS FOR ZERO

ZERADR+1
COG010

COG020
(ZERADR)
(POSADR)

!TEXT THE BYTE
!BRANCH IF NOT NEGATIVE
!JUMP TO ADDRESS FOR NEGATIVE
!DISCARD ADDRESS FOR NEGATIVE
!TEST THE BYTE
!BRANCH IF NOT ZERO
!JUMP TO ADDRESS FOR ZERO
IJUMP TO ADDRESS FOR POSITIVE

Lines = 17
Bytes = 27
Cycles = 46.33 average

751-1955-0002

2-14

6/12/B1

6502 8 x 8 Bit Unsigned Multiply Routine

bytes

cycles

3
6

PREPARE ARGUMENTS FOR SUBROUTINE
LDA
STA
LDA
STA
JSR

INT1
MPCAND
INT2
MPLIER
MULTB

!RANDOM LOCATION
!PAGE ZERO
!RANDOM LOCATION
IPAGE ZERO
!CALL SUBROUTINE

B X B UNSIGNED MULTIPLY ROUTINE
2
2
1
2
2

2
2
2
5
2/3

1
2
2
2

2
1

2/3
5
2
2/3
6

MULTB

LDA
110
LDX
HB
MULT10 ASL
A
ROL
MPLIER
BCC
MULT20
ADD MULTIPLICAND TO PRODUCT
CLC
ADC
MPCAND
BCC
MULT20
INC
MPLIER
MULT20 DEX
BNE
MULT10
RTS

!CLEAR LOW BYTE OF PRODUCT
IINIT LOOP COUNTER
!SHIFT MULTIPLIER/PRODUCT LEFT
!BRANCH IF MSB WAS 0

!HANDLE CARRY TO HIGH BYTE
!DECREMENT LOOP COUNTER
!BRANCH IF NOT DONE
IRETURN

STORE PRODUCT
3

Lines = 20
Bytes = 41
Cycles = 196 average

751-1955-0002

STA
LDA
STA
END

INT3
MPLIER
INT3+1

2-15

!LOW BYTE
!HIGH BYT

6/12/B1

" 6502 16 x 16 Bit Unsigned Multiply
16 x 16 UNSIGNED MULTIPLY
MPCAND
MPLIER
PRODUC

bytes

cycles

2
2
2
2
2
2
2
2
2

2
2
3
3

MULT16

5
5

MULDO

2
2
2
2
2
2
2
2
2
2
2
2

5
5
3/2
2
3
3
'3

3
3
3
3
2
3
3/2
5

2
3/2

MULT40

2 CONSECUTIVE BYTES IN PAGE 0
2 CONSECUTIVE BYTES IN PAGE 0 (PRODUC+2)
4 CONSECUTIVE BYTES IN PAGE 0 (OVERLAPPING MPLIER)
LDX
LDA
STA
STA
ASL
ROL
ROL
ROL
BCC
CLC
LDA
ADC
STA
LDA
ADC
STA
LDA
ADC
STA
BCC
INC
DEX
BNE
END

#16
#0
PRODUC
PRODUC+1
PRODUC
PRODUC+1
MPLIER
MPLIER+1
MULT40
PRODUC
MPCAND
PRODUC
PRODUC+1
MPCAND+1
PRODUC+1
PRODUC+2
#0
PRODUC+2
MULT40
PRODUC+3
MULDO

!INIT LOOP COUNTER
!INIT PRODUCT LSW

!SHIFT MULTIPLIER/PRODUCT LEFT

!JUMP IF MSB WAS 0
!MULTIPLICAND+PRODUCT LSW

!PROPOGATE CARRY

!DEC LOOP COUNT
! LOOP TILL DONE

Lines = 23
Bytes = 44
Cycles = 713 average

751-1955-0002

2-16

6/12/81

••

6502 Black Mave

bytes

cycles

2
2
2
2
2
2
2
2
2
2
2
2
2
1
2
2
2
1
2
2
2
2
2
2
2
1
2

2
3
2
3
2
3
2
3
2
3/2
2
5/6
6
2
3/2
5
5
2
3/2
2
3/2
5
5
5/6
6
2
3/2

Move s block of memory.
BlKMOV

lOOP1

lSTPAG

lOOP2

DONE

lOA
STA
lOA
STA
lOA
STA
lOA
STA
lOX
BEQ
LOY
lOA
STA
DEY
BNE
INC
INC
DEX
BNE
lOY
BEQ
DEC
DEC
lOA
STA
DEY
BNE
END

flO SOURCE
SRCADR
fHI SOURCE
SRCADR+1
flO DESTIN
DSTADR
fHI DESTIN
DSTADR+1
#HI COUNT
lSTPAG
10

(SCRCADR),Y
(DSTADR), Y
lOOP1
SRCADR+1
DSTADR+1

ISET UP POINTERS AND COUNT

IBRANCH If SIZE < 256 BYTES
IY REG USED AS INDEX & CNTR
IMOVE A 256 BYTE PORTION

IPOINT TO NEXT 256 BYTE PART
IX REG=NUM Of 256 BYTE PARTS

lOOP1
flO COUNT
DONE
SRCADR
DSTADR
(SRCADR) ,Y
(DSTADR), Y

IY REG=NUM Of BYTES REMAINING
IBRANCH If NONE lEfT
IADJUST ADDRESSES
IMOVE REMAINING BYTES

lOOP2

Lines = 27
Bytes = 51
Cycles = 31B16

751-1955-0002

2-17

6/12/B1

6502 Linear Search

bytes

cycles

2
2
2
2
2
2
2
2
2
1
2
2

2
3
2
3
2
3/2
2
5/6
3/2
2
3/2
5
2
3/2
2
3/2
2
5/6
3/2
2
2
3/2

2
2
2
2
2
2
1
2
2

SEARCH FOR BYTE IN REG A
SEARCH

SRCH10

SRCH20

SRCH30

DONE
Lines = 22
Bytes = 41
Cycles = 13011

LDA
STA
LDA
STA
LDX
BEQ
LDY
CMP
BEQ
INY
BNE
INC
DEX
BNE
LOY
BEQ
LDY
CMP
BEQ
INY
CPY
BNE
END

IILO STRING
STRADR
#HI STRING
STRADR+1
#HI COUNT
SRCH20
#0
(STRADR), Y
FOUND
SRCH10
STRADR
SRCH10
#LO COUNT
DONE
110

!SET UP STRING POINTER

!X = HIGH BYTE OF COUNT
!CHECK FOR 0
!Y = COUNTER AND INDEX
!MATCH?
!BRANCH IF SO
!INCREMENT COUNT/INDEX
!BRANCH IF NOT DONE WITH 256
!UPDATE POINTER TO NEXT 256
!DECREMENT HIGH BYTE OF COUNT
!BRANCH IF NOT LAST PAGE
!CHECK LAST PARTIAL PAGE
!BRANCH IF NO PARTIAL PAGE
!Y = INDEX

(STRADR), Y
FOUND
IILO COUNT
SRCH30

!DONE WITH LAST PARTIAL PAGE
!BRANCH IF NOT

6502 Insert into Linked List

bytes

cycles

2
2
2
2
1
2
2
2
2
2

2
3
6
3
2
6
3
3
3
3

INSERT THE ENTRY POINTED TO BY (NEWADR)
INSERT

LOY
LDA
STA
LDA
INY
STA
LDA
STA
LDA
STA
END

110

ROOT
(NEWADR),Y
ROOT+1
(NEWADR),Y
NEWADR
ROOT
NEWADR+1
ROOT+1

!INIT INDEX REG
!XFER OLD TOP ENTRY PTR
!FIRST 2 BYTES IS FORWARD PTR

!ROOT POINTS TO NEW ENTRY

Lines = 10
Bytes = 19
Cycles = 34

751-1955-0002

2-18

6/12/81

Bubble SDrt

bytes

cycles

2
2
3
3
2
2

2
2
4/5
4/5
3/2
2
3
4/5
5
4
5
2
3/2
2
3/2

3
3
3
2
1
2

BUBBLE SORT ARRAY INTO DESCENDING ORDER
SORT
SORT10

SORT20

LDY
LDX
LDA
CMP
BCS
LDY
PHA
LDA
STA
PLA
STA
DEX
BNE
DEY
SEQ

110

IILENGTH-1
ARRAY,X
ARRAY+1,X
SORT20
#1

!INIT EXCHANGE FLAG
!INIT INDEX/PAIR COUNT
!GET FIRST BYTE OF PAIR
!BRANCH IF FIRST > = SECOND
!SET EXCHANGE FLAG
!EXCHANGE THE PAIR

ARRAY+1,X
ARRAY,X
ARRAY+1,X
SORT10
SORT

!DEX INDEX/PAIR COUNT
!LOOP TILL ALL PAIRS EXAMINED
! CHECK EXCHANGE FLAG
!BRANCH IF EXCHANGE OCCURRED

END
Lines = 15
Bytes = 31
Cycles = 280474

6502 Interrupt Handling

bytes

cycles

2
2

2
2
1

3
3
3
3
3
4
6

INTERRUPT OVERHEAD (AOD 7 CYCLES RESPONSE TIME)
INTRPT

PHA
STX
STY
LDY
LDX
PLA
RTI
END

!SAVE REGISTERS
XSAVE
YSAVE
YSAVE
XSAVE

!RESTORE REGISTERS

!RESTORE PROCESSOR STATUS

Lines = 7
Bytes = 11
Cycles = 32

751-1955-000?

2-19
-~~------.~~--~~

6/12/81

6502 Character String Tranalation

bytes

cycles

2
2
2
2
2
2
2
2
2

2
3
2
3
2
3/2
3

2
2
2
2
2
2

2
2
2
2

1
2
2
2

TRANSLATE STRING FROM ASCII TO EBCDIC
TRANSL

5
2
4
6
2
3/2
5
5
3/2
2
3/2
5
5
2

TRAN10

TRAN20

TRAN30

6
2
3/2
DONE

LDA
STA
LDA
STA
LDA
BEQ
STA
LDY
LDA
TAX
LDA
STA
INY
BNE
INC
DEC
BNE
LDY
SEQ
DEC
LDA
TAX
LDA
STA
DEY
BNE
END

IILO STRING
STRADR
IIHI STRING
STRADR+1
IIHI LENGTH
TRAN20
COUNT
flO

(STRADR),Y

!SET UP STRING POINTER

ICHECK HIGH BYTE OF LENGTH
!BRANCH IF STRING < 256 CHARS
IINIT COUNT
IY = INDEX FOR PARTIAL STRING
!TRANSLATE A BYTE

TABLE,X
(STRADR),Y
TRAN10
STRADR+1
COUNT
TRAN10
flLO COUNT
DONE
STRADR
(STRADR),Y

! INCREMENT INDEX
!BRANCH IF NOT DONE WITH PAGE
!UPDATE POINTER TO NEXT PAGE
!DECREMENT COUNT
!BRANCH IF NOT LAST PAGE
IY = INDEX/COUNT FOR LAST PAGE
!BRANCH IF NO PARTIAL PAGE
!ADJUST POINTER
!TRANSLATE LAST PARTIAL PAGE

TABLE ,X
(STRADR),Y
TRAN30

Lines = 26
Bytes = 48
Cycles = 22068

751-1955-0002

2-20

6/12/81

10.

6502 Dynamic

bytes

cycles

2
2
2
2
2
2
1
2
2
2
2
1
2

2
5
2
6
2
5
2
2
6
2
5
2
6

~ry

Access

(BLOCK)
DYNACC

DONE

= ADDRESS

LDY
LDA
ORA
STA
LDY
LDA
CLC
ADC
STA
LDY
LDA
ASL
STA
END

OF MEMORY BLOCK

#151
(BLOCK), Y
#20
(BLOCK), Y
#70
(BLOCK), Y
#1
(BLOCK), Y
#205
(BLOCK), Y
A
(BLOCK),Y

!SET BIT 5 OF BYTE 151

!INCREMENT BYTE 70

!SHIFT BYTE 205 LEFT

Lines = 13
Bytes = 24
Cycles = 47

00-2116-01

2-21

6/12/81

Integrating an 8-Blt
DMA Controller
into a 16-Bit System

Zilog

Tutorial

November 1980

The new generation of 16-blt microprocessors
al lows the system designer to Implement a
powerful, but cost-effective computer system
using the currently available 8-blt peripheral support devices. These processors
offer advance block transfer operations that
allow blocks of data to be moved between
memory and an Input/Output (I/O) device.
Although the data transfer rates achieved
are very high, they are stll I Inadequate for
Interfacing some system peripherals such as
the new 8" Winchester disk drives. To Incorporate such high-speed peripheral
devices, the system designer needs to Integrate a Direct Memory Access (DMA) controller
device Into the system. This article II lustrates the Increase In throughput obtained by
Integrating an 8-blt DMA device Into a 16bit microprocessor system and discusses the
various Interface techniques and trade-offs
Involved In such a task.
ZSO DIRECT MEMORY ACCESS COmOUER
A DMA device performs the dedicated task of
moving data In a microprocessor system Independently of the Central Processing Unit
(CPU). The transfers are usually between
memory and an I/O device, but some DMAs are
capable of moving data from memory to memory
or between two I/O devices. In a small
microprocessor system, the CPU can normally
do these transfers via software, but this
results In a reduction of system throughput
and ties up the CPU for long periods of time
when a large amount of data Is to be moved.
The response time of the CPU In these CPUmanaged transfers Is Inherently slow and may
not be adequate In situations where the
nature of data transfers demands fast
response. The addition of a DMA device to an
8-blt microprocessor system Is easily accomplished, since most 8-blt CPU families have a
DMA controller device that shares common
family Interface protocol. Integrating a DMA
device Into a 16-blt system poses two options
to the system designer. Since 16-blt LSI DMA
devices are not presently available, the
designer can use the 8-blt devices with addl617-1564-0003

tlonal hardware, or can opt for Implementing
DMA functions using discrete TTL logic. The
latter approach offers the advantage of
Implementing only those functions that are
needed. However, even In the most simple
cases, a high part count Is required to add
DMA capability using this approach. The
8-blt devices, on the other hand, offer
extensive, Integrated capabilities and
require relatively little additional logic
to Interface to 16-blt processors.
The Z80 DMA Is a powerful 8-blt DMA device
and, unlike most other DMAs, It takes complete control of the system bus during the
data transfer. It generates all bus signals
normally generated by the Z80 CPU during a
data transfer without any external TTL
packages. Data transfers can be accomplished In three different modes. In the
Byte mode, one byte of data Is transferred at
a time, giving control of the system bus to
the CPU after each byte transfer. In the
Burst mode, a block of data bytes Is transferred and data transfer operations continue
until the READY signal (normally from an I/O
device) becomes Inactive. At this time, bus
control Is returned to the CPU and when the
I/O device Is ready to move more data (activating the READY signal), the data transfer
operation Is started again. These bursts of
data transfers continue until the whole block
has been moved. The Continuous mode operates
In the same fashion as the Burst mode, except
that the bus control Is returned to the CPU
only when the operation Is complete. If the
READY Signal goes Inactive before the whole
block Is moved, the DMA simply pauses until
It becomes active again. In addition to data
transfers, the Z80 DMA can also search for a
specific data byte. In the Search mode, data
bytes are compared to a programmable "match
byte" and an Interrupt may be generated when
a match Is found.
The zeo DMA can generate two port addresses,
with either address being variable or fixed.
It Is capable of doing a data transfer from
memory to memory or between two I/O devices,
using a single channel In any of the three

2-23
~~~---~.--.--~----.~--~

10/28/80

modes described above. The Z80 DMA has a
programmable cycle length. Thus. the read
and write cycles of a data transfer operation
can be made two. three or four clock cycles
long. and the four control signals associated
with data transfers can be deactivated onehalf clock cycle before the read or write
cycle ends. These programmable features al low
easy Interface of the DMA to slow or fast
system components. In addition. the DMA can
be made to automatically repeat a complete
operat Ion us I ng the "auto restart" feature.
Multiple DMAs can be daisy-chained In a
system without any TTL support logic. A
complete description of all the available
features of the DMA can be found In the Z80
DMA Technical Manual (document #00-2013-~

COMPARISON OF DATA lRANSFER
RATES IN A SMAU SYSTEM
Table 1 Illustrates the various transfer
speeds that can be obtained In a microprocessor system with a Z80A CPU. a Z8000
CPU. or a Z80A DMA. The Z80A DMA can achieve
an Impressive transfer rate of 1 Mbyte/sec.
The Z80A CPU. using the powerful block transTable 1.

programmed to search for a specific byte of
data while It Is transferring data. This
allows the system to perform powerful string
operations at very high data rates. The
transfer rates Shown In Table 1 Illustrate
the Improvement In system throughput that can
be achieved with a DMA device.
INTEGRATION OF A zao DMA IN A zaooo SYSTEM
A smal I. yet effective. Z8000 system can be
built using currently available zao peripherals. The implementation of such a system
Is fully described In the Zllog application
note A Small Z8000 System (document
#03-8060-01). Previous discussion has proven
the advantage of the addition of a DMA device
to such a system. The rest of this article
wll I describe the additional logic required
to Integrate the zao DMA Into a Z8000-based
system. By carefully selecting and Implementing only those functions required. the
designer can minimize the additional TTL
logic. Since zao peripherals share common
Interface logic. It Is not necessary to
duplicate the logic when other Z80 peripherals are added to the system.

Maximum Data Transfer Rates

Z80A DMAI

Z80A CPU
Memory
to
Memory

0.19 Mbytes/sec

1.0 Mbytes/sec
1.0 Mwords/sec**

I/O
to
I/O
I/O
to
Memory

Z8000 CPU
0.44 Mbytes/sec
0.44 Mwords/sec

1.0 Mbytes/sec
1.0 Mwords/sec**
1.0
1.0
2.0
2.0

0.19 Mbytes/sec

Mbytes/sec
Mwords/sec**
Mbytes/sec*
Mwords/sec*

0.4 Mbytes/sec
0.4 Mwords/sec

1 Continuous mode operation
* In Search/Transfer mode with external logic
**Requlres external logic for word transfers
fer Instruction. can transfer data at 0.19
Mbytes/sec. Since the DMA achieves the 1
Mbyte/sec. transfer rate using two-clockcycle operations for each byte of transferred
data. It requires memory devices with relatively short access times. The Z8000 CPU has
a maximum memory-ta-memory data transfer rate
of 0.44 Mtransfers/sec •• and a maximum I/Oto-memory data transfer rate of 0.40 Mtransfers/sec. The same transfer rates are obtained by the Z8000 CPU whether the data
transferred Is a byte or a word. However.
since the DMA can be made to transfer words
with some additional hardware. it can stll I
provide a data transfer rate of 1 Mtransfer/sec. In addition. the DMA can also be
617-1564-0003

Figure 1 shows a block diagram of the Interface requirements for a Z80 DMA device In a
Z8000 system. The Small Z8000 System Application Note already Implements part of the
logic shown In Figure 1. These Interface
functions are common to other Z80 peripherals. such as the PIO. SIO and CTC. This
Includes the 3-state address buffers and
bidirectional data buffers. which are used to
demultiplex the system address and data
buses. The DMA Is connected to the demultlplexed address and data lines rather than
being placed closer to the CPU. Other common
functional blocks are the Status Decoder. I/O
Decoder. and Z8000-to-Z80 Control Translator
logic.

2-24

10/28/80

Figure 1. Block Diagram

Since the zao DMA takes complete control of
address and data buses during an'operatlon,
It generates zao CPU system-bus-compatlble
control signals. However, these signals are
not compatible with the system bus control
signals generated by zaooo CPU, and a ZaD-tazaooo Control Translator logic block 15
required to Interface the OMA with the zaooo
system. In particular, the signals that need
to be generated In order to effectively
control the system bus are four status
signals STo-ST3, Byte/Word (B/W), Normal/
System (N/S), Read/Wrlte (R/W), Memory
Request (MREQ), Data Strobe (OS), and Address
Strobe (AS). The segmented ZaOOl CPU generates a segment address and a 16-blt offset
address within the segment. Since the DMA
can only output 16 bits of address Information, a Segment Register 15 required to store
the segment Information. The segment number
15 latched In this register by the zaooo CPU
prior to OMA operation. In memory-ta-memory
data transfers, the data to be moved must
reside In the same 64K address space. How
ever, In memory-ta-I/O operations, when the
block of data to be moved crosses a segment
boundary, the operation requires the loading
of a new segment number Into the Segment
Register before crossing the segment
boundary. The Segment Register 15 shown In
Figure 1.
A 4-blt Control Register that has been
appropriately programmed by the zaooo CPU
before It enables the DMA 15 used to generate
NlS, B/W, and W/DW signals. These three
617-1564-0003

Signals remain active throughout the DMA
operation. The OMA provides two signals
(MREQ and IORQ) that Indicate whether a
memory or an I/O address 15 being accessed.
These signals are gated with signals
generated by the zaooo Status Decoder, which
decodes the status signals STo-ST3 to differentiate between memory and I/O accesses In
the current CPU operation. Since the memory
and I/O address spaces of the DMA are the
same size, the MREQ and IORQ signals can be
Interchanged to generate other zaooo control
signals. The Write -(WR) signal of the OMA Is
used to generate the R/W signal.
The timing relationship between the OMA
control Signals (IORQ, MREQ, RO, WR) and
three of the zaooo control signals (AS, OS,
MREQ) 15 shown In Figure 2. In order to
generate AS and OS from the OMA-generated
control Signals, the OMA must be operated In
the variable cycle mode with a cycle length
of four clock cycles. The OMA, however, can
be allowed to run with an operational cycle
of two clock cycles, If the memory controller
can Initiate and complete a memory transaction with the OMA's control signals Instead
of using AS and OS, and If the memory devices
have the fast access times necessary for
twa-cycle transfers. Figure 3 Illustrates
the generation of AS, OS, and MREQ Signals
from DMA control signals RO, WR, and MREQ.
The four clock cycle memory read or write
operation of the OMA Is translated to a
three clock cycle CPU memory read or write
operation with this logic. The OS Signal 15

2-25

10l2a/ao

generated from RO and WR signals as shown in
the same figure.

eLK

iORci
DMA

AD r WR

MREQ,

DMA

DS
READ

iii

WRITE

MREQ

------,/'/,/,T-----X

WAIT

- - - ___

~~~~~~L~

_____ _

Figure 2. Control Signal Timings

MREQ
OMA

10011

10111

74LS175
eLK

When a dynamic RAM array needs to be refreshed, It becomes necessary to extend a
DMA read or write cycle. This Is achieved by
activating the WAIT signal of the OMA. This
signal is multiplexed with the Chip Enable
(CEl signal In the device, since the OMA
needs to be waited only when It is the bus
master. The WAIT signal, however, Is sampled
only at fixed Instances during a read or a
write cycle and then only If the cycle Is
more than two clock cycles long when the
programmable operational cycle feature Is
selected. Thus, In a three or four clock
cycle Memory Read or Write, the WAIT line Is
sampled at the failing edge of the second
clock, and on the fal ling edge of the third
clock In a four clock cycle I/O Read or Write
as Illustrated In Figure 2. This Implies
that In order to be able to use the WAIT
signal to extend the OMA operational cycle,
the designer has to opt for four clock cycle
transfers and use IORQ signal from the OMA to
generate AS and OS signals, rather than the
MREQ signal as shown In Figure 3. Since the
memory and I/O spaces of the zeo OMA are 64K
bytes each, the IORQ signal can be used to
indicate a memory access and the MREQ signal
to indicate I/O access.

AS
CPU

74LS175

elK

ClK

11001
11011

MREQ

CPU

OMA-r-+-I O

t----+--I 0

74LS175
ClK

AD-.......
-i-i 0
OMA

DS
CPU

74LS175
ClK

QI----\

Qt------I O

74LS175
ClK

"Figure 3. AS-.DS-.MREQ- Generation

617-1564-0003

2-26

10/28/80

CONTROL SIGNALS

"'~

ENBLG OIR

SYSTEM
DATA
BUS

Bl- B8

Al-Aa

Ao BAI

V1 100- 107-V
A 00- 07

Ao-A15 SAO-SA15

'Lo::;" ';:=...
100
107

74LS245
BUS
TRANSCEIVER

SYSTEM
ADDRESS
BUS

Z80A
DMA

A
00-07

...
Figure 4. 8-BIt Data Transfer Logic

BYTE, WORD AND DOUBLE WORD

BATA~TRANSFERS

The address translation logic, In conjunction
with the data buffers, al lows the~DMA to
perform byte, word or double word transfers.
The designer has the option of ~selectlng one
or more of these data transfer modes. However, the hardware required to l'mplement the
functions Increases as more options are
selected. When only byte transfers are
desired, no address translation logic or data
buffering Is needed, ~but, because the system
data bus Is 16-blts wide, an 8-blt bus transceiver buffer Is required to enable the DMA
to access the higher byte of the data bus
(Figure 4). In this case, the DMA's address
bus Is directly connected to the system
address bus. When 16-blt transfers are
desired, the DMA address bus is shifted so
that low address bit AO Is physically connected to system address bit SAl. In this
case, A15 of the DMA Is not used and SAO Is
ignored by the memory controller. An 8-blt

ClK

SYSTEM
DATA
BUS

Ii
08- 0 15

'I""

":>

data buffer serves the purpose of storing the
higher order data byte during the read cycle
and driving It In the write cycle. This Is
Illustrated In Figure 5. The 32-blt data
transfer operation Is similar to the 16-blt
operation but requires two additional data
buffers and the shifting of the ~address bus
by an additional bit. These approaches,
however, require that the same data bus width
be used In data transfers between memory and
an I/O device.
Figure 6 shows the address translation logic
needed to do 8-, 16- and 32-blt data transfers. The CPU needs to set up two signals,
B/W and W/DW, before enabling the DMA to
determine the data transfer width. These two
signals then control the shifting of the
DMA's address bus for the generation of
system addresses. Thus, while moving bytes,
the two transparent latches are enabled and
the DMA address bus remains unshlfted. The
data byte can be stored In any of the data

CONTROL SIGNALS

74LS364
DATA BUFFER
10-80

10-80

-y

I--

BAI

Z80A
DMA
00- 0 7

Ao-A14

SAI-15

SYSTEM
ADDRESS

BUS

Ii
00- 0 7

'I
Figure 5. 16-BIt Data Transfer logic

617-1564-0003

2-27

10/28/80

buffers (Figure 5) or by the DMA, depending
upon the memory organization. To accomplish
word or double word transfers, the address
bus is shifted via the multiplexers by one or
two bits, depending on the control signals.
Only the four multiplexers and a data buffer
are required to perform 8- and 16-bit data
movements. Since the upper address bits from
DMA are not used in 16- and 32-blt transfers,
up to 32K words and 16K double words can be
moved In a single DMA block transfer. To
compensate for the shifting of these
addresses, the actual port addresses are
shifted right by one or two bits before being
written to the DMA.

wIOW __
BNi....... CONTROL
lOGIC

IIS~-SAa

ler always transfers the data byte (In a byte
mode) on the low-order eight bits of the data
bus.
SUMMARY

Integration of a 8-bit DMA device Into a
16-bit microprocessor system Improves system
performance and al lows the system to add new
fast peripherals. The interfacing requires
additional logic, but some of this logic is
already Implemented in the system since the
system usually contains other 8-bit peripherals of the same CPU family sharing common

~ SAo-SA,

t 1'1

jSAa-SAl1

ISA'2-SA "

t 1'1

t l'

~ SYSTEM
SAo-SA15,) ADDRESS

...

BUS

SELoe
IISELoe
IISELOC
IISELOC
I
74LS257A
74LS257A
74LS257A
74LS257A

it·- I r--

~t- if:

BAI

A,.

2-Aa

i' AlO-A14

Z80A AoDMA A15
~

Ao-A,

74LS353 SAo-SA,

SAo-SA15

ill: G

-1
t

OC G
~

74LS353

Aa-A1S

I:":-

Figure 6. 8·, 16- or 32-811 Data Transfer Addre.. Translation Logic

us I HG

THE SEARCH MODE

The search or search/transfer modes of the
Z80 DMA need special interfacing consideration. Since the DMA can search for bytes
only, the use of these functions is limited
In a 16-blt environment without any support
logic. ThUS, when the DMA is set up to do
8-blt transfers, the hardware shown in Figure
4 allows searches on both halves of the data
bus when the data bus "Is 16 bits wide. In
the 16- and 32-bit transfer modes, however,
the DMA can compare only the low-order data
byte, and external hardware is required if
any of the higher order data bytes need to be
searched. When the hardware Is set up to do
8-, 16- and 32-bit data transfers, the search
mode can be used only if the memory control-

10/28/80

interface logiC. Also, the implementation
of the extra logic needed to Integrate the
8-bit DMA can be minimized by carefully
selecting and Implementing only necessary DMA
functions that contribute to the Improvement
of overal I system performance.
REFERENCES

2-28

Z80 DMA Techn Ica I Manua I; Z II og Inc., May
1980.

"A Small Z8000 System", Application Note,
Zilog Inc., January 1980.

Z8000 CPU Technical Manual, Zilog Inc.,
May 1980.

00-2054-01

Interfacing Z80 CPUs to the
Z8500 Peripheral Family
Application
Note

Zilog

May 1983
INTRmUCTIIJI

Data Bus Signals

The ZB500 Family consists of universal peripherals
that can interface to a variety of microprocessor
systems that uae a non-multlplexed address and
data bus. Though slmllar to ZBO perlpherals, the
ZB500 perIpherals dlffer 10 the way they respond
to I/O and Interrupt Acknowledge cycles.
In
addltlon, the advanced features of the ZB500
peripherals enhance system performance and reduce
proceasor overhead.

DrDo

Systaa Control Signals

An-AO

To deB1gn an effectIve lnterface, the user needs
an understandlng of how the ZBO Famlly lnterrupt
structure works, and how the ZB500 peripherals
interact wlth thls structure.
Thls appllcatlon
note provldes baslc lnformabon on the lnterrupt
structures, aa well as a diacuasion of the
hardware and software conslderatlons lnvolved 10
lnterfaclng the ZB500 perIpherals to the ZBO
CPUS.
Discussl0ns center sround each of the
followlng situations:
•
•
•
•

ZBOA
ZBOB
ZBOH
ZBOH

4 MHz
6 MHz
B MHz
B MHz

CPU
CPU
CPU
CPU

to
to
to
to

Data Bus (b1directIonal, 3-state).
This
bus transfers data between the CPU and the
penpherals.

Address Select Lines (optional).
These
hnes select the port and/or control
registers.
ChlP Enable (lnput, active Low).
tT is
used to select the proper per ipheral for
programmlng. tT should be gated with ~
or "RRrQ" to prevent SPUrlOUS chip selects
durlng other mach,ne cyclea.
Read (,nput, actlve Low). ~ activates the
chlp-read circuitry and gatea data from the
chip onto the data bus.

"WR'*

ZB500 4 MHz perlpherals
ZB500A 6 MHz peripherals
ZB500 4 MHz perlpherals
ZB500A 6 MHz perlpherals

Write (input, active Low). VIR" strobea data
from the data bus lnto the peripheral.

*Chip reset occurs when l![i and VIR" are actlve
slmultaneously.

ThlS appl icabon note assumes the reader has a
strong worklng knowledge of the ZB500 perlpherals;
lt is not lntended as a tutorial.

Interrupt COntrol
~

CPU HARDWARE INTERFACING

The hardware lnterface conslsts of three baslc
groups of slgnals: data bus, system control, and
lnterrupt control, descrlbed below.
For more
detailed signal information, refer to Zllog's
Data Book, Unlversal Perlpherals.

Interrupt Acknowledge (input, sctIve Low).
This
slgnal
lndlcates
an
Interrupt
Acknowledge cycle and 1S used wlth ~ to
gste the lnterrupt vector onto the data
bus.
Interrupt Request
acbve Low).

2-29

(output,

open-draIn,

lEI

Interrupt Enable In (input, active High).

Write Cycle Timing

lEO

Interrupt
Hlgh).

Figure 2 illustrates the Z8500 Write cycle
tlming.
All reglster addresses and TIlTiID< must
remaln stable throughout the cycle.
If
goes
active after Wl1" goes active, or i f
goes inactlve before Wl1" goes lnactive, then the effective
Write cycle lS shortened. Data must be available
to the perlpheral prior to the falling edge of Wl1".

Enable

Out

(output,

acbve

These lines control the interrupt dalsy
chain
for
the
perlpheral
lnterrupt
response.

Z8500 I/o OPERATlII'4

PERIPHERAL INTERRUPT OPERATION

The Z8500 peripherals generate internal control
signals from lID" and Wl1".
Slnce PCLK has no
requued phase relatlOnship to lID" or Wl1", the
circultry generabng these signals provides bme
for metastable conditions to disappear.

Understandlng
peripheral
interrupt
operation
requires a basic knowledge of the Interrupt
Pending (IP) and Interrupt Under Service (IUS)
bits in relation to the daisy chain. Both Z80 and
Z85DO peripherals are designed in such a way that
no additional interrupts can be requested during
an Interrupt Acknowledge cycle. This allows the
interrupt daisy chain to settle, and ensures
proper response of the interrupting device.

The Z8500 perlpherals are lnltialized for dl fferent operating modes by prOgrammlng the internal
registers. These lnternal reglsters are accessed
during I/O Read and Write cycles, which are
described below.

The IP bit is set in the peripheral when CPU
intervention is required (such condltions as
buffer empty, character available, error detection, or status changes).
The Interrupt Acknowledge cycle does not necessarily reset the IP
bit. This bit is cleared by a software command to
the peripheral, or when the action that generated
the interrupt is completed (i.e., reading a
character, writing data, resetting errors, or
changing the status). When the interrupt has been
serviced, other interrupts can occur.

Read Cycle Timing
Figure 1 illustrates the Z8500 Read cycle timing.
All register addresses and TIlTiID< must remaln
stable throughout the cycle.
If
goes active
after lID" goes active, or i f
goes inactive
before lID" goes inactive, then the effectlve Read
cycle is shortened.

ADDR ________-J)(~

_______________________

A_DD_R_E_S_S_V_A_L_ID____________________.J)(~

_________

\_--/

\~_____________________________/

DATA ____________________________________________~{~____D_A_TA__V_A_LI_D____')~------------IN

figure 1.

Z8500 Peripheral I/o Read Cycle Timing

2-30

2296-001

ADDR ________

-J)(~

__________________

A_D_D_R_E_S_S_V_A_LI_D______________________.J)(~

_________

\"---1

\ ____--'1
D~~~ -----------------------«~_____________D_A_TA_V_A_L_ID_____________')~---------Figure 2.

Z8500 Peripheral I/o Write Cycle Tuing

When the Z80 CPU executes the RET! instruction,
the peripherals monitor the data bus and the highest priority device under service resets its IUS
bit.

The IUS bit indicatea that an interrupt is
currently being serviced by the CPU. The iUS bit
is set during an Interrupt Acknowledge cycle lf
the IP bit is set and the lEI line is High.
If
the lEI line is Low, the IUS bit is not set, and
the device is inhibited from placlng its vector
onto the data bus.
In the Z80 peripherals, the
IUS bit is normally cleared by decoding the RETI
instruction, but can also be cleared by a software
command (510). In the Z8500 peripherals, the IUS
bit ia cleared only by software commands.

zoo

Z8500 Interrupt Daisy-Chain operation
In the Z8500 penpherals, the IUS bl t norm all y
controls the state of the lEO ll.ne.
The IP blt
affects the dalsy chaln only durmg an Interrupt
Acknowledge cycle. Slnce the IP blt lS normally
not part of the Z8500 penpheral lnterrupt daisy
chain, there lS no need to decode the RET! Instructlon.
To allow for control over the daisy
chain, Z8500 peripherals have a Olsable Lower
Chain (OLC) software command that pulls lEO Low.
This can be used to selectlvely deactlvate parts
of the dalay chaln regardless of the interrupt
status.
Table 1 shows the truth tables for the
Z8500 lnterrupt dalsy-chain control signals during
certaln cycles. Table 2 shows the lnterrupt state
dlagram for the Z8500 perlpherals.

Interrupt Daisy-Chain Qperation

In the Z80 peripherals, both the IP and IUS bits
control the lEO line and the lower portion of the
daisy chain.
When a peripheral's IP bit is set, its lEO llne is
forced Low. This is true regardless of the state
of the lEI line.
Additionally, i f the peripheraI's IUS bit is clear and its lEi line High, the
line is also forced Low.

The Z80 peripherals sample for both 'Rf and TO'llll'
active, and ~ inactive to identify an Interrupt
Acknowledge cycle. When 'Rf goes active and ~ is
inactive, the peripheral detects an Interrupt
Acknowledge cycle and allows its interrupt dalsy
chain to aettle. When the ~ line goes active
with 'Rf active, the higheat priority lnterrupting
peripheral places its interrupt vector onto the
data bus.
The IUS bit is also set to indicate
that the peripheral is currently under service.
As long as the IUS bit is set, the lEO line is
forced Low.
This inhibits any lower priority
devices from requesting an interrupt.
2296-002

Table 1. Z8500 Daisy-Chain Control Signals
Truth Table for
Daisy Chain Signsls
During Idle State
lEI
IP IUS lEO
0

X
X
X

Truth Table for
Daisy Chain Signals
Ouring iNiAiX Cycle
lEI
IP IUS lEO
0

0
0

2-31

~~~----~-~--

-._..

X
X

0
0

Table 2.

Z0500 Interrupt State Diagra.

interface.
FIgures 4 and 7 depIct some of the
logic used to lnterface the ZBOH CPU to the ZB500
and ZB500A peripherals for the I/O and Interrupt
Acknowledge interfaces.
The logic required for
adding additional Wait states into the timing flow
is not discussed in the folowing sections.

Interrupt COndItIon

~
I r E I HIgh?

ZOOA CPU to Z0500 Peripherals

<------>
INTACK

lEI

Walt for CPU INTACK Cycle

No additional Wait states are necessary during the
I/O cycles, although additional Wait states can be
inserted to compensate for timing delays that are
inherent. in a system.
Although the ZBOA timing
parameters indicate a negative value for data
valid prior to Wll', this is a worse than "worst
case" value.
This parameter is based upon the
longest (worst case) delay for data available from
the falling edge of the CPU clock minus the
shortest (best case) delay for CPU clock High to
Wll' Low. The negative value resulting from these
two parameters does not occur because the worst
case of one parameter and the best case of the
other do not occur within the same device. This
indicates that the value for data available prior
to Wll' will always be greater than zero.

CPU Read, WrIte, or Reset IP

lEO HIgh?

Return to main program

All setup and pulse width times for the ZB500
peripherals are met by the standard ZBOA timing.
In determinIng the interface necessary, the rr
signal to the ZB500 peripherals is assumed to be
the decoded address qualified with the 11l1llr
signal.

The Z8500 perIpherals use INTACK (Interrupt
Acknowledge) for recognItIon of an Interrupt
Acknowledge cycle. ThIS pin, used in conjunction
with RD, allows the ZB500 perIpheral to gate ItS
interrupt vector onto the data bus. An actIve RD
sIgnal during an Interrupt Acknowledge cycle
performs two functIons.
flrst, it allows the
highest prIority device requestIng an Interrupt to
place its Interrupt vector on the data bus.
Secondly, it sets the IUS bit in the highest
PrIOrlty devlCe to indlcate that the device IS
currently under serVIce.

Figure 3a shows the minimum ZBOA CPU to ZB500
peripheral interface timing for I/O cycles.
If
additional Wait states are needed, the same number
of Wait states can be inserted for both I/O Read
and Write cycles to simplify interface logic.
There are several ways to place the ZBOA CPU into
a Wait condition (such as counters or shift
registers to count system clock pulses), depending
upon whether or not the user wants to place WaH
states in all I/O cycles, or only during ZB500 I/O
cycles. Tables 3 and 4 list the ZB500 peripheral
and the ZBOA CPU timing parameters (respectively)
of concern during the I/O cycles. Tables 5 and 6
list the equations used in determining if these
parameters are satisfied.
In generating these
equations and the values obtained from them, the
required number of Wait states was taken into
account. The reference numbers in Tables 3 and 4
refer to the timing diagram in Figure 3a.

INPUT/OUTPUT CYCLES
Although ZB500 perIpherals are designed to be as
universal as possible, certaIn timing parameters
dl ffer from the standard ZBO tlming.
The
followIng sectlOns discuss the I/O interface for
each of the ZBO CPUs and the ZB500 peripherals.
FIgure 5 depIcts lOgIC for the ZBOA CPU to Z8500
perlpherals (and ZBOB CPU to ZB500A perlpherals)
I/O Interface as well as the Interrupt Acknowledge

2-32

Table 3.

l8500 Ti.ing Para.eters I/O Cycles

!forst Case
Min

6.
1.
2.

4.
8.
3.
7.

Address to WR Low Setup
Address to Ro Low Setup
Address to Read Data Valid
IT Low to WR Low Setup
IT Low to Ro Low Setup
Ro Low Width
WR Low Width
Ro Low to Read Data Valid
Write Data to WR Low Setup

TsA(WR)
TsA(RD)
TdA(DR)
TsCEl(WR)
TsCEl(RD)
TwRDI
TwWRI
TdRDf(DR)
TsDW(WR)

Table 4.

Z80A

Ti~ng

Max

80
80
590
0
0
390
390
255
0

Iktits

ns
ns
ns
ns
ns
ns
ns
ns
ns

Para.eters I/O Cycles

!forst Case
Min

Clock Cycle Period
Clock Cycle High Width
Clock Cycle Fall Time
Clock High to Address Valid
Clock High to R5 Low
Clock High to IORQ Low
Clock High to WR Low
Data to Clock Low Setup

TcC
TwCh
TfC
fdCr(A)
TdCr(RDf)
TdCr (IORQf)
TdCr(WRf)
TsD(Cf)

Table 5.
l8500
Para.eter

TsD(Cf)

30
110
85
75
65
50

Value

TcC-TdCr(A)
3TcC+TwCh-TdCr(A)-TsD(Cf)
2TcC+TwCh-TsD(Cf)
2TcC+TwCh+TfC-TdCr(RDf)
TcC-TdCr(A)
2TcC+TwCh+TfC-TdCr(WRf)

Table 6.
l80A
Paranaeter

250
110

Iktits

ns
ns
ns
ns
ns
ns
ns
ns

Para.eter Equations

l80A
Equation

TsA(RD)
TdA(DR)
TdRDf(DR)
TwRDl
TsA(WR)
TsDW(WR)
TwWRl

Max

140
800
460
525
140
>0
560

min
min
min
min
min
min
min

Iktits

ns
ns
ns
ns
ns
ns
ns

Para.eter Equations

l8500
Equation

Address
3TcC+TwCh-TdCr(A)-TdA(DR)

Value

Iktits

160 min

135 min

Ri5
2TcC+TwCh-TdCr(RDf)-TdRD(DR)

2-33

CLOCK

ADDR

CPU
DATA IN

CPU

VALID DATA

DATA OUT

Figure Ja.

Z80A CPU to Z8500 Peripheral Minimum I/O Cycle Ti.ing

Z80B CPU to Z8500A Peripherals

two parameters does not occur because the worst
case of one parameter and the best case of the
other do not occur within the same device.
This
indicates that the value for data available prior
to W will always be greater than zero.

No additional Wait states are necessary during I/O
cycles, although Wait states can be inserted to
compensate for ,any system delays.
Al though the
Z80B timing parameters indicate a negative value
for data valid prior to Ym", this is a worse than
"worst case" value. This parameter is based upon
the longest (worst case) delay for data available
from the falling edge of the CPU clock minus the
shortest (best case) delay for CPU clock High to
W Low. The negative value resulting from these

All setup and pulse width times for the Z8500A
peripherals are met by the standard Z80B timing.
In determining the interface necessary, the IT
signal to the Z8500A peripherals is assumed to be
the decoded address qualified with the ~
signal.

2-34

2296-003

Figure 3b shows the minimum ZBOS CPU to ZaSOOA
peripheral interface timing for I/O cycles.
If
additional Wait states are needed, the same number
of Wait states can be inserted for both I/O Read
and I/O Write cycles in order to simplify interface logic. There are several ways to place the
ZBOS CPU into a WaH condition (such as counters
or shift registers to count system clock pulses),
depending upon whether or not the user wants to
place Wait states in all I/O cycles, or only

during ZBSOOA 1/0 cycles. Tables 7 and a list the
ZBSOOA peripheral and the zaoa CPU timing
parameters (respectively) of concern during the
I/O cycles.
Tables 9 and 10 list the equations
used in determining if these parameters are satisfied.
In generating these equations and the
values obtained from them, the required number of
Wait states was taken into account. The reference
numbers in Tables 7 and B refer to the timing
diagram of Figure 3b.

CLOCK

ADDR

CPU
DATA IN

CPU
DATA OUT

--------f

Figure Jb.

2296-004

VALID DATA

--------

Z80B CPU to Z8500A Peripheral Minimum I/O Cycle Timing

2-35

Table 7.

Z8500A Timing Parameters I/O Cycles

Worst Case
6.
1-

4.
8.
3.
7.

Min
Address to WR Low Setup
Address to iii) Low Setup
Address to Read Data Val1d
CE Low to WR Low Setup
CE Low to iii) Low Setup
iii) Low Width
WR Low W1dth
iii) Low to Read Data Val1d
Wr1te Data to WR Low Setup

TsA(WR)
TsA(RD)
TdA(DR)
TsCU(WR)
TsCEl(RD)
TwRDI
TwWRI
TdRDf(DR)
TsDW(WR)

Table 8.

lkIits

420

ns
ns
ns

80
80
0
0
250
250

180
0

ns
ns
ns
ns
ns

Z80B Timing Parameters I/O Cycles

Worst Case
fcC
TwCh
TfC
fdCr(A)
TdCr(RDf)
fdCr( IORQf)
TdCr(WRf)
TsO(Cf)

Max

Hin
Clock Cycle Per10d
Clock Cycle H1gh Wldth
Clock Cycle Fall T1me
Clock High to Address Valid
Clock H1gh to RB Low
Clock H1gh to IORQ Low
Clock H1gh to WR Low
Data to Clock Low Setup

Table 9.

165
65
20
90
70
65
60
40

lkIits
ns
ns
ns
ns
ns
ns
ns
ns

Parameter Equations

Z8500A
Par_ter

Z80B
Equation

TsA(RD)
TdA(OR)
TdROf(DR)
TwRDl
TsA(WR)
TsDW(WR)
TwWRl

TcC-TdCr(A)
3TcC+TwCh-TdCr(A)-TsD(Cf)
2TcC+TwCh-TsD(Cf)
2TcC+TwCh+TfC-TdCr(RDf)
TcC-TdCrCA)

Value

2TcC+TwCh+TfC-TdCr(WRf)

>75
430
345
325
75
>0
352

m1n
min
min
min
mw
mw
m1n

lkIits
ns
ns
ns
ns
ns
ns
ns

Table 10. Par_ter Equations
Z80B
Par_ter

Z8500A
Equation

TsD(Cf)

Address
3TcC+TwCh-TdCr(A)-TdA(DR)
RD
2TcC+TwCh-TdCr(RDf)-TdRD(DR)

2-36

Value

1k11ts

50 m1n

75 min

Z80H CPU to 18500 Peripherals

enough to satisfy TwWRI (WR" Low Pulse Width).
Assuming that the WR" signal is delayed, only two
additional Wait states are needed during an I/O
Write cycle when interfacing t.he Z80H CPU to the
Z8500 peripherals.

During an I/o Read cycle, there are three l850D
parameters that must be satisfied. Depending upon
the loading characteristics of the m) signal, the
designer may need to delay the leading (falling)
edge of m; t.o satisfy the l8500 timing parameter
TsA(RD) (Address Valid to m; Setup).
Since l80H
timing parameters indicate that the m; signal may
go Low after the falling edge of T2' it is
recommended t.hat the r ising edge 0 f the system
clock be used to delay m) (if necessary). The CPU
must also be placed into a Wait condition long
enough to satisfy TdA(DR) (Address Valid to Read
Data Valid Delay) and TdRDf(DR) (m; Low to Read
Data Valid Delay).

To simplify the I/o interface, the designer can
use the same number of Wa~t states for both I/O
Read and I/O Write cycles.
Figure 3c shows the
minimum Z80H CPU to z8500 peripheral interface
timing for the I/O cyclea (assuming that the same
number of Wait states are used for both cycles and
that both m) and WR" need to be delayed). Figure
4 shows two circuits that can be used to delay the
leading (falling) edge of either the m) or the WR"
signals. There are several ways to place the l80A
CPU into a Wait condition (such as counters or
shift registers to count system clock pulses),
depending upon whether or not the user wants to
place Wait states in all I/O cycles, or only
during l8500 I/O cycles. Tables 4 and 11 list the
Z8500
peripheral
and
the
Z80H
CPU t~mlng
parameters (respectIVely) of concern during the
I/O cycles. Tables 14 and 15 hst the equatlOns
used in determining 1 f these parameters are
satlsfled. In generatlng these equations and the
values obtained from them, the reqUired number of
Wait states was taken into account. The reference
numbers in Tables 4 and 11 refer to the llming
diagram of Figure 3c.

During an I/O Write cycle, there are three other
Z8500
parameters
that
must
be
satisfied.
Depending upon the loading characteristics of the
WR" signal and the data bus, the designer may need
to delay the leading (falling) edge of WR" to
satisfy the Z8500 timing parameters TsA(WR)
(Address Valid to WR" Setup) and TsDW(WR) (Data
Valid Prior to WR" setup).
Since Z80H timing
parameters indicate that the WR signal may go Low
after the falling edge of T2' it is recommended
that the rising edge of the system clock be used
to delay WR" (if necessary).
This delay will
ensure that both parameters are satisfied.
The
CPU must also be placed into a Wait condition long

Table 11.

TcC
TwCh
rfC
rdCr(A)
TdCr( RDr)
rdCr( IORQf)
TdCr(WRr)
TsD(Cr)

1811l Timing Parlllleter I/O Cycles

Equation

Min

Clock Cycle Period
Clock Cycle High Width
Clock Cycle Fall Time
Clock High to Address Valid
Clock High to lID Low
Clock High to IORQ Low
Clock H~gh to WR Low
Data La Clock Low Setup

125
55

Table 12.

10
80
60
55
55
3D

Units
ns
ns
ns
ns
ns
ns
ns
ns

Parameter Equations

18500
Parameter

18m
Equation

TsA(RD)
TdA(DR)
TdRDf(DR)
TwRDI
TsA(WR)

2TcC-TdCr(A)
6TcC+TwCh-TdCr(A) - TsD(er)
4TcC+TwCh-TsD(Cf)
4TcC+TwCh+TfC-TdCr(RDf)
WR - delayed
2TcC-TdCr(A)

TsDW(WR)
TwWRI

Max

Value
170
695
523
503

min
min
min
mln

ns
ns
ns
ns

170 min
mln
563 m~n

ns
ns
ns

>0
4TcC+rwCh+TfC

2-37

-~--",------~-------=----------

Unlts

CLOCK

ADDR

IORQ

WAIT

RDD

READ

CPU
DATA IN

WRITE

------------------------~

CPU

VALID DATA

DATA OUT

figure le.

ZIIIIl CPU to Z8500 Peripheral MiniRa I/O Cycle Titling

2-38

2296-005

to del ay WR (if necessary).
This delay will
ensure that both parameters are satisfied.
The
CPU must also be placed into a Wait condition long
enough to satisfy TwWRl CWR" Low Pulse Width).
Assuming that the ~ signal is delayed, then only
one additional Wait state is needed during an I/O
Write cycle when interfacing the ZBOH CPU to the
ZB500A peripherals.

Z80H CPU to Z8500A Peripherals

During an I/O Read cycle, there are three ZB500A
parameters that must be satisfied. Oepending upon
the loading characteristics of the ~ signal, the
designer may need to delay the leading (falling)
edge of 1m" to satisfy the ZB500A timing parameter
TsA(RD) (Address Valid to liIT Setup). Slnce ZBOH
timing parameters indicate that the ~ signal may
go' Low after the falling edge of TZ' it is
recommended that the rising edge of the system
clock be used to delay ~ (if necessary). The CPU
must also be placed into a Wait cond1tion long
enough to satisfy TdA(DR) (Address Valid to Read
Data Valid Delay) and TdRDf(DR) (~Low to Read
Oat a Valid Oelay). Assuming tha~ the ~ slgnal is
delayed, then only one additional Wait state is
needed during an I/O Read cycle when interfacing
the ZBOH CPU to the ZB500A peripherals.

Figure 3d shows the minimum ZBOH CPU to ZB500A
peripheral interface timing for the I/O cycles
(assuming that the same number of Wait states are
used for both cycles and that both ~ and ~ need
to be delayed). Figure 4 shows two circuits that
may be used t.o delay the leading (falling) edge of
either the ~ or the ~ signals.
There are
several methods used to place the ZBOA CPU into a
Wait condition (such as counters or shift
registers to count system clock pulses), depending
upon whether or not the user wants to place Wait
states in all I/O cycles, or only during ZB500A
I/O cycles.
Tables 7 and 11 hst the ZB500A
perlpheral and the ZBOH CPU tlmlng parameters
(respect1vely) of concern dUrlng the I/O cycles.
Tables 14 and 15 IlSt the equatlons used in
determlnlng if these parameters are satisfied. In
generatlng these equatlons and the values obtained
from them, the requlred number of Walt states was
taken into account.
The reference numbers ln
Tables 4 and 11 refer to the llffilng dlagram of
Flgure 3d.

During an I/O Write cycle, there are three other
ZB500A parameters that have to be satisfied.
Depending upon the loading characteristics of the
WR signal and the data bus, the designer may need
to delay the leading (falling) edge of WR to
satisfy the ZB500A timing parameters TsA(WR)
(Address Valid to WR Setup) and TsDW(WR) (Data
Valid Prior to WR Setup).
Since ZBOH timing
parameters indicate that the WR signal may go Low
after the falling edge of TZ' it is recommended
that the rising edge of the system clock be used
Table 13.

ZBm
Parameter

TsD(Cf)

Parameter Equat10ns

Z8500
Equation

Address
6TcC+TwCh-TdCr(A)-TdA(DR)
RD - delayed
4TcC+TwCh+TfC-TdRD(DR)

Table 14.

Value

lkIits

135 mln

300 mw

Parameter Equations

Z8m
Equation

TsA(RD)
TdA(DR)
TdRDf(OR)
fwROl
TsA(WR)
TsDW(WR)
fwWRl

ZTcC-TdCr(A)
6TcC+TwCh-TdCr(A)-TsD(Cf)
4TcC+TwCh-TsD(Cf)
4TcC+TwCh+TfC-TdCr(ROf)
WR - delayed
ZTcC-TdCr(A)

Value

lkIits

170 mln
695 mw
525 mlll
503 mil

ns
ns
ns
ns

170 min

ns
ns
ns

> 0 min
2TcC+TwCh+TfC

2-39

313 mln

CLOCK

CPU
DATA IN

VALID DATA

I. .

CPU
DATA OUT

VALID DATA

figure Jd.

)

lOOO CPU to l0500A Peripheral Mini_ I/O Cycle Ti.ing

2-40

2296-006

+
74LS32

S
RD(WR)

CLOCK

RDD(WRD)

C
74LS74

RD(WR)

CLOCK

RDD(WRD)

C
74LS74

+
+

S
Q

CLOCK

Rim (Wim)

C
74LS74
RD(WR)

Figure 4. Delaying RD or WR

Table 15.

2296-007

Para.eter Equationa

Z811t

Z8500A

Par_ter

Equation

TsD(Cf)

Address
4TcC+TwCh-TdCr(A)-TdA(DR)
iID - delayed
2TcC+TwCh-TdRD(DR)

2-41

Value

lhits

55 mIn

125 mIn

necessary to give the daisy chain time to settle.
Sufficient time between INTACK active and RD
active should be allowed for the entire daisy
chain to settle.

INTERRUPT ACKNOIIlEDGE CYCLES

The primary tIming d1 fferences between the ZBO
CPUs and ZB500 peripherals occur 1n the Interrupt
Acknowledge cycle.
The ZB500 tIming parameters
that are sign1ficant durIng Interrupt Acknowledge
cycles are 11sted in Table 16, while the ZBO
parameters are 11sted in Table 17. The reference
nl.lllbers 1n Tables 16 and 17 refer to Figures 6,
Ba, and Bb.

Since the ZB500 peripheral daisy chain does not
use the IP flag except during interrupt
acknowledge, there is no need for decoding the
RETI instruction used by the ZBO peripherals. In
each of the ZB500 peripherals, there are commands
that reset the individual IUS flags.

I f the CPU and the peripherals are running at
different speeds (as with the ZBOH interface), the
INTACK signal must be synchronized to the
peripheral clock. Synchronization is discussed in
detail under Interrupt Acknowledge for ZBOH CPU to
ZB500/B500A Peripherals.

EXTERNAl INTERFACE

The following sections discuss external interface
logic required during Interrupt Acknowledge cycles
for each interface type.

During an Interrupt Acknowledge cycle, ZB500
peripherals require both INTACK and RD to be
active at certain times. Since the ZBO CPUs do
not issue either INTACK or RD, external logic must
generate these signals.

CPU/Peripheral Sale Speed

figure 5 shows the logic used to inter face the
ZBOA CPU to the ZB500 peripherals and the ZBOB CPU
to ZB500A peripherals during an Interrupt
Acknowledge cycle. The primary component in this
logic is the Shift register (74LS164), which
generates nITl\l:l(, l!rAl5", and mIT.

Generating these two signals is easily accomplished, but the ZBO CPU must be placed into a
Wait condition until the peripheral interrupt
vector is valid. If more peripherals are added to
the daisy chain, additional Wait states may be

Table 16.

Z8500 Tiaing Parueters Interrupt Acknowledge Cycles

Worst Case

4111z

Min
1.
2.
5.
3.

TsIA(PC)
ThIA(PC)
TdIAi(RD)
TwRDA
TdRDA(DR)
TsIEI(RDA)
ThIEI(RDA)
TdIEr( IE)

IN TACK Low to PCLK High Setup
INTACK Low to PCLK High Hold
INTACK Low to RD (Acknowledge) Low
AD (Acknowledge) Width
R5 (Acknowledge) to Dsta Valid
lEI to R5 (Acknowledge) Setup
lEI to RD (Acknowledge) Hold
lEI to lEO Delay

Table 17.

100
100
350
350

6 MHz

Min

Max

Im.ts

100
100
250
250
250

120
100

ns
ns
ns
ns
ns
ns
ns
ns

1BO
100
70

150

4 MHz

Min

Max

100

Z80 CPU Tilling ParaEters Interrupt Acknowledge Cycles

Worst Case

TdC(M1f)
TdM1f( IORQf)
TsD(Cr)

LOGIC

Clock Hi gh to M1 Low Delay
M1 Low to IORQ Low Delay

6111z
Min
Max

100
575*
35

Data to Clock High Setup
*ZBOA:
ZBOB:
ZBOH:

Max

2TcC + TwCh + TfC - 65
2TcC + TwCh + TfC - 50
2TcC + TwCh + TfC - 45
2-42

B IIIz

Min

BO
345*
30

Max
70

275*
25

Itlits

ns
ns
ns

74LS11

WR.-----------------------------------~~~} - -... WRITE
RESET
RD -------------------~

74LS164
A

74LS04
B

INTACK
QO ~-------_;~~~~... INTACK
74LS04
Q1
74LS04

Q2
Q3

CLR

Q4
Q5

CLOCK

74LS04

QS
Q7

74LS11

74LSOO

WAIT ~-----------_i

'------------c WAIT'
figure 5.

Z80A/Z8OB CPU to Z8500/Z8500A Peripheral Interrupt Acknowledge Interface Logic

Since it is the presence of TIiffAl:I( and an active

During I/O and normal memory access cycles, the
Shift register remains cleared because the ~
signal is inactive.
During opcode fetch cycles,
also, the Shift register remains cleared, because
only Os can be clocked through the register.
Since Shift register outputs are Low, ~,
'I'IIIT1T, and mITT are controlled by other system
logic and gated through the AND gates (74LS11).
During I/O and normal memory access cycles, ~
and 'I'IIIT1T are active as a result of the system ~
and ~ signals (respectively) becoming active.
I f system logic requires that the CPU be placed
into a Wait condition, the mITT' signal controls
the CPU.
Should it be necessary to reset the
system, ~ causes the interface logic to
generate both ~ and 'I'IIIT1T (the Z8500 peripheral
Reset condition).

~ that gates the interrupt vector onto the data

bus, the logic must also generate "RDiD at the
proper time. The timing parameter of concern here
is TdlAi(RD) [TIiffAl:I( to nIT (Acknowledge) Low
Delay].
This time delay allows the interrupt
daisy chain to settle so that
the device
requesting the interrupt can place its interrupt
vector onto the data bus.
The Shi ft register
allows a sufficient time delay from the generation
of TIfi'iiCK before i t generates"RDiD.
During this
delay, it places the CPU into a Wait state until
the valid interrupt vector can be placed onto the
data bus.
If the time between these two signals
is insufficient for daisy chain settling, more
time can be added by taking "RDiD and WAIT from a
later position on the Shift register.
Figure 6 illustrates Interrupt Acknowledge cycle
timing resulting from the Z80A CPU to Z8500
peripheral and the zaos CPU to Z8500A peripheral
interface.
This timing comes from the logic
illustrated in Figure 5, which can be used for
both interfaces.
Should more Wait states be
required, the additional time can be calculated in
terms of system clocks, since the CPU clock and
PCLK are the same.

Normally an
Interrupt
Acknowledge cycle is
indicated by the ZSO CPU when ~ and TUror are both
active (which can be detected on the third rising
clock edge after T1 ). To obtain an early indication of an Interrupt Acknowledge cycle, the Shift
register decodes an active ~ in the presence of
an inactive NRr[ on the rising edge of T2 •
During an Interrupt Acknowledge cycle, the ~
signal is generated on the rising edge 0 f T2.

2-43

2296-00S

--------"'~-----.~

Twa

CLOCK

VECTOR
DATA

-------------------------------------------------4~------------J

Figure 6.

ZSOA/ZIIOB CPU to Z8500!Z8500A Peripheral Interrupt Acknowledge Interface Ti.ing

WAIT signal is removed when sufficient time has

Z80H CPU to Z8500!Z8500A Peripherals

been allowed for the interrupt vector data to be
valid.

Figure 7 depicts logic that can be used in interfacing the ZBoH CPU to the ZB5oo/ZB5ooA peripherals.
This logic is the same as that shown in
Figure 5, except that a synchronizing flip-flop is
used to recognize an Interrupt Acknowledge cycle.
Since ZB500 peripherals do not rely upon PClK
except during Interrupt Acknowledge cycles,
synchronization need occur only at that time.
Since the CPU and the peripherals are running at
different speeds, ~ and 1m" must be
synchronized to the ZB500 peripherals clock.

Figure Ba illustrates Interrupt Acknowledge cycle
timing for the ZBoH CPU to ZB500 peripheral interface. Figure Bb illustrates Interrupt Acknowledge
cycle timing for the ZBOH CPU to ZB500A peripheral
interface. These timings result from the logic in
Figure 7. Should more Wait states be required,
the needed time should be calculated in terms of
PClKs, not CPU clocks.
Z80 CPU to ZSO and Z8500 Peripherals

Our ing 1/0 and normal memory access cyc les, the
synchronizing flip-flop and the Shift register
remain cleared because the 'R1 signal is inactive.
During opcode fetch cycles, the flip-flop and the
Shift register again remain cleared, but this time
because the ~ signal is active. The synchronizing flip-flop allows an Interrupt Acknowledge
cycle to be recognized on the rising edge of T2
when 'R1 is active and ~ is inactive, generating
the INTA signal. When INTA is active, the Shift
register can clock and generate ~ to the
peripheral and WAIT to the CPU.
The Shift
register delays the generation of 'RDIl) to the
peripheral until the daisy chain settles.
The

In a zao system, a combination of ZBo peripherals
and ZB500 peripherals can be used compatibly.
While there is no restriction on the placement of
the ZB500 peripherals in the daisy chain, it is
recommended that they be placed early in the chain
to minimize propagation delays during RET! cycles.
During an Interrupt Acknowledge cycle, the lEO
line from the ZB500 peripherals changes to reflect
the interrupt status. Time should be allowed for
this change to ripple through the remainder of the
daisy chain before activating IORQ' to the ZBO
peripherals, or 'RDIl) to the ZB500 peripherals.

2-44

2296-009

74LS11

WR ~------------------------------------------~~r-~} - - .
RESET ~------------------------------------------~~r-~

__~.

RD ~----------------------------------------~
74LS74

MREQ - - - - - - .

INTA

CLOCK ~--------------+-~

74LS164

74LS04

INTACK

74LS04

IREAD

CLR

PCLK

74LS04

07
74LS11

74LSOO

WAIT
WAIT'

figure 7.

Z80H to Z8500/Z850OA

Peripheral Interrupt Acknowledge Interface Logic

Our ing the RET! cycles, the lEO line from the
ZB500 peripherals does not change state as in the
ZBO pedpherals. As long as the peripherals are
at the top of the daisy chain, propagation delays
are minimized.

Figure 9.
This logic delays the generation of
10RQ' to the ZBO peripherals by the same amount of
time necessary to generate ~ for the Z8500
peripherals.
Timing for this logic during an
Interrupt Acknowledge cycle is depicted in
Figure 10.

The logic necessary to create the control signals
for both ZBO and ZB500 peripherals is shown in

2296-010

2-45

,.......,.T,

Twa

CLOCK

lORa

INTA

PCLK

J,..
OJ

INTACK

WAIT

READ

VECTOR
DATA

figure 8a.

!ll'"

ZOOH CPU to Z8500 Peripheral Interrupt Acknowledge Interface

T~ing

i
TI

Twa

CLOCK

IORQ

INTA

PCLK

,j,.
o...J

INTACK

WAIT

READ

VECTOR
DATA
Figure Db.

Z80H CPU to Z8500A Peripheral Interr....t Acknowledge Interface Tilling

74LS11

~: WRITE
- ! _" ' ' ' -READ
-

~•
-

RESET ~

74LSOO

RD
74LS04

IORQ

M--R-E-Q

~~---------------------

74LS164

74LS04

~
CLOCK

INTACK
74LS04 _ _
h...

QO
Q1

r--o

~ ~

I I

IORQ'

74LS04

[:>0

INTACK

IREAD

74LS04

Q6
Q7

.J
WAIT"

74LS11

74LSOO

__
WAIT'

Figure 9.

ZIIJ and Z8500 Peripheral Interrupt klcnMledge Interface logic

Twa

CLOCK

IORQ

INTACK

WAIT

READ

IORQ'

Figure 10.

lao

and l8500 Peripheral Interrupt Acknowledge Interface Tilling

SOFTWARE CONSIDERATIONS -- POLLED OPERATION
There are several options available for
interrupts on the Z8500 peripherals.
vector or IP registers can be read at
software can be used to emulate the Z80

response. The interrupt vector read reflects the
interrupt status condition even if the device is
programmed to return a vector that does not
reflect the status change (SAVor VIS is not
set). The code below is a simple software routine
that emulates the Z80 vector response operation.

servicing
Since the
any time,
interrupt

l80 Vector Interrupt Response, Emulation by Software

;This code emulates the Z80 vector int.errupt
;operation by reading the device interrupt
;vector and forming an address from a vector
;table. It then executes an indirect jump to
;the interrupt service routine.

INDX:

VECTAB:

LD
OUT
IN
INC
RET
AND
LD
LD
LD
ADD
LD
INC
LD
LD
JP

A,CIVREG
(CTRL),A
A,(CTRL)
A
Z
00001110B
E,A
D,O
HL,VECTAB
HL,DE
A, (HL)
HL
H,(HL)
L,A
(HL)

DEFW
DEFW
DEFW
DEFW
DEFW
DEFW
DEFW
DEFW

INT1
INTZ
INT3
INT4
INT5
INT6
INT7
INT8

2-50

;CURRENT INT. VECT. REG.
;WRITE REG. PTR.
;READ VECT. REG.
;VAUD VECTOR?
;NO INT - RETURN
;MASK OTHER BITS
;FORM INDEX VALUE
;ADD VECT. TABLE ADDR.
;GET LOW BYTE
;GET HIGH BYTE
;FORM ROUTINE ADDR.
;JUMP TO IT

be used in a polled interrupt environment, the TRT
pin 1S connected to the CPU.
The ZBO should not
be set for mode 2 interrupts since the CI0 will
never place a vector onto the data bus. Instead,
the CPU should be placed into mode 1 interrupt
mode and a global interrupt service routine can
poll the CI0 to determine what caused the
interrupt to occur. In t.his system, the software
emulation procedure described above 1S effect.ive.

A SUl'lE ZBO-Z8500 SYSTEM
The ZB500 devices interface eaaily to the ZBO CPU,
thus providing a system of considerable flexibility.
Figure 11 illustrates a simple system
using the ZBOA CPU and the ZB536 Counter/Timer and
Parallel 1/0 Unit (CIO) in a mode 1 or noninterrupt environment.
Since interrupt vectors
are not used, the 'IFJ'rm line is tied High and no
additional logic is needed.
Because the ClO can

+5V
+5V

INT ~--------------------~--------~ INT
8
---------,f--------~I 07-00

07-00

.....

)--------------01

Z80

Z8536

CPU

CIO
WR

A7-Ao

)------------01

I...-+--+-......-------~~--~ A1-Ao
1 0 - - - - _ - - - 0 1 CE

lORa

RESET ~---""'--I
ClK WAIT

Figure 11.

PClK

lBO to lB500 Silllple System ItJde 1 Interrupt or Non-Interrupt Structure

Add~t1onal

1.
2.
5.
4.
5.
6.

ZBO CPU Technical Manual
lBO DMA Technical Manual
ZBO PIO Technical Manual
ZBO CTC Techn1cal Manual
ZBO SIO Technical Manual
ZBOH CPU AC Character1stics

2296-015

Information - Zllog Publications

(05-0029-01 )
( 00-20D-AO)
(03-000B-01)
(03-0036-02)
(05-3033-01 )
(00-2293-01)

7. ZBO fam11~ Interru~t Structure
Tutorial
(611-1B09-0003)
B. ZB530 SCC Techn1cal Manual
(00-2057-01)
9. ZB536 CIO Techn1cal Manual
(00-2091-01)
10. lB03B flO Techn1cal Manual
(00-2051-01)
11. Zll0!l 19B2/B3 Data Book
(00-2034-02)

2-51

. .-

Z800™ 8/16-BII Microprocessor Famll,

___

~~~~_~_

.-------.- ____ --

_~_-o-~-----

- --

- -

Z80® Memory Expansion For
The Z800™
Application
Note

Zilog

March-1983
INTR(l)lJCTION

This application note describes a way in which the
ZSO user can increase memory addressing space to
16M and incorporate memory protection features
while maintaining object code compatibility with
application software.
The memory management
techniques employed here are a subset of those
used by the lSOO series of microprocessors soon to
be released by Zilog. These techniques provide a
direct path to the implementation of some lSDO
features before the fully-integrated solution is
available.

As operating systems grow more sophisticated,
application programs more complex, and the use of
high-level languaqes even more prevalent, the need
for increased memory addressing space and some
form of memory protection becomes critical.
The memory space requirements of many microprocessor applications have grown beyond the 64K
byte addressing range of today's S-bit microprocessors. While the available 16-bit processors
offer dramatically increased memory addressing
capabilities, the conversion to these products
often cannot be justified. For example, in many
cases an application might be better suited for
S-bit processing, and switching to a 16-bit
processor could result in a costlier and less
efficient implementation.
Perhaps even more
serious is the problem of software incompatibility
that occurs when changing microprocessors.
An
ideal so lution is one that both extends memory
addressing space and is object code compatible
with the user's existing software.

MEMORY MANAGEM£NT TECHNIQUES
Before discussing the techniques used to expand
the
addressing
space
and
provide
memory
protection, the concept of logical and physical
addresses and of pages in memory needs to be
explained.
The logical address is the address
generated by the microprocessor, and the physical
address is the address received by the system
memory. In a microprocessor system with no memory
management, the physical address is the same as
the logical address (Figure 1, section a).
In a
microprocessor system with memory management, the
logical address generated by the processor is
translated, or expanded, by the Memory Management
Unit (MMU) before being sent to the system memory
as the physical address (Figure 1, section b).
For example, the 16-bit logical address of the ZSO
could easily be expanded by an MMU to a 24-bit
address.

An additional requirement placed on the user by
today's increasingly complex software is that o·f
maintaining system integrity. In order to ensure
this integrity, various parts of the system software must be protected from illegal access.
Although memory protection features are an important part of memory management, they are not found
on most microprocessors.

3-3
----,

--~-------.--~------------'---

ADDRESS BUS
16

64K (2..)
BYTES OF
MEMORY

8·BIT
CPU

(a)

DATA BUS
8

ADDRESS
BUS

8·BIT
CPU

(b)

MEMORY
MANAGEMENT
UNIT

EXPANDED
ADDRESS
BUS

2" BYTES
OF MEMORY

DATA BUS
8

Figure 1.

Address Expansion with Memory Management

While there are many techniques that can be used
to implement the address translation process, this
application note considers the paging technique
only.
Two concepts are essential to the comprehension of paging: that of a logical page, which
is a section of the address space of the microprocessor; and that of a page frame, which is a
section of physical memory.
A page frame is
simply a fixed-length block of physical memory.
For the purposes of this application note, a page
frame consists of a 4K (4096 bytes) block of
physical memory. Each byte of a page frame can be

unique ly addressed by a combination of 12 address
lines (12 bits specify 4096 bytes).
The 64K
logical address space of an B-bit microprocessor
contains 16 logical pages, and a 16M physical
address space contains 4096 (4K) page frames.
A
memory management system maps the 16 logical pages
that the microprocessor "sees" into 16 of the 4K
page frames in the 16M physical memory (Figure
2) •
By partitioning the physical memory space
into 4K page frames, both memory address space
expansion and memory protection can be easily
accomplished.
4K BYTE WIDE
PAGE FRAMES IN
PHYSICAL MEMORY
FFF XXX16
FFE XXX16
FFD XXX16

16·BIT
MAPPING REGISTERS

FFC XXX16
FFB XXX16

15
14

80016

FFF16
803 XXX16
802 XXX16
801 XXX16
800 XXX16
7FF XXX16

004 XXX16
003 XXX16
002 XXX16
001 XXX16
000 XXX16

Figure 2.

Memory Management System

3-4

2265·001, 002

MEIIIRY ADDRESS SPACE: EXPANSION

The 16 page descr iptor registers allow the user to
access 16 separate page frames (64K bytes of
active memory) at anyone time.
If it becomes
necessary to access a page frame other than one of
the 16 that are current ly active, the operating
system simp 1y uses an I/O instruct ion to load a
new page frame value into the appropriate page
descriptor register.
If the page descriptor
registers are loaded with hex ooo-oor, the
resultant addressing is exactly the same as if the
address space expansion were not present (i. e. ,
the 24-bit physical Address bus addresses memory
locations hex OOOOOO-OOFFFT).

Memory address space expansion consists of taking
a 16-bit logical address output by the microprocessor and generating from that a 24-bit
physical address. The logical address is divided
into two parts, a 12-bit displacement field and a
4-bit index fie ld.
The index field is used to
select one of 16 registers known as page
descriptor registers.
Each page descriptor
register contains 12 bits of addressing information, which is used to identify a page frame in
physical memory.
The page descriptor registers
reside in the I/O space of the system and are
maintained by the operating system. The physical
address is generated by concatenating the 12 bits
of page descriptor information from the selected
page descriptor register with the 12-bit displacement field of the logical address.
Therefore,
when the microprocessor places a 16-bit logical
address on the Address bus, the lower 12 bits
(AO-A 11 ) of the address are presented to the
physical memory and Address bits A12-A 15 are used
to select one of the 16 page descriptor registers.
The 12 bits of address contained in the
selected register are placed on the bus to form
the upper 12 bits of the physical Address
(A12-A n ). This process is shown in Figure 3.

MEIIIRY PROTECTION

The memory protection features are implemented by
using attributes associated with each page frame
of memory. This is accomplished by aSSigning four
bits of attributes to each page descriptor
register.
The page descriptor registers are 16
(rather than 12) bits wide.
When a page descriptor register is selected by Address bits
A12-A15 , both the address and attribute information corresponding to that particular page frame
is accessed. Attribute bits are used by external
circuitry in the memory management system to
monitor the types of accesses made to the page
frames and to record information about the use of
the page blocks. The attribute bits are the Valid
bit, Write-Protect bit, and Modified bit, with one
bit reserved for future use.
A comp lete page
descriptor register is shown in Figure 4.

16·BIT LOGICAL ADDRESS

The Valid bit is used to indicate if the page
frame of memory associated with that particulAr
page descriptor register can be accessed.
This
bit can be read from or written to by performing
an I/O read or write to the appropriate page
descriptor register. If the Valid bit of a page
register is set to 1, it can be used to access
memory.
If the bit is cleared to 0, a memory
access to that register is invalid. When an invalid access is made, an interrupt is generated
and the address that caused the invalid access is
saved for processing by the interrupt service
routine.

16-BIT PAGE DESCRIPTOR REGISTERS

I..
I

_1-.
I 4 BITS

12 BITS

PAGE FRAME ADDRESS

I
I
I

ATTRIBUTE
BITS •

The Write-Protect bit is used to assign read-only
attributes to page frames of memory.
Like the
Valid bit, the Wr ite-Protect bit can be read from
or written to by the user. If the bit is set to
1, the memory is write-protected and an interrupt
occurs i f a write to memory is attempted. When
the Write-Protect bit is cleared to 0, both read
And write operations can be performed. This bit

12 BITS
DISPI:.ACEMENT
24·BIT PHYSICAL ADDRESS

Figure ,.

2265·003

Logical-to-Physical Address
Translation Process

3-5

MODIFIED BIT
l-PAGE FRAME HAS BEEN WRITTEN TO
O-PAGE FRAME NOT YET WRITTEN TO
VALID BIT
l-PAGE OK TO USE
O-PAGE UNAVAILABLE

RESERVED
BIT

WRITE PROTECT BIT
l-READ ONLY
O-READ AND WRITE

Figure 4.

Page Descriptor Register Format

is useful in a system in which multiple processors
share common memory, or in which an operating
system needs to be protected from accidental
writes by an executing program.

Due to the uncertain state of the register content
at power-up, certain provisions are necessary to
ensure that the system behaves in a predictable
manner.
A bypass mechanism known as Pass mode
enables
the
microprocessor
to
begin
its
initialization as if no memory management
circuitry were present.
In Pass mode, logical
Address bits A12 -A15 are passed on to physic a 1
Address bits A12-A15 and the physical Address bits
A16-A23 are set Low. After initializing the page
descriptor registers, the microprocessor can then
enter Address Translation mode.

The Modified bit is a status bit that is automatically set whenever a write is performed to a
logic a 1 address within the page frame. It can be
cleared only by reloading a a into the appropriate
lower bit of the page descriptor register. The
Modified bit is used to indicate if the page frame
has been used for a memory access and is helpful
in determining whether the information in the page
frame needs to be copied to secondary storage
before using the page frame for another purpose.

Table 1.
Port
Address

I/O Port Registers

Registers

LOADING PAGE DESCRIPTOR REGISTERS
X Xa
XXa
XX1
XX1
XX1
XX1
XX1
XX1

The page descriptor registers reside in the
microprocessor's I/O space and are accessed by the
microprocessor's I/O instructions. Each register
is 16 bits long and so must be read to or written
from twice in order to access the full register.
To facilitate this double access, two I/O
addresses are assigned to each page descriptor
register: one for the upper byte and one for the
lower byte. The assigned I/O addresses are listed
in Table 1. The page descriptor registers can be
accessed either individually or (by using the
microprocessor's Block I/O instructions) as a
block in I/O space.

a
3

a
2
3

4
5

XX2 E
XX2 F

3·6

System control port
Page fault and system status
Page descriptor register a (low byte)
Page descriptor register a (high byte)
Page descriptor register 1 (low byte)
Page descriptor register 1 (high byte)
Page descriptor register 2 (low byte)
Page descriptor register 2 (high byte)

Page descriptor register 15 (low byte)
Page descriptor register 15 (high byte)

2265-004

IMPLEMENTATION

MEMORY MANAGEMENT TECHNIQUES

(745219) and an associated multiplexer (745257).
The registers contained in the RAM form the basis
on which the attribute bits are associated with
each page frame.
These registers and the mapper
registers are loaded at the same time, and
together they form a set of 16-bit registers.

Implementation of the memory management techniques
described above for the ZBO consists of circuitry
for the memory address space expansion and memory
protection features, as well as the necessary
logic for power-up and interrupt-handling.

A functional block diagram of the circuit is shown
in Figure 5. The diagram shows two address paths
to the register set through the multiplexer.
Input pins R5 0 -R5 3 se lect a register for reading
or loading during an I/O operation, and pins MAOMA 3 are used to generate a physical address.
Logical address bits A12 -A 15 from the microprocessor are the input signals to the map address
inputs MAO-MA3.

The memory address space expansion circuitry is
based on the 745612 Memory Mapper.
This TTL
circuit contains sixteen 12-bit registers which
are used as page descr iptor registers.
Because
the Memory Mapper's registers are only 12 bits
wide, sixteen 4-bit registers must be added to
utilize the protection features.
These 4-bit
registers are added in the form of a 16 x 4 RAM

a LINES (MOo THROUGH M07)
4

C
CS----~~r-----,

16x12
RAM ARRAY

cs = M

RSo THROUGH R S 3 - - +_ _-+lCS = L

Do THROUGH

r--,
I~

MULTIPLEXER
4
MAo THROUGH M A 3 - + + -........

MAP REGISTER
ADDRESS

MULTIPLEXER
12

L1
12

LATCH
LS610
AND

'- __ ..I

PASS MODE
(MM
H)
MAO
MOa
MAl
M09
MA2
M010
MA3
MOll

Riw'----------L..J

Figure 5.

Hemry Manager Block Diagram

3-7

I ~~~~ I

D11-++-"""--I_--f--f~NATA

STROBE--;--+-----~

2265-005

BUFFER

MOo
THROUGH
MO"

The 74S612 Memory Mapper's Pass mode of operation
is slightly different from the Pass mode previously described, and provisions must be made for
it to operate in the required manner.
In Pass
mode, the 74S612 places the upper four bits of the
logical address (A12-A1S) on what corresponds to
bits A20 -A23 of the physical address while holding
bits A12-A19 Low.
This results in a physical
address that is different from the logical address
and makes Pass mode not useable for initialization. To correct this problem, the registers are
loaded with data that has been rearranged so that
Pass mode operates properly for initialization,
but remains transparent to the user. This is accomplished by arranging the data lines and address
output lines as shown in Figures 6a and 6b.
Memory protection features are incorporated by
examining the attribute bits in the page descriptor register associated with the page frame
of memory being accessed. Writing to or reading
from a block of memory whose Valid bit is cleared
to 0 or attempting to write to a page of memory
whose Write-Protect bit is set to 1 causes a fault
and interrupts the CPU. The Valid bit is tested
during every Read or Write cycle to ensure that
operations on that block of memory can be performed.
If a fault occurs, a nonmaskable interrupt is generated to the CPU and Address bits
A12 -A15 0 f the logical address are latched.
If
the page is valid and a write is requested, the
Write-Protect bit is checked to see if the page of
memory is write-protected.
As in the case of an
invalid access attempt (valid = 0), a writeprotect fault causes a nonmaskable interrupt to be
generated to the CPU, and logical Address bits
A12 -A1S are latched. Since in both cases logical
bits
A12 -A 1 5
are
latched,
the
interrupt

service routine can read these bits to determine
which page descriptor register contains the
attribute bits that caused the faults.
Reading
I/O port 03H causes the four Address bits to be
placed on data lines 00 -03'
The memory management circuit has two modes of
operation:
Pass mode and Address Translation
mode.
When powered up, the circuit is in Pass
mode and the system appears as an unmodified l80.
During Pass mode and Interrupt Acknowledge cycles,
the nonmaskable interrupt is inhibited to prevent
any undesired interrupts from occurring.
Memory
translation is enabled by writing a DOH to I/O
port DOH, and Pass mode can be reestab lished by
writing a 01 H to the same I/O port. The System
mode can be determined by reading bit 4 0 f I/O
port 03 H•
The circuit shown in Figures 6a and 6b was tested
by using a lilog lOS 1/40 Development System with
lAP (lilog Analyzer Program). Since the lOS 1/40
does not have I/O mapping capability, a user clock
was built to provide a complete testing 0 f I/O
ports used in the system. Some useful subroutines
that can be used by the memory management circuit
are given in the appendix.

CONClUSION
The scheme described provides memory expansion and
memory protection by using a flexible paging
mechanism. The scheme is compatible with both l80
object code and the forthcoming Z800 design.
It
therefore bridges the capabilities of the two
compatible microprocessor families and saves both
circuit design and software conversion effort.

3-8

r------------------I
Ao-All
I
I
I
I
I
MEGAMEMORY
I
I
I

I
I

A12-A23

RD
10

MREQ

+5V

WRITE
PROTECTED ----~--+-----------------~--~

VALID

ClK

+5V

'---""-PASS
__~~-MODWR

VALID ----~----~----~----~
D1
WR

74lS02

(F5)
7000W

LS375

6
INHIBIT

PR
4

(l2)

LS138
(D2)
Ao

iOJX
IORQ

3
4
5

A12

A13

A14

AIS

INHIBIT

RESET

G2A
G2B
G1

IOOOW
l5

Figure 6a.

2265·006

Memory Expansion Hardware Schematic

3-9

r---,
A7

Vee

I,.

.ND.......,

;

At As ,..

I-!!- +5V

~c
'-_+__+-_......:.~

.:::.::

iOiQ ....::
..
r

_127

Y2 ~:01:p-

CUB

"'---

(OS)
2-

"-"

M 1""'--+------101

t .
1

b,!!.,o"O 2X

GaA

p.!!... IOOX

10K

+'Y

~~'F

I
I
I
I
I
I
I
I
I
Wii I

MAo
MA,
MA,

"
,.

MA,
ASo

27
14
15

A"
A"
An

AS,

A"
A"
A"

A"
Au

AS,

ill

...

III!

A1.t-A

LS74

h,
(U)
+-__-1'1,'-31..6:,.14)12 ,,,,.... 4

fiERi'

13~5}

CLR Q

za.

+.v

...

,
s
, t tF. •
, lp~

looaw

t·~

Ao-AlI

+'Y

74LS13.

74L,.12
(81)

'f---

" - PREVIOUS REGISTER DATA
IX => PREVIOUS REGISTER ADDRESS
CALoUT:
THROW THE CALL Al-JAV
oRIG. RETURN ADDRESS

DE
DE
JPINIT

POP
POP
JP

******************************
**
LOAD THEN JUMP ROUTINE **
******************************
THIS WILL LOAD THE REGISTER WITH PREDEFINED ADDRESS
THEN JUMP TO THAT LOCATION BV CHANGING THE CONTENT OF
STACK POINTER BEFORE RETURN. THE FORMAT IS FOLLOWED:

--_._------_
_--__________ A_____________
__A __ _
I

••••

...

••

HL REGISTER

'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'-'

1-------I

1------

ATTRIBUTE

A23-A12
•

tit

DE REGISTER

•

_ _________ A ___________ _
'-'-'-'-''-'-'-'-'-'-'-'-'-'-'-'

____ A___

1-------------- All-AO
1-------------------------- LOGICAL PAGE
PASSED PARAM. :
A23-A16 => H
A15-A12 + 4 BITS ATTRIBUTE
LOGICAL PAGE + All-A8 => D
A7-AO =::> E
IX => REGISTER ADDR. TABLE
IV => REGISTER DATA

3-11

=<>

(O-F)

Appendix A.

Sollie Useful Subroutines (Continued)

RETURN PARAM. :
PC=DE
IX => REGISTER ADDR. TABLE
IY => REGISTER SAVED DATA
,JP INIT: CALL
CALL
PUSH
RET

FINDRG
SWAP
DE

FINDRG: LD
SRL
SRL
SRL
SRL
LD
ADD
RET

C.D
C
C
C

;

,JUMP
MOVE LOGICAL PAGE
TO LOWER NIBBLE

B.O
IX.BC

IX POINTS TO THE
REGISTER ADDRESS

THIS ROUTINE ONLY SWAPS THE CONTENT OF 1 REGISTER

SWAP:

LD
LD
LD
IN
LD
OUT
INC
IN
LD
OUT
RET

C HAS THE ADDRESS
NEW LOW BYTE
NEW HI-BYTE

C. (IX+O)
L. (IY+O)
H. (IY+l)
B. (C)
(IY+O).B
(C). L
C
B. (C)
( IY+l ). B
(C). H

SAVE LOW BYTE
WRITE LOW BYTE
SAVE HI-BYTE
WRITE HI-BYTE

******************************
** LOAD PAGE REGISTERS
**
**
SUBROUTINE
**
******************************
PASSED ~ RETURN PARAMETERS:
POINTER TO 1ST DATA => HL
NUMBER OF PAGE => A
POINTER TO 1ST REGISTER ADDR. => IX
LOADRG: PUSH
PUSH
l.D

SLA
LDLOOP: LD
OUTI
~JR

INC
,JP
LDEXIT: POP

HL
IX
B.A
B
C. (I X+O)

2X # OF PAGES 8c
RESET Z FLAG

Z. LDEXIT
IX
LDLOOP
IX

NEXT
3-12

Appendix A.

So. Useful Subroutines (Continued)

POP
RET

******************************
**
SAVE PAGE REGISTERS
**
**
SUBROUTINE
**
******************************
THIS ROUTINE SAVES DATA OF PAGE REGISTERS INTO ARRAY
POINTED BY HL. PASSED & RETURN PARAMETERS:
NUMBER OF PAGES => A
POINTER TO 1ST REG. ADDR. => IX
POINTER TO 1ST SAVED DATA => HL
SAVREG: PUSH
PUSH
LD
SLA
SALOOP: LD
INI
JR
INC
JP
SAEXIT: POP
POP
RET

HL
IX
B.A
B
C. (IX+O)
Z. SAEXn
IX
SALOOP
IX
HL

;
;

;

2X * OF PAGES
RESET Z FLAG
DATA IN

*****************************
** ERROR TRAP HANDLER
**
*****************************
THIS ROUTINE FINDS THE PAGE FAULT WHICH GENERATED NMI.
PASSED PARAMETERS:
REGISTER ADDRESS TABLE POINTER => IX
RETURN PARAMETERS:
FAULT DATA => DE
REGISTER I/O ADR. LOW BYTE => C
CAUSE => A (0 = INVALID ACCESS)
(1 = WRITE PROTECTED)
TRAP:

IN
AND
LD
LD
ADD
LD
IN
INC
IN
DEC
BIT
JR
BIT
JR
LD

A. (3H)
OFH
B,O
C.A
IX.BC
C. (IX+O)
E. (C)

READ PORT 03H
GOTCHA

; C HAS REG. ADDRESS
READ LOW BYTE

D, (C)
C
3.E
Z. NVALID
2,E
NZ. WP
A.2

HI-BYTE
TEST V BIT
TEST WP
THIS SHOULDN'T
3-13
~---~"

---

Appendix A.

So_ Useful Subrootines (Continued)

JP
NVALID: LD
JP
LD
WP:
RET
DONE:

HAPPEN
INVALID ACCESS

DONE
A,O
DONE
AI 1

WP PAGE

3-14

00·2265-01

Increased speed, additional instructions and an addressing scheme that
extends the available memory address space give the Z8108, an updated
version of the Z80 microprocessor, greater flexibility.

On-chip memory management
comes to a-bit JlP
The trend toward the use of high-level
languages in microprocessor-based systems and toward complex configurations
has created the need for more memory
space, greater execution speed, easier access to software libraries, and in general,
more sophisticated processor architectures.
To those ends, the Z8108 is the first 8-bit
microprocessor to provide on-chip memory
management to expand memory addressing and a range of operating speeds of 6
to 25 MHz for increased throughput.
The initial member of the Z800 family,
it is an enhanced version of the popular Z80
with new instructions and addressing
modes for greater flexibility. In addition,
a so-called system mode and a user mode
of operation improve system reliability.
The Z8108 also provides true 16-bit arithmetic capability and performs mathematical operations not done by the Z80.
The 40-pin chip includes a Z80-compatible bus interface with 8 address/data lines and
11 address lines, an on-chip clock oscillator, programmable dynamic memory refreshing, and expanded
I/O addressing (Fig. 1). Because of its less stringent
memory timing requirements, at an operating speed
of 6 MHz the response time of the memories used
need only be 250 ns. The processor's programmableinterrupt daisy-chain delay permits easy interfacing
with most high-speed interrupt-driven devices; no
external logic is required to generate additional wait
states during an interrupt-acknowledgment sequence. Also, a large memory can be directly addressed without external bank-switching circuitry.
Finally, because the processor executes all the instructions of the Z80, existing Z80 programs can be
Roger Whitcomb, Software Applications Engineer
Zllog Inc.
10460G Bubb Rd., Cupertino, Calif. 95014

Reprinted with permission of Electronic DeSign, October 14. 1982
Copyright 1982 Hayden Publishing Co., Inc

simply moved unchanged to the Z8108 for execution
at increased throughput or easily modified to take
advantage of the new processor's capabilities.
Looking at the architecture

Because the Z8108 is binary-code-compatible with
the Z80, it has all the registers of the Z80, including
dual 8-byte register banks A-Land A' - 1'; two 16bit index registers IX and IY; and a dual 16-bit stack
pointer and program counter. One stack pointer is
dedi~ated to system programs (including interrupts
and I traps), the other to user programs. The Z8108
has in addition a master status register that contains
a number of flags to indicate the processor's current
status, Also included are an interrupt and trapvector ta,ble pointer and I/O page registers.
Progralh~ on the Z8108 will be executed in either
the system ~he user mode. System programs have

3-15

Microprocessor Special: Enhanced 8-bitprocessor
access to all registers and instructions, but user
programs are denied access to certain of these
resources in order to provide a more secure environment-for example, one in which programs can be
reserved in protected memory. The user mode is
regarded as a subset of the Z80 instruction set
because some Z80 instructions such as Halt are
privileged in the Z8108 and can only be executed
when the unit is in the system mode. Z80 programs
will operate completely and correctly on a Z8108
since the processor assumes the system mode on
power-up or reset.
The Z8108 addresses memory management in a
number of ways. The on-chip memory management
unit (MMU) maps system and user programs and
instruction and data references separately, and easily remaps memory pages to different physical areas,
thereby permitting easy access to very large physical
memory spaces. Direct access to the memory
management hardware is usuaJly available only to
system programs.
The Z8108's added instructions include some
formalizations of undocumented Z80 instructions
(such as accessing the index registers one byte at a
time), in order to make the entire register set more
orthogonal. Four new addressing modes increase the
flexibility of the existing instructions and make code
generation for high-level languages much easier. In
addition, the Z8108 has a Test and Set instruction
to provide syncJ1fonization for multiple processors,
and both 8-bit and 16-bit multiplication and division
instructions to increase throughput in computationintensive applications.
The programmable bus timing feature increases
system throughput. Control-bit settings allow the
internal processor clock to be scaled for external bus
accesses and wait states to be automatically inserted
during bus cycles, as mentioned. Consequently, the
user can select very high clock speeds to increase
system performance without requiring high-speed
memories and I/O devices.
The interrupt structure of the Z80 has been extended in the Z8108 to include program traps for
exceptions and error conditions and a forced
interrupt-service mode. This new mode provides
automatic vectoring for each interrupt and trap, and
provides support for nested interrupt processing.
With added interrupt-acknowledgment daisychain delay, the contents of a control register may
be used to select a number of additional wait states
to be added to interrupt-acknowledge cycles. Thus,
slow peripheral devices or long interrupt daisy chains
can be accommodated.
The ZSO's input/output address space has been
augmented in the Z8108 by the addition of the I/O
page register that permits one of a number of blocks

of I/O locations to be selected. Changing this register
is a privileged operation that prevents any block from
being accessed illegitimately.
The Z8108 includes an on-chip dynamic memory
refresh controller. Refresh transactions can be
enabled or disabled under program control and the
refresh frequency can be selected. Unlke the Z80, the
Z8108 generates separate bus transactions for
refreshing, thus easing the memory-access timing
requirements. Refresh cycles lost because of DMAbus accesses or wait states are counted and
automaticaJly generated when the CPU regains control of the bus. The Z8108's refresh controller
generates a lO-bit refresh address, ensuring support
for very large dynamic RAM chips.
The on-chip oscillator-clock generator of the Z8108
simplifies system design by eliminating the need for
an external MOS clock generator-driver. A crystal
can be connected directly to the processor, or an
external TTL-compatible clock signal can be provided. From this signal, the processor generates an
internal clock, its frequency being one-half that of
the input.
Addressing modes

Besides expanding the instruction set of the Z80
with four new addressing modes (see Table 1), the
Z8108 extends some of the existing addressing modes
(such as Register Indirect) to other instructions. The
new modes are: Indexed with 16-bit Displacement,
Stack Pointer Relative, Program Counter Relative,
and Base Index.

1. The 40-pin Z81 DB microprocessor has a bus interface
compatible with the ZBO, an on-Chip oscillator whose
frequency is selectable from 6 to 25 MHz, and expandable
1/0 addressing. The ZB1 DB has all the registers of the ZBO,
plus a master status register, an interrupt and trap vector
pointer. and an 1/0 page register for monitoring the
processor's current status. The 16-bit microprocessor
executes all software instructions of the ZBO.

3-16

The Indexed with I6-bit Displacement mode is an
extension of the Z80's Indexed addressing mode and
uses a two-byte rather than a one-byte displacement.
This method permits access to large dynamic data
structures addressed by a pointer or access to arrays
whose base address is known and whose index value
can vary.
The Stack Pointer Relative mode is useful for highlevel language applications where subroutine
parameters and local variables are kept in the stack.
Addresses of these variables are fixed offsets from
the current top of the stack (located by the stack
pointer) and therefore can be accessed directly using
the Stack Pointer Relative mode.
With Program Counter Relative addressing,
position-independent code-that is, code that uses
only addresses relative to the current program location and not absolute addresses-can be produced.
This procedure is useful for standard ROMs and
subroutine libraries that can be loaded at different
locations in memory for various applications, and it
also reduces the time required to link-edit large
programs. The Z80 has a few PC-relative instructions
(all of them jumps), but the Z8I08's PC-relative
instructions include all the conditional jumps and
calls, as well as 8-bit and I6-bit load, store, and
arithmetic instructions.
Based Indexed addressing uses two registers to
address an operand (any combination of the HL, IX,
and IY registers may be used). The contents of the
two are added to produce the effective address. In
that way, both the base address of a structure and

the index or offset can be computed at execution time
(as is required for dynamic arrays). What's more,
Base Indexing can be effectively combined with the
other addressing modes, using the LDA (Load Address) instruction, to build up an arbitrarily complex
addressing mode involving any combination of indexing and indirect addressing.
In addition to the new addressing modes, the old
modes can be used for more instructions-for example, I6-bit Load and Store using the Register Indirect
or Short Index mode, 16-bit ADD using an immediate
operand, PUSH using an immediate value, and PUSH
and POP using direct memory addressing (see Table
2). These extensions give the Z8I08 the power and
flexibility appropriate for both high-level and assembly language programming.
More Instructions

Foremost among the Z8I08's new instructions are
those for multiplication and division. The multiplication instruction has several variations, including an
8-bit-by-8-bit to 16-bit result and 16-bit-by-16-bit to
32-bitresult with the operands addressable using any
of the available addressing modes. Similarly, the
division operations include 16-bit-by-8-bit to 8-bit
quotient and remainder and 32-bit-by-16-bit to 16bit quotient and remainder. The division instructions
check for quotient overflow and attempted division
by zero; these conditions will cause a trap, notifying
the operating system to print a warning message or
to abort the user program.
The Test and Set instruction has been included in

2. The dynamic page relocator uses the processor's memory management unillo map and
enable system and user programs independently. The Z81 08's 16-bitlogic addresses are
divided into two fields for defining the physical addresses and for identifying the required
set of page descriptor registers, one of which is used for system addresses, the other for
user addresses. The state of the enabling flags determines which of the programs are serviced.

3-17

Microprocessor Special: Enhanced 8-bit processor
the Z8108 to support multiprocessing. It tests the
most significant bit of the operand, setting the
condition codes appropriately and then sets the
operand to all Is. This primitive operation is often
used as a signal between two or more cooperating
programs to guarantee exclusive access while updating shared resources.
In addition to 16-bit multiplication and division,
the Z8108's architecture includes other 16-bit
arithmetic operations not found on the Z80. These
instructions include 8-bit and 16-bit Sign-Extend,
Add Accumulator to Addressing Register, 16-bit
Compare, 16-bit Increment or Decrement in Memory,
16-bit Negate, and Full 16-bit Add and Subtract. All

these operations use the HL register pair as a 16bit accumulator.
The entire register set is more fully exploited in
the Z8108 than in the Z80. The Z8108's IX and IY
registers each can be accessed as a 16-bit register
or as two single-byte registers (using any of the 8bit load, store, or arithmetic operations). That
capability in effect makes IX and IY into generalpurpose registers like the BC, DE, and HL pairs.
The Z8108 architecture includes a new group of
instructions for CPU control, to permit access to the
new registers (such as I/O page and master status)
and to handle system and user mode separation. The
LDCTL (Load Control) instruction loads data into, or

Displacement

Shick

POll1ter"

Dl$placement

Relative

,.,'
r"'pon1el\l~!hII_
lIun "hO$! Ild_ Itlh

~
'0

ZS036

counter-I/O
chip

ijj

:f -0

[

"8.

113

I~
II:

lEO

:s0 15
~

counter-itO
chip

lEI

Il(l

'"~
..J

lEO

...

~
i
.&

w
w

!!!

'"0
~

~
«

II)

I~
II:

'"
..J

g!
II)

Floppydisk

controller

Address
decoder

Electronic o.lign • April 28. 1983

3-30

walt

Pause

r:wa~lt~~::)
•••••1I
I~

Non-Maskable In_upt
Interrupt A

Address 0-23

Interrupt B

I ••••••~

Interrupt C

Address/Data 0-15

Bu. Requeat
BUB

Acknowledge

Bufferred Addr.../Data o-t5 (BAllo-BAD,,)

Receive
Transmit
I---_-+-+----o~

Counter-Timer Input 0
Counter-Timer I/O 0
Counter-Tlmar Input 1

Counter-Timer 1/0 1
Counter-Timer Input 2
Counter-Timer 110

I-----+-+-_~
I-----_+----o~

O'E

Address Strobe
Date Strobe
Input Enable
Output Enable

Readl\Nr.te

BiWt--------SYS C L K I - - - - - - -_ _ System Clock

RaedyO
DMA Strobe 0

Reedy 1
DMA Strobe 1

R""dy2
Raady3

ST.I-----l
ST,t-----l
ST,I-----l
ST,I-----l

Intemal Operation

Refresh
I/O Transaction

Stetu.

Halt
Interrupt Acknowledge A

decoder

Interrupt Acknowledge NMI
Interrupt Acknowledge C
Interrupt Acknowledge B
Memory Reference (C8chable)
Memory Reference (Non-C8chable)

5. A complele microcompUler syslem can be buill around Ihe Z8216, because ils powerful
re.ource. eliminate meny peripheral function•• For perallel 110 and interrupt control, two
Z8038. can be addad, and a Z8030 serial communication controller can add two more ..rial
110 channel••

allocate tasks to the slave Z800 processors.
For maximizing board space for memory, the
Z8216 is the best choice_ It offers many of the functions a designer needs to build a microcomputer
board. All that must be added are the interface logic
and buffers required to tie into a system bus like the
IEEE-696 or IEEE-796.
To handle interrupts and provide a parallel port
for a printer, two Z8036 counter-timer and parallel
I/O circuits can be added. For additional serial I/O,
a Z8030 dual-channel serial communications controller can be connected -to the local bus (Fig. 5).
Since the processor contains its own clock oscillator as well as a clock output, all timing can originate from its crystal. One of the counter-timers acts
as a baud-rate generator for the built-in serial port,
and the off-chip serial rommunications controller
has its own baud-rate generator, reducing system
complexity.
The special status and control signals available
from the Z8216 simplify the external logic needed to
generate the bus and buffer control signals. To demultiplex the lower 16 address/data lines, the address latch must simply be strobed with the address
strobe line, and the status lines can readily be deco00-2321-01

3-31

ded by either a 1-of-10 or a 1-of-16 decoder. (The
first 10 status outputs are used in systems that do
not have an extended processing unit, so the smaller
decoder can be used_ If an extended processing unit
is present, the remaining six outputs should be
decoded.)
Since the processor contains its own lO-bit
refresh-address generator, dynamic RAMs as large
as 1 Mbit can readily be handled without the spaceconsuming refresh logic often needed in mediumsize systems. Also, the processor can automatically
generate the appropriate wait states, thus permitting the bus timing to be optimized for the memory
access speed. 0
Acknowledgments

The authors would like to thank Greg Barr, Gary Cole, Monte
Dalrymple, Khue Duong Bob Kurihara, Stanley Lai, Donald
Mar Lan Nguyen, Mike Pitcher, Gurdev Singh, and Irving Stuart/or their valuable contributions to the development of the ZSOO
processors.

How useful?

Circle

Immediate design application
Within the next year
Not applicable

556
557
558

Electronic D..ign • April 28, 1983

Z8000™I6·BII Microprocessor Family

...-...

CosI-Bffeclive .e..ory
Seleclloa for Z8000™ CPU.
Appllcalloa
Nole

Zilog

February 1982
COST EfFECTIVE IEIDlY SELECTION Fm lIIOOO CPUS

situations.
Background for the material in this
application note can be found in the zaooo CPU
Manual
(document
#00-201O-CO)
and t;;- the
Za001/Za002 CPU ~ Specification (documert

The "memory-effective" architecture of the zaooo
CPU is the key to cost-effective system design in
msny app licat ions.
zaooo CPUs are designed to
achieve high performance without the use of highperformance memories.
Because a single application often requires hundreds of memory chips for
each CPU, this memory-effect ive design csn result
in large coat savings.

'iii0-2045-Aii) . -

TIE BASIC FlIIMUlA

Figure 1 shows a generalized view of the information path taken when the CPU issues a valid memory
address. This process ends when valid data, representing the contents of the addressed location
is returned to the CPU. Not all of the elements
shown in figure 1 are necessarily present in every
application, in which case the basic formula is
simplified for that application.

Many factors enter into the selection of CPU and
memory characteristics for a given application.
This application note examines the simple formula
that relates these factors to each other and provides examples of the formula applied in common

LOGICAL

PHYSICAL

j,.

CPU

MMU
ADDRESS

(CD)

11"-

ADDRESS

...
II'

(MA)

(MM)
VALID DATA

DATA AND

JI.

CHECK BITS

II'

MEMORY
ARRAY

ECC

(EC)

This schematic view shows the principal elemerts that enter into the basic
formula relating memory and CPU timing characteristics. Many applications
UBe subsets of these elemerts, ~ich simplifies the basic formula for
those applications.
The two-letter symbol in each box is UBed in the basic formula to represent the time length of that box's task.

Figure 1.
2206-001

1he Addreas-to-Data Path IlIlBtratea the BlBie F_la

4-3

The address issued by the CPU is called a logical
address. It is transformed by the MMU (or other
memory management circuitry) int 0 a physical
address.
The symbol "MM" in Figure 1 represents
the time required for this transformation.
When
no address translation circuitry is present in a
given application, MM=O.

upon constants that depend upon the maximum clock
speed rating of the CPU.
Furthermore, the ZOOOO
architecture allows "wait states" to be inserted
into memory access transact ions.
The number of
wait states inserted is another factor entering
into the formula for CD.
Finally, there are two
possible expressions for CD, depending upon
whether independent timing or the address strobe
signal (AS) is used to signal "address valid."

When a physical address is emitted by the MMU (or
by the CPU if address translation is not used), it
is present ed to the memory array.
After an
interval of time represented by "MA" in the basic
formula, data representing the contents of the
addressed location and check bits associated with
that location appear at the output of the memory.

The published ac characteristics of the ZBOOO CPUs
specify the exact point at which addresses become
valid.
(Parameter 9 of the a: characteristics
table relates this point to a rising clock edge.)
An address strobe signal, AS, is also prov ided by
the ZOOOO CPU.
The rising edge of AS, which
occurs approximately one-half clock period after
addresses become valid, can be used to signal
"address valid."
Use of AS simplifies the
circuitry but places a greater demand on the
memory. Furthermore, no similar signal is available from the MMU circuits designed for use with
the Z8000 CPUs, so that AS can only be used as
described above in a system without memory address
translation (Le., when MM=O).

If no error check/correction circuitry is used in
a given application, then no check bits appear,
and the output of the memory is presented to the
CPU as valid data representing the contents of the
addressed location. If error correction circuitry
is used, then the memory output is input to the
error check/correction circuitry.
After an
interval of time represented by EC in the basic
formula, the output of the error check/correction
circuitry is presented to the CPU as the contents
of the addressed locat ion.

The two ways of comput ing CD (ac characterist ic
parameters 11 and 27) are expressed in the following two equations:

The three time periods represented by MM, MA, and
EC all contribute to the total time elapsed in the
address-to-data path, but one additional calculat ion is required to reach the total. MM, MA, and
EC represent the times elapsed in the corresponding elements in the information path. The remaining term, BD, represents the time elapsed while
passing information between the specific areas.
Thus, BD must include the delays in any buffers
required for interboard bus transfers and time
spent in address decoders or other select ion
logic.
Even the time taken for propagation of
signals must be considered, although the amount is
usually negligible in comparison with MM + MA +
EC.

CD = (2+W)·CP + CH - K1
CD = (2+W)·CP - CF - K2
where:
W=
CP =
CH =
CF =
K1 ,K2 =

< CD

number of wait statea
clock period
clock width (high)
clock faUing time ,
const ants whose values depend on the
rated maximum clock apeed of the CPU

The right hand side of equation (2a) expresses the
time between the actual appearance of a valid
address output and the point at which valid data
is required. The right hand side of equat ion (2b)
expresses the time between the rising edge of AS
and the point at which valid data is required.
The values of K1 and K2 for Z8000 CPUs are given
in Table 1.

The total time elapsed in the address-to-data path
is the sum of the four terms MM, MA, EC, and BD.
This total must be less than the maximum, CD,
specified for the given CPU.
This leads to the
most fundamental form of the basic formula:
MM + MA + EC + BD

(2a)
(2b)

(1 )

The foregoing considerations can now be summarized
in the basic formula (Figure 2).
There are two
versions of this formula, one for each of the two
expressions for calculat ing CD (2a and 2b).

The term CD, however, can also be expressed as a
formula. CD depends partly upon the characteristics of the clock supplied to the CPU and part ly

4-4

TIE ""IT STATE TRADEOff
As ei tl-er version of tl-e basic formuls shows,
adding a wait state to the process increases the
maximum memory access rat ing (MA) by one clock
period (CP).
(Fractions of wait states can be
simulated by "clock stretching," to which the
discussion in this sect ion also applies.)
CPU
performance, however, is lessened by the introduction of wait states.
This sect ion is concerned
with tl-e est imat ion of that reduct ion.

Maximum Rated Clock Speed
4 MHz
6 MHz
10 MHz

130 ns

95 ns

60 ns

120 ns

100 ns

50 ns

Table 1.

The decline in performance level sttributable to
tl-e introduct ion of wait states into memory
accesses is difficult to pinpoint, since each
instruction is sffected differently. For exsmple,
s register-to-register multiplicstion takes 70
clock periods without wait ststes and 71 clock
periods with s wait stste--s reduction of 1.4~ in
execution speed. A register-to-register losd, on
the other hand, tskes three clock periods without

CPU Speed Rating Affects

the Baaic

r~la

The B_ic rOrEla
(Two Versions)

< (2+W)
MA

(A)

• CP + CH - (MM + EC + BD + K1)

< (2+W)

• CP - CF - (EC + BD + K2)

(B)

MA = rated access time of the memory
W number of wsit ststes
CP clock period
CH = clock width (high)
CF = clock fall time
MM memory translation (MMU) overhead
EC
error check/correction overhead
BD = selection logic, buffers, bus delay
K1,K2
constants (see Table 1)

=
=

=
=
=

The besic formula determines the maximum access time for memories used
with a ZBOOO CPU as a function of any factors that might affect it.
The first version of the formula is the general case and assumes that
an independent circuit is used to signal the memory when the CPU or
the MMU emits a valid address. The second version, not applicable if
memory management is used, assumes that the rising edge of sddress
strobe (AS) will be used to generate the RAS or equivalent signal to
the memory.

ri9mt 2.

1he B_ic rOrEla

4-5

--------~~~~~------~------

--------.------~~

wait states and four clock periods with a wait
state--a reduction of 251.l in execution speed.

Since the execution speed of the CPU is inversely
proportional to the clock period, the ratio of the
new speed to the old after the change ~ CP in
clock period is

In one published study (AMD, ZBOOO Benchmark
Report, 1981), five Z8000 programs were analysed.
The objective was to compare ZBOOO performance
with that of competing microprocessors, but
included in the reported results was a performance
comparison of each of the five Z8000 programs with
and without a wait state.
The reductions in
execution speed were 51.l, 61.l, 151.l, 171.l and 211.l.
The 51.l and 61.l reductions appeared in the "automated parts inspect ion" 8'.d "XY transformat ion,
both of which involve many register-to-register
arithmetic operations and few memory reference
instructions. The 151.l and 171.l reductions appeared
in the "block translation" and in the "bubble
sort," both of which involve a great many memory
accesses.
The 211.l reduction appeared in a dummy
'!reent rant procedure," which does almost nothing
other than save and restore the general registers.

CP
CP + ~CP

•

Using values of Wother than 1.

)-1

(4b)

For example, assume that version (B) of the basic
formula has been used with values W = 0, CP =
2500s (4 MHz), CF = 10ns, EC = 0, BD = 6Oos, and
K2 = 120ns.
Then MA < 500 - 10 - (60 + 120) =
310ns. If memories rated at 3500s access time are
desired the required ~ MA is 40ns.
Using (3b),
the required ~ CP is 20ns, leading to a new CP of
270ns, which corresponds to a clock speed of 3.70
MHz. Formula (4b) gives a value of

As the study cited above shows, the effect of
adding wait states varies from application to
application. If a numerical value can be assigned
to the reduction in performance level caused by
wait states in a given application, then that
value can also be compared with the reduct ions
ariSing from other approaches to providing a given
target memory access rating, such as:
Reducing the clock speed (increasing CP).

( 4a)

+ {?",,\.ro
\_.", . . . , I

•

)

+ (2+W) 'CP+CH

~MA

-1

~MA

(

That is, reducing the clock speed to achieve the
desired memory access time results in an 81.l reduction in execution speed.
If, instead, one wait
state had been inserted (increasing the maximum MA
from 310ns to 56Oos), the reduct ions in execut ion
speed for the programs cited above would range
from 51.l to 211.l.

The effect of each of these alternatives can be
ev~luated numerically and compared with the effect
of adding one wait state.

Uaing Values of W Other than 1

RedUcing Clock Speed
Assume that values have been assigned to all of
the vari abIes in the basic formula and that wait
states are desired to achieve a higher upper bound
on MA.
Assume also that a relative performance
level of PO is achieved when W=l. (For example,
for the five programs cited earlier, the values of
Po would be .95, .94, .B5, .83, and .79.) Then,
for either version of the basic formula, the
performance level corresponding to W wait states
is given by

Assume that values have been assigned to all of
the variables in the basic formula and that it is
desired to increase CP to achieve a higher. upper
bound on MA.
If ~ MA is the desired increase in
the right side of the basic formula, then each
version of the basic formula gives rise to an
equation for the required change ~CP:

~CP

~MA

2 + W + CH/CP

(3a)

p
~CP

~MA

+ W

(3b )

4-6

Po
Po + (1 - PO)·W

(5)

The difference of only 5 ns indicates that the
aystem characteristics have been closely matched.
Notics that the clock is running at less than the
rated maximum speed. An increese to the maximum
sllowed for s 6 MHz rated l8001 CPU would result
in a clock period (CP) of 165ns, and thus a maximUIII memory access rating (MA) of 118.
The 5.56
MHz clock speed results in a relative performance
level of 165/180 = .92, or an 8" reduction in
execution speed.

Thus, for example, if insert ion of one wait state
leads to a performance level of .85 (a reduction
of 15"), the inaertion of one-half wait atate (by
clock stretching) leads to a performance level of

.85

P = .85 + (.15)(.5)

or a reduction of

= .92

EXAMPlE Z: A lBOOZ WITH A Z61}Z
EXMI'lE 1: lIE ZIlOG SYSUM 8II9B

The l61J2 quasistatic 4K byte RAM is designed for
use with the l8000 CPUs. For example, with the
lea02's AS line tied direotly to the AC input of
the l61J2 (ses Figure 6 of the l61J2 Product
Specification, documert. nunber 00-Z028-AO, version
(B) of the basic formula can be used:

The lilog System 8000 provides an example that
includes all of the elemert.a of the basic
formula.
The following characteristics describe
the main memory of the System 8009:
MA
W
CP
CH
MM
EC
SO
K1

=
=
=
=
=
=
=

150ns

(dynamic RAM)

(')

1eans
80ns
90ns

(5.56 MHz)

- CF - K2

For 4 and 6 MHz rated CPUS running at maximum
speed and using the longest allowed clock fall
time (ac characteristic parameter 4), the basic
formula gives:

(l8010 MMU, 6MHz rated)

95ns

< 2·CP

(Buffers and selection logic)
(lea01, 6 MHz rated)

MA
MA

< 2·250
< 2·165

- 140 = 360 ns
- 110 = 220 ns

(4 MHz)
(6 MHz)

Version (A) of the bseic formula must hold:
150

00-2206·01

< (2+0)·180+80-(90+40+60+95)

Thus, a 350ns Z6132 can be used with a 4 MHz leoOO
and a zoOns l61J2 csn be used with a 6 MHz l8000.

= 155

4·7

BENCHMARK REPORT
Z8000 vs 8086 vs. 68000

These benchmarks compare the performance of
the Z8001 and Z8002, the Motorola 68000 and the
Intel 8086 running the set of programs which have
become Industry standards for companng microprocessors The data demonstrates that
• The 6MHz Z8oo00utperforms the 8M Hz 68000
and any version of the 8086.
• At any given memory access time, the Z8000
gives higher performance than the 8086 or 68000.
• Any given performance level can be reached with
the Z8000 using slower memories than the 8086
or 68000.
For a demanding microprocessor application the user
has the choice of three competing microprocessor
families
• The Z8000 manufactured by Zllog and AMD
• The 8086 (or IAPX 86/10) manufactured by Intel
• The 68000 manufactured by Motorola
A widely quoted benchmark companson of these
three microprocessors was published by Intel In
1980 under the title' "16-blt Benchmark Report
IAPX86, Z8000 and 68000" (Intel Publication No
AFN01551A)
Not surpnslngly, the Intel 8086 was announced the
winner In that publication Intel achieved this result by
Inefficiently coding the competing devices, thus not
utilizing the powerful Instruction sets of the more
modern Z8000 and 68000 microprocessors
In order to refute the wrong conclusions drawn by
Intel, we purposely used the same benchmarks, and
even the Identical flow diagrams We give Intel the
benefit of the doubt and assumed their performance
figures from the above mentioned document For the
Z8000 and the 68000, however, we rewrote the code
efficiently. We did not use exotic tncks, Just plain
straightforward, efficient coding that takes advantage
of the powerful Instructions of the Z8000 and the
68000.
We made one minor modification to the Intel definition of the Block Translation We wnte the translated
character back Into the same buffer where the EBCDIC
character was stored We see no reason why anybody
would perform a non-destructive translation It wastes
memory space The punst who wants our exact
response to the Intel benchmark should subtract 13%
from the Z8000 performance to accommodate nondestructive translation, which happens to be less efficient on the Z8000, but does not affect the 8086 and
68000 performance.

reference gray shade held In memory The program
controls the X-Y scan control to the camera by means
of two 7 -bit D-A converters and reads the resultant
gray shade Signal via a 12-blt A-D converter

I I \\
\ \
\ \

I I
Reject Part
Advance Conveyor

ZO=Good Dala
Z=Measured Data
Percent= Percent
Compute Toler:::: ZO·Percentl100
and Start AID Converter

Tolerance

Input Z From AID Converter

Automated Parts Inspection

Block Translation - Destructive

The block translallon benchmark translates a stnng of
EBCDIC characters Into a stnng of ASCII characters,
and overwntes the EBCDIC stnng. The benchmark
assumes 121 characters In the source stnng

Description of Benchmark Tests

The benchmark tests used In this performance
evaluation were selected for vanety and are
representative of applications Including data
processing, Image processing and anthmetlc
processing Detailed coding IS shown In the appendix.
Automated Parts Inspection

The automated parts inspection program controls the
Interface to an image-dissector camera, and compares
the gray shade Signal from each of 16,384 pOints to a

Reprinted with permIssion of Advanced Micro Devices

a CJa

4-9

;~
Relative
Performance
3.0 _WMl ___
n _ _' _ '_ _ _ t_-=_ _

;
~_"

;~ooo

Z8000B / ;
______
_ _ _ _ _ _ _ _ __
~

2.5 - " wmWN

2.0 ------,-------~,.,-------~~-- - - -

1.0

3
Figure 1

Relative Performance as a Function of Clock Frequency

Maximum frequencies are shown for available speed selections. Dotted lines Indicate planned
extensions.

4-10

10
MHz

BubbleSorl

_L2_

The bubble sort is a well-known algorithm for sorting
data elements into one sequence (in this case, numerically ascending order). The benchmark assumes that
a one-dimensional array of ten elements is to be sorted
and that the elements are intitially in numerically
descending order.
Array(O)

750

Array(O)

(1)

700

(1)

(2)

650

(3)

600

(4)

550

(5)

500
450

(6)

XO. YO

Expand The Selected
Window To Fill The
Screen

300

(2)

Arrange In
Ascending Order

(3)
(4)
(5)
(6)

550
600

(7)

400

(7)

650

(8)

350

(8)

700

(9)

300

(9)

750

Count = Number Of XY Pairs

Count = Number of Integers
In Array

Computer Graphics XV Transformation
ThiS flowchart was originally presented by Intel

Bubble Sort

XV Transformation
The XY transformation scales a selected graphic window c~ntaining 16-bit unsigned integer XY pairs. Each
X data IS offset by XO and multiplied by a fractional
scale factor L2/L1. Each Y data is offset by YO and
multiplied by the same scale factor. The benchmark
assumes the selected window contains 16 384 XY
pairs.
'

4-11

Reentrant Procedure
This benchmark demonstrates the ability of the processor to handle reentrant procedures and parameter
passing between procedures. The input parameters
are passed (by value) to the procedures. Prior to the
call, the first parameter is in one of the general registers
while the second and third parameters are stored in
memory locations PARAM2 and PARAM3, respectively.
Upon entry, the procedure preserves the state of the
processor, and it is assumed that the procedure uses
eight of the general-purpose registers. Next, the
procedure allocates the storage for three local
variables (LOCAL1 , LOCAL2, LOCAL3). The
procedure then adds the three passed parameters
an.d stores the result in the first local variable. Upon
eXit from the procedure, the state of the processor is
restored.
Table 1 shows execution times for each benchmark
on each microprocessor without and with one Wait
State. Execution times are then inverted to indicate
performance (not time), and normalized with respect
to the slowest device, the 5MHz iAPX 86/10 (i.e. the
original 8086). As can be seen from the detail data in
the appendix, the Z8001 and Z8002 are so similar in
performance that they can be grouped together.
Figure 1 shows the average performance data
graphically.

Benchmark

Z8000B
[8MHzJ
OW
1W

Absolute Performance
Auto Parts
478
Inspection
Block
388
Translation
539
Bubble
Sort
793
XY
Transformation

256

Rcc~truj"',t

Z8000A
[6MHzJ
OW
1W

Z8000
[4MHzJ
OW
1W

68000-10
[10MHzJ
OW
1W

68000-8
[8MHzJ
OW
1W

iAPX86/10
[10MHzJ
OW
1W

iAPX86/10
[8MHzJ
OW
1W

508

637

677

956

1016

470

498

587

623

668

708

835

885

456

517

607

776

912

757

916

946

1145

744

824

930

1030

'"s

646

718

861

1078

1292

507

614

634

768

912

1007

1140

1057110315851655777

804

971

827

325

1259,"s

10051120115214001440

Procedure

Performance Relative To iAPX 86/10 @ 5MHz
Auto Parts
28
2 63
21
1 97
Inspection
3 84
3 26
2 88
2 45
Block
Translation
3 38
2 82
2 54
2 12
Bubble
Sort
282
271
2 12
203
XY
Transformation
242
19
1 82
1 44
Reentrant
Procedure
Average
Relative
Performance

3.05

2.66

2.28

1.99

131

284

2.68

2.27

214

2.00

189

1.60

1.51

1 92

1 63

1 96

1 62

1.57

2.00

1 81

1 60

1 44

1 69

1 41

2.97

2 87

2 38

2 00

1 81

1.60

1 45

1 41

1 35

288

2.79

2.3

2.23

2.00

1 94

1 60

1 56

1 21

095

248

2.00

1 93

1.59

200

1 77

1.60

1 44

1.53

1.34

2.75

2.4

2.19

1.93

2.00

1.84

1.60

1.48

OW = No Wait State, 1W = One Walt State per memory access.
Table 1

Memory Access Time

The benchmark data compares the performance of
the three microprocessors at nominal clock rates
without regard to the memory access time required
to achieve the performance.
Memory speed is however, an important systems
consideration since it has a strong impact on memory
cost and the design of the supporting Circuitry. In most
systems memory cost far exceeds the cost of the CPU.
It is therefore more useful to treat the CPU clock frequency as a variable and plot performance as a function of memory access time requirement. For each
CPU, the memory access time requirement can be
relaxed by using a higher speed version of the CPU, by
lowering the actual clock frequency, or by adding Wait
States.
Data sheets for the various microprocessors indicate
the relationship between memory access time and
clock period Every Wait State adds another clock
period to the memory access time.
TAe =(K+W)T-D
TAC = memory access time required (at CPU pins)
K
= clock cycles/access (K=3 for the 8086,
K=2.5 for the Z8000 and 68000)
W = number of Wait States inserted (usually 0 or
1)

T
D

= actual clock period in ns
= sum of time for CPU delays, set-up times,
etc. This is a constant for a given part type
and speed selection. See Table for value.

4-12

Device

TAC In nanoseconds for various

~~U:I; T0; _1_)
f max

Device
and
Speed
Selection

Z8001.
Z8002
Z8001A.
Z8002A
Z8001 B.
Z8002B
68000-4
68000-8
68000-10
8086-5
8086-8
8086-10

4MHz

250ns
[4MHz)

150n8

475

167ns
[6MHz)

125ns
[8MHz)

6MHz

530

320

8MHz
4MHz
8MHz
10MHz
5MHz
8MHz
10MHz

75
120
90
80
140
80
60

550
505
535
545
610
670
690

340

238

325
335

223
233

410
430

295

315

Table 2 Memory Access Times Required

100ns
[10M Hz)

170
240

The relative performances computed previously are
obviously directly proportional to the clock frequency
used. That is, for a given device selection, the relative
performance is Inversely proportional to T, the actual
ciock period. The memory access time requirement IS
also related to the clock period.
TAC
and,
Therefore,

being allowed to vary as required, down from the maxImum for the part selection. As the clock frequency
IS reduced, a point is reached where equal performance
can be achieved by raising the ciock frequency back
up and inserting a Wait State. This results In the same
performance but a lower memory access time requirement, so it IS logical to do so.
Table 3 contains computed data of memory access
time requirements as a function of relative performance
for each device selection with 0 and 1 Walt States.
Figure 2 plots this data and shows the point at which
the Walt State can be inserted without redUCing
performance

+ D = (K + W)T = K1 T
RP
RP

=T
K1K2
TAC + D

and Relative Performance can be plotted against
memory access time required, with the ciock frequency

Relative
Performance

3.5------------------------------------------------------------Z80008

3.0------~~~;..;.;;.-------------------68000-10

a~!...W.!t~~

2.5------~~~~~~~--------------~~-------------------------

Z8000

1.5-------..;:a.,..----~~~~~;::~

1.0--------~1~------~-------&--------L--------L------~~
200
250
400
450

300

350

______500
~______
550

_L____

Fig. 2 Relative Performance as a Function of Memory Access Time
Wait States are inserted when they reduce access time requirements without affecting performance
(clock frequency is raised).

4-13

-----------

Relative
Performance

34
33
32
31
30
29
28
27
26
25
24
23
2.2
21
20
19
18
17
16
1.5
14
13
1.2
11
10

~----.-

Z8000B

Z8000A

Z8000

68000-10

68000-8

iAPX86/10

(1 s 8MHz)
W=O W=1

(1 s 6MHz)
W=O W=1

(100 4MHz)
W=O W=1

(1:5 1OM Hz)
W=O W=1

(1:5 8MHz)
W=O W=1

(f :5 10MHz)
W=O W=1

(I :58MHz)
W=O W=1

243
254
266
279
292
307
323
340
359
380
402
427
455
487
522
561
607
659
721
793
880

373
391
410
432
455
480
508
538
572
610
653
702
757
821
896
984
1090

335
356
378
403
431
462
496
536
581
633
694
765
851

486
517
551
589
631
680
735
799
873
961
1067

488
533
586
647
719
806

827
916
1023

175
184
195
206
219
233
247
264
282
302
324
350
378
411
449
493
545
608

270
285
302
320
340
362
387
414
445
480
520
566
620
684
760

221
235
252
270
290
312
337
366
398
436
479
531
593

354
379
406
437
472
512
559
613
677
753

240
256
273
293
315
340
369
402
440
485
540

349
373
400
431
466
506
553
609
676

295
320
349
382
420
465
520

413
--449
489
537
593
660

W=O = No Walt State, W= 1 = One Walt State per memory access
Table 3 Required Memory Access Time to Achieve a Given Relative Performance (in nanoseconds)

What This Benchmark Does And Doesn't Tell You
Benchmarks are popular simplifications to compare
the performance of different microprocessors, Like
all other simplifications, benchmarks must be used
with care.
At best they accurately compare the performance
of different microprocessors In a limited set of applications, which mayor may not be representative of the
applications that the user needs.
At worst they are distorted by a manufacturer who
wants to "prove" that his device is the best. By choosing
examples that favor a particular microprocessor ormore deviously - by Writing IneffiCient code for the
competitor's device, any manufacturer can "prove" that
hiS product is superior to the competition's.
Moreove~ benchmarks describe only one aspect of
the microprocessor: speed (or throughput). Other
Important technical considerations are:

Benchmarks tell nothing about these important aspects,
In spite of these limitations, benchmarks are an
Important tool for adding quantitative data to the complicated task of selecting the right microprocessor,
The soon-to-be-announced 8MHzZ8000B is 11%
faster than the soon-to-be-announced 10MHz
68000-10, and the Z8000B achieves thiS superior
performance even With substantially slower memories,
The 6MHz Z8000A is 4% faster than the 8MHz
68000-8, and the Z8000A can tolerate memory access
times 1OOns longer than required by the 68000-8,
The iAPX 86, even In its fastest 10MHz version is no

contender
The Z8000 is better,

• Code efficiency
• Ease of programming
• Ease of interfaCing to memory and I/O
• Availability of powerful peripheral devices
• Availability of hardware and software support
Finally there are good business reasons for favoring
a particular microprocessor:
• Price, availability and multiple sourcing
• Vendor reputation and quality of field application
support
• DeVice reliability and quality level.

4-14

APPENDIX
II of Clock Cycles

Z8002

BYPASS

LD R12, PER CENT ,Load Percent Tolerance
7+2W
LD R8, j GRAYTAB ,Gray Table Base Address
7 + 2W
,Number of Scans
LD RO, 16383
7+2W
LD R10, SIGNAL
,Load AID Converter
Address
7 + 2W
LD R11, XYSCAN
,Load Addresses for the
2 DIA Converters
7+2W
LD R13, REJECT
,Load Reject Port Address
7+2W
LOOP

OUT R11, RO
IN R4, R10
LD R3, R8j
INCR8,2

ENDTEST

DIV RR2, #100
SUBR4, R1
JRGEBYPASS
NEGR4
BYPASS

JR LE ENDTEST

ENDTEST

OUTR13, R4
DJNZ RO, LOOP

CONSTANT
CONSTANT
CONSTANT
CONSTANT
GRAYTAB

PERCENT=
SIGNAL=
XYSCAN=
REJECT=
WORD (16384)

,Write XY Coordinates
* 10 + W
,Z=R4 (Read Signal)
* 10+ W
,ZO=R3 (Read Reference)
* 7 +2W
,I nc Reference POinter
,R1=ZO
* 3+ W
,R3=ZO*PERCENT
* 70+ W
,R3=ZO*PERCENT1100
* 95 + 2W
,R4=Z-ZO
* 4+ W
,R4 '" 0
* 6+ W
,R4R4 = I Z-ZO I
7+ W

LOOP

Z-ZO I -ZO * PERCENTI
100
* 4+ W
,I Z-ZO I <20* PERCENTI
100
* 6
+
W
10 + W
,Reject Signal
,Process Next POint
* 11 + W

BYPASS

LOOP

ENDTEST

W
W

MOVEW

D6, #PERCENT

MOVEL

A3, #GRAYTAB

MOVEW

A5, #XYSCAN

MOVEW

A6, #REJECT

MOVEW

A4, #SIGNAL

MOVEW

(A5), DO

MOVEW

D4, (M)

MOVEW

D3, (A3)+

MOVEW
MULU

D1, D3
D3, D6

DIVU

D3, #100

SUBW

D4,D1

CMPWD4,D3

BLE

ENDTEST

MOVEW

(A6), D4

DBF

DO, LOOP

,Numberof
scans
--> DO
8 + 2W
,Percent
Tolerance
--> D6
8 + 2W
,Gray Table --> A3
12+3W
,D/A Address
--> A5 8 + 2W
,Address of
Reject Message
-->A6 8 + 2W
;NDAddress
-->A4 8 + 2W
,WrlteXY
Coordinates
9+2W
,Read Signal D4
8+ 2W
;Read Reference
8 + 2W
D3
4+ W
;D3=D3*D6
70+ W
,D3=D3*D6/100
144 + 2W
,D4=Z-ZO
4+ W
,D4<0
8/10 + W
,D4 D4
Z-ZO 4+ W
,I Z-ZO I-ZO*
PERCENT/100
4+ W
;1 Z-ZO IO
8192tlmes
Z-ZO 0 5/19 + W

# of Clock Cycles

68000
BSORT

10 {INIT

COMpo

MOVEAL A1,400

,StartAddress~

MOVEW

03,404

,Count~D3

SUBQ
CLR.B

03,#1
01

A1
12 +3W

MOVEAL AO,A1
MOVEW

00,03

MOVEW
CMP

D2,(AO)+
(AO),D2

BLS.S

DECCNT

MOVEW

(AO)(-2),(AO) ;No. Exchange these
17+4W
(AO),D2
,two words
9 + 2W
01
,Exchange Flag=1
4+3W
DO,COMP
;Done?
10 + 2W/14 + 3W
01
;No. Test Exchange
Flag
4+ W
INIT
,
8/10 + W

FINISH
Total Number of clock cycles. 7,400 + 800W

8/10

C. Bubble Sort

# of Clock Cycles

Z8002
BSORT

LD R4,ADR

MOVEW
TAS

,Load Starting Address

9+3W
LDR5,COUNT ;Load Word Count
9 + 3W
DECR5
;Set Number of Compares
4+ W
RESB RL6,0
;Clear Exchange Flag 4 + W
LDL RR2,RR4 ,Copies of Adr and Count
10
5+ W
COMP
LDL RRO, R2! ,Fetch 2 words In RO,R1
11 +2W
CP RO,R1
;Out of Order?
4+ W
JR LE DECCNT ,No-Continue
6+ W
EX RO,R1
,Yes-Swap them
6+ W
LDL R2!,RRO ,Store Back
11 +2W
SETB RL6,0
4+ W
DECCNT INC R2,2
;Polntto Next Pair
4+ W
,Decr, Word Count
4+ W
DECR3
6+ W
JRGTCOMP ;Done?
,Exchange Flag = 1? 4 + W
BITBRL6,0
10
JRNZINIT
,Yes·Start Next Pass 6 + W
,No-Done
10
Total clocks 22 + 7W + 10 (19 + 4W) + 1:
[(10-m)(56+11W)+
m=1
(M-1)(35+7W)] = 212 + 47W + 45 (91 + 18W) = 4307 + 857W

DECCNT DBE
NOTB

j'"n

LS
BSORT

BPLS

{ INIT

LDL RR12, ADR
LDR5, COUNT
DECR5
RESB RL6,0
LDL RR2,RR121'
LD R4,R5

+ W

Total clocks 32 + 8W + 10 (22 + 4W) - 2 +

1£

iAPX86/10

# of Clock Cycles

m=1
[(10-m)(68+15W)+(m-1)(40+8W)-10(4 + W)] =
5070 + 1072W

MOVBL,OFFH

,EXCHANGE=TRUE

4
A1

JNEA4
XORBL,BL

, EXCHANGE=TRUE?
4
; NO, FINISHED 4/16 +
; EXCHANGE=FALSE

MOV CX,COUNT

; CX=COUNT-1

CMPBL,OFFH

3
14+ W

DECCX

# of Clock Cycles

Z8001

12 + 3W
4+ W
,Exchange Flag = 0
4+ W
;Copy Start Address
IntoAO
4+ W
;Copy Count Into DO
4+ W
,Fetch word 8 + 2W
;Next word greater?
8+2W
;Yes, Continue

XORSI,SI

;SI=O

SS
A2: MOV AX,ARRAY(SI)
CMP AX,ARRAY(SI+2)
JLEA3
XCHG ARRAY(SHZ},AX

15+4W/13+3W
9 + 3W
4+ W
4+ W
5+ W

ARRAY(SI),AX

3+ W

4-17

,ARRAY(I) >17 +
;ARRAY(I+1)?
18+
; NO
4/16 +
;EXCHANGE ELEMENTS
6+
18+

W
W

iAPX 86/10 (Continued)
MOVBL,OFFH

4+ of Clock Cycles

68000 (Continued)

; EXCHANGE=TRUE

4
A3' INCSI
INCSI
LOOPA2

,SI=SI+2

2
2
; DEC CX & LOOP IF<>O
5/17 + W
15+ W

XYSCAL:

JMPA1
A4'
Total number of clock cycles. 9,120 + 950W

MOVEW D1 ,(A3)
SUBWD1,D5
MULU D1,D6
DIVU D1,D7
MOVEW (A3)+,D1

D. Computer Graphics XY Transformation
4+ of Clock Cycles

Z8002
Cycles
LDR2,COUNT
LD R3,jARRAY

XYSCAL

LD R4,XO
LD R5,YO
LD R6,L2
LD R7,L1
LD R1,R3j
SUBR1,R4
MULTRRO,R6
DIVRRO,R7
LD R3j,R1
INCR3,2
LD R1, R3j
SUBR1,R5
MULTRRO,R6
DIVRRO,R7
LD R3j,R1
INC R3,2

;INIT COUNT
9 + 3W
;INIT ARRAY POINTER
7 + 2W
9+3W
;INITXO
;INITYO
9+3W
;INITL2
9+3W
;INITL1
9+3W
,GET X ELEMENT 7 + 2W
;X-XO
4+ W
;(X-XO) *L2
70 + W
;(X-XO) *L2/L 1
95 + W
;STORE ELEMENT 8 + 2W
,INC POINTER
4+ W
,GET Y ELEMENT 7 + 2W
;Y-YO
4+ W
;(Y-YO)*L2
70 + W
,(Y-YO)*L2/L1
95 + W
;STORE ELEMENT 8 + 2W
,INC POINTER
4+ W

DJNZ R2,XYSCAL

;DEC R2 & LOOP IF
,R2<>0
11 +

DBF D2,XYSCAL

MOV CX,COUNT
MOV SI,OFFSET(ARRAY)
MOVDI,SI
CLD

4+ of Clock Cycle

;GET X ELEMENT 7
;X-O
4
;(X-XO)*L2
70
,(X-XO)*L2/L 1
95
,STORE ELEMENT 8
;INC POINTER
4

LD R1, RR8j
SUB R1,R4
MULTRRO,R5
LD RR8j,R1
INC R9,2
DJNZ R2,XYSCAL

;GET Y ELEMENT 7 +
;Y-YO
4+
;(Y-YO)*L2/L1
70+
,STORE ELEMENT 8 +
;INC POINTER
4+
11 +

+ 2W
W
+ W
+ W
+ 2W
+ W

LaDS ARRAY

E. Reentrant Procedure
Z8002

4+ of Clock Cycles
PUSH R15j,R8

2W
W
W
2W
W
W

PUSH R15j,PARAM2
PUSH R15j,PARAM3
CALR PROC1
INCR15,6

Total clocks 60 + 17W + 16384(387 + 17W) = 6,340,668
+ 278,545W

68000

PROC1

4+ of Clock Cycles
MOVEW D2,COUNT
MOVEW A3#ARRAY

,INITCOUNT
14+ W
,INIT ARRAY
POINTER 4
;INIT ARRAY
POINTER 2
;DF=FORWARD

;GET X ELEMENT
12+ W
,X-XO
15+ W
SUB AX,XO
;(X-XO)*L2
MULL2
130+ W
;(X-XO)*L2/L 1
DIVL1
161 + W
;STORE ELEMENT
STOSARRAY
11 + W
,GET Y ELEMENT
LaDS ARRAY
12 + Y
;Y-YO
SUBAX,YO
15+ W
;(Y-YO)*L2
MULL2
130+ W
,CY-YO)*L2/L 1
DIVL1
161 + W
,STORE ELEMENT
STOSARRAY
11 + W
LOOPXYSCAL
,DEC CX & LOOP IF
5/17 + W
,CX<>O
Total number of clock cycles = 11,200,000 + 320,000W

XYSCAL'

LD R1, RR8j
SUB R1,R3
MULT RRO,R5
DIV RRO,R6
LD RR8j,R1
INC R9.2

4+ of Clock Cycles

iAPX86/10

Cycles
;INIT COUNT
LDR2,COUNT
9 + 3W
LD R3,XO
,INITXO
10 + 3W
LD R4,YO
;INTYO
10 + 3W
LD R5,L2
,INIT L2
10 + 3W
;INITL1
10+3W
LD R6,L1
LDL RR8,jARRAY ,INIT ARRAY POINTER
11 +2W
XYSCAL:

4+ of Clock Cycles
,INITXO
12 + 3W
;INIT YO
12 + 3W
,INIT L2
12 + 3W
;INITL1
12+3W
,GETX
8 + 2W
,X-XO
4+ W
;(X-XO)*L2
70 + W
;(X-XO)*L2/L 1 140 + W
,STORE & INC POINTER
8 + 2W
;GETY
8 + 2W
,V-YO
4+ W
,(Y-YO)*L2
70 + W
,(Y-YO)*L2/L1' 140 + W
;STORE & INC POINTER
8+2W
14 + 3W/10 + 2W

Total clocks: 64 + 16W + 16386 (474 + 17W) = 7,766,016
+ 278,544W

Total clock cycles = 52 + 17W + 16384 (387+17W)
= 6,340,660 + 278,545W

Z8001

MOVEWD4,XO
MOVEWD5,YO
MOVEWD6,L2
MOVEW D7,L1
MOVEW D1(A3)
SUBWD1,D4
MULU D1,D6
DIVU D1,D7
MOVEW (A3)+,D1

,INIT COUNT
12 + 3W
;INIT ARRAY POINTER
8+2W

4-18

PUSH R15j,R14
LD R14,R15
SUB R15,6+16

,R8=PARAM1
9+
,PUSH PARAM2
13+
;PUSH PARAM3
13 +
10 +
;Remove PARAM13 from the Stack
4+
;Save R14
9+
;Initialize R14
3+
;Set up Local
Storage
7+

2W
4W
4W
W

W
2W
W
2W

Z8002 (Continued)
LDM R15[,RO,S
,PROCEDURE BODY
LD RO,S(R14)

68000 (Continued)

'" of Clock Cycles

,GetPARAMl
10+ 3W

ADD RO,6(R14)

,ADD PARAM2

ADD R0,4(R14)

,ADD PARAM3

LD -2(R14),RO

10+ 3W
,Store In LOCAL 1
12 + 3W

10 +

,PROCEDURE RETURN
LDM RO,S,R15[
ADD R15,6+16
POP R14,R15[
RET

SUB

LINK A6,#6
MOVEMW OFFO,-(SP)

,PROCEDURE BODY
MOVEW DO,A6( +10)

,Restore General
Registers
35 + lOW
:Restore SP to POint
toR14
7 + 2W
:Restore R14
lS + 2W

ADD W DO,A6( +6)
MOVEW A6(-2),DO
,PROCEDURE RETURN
MOVEMW (SP)+ ,OFFO

Z8001

'" of Clock Cycles
PUSH RR14[,RS
PUSH RR14[, PARAM2
PUSH RR14[, PARAM3

UNLK A6
RTS

,RS=PARAMl
9+ 2W
,Push PARAM2
14+4W/16+ 5W
,Push PARAM3
14+4W/16+ 5W

PUSHL RR14[,RR12
LDL RR12,RR14
SUB R15,6 + 16

LDM RR14[,RO,S
,PROCEDURE BODY
LD RO, 12(RR12)
LD Rl ,10(RR12)
ADDRO,Rl
LD Rl ,S(RR12)
ADDRO,Rl
LD -2(RR12),RO
,PROCEDURE RETURN
LDM RO,S,RR14[
ADD R15,6+16
POPL RR12,RR14[
RET

PROCl

3W
3W
W

PUSH AX
PUSH BX
PUSH CX
PUSH DX
PUSH SI
PUSH DI

,SAVE GENERAL
,REGISTERS

10 + W
10 + W
10+W
10+W
10+W
10+W

,GETPARAM1
:ADD PARAM2
,ADDPARAM3
,STORE IN LOCAL1

17+W
lS+W
1S+W
18+W

,RESTORE GENERAL
,REGISTERS

8+W
S+W
S+W
8+W
S+W
8+W
2
S+W
20+W

: PROCEDURE RETURN
POPDI
POPSI
POPDX
POPCX
POPBX
POPAX
MOVSRBP
POPBP
RET6

9 + 2W

MOVEW -(SP),PARAM3

:SAVE BP
10 + W
:INITIALIZE BP
2
,SETUP LOCAL STORAGE

MOV AX,(BP+S)
ADD AX,(BP+6)
ADC AX,(BP+4)
MOV (BP-2),AX

'" of Clock Cycles

,Push PARAM2

PUSH BP
MOV BRSP
SUBSR6

, PROCEDURE BODY

3W
W

35 + lOW
,Restore SP to Point to
RR12
7 + 2W
,Restore RR12
12 + 3W
10+ W

MOVEW -(SP),PARAM2

,RESTORESP
:RESTOREBP

Total number of clock cycles = 310 + 35W

,Push PARAM3
17

10 + W
22 +W
22 +W
19+W

:Restore RO-7

,DO=PARAMl

,PUSH PARAMl

, PROCEDURE ENTRY

,GetPARAMl

MOVEW -(SPJ,DO

'" of Clock Cycles
PUSH AX
PUSH PARAM2
PUSH PARAM3
CALL PROC1

Total clocks (Short segmentation)' 243 + 60W
Total clocks (Long segmentation) 247 + 62W

68000

:Restore A3-0,D7-4
44+ 11W
,Restore A6 12 + 3W
16 + 4W

iAPX86/10

15 + 3W
,Remove PARAMl-3
from stack 4 +
W
,Save RR12 12 + 3W
,Initialize RR12 5 +
W
,Setup Local Storage
7 + 2W
,Save RO-7 35 + lOW

14+
,Add PARAM2
14 +
4+
,Add PARAM3
14 +
4+
,Store In LOCAL 1
14 +

,Get PARAMl

Total clocks 250 + 5SW

CALR PROCl
INC R15,6

20+ 4W
:Remove PARAMl-3
from the Stack
4+ W
:A6=Framepomter
lS+ 4W
,Save A3-0,D7-4 on
Stack
4S + lOW

12 + 3W
:Add PARAM2
12 + 3W
:Add PARAM3
12 + 3W
,Store In LOCAL 1
9 + 3W

ADDW DO,A6( +S)

Total clocks' 205 + 55W

PROCl

'" of Clock Cycles

BSRSUB
ADDQSR#6

:Save Registers RO-7
25 + lOW

4-19

SPECIAL REPORT 01 FUTURE DIRECTIOI II SYSTEMS DESIGI

&..:===;;;;...,

MICROPROCESsolis/MICROCOMPUTERS

OPERATING SYSTEM
SUPPORTTHE ZBDDD WAY

All processor architectures are not created equal when it
comes to providing designers with the tools they need for
effective system resource management

by Richard Mateosian

perating systems are responsible for allocation,
deallocation, and protection of processing and
storage elements, external interfaces, programs,
and program status. They manage communication and
sharing, and define, facilitate, and enforce protocols,
conventions, and policy. Several kinds of architectural
support facilitate the operating system's task in a wide
range of applications: restriction of central processing
unit and memory use, memory mapping, sharing of programs and data, program relocation, stacks, context
switching, input/output system and interrupts,
distributed control, and support for conventions.
Operating system support is an important feature of
ZI!OOO* architecture. Special consideration was given to
that function during design of the Z8000 central processing unit (CPu), the Z-BUS· component interconnect, and
their support chips. In this discussion, "operating
system" will comprise the portion of the computer
application-both hardware and software-that is
devoted to managing hardware and software resources.
Richard Mateosian, z8000specialist at Zilog, Inc, 1315
Dell Ave, Campbell, CA 95008, is the author of
Programming the Z8000 (Sybex 1980) and Inside BASIC
Games (Sybex 1981). Formerly employed in the
development of minicomputer based turnkey.systems,
he has a BS in mathematics from Rensselaer
Polytechnic Institute and a PhD from the University
of Cali/ornia at Berkeley.
Reprinted with permission of Computer DeSign, May 1982

Hg 1 Hardware block diagram of arcade game system.
Essential elements Include cPU, memory, Input and display
devices, and clock circuits.

To show how the Z8000 provides operating system
support, an application of the hardware and software
similar to that used in a popular arcade game will be
described. Fig 1 shows the game's hardware configuration; the system elements are pieces of hardware
including cPu, memory, realtime clock, input and
display units, and integrated circuits for interface to the
CPu. Arrows represent electrical connections through
which data and control signals are passed among the
elements. Configuration of the hardware elements
alone, however, provides little insight into the game's
operation.
In the game's software architecture (Fig 2), system
elemenM are pieces of software "in action" on the data
defining the state of play at any time. Connecting
*Z8000 and Z-BUS are registered trademarks of Zilog, Inc

4-21

Restriction of CPU ICC...
The operating system must allocate
the CPU to a process while protecr---.....I ROCKET II
ting itself and other processes. In
I
other words, the operating system
I
must be able to turn the CPU over to
a process that win not perform
potentially destructive actions. To
this end, the Z8000 incorporates a
system/normal (SIN) bit in its flag/
control word (FeW) register, which
corresponds to the program status
word (psw) in other machines. (See
Fig 4.) The SIN bit determines
whether the CPU executes in system
or normal mode. In normal mode,
the portion of the FCW containing
SIN is inaccessible; the only way to
enter system mode is through execution of a system call (sc) instruction.
The refresh and program status
area pointer (PSAP) control registers
and the system mode stack register
are all inaccessible from normal
SCREEN DISPlAY
mode. The normal mode stack
register is accessible from system
mode under the alias normal stack
pointer (NSP), so that normal mode
PIa:Z Software bloek dl.anus 01 arcade I-e .ppllc.tion. Ellentlal elements are programs can pass arguments to
processes, or tasks, th.t provide lor IRpblcs aeneratlon, borlzontal and vertleal
system mode programs on the norsynchronlz.tion, .nd realtime _rekeeplnl.
mal mode stack. When the SIN bit is
arrows represent the paths and directions of inter- in the normal state, privileged instructions-ie, 110,
process communications (messages). The software con- interrupt return, nonmemory synchronization, control
figuration gives a good idea of how the game works. register manipulation, and halt-cannot be executed;
Fig 3 lists system elements supporting the hardware and operating system tasks are executed in the system mode.
Another protective feature is associated with the
software function outlined in Fig 1 and Fig 2. These
software components allow manipulation of hardware SIN- bit. There are two copies of the implied stack
and applicationuoftware, and represent system services register, one for interrupt and one for subroutine
returns. One is used when the CPU is executing in system
that all operating systems must supply.
mode, the other when it is in normal mode. Programs
executing in normal mode have no access to the system
mode stack register.
'Passing between system and normal modes requires a
PROCESS MANAGER
EVENT QUEUEI
MEMORY All.IltITDR
SEMAPHORE MANAGER
• CREATE/DESTROY
change to the FCW, which is accomplished through a
• All.IltITE/RELEASE
• SUSPEND/RESUME
• CREATEIDESTROY
privileged instruction or automatically in response to an
• QUEUE/DEQUEUE
• LOCK/UNLOCK
• WAIT/TEST/SIGNAL
interrupt or trap. Privileged instructions are load from
• SCHEDIJLE
control register (LDCTL), interrupt return (IRET), and
load program status (LOPS). A system call trap, which is
CLOCK MANAGER
MESSAGE EXCHANGE
a I-word instruction with eight programmable bits,
MESSAGE HANDLER
MAILBOX
MANAGER
• SET/READ CLOCK
• CREATE/DESTROY
allows a normal mode program to call one of 256 system
• INTERVALIFIXED• CREATE/DESTROY
• SEND/RECEIVE
mode programs.
• TIME AlARMS
• PREPARE/READ
• HARDWARE INTERFICE
• REPLY
The arcade game illustrates how system and normal
modes can be used. AU of the application software processes seen in Fig 2 can run in normal mode, while the
INTERRUPT/TRAP
UTILITY ItDIIT1NES
MEMORY MANAGEMENT
operating system elements in Fig 3 can run in system
HANDLER
CALLING
• MAPPING
mode. Calls to the operating system elements from the
• CONTEXT SWITCH
CONVENTIONS
• AtCESS RESTRICTIOII
applications software processes are made using the 156
• DISPATCH
• RELOCATION
• SHARING
system calls. For example, the defender guns process
• VIRTUAL MEMORY
can execute the instruction SC #Createprocess in order to
rue a rocket. The constant, createprocess, is a number
from 0 to 155 encoding one of the system functionsnamely, the one that creates processes. Programs and
na3 Underlylnl operatinl system elements reqnlred by
data that constitute the initial state of the new process
arcade aame .ppilcation. All elements support software
can be passed to the process creation program in
lunctlons. Hardware support II provided by Interrupt/trap
handler, c\oc:k man...., and utilly eiemnts.
registers or on a stack.
r--------,

4-22

INACCESSIBLE IN

NORMAL MODE

FlAGS

FLAG CONTROL WORD

{ I , SYSIEM MODE
o = NORMAL MODE

I-lir-

REFRESH REGISTER

I REfR£SH

I m·1
RO 10

---P-SA-PO-'N-I£-'------.IPSAP

[==~NO~RM~'~Ls~m~'~R~EGI§SI~ER==~I~·~dS~"kE~.~
Os. REGISIER NORM'L ~
~.
MODE

MODE

STACK REGISTER
'------INACCESSIBLE IN NORM'L " 0 0 £ - - - - - , - - , - - - - - - '

168115

,--_:.;.7f-;:;=I=N;;:UM;::.BE:::R~IN:::OE:..X-11---(CAUSES

S~Rl~S~~U~~~~~M MODE)

{1:

2~S

ENCODES UP TO
256 SYSTEM
PROGRAMS

• OR AD TO AI4 AND RIS IN NONSEGMENTEO OPERATION

Fig 4 Z8000 system/normal operation. SIN bit of
Dag/control word determines execution mode, system or
normal, of CPU.

Memory management
Existence of a user mode and privileged instructions
does not solve the entire protection problem; the other
half of the solution involves restriction of memory use.
Most CPU designs call for a comprehensive memory
management facility to unify the approach to restriction
of memory use, memory mapping, program relocation,
sharing of programs and data, and stack use.
The Z8000 uses an external memory management unit
(MMU) that is integrated with a segmented addressing
scheme in the CPU. The MMU translates addresses,
checks attributes, and interrupts the CPU if an invalid
access occurs. Sets of attributes are checked against access rights implicitly or explicitly associated with each
process. Then, for example, if a program in user mode
attempts to access a memory address whose attributes
do not match the program's access rights, the CPU will
trap to a system routine designed to deal with such invalid accesses. CPU addressing scheme and the MMU
determine which sets of attributes can be associated with
portions of the memory address range. Typically, attributes are associated with a segment in a machine that
uses 2-dimensional, or segmented, addressing. In a
machine with linear addressing, attributes are usually
associated with fixed size blocks of addresses called
pages.
The arcade game probably does not need memory
mapping or virtual memory, since the total memory
space of such an application is small. Access restriction,
relocation, and sharing of programs and data can be
useful in any application, however. On the other hand,
UNIX and UNiX-like operating systems, in which there
are many small processes, are well suited to the Z8000'S
segmented addressing and memory management.
Use of stacks
Stacks are important tools for meeting the operating
system's responsibilities. A stack is a last in, first out
memory associated with two operations: pushing (adding

an item) and popping (removing an item). Stacks are
explicitly or implicitly used by the operating system to
allocate memory in a flexible way, which, in connection
with based addressing, allows programs needing nonregister storage to be reentrant and position independent. A special case of this is storage of return addresses
for subroutine calls and machine state for interrupt processing. In the arcade game, the use of stacks to allow
reentry of programs plays an important role. Rocket
processes, for example, can all share a common processing routine while each uses a different set of data.
Z8000 architecture calls for the placement of stacks as
arrays in memory with an address register marking the
top of the stack and providing, through based addressing, access to items at locations relative to the top of the
stack. The stack register is a dedicated (special purpose)
register in some architectures. In the Z8000, any of the
registers Rl to Rl5 can be used as a stack register,
although the architecture determines which stack
register is to be used for saving returns from a
subroutine or the machine state on interrupts.
The implementation of stacks as arrays in memory
and the use of general purpose address registers for
stack registers make provision for overflow and
underflow protection difficult. The Z8000 provides stack
limit protection through use of the attribute specification associated with memory protection. Other architectural features are desirable for the support of stacks,
including the ability to designate one or more stacks for
program use, single- and multiple-argument push and
pop instructions, and automatic warning (traps) of
impending stack overflow or underflow.
Context switching
One difficulty that arises when several processes run
concurrently is the overhead associated with context
switching. The context of a process is that portion of its
state which occupies shared resources. For example,
since all processes must share the program counter (PC),
each process's PC value is part of its context. The Z8000
has a single set of general purpose registers, control
registers, CPU status registers, and so forth. Thus, when
the same processing element (CPU) is allocated to more
than one process, the process contexts must include the
contents of any register that is used. Context switching
saves the context of one process and recalls the stored
context of another process.
Automatic context switching is provided for interrupts and traps. When an interrupt occurs, the current
CPU status (FCW and pc) is saved on the system mode
stack, along with a "reason" read from the address data
lines ADl5 to ADO during the interrupt acknowledge
cycle. Then new values for the FCW and PC are taken
from the program status area (PSA). The IRET instruction restores PC and FCW to the preinterrupt state and
discards the reason, leaving the stack as it was before
the interrupt. Architectural features that expedite context switching include automatic saving of CPU state on
interrupts, single-instruction block register saving and
restoring, and access to all necessary control registers.
The Z8000 interrupt and trap handling facility provides an automatic, rapid context switch from the executing program to the interrupt processing routine using
interrupt vectors stored in a memory table (the PSA).
The Few. PC values, and a reason are saved on the

4-23

system mode stack, and new FCW and PC values are set
from the PSA entry (vector) corresponding to the interrupt type. The IRET instruction restores the CPU to the
preinterrupt state, while at the same time removing the
saved information from the stack.
Context switching involving general purpose registers
is facilitated in the architecture by block register saving
and restoring instructions. These can be used to
simulate pushing or popping a block of registers to or
from any stack. For example, the eight registers ROto R7
can be saved on the stack controlled by register RR14 by
executing

The PSA block of memory stores interrupt vectors (ie,
the new CPU status) for each type of interrupt and trap.
In addition to separate lines for nonvectored and vectored interrupts, as well as a nonmaskable interrupt for
situations that cannot wait, there is a table of PC values
to be indexed by an 8-bit vector placed on the AD bus by
the interrupting device. The block of memory used for
the PSA is not fixed, as it is in some cPus; it can be
anywhere in memory, and a pointer to it (the PSAP
register) can be set using the privileged LDCTL instruction.
Conflict resolution is achieved through a simple
scheme. The three levels of interrupt-nonmaskable,
DEC RU •• 16
!Make room on stack!
nonvccion:d, and vcc,ored-are assigned ,hree ieveis oi
LDM @RRI4.RO./IS
ISave the registers!
priority by the CPU. Using the privileged disable/enable
These two instructions require 39 clock cycles of exe- interrupt (DIIEI) instruction, the vectored and nonvectored interrupt lines can be masked so that interrupts
cution time, or less than 4 p.s at 10 MHz.
wait until the unmasking of the associated line. When
interrupts arrive simultaneously on more than one line,
Stacks are an important tool for
priority determines which will be processed first. The
processing routine for one interrupt type can be intermeeting the operating system 's
rupted by the routine for another if the corresponding
responsibilities.
line has not been masked. Whether other lines are to be
masked or not can be determined automatically by
In some cases, the values of control registers are specifying the appropriate mask bit in the feW portion
essential to the context of a process; the normal mode of the PSA entry. Otherwise, the determination can be
stack register and the flags register, which contains the made by the program, which can bracket interrupt senbits that define condition codes such as "less than or sitive code between DI and EI instructions.
equal to," are obvious examples. A load control register
A priority scheme is daisy chained through devices atinstruction allows the transfer of any of these registers tached to the CPU on the same interrupt line. In this way
to or from a general purpose register, permitting them devices closer to the CPU can interrupt the processing of
to be saved and restored.
more remote device interrupts unless the given line is
masked during all or part of the processing. This
110 system and interrupts
approach allows any priority resolution scheme to be
Operating system responsibilities in the 1/0 system and implemented externally.
interrupts vary greatly with the type of application. ArBlock 1/0 instructions and direct memory access are
chitecture of a general purpose CPU must provide the important and straightforward performance improveflexibility necessary to accommodate the 1/0 re- ment features. Block 1/0 instructions require careful
quirements of a wide range of applications.
implementation; they must use general purpose registers
One of the operating system's most difficult tasks is continuously to save their current state so that they can
control of access to 1/0 resources. Unlike memory, be interrupted. Direct memory access functions require
which can be divided into large, relatively homogeneous the development of bus control protocols and a means
blocks, the elements of the 1/0 space require special pur- of protecting partially loaded or saved memory blocks
pose management, protection, and access techniques. In from access by concurrently executing programs. A key
addition, device timing requirements and externally set aspect of the Z8000 1/0 system is the protection privileged
policies for conflict resolution make hardware support instructions provide, allowing an operating system to
of 110 mechanisms mandatory.
manage the 1/0 interfaces without interference from
Architectural features that support the 1/0 system and normal mode programs.
interrupts are a vectored interrupt scheme; specification
under program control of the CPU state to be established Distributed control
for each type of interrupt; and a rapid, automatic con- When processes to which separate processing units may
text switching mechanism in response to interrupts. have been allocated share a common memory, guarded
Also desirable are a means of defining conflict resolu- commands and semaphores are used. Basic architectural
tion policies and interruptibility of interrupt processing; support for these techniques is atomic test and set
a coherently designed family of components, com- (TSET), a CPU instruction that tests a memory location
patible interconnection bus, and established set of bus for the value "available" and simultaneously sets the
protocols to allow future family growth; block 110 value to "not available." "Atomic" refers to the fact
instructions and direct memory access; and restricted that there can be no other access to the given memory
location between the test and set portions of the instrucaccess to 1/0 facilities.
A vectored interrupt scheme allows the CPU state to tion. This prevents two concurrently running processes
be switched immediately to an appropriate processing from finding the location set to "available"
routine without the need for software to ascertain the simultaneously.
Architecture provides synchronizing procedures, both
interrupt type and call the appropriate routine. This is
done on the basis of either the port of connection or the for processes that share memory and for those that do
contents of a vector supplied by the interrupting device. not. In the case of shared memory. the TSET instruction

•

4-24

provides the basis for synchronization. In the case of
nonmemory synchronization, the Z-BUS specification
includes a set of lines and a protocol for resolving
simultaneous requests for shared resources while the
CPU provides instructions to support the bus connection
and protocol.

Support for conventions

In the design of a cpu, consideration must be given to
whether architecture should support all conventions
equally or encourage specific conventions through
special features. For instance, should a CPU be designed
with general support for high level languages, or should
it be designed to optimize Pascal at the expense of
FORTRAN programming efficiency? Should it provide
special features that make a subroutine argument passing convention using the stack especially efficient at the
expense of the efficiency of other argument passing conventions? zsooo design supports many conventions,
including a segmented addressing scheme, message passing for interprocess communication, component and
backplane bus protocols, and interrupt protocols for all
components.
A message is a set of characters (or words) emitted'by
one process and received, asynchronously, by another.
The processes do not need to know whether they have
been allocated the same or different processing
elements. Message passing suPPort includes block 1/0
instructions in the ZSooo cpu; asynchronous interprocessor connection in the Z-F10 (first in, first out) buffer chip; acceptance of commands from and delivery of
messages to the master CPU in designated message

registers by the universal peripheral controller (Z-UPC);
and '8llowance for high speed direct access to memory
from external devices (eg, a Z-FIO chip) through the
direct memory access chip.

Summary
Several kinds of architectural support are available to
system designers for meeting the requirements of the
modern operating system. Restriction of access to CPU
facilities, restriction of memory use, memory mapping,
sharing of programs and data, program relocation,
stacks, context switching, an 1/0 system and interrupts,
and distributed control and support for conventions are
all tools that 'can expedite effective system resource
management.

4-25

The performance of two addressing mechanisms
on three different microprocessors is examined. One of the
mechanisms-and one of the micros-provided superior performance.

A Perfornlance
COnlparison of Three
Contenlporary 16-bit
Microprocessors
Martin De Prycker*
University of Ghent

The choice of a new computer system is influenced
by considerations of various importance: compatibility
with the former system, software availability, cost,
maintenance, and system performance,! To a great extent, the system's performance depends on the central
processor's architecture. To study the performance of a
particular architecture, two methods are frequently used. One is that which was used in the CFA project,2.4 in
which three architectural parameters were defined and
compared for a set of machine language routines. The
other method consists of measuring the execution times
of assembly language benchmarks on different processors, as was done at Carnegie-Mellon5 and by Nelson
and Nagle. 6 Other contributions to architecture evaluation have been made by Shustek,7 who compared instruction execution times, and by Lunde,8 who
evaluated an ISP description of the processors. However, in order to obtain performance figures with any of
these methods, the actual processor, or a simulator, has
to be available.
The above-mentioned methods involve comparisons
of performance made at a low level; here, I compared
the performances of processors executing high-levellanguage programs. In block-structured high-level
languages, a major part of execution time is spent on
procedure and block entry/exit. (This has been noted by
Batson, Brundage, and Kearns,9 Tanenbaum,1O and
B1ake. ll ) When we also include the execution time of
variable addressing, it is clear that a larg(~ amount of the
*No\\ \\!th Bell Telephone Manufactunng Company. Antwerp, BelgIUm

execution time of block-structured high-level-language
programs is spent on procedure and block entry/exit
and variable addressing. The overall system performance is thus strongly influenced by the implementation
of the addressing mechanism. Therefore, several variable addressing mechanisms have been proposed, e.g.,
the display mechanism introduced by Dijkstra l2 and the
addressing mechanism presented by Tanenbaum. lo
In a recent paper,l) I analyzed a method for describing variable addressing implementation performance,
one that employs three independent parameter sets: a set
of program statistics determined by high-level-language
benchmarks, a set of architectural parameters based on
the processor architecture and the variable addressing
mechanism, and a set of technology-dependent parameters. The usefulness of this model lies in the independence of the three sets, and in the fact that the
processor is available in neither physical nor virtual (i.e.,
simulated) form. Hence, a complete performance analysis can be done analytically. In addition, in order to
evaluate the program statistics, the high-level-language
benchmarks can be run on any computer system.
Using this analytical model, I compared the addressing mechanisms implemented on a number of processors. I chose three comparable l6-bit micros-the Intel i8086,14 the Zilog Z8000,15 and the Motorola
MC68000,!6
In the next section I will explain the performance
model, as adapted to processors with an instruction
prefetch pipeline. 17 I describe a set of Algol and Pascal
benchmarks in the third section of this article and

0272-1732/83/0400-0026$01.00

Reprinted with permission of IEEE, April 1983

4-27

1983 IEEE

IEEE MICRO

Addressing mechanisms that implement
the block structure in high-level languages
In block·structured high·level languages, program
statements can be recursively grouped into com·
posite statements by means of two block delimiters
(begin·end and procedure·return). The recursive pro·
gram structure so generated can be represented by a
program tree (Figure 1). Each composite statement or
block can thus be given a number, its static leXical
level, which is the depth at which the block definition

the allocatlonlevaluation stack of the current environ·
ment For the sake of efficiency, the latter stack is 1m·
plemented contiguously.
It IS clear that, with the above Simple structure, ac·
cessing variables In parent static environments
necessitates tracing down the static pOinter chain,
pOSSibly to a depth Of several levels. In order to
lessen or avoid this run·time overhead, two mech·
anisms have been proposed, namely the display mech·
anism and Tanenbaum's proposal
The display mechanism. In order to provide fast ac·
Ge~::;

Hence, the lexical level of a block is always deter·
mined by the level of the (static) surrounding block: A
begin generates a lexical level which is one level
higher than the surrounding block; a corresponding
end returns the level of the block to the surrounding
level. A procedure call generates a lexical level which
is one higher than the level at which the procedure is
declared; a return puts the level back to the calling
level.
Variables may be accessed only when they are
declared within the same block or in static surround·
ing blocks, that is, when they reside at a lexical
parent level. With respect to the program tree, this
means that we can access all variables declared in
path nodes from the root to the actual active node.
This also means that scope rules are fully determined
by the static program structure known at compile
time. Within a block, each variable gets a sequence
number, and a lexical address is formed by the pair
(lexical level, sequence number). When a block ends
(by an end or return), all variables within that block
are no longer visible.
For the implementation of the scope rules of a
block·structured language, one needs two stacks: a
stack with static information (known at compile time),
and a stack with dynamic information (known only at
run time). Generally, one combines these stacks with
the evaluationlallocation stack on which the defined
variables and the temporary results are stored. The
three stacks are merged into one stack via a linked·
list technique. The stack of static and dynamic en·
vironments is implemented through marker words
that are linked. Among other information, each
marker contains two pointers: a static link, pointing
to its parent static environment, and a dynamic link,
pointing to the previous dynamic environment. The
top·most stack marker serves as the base address of
begin
real a b
begin
real c d
begin
real e f

o alO

blO 2)
1r------,
ci 1.1)

tu any iexicai ievei, Ihis scheme uses an extra

stack (display) Each display location contains a
pointer to the base of a visible environment. When a
variable at lexical level i is accessed, DISPLAY[i] is
used as base for level i. Thus, only one level of in·
direction is needed to access a variable at any static
level. The main benefit of the display mechanism is
that the address of any variable can be determined
very easily: address = DISPLAY!i] + sequence
number. Thus, the variable access time is indepen·
dent of the lexical level.
During the execution of statement Q in our exam·
pie, the display and data stack appear as shown in
Figure 2. Variables are accessible through the
display:AII variables in the three levels can be reached.
Tanenbaum's mechanism. In order to reduce the
overhead associated with display rebuilding-which
must be done after every procedure return-Tanen·
baum reduced the display to two pointers: a local
pointer LP and a global pointer GP. Local and global
variables can be reached through these pointers, and
intermediate variables must be accessed by tracing
the static pOinter chain through indirections. The ra·
tionale behind this approach is that the addressing of
variables at levels between the current level and the
global level (I.e., intermediate variables) is a relatively
rare event.
In our example the data stack during the execution
of statement Q will appear as shown in Figure 3.
Local (e,f) and global (a,b) variables can be addressed
directly; intermediate variables (C,d) can be reached
only by tracing the static pointer chain.
f

e
STATIC

STATIC

I DYNAMIC
d

I DYNAMIC
b

2
1

0
DISLAY

STACK

Figure 2. Display and stack during statement Q.

dl1 2)
f

2'ei'2i'1
f 12 2)

o
end
end
end

Figure 1. Lexical level and program tree.

STATIC

I DYNAMIC
d

I DYNAMIC
b

a
0

l~
1/

ILP
I GP

STACK

Figure 3. Pointers and stack during statement Q.

Apnl1983

4-28

ui,cu" their ,tatl,tical paramete". In the fourth ,ection
DIJk\tra', and Tanenbaum', addre"ing mechanhm" a,
implemented on the three mI<:roproce,so"" are compared. It I, ,hO\\n that Tanenbaum's mechanism always
performs better than DIJbtra', display mechani,m. In
the la;t section, I compare the relative performance of

which are accessed at an higher leXical level than
that at which they are declared.
• The total lexical-level difference of Intermediate
variables (d,,), that ", the ,um of the lexical-level
differences between declaration and access.
• The total leXICal-level difference between declaratIon and access of procedure, (\ a co;t/performance model.

The operations descrIbed here can be Viewed a, "generic
instructions," and each high-level-language program
can thus be WrItten as a sequence of these generic 1Ilstructions.
In Equation 2, T denotes an array of execution costs
T, of the generic instructions I, or

Variable addressing implementation model
. T, .
In an earlier work,tJ I expressed overall system performance as a function of three independent factors: the
high-level-language programs (benchmarks); the proce;;or architecture, I.e., the instruction set and register
organilation; and the technology. Here, I will examine
thi, model as it has been adapted to processor; with in;truction prefetch buffers of different lengths. t7
The overall system execution cost K, induced by procedure and block entry/exit and variable addressing, can
be written as a product of three independent arrays: one
composed of high-level-language program statistics 5,
one determined by the processor's architecture M, and
one influenced by the technology K T . That is,
K=KT

M·

sr,

One possible description of the execution cost K is the
execution time of the test program. Since my study involves only microprocessors, this execution tIme can be
expressed in terms of the number of clock cycles, because of the indivisibility of the clock cycle time I, (in
nanoseconds).

The number of clock cycles T, needed to execute each
generic instruction 1 depends on various parameters:
• The number of clock cycles Te, needed to execute
each generic instruction I. It is assumed that the
memory is fast enough (no wait states) and the instruction pipeline is always full.
• The number of extra clock cycles needed to perform a memory read (TMR,) and a memory write
(TMW,) and used by slower memory.
• The number of extra clock cycles in the delay TPC,.
This delay is caused by an empty pipeline resulting
from the execution of a sequence of instructions
when not enough memory is free.
• The number of clock cycles in the delay TPS,. This
delay is caused by a memory that is slower than
specified in the user's manual; hence, extra wait
states are introduced in order to have a full
pipeline.

(I)

where the superscript T denotes array transposition.
This model was obtained in a very straightforward
way: The execution cost of any high-level-language program can be determined as a weighted sum of the execution costs of the individual high-level-language instructions, with the frequency of these instructions in the test
program as the weight factor. Thus, we can write

K=T·sr.

(2)

The array 5 contains high-level-language program
statistics concerning variable addressing, and thus is 111dependent of either architecture or technology. The
statistics which make up the 5 array comprise the
following:
• The number of block entry/exits (nb).
• The number of procedure call/returns (n,,).
• The number of variables accessed in the program
(n,).

• The number of local variables accessed (nl). Local
variables are variables which are accessed at the
same level at which they are declared.
• The number of glObal variables accessed (n g ).
Global variables are variables which are declared at
the outermost level.
• The number of intermediate variables accessed (n,).
Intermediate variables are nonglobal variables

(3)

Tn)·

The total number of cycles T, can thus be written as a
sum of clock cycles:
T, = TC, + TMR, + TMW, + TPC, + TPS,.

(4)

The value of each of these parameters is determined by
the processor's architecture and technology. If we express each parameter as a product of a technologydependent part and an architecture-dependent part,
then Equation I will be satisfied, since the technological
parameters are independent of I:
TC,=C,' ~
TMR, = MR, . KMR
TMW, = MW, . K MW
TPC, = PC, . Kpc
TPS, = PS, . Kps

(5a)
(5b)
(5c)
(5d)
(5e)

IEEE MICRO

4-29

It we defIne a technological array KT and an architectural array M, a,

and

(C, MR, MW, PC, PS,)T,

(7)

then we can rewrite Equation 4:

T,=KT

(8a)

or
(8b)
If

M=(M J

•

••

.. Mn).

(9)

ApplYlllg Equation 8b to Equation 2 finally leads to the
basic model of Equation I.
For each of the five parameters of Equation 5, the
question of whether to separate them into technologydependent and architecture-dependent parts must be individually determined.
Execution lime in the optimal case. When the memory
is fast enough (no wait states) and the instruction
pipehne b full, the total number of clock cycles needed
for each generic instruction I is the sum of the number of
clock cycles C'j needed for the machine instructions j
which compose the generic instruction I. These numbers
CIj can be easily found in the microprocessor user's
manual.
Influence of slower memory on data memory operations. The read/write timing diagrams of the typical
user's manual give the minimum number of clock cycles
needed by the processor to execute a memory read or
wflte. We call these values m, and mw. Let us denote the
memory access time as x (in nanoseconds). The memory
IS fast enough ifx/t, :5m, for a data read-no wait states
have to be introduced. The number of clock cycles to be
Imerted depends on the memory speed, e.g., when
III, XWk. For instance, a relative performance of 3.5 can be prov.ided by a to-MHz MC68000
and a memory with access time of 540 nanoseconds
(>415 nanoseconds), if the best-case results are taken.
Since the memory is slower, the cost will be lower.
However, given a memory speed xbk , it cannot be
guaranteed that the performance will actually have the
value in mind, since the figures are obtained under bestcase models and the real performance value can thus be
smaller. The choice of memory speed depends on whether the application is time-sensitive. If it is, the worst-case
speed XWk must be used to ensure that the desired performance will be obtained. If the application is costsensitive rather than time-sensitive, the best-case speed
Xbk must be used, since it always results in a cheaper
configuration than if the worst-case speed is used. Of
course, this approach cannot ensure that the desired performance will be obtained.

= BEST
= WORST

25
B
W

II t I
III I

10+===t===~~==~t+~====

II I I

100

200

300

400

500

Figure 11. Relative performance of the three 16·bit micros as a func·
tion of the memory speed x.

We have analyzed the performance of addressing
mechanism implementations for block-structured highlevel languages. The performance measure defined here
can be written as a (scalar) product of three arrays, each
array depending on one parameter set. These three sets
are completely independent-that is, they comprise
technological, architectural, and program-statistical sel>.
IEEE MICRO

4-37

This model provided a bam for comparing, m three
contemporary 16-blt mlcroprocesso"" the ImplementatIOn of the traditional dl'play mechanism to the ImplementatIOn of the mechanism ploposed by Tanenbaum. A best/"or;t-case analysis overcame the lack of
Information about the microcode and its relatIOnship to
Inltruction prefetch behavIor.
The performance figures presented here were consIstent with one another and with tho,e derived in other
studie,. They showed that Tanenbaum', proposal provided a uniformly better performance than the display
mechanism. t ne ttgures atso tnCllcatea tne relative performance of the three microprocessors-·the Z8000 did
the best, the MC68000 the second-best, and the i8086
the wor;t. These results agreed well with earlier data.
The methods presented here also showed how to determine the influence of memory speed on performance,
and how the results could be used to obtain a cost/performance figure . •

Language.;;," 11:'£..£: Trans Compllfc/\, Vol. C-31. No 2,

Feb 1982,
14
15

D. Fenari, Computer Systems Performance Eva/ua/ton,
Prentice-Hall, Englewood Cliffs, NJ, 1978.

W. E. Burr and R. Gordon, "Selecting a Military Computer Architecture," Compuler, Vol. 10, No. 10, Oct.
1977, pp. 16-23.

S. H. Fuller and W. E. Burr, "Measurement and Evaluation of Alternative Computer Architectures," Computer,
Vol. 10, No. 10, Oct. 1977, pp. 24-35.

W. B. Dietz and L. Szewerenko, "Architectural EffiCiency Measures: An Overview of Three Studies," Computer,
Vol. 12, No.4, Apr. 1979, pp. 26-32.

R. D. Grappel and J. E. Hemenway, "A Tale of Four
Micros: Benchmarks Quantify Performance," EDN,
Apr. I, 1981, pp. 179-265.

V. P. Nelson and H. T. Nagle, "Digital Filtering Performance Comparison of 16-bit Microcomputer~," IEEE
MIcro, Vol. I, No. I, Feb. 1981, pp. 32-41.

L. J. Shustek, "Analysis and Performance of Computer
Instruction Sets," PhD thesis, Stanford University. Stan·
ford, CA, 1978.

A. Lunde, "Empirical Evaluation of Some Feature> of
Instruction Set Processor Architectures," Comrn. ACM,
Vol. 20, No.3, Mar. 1977, pp. 143-153.

A. P. Batson, R. E. Brundage, and J. P. Kearns, "Design Data for Algol 60 Machines," Proc. 3rd Ann. Symp.
Compuler Archlleclure, 1976, pp. 151-154.

10.

A. S. Tanenbaum, "Implications of Structured Program
ming for Machine Architecture," Comm. ACM, Vol. 21,
No.3, Mar. 1978, pp. 237-245.

II.

R. P. Blake, "Exploring a Stack Architecture," COli/piller, Vol. 10, No.5, May 1977, pp. 30-38.

12.

E. W. Dljkstra, "Recursive Programming," Numensche
Malh, Vol. 2, 1960, pp. 312-318.

13.

M. L. De Prycker, "A Performance Analysis of the Implementation of Addressmg Methods in Block-,tructured

,\tal/lta/, Intel Corp, San!.!

L8000 CPU Tcc/]fIlcal .Haflua/, li!og Corp, CUperll!1Cl,

CA,1980
16,

.\1C68000 j\lICl()/)I()Ce~'<;()! Usn's A/anual, 1'vloloro1a
Semiconductor Product'), Inc, PhOenl\, AZ, 1979

M L De Prycker, "Repre<.,enttng the Elfect... of In"truc!lon Pic/etch Il1 a Microprocc<;<.,or Pel formancc Model,"

10.

I I r rilgU/, nCWICI1-rdI.KctIU \...-1..1., '--UpU UIIO, "--!-\, I ';III.

19.

Pascal/(!! PDP-ll Undol RSX!f"lS, Tech. Report S-126
25, L.M. Enc"on Co., Stockholm, S"eden, 1979

20.

K. Jen"en and N WIrth, Pascal Uwr ,Wal/uo! and Reporf,
Spnngel Verlag, Berltn, 1976.

21.

A. V. Aha and J. D. Ullman, PllnClp/c, of Compiler
DeSign, Addison-Wesley, Readtng, MA, 1977

22.

M. L, De Prycker, "On the Development of a Mea'iurement System tor HIgh-Level Language Program
Statistics," fEEE Twns. COli/pI/len, Vol. C-31, No 9,
Sept. 1982, pp. 883-891

23.

W. Patstone, "16-bit Micro Benchmarks: An Update
With Explanations," EDN, Sepl 16,1981, pp. 169-203.

24.

Hunter and Ready, Inc., "Executive tn ROM FIls 8086,
68000," Eleclrolllcs, Jan. 27,1982, pp. 134-136.

25.

P. M. Hansen et aI., "A Performance EvaluatIOn of the
Intel iAPX 432," Compl/ler ArchlleCll/re News (ACM
Sigarch newsletter), Vol. 10, No.4, June 1982, pp. 17-26.

to appear ltl/EEE Tran.s COlllpulen
• • no

References
1.

155-163.

Clara, C A, 1979

Acknowledgment
The author wishes to thank Dr. J. Van Campenhout
for his many helpful comments and for his thorough
proofreading.

The 8086 Fal/Illl' (he! \

'T,

.."

'-'

'-'.

.,,~.

Martin De Prycker IS a systems engineer
with Bell Telephone Manufacturing Company, Antwerp, BelgIUm, where he 1<; involved tn long-range development A
member of the ACM and the IEEE, he
received the MS 111 electrical engineermg
in 1978 from the University of Ghent,
BelgIUm, and the BS and PhD in computer "cience from the same universi(v in
1979 and 1982.
.
De Prycker's addre" is Bell Telephone Manufacturlllg Company, EA5, Fr. Wellesplein 1, B2000 Antwerpen, Belgium.

April 1983

4-38

A paged-memory management chip brings virtual memory to two
16-bit CPUs. Additionally, a coordinated bus structure makes
possible distributed-processing or multitasking, multi-user systems.

16-bit ~Ps get a boost
from demand-paged MMU
Faced with applications that demand large programs and extensive data manipulation, microcomputer manufacturers are turning to virtual
memory management, an approach originally developed for minicomputers. A single chip uses
demand-paged virtual memory to expand the already large memory-addressing capabilities of two
new I6-bit microprocessors.
Running the software being developed for those
processors-the 8-Mbyte Z8003 and the 64-kbyte
Z8004-means using the latest techniques for effective memory management. The technique known as
demand-paged virtual memory, chosen for the
Z80I5 paged-memory management unit (PMMU),
keeps the most frequently used codes in fixedlength blocks in RAM, swapping them in and out of
disk storage to extend the range of addresses. Such
a scheme naturally leads to multitasking and multiuser systems, since the time spent accessing a disk
can be used for other tasks. With the Z80I5, for
example, the Z8003's 8-Mbyte logical address space
translates into a I6-Mbyte physical address space.
The Z80I5 has the same address translation and
access protection features as the
Z80I0 but is based on 2-kbyte pages
rather than the variable-length
segments used in the earlier chip.
Together, the Z80I5 and the Z8003
(or Z8004) bring multitasking and
multiuser capabilities to the microcomputer.
In addition, the Z80I5's access validation feature protects memory from
unauthorized or unintentional access. The memory management unit

also generates an Instruction Abort signal during
page faults and at the same time saves sufficient
status and information to restart or resume any
instruction after the fault is corrected.
One important application of virtual memory is
in disk-based multitasking systems. A system of
this type can be implemented easily with the Z8003
and the Z8015.
Virtual memory enables a system to execute programs that do not fit into its primary memory. In
order to accomplish this, a secondary storage
device-usually a disk-is required. When a disk
access is required, however, the program in
progress must he interrupted. This interruption can
cause large and unpredictable delays known as
paging overhead, which may become excessive because of the slow access time and transfer rates of
floppy disks. For a typical personal computer or a
small business computer, these delays might slow a
system sufficiently to make virtual memory management impractical.
Hard-disk systems, on the other hand, are faster;
therefore, the paging overhead will be shorter and

Richard Mateoaian,' Marketing Manager
Zilog Inc.
1315 Dell Ave.
Campbell, Calif. 95008
-Now with National Semiconductor Corp.

Reprinted with permission of Electronic DeSign, May 26, 1983
Copyright 1983 Hayden Publishing Co., Inc.

4-39

Computer System Design: MMU for 16-bit "Ps
therefore acceptable. When a CPU must access a
rigid disk fairly of ten-a condition called
thrashing-even the comparatively fast disk can
produce too much delay.
Fortunately, the paging overhead of a virtual
memory can be minimized with multitasking operating systems that allow one task to run while another waits for access to the disk. Such multitasking
operating systems can be single-user systems, like
MD/M n.,,,,,,, ... If.Lnoo.'I'O
V.I.
,U,&\o&.&\1& 10&,"",,'"

....... 0&., ....... ,

DUO ...

cessors are being employed.
One such feature is the Bus Lock Status signal
that accompanies a Test and Set instruction in the
Z8003 or the Z8004. That instruction prevents access
to a shared memory by another CPU or DMA controller. In that way, two CPUs, using a flag (semaphore) stored in shared memory, keep track of
which processor currently has access to a resource.
The Bus Lock Status lets other potential bus mas-

'O'''''''' ...........
H1.,.o
;v
'" TT
..........
u .... .n..

+o..-a
),"''''...... "''''n''' n ..nL.,,,,......,.n ;"" nl..".,.. ...
""' ...........u.vn " ..... M'' " C4f ... "'~v ...........'" .I..., AUUU."

~J"''''''''''''.L''',

Virtual memory and mulllproceelOr.

A distributed processing system-such as a localarea network or an intelligent terminal-places
computing power and data where they are used,
rather than at a central host computer. Supplying
each processor in such a system with its own semiconductor or magnetic memory would be prohibitively expensive. Virtual memory management,
however, permits resources to be shared among all
the devices in a system.
The entire Z8000 family, which uses extensively
programmable VLSI components, is geared to distributed processing strategies. Furthermore, a variety of features built into the Z-Bus-the interconnection protocol that all Z8000 family components are designed to use-reduces the chances of
bus conflicts and data collisions while multiple pro-

Phase

--------~- _______

>--<

registers ~

Phase

"''''''t.u,'''''I.I"u..

Most complex peripheral devices are governed by
microprocessor-based controllers, and it is natural
for a controller CPU and the main CPU to communicate through a shared memory. In such a configuration, semaphore locations can be used to manage
access to message buffers, with the Bus Lock Status
being used to generate these semaphores.

... - - - - - - - - - -.. Test

~------~

" " U,,",

Software and memory management

Addreu/~
~ Semadd"!!~
'._..
MM~

f."" l,. ........ ", ... ,U'....... A

The Test and Set instruction consists of two separate bus cycles: a memory read, followed by a memory write (Fig. la). When asserted, the Bus Lock status replaces Data Read during both cycles' (Fig. Ib).
Given the general picture of how the Bus. Lock
Status is used to implement semaphores, the question of what applications can benefit from the distributed processing approach still remains. One answer is peripheral controllers.

Semacon:°tare
'.
~--------~

s::r.::re

set ________..

Not available

X,..-------DaI--aW-ri-te-S-tot-u-.- - - - - - - } -

Data Read SlatU8

·----------Test---------....----------Set.------__ . .

Addreu/~
Stat~

Semaphore

add,...

regl'ters~

R/W-<

semaphore
contenta

>-<

Semaphore
addreaa

X
(b)

>}-

Bus Lock Statue
Data Read

Not available

Data Writ.

1. To 1Ih.....n, I'HOUree, multiple procllure mUlt '!rIt lilt • 1000tion In memory, cilled I
_Iphore, during I Tilt Ind Set Inltructlon (I). Acce.. then dependl on the _lph_'1
contente. In eddHlon, I BUI Lock Stltul IIgnel il I..ued (b). Thll Ilgnll kllpe other
potential bul m..t.... 'rom _ling the I'HOUree while It II being lilted b, the controller.

4-40

In addition to controlling access to shared resources, another aspect of virtual memory management is handling faults: CPU requests to those
memory locations which are not in the physical
memory space.
Every memory management scheme involves
translating logical addresses into physical addresses. Additionally, most schemes involve both access
checking-to prevent invalid accesses-and usage
recording to assist in implementing memory allocation algorithms.
For example, consider the flow of control in a
simple virtual memory system. During the execution of the main program, if the CPU issues an
address that does not correspond to a physical
memory, the memory management unit attempts a

logical-to-physical memory address translation. At
this point, the microprocessor's Wait input is
asserted and the memory management circuitry
performs the necessary actions, including all disk
accesses. Afterward, execution of the interrupted
instruction resumes.
There are, however, drawbacks to this approach.
First, the CPU is idle while the fault is processed
and must therefore be isolated from the bus if direct
memory access is used for memory management.
Second, the entire fault-processing action is carried
out by the memory management circuitry, without
help from the CPU.
In an alternative approach that is employed by
the Z8003 and Z8004, page faults are processed by
the CPU's ordinary interrupt-handling mechanism

EFault-prOdUClng Instruction
Main program

~~-~~-c=;.:-~-~
Automatic
saving of program
counter's contents,
flow control
word (FOW). and 16·blt
code from MMU
on stack

I
PC and FeW

set for fault
routine

_____ +_____

Fault Information
read from MMU

Saved PC contents and
FeW (as modified) restored
from stack;

16-bit MMU code

discarded from stack

Saved FeW and
PC contents modified
on stack if
necessary

I
I

..JI

L------I------ _-1

I
Fault-producing
address given
a block of
physical memory
(disk, write, and read,
as necessary)

I
I

I
I
I

Interrupt return
Instruction

I
I

L_____ I_____ JI
2. To use virtuel memory efficiently, a CPU should take part in page-fault processing. In
mOlt cases, however, it is much easier to aimply di.able the CPU and leave the job to a
memory management unit. In the 78000 family, the CPU and MMU share the burden by
running fault-proce.sing 80ftware (block B) with the CPU'. normal interrupt routine (blocks
A and C).

4-41

Computer System Design: MMU tor 16·bit "Ps
(Fig. 2), which generates an Instruction Abort signal. The signal terminates the instruction that has
produced the fault before the contents of any registers are changed. After the fault is corrected, the
instruction can simply be restarted.
Because certain instructions perform multiple
memory transfers, a fault may occur that requires
more than a simple restart. For this reason, the
Z8015 is designed to monitor the execution of instructions ann to provine accurate restart information to the fault-processing routine. Thus, the faultprocessing software restricts itself to correcting the
fault and resuming execution. Here again, a benefit
of multitasking is in switching tasks when a page
fault is being processed-allowing another task to
run while the necessary disk accesses are in the
process of being carried out.
MultiproceslOr systems

Not all multiprocessor or multitasking systems
are as complex as the one just described, nOr are
they all shared-resource designs. Some coprocessor
systems, for example, have been designed to run Z80
software in systems based on microprocessors like a
6502,8088,68000, or Z8000.

Taking that approach one step further is a system
that uses a Z8003 with a Z80 and Z8015, plus dualported memory, to run under both Unix and CP/M
(Fig. 3).
Since no memory management is used for the ZSO,
only 64 kbytes of the memory must be dual-ported.
The remainder needs to be accessible only to the
CPU. However, with memory management there is
no difficulty in extending the design to accommodate a multitaRking verRion of C!P/M. Tn t.hat. ('aRP,
as much memory as is needed in a particular application must be dual-ported.
The system forms the nucleus of a high-end personal computer that runs Unix on the Z8003 and
CP/M on the Z80. In operation, a CP/M task is initiated through Unix, and a Unix task accepts an I/O
request from the CP/M program running on the
microprocessor, carries it out, and signals its completion to the system.
The dual-ported memory is a shared resource and
is controlled using semaphore locations in memory.
As described above, a Bus Lock Status issued during
the read cycle of the Z8003 Test and Set instructions
protects semaphore locations from access by the
associated Z80 microprocessor.

Counter-timer
and
parallel 110 unit

Disk
controller

Serial
communications
controller

3. Uling multlprocaelor tnturae and a lharsd 84-kbyte dual-ported memory, a Z8OO3 and a
Z80 can form the heart of a CP/M- and Unix-baaed microcomputer. Such a 1,ltem would
u.. a Share aemaphore and a Maaaege lIeg in a sharsd-memory to carry out a handlhake.

4-42

computer System Design: MMU for 16-bit "Ps
The 64-kbytes of dual-ported memory can run on
the Z8003 under Unix. It is controlled by the Share
semaphore-a mechanism that can be easily modified to cover multiple blocks of dual-ported memory. The Share semaphore is used only for Z8003
tasks to control access to the CPIM facility (Fig. 4).
In addition, a Start semaphore initiates 1/0 requests, utility calls, and the Done signal that are
passed from the ZSO to the Z8003 by means of a
message buffer register.
A Message flag is used for handshaking with this
buffer. That flag is set by the Z80, which then waits
for it to be cleared before proceeding. The Z8003
clears Message before setting the Start semaphore.
Thereafter, its principal loop consists of waiting for
message to be set, performing the requested task,

and clearing Message.
The Start semaphore indicates that the Z80 is
executing programs in the shared memory and is set
by the Z80 only during its power-on initialization.
Following that, the Z80 microprocessor only clears
the Start flag. Subsequent setting is done by the
Z8003 whenever a Z80 program has been loaded into
the dual-ported memory of the system and is ready
to run the program's instructions. After executing
the program, the ZSO clears the Start flag.D

How useful?

Circle

553
554
555

Immediate design application
Within the next year
Not applicable

ExIt 10
CP/M

I/O request

Done

utility call

Perform

• Cie.jr Message

requested

ftag
• Clear Share

task

semaphore

(a)

(b)

4. T••k. running on .h. Z8OO3 (.l.nd.he Z80 (bl communlc••••nd synchronize .helr
.c.lvl.....hrough.he m..At. buffer, .h. m....g. fIeg, .nd .h. Slert eem.phor•. The
Sh.re ..m.phore I. used only In the Z8OO3 .llow i•• teak. sh.re .cce.. .h. Z80

.nd .he du.l-ported memory.

4-43

As memory spaces for microcomputers grow, linear addressing gets
cumbersome and error-prone. Segmented addressing solves these
problems efficiently, while anticipating 32-bitaddresses.

Segmentation advances
~C memory addressing
As a memory model, linear addressing has always
presented problems for microcomputers. In addition
to invalid accesses, traditional micros have faced
four major difficulties: accommodating objects
whose sizes vary (e.g., stacks or lists); creating and
deleting objects dynamically, causing memory
fragmentation; relocating objects after the loader
has established linkages among them; and sharing
objects among otherwise independent processes. All
five major problems-which have increased exponentially as systems have grown-can be avoided
by using the abstract addressing model provided by
segmentation and implemented in the Z8000 CPU
and its memory-management unit.
Segmentation organizes the address space into a
collection of independent objects corresponding to
the largely separate but interrelated objects found
in a typical programming situation. This method
works for addressing somewhat like a high-level
language: The programmer need not worry about the
computer memory's physical implementation. Linear addressing, on the other hand, corresponds to
a machine language: The model used for the
computer's memory is very close to its actual hardware implementation. Examining some memoryaddressing tasks that confront programmers will
illustrate the trouble with this "machine language"
strategy.
In general, a programmer deals with a variety of
objects and their interactions. Depending on how
"fine-grained" the picture is to be, a programmer
could be said to deal with just two objects, the
program and the data. Or, at the other end of the
scale, he could be said to deal with a multitude of
objects-listing separately each instruction and
datum. Between these extremes lies the typical
programming situation dealing with largely separate

PROGRAM

ARRAY

PROGRAM

ARRAY

STACK

L __

..IN.l

1. A traditional relocating loader putl the ObJects that make
up a program .equentlally Into memory apace.

Richard Mateollan, Senior Microprocessor Specialist
Zilog Components Div.
10460 Bubb Rd., Cupertino, CA 95014

Reprinted with permission of Electronic DeSign, February 19, 1981
Copyright 1981 Hayden Publishing Co., Inc.

STACK

4-45

Segmentation
but interrelated objects. A chess-playing program,
for example, might include:
• Chessboard display program
• Representation of the current position
• Program to generate legal moves
• Routine to evaluate moves
• File of previously evaluated positions
• Handling routines for the previous-position file
• Program to study published games.
ThiR Roftwlll'P. might.

!,11n

nnrlp.l' thp I'ontl'ol of lln

operating system, which can also be divided into
objects:
• Task scheduler
• Memory allocator
• Secondary-storage interface routines
• Terminal interaction routines
• Process status table
• System stack
• User-process status tables.
Usually, portions of the computer's memory are
allocated to each of these objects. A relocating loader
might pack the programs together end to end and
then allocate fixed areas for data, also end to end,
in memory not occupied by the programs (Fig. 1).
In the earliest computers, each object received an
address directly related to-in fact, usually the same
as-the actual memory address at which it was
stored. These addresses were all numbers in the
range 0 to N -1, where N was the total number of
memory locations available. Every program that
wanted to access any of these objects had to use these
addresses. As a result, one problem that has always
affected linear addressing is invalid accesses.
This hassle occurs even in the smallest systems
and on the smallest computer-a program erroneously uses an address as if it belonged to a
certain object. For example, if an array is 1024 bytes
long and a program erroneously refers to its 1025th
byte, then the reference will actually be to the first
byte of the object stored in memory immediately
following the 1024-byte array. If the erroneous access
is a store operation, then the object following the
array will have been damaged (Fig. 2).
Problems stack up

Trouble also crops up with the use of stacks. A
common approach in a single-user system is to
allocate the lowest memory values to programs and
data and the highest ones to a stack, since the push
and pop instructions on most computers are designed
to make stacks grow "backwards" in memory. The
first item placed on the stack is at the highestnumbered address, and the "top" of the stack is at
the lowest-numbered address. If program changes
cause the program and data areas to expand, less
and less remains for the stack. Sooner or later, a

4-46

1024byte
array

Program

ijn<; ~

STA array X

2. The program executes a store-Into-array, using
an out-of-range Index. The result Is an Invalid
access that wipes out part of the program.

Lowest a~dress

Program
and
data

Next element pushed

goes here

I
I
Free
I space
I
for
program
I or stack I
I growth I
I
I
I- - - - -l

----..,

Top

r----

Stack pOinter

Stack

Highest address

3. Program and stack u8uailY grow Into memory space from
opposite ends. Eventually, they may collide.

stack push will cause the stack to overflow its allotted
area and destroy programs or data (Fig. 3).
Such problems are often attacked by creating an
"envelope" around the accesses in question. For
example, instead of using the computer's indexing
capability to access arrays directly, the prOgram
might call a subroutine that accepts the index and
the identity of the array as arguments and returns
a validated memory address for fetching or storing.
(The routine might handle the actual fetching or
storing as well.) In either case, the routine would
validate an access by using the array identity as a
key to a set of array attributes, including the array's
length and location in memory.

ing system.
An envelope around push and pop instructions
could detect invalid accesses before they occurred,
and provide an alarm-but this is not a solution.
Figure 3 shows only one stack. that doesn't run out
of memory until the entire memory is exhausted.
However, if many stacks must be managed, it might
be best to assign a small amount of memory to each
stack and then expand those that were about to
overflow (Fig. 4). If all accesses to stacks go through
the envelopes that surround the push and pop instruction, the stack can be "continued" elsewhere in
memory. Through this operation, the gap in the
actual memory addresses between the last location
of the original stack and the first location of the
extension will be completely concealed from the
program using the stack.
Unfortunately, the way in which stacks are ordinarily used is not well suited to_ this approach.
Frequently, a program is allocated aolock of stack
space, which it then accesses via "based" addressing
-Le., the actual memory address of the first location
of a block of stack space is kept in a register, and
accesses into the block are made by adding an "index"
(obtained, for example, from an instruction) to the
"base" address in the register. This common practice
is incompatible with the existence of gaps in the set
of addresses assigned to the atack.
The traditional solution is to allocate a larger
contiguous block of memory to the enlarged stack
-either by moving the stack to another part of
memory or by moving something else out of its way
so that it can be expanded where it is. This approach

In the case of a stack, a similar envelope would
be placed around pushes and pops. Rather than use
the machine's push and pop instructions, the program would call subroutines for these operations,
generating a large software overhead.
Handling Invalid accesses

Another type of invalid access occurs when several
programs or sets of data-not necessarily related to
one another-share memory locations. As a result,
a program's accesses might be restricted either to
its own subroutines and data, or to portions of
memory containing data or subroutines that it
shares with another program and to which it is only
allowed certain kinds/of access (such as "read only"
or "execute only").
All the discussed software envelopes can be extended to shared-data access, but it is difficult to
place such envelopes around program accesses.
Furthermore, these envelopes are voluntary; that is,
a programmer who wishes to avoid them can usually
obtain the information needed to make the accesses
directly. To guard against such conflicts, hardware
solutions such as limit registers have been introduced.
For example, the operating system might set
registers defining the limits of a program ready to
run at locations 10000 through 19999. In that case,
the program is free to make references of any sort,
so long as the address used lies within the given
range. An attempt to call a subroutine at any higher
address, say at location 20000 would result in a
"trap," and control would be returned to the operat-

Stack
segment

Program

pus~7~op

PUSH/POP
envelope

-.,..J

Basea-addresslng
references to

L _ -14- this location are
.

actually meant

for here

Stack
segment
1
Program

uSing
based
addressmg

4. A PUSHIPOP envelope conceall the allocation of the Itack Into different legments. Lack of
luch an envelope for b..ed addre..lng Invalidate. thll Icheme.

4-47

Segmentallon
has two inherent problems. For one thing, moving
objects around in memory and keeping the unused
memory all in one place increase the processing
overhead. For another, all those base addresses for
blocks of stack space that the program has in
registers or in storage must be exchanged. Save for
the most elementary cases, this obstacle is almOlit
insurmountable.
When no memory-management facility is avail_L1_ L'L _ _ _ _ _ _ _ _ _ _ .1_ 1.1_.1",.-..3 "'_ .'L _ _ L_"': ___1__ _

au,,,,

WI"

lJ'-ugI AJ1UUCI

ID lll1111A1'U LoU "IU::;

D..,.""......::;'''''''''-

tion provided by a relocating loader.
Accommodating objects whose sizes vary leads to
yet another problem: creating and deleting objects
dynamically. It arises even in the simplest singleuser systems-for example, "initialization" code
might be abandoned after its first execution and the
space given to a large data array. Here, too, the
difficulties mount rapidly as the system becomes
more complex. Because of the difficulty in relocating
addresses, objects that should be moved to keep
unused memory together often are not. The unused

let
objec1

2nd
object
a.!!!.n~

3rd
object

4th
oblOC1
abandoned

r:l

L;:J

No~

......
5th
objOC1

6th
objOC1

5. Memory get8frlgmlntecl whln lome orlglnll
obJectel" lbandoned. Although the,. Ire
enough mlmory loclUonlleftforobJecI 8, not
Inough I,. contiguoul to 1CC0mmodltllhit
object.

memory soon becomes fragmented, which makes it
increasingly difficult to find contiguous blocks big
enough to accommodate newly created or expanded
objects-even when the total amount of unused
memory suffices (Fig. 5).
Up to now, the only "solution" has been to leave
management of the assigned memory to the user
program. The user is provided with tools like chaining commands and overlay structures in some systems but, by and iarge, the creation ud deletion of
objects are simply treated as part of the algorithm
implemented by the program.
R.loesUon 18 no .s., tuk
After the loader has established links among
program parts, it becomes almost impossible to move
any of these parts. A hardware solution has been
provided at several levels.
Dynamic relocation, which occurs after initial
program loading, requires a mechanism that allows
actual addresses to be determined at run time. One
solution is provided by various kinds of based addressing, usually in the form of relative addressing:
Calls, jumps, and loads of program constants are
specified by an offset that is added to the actual
program-eounter value. Data references, too, are
made via offsets that are to be added to a stack
pointer or other address register. Relocation by based
addressing is called "user-eontrolled" relocation,
since the running program controls setting of the
stack pointer or of another address register.
From the standpoint of reliability, "system-eontrolled" relocation is usually a better solution. Its
simplest form, memory mapping, is a translation
mechanism that converts the addresses used by the
running program (logical addresses) into the actual
memory addresses (now called physical addresses).
With memory mapping, the program always uses a
fixed set of addresses, and relocation is achieved by
a change to the translation mechanism. For example,
a translation mechanism for a value set into a base
register automatically adds that value to any address
used in the program. This approach is similar to
based addressing, which. however, uses an explicit
reference to the base register in the instruction. In
memory mapping, the base register is used to translate addresses completely independently of the program that generates them (Fig. 6).
One natural outgrowth of memory mapping is a
mechanism for sharing objects among otherwise
independent processes, even though the mapping
mechanism must be more sophisticated than a
simple base register. If different blocks of logical
addresses are mapped independently of one another,
a program or data area in physical memory can
correspond to different logical addresses for dif-

4-48

ferent processes. Thus, the shared program or data
can reside at a convenient location in the logical
address space of each process. And the mapping
mechanism will cause references from each process
to be mapped by that process's mapping scheme into
the given physical locations.
Segmentetlon offerl bener lolutlonl
Memory mapping, which provides the means for
dealing with two major problems plaguing linear
addressing, ironically must be part of any
segmented-addressing scheme, since physical memories are not usually organized in segments. Moreover,
all five major problems stemming from a linearaddressing model can be avoided.
The segmented addressing model assigns to each
object in the address space a "name" that is really
a binary number. Calling it a name emphasizes that
there is no relation between objects regardless of any
numerical relationship between their "names."
In the chess-playing example, the chessboard dis-0

Memorymapping
using
bue
register

lID

K
M-1

"Logical"
add_

play program could be assigned the name "1," the
current-position representation could be "2," the
legal-move generation program could be "3:' and 8.0
forth. The address of any location within the
chessboard display program would then consist of
the name, 1, and an address within object 1's linear
address space. If this program occupied 2048 bytes,
then the addresses within object 1 would range from
(1, 0) to (1, 2047). The length of 2048 bytes would
be an attribute of object 1 and the mechanism
responsible for the interpretation of segmented addresses would cause an appropriate error indication
if an address like (1, 2049) or higher were ever used
(Fig. 7).
Consider the case of the current-position program
-object 2 in Fig. 7. Suppose that this representation
takes the form of an array of 256 bytes. The addresses
of these bytes would be (2, 0), (2, 1)... (2, 255). One
way to refer to items of this array is indexed
addressing. The address of the desired item would
be specified by giving the array base address of

-- K

---

K+M-1
N-1

ActUlI

add_

7. With ••gm.nt.d .ddr•••lng, the .ttrlbut•• of.1I obJ.cts
.r. known, .nd .rror "'••••g•• pr.v.nt.n III.g.l.cc•••
b.'or.1t c.n do .ny h.rm.

8. M.mory m.pplng b.com••• Impl. with. b••• r.gl.t.r:
Ita "valu." I•• utomatlc.lly .dded to th.loglc.1 eddr......

4-49

Segmentation
(2, 0) in one place-say, in the instruction or in a
register-and an index (also called an offset) in a
register. The index is simply a number to be added
to the second component of the segmented address.
If the index were 17, then the item address would
be (2, 17); the address manipulation cannot affect
the object-name portion of the address, only the
linear address within the object.
In object 1 of Fig. 7-the
display program-the
_ _ _ 1... __ : _________ !Ll ...
__ _ .:I.J __ ......
! __
!_L _____ L ......

Ul'C\"UQ,UU:Ull

J. 'CoYUU,:UUl1:,

.lUI.

QUU.l 'CiiOiO

111!,A;;;J.}Jl.

..a"lVU

~;a,

performs a similar computation for addressing relative to the program counter. If the program contains
a branch to "current location + 1264," for example,
then the offset given in the instruction is applied to
the second part of the address. If the call were made
from location (1, 562), then adding 1264 to 562 would
yield (1, 1826).
Pr.v.ntlng Invalid acc •••••

Suppose that a programming error causes the
current-position representation array to be addressed with an index value of 257. In a linear
addressing scheme, the result would be a reference
to the second byte of whatever object follows the

________

23·BIT LOGICAL ADDRESS
--------~A~

87
OFFSET

-I

SEGMENT
DESCRIPTOR
REGISTER

current-position representation array in memory. If
the legal-move generation program happened to
follow the array in memory, half of its first word
would be overwritten. With segmented addressing,
the mechanism that interprets addresses would discover that (2, 257) is incompatible with the declared
length of the array (256 bytes); an appropriate error
indication would be generated.
Once the mechanism to check accesses against
.1 __ 1 ___ ..1 .... L.! __ .. _! __

L __ \... ___ .......... _'L..l: ... t..,..A : ....... 1.r"",n h","

U'Ci\,;.lQ..l'CiU VUJc .......

IIGO

~1~C:

U~'Ci1.l ~i:)\.QJJJ..lc",,,,~u,

... " '--&...... .., U\.&IU

a small step to add the checking of other object
attributes. Problems like protecting one process's
data or program from accesses by another process
or allowing "read only" or "execute only" accesses
to a section of data or program can be solved by
checking attributes associated with the objects in
question. A write into a "read-only" object, a user
access to a "system-only" object, and other such
invalid accesses can be identified and prevented.
This capability is available in the segmentedaddressing model built into the Z8001. Its 32-bit
addresses contain two fields, the segment-name field
and the "offset"; the latter is added to the physical
memory address of the segment "base" to obtain the
physical address of the element in question (Fig. 8).
For example, if segment 5 has a base address in
physical memory of 1024, then the physical memory
location addressed by the segmented address (5, 26)
is 1050, because 1024 + 26 = 1050.
Ent.r the m.mory manag.r

I
I
I
I
I
I

The Z8001 is designed to work with an external
circuit called a memory-management unit (MMU),
which keeps track of the base addresses corresponding to the various segments, and computes the actual
physical addresses. This MMU can also associate a
variety of attributes with each segment, so it can
perform the corresponding access checking and generate an error interrupt (called a "segmentation
trap") in the event of an invalid access.
Another feature of this implementation is that
seven bits have been assigned to the segment-name
field and 16 bits to the offset. The result is up to
128 segments, each of them presenting a linear
address space of 64 kbytes. Furthermore, the external MMU circuit is designed only to translate the
uppermost eight bits of the offset; the eight low-order
bits are passed directly to the physical memory.
Consequently, all segment-base addresses in physical memory must be a multiple of 256 (since the eight
low-order bits are zeroes), and the size of a segment
-one of the attributes that the MMU checks-must
be a multiple of 256 bytes.
One problem with the Z800l's segmentation
scheme is that no object can exceed 64 kbytes in size
unless it consists of more than one segment. For-

24·BIT PHYSICAL ADDRESS

8. The Z8000'a memory-menegement unit (MMU)
apeeda up addreaa tranalatlon by forwarding the
low-ollaet byte directly, while adding the high byte
to the aegment value In hardware.

4-50

tunately, this rather infrequent problem can be
solved by software with very little overhead. For
example, to access the byte with an index kept in
R3 of the array whose base is in RR2, one must replace
the instruction
LD RL 1, RR2 (R4)

with the sequence
!move high-order index to
segment field!
!add low-order index to
offset field!
!add (w. carry) high-order
index to segment field!

EXB R4
ADD R3, RS
ADCB RH2, RH4
LD RL1, @RR2

where RR4 takes the place of R3. These instructions
place several segments "end-to-end" and treat the
segment name like a number.
However, the MMU implementation has a twofold

TOP OF STACK
MEMORY
ACTUALLY
ASSIGNED
NON·FATAL
STACK WARNING
OCCURS ON REFERENCE
TO THIS AREA

64K
BYTES

\256
BYTES

I
I
I
I
I
I
I

:~~ENT-_.L

I
_---l

9. When data begin to fill the top 258 bytes of assigned stack
space, a nonfatal warning Is generated to prevent possibly
de.tructlve overflow.

speed advantage:
1. Since the segment-name field is not involved
in the address computations of indexed, based, or
relative addressing, this field can be output to the
MMU one cycle earlier than the offset portion of the
address, thus giving the MMU a one-cycle head start
on the address translation.
2. The eight low-order bits of the offset, which go
directly to the memory un translated, are the bits
needed first by the memory, which enables the
memory to get a small head start on the transaction.
As a result, an external MMU circuit entails very
little time penalty in memory addresses. The true
independence of the segment-name field from the
offset in all address computations means that offchip memory mapping can be achieved with very
little overhead.
The architectural advantage of the Z8000 family
becomes clear by comparing its economical implementation with the method by which a nonsegmented CPU might achieve memory management. Undoubtedly, the approach will take the
form of paging.
In a paged system, the uppermost bits of the linear
address are treated like a segment-name field Ofter
the address computation is complete. Until the
computation is complete, these bits are treated like
part of a monolithic linear address-they can be
changed in the course of the computation. Thus,
while a paging scheme permits memory mapping and
attribute checking, it suffers from many of the
problems of linear addressing. In addition, it cannot
achieve the overlap of MMU and CPU computational
time that is available via the Z8000's segmentation
scheme. The only antidote to the computation overhead of an off-chip MMU for a linear-addressed
machine is to design an on-chip MMU; but with the
current technology, this approach is likely to require
the sacrifice of other features.
One more noteworthy point to be made about the
way the Z8001lMMU combination implements
segmented addressing concerns the use of stacks. The
most difficult problem associated with dynamically
expanding stacks involves the correction of pointers
into the stack when a stack is moved to another
location. Naturally, this problem goes away with
memory mapping, since the logical addresses of the
locations already used on the stack don't change
when the stack is physically relocated in memory.
Furthermore, the MMU accepts as one of the attributes of a segment that it is to be used for a stack.
Consequently, as Fig. 9 shows, a nonfatal stackwarning interrupt occurs when the stack is nearly
full-Le., when an access is made into the last 256
words allocated to the stack. Moreover, the employed
method for memory-address computation and size

4-51

Segmentation
specification takes into account that stacks grow
downward in memory, from the highest addresses
toward the lowest.
Segmented VI linear

Just as there are some who argue that higher-level
languages are "inefficient" and deny the programmer the total control of assembly-language programming, a few designers adamantly reject segmentation and cling to linear addressing. In fact, their
argument has some merit. Just as high-level languages may be inappropriate for very small systems,
segmentation may represent overkill in a small
memory space. The Z8000's answer to this problem
is to provide segments large enough to accommodate
a small application completely in one segment. One
of the Z8000's addressing modes consists only of
offsets, so that no references occur outside the 64kbyte linear address space of one segment. In fact,
for such applications, a smaller package is available
that lacks the eight pins dedicated to segment-name
output and segment-error interrupt input; this
smaller version cannot enter the segmented mode of
operation at all.
Drawing the line

Where does one draw the line between systems
that are too small for segmentation, systems in
which segmentation is desirable but inessential, and
systems that are so large that segmentation is
mandatory? It is a matter of judgment. The Z8000
architecture provides a 16-bit linear address space;
in its 23-bit address space, clever, well disciplined
programmers can handle unrestricted linear addressing; in its ultimate 32-bit address space,
segmentation is undoubtedly the only viable approach.
This concern for the future expansion to 32-bit
address spaces greatly influenced the decision to use
segmented addressing in the 23-bit version. The
Z8000 represents a break from the architecture of
the Z80; it seemed shortsighted to ask designers
moving from 8-bit to 16-bit or 23-bit systems to face
one architectural break today and another in a few
years (not to mention the huge investment in
already-developed software). By developing his system around a Z8000, a designer will not have to face
another architectural upheaval when segmentation
is introduced-which, if the address space increases
to 32 bits, seems inevitable.D

4-52

Initializing the Z8001 CPU
for Segmented Operation
with the Z80 10 MMU
Application
Note

Zilog

September 1981
INTRODUCTION

The example shown In F Igure 1 also has bl t 14
set.
BIt 14 IS the SIN blt, whICh controls the
CPU's cholce of system or normal mode operatl0n.
The settlng of SIN blt duects the CPU to enter
The CPU must begln ope rat 10n 1 n
system mode.
system mode, Slnce the fust order of bUSIness IS
to establIsh an Imtial settlng for the System
mode stack regIster and to 1m t.lallze the MMU,
whlch requIres the executl0n of pnvileged 1/0
Instruct lons.

ThlS appllcatl0n note explalns how a ZSool CPU, to
whlCh at least one ZSolo MMU IS attached, IS Imbal1zed for segmented operatlOn.
Descnbed are
the speclflcatlon of the Imtlal CPU status to be
establlshed In response to RESET, executl0n of the
flrst program out of unmapped memory, and InItIalIzatIon of the fIrst, and pOSSIbly the only, MMU.
WhIle an attempt has been made to make thIS applIcatIon note self-contaIned, a general famll1anty
wlth the ZSoOl CPU and the ZSOlo MMU IS assumed.
For furlher detaIls, the reader IS referred to the
technIcal manuals desc rlblng these components
(ZSOOO CPU Techmcal Manual, document lI00-201o-C,
and ZS010 MMU Technlcal Manual, document #00-2015A).

The Inltial settIng of the EPU bIt (blt 13) In the
example shown In Flgure 1 IS 0;
If an EPU IS
present, thlS bl t can be set 1m tlally, but It IS
also posslb Ie for the CPU to determlne the appropriate setting of the blt as part of ItS Imtlahzatl0n.
The Interrupt enable bIts (bItS 12 and 11) are
Iml1ally set to 0 by the FCW specIF1ed In FIgure
1.
ThIS IS mandatory dUring the Int lallzat Ion
process, because there IS no automatlC Imtlallzatl0n of the System mode stack reglster;
the
System mode stack IS used In the processlng of all
traps and Interrupts.

INITIALIZING SEGMENTED PROGRAMMING
In response to a RESET slgnal, the ZSOOl CPU
estabhshes the CPU status speCIfied in 10cal1ons
2 through 6 of segment 0 (see FIgure 1).
MeanwhIle, the ZS010 MMU, whlch IS assumed to be connected to the CPU as shown In Flgure 2, enters a
state In Whlch It passes the SN6-SNO and AD15-ADS
lInes dlrectly through to ItS A22 -A S address output hnes and asserts a 0 on A23. The practlcal
effect of thlS IS that the first Iml1alization
Instructlons to be executed are taken from speciflC addresses In physical (unmapped) memory.
OperatIon of the ZSOol CPU In segmented mode
depends on the setl1ng of the SEG blt (blt 15) In
the Flag/Control Word (FCW) control reglster. The
1m bal FCW set tlng IS taken from locatlon 2 of
segment 0, so the contents of locatIon 2 must have
blt 15 set to duect the CPU to enter segmented
operatlng mode.

The Iml1al PC value of segment 0, offset S glVen
In the example In F Igure 1 IS a convement one,
Slnce It means that the lnltlallzat 10n programs
can follow the Imtlal CPU status In memory.
Also, the CPU status and the Imtlal1zat!On program are In the same area of memory, so only a
small part of the physlcal memory address space
needs to be commltted to a speclflc use.
• The addresses of the Int tlal CPU status and the
Imtlahzatl0n program are 10glcal addresses, but
at the tlme of execut!On of a reset or power-on
sequence, there IS no assurance that the MMUs have
been Iml1allzed to perform address translatlOn.
The ZS010 MMU, however, has been deslgned to enter

4-53

a mode after a reset or power-on sequence In Which
It passes addresses dIrectly to physIcal memory
untranslated. (More precIsely, It performs a SImple, well-defIned translatIon: segment N offset K
IS translated lo physlCal address K + N x 216 .)
Thus, the Imbal CPU status IS taken from physIcal addresses 2 through 6, and In the example
shown In FIgure 1, the Imtlal1zallon program
beglns at physlCal address 8.
One of the tasks
that the InItIalIzatIon program must perform IS to
ImtIalIze MMU mappIng tables.
Uillmately the

nent PSA and stack wIll be establlshed In
mapped memory after Imtlal1zat lOn of memory
mappIng. )
(2)

removed ent Hely from the log lcal address space,
remaInIng In physical memory, that can be left
InaccessIble unt 11 another reset or power-on
sequence occurs.

17:\

T __ J... _ _ 1 ___

LL_

l"'.L __ 1.

_ _ _ _ _ '- _ _ _ _ oJ

DeflO

.1._

\,/)

.L11..LI....LCl.L.LLC

I..IIC

,J1".c:n.. "

.LC"'=!.LOI,..C.L

I ..... nl

I,..U

ClIIU

address the "real" stack and Program Status
Area In mapped memory.
After carryIng out these steps, the program transfers to the SYSTART roullne (not In segment 0) to
contInue Imtlallzation of the speCIfIc appllcatlOn. The roullne at SYSTART IS free to estabhsh
a new mappIng for segment zero, rendenng the
1m t lallzat Ion code Inaccessib Ie;
anot he r reset
makes It avaIlable agaIn.

FIgure 3 shows an InItIalIzation program that contInues the example begun In FIgure 1. The program
carnes out three steps:
(1)

Call the SETMMU roullne (FIgure 5) to lnltlallze memory mappIng, leavIng the locatIons
In
segment 0 used by the Iml1allzatlon
sequence st 111 mapped to the same physIcal
locatIons they were uSIng before MMU InitlallZatlOn.

InItIalIze the Stack regIster (RR14) and
Program Status Area POInter (PSAP) to pOInt
at a small temporary stack and a skeleton
Program Status Area, both In known locat lOns
In physIcal (unmapped) memory.
(The perma-

The routIne at STARTUP, the skeleton Program
Status Area at INITPSA (FIgure 4), and the SETMMU
roullne and Its assocIated table at MMTAB (FIgure

CPU Status for RESET Instruction Memory, Segmeoc 0, Offsets 2-6
Offset

Meani~

Conteocs (hexadecImal)

Irrelevant

COOO

Imbal FCW:

0000

Imbal PC:

segment 0 (bItS 14-8); all other bItS must be zero

0008

Imbal PC:

offset 8 (16 bItS)

SEG (bIt 15) and SIN (bIt 14) set;

all others 0

(Start of startup program)

The values shown are a pOSSIble settIng for the Imbal CPU status to be establIshed when a
RESET SIgnal IS receIved. The FCW setting IS taken from segment 0, offset 2. The value COOO
shown here results In the set tlng of segmented operal1ng mode (bIt 15) and System mode (bIt
14). BIt 13 IS 0, IndIcatIng that no EPU IS present, and bIts 12 and 11 are 0, Indlcallng
that neIther vectored nor nonvectored Interrupts are enabled. The settIngs of the FLAGS bIts
(bItS 7-2) and the unused bItS (bItS 1-0) are Irrelevant In thIS example.
The PC segment number and offset are taken from segment 0, offsets 4 and 6, In the standard
lwo-word segmented address format.
Any address can be speCIfIed.
The value of segment 0,
offset 8 shown here allows the startup program to begIn at the next locatIon of segment O.
If MMUs are part of the system, they must handle the Imtlal InstructlOn fetches properly,
even though the CPU has not yet InItIalIzed the MMU translatIon tables.

F1gure 1.
751-1790-0008

Locahons 2-6 of Segmeoc 0 Determine Initial CPU Status

4-54

4) all

res~de ~n ROM, whereas the temporary stack
need not exceed 10 words ~n length as the
present program ~s Wrl tten) must res~de ~n RAM,
preferably ~n "physiCal segment 0", ~.e., In the
first 65,536 bytes of phys~cal memory.
In fact,
us~ng the MMTAB entry
for segment 0 shown ~n
F~gure 4, the temporary stack should res~de ~n the
fust 784 bytes of phys~cal memory. SInce all of
the ~nstruct 10ns and tables shown In F ~gures 1
through 5 occupy less than 512 bytes, a phys~cal
memory whose fus t 784 addresses refer to 512
bytes of ROM and 256 bytes of RAM (usable later
for other purposes) w~ll suff~ce.

course of execut Ing the programs shown ~n F ~gures
1 through 5.
(Of course, a memory error could
lead to an unimplemenled ~nstructlOn or system
call trap, and a faulty CPU could do pract ~cally
anyth~ng.)
Both of the ~nterrupt roullnes
prov~ded do noth~ng but halt.
The segmentat ~on
trap routIne could do somethIng more ~ntell1genl
~f It had access to a means of communlCat~ng error
~nformat~on to the "outs~de world."

(wh~ch

The MMU lmllallzatlon program shown In Flgure 5
lS easlly understood by anyone faml11ar wlth the
contenls of the Z8010 MMU Techmcal Manual.
It
beg~ns by transffiltllng a set of segment descl'1ptors to the MMU; then ~t enables address trans lat10n by the MMU.
Two "programm~ng tr~cks" and a
convenllon must be understood.

The skeleton PSA shown ~n F ~gure 4 needs 11 t tle
explanatlOn.
Only the segmentatlOn trap and the
nonmaskable ~nterrupt must be prov~ded for, s~nce
no other ~nterrupts or traps can occur In the

r---

RESET

Z8001

CPU

;
;

SNa-SNo

A23-A S

SEGT

¢ll

Z8010

____

MEMORY

MMU

~
CONTROL

SYSTEM

SUP

rr=:u~cs

AD,

RESET
A D7- AD o

5Ta-5To

AD1S- AD s

SEGT

ADD

Th~s

d1agram shows the convent 10n adopted In th~s appl1callon note for the connect 10n of the
(posslbly only) MMU. Th~s MMU wlil translate references to segments 0 through 63 (SN6 =
0). Its ChlP Select (CS) s~gnal 1S actlVated by a 0 on AD1 , whlch means that any spec~al I/O
transactlOn whose I/O address has a lower byte ~n whlCh b~t 1 ~s zero wlil be recognlZed as a
command by thlS MMU. The reason for us~ng the complement of the g~ven A/D line to seleel the
Ch1P ~s an artlfact of the behavlOr of 3-state log~c. The "floaLlng" value shows up as a Hlgh
Allow~ng the Reset lIne to be lnput to ~ causes thlS MMU to pass
on CS dUl'lng a reset.
addresses to the memory untranslated after a reset.
f~rst

In mult~ple-MMU conf~guratlOns, the Reset l1ne needs to be lled to Cs for only one of the
MMUs.
MSEN lS set and TRNS ~s cleared In that MMU, allow~ng It to pass the 1m hal memory
accesses untranslated.
All other MMUs w~ll 3-state then outputs.
The form of connectlOn
shown here ~s the same as for MMU Ifl In the examples ~n the Z8010 MMU Techn~cal Manual (doc
/100-2015-AJ.

F.tgure 2.

I'I4U Is Connected as H.... 11

4-55

The f~rst programmlng trlck lS the use of a computatl0n to determlne the number of bytes to be
transferred to the MMU by the SOTIRB lnstructl0n.
The requued number lS the dlfference between the
offset port 10ns of two addresses:
the fust
descuptor byte and the fust byte past the
descuptors.

clrcultry) lS contalned In the lower byte. In the
example 1n Flgure 4, the reglster R4 conta1ns the
speclal I/O address.
The low-order byte (RL4)
conta1ns the complement of the value 3 (blt 1
clear, all other b1tS except blt 0 set), whlCh lS
the selectlon code for MMU 111.
The upper byte
(RH4) fust conta1ns 1 (the "address" of the MMU's
Internal SAR reglster), then 2 (the opcode for
"transmt descriptor and lncrement SAR"); then 0
(the
"address" of the MMU's 1nternal mode
reglster) •

The second programmlng tuck lS the lncluslon of
the lmtIal SAR and mode reglster values ln the
table of descnptor values.
ThlS programmng
to perform the one-byte transfers are SOUTB and
SOUTIB.
The only alternatIve to the last two
lnstruct lOns before the RET, for example, lS

The table at MMTAB (Flgure 5) can be easlly
understood. The fust entry, a slngle byte of 0,
lS used to lmtIalne the SAR (segment address
reglster), an lnternal MMU reglster used to
determ1ne whlCh of the 64 segment descriptor
reglsters lS belng addressed by the command to the
MMU.

LOB RHO,II%C2
SOUTB 1.0000, RHO
That alternatIve lS perfectly acceptable ln thls
case, but ln cases where the ldent lty of the MMU
to be addressed 1S not known ln advance, the
alternat1ve shown ln Flgure 5 lS preferable.

The next 4'(n+1) bytes are the values used to
lmtlalne the descriptors for segments 0 through
n. ThlS lS done uSlng a block I/O transfer to the
MMU "address" that loads a descriptor reg1ster
(four bytes) and then lncrements the SAR to
address the next descriptor reglster.

The conventlOn that must be understood concerns
the way m WhlCh the speclal I/O lnstructl0ns are
used to select MMU operat~ons. The MMU opcode or
lnternal regIster address lS represented 1n the
h1gh-order byte of the speclal I/O space address,
wh lIe an MMU select Ion code (decoded by speCl al

The flnal byte lS used to set the MMU mode
reglster ID held to 0 and the blts MSEN and TRNS
to 1;
thlS lS a change from the values

Thls lS the lmt~ahzat10n program transferred to after a reset of the ZB001 CPU, assum1ng
the se\. tlngs shown ~n F19ure 1 for locat lons 2-6 of segment O. The FCW shown ln F19ure 1
results ln entry to th1S routlne 1n segmented system mode.
$ABS B
STARTUP:

!Program beglns at segment 0, offset 8!
LOA RR14,INITSTACK
IInitlallze system stack reglsterl
LOA RRO,INITPSA
IInltlallze PSAPI
LOCTL PSAPSEG,RO
LOCTL PSAPOFF,R1
CALR SETMMU
!Inltlallze memory mapplng!
LOA RR14,REALSTACK
!In1tlalize system stack!
LOA RRO, REALPSA
!Inltlallze PSAP!
LOCTL PSAPSEG,RO
LDCTL PSAPOFF,R1
JP SYSTART

ThlS start-up program conducts a "bootstrap" operatlOn.
It first sets the Stack reglster
(RR14) and the Program Status Address Powter (PSAP) to values 1n the unmapped physlcal memory
area used by the Inltlallzaton routlne. It then calls the SETMMU program to lnltlallze memory
mapplng. Flnally, lt sets RR14 and the PSAP to then correct values ln the mapped memory and
jumps to the address SYSTART ln mapped memory to contlnue the lnltlallzatl0n process. At thlS
pOlnt, the space ln physlcal memory used by STARTUP and the temporary PSA and stack, whlCh was
not remapped by the SETMMU rout1ne, can be released.

Figure ,.

Startup Code InitIalizes Interrupt Vectors and Memory Mapping
4-56

acknowledge status output of the CPU by assert 1rg
ADa (a + value of the 10 f1eld) and leaVlng
A015-A09 3-stated. US1ng the convent 10ns glven 1n
the Z8010 MMU Techmcal Manual, th1S uEntlfles
the MMU as MMU 111 1n the "reason" placed on the
stack when a segment trap occurs.

estab l1shed by the RESET:
MSEN set, TRNS zero.
MSEN (master enable) must be set to enable the MMU
to em1t addresses (otherw1se 1tS oodress output
hnes rema1n 3-stated). If MSEN 1S set, the TRNS
b1t determlnes whether address translat ion 1S
performed (TRNS = 1) or addresses are passed
through as 23-b1t patterns (TRNS = 0). The other
settable b1tS of the mode reg1ster, wh1Ch are left
clear by the value shown 1n F1gure 4, are URS, MST
and NMS. URS (upper range select) allows the MMU
to respond to segment numbers 64-127 rather than
0-63 on the CPU output 11nes SN6-SNO'
MST
(mult1ple
segment
tables)
allows
select lve
enabllng of address lranslatlOn by the glven MMU
(CS is used to enable command recogmtlOn by the
MMU but has no effect on address translat10n). If
MST 1S set, then match1ng the NMS (normal mode
select) value w1th the MMU's N/S 1nput 11ne serves
as an enabl1ng cr1ter10n for address translatlon.

The number and values of the descl'1ptor sett1ngs
In the table at MMTAB depend on the detal1s of the
spec1f1c ~pllcatlOn and are not dlscussed further
here.
The add1t10nal lnltlallzat10n code at
SYSTART also depends on the speClf1c ~pl1catlOn.
TYP1cally, thlS code 1nltlalues penpheral deV1ce
handl1ng, enables 1nterrupts, and starts user
processes. The deta1ls are not discussed here.
Th1S concludes the dlScuss10n of the spec1f1C
deta1ls common to the lnlllal1zatlOn of any ZOO01
cPU/Za010 MMU system.
Van at lOns are poss1ble,
but,
m
most
cases,
the
general
form
of
1nlt1ahzatlOn shown here 1S followed.

Setting the 10 f1eld of the MMU's mode reg1ster to
o duects the MMU to respond to the segment trap

ThlS 1S the Program Status Area used temporanly dunng the stage of 1mllal1zatlOn that
precedes the 1n1 t lahzat ion of memory mapplng.
It res1des In phys1cal memory duectly
followlng the STARTUP rout1ne.
INITPSA:

word
word
word
word
word
address
word
address

0,0,0,0
0,0,0,0
0,0,0,0
0,0,0,0
O,%COOO
SEGTRAP
O,%COOO
NMISTOP

No more of the PSA lS reqUlred.
10catlOns.
NMISTOP:
SEGTRAP:

! Unused entry!
!Ummplemented 1nstruct wn trap!
!Prlv11eged instruct10n trap!
ISystem Call trap!
! Segme ntat lOn trap!
!Nonmaskable interrupt!

Processing rout1nes can res1de 1n 1mmedlately follow1rg

HALT
HALT

ThiS lS the bootstrap PSA used for the orderly handl1ng of unexpected interrupts dunng the
phase of the lmt1al1zatlOn process that precedes lnllal1zat10n of memory mapping.
The two
process1ng rout1nes, NMISTOP and SEGTRAP slmply halt. More effectlve act10ns can be taken 1n
an actual system 1f ~proprlate rout1nes eX1st at known locat10ns In phys1cal memory.

Flgure 4.

Initial PSA Has Few Real Entrles

4-57

ThIS IS the MMU Inltlallzatlon routIne called from the STARTUP program;
It assumes a
slngle-MMU system.
Fust, up to 64 of the MMU's segment descnptor regIsters are loaded
from a table In memory. Then address translatIon IS enabled. The only restnctlOn on the
address translatlon set up thIS way IS that the addresses of STARTUP must cont Inue to be
mapped to the same physIcal locatIons.
SETMMU

LOB RL4,H3
COMB RL4
LOA RR2,MMTAB
lOR RH4;IJ1

SOUTIB ®R4,®RR2,R1
LOA RRO,MMTABX
SUB R1,R3
LOB RH4,H%F
SOTIRB ®R4,®RR2,R1
LOB RH4,HO
SOUTIB ®R4,®RR2,R1
RET
MMTAB:

MMTABX:

byte
word
byte
byte

!Select MMU H1 and assure BIt 0 = 1!
! Use complement to act lvate CS!
!Address of InformatIon for MMUI
!Address of SAR In MMU!
IImllallze SAR!
!Next byte past descnptor table!
INumber of bytes In descnptor table!
IOpcode for descnptor transfer!
ITransmlt descrIptor table to MMUI
! Opcode for "set mode reg" I
I Enab Ie address translat lOn!

IImtlal value (segment nurrber) of SAR!
ISegment 0: starts at physIcal address O!
784 bytes long
Execute only

0
2
11A

word BASEn
byte SIZEn
byte ATTRIBUTESn

!Segment n (~63): starts at 256*BASEn!
256·(SIZEn + 1) bytes long
attrIbutes as speCI hed

byte %CO

!MMU mode regIster value:

MSEN, TRNS; 10

= O!

ThIS MMU Imllallzatlon routIne transmIts the table of segment
descnptors at MMTAB to
the MMU addressed by specIal I/O InstructIons WIth a lower byte In whIch the value of bIt 1 IS
o (MMU H1 USIng the convent Ions suggested In the Z8010 MMU Technical Manual). FInally, It
transmIts a mode regIster value In whICh the MSEN and TRNS bItS are set and all others are O.

FIgure 5.

A Few Instructions Initialize the MMU

4-58

00-2154-01

Non-SegDlenled 18001
CPU Programming
Application Nole

Zilog

September 1981
INTROOUCTION

The Z8001 CPU, which is designed to operate with 8M
byte segmented memory address spaces, can also be
operated in a non segmented mode.
Thus the user
gets the best of two worlds: the flexibility and
power of 8M byte segmented memory address spaces,
and the economy of 16-bit addresses. Furthermore,
the Z8000 CPU Family has been designed in such a
way that operation of the Z8001 CPU in non segmented
mode is compatible, to the extent possible, with
operation of the Z8002 CPU, which is designed to be
used exclusively in nonsegmented mode.
This application note first describes in detail the
differences in memory and register space requirements and in instruction execution times between
segmented and nonsegmented Z8001 CPU operation. It
then enumerates and discusses the few points of
incompatibility between ZA002 CPU operation and
nonsegmented Z8001 CPU operation. The Z8003 CPU is
identical to the Z8001 CPU for the purposes of this
note.
One of the trickier points in dealing with nonsegmented Z8001 CPU operation is the mixing of nonsegmented and segmented programs within an application. Several ways to handle such mixing are discussed. Finally, to make parts of the discussion
completely specific, a means of handling the system
call (SC) trap is shown with actual Z8001 CPU
programs, and several utility routines designed to
be invoked through the SC mechanism are presented.

This application note deals very specifically with
"esoteric" details of Z8001 CPU operation.
The
reader is assumed to have read the Z8000 CPU
Technical Manual (OO-2010-C) and to be familiar
with the general ideas of segmented memory addressing on the Z8001 CPU and with interrupt and trap
handling in the Z8001 CPU Family.
ECONOMIES OF NONSEGHENTED Z8001 CPU OPERATION

All Z8001 CPU memory addresses are 23 bits long.
In the segmented mode of operation, each address is
specified completely, using 32-bit representations
in instructions and registers.
In nonsegmented
mode, all address representations assume implicitly
the 7-bit segment number field of the Program
Counter (PC), so that only 16 bits are required to
represent any address.
The abil i ty to use 16-bit address representations
when operating the Z8001 CPU in nonsegmented mode
results in economies of both space and time. The
economies of space derive from the smaller memory
and fewer registers used for 16-bit address representations.
The economies of time, generally
speaking, deri ve from the fact that there is no
need to fetch or store a second word of address
representations in instructions, in registers, or
on a stack. Thus, for example, a RET instruction
requires an additional three clock cycles of execution time in segmented mode, because an extra word
must be popped from the stack. The space and time
economies of nonsegmented mode Z8001 operation are
summarized in Table 1.

4-59

Table 1. EconOlllles of Z8001
Nonsegmented Operation

Function

Space Economy

Tillie EconOlll)'

(clock cycles)

Instructions using
direct addressing
(compared with full
segmented address)

1 word of
instruction
memory

Instructions using
direct addressing
(compared with short
segmented address)
Instructions using
indexed addressing
(compared with full
segmented addresses)
Storage of an address
in a register

1 word of

cycle

3 cycles

instruction
memory

1 word register

Moving an address

CALL or CALR

3 cycles

Difference in
timing between
word and long
word version of
LD, PUSH, POP, etc.
1 word of stack

RET

5 cycles

3 cycles

LOPS

2 words of data
memory

3-4 cycles

Loading to or from
PSAP or NSP control
register

1 word register

7 cycles

3P using indirect
register mode (@)
if jump is taken

1 word register

5 cycles

Use of indexed
addressing to
simulate based
addressing

Fewer instructions
for many operations

2-4 cycles for
Load instruction;
added savings
when shorter
programs result.

4-60

Table 1 can also be regarded as summarizing the
"segmentation penalty" if nonsegmented operation is
taken as the standard. It is clear from the table
that among common operations the only difference in
size between segmented and non segmented mode instructions is the extra word required by direct or
indexed addressing using full (as opposed to short
segmented) addresses in the instructions.
Most
large programs avoid direct addressing, except for
CALL instructions and references to global variables, both of which can use short segmented addressing in a large proportion of cases.
The table also shows that among common operations
not involving direct or indexed addressing, the
only difference in instruction execution time between the segmented and non segmented Z8001 CPU
operating modes is in subroutine calling and
returning. Th is difference is due to the sav ing
and restoring of 32-bit return address representations.
A major savings that is difficult to measure
quantitatively results from the use of indexed
addressing in nonsegmented mode to simulate based
addressing. Thus, for example, it is possible to
write
ADD RO,4(R15)
to add the third word of the stack to the contents
of RO. In this construction, the offset (4) plays
the role of the address, and the address (the contents of R15) plays the role of the offset. Since
each is 16 bits long, there is no difference; they
are added together to obtain the 16-bit offset portion of the argument address; the segment number
portion Is derived from the PC.
Thus, based

4-61

addressing, which is essential for the handling of
stack-based data, is available with most instructions.
There is one pitfall to watch for when using indexed addressing to simulate based addressing. Indexed references never resul t in "stack reference"
status on ST 3-STO, since this status only occurs
when the Stack register (R15) is used as an address
register. In indexed addressing, the address comes
from the instruction, dnd the register contains an
offset.
Thus, if data and stack memories are
distinguished by the STJ-STO status outputs, then
indexed address ing cannot be used to access stack
elements

lBOOZ Ca.patlbility
The road between the Z8002 CPU and nonsegmented
Z8001 CPU operation is a two-way street: programs
can migrate in either direction. For example, a
Z8001-based development system can be used to
d('velop and check programs whose target system is
Z8002-based. Conv('rsely, a Z8002-based application
can be easily evolved into a Z8001-based application by using a nonsegmented Z8001 operation as a
first step. Furthermore, utility routines or other
parts of a program developed for one of these CPUs
could be integrated with programs develop('d for the
other. All of these possibilities illustrate the
importance of writing nonsegmented code for the
Z8001 CPU.
There are very few differences between Z8002 code
and nonsegmented Z8001 code; all of them are
associated with interrupt processing (see Table 2).

Table 2. Differences Between l8002 and
Nonsegmented l8001 CPU Operation

l8002 Operation

l8001 Operation

Interrupts and traps, including
SC, cause a 3-word CPU status to
be saved on the stack in the
format:

--->

Interrupts and traps, including
SC, cause a 4-word CPU status
to be saved on the stack in the
format:

reason
FCW
16-bit PC

--->

reason
FCW
PC - segment number
PC - offset

The 256 possible interrupt
vector byte values correspond
to legal vectored interrupts.

The 128 even-numbered interrupt
vector byte values correspond
to legal vectored interrupts.

The Z8002 CPU uses a Program
Status Area (PSA) format in
which one word is dedicated to
each FCW and each PC. No entry
is required for the "segmentation trap" vector.

The Z8001 CPU, regardless of
the mode in which it is
operating, uses a PSA format
in which two words are
dedicated to each FCW and each
PC.

The Z8002 CPU must be placed in
system mode before the IRET
instruction is executed.

The Z8001 CPU must be placed
into segmented system mode
before the IRET instruction is
executed.

4-62

The practical effect of th~se differences is very
The PSA differs
small in many applications.
between the lB002 and lB001 versions, but the differences are only in the sizes of th~ vector
entries--four words for the lB001, two words for
the lB002. The lB001 restriction to ~ven-numbered
vectored interrupt devices I imi ts the number of
devices to 12B, which is ample for most appl1caThe interrupt and trap routin~s can be
t ions.
almost identical for the two versions, unless they
access the saved PC value or anything "deeper" in
the stack. Since the "reason" and the saved FCW
are the top two words of the stack in either case,
the instructions that access these items can be the
sa11K' in both versions. The lB001 versions of the
interrupt routin~s can be written in nonsegmented
form.
The SEC bit must be set to zero in the
corresponding PSA entry's FCW value, and the CPU
must b~ placed into segmented mod~ before execution
of the IRET instruction. A good approach to this
is to dedicate one of the SC instructions (e.g., SC
110) to the performance of this kind of segmented
IRET. The details of this will be explained in a
later section; the advantage of the approach is
that it provides a one-word replacement for the
IRETs of a lB002-based program.
When the lB001 CPU is operating in non segmented
mode, R14 refers to the sam~ register in both
Syst~m and Normal modes, just as in lB002 CPU operation. This is not anomalous or surprising, but
many new lBOOO programmers have been confused by
the requirement that interrupts be processed in
segment~d mode.
If an interrupt occurs when the
lB001 CPU is operating in non segmented System mode,
the CPU immediately enters the segmented System
mod~ of operation.
At that time, R14 begins to
refer to the s~gment portion of the stack register,
and the register previously referred to as R14 is
accessible now only by using the LOCTL instruction
with th~ NSPSEC operand. This situation remains in
effect until the CPU returns to nons~gmented operation, which could happen before the ~xecution of
the first instruction of th~ int~rrupt-processing
routine if the FCW loaded from the PSA do~s not
have the SEC bit set.
COIBININC SEGIENTED

All)

Progra.s that access data or call progra.s in
another s~t aust consist wholly or partially of
s~ted code.
ProgriUIS that Mke no references
outside of their own seg.ents can consist entirely
of nonSCl!Jllented code.

One point to consider when mixing segmented and
nonsegmented code is that operation of the RET
instruction depends on the mode in which the CPU is
operating when the RET is executed, whereas the
operating mode on entry to a subroutine is that of
the calling program. Thus, special steps must be
taken to assure that subroutines called by programs
running in either mode behave properly.
One
approach is to enter such routines through the SC
mechanism. Another approach is to allocate two of
the SC instructions to subroutine entry and ex 1t
functions. The first of these SC instructions is
executed as the fl rst instruction of a subroutine
to save the caller's operating mode; the second
replaces the RET instruction and causes the CPU to
enter the proper mode before return ing. Furthermore, there can be two versions of the first of
these SC instructions; each can save the caller's
op('rating mode, then place the CPU into the mode
appropriate for the given subroutine.
A Syste.s/Application Distinction

One separation of segmented and non segmented code
is on the basis of the System/Normal operating
mode. A set of g~neral utility programs can be
written to be executed in segmented System mode,
and self-contained application programs can run in
non segmented Normal mode, using the SC mechanism to
make calls on the utility programs. An approach
such as this, which centralizes control of the mixing of segmented and non segmented programs, avoids
the complications of uncontrolled mixing of modes.
TIE SC IECHANISM

The preceding discussion includes several references to the use of SC instructions.
To allow
these examples to be understood at a more concrete
level, one of the many possible ways to handl(' SC
traps is (,laborated here.

NONSEGMENTED CODE FOR

mE l8001

Segmented and non segmented programs can be mixed to
any extent desired, since any program running in
System mode can carry out the required setting or
clearing of the SEC bit in the FCW.
If such
switching of modes is to be done at many points, or
if it is to be done by programs running in Normal
mode, two of the 256 SC instructions can be dedicated to the FCW changes.

4-63

Figure 1 shows a program to be executed each time
an SC trap occurs; that is, it is assumed that the
address SCHANO will be stored in the PC field of
the SC entry (vector) of the PSA. The program at
SCHANO is assumed to be segmented, and it accesses
the System mode stack, so the SEC and SIN bits must
be set in the FCW field of the SC entry of the
PSA. Furthermore, the VIE and NVIE bits of the FCW
field of the SC entry in the PSA must be 0, for
reasons to be discussed shortly.

SCHAND:

DEC R15,#14
LDM @RR14,RO,#3
LD R1,RR14('14)
CLRB RH1
foIlLT RRO,'6
LD R2,TABLE(R1)
INC R1,#2
LDL RRO,TABLE(R1)
LDL RR14('10),RRO
I n D1
.... "

1\'

DD1/.1.1L"\
,,,n'"T\"
lUI

AND R1,H1800
AND R2,#~E7FF
OR R2,R1
LD RR14(#8),R2
LDM RO,@lR14,#3
INC R15,#6
IRET

!Room for new status & 3 registersl
IUse RO-R2 fo~ working space!
!Get SC instruction (~eason)1
!Low byte is index to tablet
of 6-byte entries
!Get FCW entry from TABLE I
!Get PC entry from TABLE!
!Put PC entry into new status!
1/",.. ............... f ........
.~

...

C,..'" .......
+ .... .
....... "'.3.

.., .. """' .. v ............ "

!Save VIE,NVIE settings!
IZero VIE,NVIE in FCW from TABLEI
!Put saved bits into new FCW!
!Put FCW into new status!
!Restore registers used!
!Bring new status to top of stack!

This SC-handling routine allows each of the 256 SC instructions
to be written as if it had its own separate interrupt. An array
of 3-word entries called TABLE contains the FCW and PC values to
be established for each, except that the VIE and NVIE (inte~rupt
enable) bits in the FCW are taken from the saved status of the
program executing the SC instruction.
The Program shown here has not been optimized fo~ speed. Multiplication of the low byte of the ~eason by 6, fo~ example, can be
accomplished in fewer clock cycles than are required for the CLRB
and MULT instructions shown here.
Figure 1.

A Flexible SC-handling Sch_

4-64

The program at SCHAND simulates a "vectored interrupt" facility for SC instructions, but the VIE and
NVIE values are taken from the saved status of the
program executing the SC instruction, not from the
"vector" for that instruction. This assures that
the routines invoked by SC instructions, which can
be called from a variety of priority levels, won't
have the side effect of enabl ing any previously
disabled interrupts.
For this reason, the FCW
entry for SC must leave both VI dnd NVI disabled.

Given this mechanism, several of the uses of the SC
instructions suggested earlier can now be made concrete. Figure 2 shows possible assignments for the
first three SC instructions; Figure 3 shows the
corresponding TABLE entries and implementing programs. A reader who has difficulty understanding
these programs or the program in Figure 1 should
review the material on interrupt and trap handling
in the Z8000 CPU Technical Manual.

SC Instruction
SC flO
SC #1
SC f/2

Perform segmented IRET
Set SEG bit in FCW
Clear SEG bit in FCW

Figure 2.

TABLE:

Function

Possible SC Instruction Functions

word %COOO
long SEGIRET
word %C080
long SEGSET
word %COOO
long SEGSET

!SC #0:

SEG, SIN set!

!SC f/l:

SEG, SIN, C set!

!SC #2:

SEG, SIN set!

SEGIRET:

INC R15, #8
IRET

!Remove SC-related stack items!

SEGSET:

LD @RR14,RO
LD RO,RR14(#2)
JR C,$l
RES RO,f/15
JR $2
SET RO,f/15
LD RR14(H2),RO
LD RO,@RR14
IRET

!Save RO, use reason as scratch!
!Get saved FCW from the stack!
!C distinguishes SC #1 from SC #2!
!C 0 for clearing SEG!

$1:
$2:

!C
for setting SEG!
!Replace altered FCW on stack!
!Restore RO!

This section of TABLE and the associated programs implement the
three SC instructions shown in Figure 2. The program at SEGIRET
is operating in segmented mode because of its entry in TABLE, so
all it needs to do is return the stack register to its value
before execution of the SC #0 and to perform the IRET.
The program at SEGSET implements both the setting and the
clearing of SEG. The C bit setting in TABLE distinguishes the
two functions. The change to SEG is made in the saved FCW on the
stack, which is the source of the status that will be established
by the IRET instruction.

Figure 3.
00·2152·01

IIIple.entation of Three SC Instructions

4·65

Calling Conventions
For The
Z8000™ Microprocessor
Software
Interface
Specification

Zilog

February 1982

1.0

INTRODUCTION

The Z8000 Callwg Convent IOns allow programs
written In vanous languages for the Z8000 mlCroprocessor to communIcate WIth each other and to
share common hbranes.
The convent lOns lnclude
argument passIng, Stack POInter status, and register asslgnments on entry to and eXlt from a
rout lne.
The convent lons descnbed here apply to
all programmIng languages supported by the Z8000
mIcroprocessor.

How the stack must be orgamzed when entering,
executwg w, and returmng from a procedure.

•

Where parameters must be
returnlng from a procedure.

2.0

when

entering

Satisfy the requuements of lanquages such as
C. PLZ/SYS, FORTRAN, and PASCAL.

NON·SEGMENTED

SEGMENTED
PROGRAMS

PROGRAMS

• Do not lntroduce undue call and return overhead

seRATeRS
H ____

~ REGISTE

In code generated by one language processor at
the expense of another.
•

Mlnlmlze the complexlty of the code generators.

•

Allow passlng
value.

structured

parameters

>-. r

•

01 4

Encourage efflclency by allowing local varlabIes to be kept In registers and parameters to
be passed In regIsters.

01 5

OPTIONA
FRAME

Lr{

POINTER

012

013

014
015

ZBoOO Register Usage

The fust group IS called the scratch reqlsters
and consIsts of RO-R7.
These regIsters WIll
contaIn
value
or
reference
parameters when
entenng a procedure and result parameters when
returmng from a procedure. WhIle executIng, the

How regIsters may be used by procedures and
what happens to the regIster contents when
caillng or returning.

0130-001

SAFE
REGISTE

_ST ACK POIN TERr

Figure 1.
The call1ng convent lOn has three parts whICh are
described In the followIng sect lOns. These three
parts descnbe:
•

As shown In FIgure 1. the ZBOOO I S general-purpose
reglster set is dlVlded Into three groups for the
purposes of thIS caillng conventlon.

Caillng conventlons were developed that:
•

•

4-67

procedure may use these registers in any way and
does not need to restore them to the ir anginal
values when it returns.
The second group IS called the safe regIsters and
conSists of RB-R14 for nonsegmented programs and
RB-R13 for segmented programs.
The values in
these reg lsters must be the same when a procedure
returns as they were when the procedure was
entered. Th IS means a safe reg ister can hold the
value of a local variable, because procedure calls
wl11 not 81tl?'!" !ts \Ifill...!€"
IF e. p!,0!:;~dlJ!"e chenge~
the value of a safe regIster, It must save the
value of that regIster when it IS entered, and
restore it when It returns.
The thud group conSists of the stack pOinter
(SP), which IS R15 for nonsegmented programs and
R14 and R15 for segmented programs.
The stack
pointer always points to the top of the stack.
The callIng convent IOn also allows for, but does
not reqUIre, the use of a frame pOlnter to pOInt
to the current stack frame (deSCribed In the next
sectIon).
When a frame pOInter IS used, It IS
always the hIghest safe regIster, R14 for a
RR12
for
a segmented
nonsegmented program,
program.

and
floating-point
result
parameters
when
returning from a procedure. While executing, the
procedure may use these registers in any way and
does not need to restore them to their original
values.
The second group IS the floatIng safe registers,
These registers are used in the same way
as the general-purpose safe registers and thus the
values In these registers must be the same when a
procedure returns as they were when the procedure

FR4-FR7.

3.0

STACK ORGANIZATION

Figure 3 shows how the top of the st ack must look
when a procedure IS entered.
The return address
must be on the top of the stack (pOInted to by the
stack pOinter), followed by any parameters that
must be passed In on the stack. ThIS fIgure also
shows the stack after the same procedure has
returned. The only dIfference IS that the return
address has been popped off the stack.

AFTER RETURN
FROM A

UPON ENTRY

TOA
PROCEDURE

PROCEDURE

I'"

(either
Floating-Point
Registers
The
l8000
simulated in software by the Z8070 emulation
package or provided in hardware by the l8070
arithmetic processing unit) are Similarly divided
into two groups as shown in Figure 2.

i'"

PARAMETERS

PASSED IN

PAS5ED IN

STORAGE

STACK
STACK

1-----1
FLOATING
SCRATCH
REGISTERS

FRO

POINTER

1------1:::

RETURN
ADDRESS

STACK
GROWTH

POINTER

STACK

GROWTH

....

FLOATING

SAFE

REGISTERS

Figure 3. The Stack Upon Entry To
and After Return From a Procedure

L-_ _ _-'FR7

Figure 2. ZBOOO Floating-Point
Register Usage

The first group is the floating scratch registers,
FRO-FR3. These registers will contain floatingpoint value parameters upon entering a procedure

DUring the execut ion of a procedure. the stack
Will contain a data area called the stack frame
(also known as the aclt vat Ion record) for that
procedure.
The st ack frame IS allocated on the
stack by the procedure and contaIns saved values,

4-68

0130-002

executes, then It must save the values of these
reg Isters tn lls stack frame when tt IS entered so
that It can restore them when It returns.
The
hIghest safe regIster not used as a frame pOInter
should be saved at the top of the act. Ivat Ion
record (nearest the return address) wIth lower
number regIsters saved at lower addresses.
ThIS
is the same order used by the LDM Instruct Ion.
Only those safe regIsters actually modIfIed by the
procedure need to be saved.

local vanables. and temporary locat Ions for the
procedure.
FIgure 4 shows the stack whIle a
. procedure IS execut ing.

STACK WITHOUT
FRAME POINTER

STACK WITH
FRAME POINTER

PARAMETERS

PARAMETERS
PASSED IN
STORAGE

PASSED IN
STORAGE
RETURN ADDRE~
FRAME

SAFE REGISTER

POINTER

SAVE AREA

STACK
FRAME

RETURN ADDRE~

OLD VALUE OF
FRAME POINTER
SAFE REGISTER
SAVE AREA

FLOATING SAFE

FOR
EXECUTING
PROCEDURE

Any floatIng safe regIsters that are modIfIed by
the procedure are saved tn the act Ivat IOn record
just
below the
last
general
purpose
safe
regIster.
HIgher numbered floating regIsters are
saved toward the top of the actIvatIon record.

STACK
FRAME

FOR
LOCAL
VARIABLES

AND
TEMPORARIES

STACK

STACK
GROWTH

Figure 4.

POINTER

LOCAL
VARIABLES
AND
TEMPORARIES

EXECUTING
PROCEDURES

4.0

STACK

Parameters provide a substitution mechanism that
permits a procedure's activity to be repeated,
varying its arguments. Parameters are referred to
as either formal or actual. Formal parameters are
the names that appear in the definition of a
procedure. Actual parameters are the values that
are substituted for the corresponding formal
parameters when the procedure is called.

GROWTH

The Stlrk During Procedure Execution

The called procedure mayor may not use the frame
pOInter as shown.
If no frame pOInter IS used.
the size of the st ack frame must not change wh lIe
the procedure IS executIng.
Thus parameters
passed in storage by calls from thIS procedure
must be accommodated In temporary locatIons at the
bottom of the stack frame, and not pushed onto the
stack.
ThIS orgamzat IOn of the stack substanbally shortens the subroutIne entry and eXIt
sequence.

The Z8000 parameter-passing convent 10ns cover
three kInds of parameters: value, reference, and
result. Value and reference parameters are passed
from the calling routme to the called routme.
For value parameters, the value of the actual
parameter IS passed.
For reference parameters,
the address of the actual parameter IS passed.
For result parameters, the value of the formal
parameter tn the called rout lne lS passed to the
correspondIng actual parameter of the callIng routIne when the called routIne returns.

If a frame pointer is used, then the calling
procedures's frame pointer must be saved on the
stack by the called routine as shown in Figure 4.
If a frame pointer is used, the size of the stack
frame can vary, and thus parameters can be pushed
onto the stack if desired.

Each kind of parameter has a length given in bytes
(denoted as length(p) for a parameter p).
For
value and result parameters, this is the length of
the declared formal parameter as determined by its
type.
For languages that do not declare formal
parameters or when the procedure declaration is
not accessible when the call is being compiled,
the length is the same as the length of the actual
parameter. For reference parameters, the length
is the length of an address, in other words, two
bytes in non segmented mode and four bytes in
segmented mode.

The calling convent IOn allows procedures wIth and
wIthout a frame pOinter to be mIxed on the stack
From thIS pOInt of VIew, the frame pointer IS just
a safe register that IS used In an agreed upon way
by certaIn procedures.
If a procedure modIfIes the contents of any of the
safe registers or float Ing safe regIsters whtle It

9130-003

PARAMETERS

4-69

In addition to a parameter's length, the calling
convention distinguishes between parameters of
floating-point type and parameters of all other
types.

•

The underlYlng reglsters of a quad word regIster (rqn) are rln rhn, rln+l. rhn+ 1, rln+Z,
rhn+Z, rln+3. and rhn+3.

ThIS IS Illustrated In Figure 5:
The kind, type and length of a parameter are
determined by the conventions of the language in
which the calling and the called procedures are
written. The user must ensure that these conventions match when making inter language calls.

RQO

RQ4

RRO
RO
UNDERLYING

RR4

RR'
R1

BYT ~ RHOIRLOIRH11RL1 RH21Rl21RH31RL3

"c~ISicn;:t

4.1

R4
RH41

I I

THE PARAMETER REGISTER ASSIGNMENT ALGORITHM

ThIS sect Ion descrIbes an algonthm that assIgns
every parameter In a parameter 11st to eIther a
general-purpose regIster. floatIng pOInt regIster,
or storage offset.
The parameter assIgned to a
regIster IS passed In that regIster durIng a
call. A parameter assIgned to storage offset IS
passed In a storage locat lOn whose address IS the
gl ven offset from the Stack POinter on entry to
the called routIne. The algorIthm asSIgns as many
parameters to general-purpose reglsters rZ-r7 and
floatIng-poInt regIsters frO-fr3 as possIble.
The algorithm makes the following assumptions:

Figure 5.

The Underlying Registers

• If n > m, general-purpose regIster rxn or rn lS
hlgher than a general-purpose reglster rxm or
rm.
A byt.e reglster rln lS hIgher than a byte
reglster rhn.
•

There are eIght float lng-POInt regIsters, frOfr7, each capable of holdIng one floatlng pOlnt
value of any preCIslon.

•

A floatIng regIster frn IS hIgher than a float-

Ing regIster frm If n

> m.

There are four kinds of general-purpose registers:

= 0 ••• 15)

•

Byte (denoted as rln, rhn, n

•

word (denoted as rn, n

•

long Word (denoted as rrn, n
10, 12, 14)

•

Quad Word (denoted as rqn, n

•

The length of a general-purpose register r
[(denoted length(r)] is 1 for a byte register,
2 for a word register, 4 for a long word
register, and 8 for a quad word register.

•

Each general-purpose regIster has a
underlYIng byte reglsters as follows:

•

The underlYlng regIster of byte regIster IS the
reg Ister 1 tsel f.

•

The underlYIng regIsters of a word regIster
(rn) are the byte regIsters rln and rhn.

•

The underlYIng reglsters of a long word
regIster (rrn) are rln, rhn, rln+l, and rhn+1.

= 0 ••• 15)
= 0,
= 0,

2, 4, 6, 8,

4, 8, 12)

set

The algOrIthm starts by proceSSIng each value or
reference parameter In left-to-rIght order.
If
there are unused regIsters of the same SIze and
type as tne parameter. lne parameter IS assIgned
to the hIqhest of these regIsters; otherwIse, It
IS aSSIgned to the next avaIlable storage
locat ion.
Once a parameter is assIgned to
storage, all the parameters In the parameter hst
that follow It are also assIgned to storage. The
same thIng IS then done for the result parameters,
except they are asslgned to the lowest avaIlable
regIsters In sequence rZ, r3, r4, •• , r7 (or frO,
frl, frZ, fr3), whereas the other parameters are
assIgned to the registers In sequence r7, r6, r5,
rZ (or fr3, frZ, frl, frO).
The result
parameters
can
overlap value
or
reference
parameters In regIsters, but not In storage.
The algorithm marks byte registers and floatingpoint registers as available or unavailable to
keep track of which registers have been assigned
to parameters, and it uses a variable, current
offset, to indicate which storage offsets have
been assigned parameters.

4-70

0130-004

4.2

TIE AlGORITlIH

This algorithm assigns parameters to registers and
storage.
The phrases in bold are defined in
detail in Table A.

byte registers underlying r2-r7 as
available, and mark all other byte registers as
unavailable.
Mark floating-point registers
frO-fr3 as available and mark all other floating-point registers unavailable.

If P will fit into a register, assign p to
a value/reference register.
If P will not fit into a register, assign
p to storage and mark all available byte
and floating-point registers as unavailable.

1. Mark all

4. Mark all

byte registers underlying r2-r7 as
available and all other byte registers as
unavailable.
Mark floating-point registers
frO-fr3 as available and all other floatingpoint registers as unavailable.

2. Initialize current offset to 4 if in segmented
mode or to 2 if in nonsegmented mode (this
allows for the return address to which the
stack pointer points).

5. For every result parameter in left-to-right
order in the parameter list, do the following:
a.

3. For every value or reference parameter in
left-to-right order in the parameter list, do
the following:

b.
c.

Determ.ne
register.

whether

will

fit

Table A.
1.

into

Detenalne whether p will fit into a
register.
If P will fit into a register, assign p to
a result register.
If p will not fit into a register, assign
p to storage and mark all available byte
and floating-point registers as unavailable.

Definition of Algorltt. Ele.ents

Determ.ne whether p will fit into a register:

Assign P to a result register:

If parameter p is a floating-point
parameter then:

If P is a floating-point value or result
parameter, then p will fit into a register if
there is a floating-point register which is
available.
Otherwise, p will fit into a
register i f there is a register r such that
length(p) = length(r) and all byte registers
underlying r are available.

Assign p to a value/reference register:

Otherwise:
value

Assign p to the highest available floating-point register r.
Mark floating-point register r as unavailable.

b.
c.

If parameter p is
parameter then:
a.
b.

a' floating-point

Otherwise:
~.

b.
c.

0130-005

b.
c.

4-71

Assign p to the lowest available floating-point register r.
Mark floating-point register r as unavailable.

Find the lowest general-purpose register r
such that length(p) = length(r) and all
byte registers underlying r are available.
Assign parameter p to register r.
Mark all byte registers underlying r as
unavailable, and mark any lower available
byte registers as unavailable.

Assign p to storage:
a.

Find the highest general-purpose register
r such that length(p) = length(r) and all
byte registers underlying r are available.
Assign parameter p to register r.
Mark all byte registers underying r as
unavailable, and mark any higher available
byte registers as unavailable.

result

If length(p) > 1 and current offset is
odd, then add 1 to current offset.
Assign parameter p to storage at offset
current offset.
Add length(p) to current offset.

APPBI>IX A

This appendix gives an example of using the Z8000
calling conventions for a C language routine,
"caller", which calls another routine, "called".

UPON RETURN
FROM "CALLED"

UPON ENTRY

TO"CALLED"

Figure 6 shows the C code, and Figure 9 shows the
corresponding assembly language code.
Figure 7
shows the registers upon entry to "called" (just
after executing line 25 in Figure 9) and after
returning from routine "called" (just after executing line 13 in Figure 9). Figure 8 shows how
the stack looks during execution of "called"
(line 11 in Figure 9).

SCRATCH

REGISTERS

SAFE

REGISTERS

long called (a,b,c,d,e)
I*called routine - returns long */
long b,c;
int a,d,e;

{
}
caller ()

{

long y;
return y;

Figure 7.

Registers

Entry To and

Return FrOll Routine Called

1* calling routine */
long a2, a3, x;
int al, a4, a5;

:t~ :::::~~:s

SAVE AREAAND

}

x = called (a1, a2, a3, a4, a5);

STACKJ

Ii'DAUC

OF "cALLi;;';;

T~r·~RAL~~
A6(E)
M(D)

RETURN

Figure 6:

ADDRESS

A Sallple C Progr_

SAVED SAFE

SP BEFORE CALL

SP ON ENTRY
TO "CALLED"

REGISTERS

STACK {
FRAME
OF "CALLED"

LOCAL

VARIABLES
AND
TEMPORARIES
OF "'CALLED"

SPWHILE
"CALLED"IS
EXECUTING

STACK

GROWTH

Figure 8. The Stack Fr_ When the Routine
Called (FrOll the Suple C Progr.) is Executing.

0130-007

4-72

1 modul MODULE
2
$SEGMENTED
3
CONSTANT
4
fp
:=r15j
5 EXTERNAL
6
stkseg LABEL
~----------

!stack segment!
code for routine called - - - - - - - - - - - - - ,

7 GLOBAL
8
called PROCEDURE
ENTRY
9
10
dec
fp,114
11
ldl
rr2,!stkSegl(fP)
inc
12
fp,11
13
ret
END
14
called

15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

!Allocate called's stack frame!
!Assign local variable y to return register!
!Deallocate stackframe!

. - - - - - - - - - - - - code for routine caller - - - - - - - - - - - - ,
caller PROCEDURE
ENTRY
sub
fp,1122
!Allocate caller's stackframe!
ld
r2IstkSeg+4+14l(fP)
ld
!Move a4 to overflow parameter area!
Istkseg I (fp),r
ld
r2Istkseg+4+161(fP)
ld
!Move a5 to overflow parameter area!
Istkseg+21(fp),r2
ld
!Move a1 to r7!
r7,lstkseg+4+12!(fP)
ldl
!Move a2 to rr4!
rr4'lstkseg+4 1( p)
ldl
rr2, stkseg+4+41(fp)
! Move a3 to rr 2!
call called
ldl
!Assign returned value to x!
~stkSeg+4+81(fP),rr2
add
p,1I22
!Deallocate caller's stackframe!
ret
END caller
END modul

figure 9.

Actual ZOOO1 Code for Progrllll of figure 4

4·73

0130·008

APPEtlHX B
SPECIAL TREATMENT OF FLOATING POINT PARAMETERS
For programs which will run on a Z8000 without a
Z8070 arithmetic processing unit or Z8070 software
emulator, floating-point value and result parameters should be treated just like non-floatingpoint parameters.

Until September 1982, all Zilog compilers will
pass floating-point parameters in the same way as
non-floating-point parameters.
Thereafter, the
full standard given here will be used.

4-74

03-0130-01

Fast Block Moves wiUt the
Z8000™CPU

Zilog

Application Brief

September 1981
of transfer is 6 clock cycles per word. In either
case, there is overhead associated with setup and
looping.
The differences in overhead make LDM
more effect ive with small blocks and LDIR more
effective with large blocks. In either case, only
blocks of words, aligned on word boundaries, are
considered. For blocks of bytes, there is a byte
version of the LOIR instruction but no byte
version of LDM.

The ZSOOO CPUs are equipped with instructions that
allow memory-to-memory transfers to proceed at
speeds usually associated with DMA equipment.
This application brief shows how to use the two
different mechanisms available in ZSOOO CPUs for
block moves; then it compares their performance
fo r long and sha rt blo cks •
The two block-moving facilities in the ZSOOO CPUs
are the LDIR instruct ion (and its alter ego, the
LDDR instruction) and the LDM instruct ion.
With
LDIR, words are moved from one memory area to
another at a basic rate of 9 clock cycles per
word, using two address registers and a 16-bit
counter register. With LDM, words are moved from
memory into registers, then from registers into
the new memory area. The basic rate for this kind

Figure 1 shows a comparison of the two methods in
moving a block of eight words.
The method using
LDIR requires SS clock cycles, v.hile the method
using LDM requires only 70 clock cycles. At clock
rates of 10 MHz, these result in trans fe r rates of
1.S2M bytes per second for the LDIR method and
2.29M bytes per second for the LDM method.

!Assume that RR12 contains the address THERE and RR1D contains the address HERE.
ing sections of ZS001 instruction move a block of S words from HERE to THERE.

The follow-

! LDIR version:
LIl< R9,t/B
LDIR @RR12,®RR10,R9

5 cycles
~cycles

SB cycles

B.B us ®10 MHz or 1.B2 M bytes/sec

! LDM version:
LDM RO,@RR10,tIS
LDM ®RR12, RO,tIS

In this case, the LDM version is
version. Othe r differences are:
(1)
(2)

35 cycles
21...cycles
70 cycles

= 7.0

us ®10 MHz, or 2.29 M bytes/sec

faster--taking BO% of the

execut ion time

of the LDIR

The LDIR version uses R9 for a counter and modifies RR10 and RR12.
The LDM version modifies RO-R7 but leaves all other registers unchanged.

In some applications, the modification of RR10 and RR12 may be desirable, in others it may
not.
Figure 1:

LDM outperfoms LOIR in an 8-word transfer.

__ . _ - - - - - . _ - - - - -

4-75

Figure 2 shows s comparison of the methods in
moving a block of 128 words.
In this csse the
LDIR method is fsster, requiring only 1170 cycles
as opposed to the 1415 cycles required for the LDM
method. At clock rates of 10 MHz, the LDIR method
gives a transfer rate of 2.19M byt.es per second,
while the LDM method achieves a rate of 1.81M
bytes per aecond.

In aummary, for large or small blocks of data the
zeooo CPUa are
capable
of
effecting
memory-to-memory transfers at rates in excess of
2M bytes per second using CPU instructions,
without the need for a DMA device.

!Assume that RR12 contains the address THERE and RR10 contains the address HERE.
two following sections of Z8001 instructions moves 128 words from HERE to THERE.

Each of the

! LDIR version:
7 cycles
LD R9,#128
LDIR aRR12,@RR10,R9 --11Q..cycles
1170 cycles

117 us ®10 MHz, or 2.19 M bytes/sec

ILDM version:
LP:

LD R9,#16
LDM RO,®RR10,#8
LDM ®RR12, RO, #8
INC R11,#16
INC R13,1I16
DEC R9
JR GT ,LP

7 + 16 x 88

= 1415

7 cycles

~: ~~~~:}s

x16

4 cycles
4 cycles
6 cycle

cycles

= 141.5

us ®10 MHz, or 1.81 M bytes/sec

In this case, the overhead of the loop associated with the LDM version outweighs the speed
advantage of the LDM instruct ion.
In fact, even if the LDM version consisted of 16
repetitions of the sequence LDM, LDM, INC, INC (without the INCs an the fine! sequence), the
LDM version would still require 1240 cycles--70 more than the LDIR version.

Figure 2:

LDIR outperforRIa lDH in a 128-t1Ord transfer

4-76

00-2186-01

Zilog

October 1982

1315 Dell Avenue
Campbell, CA 95008
(408) 370-8000

CHARACTER STRING TRANSLATION:
Z8000 vs 68000 vs 8086
Task: Translate a string of 1000 characters from one code to
another, e.g., EBCDIC TO ASCII.

EXECUTION TIME (IlSEC)
(ALL CPUs AT 10 MHz)
5606

5042

4007
3604

2358

1404

LINES
BYTES

=9
= 17

8086

LINES
BYTES

=7
= 26

68000

LINES
BYTES

=4
= 16

LINES
BYTES

Z8000

= 12
= 26

8086

CASE 1: STRING LENGTH IS KNOWN

LINES
BYTES

= 10
= 36

68000

LINES
BYTES

=9
= 28

Z8000

CASE 2: STOP IF A SPECIAL CHARACTER
IS ENCOUNTERED

4-77

Prmted m U S.A

PROGRAM LISTINGS

Z8000·

8086

68000

CASE 1:
LO
LO
LO
TRIRB

MOVE.L

R3,H1000
R6,HSTRING
R8,HTABLE
@R6,@R8,R3

LE,~.L

LE.~.L

LOOP

CLR.L
MOVE.B
MOVE.B
OBF

H1000,03
STRING,A1
TABLE,A2
DO
(A1),00
O(A2,00),(A1) +
03,LOOP

LOOP

CLO
MOV
MOV
MOV
MOV
LOOSB
XLAT
STOSB
LOOPNZ

CX,1000
SI,STRING
01, SI
BX,TABLE

LOOP

"'.!..:J"
00

CASE 2:
LOB
LO
LO
LO
LO
LO
CPIRB
SUB
TRIRB

L ___

RLO,HEOS
R1,H1000
R2,R1
R3,HSTRING
R4,R3
R5,HTABLE
RLO,@R3,R1,EQ
R2,R1
@R4,@R5,R2

MOVE.L
MOVE.L
LEj~.L

LOOP
ENTER

LEA.L
CLR.L
BRA
MOVE.B
MOVE.B
CIVIP.B
OBEQ

HEOS,04
H1000,03
STRING,A1
TABLE,A2
DO
ENTER
O(A2, OO),(A1) +
(A1),00
04,00
03,LOOP

- - _ .. _ - -

·Code and timing applies to Z8001, Z8002, Z8003, and Zl3004.
For Z8001 and Z8003 in Segmented mode, add five P.SEIC, and four bytes.

LOOP
ENTER

CLO
LES
MOV
LOS
MOV
MOV
JMP
XLAT
STOSB
LOOSB
CMP
LOOPNE

OI,STRING
BX,TABLE
SI,STRING
CX,1001
AH,EOS
ENTER

AH,AL
LOOP

Z8002®CPU

Small SlDgl.·
Board Computer
Application
Note

Zilog

August 1982
The peripherals were chosen to demonstrate l-BUS
peripherals currently available (l-SCC, l-CIO, and
l-f 10) and because of their ability to support
functions necessary for running this system. The
l-SCC provides two channels of serial communications, one for a terminal and one for a link to
a host computer, such as the System BOOO/l-LAB.
The l-CIO and l-fiO are included so that the user
of this system will have one of each l-BUS
peripheral available on the board.

INTRODUCTION

This application note describes the design of a
system using a la002 CPU and l-BUS peripherals.
This system was designed to demonstrate that a
la002 system is easy to design and build, and to
provide a vehicle for the demonstration and evaluation of l-BUS peripherals. The system includes:

•

la002 CPU

•

l-SCC Serial Communications Controller

•

l-CIO Counter-Timer Parallel Input/Output Unit

•

l-fIO fIfO Input/Output Unit

•

l6132 Memory

•

2732 EPROM

The l6132 memories were chosen because they interface easily to the la002 and provide 4K bytes of
storage per package. In a simple system such as
this, large amounts of dynamic RAM would be overkill. The l6132 provides all the storage needed
in a convenient, easily interfaced device.
The 2732 EPROM was chosen because of its density
and speed. The 2732 is twice as dense as a 2716
and is availab Ie in higher speeds than the 2716.
The higher speed EPROMs would be necessary if this
system were to operate at 6 MHz.

Basic goals of this system design were:
•

It should be simple, with minimum parts count.

•

It should use l-BUS-compatible
wherever possible.

•

It should be expandable

The system was designed to allow the use of a
modified
software
monitor
from
the
la002
Development Module.
Modifying the Software
Monitor is accomplished by simply rewriting the
serial I/O drivers for connection to a l-SCC
rather than a laO SIO, and by rewriting the
single-step code, which uses different hardware in
the new sytem. Starting from an existing monitor
considerably reduced the time necessary to
complete the software.

components

With these goals in mind, the next step in the
system design was to select the major devices in
the system.

HARDlfARE DESIGN

The la002 CPU was selected because of its high
performance and because its 64K byte addressing
range capably handles this application.
This
allows a system that is hardware compatible with
all l-BUS peripherals and memories, and thus keeps
the system cost down.

The laOOO CPU architecture is based on the machine
cycle as its fundamental unit of execution. All
hardware interface logic must be aware of what
kind of machine cycle is being executed so that,
for example, operations intended for memory affect

4-79

memory only, and not input/ouput devices.
In
order to differentiate between the different
machine cycles, logic was included in this system
to decode the four CPU status linas, ST O-ST 3 , and
to produce status signals to be used in other
parts of the system.

ADO.
In essence, for byte write operations,
ENAEVEN is active if ADO = 0 and ENAODD is active
if ADO = 1. For any other operation, both outputs
are active. This decoding is necessary because,
for byte write operations, however, the data
appeara on both halves of the Address/Data bus, so
there muat be some way of allowing writes to only
one bank of the memory.

STATUS IlECODIt«i
U37 (see the schematics attached to end of
application note) is an octal decoder (74LS138)
that decodes the first eight status codes (those
codes for which ST 3 = 0). Two sections of U15 (a
74LSOO) are used to derive a signal called MREF
which is valid for any memory access, regardless
of the type of address space (code, data, or
stack).
MREF is represented by this logic
equation:

The RAM chip select logic is composed of two
74LS138 decoders: one for the even byte (U4) and
one for the odd byte (U3). The decoders have as
inputs the uppermost three address bits (AD15AD13) , the MREF signal decoded from the status
lines, and either ENAEVEN or ENAODD. Each Z6132
is connected to one of these chip select lines,
depending on the address desired and whether it is
the even or odd bank device for the address.

EPROM INTERfACE
It would have been possible to include another

74LS138 to decode the upper eight status codes and
to OR the three status codes for code, data, and
stack memory accesses, but that would have added
additional chips, and would have been contrary to
the goal of minimum chip count.
In addition to
this status decoding, one section of U15 and thrae
sections of U16 (a 74LS32) are used to generate a
signal that is the combination of Data Strobe from
the Z8002 and a status signal for stack references. This signal is used to drive the singlestep logic, which is discussed later.

The EPROM interface logic is simpler, because the
EPROMs have no requirement for even/odd bank
select because they do not respond to write
operations. The EPROM chip selection is done by
U5, a 74lS138 decoder. This decoder is enabled by
the MREF signal and uses as select inputs
AD15-AD13 (the 2732s are 4K x 8 devices).
This
gives EPROM select signals that allow EPROMs to be
placed anywhere within the 64K byte address space
of tha Z8002.
Because there is no even/odd
selection, both even and odd byte devices at a
given address are wired to the same EPROM select
signal.

MEJlJRY INTERfACE lOGIC
WAIT STATE GENERATION

The memory interface logic is divided into two
major parts, the RAM interface (for the Z6132s),
and the EPROM interface (for the 2732s).

RAM INTERfACE
The RAM interface logic consists of even/odd bank
decoding, and chip select decoding. The even/odd
bank selection is done by one half of a 74LS157
multiplexer (U12).
It takes as its inputs the
byte/word signal (BiW) , the read/write signal
(R/II) , and Address/Data bit 0 (ADO) from the Z8002
CPU.
For any read operation, both outputs are
active.
For write operations, if the byte/word
line indicates a word write, both outputs are
active. For write operations in which the byte/
word line indicates a byte write, only the even or
odd output is active, depending on the state of

To accomodate slower memory devices, which are
often used for reasons of cost, separate wait
state generators are included for the RAMs and for
the EPROMs. Each generator takes the chip select
signals used on the board and ORs them together.
This ORed chip select is then gated with Address
Strobe (active High).
The resulting signal
presets a 74LS74 flip-flop, causing the If output
to go low. This signal is used as the wait input
to the CPU. The first falling edge of PClK clocks
the flip-flop with the "0" input Low, causing the
Q output to go High again.
This allows the
generated wait signal to be recognized once,
adding one wait state to that memory access. The
outputs of both wait state generators go through
OIP switches to two sections of a 74LS32 , which

4-80

combines these wait aignals with the BUSY outputs
of the Z6132s into one WAIT output that is fed to
the WAI T input of the ZB002. The BUSY outputs of
the Z6132s must be included because they may need
to generate one or more wait states in order to
perform their internal refreshing.
The DIP
switches allow the user to select one wait state
for RAM accesses, EPROM accesses, or both. More
elegant wait-state generators sre possible with
selectsble numbers of wait states, but the single
wait state circuits were used because of their low
psrts count and simplicity.

several devices interrupt at the same time.
In
order to allow experimentstion with different
interrupt input to the CPU (in this case VI, the
vectored interrupt input, was used), and the
interrupt acknowledge back to the peripherals
(VIACK).
The interrupt input is a wired-ORed
signal, since all peripherals have open-drain outputs for this s~gnal. The interrupt acknowledge
output of the status decoder is used to feed all
of the peripherals; the priority daisy chain
resol ves for which peripheral the acknowledge is
intended.

SINGlE-STEP LOGIC
PERIPIERAl INTERFACE
The single-step logic is composed of three flipflops (U22 and U2S).
The single-step logic is
enabled ("armed") by writing to an I/O port
address (in this case F900). Writing to this port
address sets the first flip-flop (which is connected as a set/reset latch). This then enables
the chain of two flip-flops (U28) to count stack
operations. Several gates are used to generate a
signal vslid for any stack reference; this signal
is ANDed with Data Strobe.

Using Z-BUS-compatible peripherals eliminates all
external interface logic except the chip select
circuitry.
This function is handled by U21 and
U6. U21 is used to detect the case in which the
upper-most five address bits are all 1s.
This
signal is fed into one of the enable inputs of U6,
a 74LS13S decoder. This decoder is also enabled
by the status line indicating an I/O machine
cycle. This one decoder gives eight chip select
signals derived from the upper eight bits of the
Address bus. Because Z-BUS peripherals are bytewide devices on the low byte of the Address/Data
bus, it is wise to perform the chip selection with
the bits not used by the peripheral for addressing
internal registers.
By selecting only on the
basis of the upper eight bits, the design avoids
conflict with any peripheral, because one device
may use the lower six bits while another may use
the lower seven bits. To make these chip select
signals compatible with other devices, the latched
address lines LAS-LA15 are used to drive the
decode logic. In this wsy the chip select outputs
are valid throughout the machine cycle.
Z-BUS
peripherals latch the chip select input on the
rising edge of Address Strobe, so a longer chip
select signal is not necessary. However, because
compatability with devices other than Z-BUS parts
is desirable, and, because using the longer cycle
does not add any additional logic (the latched
addresses are already needed for addressing the
EPROMS), the longer chip select signal was
incorporated.

The instruction sequence for single-stepping is to
arm the chain with an I/O write to the single-step
port and to follow this instruction immediately
with an Interrupt Return Instruction (IRET). The
stack has already been set up to return to the
next instruction in the user program.
The two
stack operations in the IRET instruction are
counted and a nonvectored interrupt is genersted.
This interrupt is not generated until the rising
edge of Data Strobe during the last machine cycle
of the IRET instruction, so it is not recognized
during that instruction. It is recognized during
the next instruction, which is the next instruction of the user program.
This instruction
executes to completion, and then the interrupt
acknowledge sequence starts.
After one instruction of the user program is
executed, control is returned to the monitor.
This allows user instructions to be executed one
at a time under softwsre control. This method of
single instruction execution was used instesd of a
method that uses hardware control of the CPU so
that the monitor could be used to examine and
alter memory and register contents between
execution of user instructions.

INTERRUPTS
Proper interconnection of Z-BUS periperal interrupt signals is easily accomplished with the logic
already in the system.
The Z-BUS interrupt structure is based on a priordaisy chain for resolving conflicts when

In the hardware design of this system, an
important question was whether or not to buffer

ity

4-81

[ ]

the Address/Data bus and the control signals.
Several items were considered in order to answer
this question.
When considering the de loads on the CPU outputs,
the only devices that present significant dc loads
are the "LS" series devices.
A l8002 output
drives at least four LS-series inputs.
The
memories and peripherals are all MDS devices, and
as such have negligible dc loading.
The capacitance of inputs is another item that
must be considered. The outputs of the lB002 are
specified at a capacitance of 100 pF, so that the
sum of the input capacitances of the devices on
the bus must be less than 100 pF.
The memory
devices have a 5-10 pF input capacitance and the
peripherals are typically 10-15 pF.
With the
number of peripheral and memory devices in this
system, there is no problem driving these inputs
directly from the l8002.

Square brackets are used to denote optional
quantities, and are not actually to be
entered.
Bar is used to denote "OR." For example,
WIB means either of the characters W or B
may be used.

(CR)

Carriage return.

All commands can be abbreviated to their first
letter.
Commands and options can be entered in
either upper or lower case.
All numbers are
represented in hexadecimal notation and must begin
with a numeric digit.
The first character typed
on a new line identifies the command being invoked.
If the command is not understood, a"?"
is printed on the terminal and a new command is
requested.

SIMtARY IT COIIWI)S:
Considering the present loading, the status and
control signals were buffered by a 74LS244, although Address Strobe, Data Strobe, and read/write
also go directly to the peripherals.
The status
outputs are fed to a number of LS-series devices,
so buffering helps the loading here.
Status is
not critical to timing, so the small delay the
buffer introduces has no effect. The Address/Data
bus was not buffered so that slower access time
memories could be used, but if the system were
expanded, ~t would be adv~sable to buffer tne
Address/Data lines with 74LS245 bidirectional
buffers.

BREAK []
Set and clear breakpoint.
COMPARE
Compare memory blocks.
DISPLAY []
[LjWIB]
Display and alter memory.
FILL
Fill memory.

GO
SOFTWARE DESIGN

Branch to last PC.

The monitor on the l80D2 Small Single Board
Computer (SSBC) is a modified version of the
monitor used on the lilog lB002 Development
Module.
The commands are the same, except that
the TAPE and PUNCH commands have been deleted.

10PORT [WIB]
I/O port read/write.
JUMP
Branch to address.

The syntax interpretation for l8002 SSBC monitor
commands is:

LOAD
Load file from host system.
MOVE
Move memory block.

The following notation
descriptions:

used in

the command

Angle brackets are used to enclose descriptive names for the quantities to be
entered, and are not actuall y to be
entered.

NEXT []
Step instruction.
QUIT
Enter transparent (terminal) mode.

4-82

specifies the number of bytes to be
compared.
If any locations of the two blocks
differ, the addresses and contents of those
locations are displayed on the terminal.

DISPlAY
NOTE
All outputs in monitor mode can be suspended with the XOFF character (CONTROL
S), and resumed with the XON character
(CONTROL Q).

Syntax:
DISPLAY []
[qWIB]
Description :

CIJMIWI)

OCSCRIPTIONS:

Displays the contents of specified memory
locations on the terminal, starting at the given
address, for the given number of bytes.

BREAK

If the number (#) of long words/words/bytes
parameter is specified, the contents of the
desired locations are displayed, both in hexadecimal notation and as ASCII characters.

Syntax:
BREAK []

Daacription

If the number of long words/words/bytes is not
specified, the memory locations are displayed
one at a time, with an opportunity to change the
contents of each location. For each location,
the address is displayed, followed by the
contents, followed by a space. If the contents
at that location must be changed, the new
contents are entered at this time. A carriage
return, either alone or after the new contents,
causes the next sequential location to be
displayed.

The BREAK command is used to set a breakpoint at
the given even address.
If n is specified, the user program execution
is not interrupted until the nth time the
breakpoint instruction is encountered. The value
for n should be in the range ~0001 - ~FFFF. If
n is not given, 1 is assumed. If the BREAK command is issued with no parameters, it clears any
previously set breakpoint. This action should
be performed before setting the current breakpoints.

If the [LIWIB] parameter is not specified, data
is displayed in word format.

When user program execution is suspended by the
BREAK command, the monitor prints a message
informing the user of the break and the address
at which it occurred.

A "Q" followed by a carriage return terminates
the command.

F"lLL

Syntax:
FILL

Syntax:
COMPARE

Description:
Description:

The FILL command is used to store the given data
word into sequential memory locations starting
at up to and including .
The command addresses must be even hexadecimal
numbers.

The COMPARE command is used to compare the contents of two blocks of memory.
Locations and specify the
starting addresses of the two blocks of memory;

4-83

that

Syntax:
GO

the FCW is set to an appropriate value.

LOAD DATA FROM IIlST

Description:

Syntax:
LOAD

This command is used to branch to the current
PC, thus continuing program execution from where
it was last interrupted.

Description:
This command is used to download a ZBOOO program
from a host system into the SSBC memory.

All registers and the FCW are restored before
branching.
Before executing a GO command,
ensure that the FCW is set to the appropriate
value.

The monitor program transmits the command line
to the host system exactl y as entered.
The
monitor assumes the host system recognizes this
command line.
When the SSBC is connected to
either a PDS-BOOO or a System-BOOO, this command
causes the file to be opened, the
data is converted to Tektronix hex format and
transmitted to the SSBC.

IOPORT
Syntax:
IOPORT [WIB]

Description:

The monitor program verifies the two checksum
values in each record and stores the data in RAM
memory at the address specified in the record.
An acknowledgement from the SSBC causes the host
to send the next record.

This command is used to read data from the given
port address, display the data on the terminal,
and write new data to that port address.
After the current port data is displayed, the
user can either enter a "Q" followed by a
carriage return to terminate the command, or
enter a series of bytes or words (maximum 12B
characters per line). Bytes or words should be
blank delimited with a carriage return at the
end.
This allows multiple writes to a port
without scrolling the terminal screen excessively. If the [W\B] parameter is not specified,
byte data is read and written to the I/O port.
If a carriage return alone is entered, a zero
value is written to the port.

A non-acknowledge from the SSBC causes the host
to retransmit the current record up to 10 times,
after which a record with an error message is
sent and the command aborted.
After successful completion of the loading
process, the entry point received in the last
record is printed on the terminal.
An ESCAPE
key is used to abort the LOAD command. Any set
breakpoints from a previous program must be
cleared before loading a new program.

IIlV[
JlIoIP

Syntax:
MOVE

Syntax:
JUMP

Description :
Description:
This command is used to move the contents of a
b lock of memory from the source address
specified by to the destination
address specified by . The value
is the number of bytes to be moved.

The JUMP command is used to branch unconditionally to the given even address.
All registers and the FCW are restored before
branching.
Before executing a JUMP, ensure

4-84

•

Program counter register named RPC

Syntax:
NEXT []

•

Flag and control word register named RFC

Description:

I f no register name is given, the contents of
all registers are displayed. If a register name
is given, the specified register name is displayed, followed by its contents, followed by a
space.

The NEXT command causes the execution of the
next n user instructions, starting at the
current PC, and displays the contents of all
registers after each instruction is executed.

If the contents of that register are to be
changed, the new contents can be entered at this
time. A carriage return, either alone or after
the new data, causes the next register.

The value should be in the range %001 %FFFF. If is not specified, 1 is assumed.

A "Q" followed by a carriage return terminates
the command.

QUIT

Syntax:
QUIT
SEN> DATA TO IIlST

Description:
Syntax:
SEND
[]

The QUIT command is used to enter the
Transparant IIKlde (terminal mode) from Monitor
mode.

Description:

In Transparant IIKlde, all keyboard input is
passed to the host serial port, and all input
from the host serial port is passed to the
terminal. The baud rate of the host serial port
is controlled by three switches of the eight
position DIP switch (U11).

The SEND command is used to transfer the contents of memory of the SSBC to a file on the
host system.
The monitor sends the command line to the host
system exactly as received. The SEND command on
PDS-8000 or a System-BOOO opens a file name
and sends an acknowledge (ASCII 0) to
the SSBC to start transmission.

The NMI switch on the SSBC is used to return to
Monitor rode.

If the file cannot be opened, an abortacknowledge (ASCII 9) is sent to the IIKlnitor and
the SEND command is aborted.

Syntax:
REGISTER []

The monitor formats the contents of memory specified by
into Tektronix hex format and transmits this
data to the host system. The monitor then waits
for an acknowledge before sending the next
record.

Description:

The REGISTER command is used to examine and
alter registers.
The following are valid register names:

•

Any of the sixteen 16-bit registers named
RO' R1 , R2 ···R 15

•

Any of the sixteen 8-bit registers named
RHO' RLO' RH1' RL1 ••• RH7' RL7

•

Any of the eight 32-bit registers named RR O'
RRZ' RR4 ••• RR14

A nonacknowledge (ASCII 7) received by the
roni tor causes the same record to be resent up
to ten times. If this record is still not sent
successfully, a record with double slash
characters (II), followed by a carriage return,
is sent to the host system to abort the SEND
program in the host. The two slash characters
are also sent if the ESCAPE key is pressed by
the user to abort the SEND process.

4-85

The address specified by is sent
in the last record as the entry address for that
file.
If no entry address is specified, an
address of %0000 is assumed.

For records with error .essages:

I f either the host system or the SSBC aborts a
LOAD or SEND process, it may send a record of the
form:

RECORD FORMAT FOR lOAD/SEMl COtI4AN)S:

The record format for the LOAD and SEND commands
is Tektronix hex format, which uses ASCII characters only.
Each record contains two checksum
bytes, a starting address, and a maximum of 30
bytes of data. The format of the record is shown
below:
For Records 1 to n:
/00«CR>
t«JNITOR I/O PROCEDURES

The starting address for the
program (4 ASCII characters).

The SSBC monitor contains subroutines to do
character I/O to and from the terminal.
These
subroutines can be called by a user program in
order to do terminal I/O. A description of each

The checksum for the entry
address (4 ASCII characters).

4-86

string is stored in a buffer pointed to by R2. R1
contains the size of the buffer.
If the size of
the string received exceeds the size of the
buffer, the zero flag is set.
All lower case
alpha characters are converted to upper case
before being stored in the buffer. R1 returns the
actual number of characters received from the
terminal.
The contents of RO and R2 are destroyed.

subroutine follows, along with detai Is of which
registers, i f any, are affected by calling the
routines. The hex address in parenthesis next to
the subroutine name is address to which the user
should do a CALL instruction to use that routine.
For example, to output a carriage return and line
feed to the terminal, a user should execute the
following instruction:
CALL

%OFD4

!output CR/LF.

RO is lost

CRlF (S0FD4)
TYIN (W"AO)

Output a carriage return followed by a line feed
to the terminal. RO is destroyed.

Get a character from the keyboard buffer. If the
buffer is empty, this procedure waits for a character to appear. The character is stored in RLO,
and the contents of RHO are destroyed.

EXPANSION
Chip decoding for extra EPROM and RAM and I/O
devices exists.
To connect additional Z-BUS
peripherals, for example, the device is wired to
the Z-BUS signals required and an unused chip
select line is connected to the chip select input
of the peripheral. Other peripheral devices can
be connected, but they may require additional
circuitry in order to interface to the Z-BUS.

TYWR (SlFC8)

Display a character in RLO on the terminal.
The
character is not displayed if the XOFF character
is received before this procedure is executed.
This procedure waits until an XON character is
received to display the character in RLO. If the
display character is a carriage return, the zero
flag is set and RHO is destroyed.

Additional Z6132 RAM devices can be connected
directly to the Z-BUS In parallel with the
existing RAMs; the only difference being the chip
select lines, which should be selected from
currently unused outputs.
Extra [PROMs can be
added in a similar manner. There is enough EPROM
decoding to fill the entire 64K byte address space
with 2732 EPROMs, and enough RAM decoding to do
the same with Z6832 RAMs.
The user can select
either RAM or [PROM.

PUTMSG (W"CO)
Send a character string to the terminal. Register
R2 should contain the address of the character
string buffer, and the first byte in the buffer
should be the number of characters to be displayed.
If there is no carriage return in the
string, the entire string specified is displayed,
otherwise the string is displayed up to and
including the first carriage return.
Registers
RO, R1, and R2 are destroyed.

Any expansion beyond two additional peripheral
chips should be accompanied by the addit ion of
74LS245 buffers on the Address/Data lines.
Buffering is already present on AS, 65, R/W, B/W and
STO-ST 3.
If 74LS245 buFfers are added, their
direction should be controlled so that they drive
from the CPU to the outside world except during
the time that Data Strobe is active during a read
operation.

TTY (W"OC)
Receive and echo at the terminal a line of characters up to the first carriage return.
The

4-87

Vee

[8[El

WAiT

p..---!
V"

dp,CS
st

~
~

Nel

~
~

BUSACK

AD'
AD.

NMi
%S002
CPU
U32

NVl

:CL~l

- '"

AD3
AD'

AS~

~15

B/W----.!
STO....!.!

MREO

f1!-

ST3....!!

740$244
U20

ST2~

~NIS

r!!- ST2

U"
,
,

,
p.!.!... REFRESH

J1-- BST3

MREF

~N'MiAci(
bLNVIAC~

9
10 U15

.sn

~
2 U15

U36

F9~~'

.~
,

BRIW'3U160

p,
74U74
U22

-=- L-.....!.Y

4U166'~U168

....

,,'

ADD~HES

(...1!.

D7 U26 07

I....!!.

06"

03 •

I....l.
I....!

,....

l-l.

U13

0'
DO
G
U

,."

LA14
LA13

oe00

3
4

G23

RAM80

RAilAO

Q~O

r 1f ,,"
74U74
U28

--!.

LS30

ADDRESS SELECTED

"t!-

1.-1

LAU

LS13S
15
U6 VO ~ F8XX

G2A

Y1
Y2
V4

l.-1

00 f!-!-- LAO

~+--LA1

d
_

G1
G2A
G2B

L$157
U12

G
lSI

S
t

BRIW
ADO

SINGLE-STEP CIRCUIT

Figure 1a.

SS8C Sc'-tic

"""

'ECODES
STARTING ADDRESS

f""L'S1'3'i"

PROMO

10::- PR"OM2

p.!!- PROM4

Y3~

PROM6

PROM8

P:::-

V51o::!- PROMA

Y6~

"""'"

Y7P!- PROME

-=-

IIOIJ

L...---EPRlL
i
p,:.:-i"""'"

V2~iRAM40

AD'
AD'

ADO-A07

p..!!-SG'fACK

'---

Y3 p..!!-IIO REF

L$13S Y3 p..!LSPEC
U37 Yo4
G1

G24

l..!l

"pLv,.e,
STA~DING

ENAEVEN

I....!!.
~ I....!!

B5T2

b-!!- iNrOP

A09
AD.

85TO

{~B

AD13·

BST1

~BSTO
~BST1

I......!.

C
U3 YO
1!2!U I"""'Li"i3s

RAM03

AD"

.--

f---2 C
~a
f-.c---2 A

~
~RAM2E

Y2~1'i.AM4E

Y3p.!!..ii1i:tm:

P-BST2

BST3

...---

ST3 p!....ST3

ClOC~

U4 YO

1E · :.~= #·

t1!- BBIW

m ~ST1
S"

aNi ~BJW
STO ~STO

.'V

RJW ~RJW

GND

AOO·AD7

"
Os r!!-os

Nis

tlLBAS

~BDS
~BRiW

ST1....E

fE-

...---

os~
RJW""'!

r!l-

AD'

ADO

~ MO

K1160A
4MHz.

,j>.

BUSREQ

~ Mi

Vec~
14

....

V"
U3S

AD1.

RESET

fL
AD13
fL
A012 tL
AD11
fL
A010 tL
A09
PAO. t1L
AD' f1!-AD,
f2!A015

WAIT

NOr--

HF...-.;rn-

Vee

>,--,-p!-- ENAODO

~
§

~-----------------------------------,
RAMPR

018 PROM~IT

AD15-

1
._j

AD14AD13AD12AD11
ADtO

'.--

,,-'2--

,-,--

8171615141312

AD'
AD, I I I I I I I I I I I
AD,
lAD<
AD2
AD'
ADO

13--

"IBUHnlJ."'"

7'~!"

4 7k 18 PLACES)
U11

1111111111111111
v"

-.l>'

'----------

RAM" =r§20 'lLS20
~
~
PCLK

,:,,'9

.I1111111111~ -I:

2732
1000)
U2'

J cs
v"

LSOO
.. __

22oA'
t9° A

D6l..!!
111

LA12

iiRi

RAM40_

PROMO.

Z6132
1000)
U8

Att

D2~

I I I I I I 'lA'
(:~~I
2
U30

'~~+=~=t+t!:j=±±±±=[3j~AlO
~~

U17

lAl0

I" 1111111 IIIIII III ::1:
I: 1111111111111111 ~I::A.

RAMeE

DO"
01~

~CE

I: I I I I I I I II I I I 1II I :1::

RAM60

I I I I I I I I II I I I I I I 1:1;

1111111 III (

~WAO

U36

1"BUSY

1 1 1 1 1 1"1 __

"'"
00

p.:

I 11111111 I I I I II II I I I I I

RAM6E

18 CE

0'
D>

• A'
7 .,

05 22

cD
0

BUSY

26.1£

CS 20
AO 10

22 OS

l2!!

• A4
3 AS

BUSY

2 AS

10 AO

'A7

~:rIJ:r

LA12

Z6132
HIGH-BYTE

Z6132
LOW.BYTE

(ODD)

3 .7

(EVEN)

25 . .

U1.

,
"

~~
'

• A4
3 AS

15 03

'A7

2 AS

"1M

22.,

t:l
~
g

Figure 1c.

00 '

SS8C Sct.e.atic

AtO

A11

f1!L

p!-

oat!!-

00
D1
13 02

17 05

~A8

f-!!

L--...-...l

AtO

U.S

S AD

23 All

"~
"05 t!!t!!-

(ODD)

18 CE

2. A9
21

2732
LOW·
BYTE

,
~

04~

2732

rtL

H'
....
BYTE D6~
(EVEN)

U31

01,

~.-£ ~§~~~~~~~

r. rc

'" 5! ....

11:1<

~::j

"1,1

2~o
~;g

01-

.1.1. .

...

,t;--" ~§ ~ ~ ~ ~ ~ ~ ~

••• ••
I~ I~ '~

C~~ ~ I~ I~ I~ ~ Ii I~ I~ I~

I~
o

•0

.1.1

~ ~

•

gl~
~~:I

•

1"1"1"1"1~nnuu~

~~I!:~~~SIit;g

."~,~

" " " '1'1 01 " • , • •
~

. .

• .

• "1"1

1£1

~1 ~1 ~1 ~1 ~
~~ § ~~ . I~ I~ It ~
g
~ ~ig) !!g ~J

;! ~;!

"' ...

. .

:g:: .. .... I'>

•

"'5!

g r!t~

~:?~~

.
. . . " .
:1 ~1 ~1 ~1 ~1 ~1 ~1
~ I~
I!'.~~.: ;!; J'" J'~'i "
~.7;;
,
N

"':=!

:W' . l

W!Ii

":l

... ::0

- -

...11
;;-" ~

'~'~~~~~§~~§l~'>

00-2264-01

••

§~~§~~~~

[, :~ .~ "~ .~ .~ .~ "~ .~

...
I~

l:g

•••
I~

~ ~

-,1·-

•

"0'
':';:1

~ f ~

~ ~ ~ ~

"1"1 "1"1 "1'1"1 °1'1 "1'1"1
4-91

• , "0'0'
1'...
.1
;
~5~

~ ~

ei . .

~ ~

.~...

f;!

r:.N

iii

..?010°.° ...°
I

!0=.

:!~

Interfacing the Z8500
Peripherals to the 68000
Application
Note

Zilog

October 1982
INTRODUCTION

the Z8500 interface itself. It shows how the different ZB500 control signa Is are generated from
the 68000 signals and summarizes the critical timings for the three types of bus cycle. The third
section shows three examples of implementing the
68000-to-Zilog-peripheral interface.
The fourth
section suggests methods of verifying the interface design by checking the three different types
of bus cycle: Read, Write, and Interrupt Acknowledge.

This application note discusses interfacing
Zilog's Z8500 family of peripherals to the 68000
microprocessor.
The Z8500 peripheral family
includes the Z8536 Counter/Timer and Parallel I/O
Unit (CIO), the Z8038 FIFO Input/Output Interface
Unit (FlO), and the Z8530 Serial Communications
Controller (SCC).
This document discusses the
Z8500/68000 interfaces and presents hardware examples and verification techniques.
One of the
three hardware examples given in this application
note shows how to implement the Z8500/68000 interface using a single-chip programmable logic array
(PAL) •

GENERAl Z8500 fAMILY DESCRIPTION
The Z8500 family is made up of programmable
periphera Is that can interface easily to the bus
of any nonmultiplexed CPU microprocessor, such as
the 68000. The three members of this famil y, the
CIO, SCC, and FlO, can sol ve many design problems.
The peripherals' operating modes can be
programmed simply by writing to their internal
registers.

This application note about interfacing supplements the following documents, which discuss the
individual components of the interface.
•

Z8036 Z-CIO/Z8536 CIO Technical Manual (document number 00-2091-01)

•

Z8038 Z-FIO Technical Manual (document number
00-2051-01)

•

Z8030/Z8530 SCC Technical Manual (document number 00-2057-01)

•

Motorola 16-Bit Microprocessor User's Manual
3rd ed. Englewood Cliffs, N.J., Prentice-Hall,
Inc. 1979.

•

Progr~ng

the Operating Hodes

The CPU can access two types of register: Control
and Data. Depending on the peripheral, registers
are selected with either the AO' A1' A/B, or D/f
function pins.
Peripheral operating modes are initialized by
programming internal registers.
Since these
registers are not directly addressable by the CPU,
a two-step procedure using the Control register is
required: first, the address of the internal register is written to the Control register, then the
data is written to the Control register. A state
machine determines whether an address or data is
being written to the Control register. Reading an
internal register follows a similar two-step

Monolithic Memories Bipolar LSI 1982 Databook

This application note is divided into four sections. The first section gives a general description of the Z8500 family and discusses pin functions, interrupt structures, and the programming
of operating modes. The second section discusses

4-93

procedure:
first, the address is written, then
the data is read.

be connected to the 68000 A1 and A2 Address bus
lines.

The Data registers that are roost frequently
accessed, for example, the SCC's transmit and
receive buffer, can be addressed directly by the
CPU with a single read or write operation. This
reduces overhead in data transfers between the
peripheral and CPU.

DE.
Each peripheral has an active Low Chip
Enable that can be derived by ANDing the selected
address decode and the 68000's Address Strobe
(AS). The active Low AS guarantees that the 68000
addresses are valid.
00-07'
The Z8500 Data bus can be directly connected to the lowest byte (00 -07) of the 68000
Data bus.

GENERATING Z8500 CONTROL SIGNALS

This section shows how to generate the 18500 control signals.
To simplify the discussion, the
section is divided into two parts. The first part
takes each individual 18500 signal and shows how
it is generated from the 68000 signals.
The
second part discusses the 18500 timing that must
be met when generating the control signals.

I£I and lEO. The peripherals use these pins to
decide the interrupt priority.
The highest
priority device should have its lEi tied High.
Its lEO should be connected to the lEI pin of the
next highest priority device.
This pattern
continues with
the
next
highest
priority
peripheral, until the peripherals are all
connected, as shown in Figure 1.

Z8500 Signal Generation

The right-hand side of Table 1 lists the 18500
signals that must be generated.
Each 0 f these
signals is discussed in a separate paragraph.
AO' A1' AlB, D/C. These pins are used to select
the peripheral's Control and Data registers that
program the different operating modes. They can

Table 1.

INT. The interrupt request pins for each peripheral in the daisy chain can be wire-ORed and connected to the 68000's ILP n pins.
The 68000 has
seven interrupt levels that can be encoded into
the ILPO' ILP1' and ILP 2 pins.
Multiple 68000
interrupt levels can be implemented by using a
multiplexer like the 74LS148.

Z8500 and 68000 Pin Fmet ions

68000 Signals
Mnemonic

A1- A23

CLK
DO-D15
DTACK
FCO-FC2
ILPO-ILP2
R/W
VMA
VPA

Z8500 Signals
Function

Address bus
Address Strobe
68000 clock (8 MHz)
Data bus
Data Transfer Acknowledge
Processor status
Interrupt request
Read/Write
Valid Memory Address
Valid Peripheral Address

FlWlCtion

Mnemonic

AO,A1,A/B,D/E*
CE
00- 0 7
lEI, lEO
INT
INTACK
PCLK
RD
WR

Register select
Chip Enable
Data bus
Interrupt daisy chain
control
Interrupt Request
Interrupt Acknowledge
Peripheral Clock
Read strobe
Write strobe

* The register select pins on each peripheral have different names.

4-94

INTACK. The INTACK pin signals the peripheral
that an Interrupt Acknowledge cycle is occurring.
The following equation describes how INTACK - is
generated:
INTACK

The Read strobe timing must meet both the Read
timing and Interrupt Acknowledge timing discussed
in the following section. In addition to enabling
the Data bus drivers, the falling edge of RD sets
the Interrupt Under Service (IUS) bits during an
Interrupt Acknowledge cycle.

= (FCO)·(FC,)·(FCZ)·(AS)

The 68000 FCO-FCZ are status pins that indicate an
Interrupt Acknowledge when they are all High.
They should be ANDed with inverted AS to guarantee
their validity.
The INTACK signal must be synchronized with PClK to guarantee set-up and hold
times.
This can be accomplished by changing the
state of INTACK on the falling edge of PClK.
If
the INTACK pin is not used, it must be tied High.

WR. This signal strobes data into the peripheral.
A data-to-write setup time requires that
data be valid before WR goes active low.
The
equation for generating the WR strobe is made up
of two components: an active reset and a normal
Write cycle, as shown in the following equation:

POLK.
The SCC and CIO require a clock for
internal synchronizstion.
The clock can be
generated by dividing down the 68000 ClK.

Forcing RD and WR simultaneously low resets the
peripherals.

WR = [(R/W)·(AS) + RESET]

Z8500 Tiaing Cycles

RD. The Read strobe goes active low under three
conditions:
hardware reset, normal Read cycle,
and an Interrupt Acknowledge cycle. The following
equation describes how RD is generated:
RD

= [(R/W)·(AS)

This section discusses the timing parameters that
must be met when generating the control signals.
The Z8500 family uses the control signals to
communicate with the CPU via three types of bus
cycle:
Read, Write, and Interrupt Acknowledge.

+ RESET]

+6V

1------1 lEI

1 - - - - -....

lEO

Z8500

Z8S00

(FIRST)

(MIDDLE)

PRIORITY

__________________________--Jr--\\-______---1rt ••Hle(NS)
PERIPHERAL

«MHo)
CIO
FlO
SCC

Figure 1.

2267-001

(LAST)

PERIPHERAL

lEO

zeloo

LOWEST

HIGHEST
PRIORITY

PCLK

lEI

FIRST
3SO

35.

26.

MIDDLE
150
160
120

LAST
100
100

Peripheral Interrupt Daisy Olain

4-95

The discussion that follows pertains to the 4 MHz
peripherals, but the 6 MHz devices have similar
timing considerations.

Write Cycle

The Write cycle transfers data from the CPU to the
peripheral. It begins by selecting the peripheral
and addressing the desired register. A setup time
of 80 ns from register select stable to the
falling edge of WR is required. The data must be
valid prior to the falling edge of WR.
The WR
pulse width is specified at 400 ns. Write cycle
timing is shown in Figure 2.

Although the peripherals have a standard CPU
interface, some of their particular timing
requirements vary. The worst-case parameters are
shown below; the timing can be optimized if only
one or two of the Z8S00 family devices are used.
Read Cycle

Interrupt Acknowledge Cycle

The Read cycle transfers data from the peripheral
to the CPU. It begins by selecting the peripheral
and appropriate register (Data or Control). The
data is gated onto the bus with the RD line.
A
setup time of 80 ns from the time the register
select inputs (AlB, cID, AO' A1) are stable to the
falling edge of RD guarantees that the proper register is accessed. The access time specification
is usually measured from the falling edge of RD to
valid data and varies between peripherals.
The
SCC specifies an additional register select to
valid data time. The Read cycle timing is shown
in Figure 2.

The Z8S00 peripheral interrupt structure offers
the designer many options. In the simplest case,
the Z8S00 peripherals can be polled with interrupts disabled.
If using interrupts, the timing
shown in Figure 2 should be observed. (Detailed
discussions of the interrupt processing can be
found in the Zilog Data Book, document number
00-2034-02.) An interrupt sequence begins with an
INT going active because of an interrupt condition. The CPU acknowledges the interrupt with an
INTACK signal.

ADR

READ
CYCLE

DATA OUT

\_>400_/
--l I- >0

WRITE {

CYCLE

DATA IN

---<

-I

VALID DATA

1-->0
)

~>ot_

IIITACK
INTERRUPT
ACKNOWLEDGE
CYCLE

--------

<300

DATA IN

Figure 2.

I( VALID DATA )

Z8500 Interface Timing (4 Itlz)

4-96

2267-002

A daisy-chain settle time (dependent upon the number of devices in the chain) ensures that the
interrupts are prioritized.
The falling edge of
RD causes the IUS bit to be set and enables a
vector to go out on the bus.

Zilog's 4 MHz Z8500 peripherals to an 8 MHz
68000. Faster CPUs or peripherals can be used by
modifying some of the timing.
These examples
suggest possible ways of implementing the interface but may require some modifications to operate
properly. They were chosen because they give the
user a variety of interface design ideas.
The
first example uses a minimum amount of TTL logic
to implement the interface because the Valid
Peripheral Address (VPA) cycle meets the Z8500
timing requirements.
In this mode the 68000
accepts only nonvectored interrupts.
The second
example uses the Data Transfer Acknowledge (DTACK)
pin.
This interface allows faster operation and
makes
use
of
the
Z8500's
8-bit
vectored
interrupts.
The third example also uses a DTACK
cycle and is similar to the second, except the
external logic is integrated into a single chip,
the PAL20X10 programmable array logic.

The table given in Figure 1 can be used to calculate the amount of settling time required by a
daisy chain. Even if there is only one peripheral
in the chain, a minimum settling time is still
required because of the internal daisy chain. The
first column specifies the amount of settling time
for only one peripheral. If there are two peripherals, the time is computed by adding together the
times shown in the first and the last columns.
For each additional peripheral in the chain, the
time specified in the middle column is added.
Recovery TiR!
The read/write recovery time specifies a minimum
amount of time between Read or Write cycles to the
same peripheral. The recovery time differs among
peripherals and is summarized in Figure 3.
In
most cases, this parameter is met because of the
time required for instruction fetches. The recovery time specification does not have to be met if
DE is deselected when Read or Write occurs.

EXAMPLE 1: A TTL Interface Using a VPA Cycle
The 68000 has a special input pin,
Valid
Peripheral Address (VPA), that can be activated by
the Z8500 chip se lect logic at the beginning of
the cycle to indicate to the 68000 that a peripheral is being accessed. This generates a special
Read/Write cycle that meets the peripheral timing
requirements. This cycle allows the Z8500 control
signals to be generated easily.
The 68000
responds to interrupts using an autovector and the
Z8500 can be programmed not to return a vector.

68000 INTERFACE EXAMPLES
This section shows three examples, presented in
increasing order of complexity, for interfacing

RoIWR

/
/

I·

\
·1

/
trecovery

Peripheral

Recovery Time

(4 MHz)

CIO
FlO
SCC

Greater than 3 PCLK cycles or 1000ns
Greater than 1OO0ns
Greater than 6 PCLK cycles + 200n8

NOTE. The diagram shows that the recovery time Is measured between consecutive reads

and writes only II the peripheral is selected

Figure 3.

2267-003

Recovery

4-97

r-r-

a level 1 interrupt. The internal registers are
accessed by AO' A1' D/C, and AlB, which can be the
68000 lowest order addresses. The timing is shown
in Figure 5.

Figure 4 shows how the hardware can be implemented. PCLK is generated by dividing down the
68000 CLK. RD, WR, and INTACK are simply ANDed
68000 signals. The worst-case daisy-chain settle
time is 450 ns. Connecting INT to IPL O generates

VIlA
FCo
FC,
FC,

All

De~D7

Au-Au

ot---

....
....

- •

L.r'\

8.000

III1'lIllR

ClK
74LS74
Q

.... 0,

,,7

",-DlC

A1-AlB

RIW

VMA

...
to.

ClK

IPLI!
1PL1

»---

!Ill
Z8500
Perlph.... 1

.5V

---1

f---

»---

WI!

0 - peLK
ClK
74LS74

~l
lIlT

IP,-

figure II.

Interface Using the YPA Cycle

eLK
\~

______________________________________

~r___

1~·~------------------>~------------------~·~llt·~:::::::::::::>~·~~~::::::::::::~'I
II

, ' -_ _ _ _ _ _ _ _ _ _ _ _....J

____________________

~r___

Figure 5.

________________

~r___

VPA Cycle Tilling

4-98

2267-004, 005

functional Description

register (74LS164) is used to generate the proper
timing.
At the beginning of each cycle, QA
(Figure 7) is set High for one PCLK cycle and then
reset.
This pulse is shifted through the
QA-QH outputs and is used to generate R5, WR,
and DTACK signals. Some of the extra Wait states
can be eliminated by tapping the Shift register
sooner (e.g., QC)'

VPA is pulled Low at the beginning of the cyc Ie
and the CPU automatically inserts Wait states
until E is synchronized.
VPA

= [(AS)'(CE)]

= [(CE)'(VMA)'(R/W)]

[(CE)' (VMA)' (R/W)]

INTACK

EXAMPLE 3:

= [(FCO)'(FC1)'(FC2)'(AS)]

EXAMPLE 2:

Single-Chip Pal Interface

This example illustrates how to interface the 4
MHz Z8500 peripherals to the 8 MHz 68000 using a
PAL20X10 device to generate all the required control signals. The PAL reduces the required interface logic to a single chip, thus minimizing board
space. This interface offers flexibility because
the internal logic can be reprogrammed without
changing the pin functions.
The PAL uses 68000
signals to generate Read, Write, and Interrupt
Acknowledge cycles. In addition to generating the
Z8500 control signals, the PAL also generates a
DT ACK to inform the 68000 of a completed data
transfer cycle. This allows the 68000 to use the
peripheral's vectored interrupts.

A TTL Interface Using DTACK Cycles

Using the 68000 Data Transfer Acknowledge (DTACK)
cycle is a second way of interfacing to the Z8500
peripherals. The 68000 inserts Wait states until
the DTACK input is strobed Low to complete the
transfer.
In addition to generating the control
signals, the interface logic must also generate
DTACK.
The timing shown in Figure 6 can be generated by
the hardware shown in Figure 7.
The 8-bit Shift

eLK

PCLK

r--

RD/WR

DTACK
INTACK

'--

;-;--

\
figure 6.

2267-006

Timing for DTACK Interface

4-99

+5V

VPAW
R/W
A"
A"
A"
A"

»-b~

....,
Au

I ...

VCC

QA
Q.

...
to.

r-Q

•

8.000

f---

CLR

t--

r<'

CLR

~~l

Z.800

GNO

.....IPH.RAL

+5V

AI"
ILPa
1LP1

"
~~V

ILPo
FCo
FC,
FC,
DTACK

WI!

..-

74L8184 QE

CLK

1!1!

Qr-O
74LS74

74LS74

CLK

f--

A23

Ft-->-

to.

74LS74
Q -A
CLR

PCLK

INT
..-

""I

Do-o,

figure 7.

JIITA'eK

74LS74

r--

Do-o,

Hardware Diagr_ for DTACK Interface

Functional Description
Timing diagrams for the Read, Write, and Interrupt
Acknowledge cycles are shown in figure 9.

Figure 8 shows the PAL's pin functions. The PAL
generates five control signals, of which four (WA,
lID, CO, and INTACK) go to the Z8500 and one
(DTACK) goes to the 68000. The remaining signals
are used internally to generate these outputs.

The PAL uses a 4-bit downcounter to generate the
proper placement of the control signals where Co
is the least-significant bit and C3 is the

CLK

Vee

lIlm"

WI!

TEST

AI"
RIW

FC.
FC,
FCo

II!m
Ne

GNO

figure 8.

PAl Pinout

4-100

2267-007, 008

most-significant bit.
All of the PAL is clocked
with the rising edge of the 68000's elK.
The
counter toggles between counts 14 and 15 and
starts counting down when AS goes active.
The
counter goes back to toggling when AS goes

inactive.
eye goes active low at the same time
the counter starts counting down.
The equations
in Figure 10 can be entered into a development
board to program the PAL.

CLK

\~---------------------------------------co
C,

c.
Co

INTERRUPT
ACKNOWLEDQE
CYCLE

DTACK

INYACK

lID

2267-009

4-101

PALZOX10
P70B9 (10)
MC6BOOO TO ZILOG PERIPHERAL INTERFACE
MMI, SUNNYVALE, CA
CLK /CS NC TEST /AS RW
FCZ FCI FCO /RESET NC GND
fOE /C3 /CZ /C1 /CO /CYC
NC /OTK /RD /WR /ACK VCC

PAL DESIGN SPECIFICATION

/CO*/TEST

COUNT/HOLD (LSB)

:=
:+:

/RESET *AS*C 1
/RESET*AS*CO

HOLD
DECREMENT

/RESET*AS*CZ
/RESET*AS*CO*Cl

HOLD
DECREMENT

/RESET*AS*C3
/RESET*AS*CO*Cl*CZ

HDLD
DECREMENT

/RESET*/ACK*CYC*C3*/CZ*/C1* CO*CS
/RESET* ACK*CYC*C3*/CZ* Cl*/CO

DTACK FOR RD/WR CYCLE
DTACK FOR INTERRUPT
OPERATION

/RESET*AS*/CYC*CO
/RESET*AS* CYC
/RESET*CYC*DTK

NEW CYCLE STARTED
PROCESSING OF CYCLE
END OF CYCLE

/RESET*CYC*/ACK*RW* C3*/CZ*CS
/RESET*CYC*/ACK*RW*/C3*CZ*C1*CO*CS
/RESET*CYC* ACK*RW* C3
RESET

NORMAL READ OPERATION
NORMAL READ OPERATION
READ DURING OPERATION

/RESET*CYC*/ACK*/RW* C3*/CZ*CS
/RESET*CYC*/ACK*/RW*/C3* CZ*Cl*CO*CS
RESET

WRITE
WRITE

/RESET*FCO*FC1*FCZ*AS* Cyc*/CO
/RESET*FCO*FC1*FCZ*CYC

INTERRUPT ACKNOWLEDGE
INTERRUPT ACKNOWLEDGE

:+:

.:+:

DTK

CYC

.+
:+:

+
:+:

ACK

figure 10. PAl Equations

Hardware Diagr_

The hardware diagram of the PAL interface is shown
in Figure 11. The 6BOOO signals CLK, CS, AS, R/W,
FC O' fCl' and FCZ are used to generate the ZB500
control signals.
The control signals are synchronous with the rising edge of the 6BOOO's CLK.
TEST and OE must be grounded.
CS is used to

enable DTACK, RD, and WR as shown in the equations. The ZB500 INT is connected to ILPO, which
generates a 6BOOO level 1 interrupt. The peripherals are memory-mapped into the highest 64K byte
block of memory, where A17-An equals "fFH".
Addresses A4-A6 are used to select the peripheral;
Al-A3 select the internal registers.
Table Z
shows the peripheral's memory map.

4-102

2267-010

+5V

VPA
A16- A23

..
A,
..

-4-Qv
3.
33
32

•

r-r--7'
2

+5V
16
VCC
YO 15
62A
Y1 14
61

A
OND

8
-:

DTACK

elK

l\li •

f'-

FC,
FC,

FC,

•

eLK

9
28

DlACK

2~:~O

R/W

FC,

1LPo
1LP1

ILP2
'-----

I'- ~

~
~

[,-INTACK 8

SCC
Z8530

36 Rl!

}SE~IAL
PORTS

WI!

[,INTACK 25

INTACK
PCLK

Alii
~ ole

~
WI!
8

00-0 7

1m'

~
~

or
lIli
WI!

+5V
40
VCC

} 3 PARALLEL

CIO
Z8538

lEI
7

OND

+5V

GND lEO

~+5V
23

--_._--

Figure 11.

PAl. Hardware Diagr_

lEI

~ or

I'-~

WI!
INYACK

~ DIC
00-07

1m'
GND lEO

171 7 ~ 18 1

+sv---1!

}PORT2

FlO
Z8038

3 lID

INTACK

~A1

31f I

PORTS

PCLK

TEST

'~
00-0 7

9
VCC

1N1'Al:K ~

FC,

FC,
+5V _ _
'0_ RESET

,r-

co
AD
WR

+5V
23
VCC

+5V

2' +5V

~ cs
88000

A'~
A1

62 •

874138

00-0 7

r,;----

1m' F

MO
lEI

+5V
.~
2

•

°r I
GND

lEO

TO
NEXT
PERIPHERAL

Table 2.
Peripheral

Peripheral Memory Map
Register

Hex Address

SCC (lB530)
Channel
Channel
Channel
Channel

B Control
B Data
A Control
B Data

FF0020
FF0022
FF0024
FF0026

CIO (lB536)
Port C's Data Register
Port B's Data Register
Port A's Data Register
Control Register

FF0010
FF0012
FF0014
FF0016

Data Registers
Control Registers

FFOOOO
FFOO02

FlO (lB03B)

INTERFACE VERIfICATION TECHNIQUES
This section suggests possible ways of verifying
the Read, Write, and Interrupt Acknowledge cycles.
Read Cycle Verification
The Read cycle should be checked first because it
is the simplest operation.
The lB500 should be
hardware reset by simultaneously pulling RD and WR
Low. When the peripheral is in the reset state,
the Control register containing the reset bit can
be read without writing the pointer. Reading back
the FlO or C10 Control register should yield a
01H'
The SCC' s Read cycle can be verified by reading
the bits in RRO. Bits 02 and 06 are set to 1 and
bits DO, 01' and 07 are o. Bits 03-05 reflect the
input pins DCO, SYNC, and CTS, respectively.
Write Cycle Verification
The Write cycle can be checked by writing to a
register and reading back the results. Both the
CIO and FlO must have their reset bits cleared by
writing OOH to their Control registers and
reading back the result. The SCC can be checked
by writing and reading to an arbitrary read/write
register, for example, the Time Constant register
(WR12 or WR13).

Interrupt Acknowledge Cycle Verification
Verifying an Interrupt Acknowledge (INTACK) cycle
consists of several steps. First, the peripheral
makes an Interrupt Request (INT) to the CPU. When
the processor is ready to se-rvice the interrupt,
it initiates an Interrupt Acknowledge (INTACK)
cycle. The peripheral then puts an B-bit vector
on the bus, and the 6BOOO uses that vector to get
to the correct service routine. This test checks
the simplest case.
First, load the Interrupt Vector register with a
vector, disable the Vector Includes Status (VIS),
and enable interrupts (IE = 1, MIE = 1, lEI = 1).
Disabling VIS guarantees that only one vector is
put on the bus. The address of the service routine corresponding to the B-bit vector number must
be loaded into the 6BOOO's vector table.
Initiating an interrupt sequence in the Fro and
CIO can be accomplished by setting one of the
interrupt pending (IP) bits and seeing if the
6BOOO jumps to the service routine (setting a
breakpoint at the beginning of the service routine
is an easy way to check if this has happened).
Initiating an interrupt sequence in the SCC is not
quite as simple because the IP bits are not as
accessible to the user.
An interrupt can be
generated indirectly via the CTS pin by enabling
the following:
CTS IE (WR15 20), EXT INT EN
(WR1 01), and MIE (WR9 OB). Any transition on the
CTS pin can initiate the interrupt sequence. The
interrupt can be re-enabled by RESET EXT/STATUS
INf (WRO 10) and RESET HIGHEST IUS (WRO 3B).

CONClUSION
lilog's
lB500
family
of
nonmultiplexed
Address/Data bus peripherals can interface easily
with the 6BOOO and provide all the support
required in a high-performance microprocessor system. The many features offered by the SCC, FlO,
and CIO solve many system design problems by making interfacing to the external world easy. These
intelligent peripherals also greatly enhance the
system performance by relieving the CPU of many
burdensome overhead tasks.
Additionally, the
powerful interrupt structure allows the 6BOOO to
use vectors and reduce interrupt response time.

4-104

00·2267·01

Inlerfacing
Ihe Z·BUS® Peripherals
10 Ihe 8086/8088
Application
Nole

Zilog

July 1982
INTROOUCTION

Microcomputer systems based on Intel's 8086 and
80B8 CPUs can take advantage of the advanced
features of lilog's Z8000 series of microprocessor
peripherals with a minimal amount of external
logic.
These devices are easily integrated and
can satisfy many of the peripheral support
requirements in a typical 80B6/B08B-based system.
This Application Note discusses a general design
that enables the 80B6/BOB8 to interface with
Zilog's Serial Communications Controller (lBOJO
Z-SCC), Counter/Timer - Parallel I/O Unit (Z80J6
Z-CIO) , and fiFO I/O Controller (lBOJ8 l-flO).
Discussions
of
the
lB500
peripherals
(non-multiplexed address and data bus versions)
can be found in other Zilog documents.

+5V

z·see
z·elo

808618088
,5 MHz)

Z·FIO
MNIMX

DT/R I - - - - - - - - - { > c - - - - - - - - - j RIW
ALEI---------{>c---------j is
iii

..rt..rU1...

peLK
(NOTE 2)

+5V

es,
(NOTE 2)

INTACK

BUS INTERfACE

11'------------------"\1 ADo-AD7
311\r-------...,

ADo-AD15
(NOTE

The Z8000 peripherals (also called Z-BUS peripherals) lend themselves conveniently to B086/80B8
- based designs because of the multiplexed address/data bus architecture. There is no need for
an external address latch because the Z8000
peripherals latch addresses internally at the
beginning of each bus cycle.
Furthermore, the
peripherals allow the CPU direct access to all of
their data and control registers. Figure 1 shows
the interface logic that translates the signals
generated by the 8086/8088 into the necessary
Z-BUS signals, and Table 1 gives a description of
each signa 1.

2255-001

4-105

ADDRESS
DECODER

(NO~~,! I------------~____'

Note.

1. The source of PCLK can, but need not, be derIved from the
System eLK.
2. Does not apply to Z-FIO
3. ADO-AD7 and A8-A 15 on 8088.
4. 101M on 8088.

Figure 1.

Interface Logic

Cio

Table 1.

Signal Descriptioos

8086/8088 Signals

Minimum/Maximum.

This input is pulled high so that the CPU will operate in the "Minimum Mode."

DT/R

Data Transmit/Receive.

ALE

Addreas Latch Enable. ALE is used to latch addresses during the first T state of each bus
cycle so that the bus can then be free to transfer data.

Read.

Write.

ADg-AD15

This is the 16-bit, multiplexed address/data bus on the BOB6.
address/data bus, AOO-A07, and a high order address bus, AB-A15.

MIlO

Memory/Input-Output. This output distinguishes between memory and I/O accesses. On the B086
it is high on memory accesses and Iowan I/O accesses. On the B08B, the polarity is reversed
(IO/M).

DT/R is high on write operations and low on read operations.

strobes data into the CPU on read operations.

WR strobes data out of the CPU on write operations.

Z-8US

The B088 has a low order

Si!Plala

Riii

Read/Write. This input tells the peripheral whether the present access is a read or write.
is generated by inverting DT/R of the 8086/BOBB.

AS*

Address Strobe. AS is the main clock signal for the Z-BUS peripherals. It is used to initiate
bus cycles by latching the address along with CSD and INTACK. It is generated by inverting ALE
of the BOB6/B08B.

DS*

Oata Strobe.
When the Z-BUS peripheral is selected, OS gates data onto or from the bus,
depending on the state of R/W. It is generated from the BOB6/BOBB signals RD and WR as shown
in Figure 1.

INTAC!(

Interrupt Acknowledge. When low, this signal tells the peripheral that the present cycle is an
Interrupt Acknowledge cycle.
Address/Data Bus. This bus is connected directly to AOO-AD7 of the 80B6/808B. It is posaible
to connect it to AO B-A0 15 of the B086 as long as the BOB6 doesn't expect to read an interrupt
vector from the peripheral during interrupt acknowledge transactions.

CSg,CS1

Chip selects. CSo is active low and is latched with the rising edge of AS. CS1 is active high
and is unlatched.
In this interface, CS1 is pulled high while CSO is generated from the
address decode logic.

PCLK

Peripheral Clock. This signal does not apply to the Z-FlO. It can also be omitted from the
Z-CIO interface i f the chip ia not used as a timer, its REQUEST/WAIT logic is disabled, and it
does not employ deskew timers in its handshake operations. The maximum frequency of PCLK is 4
or 6 MH:!:, depending on the grade of the component, and it can be asynchronous to the system
clock.

*A hardware reset of a Z-BUS peripheral is performed by driving AS and OS low simultaneously.

4-106

BUS TIMING

Each BOB6/BOBB bus cycle begins with an ALE pulse,
which is inverted to become Address Strobe (AS).
The trailing edge of this strobe latches the register address, as well as the states of CS O and
INTACK within the peripheral. OS is then used to
gate data into (write) or from (read) the selected
register, provided that an active CSO has been
latched.
To assure proper timing, the AC
Characteristics of both the BOB6/BOBB and the
l-BUS peripherals, must be examined.
The paragraphs that follow discuss all of the significant
timing considerations that pertain to Read/Write
operations in this interface.
ADDRESS AND OUP SELECT (CSo) SETUP TIMES. The 4
MHz l-BUS peripherals require that the stable

address setup time prior to AS be at least 30 ns.
Since the 5 MHz BOB6/BOBB is guaranteed to provide
valid addresses at least 60 ns before Address
Latch Enable (ALE) goes low, this requirement is
easily satisfied.
The CSO setup time is of no
concern because the lBOOO peripherals require no
CSO setup time prior to AS.

ADDRESS AND CHIP SELECT (CSO) HOLO TIMES.
The
Z-BUS speci fications require that the address and
CS O remain valid a certain period of time after
the rising edge of AS. These minimum values are
50 and 60 ns respectively for the 4 MHz devices.
At 5 MHz, the BOB6/BOBB will hold its addresses at
least 60 ns after ALE goes inactive.
Although
this is equal to the minimum CS o hold time, a safe
margin will be maintained if the propogation delay
between the address going invalid to CSo rlS1ng,
exce~s the propogation delay between ALE falling
and AS rising.
ADDRESS STROlE (AS)

TO DATA STROlE (OS)

OELAY.

The 4 MHz peripherals need a 60 ns delay between
AS rising and 05 falling. This parameter is of no
concern on write cycles because the O-flop will
delay OS until the beginning of r3 (See Figure
2). On read cycles, OS follows RD, so the delay
between AS and OS is approximately equal to the
delay between ALE and RD.
If ALE falls at its
latest possible point in time and RD falls at its
ear Hest point, the time between these two edges
would be about 60 ns. This result is unrealistic,
however, because a delay in the termination of ALE

svs eLK

SYS eLK
(5 MHz)

(5 MHz)

~MIN

ALE

....,-

MIN

~
AD15-ADo

60
MIN

A1S-Ao

(NOTE 2)

ALE

DATA OUT

...-90_
MIN

CSo

_1000q:

\
215

MIN

-MIN-

-=t::;t=~-Flc)Ar"""---1[~~:==}-;;:;;;;;:--

AD15-ADo
(NOTE
2)
_

~~N I~

~-L+--+

____________________

E3)

[

1_ _1
410

MIN

Note.

Note:

1. All hmmg In ns.
2. A)5-AS and AD7-ADO on SOSS
3 6 PCLK cycles + 200 ns for Z-SCC. ThIs parameter only

1. All hmmg In ns
2 A)5-AS and AD7-ADO on SOS8.
3. 6 PCLK cycles + 200 TIS for Z-SCC ThIS parameter only
applIes to consecutive accesses to the same devlce.

applIes to consecutIve accesses to the same devICe

Figure 2.

2255·002, 003

Write Cycle Timing

Figure 3.

4-107

Read Cycle Timing

will always lead to a delay in the activation of
RD. The actual time between the two edges is well
over 100 ns.

least one instruction fetch cycle in between I/O
accesses, and 1000 ns translates into only 5 clock
cycles at 5 MHz.

ADDRESS SETUP THE TO DATA STROBE (DS).
The 4
MHz Z-CIO and Z-FIO require that the stable
address setup time to DS
be at least 130 ns.
Since the delay between AS rising and DS falling
is well over 100 ns, and since the address setup
time to AS is at least 60 ns, this requirement is
easily satisfied.

WAIT STATE GENERATION
The previous section explained why the 4 MHz Z8000
peripherals need to place a wait state in I/O bus
cycles when interfaced to the 5 MHz 80B6/BOB8.
The following two examples illustrate how wait
state generation can be implemented.
Since
BOB6/BOB8 - based systems typically use an B2B4
Clock Chip, which synchronizes the CPU's READY
input with the system clock, the task reduces to
designing a circuit that will control the RDYl
input of the B2B4 (RDY2 is assumed to be
grounded).

DATA STROBE (DS) LOIf WIDTH.
The minimum Data
Strobe low Width of the 4 MHz Z-BUS peripherals is
390 ns.
On read cyc les, DS wi 11 have the same
width as RD, which is at least 325 + 200Nw ns,
where Nw is the number of wait states in the bus
cycle.
On write cycles, the D-flop will shorten
this minimum width to 210 + Nw 200 ns. One wait
state (Tw) in the bus cycle will ensure a
sufficiently wide Data Strobe for both types of
bus cycles. A discussion of wait state generation
is presented in the next section.

SINGLE WAIT STATE GENERATION. For the processor
to enter a wait state after T3' the RDYl input
must be low during the falling edge of SYS ClK at
the end of f 2'
Then, for the processor to enter
T4 after the wait state, RDYl must be high during
the next falling edge of SYS ClK.
To make sure
that these levels are well-established during
their sampling windows, the single wait state
generator should toggle RDY1, using the clock
edges that precede the sampling edges (Figure 4).
The circuit in Figure 5 performs this function ~d
generates a single wait state when one of the CSO
inputs is active.

WRITE DATA SETUP AND HOLD lItES. On write cycles,
the Z-BUS peripherals require the CPU to put valid
data on the bus at least 30 ns before 55 goes
active, and to hold it there at least 30 ns after
DS terminates. D-flip-flop in Figure 2 guarantees
the setup time by delaying the falling edge of WR
until the next falling edge of SYS ClK (Figure
2.). The Hold Time is also guaranteed because the
8086/8088 will hold valid data at least 90 ns
after the termination of WR.

REAO DATA SETUP AN) HOLD lItES. When the B086/
BOBB reads from memory or peripherals, it requires
them to put valid data on the bus at least 30 ns
before the falling edge of SYS ClK at the beginning of f 4 •
It also requires them to hold the
valid data at least 10 ns after this edge. Since
the Z-BUS peripherals will provide valid data
early in Tw and will hold it until after DS terminates, these parameters are well within the specifications.
VALID ACCESS RECOVERY TItE. This parameter refers
to the time between consecutive accesses to a
given peripheral. If the 4 MHz Z-SCC is accessed
twice, then the time between DS rising in the
first access and DS falling in the second access,
must be at least 6 PClK cyc les plus 200 ns (i. e.
1700 ns for a 4 MHz PClK).
The Valid Access
Recovery Time for the 4 MHz Z-CIO and Z-FIO is
1000 ns, and this can't possibly be violated with
a 5 MHz BOB6/BOBB since there will always be at

4-108

svs
eLK
RDY1

8284

Figure 4.

ROY1

T~ng

for Single Wait State

TO RDV 1

8284

Figure 5.

Single Wait State Generator

2255-004, 005

MULTIPLE MAlT STATE GENERATION. Though Read/Write
operations require only one wait state, Interrupt
Acknowledge transactions need multiple wait states
to allow for daisy-chain settling, which is
explained in the next section.
The following
discussion introduces a multiple wait state
generator and serves as a basis for understanding
the subsequent Interrupt Acknowledge Circuit.

appears at QB' and on Interrupt Acknowledge
cycles, ROY1 is held low until the leading "one"
appears at QH'
The next section shows how
INTACK can be generated and discusses the complete
interrupt interface.
INTERRUPTS
In Figure
the IN TACK input to the Z-8US
peripherals is pulled high.
This does not mean
that the peripheral can't interrupt the CPU; it
just means that it won't respond to the CPU's
interrupt acknowledge. The designer can, however,
implement a circuit that will drive INTACK, and
allow the 8086/8088 to proper ly acknowledge the
interrupts of the Z-BUS peripherals. This section
examines the interrupt acknowledge protocols of
the Z-BUS peripherals and the 8086/8088, then
proceeds to show how they can be made compatible.

In the preceeding discussion of the single wait
state generator, we established that ROY1 must be
high at the end of T3 for the processor to enter
T4 after the wait state.
In general, the
8086/8088 will continue to insert wait states
until ROY1 is driven high. In fact, the number of
wait states wi 11 be equal to the number of clock
cycles that ROY1 is held low after the rising
clock edge in T2'
A convenient way to implement a multiple wait
state generator is to use a serial shift register
such as a 74LS164.
Figure 6 shows a wait state
generator that requests one wait state on Read/
Write cycles, and up to seven wait states on
Interrupt Acknowledge cyc les.
When RO, WR, or
INTA goes active, the 74LS164 is taken out of the
clear state and logic "ones" are allowed to shift
sequentially from QA to QW
On Read/Write
cycles, ROY1 is held low until the leading "one"

Z-BUS INTERRUPT N:KNOWLEDGE PROTOCOl. The Z-BUS
peripherals typically use the daisy-chain technique of priority interrupt control.
In this
scheme the peripherals are connected together via
an interrupt daisy chain formed with their lEI
(Interrupt Enable Input) and lEO (Interrupt Enable
Output) pins (Figure 7).
The interrupt sources
within a device are similarly chained together,
with the overall effect being a daisy chain connecting all of the interrupt sources.
The daisy
chain allows higher priority interrupt sources to
preempt lower priority sources and, in the case of
simultaneous interrupt requests, determines which
request will be acknowledged.
In each bus cycle the Z-BUS peripherals use the
rising edge of AS to latch the state of INTACK.
If a low INTACK is latched, then the present cycle
is an Interrupt Acknowledge cycle and the daisy
chain determines which interrupt source is being
acknowledged in the following way. Any interrupt
source that has an interrupt pending and is not
masked from the chain will hold its lEO low.

.........k-----t-- INTACK

figure 6. "dtiple Wait State Generator
HIGHEST

LOWEST

PRIORITY

LIEf

Z-BUS

PERIPHERAL

ADo-AD7

ADO-AD7

AS
DS
INT
IN TACK

lEO

I------

TNT INTACK

2r-t t I

ADo-AD7

Z·BUS
PERIPHERAL

AS Os TNT

lEO

f----:/.f------..

lEI

ADo-AD7

INTACK

irtt I t

1 I
1

A Z-BUS Interrupt Daisy Chain

4-109

Z·BUS
PERIPHERAL
-

gLl
f.

Figure 7.

2255-006, 007

lEI

!NT

INTACK

Similarly, sources that are currently under
service (i.e. have their IUS bit set) will also
hold their lEO lines low.
All other interrupt
sources make lEO fo llow lEI.
The result is that
only the highest priority, unmasked source with an
interrupt pending will have a high lEI input; only
this peripheral will be allowed to transfer its
vector to the system bus when the Data Strobe is
issued during the Interrupt Acknowledge cycle.

will execute an Interrupt Acknowledge sequence.
The sequence cons~sts of two identical INTA bus
cycles with two idle clock cycles in between
(figure B). In both bus cycles, RD and WR remain
inactive while an INTA strobe is issued with the
same timing as a WR strobe.
The 8086/808B
requires an interrupt vector to appear on ADO AD7 at least 30 ns before the beginning of T4 in
the second INTA cycle. This protocol is normally
used to read vectors from the B259A Interrupt
Controller but it can easily be adapted to the
Z-BUS
Interrupt
Acknowledge
Protocol,
as
illustrated in the following paragraphs.

To make sure that the daisy chain has settled by
the time DS gates the vector onto the bus, the
Z-BUS peripherals require a sufficient delay between the rising edge of AS and the falling edge
of DS in INTACK cycles.
The amount of delay
required can be calculated using Table 2. for a
particular daisy chain, the minimum delay is:
Thigh for the highest priority device, plus Tl ow
for the lowest priority device, plus Tmid for each
device in between.

INTERRUPT ACKNONlEDGE COMPATIBILITY.
The first
function of the Interrupt Acknowledge circuit,
shown in figure 9, is to generate the Z-BUS INTACK
signal using INTA from the 8086/B088. Since INTA
goes active after ALE has terminated,
the
peripherals will not latch an active INTACK during
the first INTA cycle. However, if the rising edge
of INTA is used to toggle INTACK, then an active
INTACK latches with the rising edge of AS in the
second INTA cycle. Thus a rising-edge triggered
toggle flip-flop, as configured in figure 9, can
be used to generate INTACK. ~gure 10 shows the
timing relationship between INTA and INTACK.

Table 2. Daisy Dlain Settling TiEs for the Z-BUS
Peripherals {in ns}
Thigh

Z-SCC
Z-CIO
Z-fIO

Tl ow

Tmid

4MHz

6MHz

4MHz

6MHz

4MHz

6MHz

250
350
350

250
250
250

120
150
150

100
100
100

120
100
100

100
70
70

The next function of the Interrupt Acknowledge
circuit can be broken down into three operations:
first, it must cause the CPU to enter a series of
wait states after T3 in the second INTA cycle;
then, it must activate DS after a sufficient daisy
chain settling time; lastly, it must bring the CPU
out of the wait state condition when the vector is
available on the bua.

B086/8088 INTERRlPT ACKNOWLEDGE PROTOCOL.

If the
BOB6/8088 receivea an interrupt request (via its
INTR pin) while its Interrupt flag is set, then it

I I I I I
I
I
I
I
f\""'--_ _ _ _--Jn~ ___
T,

ALE

INTA _ _ _"'"

\'--_...JI
ADO-AD7

\'--_...J1

}----------:=~--------~~
FLOAT
~
figure B.

BOB6/BOBB INTA 5eqIB1Ce

4-110

2255-008

Figure 9 shows how the multiple wait state
generator, discussed in the previous section, can
be used to perform each of these operations.

While INT ACK is high the circuit operates
normally; the number of wait states it requests is
determined by the positioning of the jumper on the
Q outputs.
When INTACK goes low, it operates as
follows:
the next activation of INIA bungs the
shift register out of the clear state, and logic
"ones" shift into QA until they fill the entire
register.
When t.he leading "one" appears at QG'
DS is driven low; when it appears at QH' t.he CPU
is taken out of the wait state condition.

z-scc

808618088
(5 MHz)

Z-CIO
Z-FIO

RD~~------------------------~

This arrangement takes advantage of the full
length of the shift register and provides a
daisy-chain settling time of more than 1300 ns,
which allows the implementation of a chain with as
many as seven Z-BUS devices. Figure 10 shows the
hming of the important signals in the Interrupt
Acknowledge transaction.
lEI

INTA

HARDWARE: RESET

___-------=--I>.

The designer may want to incorporate a hardware
reset in the interface design.
This can be
accomplished with two NOR gates as shown in Figure
11 • The -,,!OR gates allow the system RESET signal
to pull AS and DS low simultaneously, and hence
put the peripheral in a reset state. A hardware
reset is not necessary, however, because all of
the peripherals are equipped with software reset
commands.

INTR~----------------------~"[D,, [D131D'!lD'' "'<>l D'.iD'.iD,

o
o

RESET

INTERRUPT CONTROL

o
o

SOFTWARE REQUEST

FLIP BIT

HARDWARE MASK

NOT RECOGNIZED

INTERRUPT { CIE
STATUS
ST13 - ST15

START CHAIN

DTC

STATUS
ST9-ST12

IUS
IP

06 05 04 03 02 01

IL= :~p )

{N~~

MCH
HRQ} HARDWARE
INTERFACE
HM
STATUS ST5-ST8

WFB
SIP

RESERVED

INTERRUPT SAVE REGISTER
TEMPORARY REGISTER

ID15ID"ID13I0"ID11ID1OID.1 D.I D"D.I D'I D41 D,I D,I D'iDOJ

I
I

VECTOR
CHANNEL NUMBER
0- CH1
1 "" CH2

PATTERN AND MASK REGISTERS

TC
EOP
MC
BASE AND CURRENT OPERATION COUNT REGISTERS

CHAIN ABORTED

MCL
MCH
HARDWARE REQUEST

INTERRUPT VECTOR REGISTER

CHAIN CONTROL REGISTER
(CHAIN LOADABLE ONLy)
(WRITE ONLy)

'fn

Vl'h!li\ll"""j'l 'I'~ =::~=:.~-:'
PATTERN AND MASK (2 WORDS)

INTERRUPT
VECTOR

CHAIN ADDRESS REGISTER
15

• 7

SEGMENT

BASE OP·COUNT (1 WORD)
BASE ARB (2 WORDS)
BASE ARA (2 WORDS)
' - - - - - - - - - - CURRENT OP·COUNT (1 WORD)
' -_ _ _ _ _ _ _ _ _ _ CURRENT ARB (2 WORDS)

0 WAIT STATES

1 WAIT STATES

2 WAIT STATES

4 WAIT STATES

' - - - - - - - - - - - - CURRENT ARA (2 WORDS)

L------------------------------~~~:~~~CAL
ADDRESS ONLY
OFFSET

tigure 2.
2271-003

18016 Ole Internal Registers
4-115

COMPLETION
STATUS STO-ST4

MCL

DATA OPERATION FIELD
Transaction

Operand Size
ARA
ARB

.In!!:.

Byte
Byte
Word
Byte
Word

Byte
Word
Word
Byte
Word

Flowthrough
Flowthrough
Flowthrough
Flyby
Flyby

Byte
Byte
Word
Byte
Word

Byte
Word
Word
Byte
Word

Flowthrough
Flowthrough
Flowthrough
Flyby
Flyby

1111
1110

Byte
Word

N/A
N/A

101X

Illegal

Code/Operation
Transfer
0001
100X
0000
0011
0010

Transfer-and-Search
0101
110X
0100
0111
0110

TRANSFER TYPE FIELD AND MATCH CONTROL FIELD
Code

Transfer Txpe

Hatch Control

00
01
10
11

Single
Demand
Demand
Demand

Stop
Stop
Stop
Stop

Transfer
Dedicated/Bus Hold
Dedicated/Bus Release
Interleave

II I

on
on
on
on

No Match
No Match
Word Match
Byte Match

Mm" CO''"O'
PULSEO OACK

""0

HAROWARE REQUEST MASK
SOFTWARE REQUEST

I
1015101410131012101110101091

CHAIN (
ENABLE

TC
MC
EOP

B TO C ( TC
RELOAD
MC
ENABLE
EOP
INTERRUPT (
ENABLE

oal 071 0 6

I I I 01 I 00 1

051 04 03 02

-~L OATA OPERATION FIELO
FLIP BIT
(0) - ARA
src, ARB
dst
(1) - ARA = dst, ARB = src

TRANSFER TYPE FIELO

;~
EOP

Figure 3. Z8016 DlC Channel Mode Register
4-116

2271-004

Table 1.

ZB016 DTC Internal Registers

Chain
Control
Bit

Port Address(Hex)
Channel 2
Channel 1

DEVICE REGISTERS

3B
2C

Master Mode register
Command register
Chain Control register
remporary register
CHANN£l REGISTERS
Address registers, chainable
Segment/Tag

Current Address - A
Current Address - B
Base Address - A
Base Address - B
Chain Address

1A
12
1E
16
26

B
6
5
0

Offset

oA
02
DE
06
22

Segnent/Tag

1B
10
C
14
24

Control registers, chainable

Current Op-Count
Base op-Count
Channel Mode* - High
Channel Mode* - Low
Pattern*
Mask*
Interrupt Vector*

3
3
2

32
36
56
52
4A
4E
5A

30
30
54
50
4B
4C
5B

2E
2A

2C
2B

Status/Save registers, Non-chainable

Status register
Interrupt Save register
*Slow-readable registers.

4-117

Offset

DB
00
OC
04
20

SEGMENT
NUMBER

SNO

ADO

SNI

ADI

SN2

AD2

SN3

AD3

SN4

AD4

SNs

ADs

SNs

ADs

SN7/MM USYNC

AD7
ADa

STo

ADs

STI

AD10

ST2

STATUS

ADll

Z8016
DTC

ST3

AD12

R/W

AD13

BiW

AD14

N/S

ADIS

BUSREQ

ADDRESSI
DATA

CS/WAIT

BAI

DREQl, DREQ2

BAa

DACK1, DACK2

DMA
CONTROL

EOP
AS

INT
lEI

INTERRUPT
CONTROL

lEO

+5V

Figure 4.

ClK

GND

l8016 OTe Pin Functions

The interface signals and pin assignments are
listed in Table 2.
50me of the signals are
three-state, i.e., they are high-impedance when
not under bus control.
The open-drain pins
require a pullup resistor 0 f 3. 3K ohms or more.
The DTC decodes the status lines (5TO-5T3) for the
Interrupt Acknowledge signal and generates status
for data transactions.
The multiplexed input
CS/WAlT serves as an active Low alip Select (CS)
signal when the DTC is a bus slave, and serves as
an active Low Wait (WAI1) signal when the DTC is
bus master and the control bit in the Master Mode
register is enabled.
The multiplexed output
5N7/MMUSYNC is driven Low when the DTC is not in
control of the system bus and the MM1 bit of the
Master Mode register is set. SN 7/MMUSYNC floats
to a high-impedance state when the DTC is not in
control of the system bus and the MM1 bit is
cleared. When the DTC is in control of the system
bus and is operating in logical address space,
this line outputs an active High MMUSYNC pulse
prior to each memory transaction cycle.
In
physical address space, this line outputs 5N 7 ,

is the
address space.

whiCh

24th

address

bit

the

lillea..:'

If a peripheral device requires DMA service, it
issues a request to the DTC by asserting DREQ. If
the channel receiving the request is enabled and
the BU5REQ and BAI lines are High, the DTC issues
a bus request to the CPU by driving the BU5REQ
line Low. When the CPU relinquishes bus control,
a Bus Acknowledge signal is output to the DTC by
driving the BAI line Low, indicating that the
request for bus control has been granted.
Upon
receipt of the Bus Acknowledge signal, the DTC
issues a DMA Acknowledge signal to the peripheral
by lowering the DACK output; it then issues the
control signals and addresses necessary to effect
the transfer. When the transfer is completed or
terminated, DACK is driven High and the DTC begins
the termination procedure. The DACK output can be
programmed as level or pulsed for Flyby transactions and as level or inactive for Flowthrough
transactions via the CM 18 bit of the Channel Mode
register.

4-118

2271-005

Table 2.

Z8016 Ole Interface Signals

Interface Signal

Pin Nunber

Input/futput

Three-State

Open-Orain

AD O-AD 15

5-20
44

In/Out
In/Out
In
Out
In/Out
Out
In
Out
In
In/Out
In/Out
In
Out
Out
Out
In/Out
Out
Out
In/Out

Yes
Yes
No
No
No
Yes
No
No
No
Yes
No
No
No
No
Yes
Yes
Yes
Yes
No

No
No
No
No
Yes
No
No
No
No
No
Yes
No
No
Yes
No
No
No
No
No

BAl
BAO
BUSREQ
B!W
CS/WAIT
DACK 1 ,DACK 2
DREQ1,DREQ2

55
EOP
lEI
lEO
INT
N/S
R/W
SN O-SN 6
SN7/MMUSYNC
ST O-ST 3
ClK
GND
+5V

3
2
35
42
39,40
36,37
43
38
46
48
47
30
41
21-25,28,29
27
31-34
45
26
4

To establish DMA operation, the internal registers
can be loaded under software by the CPU.
The
registers are addressed via the low byte of the
Address/Data bus (AD 7-AD O). The high byte of the
Address/Data bus (AD 15 -AD 8 ) is decoded with the
user's chip select logic.
Chip Select (CS) must
be valid prior to the rising edge of AS to allow
the CPU to write to, or read from, the DTC' s
registers.
During a DMA transfer, the DTC
generates control signals (R/W, B/W, N/S, and
STO-ST 3) to indicate the transfer direction, the
data size, and the type of space and transaction.
It also generates AS, 55, DACK, and MMUSYNC
signals to synchronize timing and to demultiplex
the
Address/Data
lines.
Additionally,
it
generates addresses (SN 7-SN O and AD 15-AD O for
physical addressing space or SN 6-SN O and AD15-AD O
for logical addressing space) of the source and
destination of the transfer; samples the DREQ,
WAIT, and EOP lines; stores the data for the Flowthrough transaction; and issues an EOP low signal
when the transfer is terminated.
Upon termination, the DTC performs either an interrupt,
base-to-current reloading,
chaining,
or does
nothing, under the control of Channel M:lde
register (i.e., bits CM 7-CM 15 ).

The CPU regains bus control upon sampling its
BUSREQ input; i f inactive, the CPU drives its
BUSACK output inactive.
Whenever both BAI and
BUSREQ are High and no DMA requests are pending,
the DTC passes the High signal through BAO to the
lower-priority device, enabling it to request bus
control. This procedure allows the CPU to regain
bus control whenever an interrupting device
releases bus control. See the lilog 1982/83 Data
Book" for more details on the lUog l-BUS.

To relinquish bus control, the DTC drives its
BUSREQ line High and allows BAO to follow BAl.

INITIAlIZATION
After a hardware reset (i.e., AS and 55 are
simultaneously low) or a software reset (Le., a
reset command is issued to the Command register),
take the following steps to initialize the system:
•

Clear the Master Mode (MM) register to disable
the DTC.

•

Set the Chain Abort (CA) and Non-Auto Chaining
(NAC) bits in each channel's Status register.

•

Load each channel's Chain Address register.

•

Issue Start Chain command.

"(document number 00-2034-02)

4-119

to minimize interaction with the host CPU, the DTC
loads its own control parameters from memory into
each channel (Le., performs chaining). The CPU
need to only program the Master Mode register and
each channel's Chain Address register (Figure 5).
All other registers are loaded by the channe Is
themselves from a reload table located in system
memory and pointed to by the Chain Address
register. During chaining, the N/S and B/W lines
are driven Low and the ST 3-ST O outputs are set to
1000 (i.e., Memory Transaction for Data).

the reload word is 0203 H, only Current Address
register A (Current ARA), Channe I Mode register,
and Chain Address register are reloaded with the
data in locations 1022H through 102C H (a total
of six words), and the remaining registers are not
changed. When loading the address registers, the
segment and tag word must precede the offset word
(e.g., the segment and tag word of Current Address
register A is located at 1022H' while the offset
word is located at 1024H).
After the Master Mode bit MMO is set, a Start
Chain command causes the selected channel to clear
the NAC bit in its Status register and to start
chaining.
The control parameters of the channel
are reloaded and the channel is ready to perform
the DMA operation. DMA operation can be initiated
in one of the following three ways:

The first word in the reload table, the reload
word, specifies which registers in the channel are
to be reloaded.
Bits 0 through 9 in the reload
word relate to either one or two registers in the
channel (Table 3). When a reload word bit is 1,
the register or registers corresponding to that
bit are reloaded.
The data loaded into the
selected registers follow the reload word in
memory at successively larger addresses.
The reload table is of variable length.
For
example, when the contents of the segment and
offset fields of Channel l' s Chain Address
register are OOOOH and 1020 H, the reload table
is started at location 1020H.
Thus, the data
stored at location 1020 H is the reload word. If
the reload word is 03fT H' all 0 f Channe 1 l' s
registers are loaded with the data in locations
1022H through 1042H (a total of 17 words).
If

0100
0104
010B
010A
010E
0112
0114
0118
011C
011E
0122
0126
0128
012C
0130

2101
3B16
8D07
2101
3B16
8D07
2101
3B16
8D07
2101
3B16
8D07
2101
3B16
8D07

0000
002C
0000
0026
1020
0022
0001
0038
OOAO
002C

LD
OUT
NOP
LD
OUT
NOP
LD
OUT
NOP
LD
OUT
NOP
LD
OUT
NOP
Figure 5.

•

By software request--issue
Request command.

•

By hardware request--apply a Low signal on the
channel's DREQ input; the Hardware Request Mask
bit (CM 19 ) in the Channel Mode register must be
cleared.

•

By chaining--load a Software Request bit
(CM20 = 1) into the Channel Mode register
during chaining.

R1,f10000
%002C, R1

;RES(f

R1,1I0000
%0026,R1

;LOAD SEGMENT/TAG OF CHANNEL l' S
;CHAIN ADDRESS REGISTER

R1,lf1020
1m022,R1

;LOAD OFFSET OF CHANNEL 1'S
;CHAIN ADDRESS REGISTER

R1,lfOO01
%0038,R1

;LOAD MASTER MODE REGISTER TO
;ENABLE DlC

R1,%00AO
%002C, R1

;LOAD START CHAIN COMMAND

Set

Software

Initialization of the Z8016 Ole

4-120

2271-006

Table J.

EXlllllple of Chain Control Tables

Me.ory

Data

Remarks

1020
1022
1024
1026
1028
102A
102C
102E
1030
1032
1034
1036
1038
103A
103C
103E

03FF
0000
1FOO
0074
FF01
OOAO
0000
2FOO
0074
FF01
0100
1234
FOOD
0002
0004
3042

Chain Control register
Segment/Tag of Current Address Register A
Offset of Current Address Register A
Segment/Tag of Current Address Register B
Offset of Current Address Register B
Current Op-Count
Segment/Tag of Base Address Register A
Offset of Base Address Register A
Segment/Tag of Base Address Register B
Offset of Base Address Register B
Base Op-Count Register
Pattern register
Mask register
Interrupt Vector register
Channel Mode High
Channel Mode Low

Chaining all registers
System data mem, increment, 0 waits
Starting address
I/O, hold, 2 waits
Peripheral address
160 transfers
System data, increment, 0 waits
Starting address
I/O, hold, 2 waits
Peripheral address
256 transfers
0001001000110100 as pattern
1111000000000000 as mask
Vector = 02
Pulsed DACK
Chain at EOP, 8ase to Current at
TC, Address Register A to Address
Register B Demand/Bus release,
word-to-word flyby

1040
1042

0000
1080

Segment/Tag of Chain Address
Offset of Chain Address

Address of next chain control word

1080

0182

Chain Control register

Chaining three registers

1082
1084
1086
1088
108A

0076
FF02
0050
0010
0240

Segment/Tag of Current Address Register B
Offset of Current Address Register B
Current Op-Count
Channel Mode High
Channel Mode Low

I/O, hold, 4 waits
Peripheral address
80 transfers
Software request during chaining
Interrupt at TC, Address Register A
to Address Register B, word flowthrough

When DMA operation is initiated by either software
or hardware request, the DTC drives the BUSREQ
line Low and performs the DMA operation after i t
receives an active Low BAI signal.
When DMA
operation is initiated by chaining, the DTC
performs the DMA operation as soon as chaining
ends if the MM2 bit (CPU Interleave Enable bit) is
clear. If the MM2 bit is set, the channel gives
up bus control after chaining and before DMA
operation.

bits 0 through 3 of the Channel Mode register.
The Flip bit (CM 4 ) is used to control the transfer
direction. Figure 6 shows state diagrams for the
various types of operations.
Table 4 lists the
operation codes.
Flowthrough Transfer and Flowthrough Transferand-Search operations consist of both read and
write transactions.
When bit CM4 is clear, the
DTC reads data from the location specified by The
Current Address Register A (ARA) (Le., the
source), stores the data in the Temporary
register, compares the data with the unmasked
pattern, and then writes the data into the
location specified by the Current Address Register
B (ARB) (i.e., the destination). When bit CM4 is
set, the source location is specified by the

DNA DPERATIIWS

There are three types of DMA operation: transfer,
transfer-and-search, and search, each of which can
in either
a Flowthrough
or
Flyby
occur
transaction.
They are controlled by programming

4-121

AS = 1,

OS = 0

PLACE DATA FROM
SOURCE ONTO BUS:
SAMPLE WAIT

SAMPLE DREQ AND BAI,
DRIVE BUSREQ.
DACK = 1

T22

SEND DATA TO DESTINATION:

OS = 1
UPDATE ADDRESs/COUNT
(CM4
(CM4

T23

= 0): C·ARA ON BUS

= 1): C·ARB ON BUS

RJW =

1; AS = 0

DACK

AS = 1;

T11

OS = 0

BUS RESERVED FOR DATA:
SAMPLE WAiT

T12

= 1
=0

OS =

SAMPLE

WAiT

T1WA

PLACE DATA FROM
SOURCE INTO TEMPORARY
REGISTERS:
OS = 1
T13

(CM4 = 0): C·ARB ON BUS
(CM4 = 1): C·ARA ON BUS

R/iN = 0
AS=O

Figure 6&.

T21

nowthrough Tr_fer and nowthrough Tr_fer-and-Search Operations

4-122

227Hl07

~--------~
DATA INTO TEMPORARY REGISTER
COMPARING WITH
UNMASKED PATTERN:
= 0, PULSED DACK INACTIVE
UPDATE ADDRESS AND
COUNT CHECKING TC, MC,
EOP: SAMPLING DREQ

SAMPLING DREQ
DRIVING BUSREQ
SAMPLING BAI
DACR INACTIVE

(CM4 = 0): C·ARA ON BUS:
(CM4 = 1): C·ARB ON BUS:

R/W = 1,lIll = 0
LEVEL DACK ACTIVE

lIll = 1:

os = 0

BUS RESERVED FOR DATA
SAMPLING WAIT
PULSED DACK ACTIVE
12

= 0, DACK = 0
SAMPLING WAIT
TWA

•

figure 6b.

flyby Transfer and flyby Tr_fer-and-Search Operations

Current ARB, and the destination is specified by
the Current ARA.
Flyby Transfer and Transfer-And-Search operations
consist of a single Read cycle or a single Write
cycle. When CM4 is clear, the DTC reads the data

227HJ08

from the location
the DACK signal
peripheral.
In
the data is also
and compared with

4-123

specified by the Current ARA and
strobes the data to the flyby
Transfer-and-Search operations,
stored in the Temporary register
the unmasked pattern.

~---------,
(CM. = 0): DATA INTO FLYBY PERIPHERAL
(CM. = 1): DATA FROM FLYBY PERIPHERAL
OS PULSED, DACK
1,
UPDATE ADDRESS AND COUNT,
CHECKING !£J!!C, EOP
SAMPLING DREQ

SAMPLING DREQ
DRIVING BUSREQ
SAMPLING BAI
DACK = 1

= 1

= 0 (CHANNEL REQUESTED)
(CM. = 0): C·ARA ON BUS:
(CM. = 1): C·ARB ON BUS:

R/W=l,AS=o
DACR = 0

AS =

OS =

BUS RESERVED FOR DATA
SAMPLING WAIT
PULSED DACK ACTIVE
T2

OS = 0, DACK = 0
SAMPLING WAIT
TWA

figure 6c.

Search Operation

4-124

2271·009

Table II.
Operation

Operation Code
C",-CHo*

~ratioo

Size

Codes lind

Progr~ng

Suggestions

W
B - B

If CM4 = 0 then ARA to ARB; if CM4 = 1 then ARB to ARA
If CM 18 = 0 then level OACK; if CM18 = 1 then DACK inactive

w- W
B- B

If C~ = 0 then ARA to ARB; if CM4 = 1 then ARB to ARA
If CM18 = 0 then level DACK; if CM18 = 1 then pulsed OACK

Flowthrough
Transfer &
Search

W
B- B

CM4 , CM18 same as flowthrough transfer
If CM17 = 0 then stop on no match; if CM17
match

Flyby
Transfer
Search

B- B

CM4 , CM18 aame as flyby transfer
If CM17 = 0 then stop on no match; if CM17
match

B- W

Flowthrough
Transfer

Flyby
Transfer

Flowthrough
funneling

Flyby
funneling

W- W
B- B

Operatioo Code
~
~

Single
Operation

Demand with
Bus Hold

Demand with
Bus Release
Demand
Interleave

Byte at ARA, word at ARB
If C~ = 0 then byte-to-word; if CM4
If CM18 same as transfer
Operation count = number of words

= 1 then

stop on

word-to-byte

B- W

Operatioo

1 then stop on

If CM4 = 0 then source at ARA; if CM4 = 1 then at ARB
If CM17 = 0 then stop on no match; if CM17 = 1 then stop on
match
Suggeations

Each Software Rec. command causes one operation;
Each DREQ falling edge causes one operation**
Each Software Req. command causes block operation***;
Operating when DREQ Low; Hold bus when DREQ High

Each software Req. command causes block operation***;
Operating when DREQ Low; Release bus when High
Each Software Req. command causes block operation***;
Operating when DREQ Low; Release bus to other
channel or CPU after each operation

*CM (Channel Mode) register's bit.
**The DREQ falling edge must meet the timing requirement.
***If MM2 (Master Mode) bit is set (CPU interleave is enabled), the DTC releases the bus after each
operation when the channel is not in Bus Hold mode.

4-125

When Flip bit CM4 is set, the DlC activates DACK
to the flyby peripheral, which enables the data
onto the AID bus, writes the data into the
location specified by the Current ARB, stores it
in the Temporary register, and compares it with
the unmasked pattern.
The Search operation consists of a Read cycle
only. The DTC reads data from the source location
(specified by the Current ARA when CM4 = 0 and by
Current ARB when CM4 = 1), stores the data in the
Temporary register, and compares it with the
unmasked pattern.
No data is written into any
location or peripheral.
Channel Mode register
bits CM17 _CM 16 are the match control field for
programming the Stop condition.
Channel Mode bits CM6-CMS select the channel's
response to the request to start a DMA operation.
There
are
four types of response:
single
operation, demand dedicated with bus hold, demand
dedicated with bus release, and demand interleave.
These responses are detailed below.
Figure 7 shows flow charts for each of these
responses. Interleave operations between the CPU
and the DTC, and between DTC channe Is, are shown
in Figure B.
The setting of bits CM6 and CMS are described as
follows:

a) Single operation (C"t; = 0, C~ = 0).
In
response to a software request or active DREQ
High-to-Low transition, the channel performs a
single LJMf\ 11:era{.10n. ihe DTe relinquishes bus
control after each transaction unless a second
High-to-Low DREQ transition meets the timing
requirement.
b) Demand Dedicated with Bus Hold (CH6 = 0, CMS =
1).
In response to a software request, the
channel acquires bus control, performs a DMA
operation until termination occurs (i .e., TC,
MC or EOP occurs), and then relinquishes bus
control.
In response to an active Low DREQ, the channel
acquires bus control, performs DMA operations
while DREQ is active Low, retains bus control
when DREQ is High but does nothing, resumes DMA
operation when DREQ is Low again and only
relinquishes bus control when the operation
terminates (Le., TC, MC, or EOP occurs).
If
the DACK signal is programmed as level (CM1B =
0), it will be active Low from the time the
channel acquires bus control to when it
relinquishes control.

c) DeIIIand Dedicated with Bus Release (C"t; = 1,
CMs = 0). In response to a software request
the channel performs DMA iterations until TC,
MC, or EOP occurs.
In response to a hardware
request, the channel performs DMA iterations
until DREQ goes inactive. The contents of the
Current Address registers and the Current
Operation Count register will not be reloaded
until TC, MC, or EOP occurs.

d) Demand Interleave (C"t; = 1, CH5 = 1). Demand
Interleave varies, depending on the setting of
Master Mode register bit MM 2 •
If MM2 is set
(CPU
interleave
is
enabled),
the
DTC
relinquishes bus control after each DMA
iteration and then re-requests it.
This
permits the CPU and other devices to gain bus
control during DMA operations. If MM2 is clear
(CPU interleave is disabled), control can pass
from one channel to the other without releasing
bus control. If only one channel is programmed
in Demand Interleave mode, the other channel
will retain control until termination or until
DREQ goes inactive, at which time control is
returned to the other channel.
Channel Mode register bit CM18 selects the waveform of DACK. The pulsed DACK (CM 18 = 1) is used
only in Flyby transactions. It is inactive during
Non-Fl yby transact ions when CM1 B is set.
Byte-word funne ling allows packing and unpacking
of byte data to facilitate high-speed transfers
between
byte-oriented
peripherals and
wordorganized memory.
The funneling option can be
used only in Flowthrough transactions.
For
transfers from a byte source to a word destination, two consecutive byte reads are performed to
move data from the source location.
These bytes
are assembled in the Temporary register.
The
Temporary register data is then written into the
destination location as a word. For word-to-byte
funneling, word data is read from the source
location into the Temporary register.
This word
is then written to the destination in two
consecutive byte writes. The byte address must be
programmed in the Current ARA and the word address
must be in the Current ARB.
Bit CM4 in the
Channel Mode register is used to specify the
transfer direction.
It is set to 0 to specify
byte-to-word funneling and to 1 for word-to-byte
funneling.
To access the high byte of the word
first, bit fG 3 of the Current ARB must be
cleared.
Bit TG3 of the Current ARB is set when
accessing the low byte of the word first, after
which the ARB address increments. Figure 9 shows
two examples of data funneling.

4-126

INTERRUPT
B·TO·C LOAD
CHAINING

ANOTHER
CHANNEL OR
RELEASE BUS

(

ANOTHER
CHANNEL OR
RELEASE BUS

EXIT)

(A) Single operation

INTERRUPT
B·TO·C LOAD
CHAINING
ANOTHER
CHANNEL OR
RELEASE BUS

(

ANOTHER
CHANNEL OR
RELEASE BUS

EXIT)
(

(B) Demand operation when
software requesting

Figure 7.

2271·010

EXIT)

(D) Demand dedicated with
bus hold (hardware request)

Flow Charts of DMA Operations

4-127
----------~-----,-.-'-.--

.•.."-.

_ ,- ,-.----~".-

...

~---

---,-.--'"

' - " ' - . - .- - . - .

CH 1: INTERLEAVE
eH 2: INTERLEAVE
CPU. NO INTERLEAVE

eH 1: INTERLEAVE
eH 2: INTERLEAVE

eH l' INTERLEAVE
eH 2: SOFTWARE DEMAND

CPU INTERLEAVE

CPU: INTERLEAVE

eH 1: DEMAND
eH 2: DEMAND/BUS RELEASE
CPU: NO INTERLEAVE

eH 1. DEMAND INTERLEAVE
eH 2: DEMANDIBUS HOLD
CPU: NO INTERLEAVE

;1
9.REQ2

9:)
t

CH2
TERMINATE

figure 8.

~
~

flow O1arts of Interleave Operations

eH 1 DEMAND/INTERLEAVE
eH 2: DEMANOI BUS RELEASE
CPU: INTERLEAVE

eH 1. DEMANnNTERLEAVE
eH 2: DEMANDSIBUS HOLD OR RELEASE

CPU: INTERLEAVE

A) Byte-to-Word Funneling: Data is moved from the byte source addressed at FA70 to the word
destination addressed from 1600.
Current ARA: 0010-FA70
Current ARB: 00xx-1604
Current Op-Count: 0003
Flip bit (CM4): 0

FA70, Address hold)
(Segment = 00, Offset
1604, Address hold/change)
(Segment = 00, Offset
(Three words)
(Data from "ARA" to "ARB")
Destination Data Distribution

TG 4 ,TG 3
ADDRESS

00-1600
00-1602
00-1604
00-1606
00-1608
oO-16oA

FFEE
DDCC
BBAA

*
*

EEFF

*
*

Source Data string

AA
BB
CC
DO
EE
FF

NOTES

AABB
CCDD
EEFF

ARB
WRITE FIRST

INC.
HIGH

DEC.
LOW

HOLD
HIGH

.
.
.

FFEE

*
HOLD
LOW

B) Word-to-Byte Funneling: Data is moved from the word source addressed from 1800 to the byte
destination addressed from 1AOO.
Current ARA: 0000-1AOO
Current ARB: 00xx-1800
Current Op-Count: 003
Flip bit (CM4): 1

(Segment = DO, Offset
1AOO, Address increment)
(Segment = 00, Offset
1800, Address hold/change)
(three words)
(Data from "ARB" to "ARA")
Destination Data Distribution

TG 4 ,TG 3
ADDRESS

00-1AOO
00-1A01
00-1A02
00-1A03
00-1A04
00-1AOS
00-1A06
00-1A07
00-1A08

AA
BB
CC
DO
EE
FF

BB
AA
99
88
77
66

AA
BB

BB
AA
BB
AA

*
*
*

*
*

INC.
HIGH

DEC.
LOW

HOLD
HIGH

HOLD
LOW

Source Data Distribution
Address

Word Data

00-17FA
00-17FC
00-17FE
00-1800
00-1802
00-1804
00-1806

6677
8899
AABB
CCDD
EEFF

NOTES

ARB
READ FIRST

BB
AA
BB

"Data unchanged

Figure 9.

2271-012

[xalllpies of Byte/Word Funneling

4-129

l0016 OTC-TO-lOOOO CPU INTERFACE

CPU and OTC On 5_ Board
The Address/Data bus and control signals of the
ZBOOO CPU and those of the lB016 DTC are directly
connected. The AS, 55, and BUSACK signals of the
CPU are connected through the reset logic to the
AS, 55, and BAI signals of the DTC. Cs/WAIT
demultiplexing logic is required for the CS/WAIT
input of the DTC if hardware waits are necessary.
The DREQ lines are connected to the request
outputs of peripheral devices. The DACK lines are
connected to the corresponding enable inputs of
the peripheral devices.
When programming for Flyby transactions, the R/W
input of the flyby peripheral should be inverted
internally by the peripheral or externally by
special logic. R/W High indicates that the flyby
peripheral should accept data, and R/W Low
indicates that the flyby peripheral should drive
data onto the bus.
The memory or non-flyby
peripheral uses the R/W High signal to indicate
that it should drive data onto the A/D bus, and it
uses the R/W Low signal to indicate that it should
accept the data from A/D bus.
When reading a slow-readable register (e. g., the
Channel Mode register) ,
external
logic for
inserting hardware Wait states is required.
The
worst-case 55 low width for the slow-readable
registers is approximately 2000 ns for a 4 MHz
Z0016 DTe.
The interrupt vector is supplied by
t.he Interrupt Save regl.s1:er (8 fast-readable
register), therefore, the 05 Low width for
Interrupt Acknowledge does not require hardware
Wait states.

Figure 10 shows the interface of the ZBOOO CPU and
the ZB016 OTC when located on the same board. No
buffer is required for BUSREQ.
The pins of
BUSREQ, EOP and INT require 3.3k or larger pullup
resistors.
When more than one DTC or other
peripherals are used, the BAI-BAO and lEI-lEO
daisy chains are used to determine priorities for
bus control and the interrupt service.

CPU and OTC on Different Boards
When the DTC and CPU are located on different
boards, the address/data and control signals pass
through the system bus.
The system bus must
provide:
•
•
•
•
•
•
•

Multiplexed Address/Data lines (ADO-AD15)
Bus timing lines [Address Strobe (AS),
Data Strobe (05)]
Read/Write (R/W) status signal
Bus control lines [Bus Request (BUSREQ) and Bus
Acknowledge (BUSACK)]
Interrupt Request lines
Status lines (ST O-ST 3 )
Ready (ROY) line

The BUSREQ pin of the OTC requires special
bidirectional buffer logic to prevent competition
between buses. The other connections are the same
as those made when the CPU and DTe are located on
the same board.
Figure 11 shows the interface configuration for a
Z-BUS system used with the l80i6 DTe.

4-130

+5V

....
V'

RESET

BUSREQ

BUSACK

RESET

AS
zaooo

CPU

I
Za016

RtW

N/S

INT

lEO

r--

-f>"A

ADDRESS/DATA BUS

JJ.

25LS373
G

+5V

I-'--

DECODER

""-

TlR

2946

,.!J.
AO·A15

SYSTEM BUS

1--

BAa

ADo·AD15

1'1

)

MULTIPLEXING
LOGIC

CSiIWAIT

STO
ST3

ADo·AD15

'"-

DTC
BM

lEI

BUSREQ

)

BAI

STO
ST3

of'"
w

+5V

-.:.....7
MIS

STO·ST3

BIW R/W AS

INT BUSREQ

~
00. 0 15

lEO BAa

WAIT

,
Figure 10.

DTC-to-Z8000 CPU Interface Configuration

RESET

RESET OUT

,---

+ 5V
~

CLK a127 ZCK

CPU

READY

r-- ~

RIW

STo-ST.

...

Qn~

IIIW

NIS

RIW

r 1l
OE

0....-

....
BUSREQ

Z-BUS

WAIT

....

:>'"

STO-ST3

BIW

NIS

RIW

ADo-ADI5

5TO-ST3

IIIW

NI~;

RIW

ADo-ADI5

STO-STa.NIS

ADDRESS

IIT
AS

STO-ST3

BIW

HIS

,..

...

ADo-ADI5

DREQ

DTI:
DACK

SNu-SN7

...

TIll

• •47

I-

AS RIW

ADo-ADI5

IUSACK

IAI
BAO
Cs/wAIT

WAIT AS

figure 11.

RDY

r---

IUSREQ

~
CS

r--

RIW AS

j:...

SLOW

MULTlPLEXING
LOGIC

~
~

I
I

BUSREQ

J. ~

ADo-Ao,5

--SNO-SN7

zao-Io

RIW

...

SLOW

BUSACK

,~~
'
I
1

Gt--

WAIT STATES CONTROL

;L-

Do-DI5

Ao-AIS

25L8373

CLR

RDY

SNo-SN7

tiJ

ADo-AD15

:...

"--B

MREQ

BUSACK

-'"

Y-

BUSREQ

~ 7:~:104

SYSTEM MEMORY

DECODER

---Y

zaOI)O

WAIT

CLOCK

DTC-b-Z-8US Syste. Interfa:e Configuratioo

IUFFERED
BUSREQ
LOGIC

SNO-SN

Z8016 DTC-TO-8086 CPU INTERfACE
To control data transactions the 8086 CPU provides
I8016 DTC provides 55
and R/W signals.
The R/W signal is valid and
stable at the T1 state, whereas R5 and WR are
valid at the T2 state. Therefore, the use of RD
or WR to generate a R/W signal violates the
R/W-valid-to-55
falling
edge
setup
time
requirement. To avoid this, the DT/R signal of
the 8086 CPU can be used to generate the R/W
signal for programming the DTC.
This interface
configuration between the I8016 DTC and the 8086
CPU is shown in Figure 12.

ARA:
ARB:
Op-Count:
Channel Mode:

lID and WR signals and the

External logic provides and controls the status
signals STO-ST3. See the Interface Support Logic
section of this application note for details.

Z8016 DTC-TO-I8DJO I-SCC INTERfACE
The I8030 Serial Communications Controller (I-SCC)
functions as a serial-to-parallel, parallel-toserial converter/controller.
Address and data
transactions through the Z-SCC are activated by
controlling the CS O and CS 1 inputs. The CS 1 must
remain active High throughout the data transaction.
The CS o Low allows the address of the
internal register to be accessed. Figure 13 shows
the DTC-to-I-SCC interface configuration.

Because of the write to 55 falling edge setup time
requirement,
Flyby
transactions
are
not
recommended unless the memory access time is fast
enough to meet this requirement.
The I-SCC
requests a DMA transfer by pulling the DTR/REQ
output Low.

I8016 DTC-TO-Z8018 I-FlO INTERfACE
The Z803B FIFO I/O Port (Z-FIO) provides an
asynchronous, 12B-byte FIFO buffer. This buffer
is expandable in both width and depth. The data
transfer logic of the Z-FrO is especially designed
to work with DMA controllers in high-speed
transfers.
Figure 14 shows the DTC-to-Z-FIO
interface configuration. The DACK output of the
DTC is connected to the DMASTB input of the
Z-FIO. When DACK is active Low, it masks the CS
for Flyby DMA operations.
The following rules
apply when programming the DTC to transfer data
between the A/D bus and the Z-FIO.
(1)

The time between the rising edge of 55 and
the next falling edge of 55 in the DTC must
meet the valid access recovery time of the
Z-FIO.
In Demand Block transfer operations, the delay of two 55 signals equals
approximately
two DMA clock cycles.
Therefore, Demand Inter leave transfer or
Single transfer operations are suggested.

(2)

The pulsed DACK bit (CM18 ) of the Channel
Mode register must be set.

(3)

For Flowthrough operations, CS of the I-FrO
must be activated.

(4)

For word-to-word transfers, two FIOs must
be used.

When interfacing with the I-SCC, the DTC should be
programmed for:
•
•

•

0000 - 2000
0072 - FFBO
0100
0000 - 1001

Single operation or Demand operation
Byte-to-byte flowthrough transfer, transferand-search, or search. An FlO is necessary in
Flyby mode due to recovery time parameters.
One wait state insertion for accessing the
Z-SCC and three wait states for the memory
cycle. lhis is to meet the SCC recovery time.

For example, to transfer data from the Z-SCC
(addressed as OO-FFBx) to memory (e.g., 00-2000 to
00-20FE), the ARA, ARB, Op-Count and Channel Mode
registers are:

4-133

0<1
rlO~
RESET

.......

8284

AEN1

AEN2

CPU

r==t-->-.,

.
~-

of"

ROY MIlO DEN

I
L.....-

WAIT

ADo·AD15

I I

"I
t-

I ADO
~

t-1

.- -

:Jill

JJ~?

DIR LS245

SHE

AO·~~15

SYSTEM BUS

RlW

.of~

OACK

GI-n

--L

f--I

I
_I G

ADS

MULTIPLEXING

lOGIC

-1
y

---,

DeCODER

1--.J
An

00·015

Z8016 DTC-to-8086 CPU Interface Configuration

CS/WAIT BAD

III

figure 12.

1--

B/W

DREa

DTC

......

Z8016

~AD15

..,

EOP

~l-<]:

,~ I

RO WR

MilO

~
9

o.r/
....

GENERATOR

ADDRESS/DATA BUS

STAT~l

SLOW

-r-- r

CONTROL BUS

ADDR

ADDRESS/DATA BUS

-=-

DS R/W

ST2

PORT 2

I
I
I

QADO·AD15

I
Z8038
Z·PIO

RJW

DECODER
ADO·AD15

• •

STO·ST3

I
I
I
I
I

ADO·AD7
ADa·AD15

DTC-to-Z-FIO Interface Configuration

Z8D16 DTC-TO-lB010 till INTERfACE

The Z8010 Memory Management Unit (MMU) contains a
table of access attributes that are individually
programmable for each segment.
The attributes
provided
are
read-only,
System-mode-only,
OMA-only, execute-only, and CPU-only. If the MMU
detects a memory access that violates one of the
attributes of a segment, the MMU interrupts the
CPU or OMA to inhibit an illegal memory access.
Figure 15 shows the OTC-to-MMU interface configuration. The MMUSYNC output of the OlC ORad with
the BUSACK signal of the CPU is connected to the
DMASYNC input of the MMU. The MMUSYNC pin of the

OlC is multiplexed with SN7. If bit MM1 of the
Master Mode register is set (Logical Addressing
mode), this pin outputs an MMUSYNC active High
pulse prior to each OMA cycle when the OlC is in
control of the system bus; when the OlC is not in
control of the system bus it outputs a Low level.
If the MM1 is clear (Physical Addressing mode),
this pin outputs the SN7 when the OlC is a bus
master and is driven with high-impedance off when
the OlC is not in control of the system bus.
The SUP output of the MMU is connected to the EOP
pin of the OlC so that OMA operation will be
terminated whenever a violation is detected.

4-136

227Hl17

+5V

-- "
I

EOP

MMUSYNC

Z8016

DTC

'"~'Q

'-J

BUSREQ

STO

ST1

ST2

RiW
STO

Z8010
MMU

ST1

AO·A23

Aa·A23

-:f

ST2

CLOCK

I---

SEGT

SNo-SNe

N/S ClK

.J.

ADs-AD15

~~
ST3

ST2

ST1

STO

R/W

CONTROL BUS

SNO·SNS

SEGMENT BUS

~
ADO·AD15

N/S
SNO·SN6

25LS373

/';>..

ST3

I---

...

CLOCK

~
BUSACK

ADO·AD15

R/W

SUP

DMASYNC

BAI

....
ADDRESS/DATA BUS

Figure 15.

DTC-to-llll Interface Configuration

ADa·AD15

ADO·AD7

INTERrACE SUPPORT LOGIC

shown assumes a timeout feature such as on the
AMZB127 clock chip. figure 17 shows the logic for
decoding the status lines to generate the MREQ,
IORQ, and MilO signals.

figure 16 shows the external
logic
for
multiplexing CS and WAIT (or ROY) signals for the
CS/WAIT input of the lB016 OTC. The slow circuit

cs
ADe

RtW
CP

AS _ _ _ _ _ _ _ _ _ _ _......... f
(A)

cs
BAO

WAIT,

tliltiplexing Logic

------------i~~----------~r_~
--~>01I~~--~~~~----~~~

BAI -----....I
CLOCK ---------~~------l_~~~

RDY

(8)
figure 16.

ROY. CS Multiplexing Logic
Multiplexing Logic for CS/WAIT Input

5T2 ...-----1 So

------I 51

5T3

Z8148
53 DECODER Vi

Eli

MEMRQ

L---l~r-----.,D--

-=
figure 17.

M/iO

Status Lines Decoding Logic

4-138

00·2271·02

Initializing
The elG
Application
Note

Zilog

October 1982
whether a given access refers to the pointer or
the target register.

INTRODUCTION

Zilog's Z8536 Counter/Timer and Parallel I/o Unit
(CIO) and Z8036 (I-CIO) can provide convenient
solutions to many microprocessor-based design
problems.
Their handshake control, bit manipulation, pattern recognition, and interrupt control
capabilities extend the range of applications far
beyond that of traditional counter/timer and
parallel I/O circuits.
This application note
gives a generalized procedure for initializing the
CIO, as well as an initialization example for one
particular application.
All comments in this
document referring to "the CIO" apply to both the
I8036 and Z8536.
References to the Z-CIO refer
only to the I8036.

A software reset is performed by writing a 1 to
the Reset bit in the Master Interrupt Control register. This causes all control bits to be reset
to 0, all port I/O lines to be at high impedance,
the Interrupt pin to be inactive, and the Interrupt Enable Output (lEO) pin to follow the Interrupt Enable Input (rEI) pin. A reset disables all
functions except a read or write to the Reset bit;
therefore the Reset bit must be cleared before any
other control bits can be programmed.

ACCESSING THE REGISTERS

INIT IAlIZATION

From the programmer's point of view, the only difference between the Z8036 and the Z8536 is the way
the registers are accessed.
In the Z8036, they
are mapped directly into the CPU's I/O address
space, and the Right Justified Address (RJA) bit
in the Master Interrupt Control register determines which address bits are used to select them.
When RJA = 0, bits AD6-AD1 are decoded, and when
RJA = 1, bits AD5-ADO are decoded.

Once the CIO has been reset and, in the Z-CIO, the
RJA bit has been programmed, it can easily be initialized for a given application by using the procedures outlined in the flowcharts of Figures 1
through 7. These flowcharts are intended to serve
more as a logical guide than as a sequential algorithm. The actual sequence of initialization is
unimportant, except that a few basic rules must be
observed:

The Z8536 uses only AD and A1 to select the registers and thus occupies only four bytes of I/O
address space. The Data registers for each port
are accessed directly using AD and A1' The Control registers (as well as the Data registers) can
be accessed using the following two-step sequence
with AD = A1 = 1: first, write the address of the
target register to an internal 6-bit pointer register; then read from or write to the target register.
An internal state machine determines

•

The ports and counter/timers should be enabled
only after their functions have been completely
specified.

•

When Ports A and B are linked, Port B should be
enabled before, or simultaneously with, the
enabling of Port A. Also, the Port Link Control (PLC) bit in the Master Configuration
Control register should be set before either
port is enabled.

SIFTWARE RESET

4-139

•

The counter/timers should be triggered only
after they have been enabled.

•

When Counter/Timers 1 and 2 are linked, the
functions of both must be specified and the
Counter/Timer Link Control (LC) bits (in the
Master Configuration Control register) must be
programmed before either counter/timer is
enabled.

•

The Master Interrupt Enable (MIE) bit in the
Master Interrupt Control register should be set
only after the functions of the CIO's interrupt
sources have been completely specified.

figure 1.

Table 1.

Port A or B Initialization

l80J6/l85J6 CID Register S_ry

Internal
Address

Read/Write

(Binary)

A5···Ao
000000
000001
000010
000011
000100
000101
000110
000111

Main Control Registers

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Master Interrupt Control
Master Configuration Control
Port A Interrupt Vector
Port B Interrupt Vector
Counter/Timer Interrupt Vector
Port C Data Path Polarity
Port C Data Direction
Port C Special I/O Control

Most Often Accessed Registers

001000
001001
001010
001011
001100
001101
001110
001111

*
*

R/W
R/W
R/W

Port A Command and Status
Port B Command and Status
Counter/Timer 1 Command and Status
Counter/Timer 2 Command and Status
Counter/Timer 3 Command and Status
Port A Oata**
Port B Data**
Port C Oata**

Counter/T~r

010000
010001
010010

R
R
R

Related Registers

Counter/Timer 1 Current Count
Counter/Timer Current Count
Counter/Timer 2 Current Count

(MS Byte)
(LS Byte)
(MS Byte)

* All bits can be read and some bits can be written.
** Also directly addressable in Z8~36 using pins AO and A1.

4-140

2256-001

Table 1.

Z80J6/Z85'6 CIO Register S_ry--Continued

Internal
Address

Read/Wdte

(Binary)
Counter/Ti_r Related Registers (continued)

010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111

R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R

Counter/Timer 2
Counter/Timer 3
Counter/Timer 3
Counter/Timer 1
Counter/Timer 1
Counter/Timer 2
Counter/Timer 2
Counter/Timer 3
Counter/Timer 3
Counter/Timer 1
Counter/Timer 2
Counter/Timer 3
Current Vector

Current Count (LS
Current Count (MS
Current Count (LS
Time Constant (MS
Time Constant (LS
Time Constant (MS
Time Constant (LS
Time Constant (MS
Time Constant (LS
Mode Specification
Mode Specification
Mode Specification

Port A Specification Registers

100000
100001
100010
100011
100100
100101
100110
100111

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Port
Port
Port
Port
Port
Port
Port
Port

A Mode Specification
A Handshake Specification
A Data Path Polarity
A Data Direction
A Special I/O Control
A Pattern Polarity
A Pattern Transition
A Pattern Mask

Port B Specification Registers

101000
101001
101010
101011
101100
101101
101110
101111

R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W

Port
Port
Port
Port
Port
Port
Port
Port

4-141

B Mode Specification
B Handshake Specification
B Data Path Polarity
B Data Direction
B Special I/O Control
B Pattern Polarity
B Pattern Transition
B Pattern Mask

Byte)
Byte)
Byte)
Byte)
Byte)
Byte)
Byte)
Byte)
Byte)

Figure 2.

Bit Port Initialization

4-142

2256-002

o
• Deskew Timers Are Used Only For Output Ports

Figure J.

2256-003

Handshake Port Initialization

4-143

Figure _.

Figure 3.

Port C Initialization

Handshake Port Initialization
(continued)

4-144

2256-004,005

*For hnked operatIon elTs 1 and 2 must
both be inItialized belore they are enabled

Figure 5.

2256-006

Counter/Timer Initialization

4-145

Figure 6.

Figure 7.

Interrupt Initialization

Pattern Recognition Initialization
4-146

2256-007, 008

APPLICATION EXAMPLE
Figure 8 shows the Z8036 configured to function
as:
•
•
•
•
•

An input handshake port
A priority interrupt controller
A squarewave generator
A watchdog timer
A general-purpose timer

In addition, there are two bits left over to
function as bit-addressable output lines.
The
following sections discuss the specific initialization procedures used to program each of the
functions.

Z8036Z-CIO

}

I f Port A is to place an interrupt vector on the
system bus during Interrupt Acknowledge transactions, then the Port A Interrupt Vector register
should be programmed with the appropriate value.
The Port A interrupt logic is enabled by writing
1s to bits D7 and D6 , and a 0 to bit D5 of the
Port A Command and Status register. This encoded
command sets the Port A Interrupt Enable (IE)
bit.
The programmer should specify the correct data
direction for the handshake bits, as well as the
initial state of RFD. Writing F4 (hexidecimal) to
the Port C Data Direction register programs PC 3
(RFD) as an output bit, PC Z (ACKIN) as an input
bit, and allows PC 1 and PCO to function as bitaddressable output lines. PCo, PC1' and PC3 can
be programmed with their initial values by writing
to the Port C Data register. In this example, PC3
(RFD) is initially High, signaling that Port A is
ready for data.

BIT·ADDRESSABlE
OUTPUT LINES

Port B as a Priority Interrupt Controller
jAPROCESSOR
INTERFACE

PB7~}

::::==
PB3

6-INPUT PRIORITY

INTERRUPT
CONTROLLER

pa2 - + - - PB1 .......--

L..-_ _ _ _ _ _...I

Figure 8.

Z-CIO Application Example

Port A as an Input Handshake Port
In Figure 8, Port A is an input port with Z-Wire
Interlocked Handshake.
(The CIO also supports
Strobed Handshake, Pulsed Handshake, and IEEE
3-Wire Handshake.) Port C provides the handshake
control signals, with PC Z as ACKIN (Acknowledge
Input) and PC3 as the RFD (Ready For Data) output.
Port A is specified as an input handshake port by
writing a 0 to bit D7 and a 1 to bit D6 of the
Port A Mode Specification register. Writing a 1
to bit DS and a 0 to bit D4 of the same register
specifies the double-buffered mode and allows the
port to interrupt the CPU when both the Buffer
register and Input Data register are full. Since
the ports reset to Interlocked Handshake, the Port
A Handshake Specification register need not be
programmed in this example.

2256-009

The priority interrupt controller is implemented
using the OR-Priority Encoded Vector (OR-PEV) mode
of pattern recognition.
When any of the six
inputs (P81-PB5 and PB77) are High, Port B's Pattern Match Flag and Interrupt Pending (IP) bits
are set. If no higher priority interrupt sources
(e.g., Port A) are under service, and if Port B's
interrupts are enabled, the CIO interrupts the
CPU. If no higher priority interrupts are pending
at the time of the next Interrupt Acknowledge
cycle, then Port B places its interrupt vector on
the bus. Encoded within this vector is the value
of the highest priority interrupt request at Port
B (with P8 7 as the highest priority input). The
CPU can then automatically branch to the appropriate service routine.
To function as a priority interrupt controller,
Port B must be specified as a bit port with OR-PEV
pattern match; hence a 06 H must be loaded into
the Port B Mode Specification register.
PB1-PBS
and PB7 must be programmed as input bits by writing 1s to bits D1 -D S and D7 of the Port B Data
Direction register. The polarity of the interrupt
request signalS can be specified independently in
the Port B Pattern Polarity register and the
sources can be individually masked using the Port
B Pattern Mask register. In this example, all of
the interrupts are active High and bits PB O and

4-147

The base interrupt vector should be loaded into
the Counter/Timer Interrupt Vector register, and
the Counter/Timer 1 interrupt logic is enabled by
writing 1s to bits D7 and 06, and a 0 to bit 05 of
the Counter/Timer 1 Command and Status register.
Also, the Counter/Timer VIS bit should be set so
that Counter /T imers 1 and 2 can generate unique
vectors. (This can be done at the same time the
MIE bit is set.)

PB6 are masked off; FFH is therefore loaded into
the Port B Pattern Polarity register, and BEH is
loaded into the Port B Pattern Mask register.
Transition pattern specifications should not be
used in the OR-PEV pattern match mode, so the Port
B Pattern Transition register should not be programmed.
The base interrupt vector should be loaded into
the Port B Interrupt Vector register, and the Port
B interrupt logic is enabled by writing 1s to bits
07 and 06' and a 0 to bit 05 of the Port B Command
and Status register.
Also, the Port B Vector
Includes Status (VIS) bit should be set so that
unique vectors can be generated for each of the
interrupt sources (this can be done at the same
time the MIE bit is set).

Counter/Timer 2 as a Squarewave Generator
While Counter/Timer
uses PB6 as its trigger
input, Counter/Timer ,2 can use PB O as its output.
The squarewave duty cycle is selected by writing a
1 to bit 01 and a 0 to bit 00 of the Counter/Timer
2 Mode Specification register.
Setting bits 07
and 06 of the same register sped fies the Continuous mode with an external output.
Since PB O
is the designated Counter/Timer 2 output whenever
Counter/Timer 2's External Output Enable (EOE) bit
is set, Port B must be programmed as a bit port
and PB O must be programmed as an output bit.

Counter/Tiaer 1 as a Watchdog Timer
In this example, Counter/Timer 1 acts as a watchdog timer, interrupting the CPU whenever a
10 ms
interval elapses without the occurrence of a rising edge on its trigger input (PB 6 ).
Each time
the timer is triggered (i.e., with each rising
edge on PB 6 ), it reloads its time constant and
begins counting down toward the terminal count.
Since the Counter/Timer 1 Time Constant is programmed to provide a timeout interval of 10 ms, a
terminal count condition always indicates that at
least 10 ms has elapsed since the last rising edge
on PB 6 .

In the Squarewave mode, the timeout interval
should be equal to half the period of the desired
squarewave (see the CIO Technical Manual, section
4.2.5, document number 00-2091-01).
A frequency
of 100 KHz corresponds to a period of 10 ~s and,
therefore, a timeout interval of 5 ~s.
With a
4MHz PCLK, the period of the input c lock signal
(PCLK/2) is o. 5 ~s, and therefore the necessary

Time Constant
The programmer must set bits 02 and 04 of the
Counter/Timer 1 Mode Specification register. Bit
02 is the Retrigger Enable (REB) bit, and 04 is
the External Trigger Enable (ETE) bit. All other
bits in this register can remain reset to o.
Since PB6 is the designated external trigger input
whenever Counter/Timer 1's ETE bit is set, Port B
must be programmed as a bit port and PB 6 must be
programmed as an input bit.
Since Counter/Timer 1 is in the Timer mode (i.e.,
it does not have an external count input), it
counts the pulses of the internal clock signa 1
(PCLK/2).
Assuming a 4 MHz PCLK, the Time
Constant should be 20,00010 for a 10 ms timeout
interval.
This can be achieved by loading 4EH
to the most-significant byte of Counter/Timer 1's
Time Constant, and 20H to the least-significant
byte of Counter/Timer 1's Time Constant.

10m

or OOOAH=

This

value

should be loaded into the Counter/Timer 2 Time
Constant registers. Since the squarewave generator does not interrupt the CPU, there is no need
to enable Counter/Timer 2's interrupt logic.

Counter Timer J as a General-Purpose Tiller
For Counter/Timer 3 to interrupt the CPU periodica lly, the user must specify the Continuous mode
by setting bit 07 of the Counter/Timer 3 Mode
Specification register.
All other bits in this
register can remain reset to o.
Loading 4E20H
to the Counter/Timer 3 Time Constant registers
specifies a 10 ms timeout interval. Writing 1s to
bits 07 and 06' and a 0 to bit 05 of the Counter/
Timer 3 Command and Status register enables the
Counter/Timer 3 interrupt logic.

4-148

When all of their functions have been completely
specified, the ports and counter/timers can be
enabled simultaneously by writing F4H to the
Master Configuration Control register.
At this
point, the counter/timers can be started by setting the Gate Command (GCB) and Trigger Command

( rCB) bits in each of their Command and Status
registers.
Finally, setting the MIE bit, along
with the appropriate VIS bits, completes the initialization.
Table 2 summarizes the initialization sequence for this application example.

4-149

Table 2.

Initialization Sequence for Application £xa.ple
Hex Value

Step

loaded

C~t6

Master Interrupt
Control

XOOOOOOO*

Reset l-ClO.

Master Interrupt
Control

XOOOOOOX

Clear Reset.

Port A Mode Specification

X100000X

Double-buffered input port,
interrupt on two bytes.

Port A Interrupt
Vector

X000010X

Interrupt vector depends on
user's system.

Port A Command
and Status

X001000X

Port A Interrupt Enable.

Port C Data
Direction

X000110X

PC z is input PC O' PC 1 and PC 3
are output.

Port C Data

X001111X

RFD is initially High. PC O
and PC 1 are initially Low.

Port B Mode
Specification

X101000X

Bit port, OR-PEV pattern
match.

Port B Data
Direction

X101011X

PB O is output.
input.

10.

Port B Pattern
Polarity

X101101X

11.

Port B Pattern
Mask

X101111X

PB O and PB 6 are masked off.

1Z.

Port B Interrupt
Vector

X000011X

Interrupt vector depends on
user's system.

13.

Port B Command and
Status

X001001X

Port B Interrupt Enable.

14.

Counter/Timer
Mode Specification

X011100X

Single cycle, External
Trigger Enable, Retrigger
Enable.

15.

Counter/Timer 1's
Time Constant-MS8s

X010110X

Time Constant = (ZO,000)10
for a 10 ms timeout.

16.

Counter/Timer 1's
Time Constant-LSBs

X010111X

PB1-PB7 are

Interrupt inputs are active
High.

If the initial state of the RJA bit is unknown, then the first access to the Master

Interrupt Control register must be performed with ADD

4-150

= O.

Table 2.

Address

ADrADo

Hex Value
loaded

17.

Counter/Timer
Interrupt Vector

X000100X

Interrupt vector depends on
user's system.

1 B.

Counter/Timer 1
Command and Status

X001010X

Counter/Timer
Enable.

19.

Counter/Timer 2's
Mode Specification

X011101X

Continuous, External Output
Enable, Squarewave duty
cycle.

20.

Counter/Timer 2's
Time Constant MSBs

X011000X

21.

Counter/Timer 2's
Time Constant LSBs

X011001X

Time Constant
5 /ls timeout.

22.

Counter/Timer 3
Mode Specification

X011110X

Continuous, no external
enable.

23.

Counter/Timer 3
Time Constant MSBs

X011010X

Time Constant = (20,000)10
for a 10 ms timeout.

24.

Counter/Timer 3's
Time Constant LSBs

X011011X

25.

Counter/Timer 3
Command and Status

X001100X

Counter/Timer 3 Interrupt
Enable.

26.

Master Configuration
Control

X000001X

Enable all ports and counter/
timers.

27.

Counter/Timer
Command and Status

X001010X

Trigger and Gate commands.

2B.

Counter /Timer 2
Command and Status

X001011X

Trigger and Gate commands.

29.

Counter/Timer 3
Command and Status

X001100X

Trigger and Gate commands.

30.

Master Interrupt
Control

XOOOOOOX

Master Interrupt Enable,
Port B Vector Includes
Status, Counter/Timer Vector
Includes Status.

Step

00·2256·01

Initialization Sequence for Application Example--Continued

4·151

COIIIIIeIlts

Interrupt

(10)10 for

Using sec With Z8000
In SDLe Protocol
Application
Note

Zilog

October 1982
This application note describes the use of the
I8030 Serial Communications Controller (I-SCC)
with the Z8000
CPU to implement a communications controller in a Synchronous Data Link
Control (SDLC) mode of operation.
In this
application, the Z8002 CPU acts as a controller
for the Z-SCC. This application note also applies
to the non-multiplexed l8530.

signal, the Z-SCC introduces extra wait cycles
in order to synchronize the data transfer
between a controller or DMA and the Z-SCC.

™

The example given here uses the block mode of data
transfer in its transmit and receive routines.

SOlC PROTOCOL

One channel of the I-SCC communicates with the
remote station in Half Duplex mode at 9600
bits/second. To test this application, two Z8000
Development Modules are used. Both are loaded with
the same software routines for initialization and
for transmitting and receiving messages. The main
program of one module requests the transmit
routine to send a message of the length indicated
by the 'COUNT' parameter. The other system
receives the incoming data stream, storing the
message in its resident memory.

DATA TRANSFER III)£S

The Z-SCC system interface supports the following
data transfer modes:
•

The CPU periodically po 11s the
Z-SCC status registers to determine if a
received character is available, if a character
is needed for transmission, and if any errors
have been detected.
Polled IlJde.

•

Interrupt IlJde. The Z-SCC interrupts the CPU
when certain previously defined conditions are
met.

•

Block/DIttA IlJde.

Data communications today require a communications
protocol that can transfer data quickly and
reliably.
Dne such protocol, Synchronous Data
Link Control (SOLC), is the link control used by
the IBM Systems Network Architecture (SNA)
communications package. SOLC is a subset of the
International Standards Organization (ISO) link
control called High-Level Data Link Control
(HOLC), which is used for international data
communicat ions.
SOLC is a bit-oriented protocol (BOP).
It
differs from byte-control protocols (BCPs), such
as Bisync, in that it uses only a few bit
patterns for control functions instead of several
special character sequences.
The attributes of
the SOLC protocol are position dependent rather
than character dependent, so the data link control
is determined by the position of the byte as well
as by the bit pattern.
A character in SOLC is sent as an octet, a group
of eight bits. Several octets combine to form a
message frame, in which each octet belongs to a
particular field. Each message contains: opening
flag, address, control, information, Frame Check
Sequence (FCS), and closing flag (figure 1).

Using the Wait/Request (W/REQ)

4-153

__- - - - - - Z E R O INSERTION/DELETION - - - - - -... 1
__- - - - - C R C ACCUMULATION - - - - -..
ZERO OR MORE
8·BIT
CHARACTERS
FLAG
(BEGINNING
OF MESSAGE
FRAME)

ADDRESS

INFORMATION

CONTROL

FCS

FLAG
(END OF
MESSAGE
FRAME)

Fields of the SOLe Transmission Frmne

Figure 1.

Both flag fields contain a unique binary pattern,
01111110, which indicates the beginning or the end
of the message frame. This pattern simplifies the
hardware interface in receiving devices so that
multiple devices connected to a common link do not
conflict with one another. The receiving devices
respond only after a valid flag character has been
detected. Once communication is established with
a particular device, the other devices ignore the
message until the next flag character is detected.

error-checking algorithm used in the frame-check
sequence, however, the maximum recommended block
size is approximately 4096 octets.
The frame check sequence field follows the
information or control field. The FeS is a 16-bit
Cyclic Redundancy Check (CRC) of the bits in the
address, control, and information fields. The FeS
is based on the CRC-Cel TT code, which uses the
polynomial (x 16 + x 12 + x 5 + 1). The 18030 z-see
contains the circuitry necessary to generate and
check the FeS field.

The address field contains one or more octets,
which are used to select a particular station on
the data link. An address of eight 1s is a global
address code that selects all the devices on the
data link. When a primary station sends a frame,
the address field is used to select one of several
secondary stations.
When a secondary station
sends a message to the primary station, the
address field contains the secondary station
address, i.e., the source of the message.

Zero insertion and deletion is a feature of SOLC
that allows any data pattern to be sent.
Zero
insertion occurs when five consecutive 1s in the
data pattern are transmitted. After the fifth 1, a
o is inserted before the next bit is sent. The
extra 0 does not affect the data in any way and is
deleted by the receiver, thus restoring the
original data pattern.

The control field follows the address field and
contains information about the type of frame
being sent.
The control field consists of one
octet that is always present.

Zero insertion and deletion insures that the data
stream will not contain a flag character or abort
sequence.
Six 1s preceded and followed by Os
indicate a flag sequence character.
Seven to
fourteen 1s signify an abort; 15 or more 1s
indicate an idle (inactive) line.
lhder these
three conditions, zero insertion and deletion are
inhibited. Figure 2 illustrates the various line
condit ions.

The information field contains any actual
transferred data. This field may be empt y or it.
may contain an unlimited number of octets.
However, because of the limit. at ions of the
A. ZERO INSERTION
FLAG

ADDRESS

CONTROL

FLAG

~_01_1_11_1_10__~_1_0_10_1_01_1__~0_1_11_1_10~1_1~__~~~:__~_0_1_11_1_11_0~1 ~~i~~~REAM

ZERO INSERTION
ADDRESS
CONTROL

= 10101011
= 01111111

B. ABORT CONDITION
xxxx111111101111110........

-..---.ABORT

FLAG

C. IDLE CONDITION
xxxx111111111111111 ..... :..

Figure 2.

Bit Patterns for Various line Conditions

4-154

2280·001, 002

The SOLC protocol differs from other synchronous
protocols with respect to frame timing. In Bisync
mode, for exsq>le, a host computer might
temporarily interrupt transmission by sending sync
characters instead of data.
This suspended
condition continues as long as the receiver does
not time out. With SOLC, however, it is invalid to
send flags in the middle of a frame to idle the
line. Such action causes an error condition and
disrupts orderly operation.
Thus, the transmitting device must send a coq>lete frame without
interruption. If a measage cannot be transmitted
completely, the primary station sends an abort
sequence and restarts the message transmission at
a later time.

SYSTEM INTERFACE
The Z8002 Development Ibdule consists of a Z8002
CPU, 16k words of dynamic RAM, 2k words of EPROM
monitor, a Z80A S10 providing dual serial ports, a
Z801 CTC peripheral device providing four
counter/timer channels, two Z80A PIO devices
providing 32 programmable I/O lines, and wire wrap
area for prototyping.
The block diagram is
depicted in Figure 3. Each of the peripherals in
the development module is connected in a
prioritized daisy chsin configuration. The Z-SCC
is included in this configuration by tying its lEI
line to the lEO line of another device, thus
making it one step lower in interrupt priority
coq>ared to the other device.

RSo232C
SERIAL
CHANNELS
(2)

ADDRESS
DATA

RESET
SWITCH

RESET

NMI
SWITCH

NON MASKABLE
INTERRUPT
SEGMENT
ADDRESS

Z8000
CPU

CONTROL
INPUTS

~~~~~
INIOUT ~~::::::::::::::::~~:
'"\I

figure 3.

2280-003

Block Diagr_ of Z81X1O OM

4-155

Two leOOO Development Modu les containing l-SCCs
are connected as shown in Figure 4 and Figure 5.
The Transmit Data pin of one is connected to the
Receive Data pin of the other and vice versa. The
le002 is used as a host CPU for loading the
modules' memories with software routines.

Z8002

LOCAL

REMOTE

z·scc

Figure 4.

Table 1.
Address
(hex)
FE01
FE03
FE05
FE07
FE09
FEOB
FEOD
FEOF
FE11
FE13
FE15
FE17
FE19
FE1B
FE1D
FE1F
FE21
FE23
FE25
FE27
FE29
FE2B
FE2D
FE2F

z·scc

Block Diagra. of Two ZBOOO CPUS

The le002 CPU can address either of the two bytes
contained in 16-bit words.
The CPU uses an even
address (16 bits) to access the most significant
byte of a word and an odd address for the least
significant byte of a word.
When the le002 CPU uses the lower hal f of the
Address/Data bus (ADO-AD 7 the least significant
byte) for byte read and write transactions during
I/O operations~ these transactions are performed
between the CPU and I/O ports located at odd I/O
addresses. Since the l-SCC is attached to the CPU
on the lower half of the A/D bus, its registers
must appear to the CPU at odd I/O addresses. To
achieve this, the l-SCC can be programmed to
select
its
internal
registers
using
lines
AD1-AD5.
This is done either automatically with
the Force Hardware Reset command in WR9 or by
sending a Select Shift Left Mode command to WROB
in channel B of the l-SCC. For this application,
the l-SCC registers are located at I/O port
address 'FExx'.
The Chip Select signal (CSO) is
derived by decoding I/O address 'FE' hex from
lines ADB-AD15 of the controller.
To select the read/write registers automatically,
the l-SCC decodes lines AD1-AD5 in Shift Left
mode. The register map for the Z-SCC is depicted
in Table 1.

FD1
FE33

FD5
FD7
FD9
FDB

FDD
FUF

Write Register
WROB
WR1B
WR2
WR3B
WR4B
WR5B
WR6B
WR7B
B DATA
WR9
WR10B
WR11B
WR12B
WR13B
WR14B
WR15B
WROA
WR1A
WR2
WR3A
WR4A
WR5A
WR6A
WR7A
A DATA
WR9
WR10A
WR11A
WR12A
WR13A
WR14A
WR15A

Read Register
RROB
RR1B
RR2B
RR3B

B DATA
RR10B
RR12B
RR13B
RR15B
RROA
RR1A
RR2A
RR3A

A DATA
RR10A
RR12A
RR13A
RR15A

INITIALIZATION
The l-SCC can be initialized for use in different
modes by setting various bits in its write
registers.
First, a hardware reset must be

4-156

2280·004

~
§

-!!!..

• ••
" ,.
8

IAD15

lAO"
IAD13

lAO"

•

•
•

•
3

AD15

AD14
AD13

All"

~
'3

IADo

,.• ••

IADo

IADl1

IAD10

•
•

7"Ea

IAD7

,.•

lADe
IADo

IAD4

of"-

§ll

lADe
IAIl:>
lAO,
IADo

.8
38

'A
SA

,.•

I
STOP

W
NVi

•
•

4MH,

ST,
ST,

•

,.
'8

AD,
ADe
AD,
AD,

iiIW

•

•
•

,
2

•

I I I

-- ,.
lA

IMREQ

,.
,.

•

lAS

iiii

,
LS
244

..
..
3.

47K!l

+~v

I D-+fv

ADe
AD,
AD,
ADo

BUSACK

...

......

'ff

I,.1:
6

1~C

,.~

....

lffijp

IADo

1AD10

,.
'3

IADl1

IADo

.......

IAD12

W
ii'ii

Niii

......

iiESl'I'
CLOCK

figure 5.

VlACK

4MHz

IAD13
WAIT

IAIl:>
lADe
lAD,
lAD,

.......
IAD14

2~~

lADe
lAO,

1AD15

244

LS Y2

A 13.
Eli

INIS

LS
243

4.7KO

•

IADo
lAO,

Eli

IRiW

T fE---1;

rp_

R-.>-

......

NIS

...
iiESl'I'

ST,

ADe
AD,

I I I

-'"

Z8002

•
•
•

NMI

..
....

WAIT

MREQ

AD10

ST,

7"E.--.8

iii

ADl1

..r

4.7KD

I
IP .

Z800Z With

sec

....

~
rI

+.v
iAii

iiii
IRiW

+.v

..,

.
..
2

•

...
.

•

Z8030
INTACK

ADo
AD,

TxDA

AD,

TRxCA

AD,
AD,

WAIT

ADs

AD,
Ao,
INT
PCLK

lEi
lEO

iii
RiW
CSI

CliO

RxDA

RTxCA

performed by setting bits 7 and 6 of WR9 to one;
the rest of the bits are disabled by writing a
logic zero.
SDLC protocol is established by selecting a SDLC
mode, sync mode enable, and a x1 clock in WR4. A
dats rste of 9600 baud, NRl encoding, snd a
character length of eight bits are among the other
options that are selected in this example (Table

2).
Note that WR9 is accessed twice, first to perform
a hardware reset and again at the end of the
initialization sequence to enable interrupts. The
programming sequence depicted in Table
2
establishes the necessary parameters for the
receiver and transmitter so that they are ready to
perform communication tasks when enabled.

Table 2. Progr~ng Sequence
for Initialization

Enable (VIE) bits set. The Program Status Area
Pointer (PSAP) is loaded with the address 1"04400
using the Load Control instruction (LDCTL). If the
lBOOO Development Module is intended to be used,
the PSAP need not be loaded by the programmer
because the development module's monitor loads it
automatically after the NMI button is pressed.
Since VIS and Status low are selected in WR9, the
vectors listed in Table 3 will be returned during
the Interrupt Acknowledge cycle.
Of the four
interrupts listed, only two, Ch A Receive
Character Available and Ch A Special Receive
Condition, are used in the example given here.

Table ,.

Vector
(hex)

PS
Address'>
(hex)

Interrupt

28
2A
2C
2E

446E
4472
4476
447A

ChA Transmit Buffer Empty
Ch A External Status Change
ChA Receive Char. Available
Ch A Special Receive Condition

Value
Register (hex)
WR9
WR4

CO
20

WR10
WR6
WR7
WR2
WR11

BO
AB
7E
20
16

WR12

WR13
WR14

WR15
WR5

00
60

WR3

WR1

WR9

Effect
Hardware reset
x1 clock, SDLC mode, sync mode
enable
NRl, CRC preset to one
Any station address e.g. "AB"
SDLC flag (01111110) = "7E"
Interrupt vector "20"
Tx clock from BRG output, TRxC
pin = BRG out
Lower byte of time constant =
"CE" for 9600 baud
Upper byte = D
BRG source bit = 1 for PCLK as
input, BRG enable
External Interrupt Disable
Transmit B bits/character SDLC
CRC
Rx 8 bits/character, Rx enable
(Automatic Hunt mode)
Rxint on 1st char & sp. cond.,
ext into disable
MIE, VIS, status Low

The Z8002 CPU must be operated in System mode to
execute privileged I/O instructions. So the Flag
and Control Word (FCW) should be loaded with
system normal (S/N), and the Vectored Interrupt

Interrupt Vectors

*Assuming that PSAP has been set to 4400 hel<, "PS
Address" refers to the location in the Program
Status Area where the service routine address is
stored for that particular interrupt.

TRANSMIT OPERATIIW

To transmit a block of data, the main program
calls up the transmit data routine.
With this
routine, each message block to be transmitted is
stored in memory, beginning with location 'TBUF'.
The number of characters contained. in each block
is determined by the value assigned to the 'COUNT'
parameter in the main module.
To prepare for transmission, the routine enables
the transmitter and selects the Wait On Transmit
function; it then enables the wait function. The
Wait On Transmit function indicates to the CPU
whether or not the Z-SCC is ready to accept data
from the CPU. If the CPU attempts to send data to
the Z-SCC when the transmit buffer is full, the
Z-SCC asserts its Wait line and keeps it low until
the buffer is empty. In response, the CPU extends
its I/O cycles until the Wait line goes inactive,
indicating that the Z-SCC is ready to receive
data.

4-158

The CRC generator is reset and the Transmit CRC
bit is enabled before the first character is sent,
thus including all the characters sent to the
I-SCC in the CRC calculation.
The I-SCC I S transmit underrun/EOM latch must be
reset sometime after the first character is
transmitted by writing a Reset Tx Underrun/EOM
command to WRO.
When this latch is reset, the
I-SCC automatically appends the CRC characters to
the end of the message in the case of an underrun
condition.
Finally, a three-character delay is introduced at
the end of the transmission, which allows the
I-SCC sufficient time to transmit the last data
byte and two CRC characters before disabling the
transmitter.

REDEIVE OPERATION
Once the Z-SCC is initialized, it can be prepared
to receive the message.
First, the receiver is
enabled, placing the Z-SCC in Hunt mode and thus
setting the Sync/Hunt bit in status register RRO
to 1.
In Hunt mode, the receiver searches the
incoming
data
stream for
flag
characters.
Ordinarily, the receiver transfers all the data
received between flags to the receive data FIFO.
If the receiver is in Hunt mode, however, no data
transfer takes place until an opening flag is
received.
If an abort sequence is received, the
receiver automatically re-enters Hunt mode.
The
Hunt status of the receiver is reported by the
Sync/Hunt bit in RRO.
The second byte of an SDLC frame is assumed by the
Z-SCC to be the address of the secondary stations
for which the frame is intended.
The I-SCC
provides several options for
handling this
address. If the Address Search Mode bit D2 in WR3
is set to zero, the address recognition logic is
disabled and all the received data bytes are
transferred to the receive data FIFO.
In this
mode, software must perform any address recognition. I f the Address Search Mode bit is set to
one, only those frames with addresses that match
the address programmed in WR6 or the global
address (all 1s) will be transferred to the
If the Sync Character Load
receive data FIFO.
Inhibit bit (D1 ) in WR3 is set to zero, the
address comparison is made across all eight bits
of WR6.
The comparison can be modified so that

only the four most significant bits of WR6 need
match the received address.
This alteration is
made by setting the Sync Character Load Inhibit
bit to one.
In this mode, the address field is
still eight bits wide and is transferred to the
FIFO in the same manner as the data.
In this
application, the address search is performed.
When the address match is accomplished, the
receiver leaves the Hunt mode and establishes the
Receive Interrupt on First Character mode.
Upon
detection of the receive interrupt, the CPU
generates an Interrupt Acknowledge Cycle.
The
I-SCC returns the programmed vector %2C.
This
vector points to the location %4472 in the Program
Status Area which contains the receive interrupt
service routine address.
The receive data routine is called from within the
receive
interrupt
service
routine.
While
expecting a block of data, the Wait On Receive
function is enabled.
Receive read buffer RR8 is
read and the characters are stored in memory
location R8UF.
The Z-SCC in SDLC mode automatically enab les the CRC checker for all data
between opening and closing flags and ignores the
Receive CRC Enable bit (D3) in WR3. The result of
the CRC calculation for the entire frame in RR1
becomes valid only when the End Of Frame bit is
set in RR1. The processor does not use the CRC
bytes, because the last two bits of the CRC are
never transferred to the receive data FIFO and are
not recoverable.
When the Z-SCC recognizes the closing flag, the
contents of the Receive Shift register are
transferred to the receive data FIFO, the Residue
Code (not applicable in this application) is
latched, the CRC error bit is latched in the status FIFO, and the End Of Frame bit is set in the
receive status FIFO.
When the End Of Frame bit
reaches the top of the FIFO, a special receive
condition interrupt occurs.
The special receive
condition register RR1 is read to determine the
result of the CRC calculation.
If the CRC error
bit is zero, the frame received is assumed to be
correct; if the bit is 1, an error in the
transmission is indicated.
Before leaving the interrupt service routine,
Reset Highest IUS ( Interrupt Under
Service) ,
Enable Interrupt on Next Receive Character, and
Enter Hunt Mode commands are issued to the Z-SCC.

4-159

If receive overrun error is made, a special
condition interrupt occurs.
The Z-SCC presents
vector %2E to the CPU, and the service routine
located at address %447A is executed. Register RR1
is read to determine which error occurred.
Appropriate action to correct the error should be
taken by the user at this point. Error Reset and
Reset Highest IUS commands are given to the Z-SCC
before returning to the main program so that the
other lower-priority interrupts can occur.
In addition to searching the data stream for
flags, the receiver also scans for seven
consecutive
1s,
which
indicates
an
abort
condition.
This condition is reported in the
Break/Abort bit (D7) in RRO. This is one of many
possible external status conditions. As a result

transitions of this bit can be programmed to cause
an external status interrupt. The abort condition
is terminated when a zero is received, either by
itself or as the leading zero of a flag. The
receiver leaves Hunt mode only when a flag is
found.

SOfTWARE
Software routines are presented in the following
pages. These routines can be modified to include
various other options (e.g., SDLC Loop, Digital
Phase Locked Loop etc.). By modifying the WR10
register, different encoding methods (e.g., NRII,
FMO, FM1) other than NRI can be used.

4-160

Appendix
Software Routines
plzasm
1.3
LOC
OBJ CODE

STMT SOURCE STATEMENT
1
2
3

SOLC MODULE
$LISTON $TTY
CONSTANT
WROA
\FE21
\FE21
RROA
RBUF
'5400
PSAREA
H400
COUNT
12
GLOBAL MAIN PROCEDURE
ENTRY

,.
,.
,.
,.
,.

0000
0000
0002
0004
0006
0008
OOOA
OOOC

7601
4400
701D
2100
5000
3310
OOlC

IBASE ADDRESS FOR WRO CHANNEL AI
IBASE ADDRESS FOR RaO CHANNEL AI
IBUFFER AREA FOR RECEIVE CHARACTER I
ISTART ADDRESS FOR PROGRAM STAT AREAl
IND. OF CHAR. FOR TRANSMIT ROUTINE I

LOA

Rl,PSAREA

LDCTL
LD

PSAPOFF,Rl
RO,U5000

Rl('UC),RO

OOOE
0010
0012
0014

7600
00D6'
33!0
0076

LDA

RO,REC

Rl(U76) ,RO

0016
0018
OOlA
OOlC
OOlE
0020
0022
0024
0026

7600
OOFA'
3310
007A
5FOO
0034'
5FOO
008C'
E8FF

LDA

RO,SPCOND

0028
0029
002A
002B
002C
0020
002E
002F
0030
0031
0032
0033

AS
48
45
4C
4C
4F
20
54
48
45
52
45

0034

TaUF,

Rl(n7A) ,RO

CALL

INIT

CALL

TRANSMIT

BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL

\AB
'H'
'E'
'L'
'L'

END

MAIN

ILOAD PSAPI
IFCW VALUE(i5000) AT '441C FOR VECTORED I
IINTERRUPTSI
IEXT. STATUS SERVICE ADDR. AT '4476 INI
IPSAI
ISP.COND.SERVICE ADDR AT '447A IN PSAI

ISTATION ADDRESSI

'0'

'T'
'H'
'E'
'R'
'E'

4-161

1****************** INITIALIZATION ROUTINE FOR

GLOBAL
ENTRY

0034
0034
0036
0038
003A
003C
003E
0040
0042
0044
0046
0048
004A
004C
004E
004F
0050
0051
0052
0053

2100
OOOF
7602
004E'
2101
FE21
0029
A920
3A22
0018
8004
EEF8
9E08
12
CO
08
20
14
80

0054
0055
0056
0057
0058
0059
005A
005B
005C
0050
005E
005F
0060
0061
0062
0063
0064
0065
0066
0067
0068
0069

OC
AB
OE
7E

ALOOP.

18
CE
1A
00
1C
03
1E

00
OA
60
06
C5
02
08

006A 12
006B 09
006C

END

********************* •• ,

RO,U5

INO.OF PORTS TO WRITE TOI

LOA

R2,SCCTAB

IADDRESS OF DATA FOR PORTSI

Rl,tWROA

ADDB
INC
OUTIB

RL1,@R2
R2
@R1,@R2,RO

IPOINT TO WROA,WRlA ETC THRO LOOPI

RO
NZ,ALOOP

lEND OF LOOP?I
INO,KEEP LOOPING I

TEST
JR
RET
SCCTAB. BVAL
BVAL
BVAL
BVAL
BVAL
BVAL

20
16

z-sec

INIT PROCEDURE

2*9
'CO
2*4
'20
2*10

IWR9-HARDWARE RESET I
IWR4-X1 CLK,SDLC,SYNC MODEl
IWRlO.CRC PRESET ONE,NRZ,FLAG ON IDLE,I
I FLAG ON UNDERRUN I

\80

BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL

2*6
'AB
2*7
'7E
2*2
'20
2*11

BVAL
BVAL
INIT

2*9
'09

IWR6- ANY ADDRESS FOR SDLC STATIONI
IWR7-SDLC FLAG CHARI
IWR2-INT VECTOR %201

\16

IWRl1-Tx CLOCK , TRxC OUT-BRG OUTI

2*12
'CE
2*13

IWR12- LOWER TC-CEI

2*14
'03
2*15

IWRl4-BRG ON,BRG SRC-PCLKI

IWRl3- UPPER TC-OI

IWRl5-EXT INT. DISABLE I

'00

2*5
'60
2*3
%C5
2*1
'08

IWRS-Tx 8 BITS/CHAR, SDLC CRCI
IWRl-ADDR SRCH,REC ENABLE I
IWRl-RX INT ON 1ST' SP COND,I
IEXT INT DISABLEI
IWR9- MIE,VIS,STATUS LOWI

.****************** RECEIVE ROUTINE ***************·********************1

RECEIVE A BLOCK OF MESSAGE
006C
006C
006E
0070
0072
0074
0076
0078
007A
007C
007E
0080
0082
0084
0086
0088
008A
008C

C828
3A86
FE23
6008
00A8
3A86
FE23
2101
FE31
2102
OOOE
2103
5400
3Al8
0230
9B08

GLOBAL
ENTRY

RECEIVE PROCEDURE
LOB
OUTB

RLO,li28
WROA+2,RLO

IWAIT ON RECV.I

LOB

RLO,%A8

OUTB

WROA+2,RLO

Rl,tRROA+16

R2,tCOUNT+2

ICOUNT+2 CHARACTERS TO READI

Rl,'RBUF

IRECEIVE BUFFER IN MEMORYI

INDRB

@R3,@Rl,R2

IREAD THE ENTIRE MESSAGE I

RET
END RECEIVE

4-162

IENABLE WAIT FNC. SP. CONDo INTI

1****************
I
I

GLOBAL
ENTRY

008C
008C
008E
0090
0092
0094
0096
0098
009A
009C
009E
OOAO
00A2
00A4
00A6
00A8
OOAA
OOAC
OOAE
OOBO
00B2
00B4
00B6
00B8
OOBA
OOBC
OOBE
OOCO
00C2
00C4
00C6
00C8
OOCA
OOCC
OOCE
0000
0002
0004
0006

2102
0028'
C868
3A86
FE2B
C800
3A86
FE23
C888
3A86
FE23
C880
3A86
FE21
2101
FE3l
2100
0001
C869
3A86
FE2B
3A22
0010
C8CO
3A86
FE21
2100
OOOB
3A22
0010
2100
039E
F081
C800
3A86
FE2B
9E08

DEL.

TRANSMIT ROUTINE ************************************1
SEND A BLOCK OF EIGHT DATA CHARACTERS
I
THE BLOCK STARTS AT LOCATION THUF
I

TRANSMIT PROCEDURE
LO

R2,.TBUF

IPTR TO START OF BUFFERI

LOB
OUTH

RLO,n68
WROA+l 0, RLO

IENABLE TRANSMITTER I

LOB
OUTH

RLO,nOO
WROA+2,RLO

IWAIT ON TRANSMIT I

LOB
OUTH

RLO,n88
WROA+2,RLO

IWAIT ENABLE I

LOB
OUTH

RLO,n80
WROA,RLO

IRESET TxCRC GENERATOR I

Rl,'WROA+l6

IWR8A SELECTED I

RO,n

LOB
OUTH

RLO,n69
WROA+IO,RLO

ISDLC CRCI
IWRSA-TxCRC ENABLE I

OTIRB

@Rl,@R2,RO

ISEND ADDRESSI

LOB
OUTB

RLO,nCO
WROA,RLO

IRESET TxUND/EOM LATCHI

RO,.COUNT-l

OTIRB

@Rl,@R2,RO

ISEND MESSAGE I

RO,'926

ICREATE DELAY BEFORE DISABLING I

DJNZ
LOB
OUTH

RO,DEL
RLO,.O
WROA+lO,RLO

ITRANSMITTER SO THAT CRC CAN BEl
ISENTI
10ISABLE TRANSMITTER I

RET
END TRANSMIT

1************* RECEIVE INT. SERVICE ROUTINE *************************1

0006
0006
0008
OOOA
OODC
OODE
OOBO
00E2
00E4
00E6
00E8
OOEA
OOEC
OOEE
OOFO
00F2
OON
00F6
00F8
OOFA

93F3
93F2
93Fl
93FO
3A94
FE21
A690
E602
SFOO
006C'
C838
3A86
FE21
97FO
97Fl
97F2
97F3
7BOO

GLOBAL REC PROCEDURE
ENTRY
PUSH
@RlS,R3
PUSH
@R1S,R2
@RlS,Rl
PUSH
PUSH
@RlS,RO
INB
RLl,RROA

RESET.

END REC

IREAD STATUS REG RROAI

BITB
JR
CALL

RL1,.0
Z,RESET
RECEIVE

ITEST IF Rx CHAR SETI
IYES CALL RECEIVE ROUTINE I

LOB
OUTH

RLO,n38
WROA,RLO

IRESET HIGHEST IUSI

POP
POP
POP
POP
IRET

RO,@R1S
Rl,@RlS
R2,@RlS
R3,@RlS

4-163

I •• •••••••••• SPECIAL CONDITION INTERRUPT SERVICE ROUTINE ••••••••••••••• 1
GLOBAL SPCOND PROCEDURE
ENTRY

OOFA
DOPA
oorc
OOPE
0100

93FO
3A84
FE23
A687

0102
0104
0106
0108
010A
010C
010E
0110
0112
0114
0116
0118
011A
011C
011E

E603
C820
3A86
FE21
C830
3A86
FB21
C808
3A86
FE23
C838
3A86
PE21
97FO
7BOO

0120

PUSH
INB

@R1S,RO
RLO,RROA+2

I READ ERRORS I

BITH
RLO,t7
lEND OF FRAME 11
IPROCESS OVERRUN, FRAMING ERRORS IF ANYI
JR
Z,RESE
LOB
RLO,n20
OUTH
WROA,RLO
I YES,ENABLB INT ON NEXT REC CHARI
RESEI

LDB
DUTH

RLO,n30
WROA,RLO

I BRROR RESET I

LOB
OUTH

RLO,n08
WROA+2,RLO

IWAIT DISABLB,RzINT ON 1ST OR SP COND.I

LOB
OUTH

RLO,n38
WROA,RLO

IRESET HIGHEST IUSI

POP
IRET

RO,@RlS

END SPCOND
END SDLC

4-164

00·2280·01

SCC In Binary
Synchronous Communication
Application
Note

Zilog

October 1982
Zllog's Z8030 Z-SCC Serlal Communlcatlons Controller IS one of a family of components that are
Z-BUS~ compatible wlth the Z8000· CPU. Comblned
with a Z8000 CPU (or other eXlsting 8- or 16-bit
CPUs with nonmultlplexed buses when uSlng the
Z8530 SCC), the Z-SCC forms an Integrated data
communlcations controller that is more cost effectlve and more compact than systems Incorporatlng
UARTs, baud rate generators, and phase-locked
loops as separate entities.

•

Block/DMA Mode. USing the Walt/Request (W/REQ)
signal, the Z-SCC Introduces extra walt cycles
to synchronize data transfer between a
CPU or OHA controller and the Z-SCC.

The approach examlned here implements a communlcations controller in a Blnary Synchronous mode of
operabon, with a Z8002 CPU actwg as controller
for the Z-SCC.

Three variations of character-oriented synchronous
communications are supported by the Z-SCC: Monosync, 8lsync, and External Sync (Figure 1).
In
Monosync mode, a Single sync character IS transmitted, which IS then compared to an Identical
sync character in the receiver. When the receiver
recognizes this sync character, synchronization is
complete; the recel ver then transfers subsequent
characters Into the receiver FIFO in the Z-SCC.

The example given here uses the block mode of data
transfer in its transmit and receive routines.

SYNCHRONOOS MODES

One channel of the Z-SCC IS used to communicate
wlth the remote station in Half Duplex mode at
9600 bits/second. To test thlS application, two
Z8000 Development Modules are used.
Both are
loaded with the same software routines for Initialization and for transmitting and receiving
messages. The main program of one module requests
the transmit roubne to send a message of the
length indicated In the 'COUNT' parameter. The
other system receives the Incoming data stream,
storing the message In ItS resident memory.

DATA

SYNC

DATA

CRC1

CRC21

CRC1

CRC21

•. MONOSYNC MODE

SYNC

DATA

b. BISYNC MODE
EXTERNAL
SYNC SIGNAL

DATA TRANSfER MODES

The Z-SCC system interface supports the following
data transfer modes:

c. EXTERNAL SYNC MODE

•

Polled Mode. The CPU periodlCally polls the
Z-SCC status registers to determine the availability of a received character, If a character
is needed for transmisslOn, and if any errors
have been detected.
Interrupt Mode. The Z-SCC wterrupts the CPU
when certain previously defIned conditions are
met.

2278-001

4-165

~'f:

Figure 1.

DA_T_A_ _
C_RC_1_ _
C_RC_2...1

Synchronous Modes of eo....nication

Bisync mode uses a 16-blt or 12-bit sync character
In the same way to obtain synchronization. External Sync mode uses an external signal to mark the
beginning of the data fIeld; i.e., an external
input pln (SYNC) indicates the start of the Information fIeld.

Two Z8000 Development Modules containing Z-SCCs
are connected as shown in figure 3 and figure 4.
The Transmit Data pin of one is connected to the
Receive Data pin of the other and vice versa. The
Z8002 is used as a host CPU for loading the
modules' memories with software routines.

In all synchronous modes, two Cycllc Redundancy
Check (CRC) bytes can be concatenated to the message to detect data transmission errors. The CRC
bytes ~nserted ~n the transm~tted message are compared to the CRC bytes computed to the receiver.
Any d~fferences found are held in the rece~ve
error fIfO.

The Z8000 CPU can address either of the two bytes
contained in 16-bit words. The CPU uses an even
address (16 bits) to access the most-sigmflcant
byte of a word and an odd address for the leastsignificant byte of a word.

SYSTEM INTERFACE

The Z8002 Development Module consists of a Z8002
CPU, 16K words of dynam~c RAM, 2K words of EPROM

......C
SERIAL

ADDRESS

CHANNELS

DATA

(2)

RESET
SWITCH

NMI

SWITCH

NON MASKABLE

INTERRUPT

zaooo
CPU

CONTROL
INPUTS

EXT~~~~~
INIOUT

/'----------'\1

\.----------.11

figure 2.

Block Diagru of Z8000 lit

monitor, a Z80A SIO providing dual serial ports, a
Z80A CTC peripheral device providing four counter/
timer channels, two Z80A PIO devices providing 32
programmable I/O lines, and wire wrap area for
prototyplng.
The block diagram is depicted in
figure 2. Each of the peripherals in the development module is connected in a prioritized daisy-chain configuration. The Z-SCC is included In this
configuration by tYing its lEI line to the lEO
line of another device, thus making it one step
lower in interrupt priority compared to the other
device.

4-166

_!!D___

Z8001

z·scc
LOCAL

figure 3.

_ ,!!!x.£. _

.2I~c

... - - - - .... - - - - RTxC

TRxC

RxD

TxD

Z8001

z·scc

REMOTE

Block Diagr_ of Two Z8000
DevalopEOt Modules

2278-002, 003

~
~

La
243

r--IAD,S

AOts

lAD,.

AD,.

AD'3

IAD'3

IAD'2

8r---i

IADl1

IAD,O

IAOg

IADa

+6V

AD12

Ao,o

ADe

ADa

.
~

MREQ

~
~

f'"
.....
(J)
'-.J

rom
n~

M.
ST,
Mo

IAD,

IADo

:r1ADa
AD,
35
ADs

AD.

iiiW~

NISI-!!

1A La

°1:: I I

AD!

AD,

AD3

ADo

GBAGAB

aUSACK

........
,...

TI
L

to.

...

+5V

4.7KD

~~ III

IAD12

-.::::=~C>----t~...J

Yi4

--11><>---'

1.~ iiEi!f
HIli
14
30

to.

....--f
I

IAD11 -------I

IAD'0
IADo -

IADa

OMH. :

i.
I

lAD"
lAO"

f
1Y

HIli
RESi'f

Jrn
6V

IAD'5-

CLOCK

rigure

fl.

l8002 with

sec

VlACK

IADo

lAo..

IADz

243

Z80ao

Z8002

Y7!oI

r--IAD2

La Y2

iDS

iMREQ

T ..l.

IAD3

'"
10

IX
Following is a listing of the software used in
this application. It is assumed that the PSAP has
been initialized and that the ZB002 is in System
mode when it enters the MAIN procedure.
The
background task is simulated by the "JR
$"
instruction.
Under ZINIT, each address offset shown is keyed to
the name of the corresponding register, and each
loaded value is keyed to the effect of the load.

4-187

LOC

08J COl)[

STMT SOURCE STATEMENT

1 RECEIVE MODULE
2 EXTERNAL ZINIT PROCEDURE
3 INTERNAL CONSTANT
BUF
! MEMORY BUFFER!
4
:= %6000
5
FIOBASE := 1.FOOO
!FlO BASE ADDR!
FOATA
:= %F01F
!FIO DATA REG!
6
7
CRO
:= %F001
8
ISR1
:= %F007
ISR3
:= %FOOB
9
0
11 GLOBAL MAIN PROCEDURE
12 ENTRY

0000

!CONTROL REG O!
!INTR STATUS REG 1!
!INTR STATUS REG 3!

0000 7C01

14
15
16

!DISABLE VECTORED
INTR!

! INITIALIZE flO!
LDK
RO,f/1
OUT
FIOBASE,RO

0002 BD01
0004 3B06 FOOO

0008 2101 FOOO
OOOC 5FOO 0000*

19
20
21

LD
CALL

!INITIALIZE VECTOR TABLE!
LDCTL R1,PSAP
!LOAD PROG STATUS
AREA PTR!
LD
28( R1) ,#%4000 !LOAD FCW FOR
VECTORED INTR!

R1,#FIOBASE
ZINIT

0010 7015

0012 4015 001C

0016 4000
001B 7602 0038'

LDA

R2,FULL

001C 6F12 0026

38( R1) , R2

0020 7602 0084'

LDA

R2,PAT

0024 6F12 0032

50(R1) ,R2

0028 7602 007A'

LDA

R2,EMPTY

002C 6F12 0022

34(R1),R2

0030 2101

31
32
33

R1,#BUF

0034 7C05
0036 E8FF

34
35

EI
JR

0038

36 END MAIN
37
38 INTERNAL FULL PROCEDURE
39 ENTRY
40

0038

6000

! RESET FlO WITH
EVEN ADDR!

!LOAD ADDR OF FULL
PROCEDURE!
!ENTER ADDR IN
VECTOR TABLE!
!ENTER ADDR OF
PAT PROCEDURE!
!ENTER ADDR IN
VECTOR TABLE!
!LOAD ADDR OF
EMPTY PROCEDURE!
!ENTER ADDR IN
VECTOR TABLE!

!LOAD ADDR OF MEMORY
BUFFER!
!ENABLE VECTORED INTR!
!BACKGROUND TASK!

VI
$

4-188

LOC

08J

aJI)[

SJMT SOIReE STATDENT

0038 2100 OCDC
003C 3A06 fD07
0040 3A86 fD01

41
42
43

LD
OUTB
OUTB

RO,#%OCDC
ISR1,RHO
CRO,RLO

0044
0048
004C
0050
0052
0056

44
45
46
47
4B
49
50
51
52
53
54
55
56
57
58
59
60

LD
OUTB
OUTB
CLRB
LO
EI

RO,I1%20EO
ISR3,RHO
ISR3,RLO
RL3
R2,I1fDATA
VI

INIRB

1IR1,IIIIR2, RO

!REAO DATA FROM FLO!

DI
DEC
LD
OUTB
OUTB
LD
OUTB
OUTB

VI
R1
RO,'%AOCO
ISR3,RHO
ISR3,RLO
RO,'%OE9C
ISR1,RHO
CRO, RLO

!DISABLE VECTORED INTR!

2100
3A06
3A86
8CB8
2102
7C05

20EO
fD08
fDOB
fD1F

0058 3A20 0010
005C
005E
0060
0064
0068
006C
0070
0074

7C01
AB10
2100
3A06
3A86
2100
3A06
3A86

AOCO
fDOB
fDOB
OE9C
fD07
fD01

0078 7BOO
007A
007A
007A
007C
007E
0082
0084

BD01
C302
3A36 fD08
7BOO

0084
0084
0086
008A
008E

A8BO
2104 OA06
3A46 fD07
3AC6 fD07

0092 7BOO
0094

0000

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76

!SET PATTERN MATCH IE!
!DISABLE LOWER DAISY
CHAIN!
!CLEAR FULL IP & IUS!
!CLEAR FULL IE!
!INITIALIZE COUNT!
!ENABLE VECTORED INTR!

! CLEAR FULL IP!
!SET FULL IE!
!CLEAR PATTERN MATCH IE!
!ENABLE LOWER
DAISY CHAIN!

IRET
END FULL
INTERNAL
ENTRY
LDK
LDB
OUTB
IRET
END EMPTY

EMPTY PROCEDURE
RO,#1
RH3,#%02
ISR3,RH3

INTERNAL PAT PROCEOURE
ENTRY
INCB
RL3
LD
R4,U%OA06
OUTB
ISR1,RH4
OUT8
77
ISR1,RL4

!TERMINATE BLOCK MOVE!
!CLEAR EMPTY IP AND IUS!

!INCREMENT COUNT!
!CLEAR PATTERN MATCH IP!
!CLEAR PATTERN MATCH IUS!

78
IRET
79 END PAT
80 END RECIEVE
1
2 ZIN MODULE
3 GLOBAL ZINIT PROCEDURE
4
THIS IS A GENERAL ROUTINE USED
5
6
TO INITIALIZE A Z-BUS PERIPHERAL
7
IN THIS EXAMPLE If INITIALIZES
THE Z-FlO.
8
9

4-189

LOC

08J COlE

0000 7602 0014'
0004 6103 0024'
0008 2029
OOOA A920
OOOC 3A22 0318
0010 ECFB
0012 9E08

0014
0015
0016
0017
0018
0019
001A
001B
001C
0010
001E
001F
0020
0021

01
00
01
OC
15
50
13
03
1B
55
OB
CC
01
9C

0022 0008
0024

STMT SOURCE STATDENT

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

R1
R2
R3

= PERIPHERAL BASE
= ADDR OF TABLE
= NO. OF BVfES TO

ADDR
BE OUfPUT

ENTRY
LOA
LD
LOOP:
LOB
INC
OUTIB

R2,TAB
R3,COUNT
RL 1,1002
R2
001 ,1002, R3

JR
REf

NOV ,LOOP

BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL
BVAL

%01
%00
%01
%OC
%15
%50
%13
%03
%1B
%55
%OB
\\lCC
%01
%9C

TAB:

COUNT:
WVAL
END ZIN! f
END ZIN

!CONTROL REGISTER O!
! CLEAR RESE f !
!CONTROL REGISTER O!
!INTERLOCKED HS PORT!
!CONTROL REGIS fER 3!
! INPUT TO CPU!
!CONTROL REGISTER 2!
!ENABLE PORT 2!
IPATfERN MATCH REGISTER!
!PATTERN IS 551
!INTERRUPT STATUS REGISTER 3!
!SET FULL ANO EMPTY IE!
!CONTROL REGISTER O!
!SET MIE BIT!

«$- TAB)/2

4-190

-1)

00-2307-01

Zilog Sales Offices and Technical Centers

West

Midwest

East

United Kingdom

Sales & Technical Center
Zilog, Incorporated
1315 Dell Avenue
Campbe ll, CA 95008
Phone: (408) 370-8120
TWX : 910-338-762 1

Sales & Tech nical Center
Zi log , Incorpora ted
951 North Plum Grove Road
Suite F
Schaumbu rg, IL 60195
Phone: (312) 885-8080
TWX: 910-291-1064

Sales & Technical Cen ter
Zi log , Incorporated
Corporate Place
99 South Bedford St .
Burlington, MA 01803
Phone: (617) 273-4222
TWX: 710-332- 1726

Zilog (U .K.) Limited
Zilog House
43-53 Moorbridge Road
Maidenhead
Berkshire, SL6 8PL England
Phone: 0628-39200
Telex : 848609

Sales & Technical Cen ter
Zilog, Incorpora ted
28349 Chagrin Blvd.
Suite 109
Woodmere, OH 44122
Phone: (216) 831 -7040
FAX: 216-831-2957

Sales & Tech nica l Cente r
Zilog , Incorporated
240 Cedar Knolls Rd.
Ceda r Knolls, NJ 07927
Phone: (201) 540-1671

Sales & Technical Center
Zilog , Incorpora ted
18023 Sky Pa rk Circle
Suite J
Irvine, CA 92714
Phone: (714) 549-2891
TWX: 910-595-2803
Sales & Technical Center
Zilog , Incorporated
15643 Sherman Way
Sui te 430
Van Nuys , CA 91406
Phone: (213) 989-7485
TWX: 910-495-1765
Sa les & Techn ical Center
Zilog , Incorporated
1750' 12th Ave. N.E.
Suite D161
Bel levue, WA 98004
Phone: (206) 454 -5597

Zilog, Inc.
00-232Q.Ol

South
Sales & Tec hnica l Center
Zilog, Incorporated
4851 Keller Springs Road ,
Suite 211
Dallas, TX 75248
Phone: (2 14) 931-9090
TWX: 910-860-5850
Zilog, Incorporated
7113 Burnet Rd .
Suite 207
Aust in, TX 78757
Phone: (512) 453-3216

1315 Dell Ave ., Campbell, California 95008

Technical Center
Zilog, Incorporated
3300 Buckeye Rd.
Suite 40 1
Atlanta , GA 3034 1
Phone: (404) 451-8425
Sales & Technica l Center
Zilog , Incorporated
1442 U.S. Hwy 19 South
Suite 135
Clearwater, FL 33516
Phone: (8 13) 535-557 1
Zilog , Inco rporated
613- B Pitt S1.
Cornwall, Ontario
Canada K6J 3R8
Phone: (613) 938-1121

France
Zilog, Incorporated
Cedex 31
92098 Paris La Defense
France
Phone: (1) 334-60-09
TWX : 611445 F

West Germany
Zilog GmbH
Eschenstrasse 8
D-8028 TAU FKI RCHEN
Munich , West Germany
Phone: 89-612-6046
Telex : 529110 Zilog d.

Japan
Zilog , Japan K.K.
Konparu Bldg. 5F
2-8 Akasaka 4-Chome
Minato-Ku, Tokyo 107
Japan
Phone: (81) (03) 587-0528
Telex : 2422024 AlB: Zilog J

Telephone (408)370-8000

TWX 91 0-338-7621
Printed in USA

Source Exif Data:
File Type : PDF File Type Extension : pdf MIME Type : application/pdf PDF Version : 1.3 Linearized : No XMP Toolkit : Adobe XMP Core 4.2.1-c043 52.372728, 2009/01/18-15:56:37 Create Date : 2013:08:25 10:58:22-08:00 Modify Date : 2013:08:25 16:25:58-07:00 Metadata Date : 2013:08:25 16:25:58-07:00 Producer : Adobe Acrobat 9.55 Paper Capture Plug-in Format : application/pdf Document ID : uuid:6fd5fd6d-6679-964e-b9cd-4cd657ed93ab Instance ID : uuid:18296682-7fbe-714a-a308-148cc4bc85d3 Page Layout : SinglePage Page Mode : UseNone Page Count : 391
EXIF Metadata provided by EXIF.tools

1983_Zilog_Microprocessor_Applications_Reference_Book_Volume_2 1983 Zilog Microprocessor Applications Reference Book Volume 2

Navigation menu

Versions of this User Manual:

Views

Navigation