1984_AMI_MOS_Products_Catalog_2ed 1984 AMI MOS Products Catalog 2ed

1984_AMI_MOS_Products_Catalog_2ed 1984_AMI_MOS_Products_Catalog_2ed

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1984 MOS Products Catalog .
"A.r"'~"" d Ed ition

t \

-} GOULD
AIM I Semiconductors

-} GOULD
AMII Semiconductors

Information furnished by Gould AMI in this publication is believed to be accurate. Devices
sold by Gould AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Gould AMI makes no warranty, express, statutory, implied, or by
description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Gould AMI makes no warranty of merchantability or
fitness for any purposes. Gould AMI reserves the right to discontinue production and change
specifications and prices at any time and without notice.
Advanced Product Description means that this product has not been produced in volume, the
specifications are preliminary and subject to change, and device characterization has not
been done. Therefore, prior to programming or designing this product into a system, it is
necessary to check with Gould AMI for current information.
Preliminary means that this product is in limited production, the specifications are preliminary
and subject to change. Therefore, prior to programming or designing this product into a
system, it is necessary to check with Gould AMI for current information.

These products are intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically
not recommended without additional processing by Gould AMI for such application.

MOS Products Catalog-30M-6/84-Printed in U.S.A.

AIMII.
• "-

A Subsidiary
of Gould Inc.

1984 MOS Products Catalog
Second Edition

AMI.---------r.
r

A Subsidiary
of Gould Inc.

Introduction
American Microsystems, Inc. headquartered in Santa Clara, California is the semiconductor industry leader in the
design and manufacture of custom MOSIVLSI (metal-oxide-silicon very-Iarge-scale-integrated) circuits. It manufactures special circuits for the leading computer manufacturers, telecommunications companies, automobile
manufacturers and consumer product companies worldwide. AMI is a wholly owned subsidiary of Gould, Inc.
Along with being the leading designer of custom VLSI, AMI is a major alternate source for the S6800 8-bit microprocessor family and the S80 Family of microprocessors, which are integrated systems in silicon based on the popular
Z80™ microprocessor. This microprocessor family combines advanced microprocessor, memory, and custom VLSI
technologies on a single chip.
The company provides the market with selected low power CMOS Static RAMs, and 16K, 32K, 64K, 128K and 256K
ROMs for all JEDEC pinouts or as EPROM replacements.
The most experienced designer of systems-oriented MOSIVLSI communication circuits, AMI provides components
for station equipment, PABX and Central Office Switching systems, data communications and advanced signal processing applications.
AMI is a leading innovator in combining digital and analog circuitry on a single silicon chip, and is a recognized
leader in switched capacitor filter technology.
Processing technologies range from the advanced, small geometry, high performance silicon gate CMOS to mature
PMOS metal gate and to silicon gate N-Channel. Over 27 variations are available.
AMI has design centers in Santa Clara; Pocatello, Idaho; and Swindon, England. Wafer fabrication plants are in
Santa Clara and Pocatello, and assembly facilities are in Seoul, Korea and the Philippines. A joint venture company
in Graz, Austria Microsystems International, serves the European semiconductor market with complete design and
manufacturing capabilities. A recently formed joint venture company in Japan, Asahi Microsystems Inc., designs
and will in the future produce integrated circuits for the Japanese and Pacific Basin market.
Field sales offices are located throughout the United States, in Europe and in the Far East. Their listing, plus those
of domestic and international representatives and distributors appear on pages B.39 through B.47 of this publication.
Z80 is a registered trademark of Zilog, Inc.

Table of Contents

A. Indices

o
o

Numerical
Functional
Cross-Reference

1. Gate Arrays
2. Standard Cells
3.
4.
5.
6.

Spectrum of Custom Solutions
Communication Products
Consumer Products
Memories

Microprocessors/Microcomputers
7. S6800 Family
8.
9.
10.
11.

S80 Family
S9900 Family
Future Products
Application Note Summary

B. General Information
o MOS Handling
o MOS Processes
o Product Assurance
o Packaging
o Ordering Information
o Terms of Sale
o AM I Sales Offices
o Domestic Representatives
o Domestic Distributors
o International Representatives and Distributors

•
•
•I
•I

•
•I
--

~ ASu~idia~ ~~~~~~~~~~~~~~~~~
~

of Gould Inc. _~~~~~~~~~~~~~~~_

Indices

Indices
Numerical Index
Device
810110 .......................
810430 .......................
81602 .........................
823128A ....................
8231288 ....................
82333 .........................
82350 .........................
82364A ......................
823648 ......................
8232568 ....................
823256C ....................
825089 ............... ,. ... ...
82550A ......................
82559A .... ... .......... .....
825598 ......................
82559E ......................
82559F ......................
82560A ................... :..
82560G .. .............. ......
825601 .
82561 A ......................
82561C ......................
825610 .......................
825610E ....................
82563A ......................
82569 .........................
82569A ................. .....
823698 ......................
82369C ......................
82579 .........................
825910 ............ ...... .....
825912 ............ ...... .....
82600 .........................
82601 .........................
82604 .........................
82605 .........................
82688 .........................
82709A ......................
82742 .........................
82743 .........................
82747 .........................
82748 .........................
82809 .........................
88PCP/M·1 ...............
828211 .......................
828212A .......... ..... .....
8282128 ....................
828214 .....................

Page

Device

5.51
5.55
7.76
6.43
6.43
6.21
7.84
6.31
6.31
6.47
6.4 7
4.58
4.3
4.10
3.10
4.10
4.10
4.25
4.32
4.32
4.34
4.34
4.64
4.72
4.42
4.43
4.43
4.50
4.50
4.21
4.80
4.80
5.36
5.36
5.39
5.39
5.61
5.69
5.45
5.45
5.48
5.48
5.32
4.96
4.97
4.99
4.99
4.104

828215 ..................... 4.124
82859 ......................... 5.23
83506 ......................... 4.87
83507 ......................... 4.87
83507 A .. ........ ....... ...... 4.87
83522 ....................... 4.128
83524 ....................... 4.138
835212 ..................... 4.134
83525A ..................... 4.141
835258 ..................... 4.141
83526 ....................... 4.148
83526M .................... 4.155
83528 ....................... 4.156
83529 ....................... 4.166'
83530 ....................... 4.175
83620 ........................... 5.3
EVK3620 .............. ...... 5.14
836128 ....................... 5.10
84003 ......................... 5.66
84036 ......................... 5.73
844230 ........ .......... ..... 4.89
844231 .. ............. ........ 4.89
844232 ....................... 4.89
844233 ...... ................. 4.89
844234 ......... .............. 4.89
84520 ......................... 5.15
84521 ......................... 5.23
84534 ......................... 5.29
84535 ......................... 5.26
850240 .... ............. ...... 5.63
850241 ....................... 5.63
850242 ....................... 5.63
85101 ........................... 6.2
85101 L·1 ...................... 6.2
86364 ......................... 6.35
86464 ......................... 6.38
86501 ........................... 6.2
86501L ......................... 6.2
86501 L·1 ...................... 6.2
86514 ........................... 6.3
86516 ........................... 6.7
86551 ......................... 7.87
86551A ....................... 7.87
86800 ........................... 7.3
868AOO ......................... 7.3
868800 ......................... 7.3
86801 ........................... 7.9
86802 ......................... 7.44

Page

A.2

Device

Page

868A02 ....................... 7.44
868802 ...... ................. 7.44
86303 ........................... 7.9
86303N/R ..................... 7.2
868045 ..................... 7.105
86805 ......................... 7.52
86808 ......................... 7.44
868A08 ....................... 7.44
868808 ....................... 7.44
86809 ......................... 7.70
868A09 .. ........ ............. 7.70
868809 ....................... 7.70
86809(E) ..................... 7.71
868A09(E) ................... 7.71
868809(E) ................... 7.71
86810 ....................... 7.137
868A10 ..................... 7.137
868810 ..................... 7.137
86821 ......................... 7.95
868A21 ....................... 7.95
868821 ....................... 7.95
868A316 ..................... 6.15
868A332 ............ ......... 6.18
868A364 .... ................. 6.24
8688364 .... ........ ......... 6.24
868A365 .... ........ ......... 6.27
86840 ....................... 7.101
868A40 ..................... 7.101
868840 ..................... 7.101
86846 ....................... 7.119
86850 ....................... 7.123
868A50 ..................... 7.123
868850 ..................... 7.123
86852 ....................... 7.131
868A52 ..................... 7.131
868852 ..................... 7.131
86854 ....................... 7.134
868A54 ..................... 7.134
868854 ..................... 7.134
883 ............................... 8.3
89900 ........................... 9.3
89901 ......................... 9.15
89901·4 ...................... 9.15
89902 ......................... 9.26
89902·4 .......... ...... ...... 9.26

Indices
Functional Index
Device

Page

Device

Page

Communications Products

Modems and Filters

Station Products
82550A .....................
S2559A .....................
825598 .....................
82559E .....................
82559F
82859 .......................
82560A .....................
82560G .....................
82560G/I .....................
82561 .......................
82561 A .....................
S2561C .....................
82563A .....................
S2569 .......................
S2569A .....................
S25698 .....................
S2569C .....................
S25089 .....................
S2561 0 .....................
S25610E ...................
82579 .......................
S2591 0 .....................
S25912 .....................
PCM Products
S3506 .......................
S3507 .......................
S3507A .....................
S44230 .....................
S44231 .....................
S44232 .....................
S44233 .....................
S44234 .....................
Signal Processors
S28211 .....................
S28212A ...................
8282128 ...................
S28214 .....................
828215 .....................
S8PC/PM/1 ...............
Modems and Filters
83522 .......................
835212 .....................
83524 .......................
83525 .......................

83525A .....................
835258 .....................
83526 .......................
83526M ....................
83528 .......................
83529 .......................
83530 .......................

• • • • • • • • • • • • • • • 11 • • • •

4.3
4.10
4.10
4.10
4.10
4.23
3.25
4.32
4.32
4.34
4.34
4.34
4.42
4.43
4.43
4.50
4.50
4.58
4.64
4.72
4.21
4.80
4.80
4.87
4.87
4.87
4.89
4.89
4.89
4.89
4.89
4.97
4.99
4.99
4.104
4.124
4.96
4.128
4.134
4.138
4.141

4.141
4.141
4.148
4.155
4.156
4.166
4.175

Consumer Products
Driver Circuits
82809 ....................... 5.32
84520 ....................... 5.15
84521 ....................... 5.23
84535 ....................... 5.26
84534 ....................... 5.29
Speech Products
836128 ..................... 5.10
EVK3620 .................. 5.14
Remote Control Circuits
82600 ....................... 5.36
82601 ....................... 5.36
82604 ....................... 5.39
82605 ....................... 5.39
82742 ....................... 5.45
82743 ....................... 5.45
82747 ....................... 5.48
82748 ....................... 5.48
Organ Circuits
810110 ..................... 5.51
810430 ..................... 5.55
82688 ....................... 5.61
850240 ..................... 5.63
850241 ..................... 5.63
850242 ..................... 5.63
Clock Circuits
84003 ....................... 5.66
82709A ..................... 5.69
AID Converter and Digital
Scale Circuit
84036 ....................... 5.73
Gate Arrays ............... 1.2

A.3

Device

Page

Memory Products
RAMs
86810
868A10 .....................
868810 .....................
86810-1 .....................
85101L .....................
85101 L-1 ..................
86501L .....................
86514 .......................
86516 .......................
ROMs
S68A316 ...................
868A332 ...................
82333 .......................
868A364 ...................
8688364 ...................
868A365 ...................
82364A .....................
823648 .....................
86364 .......................
86464 .......................
823128A ...................
8231288 ...................
8232568 ...................
823256C ...................

6.15
6.18
6.21
6.24
6.24
5.27
6.31
6.31
6.35
6.38
6.43
6.43
6.47
6.47

Microprocessorsl
Microcomputers
S6800 Family
S6800 .......................
S68AOO .....................
868800 .....................
86801 .......................
S6802 .......................
868A02 .....................
S68802 .....................
86808 .......................
868A08 .....................
S68808 ...................
S6803 .......................
86803N/R .................
86805 .......................
86809 .......................
S68A09 .....................
868809 .....................

7.3
7.3
7.3
7.9
7.44
7.44
7.44
7.44
7.44
7.44
7.9
7.2
7.52
7.70
7.701
7.70

• • • 11 • • • • • • • • • • • • • • • • • •

7.137
7.137
7.137
6.2
6.2
6.2
6.2
6.3
6.7

Indices
Functional Index
Device

Page

Microprocessorl
Microcomputers (Continued)
6800 Family

86809(E) ...................
868A09(E) .................
868809(E) .................
81602 .......................
82350 .......................
86551 .......................
86551A .....................
86821 .......................
868A21 .....................
868821 .....................
86840 .......................
868A40 .....................

7.71
7.71
7.71
7.76
7.84
7.87
7.87
7.95
7.95
7.95
7.101
7.101

Device

Page

Device

868840 .....................
868045 .....................
86846 .......................
86850 .......................
868A50 .....................
868850 .....................
86852 .......................
868A52 .....................
868852 .....................
86854 .......................
868A54 .....................
868854 .....................
86810 .......................
868A10 .....................
868810 .....................
86810-1 .....................

7.101
7.105
7.119
7.123
7.123
7.123
7.131
7.131
7.131
7.134
7.134
7.134
7.137
7.137
7.137
6.2

S80 Family

A.4

883 ...........................

Page

8.3

9900 Family

89900 .......................
89980 .......................
89901 .......................
89901-4 .....................
89902 .......................
89902-4 ..... ....... .........

9.3
9.10
9.15
9.15
9.26
9.26

Standard Cell Circuits

8tandard Cells ......... 2.2

Cross Reference Guide
Communication Products
Cross Reference by Manufacturer

Manufacturer
AMD
Cherry

Part Number

AMI Functional
Equivalent Part

7910

S3530
S2561

820X

Part Number

AMI Functional
Equivalent Part

Mostek

MK 5089

25089

Mostek

MK 50981

2560A

Manufacturer

ERSO

CIC 9187

2559

Mostek

MK 50982

2560A

ERSO

CIC9110E

S25610

Mostek

MK 50991

2560A

EXAR

XR2120

S35212

Mostek

MK 50992

2560A

G.I.

ACF 7310,12,7410

3526

Mostek

MK 5116

3507

G.I.

ACF 7323C

3525

Mostek

MK 5151

3507

G.I.

ACF 7363C

3525

Mostek

MK 5170

2562/2563

G.I.

ACF 7383C

3525

Mostek

MK 5175

25610

G.I.

AY5-9100

2560A

Mostek

MK 5387

2559

G.I.

AY5-9151

2560A

Mostek

MK 5389

25089

G.I.

AY5-9152

2560A

Mostek

5091

2559

G.I.

AY5-9153

2560A

Mostek

5092

2559

G.I.

AY5-9154

2560A

Mostek

5094

2559

G.I.

AY5-9158

2560A

Mostek

5382

2569

G.I.

AY5-9200

2563A

Mostek

5170

2563A

G.I.

AY3-9400

2559

Mostek

5175

S25610

G.I.

AY3-9401

2559

Mostek

5380

2559

G.I.

AY3-9410

2559

Motorola

MC 14400

3507

G.I.

AY5-9800

3525

Motorola

MC 14401

3507

Hitachi

HD 44211

3507

Motorola

MC 14402

3507

Hitachi

HD 44231

3506

Motorola

MC 14408

2560A

Intel

2913

3507

Motorola

MC 14409

2560A

Intel

2914

3507

Motorola

MC14412

S3530

Motorola

MC6170

S35212
S3526/S3526M

Intersil

ICM 7206

2559

Mitel

MT 4320

3525

Motorola

MC145433

Mitel

ML 8204

2561A

Motorola

MC145432

S3526M*

Mitel

ML 8205

2561A

Motorola

MC14413

S3526/S3526M

Mitel

MT 8865

3525

National

TP53130

S2579

Mitel

8204

S2561

National

TP5088

S2579

MK 5087

2559E

National

MF10

S3528/S3529

Mostek
• For Direct Replacement

Note: X Denotes any number

A.5

Cross Reference Guide
Communication Products
Cross Reference by Manufacturer

Part Number

AMI Functional
Equivalent Part

National

MF6

53528/53529

National

MM74HC942

53530

To!.

National

MM74HC943

53530

National

MM 5393

2560A

National

MM 5395

National

Manufacturer

NEC

Manufacturer
5iliconix

Part Number

AMI Functional
Equivalent Part

OF 322

2560A

TCM 170X

52550

To!.

TCM 5089

525089*

To!.

TCM 509X

2559

To!.

TCM 508X

2559

TP5700

52550

Tolo

TCM 150X

52561

",PO 7720

2811

Tolo

TM599532

53530

Nitron

NC 320

2560A

551

201

53525A

Phillips

TOA 1077

2559

551

202

53525A

RCA

CD 22859

2559

551

203

53525A

Reticon

R5632

S35212"

Teltone

M-980

S3524

Reticon

R5612

53526/53526M

Teltone

M-900

53525A

Reticon

R5604

53528/53529

Teltone

M-907

53525A

Reticon

R5605

53528/S3529

Teltone

M-917

53525A

Reticon

R5606

S3528/S3529

Teltone

M-927

S3525A

Reticon

R5609

S3528/S3529

Teltone

M-947

S3525B*

Reticon

R5611

S3529

Teltone

M-948

S3525A

Reticon

R5612

S3528/S3529

Teltone

M-056

S3525A

Reticon

R5614

S3528/S3529

Teltone

M-957

S3525A

Reticon

R5615

S3528/S3529

Teltone

M-967

S3525A

Reticon

R5616

S3528/S3529

Reticon

R5620

S3528/S3529

Reticon

R5621

S3528/S3529

Reticon

R5622

S3528/S3529

Sanyo

7350

S2560A

Sanyo

7351

S2560A

Seiko

S7220A

S2560A

Seiko

STC2560

S2560A

Seiko

S7210A

S25610

Sharp

408X

2559

Siliconix

OF 320

2560A

Siliconix

OF 321

• For Direct Replacement

2560A
Note: X Denotes any number

A.6

Cross Reference Guide
Memory Products
CMOS RAMs
Vendor

256x4

AMI

1Kx 1

1Kx4

S5101

4Kx 1

S6514

FUJITSU

6514/8414

8404

6508

6514
4334
6514

6504
4315
6504

146508
74C929
6508

6514
444/6514

HARRIS
HITACHI
INTERSIL

6561
435101
6551

MOTOROLA
NATIONAL
NEC

145101
74C920
5101

OKI
RCA

573
5101

574
1821

5115
1825

5104

SSS
TOSHIBA

5101
5101

5102
5508

5514

5504

6508

146504
6504

BYTE WIDE NMOS ROMs
Vendor
AMI

2Kx8

4Kx8

4Kx8*

8K x 8·24 Pin

8K x 8·28 Pin

16Kx8

32Kx8

S68A316

S68A332

S2333

S68A364

S2364A

S23128A

S23256B

AMD

AM9218

9232

9233

AM9264

AM9265

AM92128

NEC/EA

J.lPD2316

J.lPD2332A

J.lPD2332B

J.lPD8364

J.lPD2364

J.lPD23128

F68316

F3532

F3533

F3564

R03·9333

R03·9364

R03·9365

SPR·128

FAIRCHILD

J.lPD23256

FUJITSU
GI
GTE

R03·9316
2316

2332

2364

MOS
MOSTEK
MOTOROLA

MPS2364
MK34000
MCM68A316

MK36000

SIGNETICS

2616

2632

SYNERTEK

SY2316

SY2332

OKI

MK38000

SY2333

MCM65256

2664A

2664AM

23128

23256

SY2364

SY2365

SY23128

SY23256

R2364A

R2364B

VT23129

VT23256

MSM2916

ROCKWELL

R2316

SGS

M2316

TOSHIBA

MK37000

MCM68365

MCM68A332

R2332

TSU23Hl

NATIONAL
VTI

TSU333·2
MM52132
VT2332

MM52164
VT2333

VT2365A

*Pin compatible with 2732 EPROM

A.7

Microprocessor Family

,
If.ff(1.
~Qf ~~I
.......l i1
.~

DESCRIPTION

S1602

UART (UNIVERSAL ASYNCHRONOUS
RECEIVERITRANSMITTER)

S2350

USRT (UNIVERSAL SYNCHRONOUS
RECEIVERITRANSMITTER)

S6800

MPU (MICROPROCESSOR)

S6801

8·BIT MICROCOMPUTER 2K ROM,
128 BYTES RAM, UART, TIMER, 110

S6B02

8·BIT MICROPROCESSOR WITH CLOCK
AND 128 BYTES RAM

S6803

S6801 WITHOUT ROM

S6803NR

S6803 WITHOUT RAM

S6805

8·BIT MICROCOMPUTER WITH 1.1K BYTES
ROM, 64 BYTES RAM, TIMER, 110

S6808

MICROPROCESSOR AND CLOCK

ENHANCED 8·BIT MPU

S6809E

ENHANCED 8·BIT MPU EXTERNAL
CLOCK INPUT

S6810

RAM (128x8)

S6810·1

RAM LOW COST (575ns)

S6821

P
C
0
P
C
0
P
C
0
P
C
0
P
C

P
C
0
P
C
0
P
C
0
P
C

S6809

PIA

S6840

TIMER

S6846

ROM, 110, TIMER

S6850

ACIA

S6852

SSOA

S6854

AOLC

S68045

CRT CONTROLLER

S6551/6551A

ACIAlBAUO RATE GENERATOR

S9900

16·BIT MICROPROCESSOR

S9980A

16·BIT /APROCESSOR-8·BIT DATA BUS

S9901

PCI

S9902

ACC

PART NUMBER CONVENTIONS
[JO FUNCTIONAL REPLACEMENT

DEVICE

AMI PRODUCT PREFIX

FAMILY DESIGNATION

BUS SPEED (OPTIONAL)
NONE - 1MHz
A = 1.5MHz
B = 2.0MHz

P
C
0
P
C
0
P
C
0

C
0
P
C

S1883, M88868A, AY-5·1013, AY·3·1015, TR1863, DO
TR1602, TMS6011, NATIONAL 5303, SMC2502

MC6800, H0468000, F6800
X

MC6801, H06801X
MC6802, H046802, F6802

MC6803

MC6803NR

P
C
0
P
C

P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C

REPLACES

P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0
P
C
0

MC6805P2, H06805S
MC6808, H046808, F6808
MC6809, H06809, F6809E
MC6809E, H06809E, F6809E
MC6810, H046810, F6810

MC6821, H046821, F6821, SY6520 DO
MC6840, H046840, F6840
X

MC6846, H046846, F6846
MC6850, H046850, F6850
MC6852, H046852, F6852
MC6854, H046854, F6854

MC6845, H046505, SY6545DD
SY6551, ROCKWELL 6551
TMS9900

P
C
0
P
C
0
P
C
0

TMS9980A
TMS9901
TMS9902

PART DESIGNATION

QUALIFIER (OPTIONAL)
NONE 0-70"C
I -40/+ 85"C
[X]

AVAILABLE

A.S

PACKAGE TYPE
P
PLASTIC
C
CERAMIC
D = CERDIP

NOT AVAILABLE OR NOT APPLICABLE

Gate Arrays

Gate Arrays
I. Introduction

tools to allow customers to design, simulate, and layout circuits using AMI gate array and standard cell families.
Figure 1-3 show the economic tradeoffs between gate
array, standard cell, and full custom, all of which are offered
by AMI. The best solution for your needs will depend upon
your volume requirements and circuit complexity.

As the semiconductor industry has marched into the new
era of VLSI, a new market has appeared-fast turn custom
or, as it is now called, semicustom. AMI, a leader in custom
MOS since 1966, is also a leader in this new semicustom
market. AMI has introduced CAD software and hardware
Figure 1. Cost vs. Volume Alternatives

1200 GATE CMOS DEVICE

Ii
Ii

1\
20

GATE ARRAYS

:,\.

STD. CELLS,
CUSTOM

\\"

-":'::-!.-:::--.-...-.:~ - - - -- -- ------- - ------

--.-P--.-.--.-.

90 100 110 120 130 140 150 160

VOLUME(K)

Figure 3. Cost vs. Volume Alternatives

Figure 2. Cost vs. Volume Alternatives

2000 GATE CMOS DEVICE

400 GATE CMOS DEVICE

GATE ARRAYS
STD. CEllS
GATE ARRAYS

CUSTOM

STD. CEllS

CUSTOM

10 20 30 40 50 60 70 80 90 100 110120 130 140 150 160

10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160
VOLUME(K)

VOlUME(K)

1.2

Gate Arrays
The simplest semlcustom ICs are gate arrays. A gate array
consists of uncommitted component matrices of transistors (usually P- and N-type for CMOS) that allow userdefined Interconnections through a single or double layer
of metal. Since arrays employ fixed component locations
and geometries, AMI can process the wafers up to the
metallization stage and Inventory the wafers for future
customlzatlon. Thus gate arrays look like late mask programmable ROMs and benefit from this large-volume production because they appear to be a standard product. AMI
can offer them at an economical price and with fast prototyping and production turn on spans.
The second semlcustom product group is standard cells.
Standard cells employ fully customized process/mask sets
and must pass through all process steps before a userspecified circuit is completed. To design such chips, AMI
customers use precharacterized functional cells from AMI
cell libraries. Placing and routing the cells is done on AMI
computers using specially developed software. Standard
cell designs usually result in smaller chips since only the
component structures required for the user specified circuit are included, thus chips designed with cells are less
expensive than gate array designed chips.
The key to success in this new market is flexibility. Flexibility to the user entails: low risk circuit implementation, short

development span, lower development cost, lower piece
part cost (over discrete Implementations), easy to change or
modify, enhanced product features, etc; For the manufacturer, flexibility means: ease of manufacture, economies of
scale, and easy Interface with customers. One last pOint:
AM I offers the user the opportunity to migrate at a low cost,
from a gate array to a standard cell (or possibly full custom)
to further enhance his/her product. By using analog cells,
significant advances in chip function integration are at the
user's disposal.
In addition, AMI offers a wide selection of packages to meet
specific user needs. AMI offers the CAD tools needed to
work in the new market. AMI also offers the training required to move customers quickly and easily into this new
technology. See the "Custom Solutions" section in this
catalog for more details.

2 Micron Products
AMI is developing 2 micron CMOS technology to support
the next generation of gate arrays and standard cells. These
products will offer size and performance improvements of
up to 50% from their 3 micron counterparts.
Introduction of the first 2 micron gate array family is planned for fourth quarter 1984 and is expected to offer
capabilities of up to 10,000 gates.

1.3

•

Gate Arrays
II. Gate Arrays

General Description

• Arrays of Uncommitted CMOS Transistors Programmed
by Metal Layer Interconnect to Implement Arbitrary Digital Logic Functions
• Multiple Developmental Interfaces: AMI or Customer
Designed

AMI's gate array products consist of arrays of CMOS
devices whose interconnections are initially unspecified.
By "programming" interconnect at the metal layer mask
level, virtually arbitrary configurations of digital logic can
be realized in an LSI implementation.
AMI gate array designs are based on topological
cells-Le., groups of uncommitted silicon-gate N-Channel
and P-Channel transistors-that are placed at regular
intervals along the X and Y axes of the chip with intervening polysilicon underpasses. Pads,input protection circuitry, and uncommitted output drivers are placed around
the periphery.
Compared to SSIIMSI logic implementations, AMI's gate
array approach offers lower system cost and, in addition,
all the benefits of CMOS LSI. The lower system cost is due
to significant reductions in component count, board area
and power consumption. Product reliability, a strong function of component count, is thereby greatly enhanced. And
compared to fully custom LSI circuits, the gate array offers
several advantages: low development cost; shorter development time; shorter production turn-on time; and low unit
costs for small to moderate production volumes.
AMI's CMOS gate arrays are offered in three families: the
5-micron UA series, the 3-micron single metal GA series,
and the 3-micron double metal GA-D series. The 5-micron
UA series has been in production since 1980 and well over
one hundred circuits have been produced in that technology. The 3-micron GA and GA-D series are the highspeed high-density devices fabricated in AMI's state-ofthe-art 3-micron CMOS processes.
The CMOS technology used for these products is AMI's
5-micron, oxide-isolated, silicon gate CMOS process. This
process offers all the conventional advantages of
CMOS- Le., very low power consumption, broad power
supply voltage range (3V to 12V ± 10%), and high noise immunity-as well as dense circuits with high performance.
Gate propagation delays are in the five to ten ns range for 5
volt operation at room temperature. AMI gate array products can be supplied in versions intended for operation
over the standard commercial temperature range (O°C to
+ 70°C), the industrial range (- 40°C to + 85°C), or the full
military range (- 55°C to + 125°C). MIL-STD-883 Class B
screening, including internal visual inspection and

• Three Array Families-5-Micron Single Metal CMOS,
3-Micron Single Metal CMOS, and 3-Micron Double Metal
Versions
• Multiple Array Configurations- From 300 to 1260 Gates
for 5-Micron Devices, and 500 to 4000 Gates for 3-Micron
Devices
• Quick Turn Prototypes and Short Production Turn-On
Time
• Economical Semicustom Approach for Low-to-Medium
Production Volume Requirements
• Advanced Oxide-Isolated Silicon Gate CMOS Technology
• High Performance-2 to 3ns Typical Gate Delay for 3Micron Devices
• Broad Power Supply Range
• TIL or CMOS Compatible 1/0
• Up to 124 1/0 Connections
• Numerous Package Options
• Full Military Temperature Range (- 55°C to 125°C) and
MIL-STD-883 Class B Screening Available
Fiv~Micron

Gate Array Family

The family of 5-micron CMOS products is offered in six
configurations with circuit complexities equivalent to 300,
400,540,770,1000, and 1260 two-input gates, respectively.
All pads can be individually configured as inputs, outputs,
or 1/0's. Input switching characteristics can be programmed for either CMOS or TIL compatibility. LS buffer
output drivers will support CMOS levels of two low power
schottky TTL loads. TIL buffer outputs will also provide
CMOS levels and are capable of driving up to six LS TTL
loads. All output drivers can be programmed for tri-state or
open drain (open collector) operation as required.

1.4

Gate Arrays
D.C. characteristics for the 5 micron gate array family are
summarized in Table 4.

high temperature burn-in, is offered. Similarly, customerspecified high reliability screening is available for commercial and industrial applications.

Table 2. Gate Array MSI/LSI Functional Macros

Table 1. Gate Array SSI Functional Macros
DESCRIPTION

INVERTER
DUAL· INVERTER DRIVER
TRIPLE-INVERTER DRIVER
QUADRUPLE·INVERTER DRIVER
QUINTUPLE-INVERTER DRIVER
2-INPUT NAND
3-INPUT NAND
4-INPUT NAND
5-INPUT NAND
2-INPUT AND
3-INPUT AND
4-INPUT AND
2-INPUT NOR
3-INPUT NOR
4-INPUT NOR
5-INPUT NOR
2-INPUT OR
3-INPUT OR
4-INPUT OR
EXCLUSIVE OR
EXCLUSIVE NOR
2-IN ANDI2-IN NOR
2-WIDE AND·OR-INVERT
2-IN OR/2-IN NAND
2-WIDE OR-AND-INVERT
INTERNAL TRI-STATE DRIVER
2 TO 1 MULTIPLEXER
SET-RESET LATCH
CLOCKED LATCH
CLOCKED LATCH WITH SET
D FLIP-FLOP WITH RESET
D FLIP-FLOP WITH SET
D FLIP-FLOP SET AND RESET
TTL LEVEL TRANSLATOR

TTL FUNCTIONAL
EQUIVALENCE

1/6
1/6
1/6
1/6
1/6
1/4
1/3
1/2

LS04
LS04
LS04
LS04
LS04
LSOO
LS10
LS20

1/4
1/3
1/2
1/4
1/3

LS08
LS11
LS21
LS02
LS27

1/2 S260
1/4 LS32
1/4 LS86
112 S51

1/4 LS279
1/4 LS75*
1/4 LS175**

GATE
COUNT

DESCRIPTION

3 TO 8 DECODER
4 TO 16 DECODER
8T01 MULTIPLEXER
4-BIT FULL ADDER
8-BIT FUll ADDER
12-BIT FULL ADDER
16-BIT FUll ADDER
lOOK-AHEAD CARRY GENERATOR
4-BIT PRESETTABlE AND EXPANDABLE
BINARY COUNTER
4-BIT EXPANDABLE BINARY COUNTER
4-BIT PRESETTABlE BINARY COUNTER
4-BIT BINARY COUNTER
8-BIT PRESETTABlE BINARY COUNTER
12-BIT PRESETTABlE BINARY COUNTER
16-BIT PRESETTABlE BINARY COUNTER
4-BIT EXPANDABLE & PRESETTABlE
BINARY UP/DOWN COUNTER
4-BIT EXPANDABLE BINARY
UP/DOWN COUNTER
4-BIT PRESETTABlE BINARY
UP/DOWN COUNTER
4-BIT BINARY UP/DOWN COUNTER
4-BIT EXPANDABLE & PRESETTABlE
DECADE COUNTER
4-BIT EXPANDABLE DECADE COUNTER
4-BIT PRESETTABlE DECADE COUNTER
4-BIT DECADE COUNTER
4-BIT EXPANDABLE & PRESETTABlE
DECADE UP/DOWN COUNTER
4-BIT EXPANDABLE DECADE UP/DOWN
COUNTER
4-BIT PRESETTABlE DECADE UP/DOWN
COUNTER
4-BIT DECADE UP/DOWN COUNTER
4-BIT BIDIRECTIONAL SHIFT REGISTER
4-BIT PARALLEL-ACCESS SHIFT
REGISTER
8-BIT PARAllEL LOAD SHIFT REGISTER
8-BIT SHIFT /STORAGE SHIFT REGISTER
8-BIT SERIAL-IN/PARAllEl-OUT SHIFT
REGISTER
8-BIT PARAllEL IN/SERIAL-OUT SHIFT
REGISTER
8-BIT SYNCHRONOUS-lOAD SHIFT
REGISTER
8-BIT SERIAl-IN/SERIAl-OUT SHIFT
REGISTER

1
1
2
2
3
1
1.5
2
2.5
1.5
2
2.5
1
1.5
2
2.5
1.5
2
2.5
2.5
2.5
1.5
2
1.5
2
2
1
2
2.5
3
5
5
6
2

* Both polarities of the enable signal are required for CMOS ClK
** ClK and ClK are required for CMOS. The 74LS175 is reset on a positive
going transition of the control signal whereas the CMOS implementation
resets on a negative going transition of the same signal.

The current AM I array fami Iy, 300 gates to 1260 gates, is ru n in
a3-12V CMOS process (internally coded as CVA process).
In conjunction with these arrays, AMI has developed a set of
"functional overlays." Theseare basic logic element building
blocks- e.g. two input and larger gates of various types, fl ipflops, and so forth-from which complete logic designs can

* Simplified version of the TTL function

1.5

TTL FUNCTIONAL
EQUIVALENCE

GATE
COUNT

LS138
LS154
lS151
lS283

23
56
28
60
120
180
240
34

lS182
lS163
LS163*
lS163*
lS163*

52
39
47
34
104
156
208

lS169

lS169*

lS169*
lS169*

58
44

LS162
LS162*
lS162*
lS162*

56
43
51
38

lS168

LS168*

lS168*
lS168*
lS194

62
48
62

lS195
lS165
lS299

42
88
137

lS164

LS166

lS166

LS 91

•

Gate Arrays
Total Flexibility of I/O Options

be developed. Each functional overlay corresponds to a
metal Interconnect pattern that Is superimposed on a set
of uncommitted transistors (and polysilicon underpasses)
In the array to Implement the logic element. Typical functional overlay logic elements and the number of equivalent
two-Input gates are shown In Table 2.

Peripheral cell design offers total flexibility In determining
pin·out configurations and maximizes the number of options associated with each pad. Each pin in the 3-mlcron
gate array can serve any of the following functions:
• TTL Output Driver
• LSTTL Output Driver
• CMOS Output Driver
• Open Drain Output
• Tristate Output
• Analog Switch
• CMOS Input
• Voo Supply
• Vss Supply
Furthermore, the peripheral cell also contains high impedance transistors that can be used as pull-ups or pulldowns if required.
The single metal version provides up to 2500 gates and the
double metal GA-D version 4000 gates. See Table 3 for configurations.
In conjunction with these new array products, AMI offers a
complete powerful set of design automation software to
allow users complete design flexibility. Using a terminal
tied to a central AMI owned or customer owned minicomputer or mainframe, the user has access to a complete set
of design automation tools including:

Currently over 75 functional cells exist for this family.

Three-Micron Gate Array Family
As part of AMI's long range semi-custom strategy in
MOSIVLSI, AMI will continue to introduce new gate array
products. These new products will offer performance and
cost advantages not currently realizable. In conjunction
with these new array products, AMI has introduced
computer-aided design tools to automate the entire gate
array design process.
Table 3_ AMI Gate Array Configurations
3/-1 Double Metal Family
Eg. 2·
Input Gates Total Pads

Part No.
GA-1000D
GA-2000D
GA-3000D
GA-4000D

1152
2070
3080
4012

General
I/O

Power
Only

64
84
102
120

4
4
4
4

68
88
106
124

• Schematic capture

3/-1Single Metal Family
Part No.

Eg.2·
Input Gates

Total Pads

General
I/O

GA-500
GA-1000
GA-1500
GA-2000
GA-2500

540
1040
1500
2025
2500

40
54
64
74
84

40
52
64
74
84

• Logic simulation
• Circuit simulation
• Interactive or autoplace and route
• Automated placement and routing

AMI Service Makes It Simple
AMI is committed to providing service which makes getting your gate arrays nearly as simple as buying off-theshelf, standard circuits. From your logic description, net
list, database tape, or whatever format in which you choose
to supply us the design information, AMI has proven procedures designed to assure that you'll get circuits on time
and that they work the first time.
• You supply logic and specifications and we'll complete
the VLSI implementation for you.
• You supply logic using AMI macros and we'll complete
schematic capture, logic simulation, placement and
routing, and the fabrication process.
• You do your own schematic capture on any of several AMI
approved workstations and give us a net list and we'll
complete the process.
• You supply the database tape and we'll fabricate,
package and test your gate array circuits.
Regardless of how or at what stage you supply your design
data, you can be confident that your completed ICs are only a short time away. Why? Because AMI's entire manufacturing cycle, including planning and tracking procedures, has been developed during 17 years of experience

5", Single Metal Family

Part No.
UA-1
UA-2
UA-3
UA-4
UA-5
UA-6

Eg.2Input Gates Total Pads
300
400
540
770
1000
1260

40
46
52
62
70
78

Low
Power
110

High
Power
I/O

Input
Only

17
23
25
31
35
39

20
20
24
28
32
36

3
3
3
3
3
3

The newest gate array family is the high-performance GA
and GA-D series which is based on AMI's 3-micron CMOS
silicon gate process technology.
The AMI GA and GA-D series are designed for 5V operation
over military temperature range (- 55 to 125°C). Besides
high speed (2 to 3ns typical delay) and high density (up to
4K gates), it features total I/O flexibility

1.6

Gate Arrays
HOLDTM (Hierarchically Organized Logic Database) is
created by the BOLT compiler using the AMI macro library
and the BOLT description of the circuit. HOLD contains the
description of the circuit for AMI CAD programs and is updated after mask layout to include key performance information, e.g. net capacitance after routing.

in delivering customized solutions for our customers. Producing small volumes of a large number of different
designs is our standard way of doing business.
Our commitment to you won't get lost in the shuffle as is
often the case with large producers of commodity circuits.
Best yet, you get service and AMI's total MOSIVLSI capability.

SIMADTM is an event and table driven, MOS logic simulator
that creates a logic model of the circuit to be validated from
the HOLD database. Nodes may assume anyone of six
logic states 0, 1, X, L, H, and Z, thus allowing accurate
simulation of transmission gates.

You Get State-of-the-Art CMOS Technology
The advanced CMOS process technology used for AMI gate
array products offers all of the conventional advantages of
CMOS-very low power consumption, broad power supply
voltage range, high noise immunity-as well as dense circuits with high performance. Arrays are currently available
in 5-micron single metal, 3-micron single and double metal,
and in 1984, 2-micron double metal processes.

Since each logic device in the model can be assigned
propagation delays, SIMAD also allows timing verification,
including race detection.
GAPARTM is the software package that does automatic
placement and routing of arrays. GAPAR will complete at
least 98% of the wiring connections on a 100% utilized array. The GAPAR system's correct-by-construction interactive editor can be used to manually connect any unrouted
connections or to manually route critical delay paths.

You Get Leading Edge Design Support
AMI's CAD Technology is the most advanced integrated
software system for MOSIVLSI circuit design available in
the industry. It uses a common database for logic simulation, mask layout and test program generation. The common database approach eliminates errors due to data file
transcription steps and allows a gate array design to be
converted into a standard cell or a full custom circuit
without entering the same logic description again.
The heart of the system is BOLTTM (Block Oriented Logic
Translator) which is a hardware description language and a
compiler for the language. It allows the system designer to
describe the logic network in a hierarchical fashion due to
an unlimited macro nesting capability.
The logic description database is created by compiling a
BOLT description of the logic network into the HOLDTM (see
below) database format. Figure 4 shows a simple logic network and the corresponding BOLT syntax.

DELAyTM updates the HOLD database after routing with
propagation delay parameters based on actual capacitance
data.
TESTFORMTM generates compressed functional test patterns from the SIMAD logic simulation results.
TESTPROTM allows off-line generation of D.C. parametric
tests in the Factor™ test language used in Fairchild test
systems. Its output is merged with the compressed functional patterns from TESTFORM, and the result is a test program that can be tailored for use in any SentryTM tester.
AMI's software makes it reasonably simple to convert a
gate array to a standard cell or full custom circuit, resulting
in lower circuit costs when your volume warrants it. Plus
you get even more.

Figure 4_ Logic Network & BOLT Syntax

:~D-7
.=D--f'

• We offer design training classes with full-time
instructors.
• AMI has design centers to allow you to do your design
with our engineers available to assist you .
• AMI's software is available on a variety of computer
systems and workstations.

6 • NAND
5 • OR
7 • EXoR

• Through volume purchase agreements we can help you
get discounts on the hardware/software configuration
that best fits your needs.

1.7

•

Gate Arrays
Figure 5. Semicustom Development Flow

DELAY
TIMING
DATA

LOGIC INPUT

LOGIC
SIMULATION

TESTFORM
PATTERN
FORMATTER

CUSTOMER-GENERATED TEST VECTORS

TESTPRO
PROGRAM
GENERATOR

D.C. & A.C. PARAMETRIC TESTS

Packages

16 to 64, JEDEC-Standard leadless and leaded chip carriers, miniflat packs to 84 pins, and pin grid arrays to 144
pins. AMI gate array products are also available in wafer or
unpackaged die form.

Pinout or lead count varies with die size and array complexity. The arrays are offered in standard plastic and
ceramic dual·in-line packages with pin counts ranging from
Table 4. D.C. Electrical Characteristics, 5-Micron Gate Arrays

Specified @ Voo

Symbol
VOL

=5V ± 10% or 10V ± 10%, Vss =OV, TA = - 55° to

Parameter

VDD

Min.

Low Level Output Voltage
High Power Output
High Power Output
Low Power Output
Low Power Output

5
10
5
10

High Level Output Voltage
High Power Output
High Power Output
Low Power Output
Low power Output

5
10
5
10

Voo - .05
2.4
9.5
2.4
9.5

+ 125°C

Typ.

Max.

Units

0.05
0.4
0.5
0.4
0.5

V
V
V
V
V

Conditions
10L
IOL
IOL
IOL
10L

V
V
V
V
V

= 1.0",A
= 2.4mA
= 4.8mA
= 0.8mA
= 1.6mA
= -1.0",A
= -1.6mA
= -1.0mA
= -0.8mA
= -O.4mA

VIL

Input Low Voltage

5
5
10

0.0
0.0
0.0

0.8
1.5
3.0

V
V
V

IOH
IOH
10H
IOH
10H
TTL Input
CMOS Input
CMOS Input

VIH

Input High Voltage

5
5
10

2.0
3.5
7.0

Voo
Voo
Voo
1

V
V
V

TTL Input
CMOS Input
CMOS Input

",A

VIN

",A

VOH

Any Input

VOH

liN

Input Leakage Current

-1

loz

High Impedance Output
Leakage Current

-10

GIN

Input CapaCitance

0.001
5

1.8

= Voo or Vss
= Voo or Vss

Standard Cells
AMI's Standard Cell Capabilities

By combining the advantages of optimized full custom circuits and gate arrays, standard cell circuits provide a cost
effective custom solution for medium production volumes
of ten to fifty thousand units per year. In addition to their
relative advantages, standard cell circuits offer all --

e-o-

-cp--cp--cp
0--0--0---,
I

L---...:..I-'1'----(')--~-'T'-~--__ COMMON
(CONNECT TO VOD OR
LEAVE FLOATING)
- - - MECHANICAL
LINKAGE

Ron (Contact Resistance)

1kS!

Circuit Description
The 82559 is designed so that it can be interfaced easily to the dual tone signaling telephone system and that
it will more than adequately meet the recommended
telephone industry specifications regarding the dual
tone signaling scheme.

highest high group frequency of 1633Hz (Col. 4) is not
used. The frequency tolerance must be ± 1.0%. However, the 82559 provides a better than .75% accuracy.
The total harmonic and intermodulation distortion of
the dual tone must be less than 10% as seen at the telephone terminals. (Ref. 1.) The high group to low group
Signal amplitude ratio should be 2.0 ± 2dB and the
absolute amplitude of the low group and high group
tones must be within the allowed range. (Ref. 1.) These
requirements apply when the telephone is used over a
short loop or long loop and over the operating temperature range. The design of the 82559 takes into account
these considerations.

Design Objectives
The specifications that are important to the design of
the DTMF Generator are summarized below: the dual
tone signal consists of linear addition of two voice frequency signals. One of the two signals is selected from
a group of frequencies called the "Low Group" and the
other is selected from a group of frequencies called the
"High Group". The low group consists of four frequencies 697,770,852 and 941 Hz. The high group consists
of four frequencies 1209, 1336, 1477 and 1633 Hz. A
keyboard arranged in a row, column format (4 rows x 3
or 4 columns) is used for number entry. When a push
button corresponding to a digit (0 thru 9) is pushed, one
appropriate row (R1 thru R4) and one appropriate column (C1 thru C4) is selected. The active row input
selects one of the low group frequencies and the active
column input selects one of the high group frequencies. In standard dual tone telephone systems, the

Oscillator
The device contains an oscillator circuit with the
necessary paraSitic capacitances on chip so that it is
only necessary to connect a 10MQ feedback resistor
and the standard 3.58MHz TV crystal across the 08C I
and 08Co terminals to implement the oscillator function. The oscillator functions whenever a row input is
activated. The reference frequency is divided by 2 and
then drives two sets of programmable dividers, the high
group and the low group.
4.15

S2559A1B/EIF
for a common line, can be used. Conventional telephone push button keyboards as shown in Figure 1 or
X-Y keyboards with common can also be used. The
common line of these keyboards can be left unconnected or wired "high".

Keyboard Interface
The 82559 employs a calculator type scanning circuitry
to determine key closures. When no key is depressed,
active pull-down resistors are "on" on the row inputs
and active pull-up resistors are "on" on the column inputs. When a key is pushed a high level is seen on one
of the row inputs, the oscillator starts and the keyboard
scan logic turns on. The active pull-up or pull-down
resistors are selectively switched on and off as the
keyboard scan logic determines the row and the column inputs that are selected. The advantage of the
scanning technique is that a keyboard arrangement of
8PST switches are shown in Figure 2 without the need

Logic Interface
The S2559 can also interface with CM08 logic outputs
directly. The S2559 requires active "High" logic levels.
Since the active pull-up resistors present in the 82559
are fairly low value (500Q typ), diodes can be used as
shown in Figure 3 to eliminate excessive sink current
flowing into the logic outputs in their "Low" state.

Figure 2. SPST Matrix Keyboard Arranged in the 2 of 8 Row, Column Format
RI

R4
SPST MATRIX KEYSORTED:

),'

iOPTIONAL COLUMN'

are used to digitally synthesize a stair-step waveform to
approximate the sinewave function (see Figure 3). This
is done by connecting a weighted resistor ladder network between the outputs of the Johnson counter, VDD
and VREF . VREF closely tracks VDD over the operating
voltage and temperature range and therefore the peakto-peak amplitude Vp (VD D - VREF) of the stairstep function is fairly constant. VREF is so chosen that Vp falls
within the allowed range of the high group and low
group tones.

4.16

S2559A1B/EIF

Figure 3. Logic Interface for Keyboard Inputs of the 52559

Voo
14
13

R,
Rz

12
R3
11

S2559
C,
Cz
C3
C4

VSS

6
G1 THRU G8 ANY TYPE CMOS GATE
01 THRU 08 DIODES TYPE IN914 (OPTIONAL)

Figure 4. Stairstep Waveform of the Digitally Synthesized Sinewave

(voo)

1.0
0.9
0.8
0.7

>"~
N
::;
---,-11'-~~ COMMON

Ll.

RON (CONTACT RESISTANCEI.;; lkn

1
¥c,

I-I.

I.!. C3

(CONNECT TO Voo I
- - - MECHANICAL
LINKAGE

4.28

S2560A

Figure 3. Timing

n~-_-~]

IL==~-J

KEY INPUT

LOOP CURRENT
DIAL PULSES
I

rARKI

lOP

I
SPACE

•

I
I
I
I
I

lOP

I
MUTE

I
I
I
I

Table 2. Table for Selecting Oscillator Component Values for Desired Dialing Rates and Inter-Digit Pauses
Dial Rate
Desired

Dsc. Freq.

(Hz)

(kQ)

5.5/11
6/12
6.5/13
7/14
7.5/15
8/16
8.5/17
9/18
9.5/19
10/20

1320
1440
1560
1680
1800
1920
2040
2160
2280
2400

(fd/ 24O)/

Co
(pF)

Dial Rate (pps)
ORS= Vss
DRS = Voo

7.5
8
8.5
9
9.5
10

11
12
13
14
15
16
17
18
19
20

1454
1334
1230
1142
1066
1000
942
888
842
800

727
667
615
571
533
500
471
444
421
400

(fd/ 24O)

(fd/ 12O)

1920 103
fi
x

3
~
fi x10

5.5
6
6.5
Select components in the
ranges indicated in table
of electrical specifications

750

270

750

lOP (ms)
IPS = Vss
IPS = Voo

(fd /12O )

NOTE: lOP is dependent on the dialing rate selected. For example, lor a dialing rate 01 1Opps, an lOP 01 either BOOms or 400ms can be selected, For a dialing rate 01 14pps,
and lOP 01 either 1142ms or 571 ms can be selected.

Table 3.

Function
Dial Pulse Rate Selection
Inter-Digit Pause Selection

Pin Designation

Input Logic Level

Selection

DRS (14)

VSS
VOO

(f/240)pps
(f/120)pps

lOP (15)

Voo

----r

Vss

-----r

Mark/Space Ratio

MIS (12)

On Hook/Off Hook

liS (5)

Vss
VOO
Voo
Vss

NOTE: I is the oscillator Irequency and is detemined as shown in Figure 5.

4.29

960

1920

33 113/66 213
40/60
On Hook
Off Hook

S2560A

Figure 4. Pulse Dialer Circuit with Redial

Ro=10-20MQ, R1=150kQ, R2=2kQ
R3=470kQ, R4, R5 =10kQ, R1O=47kQ
R6, R8=2kQ, R7, Rg=30kQ, R11=20Q, 2W
Z1=3.9V, 01-04=IN4004, 05, 06, 07=IN914, C1 =15MF
RE=Ro=750kQ, Co=270pF, C2=O.D1MF
01, 04 = 2N555D TYPE 02, 03 = 2N5401 TYPE
Z2 = IN5379 11 OV ZENER OR 2XIN4758

NOTE. PARTS REQUIRE COMMON OF THE KEYBOARD CONNECTED TO VOO

Figure 5. Pulse Dialer Circuit with Redial (Single Hook Switch Contact Application for PABX)

R1=1D-2DMQ, R2=2kQ
R3= 470kQ, R4, R5 = 1DkQ
R6, Rs=2kQ, R7, Rg=30kQ
R10 = 47kQ, R11 = 20Q, 2W
Z1=3.9V,01- 04=IN40D4
05,06, D7=IN914, C1=15MF
RE, RD = 750kQ, CD = 270pF
C2=O.01MF, 01, 04=2N5550
02, 03 = 2N54D1
Z2 = 15DV ZENER OR VARISTOR TYPE GE MOV15D

NOTE. PARTS REQUIRE COMMON OFTHEKEYBOAROCONNECTEDTOV

4.30

S2560A

Figure 7. SPST Switch Matrix Interface

Figure 6. Circuit for Applying Momentary "ON Hook"
Condition During Power Up

VOO

C1
C2

I I

S2560A

0).

R2
100kll

10
Vss

30pF

4.31

-""r

VSS

I
-

AMI.---------.""4.

A Subsidiary
of Gould Inc.

Advanced Product Description

S2560GlS2560G1

PULSE DIALER

General Description
The S2560G is a modified version of the S2560A Pulse Dialer with complete pin/function compatibility. It is recommended to be used in all new and existing designs. Most electrical specifications for both devices are identical.
Please refer to S2560A data sheet for details. S2560G1 is low voltage version of S2560G.
Differences between the two devices are summarized below:

2560G
Operating Voltage, Dialing:
Operating Voltage, Voice Mode:
Data Retention Voltage (Minimum):
100

Operating Current:

100 Standby Current:
Keyboard Debounce Time:
X-Y Keyboard Interface:

Redial Buffer:
Dialing Characteristics:
Inter-digit pause timing

2560G1
1.5V to 3.5V
1.5V to 3.5V
1.0V
100",A@1.5V
500",A@3.5V
750",A@1V
10msec
Does not need capacitors

2.0V to 3.5V
1.5V to 3.5V
1.0V
200",A@2.0V
1000",A@3.5V
2",A@1V

22 digits
Can dial more than 22 digits. Redial
disabled if more than 22 digits are entered.
Follows dial pulses.

2560A
1.5V to 3.5V
1.5V to 3.5V
1.0V
100",A@1.5V
500",A@3.5V
750nA@1V
16msec
Capacitors required between column inputs
and Vss
20 digits
Accepts a maximum of 20 digits. Will not dial
additional digits.
Precedes dial pulses

Application Suggestions
1) In most existing designs, the S2560G will work in place of S2560A without any modifications. Problems may
arise however, if the keyboard bounce time exceeds 10ms. In such a case, the device may interpret a single key
entry as a double key. To avoid this false detection, the keyboard debounce time can be easily increased from
10ms to 20ms by changing the Oscillator Frequency from 2400Hz down to 1200Hz. This is done by changing the
value of the capacitor connected to pin 7 from 270pF to 470pF. To preserve the dialing rate at 10pps and lOP at
800ms the DRS and lOP pins now must be connected to Voo instead of Vss. Figure 1 shows the implementation
details. Note, that interfacing with x·y keyboard no longer requires capacitors to Vss from column pins.
2) The hookswitch input pin (pin 5) must be protected from spikes that can occur when the phone goes from offhook condition to on-hook. Voltage exceeding Voo on this pin can cause the device to draw excessive current.
This will discharge the capacitor across Voo and Vss causing the supply voltage to drop. If the voltage drops
below 1 volt (data retention voltage) the device could lose redial memory. To prevent the voltage on the
hookswitch pin from exceeding Voo , an external diode must be added on the hookswitch pin as shown in Figure 1.

4.32

S2560G/S2560G1
Figure 1. Transient Protection Technique Using Diode Between Voo and tiS
VDD

112

13
1

8
0

#
!

3
4

1
18
17

01
Rl
RE
RD
CD
S1

MIS
DRS

lOP

iii

2 Rl VDD

S2560G

MUTE

~
6

CDM~

RD
Vss
10
1

1
Vss

4.33

ffii~

IN914
750kQ
750kQ
750kQ
470pF
HOOK SWITCH CONTACT

,~ 0

8
RD

•
-.

:
.

AMI.~--------~
.""""4.

A Subsidiary
of Gould Inc.

Advanced Product Description

S2561/S2561 AlS2561 C

TONE RINGER

Features
o CMOS Process for Low Power Operation
o Operates Directly from Telephone Lines with
Simple Interface
D Also Capable of Logic Interface for Non-Telephone
Applications
o Provides a Tone Signal that Shifts Between Two
Predetermined Frequencies at Approximately 16Hz
to Closely Simulate the Effects of the Telephone
Bell
o Push-Pull Output Stage Allows Direct Drive, Eliminating Capacitive Coupling and Provides Increased
Power Output
o 50mW Output Drive Capability at 10V
Operating Voltage

Auto Mode Allows Amplitude Sequencing such that
the Tone Amplitude Increases in Each of the First
Three Rings and Thereafter Continues at the Maximum Level
D Single Frequency Tone Capability

General Description
The S2561 Tone Ringer is a CMOS integrated circuit
that is intended as a replacement for the mechanical
telepnone bell. It can be powered directly from the
telephone lines with minimum interface and can drive a
speaker to produce sound effects closely simulating
the telephone bell.
Data Subject to change at any time without notice. These sheets
transmitted for information only.

Pin Configuration

Block Diagram

AUTO
MANUAL

Sfs

Voo

OSCR,

THC

OSCRm

DUll

OET
INH

OSCRO

OUT H

OSCT,

OUl m

OSCT m

OUT 1

OSCT 0

QUTe

OUlM

OUTPUT

STAGE

aSCl

OUTH

OSCTo

AIM

EN/RATE

VSS

OUTe

OSCR 1

OSCR j

OUT h

OSCRo

OUT,

Vss
RATE*"

t-*-1

voo
*OPTlONAlOUTPUTFORS2561C

4.34

vss

Voo

OSCRm

S2561/S2561 A1S2561 C
Absolute Maximum Ratings:
Supply Voltage ....................................................................................................................................................................... + 12.0V·
Operating Temperature Range ...................................................................................................................................... ooe to + 70°C
Storage Temperature Range .................................................................................................................................. - 40°C to + 125°C
Voltage at any Pin ......................................................................................................................................... Vss - 0.3V to Voo + 0.3V
Lead Temperature (Soldering, 105ec) ......................................................................................................................................... 300°C
*This device incorporates a 12V internal zener diode across the VDD to VSS pins. Do NOT connect a low impedance power supply directly
across the device unless the supply voltage can be maintained below 12V or current limited to <25mA.

Electrical Characteristics:
Specifications apply over the operating temperature and

3.5V~VDD

to Vss <12.0V unless otherwise specified.

Parameter

Min.

Max.

Units

Vos

Operating Voltage (Voo to Vss)

8.0

12.0

Vos

Operating Voltage

4.0

"Auto" mode, non·ringing

los

Operating Current

500

IJ.A

Non-ringing, Voo = 10V, THC pin open, 01

IOHC

Output Drive
Output Source Current
(OUT H, OUT C outputs)

Voo=10V, VOUT=8.75V

IOle

Output Sink Current
(OUT H, OUT C outputs)

Voo=10V, VOUT=O.75V

Symbol

Conditions
Ringing, THC pin open

IOHM

Output Source Current (OutM output)

Voo=10V, VOUT=8.75V

IOlM

Output Sink Current (OUT M output)

Voo= 10V, VOUT= 0.75V

IOHl

Output Source Current (OUT l output)

Voo=10V, VOUT=8.75V

lOll

Output Sink Current (OUT l output)

Voo= 10V, VOUT= 0.75V

~in

open or Vss

CMOS to CMOS
VIH

Input Logic" 1" Level

0.7 Voo

Vil

Input Logic' '0" Level

Vss - 0.3

VOHR

Output Logic" 1" Level (Rate output)

VOLR

Output Logic "0" Level (Rate output)

Voz

Output Leakage Cu rrent
(OUT H, OUT M outputs in high
impedance state)

Voo + 0.3

All inputs

0.3 Voo

All inputs

10 = 10IJ.A (Source)

0.9 Voo

CIN

Input Capacitance

Malta

Oscillator Frequency Deviation

-5

RlOAO

Output Load Impedance Connected Across
OUT H and OUT C

600

0.5

1
1

IJ.A
IJ.A

Voo =10V, VOUT=OV
Voo= 10V, VOUT= 10V

7.5

Any pin

Fixed RC component values 1MQ ~ Rri, Rti ~ 5MQ;
1OOkQ~ Rrm , Rtm~ 750kQ; 150pF~ Cro , Cto~ 3000pF; 330pF
recommended value of Cro and Cto, supply voltage varied from
9V ± 2V (over temperature and unit-unit variations)

IIH, IL

Leakage Current, VIN = Voo or Vss

100

VTH

POE Threshold Voltage

6.5

Internal Zener Voltage

10 = 10llA (Sink)

Tone Frequency Range = 300Hz to 3400Hz
Any input, except 01 pin Voo = 10V

Iz = 5mA

The device power supply should always be turned on before the input signal sources, and the input signals should be turned off
before the power supply is turned off (Vss ';;V I ~VDD as a maximum limit). This rule will prevent over-dissipation and possible damage of
the input-protection diode when the device power supply is grounded.

4.35

S25611S2561 AlS2561 C
Functional Description
The S2561 is a CMOS device capable of simulating the
effects of the telephone bell. This is achieved by producing a tone that shifts between two predetermined
frequencies (512 and 640Hz) with a frequency ratio of
5:4 at a 16Hz rate.
Tone Generation: The output tone is derived from a tone
oscillator that uses a 3 pin R-C oscillator design consisting of one capacitor and two resistors. The oscillator
frequency is divided alternately by 4 or 5 at the shift
rate. Thus, with the oscillator adjusted for 5120Hz, a
tone signal is produced that alternates between 512Hz
and 640Hz at the shift rate. The shift rate is derived from
another 3 pin R-C oscillator which is adjusted for a nominal frequency of 5120Hz. It is divided down to 16Hz
which is used to produce the shift in the tone frequency. It should be noted that in the special case
where both oscillators are adjusted for 5120Hz, it is
only necessary to have one external R-C network for
one oscillator with the other oscillator driven from it.
The oscillators are designed such that for fixed R-C
component values an accuracy of ± 5% can be obtained over the operating supply voltage, temperature and
unit-unit variations. See Table 1 for component and frequency selections. In the single frequency mode, activated by connecting the SFS input to Vss only the
higher frequency continuous tone is produced by using
a fixed divider ratio of 4 and by disabling the shift
operation.
Ring Signal Detection: In the following description it is
assumed that both the tone and rate oscillators are adjusted for a frequency of 5120Hz. Ringing signal (nominally 42 to 105 VAC, 20Hz, 2 sec on/4 sec off duty cycle)
applied by the central office between the telephone line
pair is capacitively coupled to the tone ringer circuitry
as shown in Figure 2. Power for the device is derived
from the ringing signal itself by rectification (diodes 01
thru 04) and zener diode clamping (Z2)' The signal is
also applied to the EN input after limiting and clamping
by a resistor (R 2) and internal diodes to VDD and Vss
supplies. Internally the signal is first squared up and
then processed thru a2ms filter followed by adial pulse
reject filter. The 2ns filter is a two-stage register clocked by a 512Hz signal derived from the rate oscillator by
a divide by 10 circuit. The squared ring signal (typically
a square wave) is applied to the D input of the first stage
and also to reset inputs of both stages. This provides
for rejection of spurious noise spikes. Signals exceeding a duration of 2ms only can pass through the filter.
4.36

The dial pulse reject filter is clocked at 8Hz derived
from the rate oscillator by divide by 640 circuit. This circuit is designed to pass any signal that has at least two
transitions in a given 125ms time period. This insures
that signals below 8Hz will be rejected with certainty.
Signals over 16Hz will be passed with certainty and between 8Hz and 16Hz there is a region of uncertainty. By
adjusting the rate oscillator to a different frequency the
break points of 10Hz and 20Hz the rate oscillator can be
adjusted to 6400Hz. Of course this also increases the
tone shift rate to 20Hz. The action of the dial pulse reject filter minimizes the dial pulse interference during
dialing although it does not completely eliminate it due
to the rather large region of uncertainty associated with
this type of discrimination circuitry. The dial pulse filter
also has the characteristic that an input signal is not
detected unless its duration exceeds 125ms. This insures that the tone ringer will not respond to momentary bursts of ringing less than 125 milliseconds in duration (Ref. 1).
In logic interface applications, the 2ms filter and the
dial pulse reject filter can be inhibited by wiring the Det.
INHIBIT pin to VDD . This allows the tone ringer to be
enabled by a logic '1' level applied at the "ENABLE" input without the necessity of a 20Hz ring signal.
Voltage Sensing: The S2561 contains a voltage sensing
circuit that enables the output stage and the rate and
tone oscillators, only when the supply voltage exceeds
a predetermined value. Typical value of this threshold is
7.3 volts. This prduces two benefits. First, it insures
that the audible intensity of the output tone is fairly
constant throughout the ringing period; and secondly,
it insures proper circuit operation during the "auto"
mode operation by reducing the power consumption to
a minimum when the supply voltage drops below 7.3
volts. This extends the supply voltage decay time
beyond 4 seconds (off period of the ring signal) with an
adequate filter capacitor and insures the proper functioning of the "amplitude sequencing" counter. It is
important to note that the operating supply voltage
should be well above the threshold value during the
ringing period and that the filter capacitor should be
large enough so that the ripple on the supply voltage
does not fall below the threshold value. A supply
voltage of 10 to 12 volts is recommended.
In applications where the tone ringer is continuously
powered and below the threshold level, the internal
threshold can be bypassed by connecting the THC pin
to VDD' The internal threshold can also be reduced by

52561/52561 Al52561 C
connecting an external zener diode between the THe
and Voo pins.
Auto Mode: In the "auto" mode, activated by wiring the
"auto/manual" input to Vss , an amplitude sequencing
of the output tone can be achieved. Resistors RL and
RM are inserted in series with the OutL and OutM outputs, respectively, and paralleled with the OutH output
(Figure 1). Load is connected across OutH and Oute
pins. RL is chosen to be higher than RM. In this manner
the first ring is of the lowest amplitude, second ring is
of medium amplitude and the third and consecutive

rings thereafter are at maximum amplitude. For the proper functioning of the "amplitude sequencing" counter
the device must have at least 4.0 volts a:cross it
throughout the ring sequence. The filter capacitor is so
chosen that the supply voltage will not drop below 4.0
volts during the off period. At the end of a ring sequence when the off period substantially exceeds the 4
second duration, the counter will be reset. This will insure that the amplitude sequencing will start correctly
beginning a new ring sequence. The counter is held in •
reset during the "manual" mode operation. This pro_ . ~
duces a maximum ring amplitude at all times.
Figure 1-8. Output Stage Connected for
Manual Mode Operation

Figure 1-A. Output Stage Connected for
Auto Mode Operation

-------~

~
:OUTHn
I

II ( ) """"

VOLUME
CONTROL

I
I
I

OUTC
I

_ _ _ _ _ _ _ .J

Figure 2-8. Typical Telephone Application of
the S2561A

Figure 2-A. Typical Telephone Application of
the S2561

VDD

TRANSFORMER

OSCR j

DUl m

OUT,

EN
52561

52561A

9T027V

lMQ

.47jAF/20DY

47J.1Ff25V

Ri
Rm

200KQ

300p'

0,-0 4 IH4004
Z2

RL
R.
R.

18KQ

8Q$PEAKER

2000Q/SQXFMR
100KQ

9T027VIEHER

IN4742
12YZENER

4.37

51KH

52561/52561 Al52561 C
Output 8tage: The output stage is of push-pull type consisting of buffers L, M, Hand C. The load is connected
across pins OutH and Oute (Figure 2). During ringing,
the OutH and Oute outputs are out of phase with each
other and pulse at the tone rate. During a non-ringing
state, all outputs are forced to a known level such as
ground which insures that there is no DC component in
the load. Thus, direct coupling can be used for driving
the load. The major benefit of the push-pull arrangement is increased power output. Four times as much
power can be delivered to the load for the same operating voltage. Buffers M and H are three-state. In the
"auto" mode buffer M is active only during the second

ring and in the "high impedance" state at all other
times. Buffer H is active beginning the third ring. In the
"manual" mode buffers H, Land C are active at all
times while buffer M is in a high impedance state. The
output buffers are so designed that they can source or
sink 5mA at a Vee of 10 volts without appreciable
voltage drop. Care has been taken to make them symmetrical in both source and sink configurations. Diode
clamping is provided on all outputs to limit the voltage
spikes associated with transformer drive in both directions Vee and Vss.
Normal protection circuits are present on all inputs.

Table 1. 82561/82561 C Pin/Function Descriptions (82561 A)
Pin

Number

Function

18, 9
8,4

These are the power supply pins. The device is designed to operate over
the range of 3.5 to 12.0 volts. A range of 10 to 12 volts is recommended
for the telephone application.

10, 11, 5

These pins are for the 20Hz ring enable input. They can also be used for
DC level enabling by wiring the DI pin to VDD . EN is available for the
S2561 only.

"Auto" mode for amplitude sequencing is implemented by wiring this
pin to Vss. "Manual" mode results when connected to VDD . The
amplitude sequencing counter is held in reset during the "manual"
mode.

13, 14, 15,
7,6

These are the push-pull outputs. Load is directly connected across OutH
and Outc outputs. In the "auto" mode, resistors RL and RM can be inserted in series with the OutL and OutM outputs for amplitude sequencing (see Figure 1).

2,3,4,
1,2,3

These pins are provided to connect external resistors RRi, RRm and capacitor CRo to form an R-C oscillator with a nominal frequency of 5120Hz.
See Table 2 for components selection.

5,6,7

These pins are provided to connect external resistors RTi, RT m and
capacitor CT 0 to form an R-C oscillator from which the tone signal is
derived. With the oscillator adjusted to 512Hz and 640Hz results. See
Table 2 for components selection.

Threshold Control (THC)

The internal threshold voltage is brought out to this pin for modification
in non-telephone applications. It should be left open for telephone applications. For power supplies less than 9V connect to VDD .

Rate

This is an optional output for the S2561 C version which replaces the EN
output. This is a 16Hz output that can be used by external logic as
shown in Figure 3-A to produce a 2sec on/4sec off waveform.

Power (VDD *, Vss *)

Ring Enable (EN*,

EN)

Auto/Manual (AIM)

Outputs (Out L, OutM, Out~, Out~)

Oscillators
Rate Oscillator
(OSCRj, OSCR~ OSCR~)
Tone Oscillator
(OSCTi, OSCT m, OSCT 0)

4.38

82561/82561 Al82561 C
Table 1. (Continued)
Pin
Detectpr Inhibit (D I)

Number

Function

When this pin is connected to VDD , the dial pulse reject filter is disabled
to allow DC level enabling of the tone ringer. This pin should be hardwired to Vss in normal telephone-type applications.
When this pin is connected to Vss, only a single frequency continuous
tone is produced as long as the tone ringer is enabled. In normal applications this pin should be hardwired to VDD .

Single Frequenc;y Select (SFS)

*Pinouts of 8 pin S2561A package.

Table 2. Selection Chart for Oscillator Components and Output Frequencies
Tone/Rate Oscillator
Frequency
(Hz)

5120
6400
3200
8000

1
- _=-

Oscillator Components
RM

(kQ)

Co
(pF)

Rate
(Hz)

Tone
(Hz)

1000

200

330

16
20
10
25

512/640
640/800
320/400
800/1000

fo fo
10

Select components in the ranges indicated in the
table of electrical characteristics

320

Applications
Typical Telephone Application: Figure 2 shows the
schematic diagram of a typical telephone application
for the 52561 tone ringer. Circuit power is derived from
the telephone lines by the network formed by capacitor
C1, resistor R1, diode bridge 0 1 through 0 4 , and filter
capacitor C2 . C2 is chosen to be large enough so as to
insure that the power supply ripple during ringing does
not fall below the internal threshold level (typ. 7.3 volts)
and to provide large enough decay time during the off
period. A typical value of C2 may be .47J.lF. C1 and R1 are
chosen to satisfy the Ringer Equivalence Number
(REN) specification (Ref. 1). For REN = 1 the resistor
should be a minimum of S.2kQ. It must be noted that the
amount of power that can be delivered to the load
depends upon the selection of C 1 and R1.
The device is enabled by limiting the incoming ring
signal through resistors R2, R3 and diodes d5 and d6 .
Zener diode Z1 (typ. 9-27 volts) may be required in certain applications where large voltage transients may

4.39

occur on the line during dial pulsing. The internal 2ms
filter and the dial pulse reject filter will suppress any
undesirable components of the signal and will only respond to the normal 20Hz ring signal. Ring signals with
frequencies above 16Hz will be detected.
The configuration shown will produce a tone with
frequency components of 512Hz and 540 Hz with a shift
rate of approximately 16 Hz and deliver at least 25mW
to an SQ speaker through a 2000Q:8Q transformer. If
"manual" mode is used, a potentiometer may be inserted in series with the transformer primary to provide
volume control. If "automatic" mode is used, resistors
RL and RM can be chosen to provide desired amplitude
sequencing. Typically, signal power
will be down 20 log

first ring, and down 20 log

RLOAD

dB during the

S25611S2561 AlS2561 C

Figure 3-A. Simulation of the Telephone Bell in Non-Telephone Applications

I ,j.

VDD

75Dkn

I
I

L
-

()

DUTl

200kn

33DpF

THC

I
I

DUTM

52561,C
DUTH

OUTe

AIM

RESET

4024

~O,

_EN

RATE

16Hz

Vss

7STAGEorVIOER

I" I"

2SECQNOSON.2SECONOSOFF

0,
3

4S!:CrJNDSON4SECONOSOFr

START!STQPRINGSEQUENCE

Figure 3-B. Single Frequency Tone Application in Alarms, Buzzers, Etc.

Vao
(18)

AIM
(8)

SFS
(1)

(16) 01

};

(17)THC

II()

(15) OUTH
S2561C

};

(14) OUTM

(13) DUlL

(12) OUTe
EN (10)

SFS(1)

RATE

(9)

Vss

second ring with maximum power delivered to the load
beginning the third and consecutive rings.

be connected to Voo to allow DC level enabling of the
ringer.

In applications where dial pulse rejection is not necessary, such as in DTMF telephone systems, the ENABLE
pin may be connected directly to Voo. Det. Inh pin must

Non-Telephone Applications: The configuration shown
in Figure 3-A may be used in non-telephone applications where it is desired to simulate the telephone bell.

4.40

82561/82561 Al82561 C
The internal threshold is bypassed by wiring THC to
Voo. The rate output (16Hz) is divided down by a 7·stage
divider type 4024 to produce two signals: a 2 second on/
2 second off signal and a 4 second on/4 second off
signal. The first signal is connected to the EN pin and
the second to the DI pin to produce a 2 second on/4 se·
cond off telephone·type ring signal. The ring sequence
is initiated by removing the reset on the divider. If
"auto" mode is used, a reset signal must be applied to
the "amplitude sequencing" counter at the end of a
ring sequence so that the circuit will respond correctly
to a new ring sequence. This is done by temporarily
connecting the "auto/manual" input to Vss.
Figure 3·B shows a typical application for alarms,
buzzers, etc. Single frequency mode is used by connec·

4.41

ting the SFS input to Vss. A suitable on/off rate can be
determined by using the 7·stage divider circuit. If tin·
uous tone is not desired, the 16Hz output can be used
to gate the tone on and off by wiring it into the ENABLE
input.
Many other configurations are possible depending
upon the user's specific application.
Relerence 1. Bell system communications technical
reference:

PUB 47001 of August 1976.
"Electrical Characteristics of Bell System Network
Facilities at the Interface with Voiceband Ancillary and
Data Equipment"-2.6.1 and 2.6.3

1_
~
_
=.

AIMI.---------."fIIII(.

A Subsidiary
of Gould Inc.

S2563A

REPERTORY DIALER

Features

General Description

o
o
o
o
o
o
o
o
o
o
o

The S2563A is an improved version of the S2562 repertory dialer and can replace the S2562 in existing
applications using local power. It is however specifically designed for applications that will only use
telephone line power. To achieve this following
changes were made to the S2562 design.

o
o
o

Specifically Designed for Telephone Line Powered
Applications
CMOS Process Achieves Low Power Operation
8 or 16 Digit Number Capability (Pin Programmable)
Dial Pulse and Mute Output
Tone Outputs Obtained by Interfacing With
Standard AMI S2859 Tone Generator
Two Selections of Dial Pulse Rate
Two Selections of Inter-Digit Pause
Two Selections of Mark/Space Ratio
Memory Storage of 29 8-Digit Numbers or 16-Digit
Numbers with Standard AMI S5101 RAM
16-Digit Memory for Input Buffering and for Redial
with Access Pause Capability
Accepts the Standard Telephone DPCT Keypad or
SPST Switch X-V Matrix Keyboards; Also Capable
of Logic Interface
Can Use Standard 3 x 4 or 4 x 4 Keyboards
Inexpensive, but Accurate R-C Oscillator Design
BCD Output with Update for Single Digit Display

a. PF output was replaced by a level reset input which
allows the device to be totally powered down in the
on-hook state of the telephone.
b. To reduce power consumption in the associated
S5101 memory in the standby mode, the interface
was changed so that its CE2 input rather than the
the CE1 input is controlled by the device.
c. Process was changed toa lowervoltage CMOS pro-cess. Additionally a mark/space selection input
(MIS) was added to allow selection of either 40/60 or
33/67 ratio. Provision was also made to allow the
device to work with a standard 3x 4 or 4x 4
keyboard.

Data subject to change at any time without notice. These sheets transferred for information only.

Block Diagram

Pin Configuration
--<>

VDD

-+-0 Vss

t-----o

OSC;
OSCm

osc.

IPSo---~

RAM UO DATA

M/So---~

DRS

1--;;--;:----,/ OISPLA Y

0----""

PIN 0 - - - " "
MODE o-----<~
NLS o-----'~

I~~ o-~-~

R,o-~-~

KEYPAD

RAM ADDRESS
TONE GENERATOR

...1

C60---'--""4._ _ _

RESET

0---..-

DP 0---.------'
MUTE 0 - - - . - - - - - - - - '

4.42

AIMII.---------."""4.
~

A Subsidiary
of Gould Inc.

Advanced Product Description

S2569/S2569A

DTMF TONE GENERATOR
WITH REDIAL
General Description
The S2569/S2569A are members of the S2559 Tone
Generator family with the added features of Redial,
Disconnect, Pause and Flash. They produces the 12
dual tones corresponding to the 12 keys iocated on the
conventional Touch-Tone~ telephone keypad. The
S2569 has separate keys, located in column four, which
initiate the Disconnect(D), Pause(P), Redial(R), and
Flash(F) functions. (Note: column four keys do not
generate tones.) Only the redial feature is available on
the S2569A. Redial on the S2569A is initiated by pressing * or # as the first key offhook.
A voltage reference generated on the chip regulates the
signal levels of the dual tones to meet the recommended telephone industry specifications.

Features
o Wide Operating Supply Voltage Range (2.50-10V)
o Low Power CMOS Circuitry Allows Device Power
to be Derived Directly from the Telephone Lines
o 21 Digit Memory for Redial
o Uses Standard 3x4 (S2569A) or 4x4 (S2569) SPST or
X-Y Matrix Keyboard
o The Total Harmonic Distortion is Below Industry
Specification (Max. 7% Over Typical Loop Current
Range)
o Separate Control Keys (S2569) for Disconnect,
Pause, Redial and Flash in Column Four
o Allows Dialing of * and # Keys on S2569. For
S2569A Redial Initiated by * or # Key as First Key
Offhook, * or # can be Dialed After First Key
Off hook.

S2569 Pin Configuration

Block Diagram

Voo

TONE

DIS.

Vss

OSCi

MUTE

OSC o

S2569/A Pin Configuration

Voo

TONE

N.C.

MUTE

(DIS)

Vss

Touch·Tone is a registered trademark of AT&T

4.43

OSCi

MUTE

OSC o

N.C.

_. ~

S2569/S2569A
Absolute Maximum Rating:
DC Supply Voltage (Voo - Vss) .............................................................. + 13.5V
Operating Temperature ............................................................. O°C to + 70°C
Storage Temperature ........................................................... - 65°C to + 140°C
Power Dissipation at 25°C ................................................................ 500mW
Input Voltage .................................................... ,...... Vss - O.6-'

J. I
r---~--O--O
~~
R3-o-.~
I
I

9-- 0 --9- ~~~
, A..

, A...

:. ~

L1
7

COMMON
(CONNECTTO VOO DR
LEAVE FLOATINGI
- - - MECHANICAL
LINKAGE

Ron (Contact Rasistancel .. lkO

Figure 2. SPST Matrix Keyboard Arranged In the 2 of 8 Row, Column Format

SPST .'TN' "'YS'""'b'

-----.------.------.----~~~R1

)N.O.

4.53

S2569B/C
Logic Interface
The S2569B can also interface with CMOS logic outputs directly. The S2569B/C requires active high logic levels.
Since the pull up resistors present in the S2569B/C are fairly low values, diodes can be used as shown in Figure 3 to
eliminate excessive sink current flowing into the logic outputs in their low logic state.

Figure 3. Logic Interface for Keyboard Inputs of the 525698

VDD

15
14
13
12

R1
R2
R3
R4
S256981C
C1
C2
C3
C4

Vss

G1 THRU Gg ANY TYPE CMOS GATE
01 THRU D9 DIODES TYPE IN914 (OPTIONAL)

4.54

S2569B1C
Mhy, Cm = .02pF Ch = 5pF.

Chip Enable
The S2569B/C has a Chip Enable input at pin 2. The
Chip Enable forthe S2569B/C is an active "high". When
the Chip Enable is "low", the tone output goes to Vss,
the oscillator is inhibited and the Mute and Disconnect
outputs will go into a low state.

Single Tone Mode
The S2569B/C is capable of dialing single as well as dual
tones. Single tones in either the low group or the high
group can be generated as follows. A low group tone can
be generated by depressing two digit keys in the appropriate row. A high group tone can be generated by
depressing two digit keys in the appropriate column.

Mute Outputs (M1, M2)
The S2569B/C has push-pull buffers for Mute outputs.
With no keys depressed the Mute outputs are low.
When a key is depressed the outputs go high until the
key is released. M1 will stay high for additional 250ms.
Note that minimum mute pulse width is 70ms for M2
and 320ms for M1.
Oscillator
The device contains an oscillator circuit with the necessary parasitic capacitances and feedback resistor
(1 MQ) on chip so that it is only necessary to connect a
standard 3.58MHz TV crystal across the OSC i and OSCo
terminals to implement the oscillator function.
Oscillator Crystal Specifications
Frequency3.579545MHz + .02% Rs<1000hm, LM = 96

Note that two keys have to be depressed simultaneously
or the output will be the normal dual tones. If the keys
are depressed within 10msec of each other, the single
tone will be generated. If not, the standard d.ual tone
representing the first key depressed will be sent and the
second button will be ignored.

Test Mode
The S2569B/C will enter the test mode if all rows are
pulled high momentarily. 16 times the low group frequency will appear at the M2 output depending on
which row is selected. Also 16 times high group frequency will appear at the Flash output depending on
which column is selected.

Figure 4. Stairstep Waveform of the Digitally Synthesized Sinewave

(Voo )

1.0
0.9
0.8

>0.

e!N

0.7
0.6

:::;

c:r:

::i

ex:

0.5

0.4
0.3
0.2
0.1

(Vret )

0
TIME SEGMENTS

4.55

S2569B1C

Figure 5. Typical Timing
Normal Dialing

-Ito 1,.--__________________
1_"_1
1- --1
1

CE---.-.JU
KEYBOARD

~L._ _ _ _ _ _ _ _ _ _ _ _....J

L..J

"2"

1__1'" /::... .. ---+1

INPUT

~2)

"3"

L--

~----------~
/_1'
__
1

M(l) _ _ _-;.---,~r-I---'---~1

________~..------------..,L

--I~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Lte I-I
/-te-I
_1 +....'''....'''..
''w''------

OSC _ _ _

TONE _ _ _ _ _ _-!'.."" .."''<'~-----------~

' L - -....' '....' ' '....

f+--I·-I

-1- 1
I I12

1
,1

KEYBOARD _ _ _ _ _....J~'--_ _ _ _ _

110 .....

___ll

"3"

.. I
0.....

~p~~OARD _ _ _ _ _ _ _ _---IrT"lL._ _ _ _ _ _ _ _ _---'

"6"

TONE _ _ _ _ _---'

MIN RESET TIME:12m.
DEBOUNCE TIME:15m.
KEY RELEASE TIME:6m.
MUTE DELAY TIME:18m.

: MIN. MUTE PULSE WIDTH:70m.
OSC START UP TIME:l0m.
M(l) TURN OFF TIME:250m.
: TONE DELAY TIME:3m.

te ::

I.
"

I.
I.
110

: MIN. TONE OUT:70m.
: TONE OFF TIME:70m.
: MAX. DELAY TIME:l0m.

Redial

REDIAL KEY

--l
3
1

-1

---!RL.._______

"R"

'--_ _ _ _ _ _

-<-

r--1

..,

1'---1'___-1-------'
,,--1 1- ,

M(2)--L.f\

I
1- - - -

1-_<__1,--7__

..,......I

M(l)--.J

.J'.,\""________,s,..""""...._ .......''''",,,>L-__________

TONE _ _ _

Flash

rAL..1 ____-:----'A'--__________
1-<-ln+
_
l1

FLASHKEY _ _ _ _ _.....

-I --!,tal-

FLASHOUTPUT _ _ _ _ _ _

IL-J

f.--- 112----...1
In
112

: MIN TIME TO ENTER KEY:DOm.
: FLASH PULSE WIDTH:IOm. (S2569B) OR
606m.(S2669C)

4.56

S2569B1C

Figure 7. Typical Applications Circuit for Line Powered DTMF Dialer With Redial

FLASH

•

17 10KQ

VOD

TIP

S2569B1C
HK2

100KQ

2 CE

.1/A
750K

C1
R1

7 Vss

11 MUTE
(M1)

TONE Rc

14
13
12

~18

1N914
130Q

4.57

3.58MHz

IN914

~MII.--------------------.""'4.

A Subsidiary
of Gould Inc.

825089

DTMF TONE GENERATOR

Features
o Wide Operating Voltage Range: 2.5 to 10 Volts
o Optimized for Constant Operating Supply Voltages,
Typically 3.5V
o Tone Amplitude Stability is Within ± 1.5dB of
Nominal Over Operating Temperature Range
o Low Power CMOS Circuitry Allows Device Power to
to be Derived Directly From the Telephone Lines or
From Small Batteries
o Uses TV Crystal Standard (3.58MHz) to Derive All
Frequencies Thus Providing Very High Accuracy
and Stability
o Specifically Designed for Electronic Telephone
Applications
o Interfaces Directly to a Standard Telephone
Push-Button Keyboard With Common Terminal
o Low Total Harmonic Distortion
o Single Tone as Well as Dual Tone Capability
o Direct Replacement for Mostek MK5089 Tone
Generator

General Description
The 525089 DTMF Generator is specifically designed
to implement a dual tone telephone dialing system in
applications requiring fixed supply operation and high
stability tone output level, making it well suited for
electronic telephone applications. The device can
interface directly to a standard pushbutton telephone
keyboard with common terminal connected to Vss and
operates directly from the telephone lines. All necessary dual-tone frequencies are derived from the widely
used TV crystal standard providing very high accuracy
and stability. The required sinusoidal waveform for the
individual tones is digitally synthesized on the Chip.
The waveform so generated has very low total harmonic distortion. A voltage reference is generated on the
chip which is very stable over the operating temperature range and regulates the signal levels of the dual
tones to meet the recommended telephone industry
specifications.

Block Diagram

Pin Configuration

AKD

Voo

TONE OUT

iTl

ii1

Vss

OSCI

AKO

C4
I

1'--_ _.....
~

___________________ J

4.58

825089
Absolute Maximum Ratings:
DC Supply Voltage (Voo-Vss) ............................................................................................................................ + 10.5V
Operating Temperature: 525089 ................................................................................................... - 25°C to + 70°C
Operating Temperature: 525089-2 ...................................................................................................... O°C to + 70°C
Storage Temperature ..................................................................................................................... - 65°C to + 150°C
Power Dissipation at 25°C ................................................................................................................................ 500mW
Input Voltage ........................................................................................................................ Vss - 0.6~VIN~VOO + 0.6
Input/Output Current (except tone output) .......................................................................................................... 15mA
Tone Output Current .............................................................................................................................................. 50mA
Electrical Characteristics: (Specifications apply over the operating temperature range of O°C to
otherwise noted. Absolute values of measured parameters are specified.)
Symbol

VDD

IDD

VO R
dBcR
%DIS
NKD
IOL
IOH
IOL
IOH
t5TART
CliO

Parameter/Conditions

+ 70°C unless

(VDD·VSS)
Volts

Supply Voltage
Tone Out Mode (Valid Key Depressed)
Non Tone Out Mode (AKD Outputs toggle
with key depressed)
Supply Current
Standby (~Key Selected,
Tone and AKD Outputs Unloaded)
Operating J2.!!e Key Selected,
Tone and AKD Outputs Unloaded)
Tone Output
Dual Tone
Row Tone
RL = 10kQ
Mode Output
Amplitude
I RL = 100kQ
Ratio of Column to Row Tone* *
Distortion*
Tone Output-No Key Down

AKD Output
Output On Sink Current
Output Off Leakage Current
Oscillator Input/Output
One Key Selected
Output Sink Current
Output Source Current
One Key Selected
Oscillator Startup
Time with Crystal as Specified
Input/Output
Capacitance

• Distortion measured In accordance with the specifications described
accompanying the signal to the total power of the frequency pair".

VOL = 0.5V

VOL =
VOL =
VOH =
VOH =

0.5V
0.5V
2.5V
9.5V

3.0
10.0
3.0
10.0

2.5

10.0·

1.6

10.0

1
5
.9
4.5

20
100
1.25
10.0

JJA
JJA
mA
mA

-8.0
-7.0
3.0
10
-80

dBm
dB
dB
%
dBm

3.0
3.5
2.5-10.0
2.5-10.0

-11.0
-10.0
2.4

2.7

3.0
10.00

0.5

1.0
1

JJA

3.0
10.0
3.0
10.0
3.0-10.0

0.21
0.80
0.13
0.42
-

0.52
2.1
0.31
1.1
2

mA
mA
mA
mA
ms

16
14

pF
pF

3.0
10.00
In

Units

12
10

REF. 1 as the" ratio of the total power of all extraneous frequencies In the vOiceband above 500Hz

··525089-2 available with range of 1.0dB to 3.0dB.
525088 available with OdB ratio (column and row amplitude equal).

4.59

•

S25089
Electrical Characteristics: (Continued)
Symbol

Parameter/Conditions

(VDD'VSS )
Volts

Min.

Typ.

Max.

Units

.2(Voo
-Vss)

Row, Column and Chip Enable Inputs
V1L

Input Voltage, Low

Vss

V1H

Input Voltage, High

.8(Voo
-Vss

Voo

IIH

Input Current

V1H = O.OV

3.0

150

IJA

(Pull up)

V1H = O.OV

10.0

100

300

500

IJA

Oscillator
The 525089 contains an oscillator circuit with the
necessary parasitic capacitances and feedback resis·
tor on chip so that it is only necessary to connect a
standard 3.58M Hz TV crystal across the OSCj and 08CO
terminals to implement the oscillator function. The
oscillator functions whenever a row input is activated.
The reference frequency is divided by 4 and then drives
two sets of programmable dividers, the high group and
the low group.
Crystal Specification
A standard television color burst crystal is specified to
have much tighter tolerance than necessary for tone
generation application. By relaxing the tolerance speci·
fication the cost of the crystal can be reduced. The
recommended crystal specification is as follows:

Figure 1. Standard Telephone Push Button Keyboard

10------,

~~,---Q--Q--Q
1

1
1

1
I

8--8--8----,

~~'----Q--Q--Q

9-- 8 --Q-- -, ~
1

'------'-I.fJ'----<>---"-'T'--+---_

R4
COMMON

(CONNECT TO Vssl
- - - MECHANICAL
LINKAGE

Frequency: 3.579545MHz ± 0.02%
Rs 100Q, LM

.-0--

Ron (Contact Resistance),,",lkU

=96mH

CM = 0.02pF CH = 5pF CL = 12pF
Keyboard Interface
The 825089 can interface with the standard telephone
pushbutton keyboard (see Figure 1) with common. The
common of the keyboard must be connected to Vss.
Logic Interface
The 525089 can also interface with CMOS logic outputs
directly (see Figure 2). The 825089 requires active
"Low" logic levels. Low levels on a row and a column
input corresponds to a key closure. The pull·up resis·
tors present on the row and column inputs are in the
range of 20kQ-100kQ.
4.60

Tone Generation
When a valid key closure is detected, the keyboard
logic programs the high and low group dividers with
appropriate divider ratios so that the output of these
dividers cycle at 16 times the desired high group and
low group frequencies. The outputs of the program·
mabie dividers drive two 8·stage Johnson counters.
The symmetry of the clock input to the two divided by
16 Johnson counters allows 32 equal time segments to
be generated within each output cycle. The 32 seg·
ments are used to digitally synthesize a stair·step
waveform to approximate the sinewave function (see
Figure 3). This is done by connecting a weighted resis·
tor ladder network between the outputs of the Johnson

S25089
counter, Voo and VREF. VREF closely tracks Voo over the
operating voltage and temperature range and therefore
the peak-to-peak amplitude VP (VOO-VREF) of the stairstep function is fairly constant. VREF is so chosen that
VP falls within the allowed range of the high group and
low group tones.

Table 1. Comparison of Specified Vs. Actual
Tone Frequencies Generated by S25089

ACTIVE
INPUT

The individual tones generated by the sinewave synthesizer are then linearly added and drive an NPN transistor connected as an emitter follower to allow proper
impedance transformation at the same time preserving
signal level. This allows the device to drive varying
resistive loads without significant variation in tone
amplitude. For example, a load resistor change from
10kQ to 1kQ causes a decrease in tone amplitude of
less than 1dB.

Dual Tone Mode
When one row and one column is selected, dual tone
output conSisting of an appropriate low group and high
group tone is generated. If two digit keys that are not
either in the same row or in the same column are
depressed, the dual tone mode is disabled and no output is provided.

OUTPUT FREQUENCY Hz
SPECIFIED
ACTUAL

%ERROR
SEE NOTE

697

699.1

+0.30

770

766.2

-0.49

852

847.4

- 0.54

941

948.0

+0.74
+0.57

1209

1215.9

1336

1331.7

- 0.32

1477

1471.9

-0.35

1633

1645.0

+ 0.73

NOTE: "10 ERROR DOES NOT INCLUDE OSCILLATOR DRIFT

Single Tone Mode
Single tones either in the low group or the high group
can be generated as follows. A low group tone can be
generated by depressing two digit keys in the appropriate row. A high group tone can be generated by
depressing two digit keys in the appropriate column,
i.e., selecting the appropriate column input and two row
inputs in that column. This is slightly different from the
MK5089 which requires a low to a single column pin to
get a column tone.

Figure 2. Logic Interface for Keyboard
Inputs of the S25089

Inhibiting Single Tones
The STI input (pin 15) is used to inhibit the generation
of other than dual tones. It has an internal pull down to
Vss supply. When this input is left unconnected or connected to Vss , single tone generation as described in
the preceding paragraph (Single Tone Mode) is suppressed with all other functions operating normally.
When this input is connected to Voo supply, single or
dual tones may be generated as previously described
(Single Tone Mode, Dual Tone Mode).

voo

- I"--~
V

I--

- ---~
V

r--~

..-- ~

..--

---

K
V

- ..--i'--..
aV

5
9

Chip Enable Input (CE, Pin 2)
The chip enable input has an internal pull-up to Voo
supply. When this pin is left unconnected or connected
to Voo supply the chip operates normally. When connected to Vss supply, tone generation is inhibited. All
other chip functions operate normally.

R2
R3
-

_ S25089

c;
c;
-

Vss

Ves

Gl THRU G8 ANY TYPE CMOS GATE

4.61

-R,

voo

•

S25089

Figure 3. Stairstep Waveform of the Digitally Synthesized Sinewave
(Voo ) 1.0
0.9
0.8

>0.
C
W

0.7
0.6

....J

c:r:

:iE

a:
c

0.5

0.4
0.3
0.2
0.1
(V,ef)

TIME SEGMENTS

the AKD output goes to Vss. The device is large
enough to sink a minimum of 500~ with voltage drop
of 0.2V at a supply voltage of 3.5V.

Reference Voltage

The structure of the reference voltage employed in the
825089 is shown in Figure 4. It has the following
characteristics:

Figure 4. Structure of the Reference Voltage

a) VREF is proportional to the supply voltage. Output
tone amplitude, which is a function of (Voo - VREF), increases with supply voltage (Figure 5).
b) The temperature coefficient of VREF is low due to a
single VBE drop. Use of a resistive divider also provides
an accuracy of better than 1 %. As a result, tone amplitude variations over temperature and unit to unit are
held to less than ± 1.0dB over nominal.
c) Resistor values in the divider network are so chosen
that VREF is above the VBE drop of the tone output transistor even at the low end of the supply voltage range.
The tone output clipping at low supply voltages is thus
eliminated, which improves distortion performance.

AKD (Any Key Down or Mute) Output
The AKD output (pin 10) consists of an open drain N
channel device (see Figure 6.) When no key is depressed the AKD output is open. When a key is depressed

Vss

4.62

825089
Figure 5. Typical Single Tone Output Amplitude Vs Supply Voltage (At. = 10k)

800

700

600

:;E

500

'"
co
z

....

400

300

10
SUPPL Y VOLTAGE (VOLTS) - - . -

Figure 6. AKD output Structure

.--------~o

AKD

(PIN 10) AKD

OPEN WITH KEY RELEASED
LOW IMPEDANCE TO Vss
WITH KEY CLOSED.

)>---------l

(FROM INTERNAL
LOGIC)

Vss

4.63

AMI.-----------r

.""-

A Subsidiary
of Gould Inc.

S2561 0

10 MEMORY PULSE DIALER

Features
o Complete Pin Compatibility With S2560A and
S2560G Pulse Dialer Allowing Easy Upgrading of
Existing Designs.

Ten 1B-Digit Number Memories Plus Last Number
Redial (22 Digit) Memory On Chip.

Low Voltage CMOS Process for Direct Operation
From Telephone Lines.

Inexpensive R-C Oscillator Design With Accuracy
Better Than ± 5% Over Temperature and Unit-Unit
Variations.

Independent Select Inputs for Variation of Dialing
Rates (10pps/20pps), Mark/Space Ratio (331/3 -66 2/3/
40-60), Interdigit Pause (400ms/BOOms).

Can Interface With Inexpensive XY Matrix or Standard 2 of 7 Keyboard With Common. Also Capable
of Logic Interface (Active High).

Mute and Pulse Drivers On Chip.

Call Disconnect by Pushing * and # Keys
Simultaneously.

Pin Configuration

Block Diagram

R1
R4
KEYBOARD
INPUTS

KEYBOARD
INTERFACE

IPS

DRS

S~W~~ Hs
RATE
.AC
OSC

Co
RE

UP
MUTE

DRS

MIS

4.64

VoD

MIS

MUTE

Vss

825610
Absolute Maximum Ratings:
Supply Voltage ......................................................................................................................................................................... + 5.5V
Operating Temperature Range .................................................................................................................................. ooe to + 70 0 e
Storage Temperature Range ............................................................................................................................. - 40 0 e to + 125°e
Voltage at any Pin ..................................................................................................................................... Vss - O.3V to VDD + O.3V
Lead Temperature (Soldering, 10sec) .................................................................................................................................... 300 0 e

Electrical Characteristics:
Specifications apply over the operating temperature and
Symbol

1.5V~VDD

Vss~3.5V

Parameter

unless otherwise specified .
Conditions

Operating Voltage
Voo

Data Retention

1.0

Voo

Non Dialing State

1.S

3.S

On Hook, (HS = VDO )
Off Hook, Oscillator Not Running

Dialing State

2.0

3.5

Off Hook, Oscillator Running

Voo

Operating Current
100

Data Retention

1.0

2.0

100

Non Dialing

1.5

/AA
/AA

On Hook, (HS=Voo ) (Note 1)
Off Hook (HS = Vss ), Oscillator Not Running,
Outputs Not Loaded

100

Dialing

2.0
3.5

100
SOO

/AA
/AA

Off Hook, Oscillator Running, Outputs Not
Loaded

Output Current levels
10lOP

DP Output Low Current (Sink)

3.5

125

",A

VOUT = O.4V

10HOP

DP Output High
Current (Source)

1.5
3.5

20
125

",A
",A

VOUT = 1V
VOUT = 2.SV

10lM

MUTE Output Low Current (Sink)

3.S

125

/AA

VOUT = 0.4V

10HM

MUTE Output High
Current (Source)

1.5
3.S

20
125

",A

VOUT = lV
VOUT = 2.5V

Oscillator Frequency

2.0

Frequency Deviation

2.0 to
2.75
2.75 to
3.5

fo
,Molfo

/AA
10

kHz

-3

Fixed R-C oscillator components
50kQ~ Ro~ 750kQ; 100pF~ Co * ~ 1000pF;

-3

r50kQ~ RE~ SM~

300pF most desirable value for Co

Input Voltage levels
VIH

Logical "1"

80% of
(VDO-VSS )

Vil

Logical "0"

Vss
-0.3

CIN

Input Capacitance Any Pin

Voo
+0.3
20% of
(Voo- Vss )
7.5

V
V
pF

Note 1: 7S0nA max. data retention part available. Voo = 1.0 Volt

Functional Description

quires three external components; two resistors (Ro
and RE) and one capacitor (CD). All internal timing is
derived from this master time base. To eliminate
clock interference in the talk state, the oscillator is
only enabled during key closures and during the dialing state. It is disabled at all other times including

The pin function designations are outlined in Table
1.

Oscillator
The device contains an oscillator circuit that re-

4.65

•

825610
the "on hook" condition. For a dialing rate of 10pps the
oscillator should be adjusted to 2400Hz. Typical values
of external components for this are RD. RE = 750kQ and
Co 270pF. It is recommended that the tolerance of
resistors to be 1% and capacitor to be 5% to insure a
± 10% tolerance of the dialing rate in the system.

Figure 2. Standard Telephone Pushbutton Keyboard

:0-----.

Keyboard Interface
The 525610 employs a scanning technique to deter·
mine a key closure. This permits interlace to a DPCT
(Double Pole Common Terminal) keyboard with com·
mon connected to Voo (Figure 1), logic interface (Figure
2),or a XY matrix. A high level on the appropriate row
and column inputs constitutes a key closure for logic
interface.

RI-o-

,?t,

o.~

H"
".

4.71

+-;a

.~
CD~O

O"S

I
"0

S25610

~
"3

-r,;
I,'5

1PS

0
C

voo
MIS

Vss

'3
1'2

I '~,

"'0

.
S

r----

liP

"3~

3
r-----

33V3/66 2/3
40/60
On Hook
Off Hook

Vss
Voo
Voo
Vss

NOTE: f is the oscillator frequency and is detemined as shown in Figure 5.

YELLOW

MU1~

1
,

., .5
..

"'
111
C3

3
6
9
I

r---r----

•

AMII.---------rr

A Subsidiary
of Gould Inc.

S25610E

10 MEMORY PULSE DIALER

Features

Modified Version of the S25610 Repertory Dialer.
Optimized for European Applications

Ten 18-Digit Number Memories Plus Last Number
Redial (22 Digit) Memory On Chip.

Low Voltage CMOS Process for Direct Operation
From Telephone Lines.

o
o

Inexpensive R-C Oscillator Design With Accuracy
Better Than ± 5% Over Temperature and Unit-Unit
Variations.

o
o

Independent Select Inputs for Variation of Dialing
Rates (10pps/20pps), Mark/Space Ratio (33 V3 -66 213/
40-60)
Can Interface With Inexpensive XY Matrix or Standard 2 of 7 Keyboard With Common. Also Capable
of Logic Interface (Active High).
Mute and Pulse Drivers On Chip.
Call Disconnect by Pushing * and # Keys
Simultaneously.
Pin Selectable Access Pause/Wait Functions
Auto Pause Insertion
Pin Configuration

Block Diagram

R,
R4
KEYBOARD
INPUTS

C,D

s~W~~ Hs

WPS

itS

DRS

." ["'

RATE
OSC

CD
RE

iiP
MUTE

DRS

4.72

Voo

MIS

MUTE

tiP

Vss

S25610E
Absolute Maximum Ratings:
Supply Voltage ......................................................................................................................................................................... + 5.5V
Operating Temperature Range ........................................................................................................................... - 25°C to + 70°C
Storage Temperature Range ............................................................................................................................. - 40°C to + 125°C
Voltage at any Pin ..................................................................................................................................... Vss - O.3V to Voo + O.3V
Lead Temperature (Soldering, 10sec) .................................................................................................................................... 300°C

Electrical Characteristics:
Specifications apply over the operating temperature and

Symbol

Voo
Voo
Voo

1.5V~VDD

Vss~3.5V

Parameter

unless otherwise specified.

Conditions

Operating Vonage
Data Retention
Non Dialing State
Dialing State
Operating Current

1.5

3.5

On Hook, (HS = VO O)
Off Hook, Oscillator Not Running

2.0

3.5

Off Hook, Oscillator Running

1.0

Data Retention
Non Dialing

1.0
1.5

750
10

100

j.iA

On Hook, (HS = VOO )
Off Hook (HS = Vs s), Oscillator Not Running,
Outputs Not loaded

100

Dialing

2.0
3.5

100
500

j.iA
j.iA

Off Hook, Oscillator Running, Outputs Not
Loaded

10lOP
'OHOP

Output Current Levels
DP Output Low Current (Sink)
DP Output High
Current (Source)

3.5
1.5
3.5

125
20
125

IOlM

MUTE Output Low Current (Sink)

3.5

125

VOUT
VOUT
VOUT
VOUT

IOHM

MUTE Output High
Current (Source)

1.5
3.5

20
125

Oscillator Frequency

2.0

Afo/fo

Frequency Deviation

2.0 to
2.75
2.75 to
3.5

100

VIH

Input Voltage Levels
Logical "1"

VIL

Logical "0"

CIN

Input Capacitance Any Pin

-3

j.iA
j.iA
J.lA
j.iA
j.iA
J.lA
kHz
%

-3

80% of
Voo
(V oo - Vss) +0.3
20% of
Vss
-0.3 (Voo-Vss)
7.5

Functional Description
The pin function designations are outlined in Table
1.
Oscillator
The device contains an oscillator circuit that re4.73

VOUT
VOUT

=
=
=
=
=
=

O.4V
1V
2.5V
O.4V
1V
2.5V

Fixed R-C oscillator components *
50kQ~ Ro~ 750kQ; 100pF~ Co ~ 1000pF;
750kQ~ RE~ 5MQ
* 300pF most desirable value for Co

V
V
pF

S25610E
the "on hook" condition. For a dialing rate of 10pps the
oscillator should be adjusted to 2400Hz. Typical values
of external components for this are Ro, RE = 750kQ and
Co 270pF. It is recommended that the tolerance of
resistors to be 1% and capacitor to be 5% to insure a
± 10% tolerance of the dialing rate in the system.

Figure 2. Standard Telephone Pushbutton Keyboard

Keyboard Interface
The 525610 employs a scanning technique to determine a key closure. This permits interface to a DPCT
(Double Pole Common Terminal) keyboard with common connected to Voo (Figure 1), logic interface (Figure
2),or a XY matrix. A high level on the appropriate row
and column inputs constitutes a key closure for logic
interface.

~,-

:0------,
-Q--Q--Q

Q--Q--Q--'-I~R2
R3~'--

-Q--Q--Q
0--8--0-- -, ~

Figure 1. SPST Matrix Keyboard Arranged In a Row,
Column Format

{CONNECT TO VOO
- - - MECHANICA~
. LINKAGE
Ron (Contact ReSistance)

Off Hook Operations: The device is continuously
powered through a 150kQ resistor during off hook operation. The DP output is normally high and sources base
drive to transistor 01 to turn ON transistor 02. Transistor 02 replaces the mechanical dial contact used in
the rotary dial phones. Dial pulsing begins when the
user enters a number through the keyboard. The DP
output goes low shutting the base drive to 0 1 OFF
causing O2 to open during this pulse break. The MUTE
output also goes low during dial pulsing allowing
muting of the receiver through transistors 0 3 and 0 4 ,
The relationship of dial pulse and mute outputs are
shown in Figure 3.

C1
SPST MATRIX KEYSORTEb

I
)N.O.

lkU

KEYBOARD SPECIFICATIONS:
RON (KEY ON RESISTANCE ,,1kQ
KEYBOUNCE TIME
,,10ms

The dialing rate is derived by dividing down the dial rate
oscillator frequency. Table 2 shows the relationship of
the dialing rate with the oscillator frequency and the
dial rate select input. Different dialing rates can be
derived by simply changing the external resistor value.
The dial rate select input allows changing of the dialing
rate by a factor of 2 without the necessity of changing
the external component values. Thus, with the oscillator adjusted to 2400Hz, dialing rates of 10 or 20pps
can be achieved. Dialing rates of 7 and 14pps similarly
can be achieved by changing the oscillator frequency
to 1680Hz.

On Hook Operation: The device is continuously powered
through a 10-20MQ resistor during the on hook operation. This resistor allows enough current from the tip
and ring lines to the device to allow the internal memory to hold and thereby providing storage of the last
number dialed. DP and mute outputs are low in the on
hook state.
Any key depressions during the on-hook condition are
ignored and the oscillator is inhibited. This insures that
the current drain in the on-hook condition is very low
and used to retain the memory.
4.74

S25610E

Figure 3. Timing (Dial, Redial)

NORMAL DIALING

iii

10 ,

(ON HOOK)

_KE_Y_BO_AR_D_IN_Pu_T______

AUTO PAUSE
INSERTED

(OFF HOOK)

~~L

-I

______

~"IDP~M:

OOO__ _ _ _ _ _ _ _ _ _ _ _

siMI s:

1M: S

AUTO PAUSE
INSERTED
,

~---~

idl

------------1-~-----l.!..I
iiP

~M~UT~E________~r___1~
OSC

OFF

IDP 1M: S

i
I

lOP IMl S 1M! S

!di

---------------

~r-+-:

______

ooo__ _ _ _ _ _ _ _ooo__ _

1111

OFF

1/11

REOIALING

...., 12 ,....

KEYBOARD INPUT

I ,

, IDP 'M' S 'M'

..;;.DP~____',.

OSC

---------~l_--~I~I .~_~

•

OFF

i2.J

'M! S '):::::::=PAUSE----t

,,"

I2J -- ul!J

III!

1,: KEY DEBOUNCE TIME: 10ms
12 :. KEY RELEASE TIME: 2ms
d : PULSE TURNOFF TO MUTE TURNOFF DELAY TIME: 200",s
10 : OFF HODK TO KEYBOARD INPUT DEL AY TIME: 2ms

!DP ',MI, S', IDP ',M', S',M', S ',d',

ooo__ _ooo__ _

IIIIOFF

NOTE: TYPICAL WAVEFORMS DURING NORMAL DIALING AND REDIALING
(ASSUMES PAUSE OPTION IS SELECTED)
(TIME BASED ON OSCILLATOR FREQUENCY OF 2400Hz)

The Inter-Digit Pause (lOP) time is also derived from the
oscillator frequency and it is a function of the dialing
rate selected by the dial rate select input. If the oscillator is set to 2400Hz so that a dialing rate of 10pps is
obtained with DRS = Vss. Then an lOP of aOOms is
automatically selected. Switching the dialing rate to
20pps (DRS Voo) will lower the lOP to 400ms.

The user can enter a number up to 22 digits long from a
standard 3 x 4 XY matrix keypad (Figure 1). It is also
possible to use a logic interface or a keyboard with
common (Figure 2) for number entry. Antibounce protection circuitry is provided on chip (min. 9ms) to prevent false entry.

4.75

S25610E
Table 1. S2561 DE PIn/Function Descriptions
Pin Functions
Pin Number
Function
Keyboard
These are 4 row and 3 column inputs from the keyboard contacts. These in2,3, 4, 1, 16, 17, 18 puts are open when the keyboard is inactive. When a key is pushed, an appro(R1' R2 , R3, R4 , C1 , C2, C3)
priate row and column input must go to Voo or connect with each other. A logic
interface is also possible as shown in Figure 2. Active pull up and pull down
networks are present on these inputs when the device begins keyboard scan.
The keyboard scan begins when a key is pressed and starts the oscillator. Debouncing is provided to avoid false entry (typ. 10ms).
Walt·Pause Select (WPS)
This is a Tri-Function input pin. Leaving it open selects the access wait func15
tion. Connect to Voo selects access pause duration of 3.2sec. and connection
to Vss selects the access pause duration of 6.4sec. For detailed .description of
wait/pause functions see Operating Characteristics.
Dial Rate Select (DRS)
14
A programmable line allows selection of two different output rates such as 7 or
14pps, 10 or 20pps, etc. See Tables 2 and 4. Interdigit Pause (lOP) is a function of the selected dialing rate.
Mark/Space (M 1S)
12
This input allows selection of the mark/space ratio, as per Table 4.
Mute Out (MUTE)
11
A pulse is available that can provide a drive to turn on an external transistor to
mute the receiver during the dial pulsing. Normally it is "high"'and "low"
during dialing. It is "low" on hook.
Dial Pulse Out (DP)
Output drive is provided to turn on a transistor at the dial pulse rate. The nor9
mal output will be "low" during "space" and "high" otherwise. On hook it
is "low".
Dial Rate Oscillator
6,7,8
These pins are provided to connect external resistors RD, RE and capacitor CD
to form an R-C oscillator that generates the time base for the Key Pulser. The
output dialing rate and lOP are derived from this time base.
Hook Switch (H S)
This input detects the state of the hook switch contact; "off hook" cor5
responds to Vss condition. It is debounced during dialing. An interruption of
150ms or less will be ignored while that excess of 300ms will cause the device
to go into standby condition.
Power (Voo , Vs s)
13, 10
These are the power supply inputs. The device is designed to operate from
1.5V to 3.5V.
Table 2. Table for Selecting Oscillator Component Values for Desired Dialing Rates and Inter-Digit Pauses
Dial Rate
Ose. Freq.
Dial Rate (pps)
IDP(ms)
RD
RE
CD
Desired
(kQ)
(Hz)
(kQ)
(pF)
DRS = VDD
DRS = Vss
5.5/11
1320
5.5
11
14541 727
6/12
1440
12
13341 667
6
6.5113
1560
6.5
13
12301 615
7/14
1680
Select components in the
7
14
11421 571
7.5115
1800
ranges indicated in table
7.5
15
10661 533
8/16
1920
of electrical specifications
16
10001 500
8
8.5117
2040
17
942 1 471
8.5
9/18
18
888 1 444
2160
9
9.5/19
19
842 1 421
2280
9.5
10/20
2400
10
20
800 1 400
750
I 750 l 270

(fd /24O )1
(fd /12O)

(fd /24O )

(fd /12O )

1920 103
fi
x

960 103
fi x

Notes:
1. IDP is dependent on the dialing rate selected. For example, for a dialing rate of 1Opps, an lOP of either 800ms or 400ms can be selected. For a dialing
rate of 14pps, an IDP of either 1142ms or 571ms can be selected.

4.76

S25610E
Operating Characteristics
Normal Dialing
Off Hook,

G, ------- G

Dial pulsing to start as soon as first digit is entered
and debounced on the chip. Total number of digits
entered not to exceed 22. Numbers exceeding 22
digits can be dialed but only after the first 22 digits
have been completely dialed out. Access wait or
pause can be inserted by pressing the "#" key. Any
number of waits or pauses can be entered as long as
the total number of digits does not exceed 22. Additionally in the "pause" mode, pause is inserted automatically (two maximum) if no further digits are
entered by the time mute turns off. (Figure 3.)

Storing of a Telephone Number(s)
Numbers can be stored as follows:
Off Hook,

D, G, ----G, D, B

0, B

Off hook,

[!] ,[!] ----- G

---G

(wait for dialing to complete
before pressing 01 key)

Disconnecting call

c::J [!]

d. Inhibiting future redialing of a normally dialed
number

sequence after completion of dialing of present sequence. If an access pause has been stored in "LOC",
dialing will halt until the "#" key is pushed again. If an
access pulse is detected dialing will stop for the
selected duration.

Off hook,

G ---G -----c:J'~

(wait for dialing to complete before pressing star
key)

Pushing * key twice after normal dialing is completed
instructs the device to clear the redial buffer.
e. To clear a memory location(s)

Redlallng

Last number dialed can be redialed as follows:
Off Hook,

b. Normal dialing after memory dialing or redialing

Pushing * and # keys simultaneously causes DP and
mute outputs to go low and remain low until the keys
are released. This causes a break in the line. If the keys
are held down for a sufficiently long time (approx.
400ms), the call will be disconnected and new dial tone
will be heard upon release of the keys. This feature is
convenient when disconnecting calls by the normal
method, i.e., hanging up the phone or depressing
hookswitch is cumbersome.

Memory Dialing

Numbers can be cascaded repeating

G ,- --G -----c::J '[!] ,B

(wait for dialing to complete before pressing star
key)

Off hook, - - - - - ,

D, G, ---G, D, B

Off Hook,

Access wait/pause can be inserted in the stored sequence by pushing the "#" key. Any number of
waits/pauses may be stored as long as the total
number of digits does not exceed 22.

Off Hook,

Special Sequences
There are some special sequences that provide for
mixed dialing or other features such as call disconnect, redial inhibit or memory clear as follows:
a. Normal dialing followed by repertory dialing

0 ,0

Off hOOk,c:J

,[!] ,e:] §J ,---G ,[!] ,e:] ~

Essentially this operation is equivalent to storing a
pause in the memory location.

Last number for this purpose is defined as the last
number remaining in the buffer. Access pause is terminated by pushing the "#" key as usual. If the device is
operated in the "pause" mode and if an access pause
was automatically inserted during normal dialing, during redialing the dialing will be stopped for the pause
duration selected.

The various operating characteristics are summarized
in Table 3.

4.77

•

S25610E
Table 3. Summary of Operating Characteristics

B -----G

1) Normal Dialing:

off hook

2) Inhibit Redialing:

off hook

,G ---G ------------ G,G

3) Redialing:

off hook

4) Storing of Number(s):

off hook

5) Memory Dialing:

off hook

(wait for dialing to complete before pressing star key)

[!] ,[!]

,G,G G,G8-----G,G G,[:J~
[!] 8 ------------[!] ,~
,G --- G ------------ G,[!],~
[!] ,[!] ~
G -- G
,

(wait for dialing to complete before pressing # key)

6) Normal Dialing + Memory Dialing:

off hook

(wait for dialing to complete before pressing star key)

7) Recall + Normal Dialing:

off hook

, - - '- - - - - - - - - - -

(wait for dialing to complete before pressing 01 key)

8) Call Disconnect:

off hook

9) Clear Memory Location(s):

off hook

I*lrfl
,[:J,[!],G,Ej --- [:J,[!],G Ej
LJ L.:.J

Figure 4. Memory Dialer Circuit with Redial

Ro=10-20MQ. RI =150kQ. R2=2kQ
R3=470kQ. R4 . R5=10kQ. RIO=47kQ
R6. Rs=2kQ. R7. Rg=30kQ. RII=20Q. 2W
ZI=3.9V. DI -D 4 =IN4004. D5. 06. 07=IN914. CI =15/AF

4.78

RE=Ro=750kQ. Co=270pF. C2=001/AF
0 1 . 04 = 2N5550 TYPE 02. 03 = 2N5401 TYPE
Z2= IN5379 110V ZENER OR 2XIN4758

S25610E
Table 4.

Function

Pin Designation

Input Logic Level

Selection

DRS

VDD

960 - slOP
y

Dial Rate Selection and

(f/120)pps
(f/240)pps

Inter-Digit Pause Selection
Vss

VDD
Vss

On Hook/Off Hook

slOP

33V3/66 213
40/60
On Hook
Off Hook

Vss
VDD

M/S

Mark/Space Ratio

1920
f

Figure 5. Memory Dialer Circuit with Redial (Single Hook Switch Contact Application for PABX)

YELLOW

;..
'--.-----~

Voo

HOLD
OUT

CJ 3.58MHz

825910

C4
15

C3
C2

iiS

.11'

Cl
14
HI
H2 13
12
R3

6 Vss
10 MUTE
TONE
16

7 8

130Q

Figure 3. 825910 Timing Diagram Hold Waveform Details

i-t1-1

.:. _____________________I l. . ___

HOLDKEY_ _~h

MUTE

HOLD

------'

------~I

:.....'---------SINGLE HOLD TONE MODE ----------~.I
I

TONE OUT

I
I

:-t2--1- t3----.J
1,: 10m8 MIN
t2. t3: APPROXIMATELY BOOms

4.85

S25910/S25912
Figure 4. 525912 Memory Dialer Applications Circuit
HOLD
OUT

'---.......------4II---_-.--------'-i Voo

825912

iiS

.1~

.--_-+_......._---11--_ _-+-_~---<___-

____..---~6 VSS
10 MUTE
TONE R4 11

13012

Figure 5. 525912 Timing Diagram Hold Operation

HOLD
KEY

--+-:

t1 ~
1

----~L_J~------------------~L_J
1
1
~

HOLD

t21--

I
I

--I
I

t2 I.-I

INPUT

TONE
OUT

1.--

t3 --..11

II~t3~:
MUTE

HOLD
t1: 10ms MIN t2: lOOms TYP t3: aOOms TYP

4.86

AIMII.---------."""'4.

A Subsidiary
of Gould Inc.

83506183507183507 A

CMOS SINGLE CHIP /A-LAW/A-LAW
SYNCHRONOUS COMBO CODECS WITH FILTERS

Features
o Independent Transmit and Receive Sections With
75dB Isolation
o Low Power CMOS BOmW (Operating) BmW (Standby)
o Stable Voltage Reference On-Chip
o Meets or Exceeds AT&T 03, and CCITT G.711,
G.712 and G.733 Specifications
o Input Analog Filter Eliminates Need for External
Anti-Aliasing Prefilter
o Input/Output Op Amps for Programming Gain
o Output Op Amp Provides ± 3.1V into a 600Q Load or
Can Be Switched Off for Reduced Power (70mW)
o Special Idle Channel Noise Reduction Circuitry for
Crosstalk Suppression

o
o

Encoder has Dual-Speed Auto-Zero Loop for Fast
Acquisition on Power-Up
Low Absolute Group Delay 450!Jsec. @ 1kHz

General Description
The S3506 and S3507 are monolithic silicon gate CMOS
Companding Encoder/Decoder chips designed to implement the per channel voice frequency Codecs used
in PCM systems. The chips contain the band-limiting
filters and the analog-digital conversion circuits that
conform to the desired transfer characteristic. The
S3506 provides the European A-Law companding and
the S3507 provides the North American wLaw companding characteristic.

Block Diagram

Pin Configuration (22 Pin)
v",
T·SHIFT

Vss

ClKSEl

V,,(}04-+-------,
835061
S3507
PCMOUT

BIN

T·A/BSEl

mOUT

OUT-

Pin Configuration (28 Pin)
BIN

Vou (HV)

CLK SEL

T·AlB SEL

T·SHIFT
ADUT

VIlIlI

T·STRDBE

R.STROBEo-+-------------'

SYSClK

SYS CLK

FLT OUT

PCM OUT

PUN

U GNU

BOUT

IN-

A OUT

IN+

R·AIB SEL
R·SHIFT
R·STROBE

4.B7

VOUT

OUT-

HTROBE

CAl

OGHO

VREF

A IN

CAl GNU
A GNU
Vss (-5V)

PCM IN

83506183507183507 A
and its simplified timing requirements. Figure 6 shows
a schematic for a typical digital telephone design.

A Digital Telephone Application
Most new PABX designs are using PCM techniques for
voice switching with an increasing trend toward applying them at the telephone level. The simplest form of a
digital telephone design uses four wire pairs to interface to the switch. Two pairs carry transmit and receive
PCM voice data. One pair supplies an 8kHz synchronizing clock signal and the remaining pair supplies power
to the telephone. More sophisticated designs reduce
costs by time-division-multiplexing and superimposition techniques which minimize the number of wire
pairs. The AMI Single-chip Codec is ideally suited for
this application because of the low component count

Since asynchronous time slot operation is not
necessary, transmit and receive timing signals are
common. A phase-lock-loop derives the 256kHz system
clock and 64kHz shift clock from the 8kHz synchronizing signal received from the switch. The synchronizing
signal also serves as the transmit/receive strobe signal
since its duty cycle is not important for Codec operation. Microphone output feeds directly into the coder
input while the decoder output drives the receiver
through an impedance transformer to complete the
design.

Figure 6. Voice Processing in a Digital Telephone Application

S10R

S3S06 OR
S3507
CO DEC
W/FILTER

n""'j

PCM
IN
TSTROBE

RECEIVE

SWITCH
INTERFACE

SYNC
TSHIFT
RSHIFT

19 FLTOUT

CLKSEL
SYSCLK

CD4046
PLL

2S6kHz

CAZ(O.l"F)

C2~.lPF

04
6
(+16)
CD4024
COUNTER/DIVIDER
02
11 RESET (+4)

4.88

05
(+32)

~1~ll~~~~~
."""'4.

A Subsidiary
of Gould Inc.

844230 Family

Advanced Product Description

Single Chip Codecs With Filters
844231 A-Law Synchronous Codec
844233 A-Law Asynchronous Codec

S44232 IA'"Law Synchronous Codec
S44234 ~Law Asynchronous Codec
chips designed to perform the per channel voice frequency encoding/decoding used in PCM systems. The
chips contain the band limiting filters and analog ++
digital circuits necessary to conform to A-Law/J.lLaw
companding characteristics called out in CCID specifications.
These circuits provide the interface between the
analog signals of the subscriber loop and the digital
signals of the PCM highway in a digital telephone
switching system. The devices operate from dual
power supplies of ± 5V.
For a sampling rate of 8kHz, PCM input/output data
rate can be selected from 1536/1544/2048MHz in synchronous operation. This selection is achieved automatically.

Features
o Synchronous or Asynchronous Operation for
2048/1544/1536 KHz PCM Rate
o Precision Voltage Reference
o Meets or Exceeds AT&T 03, CCID G.711, G.712
and G.733 Specifications
o Low Power Dissipation: 60mW Typical
o Auto-Zero Cancel Circuitry Requires No External
Components
o Input Op Amp for Gain Adjustment
o Anti-aliasing Filter
o Licensed Second Source for Hitachi
General Description
The 544231/213/4 are monolithic silicon gate. CMOS

Pin Configuration

Block Diagram

AJN

VCC(5V)

GAl
GA2
PCMOUT

A GND

(N.C.)

VREF

SYNC

(N.C.)

AIM
GAl
GA2
A GND
AouT

VSS UNO DGND

CLDCK
PCMIN

Vss
PCMOUT
PD
D GND
lX.SYNC

VREF

RCV.SYNC

Vou

lX.CLOCK

PCMII

4.89

PD
D GND

AoUT

Vou

VOD

Vss
PCMOUT

RCV.CLOCK

·I :
-

844230 Family
Table 1A. Pin Descriptions (5442311544232)

No.

Symbol

Function

AIN
GA1

Analog Input
Gain Adjust1

Feed-Back Input

GA2

Gain Adjust2

10kQ~ RL~20kQCL<100pF

A GND

Analog Ground

Remarks

AOUT

Analog Output

RL~3kQ,CL~100pF

VREF

External VREF

Open or (2-3V)

Positive Power Supply

5V±5%

Voo
(N.C.)

9
10

PCM 1N
CLOCK

PCM Data Input

(TTL)

PCM Bit Clock

(TTL) 2048/15441 1536kHz

SYNC

Synchronization

(TTL) 8kHz

(N.C.)

o GND

Digital Ground

Power Down

(TTL) "0" = down

PCM OUT

PCM Data Output

Open Drain

Vss

Negative Power Supply

-5V±5%

Table 1B. Pin Descriptions (544233/544234)

No.

Symbol

Function

AIN
GA1

Analog Input

Gain Adjust1

Feed-Back Input

GA2

Gain Adjust2

1OkQ~ RL~ 20kQCL < 1OOpF

A GND

Analog Ground

AOUT

Analog Output

RL~3kQ,CL~ 1OOpF

External VREF
Positive Power Supply

Open or (2-3V)

VREF

Voo
(N.C.)

8
9

Remarks

5V±5%

RCV CLK

RCV PCM Bit Clock

(TTL) 2048/15441 1536kHz

TX CLK

TX PCM Bit Clock

(TTL) 2048/1544/1536kHz

RCV SYNC

Synchronization

(TTL) 8kHz

TX SYNC

Synchronization

(TTL) 8kHz

o GND

Digital Ground

Power Down

(TTL) "0" = down

PCM OUT

PCM Data Output

Open Drain

Vss

Negative Power Supply

-5V± 5%

4.90

S44230 Family
Absolute Maximum Rating
No.

Item

Voo

-0.3to +6V

+0.3 to +6V

Vss
Storage Temperature

Power Dissipation

0.5W

Digital Input Voltage

Analog Input Voltage

-0.3V60

GAH

Attenuation of 941 Hz

Symbol

Parameter/Conditions

Max.

Units

Attenuation Between Groups

dB wrt
700Hz
dB wrt
1200Hz

Total Harmonic Distortion
THD

Total Harmonic Distortion (dB). Dual tone of 770Hz and 1336Hz sinewave applied at the input of the filter at a level of 3dBm each. Distortion
measured at the output of each filter over the band of 300 Hz to 10kHz
(VOD = 12V)
Idle Channel Noise

-40

ICN

Idle Channel Noise measured at the output of each filter with C-message
weighting. Input of the filter terminated to BVREF

mVrms

Group Delay (Absolute)
GDL

Low Group Filter Delay over the band of 50Hz to 3kHz

4.5

6.0

GD H

High Group Filter Delay over the band of 50Hz to 3kHz

4.5

6.0

Pin #

Function

Descriptions

16,17

OSC 1N , OSCOUT

These pins are for connection of a standard 3.579545MHz TV crystal and a 10MQ
± 10% resistor for the oscillator from which all clocking is derived. Necessary
capacitances are on-chip, eliminating the need for external capacitors.

CKOUT (S3525A)

Oscillator output of 3.58M Hz is buffered and brought out at this pin. This output
drives the oscillator input of a decoder chip that uses the TV crystal as time base.
(Only one crystal between the filter and decoder chips is required.)

CKOUT (S3525B)

This is a divide by 4 output from the oscillator and is provided to supply a clock to
decoder chips that use 895kHz as time base.

11,12,13

IN -, IN +, Feedback

These three pins provide access to the differential input operational amplifier on
chip. The feedback pin in conjunction with the IN - and IN + pins allows a programmable gain stage and implementation of an anti-aliasing filter if required.

15,14

FH OUT, FL OUT

These are outputs from the high group and low group filters. These can be used as
inputs to analog receiver circuits or to the on-chip limiters.

HI IN -, HI IN +
LO IN-, LO IN+

These are inputs of the high group and low group limiters. These are used for
squaring of the respective filter outputs. (See Figure 2.)

9,10,5,6
8,7

FHSO, FLSO

These are respectively the high group and low group square wave outputs from the
limiters. These are connected to the respective inputs of digital decoder circuits.

1,4

VOD , Vss

These are the power supply voltage pins. The device can operate over a range of
7V~(VOD - Vss)~13.5V.

VREF

BVREF

An internal ground reference is derived from the Voo and Vss supply pins and
brought out to this pin. VREF is 112(Voo - Vss ) above Vss.
Buffered VREF is brought out to this pin for use with the input and limiter stages.
4.143

S3525A1S3525B

Figure 1. Typical 83525 DTMF Bandspllt Filter Loss/Delay Characteristics

1.6dB - - 0.8dBlOCTAVE
ROLLOFF

19.8I1dB(600Hz) - - -

iii'
~

- - 60dB (1209Hz)

§
70
5.0
4.5

4.0
3.5
3.0
100

2.5

110

1.5

2.0

"'
i
.!.

1.0
0.5
0.5

1.0

3.0

1.5
FREQUENCY (kHz)

Input Configurations
The applications circuits show some of the possible input configurations, including balanced differential and
single ended inputs. Transformer coupling can be used
if desired. The basic input circuit is a CMOS op amp
which can be used for impedance matching, gain
adjustment, and even filtering if desired. In the differential mode, the common mode rejection is used to reject
power line-induced noise, but layout care must be
taken to minimize capacitive feedback from pin 13 to
pin 12 to maintain stability.
Since the filters have approximately 6dB gain, the in4.144

puts should be kept low to minimize clipping at the
analog outputs (FlouT and FHoUT).

Output Considerations
The S3525 has both analog and digital outputs
available. Most integrated decoder circuits require
digital inputs so the on-chip comparators are used with
hysteresis to square the analog outputs. The sensitivity
of the receiver system can be set by the ratio of R1 and
R2, shown in Figure 2. The amount of hysteresis will set
the basic sensitivity and eliminate noise response
below that level.

83525A/835258

Figure 2. Typical Squaring Circuit

S3525 BANDSPLIT FilTER
I

I
I lOW GROUP
I SQUARED OUTPUT
I
L _____ ...JI

Crystal Oscillator

The S3525 crystal oscillator circuit requires a 10 Meg
ohm resistor in parallel with a standard 3.58MHz television colorburst crystal. For this application, however,
crystals with relaxed tolerances can be used. Specifications can be as follows:
Frequency
RS~180Q

=18pF

3.579545 ± .02%
LM rv 96MH
Ch 7pF

·I :

ASSUMING BVREF=O OR
%(Voo-VSS) then
UTP = ED(SAT) _ _
R1_
R1 + R2
l TP -ED(SAT) _ _
R1_
R1 + R2

mal design can be developed for each individual application.
Companion decoders to be used with the S3525 vary in
performance and features. Nitron's NC2030 and
MOSTEK's MK5102/03 are available units that can be
used with the S3525.
. Figure 2A. 535258 Driving MK5103

Alternate Clock Configurations

If 3.58MHz is already available in the system it can be
applied directly as a logic level to the OSCIN (pin 16).
[Max. zero rv 30% Vo o, min. one rv 70% Voo]. Waveforms
not satisfying these logic levels can be capacitively
coupled to OSC 1N as long as the 10 Meg ohm feedback
resistor is installed.
The S3525A provides a buffered 3.58MHz signal from
the on-chip oscillator to external decoders or other
devices requiring 3.58MHz. The S35258 provides a buffered + 4 output at 895kHz to drive certain tone
decoders and microprocessors. If both frequencies are
required in a system, the 3.58MHz can be capacitively
coupled as shown in Figure 2A.
Applications
The circuits shown are not necessarily optimal but are
intended to be good starting points from which an opti4.145

lAP

ClK

IRQ 0

895kHz
+10V

Vou

CKOUT 18
OSCo 17

S35258
OSC! 16

ST 4
MK5103
Nle 3 OSCOUT

S3525AI S35258
Typical Applications
Figure 3. DTMF Keyboard

Wirellne DTMF Signal Receivers

o
o

Radio DTMF Signal Receivers
Dial Tone Detectors

697--8-0 -Gt0--

o
o
o

Offsite Data Collectors/Test Instruments

770--8-~-~+~--

Security Alarms

I
I

852--[2J-~-0tG--

Remote Command Receivers

941--GJ-~-0tG--

Phone Message Playback

1209 NORMA~~:l:PHDNE 1477 i 18~:C~Al

Camera Controllers
Robot Arm Controllers
Figure 4. AMI/Mostek 2 Chip DTMF Receiver
430

+12V------~------------------------------~NY------_,--_,~__,

l~F

3,9K

CLOCK
,OS"F

470K
12
HI GROUP
STROBE

MOSTEK
MKS103
DECODER
10

470K

BINARY
OUTPUT

LOW GROUP

ALL RESISTORS IN OHMS All
CAPACITORS IN ~FARADS UNLESS
MARKED OTHERWISE

Figure 5. AMI/Nitron 2 Chip DTMF Receiver
+12V

I I

3.58MHz

116

.1~F

AUDIOIN

o--j"

l~F

AMI
S352SA
FILTER

\12
"'T"

ALL RESISTORS IN OHMS ALL
CAPACITORS IN ~FARADS UNLESS
MARKED OTHERWISE

'\7

20K

5
14

1.7K

8
25

HI GROUP

39K
11

CLOCK

18
8

lSl:;:l~F

F13
39K

5.1V ZENER_.-

f-18

NITRON
NC2030
26

.l....

f----::r .1~F
LO GROUP

7
BVREF

Additional information can be obtained from the 53525 Applications Note # AN-30t available on request from AMI, and from the suppliers of the decoder circuits,

4.146

BINARY
OUTPUT

1.7K
20K

STROBE

510Q

lOOK

All
10K

83525A/835258

Figure 6. DTMF Encf.to-end Signaling Using the Telephone Network

~""--CO---""
~

_____

DTMF
RECEIVER

/'--C-EN-TR-AL---'
OFFICE

CENTRAL
OFFICE

~
AUTO· ANSWER
DTMF
RECEIVER
REMOTELY
CONTROLLED
DEVICE
(408) 246·0330

(914) 352·5333 DTMF
HIGH SPEED
---DIAUNG
.,-------INTER·OFFICE
OF PHONE NOS..
SIGNAUNG (MF)

.1- .

'-------------~~~~OS~N:AUNG--------------t·

Remote Control

Dial Tone Detector

In some systems, a telephone set is used to do remote
controlling. A remote device to be signalled is interconnected to the telephone network with its own number (see Figure 6). When that number is dialed, the connection is established. The calling party continues to
push the buttons on his telephone, sending command
codes.* The DTMF Receiver at the central office is
disconnected once the line connection is established,
so no-problem arises in the telephone network. Now
the DTMF Receiver in the answering device is detecting and responding to the dialed digits, performing the
control functions.

Since the frequency response of switched capacitor
filters can be varied directly by varying the clock frequency, the S3525 can be used for other Telecommunications applications.
One application is a dial tone detector for telephone
accessory equipment to determine the presence or
absence of dial tone. Precision dial tone is a combination of 350 and 440Hz. By using a crystal of 1.758MHz
the 3dB points of the low group filter output will be 334
to 496Hz. Thus, all the energy from preCision dial tone
will be available at the low group output.

* Need "Polarity Guard" or non-reversing central office so encoder stays enabled.

4.147

AMI.---------."""'4.

A Subsidiary
of Gould Inc.

Advanced Product Description

83526

SINGLE FREQUENCY TUNEABLE
BANDPASSINOTCH FILTERITONE GENERATOR

Features

General Description

D Center Frequency of Filters Match and Track Frequency of Generated Tone
D Tone Frequency Adjustable Over a 100Hz to 5kHz
Range
D Unfiltered Input, Input with Notched Tone, Input
Tone and Tone Generator Outputs
D Operation from a Crystal or External CMOSITTL
Clock
D Operation at 2600Hz from a Low Cost 3.58M Hz TV
Color Burst Crystal or 256kHz Ext. Clock
D Buffered Output Drives 600Q Loads
D Single or Split Supply Operation
o Low Power CMOS Technology

The S3526 is a low power CMOS Circuit which may be
used in a variety of single frequency (SF) communication applications such as SF-Tone Receivers, Tone
Remote Control in Mobile systems, Loopback Diagnostics in Modems, control of Echo Cancellers, dialing and
privacy functions in Common Carrier Radio Telephone,
etc. The main functional blocks of the S3526 include a
low distortion tone (sinewave) generator whose frequency may be programmed using a crystal (Le. 2600Hz
using a low cost TV color burst crystal) or external
clock time base; a bandpass filter used to extract tone
information from the input signal; a band reject filter
which is used to "Notch" out tone information from the
input signal; and a buffer amplifier with selectable input (unfiltered input signal, or input signal with tone
notched) capable of driving a 600Q load.

Block Diagram

Pin Configuration

cif 0 - - 1 - - - - - - - ,

OSCo

TONE

CS~r--+--------+------~-,

INPUT

INPUT C>-:-1---------'--.------------4~

INV
BUFF

~O--~---------------~

4.148

VA8

OSCo

BPF

INV

TONE

BPF

NOTCH

cif

OSCI

Vss

BUFF

Voo

NOTCH

83526
Absolute Maximum Ratings
Supply Voltage (Voo - Vss) ............................................................................................................................ + 15.0V
Operating Temperature ....................................................................................................................... O°C to + 70°C
Storage Temperature .................................................................................................................... - 65°C to + 150°C
Input Voltage, All Pins .................................................................................................. Vss - O.3V51dB for f>1.3fc
o Uncommitted Input and Output Op Amps for AntiAliasing and Smoothing Functions
o Steps May Be Custom Programmed from a Set of
2,048 Discrete Points Via Internal ROM
o Low Power CMOS Technology

Typical Applications for the S3528 and S3529
Programmable Filters
Telecommunications

o
o
o
o

PBX and Trunk Line Status Monitoring
Automatic Answering/Forwarding/Billing Systems
Anti-Alias Filtering
Adaptive Filtering

Remote Control

o
o
o

Alarm Systems
Heating Systems
Acoustic Controllers

Test Equipment/Instrumentation

o
o
o
o

Spectrum Analyzers
Computer Controlled Analog Circuit Testers
Medical Telemetry/Filtering
ECG Signal Filtering
Automotive Command Selection and Filtering
Pin Configuration

83528 Block Diagram
Vop

o,;;-t-------,

SIG(lN)

oscoQ-:-,-+-------,
osc,

DoHP

Yss

OSCo

Ypp

Oser

BUFF OUT
DO

Vss

AGHP

DSHP

4.156

SIG IN

BUFF IN

AGHP

FLT OUT

83528
Typical Applications for the S3528 and S3529
Programmable Filters (continued)
Audio

o
o
o
o

Electronic Organs
Speech Analysis and Synthesis
Speaker Crossovers
Sonabuoys
D Spectrum Selection
o Low Distortion Digitally Tuned Audio Oscillators

General Description
The S3528's eMOS design using switched-capacitor
techniques allows easy programming of the filter's cutoff frequency (fd in 64 steps via a six-bit control word.
For dynamic control of cutoff frequencies, the S3528
can operate as a peripheral to a microprocessor system
with the code for the cutoff frequency being latched in
from the data bus. When used with the companion high
pass filter, the S3529, a bandpass or a band reject filter
with a variable center frequency is obtained. For
special applications the S3528's internal ROM can be
customized to accommodate a specific set of cutoff
frequencies from a choice of 2,048 possibilities.

Absolute Maximum Ratings
Supply Voltage (Voo - Vss) .............................................................................................................................. + 15.0V
Operating Temperature .......................................................................................................................... ooe to + 70 0 e
Storage Temperature ..................................................................................................................... - 65°e to + 150 e
Input Voltage, All Pins ..................................................................................................... Vss - O.3V~VIN~VOO + O.3V
0

D.C. Electrical Operating Characteristics: TA
Symbol

VDD
PD
RIN
CIN

=O°C to + 70°C, (Voo -

Vss)

=10V unless otherwise specified
Min.

Typ.

Max.

Units

Positive Supply (Ref. to VSS )
@10V
Power DiSSipation
@13.5V

9.0

13.5

60
135

110
225

mW
mW

Input Resistance (Pins 1-4,8,12,13,16-18)

Parameter/Conditions

Input Capacitance (Pins 1-4,8,12,13,16-18)

General Analog Signal Parameters: (Voo - Vss) = 10V, TA = ooe to
Symbol

Parameter/Conditions

15.0

Units

+ 70 oe, fclock = 3.58MHz
Min.

Typ.

Max.

-0.5

0.5

Pass Band Gain at 0.6 fc

Va
VFS

Reference Level Point (OdBmO)

Load Resistance FLT OUT, Pin 9

RL
VaUT
THO

Load Resistance BUFF OUT, Pin 7

600

Output Signal Level into RL for FLT OUT, BUFF OUT, VIN = 2.1 V
Total Harmonic Distortion at .3fc

2.0

WBN

Wideband Noise (to 30kHz) fc = 3.2kHz

.15

mVRMS

WBN

Wideband Noise (to 80kHz) fc = 15kHz

.13

mvRMS

Maximum Input Signal Level (+ 3dBmO)

1.5

VRMS

2.1

VRMS
kQ
ohms

2.1

VRMS

ICN

Idle Channel Noise fc = 3200Hz

dBrnCO

Vas
VaFS

Buffer Output (Pin 7) Offset Voltage

±10

±30

Filter Output (Pin 9) Offset Voltage

±80

± 200

4.157

I
- .

83528
Filter Performance Specifications
Low Pass Filter Characteristics:fclock 3.58MHz, (Voo - Vss) 10V, TA
Symbol
Parameter/Conditions
Pass Band Ripple (Ref. 0.6 fc)
Filter Response(1): Fe = 3200Hz (Pin 9)
(fc) 3200Hz
(See Figure 5)
(1.06fc) 3372Hz
(1.27fc) 4060
(1.3fc)4155
(1.32fc) 4235
(1.62fc) 5175
(1.3fc Upward)
4155 to 100,000Hz
Dynamic Range (V FS to ICN)
DR

=O°C to

+ 70°C
Typ.

-0.5
-5.5

±0.1
-3.0
-42
-51
-65
-75
<-51
82

0.5
-0.5

dB
dB
dB
dB
dB
dB
dB
dB

-48
-48
-48

= - 5V, TA =O°C to + 70°C unless otherwise specified

Digital Electrical Parameters: Voo = + 5V, Vss
Symbol
Parameter/Conditions
VIH
Input High Voltage
VIL
Input Low Voltage
Input Leakage Current (VIN = 0 to 4VDC)
IN
Input Capacitance
GIN

Min.
2.0

Typ.

Voo
0.8
10
15

Vss

Digital Timing Characteristics
Chip Enable Pulse Width
teE
Address Setup Time
tAS
Address Hold Time
tAH
Crystal Oscillator Frequency(2)
fose
Settling
Time from CE to Stable fe (fe = 3200)(3)
tSET
1.) Filter Response Referenced to f = 1,920Hz
2.) The tables are based on common TV crystal. See paragraph on "Clock Frequencies" for more detail.
Pin Function Description
Pin Name
Number

200

3.)

Max.

300
300
20
3.58
6

Units
Volts
Volts
/-IADC
pF
nsec
nsec
nsec
MHz
msec

_ 10,000 + 3msec

tSET -

- fc

Function

+ 5V

Voo

Positive supply voltage pin. Normally

VSS

Negative supply voltage pin. Normally - 5V ± 10%.

AGND

Analog ground reference point for analog input and output signals. Normally connected to ground.

DGNO
Do
D1
D2
D3
D4
D5

Digital ground reference point for digital input signals. Normally connected to ground.

Control word Inputs: The set of six bits allows selection of one of sixty-four cutoff frequencies. The 6 bit control word is latched on the rising edge of CEo The high-impedance inputs may be bridged directly across a
microprocessor data bus. These inputs are TTL or CMOS compatible. A "1" is 2.0V to Voo , and a "0" is
0.8V to Vss.

17
16
4

± 10%.

Chip Enable: This pin has 3 states. When IT is at Voo the data in the latch is presented to the ROM and the inputs have no effect. When CE is at ground the data presented on the inputs is read into the latch but the
previous data is still in the ROM. Returning CE to Voo presents the new data to the ROM and fe changes. When
IT is '!!.Yss the inputs go directly to the ROM, changing fe immediately. This is the configuration for a fixed
filter; CE is at Vss and the Do through D5 are tied to Voo or Vss/DGRNO depending on the desired fe.

4.158

S3528
Pin Function Description (continued)
Pin Name

ascI
OS Co
SIG IN

Number

Function

13
14

Oscillator In and Oscillator Out: Placing a crystal and a 10MQ resistor across these pins creates the time
base oscillator. An inexpensive choice is to use the 3.58MHz TV colorburst crystal.

Signal Input: This is the inverting input of the input op amp. The non-inverting input is internally connected
to Analog Ground.
Feedback: This is the feedback point for the input op amp. The feedback resistor should be ~1 OkQ for
proper operation.
Filter Out: This is the high impedance output of the programmable low pass filter. Loads must be ~1 OkQ.

FLT OUT

9
8
7

BUFF IN
BUFF OUT

Buffer Input: The inverting input of the buffer amplifier.
Buffer Out: The buffer amplifier output to drive low impedance loads. This pin may drive as low as 600Q
loads.

Figure 2. Microprocessor Interface

Example of Circuit Connection for 53528
Figure 1. Stand Alone Operation
+5V

~
VDD

OSCI

+5V

13
3
00
2
0,
1
02
18
03
17
16 0,

10MQ
OSCD
S3528
OUTPUT AMPLIFIER RESISTORS

-V fc(KHz)

-5V--------''-!

10KQ " R

OCSI 13

c::J

10MQ

OSCD 14
S3528

(KQ)

AUDIO IN

ANTJ.ALlASING
ALTER

..._-.I>Y-'"--------"+-i

ANTJ.ALlASING
FILTER

15
AUDIO OUT

SMOOTHING
FILTER

AUDIO OUT
SMOOTHING
FILTER

-5V
-5V

Operation
S3528 Filter is a CMOS Switched Capacitor Filter
device designed to provide a very accurate, very flat,
programmable filter that can be used in fixed applications where only one cutoff frequency is used, or in
dynamic applications where logic or a microprocessor
can select anyone of 64 different cutoff frequencies. It
is normally clocked by an inexpensive TV color burst
crystal and provides the cutoff frequencies seen in
Table 1 when the Data Bus pins are programmed.
4.159

All that is required for fixed operation is a 10MQ
resistor, the 3.58MHz TV crystal, and some resistors
and capaCitors around the input and output amplifiers
to set the gain, anti-aliasing, and smoothing. The Data
Bus pins are programmed from the table to either a "1"
( + 5V) or a "0" (ground or - 5V) for the desired cutoff
frequency. The CE pin is tied low, to Vss.

•

S3528
Operation (continued)
The ROM is addressed by the contents of the latch and
presents an 11-bit word to the programmable divider
which divides fCLK .
The FILTER OUT pin is capable of driving a 10kQ load
directly or, for smoothing and driving a 600Q load, the
output buffer amplifier can be used for impedance
matching.
As illustrated in the curves of Figures 3, and 5 through
7, the passband ripple (for fc<18kHz) is less than
±0.1dB and the stop band rejection is better than
50dB, as measured on a network analyzer.

For microprocessor controlled operation, the Data Bus
can be bridged across a regularTTL bus and when ~ is
strobed, the data present will be latched in and the filter
will settle down to its new cutoff frequency. In CMOS
systems, the Data Bus and CE can be swung rail-to-rail.
AGND and DGND must be at 1/2 the supply voltage.
The following table illustrates the available cutoff frequencies based on using a 3.58MHz TV crystal for a
time base, by approximately 100Hz steps through the
voice band from 100Hz to 3900Hz. Note that the hex input code for each frequency in the voice band is onehundredth of the cutoff frequency. For 3200Hz, the hex
code is 32, for 900Hz it is 09. Additional frequencies are
listed with their codes on the right side of the Table 1.0.

Table 1.0-Standard Frequency Table: Programmable Filter S3528. fCLOCK

= 3.58MHz

Voice Band

Additional Points Available

fe
Actual
(Hz)

Input Code
(HEX)

05-0 0

Divider
Ratio

00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
36
37
39

2048
895
447
298
224
179
149
128
112
99
89
81
74
69
64
60
56
53
50
47
45
43
41
39
37
36
34
33
32
31
30
29
28
27
26
25
24
23

44
100
200
300
399
500
601
699
799
904
1005
1105
1209
1297
1398
1491
1598
1688
1790
1904
1989
2081
2183
2295
2418
2486
2632
2711
2797
2887
2983
3086
3196
3314
3442
3579
3728
3891

Input Code
(HEX)

fcutoff

4.160

05 -0 0

Divider
RatiO

fe
Actual
(Hz)

OA
OB
OC
00
OE
OF
1A
1B
1C
10
1E
1F
2A
2B
2C
20
2E
2F
35
38
3A
3B
3C
30
3E
3F

188
358
90
87
85
78
61
58
52
46
44
40
38
35
22
20
18
16
15
14
12
10
9
6
5
4

476
250
994
1028
1053
1147
1467
1542
1721
1945
2034
2237
2350
2557
4067
4474
4971
5593
5965
6392
7457
8949
9943
14915
17897
22372

fCLOCK
40 (Divider Ratio)

S3528

Figure 6. Passband Control Detail,
Control
110010, fe
3200Hz

Figure 3. Family off Loss Curves for
4 Different Control Codes

0.40

0.30

0.20

;;;
:l!!.

0.10

-0.10

I--~~--~~~-

--~--~~~--~-

-0.20

-50~~~~~~-L-L~10~~0-0~~-L1-50LOO~~~~20000

-0.30

FREQUENCY (Hz]

--0.40

~--'--L-'--'---'----'----'-_.L.J.

900

~-,---,----,--L-'--L-~"---'

1800
FREQUENCY (Hz]

Figure 4. Address and Chip Enable Timing

Figure 7. Family of Loss Curves for
4 Different Control Codes

Figure 5. Loss Curve, Control

= 110010, fe = 3200Hz

65
75
55
65

;;;

:l!!.

25
35
15
25

FREQUENCY (Hzl
-5~~-L~~~~~-L~~~~~~-L~

5000

10000

15000

20000

FREQUENCY (Hz]

4.161

2700

3600

•

83528
Figure 9. Group Delay, Control = 110010, FC = 3.2kHz

Figure 8. Loss and Group Delay, Fe= 3200Hz

GOfe = x == GOle = 3.2kHz
75
2000
65
1800

1600

1400

~1400

fdrg1200

ill

!:i1200

:!!.

!:i:IE

~1000

\X kHz)

2000

1800

( 3.2kHz \

800

~ 1000

600

600
600

15
400

400
200./.~-----~~·--

200
0
0

2000

4000
FREQUENCY (Hz(

6000

-5
8000

1800
FREQUENCY (Hz)

Applications Information
Many filter applications can benefit from the 83528,
particularly if extremely flat passband response with
precise, repeatable cutoff frequencies are required. Or,
if the same performance is required at different fre·
quencies it can be switched or microprocessor control·
led. The circuits (Figures 1 and 2) illustrate how the
83528 might be connected for two different uses. The
"stand alone" drawing (Figure 1) shows how it would be
programmed as a fixed, 3200Hz low pass filter. The
other drawing (Figure 2) shows a microprocessor driven
application that lets the cutoff frequency be varied on
command.
80me fields that can use such a filter are speech analy·
sis and scrambling, geo·physical instrumentation,
under water accoustical instrumentation, two·way
radio, telecommunications, electronic music, remotely
programmable test equipment, tracking filter, etc.
Anti-Aliasing

In planning an application the basic fundamentals of
sampling devices must be considered. For example,
aliasing must be taken into consideration. If a fre·
quency close to the sampling frequency is presented to
the input it can be aliased or folded back into the pass·
4.162

2700

3600

band. Because the 83528 has an input cosine filter the
effective sample frequency is twice the filter clock frequency of 40 times the cutoff frequency. If fc = 1000Hz
and a signal of 79,200Hz is put into the filter, it will alias
the 80kHz effective sampling frequency of the input
cosine filter and appear as an 800Hz signal at the output. This means that for some applications the input op
amp must be used to construct a simple one or two
pole RC anti-aliasing filter to insure performance. In
many situations, however, this will not be necessary
since the input Signal will already be band-limited.
Smoothing

In addition, all sampling devices will have aliased components near the clock frequency in the output. For example, there will be small components at fclk ± fin in
the output waveform. This can be reduced by constructing a simple smoothing filter around the output buffer
amplifier. Because of the sinxlx characteristics of a
sample and hold stage the aliasing components are
already better than 30dB down. The clock feed through
is approximately - 50dBV. This means that a simple
one pole filter can provide another 20dB of rejection to
keep the aliasing below 50dB down. In the case of a
3kHz fCUToFF and the smoothing filter designed for a
3dB point at 4fCUTOFF the smoothing filter will affect

83528
5moothing (continued)
Figure 11. Cascaded 53528 and 53529 Control =
100001
Bandpass Configuration-1 0 % Bandwidth

the 3kHz pOint by .25dB. If this is not desirable then the
smoothing filter might be constructed as a second
order fi Iter.
For a fixed application, anti-aliasing and smoothing are
straight forward. For a dynamic operation, the desired
operating range of frequencies must be considered
carefully. It may be necessary to switch in or out additional components in the RC filters to move cutoff frequencies. The S3528 has a ratio of cutoff frequencies of
550:1 and to use the full range would require some
switching.
Notch Rejection

The filter is designed to have 51dB of rejection at
1.3fc UTOFF and greater. If greater rejection of a specific
tone or signal frequency is desired, the cutoff frequency can be selected to position the undesired tone at
1.325fcUTOFF or 1.62fcUTOFF' This will place it in a notch
as illustrated in Figure 5.
The S3529 (High Pass Filter) and the 83528 (Low Pass
Filter) can be used together to make either Band Pass
or Band Reject/Notch filters. The control code selection determines the bandwidth of the resulting filter.

1500

3000

4500

6000

FREQUENCY (HZ]

It should be noted that with the 83528 and 83529 data
pins connected in parallel and their analog inputs and
outputs in series a bandpass filter of approximately
10% bandwidth is created.

Figure 12. 53528 and 53529 in Parallel
Notch Configuration-Wide Bandwidth

Figure 10. 53528 and 53529 in Parallel
Notch Configuration-Narrow Bandwidth
75

-5~~-+-+~

1500

__+-~-+-+~__+-~~~~
3000

4500

6000

1500

FREQUENCY (HZ]

3000

FREQUENCY (HZ]

4.163

4500

6000

S3528

Figure 13. Bandpass Application: General Case Configuration

sm IN
nUT

Note:
- Anti·aliasing and smoothing filters on both chips A1, A2,
81, S2

• For same digital logic code
N = multiple of clock#1 to clock#2
fel = .9 f cu

- Lowpass after highpass to remove higher harmonics,
unless cosine input filter of lowpass needed to clean noisy in·
put signal

':
jl
, ,

:
, I
, ,
, ,
, ,
,

- For wider band width two different oscillators can be used.

- Hfilter clock (fcIOCk) for lowpass is an integer multiple of
the fclock for highpass, then 81 and A2 may be removed
without causing beat frequencies.

:, ::

lel lev

Figure 14. Notch Applications: General Case Configuration

SIGIN

4.164

53528
Figure 15. Low Distortion Digitally Tuned Audio Oscillator Application Circuit
10MQ R3

C1
0.1

OSCILLATOR OUT

t---t--"---o "-'1VP·P
ZL~10K

lose

IN914

R1
R2
D1. D2
c" C2
X1

=0.6BlcUTOFF

50KQ .25W 5%
10KQ .25W 5%
IN914
0.11iF CERAMIC
3.579545MHz COLORBURST CRYSTAL

¥
liP BUS OR SWITCHES

Crystal Oscillator

The 83528 crystal oscillator circuit requires a 10 Meg
ohm resistor in parallel with a standard 3.58MHz television colorburst crystal. For this application, however,
crystals with relaxed tolerances can be used.
Specifications can be as follows:
Frequency
R8~180Q

CL = 18pF

3.579545 ± .02%
LM "'96MH
Ch = 7pF

In addition to crystals or external clocks the 83528 can
be used with ceramic resonators such as the Murata
CSA series "Ceralock" devices. All that is required is
the resonator and 2 capacitors to Vss. Although the
resonators are not quite as accurate as crystals they
can be less expensive.

Figure 16. 83528 Driving Additional 83528 or
83529 Devices

Alternate Clock Configurations

If 3.58MHz is already available in the system it can be
applied directly as a logic level to the 08C'N (pin 13).
[Max. zero"'30% (Voo-Vss), min. one",70% (Voo-Vss)).
Waveforms not satisfying these logic levels can be
capacitively coupled to 08C'N as long as the 10 Meg
ohm feedback resistor is installed as shown in Figure
16.
Although the tables are constructed around the TV
colorburst crystal, other clock frequencies can be used
from crystals or external clocks to achieve any cutoff
frequency in the operating range. For example, by using a rate multiplier and duty-cycle restorer circuit between the system clock and the S3528, and switching
the inputs to the S3528, almost any cutoff frequency
between 40Hz and 35kHz can be selected. The clock
input frequency can be anywhere between 500kHz and
5MHz.
4.165

OSCIN

S3528
OSCOUT

10M~1

3. 58 0
MHZy

OSCIN
S3528
OR
S3529
OSCOUT

To
NE XT
DEVICE
OSCOUT

AND

OSCIN

AIMII.---------~

A Subsidiary
of Gould Inc.

Advanced Product Description

S3529

PROGRAMMABLE HIGHPASS FILTER

Features
o Cutoff Frequency Selectable in 64 Steps Via Six-Bit
Control Word
o Cutoff Frequency (fd Range of 10Hz to 20kHz,
40Hz to 20kHz Via 3.58M Hz TV Crystal
o Seventh Order Elliptical Filter
o Passband Ripple: O.1dB
o Stopband Attenuation: 51dB for f<.77 fc
o Clock Tunable Cutoff Frequency Continuously
Variable Via External Clock (Crystal, Resonator, or
TTUCMOS Clock)
o Uncommitted Input and Output Op Amps for AntiAliasing and Smoothing Functions
o Low Power CMOS Technology

Typical Applications for the S3528 and S3529
Programmable Filters
Telecommunications

o
o

PBX & Trunk Line Status Monitoring
Automatic Answering/Forwarding/Billing Systems
o Adaptive Filtering
Remote Control
o Alarm Systems
o Heating Systems
o Acoustic CO:1trollers
Test Equipment/Instrumentation
o Spectrum Analyzers
o Computer Controlled Analog Circuit Testers
o Medical Telemetry Filtering
o ECG Signal Filtering
o Automotive Command Selection and Filtering
Pin Configuration

Block Diagram
+5V

VOD

SIGIN

FLTOUT

03
04

OSC o

Vss

OSCi

BUFoUT

OGND

BUFIN

SIGIN

Voo

AGND

FlTOUT

BUFiN

BUFouT

4.166

83529
General Description

The S3529's eMOS design using switched-capacitor
techniques allows easy programming of the filter's cutoff frequency (fc) in 64 steps via a six-bit control word.
For dynamic control of cutoff frequencies, the S3529
can operate as a peripheral to a microprocessor system
with the code for the cutoff frequency being latched in

from the data bus. When used with the companion low
pass filter, the S3528, a bandpass filter with a variable
center frequency is obtained. For special applications
the S3529's internal ROM can be customized to accomodate a specific set of cutoff frequencies from a
choice of 2,048 possiblities.

Absolute Maximum Ratings
Supply Voltage (Voo - Vss) .................................................................................................................................. + 15.0V
Operating Temperature ............................................................................................................................. ooe to + 70 0 e
Storage Temperature ......................................................................................................................... - 65°e to + 150 0 e
Input Voltage, All Pins ................................................................................................................Vss -O.3V~VIN~ + 0.3V
D.C. Electrical Operating Characteristics: TA = ooe to + 70 oe, (Voo - Vss) = 10V unless otherwise specified
Symbol
Voo
Po
RIN
CIN

Parameter/Conditions

Min.

Positive Supply (Ref. to VSS )
@10V
Power Dissipation
@13.5V

9.0

Input Resistance (Pins 1-4, 7, 12, 14, 16-18)

Typ.

Max.

13.5

60
135

110
225

mW
mW
MQ

Input Capacitance (Pins 1-4,7,12,14,16-18)

Digital Electrical Parameters: Voo
Symbol

15.0

= + 5V, Vss = - 5V, TA =ooe to

Parameter/Conditions

Units

+ 70 e unless otherwise specified
0

Min.

Typ.

Max.

Units

Voo
0.8

Input Leakage Current (VIN = 0 to 4VDC)

J.tADC

Input Capacitance

Max.

Units

VIH
VIL

Input High Voltage

2.0

Input Low Voltage

Vss

IN
CIN

Digital Timing Characteristics
Symbol

Parameter/Conditions

Min.

Typ.

200

300

ns
ns

teE

Chip Enable Pulse Width

tAS

Address Setup Time

300

tAH

Address Hold Time

fosc

Crystal Oscillator Frequency(1)

3.58

MHz

tSET

Settling Time From CE to Stable fc(fc = 3200)(2)

Notes:
1. The tables are based on the common 3.58MHz color burst TV crystal.
2. t
10,000 + 3msec
SET =

---rc-

4.167

I·:
- -

83529
General Analog Signal Parameters: (Voo - Vss)
Symbol

=10V, TA =O°C to

+ 70°C, fosc =3.58MHz

Parameter/Conditions

Min.

Typ.

Max.

Units

- 0.5

0.5

Pass Band Gain at 2.2 fc

VMAX
VFS

Reference Level Point (OdBmO)

1.5

VRMS

Ma>simum Input Signal Level ( + 3dBmO)

2.1

VRMS

Load Resistance (FLTOUT, Pin 9)

RL
VOUT

Load Resistance (BU FOUT' Pin 7)

600

Output Signal Level into RL for FLTOUT, BU FOUT

2.0

kQ
Q
2.1

VRMS

.15

THO

Total Harmonic Distortion: Input code 22, Frequency = 2kHz;
Bandlimited to fClk/2

WBN

Wideband Noise: Input code 22, Bandlimited to 15kHz

.25

mVRMS

Vos
VOES

Buffer Output (Pin 7) Offset Voltage

±10

Filter Output (Pin 9) Offset Voltage

±80

Filter Performance Specifications: High Pass Filter Characteristics (fosc
TA

Symbol

= O°C to + 70°C

=3.58MHz) (Voo -

Vss)

=10V,

Parameter/Conditions

Min.

Typ.

Max.

Units

fc~f<7fc

-0.5

±0.05

0.5

-0.5

±0.1

0.5

-5

-3.0

-1

Passband ripple (Ref. 2.2 fc)
Filter Response: fc = 1005Hz

(tc)

Stopband
DR

1005Hz

(0.96 fc)

960

(0.768fc)

772

-53

-43

(.754 tc)

758

-85

-43

(.614fcl

617

-70

-43

t<.768fc

Dynamic Range (VFS to WBN)

<-53

Pin Description
Pin Name

Voo
Vss
AGNO
DGNO
Do
D1
D2
D3
D4
D5

Pin#

Function

8
5
11
13
3
2
1
18
17
16

Positive supply voltage pin. Normally + 5 volts.
Negative supply voltage pin. Normally - 5 volts.
Analog ground reference pOint for analog input signals. Normally connected to ground.
Digital ground reference point for digital input signals. Normally connected to ground.
The input bus to allow selection of the desired cutoff frequency. The value of the word presented to these pins
selects the cutoff frequency. It is latched in on the rising edge of CEo These are high impedance CMOS inputs
and can be bridged directly across a microprocessor data bus.

4.168

83529
Pin Description (Continued)

Pin Name

Pin#

aSCi
OSC o
SIG 1N

14
15
12

FLToUT
BUF1N
BUFoUT

7
6

Function
Chip Enable: This pin has 3 states. When CE is at VDD the data in the latch is presented to the ROM and the inputs have no effect. When CE is at ground the data presented on the inputs is read into the latch but the
previous data is still in the ROM. Returning CE to VDD presents the new data to the ROM and fcutoff changes.
When CE is at Vss the inputs go directly to the ROM, changing fcutoff immediately. The configuration for a fixed
filter is: CE at Vss and the Do through 05 are tied to VDD or VSS/OGND depending on the desired fcutoff.
Oscillator In and Oscillator Out. Placing a crystal and a 10MQ resistor across these pins creates the time base •
oscillator. An inexpensive choice is to use the 3.58MHz TV crystal.
Signal Input. This is the inverting input of the input op amp. The non-inverting input is internally connected to
Analog Ground.
- Feedback. This is the feedback point for the input op amp. The feedback resistor should be ~ 10kQ for proper
operation.
The high impedance output of the high pass filter. Load should be 1OKQ.
The inverting input of the buffer amplifier.
The buffer amplifier output to drive low impedance loads. Load should be ~600Q.

Example of Circuit Connection for 53529
Figure 2. Microprocessor Interface

Figure 1. Stand Alone Operation

4.169

83529
Table 1. Standard Frequency Table: Programmable Filter S3529, fclock = 3.58MHz
Voice Band
Input
°5. 00
(HEX)

00
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
36
37
39

Divider
Ratio

Ie
Actual

2048
895
447
298
224
179
149
128
112
99
89
81
74
69
64
60
56
53
50
47
45
43
41
39
37
36
34
33
32
31
30
29
28
27
26
25
24
23

40
91
182
273
363
455
546
635
726
822
914
1005
1099
1179
1271
1355
1453
1535
1627
1731
1808
1892
1985
2086
2198
2260
2392
2465
2543
2625
2712
2805
2905
3013
3129
3254
3389
3537

Additional Points
Input Code
°5. 00
(HEX)

(Hz)

Divider
Ratio

OA
OB
OC
OD
OE
OF
1A
1B
1C
1D
1E
1F
2A
28
2C
2D
2E
2F
35
38
3A
38
3C
3D
3E
3F

f
CUTOFF

188
358
90
87
85
78
61
58
52
46
44
40
38
35
22
20
18
16
15
14
12
10
9
6
5
4

Ie
Actual
(Hz)

433
227
904
935
957
1043
1334
1402
1565
1768
1849
2034
2136
2325
3697
4067
4519
5085
5423
5811
6779
8135
9039
13559
16270
20338

= fclock
44 (Divider Ratio)

Alternate Clock Configurations
If 3.58MHz is already available in the system it can be
applied directly as a logic level to the OSCIN (pin 14).
(Max. zerol'\J30% VDD , min. onel'\J70% Vss). Waveforms
not satisfying these logic levels can be capacitively
coupled to OSC 1N as long as the 10MQ feedback
resistor is installed as shown in Figure 3.

Figure 3. External Driving S3529 Pin OSCi

OSCo~
10MQ

83529
OSCi

t-1_4-+-~: ~ TTL CLOCK

'----......

4.170

15PF

53529
Figure 4. Passband Detail, Control
fe = 1005Hz

Figure 5. Loss Curve, Control = 110010,
fe = 1005Hz

110010,

)5~

0.40

o.ao

0.20

0.10

0.00

-0.10

-0.20

-0.30

-0.40
0

2000

4000

6000

8000

FREQUENCY (Hz)

Figure 7. Cascaded 83528 And 83529 Control = 100001
Bandpass Configuration-1 0 % Bandwidth

Figure 6. Loss Response, DC to Clock Detail,
Control = 110010, fe = 1005Hz

8800

17600

26400

35200

1500

44000

3000

FREQUENCY [HZ)

FREQUENCY (Hz)

4.171

4500

6000

83529
Figure 9. S3528 and S3529 In Parallel
Notch Configuration-Wide Bandwidth

Figure 8. 83528 and 83529 In Parallel
Notch Configuration-Narrow Bandwidth

;

-5

-5
0

3000

1500

4500

FR£llUBlty (lIZ!

1500

3000

4500

&000

FREQUENCY (HZJ

Applications Information
The 53529 (High Pass Filter) has a very sharp 50dB drop off at fc. The Passband Ripple is less than O.5dB. Note that
unlike passive element filters, attenuation increases for sampled-data filters at the higher frequencies due to the
sample and hold effect. (fcLOCK = 44xfcUTOFF)·
The 53529 (High Pass Filter) and the 83528 (Low Pass Filter) can be used together to make either Band Pass or
Band Reject filters. The control code selection determines the bandwidth of the resulting filter.

4.172

83529

Figure 10. Bandpass Application: General Case Configuration

SIGIN
OUT

Note:
- Anti·aliasing and smoothing filters on both chips A1, A2,
81,82

• For same digital logic code
N = multiple of c~ock#1 to clock#2

- Lowpass after high pass to remove higher harmonics,
unless cosine input filter of lowpass needed to clean noisy in·
put signal

fel = .gfcu
N

- For wider band width two different oscillators can be used.
- If filter clock (fclock) for lowpass is an integer multiple of
the fclock for highpass, then 81 and A2 may be removed
without causing beat frequencies.

Figure 11. Notch Applications: General Case Configuration

SIGIN

4.173

•

83529
Applications Information

Figure 12. Sampling Theory

Anti-Aliasing

OVERSAMPLED

fs
sampling frequency
fm = frequency bandwidth of message

f.>2fm

-f.

-fm

In planning an application the fundamentals of sampling devices must be considered.

CRITICALL Y SAMPLED

o Make certain the harmonic image does not fold into
the desired pass band. i.e, Oversample.

f. = 2fm

2~ EFl~EBa'MO
~m
-2f.

-f.

-fm

2f.

o Bandlimit the input so that the input frequencies,
noise, and tails will not come too close to the clock and
be folded back into the pass band.

--'-r:==-ct=J_+-.L.~UN,--DE+R~_AMJ...5-:TI_ED'--I--'---'--tV(f)---'~......L.a_OMI-0
_.L..:~:~m

o Bandlimit the output so that the image is sufficiently attenuated and the switched capacitor output is
smoothed. i.e., kill the higher order terms in the Fourier
Series.

--'-..La_'MI-0--'-..La_'M+-D

-3f.

-2f.

- f. - fm

2f.

3f.

o For dynamic operation check for aliasing at each
cutoff frequency.

Figure 13. Avoiding Aliasing

_00_
en
I

-8

-fs
I

- 28

f.=28

f
fO=O.58

- 28 - 8

-fs~ I ~fs
~I~ UWWIlm

fs=38

- 48 - 38 - 28 - 8

Note that critical sampling avoids aliasing, but in the above example no real life filter
can separate the message from the image. One must oversample in real life.

Figure 14. Implementation
iRCFllTERSMOOTHSSlGlrfALOUTPUT

•

.//6ro~:~::~
-8

GAP~PLlNG

1
ICLOCK

•
4.174

AIMII@---------r

."""-

A Subsidiary
of Gould Inc.

53530

BELL 103/V.21
SINGLE CHIP MODEM

Features
D Single-Chip 300 bps, Full Duplex, Asynchronous
FSK Modem
D Bell 103/113 & CCID V.21 Operation (Selectable)
D Auto Answer/Originate Operating Modes
D Manual Mode
D No External Filtering Required
D Phase Continuous Transmit Carrier Frequency
Switching
D RS-232 Control Interface
D Passthru Mode for Protocol Independence
D Low Cost 3.58MHz (TV Crystal) Time Base
D Digital & Analog Loopback Modes
D UART Clock Output (4.8KHz)
D V.25 Tone Generation

General Description
The S3530 is a Monolithic CMOS Single-Chip Full
Duplex FSK Modem integrated circuit which may be
operated in Bell 103/113 or CCID V.21 applications.
The S3530 features on-Chip transmit and receive filtering; answer/originate mode selection; RS-232 control
interface; digital and analog loopback test modes; and
generation of both the 4.8KHz UART clock and V.25
Answer Tone. The S3530 is designed for use in standalone modem applications and in applications in
which the modem function is designed directly into
the DTE.

Block Diagram

Pin Configuration

TO~~ ~_~~_.~~------~ FI_~_ER~
__

r;:======;---;==:::::c==~~NC

ClK

VDD

OTR

TEST1

CTS

TESTo

7 83530 22

8 MODEM 21

COT

iiSii
ffi

2 TP

RTS

iiH

TIMING

OTR

CONTROL
BLOCK

TESTO

TESTl

L - -_ _ _ _ _~

'--------~

j"
Vss

RTS

OSCI

OGNO

OSCo

COT

OSR

Vss

eLK

Voo

AGNO

OGNO

4.175

OSCo
OSCI

•

53530
Absolute Maximum Ratings
Supply Voltage (Voo-Vss) ................................................................. + 12.0V
Operating Temperature ............................................................. O°C to + 70°C
Storage Temperature ............................... :.......................... - 65°C to + 150°C
Input Voltage, All Pins .................................................. Vss - O.3V~VIN~VOO + O.3V
D.C. Electrical Operating Characteristics: TA = O°C to + 70°C; (Voo-Vss) = 10V; (± 5.0V)
Symbol Parameter/Conditions
Min.
Typ.
VDD
Positive Supply Voltage (ref. to DGNO and AGNO, both
+4.75
+5.0
at 0 Volts)
Negative Supply Voltage (ref. to DGND, AGND)
-4.75
-5.0
Vss
PD
Power Dissipation, Operating (@ ± 5V)
110
Input Resistance
8
RIN
CIN
Input Capacitance
Analog Signal Parameters: TA = O°C to 70°C; ± 5 VDC. fosc = 3.58MHz
Symbol Parameter/Conditions
Min.
Oscillator Frequency
fosc
Transmit Frequency Tolerance
ft
Transmit 2nd Harmonic Attenuation with respect to
to
Carrier Level
Transmit Output Level into 10KQ min., 25pF max.
TOUT
Carrier Input Range (COT open)
-48
DNR
Dynamic Range (COT open)
Bit Jitter (Input = - 30 dBm)
Bit Bias
Bias Distortion
Signal Input and Output Compatibility Table
Pin
Name
No.
Input
Output
SH
18
X
RI
19
X
TESTo
7
X
TEST1
6
X
24
OH
X
CLK
28
X
err
21
X
22
RD
X
23
X
14
DSR
X
RTS
20
X
TO
27
X
OTR
25
X
AL
26
X
DL
1
X
SL
11
X

Typ

Unit
VOC

-5.25

VDC
mW
MQ
pF

Max.

3.579545 ± 0.02"10
±1.2
50

Voltage Level
Low
High
-3
+3
-3
+3
-3
+3
-3
+3
+0.4
+2.4
+0.4
+2.4
+0.4
+2.4
+0.4
+2.4
+0.4
+2.4
+0.4
+2.4
+0.8
+2.0
+2.0
+0.8
+0.8
+2.0
+0.8
+2.0
+2.0
+0.8
+0.8
+2.0
4.176

Max.
+5.25

-9
0
48
100
1
3

Unit
MHz
Hz
dB
dBm
dBm
dB
J.lSec

"10
"10

Logic
Family
CMOS
CMOS
CMOS
CMOS
LSTTL
LSTTL
LSTTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

IOL
Milliamps

0.4
0.4
0.4
1.6
1.6
1.6

83530
Pin/Function Descriptions
Pin #

Name
DTR
(Data Terminal Ready)

RTS
(Request to Send)

23
(Clear to Send)

21
(Carrier Detect)

(Transmit Data)

A high level on this input with the DTR input in the on condition causes the device to enter
the originate mode. OH will go low to seize the phone line. Auto dialing can be performed
by turning the RTS input on and off to effect dial pulsing. This input must remain high for
the duration of data transmission. (Auto answer will not function if RTS is high)
This output goes to a low level at the completion of the handshaking sequence and turns
off when the modem disconnects. It is always turned off if the device is in the digital loopback mode. Data to be transmitted should not be applied at the TO input until this output
turns on.
This output goes to a low level to indicate that the receive data carrier has been received
at a level of at least -43dBm. It turns off if the received data carrier falls below the carrier detection threshold of -48dBm. During the off state, the Receive Data is clamped to
the MARK state.
Data bits to be transmitted are presented to this input serially by the data terminal. A high
level is considered a binary' l' or MARK and a low level is considered a binary' 0' or
SPACE. The data terminal should hold this input in the MARK state when data is not being
transmitted. During handshaking this input is ignored.

(Received Data)

The device presents data bits demodulated from the received data carrier at this output.
This output is forced high if the DTR input or the carrier detect output is off.

DSR
Data Set Ready

This output, when low, indicates to the data terminal that the modem is ready to transmit
data.

This input when high permits auto answer capability. The data access arrangement should
apply a low level to AT when a ringing signal is detected. The level should be low for at
least 107msec. The input can remain low until reset by DTR or loss of carrier. Similarly, in
manual mode, the answer mode is entered by applying a low level to this input, unless
RTS is high.

22
14

Function

A high level on this input enables all the other inputs and outputs and must be present
before the device will enter the data mode either manually or automatically. The device will
enter an irreversible disconnect sequence if the input is turned off (low level) for more
than 14 mSec during a data call. A pulse duration of less than 6 mSec will not be
detected.

(Ring Indicator)

This input allows the data terminal to make the telephone line busy (off hook) and implement the analog loopback mode. A high level on this input while DTR is high causes the
device to make the OH output low and to enter the analog loopback mode. The receive
filter center frequency is switched to correspond to the transmit filter center frequency
and the transmit data carrier output is internally connected to the receive data carrier input, as well as being available at TC.

Al
(Analog loopback)

Sl
(Select)

A high level on this input selects the CCITT V.21 data transmission format. Applying a low
level selects the Bell 103 data transmission format.

COT
(Carrier Detect
Threshold)

Applying a variable voltage level between 0 and - 5V at this pin allows control of the receiver carrier detection threshold. This will override the internally determined threshold. If
COT is set to a voltage between + 1.5 and + 2.0V the AGC will be disabled during the
test modes of pins 6 & 7.

ClK
(Clock)

A 4.8KHz lSTTl compatible square wave output is provided for supplying the 16X clock
signal required by a UART for 300 bits/sec. data rate. This output facilitates the integration of the modem function in the data terminal.

4.177

I
_ -

•

83530
Pin/Function Descriptions (Continued)
Pin #

Name

Function

OH
(Off-Hook)

This output goes to a low level when either the SA or the RTS input is on in the originate
mode, and when a valid ring signal is detected on the Ri input in the answer mode. This
output is off if DTR is off or if the disconnect sequence has been completed.

TC
(Transmit Carri,er)

This analog output is the modulated transmit data carrier. Its frequency depends upon
whether the modem is in the answer or originate mode and if a mark or space condition is
being sent (Table 1). Typically, the output level is at -9dBm.

7
6

Test 0
Test 1

These are test inputs and must be tied to Vss for normal applications. See table under
Passthru Mode.

RC
(Receive Carrier)

This analog input is the data carrier received by the data access arrangement from the
line. The modem demodulates this signal to generate the receive data bits.

DGND
(Digital Ground)

Digital ground (0 Volts).

AGND
(Analog Ground)

Analog ground (0 Volts).

8
4,15
18

has
13,12

No connect.

Voo , Vss
SH
(Switch Hook)

been

Positive and negative power pins, respectively (± 5V).
This input is used to manually place the device in the originate mode. The device will
make the OH output low and start the originate sequence if SH input is low and DTR is on.
This can be a level or a momentary low-going pulse input (min. 54 mS). A pulse duration
of less than 27 mS will not be detected. FIT should be high if SF! is to be exercised. Once
RI has been activated then RTS has no effect.

OSC o, OSC I

These are terminals for connecting an external 3.579545MHz TV crystal. All internal clock
signals are derived from this time base. An external clock signal may instead be applied at
the OSC I input. Feedback resistor and capacitors are integrated on the chip but additional
20pF caps to Vss from each pin are required.

DL
(Digital Loopback)

A high level on this input causes the device to enter the digital loopback mode. In this
mode, the received data from the remote end is internally looped back to TO and OSR is
forced high to signal to the DTE that the modem is not ready for transmission. The received data is not available on RO during the DL mode.

TP
(Test POint)

Test Pin. Must be connected to either Vss or Voo for normal operations.

EP
(Eye Pattern)

Output (analog) of the demodulator prior to slicing. Do not load.

Table 1.103/V.21 Mark and Space Frequencies
Transmit Frequency (Hz)
Mode
Bell 103 Originate
Bell 103 Answer
CCITT V.21 Originate
CCITT V. 21 Answer
CCITT V.25 Answer Tone

Receive Frequency (Hz)

Mark

Space

Mark

Space

1270
2225
980
1650

1070
2025
1180
1850

2225
1270
1650
980

2025
1070
1850
1180

2100

4.178

83530
Operation of 53530 Modem Chip

Manual Operation

The 83530 can be operated manually as well as automatically. To put it in the Answer Mode apply a negative
pulse (- 5V) on AT of greater than 107msec. If Ai is tied
low then the device will go into the Answer Mode
whenever DTR is enabled.

Bell 103/113 Mode

In the answer mode the 83530 stands idle waiting for an
incoming call. As long as DTR is true, when a low fro.m
the ring detector is presented to AI the 83530 sets OH
and D8R low which enables the hookswitch relay, connecting the modem to the phone line in the answer
mode. The 83530 waits 2.1 seconds, and then sends
carrier at 2225 Hz (mark) to the originate modem. When
the originate modem returns with 1270 Hz (mark) the
83530 carrier detect circuit turns on within 106 msec
and sets CD and CT8 both low indicating the handshaking sequence is completed. Data can be be sent and
received.
Originate Mode

In the originate mode a call is initiated, if DTR is high,
by applying a high to the RT8 input in auto mode or a
negative pulse or low to 8H in manual mode. This will
cause OH to go low pulling in the hookswitch relay to
connect the telephone line, and putting the 83530 in
the originate mode. After a suitable time, or when dial
tone is detected, RT8 can be pulsed off to provide dial
pulses*. The OH will go on and off, pulsing the line with
the desired digits. When the answering modem comes
on line it will wait 2.1 seconds ("billing delay") and then
send the 2225 Hz answer tone. 106 milliseconds later
the CD pin will go low indicating received carrier. 190
msec later the 83530 will respond with 640 msec of
1270 Hz. At the end of that time CT8 (Clear-to-8end) will
go low indicating to the terminal side that the communications link has been established.
Abort Mode

There is an automatic abort feature in the 83530 to
avoid tying up a system should there be difficulty in
establishing the link. If no carrier is detected within 14
seconds after the device has been put into the answer
or originate mode it will abort the call by turning off OH
and disconnecting the telephone line. D8R will also go
off (high). This abort time can be extended by pulsing
RT8 low for about 1msec before the 14 seconds have
elaps~d. This will reset the abort timer. If it does time
out DTR will need to be pulsed off to reset the 83530.
Shutdown Mode

8hould the received carrier fall below - 48 dBm during
data exchange for more than 213 msec the 83530 will
terminate the call and go on-hook, disconnecting the
telephone line.

8imilarly, to put it in the Originate Mode, 8H can be
pulled low for more than 54msec. By tying 8H low, the
83530 will go into the Originate Mode whenever DTR is
enabled.
Passthru Mode

Through the "Test 0" and "Test 1" lines the 83530 can
be put into the Passthru Mode. In this mode the protocol handshake is disabled, Le., the transmit and
receive functions are enabled but become independent
of timing and control. CD works as usual. The Answer
or Originate modes are selected in the same manner
with 8H or RI.

TEST 0

TEST1

PIN 7

PIN 6

S3530
STATUS

0
1

0
0

NORMAL
PASSTHRU

1 = +5V (VDD )
0= -5V (Vss)

B. V.21 Mode
The 83530 will perform the same operations described
above in the CCITT V.21 mode if the 8L pin is tied high.
The basic principle is the same but the frequencies and
the timings are switched to conform to V.21 specifications. 8ee the timing charts and Table 1 for additional
details. When in V.21 mode the V.25 answer tone of
2100Hz will be generated upon answering.
Diagnostic Modes

The 83530 has two diagnostic modes available to the
operator. By putting the AL pin high while DTR is high,
the device enters the Analog Loopback Mode. OH goes
low to busy out the phone line. The receive filter center
frequency moves to the transmit center frequency and
the TC signal is internally connected to the RC input.
The transmit signal also remains available on the TC
pin. Thus any digital data input at TD is coded and sent
out via TC, and at the same time back through the
analog input, decoded, and out on the RD pin.
By putting the DL pin high the 83530 enters the Digital
Loopback mode. In this mode any data received from
the remote end of the telephone line is retransmitted
back to its source and D8R is forced h..!i!!1. The digital or
decoded data is not available at the RD output in this
mode.
"(Note that OH only follows RTS. The proper timing for dialing
must come from the terminal on the RTS line.)

4.179

•

83530
53530 Modem Timing Chart for 103 Operating Mode

-I

/-70mSeC MINIMUM BEFORE DIALING MAY BEGIN

RECEIVE
DIAL TONE
ORIGINATE

l'"'.o------:~t~~-----.~,

RING" ANSWER

OTR

-.J

RTS

~ ~~

Sii
iiH

I~06",: \-200ms+f---640mS_

~ ~~
r

~~
TC

ANSWER
OTR

RTS

/ 1270Hz (MARK)

DATA

,
I~06m~

!_2.1SeC_
TC

___________

(MARK)
DATA
(~2225Hz~~-JX~

4.180

S3530

S3530 Modem Timing Chart for V.21 Operating Mode

RECEIVE
DIAL TONE
ORIGINATE

OTR

RING" ANSWER

F"''''''''''-

•

RTS

200

1--426ms-~ _640ms _ _

~,
r

~OATA

980Hz

ANS WER

DTR

RTS

iiii

41<-1
r

2100Hz
_2.1sec _

1650Hz

3.4sec::::
..--80ms

4.181

r426ms-

DATA

S3530
Application Circuits

Two applications circuits are illustrated. The first circuit is for a stand-alone RS-232 interface modem to be
used as a peripheral accessory to a terminal or computer. Plugging into an RS-232 serial port on one side
and into a standard modular telephone jack on the
other side it is a stand-alone direct connect modem for
operation at rates up to 300 bps.
The second circuit is an add-on modem for building into a computer and connecting to the internal parallel
buss structure. The ACIA or UART does the parallel-toserial and serial-to-parallel conversion required. The
edge connector is numbered for an Apple II application
but the same interface applies to most lAP systems.
Both circuits are intended for direct connection to the
telephone line. This requires meeting FCC Part 68 requirements for network protection as well as protection
of the modem. No suppression components are illustrated on these examples as the design of the interface
will vary depending on the needs of the designer. After
a design is completed it must be subjected to Part 68
certification before sale to the public.
If one wants to avoid the protection/certification details
then a certified DAA (Data Access Arrangement) such
as the Cermetek CH1810 can be used instead. The DAA
is designed to handle the telephone line interface including the 4 wire to 2 wire function and is already
registered with the FCC.
Whether using a DAA or not, the S3530 requires very
few external components.
Hybrid Functions

In the stand-alone circuit the hybrid 4 wire to 2 wire converter utilizing the dual op amp was configured to provide 1:1 conversion in each direction. A - 9dBm voltage
level from the Transmit Carrier pin on the S3530 is

4.182

amplified by the op amp to compensate for the losses
in the 300Q matching resistor and the coupling transformer. The transmit carrier is delivered to the line at
-9dBm.
In the receive direction the loss in the coupling transformer is compensated for by the other half of the op
amp. If there is a - 20dBm signal across Tip and Ring
then a - 20dBm signal is delivered to the Receive Carrier pin on the S3530.
The 300Q resistor is to provide the proper termination
so that Tip and Ring look like a 600Q AC impedance to
the line. The 16KQ resistor from the Transmit Carrier pin
to the inverting input of the receive op amp is to provide
sidetone suppression. The transmit carrier is provided
through the 16KQ resistor 180 0 out of phase from the
transmit carrier presented to the line. Thus, the transmit carrier is cancelled out and not presented to the
Receive Carrier pin on the S3530. Under ideal conditions 20dB or more of cancellation might be achieved,
but because telephone lines vary conSiderably, a cancellation of around 10dB is a more realistic number. The
20Q resistors in series with Tip and Ring increase the
DC impedance of the modem to the line. This is because the transformer is very close to the 100Q minimum DC impedance specification in the off-hook condition.
NOTE once again, that only minimal transient protection

is illustrated in these examples. This must be added to
meet the needs of the application and the FCC Part 68
requirements.
Also, the transformer listed is rated to 75mA loop current. To go to the maximum loop current the Microtran
number would be T5115 for 120mA loop current capability. The DC resistance may be slightly different and
the various components will need to be adjusted to retain the necessary levels of AC and DC specifications.

C/)
C

CO
CO

[

C/)

~
~

+5,

~Jt

'2.

MODULAR

+5'

Vee

of.-

~1CJKQ

ANAlOGLOOPBACK
~~

PJHADCNKE

('r

£1j.lFI4

26~DO

C/)

::::r

(')'

~
C/)
Co)

!'--

cO
VJ

Co)

IN4004

54.
lW

NOTE: THIS IS NOT FCC PART 68 APPROVED AND WILL REQUIRE MORE
TRANSIENT PROTECTION AND AN FCC CERTIFICATION TEST.

THIS SCHEMATIC IS INTENDED AS A SUGGESTED STARTING
POINT ONLY, AND SHOULD BE ADOPTED TO FIT EACH
PARTICULAR APPLICATION.

en
w
en

..
11~U~•

-~--

fn
C
CC
CC

"tI

I»

i:
S-

I»

CD
~

......

"2-

EdgeCHllltcllr

I»
MODULAR

PHONE
J.CK

g.
~

:::T

-,vf!!.

I»

,10"
DEYEE 41

!HID

0,"

:...

(Xl
~

....

. . .3

....
....
0."

3 CS'
25
087

...

S3530
300BPS
MDOEM

56551

.CIA

24 086
23 ...

Epl

COl 16

Co)

CI'J

Co)

221J8.t

0
I»

2'003

.,47

2°082

0,48

081

'811B1f

ocol"

211 eo

'C
'C

NOTE: THIS IS NOT FCC PART 68 APPROVED AND WILL REQUIRE MORE
TRANSIENT PROTECTION AND AN FCC CERTIFICATION TEST.
THIS SCHEMATIC IS INTENDED AS A SUGGESTED STARTING
POINT ONLY. AND SHOULD BE ADOPTED TO FIT EACH
PARTICULAR APPLICATION.

(,)

en
o

(,)

AMI.---------......

A Subsidiary
of Gould Inc. - - - _ - - - - - - - - - - - - - - - - - - - - - - - -

Consumer Products
Contact factory for complete data sheets

•

Consumer Products Selection Guide
SPEECH PRODUCTS
Part No.

Description

Process

Power Supplies

Packages

S3620

Speech Synthesizer

CMOS

+5V

22 Pin

S36128

131,072 Bit Female Speech
ROM

NMOS

+5V

28 Pin

EVK3620

Speech Synthesis
Evaluation Board

Part No.

Description

Process

Power Supply

Outputs

Packages

S4520

30·Volt Dichroic LCD Driver

CMOS

+ 3V to + 16VI
- 30V to - 5V

30132/38

40 Pin

DRIVERS

S4521

32 Bit Driver

CMOS

+ 3V to + 13V

40 Pin

S4535

32 Bit, High Voltage, Driver

CMOS

+ 5VI + 20- + 60

40 Pin

S4534

10 Bit, High Voltage, High Current Driver

CMOS

+5V-12VI
+ 20 to + 60

18 Pin

S2809

Universal Driver

PMOS

+ 8V to + 22V

40 Pin

Part No.

Description

Process

Power Supply

Commands

Packages

S2600

Remote Control Encoder

CMOS

+ 7V to 10V

16 Pin

S2601

Remote Control Decoder

PMOS

+ 10V to 18V

22 Pin

S2604

Remote Control Encoder

CMOS

+ 9V

16 Pin

S2605

Remote Control Decoder

CMOS

+9V

22 Pin

S2742

Remote Control Decoder

PMOS

+ 15V

512

18 Pin

S2743

Remote Control Encoder

PMOS

+9V

512

16 Pin

S2747

Remote Control Encoder

CMOS

+9V

512

16 Pin

S2748

Remote Control Decoder

CMOS

+ 12V

512

16 Pin

Part No.

Description

S10110

Analog Shift Register

PMOS

8 Pin

S10430

Divider·Keyer

PMOS

40 Pin

S2688

Noise Generator

PMOS

8 Pin

S50240

Top Octave Synthesizer

PMOS

16 Pin

S50241

Top Octave Synthesizer

PMOS

16 Pin

S50242

Top Octave Synthesizer

PMOS

16 Pin

Part No.

Description

Process

Power Supply

Digits

Packages

S4003

Fluorescent Automotive Digital Clock
(12 Hour + Date + Rally Timer)

PMOS

+ 12V

40 Pin

S2709A

Vacuum Fluorescent Digital Clock

PMOS

+ 12V

22 Pin

REMOTE CONTROL CIRCUITS

ORGAN CIRCUITS
Packages

Process

CLOCK CIRCUITS

AID CONVERTER AND DIGITAL SCALE CIRCUIT
Part No.

Description

Process

Power Supply

Digits

Packages

S4036

General Purpose AID Converter and
Digital Scale Circuit

CMOS

+9V

24 Pin

5.2

~l~ll~~~~~~
."'111(.
~

A Subsidiary
of Gould Inc.

83620

LPC-10
SPEECH SYNTHESIZER

Features
D Simple Microprocessor Interface

General Description
The S3620 LPC-10 Speech Synthesizer generates
speech of high quality and intelligibility from LPC
(Linear Predictive Coding) data stored in an external
memory. The digital interface circuitry is fully
microprocessor compatible and allows the processor
to load the data with or without a DMA controller. The •
loading takes place on a handshake basis, and in the
absence of a response from the processor the synthesizer automatically shuts down and goes into the
_ ~
powerdown mode. A busy Signal allows the processor
to sense the status of the synthesizer. The input data

D CMOS Switched-Capacitor Filter Technology
D Automatic Powerdown
D 5-8 Volts Single Power Supply Operation
D Direct Loudspeaker Drive
D 20mW Audio Output
D Low Data Rate
Block Diagram

Pin Configuration

Do
DATA
INPUTS

lAo
BUSY

o---+-..--t--l

STROBE

asc,
osc,
AGNO 0-.------'

Voo

IRQ

OSC o

NIC

lS1

OSCi

lS2
A GNO

Vss
NIC

lS, 0 - - - - - - - - /
lS2 o-------~

5.3

=NO CONNECTION

83620
allow the device to be connected directly to a 100Q
loudspeaker.
The S3620 also features an on-chip oscillator, requiring
only a 640kHz ceramic resonator and a 120pF capacitor
for normal operation.
AMI is able to provide a speech analysis service to generate the LPC parameters from customers' word lists.

rate is 2.0K bits/sec. max., but typically the average data
rate will be reduced to about 1.4K bits/sec. by means of
the data rate reduction techniques used internally.
The synthesizer is realized using analog switchedcapacitor filter technology and operates at 8K samples/
sec. An output interpolating filter and bridge power
amplifier give 20mW output power at 5 volts supply and
Absolute Maximum Ratings·

Supply Voltage ............................................................................................................................................. 11 Volts DC
Operating Temperature Range ................................................................................................................ O°C to + 70°C
Storage Temperature Range ............................................................................................................ - 55°C to + 150°C
Voltage at any Pin ...................................................................................................................... Vss - 0.3 to VDD + 0.3V
Lead Temperature (soldering, 10 sec.) .................................................................................................................. 200°C
Power Dissipation ....................................................................................................................................................... 1W
·COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and func·
tional operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

Electrical Specifications: (VDD = 5.0V ± 10%, Vss = OV, CAG = 0.047!-,F, TA = 0° to 70°C, unless otherwise specified)
D.C. Characteristics
Symbol
VIH
VIL
liN
VOL
Vos
100

IDOL

Min.

Parameter
Input High Logic" 1" Voltage
Input Low Logic "0" Voltage
Input Leakage Current
Output Low Voltage (BU, IRQ)
DC Offset Voltage, Audio Output
Supply Current, Operating
Supply Current, Powerdown

Typ.

2.4
0

Max.

Units

Voo
0.8
10
0.4

V
V
!-,A
V
V
mA
mA

0.5 Voo
35
4

Conditions

VIN = 0 to Voo
IOL = 1.6mA
RLOAO = 100Q

AC Characteristics
mW
Audio Output Power
20
nsec
Data
Set-up
Time
100
tos
nsec
Data Hold Time
10
tOH
Strobe Pulse Width
3.2
100
!-,sec
tws
nsec
1st Strobe to Busy Delay
100
500
tSB
1st Strobe to 1st IRQ Delay
19
msec
tBO
IRQ Repetition Rate
250
!-,sec
tREP
IRQ Pulse Width
3.5
!-,sec
3
two
200
!-,sec
IRQ to Strobe DelaY[See Note 1J
tas
-1%
KHz
Oscillator
Resonator
Frequency
640
+1%
Fosc
Q
RLOAO
Audio Output Load Impedance
100
pF
Input Capacitance, Oscillator
100
CINOSC
pF
CIN
Input Capacitance, Digital Interface
7
NOTE1: Failure to respond to an IRa with a new strobe within the specified period results in the chip going into the power down mode.
Po

5.4

RLo AO = 100Q
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1
See Figure 1

83620

Figure 1. Timing Requirements

Timing of First and Second Bytes

1- Iws .!.
STROBE

lao - - - -..

---J

- - - - - ----;--------\

DATA~~~~=~~_
"

BUSY

1,--- - - - -

I j..-los-lIoH,~~~

I
I'

1.....--------

IRO

x::=x:

~_-_-=-~-

I
,

----------I

---,:-IWO--~
----~
;
---~
JI

iREP

.. ,

Pin FunctionlDescription
DO through 07

Data Inputs. The speech data (in quantized form is loaded on these line in 8-bit bytes.)

Strobe Input. A rising edge on this input strobes in the data bytes. Enunciation will commence after the first frame
of data has been loaded. If no strobe is received by the chip in response to an IRQ output then enunciation stops
immediately and the chip goes into power down mode.

Busy Output. This open drain output signals that enunciation is in progress by going low,

IRQ

Interrupt Request Output. This open drain output signals that the chip is ready to receive the next byte of data.
Failure to respond within the prescribed time results in the chip going into the power-down mode.

LS1 and 2

Loudspeaker Outputs. These pins are used to connect the chip to the loudspeaker. They are D. C. coupled and have
an offset of half the supply voltage. The audio output is balanced on the two outputs.
Oscillator Input and Output. A 640KHz ceramic resonator (MuRata CSB640A or equivalent) should be connected
between these pins for normal operation, or an external 640KHz signal may be fed into aSCi. When a resonator is
used, a 120pF capacitor should be connected between aSCi input and ground.

T1 , T2, T3

Test Inputs and Outputs. These inputs should be left unconnected for normal operation.

Vss

Most negative supply input. Normally connected to OV.

Voo

Most positive supply input.

AGNO

Analog Ground. An internally generated level approximately half way between Vss and Voo. A O.047",F decoupling
capaCitor CAG should be connected from this pin to Vss. Do not connect this pin to a voltage supply.

5.5

83620
city of 32767 sampling periods (4.096sec.). The output
of this generator is scaled to a lower value and used as
a random sign, constant amplitude signal.

Circuit Description
The main components of the S3620 LPC-10 Speech
Synthesizer are shown in the block diagram.

Voiced/Unvoiced Speech Selector Switch-This switch
determines whether the voiced or unvoiced signal
source is used to drive the filter during a given frame.

Input Latch-This 8-bit latch stores the input data after
the strobe pulse and loads it into the Coefficient Address Registers.

LPC-10 Parameter Stack-This stack of 10 filter coefficients is used to control the lattice filter. The coefficients have an accuracy of 8-bits plus sign.

End of Word Decoder-This circuit detects the special
code indicating that the last byte loaded in the Input
Latch denotes the end of the speech word data and initiates the power down routine after the previous frame
has been enunciated.

10 Stage Lattice Filter-The filter which simulates the
effect of the vocal tract on the sound source (glottis) in
the human speaker is realized here as a switchedcapacitor (analog sampled data) 10 stage lattice filter.
The filter parameters are determined dynamically by
the time varying coefficients in the Parameter Stack
and the filter operates at a sampling frequency of 8KHz
(clock frequency/80).

Buffer Registers-The data from the Speech Data ROM
is assembled into frames and then decimated into the
12 parameters required for LPC-10 synthesis: pitch,
gain and the 10 lattice filter coefficients. The parameters are stored in an encoded format and the decoding is done in the parameter value ROM. The coefficient address registers are used to store the assembled
frame data and address this ROM.

Gain Controller-This controls the input signal level to
the lattice filter to vary the sound level, and is an integral part of the lattice filter.

Bit Allocation PLA-A programmable logic array is used
to control the allocation of bits in the Buffer Register to
the 12 parameters. The allocation and permissible
variations are shown in Figure 2.

Interpolation Filter-The output signal from the lattice
filter is sampled at 8KHz, and consequently its spectrum is rich in aliasing (foldover) distortion components
above 4KHz (See Figure 3). The signal is cleaned up by
passing it through a 4KHz low pass filter sampled at
160KHz. The spectrum of the output signal contains no
aliasing distortion components below 156KHz, making
the output suitable for feeding directly into a loudspeaker after amplification. This filter is also realized
using switched-capacitor filter technology.

Parameter Value ROM-This ROM is used as a look-up
table to decode the stored parameters into the LPC
coefficients.
Interpolation Logic-The coefficients for each frame of
speech, normally 20msec. are interpolated four times
per frame to generate smoother and more natural
sounding speech. Hence, the interpolation period is
one quarter of a frame period, normally 5msec. After
interpolation, the coefficients are used to drive the
pitch-pulse source, the voiced/unvoiced switch, the lattice filter and the gain control. Interpolation is inhibited
when a change from voiced to unvoiced speech, orvice
versa, is made.

Power Amplifier-The amplifier brings up the level of
the signal to give an output level of 20mW RMS into a
100Q load. The output is a balanced bridge configuration with anti-phase Signals on the 2 output pins.
Clock Generators and Power-down Control-This block
contains the oscillator and timing circuits and also
generates the analog ground reference voltage.

Pitch Register and Counter-This register stores the
pitch parameter used to control the pitch counter.

Speech Data Compression

Pitch-pulse Source-This is the signal source for voiced
speech (vowel sounds). It is realized in switchedcapacitor technology and generates symmetrical bipolar pulses at the rate specified by the pitch parameter
and controlled by the pitch counter.

The speech data rate of the synthesizer is reduced to
less than 2000 bits/sec for storage by means of a nonlinear quantization technique. Each of the 12 coeffiCients is constrained to have a fixed set of values in an
optimized manner. The actual values are dependent on
the speech data and generated automatically in the
analysis proce·ss. The parameters used to specify the
coefficients are stored in the speech data ROM and

Pseudo-random Noise Source-This is the signal source
for unvoiced speech (fricatives and sibilants) and consists ofa 15-bit linear code generator giving a periodi5.6

83620
Figure 2. Packed Quantized Data Formats
BYTE 4

BYTE 5

BYTE 3

7 6 5 432 1 0 7 6 5 4 3 2 1

~r'rl-'

VOICED

6 5 4 3 2 1

BYTE' 1

7 6 543 2 1 0 7 6 5 4 3 2 1 0
V R
I E
U P f+GAIN ~
V T

K4,K3, K2, K1

I-.f- K1 O,k9,K8,K7 ,K6,K5

I I I I I I"

UNVOICED

BYTE 2

NOT USED

r'r'IKi'T

NOT USED

REPEAT

V R
I E
U P ~GAIN f+
V T

PITCH ... GAIN

R
E
P
T

*
END OF
WORD

*NOTE: 0

• 0

NOT USED

o0 o

=SINGLE (OR LAST) REPEAT. 1 = MULTIPLE REPEAT.

Figure 3.

~~~----------- ',,~~<
4

- . . KHz

152

156

160

164

168

(a) SPECTRUM OF SIGNAL OUTPUT OF LATTICE FILTER

~k1~-----------------------~~~-156

~KHz

160

164

(b) SPECTRUM OF SIGNAL AT OUTPUT OF INTERPOLATION FILTER.
NOTE: IN BOTH CASES A SIN xix CHARACTERISTIC MOOULATES THE SPECTRA.
THIS IS OMITTEO FOR SIMPLICITY.
.

used to address the coefficient look-up table ROM.
The packing formats for the speech data are shown in
Figure 2.
The speech data rate is further reduced by two other
techniques shown in Figure 2. A substantial reduction is achieved by reducing the order of the lattice
filter (the LPC order) to 4 during periods of unvoiced

5.7

speech. This allows a 40% data reduction during
these periods, which themselves typically account
for 30-40% of speech (in the English language). A second reduction is obtained by detecting periods during which the filter parameters may be the same as
those in the previous frame. Only the gain and pitch
parameters are updated in such a frame, allowing an
80% data reduction.

•

83620
ing it from memory. The Address decode function may
be realized using a PIA. An alternative interface technique is to write the data directly into the S3620 while
reading it from the memory. This can be accomplished
by mapping the S3620 into the entire address space of
the speech data portion of the memory, so that the
strobe is generated each time a byte of data is read
from the speech memory. This can save hardware, as
well as microprocessor instf(Jctions, since the loading
of each byte is now accomplished in a single Read
cycle instead of a Read cycle followed by a Write cycle.
An example of this interfacing is shown in Figure 5,
where the speech data occupies the memory addresses 0000 to 7FFF.

Generation of Speech Data for the 53620
The speech data input to the S3620 is in a compressed
format as explained in the previous section. AMI is able
to provide a complete speech analysis service for this
purpose and can supply the data programmed into
EPROMs or mask programmed ROMs up to 128k bits.
Customers who have LPC speech analysis facilities
and wish to generate their own data should contact
AMI for further details of the quantization technique used and the availability of software to accomplish this.

Interfacing
The 83620 is designed to be easily interfaced to an 8-bit
microprocessor system such as the S6800 family. The
timing requirements are shown in Figure 1. The first
data byte should be present at the data input lines
when the strobe line is taken to a logic 1 to begin enunciation and in response to each IRQ. The busy output
may be used to identify the IRQ source during polling in
a multiple interrupt system. A typical system configuration is shown in Figure 4. The S3620 occupies a single
address in the microprocessor's memory space and
data is loaded by writing it into that address after read-

Applications
Toys and Games
EDP
Instrumentation
Communications
Industrial Controls
Automotive
Appliances

Figure 4. Typical System Configuration

4.7kQ
100Q
IRI

S68XX

VDD LS1

IRQ

A15

LS2

OSCi

VMA

S3620
OSC o

ST
Do

J
':'

MEMORY
BANK

120,F

AGND

TO OTHER PERIPHERALS

5.8

.047/AF

$3620

Figure 5.
4.7KQ

Voo

iiiO

Ao
A15

VOO LS1
LS2

OSCi
S6BXX

VMA

S3620
OSC o

Do
D7

AGNO

-=
8000 TO FFFF
PROGRAM AND
NON·SPEECH
DATA MEMORY

ADDRESS BUS

DATA BUS

5.9

0000 TO 7FFF
SPEECH DATA
MEMORY

.047~F

12°~I

AMI.======
."""4.

A Subsidiary
of Gould Inc;

S36128

131,072 BIT NMOS
FEMALE SPEECH ROM

speech data.

Features
o Approximately 100 Seconds of Stored Speech

Vocabulary for Telecommunications, Industrial and
Numeric Applications

o
o

High Quality and Natural Sounding Female Voice

The S36128 speech ROM is fully TIL compatible on all
inputs and outputs and has a single + 5V power supply.
The speech data programmed in the S36128 contains
words and phrases suitable for telecommunications
and industrial applications, such as telephone answer·
ing, status announcements, timekeeping and emer·
gency messages.

Used with Gould AMI's S3620 LPC-10 Speech
Synthesizer
Ideal for Evaluation and Prototyping

The S36128 is pin and electrically compatible with the
Gould AMI S23128, a 131,072 bit static mask program·
mabie NMOS ROM. The S23128 can be used by custo·
mers who want to program in their own vocabularies.

General Description
The 836128 is a 131,072 bit (organized as 16,384 words
by 8-bits) static NMOS ROM mask programmed with

Block Diagram

Logic Symbol

Pin Configuration

Ne
A5
As

A7
AI
As

A,o

ROW
ADDRESS
DECODER
DRIVERS

MEMORY
MATRIX
131.072 BIT
ARRAY

A"
An
Au

Aa
A2

Al
Ao

Aa
A4

Pin Names

Ao·A 13

°0-°7
OE/CE

Vcc;GND;NC

5.10

Address Inputs
Data Outputs
Output Enable/Chip Enable
5V;Ground; No Connect

S36128
Absolute Maximum Ratings*
Ambient Temperature Under Bias ........................................................................................................... O°C to 70°C
Storage Temperature ....................................................................................................................... - 65°C to 150°C
Voltage on Any Pin With Respect to Ground ......................................................................................... - 0.5V to 7V
Input Voltages ......................................................................................................................................... - 0.5V to 7V
Power Dissipation .................................................................................................................................................. 1W
*COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating cCV1ditions for extended periods may effect device reliability.

D.C. Characteristics: Vee = + 5V ± 10%, TA = O°C to 70°C
Symbol

Parameter

Min.

Typ.

Max.

Units

0.4

Conditions
IOL = 3.2mA

IOH = -400,uA

VOL
VOH

Output LOW Voltage

VIL
VIH

Input LOW Voltage

-0.5

0.8

Input HIGH Voltage

2.0

III

-10

Vee
10

Input Leakage Current

IJA

VIN = OV to Vee

ILO

Output Leakage Current

-10

IJA

Vo = 0.4V to Vee Chip Deselected

lee

Power Supply Current-Active

Chip Enabled

ISB

Power Supply Current-Standby

Chip Disabled

Output HIGH Voltage

Capacitance: TA
Symbol
CIN
COUT

2.4

=25°C, f =1.0MHz

Parameter

Max.

Units

Conditions

Input Capacitance

Min.

Typ.

Output CapaCitance

VIN = OV
VOUT = OV

Rom Data Format

Operating Description
The S36128 is to be used with the AMI S3620 female
parameter LPC (Linear Predictive Coding) speech synthesizer. Words are listed (see page 3) with their beginning address. Word data ends at the last byte before the
following word. The speech data is packed into 8-bit
bytes. These bytes are fed in parallel by the user's controller to the S3620 speech synthesizer which performs
all of the unpacking and decoding of the formatted
data. This unpacking is transparent to the user.

The ROM data begins with an address field which gives
the starting address of each word in the vocabulary list
in sequence. The addresses are given next to the appropriate word in the vocabulary listing also. The starting
address upper half (SUH) is given first and the starting
address lower half (SLH) follows. A section of data for
internal use follows. The actual speech data begins
immediately afterwards.

5.11

836128
Items terminating with three periods ( . . . ) are intended
for use at the beginning of a sentence.

Address Field Format
CONTENTS
LOCATION
(DECIMAL)
0
1
2
3
I
I
2n 2
2n-1
2n

o I

O·

SUH
SLH
SUH
SLH
I
I
SUH
SLH
EUH

0 101
0 I 0 I

ELH
0

Word
1. One
2. Two
3. Three
4. Four
5. Five
6. Six
7. Seven
8. Eight
9. Nine
10. Ten
11. Eleven
12. Twelve
13. Thirteen
14. Fourteen
15. Fifteen

I
I
n

I0I

2n+3

I0I

10101010T

'" "" 'Numbers' ""'"

WORD
1

2n+ 1
2n+2

n
SUH
SLH
EUH
ELH

All other words carry no restrictions.

I b6 I b5 I b4 I b3 I b2 I b1 JbO

I0I

END ADDRESS OF
LAST WORD
END OF
ADDRESS
FIELD

NUM8ER OF WORDS STORED IN THE SPEECH ROM
STARTING ADDRESS:UPPER HALF
STARTING ADDRESS:LOWER HALF
END ADDRESS: UPPER HALF
END ADDRESS:LOWER HALF

0000
0010
0020
0030
0040
0050
0060
0070
0080
0090
OOAO
0080
OOCO
0000
OOEO
OOFO
0100
0110
0120
0130
0140
0150
0160

31.
32.
33.
34.

Data
01
04
09
OE
12
16
10
21
25
29
2F
36
38
19
98
38
A8
80
26
FO
02
BC

10
AE
95
24
7E
E8
16
53
90
C8
A8
38
75
80
EE
75
7A
1F
FO
05
7E
90
A4 AE

01
05
OA
OE
13
17
10
22
26
2A
2F
36
38
18
10
38
28
31
2B
08
91
2E
76

A4
3D
60
C1
06
78
9F
4A
OC
CE
F7
8A
78
68
16
78
FE
3E
93
86
E8
A5
26

02
05
08
OF
13
17
1E
22
26
28
30
37
38
38
1F
2F
AD
38
A6
28
02
16
74

10
A6
11
2F
88
EO
68
FF
53
C3
1F
A9
97
3C
5F
F7
C1
69
27
FO
08
73
84

02
06
08
OF
14
18
1E
23
27
2C
31
39
80
38
1F
30
2E
38
EO
03
7B
95
2E

89 03
38 06
09 OC
C3 10
08 14
90 18
E9 1F
37 23
13 27
48 2C
3E 31
E7 3A
OOIAO
5A 22
CF 04
1F 03
C8 38
75 AA
28 80
E2 86
9A EO
EE 95
77 42

04
C3
50
43
93
DE
5F
A9
CF
A8
CF
AO
03
4A
AE
04
3C
CE
BO
69
C3
15
35

03
07
OC
10
15
19
1F
24
28
20
32
38
21
22
05
03
38
28
27
F1
07
7C
C5

88
72
C3
DO
09
80
CF
36
7A
38
5F
3C
53
FF
3D
88
5A
C3
FO
02
B8
95
AD

03
08
00
11
15
18
20
24
28
20
32
38
38
87
16
38
AO
00
26
E8
91
2E
75

09
2E
38
74
7C
68
47
C8
FE
C1
99
5A
3C
A9
E8
75
47

04
08
00
11
16
18
20
25
29
2E
35
38
38
39
17
38
20

80
A6
AE
86
72

C5
EA
A4
26
67

Word
16. Sixteen
17. Seventeen
18. Eighteen
19. Nineteen
20. Twenty
21. Thirty
22. Forty
23. Fifty
24. Sixty
25. Seventy
26. Eighty
27. Ninety
28. Hundred
29. Thousand
30. Million

Beginning Address
08E4
0995
OA60
OB11
OB09
OC50
OCC3
0038
ODA6
OE24
OEC1
OF2F
OFC3
1043
1000

35. Friday
36. Saturday
37. Sunday

138B
1408
1493

""""Days of The Week""'"

Actual Data
Address

Beginning Address
0110
01A4
0210
0289
0304
0388
0309
045F
04AE
0530
05A6
0638
06C3
0772
082E

5F
E4 Address
Field
A6
F7
63
EE
03
30
77
C8
57
69
5A Internal
E7 Use Only
78
78
03
Speech
26
Data
F1 8egins at
07 Address
74
0110
01

Monday
Tuesday
Wednesday
Thursday

1174
11 F7
127E
1306

""" "Words and Phrases""""
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.

f'6'6'7O"6E

Word List of Telephone Application Vocabulary
Guide:
Items terminating with a single period (.) are intended
for use at the end of a sentence or are a complete
sentence themselves.
5.12

After
After the tone.
Again
A.M.
And
Area code
At
At this number.
This is an automatic message.
Before
8usiness hours are ...
Connected.
Emergency
Error.
Fire.
From
Function
Good-by.
Hello.
Identification
I'm sorry.
Is
Later
Medical ..
Number
Oh
Off.
On. (opposite of off)
On

1509
157C
1663
16EB
177B
17EO
1890
18DE
1980
1868
1BEE
1016
1D9F
1E68
1EE9
1F5F
1FCF
2047
2003
2153
224A
22FF
2337
23A9
2436
24C8
2530
2590
260C

836128
Words can be concatenated to form phrases or
sentences. Some examples are:

""""Words and Phrases"""" (Continued)
67.
68.
69.
70.
71.

72.
73.
74.
75.
76.
77.
78.
79.
80.
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
92.
93.
94.
95.
96.
97.
98.

Please call.
Please enter.
Please wait.
P.M.
Police ..
Port
Press the pound key.
Press the star key.
Status
Switch
Terminated.
Thank you.
Thank you for calling.
The time is .
Through
To
To change your entry.
To exit ..
Warning!
With
You are liftp,ning to Natural Voice from AMI.
You have dialed
Your
Your call back number
Your call cannot be answered at this time.
Your party
Zero
200ms pause
100ms pause
80ms pause
40ms pause
Tone

2653
2713
27CF
287A
28FE
2977
29C8
2ACE
2BC3
2C48
2CA8
2D38
2DC1
2ECB
2FAB
2FF7
301F
313E
31 CF
325F
3299
3557
363B
368A
37A9
39E7
3AAO
3B3C
3B5A
3B69
3B75
3B7B to 3B97

Sample One:

Hello. 1 200ms 1 This is an automatic message. I
You are listening to Natural Voice from AMI. I
1 200ms 1 Thank you for calling./200ms I Good-by.
Sample Two:

Business hours are I Monday I thru I Friday I from 191
A.M. 1 to 17 140ms I P.M. I
Sample Three:

Please callI your party I before I 31 P.M.
Sample Four:

Please enter I your call back number I with 1 40ms 1
area code I after the tone. I 200ms I tone I
Sample Five:

To exit I 80ms I press the pound key.

5.13

AIMII.---------."""4..

A Subsidiary
of Gould Inc.

EVK 3620

SPEECH SYNTHESIS
EVALUATION BOARD

• Programmed microcomputer (S360S) provides
several modes of operation such as:
Playa Single word
Build and playa phrase
Repeat word or phrase
Play preprogrammed messages
Play the entire vocabulary
• Edge connector for interfacing with user system for
product prototyping.
• Onboard audio amplifier.

Features

• Needs only a + SV source and either an 8 ohm or 100
ohm loudspeaker for complete operation. (With the
addition of a 780S regulator and a capacitor it can be
run by a 9V battery eliminator similar to calculators
and video games.)
• Large speech vocabulary (up to 100 seconds of
speech stored in a 128K bit ROM).
• Demonstrates the wide application range of the
S3620 speech synthesis chip.
EVK 3620 Speech Board Block Diagram

Edge Connector Assignments

GROUND

AMI
S3605
SINGLE
CHIP
MICRO-COMPUTER

ST
iRa

AMI
S3620
SPEECH
SYNTHESIZER

1
2

+ 5V

,,+ BV C

,,+ 8V

128K BIT
SPEECH
ROM

DATA BUS

+ 5V 8

V-AUDIO
AMPLIFIER

S.14

GROUND

8 OHM OUT

100 OHM OUT

Al0

All

A12

A13

20
21

IRQ

~1~ll~~~~~
.""""4.
~

A Subsidiary
of Gould Inc.

84520

30-Volt
Dichroic LCD Driver

Features
o High Voltage Outputs Capable of a 32-Volt Swing
o Drives Up to 38 Devices
o Cascadable
o On~Chip Oscillator
o Requires Only 4 Control Lines
o CMOS Construction For:
Wide Supply Range
Low Power Consumption
High Noise Immunity
Wide Temperature Range
Applications
o Liquid Crystal Displays
o Flat Panel Displays
o Print Head Drives

General Description
The AMI S4520 is a CMOS/LSI circuit that drives highvoltage dichroic liquid crystal displays, usually under
microprocessor control. The S4520 requires only four
control inputs (CLOCK, DATA IN, LOAD and CHIP
SELECT) due to its serial input construction. It can
latch the data to be output, relieving the micropro- •
cessor from the task of generating the required waveforms, or it may be used to bring data directly to the
drivers. The A.C. frequency of the backplane output can
_ ~
be generated by the internal oscillator or, the user has
the option of supplying this signal from an external
source. If the internal oscillator is used to generate the
backplane signal, the frequency will be determined by
an external resistor and capacitor. One S4520 circuit
can drive 38 segments. Other packaging options can
provide 30 or 32 segment drivers.

Block Diagram

Pin Configuration

0"
023
0"
0"

DATA
IN

026
0032

0"
0"

CHiP

0030

029
OlD

LOAD

014
013
0"

5.15

S4520
Absolute Maxiumum Ratings
Voo ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''.................................................................... - 0.3 to + 17V
VBB ........................................................................................... "'''''''''''''''''''''''''''''''''''''''''''''''' Vss + 0.3V to·Voo - 32V
Inputs (CLK, DATA IN, LOAD, LCD~) ........................................................................................ Vss - 0.3V to Voo + 0.3V
Power Dissipation ............................................................................................................................................... 250mW
Storage Temperature ..............................................................................................."""'''''''''''''''''' - 65°C to + 125°C
Operating Temperature ...................................................................................................................... - 55°C to + 85°C
Electrical Characteristics:

3V~Voo~16V,

Symbol

Parameter

Voo

Power Supply
Logic Supply Voltage

VBB
100

55°C~TA~

Display Supply Voltage

+ 85°C, unless otherwise noted
Min.

Display Driver Current

V'H

Inputs (ClK, DATA IN, lOAD, CS)
Input High Level

Units

Test Condition

Voo -32
Voo - 32

Voo-15
Voo - 22

V
V

Voo~11V
Voo~11V

200
200
750

/-lA
/-lA
/-lA

Voo~5V

-200

/-lA

Supply Current (external oscillator)
Supply Current (internal oscillator)

IBB

Max.

0. 5Voo

Voo

Vss

0. 2VOD

CMOS input levels. No loads.
Voo = 16V; CMOS input
levels. No loads.
fBP = 100Hz. No loads.
VOD~5V

V'L
IL

Input Low Level
Input Leakage Current

/-lA

Input Capacitance

VO AVG

DC Bias (Average) Any Segment Output to
Backplane

±25

V'H

LCD~

Input High Level

0. 9Voo

Voo

Externally Driven

V'L

LCD~

Input Low Level

VBB

O· 1Voo

Externally Driven

CLSEG

Capacitance loads (typical)
Segment Output

1000

fBP~100Hz

CLBP

Backplane Output

40000

fBP~100Hz

RSEG
RBP

Segment Output Impedance

IL = 10 /-lA

Backplane Output Impedance

312

IL = 10 /-lA

Roo

Data Out Output Impedance

IL = 10 /-lA

5.16

fBP~100Hz

84520
Operating Notes
1. The shift register loads and shifts on the falling edge of CLK. DATA OUT changes on the rising edge of CLK.
2. The buffer number corresponds to how many clock pulses have occurred since its data was present at the input
(e.g., the data on Q10 was input 10 clock pulses earlier). DATA is shifted into Segment 1 and shifted out from Segments 30, 32 or 38, depending on bonding option used.
3. A logic 1, shifted into the shift register (through DATA IN), causes the corresponding segment's output to be out
of phase with the backplane.
4. A logic 1 on LOAD causes a parallel load of the data in the shift register, into the latches that control the output
drivers.
5. LOAD may also be held high while clocking. In this case, the latch is transparent and, the falling edge of LOAD will
latch the data.
6. To cascade units, (a) connect the DATA OUT of one chip to the DATA IN of the next chip, and (b) either connect
the backplane of one chip to LCD~ of all other chips (thus one RC provides frequency control for all chips) or connect LCD~ of all chips to a common driving signal. If the former is chosen, the backplane that is tied to the LCD~ of
the other chips should not also be connected to the backplanes of those chips.
7. The LCD~ pin can be used in two modes, driven or self-oscillating. If LCD~ is driven, the circuit will sense this
condition. If the LCD~ pin is allowed to oscillate, its frequency is determined by an external capacitor. The
Backplane frequency is a divide by 256 of the LCD~ frequency, in the self-oscillating mode.
8. If

LCD~

is driven externally, it is in phase with the backplane output.

9. Backplanes can be tied together, if they have the same signal applied to their

LDC~

inputs.

10. In the self-oscillating mode, the backplane frequency is approximately defined by the relationship
fsp(Hz) = 10 + R(C + .0002) at Voo = 5V, R in KQ, C in jAF.
examples:

R = 56KQ, C = .0015 jAF:
R 110Q, C .00068 jAF:

fsp=100Hz
fsp=100Hz

11. Minimum value of R for RC oscillator is 50KQ.
12. Power consumption increases for clock rise or fall times greater than 100ns.

Pin Description
Pin #*

Pin #**

Name

22
39
16
17
18
19
21
21
20
46
45
1-15,23-38
40-44,
47,48

23
40
17
18
19
20
22
22
21
47
46
1-16,24-39,
41-45,
48

VDD
Vss
Vss
CS
CLOCK
LOAD

Description

DATA IN
D038
BP

Logic Supply Voltage
Display Supply Voltage
Ground Connection
Chip Select Inverse Input
System Clock Input
Input Signal to Latch Shift Register Data
LCD Oscillator Input
LCD Oscillator Option (S4520A,S4520C)
Data Input to Shift Register
Data Output from Shift Register (after bit 38)- Primarily used for cascading
Backplane Drive Output

Q1- Q38

Segment Outputs

LCD~
LCD~ OPTION

*S4520A-lnternal Oscillator, 48-Pin Plastic DIP
* * S4520C-1 nternal Oscillator, 48-Lead Ceramic Chip Carrier

S4520B-External Oscillator, 48-Pin Plastic DIP
S4520D-External Oscillator, 48-Lead Ceramic Chip Carrier

5.17

•

S4520
Timing Characteristics:
Symbol
Parameter

Min.

Max.

Units

tCYC

Cycle time (noncascaded)

1000
500
320

ns
ns
ns

tCYC

Cycle time (cascaded)

1300
600
350

ns
ns
ns

tal, tOH

Clock pulse width low/high

450
220
140

ns
ns
ns

tOH

Clock pulse width high (cascaded)

750
320
180

ns
ns
ns

tr,

Clock rise, fall (Note 12)
Data In setup

300
150
120

ns
ns
ns

tcsc

CS setup to Clock

200
100
50

ns
ns
ns

tOH

Data hold

tccs

CS hold

450
220
140

ns
ns
ns

tCl

Load pulse setup (Note 5)

500
280
180

ns
ns
ns

tlCS

CS hold (rising LOAD to rising CS)

300
200
150

ns
ns
ns

tlW

Load pulse width (Note 5)

500
220
140

ns
ns
ns

tlC

Load pulse delay (Falling load to falling clock)

tcoo

Data Out valid from Clock

tCSl

CS setup to LOAD

5.18

3.0V
5.0V
~7.5V

I-ts

tos

550
220
110

VDD

ns
ns
ns
ns

3.0V
5.0V
~7.5V

S4520

Figure 1. Signal Timing Diagram
Icyc

~,al"
CLOCK

-''"l

1,-

j~ :
"TA.~
IDH

I-

I
I

r---'~'-I

j '~'r---

CS~

I'~'l

I
1_llC

ICSL

_ICl

P.=I ~
:

-llW-

"\~

LOAD

---1'~' C=

DATA OUT

Logic Truth Table

x
X

0
0
0
0
1
1
1
1
Notes:

X
X
.s.sL
L

.s.sL
L

NC = No Change

1
1
O
O
0
0
O
O
0
0

0
1
0
1
0
1
0
1
0
1

NC
NC
NC
NC
0
0
NC
NC
1
1

SR = Shift Register

L = Latch

5.19

NC
NC
NC
NC
ON-1_0N
ON-1_0N
NC
NC
ON-1_0N
ON-1_0N

0
1
1
1
1
1
1
1
1
1

ON(L)
ON(L)
ON(L)
ON(L)
ON(L)
QN(SR)
ON(L)
ON(L)
ON(L)
QN(SR)

84520
Chip Select Inverse Input

Data Input

The C8 input is used to enable clocking of the shift
register. When C8 is low, the chip will be selected and
the shift register will be enabled. When C8 is high, the
shift register will be disabled and the output buffers will
be driven by the data in the latches.

Data present at DATA IN will be clocked into the shift
register, when C8 is low. Data is loaded into the shift
register on the falling edge of the clock and shifts to the
output on the rising clock edge.

Clock Input

Data Output

The CLOCK input is used to clock data serially, into the
shift register. A clock signal may be continuously present, because the shift register is enabled only when
C8 is low.

Depending on the packaging option selected, 0030,
0032 and 0038 are buffered outputs driven by the
corresponding element of the shift register. The value
of DOxx will be the same as the value of the matching
shift register bit (Le. the value at 0032 will be the same
as bit 32 of the shift register). The data output is typically used to drive the data input of another 84520. By
cascading 84520 circuits in this manner, additional
display elements can be driven.

Load Input

The LOAD input controls the operation of the data latches and allows new data to be loaded into the shift
register, without changing the appearance of the display. When LOAD is high, the values in the shift register
will be loaded into the data latches. If desired, LOAD
can be held high and the data latches will be transparent. The LOAD input is disabled when C8 is high.

Backplane Output

The backplane output provides the voltage waveform
for the LCD backplane. When used with the internal
oscillator, the backplane frequency will be equal to the
oscillator frequency divided by 256:

LCD Oscillator Input

When used with an external oscillator, the LCD
oscillator is driven by the input voltage level. In this
configuration, the backplane output will be in phase
with the input waveform. In the self-oscillating mode,
an external resistor and capacitor are connected to the
oscillator input pin, and the backplane frequency will
be a divide by 256 of the internal oscillator frequency.

tsp = tosc (int) + 256.
With an external oscillator, the backplane frequency
will be in phase with and equal in magnitude to the input signal.
Segment Drive Outputs

LCD Oscillator Option

The segment drive outputs provide the segment drive
voltage to the LCD. With a logic level "1" in the latch
associated with the segment drive output, the output
voltage will be out of phase with the backplane (Le the
segment will be ON). A logic level "0" will cause the
segment drive to be in phase with the backplane output
voltage.

When the internal oscillator is used, the LCD oscillator
option is internally (or externally) connected to the LCD
oscillator input and, it provides the oscillator feedback.
When used with an external oscillator, the LCD oscillator option is not connected (Le. LCD~ OPTION is
grounded).

5.20

84520
Figure 2. Typical Application

MICROPROCESSOR DRIVEN
CASCADED DISPLAY DRIVERS

-J-

-t'

VBB ~,

22 VDD
21 .- LCD~

~r- ~

··
···
··
·

S4520A
20 DATA IN

19 LOAD

18 CLOCK

l.LCD~ OPT.

fJPROCESSOR

24V

Vss

038

BP~ "---

0038 ~

LCD
SEGMENT I

··
··
I

LCD
BA CKPLANE
~

..... ~ VDD

VBS ~

~ LCD~

··
··
···
·

~LCD~OPT.

S4520B
20 DATA IN
19 LOAD
18 CLOCK

Vss

038

BP 45
0038

~"______"~"______-J~

TO OTHER S4520B DISPLAY DRIVERS

5.21

··
·
··
I

S4520

Figure 3. 48-Lead Ceramic Chip Carrier
06
31

07
32

08
33

09
34

010
35

011
36

012 013 014
37 38 39

Vee 015
40 41

016
42

05·30

43·017

04·29

44·018

03·28

45·019

02·27
01·26
038·25
037·24

1·021

VDII"23

2·022

LCDt·22
LCDt OPT.

3·023

01·21

4·024

LOAD·20

5·025

CLK·19

6·026

17
Vss

16 15
036 035

14 13
034 033

12 11
032 031

10
030

9
8
029 028

7
027

NOTE: VIEWED FROM THE BOTTOM SIDE OF THE PACKAGE

Ordering Instructions
1. All orders must specify a package type (i.e. S4520A, 48-pin plastic DIP)
2. All orders must specify whether an internal oscillator or external oscillator will be used (i.e. S4520B, external oscillator).
3. A set-up charge or minimum order quantity may apply for packaging options not shown.
Please contact factory for further information.

5.22

AMII.---------.""'4.

A Subsidiary
of Gould Inc.

54521

32 BIT DRIVER
General Description
The AMI S4521 is an MOS/LSI circuit that drives a variety of output devices, usually under microprocessor
control. This device requires only three control lines
due to its serial input construction. It latches the data
to be output, relieving the microprocessor from the
task of generating the required waveform,or it may be
used to bring data directly to the drivers. The part acts
as a versatile peripheral to drive displays, motors,
relays and solenoids within its output limitations. It is
especially well suited to driving liquid crystal displays,
with a backplane A.C. signal option that is provided.
The A.C. frequency of the backplane output that can be
user supplied or generated by attaching a capacitor to
the LCD~ input, which controls the frequency of the internal oscillator. One circuit will drive up to 32 devices
and more can be driven by cascading several drivers
together. The S4521 F version is available in a surfacemountable plastic mini-flat pack.

Features
o Drives Up to 32 Devices
o Cascadable
o On Chip Oscillator
o Requires Only 3 Control Lines
o CMOS Construction For:
Wide Supply Range
High Noise Immunity
Wide Temperature Range
Applications:
o Liquid Crystal Displays
o LED and Incandescent Displays
o Solenoids
o Print Head Drives
o DC and Stepping Motors
o Relays.

Functional Block Diagram

Pin Configuration

CLOCK

DATA
OUT

DATA IN

LOAD

02 -------------------------- 032

LCD,

+VDD

CLOCK

LOAD

032

031

03D

Vss

029

DATA OUT

028

DATA IN

027

026

025

LCD~

024

023

022

021

020

019

010

018

011

012

016

013

015

014

5.23

I
-

- :-

84521
Absolute Maximum Ratings
VDD ............................................................ '" ..... ......... ........ ........ ... ... ..... .... ........ ................. ............. ... .... - 0.3 to + 17V
Inputs (CLK, DATA IN, LOAD, LCD~) ....................................................................................... Vss - 0.3 to VDD + 0.3V
Power Dissipation ............................................................................................................................................. 250mW
Storage Temperature ..................................................................................................................... - 65°C to + 125°C
Operating Temperature ................................................................................................................... - 40°C to + 85°C

Electrical Characteristics:
Symbol

Parameter

Voo

Supply Voltage

3V~VDD~13V,

unless otherwise noted

Max.

Units

200
200

jiA
jiA

fsp = 120Hz, No load, Voo = 5V
lCD~ High or low, fsp=O
load @ logic 0, Voo = 5V

0.6 Voo
0.5 Voo
Vss

Voo
Voo
0.2 Voo

3V~Voo<5V

5
5
2

V
V
V
jiA
pF

Min.
3

Test Condition

Supply Current
1001
1002

Operating
Quiescent
Inputs (elK, DATA IN, lOAD)

VIH

High level

V1L
IL
C1

low level
Input Current
Input Capacitance

fCLK

ClK Rate

tos

Data Set-Up Time

100

Data Change to ClK Falling Edge

tOH

Data Hold Time

Falling ClK Edge to Data Change

tpw

load Pulse Width

200

tpo

Data Out Prop. Delay

load Pulse Set-Up

300

tLCO

load Pulse Delay

Falling load Pulse to Falling ClK
Edge

VOAVG

DC Bias (Average) Any Q
Output to Backplane

±25

fsp = 120Hz

V1H
V1L

lCD~

Input High level

.9 Voo

Voo

Externally Driven

lCD~

Input Low Level

Vss

.1 Voo

Externally Driven

50,000
1.5

fsp = 120Hz
fsp = 120Hz, See Note 8

MHz

5V~Voo~13V

50% Duty Cycle

ns
220

CL= 30pF, From Rising ClK Edge
Falling ClK Edge to Rising load
Pulse

Capacitance loads
CLQ
CLBP

Q Output
Backplane

RON

Q Output Impedance

3.0

pF
f..lF
KQ

RON

Backplane Output Impedance

100

IL = 10jiA, Voo = 5V

RON

Data Out Output Impedance

3.0

IL = 10jiA, Voo = 5V

5.24

10jiA, Voo = 5V

S4521
sense this condition. If the LCD~ pin is allowed to
oscillate, its frequency is determined by an external
capacitor. The Backplane frequency is a divide by 32
of the LCDcj> frequency, in the self-oscillating mode.

Operating Notes
1. The shift register shifts on the falling edge of CLK. It
outputs on the rising edge of the CLK.
2. The buffer number corresponds to how many clock
pulses have occurred since its data was present at
the input (e.g., the data on 010 was input 10 clock
pulses earlier).

8. In the self-oscillating mode, the backplane frequency
is approximately defined by the relationship
fsp(Hz) = 0.2 + C(in ",F) at Voo = 5V.

3. A logic 1 on Data In causes a 0 output to be out of
phase with the Backplane.

9. If the total display capacitance is greater than 100,000
pF, a decoupling capacitor of 1",F is required
across the power supply (pins 1 and 36).

4. A logic 1 on Load causes a parallel load of the data in
the shift register, into the latches that control the 0
output drivers.

Pin Description

5. To cascade units, (a) connect the Data Out of one
chip to Data In of next chip, and (b) either connect
Backplane of one chip to LCDcj> of all other chips
(thus one RC provides frequency control for all
chips) or connect LCDcj> of all chips to a common
driving signal. If the former is chosen, the Backplane
that is tied to the LCDcj> inputs of the other chips
should not also be connected to the Backplanes of
those chips.
6. If LCDcj> is driven, it is in phase with the Backplane
output.
7. The LCDcj> pin can be used in two modes, driven or
self-oscillating. If LCD4> is driven, the circuit will

Signal Timing Diagrams

Description

Pin #

Name

1
2
30
31
34
35

Voo
LOAD
BP
LCDcj>
DATA IN
DATA OUT

36
40
3-29,
32·33,
37-39

Vss
CLOCK

Logic and Q Output Supply Voltage
Signal to Latch Data from Registers
Backplane Drive Output
Backplane Drive Input
Data Input to Shift Register
Data Output from Shift Registerprimarily used in cascading
Ground Connection
System Clock Input

01-0 32

Direct Drive Outputs

{11~'__________ l"ClK_===================---I~

1"-

,\,----,

1'"1-'"1- :
Y<'-________~i-------------~I'~ Iill.-'~
-i,,, 1-

DATAIN=X

·-------ILC----'------I

I P _ WL "

LDAD~,

--t-i___~!

_____________

I
I

DATAOUT _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _/ ( - - - - - - - - - - - - - -

5.25

•

AMI.======
~

A Subsidiary
of Gould Inc.

S4535

32 BIT, HIGH VOLTAGE DRIVER

Features
o High Voltage Outputs Capable of 60 Volt Swing
o Drives Up to 32 Devices
o Cascadable
o Requires Only 4 Control Lines

General Description
The AMI S4535 is a high voltage MOS/LSI circuit that
drives a variety of output devices, usually under microprocessor control, by converting low level signals such
as TTL, and CMOS to high voltage, high current drive
signals. This device requires only four control lines due
to its serial input construction. It latches the data to be
output, or it may be used to bring data directly to the
driver. The part acts as a versatile peripheral to drive
displays, motors, relays and solenoids within its output
limitations of a 60 volt swing and up to 25mA per drive.
It is especially well suited to drive vacuum fluorescent
displays due to its high voltage output capability. One
circuit will drive up to 32 devices and more can be
driven by cascading several drivers together.

Applications:

o
o
o
o
o
o

Vacuum Fluorescent Displays
LED and Incandescent Displays
Solenoids
Print Head Drives
DC and Stepping Motors
Relays

Pin Configuration

Functional Block Diagram
CLOCK

VBB
SERIAL
OUTPUT

OATA

STROBE

OUTPUT
OISABLE

vss

c:::>

02 - - - - - - - - - - - - - - - - - - - - - - - - - - 032

Output Buffer (Functional Diagram)
,-------.__-<

.............-NV'-+--<-~

5.26

v••

VDD

032

031

030

029

028

027

026

025

024

023

010

022

011

021

012

020

013

019

014

018

015

017

016

OUTPUT

STR

Vss

eLK

S4535
Absolute Maximum Ratings at 25°C
Vee ........................................................................................................................................................................... 65V
Voo ........................................................................................................................................................................... 12V
V1N .................................................................... ~.......................................................................... Vss - .3V to Voo + .3V
VOUT (Logic) ................................................................................................................................ Vss - .3V to Voo + .3V
VOUT (Display) ....................................................'......................................................................... Vss - .3V to Vee + .3V
Power Dissipation ..........................................................................................................................................,...... 1.6W
Operating Temperature ........................................................................................................................ O°C to + 70°C*
Storage Temperature ..................................................................................................................... - 65°C to + 125°C
* Extended temperature range available. Please contact AMI for price and delivery information.

Operational Specification:
Symbol

O°C~TA ~70°C

(unless otherwise noted)

Parameter

Min.

Max.

Units

V1L

Input Zero Level

-0.3

0.8

Test Condition

VIH
VSL
VS H

Input One Level

3.5

Voo + 0.3

Signal Out Zero Level

Vss

0.5

Iso = - 20J-tA

Signal Out One Level

Voo - 0.5

Iso = 20J-tA

Voo

Logic Voltage Supply

4.5

Voo
5.5

Vss

Display Voltage Supply

100

Logic Supply Current

No Loads, T= 25°C

Iss

Display Supply Current

10
168

mA
mA

No Loads, T= 25°C
With Load

VOL

Output Zero Level

Vss

1.0

10= -20~

VO H

Output One Level

Vss - 2.5
Vss - 3.2

V
V

10=5mA
10 = 25mA, One Output

tso

Serial Out Prop. Delay

Vss
Vss
500

tpo

Parallel Out Prop. Delay

j.4S

CL= 50pF
CL= 50pF

Input Pulse Width

500

tsu

Data Set-Up Time

150

Data Hold Time

Functional Description
to-parallel conversion). The latches will continue to
accept new data as long as the strobe signal is held
high.

Serial data present at the input is transferred to the shift
register on the Logic "0" to Logic "1" transition of the
clock input signal. On succeeding clock pulses, the
registers shift data information towards the serial data
output. The input serial data must be presented prior to
the rising edge of the clock input waveform.

Information present at any register is transferred to its
respective latch when the strobe signal is high (serial5.27

S4535
Pin Description

Name

Description

Vss
DO

Ground Connection

2
19

Output Disable

Pin #

Output of Shift Register-primarily used for cascading

VBB

o Output Drive Voltage

ClK

System Clock Input

Voo
STR

logic Supply Voltage

Data Input to Shift Register

01 -032

Direct Drive Outputs

3-18 and 23-38

Strobe to latch Data from Registers

Signal Timing Diagrams
Data Write
DATA

CLOCK

SERIAL OUTPUT

Data Read

itwj
STROBE

PARALLEL OUTPUTS

--.-!I'

\------.4,\

____x==

Output Inhibit
OUTPUT DISABLE

PARALLEL OUTPUTS

5.28

AIMII.---------."""4.
~

A Subsidiary
of Gould Inc.

54534

10 BIT, HIGH VOLTAGE
HIGH CURRENT DRIVER

General Description
The AMI S4534 is a high voltage, high current MOS/LSI
circuit that drives a variety of output devices, usually
under microprocessor control, by converting low level
signals such as TTL, and CMOS to high voltage, high
current drive signals. This device requires only four
control lines due to its serial input construction. It latches the data to be output, or it may be used to bring •
data directly to the driver. The part acts as a versatile
peripheral to drive displays, motors, relays and solenoids within its output limitations of a 60 volt swing and
up to 50mA per drive. It is especially well suited to drive
vacuum fluorescent displays due to its high voltage
output capability. One circuit will drive up to 10 devices
and more can be driven by cascading several drivers
together.

Features
o Outputs Capable of 60 Volt Swings at 25mA
o Drives Up to 10 Devices
o Cascadable
o Requires Only 4 Control Lines
Applications:

o
o

o
o
o

Vacuum Fluorescent Displays
LED and Incandescent Displays
Solenoids
Print Head Drives
DC and Stepping Motors
Relays

Pin Configuration

Functional Block Diagram
CLOCK

SERIAL
OUTPUT

DATA

STROBE

OUTPUT
DISABLE

VssC:>

Q, --------------------------Q1O

Output Buffer (Functional Diagram)

v,,

OUTPUT

5.29

0'0

elK

VBa

Vss

VOD

STR

84534
Absolute Maximum Ratings at 25 0 C
VBB ............................................................................................... 65V
VDO ...•.............•....................•........................................•.......... 4.5 to 15V
VIN ............................................................................... VSS - .3V to VOO + .3V
VOUT (Logic) ....................................................................... VSS - .3V to Voo + .3V
VOUT (Display) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. Vss - .3V to VBB + .3V
Power Dissipation ................................................................................ 1.2W
Operating Temperature ................................................................... ooe to + 70 e
Storage Temperature ................................................................. - 65°e to + 125°e
0

Operational Specification: ooe

70 0 e (unless otherwise noted)

Parameter

Min.

Max.

Units

Input Zero Level

-0.3

1.1

Input One Level

3.4
3.6

Voo + 0.3
Voo + 0.3

V
V

4.75V~

1.0

!1A

Voo=5V

Signal Out Zero Level

Vss

0.7

Iso= - 20!1A

Signal Out One Level

Voo - .95
4.3

V
V

Iso=20JAA, 4.75V~Voo<5.25V
Iso = 20!1A, 5.25V~ Voo~ 12.0V

VDO

Logic Voltage Supply

4.75

Voo
Voo
12

VBB

Display Voltage Supply

100

Logic Supply Current

20
30

mA
mA

No Loads, Voo=5V
No Loads, Voo = 1OV
No Loads, T = 25°C

Symbol
VIL
VIH
liN
VSL
VSH

Input Leakage Current

1.0

10 = - 20!1A

VBB
375

10=25mA

JAs

CL=50pF
CL=50pF

IBB

Display Supply Current
Output Zero Level

tso

Serial Out Prop. Delay

tpo

Parallel Out Prop. Delay

Input Pulse Width

375

tsu

Data Set-Up Time

150

Data Hold Time

Output One Level

= Voo <5.25V

5.25V~ Voo~12.0V

VOL
VOH

Vss
VBB - 2.5

Test Condition

Functional Description
Serial data present at the input is transferred to the shift
register on the Logic "0" to Logic "1" transition of the
clock input signal. On succeeding clock pulses, the
registers shift data information towards the serial data
output. The input serial data must be presented prior to
the rising edge of the clock input waveform.
Information present at any register is transferred to its
respective latch when the strobe signal is high (serialto-parallel conversion). The latches will continue to accept new data as long as the strobe signal is held high.

When the output disable input is high, all of the high
voltage buffers are disabled without affecting the information stored in the latches or shift register. With the
output disable signal low, the high voltage outputs are
controlled by the state of the latches.
At low logic supply voltages, it is possible that the
serial data output (DO) may be unstable for up to 2JAs,
after the rising edge of the strobe (STR) or output
disable (00) inputs.

5.30

84534
Table 1.

Pin Description

NUMBER OF

MAX. ALLOWABLE DUTY CYCLE AT

OUTPUTS ON

AMBIENT TEMPERATURE OF

Pin #

Name

Vss
DO

(lOUT = 25mA)

25°C

40°C

50°C

60°C

70°C

100%

97%

85%

73%

62%

13
15

100%

94%

82%

69%

100%

I 1

100%

92%

78%

100%

89%

14
1-3,
8-12,
17-18

100%

00
VBB
ClK
Voo
STR
01

100%

1-°10

Description

Ground Connection
Output of Shift Registerprimarily used in cascading
Output Disable
Output Drive Voltage
System Clock Input
logic Supply Voltage
Strobe to latch Data from Registers
Data Input to Shift Register

Direct Drive Outputs

•

Signal Timing Diagrams

Data Write
DATA

CLOCK

SERIAL OUTPUT

Data Read

STROBE

PARALLEL OUTPUTS

,twi

~
I'

\--------------+tal

____x==
Ipo

Output Inhibit
OUTPUT DISABLE

-----1111_~~
.

PARALLEL OUTPUTS

5.31

AIMI.---------."""4.

A Subsidiary
of Gould Inc.

Advanced Product Description

S2809

UNIVERSAL
DISPLAY DRIVER

General Description
The 52809 Universal Driver is a P-Channel MOS integrated circuit. Data is clocked serially into a 32-bit masterslave static shift register. This provides static parallel
drive to the output bits through drive buffers. To reduce
RFI emanation, capacitors have been integrated on the
circuit for reduction of output switching speeds. Serial
interconnection of circuits is made possible by the
Data Out Output, allowing additional bits to be driven.

Features
o 32 Bit Storage Register

32 Output Buffers

Expansion Capability for More Bits

Reduced RFI Emanation

Wired OR Capability for Higher Current

Two or more outputs may be wired together for higher
sourcing currents; useful in applications such as triac
triggering or low voltage incandescent displays. The
52809 can also be used as a parallel output device for
JAC'S such as AMI's 52000 series single chip microcomputer.

Block Diagram

Pin Configuration

OUTPUT
1 OF 32
STATIC SHIFT
REGISTER elEMENTS

24
25

OUTPUT

DATA OUT
INVERT
13

V"
BfANj(

CHIP SELECT

CLOCK

DATA IN
OUTPUT

OUTPUT

5.32

52809
Absolute Maximum Ratings
Operating Ambient Temperature TA ......................................................... 10°C to + 70°C
Storage Temperature . .................. " ........................... , ........... , ..... - 65°C to + 150°C
Vss Supply Voltage . ............................................................................. " + 25V
Positive Voltage on Any Pin . ................................................................... Vss + O.3V

Electrical Characteristics (Voo = OV, BV < Vss < 22V, TA = 10°C to + 70°C unless otherwise noted)
Symbol

Parameter

V1H

Logic 1 Level (Data, Clock,
Invert, Chip Select Inputs)

V1L

Logic 0 Level (Data, Clock
Invert, Chip Select Inputs)

VBH

Min.

Typ.

Max.

Units

Vss -0.7

Vss +0.3

VDD

Vss -7

Logic 1 Level
(Blank Input)

Vss -4.0

Vss +0.3

VBl

Logic 0 Level
(Blank Input)

VDD

Vss -7

Current Sinked or Sourced
by Blank Input

1.0

JAA

Conditions

•
Voltage applied to Blank
Input between VDD & Vss

Capacitance of Blank Input

IOH

Output Source Current

9.0

VOUT = Vss -3

IOH

Output Source Current

4.0

VOUT=Vss -1.5

los

Sink Current Output
Load Device

JAA

Output voltage = Vss

los

Sink Current Output
Load Device

JAA

Output voltage = VDD + 3V

Output Leakage Current
(Output Off)

10.0

JAA

IDD

Supply Current

3.0

Not including output source
and sink current

10M

Maximum Total Output
Loading

300

All outputs on

50
10

100K

Clock Frequency

tON

Clock Input Logic I Level
Duration

3.0

/AS

tOFF

Clock Input LogiC 0 Level
Duration

6.5

/As

t ro , tto

Display Output Current
Rise and Fall Times

150

/As

• NOTE: With supply voltages higher than 11 volts, delay exists before an output rise or fall. This delay will not exceed 1001'5 with a 22 volt supply.

5.33

*Measured between 10%
and 90% of output current
Vss < + 11V, 10H = 9ma

82809
Blank Input
This input may be used to control display Intensity by
varying the output duty cycles. With a logic 0 level at
the Blank Input, all outputs will turn off (Le., outputs will
go to the logic level of the Invert Input). With a logic 1
level at the Blank Input, outputs are again driven in
parallel by the 32 shift register elements (assuming the
Chip Select Input is at logic 0).
The Blank Input has been designed with a high thres·
hold to allow the use of a simple RC time constant to
control the display intensity. This has been shown in
Figure 1.

Functional Description
The 32·blt static shift register stores data to be used for
driving 32 output buffers. Data is clocked serially into
the register by the signal applied to the Clock Input
whenever a logic 1 level is applied to the Chip Select In·
put; during this time, outputs are not driven by the shift
register but will' go to the logic level of the invert input.
With a logic 0 level applied to the Chip Select Input, the
32 outputs are driven in parallel by the 32·bit register. It
is possible to connect S2809 circuits in series to drive
additional bits by use of the Data Output.
CI~k Input
The Clock Input is used to clock data serially into the
32·bit shift register. The signal at the Clock Input may
be continuous, since the shift register is clocked only
when a logic 1 level is applied to the Chip Select Input.
As indicated in Table 1, data is transferred from ON·1 to
ON on the negative transition of the Clock Input.

Invert Input
The Invert Input is used to invert the state of the out·
puts, if required. With a logic 0 level on this input, the
logic level of the outputs is the same as the data clock·
ed into the 32·bit shift register. A logic 1 level on the In·
vert Input causes all outputs to invert.
This input may also be used when driving liquid crystal
displays, as shown in Figure 5.

Data Input
Whenever a logic 1 level is applied to the Chip Select In·
put, data present at the the Data Input is clocked into
the 32·bit master·slave shift register. Data present at
the input to the register is clocked into the master ele·
ment during the logic 1 clock level and thus must be
valid for the duration of the positive clock pulsewidth.
This information is transferred to the slave section of
each register bit during the clock logic 0 level.

Data Output
The Data Out signal is a bufferered output driven byele·
ment 32 of the shift register. It is of the same polarity as
this last register bit and may be used to drive the Data
Input of another S2809. In this manner, S2809 circuits
may be cascaded to drive additional bits.
Table 1. Logic Truth Table

Chip Select
The Chip Select Input is used to enable clocking of the
shift register. When a logic 1 level is applied to this in·
put, the register is clocked as described above. During
this time, the output buffers are not driven by the
register outputs, but wi II be driven to the logic level pre·
sent at the Invert Input. With a logic 0 level at the Chip
Select Input, clocking of the register is disabled, and
the output buffers are driven by the 32 shift register
elements.

X
X
X
X
0
1
0
1

....

:0::

cc
....
cc
CI

a.~
zw
u en

X
X
X
I
I
I
I

....

-'
u

II:
W

>
!:

0
0

0
1
1
1
1

1
X
X
X
X

1
1

c:r

11:::1
c:lQ

0
0

ffi!;

...

NO CHANGE

o
1

ON-1-QN
ON-1-0N
ON-1-0N
ON -1-0N

1
ON
ON
0

Figure 1. Typical D!splay Intensity Control

VTH-~
.

VTH VSS -4"VTH 'VSS -7

I"----JI

f\. - - - f\. - - _ f\. - - _
--.J
"--.:..J ~

----..\

~ SEGMENT OFF

LSEGMENTON

5.34

V2(WITHLARGERC)
FULL BRIGHTNESS
V2 (WITH SMALL RC)
30% FULL BRIGHTNESS

0
1
1

52809
Figure 2. LED Drive - Series

Figure 3. LED Drive - Shunt

______ .J

Figure 4. Vacuum Fluorescent Drive

Figure 5. Liquid Crystal Drive

•

-------,

------l

______ .J

Figure 6. Clock Input Waveform

Physical Dimensions

PIN I IDENTIFIER

TON
0.06~

0.040

DATA~VAlIO_---t·~I··_OONT _ ~
IN

CARE~

5.35

AMII.---------~

A Subsidiary
of Gould Inc.

Advanced Product Description

82600/82601

ENCODER/DECODER
REMOTE-CONTROL 2-CHIP SET

Features

o
o
o

Small Parts Count - No Crystals Required
Easily Used in LED, Ultrasonic, RF, or Hardwire
Transmission Schemes
Very Low Reception Error
Low Power Drain CMOS Transmitter for Portable
and Battery Operation
Block Diagram
52600 Encoder ,:

KfyBtlAIIDIflPUTS
DE F G HI
:

7) (I)

J
13

o
o
o
o
o

31 Commands - 5-bit Output Bus With Data Valid
3 Analog (LP Filterable PWM) Outputs
Muting (Analog Output Kill/Restore)
Indexing Output - 2V2 Hz Pulse Train
Toggle Output (On/Off)
MaSk-Programmable Codes
Pin Configuration
52600

K
14)

16·PIN PLASTIC DIP
GNO=V
SS

TEST

KEY

BOARD

INPUTS

:"1
+V:VOD

Block Diagram
52601 Decoder

Pin Configuration
52601

(11)

22 PIN PLASTIC DIP
+V=Vss

POR

!T:':~
SIGNAL INPUT

VOO=GND

DATA
VAlli

5.36

82600/82601
Functional Description
The 82600/82601 is a set of two L81 circuits which
allows a complete system to be implemented for
remote control of televisions, toys, security systems,
industrial controls, etc. The choice of transmission
medium is up to the user and can be ultrasonic, infrared
radio frequency, or hardwire such as twisted pair or
telephone.
The use of a synchronizing marker technique has
eliminated the need for highly accurate frequencies
generated by crystals. The 82600 Encoder typically
generates a 40kHz carrier which it amplitudemodulates with a base-band message of 12 bits, each
bit preceded by a synchronizing marker pulse.
Bits 1 and 12 denote sync and end-ot-message, respectively, bits 2 thru 6 constitute a fixed preamble which
must be received correctly for the command bits to be
received, and bits 7 through 11 contain the command
data. The 82601 Decoder produces an output only after
two complete, consecutive, identical, 12-bit transmissions. Marker pulses, preamble bits, and redundant
transmissions, have given the 82600/82601 system a
very high immunity to noise, without a large number of
discrete components.
82600 Encoder
The 82600 is a CMOS device with an on-chip oscillator,
11 keyboard inputs, a keyboard encoder, a shift
register, and some control logic. The oscillator requires
only an external resistor and capacitor, and to conserve
power, runs only during transmission. Keyboard inputs
are active-low, and have internal pull-up resistors to
Voo. When one keyboard input from the group A
through E is activated with one from the group F
through K, the keyboard encoder generates a 5-bit
code, as given in the table entitled "82600/52601
CODING," below. This code is loaded into a shift
register in parallel with the sync, preamble, and end
bits, to form the 12-bit message.
The transmitter output is a 40 kHz square wave of 50%
duty factor which has been pulse-code-modulated by
(Le., ANDed with) a signal having a recurring pattern, a
bit frame of 3.2 millisecond duration. This bit frame is
comprised of three signals: the 8tart Signal which is 0.4
milliseconds of logic "1"; followed by the Data signal
which is 1.2 milliseconds of the lowest-order shift
register bit; followed by the Mark Signal which is 1.6
milliseconds of logic "0" (except in the first bit frame
where Mark = 1 to facilitate receiver synchronization).
5.37

The shift register is clocked once per bit frame, so that
its 12-bit message is transmitted once in a 38.4 milliseconds. The minimum number of transmissions that
can occur is two, but if the keyboard in,J>uts are active
after the first 3.6 milliseconds of any 12-bit transmission, one more 12-bit transmission will result. Transmissions are always complete, never truncated, regardless of the keyboard inputs.
The Test input is used for functional testing of the
device. A low level input will cause the oscillator frequency to be gated to the Data Output pin. This input
has an internal pull-up resistor to VD00
82601 Decoder
The 82601 is a PM08 L81 device with an on-chip oscillator, five keyboard inputs, a 40kHz signal input, and 11
outputs. The oscillator requires only an external Rand
C. The five keyboard inputs are active-low with internal
pull-up resistors to Vss; activation of any two causes
one of 10 possible 5-bit codes to be generated and fed
to the outputs of the 82601, overriding any 40kHz signal
input.
Two counters, the signal counter and the local counter,
are clocked respectively by the signal input and a
40kHz signal from the local RC oscillator timing chain.
A 40kHz input lasting 3.2 milliseconds (Le., an initial bit
frame) causes the signal counter to overrun and reset
both itself and the local counter. At specific intervals
thereafter, the local counter generates pulses used to
interrogate the contents of the signal counter. Resynchronization of the counters occurs every bit frame so
that the interrogation yields valid data bits even if the
transmitter oscillator frequency has deviated up to
± 24 % with respect to the receiver osc iIIator freq uency.
Decoded data bits from the next five bit frames following the initial synchronizing frame are compared with
the fixed preamble code. The next five decoded bits,
the command bits, are converted to a parallel format
and are compared against the command bits saved
from the prior transmission. If they match, and if the
preamble bits are correct, the command bits are gated
to the receiver outputs. However, a mismatch causes
the receiver outputs to be immediately disabled, and
the new command bits are saved for comparison
against the command bits from the next 12-bit transmission. In the case where 2 identical, proper, 12-bit
transmissions are immediately followed either by
transmissions with erroneous preamble codes or by

•

S2600/S2601
provide 64 distinct DC levels suitable for control of
volume, color saturation, brightness, motor speed, etc.
Each Analog Output increases its duty factor in
response to a particular Binary Output code and
decreases its duty factor in response to another
code-6 codes in all. The entire range of 0% to 100%
duty factor can be traversed in 6.5 seconds or at a rate
of the oscillator frequency divided by 212. All three
Analog Outputs are set to 50% duty factor whenever
01011 appears at the Binary Outputs. Analog A is
mutable; 01100 sets it to 0% duty factor. If 01100 then
disappears and reappears, the original duty factor is
restored: This of course implements the TV "sound
killer" feature.

nothing, the receiver outputs will be activated during
the end-frame of the second transmission, and wi" be
disabled 45 milliseconds thereafter. In the rest (disabled) state the five Binary Outputs are at a "1" logic level;
when not in the rest state, one or more of the opensourced output transistors will conduct to VDD. The
Data Valid outP!Jt is low during the rest state, and high
whenever data is present at the Binary Outputs.
The 82601 has five other outputs: Pulse Train, On/Off,
Analog A, Analog B, and Analog C. The states of these
outputs are controlled by the 10 particular Binary Output codes which the receiver Keyboard Inputs can
cause to be generated. The Pulse Train output provides
a 2.44Hz square wave (50% duty factor) whenever 11011
appears at the Binary Outputs, but otherwise it remains
at a logic "0". This pulse train can be used for indexing,
e.g., for stepping a TV channel selector.
The On/Off ("mains") output changes state each time
01111 appears at the Binary Outputs. In TV applications
the On/Off output is most often used to kill and restore
the main power supply.
Analog Outputs A, Band C are 10kHz pulse trains
whose duty factors are independently contro"able.
With a simple low-pass filter each of these outputs can
Message Bit Format

The 82601 has an on-chip power-on reset (POR) circuit
which sets the Pulse Train and On/Off Outputs to "0",
sets the Analog Outputs at 50% duty factor, and insures that Analog A is muted. No external components
are required to implement POR, but a POR input has
been provided for applications where externally controlled reset is desirable, e.g., where the power supply
voltage rise time is extremely slow. The POR input has
an internal resistor pull-up to Vss; pulling it low causes
a reset.

:~: 16AoSLcT4~LA~ ~ s l-:;:;~~ig~jfj~J~,~~ ~: :1----------;-~:~:::~~;- ---- ---I
]

(PREAMBLE OR COMMAND I

1 + - - - - 1.2 msec

1.0 msec - - - - - - - . .

48 CLOCKS

3,2 moec
64 CLOCKS
TYPICAL - - - - - - - - - - - - - . .

*
**

12B CLOCKS/BIT
(TYPICAL CARRIER = 40kHzI
"I" MEANS PRESENCE OF A 40kHz CARRIER (SQUARE WAVEI; "0" MEANS ABSENCE OF A 40kHz CARRIER (SDUARE WAVEI,

IF MESSAGE BIT" "I" THEN OECOOER DATA OUTPUT" ENCODER DATA INPUT = "0";
IF MESSAGE BIT" "0" THEN DECODER DATA OUTPUT = ENCODER DATA INPUT = "I"

Message Format

FIRST PREAMBLE BIT = 0
INPUT KEYED

-~-----------~

S~M

~ =
M

DON'T CARE

S 0

STARTED HERE ' "
KEY INPUTS I
PRESSEOO1...J..k:'~=~
OSC

RUN +---+--{f+---f)4.----1--~I__-....... ~+_-~
HALT

OECODE OUTPUT DATA
40kHz
TRANSMITTED MESSAGE

4-----h
SYNC
BIT

5 BITS OF
PREAMBLE

COMMAND

f4-----MESSAGE ONE

10+---------

5.38

BIT

--------<.+-01--- MESSAGE TWO
76.8msec
TYPICAL

---------~

AMII.-------------.....

A Subsidiary
of Gould Inc.

Advanced Product Description

82604/82605

ENCODER/DECODER
REMOTE-CONTROL 2-CHIP SET

Features

o
o

Accurate Data Transmission - No Frequency
Trimming Required
Easily Used in LED, Ultrasonic, RF, or Hardwire
Transmission Schemes
Very Low Reception Error
Block Diagram
82604 (~~ ;)(~lG01~"21:31~)

Low Power Drain CMOS Transmitter for Portable
and Battery Operation
18 Commands-5-bit Output Bus with Data Valid
Analog (LP Filterable PWM) Output
Muting (Analog Output Kill/Restore)
Toggle Output (On/Off)
Mask-Programmable Codes

o
o
o

Pin Configuration
CERAM
OSCILLATOR

_ _ (8)VIIO=+V

(3)

52604
CMOS
16·PIN PLASTIC OIP
GNOoVSS

(16)

~~~UT

aSCTEST

13 - J

12 -

(

o -

E -

10 -G

9 _

-Z'AMD
DECODE

SYNC

DATA OUTPUT

14 -

+V=Voo

FRAME

KEY

BOARD
INPUTS

,os.

CONTROL

Block Diagram

Pin Configuration

52605

PMOS

OSC

22-PINPLASTIC OIP

(11)

+V=Vss
LOCAL
KEYBOARD
INPUTS

ANALOG OUT
ON/OFF

POR

DATA VALID
NC
18

1
3

INPUTS

S
4
2

TEST

}"""

OUTPUTS

SIGNAL INPUT
Voo= GND

(9)

(19)

PUlSEOHIOFF
T~AIN

(20)

(18)(14) (17) (15) (16)

ANALOG A
BlNAHYOUTPUTS

(3(

VALID

5.39

82604182605
after the first 3.6 milliseconds of any 12-bit transmission, one more 12-bit transmission will result.
Transmissions are always complete, never truncated,
regardless of the keyboard inputs.
The 82604 Encoder is, however, silenced automatically
by an on-chip duration limiter if a transmission persists
for 6112 seconds (F08C = 320kHz). The absence of a
keyboard closure will reset the duration limiter so that a
new 6112 second interval starts with the next key
closure.

Functional Description
The 82604/82605 is a set of two L81 circuits which
allows a complete system to be implemented for
remote control of televisions, toys, security systems,
industrial controls, etc. The choice of transmission
medium is up to the user and can be ultrasonic, infrared
radio frequency, or hardwire such as twisted pair or
telephone.
The use of a ceramic resonator with the 82604 Encoder
eliminates the need to trim the 82605 decoder
oscillator.
The 82604 Encoder typically generates a 40kHz carrier
which it amplitude-modulates with a base-band message of 12 bits, each bit preceded by a synchronizing
marker pulse.
Bits 1 and 12 denote sync and end-of-message, respectively, bits 2 through 6 constitute a fixed pream~le
which must be received correctly for the command bits
to be received, and bits 7 through 11 contain the command data. The 82605 Decoder produces an output only
after two complete, consecutive, identical transmissions. Marker pulses, preamble bits, and redundant
transmissions, have given the 82604/82605 system a
very high immunity to nOise, without a large number of
discrete components.

82605 Decoder
The S2605 is a PM08 LSI device with an on-chip oscillator, five keyboard inputs, a 40kHz signal input, and 8
outputs. The oscillator requires only an external Rand
C. The five keyboard inputs are active-low with internal
pull-up resistors to Vss; activation of any two causes
one of 10 possible 5-bit codes to be generated and fed
to the outputs of the 82605, overriding any 40kHz signal
input.
Two counters, the signal counter and the local counter,
are clocked respectively by the signal input and a
40kHz signal from the local RC oscillator timing chain.
A 40kHz input lasting 3.2 milliseconds (Le., an initial bit
frame) causes the signal counter to overrun and reset
both itself and the local counter. At specific intervals
thereafter, the local counter generates pulses used to
interrogate the contents of the signal counter. Resynchronization of the counters occurs every bit frame so
that the interrogation yields valid data bits even if the
transmitter oscillator frequency has deviated up to
± 24% with respect to the receiver oscillator frequency.
Decoded data bits from the next five bit frames following the initial synchronizing frame are compared with
the fixed preamble code. The next five decoded bits,
the command bits, are converted to a parallel format
and are compared against the command bits saved
from the prior transmission. If they match, and if the
preamble bits are correct, the command bits are gated
to the receiver outputs. However, a mismatch causes
the receiver outputs to be immediately disabled, and
the new command bits are saved for comparison
against the command bits from the next 12-bit transmission. In the case where 2 identical, proper, 12-bit
transmissions are immediately followed either by
transmissions with erroneous preamble codes or by
nothing, the receiver outputs will be activated during
the end-frame of the second transmission, and will be
disabled 45 milliseconds thereafter. In the rest (disabled) state the five Binary Outputs are at a "1" logic level;
when not in the rest state, one or more of the opensourced output transistors will conduct to VDD. The
Data Valid output is low during the rest state, and high
whenever data is present at the Binary Outputs.

82604 Encoder
The 82604 is a CM08 device with an on-Chip oscillator,
9 keyboard inputs, a keyboard encoder, a shift register,
and some control logic. The oscillator uses an external
ceramic resonator, and to conserve power, runs only
during transmission. Keyboard inputs are active-low,
and have internal pull-up resistors to VDD . When one
keyboard input from the group C through E is activated
with one from the group F through K, the keyboard encoder generates a 5-bit code, as given "in the table entitled "S2604/S2605 CODING," below. This code is loaded
into a shift register in parallel with the sync and end bits
to form the message.
The transmitter output is a 40kHz square wave of 50%
duty factor which has been pulse-code-modulated by
(Le., ANDed with) a signal having a recurring pattern, a
bit frame of 3.2 millisecond duration. This bit frame is
comprised of three signals: the 8tart signal which is 004
milliseconds of logic "1"; followed by the Data signal
which is 1.2 milliseconds of the lowest-order shift
register bit; followed by the Mark signal which is 1.6
milliseconds of logic "0" (except in the first bit frame
where Mark = 1 to facilitate receiver synchronization).
The shift register is clocked once per bit frame, so that
its 12-bit message is transmitted once in 38.4 milliseconds. The minimum number of transmissions that
can occur is two, but if the keyboard inputs are active
5040

82604182605
ticular Binary Output code and decreases its duty factor in response to another code. The Analog Output is
mutable; 11110 sets it to 0% duty factor. If 11110 then
disappears and reappears while the On/Off output is
"On", the original duty factor is restored. This of course
implements the TV "sound killer" feature.
The 52605 has an on-chip power-on reset (PaR) circuit
which sets the On/Off Outputs to "0", sets the Analog
Outputs at 50% duty factor, and insures that Analog is
not muted. No external components are required to implement paR, but a paR input has been provided for
applications where externally controlled reset is
desirable, e.g., where the power supply voltage rise
time is extremely slow. The paR input has an internal
resistor pull-up to Vss; pulling it low causes a reset.

The 52605 has two other outputs: On/Off, and Analog.
The states of these outputs are controlled by the 10 particular Binary Output codes which the receiver Keyboard Inputs can cause to be generated.
The On/Off ("mains") output changes state each time
10011 appears at the Binary Outputs. In TV applications
the On/Off output is most often used to kill and restore
the main power supply.
The Analog Output is a 10kHz pulse trains whose duty
factors are independently controllable. With a simple
low-pass filter each of these outputs can provide 64
distinct DC levels suitable for control of volume, color
saturation, brightness, motor speed, etc. Each Analog
Output increases its duty factor in response to a par-

•

Message Bit Format

:*]

~
*

START
ALWAYS
= 1

04msec
16
..

~LOCKS

MARK
1 IN SYNC BIT

.DECODER DATA OUTPUT
1 IN SYNC AND END BITS
TRANSMITTED DATA IN FRAMES
2 THRU 11
(PLACE-HOLDER OR COMMAND)
~---

= 0 OTHERWISE

1.2 msec - - -........- - - - - 1.6 msec - - - - - - i..~

48 CLOCKS
3.2 msec
64 CLOCKS
- - - TYPICAL -------------t~
128 CLOCKS/BIT
(TYPICAL CARRIER = 40kHz)

"1" MEANS PRESENCE OF A 40kHz CARRIER (SQUARE WAVE); "0" MEANS ABSENCE OF A 40kHz CARRIER (SQUARE WAVE).
IF MESSAGE BIT = "1" THEN DECODER DATA OUTPUT = ENCODER DATA INPUT = "0";
IF MESSAGE BIT = "0" THEN DECODER DATA OUTPUT = ENCODER DATA INPUT = "1".

Message Format
FIRST PREAMBLE BIT
INPUT KEYED
~ D
STARTED HERE " \
KEY INPUTS 1
PRESSED 0
OSC
RUN
HALT
DECODE OUTPUT DATA
TRANSMITTED MESSAGE

40kHz
0

0
M

T
-<

S D

SYNC
BIT

PLACE-HOLD

S D

DON'TeARE

S D

5 BITS OF
COMMAND

END
BIT

L
SYNC
BIT

J'~ r--

5 PLACE-HMo
BITS & 5
COMMAND BITS
MESSAGE TWO

MESSAGE ONE
76.Bmsec
TYPICAL

5.41

OUTPUT
DATA =1

OUTPUT
DATA =0

L...,f- ~f- ~

--<

\
S D

END
BIT

82604/82605
52604/52605 Coding
TRANSMITTER KEYBOARD INPUT
PINS TIED TO Vss

RECEIVER KEYBOARD INPUT PINS
TIED TO Voo (Note 1)

- (Note 2)
DI
CF
DF
EF
CG
DG
EG
CH
DH
EH
EI
EJ
CI
CJ
CK
EK
DK
DJ
INVALID (Note 3)

RESULTING RECEIVER BINARY
OUTPUTS
2
1
3
4
1

0
0

1
1
1
1
1
1

1
1
1
1
0
0
0
0
1

1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
0

0
0

0
0
0

0
0
0
1

AE
BE
A
B
E
C
D
EC

1
0

1
1
1
1

1
1
1

0
0
0

0
1
1

AC
BC

1
0
0
0

1
1
0

1
0
1
0
1

0
1
0
0
0
0
1
0
1
1
0

0
0

1
0

RECEIVER
DEDICATED FUNCTIONS

INCREASE ANALOG (Note 5)
DECREASE ANALOG (Note 5)
MUTE TOGGLE (Note 4)
TOGGLE ON/OF OUTPUT
(Note 3)
INCREASE ANALOG (Note 5)
DECREASE ANALOG ~Note 5)

NOTES:
1. RECEIVER KEYBOARD INPUTS OVERRIDE ANY REMOTE SIGNAL.
2. REST STATE, "DATA VALID" OUTPUT INACTIVE

3. ANY SINGLE CLOSURE, INVALID COMBINATION OF 2 CLOSURES, OR COMBINATION OF 3 OR MORE CLOSURES OF S2604 TRANSMITTER INPUTS C, D, E, F,

4. THE MUTE TOGGLE WILL FUNCTION ONLY WHEN THE "ON/OFF" OUTPUT IS ON. HOWEVER MUTE IS CLEARED BY TURNING "ON/OFF" OFF,
THEN ON AGAIN.
5. THE PULSEWIDTH OF THE ANALOG OUTPUT MAY BE CHANGED ONLY WHEN THE "ON/OFF" OUTPUT IS ON.

Electrical Specifications-2604 Encoder- All voltages measured with respect to Vss
Absolute Maximum Ratings
Operating Ambient Temperature TA ............................................................ a to + 7aoe
Storage Temperature .................................................................. - 65°e to + 15aoe
Positive Voltage on any Pin ....................................................................... " + 14V
Negative Voltage on any Pin .................................................... , ................ " - a.3V
Electrical Characteristics: Unless otherwise noted, Voo = 8.5 ± 1.5V and TA = a to
Symbol

Parameter

Min.

Typ.

Max.

Units

320

2000

kHz

JA
%VDD

%VDD

+ 7aoe.
Conditions

Oscillator Frequency

IDO

Supply Current

VIH
VIL

Input" 1 " Threshold

ILL

Input Source Current

JAA

VI = OV

IOH

Output Source Current

1.5

IOL

Output Sink Current

-.2

-.5

Va = VDD -3V
Vo=+0.5V

Standby
20

Input "0" Threshold

300

Note: Circuit operates with VDD from 3.0V to 12.0V.

5.42

During Transmission,
Data Output = 1mA
No transmission (25°C)

82604182605
Electrical Specifications-2605 Decoder-All voltages measured with respect to Voo
Absolute Maximum Ratings
Operating Ambient Temperature TA ............................ '" ....... '" ................... aoe to 7aoe
Storage Temperature ................................................................ " - 65°e to + 15aoe
Vss Power Supply Voltage ....................................................................... " + 31V
Positive Voltage on any Pin .................................................................... Vss + a.3V
Negative Voltage on any Pin ........................................................ , ........... Vss - 31V
Electrical Characteristics: Unless otherwise noted, Vss
Symbol

Parameter

fO
afO/fO
Iss

Supply Current

=12 ± 2V and TA =a to + 7aoe.

Min.

Typ.

Oscillator Frequency

512

640

Frequency Deviation

-10
34

Max.

Units

768

kHz

Conditions

+10

Fixed Rose, Cose, Vss

No Loads, Voo = 14V

Voo = 10V

28
Signal Input:
VIH
V1L

"1" Threshold
"0" Threshold

Voltage Hysteresis
VIWV 1L
Keyboard and POR Inputs:
VIH
V1L

"1" Voltage

ILL

Source Current

%Vss

5
Vss -.5
50

Vss - 3.0

"0" Voltage
Debounce Delay
(Keyboard Inputs Only)

85
30

150

1.45

Vss - 5.5

300

/AA
msec

2.2

VI = Vss -10V

Binary Outputs (open source):
IOL

Sink Current

-0.7
-0.50

Duration

mA
-0.60

34.9

msec

Vo = Vss - 5.2V, Vss = 16V
Va = Vss - 5.2V, Vss = 10V
fO = 704 kHz

Analog Output (open drain):
aVstep

Step Voltage Change

IOH

Source Current

Vss /64
1.04

Va=Vss-0.5V, Vss=10V

1.15

Va=Vss-0.5V, Vss=14V

1.2

Va = Vss -1V

kHz

(fO -+- 64)

1.5

Vo = Vss - 2V

-30

-50

/AA

Va = .7V

1.0
fstep

Analog Step Rate

Data Valid and On/Off Outputs:
IOH

Source Current

IOL

Sink Current

Risetime (.1 Vss to .9 Vss )

Falltime (.9 Vss to .1 Vss )
tf
Note: Circuit operates with Vss from 7.0V to 30.0V

5.43

/Asec

RL =

00,

CL 50pF

/Asec

RL =

00,

CL 50pF

82604/82605

Typical Bench Test Setup, Using a 320kHz Ceramic Resonator with S2604

Voo

usc
OUT
DSC
IN

+V=10 TO 14 VDC

27K

lMEG

~ ~Of----.
T150PF

+1,C2

50pF

r220PF

r---L

DATA 16
OUT

13 J

I
I

TRANSMISSION
MEmUM

~KIA
,,~ KIB

,,~

).,..

B03 17
15
B04
16
B05

paR

13 SIG
IN

VSS

BOI 18
B02 14

--H,,,!.

KEYBOARD

VSS

121
14 K

33K

~ ,~

~RC

E
9 F AMIS2604
10 G
OSC ..!!...NC
TEST
11 H

DATA
WORD

DV 3
AMIS2605

0/0

~KIC

ANA

5 KID

DATA VALID

21
r------.TOGGLE FOR POWER CDNTRO
R3

4 KIE
VOU
12

RIP PLE ON FILTER OUTPUT 10mV p.p USING R2=10K, R3=100K, C3=0.47"F, VsS=14VDC
C, , C2, AND Cp OPTIONAL
KEYBOARD

5.44

ft,

J
'T

LOW·PASS
FILTER

OCLEVEL
FOR ANALOG
CDMTROL
e.g., VOLUME,
BRIGHTNESS,
COLOR SAT.

AMII.---------."""'4.

A Subsidiary
of Gould Inc.

S27 431S27 42

ENCODER/DECODER
REMOTE CONTROL 2-CHIP SET

Features
D RC Oscillator Used-No Crystal Required
o .Phase Locked Loop on Decoder for Reliable
Operation
D 512 User Selectable Address Codes
D Encoder Operates on a Single Rail 9 Volt Supply Suitable for Inexpensive and Convenient Battery
Operation
D User can Determine the Type of Transmission
Medium to Use

Applications
D Entry Access Systems
o Remote Engine Starting for Vehicles and Standby
Generators
D Security Systems
D Traffic Control
D Paging Systems
D Remote Control of Domestic Appliances
Pin Configuration 2743

Block Diagram 2743 Encoder
,------------ev"
,----------_OUTPUT

CONTHOI
lOGIC

•c
OSCILLATOR
- - -.... RIC

...-------_.voo

,-L_===============-===;------.

TEST

TOP VIEW

Block Diagram 2742 Decoder

Pin Configuration 2742

OUTPUT

_Vss
BIT
DECODE

VSS

ONE-SHOT HC

OUT

ONE SHOT

ICOINPUT

CAP

'OP

CAP

_Voo

BITS

ICOCAP

1-9

• PHASE OUTPUT

VCOUP

SIGUP

VOO

SIGNAL INPUT
TOP VIEW

5.45

•

52743/52742
twice the one-shot period. The one-shot can be used to
prevent the output from switching on and off too rapidly
due to system noise. The typical RC components
shown in the block diagram give a period of about one
second.

General Description- Encoder/Decoder
This two-chip PMOS set includes a user-programmable
serial data encoder for use in a simple low-power transmitter and a serial data decoder for use in a user
addressable receiver. The user can select the transmission medium (RF, infrared, or hardwire). The externally
selectable message allows up to 512 codes or addresses; this is done with the nine binary inputs on each
device. An additional 3 bits of address can be programmed on chip as a fixed preamble.

Functional Description-Serial Data Encoder
The AMI serial data encoder is comprised of three sections: Oscillator, Programming Logic, and Control
Logic. Specifically it will provide logical ones "1 ",
logical zeroes "0", and synchronization pulses "s" and
arrange them into a trinary data pattern composed of 16
data bits. Each data bit will be 32 cycles of the high frequency (HF-1/2 Oscillator Frequency) in length. Each
trinary data pattern will be 512 cycles of 1/2 the
Oscillator Frequency length.

The serial data encoder encodes by means of a
frequency-shift-keyed trinary data pattern composed of
16 data bits. Each data bit will have a length equivalent
to 32 cycles of high frequency clock (20kHz typical).
Each trinary data pattern will be 512 cycles of 1/2 the
oscillator frequency length. The encoder frequency
oscillator reference is controlled with an external RC
network. The encoder transm itter can be powered by a
single 9 volt battery so that a single momentary push
button will activate the encoder and transmitter. In the
off position there is no current flow.

A logical "1" is represented by 32 cycles of the high
frequency.
A logical "0" is represented by 16 cycles of the high frequency followed directly by 8 cycles of the low frequency (LF = 1/2 HF).

The serial data decoder in conjunction with a receiver
amplifier decodes the transmitted 16-bit coded signal.
The on-chip phase-locked-loop locks in on the 20kHz
signal even if the transmitted frequency differs from
the receiver by up to ± 15%. The coded signal input is
compared with the externally selected code. The serial
decoder looks at the transmitted signal a minimum of
three times before validating a good message. A 3-bit
"good" code counter or a 3-bit "bad" code counter
accumulates the number of successive good and bad
codes being received.

A synchronization pulse "s" is represented by 16 cycles of the low frequency.
A 16-bit data pattern will be encoded in the device in
such a manner as to have three (3) bits programmed internally and nine (9) bits programmed externally.
The Oscillator Frequency equals twice that of the High
Frequency, and the High Frequency equals twice that
of the Low Frequency.
The Oscillator circuit will require a maximum of three
(3) external components.

The decoder has an on-Chip one-shot which is user programmed by an external RC combination. Whenever
three complete good codes are received in the "good"
counter a signal enables the one-shot which controls
the signal valid output. If a series of three sequential
bad codes enter the "bad" code counter the "bad"
counter resets the "good" code counter and one-shot
period and will not allow an active output until the end
of the one-shot period. Any "good" code resets the
"bad" code counter. If the "good" counter has accumulated three good codes and activated the output one
shot, any occasional "good" code (occurring within the
one-shot period) will maintain the output by retriggering the one-shot. The output appears like a single
switch, on when "good" codes are received, off when
not, with the minimum total period being determined by

External programming inputs connected to the device
- Voo supply will be considered as a logical "1". The
bit programming current will not exceed 50~. The programming resistance should not exceed 1kQ. Unconnected external bit programming inputs will be considered at a logical "a".
A "1" (-5V~ "1" ~ VOD) presented to the "Test" input
sets the Internal counter and maintains the output of
the device "On." The input impedance of the test input
is greater than 5MQ.
For portable operation a 9V transistor battery can be used for the DC voltage supply. Proper circuit polarity
must be observed ( - VOD , + Vs s ).
5.46

S2743/S2742
82743 Absolute Maximum Ratings
DCSupplyVoltage ................................................................................. -15V
Input Voltage ....................................................................... Vss + .3VtoVss -15V
Operating Temperature Range ........................................................... - 40°C to + 100°C
Storage Temperature Range ............................................................. - 65°C to + 150°C
Lead Temperature (During Soldering) ................................................... 300°C for Max. 10sec.
82743 Electrical Characteristics (25°C Air Temperature Unless Otherwise Specified)
Symbol

Parameter
Operating Supply Voltage

Typ.

Max.

- 6.65

-9.5

-15

- 8V, - 5mA, Max.

kHz

Oscillator

J-tA

Programming Input,
R 1kQ

Bits 1-9

VDD

Operating Power Dissipation
Operating Frequency

Programming Bits 1-9, Current
External Programming Resistance
(DC Bits 1-9) Program Logical "1"

Vss - 5V

Input Levels Logical "0"

Vss -1V

Units

Conditions

Min.

VDD ; Vss = OV

Vss

V
Input R 9V>1.5M @ 5V

J-tA
MQ

(DC) Test Input Levels Test ON

Vss - 5V

VDD

Maintains Output Device
ON

Test OFF (See Note 1)

Vss -1V

Permits Normal Operation
Resistance to VDD ,
±20%

Bits 1-9 Current

Test and R+ C Input Impedance

Vss

R, C Resistance Logical" 1"

R, C Resistance Logical "0"
(See Figure 1)

Resistance to Vss
+ 20% - 30%

Output Voltage = .8V
W/VDD = -7V

Output Current (See Note 2)
Notes: 1. Effect noted at Pin 15 to vss.

2. Output Voltage Pin 15 to vss.

Figure 1. Serial Data Encoder

3. All Voltages measured with respect to Vss.

OSCILLATOR INPUT
OIAGRAM
ALL INTERNAL RESISTANCE
+20%

TO CONTROL LOGIC

13
Rl

•

5.47

AMI.---------.""4.

A Subsidiary
of Gould Inc.

82747182748

ENCODER/DECODER
REMOTE CONTROL 2-CHIP SET

Features
o RC Oscillator Used- No Crystal Required
o 512 User Selectable Address Codes
o Low Power CMOS Encoder Operates on a Single
Rail 9 Volt Supply
o Low Power CMOS Decoder Operates on a Single
Rail 12 Volt Supply

Applications
o Entry Access Systems
o Remote Engine Starting for Vehicles and Standby
Generators
o Security Systems
o Traffic Control
o Paging Systems
o Remote Control of Domestic Appl iances

Block Diagram 2747 Encoder

Pin Configuration 2747

Voo

S9
DETECT/TEST

S6
R,

OUT

Vss

DETECT/TEST

EXTERNAL
PROGRAMMING
lOGIC

Block Diagram 2748 Decoder

Pin Configuration 2748

DATA - _ - - - - - , - - - - - - - - - ,

OUTPUT OS

BIT
DECODE

DETECT
OUTPUT

5.48

Voo

OUTPUT

DATA INPUT

DATA ENTR. D.S.

Vss

DATA FRAME O.S.

82747/82748
10-bit message (40 oscillator periods) has elapsed,
there will be an equivalent period of silence (Logic "0")
output from the encoder, as mentioned previously.

General Description - Encoder/Decoder
This two-chip CMOS set includes a user-addressable
serial data encoder for use in a simple low-power transmitter and a serial data decoder for use in a useraddressable low-power receiver. This chip set may be
used with a variety of transmission media (RF, infrared,
or hardwire). Up to 512 codes or addresses are externally
selectable; this is done with the nine binary inputs on
each device.

The marker bit is equivalent to a data bit with a value of
Logic "1".
The RC oscillator circuit requires a maximum of three
external components (see Figure 1). To directly drive
the oscillator, let encoder Pins 3 and 4 float, and apply
the direct drive signal to encoder Pin 5.

The serial data encoder outputs a train of ten pulses.
The first pulse is a "marker" bit used to signal the
decoder that a message is coming. The following nine
pulses represent the encoded nine bits of binary information. The duration of the pulses output from the encoder is determined by a simple RC clock network. The
encoder transmitter can be powered by a single 9-volt
battery so that a single momentary push button will
activate the encoder and transmitter. In the off position,
there is no current flow.

The typical R1, R2 , and C components shown in Figure 2
provide an oscillator frequently of about 1ms.
External programming inputs connected to the device
will be considered as a Logic "0". Unconnected external bit programming inputs are pulled up by the chip to
a Logic "1".
A Logic "1" applied to "test detect", Pin 2, resets the internal logic and forces the encoder output to a Logic
"0". After the "test detect" pin is back at a Logic "0",
the encoder output will be a Logic "0" for 40 RC oscillator clock periods, then the 10-bit message will begin.

The serial data decoder, in conjunction with a receiver
amplifier, decodes the transmitted signal. The coded
signal input is compared with the decoder's externally
selected address. The serial decoder looks at the transmitted signal a minimum of four times before validating
a good message and turning the receiver's detection
output on.

For portable operation, a 9V transistor battery with a 6V
zener diode may be used for the DC voltage supply.

Functional Description-Serial Data Decoder
The Serial Data Decoder is comprised of four sections:
Data Entry One-Shot, 9-8it Digital Comparator, Good
Detection Control Logic, and the Retriggerable Output
One-Shot.

The decoder has an on-chip output one-shot which is
user programmed by an external RC combination. This
one-shot is used to prevent the detection output from
switching on and off too rapidly due to system noise.

The Decoder is always on, looking for a "marker" pulse
from the encoder. When a pulse is detected at the data
input, the data entry one-shot clocks it into the first
stage of a 10-bit shift register, after a user-selectable
delay. As successive pulses are detected, they are similarly shifted into the shift register, with preceding shift
register information shifted over one bit. As the marker
bit is shifted into the tenth bit of the shift register, a
comparison is made with the first nine bits of shift
register information and the nine externally programmed address inputs. If a comparison is valid, a clock
pulse is sent to the good detection counter logic. As
mentioned in the Encoder Functional Description, a
message lasts 40 encoder oscillator clock periods followed by 40 encoder oscillator clock periods of DC
Logic "0". In the Decoder, it is necessary to clear the
10-bit shift register and associated logic after the message has been received and compared with the
Decoder's external address bits. This is done using the

Functional Description-Serial Data Encoder
The Serial Data Encoder is comprised of three sections:
Oscillator, Programming Logic, and Control Logic.
Specifically, it will provide a marker pulse and nine data
pulses. This 10-bit message will be output from the encoder, then a DC logic "0" pulse will be output for a
time corresponding to the length of the 10-bit message.
The encoder will continue to cycle the message and the
logic "0" silence period as long as power is applied to
it.
Each bit of the 10-bit message is four RC oscillator
periods wide. The format of each bit is the same. First, a
Logic "1" is output for one oscillator period. Then, the
data (or marker) value is output for the next two oscillator periods. Lastly, a logic "0" is output for one
oscillator period. Thus, Logic "1" for one period, data
for two periods, and Logic "0" for the last period. After a
5.49

•

82747182748
Figure 1. Serial Data Encoder RC Oscillator

rl> I h

It> I [>-, ·

-~---=---¢.---~---¢

TO """llome

1
'OSI

2.3CxR2
R1:::2 R2
UNITS: R1. R2 (MQ)
C (JJF)

one-shot decays to a Logic "0", the detect output will
remain off, the output one-shot will not be refreshed to
a Logic "1", and the good detection counter circuit will
be reset. Once the detect output is turned on by four
message detections in a single output one-shot period,
it requires only one message detection per output oneshot period thereafter to keep the detect output continuously turned on. If no message detection occurs in
a subsequent output one-shot period, the one-shot will
decay to a Logic "0", turn off the detect output and
reset the good detection counter circuit. The typical
RC components shown in Figure 2 give an output oneshot period of about one second.

data frame one·shot. The data frame one-shot provides
a user-selectable delay from the end of a message until
the shift register is reset. The typical RC components
shown in Figure 2 provide data frame one-shot pulse
width of about 10mS, while the components for the
data entry one-shot will generate a 2ms pulse width
clock delay during data entry.
The good detection counter circuit and the retriggerable output one-shot work together. Initially, as data
begins to enter the Decoder, the output one-shot is refreshed to a Logic "1"; the detect output is off. As the
output one-shot decays toward a Logic "0", the initial
message is compared with the nine external address
bits. If the comparison is true, a clock will increment
the good detection control circuit. If four such comparisons occur, the detect output will turn on and the
output one-shot will again be refreshed to a Logic "1".
If less than four comparisons occur before the output

Also note that a logic inversion must take place exter·
nal to the output of the Encoder before it is presented
to the data input of the Decoder. Figure 2 shows a typi·
cal circuit to accomplish this.

S2747 Encoder Absolute Maximum Ratings

DC Supply Voltage .................................................................. Voo +9V, Vss OV
Input Voltage .................................................................... Vss - 0.3V to Voo + 0.3V
Operating Temperature Range (Ambient) ................................................. - 35°C to + 85°C
Storage Temperature Range (Ambient) .................................................. - 55°C to + 150°C
Lead Temperature (During Soldering) ................................................. 300°C for Max. 10 sec.

5.50

AIMI.--------------."""4.
~

A Subsidiary
of Gould Inc.

Preliminary Data Sheet

S10110

ANALOG
SHIFT REGISTER

Features

General Description

D 185 Stage "Bucket Brigade" Delay Line

The S10110 analog shift register is a monolithic circuit
fabricated with P-Channel ion-implanted MOS technology. The part differs from a digital shift register, which
is capable of only digital input and output information,
in that an audio signal is typically supplied as the data
input to the analog register, and the output is the same
audio signal delayed in time. The amount of S i g n a l .
delay is dependent on the number of bits of delay (185)
and the frequency of the two symmetrical clock inputs.
_ ~
Since each negative-going clock edge transfers data
from one stage to the next, the analog signal delay
equa.ls 185 -+ 2 x clock frequency.

Delays Audio Signals

Accepts Clock inputs up to 500kHz

D Variable Delay
D Alternate to TCA 350

Pin Configuration

Block Diagram

DATA
OUT (6)

(3) DATA

---+__

(5)

~NLOCK

1 _ _--'--_ _

(2)

~LOCK

2 _ _ _ _ _----1._ _

(4)Vss_

(1)NC---

(7)VDD-

(8) N C - - -

5.51

CLOCK 2 IN

VDD

DATA IN

vss

S10110

DATA OUT
CLOCK 11N

810110
right. When Clock 2 is negative, data is transferred from
C1 to C2 and from each other odd-numbered capacitor
to the capacitor to its right. In this manner, data is
shifted from the input to C185 after a total of 185 negative clock pulses has occurred (Le., 93 periods of Clock
1 and 92 periods of Clock 2).

Operation
Device operation may be understood by referring to
Figure 1. This is an actual schematic diagram of the
analog shift register, or "bucket brigade," showing typical external bias techniques.
Data In Input:

Data Out Output:

The analog signal, or audio signal, to be delayed is applied to pin 3. This input must be biased to a negative
voltage of approximately - 8 volts, and two resistors
may be used as a voltage divider to provide this bias.
They must be chosen so that (R 1) ± (R 2) + (R1 + R2 ) is
less than 20kQ. The input signal applied to this input
through series capacitor CIN may be as high as 6 volts
peak-to-peak.

The output of the 510110 analog shift register is a
single device, T187, with its drain at Voo and its source
connected to pin 6. If a 47K resistor to Vss is supplied at
this pin, T187 functions as a source follower.
Referring to Figure 3, it can be seen that the output potential during Clock 2 is a constant value near - 10
volts. When Clock 1 switches on (negative), the output
instantaneously drops to a level of approximately - 30
volts; this is caused by the 20 volt swing of Clock 1 and
C185. As Clock 1 remains on, device T185 transfers
charge from C184 to C185, and the output voltage
becomes more positive, depending on the charge previously stored on C184. It is during this part of Clock 1
that the output reflects the analog data stored on C1
185 bits earlier. Since the clock signal now appears on
the output, it is necessary to apply the appropriate
filtering to obtain the delayed analog signal.

Clock 1 and Clock 2 Inputs:

Applied respectively to pins 5 and 2,Clock 1 and Clock
2 are two symmetrical non-overlapping negative-going
clocks used to transfer the analog data along the 185 bit
delay line. Although these clocks may have a duty cycle
as low as 25% (Le., each clock signal is at a negative
level for 25% of its period), better output signals will be
obtained with both clock duty cycles closer to 50%. It
is important, however, that no overlap of the clock
signals occurs at a level more negative than Vss - 0.8
volts.

Applications
D Delay of Audio Signals
D Rotating Speaker Simulation
D Electronic Chorus
D Electronic Vibrato
D String Ensemble
o Reverberation

Referring again to Figure 1, it can be seen that when
Clock 1 is negative, data is transferred from the data input to capacitor C1; likewise, data is transferred from
each even-numbered capacitor to the capacitor to its
Figure 1_ Schematic Diagram and Pinouts of S1 011 0

. - - - - - - - - - - - - - - - - - - - - - - - - - -...V;";""oOT--o-- -24 VOLTS

ANALOG
DATA

r-------------~~--

I-_~-o--+I--,

--:-l.
c.

!
L_

14 L!

T185

L....-+-O-_- DATA OUT

_ _______________ J

5.52

C
5

CLOCK 1
CLOCK2

810110
Absolute Maximum Ratings
Voltage on any pin relative to Vss ....................................................
Operating temperature range ..
Storage temperature (ambient)
o.

0.0

•••

•••••

••

•••

••

•••

•

••••••••••••••••••••

•••

••

•••••••

•

••••

•••••

••

•

••

••••

+ Oo3V to - 30V
ODC to + 70 DC

- 65 DC to + 150 DC

Electrical Characteristics
(ODCrilF F

CONTROL

N Inputs

are four each of the keys F, F#, G, G#, A, A#, and G.
This results in the requirement that each of the two
S10430 divider keyers in a system take two frequencies from the first group, and four from the second
group. Stating this another way, the N1, N2, N3, and
N4 inputs must have frequencies chosen from the
group, F, F#, G, G#, A, A#, B, and G. The N5 and N6 inputs are chosen from the group, G#, D, D#, and E. The
example in Figure 4 shows one divider keyer handling
the notes, A, A#, B, G, G#, and D while the other does
the keying for D#, E, F, F#, G, and G#.

Six of the twelve tempered scale frequencies are applied to the inputs N1 through N6. Typically, these frequencies would be six of the outputs of a top octave
synthesizer, such as an S50240. In general, it doesn't
matter which frequencies are applied to the N inputs,
although this affects which keyboard keys should be
connected to the K inputs. One exception to this
arises from the fact that a 44 note keyboard contains
more of some keys than others. Specifically, there are
only three each of the keys, G#, D, D#, and E, but there

5.57

S10430
Table 1: Relationship between K and N Inputs

INPUT

PIN NO.

OUTPUT (8' PITCH)*
PIN 32

INPUT

PIN NO.

OUTPUT (8' PITCH)*
PIN 32

K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11

36
37
38
39
2
3
4
5
18
17
16

N1+4
N1+8
N1 +16
N1 +32
N2+4
N2+8
N2+16
N2+32
N3+4
N3+8
N3+16

K12
K13
K14
K15
K16
K17
K18
K19
K20
K21
K22

15
23
22
21
20
13
12
11
7
8
9

N3+32
N4+4
N4+8
N4+16
N4+32
N5+4
N5+8
N5+16
N6+4
N6+8
N6+16

*To determine outputs for 4' pitch: multiply 8' pitch output by 2.
To determine outputs for 2' pitch: multiply 8' pitch output by 4.
To determine outputs for 16' pitch: multiply 8' pitch output by
causes the attack time to be about 1ms. If the sustain
is on (sustain switch open), when the keyswitch is
opened, the K input will charge slowly back to Vss
through the time constant of C1, R1, and R2. This
results in a sustain envelope of 271 ms. Longer sustains can be obtained with larger capacitors. If the sustain switch is closed, then the decay time is governed
by the time constant of C1, R2, and R311 R1. In this example, this non-sustain decay is about 3ms.

K Inputs
The twenty-two inputs are connected either directly to
key switches or to an attack/decay circuit, such as the
one shown in Figure 1. When a negative voltage is applied to any K input, four chopper keyer circuits are
turned on, and the appropriate frequencies appear at
the four pitch outputs. The amount of current at the
output is determined by the voltage at the K input. As
the voltage becomes more negative, more current appears at the output. This will be discussed further in
the section on "Pitch Outputs."

Pitch Outputs
The outputs labeled 2' pitch, 4' pitch, 8' pitch, and 16'
pitch provide the appropriate frequencies for these
four pitches depending on which K inputs have been
selected. The selected frequencies of the outputs are
shown in Table 1. The highest octave of frequencies is
obtained directly from the N inputs. Although these
top octave frequencies are buffered internally, their
duty cycle depends on the duty cycle of the N inputs.

Connection of the K inputs to the key switches is
dependent on which frequencies are applied to which
N inputs. Table 1 shows the relationship between the
K and N inputs. If, for example, the top octave frequency F, 5588 Hz, is applied to the N2 input, K5 should
then be connected to the highest F key on the keyboard, K6 to the next highest, K7 to the next, and K8 to
the lowest F. If the highest F key is depressed, then
N2+4, or 1397 Hz would appear at the 8' Pitch Output. At the
same time, the 16' pitch, 4' pitch and 2' pitch outputs
would provide, respectively, 699 Hz, 2794 Hz, and 5588
Hz. An example of K and N input connections is given
in Figure 4.

Each output is connected to the outputs of 22 of the
chopper keyer circuits shown in Figure 2. The chopper
device, 01, is much lower in impedance than the keyer
device 02. The output voltage amplitude is dependent,
therefore, on the ratio of 02 to the output load~ Higher
output sink resistor values result in higher output
signal amplitudes. However, it is important to keep the
output sink resistor low in order to minimize the effects of intermodulation distortion between keyers.
Figure 3 shows a typical output waveform with a 100
sink resistor. Because of the need for a low value sink

To control attack, decay, and sustain times, a circuit
such as the one shown in Figure 1 may be used. When
a keyswitch is closed, the K input charges to - 25
volts through the time constant of R2 and C1. This
5.58

810430
resistor and the usual desirability of a high signal
amplitude, it may be advisable in some cases to load
the pitch outputs with operational amplifiers instead
of resistors.

dividers to be held in the reset state. A logic 1 applied
to Reset causes the dividers to function normally. To
prevent possible phase cancellation between upper
and lower manual systems, it is suggested that an RC
network be connected to this input so that the musical
instrument will be locked into proper phase relationships when power is first applied. When in the reset
condition, all chopper devices are turned on to faci!itate testing.

VKEY Input

This supply input is used exclusively for the chopper
keyer circuits (Figure 2). It is important that this be a
low impedance supply in order to minimize intermodulation distortion between keyer circuits.

AK Output

The voltage on the supply is kept low relative to VDD
and the K inputs to insure linear operation of the MOS
keying circuits.

Whenever any key input is selected, the AK output is
actively pulled to Vss to indicated that a key is played.
This output is open ended (Le., no pull-up device is pro-

r-:_;_~e_I:_i~_:_P_~t_v_s

__
le_ve_l_t_o_th_is_in_p_u_t_c_a_u_s_e_s_a_lI_bl_.n_a_ry___V_id_e_d_},_a_n_d_m_a_y_b_e_le_ft_U_n_c_o_n_n_e_ct_e_d_i_f_no_t_n_e_e_d_e_d_
. ...., •

Figure 3: Typical Keyer Output

KEV
CONTACT

25V

-OV
INPUT TO
KEVER (V EN )

I
I
I
I

I
I~
I
I

KEVER
OUTPUT
(100n LOAD
TO Vss )

5.59

-25V
-OV
.05mV

-50mV

S10430

Figure 4: Schematic Diagram of Typical Divider-Keyer Application
8' PITCH OUTPUT

2.0 MHz
OSCILLATOR

TO S10430 RESETS
ON2NO
KEYBOARD

':r

I I

1'1'

I I IJ

:asCi

voo

J 50n

CIOJ JE F

'IS
'---

/'I'~' I'V'

;: ......
Iii
21

;;:~::

iii i
I. :0

~LLII

~~~

NCNC

I I

VKEY

.......
~~~

I I I
21,1

810430

l~~I~~ ~~~.!kkk kkk~~

Ill-

r;tj03

iii

"'''''''

eil'

voo

CICCI

~ ~

-14 VOLTS

50n

\Iss

VKEY

810430

.l~~~~

2' PITCH OUTPUT

123456 7 •

H'1

NIC

50n

4' PITCH 0 UTPUT

voo

_NM.

~':r~

~OUTPUT

15 14 Il 121\ 10 9

S50240

470Kn

lifl

~I
16

50n

NOTE: ON ALL K INPUTS. THE LETIER REFERS TO THE KEY NAME, AND THE NUMBER
TO ITS LOCATION ON THf KEYBOARD. FOR EXAMPLE. Fl WOULD BE THE LOWEST
KEY ON A 44 NOTE MANUAL, AND C4 WOULD BE T~E HIGHEST.

-5 VOLTS

5.60

AMI.----------."fIIII(.
~

A Subsidiary
of Gould Inc.

82688

DIGITAL
NOISE GENERATOR

June 1978

Features

General Description

o
o

The S2688 noise generator circuit is fabricated in
P-Channel ion implanted MOS technology and supplied in an eight-lead dual in-line plastic package. The
device contains a H-bit shift register which is continuously clocked by an internal oscillator. Exclusive OR
feedback from the 14th and 17th stages causes the •
register to generate a pseudo-random noise pattern,
.
and an internal gate is included to prevent the register
_
from reaching an all zero lockup state. To facilitate
testing, the device can be easily clocked by an external
source.

o
o

Internal Oscillator
Consistent Noise Quality
Consistent Noise Amplitude
Zero State Lockup Prevention
Zeros Can Be Externally Forced Into the Register
Oscillator Can Be Driven Externally
Operates With Single or Dual Power Supplies
Eliminates Noise Preamps
Alternate to M M5837

Block Diagram

Pin Configuration

Voo

VGG

TEST A

OUTPUT

Vss

(7)

-G(1)

(2)

B(4)

(6)

5.61

82688

TEST B

82688
Absolute Maximum Ratings
Positive Voltage On Any Pin ....................................................................... Vss + 0.3V
Negative Voltage On Any Pin Except VGG' ........................................................... Vss - 28V
Negative Voltage On VGG Supply Pin ................................................................ Vss - 33V
Storage Temperature ..................................................................... - 65°C to + 150°C
Operating Ambient Temperature ................................................................ O°C to + 70°C
Electrical Specifications (0°C-_----\
o

DISABLE STATE MACHINE CLOCK
Y,4013

'12 4013

START-r
LEVEL >--+--------1

o
1
1

1
1
0

0
0
1

"OPTION A" CONVERTS A LONG START
SIGNAL TO A SHORT PULSE
"OPTION B" USES A SHORT START
SIGNAL TO DIRECTLY RUN THE STATE
MACHINE

Immediate AID Conversion Sequence
This sequence eliminates the analog data sample time, resets the 84036, and then proceeds directly with Analogto-Digital conversion. This approach should be used for data which is steady when the 84036 is signaled to begin
processing. It may be exercised by presenting the following logic series to LVR (Pin 2) and HVR (Pin 21):
Sequence Step
LVR
HVR
1
0
1
2
0
0
3
0
1
4
1
1
5 1 0
6
1
1
7 0 1
At the end of the signal sequence, the 84036 will sample the analog data input and "roll-up" the display to the
digital value of the analog input. The sequence frequency should be greater than the oscillator frequency.
Logic "1": LVR ~ VDD -1.0V
Logic "0": LVR ~ 2.5V
HVR ~ 4.5V
HVR~1.0V

5.76

Memories

•

Memory Products Selection Guide
STATIC MOS RANDOM ACCESS MEMORIES
Part No.

Organization

Process

Max. Access
Time(ns)

Max. Active
Power(mW)

Max. Standby
Power(mW)

Power
Supplies

Package

S68610

128 x 8

NMOS

250

420

N/A

+5V

24 Pin

S68A10

128 x8

NMOS

360

420

N/A

+5V

24 Pin

S6810

128 x8

NMOS

450

400

N/A

+5V

24 Pin

S6810·1

128 x 8

NMOS

575

500

N/A

+5V

24 Pin

STATIC CMOS RANDOM ACCESS MEMORIES
Part No.

Organization

Max. Access
Time(ns)

Max. Active
Power(mW)

Max. Standby
Power(mW)

Power
Supplies

Package

S5101L·1

256 x 4

450

115

.055

+5V

22 Pin

S5101L

256 x 4

650

115

.055

+5V

22 Pin

S6501 L·1

256 x 4

450

115

.055

+5V

22 Pin

S6501L

256 x 4

650

115

.055

+5V

22 Pin

S6514

1024 x 4

300

0.25

+5V

18 Pin

S6516

2048 x 8

230

55MHz

5.5

+5V

24 Pin

MOS READ ONLY MEMORIES
Part No.

Description

Organization

Process

Max. Access
Time(ns)

Max. Active
Power(mW)

Power
Supplies

Package

S68A316

16,384 Bit Static ROM

2048 x 8

NMOS

350

370

24 Pin

S68A332

32,768 Bit Static ROM

4096 x 8

NMOS

350

370

24 Pin

S2333

32,768 Bit Static ROM

4096 x 8

NMOS

350

385

24 Pin

S68A364

65,536 Bit Static ROM

8192 x 8

NMOS

350

385

24 Pin

S686364

65,536 Bit Static ROM

8192 x 8

NMOS

250

495

24 Pin

S68A365

65,536 Bit
Bank Switch ROM

8192 x 8

NMOS

450

415

24 Pin

S2364A

65,536 Bit Static ROM

8192 x 8

NMOS

350

385

28 Pin

S2364B

65,536 Bit Static ROM

8192 x 8

NMOS

250

385

28 Pin

S6364

65,536 Bit Static ROM

8192 x 8

CMOS

250

-5

28 Pin

S6464

65,536 Bit Static ROM
with On·Board RAM

8 x 1024 x 8

NMOS

450

440

24 Pin

S23128A

131,072 Bit Static ROM

16384 x 8

NMOS

350

385

28 Pin

S23128B

131,072 Bit Static ROM

16384 x 8

NMOS

250

385

28 Pin

S23256B

262,144 Bit Static ROM

32768 x 8

NMOS

250

220

28 Pin

S23256C

262,144 Bit Static ROM

32768 x 8

NMOS

150

220

28 Pin

6.2

AIMII.-------------.""'-

A Subsidiary
of Gould Inc.

Preliminary Data Sheet

MILITARY 6514

4096 BIT (1 024x4)
STATIC CMOS RAM

General Description

Features
D
D
D
D
D
D
D
D
D
D

Address Access Time-300ns Maximum
Read and Write Cycle Time-420ns Maximum
Low Power Operation-39mW Maximum @1MHz
Low Power Standby-28f..lW Maximum
On-Chip Address Registers
Low Voltage Data Retention-2 Volts
TIL Compatible Inputs and Outputs
Three-State Outputs
Military Temperature/Voltage Range
883-8 Processing

The AMI S6514 is a 4096 bit static CMOS RAM organized as 1024 words by 4 bits per word. The device offers low power and static operation from a single + 5
Volt supply. All inputs and three-state outputs are TIL
compatible. The common data 1/0 pins allow direct
interface with common bus systems.
Data is latched into the on-chip Address Registers on
the negative going edge of the Chip Enable signal. The
data is then written into the cells on the negative going
edge of Write Enable signal. The device is disabled and
goes into a low power standby mode when the Chip
Enable is High. Data in the memory will be maintained
in this mode when Vee is reduced to 2.0 Volts.

The S6514 is fabricated using AMI's CMOS Technology. This permits the manufacture of very high density, high performance CMOS RAMs.
Block Diagram

Pin Configuration
Vee

ROW
DECODER

MEMORY
MATRIX
64x64

-< t-r-+---4I~--+-I

0/00

- - - - 1.....

0/01

----4~<

1--£-........-

.....- - + - - 1

0/02 ---;~~J--~.-~r----+-I
0/03 ---;~~.t-~.---4Ir----+-I

DATA 110
CONTROL

0/00

0/01

0/02

0/03

GNO

Pin Names

COLUMN
DECODER

Address Inputs
Data Inputs/Outputs
Chip Enable
Write Enable

Ao-Ag

0/00-0 /0 3

CE
WE
ADDRESS
REGISTER

Truth Table
Mode

6.3

Data Out

Data In

Read
Write

HI-Z

Disable

HI-Z

MILITARY 6514
Absolute Maximum Ratings·
Ambient Temperature Under Bias. . .. . ... . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . ...... .. - 55°C to + 125°C
Supply Voltage - Vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. - 0.3V to + 7.0V
Input/Output Voltage Applied. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3V to Vcc + 0.3V
Storage Temperature - Tstg ................. , ................... " ..................... - 65°C to + 150°C
·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.

D.C. Electrical Characteristics: TA

= - 55°C to + 125°C, Vcc = + 5V ± 10%

Symbol

Parameter

Min.

III
ILO

Input Leakage Current

-1

Output Leakage Current

-1

ISB

Standby Supply Current

Icc
VIL

Operating Supply Current
Input Voltage LOW

VIH

Input Voltage HIGH

VOL

Output Voltage LOW

VOH

Output Voltage HIGH

Capacitance: TA

Typ.

Max.

Units

IJA

VIN = GND to Vee
VIN = GND to Vee

50
7

IJA
rnA

VIN
VIN

-0.3

0.8

2.4

Vee +0.3

0.4

IOL = 1.6mA

IOH

2.4

Conditions

= GND or Vee
= GND or Vee. f = MHz

O.4mA

=25°C, f =1MHz. Capacitance is sampled and guaranteed.

Symbol

Parameter

CIN

Input Capacitance

Min.

Typ.

Max.

Units

Conditions

GND to Vee

Max.

Units

Conditions

50
2.0

IJA
V

TELEL

Output Capacitance
COUT
Low Vec Data Retention Characteristics:
Symbol

Parameter

leeoR
VecDR

Icc for Data Retention

Min.

Vee for Data Retention

teDR

Chip Deselect to Data Retention Time

Operation Recovery Time

Typ.

Low Vee Data Retention Wave Form

Vee
1. 4.50V
2. VDR (2 V MIN)
3. V'L

4. Vee -O.2V

CE _ _~J

6.4

See Test Conditions
and Waveforms

MILITARY 6514
A.C. Test Conditions

Input Pulse levels ............. , ................. '........................................ O.BV and 2.0V
trise/tfall ....................................................................................... .:520ns
Output load ...................................................................... 1 TTL load and 50pF
Timing levels ..................................................................................... 1.5V
A.C. Electrical Characteristics: TA = - 55°C to + 125°C, Vee = + 5V ± 10%
Min.

Symbol

Parameter

TELOV

Chip Enable Access Time

TAVOV

Adress Access Time

TWLOZ

Write Enable Output Disable Time

TEHOZ

Chip Enable Output Disable Time

TELEH

Chip Enable Pulse Negative Width

TEHEL

Chip Enable Pulse Positive Width

TAVEL

Address Setup Time

TELAX

Address Hold Time

TWLWH

Write Enable Pulse Width

TWLEH

Write Enable Pulse Setup Time

TELWH

Write Enable Pulse Hold Time

TDVWH

Data Setup Time

TWHDZ

Data Hold Time

Typ.

Max.

Units

300
320
100
100

ns
ns
ns
ns

300
120
20
50
300
300
300
200
0
0
0
100

ns
ns

See A.C. Test

Conditions and

Waveforms

ns
ns
ns
ns
ns

TWHEL

Write Enable Read Setup Time

TOVWL

Output Data Valid to Write Time

TWLDV

Write Data Delay Time

TELWL

Early Output High-Z Time

TWHEH

Late Output High-Z Time

TELEL

Read or Write Cycle Time

TWH£L-j

~~A'

_TEHELTELEH1

"~~
TWLQZ - -

\
/

...
6.5

TWLDV_

"---

-I ..~TWLWH_Mf

I:=-

V
1\

HlGH·Z

..-

~
I--

TQVWL-

NOTE 1: TELEL • TELEH ARE LONGER THAN THE
MINIMUM GIVEN FOR READ OR WRITE CYCLE.

~mQ~

"_F\
DO

ns
ns

420

TAVEL

Read Modify Write Cycle

Conditions

TWH£L

~ ~H~:HDZ
J]

I!--TDVWH

MILITARY 6514

Read Cycle: WE

- - - - - TELEL---------_

=HIGH

_ __
DQ

~HIG~H.~Z

__1I,~
K- ____________

__________T_ELQ_V_----.
__

VALID DATA OUT

Write Cycle

--t_________,V
VAlIOOATA IN
\ } -_ _ _ _ _ _ __
I\'--_ _ _----:-...JJ

--"H;.:;IGH;.;;.Z_ _ _ _ _
DO

I---TELWH

6.6

TDVWH

=:! I-- TWHOZ

---=:!-~

~~l~~~~~
."""'4.

A Subsidiary
of Gould Inc.

Preliminary Data Sheet

MILITARY 6516

16,384 BIT (2048x8)
STATIC CMOS RAM

General Description
The AMI S6516 is a 16,384 bit static CMOS RAM
organized as 2048 words by8 bits. It offers low standby
and operating power dissipation from a single + 5V
power supply. All inputs and outputs are TTL compatible. The common data 110 pins allow direct interface
with common bus systems. The output enable function
facilitates memory expansion by allowing the outputs
to be OR-tied to other devices. The device operates synchronously with address registers provided on-chip.
The data is latched into the registers during the high to
low transition of the chip enable pulse.

Features
o High Speed-150ns Maximum
o Low Power Standby-1.38mW Maximum
o Low Power Operation-83mW/MHz Maximum
o On-Chip Address Registers
o Fully TTL Compatible Inputs
o Three-State TTL Outputs
o Low Voltage Data Retention - 2V
o Standard 24 Pin Package
o EPROM and ROM Compatible Pinouts

Vee

WE
DE

A5
A6
A7

ADDRESS
LATCHES

Pin Configuration

Block Diagram

ROW
DECODER
DRIVERS

MEMORY
MATRIX

AlO

DID,

0100

DID,

D/Q,

Al0

DID,

GND

0/0 3

128X128

8X16
AD
Al
A2

ADDRESS
LATCHES

COLUMN
DECODER
DRIVERS

Pin Names

110 CONTROL
CIRCUITS

Ao-A10

CE
DATA
INPUTIOUTPUT
BUFFERS

6.7

Data Inputs/Outputs

Chip Enable

Write Enable

Output Enable

Truth Table

0/07

0100

Address Inputs

0/00- 0 /0 7

Mode

Outputs

Read
Write
Chip Disable
Output Disable

L
L
H
L

H
L
X
X

L
H
X
H

Data Out
High-Z
High-Z
High-Z

MILITARY 6516
Absolute Maximum Ratings·
Ambient Temperature Under Bias .......................................................... - O°C to + 70°C
Storage Temperature ........... , ......... '" ............................................. , - 65°C to 150°C
Power Supply Voltage ......................................................................... - 0.3V to 7V
Voltage on Any Pin with Respect to Ground .............................................. - 0.3V to Vee + 0.3V
Power Dissipation ................................................................................... 1W

'COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device.
D.C. Electrical Characteristics: TA

= - 55°C to + 125°C, Vee = + 5V ± 10%

Symbol

Parameter

Min.

Max.

Units

III

Input Leakage Current

-1

Typ.

-1

J.tA

ILO

Output Leakage Current

IS8

Standby Supply Current

250

J.tA

Icc

Operating Supply Current

rnA

VIL
VIH

Input Voltage LOW

-0.3

0.8

Input Voltage HIGH

2.2

VOL
VOH

Output Voltage LOW
2.4

t = 1MHz. Capacitance is sampled and

Symbol

Parameter

CIN
COUT

Input Capacitance
Output Capacitance

+ 0.3
0.4

Output Voltage HIGH

Capacitance: TA = 25°C,

Vcc

Typ.

Min.

Conditions
VIN = GND to Vcc
VOUT = GND to Vcc
VIN = GND or Vcc
VIN = GND or Vcc.
f = 1MHz

V
V

IOL = 3.2mA

IOH = -1mA

guaranteed.

Max.

Units

Conditions

GND to Vcc

Max.

Units

Conditions

250

Low Vce Data Retention Characteristics:

Symbol

Parameter

Typ.

Min.

Icc for Data Retention

ICCDR
VCCDR

Vcc for Data Retention

2.0

!cDR

Chip Deselect to Data
Retention Time

Operation Recovery Time

TELEL

Low Vcc Data Retention Wave Form

Vee
1.
2.
3.
4.

4.50V
VDR (2 V MIN)
V1L
Vee -O.2V

@
r.i\

11---------"\1

6.8

MILITARY 6516
A.C. Test Conditions
Input Pulse Levels . ......................................................................... O.BV to 2.2V
Input Rise and Fall Times . ............................................. " ................ " ....... ~10ns
Input Timing Level ......................................................................... O.BV and 2.2V
Output Timing Levels ...................................................................... 0.6V and 2.2V
Output Load ...................................................................... 1 TTL Load and 100pF

A.C. Electrical Characteristics: TA = - 55°C to + 125°C, Vee = + 5V ± 10%
Symbol

Parameter

tElOV

Chip Enable Access Time

tAVQV

Address Access Time

tWlQZ

Write Enable Output Disable Time
Chip Enable Output Disable Time
Chip Enable Pulse Negative Width
Chip Enable Pulse Positive Width

tEHQZ
tElEH
tEHEl
tAVEl
tElAX
tWLWH
tWlEH
tElWH
tDVWH
tWHDZ
tWHEl
tOVWl
tWLDV
tElwl
tWHEH
tElEl

Address Setup Time
Address Hold Time
Write Enable Pulse Width
Write Enable Pulse Setup Time
Write Enable Pulse Hold Time
Data Setup Time
Data Hold Time
Write Enable Read Setup Time
Output Data Valid to Write Time
Write Data Delay Time
Early Output High-Z Time
Late Output High-Z Time
Read or Write Cycle time

Min.

150
60
0
25

140
140
140
90
-10
0
-10
40
-10
10
230

tEHWL , Write Enable Read Hold TIme ................... Ons MIN.
tovEH,DataSetupTimetoChipEnable ................ 140nsMIN.

Typ.

Max.

Units

150
150
50
50

ns
ns

Conditions

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tGLOV , Output Enable to Output Valid .................. 1Ons MIN.
tGHOZ , Output Enable to Output High-Z ................. 50ns MIN

Read Modify Write Cycle

6.9

MILITARY 6516

Write Cycle

Read Cycle

_.",,,1-

D/Qo-D/Q7_----'-=~_ _ _ _ _ __ I

ifE~IGlOV-

6.10

AIMII.---------~ A~~idia~ ~~~~~~~~~~~~~~~~~~~~

of Gould Inc.

~~~~~~~~~~~~~~~~~~~~

ROM Ordering Information

ROM Ordering Information
Ordering Information

ROM Sales Policy

The following information should be included in the
purchase order when ROM devices are being ordered.

Minimum Order Quantity
Architecture

Units/Pattern

16K

S6831 B, S68A316

2Kx8

1,000

32K

S68332, S68A332

4Kx8

1,000

D Quantity of prototypes for each pattern (if none, so
state)

32K

S2333 (Alternate Pinout)

4Kx8

1,000

64K

S68A364/S68B364 (24-Pin)

8Kx8

500

D Total quantity of each pattern

64K

S2364A1B (28-Pin)

8Kx8

500

128K

S23128A/B (28-Pin)

16Kx8

250

256K

S23256B/C

32Kx8

250

Capacity

D Part number
D Number of ROM patterns

D Special marking (if required)

o * Method of ROM

code entry (EPROM, punched
Unless otherwise requested by the customer, approximately 5 units will be assembled in a ceramic package
for verification of the ROM pattern by the customer.
These 5 units will be considered as part of the total
quantity ordered.

paper tape, etc.)

o *Chip select definition o

Part No.

Pricing and delivery (pricing and delivery quotes can
be obtained from any AMI Sales Office)

* If ordering a previously supplied pattern, the order
should refer to the AMI C number (CXXXXX). This C
number can be obtained from previous AMI billing or
acknowledgement.

Mask Charges*
Most ROM suppliers charge a mask charge to cover the
expense of generating tooling that is unique to each
ROM pattern. Current AMI mask charges are as follows.

Unit Quantity Variance

Min. Qty/Mask Charges

AMI manufactures ROMs in a fully proven silicon gate
N-Channel process. However, as in any semi-conductor
production, yield variations do occur. Because of these
normal yield variations a policy has been established
that requires the customer to accept a small variation
from the nominal quantity ordered.
Unit Quantity Variance
greater)

Architecture

499 Pes.

999 Pcs.

1500 Pcs.

S6831 B, S68A316

2Kx8

N/A

$ 500

S68332, S68A332, S2333

4Kx8

N/A

$ 750

S68A364, S2364

8Kx8

N/A

$2000

$1500

S23128A/B

16Kx8

$2500

$2000

$1500

S23256B/C

32Kx8

$2500

$2000

$1500

Part No.

± 5% or50 units (whichever is

"Subject to Change

Part Number

Reorder Policy
If a customer wishes to reorder the same ROM pattern,
the following policy applies. If finished inventory exists, no minimum quantity limits will be imposed.
However, if new wafer starts are required, the same
minimum quantity as for a new pattern will apply. The 5
prototypes (supplied with new patterns) will not be supplied. No mask charge is applied to a reorder of a
previously supplied ROM pattern.

An AMI ROM part number consists of a device number
followed by a single letter designating the package
type.
P - designates plastic package
C - designates ceramic package (hermetic seal)
Device Numbers
S6831 B/S68A316

2Kx8

S68A332/S68332

4Kx8

Standard Pinout

S2333

4Kx8

(Pin compatible with 2732 EPROM)

S68A364/S68B364

8Kx8

(24 Pin)

S2364A/B

8Kx8

(28 Pin-Compatible W/2764 EPROM)

S23128A/B

16Kx8

(28 Pin)

S23256B/C

32Kx8

(28 Pin)

6.12

ROM Ordering Information
ROM Package Marking

EPROM Requirements

Unless otherwise specified, AMI ROMs are marked
with a C number (the letter C followed by a 5 digit
number) and a date code. This C number identifies
both the device type and the specific pattern. This
C number will be used on all AMI documents concerning the ROM.

The following EPROMs should be used for submitting
RO M Code Data:

A ROM can also be marked with a number supplied
by the customer. A single number of up to 10 alpha
numeric characters can be marked on the device
without extra charge. Other customer markings are
possible, but must be approved before the order is
entered.

AlMI.
DA TE CODE

EPROM
PREFERRED

868318
868332
82333
868A364
82364
823128

2KX8
4KX8
4KX8
8KX8
8KX8
16KX8

OPTIONAL

2716/2516

2-2708

2532
2732
68764
2764
27128

2-2716/2516
2-2716/2516

2-2532
2-2732
2-2764

If two EPROM's are used to specify one ROM pattern,
(Le., 2 16K EPROMs for one 32K ROM) two blank
EPROMs must be submitted. In this instance, the
programmed EPROMs must clearly state which of the
two EPROMs is for lower and upper address locations
in the ROM. The preferred method is to mark the •
EPROM with the ROM address (in Hex) where the
EPROM data is to be located.

AMI LOGO

AMI C NUMBER

ROM

cxxxxx

--+--- 8030

xxxxxxx
CUSTOMER
PART NUMBER----J
(OPTIONAL)
(up to 10 Alpha-numeric
characters)

Example: Two 2716 EPROMs for 868332 ROM
Marking: EPROM # 1 000-7FF
EPROM # 2 800-FFF
Pattern Data From ROMs

ROM Code Data

AMI's preferred method of receiving ROM CODE DATA
is in EPROM. Two EPROMs should be submitted. One
is programmed to the desired code and the other is
blank. AMI will read the programmed EPROM, transfer
this data to diskette and then program the blank
EPROM from the stored information. This procedure
guarantees that the EPROM has been properly entered
into the AMI computer system. The AMI programmed
EPROM is returned to the customer for verification of
the ROM program. Unless otherwise requested, AMI
will not proceed until the customer verifies the program
in the returned EPROM.

If a customer has ROMs produced by another supplier,
these ROMs can be submitted for ROM pattern data instead of EPROMs. Obviously, these ROMs must be pin
compatible with the AMI device. The programmable
chip selects must be defined. (NOTE: In some cases a
competitor's ROM may have a chip select or enable
that is not customer defined. However, if this pin is
customer defined for the AMI ROM, the required active
logic level for this input must be specified.)
Optional Method of Supplying ROM Code Data

If an EPROM or ROM cannot be supplied, the following
other methods are acceptable.

o
o
o

6.13

9 Track NRZ Magnetic Tape (2 each) odd parity,
800 BP1
Paper Tape (AMI Hex format)
Card Deck (AMI Hex format)

ROM Ordering Information
TheAMI Hex format is described below. With its built-in
address space mapping and error checking, this format
is produced by the AMI Assembler.
Position

Description

1
2

Start of record (Letter S)
Type of record
0- Header record (comments)
1 - Data record
9- End of file record
Byte Count
Since each data byte is represented as two
hex characters, the byte count must be
multiplied by two to get the number of
characters to the end of the record. (This
includes checksum and address data.)
Records may be of any length defined in
each record by the byte count.
Address Value
The memory location where the first data
byte of this record is to be stored. Addresses should be in ascending order.

3,4

5,6,7,8

9, ... , N

N+1,N+2

Data
Each data byte is represented by two hex
characters. Most significant character
first.
Checksum
The one's complement of the additive
summation (without carry) of the data
bytes, the address, and the byte count.

Example:
S 113 0 0 0 0 4 9 E 9 F 1 0 3 2 0 F 0 4 9 3 3 9 F 7 2 0 0 0 F 5 E 0 F 0 0 12 6
S 9 0 3 0 000 F C

UiE
~~

!:..:

DATA

S 113 0 00 0 4 9 E 9 F 1 0 3 2 0 F 0 4 9 3 1 3 9 F 7 2 0 0 0 F 5 EO F 0 0 126

Paper tape format is the same as the card format above except:
a.
b.
c.
d.

6.14

The record should be a maximum of 80 characters.
Carriage return and line feed after each record followed by another record.
There should NOT be any extra line feed between records at all.
After the last record, four (4) $$$$ (dollar) signs should be punched with
carriage return and line feed indicating end of file.

AMI.---------."""4...

A Subsidiary
of Gould Inc.

Preliminary Data Sheet

S68A316

16,384 BIT (2048X8)
STATIC NMOS ROM

Features
o Fast Address Access Time:
S68A316 - 350ns Max.

General Description

EPROM Pin Compatible

Fully Static Operation

o
o
o
o

Three Programmable Chip Selects

The AMI S68316 family of 16,384 bit mask programmable Read-Only-Memories organized as 2048 words
by 8 bits offers fully static operation with a single + 5V
power supply. The device is fully TIL compatible on all
inputs and three-state outputs. The three chip selects
are mask programmable, the active level is specified
by the user. The three-state outputs facilitate memory
expansion by allowing the outputs to be OR-tied to
other devices.
The devices are fabricated using AMI's N-Channel
MOS technology. This permits the manufacture of very
high density, high performance mask programmable
ROMs.

TTL Compatible Inputs
Three-State TTL Compatible Outputs
Late Mask Programmable

Block Diagram

Logic Symbol

Pin Configuration

A7
A,

A,
As
A,

ADDRESS
DECDDER
DRIVER

16,384 BIT
ARRAY

Vee

CS 3*

CS1*

A10

AID

CS2*

128X128

Au
A,
A2

ADDRESS
DECODER
DRIVER

GND

'CSI
'CS2
·CS3

Pin Names

Do 0, O2 03 0, D, Os 0,

• USER DEFINED CHIP SELECTS
MAY BE DEFINED AS ACTIVE HIGH (CS) OR ACTIVE LOW (CS)
OR NO CONNECTION (NC)

6.15

Ao- A 1O

Address Inputs

0 0 -07

Data Outputs

CS1 - CS3

Chip Select Inputs

Vee

+ 5V Power Supply

•

S68A316
Absolute Maximum Ratings *
Ambient Temperature Under Bias ....................................................................................................... -10°C to sooe
Storage Temperature ............................................................................................................................. 65°C to 150°C
Output or Supply Voltage .............................................................................................................................. O.5V to 7V
Input Voltage .............................................................................................................................................. O.5V to 5.5V
Power Dissipation .................................................................................................................................................... 1W
·eOMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may effect device reliability.

D.C. Characteristics: Vee

Symbol

= + 5V

± 5%; TA =

Parameter

ooe to 70°C

Min.

Typ.

Max.

Units

0.4

IOL = 3.2mA

IOH = - 220IJA

VOL

Output LOW Voltage

VO H
VIL

Output HIGH Voltage
Input LOW Voltage

-0.5

O.B

VIH

Input HIGH Voltage

2.0

'll

Vee
10

Input Leakage Current

IJA

ILo

Output Leakage Current

IJA

leG

Power Supply Current

rnA

Capacitance: f

Symbol
CIN
COUT

2.4

S6BA316

Conditions

VIN = a to Vee
VOUT = O.4V to Vee
Chip Deselected

=1.0MHz; TA =25°C
Min.

Parameter

Max.

Units

Conditions

Input Capacitance

Typ.

7.5

Output Capacitance

VIN =OV
VO UT = OV

A.C.Characteristics: Vee = + 5V ± 5%; TA = ooe to + 70°C

Symbol
tAA

Max.

Units

Conditions

S6BA316

350

See A.C. Test

Parameter
Address Access Time

Min.

Typ.

tAGS

Chip Select Access Time

S6BA316

120

Conditions and

tOFF
NOTES:

Chip Deselect Time

S6BA316

120

Waveforms

1. Only positive logic formats for CS 1 -CS 3 are accepted. 1 = VHIGH; 0= VLOW
2. A "0" indicates the chip is enabled by a logic O.
A "1" indicates the chip is enabled by a logic 1.
A.C. Test Conditions
Input Pulse Levels .................................................................................................................................... O.SV to 2.0V
Input Timing Level ................................................................................................................................. O.SV and 2.0V
Output Timing Levels ............................................................................................................................ O.4V and 2.4V
Output Load ............................................................................................................................. 1 TTL Load and 100pF

6.16

S68A316

Waveforms

Propagation From Addresses

AO.A'~_I_AA_=J
_ _V_ALI_O_ _ _ __
00.0,

Propagation From Chip Selects

Cs,·CS3

0 .0,

~,--_VA_LlO_OA_TA_ _

===>t;;

VALID

lACS l""'---v-Al-,o-nA-TA-I_OFf3-

address locations in the ROW. The preferred method is
to mark the EPROM with the ROM address (in Hex)
where the EPROM data is to be located.

ROM Code Data
AMI's preferred method of receiving ROM CODE DATA
is in EPROM. Two EPROMs should be submitted. One
is programmed to the desired code and the other is
blank. AMI will read the programmed EPROM, transfer
this data to disk and then program the blank EPROM
from the stored information. This procedure guarantees that the EPROM has been properly entered into
the AMI computer system. The AMI programmed
EPROM is returned to the customer for verification of
the ROM program. Unless otherwise requested AMI
will not proceed until the customer verifies the program
in the returned EPROM.

Pattern Data from ROMS
If a customer has ROMs produced by another supplier,
these ROMs can be submitted for ROM pattern data instead of EPROMs. Obviously, these ROMs must be pin
compatible with the AMI device. The programmable
chip selects must be defined. (NOTE: In some cases a
competitors ROM may have a chip select or enable that
is not customer defined. However, if this pin is customer defined for the AMI ROM, the required active logic
level for this input must be specified.)

EPROM Requirements
Optional Method of Supply ROM Data*

The following EPROMs should be used for submitted
ROM Code Data:

If an EPROM or ROM cannot be supplied the following,
other methods are acceptable.

PREFERRED 2716; Optional (2) 2708

D 9 Track NRZ Magnetic Tape
D Paper Tape
o Card Deck
* Consult AMI sales office for format.

If two EPROMs are used to specify one ROM pattern,
two blank EPROMs must be submitted. In this instance, the programmed EPROMs must clearly state
which of the two EPROMs is for lower and upper

6.17

•

AIMII.---------.""'4.

A Subsidiary
of Gould Inc.

S68A332

32,768 BIT (4096X8)
STATIC NMOS ROM

General Description

Features
o Fast Access Time:
S68A332: 350ns Maximum

o
o

o
o
o
o
o

The AMI S68332 is a 32,768 bit static mask programmable NMOS ROM organized as 4096 words by 8 bits.
The device is fully TTL compatible on all inputs and
outputs and has a single + 5V power supply. The three
state outputs facilitate memory expansion by allowing
the outputs to be OR-tied to other devices.
The S68332 is pin compatible with UV EPROMs making system development much easier and more cost
effective. It is fully static, requiring no clocks for operation. The two chip selects are mask programmable, the
active level for each being specified by the user.
The S68332 is fabricated using AMI's N-Channel MOS
technology. This permits the manufacture of very high
density, high performance mask programmable ROMs.

Fully Static Operation
Single + 5V ± 5% Power Supply
Directly TTL Compatible Inputs
Three-State TTL Compatible Outputs
Two Programmable Chip Selects
EPROM Pin Compatible-2532
Extended Temperature Range Available

Block Diagram

Logic Symbol
'CS,

Pin Configuration
'CS,

A,
A,
A6
A,
As

ADDRESS
DECODER
DRIVER

A10

0,
0,

A,
A3

' CS 2

&S,'

CS,'

A10

ADDRESS
DECODER
DRIVER

' CS l

Vee

AD
A,

CHIP
SELECT
DECODER'

GNU

BUFFERS

Pin Names
00 0, 0, 0, 0, 0, 06 0,

Ao-A11
'PROGRAMMABLE CHIP SELECTS
MAY BE SPECIFIED AS ACTIVE LOW (CS) OR ACTIVE HIGH (CS)
OR NO CONNECT (NC)

6.18

Address Inputs

0 0 -07

Data Outputs

CS1 -CS2

Chip Select Inputs

Vee

+ 5V Power Supply

S68A332
Absolute Maximum Ratings *
Ambient Temperature Under Bias-TA (Standard Part) ........................................................................ ooe to + 70°C
(Industrial temp part) ......................................................... - 40°C to + 85°C
Storage Temperature ......................................................................................................................... - 65°C to 150°C
Output or Supply Voltages ........................................................................................................................ - O.5V to 7V
Input Voltages ........................................................................................................................................... - O.5V to 7V
Power Dissipation .................................................................................................................................................... 1W
COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This IS a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may effect device reliability.

D.C. Characteristics: Vee
+ 5V ± 5%, TA ooe to 70°C (Standard part);
- 40°C to + 85°C (Industrial temp part)
Symbol
VOL
VOH
VIL

Parameter

Min.

Typ.

Max.

Units

0.4

IOL = 3.2mA

IOH = - 22Of-tA

Output LOW Voltage
Output HIGH Voltage

2.4

Conditions

Input LOW Voltage

-0.5

0.8

VIH
III

Input HIGH Voltage

2.0

Input Leakage Current

Vcc
10

f-tA

ILO

Output Leakage Current

f-tA

Icc

Power Supply Current

Max.

Units

Conditions

Input Capacitance

Output Capacitance

VIN = OV
VOUT = OV

V
VIN = OV to Vcc
Vo = O.4V to Vcc
Chip Deselected

Capacitance: TA = 25°C, f = 1.0MHz
Symbol
CIN
COUT

Parameter

Min.

Typ.

A.C. Characteristics: Vee = + 5V ± 5%, TA = ooe to + 70°C (Standard part);
- 40°C to + 85°C (Industrial temp part)
Symbol

Parameter

Max.

Units

Conditions

tAA

Address Access Time

S68A332

Min.

Typ.

350

See A. C. Test

tACS

Chip Select Access Time

S68A332

150

Conditions

tOFF

Chip Deselect Time

S68A332

150

Waveforms

Waveforms
AO - All

'~
-*·~-l-lAA

QO-Q7

----------fPropagation From Chip Select

-------=---

""'---V-A-Ll-OO-A-TA--

Propagation From Address

6.19

S68A332/S68B332
A.C. Test Conditions
Input Pulse Levels .................................................................. O.BV and 2.0V
Input Rise and Fall Times ................................................................. ~20ns
Input Timing Level .......................................................................... 1.5V
Output Timing Levels ............................................................... O.4V and 2.4V
Output Load ............................................................... 1 TTL Load and 100pF

Custom Programming
The preferred method of pattern submission is the AMI Hex format as described below, with its built·in address
space mapping and error checking. This is the format produced by the AMI Assembler. The format is as follows and
may be on paper tape, punched cards or other media readable by AMI.

Position
1
2

3,4

5,6,7, 8

9, ... , N
N+1, N+2

Description
Start of record (Letter S)
Type of record
o- Header record (comments)
1 - Data record
9 - End of file record
Byte Count
Since each data byte is represented as two hex characters, the byte count must be multiplied by two to get the
number of characters to the end of the record. (This includes checksum and address data.) Records may be of any
length defined in each record by the byte count.
Address Value
The memory location where the first data byte of this record is to be stored. Addresses should be in ascending order.
Data
Each data byte is represented by two hex characters. Most significant character first.
Checksum
The one's complement of the additive summation (without carry) of the data bytes, the address, and the byte count.

Example:
S 1 1 300 0 049 E 9 FlO 3 2 0 F 0 4 9 3 3 9 F 7 2 0 0 0 F 5 E 0 F 0 0 1 2 6
S9 0 3 0 00 0 FC
CI
CCCl

CCI.I.I

1.1.1

Cf.I

8~
~
1.1.1(.) t-

f3
cc

u..cc:::>
Clu.. CI
t-CI (.)

cc
t-

~~ ~

::E

:::>

Cf.I

g
~
~ I"--\I,--------JA.'--------~\ ~

~~ ~

•t

CI
CI

S 1 1 3 0 0 0 049 E 9 FlO 3 2 0 F 0 4 9 3 1 3 9 F 7 2 000 F 5 E 0 F 0 0 1 2 6

NOTES:

1. Only positive logic formats for CS 1 and CS 2 are accepted. 1 = VH1GH; 0 = VLOW
2. A' '0" indicates the chip is enabled by a logic O.
A "1" indicates the chip is enabled by a logic 1.
3. Paper tape format is the same as the card format above except:
a. The record should be a maximum of 80 characters.
b. Carriage return and line feed after each record followed by another record.
c. There should NOT be any extra line feed between records at all.
d. After the last record, four (4) $$$$ (dollar) signs should be punched with carraige return and line feed indicating end of file.
6.20

~~l~~~~~
r

.""'-

A Subsidiary
of Gould Inc.

Preliminary Data Sheet

S2333

32,768 BIT (4096x8)
STATIC NMOS ROM

Features
o Fast Access Time: 350ns Maximum

General Description
The AMI S2333 is a 32,768 bit static mask programmable NMOS ROM organized as 4096 words by 8 bits. The
device is fully TIL compatible on all inputs and outputs and has a single + 5V power supply. The three
state outputs facilitate memory expansion by allowing
the outputs to be OR-tied to other devices.
The S2333 is pin compatible with UV EPROMs making
system development much easier and more cost effective. The fully static S2333 requires no clocks for operation. The two chip selects are mask programmable with
the active level for each being specified by the user.
The S2333 is fabricated using AMI's N-Channel MOS
technology. This permits the manufacture of very high
density, high performance mask programmable ROMs.

0 Fully Static Operation
0 Single + 5V ± 5% Power Supply
0 Directly TIL Compatible Inputs
0 Three-State TIL Compatible Outputs
0 Two Programmable Chip Selects
0 EPROM Pin Compatible (2732)
0 Extended Temperature Range Available

Block Diagram

Pin Configuration

Logic Symbol
CS,·

CS2'

A5
As
A7
As
Ag

A,
AD
ADDRESS
DECODER
DRIVER

32,768 BIT

ARRAY

A10

Ao
Al
A2
A3
All

ADDRESS
DECODER
DRIVER

COLUMN
VO
CIRCUITS

Al1

cs,'

A,o

CHIP
SELECT
DECODER'

OUTPUT
BUFFERS

Pin Names
Ao-A11

Address Inputs

0 0 -07

Data Outputs

·PROGRAMMABLE CHIP SELECTS

CS1 -CS2

Chip Select Inputs

MA Y BE SPECIFIED AS ACTIVE LOW (ts) OR ACTIVE HIGH (CS)
OR NO CONNECT (NC)

Vee

+ 5V

6.21

Vee

Power Supply

•

52333
Absolute Maximum Ratings·
Ambient Temperature Under Bias- TA (Standard Part) ........................................ O°C to + 70°C
(Industrial temp part) ............................... - 40°C to + 85°C
Storage Temperature ................................................................... - 65°C to 150°C
Output or Supply Voltages ................................................................... - O.5V to 7V
Input Voltages ............................................................................. - O.5V to 7V
Power Dissipation .................................................................................. 1W
·COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maxi·
mum rating conditions for extended periods may effect device reliability.

D.C. Characteristics: Vee =
Symbol

VOL
VOH
VIL
VIH

+ 5V ± 5%, TA = O°C to 70°C (Standard part); - 40°C to + 85°C (Industrial temp part)

Parameter

Min.

Output LOW Voltage
Output HIGH Voltage

Typ.

2.4
-0.5

Max.

Units

0.4
0.8

V
V
V

Vee
10

/AA

Conditions

10L = 3.2mA
10H = - 220""A

III

Input LOW Voltage
Input HIGH Voltage
Input Leakage Current

ILO

Output Leakage Current

/AA

lee

Power Supply Current

rnA

Max.

Units

. Conditions

7
10

pF
pF

VIN = OV

Capacitance: TA
Symbol

CIN
COUT

2.0

V
VIN = OV to Vee
Vo = O.4V to Vec
Chip Deselected

= 25°C, f = 1.0MHz

Parameter

Min.

Typ.

Input Capacitance
Output Capacitance

VOUT = OV

A.C. Characteristics: Vee = + 5V ± 5%, TA = O°C to 70°C (Standard part); - 40°C to + 85°C (Industrial temp part)
Symbol

tAA
tAes
tOFF

Parameter

Min.

Typ.

Address Access Time
Chip Select Access Time
Chip Deselect Time

Max.

Units

Conditions

350
120
120

ns
ns
ns

See A.C. Test
Conditions and
Waveform

Waveforms

t"'1--

VALID DATA

AO'A11~_tAA
==::1-1H,·Z

00-07

Propagation From Chip Select

~......._YA_L1_0O_A_TA_ _

Propagation From Address

6.22

82333
A.C. Test Conditions
Input Pulse Levels ......................................................................... O.8V and 2.0V
Input Rise and Fall Times ......................................................................... ~20ns
Input Timing Level .................................................................................. 1.5V
Output Timing Levels ...................................................................... O.4V and 2.4V
Output Load ...................................................................... 1 TTL Load and 100pF
address locations in the ROW. The preferred method is
to mark the EPROM with the ROM address (in Hex)
where the EPROM data is to be located.

Pattern Data from ROMS
If a customer has ROMs produced by another supplier,
these ROMs can be submitted for ROM pattern data instead of EPROMs. Obviously, these ROMs must be pin
compatible with the AMI device. The programmable
chip selects must be defined. (NOTE: In some cases a
competitors ROM may have a chip select or enable that
is not customer defined. However, if this pin is
customer defined for the AMI ROM, the required active
logic level for this input must be specified.)

EPROM Requirements

Optional Method of Supply ROM Data*
If an EPROM or ROM cannot be supplied the following,
other methods are acceptable.
o 9 Track NRZ Magnetic Tape
o Paper Tape
o Card Deck
* Consult AM I sales office for format.

The following EPROMs should be used for submitted
ROM Code Data:
PREFERRED 1-2732; Optional 2-2716
If two EPROMs are used to specify one ROM pattern,
two blank EPROMs must be submitted. In this instance, the programmed EPROMs must clearly state
which of the two EPROMs is for lower and upper

6.23

•

AIMII.---------.""'4.

A Subsidiary
of Gould Inc.

S68A364/S68B364

65,536 BIT (8192x8)
STATIC NMOS ROM

Features
D Fast Access Time: S68A364-350ns Maximum
S588364-250ns Maximum

General Description
The AMI S68364 family are 65,536 bit static mask
programmable NMOS ROMs organized as 8192 words
by 8 bits. The devices are fully TTL compatible on all inputs and outputs and have a single + 5V power supply.
The three-state outputs facilitate memory expansion
by allowing the outputs to be OR-tied to other devices.
The devices are fully static, requiring no clocks for
operation. The chip enable is mask programmable, the
active level being specified by the user. When not
enabled, power supply current is reduced to a maximum of 15mA.
The S68364 family of devices are fabricated using
AMI's NMOS ROM technology. This permits the mask
programmable ROMs.

D Low Standby Power: 85mW Maximum
D Late Mask Programmable
D Fully Static Operation
D Single

+ 5V

± 10% Power Supply

D Directly TTL Compatible Inputs
D Three-State TTL Compatible Outputs
D Programmable Chip Enable

. Block Diagram

Logic Symbol

Pin Configuration

CElCS·
AD
Al
A2
AJ
A,

ADDRESS
DECDDER
DRIVER

65536

A6
A7

As
Ag
Ala
All
A12

·CElCS

ADDRESS
DECDDER
DRIVER

CHIP
SELECT
DECODER'

VCC

A6
00

A8
Ag
A12

BIT ARRAY

CElCS·

A10

A11

GND

COLUMN
UO
CIRCUITS

OUTPUT
BUFFERS

Pin Names
Ao-A 12

CE/CS

Address Inputs
Data Outputs
Programmable Chip Enable/Chip Select

Vcc

+ 5V

00-0 7

·USER DEFINED MASK PROGRAMMABLE AS CHIP ENABLE, CHIP SELECT,
DON'T CARE-MAY BE DEFINED AS ACTIVE HIGH, ACTIVE LOW, DON'T CARE
NOTE: DON'T CARE PINS ARE CONNECTED TO ACTIVE CIRCUITRY

6.24

Power Supply

~l~ll~~~~~
."""-

A Subsidiary
01 Gould Inc.

S68A364/S68B364
Absolute Maximum Ratings *
Ambient Temperature Under Bias ................................................................................................... -10°C to + ao°c
Storage Temperature ..................................................................................................................... - 65°C to + 150°C
Output or Supply Voltages ........................................................................................................................ - 0.5V to 7V
Input Voltages ........................................................................................................................................... - 0.5V to 7V
Power Dissipation .................................................................................................................................................... 1W
*COM MENT: Stresses above those listed under" Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may effect device reliability.

Electrical Characteristics: Vee

Symbol

= + 5V

=O°C to + 70°C

± 10%, TA

Parameter

Min.

Typ.

Max.

Units

0.4

Conditions
IOL = 3.2mA

IOH

VOL

Output LOW Voltage

VOH
VIL

Output HIGH Voltage
Input LOW Voltage

-0.5

0.8

VIH

Input HIGH Voltage

2.0

IILlI

Input Leakage Current

VCC
10

IILol

Output Leakage Current

Icc

Power Supply Current

S68A364

S688364

See Note #3

Chip Deselected (See Note#4)

ISB

Power Supply Current

Capacitance: TA

Symbol
CIN
COUT

tAA

220JAA

= OV to VCC
Vo = OAV to VCC
VIN

Chip Deselected

=25°C, 1 =1.0MHz (See Note #4)

Parameter

Max.

Units

Input Capacitance

VIN

Output Capacitance

VOUT

Switching Characteristics: Vec

Symbol

2.4

Min.

= + 5V

± 10%, TA

Parameter
Address Access Time

tACE

Chip Enable Access Time

tACS

Chip Select Access Time

tOFF

Chip Deselect Time

Typ.

Conditions

= OV
= OV

= O°C to + 70°C

Min.

Typ.

Max.

Units

Conditions

S68A364

350

See Waveforms

S688364

250

and Test Load

S68A364

350

S688364

250

S68A364

150

S688364

120

S68A364

200

S688364

100

NOTES:
1. Only positive logic formats for CE/CE are accepted. 1 = VHIGH ; 0 = VLOW
2. A "0" indicates the chip is enabled by a logic 0; A "1" indicates the chip is enabled by a logic 1.
3. Power Test: Vcc=Vcc Max; CS/CE=active Output loads disconnected; Address pin inputs all held at VIL
4. Standby Power Conditions: Same as active except CE = Deselect Level at VI
5. Guaranteed by design.

6.25

See Note #5

S68A364/S68B364

Test Load

.-------TEST COMPARATOR
OUT

t---.--"VAAVA.'V---..
y"..,
-"-

CL =100pF

VL = 2.27V

RL = 585Q

CL = CSTRAY + CJ1G + CCAP

Waveforms
Propagation From Addresses

Propagation From Chip Enable

~_'M=1~ALlD
------X

CEiCE
_

VALID DATA

00'07

)[-

VALID

_It='.'--'_~'~=l
~

VALID DATA

address locations in the ROM. The preferred method is
to mark the EPROM with the ROM address (in Hex)
where the EPROM data is to be located.

Pattern Data from ROMS
If a customer has ROMs produced by another supplier,
these ROMs can be submitted for ROM pattern data instead of EPROMs. Obviously, these ROMs must be pin
compatible with the AMI device. The programmable
chip selects must be defined. (NOTE: In some cases a
competitors ROM may have a chip select or enable
that is not customer defined. However, if this pin is
customer defined for the AMI ROM, the required active
logic level for this input must be specified.)

EPROM Requirements
Optional Method of Supply ROM Data *

The following EPROMs should be used for submitted
ROM Code Data:

If an EPROM or ROM cannot be supplied the following,
other methods are acceptable.

PREFERRED 68A764

D 9 Track NRZ Magnetic Tape
D Paper Tape
D Card Deck

If two EPROMs are used to specify one ROM pattern,
two blank EPROMs must be submitted. In this instance, the programmed EPROMs must clearly state
which of the two EPROMs is for lower and upper

* Consult AMI sales office for format.

6.26

AIMII.----------."'-

A Subsidiary
of Gould Inc.

S68A365

65,536 BIT (8192x8)
STATIC BANK SWITCH NMOS ROM

General Description

Features
D Access Time
450ns
D Late Mask Programmable

The AMI S68A365 is a 65,536 bit static bank select mask
programmable NMOS ROM organized as8192 words by
8 bits. The device is fully TTL compatible on all inputs
and outputs with a single + 5V power supply. The three
state outputs facilitate memory expansion by allowing
the outputs to be OR-tied to other devices.

D Fully Static Operation
D Single

+ 5V

± 5% Power Supply

D Directly TIL Compatible Inputs and Outputs

The device is fully static, requiring no clocks for operation. The two chip selects are mask programmable with
the active level being specified by the user.

D Programmable Chip Selects·

o
o

Latch Up Circuitry
Two Banks, Selected by FF8 and FF9

D Address Skew Protection

The S68A365 features two bank selects selected by hex
codes FF8 and FF9, provided the chip selects are
active.

*User defined mask programmble Chip Select-may be
defined as active high, active low, or no connect.

The device also incorporates in its deSign, debounce
logic which provides protection against address skew.

Block Diagram

ADDRESS
DECODERI
DRIVER

Pin Configuration

32,768 BIT
ARRAY

ADDRESS
DECODE
LOGIC

Vee

CS/CS2

CS/CSl

A10

All

GNO

Pin Names

CS
DECODER

Ao-A12

0 0 -07
CS/CS
Vec
6.27

Address Inputs
Data Outputs
Programmable Chip Select
+ 5V Power Supply

S68A365
Absolute Maximum Ratings·
Ambient Temperature Under Bias .................................................................................................... - ooe to + 70°C
Storage Temperature ....................................................................................................................... - 40°C to + 90°C
Output or Supply Voltages ................................................................................................................... - 0.5V to + 7V
Input Voltages ........ ~ .............................................................................................................................. - 0.5V to + 7V
Power Dissipation ............................................................................................................................................. 415MW
·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rat·
ing only and functional operation of the device at these or at any other condition above those indicated in the operational sections of this speci·
cation is not implied., Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

Electrical Characteristics: Vcc

= + 5V ± 5%, TA =ooe to

Parameter

VOL

Output LOW Voltage

VO H
VIL

Output HIGH Voltage
Input LOW Voltage

-0.5

0.8

VIH

Input HIGH Voltage

2.2

IILlI

Input Leakage Current

Vcc
10

VIN = 0 to

IILol

Output Leakage Current

Va = 0.4V to 5.25V
Chip Deselected

Icc

Power Supply Current

Capacitance: TA
Symbol
CIN
COUT

Min.

+ 70°C,

Symbol

Typ.

Max.

Units

0.4

IOL = 1.6mA

IOH = -100 mA

2.4

Conditions

+ 5.25V

=25°C, f =1.0MHz
Max.

Units

Conditions

Input Capacitance

VIN = OV

Output Capacitance

VOUT

Max.

Units

Parameter

Switching Characteristics: Vcc =

Min.

Typ.

+ 5V ± 5%, TA = ooe to + 70°C,
Min.

Typ.

Conditions

Symbol

Parameter

tAA

Address Access Time

450

tACS

Chip Select Access Time

450

See A.C.

tBAV

Bank Switching Address Valid

500

Test Conditions

tAS

Address Skew

150

and

tOFF

Chip Deselect Time

150

Waveforms

tBAA

Bank Switching Access Time

820

In order to switch banks, both chip selects must be in a
valid state. Also, the address inputs must be hex address FF8 for a period tBAV to an internal latch and
thereby switch to Bank '0'. Likewise, for memory data to
be read from Bank '1', both chip selects and Hex address FF9 must be held valid fortBAv to set the internal
latch.

Functional Description
The S68A365 contains two banks of memory locations,
each being 4096 words by 8 bits. The Ao-A11 inputs normally access only 4096 words of data. However, the
S68A365 has a special bank-switching mode of operation which allows this device to effectively use the
Ao-A11 addresses to access 8192 words of data. The
timing diagrams illustrate this feature.

The bank switching action occurs only with addresses
6.28

S68A365
Functional Description (Continued)
occur. Thus the output data will continue to be from
one bank for as long as a bank switching operation
does not take place.

FFB and FF9. Further, if either FFB or FF9 is valid for
less than tAS, the bank switching is guaranteed not to

Switching Test Conditions
Input Timing Level ...................................................................................................................................... O.BV to 2.2V
Output Timing Levels .............................................................................................................................. O.4V'and 2.4V
Output Load ............................................................................................................................... 1 TTL Load and 100pF
Input Rise and Fall Times ........................................................................................................................... 1nsperVoit
Figure 1. Timing Diagram
A: SWITCHING ADDRESS BANK

IN_~_lI_D__J)(~

___
CS_l._CS_2________

_____________________________

VA_Ll_D______________________________

--~-----IAA----...-I

DOo·FF7, FFA·FFF

ooo·FF7, FFA·FFF

DATA FROM BANK 0(1)

1 - - - - - - - - - - NO BANK SWITCHING - - - - - - - - - - + _ - - - - - NEW ADDRESS BANK - - - - - - -

Figure 2. Timing Diagram
B: WITHIN ONE ADDRESS BANK

VALID

IOFF

VALID DATA

6.29

VALID DATA

S68A365
PREFERRED: Two 2732

ROM Code Data

Two EPROMs will be used to specify one ROM pattern.
The programmed EPROMs must clearly state which of
the two EPROMs is for Bank '0' and which is for Bank
'1'. The preferred method is to mark the EPROM with
the ROM address (in Hex) for selecting the appropriate
Bank.

AMI's preferred method of receiving ROM CODE DATA
is in EPROM. Four EPROMs should be submitted. Two
are programmed to the desired code and the remaining
two are to be blank. AMI will read the programmed
EPROMs, transfer this data to disk and then program
the blank EPROMs from the stored information. This
procedure guarantees that the EPROMs has been properly entered into the AMI computer system. The AMI
programmed EPROMs are returned to the customer for
verification of the ROM program. Unless otherwise requested AMI will not proceed until the customer
verifies the program in the returned EPROMs.

Optional Method of Supplying ROM Data·

If EPROMs cannot be supplied, the following other
methods are acceptable.
ROM 9 Track NRZ Magnetic Tape
Paper Tape
Card Deck

EPROM Requirements
The following EPROMs should be used for submitted
RO M Code Data:

·Consult AMI sales office for format.

6.30

AIMII.---------."""4.

A Subsidiary
of Gould Inc.

S2364A1S23648

Preliminary Data Sheet

65,536 BIT (8192x8)
STATIC NMOS ROM

The device is fully TTL compatible on all inputs and outputs and has a single + 5V power supply. The three
state outputs facilitate memory expansion by allowing
the outputs to be OR-tied to other devices.

Features

o
o
o
o
o
o
o
o

Fast Access Time: S2364A 350ns Maximum
S23648 250ns Maximum
Low Standby Power: 85mW Maximum
Fully Static Operation
Single + 5V ± 10% Power Supply
Directly TTL Compatible Inputs
Three-State TTL Compatible Outputs
Three Programmable Chip Enables/Selects
EPROM Pin Compatible (2764)
Late Mask Programmable

The 82364 is pin compatible with the 2764 UV EPROM
making system development much easier and more
cost effective. It is fully static, requiring no clocks for
operation. The three chip enables are mask programmable; the active level for each being specified by the
user. When not enabled, power supply current is reduced to a 15mA maximum.

General Description
The AMI S2364 is a 65,536 bit static mask programmable NMOS ROM organized as 8192 words by 8 bits.

The 82364 is fabricated using AMI's N-Channel M08
technology. This permits the manufacture OfbVeryRohMi9h
density, high performance mask programma Ie
s.
Logic Symbol

Block Diagram

Pin Configuration

·CSI ·CSI ·CSI

CE1
A5
A6
A7
As
AI
A10
A11
Au

Au
A1
A2
A3
A4

eE3
NC

Ao
ADDRESS
DECODER
DRIVER

ADDRESS
DECODER
DRIVER

65,536
BIT ARRAY

COLUMN
UO
CIRCUITS

CS/CE2·

CS/CE3·

A11

DEfOE

A10

CS/CE1·

A10

GND

·OEfOE

CHIP
SELECT
DECODER·

Pin Names

·CS/CE3

Ao-A12

Address Inputs

·OElOE---------'

0 0 -0 7

Data Outputs

·CONTROL FUNCTION AND ACTIVE LEVEL IS USER DEFINED

CS/CE 1·CS/CE 3 Chip Selects/Enables
OE/OE
Output Enable
Vcc;GND;NC

6.31

Vee

·CS/CE1
·CS/CE2

CE2

5V;Ground;No Connect

I
_.

S2364A1S2364B
Absolute Maximum Ratings *
Ambient Temperature Under Bias ................................................................................................... - O°C to + 70°C
Storage Temperature ................................................................................................................... - 65°C to + 150°C
Voltage on Any Pin With Respect to Ground ......................................................................................... - 0.5V to 7V
Input Voltages ......................................................................................................................................... - 0.5V to 7V
Power Dissipation .................................................................................................................................................. 1W
* COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

Electrical Characteristics: Vee
Symbol

= + 5V

VOL
VO H
V,L
V,H
IILlI

Parameter
Output LOW Voltage
Output HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current

IILol

Output Leakage Current

Icc
ISB

Power Supply Current-Active
Power Supply Current-Standby

Min.

=O°C to 70°C
Typ.

2.4
-0.5
2.0

Max.
0.4
0.8
Vcc
10

Units
V
V
V
V

Conditions
IOL = 3.2mA
IOH = - 220/AA

/AA

V,N = OV to 5.5V

/AA

90
15

rnA
rnA

Vo = 0.4V to Vec
Chip Deselected
See Note #1
See Note #2

Max.
7
10

Units
pF
pF

=1.0MHz (See Note #3)

Capacitance: TA 25°C, f
Symbol Parameter
Input Capacitance
C'N
Output Capacitance
COUT

Min.

Switching Characteristics: Vee =
Symbol

± 10%, TA

+ 5V ±

Address Access Time

tACE

Chip Enable Access Time

tACS

Chip Select Access Time

tOEA

Output Enable Access Time

tCED

Disable Time From Chip Enable

tOEO

Disable Time From Output Enable

tOFF

Chip Deselect Time

tOH

Output Hold Time

Conditions
V,N = OV
VOUT = OV

10%, TA = O°C to 70°C

Parameter

tAA

Typ.

Min.
S2364A
S2364B
S2364A
S2364B
S2364A
S2364B
S2364A
S2364B
S2364A
S2364B
S2364A
S2364B
S2364A
S2364B
S2364A
S2364B

10
0

6.32

Typ.

Max.
350
250
350
250
120
120
100
100
200
80
100
80
120
80

Units
ns

Conditions
See Waveforms
and Testload

ns
ns
ns
ns
See Note #3
ns
ns
See Note #3
ns

S2364A1S23648
Test Load

~
I

TESTCOMPARATOR

'VV'v--e VL = 2.27V

OUT

RL = 585Q

CL = 100pF

CL = CSTRAY

+ CJIG + CCAP

Waveforms
ADDRESS TO OUTPUT DELAY (CHIP SELECTED)

CHIP ENABLE/SELECT TO OUTPUT DELA Y (ADDRESS VALID)

~~~~ -~

ENABLE

~_ _V_AlI_O_ _~

CHIP
SELECT

OUTPUTS

OUTPUT ENABLE TO OUTPUT DELAY (ADDRESS VALID/CHIP SELECTED)

CHIP~VALID

1------

-J~

H·Z
OUTPUTS

-----+--"{'/A~

•

OUTPUT
ENABLE

DATA
OUTPUTS

HI·Z

address locations in the ROM. The preferred method is
to mark the EPROM with the ROM address (in Hex)
where the EPROM data is to be located.

Pattern Data from ROMS
If a customer has ROMs produced by another suppli~r,
these ROMs can be submitted for ROM pattern data instead of EPROMs. Obviously, these ROMs must be pin
compatible with the AMI device. The programmable
chip selects must be defined. (NOTE: In some cases a
competitors ROM may have a chip sele~t o~ en.ab~e
that is not customer defined. However, If thiS pm IS
customer defined for the AMI ROM, the required active
logic level for this input must be specified.)

EPROM Requirements
The following EPROMs should be used for submitted
ROM Code Data:
PREFERRED 1-2764; Optional 2-2732
If two EPROMs are used to specify one ROM pattern,
two blank EPROMs must be submitted. In this instance the programmed EPROMs must clearly state
which 'Of the two EPROMs is for lower and upper

Optional Method of Supply ROM Data *
If an EPROM or ROM cannot be supplied the following,
other methods are acceptable.

o
o
o

* Consult AMI sales office for format.

Notes:
. L
I
1. Active Power Conditions: Vee Vee Max! CE/CS Active eve
@ VI. Address Pins VIL• Output Load Disconnected

9 Track NRZ Magnetic Tape
Paper Tape
Card Deck

2. Standby Power Conditions: Same as active except CE
select Level @ VI
3. Guaranteed by Design

6.33

=De-

S2364A1S2364B

Package Outlines
28-Pin Plastic

28-Pin Ceramic
PlNll1ElIllFER
21

MARKIt6S
ONU'
SUIIFACE

1,450 MAX.

ONLY

L - __

.100

.020
.015
,JIL_.200MAX.
-l.020Ml..

15o~x./1
~ f--

11.01 2
-- .001
-+

Truth Table: (For simplicity, all control functions in the Truth Table are
defined as active high.)

CS/CE1

CS/CE2

CS/CE3

DEfOE

OUTPUTS

POWER

CE1
X
X
CS1
CS/CE1
CS/CE1
CS/CE1
CS/CE1

X
CE2
X
CS/CE2

X
X
CE3
CS/CE3
CS/CE3
CS3
CS/CE3
CS/CE3

X
X
X
X
X
X
OE/OE
OE/OE

HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
DATA OUT

STANDBY
STANDBY
STANDBY
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

CS2
CS/CE2
CS/CE2
CS/CE2

The user decides between a CS or CE.function and then defines the active level. The functions may also be
defined as Don't Care (DC). The chip is enabled when the inputs match the user defined states. Don't Care
pins are still connected to input protection diodes and are subject to the" Absolute Maximum Ratings".

6.34

Pins
27
26
22
20

Control Functions Available
CS2, CS2, CE2, CIT, DC
CS3, CS3, CE3,CE3, DC
OE, OE, DC
CS1, CS1, CE1, ill, DC

AIMII.---------."""4.
~

A Subsidiary
of Gould Inc.

Preliminary Data Sheet

S6364

65,536 BIT (8192x8)
STATIC CMOS ROM

Features
o Fast Access Time:
250ns Maximum

Low Standby Power
5.5mW Maximum

Fully Static Operation

o
o

Single

o
o

Three-State TTL Compatible Outputs

o
o

EPROM Pin Compatible (2764)

+ 5V

± 10% Power Supply

Directly TTL Compatible Inputs
Three Programmable Chip Enables/Selects
Programmable Output/Chip Enable

General Description
The AMI S6364 device is a 65,536 bit static mask programmable CMOS ROM organized as 8192 words by 8
bits. The device is fully TTL compatible on all inputs
and outputs and has a single + 5V power supply. The
three state outputs facilitate memory expansion by
allowing the outputs to be OR-tied to other devices.
The S6364 is pin compatible with the 2764 UV EPROM
making system development much easier and more
cost effective. It is fully static, requiring no clocks for
operation. The three chip enables are mask programmable; the active level for each being specified by the
user. When not enabled, the power supply current is •
reduced to a 10mA maximum.
The S6364 is fabricated using AMI's CMOS technology. This permits the manufacture of very high density, high performance mask programmable ROMs.

Block Diagram

Logic Symbol

Pin Configuration

"CS/CE, "CS/CE2 "CS/CE,

ADDRESS
DECODER
DRIVER

65,536
BIT ARRAY

A12

CS/CE2"
CS/CE,"

Vee

118

A11

I
I

OEiceo

A'D

L- _ _ _ _ _ _ .,

I
ADDRESS
DECODER
DRIVER

I
I
I

COLUMN
VD
CIRCUITS

I
I

*CS/CE,
*CS/CE2

CHIP
SELECT
DECODER·

I
I
I
I
I
I

A,o

~-----1

CS/CE,"

A11

0,
0,

A12

0,
OUTPUT
BUFFERS

"OE/CE

·CS/CE3

Pin Names

Ao-A12

Address Inputs
Data Outputs
CS/CEr CS/ CE3 Chip Selects/Enables
OE/CE
Output Enable/Chip Enable
5V; Ground; No Contact
Vee; GND; NC

·OElCE ----+-------'

00-07

• THE USER DECIDES BETWEEN A CS OR CE FUNCTION AND
DE OR CE FUNCTION THEN DEFINES THE ACTIVE LEVEL FOR
CS/CE AND DEICE.

6.35

S6364
Absolute Maximum Ratings *
Ambient Temperature Under Bias ......................................................... - 40°C to85°C
Storage Temperature ................................................................... - 65°C to 150°C
Output or Supply Voltages ................................................................... - 0.3V to 6V
Input Voltages ..................................................................... -0.3VtoVee +0.3V
Power Dissipation .................................................................................. 1W
·COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

D.C. Characteristics: Vee
+ 5V ± 10%, TA
Symbol Parameter
Output LOW Voltage
VOL
Output HIGH Voltage
VOH
VIL
Input LOW Voltage
VIH
Input HIGH Voltage
Input Leakage Current
IILlI

=O°C to 70°C
Min.

Typ.

2.4
-0.1
2.2

Max.

Units

0.45

V
V
V
V

IOL = 2.1mA
IOH = -400~

VIN = OV to VCC
Vo = 0.4V to Vcc
Chip Deselected
f = 1.0MHz
Chip Disabled

0.8
Vcc
10

Conditions

IILol

Output Leakage Current

Icc
ISB

Power Supply Current-Active
Power Supply Current-Standby

10
1

mA
mA

Max.
7

Units

Conditions

pF
pF

VIN = OV
VOUT = OV

Max.

Units

Conditions

250
250
80
80
80
80
80

ns
ns
ns
ns
ns
ns
ns
ns

Capacitance: TA 25° C, f 1.0M Hz
Symbol Parameter
Input Capacitance
GIN
Output Capacitance
COUT

Min.

Typ.

A.C. Characteristics: Vee = + 5V ± 10%, TA = O°C to + 70°C
Symbol Parameter
Min.
Typ.
Address Access Time
tAA
Chip Enable Access Time
tACE
Output Enable Access Time
0
tOE
Chip
Select
Access
Time
0
tACS
Disable Time From Chip Enable
0
tCED
Chip Deselect Time
0
tOFF
Disable Time From Output Enable
0
tOEO
Output Hold Time
0
tOH
TRUTH TABLE
CS/CE1

CET
X
X
X

CS1

CS/CE1
CS/CE1
CS/CE1
CS/CE1

CS/CE2

CS/CE3

DEICE

OUTPUTS

POWER

X
X

HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
HI-Z
DATA OUT

STANDBY
STANDBY
STANDBY
STANDYB
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE

X
X

CE3

X
X
X

CS/CE2

CS/CE3
CS/CE3

OE/CE
OE/CE
OE/CE

CE2

CS2

CS/CE2
CS/CE2
CS/CE2

CS3
CS/CE3
CS/CE3

OE/CE

6.36

See A.C.
Test Conditions
and
Waveforms

The user decides between a CS/CE and OE/CE
function and then defines the active level. The
functions may also be defined as a NO CONNECT
NC). The chip is enabled when the inputs match
the user defined states.

S6364
A.C. Test Conditions
Input Pulse Levels .......................................................................... O.BV t02.2V
Input Timing Level .......................................................................... 1.0Vand 2.0V
Output Timing Levels ..................................................................... O.65V and 2.2V
Output Load ...................................................................... 1 TTL Load and 100pF

Waveforms

-=__

ADDRESS~
INPUTS

.OM.

CHIP ENABLEISELECT TO OUTPUT DELAY (ADDRESS VALID)

ADDRESS TO OUTPUT DELAY (CHIP SELECTED)

CHIP
ENABLE

V_A-:_D
___
10"_ _

CHIP
SELECT

VALID

VAliD

X'-_____

H·Z

OUTPUT ENABLE TO OUTPUT DELAY (ADDRESS VAllOlCHIP SELECTED)

~m~~ ___)(

VALlO ENABLE

~r~t:

DATA
OUTPUTS

HI·Z

VALlO

OUTPUTS

Y'--____

----+----(

~~or

DAT~

H1Z
_• - -

address locations in the ROM. The preferred method is
to mark the EPROM with the ROM address (in Hex)
where the EPROM data is to be located.

Pattern Data from ROMs
If a customer has ROMs produced by another supplier,
these ROMs can be submitted for ROM pattern data instead of EPROMs. Obviously, these ROMs must be pin
compatible with the AMI device. The programmable
chip selects must be defined. (NOTE: In some cases a
competitors ROM may only have a chip select or enable
that is not customer defined. However, if this pin is
customer defined for the AMI ROM, the required active
logic level for this input must be specified.)

EPROM Requirements

Optional Method of Supply ROM Data*

The following EPROMs should be used for submitted
ROM Code Data:

If an EPROM or ROM cannot be supplied the following,
other methods are acceptable.

PREFERRED 2764

D 9 Track NRZ Magnetic Tape

If two EPROMs are used to specify one ROM pattern,
two blank EPROMs must be submitted. In this instance, the programmed EPROMs must clearly state
which of the two EPROMs is for lower and upper

Paper Tape
D Card Deck
* Consult AMI sales office for format.
6.37

AIMI.---------r

.""-

A Subsidiary
of Gould Inc.

S6464

65,536 Bit (8 X 1024 X 8) NMOS Static ROM·
With On-Board RAM

Features
o Access Times:
Address to Data - 450ns Maximum
Enable Time From A12 - 150ns Minimum
Disable Time From A12 - 225ns Maximum
o Power Dissipation 440mW Maximum
o Fully Static Operation
o Single + 5V Power Supply
o Internally Generated Control Lines
o Late Mask Programmable

The S6464 is fabricated using AMI's Late Mask Programmable NMOS technology. This permits the manufacture of very high density, high performance mask
programmable ROMs.
Designed for systems that can access only 4K bytes of
ROM, the S6464 contains a 32 x 3 user programmable
mapping ROM that allows access to the full 8K of the
main ROM. A single 5V supply is required; all inputs
and outputs are fully TIL compatible. The outputs can
be tri-stated for write operations with an output enable
generated internally from the address inputs. No external clocks or control signals are necessary. Deskewing
Circuitry is also included to prevent false mode selection caused by address skew.

General Description
The AMI S6464 is a ROMfRAM device with 65,536 bits
of static mask programmable NMOS ROM and 512 bits
of NMOS RAM. The ROM is organized as eight 1K x 8
blocks of data while the RAM organization is 64 x 8.
Block Diagram

Pin Configuration
8 (1Kx 8)

ROM

Vee

A12

Al0

All

D07

DOo

D06

DOl

D05

D02

D04

GND

D03

Pin Names
Aa-Ag
Aa- A 5
DOa-DO?
Vee, GND, NC

6.38

ROM Address Inputs
RAM Address Inputs
RAM/ROM Outputs
+ 5V, Ground, No Connect

S6464
Absolute Maximum Ratings·
Ambient Temperature .............................................................. O°C to + 60°C
Storage Temperature .......................................................... - 65°C to + 150°C
Output or Supply Voltages ............................................................ - 0.5V to 7V
Input Voltages ..................................................................... - 0.5V to 7V
Power Dissipation ....................................................................... 440mW
·COMMENTS: Stresses above those lised under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or at any other condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may effect device reliability.

D.C. Characteristics: Vee
Symbol
VOL
VOH

= + 5V

± 10%, TA

Parameter

= + 10°C to + 50°C

Min.

Typ.

Output LOW Voltage
Output HIGH Voltage

Max.

Units

0.4

IOL =

IOH = - 220/-lA

2.4

Conditions

+ 1.6mA

VIL
VIH

Input LOW Voltage

-0.5

0.8

Input HIGH Voltage

2.4

III

Input Leakage Current

Vec
±10

/J A

ILO

Output Leakage Current

±10

/-lA

Vss ~ VIN ~ Vcc
Vo = 0.4V to Vcc Chip Deselected

Icc

Power Supply Current

Vcc = 5.5 at TA = 25°C

Switching Characteristics: Vee
Symbol

= + 5V

Parameters

tAA

Access Time

tON

A12 to Data Active

tAH

Address to Data Hold

tOFF

Address Deselect Time

tow

Valid Data Pulse Width

± 10%, TA

Min.

= + 10°C to
Typ.

+ 50°C

Max.

Units

450

nsecs

Conditions

120

nsecs

See A.C. Test

nsecs

Conditions and

nsecs

Waveforms

225
300

nsecs

tOH

Valid Data to Address Hold

tos

Valid Data to Address
Set Up

300

tCYC

Cycle Time

550

820

Min.

Typ.

100

nsecs
nsecs
nsecs

Capacitance: TA = 25°C, f = 1.0MHz
Symbol
CIN
COUT

Parameter

Max.

Units

Conditions

Input Capacitance

Output Capacitance

12.5

VIN = OV
VOUT = OV

6.39

•

86464
A.C. Test Conditions
Input Pulse Levels ................................................................. O.BV and 2.4V
Input Rise and Fall Times ................................................................. ~20ns
Input Timing Level ................................................................. O.BV and 2.4V
Output Timing Levels ............................................................... 0.4V and 2.4V
Output Load ................................................................ 1 TTL Load and 40pF

Waveforms

A: READ CYCLE (ROM OR RAM)

tCYC - - - + I

000. 007________-(
HI·Z

B: WRITE CYCLE (RAM ONLY)

tCYC

'0 ~AOORESSI
READ

1040 -107F

A12

tOFF

tAH1
oQo----~------~

00 7

VALID OUTPUT

""""'"'f

" - - I............

6.40

86464
Device Features
A. Internal Organization

for the ,case of A10 = An = O. These "masked" ROM
bytes are uncovered by simply programming the mapping ROM to access the appropriate 1K x 8 page in an
additional mapping ROM location, for which either A10
or A11 = 1.

General: The two basic components of the S6464 are a
65,536 bit ROM, with its associated mapping ROM, and
a 512 bit RAM. The ROM is organized as eight pages of
1K x 8 bits each. External addresses Ao-Ag control
access to the data, within a selected 1K x 8 page. The
1-of-8 page selection is controlled by the outputs from
the 32 x 3 mapping ROM.

B. Operation
Address Space: Six modes of operation are active on
the S6464. These modes are selected only by the external address signals (see Figure 2). No other control
signals (CS, CE, OE, RIW, etc) are needed. All other addresses within the total address space of 0000 - 1FFF
have no effect except of placing the device into an output High-Z condition.

Mapping ROM: The mapping ROM has 32 words, which
are user programmable to allow optional use of the
eight pages in the main ROM. These 32 words are
accessed by two external addresses, A10 and A11 , and
three internal signals as stored in the map address latches (see Figure 1).

Load Map Latch Immediate: External addresses Ao-A2
are stored in the address map latches. During the next
ROM Read cycle, the new latched data controls the
map selection within the mapping ROM. Note that A10
and A11 can freely access one of the four pages within
the selected map, but one of the Load Map Latch
operations has to be used to change maps.

The 32 words are subdivided into eight maps of four
words each as shown in Figure 1. The three internal
signals, corresponding to the previously latched data
from Ao-A2 control the map selection. A10 and A11 controI1-of-4 selection within each map. Each word in the
mapping ROM can be programmed independently of
all other words. Each word contains three programmable bits corresponding to eight pages (0-7) in the
main ROM.

Load Map Latch Delayed: This operation is the same as
the Load Map Latch Immediate one, in that the addresses Ao-A2 are loaded immediately. However, the
change on the mapping ROM is effective not in the
next address cycle, but rather in the fourth cycle
following the Load Map Latch Delayed cycle. This
allows the three intervening cycles to be used for an
additional microprocessor operation such as a jump
instruction.

RAM: The RAM is organized as 64 x 8, with addresses
Ao-A5 controlling the byte selection and ~ controlling
the read/write selection. All other addresses must be
applied as shown in Figure 2, for selecting the RAM.
Note that the RAM address space overlays some of the
ROM address space controlled by the mapping ROM

Figure 1.

Figure 2.
MAP
0

MAP

MAP
2

MAP

MAP
6

MAP
7

Address

(Hexadecimal Notation)

0030 - 0037

Load Map Latch Immediate
(with Ao - A2

0038 - 003F

Ao
A11
0

A10
0

WORD
0

1
1

0
1

2
3

6
7

10
11

14
15

18
19

22
23

'26
27

30
31
WORD

NOTE: Decimal numbers 0-31 represent 'Words',

6.41

Mode

1000 -

103F

Load Map Latch Delayed
(with Ao - A2)
RAM Read

1040 -

107F

RAM Write

1080 - 1FFF

ROM Read

1FFC

Clear Map Latch

•

56464
will not proceed until the customer verifies the program
in the returned EPROMs.

RAM Read or Write: Addresses Ao-A5 access 1 of 64
bytes of RAM storage. Aa determines whether the
operation is Read (Aa = 0) or Write (Aa = 1). A RAM
Write operation must be followed by any operation
other than "RAM Write"; RAM read is allowed.

EPROM Requirements
The following EPROMs should be used for submitted
ROM Code Data:

ROM Read: Addresses A10 and A11 determine the selection of one of the four possible pages within a preselected map. Within the selected page, Ao-Ag select
the desired byte. For any particular map selected within
the mapping ROM, anyone of the possible 4K bytes
can be read out by a ROM Read operation. The only
exception is that the first 128 bytes in each map are
"masked" by the RAM Read or RAM Write address
locations.

PREFERRED 2-68A764
If multiple EPROMs are used to specify one ROM pattern, an equal number of blank EPROMs must be submitted. In this instance, the programmed EPROMs
must clearly state which of the EPROMs is for lower
and upper address locations in the ROM. The preferred
method is to mark each EPROM with the ROM address
(in Hex) where the EPROM data is to be located.

Clear Map Latch: This operation initializes all internal
logic, primarily for ease of reset during power on of a
system. As A10 = A11 = 1 and the outputs of the map
address latches are all at '0', the last page in the first
map of the mapping ROM is selected. The outputs of
the mapping ROM correspond to Word 3 in Figure 1.

For the EPROM containing the data for the mapping
ROM, the data should be the first 32 bytes of the
EPROM.
Pattern Data From ROMs
If a customer has ROMs produced by another supplier,
these ROMs can be submitted for ROM pattern data instead of EPROMs. Obviously, these ROMs must be pin
compatible with the AMI device.

ROM Code Data
AMI's preferred method of receiving ROM Code Data is
in EPROM. Two sets of EPROMs should be submitted.
One is programmed to the desired code and the other is
blank. AMI will read the programmed EPROMs, transfer
this data to disk and then program the blank EPROMs
from the stored information. This procedure guarantees that the EPROMs have been properly entered into
the AMI computer system. The AMI programmed
EPROMs are returned to the customer for verification
of the ROM program. Unless otherwise requested, AMI

Optional Method of Supply ROM Data*
If an EPROM or ROM cannot be supplied the following,
other methods are acceptable.
9 Track N RZ Magnet Tape

Paper Tape
Card Deck
*Consult AMI sales for format.

6.42

AIMII.~------~
• ...",..

A Subsidiary
of Gould Inc.

S23128A1S23128B

Preliminary Data Sheet

131,072 BIT (16384x8)
STATIC NMOS ROM

The device is fully TIL compatible on all inputs and outputs and has a single + 5V power supply. The three
state outputs facilitate memory expansion by allowing
the outputs to be OR-tied to other devices.

Features

o
o

o
o
o

Fast Access Time: S23128A-350ns Maximum
S231288-250ns Maximum
Low Standby Power: 110mW Max.
Fully Static Operation
Single + 5V ± 10% Power Supply
Directly TIL Compatible Outputs
Three-State TIL Compatible Outputs
Two Programmable Chip Enables/Selects
EPROM Pin Compatible (27128)
Late Mask Programmable
Programmable Output/Chip Enable

The S23128 is pin compatible with the 27128 EPROM
making system development easier and more cost
effective. The fully static S23128 requires no clocks for
operation. The three control pins are mask programmable with the active level and function being specified
by the user. The pins can also be programmed as no
connections. If CE functions are selected, automatic
powerdown is available. The power supply current is
reduced to 20mA when the chip is disabled.

General Description
The AMI S23128 is a 131,072 bit static mask programmable NMOS ROM organized as 16,384 words by 8 bits.
Block Diagram

The S23128 is fabricated using AMI's NMOS technology. This permits the manufacture of high density,
high performance ROMs.
Logic Symbol
'CS/CE, 'CS/CE,

Vee

A7
As

Pin Configuration

ROW
ADDRESS
DECODER
DRIVERS

Atz

A,
MEMORY
MATRIX
131,072 BIT
ARRAY

CS/CEz*

At3

All

AIZ

Atl

A13

OEleE'

AID

Ag
AID

AD
At

CS/CE1'

A'0

A11

A3
A4

A12

GND

'DEfCE
'CS/CEI

Pin Names

'OE/CE

Ao-A13
0 0-0 7
CS/C E1-CS/CE 2
OE/CE
Vcc;GND;NC

----+-----'

• THE USER DECIDES BETWEEN A CS OR CE FUNCTION AND
THEN DEFINES THE ACTIVE lEVEL FOR CS/CE AND OE/CE.

6.43

Address Inputs
Data Outputs
Chip Selects/Enables
Output Enable/Chip Enable
5V;Ground; No Connect

•

AIMII.---------."""4.

A Subsidiary
of Gould Inc.

S23128A1S23128B
Absolute Maximum Ratings *
Ambient Temperature Under Bias ........................................................................................................... oDe to 70 De
Storage Temperature ....................................................................................................................... - 6S De to 1S0 De
Voltage on Any Pin With Respect to Ground ......................................................................................... - O.SV to 7V
Input Voltages ................................................................•........................................................................ - O.SV to 7V
Power Dissipation .................................................................................................................................................. 1W
* COMMENT: Stresses above those listed under "Absolute Maximum Rating" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or at any other condition above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may effect device reliability.

Electrical Characteristics: Vee
Symbol

= + SV

Min.

ILO

Parameter
Output LOW Voltage
Output HIGH Voltage
Input LOW Voltage
Input HIGH Voltage
Input Leakage Current
Output Leakage Current

Icc
IS8

Power Supply Current-Active
Power Supply Current-Standby

VOL
VOH
VIL
VIH
III

=ODe to 70 De
Typ.

2.4
-0.5
2.0
-10
-10

Max.

Units

0.4

V
V
V
V

0.8
Vcc
10
10

IAA
IAA

40
20

mA
mA

Max.
7
10

Units
pF
pF

Conditions
IOL
IOH

= 3.2mA
= - 4OOIAA

VIN = OV to Vcc
Vo = 0.4V to Vcc Chip Deselected
See Note #1
See Note #2

=1.0MHz (See Note #3)

Capacitance: TA 2sDe, f
Symbol Parameter
CIN
Input Capacitance
COUT
Output Capacitance

Min.

Switching Characteristics: Vee
Symbol

± 10%, TA

= + SV ±

10%, TA

Parameter

tAA

Address Access Time

tACE

Chip Enable Access Time

tACS

Chip Select Access Time

tOEA

Output Enable Access Time

tOFF

Chip Deselect Time

tCEO

Disable Time From Chip Enable

tOEO

Disable Time From Output Enable

tOH

Output Hold Time

Typ.

VIN = OV
VOUT = OV

=ODe to 70 De
Min.

S23128A
S231288
S23128A
S231288
S231288
S231288
S23128A
S231288
S23128A
S231288
S23128A
S231288
S23128A
S231288
S23128A
S231288

Conditions

0
0

6.44

Typ.

Max.
350
250
350
250
120
80
120
80
120
80
120
80
120
80

Units

Conditions

See Waveforms

and Test Load

ns
ns
ns
See Note #3
ns
ns
See Note #3
ns

S23128A1S23128B
Test Load

I"'"""------TEST COMPARATOR

CL = 100pF

RL = 556Q

CL = CSTRA Y + CJIG

+ CCAP

Waveforms
CHIP ENABLE/SELECT TO OUTPUT DELAY (ADDRESS VALID)

ADDRESS TO OUTPUT DELAY (CHIP SELECTED)
ADDRESS
INPUTS

OUTPUTS

VALID

CHIP
ENABLE

~~r---+-~~
VALID

CHIP
SELECTS

~o.-.._VA_lI_D-_...JI~~. r-

-----

VALID

~:;1

toFf

DATA
Hi-Z
OUTPUTS ----+---4~
OUTPUT ENABLE TO OUTPUT DELA Y (ADDRESS VALID/CHIP SELECTED)

)

OUTPUT
ENABLE

VALID ENABLE

toEA
DATA
OUTPUTS

Hi-Z

- VALID DATA

-tOED

Hi-Z

ROM Code .Data
AMI's preferred method of receiving ROM CODE DATA
is in EPROM. Two EPROMs should be submitted. One
is programmed to the desired code and the other is
blank. AMI will read the programmed EPROM, transfer
this data to disk and then program the blank EPROM
from the stored information. This procedure guarantees that the EPROM has been properly entered into
the AMI computer system. The AMI programmed
EPROM is returned to the customer for verification of
the ROM program. Unless otherwise requested AMI
will not proceed until the customer verifies the program in the returned EPROM.

If two EPROMs are used to specify one ROM pattern,
two blank EPROMs must be submitted. In this instance, the programmed EPROMs must clearly state
which of the two EPROMs is for lower and upper address locations in the ROM. The preferred method is to
mark the EPROM with the ROM address (in Hex) where
the EPROM data is to be located.
Pattern Data from ROMS
If a customer has ROMs produced by another supplier,
these ROMs can be submitted for ROM pattern data instead of EPROMs. Obviously, these ROMs must be pin
compatible with the AMI device. The programmable
chip selects must be defined. (NOTE: In some cases a
competitor's ROM may have a chip select or enable
that is not customer defined. However, if this pin is
customer defined for the AMI ROM, the required active
logic level for this input must be specified.)

EPROM Requirements
The following EPROMs should be used for submitted
ROM Code Data:
PREFERRED 1-27128; Optional 2-2764
Notes:

1_ Power Test Active Conditions: Vee = Vee Max, CE/CS = Active
Level @ VI Address Pins V IL , Output Load Disconnected

2_ Power Test Standby Conditions: Sa'me as active except CE
Deselected
3_ Guaranteed by Design

6.45

•

S23128A1S23128B

Package Outlines
28-Pin Ceramic

28-Pin Plastic
PIN I IOENTIFIER

PIN IIO£NTFER

T~~

MARKINGS

OUIO
SURFACE

,=
0016

:-J¥
L-

0090

0020 MIN

:'~I'"

.020

.015

0200

MAX

~L j

0.5------55
0.535

BENOt 0.610
0.590

.010 • •

I
,I

~_+-_~~'1-_ _ _-{'5

J
~~n
II

-.200 MAX.

:r=l\

ONLY

1.450 MAX.

MAx) ~

I~:m-----J

b~1
'~

--L0.Ol0

Truth Table: (For simplicity, all control functions in the Truth Table are defined as active high).
CS/CE1

CS/CE2

DEICE

CE1

X
X

CE2

X
X

CS1
CS/CE1
CS/CE1
CS/CE1

CS/CE2
CS2
CS/CE2
CS/CE2

CE
DEICE
DEICE
DE
DEICE

Outputs

Power

Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Data Dut

Standby
Standby
Standby
Active
Active
Active
Active

Pins

Control Functions Available

27
22
20

CS2, CS2, CE2, CE2, DC
DE, DE, CE, CE, DC
CS1, CS1, CE1, CE1, DC

The user decides between a CS/CE and DEICE function and then defines the active level. The functions may also be defined as Don't Care (DC). The chip is enabled
when the inputs match the user defined states. Don't Care pins are stili connected to input protection diodes and are subject to the "Absolute Maximum Ratings"

6.46

AMI.--------~
r
.......

A Subsidiary
of Gould Inc.

Preliminary Data Sheet

S23256B/S23256C

262,144 BIT (32,768x8)
STATIC NMOS ROM

Features
o Fast Access Time:

o
D

o
D
D
D

General Description
The AMI S23256 is a 262,144 bit static mask programmable NMOS ROM organized as 32,768 words by 8
bits. The devices are fully TTL compatible on all inputs
and outputs and operate from a single + 5V ± 10%
power supply. The three state outputs facilitate
memory expansion by allowing the outputs to be ORtied to other devices.
The S23256 is pin compatible with the 27128 UV
EPROM making system development much easier and
more cost effective. It is fully static, requiring no
clocks for operation.

S23256B: 250ns Maximum
S23256C: 150ns Maximum
Low Power Dissipation
Active Current:
40mA Maximum
Standby Current: 10mA Maximum
Fully Static Operation
Two User-Defined and Programmable
Control Lines: CE/CS, OE/CE
EPROM Pin Compatible
Late Mask Programmable
Three-State TTL Compatible Outputs

The S23256 is fabricated using AMI's N-Channel MOS •
ROM technology. This permits the manufacture of very
high density, high performance mask programmable
ROMs.

Block Diagram

Pin Configuration

Logic Symbol
CEICS'

ADDRESS
DECODER
DRIVER

262,144
BIT ARRAY

ADDRESS
DECODER
DRIVER

COLUMN
VO
CIRCUITS

A13

DEICE'

A'0

CE/CS·

A'3

GND

A,o

A'2
CHIP
SELECT
DECODER'

Vee

A'4

'CElCS

NC
Au

OUTPUT
BUFFERS

OEICE'
'OE/CE -_--1
<1>2

HALT
VMA
BA

R/W

STACK PTR HR

STACK PTR LR

INDEX HR

INDEX LR

1401
(41
161
131
1371

121

151
171
1341

(391
TSC

A15 A14 A13 A12 All Ala A9 A8

All A3

Al AO

7.3

GNO
HALT
1\1

fRO
VMA
NMI
BA
Vee
AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
A10
All

39
3
4

7
8
9
10

S6800
S68AOO
S68800

38
37
36
35
34
33
32
31

30
29

RESET
TSC
132
OBE

R/W
DO
01
02
03
04
05
06
07
A15
A14
A13
A12
GNO

S6800/S68AOO/S68BOO
Absolute Maximum Ratings
Supply Voltage Vee ............................................................................................................................. - 0.3 to + 7.0V
Input Voltage VIN ............................................................................................................................... - 0.3V to + 7.0V
Operating Temperature Range TA ........................................................................................................ O°C to + 70°C
Storage Temperature Range T stg ................................................................................................ - 55°C to + 150°C

Electrical Characteristics
Nec = 5.0V, ± 5%, Vss = 0, TA = 0 to + 70°C unless otherwise noted.)
Symbol

Characteristics

Min.

Typ.

Max.

Unit

VIH
VIHe

Input High Voltage (Normal Operating Levels)

Logic
+1, +2

Vss + 2.0
Vee - 0.6

Vee
Vee + 0.3

Vdc

VIL
VILe

Input Low Voltage (Normal Operating Levels)

Logic
+1, +2

Vss - 0.3
Vss - 0.3

Vss + 0.8
Vss + 0.4

Vdc

liN

Input Leakage Current
(VIN = 0 to 5.25V, Vee
(VIN = 0 to 5.25V, Vee

Logic •
+1, +2

1.0

2.5
100

",Adc

= Max)
= O.OV)

ITSI

Three-State (Off State) Input Current
VIN = 0.4 to 2.4V, Vee = Max

VOH

Output High Voltage
(lLOAD = 205",Adc, Vee = Min)
(ILOAD = 145",Adc, Vee = Min)
(ILOAD = -100",Adc, Vee = Min)

VOL

Output Low Voltage
(ILOAD = 1.6mAdc, Vee

Power Dissipation
Capacitance#
(VIN = 0, TA = 25°C, 1 = 1.0MHz)

COUT

teye

PW4>H

tUT

10
100

",Adc

Vss
Vss
Vss

+ 2.4
+ 2.4
+ 2.4
-

0.5

Vss

+ 0.4

Vdc

Clock Pulse Width
Measured at Vee - 0.6V

10
6.5

56800
S68AOO
S68BOO

0.1
0.1
0.1

S6800
S68AOO
S68BOO

1.000
0.666
0.50

+1
+2
DO - D7
Logic Inputs
AO - A15, R/W, VMA

+1, +2 - S6800
+1, +2 - S68AOO
+1, +2 - S68BOO

400
230
180

S6800
S68AOO
S68BOO

900
600
440

Total +1 and +2 Up Time

Rise and Fall Times

-t4>r,t4>f

1.0

W
pF

Clock Timing (Figure 1)
Cycle Time

35
70
12.5
10
12
1.0
1.5
2.0
10
10
10

pF
MHz

",s

9500
9500
9500

ns
ns
ns

100

9100

+ 0.4 and Vee - 0.6
Delay Time or Clock Separation

td
Measured at VOV

Vdc
DO - D7
AO - A15, R/W, VMA
BA

Frequency 01 Operation

Measured between Vss

2.0

= Min)

CIN

DO - D7
AO - A15, R/W

= Vss + 0.6V

* Except IRQ and NMI, Which require kQ pullup load resistor for wire-OR capability at optimum operation.
#Capacitances are periodically sampled rather than 100% tested.

7.4

S6800/S68AOO/S68BOO
Read/Write Timing
Symbol
tAD

S68DD

Characteristics

S68ADD

S68BDD

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

180
165

270
250

150
135

250

Address Delay

Unit
ns

C = 90pF
C = 30pF

t ACC

Periph. Read Access Time
tAC = tUT - (tAD + t OSR )

530

tOSR

Data Setup Time (Read)

100

Input Data Hold Time

tH
tH

Output Data Hold Time

tAH

Address Hold Time
(Address, R/W, VMA)

tEH

Enable High Time for
DBE Input

450

280

220

Date Delay Time (Write)

225

165

200

tODW

160

200

140

110

100
250
40
270

100
135
40
270

ns
ns
ns
ns

150

t pcs
tPCr;tPCf
tBA
t TSE
t TSD
tOOE
t DBEr ,
tOBEf

Processor Controls
Proc. Control Setup Time
Processor Control
Rise and Fall Time
Bus Available Delay
Three-State Enable
Three-State Delay
Data Bus Enable Down
Time During 4>1 Up Time
Data Bus Enable Rise
and Fall Times

Figure 1. Clock Timing Waveform

360

100
165
40
270

120

Figure 2. Read/Write Timing Waveform

/StartofCYCI,

Measurement point for ~1 and
are the same as for MC68DO.

7.5

are shown above. Other measurements

•

S6800/S68AOO/S68BOO
Figure 3. Read Data from Memory or Peripherals
, - - START CYCLE

11
, . -_ _ _ _ _ _- " . Ville

~====;1~~~~t;;;;;;;;;;;;;;U~~

FROMMPU _
ADDRESS

DATA FROM
MEMORY
OR _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~:~@:~

Figure 4. Write Data in Memory or Peripherals

ADDRESS
FROM MPU

~OATANOTVALID
DATA FROM
MP"

START CYCLE

===§E~~~"'V
--------t---------t-~~t:~~~~~

0.,=<2 ......- - - - - - , .

Figure 5. Initialization of MPU After Restart

v:r'"

1 _ _ _ _-

~2
Reset

14-----VMA

>- 8 Clock Times

-------t.~1

__III~

)))))))))))))));;;;;;;;;;;;;;;;);;;;;;;)A~_I.
Address Out
= FFFE

-I-e:!

Address Out
= FFFF

7.6

First Instruction Loaded into MPU

Address Out = Contents of
FFFE + FFFF

S6800/S68AOO/S68BOO
Interface Description
Label

Function

(3)
(37)

Clocks Phase One and Phase Two - Two pins are used for a two-phase non-overlapping clock that runs at the Vee
voltage level.

(40)

Reset - this input is used to reset and start the MPU from a power down condition, resulting from a power failure
or an initial start-up of the processor. If a positive edge is detected on the input, this will signal the MPU to begin
the restart sequence. This will start execution of a routine to initialize the processor from its reset condition. All
the higher order address lines will be forced high. For the restart, the last two (FFFE, FFFF) locations in memory
will be used to load the program that is addressed by the program counter. During the restart routine, the interrupt mask bit is set and must be reset before the MPU can be interrupted by IRQ.
Reset must be held low for at least eight clock periods after Vee reaches 4.75 volts (Figure 4). If Reset goes high
prior to the leading edge of ~2, on the next ~1 the first restart memory vector address (FFFE) will appear on the
address lines. This location should contain the higher order eight bits to be stored into the program counter.
Following, the next address FFFF should contain the lower order eight bits to be stored into the program counter.

VMA

(5)

Valid Memory Address - This output indicates to peripheral devices that there is a valid address on the address
bus. In normal operation, this signal should be utilized for enabling peripheral interfaces such as the PIA and
ACIA. This signal is not three-state. One standard TTL load and 30pF may be directly driven by this active high
signal.

(9)

Address Bus - Sixteen pins are used for the address bus. The outputs are three-state bus drivers capable of
driving one standard TTL load and 130pF. When the output is turned off, it is essentially an open circuit. This
permits the MPU to be used in DMA applications.

A15

(25)

TSC

(39)

Three-State Control- This input causes all of the address lines and the Read/Write line to go into the off or high
impedance state. This state will occur 500ns after TSC = 2.4V. The Valid Memory Address and Bus Available
signals will be forced low. The data bus is not affected by TSC and has its own enable (Data Bus Enable). In DMA
applications, the Three-State Control line should be brought high on the leading edge of the Phase One Clock.
The ~1 clock must be held in the high state and the ~2 in the low state for this function to operate properly. The
address bus will then be available for other devices to directly address memory. Since the MPU is a dynamic
device, it can be held in this state for only 50llS or destruction of data will occur in the MPU.

(33)

Data Bus - Eight pins are used for the data bus. It is bi-directional, transferring data to and from the memory
and peripheral devices. It also has three-state output buffers capable of driving one standard TTL load at 130pF.

(26)

DBE

(36)

Data Bus Enable - This input is the three-state control signal for the MPU data bus and will enable the bus
drivers when in the high state. This input is TTL compatible; however in normal operation, it can be driven by the
phase two clock. During an MPU read cycle, the data bus drivers will be disabled internally. When it is desired
that another device control the data bus such as in Direct Memory Access (DMA) applications, DBE should be
held low.

R/W

(34)

Read/Write - This TTL compatible output signals the peripherals and memory devices whether the MPU is in a
Read (high) or Write (low) state. The normal standby state of this signal is Read (high). Three-State Control going high will Read/Write to the off (high-impedance) state. Also, when the processor is halted, it will be in the off
state. This output is capable of driving one standard TTL load and 130pF.

HALT

(2)

Halt - When this input is in the low state, all activity in the machine will be halted. This input is level sensitive. In
the halt mode, the machine will stop at the end of an instruction. Bus Available will be at a one level, Valid
Memory Address will be at a zero, and all other three-state lines will be in the three-state mode.

•
•
•

•
•

7.7

•

S6800/S68AOO/S68BOO
Label

Function

Transition of theHait line must not occur during the last 250ns of phase one. To insure single instruction operation, the Halt line must go high for one Phase One Clock cycle.
BA

(7)

Bus Available - The Bus Available signal will normally be in the low state; when activated, it will go to the high
state indicating that the microprocessor has stopped and that the address bus is available. This will occur if the
Hait line is in the low state or the processor is in the WAIT state as a result of the execution of a WAIT instruction.
At such time, all three-state output drivers will go to their off state and other outputs to their normally inactive
level. The processor is removed from the WAIT state by the occurrence of a maskable (mask bit I = 0) or nonmaskable interrupt. This output is capable of driving one standard TTL load and 30pF.

'i"RCl

(4)

Interrupt Request - This level sensitive input requests that an interrupt sequence be generated within the
machine. The processor will wait until it completes the current instruction that is being executed before it
recognizes the request. At that time, if the interrupt mask bit in the Condition Code Register is not set, the
machine will begin an interrupt sequence. The Index Register, Program Counter, Accumulators, and Condition
Code Register are stored away on the stack. Next the MPU will respond to the interrupt request by setting the interrupt mask bit high so that no further interrupts may occur. At the end of the cycle, a 16-bit address will be
loaded that points to a vectoring address which is located in memory locations FFFB and FFF9. An adress loaded
at these locations causes the MPU to branch to an interrupt routine in memory.

The Halt line must be in the high state for interrupts to be recognized.
The IRQ has a high impedance pullup device internal to the chip; however a 3kQ external resistor to Vee should
be used for wire-OR and optimum control of interrupts.
NMI

(6)

Non-Maskable Interrupt -A low-going edge on this input requests that a non-mask interrupt sequence be
generated within the processor. As with the Interrupt Request signal, the processor will complete the current instruction that is being executed before it recognizes the NMI signal. The interrupt mask bit in the Condition Code
Register has no effect on NMI. The Index Register, Program Counter, Accumulators, and Condition Code
Register are stored away in the stack. At the end·of the cycle, a 16-bit address will be loaded that points to a vectoring address which is located in memory locations FFFC and FFFD. An address loaded at these locations
causes the MPU to branch to a non-maskable interrupt routine in memory.

NMT has a high impedance pullup resistor internal to the chip;

however a 3kQ external resistor to Vee should be

used for wire-OR and optimum control of interrupts.
Inputs IRQ and NMI are hardware interrupt lines that are acknowledged during ~2 and will start the interrupt
routine on the ~1 following the completion of an instruction.
INTERRUPTS - As outlined in the interface description the S6BOO requires a 16-bit vector address to indicate the
location of routines for Restart, Non-maskable Interrupt, and Maskable Interrupt. Additionally an address is required for the Software Interrupt Instruction (SWI). The processor assumes the uppermost eight memory locations, FFFB - FFFF, are assigned as interrupt vector addresses as defined in Figure 6.

After completing the current instruction execution the processor checks for an allowable interrupt request via the
IRQ or NMlinputs as shown by the simplified flow chart in Figure 7. Recognition of either external interrupt request or a Wait for Interrupt (WAI) or Software Interrupt (SWI) instruction causes the contents of the Index
Register, Program Counter, Accumulators and Condition Code Register to be transferred to the stack as shown in
Figure B.

7.8

AIMII.----------r

......

A Subsidiary
of Gould Inc.

S68011S6803

SINGLE CHIP
MICROCOMPUTER

D 128 Bytes of RAM
(64 Bytes Power Down Retainable)
D 31 Parallel 1/0 Lines
D Divide-by-Four Internal Clock
D Hardware 8 x 8 Multiply
D Three Operating Modes
- Single Chip
- Expanded Multiplex (up to 65K Addressing)
- Expanded Non-Multiplex
D Expanded Instruction Set
D Interrupt Capability
D Low Cost Versions
- S6803- No ROM Version
- S6803NR- No ROM or RAM
D TTL-Compatible with Single 5 Volt Supply

Features

D
D
D
D
D

Instruction and Addressing Compatible
Object Code Compatible
16-Bit Programmable Timer
Single Chip or Expandable to 65K Words
On-Chip Serial Communications Interface (SCI)
- Simplex
- Half Duplex
Mark/Space (NRZ)
Biphase (FM)
- Port Expansion
FulllHalf Duplex
D Four Internal Baud Rates Available
<1>2 -+- 16, 128, 1024, 4096
D 2K Bytes of ROM

Pin Configuration

Block Diagram

Vee

RESET

•

NMI

P2D
P21

PJD
P31
P32
P33
P34
P35

P22
P23
P24
P21

P36
P37
SC2

P23

SCI

P4D
P41

P11

P42
P43

··
·
··

P44
P45
P46
P47

P1D
P11
P12

P13
P14
P15
P16
P17

7.9

AIMII.---------r

.""-

A Subsidiary
of Gould Inc.

86801186803
General Description
The 56801 MCU is an 8-bit single-chip microcomputer
system which is compatible with the S6800 family of
parts. The S6801 is object code compatible with the
S6800 instruction set.
The 56801 features improved execution times of key
S6800 instructions including Jump to Subroutine (JSR)
and all Conditioned Branches (BRA, etc.). In addition,
several new 16-bit and 8-bit instructions have been added including Push/Pull to/from Stack, Hardware 8 x 8
, Multiply, and store concatenated A and B accumulators
(D accumulator).
The S6801 MCU can be operated in three modes:
Single-Chip, Expanded Multiplex (up to 65K Byte Addressing), and Expanded Non-Multiplex. In addition, the
S6801 is available with two mask options: an on-chip
(+ 4) Clock, or an external (+ 1) Clock. The external
mode is especially useful in Multiprocessor Applications. The S6801 E can be configured as a peripheral by
using the Read/Write (R/W), Chip Select (CS), and
Register Select (RS). The Read/Write line controls the
direction of data on Port 3 and the Register Select (RS)
allows for access to either Port 3 data register or control register.
The 56801 Serial Communications Interface (SCI) permits full serial communication using no external com-

ponents in several operating modes - Full and/or Half
Duplex operation - and two formats - Standard Mark!
Space for typical Terminal/Modem interfaces and the
Bi-Phase (FM, F2F, and Manchester) Format primarily
for use between processors. Four software addressable registers are provided to configure the Serial Port;
to provide status information; and as transmit/receive
data buffers.
'
The S6801 includes a 16-bit timer with three effectively
independent timing functions: (1) Variable pulse width
measurement, (2) Variable pulse width generation, and
(3) A Timer Overflow- Find Time Flag. This makes the
S6801 ideal for applications such as Industrial Controls, Automotive Systems, AID or D/A Converters,
Modems, Real-Time Clocks, and Digital Voltage Controlled Oscillators (VCO).
The S6801 is fully TTL-compatible and requires only a
single + 5 volt supply.
The S6803 can be thought of as an S6801 operating in
expanded multiplexed mode with no ROM. The
S6803NR is comparable to the S6801 operating in expanded multiplexed mode with no RAM and no ROM.

Absolute Maximum Ratings
Supply Voltage, Vee ............................................................. - 0.3V to + 7.0V
Input Voltage, VIN . . . . • . • . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . - 0.3V to + 7.0V
Operating Temperature Range, TA ..................................................... 0° to + 70°C
Storage Temperature.Range, Tstg ................................................ - 55°C to + 150°C
Thermal Resistance, 8JA
Plastic ............................................................................. 100°C/W
Ceramic ............................................................................. 50°C/W
This device contains circuitry to protect the inputs against damage due to high static voltage or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation it is recommended that V1N and VOUT be constrained
to the range Vss (V 1N or VOUT ) VOD '

Electrical Operating Characteristics (Vee = 5.0V ± 5%, Vss = 0, TA = 0 to + 70°C, unless otherwise noted)
Symbol

Characteristic

VIH

VIL
ITSI
ITSI
VOH

Three-State (Off State) Input Current Pl 0-P17, P30-P37
(VIN = 0.5 to 2.4 Vde) P20-P24

Min.

High Voltage*

Typ.

Max.

Unit
Vde

2.0
10.0

Vee
Vee
Vss + 0.8
10
100

Vss + 2.0
Vss +4.0
Vss - 0.3

Reset
Input Low Voltage

Output High Voltage
All Outputs Except XTAL 1 and EXTAL 2
ILOAO = - 65/-1A P40-P47, E, SC1, SC2
ILOAD = -1 OO/-IA all others

Vss + 2.4

* Except mode programming levels

7.10

Vde
/-lAde
/-lAde
Vde

86801/86803
Electrical Operating Characteristics (Continued)
Symbol
VOL

Po
CIN

tposu
tpOH
tOS01
tOS02
tpwo
tCMOS
10H
VSBB
VSB

Characteristic
Output Low Voltage
All Outputs Except XTAL 1 and EXTAL 2
ILOAO = 2.0mA
Power Dissipation
Capacitance
VIN = 0, TA = 25°C, f = 1.0MHz
P40-P47, P30-P37, SC1
Other Inputs
Peripheral Data Setup Time (Figure 3)
Peripheral Data Hold Time (Figure 3)
Delay Time, Enable Negative Transition to -OS3 Neg. Trans.
Delay Time, Enable Neg. Trans. to OS3 Positive Transition
Delay Time, Enable Negative Transition to Peripheral
Data Valid (Figure 4)
Delay Time, Enable Negative Transition to Peripheral
Data Valid (.7 Vec, P20-P24 (Figure 4)
Darlington Drive Current
Va = 1.5Vdc - P10-P17
Standby Voltage (Not Operating)
(Operating)

Min.

Typ.

Max.

Unit
Vdc

Vss + 0.4
1200

mW
pF

12.5
10
200
200

-1.0

ns
ns

- 2.5

4.00
4.75

1.0
1.0

I-Is
I-Is

350

2.0

I-Is

-10

mAdc

5.25
5.25

Vdc

Max.

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

NOTE: The above electricals satisfy Ports 1 and 2 always, and Ports 3 and 4 in the single chip mode only.

Bus Timing (Figure 7)
Svmbol
tCYC
PWASH
tASR
tASF
tAso
tER
tEF
PWEH
PWEL
tASEO
tAD
toow
tOSR
tHR
tHw
tAOL
tAHL
tAH
tUT

Characteristic
Cycle Time
Address Strobe Pulse Width High
Address Strobe Rise Time
Address Strobe Fall Time
Address Strobe Delay Time
Enable Rise Time
Enable Fall Time
Enable Pulse Width High Time
Enable Pulse Width Low Time
Address Strobe to Enable Delay Time
Address Delay Time
Data Delay Write Time
Data Set-up Time
Hold Time Read
Hold Time Write
Address Delay Time for Latch
Address Hold Time for Latch
Address Hold Time
Total Up Time

Min.
1000
220

Typ.

25
25
100
25
25
450
430
90
270
225
80
10
20
200
20
20
750

7.11

•

~1~ll~~~~~
......

A Subsidiary
of Gould Inc.

86801186803
MCU Signal Description
This section gives a description of the MCU signals for the various modes. General pin assignments for the signals
are shown on page 1. SC1 and SC2 are signals which vary with the mode that the chip is in. Table 1 gives a summary
of their function.
Table 1. Mode and Port Summary

MODE

PORT 1
EIGHT LINES

PORT 2
FIVE LINES

PORT 3
EIGHT LINES

PORT 4
EIGHT LINES

SC1

SC2

SINGLE CHIP

1/0

IS3(1)

OS3(0)

ADDRESS BUS·
(As-A15)

AS(O)

R/W(O)

ADDRESS BUS·
(Ao-A7)

10S(0)

R/W(O)

EXPANDED MUX

1/0

ADDRESS BUS
(Ao-A7)
DATA BUS
00 -07

EXPANDED NON-MUX

1/0

DATA BUS
00 -0 7

• THESE LINES CAN BE SUBSTITUTED FOR 1/0 (INPUT ONLY) STARTING WITH THE MOST SIGNIFICANT ADDRESS LINE
I = INPUT
OUTPUT
R/W = READIWRITE

SC = STROBE CONTROL
AS = ADDRESS STROBE

IS = INPUT STROBE
OS = OUTPUT STROBE
lOS = 1/0 SELECT

Read/Write Timing for Ports 3 and 4 (Figures 1-2)
Symbol

Characteristic

tAD

Address Delay

Min.

270

tACC

Peripheral Read Access Time

530

tDSR

Data Setup Time (Read)

100

tHR

Input Data Hold Time

tHW

Output Data Hold Time

tAH

Address Hold Time (Address, R/W)

tDDW

Data Delay Time (Write)

tpcs
tpcr,

Processor Controls
Processor Control Setup Time
Processor Control Rise and Fall Time
(Measured between 0.8V and 2.0V)

Typ.

Max.

Unit

tACC =tuT - (tAD +tDSR)

tpCf

ns
165

225

100

ns
ns

200

Port 3 Strobe Timing (Figure 5-6)
Symbol

Characteristic

Max.

Unit

tDSD1

Output Strobe Delay 1

Min.

100

/As

tOSD2

Output Strobe Delay 2

100

I1 s

Typ.

PW IS

Input Strobe Pulse Width

200

tlH

Input Data Hold Time

tiS

Input Data Setup Time

100

7.12

86801/86803

Figure 1. Read Data From Memory or Peripherals Expanded Non-Multiplexed

PORT 4

PORT 3

DATA FRO,M
MPU - - - - - - - - - - - - - - - - -_ _-==~~
OR PERIPHERALS
0.8
DATA NOT VALID

Figure 2. Write Data in Memory or Peripherals

2.4V

PORT 3

DATA

F~~~

+ __2.•

________________

4Vcs::~~

O.4V

~~~~I

DATA NOT VALID

Ports 1 and 2, and Ports 3 and 4 in the Single Chip Mode

..........................................................................................- ,

Figure 4. Peripheral CMOS Data Delay Times
(Write Mode)

Figure 3. Peripheral Data Setup and Hold Time
(Read Mode)

P10'P17~ 2.0V

P20.P24
P30·P37
P40.P47

IPOSU)+-

2.4V

ENABLE

,.:;;O.,:..;8V_ _ _ _ _ __

CIPOH

PORT 2

P10·P17

P20·P24

O.8V

7.13

AIMII.---------r

......

A Subsidiary
of Gould Inc.

86801186803

Figure 5. Output Strobe Timing - Single Chip Mode

Figure 6. Input Strobe Timing - Single Chip Mode

iS3-----.. . . .
cPU

......_ _ _

READ OR
WRITE
INPUT DATA
PORT 3

OS3 - - - - - - -.....

Figure 7. Multiplexed Bus Timing

leye MIN

,
Alll OADS ON TTL & 90

If
2.4V ""11-

DATA STROBE
(E)

I-

- -

IASD

2.4V

ADDRESS STROBE
. (AS)

r---

f'-

-PWASH-

OAV

750ns MIN

O.4V

~
IASR

-+-

-IASF

I-I-

""1

IER_

0.4V""'f'-

PWEL

lASED

I_pw~

I 2.4V

2.4V i---IEF

j---PWEH

0.4V

\
-r-

-f-

MPU WRITE
00·07, AO·A 7
(PORT 3)

-r-

I
\

___ IADl __

I
\

0.4V

--'

_IAD_

R/W, A8·A15
(PORT 4)

VCC0.6V

IASD

IAH

ADDRESS VALID

- I D D W - - ----IDSW-

-r-

---IAHl

ADDRESS
VALID

I
\~

IHW

r--

DATA
VALID

----IDSR_
___ IAOl __

MPU READ
00·07, AO·A 7
(PORT 3)

--..
ADDRESS
VALID

IAHl

+--

\.
/

7.14

Ir-

DATA
VALID

....

IHR

86801186803
Figure 11. Typical Data Bus Output Delay
versus Capacitive Loading

Figure 8. CMOS Load
TEST POINT

O~---l"""

6"0

T30~

500

I-- ill. ;
I-- IoL ;

2G!"~ :.'AX @2.4Y
1.6mA MAX @0.4Y
Vee; 5.0Y
T. ; Z5°C

400

300

Figure 9. Bus Timing Test Load and
Ports 1, 3 and 4 for Single Chip Mode

200

l--- ~

......

100

vee
()

CL INCLUDES STRAY CAPACITANCE
0

.
....

TEST POINT ::

600

MMD700D
OR EQUIV.

500

Vee

C ... '"

ADDRESS, YMA
300

.....- - I......._ -...

1...."..00 joooI'"

200

j,...ooo' ....
j....-

J...,....o""""

....-

RIW

L-- j.oIiiIii' ....

CL
0

100

200

300

IN~LUDES

400

STRAY CAPACIrANCF.
500

600

CL LOAD CAPACITANCE (,FI

RL
MMD6150
OR EQUIV.

Signal Descriptions

Vee and Vss
These two pins are used to supply power and ground
to t~e chip. The voltage supplied will be + 5 volts

±5%.

MMD7000
OR EQUIV.

145"A MAX @2.4Y

IOL ; 1.6mA MAX @0.4Y
Yee; 5.0Y
T. ; 25°C

100

I
IoH ;

TEST POINT -O-V-1-1
.......-

600

400

c= 90pF FOR P30·P37, P40·P47, E, SC1, SC2
R= 16.5KQ FOR P30·P37, P40·P47, E, SC1, SC2

C 40 RL. R 12K
ADJUST RL SO THAT 11
3.2mA
WITH V1
0.4V and Vee = 5.25V

III-

Figure 10. Test Loads for Port 1
Darlington Load (P1O-P17)

500

400

Figure 11. Typical Data Bus Output Delay
versus Capacitive Loading

300

200

RL =2.2K
MMD6150
OR EQUIV.

t--

100

CL LOAD CAPACITANCE (,F)

u
C ::: ~

XT AL 1 and EXTAL2

These connections are for a parallel resonant fundamental crystal, AT cut. Divide by 4 circuitry is included
with the internal clock, so a 4MHz crystal may be used
to run the system at 1MHz. The divide by 4 circuitry
allows for use of the inexpensive 3.56MHz Color TV

*
7.15

~~l~~~~~
."""4.

A Subsidiary
of Gould Inc.

56801156803
crystal for. non-time critical applications. Two 27pF
capacitors are needed from the two crystal pins to
ground to insure reliable operation. EXTAL2 may be
driven by an external clock source at a 4MHz rate to run
at 1MHz with a 40/60% duty cycle. It is not restricted to
4MHz. XTAL 1 must be grounded if an external clock is
used. The following are the recommended crystal
parameters:

an initial startup of the processor. On power up, the
reset must be held low for at least 20ms. During operation, Reset, when brought low, must be held low at 3
clock cycles.

AT = Cut Parallel Resonance Crystal
Co = 7pF Max
FREQ = 4.0MHz @ CL = 24pF
Rs
50 ohms Max
Frequency Tolerance = ± 5% to ± 0.02%
The best E output "Worst Case Design" tolerance
is ± 0.05% (500ppM) using a ± 0.02% crystal.

b) 1/0 Port 2 bits, 2, 1, and 0 are latched into programmed control bits PC2, PC1 and PCO.

When a high level is detected, the MPU does the following:
a) All the higher order address lines will be forced high.

c) The last two (FFFE, FFFF) locations in memory will
be used to load the program addressed by the program
counter.

d) The interrupt mask bit is set, must be cleared before
the MPU can recognize maskable interrupts.

Vcc Standby

Enable (E)

This pin will supply + 5 volts ± 5% to the standby RAM
on the Chip. The first 64 bytes of RAM will be maintained in the power down mode with SmA current max
in the ROM version. The circuit of Figure 15 can be
utilized to assure that Vee Standby does not go below
VS BB during power down.

This suplies the external clock for the rest of the
system when the internal oscillator is used. It is a
single phase, TTL compatible clock, and will be the
divide by 4 result of the crystal frequency. It will drive
one TTL load and 90pF.
Non-Maskable Interrupt (NMI)

To retain information in the RAM during power down
the following procedure is necessary:

A low-going edge on this input requests that a nonmaskable interrupt sequence be generated within the
processor. As with the Interrupt Request Signal, the
processor will complete the current instruction that is
being executed before it recognizes the NMI signal.
The interrupt mask bit in the Condition Code Register
has no effect on N M I.

1) Write "0" into the RAM enable bit, RAM E. RAM E is
bit 6 of the RAM Control Register at location $0014.
This disables the standby RAM, thereby protecting it at
power down.
2) Keep Vee Standby greater than VS BB .

In response to an NMI interrupt, the Index Register, Program Counter, Accumulators, and Condition Code
Register are stored on the stack. At the end of the
sequence, a 16-bit address will be loaded that points to
a vectoring address located in memory locations FFFC
and FFFD. An address loaded at these locations
causes the MPU to branch to a non-maskable interrupt
service routine in memory.

Figure 13. Battery Backup for Vcc Standby

Vee STANDBY 0~--""'----40~
__--()...., vee

A 3.3KQ external resistor to Vee should be used for
wire-OR and optimum control of interrupts.

-'--

5.25V

Inputs IRQ and NMI are hardware interrupt lines that
are sampled during E and will start the interrupt routine
on the clock bar following the completion of an instruction.

Reset

Interrupt Request (IRQ)

This input is used to reset and start the MPU from a
power down condition, resulting from a power failure or

This level sensitive input requests that an interrupt
sequence be generated within the machine. The pro7.16

S6801/S6803
1/0 Strobe (lOS) (SC1)

cessor will wait until it completes the current instruction that is being executed before it recognizes the request. At that time, if the interrupt mask bit in the Condition Code Register is not set, the machine will begin
an interrupt sequence. The Index Register, Program
Counter, Accumulators, and Condition Code Register
are stored on the stack. Next the MPU will respond to
the interrupt request by setting the interrupt mask bit
high so that no further maskable interrupts may occur.
At the end of the cycle, a 16-bit address will be loaded
that pOints to a vectoring address which is located in
memory locations FFF8 and FFF9. An address loaded
at these locations causes the MPU to branch to an interrupt routine in memory.

In the expanded non-multiplexed mode of operation,
lOS internally decodes Ag through A15 as zero's and As
as a one. This allows external access of the 256 locations from $0100 to $01 FF. The timing diagrams are
shown as Figures 1 and 2.
Address Strobe (AS) (SC1)

In the expanded multiplexed mode of operation
address strobe is output on this pin. This signal is used
to latch the 8 LSBs of address which are multiplexed
with data on Port 3. An 8-bit latch is utilized in conjunction with Address Strobe, as shown in Figure 19. Address strobe signals the latch when it is time to latch
the address lines so the lines can become data bus
lines during the E pulse. The timing for this signal is
shown in the MC6801 Bus Timing, Figure 7.This signal
is also used to disable the address from the multiplexed bus allowing a deselect time, TASD before the
data is enabled to the bus.

The IRQ requires a 3.3KQ external resistor to Vee which
should be used for wire-OR and optimum control of interrupts. Internal Interrupts will use an internal interrupt
line (IRQ2). This Interrupt will operate the same as IRQ
except that it will use the vector address of FFFO and
FFF7. IRQ1 will have priority over IRQ2 if both occur at
the same time. The Interrupt Mask Bit in the condition
mode register masks both interrupts. (See Figure 23.)

56801 Ports
There are four 1/0 ports on the S6801 MCU; three 8-bit
ports and one 5-bit port. There are two control lines
associated with one of the 8-bit ports. Each port has an
associated write only Data Direction Register which
allows each I/O line to be programmed to act as an input or an output. * A "1" in the corresponding Data
Direction Register bit will cause that 1/0 line to be an
output. A "0" in the corresponding Data Direction
Register bit will cause the 1/0 line to be an input. There
are four ports: Port 1, Port 2, Port 3, and Port 4. Their
addresses and the addresses of their Data Direction
registers are givep in Table 2.

The following pins are available in the Single Chip
Mode, and are associated with Port 3 only.
Input Strobe (IS3) (SC1)

This sets an interrupt for the processor when the IS3
Enable bit is set. As shown in Figure 61nput Strobe Timing, IS3 will fall TIS minimum after data is valid on Port 3.
If IS3 Enable is set in the 1/0 Port ControllStatus
Register, an interrupt will occur. If the latch enable bit
in the 1/0 Control Status Register is set, this strobe will
latch the input data from another device when that
device has indicated that it has valid data.

* The only exception is bit 1 of Port 2, which can either be data

Output Strobe (OS3) (SC2)

input or Timer output.

This signal is used by the processor to strobe an external device, indicating valid data is on the I/O pins. The
timing for the Output Strobe is shown in Figure 5. 1/0
Port Control/Status Register is discussed in the following section.

Table 2. Port and Data Direction Register Addresses
Ports

I/O
I/O
I/O
I/O

The following pins are available in the Expanded
Modes.

Port
Port
Port
Port

1
2
3
4

Port Address

Data Direction Register Address

$0002
$0003
$0006
$0007

$0000
$0001
$0004
$0005

Read Write (RlW) (SC2)

1/0 Port 1

This TIL compatible output signals the peripherals and
memory devices whether the MPU is in a Read (high) or
a Write (low) state. The normal standby state of this
signal is Read (high). This output is capable of driving
one TIL load and 90pF.

Th is is an 8-bit port whose i nd ividual bits may be defi ned
as inputs or outputs by the corresponding bit in its data
direction register. The 8 output buffers have three-state
capability, allowing them to enter a high impedance

7.17

I
~.

AIMII.-----------.......

A Subsidiary
of Gould Inc.

86801186803
an input strobe and an output strobe, that can be used
for handshaking. They are controlled by the 110 Port
Control/Status Register explained at the end of this
section.

state when the peripheral data lines are used as inputs.
In order to be read properly, the voltage on the input
lines must be greater than 2.0 volts for a logic "1" and
less than 0.6 volt for a log ic "0". As outputs, these lines
are TTL compatible and may also be used as a source of
up to 1mA at 1.5 volts to directly drive a Darlington
base. After Reset, the 110 lines are configured as inputs.
In all three modes, Port 1 is always parallel I/O.

Expanded Non-Multiplexed Mode: In this mode Port 3
become the data bus (DrDo).
Expanded Multiplexed Mode: In this mode Port 3
becomes both the data bus (DrDo) and lower bits of the
address bus (ArAo). An address strobe output is true
when the address is on the port.

I/O Port 2
This port has five lines that may be defined as inputs or
outputs by its data direction register. The 5 output buffers have three-state capability, allowing them to enter
a high impedance state when used as an input. In order
to be read properly, the voltage on the input lines must
be greater than 2.0 volts for a logic "1" and less than 0.8
volt for a logic "0". As outputs, this port has no internal
pullup resistors but will drive TTL inputs directly. For
driving CMOS inputs, external pullup resistors are required. After Reset, the I/O lines are configured as inputs. Three pins on Port 2 (pins 10, 9 and 8 of the chip)
are used to program the mode of operation during
reset. The values of these pins at reset are latched into
the three MSBs (bits 7, 6, and 5) of Port 2 which are read
only. This is explained in the Mode Selection Section.

I/O Port 3 Control/Status Register

SOOOF

Bit
Bit
Bit
Bit

0
1
2
3

Bit 4

In all three modes, Port 2 can be configured as I/O and
provides access to the Serial Communications Interface and the Timer. Bit 1 is the only pin restricted to
data input or Timer output.
I/O Port 3

Bit 5
Bit 6

This is an 8-bit port that can be configured as I/O, as
data bus, or an address bus multiplexed with the data
bus - depending on the mode of operation hardware
programmed by the user at reset. As a data bus, Port 3
is bidirectional. As an input for peripherals, it must be
supplied regular TTL levels, that is, greater than 2.0
volts for a logic "1" and less than 0.5 volt for a logic "0".

Bit 7

Its TTL compatible three-state output buffers are
capable of driving one TTL load and 90pF. In the
Expanded Modes, after reset, the data direction
register is inhibited and data flow depends on the state
of the RlW line. The input strobe (IS3) and the output
strobe (OS3) used for handshaking are explained later.

Not used.
Not used.
Not used.
Latch Enable. This controls the input latch for
I/O Port 3. If this bit is set high the input data
will be latched with the falling edge of the Input
Strobe, IS3. This bit is cleared by reset, or CPU
Read Port 3.
(OSS) Output Strobe Select. This bit will select
if the Output Strobe should be generated by a
write to 110 Port 3 or a read of 110 Port 3. When
this bit is cleared the strobe is generated by a
read Port 3. When this bit is set the strobe is
generated by a write Port 3.
Not used.
IS3 ENABLE. This bit will be the interrupt caused by IS3. When set to a low level the IS3 FLAG
will be set by input strobe but the interrupt will
not be generated. This bit is cleared by reset.
IS3 FLAG. This is a read only status bit that is
set by the failing edge of the input strobe, IS3. It
is cleared by a read of the Control/Status
Register followed by a read or write of I/O Port
3. Reset will clear this bit.

I/O Port 4
This is an 8-bit port that can be configured as 110 or as
address lines depending on the mode of operation. In
order to be read properly, the voltage on the input lines
must be greater than 2.0 volts for a logic "1" and less
than 0.8 volt for a log ic "0". As outputs, each line is TTL
compatible and can drive 1 TTL load and 90pF. After
reset, the lines are configured as inputs. To use the
pins as addresses, therefore, they should be pro-

In the three modes Port 3 assumes the following
characteristics:
Single Chip Mode: Paraliellnputs/Outputs as programmed by its associated Data Direction Register. There are
two control lines associated with this port in this mode,
7.18

S6801/6803
grammed as outputs in the three modes. Port 4
assumes the following characteristics.

Figure 14_ Diode Configuration for the Expanded
Non-Multiplexed Mode

Single Chip Mode: ParaliellnputslOutputs as programmed by its associated Data Direction Register.
Expanded Non-Multiplexed Mode: In this mode Port 4 is
configured as the lower order address lines (A7"Ao) by
writing one's to the data direction register. When all
eight address lines are not needed, the remaining line
starting with the most significant bit, may be used as
110 (inputs only).

-_--0 Vee

RESET - - . - - . - - - -.......

TO PERIPHERAL
TO COUPLER CONTROL

Expanded Multiplexed Mode: In this mode Port 4 is configured as the high order address lines (A15-Aa) by
writing one's to the data direction register. When all
eight address lines are not needed, the remaining line,
starting with the most significant bit, may be used as
1/0 (inputs only).

TO PERIPHERAL
TO COUPLER CONTROL

P1~~~

- - - - - - - - -......---te

AS SITS 5, 6 ANO 7 OF PORT 2 ARE READ ONL Y, THE MODE CANNOT
BE CHANGED THROUGH SOFTWARE. THE MODE SELECnONS ARE
SHOWN IN TABLE 3.

TO PERIPHERAL
TO COUPLER CONTROL

P20 REFERS TO PORT 2, SIT O.

Mode Selection
The mode of operation that 6801 will operate in after
Reset is determined by hardware that the user must
wire on pins 10,9, and 8 of the chip. These pins are the
three LSBs (1102, 1101, and 1100 respectively) of Port 2.
They are latched into programmed control bits PC2,
PC1, and PCO when reset goes high. 1/0 Port 2 Register
is shown below.
7

S0003

Figure 15_ Quad Analog, Switch/Multiplexer
in a Typical S6801 Circuit

MC14066B

PC2

PCl

PCO

V04

(1/4 OF DEVICE SHOWN)

CONTROL

,V03

V02

VOl

VOO

An example of external hardware that could be used in
the Expanded Non-Multiplexed Mode is given in Figure
14. In the Expanded Non-Multiplexed Mode, pins 10,9
and 8 are programmed Hi, Lo, Hi respectively as shown.
Couplers between the pins on Port 2 and the peripherals attached may be required. If the lines go to
devices which require signals at power up differing
from the signals needed to program the 6801 's mode,
couplers are necessary.

7414

The 14066B can be used to provide this isolation between the peripheral device and the MCU during reset.
Figure 15 shows the logic diagram and xxxxx? for the
MC14066B. It is bidirectional and requires no external
logic to determine the direction of the information flow.
The logic shown insures that the data on the peripheral
will not change before it is latched into the MCU and
the MCU has started the reset sequence.

TO 14066B
CONTROL INPUTS

7.19

AIMII@---------......

A Subsidiary
of Gould Inc.

S6801/S6803
lines for I/O (inputs only). Port 3 is the data bus
multiplexed with the lower order address lines differentiated by an output called Address Strobe. Port 2 is 5
lines of Parallel I/O, SC1, Timer, or any combination
thereof. Port 1 is 8 Parallel I/O lines. In this mode it is
expandable to 65K words. (Figure 18)

56801 Basic Modes
The S6801 is capable of operating in three basic modes,
(1) Single Chip Mode, (2) Expanded Multiplexed Mode
(compatible with S6800 peripheral family), (3) Expanded
Non-Multiplexed Mode.
Single Chip Mode

Internal ClockiDivide-by-Four - This mask option is
shown in Figure 18. Only an external crystal is required
for operation.

In the Single Chip Mode the ports are configured for I/O.
In this mode, Port 3 has two associated control lines, an
input strobe and an output strobe for handshaking data.

Figure 17. S6801 MCU Expanded
Non-Multiplexed Mode

Figure 16. S6801 MCU Single Chip Mode
Vee

Vee

ENABLE

Vee STANDBY - - - - . .

PORT1~

56801
MCU

PORT1~

PORT 3
8 If 0 UNES

81/0llNES~

PORT 2
5110 LINES
UART(SERIALVOI
TIMER

PORT 4
8 I/O LINES

PORT 3

BPARAllELI'O~

PORT2<=)
5 PARAllEL 110
SERIAL I/O
TIMER

8 DATA LINES

PORT 4
T08AOORESS
LINES OR TO
7 110 LINES
L...-~_--'

(INPUTS ONLY)

VSS

Vss

Figure 18. S6801 MCU Expanded
Multiplexed Mode

Expanded Non-Multiplexed Mode

Vee

In this mode the S6801 will directly address S6800
peripherals with no external logic. In this mode Port 3
becomes the data bus. Port 4 becomes the ArAtJ
address bus or partial address and I/O (inputs only).
Port 2 can be parallel I/O, serial only. In this mode the
S6801 is expandable to 256 locations. The eight
address lines associated with Port 4 may be
substituted for I/O (inputs only) if a fewer number of
address lines will satisfy the application.

PORT 3
BLiNES
MULTIPLEX EO
OATA/AOORESS

PORT 1
BVOLINES

The Internal Clock requires only the addition of a
crystal for operation. This input will also accept an
external TTL or CMOS input, but in either case, the
clock frequency will be divided by four for this mask
option. (Figure 17)

PORT 2
5VOLINES
SERIAL VO
TIMER

Expanded Multiplexed Mode
In this mode Port 4 becomes higher order address lines
with an alternative of substituting some of the address

PORT 4
BLiNES
AOORESSBUS

VSS

7.20

86801186803
Table 3. Mode Selects

MODE
7
6

5
4
3
2
1
0

PROGRAM CONTROL

Single Chip
Expanded Multiplexed
Expanded Non-Multiplexed
Single Chip Test
64K Address I/O
Ports 3 & 4 External
Test Data Outputted from
ROM & ROM to I/O Port 3

E - EXTERNAL all vectors are external
I - INTERNAL
Ep - EXPANDED
MULTIPLEXED

Hi
Hi
Hi
Hi
La
La
La
La

Hi
Hi
La
La
Hi
Hi
La
La

Hi
La
Hi
La
Hi
La
Hi
La

ROM

RAM

INTERRUPT VECTORS

BUS

I
I
I
1(2)
E
E
I
I

I
I
I
1(1)
E
I
I
I

I
I
I
I
E
E
E
1*

I
Ep/M
Ep
I
Ep/M
Ep/M
Ep/M
Ep/m

* First two addresses read from external after reset
(1) Address for RAM XX80-XXFF
(2) ROM disabled

Lower Order Address Bus Latches

D-type latch can be used with the 86801 to latch the
least significant address byte. Figure 19 shows how to
connect the latch to the 86801. The output control to
the L8373 may be connected to ground.

Since the data is multiplexed with the lower order
address bus in Port 3, latches are required to latch
those address bits. The SN74L8373 Transparent octal
Figure 19. Latch Connection

GND
AS

I
G

PORT 3
ADDRESS/DATA

74LS373

ADDRESS: Ao-A7

DATA: 00-07
FUNCTION TABLE
OUTPUT
CONTROL
L
L
L
H

ENABLE

0
H
H
L
X

0
H
L
X
X

OUTPUT
0
H
L

A.
Z

7.21

AIMII.---------.~

A Subsidiary
of Gould Inc.

86801/86803
Programmable Timer

The S6801 contains an on-chip 16 bit programmable
timer which may be used to perform measurements on
an input waveform while independently generating an
output waveform. Pulse widths for both input and output signals may vary from a few microseconds to many
seconds. The timer hardware consists of:

•
•
•
•

an 8-bit control and status register
a 16-bit free running counter
a 16-bit output compare register, and
a 16-bit input capture register

A block diagram of the timer registers is shown in
Figure 20.

Figure 20. Block Diagram of Timer Registers
TIMER CONTROl/STATUS REGISTER
65432

soal

ICF

OCF

TOF

EICI

EDCI

I I
ETOI

SOB*
OUTPUT COMPARE

HIGH BYTE

COUNTER

OLVL

OUTPUT COMPARE

LOW BYTE
SOA

HIGH BYTE

COUNTER

SOD
INPUT CAPTURE

IEOG
SOC

S09

+21

LOW BYTE
SOE

HIGH BYTE

INPUT CAPTURE

LOW BYTE

·THE CHARACTERS ABOVE THE REGISTERS REPRESENT THEIR ADDRESS IN HEX.

clocked to the output level register. Providing the Data
Direction Register for Port 2, Bit 1 contains a "1" (output), the output level register value will appear on the
pin for Port 2 Bit 1. The values in the Output Compare
Register and Output level bit may then be changed to
control the output level on the next compare value. The
Output Compare Register is set to $FFFF during
RESET. The Compare function is inhibited for one cycle
following a write to the high byte of the Output Compare Register to insure a valid 16-bit value is in the
register before a compare is made.
Input Capture Register (SDOOD:OOOE)

Free Running Counter (S0009:000A)

The key element in the programmable timer is a 16-bit
free running counter which is driven to increasing
values by the MPU~. The counter value may be read by
the MPU software at any time. The counter is cleared to
zero on RESET and may be considered a read-only
register with one exception. Any MPU write to the
counter's address ($09) will always result in a preset
value of $FFF8 being loaded into the counter regardless of the value involved in the write. The preset
feature is intended for testing operation of the part, but
may be of value in some applications.

The Input Capture Register is a 16-bit read-only register
used to store the current value of the free running
counter when the proper transition of an external input
signal occurs. This input transition change required to
trigger the counter transfer is controlled by the input
Edge bit (EDG) in the TOSA. The Data Direction Register
bit for Port 1 Bit 0 should * be clear (zero) in order to gate
in the external input signal to the edge defect unit in the
timer.

Output Compare Register (SOOOB:OOOC)

The Output Compare Register is a 16-bit read/write
register which is used to control an output waveform.
The contents of this register are constantly compared
with the current value of the free running counter.
When a match is found a flag is set (OCF) in the Timer
Control and Status Register (TCSR) and the current
value of the Output Level bit (OLVL) in the TCSR is
7.22

S6801/S6803
*With Port 2 Bit 0 configured as an output and set to
"1", the external input will still be seen by the edge
detect unit.

• a match has been found between the value in the free
running counter and the output compare register,
and

Timer Control and Status Register (TCSR) (S0008)

• when $0000 is in the free running counter.

The Timer Control and Status Register consists of an
8-bit register of which al18 bits are readable but only the
low order 5 bits may be written. The upper three bits
contain read-only timer status information and indicate
that:

Each of the flags may be enabled onto the S6801 internal bus (R02) with an individual Enable bit in the TCSR.
If the 1-bit in the S6801 Condition Code Register has
been cleared, a priority vectored interrupt will occur
corresponding to the flag bit(s) set. A description for
each bit follows:

• a proper transition has taken place on the input pin
with a subsequent transfer of the current counter
value to the input capture register.
TIMER CONTROL

AND STATUS

ICF

OCF

TOF

EICI

EOCI

ETOI

o
IEDG

OLVL

$0008

Output Level- This value is clocked to the output level register on an output compare. If the DDR for Port 2 Bit 1 is set,
the value will appear on the output pin.

Bit 1 IEDG

Input Edge - This bit controls which transition of an input will trigger a transfer of the counter to the input capture
register. The DDR for Port 2 Bit 0 must clear for this function to operate.
IEDG = 0 Tranfer takes place on a negative (high-to-Iow transition).
IEDG = 1 Transfer takes place on a positive edge (Iow-to-high transition).

Bit 2 ElOl

Enable Timer Overflow Interrupt - When set, this bit enables IR02 to occur on the internal bus for a TOF Interrupt; when
clear the interrupt is inhibited.

Bit EOCI

Enable Output Compare Interrupt - When set, this bit enables IR02 to appear on the internal bus for an input capture interrupt; when clear the interrupt is inhibited.

Bit 4 EICI

Enable Input Capture Interrupt - When set, this bit enables IR02 to occur on the internal bus for an input capture interrupt; when clear the interrupt is inhibited.

Bit 5 TOF

Timer OverflOW Flag - This read-only bit is set when the cou nter contains $0000. It is cleared by a read of the TCSR (with
TOF set) followed by an MPU read of the Counter ($09).

Bit 6 OCF

Output Compare Flag - This read-only bit is set when a match is found between the output compare register and the free
running counter. It is cleared by a read of the TCSR (with ODF set) followed by an MPU write to the output compare
register ($OB or $OC).

Bit 7 CF

Input Capture Flag - This read-only status bit is:set by a proper transition on the input to the edge detect unit; it is cleared
by a read of the TCSR (with ICF set) followed by an MPU read of the input Capture Register ($OD).

and receiver communicate with the MPU via the data
bus and with the outside world via pins 2, 3, and 4 of
Port 2. The hardware, software, and registers are
explained in the following paragraphs.

Seriai Communications Interface

The S6801 contains a full-duplex asynchronous serial
communications interface (SCI) on board. Two serial
data formats (standard mark/space [NRZ] or Bi-phase)
are provided at several different data rates. The controller comprises a transmitter and a receiver which
operate independently of each other but in the same
data format and at the same data rate. Both transmitter

Wake-up Feature

In a typical multi-procesor application, the software
protocol will usually contain a destination address in
the initial byte(s) of the message. In order to permit non-

7.23

AIMII.---------.""4.

A Subsidiary
of Gould Inc.

S6801/S6803
• interrupt requests - enabled or masked individually
for transmitter and receiver data registers
• clock output - internal clock enabled or disabled to
Port 2 (Bit 2)
• Port 2 (Bits 3 and 4) - dedicated or not dedicated to
serial 1/0 individually for transmitter and receiver

selected MPU's to ignore the remainder of the
message, a wake-up feature is included whereby all further interrupt processing may be optionally inhibited
until the beginning of the next message. When the next
message appears, the hardware re-enables (or "wakesup") for the next message. The "wake-up" is automatically triggered by a string of ten consecutive 1's which
indicates an idle transmit line. The software protocol
must provide for the short idle period between any two
consecutive messages.

Serial Communications Hardware

The serial communications hardware is controlled by 4
registers as shown in Figure 21. The registers include:
•
•
•
•

Programmable Options

The following features of the S6801 serial 1/0 section
have programmable:
• format - standard mark/space (N RZ) or Bi-phase
• clock - external or internal
• Baud rate - one of 14 per given MPU2 clock
frequency or external clock X8 input
• wake-up feature - enabled or disabled

an 8-bit control and status register
a 4-bit rate and mode control register (write only)
an 8-bit read-only receive data register and
an 8-bit write-only transmit data register

In addition to the four registers, the serial 1/0 section
utilizes Bit 3 (serial input) and Bit 4 (serial output) or Port
2. Bit 2 of Port 2 is utilized if the internal-clock-out or
external-clock-in options are selected.

Figure 21. Serial 1/0 Registers
CONTROL AND STATUS REGISTER $0011, READ/WRITE
EXCEPT ..... (READ ONLY)

7
RDRF

6
ORFE

5
TORE

4
RIE

2
TIE

RATE AND MODE REGISTER $0010, WRITE ONLY

CCl

CCO

PORT 2 BIT 3
E]RX
PORT 2 BIT 2

EXT CLK IN/INT CLK OUT
(NOT USER ADDRESSABLE)

PORT 2 BIT 4

~~~~--~~--~--~~--~--~~--~--~~~

7.24

86801/86803
Transmit/Receive Control and Status (TRCS) Register

The TRCS register consists of an a-bit register of which all a bits may be read while only bits 0-4 may be written. The
register is initialized to $20 on RESET. The bits in the TRCS register are defined as follows:

765
RDRE

OR FE

I TORE

RIE

TIE

o
TE

ADDR.$0011

Bit 0 WU

"Wake-up on Next Message - set by S6801 software cleared by hardware on receipt of ten consecutive l' s.

Bit 1 TE

Transmit Enable - set by S6801 to produce preamble of nine consecutive l' s and to enable gating of transmitter output
to Port 2, Bit 4 regardless of OOR value corresponding to this bit; when clear, serial I/O has no effect on Port 2 Bit 4.

Bit 2 TIE

Transmit Interrupt Enable - when set, will permit an IRQ2 interrupt to occur when Bit 5 (TORE) is set; when clear, the
TORE value is masked from the bus.

Bit 3 RE

Receiver Enable - when set, gates Port 2 Bit 3 to input of receiver regardless of OOR value for this bit; when clear, serial
I/O has no effect on Port 2 Bit 3.

Bit 4 RIE

Receiver Interrupt Enable - when set, will permit an IRQ2 interrupt to occur when Bit 7 (RDRF) or Bit 6 (OR) is set; when
clear, the interrupt is masked.

Bit 5 TORE

Transmit Data Register Empty - set by hardware when a transfer is made from the transmit data register to the output
shift register. The TORE bit is cleared by reading the status register, then writing a new byte into the transmit data
register, TORE is initialized to 1 by RESET.

Bit 6 ORFE

Over-Run-Framing Error - set by hardware when an overrun or framing error occurs (receive only). An overrun is defined
as a new byte received with last byte still in Data Register/Buffer. A framing error has occurred when the byte boundaries in bit stream are not synchronized to bit counter. The ORFE bit is cleared by reading the status register, then
reading the Receive Data Register, or by RESET.

Bit 7 RDRF

Receiver Data Register Full- set by hardware when a transfer from the input shift register to the receiver data register is
made. The RORF bit is cleared by reading the status register, then reading the Receive Data Register, or by RESET.

Rate and Mode Control Register

The Rate and Mode Control register controls the following serial 1/0 variables:
•
•
•
•

Baud rate
format
Clock source, and
Port 2 Bit 2 configuration

The register consists of 4 bits all of which are write-only and cleared on RESET. The 4 bits in the register may be considered as a pair of 2-bit fields. The two low order bits control the bit rate for internal clocking and the remaining two
bits control the format and clock select logic. The register definition is as follows:

CC1

CCO

7.25

o
so

ADDR.$0010

•

AIMII.---------.~
~

A Subsidiary
of Gould Inc.

86801186803
Bit 080
Bit 1 81

Speed Select - These bits select the Baud rate for the internal clock. The four rates which may be selected are a function
of the MPU +2 clock frequency. Table 4 lists the available Baud rate.

Bit 2 CCO
Bit 3 CC1

Clock Control and Format Select - This 2-bit field controls the format and clock select logic. Table 5 defines the bit field.

Table 4. SCI Internal Baud Rates
S1, SO

XTAL

4.0MHz

4.9152MHz

2.5476MHz

00
01
10
11

+2
+2 + 16
+2 + 128
+2 + 1024
+2 + 4096

1.0MHz
62.5K BITS/S
7,812.58ITS/S
976.6 8ITS/S
244.1 8ITS/S

1.2288MHz
76.8K 8ITS/S
9,600 8ITS/S
1,200 8ITS/S
300 8ITS/S

0.6144MHz
38.4K 8ITS/S
4,800 8ITS/S
600 8ITS/S
150 8ITS/S

Table 5. Bit Field
CC1, CCO

FORMAT

CLOCK SOURCE

PORT 2 BIT 2

PORT 2 BIT 3

PORT 2 BIT 4

00
01
10
11

BI-PHASE
NRZ
NRZ
NRZ

INTERNAL
INTERNAL
INTERNAL
EXTERNAL

NOT USED
NOT USED
OUTPUT*
INPUT

**
**
SERIAL INPUT
SERIAL INPUT

**
**
SERIAL OUTPUT
SERIAL OUTPUT

*GLOGK OUTPUT IS AVAILABLE REGARDLESS OF VALUES FOR BITS RE AND TE.
**BIT 3 IS USED FOR SERIAL INPUT IF RE = "1" IN TRGS; BIT 4 IS USED FOR SERIAL OUTPUT IF TE = "1" IN TRGS.

Internally Generated Clock

• the maximum external clock frequency is 1.2MHz.

If the user wishes for the serial I/O to furnish a clock,
the following requirements are applicable:

Serial Operations

•
•
•
•

The Serial I/O hardware should be initialized by the
S6801 software prior to operation. This sequence will
normally consists of:

the values of RE and TE are immaterial
eC1, eeo must be set to 10
the maximum clock rate will be # 16
the clock will be at 1 x the bit rate and will have a
rising edge at mid·bit

• writing the desired operation control bits to the Rate
and Mode Control Register and
• writing the desired operational control bits in the
Transmit/Receive Control and Status Register.

Externally Generated Clock
If the user wishes to provide an external clock for the
serial I/O, the following requirements are applicable:

The Transmitter Enable (TE) and Receiver Enable (RE)
bits may be left set for dedicated operations.

• the CC1, ceo, field in the Rate and Mode Control
Register must be set to 11
• the external clock must be set to 8 times (x 8) the
desired baud rate and

Transmit Operations
The transmit operation is enabled by the TE bit in the
Transmit/Receive Control and Status Register. This bit
7.26

86801/86803
framing error is assumed, and bit ORFE is set. If the
tenth bit is 1, the data is transferred to the Receiver
Data Register, and interrupt flag RDRF is set. If RDRF is
still set at the next tenth bit time, ORFE will be set, indicating an over-run has occurred. When the S6801
responds to either flag (RDRF or ORFE) by reading the
status register followed by reading the Data Register
RDRF (or ORFE) will be cleared.

when set, gates the output of the serial transmit shift
register to Port 2 Bit 4 and takes unconditional control
over the Data Direction Register value for Port 2, Bit 4.
Following a RESET, the user should configure both the
Rate and Mode Control Register and the Transmit!
Receiver Control and Status Register for desired operation. Setting the TE bit during this procedure initiates
the serial output by first transmitting a ten-bit preamble
of 1s. Following the preamble, internal synchronization
is established and the transmitter section is ready for
operation.

Ram Control Register

At this point one of two situations exist:
a) if the Transmit Data Register is empty (TDRE = 1), a
continuous string of ones will be sent indicating an idle
line, or

This register, which is addressed at $0014, gives status
information about the standby RAM. An 0 in the RAM
enable bit (RAM E) will disable the standby RAM, thereby protecting it at power down if Vee is held greater
than VSBB volts, as explained previously in the signal
description for Vee Standby.

b) if data has been loaded into the Transmit Data
Register (TDRE = 0), the word is transferred to the output shift register and transmission of the data word will
begin.
During the transfer itself, the 0 start bit is first transmitted. Then the 8 data bits (beginning with bit 0) followed
by the stop bit, are transmitted. When the Transmitter
Data Register has been emptied, the hardware sets the
TDRE flag bit.

Bit
Bit
Bit
Bit
Bit
Bit

If the S6801 fails to respond to the flag within the proper
time, (TDRE is still set when the next normal transfer
from the parallel data register to the serial output
register should occur) then a1 will be sent (instead of a
0) at "Start" bit time, followed by more 1s until more
data is supplied to the data register. No Os will be sent
while TDRE remains a 1.

1
2
3
4
5
6

Bit 7

The Bi-phase mode operates as described above
except that the serial output toggles each bit time, and
on 1/2 bit times when a 1 is sent.
Receiver Operation

The receive operation is enabled by the RE bit which
gates in the serial input through Port 2 Bit 3. The
receiver section operation is conditioned by the contents of the Transmit/Receive Control and Status
Register and the Rate and Mode Control Register.

Not used.
Not used.
Not used.
Not used.
Not used.
The RAM ENABLE control bit allows the user
the ability to disable the standby RAM. This bit
is set to a logic "one" by reset which enables
the standby RAM and can be written to or zero
under program control. When the RAM is disabled, logic "zero", data is read from external
memory.
The STANDBY BIT of the control register,
$0014, is cleared when the standby voltage is
removed. This bit is a read/write status flag that
the user can read which indicates that the
standby RAM voltage has been applied, and the
data in the standby RAM is valid.

The S6801 provides up to 65K bytes of memory for program and/or data storage. The memory map is shown in
Figure 22.
Locations $0020 through $007F access external RAM
or I/O Internal RAM is accessed at $0080 through
$OOFF. The RAM may be alternately selected by mask
programming at location $AOOO. However, if the user
desires to access external RAM at those locations he
may do so by clearing the RAM ENABLE control bit of
the RAM Control Register. In this wayan extra 126

The receiver bit interval is divided into 8 sub-intervals
for internal synchronization. In the standard, non-Biphase mode, the received bit stream is synchronized by
the first 0 (space) encountered.
The approximate center of each bit time is strobed during the next 10 bits. If the tenth bit is not a 1 (stop bit) a
7.27

AIMII.---------."""'-

A Subsidiary
of Gould Inc.

86801186803
A12 and A13 as zeros or ones to provide for $C800,
$0800, $E800 for the ROM address. A12 and A13 may
also be don't care in this decoder. The primary address
for the ROM will be $F800.

bytes of external RAM are available. The first 64 bytes
of the 128 bytes of on-chip RAM are provided with a
separate power supply. This will maintain the 64 bytes
of RAM in the power down mode as explained in the pin
description for Vee Standby.

The first 32 bytes are for the special purpose registers
as shown in Table 6.

Figure 22. Memory Map
Table 6. Special Registers
soooo 'I

i ]

SPECIAL
PURPOSE

I
I

: ]
I

EXTERNAL
RAM OR UO

I
I

I ]
I

-------11
I

1-.

SOO1F :
S0020

S007F
S0080

1 .~.."."

I
II

I ]
:

HEX ADDRESS
00
01
02
03

05
SOOFF
S0100

•

I
I
som I

$0200 :

I
I

06
07
08
09

EXTERNAL RAM
OR UO FOR
NON·MULTlPLEXED
MODE

OA
OB
OC
00
OE

EXTERNAL RAM
OR ROM OR UO

I
I
I
i---------I

10
11

12
13
14

REGISTER
DATA DIRECTION 1
DATA DIRECTION 2
I/O PORT 1
I/O PORT 2
DATA DIRECTION 3
DATA DIRECTION 4
I/O PORT 3
I/O PORT 4
TCSR
COUNTER HIGH BYTE
COUNTER LOW BYTE
OUTPUT COMPARE HIGH BYTE
OUTPUT COMPARE LOW BYTE
INPUT CAPTURE HIGH BYTE
INPUT CAPTURE LOW BYTE
I/O PORT 3 CIS REGISTER
SERIAL RATE AND MODE REGISTER
SERIAL CONTROL AND STATUS REGISTER
SERIAL RECEIVER DATA REGISTER
SERIAL TRANSMIT DATA REGISTER
RAM/EROM CONTROL REGISTER

15-1 F RESERVED

Figure 23. Memory Map for Interrupt Vectors

Locations $0100 through $01 FF are available in the
Expanded Non-Multiplexed Mode. The eight address
lines of Port 4 make this 256 word expandability possible. Those not needed for address lines can be used as
input lines instead.

VECTOR
MS
Highest Priority

The full range of addresses available to the user is in
the Expanded Multiplexed Mode. Locations $0200
through $F7FF can be used as external RAM, external
ROM, or "0. Any higher order bit not required for
addressing can be used as 110 as in the Expanded NonMultiplexed Mode.
Lowest Priority

The internal ROM is located at $F800 through $FFFF.
The decoder for the ROM may be mask programmed on
7.28

DESCRIPTION

LS
Restart

FFFE,

FFFF

FFFC,

FFFD

Non·Maskabie Intenupt

FFFA,

FFFD

Software Intenupt

FFF8,

FFF9

IR0111ntenupt Strobe S

FFF6,

FFF7

IR02lTimer Input Capture

FFF4,

FFF5

IR02lTimer Output Compare

FFF2,

FFF3

IR02mmer Overflow

FFFO,

FFF1

IR02/Serlal I/O Intenupt

86801186803
General Description of Instruction Set
The S6801 is upward object code compatible with the
S6800 as it implements the full S6800 instruction set.
The execution times of key instructions have been
reduced to increase throughput. In addition, new
instructions have been added; these include 16-bit
operations and a hardware multiply.
Included in the instruction set section are the following:
• MPU Programming Model (Figure 24)
• Addressing modes
• Accumulator and memory instructions- Table 7
• New instructions
• Index register and stack manipulations- Table 8
• Jump and branch instructions- Table 9
• Special operations- Figure 25
• Condition code register manipulation instructionsTable 10
• Instruction Execution times in machine cyclesTable 11
• Summary of cycle by cycle operation- Table 12
MPU Programming Model
The programming model for the S6801 is shown in
Figure 24. The double (D) accumulator is physically the
same as the A Accumulator concatenated with the B
Accumulator so that any operation using accumulator
o will destroy information in A and B.
Figure 24. MCU Programming Model
7

I
I
I
I
I
15

ACCA

II
ACCO

ACCB

ACCUMULATOR B

ACCUMULATOR 0

INDEX REGISTER

I
I

PROGRAM COUNTER

STACK POINTER

CONOITION CODE
C REGISTER

CARRY (from Bit 7)
OVERFLOW
ZERO
NEGATIVE
INTERRUPT MASK
HALF CARRY (from Bit 3)

MPU Addressing Modes
The S6801 eight-bit microcomputer unit has seven
address modes that can be used by a programmer, with
the addressing mode a function of both the type of instruction and the coding within the instruction. A summary of the addressing modes for a particular instruction can be found in Table 11 along with the associated
instruction execution time that is given in machine
cycles. With a clock frequency of 4MHz, these times
would be microseconds.
Accumulator (ACCX) Addressing-In accumulator only
addressing, either accumulator A or accumulator B is
. specified. These are one-byte instructions.
Immediate Addressing-In immediate addressing, the
operand is contained in the second byte of the instruction except LOS and LOX which have the operand in the
second and third bytes of the instruction. The MCU
addresses this location when it fetches the immediate
instruction for execution. These are two or three-byte
instructions.
Direct Addressing-In direct addressing, the address of
the operand is contained in the second byte of the instruction. Direct addressing allows the user to directly
address the lowest 256 bytes in the machine Le., locations zero through 255. Enhanced execution times are
achieved by storing data in these locations. In most
configurations, it should be a random access memory.
These are two-byte instructions.
Extended Addressing-In extended addressing, the
address contained in the second byte of the instruction
is used as the higher eight-bits of the address of the
operand. The third byte of the instruction is used as the
lower eight-bits of the address for the operand. This is
an absolute address in memory. These are three-byte
instructions.
Indexed Addressing-In indexed addressing, the
address contained in the second byte of the instruction
is added to the index register's lowest eight bits in the
MCU. The carry is then added to the higher order eight
bits of the index register. This result is then used to
address memory. The modified address is held in a
temporary address register so there is no change to the
index register. These are two-byte instructions.
Implied Addressing-In the implied addressing mode
the instruction gives the address (Le., stack pointer, index register, etc.). These are one-byte instructions.
Relative Addressing-In relative addressing, the
address contained in the second byte of the instruction
is added to the program counter's lowest eight bits plus
two. The carry or borrow is then added to the high eight
bits. This allows the user to address data within a range
of - 125 to + 120 bytes of the present instruction.
These are two-byte instructions.
7.29

•

~1~ll~~~~~
."""4.
~

A Subsidiary
of Gould Inc.

86801/86803
Table 7. Accumulator & Memory Instructions
ACCUMULATOR AND
MEMORY
Operations

MNEMONIC

ADDRESSING MODES
IMMED. DIRECT INDEX EXTEND INHERENT
OP f'\J # OP f'\J # OP f'\J # OP f'\J # OP f'\J #

5 4 3 2 1 0
Booleanl Arithmetic
Operation

ADDA

8B 2 2 9B 3 2 AB 4 2 BB 4 3

A+M-A

AD DB

CB 2 2 DB 3 2 EB 4 2 FB 4 3

B+M-B

ADD DOUBLE

AD DO

C3 4 3 03 5 2 E3 6 2 F3 6 3

ADD ACCUMULATORS

ABA

ADD WITH CARRY

ADCA

89 2 2 99 3 2 A9 4 2 B9 4 3

A+ M + C-A

ADCB

C9 2 2 09 3 2 E9 4 2 F9 4 3

B+ M +C-B

ANDA

84 2 2 94 3 2 A4 4 2 B4 4 3

A M-A

ANDB

C4 2 2 04 3 2 E4 4 2 F4 4 3

B M-B

BIT A

85 2 2 95 3 2 A5 4 2 B5 4 3

BIT B

C5 2 2 05 3 2 E5 4 2 F5 4 3

ADD

AND

BIT TEST

CLEAR

COMPARE

4F 2 1

00 -A

CLRB

5F 2 1

00 -B

CMPA

81 2 2 91 3 2 A1 4 2 B1 4 3

CMPB

C1 2 2 01 3 2 E1 4 2 F1 4 3

COMPLEMENT, 1'S

COM

B-M
11 2 1

A-B
M-M

63 6 2 73 6 3
43 2 1

A-A

COMB

53 2 1

B-B

NEG

(NEGATE)

NEGA

OC- M-M

60 6 2 70 6 3
40 2 1
50 2 1

NEGB

19 2 1

DAA
DEC

4A 2 1
5A 2 1

DECB

OO-A-A
00- 6-B

A-1-A
B-1-B

EORA

88 2 2 98 3 2 A8 4 2 B8 4 3

A~M-A

EORB

C8 2 2 08 3 2 E8 4 2 F8 4 3

B~M-B

9C 6 2 7C 6 3

M+1-M

INC
INCA
INCB

4C 2 1

A+1-A

5C 2 1

B+1-B

LDAA

86 2 2 96 3 2 A6 4 2 B6 4 3

M-A

LDAB

C6 2 2 06 3 2 E6 4 2 F6 4 3

M-B

LOAD DOUBLE ACCUMULATOR

LOAD

CC 3 3 DC 4 2 EC 5 2 FC 5 3

M+A M+1-B

MULTIPLY UNSIGNED

MUL

LOAD ACCUMULATOR

OR, INCLUSIVE

3D 10 1

AxB-AB

ORAA

8A 2 2 9A 3 2 AA 4 2 BA 4 3

A+M-A

ORAB

CA 2 2 DA 3 2 EA 4 2 FA 4 3

B+M-B

The Condition Code Register notes are listed after Table 10.

7.30

·· tt tt
·t ·· tt tt
·t t
t
t

t
·
·· ·· tt
·· ·· tt
·· ··

t
t
t
t
t
t t
t R
t R
t R
t R

t
t
t
t
t
t

··
·

R S R R
R S R R

·· ·· t t t t
·· ·· tt tt tt tt
· ·· tt tt
·· · t t
·· ·· tt tt CDCD
R S R R

R S

R S
R S

Converts binary add of
BCD characters into BCD •
format
M-1-M

6A 6 2 7A 6 3

DECA

INCREMENT

A-M

COMA

COMPLEMENT, 2'S

EXCLUSIVE OR

CLRA

CBA

DECREMENT

A+B-A

00 -M

6F 6 2 7F 6 3

CLR

COMPARE ACCUMULATORS

DECIMAL ADJUST, A

A:B+ M:M + 1-A:B
1B 2 1

H I N Z V C

·· ·· tt tt Zero

BGT

2E 4 2

Branch If Higher

BHI

22 4 2

C+Z=O

BlE

2F 4 2

Z+(N C

H
C
ABA
ABX
ADC
ADD
ADDD
AND
ASL
ASLD
ASR
BCC
BCS
BEQ
BGE
BGT
BHI
BIT
BLE
BLS
BLT
BMI
BNE
BPL
BRA
BSR
BVC
BVS
CBA
CLC
CLI
CLR
CLV
CMP
COM
CPX
DAA
DEC
DES
OEX
EOR
INC
INS

1&.1

•
:E

U
1&.1

~
Z
j:!:!
>C
1&.1

CI
1&.1
>C
1&.1
CI

iii

~
iii

-'
1&.1
II:

II:

2
3

3
3
5
3

4
4
6
4
6

•
3

•

6
3
3
3
3
3
3

•

3
3
3
3
3
3
3

6
3
3

•
4

4
6
6

•
3
3
3

•

4
6
3

j:!:!

1&.1

!i
1&.1

•

INX
JMP
JSR
LOA
LOD
LOS
LOX
LSR
LSRD
MUL
NEG
NOP
ORA
PSH
PSHX
PUL
PULX
ROL
ROR
RTI
RTS
SBA
SBC
SEC
SEI
SEV
STA
STD
STS
STX
SUB
SUBD
SWI
TAB
TAP
TBA
TPA
TST
TSX
TXS
WAI

7.35

1&.1

:II

~
z
j:!:!

CI
1&.1
>C
1&.1
CI

>C
1&.1

iii

!Z
UoI
II:
1&.1

iii

5
3

6
4

•

3
3
3

4
4
4

5
5
5

•

5
3

•

•
•

•

6
6

•
2

•

10
6
2
4

4
2
2

•
•
4

4
4
5

5
5

6
6

12
2
2

•

-'
w

II:

1&.1

6
3

~l~ll~~~~~
."""4.
~

A Subsidiary
of Gould Inc.

86801/86803
Summary of Cycle by Cycle Operation
Table 12 provides a detailed description of the information present on the Address Bus, Data Bus, and the
ReadlWrite line (R/W) during each cycle for each instruction.
This information is useful in comparing actual with expected results during debug of both software and hardware as
the control program is executed. The information is categorized in groups according to addressing mode and
number of cycles per instruction. (In general, instruct'ions with the same addressing mode and number of cycles execute in the same manner; exceptions are indicated in the table).
Table 12. Cycle by Cycle Operation
ADDRESS MODE &
INSTRUCTIONS

CYCLE

R/W
LINE

ADDRESS BUS

DATA BUS

IMMEDIATE
ADC EOR
ADD LDA
AND ORA
BIT SBC
CMP SUB
LDS
LDX

2
3

CPX
SUBD
ADDD

2
3
4

OP CODE ADDRESS'
OP CODE ADDRESS + 1

OP CODE
OP'ERAND DATA

OP CODE ADDRESS
OP CODE ADDRESS + 1
OP CODE ADDRESS + 2

OP CODE
OPERAND DATA (High Order Byte)
OPERAND DATA (Low Order Byte)

OP CODE ADDRESS
OP CODE ADDRESS + 1
OP CODE ADDRESS + 2
ADDRESS BUS FFFF

OP CODE
OPERAND DATA (High Order Byte)
OPERAND DATA (Low Order Byte)
LOW BYTE OF RESTART VECTOR

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS OF OPERAND

OP CODE
ADDRESS OF OPERAND
OPERAND DATA

DIRECT
ADC EOR
ADD LOA
AND ORA
BIT SBC
CMP SUB

STA

2
3

2
3
LDS
LDX
LDD

STS
STX
STD

CPX
SUBD
ADDD

JSR

2
3
4
1
2

3
4
1

2
3
4
5
1
2

3
4
5

OP CODE ADDRESS
OP CODE ADDRESS + 1
DESTINATION ADDRESS

1
1

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS OF OPERAND
OPERAND ADDRESS + 1
OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS OF OPERAND
ADDRESS OF OPERAND + 1

OP CODE
ADDRESS OF OPERAND
OPERAND DATA (High Order Byte)
OPERAND DATA (Low Order Byte)
1
1

o
o

OP CODE ADDRESS
OP CODE ADDRESS + 1
OPERAND ADDRESS
OPERAND ADDRESS + 1
ADDRESS BUS FFFF
OP CODE ADDRESS
OP CODE ADDRESS + 1
SUBROUTINE ADDRESS
STACK POINTER
STACK POINTER + 1

OP CODE
DESTINATION ADDRESS
DATA FROM ACCUMULATOR

OP CODE
ADDRESS OF OPERAND
REGISTER DATA (High Order Byte)
REGISTER DATA (Low Order Byte)
OP CODE
ADDRESS OF OPERAND
OPERAND DATA (High Order Byte)
OPERAND DATA (Low Order Byte)
LOW BYTE OF RESTART VECTOR

1
1
1

o
o

OP CODE
IRRELEVANT DATA
FIRST SUBROUTINE OP CODE
RETURN ADDRESS (High Order Byte)
RETURN ADDRESS (Low Order Byte)
(continued)

7.36

86801186803
Table 12. Cycle by Cycle Operation (continued)
ADDRESS MODE &
INSTRUCTIONS

ADDRESS BUS

DATA BUS

INDEXED
JMP

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF

1
1
1

OP CODE
OFFSET
LOW BYTE OF RESTART VECTOR

ADC EOR
ADD LOA
AND ORA
BIT SBC
CMP SUB

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF
INDEX REGISTER PLUS OFFSET

1
1
1
1

OP CODE
OFFSET
LOW BYTE OF RESTART VECTOR
OPERAND DATA

STA

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF
INDEX REGISTER PLUS OFFSET

1
1
1

OP CODE
OFFSET
LOW BYTE OF RESTART VECTOR
OPERAND DATA

LOS
LOX
LDD

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF
INDEX REGISTER PLUS OFFSET
INDEX REGISTER + 1

1
1
1
1
1

OP CODE
OFFSET
LOW BYTE OF RESTART VECTOR
OPERAND DATA (High Order Byte)
OPERAND DATA (Low Order Byte)

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF
INDEX REGISTER PLUS OFFSET
INDEX REGISTER PLUS OFFSET

1
1
1

OP CODE
OFFSET
LOW BYTE OF RESTART VECTOR
OPERAND DATA (High Order Byte)
OPERAND DATA (Low Order Byte)

4
1
2
3

4
5
STS
STX
STD

1
2
3

4
5
ASL LSR
ASR NEG
CLR ROL
COM ROR
DEC TST (1)
INC

CPX
SUBD
ADDD

2
3

4
5
6
1

2
3

4
5
6
JSR

1
2
3

4
5
6

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF
INDEX REGISTER PLUS OFFSET
ADDRESS BUS FFFF
INDEX REGISTER PLUS OFFSET

0
0
1
1
1
1
1

OP CODE
OFFSET
LOW BYTE OF RESTART VECTOR
CURRENT OPERAND DATA
CURRENT OPERAND DATA
NEW OPERAND DATA

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF
INDEX REGISTER + OFFSET
INDEX REGISTER + OFFSET
ADDRESS BUS FFFF

1
1
1
1
1

OP CODE
OFFSET
LOW BYTE OF RESTART VECTOR
OPERAND DATA (High Order Byte)
OPERAND DATA (Low Order Byte)
LOW BYTE OF RESTART VECTOR

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF
INDEX REGISTER + OFFSET
STACK POINTER
STACK POINTER + 1

1
1
1
1

0
0

OP CODE
OFFSET
LOW BYTE OF RESTART VECTOR
FIRST SUBROUTINE OP CODE
RETURN ADDRESS (Low Order Byte
RETURN ADDRESS (High Order Byte)

OP CODE ADDRESS
OP CODE ADDRESS + 1
OP CODE ADDRESS

1
1
1

OP CODE
JUMP ADDRESS (High Order Byte)
JUMP ADDRESS (Low Order Byte)

EXTENDED
JMP

2
3

(continued)

7.37

•

AIMII.---------."ff!/!!(.

A Subsidiary
of Gould Inc.

S6801/S6803
Table 12. Cycle by Cycle Operation (continued)
ADDRESS MODE &
INSTRUCTIONS

ADDRESS BUS

DATA BUS

EXTENDED
. l'
1
1
1

ADC EOR
ADD LOA
AND ORA
BIT SBC
CMP SUB

1
2
3
4

OP CODE ADDRESS
OP CODE ADDRESS + 1
OP CODE ADDRESS + 2
ADDRESS OF OPERAND

STA A
STA B

1
2
3
4

OP CODE ADDRESS
OP CODE ADDRESS + 1
OP CODE ADDRESS + 2
OPERAND DESTINATION ADDRESS

OP CODE
DESTINATION ADDRESS (High Order Byte)
DESTINATION ADDRESS (Low Order Byte)
DATA FROM THE ACCUMULATOR

LOS
LOX
LDD

1
2
3
4

OP CODE ADDRESS
OP CODE ADDRESS + 1
OP CODE ADDRESS + 2
ADDRESS OF OPERAND
ADDRESS OF OPERAND + 1

1
1
1
1
1

OP CODE
ADDRESS
ADDRESS
OPERAND
OPERAND

OF OPERAND (High Order Byte)
OF OPERAND (Low Order Byte)
DATA (High Order Byte)
DATA (Low Order Byte)

STS
STX
STD

OP CODE ADDRESS
OP CODE ADDRESS + 1
OP CODE ADDRESS + 2
ADDRESS OF OPERAND
ADDRESS OF OPERAND

1
1
1

OP CODE
ADDRESS
ADDRESS
OPERAND
OPERAND

OF OPERAND (High Order Byte)
OF OPERAND (Low Order Byte)
DATA (High Order Byte)
DATA (Low Order Byte)

5
1
2
3
4

5
ASL LSR
ASR NEG
CLR ROL
COM ROR
DEC TST (1)
INC

CPX
SUBD
ADDD

JSR

1
2
3
4

5
6

OP CODE ADDRESS
OP CODE ADDRESS + 1
OP CODE ADDRESS + 2
ADDRESS OF OPERAND
ADDRESS BUS FFFF
ADDRESS OF OPERAND

1
1
1

0
0
1
1
1
1
1

OP CODE
ADDRESS OF OPERAND
ADDRESS OF OPERAND (Low Order Byte)
OPERAND DATA

OP CODE
ADDRESS OF OPERAND (High Order Byte)
ADDRESS OF OPERAND (Low Order Byte)
CURRENT OPERAND DATA
LOW BYTE OF RESTART VECTOR
NEW OPERAND DATA

5
6

OP CODE ADDRESS
OP CODE ADDRESS + 1
OP CODE ADDRESS + 2
OPERAND ADDRESS
OPERAND ADDRESS + 1
ADDRESS BUS FFFF

1
1
1
1
1

OP CODE
OPERAND ADDRESS
OPERAND ADDRESS (Low Order Byte)
OPERAND DATA (High Order Byte)
OPERAND DATA (Low Order Byte)
LOW BYTE OF RESTART VECTOR

1
2

OP CODE ADDRESS
OP CODE ADDRESS + 1

1
1

OP CODE ADDRESS + 2

5
6

SUBROUTINE STARTING ADDRESS
STACK POINTER
STACK POINTER -1

0
0

OP CODE
ADDRESS OF SUBROUTINE
(High Order Byte)
ADDRESS OF SUBROUTINE
(High Order Byte)
OP CODE OF NEXT INSTRUCTION
RETURN ADDRESS (Low Order Byte
ADDRESS OF OPERAND (High Order Byte)

1
2

OP CODE ADDRESS
OP CODE ADDRESS + 1

1
1

OP CODE
OP CODE OF NEXT INSTRUCTION

1
2
3
4

INHERENT
ABA DAA SEC
ASL DEC SEI
ASR INC SEV
CBA LSR TAB
CLC NEG TAP
CLI NOP TBA
CLR ROL TPA
CLV ROR TST
COM SBA

7.38

(continued)

56801/56803
Table 12. Cycle by Cycle Operation (continued)
ADDRESS MODE ,.
INSTRUCTIONS

ADDRESS BUS

DATA BUS

INHERENT

ABX

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF

1
1
1

OP CODE
IRRELEVANT DATA
LOW BYTE OF RESTART VECTOR

ASLD
LSRD

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF

1
1
1

OP CODE
IRRELEVANT DATA
LOW BYTE OF RESTART VECTOR

DES
INS

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS + 1
PREVIOUS REGISTER CONTENTS

1
1
1

OP CODE
OP CODE OF NEXT INSTRUCTION
IRRELEVANT DATA

INX
DEX

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF

1
1
1

OP CODE
OP CODE OF NEXT INSTRUCTION
LOW BYTE OF RESTART VECTOR

PSHA
PSHB

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS
STACK POINTER

1
1
0

OP CODE
OP CODE OF NEXT INSTRUCTION
ACCUMULATOR DATA

ISX

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS + 1
STACK POINTER

1
1
1

OP CODE
OP CODE OF NEXT INSTRUCTION
IRRELEVANT DATA

TXS

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF

1
1
1

OP CODE
OP CODE OF NEXT INSTRUCTION
LOW BYTE OF RESTART VECTOR

PULA
PULB

1
2
3
4

OP CODE ADDRESS
OP CODE ADDRESS + 1
STACK POINTER
STACK POINTER

1
1
1
1

OP CODE
OP CODE OF NEXT INSTRUCTION
IRRELEVANT DATA

PSHX

1
2
3
4

OP CODE ADDRESS
OP CODE ADDRESS + 1
STACK POINTER
STACK POINTER-1

1
1

0
0

OP CODE
IRRELEVANT DATA
INDEX REGISTER (Low Order Byte)
INDEX REGISTER (High Order Byte)

PULX

1
2
3
4
5

OP CODE ADDRESS
OP CODE ADDRESS + 1
STACK POINTER
STACK POINTER + 1
STACK POINTER + 2

1
1
1
1
1

OP CODE
IRRELEVANT DATA
IRRELEVANT DATA
INDEX REGISTER (High Order Byte)
INDEX REGISTER (Low Order Byte)

BCC
BCS
BEQ
BGE
BGT

1
2
3

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF

1
1
1

OP CODE
BRANCH OFFSET
LOW BYTE OF RESTART VECTOR

1
2
3
4
5

OP CODE ADDRESS
OP CODE ADDRESS + 1
ADDRESS BUS FFFF
SUBROUTINE STARTING ADDRESS
STACK POINTER
STACK POINTER-1

1
1
1
1
0
0

OP CODE
BRANCH OFFSET
LOW BYTE OF RESTART VECTOR
RETURN ADDRESS (Low Order Byte)
RETURN ADDRESS (Low Order Byte)
RETURN ADDRESS (High Order Byte)

BSR

BHT BNE
BLE BPL
BLS BRA
BLT BVC
BMT BVS

7.39

•

AIMII.
• """4.

A Subsidiary
of Gould Inc.

S68011S6803

Figure 26. 56801 E MCU 5ing l&Chip Mode
EXTERNAL
OSCILLATOR

ENABLE

MAIN
MICROPROCESSOR

-V
16

V
~

-V
~
PORT 4
ADDRESS
BUS

RANDOM
ACCESS
MEMORY

PERIPHERAL
INTERFACE
ADAPTER

S6801E
PERIPHERAL
PROCESSOR

PORT 3
DATA
BUS

Figure 27. 56801 MCU 5ingl&Chip Dual Processor Configuration
Vee

Vee

ENABLE

PORT 1
8 PARALLEL
VO

PORT 3
DATA TRANSFER LINES

PORT 4
8 PARAllEL
VO

PORT 2
8 PARAllEl
VO

Vss

7.40

86801186803

Figure 28. 56801 MCU Expanded
Nort-Multiplexed Mode

Figure 29. 56801 E Expanded
Nort-Multiplexed Mode

EXTERNAL
OSCILLATOR

ENABLE

S6801
MCU

S6801E
MCU

RANDOM
ACCESS
MEMORY
RAM

PERIPHERAL
INTERFACE
ADAPTER
PIA

GENERAL
PURPOSE
INTERFACE
ADAPTER

ADDRESS
BUS

GPiA

DATA
BUS

7.41

AIMII.---------."""4.

A Subsidiary
of Gould Inc.

86801/86803

Figure 30. 86801 MCU Expanded
Multiplexed Mode

ADDRESS
BUS

Figure 31. 86801 E Expanded
Multiplexed Mode

RDM

RAM

PIA

GPiA

PTM

DATA
BUS

ADDRESS
BUS

7.42

DATA
BUS

S6801/S6803
Table 13. Mode and Port Summary
MCU

...
=
=
CD
fn

~
=
=

MODE

PORT 1
Eight Lines

PORT 2
Five Lines

PORT 3
Eight Lines

PORT 4
Eight Lines

CC1

CC2

SC1

SC2

SINGLE CHIP

liD

XTAL1(1)

XTAL2(1)

IS3(0)

OS3(0)

EXPANDED MUX

liD

ADDRESS BUS
(AO-A?)
DATA BUS
(00-07)

ADDRESS BUS*
(A8-A15)

XTAL1(1)

XTAL2(1)

AS(O)

R/W(O)

EXPANDED NON-MUX

liD

1/0

DATA BUS
(00-07)

ADDRESS BUS*
(AO-A?)

XTAL1(1)

XTAL2(1)

10S(0)

R/W(O)

SINGLE CHIP

liD

ADDRESS BUS
(DO-D7)

1/0

R/W(I)

RSO(I)

CS3(1)

OS3(0)

EXPANDED MUX

liD

1/0

ADDRESS BUS
(AO-A7)
DATA BUS
(DO-D7)

ADDRESS BUS*
(A8-A15)

HALT(I)

BA(O)

AS(O)

R/W(O)

EXPANDED NON-MUX

liD

1/0

DATA BUS
(DO-D7)

ADDRESS BUS*
(AO-A7)

HALT(I)

BA(O)

AS(O)

R/W(O)

CD
fn

*These lines can be substituted for I/O (Input Only) starting with the most significant address line.
I = Input
R/W= Read/Write
IS = Input Strobe
lOS = I/O Select
0= Output
CC = Crystal Control
OS = Output Strobe
CS = Chip Select
BA = Bus Available

AS = Address Strobe
SC = Strobe Control

7.43

AIMII.---------r

."""-

A Subsidiary
of Gould Inc.

S6802/A/B/S6808/A/B

MICROPROCESSOR
WITH CLOCK AND RAM

Features
o On-Chip Clock Circuit
o 128x8-Bit On-Chip RAM (56802)
o 32 Bytes of RAM Are Retainable (56802)
o Software-Compatible With the 56800
o Expandable to 64K Words
o 5tandard TIL-Compatible Inputs and Outputs
o 8-Bit Word 5ize
o 16-Bit Memory Addressing
o Interrupt Capability
o Clock Rates:
56802/56808-1.0MHz
568A02/568A08 -1.5M Hz
568B02/568B08-2.0MHz

General Description
The 56802156808 are monolithic 8-bit microprocessors
that contain all the registers and accumulators of the
present 56800 plus an internal clock oscillator and
driver on the same chip. In addition, the 56802 has 128
bytes of RAM on board located at hex addresses 0000
to 007E. The first 32 bytes of RAM, at addresses 0000 to
001 F, may be retained in a low power mode by utilizing
Vee standby, thus facilitating memory retention during
a power-down situation. The 56808 is functionally identical to the 56802 except for the 128 bytes of RAM. The
56808 does not have any RAM.
The 56802/56808 are completely software compatible
with the 56800 as well as the entire 56800 family of
parts. Hence, the 56802/56808 are expandable to 64K
words. When the 56802 is interfaced with the 56846
ROM-I/O-Timer chip, as shown in the Block Diagram
below, a basic 2-chip microcomputer system is realized.

Typical Microcomputer Block Diagram

Vee

Pin Configuration

Vee

Vee
STANDBY

'l:e

Vss

Vee

HALt
'-1R

RESEf
EXTAL
XTAL

IRQ
VMA
COUNTER/
TIMER I/O

{

56846
ROM. I/O. TIMER

liM!
BA

VMA
CLOCK

PARALLEL

110

Vee STAND

eso

~ESft

2K BYTES ROM
10 I/O LINES
J LINES TIMER
DO - D)

RtW

DO - D)

XTAL
AD - A15

AD - A15

EXTAL

A15

A14

All

J9PF

,JJ9PF
':'

BLOCK DIAGRAM Of A TYPICAL COST EffECTIVE MICROCOMPUTER THE MPU IS THE CENTER Of THE MICROCOMPUTER SYSTEM AND IS
SHOWN IN A MINIMUM SYSTEM INTERfACING WITH A ROM COMBINATION CHIP. IT IS NOT INTENOEO THAT THIS SYSTEM BE LIMITED TO
THIS fUNCTION BUT THAT IT BE EXPANDABLE WITH OTHER PARTS IN THE S6BOO MICROCOMPUTER fAMIL Y

7.44

RtW

Vee

AID

Al2

All

Vss

S6802/A/B/S6808/A/B
Absolute Maximum Ratings
Supply Voltage, Vee ............................................................................................................................. - 0.3V to + 7.0V
Input Voltage, VIN ................................................................................................................................. - 0.3V to + 7.0V
Operating Temperature Range, TA ............................................................................................................. 0° to + 70 0
Storage Temperature ~ange, Tstg ................................................................................................... - 55°C to + 150 0
Thermal Resistance, t3JA
Plastic ........................................................................................................................................................... 100°C/W
Ceramic ........................................................................................................................................................... 50°C/W

e
e

This device contains circuitry to protect the inputs against damage due to high static voltage or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.

D.C. Characteristics:
(Vee
5.0V ± 5%, Vss

8ymbol

= O,TA =O°C to

VIH

Input High Voltage

VIL
liN

Input Low Voltage

VOH

VOL
Po
CIN
COUT
Vee
Standby
100

Standby

+ 70°C unless otherwise noted.)

Parameter

Input Leakage Current
(VIN = 0 to 5.25V, Vee = Max)
Output High Voltage
(I LOAD = - 205/-lA, Vee = Min)
(I LOAD = -145/-lA, Vee = Min)
(I LOAD = -100/-lA,
Vee = Min)
Output Low Voltage
(ILOAD = 1.6mA, Vee = Min)
Power Dissipation
Capacitance #
(VIN = 0, TA = 25°C, f = 1.0MHz

Min.
Logic, EXtal
RESET
Logic, EXtal, RESET
Logic*

1.0

00-07
AO-A15, R/W, VMA, E
BA

Vss + 2.4
Vss + 2.4
Vss + 2.4

(Measured at TA = O°C)

00-07
Logic Inputs, EXtal
AO-A15, R/W, VMA

=5.0V ± 5%, Vss =0, TA =O°C to

Parameter

Max.

Units

Vee
Vee
Vss + 0.8
2.5

V
V
/-lA
V
V
V
V

Vss +O.4

0.600

1.2

V
W
pF

10
6.5
-

12.5
10
12

4.0

5.25

8.0

+ 70°C unless otherwise noted)

86802/86808
Symbol

Standby

Clock Timing (Vee

Vss + 2.0
Vss + 4.0
Vss - 0.3
-

Vee
100

Typ.

868A02/S68A08

Min.

Typ.

Max.

Min.

Typ.

Max.

868B02/868B08
Min.

Typ.

Max.

Unit
MHz

Frequency of Operation
I
IXtal
teye
t~

Input Clock -;- 4

0.1

1.0

0.1

1.5

Crystal Frequency
Cycle Time

1.0

4.0

1.0

6.0

1.0

6.7

.50

/-ls

Fall Time Measured between Vss + 0.4V
and Vss - 2.4V

*Except IRQ and NMI, which require 3KQ pull-up load resistors for wire-OR capability at optimum operation. Does not include Extal and Xtal,
#eapacitance are periodically sampled rather than 100% tested.
7.45

which are crystal inputs.

S6802/A/B/S6808/A/B
Read/Write Timing (Figures 1 through 5; Load Circuit of Figure 3.)
(Vee = 5.0V ± 5%, Vss = 0, TA = O°C to + 70°C unless otherwise noted)

86802/86808
8ymbol

Parameter

tAO

Address Delay
C= 90pF
C= 30pF
Peripheral Read Access Time
Data Setup Time Read
Data Hold Time Read
Address Hold Time
(Address, R/W, VMA)
Data Delay Time Write
Processor Controls
Data Hold Time Write
Processor Control Setup Time
Processor Control Rise
and Fall Time

tACC
tOSR
tOHR
tAH
toow
tOHW
tpcs
tPCr,tPCf

Min.

Typ.

Max.

100

270

575
100
10

L.~'

ADDRESS
FROM MPU

2.4V
VMA

225

20
140
100

20
110
100

100

_tAO_

-f+
t ACC

-:~

4.75V

_tAH

~
......,

2.0V~

C; "

DATA VALID

2:4V
O.4V

2.4V

~
I+---tAO-

_toow_j

2.4V~

DATA
FROM MPU

2.4V~

DATA VALID

~ DATA NOT VALID

7.46

2.2K

MM06150
OR EQU1V .

~~ ~~~~O~I~

~~
~

.~~1::

_ t AH

I+---tAO_

VMA

....-

2.4V}'"-

t OSR -

_ t AO -

ADDRESS
FROM MPU

......
......

TEST POINT

-tOHR'

Figure 2. Write Data in Memory or Peripherals

O.4V

Figure 3. Bus Timing Test Load

O.8V~

R!W

ns
ns

-,2.4V
.... O.4V

O.4V

ns
ns

160

~ DATA NOT VALID

ns
ns
ns

170

30
200

DATA FROM
MPU
OR PERIPHERALS

Unit

250
60
10

Max.

150
135

360
70
10

O.4V
2.4V

Typ.

_tAO_

RIW

Min.

180
165

Figure 1. Read Data from Memory or Peripherals
E

868802/868808

868A02/868A08
Typ. Max.

Min.

~
-tOHW

c = lJOpF FOR DO - 07, E
=

90pF FOR AD - A15, RIW ..AND VMA

JDpF FOR BA

R = 11.7KnFDRDD-D7,E
=

16.5Kn FOR AO - A15, R/W, AND VMA

24KnFDR BA

S6802/A/B/S6808/A/B
Figure 4. Typical Data Bus Output Delay
Versus Capacitive Loading

Figure 5. Typical ReadlWrite, VMA, and Address
Output Delay Versus Capacitive Loading

600
500

400

600
10H = -205JJA MAX@2.4V
I--IOL = 1.6mAMAX@O.4V

'OH = -145 JJA MAX @2.4V
= 1.6mA MAX @O.4V

500 I- '0 L

I-- VCC = 5.0V
I-- TA = 25°C

]

:;;
i= 300

(S6802, S68A02)

co 200

.....

I-- ~

.- I-""'

----

w
:;;
i=

300

200

1---

100

-~+-

,.......

100

I- VCC = 5.0V
400 r- TA = 25°C

-,.......

10-

1--- r--

100

200

300

400

500

ADDRESS, VMA (S68A02)

1 1 1 1 j
C INCLUDES STRAY CAPACITANCE
L

100

600

MEMORY READY

M5
25

M3
23

AU
22

Ml
20

RE'SEf 40
6

HALT

2
4

EXTAL 39
XTAL 38
BUS AVAILABLE

VALID MEMORY ADDRESS

REAONlRITE 34

Vee
Vss

= PIN 8. 35
= PIN 1. 21

500

600

A7
16

A6
15

AS
14

A4
13

A3
12

A2
11

Al
10

AD
9

•

ENABLE 37

INTERRUPT REQUEST

400

CL LOAD CAPACITANCE (pF)

NON·MASKABLE INTERRUPT

300

200

CL, LOAD CAPACITANCE (pF)

Figure 6. Expanded Block Diagram

R/W iS680d, S68A02)

_I::::::::==' ~

CL INCLUDES STRAY CAPACITANCE

ADDRESS, VMA I - (S6802 ONLY)

26
07

27
06

2B
05

29
04

30
03

31
02

32
01

7.47

33
DO

S6802/A/B/S6808/A/B
Functional Description
MPU Registers

those applications that require storage of information
in the stack when power is lost, the stack must be nonvolatile.

A general block diagram of the S6802 is shown in
Figure 6. As shown, the number and configuration of
the registers are the same as for the S6800. The 128x8
bit RAM has been added to the basic MPU. The first 32
bytes may be operated in a low power mode via a Vee
standby. These 32 bytes can be retained during powerup and power-down conditions via the RE signal.

Index Register-The index register is a two byte register
that is used to store data or a sixteen-bit memory address for the Indexed mode of memory addressing.
Accumulators- The MPU contains two 8-bit accumulators that are used to hold operands and results from
an arithmetic logic unit (ALU).

The MPU has three 16-bit registers and three 8-bit
registers available for use by the programmer(Figure 7).

Condition Code Register-The condition code register
indicates the results of an Arithmetic Logic Unit operation: Negative (N), Zero (Z), Overflow (V), Carry from bit 7
(C), and Half Carry from bit 3 (H). These bits of the Condition Code Register are used as testable conditions
for the conditional branch instructions. Bit 4 is the interrupt mask bit (I). The used bits of the Condition Code
Register (b6 and b7) are ones.

Program Counter-'-The program counter is a two byte
(16 bits) register that points to the current program
address.
Stack Pointer-The stack pointer is a two byte register
that contains the address of the next available location
in an external push-down/pop-up stack. This stack is
normally a random access ReadlWrite memory that
may have any location (address) that is convenient. In

Figure 8 shows the order of saving the microprocessor
status within the stack.

Figure 7. Programming Model of
the Microprocessing Unit

I
I

ACCA

I
I

m- 8

0
ACCB

m -- 6

m- 5

ACCB

\ INDEX REGISTER

m -4

ACCA

m -3

IXH

PROGRAM COUNTER

m- 2

m -2

IXL

m -1

PCH

0
SP

-SP

m -7

ACCUMULATOR B

m- 9

ACCUMULATOR A

Figure 8. Saving the Status of
the Microprocessor in the Stack

-SP

\ STACK POINTER

m+1

m +2

----~I

CONDITION CODES
REGISTER

m+ 1
m +2

"'I

I
I

CARRY (FROM BIT 7)

BEFORE

AFTER

OVERFLOW
ZERO

NEGATIVE

INTERRUPT

ACCB

HALF CARRY (FROM BIT 3)

ACCA

7.48

"STACK POINTER
"CONDITION CODES (ALSO CALLED THE PROCESSOR STATUS BYTE)
" ACCUMULATOR B
"ACCUMULATOR A

IXH

"INDEX REGISTER, HIGHER ORDER 8 BITS

IXL

"INDEX REGISTER, LOWER ORDER 8 BITS

PCH

"PROGRAM COUNTER, HIGHER ORDER 8 BITS

PCL

"PROGRAM COUNTER. LOWER ORDER 8 BITS

S6802/A/B/S6808/A/B
56802/56808 MPU Description

Proper operation of the MPU requires that certain
control and timing signals be provided to accomplish specific functions and that other signal lines
be monitored to determine the state of the processor. These control and timing signals for the 568021
56808 are identical to those of the 56800 except
that T5C, DBE, ~1, ~2 input, and two unused pins
have been eliminated, and the following signal and
timing lines have been added:
RAM Enable (RE)
Crystal Connections EXtal and Xtal
Memory Ready (MR)
Vcc Standby
Enable

Data Bus (00-07)- Eight pins are used for the data bus. It
is bi-directional, transferring data to and from the
memory and peripheral devices. It also has three-stateoutput buffers capable of driving one standard TTL load
and 130pF.
Halt-When this input is in the low state, all activity in
the machine will be halted. This input is level sensitive.
In the halt mode, the machine will stop at the end of an
instruction, Bus Available will be at a high state, Valid
Memory Address will be at a low state, and all other
three-state lines will be in the three-state mode. The address bus will display the address of the next instruction.
To insure single instruction operation, transition of the
Halt line must not occur during the last 200ns of E and
the Halt line must go high for one Clock cycle.

Output (E)

The following is a summary of the S6802/S6808 MPU
signals:
Address Bus (AG-A15)-Sixteen pins are used for the address bus. The outputs are capable of driving one st~n
dard TTL load and 130pF.

Read/Write (R/W)-This TTL compatible output signals
the peripherals and memory devices whether the M PU is
in a Read (high) or Write (low) state. The normal standby
state of this signal is Read (high).

Figure 9. Power-up and Reset Timing

20ms
MIN

- .-r----------i}-------i~~~---~l°~u.
Jl--t

RESET - - t - - " " 1
20ms

__- - - - - - - 1 j ' - - - - - - : - .

MIN -

t (SEE ~~~~~:LOW)

:~----

RESET - - - - . -

I
I
RE

PCf

O.sv

------_-

~_I_____________

2.0V

OPTION 2
SEE FIGURE 10 FOR
POWER DOWN CONDITION

";;;100ns
PCr

VMA-----~/

\\.------

NOTE: IF OPTION 1 IS CHOSEN, RESET AND RE PINS CAN BE TIED TOGETHER.

7.49

•

S6802/A/B/S6808/A/B
When the processor is halted, it will be in the logical
one state. This output is capable of driving one standard TTL load and 90pF.
Valid Memory Address (VMA)-This output indicates to
peripheral devices that there is a valid address on the
addres"S bus. In normal operation, this signal should be
utilized for enabling peripheral interfaces such as the
PIA and ACIA. This signal is not three-state. One standard TTL load and 90pF may be directly driven by this
active high signal.
Bus Available (BA)-The Bus Available signal will normally be in the low state; when activated, it will go to
the high state indicating that the microprocessor has
stopped and that the address bus is available. This will
occur if the Rait line is in the low state or the processor
is in the WAIT state as a result of the execution of a
WAIT instruction. At such time, all three-state output
drivers will go to their off state and other outputs to
their normally inactive level. The processor is removed
from the WAIT state by the occurrence of a maskable
(mask bit I = 0) or non-maskable interrupt. This output
is capable of driving one standard TTL load and 30pF.
Interrupt Request (IRQ)-This level sensitive input requests that an interrupt sequence be generated within
the machine. The processor will wait until it completes
the current instruction that is being executed before it
recognizes the request. At that time, if the interrupt
mask bit in the Condition Code Register is not set, the
machine will begin an interrupt sequence. The Index
Register, Program Counter, Accumulators, and Condition Code Register are stored away on the stack. Next
the MPU will respond to the interrupt request by setting
the interrupt mask bit high so that no further interrupts
may occur. At the end of the cycle, a 16-bit address will
be loaded that points to a vectoring address which is
located in memory locations FFF8 and FFF9. An address loaded at these locations causes the MPU to
branch to an interrupt routine in memory.

the registers will be lost. If a high level is detected on
the input, this will signal the MPU to begin the restart
sequence. This will start execution of a routine to initialize the processor from its reset condition. All the
higher order address lines will be forced high. For the
restart, the last two (FFFE, FFFF) locations in memory
will be used to load the program that is addressed by
the program counter. During the restart routine, the interrupt mask bit is set and must be reset before the
MPU can be interrupted by IRQ. Power-up and reset
timing and power-down sequences are shown in
Figures 9 and 10, respectively.
Figure 10. Power-Down Sequence

Vcc - - - - - - - - , ,

150n5
tpCf ~ 100n5 ...

The Halt line must be in the high state for interrupts to
be serviced. Interrupts will be latched internally while
Halt is low.

2.0V

When RE8ET is released it must go through the low to
high threshhold without bouncing, oscillating, or otherwise causing an erroneous RE8ET (less than 3 clock
cycles). This may cause improper MPU operation.

The IRQ has a high impedance pull-up device internal to
the chip; however a 3kQ external resistor to Vee should
be used for wire-OR and optimum control of interrupts.

Reset, when brought low, must be held low at least 3
clock cycles. This allows the 86802/86808 adequate
time to respond internally to reset. This function is
independent of the 20ms power up reset that is required.

Reset-This input is used to reset and start .the MPU
from a power down condition, resulting from a power
failure or an initial start-up of the processor. When this
line is low, the MPU is inactive and the information in

7.50

S6802/A/B/S6808/A/B
Non-Maskable Interrupt (NMI)-A low-going edge on this
input requests that a non-mask-interrupt sequence be
generated within the processor. As with the Interrupt
Request signal, the processor will complete the current
instruction that is being executed before it recognizes
the NMI signal. The interrupt mask bit in the Condition
Code Register has no effect on NMI.
The Index Register, Program Counter, Accumulators,
and Condition Code Register are stored away on the
stack. At the end of the cycle, a 16-bit address will be
loaded that points to a vectoring address which is
located in memory locations FFFC and FFFD. An address loaded at these locations caused the M PU to
branch to a non-maskable interrupt routine in memory.
NMI has a high impedance pull-up resistor internal to
the chip; however a 3kQ external resistor to Vee should
be used for wire-OR and optimum control of interrupts.
Inputs l'RQ and MMI are hardware interrupt lines that
are sampled when E is high and will start the interrupt
routine on a low E following the completion of an instruction:
Figure 12 is a flow chart describing the major decision
paths and interrupt vectors of the microprocessor.
Table 2 gives the memory map for interrupt vectors.
RAM Enable (RE)-A TTL-compatible RAM enable input
controls the on-Chip RAM of the 56802. When placed in
the high state, the on-Chip memory is enabled to respond to the MPU controls. In the low state, RAM is disabled. This pin may also be utilized to disable reading
and writing the on-Chip RAM during power-down situation. RAM enable must be low three clock cycles before
Vee goes below 4.75V during power-down to retain the
on board RAM contents during Vee standby.
The Data Bus will be in the output mode when the internal RAM is accessed, which prohibits external data
from entering the MPU. Note that the internal RAM is
fully decoded from $0000 to $007F and these locations
must be disabled when internal RAM is accessed.
Extal and Xtal- The 56802/56808 has an internal
oscillator that may be crystal controlled. These connections are for a parallel resonant fundamental crystal.

(AT cut) A divide-by-four circuit has been added to the
56802 so that a 4MHz crystal may be used in lieu of a
1MHz crystal for a more cost effective system. Pin 39 of
the 56802/56808 may be driven externally by a TTL input Signal if a separate clock is required. Pin 38 is to be
left open in this mode. If the external clock is used it
may not be halted for more than 4.5j.ts. The 56802/56808
is a dynamic part except for internal RAM, and requires
the external clock to retain information. Figure 11a
shows the crystal parameters. In applications where
other than a 4.0MHz crystal is used, Table 1 gives the
designer the crystal parameters to be specified. The
table contains the entire spectrum of usable crystals
for the 56802/56808. Crystal frequencies not shown
(that lie between 1.0MHz and 4.0MHz) may be interpolated from the table. Figure 11 b shows the crystal
connection.
Table 1_ Crystal Parameters
Y1 CRYSTAL
FREQUENCY

C1 &
C2

C
LOAD

4.0MHz
3.58MHz
3.0MHz
2.5MHz
2.0MHz
1.5MHz
1.0MHz

27pF
27pF
27pF
27pF
33pF
39pF
39pF

24pF
20pF
18pF
18pF
24pF
27pF
30pF

50
50
75
74
100
200
250

ohms
ohms
ohms
ohms
ohms
ohms
ohms

VECTOR

DESCRIPTION

LS
FFFF
FFFD
FFFB

SOFTWARE INTERRUPT

FFF8

FFF9

INTERRUPT REQUEST

RESTART
NON-MASKABLE INTERRUPT

Note: Memory Read (MR), Halt, RAM Enable (RE) and Non-Maskable
interrupt should always be tied to the correct high or low state if not used.

Figure 11 b. Crystal Connection
vt

P'N38~DTP'N39
Cl
Cl+C2=27pF

Tolerance Nate:
Crilh:al HmilllllOeps
require a beHer tolerance tban ±5%. Because 01 production deviations and the Temperature Coefficient 01
the 56802, tbe best "worst case design" tolerance is ±0.05'1o. (500 ppm) using a ±0.02'1o ClVsta!. K the 56802 is nat going to
be used aver its entire temperature range 01 DoC to 70°C, a much tighter overall tolerance can be achieved.

7.51

7.0pF
7.0pF
6.7pF
6.0pF
5.5pF
4.5pF
4.0pF

MS
FFFE
FFFC
FFFA

AT - Cut Parallel Resonance Crystal
Co· 7pF Max.
FRED = 4.0PIIHz@CL = 24pF
RS • 50 ohms Max.
Frequency Tolerance - ±5~ to ±O.02%
The best E output ''Worst Case Design"
tolerance is ± 0.05% (500ppM) using A ±0.02 crystal.

mav

Co
(MAX)

Table 2. Memory Map for Interrupt Vectors

Figure 11 a. Crystal Parameters

n~tJ-H

R1
(MAX)

AMI.---------.""'4.

A Subsidiary
of Gould Inc.

86805

MICROCOMPUTER

Features
o Hardware
• 8·Bit Architecture
• 64 Bytes RAM
• 1100 Bytes ROM
• 116 Bytes of Self Check ROM
• 28·Pin Package
• Memory Mapped I/O
• Internal 8·Bit Timer with 7·Bit Prescaler
• Vectored Interrupts- External, Timer, Software,
Reset
• 20 nUCMOS Compatible I/O Line
8 Lines LED Compatible
• On·Chip Clock Circ.uit
• Self·Check Capability
• Low Voltage Inhibit
• 5 Vdc Single Supply

Software
• Similar to 6800
• Byte Efficient Instruction Set
• Versatile Interrupt Handling
• True Bit Manipulation
• Bit Test and Branch Instruction
• Indexed Addressing for Tables
• Memory Usable as Registers/Flags
• 10 Addressing Modes
• Powerful Instruction Set
- All 6800 Arithmetic Instructions
- All 6800 Logical Instructions
- All 6800 Shift Instructions
- Single Instruction Memory Examine/Change
- Full Set of Conditional Branches
Pin Configuration

Block Diagram

TIMER

Vss

RmT

iiiT

Vet

XTl

EXTl

NUM

STACK PDINTER
S
SP

TIMER

Az
A,

ACCUMUlATOR
8

81
82
83
84
8S
86

A
CPU CONTRO~

PORT
A

110
LINES

AO
Al
A2
A3
A4
AS
A6

PORT
A
REG

DATA
DIR
REG

INOEX REGISTER
8
X
CONDITION CODE
REGISTER

PROGRAM
COUNTER HIGH
3
PCH

A~U

PROGRAM
COUNTER ~OW
8

PC~

SElF CHECK
ROM

7.52

PORT
8
I/O
LINES

PORT
C

Cl
~2

I/O

LINES

lis

86805
General Description

very similar to the 56800 family of microprocessors.
Although the 6805 is not strictly source nor object code
compatible, an experienced 6800 user can easily write
6805 code. Also a 6805 user will have no trouble moving
up to the 6801 or 6809 for more complex tasks.

The 56805 is an 8-bit single chip microcomputer. It is
the first member of the growing microcomputer family
that contains a CPU, on-chip clock, ROM, RAM, 1/0 and
timer. A basic feature of the 6805 is an instruction set
Absolute Maximum Ratings

Supply Voltage, Vee ............................................................................................................................... -0.3Vto + 7.0V
Input Voltage, VIN ................................................................................................................................... - 0.3V to + 7.0V
Operating Temperature Range, TA ............................................................................................................... 0° to + 70°C
Storage Temperature ~ange, Tstg ...................................................................................................... - 55°C to + 150°C
Thermal Resistance, BJA
Plastic .............................................................................................................................................................. 85°C/W
Ceramic ........................................................................................................................................................... 50°C/W
Cerdip .............................................................................................................................................................. 51°C/W
This device contains circuitry to protect the inputs against damage due to high static voltage or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper
operation it is recommended that VIN and VOUT be constrained to the range Vss (VIN or VOUT) + Vce

Electrical'Characteristics: Vee =

Symbol
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VH

Characteristic
Input High Voltage

Typ.

Max.

Unit

4.0

Vee

Vdc

INT

4.0

Vee

Vdc

Vee
Vee
15.0

Vdc

0.8

Vdc

1.5

Vdc

Input High

Timer Mode

Voltage Timer

Self-Check Mode

Vss + 2.0
Vss + 2.0
-

Input Low Voltage

RESET

Vss - 0.3

iNT

Vss -0.3

All Other

Vss - 0.3
-

INT Hysteresis

Power Dissipation
Input Capacitance

LVR

Low Voltage Recover
Low Voltage Inhibit

Switching Characteristics: Vee =

Symbol

Min.
RESET
All Other

CIN
CIN
LVI

+ 5.25 Vdc ± 0.5Vdc, Vss = GND, TA = 0° -70°C unless otherwise noted

9.0
-

100

Vss + 0.8
-

Vdc
Vdc

Vdc
mVee
mW

350

EXTL

All Other

10
3.5

4.75
-

Vdc

+ 5.25 V ± 0.5 Vdc, Vss = GND, TA = 0° - + 70°C unless otherwise noted

Characteristic

Min.

Typ.

Max.

Unit

fcl

Clock Frequency

0.4

4.0

MHz

teye

Cycle Time

1.0

tlWL

INT Pu Ise Width

teye + 250

10
-

JAs
ns

tRWL

RESET Pulse Width

tRHL

teye + 250
20

Delay Time Reset (External Cap. = 0.47JAF)

7.53

S6805
Port Electrical Characteristics: Vee
Symbol

= + 5.25 Vdc ± 0.5 Vdc, Vss =GND, TA =0° -

Characteristic

Min.

Typ.

+ 70°C unless otherwise noted

Max.

Unit

Condition

ILOAD = 1.6mAdc
ILOAD = 100/-lAdc

Port A
VOL
VOH

Output Low Voltage

0.4

Vdc

Output High Voltage

2.4

Vdc

VOH
V1H

Output High Voltage

3.5

Vdc

ILOAD = - 1O~dc

Input High Voltage

Vss + 2.0

V1L

Input Low Voltage

Vss - 0.3

ILOAD = - 300~dc (max)
ILOAD = 500/-lAdc (max)

VOL

Output Low Voltage

VOL

Output Low Voltage

VO H

Output High Voltage

IOH

Vee

Vdc

Vss + 0.8

Vdc

0.4

Vdc

1.0

Vdc

ILOAD = 3. 2mAdc
ILOAD = 10mAdc(sink)

2.4

Vdc

ILOAD = - 200/-lAdc

Darlington Current
Drive (Source)

-1.0

-10

mAdc

V1H
V1L

Input High Voltage

Vss + 2.0

Vdc

Vss - 0.3

Vee

Input Low Voltage

Vss + 0.8

Vdc

VOL
VOH

Output Low Voltage

Vdc

2.4

Vdc

Input High Voltage

Vss + 2.0

0.4

Output High Voltage

Vee

Vdc

Vss - 0.3

Vss + 0.8

Vdc

Port B

Vo = 1.5Vdc

Port C

V1H
V1L

Input Low Voltage

ILOAD = 1.6mAdc
ILOAD - - 1OO~dc

Off·State Input Current

Three-State Ports B & C

/-IAdc

Input Current
Timer at VIN - (0.4 to 2.41
Vdc)
Figure 1. TTL Equiv. Test Load
(Port B)

Figure 2. CMOS Equiv. Test Load
(Port A)

Figure 3. TTL Equiv. Test Load
(Ports A and C)

Vee

,VeeR

TEST
POINT

MMD6150

TEST POINT

0>---------.1

':"

TEST
POINT

30 F
•

':'

'IRL

'='

C =40pF, R=1ZK

C:]GpF.R=24K

ADJUST RlSOTHATI,=3.2mA

ADJUST Rl SO THAT II:Z 1.6mA

WITH VI " O.4V AND Vee" 5.25V

WITH VI "O.4V AND Vee = S.Z5V

7.54

MMD7000

OR EOUIV.

':'

86805
Pin Description
Pin

Symbol

Description

Vee and Vss

Power is supplied to the MCU using these two pins. Vee is 5.25V ± .5V, and Vss is the
ground connection.

INT

External Interrupt provides capability to apply an external interrupt to the MCU.

4 and 5

XTL and EXTL

Provide control input for the on-chip clock circuit. The use of crystal (at cut 4M Hz maximum), a resistor or a wire jumper is sufficient to drive the internal oscillator with varying
degrees of stability. (See Internal Oscillator Options for recommendations) An internal
divide by 4 prescaler scales the frequency down to the appropriate f2 clock rate (1 MHz
maximum).

1 and 3

NUM

This pin is not for user application and should be connected to ground.

TIMER

Allows an external input to be used to decrement the internal timer circuitry. See TIMER
for detailed information about the timer circuitry.

8-11
12-19
20-27

CO-C3
BO-B7
AO-A7

Input/Output lines (AO-A7, BO-B7, CO-C3). The 20 lines are arranged into two 8-bit ports
(A and B) and one 4-bit port (C). All lines are programmed as either inputs or outputs
under software control of the data direction registers. See Inputs/Outputs for additional
information.

RESET

This pin allows resetting of the MCU. A low voltage detect feature responds to a dip in
voltage by forcing a RESET condition to clear all Data Direction Registers, so that all I/O
pins are set as inputs.

Memory
The MCU memory is configured as shown in Figure 4.
During the processing of an interrupt, the contents of
the MCU registers are pushed onto the stack in the
order shown in Figure 5. Since the stack pointer decrements during pushes, the low order byte (PCl) of the
program counter is stacked first, then the high order

three bits (PCH) are stacked first, then the high order
three bits (PCH) are stacked. This ensures that the program counter is loaded correctly as the stack pointer
increments when it pulls data from the stack. A
subroutine call will cause only the program counter
(PCH, PCl) contents to be pushed onto the stack.
Figure 5. Interrupt Stacking Order

Figure 4. MCU Memory Configuration

000

110 PORTS

0
I·OUU

76543210
PORT A

TIMER RAM
127
128

255
256

959
960

(128 BYTES)
PAGE ZERO
ROM
(1288YTES)
NOT USED
ROM
(704 BYTES)

S07F
S080

:::\:
SlCO

MAIN ROM
(964 BYTES)
1923
1924

2047

$783
$784

INTERRUPT
VECTORS
ROM (8 BYTES)

SELF CHECK ROM
(116 BYTES)
2039
2040

S7F7
S7FB

63
64

SOOl

1 1 1 11 PORT C

S002

NOT USED

S003

PORT A DDR

SOO4"

PORT BOOR
~OT USED

7
0-4

SODS"

5
1

CONDITION
CODE REGISTER

PUll
0+1

0-3

ACCUMULATOR

0+2

0-2

INDEX REGISTER

0+3

I.ORTeooR S006"

NOT USED

S007

TIMER DATA REG

S008

TIMER CTRl REG

S009
SODA

NOT USED
(54 BYTES)

1~;\

SOOO

PORT B

RAM (64 8YTES)
STACK

0-1

1
PCl"

S03F
S040

PCW

0+4

0+5

PUSH

*Forsubroutine calls, only PCH and PClare stacked

S07F

"WRITE ONl Y REGISTERS

$7FF

7.55

.~
_

86805
six most significant bits of the stack pointer are permanently set to 000011. During an MCU reset or the reset
stack pointer (RSP) instruction, the stack pointer is set
to location $07F. Subroutines and interrupts may be
nested down to location $061 which allows the
programmer to use up to 15 levels of subroutine calls. A
16th subroutine call would save the return address correctly, but the stack pointer would not remain pointing
into the stack area and there would be no way to return
from any of the subroutines.

Figure 6. Programming Model

7
A

I ACCUMULATOR

7
X

IINOEX REGISTER

0
1PROGRAM COUNTER

10
54
10 1 0 10 1 0 11 11 1

Condition Code Register (CC)

1STACK POINTER

The condition code register is a 5-bit register in which
each bit is used to indicate or flag the results of the
instruction just executed. These bits can be individually tested by a program and specific action taken as a
result of their state. Each individual condition code
register bit is explained in the following paragraphs.

I I I I I I
H

CONOITION COOE REGISTER

~CARRY/BORROW
ZERO
NEGATIVE

HALF CARRY (H)-Used during arithmetic operations
(ADD and ADC) to indicate that a carry occurred between bits 3 and 4.

INTERRUPT MASK
HALF CARRY

INTERRUPT (1)- This bit is set to mask the timer and
external interrupt (INT). If an interrupt occurs while this
bit is set it is latched and will be processed as soon as
the interrupt bit is reset.

Registers
The S6805 MCU contains two 8·bit registers (A and X),
one 11-bit register (PC), two 5-bit registers (SP and CC)
that are visible to the programmer (see Figure 6).
Accumulator (A)

NEGATIVE (N)-USED TO INDICATE that the result of
the last arithmetic, logical or data manipulation was
negative (bit 7 in result equal to a logical one).

The A·register is an 8-bit general purpose accumulator
used for arithmetic calculations and data manipulation.

ZERO (Z)- Used to indicate that the result of the last
arithmetic, logical or data manipulation was zero.

Index Register (X)

CARRY/BORROW (C)- Used to indicate that a carry or
borrow out of the arithmetic logic until (ALU) occurred
during the last arithmetic operation. This bit is also
affected during bit test and branch instructions, shifts
and rotates.

This a-bit register is used for the indexed addressing
mode. It provides an 8-bit address that may be added to
an offset to create an effective address. The index
register can also be used for limited calculations and
data manipulations when using the read/modify/write
instructions. In code sequences not employing the index register it can be used as a temporary storage area.

Timer
The MCU timer circuitry is shown in Figure 7. The 8-bit
counter is loaded under program control and counts
down toward zero as soon as the clock input is applied.
When the timer reaches zero the timer interrupt request
bit (bit 7) in the timer control register is set. The MCU
responds to this interrupt by saving the present MCU
state in the stack, fetching the timer interrupt vector
from locations $7F8 and $7F9 and executing the interrupt routine. The timer interrupt can be masked by setting the timer interrupt mask bit (bit 6) in the timer control register. The interupt bit (bit 1) in the condition code
register will also prevent a timer interrupt from being
processed.

Program Counter (PC)

This 11-bit register contains the address of the next
instruction to be executed.
Stack Pointer (SP)

The stack pointer is an 11-bit register that contains the
address of the next free location on the stack. Initially,
the stack pointer is set to location $07F and is decremented as data is being pushed onto the stack and
incremented as data is being pulled from the stack. The
7.56

86805
• Port B is also multiplexed. When ~2 is high, Port B is
the output data bus, and when ~2 is low Port B is the address lines. The output data bus can be used to monitor
the internal ROM or RAM.

The clock input to the timer can be from an external
source applied to the TIMER input pin or it can be the
internal ~2 signal. Note that when ~2 signal is used as
the source it can be gated by an input applied to the
TIMER input pin allowing the user to easily perform
pulse-width measurements. The source of the clock input is one of the options that has to be specified before
manufacture of the MCU. A prescaler option can be applied to the clock input that extends the timing interval
up to a maximum of 128 counts before being applied to
the counter. This prescaling option must also be specified before manufacturing begins. The timer continues
to count past zero and its present count can be monitored at any time by monitoring the timer data register.
This allows a program to determine the length of time
since a timer interrupt has occurred and not disturb the
counting process.
At power up or reset the prescaler and counter are initialized with all logical ones; the timer interrupt request
bit (bit 7) is cleared and the timer request mask bit (bit 6)
is set.

• Port C becomes the last three address lines and a
read/write control line.
The MCU incorporates a self test program within a 116
byte non-user accessable test program and some control logic on-chip. These 116 bytes of ROM test every
addressing mode and nearly every CPU instruction
(95% of the total microprocessor capability) while only
adding 1% to the total overall die size.
To perform the self test, the MCU output lines of Port A
and B must be externally interconnected (Figure 7) and
LED's are connected to Port C to provide both a pass/
fail indication (3Hz square wave).
The flowchart for the self test program (Figure 8) runs
four tests:
• 1/0 TEST: Tests for 110 lines that are stuck in high,
low, shorted state, or are missing a connection. The 110
lines are all externally wired together so that the program can look for problems by testing for the correct
operation of the lines as inputs and outputs and for
shorts between two adjacent lines.

Self Check Mode:
The MCU includes a non-user mode pin that replaces
the normal operating mode with one in which the internal data and address buses are available at the I/O
ports. The ports are configured as follows in the test
mode (some multiplexing of the address and data lines
is necessary):
• The internal ROM and RAM are disabled and Port A
becomes the input data bus on the ~2 of the clock and
can be used to supply instructions of data to the MCU.

• ROM ERROR: (Checksum wrong). The checksum
value of the user program must be masked into the self
check ROM when the microcomputer is built. The self
check program then tests the user ROM by computing
the checksum value, which should be equal to the
masked checksum if all the bits in the ROM are prop-

Figure 7. Timer Block Diagram

r----.,
I

TIME

I----=-'0U4T

I
L
___ JI

.J-----I-~ ~~~::RUPT REO.
6

TIMER
INTERRUPT MASK

MANUFACTURING
MASK OPTIONS

WRITE

7.57

READ

TIMER
CONTijOl REGISTER

I
::
--

86805
erly masked. Address and data lines that are stuck high,
low or to each other are also detected by this test. An
inoperable ROM will (in most cases) prevent the running of the self check program.

Figure 9. Flowchart of Self Test Routine

• RAM Bits Non-Functional: The RAM is tested by the
use of a walking bit pattern that is written into memory
and then verified. Every in RAM is set to one and then to
zero by using 9 different patterns as shown in Figure 9.
Figure 8. Interconnected Ports for Self Check Mode.
Port C Gives GoiNo Go and Diagnostic Information.
HALT

PORT C=XXOl

2
28
0.47~F

*
+9V

INT
RESET

XTAl

EXTAl

TIMER

NUM

Vee

330n

15
13
12

330n

82
Bl

330n

Vcc= PIN 3
Vss= PIN 1

HALT

PORT C=XXOl

14
HALT

PORT C=XX10

Self Test Routines
Program performs four main tests in the major loops
and provides an output signal to indicate that the part is
functional.
Interrupt Logic Failure: Using an 1/0 line the interrupt pin
is toggled to create an interrupt. The main program runs
long enough to allow the timer to underflow and causes
the timer interrupt to be enabled.
If all of these tests are successful the program, then
loops back to the beginning and starts testing again.
The self check program initially tries to get the MCU out
of the reset state to indicate that the processor is at
least working. The non-functional parts are thus immediately eliminated, and if the part fails at this first stage
the program provides a means of determining the faulty
section.

HALT

PORT C=XX"

To place the MCU in the self check mode the voltage on
the timer input (Figure 7) is raised to 8 volts which
causes several operations to take place:

HALT

PORTC=XXOO

7.58

86805
• The clocking source for the timer is shunted to the
MCU internal clock to insure that the timer will run
an underflow during the course of the program, no
matter which clocking rate is masked.
• The address of the interrupt vectors (including the
reset vector) are mapped into the self check ROM
area. This allows the self check to test the interrupt
structure.
The self check program is started by the reset signal
instead of the normal program because the vectors
(including the reset vector) have been overlaid. The
self check program runs in an endless loop testing
and retesting the processor as long as there are no
errors. Signals on the 110 lines indicate that the test
has passed, and if any test fails, the program stops
by executing a branch to self instruction. The output
lines then cease to toggle and two of the 110 lines
will indicate the cause of failure.
RAM Test Pattern
"Walking bit" patterns test sequence sets and
resets every bit in memory. (See Figure 10.)

Figure 10. RAM Test Pattern
PATTERN #1

0 0
1 0 0
0 1 0
o0 1

0
0
0
0
0 1

0
0
0
0
0

PATTERN #2

o
o
o
o
o

0
0
0
0
0

o
o
o
o
o

0
0
0
0
0

0 0 0 0 0
0 0 0 0 0
1 0 0 o 0 0

o
o
o

1
0

1 0
o1
o0
o0
o0

0
0
1
0

0
0
0
1
0 0

•
•

0 0 0 0 0 0 1 0
0 0 o 0 0 0 1
0 0 0 o 0 o 0

o
o

0 1 0
0 0 1
0 0 0
0 o 0
0 o 0

o
o

0
0
1 0
o 1
o0

0
0
0
0
1

0 0 o 1
0 0 0 0
0 0 0 0
0 0 o 0
0 0 o 0

0
0
0
0
0

Low Voltage Inhibit

As soon as the voltage at pin 3 (Vee) falls to 4.5 volts,
all 110 lines are put into a high impedance state. This
prevents erroneous data from being given to an
external device. When Vee climbs back up to 4.6
volts a vectored reset is performed.

•

•
•
•
•
o
o
o

PATTERN #9

PATTERN #8
0 0 0
0 0 0
0 0 0
1 0 0 0 0
o1 0 0 0

0
0
0
0

•
•
•
•

•
•

o -0
o0
o 0

0
0
0
0
1

•
•
•

0 0 0 1 0 o 0
0 0 0 0 1 o 0
0 0 0 0 0 1 0

o
o
o

Table 1. Cause of Chip Failure as Shown in Bits 0 and 1 of
110 Port C
BIT 0
REASON FOR FAILURE
BIT 1

0 0 0 0 1 o 0
0 0 0 0 0 1 0
0 0 0 0 0 o 1

o
o
1

Figure 11. Power Up and Reset Timing

5V _ _ _ _ _J
vee

OV
RESET
PIN

INTERNAL
RESET

_____

---------1
7.59

o
1
o
1

INTERRUPTS
I/O PORTS A OR B

RAM
ROM

•

S6805
Resets
Figure 12. Power Up Reset Delay Circuit

22K

The MCU can be reset three ways; by the external reset
input (RESET), by the internal low voltage detect circuit
already mentioned, and during the power up time. (See
Figure 11.)
Upon power up, a minimum of 20 milliseconds is needed before allowing the reset input to go high. This time
allows the internal oscillator to stabilize. Connecting a
capacitor to the RESET input as shown in Figure 12 will
provide sufficient delay.

Internal Oscillator Options
The internal oscillator circuit has been designed to require a minimum of external components. The use of a
crystal (AT cut; 4MHz max) or a resistor is sufficient to
drive the internal oscillator with varying degrees of stability. A manufacturing mask option is available to provide better matching between the external components
and the internal oscillator.

~ 0.41i-IF
PART OF
S6805
MCU

NOTE: 0.47f.JF =
APPROXIMATELY
50 MILLISECOND DELAY

The different connection methods are shown in Figure
13. Crystal specifications are given in Figure 14. A
resistor selection graph is given in Figure 15.
Figure 13. Internal Oscillator Options
RESISTOR OPTIONS

CRYSTAL OPTIONS

EXTAL

~~HxZ 0
S6805
MCU

XTAL
27pF
(Recommended)

XTAL

S6805
MCU

APPROXIMATEL Y 25% ACCURACY
TYPICAL tCYC = 1.25fJs
EXTERNAL JUMPER

CRYSTAL

+SV
EXTAL

EXTAL
":'

EXTERNAL
CLOCK
INPUT

XTAL

S680S
MCU

NO
CONNECTION

XTAL

S6805
MCU

APPROXIMATEL Y 10% ACCURACY
EXTERNAL RESISTOR

EXTERNAL CLOCK

7.60

S6805
A sinusodial signal (1 kHz maximum) can be used to
generate an external interrupt (INT) as shown in Figure
16.

Figure 14. Crystal Parameters

A flowchart of the interrupt processing sequence is
given in Figure 17.
Table 2. Interrupt Priorities
AT-CUT PARAllEL RESONANCE CRYSTAl
Co =7pF MAX
FREO=4.0MHz@C l =24pF
Rs=50 OHMS MAX

Interrupt

Priority

RESET
SWI

1
2
3
4

TNT
TIMER

Vector Address
$7FE AND
$7FC AND
$7FA AND
$7F8AND

$7FF
$7FD
$7FB
$7F9

Input/Output
Figure 15. Typical Resistor Selection Graph

There are 20 input/output pins. All pins are programmable as either inputs or outputs under software control of the data direction registers. When programmed
as outputs, all 110 pins read latched output data
regardless of the logic level at the output pin due to output loading (see Figure 18). When port B is programmed
for outputs, it is capable of sinking 10 milliamperes on
each pin (one volt maximum). All input/output lines are
TTL compatible as both inputs and outputs. Port A lines
are CMOS compatible as outputs while Port Band C
lines are CMOS compatible as inputs. Figure 19 provides some examples of port connections.

5.0

,
4.0

3.0

S
fE

VCC=5V
T.=25'C

2. 0

1.0

~ ,.......

J"... I'--10

Figure 16. Typical Sinusodial Interrupt Circuits

RESISTANCE (K OHMS)

Interrupts

2 to

4VAC-1

PEAK· TO·PEAK
(1kHz MAX)

The MCU can be interrupted three different ways;
through the external interrupt (INT) input pin, the inter·
nal timer interrupt request, and a software interrupt
instruction (SWI). When any interrupt occurs, process·
ing is suspended, the present MCU state is pushed onto the stack, the interrupt bit (I) in the condition code
register is set, the address of the interrupt routine is obtained from the appropriate interrupt vector address,
and the interrupt routine is executed. The interrupt ser·
vice routines normally end with a return from interrupt
(RTI) instruction which allows the MCU to resume pro·
cessing of the program prior to the interrupt. Table 2
provides a listing of the interrupts, their priority, and the
vector address that contain the starting address of the
appropriate interrupt routine.

AC tNPUT

S6805
MCU

IV&&"",-___-

(1k"' MAXI-V;

7.61

tNT

1fiF

___---1

tNT

S6805
MCU

•

86805
Figure 17. Interrupt Processing Flowchart

1 .... 1
7F .... SP
O.... DDR's
CLR INT LOGIC
FF .... TIMER
7F .... PRESCALER
7F .... TCR

Figure 18. Typical Port 1/0 Circuitry

OATA
DIRECTION
REGISTER

OUTPUT
DATA

BIT

OUTPUT
STATE

INPUT
TO
MCU

0
1
3-STATE

7.62

S6805

Figure 19. Typical Port Connections

••
•
••
•
••
•
A7

PORT A

PORT 8

••
•
•••

~ IC=HFE·1a
2N6386
(TYPICAL)

•
•••

'::"

PORT 8 PROGRAMMED AS OUTPUT(S) DRIVING
DARLINGTON BASE DIRECTLY
(b)

PORT A PROGRAMMEO AS OUTPUT(S) DRIVING CMOS ANO
TTL LOAD DIRECTLY
(a)

+V
80

•
•
••

PORT 8

••

·••

PORT C
10mA MAX

••
••
•

MC14049/14069
CMOS INVERTER
(TYPICAL)

•
•••

•

--C3

PORT C PROGRAMMED AS DUTPUT(S) DRIVING
CMOS USING EXTERNAL PULL·UP RESISTORS
(D)

PORT 8 PROGRAMMED AS OUTPUT(S) ORIVING LED(s) DlRECTl Y
(c)

Addressing Modes
The MCU has ten addressing modes available for use
by the programmer. They are explained and illustrated
briefly in the following paragraphs.

Bit Manipulation
The MCU has the ability to set or clear any single ran·
dom access memory or input/output bit (except the
data direction registers) with a single instruction
(BSET, BClR). Any bit in the page zero read only memo
ory can be tested, using the BRSET and BRClR instruc·
tions, and the program branches as a result of its state.
This capability to work with any bit in RAM, ROM or I/O
allows the user to have individual flags in RAM or to
handle single I/O bits as control lines. The example in
Figure 20 illustrates the usefulness of the bit manipu·
lation and test instructions. Assume that bit 0 of port A
is connected to a zero crossing detector circuit and that
bit 1 of port A is connected to the trigger of a TRIAC
which powers the controlled hardware.

Figure 20. Bit Manipulation Example

•
•
•
•
•
SELF 1 BRCLR 0, PORT A, SELF 1
BSET 1, PORTA
BCLR 1, PORT A

This program, which uses only seven ROM locations,
provides turn-on of the TRIAC within 14 microseconds
of the zero crossing. The timer could also be incorporated to provide turn-on at some later time which
would permit pulse-width modulation of the controlled
power.

•
•
•
•
•
7.63

86805
the opcode to the contents of the index register. In this
mode, 511 low memory locations are accessable.
These instructions occupy two bytes.
Indexed (16-Bit Offset)- Refer to Figure 27. This addressing mode calculates the EA by adding the contents of the two bytes following the opcode to the index
register. Thus, the entire memory space may be accessed. Instructions which use this addressing mode are
three bytes long.
Bit Set/Clear- Refer to Figure 28. This mode of addressing applies to instructions which can set or clear any
bit on page zero. The lower three bits in the opcode
specify the bit to be set or cleared while the byte following the opcode specifies the address in page zero
Bit Test and Branch- Refer to Figure 29. This mode of
addressing applies to instructions which can test any
bit in the first 256 locations ($OO-$FF) and branch to any
location relative to the PC. The byte to be tested is addressed by the byte following the opcode. The individual bit within that byte to be tested is addressed by the
lower three bits of the opcode. The third byte is the
relative address to be added to the program counter if
the branch condition is met. These instructions are
three bytes long. The value of the bit tested is written to
the carry bit in the condition code register.
Inherent- Refer to Figure 30. The inherent mode of
addressing has no EA. All the information necessary to
execute an instruction is contained in the opcode.
Direct operations on the accumulator and the index
register are included in this mode of addressing. In addition, control instructions such as SWI. RTI belong to
this group. All inherent addressing instructions are one
byte long.

Immediate-Refer to Figure 21. The immediate addressing mode accesses constants which do not change
during program execution. Such instructions are two
bytes long. The effective address (EA) is the PC and the
operand is fetched from the byte following the opcode.
Direct- Refer to Figure 22 in direct addressing, the
address of the operand is contained in the second byte
of the instruction. Direct addressing allows the user to
directly address the lowest 256 bytes in memory. All
RAM space, 1/0 registers and 128 bytes of ROM are
located in page zero to take advantage of this efficient
memory addressing mode.
Extended- Refer to Figure 23. Extended addressing is
used to reference any location in memory space. The
EA is the contents of the two bytes following the opcode. Extended addressing instructions are three bytes
long.
Relative- Refer to Figure 24. The relative addressing
mode applies only to the branch instructions. In this
mode the contents of the byte following the opcode is
added to the program counter when the branch is
taken. EA (PC) + 2 + ReI. Rei is the contents of the
location following the instruction opcode with bit 7 being the sign bit. If the branch is not tken Rei = 0, when a
branch takes place, the program goes to somewhere
within the range of + 129 bytes to - 127 of the present
instruction. These instructions are two bytes long.
Indexed (No Offset)- Refer to Figure 25. This mode of
addressing accesses the lowest 256 bytes of memory.
These instructions are one byte long and their EA is the
contents of the index register.
Indexed (a-Bit Offset)- Refer to Figure 26. The EA is
calculated by adding the contents of the byte following

Figure 21. Immediate Addressing Example
lEA

~
:

I
..!.

INDEX REG
STACK POINT

PRUG LUA N$FB USBE ~jA~6=}-_ _ _ _
USSF ~
FB

----.J

PRUG COUNT
USCO
CC

I
I
I

I
:

7.64

86805

Figure 22. Direct Addressing Example

CAT FCB

MEMORY

~::J~=t-----+---"""";!!J!ruL------i~~~2~0~J

004B

INDEX REG

PROG

LOA

CAT

t-=::jt=:::::j-----.l
f-

0520
052E

STACK POINT
PROG COUNT
052F
CC

Figure 23. Extended Addressing Example

PROGLOACAT0409~ J
040A
040B

06
E5

:
CAT FCB 64 06E5

]

MEMORY

BEO PROG2

:::;

I---!:..!...---i

~
I

STACK POINT
PROG COUNT
040C
CC

~~Q:::::=i----------..J

Figure 24. Relative Addressing Example

PROG

40
INDEX REG

7.65

86805
Figure 25. Indexed (No Offset) Addressing Example
MEMORY

TABL FCC/LU

00B81=~~=r---2!~l----t------l~=~4£C= J
INDEX REG

... "'.'-..

STACK POINT

PROG COUNT
05F5
CC

§
I

I
I

Figure 26. Indexed (8-Bit Offset) Addressing Example
MEMORY

TA8L FCB
FC8
FCB
FCB

N8F
NB6
ND8
NCF

0089
008A
D08B
008C

BF
86
08
CF

CF
INDEX REG
03
STACK POINT

PROG LOA TABL,X 075B
075C

PROG COUNT
075E
CC

§
I

I
I

Figure 27. Indexed (16-Bit Offset) Addressing Example ,..--------,
I
I

~
I

PRDG LDA TABL.X 0692
0693
0694

DB
INDEX REG
02
STACK POINT

~'
06
'
07
7E

]

TABL FCB N8F 077E t-~:---I

t:~~=r---------.l

FCB #86 077F
FCB #OB 0780,...
FCB #CF 0781 !-""";;:"'--I

7.66

PROG COUNT
0695
CC

86805
Figure 28. Bit Set/Clear Addressing Example

PORT BEaU 1 0001 I---=.:....-_~
0000
INDEX REG
STACK POINT
PROG BCLR 6, PORT B 058F
0590

r::2t==~---_---.J

I-

PROG COUNT
0591
CC

~
I

I
I,

Figure 29. Bit Test and Branch Addressing Example,.--_ _ _ _ _-,
MEMORY

PORT C Eau 2
INDEX REG
STACK POINT
PROG BCLR 2 PORT C PROG2 0574 r::~t==[]==-..J
0575105761---'-=----1

PROG COUNT
0594
CC

~
I
I
I

I
,
,

Figure 30. Inherent Addressing Example
MEMORY
,

PROG TAX

~
.... ~
CC

~
I

7.67

•

S6805
Instruction Set
instructions since it does not perform the write. Refer
to Table 4.

The MCU has a set of 59 basic instructions. They can be
divided into five different types: register/memory, read/
modify/write, branch, bit manipulation, and control. The
following paragraphs briefly explain each type. All the
instructions within a given type are presented in individual tables.

Branch Instructions-The branch instructions cause a
branch from the program when a certain condition is
met. Refer to Table 5.
Bit Manipulation Instructions-These instructions are
used on any bit in the first 256 bytes of the memory.
One group either sets or clears. The other group performs the bit test and branch operations. Refer to Table
6.

Register/Memory Instructions- Most of these instructions use two operands. One operand is either the accumulator or the index register. The other operand is obtained from memory using one of the addressing
modes. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand.
Refer to Table 3.

Control Instructions-The control instructions control
the MCU operations during program execution. Refer to
Table 7.

Read/Modify/Write Instructions- These instructions
read a memory location or a register, modify or test its
contents, and write the modified value back to memory
or to the register. The test for negative or zero (TST)
instruction is an exception to the read/modify/write

Alphabetical Listing-The complete instruction set is
given in alphabetical order in Table 8.
Opcode Map- Table 9 is an opcode map for the instructions used on the MCU.

Table 3. Register/Memory Instructions
ADDRESSING MODES
IMMEDIATE
OP

Function

DIRECT

* *

MnemoniC

Code

LOAD A FROM MEMORY

LDA

LOAD X FROM MEMORY

LOX

STORE A IN MEMORY

STA

* *

Byte. c.yctes Code

INDEXED
(No Offset)

EXTENDED

INDEXED
(8-Bit Offset)

INDEXED
16-Bit Offset)

* *

Byte. CYCles Code

Byte. Cycle. Code

Bytes Cycle. Code

* *

Bytes Cycle.

STORE X IN MEMORY

STX

ADD MEMORY TO A

ADD

ADD MEMORY AND CARRY TO A

ADC

SUBTRACT MEMORY

SUB

2
'0

SUBTRACT MEMORY FROM A WITH BORROW

SBC

AND MEMORY TO A

AND

OR MEMORY WITH A

ORA

-3

EXCLUSIVE OR MEMORY WITH A

EOR

ARITHMETIC COMPARE A WITH MEMORY

CMP

ARITHMETIC COMPARE X WITH MEMORY

CPX

BIT TEST MEMORY WITH A (Logical Compare)

BIT

JUMP UNCONDITIONAL

JMP

JUMP TO SUBROUTINE

JSR

7.68

56805
Table 4. Read/Modify/Write Instructions
ADDRESSING MODES
INHERENT
(A)
OP
Function

INHERENT
(X)
/I

INDEXED

INDEXED
(No Offset)

DIRECT
/I

(B· Bit Offset)

Mnemonic

COde

INCREMENT

INC

DECREMENT

DEC

CLEAR

CLR

COMPLEMENT

COM

NEGATE (2'5 COMPLEMENT)

NEG

ROTATE LEFT THRU CARRY

ROL

ROTATE RIGHT THRU CARRY

ROR

LOGICAL SHIFT LEFT

LSL

LOGICAL SHIFT RIGHT

LSR

ARITHMETIC SHIFT RIGHT

ASR

TEST FOR NEGATIVE OR ZERO

TST

Bytes Cycle. COde

Table 5. Branch Instructions
RELATIVE
ADDRESSING MODE
OP

Function

Byles Cycles

Mnemonic

COde

BRANCH ALWAYS

BRA

BRANCH NEVER

BRN

BRANCH IFF HIGHER

BHI

BRANCH IFF LOWER OR SAME

BLS

BRANCH IFF CARRY CLEAR
(BRANCH IFF HIGHER OR SAME)
BRANCH IFF CARRY SET
(BRANCH IFF LOWER)

BCC

(BHS)

BCS

(BLO)

BRANCH IFF NOT EQUAL

BNE

BRANCH IFF EQUAL

BEQ

BRANCH IFF HALF CARRY CLEAR

BHCC

BRANCH IFF HALF CARRY SET

BHCS

BRANCH IFF PLUS

BPL

BRANCH IFF MINUS

BMI

BRANCH IFF INTERRUPT MASK BIT IS CLEAR

BMC

BRANCH IFF INTERRUPT MASK BIT IS SET

BMS

BRANCH IFF INTERRUPT LINE IS LOW

BIL

BRANCH IFF INTERRUPT LINE IS HIGH

BIH

BRANCH TO SUBROUTINE

BSR

7.69

Bytes Cycles COde

Bytes Cycles

•

AMI.---------.""4.
r

A Subsidiary
of Gould Inc.

S6809/S68A09/S68B09

Preliminary Data Sheet

8-BIT
MICROPROCESSING UNIT

Features
o Interfaces With All 86800 Peripherals

Upward Compatible Instruction 8et and
Addressing Modes

Upward 80urce Compatible Instruction 8et and
Addressing Modes

Two 8-Bit Accumulators Can Be Concatenated
Into One 16-Bit Accumulator

On·Chip Crystal Oscillator (4 times XTAL)

General Description
The 86809 is an advanced processor within the 86800
family offering greater throughput, improved byte effi·
ciency, and increased adaptability to various software
disciplines. These include position independence,
reentrancy, recursion, block structuring, and high level
language generation.
Because the 86809 generates position·independent
code, software can be written in modular form for easy
user expansion as system requirements increase. The
86809 is hardware compatible with all 86800 peri·
pherals, and any assembly language code prepared for
the 86800 can be passed through the 86809 assembler
to produce code which will run on the 86809.

Block Diagram

Pin Configuration
+-- vee
Vss1

+--

VSS

HALT
XTAL
EXTAL
RESET

INSTRUCTION
DECODE
(IR)

8S
BA
Vcc 1
AD
A1

RESET
NMI

FIRO

IRO
A5

OMA/BREO
R/W

AS
A7

HALT
BA

BS
XTAL

A1D

EXTAL
MRDY

A12

E
0

7.70

A11
A13

~MII.---------......

A Subsidiary
of Gould Inc.

S6809E/S68A09E/S68B09E

8-BIT
MICROPROCESSING UNIT

Features
o Interfaces With All 56800 Peripherals

General Description
The S6809E is an advanced processor within the S6800
family offering greater throughput, improved byte efficiency, and increased adaptability to various software
disciplines. These include position independence, reentrancy, recursion, block structuring, and high level
language generation.

D Upward Compatible Instruction Set and Addressing
Modes

Upward Source Compatible Instruction Set and
Addressing Modes

D Two 8-Bit Accumulators Can Be Concatenated Into
One 16-Bit Accumulator
D External Clock Inputs, E and
Synchronization

Because the S6809E supports position-independent
code, software can be written in modular form for easy
user expansion as system requirements increase. The
S6809E is hardware compatible with all S6800 peripherals, and any assembly language code prepared for
the S6800 can be passed through the S6809 assembler
to produce code which will run on the S6809E.

a, Allow System

Block Diagram

Pin Configuration
TSC

+-- Vee
+-- Vss

INSTRUCTION
DECODE
(IR)

Vss

HALT

NMl

TSC

1RQ

LlC

FIRO

RESET

AVMA

BA
Vcc 1
Ao

BUSY

R/W

RESET
NMI

FIRO

A10

A15

All

A12

A13

AVMA
HALT
BA
LlC
BS

7.71

•

S6809E1S68A09E1S68B09E
The S6809E gives the user 8- and 16-bit word capability
with several hardware enhancements in the design
such as the Fast Interrupt Request (FIRQ), Memory
Ready (MRDY), and Quadrature (QOUT) and System
Clock Outputs (EOUT)' With the Fast Interrupt Request
(FIRQ) the S6809E places only the Program Counter and
Condition Code Register on the stack prior to accessing the FIRQ vector location. The Memory Ready
(MRDY) input allows extension of the data access time
for use with slow memories. The System Clock (EouT)
operates at the basic processor frequency and can be
as the synchronization signal for the entire system. The
Quadrature Output (QOUT) provides additional system
timing by signifying that address and data are stable.

S6809E Hardware Features

o
o

Fast Interrupt Request Input: Stacks
Only Program Counter and Condition Code
Interrupt Acknowledge Output Allows
Vectoring by Devices
Three Vectored Priority Interrupt Levels
SYNC Acknowledge Output Allows for
Synchronization to External Event
NMI Blocked After RESET Until After
First Load of Stack Pointer
Early Address Valid Allows Use With
Slow Memories
Last Instruction Cycle Output (L1C) for
Signalling Opcode Fetch
Busy Output Eases Multiprocessor Design

The External Clock mode of the S6809E is particularly
useful when synchronizing the processor to an externally generated signal. The Three-State Control input
(TSC) places the Address and RIW line in the high impedance state for DMA or Memory Refresh. The last
Instruction Cycle (L1C) is activated during the last cycle
of any instruction. This signifies that the next instruction cycle is the opcode fetch. The Processor Busy
signal (BUSY) facilitates multiprocessor applications
by allowing the designer to insure that flags being
modified by one processor are not accessed by another
simultaneously.

Instruction Set

o
o
o
o

o
o

Extended Range Branches
Load Effective Address
16-Bit Arithmetic
8x 8 Unsigned Multiply
(AccumulatorA * B)
SYNC Instruction-Provides Software
Sync With an External Hardware Process
Push and Pull on 2 Stacks
Push/Pull Any or All Registers
Index Registers May be Used as
a Stack Pointer
Transfer/Exchange all Registers

The S6809E features a family of addressing capabilities
which can use any of the four index registers and stack
pOinters as a pointer to the operand (or the operand address). This pointer can have a fixed or variable signed
offset that can be automatically incremented or decremented. The eight-bit direct page register permits a
user to determine which page of memory is accessed
by the instructions employing "page zero" addressing.
This quick access to any page is especially useful in
multitasking applications.

Addressing Modes

o
o
o
o
o

All S6800 Modes Plus PC Relative
Extended Indirect, Indexed Indirect, and
PC Relative Indirect
Direct Addressing Available Anywhere
in Memory Map
PC Relative Addressing: Byte Relative
(± 32,768 Bytes From PC)
Complete Indexed Addressing Including
Automatic Increment and Decrement,
Register Offsets, and Four Indexable
Register (X, Y, U and S)
Expanded Index Addressing
o 0,5,8, 16-Bit Constant Offset
o 8, 16-Bit Accumulator Offsets

The S6809E has three vectored priority-interrupt levels,
each of which automatically disables the lower priority
interrupt while leaving the higher priority interrupt
enabled.
The S6809E gives the system designer greater flexibility (through modular relocatable code) to enable the
user to reduce system software costs while at the same
time increaSing software reliability and efficiency.

7.72

. S6809E/S68A09E/S68B09E
Read-Modify-Write operation (ASL @6300).

E and Q Clock Inputs. The E and Q inputs are the clock
signals required by the S6809E. The E signal is similar
to the ~ signal of the S6800. Data is latched on the trail·
ing edge of the E signal. The Q is a Quadrature clock,
and is used to signal the validity of the addresses on
the address bus. The Q input is TTL compatible, the E
input however, directly drives the internal MaS cir·
cuitry. As a result, the E signal's levels must be higher
than TTL levels, to minimize internal skew. The required
signals are shown in Figures 1 and 2. Figure 11 shows
the circuitry required to generate the proper signals. A
74LS73 is required, as the other 7473 series are level
triggered rather than edge-triggered, and will not generate the proper waveforms.

AVMA. The AVMA output is an advanced Valid Memory
Address signal. This output goes HIGH one cycle
before the M PU performs a memory access. The advanced nature of this signal allows bus arbitration logic an
advanced warning of potential bus conflict.
LlC. The LlC output is the Last Instruction Cycle signal.
This signal's HIGH to LOW transition signals that the
current MPU cycle is an opcode fetch. The LlC signal
will be held HIGH when the MPU is Halted at the end of
an instruction (Le., not in CWAI or RESET), when the
MPU is in the SYNC state or while it is stacking during
interrupts.
TSC. The TSC input is a Tri-State-Control for the
S6809E's Address, data and R/W buffers. To force the
MPU into the High-impedance state, the TSC line
should be brought HIGH tpCST before the end of the
current cycle. The clocks for the MPU are then stopped
in the first quarter (E 0, Q 0) of the next cycle. To
regain the bus, the TSC line should be brought low, and
the clocks re-started.

BUSY. The BUSY output is used for arbitration of the
MPU bus. The BUSY signal signifies that the S6809E
will need the bus for at least the next cycle, as it is in
the middle of a multiple-byte data access. The BUSY
signal will be high forthe first two cycles of the operand
fetch of any Read-Modify-Write instruction, high during
the first operand fetch of any double-byte instructions
(LDD, STD) and high during the first byte access of any
indirect access or vector fetch operation. BUSY is not
active during pushes or pulls from the stack (PUL, PSH).
Figure 12 shows the timing for the BUSY signal for a

The TSC HIGH state is latched on the trailing edge of E,
and therefore should be timed accordingly.

Figure 10. EtQ Relationship
END OF CYCL~ (LATCH DATA)

START OF CYCLE

E~
k-~1

2.4V

ADDRESS VALID

I
I
I

Figure 11. S6809E Clock Generator
4Xfo
Osc.

SN74LS73

r-+- J

L-c

,K
l

IA)

(8)

L-c
5

......

5
R
~

SN74LS04

To MPU

VCCMin - VOL
IOL

7.73

•

AMI.---------."""4.

A Subsidiary

of Gould Inc.

51602

UNIVERSAL ASYNCHRONOUS
RECEIVER/TRANSMITTER

Features
o Full or Half Duplex Operation
Transmits and Receives Serial Data Slmul·
taneously or at Different Baud Rates
o Completely Programmable- Data Word Length,
Number of Stop Bits, Parity
o Automatic Start Bit Generation
o Data and Clock Synchronization Performed
Automatically
Block Diagram

Jl
TR.

J2
lR,

31
TRe

30
TR6

29
TR4

28
TR3

27
TR2

o
o
o
o
o
o
o

Double Buffered- Eliminates Timing Difficulties
Completely Static Circuitry
Fully TIL Compatible
Three·State Output Capability
Single Power Supply: + 5 V
Standard 40·Pin Dual·in·Line Package
Plug In Compatible with Western Digital TR1602A,
TR1B63, Fujitsu BB6BA
Pin Configuration

26
TR1

1~.5V

3[:>--2-0V
21
MR

Vee
40
TAC

23
THRl

LOAD

SBS

TIMING

·N.C

WLS,

RRD

WlS 2

RR,

SBS

RR)

CONTROL

31
WLS 2

EPE

Vss

THRE

36
WLS,

TRC

SHIFT

24
TAE

CAL

RR.

CRL

RR,

TR,

15
TAO

RR.

TR)

RR J

TA.

AA2

TR,

AR,

TA.

TA J

TA2

TR,

SFD

TRo

RRC

===::er-

RRC

TRE

ORR

OOL

THRE

3·STATE

OUTPUT

SFD

7.76

81602
General Description

word consisting of the data as well as start, parity, and
stop bit(s). Serial data is converted by the receiver section of the UART into parallel data. The receiver section
verifies correct code transmission by parity checking
and receipt of a valid stop bit. The UART can be programmed to accept word lengths of 5, 6, 7, or 8 bits.
Even or odd parity can be set. Parity generation checking can be inhibited. The number of stop bits can be
programmed for one, two, or one and one half when
transmitting a 5-bit code.

The AMI S1602 is a programmable Universal Asynchronous ReceiverlTransmitter (UART) fabricated with
N-Channel silicon gate MOS technology. All control
pins, input pins and output pins are TIL compatible,
and a single + 5 volt power supply is used. The UART
interfaces asynchronous serial data from terminals or
other peripherals, to parallel data for a microprocessor,
computer, or other terminal. Parallel data is converted
by the transmitter section of the UART into a serial
Absolute Maximum Ratings·

Vee Pin Potential to Vss Pin ................................................................................................................. - 0.3V to + 7.0V

+ 7.0V
Operating Temperature ........................................................................................................................... O°C to + 70°C
Input Voltage ........................................................................................................................................ - 0.3V to

Storage Temperature ....................................................................................................................... - 55°C to

+ 150°C

"Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the c.onditions as detailed in the operational sections of this data sheets. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Capacitance: TA
Symbol

=25°C; f = 1MHz; VIN =OV

Parameter
Input Capacitance for all Inputs

Guaranteed Operating Conditions (Referenced to VSS)
Symbol
Vee

Parameter

Operating
Temperature

+ 70°C

Min.

Typ.

Max.

Unit

4.75

5.0

5.25

0.0

Supply Voltage

O°C to

Vss
VIH

Logic Input High Voltage

O°C to + 70°C

2.2

Vee

VIL

Logic Input Low Voltage

O°C to + 70°C

-0.3

+0.8

Max.

Unit

1.4

rnA

+20

p.A

0.4

D.C. Characteristics (Guaranteed Operating Ranges Unless Otherwise Noted.)
Symbol

Min.

Parameter

IlL

Input Leakage Current (VIN = 0 to 5.25V, Vee = 5.25V)

ILZ

Output Leakage Current for 3- State (VOUT = OV to Vee,
SFD = RRD = VIH
Output Low Voltage (IOL = 1.8rnA)

VOL
VOH
lee

Typ.

-20

2.4

Output High Voltage (I0L = - 200J.lA)

Vee Supply Current

7.77

rnA

S1602
A.C. Characteristics (Guaranteed Operating Ranges Unless Otherwise Noted)
Symbol

Parameter

Min.

Typ.

Max.

Unit

800

kHz

Clock Frequency for RRC and TRC (Duty Cycle = 50%)

tpwe

CRL Pulse Width, High

200

tPWT

THRL Pulse Width, Low

180

tPWR

DRR Pulse Width, Low

180

tPWM

MR Pulse Width, High

150

Coincidence Time (Figure 3 and Figure 8)

180

ns
ns

tHOLD

Hold Time (Figure 3 and Figure 8)

tSET

Setup Time (Figure 3 and Figure 8)

tpDO

Propagation Delay Time High to Low, Output (C L = 130pF

350

tpD1

Propagation Delay Time Low to High, Output (CL =

350

Pin Description
Pin
Label
1
Vee
2
N.C.

3
4

VSS
RRD

5-12

SFD

17
18
19

RRC
DRR
DR

+ HTL)
130pF + 1TTL)

Function
Power Supply-normally at + 5V.
No Connection. On the S1602 this is an unconnected pin. On the TR1602A this is a -12V supply.
-12V is not needed on the S1602 and thus the N. C. pin allows the S1602 to be compatible with the
TR1602A.
This is normally at OV or ground.
Receive Register Disconnect. A high logic level, V1H , on this pin disconnects the Receiver Holding
Register outputs from the data outputs RRa-RR1 on pin 5-12.
Receiver Holding Register Data. These are the parallel outputs from the Receiver Holding Register, if
the RRD input is low (Vld. Data is (LSB) right justified for character formats of less than eight bits,
with RR1 being the least significant bit. Unused MSBs are forced to a low logic output level, VOL'
Parity Error. This output pin goes to a high level if the received parity does not agree with that programmed by the Even Parity Enable input (pin 39). This output is updated as each character is
transferred to the Receiver Holding Register. The Status Flag Disconnect input (pin 16) allows additional PE lines to be tied together by providing an output disconnect capability.
Framing Error. This output pin goes high if the received character has no valid stop bit. Each time a
character is transferred to the Receiver Holding Register, this output is updated. The Status Flag
Disconnect input (pin 16) allows additional FE lines to be tied together by providing an output
disconnect capability.
Overrun Error. This output pin goes high if the Data Received Flag (pin 19) did not get reset before
the next character was transferred to the Receive Holding Register. The Status Flag Disconnect input
(pin 16) allows additional DE lines to be tied together providing an output disconnect capability.
Status Flag Disconnect. When this input is high, PE, FE, DE, DR and THRE outputs are forced to high
impedance Three-State allowing bus sharing capability.
Receive Register Clock. This clock input is 16x the desired receiver shift rate.
Data Received Reset. A low level input, V1L, clears the Data Received (DR) line.
Data Received. When a complete character has been received and transferred to the Receiver Holding
Register, this output goes to the high level, VOH .
Receiver Input. Serial input data enters on this line. It is transferred to the Receiver Register as determined by the character length, parity and number of stop bits. When data is not being received, this
input must remain high, V1H .
7.78

81602
Pin Description
Pin

Label

Function

Master Reset. A high level pulse, V1H , on this input clears the internal logic. The transmitter and
Receive Registers, Receiver Holding Register, FE, OE, PE, DRR are reset. In addition, the serial output line is set to a high level, VOH.

THRE

Transmitter Holding Register Empty. This output will go high when the Transmitter Holding Register
completes transfer of its contents to the Transmitter Register. The high level indicates a new
character may be loaded into the Transmitter Holding Register.
Transmitter Holding Register Load. When a low level, V1L , is applied to this input, a character is loaded
into the Transmitter Holding Register. The character is transferred to the Transmitter Register on a
low to high level, V1H , transition as long as the Transmitter Register is not currently in the process of
transmitting a character. If a character is being transmitted, the transfer is delayed until the transmission is completed. The new character is then transferred simultaneously with the start of the
serial transmission of the new character.

TRE

Transmitter Register Empty. Goes high when the Transmitter Register has completed the serial transmission of a full character including the required number of stop bits. A high will be maintained until
the start of transmission of the next character.

TRO

Transmitter Register Output. Transmits the Transmitter Register contents (Start bit, Data bits, Parity
bit and Stop bit(s) serially. Remains high, VOH, when no data is being transmitted. Therefore, start
of transmission is determined by transition of the Start bit from high to low level voltage, VOL.
Transmitter Register Data Inputs. The THRL strobe loads the character on these lines into the
Transmitter Holding Register. If WLS 1 and WLS 2 have selected a character of less than 8 bits, the
character is right justified to the least significant bit, TR1 with the excess bits not used. A high input
level, VIH, will cause a high output level, VOH, to be transmitted.

26-33

CRL

Control Register Load. The control bits, (WLS 1 , WLS2, EPE, PI, SBS), are loaded into the Control
Register when the input is high. This input may be either strobed or hard wired to the high level.

Parity Inhibit. Parity generation and verification circuitry are inhibited when this input is high. The PE
output will be held low as well. When in the inhibit condition the Stop bit(s) will follow the last data
bit on transmission.

SBS

Stop Bit(s) Select. A high level will select two Stop bits, and a low level selects one Stop bit. If 5-bit
words are selected, a high level will generate one and one-half Stop bits.

37, 38

Word Length Select. The state of these two (2) inputs determines the character length (exclusive of
parity) as follows:
WLS 2

WLS 1

LOW

5 bits

LOW

HIGH

6 bits

WORD LENGTH

HIGH

LOW

7 bits

HIGH

8 bits

EPE

Even Parity Enable. A high voltage level, V1H , on this input will select even parity, while a low voltage
level, V1L , selects odd parity.

TRC

Transmitter Register Clock. The frequency of this clock input should be 16 times the desired baud
rate.

7.79

I
~__

51602

Figure 1. Receiver Operator Timing

, ,,"'-

START

.",.---- ..... .....

" STOP START
OATA

RII

I
I

RRI-RR S' PE, OE,
FE

I
I
I

I I I

I
\

STOP

OATA

-I

IL
Lf

I
I

ORR

SEE FIG. 2 FOR OETAIL

U~/

Figure 2. Timing for Status Flags, RR1 thru RRs and DR
10

RRC

OMINAL-sTOP
TRANSITION

, NOMINAL

STOP BIT

*,-----------

I I BIT CENTER
I I

PE, FE _ _ _ _ _ _ _ _ _ _ _..........
1

RR1-:~ ________________________-J*~~:----------------------1 - - -........ MIN 500n, +1/2 CLOCK

ORR
MAX 500n,
OR

7.80

81602

Figure 3. Transmitter Operator Timing

---+1---'

lDATA

-I..
/""1"

,...---

-----+I-n' ~~~~--I((J~

I' I:U:I

THRL

\i- . . . I
I

THRF

,'I

I SEE
,

I
I

U: l I

FIG. 6

,FOR DETAIL

Ir--:-l- - - - - I

I~-+!~i--~n~-r!------~I
I
I,

TRE

TRO

[DATA

START)

'-_/

kl+l--DA-TA---r-I--

_--,...

STOP ,;J!iTART

......

STOP

SEE FIG. 5
FOR DETAIL

Figure 4. Data Input Load Cycle

VIH

Vil

/l r- -

-----"--'
THRL

,---------,
---y

\.+- - - ---

-- --- -----i

tSH I--te
I-

tPWT - - - + I

7.81

'-------

L-\_

81602

Figure 5. Transmitter Output Timing(1)
INPUT
TRC

CRt

CFt

CR2

CF2

CRJ

CFJ

CR4

CF4

INPUT
THRL

OUTPUT
THRE

TO TRANSMITTER
HOLOING REGISTER

-i) -

OUTPUT
TRE
MAX
500ns

OUTPUT
TRO

MAX
500ns -+NOTES:
1. When the positive transition of THRL is SOOns or more before the falling edge of TRC (CF2 in the
figure), TRE is enabled at CF2. But, when soons>G»ons, TRE is invalid between CF2 and CF3.
2. THRE goes to low during SOOns Max. from the positive transition of THRl.
3. TRE goes to low during SOOns Max. from the first falling edge of TRC after THRE goes to low with
TRE high.
4. TRO goes to low (START BIT) during SOOns Max. from the first rising edge of TRC after TRE goes to
low.
S. THRE goes to high during SOOns Max. from the falling edge of TRC after START BIT is enabled.

Figure 6. Transmitter Output Timing(2)

INPUT
THRL

OUTPUT
THRE

OUTPUT
TRE
OUTPUT
TRO
OATA

NOTES:
2·S, refer to Figure S.
6. TRANSMITTER REGISTER EMPTY goes to high during SOOns Max. from the lSth rising edge of
TRC after STOP BIT is enables.

7.82

51602

Figure 7. Input After Master Reset

Figure 9. Status Flag Output

SFD

THRL

VIL

PE
DE
DR
THRE

Figure 8. Control Register Load Cycle

:~~~

VIH SBS ___ ~JJ.,'PI
EPE

Figure 10. Data Output

--=-==--=-----==-"\

RRD

- - - - - - - -

CRL

7.83

_ t pDO

•

AMI.---------."""'4.

A Subsidiary
of Gould Inc.

82350

UNIVERSAL SYNCHRONOUS
RECEIVER/TRANSMITTER

Features
o 500kHz Data Rates
0 Internal Sync Detection
0 Fill Character Register
0 Double Buffered Input/Output
0 Bus Oriented Outputs
0 5-8 Bit Characters
0 Odd/Even or No Parity
D Error Status Flags
0 Single Power Supply ( + 5V)
0 Input/Output TTL-Compatible

General Description
The S2350 Universal Synchronous Receiver Transmitter (USRT) is a single chip MOS/LSI device that
totally replaces the serial-to-parallel and parallel-toserial conversion logic required to interface a word
parallel controller or data terminal to a bit-serial, synchronous communication network.
The USRT consists of separate receiver and transmitter sections with independent clocks, data lines and
status. Common with the transmitter and receiver are
word length and parity mode. Data is transmitted and
received in a NRZ format at a rate equal to the respective input clock frequency.

Block Diagram

Pin Configuration

GND Vee

GND

TDs 138:.;,.1f - - - - -......---,
eli
151
1391
Noa,
1401
NDB2

141
NPB 131

Tep

1361

AR 1'31
1371

Rep

TBMrl91
171
Fer
181
RPE

1'01

ROA (11)

RDA

1121

NDB2

Vee

NDB,

NPB

filS

POE

RCP

rcp

rso

RilE

FCr

SWE

SCR

RDo

rBMr

RD,

RPE

RD2

ROR

RD3

RDA

RD4

iii!

RDs

RESET

RDs

RD7

RSI

ill

RSS

1141
ASI

RD7 AD6 RDS RD4 RD3 R02 ADl ROO
TBMT FeT
seR APE RCA RDA

7.84

S2350
Data messages are transmitted as a contiguous character stream, bit synchronous with respect to a clock
and character synchronous with respect to framing or
"sync" characters initializing each message. The USRT
receiver compares the contents of the internal Receiver
Sync Register with the incoming data stream in a bit
transparent mode. When a compare is made, the
receiver becomes character synchronous formatting a
5,6, 7, or 8-bit character for output each character time.
The receiver has an output buffer register allowing a full
character time to transfer the data out. The receiver
status outputs indicate received data available (RDA),
receiver overrun (ROR), receive parity error (RPE) and
sync character received (SCR). Status bits are available
on individual output lines and can also be multiplexed
onto the output data lines for bus organized systems.
The data lines have tri-state outputs.

with correct parity at the transmitter serial output (TSO).
The transmitter is buffered to allow a full character time
to respond to a transmitter buffer empty (TBMn request for data. Data is transmitted in aNRZ format
changing on the positive transition of the transmitter
clock (TCP). The character transmitter fill register is inserted into the data message if a data character is not
loaded into the transmitter after a TBMT request.
Typical Applications

0 Computer Peripherals
D Communication Concentrators
0 Integrated Modems
0 High Speed Terminals
D Time Division Multiplexing

The USRT transmitter outputs 5, 6, 7, or 8-bit characters

0 Industrial Data Transmission

Absolute Maximum Ratings
Ambient Temperature Under Bias ...................................................... O°C to + 70°C
Storage Temperature ............................................................ - 65°C to + 150°C
Positive Voltage on Any Pin With Respect to GROUND ............................................. + 7V
Negative Voltage on Any Pin With Respect to GROUN 0 ........................................... - O.5V
Power Dissipation .......................................................................... O.75W

D.C. (Static) Electrical Characteristics* (Vee = 5.0V ± 5%; TA = O°C to
Symbol

+ 70°C unless otherwise noted)

Parameter

Min.

Max.

Unit

VIH
VIL

Input High Voltage

2.0

Vcc

Input Low Voltage

-0.5

+0.8

IlL

Input Leakage Current

jJ.A

VIN

VOH

Output High Voltage

IOH

VOL

Output Low Voltage

CIN
Cour

Input Capacitance

Output Capacitance

Icc

Vcc Supply Current

100

Typ.

2.4
+0.4

Condition

= Oro Vcc V
= -100jJ.A
IOL = 1.6mA
VIN = OV; f = 1.0MHz
VIN = OV; f = 1.0MHz
No Load; Vcc = 5.25V

* Electrical Characteristics included in this advanced product description are objective specifications and may be subject to change.
A.C~

(Dynamic) Electrical Characteristics* (Vee

Symbol

Parameter

rcp,

Clock Frequency

RCP

=5.0V ±

5%; TA

=O°C to + 70°C unless otherwise noted)
Condition

7.85

_
:
- -

82350
A.C. (Dynamic) Electrical Charcteristics· (Continued)
Symbol I Parameter

Min.

Typ.

Max.

Unit

Condition

Input Pulse Width
PTCP

Transmit Clock

900

nsec

CL = 20pF

PRCP

Receive Clock

900

nsec

1TTL Load

PRST

Reset

500

nsec

PTOS

Transmit Data Strobe

200

nsec

PTFS

Transmit Fill Strobe

200

nsec

PRSS

Receive Sync Strobe

200

nsec

PCS
PROE

Control Strobe

200

nsec

Receive Data Enable

400

nsec

Note 1

PS WE

Status Word Enable

400

nsec

Note 1

500

nsec

PRR
Receiver Restart
Switching Characteristics
TTSO

Delay, TCP Clock to Serial Data Out

700

nsec

TTBMT

Delay, TCP Clock to TBMT Output

1.4

",sec

TTBMT

Delay, TDS to TBMT

700

nsec

TSTS

Delay, SWE to Status Reset

700

nsec

TROD
THROD

Delay, SWE, RDE to Data Output

400

nsec

1TTL Load

Hold Time SWE, RDE to Off State

400

nsec

CL = 130pF

TOTS

Data Set Up Time TDS, TFS, RSS, CS

nsec

TOTH

Data Hold Time TDS

700

nsec

TOTI

Data Hold time TFS, RSS

200

nsec

TCNS

Control Set Up Time NDB1, NDB2, NPB, POE

TCNH
TROA

nsec

Control Hold Time NDB1, NDB2, NPB, POE

200

nsec

Delay RDE to RDA Output

700

nsec

NOTE 1: Required to reset status and flags.

7.86

AMI.---------r

......

A Subsidiary
of Gould Inc.

86551186551 A

ASYNCHRONOUS COMMUNICATION
INTERFACE ADAPTER

Features
D On-Chip Baud Rate Generator: 15 Programmable
Baud Rates Derived from a Standard 1.8432M Hz
External Crystal (50 to 19,200 Baud)
D Programmabl,e Interrupt and Status Register to
Simplify Software Design
o Single + 5 Volt Power Supply
o Serial Echo Mode
D False Start Bit Detection
o 8-Bit Bi-Directional Data Bus for Direct Communication With the Microprocessor
D External 16X Clock Input for Non-Standard Baud
Rates (Up to 125K Baud)
D Programmable: Word Lengths; Number of Stop
Bits; and Parity Bit Generation and Detection

Data Set and Modem Control Signals Provided
D Parity: (Odd, Even, None, Mark, Space)
D Full-Duplex or Half-Duplex Operation
D 5, 6, 7, 8 and 9-Bit Transmission

General Description
The S6551/S6551A is an Asynchronous Communication Adapter (ACIA) intended to provide interfacing for
the microprocessors to serial communication data
sets and modems. A unique feature is the inclusion of
an on-chip programmable baud rate generator, with a
crystal being the only external component required.

Pin Configuration

Block Diagram

TxD

R/W----..
cSo--"
Cs;----..
RSo--..

SELECT
AND
CONTROL
LOGIC

GND

R/W

eso

eS 1

IRQ

DCD

RES

DB7

DSR

Rxe

DB6

XTAL1

DB5

iRO

RxC

RS1 - - . .

XTAL1

XTAL2

DB4

iiES--..

XTAL2

RTS

DB3

eTS

DB2

TxD

DB1

DTR

DBa

DBoT
DB7

DTR

ill

7.87

RxD

DSR

RSo

DeD

RS1

Vee

86551/86551 A
Absolute Maximum Ratings
Supply Voltage Vee ............................................................................................................................ - O.3V to + 7.0V
Input/Output Voltage VIN .......................•........................................................................•....•..•............... - O.3V to + 7.0V
e
Operating Temperature Range TA .............................................................................................................. oDe to + 70 D
Storage Temperature Range Tstg ...................................................................................................... - 55 D to + 150 D

All inputs contain protection circuitry to prevent damage to high static charges. Care shouldbe exercised to prevent unnecessary appli·
cation of voltages in excess of the allowable limits.
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifica·
tion is not implied.

Electrical Operating Characteristics (Vee

=5.0V ± 5%, TA =oDe to

+ 70 De,

unless otherwise noted)

Symbol

Parameter

V1H
V1L

Input High Voltage

2.0

Input Low Voltage

- 0.3

Min.

Typ.

Max.

Units

Vcc
0.8

ITSI

Input Leakage Current: V1N = 0 to 5V (<\>2, R/W, RES,
CS a, CS 1 , RS a, RS 1 , CTS, RxD, DCD, DSR)
Input Leakage Current for High Impedance State (Three State)

VOH

Output High Voltage: ILOAO = -100J.tA (DBa-DB?, TxD,
Rx C, RTS, DTR)

2.4

VOL

Output Low Voltage: ILOAO =1.6mA (DBa-DB?, TxD,
Rx C, RTS, DTR, IRQ)

0.4

IOH

Output High Current (Sourcing): VO H= 2.4V (DBa-DB?,
Tx D, Rx C, RTS, DTR)

-100

J.tA

IOL

Output Low Current (Sinking): VOL = 0.4V (DBa-DB?,
Tx D, Rx C, RTS, DTR, IRQ)

1.6

Output Leakage Current (Off State): VOUT = 5V (IRQ)
Clock Capacitance (<\>2)

1.0

10.0

J.tA

Input Capacitance (Except XTAL 1 and XTAL2)

CO UT

Output Capacitance

Power Dissipation (See Graph) (TA = O°C)

170

300

liN

IOFF
CCLK
CIN

Write Cycle (Vee

=5.0V ± 5%, TA =oDe to

±1.0

±2.5

J.tA

±2.0

±10.0

J.tA

+ 70 De, unless otherwise noted)
S6551

Symbol
tCYC
tc
tACW
tCAH
twcw
tCWH
tocw
tHW

Parameter
Cycle Time
<\>2 Pulse Width
Address Set-Up Time
Address Hold Time
R/W Set-Up Time
R/W Hold Time
Data Bus Set-Up Time
Data Bus Hold Time

Min.
1.0
400
120
0
120
0
150
20

(tr and tj = 1a to 3ans)

7.88

Max.
-

Min.
0.5
200
70
0
70
0
60
20

S6551A
Max.
-

Unit
J.ts
ns
ns
ns
ns
ns
ns
ns

86551/86551 A

Figure 1. Power Dissipation vs. Temperature

200

175

TYPICAL
POWER
IIISSIPAnDN
(mW)

150

125
100

'"
o

40
60
fAMBlEHT(OC)

Figure 2. Write Timing Characteristics
1 - - - - - - - - - tcyc - - - - - - - - . . l
~---VIH

CSo. Cs,. RSO. RS,

•

~----------~

.....JI_

VIL

~~~~~~~~~~~ ~~---t-oow---------t-~--~i ~'VMII.

DATA B U S " " '_______________

Read Cycle (Vee

=5.0V ± 5%, TA =O°C to + 70°C, unless otherwise noted)
S6551A

S6551
Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

tCYC

Cycle Time

1.0

0.5

+2 Pulse Width

400

200

tACR

Address Set-Up Time

120

tCAR

Address Hold Time

tweR

R/W Set-Up Time

120

teDR

Read Access Time (Valid Data)

200

150

tHR

Read Hold Time

teDA

Bus Active Time (Invalid Data)

7.89

/As
ns
ns

86551/86551 A

Figure 3. Clock Generation
XTAL1

o
OPEN

XTAL2

CIRCUIT

XTAL2 7

6551
INTERNAL CLOCK

EXTERNAL CLOCK

Figure 4. Read Timing Characteristics

CIa. CS,. RSa. RS,

J-------~----------------+-----------------------~

DATA BUS

-----------+---1

Transmit/Receive Characteristics

S6551A

S6551
Symbol

Parameter

Min.

tcCY

Transmit/Receive Clock Rate

tCH

Transmit/Receive Clock High Time

tCl

Transmit/Receive Low Time

too

EXTAL 1 to TxD Propagation Delay

tOlY
tlRQ

Max.

Min.

400*

175

500

Propagation Delay (RTS. DTR)

IRQ Propagation Delay (Clear)

(Ir and If= 10 10 30ns)

*The baud rate with external clocking is: Baud Rate =

16x tCCY

7.90

Max.

Unit

400*

175

500

550

56551/56551 A

Figure 5. Test Load for Data Bus (DBo-DB7), TxD,
DTR, RTS Outputs

Figure 6a. Interrupt and Output Timing

Vee

2.4kQ

S6551 PIN

---..--_--f(t--t-----

".~

24kQ

Figure 6c. Receive External Clock Timing

Figure 6b. Transmit Timing with External Clock

-IeH------jleey

XTAL1
(TRANSMIT
C~OCK IMPUTj

TxO

,..---,
\

.:N"

~I--le-L_---"li

leey

)-..

--IeL-------f

~\~~

NOTE: RxD RATE IS 1/16 RxC RATE.

NOTE: TxD RATE IS 1/16 TxC RATE.

Pin Description
RES (Reset). During system initialization a low on the
RE8 input will cause internal registers to be cleared.
~2 Input Clock. The input clock is the system ~2 clock
and is used to trigger all data transfers between the
system microprocessor and the 86551.

R1W (Read/Write). The RIW is generated by the microprocessor and is used to control the direction of data
transfers. A high on the RiW pin allows the processor to
read the data supplied by the 86551. A low on the RIW
pin allows a write to the 86551.
IRQ (Interrupt Request). The IRQ pin is an interrupt Signal
from the interrupt control logic. It is an open drain output, permitting several devices to be connected to the
common IRQ microprocessor input. Normally a high
level, IRQ goes low when an interrupt occurs.

CSO-CS1 (Chip Selects). The two chip select inputs are
normally connected to the processor address lines
either directly or through decoders. The 86551 is selected when C80 is high and 'CS1 is low.
RSo, RS1 (Register Selects). The two register select lines
are normally connected to the processor address lines
to allow the processor to select the various 86551 internal registers. The following table indicates the internal
register select coding:
Table 1
RS 1
0
0

RSo
0
1

1
1

0
1

READ
WRITE
Receiver Data Register
Transmit Data Register
Programmed Reset
Status Register
(Data is "Don't Care")
Command Register
Control Register

The table shows that only the Command and Control
registers are read/write. The Programmed Reset operation does not cause any data transfer, but is used to
clear the 86551 registers. The Programmed Reset is
slightly different from the Hardware Reset (RE8) and
these diferences are described in the individual register
definitions.

DBo-DB7 (Data Bus). The DBo-DB? pins are the eight
data lines used for transfer of data between the processor and the 86551. These lines are bi-directional and
are normally high-impedance except during Read
cycles when selected.
7.91

•

86551186551 A
D'SR (Data Set Ready). The "'[)"SR input pin is used to indi-

XTAL 1, XTAL2 (Crystal Pins). These pi ns are normally
directly connected to the external crystal (1.8432MHz
M-Tron MP-2 recommended) used to derive the various
baud rates. Alternatively, an externally generated clock
may be used to drive the XTAL 1 pin, in which case the
XTAL2 pin must float.
TxD (Transmit Data). The TxD output line is used to
transfer serial NRZ (non-return-to-zero) data to the
modem. The LSB (least significant bit) of the Transmit
Data Register is the first data bit transmitted and the
rate of data transmission is determined by the baud
rate selected.
RxD (Receive Data). The RxD input line is used to
transfer serial NRZ data into the ACIA from the
modem, LSB first. The receiver data rate is either the
programmed baud rate or the rate of an externally
generated receiver clock. This selection is made by
programming the Control Register.
RxC (Receive Clock). The RxC is a bi-directional pin
which serves as either the receiver 16xclock input or
the receiver 16xclock output. The latter mode results if
the internal baud rate generator is selected for receiver
data clocking.
RTS (Request to Send). The RTS output pin is used to
con!!:2.!.. the modem from the processor. The state of
the RTS pin is determined by the contents of the Command Register.
CTS (Clear to Send). The CTS input pin is used to con!!:2!..,the transmitter operation. The enable state is with
CTS low. The transmitter is automatically disabled if
CTS is high.
DTFt (Data Terminal Ready). This output pin is used to
indicate the status of the S6551 to the modem. A low on
DTR indicates the S6551 is enabled and a high indicates it is disabled. The processor controls this pin via
bit a of the Command Register.
Figure 8. Control Register Format
o
1

1 STOP BIT
2 STOP BITS
1 STOP BIT IF WORD LENGTH
~ 5 BITS AND ND PARITY
III STOP BITS IF WORD LENGTH
~ 5 BITS AND NO PARITY

WORD LENGTH

1&7
D

DATA WORD
LENGTH

RECEIVER CLDCK SDURCE
D
1

EXTERNAL RECEIVER CLOCK
BAUD RATE GENERATOR

Note: If Command Register Bit 0 1 and a change of state on DSR
occurs, IRQ will be set, and Status Register Bit 6 will reflect the
new level. The state of DSR does not affect either Transmitter or
Receiver operation.

DCD (Data Carrier Detect). The DCD input pin is used to
indicate to the S6551 the status of the carrier-detect
output of the modem. A low indicates that the modem
carrier signal is present and a high, that it is n.ot. DCD,
like DSR, is a high-impedance input and must not be a
no-connect.
Note: If Command Register Bit 0 = 1 and a change of state on DCD
occurs, IRQ will be set, and Status Register Bit 5 will reflect the
new level. The s!ate of oCDdoes not affect Transmitter operation,
but must be low for the Receiver to operate.

Figure 7. Transmitter/Receiver Clock Circuits

RECEIVER

~h'
~~~~EKR

RxC

CONTROL
REGISTER
BIT 4='"1"

SYNC
lOGIC

( -;. 16)

·r

~ MOO~'

:-.

XTAl2

RATE
GENERATOR

Iff I fT
BITS 0·3 IN
CONTROL
REGISTER

OIVIDER
(-;. 16)

TRANSMITTER
SHIFT REGISTER

TxD

CONTROL REGISTER
1716

STOP BITS

cate to the S6551 the status of the modem. A low indicates the "ready" state and a high, "not-ready." DSR is
a high-impedance input and must not be a no-connect.
If unused, it should be driven high or low, but not
switched.

514

31211

III I
0

BAUO RATE
GENERATOR
16x EXTERHAL CLOCK
50

150

3DO

600

120D

1800

134.58

2400

3600

48UO

72UO

9600

19,200

'TIIIS ALLOWS FOR 9·BIT TRANSMISSION (8 DATA BITS PLUS PARITY).

7.92

BAUO

75
109.92

:::::AA:~:::~T I I I I: I : I: I: I : I
D

S6551/S6551 A
Internal Organization

Control Register

The Transmitter/Receiver sections of the S6551 are
depicted by the block diagram in Figure 7.

The Control Register is used to select the desired
mode for the S6551. The word length, number of stop
bits, and clock controls are all determined by the Control Register, which is depicted in Figure 8.

Bits 0-3 of the Control Register select the divisor used
to generate the baud rate for the Transmitter. If the
Receiver clock is to use the same baud rate as the
Transmitter, then RxC becomes an output pin and can
be used to slave other circuits to the S6551.
Figure 9. Command Register Format

COMMANO REGISTER

1 7 i&i

PARITY CHECK CONTROLS
BIT

i4l

21 1
J

1 0J

DATA TERMINAL READY

OPERATION

Command Register
The Command Register is used to control Specific
Transmit/Receive functions and is shown in Figure 9.

- -

PARITY DISABLED
NO PARITY BIT
GENERATED
NO PARITY BIT RECEIVED

000 PARITY RECEIVER AND TRANSMITIER

EVEN PARITY RECEIVER AND
TRANSMITIER

MARK PARITY BIT TRANSMITIED,
PARITY CHECK DISABLED

SPACE PARITY BIT TRANSMITIED,
PARITY CHECK DISABLED

DISABLE RECEIVER AND ALL
INTERRUPTS (llfl!lUGH)
1 = ENABLE RECEIVER AND ALL
INTERRUPTS (DTJrlOW)
RECEIVER INTERRUPT ENABLE

iRQlMTERRUPT ENABLED FROM BIT 3
OF STATUS REGISTER
1 = iRQlMTERRUPT DISABLED
TRANSMITIER CONTROLS
BIT

~'2

NORMAUECHO MOOE
FOR RECEIVER

o = NORMAL
1 = ECHO (BITS 2 AND 3
MUST BE "0")

lrfS

TRANSMIT
INTERRUPT

LEVEL

TRANSMITIER

DISABLED

HIGH

OFF

ENABLED

LOW

DISABLED

LOW

DlSABLEO

LOW

TRANSMIT BRK

HARDWARE RESET
PROGRAM RESET

0
-

0
0

I I I I I I I II

Status Register

Figure 10. Status Register Format

The Status Register is used to indicate to the processor the status of various S6551 functions and is
outlined in Figure 10.

O",NIlTEMPTY

WRI'Tl:T1IAMSMIT

~ ~ :!!.~

NOTRESETTA8lE
REFLECTSiitii

Transmit and Receive Data Registers
These registers are used as temporary data storage for
the S6551 Transmit and Receive circuits. The Transmit
Data Register is characterized as follows:
OBit 0 is the leading bit to be transmitted.
o Unused data bits are the high-order bits and are
"don't care" for transmission.
The Receive Data Register is characterized in a similar
fashion:
OBit 0 is the leading bit received.
o Unused data bits are the high-order bits and are "0"
for the receiver.
o Parity bits are not contained in the Receive Data
Register, but are stripped-off after being used for
external parity checking. Parity and all unused highorder bits are "0".

REGISTl:REMPTY

O",D1iitDW
1=iiili1llGH

1=INTERRUPT

STATE

RHlECrsDSFi

STATUS REGISTER

'lII)wn1lllVPTSEHER"TEOFORTHESE&DHMJON~

"ClEARED AUTOMATlCAtLY AFTER A READ OF RDR AND
THE MEXT ERROR FREE RECEI'T OF DATA

""
.... R""
PAOORAMRESET

I: I~ I' I: I:I:i : I
1 :

7.93

86551186551 A
Figure 11 illustrates a single transmitted or received
data word, for the example of 8 data bits, parity, and 1
stop bit.

Figure 11. Serial Data Stream Example
"MARK"

"MARK"

---"". I

I '

START
BIT

7.94

11 1 2 1 3 1 4 1 5 1 6 1 7 1 P luJ
¥

DATA BITS

PARITY
BIT
STOP BIT

AMI.---------.'

A Subsidiary
of Gould Inc.

S6821/S68A21/S68B21

PERIPHERAL INTERFACE
ADAPTER (PIA)

Features
D 8·Bit Bidirectional Bus for Communication with
the MPU
D Two Bidirectional 8·Bit Buses for Interface to
Peripherals
D Two Programmable Control Registers
D Two Programmable Data Direction Registers
D Four Individually·Controlied Interrupt Input Lines:
Two Usable as Peripheral Control Outputs
D Handshake Control Logic for Input and Output
Peripheral Operation
D High·lmpedance Three·State and Direct Transistor
Drive Peripheral Lines
D Program Controlled Interrupt and Interrupt Disable
Capability
D CMOS Compatible Peripheral Lines

D Two TTL Drive Capability on all A and B Side
Buffers
D TTL Compatible
D Static Operation

General Description
The S6821/S68A21/S68B21 are peripheral Interface
Adapters that provide the universal means of interfac·
ing peripheral equipment to the S6800/S68AOO/S68BOO
Microprocessing Units (MPU). This device is capable of
interfacing the MPU to peripherals through two 8·bit bi·
directional peripheral data buses and four control
lines. No external logic is required for interfacing to
most peripheral devices.
The functional configuration of the PIA is programmed
by the MPU during system initialization Each of the
Pin Configuration

Block Diagram

~3BI-+====================r======,~
GNO

PAD

CAl

CA2

PAl

IRGA

PA2

TRliB

PA3

RSO

PAS

RESET

PA6

PA7
PBO

PBl

PB2

PB3

S6821
S68A21
S68B21

PB4

PBS

CSl24

PB6

CS223

PB7

CSI

=34

NABlE25

T'liOi

31-+_ _ _ _ _ _ _ _ _---1

7.95

CBl

err

CB2

CSO

VCC

R/W

S6821 IS68A21 IS68B21
General Description (Continued)
peripheral data lines can be programmed to act as an
input or output, and each of the four control/interrupt
lines may be programmed for one of several control
modes. This allows a high degree of flexibility in the
overall operation of the interface.
The PIA interfaces to the 86800/868AOO/868800 MPUs

with an eight-bit bidirectional data bus, three chip
select lines, two register select lines, two interrupt request lines, read/write line, enable line and reset line.
These signals, in conjunction with 86800/868AOO/
868800 VMA output, permit the MPU to have complete
control over the PIA. VMA may be utilized to gate the input signals to the PIA.

Absolute Maximum Ratings:
Symbol

Value

Rating
Supply Voltage

-0.3 to

VIN

Input Voltage

-0.3 to

Operating Temperature Range

Tstg

Storage Temperature Range

8ja

Thermal Resistance

Vee

Unit

+ 7.0
+ 7.0

Vde
Vdc

+ 70°
to + 150°

°C

0° to
- 55°

°C

82.5

°C/W

Note: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields;
however, it is advised that normal precautions be taken to avoid application of anv voltage higher than maximum rated
voltages to this high impedance circuit.

Electrical Characteristics
Vee = 5.0V ± 5%, Vss = 0, TA
Symbol

= 0 to 70 e unless otherwise noted.
0

Conditions

Characteristic

Bus eontrollnputs (R/W, Enable, Reset, RSO, RS1, eso, eS1, eS2)
VIH

Input High Voltage

VIL

Input Low Voltage

Vss + 2.0

Vee

Vdc

Vss - 0.3

Vss + 0.8

Vdc

liN

Input Leakage Current

CIN

Capacitance

7.5

VIN = 0, TA = 25°C,
f=1.0MHz

Vss + 0.4

Vdc

ILOAD = 3.2 mAdc

1.0

2.5

~dc

VIN = 0 to 5.25 Vdc

Interrupt Outputs (IROA, IROB)
VOL

Output Low Voltage

ILOH

Output Leakage Current (Off State)

1.0

~dc

GOUT

Capacitance

5.0

Vss + 2.0

Vee

Vdc

Vss - 0.3

Vss + 0.8

Vdc

2.0

~dc

VIN = 0.4 to 2.4 Vdc

Vdc

ILOAD = - 205~dc
ILOAD = 1.6mAdc

VOH = 2.4 Vdc
VIN = 0, TA = 25°C,
f=1.0MHz

Data Bus (00-07)
VIH

Input High Voltage

VIL

Input Low Voltage

ITSI

Three State (Off State) Input Current

VOH

Output High Voltage

VOL

Output Low Voltage

Vss + 0.4

Vdc

CIN

Capacitance

12.5

Vss + 2.4

7.96

VIN = 0, TA = 25°C
f=1.0MHz

S6821/S68A21/S68B21
Electrical Characteristics (Continued)
Symbol Characteristic
Peripheral Bus (PAO·PA7, PBO·PB7, CA1, CA2, CB1, CB2)

Input Leakage Current

liN

R/W, Reset, RSO, CSO, CS1,
CS2, CA1, CB1, Enable

1.0

2.5

JAAde

VIN = 0 to 5.25 Vdc

PBO-PB7, CB2

2.0

JAAde

VIN = 0.4 to 2.4 Vdc

JAAde

VIH = 2.4 Vdc

Three·State (Off State)
Input Current

ITSI
IIH

Input High Current

PAO-PA7, CA2

-200

IOH

Darlington Drive Current

PBO-PB7, CB2

-1.0

IlL

Input Low Current

PAD-PA7, CA2

VOH

Output High Voltage

-400

-1.3

-2.4

mAde VIL = O.4Vdc
Vdc
ILOAD = - 200JAAdc
ILOAD = - 10JAAdc

VSS + 0.4

Output Low Voltage
Capacitance

CIN

mAde Vo = 1.5 Vdc

Vss + 2.4
Vcc- 1.O

PAO-P7, PBO-PB7, CA2, CB2
PAD-PA7, CA2

VOL

-10

Vdc

ILOAD = 3.2mAdc

VIN = 0, TA = 25°C,
f=1.0MHz

550

I mW I

Power Requirements

I Power Dissipation
=

A.C. (Dynamic) Characteristics Loading 30pF and one TIL load for PAO-PA7, PBO-PB7, CA2, CB2 130pF and
one TIL load for 00-07, IROA, IROB (Vee = 5.0V ± 5%, Vss = 0, TA = O°C to + 70°C unless otherwise specified)
Peripheral Timing Characteristics:

Vee - 5.0V ± 5%, Vss

=OV, TA =O°C to

+ 70°C unless otherwise specified

S6821
Symbol

Parameter

Min.

S68B21

S68A21

Max.

Min.

Max.

Min.

Max.

Units

t pDSU

Peripheral Data Setup Time

200

135

100

tpOH

Peripheral Data Hold Time

tCA2

Delay Time, Enable Negative Transition
to CA2 Negative Transition

1.0

0.670

0.5

/As

tRS1

Delay Time, Enable Negative Transition
to CA2 Positive Transition

1.0

0.670

0.50

/AS

tr,tf

Rise and Fall Times for CA 1 and CA2
Input Signals

t RS2

Delay Time from CA 1 Active Transition
to CA2 Positive Transition

2.0

1.35

1.0

/As

tpow

Delay Time, Enable Negative Transition
to Peripheral Data Valid

1.0

0.670

0.5

/As

tCMOS

Delay Time, Enable Negative Transition to
Peripheral CMOS Data Valid PAO·PA7, CA2

2.0

1.35

1.0

/As

1.0

7.97

1.0

/As

•

S6821/S68A21/S68B21
Peripheral Timing Characteristics (Continued)
S6821
Symbol

Parameter

tCB2

Delay Time, Enable Positive Transition
to CB2 Negative Transition

t De

Delay Time, Peripheral Data Valid to
CB2 Negative Transition

tRS1

Delay Time, Enable Positive Transition
to CB2 Positive Transition

Min.

S68A21

Max.

Min.

1.0

S68821
Min.

Max.
0.670

2.0
1.0

Max.

Units

0.5

",s

ns
0.5

0.670

",s

t r , tl

Peripheral Control Output Pulse Width,
CA2/CB2
Rise and Fall Times for CB1 and CB2
Input Signals

1.0

",s

t RS2

Delay Time, CB1 Active Transition to
CB2 Positive Transition

2.0

1.35

1.0

",s

t'R

Interrupt Release Time,
IROA and IROB

1.60

1.1

0.85

",s

1.0

",s

PWCT

550

tRS3
PW ,

Interrupt Response Time
Interrupt Input Pulse Width

500

tRL

Reset Low Time*

1.0

550

1.0

550

1.0
500
0.66

500

0.5

",s

*The Reset line must be high a minimum of 1.01-ls before addressing the PIA.

Figure 1. Enable Signal Characteristics

Figure 2. Bus Read Timing Characteristics
(Read Information from PIA)

0.8V
DATA BUS

Figure 3. Bus Write Timing Characteristics
(Write Information into PIA)

Figure 4. Bus Timing Test Loads

100-071

2.0V

5.0V

O.8V
-4--- lAS

RS.

cs.

RNi

2.0V
O.8V

C
130pF

2.0V
O.8V

7.98

R
l1.7k

MM07000

DR EOUIV.

S6821 IS68A21 IS68B21
Bus Timing Characteristics (Vee

= + 5.0V

± 5%, VSS

=0, TA =TL to TH unless otherwise noted.)
S6821

S68A21

S68821

Symbol

Parameter

Min.

tCYC(E)
PW EH

Enable Cycle Time

1000

666

500

Enable Pulse Width, High

450

280

220

PW EL

Enable Pulse Width, Low

430

tEr ,tEt

Enable Pulse Rise and Fall Times

tAS

Setup Time, Address and R/W Valid to Enable
Positive Transition

160

tAH

Address Hold Time

tOOR

Data Delay Time, Read

tOHR

Data Hold Time, Read

tosw
tOHW

•,1

Max.

Min•

Max.

280
25

Min.

140

10
220

ns
ns

Units

210
25

320

Max.

180

Data Setup Time, Write

10
195

Data Hold Time, Write

Figure 5. TTL Equiv. Test Load

Figure 6. CMOS Equiv. Test Load

Figure 7. NMOS Equlv. Test Load

(PAO·PA1,PBO·P87,CA2,CB21

5'OV

Vee

~k:

TEST'O'NT~

~
0

0 4V AND Vee

5.2SV

Figure 9. CA2 Delay Time
(Read Mode; CRA-5 = CRA-3 = 1, CRA-4 = 0)

Figure 8. Peripheral Data Setup and Hold Times
(Read Mode)

PAD

PAl

PBO

PBI

~14V

O,BV

--'-O.;;.;.BV--- "-O
t:
H
-

"O'jU"-

A-:l~4V-:----

ENABLE

TESTPQINT

C'40pFR'12k

ADJUST RlSO THAT II - 3.1mA
WITH VI

•
~f'
liRO ONLYI

IPAO - PAl, PBO - PBI, CAl, CB21

_ _ _- - J

'CA2

2AV

O,BV

* Assumes part was deselected during the previous E pulse.

7.99

S6821/S68A21/S68B21

Figure 11. Peripheral CMOS Delay Times
(Write Mode; CRA-5 = CRA-3 = CRA-4 = 0)

Figure 10. CA2 Delay Time
(Read Mode; CRA-5 = 1, CRA-3 = CRA-4 = 0)

ENABlE~BV

'"""~"""

~!flf

10V

2.4V

--''t-10_4v_ _ _ _ _ __

CA1 _ _ _ _

Figure 13. CB2 Delay Time
(Read Mode; CRB-5 = CRB-3 = 1, CRB-4 = 0)

Figure 12. Peripheral Data and CB2 Delay Times
(Write Mode; CRB-5 = CRB-3 = 1, CRB-4 = 0)
\I

0.8V

f.--....

PBOPB7

tPOw

--------~Xr-24-V--------
________~ ~~0.4~V---------

i-1DC-j

'~
CB2 Note:
CB2 goes low as a result of the positive transition of Enable.

Figure 15. Interrupt Pulse Width and IRQ Response

Figure 14. Delay Time
(Write Mode; CRB-5 = 1, CRB-3 = CRB-4 = 0)

ENABl~10V

1.------ P W I I - - - .
CAI.CAI

(

1.0V

CBI.CB_l_ _---Jj\)-0.8_V____________-4'~

~'~(l----::-::-:-:,LJt-~II1'_ _

:::

''"'~, . ;,:' f\--2-!--~---

~-------- 'RS3.-------_~
*Assumes Interrupt Enable Bits are set.

*Assumes part was deselected during any previous E pulse.

Figure 17. Reset Low Time

Figure 16. IRQ Release Time

*The Reset line must be a VIH for a minimum of 1.0j.1S
before addressing the PIA.

7.100

AMI.---------."""'4.

A Subsidiary
of Gould Inc.

S6840/S68A40/S68B40

PROGRAMMABLE
TIMER

Features
o Operates from a Single 5 Volt Supply
o Fully TTL Compatible
o Single System Clock Required (Enable)
o Selectable Prescaler on Time 3 Capable of 4MHz
for the S6840, 6MHz for the S68A40 and 8MHz
for the S68840
o Programmable Interrupts (IRQ) Output to MPU
o Readable Down Counter Indicates Counts to Go to
Time-Out
o Selectable Gating for Frequency or Pulse-Width
.9ol1J.Q.arison
o RESET Input
o Three Asynchronous External Clock and Gate!
Trigger Inputs Internally Synchronized
o Three Maskable Outputs

General Description
The S6840 is a programmable subsystem component
of the S6800 fami Iy designed to provide variable system
time intervals.
The S6840 has three 16-bit binary counters, three corresponding control registers and a status register.
These counters are under software control and may be
used to cause system interrupts and/or generate output signals. The S6840 may be utilized for such tasks
as frequency measurements, event counting, interval
measuring and similar tasks. The device may be used
for square wave generation, gated delay signals, single
pulses of controlled duration, and pulse width modulation as well as system interrupts.

Block Diagram

Pin Configuration
R/W

RSO

RSI

RS2

Csii

ENA8LE

CSI

(SYSTEM.p21

28
27
26
25
24
23
22
21
20
10

....

~
-

Vss

Vee

RESET

G3 C3

G2 C2

iii Ci

7.101

•

S6840/S68A40/S68B40
Absolute,Maximum Ratings
Supply Voltage Vee .............................................................. - 0.3 to + 7.0V
Input Voltage VIN ................................................................ - 0.3 to + 7.0V
Operating Temperature Range TA .................................................... 0° to + 70°C
Storage Temperature Range Tstg ................................................. - 55° to + 150°C
Thermal Resistance 8JA ............................................................... 82.5°C/W
Note: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however. it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

Electrical Characteristics: (Vee = 5.0V ± 5%, Vss = 0, TA =O°C to + 70°C unless otherwise noted.)
Symbol

VIH
VIL

Parameter

Typ.

Min.

Max.

Unit

Conditions

Input High Voltage

Vss + 2.0

Vcc

Input Low Voltage

Vss - 0.3

Vss + 0.8

1.0

2.5

/AA

VIN = 0 to 5.25 V

2.0

/AA

VIN = 0.4 to 2.4 V

V
V

ILOAD = - 205/AA
ILOAD = - 200/AA

V
V

ILOAD = 1.6mA
ILOAD = 3.2mA
VOH = 2.4V

liN

Input Leakage Current

ITSI
VOH

Three-State (Off State) Input Current
Output High Voltage

00-0 7
All Others

VOL

Output Low Voltage

00-0 7
01-03. IRQ

ILOH
PD
CIN

Power Dissipation

00-0 7

Output Leakage Current (Off State)

Capacitance

COUT

Vss + 2.4
Vss + 2.4
Vss + 0.4
Vss + 0.4

IRQ

1.0

/AA

550

00-0 7
All Others

12.5
7.5

VIN = O. TA = 25°C.
f= 1.0MHz

IRQ
01,02,03

5.0
10

VIN = 0, TA =
f= 1.0MHz

+ 25°C.

Bus Timing Characteristics
Read (See Figure 1)
S68840

S68A40

S6840
Characteristic

Min.

Max.

Min.

Max.

Min.

Max.

Unit

t CVCE

Enable Cycle Time

1.0

0.666

0.5

/As

PW EH

Enable Pulse Width, High

0.45

4.5

0.280

4.5

0.22

4.5

/As

PW EL

Enable Pulse Width, Low

0.43

0.280

0.21

/As

t AS

Setup Time. Address and R/W Valid to Enable
Positive Transition

160

140

Symbol

320

180

220

tODR

Data Delay Time

Data Hold Time

tAH

Address Hold Time

t Er .
tEl

Rise and Fall Times for Enable Input

7.102

56840/568A40/568B40
Bus Timing Characteristics (Continued)
Write (See Figure 2)
86840

868A40

868840

8ymbol

Characlerislic

Min.

Max.

Min.

Max.

Min.

Max.

teveE

Enable Cycle Time

1.0

0.666

0.5

f.!s

PW EH

Enable Pulse Width, High

0.45

4.5

0.280

4.5

0.22

4.5

f.!s

PW EL

Enable Pulse Width, Low

0.43

0.280

0.21

f.!S

tAS

Setup Time, Address and R/W Valid to Enable
Positive Transition

160

140

tosw

Data Setup Time

195

Data Hold Time

tAH

Address Hold Time

tEr'
tEt

Rise and Fall Times for Enable Input

Unit

ns
25

AC Operating Characteristics (See Figures 3 and 7)
868A40

86840
Symbol

Min.

Characteristic

Max.

868840
Max.

Min.

Max.

Unit

0.500"

f.!s

t r,
tf

Input rise and Fall Times
(Figures 4 and 5) C, 'Gand Reset

PW L

Input Pulse Width (Figure 4)
(Asynchronous Mode) C, Gand Reset

t cvCE + tsu

+ thd

teYCE + tsu

+ thd

teYCE + tsu

+ thd

PW H

Input Pulse Width (Figure 5)
(Asynchronous Mode) C,Gand Resei

tCYCE + tsu

+ thd

t cveE + tsu

+ thd

t CVCE + tsu

+ thd

tsu

Input Setup Time (Figure 6)
(Synchronous Mode)
C,G and Reset
C3 ( -;- 8 Prescaler Mode only)

thd

PW L,
PW H

tco
tcm
tcmos
tlR

1.0

Input Hold Time (Figure 6)
(Synchronous Mode)
C', Gand Reset
C3 ( -;- 8 Prescaler Mode only)
Input Pulse Width
(Synchronous Mode)
C3 (-;- 8 Prescaler Mode only)
Output Delay, 01-03 (Figure 7)
(VOH = 2.4V, Load 8)
(VOH = 2.4V, Load D)
(VOH = 0.7 Voo , Load D)
Interrupt Release Time

TTL
MOS
CMOS

0.666"

200

120

125

62.5

700
450
2.0

460
450
1.35

340
340
1.0

ns
ns
f.!s

1.2

0.9

0.7

f.!s

7.103

•

S6840/S68A40/S68B40
Figure 1. Bus Read Timing Characteristics
(Read Information from PTM)

Figure 2. Bus Write Timing Characteristics
(Write Information into PTM)
~_ _-I",'E---""'"

14-----I"',E---~

ENABLE

RS, CS, Rlii

RS,CS,RfiiI

DATA BUS
DATA BUS

Figure 4. Input Pulse Width High

Figure 3. Input Pulse Width Low

PW _
l

t,-.

-..

. -..

1 , - - - - - - -......1

Figure 6. Output Delay

Figure 5. Input Setup and Hold Time

ENABLE

9.:R 61·63

-Jm
01·03

RESET

7.104

\'-----

AMI.---------."""'4.

A Subsidiary
of Gould Inc.

S68045/S68A045/S68B045

CRT CONTROLLER (CRTC)

Features

o
o

o
o
o
o

Generates Refresh Addresses and Row Selects
Generates Video Monitor Inputs: Horizontal and
Vertical Sync and Display Enable
Low Cost; MC6845/SY6545 Pin Compatible
Text Can Be Scrolled on a Character, Line or
Page Basis
Addresses 16K Bytes of Memory
Screen Can Be Up to 128 Characters Tall By
256 Wide
Character Font Can Be 32 Lines High With
Any Width
Two Complete ROM Programs
Cursor and/or Display Can Be Delayed 0,1 or 2

o
o
o

Block Diagram

Clock Cycles
Four Cursor Modes:
- Non-Blink
- Slow Blink
- Fast Blink
- Reverse Video With Addition of a Single TTL Gate
Three Interlace Modes
- Normal Sync
- Interlace Sync
- Interlace Sync and Video
Full Hardware Scrolling
NMOS Silicon Gate Technology
TTL-Compatible, Single + 5 Volt Supply
Pin Configuration

•

TO REFRESH
MEMORY

V..

Rmf
PR06RAMSELECT

AAO)
AAI
ROW ADDRESSES
FOR CHARACTER
GENERATORS

RA2
RA3

33
REFRESH

00)

.... D2

MEMORY
ADDRESSES

PROG

. - . 03

DATA

BUS

PROCESSOR
INTERFACE

06
D7

TO CHARACTER
GENERATOR ROM

TO CRT

CS)

TO CRT

'~;

Vee Vss
CURSOR
Vee

ClK
W
CS
RESET
ENABLE

CONTROL
lOGIC

00-07

ADDRESS
REGISTER

7.105

CDNTROl

S68045/S68A045/S68B045
General Description
The 868045 CRT Controller performs the complex interface between an 86800 Family microprocessor and a
raster scan display CRT system. The 868045 is designed to be flexible yet low cost. It is configured to both
simplify the.development and reduce the cost of equipment such as intelligent terminals, word processing,
and information display devices.

horizontal and vertical 8YNC position and width are all
mask programmable. The 868045 is capable of addressing 16K of memory for display. The CRT may be scrolled or paged through the entire display memory under
MPU control. The cursor control register determines
the cursor location on the screen, and the cursor format
can be programmed for fast blink, slow-blink, or nonblink appearance, with programmable size. By adding a
single TTL gate, the cursor can even be reversed video.
The device features two complete, independent programs implemented in user-specified ROM. Either set
of programmable variables (SO/60Hz refresh rate,
screen format, etc.) is available to the user at any time.

The CRT Controller consists of both horizontal and
vertical counting circuits, a linear address counter, and
control registers. The horizontal and vertical counting
circuits generate the Display Enable, H8YNC, V8YNC,
and RAO-RA4 signals. The RAO-RA4 lines are scan line
count signals to the external character generator ROM.
The number of characters per character row, scan lines
per character row, character rows per screen, and the

The S68045 is pin compatible with the MC6845, operates from a single 5-volt supply, and is designed using
the latest in minimum-geometry NM08 technology.

Absolute Maximum Ratings
SupplyVoltageVcc .......................................................................................................................... -0:3°Cto +7.0°C
Input Voltage VIN ....•••••....•..••............••...•.......••........•..•.......................................................................... - 0.3V to + 7.0V
Operating Temperature Range TA ............................................................................................................ O°C to + 70°C
Storage Temperature Range Tstg .................................................................................................... - 55°C to + 150°C

Bus Timing Characteristics
S68045
Symbol

868A045

Max.

Min.

Parameter

Min.

tCYC(E)

Enable Cycle Time

1000

666

500

PW EH

Enable Pulse Width, High

450

280

220

PW EL

Enable Pulse Width, Low

430

tEr, tEf

Enable Pulse Rise and Fall Times

tAS

Setup Time, Address and R/W Valid to Enable
Positive Transition

160

140

tAH

Address Hold Time

t DSW

Data Setup Time, Write

195

tDHW

Data Hold Time, Write

280
25

7.106

Max.

8688045
Min.

Max.

210

Units

S68045/S68A045/S68B045
Electrical Characteristics
Vcc=5.0V±5%; Vss=O, TA=O°C to +70°C unless otherwise noted
Symbol

Parameter

VIH
VIL

Input High Voltage (except ClK)

2.0

Input low Voltage (except elK)
Input High Voltage Clock

- 0.3
2.2

Input low Voltage Clock
Input leakage Current
Output High Voltage

-0.3

VIHC
VILC
liN
VO H
VOL
Po
CIN
CO UT
PWGL
PWCH
fc
tcr, tcf
tMAD
tRAD
toTO
tHSD
tVSD

tCDD

Ouput Low Voltage
Power Dissipation
Input Capacitance

Min.

Typ.

Max.

Unit

Vcc
0.8

Vdc
Vdc
Vdc

Vcc
.45
1.0

J.lAdc
Vdc

0.4

Vdc

12.5
10
10

mW
pF
pF
pF

600
00-07
All Others

Output Capacitance-All Outputs
Minimum Clock Pulse Width, Low

160
200

Clock Pulse Width, High
Clock Frequency
Rise and Fall Time for Clock Input
Memory Address Delay Time
Raster Address Delay Time
Display Timing Delay Time
Horizontal Sync Delay Time
Vertical Sync Delay Time
Cursor Display Timing Delay Time

Systems Operation
The S68045 CRTC generates all of the signals needed
for the proper operation of a CRT system including
HSYNC, VSYNC, Display Enable, Cursor control signals (refer to Figure 1), the refresh memory addresses
(MAO-MA 13) and row addresses (RAO-RA4). The
CRTC's timing is derived from the ClK input, which is
divided down from the dot rate counter.
The CRTC, which is compatible with the 6800 family,
communicates with the MPU by means of the standard
8-bit data bus. This primary data bus uses a buffered
interface for writing information to the display refresh
RAM by means of a separate secondary data bus. This
arrangement allows the MPU to forget about the display except for those time periods when data is actually being changed on the screen. The address bus for
the refresh RAM is continuously multiplexed between
the MPU and the CRTC.
Since the MPU is allowed transparent read/write
7.107

Vdc

2.5

2.4

10,000
2.5
20
200
200

Condition

ILOAD = - 100J.lA
ILOAD = 1.6mA

ns
ns
MHz
ns
ns

300
300
300

ns
ns
ns
ns

300

access to the display memory, the refresh RAM appears as just another RAM to the processor. This
means that the refresh memory can also be used for
program storage. Care should be taken by the system
designer, however, to insure that the portion of
memory being used for program storage is not actively
displayed.
Displayed Data Control
Display Refresh Memory Addresses (MAO-MA13) - 14
bits of address provide the CRTC with access of up to
16K of memory for use in refreshing the screen.
Row Addresses (RAO-RA4) - 5 bits of data that provide the output from the CRTC to the character
generator ROM. They allow up to 32 scan lines to be included in a character.
Cursor - This TTL compatible, active high output
indicates to external logic that the cursor is being
displayed.

•

S68045/S68A045/S68B045

Figure 1. Typical CRT Controller System
MAIN
PROCESSOR

HORIZONTAL
SYHC

HIGH
SPEED
TIMING

REFRESH
RAM

YERllCAL
SYNC

CLOCK
CURSOR.
DISPLAY ENABLE.
DDT RATE
COUNTER

The character address of the cursor is held in a register,
so the cursor's position is not lost even when scrolled
off the screen.

Register Select - The RS line selects either the Address Register (RS = "0") or one of the Data Registers
(RS "1") of the internal Register File.

CRT Control

To address one of the software programmable registers
(R12, R13, R14 or R15 in Table 2) first access the
Address Register(CS 0, RS 0) and write the number
of the desired register. Then write into the actual
register by addressing the data register section (CS = 0,
RS 1) and enter the appropriate data.
Write (W) - The W line allows a write to the internal
Register File.

All three CRT control signals are TTL compatible, active
high outputs.
Display Enable - Indicates that valid data is being
clocked to the CRT for the active display area..
Vertical Sync (VSYNC) - Makes certain the CRTC and
the CRT's vertical timing are synchronized so the picture is vertically stable.

Data Bus (00-07) - The data bus lines (DO-D7) are
write-only and allow data transfers to the CRTC internal
register file.

Horizontal Sync (HSYNC) - Makes certain the CRTC
and the CRT's horizontal timing are synchronized so
the picture is horizontally stable.

Enable (E) - The Enable signal enables the data bus
input buffers and clocks data to the CRTC. This signal
is usually derived from the processor clock, and the
high to low transition is the active edge.

Processor Interface
All processor interface lines are three state, TTUMOS
compatible inputs.

S68045 Control Clock (ClK) - The clock signal is a
high impedance, TTUMOS compatible input which
assures the CRTC is synchronized with the CRT itself.
The ClK signal is divided down by external circuitry
from the dot rate counter. The ClK frequency is equal

Chip Select (CS)- The CS line selects the CRTC
whenlow to write to the internal Register File. This
signal should only be active when there is a valid stable
address being decoded from the processor.

7.108

8680451868A0451868B045
to the dot rate frequency divided by the width of a
single character block (including framing) expressed in
dots, ClK is equal to the character rate.
Program (PROG) - The voltage on this pin determines
whether the screen format in ROM 0 (PROG lOW) or
ROM 1 (PROG HIGH) is being used.
Reset (RES) - The RES input resets the CRTC. An (active) low input on this line forces these actions:
a) MAO-MA13 are loaded with the contents of R12/R13
(the start address register).
b) The horizontal, vertical, and raster address counter
are reset to the first raster line of the first displayed
character in the first row.
c) All other outputs go low.
Note that none of the internal registers are affected by
RES.
RES on the CRTC differs from the reset for the rest of
the 6800 family in the following aspects:
a) MAO-MA13 and RAO-RA4 go to the start addresses,
instead of FFFF.

control registers in the 68045, most of which are mask
programmed. The exceptions are the Address Register,
the two Start Address Registers (R12 & R13) and the
Cursor location Registers (R14 & R15). All software
programmable registers are write only. The Address
Register is 5 bits long. The software programmable
registers are made available to the data lines whenever
the chip select (CS) goes low. When CS goes high, the
data lines show a high impedance to the
microprocessor.
Horizontal Total Register (RO) - The full horizontal
period, expressed in character times, is masked in RO.
(See Figure 2a).
Horizontal Displayed Register (R1) - This register contains the number of characters to be actually displayed
in a row. (See Figure 2a).
Horizontal SYNC Position Register (R2) - The contents
of R2 (also in character times) should be slightly larger
than the value in R1 to allow for a non-displayed right
border. (See Figure 2a.)

b) Display recommences immediately after RES goes
high.

Sync Width Register (R3) - The width of the HSYNC
pulse expressed in character times is masked into the
lower four bits of R3. The width of the HSYNC pulse has
to be non-zero.

Internal Register Description -

The width of the VSYNC pulse is masked into the upper

There is a bank of 15

Figure 2a. Approximate Timing Diagram
1

I
I

,I...oIIl-------HORIZONTAL TOTALRO _ _ _ _ _ _~------_.I
;!...
" f - - - - -_

_ HORIZONTAL DISPLAY Rl _ _ _ _ _ _ _
• 1

HORIZ
OISPLAY------'
ENABLE

I :---1

RIGHT I
MARGIN

1 LEFT

r---1

I.......f - - - - - - - - HORIZONTAL SYNC POSITION R 2 - - - - - - - - - . . I
HSYNC-------L1

~~:~ R3

MARGIN

---1

- - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

FOR MORE EXACT DIAGRAMS REFER TO THE BACK OF THE DATA SHEET. THE HORIZONTAL DISPLAY ENABLE IS ANDED WITH THE VERTICAL DISPLAY ENABLE TO PRODUCE THE
DISPLAY ENABLE AT PIN 18. NOTE THE (a) FIGURE IS TlMEO IN TERMS OF INDIVIDUAL CHARACTERS, WHEREAS THE (b) FIGURE IS TIMED IN TERMS OF CHARACTER ROWS.

7.109

S68045/S68A045/S68B045
amount the cursor is delayed is independent of how
much the Display Enable signal is delayed. This 'feature
allows the system designer to account for memory address propagation delay through the RAM, ROM, etc.

four bits of R3 without any modification, with the exception that all zeroes will make VSYNC 16 characters
wide.
Vertical Total Register (R4) - This register contains
the total number of character rows - both displayed
and non-displayed - per screen. This number is just
the total number of scan lines used divided by the
number of scan lines in a character row. If there is a remainder, it is placed in R5. (See Figure 2b).

Maximum Scan Line Register (R9) - Determines the
number of scan lines per character row including top
and bottom spacing.

Vertical Total Adjust Register (R5) - See description of
R4. A fractional number of character row times is used
to obtain a refresh rate which is exactly 50HZ, 60HZ, or
some other desired frequency. (See Figure 2b).
Vertical Displayed Register (R6) - This register contains the total number of character rows that are actually displayed on the CRT screen. (See Figure 2b).
Vertical SYNC Position (R7) - R7 contains the position
of the vertical SYNC pulse in character row times with
respect to the top character row. Increasing the value
shifts the data up. (See Figure 2b).

The cursor can be in one of the following formats.
Non-blinking
Slow blinking (1/16 the vertical refresh period)
Fast blinking (1/32 the vertical refresh period)
Reverse video (non-blinking, slow blinking, or fast
blinking)
The reverse video cursor needs an external TTL XOR
gate to be placed in the video circuit.

Interlace Mode Register (R8) - R8 controls which of
the three available raster scan modes will be used (See
Figure 3).
-

Cursor Start Register (R10) - Contains the raster line
where the cursor start (see Figure 4). The cursor start
line can be anywhere from line a to line 31.

Non-interlace or Normal sync mode
Interlaced sync mode
Interlaced sync and Video mode

The Cursor and Display Enable outputs can be delayed
(skewed) 0, 1 or 2 clock cycles with respect to the
refresh memory address outputs (MAO-MA13). The

To implement the reverse video cursor, the cursor start
line (R10) should be set to line a and the cursor end line
(R11) should be set to whatever is in R9 so that the cursor covers the entire block. On the circuit level, the output from the Cursor pin (pin 19) should be taken through
the XOR gate along with the output from the shift
register. (See Figure 5.) With this setup the character
whose memory address is in the cursor register (R141
R15) will have its background high (because Cursor
alone is high) but the character itself will be off
(because both cursor and the character are both high.

Figure 2b. Approximate Timing Diagram
II
II

I
......c - - - - - - - - - - - VERTICAL

TOTAL R 4 1 - - - - - - - - - - - - - . - -- - - - - - 1...11
1

______I

I _ - - - - - - - V E R T I C A L IHSPLAYEO R6 _ _ _ _ _ _ _ _ _ _ _ _ _1

=i'

"j
I
I

~~r:~~ -----l

I
I

1......- - - - - - -

VERTICAL
ADJUST R5

:j
I

I
I

I TOP
~MARGIN

VERTICAL SYNC POSmoN R 7 ' - - - - - - - - - . l

7.110

VERTICAL SYNC WIDTH R3

S68045/S68A045/S68B045

Figure 3. Interface Control

0
0
0
0 0 0 0

1
2

0
0

5
6

SCAN LINE ADDRESS

0
0

0
0
0

0
0

-- r
)-0

)-0

~r"\ .r"\

)-0

r""

>-c

>:;
~

>-c

r"\

>-c

~~&~
-,..... - - - >-c
~
>:--

>)-0

-~ -

-~
'-"

>-c

r""
- >:;
2
>-c 4- ~

--0

)-0

-1

-2
6

-3

'-/

>::;

-1

-~
>-c
r"\

-3

r"\
'-../

>-c

\.../

>-<
-~
'-"

>-c

- '-"
~- -

-5
-7

-4

--1

-- -- -6
- - -

-5

---3

---5

~-6
>-c

~-7

ODD
FIELD

EVEN
FlELO
NORMAL SYNC
MODE 1

,....

---7
DOD
FIELD

EVEN
FIELD
INTERLACE SYNC AND VIDEO
MODE 3

INTERLACE SYNC
MODE 2

Figure 4. Cursor Control

MODE
1
2
3
4

II
~

I'+-

CURSOR DISPLAY MDDE
Non-Blink
Cursor Non-Display
Blink, 1/16 Field Ra1e
Blink, 1/32 Field Ra1e

OFF

BLINK PERIOD =
160R 3211MES
FIELD PERIOD

6
7

CURSOR START ADR, = 9
CURSOR END ADR. = 9

Memory Start Address Register (R12/R13) - These two
software programmable, write-only registers taken
together contain the memory address of the first
character displayed on the screen. RegisterR12 contains the upper six bits ofthe fourteen refresh memory
address bits, while R13 contains the lower eight bits.
The Linear Address Generator begins counting from
the address in R12/R13. By changing the starting ad.
dress, the display can be scrolled up or down through
the 16K memory block by character, line or page. If the

CURSOR START ADR, = 9
CURSOR END ADR. = 10

CURSOR START ADR. = 1
CURSOR END ADR. = 5

value in R12/R13 is near the end of the 16K block the
display will wrap around to the front.
Cursor Address Register (R14/R1S) - These two software programmable, write-only registers, taken together, contain the address in memory of the cursor
character. Register R14 contains the upper six bits and
register R15 contains the lower eight bits of the character. Cursor position is associated with an address in
memory rather than with a position on the screen. This
7.111

S68045/S68A045/S68B045

Figure 5. Implementation of a Reversed Video Cursor

RAM

S68045

t--------,
RAO·RA4

CURSOR

~_ _ _ _ _ _ _ _ _ _---..ID-TOVIOEO

way cursor position is not lost when the display is
scrolled.
Address Register - The five bit address register is
unique in that it does not store any CRT-related information, but is used as the address storage register in
an indirect access of the other registers. When the
Register Select pin (RS) is low, the address register is
accessed by 00-04. When RS is high, the register
whose address is in the address register is accessed.
eRTC Internal Description

There are four counters which determine what the
CRTC's output will be (see Block Diagram):
1)
2)
3)
4)

Horizontal Counter
Vertical Counter
Row Address Counter
Linear Address Counter

The first two counters, and to some extent the third,
take care of the physical operation of the monitor. The
Linear Address Counter, on the other hand, is responsible for the data that is displayed on the screen.
Surrounding these counters are the registers RO-R15.
Coincidence logic continuously compares the contents of each counter with the contents of the
register(s) associated with it. When a match is found,
appropriate action is taken; the counter is reset to a fixed ordynamic value, or a flag (such as VSYNC) is set, or
both.

Two sets of registers - The start Address Register
(R12/R13) and the Cursor Position Register
(R14/R15) are programmable via the Data lines
(00-07). The other registers are all mask programmed.
There are two ROM programs available on each chip.
Selection of which ROM program will be accessed is
performed by the PROG pin.
Horizontal Counter

The Horizontal Counter produces four output flags:
HSYNC, Horizontal Display Enable, Horizontal Reset to
the Linear Address Counter, and the horizontal clock.
The Horizontal Counter is driven by the character rate
clock, which was derived from the dot rate clock (see
Table 1). Immediately after the valid display area is
entered the Horizontal Counter is reset to zero but continues incrementing.
HSYNC is the only one of the four signals which is fed
to an external device (the CRT). The Horizontal Counter
is compared to registers RO, R2 and R3 to give an
HSYNC of the desired frequency (RO), pOSition (R2) and
width (R3). (See Figure 2a.)
Horizontal Display Enable is an internal flag which,
when ANOed with Vertical DE, is output at the Display
Enable pin. The Horizontal Counter determines the proper frequency (RO), and width (R1).
The Horizontal Reset and the horizontal clock are actually identical signals: the only difference is the way
they are used. Both are pulsed once for each scan line,

7.112

S68045/S68A045/S68B045
Table 1. Comparison of all CRTC Clocks

LOCATION
OF CLOCK

NAME

CONTROLLING
REGISTER
EXTERNAL

DIVIDED BY:

PRODUCES
CHARACTER
RATE CLOCK

DOT RATE
CLOCK

EXTERNAL

TOTAL WIDTH OF A CHARACTER
BLOCK IN DOTS

CHARACTER
RATE CLOCK

EXTERNAL
INPUT

TOTAL NUMBER OF
CHARACTERS IN A ROW

HORIZONTAL
CLOCK

INTERNAL

ROW ADDRESS
CLOCK

INTERNAL

TOTAL NUMBER OF SCAN LINES
IN A CHARACTER ROW
TOTAL NUMBER OF CHARACTER
ROWS PER SCREEN

ROW ADDRESS
CLOCK
VERTICAL
CLOCK

R4, RS

Table 2. CRTC Internal Register Assignment
REGISTER FILE

HORIZONTAL TOTAL

BITS
4

HORIZONTAL DISPLAYED

Nhd

HORIZONTAL SYNC POSITION

Nhsp -1

HORIZONTAL SYNC WIDTH

VERTICAL TOTAL

VERTICAL TOTAL ADJUST

VERTICAL DISPLAYED

VERTICAL SYNC POSITION

INTERLACE MODE

MAX SCAN LINE ADDRESS

R1a

CURSOR START

R11

CURSOR END

Nvsw

>< ><
><
><
>< I
><
><
~
><
><
~
CURSOR SKEW

Nhsw

Nadl
Nvd
Nvsp -1

J>s:J

DIS. ENAB. SKEW

INTERLACE

N,1*
CURSOR START

CURSOR BLINK

CURSOR END

R12

START ADDRESS (H)
START ADDRESS (L)

START ADDRESS (L)

R14

CURSOR (H)

R15

CURSOR (L)

START ADDRESS (H)

* For Interlace Sync and Video operation, R9 should contain Nr -1
BIT 6

NO SKEW

1
1

RESULT

BIT 5

BIT 4

1 CHARACTER SKEW

a
a

2 CHARACTER SKEW

ILLEGAL

INTERLACE CONTROL
BIT 1

NOT USED

IIISPLA Y ENABLE SKEW

CURSOR SKEW

BIT 0

Nvt -1

R13

BIT 7

Nhr1

RESULT
NO SKEW

1 CHARACTER SKEW

2 CHARACTER SKEW

ILLEGAL

CURSOR CONTROL
MODE

MODE

BIT 6

BIT 5

NON-INTERLACE

NON-BLINK

NON-INTERLACE

NON-BLINK

INTERLACE SYNC

BLINK @ 1/16 FIELD PERIOD

INTERLACE SYNC & VIDEO

BLINK @ 1/32 FIELD PERIOD

7.113

•

S68045/S68A045/S68B045

Figure 6. Bus Write Timing
14-------IcycE---.:..----.l

ENABLE

RS. "CI

DATA BUS

so their frequency is equal to the character rate clock
frequency divided by the entire horizontal period
(display, non-display and retrace) expressed in
character times (which is stored in RO). The hori;zontal
clock drives the Vertical and Row address Counters.
The horizontal reset is discussed with the Linear Address Counter.

Row Address Counter

The Row Address Counter produces three sets of output: the five Row Address lines (RAO-RA4), the Row Address Cursor Enable flag and the Row Address Reset
flag. The Row Address Counter is driven by the horizontal clock. Immediately after a full character row has
been completed by the Row Address Counter is reset
to zero but continues incrementing. Note that the Row
Address Counter actually counts scan lines, which are
different from character rows. A full character row consists of however many scan lines are in register R9.
The Row Address Lines, RAO-RA4, are the only data
lines from the Row Address Counter that are fed to an
external device (the character generator ROM). The
Row Address lines just carry the count that is currently
in the Row Address Counter. The counter is reset whenever the count equals the contents of the Maximum
Scan Line Register (R9.)
Row Address Cursor Enable is a flag going to the Cursor output AND gate. The Row Address Cursor Enable
flag goes high whenever the count in the Row Address
Counter is greater than or equal to the Cursor Start
Register (R10) but less than or equal to the Cursor End
Register (R11). The other input to the Cursor output
AND gate goes high whenever the address in the Linear
Address Counter is equal to the address in the Cursor
Position Register (R14/R15).
Row Address Reset is pulsed whenever the Row Ad-

Vertical Counter

The Vertical Counter produces three output flags:
VSYNC, Vertical Display Enable, and Vertical Reset to
the Linear Address Counter. The Vertical Counter is
driven by the horizontal clock. Immediately after vertical retrace the Vertical Counter is reset to zero but
continues incrementing.
VSYNC is the only one of the three signals which is fed
to an external device (the CRT). The Vertical Counter is
compared to registers R3, R4, R5 and R7 to give a
VSYNC of the desired frequency (R4, R5), position (R7)
and width (R3). (See Figure 2b.)
Vertical Display Enable is an internal flag which, when
ANDed with Horizontal DE, is output at the Display
Enable pin. The Vertical Counter determines the proper
frequency (R4, R5) and width (R6).
Vertical Reset is pulsed once for each screen. The frequency of Vertical Reset is equal to the horizontal clock
frequency divided by the total number of scan lines in a
screen (which is equal to (R4 x R9) +R5). It will be
discussed with the Linear Address Counter.
7.114

S68045/S68A045/S68B045

Figure 7. Bus Timing Character

MAO-MA13

I
dress Counter is reset. It will be discussed with the
Linear Address Counter.
Linear Address Counter

The Linear Address Counter (LAC) produces only one
set of outputs: The Refresh Memory Address lines
(MAO·MA13). These fourteen bits are fed externally to
the Refresh RAM and internally to the Cursor Position
coincidence circuit. The LAC is driven by the character
rate clock and continuously increments during the
display, non·display and retrace portions of the screen.
It contains an internal read/write register which stores
the memory address of the first displayed character in
the current row.
When any of the three Reset flags already mentioned
(Horizontal, Row Address and Vertical) is pulsed, the
value in the internal register is loaded into the counter.
7.115

If the reset is a Horizontal Reset the value in the internal
register is not modified before the load. If the reset is a
Row Address Reset, the value in the internal "first
character" register is first increased by the number of
characters displayed on a single character row (register
R1). The new contents of the internal register are then
loaded into the Linear Address Counter.
If the reset is a Vertical Reset, the value in Start Ad·
dress Register. (R12/R13) is first loaded into the internal
register, and then into the Linear Address Counter.
The fourteen output lines allow 16K of memory to be
accessed. By incrementing or decrementing the
number in the Start Address Register, the screen can
be scrolled forward or backward through Display
Refresh RAM on a character, line, or page basis.

S68045/S68A045/S68B045

Figure 8. Refresh Memory Addressing (MAO-MA13) State Chart

HORIZONTAL DISPLAY

HORIZONTAL RETRACE (NON-IISPLA y)

CHARACTER

11 r
N~

",II

.. Ii

I
I
I

•
•

Nhd-1

Nhd

I
I
I

•

Nhl

I
I
I

Nhd-1

Nhd

•

Nhi

Nhd+1

2xNhd-1

2xNhd

I
I
I

•

Nhd+NhI

I
I
I

Nhd

I
I
I
Nhd

Nhd+1

2xNhd

2xNhd+1

I
I
I

2xNhd

2xNhd+1

(Nvd-1)xNhd

(Nvd-1)X Nhd+ 1

I
I
I

(Nvd- 1)xNhd

(Nvd-1)x Nhd+ 1

NvdXNhd

NvdXNhd+1

I
I
I

NvdXNhd

NvdXNhd+1

NvlXNhd

I
I
I

•

2xNhd-1

2xNhd

3xNhd-1

3xNhd

I
I
I

3xNhd

I I

NvdXNhd-1

I
I
I

NvdXNhd

I
I
I

NvdXNhd-1

NvdXNhd

(Nvd+1)xNhd-1

(Nvd+1)xNhd

I
I
I

•

Nhd+Nhl

•

2Nhd+NhI

•

2Nhd+NhI

..
..

I
I
I

(Nvd

1)X Nhd+Nhl

I
I
I

(Nvd-1)x Nhd+ Nhi
NvdXNhd+NhI

I
I
I

(Nvd+1)xNhd-1

(Nvd+1)xNhd

NvlXNhd+1

(NvI+ 1)x Nhd-1

(NvI+1) xNhd

I
I
I

NvlX Nhd+ Nhl

I
I
I

NvdXNhd+NhI

s:-

;;;to

l!l

··1 i
N~

~.,

Nadl
-1

NvlxNhd

NvlXNhd+1

(NvI+l)xNhd-1

(NvI+1)xNhd

NvlxNhd+NhI

(NvI+l) xNhd

(NvI+ 1)x Nhd+ 1

(NvI+2)xNhd-1

(NvI+2)xNhd

(NvI+ 1)Nhd+ Nhi

I
I

(NvI+1)xNhd

(NvI+ 1)x Nhd+ 1

(NvI+2)xNhd-1

(NvI+2)X Nhd

(NvI+1)Nhd+NhI

NOTE 1: TltE HTlAL MA IS OETERMI4EO BY TltE CONTENTS
OF START AIlllll'ESS REGISTER, R121R13. lIMING IS
SIIOWN FOR R121R13 ~ O. ONLY NON-INTERFACE AND
INTERFACE SYNC MODES ARE SHOWN.

7.116

S68045/S68A045/S68B045

Figure 9. CRTC Horizontal Timing

I--_.--_ _ _ Horizontal DiSPlaY _ _ _ _ _~-+-I
Tc

NhdXTc

------------------11

___________

1 - - - - - - - - - - - - - - - - - - - - - - T s l - (Nht + 1) x Tc

Horlzontal Retrece

Clk~~~~~~

MAO-MA13'

Character #

:Nhd- 1 : Nhd:

)

:x::::x::::x::: ::x:::::x=x:::: ±±

:NhIP-1:NhSP:

:Nhd-1: Nhd :

:Nh,p-1: NhIP:

: I

I
I
I
:
: Nht :
::X::::::::X=:=I
I
I

: Nht :

I
I

I---Nhsw x Tc-----!

HSVNC :

~I---------------------------------4--------------------~11~---------------4:

tl============~N~h~d~X~T~c==============~__________________________________________________j
Oi,pen i-

'Timing is shown for first displayed scan row only.
See Chart in Figure 16 for other rows. The initial
MA is determined by the contents of Start Address
Register, R12/R13. Timing.is shown for R12/R13 = O.

Figure 10. CRTC Vertical Timing

AELD TIME

i:::::====
Tf = (Nvl + 1) x Trc + Nadi x Tsl
~
~ Vertical Display Nvd x Trc ~
i-- --i
Vertical Relrac;
~Y~~~~:CEt=::::x:::1rc~~~~~~~

RAO-RA4
( )

VIDEO MODE
ODD FiElD

I 0 (1) I
I
I
I
I

MAO.MA13"OC

I Nsl

I (Nsl
I

I
- 1):
I

~ ~::xi::::;

'f'1' . -~- -ti'
10

~~~~ACTER \
VSYNC

Nhl'

I
I

I0
I

Nhl'l
I

I 0 (1) I

- 1) x Nhd
I

~L....Ih

!:,
I

+ Nhl I
I

I
I

:::

I
I

I Nvd . 1 I

Nvsp . 1

L-....·
,....JL.L J

I
I

~r-~
I 0 (1)
I
I
I
I
AODRESS CONTINUES TO INCREMENT ""

I 0, 1
(Nsl ·1) I
I

1)1

Nsl
0 (1l-Tadi = Nadi x Tsl~
(Nsl· 1) r'
AElD ADJUST TIME I
I
I
I

-vt--< ~ :::xi'1')%AW~/W/M///~;WflWZZ?foW!l!!/A

I :

DISPLAY
ENABLE

I (Nsf·

,~
(Nvd.- 1) x Nh,d

(NON·INTERLACE) I :
I
I

I Nsf

(N~d
d{

\
I

Nvsp

'
:

: :
Nvl

I
I

:
Nvl

/--16 x TSI----l
II
I

:
I

I
I
L.. .......11----________________________________________________
I
---'

, Nhl . Ihere musl be an even number of character times for both interlace modes.
" Initial MA is delermined by R12/R13 (Slart Address Regisler), which is zero
in this timing example.
" . Nht must be an even number of scan lines for Interlace Sync and Video Mode.

7.117

S68045/S68A045/S68B045

Figure 11. Cursor Timing
RAO·RA4'

~----------------------~--------------------~----------------____~K

I
I
I

MAO·MA13"

CHARACTER ROW "

CHARACTER"

~,r---v
~I
14
Nhd
'Nhd + 1 Nhd + 2 I
Nhd +
I

I "

Nht

I
I

Nhl

-L--L------L----'-_---7----i: ;f---L---'

: :I-~_L------L_--+-_----<-"";;;I-

I
,
I
I

CURSOR

Nhd

~
I
~~~
I Nhd + 1 I Nhd + 2 I
, Nhd +
Nhd I Nhd + 1 I Nhd + 2 I
I Nhd + I

Nhl

----------~~~--------------------~~~'------------------~~~I__________
• Timing is shown lor non·inlerlace and intenace sync modes.
Example shown has cursor programmed as:
Cursor Register = Nhd + 2
Cursor Start
1
Cursor End
=3

" The innial MA is determined by the contents 01 Start
Address Register, R12/R13. TIming is shown for
R12/R13
O.

7.118

AIMI.======
r
."""4.

A Subsidiary
of Gould Inc.

S6846

ROM-I/O-TIMER

Features
o 2048 x 8-Bit Bytes of Mask-Programmable ROM
o 8-Bit Bidirectional Data Port for Parallel Interface
Two Control Lines
o Programmable Interval Timer-Counter Functions
o Programmable 110 Peripheral Data, Control and
Direction Registers
o Compatible With the Complete S6800 Microcomputer Product Family
D TIL-Compatible Data and Peripheral Lines
o Single 5 Volt Power Supply

General Description
The S6846 combination chip provides the means, in
conjunction with the S6802, to develop a basic 2-chip
microcomputer system. The S6846 consists of 2048
bytes of mask-programmable ROM, an 8-bit bidirectional data port with control lines, and a 16-bit programmable timer-counter.
This device is capable of interfacing with the S6802
(basic S6800, clock and 128 bytes of RAM) as well as
the S6800 if desired. No external logic is-required to interface with most peripheral devices.

Block Diagram

Pin Configuration

R/W

40
RESET

39
38

01
03
04
05

36
35
34
33

CSO'
CS1*

A6
A7
AS
A9
A10

CP1i
CP2

PPO
PP1
PP2
PP3
PP5
PP6
PP7

7.119

•

56846
General Description (Continued)
The 86846 combination chip may be partitioned into
three functional operating sections: read-only memory,
timer-counter functions, and a parallel 1/0 port.
Read-Only Memory (ROM)
The mask-programmable ROM section is similar to
other AMI ROM products. The ROM is organized in a
2048 by 8-bit array to provide read-only storage for a
minimum microcomputer system. Two mask-programmable chip selects are available for user definition.
Address inputs Ao-A10 allow any of the 2048 bytes of
ROM to be uniquely addressed. Internal registers associated with the 1/0 functions may be selected with Ao,
A1 and A2• Bidirectional data lines (°0-07) allow the
transfer of data between the M PU and the 86846.
Timer-Counter Functions
Under software control this 16-bit binary counter may
be programmed to count events, measure frequencies
and time intervals, or similar tasks. It may also be used
for square wave generation, single pulses of controlled
duration, and gated delayed signals. Interrupts may be
generated from a number of conditions selectable by
software programming.

The timer-counter control register allows control of the
interrupt enables, output enables, and selection of an
internal or external clock source. Input pin CTC
(counter-timer clock) will accept an asynchronous
pulse to be used as a clock to decrement the internal
register for the counter-timer. If the divide-by-8
prescaler is used, the maximum clock rate can be four
times the master clock frequency with a maximum of
4MHz. Gate input (CTG) accepts an asynchronous TILcompatible signal which may be used as a trigger or
gating function to the counter-timer. A counter-timer
output (CTO) is also available and is under software
control via selected bits in the timer-counter control
register. This mode of operation is dependent on the
control register, the gate input, and the cloc.k source.
Parallel 1/0 Port
The parallel bidirectional 1/0 port has functional operational characteristics similar to the B port on the 86821
PIA. This includes 8 bidirectional data lines and two
handshake control signals. The control and operation
of these lines are completely software programmable.
The interrupt input (CP1) will set the interrupt flags of
the peripheral control register. The peripheral control
(CP2) may be programmed to act as an interrupt input
(set C8R2) or as a peripheral control output.

Figure 1_ Typical Microcomputer
Vec

eOUNTERI {
TIMER 110

S6846
ROM, liD, TIMER

Vcc

Vee

~--I--+-...-.IiRli

L...--...-.IMR
eso . . ...!::VM:::;:.A_ _ _---l VMA
S6802
MPU
128 BYTE
RAM
DO-07 CLOCK

RtW
PARAllEL 110

RE
NMI
SA
XTAL

Figure lis a block diagram of a typical cost effective microcomputer.
The MPU is the center of the microcomputer system and is shown in a
minimum system interfacing with a ROM combination chip. It is not
intended that this system be limited to this function but that it be
expandable with other parts in the 86800 Microcomputer family.

AO-AI5

SYSTEM EXPANSION
IF REQUIRED

7.120

XTAL

86846
Absolute Maximum Ratings
Supply Voltage ............................................................ - 0.3Vdc to + 7.0Vdc
Input Voltage .............................................................. - 0.3Vdc to + 7.0Vdc
Operating Temperature Range ..................................................... O°C to + 70°C
Storage Temperature Range ................................................... - 55°C to + 150°C
Thermal Resistance eJA
Ceramic ............................................................................ 50°C/W
Plastic ............................................................................ 100°C/W
Cerdip .............................................................................. 60°C/W
This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to
avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an
appropriate logic voltage level (e.g., either Vss or Vee)'

Power Considerations
The average chip-junction temperature, TJ, in °C can be
obtained from:
(1)
TJ = TA + (Po °eJA)
Where:
!A = Ambient Temperature, °C
eJA = Package Thermal Resistance,
Junction-to-Ambient, °C/W
Po = PINT + PPORT
PINT = Icc x Vee, Watts-Chip Internal Power
PPORT = Port Power Dissipation,
Watts- User Determined

An approximate relationship between Po and TJ (if
PPORT is neglected) is:
Po = K + (TJ + 273°C)
(2)
Solving equations 1 and 2 for K gives
K = POe(TA + 273°C) + eJA ePD2

Where K is a constant pertaining to the particular part,
K can be determined from equation 3 by measuring Po
(at equilibrium) for a known TA. Using this value of K the
values of Po and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA.

For most applications PPORT-PINT and can be
neglected. PPORT may become significant if the device
is configured to drive Darlington bases or sink LED
loads.
Electrical Characteristics: (Vee
Symbol

= 5.0V

± 5%, Vss

Parameter

=0, TA = O°C to

+ 70°C unless otherwise noted.)
Max.

Unit

Input High Voltage

All Inputs

Vss + 2.0

Vcc

Vdc

VIL

Input Low Voltage

All Inputs

Vss - 0.3

Vss + 0.8

Vdc

Vos

Clock Overshoot/Undershoot - Input High Level
- Input Low Level

Vee - 0.5
Vss - 0.5

Vee + 0.5
Vss + 0.5

Vdc

liN

Input Leakage Current

1.0

2.5

/JAde

ITS!

Three-State (Off State) Input Current

2.0

/JAdc

VIH

Min.

R/W, Reset, CS o, CS l
CP 1 , CTG, CTC, E, Ao-All
°0-°7

Typ.

PPO-PP 7 , CR 2
VOH

Output High Voltage
Other Outputs

VOL

Conditions

VIN = 0 to 5.25 Vdc

VIN 0.4 to 2.4Vdc

Vdc
°0-°7

Vss + 2.4
Vss + 2.4

ILOAD = - 205/JAdc,
ILOAD = - 100/JAdc

Output Low Voltage

Vdc
Vss + 0.4
Vss + 0.4

°0-°7

Other Outputs

7.121

(3)

ILOAD = 1.6mAdc
ILOAD = 3.2mAdc

86846
Electrical Characteristics: (Vee = 5.0V
Symbol
10H

IOL

5%, Vss = 0, TA = O°C to + 70°C unless otherwise noted.)

Parameter

Min.

Typ.

Max.

Output High Current (Sourcing)

Unit

00-0 7
Other Outputs
CP 2 , PP O-PP 7

- 205
- 200
-1.0

00-0 7
Other Outputs

1.6
3.2

VOH = 2.4Vdc
-10

Output Low Current (Sinking)

mADC

Vo = 1.5Vdc, the current lor
driving other than TTL, e.g.,
Darlington Base

mAdc

IRQ

ILOH

Output Leakage Current (Off State)

PINT

Internal Power Dissipation (measured at TA = O°C)

CIN

Capacitance

00-0 7

VOL = O.4Vdc
10

/AAdc

1000

PP O-PP 7 , CP 2
Ao-A l0 , R/W, Reset, CS o, CS 1 , CP 1 , CTC, CTG
IRQ

12.5
10
7.5

PP o-PP 7 ' CP 2 , CTO

5.0
10

1.0

MHz

1.6

/As
/As
/As

COUT

Conditions

/AAdc

Frequency 01 Operation

0.1

t CYCE
tRL
tlR

Clock Timing
Cycle Time
Reset Low Time
Interrupt Release

1.0
2

7.122

VOH = 2.4Vdc
VIN = 0, TA = 25°C,
1= 1.0MHz

AMI.---------."11f4.

A Subsidiary
of Gould Inc.

S6850/S68A50/S68B50

ASYNCHRONOUS COMMUNICATION
INTERFACE ADAPTER (ACIA)

Features
o 8-Bit Bi-directional Data Bus for Communication
with MPU
o False Start Bit Deletion

o
o

Peripheral/Modem Control Functions

One or Two Stop Bit Operation

Eight and Nine-Bit Transmission With Optional
Even and Odd Parity

Parity, Overrun and Framing Error Checking

Double Buffered Receiver and Transmitter

Programmable Control Register

o
o

Optional -;.. 1, -;.. 16, and -;.. 64 Clock Modes
Up to 500,000 bps Transmission

Block Diagram

Functional Description
The S6850 Asynchronous Communications Interface
Adapter (ACIA) provides the data formatting and control to interface serial asynchronous data communications to bus organized systems such as the S6800
Microprocessing Unit.
The S6850 includes select enable, read/write, interrupt
and bus interface logic to allow data transfer over an
8-bit bi-directional data bus. The parallel data of the
bus system is serially transmitted and received by the
asynchronous data interface, with proper formatting
and error checking. The functional configuration of the
ACIA is programmed via the data bus during system
initialization. Word lengths, clock division ratios and
transmit control through the Request to Send output
may be programmed. For modem operation three control lines are provided. These lines allow the ACIA to
interface directly with the S6860 0-600 bps digital
modem.
Pin Configuration

ClX I')
-+------------------~

1--_ _ _-+-ISfrxo

GNO

eTS

RXO

oeD

eRX

eTX

RTS

TXO

IRQ

eso

eS2

es,

Vee

+-__________________-{

CRXI'-'..')

Vcc=PIH 12
GROUHO=PIH 1

7.123

RIW

•

S6850/S68A50/S68B50
Absolute Maximum Ratings *
Supply Voltage ........................................................................................................................................ - O.3V to + 7.0V
Operating Temperature Range .................................................................................................................. O°C to + 70°C
Input Voltage ........................................................................................................................................... - O.3V to + 7.0V
Storage Temperature Range ............................................................................................................... - 55°C to + 150°C
• NOTE: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal
precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high·impedance circuit.

DC (Static) Characteristics: (Vee 5.0V ± 5%, TA 25°C, unless otherwise noted.)
Symbol
Min.
Characteristic
VIHT
Input High Threshold Voltage
+2.0
Input Low Threshold Voltage
VILT
Input Leakage Current
liN
(VIN = 0 to 5.0 Vdc)
R/W, RS, GSo, GS 1, CS'2, Enable
Three-State (Off State) Input Current
ITSI
(V IN = 0.4 to 2.4 Vdc, Vee = max) Do, 07
Output High Voltage
+2.4
VOH
(I LOAD = 100/-lAdc,
Enable Pulse Width 25/-ls)
All Outputs Except IRQ
Output Low Voltage
VOL
(I LOAD = 1.6mAdc)
Enable Pulse Width 25/-ls
Output Leakage Current (Off State)
rFm
ILO H
PD
Power Dissipation
Input CapaCitance
GIN
(VIN = 0, TA = 25°C, f = 1.0MHz)
00 - 07
R/W, RS, CS o, CS 1, CS 2, RXD, CTD, DCD, GTX, CRX
Enable
Output Capacitance
CO UT
(VIN = 0, TA = 25°G, f = 1.0MHz)

'CYC E

----__+1
~

PW EL

Max.

-...-

2.0V

O.sv
DATA BUS

7.124

Unit
Vdc
Vdc

1.0

+0.8
2.5

/-lAdc

2.0

/-lAdc

Vdc

+0.4

Vdc

1.0
300

10
525

/-lAdc
mW
pF

10
7.0
7.0
10

12.5
7.5
7.5
pF

Figure 2. Bus Read Timing Characteristics

Figure 1. Enable Signal Characteristics

1------

Typ.

S6850/S68A50/S68B50
AC (Dynamic) Characteristics
Loading = 130pF and one TIL load for Do-Dr = 20pF and 1 TTL load for RTS and TXD = 100pF and 3KQ to Vee for IRQ.
86850

868A50

868850

Symbol

Parameter

Min.

tCYC(E)
PW EH

Enable Cycle Time
Enable Pulse Width, High

PW EL

Enable Pulse Width, Low

1000
450
430

tH , tEf

Enable Pulse Rise and Fall Times

tAS

Setup Time, Address and R/W Valid to Enable
Positive Transition

160

140

tAH

Address Hold Time

tOOR

Data Delay Time, Read

tOHR

Data Hold Time, Read

tosw

Data Setup Time, Write

tOHW

Data Hold Time, Write

Max.

Min.

Max.

666
280
280
25

Min.

Max.

500
220
210

ns
ns
ns

320
10
195
10

ns
ns
ns

220

180
10
60
10

10
80
10

Units

ns
ns
ns
ns

Transmit/Receive Characteristics
Symbol

Characteristic

Min.

Typ.

Max.

Unit

500
800
800

KHz
KHz
KHz

fc
+ 1 mode
+ 16 mode
+64 mode
PW CL

Clock Pulse Width, Low State

600

PW CH

Clock Pulse Width, High State

600

troD

Delay Time, Transmit Clock to Data Out

tROSU

Set Up Time, Receive Data

500
500

nsec
nsec
1.0

JAsec
nsec

tROH

Hold Time, Receive Data

tlRQ

Delay Time, Enable to IRQ Reset

1.2

JAsec

tRTS

Delay Time, Enable to RTS

1.0

JAsec

Figure 3. Bus Write Timing Characteristics

nsec

Figure 4. Bus Timing Test Loads

2.0V

5.0V

O.BV
RL =2.5k

RS,

2.0V

RNi

O.BV

TEST POINT

cs,

O-r-~---1 ~~~~~I~
MMD7000
OR EQUIV.

2.0V
O.BV
C= 130pF FOR 00.0,
=30pF FOR RTS AND TX DATA

7.125

R= 11. 7kQ FOR 00.0,
=24kQ FOR RTS AND TX DATA

•

S6850/S68A50/S68B50

Figure 5. Transmit/Receive Timing
TRANSMIT CLOCK
(CTX)
RECEIVE CLOCK
(CRX)

PWCH

TRANSMIT CLOCK
(CTX)

----

_----2.4V

L-.4V

TTD)5D_

TRANSMIT DATA
(TXD)

2.4V

20V

____ _ ...J

RECEIVE CLOCK
(CRX)

RECEIVE DATA
(RXD)

0 BV

A20V

~lx
~DH

" \ 2.0V
0 BV

____

0.4V

2 4V
.

04V
_ _ _ _ _ 24V

- - - - - 04V

ENABLE
(E)

REOUEST TO SEND
(ATS)

~------ 0.4V

1-_ _ _ _
(iliii)

2.4V

2.0

INTERRUPT REQUEST

_______-+-__...J - - - - - 0.4V

MPU/ACIA Interface
Pin
Label
Function
(22)
ACIA Bi-directional Data Lines- The bi-directional data lines (00-07) allow for data transfer beDo
(21)
01
tween the ACIA and the MPU. The data bus output drivers are three-state devices that remain
(20)
in the high-impedance (off) state except when the MPU performs an ACIA read operation. The
O2
ReadlWrite line is in the read (high) state when the ACIA is selected for a read operation.
(19)
03
(18)
(17)
(16)
(15)

04
05
06
07

(14)

(13)

RIW

ACIA Enable Signal-The Enable signal (E) is a high impedance TTL compatible input that
enables the bus input/output data buffers and clocks data to and from the ACIA. This signal
will normally be a derivative of the 86800 02 clock.
Read/Write Control Signal- The Read/Write line is a high impedance input that is TTL compatible and is used to control the direction of data flow through the ACIA's input/output data bus
interface. When ReadlWrite is high (MPU Read cycle), the ACIA output driver is turned on and a
selected register is read. When it is low, the ACIA output driver is turned off and the MPU
writes into a selected register. Thus, the ReadlWrite signal is used to select the Read Only or
Write Only registers within the ACIA.
7.126

S6850/S68A50/S68850
MPU/ACIA Interface (Continued)
Pin
(8)
(10)
(9)

(11)

Label
CSa

CS2
RS

Function
Chip Select Signals- These three high impedance TIL compatible input lines are used to address an ACIA. A particular ACIA is selected when CSa and CS1 are high and CS2 is low.
Transfers of data to and from ACIA are then performed under the control of Enable,
Read/Write, and Register Select.
Register Select Signal- The Register Select line is a high impedance input that is TIL compatible and is used to select the Transmit/Receive Data or Control/Status registers in the ACIA.
The ReadlWrite signal line is used in conjunction with Register Select to select the Read Only
or Write Only register in each register pair.
Interrupt Request Signal-Interrupt request is a TIL compatible, open drain active low output
that is used to interrupt the MPU. The Interrupt Request remains low as long as the cause of
the interrupt is present and the appropriate interrupt enable within the ACIA is set.

(7)

ACIA/Modem or Peripheral Interface
Pin

Label

Function

(4)

CTX

Transmit Clock- The Transmit Clock is a high impedance TIL compatible input used for the
clocking of transmitted data. The transmitter initiates data on the negative transition of the
clock. Clock frequency of 1, 16, or 64 times the data rate may be selected.

(3)

CRX

Receive Clock- The Receive Clock is a high impedance TTL compatible input used for synchronization of received data. (In the -;- 1 mode, the clock and data must be synchronized
externally.) The receiver strobes the data on the positive transition of the clock. Clock frequency of 1, 16, or 64 times the data rate may be selected.

(2)

RXD

Received Data- The Received Data line is a high impedance TIL compatible input through
which data is received in a serial NRX (Non Return to Zero) format. Synchronization with a
clock for detection of data is accomplished internally when clock rates of 16 or 64 times the bit
rate are used. Data rates are in the range of 0 to 500Kbps when external synchronization is
utilized.

(6)

TXD

Transmit Data- The Transmit Data output line transfers serial NRZ data to a modem or other
peripheral device. Data rates are in the range of 0 to 500Kbps when external synchronization is
utilized.
Clear-to-Send- This high impedance TIL compatible input provides automatic control of the
transmitting end of a communications link via the modem's "clear-to-send"active low output
by inhibiting the Transmitter Data Register Empty status bit (TDRE).

RTS

Request-to-Send- The Request-to-Send output enables the MPU to control a peripheral or
modem via the data bus. The active state is low. The Request-to-Send output is controlled by
the contents of the ACIA control. register.

(24)

(5)

Data Carrier Detected- This high impedance TIL compatible input provides automatic control
of the receiving end of a communications link by means of the modem "Data-Carrier-Detect"
or "Received-line-Signal Detect" output. The DCD input inhibits and initializes the receiver
section of the ACIA when high. A low to high transition of the Data Carrier Detect initiates an
interrupt to the MPU to indicate the occurrence of a loss of carrier when the Receiver Interrupt
Enable (RIE) is set.

(23)

(12)

Vee

+5 volts ±5%

(1)

GND

Ground

7.127

•

S6850/S68A50/S68B50
Application Information
Internal Registers- The ACIA has four internal registers utilized for status, control, receiving data, and transmitting
data. The register addressing by the R/W and RS lines and the bit definitions for each register are shown in Table 1.
Table 1. Definition of ACIA Registers

DATA BUS
LINE
NUMBER

Notes::*

BUFFER ADDRESS
RS-R/W
RS·R7W
RECEIVER
CONTROL
DATE
REGISTER
REGISTER
(WRITE ONLY)
(READ ONLY)
CLK. DIVIDE
DATA BIT 0*
SEL. (CRO)
CLK. DIVIDE
DATA BIT 1
SEL. (CR1)
WORD SEL. 1
DATA BIT 2
(CR2)
WORD SEL. 2
DATA BIT 3
(CR3)
WORD SH. 3
DATA BIT 4
(CR4)
TX CONTROL 1
DATA BIT 5
(CR5)
TX CONTROL 2
DATA BIT 6
(CR6)
RX INTERRUPT
DATA BIT 7**
ENABLE (CR7)

RS·R7W
TRANSMIT
DATA
REGISTER
(WRITE ONLY)

DATA BIT 0*

DATA BIT 1

DATA BIT 2

DATA BIT 3

DATA BIT 4

DATA BIT 5

DATA BIT 6

DATA BIT 7***

RS·R/W
STATUS
REGISTER
(READ ONLY)
RX DATA REG.
FULL (RDRF)
TX DATA REG.
EMPTY (TORE)
DATA CARRIER
DET. LOSS (DCD)
CLEAR-TO-SEND
(CTS)
FRAMING ERROR
(FE)
OVERRUN (OVRN)
PARITY ERROR (PE)
INTERRUPT REQUEST
(IRQ)

Leading bit = LSD = Bit a
Unused data bits in received character will be "a's."

*** Unused data bits for transmission are "don't care's."

ACIA Status Register-Information on the status of the
ACIA is available to the MPU by reading the ACIA
Status Register. This Read Only register is selected
when RS is low and R/W is high. Information stored in
this register indicates the status of: transmitting data
register, the receiving data register and error status and
the modem status inputs of the ACIA.

been transferred and that new data may be entered. The
low state indicates that the register is full and that
transmission of a new character has not begun since
the last write data command.

Receiver Data Register Full (RDRF) [Bit OJ-Receiver Data
Register Full indicates that received data has been
transferred to the Receiver Data Register. RDRF is
cleared after an M PU read of the Receiver Data Register
or by a Master Reset. The cleared or empty state indicates that the contents of the Receiver Data Register
are not current. Data Carrier Detect being high also
causes RDRF to indicate empty.

Data Carrier Detect (DCD) [Bit 2]-The Data Carrier Detect
bit will be high when the DCD input from a modem has
gone high to indicate that a carrier is not present. This
bit going high causes an Interrupt. Request to be
generated if the Receiver Interrupt Enable (RIE) is set. It
remains high until the interrupt is cleared by reading
the Status Register and the Data Register or a Master
Reset occurs. If the DCD input remains high after Read
Status and Read Data or Master Reset have occurred,
the DCD Status bit remains high and will follow the
DCD input.

Transmit Data Register Empty (TORE) [Bit 1]-The
Transmit Data Register Empty bit being set high indicates that the Transmit Data Register contents have

Clear--to-Send (CTS) [Bit 3]-The Clear-to-Send bit indicates the state of the Clear-to-Send input from a
modem. A low CTS indicates that there is a Clear-to-

7.128

S6850/S68A50/S68B50
Send from the modem. In the high state, the Transmit
Data Register Empty bit is inhibited and the Clear-toSend status bit will be high. Master Reset does not
affect the Clear-to-Send status bit.
Framing Error (FE) [Bit 4]-Framing error indicates that
the received character is improperly framed by the start
and stop bit and is detected by the absence of the first
stop bit. This error indicates a synchronization error,
faulty transmission, or a break condition. The framing
error flag is set or reset during the receiver data transfer
time. Therefore, this error indicator is present
throughout the time that the associated character is
available.
Receiver Overrun (OVRN) [Bit 51-Overrun is an error flag
that indicates that one or more characters in the data
stream were lost. That is, a character or a number of
characters were received but not read from the
Receiver Data Register (RDR) prior to subsequent characters being received. The overrun condition begins at
the midpoint of the last bit of the second character
received in succession without a read of the RDR having occurred. The Overrun does not occur in the Status
Register until the valid character prior to Overrun has
been read. The RDRF bit remains set until Overrun is
reset. Character synchronization is maintained during
the Overrun condition. The overrun indication is reset
after the reading of data from the Receive Data
Register. Overrun is also reset by the Master Reset.
Parity Error (PE) [Bit 6]-The parity error flag indicates
that the number of highs (ones) in the character does
not agree with the preselected odd or even parity. Odd
parity is defined to be when the total number of ones is
odd. The parity error indication will be present as long
as the data character is in the RDA. If no parity is
selected, then both the transmitter parity generator output and the receiver parity check results are inhibited.
Interrupt Request (IRQ) [Bit 7]-The IRQ bit indicates the
state of the IRQ output. Any interrupt that is set and
enabled will be indicated in the status register. Any
time the IRQ output is low the IRQ bit will be high to indicate the interrupt or service request status.
Control Register-The ACIA control Register consists
of eight bits of write only buffer that are selected when
RS and R/W are low. This register controls the function
of the receiver, transmitter, interrupt enables, and the
Request-to-Send modem control output.
Counter Divide Select Bits (CRO and CR1)-The Counter
Divide Select Bits (CRO and CR1) determine the divide
ratios utilized in both the transmitter and receiver sections of the ACIA. Additionally, these bits are used to
provide a Master Reset for the ACIA which clears the
Status Register and initializes both the receiver and

transmitter. Note that after a power-on or a power-fail
restart, these bits must be set High to reset the ACIA.
After resetting, the clock divide ratio may be selected.
These counter select bits provide for the following
clock divide ratios:
Function
CR1
CRO

o
o
1
1

1
0
1

+ 16

+64
Master Reset

Word Select Bits (CR2, CR3, and CR4)- The Word Select
bits are used to select word length, parity, and the
number of stop bits. The encoding format is as follows:
CR4
CR3
CR2 Function
o
0
0
7 Bits + Even Parity + 2 Stop Bits
o
0
1
7 Bits + Odd Parity + 2 Stop Bits
o
1
0
7 Bits + Even Parity + 1 Stop Bit
o
1
1
7 Bits + Odd Parity + 1 Stop Bit
1
0
0
8 Bits + 2 Stop Bits
1
0
1
8 Bits + 1 Stop Bit
1
1
0
8 Bits + Even Parity + 1 Stop Bit
1
1
1
8 Bits + Odd Parity + 1 Stop Bit
Word length, Parity Select, and Stop Bit changes are
not double-buffered and therefore become effective
immediately.
Transmitter Control Bits (CR5 and CR6)-Two Transmitter Control bits provide for the control of the Transmitter Buffer Empty interrupt output, the Request-toSend output and the transmission of a BREAK level
(space). The following encoding format is used:
CR6
CR5 Function
o
0
RTS = low, Transmitting Interrupt Disabled
o
1
RTS = low, Transmitting Interrupt Enabled
1
0
RTS = high, Transmitting Interrupt Disabled
1
1
RTS = low, Transmitting Interrupt Disabled
and Transmits a BREAK level on the Transmit
Data Output
Receiver Interrupt Enable Bit (RIE) (CR7)-lnterrupt will
be enabled by a high level in bit position 7 of the Control
Register (CR7). Interrupts caused by the Receiver Data
Register Full being high or by a low to high transition on
the Data Carrier Detect signal line are enabled or disabled by the Receiver Interrupt Enable Bit.
Transmit Data Register (TDR)-Data is written in the
Transmit Data Register during the peripheral enable
time (E) when the ACIA has been addressed and
RS.R/W is selected. Writing data into the register
causes the Transmit Data Register Empty bit in the
status register to go low. Data can then be transmitted.
If the transmitter is idling and no character is being
transmitted, then the transfer will take place within one
7.129

•

S6850/S68A50/S68B50
bit time of the trailing edge of the Write command. If a
character is being transmitted,the new data character
will commence as soon as the previous character is
complete. The transfer of data causes the Transmit
Data Register Empty (TOR) bit to indicate empty.
Receive Data Register (RDR)-Data is automatically
transferred to the empty Receive Data Register (RDR)
from the receiver deserializer (a shift register) upon
receiving a complete character. This event causes the
Receive Data Register Full bit (RDRF) (in the status buffer) to go high (full). Data may then be read through the
bus by addressing the ACIA and selecting the Receive
Data Register with RS and R/W high when the ACIA is
enabled. The non-destructive read cycle causes the
RDRF bit to be cleared to empty although the data is retained in the RDA. The status is maintained by RDRF as
to whether or not the data is current. When the Receive
Data Register is full, the automatic transfer of data from
the Receiver Shift Register to the Data Register is inhibited and the RDR contents remain valid with its current status stored in the Status Register.

Operational Description
From the MPU Bus interface the ACIA appears as two
addressable RAM memory locations. Internally, there
are four registers; two read-only and two write-only
registers. The read-only registers are status and receive
data, and the write only registers are control and
transmit data. The serial interface consists of serial
transmit and receive lines and three modem! peripheral
control lines.
During a power-on sequence, the ACIA is internally latched in a reset condition to prevent erroneous output
transitions. This power-on reset latch can only be
released by the master reset function via the control
register; bits be> and b1 are set "high" for a master reset.
After master resetting the ACIA, the programmable
control register can be set for a number of options such
as variable clock divider ratios, variable word length,
one or two stop bits, parity (even, odd, or none) and etc.
Transmitter-A typical transmitting sequence consists
of reading the ACIA status register either as a result of
an interrupt or in the ACIA's turn in a polling sequence.

7.130

A character may be written into the Transmitter Data
Register if the status read operation has indicated that
the Transmit Data Register is empty. This character is
transferred to a shift register where it is serialized and
transmitted from the Tx Data output preceded by a start
bit and followed by one or two stop bits. Internal parity
(odd or even) can be optionally added to the character
and will occur between the last data bit and the first
stop bit. After the first character is written in the data
register, the status register can be read again to check
for a Transmit Data Register Empty condition and current peripheral status. If the register is empty, another
character can be loaded for transmission even though
the first character is in the process of being transmitted. This second character will be automatically
transferred into the shift register when the first
character transmission is completed. The above sequence continues until all the characters have been
transmitted.
Receiver-Data is received from a peripheral by means
of the Rx Data input. A divide by one clock ratio is provided for an externally synchronized clock (to its data)
while the divide by 16 and 64 ratios are provided for internal synchronization.
Bit synchronization in the divide by 16 and 64 modes is
obtained by the detection of the leading mark-to-space
transition of the start bit. False start bit deletion capability insures that a full half bit of a start bit has been
received before the internal clock is synchronized to
the bit time. As a character is being received, parity
(odd or even) will be checked and the error indication
will be available in the status register along with framing error, overrun error, and receiver data register full. In
a typical receiving sequence, the status register is read
to determine if a character has been received from a
peripheral. If the receiver data register is full, the
character is placed on the 8-bit ACIA bus when a Read
Data command is received from the MPU. The status
register can be read again to determine if another character is available in the receiver data register. The
receiver is also double buffered so that a character can
be read from the data register as another character is
being received in the shift register. The above
sequence continues until all characters have been
received.

AMI.-------------."""'4.

A Subsidiary
of Gould Inc.

S6852/S68A52/S68B52

SYNCHRONOUS SERIAL
DATA ADAPTER (SSDA)

General Description
The S6852 Synchronous Serial Data Adapter provides a
bi-directional serial interface for synchronous data information interchange. It contains interface logic for
simultaneously transmitting and receiving standard
synchronous communications characters in bus
organized systems such as the S6800 Microprocessor
systems.

Features
o Programmable Interrupts From Transmitter,
Receiver, and Error Detection Logic
o Character Synchronization on One or Two Sync
Codes
o External Synchronization Available for ParallelSerial Operation
o Programmable Sync Code Register
o Up to 600k bps Transmission
o Peripheral/Modem Control Functions
o Three Bytes of FIFO Buffering on Both Transmit
and Receive
o Seven, Eight, or Nine Bit Transmission
o Optional Even and Odd Parity
o Parity, Overrun, and Underflow Status
o Clock Rates:
1.0MHz
1.5MHz
2.0MHz

The bus interface of the S6852 includes select, enable,
read/write, interrupt, and bus interface logic to allow
data transfer over an 8-bit bi-directional data bus. The
parallel data of the bus sytem is serially transmitted
and received by the synchronous data interface with
synchronization, fill character insertion/deletion, and
error checking. The functional configuration of the
SSDA is programmed via the data bus during system
initialization. Programmable control registers provide
control for variable word lengths, transmit control,
Pin Configuration

Block Diagram

ADDRESS/CONTROL
AND INTERRUPT

PERIPHERAL/
MODEM
CONTROL

RECEIVE
DATA
DATA BUS
I/O
TRANSMIT
DATA

7.131

S6852/S68A52/S68B52
General Description (Continued)
Typical applications include floppy disk controllers,
cassette or cartridge tape controllers, data communications terminals, and numerical control systems.

receive control, synchronization control, and interrupt
control. Status, timing and control lines provide peripheral or modem control.

Absolute Maximum Ratings:
Supply Voltage ................................................................... - 0.3 to + 7.0V
Input Voltage .................................................................... - 0.3 to + 7.0V
Operating Temperature Range .......................................................
to + 70 0
Storage Temperature Range ...................................................... - 55° to + 150 0
Thermal Resistance ................................................................... + 70 0 eIW

ooe

e
e

Note: This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be
taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit.

Electrical Characteristics (Vee
Symbol

=5.0V ± 5%, Vss =0, TA =ooe to 70 e unless otherwise noted.)
0

Characteristics

Typ.

Min.

Unit

Max.

Vss + 2.0

VIH

Input High Voltage

VIL

Input Low Voltage

liN

Input Leakage Current
(VIN = 0 to 5.25Vdc)

ITSI

Three State (Off State) Input Current
(VIN = 0.4 to 2.4Vdc, Vee = 5.25Vdc)

VOH

Output High Voltage
ILOAD = - 205~dc, Enable Pulse Width<25/-1s
ILOAD = -1 OO~dc, Enable Pulse Width<25/-1s

Vdc

Tx Clk, Rx Clk, Rx Data, Enable
Reset, RS, R/W, CS, DCD, CTS
0 0-0 7

VOL

Output Low Voltage
ILOAD = 1.6mAdc, Enable Pulse Width<25/-1s

ILOH

Output Leakage Current (Off State)
VOH = 2.4Vdc

Power DiSSipation

CIN

Input Capacitance
(VIN = 0, TA == 25°C, f = 1.0MHz)

COUT

Output CapaCitance
(VIN = 0, TA = 25°C, f = 1.0MHz)

Vss + 0.8

Vdc

1.0

2.5

~dc

2.0

~dc

Vss + 2.4
Vss + 2.4

00-0 7

Tx Data, DTR, TUF

Vdc
Vdc

IRQ

Vss + 0.4

Vdc

1.0

~dc

300

525

12.5
7.5

10
5.0

00-0 7

All Other Inputs
Tx Data, SM/DTR, TUF

TRQ

Electrical Characteristics (Vee = 5.0V ± 5%, TA = 0 to 70 0 e unless otherwise noted.)
S6852

S68852

S68A52

Symbol

Characteristic

Min.

PW CL

Minimum Clock Pulse Width, Low

700

400

280

PW CH

Minimum Clock Pulse Width, High

700

400

280

Clock Frequency

t RDSU

Receive Data Setup Time

Max.

Min.

600
350

* 10/Js or 10% of the pulse width, whichever is smaller.
7.132

Max.

Min.

160

Unit
ns
ns

1500

1000
200

Max.

kHz
ns

S6852/S68A52/S68B52
Electrical Characteristics (Continued) (Vee = 5.0V

± 5%,

TA = 0 to 70°C unless otherwise noted.)

S6852
Symbol
t ROH

Characteristic
Receive Data Hold Time

Min.

Max.

350

S68A52
Min.
Max.

S68852
Min.
Max.

200

160

Unit
ns

tSM

Sync Match Delay Time

1.0

0.666

0.500

/As

tTOO

Clock-to-Data Delay for Transmitter

1.0

0.666

0.500

/As

t TUF

Transmitter Underflow

1.0

0.666

0.500

/AS

tOTR

DTR Delay Time

1.0

0.666

0.500

/As

1.2

0.800

0.600

/As

tlR

Interrupt Request Release Time

t Res

Reset Minimum Pulse Width

1.0

0.666

0.500

/AS

t eTs

CTS Setup Time

200

150

120

toeD

DCD Setup Time

500

350

250

t r , tf

Input Rise and Fall Times (except
Enable) (O.BV to 2.0V)

1.0

/AS

Bus Timing Characteristics
Symbol

Characteristic

Unit

Read
t eYeE

Enable Cycle Time

1.0

PW EH

Enable Pulse Width, High

0.45

PW EL

Enable Pulse Width, Low

0.43

0.28

0.21

/AS

t AS

Setup Time, Address and R/W
Valid to Enable Positive Transition

160

140

tOOR

Data Delay Time

0.666
25

0.28

320

0.5
25

0.22

220

/As
25

180

/As

Data Hold Time

tAH

Address Hold Time

tH ,

Rise and Fall Time for Enable Input

tEf

Write

t CVCE

Enable Cycle Time

1.0

PW EH

Enable Pulse Width, High

0.45

PW EL

Enable Pulse Width, Low

0.43

0.28

0.21

/As

t AS

Setup Time, Address and R/W
Valid to Enable Positive Transition

160

140

tosw

Setup Time

195

Data Hold Time

tAH

Address Hold Time

t Er ,
t Er

Rise and Fall Time for Enable Input

0.666
25

7.133

0.28

0.5
25

0.22

/AS
25

/As

•

AMI.---------r

."""'(.

A Subsidiary
of Gould Inc.

S6854/S68A54/S68B54

ADVANCED DATA
LINK CONTROLLER

D Quad Data Buffers for Each Rx and Tx
D Prioritized Status Register (Optional)

Features
D S6800 Compatible
D Protocol Features
o Automatic Flag Detection and Synchronization
D Zero Insertion and Deletion
o Extendable Address, Control and Logical
Control Fields (Optional)
o Variable Word Length Info Field - 5, 6, 7, or
a-bits
o Automatic Frame Check Sequence Generation
and Check
o Abort Detection and Transmission
o Idle Detection and Transmission
D Loop Mode Operation
D Loop Back Self-Test Mode
D NRZlNRZI Modes

D MODEM/DMA/Loop Interface

General Description
The S6854 ADLC performs the complex MPU/data
communication link function for the "Advanced Data
Communication Control Procedure" (ADCCP), High
Level Data Link Control (HOLC) and Synchronous Data
Link Control (SDLC) standards. The ADLC provides key
interface requirements with improved software efficiency. The AOLC is designed to provide the data communications interface for both primary and secondary
stations in stand-alone, polling, and loop configurations.
Pin Configuration

Block Diagram

~DcD
RxC

27_iiCii
26

FLAG
DETECT

TxO

iRli

OATA
BUS
OO·OJ

mEi'---

cs-

t .
r---~~--I-~===+~==~~~
L-"'T"""___r---r--.,..Jr----.-

WsP ON·L1NE CONTROL/OTR

VssPIN 1
Vee PIN 14

7.134

_ill

Vss

ill

86854

LOOP ON· LINE
CONTROLliii'R

FLAG OET

TOSR

ROSR

7 868A54 22 _ 0 0
8 868854 21 _ 0 1

ZO-OZ

RS o- l 0

19_03

RS,-11

18-04

R/w--- 12

17-05

E_13

16_06

15-07

Vee

S6854/S68A54/S68B54
Absolute Maximum Ratings*
Supply Voltage .................................................................. - 0.3 to + 7.0V
Input Voltage ................................................................... - 0.3 to + 7.0V
Operating Temperature Range ....................................................... 0° to + 70°C
Storage Temperature Range ..................................................... - 55° to + 150°C
Thermal Resistance ................................................................... 70° C/W
" This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken
to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

Electrical Characteristics: (Vee
Symbol

= 5.0V

± 5%, Vss

Parameter

= 0, TA = O°C to
Min.

VIH
Vil

Input High Voltage
Input Low Voltage

liN

Input Leakage Current

ITSI

Three-State (Off State) Input Current

VOH

Output High Voltage

VOL

Output Low Voltage

IlOH
PD

Output Leakage Current (Off State)

CIN

Capacitance

Typ.

1.0

00-0 7
00-0 7
All Others

2.0

Vss +0.8,
2.5
10

IRQ

1.0

00-0 7
All Other Inputs
IRQ
All Others

Characteristic

Min.

Conditions

Vdc
VIN = 0 to 5.25 Vdc
VIN = 0.4 to 2.4 Vdc
Vcc = 5.25 Vdc

JAAdc
JAAdc
Vdc
Vdc

Vss + 0.4

Vdc

ILOAD = - 205JAAdc
IlOAD = - 100JAAdc
IlOAD = 1.6mAdc

JAAdc

VOH = 2.4Vdc

850

12.5
7.5

pF
pF

5.0
10

pF
pF

VIN = 0, TA = 25°C,
f=1.0MHz

S68A54

S6854
Symbol

Unit

Vss + 2.4
Vss + 2.4

Power Dissipation

COUT

Max.
Vdc

Vss + 2.0

All Inputs Except 00-0 7

+ 70°C unless otherwise noted.)

Max.

Min.

S68854
Max.

Min.

Max.

Unit

PW Cl
PW CH

Minimum Clock Pulse Width, Low

700

450

280

Minimum Clock Pulse Width, High

700

450

280

Clock Frequency

t RDSU

Receive Data Setup Time

250

200

120

tRDH

Receive Data Hold Time

120

100

tATS

Request-to-Send Delay Time

680

460

340

fTOD

Clock-to-Data Delay for Transmitter

460

320

250

tFO

Flag Detect Delay Time

680

460

340

tDTR

DTR Delay Time

680

460

340

tloc

Loop On-Line Control Delay Time

680

460

340

t RDSR

RDSR Delay Time

540

400

340

t TDSR

TOSR Delay Time

540

400

340

tlR

Interrupt Request Release Time

1.2

0.9

0.7

JAs

tRES

Reset Minimum Pulse Width

t r , tf

Input Rise and Fall Times (except
Enable) (0.8V to 2.0V)

0.66

1.0

" 1.0JAs or 10% of the pulse width, whichever IS smaller.

7.135

1.0·

MHz
ns
ns

0.40

0.65
1.0·

1.5

1.0

JAs

1.0·

JAs

•

S6854/S68A54/S68B54
Bus Timing Characteristics (Vee

= + 5.0V

± 5%, Vss

=0, TA =O°C to +

+ 70°C unless otherwise noted.)
S68A54

S6854
Symbol

Characteristic

Min.

Max.

Min.

S68854

Max.

Min.

Max.

Unit

Read
tCYC

Enable Cycle Time

1.0

0.666

0.50

PW EH

Enable Pulse Width, High

0.45

0.28

0.22

PW EL

Enable Pulse Width, Low

0.43

0.28

0.21

/As

t AS

Setup Time, Address and R/W
Valid to Enable Positive Transition

160

140

tOOA

Data Delay Time

Data Hold Time

tAH

Address Hold Time

t Er ,
tEl

Rise and Fall Time lor Enable Input

220

320

180

/As

Write
t CYCE

Enable Cycle Time

1.0

0.666

0.50

/As

PW EH

Enable Pulse Width, High

0.45

0.28

0.22

/As

PW EL

Enable Pulse Width, Low

0.43

0.28

0.21

/As

t AS

Setup Time, Address and R/W
Valid to Enable Positive Transition

160

140

tosw

Setup Time

195

Data Hold Time

tAH

Address Hold Time

t Er ,
tEl

Rise and Fall Time lor Enable Input

7.136

AMI.---------r

......

A Subsidiary

of Gould Inc.

S681 O/S68A10/S6881 0

128x8 STATIC
READ/WRITE MEMORY

Features

General Description

o
o
o

The S6810/S68A10 and S68810 are static 128x8
ReadlWrite Memories designed and organized to be
compatible with the S6800/S68AOO and S68BOO Microprocessors. Interfacing to the S6810/S68A 10 and
S68B10 consists of an 8-bit bidirectional data bus,
seven address lines, s single ReadlWrite control line
and six chip enable lines, four negative and two
positive.

Organized as 128 Bytes of 8 Bits
Static Operation
Bidirectional Three-State Data Input/Output

D Six Chip Enable Inputs (Four Active Low, Two
Active High

Single 5 Volt Power Supply

D TTL Compatible

For ease of use, the S6810/S68A10 and S68810 are a
totally static memory requiring no clocks or cell
refresh. The S6810/S68A 10 and 868810 are fabricated
with N-Channel silicon gate depletion load technology
to be fully DTLlTTL compatible with only a single + 5
volt power supply required.

Maximum Access Time
450ns for S6810
360ns for S68A10
250ns for S68B10

Block Diagram

Pin Configuration

12100
AD(23)

13101

Al (22)

14102

A21211
A31201

11103
01

ADDRESS
DECODE

16104

A4(19)

Ii) 01

AlllB)

IBID6

A6(17)

191D}

READ/ 1161
WRITE
EJ113)

1101
1111
1141
1121
1111

111 1241
GNO Vee I'IVI

7.137

•

S681 O/S68A10/S6881 0
Absolute Maximum Ratings

+ 7.0V
+ 7.0V
Operating Temperature Range ................................................................................................................ O°C to + 70°C
Storage Temperature Range ........................................................................................................... - 55°C to + 150°C
Supply Voltage ..................................................................................................................................... - 0.3V to
Input Voltage ........................................................................................................................................ - 0.3V to

D.C. Characteristics:
(Vee

= + 5.0V

Symbol

± 5%, Vss

= 0, TA = O°C to + 70°C unless otherwise noted.)

Parameter

Min.

Typ.

Max.

Units

Conditions

2.5

~Adc

VIN = OV to 5.25V

liN

Input Current
(An, R/W, CS n, CS n)

VOH

Output High Voltage

VOL

Output Low Voltage

0.4

Vdc

ILo

Output Leakage Current

~Adc

CS = 0.8V or CS = 2.0V, (Three State)
VOUT = 0.4V to 2.4V

Icc

Supply Current S6810
S68A10/S68B10

80
100

mAdc
mAdc

Vcc = 5. 25V, all other pins
grounded, TA = OOC

Vdc

2.4

IOH = - 205~A
IOL = 1.0mA

A.C. Characteristics:
Read Cycle

(Vee

= + 5.0V

± 5%, Vss = 0, TA = O°C to + 70°C unless otherwise noted.)
S6810

S68A10

S68810

Symbol

Parameter

Min.

tCYC(R)

Read Cycle Time

450

tacc

Access Time

tAS

Address Setup Time

tAH

Address Hold Time

tooR

Data Delay Time (Read)

tRCS

Read to Select
Delay Time

tOHA

Data Hold from Address

Output Hold Time

tOHR

Data Hold from Read

tRH

Read Hold
from Chip Select

Max.

Min.

Max.

10
0

7.138

180

220

230

Units

ns
250

360

450

Max.

250

360

Min.

ns
ns

S681 0/S68A 10/S6881 0
Write Cycle

+ 5.0V ± 5%, Vss = O,TA = O°C to + 70°C unless otherwise noted.)

(Vee =

86810
Symbol

Parameter

Min.

868A10
Max.

Min.

868B10

Max.

Min.

Max.

Units

tcyC(W)

Write Cycle Time

450

360

250

tAS

Address Setup Time

tAH

Address Hold Time

tcs

Chip Select Pulse Width

twcs

Write to Chip Select
Delay Time

tDSW

Data Setup Time (Write)

Input Hold Time

tWH

Write Hold Time from
Chip Select

300

250

210

190
10

Read Cycle Timing

tCYC(RI
tacc
ADDRESS

tAS
O.8V

2.0V

O.8V

tAH

_DDN'TCARE
RIW

.OV

NOTE CS AND CS CAN BE ENABLED FOR CONSECUTIVE READ
CYCLES PROVIDED R W REMAINS AT V,H
DATA OUT

Write Cycle Timing
tCYC(WI
ADDRESS

'AH

ICS
2.0V
CS

IT
O.BV

~DON'TCARE

R/W

O.8V

~'DSW

NOTE: CS AND ;;SCAN BE ENABLED FOR CONSECUTIVE WRITE
CYCLES PROVIDED RIW IS STROBED TO V ,H BEFORE OR

~;avoATA IN STABLE

DATA IN

COINCIDENT WITH THE ADDRESS CHANGE, AND
REMAINS HIGH FOR TIME lAS'

"DON'TCARE

7.139

!ill

S681 O/S68A1 O/S68B1 0
AC Test Load

TEST POI NT O-......- . - i C l l - -..

~M~~G~~

130 pF*
MMD7000
OR EaUIV

"Includes Jig Capacitance

7.140

sao Family

•

sao Family Selection Guide
S83

Operating System Processor (OSP)

AIMII.---------r

.....

A Subsidiary
of Gould Inc.

883

Preliminary Data Sheet

OPERATING SYSTEM
PROCESSOR (OSP)

Features
o ZaoTM CPU Internal Architecture
o zao Instruction Set
DOn-board aK Byte ROM
o Internal/External ROM Modes
D Address, Data, and Bus Control Signals Function
Identically to the Original zao
o Dynamic RAM Interface Including Address
Multiplexing and Rowand Column Address Strobe
Signals.

trol, address, and data signals are functionally identical
to the standard zao, making it completely hardware
compatible with all zao peripheral chips. All zao instructions are present including the aoao subset, providing software compatibility as well.
Additional logic has been incorporated to allow the OS
Processor to be directly connected to 64K Dynamic
RAMs.
ROM select logic is incorporated to allow the internal
ROM to be selectively enabled or disabled under software control.

Functional Description
The OS Processor chip is a single-chip microcomputer
system with a core zao CPU and on-chip aK x a (64K
bit) ROM. This chip possesses all of the hardware
capabilities present in the standard zao chip. All con-

The OS Processor is fabricated in a NMOS process,
uses a single 5 volt power supply, and will be packaged
in a 4a-pin DIP package.

Pin Configuration

Block Diagram

CAS

EXT/OS,

RAS
RESERVED
RESERVED

ROM
SELECT
LOGIC

Z80
CPU

8Kx8
ROM

ADDRESS, DATA, & CONTROL

DYNAMIC RAM
CONTROL LOGIC

BUS CONTROL
LOGIC

CONTROL

Z80 is a registered trademark of Zilog, Inc.

a.3

•

AIMII.-------------."""'4.
~

A Subsidiary
of Gould Inc.

883
to control the addressing of external memory that
resides in the same address space as the internal ROM.
Its use will be covered later under "Prototyping With
the S83".

ROM Select Logic
This functional block controls access to the internal
ROM and also determines whether the processor will
be brought up in an internal or external mode.
When the RESET signal goes high and EXT/OS is high,
the ROM enable latch is disabled, thereby turning off
the internal ROM, and the processor begins execution
at address OOOOH just as a standard Z80 CPU would
after reset. This is referred to as EXTERNAL MODE. In
the external mode, the processor behaves identically to
a standard Z80 CPU, except that the upper 16 memory
addresses, FFFOH to FFFFH, are reserved. Address
FFFFH is used for ROM control. The other 15 locations
have been reserved for further expansion of system
control functions.

Dynamic RAM Interface
In addition to the refresh circuitry inherent to the Z80
CPU, the S83 features circuitry that enables the 8 high
order address bits to be multiplexed onto the low order
8 address lines for row and column addressing of 64K
dynamic RAMs. Row address and column address
strobes are also generated by the S83.
Bus Selection: For each memory cycle, the user may
determine whether or not the addresses will be multiplexed by use of the BUSSEL (BUS SELect) input.
BUS'SE[ is sampled slightly after the rising edge of
each T2 clock state. If aUssEL is low, the memory
access is a standard Z80 access with non-multiplexed
addresses, and CAS is not generated, however RAS is
generated. If BUSSEL is high, the multiplexing process
and generation of CAS is allowed to continue. A short
time after RAS goes low, the low byte of the address
bus will begin changing over to reflect the upper 8 bits
of the address the Z80 has generated. After the new
address (the column address) is stable, CAS goes low.
These two strobes clock the row and column addresses into the dynamic RAMs.

When the RESET signal goes high and the mode pin
EXT/OS is low, the internal ROM is switched on by
enabling the ROM enable latch, and the processor is
forced to execute NOP instructions until it reaches
address FFOOH in the internal ROM, where it begins
execution. Any internal bootstrap program code should
start at address FFOOH. This is referred to as INTERNAL MODE.
In the internal mode, the 8K x 8 internal ROM is switched on and is effectively overlayed on top of external
memory. This ROM occupies the upper 8K bytes of the
full64K byteZ80 address space. When data is read from
the internal ROM, this data appears on the external data
bus. Data written to this address space does appear on
the external data bus, however, and will be written to
any RAM that occupies that space. This RAM data cannot be read by the processor until the internal ROM has
been turned off. The internal ROM may be switched on
or off by writing a zero to bit 0 of memory address
FFFFH. The ROM may be switched back on at any time
by writing a one to bit 0 of memory address FFFFH.

Because only the upper 8 bits of the address bus
remain stable throughout the entire memory access,
selection of BUSSEL should be done with the upper 8
address lines only unless some form of address latching is used. If it is desired to use any of the lower 8
address lines (Ao-A7), they must be latched on the failing edge of MREQ, otherwise false decoding may occur
when the address lines are multiplexed.
BUSSEL is qualified with MREQ internally, so it is not
necessary to include MREQ in decoding for BUSSEL,
and the RAS/CAS logic and 'BUSSEL sampling circuitry
only operates during memory accesses. It is inoperative for 110 and interrupt cycles.

Memory locations FFFOH through FFFFH are reserved.
No code should be written in this area. Any accesses to
these sixteen addresses will be treated as external
memory accesses.
While the EXT/OS pin serves as an input on reset to set
the initial operating mode of the processor, it serves a
different purpose during normal operation. After reset,
the EXT/OS pin becomes an output, and reflects the
state of the internal OS signal. This signal indicates
that a memory read is being made to the internal ROM
address space (addresses EOOOH - FFEFH) and that
the internal ROM enable latch is set. This Signal is used

BUSSEL is also used to selectively block accesses to
the internal ROM, and this usage will be discussed
under "Prototyping With the S83".
Wait States: Because of the tighter access times
required by the Z80 CPU during an opcode fetch (Ml cycle), the S83 automatically inserts a wait state on M1
cycles if the user has selected a multiplexed memory

8.4

583
- FFFFH (not substituting for the internal ROM), its
address decoding should include EXT/OS = HIGH.
This will ensure that when an external EPROM is chip
selected and BUSSEL pulled low to select nonmultiplexed addresses, the user is not inadvertantly
decoding an internal ROM access. The inclusion of the
EXT/OS signal in chip decoding provides the
distinguishing factor between internal and external
memory spaces.

cycle with the BUSSEL input. This wait state is not added if a standard non-multiplexed bus cycle has been
selected.
The user may insert additional wait states if desired,
however care must be exercised not to hold the processor in a wait state so long that refresh requirements are
violated, as the S83, like the l80, does not generate any
refresh signals while in a wait state.
Also, during an M1 cycle, if the user adds additional
wait states beyond the one the processor has inserted,
RAS will go high on the third rising clock edge after
MREQ goes low, regardless of whether or not clock
state T3 has been reached yet. This does not violate
dynamic RAM timing constraints, as CAS will always
go high before RAS is generated again.

General CPU Operation
The core of the S83 is a l80 CPU. It contains 208 bits of
read/write memory that are accessible to the programmer. These registers include two sets of six generalpurpose registers which may be used individually as
either 8-bit registers or as 16-bit register pairs. In addition there are two sets of accumulator and flag
registers. A group of "Exchange" instructions makes
either set of main or alternate registers accessible to
the programmer. The alternate set allows operation in
foreground-background mode or it may be reserved for
very fast interrupt response. The l80 also contains a
Stack Pointer, Program Counter, two index registers, a
Refresh register (counter), and an Interrupt register.

Bus Request (DMA) Cycles: When the l80 is bus requested and an external device gains control of the
bus, the address multiplexers do not function. The RAS
and CAS logic, however, does continue to function. If
an external DMA device generates a MREQ signal, RAS
will be generated. Depending on the state of BUSSEL,
CAS mayor may not be generated. This feature allows a
DMA device to refresh dynamic RAMs while it performs
its DMA task.

Figure 1 shows three groups of registers within the l80
CPU. The first group consists of duplicate sets of 8-bit
registers: a principal set and an alternate set (designated by , [prime], e.g., A'). Both sets consist of the
Accumulator Register, the Flag Register, and six
general-purpose registers. Transfer of data between
these duplicate sets of registers is accomplished by
use of "Exchange" instructions. The result is faster
response to interrupts and easy, efficient implementation of such versatile programming techniques as
background-foreground data processing. The second
set of registers consists of six registers with assigned
functions. These are the I (Interrupt Register), the R
(Refresh Register), the IX and IY (Index Registers), the
SP (Stack Pointer), and the PC (Program Counter). The
third group consists of two interrupt status flip-flops,
plus an additional pair of flip-flops which assists in
identifying the interrupt mode at any particular time.
Table 1 provides further information on these registers.

Prototyping With the S83
While the main purpose of BUSSEL is to control the
dynamic RAM interface logic, it also controls access to
the internal ROM. If an access to the internal ROM is
attempted and BUSSEL is low, that access will be
blocked, and instead the processor will access the
external data bus using a non-multiplexed l80 address.
This input, together with the EXT/OS output, allows an
external EPROM to be substituted for the internal ROM
and still have its accesses controlled by the ROM
enable latch. This is accomplished by using the
EXT/OS output as the chip select for the EPROM, and
also feeding this signal into the BUSSEL input. Since
EXT/OS can only become low when the ROM enable
latch is on, the functionality of internal vs. external
memory spaces is still preserved. If it is desired to have
an external ROM or EPROM in the address range EOOOH

8.5

I
"-"

AIMII.---------."""4.
~

A Subsidiary
of Gould Inc.

S83
Figure 1. CPU Registers
MAIN REGISTER SET

ALTERNATE REGISTER SET

A ACCUMULATOR

F FLAG REGISTER

ACCUMULATOR

FLAG REGISTER

B GENERAL PURPOSE

C GENERAL PURPOSE

GENERAL PURPOSE

0 GENERAL PURPOSE

E GENERAL PURPOSE

GENERAL PURPOSE

H GENERAL PURPOSE

L GENERAL PURPOSE

GENERAL PURPOSE

INTERRUPT FLIP-FLOPS STATUS

IX INDEX REGISTER

IV INDEX REGISTER

INTERRUPTS DISABLED
INTERRUPTS ENABLED

STORES IFF1
DURING NMI
SERVICE

SP STACK POINTER
INTERRUPT MODE FLIp· FLOPS

PC PROGRAM COUNTER
I INTERRUPT VECTOR

R MEMORV REFRESH

IMFa

IMFb

o
o

o
1
o

1
1

INTERRUPT MODE 0
NOT USED
INTERRUPT MODE 1
INTERRUPT MODE 2

Table 1. zao CPU Registers
Register

Size (Bits)

Remarks

A, A'
F, F'
B, B'
C, C'
0,0'
E, E'
H, H'
L, L'

Accumulator
Flags
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose

8
8
8
8
8
8
8
8

Interrupt Register
Refresh Register

8
8

IX
IV
SP
PC
IFF1-IFF2
IMFa-IMFb

Index Register
Index Register
Stack Pointer
Program Counter
Interrupt Enable
Interrupt Mode

16
16
16
16
Flip-Flops
Flip-Flops

Stores an operand or the results of an operation.
See Instruction Set.
Can be used separately or as a 16-bit register with C.
See B, above.
Can be used separately or as a 16-bit register with E.
See D, above.
Can be used separately or as a 16-bit register with L.
See H, above.
Note: The (B, C), (0, E), and (H, L) sets are combined as follows:
B - High byte
C - Low byte
o - High byte
E '- Low byte
H - High byte
L - Low byte
Stores upper eight bits of memory address for vectored interrupt processing.
Provides user-transparent dynamic memory refresh. Lower seven bits are automatically incremented and all eight are placed on the address bus during each instruction fetch cycle
refresh time. The eighth bit appearing on the bus during a refresh cycle is incremented, but is
not readable or writable by the user.
Used for indexed addressing.
Same as IX, above.
Holds address of the top of the stack. See Push or Pop in instruction set.
Holds address of next instruction.
Set or reset to indicate interrupt status (see Figure 4).
Reflect Interrupt mode (see Figure 4).

8.6

883
Interrupts: General Operation
The CPU accepts two interrupt input signals: NMI and
INT. The NMI is a non-maskable interrupt and has the
highest priority. INT is a lower priority interrupt and it
requires that interrupts be enabled in software in order
to operate. INT can be connected to multiple peripheral
devices in a wired-OR configuration.

interrupting device places an instruction on the data
bus. This is normally a Restart (RST) instruction, which
will initiate a call to the selected one of eight restart
locations in page zero of memory. Unlike the 8080, the
Z80 CPU responds to the Call instruction with only one
interrupt acknowledge cycle followed by two memory
read cycles.

The Z80 has a single response mode for interrupt service for the non-maskable interrupt. The maskable
interrupt, INT, has three programmable response
modes avai lable. These are:

Mode 1 Interrupt Operation. Mode 1 operation is very
similar to that for the NMI. The prinCipal difference is
that the Mode 1 interrupt has a restart location of 0038H
only.

• Mode 0 - similar to the 8080 microprocessor.
• Mode 1 - Peripheral Interrupt service, for use with
non-8080/Z80 systems.
• Mode 2 - a vectored interrupt scheme, usuallydaisychained, for use with Z80 Family and compatible
peripheral devices.

Mode 2 Interrupt Operation_ This interrupt mode has
been designed to utilize most effectively the capabilities of the Z80 microprocessor and its associated
peripheral family. The interrupting peripheral device
selects the starting address of the interrupt service
routine. It does this by placing an 8-bit vector on the
data bus during the interrupt acknowledge cycle. The
CPU forms a pointer using this byte as the lower 8-bits
and the contents of the I register as the upper 8 bits.
This points to an entry in a table of addresses for interrupt service routines. The CPU then jumps to the routine at that address. This flexibility in selecting the
interrupt service routine address allows the peripheral
device to use several different types of sevice routines.
These routines may be located at any available location
in memory. Since the interrupting device supplies the
low-order byte of the 2-byte vector, bit 0 (Ao) should be a
zero.

The CPU services interrupts by sampling the NMI and
INT signals at the rising edge of the last clock of an instruction. Further interrupt service processing
depends upon the type of interrupt that was detected.
Details on interrupt responses are shown in the CPU
Timing Section.
Non-Maskable Interrupt (NMI). The non-maskable interrupt cannot be disabled by program control and therefore will be accepted at all times by the CPU. NMI is
usually reserved for servicing only the highest priority
type interrupts, such as that for orderly shutdown after
power failure has been detected. After recognition of
the NMI signal (providing BUSREO is not active), the
CPU jumps to restart .location 0066H. Normally, software starting at this address contains the interrupt service routine. NMI is negative edge triggered and need
not be low at the time interrupts are sampled (see Pin
Descri ptions).

Interrupt Priority (Daisy Chaining and Nested Interrupts).
The interrupt priority of each peripheral device is determined by its physical location within a daisy-chain configuration. Each device in the chain has an interrupt
enable input line (lEI) and an interrupt enable output
line (lEO), which is fed to the next lower priority device.
The first device in the daisy chain has its lEI input hardwired to a High level. The first device has highest priority, while each succeeding device has a corresponding
lower priority. This arrangement permits the CPU to
select the highest priority interrupt from several simUltaneously interrupting peripherals.

Maskable Interrupt (INT). Regardless of the interrupt
mode set by the user, the Z80 response to a maskable
interrupt input follows a common timing cycle. After
the interrupt has been detected by the CPU (provided
that interrupts are enabled and BUSREO is not active) a
special interrupt processing cycle begins. This is a
special fetch (M1) cycle in which IORO becomes active
rather than MREO, as in normal M1 cycle. In addition
this special M1 cycle is automatically extended by tw~
WAIT states, to allow for the time required to acknowledge the interrupt request.

The interrupting device disables the lEO line to the next
lower priority peripheral until it has been serviced. After
servicing, its lEO line is raised, allowing lower priority
peripherals to demand interrupt servicing.
The Z80 CPU will nest (queue) any pending interrupts or
interrupts received while a selected peripheral is being
serviced.

Mode 0 Interrupt Operation. This mode is similar to the
8080 microprocessor interrupt service procedures. The

8.7

•

AIMII.-------------."""4.
~

A Subsidiary
of Gould Inc.

S83
Interrupt Enable/Disable Operation. Two flip·flops, IFF1
and IFF2 , referred to in the register description are used
to signal the CPU interrupt status. Operation of the two
flip-flops is described in Table 2. For more details, refer
to the Z80 CPU Technical Manual and Z80 Assembly
Language Manual (available from Zilog, Inc.).

and shows the assembly language mnemonic, the
operation, the flag status, and gives comments on each
instruction. The Z80 CPU Technical Manual (03-0029-01)
and Assembly Language Programming Manual
(03-0002-01) contain significantly more details for programming use (available from Zilog, Inc.).

Table 2. State of Flip-Flops

The instructions are
categories.

Action

Comments

CPU Reset

01 instruction

EI instruction
execution
LO A, I instruction
execution
LO A, R instruction
execution
Accept NMI

following

8-bit loads
D 16-bit loads
D Exchange, block transfers, and searches
o 8-bit arithmetic and logic operations
o General-purpose arithmetic and CPU control
D 16-bit arithmetic operations
o Rotates and shifts
o Bit set, reset, and test operations
D Jumps
D Calls, returns, and restarts
o Input and output operations

Parity flag

IFF2 does not change
(Maskable interrupt
INT disabled)
IFF2 -+ IFF1 at
completion of an NMI
service routine.

RETN instruction
execution

into the

Maskable interrupt
INT disabled
Maskable interrupt
INT disabled
Maskable interrupt
INT enabled
IFF2 -+ Parity flag
IFF2

divided

A variety of addressing modes are implemented to permit efficient and fast data transfer between various
registers, memory locations, and input/output devices.
These addressing modes include:

Immediate
D Immediate extended
o Modified page zero
o Relative
D Extended
D Indexed
o Register
o Register indirect
D Implied
D Bit

Instruction Set
The Z80 microprocessor has one of the most powerful
and versatile instruction sets available in any 8·bit
microprocessor. It includes such unique operations as
a block move for fast, efficient data transfers within
memory or between memory and 110. It also allows
operations on any bit in any location in memory.
The following is a summary of the Z80 instruction set
a·Bit Load Group
Symbolic
Operation
r-r'
r-n

Mnemonic
LD r, r'
LD r, n
LD r, (HL)
LD r, (IX + d)
LD r, (IV

+ d)

LD (HL), r
LD (IX + d), r
LD (IV

+ d), r

Flags
H

+ d)

X
X

r - (HL)
r-(IX + d)
r-(IV

Opcode

PlY

76 543 210 Hex
r'
01
r
00 r' 110
-n01
r 110
11 011 101
01
r 101

X
X

1
2

No. of M No. of T
Cycles States

1
2

7
7
19

-d-

11
01

(HL) - r
(IX + d) - r

X
X

01
11
01

+ d)-r

11
01

(IV

No. of
Bytes

8.8

111 101 FD
r 110
-d110 r
011 101 DD
110 r
-d111 101 FD
110 r
-d-

7
19
19

Comments
r, r' Reg.
000
B
001
C
010
D
011
E
100
H
101
L
111
A

883
a-Bit Load Group (continued)

Flags
H
X

(IX + d) - n

11
00

LD(IV + d), n

(IV + d) - n

11
00

LD A, (Be)
LD A, (DE)
LD A, (nn)

A - (Be)
A - (DE)
A - (nn)

X
X
X

00
00
00

LD (Be), A
LD (DE), A
LD (nn), A

(Be) -A
(DE) -A
(nn) - A

X
X
X

00
00
00

LD A, I

A-I

IFF

LD A, R

A-R

IFF

LD I, A

I-A

LD R, A

R-A

Mnemonic
LD (HL), n

Symbolic
Operation
(HL) - n

LD(IX + d}, n

PlY

76
00

11
01
11
01
11
01
11
01

Opcode
543 210 Hex
110 110 36
-n011 101 DD
110 110 36
-d-n111 101 FD
110 110 36
-d-n001 010 OA
011 010 1A
111 010 3A
-n-n000 010 02
010 010 12
110 010 32
-n-n101 101 ED
010 111 57
101 101 ED
011 111 5F
101 101 ED
000 111 47
101 101 ED
001 111 4F

No. of
Bytes
2

Opcode
543 210 Hex
ddO 001
-n-n011 101 DD
100 001 21
-n-n111 101 FD
100 001 21
-n-n101 010 2A
-n-n101 101 ED
dd1 011
-n-n011 101 DD
101 010 2A
-n-n111 101 FD
101 010 2A
-n-n100 010 22
-n-n101 101 ED
ddO 011
-n-n-

No. of
Bytes
3

No. of M No. of T
Cycles States
10
3

Comments

7
7
13
7
7
13

NOTES: r, r' means any of the registers A, S, C, D, E, H, L
IFF the content of the interrupt enable flip-flop, (IFF) is copied into the P/V flag

16-Bit Load Group
Mnemonic
LD dd, nn

Symbolic
Operation

Flags
H
X

dd - nn

PlY

LD IX, nn

IX - nn

LD IV, nn

IV - nn

LD HL, (nn)

H - (nn + 1)

LD dd, (nn)

dd H - (nn+ 1)
dd L - (nn)

11
01

LD IX, (nn)

IX H - (nn + 1)
IX L - (nn)

11
00

LD IV, (nn)

IV H - (nn+ 1)
IV L - (nn)

11
00

LD (nn), HL

(nn + 1) - H
(nn) - L

LD (nn), dd

(nn + 1) - dd H
(nn) - dd L

11
01

11
00
11
00

8.9

No. of M No. of T
Cycles States
10
3
14

16
20

Comments
dd
Pair

oo-BC
01
10
11

DE
HL
SP

AMII.
-)

A Subsidiary
of Gould Inc.

883
16·Bit Load Group (continued)
Mnemonic
LD (nn), IX

Symbolic
Operation
(nn + 1) ..... IX H
(nn) ..... IX l

Z
X

Flags
H
X

LD (nn), IY

(nn+1) ..... IY H
(nn) ..... IY l

LD SP, HL
LD SP, IX

Sp ..... HL
SP ..... IX

X
X

LD SP, IV

SP ..... IY

PUSHqq

(SP-2) ..... qql
(SP-1) ..... qqH
SP - SP -2
(SP-2) ..... IX l
(SP-1) ..... IX H
SP - SP -2
(SP-2) ..... IY l
(SP-1) ..... IY H
SP - SP -2
qqH ..... (SP+1)
qql ..... (SP)
SP - SP +2
IX H ..... (SP+ 1)

PUSH IX
PUSH IV
POP qq
POP IX

PlY

76
11
00

11
00
11
11
11
11
11
11

IY H..... (SP+ 1)

Comments

6
10
10
11

011 101
100 101

DD
E5

11
11

111 101
100 101

FD
E5

qqO 001

11
11

011 101
100 001

DD
E1

11
11

111 101
100 001

FD
E1

~Y~:: ~~P~2
NOTES:

No. of No.ofM No. of T
Bytes Cycles States
4
20
6

11
11

~~: ~~P~2

POP IY

Opcode
543 210 Hex
011 101 DD
100 010 22
..... n..... n111 101 FD
100 010 22
..... n..... n111 001 F9
011 101 DD
111 001 F9
111 101 FD
111 001 F9
qqO 101

.illL...Eillr
00
01
10
11

Be
DE
HL
AF

dd is any of the register pairs BC, DE, Hl, SP.
qq is any of the register pairs AF, BC, DE, HL.
(PAIR)H, (PAIR)I, refer to high order and low order eight bits of the register pair respectively, e.g., BCl = C, AFH = A.

Exchange, Block Transfer, Block Search Groups
Mnemonic
EX DE, HL
EX AF, AF'
EXX
EX (SP), HL
EX (SP), IX
EX (SP), IY

Symbolic
Operation
DE - HL
AF - AF'
Be - Be'
DE - DE'
HL - HL'
H-(SP+1)
L - (SP)
IX H -(SP+1)
IX l - (SP)
IY H - (SP+ 1)
IY l - (SP)

X
X
X
X

100 011

X
X

11
11
11
11

011
100
111
100

101
011
101
011

DD
E3
FD
E3

11
10

101 101
100 000

ED
AO

Load (HL) into
(DE), increment
the pointers and
decrement the byte
counter (Be)

11
10

101 101
110 000

ED
BO

21
26

If Be
If Be

11
10

101 101
101 000

ED
A8

LDI

(DE) ..... (HL)
DE ..... DE + 1
HL ..... HL + 1
Be ..... Be -1

LDIR

(DE) ..... (HL)
DE ..... DE + 1
DE ..... DE +1
HL ..... HL + 1
Be ..... Be - 1
Repeat until
Be = a

LDD

(DE) ..... (HL)
DE ..... DE -1

PlY

CD
1

76
11
00
11

Opcode
543 210 Hex
101 011 EB
001 000 08
011 001 D9

No. of No. of M No. of T
Bytes Cycles States
4
1
1
1
4
1
4
1
1

Flags
H
X
X
X

NOTE:

1
2

PIV flag is 0 if the result of BC -1 = 0, otherwise P/V
PIV flag Is 0 at completion of Instruction.

CD
1

= 1.

8.10

(2)

Comments

*= 0a

883
Exchange, Block Transfer, Block Search Groups (continued)
Mnemonic
LDD
(cant)

Symbolic
Operation
HL - HL -1
BC - BC -1

Flags
H

PlY

Opcode
543 210 Hex

No. of
Bytes

No. of M No. of T
Cycles Stales

Comments

CZ>

LDDR

(DE) - (HL)
DE - DE -1
HL - HL -1
BC - BC -1
Repeat until
BC = 0

CPI

A - (HL)
HL - HL + 1
BC - BC -1

CPIR

A - (HL)

CPO

A - (HL)
HL - HL -1
BC - BC -1

CPDR

A - (HL)

(3)

ED
B8

21
16

11
10

101 101
100 001

ED
A1

If BC '" 0
If BC = 0

(3)

101 101

110 001

11
10

101 101
101 001

ED
A9

101 101

111 001

If BC '" 0 and
A", (HL)
If BC = 0 or
A = (HL)

CD
X

HL - HL -1
BC - BC -1
Repeat until
A = (HL) or
BC = 0
NOTES:

101 101
111 000

<3.l

HL - HL +1
BC - BC -1
Repeat until
A = (HL) or
BC = 0

11
10

P/v flag is a if the result of Be -1 = O. otherwise P/V
P/v flag is a at completion of instruction only.
3 Z flag is 1 if A = (HL). otherwise Z = O.

If BC '" 0 and
A", (HL)
If BC = 0 or
A = (HL)

8-Bit Arithmetic and Logical Group
Mnemonic
ADD A, r
ADD A, n

Symbolic
Operation
A-A+r
A-A+n

~
~

X
X

Flags
H
X
~
X
~

PlY

V
V

10
11

Opcode
543 210 Hex

IB\
:nmL

r
110

No. of
Bytes
1
2

No. of M No. of T
Cycles Stales
4
1
2
7

-nADD A, (HL)
ADD A,(IX + d)

A - A + (HL)
A-A+(IX+d)

X
X

V
V

ADD A,(IY + d)

A+-A+(IY+d)

ADC A, s
SUB s
SBC A, s
AND s
OR s
XOR s
CP s
INC r
INC (HL)
INC (IX + d)

A - A+s+ CY
A-A -s
A-A-s-CY
A -AA s
A -A V s
A- Ae s
A -s
r-r + 1
(HL)-(HL) + 1
(IX + d) (IX + d) + 1

X
X
X
X
X
X
X
X
X
X

V
V
V
P
P
P
V
V
V
V

INC (IY + d)

(IY + d) (IY + d) + 1

10 [illlID 110
11 011 101
10
110
-d11 111 101
10 [QQQJ 110
-d-

rnnm

00
00
11
00

Bij

7
DO

r
110
011 101 DO
110 []][J
-d11 111 101 FD
00 110 []][1
-d-

8.11

Comments
r
Reg.

000

001
010
011
100
101
111

C
0
E
H
L
A

s is any of r, n,
(HL), (IX + d),
(IY + d) as shown
for ADD instruction.
The indicated bits
replace the ~ in
the ADD set above
4
11

23
23

•

AIMII.
->
A Subsidiary
of Gould Inc.

583
8-Bit Arithmetic and Logic Group (continued)
Mnemonic

Symbolic
Operation

DEC m

m-m -1

Flags
H

Opcode

PlY
V

76 543 210 Hex

rran

No. of
Bytes

No. of M No. of T
Cycles States

Comments
m is any of r, (HL),
(IX +d), (IV +d)
as shown for INC.
DEC same format
and states as INC.
R~e O][J with
in opcode.

General-Purpose Arithmetic and CPU Control Groups
Mnemonic
DAA

Symbolic
Operation

Flags
H

CPL

Converts acc,
content into
packed BCD
following add
or subtract with
packed BCD
operands.
A-A

NEG

A-O-A

CCF

CV - CV

SCF
NOP
HALT
01 •
EI •
1M 0

CV -1
No operation
CPU halted
IFF - 0
IFF -1
Set interrupt
mode 0
Set interrupt
mode 1
Set interrupt
mode 2

X
X
X
X
X
X

1M 1
1M 2

X
X

Opcode

PlY

76 543 210 Hex

No. of
Bytes

100 111

101 111

11
01
00

101 101
000 100
111 111

ED
44
3F

00
00
01
11
11
11
01
11
01
11
01

110
000
110
110
111
101
000
101
010
101
all

37
00
76
F3
FB
ED
46
ED
56
ED
SE

111
000
110
011
011
101
110
101
110
101
110

No. of M No. of T
Cycles States
1

Comments
Decimal adjust
accumulator.

4
4
4
4
4
8

Complement accumulator (one's complement)
Negate acc, (two's
complement).
Complement carry
flag.
Set carry flag.

NOTES: IFF indicates the interrupt enable flip-flop.
CY indicates the carry flip-flop.
* indicates interrupts are not sampled at the end of EI or 01.

16-Bit Arithmetic Group
Mnemonic

Symbolic
Operation

ADD HL, ss

HL - HL +ss

ADC HL, ss

HL - HL +
ss + CV

SBC HL, ss

HL - HL -ss
-CV
IX -IX + pp

ADD IX, pp

Flags
H

Opcode

PlY

76 543 210 Hex

ssl

11
01

101 101
ssl 010

11
01
11
01

101
ssO
011
ppl

001

101
010
101
001

No. of
Bytes
1

No. of M No. ofT
Cycles States
3

Comments

~
01
10
11

DE
HL
SP

Reg.

01
10
11
ADD IV, rr

IV -IV + rr

11
00

111 101
rrl 001

ss - ss + 1
IX -IX + 1

X
X

00
11
00

8.12

ssO 011
011 101
100 011

DO
23

6
10

DE
IX
SP

~
01
10
11

INC ss
INC IX

DE
IV
SP

S83
16-Bit Arithmetic Group (continued)
Mnemonic

Symbolic
Operation

Aags

INC IV

IV -IV + 1

DEC ss
DEX IX

ss - ss -1
IX -IX-1

X
X

DEC IV

IV -IV-1

P/V

76
11
00
00
11
00
11
00

Opcode
543 210 Hex
111
100
ss1
011
101
111
101

101
011
011
101
011
101
011

FD
23

No. of
Bytes
2

No. of M No. ofT
Cycles States
2

Comments

6
DD
2B
FD
2B

10
10

NOTES: ss is any of the register pairs BG, DE, HL, SP.
pp is any of the register pairs BG, DE, IX, sP.
rr IS any of the register pairs Be, DE, IY, SP

Rotate and Shift Group
Symbolic
Operation

Mnemonic

1lli-4EID=J

RLCA

Flags
S

. ..

P/V

Opcode
543 210 Hex

No. of
Bytes

No. of M No. ofT
Cycles States

Comments

000 111

Rotate left circular
accumulator.

010 111

Rotate left
accumulator.

000 111

Rotate left circular
accumulator.

011

Rotate left
accumulator.

A
RLA

L{ti)=--iE]p
A

RRCA

c:r:z3=l--lCYl
A

RRA

~[illJ
A

RLCr

11
00
11
00

RLC (HL)

[Y)---4E&J

RLC(IX + d)

11
11

r, (HL), (IX +
d), (IV +d)

[QI-L{8P

001 011 CB
r
001 011 CB
rnnID 110

011 101
001 011

rnnID

110
111 101 FD
001 011 CB
-d .....
00 [QQQJ 110

[ill]]

m r, (HL),
(IX + d),
(IV + d)
RRC m

DO
CB

Rotate left circular
register r.
r
Reg.

000

001
010
011
100
101
111

C
0
E
H
L
A

-d .....
00
11
11

RLC (IV + d)

RL m

111

[QQJ]

m r, (HL),
(IX + d),
(IV + d)

8.13

Instruction format
and states are as
shown for RLC's.
To form new opcode
replace IDQQ] or
RLC's with shown
code.

AIMII.
-}

A Subsidiary
of Gould Inc.

883
Rotate and Shift Group (continued)
Symbolic
Operation

Mnemonic

RR m

Flags
H

LIZ3--IfuJ

P/V

Opcode
543 210 Hex

No. of
Bytes

No. of M No. of T
Cycles States

Comments

[QITI

m r, (HL),
(IX + d),
(IV +d)

1C]~0

SLA m

IIQQJ

m r, (HL),
(IX + d),
(IV + d)

SRA m

crm-~

[ill]

ITIIJ

11
01

101 101
101 111

ED
6F

11
01

101 101
100 111

ED
67

Rags
H
X

P/V
X

m r, (HL),
(IX +d),
(IV +d)

SRL m

o-EQ}-IQY]
m r, (HL),
(IX + d),
(IV +d)

RLD

RRD

~
~
A

(HL)

Rotate digit left and
right between the
accumulator and
location (HL). The
content of the
upper half of the
accumulator is
unaffected.

Bit Set, Reset and Test Group
Mnemonic
Bit b,r

Symbolic
Operation

Z - rb

BIT b, (HL)

Z - (HI')b

BIT b,(IX+d)b

Z - (IX +d)b

BIT b,(IV + d)b

Z - (IV + d)b

SET b, r

rb - 1

SET b, (HL)

(HL)b -1

Opcode
543 210 Hex
001 011 CB
r
b
001 011 CB
b 110
011 101 DD
001 01.1 CB
-d01
b 110

N
0

76
11
01
11
01
11
11

11
11

111 101
001 011
-d01
b 110

FD
CB

001 011
b
r
001 011
b 110

11
11
11
11

8.14

No. of
Bytes
2

No. of M No. of T
Cycles States
2
8
12
20

Comments
r
Reg.
000
B
001
C
010
D
011
E
100
H
101
L
111
A
Bit Tested
000
0
001
010
011
100
101
110
111

883
Bit Set, Reset and Test Group (continued)
Mnemonic

Symbolic
Operation

Flags
H

SET b, (IX + d)

(IX

d)b-1

11
11

SET b,(IY + d)

(IV

d)b-1

11
11
11

RES b, m

mb - 0
m r, (Hl),
(IX + d),
(IV + d)

PlY

Opcode
76 543 210 Hex
011 101
001 011
-db 110
111 101
001 011
-d110

11
10

DO
CB

No. of No.ofM No. of T
Bytes Cycles States

FD
CB

Comments

To form new opcode
replace 11 of SET b,
s with 10 Flags
and time states for
SET instruction.

NOTES: The notation mb indicates bit b (O to 7) or location m.

Jump Group
Mnemonic
JP nn

Symbolic
Operation

Flags
H

PC - nn

JP cc, nn

If condition cc
is true PCnn, otherwise
continue

JR e

PC - PC

JR C, e

JP (Hl)
JP (IX)

If C = 0,
continue
If C = 1,
PC - PC +
If C = 1,
continue
If C = 0,
PC - PC +
If Z = 0,
continue
If Z = 1,
PC - PC +
If Z = 1,
continue
If Z = 0,
PC - PC +
PC - Hl
PC -IX

JP (IV)

PC -IV

DJNZ, e

B - B-1
If B = O.
continue.
If B '" 0,
PC - PC + e

JR NC, e

JP Z, e

JR NZ, e

P/V

00 011 000
-e-200 111 000
-e -2-

X
e

00 110 000
-e -2-

e
X

Opcode
543 210 Hex
11 000 011 C3
-n-n11
cc 010
-n-n-

00 101 000
-e-2-

No. of
Bytes
3

No. of M No. of T
Cycles States
10
3
10

If condition is met.

If condition not met.

X
X

11 101 001
11 011 101
11 101 001
11 111 101
11 101 001
00 010 000
-e-2-

E9
DO
E9
FD
E9
10

If condition is met.
If condition not met.

12
e

QQ[]CiliQ[]
NZ non-zero
A zero
NC non-carry
C carry
PO parity odd
PE parity even
P sign positive
M sign negative

00 100 000
-e-2-

000
001
OlO
011
100
101
110
111

12
e

Comments

If condition is met.

4
8

If B = O.
13

If B '" 0_

NOTES: e represents the extension in the relative addressing mode.
e is a signed two's complement number in the range < -126. 129 >.
e - 2 In the opcode provides an effective address of pc + e as PC is incremented by two prior to the addition of e.

Call and Return Group
Mnemonic
CAll nn

Symbolic
Operation
(SP-l) -PCH
(SP-2) -PCl
PC - nn

Flags
H

P/V

Opcode
76 543 210 Hex
11

8.15

001 101
-n-n-

No. of No. of M No. of T
Bytes Cycles States
17
5
3

Comments

AIM I.
-)

A Subsidiary
of Gould Inc.

883
Call and Return Group (continued)
Mnemonic
CALL CC, nn

RET
RET cc

RET!
RETNl
RST p

Symbolic
Operation
If condition
cc is false
continue,
otherwise same
as CALL nn
PCl - (SP)
PC H- (SP+ 1)
If condition
cc is false
continue,
otherwise
same as
RET

Flags
H

Z
X

PlY

76
11

Opcode
543 210 Hex
cc 100
....... n·-+
-n001 001
cc

No. of
Bytes
3

No. of M No. ofT
Cycles States
10
3
17

11
01
11
01

101
001
101
000

101
101
101
101

If cc is true.

000

If cc is false.

Return from
interrupt
Return from
non-maskable
interrupt
(SP-l) - PC H
(SP-2) - PCl
PC H - 0
PCl - P

Comments
If cc is false.

ED
4D
ED
45

14
14

111

If cc
cc
000
001
010
011
100
101
110
111

is true.
Condition
NZ non-zero
Z zero
NC non-carry
C carry
PO parity odd
PE parity even
P sign positive
M sign negative

~
001
010
011
100
101
110
111

08H
10H
18H
20H
28H
30H
38H

NOTE: 1RETN loads IFF2 - IFF 1.

Input and Output Group
Mnemonic
IN A, (n)

Symbolic
Operation

A - (n)

IN r, (C)

r-(C)
if r = 110 only
the flags will
be af1ected

INI

(HL) - (C)
B-B-1
HL - HL + 1
(HL) - (C)
B-B-1
HL - HL + 1
Repeat until
B= 0

OUT (n), A

(HL) -(C)
B-8-1
HL - HL - 1
(HL) +- (C)
B-B-1
HL - HL - 1
Repeat until
B= 0
(n) -A

OUT (C), r

OUTI

INIR

IND
INDR

Flags
H

PlY

Opcode
543 210 Hex
011 011 DB
-n11 101 101 ED
000
01

76
11

No. of
Bytes
2

No. of M No. of T
Cycles States
11
3
12

Comments
n to Ao Acc. to A8
C to Ao B to A8 -

A7
- A15
A7
A15

(2)
1

CD
t

X
X

101 101
100 010

11
10

101 101
110 010

11
10

101 101
101 010

ED
AA

11
10

101 101
111 010

ED
BA

(2)

11
10

11
01

5
(If B*O)
4
(If B=O)

C to Ao - A7
B to A8 - A15

C to Ao - A7
8 to A8 - A15

C to Ao - A7
8to A8 - A15

C to Ao - A7
B to A8 - A15

010 011

101 101
001

-n-

CD
X

8.16

11
10

101 101
100 011

n to Ao
Ace. to
C to Ao
B to A8

A8
-

A7
- A15
A7
A15

C to Ao - A7
B to A8 - A15

583
Input and Output Group (continued)
Mnemonic

Symbolic
Operation

Flags
H

PlY

11
10

Opcode
543 210 Hex

No. of
Bytes

No. of M No. of T
Cycles States

Comments

(2)
(C) +- (HL)
B+-B-l
HL +- HL + 1
Repeat until
B= 0

OTIR

101 101
110 011

(If B*O)
4
(If B= 0)

C to Ao - A7
B to As - A15

CD
(C) +- (HL)
B+-B-l
HL +- HL - 1

OUTD

11
10

101 101
101 011

ED
AB

11
10

101 101
111 011

C to Ao - A7
B to As - A15

(If B*O)
4
(If B=O)

C to Ao - A7
B to As - A15

(2)
OTDR

NOTE:

16-bit value in range < 0,65535 >.

Pin Descriptions

Pin Name

Description
ADDRESS BUS. Tri-state output, active high.
DATA BUS. Tri-state input/output, active high.
MACHINE CYCLE ONE. Output, active low. Indicates current machine cycle is the OP code fetch cycle. M1 together with
10RQ indicates an interrupt acknowledge cycle.
MEMORY REQUEST. Tri-state input/output, active low. Indicates that the address bus holds a valid memory address for a
memory read or write operation. Functions as an input only during Bus Request cycles for RAS/CAS generation.
INPUT/OUTPUT REQUEST. Tri-state output, active low. Indicates that the lower half of the address bus holds a valid 1/0
address. Also generated with m when an interrupt is being acknowledged to indicate that a response vector can be placed on the data bus.
READ. Tri-state output, active low. Indicates that the CPU wants to read data from memory or an 1/0 device. The addressed memory or I/O device should use this signal to gate data onto the CPU data bus.
WRITE. Tri-state output, active low. Indicates that CPU data bus holds valid data to be stored in memory or an 1/0 device.
REFRESH. Output, active low. RFSH, together with MREQ, indicates that the lower 8 bits of the address bus contain a
refresh address for dynamic memories.
HALT STATE. Output, active low. Indicates that the CPU has executed a software halt instruction and is awaiting either a
non-maskable interrupt or a maskable'interrupt (if enabled) before operation can resume. While halted, the CPU executes
NOP's to maintain memory refresh activity.

WAIT. Input, active low. Indicates that the addressed memory or 1/0 devices are not ready for data transfer. The CPU continues to enter a Wait state as long as this signal is active. Extended WAIT periods can prevent the CPU from refreshing
dynamic memory properly.
INTERRUPT REQUEST. Input, active low. Generated by 1/0 devices. Will be honored at the end of the current instruction if
the internal software controlled interrupt enable flip-flop is enabled, removing the interrupt mask. INT is normally wireORed and requires an external pullup for these applications.

8.18

583
Pin Descriptions (continued)

Pin Name

Description
NON·MASKABLE INTERRUPT. Input negative edge triggered. Has higher priority than INT and is always recognized at the
end of the current instruction and cannot be masked by the interrupt enable flip-flop as with a normal interrupt. Automatically forces CPU to restart at location 0066H.
RESET. Input, active low. Initializes CPU as follows: reset interrupt enab,le flip-flop, clear PC, clear registers I and R, and
set interrupt to 8080A similar mode. During reset, the address and data bus go to a high impedance state and all control
output signals go to the inactive state. The processor will be vectored to either address OOOOH or address FFOOH depending on the state of the EXT/OS input. Note that RESET must be active for a minimum of three full clock cycles before the
reset operation is complete.
BUS REQUEST. Input, active low. Has higher priority than NMI and is always recognized at the end of the current machine
cycle. Used to request that the CPU address bus, data bus, and MREO, lORa, RD, and WR control signals to go to a high
impedance state so that other devices can control these lines. BUSREO is normally wire-ORed and requires an external
pullup for these applications. Extended BUSREO periods may cause refresh problems.
BUS ACKNOWLEDGE. Output, active low. Indicates to the requesting device that the CPU address bus, data bus, and
MREO, lORa, ·RD, and WR control signals have been set to their high impedance state and the external device can control
these signals.
ROW ADDRESS STROBE. Output, active low. Indicates that the lower 8 bits of the CPU address bus contain a valid row
address for dynamic RAMs providing the CPU has not been bus requested. Strobes row address into dynamic RAM
address latch.
COLUMN ADDRESS STROBE. Output, active low. Indicates that the lower 8 bits of the CPU address bus contain a valid column address for dynamic RAMs providing the CPU has not been bus requested. Strobes column address into dynamic
RAM address latch.
BUS SELECT. Input, active low. Determines whether address bus will be multiplexed for dynamic RAMs. When active,
addresses will not be multiplexed and CAS will not be generated for that particular memory cycle. In addition, an active
low level on BUSSEL during an access to the internal ROM (as indicated by EXT/OS) will cause the CPU to read data from
the external data bus rather than from the internal ROM. BUSSEL also controls the generation of CAS during DMA cycles.

EXT/OS

EXTERNAL MODE SELECT. Input/output. Determines whether processor comes up in the internal or external mode on the
rising edge of reset. When high on reset, the internal ROM is disabled and the CPU performs a normal Z80 reset operation.
When low on reset, the internal ROM is enabled and the CPU is vectored to ROM address FFOO. After reset, this pin is an
output indicating an access to the internal ROM address space with the ROM enable latch set.

8.19

:: _

AMII.======
.""'4.

A Subsidiary
of Gould Inc.

883
System Timing
The S83 executes instructions by proceeding through a
specific sequence of operations:

Figure 2b shows an opcode fetch in which BUSSEL is
high. In this case, the upper byte of the address bus will
remain stable throughout the entire memory access cycle, however, the lower byte of the address bus is multiplexed for interfacing to dynamic RAMs. Initially, the
low byte of the address bus will contain a row address,
and RAS will be generated. The falling edge of RAS is
used to strobe the row address into the dynamic RAMs.
After the address multiplexers have switched, CAS is
generated, and is used to strobe the column address into the dynamic RAMs.

• Memory read or write

• 110 device read or write
• Interrupt acknowledge
The basic clock period is referred to as a T time or
cycle, and three or more T cycles make up a machine
cycle(M1, M2, or M3 for instance). Machine cycles can
be extended either by the CPU automatically inserting
one or more Wait states or by the insertion of one or
more wait states by the user.

One wait state is inserted automatically by the processor. Additional user wait states may be inserted, however RAS will go high on the third rising clock edge
after MREQ goes low regardless of how many wait
states are used. CAS, however, will not go high until
MREQ goes high at the end of the opcode fetch. In interfacing to dynamic RAMs, it is permissible for RAS to
go high before CAS goes high so long as both signals
are high before RAS goes low again.

Instruction Op Code Fetch
The program counter content (PC) is placed on the address bus immediately at the start of the cycle. One half
clock time later MREQ goes active. RD when active indicates that the memory data should be enabled onto
the CPU data bus. The CPU samples data with the rising edge of the clock state T3. Clock state T3 and T4 of a
CPU is internally decoding and executing the instruction. The refresh control signal RFSH indicates that a
refresh read of all dynamic memories is in progress.

mJ'S'SE[ must remain stable from the rising edge of T2

until after the rising edge of T2. Decoding address lines
to generate BUSSEL will fulfill this requirement. It is
not necessary to include MREQ in the generation of
BUSSEL.

Figure 2a shows an opcode fetch in which BUSSEL is
low. This cycle is no different from a standard Z80 CPU,
except that a Row Address Strobe will be generated
during both the opcode fetch and during the refresh
operation.

8.20

S83

Figure 2a. Opcode Fetch (Non-Multiplexed)

CLOCK

Ao·A15

MREQ

ifij

WAIT

00. 07

RFSH

BUSSEl

,~@~
RAS

"NOTE:

--®.

'-®~f

iiAS WILL GO HIGH ON THE THIRD RISING CLOCK EDGE AFTER
MREQ GOES LOW. THIS MAY BE BEFORE T3 IF ADDInONAL
WAIT STATES HAVE BEEN INSERTED.

8.21

•

AIMII.---------r

."""-

A Subsidiary
of Gould Inc.

883
Figure 2b. Opcode Fetch (Multiplexed)

Tw·

CLOCK

As·A15

_-'-_oJ

1'I--.,..,...::"':':~+-----++~'}----++---++--'1"""-----+----+-'

iiii

WAIT

--+-----~~--_+----~~~~J--

,
1

NOTE: Tw·

• NOTE:

= ONE WAIT

STATE AUTOMATICALLY INSERTED BY CPU

iiAS WILL GO HIGH ON THE THIRD RISING CLOCK EDGE AFTER
MREO GOES LOW. THIS MAY BE BEFORE T3 IF ADDITIONAL
WAIT STATES HAVE BEEN INSERTED.

8.22

883
Figure 3a illustrates a memory read or write where
BDsSEL is low. This is the same as a standard Z80
memory read or write cycle, except that RAS goes low
during the cycle, effectively performing a refresh read
operation to any dynamic RAMs in the system.

Memory Read or Write Cycles
Illustrated here is the timing of memory read or write
cycles other tha.!!,1ln OP code fetch cycle (M1 cycle).
The MREQ and RD signals are used exactly as in the
fetch cycle. In the case of a memory write cycle, the
MREQ also becomes active when the address bus is
stable. The WR line is active when data on the data bus
is stable so that it can be used directly as a R/W pulse to
virtually any type of semiconductor memory.

Figure 3b illustrates a memory read or write where
BUSSEL is high. The operating of the address multiplexing and the two address strobes, RAS and CAS, is
the same as for a multiplexed instruction opcode fetch,
except that no automatic wait states are generated.

Figure 3a. Memory Read/Write (Non-Multiplexed)

T2
~LOCK

•
Viii I

OPER~~iJ~
{
00-07

----+tt:~~=~::~O~AT~AO~UT~===!:j

-=t=54@c·
58

BUSSEL

,~------------------

-----~---~~~.. ~:~------------

8.23

AIMII.-----------------."""'4.

A Subsidiary
of Gould Inc.

883
Figure 3b. Memory Read/Write (Multiplexed)

CLOCK

J
-

rJ
~

I+

@ ...
j

OPER~~IJ~

:n~

- ®r-

-@ROW
ADDRESS

COLUMN
ADDRESS

®f--

--I® --~\.
I

-~):

8.24

-r-

883
Input or Output Cycles
Figure 4 illustrates the timing for an 1/0 read or 1/0 write
operation. Notice that during 1/0 operations a single
wait state is automatically inserted (Tw*). The reason

for this is that during 1/0 operations this allows sufficient time for an 1/0 port to decode its address and activate the WAIT line if a wait is required.

Figure 4. Input or Output Cycles

110 {
READ
OPERATION

-I®1~------------7~------------JI-®-

-®-

110 {
WRITE
OPERATION
00·07

---------.r------------~:();'-----;OA;;TA~O~UT------.,
NOTE: Tw·
CPU.

NOTE: Tw·

ONE WAIT CYCLE AUTOMATICALLY INSERTED BY

ONE WAIT CYCLE AUTOMATICALLY INSERTED BY CPU.

8.25

•

~MII.---------.""""-

A Subsidiary
of Gould Inc.

883
Interrupt Request/Acknowledge Cycle
The interrupt signal is sampled by the CPU with the rising edge of the last clock at the end of any instruction.
When an interrupt is accepted, a special M1 cycle is
generated. During this M1 cycle, the IORO signal
becomes active (instead of MREQ) to indicate that the

interrupting device can place an 8-bit vector on the data
bus. Two wait states (Tw*) are automatically added to
this cycle so that a ripple priority interrupt scheme,
such as the one used in the Z80 peripheral controllers,
can be easily implemented (Figure 5).

Figure 5. Interrupt Request/Acknowledge Cycle

+--',_______p_c_+-_ _ _~(~--I+___f+_..,,~~-

AO·A15 _ _ _ _ _ _

IORO

WAIT

-----~---------------~--~--'

DO.D7=======~~------------6H=::::;:=)(~~~K::

NOTE: 1) TL ~ LAST STATE OF PREVIOUS INSTRUCTION.
2) TWO WAIT CYCLES AUTOMATICALLY INSERTED BY CPU(").

8.26

883
Non-Maskable Interrupt Request Cycle
NMI is sampled at the same time as the maskable interrupt input INT but has higher priority and cannot be disabled under software control. The subsequent timing is
similar to that of a normal instruction fetch except that
data put on the bus by the memory is ignored. The CPU
instead executes a restart (RST) address 0066H (Figure

6). The RAS, CAS and address multiplexing functions
operate the same as for a regular instruction opcode
fetch, including the disabling of address multiplexing
and CAS with BUSSEL. Refer to the opcode fetch timing diagram for further timing information on these
signals.

Figure 6. Non-Maskable Interrupt Request Operation

1.----------------------M1-------------------.1

CLOCK

NMI~=====¥===
Ao·A15

------------+-"'+--+-------+'"l"------+--+----_+'

• ALTHOUGH NMI IS AN ASYNCHRONOUS INPUT, TO GUARANTEE ITS BEING
RECOGNIZED ON THE FOLLOWING MACHINE CYCLE, NMI'S FALLING EDGE
MUST OCCUR NO LATER THAN THE RISING EDGE OF THE CLOCK CYCLE
PRECEDING TlAST.

NOTE:

HAs, CAS, AND ADDRESS MULTIPLEXING FUNCTION AS FOR
.!!llIIM!L OPCODE FETCH DEPENDING ON THE STATE OF
BUSSEL.

8.27

AIMI.---------."""4.
~

A Subsidiary
of Gould Inc.

883
Bus Request Acknowledge Cycle
The CPU samples BUSREO with the rising edge of the
last clock period of any machine cycle (Figure 7). If
BUS REO is active, the CPU sets its address, data, and
MREO, 10RO, RD, and WR lines to a high-impedance
state with the rising edge of the next clock pulse. At
that time, any external device can take control of these
lines, usually to transfer data between memory and I/O
devices. While an external device has control of the

bus, address multiplexing is inhibited, however the
ROM select logic for the internal ROM and the
RAS/CAS generation logic is functional. BUSSEl is still
sampled, and will enable/disable the generation of
CAS. Using these features, a DMA device may access
the internal ROM, switch it on or off, and may use the
S83 internal logic to generate RAS and CAS, however
address multiplexing must be done external to the S83.

Figure 7. BUS Request/Acknowledge Cycle

CLOCK

BUSREQ

BUSACK

Ao·AI5

00·07

MREQ

.....

RFSH

HALT

NOTE: Tl ~ LAST STATE OF ANY M CYCLE.
Tx ~ AN ARBITRARY CLOCK CYCLE USED BY REQUESTING DEVICE.

8.28

UNCHANGED

883
Halt Acknowledge Cycle
When the CPU receives a Halt instruction, it executes
NOP states until either an INT or N MI input is received.

When in the Halt state, the HALT output is active and
remains so until an interrupt is received (Figure 8).

Figure 8. Halt Acknowledge Cycle

.. ,- T,

..
,

CLOCK

HAU

cr'

NMi

NOTE: INT WILL ALSO FORCE AiiAITEXIT.
·SEE NOTE, FIGURE 9.

8.29

~1~ll~~~~~
.""'4.
~

A Subsidiary
of Gould Inc.

S83
Reset Cycle
RESET must be active for at least three clock cycles for
the CPU to properly perform its reset operation. As long
as RESET remains active, the address and data buses
float, and the control outputs are inactive. Once RESET
goes inactive, three internal T cycles are consumed
before the CPU resumes normal processing operation
(Figure 9). EXT/OS is sampled on the rising edge of
RESET. If EXT/OS is high, the ROM enable latch is

reset, and the S83 performs a reset to location OOOOH
identical to a standard Z80. If EXT/OS is low, the internal ROM enable latch is set, enabling the internal 8K
byte ROM. The processor is then forced to execute
Nap instructions until it reaches address FFOOH,
where it begins execution. In essence, a reset operation with EXT/OS low causes the processor to begin
operation at address FFOOH in the internal ROM.

Figure 9. Reset Cycle

-Ml-----

CLOCK

00.07

~~----j:.;.;LOAT------+--------

--------------®...."

...

iii _ _ _ _ _ _ _ _ _ _ _----J

MRWR

r
\------~ ____________________·__@~-®~61-------------------------U
~~

bQZU'l

EXT/OS

8.30

S83
AC Characteristics
Number

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

S83-4 (4.0MHz)
Min. (n5) Max. (n5)

Symbol

Parameter

TcC
TwCh
TwCI
TfC
TrC
TdCr(A)
TdA(MREOf)
TdCf(MREOf)
TdCr(MREOr)
TwMREOh
TwMRE01
TdCf(MREOr)
TdCf(RDf)
TdCr(RDr)
TsD(Cr)
ThD(RDr)
TsWAIT(Cf)
ThWAIT(Cf)
TdCr(M1f)
TdCr(M1 r)
TdCr(RFSHf)
TdCr(RFSHr)
TdCf(RDr)
TdCr(RDf)
TsD(Cf)
TdA(IOROf)
TdCr(IOROf)
TdCf(IOROr)
TdD(WRf)
TdCf(WRf)
TwWR
TdCf(WRr)
TdD(WRf)
TdCr(WRf)
TdWRr(D)
TdCf(HALT)
TwNMI
TsBUSREQ(Cr)
ThBUSREO(Cr)
TdCr(BUSACKf)
TdCf(BUSACKr)
TdCr(Dz)
TdCr(CTz)

Clock Cycle Time
Clock Pulse Width (High)
Clock Pulse Width (Low)
Clock Fall Time
Clock Rise Time
Clock t to Address Valid Delay
Address Valid to MREO ~ Delay
Clock +to MREQ +Delay
Clock t to MREO t Delay
MREO Pulse Width (High)
MREO Pulse Width (Low)
Clock +to MREO t Delay
Clock +to RD +Delay
Clock t to RD t Delay
Data Setup Time to Clock t
Data Hold Time to RD t
WAIT Setup Time to Clock ~
WAIT Hold Time after Clock ~
Clock t to M1 +Delay
Clock t to M1 t Delay
Clock t to RFSH +Delay
Clock t to RFSH t Delay
Clock ~ to RD t
Clock t to RD +Delay
Data Setup to Clock +during M2 , M3, M4 or M5 Cycles
Address Stable prior to IORO +
Clock t to IORO ~ Delay
Clock +to IORO t Delay
Data Stable prior to WR +
Clock +to WR +Delay
WR Pulse Width
Clock +to WR t Delay
Data Stable prior to WR +
Clock t to WR +Delay
Data Stable from WR t
Clock +to HALT t to ~
NMI Pulse Width
BUSREO Setup Time to Clock t
BUSREO Hold Time after Clock t
Clock t to BUSACK ~ Delay
Clock +to BUSACK t Delay
Clock t to Data Float Delay
Clock t to Control Outputs Float Delay (MREO, IORO,
RD, and WR)

250*
110
110

65*

110*
220*

2000
2000
30
30
110
85
85
-

85
95
85

0
100
100
130
120
85
85

50
180*
-

75
85

80*

220*

-10*

80
-

60*
80
50
0

65
300

100
100
90
80

* For clock periods other than the minimums shown in the table, calculate parameters using the expressions in the table on the
following page.

8.31

AIMII.
-)

A Subsidiary
of Gould Inc.

583
AC Characteristics (continued)
Number

S83·4 (4.0MHz)
Min. (ns) Max. (ns)

Symbol

Parameter

44
45

TdCr(Az)
TdCTr(A)

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69

TsRESET(Cr)
ThRESET(Cr)
TsINTf(Cr)
ThINTr(Cr)
TdM1f(IOROf)
TdCf(IOROf)
TdCf(IOROr)
TdCf(D)
TsBUSSELf(Cr)
ThCr(BUSSEl)
TwRASh
TwRASI
TdMREOf(RASf)
TsRAd(RASf)
ThRASf(RAd)
TdCf(CASf)
TsCAd(CASf)
TdCr(CAd)
TsRFAd(RASf)
TdMREOr(CASr)
TsEXT(RESETr)
ThEXT(RESETr)
TdCr(RASr)
TdMREOr(RASr)

Clock t to Address Float Delay
MREQ t, 'j(Jfill t, RD t, and WR t to Address
Hold Time
RESET to Clock t Setup Time
RESET to Clock t Hold Time
INT to Clock t Setup Time
INT to Clock t Hold Time
M1 ~ to IORO ~ Delay
Clock ~ to 'iORU ~ Delay
Clock t to IORO t Delay
Clock ~ to Data Valid Delay
BUSSEL ~ to ClK t Setup
ClK ~ to BUSSEl Hold Time
RAS Precharge Time (High State)
RAS low Pulse Width (Refresh)
MREO ~ to RAS ~ Delay
Row Address Valid to R'A'S ~ Setup Time
RAS ~ to Row Address Hold Time
ClK ~ to CAS ~ Delay
Column Address to CAS ~ Setup Time
ClK t to Column Address Valid Delay
Refresh Address to RAS ~ Setup Time
MREO t to CAS t Delay
EXT to 'RtS'ETt Setup Time
EXT to RESET t Hold Time
ClK t to RAS t Delay (M1 Cycle)
MREQ t to RAS t Delay (Non·M1 Cycle)

90
80*
60
0
80
0
565*
85
85
150
0
25
120
220
65
65
20
75
35
160
0
85
60
0

* For clock periods other than the minimums shown in the table, calculate parameters using the expressions in the table on the following page.

Footnotes to AC Characteristics
Number

7
10
11
26
29
31
33
35
45
50
AC Test Conditions:
VIH = 2.0V
VIL = O.BV
VIHC = Vec - O.6V
VILe = 0.45V

Symbol

S83·4

TcC
TdA(MREOf)
TwMREOh
TwMREQ1
TdA(IOROf)
TdD(WRf)
TwWR
TdD(WRf)
TdWRr(D)
TdCTr(A)
TdM1f(IOROf)

TwCh + TwC1 + TrC + TfC
TwCh + TfC - 65
TwCh + TfC - 20
TcC - 30
TcC - 70
TcC - 170
TcC - 30
TwC1 + TrC - 140
TwC1 + TrC - 70
TwCl + TrC - 50
2TcC + TwCh + TfC - 65

VOH = 2.0V
VOL = O.BV
FLOAT = ±O.5V

8.32

85
85

583
Absolute Maximum Ratings
Storage Temperature ............................................................ 65°C to + 150°C
Temperature under Bias .................................................. Specified Operating Range
Voltages on all inputs and outputs with respect to ground ................................. - O.3V to + 7V
Power Dissipation ........................................................................ 1.5 W
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any
condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect device reliability.

Standard Test Conditions
The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND (OV). Positive current flows
into the referenced pin. Available operating temperature ranges are:
•

= O°C to

+5V

+ 70°c, + 4.75V ~ Vee < + 5.25V

All ac parameters assume a load capacitance of 100pF.
Add 10ns delay for each 50pF increase in load up to a
maximum of 200pF for the data bus and 100pF for
address and control lines.

DC Characteristics
Symbol

Parameter

Min.

Max.

Unit

Test Condition

VILC
VIHC
VIL

Clock Input Low Voltage

-0.3

0.45

Clock Input High Voltage

Vcc -.6

Vcc +.3

Input Low Voltage

-0.3

0.8

VIH

Input High Voltage

2.0

VOL
VOH

Output Low Voltage

Vcc
0.4

10L = 2.0mA

10H = - 25Ol1A

Icc

Power Supply Current

Output High Voltage

2.4

200

III

Input Leakage Current

I1A

ILEAK

3-State Output Leakage Current in Float

-10

101

I1A

VIN = 0 to Vcc
VOUT = 0.4 to Vcc

Symbol

Parameter

Min.

Max.

Unit

Note

CCLOCK

Clock Capacitance

CIN

Input Capacitance

COUT

Output Capacitance

Capacitance

8.33

Unmeasured pins
returned to ground

AMI.--------------~ A&~dia~ ~~~~~~~~~~~~~~~~~~~

of Gould Inc. ~~~~~~~~~_~_~_~~~~~

89900
HIGH PERFORMANCE
MICROPROCESSOR FAMILY
Contact factory for complete data sheets

•

S9900 Family Selection Guide
Microprocessors
S9900

16·Bit Microprocessor

S9980A

16·Bit Microprocessor 8·Bit Data Bus

Peripherals
S9901/S9901·4

Programmable Systems Interface (PSI)

S9902/S9902·4

UART/Asynchronous Communications Controller (USRT/ACC)

9.2

AIMII.---------."""'4.
~

A Subsidiary
of Gould Inc.

S9900

16-81T
MICROPROCESSOR

General Description

Features
D 16-Bit Instruction Word
D Full Minicomputer Instruction Set Capability Including Multiply and Divide
D Up to 65,536 Bytes of Memory
o 3.3M Hz Speed
D Advanced Memory-to-Memory Architecture
o Separate Memory, 1/0 and Interrupt-Bus Structures
o 16 General Registers
D 16 Prioritized Interrupts
D Programmed and DMA 1/0 Capability
D N-Channel Silicon-Gate Technology

The S9900 microprocessor is a single-chip 16-bit central
processing unit (CPU) produced using N-Channel
silicon-gate MOS technology. The instruction set of the
S9900 includes the capabilities offered by full minicomputers. The unique memory-to-memory architecture
features multiple register files, resident in memory,
which allow faster response to interrupts and increased
programming flexibility. The separate bus structure
simplifies the system design effort. AMI provides a compatible set of MOS memory and support circuits to be
used with an S9900 system. The system is fully supported by software and complete prototyping systems.

Block Diagram

Pin Configuration

INTERRUPT

ADDRESS

CLDCK----'

CRU

DATA
IIC=NOIllTE/lNAL~

9.3

S9900

MEMEN

READY

Vee

013

D10

¢4

Vss

S9900
S9900 Electrical and Mechanical Specifications
Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)*
Supply Voltage, Vcc (See Note 1) ................................. ,....................................................................... - O.3V to + 20V
Supply Voltage, Voo (See Note 1) ......................................................................................................... - O.3V to + 20V
Supply Voltage, Vss (See Note 1) .......................................................................................................... - O.3V to + 20V
All Input Voltages (See Note 1) ............................................................................................................. - O.3V to + 20V
Output Voltage, (With Respect to Vss) ..................................................................................................... - 2V to + 7V
Continuous Power Dissipation ............................................................................................................................... 1.2W
Operating Free-Air Temperature Range .................................................................................................. O°C to + 70°C
Storage Temperature Range ........................................................................................................... - 55°C to + 150°C
* Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This Is a stress rating and functional operation
of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this speci·
fication is not implied. Exposure to absolute maximum·rated conditions for extended periods may affect device reliability.
NOTE 1: Under absolute maximum ratings voltage values are with respect to the most negative supply, VBB (substrate), unless otherwise
noted. Throughout the remainder of this section, voltage values are with respect to Vss.

Recommended Operating Conditions
Symbol
VBB
Vee
VDD
Vss
V1H
VIH(~)

V1L
VIL(~)

Parameter
Supply voltage
Supply voltage
Supply voltage
Supply voltage
High-level input voltage (all inputs except clocks)
Voo= 11.4
High-level clock input voltage
VDD = 12.6
Low-level input voltage (all inputs except clocks)
Low-level clock input voltage
Operating free-air temperature

Min.
- 5.25
4.75
11.4
2.2
10.0
10.6
-1
-0.3
0

Nom.
-5
5
12
0
2.4

0.4
0.3

Max.
- 4.75
5.25
12.6
Vee + 1

Unit
V
V
V
V
V

VDo

0.8
0.6
70

V
V
°C

Conditions

Timing Requirements Over Full Range of Recommended Operating Conditions (See Figures 1 and 2)
Symbol
tc (1.

9.6

S9900
Pin Description
Table 1 defines the 89900 pin assignments and describes the function of each pin.
Table 1. 89900 Pin Assignments and Functions

Signa!ure

I/O

AO (MSB)
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14 (LSB)

24
23
22
21
20
19
18
17
16
15
14
13
12
10

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

DO (MSB)
01
02
03
04
05
06
07
D8
09
010
011
012
013
014
015 (LSB)

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

I/O
lID
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
lID

Description
ADDRESS BUS
AO through A14 comprise the address bus. This 3·state bus provides the memory·address vec·
tor to the external·memory system when MEM EN is active and I/O·bit addresses and external·
instruction addresses to the I/O system when MEMEN is inactive. The address bus assumes the
high·impedance state when HaLOA is active.

DATA BUS

YBB

Vee
VDD
VSS

DO through 015 comprise the bidirectional 3·state data bus. This bus transters memory data
to (when writing) and from (when reading) the external·memory system when MEMEN is
active. The data bus assumes the high·impedance state when HO LOA is active.

POWER SUPPLIES
Supply voltage (-5V NOM)
Supply voltage (5V NOM). Pins 2 and 59 must be connected in parallel.
Supply volage (12V NOM)
Ground reference. Pins 26 and 40 must be connected in parallel.

1
2,59
27
26,40

CLOCKS
<1>1
<1>2
3
4

8
9
28
25

IN
IN
IN
IN

Phase-l clock
Phase- 2 clock
Phase- 3 clock
Phase-4 clock

9.7

89900
Table 1. 89900 Pin Assignments and Functions (Continued)

Signature

1/0

Description
BUS CONTROL

OBIN

OUT

Data bus in. When active (high), OBIN indicates that the S9900 has disabled its output buffers
to allow the memory to place memory-read data on the data bus during MEMEN. OBIN remains low in all other cases except when HO LOA is active.

MEMEN

OUT

Memory enable. When active (low), MEMEN indicates that the address bus contains a memory
address.

OUT

Write enable. When active (low), WE indicates that memory-write data is available from the
S9900 to be written into memory.

CRUCLK

OUT

CRU clock. When active (high), CRUC LK indicates that external interface logic should sample
the output data on CRUO UT or should decode external instructions on AO through A2.

CRUIN

CRU data in. CRUIN, normally driven by 3-state or open-collector devices, receives input
data from external interface logic. When the processor executes a STC R or TB instruction, it
samples CRUIN for the level of the CRU input bit specified by the address bus (A3 through
A14).

CRUOUT

OUT

CRU data out. Serial I/O data appears on the CRUOUT line when an LOCR, SBZ, or SBO instruction is executed. The data on CRUOUT should be sampled by external I/O interface logic
when CRUCLK goes active (high).

--INTREQ

Interrupt request. When active (low), INTREQ indicates that an external-interrupt is requested.
If INT REQ is active, the processor loads the data on the interrupt-code-input lines ICO through
IC3 into the internal interrupt-code-storage register. The code is compared to the interrupt
mask bits of the status register. If equal or higher priority than the enabled interrupt level
(interrupt code equal or less than status register bits 12 through 15) the S9900 interrupt sequence i$.initiated. If the comparison fails, the processor ignores the request. INTREQ should
remain active and the processor will continue to sample ICO through IC3 until the program
enables a sufficiently low priority to accept the request interrupt.

ICO (MSB)
ICl
IC2
IC3 (LSB)

36
35
34
33

IN
IN
IN
IN

Interrupt codes. ICO is the MSB of the interrupt code, which is sampled when INTREQ is active. When ICO through IC3 are LLLH, the highest external-priority interrupt is being requested
and when HHHH, the lowest-priority interrupt is being requested.

INTERRUPT CONTROL

MEMORY CONTROL
HOLD

Hold. When active (low), HO LO indicates to the processor that an external controller (e.g.,
OMA device) desires to utilize the address and data buses to transfer data to or from memory. The S9900 enters the hold state following a hold signal when it has completed its present
memory cycle.* T~rocessor then places the address and data buses in the high-impedance
state (along with WE, MEMEN, and OBIN) and responds with a hold-acknowledge signal
(HO LOA). When HO LO is removed, the processor returns to normal operation.

*If the cycle following the present memory cycle is also a memory cycle, it, too, is completed before the 89900 enters the hold state. The maximum
number of consecutive memory cycles is three.

9.8

S9900
Table 1. 59900 Assignments and Functions (Continued)
Signature

I/O

Description

HOLDA

OUT

Hold acknowledge. When active (high), HO LOA indicates that the processor is in the hold state
and the address and data buses and memory control outputs (WE, MEM EN, and OBI N) are in
the high-impedance state.

READY

Ready. When active (high). READY indicates that memory will be ready to read or write during the next clock cycle. When not-ready is indicated during a memory operation, the S9900
enters a wait state and suspends internal operation until the memory systems indicate ready.

WAIT

OUT

Wait. When active (high). WAIT indicates that the S9900 has entered a wait state because of a
not-ready condition from memory.
TIMING AND CONTROL

IAQ

OUT

Instruction acquisition. IAQ is active (high) during any memory cycle when the S9900 is acquiring an instruction. IAQ can be used to detect illegal op codes.

LOAD

Load. When active (low), LOAD causes the S9900 to execute a nonmaskable interrupt with
memory address F'FFC16 containing the trap vector (WP and PC). The load sequence begins
after the instruction being executed is completed. LOAD will also terminate an idle state. If
LOAD is active during the time RESET is released, then the LOAD trap will occur after the
RESET fuction is completed. LOAD should remain active for one instruction period. IAQ can
be used to determine instruction boundaries. This signal can be used to implement cold-start
ROM loaders. Additionally, front-panel routines can be implemented using CRU bits as frontpanel-interface signals and software-control routines to control the panel operations.

RESET

Reset. When active (low). RESET causes the processor to be reset and inhibitsWE and CRUCLK.
When RESET is released, the S9900 then initiates a level-zero interrupt sequence that acquires
WP and PC from locations 0000 and 0002, sets all status register bits to zero, and starts execution. RESET will also terminate an idle state. RESET must be held active for a minimum
of three clock cycles.

*If the cycle following the present memory cycle is also a memory cycle it, too, is completed before the S9900 enters the hold state. The maximum
number of consecutive memory cycles is three.

9.9

AMI.---------......

A Subsidiary
of Gould Inc.

S9980A

16·BIT
MICROPROCESSOR

General Description

Features
o 16-Bit Instruction Word
o Full Minicomputer Instruction Set Capability Including Multiply and Divide
o Up to 16,384 Bytes of Memory
o 8-Bit Memory Data Bus
o Advanced Memory-to-Memory Architecture
o Separate Memory, I/O and Interrupt-Bus Structures
o 16 General Registers
o 4 Prioritized Interrupts
o Programmed and DMA I/O Capability
DOn-Chip 4-Phase Clock Generator
o 40-Pin Package
ON-Channel Silicon-Gate Technology

The S9980A microprocessor is a software-compatible
member of AMI's 9900 family of microprocessors.
Designed to minimize the system cost for smaller systems, the S9980A is a single-chip 16-bit central processing unit (CPU) which has an 8-bit data bus, on-chip
clock, and is packaged in a 40-pin package. The instruction set of the S9980A includes the capabilities offered
by full minicomputers and is exactly the same as the
9900s. The unique memory-ta-memory architecture features multiple register files, resident in memory, which
allow faster response to interrupts and increased programming flexibility. The separate bus structure simplifies the system design effort.

Block Diagram

Pin Configuration

ADDRESS

INTERRUPT

HOLD
I191.D~

lAO
~13/CRUQUT
~12

CONTROL

CLOCK----'

MEMEN

RUDY

WE
CRUCLK
VIII

~11

VIS

Al0

CKiI

Uti

liTO

liT 1

D8II

liT 2

CRU

DATA

9.10

CRUll

Yet

S9980A
S9980A Electrical and Mechanical Specifications
Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)·
Supply Voltage, Vcc (See Note 1) ......................................................................................................... - O.3V to + 15V
Supply Voltage, VDD (See Note 1) ......................................................................................................... - O.3V to + 15V
Supply Voltage, VBB (See Note 1) ......................................................................................................... - 5.25V to + OV
All Input Voltages (See Note 1) ............................................................................................................. - O.3V to + 15V
Output Voltage, (See Note 1) ..................................................................................................................... - 2Vto + 7V
Continuous Power Dissipation ............................................................................................................................... 1.4W
Operating Free-Air Temperature Range .................................................................................................. ODC to + 70 DC
Storage Temperature Range ........................................................................................................... - 55 DC to + 150 DC
* Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating and functional operation

of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Under absolute maximum ratings voltage values are with respect to the most negative supply, Vee (substrate), unless otherwise
noted. Throughout the remainder of this section, voltage values are with respect to Vss.

Recommended Operating Conditions
Symbol
VBB
Vee
VDD
Vss
VIH
VIL
TA

Min.
- 5.25
4.75
11.4

Parameter
Supply voltage
Supply voltage
Supply voltage
Supply voltage
High-level input voltage
Low-level input voltage
Operating free-air temperature

2.2
-1
0

Nom.
-5
5
12
0
2.4
0.4
20

Max.
- 4.75
5.25
12.6
Vee + 1
0.8
70

Unit
V
V
V
V
V
V
°C

Conditions

Electrical Characterisitcs Over Full Range of Recommended Operating Conditions
(unless otherwise noted)
Symbol

Parameter

VO H

Data Bus during DBIN
WE, MEMEN, DBIN,
Input Current during HOLDA
Any other inputs
High-level output voltage

VOL

Low-level output voltage

IBB

Supply current from VBB

Min.

Typ.·

Max.

Unit

Conditions

± 75

JJA

± 75

JJA

± 10

JJA
V

2.4
0.5
0.65
1
60
50
80
75

lee

Supply current from Vee

IDD

Supply current from VDD

Input capacitance (any inpots except
data bus)

CDB

Data bus capacitance

Output capacitance (any output except
data bus)

9.11

= Vss to Vee
VI = Vss to Vee
10 = - 0.4mA
10 = 2mA
10 = 3.2mA

rnA

50
40
70
65

* All typical values are at TA = 25°C and nominal voltages

= Vss to Vee

rnA
rnA

O°C
70°C
O°C
70°C
f = 1MHz, unmeasured
pins at Vss
f = 1MHz, unmeasured
pins at Vss
f = 1MHz, unmeasured
pins at Vss

•

S9980A
External Clock
The external clock on the 89980 uses the CKIN pin. The external clock source must conform to the following speci·
fications:
Symbol

Parameter

Min.

Typ.

Max.

Unit

MHz

fext
VH

External source frequency·

External source high level

2.2

VL
t r/tf

External source low level
External source rise/fall time

tWH

External source high level pulse width

tWL

External source low level pulse width

Conditions

V
0.8
10

V
ns

*This allows a system speed of 1.5MHz to 2.5MHz

Switching characteristics Over Full Range of Recommended Operating Conditions
The timing of all the inputs and outputs is controlled by the internal 4 phase clock; thus all timings are based on the
width of one phase of the internal clock. This is lIf(CKIN) (whether driven or from a crystal). This is also 1f4/fsystem. In
the following table this phase time is denoted two
All external Signals are with reference to
Symbol

t3 (see Figure 1).

Parameter

Min.

Typ.

Max.

Unit

tr (t3)

Rise time of t3

tr (t3)

Fall time of t3

7.5

tw (t3)

Pulse width of t3

tw- 1O

tw+ 10

tsu

Data or control setup time·

tw- 15
tw- 3O

Data hold time·

tpHL(WE)

Propagation delay time WE high to low

tpLH(WE)

Propagation delay time WE low to high

t PHL(CRUGLK)

Propagation delay time, CRUCLK high to low

t PHL(CRUGLK)

Propagation delay time, CRUCLK low to high

tov

Delay time from output valid to t3 low

tox

Delay time from output invalid to t3 low

ns
ns

2ttw+ 10

tw = 1/f(cKIN)

tw- 1O

tw+ 20

= 1f4fsystem

tw
-20

tw+ 10
-10

tw+ 30

CL= 200pF

+ 10

2tw- 1O

2tw

2tw+ 2O

tw- 50

tw- 30
tw- 20

ns
tw

*AII inputs except ICO-rC2 must be synchronized to meet these requirements. ICO-IC2 may change synchronously.

9.12

Conditions

S9980A

Figure 1. External Signal Timing

t'(¢I_~

-------...jw1o------

__t_f_(¢_)

I
INPUTS

-I l....
-I
_____~__~I-________~T~----~----~t~
______
t PHL

t PLH

CRUCLK

OTHER
OUTPUTS

Pin Description
Table 1 defines the S9980A pin assignments and describes the function of each pin.
Table 1. S9980A Pin Assignments and Functions
Signature

liD

Description

AO (MSB)
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13/GRUOUT

17
16
15
14
13
12
11
10
9
8
7
6
5
4

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

ADDRESS BUS
AO through A13 comprise the address bus. This 3-state bus provides the memory-address
vector to the external-memory system when MEMEN is active and li~-bit addresses and
external-instruction addresses to the liD system when MEMEN is inactive. The address bus
assumes the high-impedance state when HOLDA is active.

DO (MSB)
01
02
03
04
05
06
07 (LSB)

26
27
28
29
30
31
32
33

liD
1/0
liD
liD
liD
liD
liD
liD

DATA BUS
DO through 07 comprise the bidirectional 3-state data bus. This bus transfers memory data
to (when writing) and from (when reading) the external-memory system when MEMEN is active. The data bus assumes the high-impedance state when HOLDA is active.

CRUDUT
Serial 110 data appears on A13 when an LDGR, SBZ and SBO instruction is executed. This
data should be sampled by the liD interface logic when GRUGLK goes active (high). One bit
of the external instruction code appears on A13 during external instruction execution.

9.13

•

S9980A
Table 1. S9980A Pin Assignments and Functions (Continued)

Signature

VBB
Vcc
Voo
Vss

21
20
36
35

CKIN

Description

110

POWER SUPPLIES
Supply voltage (- 5V NOM)
Supply voltage (5V NOM)
Supply voltage (12V NOM)
Grou nd reference
IN

CLOCKS
Clock In. A TTL compatible input used to generate the internal4-phase clock. CKIN frequency
is 4 times the desired system frequency.

OUT

Clock phase 3 (cI>3) inverted; used as a timing reference.

DBIN

OUT

MEMEN

OUT

BUS CONTROL
Data bus in. When active (high), DBIN indicates that the S9980A has disabled its output buffers to allow the memory to place memory-read data on the data bus during MEMEN. DBIN
remains low in all other cases except when HOLDA is active at which time it is in the highimpedance state.
Memory enable. When active (low), MEMEN indicates that the address bus contains a
memory address. When HOLDA is active. MEMEN is in the high impedance state

OUT

Write enable. When active (low). WE indicates that memory-write data is available from the
S9980 to be written into memory. When HOLDA IS active. WE is in the high-Impedance state

CRUCLK

OUT

CRU clock. When active (high), CRUCLK indicates that external interface logiC should sample the output data on CRUOUT or should decode external instructions on AD. At At3

CRUIN

CRU data in. CRUIN. normally driven by 3-state or open-collector deVices. receives Input
data from external interface logic. When the processor executes a STCR or TB Instruction it
samples CRUIN for the level of the CRU input bit specified by the address bus (A2 through
A12).

INT2
INT1
INTO

23
24
25

IN
IN
IN

Interrupt code. Refer to interrupt discussion for detailed deSCription

HOLD

HOLDA

READY

lAO

MEMORY CONTROL
Hold. When active (low), HOLD indicates to the processor that an external controller (e.g
DMA device) desires to utilize the address and data buses to transfer data to or from
memory. The S998DA enters the hold state following a hold signal when it has completea Its
present memory cycle.' The processor then places the address and data buses in the hlghimpedance state (along with WE. MEMEN. and DBIN) and responds with a holdacknowledge signal (HOLDA). When HOLD is removed. the processor returns to normal
operation

OUT

Hold acknowledge. When active (high). HOLDA indicates that the processor IS In the hold
state and the address and data buses and memory control outputs (WE MEMEN. and DBINI
are in the high-impedance state.

Ready. When active (high). READY indicates that memory will be ready to read or write during the next clock cycle. When not-ready is indicated dUring a memory operation. the
S998DA enters a walt state and suspends internal operatIOn until the memory systems indicated ready

OUT

·,f the cycle following the present memory cycle

TIMING AND CONTROL
Instruction acquIsition lAO is active (high) during any memory cycle when the S9980A IS ac
quiring an Instruction. lAO can be used to detect illegal op codes It may also be used to synchronize LOAD stimulus
IS

also a memory cycle

It.

too

completed before S9980 enters hold state

9.14

AMII.---------......

A Subsidiary
of Gould Inc.

59901159901 .. 4

PROGRAMMABLE SYSTEMS
INTERFACE CIRCUIT

Features
ON-Channel Silicon-Gate Process
o 9900 Series CRU Peripheral
o Performs Interrupt and 1/0 Interface Functions
6 Dedicated Interrupt Input Lines
7 Dedicated 1/0 Ports
9 Ports Programmable as Interrupts or I/O
o Easily Stacked for Interrupt and 1/0 Expansion
o Interval and Event Timer
o Single 5V Supply

General Description
The S9901 Programmable Systems Interface is a multifunctioned component designed to provide low cost
interrupts and 1/0 ports in a 9900/9980 microprocessor
system. It is fabricated with N-channel Silicon-gate technology and is completely TTL compatible on all inputs
including the power supply (+ 5V) and Single-phase
clock. The Programmable Systems Interface provides a
9900/9980 system with interrupt control, 1/0 ports, and a
real-time clock as shown on page 1.

Block -Diagram

S9901 Pin Configuration
Vcc
so
po

RSTI
CRUOUT
CRUCLK

CRUIN

SI
S2

ilffi7ii15
INT8/PI4

INT4

iNT97Pi3

INTJ

INT10/PI2

il'ITiiEli

INTI11P11

IC3

INT12/Pl0

IC2

ICI

INTI4/P8

ICO

Vss

INTI

S4
INT15/P7

INT2
P6

89900/9980 System
AUURESS BUS

r---------------------, ,-------------------,

PROGRAMMABLE
SYSTEMS
INTERFACE

MEMORY
S990o/S998o
CPU

DATA BUS

9.15

•

89901189901-4
59901 Electrical Specifications
Absolute Maximum Ratings Over Operating Free Air Temperature Range (Unless Otherwise Noted)*
Supply Voltages, VccandVss ....................................................... -O.3Vto + 10V
All Input and Output Voltages ....................................................... - O.3V to + 10V
Continuous Power Dissipation .............................................................. O.75W
Operating Free-AirTemperature Range ................................................. O°C to + 70°C
Storage Temperature Range ...................................................... - 65°C to + 150°C
"Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating
Conditions" section of this specification is not implied. Exposure to absolute maximum rated conditions for extended period may affect
device reliability.

Recommended Operating Conditions
Parameter
Supply Voltage, Vee
Supply Voltage, Vss
High-Level Input Voltage, VIH
Low-Level Input Voltage, VIL
Operating Free-Air Temperature, TA

Min.
4.75

Nom.
5
0
2
0.8

Max.
5.25

Unit
V
V
V
V
°C

Electrical Characteristics
Over Full Range of Recommended Operating Conditions (Unless Otherwise Noted)
Symbol
Parameter
Min.
Max.
Unit
Typ.
Input Current (Any Input)
±10
II
J-LA
2.4
V
VOH
High Level Output Voltage
2
V
V
Low Level Output Voltage
0.4
VOL
mA
Supply Current from Vee
100
Icc
200
mA
Supply Current from Vss
Iss
mA
Average Supply Current from Vee
60
lee(av)
Capacitance, Any Input
10
pF
Ci
pF
Capacitance, Any Output
20
Co

Conditions
VI = OV to Vee
10H = 100J-LA
10H = -400J-LA
10L = 3.2mA

tc(O) = 333ns, TA = 25°C
f=1MHz,
All Other Pins at OV

Timing Requirements
Over Full Range of Operating Conditions
Symbol
tc(O)
tam
!fLO)
tW(OLl
tW(OH)
tsu1
tsu~

tsu2
tW1m3UCI K\
th

Parameter
Clock Cycle Time
Clock Rise Time
Clock Fall Time
Clock Pulse Low Width
Clock Pulse High Width
Setup Time for SO-S4, CE, or CRU OUT
Before CRU CLK
Setup Time, Input Before Valid CRU IN
Setup Time, Interrupt Before 0 Low
CRU Clock Pulse Width
Address Hold Time

Min.
300
5
5
45
225
100
200
60
100
60

9.16

S9901
Nom.
333
10
10
55
240
200
200
80
80

Max.
2000
40
40
300

Min.
240
5
10
40
180
80
180
50
80
50

S9901-4
Nom.
250

80
180
50

Max.
667
40
40
300

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

S99011S9901-4
Switching Characteristics
Over Full Range of Recommended Operating Conditions
89901
8ymbol
tpD

tpD

Min.

Parameter
Propagation Delay, 0 Low to Valid
INTREQ, Ico ·I C3
Propagation Delay, 50.5 4 or CE
to Valid CRU fN

89901·4

Typ.

Max.

Typ.

Max.

Unit

110

CL = 100pF,
2 TTL Loads

320

240

CL = 100pF

Min.

Test Conditions

Figure 1. Switching Characteristics

'w(4

S9901

11m

.I.

9.25

•

AJMI.---------.~

A Subsidiary
of Gould Inc.

Advanced Product Description

89902/89902-4

ASYNCHRONOUS COMMUNICATIONS
CONTROLLER (ACC)

Features
o 5- to 8-Bit Character Length
o 1, 1V2,or2Stop Bits
o Even, Odd, or No Parity
o Fully Programmable Data Rate Generation
o Interval Timer with Resolution from 64 to 16,320 /As
o Fully TIL Compatible, Including Single Power
Supply

General Description
The 59902 Asynchronous Communication Controller
(ACC) is a peripheral device for the 59900 family of
microprocessors. The ACC provides an interface between the microprocessor and a serial asynchronoiJs
communication channel, performing the timing and
data serialization and deserialization, thus facilitating the control of the asynchronous channel by the
microprocessor.

Block Diagram

Pin Configuration

INT
DSR

CPU
IIF
RIN
INT

CTS

XDUT

9.26

Vee

XOUT

RIN

CRUIN

CRUCLK

89902

ACC

RTS

CTS

DSR

CRUOUT

Vss

89902/89902-4
S9902 Electrical Specifications
Absolute Maximum Ratings Over Operating Free Air Temperature Range (Unless Otherwise Noted)*
Supply Voltage, Vcc ............................................................... - O.3V to + 10V
All Input and Output Voltages ....................................................... - O.3V to + 10V
Continuous Power Dissipation ............................................................... O.7W
Operating Free-Air Temperature Range ................................................. O°C to + 70°C
Storage Temperature Range ...................................................... - 65°C to + 150°C
*Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute maximum rated conditions for extended period may affect device
reliability.

Recommended Operating Conditions
Parameter

Min.
4.75

Supply Voltage, VCC
Supply Voltage, Vss
High-Level Input Voltage, VIH
Low-Level Input Voltage, VIL
Operating Free-Air Temperature, TA

Nom.
5
0
2.4
0.4

2.2

VOH

Input Current (Any Input)
High Level Output Voltage

VCC
0.8
70

Electrical Characteristics
Over Full Range of Recommended Operating Conditions (Unless Otherwise Noted)
Symbol
Typ.
Parameter
Min.
Max.
Unit
'I

Max.
5.25

±10

VI = OV to Vcc

IOH = 1OOl-tA
IOH = - 4OO I-tA

3.0

2.0

0.85

100

VOL

Low Level Output Voltage

2.5
0.4

ICC(AV)
Ci
Co

Average Supply Current from Vcc

2.5

Capacitance, Any Input
Capacitance, Any Output

10
20

Conditions

2.2

Unit
V
V
V
V
°C

IOL = 3.2mA
tC(O) = 250ns, TA = 25°C
f = 1MHz,
All other pins at OV

Timing Requirements
Over Full Range of Operating Conditions
S9902
Symbol

S9902-4

tC(O)
tr(o)

Clock Rise Time

Max.
667
40

tf(O)

Clock Fall Time

225

tH(O)

Clock Pulse Low Width (High Level)
Clock Pulse Width (Low Level)

tsu(ad)
tSU(CE)
tHD
twcc

Setup Time for Address and CRUOUT Before
CRU CLK
Setup Time for CE Before CRU CLK
Hold Time for Address, CE and CRU OUT After
CRU CLK
CRU CLK Pulse Width

9.27

Max.
2000

Min.
240

Typ.

333
10

tL(O)

Min.
300

Typ.

Parameter
Clock Cycle Time

250

Unit
ns
ns

225

240

180

220

150

100

185

110

100

120

•

89902189902-4
Switching Characteristics
Over Full Range of Recommended Operating Conditions
Symbol

Parameter

Max.

Unit

tpCI(cd)

400

CL = 100pF,

tpCI(CE)

Propagation Delay, Address-to-Valid CRU 1N
Propagation Delay, CE-to-Valid CRU 1N

Min.

Typ.

Conditions

400

CL = 100pF

CRUIN Hold Time After Address

Figure 3. Switching Characteristics

1.----..
-----+1·1
te(¢)

1...
·---tH(¢)-------l·1

¢TTL

\
IsU(CE)-H

SO·S4

UNKNOWN

t,u(ad)

H-tHD

CRU BIT ADDRESS n

' " " " ,"",W.'

-t.==:J

t wee

tHO

1+------1·-*--·1

tHO

::J

I
C

l-----/-tPCI(CE)

CRU BIT ADDRESSm

9900%%~r__\j~______~r--\~______~2'~2----------------------

CRUCLK

________1____
t,u(ad)

CRUDUT

UNKNOWN

1
CRU DATA OUT n

X,-__

C_R_UD_AT_A_OU_T_n+_l_ _C J - - - U N - K N - - " ; O W - N - - C

~tPCI('d)-1
---------------------~21~----~
CRUIN

DON'T CARE

9.28

-1

89902/89902-4
59902 Pin Description
Table 1 defines the 59902 pin assignments and describes the function of each pin as shown on page 1.
Table 1.

Signature

I/O

Description

INT

Interrupt-when active (low), the INT output indicates that at least one of the interrupt conditions has
occurred.

XOUT
RIN

Transmitter serial data output line-XOUT remains inactive (high) when S9902 is not transmitting.

Receiver serial data input line-RCV-must be held in the inactive (high) state when not receiving
data. A transition from high to low will activate the receiver circuitry.

CRU 1N

5erial data output pin from S9902 to CRU 1N input pin of the CPU.

RT5

Request-to-send output from S9902 to modem. This output is enabled by the CPU and remains active
(low) during transmission from the 59902.

CT5

Clear-to-send input from modem to 59902. When active (low), it enables the transmitter section of
59902.

D5R

Data set ready intput from modem to 59902. This input generates an interrupt when going On or Off.

CRUOUT

5erial data input line to S9902 from CRUOUT line of the CPU.

Vss
54 (L'SB)
S3
S2
S1
50
CRU CLK

Ground reference voltage.

10
11
12
13
14

I
I
I
I
I

Address bus SO-S4 are the lines that are addressed by the CPU to select a particular S9902 function.

CRU Clock. When active (high), S9902 from CRU OUT line of the CPU.

~
CE

TTL Clock.

Chip enable-when CE is inactive (high), the 59902 address decoding is inhibited which prevents execution of any 59902 command function. CRU 1N remains at high-impedance when CEis inactive (high).

Vee

Supply voltage (+ 5V nominal).

Device Interface

CPU Interface

The relationship of the ACC to other components in the
system is shown in Figures 2 and 3. The ACC is connected to the asynchronous channel through level
shifters which translate the TIL inputs and outputs to
the appropriate levels (e.g., R5-232C, TTY current loop,
etc.). The microprocessor transfers data to and from the
ACe via the Communication Register Unit (CRU).

The ACC interfaces to the CPU through the Communication Register Unit (CRU). The CRU interface consists
of five address-select lines (50-54), chip enable (CE), and
three CRU control lines (CRU 1N , CRUOUT, and CRUClK)'
When CE becomes active (low), the five select lines address the CRU bit being accessed. When data is being
transferred to the ACC from the CPU, CRUOUT contains
the valid datum which is strobed by CRUClK. When
ACC data is being read, CRU 1N is the datum output by
the ACC.

9.29

89902/89902-4

Figure 4. S9902 ACC In a S9900 System

SERIAL {
SYN·
CHRONOUS
IIF

MEMORY
IIF

Figure 5. S9902 ACC in a S9980 System

SERIAL
SYN'{
CHRONOUS
IIF

MEMORY
IIF

9.30

89902189902-4
Asynchronous Communication Channel Interface

Interrupt Output
The interrupt output (INn is active (low) when any of the
following conditions occurs and the corresponding interrupt has been enabled by the CPU:

The interface to the asynchronous communication
channel consists of an output control line (RTS), two input status lines (DSR and CTS), and serial transmit
(>-_ _ _ _.. OUTPUT

Clock Input

Device Operation

The clock input to the ACC (~ is normally provided by the
~ output of the clock generator (9900 systems) or the
S9980 (9980 systems). This clock input is used to generate the internal device clock, which provides the time
base for the transmitter, receiver, and interval timer of
the ACC.

Control and Data Output

Data and control information is transferred to the ACC
using CE, SO-S4, CRU OUT , and CRUCLK' The diagrams
on page 7 show the connection of the ACC to the S9900
and S9980 CPUs. The high-order CPU address lines are
used to decide the CE signal when the device is being
selected. The low-order address lines are connected to
the five address-select lines (SO-S4)' Table 2 describes
the output bit address assignments for the ACC.

9.31

•

89902189902·4
Connection of the ACC to the 89900

89900

809902

mn FROM CLOCK GENERATOR
CRUCLK

'-----------~ CRUCLK

CRUOUT

CRUIN

80 ' - - - - - - - - - - - - - - - l A 1 0
81

All

A12

A13

CE n..---0'1~

AO-A9

Connection of the ACC to the 89980 CPU's
89980

89902

CRUCLK

CRUCLK
CRUOUT

A13

CRUIN

80
81

A10

All

A12

9.32

AU-A7

89902189902-4
Table 2. S9902 ACC Output Bit Address Assignments

Address 2
S2
S3

1
1
1
1
1
1
0
0
0
0
0

0
0
0
0
0
0
1
1
1
1
1

1
1
0
0
0
0
1
1
1
1
0

0
0
1
1
0
0
1
1
0
0
1

1
0
1
0
1
0
1
0
1
0
1

Address10

Name

Description

31
30-22
21
20
19
18
17
16
15
14
13
12
11
10-0

RESET

Reset Device
Not used
Data Set Status Change Interrupt Enable
Timer Interrupt Enable
Transmitter Interrupt Enable
Receiver Interrupt Enable
Break On
Request to Send On
Test Mode
Load Control Register
Load Interval Register
Load Receiver Data Rate Register
Load Transmit Data Rate Register
Control, Interval, Receive Data Rate, Transmit Data Rate, and
Transmit Buffer Registers

DSCENB
TIMENB
XBIENB
RIENB
BRKON
RTSON
TSTMD
LDCTRL
LDIR
LR[;)R
LXDR

Bit 31 (RESET)

Writing a one or zero to Bit 31 causes the device to be reset, disabling all interrupts, initializing the
transmitter and receiver, setting RTS inactive (high), setting all register load control flags (LDCTRL,
LDIR, LRDR, and LXDR) to a logic one level, and resetting the BREAK flag. No other input or output
operations should be performed for 11,0' clock cycles after issuing the RESET command.

Bit 30-Bit 22

Not used.

Bit 21 (DSCENB)

Data Set Change Interrupt Enable. Writing a one to Bit 21 causes the INT output to be active (low)
whenever DSCH (Data Set Status Change) is a logic one. Writing a zero to Bit 21 causes DSCH interrupts to be disabled. Writing either a one or zero to Bit 21 causes DSCH to be reset.

Bit 20 (TIMENB)

Timer Interrupt Enable. Writing a one to Bit 20 causes the TNT output to be active whenever TIMELP
(Timer Elapsed) is a logic one. Writing a zero to Bit 20 causes TIMELP interrupts to be disabled. Writing
either a one or zero to Bit 20 causes TI MELP and TI MERR (Timer Error) to be reset.

Bit 19 (XBIENB)

Transmit Buffer Interrupt Enable. Writing a one to Bit 19 causes the INT output to be active whenever
XBRE (Transmit Buffer Register Empty) is a logic one. Writing a zero to Bit 19 causes XBRE interrupts to
be disabled. The state of XBRE is not affected by writing to Bit 19.

Bit 18 (RIENB)

Receiver Interrupt Enable. Writing a one to Bit 18 causes the TNT output to be active whenever RBRL
(Receiver Buffer Register Loaded) is a logic one. Writing a zero to Bit 18 disables RBRL interrupts.
Writing either a one or zero to Bit 18 causes RBRL to be reset.

Bit 17 (BRKON)

Break On. Writing a one to Bit 17 causes the XOUT (Transmitter Serial Data Output) to go to a logic zero
whenever the transmitter is active and the Transmit Buffer Register (XBR) and the Transmit Shift
Register (XSR) are empty. While BRKON is set, loading of characters into the XBR is inhibited. Writing a
zero to Bit 17 causes BRKON to be reset and the transmitter to resume normal operation.

Bit 16 (RTSON)

Request-to-Send On. Writing a one to Bit 16 causes the RTS output to be active (low). Writing a zero to
Bit 16 causes RTS to go to a logic one after the XSR and XBR are empty, and BRKON is reset. Thus, the
RTS output does not become inactive (high) until after character transmission has been completed.

Bit 15 (TSTM D)

Test Mode. Writing a one to Bit 15 causes RTS to be internally connected to CTS, XOUT to be internally
connected to RIN, DSR to be internally held low, and the Interval Timer to operate at 32 times its normal
rate. Writing a zero to Bit 15 re-enables normal device operation.

9.33

89902189902-4
Bit 14-11

Register Load Control Flags. Output Bits 14-11 control which of the five registers will be loaded by
writing to Bits 10-0. The flags are prioritized as shown in Table 3.

Table 3. 59902 ACC Register Load Selection

LOCTRL

LOIR

LOR

LXOR

1
0
0
0
0

X
1
0
0
0

X
X
1
X
0

X
X
X
1
0

Control Register
Interval Register
Receive Data Rate Register
Transmit Data Rate Register
Transmit Buffer Register

Bit 14 (LDCTRL)

Load Control Register. Writing a one to Bit 1 causes LDCTRL to be set to a logic one. When LDCTRL = 1,
any data written to bits 0-7 are directed to the Control Register. Note that LDCTRL is also set to a logic
one when a one or zero is written to Bit 31 (RESET). Writing a zero to Bit 14 causes LDCTRL to be reset
to a logic zero, disabling loading of the Control Register. LDCTRL is also automatically reset to a logic
zero when a datum is written to Bit 7 of the Control Register which normally occurs as the last bit written when loading the Control Register with a LDCR instruction.

Bit 13 (LDIR)

Load Interval Register, Writing a one to Bit 13 causes LDI R to be set to a logic one. When LDI R= 1 and
LDCTRL = 0, any data written to Bits 0-7 are directed to the Interval Register. Note that LDIR is also set
to a logic one when a datum is written to Bit 31 (RESET); however, Interval Register loading is not
enabled until LDCTRL is set to a logic zero. Writing a zero to Bit 13 causes LDI Rto be reset to logic zero,
disabling loading of the Internal Register. LDIR is also automatically reset to logic zero when a datum is
written to Bit 7 of the Interval Register, which normally occurs as the last bit written when loading the
Interval Register with a LDCR instruction.

Bit 12 (LRDR)

Load Receive Data Rate Register. Writing a one to Bit 12 causes LRDR to be set to a logic one. When
LRDR = 1, LDIR = 0, and LDCTRL = 0, any data written to Bits 0-10 are directed to the Receive Data
Rate Register. Note that LRDR is also set to a logic one when a datum is written to Bit 31 (RESET);
however, Receive Data Rate Register loading is not enabled until LDCTRL and LDIR have been set to a
logic zero. Writing a zero to Bit 12 causes LRDR to be reset to a logic zero, disabling loading of the
Receive Data Rate Register. LRDR is also automatically reset to logic zero when a datum is written to Bit
10 of the Receive Data Rate Register, which normally occurs as the last bit written when loading the
Receive Data Rate Register with a LDCR instruction.

Bit 11 (LXDR)

Load Transmit Data Rate Register. Writing a one to Bit 11 causes LXDR to be set to a logic one. When
LXDR = 1, LDIR = 0, and LDCTRL = 0, any data written to Bits 0-10 are directed to the Transmit Data
Rate Register. Note that loading of both the Receive and Transmit Data Rate Registers is enabled when
LDCTRL = 0, LDIR = 0, LRDR = 1, and LXDR = 1; thus these two registers may be loaded
simultaneously when data are received and transmitted at the same rate. LXDR is also set to a logic one
when a datum is written to Bit 31 (RESET); however, Transmit Data Rate Register loading is not enabled
until LDCTRL and LDIR have been reset to logic zero. Writing a zero to Bit 11 causes LXDR to be reset to
logic zero, disabling loading of the Transmit Data Rate Register. Since Bit 11 is the next bit addressed
after loading the Transmit Data Rate Register, the register may be loaded and the LXDR flag reset with a
single LDCR instruction where 12 bits (Bits 0-11) are written, with a zero written to Bit 11.

Control Register
The Control Register is loaded to select character length, device clock operation, parity, and the number of stop
bits for the transmitter. Table 4 shows the bit address assignments for the Control Register.

9.34

89902189902-4
Table 4. Control Register Bit Address Assignments
Address 10

Name

SBS1
SBS2
PENB
PODD
CLK4M
RCL1
RCLO

6
5
4

3
2
1
0

Description

I•

Stop Bit Select
Parity Enable
Odd Parity Select
o Input Divide Select
Not Used

I•

Character Length Select

SBS1

SBS2

PENB

PODD

CLK4M

NOT USED

MSB
Bits 7 and 6
(SBS1 and SBS2)

o
RCL 1

RCLO
LSB

Stop Bit Selection. The number of stop bits to be appended to each transmitter character is selected by
Bits 7 and 6 of the Control Register as shown below. The receiver only tests for a single stop bit,
regardless of the status of Bits 7 and 6.
Stop Bit Selection

Bits 5 and 4
(PENB and PODD)

SBS1
Bit 7

SBS2
Bit 6

Number of Transmitted
Stop Bits

0
0
1
1

0
1
0
1

1V2
2
1
1

Parity Selection. The type of parity to be generated for transmission and detected for reception is selected
by Bits 5 and 4 of the Control Register as shown below. When parity is enabled (PENB = 1), the parity bit
is transmitted and received in addition to the number of bits selected for the character length. Odd parity
is such that the total number of ones in the character and parity bit, exclusive of stop bit{s), will be odd.
For even parity, the total number of ones will be even.
Parity Selection

Bit 3 (CLK4M)

PENB
Bit 5

PODD
Bit 4

PARITY

0
0
1
1

0
1
0
1

None
None
Even
Odd

~ Input Divide Select. The ~ input to the S9902 ACC is used to generate internal dynamic logic clocking
and to establish the time base for the Interval Timer, Transmitter and Receiver. The ~ input is internally
divided by either 3 or 4 to generate the two-phase internal clocks required for MaS logic, and to establish

9.35

1_:
_

59902159902-4
the basic internal operating frequency (tint) and internal clock period {tint}. When Bit 3 of the Control Register is set to a logic one
(CLK4M = 1), + is internally divided by 4, and when CLK4M = 0, + is divided by 3. For example, when f+ = 3MHz, as in a standard
3M Hz S9900 system, and CLK4M = 0, + is internally divided by 3 to generate an internal clock period tint of 1J.ls. The figure below
shows the operation of the internal clock divider circuitry. The internal clock frequency should be no greater than 1. 1MHz; thus, when
f+>3.3MHz, CLK4M should be set to a logic one.
Internal Clock Divider Circuitry

+ External Input

+ n

n = 4 if CLK4M = 1

+1 int •

n=3 if CLK4M=0

to internal logic
int

~------------------~

tint
Bits 1 and 0
(RCL1 and RCL o)

I
fint

Character Length Select. The number of data bits in each transmitted and received character is determined by Bits 1 and 0 of the Control Register as shown below.
Character length Selection
RCll
Bit 1

RClD
Bit D

0
0
1
1

0
1
0
1

Character
length
5
5
7
8

Bits
Bits
Bits
Bits

Interval Register
The Interval Register is enabled for loading whenever LOCTRL = 0 and LOIR = 1. The Interval Register is used for
selecting the rate at which interrupts are generated by the Interval Timer of the ACC. The figure below shows the bit
address assignments for the Interval Register when enabled for loading.
Interval Register Bit Address Assignments
7

TMR7

TMR5

TMR4

TMR3

TMR2

o
TMR1

TMRO
LSB

MSB

The figure below illustrates the establishment of the interval for the Interval Timer. As an example, if the Interval
Register is loaded with a value of 8016 (12810) the interval at which Timer Interrupts are generated is tlTVL = tint - 64
M = (1J.1s) (- 64) (- 128) = 8.192 ms. when tint = 1J.ls.
0

Time Internal Selection

signal

. L+.:. :.;IN:. .:.T_ _..
~ + 54

frequency
time

fint
tint

m = (TMR7-TMRO)
fint/ 54
54 tint

TIMELP
fint/(54) (m)
54 m tint

9.36

89902/89902-4
Receive Data Rate Register

The Receive Data Rate Register is enabled for loading whenever LDCTRL 0, LDIR 0, and LRDR 1. The Receive
Data Rate Register is used for selecting the bit rate at which data is received. The diagram shows the bit address
assignments for the Receive Data Rate Register when enabled for loading.

Receive Data Rate Register Bit Address Assignments
10
RDV8

9
I

RDR9

RDR8

?
I

RDR?

RDR6

5
I

RDR5

4
I

RDR4

RDR3

RDR2

0
I

RDR1

RDRO

MSB

LSB

The following diagram describes the manner in which the receive data rate is established. Basically, two programmable counters are used to determine the interval for one-half the bit period of receive data. The first counter either
divides the internal system clock frequency (fint) by either 8 (RDV8 = 1) or 1 (RDV8 = 0). The second counter has ten
stages and may be programmed to divide its input signal by any value from 1 (RDR9-RDRO = 0000000001) to 1023
(RDR8-RDRO 1111111111). The frequency of the output of the second counter (fRHBT) is double the receive-data
rate. Register is loaded with a value of 11000111000, RDV8 1, and RDR9-RDRO 1000111000 23816 568 10.
Thus, for fint 1MHz, the receive-data rate 1 x 106 + 8 + 568 + 2 110.04 bits per second.

=
=

Receive Data Rate Selection

~INT

signal

+m
m = 8 (RDV8 = 1)
or m = 1(RDV8 = 0)

+ n

----. n = (RDR9-RDRO)

RHBT

fint
!lflL = fRHBT
m
mom
Quantitatively, the receive data rate fRCV may be described by the following algebraic expression:
frequency

fint

fRHBT

fint

2mn

(2) (8 RDV8 ) (RDR9-RDRO)

Transmit Data Rate Register

The Transmit Data Rate Register is enabled for loading whenever LDCTRL 0, LDIR 0, and LXDR 1. The Transmit Data Rate Register is used for selecting the data rate for the transmitter. The figure below shows the bit address
assignments for the Transmit Data Rate Register.
10

Selection of transmit data rate is accomplished with the Transmit Data Rate Register in the same way that the
receive data rate is selected when the Receive Data Rate Register. The algebraiC expression for the Transmit Data
Rate fXMT is:

fXMT =

fXHBT

fint
(2) (8 XDV8 ) (XDR9-XDRO)

For example, if the Transmit Data Rate Register is loaded with a value of 00110100001, XDV8 = 0, and XDR9XDRO 1A1 16 417, the transmit data rate 1 X 106 + 2 + 1 + 417 1199.04 bits per second.

9.37

•

89902189902-4
Transmit Buffer Register
The Transmit Buffer Register Is enabled for loading when LOCTRL = 0, LOIR = 0, LROR = 0, LXOR = 0, and
BRKON 0. The Transmit Buffer Register is used for storage of the next character to be transmitted. When the
transmitter is active, the contents of. the Transmit Buffer Register are transferred to the Transmit Shift Register
each time the previous character has been completely transmitted. The bit address assignments for the Transmit
Buffer Register are shown below:
Transmit Buffer Register Bit Address Assignments

XBR7

XBR6

XBR5

XBR4

XBR3

XBR2

XBR1

XBRO
LSB

MSB

All 8 bits should be transferred into the register, regardless of the selected character length. The extraneous high·
order bits will be ignored for transmission purposes; however, loading of bit 7 is internally detected to cause the
Transmit Buffer Register Empty (XBRE) status flag to be reset.

Status and Data Input
Status and data information is read from the ACC using CE, 50.54, and CRU 1N • The following figure illustrates the
relationship of the signals used to access data from the ACC. Table 6 describes the input bit address assignments
for the ACC.

SO -S4

don't care

CRUIN

n+1

Hi-Z

n+2

bit n + 1

bit n

bit n + 2

don't care

n+3

bit n + 3

Hi-Z

Table 5. CRU Output Bit Address Assignments

I TSTMD I LDCTAL I
, I

LAOA

LXOA

CONTROL, INTERVAL, RECEIVE DATA RATE, TRANSMIT DATA RATE, AND TRANSMIT BUFFER REGISTERS

PENB

PODD

I CLK4M I - I

ACL1

Character Length

fint'"

fiIt3+ClK4M)

I
o

I '

TMA'

.TMA 6

TMA5

TMA4

TMA3

TMA2

TMA'

TMAO

ADA2

ADA'

ADAO

XDA2

XDA'

XDAO

XBA2

XBA'

XBAO

TMA

TITVL" tint X 64 X TMR

I
o

I '

ADV8

ADA9

ADA8

ADA'

ADA6

ADA5

ADA4

ADA3

ADA
frev .. fint ..;- 8 ROVe..;... RDR .;. 2

I
NOTE ~: LOADING OF THE BIT INDICATED BY
CAUSES THE LOAD CONTROL

c:::J

, I

XDV8

XDA9

XDA8

XDA'

TRANSMIT DATA RATE REGISTER

XDA6

XDA5

XDA4

XDA3

FLAG FOR

THAT REGISTER TO BE AUTOMATICALLY RESET

XDA

fxmy"

fint -;.

BXfva . ;. . XCI -;- 2

TRANSMIT BUFFER REGISTER

XBA'

9.38

XBA6

XBA5

XBA4

59902/59902-4
Table 6. 89902 ACC Input Bit Address Assignments

Addressg
80

1
1
1
1
1
1
1
1
0
0
0

1
1
0
0
0
0
1
1
1

0
0

0
0
0
0
1
1
1
1
0
0
0
0

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0

a
0
1
1
1
1
1
1
1
1

1
1
0
0
1
1
0
0
1
1

1
0
1
0
1
0
1
0
1
0
1

a
0
1
1

a
0
1
1
0
0
1
1
0
0

a
1
0
1

a
1
0
1
0
1
0
1
0

Address10

Name

31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

INT
FLAG
DSCH
CTS
DSR
RTS
TIMELP
TIMERR
XSRE
XBRE
RBRL
DSCINT
TIMINT

9
8
7-0

XBINT
RBINT
RIN
RSBD
RFBD
RFER
ROVER
RPER
RCVERR
RBR7-RBR(

Description
Interrupt
Register Load Control Flag Set
Data Set Status Change
Clear to Send
Data Set Ready
Request to Send
Timer Elapsed
Timer Error
Transmit Shift Register Empty
Transmit Buffer Register Empty
Receive Buffer Register Loaded
Data Set Status Charge Interrupt (DSCH-DSCENB)
Timer Interrupt (TIMELP-TIMENB)
Not used (always = 0)
Transmitter Interrupt (XBRE-XBIENB)
Receiver Interrupt (RBRL-RIENB)
Receive Input
Receive Start Bit Detect
Receive Full Bit Detect
Receive Framing Error
Receive Overrun Error
Receive Parity Error
Receive Error
Not used (always = 0)
Receive Buffer Register (Received Data)

Bit 31 (INT)

INT = DSCINT + TIMINT + XBINT + RBI NT. The interrupt output (INT) is active when this status signal
is a logic 1.

Bit 30 (FLAG)

FLAG = LDCTRL + LRDR + LXDR = BRKON. When any of the register load control flags or BRKON is
set, FLAG = 1.

Bit 29 (DSCH)

Data Set Status Change Enable. DSCH is set when the DSR or CTS input changes state. To ensure
recognition of the state change, DSR or CTS must remain stable in its new state for a minimum of two
internal clock cycles. DSCH is reset by an output to bit 21 (DSCENB).

Bit 28 (CTS)

Clear to Send. The CTS signal indicates the inverted status of the CTS device input.

Bit 27 (DSR)

Data Set Ready. The DSR signal indicates the inverted status of the DSR device input.

Bit 26 (RTS)

Request to Send. The RTS signal indicates the inverted status of the RTS device output.

Bit 25 (TIMELP)

Timer Elapsed. TIMELP is set each time the Interval Timer decrements to O. TIMELP is reset by an output to bit 20 (TIMENB).

9.39

59902159902-4
Bit 24 (TIMERR)

Timer Error. TIMERR is set whenever the Interval timer decrements to a and TIMElP is already set,
indicating that the occurrence of TIMElP was not recognized and cleared by the CPU before subsequent
intervals elapsed. TIMERR is reset by an output to bit 20 (TIMENB).

Bit 23 (XSRE)

Transmit Shift Register Empty. When XSRE = 1, no data is currently being transmitted and the XOUT
output is at logic 1 unless BRKON is set. When XSRE = 0, transmission of data is in progress.

Bit 22 (XBRE)

Transmit Buffer Register Empty. When XBRE = 1, the transmit buffer register does not contain the next
character to be transmitted. XBRE is set each time the contents of the transmit buffer register are transferred to the transmit shift register. XBRE is reset by an output to bit 7 of the transmit buffer register
(XBR7), indicating that a character has been loaded.

Bit 21 (RBRl)

Receive Buffer Register loaded. RBRl is set when a complete character has been assembled in the
receive shift register and the character is transferred to the receive buffer register. RBRl is reset by an
output to bit 18 (RIENB).

Bit 20 (DSCINT)

Data Set Status Change Interrupt. DSCINT = DSCH (input bit 29)· DSCENB (output bit 21). DSCINT indicates the presence of an enabled interrupt caused by the changing of state of DRS or CTS.

Bit 19 (TIMINT)

Timer Interrupt. TIMINT = TIMELP (input bit 25) • TIMENB (output bit 20). TIMINT indicates the
presence of an enabled interrupt caused by the interval timer.

Bit 17 (XBINT)

Transmitter Interrupt. XBINT=XBRE (input bit 22)· XBIENB (outpu't bit 19). XBINT indicates the
presence of an enabled interrupt caused by the transmitter.

Bit 16 (RBI NT)

Receiver Interrupt. RBINT = RBRl (input bit 21 • RIENB (output bit 18). RBINT indicates the presence
of an enabled interrupt caused by the receiver.

Bit 15 (RIN)

Receive Input. RIN indicates the status of the RIN input to the device.

Bit 14 (RSBD)

Receive Start Bit Detect. RSBD is set one-half bit time after the Ho-O transition of RIN indicating the
start bit of a character. If RIN is not still aat this point in time, RSBD is reset. Otherwise, RSBD remains
true until the complete character has been received. This bit is normally used for testing purposes.

Bit 13 (RFBO)

Receive Full Bit Detect. RFBD is set one bit time after RSBD is set to indicate the sample pOint for the
first data bit of the received character. RSBD is reset when the character has been completely received.
This bit is normally used for testing purposes.

Bit 12 (RFER)

Receive Framing Error. RFER is set when a character is received in which the stop bit, which should be
a logic 1, is a logic O. RFER should only be read when RBRl (input bit 21) is a 1. RFER is reset when a
character with a correct stop bit is received.

Bit 11 (ROVER)

Receive Overrun Error. ROVER is set when a new character is received before the RBRl flag (input bit
21) is reset, indicating that the CPU failed to read the previous character and reset RBRl before the present character is completely received. ROVER is reset when a character is received and RBRl is a when
the character is transferred to the receive buffer register.

Bit 10 (RPER)

Receive Parity Error. RPER is set when a character is received in which the parity is incorrect. RPER is
reset when a character with correct parity is received.

Bit 9 (RCVERR)

Receive Error. RCVERR = RFER + ROVER + RPER. RCVERR indicates the presence of an error in the
most recently received character.

Bit 7-Bit a
(RBR7-RBRO

Receive Buffer Register. The receive buffer register contains the most recently received character. For
character lengths of fewer than 8 bits the character is right justified, with unused most significant bit(s)
all zero(es). The presence of valid data in the receive buffer register is indicated when RBRl is a logic 1.

9.40

89902189902-4
Transmitter Operation

Data Transmission

Transmitter Initialization

If the Transmit Buffer Register contains a character,
transmission begins. The contents of the Transmit Buffer Register are transferred to the Transmit Shift
Register, causing XSRE to be reset and XBRE to be set.
The first bit transmitted (start bit) is always a logic O.
Subsequently, the character is shifted out, LSB first.
Only the number of bits specified by RCL1 and RCLo
(character length select) of the Control Register are
shifted. If parity is enabled, the correct parity bit is next
transmitted. Finally the stop bit(s) selected by SBS1
and SBSo of the Control Register are transmitted. Stop
bits are always logic one. XSRE is set to indicate that
no transmission is in progress, and the transmitter
again tests XBRE to determine if the CPU has yet loaded the next character. The waveform for a transmitted
character is shown below.

The operation of the transmitter is described in Figure
7. The-transmitter is initialized by issuing the RESET
command (output to bit 31), which causes the internal
signals XSRE and XBRE to ,be set, and BRKON to be
reset. Device outputs RTS and XOUT are set, placing
the transmitter in its idle state. When RTSON is set by
the CPU, the RTS output becomes active and the
transmitter becomes active when CTS goes low.

Transmitted Character Waveform

PARITY
, BIT I

,STARTI
, BIT'

XOUT

NUMBER
OF BITS

I, I I
LSB

,
,

I I I
,

LSB+i

MSB

,
I

TRANSMITTED CHARACTER

5,6,7, OR 8

STOP
BIT(S)

I
I

I
IOOR 111,l-112,OR2,

•

message may not be loaded into the Transmit Buffer
Register until after BRKON is reset.

BREAK Trapsmission

The BREAK message is transmitted only if XBRE = 1,
CTS 9, and BRKON 1. After transmission of the
BREAK message begins, loading of the Transmit Buffer
Register is inhibited and XOUT is reset. When BRKON
is reset by the CPU, XOUT is set and normal operation
continues. It is important to note that characters loaded
into the Transmit Buffer Register are transmitted prior
to the BREAK message regardless of whether the
character has been loaded into the Transmit Shift
Register before BRKON is set. Any character to be
transmitted subsequent to transmission of the BREAK

Transmission Termination

Whenever XSRE 1 and BRKON 0, the transmitter is
idle, with XOUT set to one. If RTSON is reset at this
time, the RTS device output will go inactive, disab..!!.!!9
further data transmission until RTSON is again set. RTS
will not go inactive, however, until any characters loaded into the Transmit Buffer Register prior to resetting
RTSON are transmitted and BRKON = O.

9.41

•

89902189902-4

S9902 Transmitter Operation

SET XBRE
SET XOUT
RESETRTS

RESET XSRE
SETXBRE
XMIT START
BIT (XOUT = 0)

Receiver Operation
Receiver Initialization

that no character is currently in the Receive Buffer
Register, and the RSBD and RFBD flags are reset. The
receiver remains in the inactive state until a 1 to 0 transition is detected on the RIN device input.

Operation of the S9902 receiver is described in Figure
8. The receiver is initialized any time the CPU issues the
RESET command. The RBRl flag is reset to indicate
9.42

59902189902-4

59902 Receiver Operation

•
Start Bit Detection

The receiver delays one-half bit time and again samples RIN to ensure that a valid start bit has been detected. If
RIN 0 after the half-bit delay, RSBD is set and data reception begins. If RIN 1, no data reception occurs.

9.43

89902/89902-4
parity. After an additional bit delay, the received
character is transferred to the Receive Buffer Register,
RBRL is set, ROVER and RPER are loaded with appropriate values, and RIN is tested for a valid stop bit. If
RIN 1, the stop bit is valid. RFER, RSBO, and RFBO
are reset and the receiver waits for the next start bit to
begin reception of the next character.

Data Reception
In addition to verifying the valid start bit, the half-bit
delay after the Ho-O transition also establishes the
sample point for all subsequent data bits in this character. Theoretically, the sample pOint is in the center of
each bit cell, thus maximizing the limits of acceptable
distortion of data cells. After the first full bit delay, the
least significant data bit is received and RFBO is set.
The receiver continues to delay one-bit intervals and
sample RIN until the selected number of bits is received. If parity is enabled, one additional bit is read for

If RIN 0 when the stop is sampled, RFER is set to indicate the occurrence of a framing error. RSBO and RFBO
are reset but sampling for the start bit of the next character does not begin until RIN 1.

Character Reception Timing
ISTARTI
BIT

RIN

SAMPLE POINTS

I
I

NUMBER OF BITS

PARITY
BIT I STOP I
I BIT I

RECEIVED DATA

I
LSB ILSB+11

5,6,7, OR 8

..
Interval Timer Operation
Interval Timer Operation

A flowchart of the operation of the Interval Timer is
shown in Figure 9. Execution of the RESET command
by the CPU causes TIMELP and TIM ERR to be reset and
LOIR to be set. Resetting LOIR causes the contents of
the Interval Register to be loaded into the Interval
Timer, thus beginning the selected time interval. The
timer is decremented every 64 internal clock cycles
(every 2 internal clock cycles when in Test Mode) until it
reaches zero, at which time the Interval Timer is reloaded by the Interval Register and TIMELP is set. If
TIMELP was already set, TIMERR is set to indicate that
TIMELP was not cleared by the CPU before the next
time period elapsed. Each time LOIR is reset the contents of the Interval Register are loaded into the Interval
Timer, thus restarting the time.

Device Application
This section describes the software interface between
the CPU and the S9902 ACe and discusses some of the
design considerations in the use of this device in asynchronous communications applications.
9.44

89902189902-4
at 1200 bits per second. Had it been desired that both the
transmitter and receiver operate at 300 bits per second,
the "LDCR @RDR,11" instruction would have been
deleted, and the "LDCR @XDR,12" instruction would
have caused both data rate registers to be loaded and
LRDR and LXDR to have been reset.

Device Initialization

The ACC is initialized by the CPU issuing the
RESET command, followed by loading the Control,
Interval, Receive Data Rate, and Transmit Data Rate
registers. Assume that the value to be loaded into
the CRU Base Register (register 12) in order to point
to bit 0 is 004016' In this application, characters will

Initialization Program

have 7 bits of data plus even parity and one stop bit. The
o input to the ACC is a 3MHz signal. The ACC will divide
this signal frequency by 3 to generate an internal clock
frequency of 1MHz. An interrupt will be generated by the
Interval Timer every 1.6 milliseconds when timer interrupts are enabled. The transmitter will operate at a data
rate of 300 bits per second and the receiver will operate
LI
SBO
LDCR
LDCR
LDCR
LDCR

R12,>40
31
@CNTRL, 8
@INTVL, 8
@RDR, 11
@XDR, 12

The initialization program for the configuration
previously described is as shown below. The RESET
command disables all interrupts, initializes all controllers, sets the four register load control flags
(LDCTRL, LOIR, LRDR, and LXDR). Loading the last bits
of each of the registers causes the load control flag to
be automatically reset.

INITIALIZE CRU BASE
RESET COMMAND
LOAD CONTROL AND RESET LDCTRL
LOAD INTERVAL AND RESET LDIR
LOAD RDR AND RESET LRDR
LOAD XDR AND RESET LXDR

•
•
•
CNTRL
INTVL
RDR
XDR

BYTE
BYTE
DATA
DATA

>A2
1600/64

>1A1
>4DO

The RESET command initializes all subcontrollers, disables interrupts, and sets LDCTRL, LOIR, LROR, and LXDR,
enabling loading of the control register.

Control Register
The options described previously are selected by loading the value shown below.

SBS1 \ SBS2\ PENB \ POOO\ClK4M\

VALUE

\ RCl1 \ RCLO

MSB

LSB

'lO 1'lO ~L _0, ' L:':T:HA::::"
A

00
R2, RCVLST
R3, MXRCNT
R4, CARRET
21
RCVLP
*R2,8
18
R3
RCVEND
*R2 + ,R4
RCVLP

INITIALIZE LIST COUNT
INITIALIZE MAX COUNT
SET UP END OF BLOCK CHARACTER
WAIT FOR RBRL = 1
STORE CHARACTER
RESET RBRL
DECREMENT COUNT
END IF COUNT = 0
COMPARE TO EOB CHARACTER, INCREMENT POINTER
LOOP IF NOT COMPLETE
END OF SUBROUTINE

Register Loading After Initialization
The control, interval,. and data rate registers may be reloaded after initialization. For example, it may be desirable to
change the interval of the timer. Assume, for sample, that the interval is to be changed to 10.24 milliseconds. The instruction sequence is as follows:
SBO
LDCR

13
@INTVL2,8

SET LOAD CONTROL FLAG
LOAD REGISTER, RESET FLAG

•
•
•
INTVL2

BYTE

10240/64

9.47

•

59902159902-4
Caution should be exercised when transmitter interrupts are enabled to ensure that' the transmitter interrupt does
not occur while the load control flag is set. For example, if the transmitter interrupts between execution of the
"SBO 13" and the next instruction, the transmit buffer is not enabled for loading when the transmitter interrupt ser·
vice routine is entered because the LDIR flag is set. This situation may be avoided by the following sequence:
BLWP

•
•
•
lTV CPC

LI MI
MOV
SBO
LDCR
RTWP

@INTVCHG

CALL SUBROUTINE

MASK ALL INTERRUPTS
LOAD CRU BASE ADDRESS
SET FLAG
LOAD REGISTER AND RESET FLAG
RESTORE MASK AND RETURN

@24(R13), RIZ
13
@INTVL2,8

•
•
•
ITVCHG
INTVL2

DATA
BYTE

ACCWP, ITVCPC
10240/64

In this case all interrupts are masked, ensuring that all interrupts are disabled while the load control flag is set.

9.48

·"""'4.
~

A
of Subsidiary
Gould Inc. - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

Future Products
Communication Products
S2579

BCD Input DTMF Generator

S2575

Pulse/DTMF Switchable Dialer With Three Number Repertory Memory

S2552

Telephone Hybrid Plus Pulse Dialer Single Chip Phone

S2553

Telephone Hybrid Plus DTMF Dialer Single Chip Phone

S2567

DTMF Generator With Microprocessor Bus Interface

S35213

Bell 212A Modem

S3559

Call Progress Monitor With DTMF and Pulse Dialer

S7720

Second Source For NEC7720 Digital Signal Processor

S28216

Echo Canceller Processor

Consumer Products
S3620

M/F LPC-10 Speech Synthesizer. Designed As Macro Cell To Allow For
Easy Customization.

ROMs
680XX

High Speed Family of NMOS ROMs Including 32K, 64K Bi-Polar PROM
Pin-Outs

Semi-Custom Products
Two Micron Family of Gate Arrays and Standard Cells
1.25 Micron Family of Gate Arrays and Standard Cells

Microprocessors/Microcomputers
S750X

CMOS 4-Bit Single Chip Microcomputers

S78XX

CMOS High-End 8-Bit Single Chip Microcomputers

S80

Operating System Processor Family

•

~1~ll~~~~~
.~

A Subsidiary
of Gould Inc.

Application Note Summary
Communications Products
52559 DTMF Tone Generator

Describes design considerations, test methods, and results obtained using the S2559 Tone Generator family in
DTMF pushbutton telephones. Interface with type 500 and 2500 networks are discussed. Use in ancillary equipment
is also covered.
Using the 53525A1B

DTMF Bandsplit Filter

Consumer Products
M05 Music

MaS Music is a primer on the application of standard MaS/LSI circuits in creating electronic music. This note
discusses the key elements of music production in an electronic organ.

86800 Family
A Minimal 56802156846 5ystems Design

Details how to make an S6802/S6846 version of the EVK in a minimal systems application.
568045 Compared with Motorola MC 6845

Describes the fundamental differences between the two devices.

89900 Family
59900 Minimum 5ystem Design with the 59900 16-Bit Microprocessor

This design uses just the CPU, a 1K ROM, a 2K RAM, a clock and six smaller IC's.
59900 Controlled Dot Matrix Printer

S9900 shows how to control a 7040 series dot matrix printer in a minimal systems application .

•
-

Guide to MOS Handling
8. All equipment used in the assembly area must be
thoroughly grounded. Attention should be given to
equipment that may be Inductively coupled and generate stray voltages. Soldering irons must have grounded tips. Grounding must also be provided for solder
posts, reflow soldering equipment, etc.

At AMI we are continually searching for more effective
methods of providing protection for MOS devices. Present
configurations of protective devices are the result of years
of research and review of field problems.
Although the oxide breakdown voltage may be far beyond
the voltage levels encountered in normal operation, excessive voltages may cause permanent damage. Even though
AMI has evolved the best designed protective device possible, we recognize that it is not 100% effective.

9. During assembly of ICs to printed circuit boards, it is
advisable to place a grounding clip across the fingers
of the board to ground all leads and lines on the board.
10. Use of carpets should be discouraged in work areas,

A large number of failed returns have been due to misapplication of biases. In particular, forward bias conditions
cause excessive current through the protective devices,
which in turn will vaporize metal lines to the inputs. Careful
inspection of the device data sheets and proper pin designation should help reduce this failure mode.

but in other areas may be treated with anti-static solution to reduce static generation.
11. MOS parts should be handled on conductive surfaces

and the handler must touch the conductive surface
before touching the parts.

Gate ruptures caused by static discharge also account for a
large percentage of device failures in customers' manufacturing areas. Precautions should be taken to minimize the
possibility of static charges occurring during handling and
assembly of MOS circuits.

12. In addition, no power should be applied to the socket or

board while the MOS device is being inserted. This permits any static charge accumulated on the MOS device
to be safely removed before power is applied.

To assist our customers in reducing the hazards which may
be detrimental to MOS circuits, the following guidelines for
handling MOS are offered. The precautions listed here are
used at AMI.

13. MOS devices should not be handled by their leads

1. All benches used for assembly or test of MOS circuits

14. In general, materials prone to static charge accumu-

unless absolutely necessary. If possible, MOS devices
should be handled by their packages as opposed to
their leads.
lation should not come in contact with MOS devices.

are covered with conductive sheets. WARNING: Never
expose an operator directly to a hard electrical ground.
For safety reasons, the operator must have a resistance
of at least 100K Ohms between himself and hard electrical ground.

These precautions should be observed even when an MOS
device is suspected of being defective. The true cause of
failure cannot be accurately determined if the device is
damaged due to static charge build-up.

2. All entrances to work areas have grounding plates on
door and/or floor, which must be contacted by people
entering the area.

It should be remembered that even the most elaborate
physical prevention techniques will not eliminate device
failure if personnel are not fully trained in the proper handling of MOS.

3. Conductive straps are worn inside and outside of
employees' shoes so that body charges are grounded
when entering work area.

This is a most important point and
should not be overlooked_

4. Anti-static neutralized smocks are worn to eliminate
the possibility of static charges being generated by
friction of normal wear. Two types are available; Dupont
anti-static nylon and Dupont neutralized 65% polyesterl
35% cotton.
5. Cotton gloves are worn while handling parts. Nylon
gloves and rubber finger cots are not allowed.

More information can be obtained by contacting the Product Assurance Department.

6. Humidity is controlled at a minimum of 35% to help

American Microsystems, Inc.

reduce generation of static Voltages.

3800 Homestead Road

7. All parts are transported in conductive trays. Use of
plastic containers is forbidden. Axial leaded parts are
stored in conductive foam, such as Velofoam#7611.

Santa Clara, California 95051
Telephone (408) 246-0330
TWX 910-338-0024 or 910-338-0018

B.2

MOS Processes
Process Descriptions

use today in some devices. Several versions of this process
have evolved since its earliest days. A thin slice (8 to 10
mils) of lightly doped N-type silicon wafer serves as the substrate or body of the MOS transistor. Two closely spaced,
heavily doped P-type regions, the source and drain, are
formed within the substrate by selective diffusion of an impurity that provides holes as majority electrical carriers. A
thin deposited layer of aluminum metal, the gate, covers the
area between the source and drain regions, but is electrically
insulated from the substrate by a thin layer (1000-15000A) of
silicon dioxide. The P-Channel transistor is turned on by a
negative gate voltage and conducts current between the
source and the drain by means of holes as the majority
carriers.

Each of the major MOS processes is described on the
following pages. First, the established production proven
processes are described, followed by those advanced processes, which are starting to go into volume production
now. In each case, the basic processes is described first,
followed by an explanation of its advantages, applications,
etc.
P-Channel Metal Gate Process
Of all the basic MOS processes, P-Channel Metal Gate is
the oldest and the most completely developed. It has served
as the foundation for the MOS/LSI industry and still finds
Figure B.1. Summary of MOS Process Characteristics

MATERIALS: N·SILICON SUBSTRATE - [111[ FOR HIGH Vr • [100[ FOR
LOW Vr .
ALUMINUM GATE. SOURCE. AND DRAIN CONTACTS.
PERFORMANCE: POOR SPEED-POWER PRODUCT: VrIVrF TRADEOFF.
COMPLEXITY: TYPICALLY 15 OR LESS PROCESS STEPS.

P·CHANNEl METAL GATE
VARIATIONS:
1. High Threshold (HiVr )
2. Low Threshold (LoVr )

I
: SAME AS ABOVE, ALWAYS 11111 SILICON.
{ MATERIAlS
PERFORMA NCE: LOWER Vr BY ALTERING
TERM; HIGH VTF OF [111 J
SILICON; ENHANCEMENT ANO DEPLETION MODE TRAN·
SISTORS POSSIBLE
COMPLEXIT Y: OVER 15, LESS THAN 20 PROCESS STEPS.

ION IMPLANTED P·CHANNEl METAL GATE

1. With enhancement and depletion mode devices
on same chip

P.CHANNEl
{
SILICON GATE
(Usually with Ion Implantation)
VARIATIONS:
1. With buried interconnect layer
2. With enhancement and depletion mode devices
on same chip
3. Selective Fox (Field Oxidation)
4. Four Vr Process

N.CHANNEl

MATERIALS: [lllJ SUBSTRATE, DOPEO POL YCRYSTALLINE
SILICON GATE
PERFORMANCE: LOWER Vr THROUGH ~MS TERM, BUT HIGH
VrFOF[lllJSILICON
COMPLEXITY: 15·20 PROCESS STEPS, BUT OVER 25 WITH
COMBINED ENHANCEMENT AND DEPLETION
MODE DEVICES
MATERIALS: [100J P·SILICON SUBSTRATE, DOPING POLY·
SILICON GATE, ION IMPLANTED FiElD

PERFORMANCE: ~:SE~~~~CRU~!~, THROUGH HIGH MOBILITY (jJ)

COMPLEXITY: SAME AS P-CHANNEL SiGATE FOR OLDER
PROCESSES. 20·25 PROCESS STEPS FOR
NEWER PROCESSES.

CMOS
NCE: LOW POWER, HIGH SPEED. HIGH VOLTAGE PROCESSES FOR POWER
SUPPLIES UP TO 13.5V; LOW VOLTAGE PROCESSES FOR POWER SUPPLIES
UP TO 5.5V.
MATERIAL S: [100J N·SILICON SUBSTRATE, ION IMPLANTED P·WElL
COMPLEXIT Y: OVER 25 PROCESS STEPS
SPECIAL PROCESS: LINEAR CAPACITORS FOR SWITCHED CAPACITOR
LINEAR INTEGRATED CIRCUITS. NAND ROM OPTION FOR DENSE, LOW
SPEED ROM.

{ pmFORM'
VARIATIONS:
1. Planar, N+/P+ Poly
2. Selective Fox, N+Poly
3. Selective Fox, N+ Poly. isolated P·Well

B.3

MOS Processes
Figure B.2. shows the ion implantation step in a diagrammatic manner. It is performed after the gate oxide is grown,
but before the source, gate, and drain metallization deposition. The wafer is exposed to an ion beam which penetrates
through the thin gate oxide layer and implants ions into the
silicon substrate. Other areas of the substrate are protected both by the thicker oxide layer and sometimes also
by other masking means. Ion implantation can be used with
any process and, therefore could, except for the custom of
the industry, be considered a special technique, rather than
a process in itself.

The basic P-Channel metal gate process can be subdivided
into two general categories: High-threshold and lowthreshold. Various manufacturers use different techniques
(particularly so with the low threshold pr.ocess) to achieve
similar results, but the difference between them always
rests in the threshold voltage VT required to turn a transistor on. The high threshold VT is typically - 3 to - 5 volts
and the low threshold VT is typically - 1.5 to - 2.5 volts.
The original technique used to achieve the difference in
threshold voltages was by the use of substrates with different crystalline structures. The high VT process used [111]
silicon whereas, the low VT process used [100] silicon. The
difference in the silicon structure causes the surface
charge between the substrate and the silicon dioxide to
change in such a manner that it lowers the threshold
voltages.

Figure B.2. Diagram of Ion Implantation Step

One of the main advantages of lowering VT is the ability to
interface the device with TTL circuitry. However, the use of
[100] silicon carries with it a distinct disadvantage also.
Just as the surface layer of the [100] silicon can be inverted
by a lower VT, so it also can be inverted at other random
locations-through the thick oxide layers-by large voltages that may appear in the metal interconnections between circuit components. This is undesirable because it
creates parasitic transistors, which interfere with circuit
operation. The maximum voltage that can be carried in the
interconnections is called the parasitic field oxide threshold voltage VTF , and generally limits the overall voltage at
which a circuit can operate. This, then, is the main factor
that limits the use of the [100] low VT process. A drop in VTF
between a high VT and low VT process may, for example, be
from - 28V to -17V.

BORON (HYPE) IONS FROM IMPLANTER ACCELERATOR

t t tt t t t

The implantation of P-type ions into the substrate, in effect,
reduces the effective concentration of N-type ions in the
channel area and thus lowers the VT required to turn the
transistor on. At the same time, itdoes not alter the N-type
ion concentration elsewhere in the substrate and therefore,
does not reduce the parasitic field oxide threshold voltage
VTF (a problem with the low VT P-Channel Metal Gate process, described above). The [111] silicon usually is used in
ion-implanted transistors.

The low VT process, because of its lower operating
voltages, usually produces circuits with a lower operating
speed than the high VT process, but is easier to interface
with other circuits, consumes less power, and therefore is
more suitable for clocked circuits. Both P-Channel metal
gate processes yield devices slower in speed than those
made by other MaS processes, and have a relatively poor
speed/power product. Both processes require two power
supplies in most circuit designs, but the high VT process,
because it operates at a high threshold voltage, has excellent noise immunity.

In fact, if the channel area is exposed to the ion beam long
enough, the substrate in the area can be turned into P-type
silicon (while the body of the substrate still remains N-type)
and the transistor becomes a depletion mode device. In any
circuit some transistors can be made enhancement type,
while others are depletion type, and the combination is a
very useful circuit design tool.

Ion Implanted P-Channel Metal Gate Process
The P-Channel Ion Implanted process uses essentially the
same geometrical structure and the same materials as the
high VT P-Channel process, but includes the ion implantation step. The purpose of ion implantation is to introduce
P-type impurity ions into the substrate in the limited area
under the gate electrode. By changing the characteristics
of the substrate in the gate area, it is possible to lower the
threshold voltage VT of the transistor, without influencing
any other of its properties.

The lon-implanted P-Channel Metal Gate process is very
much in use today. Among all the processes, it represents a
good optimization between cost and performance and thus
is the logical choice for many common circuits, such as
memory devices, data handling (communication) circuits,
and others.

B.4

MOSProcesses
separate step, after the thick oxide layer is in place, the
simultaneous deposition of additional polysilicon interconnect lines is only a matter of masking. These interconnect
lines are buried by later steps, as shown in Figure B.3.

Because of its low VT, it offers the designer a choice of using low power supply voltages to conserve power or increase supply voltages to get more driving power and thus
increase speed. At low power levels it is more feasible to
implement clock generating and gating circuits on the chip.
In most circuit designs only a single power supply voltage
is required.

Figure B.3. Crossection of an N-Channel Silicon
Gate MOS Transistor

N-Channel Process
Historically, N-Channel process and its advantages were
known well at the time when the first P-Channel devices
were successfully manufactured; however, it was much
more difficult to produce N-Channel. One of the main
reasons was that the polarity of intrinsic charges in the
materials combined in such a way that a transistor was on
at OV and had a VT of only a few tenths of a volt (positive).
Thus, the transistor operated as a marginal depletion mode
device without a well-defined on/off biasing range.
Attempts to raise VT by varying gate oxide thickness, increasing the substrate doping, and back biasing the substrate, created other objectionable results and it was not
until research into materials, along with ion implantation,
silicon gates, and other improvements came about that
N-Channel became practical for high density circuits.

(a) TRANSISTOR READY FOR SOURCE AND DRAIN DIFFUSIONS

P SUBSTRATE

The N-Channel process gained its strength only after the
P-Channel process, ion implantation, and silicon gate all
were already well developed. N-Channel went into volume
productions with advent of the 4K dynamic RAM and the
microprocessor, both of which required speed and high
density. Because P-Channel processes were nearing their
limits in both of these respects, N-Channel became the
logical answer.

(b) FINISHED TRANSISTOR

One minor limitation associated with the buried interconnect lines is their location. Because the source and drain
diffusions are done after the polysilicon is deposited [see
(a) of Figure B.3] the interconnect lines cannot be located
over these diffusion regions.

The N-Channel process is structurally different from any of
the processes described so far, in that the source, drain,
and channel all are N-type silicon, whereas the body of the
substrate is P-type. Conduction in the N-Channel is by
means of electrons, rather than holes.

A second advantage of a silicon gate is associated with the
reduction of overlap between the gate and both the source
and drain. This reduces the parasitic capacitance at each
location and improves speed, as well as power consumption characteristics. Whereas in the metal gate process, the
P region source and drain diffusion must be done prior to
deposition of the gate electrode, in silicon gate process,
the electrode is in place during diffusion, see (a) of Figure
B.3. Therefore, no planned overlap for manufacturing
tolerance purposes need exist and the gate is said to be
self-aligned. The only overlap that occurs is due to the normallateral extension of the source and drain regions during
the diffusion process.

The main advantage of the N-Channel process is that the
mobility of electrons is about three times greater than that
of holes and, therefore, N-Channel transistors are faster
than P-Channel. In addition, the increased mobility allows
more current flow in a channel of any given size, and therefore N-Channel transistors can be made smaller. The positive gate voltage allows an N-Channel transistor to be completely compatible with TTL.
Although metal gate N-Channel processes have been used,
the predominant N-Channel process is a silicon gate process. Among the advantages of silicon gate is the possibility
of a buried layer of interconnect lines, in addition to the normal aluminum interconnnections deposited on the surface
of the chip. This gives the circuit designer more latitude in
layout and often allows the reduction of the total chip size.
Because the polysilicon gate electrode is deposited in a

The Silicon-gate process produces devices that are more
compact than metal gate, and are slightly faster because of
the reduced gate overlap capacitance. Because the basic
silicon gate process is relatively simple, it is also economical. It is a versatile process that is used in memory devices
and most any other circuit.

B.5

MOS Processes
processes allow Single power supply voltages from + 1.5 to
+5.5 volts.

In addition to its use in large memory chips and microprocessors, N-Channel has become a good general purpose
process for circuits in which compactness and high speed
are important.

The first implementation of an inverting gate is a process
that uses both n + to p + polysilicon. The basic structure is
a first-generation approach to which a selective fieldoxidation process has been added.

CMOS

The basic CMOS circuit is an inverter, which consists of
two adjacent transistors-one an N-Channel, the other a
P-Channel, as shown in Figure B.4. The two are fabricated
on the same substrate, which can be either N or P type.

Figure B.5 shows the plan and section views of the threedevice gate portion. Because the P-Well in the top view
spans both N-Channel devices, it is referred to as ubiquitous, and the process is called Ubiquitous P-Well.

The CMOS inverter in Figure B.4 is fabricated on an N-type
silicon substrate in which a P "tub" is diffused to form the
body for the N-Channel transistor. All other steps, including
the use of silicon gates and ion implantation, are much the
same as for other processes.

In this planar process, p + guard rings are used to reduce
surface leakage. Polysilicon cannot cross the rings, however, so that bridges must be built. Note the use of p +
polysilicon in the P-Channel areas. The plan view shows the
construction of the bridges linking p + to metal to n + .
(Were the process to be used for a lOW-Voltage, firstgeneration application like a watch circuit, the guard rings
would not be necessary and polysilicon could directly connect N-Channel and P-Channel devices; however, to ensure
good ohmic contact from one type of polysilicon to another,
polysilicon-diode contacts must be capped with metal.)

The main advantage of CMOS is extremely low power consumption. When the common inpuJ to both gate electrodes
is at a logic 1 (a positive voltage) the N-Channel transistor is
biased on, the P-Channel is off, and the output is near
ground potential. Conversely, when the input is at a logic 0
level, its negative voltage biases only the P-Channel transistor on and the output is near the drain voltage + VDD • In
either case, only one of the two transistors is on at a time
and thus, there is virtually no current flow and no power
consumption. Only during the transition from one logic
level to the other are both transistors on and current flow increases momentarily.

This process provides a buried contact (n + polysilicon to
n + diffusion) that can yield a circuit-density advantage.
However, neither of the other two second-generation
approaches provides buried contacts. Therefore, if a layout
in this process is to be compatible with the others, the
buried contact must be eliminated. Though there will be a
penalty in real estate, the gain for custom applications is a
great increase in the number of available CMOS vendors.

Silicon Gate CMOS is also fast approaching speeds of
bipolar TTL circuits. On the other hand, the use of two transistors in every gate makes CMOS slightly more complex
and costly, and requires more chip size. For these reasons,
the original popularity of CMOS was in SSI logic elements
and MSI circuits-logic gates, inverters, small shift
registers, counters, etc. These CMOS devices constitute a
logiC family in the same way as TTL, ECl, and other bipolar
circuits do; and in the areas of very low power consumption,
high noise immunity, and simplicity of operation, are still
widely accepted by discrete logic circuit designers.

The n + -Only Polysilicon Approach

Both of the second-generation CMOS processes that follow
are variants of the n + -only, selective-field-oxide approach.
One closely resembles the p + n + Ubiquitous-P-Well process, since it, too, has a Ubiquitous P-Well that is implanted
before the field oxidation and thus runs under the field
oxide. The other, called isolated P-Well, has separate wells
for each N-Channel device that are implanted after field
oxidation.

low power CMOS circuits made the watch circuit possible
and also have been used in space exploration, battery
operated consumer products, and automotive control
devices. As experience was gained with CMOS, tighter
design rules and reduced device sizes have been implemented and now VlSI circuits, such as 16K RAM memories
and microprocessors, are being manufactured in volume.

Figure B.6 shows the section and plan views of the n + -only
Ubiquitous-P-Well approach used to build the gate of Figure
B.4. This is the 5~m process recommended by AMI and
others for new, high-performance CMOS designs. The layout is simpler than with the n + /p + polysilicon UbiquitousWell approach (there are no buried contacts and no
polysilicon-diode contacts), and it occupies less area for
the same line widths. Also, since the process permits implanting in the field region, no guard rings are required.

CMOS circuits can be operated on a single power supply
voltage, which can be varied from + 2.5 to about + 13.5
volts with the high voltage processes, with a higher voltage
giving more speed and higher noise immunity. low voltage

B.6

MOS Processes
Polysilicon can thus cross directly from P- to N-Channel
device areas without the need for bridges or polysilicondioxide contacts.
A variant of the all n + (See Figure B.7) polysilicon process
just discussed uses basically the selective field-oxide
approach except that the P-Wells are not continuous under
the field-oxide areas; they are Instead bounded by field-

oxide edges. Since the P-Wells are naturally isolated from
one another, the process Is called n + poly-isolated P-Well.
The Isolated wells must all be connected to ground; If they
are left floating, circuit malfunctions are bound to occur.
The grounding Is done either with p + diffusions or with
top-side metalization that covers a p + -to-P-Well contact
diffusion.

Figure 8.4. Crossectlon and Schematic Diagram of a CMOS Inverter

INPUT

-{:>o--

OUTPUT

Voo

INPUT -__.-....

P-CH
...-.-- OUTPUT

N-CH

B.7

MOS Processes
Figure B.S. n + Ip + Polysilicon Approach

P-CHANNEL

N-CHANNEL

p+-PoLYSILICoN-Top+ DIFFUSION BURIED
CONTACT

( n + PoLYSILICoN

'--------.

( n + DIFFUSION

1---:"""-..,

TO VDD

I
I
I

~)-------t

p+ DIFFUSION

P-WELL EDGE

.-----"'1

" - p+ GUARD RING

THE FIRST HIGH-PERFORMANCE COMPLEMENTARY -MoS PLANAR
PRoCESS_ ITS DRAWBACKS: TWO TYPES OF PoLYSILICoN ARE
USED, AND THE UNAVAILABILITY OF FIELD IMPLANT DOPING TIES
FIELD THRESHOLD TO DEVICE THRESHOLOS_

B.8

MOS Processes
Figure B.6. n + - Only Polysilicon Approach

P·CHANNEL

N·CHANNEL
IMPLANTED FIELD

ALUMINUM)

"+ '"""'""'\

("+ """"'"

r---~--------~---4--------------~

ALL NEW HIGH·PERFORMANCE CMOS CIRCUITS WILL USE ONE
TYPE OF POL YSILICON. THIS VERSION HAS A UBIQUITOUS
P·WELL: THAT IS, SERIES N·CHANNEL DEVICES SIT IN A COMMON
P·WELL, WHICH, IMPLANTED BEFORE FIELD OXIDATION, RUNS
UNDER THE FIELD OXIDE. THIS IS AMI'S PREFERRED CMOS PRO·
CESS FORMAT FOR ALL NEW DESIGNS.

B.9

MOS Processes
Figure B.7.lsolated Wells

N·CHANNEL

P·CHANNEL
IMPLANTED FIELD

ALUMINUM)

pO"SlUCON \

POL YSILICON

P·WELL
CONNECTION

r---~---------4----4--L---------,

~ n + DIFFUSION
P+ .Fro,... )

THE THIRD CMOS APPROACH ISOLATES ALL N·CHANNEL DEVICES
IN SEPARATE P·WELLS, SINCE THE ISOLATED WELLS MUST BE
DOPED MUCH MORE HEAVILY THAN THOSE OF THE UBIQUITOUS·
WELL APPROACH, n + .TO P·WELL CAPACITANCE IS GREATER
AND SWITCHING SPEEDS LOWER. THIS IS AN n + ·ONLY
POLYSILICON PROCESS.

B.10

MOSProcesses
In the Isolated-Well process, the P-Wells must be doped
much more heavily than in the Ubiquitous-Well process.
One result is a higher junction capacitance between the n +
areas and the wells that both slows switching speeds and
raises the power dissipation of a device. Even though the
speed loss could be compensated for by slightly shorter
channel lengths, the operating power still remains high.

Table 1_ Layout Compatibility Concerns for
CMOS Processes
Layout Feature

n + - Only PolysiHeon n + - Only PolyslNeon
Ubiquitous P·Well
Isolated P·WeU

Polysilicon Diode
Contact

Yes

P-Well Isolation With
Diffusion Mask

Yes

Tight P-Well-To-p +
Spacing

Yes

Layout Care Required
For P-Well
Electrical Contacts

Yes

Bu ried Contact

Although currently available from AMI and other manufacturers, the Isolated-Well process is in fact not recommended
for new designs by AMI. Its layout takes up more area than
does one using the Ubiquitous-Well approach, even though
its P-Well to p + -area spacing is slightly less.

n + /p + Polyslneon
Ubiquitous P·Well

Figure B.8. Comparative Data on Major MOS Processes
MASKS
REQUIRED
9

I-

I- P METAL GATE HI V,

P METAL GATE HI V,

1000-

P METAL GATELO V,

f- P METAL GATE LO V,

I- P METAL GATE HI Vr

(-PSi-GATE

I- PION IMPLANT

100-

I- PSi-GATE
I- PION IMPLANT

f-PSI-GATE

I=I-~ ~IEmEGATE LO V,

r--N Si-GATE
I - N Si-GATELO V,

- I- CMOS LINEAR PROCESS

- ! - CMOS, N-CHANNEL 4 Vr PROCESS

I-

NSi-GATELOV,
I - PION IMPLANT

_ !- N-CHANNEL Si-GATE (DEPLETION LOAD)

- f-

N-CHANNEL SI-GATE LO V,

- I--'- N-CHANNEL SI-GATE

I- NSi-GATELO V,

100-

f-NSI-GATE

I- N SI-GA TE OEP LO

_ I- P-CHANNEL SI-GATE
- I- P-CHANNEL METAL GATE ION IMPLANT

r--N Si-GATE DEP LD, VMOS

10010-

-I-

P-CHANNEL METAL GATELO V,

-I-

P-CHANNEL METAL GATE to V,

10-

I- CMOS (PLANAR)

I-CMOS
1-

t-CMOS
f - N Si-GATE DEP LD

0RELATIVE SPEED
POWER PRODUCT
(NS-MW)

0RELATIVE POWER
(AT AXED SPEED)

10-

I- CMOS (SELECTIVE FOX)

RELATIVE
PROPAGATION
DELAY

8.11

RELATIVE COST
PER LOGIC FUNCTION

MOS Processes
7.5 Micron CMOS Process Parameters

Parameter
VTN
VTP
VTF
BVDSS
RDiFF P+
N+
RpOLY P+
N+
Tax
P+
Xi
N+
Operating Voltage
Max Rating
Process Designator

Low VT
Min.
Max.

High VT
Min.
Max.

Comments

.55
- .4
8
24
30
9
118
30
1300
1.8"
2.0"

1.0
- .8
15
28
28
9.1
80
29
1200
1.8"
2.0"
5
-

N'Channel Threshold at lflA 50 x 7.5fl Device (Volts)
p·Channel Threshold at lflA 50 x 7.5fl Device (Volts)
Poly Field Threshold at lflA 50 x IOfl Device (Volts)
Drai~·Source Breakdown (Volts)
Diffusion Resistivity Q/D
Diffusion Resistivity Q/D
Poly Resistivity Q/D
Poly Resistivity Q/D
Gate Oxide Thickness, In Angstroms
Junction Depth, In fl
Junction Depth, In fl
In Volts
In Volts

CTA

.85
- .95

39
15
172

5
5.5
CTA

CTE

1.5
-1.4

33
12.6
140
39

12
13.2
CTE

(" TYPical)

CMOS I Process Parameters

Parameter

Glnlral Purpose
High ·V
Low V
Min.
Min.
Max.
Max.

Doubll Poly
High V
Low V
Min.
Max.
Min.
Max.

NAND ROM
High V
Low V
Min.
Min.
Max.
Max.

VTN

0.7

1.3

0.5

1.1

0.7

1.3

0.5

1.1

0.7

1.3

0.5

1.1

VTP

-0.7

-1.3

-05

-1.1

-0.7

-1.3

-0.5

-1.1

-0.7

-1.3

-0.5

-1.1

VTF
BVDSS
RDIFF p+
N+
RpOLY
Tax
P+
Xi
N+
Operating Voltage
Max Rating
Process Designator

15
35
15
750
1.2"
1.5"
2.2

CVA

35
80
45
850

13.2
13.2
CVA

7
7
15
35
15
750
1.2"
1.5"
1.5

CVH

35
80
45
850

5.5
5.5
CVH

15
35
15
750
1.2"
1.5"
2.2

CVB

35
80
45
850

13.2
13.2
CVB

7
7
15
35
15
750
1.2"
1.5"
1.5
CVE

35
80
45
850

5.5
5.5
CVE

("TYPical)

CMOS II Process Parameters (P·Well)
Parameter
VTN
VTP
VTF
BVDSS
RDiFF P+
N+
RpOLY
Tax
P+
Xi
N+
Operating Voltage
Max Rating
Process Designator

Single Metal
Min.
Max.
0.6
-0.6
14.0
14.0
35
15
15
450
0.3
0.3
5.0
CCB

1.0
-1.0

80
40
30
550
0.5
0.5
10.0
10.0
CCB

Doubll Metal •
Max.
Min.
0.6
-0.6
14.0
14.0
35
15
15
450
0.3
0.3
5.0

CCD

1.0
-1.0
-

80
40
30
550
0.5
0.5
10.0
10.0
CCD

Comments
N'Channel Threshold (Volts)
P·Channel Threshold (Volts)
Poly Field Threshold (Volts)
Drain·Source Breakdown (Volts)
Diffusion Resistivity Q/D
Diffusion Resistivity Q/D
Poly Resistivity, Q/D (All Poly is N+ )
Gate Oxide Thickness, In Angstroms
Junction Depth, In fl
Junction Depth, In fl
In Volts
In Volts

15
35
15
750
1.2"
1.5"
2.2

CVD

35
80
45
850

13.2
13.2
CVD

7
7
15
35
15
750
1.2"
1.5"
1.5

CVC

35
80
45
850

5.5
5.5
CVC

Comments
N'Channel Threshold 50 x 5fl Device
(Volts)
p·Channel Threshold 50 x 5fl Device
(Volts)
Poly Field Threshold (Volts)
Drain·Source Breakdown (Volts)
Diffusion Resistivity Q/D
Diffusion Resistivity Q/D
Poly Resistivity Q/D (All poly is N+ )
Gate Oxide Thickness, In Angstroms
Junction Depth, In fl
Junction Depth, In fl
In Volts
In Volts

MOS Processes
6 & 5 Micron SIGate NMOS Process Parameters
6 Micron
Low VT

5 Micron
16.67/Procell
Shrink

HlghVT

Parameter

Min.

Max.

Min.

Max.

Min.

MIx.

Min.

Max.

VTE

1.0

0.8

1.2

.75

1.25

0.6

1.0

VTO

-3.0

-4.0

-2.5

-3.5

- 2.5

-3.5

-2.5

-3.5

VTN

- .2

-.2

VTDO
VTF

-4.35

-3.65

Bvoss
ROIFF
RpOLY
Tox
Xj
Operating Voltage

13
14

12
14

30
14

Extrapolated Enhancement Threshold on a 50 x 61' Transistor (Volts)
Extrapolated Depletion Threshold on a 50 x 501' Transistor (Volts)
Intrinsic Device Threshold 50 x 6).1 Transistor (Volts)
Deep Depletion Threshold (Volts)
Poly Field Threshold (Volts)
Drain-Source Breakdown on 50 x 501' Transistor

N+ Region Resistivity Q/O
N+ Doped Poly Resistivity Q/O

1000
1.2

1150

1000

1150

750

850

750

850

Gate Dxide Thickness, In Angstroms

1.6
12

1.2

1.6
12

0.8
5

1.2
12

0.8
5

1.2
12

Junction Depth, In I'
In Volts

Max Rating
Process DeSignator

Comments

13.2
NVC

13.2

NVC

13.2

NVD

NVS

13.2

In Volts

NEA/NEC

NVS

NMOS I & NMOS II Process Parameters
NMOS I

NMOS II

4VT

Std.

4VT

Parameter

Min.

MIx.

Min.

Max.

Min.

Max.

Min.

Max.

VTE

0.6

1.0

0.6

1.0

0.6

1.0

0.6

1.0

-3.5
N/A

-2.5
N/A

-3.5
-0.15

- 2.5

-3.5

-2.5

Extrapolated Threshold 50 x 501' Device (Volts)

N/A

N/A
N/A

Extrapolated Threshold 50 x 61' Device (Volts)

-4.85

+0.15
-4.15

Poly Field Threshold (Volts)

VTD

-3.5

-2.5

VTN

-0.15

+0.15

VTOO

-4.35

N/A
7.5

N/A
-

7.5

VTF

7.5

-3.65
-

Bvoss

7.5

7.5
7.5

N/A

7.5
7.5

50
750

20
450

Tox

20
650

20
450

Xj
Operating Voltage

0.3

0.5
5/12
5.5/13.2
NDD

ROIFF
RpOLY

Max Rating

Process DeSignator

NDD

650
0.3

0.5
5/12
5.5/13.2
NDE

NDE

0.3

550
0.5

Extrapolated Enhancement Threshold Voltage on a 50 x 41'
Transistor (41' Processes)
or 50 x 31' Transistor (31' Processes) (Volts)

Extrapolated Threshold 50 x 501' Device (Volts)
Punch Through Voltage 50 x 41' Device (41' Processes)
or 50 x 31' Device (31' Processes) (Volts)
Diffusion Resistivity Q/O

30
40

Poly Resistivity Q/O
Gate Oxide Thickness, In Angstroms

550

0.3
-

Comments

0.5

N+ Junction Depth, In I'
In Volts

5.5

NCC

NCA

In Volts

7.5 Micron Metal Gate PMOS Process Parameters

oImplant
Parameter

High VT
Min.
Max.

1 Implant

Med VT
Min.
Max.

2 Implant

Low VT
Min.

Max.

Min.

Max.

Min.

Max.

VTE

-3.25

-4.95

-2.8

-4.2

-1.8

-2.5

-1.0

-1.8

-1.2

-2.0

VTO

N/A

5.0

N/A
-

4.0

VTF

N/A
-

Bvoss

RDiFF
los/mA
BVOXG
XjJ
Process Designator

30
1.25

2.55

0.8

120

17
PMC

1.9
PMC

80
1.7

2.2
1.9
PMT

PMT

0.8

2.0
1.9
PMD

2.8

100
1.7
PMD

90
1.7
PNR

60
4.0

19
PNR

30
2

60
4

90
1.7
POG

1.9
POG

Comments
los= 11'A
Depletion Measurement on a 501' Transistor (Volts)
Field Threshold (Volts)
Drain-Source Breakdown (Volts)
Sheet Resistivity Q/O
Drain-Source Current (mA)
Gate Oxide Breakdown (Volts)
Junction Depth, In I'

MOS Processes
CMOS II Process Parameters (N-Well)

Parameter
VTN
VTP
VTF
Bvoss
ROIFF P+
N+
Tox
Xj
P+
N+
Operating Voltage
Max Rating
Process Designator

Single Metal
Min.
Max.
0.6
-0.6
15
15
50
15
390
0.3
0.3

1.0
-1.0

100
40
460
0.5
0.5
10
9
11
CCN/CCO

Double Metal
MIx.
Min.
1.0
-1.0

0.6
-:0.6
+15
+15
50
15
390
0.3
0.3

100
40
460
0.5
0.5
10
11
CCP

Comments
N-Channel Threshold Voltage (Volts)
P-Channel Threshold Voltage (Volts)
Poly Field Threshold (Volts)
Drain-Source Breakdown (Volts)
Dilfusion Resistivity Q/O
Diffusion Resistivity Q/O
Gate Oxide Thickness, In Angstroms
Junction Depth, In I"
Jun.ction Depth, In I"
In Volts
In Volts
In Volts

~1~ll~~~~~
."""'4.
~

A Subsidiary
of Gould Inc.

Product Assurance Program
Introduction
Quality is one of the most· used, least understood, and
variously defined assets of the semiconductor industry. At
AMI we have always known just how important effective
quality assurance, quality control, and reliability monitor·
ing are in the ability to deliver a repeatably reliable product.
Particularly, through the manufacture of custom MOS/LSI,
experience has proved that one of the most important
tasks of quality assurance is the effective control and
monitoring of manufacturing processes. Such control and
monitoring has a twofold purpose: to assure a conSistently
good product, and to assure that the product can be
manufactured at a later date with the same degree of
reliability.
To effectively achieve these objectives, AMI has developed
a Product Assurance Program consisting of three major
functions:
• Quality Control
• Quality Assurance
• Reliability
Each function has a different area of concern, but all share
the responsibility for a reliable product.

The AMI Product Assurance Program
The program is based on MIL·STD·883, MIL·M·38510, and
MIL·Q·9858A methods. Under this program, AMI manufac·
tures highest quality MOS devices for all segments of the
commercial and industrial market and, under special adap·
tations of the basic program, also manufactures high
reliability devices to full military specifications for specific
customers.
The three aspects of the AMI Product Assurance Pro·
gram-Quality Control, Quality Assurance, and Reliabil·
ity-have been developed as a result of many years of
experience in MOS device design and manufacture.
Quality Control establishes that every method meets or
fails to meet, processing or production standards-QC
checks methods.
Quality Assurance establishes that every method meets, or
fails to meet, product parameters-QA checks results.
Reliability establishes that QA and QC are effec·
tive- Reliability checks device performance.
One indication that the AMI Product Assurance Program
has been effective is that NASA has endorsed AMI pro·
ducts for flight quality hardware since 1967. The Lunar
Landers and Mars Landers all have incorporated AMI cir·
cuits, and AMI circuits have also been utilized in the Viking
and Vinson programs, as well as many other military air·
borne and reconnaissance hardware programs.

Quality Control
The Quality Control function in AMI's Product Assurance
Program involves constant monitoring of all aspects of
materials and production, starting with the raw materials
purchased, through all processing steps, to device ship·

ment. There are three major areas of Quality Control:
• Incoming Materials Control
• Microlithography Control
• Process/Assembly Control

Incoming Materials Control
All purchased materials, including raw silicon, are checked
carefully to various test and sampling plans. The purpose
of incoming materials inspection is to ensure that all items
required for the production of AMI MOS circuits meet such
standards as are required for the production of high quali·
ty, high reliability devices.
Incoming inspection is performed to specifications agreed
to by suppliers of all materials. The Quality Control group
continuously analyzes supplier performance, performs
comparative analysis of different suppliers, and qualifies
the suppliers.
Tests are performed on all direct material, Including
packages, wire, lids, eutectics, and lead frames. These
tests are performed using a basic sampling plan in accor·
dance with MIL·S·19500, generally to a Lot Tolerance Per·
cent Defective (LTPD) level of 10%. The AQL must be
below 1% overall.
Two incoming material inspection sequences illustrate the
thoroughness of AMI Quality Control:
•

Purchased packages are first inspected visually. Then,
dimensional inspections are performed, followed by a
full functional inspection, which subjects the
packages to an entire production run simulation. Final·
Iy, a full electrical evaluation is made, including
checks of the Insulation, reSistance, and lead·to·lead
isolation. A package lot which passes these tests to an
acceptable LTPD level is accepted.
Raw silicon must also pass visual and dimensional
checks. In addition, a preferential etch quality inspec·
tion is performed. For this inspection, the underlayers
of bulk silicon are examined for potential anomalies
such as dislocation, slippage or etch pits. Resistivity
of the silicon is also tested.

Microlithography Control
Microlithography involves the processes which result in
finished working plates, used for the fabrication of wafers.
These processes are pattern or artwork generation, photoreduction, and the actual printing of the working plates.
Pattern generation now is the most common practice at
AMI. The circuit layout is digitized and stored on a tape,
which then is read into an automated pattern generator
which prints a highly accurate 10x reticle directly.
In cases where the more traditional method of artwork
generation is used whether Rubylith, Gerber Plots, AMI
generat~d or customer generated-the artwork is
thoroughly inspected. It is checked for level·to·level
registration and dimensional tolerances. Also, a close
visual inspection of the workmanship is made. AMI artwork
is usually produced at 200x magnification and must con·

Product Assurance Program
form to stringent design rules, which have been developed
over a period of years as part of the process control requirements.
Acceptable artwork is photographically reduced to a 20x
magnification, and then further to a 10x magnification. The
resulting 10x reticles are then used for producing 1x
masters. The masters undergo severe registration comparisons to a registration master and all dimensions are
checked to insure that reductions have been precise. During this step, image and geometry are scrutinized for missing or faded portions and other possible photographic
omissions.
For a typical N-Channel silicon gate device, master sets
are checked at all six geometry levels in various combinations against each other and against a proven master set.
Allowable deviations within the die are limited to 0.5
micron, deviations within a plate are limited to 1 micron,
and all plate deviations are considered cumulatively.
Upon successful completion of a device master set, it is
released to manufacturing where the 1x plates are printed.
A sample inspection is performed by manufacturing on
each 30-plate lot and the entire lot is returned to Quality
Control for final acceptance. Quality Control performs
audits on each manufacturing inspector daily, by sample
inspection techniques.
The plates can De rejected first by manufacturing when the
30-plate lots are inspected, or by Quality Control when the
lots are submitted for final acceptance. If either group rejects the plates, they are rescreened and then undergo the
same inspection sequence. In the rescreening process, the
plates undergo registration checks; visual checks for pin
holes, protrusions, and faded or missing images, as well as
all critical dimension checks.

Process Control
Once device production has started in manufacturing, AMI
Quality Control becomes involved in one of the most important aspects of the Product Assurance Program-the
analysis and monitoring of virtually all production processes, equipment, and devices.
Process controls are performed in the fabrication area, by
the Quality Control Fabrication Group, to assure
adherence to specifications. This involves checks on
operators, equipment and environment. Operators are
tested for familiarity with equipment and adherence to procedure. Equipment is closely checked both through
calibration and maintenance audits. Environmental control
involves close monitoring of temperature, relative humidity, water resistivity and bacteria content, as well as particle
content in ambient air. All parameters are accurately controlled to minimize the possibility of contamination or
adverse effects due to temperature or humidity excesses.
Experience has proven that such close control of the
operators, equipment, and environment is highly effective
towards improved quality and increased yields.
In addition to the specification adherence activities of the

Figure 1. Flowchart of Product Assurance
Program Implementation

1-+--- ac INSPECTION

PHOTO SUPPORT
ac INSPECTION

ac FAB INSPECTION
ac LAB MONITORS

1-+--- ac INSPECTION

ASSEMBLY
SCRIBE/BREAK
1ST OPTICAL
DIE ATTACH
BOND 2ND
OPTICAL SEAL
~--r------I

l~"·"·"'""

H----

ac INSPECTION

1-+--- MANUFACTURING

aA ACCEPTANCE
PROGRAM VERIFICATION
VISUAL/ MECHANICAL
TESTING
FUNCTIONAL TESTING
PARAMETRIC TESTING
TEMPERATURE TESTING

....- - - aA INSPECTION

SHIP

Product Assurance Program
QC Fabrication Group, A QC Laboratory performs constant
process monitoring of virtually every step of all processes.
Specimens are taken from all production steps and critical·
Iy evaluated. Sampling frequency varies, depending on the
process, but generally, oxidation, diffusion, masking and
evaporization are the most closely monitored steps.
Results are supplied both to manufacturing and engi·
neering. When evidence of a problem occurs, QC provides
recommendations for corrections and follows up the
corrective action taken.
Optical Inspections are performed at several steps; quality
control limits are based on a 10% LTPD. The chart in
Figure 1 shows process steps and process control points.

Quality Assurance
The Quality Assurance function in the Product Assurance
Program involves checking the ability of manufactured
parts to meet specifications. In addition, the QA group also
is responsible for calibration of all equipment, and for the
maintenance of AMI internal product specifications, to
assure that they are always in conformance with customer
specifications or otherAMI specifications.
After devices undergo 100% testing in manufacturing, they
are sent to Quality Assurance for acceptance. Lots are
defined, and using the product specifications, sample
sizes are determined, along with the types of tests to be
performed and the test equipment to be used. Lots must
pass QA testing to a 0.04% AQL.
Three types of tests are performed on the samples:
visual/mechanical, parametric, and functional. All tests are
performed both at room temperature and at elevated
temperature. In addition, a number of other special temper·
ature tests may be performed if required by the specifica·
tion.
To perform the tests, QA uses AMI PAFT test systems,
ROM test systems, Macrodata testers, Fairchild Sentry,
LTX Sentinel, XINCOM systems, Teradyne test systems,
and various bench test units. In special instances a part
may also be tested in a real life environment in the equip·
ment which is to finally utilize it.
If a lot is rejected during QA testing, it is returned to the
production source for an electrical rescreening. It is then
returned to QA for acceptance but is identified as a resub·
mitted lot. If it fails again, corrective action in engineering
is initiated. As evidence of the problem is detected, the
parts may also be traced all the way back to the wafer run
to analyze the cause.
When a lot is acceptable, it is sent to packaging and then
to finished goods. When parts leave finished goods, they
are again checked by the QA group to a 10% LTPD with
visual/mechanical tests. Also, all supporting documenta·
tion for the parts is verified, including QA acceptance,
special customer speCifications, certificates of com·
pliance, etc. Only after this last check are devices con·
sidered ready for plant clearance.

If there are customer returns, they are first sample tested
by QA to determine the cause of the return. (Many times an
invalid customer test will incorrectly cause returns.)
Selected return samples are sent to Reliability for failure
analysis.

Reliability
The Reliability function in the Product Assurance Program
involves process qualification, device qualification,
package qualification, reliability program qualification and
failure analysis. To perform these functions AMI Reliability
group is organized into two major areas:
• Reliability Laboratory
• Failure Analysis

Reliability Laboratory
AMI Reliability Laboratory is responsible for the following
functions.
• New Process Qualification
• Process Change Qualification
• Process Monitoring
• New Device Qualification
• Device Change Qualification
• New Package Qualification
• Device Monitoring
• Package Change Qualification
• Package Monitoring
• High Reliability Pro'grams
There are various C~OSeIY interrelated and interactive
phases involved in t e development of a new process,
device, package or reliability program. A process change
may affect device performance, a device change may affect
process repeatability, and a package change may affect
both device performance and process repeatability. To be
effective, the Reliability Laboratory must monitor and
analyze all aspects of new or changed processes, devices,
and packages. It must be determined what the final effect
is on product reliability, and then evaluate the merits of the
innovation or change.
Process Qualification
For example, AMI Research and Development group
recommends a new process or process alteration when it
feels that the change can result in product improvement.
The Reliability Laboratory then performs appropriate
environmental and electrical evaluations of a new process.
Typically, a special test vehicle, or "rei chip", generated by
R&D during process development, is used to qualify the
recommended new process or process change.
The rei chip is composed of circuit elements similar to
those that may be required under worst· case circuit design
conditions. The rei chip elements are standard for any
given process, and thus allow precise comparisons bet·
ween diffusion runs. The following is an example of what is
included on a typical rei chip:
• A discrete inverter and an MOS capacitor

Product Assurance Program
• A large peN junction covered by an MOS
capacitor.
• A large peN junction area (identical to the junction area above, but without the MOS capacitor)
• A large area MOS capacitor over substrate
• Several long contact strings with ·different contact geometries
• Several long conductor geometries, which cross
a series of eight deeply etched areas
Each circuit element of a rei chip allows a specific test to
be performed. As an example, the discrete inverter and
MOS load device accommodate power life tests. As a consequence, any type of parameter drift can be observed. The
MOS capacitor, covering the large peN junction, can serve
to indicate the presence of contamination in the oxide,
under the oxide, or in the bulk silicon. If unusual drift is
evidenced, the location of contamination can be determined through analysis of the additional MOS capacitor
and the large peN junction area. The metal conductor interconnecting contacts is useful for life testing under
relatively high current conditions. It facilitates the detection of metal separation when moisture or other contaminants are present.
The conductors crossing deeply etched areas allow the
checking of process control. Rather than depending upon
optical inspection of metal quality, burned out areas caused by high currents are readily identified and provide a
quantitative measure of metal quality.
If the Reliability Laboratory determines that a recommended new process or process change is viable for
manufacturing purposes, further analysis is necessary to
determine that production devices can be manufactured in
high volume, in a repeatable and reliable manner.

Process Monitoring
In addition to process qualification, the Reliability group
also conducts ongoing process monitoring programs.
Once every 90 days each major production process is eval-

uated using rei chips as test vehicles. The resulting test
data is analyzed for parameter limits and process stability.
In this manner AMI can help assure repeatability and high
product quality.

Package Qualifications
New packages are also qualified before they are adopted.
To analyze packages, a qualification matrix is designed,
according to which the new package and an established
package (used for control) are tested concurrently. The test
matrix consists of a full spectrum of electrical and environmental stress tests, in accordance with MIL-STD-883.
Failure Analysis
Another important function of the Reliability group is
failure analysis. Scanning electron microscopes, high
power optical microscopes, diagnostic probe stations, and
other'equipment is used in failure analysis of devices submitted from various sources. It is the function of the
Reliability group to determine the cause of failure and
recommend corrective action.
The Reliability group provides a failure analysis service for
the previously mentioned in-house programs and for the
evaluation of customer returns. All AMI customers are provided a failure analysis service for any part that fails within
one year from date of purchase and the results of the analysis are returned in the form of a written report.

Summary
The Product Assurance Program at AMI is oriented
towards process control and monitoring, and the evaluation of devices. The Program consists of three major functions: Quality Control, Quality Assurance, and Reliability.
Constant monitoring of all phases of production, with
information feedback at all levels, allows fast and efficient
detection of problems, evaluation and analYSiS, correction,
and verification of the correction. The overall result is a line
of products which are highly repeatable and reliable, with a
very low reject level.

Packaging
Introduction
Plastic Packages
AMI is excelling in the use of transfer molding of plastic packages. All of our plastic packages are produced by mounting
the die on a lead frame, gold wire bonding, transfer molding and tin plating the external leads. Many of. the packages
utilize a copper leadframe which combines low cost with high heat dissipation characteristics. We are proud of our
plastic packaging capabilities.

Plastic Package
The AMI plastic dual-in-line package is the equivalent of
the widely accepted industry standard, refined by AMI for
MOS/LSI applications. The package consists of a plastic
body, transfer-molded directly onto the assembled lead
frame and die. The lead frame is copper alloy, with external
pins tin plated. Internally, there is a 150J..dn. silver spot on
the die attach pad and on each bonding fingertip. Gold bonding wire is attached with the thermosonic gold ball bonding technique.
Materials of the lead frame, the package body, and the die
attach are all closely matched in thermal expansion coefficients, to provide optimum response to various thermal
conditions. During manufacture every step of the process
is rigorously monitored to assure maximum quality of the
AMI plastic package.
Available in: 8, 14, 16, 18, 22, 24, 28, 40, 48 and 64 pin
configurations.

B.19

GOLD BONDING WIRE

Packaging
Plastic Chip Carrier
As in the ceramic chip carrier, the plastic chip carrier
(P.C.C.) provides excellent packaging density for high pin
count packages, but is an excellent cost alternative to ceramic. The P.C.C. is both surface and socket mountable,
and has high lead strengths.

As all AMI plastic packages, it is transfer molded and
thermosonically wire bonded. Die is mounted on a copper
lead frame and extenal leads are tin plated.
Available in: 44, 68 and 84 pin configurations.

BODY

Mini-Flatpack
The mini-flatpack is a cost effective, transfer molded It is processed with a lead frame of alloy 42 gold thermoplastic package that provides high package density, sur- sonic wire bonding, and tin plated external leads.
face mounting capabilities. It is a four sided alternative to Available in 18,22,24,28,40,44 and 80 pin configurations.
the plastic dual-in-line package provided by AMI.

TIN
PLATING

8.20

Packaging

GOLD
WIRE
BOND

S.O.l.c.

DIE

The small outline integrated circuit (s.o.l.e) package is
another of the low cost plastic packages in the AMI reper·
toire. Utilizing the dual-in-line configuration, a small dense,
surface mountable package is originated, which maximizes the use of board space.
Available in: 16 and 28 pin configurations.

TIN
PLATING

Pin Grid Array
Built on the same concept as the ceramic side brazed
package, the Pin Grid Array is also suitable for high
reliability applications but provides the opportunity for
high density packaging with very high pin counts. The unique lead design makes it compatible with socket insertion
mounting.
Most commonly supplied with an AI 2 0 3 ceramic body, gold
plating on the lead and die cavity, and sealed with a goldtin eutectic solder on a Kovar/alloy 42 lead.
Available in: 68, 84, 100, 144 pin configurations.

GOLD PLATE

8.21

COPPER
LEADFRAME

Packaging
Introduction
Ceramic Packages
The ceramic and cerdip packages provided by AMI are commonly used for high reliability applications. Glass or solder
eutectic sealing and ceramic body yields excellent hermeticity characteristics, thereby insuring against device failure
from moisture penetration. AMI supplies a full range of ceramic packages to meet many applications.

KOVAR OR
CERAMIC L10

Ceramic Package
Industry standard high performance, high reliability
package, made of three layers of AI 20 3 ceramic and nickel·
plated rtdfractory metal. Either a low temperature glass
sealed ceramic lid or a gold tin eutectic sealed Kovar lid is
used to form the hermetic cavity of this package. Package
le~ds are available with gold or tin plating for socket insertion or soldering.
Available in 14, 16, 18, 22, 24, 28 40 and 64 pin
configurations.

Cerdip Package
The Cerdip dual-in-line package has the same high performancecharacteristics as the standard three-layer ceramic
package yet is a cost-effective alternative. It is a military
approved type package with excellent reliability
characteristics.
The package consists of an Alumina (A1 20 3 base and the
same material lid, hermetically fused onto the base with
low temperature solder glass.
Available in 14, 16, 18, 20, 22, 24, 28 and 40 pin
configurations.

8.22

BOND
WIRES

Packaging

Chip Carrier Package
Chip carriers are the new industry standard in reducing
package size. Built on the same concept as the highly
reliable side-braze ceramic package, it is made of three
layers of AL 20 3 ceramic, refractory metallization and gold
plating. The chip carrier also offers contact pads equally
spaced on all four sides of the carrier resulting in increased package denSity, better electrical characteristics, and a
more cost effective way of packaging IC devices.
The package comes with a gold tin eutectic sealed metal lid
or the low cost glass sealed ceramic lid creating a standard
hermetic cavity.
Available in 20, 24, 28, 40, 44,68 and 84 LD standard 3-layer
versions and 24, 28, 44 LD slam style on 50 mil center lines
to the JEDEC standards.

a-Pin Plastic

GOLD PlA TED SEAL RING
IOPTIONAL)

~~?n@~~

14-Pin Plastic

0.100TYP -=0.020
0.0 15

L-

.100 MIN

8----.

~'065
0.040.

0.020 MIN

j TYP
0.100

0.400 MAX
4_

Llg:;~g

0.310
0.
2901

100 MIN

BEND

15° MAXJb

0.795 MAX

0.065'
0.040 TYP
I

~ 1~2U
~~

J~-I--J.f-

0020
MIN
.

jR~

='~.

0.020
0.015

J l l . 0 . 2 0 0 MAX

1\:0

PIN 1 IDENTIFIER

PIN 11DENTIFIERb

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1
I----t--I 0.280
0.220

8 E N D t : [ - 0.310
O~

,R'
150MAx,J~'1 11'\
I

JLO.012
0.008

0.012

I-- --If-.. 0008

8.23

TVP

Packaging
14-Pin Ceramic

16-Pin Plastic
PIN 1 IDENTIFIER

"~= ~--Pl-"'-':~l-~-"g' :~;gi:

.065·,040

_____---'T---'---"'-'.L--"-_
7

0.020
0.015

1'='-+--...1--

1.'95.

,020IllN.-II-

.100

~IN J~~=0'200

1-'' ' -1

I--

DII----!I

MAX

0,020 MIN

BEND

J~~
WMAXJL
16-Pin Cerdip

JL:m

15"MAX

R
I

'--.. ./ f--

.280 MAX
.220
MIN
310 MAX
290 MIN

:~6~

---ii-0,01O TYP

16-Pin Ceramic

PIN 1 IDENTIFIER

PIN 1 IDENTIFIER
MARKINGS

---'11

16 /""

S~~F~~E
ONLY

0.810 MAX.
I

0.020

0f=JF'.~:~"iif
.100 MIN.

Jf-I

0.200 MAX.
0.020 MIN.

BEND

L-l+ ~:m

0.310
, 0.290

/L JL'

15' MAX.

'----I'

18-Pin Ceramic

16-Lead Plastic S.O.l.C.

PIN l l D E N T I F I E R h

.030R •
•011 MAX.

.050 TYP.

.41, 0
MAX.

r . _I

.004MI~

DEPTH

'025j~'005 -1
.018 TYP• ..----

0.012
0.008

~ ~ .098 MAX.
.104 MAX.

[]

0065
0040

0200 MAX
.

.335 MIN.
.351 MAX·l

0.295
0.275

Ir-1
r-ll

0 310
.
0.290

,0~'c=~=r
MAX.

.025xW ~r

MARKINGS
ON LID
SURFACE
ONLY

0920 MAX

L.299 MAX.J I
.402 MIN. _
.410 MAX.

15'MAX~L

.010 REF.

8.24

JLO.012
0.008

Packaging
18-Pin Cerdip

18-Pln Plastic

PIN 1 IDENTIFIER

.038 MAX
.026 MIN
.020 MAX
.015 MIN

L-

100:J~0'200

MAX

I--0.Q20 MIN

BEND

.310 MAX
290 MIN

R
15'MAXJ

18-Lead Mini-Fiat Pack

.012 MAX

f- -If- .008 MIN

20-Lead Chip Carrier

...

.054
11.676<1

"'C'"
0',15"
BEND LINE

020 x 45'
--H-(:5080X4S0)

~-L-"TTTnr---'-'rrn'------!il~MAX
.

040 x 45' 3 PlC'S
(':0160 x 45° 3 PLC'S)

5'TOPIBTM-oy"

.090 MIl

.010 REF
.082 ~ :~~:

20-Pin Plastic

22-Pin Plastic
PIN 1 IDENTIFIER

B.25

Packaging
22·Pln Ceramic

22·Pln Cerdlp

PIN 1 IDENTIFIER
PIN 1 IDENTIFIER

22
MARKINGS
DN LID
SURFACE
ONLY

i~l'

0015

rIn- 0200

l00:J
1-. 0.410-1
0.390 I

0015MIN

0.008

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MARKINGS ON LID
SURFACE ONLY

:Ii:li

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......
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ii
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"
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50
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'(3 PLCS)

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- .005

BENDi°,410i
0 390

WMAX' - /

PIN 1 IDENTIFIER

""d

L- g~~~ ~

/~ Jl"

JLO.012

22-Lead Mini-Flat Pack

.020 RAD

MAX

I-

A~
15°MAX""

:Ii:li :Ii

~~ ~~~

B.26

Packaging
24-Lead Mini-Fiat Pack

24-Pln Ceramic

PIN 1 IDENTIFIER

.012 RAD

(3 PleS)

MARKINGS
ON LID
SURFACE
ONLY

7l=".+-'----'---"12'-':-_ _~'3

0.020 MIN

=:5 =;1
50
ss ss
'''~.
TOP. IBTM1r Ii:;g ~
TOP
I BTM
111\\

l;;.
""""
'":'":

.:.
.082 _+ :~~:

15' MAX

.010 REF

24-Pin Cerdip

24-Pin Plastic

PIN 1 IDENTIFIER

-T'l
:::'"'1'''

.m.
0015

+==

100 MIN

015 MIN

JJjEJ:o
I-

12~

200 MAX

LO.590J
0.480

BENDlg~~g I

,1E31

WMA0~

jlg~~

B.27

JLO.012
0.008

Packaging
28·Lead Plastic Mlnl·Flat Package

28·Pln Ceramic

PlN1IOENTIFlER
28

MARKINGS

ONLIO

SURFACE
ONLY

L-- __
.100

.020
.011

,~]

IL-.20DMAX.

--l.02DMIN.

28·Pin Plastic

28·Lead Plastic S.O.l.C.

.050

:ru

.016 TYP'

':7MA~

0040

0020
0015

l00:]¥ 0200 MAX
0020 MIN

I-

LO.58sJ

BENDtg:~=J
0.515

!-.335MII'j
.025 x 45]t"1 MAX. \ iL

AC=Jt,I

'S'MAX / I

......; I--

~10REF.

---4- 0012
0.008

8.28

MAX.

.04&.-1
REF•

Packaging
28-Pln Cerdip

28-Lead Chip Carrier

PIN 1 IDENTIFIER

460

(11~~;0):=J

(11.3030)

008 R. 28 PLC'S
(:2032 R. 28 PLC'S)
.025 TYP
.050 TYP
.6350 TYP
(1.2700 TYP) __

066
054
(1.3716)
(1.6764)

-I

~(~~~O\4~~.)]
I~L

100.1
MAX

II+-

0.020
0.Q15

fJ{l
L

.100MIN
0.Q15 MIN

LO.590J
0.480
0.61018END

~E3,

0'590

0.200 MAX

JL'

/1
"'-I I---

15"MAX

0.012
0.008

36-Lead Ceramic Chip Carrier

40-Pin Ceramic
PIN lIDENTIFIER\

--~

~ r l 1,1
065 ± .010

.550 ± .015 SQ':1

631
--l-

.020 x 45° '" REF.
.050: TYP .. 040 x 450
TYP.
.025
3 PLACES

PIN
IDfNllncR

MARKINGS
ON LID
SURFACE
ONLY

I
2,060 MAX

36009R.
PLACES

I
I

,610 _~
i-0,590

j
I

15' MAX '''/

B.29

i--!

0,012
0.008

Packaging

40-Lead Chip Carrier

+.010
.480 SO. _ .003
(121920

so ~~~ig)

-\ h

-.. I

ll--

020 R404bL~L~S)
(.5080
012 R 3 PLCS
008 R 40 PLCS
(3048 R 3 PLCS)
(2032 R 40 PLCS)
100
~

065 ± 008
(16510 ± 2032)

-MAX

..-....n'fMliOuuuu,n'

~~
,":~ '~ ER

Packaging
44-Lead Mini-Flat Pack

44-Lead Plastic Chip Carrier

44-Lead Pin P.C.C. Outline

TOP VIEW

=iE

BOTTOM VIEW

['. ' 'os']

.045

lElE

"''''
"",.

'-j

",."
NO

",."

.015

. ~L

"-1

.015

.650 + .010 SQ.J
- .000
LEAD THICKNESS

m
L.500 ±.005
SQ.

.050 '± .003

010 INT HAD

.•"' ...'m.~. . .
.170 ±

.~~.027INT. HAD.
1 .02'6 TYP.

~ .616 ± .020S·018 ± .003 TYP.

-J L.028 ± .003 TYP.

48-Lead Ceramic

52-Lead Chip Carrier

.590;. 010
.018~TYP.

"PIN 1

.020

.065 ± .010

IDENTIFIER

[.750 ± .015SQ"]

.0401.050
TYP.

B.31

(

x 45° '" REF •
.050'" TYP.
.025 --j r·040 x 45°
TYP. I
3 PLACES

PIN 1

10ENTlRER

.008 R.
52 PLACES

Packaging
64-Pln Ceramic

64-Pln Plastic
.015
.020
_t_ _

1.... 1..-.
-

-t-

.'OOMIN.
020 MIN.

.040 MIN
.060 MAX

-tPIN SPACING 0.100 T.P

(SeeN'leA1L

3.400 MAX.

lttoI_

1:==--! _ _...---'_-,,3~2_~_ _...., 33

.100 MIN .....I ...

1-----1:m ~fNX(l)

MIN

.210MAX_

.920 MAX

-.890 MIN -

~t:J50

.-!\\_.008-.012

TOP VIEW

BonOMVIEW

[""':]

~rt:4~~~~~ l

ffi(:t1{OT(OTBf~~~7{fJ1 K

["045

H.t1_-$. ~

.045

'-i

C
B
./'

INDEX MA RK~./

.0 19 ".

L-~~~3~4~5~6~7~8~9~1~0~ldlA
_I

-I M~
i!=W
If I .075 ± .010
~ ~ ~ ~ ~ ~ ~ tr=ii1~~.170 ± .010
- .030

MAX.

68-Lead Plastic Chip Carrier

68-Pin Grid Array

r1.098SU. ± .015

1--·890 .. 910--!
I
I

NOTE A. Each pin cenll!rtinl! is localed wilhin 0.010 01 ils trut IOnglludlnalpositlon

W MAX_I

-1

NOTE: (1) DIMENSION DOES NOT INCLUDE FLASH

1--.820 .. 880

.... 200 MAX.

IBEND LINE

.080 DIA
(73 PlCS)

L.BOO ± .005 SQ.J

.018 ± .003

.~~:D±T~::lH~~~\
.170 l.0051

--, r.050 ± .003 TYP.

~ I-.026 TYP.

B.32

.010 IHT. HAD•

'i"OUlf1)gfu~027

IHT. HAD.

917 + 020 ---,-,-, ... 018 ± .003 TYP.
•
_.
-n-.02B ± .003 TYP.

5~
-II-+-

.008
.012

Packaging
S8-Lead Chip Carrier

950

080

so ~g~8

(24.1300

•

S8-Lead Mini-Fiat Pack

~~~!g)

± .008

.050 TYP

'0!3~~~1D-Clliill[!jj~~liill[lllilfrill:~"'ii~~_:_~_X

.025 TYP

1'l:~1[tn:n:lt:I1ftjt'-:~W

NON·ACTIVE
PIN 1 IDENTIFIER

L._~mmf1mmm'mmlr"l---~
/.012 R
(3 PLCS)

l
~

.124 MAX
.100 MIN

7°
TOP & BTM

.010REF

0°-1;7

~ :~~~

.079

84-Pin Grid Array Outline

.097 MAX
.090 MIN .

84-Lead Plastic Chip Carrier
TOP VIEW

BOTTOM VIEW

1.100 SO ± .015

Qu.

~'1r-nnno+-............,
.018

PIN 1IHDlCATOR/

.. 01e

1.000 ± .005 SQ.

STANDOFF

~
.... L

Ip.." ....'"

nnnn nn
.060 DIA.

'1.150 + .010 SQ.
- .000
LEAD THICKNESS'
.008 ± .001 TYP\

± .01'

. 170

.020 ± .003

±; .OOS!
I

8.33

•

~.050 ± .003 TYP.

.010 INT. HAD•

\1buij;~!'OUU\ll10~.027
INT. RAD .
.01B
.003 TYP.
,

.026 TYP. ~ 1.117 ± .020 X;028 ± .003 TVP.

Packaging
84-Lead Chip Carrier

1OO-Pln Array Outline

1.080 MAX - - - - ,

PIN A11DENTIFYING
CORNER

PIN·':I~

IDENTIFIER

~----

LID

--L-~lmlQl:u:llllJJ:mrul.QrullJ.rum.:?
~)(4~'3PlCS

r· 019

(.0160)(45")

..JMA~
I

.080 + .010

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ .150 ;

.010

-11- .020 DIA ± .002

120-Pln Grid Array Outline

144-Pln Grid Array Outline

1.200 ± .014
.100

Du.

~lID

P
PIN 1 INDEX, /
[:"....

•... ±

PIN 1 INDICATOR- /
.019 MAX
.080 ± .010

PIN # 1

.,~

~ ~'~ ~~ n ~ ~ tr ~ ~
.030 REF. J .018 DIA ± .005

:=l

'U ~U U'lfij uUUUU UuU'=C;:

.080 DIA. TYP.

STANDOFF" .030
.170 ± .020

B.34

.018 DIA-H..
± .002

'\3
'- .080 DIA.

~ .170 ± .020

Ordering Information
Standard Products
Any product In this MOS Products Catalog can be ordered
using the simple system described below. With this system
it is possible to completely specify any standard device In
this catalog in a manner that is compatible with AMI's order
processing methods. The example below shows how this
ordering system works and will help you to order your parts
in a manner that can be expedited rapidly and accurately.
All orders (except those in sample quantities) are normally
shipped in plastic containers or aluminum tube containers,

which protect the devices from static electricity damage
under all normal handling conditions. Either container is
compatible with standard automatic IC handling equipment.
Any device described in this catalog Is an AMI Standard
Product. However, ROM devices that require mask preparation or programming to the requirements of a particular
user, devices that must be tested to other than AMI Quality
Assurance standard procedures, or other devices requiring
special masks are sold on a negotiated price basis.

~~@@®

~[P)

~~@@®~

r=J[p)
r=J [Q)

~®®@@
~®®~@@

c:::::J

~@~@~o®

r=J ~

~~@lJ~@

c:::::J

[Q)

~
"-..r-I

Package Type-a single letter designation which identifies
the basic package type. The letters are coded as follows:
P - Plastic package
0- Cerdip package
C - Ceramic (three-layer) package

Device Number- prefix S, followed by four (or five*) numeric digits that define the basic device type. Versions to the
basic d,evice are indicated by an additional alpha or numeric
digit as shown in the above examples.
*Organ Circuits

B.35

Terms of Sale
TERMS OF SALE
1. ACCePTANCE: THE TERMS OF SALE CONTAINED HEREIN APPLY TO ALL QUOTATIONS MADE
AND PURCHASE ORDERS ENTERED INTO BY THE SELLER. SOME OF THE TERMS SET OUT HERE
MAY DIFFER FROM THOSE IN BUYER'S PURCHASE ORDER AND SOME MAY BE NEW. THIS
ACCEPTANCE IS CONDITIONAL ON BUYER'S ASSENT TO THE TERMS SET OUT HERE IN LIEU OF
THOSE IN BUYER'S PURCHASE ORDER. SELLER'S FAILURE TO OBJECT TO PROVISIONS CON·
TAINED IN ANY COMMUNICATION FROM BUYER SHALL NOT BE DEEMED A WAIVER OF THE
PROVISIONS OF THIS ACCEPTANCE. ANY CHANGES IN THE TERMS CONTAINED HEREIN MUST
SPECIFICALLY BE AGREED TO IN WRITING BY AN OFFICER OF THE SELLER BEFORE BECOM·
ING BINDING ON EITHER THE SELLER OR THE BUYER. All orders or contracts must be approved
and accepted by the Seller at Its home office. These terms shall be applicable whether or not they are
attached to or enclosed with the products to be sold or sold hereunder. Prices for the Items called for
hereby are not subject to audit.
2. PAYMENT:
(a) Unless otherwise agreed, all Invoices are due and payable thirty (30) days from date of In·
voice. No discounts are authorized. Shipments, deliveries, and performance of work shall at all times
be subject to the approval of the Selle~s credit department and the Seller may at any time decline to
make any shipments or deliveries or perform any work except upon receipt of payment or upon terms
and conditions or security satisfactory to such department.
(b) If, In the judgment of the Seller, the financial condition of the Buyer at any time does not
Justify continuation of production or shipment on the terms of payment originally specified, the Seller
may require full or partial peyment In advance and, In the event of the benkruptcy or Insolvency of the
Buyer or In the event any proceeding Is brought by or against the Buyer under the bankruptcy or Insol·
vency laws, the Seller shall be entitled to cancel any order then outstanding and shall receive relm·
bursement for Its cancellation charges.
(c) Each shipment shall be considered a separate and Independent transaction, and peyment
therefore shall ba made accordingly. If shipments are delayed by the Buyer, payments shall become
due on the date when the Seller Is prepared to make shipment. If the work covered by the purchase
order is delayed by the Buyer, payments shall be made based on the purchase price and the percen·
tage of completion. Products held for the Buyer shall be at the risk and expense of the Buyer.
3. TAXES: Unless otherwise provided herein, the amount of any present or future sales, revenue, ex·
clse or other taxes, fees, or other charges of any nature, Imposed by any public authority, (national,
state, local or other) applicable to the products covered by this order, or the manufacture or sale thereof, shall ba added to the purchase price and shall be paid by the Buyer, or In lieu thereof, the Buyer
shall provide the Seller with a tax exemption certificate acceptable to the taxing authority.
4. F.O.B. POINT: All sales are made F.O.B. point of shipment. Selle~s title passes to Buyer, and
Selle~s liability as to delivery ceases upon making delivery of material purchased hereunder to carrier
at shipping pOint, the carrier acting as Buye~s agent. All claims for damages must be flied with the
carrier. Shipments will normally be made by Parcel Post, United Parcel Service (UPS), Air Express, or
Air Freight. Unless specific Instructions from Buyer specify which of the foregoing methods of shipment is to ba used, the Seller will exercise his own discretion.
5. DELIVERY: Shipping dates are approximate and are based upon prompt receipt from Buyer of all
necessary Information. In no event will Seller ba liable for any re-procurement costs, nor for delay or
non-delivery, due to causes beyond Its reasonable control Including, but not limited to, acts of God,
acts of civil or military authority, priorities, fires, strikes, lockouts, slow-downs, shortages, factory or
labor conditions, yield problems, and Inability due to causes beyond the Selle~s reasonable control to
obtain necessary labor, materials, or manufacturing facilities. In the event of any such delay, the date
of delivery shall, at the request of the Seller, be deferred for a period equal to the time lost by reason of
the delay.
In the event Selle~s production Is curtailed for any of the above reasons so that Seller cannot
deliver the full amount released hereunder, Seller may allocate production deliveries among Its
various customers then under contract for similar gOods. The allocation will be made In a commer·
clally fair and reasonable manner. When allocation has been made, Buyer will be notified of the
estimated quota made available.
6. PATENTS: The Buyer shall hold the Seller harmless against any expense or loss resulting from In·
frlngement of patents, trademarks, or unfair competition ariSing from compliance with .Buye~s
deSigns, specifications, or Instructions. The sale of products by the Seller does not convey any
license, by Impllcallon, estoppel, or otherwise, under patent claims covering combinations of said
products with other devices or elements.
Except as otherwise provided In the preceding paragraph, the Seller shall defend any suit or proceeding brought against the Buyer, so far as based on a claim that any product, or any part thereof,
fumlshed under this contract constitutes an Infringement of any patent of the United States, If noll·
fled promplly In writing and given authority, Information, and assistance (at the Selle~s expense) for
defense of same, and the Seller shall pay all damages and costs awarded therein against the Buyer. In
case said product, or any part thereof, Is, In such suit, held to constitute Infringement of patent, and
the use of said product Is enjoined, the Seller shall, at Its own expense, either procure for the Buyer
the right to continue using said product or part, replace same with non-Infringing product, modify It so
It becomes non-Infringing, or remove said product and refund the purchase price and the transportation and Installation costs thereof. In no event shall Selle~s total liability to the Buyer under or as a
result of compliance with the provisions of this paragraph exceed the aggregate sum paid by the
Buyer for the allegedly Infringing product. The foregoing states the enllre liability of the Seller for
patent Infringement by the said products or any part thereof. THIS PROVISION IS STATED IN LIEU OF
ANY OTHER EXPRESSED, IMPLIED, OR STATUTORY WARRANTY AGAINST INFRINGEMENT AND
SHALL BE THE SOLE AND EXCLUSIVE REMEDY FOR PATENT INFRINGEMENT OF ANY KIND.
7. INSPECTION: Unless otherwise specified and agreed upon, the material to be furnished under this
order shall be subject to the Selle~s standard Inspection at the place of manufacture. If It has been
agreed upon and specified In this order that Buyer Is to Inspect or provide for Inspection at place of
manufacture such Inspection shall be so conducted as to not Interfere unreasonably with Selle~s
operations and consequent approval or rejection shall be made before shipment of the material.
Notwithstanding the foregoing, If, upon receipt of such material by Buyer, the same shall appear not
to conform to the contract, the Buyer shall Immediately nollfy the Seller of such conditions and afford
the Seller a reasonable opportunity to Inspect the material. No material shall be retumed without
Selle~s consent. Selle~s Return Material Authorization form must accompany such retumed material.

8. LIMITED WARRANTY: The Seller warrants that the products to be delivered under this purchase
order will be free from defects In material and workmanship under normal use and service. Selle~s
obligations under this Warranty are limited to replacing or repel ring or giving credit for, at Its option, at
Its factory, any of said products which shall, within one (1) year after shipment, be retumed to the
Selle~s factory of Origin, transportation charges prepaid, and which are, after examination, disclosed
to the Selle~s satisfaction to be thus defective. THIS WARRANTY IS EXPRESSED IN LIEU OF ALL
OTHER WARRANTIES EXPRESSED, STATUTORY, OR IMPLIED, INCLUDING THE IMPLIED WAR·
RANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, AND OF ALL
OTHER OBLIGATIONS OR LIABILITIES ON THE SELLER'S PART, AND IT NEITHER ASSUMES NOR
AUTHORIZES ANY OTHER PERSON TO ASSUME FOR THE SELLER ANY OTHER LIABILITIES IN
CONNECTION WITH THE SALE OF THE SAID ARTICLES. This Warranty shall not apply to any of
such products which shall have been repaired or altered, except by the Seller, or which shall have
been subjected to misuse, negligence, or accident. The aforementioned provisions do not extend the
original warranty period of any product which has either been repaired or replaced by Seller.
It is understood that If this order calls for the delivery of semiconductor devices which are not
finished and fully encapsulated, that no warranty, statutory, expressed or Implied, Including the 1m·
plied warranty of merchantability and fitness for a particular purpose, shall apply. All such devices are
s.old as Is where Is.
9. PRODUCTS NOT WARRANTED BY SELLER: The second paragreph of Paragraph 6, Patents, and Par·
agraph B, Limited Warranty, above apply only to Integrated circuits of Selle~s own manufacture. IN
THE CASE OF PRODUCTS OTHER THAN INTEGRATED CIRCUITS OF SELLER'S OWN MANUFACTURE, SELLER MAKES NO WARRANTIES EXPRESSED, STATUTORY OR IMPLIED INCLUDING THE
IMPLIED WARRANTIES OF MERCHANTABILITY, FREEDOM FROM PATENT INFRINGEMENT AND
FITNESS FOR A PARTICULAR PURPOSE. Such products may be warranted by the original manufac·
turer of such products. For further Information regarding the possible warranty of such products con·
tact Seller.

10. PRICE ADJUSTMENTS: Selle~s unit prices are based on certain material costs. These materials Include, among other things, gold peckages and silicon. Adjustments shall be as follows:
(a) Gold. The price at the time of shipment shall be adjUsted for Increases In the cost of gold In
accordance with Selle~s current Gold Price Adjustment List. this adjustment will be shown as a
seperate line Item on each Invoice.
(b) Other Materials. In the event of significant Increases in other materials, Seller reserves the right
to renegotiate the unit prices. If the pertles cannot agree on such Increase, then neither party shall
have any further obligations with regard to the delivery or purchase of any units not then scheduled
for production.

11. VARIATION IN QUANTITY: 11th Is order calls for a product not listed In Selle~s current catalog, or for
a product which Is specially programmed for Buyer, It Is agreed that Seller may ship a quantity which
Is five percent (5%) more or less than the ordered quantity and that such quantity shipped will be
accepted and paid for in full satisfaction of each party's obligation hereunder for the quantity order.

12. CONSEQUENTIAL DAMAGES: In no event shall Seller be liable for special, Incidental or consequen·
tial damages.
13. GENERAL:
(a) The validity, performance and construction of these terms and all sales hereunder shall be
governed by the laws of the State of California
(b) The Seller represents that with respect to the production of articles andlor performance of the
services covered by this order it will fully comply with all requirements of the Fair Labor Standards Act
of 1938, as amended, Williams-Steiger Occupational Safety and Health Act of 1970, Executive Orders
11375 and 11246, Section 202 and 204.
(c) The Buyer may not unilaterally make changes In the drawings, designs or specifications for the
Items to be furnished hereunder without Selle~s prior consent.
(d) Except to the extent provided In Paragraph 14, below, this order Is not subject to cancellation or
termination for convenience.
(e) If Buyer Is In breach of Its obligations under this order, Buyer shall remain liable for all unpaid
charges and sums due to Seller and will reimburse Seller for all damages suffered or Incurred by
Seller as a result of Buyer's breach. The remedies provided herein shall be In addition to all other legal
means and remedies available to Seller.
(f) Buyer acknowledges that all or part of the products purchased hereunder may be manufactured
andlor assembled at any of Seller's facilities domestic or foreign.
(g) Unless otherwise agreed In a writing signed by both Buyer and Seller, Seller shall retain title to
and possession of all tOOling of any kind (Including but not limited to masks and pettern generator
tapes) used In the production of products fumlshed hereunder.
(h) Buyer, by accepting these products, certifies that he will not export or re-export the products
furnished hereunder unless he complies fully with all laws and regulations of the United States
relating to such export or re-export, Including but not limited to the Export Administration Act of 1979
and the Export Administration Regulations of the U.S. Department of Commerce.
(I) Seller shall own all copyrights In or relating to each product developed by Seller whether or not
such product is developed under contract with a third party.
Buye~s original purchase order Indicates by contract
number, that It Is placed under a government contract, only the following provisions of the current
Defense Acquisition Regulations are applicable In accordance with the terms thereof, with an appropriate substitution of parties, as the case may be • I.e., "Contracting Offlce~' shall mean "Buyer",
"Contracto~' shall mean "Selle~', and the term "Contract" shall mean this order.
7·103.1, Definitions; 7·103.3, Extras; 7·103.4, Variation In Quantity; 7·103.B, Assignment of Claims;
7·103.9, Additional Bond Security; 7·103.13, Renegotiation; 7·103.15, Rhodesia and Certain Commu·
nlst Areas; 7·103.16, Contract Work Hours and Safety Standards Act· Overtime Compensation;
7·103.17, Walsh·Healey Public Contracts Act; 7·103.1B, Equal Opportunity Clause; 7·103.19, Offl·
clals Not to Benefit; 7·103.20, Covenant Against Contingent Fees; 7·103.21, Termination for Convenlence of the Government (only to the extent that Buyer's contract Is terminated for the convenience of the government); 7·103.22, Authorization and Consent; 7·103.23, Notice and Assistance
Regarding Patent Infringement; 7·103.24, Responsibility for Inspection; 7·103.25, Commercial Bills
of lading Covering Shipments Undar FOB Origin Contracts; 7·103.27, Listing of Employment
Openings; 7'104.4, Notice to the Government of Labor Disputes; 7·104.11, Excess Profit; 7·104.15,
Examination of Records by Comptroller General; 7·104.20, Utilization of Labor Surplus Area Con·

14. GOVERNMENT CONTRACT PROVISIONS: If

cerns.

B.37

JANUARY 1984

Worldwide Sales Offices
United States
Northwest Region
HEADQUARTERS-3800 Homestead Road, Santa Clara, California 95051 ............................... (408) 246-0330
TWX: 910-338-0018
or 910-338-0024
CALIFORNIA, 2960 Gordon Avenue, Santa Clara 95051 ........................................... . (408) 738-4151
WASHINGTON, 20709 N.E. 232nd Avenue, Battle Ground 98604 .................................... . (206) 687-3101
WASHINGTON, 10655 N.E. 4th Street, Suite 400, Bellevue 98004 ................................... . (206) 462-8870

Southwest Region
CALIFORNIA, 2900 Bristol Street, Suite A-202, Costa Mesa 92626 .................................. .
CALIFORNIA, 2850 Pio Pi co Drive, Suite L, Carlsbad 92008 ........................................ .
ARIZONA, 7950 E. Redfield Road, Scottsdale 85260 .............................................. .

(714) 751-1634
(619) 434-6031
(602) 996-5638

Central Region
ILLINOIS,500 Higgins Road, Suite 210, Elk Grove Village 60007 .................................... .
MICHIGAN, 29200 Vassar Avenue, Suite 221, Livonia 48152 ........................................ .
COLORADO, 7346A So. Alton Way, Englewood 80112 ............................................ .

(312) 437-6496
(313) 478-4220
(303) 694-0629

Southeastern Region
FLORIDA, 139 Whooping Loop, Altamonte Springs 32701 ......................................... .
NORTH CAROLINA, 5711 Six Forks Road, Suite 210, Raleigh 27609 ................................. .
ALABAMA, 555 Sparkman Drive, Suite 822, Huntsville 35805 ...................................... .
TEXAS, 725 South Central Expressway, Suite A-9, Richardson 75080 ............................... .
TEXAS, Austin 78746 ....................................................................... .

(305)
(919)
(205)
(214)
(214)
(512)

830-8889
847-9468
830-1435
231-5721
231-5285
327-5286

(215)
(804)
(317)
(614)

643-0217
973-1213
773-6330
436-0330

Mid·Atlantic Area
PENNSYLVANIA, Axewood East, Butler & Skippack Pikes, Suite 230, Ambler 19002 ................... .
VIRGINIA, Northway Building, 500 Westfield Road, Suite 26, Charlottesville 22906 .................... .
INDIANA, 408 South 9th Street, Suite 201, Noblesville 46060 ...................................... .
OHIO, 100 East Wilson Bridge Road, Suite 225, Worthington 43085 ................................. .

Northeastern Region
NEW YORK, 20F Robert Pitt Drive, Suite 208, Monsey 10952 ....................................... .
MASSACHUSETTS,24 Muzzey Street, Lexington 02173 ........................................... .

(914) 352-5333
(617) 861-6530

Europe
HEADQUARTERS-Austria Microsystems International GmbH, Schloss Premstatten
8141 Unterpremstatten, Austria .............................................................. .

(43)3136/3666

Sales Offices
ENGLAND, AMI Microsystems, Ltd., Princes House, Princes St., Swindon SN1 2HU ...................
FRANCE, AMI Microsystems, S.A.R.L., 124 Avenue de Paris, 94300 Vincennes ........................
WEST GERMANY, AMI Microsystems GmbH, Suite 237, Rosenheimer Strasse 30/32, 8000 Munich 80 .....
ITALY, AMI Microsystems S.R.L., Piazzale Lugano, 9, 20158 Milano ................................

.
.
.
,

(0793) 37852
(01) 374 00 90
(089) 483081
(02) 3761275
or 3763022

Japan and Pacific Basin
JAPAN, Asahi Microsystems, Inc., 17F, Imperial Tower, 1-1-1, Uchisaiwai-Cho, Chiyoda-Ku, Tokyo 100

8.39

(81) 3-507-2371

Domestic Representatives
CANADA, Burnaby B.C.. . . . . . . . . . . . . . . . . . . . . . . . ..
CANADA, Mississauga, Ontario. . . . . . . . . . . . . . . . ..
CANADA, Ottowa, Ontario. . . . . . . . . . . . . . . . . . . . . ..
CANADA, St. Laurent, Quebec. . . . . . . . . . . . . . . . . . ..
CANADA, Stittsville, Ontario. . . . . . . . . . . . . .. . . . . ..
IOWA, Cedar Rapids ............................
MASSACHUSETTS, Tyngsboro. . . . . . . . . . . . . . . . . . ..
MINNESOTA, Minneapolis. . . . . . . . . . . . . . . . . . . . . ..
NEW YORK, Clinton. . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PUERTO RICO, San Juan. . . . . . . . . . . . . . . . . . . . . . . ..

Woodbery Elect. Sales Ltd ................... .
Vitel Electronics .......................... .
Vitel Electronics .......................... .
Vitel Electronics .......................... .
Vitel Electronics .......................... .
Comstrand, Inc............................ .
Comptech ................................ .
Comstrand, Inc............................ .
Advanced Components ..................... .
Electronic Tech. Sales, Inc.................. .

B.41

(604)
(416)
(613)
(514)
(613)
(319)
(617)
(612)
(315)
(809)

430·3302
676·9720
592·0090
331·7393
582·0090
377·1575
649·3030
788·9234
853·6438
790·4300

Domestic Distributors
ALABAMA, Huntsville. . . . . . . . . . . . . . . . . . . . . . . . . ..
ARIZONA, Phoenix ............................
ARIZONA, Scottsdale. . . . . . . . . . . . . . . . . . . . . . . . . ..
ARIZONA, Tempe. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ARIZONA, Tucson .............................
CALIFORNIA, Canoga Park ......................
CALIFORNIA, Chatsworth .......................
CALIFORNIA, Cupertino ........................
CALIFORNIA, Irvine ............................
CALIFORNIA, Los Angeles ......................
CALIFORNIA, Palo Alto .........................
CALIFORNIA, Sacramento.......................
CALIFORNIA, San Diego ........................
CALIFORNIA, San Diego ........................
CALIFORNIA, San Jose .........................
CALIFORNIA, Santa Clara .......................
CALIFORNIA, Tustin ...........................
CALIFORNIA, Tustin ...........................
CANADA, Alberta, Calgary ......................
CANADA, British Columbia, Vancouver ...........
CANADA, Ontario, Downsview ...................
CANADA, Ontario, Downsview ...................
CANADA, Ottawa ..............................
CANADA, Quebec, Montreal ....................
CANADA, Quebec, Point Claire ..................
CANADA, Quebec .............................
COLORADO, Englewood. . . . . . . . . . . . . . . . . . . . . . . ..
COLORADO, Englewood. . . . . . . . . . . . . . . . . . . . . . . ..
CONNECTICUT, Danbury .......................
CONNECTICUT, Wallingford .....................
FLORIDA, Altamonte Springs ....................
FLORIDA, Ft. Lauderdale .......................
FLORIDA, Hollywood ..........................
FLORIDA, St. Petersburg .......................
GEORGIA, Norcross ...........................
GEORGIA, Norcross ...........................
ILLINOIS, Elk Grove Village .....................
ILLINOIS, Elk Grove Village .....................
IOWA, Cedar Rapids ...........................
KANSAS, Overland Park ........................
MARYLAND, Baltimore ..........................
MARYLAND, Gaithersburg ......................
MASSACHUSETTS, Bedford .....................
MASSACHUSETTS, Billerica .....................
MICHIGAN, Livonia ............................
MINNESOTA, Eden Prairie ......................
MINNESOTA, Edina ............................
MISSOURI, Earth City. . . . . . . . . . . . . . . . . . . . . . . . . ..
MISSOURI, Maryland Heights ....................
NEW HAMPSHIRE, Manchester. . . . . . . . . . . . . . . . . ..
NEW JERSEY, Fairfield .........................
NEW JERSEY, Fairfield .........................
NEW YORK, Rochester .........................
NEW YORK, Westbury L.I. .......................
NORTH CAROLINA, Raleigh .....................
NORTH CAROLINA, Raleigh .....................

Schweber Electronics ...................... .
Kierulff Electronics ....................... .
Western Microtechnology .................. .
Anthem Electronics ....................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Anthem Electronics ...................... .
Western Microtechnology ................. .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Kierulff Electronics ....................... .
Schweber Electronics ...................... .
Anthem Electronics ...................... .
Kierulff Electronics ....................... .
Anthem Electronics ...................... .
Schweber Electronics ..................... .
Anthem Electronics ...................... .
Kierulff Electronics ....................... .
Future Electronics ........................ .
Future Electronics, Inc. . .................. .
Cesco Electronics, Ltd. . ................... .
Future Electronics, Inc.................... .
Future Electronics, Inc.................... .
Cesco Electronics, Ltd ..................... .
Future Electronics, Inc. . .................. .
Cesco Electronics, Ltd. . ................... .
Anthem Electronics ....................... .
Kierulff Electronics ........................ .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Schweber Electronics ..................... .
Schweber Electronics ..................... .
Kierulff Electronics ........................ .
Schweber Electronics ..................... .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Scheweber ............................... .
Kierulff Electronics ....................... .
Schweber Electronics ...................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Schweber Electronics ..................... .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .

8.43

(205)
(602)
(602)
(602)
(602)
(213)
(213)
(408)
(714)
(213)
(415)
(916)
(619)
(619)
(408)
(408)
(714)
(714)
(403)
(604)
(416)
(416)
(613)
(514)
(514)
(418)
(303)
(303)
(203)
(203)
(305)
(305)
(305)
(813)
(404)
(404)
(312)
(312)
(319)
(913)
(301)
(301)
(617)
(617)
(313)
(612)
(612)
(314)
(314)
(603)
(201)
(201)
(716)
(516)
(919)
(919)

882·2200
243·4101
948·4240
244·0900
624·9986
999·4702
700·1000
725·1660
863·0220
725·0325
968·6292
929·9732
453·4871
278·2112
946·8000
748·4700
730·8000
731·5711
259·6408
438·5545
661·0220
663·5563
820·8313
735·5511
694·7710
687·4231
790·4500
790·4444
792·3742
265·1115
331·7555
486·4004
927·0511
576·1966
447·5252
449·9170
640·0200
364·3750
373·1417
492·2921
247·5020
840·5900
275·5100
935·5134
525·8100
941·5280
941·7500
739·0526
739·0855
625·2250
575·6750
227·7880
424·2222
334-7474
872-8410
867-0000

Domestic Distributors
OHIO, Beachwood .............................
OHIO, Cleveland ..............................
OHIO, Dayton. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
OKLAHOMA, Tulsa ............................
OKLAHOMA, Tulsa .............................
OREGON, Portland ............................
PENNSYLVANIA, Horsham ......................
PENNSYLVANIA, Pittsburgh. . . . . . . . . . . . . . . . . . . . ..
TEXAS, Austin ................................
TEXAS, Austin ................................
TEXAS, Dallas ................................
TEXAS, Dallas ................................
TEXAS, Houston ..............................
TEXAS, Houston ..............................
UTAH, Salt Lake City ...........................
WASHINGTON, Redmond. . . . . . . . . . . . . . . . . . . . . . ..
WASHINGTON, Tukwila ........................
WISCONSIN, Brookfield.........................
WISCONSIN, Waukesha ........................

Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Schweber Electron ics ...................... .
Kierulff Electronics ....................... .
Schweber Electronics ...................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Schweber Electronics ...................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Schweber Electronics ..................... .
Kierulff Electronics ....................... .
Anthem Electronics ....................... .
Kierulff Electronics ....................... .
Schweber Electronics ...................... .
Kierulff Electronics ....................... .

B.45

(216)
(216)
(513)
(918)
(918)
(503)
(215)
(412)
(512)
(512)
(214)
(214)
(713)
(713)
(801)
(206)
(206)
(414)
(414)

464-2970
587-6558
439-1800
252-7537
622-8000
641-9150
441-0600
782-1600
835-2090
458-8253
343-2400
661-5010
530-7030
784-3600
973-6913
881-0850
575-4420
784-9020
784-8160

International Representatives & Distributors
ARGENTINA, Buenos Aires ......................
AUSTRALIA, Preston, Victoria ...................
BRAZIL, Sao Paulo .............................
CHILE .......................................
DENMARK, ...................................
ENGLAND, Derby ..............................
ENGLAND, Harlow, Essex .......................
FINLAND, Espoo ..............................
FRANCE, Sevres ..............................
HONG KONG, Kowloon .........................
INDIA, Nagar, Punjab ..........................
ISRAEL, Tel Aviv ..............................
ITALY .......................................
JAPAN, Tokyo ................................
MEXICO .....................................
NETHERLANDS, Badhoevedere ..................
NETHERLANDS, Rotterdam .....................
NEW ZEALAND, Auckland .......................
NORWAY, Oslo ...............................
SINGAPORE, Singapore ........................
SOUTH AFRICA, Transvaal ......................
SOUTH KOREA, Seoul ..........................
SPAIN, Madrid ................................
SWEDEN, Spanga .............................
SWITZERLAND, Zurich .........................
TAIWAN, Taipai ...............................
WEST GERMANY, Berlin ........................
WEST GERMANY, Frankenthal ...................
WEST GERMANY, Munich .......................
WEST GERMANY, Schleswig ....................
WEST GERMANY, Stuttgart .....................
WEST GERMANY, Viersen .......................
YUGOSLAVIA, Ljubljana ........................

YEL S.R.L. ............................... .
Rifa Pty. Ltd. . ............................ .
Datatronix Electronica Ltda................ .
Victronics Ltda. . ......................... .
Semicap A/S ............................. .
Quarndon Electronics Ltd. . ................ .
VSI Electronics (UK) Ltd .................... .
OY Atomica AB .......................... .
Tekelec Airtronic ......................... .
Electrocon Products Ltd. . ................. .
Semiconductor Complex Ltd. . ............. .
Professional Elect. Ltd.(P.E.L.) .............. .
International Commerce Co ................ .
Intern ix, Inc .............................. .
Dicopel S.A. . ............................ .
Techmation Elec. NV ...................... .
DMA Nederland, BV ....................... .
David P. Reid (NZ) Ltd ...................... .
Rifa-Hoyem A/S .......................... .
Dynamar Int'l. Ltd ......................... .
Promilect ............................... .
Kortronics Enterprise ..................... .
Actron .................................. .
A.B. Rifa ................................ .
W. Moor AG ............................. .
Promotor Co., Ltd ......................... .
Aktiv Elektronik GmbH .................... .
Gleichman .............................. .
Dema Electronic GmbH ................... .
Ing. Bruo Dreyer .......................... .
Ditronic GmbH ........................... .
Mostron Halbieitervertriebs ................ .
ISKRA/Standard/Iskra IEZE ................ .

B.47

(54) 1-46 2211
61 (3) 480 1211
11-826-0111
56(2)36440-30237
(01) 22150
(0332) 32651
(0279) 2935477
(80) 423533
(01) 534-75-35
3- 687214-6
91 (172) 87495
410656
(81) 3-369-1101
(903) 561-3211
(04189) 2222
010-361288
(9) 488049
47-413755
(65) 746 6188
(011) 485712
2634-5497
(00341) 4026085
(08) 7522500
(01) 8406644
(02) 767-0101
(030) 6845088
(89) 28 8018
(04621) 24055
0711/724844
(0216) 17024
(051) 551-353

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1984_AMI_MOS_Products_Catalog_2ed 1984 AMI MOS Products Catalog 2ed

1984_AMI_MOS_Products_Catalog_2ed 1984_AMI_MOS_Products_Catalog_2ed

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